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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.md b/README.md new file mode 100644 index 0000000..f11608b --- /dev/null +++ b/README.md @@ -0,0 +1,5 @@ +# Xilinx Unisim Library + +The Xilinx Unisim Library Verilog available as open source under Apache 2.0. + +These files coincide with the 2020.1 release of Vivado. diff --git a/verilog/src/unisims/AND2B1L.v b/verilog/src/unisims/AND2B1L.v new file mode 100644 index 0000000..a60e87e --- /dev/null +++ b/verilog/src/unisims/AND2B1L.v @@ -0,0 +1,97 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Two input AND gate implemented in place of a CLB Latch +// /___/ /\ Filename : AND2B1L.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 04/01/08 - Initial version. +// 04/14/09 - 517897 - Invert SRI not DI +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 04/16/13 - 683925 - add invertible pin support. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module AND2B1L #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [0:0] IS_SRI_INVERTED = 1'b0 +)( + output O, + + input DI, + input SRI +); + +// define constants + localparam MODULE_NAME = "AND2B1L"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "AND2B1L_dr.v" +`else + reg [0:0] IS_SRI_INVERTED_REG = IS_SRI_INVERTED; +`endif + +`ifdef XIL_XECLIB + tri0 glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire DI_in; + wire SRI_in; + + assign DI_in = DI; + assign SRI_in = SRI ^ IS_SRI_INVERTED_REG; + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + assign O = ~glblGSR && DI_in && ~SRI_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (DI => O) = (0:0:0, 0:0:0); + (SRI => O) = (0:0:0, 0:0:0); + $width (negedge SRI, 0:0:0, 0, notifier); + $width (posedge SRI, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/AUTOBUF.v b/verilog/src/unisims/AUTOBUF.v new file mode 100644 index 0000000..c2f66b1 --- /dev/null +++ b/verilog/src/unisims/AUTOBUF.v @@ -0,0 +1,90 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Clock Buffer +// /___/ /\ Filename : AUTOBUF.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module AUTOBUF (O, I); + + parameter BUFFER_TYPE = "AUTO"; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + + input I; + + initial begin + + case (BUFFER_TYPE) + "AUTO" : ; + "BUF" : ; + "BUFG" : ; + "BUFGP" : ; + "BUFH" : ; + "BUFIO" : ; + "BUFIO2" : ; + "BUFIO2FB" : ; + "BUFR" : ; + "IBUF" : ; + "IBUFG" : ; + "NONE" : ; + "OBUF" : ; + default : begin + $display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE); + end + endcase + + end + + buf B1 (O, I); + +`ifdef XIL_TIMING + + specify + + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/BIBUF.v b/verilog/src/unisims/BIBUF.v new file mode 100644 index 0000000..7c24f3d --- /dev/null +++ b/verilog/src/unisims/BIBUF.v @@ -0,0 +1,67 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Bi-Directional IO +// /___/ /\ Filename : BIBUF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BIBUF +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + inout IO, + inout PAD +); + +// define constants + localparam MODULE_NAME = "BIBUF"; + + tri0 glblGSR = glbl.GSR; + +// begin behavioral model + + wire PAD_io; + wire IO_io; + + assign #10 PAD_io = PAD; + assign #10 IO_io = IO; + + assign (weak1, weak0) IO = PAD_io; + assign (weak1, weak0) PAD = IO_io; + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BITSLICE_CONTROL.v b/verilog/src/unisims/BITSLICE_CONTROL.v new file mode 100644 index 0000000..d20481d --- /dev/null +++ b/verilog/src/unisims/BITSLICE_CONTROL.v @@ -0,0 +1,1013 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / BITSLICE_CONTROL +// /___/ /\ Filename : BITSLICE_CONTROL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BITSLICE_CONTROL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CTRL_CLK = "EXTERNAL", + parameter DIV_MODE = "DIV2", + parameter EN_CLK_TO_EXT_NORTH = "DISABLE", + parameter EN_CLK_TO_EXT_SOUTH = "DISABLE", + parameter EN_DYN_ODLY_MODE = "FALSE", + parameter EN_OTHER_NCLK = "FALSE", + parameter EN_OTHER_PCLK = "FALSE", + parameter IDLY_VT_TRACK = "TRUE", + parameter INV_RXCLK = "FALSE", + parameter ODLY_VT_TRACK = "TRUE", + parameter QDLY_VT_TRACK = "TRUE", + parameter [5:0] READ_IDLE_COUNT = 6'h00, + parameter REFCLK_SRC = "PLLCLK", + parameter integer ROUNDING_FACTOR = 16, + parameter RXGATE_EXTEND = "FALSE", + parameter RX_CLK_PHASE_N = "SHIFT_0", + parameter RX_CLK_PHASE_P = "SHIFT_0", + parameter RX_GATING = "DISABLE", + parameter SELF_CALIBRATE = "ENABLE", + parameter SERIAL_MODE = "FALSE", + parameter SIM_DEVICE = "ULTRASCALE", + parameter SIM_SPEEDUP = "FAST", + parameter real SIM_VERSION = 2.0, + parameter TX_GATING = "DISABLE" +)( + output CLK_TO_EXT_NORTH, + output CLK_TO_EXT_SOUTH, + output DLY_RDY, + output [6:0] DYN_DCI, + output NCLK_NIBBLE_OUT, + output PCLK_NIBBLE_OUT, + output [15:0] RIU_RD_DATA, + output RIU_VALID, + output [39:0] RX_BIT_CTRL_OUT0, + output [39:0] RX_BIT_CTRL_OUT1, + output [39:0] RX_BIT_CTRL_OUT2, + output [39:0] RX_BIT_CTRL_OUT3, + output [39:0] RX_BIT_CTRL_OUT4, + output [39:0] RX_BIT_CTRL_OUT5, + output [39:0] RX_BIT_CTRL_OUT6, + output [39:0] TX_BIT_CTRL_OUT0, + output [39:0] TX_BIT_CTRL_OUT1, + output [39:0] TX_BIT_CTRL_OUT2, + output [39:0] TX_BIT_CTRL_OUT3, + output [39:0] TX_BIT_CTRL_OUT4, + output [39:0] TX_BIT_CTRL_OUT5, + output [39:0] TX_BIT_CTRL_OUT6, + output [39:0] TX_BIT_CTRL_OUT_TRI, + output VTC_RDY, + + input CLK_FROM_EXT, + input EN_VTC, + input NCLK_NIBBLE_IN, + input PCLK_NIBBLE_IN, + input [3:0] PHY_RDCS0, + input [3:0] PHY_RDCS1, + input [3:0] PHY_RDEN, + input [3:0] PHY_WRCS0, + input [3:0] PHY_WRCS1, + input PLL_CLK, + input REFCLK, + input [5:0] RIU_ADDR, + input RIU_CLK, + input RIU_NIBBLE_SEL, + input [15:0] RIU_WR_DATA, + input RIU_WR_EN, + input RST, + input [39:0] RX_BIT_CTRL_IN0, + input [39:0] RX_BIT_CTRL_IN1, + input [39:0] RX_BIT_CTRL_IN2, + input [39:0] RX_BIT_CTRL_IN3, + input [39:0] RX_BIT_CTRL_IN4, + input [39:0] RX_BIT_CTRL_IN5, + input [39:0] RX_BIT_CTRL_IN6, + input [3:0] TBYTE_IN, + input [39:0] TX_BIT_CTRL_IN0, + input [39:0] TX_BIT_CTRL_IN1, + input [39:0] TX_BIT_CTRL_IN2, + input [39:0] TX_BIT_CTRL_IN3, + input [39:0] TX_BIT_CTRL_IN4, + input [39:0] TX_BIT_CTRL_IN5, + input [39:0] TX_BIT_CTRL_IN6, + input [39:0] TX_BIT_CTRL_IN_TRI +); + +// define constants + localparam MODULE_NAME = "BITSLICE_CONTROL"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BITSLICE_CONTROL_dr.v" +`else + localparam [64:1] CTRL_CLK_REG = CTRL_CLK; + localparam [32:1] DIV_MODE_REG = DIV_MODE; + localparam [56:1] EN_CLK_TO_EXT_NORTH_REG = EN_CLK_TO_EXT_NORTH; + localparam [56:1] EN_CLK_TO_EXT_SOUTH_REG = EN_CLK_TO_EXT_SOUTH; + localparam [40:1] EN_DYN_ODLY_MODE_REG = EN_DYN_ODLY_MODE; + localparam [40:1] EN_OTHER_NCLK_REG = EN_OTHER_NCLK; + localparam [40:1] EN_OTHER_PCLK_REG = EN_OTHER_PCLK; + localparam [40:1] IDLY_VT_TRACK_REG = IDLY_VT_TRACK; + localparam [40:1] INV_RXCLK_REG = INV_RXCLK; + localparam [40:1] ODLY_VT_TRACK_REG = ODLY_VT_TRACK; + localparam [40:1] QDLY_VT_TRACK_REG = QDLY_VT_TRACK; + localparam [5:0] READ_IDLE_COUNT_REG = READ_IDLE_COUNT; + localparam [48:1] REFCLK_SRC_REG = REFCLK_SRC; + localparam [7:0] ROUNDING_FACTOR_REG = ROUNDING_FACTOR; + localparam [40:1] RXGATE_EXTEND_REG = RXGATE_EXTEND; + localparam [64:1] RX_CLK_PHASE_N_REG = RX_CLK_PHASE_N; + localparam [64:1] RX_CLK_PHASE_P_REG = RX_CLK_PHASE_P; + localparam [56:1] RX_GATING_REG = RX_GATING; + localparam [56:1] SELF_CALIBRATE_REG = SELF_CALIBRATE; + localparam [40:1] SERIAL_MODE_REG = SERIAL_MODE; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [32:1] SIM_SPEEDUP_REG = SIM_SPEEDUP; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [56:1] TX_GATING_REG = TX_GATING; +`endif + + localparam [40:1] BISC_MULTI_FREQ_EN_REG = "TRUE"; + localparam [56:1] CONTROL_DLY_TEST_EN_REG = "DISABLE"; + localparam [40:1] DC_ADJ_EN_REG = "FALSE"; + localparam [12:0] DLY_RNK0_REG = 13'h0000; + localparam [12:0] DLY_RNK1_REG = 13'h0000; + localparam [12:0] DLY_RNK2_REG = 13'h0000; + localparam [12:0] DLY_RNK3_REG = 13'h0000; + localparam [2:0] FDLY_REG = 3'b010; + localparam [7:0] INCDEC_CRSE_REG = 8'h08; + localparam [40:1] MASK_FIXDLY_REG = "FALSE"; + localparam [9:0] MON_REG = 10'h000; + localparam [8:0] NQTR_REG = 9'h000; + localparam [8:0] PQTR_REG = 9'h000; + localparam [40:1] RIU_RL_ARBITRATION_FIX_EN_REG = "TRUE"; + localparam [1:0] SPARE_REG = 2'b00; + + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CLK_TO_EXT_NORTH_out; + wire CLK_TO_EXT_SOUTH_out; + wire DLY_RDY_out; + wire DLY_TEST_OUT_out; + wire LOCAL_DIV_CLK_out; + wire MASTER_PD_OUT_out; + wire NCLK_NIBBLE_OUT_out; + wire PCLK_NIBBLE_OUT_out; + wire PLL_CLK_EN_out; + wire REFCLK_DFD_out; + wire RIU_VALID_out; + wire VTC_RDY_out; + wire [15:0] RIU_RD_DATA_out; + wire [39:0] RX_BIT_CTRL_OUT0_out; + wire [39:0] RX_BIT_CTRL_OUT1_out; + wire [39:0] RX_BIT_CTRL_OUT2_out; + wire [39:0] RX_BIT_CTRL_OUT3_out; + wire [39:0] RX_BIT_CTRL_OUT4_out; + wire [39:0] RX_BIT_CTRL_OUT5_out; + wire [39:0] RX_BIT_CTRL_OUT6_out; + wire [39:0] TX_BIT_CTRL_OUT0_out; + wire [39:0] TX_BIT_CTRL_OUT1_out; + wire [39:0] TX_BIT_CTRL_OUT2_out; + wire [39:0] TX_BIT_CTRL_OUT3_out; + wire [39:0] TX_BIT_CTRL_OUT4_out; + wire [39:0] TX_BIT_CTRL_OUT5_out; + wire [39:0] TX_BIT_CTRL_OUT6_out; + wire [39:0] TX_BIT_CTRL_OUT_TRI_out; + wire [6:0] DYN_DCI_out; + + wire CLK_TO_EXT_NORTH_delay; + wire CLK_TO_EXT_SOUTH_delay; + wire DLY_RDY_delay; + wire NCLK_NIBBLE_OUT_delay; + wire PCLK_NIBBLE_OUT_delay; + wire RIU_VALID_delay; + wire VTC_RDY_delay; + wire [15:0] RIU_RD_DATA_delay; + wire [39:0] RX_BIT_CTRL_OUT0_delay; + wire [39:0] RX_BIT_CTRL_OUT1_delay; + wire [39:0] RX_BIT_CTRL_OUT2_delay; + wire [39:0] RX_BIT_CTRL_OUT3_delay; + wire [39:0] RX_BIT_CTRL_OUT4_delay; + wire [39:0] RX_BIT_CTRL_OUT5_delay; + wire [39:0] RX_BIT_CTRL_OUT6_delay; + wire [39:0] TX_BIT_CTRL_OUT0_delay; + wire [39:0] TX_BIT_CTRL_OUT1_delay; + wire [39:0] TX_BIT_CTRL_OUT2_delay; + wire [39:0] TX_BIT_CTRL_OUT3_delay; + wire [39:0] TX_BIT_CTRL_OUT4_delay; + wire [39:0] TX_BIT_CTRL_OUT5_delay; + wire [39:0] TX_BIT_CTRL_OUT6_delay; + wire [39:0] TX_BIT_CTRL_OUT_TRI_delay; + wire [6:0] DYN_DCI_delay; + + wire CLK_FROM_EXT_in; + wire CLK_STOP_in; + wire DLY_TEST_IN_in; + wire EN_VTC_in; + wire NCLK_NIBBLE_IN_in; + wire PCLK_NIBBLE_IN_in; + wire PLL_CLK_in; + wire REFCLK_in; + wire RIU_CLK_in; + wire RIU_NIBBLE_SEL_in; + wire RIU_WR_EN_in; + wire RST_in; + wire SCAN_INT_in; + wire [15:0] RIU_WR_DATA_in; + wire [39:0] RX_BIT_CTRL_IN0_in; + wire [39:0] RX_BIT_CTRL_IN1_in; + wire [39:0] RX_BIT_CTRL_IN2_in; + wire [39:0] RX_BIT_CTRL_IN3_in; + wire [39:0] RX_BIT_CTRL_IN4_in; + wire [39:0] RX_BIT_CTRL_IN5_in; + wire [39:0] RX_BIT_CTRL_IN6_in; + wire [39:0] TX_BIT_CTRL_IN0_in; + wire [39:0] TX_BIT_CTRL_IN1_in; + wire [39:0] TX_BIT_CTRL_IN2_in; + wire [39:0] TX_BIT_CTRL_IN3_in; + wire [39:0] TX_BIT_CTRL_IN4_in; + wire [39:0] TX_BIT_CTRL_IN5_in; + wire [39:0] TX_BIT_CTRL_IN6_in; + wire [39:0] TX_BIT_CTRL_IN_TRI_in; + wire [3:0] PHY_RDCS0_in; + wire [3:0] PHY_RDCS1_in; + wire [3:0] PHY_RDEN_in; + wire [3:0] PHY_WRCS0_in; + wire [3:0] PHY_WRCS1_in; + wire [3:0] TBYTE_IN_in; + wire [5:0] RIU_ADDR_in; + + wire CLK_FROM_EXT_delay; + wire EN_VTC_delay; + wire NCLK_NIBBLE_IN_delay; + wire PCLK_NIBBLE_IN_delay; + wire PLL_CLK_delay; + wire REFCLK_delay; + wire RIU_CLK_delay; + wire RIU_NIBBLE_SEL_delay; + wire RIU_WR_EN_delay; + wire RST_delay; + wire [15:0] RIU_WR_DATA_delay; + wire [39:0] RX_BIT_CTRL_IN0_delay; + wire [39:0] RX_BIT_CTRL_IN1_delay; + wire [39:0] RX_BIT_CTRL_IN2_delay; + wire [39:0] RX_BIT_CTRL_IN3_delay; + wire [39:0] RX_BIT_CTRL_IN4_delay; + wire [39:0] RX_BIT_CTRL_IN5_delay; + wire [39:0] RX_BIT_CTRL_IN6_delay; + wire [39:0] TX_BIT_CTRL_IN0_delay; + wire [39:0] TX_BIT_CTRL_IN1_delay; + wire [39:0] TX_BIT_CTRL_IN2_delay; + wire [39:0] TX_BIT_CTRL_IN3_delay; + wire [39:0] TX_BIT_CTRL_IN4_delay; + wire [39:0] TX_BIT_CTRL_IN5_delay; + wire [39:0] TX_BIT_CTRL_IN6_delay; + wire [39:0] TX_BIT_CTRL_IN_TRI_delay; + wire [3:0] PHY_RDCS0_delay; + wire [3:0] PHY_RDCS1_delay; + wire [3:0] PHY_RDEN_delay; + wire [3:0] PHY_WRCS0_delay; + wire [3:0] PHY_WRCS1_delay; + wire [3:0] TBYTE_IN_delay; + wire [5:0] RIU_ADDR_delay; + + assign #(out_delay) CLK_TO_EXT_NORTH = CLK_TO_EXT_NORTH_delay; + assign #(out_delay) CLK_TO_EXT_SOUTH = CLK_TO_EXT_SOUTH_delay; + assign #(out_delay) DLY_RDY = DLY_RDY_delay; + assign #(out_delay) DYN_DCI = DYN_DCI_delay; + assign #(out_delay) NCLK_NIBBLE_OUT = NCLK_NIBBLE_OUT_delay; + assign #(out_delay) PCLK_NIBBLE_OUT = PCLK_NIBBLE_OUT_delay; + assign #(out_delay) RIU_RD_DATA = RIU_RD_DATA_delay; + assign #(out_delay) RIU_VALID = RIU_VALID_delay; + assign #(out_delay) RX_BIT_CTRL_OUT0 = RX_BIT_CTRL_OUT0_delay; + assign #(out_delay) RX_BIT_CTRL_OUT1 = RX_BIT_CTRL_OUT1_delay; + assign #(out_delay) RX_BIT_CTRL_OUT2 = RX_BIT_CTRL_OUT2_delay; + assign #(out_delay) RX_BIT_CTRL_OUT3 = RX_BIT_CTRL_OUT3_delay; + assign #(out_delay) RX_BIT_CTRL_OUT4 = RX_BIT_CTRL_OUT4_delay; + assign #(out_delay) RX_BIT_CTRL_OUT5 = RX_BIT_CTRL_OUT5_delay; + assign #(out_delay) RX_BIT_CTRL_OUT6 = RX_BIT_CTRL_OUT6_delay; + assign #(out_delay) TX_BIT_CTRL_OUT0 = TX_BIT_CTRL_OUT0_delay; + assign #(out_delay) TX_BIT_CTRL_OUT1 = TX_BIT_CTRL_OUT1_delay; + assign #(out_delay) TX_BIT_CTRL_OUT2 = TX_BIT_CTRL_OUT2_delay; + assign #(out_delay) TX_BIT_CTRL_OUT3 = TX_BIT_CTRL_OUT3_delay; + assign #(out_delay) TX_BIT_CTRL_OUT4 = TX_BIT_CTRL_OUT4_delay; + assign #(out_delay) TX_BIT_CTRL_OUT5 = TX_BIT_CTRL_OUT5_delay; + assign #(out_delay) TX_BIT_CTRL_OUT6 = TX_BIT_CTRL_OUT6_delay; + assign #(out_delay) TX_BIT_CTRL_OUT_TRI = TX_BIT_CTRL_OUT_TRI_delay; + assign #(out_delay) VTC_RDY = VTC_RDY_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) PHY_RDCS0_delay = PHY_RDCS0; + assign #(in_delay) PHY_RDCS1_delay = PHY_RDCS1; + assign #(in_delay) PHY_RDEN_delay = PHY_RDEN; + assign #(in_delay) PHY_WRCS0_delay = PHY_WRCS0; + assign #(in_delay) PHY_WRCS1_delay = PHY_WRCS1; + assign #(inclk_delay) PLL_CLK_delay = PLL_CLK; + assign #(inclk_delay) REFCLK_delay = REFCLK; + assign #(in_delay) RIU_ADDR_delay = RIU_ADDR; + assign #(inclk_delay) RIU_CLK_delay = RIU_CLK; + assign #(in_delay) RIU_NIBBLE_SEL_delay = RIU_NIBBLE_SEL; + assign #(in_delay) RIU_WR_DATA_delay = RIU_WR_DATA; + assign #(in_delay) RIU_WR_EN_delay = RIU_WR_EN; + assign #(in_delay) RST_delay = RST; + assign #(in_delay) TBYTE_IN_delay = TBYTE_IN; + +`endif + +// inputs with no timing checks + + assign #(in_delay) CLK_FROM_EXT_delay = CLK_FROM_EXT; + assign #(in_delay) NCLK_NIBBLE_IN_delay = NCLK_NIBBLE_IN; + assign #(in_delay) PCLK_NIBBLE_IN_delay = PCLK_NIBBLE_IN; + assign #(in_delay) RX_BIT_CTRL_IN0_delay = RX_BIT_CTRL_IN0; + assign #(in_delay) RX_BIT_CTRL_IN1_delay = RX_BIT_CTRL_IN1; + assign #(in_delay) RX_BIT_CTRL_IN2_delay = RX_BIT_CTRL_IN2; + assign #(in_delay) RX_BIT_CTRL_IN3_delay = RX_BIT_CTRL_IN3; + assign #(in_delay) RX_BIT_CTRL_IN4_delay = RX_BIT_CTRL_IN4; + assign #(in_delay) RX_BIT_CTRL_IN5_delay = RX_BIT_CTRL_IN5; + assign #(in_delay) RX_BIT_CTRL_IN6_delay = RX_BIT_CTRL_IN6; + assign #(in_delay) TX_BIT_CTRL_IN0_delay = TX_BIT_CTRL_IN0; + assign #(in_delay) TX_BIT_CTRL_IN1_delay = TX_BIT_CTRL_IN1; + assign #(in_delay) TX_BIT_CTRL_IN2_delay = TX_BIT_CTRL_IN2; + assign #(in_delay) TX_BIT_CTRL_IN3_delay = TX_BIT_CTRL_IN3; + assign #(in_delay) TX_BIT_CTRL_IN4_delay = TX_BIT_CTRL_IN4; + assign #(in_delay) TX_BIT_CTRL_IN5_delay = TX_BIT_CTRL_IN5; + assign #(in_delay) TX_BIT_CTRL_IN6_delay = TX_BIT_CTRL_IN6; + assign #(in_delay) TX_BIT_CTRL_IN_TRI_delay = TX_BIT_CTRL_IN_TRI; + + assign CLK_TO_EXT_NORTH_delay = CLK_TO_EXT_NORTH_out; + assign CLK_TO_EXT_SOUTH_delay = CLK_TO_EXT_SOUTH_out; + assign DLY_RDY_delay = DLY_RDY_out; + assign DYN_DCI_delay = DYN_DCI_out; + assign NCLK_NIBBLE_OUT_delay = NCLK_NIBBLE_OUT_out; + assign PCLK_NIBBLE_OUT_delay = PCLK_NIBBLE_OUT_out; + assign RIU_RD_DATA_delay = RIU_RD_DATA_out; + assign RIU_VALID_delay = RIU_VALID_out; + assign RX_BIT_CTRL_OUT0_delay = RX_BIT_CTRL_OUT0_out; + assign RX_BIT_CTRL_OUT1_delay = RX_BIT_CTRL_OUT1_out; + assign RX_BIT_CTRL_OUT2_delay = RX_BIT_CTRL_OUT2_out; + assign RX_BIT_CTRL_OUT3_delay = RX_BIT_CTRL_OUT3_out; + assign RX_BIT_CTRL_OUT4_delay = RX_BIT_CTRL_OUT4_out; + assign RX_BIT_CTRL_OUT5_delay = RX_BIT_CTRL_OUT5_out; + assign RX_BIT_CTRL_OUT6_delay = RX_BIT_CTRL_OUT6_out; + assign TX_BIT_CTRL_OUT0_delay = TX_BIT_CTRL_OUT0_out; + assign TX_BIT_CTRL_OUT1_delay = TX_BIT_CTRL_OUT1_out; + assign TX_BIT_CTRL_OUT2_delay = TX_BIT_CTRL_OUT2_out; + assign TX_BIT_CTRL_OUT3_delay = TX_BIT_CTRL_OUT3_out; + assign TX_BIT_CTRL_OUT4_delay = TX_BIT_CTRL_OUT4_out; + assign TX_BIT_CTRL_OUT5_delay = TX_BIT_CTRL_OUT5_out; + assign TX_BIT_CTRL_OUT6_delay = TX_BIT_CTRL_OUT6_out; + assign TX_BIT_CTRL_OUT_TRI_delay = TX_BIT_CTRL_OUT_TRI_out; + assign VTC_RDY_delay = VTC_RDY_out; + + assign CLK_FROM_EXT_in = CLK_FROM_EXT_delay; + assign EN_VTC_in = (EN_VTC === 1'bz) || EN_VTC_delay; // rv 1 + assign NCLK_NIBBLE_IN_in = NCLK_NIBBLE_IN_delay; + assign PCLK_NIBBLE_IN_in = PCLK_NIBBLE_IN_delay; + assign PHY_RDCS0_in = PHY_RDCS0_delay; + assign PHY_RDCS1_in = PHY_RDCS1_delay; + assign PHY_RDEN_in = PHY_RDEN_delay; + assign PHY_WRCS0_in = PHY_WRCS0_delay; + assign PHY_WRCS1_in = PHY_WRCS1_delay; + assign PLL_CLK_in = PLL_CLK_delay; + assign REFCLK_in = REFCLK_delay; + assign RIU_ADDR_in = RIU_ADDR_delay; + assign RIU_CLK_in = RIU_CLK_delay; + assign RIU_NIBBLE_SEL_in = (RIU_NIBBLE_SEL !== 1'bz) && RIU_NIBBLE_SEL_delay; // rv 0 + assign RIU_WR_DATA_in = RIU_WR_DATA_delay; + assign RIU_WR_EN_in = RIU_WR_EN_delay; + assign RST_in = RST_delay; + assign RX_BIT_CTRL_IN0_in = RX_BIT_CTRL_IN0_delay; + assign RX_BIT_CTRL_IN1_in = RX_BIT_CTRL_IN1_delay; + assign RX_BIT_CTRL_IN2_in = RX_BIT_CTRL_IN2_delay; + assign RX_BIT_CTRL_IN3_in = RX_BIT_CTRL_IN3_delay; + assign RX_BIT_CTRL_IN4_in = RX_BIT_CTRL_IN4_delay; + assign RX_BIT_CTRL_IN5_in = RX_BIT_CTRL_IN5_delay; + assign RX_BIT_CTRL_IN6_in = RX_BIT_CTRL_IN6_delay; + assign TBYTE_IN_in[0] = (TBYTE_IN[0] !== 1'bz) && TBYTE_IN_delay[0]; // rv 0 + assign TBYTE_IN_in[1] = (TBYTE_IN[1] !== 1'bz) && TBYTE_IN_delay[1]; // rv 0 + assign TBYTE_IN_in[2] = (TBYTE_IN[2] !== 1'bz) && TBYTE_IN_delay[2]; // rv 0 + assign TBYTE_IN_in[3] = (TBYTE_IN[3] !== 1'bz) && TBYTE_IN_delay[3]; // rv 0 + assign TX_BIT_CTRL_IN0_in = TX_BIT_CTRL_IN0_delay; + assign TX_BIT_CTRL_IN1_in = TX_BIT_CTRL_IN1_delay; + assign TX_BIT_CTRL_IN2_in = TX_BIT_CTRL_IN2_delay; + assign TX_BIT_CTRL_IN3_in = TX_BIT_CTRL_IN3_delay; + assign TX_BIT_CTRL_IN4_in = TX_BIT_CTRL_IN4_delay; + assign TX_BIT_CTRL_IN5_in = TX_BIT_CTRL_IN5_delay; + assign TX_BIT_CTRL_IN6_in = TX_BIT_CTRL_IN6_delay; + assign TX_BIT_CTRL_IN_TRI_in = TX_BIT_CTRL_IN_TRI_delay; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CTRL_CLK_REG != "EXTERNAL") && + (CTRL_CLK_REG != "INTERNAL"))) begin + $display("Error: [Unisim %s-103] CTRL_CLK attribute is set to %s. Legal values for this attribute are EXTERNAL or INTERNAL. Instance: %m", MODULE_NAME, CTRL_CLK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIV_MODE_REG != "DIV2") && + (DIV_MODE_REG != "DIV4"))) begin + $display("Error: [Unisim %s-105] DIV_MODE attribute is set to %s. Legal values for this attribute are DIV2 or DIV4. Instance: %m", MODULE_NAME, DIV_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_CLK_TO_EXT_NORTH_REG != "DISABLE") && + (EN_CLK_TO_EXT_NORTH_REG != "ENABLE"))) begin + $display("Error: [Unisim %s-110] EN_CLK_TO_EXT_NORTH attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, EN_CLK_TO_EXT_NORTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_CLK_TO_EXT_SOUTH_REG != "DISABLE") && + (EN_CLK_TO_EXT_SOUTH_REG != "ENABLE"))) begin + $display("Error: [Unisim %s-111] EN_CLK_TO_EXT_SOUTH attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, EN_CLK_TO_EXT_SOUTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_DYN_ODLY_MODE_REG != "FALSE") && + (EN_DYN_ODLY_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] EN_DYN_ODLY_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_DYN_ODLY_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_OTHER_NCLK_REG != "FALSE") && + (EN_OTHER_NCLK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] EN_OTHER_NCLK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_OTHER_NCLK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_OTHER_PCLK_REG != "FALSE") && + (EN_OTHER_PCLK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] EN_OTHER_PCLK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_OTHER_PCLK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IDLY_VT_TRACK_REG != "TRUE") && + (IDLY_VT_TRACK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-116] IDLY_VT_TRACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IDLY_VT_TRACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((INV_RXCLK_REG != "FALSE") && + (INV_RXCLK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] INV_RXCLK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, INV_RXCLK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ODLY_VT_TRACK_REG != "TRUE") && + (ODLY_VT_TRACK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-122] ODLY_VT_TRACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ODLY_VT_TRACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QDLY_VT_TRACK_REG != "TRUE") && + (QDLY_VT_TRACK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-124] QDLY_VT_TRACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, QDLY_VT_TRACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REFCLK_SRC_REG != "PLLCLK") && + (REFCLK_SRC_REG != "REFCLK"))) begin + $display("Error: [Unisim %s-126] REFCLK_SRC attribute is set to %s. Legal values for this attribute are PLLCLK or REFCLK. Instance: %m", MODULE_NAME, REFCLK_SRC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ROUNDING_FACTOR_REG != 16) && + (ROUNDING_FACTOR_REG != 2) && + (ROUNDING_FACTOR_REG != 4) && + (ROUNDING_FACTOR_REG != 8) && + (ROUNDING_FACTOR_REG != 32) && + (ROUNDING_FACTOR_REG != 64) && + (ROUNDING_FACTOR_REG != 128))) begin + $display("Error: [Unisim %s-128] ROUNDING_FACTOR attribute is set to %d. Legal values for this attribute are 16, 2, 4, 8, 32, 64 or 128. Instance: %m", MODULE_NAME, ROUNDING_FACTOR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGATE_EXTEND_REG != "FALSE") && + (RXGATE_EXTEND_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] RXGATE_EXTEND attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGATE_EXTEND_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK_PHASE_N_REG != "SHIFT_0") && + (RX_CLK_PHASE_N_REG != "SHIFT_90"))) begin + $display("Error: [Unisim %s-130] RX_CLK_PHASE_N attribute is set to %s. Legal values for this attribute are SHIFT_0 or SHIFT_90. Instance: %m", MODULE_NAME, RX_CLK_PHASE_N_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK_PHASE_P_REG != "SHIFT_0") && + (RX_CLK_PHASE_P_REG != "SHIFT_90"))) begin + $display("Error: [Unisim %s-131] RX_CLK_PHASE_P attribute is set to %s. Legal values for this attribute are SHIFT_0 or SHIFT_90. Instance: %m", MODULE_NAME, RX_CLK_PHASE_P_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_GATING_REG != "DISABLE") && + (RX_GATING_REG != "ENABLE"))) begin + $display("Error: [Unisim %s-132] RX_GATING attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, RX_GATING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SELF_CALIBRATE_REG != "ENABLE") && + (SELF_CALIBRATE_REG != "DISABLE"))) begin + $display("Error: [Unisim %s-133] SELF_CALIBRATE attribute is set to %s. Legal values for this attribute are ENABLE or DISABLE. Instance: %m", MODULE_NAME, SELF_CALIBRATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SERIAL_MODE_REG != "FALSE") && + (SERIAL_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-134] SERIAL_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SERIAL_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-135] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_SPEEDUP_REG != "FAST") && + (SIM_SPEEDUP_REG != "SLOW"))) begin + $display("Error: [Unisim %s-136] SIM_SPEEDUP attribute is set to %s. Legal values for this attribute are FAST or SLOW. Instance: %m", MODULE_NAME, SIM_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-137] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_GATING_REG != "DISABLE") && + (TX_GATING_REG != "ENABLE"))) begin + $display("Error: [Unisim %s-139] TX_GATING attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, TX_GATING_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + if (SIM_DEVICE_REG == "ULTRASCALE") begin + if (RX_CLK_PHASE_P_REG == "SHIFT_90" || RX_CLK_PHASE_N_REG == "SHIFT_90") begin + $display("WARNING: [Unisim %s-1] When using RX_CLK_PHASE_ = SHIFT_90 simulation may not match hardware when using RX_DELAY_VALUE > 0 or CASCADE = TRUE. Every BITSLICE_CONTROL must have at least one RX_BITSLICE with DELAY_VALUE = 0 in order to ensure proper alignment. Instance: %m",MODULE_NAME); + end + end + end + + + assign CLK_STOP_in = 1'b1; // tie off + assign DLY_TEST_IN_in = 1'b0; // tie off + assign SCAN_INT_in = 1'b1; // tie off + +generate +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_BITSLICE_CONTROL_D1 SIP_BITSLICE_CONTROL_INST ( + .BISC_MULTI_FREQ_EN (BISC_MULTI_FREQ_EN_REG), + .CONTROL_DLY_TEST_EN (CONTROL_DLY_TEST_EN_REG), + .CTRL_CLK (CTRL_CLK_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DIV_MODE (DIV_MODE_REG), + .DLY_RNK0 (DLY_RNK0_REG), + .DLY_RNK1 (DLY_RNK1_REG), + .DLY_RNK2 (DLY_RNK2_REG), + .DLY_RNK3 (DLY_RNK3_REG), + .EN_CLK_TO_EXT_NORTH (EN_CLK_TO_EXT_NORTH_REG), + .EN_CLK_TO_EXT_SOUTH (EN_CLK_TO_EXT_SOUTH_REG), + .EN_DYN_ODLY_MODE (EN_DYN_ODLY_MODE_REG), + .EN_OTHER_NCLK (EN_OTHER_NCLK_REG), + .EN_OTHER_PCLK (EN_OTHER_PCLK_REG), + .FDLY (FDLY_REG), + .IDLY_VT_TRACK (IDLY_VT_TRACK_REG), + .INCDEC_CRSE (INCDEC_CRSE_REG), + .INV_RXCLK (INV_RXCLK_REG), + .MASK_FIXDLY (MASK_FIXDLY_REG), + .MON (MON_REG), + .NQTR (NQTR_REG), + .ODLY_VT_TRACK (ODLY_VT_TRACK_REG), + .PQTR (PQTR_REG), + .QDLY_VT_TRACK (QDLY_VT_TRACK_REG), + .READ_IDLE_COUNT (READ_IDLE_COUNT_REG), + .REFCLK_SRC (REFCLK_SRC_REG), + .RIU_RL_ARBITRATION_FIX_EN (RIU_RL_ARBITRATION_FIX_EN_REG), + .ROUNDING_FACTOR (ROUNDING_FACTOR_REG), + .RXGATE_EXTEND (RXGATE_EXTEND_REG), + .RX_CLK_PHASE_N (RX_CLK_PHASE_N_REG), + .RX_CLK_PHASE_P (RX_CLK_PHASE_P_REG), + .RX_GATING (RX_GATING_REG), + .SELF_CALIBRATE (SELF_CALIBRATE_REG), + .SERIAL_MODE (SERIAL_MODE_REG), + .SIM_SPEEDUP (SIM_SPEEDUP_REG), + .SPARE (SPARE_REG), + .TX_GATING (TX_GATING_REG), + .CLK_TO_EXT_NORTH (CLK_TO_EXT_NORTH_out), + .CLK_TO_EXT_SOUTH (CLK_TO_EXT_SOUTH_out), + .DLY_RDY (DLY_RDY_out), + .DLY_TEST_OUT (DLY_TEST_OUT_out), + .DYN_DCI (DYN_DCI_out), + .LOCAL_DIV_CLK (LOCAL_DIV_CLK_out), + .MASTER_PD_OUT (MASTER_PD_OUT_out), + .NCLK_NIBBLE_OUT (NCLK_NIBBLE_OUT_out), + .PCLK_NIBBLE_OUT (PCLK_NIBBLE_OUT_out), + .PLL_CLK_EN (PLL_CLK_EN_out), + .REFCLK_DFD (REFCLK_DFD_out), + .RIU_RD_DATA (RIU_RD_DATA_out), + .RIU_VALID (RIU_VALID_out), + .RX_BIT_CTRL_OUT0 (RX_BIT_CTRL_OUT0_out), + .RX_BIT_CTRL_OUT1 (RX_BIT_CTRL_OUT1_out), + .RX_BIT_CTRL_OUT2 (RX_BIT_CTRL_OUT2_out), + .RX_BIT_CTRL_OUT3 (RX_BIT_CTRL_OUT3_out), + .RX_BIT_CTRL_OUT4 (RX_BIT_CTRL_OUT4_out), + .RX_BIT_CTRL_OUT5 (RX_BIT_CTRL_OUT5_out), + .RX_BIT_CTRL_OUT6 (RX_BIT_CTRL_OUT6_out), + .TX_BIT_CTRL_OUT0 (TX_BIT_CTRL_OUT0_out), + .TX_BIT_CTRL_OUT1 (TX_BIT_CTRL_OUT1_out), + .TX_BIT_CTRL_OUT2 (TX_BIT_CTRL_OUT2_out), + .TX_BIT_CTRL_OUT3 (TX_BIT_CTRL_OUT3_out), + .TX_BIT_CTRL_OUT4 (TX_BIT_CTRL_OUT4_out), + .TX_BIT_CTRL_OUT5 (TX_BIT_CTRL_OUT5_out), + .TX_BIT_CTRL_OUT6 (TX_BIT_CTRL_OUT6_out), + .TX_BIT_CTRL_OUT_TRI (TX_BIT_CTRL_OUT_TRI_out), + .VTC_RDY (VTC_RDY_out), + .CLK_FROM_EXT (CLK_FROM_EXT_in), + .CLK_STOP (CLK_STOP_in), + .DLY_TEST_IN (DLY_TEST_IN_in), + .EN_VTC (EN_VTC_in), + .NCLK_NIBBLE_IN (NCLK_NIBBLE_IN_in), + .PCLK_NIBBLE_IN (PCLK_NIBBLE_IN_in), + .PHY_RDCS0 (PHY_RDCS0_in), + .PHY_RDCS1 (PHY_RDCS1_in), + .PHY_RDEN (PHY_RDEN_in), + .PHY_WRCS0 (PHY_WRCS0_in), + .PHY_WRCS1 (PHY_WRCS1_in), + .PLL_CLK (PLL_CLK_in), + .REFCLK (REFCLK_in), + .RIU_ADDR (RIU_ADDR_in), + .RIU_CLK (RIU_CLK_in), + .RIU_NIBBLE_SEL (RIU_NIBBLE_SEL_in), + .RIU_WR_DATA (RIU_WR_DATA_in), + .RIU_WR_EN (RIU_WR_EN_in), + .RST (RST_in), + .RX_BIT_CTRL_IN0 (RX_BIT_CTRL_IN0_in), + .RX_BIT_CTRL_IN1 (RX_BIT_CTRL_IN1_in), + .RX_BIT_CTRL_IN2 (RX_BIT_CTRL_IN2_in), + .RX_BIT_CTRL_IN3 (RX_BIT_CTRL_IN3_in), + .RX_BIT_CTRL_IN4 (RX_BIT_CTRL_IN4_in), + .RX_BIT_CTRL_IN5 (RX_BIT_CTRL_IN5_in), + .RX_BIT_CTRL_IN6 (RX_BIT_CTRL_IN6_in), + .SCAN_INT (SCAN_INT_in), + .TBYTE_IN (TBYTE_IN_in), + .TX_BIT_CTRL_IN0 (TX_BIT_CTRL_IN0_in), + .TX_BIT_CTRL_IN1 (TX_BIT_CTRL_IN1_in), + .TX_BIT_CTRL_IN2 (TX_BIT_CTRL_IN2_in), + .TX_BIT_CTRL_IN3 (TX_BIT_CTRL_IN3_in), + .TX_BIT_CTRL_IN4 (TX_BIT_CTRL_IN4_in), + .TX_BIT_CTRL_IN5 (TX_BIT_CTRL_IN5_in), + .TX_BIT_CTRL_IN6 (TX_BIT_CTRL_IN6_in), + .TX_BIT_CTRL_IN_TRI (TX_BIT_CTRL_IN_TRI_in), + .GSR (glblGSR) + ); +end +else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + SIP_BITSLICE_CONTROL_K2 SIP_BITSLICE_CONTROL_INST ( + .CONTROL_DLY_TEST_EN (CONTROL_DLY_TEST_EN_REG), + .CTRL_CLK (CTRL_CLK_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DIV_MODE (DIV_MODE_REG), + .DLY_RNK0 (DLY_RNK0_REG), + .DLY_RNK1 (DLY_RNK1_REG), + .DLY_RNK2 (DLY_RNK2_REG), + .DLY_RNK3 (DLY_RNK3_REG), + .EN_CLK_TO_EXT_NORTH (EN_CLK_TO_EXT_NORTH_REG), + .EN_CLK_TO_EXT_SOUTH (EN_CLK_TO_EXT_SOUTH_REG), + .EN_DYN_ODLY_MODE (EN_DYN_ODLY_MODE_REG), + .EN_OTHER_NCLK (EN_OTHER_NCLK_REG), + .EN_OTHER_PCLK (EN_OTHER_PCLK_REG), + .FDLY (FDLY_REG), + .IDLY_VT_TRACK (IDLY_VT_TRACK_REG), + .INCDEC_CRSE (INCDEC_CRSE_REG), + .INV_RXCLK (INV_RXCLK_REG), + .MON (MON_REG), + .NQTR (NQTR_REG), + .ODLY_VT_TRACK (ODLY_VT_TRACK_REG), + .PQTR (PQTR_REG), + .QDLY_VT_TRACK (QDLY_VT_TRACK_REG), + .READ_IDLE_COUNT (READ_IDLE_COUNT_REG), + .REFCLK_SRC (REFCLK_SRC_REG), + .ROUNDING_FACTOR (ROUNDING_FACTOR_REG), + .RXGATE_EXTEND (RXGATE_EXTEND_REG), + .RX_CLK_PHASE_N (RX_CLK_PHASE_N_REG), + .RX_CLK_PHASE_P (RX_CLK_PHASE_P_REG), + .RX_GATING (RX_GATING_REG), + .SELF_CALIBRATE (SELF_CALIBRATE_REG), + .SERIAL_MODE (SERIAL_MODE_REG), + .SIM_SPEEDUP (SIM_SPEEDUP_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .TX_GATING (TX_GATING_REG), + .CLK_TO_EXT_NORTH (CLK_TO_EXT_NORTH_out), + .CLK_TO_EXT_SOUTH (CLK_TO_EXT_SOUTH_out), + .DLY_RDY (DLY_RDY_out), + .DLY_TEST_OUT (DLY_TEST_OUT_out), + .DYN_DCI (DYN_DCI_out), + .LOCAL_DIV_CLK (LOCAL_DIV_CLK_out), + .MASTER_PD_OUT (MASTER_PD_OUT_out), + .NCLK_NIBBLE_OUT (NCLK_NIBBLE_OUT_out), + .PCLK_NIBBLE_OUT (PCLK_NIBBLE_OUT_out), + .PLL_CLK_EN (PLL_CLK_EN_out), + .REFCLK_DFD (REFCLK_DFD_out), + .RIU_RD_DATA (RIU_RD_DATA_out), + .RIU_VALID (RIU_VALID_out), + .RX_BIT_CTRL_OUT0 (RX_BIT_CTRL_OUT0_out), + .RX_BIT_CTRL_OUT1 (RX_BIT_CTRL_OUT1_out), + .RX_BIT_CTRL_OUT2 (RX_BIT_CTRL_OUT2_out), + .RX_BIT_CTRL_OUT3 (RX_BIT_CTRL_OUT3_out), + .RX_BIT_CTRL_OUT4 (RX_BIT_CTRL_OUT4_out), + .RX_BIT_CTRL_OUT5 (RX_BIT_CTRL_OUT5_out), + .RX_BIT_CTRL_OUT6 (RX_BIT_CTRL_OUT6_out), + .TX_BIT_CTRL_OUT0 (TX_BIT_CTRL_OUT0_out), + .TX_BIT_CTRL_OUT1 (TX_BIT_CTRL_OUT1_out), + .TX_BIT_CTRL_OUT2 (TX_BIT_CTRL_OUT2_out), + .TX_BIT_CTRL_OUT3 (TX_BIT_CTRL_OUT3_out), + .TX_BIT_CTRL_OUT4 (TX_BIT_CTRL_OUT4_out), + .TX_BIT_CTRL_OUT5 (TX_BIT_CTRL_OUT5_out), + .TX_BIT_CTRL_OUT6 (TX_BIT_CTRL_OUT6_out), + .TX_BIT_CTRL_OUT_TRI (TX_BIT_CTRL_OUT_TRI_out), + .VTC_RDY (VTC_RDY_out), + .CLK_FROM_EXT (CLK_FROM_EXT_in), + .CLK_STOP (CLK_STOP_in), + .DLY_TEST_IN (DLY_TEST_IN_in), + .EN_VTC (EN_VTC_in), + .NCLK_NIBBLE_IN (NCLK_NIBBLE_IN_in), + .PCLK_NIBBLE_IN (PCLK_NIBBLE_IN_in), + .PHY_RDCS0 (PHY_RDCS0_in), + .PHY_RDCS1 (PHY_RDCS1_in), + .PHY_RDEN (PHY_RDEN_in), + .PHY_WRCS0 (PHY_WRCS0_in), + .PHY_WRCS1 (PHY_WRCS1_in), + .PLL_CLK (PLL_CLK_in), + .REFCLK (REFCLK_in), + .RIU_ADDR (RIU_ADDR_in), + .RIU_CLK (RIU_CLK_in), + .RIU_NIBBLE_SEL (RIU_NIBBLE_SEL_in), + .RIU_WR_DATA (RIU_WR_DATA_in), + .RIU_WR_EN (RIU_WR_EN_in), + .RST (RST_in), + .RX_BIT_CTRL_IN0 (RX_BIT_CTRL_IN0_in), + .RX_BIT_CTRL_IN1 (RX_BIT_CTRL_IN1_in), + .RX_BIT_CTRL_IN2 (RX_BIT_CTRL_IN2_in), + .RX_BIT_CTRL_IN3 (RX_BIT_CTRL_IN3_in), + .RX_BIT_CTRL_IN4 (RX_BIT_CTRL_IN4_in), + .RX_BIT_CTRL_IN5 (RX_BIT_CTRL_IN5_in), + .RX_BIT_CTRL_IN6 (RX_BIT_CTRL_IN6_in), + .SCAN_INT (SCAN_INT_in), + .TBYTE_IN (TBYTE_IN_in), + .TX_BIT_CTRL_IN0 (TX_BIT_CTRL_IN0_in), + .TX_BIT_CTRL_IN1 (TX_BIT_CTRL_IN1_in), + .TX_BIT_CTRL_IN2 (TX_BIT_CTRL_IN2_in), + .TX_BIT_CTRL_IN3 (TX_BIT_CTRL_IN3_in), + .TX_BIT_CTRL_IN4 (TX_BIT_CTRL_IN4_in), + .TX_BIT_CTRL_IN5 (TX_BIT_CTRL_IN5_in), + .TX_BIT_CTRL_IN6 (TX_BIT_CTRL_IN6_in), + .TX_BIT_CTRL_IN_TRI (TX_BIT_CTRL_IN_TRI_in), + .GSR (glblGSR) + ); +end +endgenerate + specify + (PLL_CLK => DLY_RDY) = (100:100:100, 100:100:100); + (PLL_CLK => RX_BIT_CTRL_OUT0[20]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT0[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT0[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT1[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT1[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT2[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT2[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT3[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT3[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT4[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT4[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT5[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT5[26]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT6[25]) = (0:0:0, 0:0:0); + (PLL_CLK => TX_BIT_CTRL_OUT6[26]) = (0:0:0, 0:0:0); + (PLL_CLK => VTC_RDY) = (100:100:100, 100:100:100); + (RIU_CLK => DLY_RDY) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[0]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[10]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[11]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[12]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[13]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[14]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[15]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[1]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[2]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[3]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[4]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[5]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[6]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[7]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[8]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_RD_DATA[9]) = (100:100:100, 100:100:100); + (RIU_CLK => RIU_VALID) = (100:100:100, 100:100:100); + (RIU_CLK => VTC_RDY) = (100:100:100, 100:100:100); + (RX_BIT_CTRL_IN0[9] => RX_BIT_CTRL_OUT0[20]) = (0:0:0, 0:0:0); + (posedge RST => (VTC_RDY +: 0)) = (100:100:100, 100:100:100); + // (TX_BIT_CTRL_OUT0[26] => DLY_RDY) = (0:0:0, 0:0:0); // error prop output to output + // (TX_BIT_CTRL_OUT0[26] => VTC_RDY) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge PLL_CLK, 0:0:0, notifier); + $period (negedge REFCLK, 0:0:0, notifier); + $period (negedge RIU_CLK, 0:0:0, notifier); + $period (posedge PLL_CLK, 0:0:0, notifier); + $period (posedge REFCLK, 0:0:0, notifier); + $period (posedge RIU_CLK, 0:0:0, notifier); + $recrem (negedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay); + $recrem (posedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS0[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[0]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS0[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[1]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS0[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[2]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS0[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[3]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS1[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[0]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS1[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[1]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS1[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[2]); + $setuphold (posedge PLL_CLK, negedge PHY_RDCS1[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[3]); + $setuphold (posedge PLL_CLK, negedge PHY_RDEN[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[0]); + $setuphold (posedge PLL_CLK, negedge PHY_RDEN[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[1]); + $setuphold (posedge PLL_CLK, negedge PHY_RDEN[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[2]); + $setuphold (posedge PLL_CLK, negedge PHY_RDEN[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[3]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS0[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[0]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS0[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[1]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS0[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[2]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS0[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[3]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS1[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[0]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS1[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[1]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS1[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[2]); + $setuphold (posedge PLL_CLK, negedge PHY_WRCS1[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[3]); + $setuphold (posedge PLL_CLK, negedge TBYTE_IN[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[0]); + $setuphold (posedge PLL_CLK, negedge TBYTE_IN[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[1]); + $setuphold (posedge PLL_CLK, negedge TBYTE_IN[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[2]); + $setuphold (posedge PLL_CLK, negedge TBYTE_IN[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[3]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS0[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[0]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS0[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[1]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS0[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[2]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS0[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS0_delay[3]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS1[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[0]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS1[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[1]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS1[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[2]); + $setuphold (posedge PLL_CLK, posedge PHY_RDCS1[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDCS1_delay[3]); + $setuphold (posedge PLL_CLK, posedge PHY_RDEN[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[0]); + $setuphold (posedge PLL_CLK, posedge PHY_RDEN[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[1]); + $setuphold (posedge PLL_CLK, posedge PHY_RDEN[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[2]); + $setuphold (posedge PLL_CLK, posedge PHY_RDEN[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_RDEN_delay[3]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS0[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[0]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS0[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[1]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS0[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[2]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS0[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS0_delay[3]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS1[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[0]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS1[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[1]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS1[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[2]); + $setuphold (posedge PLL_CLK, posedge PHY_WRCS1[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, PHY_WRCS1_delay[3]); + $setuphold (posedge PLL_CLK, posedge TBYTE_IN[0], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[0]); + $setuphold (posedge PLL_CLK, posedge TBYTE_IN[1], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[1]); + $setuphold (posedge PLL_CLK, posedge TBYTE_IN[2], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[2]); + $setuphold (posedge PLL_CLK, posedge TBYTE_IN[3], 0:0:0, 0:0:0, notifier, , , PLL_CLK_delay, TBYTE_IN_delay[3]); + $setuphold (posedge RIU_CLK, negedge EN_VTC, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, EN_VTC_delay); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[0], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[0]); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[1], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[1]); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[2], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[2]); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[3], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[3]); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[4], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[4]); + $setuphold (posedge RIU_CLK, negedge RIU_ADDR[5], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[5]); + $setuphold (posedge RIU_CLK, negedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_NIBBLE_SEL_delay); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[0], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[0]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[10], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[10]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[11], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[11]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[12], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[12]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[13], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[13]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[14], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[14]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[15], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[15]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[1], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[1]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[2], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[2]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[3], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[3]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[4], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[4]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[5], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[5]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[6], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[6]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[7], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[7]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[8], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[8]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_DATA[9], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[9]); + $setuphold (posedge RIU_CLK, negedge RIU_WR_EN, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_EN_delay); + $setuphold (posedge RIU_CLK, posedge EN_VTC, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, EN_VTC_delay); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[0], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[0]); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[1], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[1]); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[2], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[2]); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[3], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[3]); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[4], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[4]); + $setuphold (posedge RIU_CLK, posedge RIU_ADDR[5], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_ADDR_delay[5]); + $setuphold (posedge RIU_CLK, posedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_NIBBLE_SEL_delay); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[0], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[0]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[10], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[10]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[11], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[11]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[12], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[12]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[13], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[13]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[14], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[14]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[15], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[15]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[1], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[1]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[2], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[2]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[3], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[3]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[4], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[4]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[5], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[5]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[6], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[6]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[7], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[7]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[8], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[8]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_DATA[9], 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_DATA_delay[9]); + $setuphold (posedge RIU_CLK, posedge RIU_WR_EN, 0:0:0, 0:0:0, notifier, , , RIU_CLK_delay, RIU_WR_EN_delay); + $width (negedge PLL_CLK, 0:0:0, 0, notifier); + $width (negedge REFCLK, 0:0:0, 0, notifier); + $width (negedge RIU_CLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge PLL_CLK, 0:0:0, 0, notifier); + $width (posedge REFCLK, 0:0:0, 0, notifier); + $width (posedge RIU_CLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BSCANE2.v b/verilog/src/unisims/BSCANE2.v new file mode 100644 index 0000000..89d359f --- /dev/null +++ b/verilog/src/unisims/BSCANE2.v @@ -0,0 +1,149 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Boundary Scan Logic Control Circuit for VIRTEX7 +// /___/ /\ Filename : BSCANE2.v +// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010 +// \___\/\___\ +// +// Revision: +// 02/08/10 - Initial version. +// 06/10/11 - CR 613789. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// 04/07/15 - Added negedge to SEL (CR 857726). +// End Revision + + +`timescale 1 ps / 1 ps + +`celldefine + +module BSCANE2 ( + CAPTURE, + DRCK, + RESET, + RUNTEST, + SEL, + SHIFT, + TCK, + TDI, + TMS, + UPDATE, + + TDO +); + + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + + input TDO; + reg SEL_reg; + reg SEL_zd; + + pulldown (DRCK); + pulldown (RESET); + pulldown (SEL); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + +//--#################################################################### +//--##### Initialization ### +//--#################################################################### + initial begin + + //-------- JTAG_CHAIN + + if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin + $display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN); + #1 $finish; + end + + end + +//--#################################################################### +//--##### Jtag_select ### +//--#################################################################### + always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin + if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL; + else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL; + else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL; + else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL; + end +//--#################################################################### +//--##### USER_TDO ### +//--#################################################################### + always@(TDO) begin + if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO; + else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO; + else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO; + else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO; + end +//--#################################################################### +//--##### USER_SEL ### +//--#################################################################### + always @(negedge glbl.JTAG_TCK_GLBL or posedge SEL_zd) begin + SEL_reg = SEL_zd; + end + assign SEL = SEL_reg; +//--#################################################################### +//--##### Output ### +//--#################################################################### + + assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; + assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + + assign RESET = glbl.JTAG_RESET_GLBL; + assign RUNTEST = glbl.JTAG_RUNTEST_GLBL; + assign SHIFT = glbl.JTAG_SHIFT_GLBL; + assign TDI = glbl.JTAG_TDI_GLBL; + assign TCK = glbl.JTAG_TCK_GLBL; + assign TMS = glbl.JTAG_TMS_GLBL; + assign UPDATE = glbl.JTAG_UPDATE_GLBL; + + specify + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUF.v b/verilog/src/unisims/BUF.v new file mode 100644 index 0000000..297603f --- /dev/null +++ b/verilog/src/unisims/BUF.v @@ -0,0 +1,65 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / General Purpose Buffer +// /___/ /\ Filename : BUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module BUF (O, I); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + output O; + input I; + + buf B1 (O, I); + +`ifdef XIL_TIMING + + specify + + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/BUFCE_LEAF.v b/verilog/src/unisims/BUFCE_LEAF.v new file mode 100644 index 0000000..276a463 --- /dev/null +++ b/verilog/src/unisims/BUFCE_LEAF.v @@ -0,0 +1,192 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Clock Buffer +// /___/ /\ Filename : BUFCE_LEAF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/15/12 - Initial version. +// 02/04/14 - update specify block +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFCE_LEAF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CE_TYPE = "SYNC", + parameter [0:0] IS_CE_INVERTED = 1'b0, + parameter [0:0] IS_I_INVERTED = 1'b0 +)( + output O, + + input CE, + input I +); + +// define constants + localparam MODULE_NAME = "BUFCE_LEAF"; + +// Parameter encodings and registers + localparam CE_TYPE_ASYNC = 1; + localparam CE_TYPE_SYNC = 0; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFCE_LEAF_dr.v" +`else + reg [40:1] CE_TYPE_REG = CE_TYPE; + reg [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED; + reg [0:0] IS_I_INVERTED_REG = IS_I_INVERTED; +`endif + +`ifdef XIL_XECLIB + wire CE_TYPE_BIN; +`else + reg CE_TYPE_BIN; +`endif + + reg attr_test; + reg attr_err; +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CE_in; + wire I_in; + +`ifdef XIL_TIMING + wire CE_delay; + wire I_delay; +`endif + +`ifdef XIL_TIMING + assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I_delay ^ IS_I_INVERTED_REG; +`else + assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I ^ IS_I_INVERTED_REG; +`endif + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + CE_TYPE_SYNC; + +`else + always @ (trig_attr) begin + #1; + CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + CE_TYPE_SYNC; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CE_TYPE_REG != "SYNC") && + (CE_TYPE_REG != "ASYNC"))) begin + $display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg enable_clk = 1'b1; + + always @(I_in or CE_in or glblGSR) begin + if (glblGSR) + enable_clk = 1'b1; + else if ((CE_TYPE_BIN == CE_TYPE_ASYNC) || ~I_in) + enable_clk = CE_in; + end + + assign O = enable_clk & I_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire i_en_n; + wire i_en_p; + + assign i_en_n = IS_I_INVERTED_REG; + assign i_en_p = ~IS_I_INVERTED_REG; +`endif + +`ifdef XIL_TIMING + specify + (CE => O) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $width (negedge CE, 0:0:0, 0, notifier); + $width (posedge CE, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFCE_ROW.v b/verilog/src/unisims/BUFCE_ROW.v new file mode 100644 index 0000000..0b754ba --- /dev/null +++ b/verilog/src/unisims/BUFCE_ROW.v @@ -0,0 +1,204 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Clock Buffer +// /___/ /\ Filename : BUFCE_ROW.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/15/12 - Initial version. +// 02/04/14 - update specify block +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFCE_ROW #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CE_TYPE = "SYNC", + parameter [0:0] IS_CE_INVERTED = 1'b0, + parameter [0:0] IS_I_INVERTED = 1'b0 +)( + output O, + + input CE, + input I +); + +// define constants + localparam MODULE_NAME = "BUFCE_ROW"; + +// Parameter encodings and registers + localparam CE_TYPE_ASYNC = 1; + localparam CE_TYPE_HARDSYNC = 2; + localparam CE_TYPE_SYNC = 0; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFCE_ROW_dr.v" +`else + reg [64:1] CE_TYPE_REG = CE_TYPE; + reg [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED; + reg [0:0] IS_I_INVERTED_REG = IS_I_INVERTED; +`endif + +`ifdef XIL_XECLIB + wire [1:0] CE_TYPE_BIN; +`else + reg [1:0] CE_TYPE_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CE_in; + wire I_in; + +`ifdef XIL_TIMING + wire CE_delay; + wire I_delay; +`endif + +`ifdef XIL_TIMING + assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I_delay ^ IS_I_INVERTED_REG; +`else + assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I ^ IS_I_INVERTED_REG; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + +`else + always @ (trig_attr) begin + #1; + CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CE_TYPE_REG != "SYNC") && + (CE_TYPE_REG != "ASYNC") && + (CE_TYPE_REG != "HARDSYNC"))) begin + $display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC, ASYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg enable_clk = 1'b1; + + always @(I_in or CE_in or glblGSR) begin + if (glblGSR) + enable_clk = 1'b1; + else if ((CE_TYPE_BIN == CE_TYPE_ASYNC) || ~I_in) + enable_clk = CE_in; + end + + assign O = enable_clk & I_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire i_en_n; + wire i_en_p; + + assign i_en_n = IS_I_INVERTED_REG; + assign i_en_p = ~IS_I_INVERTED_REG; + +`endif + +`ifdef XIL_TIMING + specify + (CE => O) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $width (negedge CE, 0:0:0, 0, notifier); + $width (posedge CE, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFG.v b/verilog/src/unisims/BUFG.v new file mode 100644 index 0000000..5d39855 --- /dev/null +++ b/verilog/src/unisims/BUFG.v @@ -0,0 +1,76 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / General Clock Buffer +// /___/ /\ Filename : BUFG.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFG +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output O, + + input I +); + +// define constants + localparam MODULE_NAME = "BUFG"; + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + buf B1 (O, I); + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFGCE.v b/verilog/src/unisims/BUFGCE.v new file mode 100644 index 0000000..2b39cfe --- /dev/null +++ b/verilog/src/unisims/BUFGCE.v @@ -0,0 +1,353 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / General Clock Buffer with Clock Enable +// /___/ /\ Filename : BUFGCE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/15/12 - Initial version. +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFGCE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CE_TYPE = "SYNC", + parameter [0:0] IS_CE_INVERTED = 1'b0, + parameter [0:0] IS_I_INVERTED = 1'b0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter STARTUP_SYNC = "FALSE" +)( + output O, + + input CE, + input I +); + +// define constants + localparam MODULE_NAME = "BUFGCE"; + +// Parameter encodings and registers + localparam CE_TYPE_ASYNC = 1; + localparam CE_TYPE_HARDSYNC = 2; + localparam CE_TYPE_SYNC = 0; + localparam SIM_DEVICE_7SERIES = 1; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE = 4; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 5; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 7; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 8; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF = 10; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 11; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 12; + localparam SIM_DEVICE_VERSAL_HBM = 15; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 16; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 17; + localparam SIM_DEVICE_VERSAL_PREMIUM = 18; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 19; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 20; + localparam SIM_DEVICE_VERSAL_PRIME = 21; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 22; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 23; + localparam STARTUP_SYNC_FALSE = 0; + localparam STARTUP_SYNC_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFGCE_dr.v" +`else + reg [64:1] CE_TYPE_REG = CE_TYPE; + reg [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED; + reg [0:0] IS_I_INVERTED_REG = IS_I_INVERTED; + reg [144:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC; +`endif + +`ifdef XIL_XECLIB + wire [1:0] CE_TYPE_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire STARTUP_SYNC_BIN; +`else + reg [1:0] CE_TYPE_BIN; + reg [4:0] SIM_DEVICE_BIN; + reg STARTUP_SYNC_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CE_in; + wire I_in; + +`ifdef XIL_TIMING + wire CE_delay; + wire I_delay; +`endif + +`ifdef XIL_TIMING + assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I_delay ^ IS_I_INVERTED_REG; +`else + assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1 + assign I_in = I ^ IS_I_INVERTED_REG; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + +`else + always @ (trig_attr) begin + #1; + CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CE_TYPE_REG != "SYNC") && + (CE_TYPE_REG != "ASYNC") && + (CE_TYPE_REG != "HARDSYNC"))) begin + $display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC, ASYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "7SERIES") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, 7SERIES, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_SYNC_REG != "FALSE") && + (STARTUP_SYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + + reg O_out; + reg enable_clk; + reg [2:0] gwe_sync; + wire gwe_muxed_sync; + reg [2:0] ce_sync; + wire ce_muxed_sync; + wire cb; + + + initial begin + gwe_sync = 3'b000; + ce_sync = 3'b000; + enable_clk = 1'b0; + end + + always @(posedge I_in ) begin + if(I_in==1'b1) + gwe_sync <= {gwe_sync[1:0], ~glblGSR}; + end + + assign gwe_muxed_sync = (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE) ? gwe_sync[2] : ~glblGSR; + + + always @(posedge I_in ) begin + if(I_in==1'b1) + ce_sync <= {ce_sync[1:0], CE_in}; + end + + assign ce_muxed_sync = (CE_TYPE_BIN == CE_TYPE_HARDSYNC) ? ce_sync[2] : CE_in; + + assign cb = ~( (~gwe_muxed_sync) || ((CE_TYPE_BIN !== CE_TYPE_ASYNC) && I_in)); + + + always @(*) begin + if(cb) + enable_clk <= ce_muxed_sync; + end + + always @(*) + O_out = enable_clk && I_in; + + assign O = O_out; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire i_en_n; + wire i_en_p; + + assign i_en_n = IS_I_INVERTED_REG; + assign i_en_p = ~IS_I_INVERTED_REG; + +`endif + +`ifdef XIL_TIMING + specify + (CE => O) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $width (negedge CE, 0:0:0, 0, notifier); + $width (negedge I, 0:0:0, 0, notifier); + $width (posedge CE, 0:0:0, 0, notifier); + $width (posedge I, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFGCE_DIV.v b/verilog/src/unisims/BUFGCE_DIV.v new file mode 100644 index 0000000..595e3df --- /dev/null +++ b/verilog/src/unisims/BUFGCE_DIV.v @@ -0,0 +1,586 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2020.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / BUFGCE_DIV +// /___/ /\ Filename : BUFGCE_DIV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFGCE_DIV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer BUFGCE_DIVIDE = 1, + parameter CE_TYPE = "SYNC", + parameter HARDSYNC_CLR = "FALSE", + parameter [0:0] IS_CE_INVERTED = 1'b0, + parameter [0:0] IS_CLR_INVERTED = 1'b0, + parameter [0:0] IS_I_INVERTED = 1'b0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter STARTUP_SYNC = "FALSE" +)( + output O, + + input CE, + input CLR, + input I +); + +// define constants + localparam MODULE_NAME = "BUFGCE_DIV"; + +// Parameter encodings and registers + localparam CE_TYPE_HARDSYNC = 1; + localparam CE_TYPE_SYNC = 0; + localparam HARDSYNC_CLR_FALSE = 0; + localparam HARDSYNC_CLR_TRUE = 1; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 4; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 7; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 8; + localparam SIM_DEVICE_VERSAL_AI_RF = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 10; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 11; + localparam SIM_DEVICE_VERSAL_HBM = 14; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PREMIUM = 17; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 19; + localparam SIM_DEVICE_VERSAL_PRIME = 20; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 21; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 22; + localparam STARTUP_SYNC_FALSE = 0; + localparam STARTUP_SYNC_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFGCE_DIV_dr.v" +`else + reg [31:0] BUFGCE_DIVIDE_REG = BUFGCE_DIVIDE; + reg [64:1] CE_TYPE_REG = CE_TYPE; + reg [40:1] HARDSYNC_CLR_REG = HARDSYNC_CLR; + reg [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED; + reg [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED; + reg [0:0] IS_I_INVERTED_REG = IS_I_INVERTED; + reg [144:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC; +`endif + +`ifdef XIL_XECLIB + wire [3:0] BUFGCE_DIVIDE_BIN; + wire CE_TYPE_BIN; + wire HARDSYNC_CLR_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire STARTUP_SYNC_BIN; +`else + reg [3:0] BUFGCE_DIVIDE_BIN; + reg CE_TYPE_BIN; + reg HARDSYNC_CLR_BIN; + reg [4:0] SIM_DEVICE_BIN; + reg STARTUP_SYNC_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CE_in; + wire CLR_in; + wire I_in; + +`ifdef XIL_TIMING + wire CE_delay; + wire CLR_delay; + wire I_delay; +`endif + +`ifdef XIL_TIMING + assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1 + assign CLR_in = (CLR !== 1'bz) && (CLR_delay ^ IS_CLR_INVERTED_REG); // rv 0 + assign I_in = I_delay ^ IS_I_INVERTED_REG; +`else + assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1 + assign CLR_in = (CLR !== 1'bz) && (CLR ^ IS_CLR_INVERTED_REG); // rv 0 + assign I_in = I ^ IS_I_INVERTED_REG; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign BUFGCE_DIVIDE_BIN = BUFGCE_DIVIDE_REG[3:0]; + + assign CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + + assign HARDSYNC_CLR_BIN = + (HARDSYNC_CLR_REG == "FALSE") ? HARDSYNC_CLR_FALSE : + (HARDSYNC_CLR_REG == "TRUE") ? HARDSYNC_CLR_TRUE : + HARDSYNC_CLR_FALSE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + +`else + always @ (trig_attr) begin + #1; + BUFGCE_DIVIDE_BIN = BUFGCE_DIVIDE_REG[3:0]; + + CE_TYPE_BIN = + (CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC : + (CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC : + CE_TYPE_SYNC; + + HARDSYNC_CLR_BIN = + (HARDSYNC_CLR_REG == "FALSE") ? HARDSYNC_CLR_FALSE : + (HARDSYNC_CLR_REG == "TRUE") ? HARDSYNC_CLR_TRUE : + HARDSYNC_CLR_FALSE; + + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BUFGCE_DIVIDE_REG != 1) && + (BUFGCE_DIVIDE_REG != 2) && + (BUFGCE_DIVIDE_REG != 3) && + (BUFGCE_DIVIDE_REG != 4) && + (BUFGCE_DIVIDE_REG != 5) && + (BUFGCE_DIVIDE_REG != 6) && + (BUFGCE_DIVIDE_REG != 7) && + (BUFGCE_DIVIDE_REG != 8))) begin + $display("Error: [Unisim %s-101] BUFGCE_DIVIDE attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8. Instance: %m", MODULE_NAME, BUFGCE_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CE_TYPE_REG != "SYNC") && + (CE_TYPE_REG != "HARDSYNC"))) begin + $display("Error: [Unisim %s-102] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((HARDSYNC_CLR_REG != "FALSE") && + (HARDSYNC_CLR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-103] HARDSYNC_CLR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, HARDSYNC_CLR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-107] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_SYNC_REG != "FALSE") && + (STARTUP_SYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + integer clk_count, first_toggle_count, second_toggle_count; + reg first_rise, first_half_period; + reg O_bufgce_div; + wire i_ce; + wire CLR_int; + reg ce_en; + wire gsr_muxed_sync; + wire ce_muxed_sync; + wire clr_muxed_sync; + wire clr_muxed_xrm; + reg [2:0] gwe_sync; + reg [2:0] ce_sync; + reg [2:0] clr_sync; + + always @ (trig_attr) begin + #1; + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE)) begin + $display("Warning: [Unisim %s-200] SIM_DEVICE attribute is set to %s and STARTUP_SYNC is set to %s. STARTUP_SYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, STARTUP_SYNC_REG); + STARTUP_SYNC_BIN = STARTUP_SYNC_FALSE; //force correct + end + + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (CE_TYPE_BIN == CE_TYPE_HARDSYNC)) begin + $display("Warning: [Unisim %s-201] SIM_DEVICE attribute is set to %s and CE_TYPE is set to %s. HARDSYNC CE functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, CE_TYPE_REG); + CE_TYPE_BIN = CE_TYPE_SYNC; //force correct + end + + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (HARDSYNC_CLR == HARDSYNC_CLR_TRUE )) begin + $display("Warning: [Unisim %s-202] SIM_DEVICE attribute is set to %s and HARDSYNC_CLR is set to %s. HARDSYNC CLR functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, HARDSYNC_CLR_REG); + HARDSYNC_CLR_BIN = HARDSYNC_CLR_FALSE; //force correct + end + + end //always + + + + initial begin + clk_count = 1; + first_toggle_count = 1; + second_toggle_count = 1; + O_bufgce_div = 1'b0; + ce_en = 1'b0; + gwe_sync = 3'b000; + ce_sync = 3'b000; + clr_sync = 3'b111; + + + end + + always @(posedge I_in) begin + if(I_in==1'b1) + gwe_sync <= {gwe_sync[1:0], ~glblGSR}; + end + + assign gsr_muxed_sync = (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE) ? ~gwe_sync[2] : glblGSR; + + always @(negedge I_in) begin + if(I_in==1'b0) + clr_sync <= {clr_sync[1:0], CLR_in}; + end + + assign clr_muxed_sync = (HARDSYNC_CLR_BIN == HARDSYNC_CLR_TRUE) ? clr_sync[2] : CLR_in; + assign clr_muxed_xrm = (clr_muxed_sync ===1'bX) ? 1'b1 : clr_muxed_sync; + + always @(posedge I_in) begin + if(I_in==1'b1) + ce_sync <= {ce_sync[1:0], CE_in}; + end + + assign ce_muxed_sync = (CE_TYPE_BIN == CE_TYPE_HARDSYNC) ? ce_sync[2] : CE_in; + + + always @ (trig_attr) begin + #1; + case (BUFGCE_DIVIDE_BIN) + 1 : begin + first_toggle_count = 1; + second_toggle_count = 1; + end + 2 : begin + first_toggle_count = 2; + second_toggle_count = 2; + end + 3 : begin + first_toggle_count = 2; + second_toggle_count = 4; + end + 4 : begin + first_toggle_count = 4; + second_toggle_count = 4; + end + 5 : begin + first_toggle_count = 4; + second_toggle_count = 6; + end + 6 : begin + first_toggle_count = 6; + second_toggle_count = 6; + end + 7 : begin + first_toggle_count = 6; + second_toggle_count = 8; + end + 8 : begin + first_toggle_count = 8; + second_toggle_count = 8; + end + endcase // case(BUFGCE_DIV) + + end + + always begin + if (gsr_muxed_sync == 1'b1) begin + assign O_bufgce_div = 1'b0; + assign clk_count = 0; + assign first_rise = 1'b1; + assign first_half_period = 1'b0; + end + else if (gsr_muxed_sync == 1'b0) begin + deassign O_bufgce_div; + deassign clk_count; + deassign first_rise; + deassign first_half_period; + end + @(gsr_muxed_sync); + end + + always @(I_in, gsr_muxed_sync, ce_muxed_sync, clr_muxed_xrm) begin + if (gsr_muxed_sync || clr_muxed_xrm) + ce_en <= 1'b0; + else if (~I_in) + ce_en <= ce_muxed_sync; + end + + assign i_ce = I_in & ce_en; + + always @(i_ce or posedge gsr_muxed_sync or posedge clr_muxed_xrm) begin + if (first_toggle_count == 1) begin + O_bufgce_div = i_ce; + end + else begin + if(clr_muxed_xrm == 1'b1 || gsr_muxed_sync == 1'b1) begin + O_bufgce_div = 1'b0; + clk_count = 1; + first_half_period = 1'b1; + first_rise = 1'b1; + end + else if(clr_muxed_xrm == 1'b0 && gsr_muxed_sync == 1'b0) begin + if (i_ce == 1'b1 && first_rise == 1'b1) begin + O_bufgce_div = 1'b1; + clk_count = 1; + first_half_period = 1'b1; + first_rise = 1'b0; + end + else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin + O_bufgce_div = ~O_bufgce_div; + clk_count = 1; + first_half_period = 1'b1; + end + else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin + O_bufgce_div = ~O_bufgce_div; + clk_count = 1; + first_half_period = 1'b0; + end + else if (first_rise == 1'b0) begin + clk_count = clk_count + 1; + end + end + end + end + + assign O = O_bufgce_div; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire i_en_n; + wire i_en_p; + + assign i_en_n = IS_I_INVERTED_REG; + assign i_en_p = ~IS_I_INVERTED_REG; + +`endif + + specify + (I => O) = (0:0:0, 0:0:0); + (negedge CLR => (O +: 0)) = (0:0:0, 0:0:0); + (posedge CLR => (O +: 0)) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $recrem (negedge CLR, negedge I, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, CLR_delay, I_delay); + $recrem (negedge CLR, posedge I, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, CLR_delay, I_delay); + $recrem (posedge CLR, negedge I, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, CLR_delay, I_delay); + $recrem (posedge CLR, posedge I, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, CLR_delay, I_delay); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (negedge I, negedge CLR, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CLR_delay); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay); + $setuphold (negedge I, posedge CLR, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CLR_delay); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $setuphold (posedge I, negedge CLR, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CLR_delay); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay); + $setuphold (posedge I, posedge CLR, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CLR_delay); + $width (negedge CLR, 0:0:0, 0, notifier); + $width (negedge I, 0:0:0, 0, notifier); + $width (posedge CLR, 0:0:0, 0, notifier); + $width (posedge I, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFGCTRL.v b/verilog/src/unisims/BUFGCTRL.v new file mode 100644 index 0000000..b165fbb --- /dev/null +++ b/verilog/src/unisims/BUFGCTRL.v @@ -0,0 +1,668 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / General Clock Control Buffer +// /___/ /\ Filename : BUFGCTRL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFGCTRL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CE_TYPE_CE0 = "SYNC", + parameter CE_TYPE_CE1 = "SYNC", + parameter integer INIT_OUT = 0, + parameter [0:0] IS_CE0_INVERTED = 1'b0, + parameter [0:0] IS_CE1_INVERTED = 1'b0, + parameter [0:0] IS_I0_INVERTED = 1'b0, + parameter [0:0] IS_I1_INVERTED = 1'b0, + parameter [0:0] IS_IGNORE0_INVERTED = 1'b0, + parameter [0:0] IS_IGNORE1_INVERTED = 1'b0, + parameter [0:0] IS_S0_INVERTED = 1'b0, + parameter [0:0] IS_S1_INVERTED = 1'b0, + parameter PRESELECT_I0 = "FALSE", + parameter PRESELECT_I1 = "FALSE", + parameter SIM_DEVICE = "ULTRASCALE", + parameter STARTUP_SYNC = "FALSE" +)( + output O, + + input CE0, + input CE1, + input I0, + input I1, + input IGNORE0, + input IGNORE1, + input S0, + input S1 +); + +// define constants + localparam MODULE_NAME = "BUFGCTRL"; + +// Parameter encodings and registers + localparam CE_TYPE_CE0_HARDSYNC = 1; + localparam CE_TYPE_CE0_SYNC = 0; + localparam CE_TYPE_CE1_HARDSYNC = 1; + localparam CE_TYPE_CE1_SYNC = 0; + localparam PRESELECT_I0_FALSE = 0; + localparam PRESELECT_I0_TRUE = 1; + localparam PRESELECT_I1_FALSE = 0; + localparam PRESELECT_I1_TRUE = 1; + localparam SIM_DEVICE_7SERIES = 1; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE = 4; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 5; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 7; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 8; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF = 10; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 11; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 12; + localparam SIM_DEVICE_VERSAL_HBM = 15; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 16; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 17; + localparam SIM_DEVICE_VERSAL_PREMIUM = 18; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 19; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 20; + localparam SIM_DEVICE_VERSAL_PRIME = 21; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 22; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 23; + localparam STARTUP_SYNC_FALSE = 0; + localparam STARTUP_SYNC_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFGCTRL_dr.v" +`else + reg [64:1] CE_TYPE_CE0_REG = CE_TYPE_CE0; + reg [64:1] CE_TYPE_CE1_REG = CE_TYPE_CE1; + reg [31:0] INIT_OUT_REG = INIT_OUT; + reg [0:0] IS_CE0_INVERTED_REG = IS_CE0_INVERTED; + reg [0:0] IS_CE1_INVERTED_REG = IS_CE1_INVERTED; + reg [0:0] IS_I0_INVERTED_REG = IS_I0_INVERTED; + reg [0:0] IS_I1_INVERTED_REG = IS_I1_INVERTED; + reg [0:0] IS_IGNORE0_INVERTED_REG = IS_IGNORE0_INVERTED; + reg [0:0] IS_IGNORE1_INVERTED_REG = IS_IGNORE1_INVERTED; + reg [0:0] IS_S0_INVERTED_REG = IS_S0_INVERTED; + reg [0:0] IS_S1_INVERTED_REG = IS_S1_INVERTED; + reg [40:1] PRESELECT_I0_REG = PRESELECT_I0; + reg [40:1] PRESELECT_I1_REG = PRESELECT_I1; + reg [144:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC; +`endif + +`ifdef XIL_XECLIB + wire CE_TYPE_CE0_BIN; + wire CE_TYPE_CE1_BIN; + wire INIT_OUT_BIN; + wire PRESELECT_I0_BIN; + wire PRESELECT_I1_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire STARTUP_SYNC_BIN; +`else + reg CE_TYPE_CE0_BIN; + reg CE_TYPE_CE1_BIN; + reg INIT_OUT_BIN; + reg PRESELECT_I0_BIN; + reg PRESELECT_I1_BIN; + reg [4:0] SIM_DEVICE_BIN; + reg STARTUP_SYNC_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; + reg glblGRESTORE = 1'b0; +`else + tri0 glblGSR = glbl.GSR; + tri0 glblGRESTORE = glbl.GRESTORE; +`endif + + wire CE0_in; + wire CE1_in; + wire I0_in; + wire I1_in; + wire IGNORE0_in; + wire IGNORE1_in; + wire S0_in; + wire S1_in; + +`ifdef XIL_TIMING + wire CE0_delay; + wire CE1_delay; + wire I0_delay; + wire I1_delay; + wire S0_delay; + wire S1_delay; +`endif + +`ifdef XIL_TIMING + assign CE0_in = (CE0 !== 1'bz) && (CE0_delay ^ IS_CE0_INVERTED_REG); // rv 0 + assign CE1_in = (CE1 !== 1'bz) && (CE1_delay ^ IS_CE1_INVERTED_REG); // rv 0 + assign I0_in = I0_delay ^ IS_I0_INVERTED_REG; + assign I1_in = I1_delay ^ IS_I1_INVERTED_REG; + assign S0_in = (S0 !== 1'bz) && (S0_delay ^ IS_S0_INVERTED_REG); // rv 0 + assign S1_in = (S1 !== 1'bz) && (S1_delay ^ IS_S1_INVERTED_REG); // rv 0 +`else + assign CE0_in = (CE0 !== 1'bz) && (CE0 ^ IS_CE0_INVERTED_REG); // rv 0 + assign CE1_in = (CE1 !== 1'bz) && (CE1 ^ IS_CE1_INVERTED_REG); // rv 0 + assign I0_in = I0 ^ IS_I0_INVERTED_REG; + assign I1_in = I1 ^ IS_I1_INVERTED_REG; + assign S0_in = (S0 !== 1'bz) && (S0 ^ IS_S0_INVERTED_REG); // rv 0 + assign S1_in = (S1 !== 1'bz) && (S1 ^ IS_S1_INVERTED_REG); // rv 0 +`endif + + assign IGNORE0_in = (IGNORE0 !== 1'bz) && (IGNORE0 ^ IS_IGNORE0_INVERTED_REG); // rv 0 + assign IGNORE1_in = (IGNORE1 !== 1'bz) && (IGNORE1 ^ IS_IGNORE1_INVERTED_REG); // rv 0 + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CE_TYPE_CE0_BIN = + (CE_TYPE_CE0_REG == "SYNC") ? CE_TYPE_CE0_SYNC : + (CE_TYPE_CE0_REG == "HARDSYNC") ? CE_TYPE_CE0_HARDSYNC : + CE_TYPE_CE0_SYNC; + + assign CE_TYPE_CE1_BIN = + (CE_TYPE_CE1_REG == "SYNC") ? CE_TYPE_CE1_SYNC : + (CE_TYPE_CE1_REG == "HARDSYNC") ? CE_TYPE_CE1_HARDSYNC : + CE_TYPE_CE1_SYNC; + + assign INIT_OUT_BIN = INIT_OUT_REG[0]; + + assign PRESELECT_I0_BIN = + (PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE : + (PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE : + PRESELECT_I0_FALSE; + + assign PRESELECT_I1_BIN = + (PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE : + (PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE : + PRESELECT_I1_FALSE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + +`else + always @ (trig_attr) begin + #1; + CE_TYPE_CE0_BIN = + (CE_TYPE_CE0_REG == "SYNC") ? CE_TYPE_CE0_SYNC : + (CE_TYPE_CE0_REG == "HARDSYNC") ? CE_TYPE_CE0_HARDSYNC : + CE_TYPE_CE0_SYNC; + + CE_TYPE_CE1_BIN = + (CE_TYPE_CE1_REG == "SYNC") ? CE_TYPE_CE1_SYNC : + (CE_TYPE_CE1_REG == "HARDSYNC") ? CE_TYPE_CE1_HARDSYNC : + CE_TYPE_CE1_SYNC; + + INIT_OUT_BIN = INIT_OUT_REG[0]; + + PRESELECT_I0_BIN = + (PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE : + (PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE : + PRESELECT_I0_FALSE; + + PRESELECT_I1_BIN = + (PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE : + (PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE : + PRESELECT_I1_FALSE; + + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CE_TYPE_CE0_REG != "SYNC") && + (CE_TYPE_CE0_REG != "HARDSYNC"))) begin + $display("Error: [Unisim %s-101] CE_TYPE_CE0 attribute is set to %s. Legal values for this attribute are SYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_CE0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CE_TYPE_CE1_REG != "SYNC") && + (CE_TYPE_CE1_REG != "HARDSYNC"))) begin + $display("Error: [Unisim %s-102] CE_TYPE_CE1 attribute is set to %s. Legal values for this attribute are SYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_CE1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((INIT_OUT_REG != 0) && + (INIT_OUT_REG != 1))) begin + $display("Error: [Unisim %s-104] INIT_OUT attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, INIT_OUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PRESELECT_I0_REG != "FALSE") && + (PRESELECT_I0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] PRESELECT_I0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PRESELECT_I0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PRESELECT_I1_REG != "FALSE") && + (PRESELECT_I1_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] PRESELECT_I1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PRESELECT_I1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "7SERIES") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-115] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, 7SERIES, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_SYNC_REG != "FALSE") && + (STARTUP_SYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg O_out; + + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + +// *** both preselects can not be 1 simultaneously. + if ((PRESELECT_I0_REG == "TRUE") && (PRESELECT_I1_REG == "TRUE")) begin + $display("Error : [Unisim %s-1] The attributes PRESELECT_I0 and PRESELECT_I1 should not be set to TRUE simultaneously. Instance: %m", MODULE_NAME); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + always @ (trig_attr) begin + #1; + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE)) begin + $display("Warning: [Unisim %s-200] SIM_DEVICE attribute is set to %s and STARTUP_SYNC is set to %s. STARTUP_SYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, STARTUP_SYNC_REG); + STARTUP_SYNC_BIN = STARTUP_SYNC_FALSE; //force correct + end + + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (CE_TYPE_CE0_BIN == CE_TYPE_CE0_HARDSYNC || CE_TYPE_CE1_BIN==CE_TYPE_CE1_HARDSYNC)) begin + $display("Warning: [Unisim %s-201] SIM_DEVICE attribute is set to %s; CE_TYPE_CE0 is set to %s and CE_TYPE_CE1 is set to %s. HARDSYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, CE_TYPE_CE0_REG, CE_TYPE_CE1_REG); + CE_TYPE_CE0_BIN = CE_TYPE_CE0_SYNC; //force correct + CE_TYPE_CE1_BIN = CE_TYPE_CE1_SYNC; + end + end //always + +`endif + + + reg [2:0] gwe0_sync; + reg [2:0] gwe1_sync; + wire gwe_sync; + wire gwe; + wire gwe_muxed_sync; + reg [2:0] CE0_sync; + reg [2:0] CE1_sync; + wire ce0_muxed_sync; + wire ce1_muxed_sync; + reg CE0_in_dly; + reg CE1_in_dly; + wire I0_optinv; + wire I1_optinv; + wire d00; + wire d01; + wire d10; + wire d11; + reg qb00; + reg qb01; + reg qb10; + reg qb11; + wire cb00; + wire cb01; + wire cb10; + wire cb11; + reg state0; + reg state1; + + initial begin + CE0_sync = 3'b000; + CE1_sync = 3'b000; + gwe0_sync = 3'b000; + gwe1_sync = 3'b000; + O_out = 1'b0; + + #2; + qb00 = (PRESELECT_I0_BIN==PRESELECT_I0_TRUE)? 1'b1:1'b0; + qb01 = (PRESELECT_I0_BIN==PRESELECT_I0_TRUE)? 1'b1:1'b0; + qb10 = (PRESELECT_I1_BIN==PRESELECT_I1_TRUE)? 1'b1:1'b0; + qb11 = (PRESELECT_I1_BIN==PRESELECT_I1_TRUE)? 1'b1:1'b0; + //don't put anything after here + end + + assign gwe = ~glblGSR; + + assign I0_optinv = INIT_OUT_BIN ^ I0_in; + assign I1_optinv = INIT_OUT_BIN ^ I1_in; + + always @ (negedge I0_optinv or posedge glblGRESTORE) begin + if(glblGRESTORE) + gwe0_sync <= 3'd0; + else + gwe0_sync <= {gwe0_sync[1:0], gwe}; + end + + always @ (negedge I1_optinv or posedge glblGRESTORE) begin + if(glblGRESTORE) + gwe1_sync <= 3'd0; + else + gwe1_sync <= {gwe1_sync[1:0], gwe}; + end + + assign gwe_sync = ((PRESELECT_I0_BIN==PRESELECT_I0_TRUE ) ? gwe0_sync[2] : + (PRESELECT_I1_BIN==PRESELECT_I1_TRUE ) ? gwe1_sync[2] : + (gwe0_sync[2] | gwe1_sync[2])); + assign gwe_muxed_sync = (STARTUP_SYNC_BIN==STARTUP_SYNC_TRUE) ? gwe_sync : gwe; + + always @(*) CE0_in_dly = #1 CE0_in; + always @(*) CE1_in_dly = #1 CE1_in; + + always @ (posedge I0_optinv or posedge glblGRESTORE) + if(glblGRESTORE) + CE0_sync <= 3'd0; + else + CE0_sync <= {CE0_sync[1:0], CE0_in_dly}; + + always @ (posedge I1_optinv or posedge glblGRESTORE) + if(glblGRESTORE) + CE1_sync <= 3'd0; + else + CE1_sync <= {CE1_sync[1:0], CE1_in_dly}; + + + assign ce0_muxed_sync = (CE_TYPE_CE0_BIN==CE_TYPE_CE0_HARDSYNC) ? CE0_sync[2] : CE0_in; + assign ce1_muxed_sync = (CE_TYPE_CE1_BIN==CE_TYPE_CE1_HARDSYNC) ? CE1_sync[2] : CE1_in; + + assign d00 = ~(state1 & S0_in); + assign d01 = ~(qb00 & ce0_muxed_sync); + assign d10 = ~(state0 & S1_in); + assign d11 = ~(qb10 & ce1_muxed_sync); + + assign cb00 = ~( (~gwe_muxed_sync) | (~IGNORE0_in) & (~I0_optinv) ); + assign cb01 = ~( (~gwe_muxed_sync) | (~IGNORE0_in) & ( I0_optinv) ); + assign cb10 = ~( (~gwe_muxed_sync) | (~IGNORE1_in) & (~I1_optinv) ); + assign cb11 = ~( (~gwe_muxed_sync) | (~IGNORE1_in) & ( I1_optinv) ); + + always@(*) begin + if (glblGRESTORE && ~PRESELECT_I0_BIN) + qb00 <= 1'b0; + else if (glblGRESTORE && PRESELECT_I0_BIN) + qb00 <= 1'b1; + else if(cb00) + qb00 <= #1 ~d00; + end + + always@(*) begin + if (glblGRESTORE && ~PRESELECT_I0_BIN) + qb01 <= 1'b0; + else if (glblGRESTORE && PRESELECT_I0_BIN) + qb01 <= 1'b1; + else if(cb01) + qb01 <= #1 ~d01; + end + + always @(*) begin + if (glblGRESTORE && ~PRESELECT_I1_BIN) + qb10 <= 1'b0; + else if (glblGRESTORE && PRESELECT_I1_BIN) + qb10 <= 1'b1; + else if(cb10) + qb10 <= #1 ~d10; + end + + always@(*) begin + if (glblGRESTORE && ~PRESELECT_I1_BIN) + qb11 <= 1'b0; + else if (glblGRESTORE && PRESELECT_I1_BIN) + qb11 <= 1'b1; + else if(cb11) + qb11 <= #1 ~d11; + end + + always@(*) begin + state0 = ~(qb01|(~gwe_muxed_sync)); + state1 = ~(qb11|(~gwe_muxed_sync)); + end + + always @(*) begin + case ({state1,state0}) + 2'b00 : O_out = 1'b0; + 2'b01 : O_out = I1_in; + 2'b10 : O_out = I0_in; + 2'b11 : O_out = INIT_OUT_BIN; + default : O_out = 1'bx; + endcase + end + + assign O = O_out; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire i0_en_n; + wire i0_en_p; + wire i1_en_n; + wire i1_en_p; + + assign i0_en_n = IS_I0_INVERTED_REG; + assign i0_en_p = ~IS_I0_INVERTED_REG; + assign i1_en_n = IS_I1_INVERTED_REG; + assign i1_en_p = ~IS_I1_INVERTED_REG; + +`endif + +// I0/I1 are clocks but do not clock anything in this model. do not need the 100 ps. +// specify absorbs a potential glitch in functional simuation when S0/S1 switch +// that needs to remain to match rtl. +// IO paths are combinatorial through muxes and not registers +`ifdef XIL_TIMING + specify + (CE0 => O) = (0:0:0, 0:0:0); + (CE1 => O) = (0:0:0, 0:0:0); + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + $period (negedge I0, 0:0:0, notifier); + $period (negedge I1, 0:0:0, notifier); + $period (posedge I0, 0:0:0, notifier); + $period (posedge I1, 0:0:0, notifier); + $setuphold (negedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, CE0_delay); + $setuphold (negedge I0, negedge S0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, S0_delay); + $setuphold (negedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, CE0_delay); + $setuphold (negedge I0, posedge S0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, S0_delay); + $setuphold (negedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, CE1_delay); + $setuphold (negedge I1, negedge S1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, S1_delay); + $setuphold (negedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, CE1_delay); + $setuphold (negedge I1, posedge S1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, S1_delay); + $setuphold (posedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, CE0_delay); + $setuphold (posedge I0, negedge S0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, S0_delay); + $setuphold (posedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, CE0_delay); + $setuphold (posedge I0, posedge S0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, S0_delay); + $setuphold (posedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, CE1_delay); + $setuphold (posedge I1, negedge S1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, S1_delay); + $setuphold (posedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, CE1_delay); + $setuphold (posedge I1, posedge S1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, S1_delay); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFGP.v b/verilog/src/unisims/BUFGP.v new file mode 100644 index 0000000..8a3f654 --- /dev/null +++ b/verilog/src/unisims/BUFGP.v @@ -0,0 +1,63 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Primary Global Buffer for Driving Clocks or Long Lines +// /___/ /\ Filename : BUFGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module BUFGP (O, I); + + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + + output O; + input I; + + buf B1 (O, I); + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFG_GT.v b/verilog/src/unisims/BUFG_GT.v new file mode 100644 index 0000000..2fbfcea --- /dev/null +++ b/verilog/src/unisims/BUFG_GT.v @@ -0,0 +1,489 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2020.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / BUFG_GT +// /___/ /\ Filename : BUFG_GT.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFG_GT #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "ULTRASCALE", + parameter STARTUP_SYNC = "FALSE" +)( + output O, + + input CE, + input CEMASK, + input CLR, + input CLRMASK, + input [2:0] DIV, + input I +); + +// define constants + localparam MODULE_NAME = "BUFG_GT"; + +// Parameter encodings and registers + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 4; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 7; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 8; + localparam SIM_DEVICE_VERSAL_AI_RF = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 10; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 11; + localparam SIM_DEVICE_VERSAL_HBM = 14; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PREMIUM = 17; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 19; + localparam SIM_DEVICE_VERSAL_PRIME = 20; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 21; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 22; + localparam STARTUP_SYNC_FALSE = 0; + localparam STARTUP_SYNC_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFG_GT_dr.v" +`else + reg [144:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC; +`endif + +`ifdef XIL_XECLIB + wire [4:0] SIM_DEVICE_BIN; + wire STARTUP_SYNC_BIN; +`else + reg [4:0] SIM_DEVICE_BIN; + reg STARTUP_SYNC_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CEMASK_in; + wire CE_in; + wire CLRMASK_in; + wire CLR_in; + wire I_in; + wire [2:0] DIV_in; + + assign CEMASK_in = (CEMASK !== 1'bz) && CEMASK; // rv 0 + assign CE_in = (CE === 1'bz) || CE; // rv 1 + assign CLRMASK_in = (CLRMASK !== 1'bz) && CLRMASK; // rv 0 + assign CLR_in = (CLR !== 1'bz) && CLR; // rv 0 + assign DIV_in[0] = (DIV[0] !== 1'bz) && DIV[0]; // rv 0 + assign DIV_in[1] = (DIV[1] !== 1'bz) && DIV[1]; // rv 0 + assign DIV_in[2] = (DIV[2] !== 1'bz) && DIV[2]; // rv 0 + assign I_in = I; + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + +`else + always @ (trig_attr) begin + #1; + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_SYNC_REG != "FALSE") && + (STARTUP_SYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end //always + + always @ (trig_attr) begin + #1; + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE)) begin + $display("Warning: [Unisim %s-200] SIM_DEVICE attribute is set to %s and STARTUP_SYNC is set to %s. STARTUP_SYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, STARTUP_SYNC_REG); + STARTUP_SYNC_BIN = STARTUP_SYNC_FALSE; //force correct + end + end //always + +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + integer clk_count=1, first_toggle_count=1, second_toggle_count=1; + reg first_rise = 1'b0, first_half_period = 1'b0; + reg O_bufg_gt = 0; + reg O_bufg_gt_dev = 0; + wire i_ce, i_inv, clr_inv ; + wire ce_masked, clrmask_inv, clr_masked; + reg ce_en = 1'b0; + reg ce_sync1 = 1'b0; + reg ce_sync2 = 1'b0; + reg clr_sync1 = 1'b0; + reg clr_sync2 = 1'b0; + wire ce_sync; + wire clr_sync; + reg [2:0] gwe_sync; + wire gsr_muxed_sync; + reg sim_device_versal_or_later; + + initial begin + gwe_sync = 3'b000; + sim_device_versal_or_later = 1'b0; + end + + always @ (trig_attr) begin + #1; + if ((SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_CORE ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_CORE_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_CORE_ES2 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_EDGE ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_RF ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_RF_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_AI_RF_ES2 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_HBM ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_HBM_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_HBM_ES2 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PREMIUM ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PREMIUM_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PREMIUM_ES2 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PRIME ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PRIME_ES1 ) || + (SIM_DEVICE_BIN == SIM_DEVICE_VERSAL_PRIME_ES2 )) + sim_device_versal_or_later <= 1'b1; + else + sim_device_versal_or_later <= 1'b0; + end //always + + always @(posedge I_in) begin + if(I_in==1'b1) + gwe_sync <= {gwe_sync[1:0], ~glblGSR}; + end + + assign gsr_muxed_sync = (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE) ? ~gwe_sync[2] : glblGSR; + + always@(DIV_in) begin + case (DIV_in) + 3'b000 : begin + first_toggle_count = 1; + second_toggle_count = 1; + end + 3'b001 : begin + first_toggle_count = 2; + second_toggle_count = 2; + end + 3'b010 : begin + first_toggle_count = 2; + second_toggle_count = 4; + end + 3'b011 : begin + first_toggle_count = 4; + second_toggle_count = 4; + end + 3'b100 : begin + first_toggle_count = 4; + second_toggle_count = 6; + end + 3'b101 : begin + first_toggle_count = 6; + second_toggle_count = 6; + end + 3'b110 : begin + first_toggle_count = 6; + second_toggle_count = 8; + end + 3'b111 : begin + first_toggle_count = 8; + second_toggle_count = 8; + end + endcase // case(BUFG_GT) + + end + + always begin + if (gsr_muxed_sync == 1'b1) begin + assign O_bufg_gt = 1'b0; + assign clk_count = 0; + assign first_rise = 1'b1; + assign first_half_period = 1'b0; + end + else if (gsr_muxed_sync == 1'b0) begin + deassign O_bufg_gt; + deassign clk_count; + deassign first_rise; + deassign first_half_period; + end + @(gsr_muxed_sync); + end + + always @(posedge I_in, posedge gsr_muxed_sync) + begin + if (gsr_muxed_sync == 1'b1) + begin + ce_sync1 <= 1'b0; + ce_sync2 <= 1'b0; + end + else + begin + ce_sync1 <= CE_in; + ce_sync2 <= ce_sync1; + end + end + + assign ce_sync = sim_device_versal_or_later ? CE_in : ce_sync2; + + assign clr_inv = ~CLR_in; + + always @(posedge I_in, negedge clr_inv) + begin + if(~clr_inv) + begin + clr_sync1 <= 1'b0; + clr_sync2 <= 1'b0; + end + else + {clr_sync2, clr_sync1} <= {clr_sync1, 1'b1}; + end + assign clr_sync = sim_device_versal_or_later ? clr_inv : clr_sync2; + + assign i_inv = ~I_in; + assign clrmask_inv = ~CLRMASK_in; + assign ce_masked = ce_sync | CEMASK_in; + assign clr_masked = ~clr_sync & clrmask_inv; + + always @(i_inv, gsr_muxed_sync, ce_masked, clr_masked) + begin + if (gsr_muxed_sync || clr_masked) + ce_en <= 1'b0; + else if (i_inv) + ce_en <= ce_masked; + end + + assign i_ce = I_in & ce_en; + + always @(i_ce or posedge gsr_muxed_sync or posedge clr_masked) begin + if (first_toggle_count == 1) begin + O_bufg_gt = i_ce; + end + else begin + if(clr_masked == 1'b1 || gsr_muxed_sync == 1'b1) begin + O_bufg_gt = 1'b0; + clk_count = 1; + first_half_period = 1'b1; + first_rise = 1'b1; + end + else if(clr_masked == 1'b0 && gsr_muxed_sync == 1'b0) begin + if (i_ce == 1'b1 && first_rise == 1'b1) begin + O_bufg_gt = 1'b1; + clk_count = 1; + first_half_period = 1'b1; + first_rise = 1'b0; + end + else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin + O_bufg_gt = ~O_bufg_gt; + clk_count = 1; + first_half_period = 1'b1; + end + else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin + O_bufg_gt = ~O_bufg_gt; + clk_count = 1; + first_half_period = 1'b0; + end + else if (first_rise == 1'b0) begin + clk_count = clk_count + 1; + end + end + end + end + + // assign #1 O = O_bufg_gt; + + always @(*) begin + if(sim_device_versal_or_later) + O_bufg_gt_dev <= O_bufg_gt; + else + O_bufg_gt_dev <= #1 O_bufg_gt; + end + + assign O = O_bufg_gt_dev; + + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $width (negedge CLR, 0:0:0, 0, notifier); + $width (negedge I, 0:0:0, 0, notifier); + $width (posedge CLR, 0:0:0, 0, notifier); + $width (posedge I, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFG_GT_SYNC.v b/verilog/src/unisims/BUFG_GT_SYNC.v new file mode 100644 index 0000000..81cb733 --- /dev/null +++ b/verilog/src/unisims/BUFG_GT_SYNC.v @@ -0,0 +1,71 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Synchronizer for BUFG_GT Control Signals +// /___/ /\ Filename : BUFG_GT_SYNC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/03/14 - Initial version. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFG_GT_SYNC +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output CESYNC, + output CLRSYNC, + + input CE, + input CLK, + input CLR +); + +// define constants + localparam MODULE_NAME = "BUFG_GT_SYNC"; + + wire CE_in; + wire CLK_in; + wire CLR_in; + + assign CE_in = (CE === 1'bz) || CE; // rv 1 + assign CLK_in = CLK; + assign CLR_in = (CLR !== 1'bz) && CLR; // rv 0 + +// begin behavioral model + + assign CESYNC = CE_in; + assign CLRSYNC = CLR_in; + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFG_PS.v b/verilog/src/unisims/BUFG_PS.v new file mode 100644 index 0000000..0cee1e5 --- /dev/null +++ b/verilog/src/unisims/BUFG_PS.v @@ -0,0 +1,294 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / A high-fanout buffer for low-skew distribution of the PS Clock signals +// /___/ /\ Filename : BUFG_PS.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFG_PS #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter STARTUP_SYNC = "FALSE" +)( + output O, + + input I +); + +// define constants + localparam MODULE_NAME = "BUFG_PS"; + +// Parameter encodings and registers + localparam SIM_DEVICE_ULTRASCALE_PLUS = 0; + localparam SIM_DEVICE_VERSAL_AI_CORE = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_RF = 8; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10; + localparam SIM_DEVICE_VERSAL_HBM = 13; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 14; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 15; + localparam SIM_DEVICE_VERSAL_PREMIUM = 16; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 17; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 18; + localparam SIM_DEVICE_VERSAL_PRIME = 19; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 20; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 21; + localparam STARTUP_SYNC_FALSE = 0; + localparam STARTUP_SYNC_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "BUFG_PS_dr.v" +`else + reg [144:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC; +`endif + +`ifdef XIL_XECLIB + wire [4:0] SIM_DEVICE_BIN; + wire STARTUP_SYNC_BIN; +`else + reg [4:0] SIM_DEVICE_BIN; + reg STARTUP_SYNC_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE_PLUS; + + assign STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + +`else + always @ (trig_attr) begin + #1; + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE_PLUS; + + STARTUP_SYNC_BIN = + (STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE : + (STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE : + STARTUP_SYNC_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_SYNC_REG != "FALSE") && + (STARTUP_SYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end //always + + always @ (trig_attr) begin + #1; + if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) && + (SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) && + (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE)) begin + $display("Warning: [Unisim %s-200] SIM_DEVICE attribute is set to %s and STARTUP_SYNC is set to %s. STARTUP_SYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, STARTUP_SYNC_REG); + STARTUP_SYNC_BIN = STARTUP_SYNC_FALSE; //force correct + end + end //always + +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg enable_clk; + reg [2:0] gwe_sync; + wire gwe_muxed_sync; + reg gwe_latch; + wire I_in; + reg O_out; + + assign I_in = I; + + initial begin + gwe_sync = 3'b000; + enable_clk = 1'b0; + end + + always @(posedge I_in) begin + if(I_in==1'b1) + gwe_sync <= {gwe_sync[1:0], ~glblGSR}; + end + + assign gwe_muxed_sync = (STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE) ? gwe_sync[2] : ~glblGSR; + + always @(*) begin + if(~I_in) + gwe_latch <= gwe_muxed_sync; + end + + always @(*) + O_out = gwe_latch && I_in; + + assign O = O_out; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $width (negedge I, 0:0:0, 0, notifier); + $width (posedge I, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFH.v b/verilog/src/unisims/BUFH.v new file mode 100644 index 0000000..96c24b4 --- /dev/null +++ b/verilog/src/unisims/BUFH.v @@ -0,0 +1,67 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / H Clock Buffer +// /___/ /\ Filename : BUFH.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 09//9/08 - Change to use BUFHCE according to yaml. +// 11/11/08 - Change to not use BUFHCE. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module BUFH (O, I); + + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + reg notifier; + +`endif + + + output O; + input I; + + buf B1 (O, I); + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + $period (posedge I, 0:0:0, notifier); + specparam PATHPULSE$ = 0; + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/BUFHCE.v b/verilog/src/unisims/BUFHCE.v new file mode 100644 index 0000000..b2d3f04 --- /dev/null +++ b/verilog/src/unisims/BUFHCE.v @@ -0,0 +1,151 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i +// \ \ Description : Xilinx Timing Simulation Library Component +// / / H Clock Buffer with Active High Enable +// /___/ /\ Filename : BUFHCE.v +// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009 +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 09/19/08 - Add GSR +// 10/19/08 - Recoding to same as BUFGCE according to hardware. +// 11/15/10 - Add CE_TYPE attribute (CR578114) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 05/24/12 - 661573 - Remove 100 ps delay +// 10/12/12 - 681696 - fix preselect behavior. +// 10/30/12 - 684744 - match mapping with ISE. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps/1 ps + +`celldefine + +module BUFHCE #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter CE_TYPE = "SYNC", + parameter integer INIT_OUT = 0, + parameter [0:0] IS_CE_INVERTED = 1'b0 +)( + output O, + + input CE, + input I +); + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + wire del_I, delCE; + wire NCE, o_bufg_o, o_bufg1_o; + reg CE_TYPE_BINARY; + reg INIT_OUT_BINARY; + reg IS_CE_INVERTED_BIN = IS_CE_INVERTED; + + initial begin + case (CE_TYPE) + "SYNC" : CE_TYPE_BINARY = 1'b0; + "ASYNC" : CE_TYPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CE_TYPE on BUFHCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE); + #1 $finish; + end + endcase + + if ((INIT_OUT >= 0) && (INIT_OUT <= 1)) + INIT_OUT_BINARY = INIT_OUT; + else begin + $display("Attribute Syntax Error : The Attribute INIT_OUT on BUFHCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT); + #1 $finish; + end + + end + + + BUFGCTRL bufgctrl0_inst (.O(o_bufg_o), + .CE0(~NCE), + .CE1(NCE), + .I0(del_I), + .I1(1'b0), + .IGNORE0(CE_TYPE_BINARY), + .IGNORE1(1'b0), + .S0(1'b1), + .S1(1'b1)); + + defparam bufgctrl0_inst.INIT_OUT = 1'b0; + defparam bufgctrl0_inst.PRESELECT_I0 = "TRUE"; + defparam bufgctrl0_inst.PRESELECT_I1 = "FALSE"; + + + INV I1 (.I(delCE ^ IS_CE_INVERTED_BIN), + .O(NCE)); + + + BUFGCTRL bufgctrl1_inst (.O(o_bufg1_o), + .CE0(~NCE), + .CE1(NCE), + .I0(del_I), + .I1(1'b1), + .IGNORE0(CE_TYPE_BINARY), + .IGNORE1(1'b0), + .S0(1'b1), + .S1(1'b1)); + + defparam bufgctrl1_inst.INIT_OUT = 1'b0; + defparam bufgctrl1_inst.PRESELECT_I0 = "TRUE"; + defparam bufgctrl1_inst.PRESELECT_I1 = "FALSE"; + + + assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o; + + +`ifndef XIL_TIMING + + assign del_I = I; + assign delCE = CE; + +`endif + + + specify + + (I => O) = (0:0:0, 0:0:0); + +`ifdef XIL_TIMING + + $period (posedge I, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE); + +`endif + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFIO.v b/verilog/src/unisims/BUFIO.v new file mode 100644 index 0000000..043133c --- /dev/null +++ b/verilog/src/unisims/BUFIO.v @@ -0,0 +1,76 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Local Clock Buffer for I/O +// /___/ /\ Filename : BUFIO.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 05/30/07 - Changed timescale to 1 ps / 1 ps. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFIO +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output O, + + input I +); + +// define constants + localparam MODULE_NAME = "BUFIO"; + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + buf B1 (O, I); + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFMR.v b/verilog/src/unisims/BUFMR.v new file mode 100644 index 0000000..de6e58d --- /dev/null +++ b/verilog/src/unisims/BUFMR.v @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.1 +// \ \ Description : +// / / +// /__/ /\ Filename : BUFMR.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 05/24/12 - 661573 - Remove 100 ps delay +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFMR ( + O, + + I +); + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + reg notifier; + +`endif + + output O; + + input I; + + + buf B1 (O, I); + + specify + + ( I => O) = (0:0:0, 0:0:0); + +`ifdef XIL_TIMING + + $period (posedge I, 0:0:0, notifier); + +`endif + + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFMRCE.v b/verilog/src/unisims/BUFMRCE.v new file mode 100644 index 0000000..46b7ef2 --- /dev/null +++ b/verilog/src/unisims/BUFMRCE.v @@ -0,0 +1,120 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.1 +// \ \ Description : +// / / +// /__/ /\ Filename : BUFMRCE.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 05/24/12 - 661573 - Remove 100 ps delay +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFMRCE #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter CE_TYPE = "SYNC", + parameter integer INIT_OUT = 0, + parameter [0:0] IS_CE_INVERTED = 1'b0 +)( + output O, + + input CE, + input I +); + + wire NCE, o_bufg_o, o_bufg1_o; + reg CE_TYPE_BINARY; + reg INIT_OUT_BINARY; + reg IS_CE_INVERTED_BIN = IS_CE_INVERTED; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + + wire O_OUT; + + wire delay_CE; + wire delay_I; + + initial begin + case (CE_TYPE) + "SYNC" : CE_TYPE_BINARY = 1'b0; + "ASYNC" : CE_TYPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CE_TYPE on BUFMRCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE); + #1 $finish; + end + endcase + + if ((INIT_OUT >= 0) && (INIT_OUT <= 1)) + INIT_OUT_BINARY = INIT_OUT; + else begin + $display("Attribute Syntax Error : The Attribute INIT_OUT on BUFMRCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT); + #1 $finish; + end + + end + + + BUFGCTRL #(.INIT_OUT(1'b0), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B1 + (.O(o_bufg_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b0), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1)); + + + INV I1 (.I(delay_CE ^ IS_CE_INVERTED_BIN), .O(NCE)); + + + BUFGCTRL #(.INIT_OUT(1'b1), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B2 + (.O(o_bufg1_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1)); + + + assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o; + +`ifndef XIL_TIMING + + assign delay_I = I; + assign delay_CE = CE; + +`endif + + specify + ( I => O) = (0:0:0, 0:0:0); + + `ifdef XIL_TIMING + + $period (posedge I, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE); + + `endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/BUFR.v b/verilog/src/unisims/BUFR.v new file mode 100644 index 0000000..2ba437a --- /dev/null +++ b/verilog/src/unisims/BUFR.v @@ -0,0 +1,259 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i (O.72) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Regional Clock Buffer +// /___/ /\ Filename : BUFR.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus. +// 04/04/2005 - Add SIM_DEVICE paramter to support Virtex5. CE pin has 4 clock +// latency for Virtex 4 and none for Virtex5 +// 07/25/05 - Updated names to Virtex5 +// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch. +// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206). +// 07/19/06 - Add wire declaration for undeclared wire signals. +// 04/01/09 - CR 517236 -- Added VIRTEX6 support +// 11/13/09 - Added VIRTEX7 +// 01/20/10 - Change VIRTEX7 to internal_name (CR545223) +// 02/23/10 - Use assign for o_out (CR543271) +// 06/09/10 - Change internal_name to 7_SERIES +// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653) +// 08/09/11 - Add 7SERIES to ce_en logic (CR620544) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 03/15/12 - Match with hardware (CR 650440) +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module BUFR (O, CE, CLR, I); + + output O; + + input CE; + input CLR; + input I; + + parameter BUFR_DIVIDE = "BYPASS"; + parameter SIM_DEVICE = "7SERIES"; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + integer count, period_toggle, half_period_toggle; + reg first_rise, half_period_done; + reg notifier; + reg o_out_divide = 0; + wire o_out; + reg ce_enable1, ce_enable2, ce_enable3, ce_enable4; + tri0 GSR = glbl.GSR; + wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce; + + buf buf_i (i_in, I); + buf buf_ce (ce_in, CE); + buf buf_clr (clr_in, CLR); + buf buf_gsr (gsr_in, GSR); + buf buf_o (O, o_out); + + initial begin + case (BUFR_DIVIDE) + "BYPASS" : period_toggle = 0; + "1" : begin + period_toggle = 1; + half_period_toggle = 1; + end + "2" : begin + period_toggle = 2; + half_period_toggle = 2; + end + "3" : begin + period_toggle = 4; + half_period_toggle = 2; + end + "4" : begin + period_toggle = 4; + half_period_toggle = 4; + end + "5" : begin + period_toggle = 6; + half_period_toggle = 4; + end + "6" : begin + period_toggle = 6; + half_period_toggle = 6; + end + "7" : begin + period_toggle = 8; + half_period_toggle = 6; + end + "8" : begin + period_toggle = 8; + half_period_toggle = 8; + end + default : begin + $display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE); + #1 $finish; + end + endcase // case(BUFR_DIVIDE) + + case (SIM_DEVICE) + "VIRTEX4" : ; + "VIRTEX5" : ; + "VIRTEX6" : ; + "7SERIES" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE); + #1 $finish; + end + endcase + + end // initial begin + + + always @(gsr_in or clr_in) + if (gsr_in == 1'b1 || clr_in == 1'b1) begin + assign o_out_divide = 1'b0; + assign count = 0; + assign first_rise = 1'b1; + assign half_period_done = 1'b0; + if (gsr_in == 1'b1) begin + assign ce_enable1 = 1'b0; + assign ce_enable2 = 1'b0; + assign ce_enable3 = 1'b0; + assign ce_enable4 = 1'b0; + end + end + else if (gsr_in == 1'b0 || clr_in == 1'b0) begin + deassign o_out_divide; + deassign count; + deassign first_rise; + deassign half_period_done; + if (gsr_in == 1'b0) begin + deassign ce_enable1; + deassign ce_enable2; + deassign ce_enable3; + deassign ce_enable4; + end + end + + + always @(negedge i_in) + begin + ce_enable1 <= ce_in; + ce_enable2 <= ce_enable1; + ce_enable3 <= ce_enable2; + ce_enable4 <= ce_enable3; + end + + assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4; + + assign i_ce = i_in & ce_en; + + generate + case (SIM_DEVICE) + "VIRTEX4" : begin + always @(i_in or ce_en) + if (ce_en == 1'b1) begin + if (i_in == 1'b1 && first_rise == 1'b1) begin + o_out_divide = 1'b1; + first_rise = 1'b0; + end + else if (count == half_period_toggle && half_period_done == 1'b0) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b1; + count = 0; + end + else if (count == period_toggle && half_period_done == 1'b1) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b0; + count = 0; + end + + if (first_rise == 1'b0) + count = count + 1; + end // if (ce_in == 1'b1) + else begin + count = 0; + first_rise = 1; + end + end + "VIRTEX5","VIRTEX6","7SERIES" : begin + always @(i_ce) + begin + if (i_ce == 1'b1 && first_rise == 1'b1) begin + o_out_divide = 1'b1; + first_rise = 1'b0; + end + else if (count == half_period_toggle && half_period_done == 1'b0) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b1; + count = 0; + end + else if (count == period_toggle && half_period_done == 1'b1) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b0; + count = 0; + end + + if (first_rise == 1'b0) begin + count = count + 1; + end // if (ce_in == 1'b1) + end + end + endcase + endgenerate + + assign o_out = (period_toggle == 0) ? i_in : o_out_divide; + + + +//*** Timing Checks Start here + + always @(notifier) begin + o_out_divide <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (CLR => O) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + $period (negedge I, 0:0:0, notifier); + $period (posedge I, 0:0:0, notifier); + $setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier); + $setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier); + $setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier); + $setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier); + $width (posedge CLR, 0:0:0, 0, notifier); + $width (posedge I, 0:0:0, 0, notifier); + $width (negedge I, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // BUFR + +`endcelldefine diff --git a/verilog/src/unisims/CAPTUREE2.v b/verilog/src/unisims/CAPTUREE2.v new file mode 100644 index 0000000..bc51d7f --- /dev/null +++ b/verilog/src/unisims/CAPTUREE2.v @@ -0,0 +1,95 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.1 +// \ \ Description : +// / / +// /__/ /\ Filename : CAPTUREE2.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl +// Revision: 1.0 +// 05/09/12 - removed GSR reference (CR 659430). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module CAPTUREE2 ( + CAP, + CLK +); + + parameter ONESHOT = "TRUE"; + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif + + + input CAP; + input CLK; + + reg [0:0] ONESHOT_BINARY; + + reg notifier; + + + wire CAP_IN; + wire CLK_IN; + + wire CAP_INDELAY; + wire CLK_INDELAY; + + initial begin + case (ONESHOT) + "TRUE" : ONESHOT_BINARY = 1'b1; + "FALSE" : ONESHOT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ONESHOT on CAPTUREE2 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ONESHOT); + #1 $finish; + end + endcase + + end + + + buf B_CAP (CAP_IN, CAP); + buf B_CLK (CLK_IN, CLK); + + specify + + `ifdef XIL_TIMING + $period (posedge CLK, 0:0:0, notifier); + $setuphold (posedge CLK, negedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP); + $setuphold (posedge CLK, posedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP); + + `endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/CARRY4.v b/verilog/src/unisims/CARRY4.v new file mode 100644 index 0000000..37ebe7a --- /dev/null +++ b/verilog/src/unisims/CARRY4.v @@ -0,0 +1,176 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Fast Carry Logic with Look Ahead +// /___/ /\ Filename : CARRY4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 04/11/05 - Initial version. +// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752) +// 05/31/05 - Change pin order, remove connection check for CYINIT and CI. +// 12/21/05 - Add timing path. +// 04/13/06 - Add full timing path for DI to O (CR228786) +// 06/04/07 - Add wire definition. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module CARRY4 +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output [3:0] CO, + output [3:0] O, + + input CI, + input CYINIT, + input [3:0] DI, + input [3:0] S +); + +// define constants + localparam MODULE_NAME = "CARRY4"; + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CI_in; + wire CYINIT_in; + wire [3:0] DI_in; + wire [3:0] S_in; + + assign CI_in = (CI !== 1'bz) && CI; // rv 0 + assign CYINIT_in = (CYINIT !== 1'bz) && CYINIT; // rv 0 + assign DI_in = DI; + assign S_in = S; + +// begin behavioral model + + wire [3:0] CO_fb; + assign CO_fb = {CO[2:0], CI_in || CYINIT_in}; + assign O = S_in ^ CO_fb; + assign CO = (S_in & CO_fb) | (~S_in & DI_in); + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (CI => CO[0]) = (0:0:0, 0:0:0); + (CI => CO[1]) = (0:0:0, 0:0:0); + (CI => CO[2]) = (0:0:0, 0:0:0); + (CI => CO[3]) = (0:0:0, 0:0:0); + (CI => O[0]) = (0:0:0, 0:0:0); + (CI => O[1]) = (0:0:0, 0:0:0); + (CI => O[2]) = (0:0:0, 0:0:0); + (CI => O[3]) = (0:0:0, 0:0:0); + (CYINIT => CO[0]) = (0:0:0, 0:0:0); + (CYINIT => CO[1]) = (0:0:0, 0:0:0); + (CYINIT => CO[2]) = (0:0:0, 0:0:0); + (CYINIT => CO[3]) = (0:0:0, 0:0:0); + (CYINIT => O[0]) = (0:0:0, 0:0:0); + (CYINIT => O[1]) = (0:0:0, 0:0:0); + (CYINIT => O[2]) = (0:0:0, 0:0:0); + (CYINIT => O[3]) = (0:0:0, 0:0:0); + (DI[0] => CO[0]) = (0:0:0, 0:0:0); + (DI[0] => CO[1]) = (0:0:0, 0:0:0); + (DI[0] => CO[2]) = (0:0:0, 0:0:0); + (DI[0] => CO[3]) = (0:0:0, 0:0:0); + (DI[0] => O[0]) = (0:0:0, 0:0:0); + (DI[0] => O[1]) = (0:0:0, 0:0:0); + (DI[0] => O[2]) = (0:0:0, 0:0:0); + (DI[0] => O[3]) = (0:0:0, 0:0:0); + (DI[1] => CO[0]) = (0:0:0, 0:0:0); + (DI[1] => CO[1]) = (0:0:0, 0:0:0); + (DI[1] => CO[2]) = (0:0:0, 0:0:0); + (DI[1] => CO[3]) = (0:0:0, 0:0:0); + (DI[1] => O[0]) = (0:0:0, 0:0:0); + (DI[1] => O[1]) = (0:0:0, 0:0:0); + (DI[1] => O[2]) = (0:0:0, 0:0:0); + (DI[1] => O[3]) = (0:0:0, 0:0:0); + (DI[2] => CO[0]) = (0:0:0, 0:0:0); + (DI[2] => CO[1]) = (0:0:0, 0:0:0); + (DI[2] => CO[2]) = (0:0:0, 0:0:0); + (DI[2] => CO[3]) = (0:0:0, 0:0:0); + (DI[2] => O[0]) = (0:0:0, 0:0:0); + (DI[2] => O[1]) = (0:0:0, 0:0:0); + (DI[2] => O[2]) = (0:0:0, 0:0:0); + (DI[2] => O[3]) = (0:0:0, 0:0:0); + (DI[3] => CO[0]) = (0:0:0, 0:0:0); + (DI[3] => CO[1]) = (0:0:0, 0:0:0); + (DI[3] => CO[2]) = (0:0:0, 0:0:0); + (DI[3] => CO[3]) = (0:0:0, 0:0:0); + (DI[3] => O[0]) = (0:0:0, 0:0:0); + (DI[3] => O[1]) = (0:0:0, 0:0:0); + (DI[3] => O[2]) = (0:0:0, 0:0:0); + (DI[3] => O[3]) = (0:0:0, 0:0:0); + (S[0] => CO[0]) = (0:0:0, 0:0:0); + (S[0] => CO[1]) = (0:0:0, 0:0:0); + (S[0] => CO[2]) = (0:0:0, 0:0:0); + (S[0] => CO[3]) = (0:0:0, 0:0:0); + (S[0] => O[0]) = (0:0:0, 0:0:0); + (S[0] => O[1]) = (0:0:0, 0:0:0); + (S[0] => O[2]) = (0:0:0, 0:0:0); + (S[0] => O[3]) = (0:0:0, 0:0:0); + (S[1] => CO[0]) = (0:0:0, 0:0:0); + (S[1] => CO[1]) = (0:0:0, 0:0:0); + (S[1] => CO[2]) = (0:0:0, 0:0:0); + (S[1] => CO[3]) = (0:0:0, 0:0:0); + (S[1] => O[0]) = (0:0:0, 0:0:0); + (S[1] => O[1]) = (0:0:0, 0:0:0); + (S[1] => O[2]) = (0:0:0, 0:0:0); + (S[1] => O[3]) = (0:0:0, 0:0:0); + (S[2] => CO[0]) = (0:0:0, 0:0:0); + (S[2] => CO[1]) = (0:0:0, 0:0:0); + (S[2] => CO[2]) = (0:0:0, 0:0:0); + (S[2] => CO[3]) = (0:0:0, 0:0:0); + (S[2] => O[0]) = (0:0:0, 0:0:0); + (S[2] => O[1]) = (0:0:0, 0:0:0); + (S[2] => O[2]) = (0:0:0, 0:0:0); + (S[2] => O[3]) = (0:0:0, 0:0:0); + (S[3] => CO[0]) = (0:0:0, 0:0:0); + (S[3] => CO[1]) = (0:0:0, 0:0:0); + (S[3] => CO[2]) = (0:0:0, 0:0:0); + (S[3] => CO[3]) = (0:0:0, 0:0:0); + (S[3] => O[0]) = (0:0:0, 0:0:0); + (S[3] => O[1]) = (0:0:0, 0:0:0); + (S[3] => O[2]) = (0:0:0, 0:0:0); + (S[3] => O[3]) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/CARRY8.v b/verilog/src/unisims/CARRY8.v new file mode 100644 index 0000000..c8a4112 --- /dev/null +++ b/verilog/src/unisims/CARRY8.v @@ -0,0 +1,322 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Fast Carry Logic with Look Ahead +// /___/ /\ Filename : CARRY8.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision +// 09/26/12 - Initial functional version. +// 05/24/13 - Add CARRY_TYPE, CI_TOP +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module CARRY8 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CARRY_TYPE = "SINGLE_CY8" +)( + output [7:0] CO, + output [7:0] O, + + input CI, + input CI_TOP, + input [7:0] DI, + input [7:0] S +); + +// define constants + localparam MODULE_NAME = "CARRY8"; + +// Parameter encodings and registers + localparam CARRY_TYPE_DUAL_CY4 = 1; + localparam CARRY_TYPE_SINGLE_CY8 = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "CARRY8_dr.v" +`else + reg [80:1] CARRY_TYPE_REG = CARRY_TYPE; +`endif + +`ifdef XIL_XECLIB + wire CARRY_TYPE_BIN; +`else + reg CARRY_TYPE_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire CI_TOP_in; + wire CI_in; + wire [7:0] DI_in; + wire [7:0] S_in; + + + assign CI_TOP_in = ((CI_TOP !== 1'bz) && + ((CARRY_TYPE_BIN == CARRY_TYPE_DUAL_CY4) && CI_TOP)) || + ((CARRY_TYPE_BIN == CARRY_TYPE_SINGLE_CY8) && CO[3]); // rv 0 + assign CI_in = (CI !== 1'bz) && CI; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0 + assign S_in[7] = (S[7] !== 1'bz) && S[7]; // rv 0 + assign S_in[6] = (S[6] !== 1'bz) && S[6]; // rv 0 + assign S_in[5] = (S[5] !== 1'bz) && S[5]; // rv 0 + assign S_in[4] = (S[4] !== 1'bz) && S[4]; // rv 0 + assign S_in[3] = (S[3] !== 1'bz) && S[3]; // rv 0 + assign S_in[2] = (S[2] !== 1'bz) && S[2]; // rv 0 + assign S_in[1] = (S[1] !== 1'bz) && S[1]; // rv 0 + assign S_in[0] = (S[0] !== 1'bz) && S[0]; // rv 0 + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CARRY_TYPE_BIN = + (CARRY_TYPE_REG == "SINGLE_CY8") ? CARRY_TYPE_SINGLE_CY8 : + (CARRY_TYPE_REG == "DUAL_CY4") ? CARRY_TYPE_DUAL_CY4 : + CARRY_TYPE_SINGLE_CY8; + +`else + always @(trig_attr) begin + #1; + CARRY_TYPE_BIN = + (CARRY_TYPE_REG == "SINGLE_CY8") ? CARRY_TYPE_SINGLE_CY8 : + (CARRY_TYPE_REG == "DUAL_CY4") ? CARRY_TYPE_DUAL_CY4 : + CARRY_TYPE_SINGLE_CY8; + + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CARRY_TYPE_REG != "SINGLE_CY8") && + (CARRY_TYPE_REG != "DUAL_CY4"))) begin + $display("Error: [Unisim %s-101] CARRY_TYPE attribute is set to %s. Legal values for this attribute are SINGLE_CY8 or DUAL_CY4. Instance: %m", MODULE_NAME, CARRY_TYPE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + + wire [7:0] CO_fb; + assign CO_fb = {CO[6:4], CI_TOP_in, CO[2:0], CI_in}; + assign O = S_in ^ CO_fb; + assign CO = (S_in & CO_fb) | (~S_in & DI_in); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (CI => CO[0]) = (0:0:0, 0:0:0); + (CI => CO[1]) = (0:0:0, 0:0:0); + (CI => CO[2]) = (0:0:0, 0:0:0); + (CI => CO[3]) = (0:0:0, 0:0:0); + (CI => CO[4]) = (0:0:0, 0:0:0); + (CI => CO[5]) = (0:0:0, 0:0:0); + (CI => CO[6]) = (0:0:0, 0:0:0); + (CI => CO[7]) = (0:0:0, 0:0:0); + (CI => O[0]) = (0:0:0, 0:0:0); + (CI => O[1]) = (0:0:0, 0:0:0); + (CI => O[2]) = (0:0:0, 0:0:0); + (CI => O[3]) = (0:0:0, 0:0:0); + (CI => O[4]) = (0:0:0, 0:0:0); + (CI => O[5]) = (0:0:0, 0:0:0); + (CI => O[6]) = (0:0:0, 0:0:0); + (CI => O[7]) = (0:0:0, 0:0:0); + (CI_TOP => CO[4]) = (0:0:0, 0:0:0); + (CI_TOP => CO[5]) = (0:0:0, 0:0:0); + (CI_TOP => CO[6]) = (0:0:0, 0:0:0); + (CI_TOP => CO[7]) = (0:0:0, 0:0:0); + (CI_TOP => O[4]) = (0:0:0, 0:0:0); + (CI_TOP => O[5]) = (0:0:0, 0:0:0); + (CI_TOP => O[6]) = (0:0:0, 0:0:0); + (CI_TOP => O[7]) = (0:0:0, 0:0:0); + (DI[0] => CO[0]) = (0:0:0, 0:0:0); + (DI[0] => CO[1]) = (0:0:0, 0:0:0); + (DI[0] => CO[2]) = (0:0:0, 0:0:0); + (DI[0] => CO[3]) = (0:0:0, 0:0:0); + (DI[0] => CO[4]) = (0:0:0, 0:0:0); + (DI[0] => CO[5]) = (0:0:0, 0:0:0); + (DI[0] => CO[6]) = (0:0:0, 0:0:0); + (DI[0] => CO[7]) = (0:0:0, 0:0:0); + (DI[0] => O[0]) = (0:0:0, 0:0:0); + (DI[0] => O[1]) = (0:0:0, 0:0:0); + (DI[0] => O[2]) = (0:0:0, 0:0:0); + (DI[0] => O[3]) = (0:0:0, 0:0:0); + (DI[0] => O[4]) = (0:0:0, 0:0:0); + (DI[0] => O[5]) = (0:0:0, 0:0:0); + (DI[0] => O[6]) = (0:0:0, 0:0:0); + (DI[0] => O[7]) = (0:0:0, 0:0:0); + (DI[1] => CO[1]) = (0:0:0, 0:0:0); + (DI[1] => CO[2]) = (0:0:0, 0:0:0); + (DI[1] => CO[3]) = (0:0:0, 0:0:0); + (DI[1] => CO[4]) = (0:0:0, 0:0:0); + (DI[1] => CO[5]) = (0:0:0, 0:0:0); + (DI[1] => CO[6]) = (0:0:0, 0:0:0); + (DI[1] => CO[7]) = (0:0:0, 0:0:0); + (DI[1] => O[2]) = (0:0:0, 0:0:0); + (DI[1] => O[3]) = (0:0:0, 0:0:0); + (DI[1] => O[4]) = (0:0:0, 0:0:0); + (DI[1] => O[5]) = (0:0:0, 0:0:0); + (DI[1] => O[6]) = (0:0:0, 0:0:0); + (DI[1] => O[7]) = (0:0:0, 0:0:0); + (DI[2] => CO[2]) = (0:0:0, 0:0:0); + (DI[2] => CO[3]) = (0:0:0, 0:0:0); + (DI[2] => CO[4]) = (0:0:0, 0:0:0); + (DI[2] => CO[5]) = (0:0:0, 0:0:0); + (DI[2] => CO[6]) = (0:0:0, 0:0:0); + (DI[2] => CO[7]) = (0:0:0, 0:0:0); + (DI[2] => O[3]) = (0:0:0, 0:0:0); + (DI[2] => O[4]) = (0:0:0, 0:0:0); + (DI[2] => O[5]) = (0:0:0, 0:0:0); + (DI[2] => O[6]) = (0:0:0, 0:0:0); + (DI[2] => O[7]) = (0:0:0, 0:0:0); + (DI[3] => CO[3]) = (0:0:0, 0:0:0); + (DI[3] => CO[4]) = (0:0:0, 0:0:0); + (DI[3] => CO[5]) = (0:0:0, 0:0:0); + (DI[3] => CO[6]) = (0:0:0, 0:0:0); + (DI[3] => CO[7]) = (0:0:0, 0:0:0); + (DI[3] => O[4]) = (0:0:0, 0:0:0); + (DI[3] => O[5]) = (0:0:0, 0:0:0); + (DI[3] => O[6]) = (0:0:0, 0:0:0); + (DI[3] => O[7]) = (0:0:0, 0:0:0); + (DI[4] => CO[4]) = (0:0:0, 0:0:0); + (DI[4] => CO[5]) = (0:0:0, 0:0:0); + (DI[4] => CO[6]) = (0:0:0, 0:0:0); + (DI[4] => CO[7]) = (0:0:0, 0:0:0); + (DI[4] => O[5]) = (0:0:0, 0:0:0); + (DI[4] => O[6]) = (0:0:0, 0:0:0); + (DI[4] => O[7]) = (0:0:0, 0:0:0); + (DI[5] => CO[5]) = (0:0:0, 0:0:0); + (DI[5] => CO[6]) = (0:0:0, 0:0:0); + (DI[5] => CO[7]) = (0:0:0, 0:0:0); + (DI[5] => O[6]) = (0:0:0, 0:0:0); + (DI[5] => O[7]) = (0:0:0, 0:0:0); + (DI[6] => CO[6]) = (0:0:0, 0:0:0); + (DI[6] => CO[7]) = (0:0:0, 0:0:0); + (DI[6] => O[7]) = (0:0:0, 0:0:0); + (DI[7] => CO[7]) = (0:0:0, 0:0:0); + (S[0] => CO[0]) = (0:0:0, 0:0:0); + (S[0] => CO[1]) = (0:0:0, 0:0:0); + (S[0] => CO[2]) = (0:0:0, 0:0:0); + (S[0] => CO[3]) = (0:0:0, 0:0:0); + (S[0] => CO[4]) = (0:0:0, 0:0:0); + (S[0] => CO[5]) = (0:0:0, 0:0:0); + (S[0] => CO[6]) = (0:0:0, 0:0:0); + (S[0] => CO[7]) = (0:0:0, 0:0:0); + (S[0] => O[0]) = (0:0:0, 0:0:0); + (S[0] => O[1]) = (0:0:0, 0:0:0); + (S[0] => O[2]) = (0:0:0, 0:0:0); + (S[0] => O[3]) = (0:0:0, 0:0:0); + (S[0] => O[4]) = (0:0:0, 0:0:0); + (S[0] => O[5]) = (0:0:0, 0:0:0); + (S[0] => O[6]) = (0:0:0, 0:0:0); + (S[0] => O[7]) = (0:0:0, 0:0:0); + (S[1] => CO[1]) = (0:0:0, 0:0:0); + (S[1] => CO[2]) = (0:0:0, 0:0:0); + (S[1] => CO[3]) = (0:0:0, 0:0:0); + (S[1] => CO[4]) = (0:0:0, 0:0:0); + (S[1] => CO[5]) = (0:0:0, 0:0:0); + (S[1] => CO[6]) = (0:0:0, 0:0:0); + (S[1] => CO[7]) = (0:0:0, 0:0:0); + (S[1] => O[1]) = (0:0:0, 0:0:0); + (S[1] => O[2]) = (0:0:0, 0:0:0); + (S[1] => O[3]) = (0:0:0, 0:0:0); + (S[1] => O[4]) = (0:0:0, 0:0:0); + (S[1] => O[5]) = (0:0:0, 0:0:0); + (S[1] => O[6]) = (0:0:0, 0:0:0); + (S[1] => O[7]) = (0:0:0, 0:0:0); + (S[2] => CO[2]) = (0:0:0, 0:0:0); + (S[2] => CO[3]) = (0:0:0, 0:0:0); + (S[2] => CO[4]) = (0:0:0, 0:0:0); + (S[2] => CO[5]) = (0:0:0, 0:0:0); + (S[2] => CO[6]) = (0:0:0, 0:0:0); + (S[2] => CO[7]) = (0:0:0, 0:0:0); + (S[2] => O[2]) = (0:0:0, 0:0:0); + (S[2] => O[3]) = (0:0:0, 0:0:0); + (S[2] => O[4]) = (0:0:0, 0:0:0); + (S[2] => O[5]) = (0:0:0, 0:0:0); + (S[2] => O[6]) = (0:0:0, 0:0:0); + (S[2] => O[7]) = (0:0:0, 0:0:0); + (S[3] => CO[3]) = (0:0:0, 0:0:0); + (S[3] => CO[4]) = (0:0:0, 0:0:0); + (S[3] => CO[5]) = (0:0:0, 0:0:0); + (S[3] => CO[6]) = (0:0:0, 0:0:0); + (S[3] => CO[7]) = (0:0:0, 0:0:0); + (S[3] => O[3]) = (0:0:0, 0:0:0); + (S[3] => O[4]) = (0:0:0, 0:0:0); + (S[3] => O[5]) = (0:0:0, 0:0:0); + (S[3] => O[6]) = (0:0:0, 0:0:0); + (S[3] => O[7]) = (0:0:0, 0:0:0); + (S[4] => CO[4]) = (0:0:0, 0:0:0); + (S[4] => CO[5]) = (0:0:0, 0:0:0); + (S[4] => CO[6]) = (0:0:0, 0:0:0); + (S[4] => CO[7]) = (0:0:0, 0:0:0); + (S[4] => O[4]) = (0:0:0, 0:0:0); + (S[4] => O[5]) = (0:0:0, 0:0:0); + (S[4] => O[6]) = (0:0:0, 0:0:0); + (S[4] => O[7]) = (0:0:0, 0:0:0); + (S[5] => CO[5]) = (0:0:0, 0:0:0); + (S[5] => CO[6]) = (0:0:0, 0:0:0); + (S[5] => CO[7]) = (0:0:0, 0:0:0); + (S[5] => O[5]) = (0:0:0, 0:0:0); + (S[5] => O[6]) = (0:0:0, 0:0:0); + (S[5] => O[7]) = (0:0:0, 0:0:0); + (S[6] => CO[6]) = (0:0:0, 0:0:0); + (S[6] => CO[7]) = (0:0:0, 0:0:0); + (S[6] => O[6]) = (0:0:0, 0:0:0); + (S[6] => O[7]) = (0:0:0, 0:0:0); + (S[7] => CO[7]) = (0:0:0, 0:0:0); + (S[7] => O[7]) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/CFGLUT5.v b/verilog/src/unisims/CFGLUT5.v new file mode 100644 index 0000000..37bb9da --- /dev/null +++ b/verilog/src/unisims/CFGLUT5.v @@ -0,0 +1,178 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : CFGLUT5.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision +// 12/27/05 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 05/13/13 - add IS_CLK_INVERTED +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module CFGLUT5 #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [31:0] INIT = 32'h00000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output CDO, + output O5, + output O6, + + input CDI, + input CE, + input CLK, + input I0, + input I1, + input I2, + input I3, + input I4 +); + +`ifdef XIL_TIMING + wire CDI_dly; + wire CE_dly; + wire CLK_dly; +`endif + + reg [31:0] data = INIT; + reg first_time = 1'b1; + + initial + begin + assign data = INIT; + first_time <= #100000 1'b0; +`ifdef XIL_TIMING + while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`else + while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`endif + deassign data; + end + +`ifdef XIL_TIMING +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK_dly) begin + if (CE_dly == 1'b1) begin + data[31:0] <= {data[30:0], CDI_dly}; + end + end +end else begin : generate_block1 + always @(negedge CLK_dly) begin + if (CE_dly == 1'b1) begin + data[31:0] <= {data[30:0], CDI_dly}; + end + end +end +endgenerate +`else +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK) begin + if (CE == 1'b1) begin + data[31:0] <= {data[30:0], CDI}; + end + end +end else begin : generate_block1 + always @(negedge CLK) begin + if (CE == 1'b1) begin + data[31:0] <= {data[30:0], CDI}; + end + end +end +endgenerate +`endif + + assign O6 = data[{I4,I3,I2,I1,I0}]; + assign O5 = data[{1'b0,I3,I2,I1,I0}]; + assign CDO = data[31]; + +`ifdef XIL_TIMING + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_ce_clk_en_p; + wire sh_ce_clk_en_n; + + always @(notifier) + data[0] = 1'bx; + + assign sh_clk_en_p = ~IS_CLK_INVERTED; + assign sh_clk_en_n = IS_CLK_INVERTED; + assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED; + assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED; +`endif + + specify + (CLK => CDO) = (100:100:100, 100:100:100); + (CLK => O5) = (100:100:100, 100:100:100); + (CLK => O6) = (100:100:100, 100:100:100); + (I0 => CDO) = (0:0:0, 0:0:0); + (I0 => O5) = (0:0:0, 0:0:0); + (I0 => O6) = (0:0:0, 0:0:0); + (I1 => CDO) = (0:0:0, 0:0:0); + (I1 => O5) = (0:0:0, 0:0:0); + (I1 => O6) = (0:0:0, 0:0:0); + (I2 => CDO) = (0:0:0, 0:0:0); + (I2 => O5) = (0:0:0, 0:0:0); + (I2 => O6) = (0:0:0, 0:0:0); + (I3 => CDO) = (0:0:0, 0:0:0); + (I3 => O5) = (0:0:0, 0:0:0); + (I3 => O6) = (0:0:0, 0:0:0); + (I4 => CDO) = (0:0:0, 0:0:0); + (I4 => O5) = (0:0:0, 0:0:0); + (I4 => O6) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/CMAC.v b/verilog/src/unisims/CMAC.v new file mode 100644 index 0000000..5059f9f --- /dev/null +++ b/verilog/src/unisims/CMAC.v @@ -0,0 +1,8809 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 100G MAC Block +// /___/ /\ Filename : CMAC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module CMAC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE", + parameter CTL_RX_CHECK_ACK = "TRUE", + parameter CTL_RX_CHECK_PREAMBLE = "FALSE", + parameter CTL_RX_CHECK_SFD = "FALSE", + parameter CTL_RX_DELETE_FCS = "TRUE", + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808, + parameter CTL_RX_FORWARD_CONTROL = "FALSE", + parameter CTL_RX_IGNORE_FCS = "FALSE", + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580, + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40, + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001, + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF, + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF, + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000, + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000, + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001, + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001, + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000, + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000, + parameter CTL_RX_PROCESS_LFI = "FALSE", + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF, + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00, + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100, + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600, + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00, + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00, + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200, + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500, + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200, + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300, + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800, + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500, + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00, + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700, + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400, + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600, + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00, + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900, + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900, + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900, + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400, + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE", + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001, + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001, + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808, + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808, + parameter CTL_TX_FCS_INS_ENABLE = "TRUE", + parameter CTL_TX_IGNORE_FCS = "FALSE", + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001, + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001, + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE", + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1, + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000, + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000, + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF, + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00, + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100, + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600, + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00, + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00, + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200, + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500, + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200, + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300, + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800, + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500, + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00, + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700, + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400, + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600, + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00, + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900, + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900, + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900, + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400, + parameter SIM_VERSION = "2.0", + parameter TEST_MODE_PIN_CHAR = "FALSE" +)( + output [15:0] DRP_DO, + output DRP_RDY, + output [127:0] RX_DATAOUT0, + output [127:0] RX_DATAOUT1, + output [127:0] RX_DATAOUT2, + output [127:0] RX_DATAOUT3, + output RX_ENAOUT0, + output RX_ENAOUT1, + output RX_ENAOUT2, + output RX_ENAOUT3, + output RX_EOPOUT0, + output RX_EOPOUT1, + output RX_EOPOUT2, + output RX_EOPOUT3, + output RX_ERROUT0, + output RX_ERROUT1, + output RX_ERROUT2, + output RX_ERROUT3, + output [6:0] RX_LANE_ALIGNER_FILL_0, + output [6:0] RX_LANE_ALIGNER_FILL_1, + output [6:0] RX_LANE_ALIGNER_FILL_10, + output [6:0] RX_LANE_ALIGNER_FILL_11, + output [6:0] RX_LANE_ALIGNER_FILL_12, + output [6:0] RX_LANE_ALIGNER_FILL_13, + output [6:0] RX_LANE_ALIGNER_FILL_14, + output [6:0] RX_LANE_ALIGNER_FILL_15, + output [6:0] RX_LANE_ALIGNER_FILL_16, + output [6:0] RX_LANE_ALIGNER_FILL_17, + output [6:0] RX_LANE_ALIGNER_FILL_18, + output [6:0] RX_LANE_ALIGNER_FILL_19, + output [6:0] RX_LANE_ALIGNER_FILL_2, + output [6:0] RX_LANE_ALIGNER_FILL_3, + output [6:0] RX_LANE_ALIGNER_FILL_4, + output [6:0] RX_LANE_ALIGNER_FILL_5, + output [6:0] RX_LANE_ALIGNER_FILL_6, + output [6:0] RX_LANE_ALIGNER_FILL_7, + output [6:0] RX_LANE_ALIGNER_FILL_8, + output [6:0] RX_LANE_ALIGNER_FILL_9, + output [3:0] RX_MTYOUT0, + output [3:0] RX_MTYOUT1, + output [3:0] RX_MTYOUT2, + output [3:0] RX_MTYOUT3, + output [4:0] RX_PTP_PCSLANE_OUT, + output [79:0] RX_PTP_TSTAMP_OUT, + output RX_SOPOUT0, + output RX_SOPOUT1, + output RX_SOPOUT2, + output RX_SOPOUT3, + output STAT_RX_ALIGNED, + output STAT_RX_ALIGNED_ERR, + output [6:0] STAT_RX_BAD_CODE, + output [3:0] STAT_RX_BAD_FCS, + output STAT_RX_BAD_PREAMBLE, + output STAT_RX_BAD_SFD, + output STAT_RX_BIP_ERR_0, + output STAT_RX_BIP_ERR_1, + output STAT_RX_BIP_ERR_10, + output STAT_RX_BIP_ERR_11, + output STAT_RX_BIP_ERR_12, + output STAT_RX_BIP_ERR_13, + output STAT_RX_BIP_ERR_14, + output STAT_RX_BIP_ERR_15, + output STAT_RX_BIP_ERR_16, + output STAT_RX_BIP_ERR_17, + output STAT_RX_BIP_ERR_18, + output STAT_RX_BIP_ERR_19, + output STAT_RX_BIP_ERR_2, + output STAT_RX_BIP_ERR_3, + output STAT_RX_BIP_ERR_4, + output STAT_RX_BIP_ERR_5, + output STAT_RX_BIP_ERR_6, + output STAT_RX_BIP_ERR_7, + output STAT_RX_BIP_ERR_8, + output STAT_RX_BIP_ERR_9, + output [19:0] STAT_RX_BLOCK_LOCK, + output STAT_RX_BROADCAST, + output [3:0] STAT_RX_FRAGMENT, + output [3:0] STAT_RX_FRAMING_ERR_0, + output [3:0] STAT_RX_FRAMING_ERR_1, + output [3:0] STAT_RX_FRAMING_ERR_10, + output [3:0] STAT_RX_FRAMING_ERR_11, + output [3:0] STAT_RX_FRAMING_ERR_12, + output [3:0] STAT_RX_FRAMING_ERR_13, + output [3:0] STAT_RX_FRAMING_ERR_14, + output [3:0] STAT_RX_FRAMING_ERR_15, + output [3:0] STAT_RX_FRAMING_ERR_16, + output [3:0] STAT_RX_FRAMING_ERR_17, + output [3:0] STAT_RX_FRAMING_ERR_18, + output [3:0] STAT_RX_FRAMING_ERR_19, + output [3:0] STAT_RX_FRAMING_ERR_2, + output [3:0] STAT_RX_FRAMING_ERR_3, + output [3:0] STAT_RX_FRAMING_ERR_4, + output [3:0] STAT_RX_FRAMING_ERR_5, + output [3:0] STAT_RX_FRAMING_ERR_6, + output [3:0] STAT_RX_FRAMING_ERR_7, + output [3:0] STAT_RX_FRAMING_ERR_8, + output [3:0] STAT_RX_FRAMING_ERR_9, + output STAT_RX_FRAMING_ERR_VALID_0, + output STAT_RX_FRAMING_ERR_VALID_1, + output STAT_RX_FRAMING_ERR_VALID_10, + output STAT_RX_FRAMING_ERR_VALID_11, + output STAT_RX_FRAMING_ERR_VALID_12, + output STAT_RX_FRAMING_ERR_VALID_13, + output STAT_RX_FRAMING_ERR_VALID_14, + output STAT_RX_FRAMING_ERR_VALID_15, + output STAT_RX_FRAMING_ERR_VALID_16, + output STAT_RX_FRAMING_ERR_VALID_17, + output STAT_RX_FRAMING_ERR_VALID_18, + output STAT_RX_FRAMING_ERR_VALID_19, + output STAT_RX_FRAMING_ERR_VALID_2, + output STAT_RX_FRAMING_ERR_VALID_3, + output STAT_RX_FRAMING_ERR_VALID_4, + output STAT_RX_FRAMING_ERR_VALID_5, + output STAT_RX_FRAMING_ERR_VALID_6, + output STAT_RX_FRAMING_ERR_VALID_7, + output STAT_RX_FRAMING_ERR_VALID_8, + output STAT_RX_FRAMING_ERR_VALID_9, + output STAT_RX_GOT_SIGNAL_OS, + output STAT_RX_HI_BER, + output STAT_RX_INRANGEERR, + output STAT_RX_INTERNAL_LOCAL_FAULT, + output STAT_RX_JABBER, + output [7:0] STAT_RX_LANE0_VLM_BIP7, + output STAT_RX_LANE0_VLM_BIP7_VALID, + output STAT_RX_LOCAL_FAULT, + output [19:0] STAT_RX_MF_ERR, + output [19:0] STAT_RX_MF_LEN_ERR, + output [19:0] STAT_RX_MF_REPEAT_ERR, + output STAT_RX_MISALIGNED, + output STAT_RX_MULTICAST, + output STAT_RX_OVERSIZE, + output STAT_RX_PACKET_1024_1518_BYTES, + output STAT_RX_PACKET_128_255_BYTES, + output STAT_RX_PACKET_1519_1522_BYTES, + output STAT_RX_PACKET_1523_1548_BYTES, + output STAT_RX_PACKET_1549_2047_BYTES, + output STAT_RX_PACKET_2048_4095_BYTES, + output STAT_RX_PACKET_256_511_BYTES, + output STAT_RX_PACKET_4096_8191_BYTES, + output STAT_RX_PACKET_512_1023_BYTES, + output STAT_RX_PACKET_64_BYTES, + output STAT_RX_PACKET_65_127_BYTES, + output STAT_RX_PACKET_8192_9215_BYTES, + output STAT_RX_PACKET_BAD_FCS, + output STAT_RX_PACKET_LARGE, + output [3:0] STAT_RX_PACKET_SMALL, + output STAT_RX_PAUSE, + output [15:0] STAT_RX_PAUSE_QUANTA0, + output [15:0] STAT_RX_PAUSE_QUANTA1, + output [15:0] STAT_RX_PAUSE_QUANTA2, + output [15:0] STAT_RX_PAUSE_QUANTA3, + output [15:0] STAT_RX_PAUSE_QUANTA4, + output [15:0] STAT_RX_PAUSE_QUANTA5, + output [15:0] STAT_RX_PAUSE_QUANTA6, + output [15:0] STAT_RX_PAUSE_QUANTA7, + output [15:0] STAT_RX_PAUSE_QUANTA8, + output [8:0] STAT_RX_PAUSE_REQ, + output [8:0] STAT_RX_PAUSE_VALID, + output STAT_RX_RECEIVED_LOCAL_FAULT, + output STAT_RX_REMOTE_FAULT, + output STAT_RX_STATUS, + output [3:0] STAT_RX_STOMPED_FCS, + output [19:0] STAT_RX_SYNCED, + output [19:0] STAT_RX_SYNCED_ERR, + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH, + output STAT_RX_TOOLONG, + output [7:0] STAT_RX_TOTAL_BYTES, + output [13:0] STAT_RX_TOTAL_GOOD_BYTES, + output STAT_RX_TOTAL_GOOD_PACKETS, + output [3:0] STAT_RX_TOTAL_PACKETS, + output STAT_RX_TRUNCATED, + output [3:0] STAT_RX_UNDERSIZE, + output STAT_RX_UNICAST, + output STAT_RX_USER_PAUSE, + output STAT_RX_VLAN, + output [19:0] STAT_RX_VL_DEMUXED, + output [4:0] STAT_RX_VL_NUMBER_0, + output [4:0] STAT_RX_VL_NUMBER_1, + output [4:0] STAT_RX_VL_NUMBER_10, + output [4:0] STAT_RX_VL_NUMBER_11, + output [4:0] STAT_RX_VL_NUMBER_12, + output [4:0] STAT_RX_VL_NUMBER_13, + output [4:0] STAT_RX_VL_NUMBER_14, + output [4:0] STAT_RX_VL_NUMBER_15, + output [4:0] STAT_RX_VL_NUMBER_16, + output [4:0] STAT_RX_VL_NUMBER_17, + output [4:0] STAT_RX_VL_NUMBER_18, + output [4:0] STAT_RX_VL_NUMBER_19, + output [4:0] STAT_RX_VL_NUMBER_2, + output [4:0] STAT_RX_VL_NUMBER_3, + output [4:0] STAT_RX_VL_NUMBER_4, + output [4:0] STAT_RX_VL_NUMBER_5, + output [4:0] STAT_RX_VL_NUMBER_6, + output [4:0] STAT_RX_VL_NUMBER_7, + output [4:0] STAT_RX_VL_NUMBER_8, + output [4:0] STAT_RX_VL_NUMBER_9, + output STAT_TX_BAD_FCS, + output STAT_TX_BROADCAST, + output STAT_TX_FRAME_ERROR, + output STAT_TX_LOCAL_FAULT, + output STAT_TX_MULTICAST, + output STAT_TX_PACKET_1024_1518_BYTES, + output STAT_TX_PACKET_128_255_BYTES, + output STAT_TX_PACKET_1519_1522_BYTES, + output STAT_TX_PACKET_1523_1548_BYTES, + output STAT_TX_PACKET_1549_2047_BYTES, + output STAT_TX_PACKET_2048_4095_BYTES, + output STAT_TX_PACKET_256_511_BYTES, + output STAT_TX_PACKET_4096_8191_BYTES, + output STAT_TX_PACKET_512_1023_BYTES, + output STAT_TX_PACKET_64_BYTES, + output STAT_TX_PACKET_65_127_BYTES, + output STAT_TX_PACKET_8192_9215_BYTES, + output STAT_TX_PACKET_LARGE, + output STAT_TX_PACKET_SMALL, + output STAT_TX_PAUSE, + output [8:0] STAT_TX_PAUSE_VALID, + output STAT_TX_PTP_FIFO_READ_ERROR, + output STAT_TX_PTP_FIFO_WRITE_ERROR, + output [6:0] STAT_TX_TOTAL_BYTES, + output [13:0] STAT_TX_TOTAL_GOOD_BYTES, + output STAT_TX_TOTAL_GOOD_PACKETS, + output STAT_TX_TOTAL_PACKETS, + output STAT_TX_UNICAST, + output STAT_TX_USER_PAUSE, + output STAT_TX_VLAN, + output TX_OVFOUT, + output [4:0] TX_PTP_PCSLANE_OUT, + output [79:0] TX_PTP_TSTAMP_OUT, + output [15:0] TX_PTP_TSTAMP_TAG_OUT, + output TX_PTP_TSTAMP_VALID_OUT, + output TX_RDYOUT, + output [15:0] TX_SERDES_ALT_DATA0, + output [15:0] TX_SERDES_ALT_DATA1, + output [15:0] TX_SERDES_ALT_DATA2, + output [15:0] TX_SERDES_ALT_DATA3, + output [63:0] TX_SERDES_DATA0, + output [63:0] TX_SERDES_DATA1, + output [63:0] TX_SERDES_DATA2, + output [63:0] TX_SERDES_DATA3, + output [31:0] TX_SERDES_DATA4, + output [31:0] TX_SERDES_DATA5, + output [31:0] TX_SERDES_DATA6, + output [31:0] TX_SERDES_DATA7, + output [31:0] TX_SERDES_DATA8, + output [31:0] TX_SERDES_DATA9, + output TX_UNFOUT, + + input CTL_CAUI4_MODE, + input CTL_RX_CHECK_ETYPE_GCP, + input CTL_RX_CHECK_ETYPE_GPP, + input CTL_RX_CHECK_ETYPE_PCP, + input CTL_RX_CHECK_ETYPE_PPP, + input CTL_RX_CHECK_MCAST_GCP, + input CTL_RX_CHECK_MCAST_GPP, + input CTL_RX_CHECK_MCAST_PCP, + input CTL_RX_CHECK_MCAST_PPP, + input CTL_RX_CHECK_OPCODE_GCP, + input CTL_RX_CHECK_OPCODE_GPP, + input CTL_RX_CHECK_OPCODE_PCP, + input CTL_RX_CHECK_OPCODE_PPP, + input CTL_RX_CHECK_SA_GCP, + input CTL_RX_CHECK_SA_GPP, + input CTL_RX_CHECK_SA_PCP, + input CTL_RX_CHECK_SA_PPP, + input CTL_RX_CHECK_UCAST_GCP, + input CTL_RX_CHECK_UCAST_GPP, + input CTL_RX_CHECK_UCAST_PCP, + input CTL_RX_CHECK_UCAST_PPP, + input CTL_RX_ENABLE, + input CTL_RX_ENABLE_GCP, + input CTL_RX_ENABLE_GPP, + input CTL_RX_ENABLE_PCP, + input CTL_RX_ENABLE_PPP, + input CTL_RX_FORCE_RESYNC, + input [8:0] CTL_RX_PAUSE_ACK, + input [8:0] CTL_RX_PAUSE_ENABLE, + input [79:0] CTL_RX_SYSTEMTIMERIN, + input CTL_RX_TEST_PATTERN, + input CTL_TX_ENABLE, + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE, + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, + input [8:0] CTL_TX_PAUSE_ENABLE, + input [15:0] CTL_TX_PAUSE_QUANTA0, + input [15:0] CTL_TX_PAUSE_QUANTA1, + input [15:0] CTL_TX_PAUSE_QUANTA2, + input [15:0] CTL_TX_PAUSE_QUANTA3, + input [15:0] CTL_TX_PAUSE_QUANTA4, + input [15:0] CTL_TX_PAUSE_QUANTA5, + input [15:0] CTL_TX_PAUSE_QUANTA6, + input [15:0] CTL_TX_PAUSE_QUANTA7, + input [15:0] CTL_TX_PAUSE_QUANTA8, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8, + input [8:0] CTL_TX_PAUSE_REQ, + input CTL_TX_PTP_VLANE_ADJUST_MODE, + input CTL_TX_RESEND_PAUSE, + input CTL_TX_SEND_IDLE, + input CTL_TX_SEND_RFI, + input [79:0] CTL_TX_SYSTEMTIMERIN, + input CTL_TX_TEST_PATTERN, + input [9:0] DRP_ADDR, + input DRP_CLK, + input [15:0] DRP_DI, + input DRP_EN, + input DRP_WE, + input RX_CLK, + input RX_RESET, + input [15:0] RX_SERDES_ALT_DATA0, + input [15:0] RX_SERDES_ALT_DATA1, + input [15:0] RX_SERDES_ALT_DATA2, + input [15:0] RX_SERDES_ALT_DATA3, + input [9:0] RX_SERDES_CLK, + input [63:0] RX_SERDES_DATA0, + input [63:0] RX_SERDES_DATA1, + input [63:0] RX_SERDES_DATA2, + input [63:0] RX_SERDES_DATA3, + input [31:0] RX_SERDES_DATA4, + input [31:0] RX_SERDES_DATA5, + input [31:0] RX_SERDES_DATA6, + input [31:0] RX_SERDES_DATA7, + input [31:0] RX_SERDES_DATA8, + input [31:0] RX_SERDES_DATA9, + input [9:0] RX_SERDES_RESET, + input TX_CLK, + input [127:0] TX_DATAIN0, + input [127:0] TX_DATAIN1, + input [127:0] TX_DATAIN2, + input [127:0] TX_DATAIN3, + input TX_ENAIN0, + input TX_ENAIN1, + input TX_ENAIN2, + input TX_ENAIN3, + input TX_EOPIN0, + input TX_EOPIN1, + input TX_EOPIN2, + input TX_EOPIN3, + input TX_ERRIN0, + input TX_ERRIN1, + input TX_ERRIN2, + input TX_ERRIN3, + input [3:0] TX_MTYIN0, + input [3:0] TX_MTYIN1, + input [3:0] TX_MTYIN2, + input [3:0] TX_MTYIN3, + input [1:0] TX_PTP_1588OP_IN, + input [15:0] TX_PTP_CHKSUM_OFFSET_IN, + input [63:0] TX_PTP_RXTSTAMP_IN, + input [15:0] TX_PTP_TAG_FIELD_IN, + input [15:0] TX_PTP_TSTAMP_OFFSET_IN, + input TX_PTP_UPD_CHKSUM_IN, + input TX_RESET, + input TX_SOPIN0, + input TX_SOPIN1, + input TX_SOPIN2, + input TX_SOPIN3 +); + +// define constants + localparam MODULE_NAME = "CMAC"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "CMAC_dr.v" +`else + localparam [40:1] CTL_PTP_TRANSPCLK_MODE_REG = CTL_PTP_TRANSPCLK_MODE; + localparam [40:1] CTL_RX_CHECK_ACK_REG = CTL_RX_CHECK_ACK; + localparam [40:1] CTL_RX_CHECK_PREAMBLE_REG = CTL_RX_CHECK_PREAMBLE; + localparam [40:1] CTL_RX_CHECK_SFD_REG = CTL_RX_CHECK_SFD; + localparam [40:1] CTL_RX_DELETE_FCS_REG = CTL_RX_DELETE_FCS; + localparam [15:0] CTL_RX_ETYPE_GCP_REG = CTL_RX_ETYPE_GCP; + localparam [15:0] CTL_RX_ETYPE_GPP_REG = CTL_RX_ETYPE_GPP; + localparam [15:0] CTL_RX_ETYPE_PCP_REG = CTL_RX_ETYPE_PCP; + localparam [15:0] CTL_RX_ETYPE_PPP_REG = CTL_RX_ETYPE_PPP; + localparam [40:1] CTL_RX_FORWARD_CONTROL_REG = CTL_RX_FORWARD_CONTROL; + localparam [40:1] CTL_RX_IGNORE_FCS_REG = CTL_RX_IGNORE_FCS; + localparam [14:0] CTL_RX_MAX_PACKET_LEN_REG = CTL_RX_MAX_PACKET_LEN; + localparam [7:0] CTL_RX_MIN_PACKET_LEN_REG = CTL_RX_MIN_PACKET_LEN; + localparam [15:0] CTL_RX_OPCODE_GPP_REG = CTL_RX_OPCODE_GPP; + localparam [15:0] CTL_RX_OPCODE_MAX_GCP_REG = CTL_RX_OPCODE_MAX_GCP; + localparam [15:0] CTL_RX_OPCODE_MAX_PCP_REG = CTL_RX_OPCODE_MAX_PCP; + localparam [15:0] CTL_RX_OPCODE_MIN_GCP_REG = CTL_RX_OPCODE_MIN_GCP; + localparam [15:0] CTL_RX_OPCODE_MIN_PCP_REG = CTL_RX_OPCODE_MIN_PCP; + localparam [15:0] CTL_RX_OPCODE_PPP_REG = CTL_RX_OPCODE_PPP; + localparam [47:0] CTL_RX_PAUSE_DA_MCAST_REG = CTL_RX_PAUSE_DA_MCAST; + localparam [47:0] CTL_RX_PAUSE_DA_UCAST_REG = CTL_RX_PAUSE_DA_UCAST; + localparam [47:0] CTL_RX_PAUSE_SA_REG = CTL_RX_PAUSE_SA; + localparam [40:1] CTL_RX_PROCESS_LFI_REG = CTL_RX_PROCESS_LFI; + localparam [15:0] CTL_RX_VL_LENGTH_MINUS1_REG = CTL_RX_VL_LENGTH_MINUS1; + localparam [63:0] CTL_RX_VL_MARKER_ID0_REG = CTL_RX_VL_MARKER_ID0; + localparam [63:0] CTL_RX_VL_MARKER_ID1_REG = CTL_RX_VL_MARKER_ID1; + localparam [63:0] CTL_RX_VL_MARKER_ID10_REG = CTL_RX_VL_MARKER_ID10; + localparam [63:0] CTL_RX_VL_MARKER_ID11_REG = CTL_RX_VL_MARKER_ID11; + localparam [63:0] CTL_RX_VL_MARKER_ID12_REG = CTL_RX_VL_MARKER_ID12; + localparam [63:0] CTL_RX_VL_MARKER_ID13_REG = CTL_RX_VL_MARKER_ID13; + localparam [63:0] CTL_RX_VL_MARKER_ID14_REG = CTL_RX_VL_MARKER_ID14; + localparam [63:0] CTL_RX_VL_MARKER_ID15_REG = CTL_RX_VL_MARKER_ID15; + localparam [63:0] CTL_RX_VL_MARKER_ID16_REG = CTL_RX_VL_MARKER_ID16; + localparam [63:0] CTL_RX_VL_MARKER_ID17_REG = CTL_RX_VL_MARKER_ID17; + localparam [63:0] CTL_RX_VL_MARKER_ID18_REG = CTL_RX_VL_MARKER_ID18; + localparam [63:0] CTL_RX_VL_MARKER_ID19_REG = CTL_RX_VL_MARKER_ID19; + localparam [63:0] CTL_RX_VL_MARKER_ID2_REG = CTL_RX_VL_MARKER_ID2; + localparam [63:0] CTL_RX_VL_MARKER_ID3_REG = CTL_RX_VL_MARKER_ID3; + localparam [63:0] CTL_RX_VL_MARKER_ID4_REG = CTL_RX_VL_MARKER_ID4; + localparam [63:0] CTL_RX_VL_MARKER_ID5_REG = CTL_RX_VL_MARKER_ID5; + localparam [63:0] CTL_RX_VL_MARKER_ID6_REG = CTL_RX_VL_MARKER_ID6; + localparam [63:0] CTL_RX_VL_MARKER_ID7_REG = CTL_RX_VL_MARKER_ID7; + localparam [63:0] CTL_RX_VL_MARKER_ID8_REG = CTL_RX_VL_MARKER_ID8; + localparam [63:0] CTL_RX_VL_MARKER_ID9_REG = CTL_RX_VL_MARKER_ID9; + localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR; + localparam [47:0] CTL_TX_DA_GPP_REG = CTL_TX_DA_GPP; + localparam [47:0] CTL_TX_DA_PPP_REG = CTL_TX_DA_PPP; + localparam [15:0] CTL_TX_ETHERTYPE_GPP_REG = CTL_TX_ETHERTYPE_GPP; + localparam [15:0] CTL_TX_ETHERTYPE_PPP_REG = CTL_TX_ETHERTYPE_PPP; + localparam [40:1] CTL_TX_FCS_INS_ENABLE_REG = CTL_TX_FCS_INS_ENABLE; + localparam [40:1] CTL_TX_IGNORE_FCS_REG = CTL_TX_IGNORE_FCS; + localparam [15:0] CTL_TX_OPCODE_GPP_REG = CTL_TX_OPCODE_GPP; + localparam [15:0] CTL_TX_OPCODE_PPP_REG = CTL_TX_OPCODE_PPP; + localparam [40:1] CTL_TX_PTP_1STEP_ENABLE_REG = CTL_TX_PTP_1STEP_ENABLE; + localparam [10:0] CTL_TX_PTP_LATENCY_ADJUST_REG = CTL_TX_PTP_LATENCY_ADJUST; + localparam [47:0] CTL_TX_SA_GPP_REG = CTL_TX_SA_GPP; + localparam [47:0] CTL_TX_SA_PPP_REG = CTL_TX_SA_PPP; + localparam [15:0] CTL_TX_VL_LENGTH_MINUS1_REG = CTL_TX_VL_LENGTH_MINUS1; + localparam [63:0] CTL_TX_VL_MARKER_ID0_REG = CTL_TX_VL_MARKER_ID0; + localparam [63:0] CTL_TX_VL_MARKER_ID1_REG = CTL_TX_VL_MARKER_ID1; + localparam [63:0] CTL_TX_VL_MARKER_ID10_REG = CTL_TX_VL_MARKER_ID10; + localparam [63:0] CTL_TX_VL_MARKER_ID11_REG = CTL_TX_VL_MARKER_ID11; + localparam [63:0] CTL_TX_VL_MARKER_ID12_REG = CTL_TX_VL_MARKER_ID12; + localparam [63:0] CTL_TX_VL_MARKER_ID13_REG = CTL_TX_VL_MARKER_ID13; + localparam [63:0] CTL_TX_VL_MARKER_ID14_REG = CTL_TX_VL_MARKER_ID14; + localparam [63:0] CTL_TX_VL_MARKER_ID15_REG = CTL_TX_VL_MARKER_ID15; + localparam [63:0] CTL_TX_VL_MARKER_ID16_REG = CTL_TX_VL_MARKER_ID16; + localparam [63:0] CTL_TX_VL_MARKER_ID17_REG = CTL_TX_VL_MARKER_ID17; + localparam [63:0] CTL_TX_VL_MARKER_ID18_REG = CTL_TX_VL_MARKER_ID18; + localparam [63:0] CTL_TX_VL_MARKER_ID19_REG = CTL_TX_VL_MARKER_ID19; + localparam [63:0] CTL_TX_VL_MARKER_ID2_REG = CTL_TX_VL_MARKER_ID2; + localparam [63:0] CTL_TX_VL_MARKER_ID3_REG = CTL_TX_VL_MARKER_ID3; + localparam [63:0] CTL_TX_VL_MARKER_ID4_REG = CTL_TX_VL_MARKER_ID4; + localparam [63:0] CTL_TX_VL_MARKER_ID5_REG = CTL_TX_VL_MARKER_ID5; + localparam [63:0] CTL_TX_VL_MARKER_ID6_REG = CTL_TX_VL_MARKER_ID6; + localparam [63:0] CTL_TX_VL_MARKER_ID7_REG = CTL_TX_VL_MARKER_ID7; + localparam [63:0] CTL_TX_VL_MARKER_ID8_REG = CTL_TX_VL_MARKER_ID8; + localparam [63:0] CTL_TX_VL_MARKER_ID9_REG = CTL_TX_VL_MARKER_ID9; + localparam [24:1] SIM_VERSION_REG = SIM_VERSION; + localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire DRP_RDY_out; + wire RX_ENAOUT0_out; + wire RX_ENAOUT1_out; + wire RX_ENAOUT2_out; + wire RX_ENAOUT3_out; + wire RX_EOPOUT0_out; + wire RX_EOPOUT1_out; + wire RX_EOPOUT2_out; + wire RX_EOPOUT3_out; + wire RX_ERROUT0_out; + wire RX_ERROUT1_out; + wire RX_ERROUT2_out; + wire RX_ERROUT3_out; + wire RX_SOPOUT0_out; + wire RX_SOPOUT1_out; + wire RX_SOPOUT2_out; + wire RX_SOPOUT3_out; + wire STAT_RX_ALIGNED_ERR_out; + wire STAT_RX_ALIGNED_out; + wire STAT_RX_BAD_PREAMBLE_out; + wire STAT_RX_BAD_SFD_out; + wire STAT_RX_BIP_ERR_0_out; + wire STAT_RX_BIP_ERR_10_out; + wire STAT_RX_BIP_ERR_11_out; + wire STAT_RX_BIP_ERR_12_out; + wire STAT_RX_BIP_ERR_13_out; + wire STAT_RX_BIP_ERR_14_out; + wire STAT_RX_BIP_ERR_15_out; + wire STAT_RX_BIP_ERR_16_out; + wire STAT_RX_BIP_ERR_17_out; + wire STAT_RX_BIP_ERR_18_out; + wire STAT_RX_BIP_ERR_19_out; + wire STAT_RX_BIP_ERR_1_out; + wire STAT_RX_BIP_ERR_2_out; + wire STAT_RX_BIP_ERR_3_out; + wire STAT_RX_BIP_ERR_4_out; + wire STAT_RX_BIP_ERR_5_out; + wire STAT_RX_BIP_ERR_6_out; + wire STAT_RX_BIP_ERR_7_out; + wire STAT_RX_BIP_ERR_8_out; + wire STAT_RX_BIP_ERR_9_out; + wire STAT_RX_BROADCAST_out; + wire STAT_RX_FRAMING_ERR_VALID_0_out; + wire STAT_RX_FRAMING_ERR_VALID_10_out; + wire STAT_RX_FRAMING_ERR_VALID_11_out; + wire STAT_RX_FRAMING_ERR_VALID_12_out; + wire STAT_RX_FRAMING_ERR_VALID_13_out; + wire STAT_RX_FRAMING_ERR_VALID_14_out; + wire STAT_RX_FRAMING_ERR_VALID_15_out; + wire STAT_RX_FRAMING_ERR_VALID_16_out; + wire STAT_RX_FRAMING_ERR_VALID_17_out; + wire STAT_RX_FRAMING_ERR_VALID_18_out; + wire STAT_RX_FRAMING_ERR_VALID_19_out; + wire STAT_RX_FRAMING_ERR_VALID_1_out; + wire STAT_RX_FRAMING_ERR_VALID_2_out; + wire STAT_RX_FRAMING_ERR_VALID_3_out; + wire STAT_RX_FRAMING_ERR_VALID_4_out; + wire STAT_RX_FRAMING_ERR_VALID_5_out; + wire STAT_RX_FRAMING_ERR_VALID_6_out; + wire STAT_RX_FRAMING_ERR_VALID_7_out; + wire STAT_RX_FRAMING_ERR_VALID_8_out; + wire STAT_RX_FRAMING_ERR_VALID_9_out; + wire STAT_RX_GOT_SIGNAL_OS_out; + wire STAT_RX_HI_BER_out; + wire STAT_RX_INRANGEERR_out; + wire STAT_RX_INTERNAL_LOCAL_FAULT_out; + wire STAT_RX_JABBER_out; + wire STAT_RX_LANE0_VLM_BIP7_VALID_out; + wire STAT_RX_LOCAL_FAULT_out; + wire STAT_RX_MISALIGNED_out; + wire STAT_RX_MULTICAST_out; + wire STAT_RX_OVERSIZE_out; + wire STAT_RX_PACKET_1024_1518_BYTES_out; + wire STAT_RX_PACKET_128_255_BYTES_out; + wire STAT_RX_PACKET_1519_1522_BYTES_out; + wire STAT_RX_PACKET_1523_1548_BYTES_out; + wire STAT_RX_PACKET_1549_2047_BYTES_out; + wire STAT_RX_PACKET_2048_4095_BYTES_out; + wire STAT_RX_PACKET_256_511_BYTES_out; + wire STAT_RX_PACKET_4096_8191_BYTES_out; + wire STAT_RX_PACKET_512_1023_BYTES_out; + wire STAT_RX_PACKET_64_BYTES_out; + wire STAT_RX_PACKET_65_127_BYTES_out; + wire STAT_RX_PACKET_8192_9215_BYTES_out; + wire STAT_RX_PACKET_BAD_FCS_out; + wire STAT_RX_PACKET_LARGE_out; + wire STAT_RX_PAUSE_out; + wire STAT_RX_RECEIVED_LOCAL_FAULT_out; + wire STAT_RX_REMOTE_FAULT_out; + wire STAT_RX_STATUS_out; + wire STAT_RX_TOOLONG_out; + wire STAT_RX_TOTAL_GOOD_PACKETS_out; + wire STAT_RX_TRUNCATED_out; + wire STAT_RX_UNICAST_out; + wire STAT_RX_USER_PAUSE_out; + wire STAT_RX_VLAN_out; + wire STAT_TX_BAD_FCS_out; + wire STAT_TX_BROADCAST_out; + wire STAT_TX_FRAME_ERROR_out; + wire STAT_TX_LOCAL_FAULT_out; + wire STAT_TX_MULTICAST_out; + wire STAT_TX_PACKET_1024_1518_BYTES_out; + wire STAT_TX_PACKET_128_255_BYTES_out; + wire STAT_TX_PACKET_1519_1522_BYTES_out; + wire STAT_TX_PACKET_1523_1548_BYTES_out; + wire STAT_TX_PACKET_1549_2047_BYTES_out; + wire STAT_TX_PACKET_2048_4095_BYTES_out; + wire STAT_TX_PACKET_256_511_BYTES_out; + wire STAT_TX_PACKET_4096_8191_BYTES_out; + wire STAT_TX_PACKET_512_1023_BYTES_out; + wire STAT_TX_PACKET_64_BYTES_out; + wire STAT_TX_PACKET_65_127_BYTES_out; + wire STAT_TX_PACKET_8192_9215_BYTES_out; + wire STAT_TX_PACKET_LARGE_out; + wire STAT_TX_PACKET_SMALL_out; + wire STAT_TX_PAUSE_out; + wire STAT_TX_PTP_FIFO_READ_ERROR_out; + wire STAT_TX_PTP_FIFO_WRITE_ERROR_out; + wire STAT_TX_TOTAL_GOOD_PACKETS_out; + wire STAT_TX_TOTAL_PACKETS_out; + wire STAT_TX_UNICAST_out; + wire STAT_TX_USER_PAUSE_out; + wire STAT_TX_VLAN_out; + wire TX_OVFOUT_out; + wire TX_PTP_TSTAMP_VALID_OUT_out; + wire TX_RDYOUT_out; + wire TX_UNFOUT_out; + wire [127:0] RX_DATAOUT0_out; + wire [127:0] RX_DATAOUT1_out; + wire [127:0] RX_DATAOUT2_out; + wire [127:0] RX_DATAOUT3_out; + wire [12:0] SCAN_OUT_DRPCTRL_out; + wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_out; + wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_out; + wire [15:0] DRP_DO_out; + wire [15:0] STAT_RX_PAUSE_QUANTA0_out; + wire [15:0] STAT_RX_PAUSE_QUANTA1_out; + wire [15:0] STAT_RX_PAUSE_QUANTA2_out; + wire [15:0] STAT_RX_PAUSE_QUANTA3_out; + wire [15:0] STAT_RX_PAUSE_QUANTA4_out; + wire [15:0] STAT_RX_PAUSE_QUANTA5_out; + wire [15:0] STAT_RX_PAUSE_QUANTA6_out; + wire [15:0] STAT_RX_PAUSE_QUANTA7_out; + wire [15:0] STAT_RX_PAUSE_QUANTA8_out; + wire [15:0] TX_PTP_TSTAMP_TAG_OUT_out; + wire [15:0] TX_SERDES_ALT_DATA0_out; + wire [15:0] TX_SERDES_ALT_DATA1_out; + wire [15:0] TX_SERDES_ALT_DATA2_out; + wire [15:0] TX_SERDES_ALT_DATA3_out; + wire [181:0] SCAN_OUT_CMAC_out; + wire [19:0] STAT_RX_BLOCK_LOCK_out; + wire [19:0] STAT_RX_MF_ERR_out; + wire [19:0] STAT_RX_MF_LEN_ERR_out; + wire [19:0] STAT_RX_MF_REPEAT_ERR_out; + wire [19:0] STAT_RX_SYNCED_ERR_out; + wire [19:0] STAT_RX_SYNCED_out; + wire [19:0] STAT_RX_VL_DEMUXED_out; + wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_out; + wire [31:0] TX_SERDES_DATA4_out; + wire [31:0] TX_SERDES_DATA5_out; + wire [31:0] TX_SERDES_DATA6_out; + wire [31:0] TX_SERDES_DATA7_out; + wire [31:0] TX_SERDES_DATA8_out; + wire [31:0] TX_SERDES_DATA9_out; + wire [3:0] RX_MTYOUT0_out; + wire [3:0] RX_MTYOUT1_out; + wire [3:0] RX_MTYOUT2_out; + wire [3:0] RX_MTYOUT3_out; + wire [3:0] STAT_RX_BAD_FCS_out; + wire [3:0] STAT_RX_FRAGMENT_out; + wire [3:0] STAT_RX_FRAMING_ERR_0_out; + wire [3:0] STAT_RX_FRAMING_ERR_10_out; + wire [3:0] STAT_RX_FRAMING_ERR_11_out; + wire [3:0] STAT_RX_FRAMING_ERR_12_out; + wire [3:0] STAT_RX_FRAMING_ERR_13_out; + wire [3:0] STAT_RX_FRAMING_ERR_14_out; + wire [3:0] STAT_RX_FRAMING_ERR_15_out; + wire [3:0] STAT_RX_FRAMING_ERR_16_out; + wire [3:0] STAT_RX_FRAMING_ERR_17_out; + wire [3:0] STAT_RX_FRAMING_ERR_18_out; + wire [3:0] STAT_RX_FRAMING_ERR_19_out; + wire [3:0] STAT_RX_FRAMING_ERR_1_out; + wire [3:0] STAT_RX_FRAMING_ERR_2_out; + wire [3:0] STAT_RX_FRAMING_ERR_3_out; + wire [3:0] STAT_RX_FRAMING_ERR_4_out; + wire [3:0] STAT_RX_FRAMING_ERR_5_out; + wire [3:0] STAT_RX_FRAMING_ERR_6_out; + wire [3:0] STAT_RX_FRAMING_ERR_7_out; + wire [3:0] STAT_RX_FRAMING_ERR_8_out; + wire [3:0] STAT_RX_FRAMING_ERR_9_out; + wire [3:0] STAT_RX_PACKET_SMALL_out; + wire [3:0] STAT_RX_STOMPED_FCS_out; + wire [3:0] STAT_RX_TOTAL_PACKETS_out; + wire [3:0] STAT_RX_UNDERSIZE_out; + wire [4:0] RX_PTP_PCSLANE_OUT_out; + wire [4:0] STAT_RX_VL_NUMBER_0_out; + wire [4:0] STAT_RX_VL_NUMBER_10_out; + wire [4:0] STAT_RX_VL_NUMBER_11_out; + wire [4:0] STAT_RX_VL_NUMBER_12_out; + wire [4:0] STAT_RX_VL_NUMBER_13_out; + wire [4:0] STAT_RX_VL_NUMBER_14_out; + wire [4:0] STAT_RX_VL_NUMBER_15_out; + wire [4:0] STAT_RX_VL_NUMBER_16_out; + wire [4:0] STAT_RX_VL_NUMBER_17_out; + wire [4:0] STAT_RX_VL_NUMBER_18_out; + wire [4:0] STAT_RX_VL_NUMBER_19_out; + wire [4:0] STAT_RX_VL_NUMBER_1_out; + wire [4:0] STAT_RX_VL_NUMBER_2_out; + wire [4:0] STAT_RX_VL_NUMBER_3_out; + wire [4:0] STAT_RX_VL_NUMBER_4_out; + wire [4:0] STAT_RX_VL_NUMBER_5_out; + wire [4:0] STAT_RX_VL_NUMBER_6_out; + wire [4:0] STAT_RX_VL_NUMBER_7_out; + wire [4:0] STAT_RX_VL_NUMBER_8_out; + wire [4:0] STAT_RX_VL_NUMBER_9_out; + wire [4:0] TX_PTP_PCSLANE_OUT_out; + wire [63:0] TX_SERDES_DATA0_out; + wire [63:0] TX_SERDES_DATA1_out; + wire [63:0] TX_SERDES_DATA2_out; + wire [63:0] TX_SERDES_DATA3_out; + wire [6:0] RX_LANE_ALIGNER_FILL_0_out; + wire [6:0] RX_LANE_ALIGNER_FILL_10_out; + wire [6:0] RX_LANE_ALIGNER_FILL_11_out; + wire [6:0] RX_LANE_ALIGNER_FILL_12_out; + wire [6:0] RX_LANE_ALIGNER_FILL_13_out; + wire [6:0] RX_LANE_ALIGNER_FILL_14_out; + wire [6:0] RX_LANE_ALIGNER_FILL_15_out; + wire [6:0] RX_LANE_ALIGNER_FILL_16_out; + wire [6:0] RX_LANE_ALIGNER_FILL_17_out; + wire [6:0] RX_LANE_ALIGNER_FILL_18_out; + wire [6:0] RX_LANE_ALIGNER_FILL_19_out; + wire [6:0] RX_LANE_ALIGNER_FILL_1_out; + wire [6:0] RX_LANE_ALIGNER_FILL_2_out; + wire [6:0] RX_LANE_ALIGNER_FILL_3_out; + wire [6:0] RX_LANE_ALIGNER_FILL_4_out; + wire [6:0] RX_LANE_ALIGNER_FILL_5_out; + wire [6:0] RX_LANE_ALIGNER_FILL_6_out; + wire [6:0] RX_LANE_ALIGNER_FILL_7_out; + wire [6:0] RX_LANE_ALIGNER_FILL_8_out; + wire [6:0] RX_LANE_ALIGNER_FILL_9_out; + wire [6:0] STAT_RX_BAD_CODE_out; + wire [6:0] STAT_TX_TOTAL_BYTES_out; + wire [79:0] RX_PTP_TSTAMP_OUT_out; + wire [79:0] TX_PTP_TSTAMP_OUT_out; + wire [7:0] STAT_RX_LANE0_VLM_BIP7_out; + wire [7:0] STAT_RX_TOTAL_BYTES_out; + wire [8:0] STAT_RX_PAUSE_REQ_out; + wire [8:0] STAT_RX_PAUSE_VALID_out; + wire [8:0] STAT_TX_PAUSE_VALID_out; + + wire DRP_RDY_delay; + wire RX_ENAOUT0_delay; + wire RX_ENAOUT1_delay; + wire RX_ENAOUT2_delay; + wire RX_ENAOUT3_delay; + wire RX_EOPOUT0_delay; + wire RX_EOPOUT1_delay; + wire RX_EOPOUT2_delay; + wire RX_EOPOUT3_delay; + wire RX_ERROUT0_delay; + wire RX_ERROUT1_delay; + wire RX_ERROUT2_delay; + wire RX_ERROUT3_delay; + wire RX_SOPOUT0_delay; + wire RX_SOPOUT1_delay; + wire RX_SOPOUT2_delay; + wire RX_SOPOUT3_delay; + wire STAT_RX_ALIGNED_ERR_delay; + wire STAT_RX_ALIGNED_delay; + wire STAT_RX_BAD_PREAMBLE_delay; + wire STAT_RX_BAD_SFD_delay; + wire STAT_RX_BIP_ERR_0_delay; + wire STAT_RX_BIP_ERR_10_delay; + wire STAT_RX_BIP_ERR_11_delay; + wire STAT_RX_BIP_ERR_12_delay; + wire STAT_RX_BIP_ERR_13_delay; + wire STAT_RX_BIP_ERR_14_delay; + wire STAT_RX_BIP_ERR_15_delay; + wire STAT_RX_BIP_ERR_16_delay; + wire STAT_RX_BIP_ERR_17_delay; + wire STAT_RX_BIP_ERR_18_delay; + wire STAT_RX_BIP_ERR_19_delay; + wire STAT_RX_BIP_ERR_1_delay; + wire STAT_RX_BIP_ERR_2_delay; + wire STAT_RX_BIP_ERR_3_delay; + wire STAT_RX_BIP_ERR_4_delay; + wire STAT_RX_BIP_ERR_5_delay; + wire STAT_RX_BIP_ERR_6_delay; + wire STAT_RX_BIP_ERR_7_delay; + wire STAT_RX_BIP_ERR_8_delay; + wire STAT_RX_BIP_ERR_9_delay; + wire STAT_RX_BROADCAST_delay; + wire STAT_RX_FRAMING_ERR_VALID_0_delay; + wire STAT_RX_FRAMING_ERR_VALID_10_delay; + wire STAT_RX_FRAMING_ERR_VALID_11_delay; + wire STAT_RX_FRAMING_ERR_VALID_12_delay; + wire STAT_RX_FRAMING_ERR_VALID_13_delay; + wire STAT_RX_FRAMING_ERR_VALID_14_delay; + wire STAT_RX_FRAMING_ERR_VALID_15_delay; + wire STAT_RX_FRAMING_ERR_VALID_16_delay; + wire STAT_RX_FRAMING_ERR_VALID_17_delay; + wire STAT_RX_FRAMING_ERR_VALID_18_delay; + wire STAT_RX_FRAMING_ERR_VALID_19_delay; + wire STAT_RX_FRAMING_ERR_VALID_1_delay; + wire STAT_RX_FRAMING_ERR_VALID_2_delay; + wire STAT_RX_FRAMING_ERR_VALID_3_delay; + wire STAT_RX_FRAMING_ERR_VALID_4_delay; + wire STAT_RX_FRAMING_ERR_VALID_5_delay; + wire STAT_RX_FRAMING_ERR_VALID_6_delay; + wire STAT_RX_FRAMING_ERR_VALID_7_delay; + wire STAT_RX_FRAMING_ERR_VALID_8_delay; + wire STAT_RX_FRAMING_ERR_VALID_9_delay; + wire STAT_RX_GOT_SIGNAL_OS_delay; + wire STAT_RX_HI_BER_delay; + wire STAT_RX_INRANGEERR_delay; + wire STAT_RX_INTERNAL_LOCAL_FAULT_delay; + wire STAT_RX_JABBER_delay; + wire STAT_RX_LANE0_VLM_BIP7_VALID_delay; + wire STAT_RX_LOCAL_FAULT_delay; + wire STAT_RX_MISALIGNED_delay; + wire STAT_RX_MULTICAST_delay; + wire STAT_RX_OVERSIZE_delay; + wire STAT_RX_PACKET_1024_1518_BYTES_delay; + wire STAT_RX_PACKET_128_255_BYTES_delay; + wire STAT_RX_PACKET_1519_1522_BYTES_delay; + wire STAT_RX_PACKET_1523_1548_BYTES_delay; + wire STAT_RX_PACKET_1549_2047_BYTES_delay; + wire STAT_RX_PACKET_2048_4095_BYTES_delay; + wire STAT_RX_PACKET_256_511_BYTES_delay; + wire STAT_RX_PACKET_4096_8191_BYTES_delay; + wire STAT_RX_PACKET_512_1023_BYTES_delay; + wire STAT_RX_PACKET_64_BYTES_delay; + wire STAT_RX_PACKET_65_127_BYTES_delay; + wire STAT_RX_PACKET_8192_9215_BYTES_delay; + wire STAT_RX_PACKET_BAD_FCS_delay; + wire STAT_RX_PACKET_LARGE_delay; + wire STAT_RX_PAUSE_delay; + wire STAT_RX_RECEIVED_LOCAL_FAULT_delay; + wire STAT_RX_REMOTE_FAULT_delay; + wire STAT_RX_STATUS_delay; + wire STAT_RX_TOOLONG_delay; + wire STAT_RX_TOTAL_GOOD_PACKETS_delay; + wire STAT_RX_TRUNCATED_delay; + wire STAT_RX_UNICAST_delay; + wire STAT_RX_USER_PAUSE_delay; + wire STAT_RX_VLAN_delay; + wire STAT_TX_BAD_FCS_delay; + wire STAT_TX_BROADCAST_delay; + wire STAT_TX_FRAME_ERROR_delay; + wire STAT_TX_LOCAL_FAULT_delay; + wire STAT_TX_MULTICAST_delay; + wire STAT_TX_PACKET_1024_1518_BYTES_delay; + wire STAT_TX_PACKET_128_255_BYTES_delay; + wire STAT_TX_PACKET_1519_1522_BYTES_delay; + wire STAT_TX_PACKET_1523_1548_BYTES_delay; + wire STAT_TX_PACKET_1549_2047_BYTES_delay; + wire STAT_TX_PACKET_2048_4095_BYTES_delay; + wire STAT_TX_PACKET_256_511_BYTES_delay; + wire STAT_TX_PACKET_4096_8191_BYTES_delay; + wire STAT_TX_PACKET_512_1023_BYTES_delay; + wire STAT_TX_PACKET_64_BYTES_delay; + wire STAT_TX_PACKET_65_127_BYTES_delay; + wire STAT_TX_PACKET_8192_9215_BYTES_delay; + wire STAT_TX_PACKET_LARGE_delay; + wire STAT_TX_PACKET_SMALL_delay; + wire STAT_TX_PAUSE_delay; + wire STAT_TX_PTP_FIFO_READ_ERROR_delay; + wire STAT_TX_PTP_FIFO_WRITE_ERROR_delay; + wire STAT_TX_TOTAL_GOOD_PACKETS_delay; + wire STAT_TX_TOTAL_PACKETS_delay; + wire STAT_TX_UNICAST_delay; + wire STAT_TX_USER_PAUSE_delay; + wire STAT_TX_VLAN_delay; + wire TX_OVFOUT_delay; + wire TX_PTP_TSTAMP_VALID_OUT_delay; + wire TX_RDYOUT_delay; + wire TX_UNFOUT_delay; + wire [127:0] RX_DATAOUT0_delay; + wire [127:0] RX_DATAOUT1_delay; + wire [127:0] RX_DATAOUT2_delay; + wire [127:0] RX_DATAOUT3_delay; + wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_delay; + wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_delay; + wire [15:0] DRP_DO_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA0_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA1_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA2_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA3_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA4_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA5_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA6_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA7_delay; + wire [15:0] STAT_RX_PAUSE_QUANTA8_delay; + wire [15:0] TX_PTP_TSTAMP_TAG_OUT_delay; + wire [15:0] TX_SERDES_ALT_DATA0_delay; + wire [15:0] TX_SERDES_ALT_DATA1_delay; + wire [15:0] TX_SERDES_ALT_DATA2_delay; + wire [15:0] TX_SERDES_ALT_DATA3_delay; + wire [19:0] STAT_RX_BLOCK_LOCK_delay; + wire [19:0] STAT_RX_MF_ERR_delay; + wire [19:0] STAT_RX_MF_LEN_ERR_delay; + wire [19:0] STAT_RX_MF_REPEAT_ERR_delay; + wire [19:0] STAT_RX_SYNCED_ERR_delay; + wire [19:0] STAT_RX_SYNCED_delay; + wire [19:0] STAT_RX_VL_DEMUXED_delay; + wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_delay; + wire [31:0] TX_SERDES_DATA4_delay; + wire [31:0] TX_SERDES_DATA5_delay; + wire [31:0] TX_SERDES_DATA6_delay; + wire [31:0] TX_SERDES_DATA7_delay; + wire [31:0] TX_SERDES_DATA8_delay; + wire [31:0] TX_SERDES_DATA9_delay; + wire [3:0] RX_MTYOUT0_delay; + wire [3:0] RX_MTYOUT1_delay; + wire [3:0] RX_MTYOUT2_delay; + wire [3:0] RX_MTYOUT3_delay; + wire [3:0] STAT_RX_BAD_FCS_delay; + wire [3:0] STAT_RX_FRAGMENT_delay; + wire [3:0] STAT_RX_FRAMING_ERR_0_delay; + wire [3:0] STAT_RX_FRAMING_ERR_10_delay; + wire [3:0] STAT_RX_FRAMING_ERR_11_delay; + wire [3:0] STAT_RX_FRAMING_ERR_12_delay; + wire [3:0] STAT_RX_FRAMING_ERR_13_delay; + wire [3:0] STAT_RX_FRAMING_ERR_14_delay; + wire [3:0] STAT_RX_FRAMING_ERR_15_delay; + wire [3:0] STAT_RX_FRAMING_ERR_16_delay; + wire [3:0] STAT_RX_FRAMING_ERR_17_delay; + wire [3:0] STAT_RX_FRAMING_ERR_18_delay; + wire [3:0] STAT_RX_FRAMING_ERR_19_delay; + wire [3:0] STAT_RX_FRAMING_ERR_1_delay; + wire [3:0] STAT_RX_FRAMING_ERR_2_delay; + wire [3:0] STAT_RX_FRAMING_ERR_3_delay; + wire [3:0] STAT_RX_FRAMING_ERR_4_delay; + wire [3:0] STAT_RX_FRAMING_ERR_5_delay; + wire [3:0] STAT_RX_FRAMING_ERR_6_delay; + wire [3:0] STAT_RX_FRAMING_ERR_7_delay; + wire [3:0] STAT_RX_FRAMING_ERR_8_delay; + wire [3:0] STAT_RX_FRAMING_ERR_9_delay; + wire [3:0] STAT_RX_PACKET_SMALL_delay; + wire [3:0] STAT_RX_STOMPED_FCS_delay; + wire [3:0] STAT_RX_TOTAL_PACKETS_delay; + wire [3:0] STAT_RX_UNDERSIZE_delay; + wire [4:0] RX_PTP_PCSLANE_OUT_delay; + wire [4:0] STAT_RX_VL_NUMBER_0_delay; + wire [4:0] STAT_RX_VL_NUMBER_10_delay; + wire [4:0] STAT_RX_VL_NUMBER_11_delay; + wire [4:0] STAT_RX_VL_NUMBER_12_delay; + wire [4:0] STAT_RX_VL_NUMBER_13_delay; + wire [4:0] STAT_RX_VL_NUMBER_14_delay; + wire [4:0] STAT_RX_VL_NUMBER_15_delay; + wire [4:0] STAT_RX_VL_NUMBER_16_delay; + wire [4:0] STAT_RX_VL_NUMBER_17_delay; + wire [4:0] STAT_RX_VL_NUMBER_18_delay; + wire [4:0] STAT_RX_VL_NUMBER_19_delay; + wire [4:0] STAT_RX_VL_NUMBER_1_delay; + wire [4:0] STAT_RX_VL_NUMBER_2_delay; + wire [4:0] STAT_RX_VL_NUMBER_3_delay; + wire [4:0] STAT_RX_VL_NUMBER_4_delay; + wire [4:0] STAT_RX_VL_NUMBER_5_delay; + wire [4:0] STAT_RX_VL_NUMBER_6_delay; + wire [4:0] STAT_RX_VL_NUMBER_7_delay; + wire [4:0] STAT_RX_VL_NUMBER_8_delay; + wire [4:0] STAT_RX_VL_NUMBER_9_delay; + wire [4:0] TX_PTP_PCSLANE_OUT_delay; + wire [63:0] TX_SERDES_DATA0_delay; + wire [63:0] TX_SERDES_DATA1_delay; + wire [63:0] TX_SERDES_DATA2_delay; + wire [63:0] TX_SERDES_DATA3_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_0_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_10_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_11_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_12_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_13_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_14_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_15_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_16_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_17_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_18_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_19_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_1_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_2_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_3_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_4_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_5_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_6_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_7_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_8_delay; + wire [6:0] RX_LANE_ALIGNER_FILL_9_delay; + wire [6:0] STAT_RX_BAD_CODE_delay; + wire [6:0] STAT_TX_TOTAL_BYTES_delay; + wire [79:0] RX_PTP_TSTAMP_OUT_delay; + wire [79:0] TX_PTP_TSTAMP_OUT_delay; + wire [7:0] STAT_RX_LANE0_VLM_BIP7_delay; + wire [7:0] STAT_RX_TOTAL_BYTES_delay; + wire [8:0] STAT_RX_PAUSE_REQ_delay; + wire [8:0] STAT_RX_PAUSE_VALID_delay; + wire [8:0] STAT_TX_PAUSE_VALID_delay; + + wire CTL_CAUI4_MODE_in; + wire CTL_RX_CHECK_ETYPE_GCP_in; + wire CTL_RX_CHECK_ETYPE_GPP_in; + wire CTL_RX_CHECK_ETYPE_PCP_in; + wire CTL_RX_CHECK_ETYPE_PPP_in; + wire CTL_RX_CHECK_MCAST_GCP_in; + wire CTL_RX_CHECK_MCAST_GPP_in; + wire CTL_RX_CHECK_MCAST_PCP_in; + wire CTL_RX_CHECK_MCAST_PPP_in; + wire CTL_RX_CHECK_OPCODE_GCP_in; + wire CTL_RX_CHECK_OPCODE_GPP_in; + wire CTL_RX_CHECK_OPCODE_PCP_in; + wire CTL_RX_CHECK_OPCODE_PPP_in; + wire CTL_RX_CHECK_SA_GCP_in; + wire CTL_RX_CHECK_SA_GPP_in; + wire CTL_RX_CHECK_SA_PCP_in; + wire CTL_RX_CHECK_SA_PPP_in; + wire CTL_RX_CHECK_UCAST_GCP_in; + wire CTL_RX_CHECK_UCAST_GPP_in; + wire CTL_RX_CHECK_UCAST_PCP_in; + wire CTL_RX_CHECK_UCAST_PPP_in; + wire CTL_RX_ENABLE_GCP_in; + wire CTL_RX_ENABLE_GPP_in; + wire CTL_RX_ENABLE_PCP_in; + wire CTL_RX_ENABLE_PPP_in; + wire CTL_RX_ENABLE_in; + wire CTL_RX_FORCE_RESYNC_in; + wire CTL_RX_TEST_PATTERN_in; + wire CTL_TX_ENABLE_in; + wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in; + wire CTL_TX_PTP_VLANE_ADJUST_MODE_in; + wire CTL_TX_RESEND_PAUSE_in; + wire CTL_TX_SEND_IDLE_in; + wire CTL_TX_SEND_RFI_in; + wire CTL_TX_TEST_PATTERN_in; + wire DRP_CLK_in; + wire DRP_EN_in; + wire DRP_WE_in; + wire RX_CLK_in; + wire RX_RESET_in; + wire SCAN_EN_in; + wire TEST_MODE_in; + wire TEST_RESET_in; + wire TX_CLK_in; + wire TX_ENAIN0_in; + wire TX_ENAIN1_in; + wire TX_ENAIN2_in; + wire TX_ENAIN3_in; + wire TX_EOPIN0_in; + wire TX_EOPIN1_in; + wire TX_EOPIN2_in; + wire TX_EOPIN3_in; + wire TX_ERRIN0_in; + wire TX_ERRIN1_in; + wire TX_ERRIN2_in; + wire TX_ERRIN3_in; + wire TX_PTP_UPD_CHKSUM_IN_in; + wire TX_RESET_in; + wire TX_SOPIN0_in; + wire TX_SOPIN1_in; + wire TX_SOPIN2_in; + wire TX_SOPIN3_in; + wire [127:0] TX_DATAIN0_in; + wire [127:0] TX_DATAIN1_in; + wire [127:0] TX_DATAIN2_in; + wire [127:0] TX_DATAIN3_in; + wire [12:0] SCAN_IN_DRPCTRL_in; + wire [15:0] CTL_TX_PAUSE_QUANTA0_in; + wire [15:0] CTL_TX_PAUSE_QUANTA1_in; + wire [15:0] CTL_TX_PAUSE_QUANTA2_in; + wire [15:0] CTL_TX_PAUSE_QUANTA3_in; + wire [15:0] CTL_TX_PAUSE_QUANTA4_in; + wire [15:0] CTL_TX_PAUSE_QUANTA5_in; + wire [15:0] CTL_TX_PAUSE_QUANTA6_in; + wire [15:0] CTL_TX_PAUSE_QUANTA7_in; + wire [15:0] CTL_TX_PAUSE_QUANTA8_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_in; + wire [15:0] DRP_DI_in; + wire [15:0] RX_SERDES_ALT_DATA0_in; + wire [15:0] RX_SERDES_ALT_DATA1_in; + wire [15:0] RX_SERDES_ALT_DATA2_in; + wire [15:0] RX_SERDES_ALT_DATA3_in; + wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_in; + wire [15:0] TX_PTP_TAG_FIELD_IN_in; + wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_in; + wire [181:0] SCAN_IN_CMAC_in; + wire [1:0] TX_PTP_1588OP_IN_in; + wire [31:0] RX_SERDES_DATA4_in; + wire [31:0] RX_SERDES_DATA5_in; + wire [31:0] RX_SERDES_DATA6_in; + wire [31:0] RX_SERDES_DATA7_in; + wire [31:0] RX_SERDES_DATA8_in; + wire [31:0] RX_SERDES_DATA9_in; + wire [3:0] TX_MTYIN0_in; + wire [3:0] TX_MTYIN1_in; + wire [3:0] TX_MTYIN2_in; + wire [3:0] TX_MTYIN3_in; + wire [63:0] RX_SERDES_DATA0_in; + wire [63:0] RX_SERDES_DATA1_in; + wire [63:0] RX_SERDES_DATA2_in; + wire [63:0] RX_SERDES_DATA3_in; + wire [63:0] TX_PTP_RXTSTAMP_IN_in; + wire [79:0] CTL_RX_SYSTEMTIMERIN_in; + wire [79:0] CTL_TX_SYSTEMTIMERIN_in; + wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in; + wire [8:0] CTL_RX_PAUSE_ACK_in; + wire [8:0] CTL_RX_PAUSE_ENABLE_in; + wire [8:0] CTL_TX_PAUSE_ENABLE_in; + wire [8:0] CTL_TX_PAUSE_REQ_in; + wire [9:0] DRP_ADDR_in; + wire [9:0] RX_SERDES_CLK_in; + wire [9:0] RX_SERDES_RESET_in; + + wire CTL_CAUI4_MODE_delay; + wire CTL_RX_CHECK_ETYPE_GCP_delay; + wire CTL_RX_CHECK_ETYPE_GPP_delay; + wire CTL_RX_CHECK_ETYPE_PCP_delay; + wire CTL_RX_CHECK_ETYPE_PPP_delay; + wire CTL_RX_CHECK_MCAST_GCP_delay; + wire CTL_RX_CHECK_MCAST_GPP_delay; + wire CTL_RX_CHECK_MCAST_PCP_delay; + wire CTL_RX_CHECK_MCAST_PPP_delay; + wire CTL_RX_CHECK_OPCODE_GCP_delay; + wire CTL_RX_CHECK_OPCODE_GPP_delay; + wire CTL_RX_CHECK_OPCODE_PCP_delay; + wire CTL_RX_CHECK_OPCODE_PPP_delay; + wire CTL_RX_CHECK_SA_GCP_delay; + wire CTL_RX_CHECK_SA_GPP_delay; + wire CTL_RX_CHECK_SA_PCP_delay; + wire CTL_RX_CHECK_SA_PPP_delay; + wire CTL_RX_CHECK_UCAST_GCP_delay; + wire CTL_RX_CHECK_UCAST_GPP_delay; + wire CTL_RX_CHECK_UCAST_PCP_delay; + wire CTL_RX_CHECK_UCAST_PPP_delay; + wire CTL_RX_ENABLE_GCP_delay; + wire CTL_RX_ENABLE_GPP_delay; + wire CTL_RX_ENABLE_PCP_delay; + wire CTL_RX_ENABLE_PPP_delay; + wire CTL_RX_ENABLE_delay; + wire CTL_RX_FORCE_RESYNC_delay; + wire CTL_RX_TEST_PATTERN_delay; + wire CTL_TX_ENABLE_delay; + wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay; + wire CTL_TX_PTP_VLANE_ADJUST_MODE_delay; + wire CTL_TX_RESEND_PAUSE_delay; + wire CTL_TX_SEND_IDLE_delay; + wire CTL_TX_SEND_RFI_delay; + wire CTL_TX_TEST_PATTERN_delay; + wire DRP_CLK_delay; + wire DRP_EN_delay; + wire DRP_WE_delay; + wire RX_CLK_delay; + wire RX_RESET_delay; + wire TX_CLK_delay; + wire TX_ENAIN0_delay; + wire TX_ENAIN1_delay; + wire TX_ENAIN2_delay; + wire TX_ENAIN3_delay; + wire TX_EOPIN0_delay; + wire TX_EOPIN1_delay; + wire TX_EOPIN2_delay; + wire TX_EOPIN3_delay; + wire TX_ERRIN0_delay; + wire TX_ERRIN1_delay; + wire TX_ERRIN2_delay; + wire TX_ERRIN3_delay; + wire TX_PTP_UPD_CHKSUM_IN_delay; + wire TX_RESET_delay; + wire TX_SOPIN0_delay; + wire TX_SOPIN1_delay; + wire TX_SOPIN2_delay; + wire TX_SOPIN3_delay; + wire [127:0] TX_DATAIN0_delay; + wire [127:0] TX_DATAIN1_delay; + wire [127:0] TX_DATAIN2_delay; + wire [127:0] TX_DATAIN3_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA0_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA1_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA2_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA3_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA4_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA5_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA6_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA7_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA8_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_delay; + wire [15:0] DRP_DI_delay; + wire [15:0] RX_SERDES_ALT_DATA0_delay; + wire [15:0] RX_SERDES_ALT_DATA1_delay; + wire [15:0] RX_SERDES_ALT_DATA2_delay; + wire [15:0] RX_SERDES_ALT_DATA3_delay; + wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_delay; + wire [15:0] TX_PTP_TAG_FIELD_IN_delay; + wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_delay; + wire [1:0] TX_PTP_1588OP_IN_delay; + wire [31:0] RX_SERDES_DATA4_delay; + wire [31:0] RX_SERDES_DATA5_delay; + wire [31:0] RX_SERDES_DATA6_delay; + wire [31:0] RX_SERDES_DATA7_delay; + wire [31:0] RX_SERDES_DATA8_delay; + wire [31:0] RX_SERDES_DATA9_delay; + wire [3:0] TX_MTYIN0_delay; + wire [3:0] TX_MTYIN1_delay; + wire [3:0] TX_MTYIN2_delay; + wire [3:0] TX_MTYIN3_delay; + wire [63:0] RX_SERDES_DATA0_delay; + wire [63:0] RX_SERDES_DATA1_delay; + wire [63:0] RX_SERDES_DATA2_delay; + wire [63:0] RX_SERDES_DATA3_delay; + wire [63:0] TX_PTP_RXTSTAMP_IN_delay; + wire [79:0] CTL_RX_SYSTEMTIMERIN_delay; + wire [79:0] CTL_TX_SYSTEMTIMERIN_delay; + wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay; + wire [8:0] CTL_RX_PAUSE_ACK_delay; + wire [8:0] CTL_RX_PAUSE_ENABLE_delay; + wire [8:0] CTL_TX_PAUSE_ENABLE_delay; + wire [8:0] CTL_TX_PAUSE_REQ_delay; + wire [9:0] DRP_ADDR_delay; + wire [9:0] RX_SERDES_CLK_delay; + wire [9:0] RX_SERDES_RESET_delay; + + assign #(out_delay) DRP_DO = DRP_DO_delay; + assign #(out_delay) DRP_RDY = DRP_RDY_delay; + assign #(out_delay) RX_DATAOUT0 = RX_DATAOUT0_delay; + assign #(out_delay) RX_DATAOUT1 = RX_DATAOUT1_delay; + assign #(out_delay) RX_DATAOUT2 = RX_DATAOUT2_delay; + assign #(out_delay) RX_DATAOUT3 = RX_DATAOUT3_delay; + assign #(out_delay) RX_ENAOUT0 = RX_ENAOUT0_delay; + assign #(out_delay) RX_ENAOUT1 = RX_ENAOUT1_delay; + assign #(out_delay) RX_ENAOUT2 = RX_ENAOUT2_delay; + assign #(out_delay) RX_ENAOUT3 = RX_ENAOUT3_delay; + assign #(out_delay) RX_EOPOUT0 = RX_EOPOUT0_delay; + assign #(out_delay) RX_EOPOUT1 = RX_EOPOUT1_delay; + assign #(out_delay) RX_EOPOUT2 = RX_EOPOUT2_delay; + assign #(out_delay) RX_EOPOUT3 = RX_EOPOUT3_delay; + assign #(out_delay) RX_ERROUT0 = RX_ERROUT0_delay; + assign #(out_delay) RX_ERROUT1 = RX_ERROUT1_delay; + assign #(out_delay) RX_ERROUT2 = RX_ERROUT2_delay; + assign #(out_delay) RX_ERROUT3 = RX_ERROUT3_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_0 = RX_LANE_ALIGNER_FILL_0_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_1 = RX_LANE_ALIGNER_FILL_1_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_10 = RX_LANE_ALIGNER_FILL_10_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_11 = RX_LANE_ALIGNER_FILL_11_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_12 = RX_LANE_ALIGNER_FILL_12_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_13 = RX_LANE_ALIGNER_FILL_13_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_14 = RX_LANE_ALIGNER_FILL_14_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_15 = RX_LANE_ALIGNER_FILL_15_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_16 = RX_LANE_ALIGNER_FILL_16_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_17 = RX_LANE_ALIGNER_FILL_17_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_18 = RX_LANE_ALIGNER_FILL_18_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_19 = RX_LANE_ALIGNER_FILL_19_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_2 = RX_LANE_ALIGNER_FILL_2_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_3 = RX_LANE_ALIGNER_FILL_3_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_4 = RX_LANE_ALIGNER_FILL_4_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_5 = RX_LANE_ALIGNER_FILL_5_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_6 = RX_LANE_ALIGNER_FILL_6_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_7 = RX_LANE_ALIGNER_FILL_7_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_8 = RX_LANE_ALIGNER_FILL_8_delay; + assign #(out_delay) RX_LANE_ALIGNER_FILL_9 = RX_LANE_ALIGNER_FILL_9_delay; + assign #(out_delay) RX_MTYOUT0 = RX_MTYOUT0_delay; + assign #(out_delay) RX_MTYOUT1 = RX_MTYOUT1_delay; + assign #(out_delay) RX_MTYOUT2 = RX_MTYOUT2_delay; + assign #(out_delay) RX_MTYOUT3 = RX_MTYOUT3_delay; + assign #(out_delay) RX_PTP_PCSLANE_OUT = RX_PTP_PCSLANE_OUT_delay; + assign #(out_delay) RX_PTP_TSTAMP_OUT = RX_PTP_TSTAMP_OUT_delay; + assign #(out_delay) RX_SOPOUT0 = RX_SOPOUT0_delay; + assign #(out_delay) RX_SOPOUT1 = RX_SOPOUT1_delay; + assign #(out_delay) RX_SOPOUT2 = RX_SOPOUT2_delay; + assign #(out_delay) RX_SOPOUT3 = RX_SOPOUT3_delay; + assign #(out_delay) STAT_RX_ALIGNED = STAT_RX_ALIGNED_delay; + assign #(out_delay) STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_delay; + assign #(out_delay) STAT_RX_BAD_CODE = STAT_RX_BAD_CODE_delay; + assign #(out_delay) STAT_RX_BAD_FCS = STAT_RX_BAD_FCS_delay; + assign #(out_delay) STAT_RX_BAD_PREAMBLE = STAT_RX_BAD_PREAMBLE_delay; + assign #(out_delay) STAT_RX_BAD_SFD = STAT_RX_BAD_SFD_delay; + assign #(out_delay) STAT_RX_BIP_ERR_0 = STAT_RX_BIP_ERR_0_delay; + assign #(out_delay) STAT_RX_BIP_ERR_1 = STAT_RX_BIP_ERR_1_delay; + assign #(out_delay) STAT_RX_BIP_ERR_10 = STAT_RX_BIP_ERR_10_delay; + assign #(out_delay) STAT_RX_BIP_ERR_11 = STAT_RX_BIP_ERR_11_delay; + assign #(out_delay) STAT_RX_BIP_ERR_12 = STAT_RX_BIP_ERR_12_delay; + assign #(out_delay) STAT_RX_BIP_ERR_13 = STAT_RX_BIP_ERR_13_delay; + assign #(out_delay) STAT_RX_BIP_ERR_14 = STAT_RX_BIP_ERR_14_delay; + assign #(out_delay) STAT_RX_BIP_ERR_15 = STAT_RX_BIP_ERR_15_delay; + assign #(out_delay) STAT_RX_BIP_ERR_16 = STAT_RX_BIP_ERR_16_delay; + assign #(out_delay) STAT_RX_BIP_ERR_17 = STAT_RX_BIP_ERR_17_delay; + assign #(out_delay) STAT_RX_BIP_ERR_18 = STAT_RX_BIP_ERR_18_delay; + assign #(out_delay) STAT_RX_BIP_ERR_19 = STAT_RX_BIP_ERR_19_delay; + assign #(out_delay) STAT_RX_BIP_ERR_2 = STAT_RX_BIP_ERR_2_delay; + assign #(out_delay) STAT_RX_BIP_ERR_3 = STAT_RX_BIP_ERR_3_delay; + assign #(out_delay) STAT_RX_BIP_ERR_4 = STAT_RX_BIP_ERR_4_delay; + assign #(out_delay) STAT_RX_BIP_ERR_5 = STAT_RX_BIP_ERR_5_delay; + assign #(out_delay) STAT_RX_BIP_ERR_6 = STAT_RX_BIP_ERR_6_delay; + assign #(out_delay) STAT_RX_BIP_ERR_7 = STAT_RX_BIP_ERR_7_delay; + assign #(out_delay) STAT_RX_BIP_ERR_8 = STAT_RX_BIP_ERR_8_delay; + assign #(out_delay) STAT_RX_BIP_ERR_9 = STAT_RX_BIP_ERR_9_delay; + assign #(out_delay) STAT_RX_BLOCK_LOCK = STAT_RX_BLOCK_LOCK_delay; + assign #(out_delay) STAT_RX_BROADCAST = STAT_RX_BROADCAST_delay; + assign #(out_delay) STAT_RX_FRAGMENT = STAT_RX_FRAGMENT_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_0 = STAT_RX_FRAMING_ERR_0_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_1 = STAT_RX_FRAMING_ERR_1_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_10 = STAT_RX_FRAMING_ERR_10_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_11 = STAT_RX_FRAMING_ERR_11_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_12 = STAT_RX_FRAMING_ERR_12_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_13 = STAT_RX_FRAMING_ERR_13_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_14 = STAT_RX_FRAMING_ERR_14_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_15 = STAT_RX_FRAMING_ERR_15_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_16 = STAT_RX_FRAMING_ERR_16_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_17 = STAT_RX_FRAMING_ERR_17_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_18 = STAT_RX_FRAMING_ERR_18_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_19 = STAT_RX_FRAMING_ERR_19_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_2 = STAT_RX_FRAMING_ERR_2_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_3 = STAT_RX_FRAMING_ERR_3_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_4 = STAT_RX_FRAMING_ERR_4_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_5 = STAT_RX_FRAMING_ERR_5_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_6 = STAT_RX_FRAMING_ERR_6_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_7 = STAT_RX_FRAMING_ERR_7_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_8 = STAT_RX_FRAMING_ERR_8_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_9 = STAT_RX_FRAMING_ERR_9_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_0 = STAT_RX_FRAMING_ERR_VALID_0_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_1 = STAT_RX_FRAMING_ERR_VALID_1_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_10 = STAT_RX_FRAMING_ERR_VALID_10_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_11 = STAT_RX_FRAMING_ERR_VALID_11_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_12 = STAT_RX_FRAMING_ERR_VALID_12_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_13 = STAT_RX_FRAMING_ERR_VALID_13_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_14 = STAT_RX_FRAMING_ERR_VALID_14_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_15 = STAT_RX_FRAMING_ERR_VALID_15_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_16 = STAT_RX_FRAMING_ERR_VALID_16_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_17 = STAT_RX_FRAMING_ERR_VALID_17_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_18 = STAT_RX_FRAMING_ERR_VALID_18_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_19 = STAT_RX_FRAMING_ERR_VALID_19_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_2 = STAT_RX_FRAMING_ERR_VALID_2_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_3 = STAT_RX_FRAMING_ERR_VALID_3_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_4 = STAT_RX_FRAMING_ERR_VALID_4_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_5 = STAT_RX_FRAMING_ERR_VALID_5_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_6 = STAT_RX_FRAMING_ERR_VALID_6_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_7 = STAT_RX_FRAMING_ERR_VALID_7_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_8 = STAT_RX_FRAMING_ERR_VALID_8_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_9 = STAT_RX_FRAMING_ERR_VALID_9_delay; + assign #(out_delay) STAT_RX_GOT_SIGNAL_OS = STAT_RX_GOT_SIGNAL_OS_delay; + assign #(out_delay) STAT_RX_HI_BER = STAT_RX_HI_BER_delay; + assign #(out_delay) STAT_RX_INRANGEERR = STAT_RX_INRANGEERR_delay; + assign #(out_delay) STAT_RX_INTERNAL_LOCAL_FAULT = STAT_RX_INTERNAL_LOCAL_FAULT_delay; + assign #(out_delay) STAT_RX_JABBER = STAT_RX_JABBER_delay; + assign #(out_delay) STAT_RX_LANE0_VLM_BIP7 = STAT_RX_LANE0_VLM_BIP7_delay; + assign #(out_delay) STAT_RX_LANE0_VLM_BIP7_VALID = STAT_RX_LANE0_VLM_BIP7_VALID_delay; + assign #(out_delay) STAT_RX_LOCAL_FAULT = STAT_RX_LOCAL_FAULT_delay; + assign #(out_delay) STAT_RX_MF_ERR = STAT_RX_MF_ERR_delay; + assign #(out_delay) STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_delay; + assign #(out_delay) STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_delay; + assign #(out_delay) STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_delay; + assign #(out_delay) STAT_RX_MULTICAST = STAT_RX_MULTICAST_delay; + assign #(out_delay) STAT_RX_OVERSIZE = STAT_RX_OVERSIZE_delay; + assign #(out_delay) STAT_RX_PACKET_1024_1518_BYTES = STAT_RX_PACKET_1024_1518_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_128_255_BYTES = STAT_RX_PACKET_128_255_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_1519_1522_BYTES = STAT_RX_PACKET_1519_1522_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_1523_1548_BYTES = STAT_RX_PACKET_1523_1548_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_1549_2047_BYTES = STAT_RX_PACKET_1549_2047_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_2048_4095_BYTES = STAT_RX_PACKET_2048_4095_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_256_511_BYTES = STAT_RX_PACKET_256_511_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_4096_8191_BYTES = STAT_RX_PACKET_4096_8191_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_512_1023_BYTES = STAT_RX_PACKET_512_1023_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_64_BYTES = STAT_RX_PACKET_64_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_65_127_BYTES = STAT_RX_PACKET_65_127_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_8192_9215_BYTES = STAT_RX_PACKET_8192_9215_BYTES_delay; + assign #(out_delay) STAT_RX_PACKET_BAD_FCS = STAT_RX_PACKET_BAD_FCS_delay; + assign #(out_delay) STAT_RX_PACKET_LARGE = STAT_RX_PACKET_LARGE_delay; + assign #(out_delay) STAT_RX_PACKET_SMALL = STAT_RX_PACKET_SMALL_delay; + assign #(out_delay) STAT_RX_PAUSE = STAT_RX_PAUSE_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA0 = STAT_RX_PAUSE_QUANTA0_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA1 = STAT_RX_PAUSE_QUANTA1_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA2 = STAT_RX_PAUSE_QUANTA2_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA3 = STAT_RX_PAUSE_QUANTA3_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA4 = STAT_RX_PAUSE_QUANTA4_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA5 = STAT_RX_PAUSE_QUANTA5_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA6 = STAT_RX_PAUSE_QUANTA6_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA7 = STAT_RX_PAUSE_QUANTA7_delay; + assign #(out_delay) STAT_RX_PAUSE_QUANTA8 = STAT_RX_PAUSE_QUANTA8_delay; + assign #(out_delay) STAT_RX_PAUSE_REQ = STAT_RX_PAUSE_REQ_delay; + assign #(out_delay) STAT_RX_PAUSE_VALID = STAT_RX_PAUSE_VALID_delay; + assign #(out_delay) STAT_RX_RECEIVED_LOCAL_FAULT = STAT_RX_RECEIVED_LOCAL_FAULT_delay; + assign #(out_delay) STAT_RX_REMOTE_FAULT = STAT_RX_REMOTE_FAULT_delay; + assign #(out_delay) STAT_RX_STATUS = STAT_RX_STATUS_delay; + assign #(out_delay) STAT_RX_STOMPED_FCS = STAT_RX_STOMPED_FCS_delay; + assign #(out_delay) STAT_RX_SYNCED = STAT_RX_SYNCED_delay; + assign #(out_delay) STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_delay; + assign #(out_delay) STAT_RX_TEST_PATTERN_MISMATCH = STAT_RX_TEST_PATTERN_MISMATCH_delay; + assign #(out_delay) STAT_RX_TOOLONG = STAT_RX_TOOLONG_delay; + assign #(out_delay) STAT_RX_TOTAL_BYTES = STAT_RX_TOTAL_BYTES_delay; + assign #(out_delay) STAT_RX_TOTAL_GOOD_BYTES = STAT_RX_TOTAL_GOOD_BYTES_delay; + assign #(out_delay) STAT_RX_TOTAL_GOOD_PACKETS = STAT_RX_TOTAL_GOOD_PACKETS_delay; + assign #(out_delay) STAT_RX_TOTAL_PACKETS = STAT_RX_TOTAL_PACKETS_delay; + assign #(out_delay) STAT_RX_TRUNCATED = STAT_RX_TRUNCATED_delay; + assign #(out_delay) STAT_RX_UNDERSIZE = STAT_RX_UNDERSIZE_delay; + assign #(out_delay) STAT_RX_UNICAST = STAT_RX_UNICAST_delay; + assign #(out_delay) STAT_RX_USER_PAUSE = STAT_RX_USER_PAUSE_delay; + assign #(out_delay) STAT_RX_VLAN = STAT_RX_VLAN_delay; + assign #(out_delay) STAT_RX_VL_DEMUXED = STAT_RX_VL_DEMUXED_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_0 = STAT_RX_VL_NUMBER_0_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_1 = STAT_RX_VL_NUMBER_1_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_10 = STAT_RX_VL_NUMBER_10_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_11 = STAT_RX_VL_NUMBER_11_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_12 = STAT_RX_VL_NUMBER_12_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_13 = STAT_RX_VL_NUMBER_13_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_14 = STAT_RX_VL_NUMBER_14_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_15 = STAT_RX_VL_NUMBER_15_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_16 = STAT_RX_VL_NUMBER_16_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_17 = STAT_RX_VL_NUMBER_17_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_18 = STAT_RX_VL_NUMBER_18_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_19 = STAT_RX_VL_NUMBER_19_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_2 = STAT_RX_VL_NUMBER_2_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_3 = STAT_RX_VL_NUMBER_3_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_4 = STAT_RX_VL_NUMBER_4_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_5 = STAT_RX_VL_NUMBER_5_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_6 = STAT_RX_VL_NUMBER_6_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_7 = STAT_RX_VL_NUMBER_7_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_8 = STAT_RX_VL_NUMBER_8_delay; + assign #(out_delay) STAT_RX_VL_NUMBER_9 = STAT_RX_VL_NUMBER_9_delay; + assign #(out_delay) STAT_TX_BAD_FCS = STAT_TX_BAD_FCS_delay; + assign #(out_delay) STAT_TX_BROADCAST = STAT_TX_BROADCAST_delay; + assign #(out_delay) STAT_TX_FRAME_ERROR = STAT_TX_FRAME_ERROR_delay; + assign #(out_delay) STAT_TX_LOCAL_FAULT = STAT_TX_LOCAL_FAULT_delay; + assign #(out_delay) STAT_TX_MULTICAST = STAT_TX_MULTICAST_delay; + assign #(out_delay) STAT_TX_PACKET_1024_1518_BYTES = STAT_TX_PACKET_1024_1518_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_128_255_BYTES = STAT_TX_PACKET_128_255_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_1519_1522_BYTES = STAT_TX_PACKET_1519_1522_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_1523_1548_BYTES = STAT_TX_PACKET_1523_1548_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_1549_2047_BYTES = STAT_TX_PACKET_1549_2047_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_2048_4095_BYTES = STAT_TX_PACKET_2048_4095_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_256_511_BYTES = STAT_TX_PACKET_256_511_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_4096_8191_BYTES = STAT_TX_PACKET_4096_8191_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_512_1023_BYTES = STAT_TX_PACKET_512_1023_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_64_BYTES = STAT_TX_PACKET_64_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_65_127_BYTES = STAT_TX_PACKET_65_127_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_8192_9215_BYTES = STAT_TX_PACKET_8192_9215_BYTES_delay; + assign #(out_delay) STAT_TX_PACKET_LARGE = STAT_TX_PACKET_LARGE_delay; + assign #(out_delay) STAT_TX_PACKET_SMALL = STAT_TX_PACKET_SMALL_delay; + assign #(out_delay) STAT_TX_PAUSE = STAT_TX_PAUSE_delay; + assign #(out_delay) STAT_TX_PAUSE_VALID = STAT_TX_PAUSE_VALID_delay; + assign #(out_delay) STAT_TX_PTP_FIFO_READ_ERROR = STAT_TX_PTP_FIFO_READ_ERROR_delay; + assign #(out_delay) STAT_TX_PTP_FIFO_WRITE_ERROR = STAT_TX_PTP_FIFO_WRITE_ERROR_delay; + assign #(out_delay) STAT_TX_TOTAL_BYTES = STAT_TX_TOTAL_BYTES_delay; + assign #(out_delay) STAT_TX_TOTAL_GOOD_BYTES = STAT_TX_TOTAL_GOOD_BYTES_delay; + assign #(out_delay) STAT_TX_TOTAL_GOOD_PACKETS = STAT_TX_TOTAL_GOOD_PACKETS_delay; + assign #(out_delay) STAT_TX_TOTAL_PACKETS = STAT_TX_TOTAL_PACKETS_delay; + assign #(out_delay) STAT_TX_UNICAST = STAT_TX_UNICAST_delay; + assign #(out_delay) STAT_TX_USER_PAUSE = STAT_TX_USER_PAUSE_delay; + assign #(out_delay) STAT_TX_VLAN = STAT_TX_VLAN_delay; + assign #(out_delay) TX_OVFOUT = TX_OVFOUT_delay; + assign #(out_delay) TX_PTP_PCSLANE_OUT = TX_PTP_PCSLANE_OUT_delay; + assign #(out_delay) TX_PTP_TSTAMP_OUT = TX_PTP_TSTAMP_OUT_delay; + assign #(out_delay) TX_PTP_TSTAMP_TAG_OUT = TX_PTP_TSTAMP_TAG_OUT_delay; + assign #(out_delay) TX_PTP_TSTAMP_VALID_OUT = TX_PTP_TSTAMP_VALID_OUT_delay; + assign #(out_delay) TX_RDYOUT = TX_RDYOUT_delay; + assign #(out_delay) TX_SERDES_ALT_DATA0 = TX_SERDES_ALT_DATA0_delay; + assign #(out_delay) TX_SERDES_ALT_DATA1 = TX_SERDES_ALT_DATA1_delay; + assign #(out_delay) TX_SERDES_ALT_DATA2 = TX_SERDES_ALT_DATA2_delay; + assign #(out_delay) TX_SERDES_ALT_DATA3 = TX_SERDES_ALT_DATA3_delay; + assign #(out_delay) TX_SERDES_DATA0 = TX_SERDES_DATA0_delay; + assign #(out_delay) TX_SERDES_DATA1 = TX_SERDES_DATA1_delay; + assign #(out_delay) TX_SERDES_DATA2 = TX_SERDES_DATA2_delay; + assign #(out_delay) TX_SERDES_DATA3 = TX_SERDES_DATA3_delay; + assign #(out_delay) TX_SERDES_DATA4 = TX_SERDES_DATA4_delay; + assign #(out_delay) TX_SERDES_DATA5 = TX_SERDES_DATA5_delay; + assign #(out_delay) TX_SERDES_DATA6 = TX_SERDES_DATA6_delay; + assign #(out_delay) TX_SERDES_DATA7 = TX_SERDES_DATA7_delay; + assign #(out_delay) TX_SERDES_DATA8 = TX_SERDES_DATA8_delay; + assign #(out_delay) TX_SERDES_DATA9 = TX_SERDES_DATA9_delay; + assign #(out_delay) TX_UNFOUT = TX_UNFOUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) DRP_CLK_delay = DRP_CLK; + assign #(inclk_delay) RX_CLK_delay = RX_CLK; + assign #(inclk_delay) TX_CLK_delay = TX_CLK; + + assign #(in_delay) CTL_CAUI4_MODE_delay = CTL_CAUI4_MODE; + assign #(in_delay) CTL_RX_CHECK_ETYPE_GCP_delay = CTL_RX_CHECK_ETYPE_GCP; + assign #(in_delay) CTL_RX_CHECK_ETYPE_GPP_delay = CTL_RX_CHECK_ETYPE_GPP; + assign #(in_delay) CTL_RX_CHECK_ETYPE_PCP_delay = CTL_RX_CHECK_ETYPE_PCP; + assign #(in_delay) CTL_RX_CHECK_ETYPE_PPP_delay = CTL_RX_CHECK_ETYPE_PPP; + assign #(in_delay) CTL_RX_CHECK_MCAST_GCP_delay = CTL_RX_CHECK_MCAST_GCP; + assign #(in_delay) CTL_RX_CHECK_MCAST_GPP_delay = CTL_RX_CHECK_MCAST_GPP; + assign #(in_delay) CTL_RX_CHECK_MCAST_PCP_delay = CTL_RX_CHECK_MCAST_PCP; + assign #(in_delay) CTL_RX_CHECK_MCAST_PPP_delay = CTL_RX_CHECK_MCAST_PPP; + assign #(in_delay) CTL_RX_CHECK_OPCODE_GCP_delay = CTL_RX_CHECK_OPCODE_GCP; + assign #(in_delay) CTL_RX_CHECK_OPCODE_GPP_delay = CTL_RX_CHECK_OPCODE_GPP; + assign #(in_delay) CTL_RX_CHECK_OPCODE_PCP_delay = CTL_RX_CHECK_OPCODE_PCP; + assign #(in_delay) CTL_RX_CHECK_OPCODE_PPP_delay = CTL_RX_CHECK_OPCODE_PPP; + assign #(in_delay) CTL_RX_CHECK_SA_GCP_delay = CTL_RX_CHECK_SA_GCP; + assign #(in_delay) CTL_RX_CHECK_SA_GPP_delay = CTL_RX_CHECK_SA_GPP; + assign #(in_delay) CTL_RX_CHECK_SA_PCP_delay = CTL_RX_CHECK_SA_PCP; + assign #(in_delay) CTL_RX_CHECK_SA_PPP_delay = CTL_RX_CHECK_SA_PPP; + assign #(in_delay) CTL_RX_CHECK_UCAST_GCP_delay = CTL_RX_CHECK_UCAST_GCP; + assign #(in_delay) CTL_RX_CHECK_UCAST_GPP_delay = CTL_RX_CHECK_UCAST_GPP; + assign #(in_delay) CTL_RX_CHECK_UCAST_PCP_delay = CTL_RX_CHECK_UCAST_PCP; + assign #(in_delay) CTL_RX_CHECK_UCAST_PPP_delay = CTL_RX_CHECK_UCAST_PPP; + assign #(in_delay) CTL_RX_ENABLE_GCP_delay = CTL_RX_ENABLE_GCP; + assign #(in_delay) CTL_RX_ENABLE_GPP_delay = CTL_RX_ENABLE_GPP; + assign #(in_delay) CTL_RX_ENABLE_PCP_delay = CTL_RX_ENABLE_PCP; + assign #(in_delay) CTL_RX_ENABLE_PPP_delay = CTL_RX_ENABLE_PPP; + assign #(in_delay) CTL_RX_ENABLE_delay = CTL_RX_ENABLE; + assign #(in_delay) CTL_RX_FORCE_RESYNC_delay = CTL_RX_FORCE_RESYNC; + assign #(in_delay) CTL_RX_PAUSE_ACK_delay = CTL_RX_PAUSE_ACK; + assign #(in_delay) CTL_RX_PAUSE_ENABLE_delay = CTL_RX_PAUSE_ENABLE; + assign #(in_delay) CTL_RX_SYSTEMTIMERIN_delay = CTL_RX_SYSTEMTIMERIN; + assign #(in_delay) CTL_RX_TEST_PATTERN_delay = CTL_RX_TEST_PATTERN; + assign #(in_delay) CTL_TX_ENABLE_delay = CTL_TX_ENABLE; + assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + assign #(in_delay) CTL_TX_PAUSE_ENABLE_delay = CTL_TX_PAUSE_ENABLE; + assign #(in_delay) CTL_TX_PAUSE_QUANTA0_delay = CTL_TX_PAUSE_QUANTA0; + assign #(in_delay) CTL_TX_PAUSE_QUANTA1_delay = CTL_TX_PAUSE_QUANTA1; + assign #(in_delay) CTL_TX_PAUSE_QUANTA2_delay = CTL_TX_PAUSE_QUANTA2; + assign #(in_delay) CTL_TX_PAUSE_QUANTA3_delay = CTL_TX_PAUSE_QUANTA3; + assign #(in_delay) CTL_TX_PAUSE_QUANTA4_delay = CTL_TX_PAUSE_QUANTA4; + assign #(in_delay) CTL_TX_PAUSE_QUANTA5_delay = CTL_TX_PAUSE_QUANTA5; + assign #(in_delay) CTL_TX_PAUSE_QUANTA6_delay = CTL_TX_PAUSE_QUANTA6; + assign #(in_delay) CTL_TX_PAUSE_QUANTA7_delay = CTL_TX_PAUSE_QUANTA7; + assign #(in_delay) CTL_TX_PAUSE_QUANTA8_delay = CTL_TX_PAUSE_QUANTA8; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER0_delay = CTL_TX_PAUSE_REFRESH_TIMER0; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER1_delay = CTL_TX_PAUSE_REFRESH_TIMER1; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER2_delay = CTL_TX_PAUSE_REFRESH_TIMER2; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER3_delay = CTL_TX_PAUSE_REFRESH_TIMER3; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER4_delay = CTL_TX_PAUSE_REFRESH_TIMER4; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER5_delay = CTL_TX_PAUSE_REFRESH_TIMER5; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER6_delay = CTL_TX_PAUSE_REFRESH_TIMER6; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER7_delay = CTL_TX_PAUSE_REFRESH_TIMER7; + assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER8_delay = CTL_TX_PAUSE_REFRESH_TIMER8; + assign #(in_delay) CTL_TX_PAUSE_REQ_delay = CTL_TX_PAUSE_REQ; + assign #(in_delay) CTL_TX_PTP_VLANE_ADJUST_MODE_delay = CTL_TX_PTP_VLANE_ADJUST_MODE; + assign #(in_delay) CTL_TX_RESEND_PAUSE_delay = CTL_TX_RESEND_PAUSE; + assign #(in_delay) CTL_TX_SEND_IDLE_delay = CTL_TX_SEND_IDLE; + assign #(in_delay) CTL_TX_SEND_RFI_delay = CTL_TX_SEND_RFI; + assign #(in_delay) CTL_TX_SYSTEMTIMERIN_delay = CTL_TX_SYSTEMTIMERIN; + assign #(in_delay) CTL_TX_TEST_PATTERN_delay = CTL_TX_TEST_PATTERN; + assign #(in_delay) DRP_ADDR_delay = DRP_ADDR; + assign #(in_delay) DRP_DI_delay = DRP_DI; + assign #(in_delay) DRP_EN_delay = DRP_EN; + assign #(in_delay) DRP_WE_delay = DRP_WE; + assign #(in_delay) RX_RESET_delay = RX_RESET; + assign #(in_delay) RX_SERDES_ALT_DATA0_delay = RX_SERDES_ALT_DATA0; + assign #(in_delay) RX_SERDES_ALT_DATA1_delay = RX_SERDES_ALT_DATA1; + assign #(in_delay) RX_SERDES_ALT_DATA2_delay = RX_SERDES_ALT_DATA2; + assign #(in_delay) RX_SERDES_ALT_DATA3_delay = RX_SERDES_ALT_DATA3; + assign #(in_delay) RX_SERDES_DATA0_delay = RX_SERDES_DATA0; + assign #(in_delay) RX_SERDES_DATA1_delay = RX_SERDES_DATA1; + assign #(in_delay) RX_SERDES_DATA2_delay = RX_SERDES_DATA2; + assign #(in_delay) RX_SERDES_DATA3_delay = RX_SERDES_DATA3; + assign #(in_delay) RX_SERDES_DATA4_delay = RX_SERDES_DATA4; + assign #(in_delay) RX_SERDES_DATA5_delay = RX_SERDES_DATA5; + assign #(in_delay) RX_SERDES_DATA6_delay = RX_SERDES_DATA6; + assign #(in_delay) RX_SERDES_DATA7_delay = RX_SERDES_DATA7; + assign #(in_delay) RX_SERDES_DATA8_delay = RX_SERDES_DATA8; + assign #(in_delay) RX_SERDES_DATA9_delay = RX_SERDES_DATA9; + assign #(in_delay) RX_SERDES_RESET_delay = RX_SERDES_RESET; + assign #(in_delay) TX_DATAIN0_delay = TX_DATAIN0; + assign #(in_delay) TX_DATAIN1_delay = TX_DATAIN1; + assign #(in_delay) TX_DATAIN2_delay = TX_DATAIN2; + assign #(in_delay) TX_DATAIN3_delay = TX_DATAIN3; + assign #(in_delay) TX_ENAIN0_delay = TX_ENAIN0; + assign #(in_delay) TX_ENAIN1_delay = TX_ENAIN1; + assign #(in_delay) TX_ENAIN2_delay = TX_ENAIN2; + assign #(in_delay) TX_ENAIN3_delay = TX_ENAIN3; + assign #(in_delay) TX_EOPIN0_delay = TX_EOPIN0; + assign #(in_delay) TX_EOPIN1_delay = TX_EOPIN1; + assign #(in_delay) TX_EOPIN2_delay = TX_EOPIN2; + assign #(in_delay) TX_EOPIN3_delay = TX_EOPIN3; + assign #(in_delay) TX_ERRIN0_delay = TX_ERRIN0; + assign #(in_delay) TX_ERRIN1_delay = TX_ERRIN1; + assign #(in_delay) TX_ERRIN2_delay = TX_ERRIN2; + assign #(in_delay) TX_ERRIN3_delay = TX_ERRIN3; + assign #(in_delay) TX_MTYIN0_delay = TX_MTYIN0; + assign #(in_delay) TX_MTYIN1_delay = TX_MTYIN1; + assign #(in_delay) TX_MTYIN2_delay = TX_MTYIN2; + assign #(in_delay) TX_MTYIN3_delay = TX_MTYIN3; + assign #(in_delay) TX_PTP_1588OP_IN_delay = TX_PTP_1588OP_IN; + assign #(in_delay) TX_PTP_CHKSUM_OFFSET_IN_delay = TX_PTP_CHKSUM_OFFSET_IN; + assign #(in_delay) TX_PTP_RXTSTAMP_IN_delay = TX_PTP_RXTSTAMP_IN; + assign #(in_delay) TX_PTP_TAG_FIELD_IN_delay = TX_PTP_TAG_FIELD_IN; + assign #(in_delay) TX_PTP_TSTAMP_OFFSET_IN_delay = TX_PTP_TSTAMP_OFFSET_IN; + assign #(in_delay) TX_PTP_UPD_CHKSUM_IN_delay = TX_PTP_UPD_CHKSUM_IN; + assign #(in_delay) TX_RESET_delay = TX_RESET; + assign #(in_delay) TX_SOPIN0_delay = TX_SOPIN0; + assign #(in_delay) TX_SOPIN1_delay = TX_SOPIN1; + assign #(in_delay) TX_SOPIN2_delay = TX_SOPIN2; + assign #(in_delay) TX_SOPIN3_delay = TX_SOPIN3; + assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK; +`endif + +// inputs with no timing checks + //assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK; + + + assign DRP_DO_delay = DRP_DO_out; + assign DRP_RDY_delay = DRP_RDY_out; + assign RX_DATAOUT0_delay = RX_DATAOUT0_out; + assign RX_DATAOUT1_delay = RX_DATAOUT1_out; + assign RX_DATAOUT2_delay = RX_DATAOUT2_out; + assign RX_DATAOUT3_delay = RX_DATAOUT3_out; + assign RX_ENAOUT0_delay = RX_ENAOUT0_out; + assign RX_ENAOUT1_delay = RX_ENAOUT1_out; + assign RX_ENAOUT2_delay = RX_ENAOUT2_out; + assign RX_ENAOUT3_delay = RX_ENAOUT3_out; + assign RX_EOPOUT0_delay = RX_EOPOUT0_out; + assign RX_EOPOUT1_delay = RX_EOPOUT1_out; + assign RX_EOPOUT2_delay = RX_EOPOUT2_out; + assign RX_EOPOUT3_delay = RX_EOPOUT3_out; + assign RX_ERROUT0_delay = RX_ERROUT0_out; + assign RX_ERROUT1_delay = RX_ERROUT1_out; + assign RX_ERROUT2_delay = RX_ERROUT2_out; + assign RX_ERROUT3_delay = RX_ERROUT3_out; + assign RX_LANE_ALIGNER_FILL_0_delay = RX_LANE_ALIGNER_FILL_0_out; + assign RX_LANE_ALIGNER_FILL_10_delay = RX_LANE_ALIGNER_FILL_10_out; + assign RX_LANE_ALIGNER_FILL_11_delay = RX_LANE_ALIGNER_FILL_11_out; + assign RX_LANE_ALIGNER_FILL_12_delay = RX_LANE_ALIGNER_FILL_12_out; + assign RX_LANE_ALIGNER_FILL_13_delay = RX_LANE_ALIGNER_FILL_13_out; + assign RX_LANE_ALIGNER_FILL_14_delay = RX_LANE_ALIGNER_FILL_14_out; + assign RX_LANE_ALIGNER_FILL_15_delay = RX_LANE_ALIGNER_FILL_15_out; + assign RX_LANE_ALIGNER_FILL_16_delay = RX_LANE_ALIGNER_FILL_16_out; + assign RX_LANE_ALIGNER_FILL_17_delay = RX_LANE_ALIGNER_FILL_17_out; + assign RX_LANE_ALIGNER_FILL_18_delay = RX_LANE_ALIGNER_FILL_18_out; + assign RX_LANE_ALIGNER_FILL_19_delay = RX_LANE_ALIGNER_FILL_19_out; + assign RX_LANE_ALIGNER_FILL_1_delay = RX_LANE_ALIGNER_FILL_1_out; + assign RX_LANE_ALIGNER_FILL_2_delay = RX_LANE_ALIGNER_FILL_2_out; + assign RX_LANE_ALIGNER_FILL_3_delay = RX_LANE_ALIGNER_FILL_3_out; + assign RX_LANE_ALIGNER_FILL_4_delay = RX_LANE_ALIGNER_FILL_4_out; + assign RX_LANE_ALIGNER_FILL_5_delay = RX_LANE_ALIGNER_FILL_5_out; + assign RX_LANE_ALIGNER_FILL_6_delay = RX_LANE_ALIGNER_FILL_6_out; + assign RX_LANE_ALIGNER_FILL_7_delay = RX_LANE_ALIGNER_FILL_7_out; + assign RX_LANE_ALIGNER_FILL_8_delay = RX_LANE_ALIGNER_FILL_8_out; + assign RX_LANE_ALIGNER_FILL_9_delay = RX_LANE_ALIGNER_FILL_9_out; + assign RX_MTYOUT0_delay = RX_MTYOUT0_out; + assign RX_MTYOUT1_delay = RX_MTYOUT1_out; + assign RX_MTYOUT2_delay = RX_MTYOUT2_out; + assign RX_MTYOUT3_delay = RX_MTYOUT3_out; + assign RX_PTP_PCSLANE_OUT_delay = RX_PTP_PCSLANE_OUT_out; + assign RX_PTP_TSTAMP_OUT_delay = RX_PTP_TSTAMP_OUT_out; + assign RX_SOPOUT0_delay = RX_SOPOUT0_out; + assign RX_SOPOUT1_delay = RX_SOPOUT1_out; + assign RX_SOPOUT2_delay = RX_SOPOUT2_out; + assign RX_SOPOUT3_delay = RX_SOPOUT3_out; + assign STAT_RX_ALIGNED_ERR_delay = STAT_RX_ALIGNED_ERR_out; + assign STAT_RX_ALIGNED_delay = STAT_RX_ALIGNED_out; + assign STAT_RX_BAD_CODE_delay = STAT_RX_BAD_CODE_out; + assign STAT_RX_BAD_FCS_delay = STAT_RX_BAD_FCS_out; + assign STAT_RX_BAD_PREAMBLE_delay = STAT_RX_BAD_PREAMBLE_out; + assign STAT_RX_BAD_SFD_delay = STAT_RX_BAD_SFD_out; + assign STAT_RX_BIP_ERR_0_delay = STAT_RX_BIP_ERR_0_out; + assign STAT_RX_BIP_ERR_10_delay = STAT_RX_BIP_ERR_10_out; + assign STAT_RX_BIP_ERR_11_delay = STAT_RX_BIP_ERR_11_out; + assign STAT_RX_BIP_ERR_12_delay = STAT_RX_BIP_ERR_12_out; + assign STAT_RX_BIP_ERR_13_delay = STAT_RX_BIP_ERR_13_out; + assign STAT_RX_BIP_ERR_14_delay = STAT_RX_BIP_ERR_14_out; + assign STAT_RX_BIP_ERR_15_delay = STAT_RX_BIP_ERR_15_out; + assign STAT_RX_BIP_ERR_16_delay = STAT_RX_BIP_ERR_16_out; + assign STAT_RX_BIP_ERR_17_delay = STAT_RX_BIP_ERR_17_out; + assign STAT_RX_BIP_ERR_18_delay = STAT_RX_BIP_ERR_18_out; + assign STAT_RX_BIP_ERR_19_delay = STAT_RX_BIP_ERR_19_out; + assign STAT_RX_BIP_ERR_1_delay = STAT_RX_BIP_ERR_1_out; + assign STAT_RX_BIP_ERR_2_delay = STAT_RX_BIP_ERR_2_out; + assign STAT_RX_BIP_ERR_3_delay = STAT_RX_BIP_ERR_3_out; + assign STAT_RX_BIP_ERR_4_delay = STAT_RX_BIP_ERR_4_out; + assign STAT_RX_BIP_ERR_5_delay = STAT_RX_BIP_ERR_5_out; + assign STAT_RX_BIP_ERR_6_delay = STAT_RX_BIP_ERR_6_out; + assign STAT_RX_BIP_ERR_7_delay = STAT_RX_BIP_ERR_7_out; + assign STAT_RX_BIP_ERR_8_delay = STAT_RX_BIP_ERR_8_out; + assign STAT_RX_BIP_ERR_9_delay = STAT_RX_BIP_ERR_9_out; + assign STAT_RX_BLOCK_LOCK_delay = STAT_RX_BLOCK_LOCK_out; + assign STAT_RX_BROADCAST_delay = STAT_RX_BROADCAST_out; + assign STAT_RX_FRAGMENT_delay = STAT_RX_FRAGMENT_out; + assign STAT_RX_FRAMING_ERR_0_delay = STAT_RX_FRAMING_ERR_0_out; + assign STAT_RX_FRAMING_ERR_10_delay = STAT_RX_FRAMING_ERR_10_out; + assign STAT_RX_FRAMING_ERR_11_delay = STAT_RX_FRAMING_ERR_11_out; + assign STAT_RX_FRAMING_ERR_12_delay = STAT_RX_FRAMING_ERR_12_out; + assign STAT_RX_FRAMING_ERR_13_delay = STAT_RX_FRAMING_ERR_13_out; + assign STAT_RX_FRAMING_ERR_14_delay = STAT_RX_FRAMING_ERR_14_out; + assign STAT_RX_FRAMING_ERR_15_delay = STAT_RX_FRAMING_ERR_15_out; + assign STAT_RX_FRAMING_ERR_16_delay = STAT_RX_FRAMING_ERR_16_out; + assign STAT_RX_FRAMING_ERR_17_delay = STAT_RX_FRAMING_ERR_17_out; + assign STAT_RX_FRAMING_ERR_18_delay = STAT_RX_FRAMING_ERR_18_out; + assign STAT_RX_FRAMING_ERR_19_delay = STAT_RX_FRAMING_ERR_19_out; + assign STAT_RX_FRAMING_ERR_1_delay = STAT_RX_FRAMING_ERR_1_out; + assign STAT_RX_FRAMING_ERR_2_delay = STAT_RX_FRAMING_ERR_2_out; + assign STAT_RX_FRAMING_ERR_3_delay = STAT_RX_FRAMING_ERR_3_out; + assign STAT_RX_FRAMING_ERR_4_delay = STAT_RX_FRAMING_ERR_4_out; + assign STAT_RX_FRAMING_ERR_5_delay = STAT_RX_FRAMING_ERR_5_out; + assign STAT_RX_FRAMING_ERR_6_delay = STAT_RX_FRAMING_ERR_6_out; + assign STAT_RX_FRAMING_ERR_7_delay = STAT_RX_FRAMING_ERR_7_out; + assign STAT_RX_FRAMING_ERR_8_delay = STAT_RX_FRAMING_ERR_8_out; + assign STAT_RX_FRAMING_ERR_9_delay = STAT_RX_FRAMING_ERR_9_out; + assign STAT_RX_FRAMING_ERR_VALID_0_delay = STAT_RX_FRAMING_ERR_VALID_0_out; + assign STAT_RX_FRAMING_ERR_VALID_10_delay = STAT_RX_FRAMING_ERR_VALID_10_out; + assign STAT_RX_FRAMING_ERR_VALID_11_delay = STAT_RX_FRAMING_ERR_VALID_11_out; + assign STAT_RX_FRAMING_ERR_VALID_12_delay = STAT_RX_FRAMING_ERR_VALID_12_out; + assign STAT_RX_FRAMING_ERR_VALID_13_delay = STAT_RX_FRAMING_ERR_VALID_13_out; + assign STAT_RX_FRAMING_ERR_VALID_14_delay = STAT_RX_FRAMING_ERR_VALID_14_out; + assign STAT_RX_FRAMING_ERR_VALID_15_delay = STAT_RX_FRAMING_ERR_VALID_15_out; + assign STAT_RX_FRAMING_ERR_VALID_16_delay = STAT_RX_FRAMING_ERR_VALID_16_out; + assign STAT_RX_FRAMING_ERR_VALID_17_delay = STAT_RX_FRAMING_ERR_VALID_17_out; + assign STAT_RX_FRAMING_ERR_VALID_18_delay = STAT_RX_FRAMING_ERR_VALID_18_out; + assign STAT_RX_FRAMING_ERR_VALID_19_delay = STAT_RX_FRAMING_ERR_VALID_19_out; + assign STAT_RX_FRAMING_ERR_VALID_1_delay = STAT_RX_FRAMING_ERR_VALID_1_out; + assign STAT_RX_FRAMING_ERR_VALID_2_delay = STAT_RX_FRAMING_ERR_VALID_2_out; + assign STAT_RX_FRAMING_ERR_VALID_3_delay = STAT_RX_FRAMING_ERR_VALID_3_out; + assign STAT_RX_FRAMING_ERR_VALID_4_delay = STAT_RX_FRAMING_ERR_VALID_4_out; + assign STAT_RX_FRAMING_ERR_VALID_5_delay = STAT_RX_FRAMING_ERR_VALID_5_out; + assign STAT_RX_FRAMING_ERR_VALID_6_delay = STAT_RX_FRAMING_ERR_VALID_6_out; + assign STAT_RX_FRAMING_ERR_VALID_7_delay = STAT_RX_FRAMING_ERR_VALID_7_out; + assign STAT_RX_FRAMING_ERR_VALID_8_delay = STAT_RX_FRAMING_ERR_VALID_8_out; + assign STAT_RX_FRAMING_ERR_VALID_9_delay = STAT_RX_FRAMING_ERR_VALID_9_out; + assign STAT_RX_GOT_SIGNAL_OS_delay = STAT_RX_GOT_SIGNAL_OS_out; + assign STAT_RX_HI_BER_delay = STAT_RX_HI_BER_out; + assign STAT_RX_INRANGEERR_delay = STAT_RX_INRANGEERR_out; + assign STAT_RX_INTERNAL_LOCAL_FAULT_delay = STAT_RX_INTERNAL_LOCAL_FAULT_out; + assign STAT_RX_JABBER_delay = STAT_RX_JABBER_out; + assign STAT_RX_LANE0_VLM_BIP7_VALID_delay = STAT_RX_LANE0_VLM_BIP7_VALID_out; + assign STAT_RX_LANE0_VLM_BIP7_delay = STAT_RX_LANE0_VLM_BIP7_out; + assign STAT_RX_LOCAL_FAULT_delay = STAT_RX_LOCAL_FAULT_out; + assign STAT_RX_MF_ERR_delay = STAT_RX_MF_ERR_out; + assign STAT_RX_MF_LEN_ERR_delay = STAT_RX_MF_LEN_ERR_out; + assign STAT_RX_MF_REPEAT_ERR_delay = STAT_RX_MF_REPEAT_ERR_out; + assign STAT_RX_MISALIGNED_delay = STAT_RX_MISALIGNED_out; + assign STAT_RX_MULTICAST_delay = STAT_RX_MULTICAST_out; + assign STAT_RX_OVERSIZE_delay = STAT_RX_OVERSIZE_out; + assign STAT_RX_PACKET_1024_1518_BYTES_delay = STAT_RX_PACKET_1024_1518_BYTES_out; + assign STAT_RX_PACKET_128_255_BYTES_delay = STAT_RX_PACKET_128_255_BYTES_out; + assign STAT_RX_PACKET_1519_1522_BYTES_delay = STAT_RX_PACKET_1519_1522_BYTES_out; + assign STAT_RX_PACKET_1523_1548_BYTES_delay = STAT_RX_PACKET_1523_1548_BYTES_out; + assign STAT_RX_PACKET_1549_2047_BYTES_delay = STAT_RX_PACKET_1549_2047_BYTES_out; + assign STAT_RX_PACKET_2048_4095_BYTES_delay = STAT_RX_PACKET_2048_4095_BYTES_out; + assign STAT_RX_PACKET_256_511_BYTES_delay = STAT_RX_PACKET_256_511_BYTES_out; + assign STAT_RX_PACKET_4096_8191_BYTES_delay = STAT_RX_PACKET_4096_8191_BYTES_out; + assign STAT_RX_PACKET_512_1023_BYTES_delay = STAT_RX_PACKET_512_1023_BYTES_out; + assign STAT_RX_PACKET_64_BYTES_delay = STAT_RX_PACKET_64_BYTES_out; + assign STAT_RX_PACKET_65_127_BYTES_delay = STAT_RX_PACKET_65_127_BYTES_out; + assign STAT_RX_PACKET_8192_9215_BYTES_delay = STAT_RX_PACKET_8192_9215_BYTES_out; + assign STAT_RX_PACKET_BAD_FCS_delay = STAT_RX_PACKET_BAD_FCS_out; + assign STAT_RX_PACKET_LARGE_delay = STAT_RX_PACKET_LARGE_out; + assign STAT_RX_PACKET_SMALL_delay = STAT_RX_PACKET_SMALL_out; + assign STAT_RX_PAUSE_QUANTA0_delay = STAT_RX_PAUSE_QUANTA0_out; + assign STAT_RX_PAUSE_QUANTA1_delay = STAT_RX_PAUSE_QUANTA1_out; + assign STAT_RX_PAUSE_QUANTA2_delay = STAT_RX_PAUSE_QUANTA2_out; + assign STAT_RX_PAUSE_QUANTA3_delay = STAT_RX_PAUSE_QUANTA3_out; + assign STAT_RX_PAUSE_QUANTA4_delay = STAT_RX_PAUSE_QUANTA4_out; + assign STAT_RX_PAUSE_QUANTA5_delay = STAT_RX_PAUSE_QUANTA5_out; + assign STAT_RX_PAUSE_QUANTA6_delay = STAT_RX_PAUSE_QUANTA6_out; + assign STAT_RX_PAUSE_QUANTA7_delay = STAT_RX_PAUSE_QUANTA7_out; + assign STAT_RX_PAUSE_QUANTA8_delay = STAT_RX_PAUSE_QUANTA8_out; + assign STAT_RX_PAUSE_REQ_delay = STAT_RX_PAUSE_REQ_out; + assign STAT_RX_PAUSE_VALID_delay = STAT_RX_PAUSE_VALID_out; + assign STAT_RX_PAUSE_delay = STAT_RX_PAUSE_out; + assign STAT_RX_RECEIVED_LOCAL_FAULT_delay = STAT_RX_RECEIVED_LOCAL_FAULT_out; + assign STAT_RX_REMOTE_FAULT_delay = STAT_RX_REMOTE_FAULT_out; + assign STAT_RX_STATUS_delay = STAT_RX_STATUS_out; + assign STAT_RX_STOMPED_FCS_delay = STAT_RX_STOMPED_FCS_out; + assign STAT_RX_SYNCED_ERR_delay = STAT_RX_SYNCED_ERR_out; + assign STAT_RX_SYNCED_delay = STAT_RX_SYNCED_out; + assign STAT_RX_TEST_PATTERN_MISMATCH_delay = STAT_RX_TEST_PATTERN_MISMATCH_out; + assign STAT_RX_TOOLONG_delay = STAT_RX_TOOLONG_out; + assign STAT_RX_TOTAL_BYTES_delay = STAT_RX_TOTAL_BYTES_out; + assign STAT_RX_TOTAL_GOOD_BYTES_delay = STAT_RX_TOTAL_GOOD_BYTES_out; + assign STAT_RX_TOTAL_GOOD_PACKETS_delay = STAT_RX_TOTAL_GOOD_PACKETS_out; + assign STAT_RX_TOTAL_PACKETS_delay = STAT_RX_TOTAL_PACKETS_out; + assign STAT_RX_TRUNCATED_delay = STAT_RX_TRUNCATED_out; + assign STAT_RX_UNDERSIZE_delay = STAT_RX_UNDERSIZE_out; + assign STAT_RX_UNICAST_delay = STAT_RX_UNICAST_out; + assign STAT_RX_USER_PAUSE_delay = STAT_RX_USER_PAUSE_out; + assign STAT_RX_VLAN_delay = STAT_RX_VLAN_out; + assign STAT_RX_VL_DEMUXED_delay = STAT_RX_VL_DEMUXED_out; + assign STAT_RX_VL_NUMBER_0_delay = STAT_RX_VL_NUMBER_0_out; + assign STAT_RX_VL_NUMBER_10_delay = STAT_RX_VL_NUMBER_10_out; + assign STAT_RX_VL_NUMBER_11_delay = STAT_RX_VL_NUMBER_11_out; + assign STAT_RX_VL_NUMBER_12_delay = STAT_RX_VL_NUMBER_12_out; + assign STAT_RX_VL_NUMBER_13_delay = STAT_RX_VL_NUMBER_13_out; + assign STAT_RX_VL_NUMBER_14_delay = STAT_RX_VL_NUMBER_14_out; + assign STAT_RX_VL_NUMBER_15_delay = STAT_RX_VL_NUMBER_15_out; + assign STAT_RX_VL_NUMBER_16_delay = STAT_RX_VL_NUMBER_16_out; + assign STAT_RX_VL_NUMBER_17_delay = STAT_RX_VL_NUMBER_17_out; + assign STAT_RX_VL_NUMBER_18_delay = STAT_RX_VL_NUMBER_18_out; + assign STAT_RX_VL_NUMBER_19_delay = STAT_RX_VL_NUMBER_19_out; + assign STAT_RX_VL_NUMBER_1_delay = STAT_RX_VL_NUMBER_1_out; + assign STAT_RX_VL_NUMBER_2_delay = STAT_RX_VL_NUMBER_2_out; + assign STAT_RX_VL_NUMBER_3_delay = STAT_RX_VL_NUMBER_3_out; + assign STAT_RX_VL_NUMBER_4_delay = STAT_RX_VL_NUMBER_4_out; + assign STAT_RX_VL_NUMBER_5_delay = STAT_RX_VL_NUMBER_5_out; + assign STAT_RX_VL_NUMBER_6_delay = STAT_RX_VL_NUMBER_6_out; + assign STAT_RX_VL_NUMBER_7_delay = STAT_RX_VL_NUMBER_7_out; + assign STAT_RX_VL_NUMBER_8_delay = STAT_RX_VL_NUMBER_8_out; + assign STAT_RX_VL_NUMBER_9_delay = STAT_RX_VL_NUMBER_9_out; + assign STAT_TX_BAD_FCS_delay = STAT_TX_BAD_FCS_out; + assign STAT_TX_BROADCAST_delay = STAT_TX_BROADCAST_out; + assign STAT_TX_FRAME_ERROR_delay = STAT_TX_FRAME_ERROR_out; + assign STAT_TX_LOCAL_FAULT_delay = STAT_TX_LOCAL_FAULT_out; + assign STAT_TX_MULTICAST_delay = STAT_TX_MULTICAST_out; + assign STAT_TX_PACKET_1024_1518_BYTES_delay = STAT_TX_PACKET_1024_1518_BYTES_out; + assign STAT_TX_PACKET_128_255_BYTES_delay = STAT_TX_PACKET_128_255_BYTES_out; + assign STAT_TX_PACKET_1519_1522_BYTES_delay = STAT_TX_PACKET_1519_1522_BYTES_out; + assign STAT_TX_PACKET_1523_1548_BYTES_delay = STAT_TX_PACKET_1523_1548_BYTES_out; + assign STAT_TX_PACKET_1549_2047_BYTES_delay = STAT_TX_PACKET_1549_2047_BYTES_out; + assign STAT_TX_PACKET_2048_4095_BYTES_delay = STAT_TX_PACKET_2048_4095_BYTES_out; + assign STAT_TX_PACKET_256_511_BYTES_delay = STAT_TX_PACKET_256_511_BYTES_out; + assign STAT_TX_PACKET_4096_8191_BYTES_delay = STAT_TX_PACKET_4096_8191_BYTES_out; + assign STAT_TX_PACKET_512_1023_BYTES_delay = STAT_TX_PACKET_512_1023_BYTES_out; + assign STAT_TX_PACKET_64_BYTES_delay = STAT_TX_PACKET_64_BYTES_out; + assign STAT_TX_PACKET_65_127_BYTES_delay = STAT_TX_PACKET_65_127_BYTES_out; + assign STAT_TX_PACKET_8192_9215_BYTES_delay = STAT_TX_PACKET_8192_9215_BYTES_out; + assign STAT_TX_PACKET_LARGE_delay = STAT_TX_PACKET_LARGE_out; + assign STAT_TX_PACKET_SMALL_delay = STAT_TX_PACKET_SMALL_out; + assign STAT_TX_PAUSE_VALID_delay = STAT_TX_PAUSE_VALID_out; + assign STAT_TX_PAUSE_delay = STAT_TX_PAUSE_out; + assign STAT_TX_PTP_FIFO_READ_ERROR_delay = STAT_TX_PTP_FIFO_READ_ERROR_out; + assign STAT_TX_PTP_FIFO_WRITE_ERROR_delay = STAT_TX_PTP_FIFO_WRITE_ERROR_out; + assign STAT_TX_TOTAL_BYTES_delay = STAT_TX_TOTAL_BYTES_out; + assign STAT_TX_TOTAL_GOOD_BYTES_delay = STAT_TX_TOTAL_GOOD_BYTES_out; + assign STAT_TX_TOTAL_GOOD_PACKETS_delay = STAT_TX_TOTAL_GOOD_PACKETS_out; + assign STAT_TX_TOTAL_PACKETS_delay = STAT_TX_TOTAL_PACKETS_out; + assign STAT_TX_UNICAST_delay = STAT_TX_UNICAST_out; + assign STAT_TX_USER_PAUSE_delay = STAT_TX_USER_PAUSE_out; + assign STAT_TX_VLAN_delay = STAT_TX_VLAN_out; + assign TX_OVFOUT_delay = TX_OVFOUT_out; + assign TX_PTP_PCSLANE_OUT_delay = TX_PTP_PCSLANE_OUT_out; + assign TX_PTP_TSTAMP_OUT_delay = TX_PTP_TSTAMP_OUT_out; + assign TX_PTP_TSTAMP_TAG_OUT_delay = TX_PTP_TSTAMP_TAG_OUT_out; + assign TX_PTP_TSTAMP_VALID_OUT_delay = TX_PTP_TSTAMP_VALID_OUT_out; + assign TX_RDYOUT_delay = TX_RDYOUT_out; + assign TX_SERDES_ALT_DATA0_delay = TX_SERDES_ALT_DATA0_out; + assign TX_SERDES_ALT_DATA1_delay = TX_SERDES_ALT_DATA1_out; + assign TX_SERDES_ALT_DATA2_delay = TX_SERDES_ALT_DATA2_out; + assign TX_SERDES_ALT_DATA3_delay = TX_SERDES_ALT_DATA3_out; + assign TX_SERDES_DATA0_delay = TX_SERDES_DATA0_out; + assign TX_SERDES_DATA1_delay = TX_SERDES_DATA1_out; + assign TX_SERDES_DATA2_delay = TX_SERDES_DATA2_out; + assign TX_SERDES_DATA3_delay = TX_SERDES_DATA3_out; + assign TX_SERDES_DATA4_delay = TX_SERDES_DATA4_out; + assign TX_SERDES_DATA5_delay = TX_SERDES_DATA5_out; + assign TX_SERDES_DATA6_delay = TX_SERDES_DATA6_out; + assign TX_SERDES_DATA7_delay = TX_SERDES_DATA7_out; + assign TX_SERDES_DATA8_delay = TX_SERDES_DATA8_out; + assign TX_SERDES_DATA9_delay = TX_SERDES_DATA9_out; + assign TX_UNFOUT_delay = TX_UNFOUT_out; + + assign CTL_CAUI4_MODE_in = CTL_CAUI4_MODE_delay; + assign CTL_RX_CHECK_ETYPE_GCP_in = CTL_RX_CHECK_ETYPE_GCP_delay; + assign CTL_RX_CHECK_ETYPE_GPP_in = CTL_RX_CHECK_ETYPE_GPP_delay; + assign CTL_RX_CHECK_ETYPE_PCP_in = CTL_RX_CHECK_ETYPE_PCP_delay; + assign CTL_RX_CHECK_ETYPE_PPP_in = CTL_RX_CHECK_ETYPE_PPP_delay; + assign CTL_RX_CHECK_MCAST_GCP_in = CTL_RX_CHECK_MCAST_GCP_delay; + assign CTL_RX_CHECK_MCAST_GPP_in = CTL_RX_CHECK_MCAST_GPP_delay; + assign CTL_RX_CHECK_MCAST_PCP_in = CTL_RX_CHECK_MCAST_PCP_delay; + assign CTL_RX_CHECK_MCAST_PPP_in = CTL_RX_CHECK_MCAST_PPP_delay; + assign CTL_RX_CHECK_OPCODE_GCP_in = CTL_RX_CHECK_OPCODE_GCP_delay; + assign CTL_RX_CHECK_OPCODE_GPP_in = CTL_RX_CHECK_OPCODE_GPP_delay; + assign CTL_RX_CHECK_OPCODE_PCP_in = CTL_RX_CHECK_OPCODE_PCP_delay; + assign CTL_RX_CHECK_OPCODE_PPP_in = CTL_RX_CHECK_OPCODE_PPP_delay; + assign CTL_RX_CHECK_SA_GCP_in = CTL_RX_CHECK_SA_GCP_delay; + assign CTL_RX_CHECK_SA_GPP_in = CTL_RX_CHECK_SA_GPP_delay; + assign CTL_RX_CHECK_SA_PCP_in = CTL_RX_CHECK_SA_PCP_delay; + assign CTL_RX_CHECK_SA_PPP_in = CTL_RX_CHECK_SA_PPP_delay; + assign CTL_RX_CHECK_UCAST_GCP_in = CTL_RX_CHECK_UCAST_GCP_delay; + assign CTL_RX_CHECK_UCAST_GPP_in = CTL_RX_CHECK_UCAST_GPP_delay; + assign CTL_RX_CHECK_UCAST_PCP_in = CTL_RX_CHECK_UCAST_PCP_delay; + assign CTL_RX_CHECK_UCAST_PPP_in = CTL_RX_CHECK_UCAST_PPP_delay; + assign CTL_RX_ENABLE_GCP_in = CTL_RX_ENABLE_GCP_delay; + assign CTL_RX_ENABLE_GPP_in = CTL_RX_ENABLE_GPP_delay; + assign CTL_RX_ENABLE_PCP_in = CTL_RX_ENABLE_PCP_delay; + assign CTL_RX_ENABLE_PPP_in = CTL_RX_ENABLE_PPP_delay; + assign CTL_RX_ENABLE_in = CTL_RX_ENABLE_delay; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay; + assign CTL_RX_PAUSE_ACK_in = CTL_RX_PAUSE_ACK_delay; + assign CTL_RX_PAUSE_ENABLE_in = CTL_RX_PAUSE_ENABLE_delay; + assign CTL_RX_SYSTEMTIMERIN_in = CTL_RX_SYSTEMTIMERIN_delay; + assign CTL_RX_TEST_PATTERN_in = CTL_RX_TEST_PATTERN_delay; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay; + assign CTL_TX_PAUSE_ENABLE_in = CTL_TX_PAUSE_ENABLE_delay; + assign CTL_TX_PAUSE_QUANTA0_in = CTL_TX_PAUSE_QUANTA0_delay; + assign CTL_TX_PAUSE_QUANTA1_in = CTL_TX_PAUSE_QUANTA1_delay; + assign CTL_TX_PAUSE_QUANTA2_in = CTL_TX_PAUSE_QUANTA2_delay; + assign CTL_TX_PAUSE_QUANTA3_in = CTL_TX_PAUSE_QUANTA3_delay; + assign CTL_TX_PAUSE_QUANTA4_in = CTL_TX_PAUSE_QUANTA4_delay; + assign CTL_TX_PAUSE_QUANTA5_in = CTL_TX_PAUSE_QUANTA5_delay; + assign CTL_TX_PAUSE_QUANTA6_in = CTL_TX_PAUSE_QUANTA6_delay; + assign CTL_TX_PAUSE_QUANTA7_in = CTL_TX_PAUSE_QUANTA7_delay; + assign CTL_TX_PAUSE_QUANTA8_in = CTL_TX_PAUSE_QUANTA8_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER0_in = CTL_TX_PAUSE_REFRESH_TIMER0_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER1_in = CTL_TX_PAUSE_REFRESH_TIMER1_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER2_in = CTL_TX_PAUSE_REFRESH_TIMER2_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER3_in = CTL_TX_PAUSE_REFRESH_TIMER3_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER4_in = CTL_TX_PAUSE_REFRESH_TIMER4_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER5_in = CTL_TX_PAUSE_REFRESH_TIMER5_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER6_in = CTL_TX_PAUSE_REFRESH_TIMER6_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER7_in = CTL_TX_PAUSE_REFRESH_TIMER7_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER8_in = CTL_TX_PAUSE_REFRESH_TIMER8_delay; + assign CTL_TX_PAUSE_REQ_in = CTL_TX_PAUSE_REQ_delay; + assign CTL_TX_PTP_VLANE_ADJUST_MODE_in = CTL_TX_PTP_VLANE_ADJUST_MODE_delay; + assign CTL_TX_RESEND_PAUSE_in = CTL_TX_RESEND_PAUSE_delay; + assign CTL_TX_SEND_IDLE_in = CTL_TX_SEND_IDLE_delay; + assign CTL_TX_SEND_RFI_in = CTL_TX_SEND_RFI_delay; + assign CTL_TX_SYSTEMTIMERIN_in = CTL_TX_SYSTEMTIMERIN_delay; + assign CTL_TX_TEST_PATTERN_in = CTL_TX_TEST_PATTERN_delay; + assign DRP_ADDR_in = DRP_ADDR_delay; + assign DRP_CLK_in = DRP_CLK_delay; + assign DRP_DI_in = DRP_DI_delay; + assign DRP_EN_in = DRP_EN_delay; + assign DRP_WE_in = DRP_WE_delay; + assign RX_CLK_in = RX_CLK_delay; + assign RX_RESET_in = RX_RESET_delay; + assign RX_SERDES_ALT_DATA0_in = RX_SERDES_ALT_DATA0_delay; + assign RX_SERDES_ALT_DATA1_in = RX_SERDES_ALT_DATA1_delay; + assign RX_SERDES_ALT_DATA2_in = RX_SERDES_ALT_DATA2_delay; + assign RX_SERDES_ALT_DATA3_in = RX_SERDES_ALT_DATA3_delay; + assign RX_SERDES_CLK_in = RX_SERDES_CLK_delay; + assign RX_SERDES_DATA0_in = RX_SERDES_DATA0_delay; + assign RX_SERDES_DATA1_in = RX_SERDES_DATA1_delay; + assign RX_SERDES_DATA2_in = RX_SERDES_DATA2_delay; + assign RX_SERDES_DATA3_in = RX_SERDES_DATA3_delay; + assign RX_SERDES_DATA4_in = RX_SERDES_DATA4_delay; + assign RX_SERDES_DATA5_in = RX_SERDES_DATA5_delay; + assign RX_SERDES_DATA6_in = RX_SERDES_DATA6_delay; + assign RX_SERDES_DATA7_in = RX_SERDES_DATA7_delay; + assign RX_SERDES_DATA8_in = RX_SERDES_DATA8_delay; + assign RX_SERDES_DATA9_in = RX_SERDES_DATA9_delay; + assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay; + assign TX_CLK_in = TX_CLK_delay; + assign TX_DATAIN0_in = TX_DATAIN0_delay; + assign TX_DATAIN1_in = TX_DATAIN1_delay; + assign TX_DATAIN2_in = TX_DATAIN2_delay; + assign TX_DATAIN3_in = TX_DATAIN3_delay; + assign TX_ENAIN0_in = TX_ENAIN0_delay; + assign TX_ENAIN1_in = TX_ENAIN1_delay; + assign TX_ENAIN2_in = TX_ENAIN2_delay; + assign TX_ENAIN3_in = TX_ENAIN3_delay; + assign TX_EOPIN0_in = TX_EOPIN0_delay; + assign TX_EOPIN1_in = TX_EOPIN1_delay; + assign TX_EOPIN2_in = TX_EOPIN2_delay; + assign TX_EOPIN3_in = TX_EOPIN3_delay; + assign TX_ERRIN0_in = TX_ERRIN0_delay; + assign TX_ERRIN1_in = TX_ERRIN1_delay; + assign TX_ERRIN2_in = TX_ERRIN2_delay; + assign TX_ERRIN3_in = TX_ERRIN3_delay; + assign TX_MTYIN0_in = TX_MTYIN0_delay; + assign TX_MTYIN1_in = TX_MTYIN1_delay; + assign TX_MTYIN2_in = TX_MTYIN2_delay; + assign TX_MTYIN3_in = TX_MTYIN3_delay; + assign TX_PTP_1588OP_IN_in = TX_PTP_1588OP_IN_delay; + assign TX_PTP_CHKSUM_OFFSET_IN_in = TX_PTP_CHKSUM_OFFSET_IN_delay; + assign TX_PTP_RXTSTAMP_IN_in = TX_PTP_RXTSTAMP_IN_delay; + assign TX_PTP_TAG_FIELD_IN_in = TX_PTP_TAG_FIELD_IN_delay; + assign TX_PTP_TSTAMP_OFFSET_IN_in = TX_PTP_TSTAMP_OFFSET_IN_delay; + assign TX_PTP_UPD_CHKSUM_IN_in = TX_PTP_UPD_CHKSUM_IN_delay; + assign TX_RESET_in = TX_RESET_delay; + assign TX_SOPIN0_in = TX_SOPIN0_delay; + assign TX_SOPIN1_in = TX_SOPIN1_delay; + assign TX_SOPIN2_in = TX_SOPIN2_delay; + assign TX_SOPIN3_in = TX_SOPIN3_delay; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CTL_PTP_TRANSPCLK_MODE_REG != "FALSE") && + (CTL_PTP_TRANSPCLK_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] CTL_PTP_TRANSPCLK_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_PTP_TRANSPCLK_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_ACK_REG != "TRUE") && + (CTL_RX_CHECK_ACK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-102] CTL_RX_CHECK_ACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_ACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_PREAMBLE_REG != "FALSE") && + (CTL_RX_CHECK_PREAMBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-103] CTL_RX_CHECK_PREAMBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_PREAMBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_SFD_REG != "FALSE") && + (CTL_RX_CHECK_SFD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] CTL_RX_CHECK_SFD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_SFD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_DELETE_FCS_REG != "TRUE") && + (CTL_RX_DELETE_FCS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-105] CTL_RX_DELETE_FCS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_DELETE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_FORWARD_CONTROL_REG != "FALSE") && + (CTL_RX_FORWARD_CONTROL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] CTL_RX_FORWARD_CONTROL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_FORWARD_CONTROL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_IGNORE_FCS_REG != "FALSE") && + (CTL_RX_IGNORE_FCS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] CTL_RX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_IGNORE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_MAX_PACKET_LEN_REG < 15'h0000) || (CTL_RX_MAX_PACKET_LEN_REG > 15'h3FFF))) begin + $display("Error: [Unisim %s-112] CTL_RX_MAX_PACKET_LEN attribute is set to %h. Legal values for this attribute are 15'h0000 to 15'h3FFF. Instance: %m", MODULE_NAME, CTL_RX_MAX_PACKET_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_PROCESS_LFI_REG != "FALSE") && + (CTL_RX_PROCESS_LFI_REG != "TRUE"))) begin + $display("Error: [Unisim %s-123] CTL_RX_PROCESS_LFI attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_PROCESS_LFI_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") && + (CTL_TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-145] CTL_TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_FCS_INS_ENABLE_REG != "TRUE") && + (CTL_TX_FCS_INS_ENABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-150] CTL_TX_FCS_INS_ENABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_TX_FCS_INS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_IGNORE_FCS_REG != "FALSE") && + (CTL_TX_IGNORE_FCS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-151] CTL_TX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_IGNORE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_PTP_1STEP_ENABLE_REG != "FALSE") && + (CTL_TX_PTP_1STEP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-154] CTL_TX_PTP_1STEP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_PTP_1STEP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != "2.0") && + (SIM_VERSION_REG != "1.0"))) begin + $display("Error: [Unisim %s-179] SIM_VERSION attribute is set to %s. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TEST_MODE_PIN_CHAR_REG != "FALSE") && + (TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-180] TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign SCAN_EN_in = 1'b0; //manual tie off + assign SCAN_IN_CMAC_in = 182'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign SCAN_IN_DRPCTRL_in = 13'b1111111111111; // tie off + assign TEST_MODE_in = 1'b0; //manual tie off + assign TEST_RESET_in = 1'b1; // tie off + +generate +if (SIM_VERSION == "2.0" ) begin : generate_block1 + SIP_CMAC_ES2 SIP_CMAC_INST ( + .CTL_PTP_TRANSPCLK_MODE (CTL_PTP_TRANSPCLK_MODE_REG), + .CTL_RX_CHECK_ACK (CTL_RX_CHECK_ACK_REG), + .CTL_RX_CHECK_PREAMBLE (CTL_RX_CHECK_PREAMBLE_REG), + .CTL_RX_CHECK_SFD (CTL_RX_CHECK_SFD_REG), + .CTL_RX_DELETE_FCS (CTL_RX_DELETE_FCS_REG), + .CTL_RX_ETYPE_GCP (CTL_RX_ETYPE_GCP_REG), + .CTL_RX_ETYPE_GPP (CTL_RX_ETYPE_GPP_REG), + .CTL_RX_ETYPE_PCP (CTL_RX_ETYPE_PCP_REG), + .CTL_RX_ETYPE_PPP (CTL_RX_ETYPE_PPP_REG), + .CTL_RX_FORWARD_CONTROL (CTL_RX_FORWARD_CONTROL_REG), + .CTL_RX_IGNORE_FCS (CTL_RX_IGNORE_FCS_REG), + .CTL_RX_MAX_PACKET_LEN (CTL_RX_MAX_PACKET_LEN_REG), + .CTL_RX_MIN_PACKET_LEN (CTL_RX_MIN_PACKET_LEN_REG), + .CTL_RX_OPCODE_GPP (CTL_RX_OPCODE_GPP_REG), + .CTL_RX_OPCODE_MAX_GCP (CTL_RX_OPCODE_MAX_GCP_REG), + .CTL_RX_OPCODE_MAX_PCP (CTL_RX_OPCODE_MAX_PCP_REG), + .CTL_RX_OPCODE_MIN_GCP (CTL_RX_OPCODE_MIN_GCP_REG), + .CTL_RX_OPCODE_MIN_PCP (CTL_RX_OPCODE_MIN_PCP_REG), + .CTL_RX_OPCODE_PPP (CTL_RX_OPCODE_PPP_REG), + .CTL_RX_PAUSE_DA_MCAST (CTL_RX_PAUSE_DA_MCAST_REG), + .CTL_RX_PAUSE_DA_UCAST (CTL_RX_PAUSE_DA_UCAST_REG), + .CTL_RX_PAUSE_SA (CTL_RX_PAUSE_SA_REG), + .CTL_RX_PROCESS_LFI (CTL_RX_PROCESS_LFI_REG), + .CTL_RX_VL_LENGTH_MINUS1 (CTL_RX_VL_LENGTH_MINUS1_REG), + .CTL_RX_VL_MARKER_ID0 (CTL_RX_VL_MARKER_ID0_REG), + .CTL_RX_VL_MARKER_ID1 (CTL_RX_VL_MARKER_ID1_REG), + .CTL_RX_VL_MARKER_ID10 (CTL_RX_VL_MARKER_ID10_REG), + .CTL_RX_VL_MARKER_ID11 (CTL_RX_VL_MARKER_ID11_REG), + .CTL_RX_VL_MARKER_ID12 (CTL_RX_VL_MARKER_ID12_REG), + .CTL_RX_VL_MARKER_ID13 (CTL_RX_VL_MARKER_ID13_REG), + .CTL_RX_VL_MARKER_ID14 (CTL_RX_VL_MARKER_ID14_REG), + .CTL_RX_VL_MARKER_ID15 (CTL_RX_VL_MARKER_ID15_REG), + .CTL_RX_VL_MARKER_ID16 (CTL_RX_VL_MARKER_ID16_REG), + .CTL_RX_VL_MARKER_ID17 (CTL_RX_VL_MARKER_ID17_REG), + .CTL_RX_VL_MARKER_ID18 (CTL_RX_VL_MARKER_ID18_REG), + .CTL_RX_VL_MARKER_ID19 (CTL_RX_VL_MARKER_ID19_REG), + .CTL_RX_VL_MARKER_ID2 (CTL_RX_VL_MARKER_ID2_REG), + .CTL_RX_VL_MARKER_ID3 (CTL_RX_VL_MARKER_ID3_REG), + .CTL_RX_VL_MARKER_ID4 (CTL_RX_VL_MARKER_ID4_REG), + .CTL_RX_VL_MARKER_ID5 (CTL_RX_VL_MARKER_ID5_REG), + .CTL_RX_VL_MARKER_ID6 (CTL_RX_VL_MARKER_ID6_REG), + .CTL_RX_VL_MARKER_ID7 (CTL_RX_VL_MARKER_ID7_REG), + .CTL_RX_VL_MARKER_ID8 (CTL_RX_VL_MARKER_ID8_REG), + .CTL_RX_VL_MARKER_ID9 (CTL_RX_VL_MARKER_ID9_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_DA_GPP (CTL_TX_DA_GPP_REG), + .CTL_TX_DA_PPP (CTL_TX_DA_PPP_REG), + .CTL_TX_ETHERTYPE_GPP (CTL_TX_ETHERTYPE_GPP_REG), + .CTL_TX_ETHERTYPE_PPP (CTL_TX_ETHERTYPE_PPP_REG), + .CTL_TX_FCS_INS_ENABLE (CTL_TX_FCS_INS_ENABLE_REG), + .CTL_TX_IGNORE_FCS (CTL_TX_IGNORE_FCS_REG), + .CTL_TX_OPCODE_GPP (CTL_TX_OPCODE_GPP_REG), + .CTL_TX_OPCODE_PPP (CTL_TX_OPCODE_PPP_REG), + .CTL_TX_PTP_1STEP_ENABLE (CTL_TX_PTP_1STEP_ENABLE_REG), + .CTL_TX_PTP_LATENCY_ADJUST (CTL_TX_PTP_LATENCY_ADJUST_REG), + .CTL_TX_SA_GPP (CTL_TX_SA_GPP_REG), + .CTL_TX_SA_PPP (CTL_TX_SA_PPP_REG), + .CTL_TX_VL_LENGTH_MINUS1 (CTL_TX_VL_LENGTH_MINUS1_REG), + .CTL_TX_VL_MARKER_ID0 (CTL_TX_VL_MARKER_ID0_REG), + .CTL_TX_VL_MARKER_ID1 (CTL_TX_VL_MARKER_ID1_REG), + .CTL_TX_VL_MARKER_ID10 (CTL_TX_VL_MARKER_ID10_REG), + .CTL_TX_VL_MARKER_ID11 (CTL_TX_VL_MARKER_ID11_REG), + .CTL_TX_VL_MARKER_ID12 (CTL_TX_VL_MARKER_ID12_REG), + .CTL_TX_VL_MARKER_ID13 (CTL_TX_VL_MARKER_ID13_REG), + .CTL_TX_VL_MARKER_ID14 (CTL_TX_VL_MARKER_ID14_REG), + .CTL_TX_VL_MARKER_ID15 (CTL_TX_VL_MARKER_ID15_REG), + .CTL_TX_VL_MARKER_ID16 (CTL_TX_VL_MARKER_ID16_REG), + .CTL_TX_VL_MARKER_ID17 (CTL_TX_VL_MARKER_ID17_REG), + .CTL_TX_VL_MARKER_ID18 (CTL_TX_VL_MARKER_ID18_REG), + .CTL_TX_VL_MARKER_ID19 (CTL_TX_VL_MARKER_ID19_REG), + .CTL_TX_VL_MARKER_ID2 (CTL_TX_VL_MARKER_ID2_REG), + .CTL_TX_VL_MARKER_ID3 (CTL_TX_VL_MARKER_ID3_REG), + .CTL_TX_VL_MARKER_ID4 (CTL_TX_VL_MARKER_ID4_REG), + .CTL_TX_VL_MARKER_ID5 (CTL_TX_VL_MARKER_ID5_REG), + .CTL_TX_VL_MARKER_ID6 (CTL_TX_VL_MARKER_ID6_REG), + .CTL_TX_VL_MARKER_ID7 (CTL_TX_VL_MARKER_ID7_REG), + .CTL_TX_VL_MARKER_ID8 (CTL_TX_VL_MARKER_ID8_REG), + .CTL_TX_VL_MARKER_ID9 (CTL_TX_VL_MARKER_ID9_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_LANE_ALIGNER_FILL_0 (RX_LANE_ALIGNER_FILL_0_out), + .RX_LANE_ALIGNER_FILL_1 (RX_LANE_ALIGNER_FILL_1_out), + .RX_LANE_ALIGNER_FILL_10 (RX_LANE_ALIGNER_FILL_10_out), + .RX_LANE_ALIGNER_FILL_11 (RX_LANE_ALIGNER_FILL_11_out), + .RX_LANE_ALIGNER_FILL_12 (RX_LANE_ALIGNER_FILL_12_out), + .RX_LANE_ALIGNER_FILL_13 (RX_LANE_ALIGNER_FILL_13_out), + .RX_LANE_ALIGNER_FILL_14 (RX_LANE_ALIGNER_FILL_14_out), + .RX_LANE_ALIGNER_FILL_15 (RX_LANE_ALIGNER_FILL_15_out), + .RX_LANE_ALIGNER_FILL_16 (RX_LANE_ALIGNER_FILL_16_out), + .RX_LANE_ALIGNER_FILL_17 (RX_LANE_ALIGNER_FILL_17_out), + .RX_LANE_ALIGNER_FILL_18 (RX_LANE_ALIGNER_FILL_18_out), + .RX_LANE_ALIGNER_FILL_19 (RX_LANE_ALIGNER_FILL_19_out), + .RX_LANE_ALIGNER_FILL_2 (RX_LANE_ALIGNER_FILL_2_out), + .RX_LANE_ALIGNER_FILL_3 (RX_LANE_ALIGNER_FILL_3_out), + .RX_LANE_ALIGNER_FILL_4 (RX_LANE_ALIGNER_FILL_4_out), + .RX_LANE_ALIGNER_FILL_5 (RX_LANE_ALIGNER_FILL_5_out), + .RX_LANE_ALIGNER_FILL_6 (RX_LANE_ALIGNER_FILL_6_out), + .RX_LANE_ALIGNER_FILL_7 (RX_LANE_ALIGNER_FILL_7_out), + .RX_LANE_ALIGNER_FILL_8 (RX_LANE_ALIGNER_FILL_8_out), + .RX_LANE_ALIGNER_FILL_9 (RX_LANE_ALIGNER_FILL_9_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_PTP_PCSLANE_OUT (RX_PTP_PCSLANE_OUT_out), + .RX_PTP_TSTAMP_OUT (RX_PTP_TSTAMP_OUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT_CMAC (SCAN_OUT_CMAC_out), + .SCAN_OUT_DRPCTRL (SCAN_OUT_DRPCTRL_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_CODE (STAT_RX_BAD_CODE_out), + .STAT_RX_BAD_FCS (STAT_RX_BAD_FCS_out), + .STAT_RX_BAD_PREAMBLE (STAT_RX_BAD_PREAMBLE_out), + .STAT_RX_BAD_SFD (STAT_RX_BAD_SFD_out), + .STAT_RX_BIP_ERR_0 (STAT_RX_BIP_ERR_0_out), + .STAT_RX_BIP_ERR_1 (STAT_RX_BIP_ERR_1_out), + .STAT_RX_BIP_ERR_10 (STAT_RX_BIP_ERR_10_out), + .STAT_RX_BIP_ERR_11 (STAT_RX_BIP_ERR_11_out), + .STAT_RX_BIP_ERR_12 (STAT_RX_BIP_ERR_12_out), + .STAT_RX_BIP_ERR_13 (STAT_RX_BIP_ERR_13_out), + .STAT_RX_BIP_ERR_14 (STAT_RX_BIP_ERR_14_out), + .STAT_RX_BIP_ERR_15 (STAT_RX_BIP_ERR_15_out), + .STAT_RX_BIP_ERR_16 (STAT_RX_BIP_ERR_16_out), + .STAT_RX_BIP_ERR_17 (STAT_RX_BIP_ERR_17_out), + .STAT_RX_BIP_ERR_18 (STAT_RX_BIP_ERR_18_out), + .STAT_RX_BIP_ERR_19 (STAT_RX_BIP_ERR_19_out), + .STAT_RX_BIP_ERR_2 (STAT_RX_BIP_ERR_2_out), + .STAT_RX_BIP_ERR_3 (STAT_RX_BIP_ERR_3_out), + .STAT_RX_BIP_ERR_4 (STAT_RX_BIP_ERR_4_out), + .STAT_RX_BIP_ERR_5 (STAT_RX_BIP_ERR_5_out), + .STAT_RX_BIP_ERR_6 (STAT_RX_BIP_ERR_6_out), + .STAT_RX_BIP_ERR_7 (STAT_RX_BIP_ERR_7_out), + .STAT_RX_BIP_ERR_8 (STAT_RX_BIP_ERR_8_out), + .STAT_RX_BIP_ERR_9 (STAT_RX_BIP_ERR_9_out), + .STAT_RX_BLOCK_LOCK (STAT_RX_BLOCK_LOCK_out), + .STAT_RX_BROADCAST (STAT_RX_BROADCAST_out), + .STAT_RX_FRAGMENT (STAT_RX_FRAGMENT_out), + .STAT_RX_FRAMING_ERR_0 (STAT_RX_FRAMING_ERR_0_out), + .STAT_RX_FRAMING_ERR_1 (STAT_RX_FRAMING_ERR_1_out), + .STAT_RX_FRAMING_ERR_10 (STAT_RX_FRAMING_ERR_10_out), + .STAT_RX_FRAMING_ERR_11 (STAT_RX_FRAMING_ERR_11_out), + .STAT_RX_FRAMING_ERR_12 (STAT_RX_FRAMING_ERR_12_out), + .STAT_RX_FRAMING_ERR_13 (STAT_RX_FRAMING_ERR_13_out), + .STAT_RX_FRAMING_ERR_14 (STAT_RX_FRAMING_ERR_14_out), + .STAT_RX_FRAMING_ERR_15 (STAT_RX_FRAMING_ERR_15_out), + .STAT_RX_FRAMING_ERR_16 (STAT_RX_FRAMING_ERR_16_out), + .STAT_RX_FRAMING_ERR_17 (STAT_RX_FRAMING_ERR_17_out), + .STAT_RX_FRAMING_ERR_18 (STAT_RX_FRAMING_ERR_18_out), + .STAT_RX_FRAMING_ERR_19 (STAT_RX_FRAMING_ERR_19_out), + .STAT_RX_FRAMING_ERR_2 (STAT_RX_FRAMING_ERR_2_out), + .STAT_RX_FRAMING_ERR_3 (STAT_RX_FRAMING_ERR_3_out), + .STAT_RX_FRAMING_ERR_4 (STAT_RX_FRAMING_ERR_4_out), + .STAT_RX_FRAMING_ERR_5 (STAT_RX_FRAMING_ERR_5_out), + .STAT_RX_FRAMING_ERR_6 (STAT_RX_FRAMING_ERR_6_out), + .STAT_RX_FRAMING_ERR_7 (STAT_RX_FRAMING_ERR_7_out), + .STAT_RX_FRAMING_ERR_8 (STAT_RX_FRAMING_ERR_8_out), + .STAT_RX_FRAMING_ERR_9 (STAT_RX_FRAMING_ERR_9_out), + .STAT_RX_FRAMING_ERR_VALID_0 (STAT_RX_FRAMING_ERR_VALID_0_out), + .STAT_RX_FRAMING_ERR_VALID_1 (STAT_RX_FRAMING_ERR_VALID_1_out), + .STAT_RX_FRAMING_ERR_VALID_10 (STAT_RX_FRAMING_ERR_VALID_10_out), + .STAT_RX_FRAMING_ERR_VALID_11 (STAT_RX_FRAMING_ERR_VALID_11_out), + .STAT_RX_FRAMING_ERR_VALID_12 (STAT_RX_FRAMING_ERR_VALID_12_out), + .STAT_RX_FRAMING_ERR_VALID_13 (STAT_RX_FRAMING_ERR_VALID_13_out), + .STAT_RX_FRAMING_ERR_VALID_14 (STAT_RX_FRAMING_ERR_VALID_14_out), + .STAT_RX_FRAMING_ERR_VALID_15 (STAT_RX_FRAMING_ERR_VALID_15_out), + .STAT_RX_FRAMING_ERR_VALID_16 (STAT_RX_FRAMING_ERR_VALID_16_out), + .STAT_RX_FRAMING_ERR_VALID_17 (STAT_RX_FRAMING_ERR_VALID_17_out), + .STAT_RX_FRAMING_ERR_VALID_18 (STAT_RX_FRAMING_ERR_VALID_18_out), + .STAT_RX_FRAMING_ERR_VALID_19 (STAT_RX_FRAMING_ERR_VALID_19_out), + .STAT_RX_FRAMING_ERR_VALID_2 (STAT_RX_FRAMING_ERR_VALID_2_out), + .STAT_RX_FRAMING_ERR_VALID_3 (STAT_RX_FRAMING_ERR_VALID_3_out), + .STAT_RX_FRAMING_ERR_VALID_4 (STAT_RX_FRAMING_ERR_VALID_4_out), + .STAT_RX_FRAMING_ERR_VALID_5 (STAT_RX_FRAMING_ERR_VALID_5_out), + .STAT_RX_FRAMING_ERR_VALID_6 (STAT_RX_FRAMING_ERR_VALID_6_out), + .STAT_RX_FRAMING_ERR_VALID_7 (STAT_RX_FRAMING_ERR_VALID_7_out), + .STAT_RX_FRAMING_ERR_VALID_8 (STAT_RX_FRAMING_ERR_VALID_8_out), + .STAT_RX_FRAMING_ERR_VALID_9 (STAT_RX_FRAMING_ERR_VALID_9_out), + .STAT_RX_GOT_SIGNAL_OS (STAT_RX_GOT_SIGNAL_OS_out), + .STAT_RX_HI_BER (STAT_RX_HI_BER_out), + .STAT_RX_INRANGEERR (STAT_RX_INRANGEERR_out), + .STAT_RX_INTERNAL_LOCAL_FAULT (STAT_RX_INTERNAL_LOCAL_FAULT_out), + .STAT_RX_JABBER (STAT_RX_JABBER_out), + .STAT_RX_LANE0_VLM_BIP7 (STAT_RX_LANE0_VLM_BIP7_out), + .STAT_RX_LANE0_VLM_BIP7_VALID (STAT_RX_LANE0_VLM_BIP7_VALID_out), + .STAT_RX_LOCAL_FAULT (STAT_RX_LOCAL_FAULT_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MULTICAST (STAT_RX_MULTICAST_out), + .STAT_RX_OVERSIZE (STAT_RX_OVERSIZE_out), + .STAT_RX_PACKET_1024_1518_BYTES (STAT_RX_PACKET_1024_1518_BYTES_out), + .STAT_RX_PACKET_128_255_BYTES (STAT_RX_PACKET_128_255_BYTES_out), + .STAT_RX_PACKET_1519_1522_BYTES (STAT_RX_PACKET_1519_1522_BYTES_out), + .STAT_RX_PACKET_1523_1548_BYTES (STAT_RX_PACKET_1523_1548_BYTES_out), + .STAT_RX_PACKET_1549_2047_BYTES (STAT_RX_PACKET_1549_2047_BYTES_out), + .STAT_RX_PACKET_2048_4095_BYTES (STAT_RX_PACKET_2048_4095_BYTES_out), + .STAT_RX_PACKET_256_511_BYTES (STAT_RX_PACKET_256_511_BYTES_out), + .STAT_RX_PACKET_4096_8191_BYTES (STAT_RX_PACKET_4096_8191_BYTES_out), + .STAT_RX_PACKET_512_1023_BYTES (STAT_RX_PACKET_512_1023_BYTES_out), + .STAT_RX_PACKET_64_BYTES (STAT_RX_PACKET_64_BYTES_out), + .STAT_RX_PACKET_65_127_BYTES (STAT_RX_PACKET_65_127_BYTES_out), + .STAT_RX_PACKET_8192_9215_BYTES (STAT_RX_PACKET_8192_9215_BYTES_out), + .STAT_RX_PACKET_BAD_FCS (STAT_RX_PACKET_BAD_FCS_out), + .STAT_RX_PACKET_LARGE (STAT_RX_PACKET_LARGE_out), + .STAT_RX_PACKET_SMALL (STAT_RX_PACKET_SMALL_out), + .STAT_RX_PAUSE (STAT_RX_PAUSE_out), + .STAT_RX_PAUSE_QUANTA0 (STAT_RX_PAUSE_QUANTA0_out), + .STAT_RX_PAUSE_QUANTA1 (STAT_RX_PAUSE_QUANTA1_out), + .STAT_RX_PAUSE_QUANTA2 (STAT_RX_PAUSE_QUANTA2_out), + .STAT_RX_PAUSE_QUANTA3 (STAT_RX_PAUSE_QUANTA3_out), + .STAT_RX_PAUSE_QUANTA4 (STAT_RX_PAUSE_QUANTA4_out), + .STAT_RX_PAUSE_QUANTA5 (STAT_RX_PAUSE_QUANTA5_out), + .STAT_RX_PAUSE_QUANTA6 (STAT_RX_PAUSE_QUANTA6_out), + .STAT_RX_PAUSE_QUANTA7 (STAT_RX_PAUSE_QUANTA7_out), + .STAT_RX_PAUSE_QUANTA8 (STAT_RX_PAUSE_QUANTA8_out), + .STAT_RX_PAUSE_REQ (STAT_RX_PAUSE_REQ_out), + .STAT_RX_PAUSE_VALID (STAT_RX_PAUSE_VALID_out), + .STAT_RX_RECEIVED_LOCAL_FAULT (STAT_RX_RECEIVED_LOCAL_FAULT_out), + .STAT_RX_REMOTE_FAULT (STAT_RX_REMOTE_FAULT_out), + .STAT_RX_STATUS (STAT_RX_STATUS_out), + .STAT_RX_STOMPED_FCS (STAT_RX_STOMPED_FCS_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_TEST_PATTERN_MISMATCH (STAT_RX_TEST_PATTERN_MISMATCH_out), + .STAT_RX_TOOLONG (STAT_RX_TOOLONG_out), + .STAT_RX_TOTAL_BYTES (STAT_RX_TOTAL_BYTES_out), + .STAT_RX_TOTAL_GOOD_BYTES (STAT_RX_TOTAL_GOOD_BYTES_out), + .STAT_RX_TOTAL_GOOD_PACKETS (STAT_RX_TOTAL_GOOD_PACKETS_out), + .STAT_RX_TOTAL_PACKETS (STAT_RX_TOTAL_PACKETS_out), + .STAT_RX_TRUNCATED (STAT_RX_TRUNCATED_out), + .STAT_RX_UNDERSIZE (STAT_RX_UNDERSIZE_out), + .STAT_RX_UNICAST (STAT_RX_UNICAST_out), + .STAT_RX_USER_PAUSE (STAT_RX_USER_PAUSE_out), + .STAT_RX_VLAN (STAT_RX_VLAN_out), + .STAT_RX_VL_DEMUXED (STAT_RX_VL_DEMUXED_out), + .STAT_RX_VL_NUMBER_0 (STAT_RX_VL_NUMBER_0_out), + .STAT_RX_VL_NUMBER_1 (STAT_RX_VL_NUMBER_1_out), + .STAT_RX_VL_NUMBER_10 (STAT_RX_VL_NUMBER_10_out), + .STAT_RX_VL_NUMBER_11 (STAT_RX_VL_NUMBER_11_out), + .STAT_RX_VL_NUMBER_12 (STAT_RX_VL_NUMBER_12_out), + .STAT_RX_VL_NUMBER_13 (STAT_RX_VL_NUMBER_13_out), + .STAT_RX_VL_NUMBER_14 (STAT_RX_VL_NUMBER_14_out), + .STAT_RX_VL_NUMBER_15 (STAT_RX_VL_NUMBER_15_out), + .STAT_RX_VL_NUMBER_16 (STAT_RX_VL_NUMBER_16_out), + .STAT_RX_VL_NUMBER_17 (STAT_RX_VL_NUMBER_17_out), + .STAT_RX_VL_NUMBER_18 (STAT_RX_VL_NUMBER_18_out), + .STAT_RX_VL_NUMBER_19 (STAT_RX_VL_NUMBER_19_out), + .STAT_RX_VL_NUMBER_2 (STAT_RX_VL_NUMBER_2_out), + .STAT_RX_VL_NUMBER_3 (STAT_RX_VL_NUMBER_3_out), + .STAT_RX_VL_NUMBER_4 (STAT_RX_VL_NUMBER_4_out), + .STAT_RX_VL_NUMBER_5 (STAT_RX_VL_NUMBER_5_out), + .STAT_RX_VL_NUMBER_6 (STAT_RX_VL_NUMBER_6_out), + .STAT_RX_VL_NUMBER_7 (STAT_RX_VL_NUMBER_7_out), + .STAT_RX_VL_NUMBER_8 (STAT_RX_VL_NUMBER_8_out), + .STAT_RX_VL_NUMBER_9 (STAT_RX_VL_NUMBER_9_out), + .STAT_TX_BAD_FCS (STAT_TX_BAD_FCS_out), + .STAT_TX_BROADCAST (STAT_TX_BROADCAST_out), + .STAT_TX_FRAME_ERROR (STAT_TX_FRAME_ERROR_out), + .STAT_TX_LOCAL_FAULT (STAT_TX_LOCAL_FAULT_out), + .STAT_TX_MULTICAST (STAT_TX_MULTICAST_out), + .STAT_TX_PACKET_1024_1518_BYTES (STAT_TX_PACKET_1024_1518_BYTES_out), + .STAT_TX_PACKET_128_255_BYTES (STAT_TX_PACKET_128_255_BYTES_out), + .STAT_TX_PACKET_1519_1522_BYTES (STAT_TX_PACKET_1519_1522_BYTES_out), + .STAT_TX_PACKET_1523_1548_BYTES (STAT_TX_PACKET_1523_1548_BYTES_out), + .STAT_TX_PACKET_1549_2047_BYTES (STAT_TX_PACKET_1549_2047_BYTES_out), + .STAT_TX_PACKET_2048_4095_BYTES (STAT_TX_PACKET_2048_4095_BYTES_out), + .STAT_TX_PACKET_256_511_BYTES (STAT_TX_PACKET_256_511_BYTES_out), + .STAT_TX_PACKET_4096_8191_BYTES (STAT_TX_PACKET_4096_8191_BYTES_out), + .STAT_TX_PACKET_512_1023_BYTES (STAT_TX_PACKET_512_1023_BYTES_out), + .STAT_TX_PACKET_64_BYTES (STAT_TX_PACKET_64_BYTES_out), + .STAT_TX_PACKET_65_127_BYTES (STAT_TX_PACKET_65_127_BYTES_out), + .STAT_TX_PACKET_8192_9215_BYTES (STAT_TX_PACKET_8192_9215_BYTES_out), + .STAT_TX_PACKET_LARGE (STAT_TX_PACKET_LARGE_out), + .STAT_TX_PACKET_SMALL (STAT_TX_PACKET_SMALL_out), + .STAT_TX_PAUSE (STAT_TX_PAUSE_out), + .STAT_TX_PAUSE_VALID (STAT_TX_PAUSE_VALID_out), + .STAT_TX_PTP_FIFO_READ_ERROR (STAT_TX_PTP_FIFO_READ_ERROR_out), + .STAT_TX_PTP_FIFO_WRITE_ERROR (STAT_TX_PTP_FIFO_WRITE_ERROR_out), + .STAT_TX_TOTAL_BYTES (STAT_TX_TOTAL_BYTES_out), + .STAT_TX_TOTAL_GOOD_BYTES (STAT_TX_TOTAL_GOOD_BYTES_out), + .STAT_TX_TOTAL_GOOD_PACKETS (STAT_TX_TOTAL_GOOD_PACKETS_out), + .STAT_TX_TOTAL_PACKETS (STAT_TX_TOTAL_PACKETS_out), + .STAT_TX_UNICAST (STAT_TX_UNICAST_out), + .STAT_TX_USER_PAUSE (STAT_TX_USER_PAUSE_out), + .STAT_TX_VLAN (STAT_TX_VLAN_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_PTP_PCSLANE_OUT (TX_PTP_PCSLANE_OUT_out), + .TX_PTP_TSTAMP_OUT (TX_PTP_TSTAMP_OUT_out), + .TX_PTP_TSTAMP_TAG_OUT (TX_PTP_TSTAMP_TAG_OUT_out), + .TX_PTP_TSTAMP_VALID_OUT (TX_PTP_TSTAMP_VALID_OUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_ALT_DATA0 (TX_SERDES_ALT_DATA0_out), + .TX_SERDES_ALT_DATA1 (TX_SERDES_ALT_DATA1_out), + .TX_SERDES_ALT_DATA2 (TX_SERDES_ALT_DATA2_out), + .TX_SERDES_ALT_DATA3 (TX_SERDES_ALT_DATA3_out), + .TX_SERDES_DATA0 (TX_SERDES_DATA0_out), + .TX_SERDES_DATA1 (TX_SERDES_DATA1_out), + .TX_SERDES_DATA2 (TX_SERDES_DATA2_out), + .TX_SERDES_DATA3 (TX_SERDES_DATA3_out), + .TX_SERDES_DATA4 (TX_SERDES_DATA4_out), + .TX_SERDES_DATA5 (TX_SERDES_DATA5_out), + .TX_SERDES_DATA6 (TX_SERDES_DATA6_out), + .TX_SERDES_DATA7 (TX_SERDES_DATA7_out), + .TX_SERDES_DATA8 (TX_SERDES_DATA8_out), + .TX_SERDES_DATA9 (TX_SERDES_DATA9_out), + .TX_UNFOUT (TX_UNFOUT_out), + .CTL_CAUI4_MODE (CTL_CAUI4_MODE_in), + .CTL_RX_CHECK_ETYPE_GCP (CTL_RX_CHECK_ETYPE_GCP_in), + .CTL_RX_CHECK_ETYPE_GPP (CTL_RX_CHECK_ETYPE_GPP_in), + .CTL_RX_CHECK_ETYPE_PCP (CTL_RX_CHECK_ETYPE_PCP_in), + .CTL_RX_CHECK_ETYPE_PPP (CTL_RX_CHECK_ETYPE_PPP_in), + .CTL_RX_CHECK_MCAST_GCP (CTL_RX_CHECK_MCAST_GCP_in), + .CTL_RX_CHECK_MCAST_GPP (CTL_RX_CHECK_MCAST_GPP_in), + .CTL_RX_CHECK_MCAST_PCP (CTL_RX_CHECK_MCAST_PCP_in), + .CTL_RX_CHECK_MCAST_PPP (CTL_RX_CHECK_MCAST_PPP_in), + .CTL_RX_CHECK_OPCODE_GCP (CTL_RX_CHECK_OPCODE_GCP_in), + .CTL_RX_CHECK_OPCODE_GPP (CTL_RX_CHECK_OPCODE_GPP_in), + .CTL_RX_CHECK_OPCODE_PCP (CTL_RX_CHECK_OPCODE_PCP_in), + .CTL_RX_CHECK_OPCODE_PPP (CTL_RX_CHECK_OPCODE_PPP_in), + .CTL_RX_CHECK_SA_GCP (CTL_RX_CHECK_SA_GCP_in), + .CTL_RX_CHECK_SA_GPP (CTL_RX_CHECK_SA_GPP_in), + .CTL_RX_CHECK_SA_PCP (CTL_RX_CHECK_SA_PCP_in), + .CTL_RX_CHECK_SA_PPP (CTL_RX_CHECK_SA_PPP_in), + .CTL_RX_CHECK_UCAST_GCP (CTL_RX_CHECK_UCAST_GCP_in), + .CTL_RX_CHECK_UCAST_GPP (CTL_RX_CHECK_UCAST_GPP_in), + .CTL_RX_CHECK_UCAST_PCP (CTL_RX_CHECK_UCAST_PCP_in), + .CTL_RX_CHECK_UCAST_PPP (CTL_RX_CHECK_UCAST_PPP_in), + .CTL_RX_ENABLE (CTL_RX_ENABLE_in), + .CTL_RX_ENABLE_GCP (CTL_RX_ENABLE_GCP_in), + .CTL_RX_ENABLE_GPP (CTL_RX_ENABLE_GPP_in), + .CTL_RX_ENABLE_PCP (CTL_RX_ENABLE_PCP_in), + .CTL_RX_ENABLE_PPP (CTL_RX_ENABLE_PPP_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_PAUSE_ACK (CTL_RX_PAUSE_ACK_in), + .CTL_RX_PAUSE_ENABLE (CTL_RX_PAUSE_ENABLE_in), + .CTL_RX_SYSTEMTIMERIN (CTL_RX_SYSTEMTIMERIN_in), + .CTL_RX_TEST_PATTERN (CTL_RX_TEST_PATTERN_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in), + .CTL_TX_PAUSE_ENABLE (CTL_TX_PAUSE_ENABLE_in), + .CTL_TX_PAUSE_QUANTA0 (CTL_TX_PAUSE_QUANTA0_in), + .CTL_TX_PAUSE_QUANTA1 (CTL_TX_PAUSE_QUANTA1_in), + .CTL_TX_PAUSE_QUANTA2 (CTL_TX_PAUSE_QUANTA2_in), + .CTL_TX_PAUSE_QUANTA3 (CTL_TX_PAUSE_QUANTA3_in), + .CTL_TX_PAUSE_QUANTA4 (CTL_TX_PAUSE_QUANTA4_in), + .CTL_TX_PAUSE_QUANTA5 (CTL_TX_PAUSE_QUANTA5_in), + .CTL_TX_PAUSE_QUANTA6 (CTL_TX_PAUSE_QUANTA6_in), + .CTL_TX_PAUSE_QUANTA7 (CTL_TX_PAUSE_QUANTA7_in), + .CTL_TX_PAUSE_QUANTA8 (CTL_TX_PAUSE_QUANTA8_in), + .CTL_TX_PAUSE_REFRESH_TIMER0 (CTL_TX_PAUSE_REFRESH_TIMER0_in), + .CTL_TX_PAUSE_REFRESH_TIMER1 (CTL_TX_PAUSE_REFRESH_TIMER1_in), + .CTL_TX_PAUSE_REFRESH_TIMER2 (CTL_TX_PAUSE_REFRESH_TIMER2_in), + .CTL_TX_PAUSE_REFRESH_TIMER3 (CTL_TX_PAUSE_REFRESH_TIMER3_in), + .CTL_TX_PAUSE_REFRESH_TIMER4 (CTL_TX_PAUSE_REFRESH_TIMER4_in), + .CTL_TX_PAUSE_REFRESH_TIMER5 (CTL_TX_PAUSE_REFRESH_TIMER5_in), + .CTL_TX_PAUSE_REFRESH_TIMER6 (CTL_TX_PAUSE_REFRESH_TIMER6_in), + .CTL_TX_PAUSE_REFRESH_TIMER7 (CTL_TX_PAUSE_REFRESH_TIMER7_in), + .CTL_TX_PAUSE_REFRESH_TIMER8 (CTL_TX_PAUSE_REFRESH_TIMER8_in), + .CTL_TX_PAUSE_REQ (CTL_TX_PAUSE_REQ_in), + .CTL_TX_PTP_VLANE_ADJUST_MODE (CTL_TX_PTP_VLANE_ADJUST_MODE_in), + .CTL_TX_RESEND_PAUSE (CTL_TX_RESEND_PAUSE_in), + .CTL_TX_SEND_IDLE (CTL_TX_SEND_IDLE_in), + .CTL_TX_SEND_RFI (CTL_TX_SEND_RFI_in), + .CTL_TX_SYSTEMTIMERIN (CTL_TX_SYSTEMTIMERIN_in), + .CTL_TX_TEST_PATTERN (CTL_TX_TEST_PATTERN_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .RX_CLK (RX_CLK_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_ALT_DATA0 (RX_SERDES_ALT_DATA0_in), + .RX_SERDES_ALT_DATA1 (RX_SERDES_ALT_DATA1_in), + .RX_SERDES_ALT_DATA2 (RX_SERDES_ALT_DATA2_in), + .RX_SERDES_ALT_DATA3 (RX_SERDES_ALT_DATA3_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA0 (RX_SERDES_DATA0_in), + .RX_SERDES_DATA1 (RX_SERDES_DATA1_in), + .RX_SERDES_DATA2 (RX_SERDES_DATA2_in), + .RX_SERDES_DATA3 (RX_SERDES_DATA3_in), + .RX_SERDES_DATA4 (RX_SERDES_DATA4_in), + .RX_SERDES_DATA5 (RX_SERDES_DATA5_in), + .RX_SERDES_DATA6 (RX_SERDES_DATA6_in), + .RX_SERDES_DATA7 (RX_SERDES_DATA7_in), + .RX_SERDES_DATA8 (RX_SERDES_DATA8_in), + .RX_SERDES_DATA9 (RX_SERDES_DATA9_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_EN (SCAN_EN_in), + .SCAN_IN_CMAC (SCAN_IN_CMAC_in), + .SCAN_IN_DRPCTRL (SCAN_IN_DRPCTRL_in), + .TEST_MODE (TEST_MODE_in), + .TEST_RESET (TEST_RESET_in), + .TX_CLK (TX_CLK_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_PTP_1588OP_IN (TX_PTP_1588OP_IN_in), + .TX_PTP_CHKSUM_OFFSET_IN (TX_PTP_CHKSUM_OFFSET_IN_in), + .TX_PTP_RXTSTAMP_IN (TX_PTP_RXTSTAMP_IN_in), + .TX_PTP_TAG_FIELD_IN (TX_PTP_TAG_FIELD_IN_in), + .TX_PTP_TSTAMP_OFFSET_IN (TX_PTP_TSTAMP_OFFSET_IN_in), + .TX_PTP_UPD_CHKSUM_IN (TX_PTP_UPD_CHKSUM_IN_in), + .TX_RESET (TX_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); +end else begin : generate_block1 + SIP_CMAC SIP_CMAC_INST ( + .CTL_PTP_TRANSPCLK_MODE (CTL_PTP_TRANSPCLK_MODE_REG), + .CTL_RX_CHECK_ACK (CTL_RX_CHECK_ACK_REG), + .CTL_RX_CHECK_PREAMBLE (CTL_RX_CHECK_PREAMBLE_REG), + .CTL_RX_CHECK_SFD (CTL_RX_CHECK_SFD_REG), + .CTL_RX_DELETE_FCS (CTL_RX_DELETE_FCS_REG), + .CTL_RX_ETYPE_GCP (CTL_RX_ETYPE_GCP_REG), + .CTL_RX_ETYPE_GPP (CTL_RX_ETYPE_GPP_REG), + .CTL_RX_ETYPE_PCP (CTL_RX_ETYPE_PCP_REG), + .CTL_RX_ETYPE_PPP (CTL_RX_ETYPE_PPP_REG), + .CTL_RX_FORWARD_CONTROL (CTL_RX_FORWARD_CONTROL_REG), + .CTL_RX_IGNORE_FCS (CTL_RX_IGNORE_FCS_REG), + .CTL_RX_MAX_PACKET_LEN (CTL_RX_MAX_PACKET_LEN_REG), + .CTL_RX_MIN_PACKET_LEN (CTL_RX_MIN_PACKET_LEN_REG), + .CTL_RX_OPCODE_GPP (CTL_RX_OPCODE_GPP_REG), + .CTL_RX_OPCODE_MAX_GCP (CTL_RX_OPCODE_MAX_GCP_REG), + .CTL_RX_OPCODE_MAX_PCP (CTL_RX_OPCODE_MAX_PCP_REG), + .CTL_RX_OPCODE_MIN_GCP (CTL_RX_OPCODE_MIN_GCP_REG), + .CTL_RX_OPCODE_MIN_PCP (CTL_RX_OPCODE_MIN_PCP_REG), + .CTL_RX_OPCODE_PPP (CTL_RX_OPCODE_PPP_REG), + .CTL_RX_PAUSE_DA_MCAST (CTL_RX_PAUSE_DA_MCAST_REG), + .CTL_RX_PAUSE_DA_UCAST (CTL_RX_PAUSE_DA_UCAST_REG), + .CTL_RX_PAUSE_SA (CTL_RX_PAUSE_SA_REG), + .CTL_RX_PROCESS_LFI (CTL_RX_PROCESS_LFI_REG), + .CTL_RX_VL_LENGTH_MINUS1 (CTL_RX_VL_LENGTH_MINUS1_REG), + .CTL_RX_VL_MARKER_ID0 (CTL_RX_VL_MARKER_ID0_REG), + .CTL_RX_VL_MARKER_ID1 (CTL_RX_VL_MARKER_ID1_REG), + .CTL_RX_VL_MARKER_ID10 (CTL_RX_VL_MARKER_ID10_REG), + .CTL_RX_VL_MARKER_ID11 (CTL_RX_VL_MARKER_ID11_REG), + .CTL_RX_VL_MARKER_ID12 (CTL_RX_VL_MARKER_ID12_REG), + .CTL_RX_VL_MARKER_ID13 (CTL_RX_VL_MARKER_ID13_REG), + .CTL_RX_VL_MARKER_ID14 (CTL_RX_VL_MARKER_ID14_REG), + .CTL_RX_VL_MARKER_ID15 (CTL_RX_VL_MARKER_ID15_REG), + .CTL_RX_VL_MARKER_ID16 (CTL_RX_VL_MARKER_ID16_REG), + .CTL_RX_VL_MARKER_ID17 (CTL_RX_VL_MARKER_ID17_REG), + .CTL_RX_VL_MARKER_ID18 (CTL_RX_VL_MARKER_ID18_REG), + .CTL_RX_VL_MARKER_ID19 (CTL_RX_VL_MARKER_ID19_REG), + .CTL_RX_VL_MARKER_ID2 (CTL_RX_VL_MARKER_ID2_REG), + .CTL_RX_VL_MARKER_ID3 (CTL_RX_VL_MARKER_ID3_REG), + .CTL_RX_VL_MARKER_ID4 (CTL_RX_VL_MARKER_ID4_REG), + .CTL_RX_VL_MARKER_ID5 (CTL_RX_VL_MARKER_ID5_REG), + .CTL_RX_VL_MARKER_ID6 (CTL_RX_VL_MARKER_ID6_REG), + .CTL_RX_VL_MARKER_ID7 (CTL_RX_VL_MARKER_ID7_REG), + .CTL_RX_VL_MARKER_ID8 (CTL_RX_VL_MARKER_ID8_REG), + .CTL_RX_VL_MARKER_ID9 (CTL_RX_VL_MARKER_ID9_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_DA_GPP (CTL_TX_DA_GPP_REG), + .CTL_TX_DA_PPP (CTL_TX_DA_PPP_REG), + .CTL_TX_ETHERTYPE_GPP (CTL_TX_ETHERTYPE_GPP_REG), + .CTL_TX_ETHERTYPE_PPP (CTL_TX_ETHERTYPE_PPP_REG), + .CTL_TX_FCS_INS_ENABLE (CTL_TX_FCS_INS_ENABLE_REG), + .CTL_TX_IGNORE_FCS (CTL_TX_IGNORE_FCS_REG), + .CTL_TX_OPCODE_GPP (CTL_TX_OPCODE_GPP_REG), + .CTL_TX_OPCODE_PPP (CTL_TX_OPCODE_PPP_REG), + .CTL_TX_PTP_1STEP_ENABLE (CTL_TX_PTP_1STEP_ENABLE_REG), + .CTL_TX_PTP_LATENCY_ADJUST (CTL_TX_PTP_LATENCY_ADJUST_REG), + .CTL_TX_SA_GPP (CTL_TX_SA_GPP_REG), + .CTL_TX_SA_PPP (CTL_TX_SA_PPP_REG), + .CTL_TX_VL_LENGTH_MINUS1 (CTL_TX_VL_LENGTH_MINUS1_REG), + .CTL_TX_VL_MARKER_ID0 (CTL_TX_VL_MARKER_ID0_REG), + .CTL_TX_VL_MARKER_ID1 (CTL_TX_VL_MARKER_ID1_REG), + .CTL_TX_VL_MARKER_ID10 (CTL_TX_VL_MARKER_ID10_REG), + .CTL_TX_VL_MARKER_ID11 (CTL_TX_VL_MARKER_ID11_REG), + .CTL_TX_VL_MARKER_ID12 (CTL_TX_VL_MARKER_ID12_REG), + .CTL_TX_VL_MARKER_ID13 (CTL_TX_VL_MARKER_ID13_REG), + .CTL_TX_VL_MARKER_ID14 (CTL_TX_VL_MARKER_ID14_REG), + .CTL_TX_VL_MARKER_ID15 (CTL_TX_VL_MARKER_ID15_REG), + .CTL_TX_VL_MARKER_ID16 (CTL_TX_VL_MARKER_ID16_REG), + .CTL_TX_VL_MARKER_ID17 (CTL_TX_VL_MARKER_ID17_REG), + .CTL_TX_VL_MARKER_ID18 (CTL_TX_VL_MARKER_ID18_REG), + .CTL_TX_VL_MARKER_ID19 (CTL_TX_VL_MARKER_ID19_REG), + .CTL_TX_VL_MARKER_ID2 (CTL_TX_VL_MARKER_ID2_REG), + .CTL_TX_VL_MARKER_ID3 (CTL_TX_VL_MARKER_ID3_REG), + .CTL_TX_VL_MARKER_ID4 (CTL_TX_VL_MARKER_ID4_REG), + .CTL_TX_VL_MARKER_ID5 (CTL_TX_VL_MARKER_ID5_REG), + .CTL_TX_VL_MARKER_ID6 (CTL_TX_VL_MARKER_ID6_REG), + .CTL_TX_VL_MARKER_ID7 (CTL_TX_VL_MARKER_ID7_REG), + .CTL_TX_VL_MARKER_ID8 (CTL_TX_VL_MARKER_ID8_REG), + .CTL_TX_VL_MARKER_ID9 (CTL_TX_VL_MARKER_ID9_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_LANE_ALIGNER_FILL_0 (RX_LANE_ALIGNER_FILL_0_out), + .RX_LANE_ALIGNER_FILL_1 (RX_LANE_ALIGNER_FILL_1_out), + .RX_LANE_ALIGNER_FILL_10 (RX_LANE_ALIGNER_FILL_10_out), + .RX_LANE_ALIGNER_FILL_11 (RX_LANE_ALIGNER_FILL_11_out), + .RX_LANE_ALIGNER_FILL_12 (RX_LANE_ALIGNER_FILL_12_out), + .RX_LANE_ALIGNER_FILL_13 (RX_LANE_ALIGNER_FILL_13_out), + .RX_LANE_ALIGNER_FILL_14 (RX_LANE_ALIGNER_FILL_14_out), + .RX_LANE_ALIGNER_FILL_15 (RX_LANE_ALIGNER_FILL_15_out), + .RX_LANE_ALIGNER_FILL_16 (RX_LANE_ALIGNER_FILL_16_out), + .RX_LANE_ALIGNER_FILL_17 (RX_LANE_ALIGNER_FILL_17_out), + .RX_LANE_ALIGNER_FILL_18 (RX_LANE_ALIGNER_FILL_18_out), + .RX_LANE_ALIGNER_FILL_19 (RX_LANE_ALIGNER_FILL_19_out), + .RX_LANE_ALIGNER_FILL_2 (RX_LANE_ALIGNER_FILL_2_out), + .RX_LANE_ALIGNER_FILL_3 (RX_LANE_ALIGNER_FILL_3_out), + .RX_LANE_ALIGNER_FILL_4 (RX_LANE_ALIGNER_FILL_4_out), + .RX_LANE_ALIGNER_FILL_5 (RX_LANE_ALIGNER_FILL_5_out), + .RX_LANE_ALIGNER_FILL_6 (RX_LANE_ALIGNER_FILL_6_out), + .RX_LANE_ALIGNER_FILL_7 (RX_LANE_ALIGNER_FILL_7_out), + .RX_LANE_ALIGNER_FILL_8 (RX_LANE_ALIGNER_FILL_8_out), + .RX_LANE_ALIGNER_FILL_9 (RX_LANE_ALIGNER_FILL_9_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_PTP_PCSLANE_OUT (RX_PTP_PCSLANE_OUT_out), + .RX_PTP_TSTAMP_OUT (RX_PTP_TSTAMP_OUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT_CMAC (SCAN_OUT_CMAC_out), + .SCAN_OUT_DRPCTRL (SCAN_OUT_DRPCTRL_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_CODE (STAT_RX_BAD_CODE_out), + .STAT_RX_BAD_FCS (STAT_RX_BAD_FCS_out), + .STAT_RX_BAD_PREAMBLE (STAT_RX_BAD_PREAMBLE_out), + .STAT_RX_BAD_SFD (STAT_RX_BAD_SFD_out), + .STAT_RX_BIP_ERR_0 (STAT_RX_BIP_ERR_0_out), + .STAT_RX_BIP_ERR_1 (STAT_RX_BIP_ERR_1_out), + .STAT_RX_BIP_ERR_10 (STAT_RX_BIP_ERR_10_out), + .STAT_RX_BIP_ERR_11 (STAT_RX_BIP_ERR_11_out), + .STAT_RX_BIP_ERR_12 (STAT_RX_BIP_ERR_12_out), + .STAT_RX_BIP_ERR_13 (STAT_RX_BIP_ERR_13_out), + .STAT_RX_BIP_ERR_14 (STAT_RX_BIP_ERR_14_out), + .STAT_RX_BIP_ERR_15 (STAT_RX_BIP_ERR_15_out), + .STAT_RX_BIP_ERR_16 (STAT_RX_BIP_ERR_16_out), + .STAT_RX_BIP_ERR_17 (STAT_RX_BIP_ERR_17_out), + .STAT_RX_BIP_ERR_18 (STAT_RX_BIP_ERR_18_out), + .STAT_RX_BIP_ERR_19 (STAT_RX_BIP_ERR_19_out), + .STAT_RX_BIP_ERR_2 (STAT_RX_BIP_ERR_2_out), + .STAT_RX_BIP_ERR_3 (STAT_RX_BIP_ERR_3_out), + .STAT_RX_BIP_ERR_4 (STAT_RX_BIP_ERR_4_out), + .STAT_RX_BIP_ERR_5 (STAT_RX_BIP_ERR_5_out), + .STAT_RX_BIP_ERR_6 (STAT_RX_BIP_ERR_6_out), + .STAT_RX_BIP_ERR_7 (STAT_RX_BIP_ERR_7_out), + .STAT_RX_BIP_ERR_8 (STAT_RX_BIP_ERR_8_out), + .STAT_RX_BIP_ERR_9 (STAT_RX_BIP_ERR_9_out), + .STAT_RX_BLOCK_LOCK (STAT_RX_BLOCK_LOCK_out), + .STAT_RX_BROADCAST (STAT_RX_BROADCAST_out), + .STAT_RX_FRAGMENT (STAT_RX_FRAGMENT_out), + .STAT_RX_FRAMING_ERR_0 (STAT_RX_FRAMING_ERR_0_out), + .STAT_RX_FRAMING_ERR_1 (STAT_RX_FRAMING_ERR_1_out), + .STAT_RX_FRAMING_ERR_10 (STAT_RX_FRAMING_ERR_10_out), + .STAT_RX_FRAMING_ERR_11 (STAT_RX_FRAMING_ERR_11_out), + .STAT_RX_FRAMING_ERR_12 (STAT_RX_FRAMING_ERR_12_out), + .STAT_RX_FRAMING_ERR_13 (STAT_RX_FRAMING_ERR_13_out), + .STAT_RX_FRAMING_ERR_14 (STAT_RX_FRAMING_ERR_14_out), + .STAT_RX_FRAMING_ERR_15 (STAT_RX_FRAMING_ERR_15_out), + .STAT_RX_FRAMING_ERR_16 (STAT_RX_FRAMING_ERR_16_out), + .STAT_RX_FRAMING_ERR_17 (STAT_RX_FRAMING_ERR_17_out), + .STAT_RX_FRAMING_ERR_18 (STAT_RX_FRAMING_ERR_18_out), + .STAT_RX_FRAMING_ERR_19 (STAT_RX_FRAMING_ERR_19_out), + .STAT_RX_FRAMING_ERR_2 (STAT_RX_FRAMING_ERR_2_out), + .STAT_RX_FRAMING_ERR_3 (STAT_RX_FRAMING_ERR_3_out), + .STAT_RX_FRAMING_ERR_4 (STAT_RX_FRAMING_ERR_4_out), + .STAT_RX_FRAMING_ERR_5 (STAT_RX_FRAMING_ERR_5_out), + .STAT_RX_FRAMING_ERR_6 (STAT_RX_FRAMING_ERR_6_out), + .STAT_RX_FRAMING_ERR_7 (STAT_RX_FRAMING_ERR_7_out), + .STAT_RX_FRAMING_ERR_8 (STAT_RX_FRAMING_ERR_8_out), + .STAT_RX_FRAMING_ERR_9 (STAT_RX_FRAMING_ERR_9_out), + .STAT_RX_FRAMING_ERR_VALID_0 (STAT_RX_FRAMING_ERR_VALID_0_out), + .STAT_RX_FRAMING_ERR_VALID_1 (STAT_RX_FRAMING_ERR_VALID_1_out), + .STAT_RX_FRAMING_ERR_VALID_10 (STAT_RX_FRAMING_ERR_VALID_10_out), + .STAT_RX_FRAMING_ERR_VALID_11 (STAT_RX_FRAMING_ERR_VALID_11_out), + .STAT_RX_FRAMING_ERR_VALID_12 (STAT_RX_FRAMING_ERR_VALID_12_out), + .STAT_RX_FRAMING_ERR_VALID_13 (STAT_RX_FRAMING_ERR_VALID_13_out), + .STAT_RX_FRAMING_ERR_VALID_14 (STAT_RX_FRAMING_ERR_VALID_14_out), + .STAT_RX_FRAMING_ERR_VALID_15 (STAT_RX_FRAMING_ERR_VALID_15_out), + .STAT_RX_FRAMING_ERR_VALID_16 (STAT_RX_FRAMING_ERR_VALID_16_out), + .STAT_RX_FRAMING_ERR_VALID_17 (STAT_RX_FRAMING_ERR_VALID_17_out), + .STAT_RX_FRAMING_ERR_VALID_18 (STAT_RX_FRAMING_ERR_VALID_18_out), + .STAT_RX_FRAMING_ERR_VALID_19 (STAT_RX_FRAMING_ERR_VALID_19_out), + .STAT_RX_FRAMING_ERR_VALID_2 (STAT_RX_FRAMING_ERR_VALID_2_out), + .STAT_RX_FRAMING_ERR_VALID_3 (STAT_RX_FRAMING_ERR_VALID_3_out), + .STAT_RX_FRAMING_ERR_VALID_4 (STAT_RX_FRAMING_ERR_VALID_4_out), + .STAT_RX_FRAMING_ERR_VALID_5 (STAT_RX_FRAMING_ERR_VALID_5_out), + .STAT_RX_FRAMING_ERR_VALID_6 (STAT_RX_FRAMING_ERR_VALID_6_out), + .STAT_RX_FRAMING_ERR_VALID_7 (STAT_RX_FRAMING_ERR_VALID_7_out), + .STAT_RX_FRAMING_ERR_VALID_8 (STAT_RX_FRAMING_ERR_VALID_8_out), + .STAT_RX_FRAMING_ERR_VALID_9 (STAT_RX_FRAMING_ERR_VALID_9_out), + .STAT_RX_GOT_SIGNAL_OS (STAT_RX_GOT_SIGNAL_OS_out), + .STAT_RX_HI_BER (STAT_RX_HI_BER_out), + .STAT_RX_INRANGEERR (STAT_RX_INRANGEERR_out), + .STAT_RX_INTERNAL_LOCAL_FAULT (STAT_RX_INTERNAL_LOCAL_FAULT_out), + .STAT_RX_JABBER (STAT_RX_JABBER_out), + .STAT_RX_LANE0_VLM_BIP7 (STAT_RX_LANE0_VLM_BIP7_out), + .STAT_RX_LANE0_VLM_BIP7_VALID (STAT_RX_LANE0_VLM_BIP7_VALID_out), + .STAT_RX_LOCAL_FAULT (STAT_RX_LOCAL_FAULT_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MULTICAST (STAT_RX_MULTICAST_out), + .STAT_RX_OVERSIZE (STAT_RX_OVERSIZE_out), + .STAT_RX_PACKET_1024_1518_BYTES (STAT_RX_PACKET_1024_1518_BYTES_out), + .STAT_RX_PACKET_128_255_BYTES (STAT_RX_PACKET_128_255_BYTES_out), + .STAT_RX_PACKET_1519_1522_BYTES (STAT_RX_PACKET_1519_1522_BYTES_out), + .STAT_RX_PACKET_1523_1548_BYTES (STAT_RX_PACKET_1523_1548_BYTES_out), + .STAT_RX_PACKET_1549_2047_BYTES (STAT_RX_PACKET_1549_2047_BYTES_out), + .STAT_RX_PACKET_2048_4095_BYTES (STAT_RX_PACKET_2048_4095_BYTES_out), + .STAT_RX_PACKET_256_511_BYTES (STAT_RX_PACKET_256_511_BYTES_out), + .STAT_RX_PACKET_4096_8191_BYTES (STAT_RX_PACKET_4096_8191_BYTES_out), + .STAT_RX_PACKET_512_1023_BYTES (STAT_RX_PACKET_512_1023_BYTES_out), + .STAT_RX_PACKET_64_BYTES (STAT_RX_PACKET_64_BYTES_out), + .STAT_RX_PACKET_65_127_BYTES (STAT_RX_PACKET_65_127_BYTES_out), + .STAT_RX_PACKET_8192_9215_BYTES (STAT_RX_PACKET_8192_9215_BYTES_out), + .STAT_RX_PACKET_BAD_FCS (STAT_RX_PACKET_BAD_FCS_out), + .STAT_RX_PACKET_LARGE (STAT_RX_PACKET_LARGE_out), + .STAT_RX_PACKET_SMALL (STAT_RX_PACKET_SMALL_out), + .STAT_RX_PAUSE (STAT_RX_PAUSE_out), + .STAT_RX_PAUSE_QUANTA0 (STAT_RX_PAUSE_QUANTA0_out), + .STAT_RX_PAUSE_QUANTA1 (STAT_RX_PAUSE_QUANTA1_out), + .STAT_RX_PAUSE_QUANTA2 (STAT_RX_PAUSE_QUANTA2_out), + .STAT_RX_PAUSE_QUANTA3 (STAT_RX_PAUSE_QUANTA3_out), + .STAT_RX_PAUSE_QUANTA4 (STAT_RX_PAUSE_QUANTA4_out), + .STAT_RX_PAUSE_QUANTA5 (STAT_RX_PAUSE_QUANTA5_out), + .STAT_RX_PAUSE_QUANTA6 (STAT_RX_PAUSE_QUANTA6_out), + .STAT_RX_PAUSE_QUANTA7 (STAT_RX_PAUSE_QUANTA7_out), + .STAT_RX_PAUSE_QUANTA8 (STAT_RX_PAUSE_QUANTA8_out), + .STAT_RX_PAUSE_REQ (STAT_RX_PAUSE_REQ_out), + .STAT_RX_PAUSE_VALID (STAT_RX_PAUSE_VALID_out), + .STAT_RX_RECEIVED_LOCAL_FAULT (STAT_RX_RECEIVED_LOCAL_FAULT_out), + .STAT_RX_REMOTE_FAULT (STAT_RX_REMOTE_FAULT_out), + .STAT_RX_STATUS (STAT_RX_STATUS_out), + .STAT_RX_STOMPED_FCS (STAT_RX_STOMPED_FCS_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_TEST_PATTERN_MISMATCH (STAT_RX_TEST_PATTERN_MISMATCH_out), + .STAT_RX_TOOLONG (STAT_RX_TOOLONG_out), + .STAT_RX_TOTAL_BYTES (STAT_RX_TOTAL_BYTES_out), + .STAT_RX_TOTAL_GOOD_BYTES (STAT_RX_TOTAL_GOOD_BYTES_out), + .STAT_RX_TOTAL_GOOD_PACKETS (STAT_RX_TOTAL_GOOD_PACKETS_out), + .STAT_RX_TOTAL_PACKETS (STAT_RX_TOTAL_PACKETS_out), + .STAT_RX_TRUNCATED (STAT_RX_TRUNCATED_out), + .STAT_RX_UNDERSIZE (STAT_RX_UNDERSIZE_out), + .STAT_RX_UNICAST (STAT_RX_UNICAST_out), + .STAT_RX_USER_PAUSE (STAT_RX_USER_PAUSE_out), + .STAT_RX_VLAN (STAT_RX_VLAN_out), + .STAT_RX_VL_DEMUXED (STAT_RX_VL_DEMUXED_out), + .STAT_RX_VL_NUMBER_0 (STAT_RX_VL_NUMBER_0_out), + .STAT_RX_VL_NUMBER_1 (STAT_RX_VL_NUMBER_1_out), + .STAT_RX_VL_NUMBER_10 (STAT_RX_VL_NUMBER_10_out), + .STAT_RX_VL_NUMBER_11 (STAT_RX_VL_NUMBER_11_out), + .STAT_RX_VL_NUMBER_12 (STAT_RX_VL_NUMBER_12_out), + .STAT_RX_VL_NUMBER_13 (STAT_RX_VL_NUMBER_13_out), + .STAT_RX_VL_NUMBER_14 (STAT_RX_VL_NUMBER_14_out), + .STAT_RX_VL_NUMBER_15 (STAT_RX_VL_NUMBER_15_out), + .STAT_RX_VL_NUMBER_16 (STAT_RX_VL_NUMBER_16_out), + .STAT_RX_VL_NUMBER_17 (STAT_RX_VL_NUMBER_17_out), + .STAT_RX_VL_NUMBER_18 (STAT_RX_VL_NUMBER_18_out), + .STAT_RX_VL_NUMBER_19 (STAT_RX_VL_NUMBER_19_out), + .STAT_RX_VL_NUMBER_2 (STAT_RX_VL_NUMBER_2_out), + .STAT_RX_VL_NUMBER_3 (STAT_RX_VL_NUMBER_3_out), + .STAT_RX_VL_NUMBER_4 (STAT_RX_VL_NUMBER_4_out), + .STAT_RX_VL_NUMBER_5 (STAT_RX_VL_NUMBER_5_out), + .STAT_RX_VL_NUMBER_6 (STAT_RX_VL_NUMBER_6_out), + .STAT_RX_VL_NUMBER_7 (STAT_RX_VL_NUMBER_7_out), + .STAT_RX_VL_NUMBER_8 (STAT_RX_VL_NUMBER_8_out), + .STAT_RX_VL_NUMBER_9 (STAT_RX_VL_NUMBER_9_out), + .STAT_TX_BAD_FCS (STAT_TX_BAD_FCS_out), + .STAT_TX_BROADCAST (STAT_TX_BROADCAST_out), + .STAT_TX_FRAME_ERROR (STAT_TX_FRAME_ERROR_out), + .STAT_TX_LOCAL_FAULT (STAT_TX_LOCAL_FAULT_out), + .STAT_TX_MULTICAST (STAT_TX_MULTICAST_out), + .STAT_TX_PACKET_1024_1518_BYTES (STAT_TX_PACKET_1024_1518_BYTES_out), + .STAT_TX_PACKET_128_255_BYTES (STAT_TX_PACKET_128_255_BYTES_out), + .STAT_TX_PACKET_1519_1522_BYTES (STAT_TX_PACKET_1519_1522_BYTES_out), + .STAT_TX_PACKET_1523_1548_BYTES (STAT_TX_PACKET_1523_1548_BYTES_out), + .STAT_TX_PACKET_1549_2047_BYTES (STAT_TX_PACKET_1549_2047_BYTES_out), + .STAT_TX_PACKET_2048_4095_BYTES (STAT_TX_PACKET_2048_4095_BYTES_out), + .STAT_TX_PACKET_256_511_BYTES (STAT_TX_PACKET_256_511_BYTES_out), + .STAT_TX_PACKET_4096_8191_BYTES (STAT_TX_PACKET_4096_8191_BYTES_out), + .STAT_TX_PACKET_512_1023_BYTES (STAT_TX_PACKET_512_1023_BYTES_out), + .STAT_TX_PACKET_64_BYTES (STAT_TX_PACKET_64_BYTES_out), + .STAT_TX_PACKET_65_127_BYTES (STAT_TX_PACKET_65_127_BYTES_out), + .STAT_TX_PACKET_8192_9215_BYTES (STAT_TX_PACKET_8192_9215_BYTES_out), + .STAT_TX_PACKET_LARGE (STAT_TX_PACKET_LARGE_out), + .STAT_TX_PACKET_SMALL (STAT_TX_PACKET_SMALL_out), + .STAT_TX_PAUSE (STAT_TX_PAUSE_out), + .STAT_TX_PAUSE_VALID (STAT_TX_PAUSE_VALID_out), + .STAT_TX_PTP_FIFO_READ_ERROR (STAT_TX_PTP_FIFO_READ_ERROR_out), + .STAT_TX_PTP_FIFO_WRITE_ERROR (STAT_TX_PTP_FIFO_WRITE_ERROR_out), + .STAT_TX_TOTAL_BYTES (STAT_TX_TOTAL_BYTES_out), + .STAT_TX_TOTAL_GOOD_BYTES (STAT_TX_TOTAL_GOOD_BYTES_out), + .STAT_TX_TOTAL_GOOD_PACKETS (STAT_TX_TOTAL_GOOD_PACKETS_out), + .STAT_TX_TOTAL_PACKETS (STAT_TX_TOTAL_PACKETS_out), + .STAT_TX_UNICAST (STAT_TX_UNICAST_out), + .STAT_TX_USER_PAUSE (STAT_TX_USER_PAUSE_out), + .STAT_TX_VLAN (STAT_TX_VLAN_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_PTP_PCSLANE_OUT (TX_PTP_PCSLANE_OUT_out), + .TX_PTP_TSTAMP_OUT (TX_PTP_TSTAMP_OUT_out), + .TX_PTP_TSTAMP_TAG_OUT (TX_PTP_TSTAMP_TAG_OUT_out), + .TX_PTP_TSTAMP_VALID_OUT (TX_PTP_TSTAMP_VALID_OUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_ALT_DATA0 (TX_SERDES_ALT_DATA0_out), + .TX_SERDES_ALT_DATA1 (TX_SERDES_ALT_DATA1_out), + .TX_SERDES_ALT_DATA2 (TX_SERDES_ALT_DATA2_out), + .TX_SERDES_ALT_DATA3 (TX_SERDES_ALT_DATA3_out), + .TX_SERDES_DATA0 (TX_SERDES_DATA0_out), + .TX_SERDES_DATA1 (TX_SERDES_DATA1_out), + .TX_SERDES_DATA2 (TX_SERDES_DATA2_out), + .TX_SERDES_DATA3 (TX_SERDES_DATA3_out), + .TX_SERDES_DATA4 (TX_SERDES_DATA4_out), + .TX_SERDES_DATA5 (TX_SERDES_DATA5_out), + .TX_SERDES_DATA6 (TX_SERDES_DATA6_out), + .TX_SERDES_DATA7 (TX_SERDES_DATA7_out), + .TX_SERDES_DATA8 (TX_SERDES_DATA8_out), + .TX_SERDES_DATA9 (TX_SERDES_DATA9_out), + .TX_UNFOUT (TX_UNFOUT_out), + .CTL_CAUI4_MODE (CTL_CAUI4_MODE_in), + .CTL_RX_CHECK_ETYPE_GCP (CTL_RX_CHECK_ETYPE_GCP_in), + .CTL_RX_CHECK_ETYPE_GPP (CTL_RX_CHECK_ETYPE_GPP_in), + .CTL_RX_CHECK_ETYPE_PCP (CTL_RX_CHECK_ETYPE_PCP_in), + .CTL_RX_CHECK_ETYPE_PPP (CTL_RX_CHECK_ETYPE_PPP_in), + .CTL_RX_CHECK_MCAST_GCP (CTL_RX_CHECK_MCAST_GCP_in), + .CTL_RX_CHECK_MCAST_GPP (CTL_RX_CHECK_MCAST_GPP_in), + .CTL_RX_CHECK_MCAST_PCP (CTL_RX_CHECK_MCAST_PCP_in), + .CTL_RX_CHECK_MCAST_PPP (CTL_RX_CHECK_MCAST_PPP_in), + .CTL_RX_CHECK_OPCODE_GCP (CTL_RX_CHECK_OPCODE_GCP_in), + .CTL_RX_CHECK_OPCODE_GPP (CTL_RX_CHECK_OPCODE_GPP_in), + .CTL_RX_CHECK_OPCODE_PCP (CTL_RX_CHECK_OPCODE_PCP_in), + .CTL_RX_CHECK_OPCODE_PPP (CTL_RX_CHECK_OPCODE_PPP_in), + .CTL_RX_CHECK_SA_GCP (CTL_RX_CHECK_SA_GCP_in), + .CTL_RX_CHECK_SA_GPP (CTL_RX_CHECK_SA_GPP_in), + .CTL_RX_CHECK_SA_PCP (CTL_RX_CHECK_SA_PCP_in), + .CTL_RX_CHECK_SA_PPP (CTL_RX_CHECK_SA_PPP_in), + .CTL_RX_CHECK_UCAST_GCP (CTL_RX_CHECK_UCAST_GCP_in), + .CTL_RX_CHECK_UCAST_GPP (CTL_RX_CHECK_UCAST_GPP_in), + .CTL_RX_CHECK_UCAST_PCP (CTL_RX_CHECK_UCAST_PCP_in), + .CTL_RX_CHECK_UCAST_PPP (CTL_RX_CHECK_UCAST_PPP_in), + .CTL_RX_ENABLE (CTL_RX_ENABLE_in), + .CTL_RX_ENABLE_GCP (CTL_RX_ENABLE_GCP_in), + .CTL_RX_ENABLE_GPP (CTL_RX_ENABLE_GPP_in), + .CTL_RX_ENABLE_PCP (CTL_RX_ENABLE_PCP_in), + .CTL_RX_ENABLE_PPP (CTL_RX_ENABLE_PPP_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_PAUSE_ACK (CTL_RX_PAUSE_ACK_in), + .CTL_RX_PAUSE_ENABLE (CTL_RX_PAUSE_ENABLE_in), + .CTL_RX_SYSTEMTIMERIN (CTL_RX_SYSTEMTIMERIN_in), + .CTL_RX_TEST_PATTERN (CTL_RX_TEST_PATTERN_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in), + .CTL_TX_PAUSE_ENABLE (CTL_TX_PAUSE_ENABLE_in), + .CTL_TX_PAUSE_QUANTA0 (CTL_TX_PAUSE_QUANTA0_in), + .CTL_TX_PAUSE_QUANTA1 (CTL_TX_PAUSE_QUANTA1_in), + .CTL_TX_PAUSE_QUANTA2 (CTL_TX_PAUSE_QUANTA2_in), + .CTL_TX_PAUSE_QUANTA3 (CTL_TX_PAUSE_QUANTA3_in), + .CTL_TX_PAUSE_QUANTA4 (CTL_TX_PAUSE_QUANTA4_in), + .CTL_TX_PAUSE_QUANTA5 (CTL_TX_PAUSE_QUANTA5_in), + .CTL_TX_PAUSE_QUANTA6 (CTL_TX_PAUSE_QUANTA6_in), + .CTL_TX_PAUSE_QUANTA7 (CTL_TX_PAUSE_QUANTA7_in), + .CTL_TX_PAUSE_QUANTA8 (CTL_TX_PAUSE_QUANTA8_in), + .CTL_TX_PAUSE_REFRESH_TIMER0 (CTL_TX_PAUSE_REFRESH_TIMER0_in), + .CTL_TX_PAUSE_REFRESH_TIMER1 (CTL_TX_PAUSE_REFRESH_TIMER1_in), + .CTL_TX_PAUSE_REFRESH_TIMER2 (CTL_TX_PAUSE_REFRESH_TIMER2_in), + .CTL_TX_PAUSE_REFRESH_TIMER3 (CTL_TX_PAUSE_REFRESH_TIMER3_in), + .CTL_TX_PAUSE_REFRESH_TIMER4 (CTL_TX_PAUSE_REFRESH_TIMER4_in), + .CTL_TX_PAUSE_REFRESH_TIMER5 (CTL_TX_PAUSE_REFRESH_TIMER5_in), + .CTL_TX_PAUSE_REFRESH_TIMER6 (CTL_TX_PAUSE_REFRESH_TIMER6_in), + .CTL_TX_PAUSE_REFRESH_TIMER7 (CTL_TX_PAUSE_REFRESH_TIMER7_in), + .CTL_TX_PAUSE_REFRESH_TIMER8 (CTL_TX_PAUSE_REFRESH_TIMER8_in), + .CTL_TX_PAUSE_REQ (CTL_TX_PAUSE_REQ_in), + .CTL_TX_PTP_VLANE_ADJUST_MODE (CTL_TX_PTP_VLANE_ADJUST_MODE_in), + .CTL_TX_RESEND_PAUSE (CTL_TX_RESEND_PAUSE_in), + .CTL_TX_SEND_IDLE (CTL_TX_SEND_IDLE_in), + .CTL_TX_SEND_RFI (CTL_TX_SEND_RFI_in), + .CTL_TX_SYSTEMTIMERIN (CTL_TX_SYSTEMTIMERIN_in), + .CTL_TX_TEST_PATTERN (CTL_TX_TEST_PATTERN_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .RX_CLK (RX_CLK_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_ALT_DATA0 (RX_SERDES_ALT_DATA0_in), + .RX_SERDES_ALT_DATA1 (RX_SERDES_ALT_DATA1_in), + .RX_SERDES_ALT_DATA2 (RX_SERDES_ALT_DATA2_in), + .RX_SERDES_ALT_DATA3 (RX_SERDES_ALT_DATA3_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA0 (RX_SERDES_DATA0_in), + .RX_SERDES_DATA1 (RX_SERDES_DATA1_in), + .RX_SERDES_DATA2 (RX_SERDES_DATA2_in), + .RX_SERDES_DATA3 (RX_SERDES_DATA3_in), + .RX_SERDES_DATA4 (RX_SERDES_DATA4_in), + .RX_SERDES_DATA5 (RX_SERDES_DATA5_in), + .RX_SERDES_DATA6 (RX_SERDES_DATA6_in), + .RX_SERDES_DATA7 (RX_SERDES_DATA7_in), + .RX_SERDES_DATA8 (RX_SERDES_DATA8_in), + .RX_SERDES_DATA9 (RX_SERDES_DATA9_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_EN (SCAN_EN_in), + .SCAN_IN_CMAC (SCAN_IN_CMAC_in), + .SCAN_IN_DRPCTRL (SCAN_IN_DRPCTRL_in), + .TEST_MODE (TEST_MODE_in), + .TEST_RESET (TEST_RESET_in), + .TX_CLK (TX_CLK_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_PTP_1588OP_IN (TX_PTP_1588OP_IN_in), + .TX_PTP_CHKSUM_OFFSET_IN (TX_PTP_CHKSUM_OFFSET_IN_in), + .TX_PTP_RXTSTAMP_IN (TX_PTP_RXTSTAMP_IN_in), + .TX_PTP_TAG_FIELD_IN (TX_PTP_TAG_FIELD_IN_in), + .TX_PTP_TSTAMP_OFFSET_IN (TX_PTP_TSTAMP_OFFSET_IN_in), + .TX_PTP_UPD_CHKSUM_IN (TX_PTP_UPD_CHKSUM_IN_in), + .TX_RESET (TX_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); + end + endgenerate + + specify + (DRP_CLK => DRP_DO[0]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[10]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[11]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[12]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[13]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[14]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[15]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[1]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[2]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[3]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[4]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[5]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[6]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[7]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[8]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[9]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_RDY) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_ALIGNED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_ALIGNED_ERR) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_PREAMBLE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_SFD) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_0) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_1) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_10) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_11) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_12) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_13) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_14) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_15) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_16) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_17) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_18) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_19) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_2) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_4) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_5) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_6) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_7) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_8) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_9) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BROADCAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_0) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_1) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_10) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_11) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_12) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_13) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_14) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_15) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_16) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_17) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_18) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_19) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_2) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_4) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_5) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_6) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_7) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_8) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_9) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_GOT_SIGNAL_OS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_HI_BER) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_INRANGEERR) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_INTERNAL_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_JABBER) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7_VALID) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MISALIGNED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MULTICAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_OVERSIZE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1024_1518_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_128_255_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1519_1522_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1523_1548_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1549_2047_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_2048_4095_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_256_511_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_4096_8191_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_512_1023_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_64_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_65_127_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_8192_9215_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_BAD_FCS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_LARGE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RECEIVED_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_REMOTE_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STATUS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOOLONG) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_PACKETS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TRUNCATED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNICAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_USER_PAUSE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VLAN) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_BAD_FCS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_BROADCAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_FRAME_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_LOCAL_FAULT) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_MULTICAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1024_1518_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_128_255_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1519_1522_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1523_1548_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1549_2047_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_2048_4095_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_256_511_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_4096_8191_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_512_1023_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_64_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_65_127_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_8192_9215_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_LARGE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_SMALL) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[6]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[7]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[8]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PTP_FIFO_READ_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PTP_FIFO_WRITE_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[6]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[10]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[11]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[12]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[13]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[6]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[7]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[8]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[9]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_PACKETS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_PACKETS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_UNICAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_USER_PAUSE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_VLAN) = (100:100:100, 100:100:100); + (TX_CLK => TX_OVFOUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[64]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[65]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[66]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[67]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[68]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[69]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[70]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[71]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[72]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[73]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[74]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[75]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[76]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[77]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[78]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[79]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_VALID_OUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_RDYOUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_UNFOUT) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge DRP_CLK, 0:0:0, notifier); + $period (negedge RX_CLK, 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (negedge TX_CLK, 0:0:0, notifier); + $period (posedge DRP_CLK, 0:0:0, notifier); + $period (posedge RX_CLK, 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (posedge TX_CLK, 0:0:0, notifier); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (negedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, TX_CLK_delay); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (posedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, TX_CLK_delay); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, posedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_FORCE_RESYNC, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_FORCE_RESYNC_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge RX_CLK, negedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_TEST_PATTERN_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_FORCE_RESYNC, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_FORCE_RESYNC_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge RX_CLK, posedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_TEST_PATTERN_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_IDLE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_RFI_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_TEST_PATTERN_delay); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge TX_CLK, posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_IDLE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_RFI_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_TEST_PATTERN_delay); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN3_delay); + $width (negedge DRP_CLK, 0:0:0, 0, notifier); + $width (negedge RX_CLK, 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (negedge TX_CLK, 0:0:0, 0, notifier); + $width (posedge DRP_CLK, 0:0:0, 0, notifier); + $width (posedge RX_CLK, 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (posedge TX_CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/CMACE4.v b/verilog/src/unisims/CMACE4.v new file mode 100644 index 0000000..00a5643 --- /dev/null +++ b/verilog/src/unisims/CMACE4.v @@ -0,0 +1,10867 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 100G MAC Block +// /___/ /\ Filename : CMACE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module CMACE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE", + parameter CTL_RX_CHECK_ACK = "TRUE", + parameter CTL_RX_CHECK_PREAMBLE = "FALSE", + parameter CTL_RX_CHECK_SFD = "FALSE", + parameter CTL_RX_DELETE_FCS = "TRUE", + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808, + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808, + parameter CTL_RX_FORWARD_CONTROL = "FALSE", + parameter CTL_RX_IGNORE_FCS = "FALSE", + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580, + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40, + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001, + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF, + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF, + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000, + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000, + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001, + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001, + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000, + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000, + parameter CTL_RX_PROCESS_LFI = "FALSE", + parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046, + parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0, + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF, + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00, + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100, + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600, + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00, + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00, + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200, + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500, + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200, + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300, + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800, + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500, + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00, + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700, + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400, + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600, + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00, + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900, + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900, + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900, + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400, + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE", + parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE", + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001, + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001, + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808, + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808, + parameter CTL_TX_FCS_INS_ENABLE = "TRUE", + parameter CTL_TX_IGNORE_FCS = "FALSE", + parameter [3:0] CTL_TX_IPG_VALUE = 4'hC, + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001, + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001, + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE", + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1, + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000, + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000, + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF, + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00, + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100, + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600, + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00, + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00, + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200, + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500, + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200, + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300, + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800, + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500, + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00, + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700, + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400, + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600, + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00, + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900, + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900, + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900, + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter TEST_MODE_PIN_CHAR = "FALSE" +)( + output [15:0] DRP_DO, + output DRP_RDY, + output [329:0] RSFEC_BYPASS_RX_DOUT, + output RSFEC_BYPASS_RX_DOUT_CW_START, + output RSFEC_BYPASS_RX_DOUT_VALID, + output [329:0] RSFEC_BYPASS_TX_DOUT, + output RSFEC_BYPASS_TX_DOUT_CW_START, + output RSFEC_BYPASS_TX_DOUT_VALID, + output [127:0] RX_DATAOUT0, + output [127:0] RX_DATAOUT1, + output [127:0] RX_DATAOUT2, + output [127:0] RX_DATAOUT3, + output RX_ENAOUT0, + output RX_ENAOUT1, + output RX_ENAOUT2, + output RX_ENAOUT3, + output RX_EOPOUT0, + output RX_EOPOUT1, + output RX_EOPOUT2, + output RX_EOPOUT3, + output RX_ERROUT0, + output RX_ERROUT1, + output RX_ERROUT2, + output RX_ERROUT3, + output [6:0] RX_LANE_ALIGNER_FILL_0, + output [6:0] RX_LANE_ALIGNER_FILL_1, + output [6:0] RX_LANE_ALIGNER_FILL_10, + output [6:0] RX_LANE_ALIGNER_FILL_11, + output [6:0] RX_LANE_ALIGNER_FILL_12, + output [6:0] RX_LANE_ALIGNER_FILL_13, + output [6:0] RX_LANE_ALIGNER_FILL_14, + output [6:0] RX_LANE_ALIGNER_FILL_15, + output [6:0] RX_LANE_ALIGNER_FILL_16, + output [6:0] RX_LANE_ALIGNER_FILL_17, + output [6:0] RX_LANE_ALIGNER_FILL_18, + output [6:0] RX_LANE_ALIGNER_FILL_19, + output [6:0] RX_LANE_ALIGNER_FILL_2, + output [6:0] RX_LANE_ALIGNER_FILL_3, + output [6:0] RX_LANE_ALIGNER_FILL_4, + output [6:0] RX_LANE_ALIGNER_FILL_5, + output [6:0] RX_LANE_ALIGNER_FILL_6, + output [6:0] RX_LANE_ALIGNER_FILL_7, + output [6:0] RX_LANE_ALIGNER_FILL_8, + output [6:0] RX_LANE_ALIGNER_FILL_9, + output [3:0] RX_MTYOUT0, + output [3:0] RX_MTYOUT1, + output [3:0] RX_MTYOUT2, + output [3:0] RX_MTYOUT3, + output [7:0] RX_OTN_BIP8_0, + output [7:0] RX_OTN_BIP8_1, + output [7:0] RX_OTN_BIP8_2, + output [7:0] RX_OTN_BIP8_3, + output [7:0] RX_OTN_BIP8_4, + output [65:0] RX_OTN_DATA_0, + output [65:0] RX_OTN_DATA_1, + output [65:0] RX_OTN_DATA_2, + output [65:0] RX_OTN_DATA_3, + output [65:0] RX_OTN_DATA_4, + output RX_OTN_ENA, + output RX_OTN_LANE0, + output RX_OTN_VLMARKER, + output [55:0] RX_PREOUT, + output [4:0] RX_PTP_PCSLANE_OUT, + output [79:0] RX_PTP_TSTAMP_OUT, + output RX_SOPOUT0, + output RX_SOPOUT1, + output RX_SOPOUT2, + output RX_SOPOUT3, + output STAT_RX_ALIGNED, + output STAT_RX_ALIGNED_ERR, + output [2:0] STAT_RX_BAD_CODE, + output [2:0] STAT_RX_BAD_FCS, + output STAT_RX_BAD_PREAMBLE, + output STAT_RX_BAD_SFD, + output STAT_RX_BIP_ERR_0, + output STAT_RX_BIP_ERR_1, + output STAT_RX_BIP_ERR_10, + output STAT_RX_BIP_ERR_11, + output STAT_RX_BIP_ERR_12, + output STAT_RX_BIP_ERR_13, + output STAT_RX_BIP_ERR_14, + output STAT_RX_BIP_ERR_15, + output STAT_RX_BIP_ERR_16, + output STAT_RX_BIP_ERR_17, + output STAT_RX_BIP_ERR_18, + output STAT_RX_BIP_ERR_19, + output STAT_RX_BIP_ERR_2, + output STAT_RX_BIP_ERR_3, + output STAT_RX_BIP_ERR_4, + output STAT_RX_BIP_ERR_5, + output STAT_RX_BIP_ERR_6, + output STAT_RX_BIP_ERR_7, + output STAT_RX_BIP_ERR_8, + output STAT_RX_BIP_ERR_9, + output [19:0] STAT_RX_BLOCK_LOCK, + output STAT_RX_BROADCAST, + output [2:0] STAT_RX_FRAGMENT, + output [1:0] STAT_RX_FRAMING_ERR_0, + output [1:0] STAT_RX_FRAMING_ERR_1, + output [1:0] STAT_RX_FRAMING_ERR_10, + output [1:0] STAT_RX_FRAMING_ERR_11, + output [1:0] STAT_RX_FRAMING_ERR_12, + output [1:0] STAT_RX_FRAMING_ERR_13, + output [1:0] STAT_RX_FRAMING_ERR_14, + output [1:0] STAT_RX_FRAMING_ERR_15, + output [1:0] STAT_RX_FRAMING_ERR_16, + output [1:0] STAT_RX_FRAMING_ERR_17, + output [1:0] STAT_RX_FRAMING_ERR_18, + output [1:0] STAT_RX_FRAMING_ERR_19, + output [1:0] STAT_RX_FRAMING_ERR_2, + output [1:0] STAT_RX_FRAMING_ERR_3, + output [1:0] STAT_RX_FRAMING_ERR_4, + output [1:0] STAT_RX_FRAMING_ERR_5, + output [1:0] STAT_RX_FRAMING_ERR_6, + output [1:0] STAT_RX_FRAMING_ERR_7, + output [1:0] STAT_RX_FRAMING_ERR_8, + output [1:0] STAT_RX_FRAMING_ERR_9, + output STAT_RX_FRAMING_ERR_VALID_0, + output STAT_RX_FRAMING_ERR_VALID_1, + output STAT_RX_FRAMING_ERR_VALID_10, + output STAT_RX_FRAMING_ERR_VALID_11, + output STAT_RX_FRAMING_ERR_VALID_12, + output STAT_RX_FRAMING_ERR_VALID_13, + output STAT_RX_FRAMING_ERR_VALID_14, + output STAT_RX_FRAMING_ERR_VALID_15, + output STAT_RX_FRAMING_ERR_VALID_16, + output STAT_RX_FRAMING_ERR_VALID_17, + output STAT_RX_FRAMING_ERR_VALID_18, + output STAT_RX_FRAMING_ERR_VALID_19, + output STAT_RX_FRAMING_ERR_VALID_2, + output STAT_RX_FRAMING_ERR_VALID_3, + output STAT_RX_FRAMING_ERR_VALID_4, + output STAT_RX_FRAMING_ERR_VALID_5, + output STAT_RX_FRAMING_ERR_VALID_6, + output STAT_RX_FRAMING_ERR_VALID_7, + output STAT_RX_FRAMING_ERR_VALID_8, + output STAT_RX_FRAMING_ERR_VALID_9, + output STAT_RX_GOT_SIGNAL_OS, + output STAT_RX_HI_BER, + output STAT_RX_INRANGEERR, + output STAT_RX_INTERNAL_LOCAL_FAULT, + output STAT_RX_JABBER, + output [7:0] STAT_RX_LANE0_VLM_BIP7, + output STAT_RX_LANE0_VLM_BIP7_VALID, + output STAT_RX_LOCAL_FAULT, + output [19:0] STAT_RX_MF_ERR, + output [19:0] STAT_RX_MF_LEN_ERR, + output [19:0] STAT_RX_MF_REPEAT_ERR, + output STAT_RX_MISALIGNED, + output STAT_RX_MULTICAST, + output STAT_RX_OVERSIZE, + output STAT_RX_PACKET_1024_1518_BYTES, + output STAT_RX_PACKET_128_255_BYTES, + output STAT_RX_PACKET_1519_1522_BYTES, + output STAT_RX_PACKET_1523_1548_BYTES, + output STAT_RX_PACKET_1549_2047_BYTES, + output STAT_RX_PACKET_2048_4095_BYTES, + output STAT_RX_PACKET_256_511_BYTES, + output STAT_RX_PACKET_4096_8191_BYTES, + output STAT_RX_PACKET_512_1023_BYTES, + output STAT_RX_PACKET_64_BYTES, + output STAT_RX_PACKET_65_127_BYTES, + output STAT_RX_PACKET_8192_9215_BYTES, + output STAT_RX_PACKET_BAD_FCS, + output STAT_RX_PACKET_LARGE, + output [2:0] STAT_RX_PACKET_SMALL, + output STAT_RX_PAUSE, + output [15:0] STAT_RX_PAUSE_QUANTA0, + output [15:0] STAT_RX_PAUSE_QUANTA1, + output [15:0] STAT_RX_PAUSE_QUANTA2, + output [15:0] STAT_RX_PAUSE_QUANTA3, + output [15:0] STAT_RX_PAUSE_QUANTA4, + output [15:0] STAT_RX_PAUSE_QUANTA5, + output [15:0] STAT_RX_PAUSE_QUANTA6, + output [15:0] STAT_RX_PAUSE_QUANTA7, + output [15:0] STAT_RX_PAUSE_QUANTA8, + output [8:0] STAT_RX_PAUSE_REQ, + output [8:0] STAT_RX_PAUSE_VALID, + output STAT_RX_RECEIVED_LOCAL_FAULT, + output STAT_RX_REMOTE_FAULT, + output STAT_RX_RSFEC_AM_LOCK0, + output STAT_RX_RSFEC_AM_LOCK1, + output STAT_RX_RSFEC_AM_LOCK2, + output STAT_RX_RSFEC_AM_LOCK3, + output STAT_RX_RSFEC_CORRECTED_CW_INC, + output STAT_RX_RSFEC_CW_INC, + output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC, + output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC, + output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC, + output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC, + output STAT_RX_RSFEC_HI_SER, + output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS, + output [13:0] STAT_RX_RSFEC_LANE_FILL_0, + output [13:0] STAT_RX_RSFEC_LANE_FILL_1, + output [13:0] STAT_RX_RSFEC_LANE_FILL_2, + output [13:0] STAT_RX_RSFEC_LANE_FILL_3, + output [7:0] STAT_RX_RSFEC_LANE_MAPPING, + output [31:0] STAT_RX_RSFEC_RSVD, + output STAT_RX_RSFEC_UNCORRECTED_CW_INC, + output STAT_RX_STATUS, + output [2:0] STAT_RX_STOMPED_FCS, + output [19:0] STAT_RX_SYNCED, + output [19:0] STAT_RX_SYNCED_ERR, + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH, + output STAT_RX_TOOLONG, + output [6:0] STAT_RX_TOTAL_BYTES, + output [13:0] STAT_RX_TOTAL_GOOD_BYTES, + output STAT_RX_TOTAL_GOOD_PACKETS, + output [2:0] STAT_RX_TOTAL_PACKETS, + output STAT_RX_TRUNCATED, + output [2:0] STAT_RX_UNDERSIZE, + output STAT_RX_UNICAST, + output STAT_RX_USER_PAUSE, + output STAT_RX_VLAN, + output [19:0] STAT_RX_VL_DEMUXED, + output [4:0] STAT_RX_VL_NUMBER_0, + output [4:0] STAT_RX_VL_NUMBER_1, + output [4:0] STAT_RX_VL_NUMBER_10, + output [4:0] STAT_RX_VL_NUMBER_11, + output [4:0] STAT_RX_VL_NUMBER_12, + output [4:0] STAT_RX_VL_NUMBER_13, + output [4:0] STAT_RX_VL_NUMBER_14, + output [4:0] STAT_RX_VL_NUMBER_15, + output [4:0] STAT_RX_VL_NUMBER_16, + output [4:0] STAT_RX_VL_NUMBER_17, + output [4:0] STAT_RX_VL_NUMBER_18, + output [4:0] STAT_RX_VL_NUMBER_19, + output [4:0] STAT_RX_VL_NUMBER_2, + output [4:0] STAT_RX_VL_NUMBER_3, + output [4:0] STAT_RX_VL_NUMBER_4, + output [4:0] STAT_RX_VL_NUMBER_5, + output [4:0] STAT_RX_VL_NUMBER_6, + output [4:0] STAT_RX_VL_NUMBER_7, + output [4:0] STAT_RX_VL_NUMBER_8, + output [4:0] STAT_RX_VL_NUMBER_9, + output STAT_TX_BAD_FCS, + output STAT_TX_BROADCAST, + output STAT_TX_FRAME_ERROR, + output STAT_TX_LOCAL_FAULT, + output STAT_TX_MULTICAST, + output STAT_TX_PACKET_1024_1518_BYTES, + output STAT_TX_PACKET_128_255_BYTES, + output STAT_TX_PACKET_1519_1522_BYTES, + output STAT_TX_PACKET_1523_1548_BYTES, + output STAT_TX_PACKET_1549_2047_BYTES, + output STAT_TX_PACKET_2048_4095_BYTES, + output STAT_TX_PACKET_256_511_BYTES, + output STAT_TX_PACKET_4096_8191_BYTES, + output STAT_TX_PACKET_512_1023_BYTES, + output STAT_TX_PACKET_64_BYTES, + output STAT_TX_PACKET_65_127_BYTES, + output STAT_TX_PACKET_8192_9215_BYTES, + output STAT_TX_PACKET_LARGE, + output STAT_TX_PACKET_SMALL, + output STAT_TX_PAUSE, + output [8:0] STAT_TX_PAUSE_VALID, + output STAT_TX_PTP_FIFO_READ_ERROR, + output STAT_TX_PTP_FIFO_WRITE_ERROR, + output [5:0] STAT_TX_TOTAL_BYTES, + output [13:0] STAT_TX_TOTAL_GOOD_BYTES, + output STAT_TX_TOTAL_GOOD_PACKETS, + output STAT_TX_TOTAL_PACKETS, + output STAT_TX_UNICAST, + output STAT_TX_USER_PAUSE, + output STAT_TX_VLAN, + output TX_OVFOUT, + output [4:0] TX_PTP_PCSLANE_OUT, + output [79:0] TX_PTP_TSTAMP_OUT, + output [15:0] TX_PTP_TSTAMP_TAG_OUT, + output TX_PTP_TSTAMP_VALID_OUT, + output TX_RDYOUT, + output [15:0] TX_SERDES_ALT_DATA0, + output [15:0] TX_SERDES_ALT_DATA1, + output [15:0] TX_SERDES_ALT_DATA2, + output [15:0] TX_SERDES_ALT_DATA3, + output [63:0] TX_SERDES_DATA0, + output [63:0] TX_SERDES_DATA1, + output [63:0] TX_SERDES_DATA2, + output [63:0] TX_SERDES_DATA3, + output [31:0] TX_SERDES_DATA4, + output [31:0] TX_SERDES_DATA5, + output [31:0] TX_SERDES_DATA6, + output [31:0] TX_SERDES_DATA7, + output [31:0] TX_SERDES_DATA8, + output [31:0] TX_SERDES_DATA9, + output TX_UNFOUT, + + input CTL_CAUI4_MODE, + input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, + input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, + input CTL_RX_CHECK_ETYPE_GCP, + input CTL_RX_CHECK_ETYPE_GPP, + input CTL_RX_CHECK_ETYPE_PCP, + input CTL_RX_CHECK_ETYPE_PPP, + input CTL_RX_CHECK_MCAST_GCP, + input CTL_RX_CHECK_MCAST_GPP, + input CTL_RX_CHECK_MCAST_PCP, + input CTL_RX_CHECK_MCAST_PPP, + input CTL_RX_CHECK_OPCODE_GCP, + input CTL_RX_CHECK_OPCODE_GPP, + input CTL_RX_CHECK_OPCODE_PCP, + input CTL_RX_CHECK_OPCODE_PPP, + input CTL_RX_CHECK_SA_GCP, + input CTL_RX_CHECK_SA_GPP, + input CTL_RX_CHECK_SA_PCP, + input CTL_RX_CHECK_SA_PPP, + input CTL_RX_CHECK_UCAST_GCP, + input CTL_RX_CHECK_UCAST_GPP, + input CTL_RX_CHECK_UCAST_PCP, + input CTL_RX_CHECK_UCAST_PPP, + input CTL_RX_ENABLE, + input CTL_RX_ENABLE_GCP, + input CTL_RX_ENABLE_GPP, + input CTL_RX_ENABLE_PCP, + input CTL_RX_ENABLE_PPP, + input CTL_RX_FORCE_RESYNC, + input [8:0] CTL_RX_PAUSE_ACK, + input [8:0] CTL_RX_PAUSE_ENABLE, + input CTL_RX_RSFEC_ENABLE, + input CTL_RX_RSFEC_ENABLE_CORRECTION, + input CTL_RX_RSFEC_ENABLE_INDICATION, + input [79:0] CTL_RX_SYSTEMTIMERIN, + input CTL_RX_TEST_PATTERN, + input CTL_TX_ENABLE, + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE, + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, + input [8:0] CTL_TX_PAUSE_ENABLE, + input [15:0] CTL_TX_PAUSE_QUANTA0, + input [15:0] CTL_TX_PAUSE_QUANTA1, + input [15:0] CTL_TX_PAUSE_QUANTA2, + input [15:0] CTL_TX_PAUSE_QUANTA3, + input [15:0] CTL_TX_PAUSE_QUANTA4, + input [15:0] CTL_TX_PAUSE_QUANTA5, + input [15:0] CTL_TX_PAUSE_QUANTA6, + input [15:0] CTL_TX_PAUSE_QUANTA7, + input [15:0] CTL_TX_PAUSE_QUANTA8, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7, + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8, + input [8:0] CTL_TX_PAUSE_REQ, + input CTL_TX_PTP_VLANE_ADJUST_MODE, + input CTL_TX_RESEND_PAUSE, + input CTL_TX_RSFEC_ENABLE, + input CTL_TX_SEND_IDLE, + input CTL_TX_SEND_LFI, + input CTL_TX_SEND_RFI, + input [79:0] CTL_TX_SYSTEMTIMERIN, + input CTL_TX_TEST_PATTERN, + input [9:0] DRP_ADDR, + input DRP_CLK, + input [15:0] DRP_DI, + input DRP_EN, + input DRP_WE, + input [329:0] RSFEC_BYPASS_RX_DIN, + input RSFEC_BYPASS_RX_DIN_CW_START, + input [329:0] RSFEC_BYPASS_TX_DIN, + input RSFEC_BYPASS_TX_DIN_CW_START, + input RX_CLK, + input RX_RESET, + input [15:0] RX_SERDES_ALT_DATA0, + input [15:0] RX_SERDES_ALT_DATA1, + input [15:0] RX_SERDES_ALT_DATA2, + input [15:0] RX_SERDES_ALT_DATA3, + input [9:0] RX_SERDES_CLK, + input [63:0] RX_SERDES_DATA0, + input [63:0] RX_SERDES_DATA1, + input [63:0] RX_SERDES_DATA2, + input [63:0] RX_SERDES_DATA3, + input [31:0] RX_SERDES_DATA4, + input [31:0] RX_SERDES_DATA5, + input [31:0] RX_SERDES_DATA6, + input [31:0] RX_SERDES_DATA7, + input [31:0] RX_SERDES_DATA8, + input [31:0] RX_SERDES_DATA9, + input [9:0] RX_SERDES_RESET, + input TX_CLK, + input [127:0] TX_DATAIN0, + input [127:0] TX_DATAIN1, + input [127:0] TX_DATAIN2, + input [127:0] TX_DATAIN3, + input TX_ENAIN0, + input TX_ENAIN1, + input TX_ENAIN2, + input TX_ENAIN3, + input TX_EOPIN0, + input TX_EOPIN1, + input TX_EOPIN2, + input TX_EOPIN3, + input TX_ERRIN0, + input TX_ERRIN1, + input TX_ERRIN2, + input TX_ERRIN3, + input [3:0] TX_MTYIN0, + input [3:0] TX_MTYIN1, + input [3:0] TX_MTYIN2, + input [3:0] TX_MTYIN3, + input [55:0] TX_PREIN, + input [1:0] TX_PTP_1588OP_IN, + input [15:0] TX_PTP_CHKSUM_OFFSET_IN, + input [63:0] TX_PTP_RXTSTAMP_IN, + input [15:0] TX_PTP_TAG_FIELD_IN, + input [15:0] TX_PTP_TSTAMP_OFFSET_IN, + input TX_PTP_UPD_CHKSUM_IN, + input TX_RESET, + input TX_SOPIN0, + input TX_SOPIN1, + input TX_SOPIN2, + input TX_SOPIN3 +); + +// define constants + localparam MODULE_NAME = "CMACE4"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "CMACE4_dr.v" +`else + localparam [40:1] CTL_PTP_TRANSPCLK_MODE_REG = CTL_PTP_TRANSPCLK_MODE; + localparam [40:1] CTL_RX_CHECK_ACK_REG = CTL_RX_CHECK_ACK; + localparam [40:1] CTL_RX_CHECK_PREAMBLE_REG = CTL_RX_CHECK_PREAMBLE; + localparam [40:1] CTL_RX_CHECK_SFD_REG = CTL_RX_CHECK_SFD; + localparam [40:1] CTL_RX_DELETE_FCS_REG = CTL_RX_DELETE_FCS; + localparam [15:0] CTL_RX_ETYPE_GCP_REG = CTL_RX_ETYPE_GCP; + localparam [15:0] CTL_RX_ETYPE_GPP_REG = CTL_RX_ETYPE_GPP; + localparam [15:0] CTL_RX_ETYPE_PCP_REG = CTL_RX_ETYPE_PCP; + localparam [15:0] CTL_RX_ETYPE_PPP_REG = CTL_RX_ETYPE_PPP; + localparam [40:1] CTL_RX_FORWARD_CONTROL_REG = CTL_RX_FORWARD_CONTROL; + localparam [40:1] CTL_RX_IGNORE_FCS_REG = CTL_RX_IGNORE_FCS; + localparam [14:0] CTL_RX_MAX_PACKET_LEN_REG = CTL_RX_MAX_PACKET_LEN; + localparam [7:0] CTL_RX_MIN_PACKET_LEN_REG = CTL_RX_MIN_PACKET_LEN; + localparam [15:0] CTL_RX_OPCODE_GPP_REG = CTL_RX_OPCODE_GPP; + localparam [15:0] CTL_RX_OPCODE_MAX_GCP_REG = CTL_RX_OPCODE_MAX_GCP; + localparam [15:0] CTL_RX_OPCODE_MAX_PCP_REG = CTL_RX_OPCODE_MAX_PCP; + localparam [15:0] CTL_RX_OPCODE_MIN_GCP_REG = CTL_RX_OPCODE_MIN_GCP; + localparam [15:0] CTL_RX_OPCODE_MIN_PCP_REG = CTL_RX_OPCODE_MIN_PCP; + localparam [15:0] CTL_RX_OPCODE_PPP_REG = CTL_RX_OPCODE_PPP; + localparam [47:0] CTL_RX_PAUSE_DA_MCAST_REG = CTL_RX_PAUSE_DA_MCAST; + localparam [47:0] CTL_RX_PAUSE_DA_UCAST_REG = CTL_RX_PAUSE_DA_UCAST; + localparam [47:0] CTL_RX_PAUSE_SA_REG = CTL_RX_PAUSE_SA; + localparam [40:1] CTL_RX_PROCESS_LFI_REG = CTL_RX_PROCESS_LFI; + localparam [8:0] CTL_RX_RSFEC_AM_THRESHOLD_REG = CTL_RX_RSFEC_AM_THRESHOLD; + localparam [1:0] CTL_RX_RSFEC_FILL_ADJUST_REG = CTL_RX_RSFEC_FILL_ADJUST; + localparam [15:0] CTL_RX_VL_LENGTH_MINUS1_REG = CTL_RX_VL_LENGTH_MINUS1; + localparam [63:0] CTL_RX_VL_MARKER_ID0_REG = CTL_RX_VL_MARKER_ID0; + localparam [63:0] CTL_RX_VL_MARKER_ID1_REG = CTL_RX_VL_MARKER_ID1; + localparam [63:0] CTL_RX_VL_MARKER_ID10_REG = CTL_RX_VL_MARKER_ID10; + localparam [63:0] CTL_RX_VL_MARKER_ID11_REG = CTL_RX_VL_MARKER_ID11; + localparam [63:0] CTL_RX_VL_MARKER_ID12_REG = CTL_RX_VL_MARKER_ID12; + localparam [63:0] CTL_RX_VL_MARKER_ID13_REG = CTL_RX_VL_MARKER_ID13; + localparam [63:0] CTL_RX_VL_MARKER_ID14_REG = CTL_RX_VL_MARKER_ID14; + localparam [63:0] CTL_RX_VL_MARKER_ID15_REG = CTL_RX_VL_MARKER_ID15; + localparam [63:0] CTL_RX_VL_MARKER_ID16_REG = CTL_RX_VL_MARKER_ID16; + localparam [63:0] CTL_RX_VL_MARKER_ID17_REG = CTL_RX_VL_MARKER_ID17; + localparam [63:0] CTL_RX_VL_MARKER_ID18_REG = CTL_RX_VL_MARKER_ID18; + localparam [63:0] CTL_RX_VL_MARKER_ID19_REG = CTL_RX_VL_MARKER_ID19; + localparam [63:0] CTL_RX_VL_MARKER_ID2_REG = CTL_RX_VL_MARKER_ID2; + localparam [63:0] CTL_RX_VL_MARKER_ID3_REG = CTL_RX_VL_MARKER_ID3; + localparam [63:0] CTL_RX_VL_MARKER_ID4_REG = CTL_RX_VL_MARKER_ID4; + localparam [63:0] CTL_RX_VL_MARKER_ID5_REG = CTL_RX_VL_MARKER_ID5; + localparam [63:0] CTL_RX_VL_MARKER_ID6_REG = CTL_RX_VL_MARKER_ID6; + localparam [63:0] CTL_RX_VL_MARKER_ID7_REG = CTL_RX_VL_MARKER_ID7; + localparam [63:0] CTL_RX_VL_MARKER_ID8_REG = CTL_RX_VL_MARKER_ID8; + localparam [63:0] CTL_RX_VL_MARKER_ID9_REG = CTL_RX_VL_MARKER_ID9; + localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR; + localparam [40:1] CTL_TX_CUSTOM_PREAMBLE_ENABLE_REG = CTL_TX_CUSTOM_PREAMBLE_ENABLE; + localparam [47:0] CTL_TX_DA_GPP_REG = CTL_TX_DA_GPP; + localparam [47:0] CTL_TX_DA_PPP_REG = CTL_TX_DA_PPP; + localparam [15:0] CTL_TX_ETHERTYPE_GPP_REG = CTL_TX_ETHERTYPE_GPP; + localparam [15:0] CTL_TX_ETHERTYPE_PPP_REG = CTL_TX_ETHERTYPE_PPP; + localparam [40:1] CTL_TX_FCS_INS_ENABLE_REG = CTL_TX_FCS_INS_ENABLE; + localparam [40:1] CTL_TX_IGNORE_FCS_REG = CTL_TX_IGNORE_FCS; + localparam [3:0] CTL_TX_IPG_VALUE_REG = CTL_TX_IPG_VALUE; + localparam [15:0] CTL_TX_OPCODE_GPP_REG = CTL_TX_OPCODE_GPP; + localparam [15:0] CTL_TX_OPCODE_PPP_REG = CTL_TX_OPCODE_PPP; + localparam [40:1] CTL_TX_PTP_1STEP_ENABLE_REG = CTL_TX_PTP_1STEP_ENABLE; + localparam [10:0] CTL_TX_PTP_LATENCY_ADJUST_REG = CTL_TX_PTP_LATENCY_ADJUST; + localparam [47:0] CTL_TX_SA_GPP_REG = CTL_TX_SA_GPP; + localparam [47:0] CTL_TX_SA_PPP_REG = CTL_TX_SA_PPP; + localparam [15:0] CTL_TX_VL_LENGTH_MINUS1_REG = CTL_TX_VL_LENGTH_MINUS1; + localparam [63:0] CTL_TX_VL_MARKER_ID0_REG = CTL_TX_VL_MARKER_ID0; + localparam [63:0] CTL_TX_VL_MARKER_ID1_REG = CTL_TX_VL_MARKER_ID1; + localparam [63:0] CTL_TX_VL_MARKER_ID10_REG = CTL_TX_VL_MARKER_ID10; + localparam [63:0] CTL_TX_VL_MARKER_ID11_REG = CTL_TX_VL_MARKER_ID11; + localparam [63:0] CTL_TX_VL_MARKER_ID12_REG = CTL_TX_VL_MARKER_ID12; + localparam [63:0] CTL_TX_VL_MARKER_ID13_REG = CTL_TX_VL_MARKER_ID13; + localparam [63:0] CTL_TX_VL_MARKER_ID14_REG = CTL_TX_VL_MARKER_ID14; + localparam [63:0] CTL_TX_VL_MARKER_ID15_REG = CTL_TX_VL_MARKER_ID15; + localparam [63:0] CTL_TX_VL_MARKER_ID16_REG = CTL_TX_VL_MARKER_ID16; + localparam [63:0] CTL_TX_VL_MARKER_ID17_REG = CTL_TX_VL_MARKER_ID17; + localparam [63:0] CTL_TX_VL_MARKER_ID18_REG = CTL_TX_VL_MARKER_ID18; + localparam [63:0] CTL_TX_VL_MARKER_ID19_REG = CTL_TX_VL_MARKER_ID19; + localparam [63:0] CTL_TX_VL_MARKER_ID2_REG = CTL_TX_VL_MARKER_ID2; + localparam [63:0] CTL_TX_VL_MARKER_ID3_REG = CTL_TX_VL_MARKER_ID3; + localparam [63:0] CTL_TX_VL_MARKER_ID4_REG = CTL_TX_VL_MARKER_ID4; + localparam [63:0] CTL_TX_VL_MARKER_ID5_REG = CTL_TX_VL_MARKER_ID5; + localparam [63:0] CTL_TX_VL_MARKER_ID6_REG = CTL_TX_VL_MARKER_ID6; + localparam [63:0] CTL_TX_VL_MARKER_ID7_REG = CTL_TX_VL_MARKER_ID7; + localparam [63:0] CTL_TX_VL_MARKER_ID8_REG = CTL_TX_VL_MARKER_ID8; + localparam [63:0] CTL_TX_VL_MARKER_ID9_REG = CTL_TX_VL_MARKER_ID9; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR; +`endif + + localparam [40:1] CTL_CSSD_EN_REG = "FALSE"; + localparam [15:0] CTL_CSSD_MRKR_INIT_REG = 16'h0000; + localparam [11:0] CTL_CSSD_ROOT_CLK_DIS_REG = 12'h000; + localparam [3:0] CTL_CSSD_ROOT_CLK_SEL_REG = 4'h0; + localparam [40:1] CTL_CSSD_SNGL_CHAIN_MD_REG = "FALSE"; + localparam [15:0] CTL_CSSD_STOP_COUNT_0_REG = 16'h00FF; + localparam [15:0] CTL_CSSD_STOP_COUNT_1_REG = 16'h0000; + localparam [15:0] CTL_CSSD_STOP_COUNT_2_REG = 16'h0000; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CFG_RESET_CSSD_out; + wire CSSD_CLK_STOP_DONE_out; + wire DRP_RDY_out; + wire GRESTORE_CSSD_out; + wire GWE_CSSD_out; + wire RSFEC_BYPASS_RX_DOUT_CW_START_out; + wire RSFEC_BYPASS_RX_DOUT_VALID_out; + wire RSFEC_BYPASS_TX_DOUT_CW_START_out; + wire RSFEC_BYPASS_TX_DOUT_VALID_out; + wire RX_ENAOUT0_out; + wire RX_ENAOUT1_out; + wire RX_ENAOUT2_out; + wire RX_ENAOUT3_out; + wire RX_EOPOUT0_out; + wire RX_EOPOUT1_out; + wire RX_EOPOUT2_out; + wire RX_EOPOUT3_out; + wire RX_ERROUT0_out; + wire RX_ERROUT1_out; + wire RX_ERROUT2_out; + wire RX_ERROUT3_out; + wire RX_OTN_ENA_out; + wire RX_OTN_LANE0_out; + wire RX_OTN_VLMARKER_out; + wire RX_SOPOUT0_out; + wire RX_SOPOUT1_out; + wire RX_SOPOUT2_out; + wire RX_SOPOUT3_out; + wire STAT_RX_ALIGNED_ERR_out; + wire STAT_RX_ALIGNED_out; + wire STAT_RX_BAD_PREAMBLE_out; + wire STAT_RX_BAD_SFD_out; + wire STAT_RX_BIP_ERR_0_out; + wire STAT_RX_BIP_ERR_10_out; + wire STAT_RX_BIP_ERR_11_out; + wire STAT_RX_BIP_ERR_12_out; + wire STAT_RX_BIP_ERR_13_out; + wire STAT_RX_BIP_ERR_14_out; + wire STAT_RX_BIP_ERR_15_out; + wire STAT_RX_BIP_ERR_16_out; + wire STAT_RX_BIP_ERR_17_out; + wire STAT_RX_BIP_ERR_18_out; + wire STAT_RX_BIP_ERR_19_out; + wire STAT_RX_BIP_ERR_1_out; + wire STAT_RX_BIP_ERR_2_out; + wire STAT_RX_BIP_ERR_3_out; + wire STAT_RX_BIP_ERR_4_out; + wire STAT_RX_BIP_ERR_5_out; + wire STAT_RX_BIP_ERR_6_out; + wire STAT_RX_BIP_ERR_7_out; + wire STAT_RX_BIP_ERR_8_out; + wire STAT_RX_BIP_ERR_9_out; + wire STAT_RX_BROADCAST_out; + wire STAT_RX_FRAMING_ERR_VALID_0_out; + wire STAT_RX_FRAMING_ERR_VALID_10_out; + wire STAT_RX_FRAMING_ERR_VALID_11_out; + wire STAT_RX_FRAMING_ERR_VALID_12_out; + wire STAT_RX_FRAMING_ERR_VALID_13_out; + wire STAT_RX_FRAMING_ERR_VALID_14_out; + wire STAT_RX_FRAMING_ERR_VALID_15_out; + wire STAT_RX_FRAMING_ERR_VALID_16_out; + wire STAT_RX_FRAMING_ERR_VALID_17_out; + wire STAT_RX_FRAMING_ERR_VALID_18_out; + wire STAT_RX_FRAMING_ERR_VALID_19_out; + wire STAT_RX_FRAMING_ERR_VALID_1_out; + wire STAT_RX_FRAMING_ERR_VALID_2_out; + wire STAT_RX_FRAMING_ERR_VALID_3_out; + wire STAT_RX_FRAMING_ERR_VALID_4_out; + wire STAT_RX_FRAMING_ERR_VALID_5_out; + wire STAT_RX_FRAMING_ERR_VALID_6_out; + wire STAT_RX_FRAMING_ERR_VALID_7_out; + wire STAT_RX_FRAMING_ERR_VALID_8_out; + wire STAT_RX_FRAMING_ERR_VALID_9_out; + wire STAT_RX_GOT_SIGNAL_OS_out; + wire STAT_RX_HI_BER_out; + wire STAT_RX_INRANGEERR_out; + wire STAT_RX_INTERNAL_LOCAL_FAULT_out; + wire STAT_RX_JABBER_out; + wire STAT_RX_LANE0_VLM_BIP7_VALID_out; + wire STAT_RX_LOCAL_FAULT_out; + wire STAT_RX_MISALIGNED_out; + wire STAT_RX_MULTICAST_out; + wire STAT_RX_OVERSIZE_out; + wire STAT_RX_PACKET_1024_1518_BYTES_out; + wire STAT_RX_PACKET_128_255_BYTES_out; + wire STAT_RX_PACKET_1519_1522_BYTES_out; + wire STAT_RX_PACKET_1523_1548_BYTES_out; + wire STAT_RX_PACKET_1549_2047_BYTES_out; + wire STAT_RX_PACKET_2048_4095_BYTES_out; + wire STAT_RX_PACKET_256_511_BYTES_out; + wire STAT_RX_PACKET_4096_8191_BYTES_out; + wire STAT_RX_PACKET_512_1023_BYTES_out; + wire STAT_RX_PACKET_64_BYTES_out; + wire STAT_RX_PACKET_65_127_BYTES_out; + wire STAT_RX_PACKET_8192_9215_BYTES_out; + wire STAT_RX_PACKET_BAD_FCS_out; + wire STAT_RX_PACKET_LARGE_out; + wire STAT_RX_PAUSE_out; + wire STAT_RX_RECEIVED_LOCAL_FAULT_out; + wire STAT_RX_REMOTE_FAULT_out; + wire STAT_RX_RSFEC_AM_LOCK0_out; + wire STAT_RX_RSFEC_AM_LOCK1_out; + wire STAT_RX_RSFEC_AM_LOCK2_out; + wire STAT_RX_RSFEC_AM_LOCK3_out; + wire STAT_RX_RSFEC_CORRECTED_CW_INC_out; + wire STAT_RX_RSFEC_CW_INC_out; + wire STAT_RX_RSFEC_HI_SER_out; + wire STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS_out; + wire STAT_RX_RSFEC_UNCORRECTED_CW_INC_out; + wire STAT_RX_STATUS_out; + wire STAT_RX_TOOLONG_out; + wire STAT_RX_TOTAL_GOOD_PACKETS_out; + wire STAT_RX_TRUNCATED_out; + wire STAT_RX_UNICAST_out; + wire STAT_RX_USER_PAUSE_out; + wire STAT_RX_VLAN_out; + wire STAT_TX_BAD_FCS_out; + wire STAT_TX_BROADCAST_out; + wire STAT_TX_FRAME_ERROR_out; + wire STAT_TX_LOCAL_FAULT_out; + wire STAT_TX_MULTICAST_out; + wire STAT_TX_PACKET_1024_1518_BYTES_out; + wire STAT_TX_PACKET_128_255_BYTES_out; + wire STAT_TX_PACKET_1519_1522_BYTES_out; + wire STAT_TX_PACKET_1523_1548_BYTES_out; + wire STAT_TX_PACKET_1549_2047_BYTES_out; + wire STAT_TX_PACKET_2048_4095_BYTES_out; + wire STAT_TX_PACKET_256_511_BYTES_out; + wire STAT_TX_PACKET_4096_8191_BYTES_out; + wire STAT_TX_PACKET_512_1023_BYTES_out; + wire STAT_TX_PACKET_64_BYTES_out; + wire STAT_TX_PACKET_65_127_BYTES_out; + wire STAT_TX_PACKET_8192_9215_BYTES_out; + wire STAT_TX_PACKET_LARGE_out; + wire STAT_TX_PACKET_SMALL_out; + wire STAT_TX_PAUSE_out; + wire STAT_TX_PTP_FIFO_READ_ERROR_out; + wire STAT_TX_PTP_FIFO_WRITE_ERROR_out; + wire STAT_TX_TOTAL_GOOD_PACKETS_out; + wire STAT_TX_TOTAL_PACKETS_out; + wire STAT_TX_UNICAST_out; + wire STAT_TX_USER_PAUSE_out; + wire STAT_TX_VLAN_out; + wire TX_OVFOUT_out; + wire TX_PTP_TSTAMP_VALID_OUT_out; + wire TX_RDYOUT_out; + wire TX_UNFOUT_out; + wire [127:0] RX_DATAOUT0_out; + wire [127:0] RX_DATAOUT1_out; + wire [127:0] RX_DATAOUT2_out; + wire [127:0] RX_DATAOUT3_out; + wire [13:0] STAT_RX_RSFEC_LANE_FILL_0_out; + wire [13:0] STAT_RX_RSFEC_LANE_FILL_1_out; + wire [13:0] STAT_RX_RSFEC_LANE_FILL_2_out; + wire [13:0] STAT_RX_RSFEC_LANE_FILL_3_out; + wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_out; + wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_out; + wire [15:0] DRP_DO_out; + wire [15:0] STAT_RX_PAUSE_QUANTA0_out; + wire [15:0] STAT_RX_PAUSE_QUANTA1_out; + wire [15:0] STAT_RX_PAUSE_QUANTA2_out; + wire [15:0] STAT_RX_PAUSE_QUANTA3_out; + wire [15:0] STAT_RX_PAUSE_QUANTA4_out; + wire [15:0] STAT_RX_PAUSE_QUANTA5_out; + wire [15:0] STAT_RX_PAUSE_QUANTA6_out; + wire [15:0] STAT_RX_PAUSE_QUANTA7_out; + wire [15:0] STAT_RX_PAUSE_QUANTA8_out; + wire [15:0] TX_PTP_TSTAMP_TAG_OUT_out; + wire [15:0] TX_SERDES_ALT_DATA0_out; + wire [15:0] TX_SERDES_ALT_DATA1_out; + wire [15:0] TX_SERDES_ALT_DATA2_out; + wire [15:0] TX_SERDES_ALT_DATA3_out; + wire [19:0] STAT_RX_BLOCK_LOCK_out; + wire [19:0] STAT_RX_MF_ERR_out; + wire [19:0] STAT_RX_MF_LEN_ERR_out; + wire [19:0] STAT_RX_MF_REPEAT_ERR_out; + wire [19:0] STAT_RX_SYNCED_ERR_out; + wire [19:0] STAT_RX_SYNCED_out; + wire [19:0] STAT_RX_VL_DEMUXED_out; + wire [1:0] STAT_RX_FRAMING_ERR_0_out; + wire [1:0] STAT_RX_FRAMING_ERR_10_out; + wire [1:0] STAT_RX_FRAMING_ERR_11_out; + wire [1:0] STAT_RX_FRAMING_ERR_12_out; + wire [1:0] STAT_RX_FRAMING_ERR_13_out; + wire [1:0] STAT_RX_FRAMING_ERR_14_out; + wire [1:0] STAT_RX_FRAMING_ERR_15_out; + wire [1:0] STAT_RX_FRAMING_ERR_16_out; + wire [1:0] STAT_RX_FRAMING_ERR_17_out; + wire [1:0] STAT_RX_FRAMING_ERR_18_out; + wire [1:0] STAT_RX_FRAMING_ERR_19_out; + wire [1:0] STAT_RX_FRAMING_ERR_1_out; + wire [1:0] STAT_RX_FRAMING_ERR_2_out; + wire [1:0] STAT_RX_FRAMING_ERR_3_out; + wire [1:0] STAT_RX_FRAMING_ERR_4_out; + wire [1:0] STAT_RX_FRAMING_ERR_5_out; + wire [1:0] STAT_RX_FRAMING_ERR_6_out; + wire [1:0] STAT_RX_FRAMING_ERR_7_out; + wire [1:0] STAT_RX_FRAMING_ERR_8_out; + wire [1:0] STAT_RX_FRAMING_ERR_9_out; + wire [267:0] SCAN_OUT_out; + wire [2:0] STAT_RX_BAD_CODE_out; + wire [2:0] STAT_RX_BAD_FCS_out; + wire [2:0] STAT_RX_FRAGMENT_out; + wire [2:0] STAT_RX_PACKET_SMALL_out; + wire [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC_out; + wire [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC_out; + wire [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC_out; + wire [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC_out; + wire [2:0] STAT_RX_STOMPED_FCS_out; + wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_out; + wire [2:0] STAT_RX_TOTAL_PACKETS_out; + wire [2:0] STAT_RX_UNDERSIZE_out; + wire [31:0] STAT_RX_RSFEC_RSVD_out; + wire [31:0] TX_SERDES_DATA4_out; + wire [31:0] TX_SERDES_DATA5_out; + wire [31:0] TX_SERDES_DATA6_out; + wire [31:0] TX_SERDES_DATA7_out; + wire [31:0] TX_SERDES_DATA8_out; + wire [31:0] TX_SERDES_DATA9_out; + wire [329:0] RSFEC_BYPASS_RX_DOUT_out; + wire [329:0] RSFEC_BYPASS_TX_DOUT_out; + wire [3:0] RX_MTYOUT0_out; + wire [3:0] RX_MTYOUT1_out; + wire [3:0] RX_MTYOUT2_out; + wire [3:0] RX_MTYOUT3_out; + wire [4:0] RX_PTP_PCSLANE_OUT_out; + wire [4:0] STAT_RX_VL_NUMBER_0_out; + wire [4:0] STAT_RX_VL_NUMBER_10_out; + wire [4:0] STAT_RX_VL_NUMBER_11_out; + wire [4:0] STAT_RX_VL_NUMBER_12_out; + wire [4:0] STAT_RX_VL_NUMBER_13_out; + wire [4:0] STAT_RX_VL_NUMBER_14_out; + wire [4:0] STAT_RX_VL_NUMBER_15_out; + wire [4:0] STAT_RX_VL_NUMBER_16_out; + wire [4:0] STAT_RX_VL_NUMBER_17_out; + wire [4:0] STAT_RX_VL_NUMBER_18_out; + wire [4:0] STAT_RX_VL_NUMBER_19_out; + wire [4:0] STAT_RX_VL_NUMBER_1_out; + wire [4:0] STAT_RX_VL_NUMBER_2_out; + wire [4:0] STAT_RX_VL_NUMBER_3_out; + wire [4:0] STAT_RX_VL_NUMBER_4_out; + wire [4:0] STAT_RX_VL_NUMBER_5_out; + wire [4:0] STAT_RX_VL_NUMBER_6_out; + wire [4:0] STAT_RX_VL_NUMBER_7_out; + wire [4:0] STAT_RX_VL_NUMBER_8_out; + wire [4:0] STAT_RX_VL_NUMBER_9_out; + wire [4:0] TX_PTP_PCSLANE_OUT_out; + wire [55:0] RX_PREOUT_out; + wire [5:0] STAT_TX_TOTAL_BYTES_out; + wire [63:0] TX_SERDES_DATA0_out; + wire [63:0] TX_SERDES_DATA1_out; + wire [63:0] TX_SERDES_DATA2_out; + wire [63:0] TX_SERDES_DATA3_out; + wire [65:0] RX_OTN_DATA_0_out; + wire [65:0] RX_OTN_DATA_1_out; + wire [65:0] RX_OTN_DATA_2_out; + wire [65:0] RX_OTN_DATA_3_out; + wire [65:0] RX_OTN_DATA_4_out; + wire [6:0] RX_LANE_ALIGNER_FILL_0_out; + wire [6:0] RX_LANE_ALIGNER_FILL_10_out; + wire [6:0] RX_LANE_ALIGNER_FILL_11_out; + wire [6:0] RX_LANE_ALIGNER_FILL_12_out; + wire [6:0] RX_LANE_ALIGNER_FILL_13_out; + wire [6:0] RX_LANE_ALIGNER_FILL_14_out; + wire [6:0] RX_LANE_ALIGNER_FILL_15_out; + wire [6:0] RX_LANE_ALIGNER_FILL_16_out; + wire [6:0] RX_LANE_ALIGNER_FILL_17_out; + wire [6:0] RX_LANE_ALIGNER_FILL_18_out; + wire [6:0] RX_LANE_ALIGNER_FILL_19_out; + wire [6:0] RX_LANE_ALIGNER_FILL_1_out; + wire [6:0] RX_LANE_ALIGNER_FILL_2_out; + wire [6:0] RX_LANE_ALIGNER_FILL_3_out; + wire [6:0] RX_LANE_ALIGNER_FILL_4_out; + wire [6:0] RX_LANE_ALIGNER_FILL_5_out; + wire [6:0] RX_LANE_ALIGNER_FILL_6_out; + wire [6:0] RX_LANE_ALIGNER_FILL_7_out; + wire [6:0] RX_LANE_ALIGNER_FILL_8_out; + wire [6:0] RX_LANE_ALIGNER_FILL_9_out; + wire [6:0] STAT_RX_TOTAL_BYTES_out; + wire [79:0] RX_PTP_TSTAMP_OUT_out; + wire [79:0] TX_PTP_TSTAMP_OUT_out; + wire [7:0] RX_OTN_BIP8_0_out; + wire [7:0] RX_OTN_BIP8_1_out; + wire [7:0] RX_OTN_BIP8_2_out; + wire [7:0] RX_OTN_BIP8_3_out; + wire [7:0] RX_OTN_BIP8_4_out; + wire [7:0] STAT_RX_LANE0_VLM_BIP7_out; + wire [7:0] STAT_RX_RSFEC_LANE_MAPPING_out; + wire [8:0] STAT_RX_PAUSE_REQ_out; + wire [8:0] STAT_RX_PAUSE_VALID_out; + wire [8:0] STAT_TX_PAUSE_VALID_out; + + wire CSSD_CLK_STOP_EVENT_in; + wire CSSD_RESETN_in; + wire CTL_CAUI4_MODE_in; + wire CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_in; + wire CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_in; + wire CTL_RX_CHECK_ETYPE_GCP_in; + wire CTL_RX_CHECK_ETYPE_GPP_in; + wire CTL_RX_CHECK_ETYPE_PCP_in; + wire CTL_RX_CHECK_ETYPE_PPP_in; + wire CTL_RX_CHECK_MCAST_GCP_in; + wire CTL_RX_CHECK_MCAST_GPP_in; + wire CTL_RX_CHECK_MCAST_PCP_in; + wire CTL_RX_CHECK_MCAST_PPP_in; + wire CTL_RX_CHECK_OPCODE_GCP_in; + wire CTL_RX_CHECK_OPCODE_GPP_in; + wire CTL_RX_CHECK_OPCODE_PCP_in; + wire CTL_RX_CHECK_OPCODE_PPP_in; + wire CTL_RX_CHECK_SA_GCP_in; + wire CTL_RX_CHECK_SA_GPP_in; + wire CTL_RX_CHECK_SA_PCP_in; + wire CTL_RX_CHECK_SA_PPP_in; + wire CTL_RX_CHECK_UCAST_GCP_in; + wire CTL_RX_CHECK_UCAST_GPP_in; + wire CTL_RX_CHECK_UCAST_PCP_in; + wire CTL_RX_CHECK_UCAST_PPP_in; + wire CTL_RX_ENABLE_GCP_in; + wire CTL_RX_ENABLE_GPP_in; + wire CTL_RX_ENABLE_PCP_in; + wire CTL_RX_ENABLE_PPP_in; + wire CTL_RX_ENABLE_in; + wire CTL_RX_FORCE_RESYNC_in; + wire CTL_RX_RSFEC_ENABLE_CORRECTION_in; + wire CTL_RX_RSFEC_ENABLE_INDICATION_in; + wire CTL_RX_RSFEC_ENABLE_in; + wire CTL_RX_TEST_PATTERN_in; + wire CTL_TX_ENABLE_in; + wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in; + wire CTL_TX_PTP_VLANE_ADJUST_MODE_in; + wire CTL_TX_RESEND_PAUSE_in; + wire CTL_TX_RSFEC_ENABLE_in; + wire CTL_TX_SEND_IDLE_in; + wire CTL_TX_SEND_LFI_in; + wire CTL_TX_SEND_RFI_in; + wire CTL_TX_TEST_PATTERN_in; + wire DRP_CLK_in; + wire DRP_EN_in; + wire DRP_WE_in; + wire RSFEC_BYPASS_RX_DIN_CW_START_in; + wire RSFEC_BYPASS_TX_DIN_CW_START_in; + wire RX_CLK_in; + wire RX_RESET_in; + wire SCAN_CLK_in; + wire SCAN_EN_N_in; + wire TEST_MODE_N_in; + wire TEST_RESET_in; + wire TX_CLK_in; + wire TX_ENAIN0_in; + wire TX_ENAIN1_in; + wire TX_ENAIN2_in; + wire TX_ENAIN3_in; + wire TX_EOPIN0_in; + wire TX_EOPIN1_in; + wire TX_EOPIN2_in; + wire TX_EOPIN3_in; + wire TX_ERRIN0_in; + wire TX_ERRIN1_in; + wire TX_ERRIN2_in; + wire TX_ERRIN3_in; + wire TX_PTP_UPD_CHKSUM_IN_in; + wire TX_RESET_in; + wire TX_SOPIN0_in; + wire TX_SOPIN1_in; + wire TX_SOPIN2_in; + wire TX_SOPIN3_in; + wire [127:0] TX_DATAIN0_in; + wire [127:0] TX_DATAIN1_in; + wire [127:0] TX_DATAIN2_in; + wire [127:0] TX_DATAIN3_in; + wire [15:0] CTL_TX_PAUSE_QUANTA0_in; + wire [15:0] CTL_TX_PAUSE_QUANTA1_in; + wire [15:0] CTL_TX_PAUSE_QUANTA2_in; + wire [15:0] CTL_TX_PAUSE_QUANTA3_in; + wire [15:0] CTL_TX_PAUSE_QUANTA4_in; + wire [15:0] CTL_TX_PAUSE_QUANTA5_in; + wire [15:0] CTL_TX_PAUSE_QUANTA6_in; + wire [15:0] CTL_TX_PAUSE_QUANTA7_in; + wire [15:0] CTL_TX_PAUSE_QUANTA8_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_in; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_in; + wire [15:0] DRP_DI_in; + wire [15:0] RX_SERDES_ALT_DATA0_in; + wire [15:0] RX_SERDES_ALT_DATA1_in; + wire [15:0] RX_SERDES_ALT_DATA2_in; + wire [15:0] RX_SERDES_ALT_DATA3_in; + wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_in; + wire [15:0] TX_PTP_TAG_FIELD_IN_in; + wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_in; + wire [1:0] TX_PTP_1588OP_IN_in; + wire [267:0] SCAN_IN_in; + wire [31:0] RX_SERDES_DATA4_in; + wire [31:0] RX_SERDES_DATA5_in; + wire [31:0] RX_SERDES_DATA6_in; + wire [31:0] RX_SERDES_DATA7_in; + wire [31:0] RX_SERDES_DATA8_in; + wire [31:0] RX_SERDES_DATA9_in; + wire [329:0] RSFEC_BYPASS_RX_DIN_in; + wire [329:0] RSFEC_BYPASS_TX_DIN_in; + wire [3:0] TX_MTYIN0_in; + wire [3:0] TX_MTYIN1_in; + wire [3:0] TX_MTYIN2_in; + wire [3:0] TX_MTYIN3_in; + wire [55:0] TX_PREIN_in; + wire [63:0] RX_SERDES_DATA0_in; + wire [63:0] RX_SERDES_DATA1_in; + wire [63:0] RX_SERDES_DATA2_in; + wire [63:0] RX_SERDES_DATA3_in; + wire [63:0] TX_PTP_RXTSTAMP_IN_in; + wire [79:0] CTL_RX_SYSTEMTIMERIN_in; + wire [79:0] CTL_TX_SYSTEMTIMERIN_in; + wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in; + wire [8:0] CTL_RX_PAUSE_ACK_in; + wire [8:0] CTL_RX_PAUSE_ENABLE_in; + wire [8:0] CTL_TX_PAUSE_ENABLE_in; + wire [8:0] CTL_TX_PAUSE_REQ_in; + wire [9:0] DRP_ADDR_in; + wire [9:0] RX_SERDES_CLK_in; + wire [9:0] RX_SERDES_RESET_in; + +`ifdef XIL_TIMING + wire CTL_CAUI4_MODE_delay; + wire CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay; + wire CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_delay; + wire CTL_RX_CHECK_ETYPE_GCP_delay; + wire CTL_RX_CHECK_ETYPE_GPP_delay; + wire CTL_RX_CHECK_ETYPE_PCP_delay; + wire CTL_RX_CHECK_ETYPE_PPP_delay; + wire CTL_RX_CHECK_MCAST_GCP_delay; + wire CTL_RX_CHECK_MCAST_GPP_delay; + wire CTL_RX_CHECK_MCAST_PCP_delay; + wire CTL_RX_CHECK_MCAST_PPP_delay; + wire CTL_RX_CHECK_OPCODE_GCP_delay; + wire CTL_RX_CHECK_OPCODE_GPP_delay; + wire CTL_RX_CHECK_OPCODE_PCP_delay; + wire CTL_RX_CHECK_OPCODE_PPP_delay; + wire CTL_RX_CHECK_SA_GCP_delay; + wire CTL_RX_CHECK_SA_GPP_delay; + wire CTL_RX_CHECK_SA_PCP_delay; + wire CTL_RX_CHECK_SA_PPP_delay; + wire CTL_RX_CHECK_UCAST_GCP_delay; + wire CTL_RX_CHECK_UCAST_GPP_delay; + wire CTL_RX_CHECK_UCAST_PCP_delay; + wire CTL_RX_CHECK_UCAST_PPP_delay; + wire CTL_RX_ENABLE_GCP_delay; + wire CTL_RX_ENABLE_GPP_delay; + wire CTL_RX_ENABLE_PCP_delay; + wire CTL_RX_ENABLE_PPP_delay; + wire CTL_RX_ENABLE_delay; + wire CTL_RX_FORCE_RESYNC_delay; + wire CTL_RX_RSFEC_ENABLE_CORRECTION_delay; + wire CTL_RX_RSFEC_ENABLE_INDICATION_delay; + wire CTL_RX_RSFEC_ENABLE_delay; + wire CTL_RX_TEST_PATTERN_delay; + wire CTL_TX_ENABLE_delay; + wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay; + wire CTL_TX_PTP_VLANE_ADJUST_MODE_delay; + wire CTL_TX_RESEND_PAUSE_delay; + wire CTL_TX_RSFEC_ENABLE_delay; + wire CTL_TX_SEND_IDLE_delay; + wire CTL_TX_SEND_LFI_delay; + wire CTL_TX_SEND_RFI_delay; + wire CTL_TX_TEST_PATTERN_delay; + wire DRP_CLK_delay; + wire DRP_EN_delay; + wire DRP_WE_delay; + wire RSFEC_BYPASS_RX_DIN_CW_START_delay; + wire RSFEC_BYPASS_TX_DIN_CW_START_delay; + wire RX_CLK_delay; + wire RX_RESET_delay; + wire TX_CLK_delay; + wire TX_ENAIN0_delay; + wire TX_ENAIN1_delay; + wire TX_ENAIN2_delay; + wire TX_ENAIN3_delay; + wire TX_EOPIN0_delay; + wire TX_EOPIN1_delay; + wire TX_EOPIN2_delay; + wire TX_EOPIN3_delay; + wire TX_ERRIN0_delay; + wire TX_ERRIN1_delay; + wire TX_ERRIN2_delay; + wire TX_ERRIN3_delay; + wire TX_PTP_UPD_CHKSUM_IN_delay; + wire TX_RESET_delay; + wire TX_SOPIN0_delay; + wire TX_SOPIN1_delay; + wire TX_SOPIN2_delay; + wire TX_SOPIN3_delay; + wire [127:0] TX_DATAIN0_delay; + wire [127:0] TX_DATAIN1_delay; + wire [127:0] TX_DATAIN2_delay; + wire [127:0] TX_DATAIN3_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA0_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA1_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA2_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA3_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA4_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA5_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA6_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA7_delay; + wire [15:0] CTL_TX_PAUSE_QUANTA8_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_delay; + wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_delay; + wire [15:0] DRP_DI_delay; + wire [15:0] RX_SERDES_ALT_DATA0_delay; + wire [15:0] RX_SERDES_ALT_DATA1_delay; + wire [15:0] RX_SERDES_ALT_DATA2_delay; + wire [15:0] RX_SERDES_ALT_DATA3_delay; + wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_delay; + wire [15:0] TX_PTP_TAG_FIELD_IN_delay; + wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_delay; + wire [1:0] TX_PTP_1588OP_IN_delay; + wire [31:0] RX_SERDES_DATA4_delay; + wire [31:0] RX_SERDES_DATA5_delay; + wire [31:0] RX_SERDES_DATA6_delay; + wire [31:0] RX_SERDES_DATA7_delay; + wire [31:0] RX_SERDES_DATA8_delay; + wire [31:0] RX_SERDES_DATA9_delay; + wire [329:0] RSFEC_BYPASS_RX_DIN_delay; + wire [329:0] RSFEC_BYPASS_TX_DIN_delay; + wire [3:0] TX_MTYIN0_delay; + wire [3:0] TX_MTYIN1_delay; + wire [3:0] TX_MTYIN2_delay; + wire [3:0] TX_MTYIN3_delay; + wire [55:0] TX_PREIN_delay; + wire [63:0] RX_SERDES_DATA0_delay; + wire [63:0] RX_SERDES_DATA1_delay; + wire [63:0] RX_SERDES_DATA2_delay; + wire [63:0] RX_SERDES_DATA3_delay; + wire [63:0] TX_PTP_RXTSTAMP_IN_delay; + wire [79:0] CTL_RX_SYSTEMTIMERIN_delay; + wire [79:0] CTL_TX_SYSTEMTIMERIN_delay; + wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay; + wire [8:0] CTL_RX_PAUSE_ACK_delay; + wire [8:0] CTL_RX_PAUSE_ENABLE_delay; + wire [8:0] CTL_TX_PAUSE_ENABLE_delay; + wire [8:0] CTL_TX_PAUSE_REQ_delay; + wire [9:0] DRP_ADDR_delay; + wire [9:0] RX_SERDES_CLK_delay; + wire [9:0] RX_SERDES_RESET_delay; +`endif + + assign DRP_DO = DRP_DO_out; + assign DRP_RDY = DRP_RDY_out; + assign RSFEC_BYPASS_RX_DOUT = RSFEC_BYPASS_RX_DOUT_out; + assign RSFEC_BYPASS_RX_DOUT_CW_START = RSFEC_BYPASS_RX_DOUT_CW_START_out; + assign RSFEC_BYPASS_RX_DOUT_VALID = RSFEC_BYPASS_RX_DOUT_VALID_out; + assign RSFEC_BYPASS_TX_DOUT = RSFEC_BYPASS_TX_DOUT_out; + assign RSFEC_BYPASS_TX_DOUT_CW_START = RSFEC_BYPASS_TX_DOUT_CW_START_out; + assign RSFEC_BYPASS_TX_DOUT_VALID = RSFEC_BYPASS_TX_DOUT_VALID_out; + assign RX_DATAOUT0 = RX_DATAOUT0_out; + assign RX_DATAOUT1 = RX_DATAOUT1_out; + assign RX_DATAOUT2 = RX_DATAOUT2_out; + assign RX_DATAOUT3 = RX_DATAOUT3_out; + assign RX_ENAOUT0 = RX_ENAOUT0_out; + assign RX_ENAOUT1 = RX_ENAOUT1_out; + assign RX_ENAOUT2 = RX_ENAOUT2_out; + assign RX_ENAOUT3 = RX_ENAOUT3_out; + assign RX_EOPOUT0 = RX_EOPOUT0_out; + assign RX_EOPOUT1 = RX_EOPOUT1_out; + assign RX_EOPOUT2 = RX_EOPOUT2_out; + assign RX_EOPOUT3 = RX_EOPOUT3_out; + assign RX_ERROUT0 = RX_ERROUT0_out; + assign RX_ERROUT1 = RX_ERROUT1_out; + assign RX_ERROUT2 = RX_ERROUT2_out; + assign RX_ERROUT3 = RX_ERROUT3_out; + assign RX_LANE_ALIGNER_FILL_0 = RX_LANE_ALIGNER_FILL_0_out; + assign RX_LANE_ALIGNER_FILL_1 = RX_LANE_ALIGNER_FILL_1_out; + assign RX_LANE_ALIGNER_FILL_10 = RX_LANE_ALIGNER_FILL_10_out; + assign RX_LANE_ALIGNER_FILL_11 = RX_LANE_ALIGNER_FILL_11_out; + assign RX_LANE_ALIGNER_FILL_12 = RX_LANE_ALIGNER_FILL_12_out; + assign RX_LANE_ALIGNER_FILL_13 = RX_LANE_ALIGNER_FILL_13_out; + assign RX_LANE_ALIGNER_FILL_14 = RX_LANE_ALIGNER_FILL_14_out; + assign RX_LANE_ALIGNER_FILL_15 = RX_LANE_ALIGNER_FILL_15_out; + assign RX_LANE_ALIGNER_FILL_16 = RX_LANE_ALIGNER_FILL_16_out; + assign RX_LANE_ALIGNER_FILL_17 = RX_LANE_ALIGNER_FILL_17_out; + assign RX_LANE_ALIGNER_FILL_18 = RX_LANE_ALIGNER_FILL_18_out; + assign RX_LANE_ALIGNER_FILL_19 = RX_LANE_ALIGNER_FILL_19_out; + assign RX_LANE_ALIGNER_FILL_2 = RX_LANE_ALIGNER_FILL_2_out; + assign RX_LANE_ALIGNER_FILL_3 = RX_LANE_ALIGNER_FILL_3_out; + assign RX_LANE_ALIGNER_FILL_4 = RX_LANE_ALIGNER_FILL_4_out; + assign RX_LANE_ALIGNER_FILL_5 = RX_LANE_ALIGNER_FILL_5_out; + assign RX_LANE_ALIGNER_FILL_6 = RX_LANE_ALIGNER_FILL_6_out; + assign RX_LANE_ALIGNER_FILL_7 = RX_LANE_ALIGNER_FILL_7_out; + assign RX_LANE_ALIGNER_FILL_8 = RX_LANE_ALIGNER_FILL_8_out; + assign RX_LANE_ALIGNER_FILL_9 = RX_LANE_ALIGNER_FILL_9_out; + assign RX_MTYOUT0 = RX_MTYOUT0_out; + assign RX_MTYOUT1 = RX_MTYOUT1_out; + assign RX_MTYOUT2 = RX_MTYOUT2_out; + assign RX_MTYOUT3 = RX_MTYOUT3_out; + assign RX_OTN_BIP8_0 = RX_OTN_BIP8_0_out; + assign RX_OTN_BIP8_1 = RX_OTN_BIP8_1_out; + assign RX_OTN_BIP8_2 = RX_OTN_BIP8_2_out; + assign RX_OTN_BIP8_3 = RX_OTN_BIP8_3_out; + assign RX_OTN_BIP8_4 = RX_OTN_BIP8_4_out; + assign RX_OTN_DATA_0 = RX_OTN_DATA_0_out; + assign RX_OTN_DATA_1 = RX_OTN_DATA_1_out; + assign RX_OTN_DATA_2 = RX_OTN_DATA_2_out; + assign RX_OTN_DATA_3 = RX_OTN_DATA_3_out; + assign RX_OTN_DATA_4 = RX_OTN_DATA_4_out; + assign RX_OTN_ENA = RX_OTN_ENA_out; + assign RX_OTN_LANE0 = RX_OTN_LANE0_out; + assign RX_OTN_VLMARKER = RX_OTN_VLMARKER_out; + assign RX_PREOUT = RX_PREOUT_out; + assign RX_PTP_PCSLANE_OUT = RX_PTP_PCSLANE_OUT_out; + assign RX_PTP_TSTAMP_OUT = RX_PTP_TSTAMP_OUT_out; + assign RX_SOPOUT0 = RX_SOPOUT0_out; + assign RX_SOPOUT1 = RX_SOPOUT1_out; + assign RX_SOPOUT2 = RX_SOPOUT2_out; + assign RX_SOPOUT3 = RX_SOPOUT3_out; + assign STAT_RX_ALIGNED = STAT_RX_ALIGNED_out; + assign STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_out; + assign STAT_RX_BAD_CODE = STAT_RX_BAD_CODE_out; + assign STAT_RX_BAD_FCS = STAT_RX_BAD_FCS_out; + assign STAT_RX_BAD_PREAMBLE = STAT_RX_BAD_PREAMBLE_out; + assign STAT_RX_BAD_SFD = STAT_RX_BAD_SFD_out; + assign STAT_RX_BIP_ERR_0 = STAT_RX_BIP_ERR_0_out; + assign STAT_RX_BIP_ERR_1 = STAT_RX_BIP_ERR_1_out; + assign STAT_RX_BIP_ERR_10 = STAT_RX_BIP_ERR_10_out; + assign STAT_RX_BIP_ERR_11 = STAT_RX_BIP_ERR_11_out; + assign STAT_RX_BIP_ERR_12 = STAT_RX_BIP_ERR_12_out; + assign STAT_RX_BIP_ERR_13 = STAT_RX_BIP_ERR_13_out; + assign STAT_RX_BIP_ERR_14 = STAT_RX_BIP_ERR_14_out; + assign STAT_RX_BIP_ERR_15 = STAT_RX_BIP_ERR_15_out; + assign STAT_RX_BIP_ERR_16 = STAT_RX_BIP_ERR_16_out; + assign STAT_RX_BIP_ERR_17 = STAT_RX_BIP_ERR_17_out; + assign STAT_RX_BIP_ERR_18 = STAT_RX_BIP_ERR_18_out; + assign STAT_RX_BIP_ERR_19 = STAT_RX_BIP_ERR_19_out; + assign STAT_RX_BIP_ERR_2 = STAT_RX_BIP_ERR_2_out; + assign STAT_RX_BIP_ERR_3 = STAT_RX_BIP_ERR_3_out; + assign STAT_RX_BIP_ERR_4 = STAT_RX_BIP_ERR_4_out; + assign STAT_RX_BIP_ERR_5 = STAT_RX_BIP_ERR_5_out; + assign STAT_RX_BIP_ERR_6 = STAT_RX_BIP_ERR_6_out; + assign STAT_RX_BIP_ERR_7 = STAT_RX_BIP_ERR_7_out; + assign STAT_RX_BIP_ERR_8 = STAT_RX_BIP_ERR_8_out; + assign STAT_RX_BIP_ERR_9 = STAT_RX_BIP_ERR_9_out; + assign STAT_RX_BLOCK_LOCK = STAT_RX_BLOCK_LOCK_out; + assign STAT_RX_BROADCAST = STAT_RX_BROADCAST_out; + assign STAT_RX_FRAGMENT = STAT_RX_FRAGMENT_out; + assign STAT_RX_FRAMING_ERR_0 = STAT_RX_FRAMING_ERR_0_out; + assign STAT_RX_FRAMING_ERR_1 = STAT_RX_FRAMING_ERR_1_out; + assign STAT_RX_FRAMING_ERR_10 = STAT_RX_FRAMING_ERR_10_out; + assign STAT_RX_FRAMING_ERR_11 = STAT_RX_FRAMING_ERR_11_out; + assign STAT_RX_FRAMING_ERR_12 = STAT_RX_FRAMING_ERR_12_out; + assign STAT_RX_FRAMING_ERR_13 = STAT_RX_FRAMING_ERR_13_out; + assign STAT_RX_FRAMING_ERR_14 = STAT_RX_FRAMING_ERR_14_out; + assign STAT_RX_FRAMING_ERR_15 = STAT_RX_FRAMING_ERR_15_out; + assign STAT_RX_FRAMING_ERR_16 = STAT_RX_FRAMING_ERR_16_out; + assign STAT_RX_FRAMING_ERR_17 = STAT_RX_FRAMING_ERR_17_out; + assign STAT_RX_FRAMING_ERR_18 = STAT_RX_FRAMING_ERR_18_out; + assign STAT_RX_FRAMING_ERR_19 = STAT_RX_FRAMING_ERR_19_out; + assign STAT_RX_FRAMING_ERR_2 = STAT_RX_FRAMING_ERR_2_out; + assign STAT_RX_FRAMING_ERR_3 = STAT_RX_FRAMING_ERR_3_out; + assign STAT_RX_FRAMING_ERR_4 = STAT_RX_FRAMING_ERR_4_out; + assign STAT_RX_FRAMING_ERR_5 = STAT_RX_FRAMING_ERR_5_out; + assign STAT_RX_FRAMING_ERR_6 = STAT_RX_FRAMING_ERR_6_out; + assign STAT_RX_FRAMING_ERR_7 = STAT_RX_FRAMING_ERR_7_out; + assign STAT_RX_FRAMING_ERR_8 = STAT_RX_FRAMING_ERR_8_out; + assign STAT_RX_FRAMING_ERR_9 = STAT_RX_FRAMING_ERR_9_out; + assign STAT_RX_FRAMING_ERR_VALID_0 = STAT_RX_FRAMING_ERR_VALID_0_out; + assign STAT_RX_FRAMING_ERR_VALID_1 = STAT_RX_FRAMING_ERR_VALID_1_out; + assign STAT_RX_FRAMING_ERR_VALID_10 = STAT_RX_FRAMING_ERR_VALID_10_out; + assign STAT_RX_FRAMING_ERR_VALID_11 = STAT_RX_FRAMING_ERR_VALID_11_out; + assign STAT_RX_FRAMING_ERR_VALID_12 = STAT_RX_FRAMING_ERR_VALID_12_out; + assign STAT_RX_FRAMING_ERR_VALID_13 = STAT_RX_FRAMING_ERR_VALID_13_out; + assign STAT_RX_FRAMING_ERR_VALID_14 = STAT_RX_FRAMING_ERR_VALID_14_out; + assign STAT_RX_FRAMING_ERR_VALID_15 = STAT_RX_FRAMING_ERR_VALID_15_out; + assign STAT_RX_FRAMING_ERR_VALID_16 = STAT_RX_FRAMING_ERR_VALID_16_out; + assign STAT_RX_FRAMING_ERR_VALID_17 = STAT_RX_FRAMING_ERR_VALID_17_out; + assign STAT_RX_FRAMING_ERR_VALID_18 = STAT_RX_FRAMING_ERR_VALID_18_out; + assign STAT_RX_FRAMING_ERR_VALID_19 = STAT_RX_FRAMING_ERR_VALID_19_out; + assign STAT_RX_FRAMING_ERR_VALID_2 = STAT_RX_FRAMING_ERR_VALID_2_out; + assign STAT_RX_FRAMING_ERR_VALID_3 = STAT_RX_FRAMING_ERR_VALID_3_out; + assign STAT_RX_FRAMING_ERR_VALID_4 = STAT_RX_FRAMING_ERR_VALID_4_out; + assign STAT_RX_FRAMING_ERR_VALID_5 = STAT_RX_FRAMING_ERR_VALID_5_out; + assign STAT_RX_FRAMING_ERR_VALID_6 = STAT_RX_FRAMING_ERR_VALID_6_out; + assign STAT_RX_FRAMING_ERR_VALID_7 = STAT_RX_FRAMING_ERR_VALID_7_out; + assign STAT_RX_FRAMING_ERR_VALID_8 = STAT_RX_FRAMING_ERR_VALID_8_out; + assign STAT_RX_FRAMING_ERR_VALID_9 = STAT_RX_FRAMING_ERR_VALID_9_out; + assign STAT_RX_GOT_SIGNAL_OS = STAT_RX_GOT_SIGNAL_OS_out; + assign STAT_RX_HI_BER = STAT_RX_HI_BER_out; + assign STAT_RX_INRANGEERR = STAT_RX_INRANGEERR_out; + assign STAT_RX_INTERNAL_LOCAL_FAULT = STAT_RX_INTERNAL_LOCAL_FAULT_out; + assign STAT_RX_JABBER = STAT_RX_JABBER_out; + assign STAT_RX_LANE0_VLM_BIP7 = STAT_RX_LANE0_VLM_BIP7_out; + assign STAT_RX_LANE0_VLM_BIP7_VALID = STAT_RX_LANE0_VLM_BIP7_VALID_out; + assign STAT_RX_LOCAL_FAULT = STAT_RX_LOCAL_FAULT_out; + assign STAT_RX_MF_ERR = STAT_RX_MF_ERR_out; + assign STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_out; + assign STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_out; + assign STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_out; + assign STAT_RX_MULTICAST = STAT_RX_MULTICAST_out; + assign STAT_RX_OVERSIZE = STAT_RX_OVERSIZE_out; + assign STAT_RX_PACKET_1024_1518_BYTES = STAT_RX_PACKET_1024_1518_BYTES_out; + assign STAT_RX_PACKET_128_255_BYTES = STAT_RX_PACKET_128_255_BYTES_out; + assign STAT_RX_PACKET_1519_1522_BYTES = STAT_RX_PACKET_1519_1522_BYTES_out; + assign STAT_RX_PACKET_1523_1548_BYTES = STAT_RX_PACKET_1523_1548_BYTES_out; + assign STAT_RX_PACKET_1549_2047_BYTES = STAT_RX_PACKET_1549_2047_BYTES_out; + assign STAT_RX_PACKET_2048_4095_BYTES = STAT_RX_PACKET_2048_4095_BYTES_out; + assign STAT_RX_PACKET_256_511_BYTES = STAT_RX_PACKET_256_511_BYTES_out; + assign STAT_RX_PACKET_4096_8191_BYTES = STAT_RX_PACKET_4096_8191_BYTES_out; + assign STAT_RX_PACKET_512_1023_BYTES = STAT_RX_PACKET_512_1023_BYTES_out; + assign STAT_RX_PACKET_64_BYTES = STAT_RX_PACKET_64_BYTES_out; + assign STAT_RX_PACKET_65_127_BYTES = STAT_RX_PACKET_65_127_BYTES_out; + assign STAT_RX_PACKET_8192_9215_BYTES = STAT_RX_PACKET_8192_9215_BYTES_out; + assign STAT_RX_PACKET_BAD_FCS = STAT_RX_PACKET_BAD_FCS_out; + assign STAT_RX_PACKET_LARGE = STAT_RX_PACKET_LARGE_out; + assign STAT_RX_PACKET_SMALL = STAT_RX_PACKET_SMALL_out; + assign STAT_RX_PAUSE = STAT_RX_PAUSE_out; + assign STAT_RX_PAUSE_QUANTA0 = STAT_RX_PAUSE_QUANTA0_out; + assign STAT_RX_PAUSE_QUANTA1 = STAT_RX_PAUSE_QUANTA1_out; + assign STAT_RX_PAUSE_QUANTA2 = STAT_RX_PAUSE_QUANTA2_out; + assign STAT_RX_PAUSE_QUANTA3 = STAT_RX_PAUSE_QUANTA3_out; + assign STAT_RX_PAUSE_QUANTA4 = STAT_RX_PAUSE_QUANTA4_out; + assign STAT_RX_PAUSE_QUANTA5 = STAT_RX_PAUSE_QUANTA5_out; + assign STAT_RX_PAUSE_QUANTA6 = STAT_RX_PAUSE_QUANTA6_out; + assign STAT_RX_PAUSE_QUANTA7 = STAT_RX_PAUSE_QUANTA7_out; + assign STAT_RX_PAUSE_QUANTA8 = STAT_RX_PAUSE_QUANTA8_out; + assign STAT_RX_PAUSE_REQ = STAT_RX_PAUSE_REQ_out; + assign STAT_RX_PAUSE_VALID = STAT_RX_PAUSE_VALID_out; + assign STAT_RX_RECEIVED_LOCAL_FAULT = STAT_RX_RECEIVED_LOCAL_FAULT_out; + assign STAT_RX_REMOTE_FAULT = STAT_RX_REMOTE_FAULT_out; + assign STAT_RX_RSFEC_AM_LOCK0 = STAT_RX_RSFEC_AM_LOCK0_out; + assign STAT_RX_RSFEC_AM_LOCK1 = STAT_RX_RSFEC_AM_LOCK1_out; + assign STAT_RX_RSFEC_AM_LOCK2 = STAT_RX_RSFEC_AM_LOCK2_out; + assign STAT_RX_RSFEC_AM_LOCK3 = STAT_RX_RSFEC_AM_LOCK3_out; + assign STAT_RX_RSFEC_CORRECTED_CW_INC = STAT_RX_RSFEC_CORRECTED_CW_INC_out; + assign STAT_RX_RSFEC_CW_INC = STAT_RX_RSFEC_CW_INC_out; + assign STAT_RX_RSFEC_ERR_COUNT0_INC = STAT_RX_RSFEC_ERR_COUNT0_INC_out; + assign STAT_RX_RSFEC_ERR_COUNT1_INC = STAT_RX_RSFEC_ERR_COUNT1_INC_out; + assign STAT_RX_RSFEC_ERR_COUNT2_INC = STAT_RX_RSFEC_ERR_COUNT2_INC_out; + assign STAT_RX_RSFEC_ERR_COUNT3_INC = STAT_RX_RSFEC_ERR_COUNT3_INC_out; + assign STAT_RX_RSFEC_HI_SER = STAT_RX_RSFEC_HI_SER_out; + assign STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS = STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS_out; + assign STAT_RX_RSFEC_LANE_FILL_0 = STAT_RX_RSFEC_LANE_FILL_0_out; + assign STAT_RX_RSFEC_LANE_FILL_1 = STAT_RX_RSFEC_LANE_FILL_1_out; + assign STAT_RX_RSFEC_LANE_FILL_2 = STAT_RX_RSFEC_LANE_FILL_2_out; + assign STAT_RX_RSFEC_LANE_FILL_3 = STAT_RX_RSFEC_LANE_FILL_3_out; + assign STAT_RX_RSFEC_LANE_MAPPING = STAT_RX_RSFEC_LANE_MAPPING_out; + assign STAT_RX_RSFEC_RSVD = STAT_RX_RSFEC_RSVD_out; + assign STAT_RX_RSFEC_UNCORRECTED_CW_INC = STAT_RX_RSFEC_UNCORRECTED_CW_INC_out; + assign STAT_RX_STATUS = STAT_RX_STATUS_out; + assign STAT_RX_STOMPED_FCS = STAT_RX_STOMPED_FCS_out; + assign STAT_RX_SYNCED = STAT_RX_SYNCED_out; + assign STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_out; + assign STAT_RX_TEST_PATTERN_MISMATCH = STAT_RX_TEST_PATTERN_MISMATCH_out; + assign STAT_RX_TOOLONG = STAT_RX_TOOLONG_out; + assign STAT_RX_TOTAL_BYTES = STAT_RX_TOTAL_BYTES_out; + assign STAT_RX_TOTAL_GOOD_BYTES = STAT_RX_TOTAL_GOOD_BYTES_out; + assign STAT_RX_TOTAL_GOOD_PACKETS = STAT_RX_TOTAL_GOOD_PACKETS_out; + assign STAT_RX_TOTAL_PACKETS = STAT_RX_TOTAL_PACKETS_out; + assign STAT_RX_TRUNCATED = STAT_RX_TRUNCATED_out; + assign STAT_RX_UNDERSIZE = STAT_RX_UNDERSIZE_out; + assign STAT_RX_UNICAST = STAT_RX_UNICAST_out; + assign STAT_RX_USER_PAUSE = STAT_RX_USER_PAUSE_out; + assign STAT_RX_VLAN = STAT_RX_VLAN_out; + assign STAT_RX_VL_DEMUXED = STAT_RX_VL_DEMUXED_out; + assign STAT_RX_VL_NUMBER_0 = STAT_RX_VL_NUMBER_0_out; + assign STAT_RX_VL_NUMBER_1 = STAT_RX_VL_NUMBER_1_out; + assign STAT_RX_VL_NUMBER_10 = STAT_RX_VL_NUMBER_10_out; + assign STAT_RX_VL_NUMBER_11 = STAT_RX_VL_NUMBER_11_out; + assign STAT_RX_VL_NUMBER_12 = STAT_RX_VL_NUMBER_12_out; + assign STAT_RX_VL_NUMBER_13 = STAT_RX_VL_NUMBER_13_out; + assign STAT_RX_VL_NUMBER_14 = STAT_RX_VL_NUMBER_14_out; + assign STAT_RX_VL_NUMBER_15 = STAT_RX_VL_NUMBER_15_out; + assign STAT_RX_VL_NUMBER_16 = STAT_RX_VL_NUMBER_16_out; + assign STAT_RX_VL_NUMBER_17 = STAT_RX_VL_NUMBER_17_out; + assign STAT_RX_VL_NUMBER_18 = STAT_RX_VL_NUMBER_18_out; + assign STAT_RX_VL_NUMBER_19 = STAT_RX_VL_NUMBER_19_out; + assign STAT_RX_VL_NUMBER_2 = STAT_RX_VL_NUMBER_2_out; + assign STAT_RX_VL_NUMBER_3 = STAT_RX_VL_NUMBER_3_out; + assign STAT_RX_VL_NUMBER_4 = STAT_RX_VL_NUMBER_4_out; + assign STAT_RX_VL_NUMBER_5 = STAT_RX_VL_NUMBER_5_out; + assign STAT_RX_VL_NUMBER_6 = STAT_RX_VL_NUMBER_6_out; + assign STAT_RX_VL_NUMBER_7 = STAT_RX_VL_NUMBER_7_out; + assign STAT_RX_VL_NUMBER_8 = STAT_RX_VL_NUMBER_8_out; + assign STAT_RX_VL_NUMBER_9 = STAT_RX_VL_NUMBER_9_out; + assign STAT_TX_BAD_FCS = STAT_TX_BAD_FCS_out; + assign STAT_TX_BROADCAST = STAT_TX_BROADCAST_out; + assign STAT_TX_FRAME_ERROR = STAT_TX_FRAME_ERROR_out; + assign STAT_TX_LOCAL_FAULT = STAT_TX_LOCAL_FAULT_out; + assign STAT_TX_MULTICAST = STAT_TX_MULTICAST_out; + assign STAT_TX_PACKET_1024_1518_BYTES = STAT_TX_PACKET_1024_1518_BYTES_out; + assign STAT_TX_PACKET_128_255_BYTES = STAT_TX_PACKET_128_255_BYTES_out; + assign STAT_TX_PACKET_1519_1522_BYTES = STAT_TX_PACKET_1519_1522_BYTES_out; + assign STAT_TX_PACKET_1523_1548_BYTES = STAT_TX_PACKET_1523_1548_BYTES_out; + assign STAT_TX_PACKET_1549_2047_BYTES = STAT_TX_PACKET_1549_2047_BYTES_out; + assign STAT_TX_PACKET_2048_4095_BYTES = STAT_TX_PACKET_2048_4095_BYTES_out; + assign STAT_TX_PACKET_256_511_BYTES = STAT_TX_PACKET_256_511_BYTES_out; + assign STAT_TX_PACKET_4096_8191_BYTES = STAT_TX_PACKET_4096_8191_BYTES_out; + assign STAT_TX_PACKET_512_1023_BYTES = STAT_TX_PACKET_512_1023_BYTES_out; + assign STAT_TX_PACKET_64_BYTES = STAT_TX_PACKET_64_BYTES_out; + assign STAT_TX_PACKET_65_127_BYTES = STAT_TX_PACKET_65_127_BYTES_out; + assign STAT_TX_PACKET_8192_9215_BYTES = STAT_TX_PACKET_8192_9215_BYTES_out; + assign STAT_TX_PACKET_LARGE = STAT_TX_PACKET_LARGE_out; + assign STAT_TX_PACKET_SMALL = STAT_TX_PACKET_SMALL_out; + assign STAT_TX_PAUSE = STAT_TX_PAUSE_out; + assign STAT_TX_PAUSE_VALID = STAT_TX_PAUSE_VALID_out; + assign STAT_TX_PTP_FIFO_READ_ERROR = STAT_TX_PTP_FIFO_READ_ERROR_out; + assign STAT_TX_PTP_FIFO_WRITE_ERROR = STAT_TX_PTP_FIFO_WRITE_ERROR_out; + assign STAT_TX_TOTAL_BYTES = STAT_TX_TOTAL_BYTES_out; + assign STAT_TX_TOTAL_GOOD_BYTES = STAT_TX_TOTAL_GOOD_BYTES_out; + assign STAT_TX_TOTAL_GOOD_PACKETS = STAT_TX_TOTAL_GOOD_PACKETS_out; + assign STAT_TX_TOTAL_PACKETS = STAT_TX_TOTAL_PACKETS_out; + assign STAT_TX_UNICAST = STAT_TX_UNICAST_out; + assign STAT_TX_USER_PAUSE = STAT_TX_USER_PAUSE_out; + assign STAT_TX_VLAN = STAT_TX_VLAN_out; + assign TX_OVFOUT = TX_OVFOUT_out; + assign TX_PTP_PCSLANE_OUT = TX_PTP_PCSLANE_OUT_out; + assign TX_PTP_TSTAMP_OUT = TX_PTP_TSTAMP_OUT_out; + assign TX_PTP_TSTAMP_TAG_OUT = TX_PTP_TSTAMP_TAG_OUT_out; + assign TX_PTP_TSTAMP_VALID_OUT = TX_PTP_TSTAMP_VALID_OUT_out; + assign TX_RDYOUT = TX_RDYOUT_out; + assign TX_SERDES_ALT_DATA0 = TX_SERDES_ALT_DATA0_out; + assign TX_SERDES_ALT_DATA1 = TX_SERDES_ALT_DATA1_out; + assign TX_SERDES_ALT_DATA2 = TX_SERDES_ALT_DATA2_out; + assign TX_SERDES_ALT_DATA3 = TX_SERDES_ALT_DATA3_out; + assign TX_SERDES_DATA0 = TX_SERDES_DATA0_out; + assign TX_SERDES_DATA1 = TX_SERDES_DATA1_out; + assign TX_SERDES_DATA2 = TX_SERDES_DATA2_out; + assign TX_SERDES_DATA3 = TX_SERDES_DATA3_out; + assign TX_SERDES_DATA4 = TX_SERDES_DATA4_out; + assign TX_SERDES_DATA5 = TX_SERDES_DATA5_out; + assign TX_SERDES_DATA6 = TX_SERDES_DATA6_out; + assign TX_SERDES_DATA7 = TX_SERDES_DATA7_out; + assign TX_SERDES_DATA8 = TX_SERDES_DATA8_out; + assign TX_SERDES_DATA9 = TX_SERDES_DATA9_out; + assign TX_UNFOUT = TX_UNFOUT_out; + +`ifdef XIL_TIMING + assign CTL_CAUI4_MODE_in = CTL_CAUI4_MODE_delay; + assign CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_in = CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay; + assign CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_in = CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_delay; + assign CTL_RX_CHECK_ETYPE_GCP_in = CTL_RX_CHECK_ETYPE_GCP_delay; + assign CTL_RX_CHECK_ETYPE_GPP_in = CTL_RX_CHECK_ETYPE_GPP_delay; + assign CTL_RX_CHECK_ETYPE_PCP_in = CTL_RX_CHECK_ETYPE_PCP_delay; + assign CTL_RX_CHECK_ETYPE_PPP_in = CTL_RX_CHECK_ETYPE_PPP_delay; + assign CTL_RX_CHECK_MCAST_GCP_in = CTL_RX_CHECK_MCAST_GCP_delay; + assign CTL_RX_CHECK_MCAST_GPP_in = CTL_RX_CHECK_MCAST_GPP_delay; + assign CTL_RX_CHECK_MCAST_PCP_in = CTL_RX_CHECK_MCAST_PCP_delay; + assign CTL_RX_CHECK_MCAST_PPP_in = CTL_RX_CHECK_MCAST_PPP_delay; + assign CTL_RX_CHECK_OPCODE_GCP_in = CTL_RX_CHECK_OPCODE_GCP_delay; + assign CTL_RX_CHECK_OPCODE_GPP_in = CTL_RX_CHECK_OPCODE_GPP_delay; + assign CTL_RX_CHECK_OPCODE_PCP_in = CTL_RX_CHECK_OPCODE_PCP_delay; + assign CTL_RX_CHECK_OPCODE_PPP_in = CTL_RX_CHECK_OPCODE_PPP_delay; + assign CTL_RX_CHECK_SA_GCP_in = CTL_RX_CHECK_SA_GCP_delay; + assign CTL_RX_CHECK_SA_GPP_in = CTL_RX_CHECK_SA_GPP_delay; + assign CTL_RX_CHECK_SA_PCP_in = CTL_RX_CHECK_SA_PCP_delay; + assign CTL_RX_CHECK_SA_PPP_in = CTL_RX_CHECK_SA_PPP_delay; + assign CTL_RX_CHECK_UCAST_GCP_in = CTL_RX_CHECK_UCAST_GCP_delay; + assign CTL_RX_CHECK_UCAST_GPP_in = CTL_RX_CHECK_UCAST_GPP_delay; + assign CTL_RX_CHECK_UCAST_PCP_in = CTL_RX_CHECK_UCAST_PCP_delay; + assign CTL_RX_CHECK_UCAST_PPP_in = CTL_RX_CHECK_UCAST_PPP_delay; + assign CTL_RX_ENABLE_GCP_in = CTL_RX_ENABLE_GCP_delay; + assign CTL_RX_ENABLE_GPP_in = CTL_RX_ENABLE_GPP_delay; + assign CTL_RX_ENABLE_PCP_in = CTL_RX_ENABLE_PCP_delay; + assign CTL_RX_ENABLE_PPP_in = CTL_RX_ENABLE_PPP_delay; + assign CTL_RX_ENABLE_in = CTL_RX_ENABLE_delay; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay; + assign CTL_RX_PAUSE_ACK_in = CTL_RX_PAUSE_ACK_delay; + assign CTL_RX_PAUSE_ENABLE_in = CTL_RX_PAUSE_ENABLE_delay; + assign CTL_RX_RSFEC_ENABLE_CORRECTION_in = CTL_RX_RSFEC_ENABLE_CORRECTION_delay; + assign CTL_RX_RSFEC_ENABLE_INDICATION_in = CTL_RX_RSFEC_ENABLE_INDICATION_delay; + assign CTL_RX_RSFEC_ENABLE_in = CTL_RX_RSFEC_ENABLE_delay; + assign CTL_RX_SYSTEMTIMERIN_in = CTL_RX_SYSTEMTIMERIN_delay; + assign CTL_RX_TEST_PATTERN_in = CTL_RX_TEST_PATTERN_delay; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay; + assign CTL_TX_PAUSE_ENABLE_in = CTL_TX_PAUSE_ENABLE_delay; + assign CTL_TX_PAUSE_QUANTA0_in = CTL_TX_PAUSE_QUANTA0_delay; + assign CTL_TX_PAUSE_QUANTA1_in = CTL_TX_PAUSE_QUANTA1_delay; + assign CTL_TX_PAUSE_QUANTA2_in = CTL_TX_PAUSE_QUANTA2_delay; + assign CTL_TX_PAUSE_QUANTA3_in = CTL_TX_PAUSE_QUANTA3_delay; + assign CTL_TX_PAUSE_QUANTA4_in = CTL_TX_PAUSE_QUANTA4_delay; + assign CTL_TX_PAUSE_QUANTA5_in = CTL_TX_PAUSE_QUANTA5_delay; + assign CTL_TX_PAUSE_QUANTA6_in = CTL_TX_PAUSE_QUANTA6_delay; + assign CTL_TX_PAUSE_QUANTA7_in = CTL_TX_PAUSE_QUANTA7_delay; + assign CTL_TX_PAUSE_QUANTA8_in = CTL_TX_PAUSE_QUANTA8_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER0_in = CTL_TX_PAUSE_REFRESH_TIMER0_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER1_in = CTL_TX_PAUSE_REFRESH_TIMER1_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER2_in = CTL_TX_PAUSE_REFRESH_TIMER2_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER3_in = CTL_TX_PAUSE_REFRESH_TIMER3_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER4_in = CTL_TX_PAUSE_REFRESH_TIMER4_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER5_in = CTL_TX_PAUSE_REFRESH_TIMER5_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER6_in = CTL_TX_PAUSE_REFRESH_TIMER6_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER7_in = CTL_TX_PAUSE_REFRESH_TIMER7_delay; + assign CTL_TX_PAUSE_REFRESH_TIMER8_in = CTL_TX_PAUSE_REFRESH_TIMER8_delay; + assign CTL_TX_PAUSE_REQ_in = CTL_TX_PAUSE_REQ_delay; + assign CTL_TX_PTP_VLANE_ADJUST_MODE_in = CTL_TX_PTP_VLANE_ADJUST_MODE_delay; + assign CTL_TX_RESEND_PAUSE_in = CTL_TX_RESEND_PAUSE_delay; + assign CTL_TX_RSFEC_ENABLE_in = CTL_TX_RSFEC_ENABLE_delay; + assign CTL_TX_SEND_IDLE_in = CTL_TX_SEND_IDLE_delay; + assign CTL_TX_SEND_LFI_in = CTL_TX_SEND_LFI_delay; + assign CTL_TX_SEND_RFI_in = CTL_TX_SEND_RFI_delay; + assign CTL_TX_SYSTEMTIMERIN_in = CTL_TX_SYSTEMTIMERIN_delay; + assign CTL_TX_TEST_PATTERN_in = CTL_TX_TEST_PATTERN_delay; + assign DRP_ADDR_in = DRP_ADDR_delay; + assign DRP_CLK_in = DRP_CLK_delay; + assign DRP_DI_in = DRP_DI_delay; + assign DRP_EN_in = DRP_EN_delay; + assign DRP_WE_in = DRP_WE_delay; + assign RSFEC_BYPASS_RX_DIN_CW_START_in = RSFEC_BYPASS_RX_DIN_CW_START_delay; + assign RSFEC_BYPASS_RX_DIN_in = RSFEC_BYPASS_RX_DIN_delay; + assign RSFEC_BYPASS_TX_DIN_CW_START_in = RSFEC_BYPASS_TX_DIN_CW_START_delay; + assign RSFEC_BYPASS_TX_DIN_in = RSFEC_BYPASS_TX_DIN_delay; + assign RX_CLK_in = RX_CLK_delay; + assign RX_RESET_in = RX_RESET_delay; + assign RX_SERDES_ALT_DATA0_in = RX_SERDES_ALT_DATA0_delay; + assign RX_SERDES_ALT_DATA1_in = RX_SERDES_ALT_DATA1_delay; + assign RX_SERDES_ALT_DATA2_in = RX_SERDES_ALT_DATA2_delay; + assign RX_SERDES_ALT_DATA3_in = RX_SERDES_ALT_DATA3_delay; + assign RX_SERDES_CLK_in[0] = RX_SERDES_CLK_delay[0]; + assign RX_SERDES_CLK_in[1] = RX_SERDES_CLK_delay[1]; + assign RX_SERDES_CLK_in[2] = RX_SERDES_CLK_delay[2]; + assign RX_SERDES_CLK_in[3] = RX_SERDES_CLK_delay[3]; + assign RX_SERDES_CLK_in[4] = RX_SERDES_CLK_delay[4]; + assign RX_SERDES_CLK_in[5] = RX_SERDES_CLK_delay[5]; + assign RX_SERDES_CLK_in[6] = RX_SERDES_CLK_delay[6]; + assign RX_SERDES_CLK_in[7] = RX_SERDES_CLK_delay[7]; + assign RX_SERDES_CLK_in[8] = RX_SERDES_CLK_delay[8]; + assign RX_SERDES_CLK_in[9] = RX_SERDES_CLK_delay[9]; + assign RX_SERDES_DATA0_in = RX_SERDES_DATA0_delay; + assign RX_SERDES_DATA1_in = RX_SERDES_DATA1_delay; + assign RX_SERDES_DATA2_in = RX_SERDES_DATA2_delay; + assign RX_SERDES_DATA3_in = RX_SERDES_DATA3_delay; + assign RX_SERDES_DATA4_in = RX_SERDES_DATA4_delay; + assign RX_SERDES_DATA5_in = RX_SERDES_DATA5_delay; + assign RX_SERDES_DATA6_in = RX_SERDES_DATA6_delay; + assign RX_SERDES_DATA7_in = RX_SERDES_DATA7_delay; + assign RX_SERDES_DATA8_in = RX_SERDES_DATA8_delay; + assign RX_SERDES_DATA9_in = RX_SERDES_DATA9_delay; + assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay; + assign TX_CLK_in = TX_CLK_delay; + assign TX_DATAIN0_in = TX_DATAIN0_delay; + assign TX_DATAIN1_in = TX_DATAIN1_delay; + assign TX_DATAIN2_in = TX_DATAIN2_delay; + assign TX_DATAIN3_in = TX_DATAIN3_delay; + assign TX_ENAIN0_in = TX_ENAIN0_delay; + assign TX_ENAIN1_in = TX_ENAIN1_delay; + assign TX_ENAIN2_in = TX_ENAIN2_delay; + assign TX_ENAIN3_in = TX_ENAIN3_delay; + assign TX_EOPIN0_in = TX_EOPIN0_delay; + assign TX_EOPIN1_in = TX_EOPIN1_delay; + assign TX_EOPIN2_in = TX_EOPIN2_delay; + assign TX_EOPIN3_in = TX_EOPIN3_delay; + assign TX_ERRIN0_in = TX_ERRIN0_delay; + assign TX_ERRIN1_in = TX_ERRIN1_delay; + assign TX_ERRIN2_in = TX_ERRIN2_delay; + assign TX_ERRIN3_in = TX_ERRIN3_delay; + assign TX_MTYIN0_in = TX_MTYIN0_delay; + assign TX_MTYIN1_in = TX_MTYIN1_delay; + assign TX_MTYIN2_in = TX_MTYIN2_delay; + assign TX_MTYIN3_in = TX_MTYIN3_delay; + assign TX_PREIN_in = TX_PREIN_delay; + assign TX_PTP_1588OP_IN_in = TX_PTP_1588OP_IN_delay; + assign TX_PTP_CHKSUM_OFFSET_IN_in = TX_PTP_CHKSUM_OFFSET_IN_delay; + assign TX_PTP_RXTSTAMP_IN_in = TX_PTP_RXTSTAMP_IN_delay; + assign TX_PTP_TAG_FIELD_IN_in = TX_PTP_TAG_FIELD_IN_delay; + assign TX_PTP_TSTAMP_OFFSET_IN_in = TX_PTP_TSTAMP_OFFSET_IN_delay; + assign TX_PTP_UPD_CHKSUM_IN_in = TX_PTP_UPD_CHKSUM_IN_delay; + assign TX_RESET_in = TX_RESET_delay; + assign TX_SOPIN0_in = TX_SOPIN0_delay; + assign TX_SOPIN1_in = TX_SOPIN1_delay; + assign TX_SOPIN2_in = TX_SOPIN2_delay; + assign TX_SOPIN3_in = TX_SOPIN3_delay; +`else + assign CTL_CAUI4_MODE_in = CTL_CAUI4_MODE; + assign CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_in = CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE; + assign CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_in = CTL_RSFEC_IEEE_ERROR_INDICATION_MODE; + assign CTL_RX_CHECK_ETYPE_GCP_in = CTL_RX_CHECK_ETYPE_GCP; + assign CTL_RX_CHECK_ETYPE_GPP_in = CTL_RX_CHECK_ETYPE_GPP; + assign CTL_RX_CHECK_ETYPE_PCP_in = CTL_RX_CHECK_ETYPE_PCP; + assign CTL_RX_CHECK_ETYPE_PPP_in = CTL_RX_CHECK_ETYPE_PPP; + assign CTL_RX_CHECK_MCAST_GCP_in = CTL_RX_CHECK_MCAST_GCP; + assign CTL_RX_CHECK_MCAST_GPP_in = CTL_RX_CHECK_MCAST_GPP; + assign CTL_RX_CHECK_MCAST_PCP_in = CTL_RX_CHECK_MCAST_PCP; + assign CTL_RX_CHECK_MCAST_PPP_in = CTL_RX_CHECK_MCAST_PPP; + assign CTL_RX_CHECK_OPCODE_GCP_in = CTL_RX_CHECK_OPCODE_GCP; + assign CTL_RX_CHECK_OPCODE_GPP_in = CTL_RX_CHECK_OPCODE_GPP; + assign CTL_RX_CHECK_OPCODE_PCP_in = CTL_RX_CHECK_OPCODE_PCP; + assign CTL_RX_CHECK_OPCODE_PPP_in = CTL_RX_CHECK_OPCODE_PPP; + assign CTL_RX_CHECK_SA_GCP_in = CTL_RX_CHECK_SA_GCP; + assign CTL_RX_CHECK_SA_GPP_in = CTL_RX_CHECK_SA_GPP; + assign CTL_RX_CHECK_SA_PCP_in = CTL_RX_CHECK_SA_PCP; + assign CTL_RX_CHECK_SA_PPP_in = CTL_RX_CHECK_SA_PPP; + assign CTL_RX_CHECK_UCAST_GCP_in = CTL_RX_CHECK_UCAST_GCP; + assign CTL_RX_CHECK_UCAST_GPP_in = CTL_RX_CHECK_UCAST_GPP; + assign CTL_RX_CHECK_UCAST_PCP_in = CTL_RX_CHECK_UCAST_PCP; + assign CTL_RX_CHECK_UCAST_PPP_in = CTL_RX_CHECK_UCAST_PPP; + assign CTL_RX_ENABLE_GCP_in = CTL_RX_ENABLE_GCP; + assign CTL_RX_ENABLE_GPP_in = CTL_RX_ENABLE_GPP; + assign CTL_RX_ENABLE_PCP_in = CTL_RX_ENABLE_PCP; + assign CTL_RX_ENABLE_PPP_in = CTL_RX_ENABLE_PPP; + assign CTL_RX_ENABLE_in = CTL_RX_ENABLE; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC; + assign CTL_RX_PAUSE_ACK_in = CTL_RX_PAUSE_ACK; + assign CTL_RX_PAUSE_ENABLE_in = CTL_RX_PAUSE_ENABLE; + assign CTL_RX_RSFEC_ENABLE_CORRECTION_in = CTL_RX_RSFEC_ENABLE_CORRECTION; + assign CTL_RX_RSFEC_ENABLE_INDICATION_in = CTL_RX_RSFEC_ENABLE_INDICATION; + assign CTL_RX_RSFEC_ENABLE_in = CTL_RX_RSFEC_ENABLE; + assign CTL_RX_SYSTEMTIMERIN_in = CTL_RX_SYSTEMTIMERIN; + assign CTL_RX_TEST_PATTERN_in = CTL_RX_TEST_PATTERN; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + assign CTL_TX_PAUSE_ENABLE_in = CTL_TX_PAUSE_ENABLE; + assign CTL_TX_PAUSE_QUANTA0_in = CTL_TX_PAUSE_QUANTA0; + assign CTL_TX_PAUSE_QUANTA1_in = CTL_TX_PAUSE_QUANTA1; + assign CTL_TX_PAUSE_QUANTA2_in = CTL_TX_PAUSE_QUANTA2; + assign CTL_TX_PAUSE_QUANTA3_in = CTL_TX_PAUSE_QUANTA3; + assign CTL_TX_PAUSE_QUANTA4_in = CTL_TX_PAUSE_QUANTA4; + assign CTL_TX_PAUSE_QUANTA5_in = CTL_TX_PAUSE_QUANTA5; + assign CTL_TX_PAUSE_QUANTA6_in = CTL_TX_PAUSE_QUANTA6; + assign CTL_TX_PAUSE_QUANTA7_in = CTL_TX_PAUSE_QUANTA7; + assign CTL_TX_PAUSE_QUANTA8_in = CTL_TX_PAUSE_QUANTA8; + assign CTL_TX_PAUSE_REFRESH_TIMER0_in = CTL_TX_PAUSE_REFRESH_TIMER0; + assign CTL_TX_PAUSE_REFRESH_TIMER1_in = CTL_TX_PAUSE_REFRESH_TIMER1; + assign CTL_TX_PAUSE_REFRESH_TIMER2_in = CTL_TX_PAUSE_REFRESH_TIMER2; + assign CTL_TX_PAUSE_REFRESH_TIMER3_in = CTL_TX_PAUSE_REFRESH_TIMER3; + assign CTL_TX_PAUSE_REFRESH_TIMER4_in = CTL_TX_PAUSE_REFRESH_TIMER4; + assign CTL_TX_PAUSE_REFRESH_TIMER5_in = CTL_TX_PAUSE_REFRESH_TIMER5; + assign CTL_TX_PAUSE_REFRESH_TIMER6_in = CTL_TX_PAUSE_REFRESH_TIMER6; + assign CTL_TX_PAUSE_REFRESH_TIMER7_in = CTL_TX_PAUSE_REFRESH_TIMER7; + assign CTL_TX_PAUSE_REFRESH_TIMER8_in = CTL_TX_PAUSE_REFRESH_TIMER8; + assign CTL_TX_PAUSE_REQ_in = CTL_TX_PAUSE_REQ; + assign CTL_TX_PTP_VLANE_ADJUST_MODE_in = CTL_TX_PTP_VLANE_ADJUST_MODE; + assign CTL_TX_RESEND_PAUSE_in = CTL_TX_RESEND_PAUSE; + assign CTL_TX_RSFEC_ENABLE_in = CTL_TX_RSFEC_ENABLE; + assign CTL_TX_SEND_IDLE_in = CTL_TX_SEND_IDLE; + assign CTL_TX_SEND_LFI_in = CTL_TX_SEND_LFI; + assign CTL_TX_SEND_RFI_in = CTL_TX_SEND_RFI; + assign CTL_TX_SYSTEMTIMERIN_in = CTL_TX_SYSTEMTIMERIN; + assign CTL_TX_TEST_PATTERN_in = CTL_TX_TEST_PATTERN; + assign DRP_ADDR_in = DRP_ADDR; + assign DRP_CLK_in = DRP_CLK; + assign DRP_DI_in = DRP_DI; + assign DRP_EN_in = DRP_EN; + assign DRP_WE_in = DRP_WE; + assign RSFEC_BYPASS_RX_DIN_CW_START_in = RSFEC_BYPASS_RX_DIN_CW_START; + assign RSFEC_BYPASS_RX_DIN_in = RSFEC_BYPASS_RX_DIN; + assign RSFEC_BYPASS_TX_DIN_CW_START_in = RSFEC_BYPASS_TX_DIN_CW_START; + assign RSFEC_BYPASS_TX_DIN_in = RSFEC_BYPASS_TX_DIN; + assign RX_CLK_in = RX_CLK; + assign RX_RESET_in = RX_RESET; + assign RX_SERDES_ALT_DATA0_in = RX_SERDES_ALT_DATA0; + assign RX_SERDES_ALT_DATA1_in = RX_SERDES_ALT_DATA1; + assign RX_SERDES_ALT_DATA2_in = RX_SERDES_ALT_DATA2; + assign RX_SERDES_ALT_DATA3_in = RX_SERDES_ALT_DATA3; + assign RX_SERDES_CLK_in[0] = RX_SERDES_CLK[0]; + assign RX_SERDES_CLK_in[1] = RX_SERDES_CLK[1]; + assign RX_SERDES_CLK_in[2] = RX_SERDES_CLK[2]; + assign RX_SERDES_CLK_in[3] = RX_SERDES_CLK[3]; + assign RX_SERDES_CLK_in[4] = RX_SERDES_CLK[4]; + assign RX_SERDES_CLK_in[5] = RX_SERDES_CLK[5]; + assign RX_SERDES_CLK_in[6] = RX_SERDES_CLK[6]; + assign RX_SERDES_CLK_in[7] = RX_SERDES_CLK[7]; + assign RX_SERDES_CLK_in[8] = RX_SERDES_CLK[8]; + assign RX_SERDES_CLK_in[9] = RX_SERDES_CLK[9]; + assign RX_SERDES_DATA0_in = RX_SERDES_DATA0; + assign RX_SERDES_DATA1_in = RX_SERDES_DATA1; + assign RX_SERDES_DATA2_in = RX_SERDES_DATA2; + assign RX_SERDES_DATA3_in = RX_SERDES_DATA3; + assign RX_SERDES_DATA4_in = RX_SERDES_DATA4; + assign RX_SERDES_DATA5_in = RX_SERDES_DATA5; + assign RX_SERDES_DATA6_in = RX_SERDES_DATA6; + assign RX_SERDES_DATA7_in = RX_SERDES_DATA7; + assign RX_SERDES_DATA8_in = RX_SERDES_DATA8; + assign RX_SERDES_DATA9_in = RX_SERDES_DATA9; + assign RX_SERDES_RESET_in = RX_SERDES_RESET; + assign TX_CLK_in = TX_CLK; + assign TX_DATAIN0_in = TX_DATAIN0; + assign TX_DATAIN1_in = TX_DATAIN1; + assign TX_DATAIN2_in = TX_DATAIN2; + assign TX_DATAIN3_in = TX_DATAIN3; + assign TX_ENAIN0_in = TX_ENAIN0; + assign TX_ENAIN1_in = TX_ENAIN1; + assign TX_ENAIN2_in = TX_ENAIN2; + assign TX_ENAIN3_in = TX_ENAIN3; + assign TX_EOPIN0_in = TX_EOPIN0; + assign TX_EOPIN1_in = TX_EOPIN1; + assign TX_EOPIN2_in = TX_EOPIN2; + assign TX_EOPIN3_in = TX_EOPIN3; + assign TX_ERRIN0_in = TX_ERRIN0; + assign TX_ERRIN1_in = TX_ERRIN1; + assign TX_ERRIN2_in = TX_ERRIN2; + assign TX_ERRIN3_in = TX_ERRIN3; + assign TX_MTYIN0_in = TX_MTYIN0; + assign TX_MTYIN1_in = TX_MTYIN1; + assign TX_MTYIN2_in = TX_MTYIN2; + assign TX_MTYIN3_in = TX_MTYIN3; + assign TX_PREIN_in = TX_PREIN; + assign TX_PTP_1588OP_IN_in = TX_PTP_1588OP_IN; + assign TX_PTP_CHKSUM_OFFSET_IN_in = TX_PTP_CHKSUM_OFFSET_IN; + assign TX_PTP_RXTSTAMP_IN_in = TX_PTP_RXTSTAMP_IN; + assign TX_PTP_TAG_FIELD_IN_in = TX_PTP_TAG_FIELD_IN; + assign TX_PTP_TSTAMP_OFFSET_IN_in = TX_PTP_TSTAMP_OFFSET_IN; + assign TX_PTP_UPD_CHKSUM_IN_in = TX_PTP_UPD_CHKSUM_IN; + assign TX_RESET_in = TX_RESET; + assign TX_SOPIN0_in = TX_SOPIN0; + assign TX_SOPIN1_in = TX_SOPIN1; + assign TX_SOPIN2_in = TX_SOPIN2; + assign TX_SOPIN3_in = TX_SOPIN3; +`endif + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CTL_PTP_TRANSPCLK_MODE_REG != "FALSE") && + (CTL_PTP_TRANSPCLK_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] CTL_PTP_TRANSPCLK_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_PTP_TRANSPCLK_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_ACK_REG != "TRUE") && + (CTL_RX_CHECK_ACK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-110] CTL_RX_CHECK_ACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_ACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_PREAMBLE_REG != "FALSE") && + (CTL_RX_CHECK_PREAMBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] CTL_RX_CHECK_PREAMBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_PREAMBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_CHECK_SFD_REG != "FALSE") && + (CTL_RX_CHECK_SFD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] CTL_RX_CHECK_SFD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_SFD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_DELETE_FCS_REG != "TRUE") && + (CTL_RX_DELETE_FCS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-113] CTL_RX_DELETE_FCS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_DELETE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_ETYPE_GCP_REG < 16'h0600) || (CTL_RX_ETYPE_GCP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-114] CTL_RX_ETYPE_GCP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_GCP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_ETYPE_GPP_REG < 16'h0600) || (CTL_RX_ETYPE_GPP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-115] CTL_RX_ETYPE_GPP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_GPP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_ETYPE_PCP_REG < 16'h0600) || (CTL_RX_ETYPE_PCP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-116] CTL_RX_ETYPE_PCP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_PCP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_ETYPE_PPP_REG < 16'h0600) || (CTL_RX_ETYPE_PPP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-117] CTL_RX_ETYPE_PPP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_PPP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_FORWARD_CONTROL_REG != "FALSE") && + (CTL_RX_FORWARD_CONTROL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] CTL_RX_FORWARD_CONTROL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_FORWARD_CONTROL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_IGNORE_FCS_REG != "FALSE") && + (CTL_RX_IGNORE_FCS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-119] CTL_RX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_IGNORE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_MAX_PACKET_LEN_REG < 15'h0040) || (CTL_RX_MAX_PACKET_LEN_REG > 15'h3FFF))) begin + $display("Error: [Unisim %s-120] CTL_RX_MAX_PACKET_LEN attribute is set to %h. Legal values for this attribute are 15'h0040 to 15'h3FFF. Instance: %m", MODULE_NAME, CTL_RX_MAX_PACKET_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_MIN_PACKET_LEN_REG < 8'h40) || (CTL_RX_MIN_PACKET_LEN_REG > 8'hFF))) begin + $display("Error: [Unisim %s-121] CTL_RX_MIN_PACKET_LEN attribute is set to %h. Legal values for this attribute are 8'h40 to 8'hFF. Instance: %m", MODULE_NAME, CTL_RX_MIN_PACKET_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_PROCESS_LFI_REG != "FALSE") && + (CTL_RX_PROCESS_LFI_REG != "TRUE"))) begin + $display("Error: [Unisim %s-131] CTL_RX_PROCESS_LFI attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_PROCESS_LFI_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_VL_LENGTH_MINUS1_REG < 16'h01FF) || (CTL_RX_VL_LENGTH_MINUS1_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-134] CTL_RX_VL_LENGTH_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h01FF to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_LENGTH_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") && + (CTL_TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-155] CTL_TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_CUSTOM_PREAMBLE_ENABLE_REG != "FALSE") && + (CTL_TX_CUSTOM_PREAMBLE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-156] CTL_TX_CUSTOM_PREAMBLE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_CUSTOM_PREAMBLE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_ETHERTYPE_GPP_REG < 16'h0600) || (CTL_TX_ETHERTYPE_GPP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-159] CTL_TX_ETHERTYPE_GPP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_ETHERTYPE_GPP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_ETHERTYPE_PPP_REG < 16'h0600) || (CTL_TX_ETHERTYPE_PPP_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-160] CTL_TX_ETHERTYPE_PPP attribute is set to %h. Legal values for this attribute are 16'h0600 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_ETHERTYPE_PPP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_FCS_INS_ENABLE_REG != "TRUE") && + (CTL_TX_FCS_INS_ENABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-161] CTL_TX_FCS_INS_ENABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_TX_FCS_INS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_IGNORE_FCS_REG != "FALSE") && + (CTL_TX_IGNORE_FCS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-162] CTL_TX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_IGNORE_FCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_PTP_1STEP_ENABLE_REG != "FALSE") && + (CTL_TX_PTP_1STEP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-166] CTL_TX_PTP_1STEP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_PTP_1STEP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_VL_LENGTH_MINUS1_REG < 16'h01FF) || (CTL_TX_VL_LENGTH_MINUS1_REG > 16'hFFFF))) begin + $display("Error: [Unisim %s-170] CTL_TX_VL_LENGTH_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h01FF to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_LENGTH_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-191] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TEST_MODE_PIN_CHAR_REG != "FALSE") && + (TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-192] TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign CSSD_CLK_STOP_EVENT_in = 1'b1; // tie off + assign CSSD_RESETN_in = 1'b1; // tie off + assign SCAN_CLK_in = 1'b1; // tie off + assign SCAN_EN_N_in = 1'b1; // tie off + assign SCAN_IN_in = 268'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign TEST_MODE_N_in = 1'b1; // tie off + assign TEST_RESET_in = 1'b1; // tie off + + SIP_CMACE4 SIP_CMACE4_INST ( + .CTL_CSSD_EN (CTL_CSSD_EN_REG), + .CTL_CSSD_MRKR_INIT (CTL_CSSD_MRKR_INIT_REG), + .CTL_CSSD_ROOT_CLK_DIS (CTL_CSSD_ROOT_CLK_DIS_REG), + .CTL_CSSD_ROOT_CLK_SEL (CTL_CSSD_ROOT_CLK_SEL_REG), + .CTL_CSSD_SNGL_CHAIN_MD (CTL_CSSD_SNGL_CHAIN_MD_REG), + .CTL_CSSD_STOP_COUNT_0 (CTL_CSSD_STOP_COUNT_0_REG), + .CTL_CSSD_STOP_COUNT_1 (CTL_CSSD_STOP_COUNT_1_REG), + .CTL_CSSD_STOP_COUNT_2 (CTL_CSSD_STOP_COUNT_2_REG), + .CTL_PTP_TRANSPCLK_MODE (CTL_PTP_TRANSPCLK_MODE_REG), + .CTL_RX_CHECK_ACK (CTL_RX_CHECK_ACK_REG), + .CTL_RX_CHECK_PREAMBLE (CTL_RX_CHECK_PREAMBLE_REG), + .CTL_RX_CHECK_SFD (CTL_RX_CHECK_SFD_REG), + .CTL_RX_DELETE_FCS (CTL_RX_DELETE_FCS_REG), + .CTL_RX_ETYPE_GCP (CTL_RX_ETYPE_GCP_REG), + .CTL_RX_ETYPE_GPP (CTL_RX_ETYPE_GPP_REG), + .CTL_RX_ETYPE_PCP (CTL_RX_ETYPE_PCP_REG), + .CTL_RX_ETYPE_PPP (CTL_RX_ETYPE_PPP_REG), + .CTL_RX_FORWARD_CONTROL (CTL_RX_FORWARD_CONTROL_REG), + .CTL_RX_IGNORE_FCS (CTL_RX_IGNORE_FCS_REG), + .CTL_RX_MAX_PACKET_LEN (CTL_RX_MAX_PACKET_LEN_REG), + .CTL_RX_MIN_PACKET_LEN (CTL_RX_MIN_PACKET_LEN_REG), + .CTL_RX_OPCODE_GPP (CTL_RX_OPCODE_GPP_REG), + .CTL_RX_OPCODE_MAX_GCP (CTL_RX_OPCODE_MAX_GCP_REG), + .CTL_RX_OPCODE_MAX_PCP (CTL_RX_OPCODE_MAX_PCP_REG), + .CTL_RX_OPCODE_MIN_GCP (CTL_RX_OPCODE_MIN_GCP_REG), + .CTL_RX_OPCODE_MIN_PCP (CTL_RX_OPCODE_MIN_PCP_REG), + .CTL_RX_OPCODE_PPP (CTL_RX_OPCODE_PPP_REG), + .CTL_RX_PAUSE_DA_MCAST (CTL_RX_PAUSE_DA_MCAST_REG), + .CTL_RX_PAUSE_DA_UCAST (CTL_RX_PAUSE_DA_UCAST_REG), + .CTL_RX_PAUSE_SA (CTL_RX_PAUSE_SA_REG), + .CTL_RX_PROCESS_LFI (CTL_RX_PROCESS_LFI_REG), + .CTL_RX_RSFEC_AM_THRESHOLD (CTL_RX_RSFEC_AM_THRESHOLD_REG), + .CTL_RX_RSFEC_FILL_ADJUST (CTL_RX_RSFEC_FILL_ADJUST_REG), + .CTL_RX_VL_LENGTH_MINUS1 (CTL_RX_VL_LENGTH_MINUS1_REG), + .CTL_RX_VL_MARKER_ID0 (CTL_RX_VL_MARKER_ID0_REG), + .CTL_RX_VL_MARKER_ID1 (CTL_RX_VL_MARKER_ID1_REG), + .CTL_RX_VL_MARKER_ID10 (CTL_RX_VL_MARKER_ID10_REG), + .CTL_RX_VL_MARKER_ID11 (CTL_RX_VL_MARKER_ID11_REG), + .CTL_RX_VL_MARKER_ID12 (CTL_RX_VL_MARKER_ID12_REG), + .CTL_RX_VL_MARKER_ID13 (CTL_RX_VL_MARKER_ID13_REG), + .CTL_RX_VL_MARKER_ID14 (CTL_RX_VL_MARKER_ID14_REG), + .CTL_RX_VL_MARKER_ID15 (CTL_RX_VL_MARKER_ID15_REG), + .CTL_RX_VL_MARKER_ID16 (CTL_RX_VL_MARKER_ID16_REG), + .CTL_RX_VL_MARKER_ID17 (CTL_RX_VL_MARKER_ID17_REG), + .CTL_RX_VL_MARKER_ID18 (CTL_RX_VL_MARKER_ID18_REG), + .CTL_RX_VL_MARKER_ID19 (CTL_RX_VL_MARKER_ID19_REG), + .CTL_RX_VL_MARKER_ID2 (CTL_RX_VL_MARKER_ID2_REG), + .CTL_RX_VL_MARKER_ID3 (CTL_RX_VL_MARKER_ID3_REG), + .CTL_RX_VL_MARKER_ID4 (CTL_RX_VL_MARKER_ID4_REG), + .CTL_RX_VL_MARKER_ID5 (CTL_RX_VL_MARKER_ID5_REG), + .CTL_RX_VL_MARKER_ID6 (CTL_RX_VL_MARKER_ID6_REG), + .CTL_RX_VL_MARKER_ID7 (CTL_RX_VL_MARKER_ID7_REG), + .CTL_RX_VL_MARKER_ID8 (CTL_RX_VL_MARKER_ID8_REG), + .CTL_RX_VL_MARKER_ID9 (CTL_RX_VL_MARKER_ID9_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_CUSTOM_PREAMBLE_ENABLE (CTL_TX_CUSTOM_PREAMBLE_ENABLE_REG), + .CTL_TX_DA_GPP (CTL_TX_DA_GPP_REG), + .CTL_TX_DA_PPP (CTL_TX_DA_PPP_REG), + .CTL_TX_ETHERTYPE_GPP (CTL_TX_ETHERTYPE_GPP_REG), + .CTL_TX_ETHERTYPE_PPP (CTL_TX_ETHERTYPE_PPP_REG), + .CTL_TX_FCS_INS_ENABLE (CTL_TX_FCS_INS_ENABLE_REG), + .CTL_TX_IGNORE_FCS (CTL_TX_IGNORE_FCS_REG), + .CTL_TX_IPG_VALUE (CTL_TX_IPG_VALUE_REG), + .CTL_TX_OPCODE_GPP (CTL_TX_OPCODE_GPP_REG), + .CTL_TX_OPCODE_PPP (CTL_TX_OPCODE_PPP_REG), + .CTL_TX_PTP_1STEP_ENABLE (CTL_TX_PTP_1STEP_ENABLE_REG), + .CTL_TX_PTP_LATENCY_ADJUST (CTL_TX_PTP_LATENCY_ADJUST_REG), + .CTL_TX_SA_GPP (CTL_TX_SA_GPP_REG), + .CTL_TX_SA_PPP (CTL_TX_SA_PPP_REG), + .CTL_TX_VL_LENGTH_MINUS1 (CTL_TX_VL_LENGTH_MINUS1_REG), + .CTL_TX_VL_MARKER_ID0 (CTL_TX_VL_MARKER_ID0_REG), + .CTL_TX_VL_MARKER_ID1 (CTL_TX_VL_MARKER_ID1_REG), + .CTL_TX_VL_MARKER_ID10 (CTL_TX_VL_MARKER_ID10_REG), + .CTL_TX_VL_MARKER_ID11 (CTL_TX_VL_MARKER_ID11_REG), + .CTL_TX_VL_MARKER_ID12 (CTL_TX_VL_MARKER_ID12_REG), + .CTL_TX_VL_MARKER_ID13 (CTL_TX_VL_MARKER_ID13_REG), + .CTL_TX_VL_MARKER_ID14 (CTL_TX_VL_MARKER_ID14_REG), + .CTL_TX_VL_MARKER_ID15 (CTL_TX_VL_MARKER_ID15_REG), + .CTL_TX_VL_MARKER_ID16 (CTL_TX_VL_MARKER_ID16_REG), + .CTL_TX_VL_MARKER_ID17 (CTL_TX_VL_MARKER_ID17_REG), + .CTL_TX_VL_MARKER_ID18 (CTL_TX_VL_MARKER_ID18_REG), + .CTL_TX_VL_MARKER_ID19 (CTL_TX_VL_MARKER_ID19_REG), + .CTL_TX_VL_MARKER_ID2 (CTL_TX_VL_MARKER_ID2_REG), + .CTL_TX_VL_MARKER_ID3 (CTL_TX_VL_MARKER_ID3_REG), + .CTL_TX_VL_MARKER_ID4 (CTL_TX_VL_MARKER_ID4_REG), + .CTL_TX_VL_MARKER_ID5 (CTL_TX_VL_MARKER_ID5_REG), + .CTL_TX_VL_MARKER_ID6 (CTL_TX_VL_MARKER_ID6_REG), + .CTL_TX_VL_MARKER_ID7 (CTL_TX_VL_MARKER_ID7_REG), + .CTL_TX_VL_MARKER_ID8 (CTL_TX_VL_MARKER_ID8_REG), + .CTL_TX_VL_MARKER_ID9 (CTL_TX_VL_MARKER_ID9_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .CFG_RESET_CSSD (CFG_RESET_CSSD_out), + .CSSD_CLK_STOP_DONE (CSSD_CLK_STOP_DONE_out), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .GRESTORE_CSSD (GRESTORE_CSSD_out), + .GWE_CSSD (GWE_CSSD_out), + .RSFEC_BYPASS_RX_DOUT (RSFEC_BYPASS_RX_DOUT_out), + .RSFEC_BYPASS_RX_DOUT_CW_START (RSFEC_BYPASS_RX_DOUT_CW_START_out), + .RSFEC_BYPASS_RX_DOUT_VALID (RSFEC_BYPASS_RX_DOUT_VALID_out), + .RSFEC_BYPASS_TX_DOUT (RSFEC_BYPASS_TX_DOUT_out), + .RSFEC_BYPASS_TX_DOUT_CW_START (RSFEC_BYPASS_TX_DOUT_CW_START_out), + .RSFEC_BYPASS_TX_DOUT_VALID (RSFEC_BYPASS_TX_DOUT_VALID_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_LANE_ALIGNER_FILL_0 (RX_LANE_ALIGNER_FILL_0_out), + .RX_LANE_ALIGNER_FILL_1 (RX_LANE_ALIGNER_FILL_1_out), + .RX_LANE_ALIGNER_FILL_10 (RX_LANE_ALIGNER_FILL_10_out), + .RX_LANE_ALIGNER_FILL_11 (RX_LANE_ALIGNER_FILL_11_out), + .RX_LANE_ALIGNER_FILL_12 (RX_LANE_ALIGNER_FILL_12_out), + .RX_LANE_ALIGNER_FILL_13 (RX_LANE_ALIGNER_FILL_13_out), + .RX_LANE_ALIGNER_FILL_14 (RX_LANE_ALIGNER_FILL_14_out), + .RX_LANE_ALIGNER_FILL_15 (RX_LANE_ALIGNER_FILL_15_out), + .RX_LANE_ALIGNER_FILL_16 (RX_LANE_ALIGNER_FILL_16_out), + .RX_LANE_ALIGNER_FILL_17 (RX_LANE_ALIGNER_FILL_17_out), + .RX_LANE_ALIGNER_FILL_18 (RX_LANE_ALIGNER_FILL_18_out), + .RX_LANE_ALIGNER_FILL_19 (RX_LANE_ALIGNER_FILL_19_out), + .RX_LANE_ALIGNER_FILL_2 (RX_LANE_ALIGNER_FILL_2_out), + .RX_LANE_ALIGNER_FILL_3 (RX_LANE_ALIGNER_FILL_3_out), + .RX_LANE_ALIGNER_FILL_4 (RX_LANE_ALIGNER_FILL_4_out), + .RX_LANE_ALIGNER_FILL_5 (RX_LANE_ALIGNER_FILL_5_out), + .RX_LANE_ALIGNER_FILL_6 (RX_LANE_ALIGNER_FILL_6_out), + .RX_LANE_ALIGNER_FILL_7 (RX_LANE_ALIGNER_FILL_7_out), + .RX_LANE_ALIGNER_FILL_8 (RX_LANE_ALIGNER_FILL_8_out), + .RX_LANE_ALIGNER_FILL_9 (RX_LANE_ALIGNER_FILL_9_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_OTN_BIP8_0 (RX_OTN_BIP8_0_out), + .RX_OTN_BIP8_1 (RX_OTN_BIP8_1_out), + .RX_OTN_BIP8_2 (RX_OTN_BIP8_2_out), + .RX_OTN_BIP8_3 (RX_OTN_BIP8_3_out), + .RX_OTN_BIP8_4 (RX_OTN_BIP8_4_out), + .RX_OTN_DATA_0 (RX_OTN_DATA_0_out), + .RX_OTN_DATA_1 (RX_OTN_DATA_1_out), + .RX_OTN_DATA_2 (RX_OTN_DATA_2_out), + .RX_OTN_DATA_3 (RX_OTN_DATA_3_out), + .RX_OTN_DATA_4 (RX_OTN_DATA_4_out), + .RX_OTN_ENA (RX_OTN_ENA_out), + .RX_OTN_LANE0 (RX_OTN_LANE0_out), + .RX_OTN_VLMARKER (RX_OTN_VLMARKER_out), + .RX_PREOUT (RX_PREOUT_out), + .RX_PTP_PCSLANE_OUT (RX_PTP_PCSLANE_OUT_out), + .RX_PTP_TSTAMP_OUT (RX_PTP_TSTAMP_OUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT (SCAN_OUT_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_CODE (STAT_RX_BAD_CODE_out), + .STAT_RX_BAD_FCS (STAT_RX_BAD_FCS_out), + .STAT_RX_BAD_PREAMBLE (STAT_RX_BAD_PREAMBLE_out), + .STAT_RX_BAD_SFD (STAT_RX_BAD_SFD_out), + .STAT_RX_BIP_ERR_0 (STAT_RX_BIP_ERR_0_out), + .STAT_RX_BIP_ERR_1 (STAT_RX_BIP_ERR_1_out), + .STAT_RX_BIP_ERR_10 (STAT_RX_BIP_ERR_10_out), + .STAT_RX_BIP_ERR_11 (STAT_RX_BIP_ERR_11_out), + .STAT_RX_BIP_ERR_12 (STAT_RX_BIP_ERR_12_out), + .STAT_RX_BIP_ERR_13 (STAT_RX_BIP_ERR_13_out), + .STAT_RX_BIP_ERR_14 (STAT_RX_BIP_ERR_14_out), + .STAT_RX_BIP_ERR_15 (STAT_RX_BIP_ERR_15_out), + .STAT_RX_BIP_ERR_16 (STAT_RX_BIP_ERR_16_out), + .STAT_RX_BIP_ERR_17 (STAT_RX_BIP_ERR_17_out), + .STAT_RX_BIP_ERR_18 (STAT_RX_BIP_ERR_18_out), + .STAT_RX_BIP_ERR_19 (STAT_RX_BIP_ERR_19_out), + .STAT_RX_BIP_ERR_2 (STAT_RX_BIP_ERR_2_out), + .STAT_RX_BIP_ERR_3 (STAT_RX_BIP_ERR_3_out), + .STAT_RX_BIP_ERR_4 (STAT_RX_BIP_ERR_4_out), + .STAT_RX_BIP_ERR_5 (STAT_RX_BIP_ERR_5_out), + .STAT_RX_BIP_ERR_6 (STAT_RX_BIP_ERR_6_out), + .STAT_RX_BIP_ERR_7 (STAT_RX_BIP_ERR_7_out), + .STAT_RX_BIP_ERR_8 (STAT_RX_BIP_ERR_8_out), + .STAT_RX_BIP_ERR_9 (STAT_RX_BIP_ERR_9_out), + .STAT_RX_BLOCK_LOCK (STAT_RX_BLOCK_LOCK_out), + .STAT_RX_BROADCAST (STAT_RX_BROADCAST_out), + .STAT_RX_FRAGMENT (STAT_RX_FRAGMENT_out), + .STAT_RX_FRAMING_ERR_0 (STAT_RX_FRAMING_ERR_0_out), + .STAT_RX_FRAMING_ERR_1 (STAT_RX_FRAMING_ERR_1_out), + .STAT_RX_FRAMING_ERR_10 (STAT_RX_FRAMING_ERR_10_out), + .STAT_RX_FRAMING_ERR_11 (STAT_RX_FRAMING_ERR_11_out), + .STAT_RX_FRAMING_ERR_12 (STAT_RX_FRAMING_ERR_12_out), + .STAT_RX_FRAMING_ERR_13 (STAT_RX_FRAMING_ERR_13_out), + .STAT_RX_FRAMING_ERR_14 (STAT_RX_FRAMING_ERR_14_out), + .STAT_RX_FRAMING_ERR_15 (STAT_RX_FRAMING_ERR_15_out), + .STAT_RX_FRAMING_ERR_16 (STAT_RX_FRAMING_ERR_16_out), + .STAT_RX_FRAMING_ERR_17 (STAT_RX_FRAMING_ERR_17_out), + .STAT_RX_FRAMING_ERR_18 (STAT_RX_FRAMING_ERR_18_out), + .STAT_RX_FRAMING_ERR_19 (STAT_RX_FRAMING_ERR_19_out), + .STAT_RX_FRAMING_ERR_2 (STAT_RX_FRAMING_ERR_2_out), + .STAT_RX_FRAMING_ERR_3 (STAT_RX_FRAMING_ERR_3_out), + .STAT_RX_FRAMING_ERR_4 (STAT_RX_FRAMING_ERR_4_out), + .STAT_RX_FRAMING_ERR_5 (STAT_RX_FRAMING_ERR_5_out), + .STAT_RX_FRAMING_ERR_6 (STAT_RX_FRAMING_ERR_6_out), + .STAT_RX_FRAMING_ERR_7 (STAT_RX_FRAMING_ERR_7_out), + .STAT_RX_FRAMING_ERR_8 (STAT_RX_FRAMING_ERR_8_out), + .STAT_RX_FRAMING_ERR_9 (STAT_RX_FRAMING_ERR_9_out), + .STAT_RX_FRAMING_ERR_VALID_0 (STAT_RX_FRAMING_ERR_VALID_0_out), + .STAT_RX_FRAMING_ERR_VALID_1 (STAT_RX_FRAMING_ERR_VALID_1_out), + .STAT_RX_FRAMING_ERR_VALID_10 (STAT_RX_FRAMING_ERR_VALID_10_out), + .STAT_RX_FRAMING_ERR_VALID_11 (STAT_RX_FRAMING_ERR_VALID_11_out), + .STAT_RX_FRAMING_ERR_VALID_12 (STAT_RX_FRAMING_ERR_VALID_12_out), + .STAT_RX_FRAMING_ERR_VALID_13 (STAT_RX_FRAMING_ERR_VALID_13_out), + .STAT_RX_FRAMING_ERR_VALID_14 (STAT_RX_FRAMING_ERR_VALID_14_out), + .STAT_RX_FRAMING_ERR_VALID_15 (STAT_RX_FRAMING_ERR_VALID_15_out), + .STAT_RX_FRAMING_ERR_VALID_16 (STAT_RX_FRAMING_ERR_VALID_16_out), + .STAT_RX_FRAMING_ERR_VALID_17 (STAT_RX_FRAMING_ERR_VALID_17_out), + .STAT_RX_FRAMING_ERR_VALID_18 (STAT_RX_FRAMING_ERR_VALID_18_out), + .STAT_RX_FRAMING_ERR_VALID_19 (STAT_RX_FRAMING_ERR_VALID_19_out), + .STAT_RX_FRAMING_ERR_VALID_2 (STAT_RX_FRAMING_ERR_VALID_2_out), + .STAT_RX_FRAMING_ERR_VALID_3 (STAT_RX_FRAMING_ERR_VALID_3_out), + .STAT_RX_FRAMING_ERR_VALID_4 (STAT_RX_FRAMING_ERR_VALID_4_out), + .STAT_RX_FRAMING_ERR_VALID_5 (STAT_RX_FRAMING_ERR_VALID_5_out), + .STAT_RX_FRAMING_ERR_VALID_6 (STAT_RX_FRAMING_ERR_VALID_6_out), + .STAT_RX_FRAMING_ERR_VALID_7 (STAT_RX_FRAMING_ERR_VALID_7_out), + .STAT_RX_FRAMING_ERR_VALID_8 (STAT_RX_FRAMING_ERR_VALID_8_out), + .STAT_RX_FRAMING_ERR_VALID_9 (STAT_RX_FRAMING_ERR_VALID_9_out), + .STAT_RX_GOT_SIGNAL_OS (STAT_RX_GOT_SIGNAL_OS_out), + .STAT_RX_HI_BER (STAT_RX_HI_BER_out), + .STAT_RX_INRANGEERR (STAT_RX_INRANGEERR_out), + .STAT_RX_INTERNAL_LOCAL_FAULT (STAT_RX_INTERNAL_LOCAL_FAULT_out), + .STAT_RX_JABBER (STAT_RX_JABBER_out), + .STAT_RX_LANE0_VLM_BIP7 (STAT_RX_LANE0_VLM_BIP7_out), + .STAT_RX_LANE0_VLM_BIP7_VALID (STAT_RX_LANE0_VLM_BIP7_VALID_out), + .STAT_RX_LOCAL_FAULT (STAT_RX_LOCAL_FAULT_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MULTICAST (STAT_RX_MULTICAST_out), + .STAT_RX_OVERSIZE (STAT_RX_OVERSIZE_out), + .STAT_RX_PACKET_1024_1518_BYTES (STAT_RX_PACKET_1024_1518_BYTES_out), + .STAT_RX_PACKET_128_255_BYTES (STAT_RX_PACKET_128_255_BYTES_out), + .STAT_RX_PACKET_1519_1522_BYTES (STAT_RX_PACKET_1519_1522_BYTES_out), + .STAT_RX_PACKET_1523_1548_BYTES (STAT_RX_PACKET_1523_1548_BYTES_out), + .STAT_RX_PACKET_1549_2047_BYTES (STAT_RX_PACKET_1549_2047_BYTES_out), + .STAT_RX_PACKET_2048_4095_BYTES (STAT_RX_PACKET_2048_4095_BYTES_out), + .STAT_RX_PACKET_256_511_BYTES (STAT_RX_PACKET_256_511_BYTES_out), + .STAT_RX_PACKET_4096_8191_BYTES (STAT_RX_PACKET_4096_8191_BYTES_out), + .STAT_RX_PACKET_512_1023_BYTES (STAT_RX_PACKET_512_1023_BYTES_out), + .STAT_RX_PACKET_64_BYTES (STAT_RX_PACKET_64_BYTES_out), + .STAT_RX_PACKET_65_127_BYTES (STAT_RX_PACKET_65_127_BYTES_out), + .STAT_RX_PACKET_8192_9215_BYTES (STAT_RX_PACKET_8192_9215_BYTES_out), + .STAT_RX_PACKET_BAD_FCS (STAT_RX_PACKET_BAD_FCS_out), + .STAT_RX_PACKET_LARGE (STAT_RX_PACKET_LARGE_out), + .STAT_RX_PACKET_SMALL (STAT_RX_PACKET_SMALL_out), + .STAT_RX_PAUSE (STAT_RX_PAUSE_out), + .STAT_RX_PAUSE_QUANTA0 (STAT_RX_PAUSE_QUANTA0_out), + .STAT_RX_PAUSE_QUANTA1 (STAT_RX_PAUSE_QUANTA1_out), + .STAT_RX_PAUSE_QUANTA2 (STAT_RX_PAUSE_QUANTA2_out), + .STAT_RX_PAUSE_QUANTA3 (STAT_RX_PAUSE_QUANTA3_out), + .STAT_RX_PAUSE_QUANTA4 (STAT_RX_PAUSE_QUANTA4_out), + .STAT_RX_PAUSE_QUANTA5 (STAT_RX_PAUSE_QUANTA5_out), + .STAT_RX_PAUSE_QUANTA6 (STAT_RX_PAUSE_QUANTA6_out), + .STAT_RX_PAUSE_QUANTA7 (STAT_RX_PAUSE_QUANTA7_out), + .STAT_RX_PAUSE_QUANTA8 (STAT_RX_PAUSE_QUANTA8_out), + .STAT_RX_PAUSE_REQ (STAT_RX_PAUSE_REQ_out), + .STAT_RX_PAUSE_VALID (STAT_RX_PAUSE_VALID_out), + .STAT_RX_RECEIVED_LOCAL_FAULT (STAT_RX_RECEIVED_LOCAL_FAULT_out), + .STAT_RX_REMOTE_FAULT (STAT_RX_REMOTE_FAULT_out), + .STAT_RX_RSFEC_AM_LOCK0 (STAT_RX_RSFEC_AM_LOCK0_out), + .STAT_RX_RSFEC_AM_LOCK1 (STAT_RX_RSFEC_AM_LOCK1_out), + .STAT_RX_RSFEC_AM_LOCK2 (STAT_RX_RSFEC_AM_LOCK2_out), + .STAT_RX_RSFEC_AM_LOCK3 (STAT_RX_RSFEC_AM_LOCK3_out), + .STAT_RX_RSFEC_CORRECTED_CW_INC (STAT_RX_RSFEC_CORRECTED_CW_INC_out), + .STAT_RX_RSFEC_CW_INC (STAT_RX_RSFEC_CW_INC_out), + .STAT_RX_RSFEC_ERR_COUNT0_INC (STAT_RX_RSFEC_ERR_COUNT0_INC_out), + .STAT_RX_RSFEC_ERR_COUNT1_INC (STAT_RX_RSFEC_ERR_COUNT1_INC_out), + .STAT_RX_RSFEC_ERR_COUNT2_INC (STAT_RX_RSFEC_ERR_COUNT2_INC_out), + .STAT_RX_RSFEC_ERR_COUNT3_INC (STAT_RX_RSFEC_ERR_COUNT3_INC_out), + .STAT_RX_RSFEC_HI_SER (STAT_RX_RSFEC_HI_SER_out), + .STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS (STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS_out), + .STAT_RX_RSFEC_LANE_FILL_0 (STAT_RX_RSFEC_LANE_FILL_0_out), + .STAT_RX_RSFEC_LANE_FILL_1 (STAT_RX_RSFEC_LANE_FILL_1_out), + .STAT_RX_RSFEC_LANE_FILL_2 (STAT_RX_RSFEC_LANE_FILL_2_out), + .STAT_RX_RSFEC_LANE_FILL_3 (STAT_RX_RSFEC_LANE_FILL_3_out), + .STAT_RX_RSFEC_LANE_MAPPING (STAT_RX_RSFEC_LANE_MAPPING_out), + .STAT_RX_RSFEC_RSVD (STAT_RX_RSFEC_RSVD_out), + .STAT_RX_RSFEC_UNCORRECTED_CW_INC (STAT_RX_RSFEC_UNCORRECTED_CW_INC_out), + .STAT_RX_STATUS (STAT_RX_STATUS_out), + .STAT_RX_STOMPED_FCS (STAT_RX_STOMPED_FCS_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_TEST_PATTERN_MISMATCH (STAT_RX_TEST_PATTERN_MISMATCH_out), + .STAT_RX_TOOLONG (STAT_RX_TOOLONG_out), + .STAT_RX_TOTAL_BYTES (STAT_RX_TOTAL_BYTES_out), + .STAT_RX_TOTAL_GOOD_BYTES (STAT_RX_TOTAL_GOOD_BYTES_out), + .STAT_RX_TOTAL_GOOD_PACKETS (STAT_RX_TOTAL_GOOD_PACKETS_out), + .STAT_RX_TOTAL_PACKETS (STAT_RX_TOTAL_PACKETS_out), + .STAT_RX_TRUNCATED (STAT_RX_TRUNCATED_out), + .STAT_RX_UNDERSIZE (STAT_RX_UNDERSIZE_out), + .STAT_RX_UNICAST (STAT_RX_UNICAST_out), + .STAT_RX_USER_PAUSE (STAT_RX_USER_PAUSE_out), + .STAT_RX_VLAN (STAT_RX_VLAN_out), + .STAT_RX_VL_DEMUXED (STAT_RX_VL_DEMUXED_out), + .STAT_RX_VL_NUMBER_0 (STAT_RX_VL_NUMBER_0_out), + .STAT_RX_VL_NUMBER_1 (STAT_RX_VL_NUMBER_1_out), + .STAT_RX_VL_NUMBER_10 (STAT_RX_VL_NUMBER_10_out), + .STAT_RX_VL_NUMBER_11 (STAT_RX_VL_NUMBER_11_out), + .STAT_RX_VL_NUMBER_12 (STAT_RX_VL_NUMBER_12_out), + .STAT_RX_VL_NUMBER_13 (STAT_RX_VL_NUMBER_13_out), + .STAT_RX_VL_NUMBER_14 (STAT_RX_VL_NUMBER_14_out), + .STAT_RX_VL_NUMBER_15 (STAT_RX_VL_NUMBER_15_out), + .STAT_RX_VL_NUMBER_16 (STAT_RX_VL_NUMBER_16_out), + .STAT_RX_VL_NUMBER_17 (STAT_RX_VL_NUMBER_17_out), + .STAT_RX_VL_NUMBER_18 (STAT_RX_VL_NUMBER_18_out), + .STAT_RX_VL_NUMBER_19 (STAT_RX_VL_NUMBER_19_out), + .STAT_RX_VL_NUMBER_2 (STAT_RX_VL_NUMBER_2_out), + .STAT_RX_VL_NUMBER_3 (STAT_RX_VL_NUMBER_3_out), + .STAT_RX_VL_NUMBER_4 (STAT_RX_VL_NUMBER_4_out), + .STAT_RX_VL_NUMBER_5 (STAT_RX_VL_NUMBER_5_out), + .STAT_RX_VL_NUMBER_6 (STAT_RX_VL_NUMBER_6_out), + .STAT_RX_VL_NUMBER_7 (STAT_RX_VL_NUMBER_7_out), + .STAT_RX_VL_NUMBER_8 (STAT_RX_VL_NUMBER_8_out), + .STAT_RX_VL_NUMBER_9 (STAT_RX_VL_NUMBER_9_out), + .STAT_TX_BAD_FCS (STAT_TX_BAD_FCS_out), + .STAT_TX_BROADCAST (STAT_TX_BROADCAST_out), + .STAT_TX_FRAME_ERROR (STAT_TX_FRAME_ERROR_out), + .STAT_TX_LOCAL_FAULT (STAT_TX_LOCAL_FAULT_out), + .STAT_TX_MULTICAST (STAT_TX_MULTICAST_out), + .STAT_TX_PACKET_1024_1518_BYTES (STAT_TX_PACKET_1024_1518_BYTES_out), + .STAT_TX_PACKET_128_255_BYTES (STAT_TX_PACKET_128_255_BYTES_out), + .STAT_TX_PACKET_1519_1522_BYTES (STAT_TX_PACKET_1519_1522_BYTES_out), + .STAT_TX_PACKET_1523_1548_BYTES (STAT_TX_PACKET_1523_1548_BYTES_out), + .STAT_TX_PACKET_1549_2047_BYTES (STAT_TX_PACKET_1549_2047_BYTES_out), + .STAT_TX_PACKET_2048_4095_BYTES (STAT_TX_PACKET_2048_4095_BYTES_out), + .STAT_TX_PACKET_256_511_BYTES (STAT_TX_PACKET_256_511_BYTES_out), + .STAT_TX_PACKET_4096_8191_BYTES (STAT_TX_PACKET_4096_8191_BYTES_out), + .STAT_TX_PACKET_512_1023_BYTES (STAT_TX_PACKET_512_1023_BYTES_out), + .STAT_TX_PACKET_64_BYTES (STAT_TX_PACKET_64_BYTES_out), + .STAT_TX_PACKET_65_127_BYTES (STAT_TX_PACKET_65_127_BYTES_out), + .STAT_TX_PACKET_8192_9215_BYTES (STAT_TX_PACKET_8192_9215_BYTES_out), + .STAT_TX_PACKET_LARGE (STAT_TX_PACKET_LARGE_out), + .STAT_TX_PACKET_SMALL (STAT_TX_PACKET_SMALL_out), + .STAT_TX_PAUSE (STAT_TX_PAUSE_out), + .STAT_TX_PAUSE_VALID (STAT_TX_PAUSE_VALID_out), + .STAT_TX_PTP_FIFO_READ_ERROR (STAT_TX_PTP_FIFO_READ_ERROR_out), + .STAT_TX_PTP_FIFO_WRITE_ERROR (STAT_TX_PTP_FIFO_WRITE_ERROR_out), + .STAT_TX_TOTAL_BYTES (STAT_TX_TOTAL_BYTES_out), + .STAT_TX_TOTAL_GOOD_BYTES (STAT_TX_TOTAL_GOOD_BYTES_out), + .STAT_TX_TOTAL_GOOD_PACKETS (STAT_TX_TOTAL_GOOD_PACKETS_out), + .STAT_TX_TOTAL_PACKETS (STAT_TX_TOTAL_PACKETS_out), + .STAT_TX_UNICAST (STAT_TX_UNICAST_out), + .STAT_TX_USER_PAUSE (STAT_TX_USER_PAUSE_out), + .STAT_TX_VLAN (STAT_TX_VLAN_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_PTP_PCSLANE_OUT (TX_PTP_PCSLANE_OUT_out), + .TX_PTP_TSTAMP_OUT (TX_PTP_TSTAMP_OUT_out), + .TX_PTP_TSTAMP_TAG_OUT (TX_PTP_TSTAMP_TAG_OUT_out), + .TX_PTP_TSTAMP_VALID_OUT (TX_PTP_TSTAMP_VALID_OUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_ALT_DATA0 (TX_SERDES_ALT_DATA0_out), + .TX_SERDES_ALT_DATA1 (TX_SERDES_ALT_DATA1_out), + .TX_SERDES_ALT_DATA2 (TX_SERDES_ALT_DATA2_out), + .TX_SERDES_ALT_DATA3 (TX_SERDES_ALT_DATA3_out), + .TX_SERDES_DATA0 (TX_SERDES_DATA0_out), + .TX_SERDES_DATA1 (TX_SERDES_DATA1_out), + .TX_SERDES_DATA2 (TX_SERDES_DATA2_out), + .TX_SERDES_DATA3 (TX_SERDES_DATA3_out), + .TX_SERDES_DATA4 (TX_SERDES_DATA4_out), + .TX_SERDES_DATA5 (TX_SERDES_DATA5_out), + .TX_SERDES_DATA6 (TX_SERDES_DATA6_out), + .TX_SERDES_DATA7 (TX_SERDES_DATA7_out), + .TX_SERDES_DATA8 (TX_SERDES_DATA8_out), + .TX_SERDES_DATA9 (TX_SERDES_DATA9_out), + .TX_UNFOUT (TX_UNFOUT_out), + .CSSD_CLK_STOP_EVENT (CSSD_CLK_STOP_EVENT_in), + .CSSD_RESETN (CSSD_RESETN_in), + .CTL_CAUI4_MODE (CTL_CAUI4_MODE_in), + .CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE (CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_in), + .CTL_RSFEC_IEEE_ERROR_INDICATION_MODE (CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_in), + .CTL_RX_CHECK_ETYPE_GCP (CTL_RX_CHECK_ETYPE_GCP_in), + .CTL_RX_CHECK_ETYPE_GPP (CTL_RX_CHECK_ETYPE_GPP_in), + .CTL_RX_CHECK_ETYPE_PCP (CTL_RX_CHECK_ETYPE_PCP_in), + .CTL_RX_CHECK_ETYPE_PPP (CTL_RX_CHECK_ETYPE_PPP_in), + .CTL_RX_CHECK_MCAST_GCP (CTL_RX_CHECK_MCAST_GCP_in), + .CTL_RX_CHECK_MCAST_GPP (CTL_RX_CHECK_MCAST_GPP_in), + .CTL_RX_CHECK_MCAST_PCP (CTL_RX_CHECK_MCAST_PCP_in), + .CTL_RX_CHECK_MCAST_PPP (CTL_RX_CHECK_MCAST_PPP_in), + .CTL_RX_CHECK_OPCODE_GCP (CTL_RX_CHECK_OPCODE_GCP_in), + .CTL_RX_CHECK_OPCODE_GPP (CTL_RX_CHECK_OPCODE_GPP_in), + .CTL_RX_CHECK_OPCODE_PCP (CTL_RX_CHECK_OPCODE_PCP_in), + .CTL_RX_CHECK_OPCODE_PPP (CTL_RX_CHECK_OPCODE_PPP_in), + .CTL_RX_CHECK_SA_GCP (CTL_RX_CHECK_SA_GCP_in), + .CTL_RX_CHECK_SA_GPP (CTL_RX_CHECK_SA_GPP_in), + .CTL_RX_CHECK_SA_PCP (CTL_RX_CHECK_SA_PCP_in), + .CTL_RX_CHECK_SA_PPP (CTL_RX_CHECK_SA_PPP_in), + .CTL_RX_CHECK_UCAST_GCP (CTL_RX_CHECK_UCAST_GCP_in), + .CTL_RX_CHECK_UCAST_GPP (CTL_RX_CHECK_UCAST_GPP_in), + .CTL_RX_CHECK_UCAST_PCP (CTL_RX_CHECK_UCAST_PCP_in), + .CTL_RX_CHECK_UCAST_PPP (CTL_RX_CHECK_UCAST_PPP_in), + .CTL_RX_ENABLE (CTL_RX_ENABLE_in), + .CTL_RX_ENABLE_GCP (CTL_RX_ENABLE_GCP_in), + .CTL_RX_ENABLE_GPP (CTL_RX_ENABLE_GPP_in), + .CTL_RX_ENABLE_PCP (CTL_RX_ENABLE_PCP_in), + .CTL_RX_ENABLE_PPP (CTL_RX_ENABLE_PPP_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_PAUSE_ACK (CTL_RX_PAUSE_ACK_in), + .CTL_RX_PAUSE_ENABLE (CTL_RX_PAUSE_ENABLE_in), + .CTL_RX_RSFEC_ENABLE (CTL_RX_RSFEC_ENABLE_in), + .CTL_RX_RSFEC_ENABLE_CORRECTION (CTL_RX_RSFEC_ENABLE_CORRECTION_in), + .CTL_RX_RSFEC_ENABLE_INDICATION (CTL_RX_RSFEC_ENABLE_INDICATION_in), + .CTL_RX_SYSTEMTIMERIN (CTL_RX_SYSTEMTIMERIN_in), + .CTL_RX_TEST_PATTERN (CTL_RX_TEST_PATTERN_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in), + .CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in), + .CTL_TX_PAUSE_ENABLE (CTL_TX_PAUSE_ENABLE_in), + .CTL_TX_PAUSE_QUANTA0 (CTL_TX_PAUSE_QUANTA0_in), + .CTL_TX_PAUSE_QUANTA1 (CTL_TX_PAUSE_QUANTA1_in), + .CTL_TX_PAUSE_QUANTA2 (CTL_TX_PAUSE_QUANTA2_in), + .CTL_TX_PAUSE_QUANTA3 (CTL_TX_PAUSE_QUANTA3_in), + .CTL_TX_PAUSE_QUANTA4 (CTL_TX_PAUSE_QUANTA4_in), + .CTL_TX_PAUSE_QUANTA5 (CTL_TX_PAUSE_QUANTA5_in), + .CTL_TX_PAUSE_QUANTA6 (CTL_TX_PAUSE_QUANTA6_in), + .CTL_TX_PAUSE_QUANTA7 (CTL_TX_PAUSE_QUANTA7_in), + .CTL_TX_PAUSE_QUANTA8 (CTL_TX_PAUSE_QUANTA8_in), + .CTL_TX_PAUSE_REFRESH_TIMER0 (CTL_TX_PAUSE_REFRESH_TIMER0_in), + .CTL_TX_PAUSE_REFRESH_TIMER1 (CTL_TX_PAUSE_REFRESH_TIMER1_in), + .CTL_TX_PAUSE_REFRESH_TIMER2 (CTL_TX_PAUSE_REFRESH_TIMER2_in), + .CTL_TX_PAUSE_REFRESH_TIMER3 (CTL_TX_PAUSE_REFRESH_TIMER3_in), + .CTL_TX_PAUSE_REFRESH_TIMER4 (CTL_TX_PAUSE_REFRESH_TIMER4_in), + .CTL_TX_PAUSE_REFRESH_TIMER5 (CTL_TX_PAUSE_REFRESH_TIMER5_in), + .CTL_TX_PAUSE_REFRESH_TIMER6 (CTL_TX_PAUSE_REFRESH_TIMER6_in), + .CTL_TX_PAUSE_REFRESH_TIMER7 (CTL_TX_PAUSE_REFRESH_TIMER7_in), + .CTL_TX_PAUSE_REFRESH_TIMER8 (CTL_TX_PAUSE_REFRESH_TIMER8_in), + .CTL_TX_PAUSE_REQ (CTL_TX_PAUSE_REQ_in), + .CTL_TX_PTP_VLANE_ADJUST_MODE (CTL_TX_PTP_VLANE_ADJUST_MODE_in), + .CTL_TX_RESEND_PAUSE (CTL_TX_RESEND_PAUSE_in), + .CTL_TX_RSFEC_ENABLE (CTL_TX_RSFEC_ENABLE_in), + .CTL_TX_SEND_IDLE (CTL_TX_SEND_IDLE_in), + .CTL_TX_SEND_LFI (CTL_TX_SEND_LFI_in), + .CTL_TX_SEND_RFI (CTL_TX_SEND_RFI_in), + .CTL_TX_SYSTEMTIMERIN (CTL_TX_SYSTEMTIMERIN_in), + .CTL_TX_TEST_PATTERN (CTL_TX_TEST_PATTERN_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .RSFEC_BYPASS_RX_DIN (RSFEC_BYPASS_RX_DIN_in), + .RSFEC_BYPASS_RX_DIN_CW_START (RSFEC_BYPASS_RX_DIN_CW_START_in), + .RSFEC_BYPASS_TX_DIN (RSFEC_BYPASS_TX_DIN_in), + .RSFEC_BYPASS_TX_DIN_CW_START (RSFEC_BYPASS_TX_DIN_CW_START_in), + .RX_CLK (RX_CLK_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_ALT_DATA0 (RX_SERDES_ALT_DATA0_in), + .RX_SERDES_ALT_DATA1 (RX_SERDES_ALT_DATA1_in), + .RX_SERDES_ALT_DATA2 (RX_SERDES_ALT_DATA2_in), + .RX_SERDES_ALT_DATA3 (RX_SERDES_ALT_DATA3_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA0 (RX_SERDES_DATA0_in), + .RX_SERDES_DATA1 (RX_SERDES_DATA1_in), + .RX_SERDES_DATA2 (RX_SERDES_DATA2_in), + .RX_SERDES_DATA3 (RX_SERDES_DATA3_in), + .RX_SERDES_DATA4 (RX_SERDES_DATA4_in), + .RX_SERDES_DATA5 (RX_SERDES_DATA5_in), + .RX_SERDES_DATA6 (RX_SERDES_DATA6_in), + .RX_SERDES_DATA7 (RX_SERDES_DATA7_in), + .RX_SERDES_DATA8 (RX_SERDES_DATA8_in), + .RX_SERDES_DATA9 (RX_SERDES_DATA9_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_CLK (SCAN_CLK_in), + .SCAN_EN_N (SCAN_EN_N_in), + .SCAN_IN (SCAN_IN_in), + .TEST_MODE_N (TEST_MODE_N_in), + .TEST_RESET (TEST_RESET_in), + .TX_CLK (TX_CLK_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_PREIN (TX_PREIN_in), + .TX_PTP_1588OP_IN (TX_PTP_1588OP_IN_in), + .TX_PTP_CHKSUM_OFFSET_IN (TX_PTP_CHKSUM_OFFSET_IN_in), + .TX_PTP_RXTSTAMP_IN (TX_PTP_RXTSTAMP_IN_in), + .TX_PTP_TAG_FIELD_IN (TX_PTP_TAG_FIELD_IN_in), + .TX_PTP_TSTAMP_OFFSET_IN (TX_PTP_TSTAMP_OFFSET_IN_in), + .TX_PTP_UPD_CHKSUM_IN (TX_PTP_UPD_CHKSUM_IN_in), + .TX_RESET (TX_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DRP_CLK => DRP_DO[0]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[10]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[11]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[12]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[13]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[14]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[15]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[1]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[2]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[3]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[4]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[5]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[6]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[7]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[8]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[9]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_RDY) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[100]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[101]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[102]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[103]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[104]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[105]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[106]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[107]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[108]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[109]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[10]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[110]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[111]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[112]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[113]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[114]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[115]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[116]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[117]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[118]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[119]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[11]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[120]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[121]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[122]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[123]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[124]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[125]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[126]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[127]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[128]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[129]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[12]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[130]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[131]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[132]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[133]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[134]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[135]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[136]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[137]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[138]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[139]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[13]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[140]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[141]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[142]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[143]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[144]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[145]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[146]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[147]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[148]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[149]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[14]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[150]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[151]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[152]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[153]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[154]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[155]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[156]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[157]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[158]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[159]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[15]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[160]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[161]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[162]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[163]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[164]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[165]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[166]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[167]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[168]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[169]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[16]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[170]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[171]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[172]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[173]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[174]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[175]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[176]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[177]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[178]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[179]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[17]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[180]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[181]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[182]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[183]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[184]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[185]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[186]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[187]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[188]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[189]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[18]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[190]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[191]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[192]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[193]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[194]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[195]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[196]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[197]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[198]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[199]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[19]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[200]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[201]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[202]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[203]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[204]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[205]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[206]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[207]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[208]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[209]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[20]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[210]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[211]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[212]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[213]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[214]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[215]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[216]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[217]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[218]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[219]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[21]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[220]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[221]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[222]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[223]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[224]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[225]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[226]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[227]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[228]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[229]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[22]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[230]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[231]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[232]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[233]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[234]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[235]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[236]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[237]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[238]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[239]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[23]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[240]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[241]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[242]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[243]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[244]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[245]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[246]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[247]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[248]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[249]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[24]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[250]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[251]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[252]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[253]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[254]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[255]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[256]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[257]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[258]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[259]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[25]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[260]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[261]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[262]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[263]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[264]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[265]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[266]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[267]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[268]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[269]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[26]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[270]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[271]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[272]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[273]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[274]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[275]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[276]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[277]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[278]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[279]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[27]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[280]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[281]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[282]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[283]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[284]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[285]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[286]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[287]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[288]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[289]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[28]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[290]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[291]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[292]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[293]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[294]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[295]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[296]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[297]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[298]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[299]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[29]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[300]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[301]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[302]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[303]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[304]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[305]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[306]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[307]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[308]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[309]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[30]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[310]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[311]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[312]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[313]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[314]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[315]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[316]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[317]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[318]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[319]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[31]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[320]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[321]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[322]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[323]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[324]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[325]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[326]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[327]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[328]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[329]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[32]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[33]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[34]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[35]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[36]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[37]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[38]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[39]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[40]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[41]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[42]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[43]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[44]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[45]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[46]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[47]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[48]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[49]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[50]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[51]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[52]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[53]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[54]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[55]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[56]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[57]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[58]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[59]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[5]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[60]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[61]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[62]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[63]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[64]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[65]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[66]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[67]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[68]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[69]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[6]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[70]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[71]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[72]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[73]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[74]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[75]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[76]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[77]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[78]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[79]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[7]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[80]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[81]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[82]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[83]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[84]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[85]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[86]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[87]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[88]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[89]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[8]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[90]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[91]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[92]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[93]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[94]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[95]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[96]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[97]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[98]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[99]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT[9]) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT_CW_START) = (100:100:100, 100:100:100); + (RX_CLK => RSFEC_BYPASS_RX_DOUT_VALID) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT0[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT1[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT2[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[100]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[101]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[102]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[103]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[104]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[105]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[106]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[107]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[108]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[109]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[110]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[111]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[112]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[113]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[114]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[115]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[116]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[117]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[118]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[119]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[120]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[121]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[122]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[123]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[124]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[125]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[126]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[127]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[80]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[81]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[82]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[83]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[84]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[85]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[86]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[87]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[88]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[89]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[90]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[91]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[92]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[93]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[94]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[95]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[96]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[97]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[98]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[99]) = (100:100:100, 100:100:100); + (RX_CLK => RX_DATAOUT3[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_ENAOUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_EOPOUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_ERROUT3) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_10[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_11[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_12[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_13[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_14[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_15[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_16[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_17[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_18[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_19[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_4[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_5[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_6[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_7[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_8[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_LANE_ALIGNER_FILL_9[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_MTYOUT3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_0[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_1[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_2[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_3[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_BIP8_4[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_0[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_1[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_2[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_3[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_DATA_4[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_ENA) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_LANE0) = (100:100:100, 100:100:100); + (RX_CLK => RX_OTN_VLMARKER) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PREOUT[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_PCSLANE_OUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[10]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[11]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[12]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[13]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[14]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[15]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[16]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[17]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[18]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[19]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[20]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[21]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[22]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[23]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[24]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[25]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[26]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[27]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[28]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[29]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[30]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[31]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[32]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[33]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[34]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[35]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[36]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[37]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[38]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[39]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[40]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[41]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[42]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[43]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[44]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[45]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[46]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[47]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[48]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[49]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[50]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[51]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[52]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[53]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[54]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[55]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[56]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[57]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[58]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[59]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[60]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[61]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[62]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[63]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[64]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[65]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[66]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[67]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[68]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[69]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[70]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[71]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[72]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[73]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[74]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[75]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[76]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[77]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[78]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[79]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[8]) = (100:100:100, 100:100:100); + (RX_CLK => RX_PTP_TSTAMP_OUT[9]) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT0) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT1) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT2) = (100:100:100, 100:100:100); + (RX_CLK => RX_SOPOUT3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_ALIGNED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_ALIGNED_ERR) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_CODE[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_FCS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_PREAMBLE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BAD_SFD) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_0) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_1) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_10) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_11) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_12) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_13) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_14) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_15) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_16) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_17) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_18) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_19) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_2) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_4) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_5) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_6) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_7) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_8) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BIP_ERR_9) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BLOCK_LOCK[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_BROADCAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAGMENT[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_0) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_1) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_10) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_11) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_12) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_13) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_14) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_15) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_16) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_17) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_18) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_19) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_2) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_4) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_5) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_6) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_7) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_8) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_FRAMING_ERR_VALID_9) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_GOT_SIGNAL_OS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_HI_BER) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_INRANGEERR) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_INTERNAL_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_JABBER) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LANE0_VLM_BIP7_VALID) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_LEN_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MF_REPEAT_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MISALIGNED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_MULTICAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_OVERSIZE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1024_1518_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_128_255_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1519_1522_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1523_1548_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_1549_2047_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_2048_4095_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_256_511_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_4096_8191_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_512_1023_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_64_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_65_127_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_8192_9215_BYTES) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_BAD_FCS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_LARGE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PACKET_SMALL[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA0[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA1[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA2[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA3[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA4[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA5[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA6[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA7[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_QUANTA8[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_REQ[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_PAUSE_VALID[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RECEIVED_LOCAL_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_REMOTE_FAULT) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_AM_LOCK0) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_AM_LOCK1) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_AM_LOCK2) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_AM_LOCK3) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_CORRECTED_CW_INC) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_CW_INC) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT0_INC[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT0_INC[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT0_INC[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT1_INC[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT1_INC[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT1_INC[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT2_INC[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT2_INC[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT2_INC[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT3_INC[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT3_INC[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_ERR_COUNT3_INC[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_HI_SER) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_0[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_1[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_2[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_FILL_3[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_LANE_MAPPING[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[20]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[21]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[22]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_RSVD[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_RSFEC_UNCORRECTED_CW_INC) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STATUS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_STOMPED_FCS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_SYNCED_ERR[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOOLONG) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_BYTES[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_GOOD_PACKETS) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TOTAL_PACKETS[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_TRUNCATED) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNDERSIZE[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_UNICAST) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_USER_PAUSE) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VLAN) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[10]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[11]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[12]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[13]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[14]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[15]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[16]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[17]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[18]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[19]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[5]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[6]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[7]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[8]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_DEMUXED[9]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_0[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_10[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_11[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_12[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_13[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_14[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_15[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_16[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_17[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_18[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_19[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_1[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_2[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_3[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_4[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_5[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_6[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_7[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_8[4]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[0]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[1]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[2]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[3]) = (100:100:100, 100:100:100); + (RX_CLK => STAT_RX_VL_NUMBER_9[4]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[100]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[101]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[102]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[103]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[104]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[105]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[106]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[107]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[108]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[109]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[10]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[110]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[111]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[112]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[113]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[114]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[115]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[116]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[117]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[118]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[119]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[11]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[120]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[121]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[122]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[123]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[124]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[125]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[126]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[127]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[128]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[129]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[12]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[130]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[131]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[132]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[133]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[134]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[135]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[136]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[137]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[138]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[139]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[13]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[140]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[141]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[142]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[143]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[144]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[145]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[146]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[147]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[148]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[149]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[14]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[150]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[151]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[152]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[153]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[154]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[155]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[156]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[157]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[158]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[159]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[15]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[160]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[161]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[162]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[163]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[164]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[165]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[166]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[167]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[168]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[169]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[16]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[170]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[171]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[172]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[173]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[174]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[175]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[176]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[177]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[178]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[179]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[17]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[180]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[181]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[182]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[183]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[184]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[185]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[186]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[187]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[188]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[189]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[18]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[190]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[191]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[192]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[193]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[194]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[195]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[196]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[197]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[198]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[199]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[19]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[200]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[201]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[202]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[203]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[204]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[205]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[206]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[207]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[208]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[209]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[20]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[210]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[211]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[212]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[213]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[214]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[215]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[216]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[217]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[218]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[219]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[21]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[220]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[221]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[222]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[223]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[224]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[225]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[226]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[227]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[228]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[229]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[22]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[230]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[231]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[232]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[233]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[234]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[235]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[236]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[237]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[238]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[239]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[23]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[240]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[241]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[242]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[243]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[244]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[245]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[246]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[247]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[248]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[249]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[24]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[250]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[251]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[252]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[253]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[254]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[255]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[256]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[257]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[258]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[259]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[25]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[260]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[261]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[262]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[263]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[264]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[265]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[266]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[267]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[268]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[269]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[26]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[270]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[271]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[272]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[273]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[274]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[275]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[276]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[277]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[278]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[279]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[27]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[280]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[281]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[282]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[283]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[284]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[285]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[286]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[287]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[288]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[289]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[28]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[290]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[291]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[292]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[293]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[294]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[295]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[296]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[297]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[298]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[299]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[29]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[300]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[301]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[302]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[303]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[304]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[305]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[306]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[307]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[308]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[309]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[30]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[310]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[311]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[312]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[313]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[314]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[315]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[316]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[317]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[318]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[319]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[31]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[320]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[321]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[322]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[323]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[324]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[325]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[326]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[327]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[328]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[329]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[32]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[33]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[34]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[35]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[36]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[37]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[38]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[39]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[40]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[41]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[42]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[43]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[44]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[45]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[46]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[47]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[48]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[49]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[50]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[51]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[52]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[53]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[54]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[55]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[56]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[57]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[58]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[59]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[60]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[61]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[62]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[63]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[64]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[65]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[66]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[67]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[68]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[69]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[70]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[71]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[72]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[73]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[74]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[75]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[76]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[77]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[78]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[79]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[80]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[81]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[82]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[83]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[84]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[85]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[86]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[87]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[88]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[89]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[90]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[91]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[92]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[93]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[94]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[95]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[96]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[97]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[98]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[99]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT[9]) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT_CW_START) = (100:100:100, 100:100:100); + (TX_CLK => RSFEC_BYPASS_TX_DOUT_VALID) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_BAD_FCS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_BROADCAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_FRAME_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_LOCAL_FAULT) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_MULTICAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1024_1518_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_128_255_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1519_1522_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1523_1548_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_1549_2047_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_2048_4095_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_256_511_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_4096_8191_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_512_1023_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_64_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_65_127_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_8192_9215_BYTES) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_LARGE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PACKET_SMALL) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[6]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[7]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PAUSE_VALID[8]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PTP_FIFO_READ_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_PTP_FIFO_WRITE_ERROR) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_BYTES[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[0]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[10]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[11]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[12]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[13]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[1]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[2]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[3]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[4]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[5]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[6]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[7]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[8]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[9]) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_GOOD_PACKETS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_TOTAL_PACKETS) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_UNICAST) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_USER_PAUSE) = (100:100:100, 100:100:100); + (TX_CLK => STAT_TX_VLAN) = (100:100:100, 100:100:100); + (TX_CLK => TX_OVFOUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_PCSLANE_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[64]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[65]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[66]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[67]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[68]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[69]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[70]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[71]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[72]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[73]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[74]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[75]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[76]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[77]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[78]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[79]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_OUT[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_TAG_OUT[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_PTP_TSTAMP_VALID_OUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_RDYOUT) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA0[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA1[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA2[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_ALT_DATA3[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA0[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA1[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA2[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[32]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[33]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[34]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[35]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[36]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[37]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[38]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[39]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[40]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[41]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[42]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[43]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[44]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[45]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[46]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[47]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[48]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[49]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[50]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[51]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[52]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[53]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[54]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[55]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[56]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[57]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[58]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[59]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[60]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[61]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[62]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[63]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA3[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA4[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA5[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA6[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA7[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA8[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[10]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[11]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[12]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[13]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[14]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[15]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[16]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[17]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[18]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[19]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[20]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[21]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[22]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[23]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[24]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[25]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[26]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[27]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[28]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[29]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[30]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[31]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_SERDES_DATA9[9]) = (100:100:100, 100:100:100); + (TX_CLK => TX_UNFOUT) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge DRP_CLK, 0:0:0, notifier); + $period (negedge RX_CLK, 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (negedge TX_CLK, 0:0:0, notifier); + $period (posedge DRP_CLK, 0:0:0, notifier); + $period (posedge RX_CLK, 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (posedge TX_CLK, 0:0:0, notifier); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_CLK_delay); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_CLK_delay); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_CLK_delay); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (negedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, TX_CLK_delay); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_CLK_delay); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_CLK_delay); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_CLK, 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_CLK_delay); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (posedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, TX_CLK_delay); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, posedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge RX_CLK, negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PCP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PPP_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge RX_CLK, negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_RSFEC_ENABLE_CORRECTION, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_CORRECTION_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_RSFEC_ENABLE_INDICATION, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_INDICATION_delay); + $setuphold (posedge RX_CLK, negedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_TEST_PATTERN_delay); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[0]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[100], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[100]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[101], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[101]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[102], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[102]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[103], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[103]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[104], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[104]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[105], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[105]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[106], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[106]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[107], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[107]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[108], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[108]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[109], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[109]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[10], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[10]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[110], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[110]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[111], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[111]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[112], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[112]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[113], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[113]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[114], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[114]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[115], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[115]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[116], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[116]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[117], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[117]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[118], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[118]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[119], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[119]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[11], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[11]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[120], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[120]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[121], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[121]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[122], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[122]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[123], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[123]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[124], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[124]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[125], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[125]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[126], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[126]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[127], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[127]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[128], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[128]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[129], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[129]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[12], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[12]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[130], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[130]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[131], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[131]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[132], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[132]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[133], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[133]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[134], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[134]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[135], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[135]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[136], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[136]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[137], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[137]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[138], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[138]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[139], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[139]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[13], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[13]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[140], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[140]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[141], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[141]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[142], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[142]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[143], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[143]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[144], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[144]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[145], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[145]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[146], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[146]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[147], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[147]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[148], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[148]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[149], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[149]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[14], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[14]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[150], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[150]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[151], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[151]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[152], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[152]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[153], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[153]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[154], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[154]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[155], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[155]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[156], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[156]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[157], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[157]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[158], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[158]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[159], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[159]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[15], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[15]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[160], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[160]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[161], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[161]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[162], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[162]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[163], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[163]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[164], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[164]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[165], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[165]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[166], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[166]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[167], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[167]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[168], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[168]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[169], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[169]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[16], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[16]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[170], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[170]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[171], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[171]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[172], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[172]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[173], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[173]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[174], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[174]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[175], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[175]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[176], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[176]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[177], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[177]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[178], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[178]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[179], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[179]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[17], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[17]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[180], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[180]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[181], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[181]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[182], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[182]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[183], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[183]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[184], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[184]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[185], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[185]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[186], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[186]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[187], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[187]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[188], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[188]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[189], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[189]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[18], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[18]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[190], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[190]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[191], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[191]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[192], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[192]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[193], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[193]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[194], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[194]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[195], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[195]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[196], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[196]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[197], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[197]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[198], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[198]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[199], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[199]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[19], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[19]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[1]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[200], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[200]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[201], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[201]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[202], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[202]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[203], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[203]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[204], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[204]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[205], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[205]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[206], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[206]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[207], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[207]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[208], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[208]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[209], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[209]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[20], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[20]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[210], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[210]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[211], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[211]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[212], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[212]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[213], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[213]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[214], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[214]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[215], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[215]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[216], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[216]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[217], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[217]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[218], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[218]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[219], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[219]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[21], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[21]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[220], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[220]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[221], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[221]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[222], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[222]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[223], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[223]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[224], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[224]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[225], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[225]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[226], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[226]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[227], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[227]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[228], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[228]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[229], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[229]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[22], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[22]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[230], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[230]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[231], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[231]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[232], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[232]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[233], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[233]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[234], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[234]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[235], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[235]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[236], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[236]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[237], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[237]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[238], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[238]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[239], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[239]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[23], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[23]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[240], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[240]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[241], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[241]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[242], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[242]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[243], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[243]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[244], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[244]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[245], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[245]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[246], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[246]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[247], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[247]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[248], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[248]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[249], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[249]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[24], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[24]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[250], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[250]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[251], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[251]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[252], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[252]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[253], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[253]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[254], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[254]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[255], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[255]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[256], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[256]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[257], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[257]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[258], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[258]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[259], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[259]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[25], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[25]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[260], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[260]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[261], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[261]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[262], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[262]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[263], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[263]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[264], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[264]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[265], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[265]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[266], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[266]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[267], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[267]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[268], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[268]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[269], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[269]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[26], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[26]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[270], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[270]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[271], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[271]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[272], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[272]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[273], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[273]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[274], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[274]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[275], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[275]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[276], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[276]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[277], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[277]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[278], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[278]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[279], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[279]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[27], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[27]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[280], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[280]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[281], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[281]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[282], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[282]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[283], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[283]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[284], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[284]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[285], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[285]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[286], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[286]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[287], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[287]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[288], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[288]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[289], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[289]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[28], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[28]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[290], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[290]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[291], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[291]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[292], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[292]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[293], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[293]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[294], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[294]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[295], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[295]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[296], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[296]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[297], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[297]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[298], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[298]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[299], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[299]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[29], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[29]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[2]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[300], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[300]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[301], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[301]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[302], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[302]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[303], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[303]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[304], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[304]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[305], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[305]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[306], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[306]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[307], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[307]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[308], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[308]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[309], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[309]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[30], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[30]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[310], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[310]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[311], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[311]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[312], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[312]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[313], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[313]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[314], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[314]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[315], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[315]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[316], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[316]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[317], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[317]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[318], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[318]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[319], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[319]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[31], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[31]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[320], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[320]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[321], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[321]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[322], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[322]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[323], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[323]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[324], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[324]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[325], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[325]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[326], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[326]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[327], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[327]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[328], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[328]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[329], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[329]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[32], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[32]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[33], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[33]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[34], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[34]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[35], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[35]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[36], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[36]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[37], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[37]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[38], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[38]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[39], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[39]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[3]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[40], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[40]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[41], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[41]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[42], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[42]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[43], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[43]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[44], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[44]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[45], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[45]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[46], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[46]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[47], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[47]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[48], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[48]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[49], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[49]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[4]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[50], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[50]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[51], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[51]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[52], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[52]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[53], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[53]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[54], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[54]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[55], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[55]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[56], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[56]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[57], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[57]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[58], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[58]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[59], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[59]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[5]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[60], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[60]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[61], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[61]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[62], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[62]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[63], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[63]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[64], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[64]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[65], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[65]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[66], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[66]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[67], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[67]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[68], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[68]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[69], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[69]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[6]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[70], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[70]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[71], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[71]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[72], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[72]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[73], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[73]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[74], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[74]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[75], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[75]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[76], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[76]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[77], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[77]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[78], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[78]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[79], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[79]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[7]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[80], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[80]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[81], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[81]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[82], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[82]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[83], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[83]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[84], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[84]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[85], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[85]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[86], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[86]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[87], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[87]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[88], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[88]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[89], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[89]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[8]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[90], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[90]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[91], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[91]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[92], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[92]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[93], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[93]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[94], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[94]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[95], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[95]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[96], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[96]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[97], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[97]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[98], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[98]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[99], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[99]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN[9], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[9]); + $setuphold (posedge RX_CLK, negedge RSFEC_BYPASS_RX_DIN_CW_START, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_CW_START_delay); + $setuphold (posedge RX_CLK, posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RSFEC_IEEE_ERROR_INDICATION_MODE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_GPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PCP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_ENABLE_PPP_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge RX_CLK, posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_RSFEC_ENABLE_CORRECTION, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_CORRECTION_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_RSFEC_ENABLE_INDICATION, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_RSFEC_ENABLE_INDICATION_delay); + $setuphold (posedge RX_CLK, posedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, CTL_RX_TEST_PATTERN_delay); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[0], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[0]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[100], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[100]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[101], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[101]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[102], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[102]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[103], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[103]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[104], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[104]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[105], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[105]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[106], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[106]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[107], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[107]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[108], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[108]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[109], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[109]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[10], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[10]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[110], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[110]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[111], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[111]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[112], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[112]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[113], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[113]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[114], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[114]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[115], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[115]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[116], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[116]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[117], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[117]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[118], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[118]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[119], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[119]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[11], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[11]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[120], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[120]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[121], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[121]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[122], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[122]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[123], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[123]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[124], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[124]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[125], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[125]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[126], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[126]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[127], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[127]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[128], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[128]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[129], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[129]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[12], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[12]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[130], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[130]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[131], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[131]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[132], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[132]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[133], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[133]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[134], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[134]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[135], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[135]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[136], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[136]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[137], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[137]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[138], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[138]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[139], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[139]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[13], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[13]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[140], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[140]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[141], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[141]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[142], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[142]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[143], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[143]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[144], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[144]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[145], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[145]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[146], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[146]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[147], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[147]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[148], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[148]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[149], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[149]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[14], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[14]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[150], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[150]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[151], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[151]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[152], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[152]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[153], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[153]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[154], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[154]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[155], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[155]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[156], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[156]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[157], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[157]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[158], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[158]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[159], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[159]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[15], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[15]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[160], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[160]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[161], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[161]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[162], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[162]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[163], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[163]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[164], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[164]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[165], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[165]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[166], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[166]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[167], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[167]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[168], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[168]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[169], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[169]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[16], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[16]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[170], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[170]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[171], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[171]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[172], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[172]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[173], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[173]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[174], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[174]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[175], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[175]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[176], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[176]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[177], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[177]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[178], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[178]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[179], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[179]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[17], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[17]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[180], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[180]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[181], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[181]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[182], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[182]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[183], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[183]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[184], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[184]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[185], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[185]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[186], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[186]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[187], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[187]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[188], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[188]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[189], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[189]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[18], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[18]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[190], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[190]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[191], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[191]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[192], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[192]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[193], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[193]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[194], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[194]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[195], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[195]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[196], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[196]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[197], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[197]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[198], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[198]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[199], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[199]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[19], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[19]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[1], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[1]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[200], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[200]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[201], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[201]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[202], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[202]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[203], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[203]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[204], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[204]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[205], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[205]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[206], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[206]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[207], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[207]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[208], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[208]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[209], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[209]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[20], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[20]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[210], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[210]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[211], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[211]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[212], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[212]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[213], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[213]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[214], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[214]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[215], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[215]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[216], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[216]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[217], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[217]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[218], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[218]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[219], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[219]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[21], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[21]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[220], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[220]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[221], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[221]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[222], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[222]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[223], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[223]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[224], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[224]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[225], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[225]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[226], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[226]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[227], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[227]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[228], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[228]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[229], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[229]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[22], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[22]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[230], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[230]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[231], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[231]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[232], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[232]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[233], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[233]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[234], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[234]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[235], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[235]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[236], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[236]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[237], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[237]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[238], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[238]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[239], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[239]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[23], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[23]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[240], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[240]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[241], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[241]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[242], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[242]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[243], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[243]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[244], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[244]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[245], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[245]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[246], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[246]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[247], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[247]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[248], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[248]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[249], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[249]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[24], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[24]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[250], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[250]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[251], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[251]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[252], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[252]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[253], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[253]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[254], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[254]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[255], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[255]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[256], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[256]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[257], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[257]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[258], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[258]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[259], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[259]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[25], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[25]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[260], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[260]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[261], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[261]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[262], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[262]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[263], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[263]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[264], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[264]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[265], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[265]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[266], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[266]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[267], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[267]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[268], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[268]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[269], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[269]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[26], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[26]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[270], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[270]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[271], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[271]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[272], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[272]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[273], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[273]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[274], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[274]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[275], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[275]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[276], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[276]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[277], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[277]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[278], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[278]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[279], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[279]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[27], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[27]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[280], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[280]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[281], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[281]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[282], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[282]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[283], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[283]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[284], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[284]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[285], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[285]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[286], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[286]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[287], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[287]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[288], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[288]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[289], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[289]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[28], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[28]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[290], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[290]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[291], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[291]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[292], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[292]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[293], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[293]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[294], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[294]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[295], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[295]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[296], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[296]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[297], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[297]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[298], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[298]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[299], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[299]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[29], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[29]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[2], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[2]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[300], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[300]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[301], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[301]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[302], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[302]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[303], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[303]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[304], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[304]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[305], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[305]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[306], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[306]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[307], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[307]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[308], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[308]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[309], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[309]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[30], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[30]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[310], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[310]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[311], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[311]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[312], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[312]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[313], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[313]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[314], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[314]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[315], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[315]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[316], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[316]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[317], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[317]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[318], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[318]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[319], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[319]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[31], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[31]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[320], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[320]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[321], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[321]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[322], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[322]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[323], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[323]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[324], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[324]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[325], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[325]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[326], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[326]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[327], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[327]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[328], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[328]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[329], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[329]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[32], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[32]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[33], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[33]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[34], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[34]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[35], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[35]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[36], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[36]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[37], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[37]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[38], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[38]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[39], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[39]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[3], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[3]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[40], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[40]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[41], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[41]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[42], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[42]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[43], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[43]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[44], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[44]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[45], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[45]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[46], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[46]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[47], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[47]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[48], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[48]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[49], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[49]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[4], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[4]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[50], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[50]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[51], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[51]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[52], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[52]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[53], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[53]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[54], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[54]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[55], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[55]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[56], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[56]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[57], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[57]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[58], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[58]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[59], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[59]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[5], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[5]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[60], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[60]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[61], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[61]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[62], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[62]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[63], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[63]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[64], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[64]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[65], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[65]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[66], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[66]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[67], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[67]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[68], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[68]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[69], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[69]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[6], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[6]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[70], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[70]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[71], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[71]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[72], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[72]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[73], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[73]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[74], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[74]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[75], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[75]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[76], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[76]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[77], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[77]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[78], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[78]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[79], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[79]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[7], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[7]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[80], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[80]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[81], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[81]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[82], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[82]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[83], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[83]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[84], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[84]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[85], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[85]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[86], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[86]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[87], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[87]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[88], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[88]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[89], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[89]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[8], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[8]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[90], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[90]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[91], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[91]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[92], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[92]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[93], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[93]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[94], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[94]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[95], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[95]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[96], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[96]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[97], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[97]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[98], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[98]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[99], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[99]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN[9], 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_delay[9]); + $setuphold (posedge RX_CLK, posedge RSFEC_BYPASS_RX_DIN_CW_START, 0:0:0, 0:0:0, notifier, , , RX_CLK_delay, RSFEC_BYPASS_RX_DIN_CW_START_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[1], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[2], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[3], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[4], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[5], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[6], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[7], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[8], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], negedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge RX_SERDES_CLK[9], posedge CTL_RX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], CTL_RX_RSFEC_ENABLE_delay); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge TX_CLK, negedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RSFEC_ENABLE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_IDLE_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SEND_LFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_LFI_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_RFI_delay); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge TX_CLK, negedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_TEST_PATTERN_delay); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[0]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[100]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[101]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[102]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[103]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[104]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[105]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[106]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[107]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[108]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[109]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[10]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[110]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[111]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[112]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[113]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[114]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[115]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[116]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[117]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[118]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[119]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[11]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[120]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[121]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[122]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[123]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[124]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[125]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[126]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[127]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[128], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[128]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[129], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[129]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[12]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[130], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[130]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[131], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[131]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[132], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[132]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[133], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[133]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[134], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[134]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[135], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[135]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[136], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[136]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[137], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[137]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[138], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[138]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[139], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[139]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[13]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[140], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[140]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[141], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[141]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[142], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[142]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[143], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[143]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[144], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[144]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[145], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[145]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[146], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[146]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[147], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[147]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[148], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[148]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[149], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[149]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[14]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[150], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[150]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[151], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[151]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[152], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[152]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[153], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[153]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[154], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[154]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[155], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[155]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[156], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[156]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[157], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[157]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[158], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[158]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[159], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[159]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[15]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[160], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[160]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[161], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[161]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[162], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[162]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[163], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[163]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[164], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[164]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[165], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[165]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[166], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[166]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[167], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[167]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[168], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[168]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[169], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[169]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[16]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[170], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[170]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[171], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[171]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[172], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[172]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[173], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[173]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[174], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[174]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[175], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[175]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[176], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[176]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[177], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[177]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[178], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[178]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[179], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[179]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[17]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[180], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[180]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[181], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[181]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[182], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[182]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[183], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[183]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[184], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[184]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[185], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[185]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[186], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[186]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[187], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[187]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[188], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[188]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[189], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[189]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[18]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[190], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[190]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[191], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[191]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[192], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[192]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[193], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[193]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[194], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[194]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[195], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[195]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[196], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[196]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[197], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[197]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[198], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[198]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[199], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[199]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[19]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[1]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[200], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[200]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[201], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[201]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[202], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[202]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[203], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[203]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[204], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[204]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[205], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[205]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[206], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[206]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[207], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[207]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[208], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[208]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[209], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[209]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[20]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[210], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[210]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[211], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[211]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[212], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[212]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[213], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[213]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[214], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[214]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[215], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[215]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[216], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[216]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[217], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[217]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[218], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[218]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[219], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[219]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[21]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[220], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[220]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[221], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[221]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[222], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[222]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[223], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[223]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[224], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[224]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[225], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[225]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[226], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[226]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[227], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[227]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[228], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[228]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[229], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[229]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[22]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[230], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[230]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[231], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[231]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[232], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[232]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[233], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[233]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[234], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[234]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[235], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[235]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[236], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[236]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[237], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[237]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[238], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[238]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[239], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[239]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[23]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[240], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[240]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[241], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[241]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[242], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[242]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[243], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[243]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[244], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[244]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[245], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[245]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[246], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[246]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[247], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[247]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[248], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[248]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[249], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[249]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[24]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[250], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[250]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[251], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[251]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[252], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[252]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[253], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[253]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[254], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[254]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[255], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[255]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[256], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[256]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[257], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[257]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[258], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[258]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[259], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[259]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[25]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[260], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[260]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[261], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[261]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[262], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[262]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[263], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[263]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[264], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[264]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[265], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[265]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[266], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[266]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[267], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[267]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[268], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[268]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[269], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[269]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[26]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[270], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[270]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[271], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[271]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[272], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[272]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[273], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[273]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[274], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[274]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[275], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[275]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[276], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[276]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[277], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[277]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[278], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[278]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[279], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[279]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[27]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[280], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[280]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[281], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[281]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[282], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[282]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[283], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[283]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[284], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[284]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[285], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[285]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[286], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[286]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[287], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[287]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[288], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[288]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[289], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[289]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[28]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[290], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[290]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[291], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[291]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[292], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[292]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[293], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[293]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[294], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[294]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[295], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[295]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[296], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[296]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[297], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[297]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[298], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[298]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[299], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[299]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[29]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[2]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[300], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[300]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[301], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[301]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[302], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[302]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[303], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[303]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[304], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[304]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[305], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[305]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[306], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[306]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[307], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[307]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[308], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[308]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[309], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[309]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[30]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[310], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[310]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[311], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[311]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[312], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[312]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[313], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[313]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[314], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[314]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[315], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[315]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[316], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[316]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[317], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[317]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[318], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[318]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[319], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[319]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[31]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[320], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[320]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[321], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[321]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[322], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[322]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[323], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[323]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[324], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[324]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[325], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[325]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[326], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[326]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[327], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[327]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[328], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[328]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[329], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[329]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[32]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[33]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[34]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[35]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[36]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[37]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[38]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[39]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[3]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[40]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[41]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[42]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[43]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[44]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[45]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[46]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[47]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[48]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[49]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[4]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[50]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[51]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[52]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[53]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[54]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[55]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[56]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[57]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[58]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[59]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[5]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[60]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[61]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[62]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[63]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[64]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[65]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[66]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[67]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[68]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[69]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[6]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[70]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[71]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[72]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[73]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[74]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[75]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[76]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[77]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[78]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[79]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[7]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[80]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[81]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[82]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[83]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[84]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[85]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[86]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[87]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[88]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[89]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[8]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[90]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[91]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[92]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[93]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[94]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[95]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[96]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[97]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[98]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[99]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[9]); + $setuphold (posedge TX_CLK, negedge RSFEC_BYPASS_TX_DIN_CW_START, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_CW_START_delay); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge TX_CLK, negedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PREIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[63]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, negedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge TX_CLK, negedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge TX_CLK, posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_CAUI4_MODE_delay); + $setuphold (posedge TX_CLK, posedge CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_RSFEC_ENABLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_RSFEC_ENABLE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_IDLE_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SEND_LFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_LFI_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SEND_RFI_delay); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]); + $setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]); + $setuphold (posedge TX_CLK, posedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, CTL_TX_TEST_PATTERN_delay); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[0]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[100]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[101]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[102]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[103]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[104]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[105]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[106]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[107]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[108]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[109]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[10]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[110]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[111]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[112]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[113]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[114]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[115]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[116]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[117]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[118]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[119]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[11]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[120]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[121]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[122]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[123]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[124]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[125]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[126]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[127]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[128], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[128]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[129], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[129]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[12]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[130], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[130]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[131], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[131]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[132], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[132]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[133], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[133]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[134], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[134]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[135], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[135]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[136], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[136]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[137], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[137]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[138], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[138]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[139], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[139]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[13]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[140], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[140]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[141], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[141]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[142], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[142]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[143], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[143]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[144], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[144]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[145], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[145]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[146], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[146]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[147], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[147]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[148], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[148]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[149], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[149]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[14]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[150], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[150]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[151], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[151]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[152], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[152]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[153], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[153]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[154], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[154]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[155], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[155]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[156], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[156]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[157], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[157]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[158], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[158]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[159], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[159]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[15]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[160], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[160]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[161], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[161]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[162], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[162]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[163], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[163]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[164], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[164]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[165], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[165]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[166], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[166]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[167], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[167]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[168], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[168]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[169], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[169]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[16]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[170], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[170]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[171], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[171]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[172], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[172]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[173], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[173]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[174], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[174]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[175], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[175]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[176], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[176]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[177], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[177]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[178], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[178]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[179], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[179]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[17]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[180], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[180]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[181], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[181]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[182], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[182]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[183], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[183]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[184], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[184]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[185], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[185]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[186], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[186]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[187], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[187]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[188], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[188]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[189], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[189]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[18]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[190], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[190]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[191], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[191]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[192], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[192]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[193], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[193]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[194], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[194]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[195], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[195]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[196], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[196]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[197], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[197]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[198], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[198]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[199], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[199]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[19]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[1]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[200], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[200]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[201], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[201]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[202], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[202]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[203], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[203]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[204], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[204]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[205], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[205]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[206], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[206]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[207], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[207]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[208], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[208]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[209], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[209]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[20]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[210], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[210]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[211], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[211]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[212], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[212]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[213], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[213]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[214], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[214]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[215], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[215]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[216], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[216]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[217], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[217]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[218], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[218]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[219], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[219]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[21]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[220], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[220]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[221], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[221]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[222], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[222]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[223], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[223]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[224], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[224]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[225], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[225]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[226], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[226]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[227], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[227]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[228], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[228]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[229], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[229]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[22]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[230], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[230]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[231], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[231]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[232], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[232]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[233], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[233]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[234], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[234]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[235], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[235]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[236], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[236]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[237], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[237]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[238], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[238]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[239], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[239]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[23]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[240], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[240]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[241], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[241]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[242], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[242]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[243], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[243]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[244], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[244]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[245], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[245]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[246], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[246]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[247], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[247]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[248], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[248]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[249], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[249]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[24]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[250], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[250]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[251], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[251]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[252], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[252]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[253], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[253]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[254], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[254]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[255], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[255]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[256], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[256]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[257], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[257]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[258], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[258]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[259], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[259]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[25]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[260], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[260]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[261], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[261]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[262], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[262]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[263], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[263]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[264], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[264]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[265], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[265]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[266], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[266]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[267], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[267]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[268], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[268]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[269], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[269]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[26]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[270], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[270]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[271], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[271]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[272], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[272]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[273], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[273]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[274], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[274]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[275], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[275]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[276], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[276]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[277], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[277]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[278], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[278]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[279], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[279]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[27]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[280], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[280]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[281], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[281]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[282], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[282]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[283], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[283]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[284], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[284]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[285], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[285]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[286], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[286]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[287], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[287]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[288], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[288]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[289], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[289]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[28]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[290], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[290]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[291], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[291]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[292], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[292]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[293], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[293]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[294], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[294]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[295], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[295]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[296], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[296]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[297], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[297]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[298], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[298]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[299], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[299]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[29]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[2]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[300], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[300]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[301], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[301]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[302], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[302]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[303], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[303]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[304], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[304]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[305], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[305]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[306], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[306]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[307], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[307]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[308], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[308]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[309], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[309]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[30]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[310], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[310]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[311], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[311]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[312], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[312]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[313], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[313]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[314], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[314]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[315], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[315]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[316], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[316]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[317], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[317]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[318], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[318]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[319], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[319]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[31]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[320], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[320]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[321], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[321]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[322], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[322]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[323], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[323]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[324], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[324]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[325], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[325]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[326], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[326]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[327], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[327]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[328], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[328]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[329], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[329]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[32]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[33]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[34]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[35]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[36]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[37]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[38]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[39]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[3]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[40]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[41]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[42]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[43]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[44]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[45]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[46]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[47]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[48]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[49]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[4]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[50]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[51]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[52]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[53]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[54]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[55]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[56]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[57]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[58]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[59]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[5]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[60]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[61]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[62]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[63]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[64]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[65]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[66]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[67]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[68]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[69]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[6]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[70]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[71]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[72]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[73]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[74]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[75]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[76]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[77]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[78]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[79]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[7]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[80]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[81]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[82]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[83]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[84]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[85]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[86]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[87]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[88]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[89]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[8]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[90]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[91]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[92]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[93]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[94]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[95]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[96]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[97]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[98]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[99]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_delay[9]); + $setuphold (posedge TX_CLK, posedge RSFEC_BYPASS_TX_DIN_CW_START, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, RSFEC_BYPASS_TX_DIN_CW_START_delay); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge TX_CLK, posedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PREIN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PREIN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[63], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[63]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]); + $setuphold (posedge TX_CLK, posedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge TX_CLK, posedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , TX_CLK_delay, TX_SOPIN3_delay); + $width (negedge DRP_CLK, 0:0:0, 0, notifier); + $width (negedge RX_CLK, 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (negedge TX_CLK, 0:0:0, 0, notifier); + $width (posedge DRP_CLK, 0:0:0, 0, notifier); + $width (posedge RX_CLK, 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (posedge TX_CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DCIRESET.v b/verilog/src/unisims/DCIRESET.v new file mode 100644 index 0000000..6a2958e --- /dev/null +++ b/verilog/src/unisims/DCIRESET.v @@ -0,0 +1,86 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Reset for DCI State Machine +// /___/ /\ Filename : DCIRESET.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module DCIRESET (LOCKED, RST); + + output LOCKED; + input RST; + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + time sample_rising, sample_falling; + + always @(RST) + begin + + if (RST) + sample_rising = $time; + else if (!RST) + sample_falling = $time; + + + if (sample_falling - sample_rising < 100000) + $display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0); + + if (sample_rising - sample_falling < 100000) + $display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0); + + + end // always @ (RST) + + assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1; + + +`ifdef XIL_TIMING + + specify + + (RST => LOCKED) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/DCM_ADV.v b/verilog/src/unisims/DCM_ADV.v new file mode 100644 index 0000000..096aded --- /dev/null +++ b/verilog/src/unisims/DCM_ADV.v @@ -0,0 +1,1903 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i (O.50) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Digital Clock Manager with Advanced Features +// /___/ /\ Filename : DCM_ADV.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/11/05 - Remove GSR pin; Add LOC parameter. +// 03/23/04 - Initial version. +// 04/11/05 - Add parameter DFS_OSCILLATOR_MODE to support R. +// 04/22/05 - Change DRP set clkfx M/D value effected on RST=1, not rising +// edge. (CR 206731) +// 05/11/05 - Add parameter DCM_AUTOCALIBRATION (CR 208095). +// - Add clkin alignment check control to remove the glitch when +// clkin stopped. (CR207409). +// 05/19/05 - Add initial to all clock outputs. (CR 208380). +// 05/25/05 - Seperate clock_second_pos and neg to another process due to +// wait caused unreset. Set fb_delay_found after fb_delay computed. +// (CR 208771) +// 07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465). +// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +// 12/02/05 - Add warning for un-used DRP address use. (CR 221885) +// 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) +// 01/06/06 - Remove GSR from 3 cycle check. (223099). +// 01/12/06 - Remove GSR from reset logic. (223099). +// 01/12/06 - Add rst_in to period_div and period_ps block to handle clkin frequency +// change case. (CR 221989). +// 01/26/06 - Remove $finish from DRP Warning and change invalid to unsupported +// address. (CR 224743) +// Add reset to maximum period check module (CR224287). +// 02/28/06 - Add SIM_DEVICE generic to support V5 and V4 M and D for CLKFX (BT#1003). +// Add integer and real to parameter declaration. +// 03/10/06 - Add wire declaration for lock_period_dly signal (CR 227126) +// 08/10/06 - Set PSDONE to 0 when CLKOUT_PHASE_SHIFT=FIXED (CR 227018). +// 03/07/07 - Change DRP CLKFX Multiplier to bit 15 to 8 and Divider to bit 7 to 0. +// (CR 435600). +// 04/06/07 - Enable the clock out in clock low time after reset in model +// clock_divide_by_2 (CR 437471). +// 06/04/07 - Add wire declaration for internal signals, Remove buf from unisim. +// 09/20/07 - Use 1.5 factor for clock stopped check when CLKIN divide by 2 set(CR446707). +// 11/01/07 - Add DRP DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE read/write support (CR435651) +// 12/20/07 - Add DRP CLKIN_DIVIDE_BY_2 read/write support (CR457282) +// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +// 03/11/08 - Not check clock lost when negative edge period smaller than positive edge +// period in dcm_adv_clock_lost module (CR469499). +// 03/12/08 - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +// 07/08/08 - Use clkin_div instead of period to generate lock_period_dly (CR476425) +// 10/02/08 - Reset ps_kick_off_cmd after phase shifting (CR490447) +// 03/09/11 - set period and period_fx to 0 when rst (CR595385) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine +`define CLKFX_MULTIPLY_ADDR 80 +`define CLKFX_DIVIDE_ADDR 82 +`define PHASE_SHIFT_ADDR 85 +`define PHASE_SHIFT_KICK_OFF_ADDR 17 +`define DCM_DEFAULT_STATUS_ADDR 0 +`define DFS_FREQ_MODE_ADDR 65 +`define DLL_FREQ_MODE_ADDR 81 +`define CLKIN_DIV_BY2_ADDR 68 + + +module DCM_ADV ( + CLK0, + CLK180, + CLK270, + CLK2X, + CLK2X180, + CLK90, + CLKDV, + CLKFX, + CLKFX180, + DO, + DRDY, + LOCKED, + PSDONE, + CLKFB, + CLKIN, + DADDR, + DCLK, + DEN, + DI, + DWE, + PSCLK, + PSEN, + PSINCDEC, + RST +); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; // non-simulatable +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DCM_AUTOCALIBRATION = "TRUE"; +parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; // non-simulatable +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hF0F0; // non-simulatable +parameter integer MAXPERCLKIN = 1000000; // non-modifiable simulation parameter +parameter integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter +parameter integer PHASE_SHIFT = 0; +parameter integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter +parameter integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter +parameter SIM_DEVICE ="VIRTEX4"; +parameter LOC = "UNPLACED"; +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + +localparam DFS_OSCILLATOR_MODE = "PHASE_FREQ_LOCK"; + +output CLK0; +output CLK180; +output CLK270; +output CLK2X180; +output CLK2X; +output CLK90; +output CLKDV; +output CLKFX180; +output CLKFX; +output DRDY; +output LOCKED; +output PSDONE; +output [15:0] DO; + +input CLKFB; +input CLKIN; +input DCLK; +input DEN; +input DWE; +input PSCLK; +input PSEN; +input PSINCDEC; +tri0 GSR = glbl.GSR; +input RST; +input [15:0] DI; +input [6:0] DADDR; + +reg CLK0; +reg CLK180; +reg CLK270; +reg CLK2X180; +reg CLK2X; +reg CLK90; +reg CLKDV; +reg CLKFX180; +reg CLKFX; + +wire [15:0] di_in; +wire [6:0] daddr_in; + +wire clkfb_in, clkin_in, dssen_in; +wire psclk_in, psen_in, psincdec_in, rst_in, gsr_in, rst_input ; +wire locked_out_out; +wire dwe_in, den_in, dclk_in, clkin_lost_out, clkfx_lost_out, clkfb_lost_out; +reg rst_flag; +reg clk0_out; +reg clk2x_out, clkdv_out; +reg clkfx_out, locked_out, psdone_out, ps_overflow_out; +reg clkfx_out_avg, clkfx_out_ph; +reg ps_lock; +reg drdy_out; +wire [15:0] do_out; +reg [15:0] do_out_s, do_out_drp, do_out_drp1; +reg do_stat_en; +reg [6:0] daddr_in_lat; +reg valid_daddr; + + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clkin_type_i; +wire clkin_type; +reg [2:0] ps_type; +reg [3:0] deskew_adjust_mode; +wire dfs_mode_type; +reg dfs_mode_type_i; +wire [1:0] dll_mode_type; +reg [1:0] dll_mode_type_i; +reg sim_device_type; +reg clk1x_type; +integer ps_in, ps_min, ps_max; +integer ps_in_ps, ps_in_psdrp, ps_in_curr; +integer ps_delay_ps, ps_delay_drp; +integer clkdv_cnt; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg [1:0] lock_out; +reg lock_out1_neg; +reg lock_fb, lock_ps, lock_ps_dly; +reg fb_delay_found; +reg clock_stopped; +reg clkin_chkin, clkfb_chkin; + +wire chk_enable, chk_rst; +wire clkin_div; +wire locked_out_tmp; +wire lock_period_pulse; +reg lock_period_dly; + +reg clkin_ps; +reg clkin_fb; + +time FINE_SHIFT_RANGE; +time ps_delay; +time delay_edge; +time clkin_period [2:0]; +time period, period_50, period_25, period_25_rm; +time period_div; +time period_orig; +time period_stop_ck; +time period_ps; +time clkout_delay; +time fb_delay; +time period_fx, remain_fx; +time period_fxtmp, period_fxavg; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; +time clkin_div_edge, clkin_ps_edge, clkin_edge; +time tap_delay_step; + +reg clkin_window, clkfb_window; +reg [2:0] rst_reg; +reg [12:0] numerator, denominator, gcd; +reg [23:0] i, n, d, p; + +reg first_time_locked; +reg en_status; +reg [1521:0] mem_drp; +reg drp_lock; +reg drp_lock1; +reg ps_drp_lock, ps_drp_lock_tmp, ps_drp_lock_tmp1; +integer ps_drp, ps_in_drp; +reg ps_kick_off_cmd; + +reg single_step_lock, single_step_lock_tmp, single_step_done; +integer clkfx_multiply_drp, clkfx_divide_drp; +reg [7:0] clkfx_m_reg, clkfx_d_reg; +reg [15:0] clkfx_md_reg, dfs_mode_reg, dll_mode_reg, clkin_div2_reg; +reg inc_dec; + +real clock_stopped_factor; + + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM_ADV, the simulator resolution must be set to 1ps or smaller."); + #1 $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 3.5 : divide_type = 'd7; + 4.0 : divide_type = 'd8; + 4.5 : divide_type = 'd9; + 5.0 : divide_type = 'd10; + 5.5 : divide_type = 'd11; + 6.0 : divide_type = 'd12; + 6.5 : divide_type = 'd13; + 7.0 : divide_type = 'd14; + 7.5 : divide_type = 'd15; + 8.0 : divide_type = 'd16; + 9.0 : divide_type = 'd18; + 10.0 : divide_type = 'd20; + 11.0 : divide_type = 'd22; + 12.0 : divide_type = 'd24; + 13.0 : divide_type = 'd26; + 14.0 : divide_type = 'd28; + 15.0 : divide_type = 'd30; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_ADV instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + #1 $finish; + end + endcase + +// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") +// if ((CLKFX_DIVIDE <= 0) || (4096 < CLKFX_DIVIDE)) begin +// $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 4096.", CLKFX_DIVIDE); +// $finish; +// end +// else + if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); + #1 $finish; + end + +// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") +// if ((CLKFX_MULTIPLY <= 1) || (4096 < CLKFX_MULTIPLY)) begin +// $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 4096.", CLKFX_MULTIPLY); +// $finish; +// end +// else + if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); + #1 $finish; + end + + case (CLKIN_DIVIDE_BY_2) + "FALSE" : begin + clkin_type_i = 0; + clock_stopped_factor = 2.0; + end + "TRUE" : begin + clkin_type_i = 1; + clock_stopped_factor = 1.5; + end + default : begin + $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); + #1 $finish; + end + endcase + + case (CLKOUT_PHASE_SHIFT) + "NONE" : begin + ps_in = 0 + 256; + ps_type = 3'b000; + end + "FIXED" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = -255 + 256; + ps_type = 3'b001; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 10000; + else + FINE_SHIFT_RANGE = 7000; + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + #1 $finish; + end + end + "VARIABLE_POSITIVE" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = 0 + 256; + ps_type = 3'b011; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 10000; + else + FINE_SHIFT_RANGE = 7000; + if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are 0 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not 0 ... 255.", PHASE_SHIFT); + #1 $finish; + end + end + "VARIABLE_CENTER" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = -255 + 256; + ps_type = 3'b100; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 5000; + else + FINE_SHIFT_RANGE = 3500; + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + #1 $finish; + end + end + "DIRECT" : begin + ps_in = PHASE_SHIFT; + ps_max = 1023; + ps_min = 0; + ps_type = 3'b101; + if (DCM_PERFORMANCE_MODE == "MAX_RANGE") + begin + tap_delay_step = 18; + FINE_SHIFT_RANGE = 10000; + end + else + begin + tap_delay_step = 11; + FINE_SHIFT_RANGE = 7000; + end + if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 1023)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute is 0 to 1023.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not 0 to 1023.", PHASE_SHIFT); + #1 $finish; + end + end + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_PHASE_SHIFT on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT.", CLKOUT_PHASE_SHIFT); + #1 $finish; + end + endcase + + ps_in_curr = ps_in; + ps_in_ps = ps_in; + ps_in_psdrp = ps_in; + + case (CLK_FEEDBACK) + "NONE" : begin + clkfb_type = 0; + $display("Attribute CLK_FEEDBACK is set to value NONE."); + $display("In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN"); + end + "1X" : clkfb_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK); + #1 $finish; + end + endcase + + case (DCM_PERFORMANCE_MODE) + "MAX_SPEED" : ; + "MAX_RANGE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute DCM_PERFORMANCE_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are MAX_SPEED or MAX_RANGE.", DCM_PERFORMANCE_MODE); + #1 $finish; + end + endcase + + case (DESKEW_ADJUST) + "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 0; + "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; + "0" : deskew_adjust_mode = 0; + "1" : deskew_adjust_mode = 1; + "2" : deskew_adjust_mode = 2; + "3" : deskew_adjust_mode = 3; + "4" : deskew_adjust_mode = 4; + "5" : deskew_adjust_mode = 5; + "6" : deskew_adjust_mode = 6; + "7" : deskew_adjust_mode = 7; + "8" : deskew_adjust_mode = 8; + "9" : deskew_adjust_mode = 9; + "10" : deskew_adjust_mode = 10; + "11" : deskew_adjust_mode = 11; + "12" : deskew_adjust_mode = 12; + "13" : deskew_adjust_mode = 13; + "14" : deskew_adjust_mode = 14; + "15" : deskew_adjust_mode = 15; + "16" : deskew_adjust_mode = 16; + "17" : deskew_adjust_mode = 17; + "18" : deskew_adjust_mode = 18; + "19" : deskew_adjust_mode = 19; + "20" : deskew_adjust_mode = 20; + "21" : deskew_adjust_mode = 21; + "22" : deskew_adjust_mode = 22; + "23" : deskew_adjust_mode = 23; + "24" : deskew_adjust_mode = 24; + "25" : deskew_adjust_mode = 25; + "26" : deskew_adjust_mode = 26; + "27" : deskew_adjust_mode = 27; + "28" : deskew_adjust_mode = 28; + "29" : deskew_adjust_mode = 29; + "30" : deskew_adjust_mode = 30; + "31" : deskew_adjust_mode = 31; + default : begin + $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_ADV instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); + #1 $finish; + end + endcase + + case (DFS_FREQUENCY_MODE) + "HIGH" : dfs_mode_type_i = 1; + "LOW" : dfs_mode_type_i = 0; + default : begin + $display(" Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); + #1 $finish; + end + endcase + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DLL_FREQUENCY_MODE) + "HIGH" : dll_mode_type_i = 2'b11; + "LOW" : dll_mode_type_i = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); + #1 $finish; + end + endcase + + case (FACTORY_JF) + 16'hF0F0 : ; + default : + $display("Attribute Syntax Warning : The attribute FACTORY_JF on DCM_ADV instance %m is set to %h. Legal value is F0F0.", FACTORY_JF); + endcase + + case (DUTY_CYCLE_CORRECTION) + "FALSE" : if (SIM_DEVICE=="VIRTEX4") clk1x_type = 0; else clk1x_type = 1; + "TRUE" : clk1x_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + #1 $finish; + end + endcase + + case (STARTUP_WAIT) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + #1 $finish; + end + endcase + + case (DCM_AUTOCALIBRATION) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DCM_AUTOCALIBRATION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DCM_AUTOCALIBRATION); + #1 $finish; + end + endcase + + case (SIM_DEVICE) + "VIRTEX5" : sim_device_type = 1; + "VIRTEX4" : sim_device_type = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV instance %m is set to %s. Legal values for this attribute are VIRTEX5 or VIRTEX4.", SIM_DEVICE); + #1 $finish; + end + endcase + +end + + +// +// input wire delays +// + + buf b_LOCKED (LOCKED, locked_out_out); + buf b_PSDONE (PSDONE, psdone_out); + buf b_DO0 (DO[0], do_out[0]); + buf b_DO1 (DO[1], do_out[1]); + buf b_DO2 (DO[2], do_out[2]); + buf b_DO3 (DO[3], do_out[3]); + buf b_DO4 (DO[4], do_out[4]); + buf b_DO5 (DO[5], do_out[5]); + buf b_DO6 (DO[6], do_out[6]); + buf b_DO7 (DO[7], do_out[7]); + buf b_DO8 (DO[8], do_out[8]); + buf b_DO9 (DO[9], do_out[9]); + buf b_DO10 (DO[10], do_out[10]); + buf b_DO11 (DO[11], do_out[11]); + buf b_DO12 (DO[12], do_out[12]); + buf b_DO13 (DO[13], do_out[13]); + buf b_DO14 (DO[14], do_out[14]); + buf b_DO15 (DO[15], do_out[15]); + buf b_DRDY (DRDY, drdy_out); + + buf b_CLKIN (clkin_in, CLKIN); + buf b_CLKFB (clkfb_in, CLKFB); + buf b_PSCLK (psclk_in, PSCLK); + buf b_PSEN (psen_in, PSEN); + buf b_PSINCDEC (psincdec_in, PSINCDEC); + buf b_GSR (gsr_in, GSR); + buf b_RST (rst_input, RST); + buf b_DADDR0 (daddr_in[0], DADDR[0]); + buf b_DADDR1 (daddr_in[1], DADDR[1]); + buf b_DADDR2 (daddr_in[2], DADDR[2]); + buf b_DADDR3 (daddr_in[3], DADDR[3]); + buf b_DADDR4 (daddr_in[4], DADDR[4]); + buf b_DADDR5 (daddr_in[5], DADDR[5]); + buf b_DADDR6 (daddr_in[6], DADDR[6]); + buf b_DI0 (di_in[0], DI[0]); + buf b_DI1 (di_in[1], DI[1]); + buf b_DI2 (di_in[2], DI[2]); + buf b_DI3 (di_in[3], DI[3]); + buf b_DI4 (di_in[4], DI[4]); + buf b_DI5 (di_in[5], DI[5]); + buf b_DI6 (di_in[6], DI[6]); + buf b_DI7 (di_in[7], DI[7]); + buf b_DI8 (di_in[8], DI[8]); + buf b_DI9 (di_in[9], DI[9]); + buf b_DI10 (di_in[10], DI[10]); + buf b_DI11 (di_in[11], DI[11]); + buf b_DI12 (di_in[12], DI[12]); + buf b_DI13 (di_in[13], DI[13]); + buf b_DI14 (di_in[14], DI[14]); + buf b_DI15 (di_in[15], DI[15]); + buf b_DWE (dwe_in, DWE); + buf b_DEN (den_in, DEN); + buf b_DCLK (dclk_in, DCLK); + +assign rst_in = rst_input; + +dcm_adv_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); + +dcm_adv_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); +dcm_adv_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); + +dcm_adv_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); +dcm_adv_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); +dcm_adv_clock_lost i_clkfb_lost (CLKFB, first_time_locked, clkfb_lost_out, rst_in); + + +always @(clkin_div) + clkin_ps <= #(ps_delay) clkin_div; + +always @(clkin_ps or lock_fb) + clkin_fb = clkin_ps & lock_fb; + +always @(posedge clkin_fb or posedge chk_rst) + if (chk_rst) + clkin_chkin <= 0; + else + clkin_chkin <= 1; + +always @(posedge clkfb_in or posedge chk_rst) + if (chk_rst) + clkfb_chkin <= 0; + else + clkfb_chkin <= 1; + + assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; + assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && + lock_ps ==1 && lock_fb ==1 ) ? 1 : 0; + +always @(posedge clkin_div or posedge rst_in) + if (rst_in) begin + period_div <= 0; + clkin_div_edge <= 0; + end + else + if ( clkin_div == 1) begin + clkin_div_edge <= $time; + if (($time - clkin_div_edge) <= (1.5 * period_div)) + period_div <= $time - clkin_div_edge; + else if ((period_div == 0) && (clkin_div_edge != 0)) + period_div <= $time - clkin_div_edge; + end + + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + period_ps <= 0; + clkin_ps_edge <= 0; + end + else + if (clkin_ps==1) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; + end + +always @(posedge clkin_ps) begin + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; +end + +always @(period or fb_delay) + if (fb_delay ==0) + clkout_delay = 0; + else + clkout_delay = period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_input; + rst_reg[1] <= rst_reg[0] & rst_input; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_input; +end + +reg rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +rst_flag = 0; +end + +always @(rst_input) +begin + if (rst_input) + rst_flag = 0; + + rst_tmp1 = rst_input; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); + end + end + rst_tmp2 = rst_tmp1; +end + +initial begin + CLK0 = 0; + CLK2X =0; + CLK2X180 = 0; + CLK90 = 0; + CLK180 =0; + CLK270 = 0; + CLKDV = 0; + CLKFX = 0; + CLKFX180 =0; + clk0_out = 0; + clk2x_out = 0; + clkdv_cnt = 0; + clkdv_out = 0; + clkfb_window = 0; + clkfx_out = 0; + clkfx_out_avg = 0; + clkfx_out_ph = 0; + clkin_div_edge = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + period = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_out = 2'b00; + lock_out1_neg = 0; + lock_period = 0; + lock_period_dly = 0; + lock_ps = 0; + lock_ps_dly = 0; + locked_out = 0; + period = 0; + period_div = 0; + period_fx = 0; + period_fxavg = 0; + period_orig = 0; + period_stop_ck = 0; + period_ps = 0; + delay_edge = 0; + psdone_out = 0; + ps_delay = 0; + ps_lock = 0; + inc_dec = 0; + ps_overflow_out = 0; + ps_delay_ps = 0; + ps_delay_drp = 0; + rst_reg = 3'b000; + numerator = CLKFX_MULTIPLY; + denominator = CLKFX_DIVIDE; + clkfx_multiply_drp = CLKFX_MULTIPLY; + clkfx_divide_drp = CLKFX_DIVIDE; + clkfx_m_reg = CLKFX_MULTIPLY; + clkfx_d_reg = CLKFX_DIVIDE; + clkfx_md_reg = {clkfx_m_reg, clkfx_d_reg}; + gcd = 1; + drdy_out = 0; + do_out_drp = 16'h0000; + do_out_drp1 = 16'h0000; + do_out_s = 16'h0000; + valid_daddr = 0; + + first_time_locked = 0; + en_status = 0; + drp_lock = 0; + ps_drp = 0; + ps_kick_off_cmd = 0; + single_step_lock = 0; + single_step_lock_tmp = 0; + single_step_done = 0; + ps_drp_lock = 0; + ps_drp_lock_tmp = 0; + clkin_chkin = 0; + clkfb_chkin = 0; + + dfs_mode_reg = {13'bxxxxxxxxxxxxx, dfs_mode_type_i, 2'bxx}; + dll_mode_reg = {12'bxxxxxxxxxxxx, dll_mode_type_i, 2'bxx}; + clkin_div2_reg = {5'bxxxxx, clkin_type_i, 10'bxxxxxxxxxx}; + do_stat_en = 1; +end + + + assign dfs_mode_type = dfs_mode_reg[2]; + assign dll_mode_type = dll_mode_reg[3:2]; + assign clkin_type = clkin_div2_reg[10]; +// +// phase shift parameters +// + +always @(posedge lock_period) begin + if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100)) begin + if (PHASE_SHIFT > 0) begin + if ((ps_in * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, PHASE_SHIFT * period_orig/ 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end + else if (PHASE_SHIFT < 0) begin + if ((period_orig > FINE_SHIFT_RANGE) && + ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, -(PHASE_SHIFT) * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end + end + else if (ps_type == 3'b101) begin + if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) begin + $display(" Phase shift Error : Allowed phase shift range on instance %m is between 0 to %d. ", FINE_SHIFT_RANGE / tap_delay_step); + $finish; + end + end +end + +always @(posedge lock_period_pulse or posedge rst_in or ps_delay_ps or ps_delay_drp or ps_in_ps + or ps_in_psdrp) + if (rst_in) begin + ps_delay <= 0; + ps_in_curr <= ps_in; + end + else if (lock_period_pulse) begin + if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100)) + ps_delay <= (ps_in * period_div / 256); + else if (ps_type == 3'b101) + ps_delay <= ps_in * tap_delay_step; + end + else begin + if (((ps_type == 3'b011) || (ps_type == 3'b100) ) ) + begin + ps_in_curr = ps_in_ps; + ps_delay = (ps_in_ps * period_div / 256); + end + else if ((ps_type == 3'b101) && (ps_lock==1)) + begin + ps_in_curr = ps_in_ps; + ps_delay = ps_in_ps * tap_delay_step; + end + else if ((ps_type == 3'b101) && (ps_drp_lock==1)) + begin + ps_in_curr = ps_in_psdrp; + ps_delay = ps_delay_drp; + end + end + + + + +always @(posedge psclk_in or posedge rst_in) + if (rst_in) begin + ps_in_ps <= ps_in; + ps_overflow_out <= 0; +// ps_delay_ps <= 0; + end + else begin + if ((ps_type == 3'b011) || (ps_type == 3'b100) ) begin + if (psen_in) + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else + if (psincdec_in == 1) begin + if (ps_in_ps == ps_max) + ps_overflow_out <= 1; + else if (((ps_in_ps + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_in_ps == ps_min) + ps_overflow_out <= 1; + else if ((period_orig > FINE_SHIFT_RANGE) && + (((ps_in_ps - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + if (ps_type == 3'b101) begin + if (psen_in == 1) begin + if (ps_lock == 1) begin + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "); + end + else + begin + if (psincdec_in == 1) begin + if (ps_in_curr == ps_max) + ps_overflow_out <= 1; + else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else + begin + ps_in_ps <= ps_in_curr + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_in_curr == ps_min) + ps_overflow_out <= 1; + else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else + begin + ps_in_ps <= ps_in_curr - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + end + end + if ( psdone_out == 1) + ps_lock <= 0; +end + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + single_step_lock <= 0; + ps_in_psdrp <= ps_in; + ps_delay_drp <= 0; + end + else begin + if (ps_type == 3'b101) begin + if (ps_drp_lock == 1) begin + if (inc_dec == 1) begin + if (ps_in_curr < ps_in_drp) begin + if (single_step_lock == 0) + begin + single_step_lock <= 1; + ps_in_psdrp <= ps_in_curr + 1; + ps_delay_drp <= ps_delay + tap_delay_step; + end + end + else if (ps_in_curr == ps_in_drp) + ps_drp_lock <= 0; + end + else if (inc_dec == 0) begin + if (ps_in_curr > ps_in_drp) begin + if (single_step_lock == 0) + begin + single_step_lock <= 1; + ps_in_psdrp <= ps_in_curr - 1; + ps_delay_drp <= ps_delay - tap_delay_step; + end + end + else if (ps_in_psdrp == ps_in_drp) + ps_drp_lock <= 0; + end + end + + if ( single_step_lock_tmp == 1) + single_step_lock <= 0; + + if (ps_drp_lock_tmp == 1) + ps_drp_lock <= 1; + end +end + +always @( single_step_lock or clkin_ps) +begin + @( posedge single_step_lock) + @( posedge clkin_ps) + @( posedge clkin_ps) + @( posedge clkin_ps) + single_step_lock_tmp <= 1; + @( posedge clkin_ps) + single_step_lock_tmp <= 0; +end + +always @( ps_kick_off_cmd or dclk_in or clkin_in or ps_drp_lock ) +begin + @(posedge ps_kick_off_cmd) + @( posedge dclk_in) + @( posedge dclk_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + ps_drp_lock_tmp <= 1; + @( posedge ps_drp_lock) + ps_drp_lock_tmp <= 0; +end + +always @(posedge ps_lock or negedge ps_drp_lock ) + if (ps_type != 3'b000 || ps_type != 3'b001) begin + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge psclk_in) + @(posedge psclk_in) + begin + psdone_out = 1; + @(posedge psclk_in); + psdone_out = 0; + end + end + +// +// determine clock period +// + +always @(period_orig) + period_stop_ck = period_orig * clock_stopped_factor; + + +always @(posedge clkin_div or negedge clkin_div or posedge rst_in) + if ( rst_in == 1) + begin + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_edge <= 0; + end + else + if (clkin_div == 1) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; + end + else if (clkin_div == 0) + if (lock_period == 1) begin + if (100000000 < clkin_period[0]/1000) + begin + end +// else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin + else if ((period_stop_ck <= clkin_period[0]) && (clock_stopped == 0)) begin + clkin_period[0] <= clkin_period[1]; + end + end + +// +// evaluate_clock_period process +// +always @(negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + lock_period <= 0; + clock_stopped <= 1; + period_fxtmp <= 0; + period <= 0; + period_orig <= 0; + end + else begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period_fxtmp <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 10000, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end +// else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + else if ((period_stop_ck <= clkin_period[0]) && clock_stopped == 1'b0) begin +// clkin_period[0] = clkin_period[1]; + clock_stopped <= 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped <= 1'b0; + period_fxtmp <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + end + end +end + + always @(posedge clkin_div or posedge rst_in) + if (rst_in) + lock_period_dly <= 0; + else + lock_period_dly <= lock_period; + +// assign #(period_50) lock_period_dly = lock_period; + assign lock_period_pulse = (lock_period==1 && lock_period_dly==0) ? 1 : 0; + +// +// determine clock delay +// + + +//always @(posedge lock_period or posedge rst_in) begin +always @(posedge lock_ps_dly or posedge rst_in) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found <= 0; + end + else begin + if (lock_period && clkfb_type != 0) begin + if (clkfb_type == 1) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) begin + fb_delay <= ($time - delay_edge) % period_orig; + fb_delay_found <= 1; + end + end + end + +// +// determine feedback lock +// + +always @(posedge clkfb_in or posedge rst_in) begin + if (rst_in) + clkfb_window <= 0; + else begin + #0 clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; + end +end + +always @(posedge clkin_fb or posedge rst_in) begin + if (rst_in) + clkin_window <= 0; + else begin + #0 clkin_window <= 1; + #cycle_jitter clkin_window <= 0; + end +end + +always @(posedge clkin_fb or posedge rst_in) begin + if (rst_in) + lock_clkin <= 0; + else begin + #1 + if ((clkfb_window && fb_delay_found ) || (clkin_lost_out == 1'b0 && lock_out[0]==1'b1)) + lock_clkin <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkin <= 0; + end +end + +always @(posedge clkfb_in or posedge rst_in) begin + if (rst_in) + lock_clkfb <= 0; + else begin + #1 + if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b0 && lock_out[0]==1'b1)) + lock_clkfb <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkfb <= 0; + end +end + +always @(negedge clkin_fb or posedge rst_in) begin + if (rst_in) + lock_delay <= 0; + else + lock_delay <= lock_clkin || lock_clkfb; +end + +// +// generate lock signal +// + + assign locked_out_out = (rst_flag) ? 1'bx : locked_out; + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + lock_out <= 2'b00; + locked_out <=0; + end + else begin + if (clkfb_type == 0) + lock_out[0] <= lock_period; + else + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; + end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_out1_neg <= 0; + else + lock_out1_neg <= lock_out[1]; + + +// +// generate the clk1x_out +// + +always @(period) begin + period_25 = period /4; + period_50 = 2 * period_25; +end + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk0_out <= 0; + else if (clkin_ps ==1) + if (clk1x_type==1 && lock_out[0]) begin + clk0_out <= 1; + #(period_50); + clk0_out <= 0; + end + else + clk0_out <= 1; + else if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0] ==1 && lock_out[1] == 0))) + clk0_out <= 0; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps or posedge rst_in ) + if (rst_in) + clk2x_out <= 0; + else begin + clk2x_out <= 1; + #(period_25) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period_25); + clk2x_out <= 1; + #(period_25); + clk2x_out <= 0; + end + else begin + #(period_50); + end + end + +// +// generate the clkdv_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) begin + clkdv_out <= 1'b0; + clkdv_cnt <= 0; + end + else + if (lock_out1_neg) begin + if (clkdv_cnt >= divide_type -1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < divide_type /2) + clkdv_out <= 1'b1; + else + if ( (divide_type[0] == 1'b1) && dll_mode_type == 2'b00) + clkdv_out <= #(period/4) 1'b0; + else + clkdv_out <= 1'b0; + end + +// +//determine_clkfx_divide_multiply +// +always @( rst_in or clkfx_multiply_drp or clkfx_divide_drp) +begin + if (rst_in == 1 ) begin + numerator = clkfx_multiply_drp; + denominator = clkfx_divide_drp; + end +end + +// +// generate fx output signal +// + +always @(lock_period or period_fxtmp or denominator or numerator ) + if (lock_period == 1'b1) + period_fxavg = (period_fxtmp * denominator) / (numerator * 2); + + +//always @(lock_period or period or denominator or numerator ) +always @(lock_ps or period or denominator or numerator or rst_in) + if (rst_in == 1'b1) begin + period_fx = 0; + remain_fx = 0; + end + else begin + if (lock_ps == 1'b1) begin + period_fx = (period * denominator) / (numerator * 2); + remain_fx = (period * denominator) % (numerator * 2); + end + end + +always @(clkfx_out_avg or clkfx_out_ph) + if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") + clkfx_out = clkfx_out_avg; + else + clkfx_out = clkfx_out_ph; + + +always @(locked_out or posedge rst_in or clkfx_out_avg ) + if (rst_in == 1) + clkfx_out_avg <= 0; + else if (locked_out == 1) + if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") + clkfx_out_avg <= #(period_fxavg) ~clkfx_out_avg; + +always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in) + if (rst_in == 1) + clkfx_out_ph = 0; + else if (clkin_lost_out == 1'b1 ) begin + if (locked_out == 1) + @(negedge rst_reg[2]); + end + else + if (lock_out[1] == 1 && DFS_OSCILLATOR_MODE == "PHASE_FREQ_LOCK") begin + if (lock_out[1] == 1 ) begin + clkfx_out_ph = 1'b1; + for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin + #(period_fx); + if (p < remain_fx) + #1; + clkfx_out_ph = !clkfx_out_ph; + end + if (period_fx > (period / 2)) begin + #(period_fx - (period / 2)); + end + end + end + +// +// detect_first_time_locked +// + +always @(posedge locked_out) + if (first_time_locked == 0) + first_time_locked <= 1; + +always @(ps_overflow_out or clkin_lost_out or clkfx_lost_out or + clkfb_lost_out or en_status) + if ( en_status != 1) + do_out_s[3:0] = 4'b0; + else + begin + do_out_s[0] = ps_overflow_out; + do_out_s[1] = clkin_lost_out; + do_out_s[2] = clkfx_lost_out; + do_out_s[3] = clkfb_lost_out; + end + + assign do_out = (do_stat_en == 0) ? do_out_drp1 : do_out_s; + +always @(posedge rst_in or posedge LOCKED) + if (rst_in == 1) + en_status <= 0; + else + en_status <= 1; + +// +// drp process +// + +always @(posedge dclk_in or posedge gsr_in) + if (gsr_in == 1) begin + drp_lock <= 0; + ps_in_drp <= 0; + ps_kick_off_cmd <= 0; + do_out_drp <= 16'b0; + do_out_drp1 <= 16'b0; + do_stat_en <= 1; + drdy_out <= 0; + end + else begin + valid_daddr = addr_is_valid(daddr_in); + if (DEN == 1) begin + if (drp_lock == 1) + $display(" Warning : DEN is high at DCM_ADV instance %m at time %t. Please wait for DRDY signal before next read/write operation through DRP. ", $time); + else begin + drp_lock <= 1; + + if (DWE == 0 && sim_device_type == 1 ) begin + if (daddr_in == `DCM_DEFAULT_STATUS_ADDR) + do_stat_en <= 1; + else begin + do_stat_en <= 0; + if (daddr_in == `DFS_FREQ_MODE_ADDR) + do_out_drp <= dfs_mode_reg; + else if (daddr_in == `DLL_FREQ_MODE_ADDR) + do_out_drp <= dll_mode_reg; + else if (daddr_in == `CLKFX_MULTIPLY_ADDR) + do_out_drp <= clkfx_md_reg; + else if (daddr_in == `CLKIN_DIV_BY2_ADDR) + do_out_drp <= clkin_div2_reg; + else + do_out_drp <= 16'b0; + end + end + + if (DWE == 1) begin + if (valid_daddr) begin + if (daddr_in == `CLKFX_MULTIPLY_ADDR) begin + if (sim_device_type == 1) begin + clkfx_divide_drp <= di_in[7:0] + 1; + clkfx_multiply_drp <= di_in[15:8] + 1; + clkfx_md_reg <= di_in; + end + else + clkfx_multiply_drp <= di_in[4:0] + 1; + end + else if (daddr_in == `CLKFX_DIVIDE_ADDR && sim_device_type == 0) begin + clkfx_divide_drp <= di_in[4:0] + 1; + end + else if (daddr_in == `PHASE_SHIFT_ADDR) begin + ps_drp <= di_in[10:0]; + end + else if (daddr_in == `PHASE_SHIFT_KICK_OFF_ADDR) begin + if (ps_kick_off_cmd == 0) begin + ps_kick_off_cmd <= 1; + ps_in_drp <= ps_drp; + if (ps_in < ps_drp) + inc_dec <= 1; + else if (ps_in > ps_drp) + inc_dec <= 0; + end + end + else if (daddr_in == `DFS_FREQ_MODE_ADDR && sim_device_type == 1) begin + dfs_mode_reg <= di_in; + end + else if (daddr_in == `DLL_FREQ_MODE_ADDR && sim_device_type == 1) begin + dll_mode_reg <= di_in; + end + else if (daddr_in == `CLKIN_DIV_BY2_ADDR && sim_device_type == 1) begin + clkin_div2_reg <= di_in; + end + else + $display(" Warning : Address DADDR=%b is unsupported at DCM_ADV instance %m at time %t. ", daddr_in, $time); + + end + end + end + end + + if ( drp_lock == 1) + drp_lock1 <= 1; + + if ( drp_lock1 == 1) begin + drp_lock <= 0; + drp_lock1 <= 0; + drdy_out <= 1; + do_out_drp1 <= do_out_drp; + do_out_drp <= 16'b0; + end + + if (drdy_out == 1) begin + drdy_out <= 0; + do_out_drp1 <= 16'b0; + end + if (ps_drp_lock_tmp1 == 1) begin + if (ps_kick_off_cmd == 1) + ps_kick_off_cmd <= 0; + end + end + + always @(negedge ps_drp_lock) begin + @(posedge dclk_in) + ps_drp_lock_tmp1 <= 1; + @(posedge dclk_in) + ps_drp_lock_tmp1 <= 0; + end + +function addr_is_valid; +input [6:0] daddr_funcin; +begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) + addr_is_valid = 0; +end +endfunction + +// end process drp; + +// +// drive_drdy_out process +// + +//always @(drp_lock or dclk_in or gsr_in) +// @(negedge drp_lock) +// @(posedge dclk_in) begin +// if (gsr_in == 0) +// drdy_out = 1; +// @(posedge dclk_in) +// drdy_out = 0; +// end + +// +// generate all output signal +// + +always @(rst_in) +if (rst_in) begin + assign CLK0 = 0; + assign CLK90 = 0; + assign CLK180 = 0; + assign CLK270 = 0; + assign CLK2X = 0; + assign CLK2X180 =0; + assign CLKDV = 0; + assign CLKFX = 0; + assign CLKFX180 = 0; +end +else begin + deassign CLK0; + deassign CLK90; + deassign CLK180; + deassign CLK270; + deassign CLK2X; + deassign CLK2X180; + deassign CLKDV; + deassign CLKFX; + deassign CLKFX180; +end + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out; + CLK90 <= #(clkout_delay + period / 4) clk0_out; + CLK180 <= #(clkout_delay + period / 2) clk0_out; + CLK270 <= #(clkout_delay + period / 4) ~clk0_out; + end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out; + CLK2X180 <= #(clkout_delay) ~clk2x_out ; +end + + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out; + +always @(clkfx_out ) + CLKFX <= #(clkout_delay) clkfx_out; + +always @( clkfx_out or first_time_locked or locked_out) begin + if ( ~first_time_locked) + CLKFX180 <= 0; + else + CLKFX180 <= #(clkout_delay) ~clkfx_out; +end + +specify + (CLKIN => LOCKED) = (100:100:100, 100:100:100); + (DCLK => DO[0]) = (100:100:100, 100:100:100); + (DCLK => DO[10]) = (100:100:100, 100:100:100); + (DCLK => DO[11]) = (100:100:100, 100:100:100); + (DCLK => DO[12]) = (100:100:100, 100:100:100); + (DCLK => DO[13]) = (100:100:100, 100:100:100); + (DCLK => DO[14]) = (100:100:100, 100:100:100); + (DCLK => DO[15]) = (100:100:100, 100:100:100); + (DCLK => DO[1]) = (100:100:100, 100:100:100); + (DCLK => DO[2]) = (100:100:100, 100:100:100); + (DCLK => DO[3]) = (100:100:100, 100:100:100); + (DCLK => DO[4]) = (100:100:100, 100:100:100); + (DCLK => DO[5]) = (100:100:100, 100:100:100); + (DCLK => DO[6]) = (100:100:100, 100:100:100); + (DCLK => DO[7]) = (100:100:100, 100:100:100); + (DCLK => DO[8]) = (100:100:100, 100:100:100); + (DCLK => DO[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (PSCLK => PSDONE) = (100:100:100, 100:100:100); + $period (posedge CLKIN, 1111); + $period (posedge PSCLK, 1111); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0); + $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0); + $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0); + $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0); + $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0); + + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (posedge PSCLK, 0:0:0, 0, notifier); + $width (negedge PSCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +////////////////////////////////////////////////////// + +module dcm_adv_clock_divide_by_2 (clock, clock_type, clock_out, rst); +input clock; +input clock_type; +input rst; +output clock_out; + +reg clock_out; +reg clock_div2; +reg [2:0] rst_reg; +wire clk_src; + +initial begin + clock_out = 1'b0; + clock_div2 = 1'b0; +end + +always @(posedge clock) + clock_div2 <= ~clock_div2; + +always @(posedge clock) begin + rst_reg[0] <= rst; + rst_reg[1] <= rst_reg[0] & rst; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; +end + +assign clk_src = (clock_type) ? clock_div2 : clock; + +always @(clk_src or rst or rst_reg) + if (rst == 1'b0) + clock_out = clk_src; + else if (rst == 1'b1) begin + clock_out = 1'b0; + @(negedge rst_reg[2]); + if (clk_src == 1'b1) + @(negedge clk_src); + end + + +endmodule + +module dcm_adv_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock ) +begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period && rst == 0 ) begin + $display(" Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + +module dcm_adv_clock_lost (clock, enable, lost, rst); +input clock; +input enable; +input rst; +output lost; + +reg lost_r, lost_f, lost; + +time clock_edge, clock_edge_neg; +time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win; +time period_chk_win; +integer clock_low, clock_high; +integer clock_posedge, clock_negedge; +integer clock_second_pos, clock_second_neg; + +initial begin + clock_edge = 0; + clock_edge_neg = 0; + clock_high = 0; + clock_low = 0; + lost_r = 0; + lost_f = 0; + period = 0; + period_neg = 0; + period_tmp = 0; + period_tmp_win = 0; + period_neg_tmp = 0; + period_neg_tmp_win = 0; + period_chk_win = 0; + clock_posedge = 0; + clock_negedge = 0; + clock_second_pos = 0; + clock_second_neg = 0; +end + +always @(posedge clock or negedge clock or posedge rst) + if (rst) begin + clock_second_pos <= 0; + clock_second_neg <= 0; + end + else if (clock) + clock_second_pos <= 1; + else if (~clock) + clock_second_neg <= 1; + +always @(posedge clock or posedge rst) + if (rst) begin + period <= 0; + end + else begin + clock_edge <= $time; + period_tmp = $time - clock_edge; + if (period != 0 && (period_tmp <= period_tmp_win)) + period <= period_tmp; + else if (period != 0 && (period_tmp > period_tmp_win)) + period <= 0; + else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) + period <= period_tmp; + end + +always @(period) begin + period_tmp_win = 1.5 * period; + period_chk_win = (period * 9.1) / 10; +end + +always @(negedge clock or posedge rst) + if (rst) + period_neg <= 0; + else begin + clock_edge_neg <= $time; + period_neg_tmp = $time - clock_edge_neg; + if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win)) + period_neg <= period_neg_tmp; + else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win)) + period_neg <= 0; + else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1) + period_neg <= period_neg_tmp; + end + +always @(period_neg) + period_neg_tmp_win = 1.5 * period_neg; + +always @(posedge clock or posedge rst) + if (rst) + lost_r <= 0; + else + if (enable == 1 && clock_second_pos == 1) begin + #1; + if ( period != 0) + lost_r <= 0; + #(period_chk_win) + if ((clock_low != 1) && (clock_posedge != 1) && rst == 0 ) + lost_r <= 1; + end + +always @(negedge clock or posedge rst) + if (rst==1) begin + lost_f <= 0; + end + else begin + if (enable == 1 && clock_second_neg == 1) begin + if ( period != 0) + lost_f <= 0; + #(period_chk_win) + if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg)) + lost_f <= 1; + end + end + +always @( lost_r or lost_f or enable) + if (enable == 1) + lost = lost_r | lost_f; + else + lost = 0; + +always @(posedge clock or negedge clock or posedge rst) + if (rst==1) begin + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + end + else + if (clock ==1) begin + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end + else if (clock == 0) begin + clock_low <= 1; + clock_high <= 0; + clock_posedge <= 1; + clock_negedge <= 0; + end + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DCM_SP.v b/verilog/src/unisims/DCM_SP.v new file mode 100644 index 0000000..be8e048 --- /dev/null +++ b/verilog/src/unisims/DCM_SP.v @@ -0,0 +1,1367 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i (O.73) +// \ \ Description : Xilinx Function Simulation Library Component +// / / Digital Clock Manager +// /___/ /\ Filename : DCM_SP.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 02/28/06 - Initial version. +// 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). +// 06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283). +// 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). +// Give warning not support initial phase shifting for variable phase shifting. +// (CR 235216). +// 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). +// 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). +// 04/06/07 - Enable the clock out in clock low time after reset in model +// clock_divide_by_2 (CR 437471). +// 07/10/07 - Remove modulaton of ps_delay_md for none and fixed delay type (CR441155) +// 08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628). +// 01/22/08 - Add () to ps_in * period_in of ps_delay_md calculation (CR466293). +// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893) +// 03/20/08 - Not check clock lost when negative edge period smaller than positive +// edge period in dcm_sp_clock_lost module (CR469499). +// - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +// 05/13/08 - Change min input clock freq from 1.0Mhz to 0.2Mhz (CR467770) +// 07/16/08 - remove condition for lock_out[0] when 2x feedback (CR476637). +// 04/20/09 - Delay LOCKED (CR518620) +// 12/03/09 - Add STATUS[5]=CLKFX STATUS[7]=CLKIN (CR538362) +// 08/10/11 - change ps_max_range (CR618799). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + + +`timescale 1 ps / 1 ps +`celldefine + +module DCM_SP ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, + CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, + CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; // non-simulatable +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DSS_MODE = "NONE"; // non-simulatable +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; // non-simulatable +parameter integer MAXPERCLKIN = 5000000; // non-modifiable simulation parameter +parameter integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter +parameter integer PHASE_SHIFT = 0; +parameter integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter +parameter integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter +parameter STARTUP_WAIT = "FALSE"; // non-simulatable +parameter LOC = "UNPLACED"; + +localparam PS_STEP = 25; + +input CLKFB, CLKIN, DSSEN; +input PSCLK, PSEN, PSINCDEC, RST; + +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; +output [7:0] STATUS; + +reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +reg CLKDV, CLKFX, CLKFX180; + +wire clkin_lost_out, clkfx_lost_out; +wire locked_out_out; +wire clkfb_in, clkin_in, dssen_in; +wire psclk_in, psen_in, psincdec_in, rst_in; +reg clk0_out; +reg clk2x_out, clkdv_out; +reg clkfx_out, clkfx180_en; +reg rst_flag; +reg locked_out, psdone_out, ps_overflow_out, ps_lock; +reg locked_out0; +reg locked_out_dly; +reg clkfb_div, clkfb_chk, clkfb_div_en; +integer clkdv_cnt; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clkin_type; +reg [1:0] ps_type; +reg [3:0] deskew_adjust_mode; +reg dfs_mode_type; +reg dll_mode_type; +reg clk1x_type; +integer ps_in; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg first_time_locked; +reg en_status; +reg ps_overflow_out_ext; +reg clkin_lost_out_ext; +reg clkfx_lost_out_ext; +reg [1:0] lock_out; +reg lock_out1_neg; +reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp; +reg fb_delay_found; +reg clock_stopped; +reg clkin_chkin, clkfb_chkin; + +wire chk_enable, chk_rst; +wire clkin_div; +wire lock_period_pulse; +wire lock_out_fbd; +wire lock_period_dly, lock_period_dly1; + +reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag; +reg clkin_fb; + +time FINE_SHIFT_RANGE; +//time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; +integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; +integer ps_delay_last; +integer ps_acc; +time clkin_edge; +time clkin_div_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period, period_50, period_25; +integer period_int, period_int2, period_int3, period_ps_tmp; +time period_div; +integer period_orig_int; +time period_orig1; +time period_orig; +time period_ps; +time clkout_delay; +time fb_delay; +time period_fx, remain_fx; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg [2:0] rst_reg; +reg [12:0] numerator, denominator, gcd; +reg [23:0] i, n, d, p; + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller."); + #1 $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 3.5 : divide_type = 'd7; + 4.0 : divide_type = 'd8; + 4.5 : divide_type = 'd9; + 5.0 : divide_type = 'd10; + 5.5 : divide_type = 'd11; + 6.0 : divide_type = 'd12; + 6.5 : divide_type = 'd13; + 7.0 : divide_type = 'd14; + 7.5 : divide_type = 'd15; + 8.0 : divide_type = 'd16; + 9.0 : divide_type = 'd18; + 10.0 : divide_type = 'd20; + 11.0 : divide_type = 'd22; + 12.0 : divide_type = 'd24; + 13.0 : divide_type = 'd26; + 14.0 : divide_type = 'd28; + 15.0 : divide_type = 'd30; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + #1 $finish; + end + endcase + + if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); + #1 $finish; + end + + if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); + #1 $finish; + end + + case (CLKIN_DIVIDE_BY_2) + "false" : clkin_type = 0; + "FALSE" : clkin_type = 0; + "true" : clkin_type = 1; + "TRUE" : clkin_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); + #1 $finish; + end + endcase + + case (CLKOUT_PHASE_SHIFT) + "NONE" : begin + ps_in = 256; + ps_type = 2'b0; + end + "none" : begin + ps_in = 256; + ps_type = 2'b0; + end + "FIXED" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b01; + end + "fixed" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b01; + end + "VARIABLE" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b10; + end + "variable" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b10; + if (PHASE_SHIFT != 0) + $display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT); + end + default : begin + $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT); + #1 $finish; + end + endcase + + + case (CLK_FEEDBACK) + "none" : clkfb_type = 2'b00; + "NONE" : clkfb_type = 2'b00; + "1x" : clkfb_type = 2'b01; + "1X" : clkfb_type = 2'b01; + "2x" : clkfb_type = 2'b10; + "2X" : clkfb_type = 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK); + #1 $finish; + end + endcase + + case (DESKEW_ADJUST) + "source_synchronous" : deskew_adjust_mode = 8; + "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8; + "system_synchronous" : deskew_adjust_mode = 11; + "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; + "0" : deskew_adjust_mode = 0; + "1" : deskew_adjust_mode = 1; + "2" : deskew_adjust_mode = 2; + "3" : deskew_adjust_mode = 3; + "4" : deskew_adjust_mode = 4; + "5" : deskew_adjust_mode = 5; + "6" : deskew_adjust_mode = 6; + "7" : deskew_adjust_mode = 7; + "8" : deskew_adjust_mode = 8; + "9" : deskew_adjust_mode = 9; + "10" : deskew_adjust_mode = 10; + "11" : deskew_adjust_mode = 11; + "12" : deskew_adjust_mode = 12; + "13" : deskew_adjust_mode = 13; + "14" : deskew_adjust_mode = 14; + "15" : deskew_adjust_mode = 15; + default : begin + $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); + #1 $finish; + end + endcase + + case (DFS_FREQUENCY_MODE) + "high" : dfs_mode_type = 1; + "HIGH" : dfs_mode_type = 1; + "low" : dfs_mode_type = 0; + "LOW" : dfs_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); + #1 $finish; + end + endcase + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DLL_FREQUENCY_MODE) + "high" : dll_mode_type = 1; + "HIGH" : dll_mode_type = 1; + "low" : dll_mode_type = 0; + "LOW" : dll_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); + #1 $finish; + end + endcase + + if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin + $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s. CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK); + #1 $finish; + end + + case (DSS_MODE) + "none" : ; + "NONE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute is NONE.", DSS_MODE); + #1 $finish; + end + endcase + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type = 0; + "FALSE" : clk1x_type = 0; + "true" : clk1x_type = 1; + "TRUE" : clk1x_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + #1 $finish; + end + endcase + + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + #1 $finish; + end + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + #1 $finish; + end + endcase +end + +// +// fx parameters +// + +initial begin + gcd = 1; + for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin + if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0)) + gcd = i; + end + numerator = CLKFX_MULTIPLY / gcd; + denominator = CLKFX_DIVIDE / gcd; +end + +// +// input wire delays +// + +buf b_clkin (clkin_in, CLKIN); +buf b_clkfb (clkfb_in, CLKFB); +buf b_dssen (dssen_in, DSSEN); +buf b_psclk (psclk_in, PSCLK); +buf b_psen (psen_in, PSEN); +buf b_psincdec (psincdec_in, PSINCDEC); +buf b_rst (rst_in, RST); +buf b_LOCKED (LOCKED, locked_out_out); +buf b_PSDONE (PSDONE, psdone_out); +buf b_ps_overflow (STATUS[0], ps_overflow_out_ext); +buf b_clkin_lost (STATUS[1], clkin_lost_out_ext); +buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext); +buf b_sts_5 (STATUS[5], clkfx_out); +buf b_sts_7 (STATUS[7], clkin_in); + +assign STATUS[4:3] = 2'b0; +assign STATUS[6] = 1'b0; + +dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); + +dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); +dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); + +dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); +dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); + +always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out) + if (rst_in == 1 || en_status == 0) begin + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + end + else + begin + ps_overflow_out_ext = ps_overflow_out; + clkin_lost_out_ext = clkin_lost_out; + clkfx_lost_out_ext = clkfx_lost_out; + end + +always @(posedge rst_in or posedge LOCKED) + if (rst_in == 1) + en_status <= 0; + else + en_status <= 1; + + +always @(clkin_div) + clkin_ps_tmp <= #(ps_delay_md) clkin_div; + +always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win) + if (clkin_ps_mkup_win) + clkin_ps = clkin_ps_mkup; + else + clkin_ps = clkin_ps_tmp; + +always @(ps_delay_last or period_int or ps_delay) begin + period_int2 = 2 * period_int; + period_int3 = 3 * period_int; + if ((ps_delay_last >= period_int && ps_delay < period_int) || + (ps_delay_last >= period_int2 && ps_delay < period_int2) || + (ps_delay_last >= period_int3 && ps_delay < period_int3)) + clkin_ps_mkup_flag = 1; + else + clkin_ps_mkup_flag = 0; +end + +always @(posedge clkin_div or negedge clkin_div) begin + if (ps_type == 2'b10) begin + if ((ps_delay_last > 0 && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin + if (clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 1; + #1; + @(negedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 0; + end + end + else begin + clkin_ps_mkup_win <= 0; + clkin_ps_mkup <= 0; + #1; + @(posedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 1; + end + @(negedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 0; + end + end + end + else begin + clkin_ps_mkup_win <= 0; + clkin_ps_mkup <= 0; + end + ps_delay_last <= ps_delay; + end +end + +always @(clkin_ps or lock_fb) + clkin_fb = clkin_ps & lock_fb; + +always @(negedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div_en <= 0; + else + if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps) + clkfb_div_en <= 1; + +always @(posedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div <= 0; + else + if (clkfb_div_en ) + clkfb_div <= ~clkfb_div; + +always @(clkfb_in or clkfb_div ) + if (clkfb_type == 2'b10 ) + clkfb_chk = clkfb_div; + else + clkfb_chk = clkfb_in & lock_fb_dly; + +always @(posedge clkin_fb or posedge chk_rst) + if (chk_rst) + clkin_chkin <= 0; + else + clkin_chkin <= 1; + +always @(posedge clkfb_chk or posedge chk_rst) + if (chk_rst) + clkfb_chkin <= 0; + else + clkfb_chkin <= 1; + + assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; + assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && + lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0; + +always @(posedge clkin_div or posedge rst_in) + if (rst_in) begin + period_div <= 0; + clkin_div_edge <= 0; + end + else + if ( clkin_div ==1 ) begin + clkin_div_edge <= $time; + if (($time - clkin_div_edge) <= (1.5 * period_div)) + period_div <= $time - clkin_div_edge; + else if ((period_div == 0) && (clkin_div_edge != 0)) + period_div <= $time - clkin_div_edge; + end + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + period_ps <= 0; + clkin_ps_edge <= 0; + end + else + if (clkin_ps == 1 ) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; + end + +always @(posedge clkin_ps) begin + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + lock_fb_dly_tmp <= lock_fb; +end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_fb_dly <= 1'b0; + else + lock_fb_dly <= #(period * 0.75) lock_fb_dly_tmp; + + +always @(period or fb_delay or posedge rst_in) + if (rst_in) + clkout_delay = 0; + else begin + if (fb_delay == 0) + clkout_delay = 0; + else + clkout_delay = period - fb_delay; + end + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +reg rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +rst_flag = 0; +end + +always @(rst_in) +begin + if (rst_in) + rst_flag = 0; + + rst_tmp1 = rst_in; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); + end + end + rst_tmp2 = rst_tmp1; +end + +initial begin + CLK0 = 0; + CLK180 = 0; + CLK270 = 0; + CLK2X = 0; + CLK2X180 = 0; + CLK90 = 0; + CLKDV = 0; + CLKFX = 0; + CLKFX180 = 0; + clk0_out = 0; + clk2x_out = 0; + clkdv_out = 0; + clkdv_cnt = 0; + clkfb_window = 0; + clkfx_out = 0; + clkfx180_en = 0; + clkin_div_edge = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_edge = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_fb_dly = 0; + lock_out = 2'b00; + lock_out1_neg = 0; + lock_period = 0; + lock_ps = 0; + lock_ps_dly = 0; + locked_out = 0; + locked_out0 = 0; + locked_out_dly = 0; + period = 0; + period_int = 0; + period_int2 = 0; + period_int3 = 0; + period_div = 0; + period_fx = 0; + period_orig = 0; + period_orig_int = 0; + period_ps = 0; + psdone_out = 0; + ps_delay = 0; + ps_delay_md = 0; + ps_delay_init = 0; + ps_acc = 0; + ps_delay_all = 0; + ps_lock = 0; + ps_overflow_out = 0; + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + rst_reg = 3'b000; + first_time_locked = 0; + en_status = 0; + clkfb_div = 0; + clkin_chkin = 0; + clkfb_chkin = 0; + clkin_ps_mkup = 0; + clkin_ps_mkup_win = 0; + clkin_ps_mkup_flag = 0; + ps_delay_last = 0; + clkin_ps_tmp = 0; +end + +// RST less than 3 cycles, lock = x + + assign locked_out_out = (rst_flag) ? 1'bx : locked_out_dly; + + always @(locked_out) + locked_out_dly <= #clkout_delay locked_out; + +// +// detect_first_time_locked +// +always @(posedge locked_out) + if (first_time_locked == 0) + first_time_locked <= 1; + +// +// phase shift parameters +// + +always @(posedge lock_period) + ps_delay_init <= ps_in * period_orig /256; + + +always @(period) begin + period_int = period; + if (clkin_type==1) + period_ps_tmp = 2 * period; + else + period_ps_tmp = period; + + if (period_ps_tmp > 3000) begin + if (period_ps_tmp > 16667) + ps_max_range = (10 * (period_ps_tmp - 3000))/1000; + else + ps_max_range = (15 * (period_ps_tmp - 3000))/1000; + end + else + ps_max_range = 0; +end + +always @(ps_delay or rst_in or period_int or fb_delay_found) + if ( rst_in) + ps_delay_md = 0; + else if (fb_delay_found) begin + if (ps_type == 2'b10) + ps_delay_md = period_int + ps_delay % period_int; + else + ps_delay_md = period_int + (ps_in * period_int) /256; + end + +always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse) + if (rst_in) begin + ps_delay <= 0; + ps_overflow_out <= 0; + ps_acc <= 0; + end + else if (lock_period_pulse) + ps_delay <= ps_delay_init; + else begin + if (ps_type == 2'b10) + if (psen_in) begin + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else if (lock_ps) begin + if (psincdec_in == 1) begin + if (ps_acc > ps_max_range) + ps_overflow_out <= 1; + else begin + ps_delay <= ps_delay + PS_STEP; + ps_acc <= ps_acc + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_acc < -ps_max_range) + ps_overflow_out <= 1; + else begin + ps_delay <= ps_delay - PS_STEP; + ps_acc <= ps_acc - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + end + if (psdone_out) + ps_lock <= 0; + end + +always @(posedge ps_lock) begin + @(posedge clkin_ps); + @(posedge psclk_in); + @(posedge psclk_in); + @(posedge psclk_in) + psdone_out <= 1; + @(posedge psclk_in) + psdone_out <= 0; +// ps_lock <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_div or negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_edge <= 0; + end + else + if (clkin_div == 1) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; + end + else if (clkin_div == 0) + if (lock_period == 1) + if (100000000 < clkin_period[0]/1000) + begin + end + else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin + clkin_period[0] <= clkin_period[1]; + end + +always @(negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + lock_period <= 0; + clock_stopped <= 1; + end + else begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clock_stopped <= 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped <= 1'b0; + end + end +end + + assign #1 lock_period_dly1 = lock_period; + assign #(period_50) lock_period_dly = lock_period_dly1; + assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0; + +// +// determine clock delay +// + + assign lock_out_fbd = lock_out[0]; + +always @(posedge lock_out_fbd or posedge rst_in) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found <= 0; + end + else begin + if ( clkfb_type != 2'b00 && fb_delay_found == 0) begin + if (clkfb_type == 2'b01) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2'b10) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) begin + if (clkfb_type == 2'b10) begin + period_orig1 = period_orig / 2; + fb_delay <= ($time - delay_edge) % period_orig1; + end + else + fb_delay <= ($time - delay_edge) % period_orig; + + fb_delay_found <= 1; + end + end + end + +// +// determine feedback lock +// + +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + clkfb_window <= 0; + else begin + clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + clkin_window <= 0; + else begin + clkin_window <= 1; + #cycle_jitter clkin_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + lock_clkin <= 0; + else begin + #1 + if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkin <= 1; + else + if (chk_enable==1 && ps_lock == 0) + lock_clkin <= 0; + end + +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + lock_clkfb <= 0; + else begin + #1 + if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkfb <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkfb <= 0; + end + +always @(negedge clkin_fb or posedge rst_in) + if (rst_in) + lock_delay <= 0; + else + lock_delay <= lock_clkin || lock_clkfb; + +// +// generate lock signal +// + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + lock_out <= 2'b0; + locked_out <=0; + locked_out0 <=0; + end + else begin + lock_out[0] <= lock_period; + lock_out[1] <= lock_out[0]; + if (lock_fb_dly_tmp == 1) + locked_out0 <= lock_out[1]; + locked_out <= locked_out0; + end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_out1_neg <= 0; + else +// lock_out1_neg <= lock_out[1]; + lock_out1_neg <= locked_out0; + + +// +// generate the clk1x_out +// + +always @(period) begin + period_25 = period /4; + period_50 = 2 * period_25; +end + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk0_out <= 0; + else + if (clkin_ps ==1) + if (clk1x_type==1 && lock_out[0]) begin + clk0_out <= 1; + #(period_50) + clk0_out <= 0; + end + else + clk0_out <= 1; + else + if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0))) + clk0_out <= 0; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps or posedge rst_in ) + if (rst_in) + clk2x_out <= 0; + else begin + clk2x_out <= 1; + #(period_25) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period_25); + clk2x_out <= 1; + #(period_25); + clk2x_out <= 0; + end + else begin + #(period_50); + end + end + +// +// generate the clkdv_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) begin + clkdv_out <= 1'b0; + clkdv_cnt <= 0; + end + else + if (lock_out1_neg) begin + if (clkdv_cnt >= divide_type -1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < divide_type /2) + clkdv_out <= 1'b1; + else + if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0) + clkdv_out <= #(period_25) 1'b0; + else + clkdv_out <= 1'b0; + end + + +// +// generate fx output signal +// + +always @(lock_period or period or denominator or numerator) begin + if (lock_period == 1'b1) begin + period_fx = (period * denominator) / (numerator * 2); + remain_fx = (period * denominator) % (numerator * 2); + end +end + +always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in ) + if (rst_in == 1) + clkfx_out = 1'b0; + else if (clkin_lost_out == 1'b1 ) begin + if (locked_out == 1) + @(negedge rst_reg[2]); + end + else + if (locked_out0 == 1) begin + clkfx_out = 1'b1; + for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin + #(period_fx); + if (p < remain_fx) + #1; + clkfx_out = !clkfx_out; + end + if (period_fx > (period_50)) begin + #(period_fx - (period_50)); + end + end + +// +// generate all output signal +// + +always @(rst_in) +if (rst_in) begin + assign CLK0 = 0; + assign CLK90 = 0; + assign CLK180 = 0; + assign CLK270 = 0; + assign CLK2X = 0; + assign CLK2X180 =0; + assign CLKDV = 0; + assign CLKFX = 0; + assign CLKFX180 = 0; +end +else begin + deassign CLK0; + deassign CLK90; + deassign CLK180; + deassign CLK270; + deassign CLK2X; + deassign CLK2X180; + deassign CLKDV; + deassign CLKFX; + deassign CLKFX180; +end + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00); + CLK90 <= #(clkout_delay + period_25) clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00); + CLK270 <= #(clkout_delay + period_25) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); +end + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00); + +always @(clkfx_out ) + CLKFX <= #(clkout_delay) clkfx_out; + +always @( clkfx_out or first_time_locked or locked_out) + if ( ~first_time_locked) + CLKFX180 = 0; + else + CLKFX180 <= #(clkout_delay) ~clkfx_out; + +specify + (CLKIN => LOCKED) = (100:100:100, 100:100:100); + (PSCLK => PSDONE) = (100:100:100, 100:100:100); + + $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier); + $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier); + $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier); + $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier); + + $period (posedge CLKIN, 1111, notifier); + $period (posedge PSCLK, 1111, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (posedge PSCLK, 0:0:0, 0, notifier); + $width (negedge PSCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +////////////////////////////////////////////////////// + +module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst); +input clock; +input clock_type; +input rst; +output clock_out; + +reg clock_out; +reg clock_div2; +reg [2:0] rst_reg; +wire clk_src; + +initial begin + clock_out = 1'b0; + clock_div2 = 1'b0; +end + +always @(posedge clock) + clock_div2 <= ~clock_div2; + +always @(posedge clock) begin + rst_reg[0] <= rst; + rst_reg[1] <= rst_reg[0] & rst; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; +end + +assign clk_src = (clock_type) ? clock_div2 : clock; + +always @(clk_src or rst or rst_reg) + if (rst == 1'b0) + clock_out = clk_src; + else if (rst == 1'b1) begin + clock_out = 1'b0; + @(negedge rst_reg[2]); + if (clk_src == 1'b1) + @(negedge clk_src); + end + + +endmodule + +module dcm_sp_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock) begin + clock_edge <= $time; +// clock_period <= $time - clock_edge; + clock_period = $time - clock_edge; + if (clock_period > maximum_period ) begin + if (rst == 0) + $display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + +module dcm_sp_clock_lost (clock, enable, lost, rst); +input clock; +input enable; +input rst; +output lost; + +time clock_edge, clock_edge_neg; +time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win; +time period_chk_win; +integer clock_low, clock_high; +integer clock_posedge, clock_negedge; +integer clock_second_pos, clock_second_neg; +reg lost_r, lost_f, lost; + +initial begin + clock_edge = 0; + clock_edge_neg = 0; + clock_high = 0; + clock_low = 0; + lost_r = 0; + lost_f = 0; + period = 0; + period_neg = 0; + period_tmp = 0; + period_tmp_win = 0; + period_neg_tmp = 0; + period_neg_tmp_win = 0; + period_chk_win = 0; + clock_posedge = 0; + clock_negedge = 0; + clock_second_pos = 0; + clock_second_neg = 0; +end + +always @(posedge clock or posedge rst) + if (rst==1) + period <= 0; + else begin + clock_edge <= $time; + period_tmp = $time - clock_edge; + if (period != 0 && (period_tmp <= period_tmp_win)) + period <= period_tmp; + else if (period != 0 && (period_tmp > period_tmp_win)) + period <= 0; + else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) + period <= period_tmp; + end + +always @(period) begin + period_tmp_win = 1.5 * period; + period_chk_win = (period * 9.1) / 10; +end + +always @(negedge clock or posedge rst) + if (rst) + period_neg <= 0; + else begin + clock_edge_neg <= $time; + period_neg_tmp = $time - clock_edge_neg; + if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win)) + period_neg <= period_neg_tmp; + else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win)) + period_neg <= 0; + else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1) + period_neg <= period_neg_tmp; + end + +always @(period_neg) + period_neg_tmp_win = 1.5 * period_neg; + + +always @(posedge clock or posedge rst) + if (rst) + lost_r <= 0; + else + if (enable == 1 && clock_second_pos == 1) begin + #1; + if ( period != 0) + lost_r <= 0; + #(period_chk_win) + if ((clock_low != 1) && (clock_posedge != 1) && rst == 0) + lost_r <= 1; + end + +always @(posedge clock or negedge clock or posedge rst) + if (rst) begin + clock_second_pos <= 0; + clock_second_neg <= 0; + end + else if (clock) + clock_second_pos <= 1; + else if (~clock) + clock_second_neg <= 1; + +always @(negedge clock or posedge rst) + if (rst==1) begin + lost_f <= 0; + end + else begin + if (enable == 1 && clock_second_neg == 1) begin + if ( period != 0) + lost_f <= 0; + #(period_chk_win) + if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg)) + lost_f <= 1; + end + end + +always @( lost_r or lost_f or enable) +begin + if (enable == 1) + lost = lost_r | lost_f; + else + lost = 0; +end + + +always @(posedge clock or negedge clock or posedge rst) + if (rst==1) begin + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + end + else begin + if (clock ==1) begin + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end + else if (clock == 0) begin + clock_low <= 1; + clock_high <= 0; + clock_posedge <= 1; + clock_negedge <= 0; + end +end + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DIFFINBUF.v b/verilog/src/unisims/DIFFINBUF.v new file mode 100644 index 0000000..087b078 --- /dev/null +++ b/verilog/src/unisims/DIFFINBUF.v @@ -0,0 +1,252 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : DIFFINBUF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 808642 Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DIFFINBUF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DIFF_TERM = "FALSE", + parameter DQS_BIAS = "FALSE", + parameter IBUF_LOW_PWR = "TRUE", + parameter ISTANDARD = "UNUSED", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0 +)( + output O, + output O_B, + + input DIFF_IN_N, + input DIFF_IN_P, + input [3:0] OSC, + input [1:0] OSC_EN, + input VREF +); + +// define constants + localparam MODULE_NAME = "DIFFINBUF"; + +// Parameter encodings and registers + localparam DIFF_TERM_FALSE = 0; + localparam DIFF_TERM_TRUE = 1; + localparam DQS_BIAS_FALSE = 0; + localparam DQS_BIAS_TRUE = 1; + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + + reg trig_attr = 1'b0; + localparam [40:1] DIFF_TERM_REG = DIFF_TERM; + localparam [40:1] DQS_BIAS_REG = DQS_BIAS; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + + wire DIFF_TERM_BIN; + wire DQS_BIAS_BIN; + wire IBUF_LOW_PWR_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg O_B_out; + reg O_out; + + wire [1:0] OSC_EN_in; + wire [3:0] OSC_in; + +`ifdef XIL_TIMING + wire [1:0] OSC_EN_delay; + wire [3:0] OSC_delay; +`endif + + reg O_OSC_in; + reg O_B_OSC_in; + integer OSC_int = 0; + + assign O = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out; + assign O_B = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out; + +`ifdef XIL_TIMING + assign OSC_EN_in[0] = OSC_EN_delay[0]; + assign OSC_EN_in[1] = OSC_EN_delay[1]; + assign OSC_in = OSC_delay; +`else + assign OSC_EN_in[0] = OSC_EN[0]; + assign OSC_EN_in[1] = OSC_EN[1]; + assign OSC_in = OSC; +`endif + + assign DIFF_TERM_BIN = + (DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE : + (DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE : + DIFF_TERM_FALSE; + + assign DQS_BIAS_BIN = + (DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE : + (DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE : + DQS_BIAS_FALSE; + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-106] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-111] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin + $display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG); + attr_err = 1'b1; +end + + if ((attr_test == 1'b1) || + ((DQS_BIAS_REG != "FALSE") && + (DQS_BIAS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + always @ (OSC_in or OSC_EN_in) begin + OSC_int = OSC_in[2:0] * 5; + if (OSC_in[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in === 2'b11) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin + O_OSC_in <= 1'b0; + O_B_OSC_in <= 1'b1; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin + O_OSC_in <= 1'b1; + O_B_OSC_in <= 1'b0; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin + O_OSC_in <= ~O_OSC_in; + O_B_OSC_in <= ~O_B_OSC_in; + end + end + end + + initial begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin + O_OSC_in <= 1'b0; + O_B_OSC_in <= 1'b1; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin + O_OSC_in <= 1'b1; + O_B_OSC_in <= 1'b0; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin + O_OSC_in <= 1'bx; + O_B_OSC_in <= 1'bx; + end + end + + always @(DIFF_IN_P or DIFF_IN_N or DQS_BIAS_BIN) begin + if (DIFF_IN_P == 1'b1 && DIFF_IN_N == 1'b0) begin + O_out <= 1'b1; + O_B_out <= 1'b0; + end + else if (DIFF_IN_P == 1'b0 && DIFF_IN_N == 1'b1) begin + O_out <= 1'b0; + O_B_out <= 1'b1; + end + else if ((DIFF_IN_P === 1'bz || DIFF_IN_P == 1'b0) && (DIFF_IN_N === 1'bz || DIFF_IN_N == 1'b1)) begin + if (DQS_BIAS_BIN == 1'b1) begin + O_out <= 1'b0; + O_B_out <= 1'b1; + end + else begin + O_out <= 1'bx; + O_B_out <= 1'bx; + end + end else if ((DIFF_IN_P === 1'bx) || (DIFF_IN_N === 1'bx)) begin + O_out <= 1'bx; + O_B_out <= 1'bx; + end + // O_out <= DIFF_IN_P; + // O_B_out <= DIFF_IN_N; + end + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DIFF_IN_N => O) = (0:0:0, 0:0:0); + (DIFF_IN_N => O_B) = (0:0:0, 0:0:0); + (DIFF_IN_P => O) = (0:0:0, 0:0:0); + (DIFF_IN_P => O_B) = (0:0:0, 0:0:0); + (OSC *> O) = (0:0:0, 0:0:0); + (OSC *> O_B) = (0:0:0, 0:0:0); + (OSC_EN *> O) = (0:0:0, 0:0:0); + (OSC_EN *> O_B) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge OSC_EN, negedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay); + $setuphold (negedge OSC_EN, posedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DNA_PORT.v b/verilog/src/unisims/DNA_PORT.v new file mode 100644 index 0000000..f83b469 --- /dev/null +++ b/verilog/src/unisims/DNA_PORT.v @@ -0,0 +1,117 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Device DNA Data Access Port +// /___/ /\ Filename : DNA_PORT.v +// \ \ / \ Timestamp : Mon Oct 10 14:55:34 PDT 2005 +// \___\/\___\ +// +// Revision: +// 10/10/05 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 04/07/08 - CR 469973 -- Header Description fix +// 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE[56:55] +// 09/18/08 - CR 488646 -- added period check for simprim +// 10/28/08 - IR 494079 -- Shifting of dna_value is corrected to MSB first out +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/27/12 - Removed DRC warning for SIM_DNA_VALUE (CR 669726). +// 01/21/15 - Update to 7 series behavior (PR 841966). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT); + + parameter [56:0] SIM_DNA_VALUE = 57'h0; + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output DOUT; + + input CLK, DIN, READ, SHIFT; + + tri0 GSR = glbl.GSR; + + localparam MAX_DNA_BITS = 57; + localparam MSB_DNA_BITS = MAX_DNA_BITS - 1; + + reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE; + reg dout_out; + reg notifier; + + wire clk_in, din_in, gsr_in, read_in, shift_in; + + buf b_dout (DOUT, dout_out); + buf b_clk (clk_in, CLK); + buf b_din (din_in, DIN); + buf buf_gsr (gsr_in, GSR); + buf b_read (read_in, READ); + buf b_shift (shift_in, SHIFT); + + +// GSR has no effect + + always @(posedge clk_in) begin + if(read_in == 1'b1) begin + dna_val = SIM_DNA_VALUE; + dout_out = dna_val[MSB_DNA_BITS]; + end // read_in == 1'b1 + else if(read_in == 1'b0) + if(shift_in == 1'b1) begin +// IR 494079 +// dna_val = {din_in, dna_val[MSB_DNA_BITS :1]}; + dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in}; + dout_out = dna_val[MSB_DNA_BITS]; + end // shift_in == 1'b1 + end // always @ (posedge clk_in) + + + specify + + (CLK => DOUT) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + $period (posedge CLK, 0:0:0, notifier); + $setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier); + +`endif + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule // DNA_PORT + +`endcelldefine diff --git a/verilog/src/unisims/DNA_PORTE2.v b/verilog/src/unisims/DNA_PORTE2.v new file mode 100644 index 0000000..4971603 --- /dev/null +++ b/verilog/src/unisims/DNA_PORTE2.v @@ -0,0 +1,140 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2013.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : DNA_PORTE2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 06/07/13 - Initial version. +// 08/27/13 - Added timing support. +// 01/21/14 - Added missing timing (CR 767382). +// 05/28/14 - New simulation library message format. +// 10/02/14 - Fixed shift in order. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +//`celldefine + +module DNA_PORTE2 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000 +)( + output DOUT, + + input CLK, + input DIN, + input READ, + input SHIFT +); + + reg [95:0] SIM_DNA_VALUE_reg = SIM_DNA_VALUE; + + // include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "DNA_PORTE2_dr.v" + `endif + + tri0 GSR = glbl.GSR; + + localparam MAX_DNA_BITS = 96; + localparam MSB_DNA_BITS = MAX_DNA_BITS - 1; + + reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE; + reg dout_out; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + + wire clk_in; + wire din_in; + wire read_in; + wire shift_in; + wire clk_delay; + wire din_delay; + wire read_delay; + wire shift_delay; + localparam MODULE_NAME = "DNA_PORTE2"; + + assign DOUT = dout_out; + +`ifdef XIL_TIMING // inputs with timing checks + assign clk_in = clk_delay; + assign din_in = din_delay; + assign read_in = read_delay; + assign shift_in = shift_delay; +`endif // `ifdef XIL_TIMING + +`ifndef XIL_TIMING // inputs with timing checks + assign clk_in = CLK; + assign din_in = DIN; + assign read_in = READ; + assign shift_in = SHIFT; +`endif // `ifndef XIL_TIMING + + initial + if ((SIM_DNA_VALUE_reg < 96'h000000000000000000000000) || (SIM_DNA_VALUE_reg > 96'hFFFFFFFFFFFFFFFFFFFFFFFD)) begin + $display("Error: [Unisim %s-101] SIM_DNA_VALUE attribute is set to %h. Legal values for this attribute are 96'h000000000000000000000000 to 96'hFFFFFFFFFFFFFFFFFFFFFFFD. Instance: %m", MODULE_NAME, SIM_DNA_VALUE_reg); + #1 $finish; + end + + + always @(posedge clk_in) begin + if(read_in == 1'b1) begin + dna_val = SIM_DNA_VALUE_reg; + dout_out = SIM_DNA_VALUE_reg[0]; + end // read_in == 1'b1 + else if(read_in == 1'b0) + if(shift_in == 1'b1) begin + dna_val = {din_in, dna_val[MSB_DNA_BITS : 1]}; + dout_out = dna_val[0]; + end // shift_in == 1'b1 + end // always @ (posedge clk_in) + + + specify + (CLK => DOUT) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING // Simprim + $setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay); + $setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay); + $setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay); + $setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay); + $setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay); + $setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay); + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + + +endmodule + +//`endcelldefine diff --git a/verilog/src/unisims/DPHY_DIFFINBUF.v b/verilog/src/unisims/DPHY_DIFFINBUF.v new file mode 100644 index 0000000..4b37353 --- /dev/null +++ b/verilog/src/unisims/DPHY_DIFFINBUF.v @@ -0,0 +1,185 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : DPHY_DIFFINBUF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DPHY_DIFFINBUF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DIFF_TERM = "TRUE", + parameter ISTANDARD = "DEFAULT" +)( + output HSRX_O, + output LPRX_O_N, + output LPRX_O_P, + + input HSRX_DISABLE, + input I, + input IB, + input LPRX_DISABLE +); + +// define constants + localparam MODULE_NAME = "DPHY_DIFFINBUF"; + +// Parameter encodings and registers + localparam DIFF_TERM_FALSE = 1; + localparam DIFF_TERM_TRUE = 0; + localparam ISTANDARD_DEFAULT = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DPHY_DIFFINBUF_dr.v" +`else + localparam [40:1] DIFF_TERM_REG = DIFF_TERM; + localparam [56:1] ISTANDARD_REG = ISTANDARD; +`endif + + wire DIFF_TERM_BIN; + wire ISTANDARD_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire HSRX_O_out; + wire LPRX_O_N_out; + wire LPRX_O_P_out; + + wire HSRX_DISABLE_in; + wire IB_in; + wire I_in; + wire LPRX_DISABLE_in; + + assign HSRX_O = HSRX_O_out; + assign LPRX_O_N = LPRX_O_N_out; + assign LPRX_O_P = LPRX_O_P_out; + + assign HSRX_DISABLE_in = HSRX_DISABLE; + assign IB_in = IB; + assign I_in = I; + assign LPRX_DISABLE_in = LPRX_DISABLE; + + assign DIFF_TERM_BIN = + (DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE : + (DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE : + DIFF_TERM_TRUE; + + assign ISTANDARD_BIN = + (ISTANDARD_REG == "DEFAULT") ? ISTANDARD_DEFAULT : + ISTANDARD_DEFAULT; + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-103] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1; + $finish; + end +`endif + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DIFF_TERM_REG != "TRUE") && + (DIFF_TERM_REG != "FALSE"))) begin + $display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG); + attr_err = 1'b1; + end + +// no check +// if ((attr_test == 1'b1) || +// ((ISTANDARD_REG != "DEFAULT"))) begin +// $display("Error: [Unisim %s-102] ISTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, ISTANDARD_REG); +// attr_err = 1'b1; +// end + + if (attr_err == 1'b1) #1 $finish; + end + + reg o_out; + wire [1:0] lp_out; + wire lp_mode; + wire hs_mode; + wire hs_out; + reg [3*8:1] strP,strN; + + always @(*) + begin + $sformat(strP, "%v", I); + $sformat(strN, "%v", IB); + end + + assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong + + assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0; + assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0; + + assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0; + + assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0; + assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0; + + always @ (I_in or IB_in) begin + if (I_in == 1'b1 && IB_in == 1'b0) + o_out <= 1'b1; + else if (I_in == 1'b0 && IB_in == 1'b1) + o_out <= 1'b0; + else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz ) + o_out <= 1'bx; + end + +specify + (HSRX_DISABLE => HSRX_O) = (0:0:0, 0:0:0); + (I => HSRX_O) = (0:0:0, 0:0:0); + (I => LPRX_O_P) = (0:0:0, 0:0:0); + (IB => HSRX_O) = (0:0:0, 0:0:0); + (IB => LPRX_O_N) = (0:0:0, 0:0:0); + (LPRX_DISABLE => LPRX_O_N) = (0:0:0, 0:0:0); + (LPRX_DISABLE => LPRX_O_P) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP48E1.v b/verilog/src/unisims/DSP48E1.v new file mode 100644 index 0000000..38f8424 --- /dev/null +++ b/verilog/src/unisims/DSP48E1.v @@ -0,0 +1,2153 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers +// /___/ /\ Filename : DSP48E1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/21/09 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/24/13 - add optinv +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP48E1 #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter integer ACASCREG = 1, + parameter integer ADREG = 1, + parameter integer ALUMODEREG = 1, + parameter integer AREG = 1, + parameter AUTORESET_PATDET = "NO_RESET", + parameter A_INPUT = "DIRECT", + parameter integer BCASCREG = 1, + parameter integer BREG = 1, + parameter B_INPUT = "DIRECT", + parameter integer CARRYINREG = 1, + parameter integer CARRYINSELREG = 1, + parameter integer CREG = 1, + parameter integer DREG = 1, + parameter integer INMODEREG = 1, + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000, + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [4:0] IS_INMODE_INVERTED = 5'b00000, + parameter [6:0] IS_OPMODE_INVERTED = 7'b0000000, + parameter [47:0] MASK = 48'h3FFFFFFFFFFF, + parameter integer MREG = 1, + parameter integer OPMODEREG = 1, + parameter [47:0] PATTERN = 48'h000000000000, + parameter integer PREG = 1, + parameter SEL_MASK = "MASK", + parameter SEL_PATTERN = "PATTERN", + parameter USE_DPORT = "FALSE", + parameter USE_MULT = "MULTIPLY", + parameter USE_PATTERN_DETECT = "NO_PATDET", + parameter USE_SIMD = "ONE48" +)( + output [29:0] ACOUT, + output [17:0] BCOUT, + output CARRYCASCOUT, + output [3:0] CARRYOUT, + output MULTSIGNOUT, + output OVERFLOW, + output [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + + input [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + +// define constants + localparam MODULE_NAME = "DSP48E1"; + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------- + localparam MAX_ACOUT = 30; + localparam MAX_BCOUT = 18; + localparam MAX_CARRYOUT = 4; + localparam MAX_P = 48; + localparam MAX_PCOUT = 48; + + localparam MAX_A = 30; + localparam MAX_ACIN = 30; + localparam MAX_ALUMODE = 4; + localparam MAX_A_MULT = 25; + localparam MAX_B = 18; + localparam MAX_B_MULT = 18; + localparam MAX_BCIN = 18; + localparam MAX_C = 48; + localparam MAX_CARRYINSEL = 3; + localparam MAX_D = 25; + localparam MAX_INMODE = 5; + localparam MAX_OPMODE = 7; + localparam MAX_PCIN = 48; + + localparam MAX_ALU_FULL = 48; + localparam MAX_ALU_HALF = 24; + localparam MAX_ALU_QUART = 12; + + localparam MSB_ACOUT = MAX_ACOUT - 1; + localparam MSB_BCOUT = MAX_BCOUT - 1; + localparam MSB_CARRYOUT = MAX_CARRYOUT - 1; + localparam MSB_P = MAX_P - 1; + localparam MSB_PCOUT = MAX_PCOUT - 1; + + localparam MSB_A = MAX_A - 1; + localparam MSB_ACIN = MAX_ACIN - 1; + localparam MSB_ALUMODE = MAX_ALUMODE - 1; + localparam MSB_A_MULT = MAX_A_MULT - 1; + localparam MSB_B = MAX_B - 1; + localparam MSB_B_MULT = MAX_B_MULT - 1; + localparam MSB_BCIN = MAX_BCIN - 1; + localparam MSB_C = MAX_C - 1; + localparam MSB_CARRYINSEL = MAX_CARRYINSEL - 1; + localparam MSB_D = MAX_D - 1; + localparam MSB_INMODE = MAX_INMODE - 1; + localparam MSB_OPMODE = MAX_OPMODE - 1; + localparam MSB_PCIN = MAX_PCIN - 1; + + localparam MSB_ALU_FULL = MAX_ALU_FULL - 1; + localparam MSB_ALU_HALF = MAX_ALU_HALF - 1; + localparam MSB_ALU_QUART = MAX_ALU_QUART - 1; + + localparam SHIFT_MUXZ = 17; + + wire [3:0] IS_ALUMODE_INVERTED_BIN = IS_ALUMODE_INVERTED; + wire [0:0] IS_CARRYIN_INVERTED_BIN = IS_CARRYIN_INVERTED; + wire [0:0] IS_CLK_INVERTED_BIN = IS_CLK_INVERTED; + wire [4:0] IS_INMODE_INVERTED_BIN = IS_INMODE_INVERTED; + wire [6:0] IS_OPMODE_INVERTED_BIN = IS_OPMODE_INVERTED; + + reg [29:0] a_o_mux, qa_o_mux, qa_o_reg1, qa_o_reg2, qacout_o_mux; + +// new + reg [4:0] qinmode_o_mux, qinmode_o_reg; +// new + wire [24:0] a_preaddsub; + + reg [17:0] b_o_mux, qb_o_mux, qb_o_reg1, qb_o_reg2, qbcout_o_mux; + reg [2:0] qcarryinsel_o_mux, qcarryinsel_o_reg1; + +// new + reg [MSB_D:0] d_o_mux, qd_o_mux, qd_o_reg1; + + reg [(MSB_A_MULT+MSB_B_MULT+1):0] qmult_o_mux, qmult_o_reg; // 42:0 + reg [47:0] qc_o_mux, qc_o_reg1; + reg [47:0] qp_o_mux, qp_o_reg1; + reg [47:0] qx_o_mux, qy_o_mux, qz_o_mux; + reg [6:0] qopmode_o_mux, qopmode_o_reg1; + + reg notifier; + + reg qcarryin_o_mux0, qcarryin_o_reg0, qcarryin_o_mux7, qcarryin_o_reg7; + reg qcarryin_o_mux, qcarryin_o_reg; + + reg [3:0] qalumode_o_mux, qalumode_o_reg1; + + reg invalid_opmode, opmode_valid_flag, ping_opmode_drc_check = 0; + +// reg [47:0] alu_o; + wire [47:0] alu_o; + + reg qmultsignout_o_reg, multsignout_o_mux; + wire multsignout_o_opmode; + + reg [MAX_ALU_FULL:0] alu_full_tmp; + reg [MAX_ALU_HALF:0] alu_hlf1_tmp, alu_hlf2_tmp; + reg [MAX_ALU_QUART:0] alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp; + + wire pdet_o_mux, pdetb_o_mux; + + wire [47:0] the_pattern; + reg [47:0] the_mask = 0; + wire carrycascout_o; + wire the_auto_reset_patdet; + reg carrycascout_o_reg = 0; + reg carrycascout_o_mux = 0; + +// reg [3:0] carryout_o = 0; +// CR 577648 +// reg [3:0] carryout_o_reg = 0; +// reg [3:0] carryout_o_mux = 0; +// CR 588861 + reg [3:0] carryout_o_reg = 0; + reg [3:0] carryout_o_mux; + wire [3:0] carryout_x_o; + + wire pdet_o, pdetb_o; + reg pdet_o_reg1, pdet_o_reg2, pdetb_o_reg1, pdetb_o_reg2; + wire overflow_o, underflow_o; + + wire [(MSB_A_MULT+MSB_B_MULT+1):0] mult_o; +// reg [(MSB_A_MULT+MSB_B_MULT+1):0] mult_o; // 42:0 +// new + wire [MSB_A_MULT:0] ad_addsub, ad_mult; + reg [MSB_A_MULT:0] qad_o_reg1, qad_o_mux; + wire [MSB_B_MULT:0] b_mult; + + reg cci_drc_msg = 1'b0; + reg cis_drc_msg = 1'b0; + + wire [MSB_A:0] a_in; + wire [MSB_ACIN:0] acin_in; + wire [MSB_B:0] b_in; + wire [MSB_BCIN:0] bcin_in; + wire [MSB_CARRYINSEL:0] carryinsel_in; + wire [MSB_PCIN:0] pcin_in, c_in; + wire [MSB_OPMODE:0] opmode_in; + wire [MSB_ALUMODE:0] alumode_in; + wire carryin_in; + wire carrycascin_in; + wire cep_in; + wire cea1_in; + wire cea2_in; + wire cealumode_in; + wire ceb1_in; + wire ceb2_in; + wire cec_in; + wire cead_in; + wire ced_in; + wire cecarryin_in; + wire cectrl_in; + wire ceinmode_in; + wire cem_in; + wire clk_in; + wire [MSB_D:0] d_in; + wire gsr_in; + wire [MSB_INMODE:0] inmode_in; + wire multsignin_in; + wire rstp_in; + wire rsta_in; + wire rstalumode_in; + wire rstb_in; + wire rstallcarryin_in; + wire rstc_in; + wire rstctrl_in; + wire rstd_in; + wire rstinmode_in; + wire rstm_in; + + wire [MSB_A:0] a_dly; + wire [MSB_ACIN:0] acin_dly; + wire [MSB_B:0] b_dly; + wire [MSB_BCIN:0] bcin_dly; + wire [MSB_CARRYINSEL:0] carryinsel_dly; + wire [MSB_PCIN:0] pcin_dly, c_dly; + wire [MSB_OPMODE:0] opmode_dly; + wire [MSB_ALUMODE:0] alumode_dly; + wire carryin_dly; + wire carrycascin_dly; + wire cep_dly; + wire cea1_dly; + wire cea2_dly; + wire cealumode_dly; + wire ceb1_dly; + wire ceb2_dly; + wire cec_dly; + wire cead_dly; + wire ced_dly; + wire cecarryin_dly; + wire cectrl_dly; + wire ceinmode_dly; + wire cem_dly; + wire clk_dly; + wire [MSB_D:0] d_dly; + wire [MSB_INMODE:0] inmode_dly; + wire multsignin_dly; + wire rstp_dly; + wire rsta_dly; + wire rstalumode_dly; + wire rstb_dly; + wire rstallcarryin_dly; + wire rstc_dly; + wire rstctrl_dly; + wire rstd_dly; + wire rstinmode_dly; + wire rstm_dly; + +`ifdef XIL_TIMING +// wire nrsta; +// wire nrstb; +// wire nrstc; +// wire nrstp; +// wire nrstallcarryin; +// wire nrstctrl; + wire cea12_enable; + wire ceb12_enable; + wire a_en_n, a_en_p; + wire b_en_n, b_en_p; + wire c_en_n, c_en_p; + wire d_en_n, d_en_p; + wire acin_en_n, acin_en_p; + wire bcin_en_n, bcin_en_p; + wire carryin_en_n, carryin_en_p; + wire carryinsel_en_n, carryinsel_en_p; + wire opmode_en_n, opmode_en_p; + wire inmode_en_n, inmode_en_p; + wire pcin_en_n, pcin_en_p; + wire clk_en_n, clk_en_p; + wire clk_gsr_en_n, clk_gsr_en_p; + wire clk_rsta_en_n, clk_rsta_en_p; + wire clk_rstb_en_n, clk_rstb_en_p; + wire clk_rstc_en_n, clk_rstc_en_p; + wire clk_rstd_en_n, clk_rstd_en_p; + wire clk_rstm_en_n, clk_rstm_en_p; + wire clk_rstp_en_n, clk_rstp_en_p; + wire clk_rstallcarryin_en_n, clk_rstallcarryin_en_p; + wire clk_rstctrl_en_n, clk_rstctrl_en_p; + wire clk_rstinmode_en_n, clk_rstinmode_en_p; +`endif + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + buf b_acout_o[MSB_ACOUT:0] (ACOUT, qacout_o_mux); + buf b_bcout_o[MSB_BCOUT:0] (BCOUT, qbcout_o_mux); + buf b_carrycascout (CARRYCASCOUT, carrycascout_o_mux); + buf b_carryout[MSB_CARRYOUT:0] (CARRYOUT, carryout_x_o); + buf b_multsignout (MULTSIGNOUT, multsignout_o_mux); + buf b_overflow (OVERFLOW, overflow_o); + buf b_p_o[MSB_P:0] (P, qp_o_mux); + buf b_pcout_o[MSB_PCOUT:0] (PCOUT, qp_o_mux); + buf b_patterndetect (PATTERNDETECT, pdet_o_mux); + buf b_patternbdetect (PATTERNBDETECT, pdetb_o_mux); + buf b_underflow (UNDERFLOW, underflow_o); + +//----------------------------------------------------- +//----------- Inputs -------------------------------- +//----------------------------------------------------- + buf b_gsr (gsr_in, GSR); + +`ifndef XIL_TIMING + assign a_dly = A; + assign acin_dly = ACIN; + assign alumode_dly = ALUMODE; + assign b_dly = B; + assign bcin_dly = BCIN; + assign c_dly = C; + assign carrycascin_dly = CARRYCASCIN; + assign carryin_dly = CARRYIN; + assign carryinsel_dly = CARRYINSEL; + assign cea1_dly = CEA1; + assign cea2_dly = CEA2; + assign cead_dly = CEAD; + assign cealumode_dly = CEALUMODE; + assign ceb1_dly = CEB1; + assign ceb2_dly = CEB2; + assign cec_dly = CEC; + assign cecarryin_dly = CECARRYIN; + assign cectrl_dly = CECTRL; + assign ced_dly = CED; + assign ceinmode_dly = CEINMODE; + assign cem_dly = CEM; + assign cep_dly = CEP; + assign clk_dly = CLK; + assign d_dly = D; + assign inmode_dly = INMODE; + assign multsignin_dly = MULTSIGNIN; + assign opmode_dly = OPMODE; + assign pcin_dly = PCIN; + assign rsta_dly = RSTA; + assign rstallcarryin_dly = RSTALLCARRYIN; + assign rstalumode_dly = RSTALUMODE; + assign rstb_dly = RSTB; + assign rstc_dly = RSTC; + assign rstctrl_dly = RSTCTRL; + assign rstd_dly = RSTD; + assign rstinmode_dly = RSTINMODE; + assign rstm_dly = RSTM; + assign rstp_dly = RSTP; +`endif // `ifndef XIL_TIMING + + assign a_in = a_dly; + assign acin_in = acin_dly; + assign alumode_in = alumode_dly ^ IS_ALUMODE_INVERTED_BIN; + assign b_in = b_dly; + assign bcin_in = bcin_dly; + assign c_in = c_dly; + assign carrycascin_in = carrycascin_dly; + assign carryin_in = carryin_dly ^ IS_CARRYIN_INVERTED_BIN; + assign carryinsel_in = carryinsel_dly; + assign cea1_in = cea1_dly; + assign cea2_in = cea2_dly; + assign cead_in = cead_dly; + assign cealumode_in = cealumode_dly; + assign ceb1_in = ceb1_dly; + assign ceb2_in = ceb2_dly; + assign cec_in = cec_dly; + assign cecarryin_in = cecarryin_dly; + assign cectrl_in = cectrl_dly; + assign ced_in = ced_dly; + assign ceinmode_in = ceinmode_dly; + assign cem_in = cem_dly; + assign cep_in = cep_dly; + assign clk_in = clk_dly ^ IS_CLK_INVERTED_BIN; + assign d_in = d_dly; + assign inmode_in = inmode_dly ^ IS_INMODE_INVERTED_BIN; + assign multsignin_in = multsignin_dly; + assign opmode_in = opmode_dly ^ IS_OPMODE_INVERTED_BIN; + assign pcin_in = pcin_dly; + assign rsta_in = rsta_dly; + assign rstallcarryin_in = rstallcarryin_dly; + assign rstalumode_in = rstalumode_dly; + assign rstb_in = rstb_dly; + assign rstc_in = rstc_dly; + assign rstctrl_in = rstctrl_dly; + assign rstd_in = rstd_dly; + assign rstinmode_in = rstinmode_dly; + assign rstm_in = rstm_dly; + assign rstp_in = rstp_dly; + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in) begin + assign qcarryin_o_reg0 = 1'b0; + assign qcarryinsel_o_reg1 = 3'b0; + assign qopmode_o_reg1 = 7'b0; + assign qalumode_o_reg1 = 4'b0; + assign qa_o_reg1 = 30'b0; + assign qa_o_reg2 = 30'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qp_o_reg1 = 48'b0; + assign qmult_o_reg = 43'b0; + assign pdet_o_reg1 = 1'b0; + assign pdet_o_reg2 = 1'b0; + assign pdetb_o_reg1 = 1'b0; + assign pdetb_o_reg2 = 1'b0; +// 577648 commented out the following line +// assign carryout_o_reg = 4'b0; + assign carrycascout_o_reg = 1'b0; + assign qmultsignout_o_reg = 1'b0; + assign qd_o_reg1 = 25'b0; + assign qad_o_reg1 = 25'b0; + assign qinmode_o_reg = 5'b0; +// assign mult_o = 43'b0; + end + else begin + deassign qcarryin_o_reg0; + deassign qcarryinsel_o_reg1; + deassign qopmode_o_reg1; + deassign qalumode_o_reg1; + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qp_o_reg1; + deassign qmult_o_reg; + deassign pdet_o_reg1; + deassign pdet_o_reg2; + deassign pdetb_o_reg1; + deassign pdetb_o_reg2; +// 577648 commented out the following line +// deassign carryout_o_reg; + deassign carrycascout_o_reg; + deassign qmultsignout_o_reg; + deassign qd_o_reg1; + deassign qad_o_reg1; + deassign qinmode_o_reg; +// deassign mult_o; + end + end + + + initial begin + opmode_valid_flag <= 1; + invalid_opmode <= 1; + + //-------- A_INPUT check + + case (A_INPUT) + "DIRECT", "CASCADE" : ; + default : begin + $display("Attribute Syntax Error : The attribute A_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", A_INPUT); + #1 $finish; + end + endcase + + //-------- ALUMODEREG check + + case (ALUMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute ALUMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ALUMODEREG); + #1 $finish; + end + endcase + + //-------- AREG check + + case (AREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + #1 $finish; + end + endcase + + //-------- (ACASCREG) and (ACASCREG vs AREG) check + + case (AREG) + 0 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 0 when attribute AREG = 0.", ACASCREG); + #1 $finish; + end + 1 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 1 when attribute AREG = 1.", ACASCREG); + #1 $finish; + end + 2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = 2.", ACASCREG); + #1 $finish; + end + default : ; + endcase + + //-------- B_INPUT check + + case (B_INPUT) + "DIRECT", "CASCADE" : ; + default : begin + $display("Attribute Syntax Error : The attribute B_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + #1 $finish; + end + endcase + + + //-------- BREG check + + case (BREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + #1 $finish; + end + endcase + + //-------- (BCASCREG) and (BCASCREG vs BREG) check + + case (BREG) + 0 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 0 when attribute BREG = 0.", BCASCREG); + #1 $finish; + end + 1 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 1 when attribute BREG = 1.", BCASCREG); + #1 $finish; + end + 2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to either 2 or 1 when attribute BREG = 2.", BCASCREG); + #1 $finish; + end + default : ; + endcase + + //-------- CARRYINREG check + + case (CARRYINREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINREG); + #1 $finish; + end + endcase + + //-------- CARRYINSELREG check + + case (CARRYINSELREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINSELREG); + #1 $finish; + end + endcase + + //-------- CREG check + + case (CREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, or 1.", CREG); + #1 $finish; + end + endcase + + + //-------- OPMODEREG check + + case (OPMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", OPMODEREG); + #1 $finish; + end + endcase + + //-------- USE_MULT + + case (USE_MULT) + "NONE", "MULTIPLY", "DYNAMIC" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", USE_MULT); + #1 $finish; + end +/* + "MULT" : if (MREG != 0) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 0.", USE_MULT); + #1 $finish; + end + "MULT_S" : if (MREG != 1) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 1.", USE_MULT); + #1 $finish; + end + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are NONE, MULT or MULT_S.", USE_MULT); + #1 $finish; + end +*/ + endcase + + //-------- USE_PATTERN_DETECT + + case (USE_PATTERN_DETECT) + "PATDET", "NO_PATDET" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATDET or NO_PATDET.", USE_PATTERN_DETECT); + #1 $finish; + end + endcase + + //-------- AUTORESET_PATDET check + + case (AUTORESET_PATDET) + "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATDET on DSP48E1 instance %m is set to %s. Legal values for this attribute are NO_RESET or RESET_MATCH or RESET_NOT_MATCH.", AUTORESET_PATDET); + #1 $finish; + end + endcase + + //-------- SEL_PATTERN check + + case(SEL_PATTERN) + "PATTERN", "C" : ; + default : begin + $display("Attribute Syntax Error : The attribute SEL_PATTERN on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATTERN or C.", SEL_PATTERN); + #1 $finish; + end + endcase + + //-------- SEL_MASK check + + case(SEL_MASK) + "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" : ; + default : begin + $display("Attribute Syntax Error : The attribute SEL_MASK on DSP48E1 instance %m is set to %s. Legal values for this attribute are MASK or C or ROUNDING_MODE1 or ROUNDING_MODE2.", SEL_MASK); + #1 $finish; + end + endcase + + //-------- MREG check + + case (MREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", MREG); + #1 $finish; + end + endcase + + + //-------- PREG check + + case (PREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", PREG); + #1 $finish; + end + endcase + + + #100010 ping_opmode_drc_check <= 1; + + +//********************************************************* +//*** ADDITIONAL DRC +//********************************************************* +// CR 219407 -- (1) +// old ask vicv +/* + if((AUTORESET_PATTERN_DETECT == "TRUE") && (USE_PATTERN_DETECT == "NO_PATDET")) begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "); + end +*/ +//********************************************************* +//*** new attribute DRC +//********************************************************* + + //-------- ADREG check + + case (ADREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute ADREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ADREG); + #1 $finish; + end + endcase + + //-------- DREG check + + case (DREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute DREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", DREG); + #1 $finish; + end + endcase + + //-------- INMODEREG check + + case (INMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute INMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", INMODEREG); + #1 $finish; + end + endcase + + //-------- USE_DPORT + + case (USE_DPORT) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_DPORT on DSP48E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", USE_DPORT); + #1 $finish; + end + endcase + + if ((USE_MULT == "NONE") && (MREG !== 0)) begin + $display("Error : [Unisim %s-10] : Attribute USE_MULT is set to \"NONE\" and MREG is set to %2d. MREG must be set to 0 when the multiplier is not used. Instance %m", MODULE_NAME, MREG); + #1 $finish; + end + + end + + +//********************************************************* +//********** INMODE signal registering ************ +//********************************************************* +// new + always @(posedge clk_in) begin + if (rstinmode_in) + qinmode_o_reg <= 5'b0; + else if (ceinmode_in) + qinmode_o_reg <= inmode_in; + end + + generate + case (INMODEREG) + 0: begin + always @(inmode_in) + qinmode_o_mux <= inmode_in; + end + + 1: begin + always @(qinmode_o_reg) + qinmode_o_mux <= qinmode_o_reg; + end + endcase + endgenerate + +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + generate + case (A_INPUT) + "DIRECT" : always @(a_in) a_o_mux <= a_in; + "CASCADE" : always @(acin_in) a_o_mux <= acin_in; + endcase + endgenerate + + generate + case (AREG) + 1 : begin + always @(posedge clk_in) begin + if (rsta_in) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + if (cea1_in) + qa_o_reg1 <= a_o_mux; + if (cea2_in) + qa_o_reg2 <= a_o_mux; + end + end + end + + 2 : begin + always @(posedge clk_in) begin + if (rsta_in) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + if (cea1_in) + qa_o_reg1 <= a_o_mux; + if (cea2_in) + qa_o_reg2 <= qa_o_reg1; + end + end + end + endcase + endgenerate + + generate + case (AREG) + 0: always @(a_o_mux) qa_o_mux <= a_o_mux; + 1,2 : always @(qa_o_reg2) qa_o_mux <= qa_o_reg2; + endcase + endgenerate + + generate + case (ACASCREG) + 1: always @(qa_o_mux or qa_o_reg1) begin + if(AREG == 2) + qacout_o_mux <= qa_o_reg1; + else + qacout_o_mux <= qa_o_mux; + end + 0,2 : always @(qa_o_mux) qacout_o_mux <= qa_o_mux; + endcase + endgenerate + +// new + + assign a_preaddsub = qinmode_o_mux[1]? 25'b0:(qinmode_o_mux[0]?qa_o_reg1[24:0]:qa_o_mux[24:0]); + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + generate + case (B_INPUT) + "DIRECT" : always @(b_in) b_o_mux <= b_in; + "CASCADE" : always @(bcin_in) b_o_mux <= bcin_in; + endcase + endgenerate + + generate + case (BREG) + 1 : begin + always @(posedge clk_in) begin + if (rstb_in) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + if (ceb1_in) + qb_o_reg1 <= b_o_mux; + if (ceb2_in) + qb_o_reg2 <= b_o_mux; + end + end + end + + 2 : begin + always @(posedge clk_in) begin + if (rstb_in) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + if (ceb1_in) + qb_o_reg1 <= b_o_mux; + if (ceb2_in) + qb_o_reg2 <= qb_o_reg1; + end + end + end + endcase + endgenerate + + generate + case (BREG) + 0: always @(b_o_mux) qb_o_mux <= b_o_mux; + 1,2 : always @(qb_o_reg2) qb_o_mux <= qb_o_reg2; + endcase + endgenerate + + generate + case (BCASCREG) + 1: always @(qb_o_mux or qb_o_reg1) begin + if(BREG == 2) + qbcout_o_mux <= qb_o_reg1; + else + qbcout_o_mux <= qb_o_mux; + end + 0,2 : always @(qb_o_mux) qbcout_o_mux <= qb_o_mux; + endcase + endgenerate + + +// new + + assign b_mult = qinmode_o_mux[4]?qb_o_reg1:qb_o_mux; + +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge clk_in) begin + if (rstc_in) + qc_o_reg1 <= 48'b0; + else if (cec_in) + qc_o_reg1 <= c_in; + end + + + generate + case (CREG) + 0 : always @(c_in) qc_o_mux <= c_in; + 1 : always @(qc_o_reg1) qc_o_mux <= qc_o_reg1; + endcase + endgenerate + + +// new + +//********************************************************* +//*** Input register D with 1 level deep of register +//********************************************************* + always @(posedge clk_in) begin + if (rstd_in) + qd_o_reg1 <= 25'b0; + else if (ced_in) + qd_o_reg1 <= d_in; + end + + generate + case (DREG) + 0 : always @(d_in) qd_o_mux <= d_in; + 1 : always @(qd_o_reg1) qd_o_mux <= qd_o_reg1; + endcase + endgenerate + + + + +//********************************************************* +//*** Preaddsub AD register with 1 level deep of register +//********************************************************* +// new + assign ad_addsub = qinmode_o_mux[3]?(-a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0)):(a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0)); + + always @(posedge clk_in) begin + if (rstd_in) + qad_o_reg1 <= 25'b0; + else if (cead_in) + qad_o_reg1 <= ad_addsub; + end + + generate + case (ADREG) + 0 : always @(ad_addsub) qad_o_mux <= ad_addsub; + 1 : always @(qad_o_reg1) qad_o_mux <= qad_o_reg1; + endcase + endgenerate + +/*------------------------------------------------- */ +/*------------------------------------------------- */ + + assign ad_mult = (USE_DPORT=="TRUE")? qad_o_mux : a_preaddsub; +//********************************************************* + +//********************************************************* +//*************** 25x18 Multiplier *************** +//********************************************************* +// 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +// SIMD=FOUR12 and SIMD=TWO24 +// Made mult_o to be "X" + + always @(qopmode_o_mux) begin + if(qopmode_o_mux[3:0] == 4'b0101) + if((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) + $display("OPMODE Input Warning : The OPMODE[3:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", qopmode_o_mux[3:0], $time/1000.0); + end + +// assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))? 43'b0 : {{18{ad_mult[24]}}, ad_mult[24:0]} * {{25{b_mult[17]}}, b_mult}; + + assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD != "ONE48")) ? 43'b0 : + (carryinsel_in == 3'b010) ? 43'bx : + {{18{ad_mult[24]}}, ad_mult[24:0]} * {{25{b_mult[17]}}, b_mult}; + +// always @(*) begin +// if ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) +// mult_o = 43'b0; +// else if (qcarryinsel_o_mux == 3'b010) +// mult_o = 43'bx; +// else +// mult_o = {{18{ad_mult[24]}}, ad_mult[24:0]} * {{25{b_mult[17]}}, b_mult}; +// end + + always @(posedge clk_in) begin + if (rstm_in) begin + qmult_o_reg <= 43'b0; + end + else if (cem_in) begin + qmult_o_reg <= mult_o; + end + end + + always @ (mult_o, qmult_o_reg, qcarryinsel_o_mux) begin + if (qcarryinsel_o_mux == 3'b010) begin + qmult_o_mux = 43'bx ; + end else if (MREG == 1) begin + qmult_o_mux = qmult_o_reg; + end else + qmult_o_mux = mult_o; + end + +// generate +// case (MREG) +// 0 : always @(mult_o) qmult_o_mux <= mult_o; +// 1 : always @(qmult_o_reg) qmult_o_mux <= qmult_o_reg; +// endcase +// endgenerate + + +//*** X mux +// ask jmt + + always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux[1:0] or qcarryinsel_o_mux) begin +//add post 2014.4 +// if (qcarryinsel_o_mux == 3'b010) && (OPMODEREG == 0) begin +// qx_o_mux <= 48'bx; +// else + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{5{qmult_o_mux[MSB_A_MULT + MSB_B_MULT + 1]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; +// new DRC + 2'b11 : begin + if((USE_MULT == "MULTIPLY") && ( + (AREG==0 && BREG==0 && MREG==0) || + (AREG==0 && BREG==0 && PREG==0) || + (MREG==0 && PREG==0))) + $display("OPMODE Input Warning : The OPMODE[1:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = MULTIPLY at %.3f ns. Please set USE_MULT to either NONE or DYNAMIC.", qopmode_o_mux[1:0], $time/1000.0); + else + qx_o_mux <= {qa_o_mux[MSB_A:0], qb_o_mux[MSB_B:0]}; + end + + default : begin + end + endcase + end + + +//*** Y mux + +// 08-06-08 +// IR 478378 + wire [47:0] y_mac_cascd = (qopmode_o_mux[6:4] == 3'b100) ? {48{multsignin_in}} : {48{1'b1}}; + + always @(qc_o_mux or qopmode_o_mux[3:2] or qcarryinsel_o_mux or y_mac_cascd) begin +//add post 2014.4 +// if (qcarryinsel_o_mux == 3'b010) && (OPMODEREG == 0) begin +// qy_o_mux <= 48'bx; +// else + case (qopmode_o_mux[3:2]) + 2'b00 : qy_o_mux <= 48'b0; + 2'b01 : qy_o_mux <= 48'b0; +// 08-06-08 + 2'b10 : qy_o_mux <= y_mac_cascd; // choose all ones or mult-sign-extend + 2'b11 : qy_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or pcin_in or qopmode_o_mux[6:4] or qcarryinsel_o_mux) begin +// ask jmt +//add post 2014.4 +// if (qcarryinsel_o_mux == 3'b010) && (OPMODEREG == 0) begin +// qz_o_mux <= 48'bx; +// else + casex (qopmode_o_mux[6:4]) + 3'b000 : qz_o_mux <= 48'b0; + 3'b001 : qz_o_mux <= pcin_in; + 3'b010 : qz_o_mux <= qp_o_mux; + 3'b011 : qz_o_mux <= qc_o_mux; + 3'b100 : qz_o_mux <= qp_o_mux; + 3'b101 : qz_o_mux <= {{17{pcin_in[47]}}, pcin_in[47:17]}; +// ask jmt + 3'b11x : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]}; + default : begin + end + endcase + end + + + +//*** CarryInSel and OpMode with 1 level of register + always @(posedge clk_in) begin + if (rstctrl_in) begin + qcarryinsel_o_reg1 <= 3'b0; + qopmode_o_reg1 <= 7'b0; + end + else if (cectrl_in) begin + qcarryinsel_o_reg1 <= carryinsel_in; + qopmode_o_reg1 <= opmode_in; + end + end + + generate + case (CARRYINSELREG) + 0 : always @(carryinsel_in) qcarryinsel_o_mux <= carryinsel_in; + 1 : always @(qcarryinsel_o_reg1) qcarryinsel_o_mux <= qcarryinsel_o_reg1; + endcase + endgenerate + + +//CR 219047 (3) + + always @(qcarryinsel_o_mux or carrycascin_in or multsignin_in or qopmode_o_mux) begin + if(qcarryinsel_o_mux == 3'b010) begin + if(!((multsignin_in === 1'bx) || (cci_drc_msg == 1'b1) || + ((qopmode_o_mux == 7'b1001000) && !(multsignin_in === 1'bx)) || + ((multsignin_in == 1'b0) && (carrycascin_in == 1'b0)))) begin + $display("DRC warning : CARRYCASCIN can only be used in the current DSP48E1 instance %m if the previous DSP48E1 is performing a two input ADD or SUBTRACT operation, or the current DSP48E1 is configured in the MAC extend opmode 7'b1001000 at %.3f ns.", $time/1000.0); + cci_drc_msg = 1'b1; + end + if(!((multsignin_in === 1'bx) || (qopmode_o_mux[3:0] != 4'b0101))) begin + $display("DRC warning : CARRYINSEL is set to 010 with OPMODE set to multiplication (xxx0101). This is an illegal mode and may show deviation between simulation results and hardware behavior. DSP48E1 instance %m at %.3f ns.", $time/1000.0); + end + if(!((multsignin_in === 1'bx) || (cis_drc_msg == 1'b1) || + (OPMODEREG == 1'b1))) begin + $display("DRC warning : CARRYINSEL is set to 010 with OPMODEREG set to 0. This causes unknown values after reset occurs. It is suggested to use OPMODEREG = 1 when cascading large adders. DSP48E1 instance %m at %.3f ns.", $time/1000.0); + cis_drc_msg = 1'b1; + end + end + end + + generate + case (OPMODEREG) + 0 : always @(opmode_in) qopmode_o_mux <= opmode_in; + 1 : always @(qopmode_o_reg1) qopmode_o_mux <= qopmode_o_reg1; + endcase + endgenerate + + +//*** ALUMODE with 1 level of register + always @(posedge clk_in) begin + if (rstalumode_in) + qalumode_o_reg1 <= 4'b0; + else if (cealumode_in) + qalumode_o_reg1 <= alumode_in; + end + + + generate + case (ALUMODEREG) + 0 : always @(alumode_in) qalumode_o_mux <= alumode_in; + 1 : always @(qalumode_o_reg1) qalumode_o_mux <= qalumode_o_reg1; + endcase + endgenerate + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + + task deassign_xyz_mux; + begin + opmode_valid_flag = 1; + invalid_opmode = 1; // reset invalid opmode + end + endtask // deassign_xyz_mux + + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + opmode_valid_flag = 0; + invalid_opmode = 0; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + + always @(ping_opmode_drc_check or qalumode_o_mux or qopmode_o_mux or qcarryinsel_o_mux ) begin + + if ($time > 100000) begin // no check at first 100ns + case (qalumode_o_mux[3:2]) + 2'b00 : + //-- ARITHMETIC MODES DRC + casex ({qopmode_o_mux, qcarryinsel_o_mux}) + 10'bxxx0101010 : deassign_xyz_mux; // seperate drc above for these cases + 10'b0000000000 : deassign_xyz_mux; + 10'b0000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000011000 : deassign_xyz_mux; + 10'b0000011010 : deassign_xyz_mux; +// CR 573535 10'b0000011100 : deassign_xyz_mux; + 10'b0000011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000101000 : deassign_xyz_mux; + 10'b0001000000 : deassign_xyz_mux; + 10'b0001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001011000 : deassign_xyz_mux; + 10'b0001011010 : deassign_xyz_mux; +// CR 573535 10'b0001011100 : deassign_xyz_mux; + 10'b0001011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001100000 : deassign_xyz_mux; + 10'b0001100010 : deassign_xyz_mux; +// CR 573535 10'b0001100100 : deassign_xyz_mux; + 10'b0001100100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001111000 : deassign_xyz_mux; + 10'b0001111010 : deassign_xyz_mux; +// CR 573535 10'b0001111100 : deassign_xyz_mux; + 10'b0001111100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010000000 : deassign_xyz_mux; + 10'b0010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010011000 : deassign_xyz_mux; + 10'b0010011001 : deassign_xyz_mux; + 10'b0010011011 : deassign_xyz_mux; + 10'b0010101000 : deassign_xyz_mux; + 10'b0010101001 : deassign_xyz_mux; + 10'b0010101011 : deassign_xyz_mux; + 10'b0010101110 : deassign_xyz_mux; + 10'b0011000000 : deassign_xyz_mux; + 10'b0011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011011000 : deassign_xyz_mux; + 10'b0011011001 : deassign_xyz_mux; + 10'b0011011011 : deassign_xyz_mux; + 10'b0011100000 : deassign_xyz_mux; + 10'b0011100001 : deassign_xyz_mux; + 10'b0011100011 : deassign_xyz_mux; + 10'b0011100100 : deassign_xyz_mux; + 10'b0011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011111000 : deassign_xyz_mux; + 10'b0011111001 : deassign_xyz_mux; + 10'b0011111011 : deassign_xyz_mux; + 10'b0100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110000000 : deassign_xyz_mux; + 10'b0110000010 : deassign_xyz_mux; +// CR 573535 10'b0110000100 : deassign_xyz_mux; + 10'b0110000100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110011000 : deassign_xyz_mux; + 10'b0110011010 : deassign_xyz_mux; +// CR 573535 10'b0110011100 : deassign_xyz_mux; + 10'b0110011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110101000 : deassign_xyz_mux; + 10'b0110101110 : deassign_xyz_mux; + 10'b0111000000 : deassign_xyz_mux; + 10'b0111000010 : deassign_xyz_mux; +// CR 573535 10'b0111000100 : deassign_xyz_mux; + 10'b0111000100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111011000 : deassign_xyz_mux; + 10'b0111100000 : deassign_xyz_mux; + 10'b0111100010 : deassign_xyz_mux; + 10'b0111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111111000 : deassign_xyz_mux; + 10'b1001000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010000000 : deassign_xyz_mux; + 10'b1010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010011000 : deassign_xyz_mux; + 10'b1010011001 : deassign_xyz_mux; + 10'b1010011011 : deassign_xyz_mux; + 10'b1010101000 : deassign_xyz_mux; + 10'b1010101001 : deassign_xyz_mux; + 10'b1010101011 : deassign_xyz_mux; + 10'b1010101110 : deassign_xyz_mux; + 10'b1011000000 : deassign_xyz_mux; + 10'b1011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011011000 : deassign_xyz_mux; + 10'b1011011001 : deassign_xyz_mux; + 10'b1011011011 : deassign_xyz_mux; + 10'b1011100000 : deassign_xyz_mux; + 10'b1011100001 : deassign_xyz_mux; + 10'b1011100011 : deassign_xyz_mux; + 10'b1011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011111000 : deassign_xyz_mux; + 10'b1011111001 : deassign_xyz_mux; + 10'b1011111011 : deassign_xyz_mux; + 10'b1100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + opmode_valid_flag = 0; + invalid_opmode = 0; +// CR 444150 + if( ({qopmode_o_mux, qcarryinsel_o_mux} == 10'b0000000010) && ((OPMODEREG==1) && (CARRYINSELREG ==0)) ) $display("DRC warning : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, in order to ensure that the simulation model will match the hardware behavior in all use cases.", CARRYINSELREG); + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE is invalid at %.3f ns. This warning may be due to a mismatch in the OPMODEREG and CARRYINSELREG attribute settings. It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value. ", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + 2'b01, 2'b11 : + //-- LOGIC MODES DRC + case (qopmode_o_mux) + 7'b0000000 : deassign_xyz_mux; + 7'b0000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0000011 : deassign_xyz_mux; + 7'b0010000 : deassign_xyz_mux; + 7'b0010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0010011 : deassign_xyz_mux; + 7'b0100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110000 : deassign_xyz_mux; + 7'b0110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110011 : deassign_xyz_mux; + 7'b1010000 : deassign_xyz_mux; + 7'b1010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1010011 : deassign_xyz_mux; + 7'b1100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001000 : deassign_xyz_mux; + 7'b0001010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001011 : deassign_xyz_mux; + 7'b0011000 : deassign_xyz_mux; + 7'b0011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0011011 : deassign_xyz_mux; + 7'b0101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111000 : deassign_xyz_mux; + 7'b0111010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111011 : deassign_xyz_mux; + 7'b1011000 : deassign_xyz_mux; + 7'b1011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1011011 : deassign_xyz_mux; + 7'b1101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is invalid for LOGIC MODES at %.3f ns.", qopmode_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + endcase // case(qalumode_o_mux) + + end // if ($time > 100000) + + end // always @ (qopmode_o_mux) + + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + + wire mult_cout = ~qp_o_mux[42]; + reg [MSB_ALU_FULL:0] co; + reg [MSB_ALU_FULL:0] s; + wire [MSB_ALU_FULL:0] comux,smux; + wire [MSB_CARRYOUT:0] carryout_o_hw; + wire [MSB_CARRYOUT:0] carryout_o; + wire tmp_carrycascout_in; + + always @ (qx_o_mux or qy_o_mux or qz_o_mux or qalumode_o_mux[0]) begin + if (qalumode_o_mux[0]) begin + co = ((qx_o_mux & qy_o_mux)|((~qz_o_mux) & qy_o_mux)|(qx_o_mux & (~qz_o_mux))); + s = (~qz_o_mux) ^ qx_o_mux ^ qy_o_mux; + end + else begin + co = ((qx_o_mux & qy_o_mux)|(qz_o_mux & qy_o_mux)|(qx_o_mux & qz_o_mux)); + s = qz_o_mux ^ qx_o_mux ^ qy_o_mux; + end + end + + assign comux = qalumode_o_mux[2] ? 0 : co; + assign smux = qalumode_o_mux[3] ? co : s; + + // FINAL ADDER + wire [12:0] s0 = {comux[10:0],qcarryin_o_mux}+smux[11:0]; + wire cout0 = (comux[11] + s0[12]); + assign carryout_o_hw[0] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout0 : cout0; + wire C1 = (USE_SIMD == "FOUR12") ? 1'b0 : s0[12]; + + wire co11_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[11]; + wire [12:0] s1 = {comux[22:12],co11_lsb}+smux[23:12]+C1; + wire cout1 = (comux[23] + s1[12]); + assign carryout_o_hw[1] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout1 : cout1; + wire C2 = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? 1'b0 : s1[12]; + + wire co23_lsb = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? + 1'b0 : comux[23]; + + wire [12:0] s2 = {comux[34:24],co23_lsb}+smux[35:24]+C2; + wire cout2 = (comux[35] + s2[12]); + assign carryout_o_hw[2] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout2 : cout2; + wire C3 = (USE_SIMD == "FOUR12") ? 1'b0 : s2[12]; + + wire co35_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[35]; + wire [13:0] s3 = {comux[47:36],co35_lsb}+smux[47:36]+C3; + wire cout3 = s3[12]; + + assign carryout_o_hw[3] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout3 : cout3; + + wire cout4 = s3[13]; +// assign carryout_o_hw[4] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout4 : cout4; + + assign alu_o = qalumode_o_mux[1] ? ~{s3[11:0],s2[11:0],s1[11:0],s0[11:0]} : + {s3[11:0],s2[11:0],s1[11:0],s0[11:0]}; + // COMPUTE CARRYCASCOUT + assign carrycascout_o = cout3; + + // COMPUTE MULTSIGNOUT + // 08-06-08 assign multsignout_o_opmode = (qopmode_o_mux[3:0] === 4'b100) ? multsignin_in : ~qp_o_mux[42]; + // IR 478378 + assign multsignout_o_opmode = (qopmode_o_mux[6:4] === 3'b100) ? multsignin_in : qmult_o_mux[42]; + + // CR 523600 -- "X" carryout for multiply and logic operations + assign carryout_o[3] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : carryout_o_hw[3]; + assign carryout_o[2] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[2] : 1'bx; + assign carryout_o[1] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_hw[1] : 1'bx; + assign carryout_o[0] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[0] : 1'bx; + +//--########################### END ALU ################################ + + +//*** CarryIn Mux and Register + +//------- input 0 + always @(posedge clk_in) begin + if (rstallcarryin_in) + qcarryin_o_reg0 <= 1'b0; + else if (cecarryin_in) + qcarryin_o_reg0 <= carryin_in; + end + + generate + case (CARRYINREG) + 0 : always @(carryin_in) qcarryin_o_mux0 <= carryin_in; + 1 : always @(qcarryin_o_reg0) qcarryin_o_mux0 <= qcarryin_o_reg0; + endcase + endgenerate + +//------- input 7 + always @(posedge clk_in) begin + if (rstallcarryin_in) + qcarryin_o_reg7 <= 1'b0; +// old else if (cemultcarryin_in) +// new + else if (cem_in) +// IR 478377 + qcarryin_o_reg7 <= ad_mult[24] ~^ b_mult[17]; // xnor + end + +// always @(qa_o_mux[24] or qb_o_mux[17] or qcarryin_o_reg7) begin + always @(ad_mult[24] or b_mult[17] or qcarryin_o_reg7) begin +// old case (MULTCARRYINREG) +// new + case (MREG) +// IR 478377 + 0 : qcarryin_o_mux7 <= ad_mult[24] ~^ b_mult[17]; + 1 : qcarryin_o_mux7 <= qcarryin_o_reg7; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + reg qcarryin_o_mux_tmp; + always @(qcarryin_o_mux0 or pcin_in[47] or carrycascin_in or carrycascout_o_mux or qp_o_mux[47] or qcarryin_o_mux7 or qcarryinsel_o_mux) begin + case (qcarryinsel_o_mux) + 3'b000 : qcarryin_o_mux_tmp <= qcarryin_o_mux0; + 3'b001 : qcarryin_o_mux_tmp <= ~pcin_in[47]; + 3'b010 : qcarryin_o_mux_tmp <= carrycascin_in; + 3'b011 : qcarryin_o_mux_tmp <= pcin_in[47]; + 3'b100 : qcarryin_o_mux_tmp <= carrycascout_o_mux; + 3'b101 : qcarryin_o_mux_tmp <= ~qp_o_mux[47]; + 3'b110 : qcarryin_o_mux_tmp <= qcarryin_o_mux7; + 3'b111 : qcarryin_o_mux_tmp <= qp_o_mux[47]; + default : begin + end + endcase + end + // disable carryin when performing logic operation + always @(qcarryin_o_mux_tmp or qalumode_o_mux[3:2]) begin + qcarryin_o_mux <= (qalumode_o_mux[3] || qalumode_o_mux[2]) ? 1'b0 : qcarryin_o_mux_tmp; + end + + +//--#################################################################### +//--##### AUTORESET_PATDET ##### +//--#################################################################### + assign the_auto_reset_patdet = ((AUTORESET_PATDET == "RESET_MATCH") && pdet_o_reg1) + || + ((AUTORESET_PATDET == "RESET_NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1)); +//--#################################################################### +//--##### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT and PCOUT ###### +//--#################################################################### +//*** register with 1 level of register + always @(posedge clk_in) begin + if(rstp_in || the_auto_reset_patdet) + begin + carryout_o_reg <= 4'b0; + carrycascout_o_reg <= 1'b0; + qmultsignout_o_reg <= 1'b0; + qp_o_reg1 <= 48'b0; + end + else if (cep_in) begin + carryout_o_reg <= carryout_o; + carrycascout_o_reg <= carrycascout_o; + qmultsignout_o_reg <= multsignout_o_opmode; + qp_o_reg1 <= alu_o; + end + end + + generate + case (PREG) + 0: begin + always @(carryout_o) + carryout_o_mux <= carryout_o; + always @(carrycascout_o) + carrycascout_o_mux <= carrycascout_o; + always @(multsignout_o_opmode) + multsignout_o_mux <= multsignout_o_opmode; + always @(alu_o) + qp_o_mux <= #1 alu_o; + end + + 1: begin + always @(carryout_o_reg) + carryout_o_mux <= carryout_o_reg; + always @(carrycascout_o_reg) + carrycascout_o_mux <= carrycascout_o_reg; + always @(qmultsignout_o_reg) + multsignout_o_mux <= qmultsignout_o_reg; + always @(qp_o_reg1) + qp_o_mux <= qp_o_reg1; + end + endcase + endgenerate + + + +//CR 219047 (2) +// ask jmt whether i should comment this out +/* + always @(qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)] or qopmode_o_mux[3:0]) begin + if(qopmode_o_mux[3:0] == 4'b0101) + multsignout_o_opmode = qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)]; + else + multsignout_o_opmode = 1'bx; + end +*/ + + + +// assign carryout_x_o[4] = carryout_o_mux[4]; +// CR 510304 output X during multiply operation + + assign carryout_x_o[3] = carryout_o_mux[3]; + assign carryout_x_o[2] = (USE_SIMD == "FOUR12") ? carryout_o_mux[2] : 1'bx; + assign carryout_x_o[1] = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_mux[1] : 1'bx; + assign carryout_x_o[0] = (USE_SIMD == "FOUR12") ? carryout_o_mux[0] : 1'bx; + + +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + + +// new + // selet pattern + assign the_pattern = (SEL_PATTERN == "PATTERN") ? PATTERN : qc_o_mux; + + // selet mask + always @(qc_o_mux) begin + if (USE_PATTERN_DETECT == "NO_PATDET") + the_mask <= {48{1'b1}}; + else + case(SEL_MASK) + "MASK" : the_mask <= MASK; + "C" : the_mask <= qc_o_mux; + "ROUNDING_MODE1" : the_mask <= ~qc_o_mux << 1; + "ROUNDING_MODE2" : the_mask <= ~qc_o_mux << 2; + default : ; + endcase + end + + //-- now do the pattern detection + +// assign pdet_o = &(~(the_pattern ^ alu_o) | the_mask); +// assign pdetb_o = &((the_pattern ^ alu_o) | the_mask); + assign pdet_o = (~opmode_valid_flag) ? 1'bx : &(~(the_pattern ^ alu_o) | the_mask); + assign pdetb_o = (~opmode_valid_flag) ? 1'bx : &((the_pattern ^ alu_o) | the_mask); + +// assign pdet_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdet_o_reg1 : pdet_o; +// assign pdetb_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdetb_o_reg1 : pdetb_o; + assign pdet_o_mux = (PREG == 1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = (PREG == 1) ? pdetb_o_reg1 : pdetb_o; + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + + always @(posedge clk_in) begin + if((rstp_in) || the_auto_reset_patdet) + begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end + else if(cep_in) + begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg2 <= pdetb_o_reg1; + pdetb_o_reg1 <= pdetb_o; + end + end + + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + generate if ((USE_PATTERN_DETECT == "PATDET") || (PREG == 1)) + begin + assign overflow_o = pdet_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + assign underflow_o = pdetb_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + end + else + begin + assign overflow_o = 1'bx; + assign underflow_o = 1'bx; + end + endgenerate + + +`ifdef XIL_TIMING +//*** Timing Checks Start here + + always @(notifier) begin + qp_o_mux <= 48'bx; + qb_o_mux <= 18'bx; + end + +// not (nrsta, rsta_in); +// not (nrstb, rstb_in); +// not (nrstc, rstc_in); +// not (nrstp, rstp_in); +// not (nrstallcarryin, rstallcarryin_in); +// not (nrstctrl, rstctrl_in); + +// not (nrstinmode, rstinmode_in); +// not (nrstd, rstd_in); + + assign cea12_enable = (((AREG == 1) && cea1_in) || ((AREG == 2) && (cea1_in || cea2_in))); + assign ceb12_enable = (((BREG == 1) && ceb1_in) || ((BREG == 2) && (ceb1_in || ceb2_in))); + + assign a_en_n = (A_INPUT == "DIRECT") && cea12_enable && ~rsta_in && IS_CLK_INVERTED_BIN; + assign a_en_p = (A_INPUT == "DIRECT") && cea12_enable && ~rsta_in && ~IS_CLK_INVERTED_BIN; + assign b_en_n = (B_INPUT == "DIRECT") && ceb12_enable && ~rstb_in && IS_CLK_INVERTED_BIN; + assign b_en_p = (B_INPUT == "DIRECT") && ceb12_enable && ~rstb_in && ~IS_CLK_INVERTED_BIN; + + assign acin_en_n = (A_INPUT == "CASCADE") && cea12_enable && ~rsta_in && IS_CLK_INVERTED_BIN; + assign acin_en_p = (A_INPUT == "CASCADE") && cea12_enable && ~rsta_in && ~IS_CLK_INVERTED_BIN; + assign bcin_en_n = (B_INPUT == "CASCADE") && ceb12_enable && ~rstb_in && IS_CLK_INVERTED_BIN; + assign bcin_en_p = (B_INPUT == "CASCADE") && ceb12_enable && ~rstb_in && ~IS_CLK_INVERTED_BIN; + + assign carryin_en_n = cea12_enable && ceb12_enable && cecarryin_in && ~rsta_in && ~rstb_in && ~rstallcarryin_in && IS_CLK_INVERTED_BIN; + assign carryin_en_p = cea12_enable && ceb12_enable && cecarryin_in && ~rsta_in && ~rstb_in && ~rstallcarryin_in && ~IS_CLK_INVERTED_BIN; + assign carryinsel_en_n = cea12_enable && ceb12_enable && ~rsta_in && ~rstb_in && ~rstctrl_in && IS_CLK_INVERTED_BIN; + assign carryinsel_en_p = cea12_enable && ceb12_enable && ~rsta_in && ~rstb_in && ~rstctrl_in && ~IS_CLK_INVERTED_BIN; + assign opmode_en_n = cectrl_in && ~rstctrl_in && IS_CLK_INVERTED_BIN; + assign opmode_en_p = cectrl_in && ~rstctrl_in && ~IS_CLK_INVERTED_BIN; + assign pcin_en_n = cep_in && ~rstp_in && IS_CLK_INVERTED_BIN; + assign pcin_en_p = cep_in && ~rstp_in && ~IS_CLK_INVERTED_BIN; + + assign c_en_n = cec_in && ~rstc_in && IS_CLK_INVERTED_BIN; + assign c_en_p = cec_in && ~rstc_in && ~IS_CLK_INVERTED_BIN; + + assign inmode_en_n = ceinmode_in && ~rstinmode_in && IS_CLK_INVERTED_BIN; + assign inmode_en_p = ceinmode_in && ~rstinmode_in && ~IS_CLK_INVERTED_BIN; + assign d_en_n = ced_in && ~rstd_in && IS_CLK_INVERTED_BIN; + assign d_en_p = ced_in && ~rstd_in && ~IS_CLK_INVERTED_BIN; + + assign clk_gsr_en_n = ~gsr_in && IS_CLK_INVERTED_BIN; + assign clk_gsr_en_p = ~gsr_in && ~IS_CLK_INVERTED_BIN; + assign clk_rsta_en_n = ~rsta_in && IS_CLK_INVERTED_BIN; + assign clk_rsta_en_p = ~rsta_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstb_en_n = ~rstb_in && IS_CLK_INVERTED_BIN; + assign clk_rstb_en_p = ~rstb_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstc_en_n = ~rstc_in && IS_CLK_INVERTED_BIN; + assign clk_rstc_en_p = ~rstc_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstd_en_n = ~rstd_in && IS_CLK_INVERTED_BIN; + assign clk_rstd_en_p = ~rstd_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstm_en_n = ~rstm_in && IS_CLK_INVERTED_BIN; + assign clk_rstm_en_p = ~rstm_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstp_en_n = ~rstp_in && IS_CLK_INVERTED_BIN; + assign clk_rstp_en_p = ~rstp_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstallcarryin_en_n = ~rstallcarryin_in && IS_CLK_INVERTED_BIN; + assign clk_rstallcarryin_en_p = ~rstallcarryin_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstctrl_en_n = ~rstctrl_in && IS_CLK_INVERTED_BIN; + assign clk_rstctrl_en_p = ~rstctrl_in && ~IS_CLK_INVERTED_BIN; + assign clk_rstinmode_en_n = ~rstinmode_in && IS_CLK_INVERTED_BIN; + assign clk_rstinmode_en_p = ~rstinmode_in && ~IS_CLK_INVERTED_BIN; + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; +`endif + + specify + (A *> ACOUT) = (0:0:0, 0:0:0); + (A *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (A *> CARRYOUT) = (0:0:0, 0:0:0); + (A *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (A *> OVERFLOW) = (0:0:0, 0:0:0); + (A *> P) = (0:0:0, 0:0:0); + (A *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (A *> PATTERNDETECT) = (0:0:0, 0:0:0); + (A *> PCOUT) = (0:0:0, 0:0:0); + (A *> UNDERFLOW) = (0:0:0, 0:0:0); + (ACIN *> ACOUT) = (0:0:0, 0:0:0); + (ACIN *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (ACIN *> CARRYOUT) = (0:0:0, 0:0:0); + (ACIN *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (ACIN *> OVERFLOW) = (0:0:0, 0:0:0); + (ACIN *> P) = (0:0:0, 0:0:0); + (ACIN *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (ACIN *> PATTERNDETECT) = (0:0:0, 0:0:0); + (ACIN *> PCOUT) = (0:0:0, 0:0:0); + (ACIN *> UNDERFLOW) = (0:0:0, 0:0:0); + (ALUMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (ALUMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (ALUMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (ALUMODE *> OVERFLOW) = (0:0:0, 0:0:0); + (ALUMODE *> P) = (0:0:0, 0:0:0); + (ALUMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (ALUMODE *> PATTERNDETECT) = (0:0:0, 0:0:0); + (ALUMODE *> PCOUT) = (0:0:0, 0:0:0); + (ALUMODE *> UNDERFLOW) = (0:0:0, 0:0:0); + (B *> BCOUT) = (0:0:0, 0:0:0); + (B *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (B *> CARRYOUT) = (0:0:0, 0:0:0); + (B *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (B *> OVERFLOW) = (0:0:0, 0:0:0); + (B *> P) = (0:0:0, 0:0:0); + (B *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (B *> PATTERNDETECT) = (0:0:0, 0:0:0); + (B *> PCOUT) = (0:0:0, 0:0:0); + (B *> UNDERFLOW) = (0:0:0, 0:0:0); + (BCIN *> BCOUT) = (0:0:0, 0:0:0); + (BCIN *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (BCIN *> CARRYOUT) = (0:0:0, 0:0:0); + (BCIN *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (BCIN *> OVERFLOW) = (0:0:0, 0:0:0); + (BCIN *> P) = (0:0:0, 0:0:0); + (BCIN *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (BCIN *> PATTERNDETECT) = (0:0:0, 0:0:0); + (BCIN *> PCOUT) = (0:0:0, 0:0:0); + (BCIN *> UNDERFLOW) = (0:0:0, 0:0:0); + (C *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (C *> CARRYOUT) = (0:0:0, 0:0:0); + (C *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (C *> OVERFLOW) = (0:0:0, 0:0:0); + (C *> P) = (0:0:0, 0:0:0); + (C *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (C *> PATTERNDETECT) = (0:0:0, 0:0:0); + (C *> PCOUT) = (0:0:0, 0:0:0); + (C *> UNDERFLOW) = (0:0:0, 0:0:0); + (CARRYCASCIN *> CARRYOUT) = (0:0:0, 0:0:0); + (CARRYCASCIN *> P) = (0:0:0, 0:0:0); + (CARRYCASCIN *> PCOUT) = (0:0:0, 0:0:0); + (CARRYCASCIN => CARRYCASCOUT) = (0:0:0, 0:0:0); + (CARRYCASCIN => MULTSIGNOUT) = (0:0:0, 0:0:0); + (CARRYCASCIN => OVERFLOW) = (0:0:0, 0:0:0); + (CARRYCASCIN => PATTERNBDETECT) = (0:0:0, 0:0:0); + (CARRYCASCIN => PATTERNDETECT) = (0:0:0, 0:0:0); + (CARRYCASCIN => UNDERFLOW) = (0:0:0, 0:0:0); + (CARRYIN *> CARRYOUT) = (0:0:0, 0:0:0); + (CARRYIN *> P) = (0:0:0, 0:0:0); + (CARRYIN *> PCOUT) = (0:0:0, 0:0:0); + (CARRYIN => CARRYCASCOUT) = (0:0:0, 0:0:0); + (CARRYIN => MULTSIGNOUT) = (0:0:0, 0:0:0); + (CARRYIN => OVERFLOW) = (0:0:0, 0:0:0); + (CARRYIN => PATTERNBDETECT) = (0:0:0, 0:0:0); + (CARRYIN => PATTERNDETECT) = (0:0:0, 0:0:0); + (CARRYIN => UNDERFLOW) = (0:0:0, 0:0:0); + (CARRYINSEL *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> CARRYOUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> OVERFLOW) = (0:0:0, 0:0:0); + (CARRYINSEL *> P) = (0:0:0, 0:0:0); + (CARRYINSEL *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (CARRYINSEL *> PATTERNDETECT) = (0:0:0, 0:0:0); + (CARRYINSEL *> PCOUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> UNDERFLOW) = (0:0:0, 0:0:0); + (CLK *> ACOUT) = (100:100:100, 100:100:100); + (CLK *> BCOUT) = (100:100:100, 100:100:100); + (CLK *> CARRYOUT) = (100:100:100, 100:100:100); + (CLK *> P) = (100:100:100, 100:100:100); + (CLK *> PCOUT) = (100:100:100, 100:100:100); + (CLK => CARRYCASCOUT) = (100:100:100, 100:100:100); + (CLK => MULTSIGNOUT) = (100:100:100, 100:100:100); + (CLK => OVERFLOW) = (100:100:100, 100:100:100); + (CLK => PATTERNBDETECT) = (100:100:100, 100:100:100); + (CLK => PATTERNDETECT) = (100:100:100, 100:100:100); + (CLK => UNDERFLOW) = (100:100:100, 100:100:100); + (D *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (D *> CARRYOUT) = (0:0:0, 0:0:0); + (D *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (D *> OVERFLOW) = (0:0:0, 0:0:0); + (D *> P) = (0:0:0, 0:0:0); + (D *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (D *> PATTERNDETECT) = (0:0:0, 0:0:0); + (D *> PCOUT) = (0:0:0, 0:0:0); + (D *> UNDERFLOW) = (0:0:0, 0:0:0); + (INMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (INMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (INMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (INMODE *> OVERFLOW) = (0:0:0, 0:0:0); + (INMODE *> P) = (0:0:0, 0:0:0); + (INMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (INMODE *> PATTERNDETECT) = (0:0:0, 0:0:0); + (INMODE *> PCOUT) = (0:0:0, 0:0:0); + (INMODE *> UNDERFLOW) = (0:0:0, 0:0:0); + (MULTSIGNIN *> CARRYOUT) = (0:0:0, 0:0:0); + (MULTSIGNIN *> P) = (0:0:0, 0:0:0); + (MULTSIGNIN *> PCOUT) = (0:0:0, 0:0:0); + (MULTSIGNIN => CARRYCASCOUT) = (0:0:0, 0:0:0); + (MULTSIGNIN => MULTSIGNOUT) = (0:0:0, 0:0:0); + (MULTSIGNIN => OVERFLOW) = (0:0:0, 0:0:0); + (MULTSIGNIN => PATTERNBDETECT) = (0:0:0, 0:0:0); + (MULTSIGNIN => PATTERNDETECT) = (0:0:0, 0:0:0); + (MULTSIGNIN => UNDERFLOW) = (0:0:0, 0:0:0); + (OPMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (OPMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (OPMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (OPMODE *> OVERFLOW) = (0:0:0, 0:0:0); + (OPMODE *> P) = (0:0:0, 0:0:0); + (OPMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (OPMODE *> PATTERNDETECT) = (0:0:0, 0:0:0); + (OPMODE *> PCOUT) = (0:0:0, 0:0:0); + (OPMODE *> UNDERFLOW) = (0:0:0, 0:0:0); + (PCIN *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (PCIN *> CARRYOUT) = (0:0:0, 0:0:0); + (PCIN *> MULTSIGNOUT) = (0:0:0, 0:0:0); + (PCIN *> OVERFLOW) = (0:0:0, 0:0:0); + (PCIN *> P) = (0:0:0, 0:0:0); + (PCIN *> PATTERNBDETECT) = (0:0:0, 0:0:0); + (PCIN *> PATTERNDETECT) = (0:0:0, 0:0:0); + (PCIN *> PCOUT) = (0:0:0, 0:0:0); + (PCIN *> UNDERFLOW) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge A, 0:0:0, 0:0:0, notifier,a_en_n,a_en_n, clk_dly, a_dly); + $setuphold (negedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier,acin_en_n,acin_en_n, clk_dly, acin_dly); + $setuphold (negedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, alumode_dly); + $setuphold (negedge CLK, negedge B, 0:0:0, 0:0:0, notifier,b_en_n,b_en_n, clk_dly, b_dly); + $setuphold (negedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier,bcin_en_n,bcin_en_n, clk_dly, bcin_dly); + $setuphold (negedge CLK, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n, clk_dly, c_dly); + $setuphold (negedge CLK, negedge CARRYCASCIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, carrycascin_dly); + $setuphold (negedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier,carryin_en_n,carryin_en_n, clk_dly, carryin_dly); + $setuphold (negedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier,carryinsel_en_n,carryinsel_en_n, clk_dly, carryinsel_dly); + $setuphold (negedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier,clk_rsta_en_n,clk_rsta_en_n, clk_dly, cea1_dly); + $setuphold (negedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier,clk_rsta_en_n,clk_rsta_en_n, clk_dly, cea2_dly); + $setuphold (negedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier,clk_rstd_en_n,clk_rstd_en_n, clk_dly, cead_dly); + $setuphold (negedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, cealumode_dly); + $setuphold (negedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier,clk_rstb_en_n,clk_rstb_en_n, clk_dly, ceb1_dly); + $setuphold (negedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier,clk_rstb_en_n,clk_rstb_en_n, clk_dly, ceb2_dly); + $setuphold (negedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier,clk_rstc_en_n,clk_rstc_en_n, clk_dly, cec_dly); + $setuphold (negedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier,clk_rstallcarryin_en_n,clk_rstallcarryin_en_n, clk_dly, cecarryin_dly); + $setuphold (negedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier,clk_rstctrl_en_n,clk_rstctrl_en_n, clk_dly, cectrl_dly); + $setuphold (negedge CLK, negedge CED, 0:0:0, 0:0:0, notifier,clk_rstd_en_n,clk_rstd_en_n, clk_dly, ced_dly); + $setuphold (negedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier,clk_rstinmode_en_n,clk_rstinmode_en_n, clk_dly, ceinmode_dly); + $setuphold (negedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,clk_rstm_en_n,clk_rstm_en_n, clk_dly, cem_dly); + $setuphold (negedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier,clk_rstp_en_n,clk_rstp_en_n, clk_dly, cep_dly); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,d_en_n,d_en_n, clk_dly, d_dly); + $setuphold (negedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier,inmode_en_n,inmode_en_n, clk_dly, inmode_dly); + $setuphold (negedge CLK, negedge MULTSIGNIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, multsignin_dly); + $setuphold (negedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier,opmode_en_n,opmode_en_n, clk_dly, opmode_dly); + $setuphold (negedge CLK, negedge PCIN, 0:0:0, 0:0:0, notifier,pcin_en_n,pcin_en_n, clk_dly, pcin_dly); + $setuphold (negedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rsta_dly); + $setuphold (negedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstallcarryin_dly); + $setuphold (negedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstalumode_dly); + $setuphold (negedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstb_dly); + $setuphold (negedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstc_dly); + $setuphold (negedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstctrl_dly); + $setuphold (negedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstd_dly); + $setuphold (negedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstinmode_dly); + $setuphold (negedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstm_dly); + $setuphold (negedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstp_dly); + $setuphold (negedge CLK, posedge A, 0:0:0, 0:0:0, notifier,a_en_n,a_en_n, clk_dly, a_dly); + $setuphold (negedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier,acin_en_n,acin_en_n, clk_dly, acin_dly); + $setuphold (negedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, alumode_dly); + $setuphold (negedge CLK, posedge B, 0:0:0, 0:0:0, notifier,b_en_n,b_en_n, clk_dly, b_dly ); + $setuphold (negedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier,bcin_en_n,bcin_en_n, clk_dly, bcin_dly); + $setuphold (negedge CLK, posedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n, clk_dly, c_dly); + $setuphold (negedge CLK, posedge CARRYCASCIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, carrycascin_dly); + $setuphold (negedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier,carryin_en_n,carryin_en_n, clk_dly, carryin_dly); + $setuphold (negedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier,carryinsel_en_n,carryinsel_en_n, clk_dly, carryinsel_dly); + $setuphold (negedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier,clk_rsta_en_n,clk_rsta_en_n, clk_dly, cea1_dly); + $setuphold (negedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier,clk_rsta_en_n,clk_rsta_en_n, clk_dly, cea2_dly); + $setuphold (negedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier,clk_rstd_en_n,clk_rstd_en_n, clk_dly, cead_dly); + $setuphold (negedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, cealumode_dly); + $setuphold (negedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier,clk_rstb_en_n,clk_rstb_en_n, clk_dly, ceb1_dly); + $setuphold (negedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier,clk_rstb_en_n,clk_rstb_en_n, clk_dly, ceb2_dly); + $setuphold (negedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier,clk_rstc_en_n,clk_rstc_en_n, clk_dly, cec_dly); + $setuphold (negedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier,clk_rstallcarryin_en_n,clk_rstallcarryin_en_n, clk_dly, cecarryin_dly); + $setuphold (negedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier,clk_rstctrl_en_n,clk_rstctrl_en_n, clk_dly, cectrl_dly); + $setuphold (negedge CLK, posedge CED, 0:0:0, 0:0:0, notifier,clk_rstd_en_n,clk_rstd_en_n, clk_dly, ced_dly); + $setuphold (negedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier,clk_rstinmode_en_n,clk_rstinmode_en_n, clk_dly, ceinmode_dly); + $setuphold (negedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,clk_rstm_en_n,clk_rstm_en_n, clk_dly, cem_dly); + $setuphold (negedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier,clk_rstp_en_n,clk_rstp_en_n, clk_dly, cep_dly); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,d_en_n,d_en_n, clk_dly, d_dly); + $setuphold (negedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier,inmode_en_n,inmode_en_n, clk_dly, inmode_dly); + $setuphold (negedge CLK, posedge MULTSIGNIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, clk_dly, multsignin_dly); + $setuphold (negedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier,opmode_en_n,opmode_en_n, clk_dly, opmode_dly); + $setuphold (negedge CLK, posedge PCIN, 0:0:0, 0:0:0, notifier,pcin_en_n,pcin_en_n, clk_dly, pcin_dly); + $setuphold (negedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rsta_dly); + $setuphold (negedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstallcarryin_dly); + $setuphold (negedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstalumode_dly); + $setuphold (negedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstb_dly); + $setuphold (negedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstc_dly); + $setuphold (negedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstctrl_dly); + $setuphold (negedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstd_dly); + $setuphold (negedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstinmode_dly); + $setuphold (negedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstm_dly); + $setuphold (negedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier,clk_gsr_en_n,clk_gsr_en_n, clk_dly, rstp_dly); + $setuphold (posedge CLK, negedge A, 0:0:0, 0:0:0, notifier,a_en_p,a_en_p, clk_dly, a_dly); + $setuphold (posedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier,acin_en_p,acin_en_p, clk_dly, acin_dly); + $setuphold (posedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, alumode_dly); + $setuphold (posedge CLK, negedge B, 0:0:0, 0:0:0, notifier,b_en_p,b_en_p, clk_dly, b_dly); + $setuphold (posedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier,bcin_en_p,bcin_en_p, clk_dly, bcin_dly); + $setuphold (posedge CLK, negedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p, clk_dly, c_dly); + $setuphold (posedge CLK, negedge CARRYCASCIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, carrycascin_dly); + $setuphold (posedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier,carryin_en_p,carryin_en_p, clk_dly, carryin_dly); + $setuphold (posedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier,carryinsel_en_p,carryinsel_en_p, clk_dly, carryinsel_dly); + $setuphold (posedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier,clk_rsta_en_p,clk_rsta_en_p, clk_dly, cea1_dly); + $setuphold (posedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier,clk_rsta_en_p,clk_rsta_en_p, clk_dly, cea2_dly); + $setuphold (posedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier,clk_rstd_en_p,clk_rstd_en_p, clk_dly, cead_dly); + $setuphold (posedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, cealumode_dly); + $setuphold (posedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier,clk_rstb_en_p,clk_rstb_en_p, clk_dly, ceb1_dly); + $setuphold (posedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier,clk_rstb_en_p,clk_rstb_en_p, clk_dly, ceb2_dly); + $setuphold (posedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier,clk_rstc_en_p,clk_rstc_en_p, clk_dly, cec_dly); + $setuphold (posedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier,clk_rstallcarryin_en_p,clk_rstallcarryin_en_p, clk_dly, cecarryin_dly); + $setuphold (posedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier,clk_rstctrl_en_p,clk_rstctrl_en_p, clk_dly, cectrl_dly); + $setuphold (posedge CLK, negedge CED, 0:0:0, 0:0:0, notifier,clk_rstd_en_p,clk_rstd_en_p, clk_dly, ced_dly); + $setuphold (posedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier,clk_rstinmode_en_p,clk_rstinmode_en_p, clk_dly, ceinmode_dly); + $setuphold (posedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,clk_rstm_en_p,clk_rstm_en_p, clk_dly, cem_dly); + $setuphold (posedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier,clk_rstp_en_p,clk_rstp_en_p, clk_dly, cep_dly); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,d_en_p,d_en_p, clk_dly, d_dly); + $setuphold (posedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier,inmode_en_p,inmode_en_p, clk_dly, inmode_dly); + $setuphold (posedge CLK, negedge MULTSIGNIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, multsignin_dly); + $setuphold (posedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier,opmode_en_p,opmode_en_p, clk_dly, opmode_dly); + $setuphold (posedge CLK, negedge PCIN, 0:0:0, 0:0:0, notifier,pcin_en_p,pcin_en_p, clk_dly, pcin_dly); + $setuphold (posedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rsta_dly); + $setuphold (posedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstallcarryin_dly); + $setuphold (posedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstalumode_dly); + $setuphold (posedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstb_dly); + $setuphold (posedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstc_dly); + $setuphold (posedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstctrl_dly); + $setuphold (posedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstd_dly); + $setuphold (posedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstinmode_dly); + $setuphold (posedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstm_dly); + $setuphold (posedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstp_dly); + $setuphold (posedge CLK, posedge A, 0:0:0, 0:0:0, notifier,a_en_p,a_en_p, clk_dly, a_dly); + $setuphold (posedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier,acin_en_p,acin_en_p, clk_dly, acin_dly); + $setuphold (posedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, alumode_dly); + $setuphold (posedge CLK, posedge B, 0:0:0, 0:0:0, notifier,b_en_p,b_en_p, clk_dly, b_dly ); + $setuphold (posedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier,bcin_en_p,bcin_en_p, clk_dly, bcin_dly); + $setuphold (posedge CLK, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p, clk_dly, c_dly); + $setuphold (posedge CLK, posedge CARRYCASCIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, carrycascin_dly); + $setuphold (posedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier,carryin_en_p,carryin_en_p, clk_dly, carryin_dly); + $setuphold (posedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier,carryinsel_en_p,carryinsel_en_p, clk_dly, carryinsel_dly); + $setuphold (posedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier,clk_rsta_en_p,clk_rsta_en_p, clk_dly, cea1_dly); + $setuphold (posedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier,clk_rsta_en_p,clk_rsta_en_p, clk_dly, cea2_dly); + $setuphold (posedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier,clk_rstd_en_p,clk_rstd_en_p, clk_dly, cead_dly); + $setuphold (posedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, cealumode_dly); + $setuphold (posedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier,clk_rstb_en_p,clk_rstb_en_p, clk_dly, ceb1_dly); + $setuphold (posedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier,clk_rstb_en_p,clk_rstb_en_p, clk_dly, ceb2_dly); + $setuphold (posedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier,clk_rstc_en_p,clk_rstc_en_p, clk_dly, cec_dly); + $setuphold (posedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier,clk_rstallcarryin_en_p,clk_rstallcarryin_en_p, clk_dly, cecarryin_dly); + $setuphold (posedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier,clk_rstctrl_en_p,clk_rstctrl_en_p, clk_dly, cectrl_dly); + $setuphold (posedge CLK, posedge CED, 0:0:0, 0:0:0, notifier,clk_rstd_en_p,clk_rstd_en_p, clk_dly, ced_dly); + $setuphold (posedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier,clk_rstinmode_en_p,clk_rstinmode_en_p, clk_dly, ceinmode_dly); + $setuphold (posedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,clk_rstm_en_p,clk_rstm_en_p, clk_dly, cem_dly); + $setuphold (posedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier,clk_rstp_en_p,clk_rstp_en_p, clk_dly, cep_dly); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,d_en_p,d_en_p, clk_dly, d_dly); + $setuphold (posedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier,inmode_en_p,inmode_en_p, clk_dly, inmode_dly); + $setuphold (posedge CLK, posedge MULTSIGNIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, clk_dly, multsignin_dly); + $setuphold (posedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier,opmode_en_p,opmode_en_p, clk_dly, opmode_dly); + $setuphold (posedge CLK, posedge PCIN, 0:0:0, 0:0:0, notifier,pcin_en_p,pcin_en_p, clk_dly, pcin_dly); + $setuphold (posedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rsta_dly); + $setuphold (posedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstallcarryin_dly); + $setuphold (posedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstalumode_dly); + $setuphold (posedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstb_dly); + $setuphold (posedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstc_dly); + $setuphold (posedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstctrl_dly); + $setuphold (posedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstd_dly); + $setuphold (posedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstinmode_dly); + $setuphold (posedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstm_dly); + $setuphold (posedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier,clk_gsr_en_p,clk_gsr_en_p, clk_dly, rstp_dly); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP48E2.v b/verilog/src/unisims/DSP48E2.v new file mode 100644 index 0000000..374f8cb --- /dev/null +++ b/verilog/src/unisims/DSP48E2.v @@ -0,0 +1,1830 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 48-bit Multi-Functional Arithmetic Block +// /___/ /\ Filename : DSP48E2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 01/10/13 - 694456 - DIN_in/D_in connectivity issue +// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml +// 02/13/13 - PCIN_47A change from internal feedback to PCIN(47) pin +// 03/06/13 - 701316 - A_B_reg no clk when REG=0 +// 04/03/13 - yaml update +// 04/08/13 - 710304 - AREG, BREG, ACASCREG and BCASCREG dynamic registers mis sized. +// 04/22/13 - 714213 - ACOUT, BCOUT wrong logic +// 04/22/13 - 713695 - Zero mult result on USE_SIMD +// 04/22/13 - 713617 - CARRYCASCOUT behaviour +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 04/23/13 - 713706 - change P_PDBK connection +// 05/07/13 - 716896 - AREG, BREG, ACASCREG and BCASCREG localparams mis sized. +// 05/07/13 - 716896 - ALUMODE/OPMODE_INV_REG mis sized +// 05/07/13 - 716896 - INMODE_INV_REG mis sized +// 05/07/13 - x_mac_cascd missing for sensitivity list. +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP48E2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer ACASCREG = 1, + parameter integer ADREG = 1, + parameter integer ALUMODEREG = 1, + parameter AMULTSEL = "A", + parameter integer AREG = 1, + parameter AUTORESET_PATDET = "NO_RESET", + parameter AUTORESET_PRIORITY = "RESET", + parameter A_INPUT = "DIRECT", + parameter integer BCASCREG = 1, + parameter BMULTSEL = "B", + parameter integer BREG = 1, + parameter B_INPUT = "DIRECT", + parameter integer CARRYINREG = 1, + parameter integer CARRYINSELREG = 1, + parameter integer CREG = 1, + parameter integer DREG = 1, + parameter integer INMODEREG = 1, + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000, + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [4:0] IS_INMODE_INVERTED = 5'b00000, + parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000, + parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0, + parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0, + parameter [0:0] IS_RSTA_INVERTED = 1'b0, + parameter [0:0] IS_RSTB_INVERTED = 1'b0, + parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0, + parameter [0:0] IS_RSTC_INVERTED = 1'b0, + parameter [0:0] IS_RSTD_INVERTED = 1'b0, + parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0, + parameter [0:0] IS_RSTM_INVERTED = 1'b0, + parameter [0:0] IS_RSTP_INVERTED = 1'b0, + parameter [47:0] MASK = 48'h3FFFFFFFFFFF, + parameter integer MREG = 1, + parameter integer OPMODEREG = 1, + parameter [47:0] PATTERN = 48'h000000000000, + parameter PREADDINSEL = "A", + parameter integer PREG = 1, + parameter [47:0] RND = 48'h000000000000, + parameter SEL_MASK = "MASK", + parameter SEL_PATTERN = "PATTERN", + parameter USE_MULT = "MULTIPLY", + parameter USE_PATTERN_DETECT = "NO_PATDET", + parameter USE_SIMD = "ONE48", + parameter USE_WIDEXOR = "FALSE", + parameter XORSIMD = "XOR24_48_96" +)( + output [29:0] ACOUT, + output [17:0] BCOUT, + output CARRYCASCOUT, + output [3:0] CARRYOUT, + output MULTSIGNOUT, + output OVERFLOW, + output [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + output [7:0] XOROUT, + + input [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [26:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [8:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + +// define constants + localparam MODULE_NAME = "DSP48E2"; + +// Parameter encodings and registers + localparam AMULTSEL_A = 0; + localparam AMULTSEL_AD = 1; + localparam AUTORESET_PATDET_NO_RESET = 0; + localparam AUTORESET_PATDET_RESET_MATCH = 1; + localparam AUTORESET_PATDET_RESET_NOT_MATCH = 2; + localparam AUTORESET_PRIORITY_CEP = 1; + localparam AUTORESET_PRIORITY_RESET = 0; + localparam A_INPUT_CASCADE = 1; + localparam A_INPUT_DIRECT = 0; + localparam BMULTSEL_AD = 1; + localparam BMULTSEL_B = 0; + localparam B_INPUT_CASCADE = 1; + localparam B_INPUT_DIRECT = 0; + localparam PREADDINSEL_A = 0; + localparam PREADDINSEL_B = 1; + localparam SEL_MASK_C = 1; + localparam SEL_MASK_MASK = 0; + localparam SEL_MASK_ROUNDING_MODE1 = 2; + localparam SEL_MASK_ROUNDING_MODE2 = 3; + localparam SEL_PATTERN_C = 1; + localparam SEL_PATTERN_PATTERN = 0; + localparam USE_MULT_DYNAMIC = 1; + localparam USE_MULT_MULTIPLY = 0; + localparam USE_MULT_NONE = 2; + localparam USE_PATTERN_DETECT_NO_PATDET = 0; + localparam USE_PATTERN_DETECT_PATDET = 1; + localparam USE_SIMD_FOUR12 = 1; + localparam USE_SIMD_ONE48 = 0; + localparam USE_SIMD_TWO24 = 2; + localparam USE_WIDEXOR_FALSE = 0; + localparam USE_WIDEXOR_TRUE = 1; + localparam XORSIMD_XOR12 = 1; + localparam XORSIMD_XOR24_48_96 = 0; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP48E2_dr.v" +`else + reg [31:0] ACASCREG_REG = ACASCREG; + reg [31:0] ADREG_REG = ADREG; + reg [31:0] ALUMODEREG_REG = ALUMODEREG; + reg [16:1] AMULTSEL_REG = AMULTSEL; + reg [31:0] AREG_REG = AREG; + reg [120:1] AUTORESET_PATDET_REG = AUTORESET_PATDET; + reg [40:1] AUTORESET_PRIORITY_REG = AUTORESET_PRIORITY; + reg [56:1] A_INPUT_REG = A_INPUT; + reg [31:0] BCASCREG_REG = BCASCREG; + reg [16:1] BMULTSEL_REG = BMULTSEL; + reg [31:0] BREG_REG = BREG; + reg [56:1] B_INPUT_REG = B_INPUT; + reg [31:0] CARRYINREG_REG = CARRYINREG; + reg [31:0] CARRYINSELREG_REG = CARRYINSELREG; + reg [31:0] CREG_REG = CREG; + reg [31:0] DREG_REG = DREG; + reg [31:0] INMODEREG_REG = INMODEREG; + reg [3:0] IS_ALUMODE_INVERTED_REG = IS_ALUMODE_INVERTED; + reg [0:0] IS_CARRYIN_INVERTED_REG = IS_CARRYIN_INVERTED; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED; + reg [8:0] IS_OPMODE_INVERTED_REG = IS_OPMODE_INVERTED; + reg [0:0] IS_RSTALLCARRYIN_INVERTED_REG = IS_RSTALLCARRYIN_INVERTED; + reg [0:0] IS_RSTALUMODE_INVERTED_REG = IS_RSTALUMODE_INVERTED; + reg [0:0] IS_RSTA_INVERTED_REG = IS_RSTA_INVERTED; + reg [0:0] IS_RSTB_INVERTED_REG = IS_RSTB_INVERTED; + reg [0:0] IS_RSTCTRL_INVERTED_REG = IS_RSTCTRL_INVERTED; + reg [0:0] IS_RSTC_INVERTED_REG = IS_RSTC_INVERTED; + reg [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED; + reg [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED; + reg [0:0] IS_RSTM_INVERTED_REG = IS_RSTM_INVERTED; + reg [0:0] IS_RSTP_INVERTED_REG = IS_RSTP_INVERTED; + reg [47:0] MASK_REG = MASK; + reg [31:0] MREG_REG = MREG; + reg [31:0] OPMODEREG_REG = OPMODEREG; + reg [47:0] PATTERN_REG = PATTERN; + reg [8:1] PREADDINSEL_REG = PREADDINSEL; + reg [31:0] PREG_REG = PREG; + reg [47:0] RND_REG = RND; + reg [112:1] SEL_MASK_REG = SEL_MASK; + reg [56:1] SEL_PATTERN_REG = SEL_PATTERN; + reg [64:1] USE_MULT_REG = USE_MULT; + reg [72:1] USE_PATTERN_DETECT_REG = USE_PATTERN_DETECT; + reg [48:1] USE_SIMD_REG = USE_SIMD; + reg [40:1] USE_WIDEXOR_REG = USE_WIDEXOR; + reg [88:1] XORSIMD_REG = XORSIMD; +`endif + +`ifdef XIL_XECLIB + wire [1:0] ACASCREG_BIN; + wire ADREG_BIN; + wire ALUMODEREG_BIN; + wire AMULTSEL_BIN; + wire [1:0] AREG_BIN; + wire [1:0] AUTORESET_PATDET_BIN; + wire AUTORESET_PRIORITY_BIN; + wire A_INPUT_BIN; + wire [1:0] BCASCREG_BIN; + wire BMULTSEL_BIN; + wire [1:0] BREG_BIN; + wire B_INPUT_BIN; + wire CARRYINREG_BIN; + wire CARRYINSELREG_BIN; + wire CREG_BIN; + wire DREG_BIN; + wire INMODEREG_BIN; + wire MREG_BIN; + wire OPMODEREG_BIN; + wire PREADDINSEL_BIN; + wire PREG_BIN; + wire [1:0] SEL_MASK_BIN; + wire SEL_PATTERN_BIN; + wire [1:0] USE_MULT_BIN; + wire USE_PATTERN_DETECT_BIN; + wire [1:0] USE_SIMD_BIN; + wire USE_WIDEXOR_BIN; + wire XORSIMD_BIN; +`else + reg [1:0] ACASCREG_BIN; + reg ADREG_BIN; + reg ALUMODEREG_BIN; + reg AMULTSEL_BIN; + reg [1:0] AREG_BIN; + reg [1:0] AUTORESET_PATDET_BIN; + reg AUTORESET_PRIORITY_BIN; + reg A_INPUT_BIN; + reg [1:0] BCASCREG_BIN; + reg BMULTSEL_BIN; + reg [1:0] BREG_BIN; + reg B_INPUT_BIN; + reg CARRYINREG_BIN; + reg CARRYINSELREG_BIN; + reg CREG_BIN; + reg DREG_BIN; + reg INMODEREG_BIN; + reg MREG_BIN; + reg OPMODEREG_BIN; + reg PREADDINSEL_BIN; + reg PREG_BIN; + reg [1:0] SEL_MASK_BIN; + reg SEL_PATTERN_BIN; + reg [1:0] USE_MULT_BIN; + reg USE_PATTERN_DETECT_BIN; + reg [1:0] USE_SIMD_BIN; + reg USE_WIDEXOR_BIN; + reg XORSIMD_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CARRYCASCIN_in; + wire CARRYIN_in; + wire CEA1_in; + wire CEA2_in; + wire CEAD_in; + wire CEALUMODE_in; + wire CEB1_in; + wire CEB2_in; + wire CECARRYIN_in; + wire CECTRL_in; + wire CEC_in; + wire CED_in; + wire CEINMODE_in; + wire CEM_in; + wire CEP_in; + wire CLK_in; + wire MULTSIGNIN_in; + wire RSTALLCARRYIN_in; + wire RSTALUMODE_in; + wire RSTA_in; + wire RSTB_in; + wire RSTCTRL_in; + wire RSTC_in; + wire RSTD_in; + wire RSTINMODE_in; + wire RSTM_in; + wire RSTP_in; + wire [17:0] BCIN_in; + wire [17:0] B_in; + wire [26:0] D_in; + wire [29:0] ACIN_in; + wire [29:0] A_in; + wire [2:0] CARRYINSEL_in; + wire [3:0] ALUMODE_in; + wire [47:0] C_in; + wire [47:0] PCIN_in; + wire [4:0] INMODE_in; + wire [8:0] OPMODE_in; + + assign ACIN_in = ACIN; + assign ALUMODE_in[0] = (ALUMODE[0] !== 1'bz) && (ALUMODE[0] ^ IS_ALUMODE_INVERTED_REG[0]); // rv 0 + assign ALUMODE_in[1] = (ALUMODE[1] !== 1'bz) && (ALUMODE[1] ^ IS_ALUMODE_INVERTED_REG[1]); // rv 0 + assign ALUMODE_in[2] = (ALUMODE[2] !== 1'bz) && (ALUMODE[2] ^ IS_ALUMODE_INVERTED_REG[2]); // rv 0 + assign ALUMODE_in[3] = (ALUMODE[3] !== 1'bz) && (ALUMODE[3] ^ IS_ALUMODE_INVERTED_REG[3]); // rv 0 + assign A_in[0] = (A[0] === 1'bz) || A[0]; // rv 1 + assign A_in[10] = (A[10] === 1'bz) || A[10]; // rv 1 + assign A_in[11] = (A[11] === 1'bz) || A[11]; // rv 1 + assign A_in[12] = (A[12] === 1'bz) || A[12]; // rv 1 + assign A_in[13] = (A[13] === 1'bz) || A[13]; // rv 1 + assign A_in[14] = (A[14] === 1'bz) || A[14]; // rv 1 + assign A_in[15] = (A[15] === 1'bz) || A[15]; // rv 1 + assign A_in[16] = (A[16] === 1'bz) || A[16]; // rv 1 + assign A_in[17] = (A[17] === 1'bz) || A[17]; // rv 1 + assign A_in[18] = (A[18] === 1'bz) || A[18]; // rv 1 + assign A_in[19] = (A[19] === 1'bz) || A[19]; // rv 1 + assign A_in[1] = (A[1] === 1'bz) || A[1]; // rv 1 + assign A_in[20] = (A[20] === 1'bz) || A[20]; // rv 1 + assign A_in[21] = (A[21] === 1'bz) || A[21]; // rv 1 + assign A_in[22] = (A[22] === 1'bz) || A[22]; // rv 1 + assign A_in[23] = (A[23] === 1'bz) || A[23]; // rv 1 + assign A_in[24] = (A[24] === 1'bz) || A[24]; // rv 1 + assign A_in[25] = (A[25] === 1'bz) || A[25]; // rv 1 + assign A_in[26] = (A[26] === 1'bz) || A[26]; // rv 1 + assign A_in[27] = (A[27] === 1'bz) || A[27]; // rv 1 + assign A_in[28] = (A[28] === 1'bz) || A[28]; // rv 1 + assign A_in[29] = (A[29] === 1'bz) || A[29]; // rv 1 + assign A_in[2] = (A[2] === 1'bz) || A[2]; // rv 1 + assign A_in[3] = (A[3] === 1'bz) || A[3]; // rv 1 + assign A_in[4] = (A[4] === 1'bz) || A[4]; // rv 1 + assign A_in[5] = (A[5] === 1'bz) || A[5]; // rv 1 + assign A_in[6] = (A[6] === 1'bz) || A[6]; // rv 1 + assign A_in[7] = (A[7] === 1'bz) || A[7]; // rv 1 + assign A_in[8] = (A[8] === 1'bz) || A[8]; // rv 1 + assign A_in[9] = (A[9] === 1'bz) || A[9]; // rv 1 + assign BCIN_in = BCIN; + assign B_in[0] = (B[0] === 1'bz) || B[0]; // rv 1 + assign B_in[10] = (B[10] === 1'bz) || B[10]; // rv 1 + assign B_in[11] = (B[11] === 1'bz) || B[11]; // rv 1 + assign B_in[12] = (B[12] === 1'bz) || B[12]; // rv 1 + assign B_in[13] = (B[13] === 1'bz) || B[13]; // rv 1 + assign B_in[14] = (B[14] === 1'bz) || B[14]; // rv 1 + assign B_in[15] = (B[15] === 1'bz) || B[15]; // rv 1 + assign B_in[16] = (B[16] === 1'bz) || B[16]; // rv 1 + assign B_in[17] = (B[17] === 1'bz) || B[17]; // rv 1 + assign B_in[1] = (B[1] === 1'bz) || B[1]; // rv 1 + assign B_in[2] = (B[2] === 1'bz) || B[2]; // rv 1 + assign B_in[3] = (B[3] === 1'bz) || B[3]; // rv 1 + assign B_in[4] = (B[4] === 1'bz) || B[4]; // rv 1 + assign B_in[5] = (B[5] === 1'bz) || B[5]; // rv 1 + assign B_in[6] = (B[6] === 1'bz) || B[6]; // rv 1 + assign B_in[7] = (B[7] === 1'bz) || B[7]; // rv 1 + assign B_in[8] = (B[8] === 1'bz) || B[8]; // rv 1 + assign B_in[9] = (B[9] === 1'bz) || B[9]; // rv 1 + assign CARRYCASCIN_in = CARRYCASCIN; + assign CARRYINSEL_in[0] = (CARRYINSEL[0] !== 1'bz) && CARRYINSEL[0]; // rv 0 + assign CARRYINSEL_in[1] = (CARRYINSEL[1] !== 1'bz) && CARRYINSEL[1]; // rv 0 + assign CARRYINSEL_in[2] = (CARRYINSEL[2] !== 1'bz) && CARRYINSEL[2]; // rv 0 + assign CARRYIN_in = (CARRYIN !== 1'bz) && (CARRYIN ^ IS_CARRYIN_INVERTED_REG); // rv 0 + assign CEA1_in = (CEA1 !== 1'bz) && CEA1; // rv 0 + assign CEA2_in = (CEA2 !== 1'bz) && CEA2; // rv 0 + assign CEAD_in = (CEAD !== 1'bz) && CEAD; // rv 0 + assign CEALUMODE_in = (CEALUMODE !== 1'bz) && CEALUMODE; // rv 0 + assign CEB1_in = (CEB1 !== 1'bz) && CEB1; // rv 0 + assign CEB2_in = (CEB2 !== 1'bz) && CEB2; // rv 0 + assign CECARRYIN_in = (CECARRYIN !== 1'bz) && CECARRYIN; // rv 0 + assign CECTRL_in = (CECTRL !== 1'bz) && CECTRL; // rv 0 + assign CEC_in = (CEC !== 1'bz) && CEC; // rv 0 + assign CED_in = (CED !== 1'bz) && CED; // rv 0 + assign CEINMODE_in = CEINMODE; + assign CEM_in = (CEM !== 1'bz) && CEM; // rv 0 + assign CEP_in = (CEP !== 1'bz) && CEP; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign C_in[0] = (C[0] === 1'bz) || C[0]; // rv 1 + assign C_in[10] = (C[10] === 1'bz) || C[10]; // rv 1 + assign C_in[11] = (C[11] === 1'bz) || C[11]; // rv 1 + assign C_in[12] = (C[12] === 1'bz) || C[12]; // rv 1 + assign C_in[13] = (C[13] === 1'bz) || C[13]; // rv 1 + assign C_in[14] = (C[14] === 1'bz) || C[14]; // rv 1 + assign C_in[15] = (C[15] === 1'bz) || C[15]; // rv 1 + assign C_in[16] = (C[16] === 1'bz) || C[16]; // rv 1 + assign C_in[17] = (C[17] === 1'bz) || C[17]; // rv 1 + assign C_in[18] = (C[18] === 1'bz) || C[18]; // rv 1 + assign C_in[19] = (C[19] === 1'bz) || C[19]; // rv 1 + assign C_in[1] = (C[1] === 1'bz) || C[1]; // rv 1 + assign C_in[20] = (C[20] === 1'bz) || C[20]; // rv 1 + assign C_in[21] = (C[21] === 1'bz) || C[21]; // rv 1 + assign C_in[22] = (C[22] === 1'bz) || C[22]; // rv 1 + assign C_in[23] = (C[23] === 1'bz) || C[23]; // rv 1 + assign C_in[24] = (C[24] === 1'bz) || C[24]; // rv 1 + assign C_in[25] = (C[25] === 1'bz) || C[25]; // rv 1 + assign C_in[26] = (C[26] === 1'bz) || C[26]; // rv 1 + assign C_in[27] = (C[27] === 1'bz) || C[27]; // rv 1 + assign C_in[28] = (C[28] === 1'bz) || C[28]; // rv 1 + assign C_in[29] = (C[29] === 1'bz) || C[29]; // rv 1 + assign C_in[2] = (C[2] === 1'bz) || C[2]; // rv 1 + assign C_in[30] = (C[30] === 1'bz) || C[30]; // rv 1 + assign C_in[31] = (C[31] === 1'bz) || C[31]; // rv 1 + assign C_in[32] = (C[32] === 1'bz) || C[32]; // rv 1 + assign C_in[33] = (C[33] === 1'bz) || C[33]; // rv 1 + assign C_in[34] = (C[34] === 1'bz) || C[34]; // rv 1 + assign C_in[35] = (C[35] === 1'bz) || C[35]; // rv 1 + assign C_in[36] = (C[36] === 1'bz) || C[36]; // rv 1 + assign C_in[37] = (C[37] === 1'bz) || C[37]; // rv 1 + assign C_in[38] = (C[38] === 1'bz) || C[38]; // rv 1 + assign C_in[39] = (C[39] === 1'bz) || C[39]; // rv 1 + assign C_in[3] = (C[3] === 1'bz) || C[3]; // rv 1 + assign C_in[40] = (C[40] === 1'bz) || C[40]; // rv 1 + assign C_in[41] = (C[41] === 1'bz) || C[41]; // rv 1 + assign C_in[42] = (C[42] === 1'bz) || C[42]; // rv 1 + assign C_in[43] = (C[43] === 1'bz) || C[43]; // rv 1 + assign C_in[44] = (C[44] === 1'bz) || C[44]; // rv 1 + assign C_in[45] = (C[45] === 1'bz) || C[45]; // rv 1 + assign C_in[46] = (C[46] === 1'bz) || C[46]; // rv 1 + assign C_in[47] = (C[47] === 1'bz) || C[47]; // rv 1 + assign C_in[4] = (C[4] === 1'bz) || C[4]; // rv 1 + assign C_in[5] = (C[5] === 1'bz) || C[5]; // rv 1 + assign C_in[6] = (C[6] === 1'bz) || C[6]; // rv 1 + assign C_in[7] = (C[7] === 1'bz) || C[7]; // rv 1 + assign C_in[8] = (C[8] === 1'bz) || C[8]; // rv 1 + assign C_in[9] = (C[9] === 1'bz) || C[9]; // rv 1 + assign D_in[0] = (D[0] !== 1'bz) && D[0]; // rv 0 + assign D_in[10] = (D[10] !== 1'bz) && D[10]; // rv 0 + assign D_in[11] = (D[11] !== 1'bz) && D[11]; // rv 0 + assign D_in[12] = (D[12] !== 1'bz) && D[12]; // rv 0 + assign D_in[13] = (D[13] !== 1'bz) && D[13]; // rv 0 + assign D_in[14] = (D[14] !== 1'bz) && D[14]; // rv 0 + assign D_in[15] = (D[15] !== 1'bz) && D[15]; // rv 0 + assign D_in[16] = (D[16] !== 1'bz) && D[16]; // rv 0 + assign D_in[17] = (D[17] !== 1'bz) && D[17]; // rv 0 + assign D_in[18] = (D[18] !== 1'bz) && D[18]; // rv 0 + assign D_in[19] = (D[19] !== 1'bz) && D[19]; // rv 0 + assign D_in[1] = (D[1] !== 1'bz) && D[1]; // rv 0 + assign D_in[20] = (D[20] !== 1'bz) && D[20]; // rv 0 + assign D_in[21] = (D[21] !== 1'bz) && D[21]; // rv 0 + assign D_in[22] = (D[22] !== 1'bz) && D[22]; // rv 0 + assign D_in[23] = (D[23] !== 1'bz) && D[23]; // rv 0 + assign D_in[24] = (D[24] !== 1'bz) && D[24]; // rv 0 + assign D_in[25] = (D[25] !== 1'bz) && D[25]; // rv 0 + assign D_in[26] = (D[26] !== 1'bz) && D[26]; // rv 0 + assign D_in[2] = (D[2] !== 1'bz) && D[2]; // rv 0 + assign D_in[3] = (D[3] !== 1'bz) && D[3]; // rv 0 + assign D_in[4] = (D[4] !== 1'bz) && D[4]; // rv 0 + assign D_in[5] = (D[5] !== 1'bz) && D[5]; // rv 0 + assign D_in[6] = (D[6] !== 1'bz) && D[6]; // rv 0 + assign D_in[7] = (D[7] !== 1'bz) && D[7]; // rv 0 + assign D_in[8] = (D[8] !== 1'bz) && D[8]; // rv 0 + assign D_in[9] = (D[9] !== 1'bz) && D[9]; // rv 0 + assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0 + assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0 + assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0 + assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0 + assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0 + assign MULTSIGNIN_in = MULTSIGNIN; + assign OPMODE_in[0] = (OPMODE[0] !== 1'bz) && (OPMODE[0] ^ IS_OPMODE_INVERTED_REG[0]); // rv 0 + assign OPMODE_in[1] = (OPMODE[1] !== 1'bz) && (OPMODE[1] ^ IS_OPMODE_INVERTED_REG[1]); // rv 0 + assign OPMODE_in[2] = (OPMODE[2] !== 1'bz) && (OPMODE[2] ^ IS_OPMODE_INVERTED_REG[2]); // rv 0 + assign OPMODE_in[3] = (OPMODE[3] !== 1'bz) && (OPMODE[3] ^ IS_OPMODE_INVERTED_REG[3]); // rv 0 + assign OPMODE_in[4] = (OPMODE[4] !== 1'bz) && (OPMODE[4] ^ IS_OPMODE_INVERTED_REG[4]); // rv 0 + assign OPMODE_in[5] = (OPMODE[5] !== 1'bz) && (OPMODE[5] ^ IS_OPMODE_INVERTED_REG[5]); // rv 0 + assign OPMODE_in[6] = (OPMODE[6] !== 1'bz) && (OPMODE[6] ^ IS_OPMODE_INVERTED_REG[6]); // rv 0 + assign OPMODE_in[7] = (OPMODE[7] !== 1'bz) && (OPMODE[7] ^ IS_OPMODE_INVERTED_REG[7]); // rv 0 + assign OPMODE_in[8] = (OPMODE[8] !== 1'bz) && (OPMODE[8] ^ IS_OPMODE_INVERTED_REG[8]); // rv 0 + assign PCIN_in = PCIN; + assign RSTALLCARRYIN_in = (RSTALLCARRYIN !== 1'bz) && (RSTALLCARRYIN ^ IS_RSTALLCARRYIN_INVERTED_REG); // rv 0 + assign RSTALUMODE_in = (RSTALUMODE !== 1'bz) && (RSTALUMODE ^ IS_RSTALUMODE_INVERTED_REG); // rv 0 + assign RSTA_in = (RSTA !== 1'bz) && (RSTA ^ IS_RSTA_INVERTED_REG); // rv 0 + assign RSTB_in = (RSTB !== 1'bz) && (RSTB ^ IS_RSTB_INVERTED_REG); // rv 0 + assign RSTCTRL_in = (RSTCTRL !== 1'bz) && (RSTCTRL ^ IS_RSTCTRL_INVERTED_REG); // rv 0 + assign RSTC_in = (RSTC !== 1'bz) && (RSTC ^ IS_RSTC_INVERTED_REG); // rv 0 + assign RSTD_in = (RSTD !== 1'bz) && (RSTD ^ IS_RSTD_INVERTED_REG); // rv 0 + assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE ^ IS_RSTINMODE_INVERTED_REG); // rv 0 + assign RSTM_in = (RSTM !== 1'bz) && (RSTM ^ IS_RSTM_INVERTED_REG); // rv 0 + assign RSTP_in = (RSTP !== 1'bz) && (RSTP ^ IS_RSTP_INVERTED_REG); // rv 0 + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign ACASCREG_BIN = ACASCREG_REG[1:0]; + + assign ADREG_BIN = ADREG_REG[0]; + + assign ALUMODEREG_BIN = ALUMODEREG_REG[0]; + + assign AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + assign AREG_BIN = AREG_REG[1:0]; + + assign AUTORESET_PATDET_BIN = + (AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET : + (AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH : + (AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH : + AUTORESET_PATDET_NO_RESET; + + assign AUTORESET_PRIORITY_BIN = + (AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET : + (AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP : + AUTORESET_PRIORITY_RESET; + + assign A_INPUT_BIN = + (A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT : + (A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE : + A_INPUT_DIRECT; + + assign BCASCREG_BIN = BCASCREG_REG[1:0]; + + assign BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + assign BREG_BIN = BREG_REG[1:0]; + + assign B_INPUT_BIN = + (B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT : + (B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE : + B_INPUT_DIRECT; + + assign CARRYINREG_BIN = CARRYINREG_REG[0]; + + assign CARRYINSELREG_BIN = CARRYINSELREG_REG[0]; + + assign CREG_BIN = CREG_REG[0]; + + assign DREG_BIN = DREG_REG[0]; + + assign INMODEREG_BIN = INMODEREG_REG[0]; + + assign MREG_BIN = MREG_REG[0]; + + assign OPMODEREG_BIN = OPMODEREG_REG[0]; + + assign PREADDINSEL_BIN = + (PREADDINSEL_REG == "A") ? PREADDINSEL_A : + (PREADDINSEL_REG == "B") ? PREADDINSEL_B : + PREADDINSEL_A; + + assign PREG_BIN = PREG_REG[0]; + + assign SEL_MASK_BIN = + (SEL_MASK_REG == "MASK") ? SEL_MASK_MASK : + (SEL_MASK_REG == "C") ? SEL_MASK_C : + (SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 : + (SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 : + SEL_MASK_MASK; + + assign SEL_PATTERN_BIN = + (SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN : + (SEL_PATTERN_REG == "C") ? SEL_PATTERN_C : + SEL_PATTERN_PATTERN; + + assign USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + + assign USE_PATTERN_DETECT_BIN = + (USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET : + (USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET : + USE_PATTERN_DETECT_NO_PATDET; + + assign USE_SIMD_BIN = + (USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 : + (USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 : + (USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 : + USE_SIMD_ONE48; + + assign USE_WIDEXOR_BIN = + (USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE : + (USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE : + USE_WIDEXOR_FALSE; + + assign XORSIMD_BIN = + (XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 : + (XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 : + XORSIMD_XOR24_48_96; + +`else +always @(trig_attr) begin +#1; + ACASCREG_BIN = ACASCREG_REG[1:0]; + + ADREG_BIN = ADREG_REG[0]; + + ALUMODEREG_BIN = ALUMODEREG_REG[0]; + + AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + AREG_BIN = AREG_REG[1:0]; + + AUTORESET_PATDET_BIN = + (AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET : + (AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH : + (AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH : + AUTORESET_PATDET_NO_RESET; + + AUTORESET_PRIORITY_BIN = + (AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET : + (AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP : + AUTORESET_PRIORITY_RESET; + + A_INPUT_BIN = + (A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT : + (A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE : + A_INPUT_DIRECT; + + BCASCREG_BIN = BCASCREG_REG[1:0]; + + BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + BREG_BIN = BREG_REG[1:0]; + + B_INPUT_BIN = + (B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT : + (B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE : + B_INPUT_DIRECT; + + CARRYINREG_BIN = CARRYINREG_REG[0]; + + CARRYINSELREG_BIN = CARRYINSELREG_REG[0]; + + CREG_BIN = CREG_REG[0]; + + DREG_BIN = DREG_REG[0]; + + INMODEREG_BIN = INMODEREG_REG[0]; + + MREG_BIN = MREG_REG[0]; + + OPMODEREG_BIN = OPMODEREG_REG[0]; + + PREADDINSEL_BIN = + (PREADDINSEL_REG == "A") ? PREADDINSEL_A : + (PREADDINSEL_REG == "B") ? PREADDINSEL_B : + PREADDINSEL_A; + + PREG_BIN = PREG_REG[0]; + + SEL_MASK_BIN = + (SEL_MASK_REG == "MASK") ? SEL_MASK_MASK : + (SEL_MASK_REG == "C") ? SEL_MASK_C : + (SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 : + (SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 : + SEL_MASK_MASK; + + SEL_PATTERN_BIN = + (SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN : + (SEL_PATTERN_REG == "C") ? SEL_PATTERN_C : + SEL_PATTERN_PATTERN; + + USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + + USE_PATTERN_DETECT_BIN = + (USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET : + (USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET : + USE_PATTERN_DETECT_NO_PATDET; + + USE_SIMD_BIN = + (USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 : + (USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 : + (USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 : + USE_SIMD_ONE48; + + USE_WIDEXOR_BIN = + (USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE : + (USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE : + USE_WIDEXOR_FALSE; + + XORSIMD_BIN = + (XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 : + (XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 : + XORSIMD_XOR24_48_96; + +end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ACASCREG_REG != 1) && + (ACASCREG_REG != 0) && + (ACASCREG_REG != 2))) begin + $display("Error: [Unisim %s-101] ACASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, ACASCREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ADREG_REG != 1) && + (ADREG_REG != 0))) begin + $display("Error: [Unisim %s-102] ADREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ADREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALUMODEREG_REG != 1) && + (ALUMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-103] ALUMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ALUMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AMULTSEL_REG != "A") && + (AMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-104] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AREG_REG != 1) && + (AREG_REG != 0) && + (AREG_REG != 2))) begin + $display("Error: [Unisim %s-105] AREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, AREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AUTORESET_PATDET_REG != "NO_RESET") && + (AUTORESET_PATDET_REG != "RESET_MATCH") && + (AUTORESET_PATDET_REG != "RESET_NOT_MATCH"))) begin + $display("Error: [Unisim %s-106] AUTORESET_PATDET attribute is set to %s. Legal values for this attribute are NO_RESET, RESET_MATCH or RESET_NOT_MATCH. Instance: %m", MODULE_NAME, AUTORESET_PATDET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AUTORESET_PRIORITY_REG != "RESET") && + (AUTORESET_PRIORITY_REG != "CEP"))) begin + $display("Error: [Unisim %s-107] AUTORESET_PRIORITY attribute is set to %s. Legal values for this attribute are RESET or CEP. Instance: %m", MODULE_NAME, AUTORESET_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((A_INPUT_REG != "DIRECT") && + (A_INPUT_REG != "CASCADE"))) begin + $display("Error: [Unisim %s-108] A_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, A_INPUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BCASCREG_REG != 1) && + (BCASCREG_REG != 0) && + (BCASCREG_REG != 2))) begin + $display("Error: [Unisim %s-109] BCASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BCASCREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BMULTSEL_REG != "B") && + (BMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-110] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BREG_REG != 1) && + (BREG_REG != 0) && + (BREG_REG != 2))) begin + $display("Error: [Unisim %s-111] BREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((B_INPUT_REG != "DIRECT") && + (B_INPUT_REG != "CASCADE"))) begin + $display("Error: [Unisim %s-112] B_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, B_INPUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CARRYINREG_REG != 1) && + (CARRYINREG_REG != 0))) begin + $display("Error: [Unisim %s-113] CARRYINREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CARRYINSELREG_REG != 1) && + (CARRYINSELREG_REG != 0))) begin + $display("Error: [Unisim %s-114] CARRYINSELREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINSELREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CREG_REG != 1) && + (CREG_REG != 0))) begin + $display("Error: [Unisim %s-115] CREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DREG_REG != 1) && + (DREG_REG != 0))) begin + $display("Error: [Unisim %s-116] DREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((INMODEREG_REG != 1) && + (INMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-117] INMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, INMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MREG_REG != 1) && + (MREG_REG != 0))) begin + $display("Error: [Unisim %s-134] MREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, MREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OPMODEREG_REG != 1) && + (OPMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-135] OPMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, OPMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREADDINSEL_REG != "A") && + (PREADDINSEL_REG != "B"))) begin + $display("Error: [Unisim %s-137] PREADDINSEL attribute is set to %s. Legal values for this attribute are A or B. Instance: %m", MODULE_NAME, PREADDINSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREG_REG != 1) && + (PREG_REG != 0))) begin + $display("Error: [Unisim %s-138] PREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, PREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SEL_MASK_REG != "MASK") && + (SEL_MASK_REG != "C") && + (SEL_MASK_REG != "ROUNDING_MODE1") && + (SEL_MASK_REG != "ROUNDING_MODE2"))) begin + $display("Error: [Unisim %s-140] SEL_MASK attribute is set to %s. Legal values for this attribute are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2. Instance: %m", MODULE_NAME, SEL_MASK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SEL_PATTERN_REG != "PATTERN") && + (SEL_PATTERN_REG != "C"))) begin + $display("Error: [Unisim %s-141] SEL_PATTERN attribute is set to %s. Legal values for this attribute are PATTERN or C. Instance: %m", MODULE_NAME, SEL_PATTERN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_MULT_REG != "MULTIPLY") && + (USE_MULT_REG != "DYNAMIC") && + (USE_MULT_REG != "NONE"))) begin + $display("Error: [Unisim %s-142] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_PATTERN_DETECT_REG != "NO_PATDET") && + (USE_PATTERN_DETECT_REG != "PATDET"))) begin + $display("Error: [Unisim %s-143] USE_PATTERN_DETECT attribute is set to %s. Legal values for this attribute are NO_PATDET or PATDET. Instance: %m", MODULE_NAME, USE_PATTERN_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_SIMD_REG != "ONE48") && + (USE_SIMD_REG != "FOUR12") && + (USE_SIMD_REG != "TWO24"))) begin + $display("Error: [Unisim %s-144] USE_SIMD attribute is set to %s. Legal values for this attribute are ONE48, FOUR12 or TWO24. Instance: %m", MODULE_NAME, USE_SIMD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_WIDEXOR_REG != "FALSE") && + (USE_WIDEXOR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-145] USE_WIDEXOR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_WIDEXOR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XORSIMD_REG != "XOR24_48_96") && + (XORSIMD_REG != "XOR12"))) begin + $display("Error: [Unisim %s-146] XORSIMD attribute is set to %s. Legal values for this attribute are XOR24_48_96 or XOR12. Instance: %m", MODULE_NAME, XORSIMD_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +// begin behavioral model + + always @(trig_attr) begin + #1; + case (AREG_REG) + 0, 1 : if (AREG_REG != ACASCREG_REG) begin + $display("Error: [Unisim %s-2] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 0 or 1, ACASCREG must be set to the same value. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG); + attr_err = 1'b1; + end + 2 : if (ACASCREG_REG == 0) begin + $display("Error: [Unisim %s-3] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 2, ACASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG); + attr_err = 1'b1; + end + endcase + + case (BREG_REG) + 0, 1 : if (BREG_REG != BCASCREG_REG) begin + $display("Error: [Unisim %s-4] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 0 or 1, BCASCREG must be set to the same value. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG); + attr_err = 1'b1; + end + 2 : if (BCASCREG_REG == 0) begin + $display("Error: [Unisim %s-5] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 2, BCASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG); + attr_err = 1'b1; + end + endcase + + if (attr_err == 1'b1) #1 $finish; + end + + always @(trig_attr) begin + #1; + if ((USE_MULT_REG == "NONE") && (MREG_REG !== 0)) begin + $display("Error : [Unisim %s-6] : Attribute USE_MULT is set to \"NONE\" and MREG is set to %d. MREG must be set to 0 when the multiplier is not used. Instance %m", MODULE_NAME, MREG_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +// Connections between atoms + wire [44:0] U_DATA; + wire [44:0] V_DATA; + reg [26:0] A2A1; + reg [17:0] B2B1; + wire AMULT26_in; + wire BMULT17_in; + wire ALUMODE10_in; + wire CCOUT_in; + wire MULTSIGN_ALU_in; + wire P_FDBK_47_in; + wire [26:0] AD_DATA; + wire [26:0] AD_in; + wire [26:0] D_DATA; + wire [26:0] PREADD_AB; + wire [3:0] COUT_in; + wire [44:0] U_in; + wire [44:0] V_in; + wire [44:0] U_DATA_in; + wire [44:0] V_DATA_in; + wire [47:0] ALU_OUT_in; + wire [47:0] C_DATA_in; + wire [47:0] P_FDBK_in; + wire [7:0] XOR_MX_in; + +// DSP_ALU wires + localparam MAX_ALU_FULL = 48; + localparam MAX_CARRYOUT = 4; + localparam A_WIDTH = 30; + localparam B_WIDTH = 18; + localparam C_WIDTH = 48; + localparam D_WIDTH = 27; + localparam M_WIDTH = 45; + localparam P_WIDTH = 48; + reg cci_drc_msg; + reg cis_drc_msg; + + + wire CARRYIN_mux; + reg CARRYIN_reg; + reg [3:0] ALUMODE_reg; + reg [2:0] CARRYINSEL_mux; + reg [2:0] CARRYINSEL_reg; + reg [8:0] OPMODE_mux; + reg [8:0] OPMODE_reg; + + wire [47:0] x_mac_cascd; + + reg [47:0] wmux; + reg [47:0] xmux; + reg [47:0] ymux; + reg [47:0] zmux; + wire [47:0] z_optinv; + + wire cin; + reg cin_b; + wire rst_carryin_g; + reg qmultcarryin; + + wire c_mult; + wire ce_m_g; + wire d_carryin_int; + wire dr_carryin_int; + wire multcarryin_data; + + reg invalid_opmode; + reg opmode_valid_flag_dal; // used in OPMODE DRC + reg ping_opmode_drc_check; + + wire [MAX_ALU_FULL-1:0] co; + wire [MAX_ALU_FULL-1:0] s; + wire [MAX_ALU_FULL-1:0] comux; + wire [MAX_ALU_FULL-1:0] comux_w; + wire [MAX_ALU_FULL-1:0] comux4simd; + wire [MAX_ALU_FULL-1:0] smux; + wire [MAX_ALU_FULL-1:0] smux_w; + wire [MAX_ALU_FULL:0] a_int; + wire [12:0] s0; + wire cout0; + wire intc1; + wire co12_lsb; + wire [12:0] s1; + wire cout1; + wire intc2; + wire co24_lsb; + wire [12:0] s2; + wire cout2; + wire intc3; + wire co36_lsb; + wire [13:0] s3; + wire cout3; + wire cout4; + wire xor_12a; + wire xor_12b; + wire xor_12c; + wire xor_12d; + wire xor_12e; + wire xor_12f; + wire xor_12g; + wire xor_12h; + wire xor_24a; + wire xor_24b; + wire xor_24c; + wire xor_24d; + wire xor_48a; + wire xor_48b; + wire xor_96; + wire cout_0; + wire cout_1; + wire cout_2; + wire cout_3; + wire mult_or_logic; + +// DSP_A_B_DATA wires + reg [29:0] A1_reg; + reg [29:0] A2_reg; + wire [A_WIDTH-1:0] A_ALU; + reg [17:0] B2_reg; + reg [B_WIDTH-1:0] B1_DATA_out; + wire [B_WIDTH-1:0] B2_DATA; + wire [B_WIDTH-1:0] B_ALU; + +// DSP_C_DATA wires + reg [C_WIDTH-1:0] C_reg; + +// DSP_MULTIPLIER wires + reg [17:0] b_mult_mux; + reg [26:0] a_mult_mux; + reg [M_WIDTH-1:0] mult; + reg [M_WIDTH-2:0] ps_u_mask; + reg [M_WIDTH-2:0] ps_v_mask; + +// DSP_M_DATA wires + reg [M_WIDTH-1:0] U_DATA_reg; + reg [M_WIDTH-1:0] V_DATA_reg; + +// DSP_OUTPUT wires + wire the_auto_reset_patdet; + wire auto_reset_pri; + wire [47:0] the_mask; + wire [47:0] the_pattern; + reg opmode_valid_flag_dou = 1'b1; // TODO + + reg [3:0] COUT_reg; + reg ALUMODE10_reg; + wire ALUMODE10_mux; + reg MULTSIGN_ALU_reg; + reg [47:0] ALU_OUT_reg; + reg [7:0] XOR_MX_reg; + + wire pdet_o; + wire pdetb_o; + wire pdet_o_mux; + wire pdetb_o_mux; + wire overflow_data; + wire underflow_data; + reg pdet_o_reg1; + reg pdet_o_reg2; + reg pdetb_o_reg1; + reg pdetb_o_reg2; + +// DSP_PREADD wires + wire [26:0] D_DATA_mux; + +// DSP_PREADD_DATA wires + wire [4:0] INMODE_mux; + reg [4:0] INMODE_reg; + reg [D_WIDTH-1:0] AD_DATA_reg; + reg [D_WIDTH-1:0] D_DATA_reg; + +// atom interconnect + assign U_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? U_DATA : 45'h100000000000; + assign V_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? V_DATA : 45'h100000000000; + reg [3:0] ALUMODE_DATA; + reg DREG_INT; + reg ADREG_INT; + + +// initialize regs +`ifndef XIL_XECLIB +initial begin + cci_drc_msg = 1'b0; + cis_drc_msg = 1'b0; + CARRYIN_reg = 1'b0; + ALUMODE_reg = 4'b0; + CARRYINSEL_mux = 3'b0; + CARRYINSEL_reg = 3'b0; + OPMODE_mux = 9'b0; + OPMODE_reg = 9'b0; + wmux = 48'b0; + xmux = 48'b0; + ymux = 48'b0; + zmux = 48'b0; + cin_b = 1'b0; + qmultcarryin = 1'b0; + invalid_opmode = 1'b1; + opmode_valid_flag_dal = 1'b1; + ping_opmode_drc_check = 1'b0; + A1_reg = 30'b0; + A2_reg = 30'b0; + B2_reg = 18'b0; + B1_DATA_out = {B_WIDTH{1'b0}}; + C_reg = {C_WIDTH{1'b0}}; + ps_u_mask = 44'h55555555555; + ps_v_mask = 44'haaaaaaaaaaa; + U_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}}; + V_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}}; + COUT_reg = 4'b0000; + ALUMODE10_reg = 1'b0; + MULTSIGN_ALU_reg = 1'b0; + ALU_OUT_reg = 48'b0; + XOR_MX_reg = 8'b0; + pdet_o_reg1 = 1'b0; + pdet_o_reg2 = 1'b0; + pdetb_o_reg1 = 1'b0; + pdetb_o_reg2 = 1'b0; + INMODE_reg = 5'b0; + AD_DATA_reg = {D_WIDTH{1'b0}}; + D_DATA_reg = {D_WIDTH{1'b0}}; +end +`endif + +// DSP_ALU +//*** W mux NB + always @(OPMODE_mux[8:7] or P_FDBK_in or RND_REG or C_DATA_in) + case (OPMODE_mux[8:7]) + 2'b00 : wmux = 48'b0; + 2'b01 : wmux = P_FDBK_in; + 2'b10 : wmux = RND_REG; + 2'b11 : wmux = C_DATA_in; + default : wmux = {48{1'bx}}; + endcase + +// To support MAC-cascade add multsignin to bit 1 of X + assign x_mac_cascd = (OPMODE_mux[6:4] == 3'b100) ? {{46{1'b0}},MULTSIGNIN_in,1'b0} : {48{1'b0}}; + +//*** X mux NB + always @(U_DATA_in or P_FDBK_in or A_ALU or B_ALU or OPMODE_mux[1:0] or x_mac_cascd) + case (OPMODE_mux[1:0]) + 2'b00 : xmux = x_mac_cascd; + 2'b01 : xmux = {{3{U_DATA_in[44]}}, U_DATA_in}; + 2'b10 : xmux = P_FDBK_in; + 2'b11 : xmux = {A_ALU, B_ALU}; + default : xmux = {48{1'bx}}; + endcase + +//*** Y mux NB + always @(OPMODE_mux[3:2] or V_DATA_in or C_DATA_in) + case (OPMODE_mux[3:2]) + 2'b00 : ymux = 48'b0; + 2'b01 : ymux = {{3{1'b0}}, V_DATA_in}; + 2'b10 : ymux = {48{1'b1}}; + 2'b11 : ymux = C_DATA_in; + default : ymux = {48{1'bx}}; + endcase + +//*** Z mux NB + always @(OPMODE_mux[6:4] or PCIN_in or P_FDBK_in or C_DATA_in or P_FDBK_47_in) + casex (OPMODE_mux[6:4]) + 3'b000 : zmux = 48'b0; + 3'b001 : zmux = PCIN_in; + 3'b010 : zmux = P_FDBK_in; + 3'b011 : zmux = C_DATA_in; + 3'b100 : zmux = P_FDBK_in; + 3'b101 : zmux = {{9{PCIN_in[47]}}, {8{PCIN_in[47]}}, PCIN_in[47:17]}; + 3'b11x : zmux = {{9{P_FDBK_47_in}}, {8{P_FDBK_in[47]}}, P_FDBK_in[47:17]}; + default : zmux = {48{1'bx}}; + endcase + +//********************************************************* +//*** CARRYINSEL and OPMODE with 1 level of register +//********************************************************* + always @(posedge CLK_in) begin + if (RSTCTRL_in || glblGSR) begin + OPMODE_reg <= 9'b0; + end + else if (CECTRL_in) begin + OPMODE_reg <= OPMODE_in; + end + end + + always @(posedge CLK_in) begin + if (RSTCTRL_in || glblGSR) begin + CARRYINSEL_reg <= 3'b0; + end + else if (CECTRL_in) begin + CARRYINSEL_reg <= CARRYINSEL_in; + end + end + + always @(*) CARRYINSEL_mux = (CARRYINSELREG_BIN == 1'b1) ? CARRYINSEL_reg : CARRYINSEL_in; + + always @(*) begin + if (OPMODEREG_BIN == 1'b1) OPMODE_mux = OPMODE_reg; + else OPMODE_mux = OPMODE_in; + end + + always @(CARRYINSEL_mux or CARRYCASCIN_in or MULTSIGNIN_in or OPMODE_mux) begin + if (CARRYINSEL_mux == 3'b010) begin + if (!((MULTSIGNIN_in === 1'bx) || (cci_drc_msg == 1'b1) || + ((OPMODE_mux == 9'b001001000) && !(MULTSIGNIN_in === 1'bx)) || + ((MULTSIGNIN_in == 1'b0) && (CARRYCASCIN_in == 1'b0)))) begin + $display("DRC warning : [Unisim %s-7] CARRYCASCIN can only be used in the current %s if the previous %s is performing a two input ADD or SUBRTACT operation or the current %s is configured in the MAC extend opmode 7'b1001000 at %.3f ns. Instance %m\n", MODULE_NAME, MODULE_NAME, MODULE_NAME, MODULE_NAME, $time/1000.0); +// CR 619940 -- Enhanced DRC warning + $display("The simulation model does not know the placement of the %s slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the %s slices and ensure that these warnings are not being breached\n", MODULE_NAME, MODULE_NAME); + cci_drc_msg = 1'b1; + end + if (!((MULTSIGNIN_in === 1'bx) || (OPMODE_mux[3:0] != 4'b0101))) begin + $display("DRC warning : [Unisim %s-10] CARRYINSEL is set to 010 with OPMODE set to multiplication (xxx0101). This is an illegal mode and may show deviation between simulation results and hardware behavior. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0); + end + if (!((MULTSIGNIN_in === 1'bx) || (cis_drc_msg == 1'b1) || + (OPMODEREG_BIN == 1'b1))) begin + $display("DRC warning : [Unisim %s-11] CARRYINSEL is set to 010 with OPMODEREG set to 0. This causes unknown values after reset occurs. It is suggested to use OPMODEREG = 1 when cascading large adders. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0); + cis_drc_msg = 1'b1; + end + end + end + +//********************************************************* +//*** ALUMODE with 1 level of register +//********************************************************* + always @(posedge CLK_in) begin + if (RSTALUMODE_in || glblGSR) + ALUMODE_reg <= 4'b0; + else if (CEALUMODE_in) + ALUMODE_reg <= ALUMODE_in; + end + + always @(*) ALUMODE_DATA = (ALUMODEREG_BIN == 1'b1) ? ALUMODE_reg : ALUMODE_in; + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + +// needs PREG from output block +// ~2000 lines code - skip for now - copy/rework from DSP48E1. + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + +// ADDSUB block - first stage of ALU develops sums and carries for Final Adder +// Invert Z for subtract operation using alumode<0> + assign z_optinv = {48{ALUMODE_DATA[0]}} ^ zmux; + +// Add W, X, Y, Z carry-save style; basically full adder logic below + assign co = ((xmux & ymux)|(z_optinv & ymux)|(xmux & z_optinv)); +// s has a fan-out of 2 (1) FA with W (2) second leg of XOR tree + assign s = (z_optinv^xmux^ymux); + +// Mux S and CO to do 2 operands logic operations +// S = produce XOR/XNOR, NOT functions +// CO = produce AND/NAND, OR/NOR functions + assign comux = ALUMODE_DATA[2] ? 0 : co; + assign smux = ALUMODE_DATA[3] ? co : s; + +// Carry mux to handle SIMD mode +// SIMD must be used here since addition of W requires carry propogation + assign comux4simd = { + comux[47:36], + comux[35]&&(USE_SIMD_BIN != USE_SIMD_FOUR12), + comux[34:24], + comux[23]&&(USE_SIMD_BIN == USE_SIMD_ONE48), + comux[22:12], + comux[11]&&(USE_SIMD_BIN != USE_SIMD_FOUR12), + comux[10:0] + }; + +// FA to combine W-mux with s and co +// comux must be shifted to properly reflect carry operation + assign smux_w = smux ^ {comux4simd[46:0],1'b0} ^ wmux; + assign comux_w = ((smux & {comux4simd[46:0],1'b0}) | + (wmux & {comux4simd[46:0],1'b0}) | + (smux & wmux)); + +// alumode10 indicates a subtraction, used to correct carryout polarity + assign ALUMODE10_in = (ALUMODE_DATA[0] & ALUMODE_DATA[1]); + +// prepare data for Final Adder +// a[0] is in fact the cin bit, adder inputs: a[48:1], b[47:0], cin= a[0] + assign a_int = {comux_w, cin}; +// assign b_int = smux_w; + +// FINAL ADDER - second stage develops final sums and carries + assign s0 = a_int[11:0] + smux_w[11:0]; + // invert if alumode10 + assign cout0 = ALUMODE10_in ^ (a_int[12] ^ s0[12] ^ comux[11]); + + // internal carry is zero'd out on mc_simd == 1 + assign intc1 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s0[12]; + // next lsb is zero'd out on mc_simd == 1 + assign co12_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[12]; + // + assign s1 = {a_int[23:13],co12_lsb} + smux_w[23:12] + intc1; + assign cout1 = ALUMODE10_in ^ (a_int[24] ^ s1[12] ^ comux[23]); + assign intc2 = (USE_SIMD_BIN == USE_SIMD_ONE48) && s1[12]; + assign co24_lsb = (USE_SIMD_BIN == USE_SIMD_ONE48) && a_int[24]; + // + assign s2 = {a_int[35:25],co24_lsb} + smux_w[35:24] + intc2; + assign cout2 = ALUMODE10_in ^ (a_int[36] ^ s2[12] ^ comux[35]); + assign intc3 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s2[12]; + assign co36_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[36]; + // + assign s3 = {a_int[48:37],co36_lsb} + {comux4simd[47],smux_w[47:36]} + intc3; + assign cout3 = ALUMODE10_in ^ s3[12]; + +// Not gated with alumode10 since used to propogate carry in wide multiply + assign cout4 = s3[13]; + +// Wide XOR + assign xor_12a = USE_WIDEXOR_BIN ? ^s[5:0] : 0; + assign xor_12b = USE_WIDEXOR_BIN ? ^s[11:6] : 0; + assign xor_12c = USE_WIDEXOR_BIN ? ^s[17:12] : 0; + assign xor_12d = USE_WIDEXOR_BIN ? ^s[23:18] : 0; + assign xor_12e = USE_WIDEXOR_BIN ? ^s[29:24] : 0; + assign xor_12f = USE_WIDEXOR_BIN ? ^s[35:30] : 0; + assign xor_12g = USE_WIDEXOR_BIN ? ^s[41:36] : 0; + assign xor_12h = USE_WIDEXOR_BIN ? ^s[47:42] : 0; + + assign xor_24a = xor_12a ^ xor_12b; + assign xor_24b = xor_12c ^ xor_12d; + assign xor_24c = xor_12e ^ xor_12f; + assign xor_24d = xor_12g ^ xor_12h; + + assign xor_48a = xor_24a ^ xor_24b; + assign xor_48b = xor_24c ^ xor_24d; + + assign xor_96 = xor_48a ^ xor_48b; + +// "X" carryout for multiply and logic operations + assign mult_or_logic = ((OPMODE_mux[3:0] == 4'b0101) || + (ALUMODE_DATA[3:2] != 2'b00)); +// allow carrycascout to not X in output atom +// assign cout_3 = mult_or_logic ? 1'bx : cout3; + assign cout_3 = cout3; + assign cout_2 = mult_or_logic ? 1'bx : cout2; + assign cout_1 = mult_or_logic ? 1'bx : cout1; + assign cout_0 = mult_or_logic ? 1'bx : cout0; +// drive signals to Output Atom + assign COUT_in[3] = cout_3; + assign COUT_in[2] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_2 : 1'bx; + assign COUT_in[1] = (USE_SIMD_BIN != USE_SIMD_ONE48 ) ? cout_1 : 1'bx; + assign COUT_in[0] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_0 : 1'bx; + assign MULTSIGN_ALU_in = s3[13]; // from alu rtl but doesn't seem right + assign #1 ALU_OUT_in = {48{ALUMODE_DATA[1]}} ^ {s3[11:0],s2[11:0],s1[11:0],s0[11:0]}; // break 0 delay feedback + assign XOR_MX_in[0] = XORSIMD_BIN ? xor_12a : xor_24a; + assign XOR_MX_in[1] = XORSIMD_BIN ? xor_12b : xor_48a; + assign XOR_MX_in[2] = XORSIMD_BIN ? xor_12c : xor_24b; + assign XOR_MX_in[3] = XORSIMD_BIN ? xor_12d : xor_96; + assign XOR_MX_in[4] = XORSIMD_BIN ? xor_12e : xor_24c; + assign XOR_MX_in[5] = XORSIMD_BIN ? xor_12f : xor_48b; + assign XOR_MX_in[6] = XORSIMD_BIN ? xor_12g : xor_24d; + assign XOR_MX_in[7] = xor_12h; + + +//--########################### END ALU ################################ + + +//*** CarryIn Mux and Register + +//------- input 0 + always @(posedge CLK_in) begin + if (RSTALLCARRYIN_in || glblGSR) + CARRYIN_reg <= 1'b0; + else if (CECARRYIN_in) + CARRYIN_reg <= CARRYIN_in; + end + + assign CARRYIN_mux = (CARRYINREG_BIN == 1'b1) ? CARRYIN_reg : CARRYIN_in; + +// INTERNAL CARRYIN REGISTER + assign c_mult = !(AMULT26_in^BMULT17_in); + assign ce_m_g = CEM_in & ~glblGSR; // & gwe + assign rst_carryin_g = RSTALLCARRYIN_in & ~glblGSR; // & gwe + assign d_carryin_int = ce_m_g ? c_mult : qmultcarryin; + +// rstallcarryin is injected through data path + assign dr_carryin_int = rst_carryin_g ? 0 : d_carryin_int; + + always @(posedge CLK_in) begin + if (glblGSR) + qmultcarryin <= 1'b0; + else + qmultcarryin <= dr_carryin_int; + end + + // bypass register mux + assign multcarryin_data = (MREG_BIN == 1'b1) ? qmultcarryin : c_mult; + +//NB + always @(CARRYINSEL_mux or CARRYIN_mux or PCIN_in[47] or CARRYCASCIN_in or CCOUT_in or P_FDBK_in[47] or multcarryin_data) begin + case (CARRYINSEL_mux) + 3'b000 : cin_b = ~CARRYIN_mux; + 3'b001 : cin_b = PCIN_in[47]; + 3'b010 : cin_b = ~CARRYCASCIN_in; + 3'b011 : cin_b = ~PCIN_in[47]; + 3'b100 : cin_b = ~CCOUT_in; + 3'b101 : cin_b = P_FDBK_in[47]; + 3'b110 : cin_b = ~multcarryin_data; + 3'b111 : cin_b = ~P_FDBK_in[47]; + default : cin_b = 1'bx; + endcase + end +// disable carryin when performing logic operation + assign cin = (ALUMODE_DATA[3] || ALUMODE_DATA[2]) ? 1'b0 : ~cin_b; + +// DSP_A_B_DATA +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin + A1_reg <= {A_WIDTH{1'b0}}; + end else if (CEA1_in) begin + if (A_INPUT_BIN == A_INPUT_CASCADE) begin + A1_reg <= ACIN_in; + end else begin + A1_reg <= A_in; + end + end + end + + always @(posedge CLK_in) begin + if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin + A2_reg <= {A_WIDTH{1'b0}}; + end else if (CEA2_in) begin + if (AREG_BIN == 2'b10) begin + A2_reg <= A1_reg; + end else if (A_INPUT_BIN == A_INPUT_CASCADE) begin + A2_reg <= ACIN_in; + end else begin + A2_reg <= A_in; + end + end + end + + assign A_ALU = (AREG_BIN != 2'b00) ? A2_reg : + (A_INPUT_BIN == A_INPUT_CASCADE) ? ACIN_in : + A_in; + +// assumes encoding the same for ACASCREG and AREG + assign ACOUT = (ACASCREG_BIN == AREG_BIN) ? A_ALU : A1_reg; + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTB_in || (BREG_BIN == 2'b00) || glblGSR) begin + B1_DATA_out <= 18'b0; + end else if (CEB1_in) begin + if (B_INPUT_BIN == B_INPUT_CASCADE) B1_DATA_out <= BCIN_in; + else B1_DATA_out <= B_in; + end + end + + always @(posedge CLK_in) begin + if (RSTB_in || glblGSR) B2_reg <= 18'b0; + else if (CEB2_in) begin + if (BREG_BIN == 2'b10) B2_reg <= B1_DATA_out; + else if (B_INPUT_BIN == B_INPUT_CASCADE) B2_reg <= BCIN_in; + else B2_reg <= B_in; + end + end + + assign B_ALU = (BREG_BIN != 2'b00) ? B2_reg : + (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : + B_in; + + assign B2_DATA = (BREG_BIN != 2'b00) ? B2_reg : + (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : + B_in; + +// assumes encoding the same for BCASCREG and BREG + assign BCOUT = (BCASCREG_BIN == BREG_BIN) ? B2_DATA : B1_DATA_out; + +// DSP_C_DATA +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTC_in || (CREG_BIN == 1'b0) || glblGSR) begin + C_reg <= 48'b0; + end else if (CEC_in) begin + C_reg <= C_in; + end + end + + assign C_DATA_in = (CREG_BIN == 1'b1) ? C_reg : C_in; + +// DSP_MULTIPLIER +always @(*) begin + if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1; + else a_mult_mux = AD_DATA; +end +always @(*) begin + if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1; + else b_mult_mux = AD_DATA; +end + + assign AMULT26_in = a_mult_mux[26]; + assign BMULT17_in = b_mult_mux[17]; +// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1 + assign U_in = {1'b1, mult[43:0] & ps_u_mask}; + assign V_in = {~mult[44], mult[43:0] & ps_v_mask}; + +always @(*) begin + if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0; + else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux}); +end + +// DSP_M_DATA +//********************************************************* +//*** Multiplier outputs U, V with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTM_in || (MREG_BIN == 1'b0) || glblGSR) begin + U_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}}; + V_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}}; + end else if (CEM_in) begin + U_DATA_reg <= U_in; + V_DATA_reg <= V_in; + end + end + + assign U_DATA = (MREG_BIN == 1'b1) ? U_DATA_reg : U_in; + assign V_DATA = (MREG_BIN == 1'b1) ? V_DATA_reg : V_in; + +// DSP_OUTPUT +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + + // select pattern + assign the_pattern = (SEL_PATTERN_BIN == SEL_PATTERN_PATTERN) ? PATTERN_REG : C_DATA_in; + + // select mask + assign the_mask = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_NO_PATDET) ? {C_WIDTH{1'b1}} : + (SEL_MASK_BIN == SEL_MASK_C) ? C_DATA_in : + (SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE1) ? {~(C_DATA_in[C_WIDTH-2:0]),1'b0} : + (SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE2) ? {~(C_DATA_in[C_WIDTH-3:0]),2'b0} : + MASK_REG; // default or (SEL_MASK_BIN == SEL_MASK_MASK) + + //-- now do the pattern detection + + assign pdet_o = &(~(the_pattern ^ ALU_OUT_in) | the_mask); + assign pdetb_o = &( (the_pattern ^ ALU_OUT_in) | the_mask); + + assign PATTERNDETECT = opmode_valid_flag_dou ? pdet_o_mux : 1'bx; + assign PATTERNBDETECT = opmode_valid_flag_dou ? pdetb_o_mux : 1'bx; + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + + always @(posedge CLK_in) begin + if (RSTP_in || glblGSR || the_auto_reset_patdet) begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end else if (CEP_in && PREG_BIN) begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdetb_o_reg2 <= pdetb_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg1 <= pdetb_o; + end + end + + assign pdet_o_mux = (PREG_BIN == 1'b1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = (PREG_BIN == 1'b1) ? pdetb_o_reg1 : pdetb_o; + assign overflow_data = (PREG_BIN == 1'b1) ? pdet_o_reg2 : pdet_o; + assign underflow_data = (PREG_BIN == 1'b1) ? pdetb_o_reg2 : pdetb_o; + +//--#################################################################### +//--##### AUTORESET_PATDET ##### +//--#################################################################### + assign auto_reset_pri = (AUTORESET_PRIORITY_BIN == AUTORESET_PRIORITY_RESET) || CEP_in; + + assign the_auto_reset_patdet = + (AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_MATCH) ? + auto_reset_pri && pdet_o_mux : + (AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_NOT_MATCH) ? + auto_reset_pri && overflow_data && ~pdet_o_mux : 1'b0; // NO_RESET + +//--#################################################################### +//--#### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT, PCOUT and XOROUT reg ##### +//--#################################################################### +//*** register with 1 level of register + always @(posedge CLK_in) begin + if (RSTP_in || glblGSR || the_auto_reset_patdet) begin + COUT_reg <= 4'b0000; + ALUMODE10_reg <= 1'b0; + MULTSIGN_ALU_reg <= 1'b0; + ALU_OUT_reg <= 48'b0; + XOR_MX_reg <= 8'b0; + end else if (CEP_in && PREG_BIN) begin + COUT_reg <= COUT_in; + ALUMODE10_reg <= ALUMODE10_in; + MULTSIGN_ALU_reg <= MULTSIGN_ALU_in; + ALU_OUT_reg <= ALU_OUT_in; + XOR_MX_reg <= XOR_MX_in; + end + end + + assign ALUMODE10_mux = (PREG_BIN == 1'b1) ? ALUMODE10_reg : ALUMODE10_in; + assign CARRYOUT = (PREG_BIN == 1'b1) ? COUT_reg : COUT_in; + assign MULTSIGNOUT = (PREG_BIN == 1'b1) ? MULTSIGN_ALU_reg : MULTSIGN_ALU_in; + assign P = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in; + assign XOROUT = (PREG_BIN == 1'b1) ? XOR_MX_reg : XOR_MX_in; + assign CCOUT_in = ALUMODE10_reg ^ COUT_reg[3]; + assign CARRYCASCOUT = (PREG_BIN == 1'b1) ? ALUMODE10_reg ^ COUT_reg[3]: + ALUMODE10_in ^ COUT_in[3]; + assign P_FDBK_in = ALU_OUT_reg; + assign P_FDBK_47_in = ALU_OUT_reg[47]; + assign PCOUT = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in; + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + assign OVERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ? + ~pdet_o_mux && ~pdetb_o_mux && overflow_data : 1'bx; + assign UNDERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ? + ~pdet_o_mux && ~pdetb_o_mux && underflow_data : 1'bx; +// DSP_PREADD +//********************************************************* +//*** Preaddsub AD +//********************************************************* + assign D_DATA_mux = INMODE_mux[2] ? D_DATA : 27'b0; + assign AD_in = INMODE_mux[3] ? (D_DATA_mux - PREADD_AB) : (D_DATA_mux + PREADD_AB); + +// DSP_PREADD_DATA + always @ (*) begin + if (((AMULTSEL_BIN == AMULTSEL_A) && + (BMULTSEL_BIN == BMULTSEL_B)) || + (USE_MULT_BIN == USE_MULT_NONE)) begin + DREG_INT = 1'b0; + end else begin + DREG_INT = DREG_BIN; + end + end + + always @ (*) begin + if (((AMULTSEL_BIN == AMULTSEL_A) && (BMULTSEL_BIN == BMULTSEL_B)) || + (USE_MULT_BIN == USE_MULT_NONE)) begin + ADREG_INT = 1'b0; + end else begin + ADREG_INT = ADREG_BIN; + end + end + + always @(*) begin + if ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) A2A1 = 27'b0; + else if (INMODE_mux[0]==1'b1) A2A1 = A1_reg[26:0]; + else A2A1 = A_ALU[26:0]; + end + always @(*) begin + if ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) B2B1 = 18'b0; + else if (INMODE_mux[4]==1'b1) B2B1 = B1_DATA_out; + else B2B1 = B2_DATA; + end + assign PREADD_AB = (PREADDINSEL_BIN==PREADDINSEL_B) ? {{9{B2B1[17]}}, B2B1} : A2A1; + +//********************************************************* +//********** INMODE signal registering ************ +//********************************************************* +// new + + always @(posedge CLK_in) begin + if (RSTINMODE_in || (INMODEREG_BIN == 1'b0) || glblGSR) begin + INMODE_reg <= 5'b0; + end else if (CEINMODE_in) begin + INMODE_reg <= INMODE_in; + end + end + + assign INMODE_mux = (INMODEREG_BIN == 1'b1) ? INMODE_reg : INMODE_in; + +//********************************************************* +//*** Input register D with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTD_in || (DREG_INT == 1'b0) || glblGSR) begin + D_DATA_reg <= {D_WIDTH{1'b0}}; + end else if (CED_in) begin + D_DATA_reg <= D_in; + end + end + + assign D_DATA = (DREG_INT == 1'b1) ? D_DATA_reg : D_in; + +//********************************************************* +//*** Input register AD with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTD_in || glblGSR) begin + AD_DATA_reg <= 27'b0; + end else if (CEAD_in) AD_DATA_reg <= AD_in; + end + + assign AD_DATA = (ADREG_INT == 1'b1) ? AD_DATA_reg : AD_in; + + always @(OPMODE_mux) begin + if (((OPMODE_mux[1:0] == 2'b11) && (USE_MULT_BIN == USE_MULT_MULTIPLY)) && + ((AREG_BIN==2'b00 && BREG_BIN==2'b00 && MREG_BIN==1'b0) || + (AREG_BIN==2'b00 && BREG_BIN==2'b00 && PREG_BIN==1'b0) || + (MREG_BIN==1'b0 && PREG_BIN==1'b0))) + $display("OPMODE Input Warning : [Unisim %s-8] The OPMODE[1:0] (%b) is invalid when using attributes USE_MULT = MULTIPLY and (A, B and M) or (A, B and P) or (M and P) are not REGISTERED at time %.3f ns. Please set USE_MULT to either NONE or DYNAMIC or REGISTER one of each group. (A or B) and (M or P) will satisfy the requirement. Instance %m", MODULE_NAME, OPMODE_mux[1:0], $time/1000.0); + if ((OPMODE_mux[3:0] == 4'b0101) && + ((USE_MULT_BIN == USE_MULT_NONE) || (USE_SIMD_BIN != USE_SIMD_ONE48))) + $display("OPMODE Input Warning : [Unisim %s-9] The OPMODE[3:0] (%b) is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns. Instance %m", MODULE_NAME, OPMODE_mux[3:0], $time/1000.0); + end + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_ALU.v b/verilog/src/unisims/DSP_ALU.v new file mode 100644 index 0000000..1272854 --- /dev/null +++ b/verilog/src/unisims/DSP_ALU.v @@ -0,0 +1,948 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_ALU +// /___/ /\ Filename : DSP_ALU.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 04/22/13 - 713695 - Zero mult result on USE_SIMD +// 04/22/13 - 713617 - CARRYCASCOUT behaviour +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 05/07/13 - 716896 - ALUMODE/OPMODE_INV_REG mis sized +// 05/07/13 - x_mac_cascd missing for sensitivity list. +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_ALU #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer ALUMODEREG = 1, + parameter integer CARRYINREG = 1, + parameter integer CARRYINSELREG = 1, + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000, + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000, + parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0, + parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0, + parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0, + parameter integer MREG = 1, + parameter integer OPMODEREG = 1, + parameter [47:0] RND = 48'h000000000000, + parameter USE_SIMD = "ONE48", + parameter USE_WIDEXOR = "FALSE", + parameter XORSIMD = "XOR24_48_96" +)( + output ALUMODE10, + output [47:0] ALU_OUT, + output [3:0] COUT, + output MULTSIGN_ALU, + output [7:0] XOR_MX, + + input [3:0] ALUMODE, + input AMULT26, + input [29:0] A_ALU, + input BMULT17, + input [17:0] B_ALU, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CCOUT, + input CEALUMODE, + input CECARRYIN, + input CECTRL, + input CEM, + input CLK, + input [47:0] C_DATA, + input MULTSIGNIN, + input [8:0] OPMODE, + input [47:0] PCIN, + input [47:0] P_FDBK, + input P_FDBK_47, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTCTRL, + input [44:0] U_DATA, + input [44:0] V_DATA +); + +// define constants + localparam MODULE_NAME = "DSP_ALU"; + +// Parameter encodings and registers + localparam USE_SIMD_FOUR12 = 1; + localparam USE_SIMD_ONE48 = 0; + localparam USE_SIMD_TWO24 = 2; + localparam USE_WIDEXOR_FALSE = 0; + localparam USE_WIDEXOR_TRUE = 1; + localparam XORSIMD_XOR12 = 1; + localparam XORSIMD_XOR24_48_96 = 0; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_ALU_dr.v" +`else + reg [31:0] ALUMODEREG_REG = ALUMODEREG; + reg [31:0] CARRYINREG_REG = CARRYINREG; + reg [31:0] CARRYINSELREG_REG = CARRYINSELREG; + reg [3:0] IS_ALUMODE_INVERTED_REG = IS_ALUMODE_INVERTED; + reg [0:0] IS_CARRYIN_INVERTED_REG = IS_CARRYIN_INVERTED; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [8:0] IS_OPMODE_INVERTED_REG = IS_OPMODE_INVERTED; + reg [0:0] IS_RSTALLCARRYIN_INVERTED_REG = IS_RSTALLCARRYIN_INVERTED; + reg [0:0] IS_RSTALUMODE_INVERTED_REG = IS_RSTALUMODE_INVERTED; + reg [0:0] IS_RSTCTRL_INVERTED_REG = IS_RSTCTRL_INVERTED; + reg [31:0] MREG_REG = MREG; + reg [31:0] OPMODEREG_REG = OPMODEREG; + reg [47:0] RND_REG = RND; + reg [48:1] USE_SIMD_REG = USE_SIMD; + reg [40:1] USE_WIDEXOR_REG = USE_WIDEXOR; + reg [88:1] XORSIMD_REG = XORSIMD; +`endif + +`ifdef XIL_XECLIB + wire ALUMODEREG_BIN; + wire CARRYINREG_BIN; + wire CARRYINSELREG_BIN; + wire MREG_BIN; + wire OPMODEREG_BIN; + wire [1:0] USE_SIMD_BIN; + wire USE_WIDEXOR_BIN; + wire XORSIMD_BIN; +`else + reg ALUMODEREG_BIN; + reg CARRYINREG_BIN; + reg CARRYINSELREG_BIN; + reg MREG_BIN; + reg OPMODEREG_BIN; + reg [1:0] USE_SIMD_BIN; + reg USE_WIDEXOR_BIN; + reg XORSIMD_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire AMULT26_in; + wire BMULT17_in; + wire CARRYCASCIN_in; + wire CARRYIN_in; + wire CCOUT_in; + wire CEALUMODE_in; + wire CECARRYIN_in; + wire CECTRL_in; + wire CEM_in; + wire CLK_in; + wire MULTSIGNIN_in; + wire P_FDBK_47_in; + wire RSTALLCARRYIN_in; + wire RSTALUMODE_in; + wire RSTCTRL_in; + wire [17:0] B_ALU_in; + wire [29:0] A_ALU_in; + wire [2:0] CARRYINSEL_in; + wire [3:0] ALUMODE_in; + wire [44:0] U_DATA_in; + wire [44:0] V_DATA_in; + wire [47:0] C_DATA_in; + wire [47:0] PCIN_in; + wire [47:0] P_FDBK_in; + wire [8:0] OPMODE_in; + +`ifdef XIL_TIMING + wire AMULT26_delay; + wire BMULT17_delay; + wire CARRYIN_delay; + wire CEALUMODE_delay; + wire CECARRYIN_delay; + wire CECTRL_delay; + wire CEM_delay; + wire CLK_delay; + wire RSTALLCARRYIN_delay; + wire RSTALUMODE_delay; + wire RSTCTRL_delay; + wire [2:0] CARRYINSEL_delay; + wire [3:0] ALUMODE_delay; + wire [8:0] OPMODE_delay; +`endif + +`ifdef XIL_TIMING + assign ALUMODE_in[0] = (ALUMODE[0] !== 1'bz) && (ALUMODE_delay[0] ^ IS_ALUMODE_INVERTED_REG[0]); // rv 0 + assign ALUMODE_in[1] = (ALUMODE[1] !== 1'bz) && (ALUMODE_delay[1] ^ IS_ALUMODE_INVERTED_REG[1]); // rv 0 + assign ALUMODE_in[2] = (ALUMODE[2] !== 1'bz) && (ALUMODE_delay[2] ^ IS_ALUMODE_INVERTED_REG[2]); // rv 0 + assign ALUMODE_in[3] = (ALUMODE[3] !== 1'bz) && (ALUMODE_delay[3] ^ IS_ALUMODE_INVERTED_REG[3]); // rv 0 + assign AMULT26_in = AMULT26_delay; + assign BMULT17_in = BMULT17_delay; + assign CARRYINSEL_in[0] = (CARRYINSEL[0] !== 1'bz) && CARRYINSEL_delay[0]; // rv 0 + assign CARRYINSEL_in[1] = (CARRYINSEL[1] !== 1'bz) && CARRYINSEL_delay[1]; // rv 0 + assign CARRYINSEL_in[2] = (CARRYINSEL[2] !== 1'bz) && CARRYINSEL_delay[2]; // rv 0 + assign CARRYIN_in = (CARRYIN !== 1'bz) && (CARRYIN_delay ^ IS_CARRYIN_INVERTED_REG); // rv 0 + assign CEALUMODE_in = (CEALUMODE !== 1'bz) && CEALUMODE_delay; // rv 0 + assign CECARRYIN_in = (CECARRYIN !== 1'bz) && CECARRYIN_delay; // rv 0 + assign CECTRL_in = (CECTRL !== 1'bz) && CECTRL_delay; // rv 0 + assign CEM_in = (CEM !== 1'bz) && CEM_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign OPMODE_in[0] = (OPMODE[0] !== 1'bz) && (OPMODE_delay[0] ^ IS_OPMODE_INVERTED_REG[0]); // rv 0 + assign OPMODE_in[1] = (OPMODE[1] !== 1'bz) && (OPMODE_delay[1] ^ IS_OPMODE_INVERTED_REG[1]); // rv 0 + assign OPMODE_in[2] = (OPMODE[2] !== 1'bz) && (OPMODE_delay[2] ^ IS_OPMODE_INVERTED_REG[2]); // rv 0 + assign OPMODE_in[3] = (OPMODE[3] !== 1'bz) && (OPMODE_delay[3] ^ IS_OPMODE_INVERTED_REG[3]); // rv 0 + assign OPMODE_in[4] = (OPMODE[4] !== 1'bz) && (OPMODE_delay[4] ^ IS_OPMODE_INVERTED_REG[4]); // rv 0 + assign OPMODE_in[5] = (OPMODE[5] !== 1'bz) && (OPMODE_delay[5] ^ IS_OPMODE_INVERTED_REG[5]); // rv 0 + assign OPMODE_in[6] = (OPMODE[6] !== 1'bz) && (OPMODE_delay[6] ^ IS_OPMODE_INVERTED_REG[6]); // rv 0 + assign OPMODE_in[7] = (OPMODE[7] !== 1'bz) && (OPMODE_delay[7] ^ IS_OPMODE_INVERTED_REG[7]); // rv 0 + assign OPMODE_in[8] = (OPMODE[8] !== 1'bz) && (OPMODE_delay[8] ^ IS_OPMODE_INVERTED_REG[8]); // rv 0 + assign RSTALLCARRYIN_in = (RSTALLCARRYIN !== 1'bz) && (RSTALLCARRYIN_delay ^ IS_RSTALLCARRYIN_INVERTED_REG); // rv 0 + assign RSTALUMODE_in = (RSTALUMODE !== 1'bz) && (RSTALUMODE_delay ^ IS_RSTALUMODE_INVERTED_REG); // rv 0 + assign RSTCTRL_in = (RSTCTRL !== 1'bz) && (RSTCTRL_delay ^ IS_RSTCTRL_INVERTED_REG); // rv 0 +`else + assign ALUMODE_in[0] = (ALUMODE[0] !== 1'bz) && (ALUMODE[0] ^ IS_ALUMODE_INVERTED_REG[0]); // rv 0 + assign ALUMODE_in[1] = (ALUMODE[1] !== 1'bz) && (ALUMODE[1] ^ IS_ALUMODE_INVERTED_REG[1]); // rv 0 + assign ALUMODE_in[2] = (ALUMODE[2] !== 1'bz) && (ALUMODE[2] ^ IS_ALUMODE_INVERTED_REG[2]); // rv 0 + assign ALUMODE_in[3] = (ALUMODE[3] !== 1'bz) && (ALUMODE[3] ^ IS_ALUMODE_INVERTED_REG[3]); // rv 0 + assign AMULT26_in = AMULT26; + assign BMULT17_in = BMULT17; + assign CARRYINSEL_in[0] = (CARRYINSEL[0] !== 1'bz) && CARRYINSEL[0]; // rv 0 + assign CARRYINSEL_in[1] = (CARRYINSEL[1] !== 1'bz) && CARRYINSEL[1]; // rv 0 + assign CARRYINSEL_in[2] = (CARRYINSEL[2] !== 1'bz) && CARRYINSEL[2]; // rv 0 + assign CARRYIN_in = (CARRYIN !== 1'bz) && (CARRYIN ^ IS_CARRYIN_INVERTED_REG); // rv 0 + assign CEALUMODE_in = (CEALUMODE !== 1'bz) && CEALUMODE; // rv 0 + assign CECARRYIN_in = (CECARRYIN !== 1'bz) && CECARRYIN; // rv 0 + assign CECTRL_in = (CECTRL !== 1'bz) && CECTRL; // rv 0 + assign CEM_in = (CEM !== 1'bz) && CEM; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign OPMODE_in[0] = (OPMODE[0] !== 1'bz) && (OPMODE[0] ^ IS_OPMODE_INVERTED_REG[0]); // rv 0 + assign OPMODE_in[1] = (OPMODE[1] !== 1'bz) && (OPMODE[1] ^ IS_OPMODE_INVERTED_REG[1]); // rv 0 + assign OPMODE_in[2] = (OPMODE[2] !== 1'bz) && (OPMODE[2] ^ IS_OPMODE_INVERTED_REG[2]); // rv 0 + assign OPMODE_in[3] = (OPMODE[3] !== 1'bz) && (OPMODE[3] ^ IS_OPMODE_INVERTED_REG[3]); // rv 0 + assign OPMODE_in[4] = (OPMODE[4] !== 1'bz) && (OPMODE[4] ^ IS_OPMODE_INVERTED_REG[4]); // rv 0 + assign OPMODE_in[5] = (OPMODE[5] !== 1'bz) && (OPMODE[5] ^ IS_OPMODE_INVERTED_REG[5]); // rv 0 + assign OPMODE_in[6] = (OPMODE[6] !== 1'bz) && (OPMODE[6] ^ IS_OPMODE_INVERTED_REG[6]); // rv 0 + assign OPMODE_in[7] = (OPMODE[7] !== 1'bz) && (OPMODE[7] ^ IS_OPMODE_INVERTED_REG[7]); // rv 0 + assign OPMODE_in[8] = (OPMODE[8] !== 1'bz) && (OPMODE[8] ^ IS_OPMODE_INVERTED_REG[8]); // rv 0 + assign RSTALLCARRYIN_in = (RSTALLCARRYIN !== 1'bz) && (RSTALLCARRYIN ^ IS_RSTALLCARRYIN_INVERTED_REG); // rv 0 + assign RSTALUMODE_in = (RSTALUMODE !== 1'bz) && (RSTALUMODE ^ IS_RSTALUMODE_INVERTED_REG); // rv 0 + assign RSTCTRL_in = (RSTCTRL !== 1'bz) && (RSTCTRL ^ IS_RSTCTRL_INVERTED_REG); // rv 0 +`endif + + assign A_ALU_in = A_ALU; + assign B_ALU_in = B_ALU; + assign CARRYCASCIN_in = CARRYCASCIN; + assign CCOUT_in = CCOUT; + assign C_DATA_in = C_DATA; + assign MULTSIGNIN_in = MULTSIGNIN; + assign PCIN_in = PCIN; + assign P_FDBK_47_in = P_FDBK_47; + assign P_FDBK_in = P_FDBK; + assign U_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? U_DATA : 45'h100000000000; + assign V_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? V_DATA : 45'h100000000000; + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign ALUMODEREG_BIN = ALUMODEREG_REG[0]; + + assign CARRYINREG_BIN = CARRYINREG_REG[0]; + + assign CARRYINSELREG_BIN = CARRYINSELREG_REG[0]; + + assign MREG_BIN = MREG_REG[0]; + + assign OPMODEREG_BIN = OPMODEREG_REG[0]; + + assign USE_SIMD_BIN = + (USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 : + (USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 : + (USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 : + USE_SIMD_ONE48; + + assign USE_WIDEXOR_BIN = + (USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE : + (USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE : + USE_WIDEXOR_FALSE; + + assign XORSIMD_BIN = + (XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 : + (XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 : + XORSIMD_XOR24_48_96; + +`else +always @(trig_attr) begin +#1; + ALUMODEREG_BIN = ALUMODEREG_REG[0]; + + CARRYINREG_BIN = CARRYINREG_REG[0]; + + CARRYINSELREG_BIN = CARRYINSELREG_REG[0]; + + MREG_BIN = MREG_REG[0]; + + OPMODEREG_BIN = OPMODEREG_REG[0]; + + USE_SIMD_BIN = + (USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 : + (USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 : + (USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 : + USE_SIMD_ONE48; + + USE_WIDEXOR_BIN = + (USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE : + (USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE : + USE_WIDEXOR_FALSE; + + XORSIMD_BIN = + (XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 : + (XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 : + XORSIMD_XOR24_48_96; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ALUMODEREG_REG != 1) && + (ALUMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-101] ALUMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ALUMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CARRYINREG_REG != 1) && + (CARRYINREG_REG != 0))) begin + $display("Error: [Unisim %s-102] CARRYINREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CARRYINSELREG_REG != 1) && + (CARRYINSELREG_REG != 0))) begin + $display("Error: [Unisim %s-103] CARRYINSELREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CARRYINSELREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MREG_REG != 1) && + (MREG_REG != 0))) begin + $display("Error: [Unisim %s-111] MREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, MREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OPMODEREG_REG != 1) && + (OPMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-112] OPMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, OPMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_SIMD_REG != "ONE48") && + (USE_SIMD_REG != "FOUR12") && + (USE_SIMD_REG != "TWO24"))) begin + $display("Error: [Unisim %s-114] USE_SIMD attribute is set to %s. Legal values for this attribute are ONE48, FOUR12 or TWO24. Instance: %m", MODULE_NAME, USE_SIMD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_WIDEXOR_REG != "FALSE") && + (USE_WIDEXOR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-115] USE_WIDEXOR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_WIDEXOR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XORSIMD_REG != "XOR24_48_96") && + (XORSIMD_REG != "XOR12"))) begin + $display("Error: [Unisim %s-116] XORSIMD attribute is set to %s. Legal values for this attribute are XOR24_48_96 or XOR12. Instance: %m", MODULE_NAME, XORSIMD_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam MAX_ALU_FULL = 48; + localparam MAX_CARRYOUT = 4; + reg cci_drc_msg; + reg cis_drc_msg; + + + wire CARRYIN_mux; + reg CARRYIN_reg; + reg [3:0] ALUMODE_reg; + reg [2:0] CARRYINSEL_mux; + reg [2:0] CARRYINSEL_reg; + reg [8:0] OPMODE_mux; + reg [8:0] OPMODE_reg; + + wire [47:0] x_mac_cascd; + + reg [47:0] wmux; + reg [47:0] xmux; + reg [47:0] ymux; + reg [47:0] zmux; + wire [47:0] z_optinv; + + wire cin; + reg cin_b; + wire rst_carryin_g; + reg qmultcarryin; + + wire c_mult; + wire ce_m_g; + wire d_carryin_int; + wire dr_carryin_int; + wire multcarryin_data; + + reg invalid_opmode; + reg opmode_valid_flag_dal; // used in OPMODE DRC + reg ping_opmode_drc_check; + + wire [MAX_ALU_FULL-1:0] co; + wire [MAX_ALU_FULL-1:0] s; + wire [MAX_ALU_FULL-1:0] comux; + wire [MAX_ALU_FULL-1:0] comux_w; + wire [MAX_ALU_FULL-1:0] comux4simd; + wire [MAX_ALU_FULL-1:0] smux; + wire [MAX_ALU_FULL-1:0] smux_w; + wire [MAX_ALU_FULL:0] a_int; + wire [12:0] s0; + wire cout0; + wire intc1; + wire co12_lsb; + wire [12:0] s1; + wire cout1; + wire intc2; + wire co24_lsb; + wire [12:0] s2; + wire cout2; + wire intc3; + wire co36_lsb; + wire [13:0] s3; + wire cout3; + wire cout4; + wire xor_12a; + wire xor_12b; + wire xor_12c; + wire xor_12d; + wire xor_12e; + wire xor_12f; + wire xor_12g; + wire xor_12h; + wire xor_24a; + wire xor_24b; + wire xor_24c; + wire xor_24d; + wire xor_48a; + wire xor_48b; + wire xor_96; + wire cout_0; + wire cout_1; + wire cout_2; + wire cout_3; + wire mult_or_logic; + + reg [3:0] ALUMODE_DATA; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + cci_drc_msg = 1'b0; + cis_drc_msg = 1'b0; + CARRYIN_reg = 1'b0; + ALUMODE_reg = 4'b0; + CARRYINSEL_mux = 3'b0; + CARRYINSEL_reg = 3'b0; + OPMODE_mux = 9'b0; + OPMODE_reg = 9'b0; + wmux = 48'b0; + xmux = 48'b0; + ymux = 48'b0; + zmux = 48'b0; + cin_b = 1'b0; + qmultcarryin = 1'b0; + invalid_opmode = 1'b1; + opmode_valid_flag_dal = 1'b1; + ping_opmode_drc_check = 1'b0; +end +`endif + +//*** W mux NB + always @(OPMODE_mux[8:7] or P_FDBK_in or RND_REG or C_DATA_in) + case (OPMODE_mux[8:7]) + 2'b00 : wmux = 48'b0; + 2'b01 : wmux = P_FDBK_in; + 2'b10 : wmux = RND_REG; + 2'b11 : wmux = C_DATA_in; + default : wmux = {48{1'bx}}; + endcase + +// To support MAC-cascade add multsignin to bit 1 of X + assign x_mac_cascd = (OPMODE_mux[6:4] == 3'b100) ? {{46{1'b0}},MULTSIGNIN_in,1'b0} : {48{1'b0}}; + +//*** X mux NB + always @(U_DATA_in or P_FDBK_in or A_ALU_in or B_ALU_in or OPMODE_mux[1:0] or x_mac_cascd) + case (OPMODE_mux[1:0]) + 2'b00 : xmux = x_mac_cascd; + 2'b01 : xmux = {{3{U_DATA_in[44]}}, U_DATA_in}; + 2'b10 : xmux = P_FDBK_in; + 2'b11 : xmux = {A_ALU_in, B_ALU_in}; + default : xmux = {48{1'bx}}; + endcase + +//*** Y mux NB + always @(OPMODE_mux[3:2] or V_DATA_in or C_DATA_in) + case (OPMODE_mux[3:2]) + 2'b00 : ymux = 48'b0; + 2'b01 : ymux = {{3{1'b0}}, V_DATA_in}; + 2'b10 : ymux = {48{1'b1}}; + 2'b11 : ymux = C_DATA_in; + default : ymux = {48{1'bx}}; + endcase + +//*** Z mux NB + always @(OPMODE_mux[6:4] or PCIN_in or P_FDBK_in or C_DATA_in or P_FDBK_47_in) + casex (OPMODE_mux[6:4]) + 3'b000 : zmux = 48'b0; + 3'b001 : zmux = PCIN_in; + 3'b010 : zmux = P_FDBK_in; + 3'b011 : zmux = C_DATA_in; + 3'b100 : zmux = P_FDBK_in; + 3'b101 : zmux = {{9{PCIN_in[47]}}, {8{PCIN_in[47]}}, PCIN_in[47:17]}; + 3'b11x : zmux = {{9{P_FDBK_47_in}}, {8{P_FDBK_in[47]}}, P_FDBK_in[47:17]}; + default : zmux = {48{1'bx}}; + endcase + +//********************************************************* +//*** CARRYINSEL and OPMODE with 1 level of register +//********************************************************* + always @(posedge CLK_in) begin + if (RSTCTRL_in || glblGSR) begin + OPMODE_reg <= 9'b0; + end + else if (CECTRL_in) begin + OPMODE_reg <= OPMODE_in; + end + end + + always @(posedge CLK_in) begin + if (RSTCTRL_in || glblGSR) begin + CARRYINSEL_reg <= 3'b0; + end + else if (CECTRL_in) begin + CARRYINSEL_reg <= CARRYINSEL_in; + end + end + + always @(*) CARRYINSEL_mux = (CARRYINSELREG_BIN == 1'b1) ? CARRYINSEL_reg : CARRYINSEL_in; + + always @(*) begin + if (OPMODEREG_BIN == 1'b1) OPMODE_mux = OPMODE_reg; + else OPMODE_mux = OPMODE_in; + end + + always @(CARRYINSEL_mux or CARRYCASCIN_in or MULTSIGNIN_in or OPMODE_mux) begin + if (CARRYINSEL_mux == 3'b010) begin + if (!((MULTSIGNIN_in === 1'bx) || (cci_drc_msg == 1'b1) || + ((OPMODE_mux == 9'b001001000) && !(MULTSIGNIN_in === 1'bx)) || + ((MULTSIGNIN_in == 1'b0) && (CARRYCASCIN_in == 1'b0)))) begin + $display("DRC warning : [Unisim %s-7] CARRYCASCIN can only be used in the current %s if the previous %s is performing a two input ADD or SUBRTACT operation or the current %s is configured in the MAC extend opmode 7'b1001000 at %.3f ns. Instance %m\n", MODULE_NAME, MODULE_NAME, MODULE_NAME, MODULE_NAME, $time/1000.0); +// CR 619940 -- Enhanced DRC warning + $display("The simulation model does not know the placement of the %s slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the %s slices and ensure that these warnings are not being breached\n", MODULE_NAME, MODULE_NAME); + cci_drc_msg = 1'b1; + end + if (!((MULTSIGNIN_in === 1'bx) || (OPMODE_mux[3:0] != 4'b0101))) begin + $display("DRC warning : [Unisim %s-10] CARRYINSEL is set to 010 with OPMODE set to multiplication (xxx0101). This is an illegal mode and may show deviation between simulation results and hardware behavior. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0); + end + if (!((MULTSIGNIN_in === 1'bx) || (cis_drc_msg == 1'b1) || + (OPMODEREG_BIN == 1'b1))) begin + $display("DRC warning : [Unisim %s-11] CARRYINSEL is set to 010 with OPMODEREG set to 0. This causes unknown values after reset occurs. It is suggested to use OPMODEREG = 1 when cascading large adders. %s instance %m at %.3f ns.", MODULE_NAME, MODULE_NAME, $time/1000.0); + cis_drc_msg = 1'b1; + end + end + end + +//********************************************************* +//*** ALUMODE with 1 level of register +//********************************************************* + always @(posedge CLK_in) begin + if (RSTALUMODE_in || glblGSR) + ALUMODE_reg <= 4'b0; + else if (CEALUMODE_in) + ALUMODE_reg <= ALUMODE_in; + end + + always @(*) ALUMODE_DATA = (ALUMODEREG_BIN == 1'b1) ? ALUMODE_reg : ALUMODE_in; + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + +// needs PREG from output block +// ~2000 lines code - skip for now - copy/rework from DSP48E1. + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + +// ADDSUB block - first stage of ALU develops sums and carries for Final Adder +// Invert Z for subtract operation using alumode<0> + assign z_optinv = {48{ALUMODE_DATA[0]}} ^ zmux; + +// Add W, X, Y, Z carry-save style; basically full adder logic below + assign co = ((xmux & ymux)|(z_optinv & ymux)|(xmux & z_optinv)); +// s has a fan-out of 2 (1) FA with W (2) second leg of XOR tree + assign s = (z_optinv^xmux^ymux); + +// Mux S and CO to do 2 operands logic operations +// S = produce XOR/XNOR, NOT functions +// CO = produce AND/NAND, OR/NOR functions + assign comux = ALUMODE_DATA[2] ? 0 : co; + assign smux = ALUMODE_DATA[3] ? co : s; + +// Carry mux to handle SIMD mode +// SIMD must be used here since addition of W requires carry propogation + assign comux4simd = { + comux[47:36], + comux[35]&&(USE_SIMD_BIN != USE_SIMD_FOUR12), + comux[34:24], + comux[23]&&(USE_SIMD_BIN == USE_SIMD_ONE48), + comux[22:12], + comux[11]&&(USE_SIMD_BIN != USE_SIMD_FOUR12), + comux[10:0] + }; + +// FA to combine W-mux with s and co +// comux must be shifted to properly reflect carry operation + assign smux_w = smux ^ {comux4simd[46:0],1'b0} ^ wmux; + assign comux_w = ((smux & {comux4simd[46:0],1'b0}) | + (wmux & {comux4simd[46:0],1'b0}) | + (smux & wmux)); + +// alumode10 indicates a subtraction, used to correct carryout polarity + assign ALUMODE10 = (ALUMODE_DATA[0] & ALUMODE_DATA[1]); + +// prepare data for Final Adder +// a[0] is in fact the cin bit, adder inputs: a[48:1], b[47:0], cin= a[0] + assign a_int = {comux_w, cin}; +// assign b_int = smux_w; + +// FINAL ADDER - second stage develops final sums and carries + assign s0 = a_int[11:0] + smux_w[11:0]; + // invert if alumode10 + assign cout0 = ALUMODE10 ^ (a_int[12] ^ s0[12] ^ comux[11]); + // internal carry is zero'd out on mc_simd == 1 + assign intc1 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s0[12]; + // next lsb is zero'd out on mc_simd == 1 + assign co12_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[12]; + // + assign s1 = {a_int[23:13],co12_lsb} + smux_w[23:12] + intc1; + assign cout1 = ALUMODE10 ^ (a_int[24] ^ s1[12] ^ comux[23]); + assign intc2 = (USE_SIMD_BIN == USE_SIMD_ONE48) && s1[12]; + assign co24_lsb = (USE_SIMD_BIN == USE_SIMD_ONE48) && a_int[24]; + // + assign s2 = {a_int[35:25],co24_lsb} + smux_w[35:24] + intc2; + assign cout2 = ALUMODE10 ^ (a_int[36] ^ s2[12] ^ comux[35]); + assign intc3 = (USE_SIMD_BIN != USE_SIMD_FOUR12) && s2[12]; + assign co36_lsb = (USE_SIMD_BIN != USE_SIMD_FOUR12) && a_int[36]; + // + assign s3 = {a_int[48:37],co36_lsb} + {comux4simd[47],smux_w[47:36]} + intc3; + assign cout3 = ALUMODE10 ^ s3[12]; + +// Not gated with alumode10 since used to propogate carry in wide multiply + assign cout4 = s3[13]; + +// Wide XOR + assign xor_12a = USE_WIDEXOR_BIN ? ^s[5:0] : 0; + assign xor_12b = USE_WIDEXOR_BIN ? ^s[11:6] : 0; + assign xor_12c = USE_WIDEXOR_BIN ? ^s[17:12] : 0; + assign xor_12d = USE_WIDEXOR_BIN ? ^s[23:18] : 0; + assign xor_12e = USE_WIDEXOR_BIN ? ^s[29:24] : 0; + assign xor_12f = USE_WIDEXOR_BIN ? ^s[35:30] : 0; + assign xor_12g = USE_WIDEXOR_BIN ? ^s[41:36] : 0; + assign xor_12h = USE_WIDEXOR_BIN ? ^s[47:42] : 0; + + assign xor_24a = xor_12a ^ xor_12b; + assign xor_24b = xor_12c ^ xor_12d; + assign xor_24c = xor_12e ^ xor_12f; + assign xor_24d = xor_12g ^ xor_12h; + + assign xor_48a = xor_24a ^ xor_24b; + assign xor_48b = xor_24c ^ xor_24d; + + assign xor_96 = xor_48a ^ xor_48b; + +// "X" carryout for multiply and logic operations + assign mult_or_logic = ((OPMODE_mux[3:0] == 4'b0101) || + (ALUMODE_DATA[3:2] != 2'b00)); +// allow carrycascout to not X in output atom +// assign cout_3 = mult_or_logic ? 1'bx : cout3; + assign cout_3 = cout3; + assign cout_2 = mult_or_logic ? 1'bx : cout2; + assign cout_1 = mult_or_logic ? 1'bx : cout1; + assign cout_0 = mult_or_logic ? 1'bx : cout0; +// drive signals to Output Atom + assign COUT[3] = cout_3; + assign COUT[2] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_2 : 1'bx; + assign COUT[1] = (USE_SIMD_BIN != USE_SIMD_ONE48 ) ? cout_1 : 1'bx; + assign COUT[0] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_0 : 1'bx; + assign MULTSIGN_ALU = s3[13]; + assign #1 ALU_OUT = {48{ALUMODE_DATA[1]}} ^ {s3[11:0],s2[11:0],s1[11:0],s0[11:0]}; // break 0 delay feedback + assign XOR_MX[0] = XORSIMD_BIN ? xor_12a : xor_24a; + assign XOR_MX[1] = XORSIMD_BIN ? xor_12b : xor_48a; + assign XOR_MX[2] = XORSIMD_BIN ? xor_12c : xor_24b; + assign XOR_MX[3] = XORSIMD_BIN ? xor_12d : xor_96; + assign XOR_MX[4] = XORSIMD_BIN ? xor_12e : xor_24c; + assign XOR_MX[5] = XORSIMD_BIN ? xor_12f : xor_48b; + assign XOR_MX[6] = XORSIMD_BIN ? xor_12g : xor_24d; + assign XOR_MX[7] = xor_12h; + + +//--########################### END ALU ################################ + + +//*** CarryIn Mux and Register + +//------- input 0 + always @(posedge CLK_in) begin + if (RSTALLCARRYIN_in || glblGSR) + CARRYIN_reg <= 1'b0; + else if (CECARRYIN_in) + CARRYIN_reg <= CARRYIN_in; + end + + assign CARRYIN_mux = (CARRYINREG_BIN == 1'b1) ? CARRYIN_reg : CARRYIN_in; + +// INTERNAL CARRYIN REGISTER + assign c_mult = !(AMULT26_in^BMULT17_in); + assign ce_m_g = CEM_in & ~glblGSR; // & gwe + assign rst_carryin_g = RSTALLCARRYIN_in & ~glblGSR; // & gwe + assign d_carryin_int = ce_m_g ? c_mult : qmultcarryin; + +// rstallcarryin is injected through data path + assign dr_carryin_int = rst_carryin_g ? 0 : d_carryin_int; + + always @(posedge CLK_in) begin + if (glblGSR) + qmultcarryin <= 1'b0; + else + qmultcarryin <= dr_carryin_int; + end + + // bypass register mux + assign multcarryin_data = (MREG_BIN == 1'b1) ? qmultcarryin : c_mult; + +//NB + always @(CARRYINSEL_mux or CARRYIN_mux or PCIN_in[47] or CARRYCASCIN_in or CCOUT_in or P_FDBK_in[47] or multcarryin_data) begin + case (CARRYINSEL_mux) + 3'b000 : cin_b = ~CARRYIN_mux; + 3'b001 : cin_b = PCIN_in[47]; + 3'b010 : cin_b = ~CARRYCASCIN_in; + 3'b011 : cin_b = ~PCIN_in[47]; + 3'b100 : cin_b = ~CCOUT_in; + 3'b101 : cin_b = P_FDBK_in[47]; + 3'b110 : cin_b = ~multcarryin_data; + 3'b111 : cin_b = ~P_FDBK_in[47]; + default : cin_b = 1'bx; + endcase + end +// disable carryin when performing logic operation + assign cin = (ALUMODE_DATA[3] || ALUMODE_DATA[2]) ? 1'b0 : ~cin_b; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (ALUMODE *> ALUMODE10) = (0:0:0, 0:0:0); + (ALUMODE *> ALU_OUT) = (0:0:0, 0:0:0); + (ALUMODE *> COUT) = (0:0:0, 0:0:0); + (ALUMODE *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (ALUMODE *> XOR_MX) = (0:0:0, 0:0:0); + (AMULT26 *> ALU_OUT) = (0:0:0, 0:0:0); + (AMULT26 *> COUT) = (0:0:0, 0:0:0); + (AMULT26 => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (A_ALU *> ALU_OUT) = (0:0:0, 0:0:0); + (A_ALU *> COUT) = (0:0:0, 0:0:0); + (A_ALU *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (A_ALU *> XOR_MX) = (0:0:0, 0:0:0); + (BMULT17 *> ALU_OUT) = (0:0:0, 0:0:0); + (BMULT17 *> COUT) = (0:0:0, 0:0:0); + (BMULT17 => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (B_ALU *> ALU_OUT) = (0:0:0, 0:0:0); + (B_ALU *> COUT) = (0:0:0, 0:0:0); + (B_ALU *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (B_ALU *> XOR_MX) = (0:0:0, 0:0:0); + (CARRYCASCIN *> ALU_OUT) = (0:0:0, 0:0:0); + (CARRYCASCIN *> COUT) = (0:0:0, 0:0:0); + (CARRYCASCIN => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (CARRYIN *> ALU_OUT) = (0:0:0, 0:0:0); + (CARRYIN *> COUT) = (0:0:0, 0:0:0); + (CARRYIN => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (CARRYINSEL *> ALU_OUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> COUT) = (0:0:0, 0:0:0); + (CARRYINSEL *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (CCOUT *> ALU_OUT) = (0:0:0, 0:0:0); + (CCOUT *> COUT) = (0:0:0, 0:0:0); + (CCOUT => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (CLK *> ALU_OUT) = (0:0:0, 0:0:0); + (CLK *> COUT) = (0:0:0, 0:0:0); + (CLK *> XOR_MX) = (0:0:0, 0:0:0); + (CLK => ALUMODE10) = (0:0:0, 0:0:0); + (CLK => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (C_DATA *> ALU_OUT) = (0:0:0, 0:0:0); + (C_DATA *> COUT) = (0:0:0, 0:0:0); + (C_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (C_DATA *> XOR_MX) = (0:0:0, 0:0:0); + (MULTSIGNIN *> ALU_OUT) = (0:0:0, 0:0:0); + (MULTSIGNIN *> COUT) = (0:0:0, 0:0:0); + (MULTSIGNIN => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (OPMODE *> ALU_OUT) = (0:0:0, 0:0:0); + (OPMODE *> COUT) = (0:0:0, 0:0:0); + (OPMODE *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (OPMODE *> XOR_MX) = (0:0:0, 0:0:0); + (PCIN *> ALU_OUT) = (0:0:0, 0:0:0); + (PCIN *> COUT) = (0:0:0, 0:0:0); + (PCIN *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (PCIN *> XOR_MX) = (0:0:0, 0:0:0); + (P_FDBK *> ALU_OUT) = (0:0:0, 0:0:0); + (P_FDBK *> COUT) = (0:0:0, 0:0:0); + (P_FDBK *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (P_FDBK *> XOR_MX) = (0:0:0, 0:0:0); + (P_FDBK_47 *> ALU_OUT) = (0:0:0, 0:0:0); + (P_FDBK_47 *> COUT) = (0:0:0, 0:0:0); + (P_FDBK_47 *> XOR_MX) = (0:0:0, 0:0:0); + (P_FDBK_47 => MULTSIGN_ALU) = (0:0:0, 0:0:0); + (U_DATA *> ALU_OUT) = (0:0:0, 0:0:0); + (U_DATA *> COUT) = (0:0:0, 0:0:0); + (U_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0); + (V_DATA *> ALU_OUT) = (0:0:0, 0:0:0); + (V_DATA *> COUT) = (0:0:0, 0:0:0); + (V_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALUMODE_delay); + $setuphold (negedge CLK, negedge AMULT26, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AMULT26_delay); + $setuphold (negedge CLK, negedge BMULT17, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BMULT17_delay); + $setuphold (negedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CARRYIN_delay); + $setuphold (negedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CARRYINSEL_delay); + $setuphold (negedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEALUMODE_delay); + $setuphold (negedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CECARRYIN_delay); + $setuphold (negedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CECTRL_delay); + $setuphold (negedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEM_delay); + $setuphold (negedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OPMODE_delay); + $setuphold (negedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTALLCARRYIN_delay); + $setuphold (negedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTALUMODE_delay); + $setuphold (negedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTCTRL_delay); + $setuphold (negedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALUMODE_delay); + $setuphold (negedge CLK, posedge AMULT26, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AMULT26_delay); + $setuphold (negedge CLK, posedge BMULT17, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BMULT17_delay); + $setuphold (negedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CARRYIN_delay); + $setuphold (negedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CARRYINSEL_delay); + $setuphold (negedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEALUMODE_delay); + $setuphold (negedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CECARRYIN_delay); + $setuphold (negedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CECTRL_delay); + $setuphold (negedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEM_delay); + $setuphold (negedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OPMODE_delay); + $setuphold (negedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTALLCARRYIN_delay); + $setuphold (negedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTALUMODE_delay); + $setuphold (negedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTCTRL_delay); + $setuphold (posedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALUMODE_delay); + $setuphold (posedge CLK, negedge AMULT26, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AMULT26_delay); + $setuphold (posedge CLK, negedge BMULT17, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BMULT17_delay); + $setuphold (posedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CARRYIN_delay); + $setuphold (posedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CARRYINSEL_delay); + $setuphold (posedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEALUMODE_delay); + $setuphold (posedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CECARRYIN_delay); + $setuphold (posedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CECTRL_delay); + $setuphold (posedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEM_delay); + $setuphold (posedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OPMODE_delay); + $setuphold (posedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTALLCARRYIN_delay); + $setuphold (posedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTALUMODE_delay); + $setuphold (posedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTCTRL_delay); + $setuphold (posedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALUMODE_delay); + $setuphold (posedge CLK, posedge AMULT26, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AMULT26_delay); + $setuphold (posedge CLK, posedge BMULT17, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BMULT17_delay); + $setuphold (posedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CARRYIN_delay); + $setuphold (posedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CARRYINSEL_delay); + $setuphold (posedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEALUMODE_delay); + $setuphold (posedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CECARRYIN_delay); + $setuphold (posedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CECTRL_delay); + $setuphold (posedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEM_delay); + $setuphold (posedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OPMODE_delay); + $setuphold (posedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTALLCARRYIN_delay); + $setuphold (posedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTALUMODE_delay); + $setuphold (posedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTCTRL_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_A_B_DATA.v b/verilog/src/unisims/DSP_A_B_DATA.v new file mode 100644 index 0000000..f7555f0 --- /dev/null +++ b/verilog/src/unisims/DSP_A_B_DATA.v @@ -0,0 +1,598 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_A_B_DATA +// /___/ /\ Filename : DSP_A_B_DATA.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 03/06/13 - 701316 - A_B_reg no clk when REG=0 +// 04/08/13 - 710304 - AREG, BREG, ACASCREG and BCASCREG dynamic registers mis sized. +// 04/22/13 - 714213 - ACOUT, BCOUT wrong logic +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 05/07/13 - 716896 - AREG, BREG, ACASCREG and BCASCREG localparams mis sized. +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_A_B_DATA #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer ACASCREG = 1, + parameter integer AREG = 1, + parameter A_INPUT = "DIRECT", + parameter integer BCASCREG = 1, + parameter integer BREG = 1, + parameter B_INPUT = "DIRECT", + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RSTA_INVERTED = 1'b0, + parameter [0:0] IS_RSTB_INVERTED = 1'b0 +)( + output [26:0] A1_DATA, + output [26:0] A2_DATA, + output [29:0] ACOUT, + output [29:0] A_ALU, + output [17:0] B1_DATA, + output [17:0] B2_DATA, + output [17:0] BCOUT, + output [17:0] B_ALU, + + input [29:0] A, + input [29:0] ACIN, + input [17:0] B, + input [17:0] BCIN, + input CEA1, + input CEA2, + input CEB1, + input CEB2, + input CLK, + input RSTA, + input RSTB +); + +// define constants + localparam MODULE_NAME = "DSP_A_B_DATA"; + +// Parameter encodings and registers + localparam A_INPUT_CASCADE = 1; + localparam A_INPUT_DIRECT = 0; + localparam B_INPUT_CASCADE = 1; + localparam B_INPUT_DIRECT = 0; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_A_B_DATA_dr.v" +`else + reg [31:0] ACASCREG_REG = ACASCREG; + reg [31:0] AREG_REG = AREG; + reg [56:1] A_INPUT_REG = A_INPUT; + reg [31:0] BCASCREG_REG = BCASCREG; + reg [31:0] BREG_REG = BREG; + reg [56:1] B_INPUT_REG = B_INPUT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_RSTA_INVERTED_REG = IS_RSTA_INVERTED; + reg [0:0] IS_RSTB_INVERTED_REG = IS_RSTB_INVERTED; +`endif + +`ifdef XIL_XECLIB + wire [1:0] ACASCREG_BIN; + wire [1:0] AREG_BIN; + wire A_INPUT_BIN; + wire [1:0] BCASCREG_BIN; + wire [1:0] BREG_BIN; + wire B_INPUT_BIN; +`else + reg [1:0] ACASCREG_BIN; + reg [1:0] AREG_BIN; + reg A_INPUT_BIN; + reg [1:0] BCASCREG_BIN; + reg [1:0] BREG_BIN; + reg B_INPUT_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CEA1_in; + wire CEA2_in; + wire CEB1_in; + wire CEB2_in; + wire CLK_in; + wire RSTA_in; + wire RSTB_in; + wire [17:0] BCIN_in; + wire [17:0] B_in; + wire [29:0] ACIN_in; + wire [29:0] A_in; + +`ifdef XIL_TIMING + wire CEA1_delay; + wire CEA2_delay; + wire CEB1_delay; + wire CEB2_delay; + wire CLK_delay; + wire RSTA_delay; + wire RSTB_delay; + wire [17:0] BCIN_delay; + wire [17:0] B_delay; + wire [29:0] ACIN_delay; + wire [29:0] A_delay; +`endif + +`ifdef XIL_TIMING + assign ACIN_in = ACIN_delay; + assign A_in[0] = (A[0] === 1'bz) || A_delay[0]; // rv 1 + assign A_in[10] = (A[10] === 1'bz) || A_delay[10]; // rv 1 + assign A_in[11] = (A[11] === 1'bz) || A_delay[11]; // rv 1 + assign A_in[12] = (A[12] === 1'bz) || A_delay[12]; // rv 1 + assign A_in[13] = (A[13] === 1'bz) || A_delay[13]; // rv 1 + assign A_in[14] = (A[14] === 1'bz) || A_delay[14]; // rv 1 + assign A_in[15] = (A[15] === 1'bz) || A_delay[15]; // rv 1 + assign A_in[16] = (A[16] === 1'bz) || A_delay[16]; // rv 1 + assign A_in[17] = (A[17] === 1'bz) || A_delay[17]; // rv 1 + assign A_in[18] = (A[18] === 1'bz) || A_delay[18]; // rv 1 + assign A_in[19] = (A[19] === 1'bz) || A_delay[19]; // rv 1 + assign A_in[1] = (A[1] === 1'bz) || A_delay[1]; // rv 1 + assign A_in[20] = (A[20] === 1'bz) || A_delay[20]; // rv 1 + assign A_in[21] = (A[21] === 1'bz) || A_delay[21]; // rv 1 + assign A_in[22] = (A[22] === 1'bz) || A_delay[22]; // rv 1 + assign A_in[23] = (A[23] === 1'bz) || A_delay[23]; // rv 1 + assign A_in[24] = (A[24] === 1'bz) || A_delay[24]; // rv 1 + assign A_in[25] = (A[25] === 1'bz) || A_delay[25]; // rv 1 + assign A_in[26] = (A[26] === 1'bz) || A_delay[26]; // rv 1 + assign A_in[27] = (A[27] === 1'bz) || A_delay[27]; // rv 1 + assign A_in[28] = (A[28] === 1'bz) || A_delay[28]; // rv 1 + assign A_in[29] = (A[29] === 1'bz) || A_delay[29]; // rv 1 + assign A_in[2] = (A[2] === 1'bz) || A_delay[2]; // rv 1 + assign A_in[3] = (A[3] === 1'bz) || A_delay[3]; // rv 1 + assign A_in[4] = (A[4] === 1'bz) || A_delay[4]; // rv 1 + assign A_in[5] = (A[5] === 1'bz) || A_delay[5]; // rv 1 + assign A_in[6] = (A[6] === 1'bz) || A_delay[6]; // rv 1 + assign A_in[7] = (A[7] === 1'bz) || A_delay[7]; // rv 1 + assign A_in[8] = (A[8] === 1'bz) || A_delay[8]; // rv 1 + assign A_in[9] = (A[9] === 1'bz) || A_delay[9]; // rv 1 + assign BCIN_in = BCIN_delay; + assign B_in[0] = (B[0] === 1'bz) || B_delay[0]; // rv 1 + assign B_in[10] = (B[10] === 1'bz) || B_delay[10]; // rv 1 + assign B_in[11] = (B[11] === 1'bz) || B_delay[11]; // rv 1 + assign B_in[12] = (B[12] === 1'bz) || B_delay[12]; // rv 1 + assign B_in[13] = (B[13] === 1'bz) || B_delay[13]; // rv 1 + assign B_in[14] = (B[14] === 1'bz) || B_delay[14]; // rv 1 + assign B_in[15] = (B[15] === 1'bz) || B_delay[15]; // rv 1 + assign B_in[16] = (B[16] === 1'bz) || B_delay[16]; // rv 1 + assign B_in[17] = (B[17] === 1'bz) || B_delay[17]; // rv 1 + assign B_in[1] = (B[1] === 1'bz) || B_delay[1]; // rv 1 + assign B_in[2] = (B[2] === 1'bz) || B_delay[2]; // rv 1 + assign B_in[3] = (B[3] === 1'bz) || B_delay[3]; // rv 1 + assign B_in[4] = (B[4] === 1'bz) || B_delay[4]; // rv 1 + assign B_in[5] = (B[5] === 1'bz) || B_delay[5]; // rv 1 + assign B_in[6] = (B[6] === 1'bz) || B_delay[6]; // rv 1 + assign B_in[7] = (B[7] === 1'bz) || B_delay[7]; // rv 1 + assign B_in[8] = (B[8] === 1'bz) || B_delay[8]; // rv 1 + assign B_in[9] = (B[9] === 1'bz) || B_delay[9]; // rv 1 + assign CEA1_in = (CEA1 !== 1'bz) && CEA1_delay; // rv 0 + assign CEA2_in = (CEA2 !== 1'bz) && CEA2_delay; // rv 0 + assign CEB1_in = (CEB1 !== 1'bz) && CEB1_delay; // rv 0 + assign CEB2_in = (CEB2 !== 1'bz) && CEB2_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign RSTA_in = (RSTA !== 1'bz) && (RSTA_delay ^ IS_RSTA_INVERTED_REG); // rv 0 + assign RSTB_in = (RSTB !== 1'bz) && (RSTB_delay ^ IS_RSTB_INVERTED_REG); // rv 0 +`else + assign ACIN_in = ACIN; + assign A_in[0] = (A[0] === 1'bz) || A[0]; // rv 1 + assign A_in[10] = (A[10] === 1'bz) || A[10]; // rv 1 + assign A_in[11] = (A[11] === 1'bz) || A[11]; // rv 1 + assign A_in[12] = (A[12] === 1'bz) || A[12]; // rv 1 + assign A_in[13] = (A[13] === 1'bz) || A[13]; // rv 1 + assign A_in[14] = (A[14] === 1'bz) || A[14]; // rv 1 + assign A_in[15] = (A[15] === 1'bz) || A[15]; // rv 1 + assign A_in[16] = (A[16] === 1'bz) || A[16]; // rv 1 + assign A_in[17] = (A[17] === 1'bz) || A[17]; // rv 1 + assign A_in[18] = (A[18] === 1'bz) || A[18]; // rv 1 + assign A_in[19] = (A[19] === 1'bz) || A[19]; // rv 1 + assign A_in[1] = (A[1] === 1'bz) || A[1]; // rv 1 + assign A_in[20] = (A[20] === 1'bz) || A[20]; // rv 1 + assign A_in[21] = (A[21] === 1'bz) || A[21]; // rv 1 + assign A_in[22] = (A[22] === 1'bz) || A[22]; // rv 1 + assign A_in[23] = (A[23] === 1'bz) || A[23]; // rv 1 + assign A_in[24] = (A[24] === 1'bz) || A[24]; // rv 1 + assign A_in[25] = (A[25] === 1'bz) || A[25]; // rv 1 + assign A_in[26] = (A[26] === 1'bz) || A[26]; // rv 1 + assign A_in[27] = (A[27] === 1'bz) || A[27]; // rv 1 + assign A_in[28] = (A[28] === 1'bz) || A[28]; // rv 1 + assign A_in[29] = (A[29] === 1'bz) || A[29]; // rv 1 + assign A_in[2] = (A[2] === 1'bz) || A[2]; // rv 1 + assign A_in[3] = (A[3] === 1'bz) || A[3]; // rv 1 + assign A_in[4] = (A[4] === 1'bz) || A[4]; // rv 1 + assign A_in[5] = (A[5] === 1'bz) || A[5]; // rv 1 + assign A_in[6] = (A[6] === 1'bz) || A[6]; // rv 1 + assign A_in[7] = (A[7] === 1'bz) || A[7]; // rv 1 + assign A_in[8] = (A[8] === 1'bz) || A[8]; // rv 1 + assign A_in[9] = (A[9] === 1'bz) || A[9]; // rv 1 + assign BCIN_in = BCIN; + assign B_in[0] = (B[0] === 1'bz) || B[0]; // rv 1 + assign B_in[10] = (B[10] === 1'bz) || B[10]; // rv 1 + assign B_in[11] = (B[11] === 1'bz) || B[11]; // rv 1 + assign B_in[12] = (B[12] === 1'bz) || B[12]; // rv 1 + assign B_in[13] = (B[13] === 1'bz) || B[13]; // rv 1 + assign B_in[14] = (B[14] === 1'bz) || B[14]; // rv 1 + assign B_in[15] = (B[15] === 1'bz) || B[15]; // rv 1 + assign B_in[16] = (B[16] === 1'bz) || B[16]; // rv 1 + assign B_in[17] = (B[17] === 1'bz) || B[17]; // rv 1 + assign B_in[1] = (B[1] === 1'bz) || B[1]; // rv 1 + assign B_in[2] = (B[2] === 1'bz) || B[2]; // rv 1 + assign B_in[3] = (B[3] === 1'bz) || B[3]; // rv 1 + assign B_in[4] = (B[4] === 1'bz) || B[4]; // rv 1 + assign B_in[5] = (B[5] === 1'bz) || B[5]; // rv 1 + assign B_in[6] = (B[6] === 1'bz) || B[6]; // rv 1 + assign B_in[7] = (B[7] === 1'bz) || B[7]; // rv 1 + assign B_in[8] = (B[8] === 1'bz) || B[8]; // rv 1 + assign B_in[9] = (B[9] === 1'bz) || B[9]; // rv 1 + assign CEA1_in = (CEA1 !== 1'bz) && CEA1; // rv 0 + assign CEA2_in = (CEA2 !== 1'bz) && CEA2; // rv 0 + assign CEB1_in = (CEB1 !== 1'bz) && CEB1; // rv 0 + assign CEB2_in = (CEB2 !== 1'bz) && CEB2; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign RSTA_in = (RSTA !== 1'bz) && (RSTA ^ IS_RSTA_INVERTED_REG); // rv 0 + assign RSTB_in = (RSTB !== 1'bz) && (RSTB ^ IS_RSTB_INVERTED_REG); // rv 0 +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign ACASCREG_BIN = ACASCREG_REG[1:0]; + + assign AREG_BIN = AREG_REG[1:0]; + + assign A_INPUT_BIN = + (A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT : + (A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE : + A_INPUT_DIRECT; + + assign BCASCREG_BIN = BCASCREG_REG[1:0]; + + assign BREG_BIN = BREG_REG[1:0]; + + assign B_INPUT_BIN = + (B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT : + (B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE : + B_INPUT_DIRECT; + +`else +always @(trig_attr) begin +#1; + ACASCREG_BIN = ACASCREG_REG[1:0]; + + AREG_BIN = AREG_REG[1:0]; + + A_INPUT_BIN = + (A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT : + (A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE : + A_INPUT_DIRECT; + + BCASCREG_BIN = BCASCREG_REG[1:0]; + + BREG_BIN = BREG_REG[1:0]; + + B_INPUT_BIN = + (B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT : + (B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE : + B_INPUT_DIRECT; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ACASCREG_REG != 1) && + (ACASCREG_REG != 0) && + (ACASCREG_REG != 2))) begin + $display("Error: [Unisim %s-101] ACASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, ACASCREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AREG_REG != 1) && + (AREG_REG != 0) && + (AREG_REG != 2))) begin + $display("Error: [Unisim %s-102] AREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, AREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((A_INPUT_REG != "DIRECT") && + (A_INPUT_REG != "CASCADE"))) begin + $display("Error: [Unisim %s-103] A_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, A_INPUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BCASCREG_REG != 1) && + (BCASCREG_REG != 0) && + (BCASCREG_REG != 2))) begin + $display("Error: [Unisim %s-104] BCASCREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BCASCREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BREG_REG != 1) && + (BREG_REG != 0) && + (BREG_REG != 2))) begin + $display("Error: [Unisim %s-105] BREG attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, BREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((B_INPUT_REG != "DIRECT") && + (B_INPUT_REG != "CASCADE"))) begin + $display("Error: [Unisim %s-106] B_INPUT attribute is set to %s. Legal values for this attribute are DIRECT or CASCADE. Instance: %m", MODULE_NAME, B_INPUT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + always @(trig_attr) begin + #1; + case (AREG_REG) + 0, 1 : if (AREG_REG != ACASCREG_REG) begin + $display("Error: [Unisim %s-2] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 0 or 1, ACASCREG must be set to the same value. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG); + attr_err = 1'b1; + end + 2 : if (ACASCREG_REG == 0) begin + $display("Error: [Unisim %s-3] AREG attribute is set to %0d and ACASCREG attribute is set to %0d. When AREG is 2, ACASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, AREG_REG, ACASCREG_REG); + attr_err = 1'b1; + end + endcase + + case (BREG_REG) + 0, 1 : if (BREG_REG != BCASCREG_REG) begin + $display("Error: [Unisim %s-4] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 0 or 1, BCASCREG must be set to the same value. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG); + attr_err = 1'b1; + end + 2 : if (BCASCREG_REG == 0) begin + $display("Error: [Unisim %s-5] BREG attribute is set to %0d and BCASCREG attribute is set to %0d. When BREG is 2, BCASCREG must be set to 1 or 2. Instance: %m", MODULE_NAME, BREG_REG, BCASCREG_REG); + attr_err = 1'b1; + end + endcase + + if (attr_err == 1'b1) #1 $finish; + end + + localparam A_WIDTH = 30; + localparam B_WIDTH = 18; + reg [29:0] A1_reg; + reg [29:0] A2_reg; + wire [17:0] B_BCIN_mux; + reg [17:0] B2_reg; + reg [B_WIDTH-1:0] B1_DATA_out; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + A1_reg = 30'b0; + A2_reg = 30'b0; + B2_reg = 18'b0; + B1_DATA_out = {B_WIDTH{1'b0}}; +end +`endif + +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin + A1_reg <= {A_WIDTH{1'b0}}; + end else if (CEA1_in) begin + if (A_INPUT_BIN == A_INPUT_CASCADE) begin + A1_reg <= ACIN_in; + end else begin + A1_reg <= A_in; + end + end + end + + always @(posedge CLK_in) begin + if (RSTA_in || (AREG_BIN == 2'b00) || glblGSR) begin + A2_reg <= {A_WIDTH{1'b0}}; + end else if (CEA2_in) begin + if (AREG_BIN == 2'b10) begin + A2_reg <= A1_reg; + end else if (A_INPUT_BIN == A_INPUT_CASCADE) begin + A2_reg <= ACIN_in; + end else begin + A2_reg <= A_in; + end + end + end + + assign A_ALU = (AREG_BIN != 2'b00) ? A2_reg : + (A_INPUT_BIN == A_INPUT_CASCADE) ? ACIN_in : + A_in; + +// assumes encoding the same for ACASCREG and AREG + assign ACOUT = (ACASCREG_BIN == AREG_BIN) ? A_ALU : A1_reg; + assign A1_DATA = A1_reg[26:0]; + + assign A2_DATA = A_ALU[26:0]; + + assign B1_DATA = B1_DATA_out; + + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTB_in || (BREG_BIN == 2'b00) || glblGSR) begin + B1_DATA_out <= 18'b0; + end else if (CEB1_in) begin + if (B_INPUT_BIN == B_INPUT_CASCADE) B1_DATA_out <= BCIN_in; + else B1_DATA_out <= B_in; + end + end + + always @(posedge CLK_in) begin + if (RSTB_in || glblGSR) B2_reg <= 18'b0; + else if (CEB2_in) begin + if (BREG_BIN == 2'b10) B2_reg <= B1_DATA_out; + else if (B_INPUT_BIN == B_INPUT_CASCADE) B2_reg <= BCIN_in; + else B2_reg <= B_in; + end + end + + assign B_ALU = (BREG_BIN != 2'b00) ? B2_reg : + (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : + B_in; + + assign B2_DATA = (BREG_BIN != 2'b00) ? B2_reg : + (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : + B_in; + +// assumes encoding the same for BCASCREG and BREG + assign BCOUT = (BCASCREG_BIN == BREG_BIN) ? B2_DATA : B1_DATA_out; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (A *> A2_DATA) = (0:0:0, 0:0:0); + (A *> ACOUT) = (0:0:0, 0:0:0); + (A *> A_ALU) = (0:0:0, 0:0:0); + (ACIN *> A2_DATA) = (0:0:0, 0:0:0); + (ACIN *> ACOUT) = (0:0:0, 0:0:0); + (ACIN *> A_ALU) = (0:0:0, 0:0:0); + (B *> B2_DATA) = (0:0:0, 0:0:0); + (B *> BCOUT) = (0:0:0, 0:0:0); + (B *> B_ALU) = (0:0:0, 0:0:0); + (BCIN *> B2_DATA) = (0:0:0, 0:0:0); + (BCIN *> BCOUT) = (0:0:0, 0:0:0); + (BCIN *> B_ALU) = (0:0:0, 0:0:0); + (CLK *> A1_DATA) = (0:0:0, 0:0:0); + (CLK *> A2_DATA) = (0:0:0, 0:0:0); + (CLK *> ACOUT) = (0:0:0, 0:0:0); + (CLK *> A_ALU) = (0:0:0, 0:0:0); + (CLK *> B1_DATA) = (0:0:0, 0:0:0); + (CLK *> B2_DATA) = (0:0:0, 0:0:0); + (CLK *> BCOUT) = (0:0:0, 0:0:0); + (CLK *> B_ALU) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, A_delay); + $setuphold (negedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ACIN_delay); + $setuphold (negedge CLK, negedge B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, B_delay); + $setuphold (negedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BCIN_delay); + $setuphold (negedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEA1_delay); + $setuphold (negedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEA2_delay); + $setuphold (negedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEB1_delay); + $setuphold (negedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEB2_delay); + $setuphold (negedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTA_delay); + $setuphold (negedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTB_delay); + $setuphold (negedge CLK, posedge A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, A_delay); + $setuphold (negedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ACIN_delay); + $setuphold (negedge CLK, posedge B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, B_delay); + $setuphold (negedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BCIN_delay); + $setuphold (negedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEA1_delay); + $setuphold (negedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEA2_delay); + $setuphold (negedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEB1_delay); + $setuphold (negedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEB2_delay); + $setuphold (negedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTA_delay); + $setuphold (negedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTB_delay); + $setuphold (posedge CLK, negedge A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, A_delay); + $setuphold (posedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ACIN_delay); + $setuphold (posedge CLK, negedge B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, B_delay); + $setuphold (posedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BCIN_delay); + $setuphold (posedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEA1_delay); + $setuphold (posedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEA2_delay); + $setuphold (posedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEB1_delay); + $setuphold (posedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEB2_delay); + $setuphold (posedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTA_delay); + $setuphold (posedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTB_delay); + $setuphold (posedge CLK, posedge A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, A_delay); + $setuphold (posedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ACIN_delay); + $setuphold (posedge CLK, posedge B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, B_delay); + $setuphold (posedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BCIN_delay); + $setuphold (posedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEA1_delay); + $setuphold (posedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEA2_delay); + $setuphold (posedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEB1_delay); + $setuphold (posedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEB2_delay); + $setuphold (posedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTA_delay); + $setuphold (posedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTB_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_C_DATA.v b/verilog/src/unisims/DSP_C_DATA.v new file mode 100644 index 0000000..e62217b --- /dev/null +++ b/verilog/src/unisims/DSP_C_DATA.v @@ -0,0 +1,310 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_C_DATA +// /___/ /\ Filename : DSP_C_DATA.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_C_DATA #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer CREG = 1, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RSTC_INVERTED = 1'b0 +)( + output [47:0] C_DATA, + + input [47:0] C, + input CEC, + input CLK, + input RSTC +); + +// define constants + localparam MODULE_NAME = "DSP_C_DATA"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_C_DATA_dr.v" +`else + reg [31:0] CREG_REG = CREG; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_RSTC_INVERTED_REG = IS_RSTC_INVERTED; +`endif + +`ifdef XIL_XECLIB + wire CREG_BIN; +`else + reg CREG_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CEC_in; + wire CLK_in; + wire RSTC_in; + wire [47:0] C_in; + +`ifdef XIL_TIMING + wire CEC_delay; + wire CLK_delay; + wire RSTC_delay; + wire [47:0] C_delay; +`endif + +`ifdef XIL_TIMING + assign CEC_in = (CEC !== 1'bz) && CEC_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign C_in[0] = (C[0] === 1'bz) || C_delay[0]; // rv 1 + assign C_in[10] = (C[10] === 1'bz) || C_delay[10]; // rv 1 + assign C_in[11] = (C[11] === 1'bz) || C_delay[11]; // rv 1 + assign C_in[12] = (C[12] === 1'bz) || C_delay[12]; // rv 1 + assign C_in[13] = (C[13] === 1'bz) || C_delay[13]; // rv 1 + assign C_in[14] = (C[14] === 1'bz) || C_delay[14]; // rv 1 + assign C_in[15] = (C[15] === 1'bz) || C_delay[15]; // rv 1 + assign C_in[16] = (C[16] === 1'bz) || C_delay[16]; // rv 1 + assign C_in[17] = (C[17] === 1'bz) || C_delay[17]; // rv 1 + assign C_in[18] = (C[18] === 1'bz) || C_delay[18]; // rv 1 + assign C_in[19] = (C[19] === 1'bz) || C_delay[19]; // rv 1 + assign C_in[1] = (C[1] === 1'bz) || C_delay[1]; // rv 1 + assign C_in[20] = (C[20] === 1'bz) || C_delay[20]; // rv 1 + assign C_in[21] = (C[21] === 1'bz) || C_delay[21]; // rv 1 + assign C_in[22] = (C[22] === 1'bz) || C_delay[22]; // rv 1 + assign C_in[23] = (C[23] === 1'bz) || C_delay[23]; // rv 1 + assign C_in[24] = (C[24] === 1'bz) || C_delay[24]; // rv 1 + assign C_in[25] = (C[25] === 1'bz) || C_delay[25]; // rv 1 + assign C_in[26] = (C[26] === 1'bz) || C_delay[26]; // rv 1 + assign C_in[27] = (C[27] === 1'bz) || C_delay[27]; // rv 1 + assign C_in[28] = (C[28] === 1'bz) || C_delay[28]; // rv 1 + assign C_in[29] = (C[29] === 1'bz) || C_delay[29]; // rv 1 + assign C_in[2] = (C[2] === 1'bz) || C_delay[2]; // rv 1 + assign C_in[30] = (C[30] === 1'bz) || C_delay[30]; // rv 1 + assign C_in[31] = (C[31] === 1'bz) || C_delay[31]; // rv 1 + assign C_in[32] = (C[32] === 1'bz) || C_delay[32]; // rv 1 + assign C_in[33] = (C[33] === 1'bz) || C_delay[33]; // rv 1 + assign C_in[34] = (C[34] === 1'bz) || C_delay[34]; // rv 1 + assign C_in[35] = (C[35] === 1'bz) || C_delay[35]; // rv 1 + assign C_in[36] = (C[36] === 1'bz) || C_delay[36]; // rv 1 + assign C_in[37] = (C[37] === 1'bz) || C_delay[37]; // rv 1 + assign C_in[38] = (C[38] === 1'bz) || C_delay[38]; // rv 1 + assign C_in[39] = (C[39] === 1'bz) || C_delay[39]; // rv 1 + assign C_in[3] = (C[3] === 1'bz) || C_delay[3]; // rv 1 + assign C_in[40] = (C[40] === 1'bz) || C_delay[40]; // rv 1 + assign C_in[41] = (C[41] === 1'bz) || C_delay[41]; // rv 1 + assign C_in[42] = (C[42] === 1'bz) || C_delay[42]; // rv 1 + assign C_in[43] = (C[43] === 1'bz) || C_delay[43]; // rv 1 + assign C_in[44] = (C[44] === 1'bz) || C_delay[44]; // rv 1 + assign C_in[45] = (C[45] === 1'bz) || C_delay[45]; // rv 1 + assign C_in[46] = (C[46] === 1'bz) || C_delay[46]; // rv 1 + assign C_in[47] = (C[47] === 1'bz) || C_delay[47]; // rv 1 + assign C_in[4] = (C[4] === 1'bz) || C_delay[4]; // rv 1 + assign C_in[5] = (C[5] === 1'bz) || C_delay[5]; // rv 1 + assign C_in[6] = (C[6] === 1'bz) || C_delay[6]; // rv 1 + assign C_in[7] = (C[7] === 1'bz) || C_delay[7]; // rv 1 + assign C_in[8] = (C[8] === 1'bz) || C_delay[8]; // rv 1 + assign C_in[9] = (C[9] === 1'bz) || C_delay[9]; // rv 1 + assign RSTC_in = (RSTC !== 1'bz) && (RSTC_delay ^ IS_RSTC_INVERTED_REG); // rv 0 +`else + assign CEC_in = (CEC !== 1'bz) && CEC; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign C_in[0] = (C[0] === 1'bz) || C[0]; // rv 1 + assign C_in[10] = (C[10] === 1'bz) || C[10]; // rv 1 + assign C_in[11] = (C[11] === 1'bz) || C[11]; // rv 1 + assign C_in[12] = (C[12] === 1'bz) || C[12]; // rv 1 + assign C_in[13] = (C[13] === 1'bz) || C[13]; // rv 1 + assign C_in[14] = (C[14] === 1'bz) || C[14]; // rv 1 + assign C_in[15] = (C[15] === 1'bz) || C[15]; // rv 1 + assign C_in[16] = (C[16] === 1'bz) || C[16]; // rv 1 + assign C_in[17] = (C[17] === 1'bz) || C[17]; // rv 1 + assign C_in[18] = (C[18] === 1'bz) || C[18]; // rv 1 + assign C_in[19] = (C[19] === 1'bz) || C[19]; // rv 1 + assign C_in[1] = (C[1] === 1'bz) || C[1]; // rv 1 + assign C_in[20] = (C[20] === 1'bz) || C[20]; // rv 1 + assign C_in[21] = (C[21] === 1'bz) || C[21]; // rv 1 + assign C_in[22] = (C[22] === 1'bz) || C[22]; // rv 1 + assign C_in[23] = (C[23] === 1'bz) || C[23]; // rv 1 + assign C_in[24] = (C[24] === 1'bz) || C[24]; // rv 1 + assign C_in[25] = (C[25] === 1'bz) || C[25]; // rv 1 + assign C_in[26] = (C[26] === 1'bz) || C[26]; // rv 1 + assign C_in[27] = (C[27] === 1'bz) || C[27]; // rv 1 + assign C_in[28] = (C[28] === 1'bz) || C[28]; // rv 1 + assign C_in[29] = (C[29] === 1'bz) || C[29]; // rv 1 + assign C_in[2] = (C[2] === 1'bz) || C[2]; // rv 1 + assign C_in[30] = (C[30] === 1'bz) || C[30]; // rv 1 + assign C_in[31] = (C[31] === 1'bz) || C[31]; // rv 1 + assign C_in[32] = (C[32] === 1'bz) || C[32]; // rv 1 + assign C_in[33] = (C[33] === 1'bz) || C[33]; // rv 1 + assign C_in[34] = (C[34] === 1'bz) || C[34]; // rv 1 + assign C_in[35] = (C[35] === 1'bz) || C[35]; // rv 1 + assign C_in[36] = (C[36] === 1'bz) || C[36]; // rv 1 + assign C_in[37] = (C[37] === 1'bz) || C[37]; // rv 1 + assign C_in[38] = (C[38] === 1'bz) || C[38]; // rv 1 + assign C_in[39] = (C[39] === 1'bz) || C[39]; // rv 1 + assign C_in[3] = (C[3] === 1'bz) || C[3]; // rv 1 + assign C_in[40] = (C[40] === 1'bz) || C[40]; // rv 1 + assign C_in[41] = (C[41] === 1'bz) || C[41]; // rv 1 + assign C_in[42] = (C[42] === 1'bz) || C[42]; // rv 1 + assign C_in[43] = (C[43] === 1'bz) || C[43]; // rv 1 + assign C_in[44] = (C[44] === 1'bz) || C[44]; // rv 1 + assign C_in[45] = (C[45] === 1'bz) || C[45]; // rv 1 + assign C_in[46] = (C[46] === 1'bz) || C[46]; // rv 1 + assign C_in[47] = (C[47] === 1'bz) || C[47]; // rv 1 + assign C_in[4] = (C[4] === 1'bz) || C[4]; // rv 1 + assign C_in[5] = (C[5] === 1'bz) || C[5]; // rv 1 + assign C_in[6] = (C[6] === 1'bz) || C[6]; // rv 1 + assign C_in[7] = (C[7] === 1'bz) || C[7]; // rv 1 + assign C_in[8] = (C[8] === 1'bz) || C[8]; // rv 1 + assign C_in[9] = (C[9] === 1'bz) || C[9]; // rv 1 + assign RSTC_in = (RSTC !== 1'bz) && (RSTC ^ IS_RSTC_INVERTED_REG); // rv 0 +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign CREG_BIN = CREG_REG[0]; + +`else +always @(trig_attr) begin +#1; + CREG_BIN = CREG_REG[0]; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CREG_REG != 1) && + (CREG_REG != 0))) begin + $display("Error: [Unisim %s-101] CREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, CREG_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam C_WIDTH = 48; + reg [C_WIDTH-1:0] C_reg; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + C_reg = {C_WIDTH{1'b0}}; +end +`endif + +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTC_in || (CREG_BIN == 1'b0) || glblGSR) begin + C_reg <= 48'b0; + end else if (CEC_in) begin + C_reg <= C_in; + end + end + + assign C_DATA = (CREG_BIN == 1'b1) ? C_reg : C_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (C *> C_DATA) = (0:0:0, 0:0:0); + (CLK *> C_DATA) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge CLK, negedge C, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, C_delay); + $setuphold (negedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEC_delay); + $setuphold (negedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTC_delay); + $setuphold (negedge CLK, posedge C, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, C_delay); + $setuphold (negedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEC_delay); + $setuphold (negedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTC_delay); + $setuphold (posedge CLK, negedge C, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, C_delay); + $setuphold (posedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEC_delay); + $setuphold (posedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTC_delay); + $setuphold (posedge CLK, posedge C, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, C_delay); + $setuphold (posedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEC_delay); + $setuphold (posedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTC_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_MULTIPLIER.v b/verilog/src/unisims/DSP_MULTIPLIER.v new file mode 100644 index 0000000..015e9ac --- /dev/null +++ b/verilog/src/unisims/DSP_MULTIPLIER.v @@ -0,0 +1,3836 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_MULTIPLIER +// /___/ /\ Filename : DSP_MULTIPLIER.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_MULTIPLIER #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter AMULTSEL = "A", + parameter BMULTSEL = "B", + parameter USE_MULT = "MULTIPLY" +)( + output AMULT26, + output BMULT17, + output [44:0] U, + output [44:0] V, + + input [26:0] A2A1, + input [26:0] AD_DATA, + input [17:0] B2B1 +); + +// define constants + localparam MODULE_NAME = "DSP_MULTIPLIER"; + +// Parameter encodings and registers + localparam AMULTSEL_A = 0; + localparam AMULTSEL_AD = 1; + localparam BMULTSEL_AD = 1; + localparam BMULTSEL_B = 0; + localparam USE_MULT_DYNAMIC = 1; + localparam USE_MULT_MULTIPLY = 0; + localparam USE_MULT_NONE = 2; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_MULTIPLIER_dr.v" +`else + reg [16:1] AMULTSEL_REG = AMULTSEL; + reg [16:1] BMULTSEL_REG = BMULTSEL; + reg [64:1] USE_MULT_REG = USE_MULT; +`endif + +`ifdef XIL_XECLIB + wire AMULTSEL_BIN; + wire BMULTSEL_BIN; + wire [1:0] USE_MULT_BIN; +`else + reg AMULTSEL_BIN; + reg BMULTSEL_BIN; + reg [1:0] USE_MULT_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + assign BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + assign USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + +`else +always @(trig_attr) begin +#1; + AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((AMULTSEL_REG != "A") && + (AMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-101] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BMULTSEL_REG != "B") && + (BMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-102] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_MULT_REG != "MULTIPLY") && + (USE_MULT_REG != "DYNAMIC") && + (USE_MULT_REG != "NONE"))) begin + $display("Error: [Unisim %s-103] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +// begin behavioral model + + localparam M_WIDTH = 45; + reg [17:0] b_mult_mux; + reg [26:0] a_mult_mux; + reg [M_WIDTH-1:0] mult; + reg [M_WIDTH-2:0] ps_u_mask; + reg [M_WIDTH-2:0] ps_v_mask; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + ps_u_mask = 44'h55555555555; + ps_v_mask = 44'haaaaaaaaaaa; +end +`endif + +always @(*) begin + if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1; + else a_mult_mux = AD_DATA; +end +always @(*) begin + if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1; + else b_mult_mux = AD_DATA; +end + + assign AMULT26 = a_mult_mux[26]; + assign BMULT17 = b_mult_mux[17]; +// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1 + assign U = {1'b1, mult[43:0] & ps_u_mask}; + assign V = {~mult[44], mult[43:0] & ps_v_mask}; + +always @(*) begin + if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0; + else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux}); +end + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (A2A1[0] => U[10]) = (0:0:0, 0:0:0); + (A2A1[0] => U[11]) = (0:0:0, 0:0:0); + (A2A1[0] => U[12]) = (0:0:0, 0:0:0); + (A2A1[0] => U[13]) = (0:0:0, 0:0:0); + (A2A1[0] => U[14]) = (0:0:0, 0:0:0); + (A2A1[0] => U[15]) = (0:0:0, 0:0:0); + (A2A1[0] => U[16]) = (0:0:0, 0:0:0); + (A2A1[0] => U[17]) = (0:0:0, 0:0:0); + (A2A1[0] => U[18]) = (0:0:0, 0:0:0); + (A2A1[0] => U[19]) = (0:0:0, 0:0:0); + (A2A1[0] => U[1]) = (0:0:0, 0:0:0); + (A2A1[0] => U[20]) = (0:0:0, 0:0:0); + (A2A1[0] => U[21]) = (0:0:0, 0:0:0); + (A2A1[0] => U[2]) = (0:0:0, 0:0:0); + (A2A1[0] => U[3]) = (0:0:0, 0:0:0); + (A2A1[0] => U[4]) = (0:0:0, 0:0:0); + (A2A1[0] => U[5]) = (0:0:0, 0:0:0); + (A2A1[0] => U[6]) = (0:0:0, 0:0:0); + (A2A1[0] => U[7]) = (0:0:0, 0:0:0); + (A2A1[0] => U[8]) = (0:0:0, 0:0:0); + (A2A1[0] => U[9]) = (0:0:0, 0:0:0); + (A2A1[0] => V[0]) = (0:0:0, 0:0:0); + (A2A1[0] => V[10]) = (0:0:0, 0:0:0); + (A2A1[0] => V[11]) = (0:0:0, 0:0:0); + (A2A1[0] => V[12]) = (0:0:0, 0:0:0); + (A2A1[0] => V[13]) = (0:0:0, 0:0:0); + (A2A1[0] => V[14]) = (0:0:0, 0:0:0); + (A2A1[0] => V[15]) = (0:0:0, 0:0:0); + (A2A1[0] => V[16]) = (0:0:0, 0:0:0); + (A2A1[0] => V[17]) = (0:0:0, 0:0:0); + (A2A1[0] => V[18]) = (0:0:0, 0:0:0); + (A2A1[0] => V[19]) = (0:0:0, 0:0:0); + (A2A1[0] => V[20]) = (0:0:0, 0:0:0); + (A2A1[0] => V[4]) = (0:0:0, 0:0:0); + (A2A1[0] => V[5]) = (0:0:0, 0:0:0); + (A2A1[0] => V[6]) = (0:0:0, 0:0:0); + (A2A1[0] => V[7]) = (0:0:0, 0:0:0); + (A2A1[0] => V[8]) = (0:0:0, 0:0:0); + (A2A1[0] => V[9]) = (0:0:0, 0:0:0); + (A2A1[10] => U[11]) = (0:0:0, 0:0:0); + (A2A1[10] => U[12]) = (0:0:0, 0:0:0); + (A2A1[10] => U[13]) = (0:0:0, 0:0:0); + (A2A1[10] => U[14]) = (0:0:0, 0:0:0); + (A2A1[10] => U[15]) = (0:0:0, 0:0:0); + (A2A1[10] => U[16]) = (0:0:0, 0:0:0); + (A2A1[10] => U[17]) = (0:0:0, 0:0:0); + (A2A1[10] => U[18]) = (0:0:0, 0:0:0); + (A2A1[10] => U[19]) = (0:0:0, 0:0:0); + (A2A1[10] => U[20]) = (0:0:0, 0:0:0); + (A2A1[10] => U[21]) = (0:0:0, 0:0:0); + (A2A1[10] => U[22]) = (0:0:0, 0:0:0); + (A2A1[10] => U[23]) = (0:0:0, 0:0:0); + (A2A1[10] => U[24]) = (0:0:0, 0:0:0); + (A2A1[10] => U[25]) = (0:0:0, 0:0:0); + (A2A1[10] => U[26]) = (0:0:0, 0:0:0); + (A2A1[10] => U[27]) = (0:0:0, 0:0:0); + (A2A1[10] => U[28]) = (0:0:0, 0:0:0); + (A2A1[10] => U[29]) = (0:0:0, 0:0:0); + (A2A1[10] => U[30]) = (0:0:0, 0:0:0); + (A2A1[10] => U[31]) = (0:0:0, 0:0:0); + (A2A1[10] => V[10]) = (0:0:0, 0:0:0); + (A2A1[10] => V[11]) = (0:0:0, 0:0:0); + (A2A1[10] => V[12]) = (0:0:0, 0:0:0); + (A2A1[10] => V[13]) = (0:0:0, 0:0:0); + (A2A1[10] => V[14]) = (0:0:0, 0:0:0); + (A2A1[10] => V[15]) = (0:0:0, 0:0:0); + (A2A1[10] => V[16]) = (0:0:0, 0:0:0); + (A2A1[10] => V[17]) = (0:0:0, 0:0:0); + (A2A1[10] => V[18]) = (0:0:0, 0:0:0); + (A2A1[10] => V[19]) = (0:0:0, 0:0:0); + (A2A1[10] => V[20]) = (0:0:0, 0:0:0); + (A2A1[10] => V[21]) = (0:0:0, 0:0:0); + (A2A1[10] => V[22]) = (0:0:0, 0:0:0); + (A2A1[10] => V[23]) = (0:0:0, 0:0:0); + (A2A1[10] => V[24]) = (0:0:0, 0:0:0); + (A2A1[10] => V[25]) = (0:0:0, 0:0:0); + (A2A1[10] => V[26]) = (0:0:0, 0:0:0); + (A2A1[10] => V[27]) = (0:0:0, 0:0:0); + (A2A1[10] => V[28]) = (0:0:0, 0:0:0); + (A2A1[10] => V[29]) = (0:0:0, 0:0:0); + (A2A1[10] => V[30]) = (0:0:0, 0:0:0); + (A2A1[11] => U[12]) = (0:0:0, 0:0:0); + (A2A1[11] => U[13]) = (0:0:0, 0:0:0); + (A2A1[11] => U[14]) = (0:0:0, 0:0:0); + (A2A1[11] => U[15]) = (0:0:0, 0:0:0); + (A2A1[11] => U[16]) = (0:0:0, 0:0:0); + (A2A1[11] => U[17]) = (0:0:0, 0:0:0); + (A2A1[11] => U[18]) = (0:0:0, 0:0:0); + (A2A1[11] => U[19]) = (0:0:0, 0:0:0); + (A2A1[11] => U[20]) = (0:0:0, 0:0:0); + (A2A1[11] => U[21]) = (0:0:0, 0:0:0); + (A2A1[11] => U[22]) = (0:0:0, 0:0:0); + (A2A1[11] => U[23]) = (0:0:0, 0:0:0); + (A2A1[11] => U[24]) = (0:0:0, 0:0:0); + (A2A1[11] => U[25]) = (0:0:0, 0:0:0); + (A2A1[11] => U[26]) = (0:0:0, 0:0:0); + (A2A1[11] => U[27]) = (0:0:0, 0:0:0); + (A2A1[11] => U[28]) = (0:0:0, 0:0:0); + (A2A1[11] => U[29]) = (0:0:0, 0:0:0); + (A2A1[11] => U[30]) = (0:0:0, 0:0:0); + (A2A1[11] => U[31]) = (0:0:0, 0:0:0); + (A2A1[11] => U[32]) = (0:0:0, 0:0:0); + (A2A1[11] => V[11]) = (0:0:0, 0:0:0); + (A2A1[11] => V[12]) = (0:0:0, 0:0:0); + (A2A1[11] => V[13]) = (0:0:0, 0:0:0); + (A2A1[11] => V[14]) = (0:0:0, 0:0:0); + (A2A1[11] => V[15]) = (0:0:0, 0:0:0); + (A2A1[11] => V[16]) = (0:0:0, 0:0:0); + (A2A1[11] => V[17]) = (0:0:0, 0:0:0); + (A2A1[11] => V[18]) = (0:0:0, 0:0:0); + (A2A1[11] => V[19]) = (0:0:0, 0:0:0); + (A2A1[11] => V[20]) = (0:0:0, 0:0:0); + (A2A1[11] => V[21]) = (0:0:0, 0:0:0); + (A2A1[11] => V[22]) = (0:0:0, 0:0:0); + (A2A1[11] => V[23]) = (0:0:0, 0:0:0); + (A2A1[11] => V[24]) = (0:0:0, 0:0:0); + (A2A1[11] => V[25]) = (0:0:0, 0:0:0); + (A2A1[11] => V[26]) = (0:0:0, 0:0:0); + (A2A1[11] => V[27]) = (0:0:0, 0:0:0); + (A2A1[11] => V[28]) = (0:0:0, 0:0:0); + (A2A1[11] => V[29]) = (0:0:0, 0:0:0); + (A2A1[11] => V[30]) = (0:0:0, 0:0:0); + (A2A1[11] => V[31]) = (0:0:0, 0:0:0); + (A2A1[12] => U[13]) = (0:0:0, 0:0:0); + (A2A1[12] => U[14]) = (0:0:0, 0:0:0); + (A2A1[12] => U[15]) = (0:0:0, 0:0:0); + (A2A1[12] => U[16]) = (0:0:0, 0:0:0); + (A2A1[12] => U[17]) = (0:0:0, 0:0:0); + (A2A1[12] => U[18]) = (0:0:0, 0:0:0); + (A2A1[12] => U[19]) = (0:0:0, 0:0:0); + (A2A1[12] => U[20]) = (0:0:0, 0:0:0); + (A2A1[12] => U[21]) = (0:0:0, 0:0:0); + (A2A1[12] => U[22]) = (0:0:0, 0:0:0); + (A2A1[12] => U[23]) = (0:0:0, 0:0:0); + (A2A1[12] => U[24]) = (0:0:0, 0:0:0); + (A2A1[12] => U[25]) = (0:0:0, 0:0:0); + (A2A1[12] => U[26]) = (0:0:0, 0:0:0); + (A2A1[12] => U[27]) = (0:0:0, 0:0:0); + (A2A1[12] => U[28]) = (0:0:0, 0:0:0); + (A2A1[12] => U[29]) = (0:0:0, 0:0:0); + (A2A1[12] => U[30]) = (0:0:0, 0:0:0); + (A2A1[12] => U[31]) = (0:0:0, 0:0:0); + (A2A1[12] => U[32]) = (0:0:0, 0:0:0); + (A2A1[12] => U[33]) = (0:0:0, 0:0:0); + (A2A1[12] => V[12]) = (0:0:0, 0:0:0); + (A2A1[12] => V[13]) = (0:0:0, 0:0:0); + (A2A1[12] => V[14]) = (0:0:0, 0:0:0); + (A2A1[12] => V[15]) = (0:0:0, 0:0:0); + (A2A1[12] => V[16]) = (0:0:0, 0:0:0); + (A2A1[12] => V[17]) = (0:0:0, 0:0:0); + (A2A1[12] => V[18]) = (0:0:0, 0:0:0); + (A2A1[12] => V[19]) = (0:0:0, 0:0:0); + (A2A1[12] => V[20]) = (0:0:0, 0:0:0); + (A2A1[12] => V[21]) = (0:0:0, 0:0:0); + (A2A1[12] => V[22]) = (0:0:0, 0:0:0); + (A2A1[12] => V[23]) = (0:0:0, 0:0:0); + (A2A1[12] => V[24]) = (0:0:0, 0:0:0); + (A2A1[12] => V[25]) = (0:0:0, 0:0:0); + (A2A1[12] => V[26]) = (0:0:0, 0:0:0); + (A2A1[12] => V[27]) = (0:0:0, 0:0:0); + (A2A1[12] => V[28]) = (0:0:0, 0:0:0); + (A2A1[12] => V[29]) = (0:0:0, 0:0:0); + (A2A1[12] => V[30]) = (0:0:0, 0:0:0); + (A2A1[12] => V[31]) = (0:0:0, 0:0:0); + (A2A1[12] => V[32]) = (0:0:0, 0:0:0); + (A2A1[13] => U[14]) = (0:0:0, 0:0:0); + (A2A1[13] => U[15]) = (0:0:0, 0:0:0); + (A2A1[13] => U[16]) = (0:0:0, 0:0:0); + (A2A1[13] => U[17]) = (0:0:0, 0:0:0); + (A2A1[13] => U[18]) = (0:0:0, 0:0:0); + (A2A1[13] => U[19]) = (0:0:0, 0:0:0); + (A2A1[13] => U[20]) = (0:0:0, 0:0:0); + (A2A1[13] => U[21]) = (0:0:0, 0:0:0); + (A2A1[13] => U[22]) = (0:0:0, 0:0:0); + (A2A1[13] => U[23]) = (0:0:0, 0:0:0); + (A2A1[13] => U[24]) = (0:0:0, 0:0:0); + (A2A1[13] => U[25]) = (0:0:0, 0:0:0); + (A2A1[13] => U[26]) = (0:0:0, 0:0:0); + (A2A1[13] => U[27]) = (0:0:0, 0:0:0); + (A2A1[13] => U[28]) = (0:0:0, 0:0:0); + (A2A1[13] => U[29]) = (0:0:0, 0:0:0); + (A2A1[13] => U[30]) = (0:0:0, 0:0:0); + (A2A1[13] => U[31]) = (0:0:0, 0:0:0); + (A2A1[13] => U[32]) = (0:0:0, 0:0:0); + (A2A1[13] => U[33]) = (0:0:0, 0:0:0); + (A2A1[13] => U[34]) = (0:0:0, 0:0:0); + (A2A1[13] => V[13]) = (0:0:0, 0:0:0); + (A2A1[13] => V[14]) = (0:0:0, 0:0:0); + (A2A1[13] => V[15]) = (0:0:0, 0:0:0); + (A2A1[13] => V[16]) = (0:0:0, 0:0:0); + (A2A1[13] => V[17]) = (0:0:0, 0:0:0); + (A2A1[13] => V[18]) = (0:0:0, 0:0:0); + (A2A1[13] => V[19]) = (0:0:0, 0:0:0); + (A2A1[13] => V[20]) = (0:0:0, 0:0:0); + (A2A1[13] => V[21]) = (0:0:0, 0:0:0); + (A2A1[13] => V[22]) = (0:0:0, 0:0:0); + (A2A1[13] => V[23]) = (0:0:0, 0:0:0); + (A2A1[13] => V[24]) = (0:0:0, 0:0:0); + (A2A1[13] => V[25]) = (0:0:0, 0:0:0); + (A2A1[13] => V[26]) = (0:0:0, 0:0:0); + (A2A1[13] => V[27]) = (0:0:0, 0:0:0); + (A2A1[13] => V[28]) = (0:0:0, 0:0:0); + (A2A1[13] => V[29]) = (0:0:0, 0:0:0); + (A2A1[13] => V[30]) = (0:0:0, 0:0:0); + (A2A1[13] => V[31]) = (0:0:0, 0:0:0); + (A2A1[13] => V[32]) = (0:0:0, 0:0:0); + (A2A1[13] => V[33]) = (0:0:0, 0:0:0); + (A2A1[14] => U[15]) = (0:0:0, 0:0:0); + (A2A1[14] => U[16]) = (0:0:0, 0:0:0); + (A2A1[14] => U[17]) = (0:0:0, 0:0:0); + (A2A1[14] => U[18]) = (0:0:0, 0:0:0); + (A2A1[14] => U[19]) = (0:0:0, 0:0:0); + (A2A1[14] => U[20]) = (0:0:0, 0:0:0); + (A2A1[14] => U[21]) = (0:0:0, 0:0:0); + (A2A1[14] => U[22]) = (0:0:0, 0:0:0); + (A2A1[14] => U[23]) = (0:0:0, 0:0:0); + (A2A1[14] => U[24]) = (0:0:0, 0:0:0); + (A2A1[14] => U[25]) = (0:0:0, 0:0:0); + (A2A1[14] => U[26]) = (0:0:0, 0:0:0); + (A2A1[14] => U[27]) = (0:0:0, 0:0:0); + (A2A1[14] => U[28]) = (0:0:0, 0:0:0); + (A2A1[14] => U[29]) = (0:0:0, 0:0:0); + (A2A1[14] => U[30]) = (0:0:0, 0:0:0); + (A2A1[14] => U[31]) = (0:0:0, 0:0:0); + (A2A1[14] => U[32]) = (0:0:0, 0:0:0); + (A2A1[14] => U[33]) = (0:0:0, 0:0:0); + (A2A1[14] => U[34]) = (0:0:0, 0:0:0); + (A2A1[14] => V[14]) = (0:0:0, 0:0:0); + (A2A1[14] => V[15]) = (0:0:0, 0:0:0); + (A2A1[14] => V[16]) = (0:0:0, 0:0:0); + (A2A1[14] => V[17]) = (0:0:0, 0:0:0); + (A2A1[14] => V[18]) = (0:0:0, 0:0:0); + (A2A1[14] => V[19]) = (0:0:0, 0:0:0); + (A2A1[14] => V[20]) = (0:0:0, 0:0:0); + (A2A1[14] => V[21]) = (0:0:0, 0:0:0); + (A2A1[14] => V[22]) = (0:0:0, 0:0:0); + (A2A1[14] => V[23]) = (0:0:0, 0:0:0); + (A2A1[14] => V[24]) = (0:0:0, 0:0:0); + (A2A1[14] => V[25]) = (0:0:0, 0:0:0); + (A2A1[14] => V[26]) = (0:0:0, 0:0:0); + (A2A1[14] => V[27]) = (0:0:0, 0:0:0); + (A2A1[14] => V[28]) = (0:0:0, 0:0:0); + (A2A1[14] => V[29]) = (0:0:0, 0:0:0); + (A2A1[14] => V[30]) = (0:0:0, 0:0:0); + (A2A1[14] => V[31]) = (0:0:0, 0:0:0); + (A2A1[14] => V[32]) = (0:0:0, 0:0:0); + (A2A1[14] => V[33]) = (0:0:0, 0:0:0); + (A2A1[15] => U[16]) = (0:0:0, 0:0:0); + (A2A1[15] => U[17]) = (0:0:0, 0:0:0); + (A2A1[15] => U[18]) = (0:0:0, 0:0:0); + (A2A1[15] => U[19]) = (0:0:0, 0:0:0); + (A2A1[15] => U[20]) = (0:0:0, 0:0:0); + (A2A1[15] => U[21]) = (0:0:0, 0:0:0); + (A2A1[15] => U[22]) = (0:0:0, 0:0:0); + (A2A1[15] => U[23]) = (0:0:0, 0:0:0); + (A2A1[15] => U[24]) = (0:0:0, 0:0:0); + (A2A1[15] => U[25]) = (0:0:0, 0:0:0); + (A2A1[15] => U[26]) = (0:0:0, 0:0:0); + (A2A1[15] => U[27]) = (0:0:0, 0:0:0); + (A2A1[15] => U[28]) = (0:0:0, 0:0:0); + (A2A1[15] => U[29]) = (0:0:0, 0:0:0); + (A2A1[15] => U[30]) = (0:0:0, 0:0:0); + (A2A1[15] => U[31]) = (0:0:0, 0:0:0); + (A2A1[15] => U[32]) = (0:0:0, 0:0:0); + (A2A1[15] => U[33]) = (0:0:0, 0:0:0); + (A2A1[15] => U[34]) = (0:0:0, 0:0:0); + (A2A1[15] => U[35]) = (0:0:0, 0:0:0); + (A2A1[15] => U[36]) = (0:0:0, 0:0:0); + (A2A1[15] => V[15]) = (0:0:0, 0:0:0); + (A2A1[15] => V[16]) = (0:0:0, 0:0:0); + (A2A1[15] => V[17]) = (0:0:0, 0:0:0); + (A2A1[15] => V[18]) = (0:0:0, 0:0:0); + (A2A1[15] => V[19]) = (0:0:0, 0:0:0); + (A2A1[15] => V[20]) = (0:0:0, 0:0:0); + (A2A1[15] => V[21]) = (0:0:0, 0:0:0); + (A2A1[15] => V[22]) = (0:0:0, 0:0:0); + (A2A1[15] => V[23]) = (0:0:0, 0:0:0); + (A2A1[15] => V[24]) = (0:0:0, 0:0:0); + (A2A1[15] => V[25]) = (0:0:0, 0:0:0); + (A2A1[15] => V[26]) = (0:0:0, 0:0:0); + (A2A1[15] => V[27]) = (0:0:0, 0:0:0); + (A2A1[15] => V[28]) = (0:0:0, 0:0:0); + (A2A1[15] => V[29]) = (0:0:0, 0:0:0); + (A2A1[15] => V[30]) = (0:0:0, 0:0:0); + (A2A1[15] => V[31]) = (0:0:0, 0:0:0); + (A2A1[15] => V[32]) = (0:0:0, 0:0:0); + (A2A1[15] => V[33]) = (0:0:0, 0:0:0); + (A2A1[15] => V[34]) = (0:0:0, 0:0:0); + (A2A1[15] => V[35]) = (0:0:0, 0:0:0); + (A2A1[16] => U[17]) = (0:0:0, 0:0:0); + (A2A1[16] => U[18]) = (0:0:0, 0:0:0); + (A2A1[16] => U[19]) = (0:0:0, 0:0:0); + (A2A1[16] => U[20]) = (0:0:0, 0:0:0); + (A2A1[16] => U[21]) = (0:0:0, 0:0:0); + (A2A1[16] => U[22]) = (0:0:0, 0:0:0); + (A2A1[16] => U[23]) = (0:0:0, 0:0:0); + (A2A1[16] => U[24]) = (0:0:0, 0:0:0); + (A2A1[16] => U[25]) = (0:0:0, 0:0:0); + (A2A1[16] => U[26]) = (0:0:0, 0:0:0); + (A2A1[16] => U[27]) = (0:0:0, 0:0:0); + (A2A1[16] => U[28]) = (0:0:0, 0:0:0); + (A2A1[16] => U[29]) = (0:0:0, 0:0:0); + (A2A1[16] => U[30]) = (0:0:0, 0:0:0); + (A2A1[16] => U[31]) = (0:0:0, 0:0:0); + (A2A1[16] => U[32]) = (0:0:0, 0:0:0); + (A2A1[16] => U[33]) = (0:0:0, 0:0:0); + (A2A1[16] => U[34]) = (0:0:0, 0:0:0); + (A2A1[16] => U[35]) = (0:0:0, 0:0:0); + (A2A1[16] => U[36]) = (0:0:0, 0:0:0); + (A2A1[16] => V[16]) = (0:0:0, 0:0:0); + (A2A1[16] => V[17]) = (0:0:0, 0:0:0); + (A2A1[16] => V[18]) = (0:0:0, 0:0:0); + (A2A1[16] => V[19]) = (0:0:0, 0:0:0); + (A2A1[16] => V[20]) = (0:0:0, 0:0:0); + (A2A1[16] => V[21]) = (0:0:0, 0:0:0); + (A2A1[16] => V[22]) = (0:0:0, 0:0:0); + (A2A1[16] => V[23]) = (0:0:0, 0:0:0); + (A2A1[16] => V[24]) = (0:0:0, 0:0:0); + (A2A1[16] => V[25]) = (0:0:0, 0:0:0); + (A2A1[16] => V[26]) = (0:0:0, 0:0:0); + (A2A1[16] => V[27]) = (0:0:0, 0:0:0); + (A2A1[16] => V[28]) = (0:0:0, 0:0:0); + (A2A1[16] => V[29]) = (0:0:0, 0:0:0); + (A2A1[16] => V[30]) = (0:0:0, 0:0:0); + (A2A1[16] => V[31]) = (0:0:0, 0:0:0); + (A2A1[16] => V[32]) = (0:0:0, 0:0:0); + (A2A1[16] => V[33]) = (0:0:0, 0:0:0); + (A2A1[16] => V[34]) = (0:0:0, 0:0:0); + (A2A1[16] => V[35]) = (0:0:0, 0:0:0); + (A2A1[17] => U[18]) = (0:0:0, 0:0:0); + (A2A1[17] => U[19]) = (0:0:0, 0:0:0); + (A2A1[17] => U[20]) = (0:0:0, 0:0:0); + (A2A1[17] => U[21]) = (0:0:0, 0:0:0); + (A2A1[17] => U[22]) = (0:0:0, 0:0:0); + (A2A1[17] => U[23]) = (0:0:0, 0:0:0); + (A2A1[17] => U[24]) = (0:0:0, 0:0:0); + (A2A1[17] => U[25]) = (0:0:0, 0:0:0); + (A2A1[17] => U[26]) = (0:0:0, 0:0:0); + (A2A1[17] => U[27]) = (0:0:0, 0:0:0); + (A2A1[17] => U[28]) = (0:0:0, 0:0:0); + (A2A1[17] => U[29]) = (0:0:0, 0:0:0); + (A2A1[17] => U[30]) = (0:0:0, 0:0:0); + (A2A1[17] => U[31]) = (0:0:0, 0:0:0); + (A2A1[17] => U[32]) = (0:0:0, 0:0:0); + (A2A1[17] => U[33]) = (0:0:0, 0:0:0); + (A2A1[17] => U[34]) = (0:0:0, 0:0:0); + (A2A1[17] => U[35]) = (0:0:0, 0:0:0); + (A2A1[17] => U[36]) = (0:0:0, 0:0:0); + (A2A1[17] => U[37]) = (0:0:0, 0:0:0); + (A2A1[17] => V[17]) = (0:0:0, 0:0:0); + (A2A1[17] => V[18]) = (0:0:0, 0:0:0); + (A2A1[17] => V[19]) = (0:0:0, 0:0:0); + (A2A1[17] => V[20]) = (0:0:0, 0:0:0); + (A2A1[17] => V[21]) = (0:0:0, 0:0:0); + (A2A1[17] => V[22]) = (0:0:0, 0:0:0); + (A2A1[17] => V[23]) = (0:0:0, 0:0:0); + (A2A1[17] => V[24]) = (0:0:0, 0:0:0); + (A2A1[17] => V[25]) = (0:0:0, 0:0:0); + (A2A1[17] => V[26]) = (0:0:0, 0:0:0); + (A2A1[17] => V[27]) = (0:0:0, 0:0:0); + (A2A1[17] => V[28]) = (0:0:0, 0:0:0); + (A2A1[17] => V[29]) = (0:0:0, 0:0:0); + (A2A1[17] => V[30]) = (0:0:0, 0:0:0); + (A2A1[17] => V[31]) = (0:0:0, 0:0:0); + (A2A1[17] => V[32]) = (0:0:0, 0:0:0); + (A2A1[17] => V[33]) = (0:0:0, 0:0:0); + (A2A1[17] => V[34]) = (0:0:0, 0:0:0); + (A2A1[17] => V[35]) = (0:0:0, 0:0:0); + (A2A1[17] => V[36]) = (0:0:0, 0:0:0); + (A2A1[18] => U[19]) = (0:0:0, 0:0:0); + (A2A1[18] => U[20]) = (0:0:0, 0:0:0); + (A2A1[18] => U[21]) = (0:0:0, 0:0:0); + (A2A1[18] => U[22]) = (0:0:0, 0:0:0); + (A2A1[18] => U[23]) = (0:0:0, 0:0:0); + (A2A1[18] => U[24]) = (0:0:0, 0:0:0); + (A2A1[18] => U[25]) = (0:0:0, 0:0:0); + (A2A1[18] => U[26]) = (0:0:0, 0:0:0); + (A2A1[18] => U[27]) = (0:0:0, 0:0:0); + (A2A1[18] => U[28]) = (0:0:0, 0:0:0); + (A2A1[18] => U[29]) = (0:0:0, 0:0:0); + (A2A1[18] => U[30]) = (0:0:0, 0:0:0); + (A2A1[18] => U[31]) = (0:0:0, 0:0:0); + (A2A1[18] => U[32]) = (0:0:0, 0:0:0); + (A2A1[18] => U[33]) = (0:0:0, 0:0:0); + (A2A1[18] => U[34]) = (0:0:0, 0:0:0); + (A2A1[18] => U[35]) = (0:0:0, 0:0:0); + (A2A1[18] => U[36]) = (0:0:0, 0:0:0); + (A2A1[18] => U[37]) = (0:0:0, 0:0:0); + (A2A1[18] => U[38]) = (0:0:0, 0:0:0); + (A2A1[18] => V[18]) = (0:0:0, 0:0:0); + (A2A1[18] => V[19]) = (0:0:0, 0:0:0); + (A2A1[18] => V[20]) = (0:0:0, 0:0:0); + (A2A1[18] => V[21]) = (0:0:0, 0:0:0); + (A2A1[18] => V[22]) = (0:0:0, 0:0:0); + (A2A1[18] => V[23]) = (0:0:0, 0:0:0); + (A2A1[18] => V[24]) = (0:0:0, 0:0:0); + (A2A1[18] => V[25]) = (0:0:0, 0:0:0); + (A2A1[18] => V[26]) = (0:0:0, 0:0:0); + (A2A1[18] => V[27]) = (0:0:0, 0:0:0); + (A2A1[18] => V[28]) = (0:0:0, 0:0:0); + (A2A1[18] => V[29]) = (0:0:0, 0:0:0); + (A2A1[18] => V[30]) = (0:0:0, 0:0:0); + (A2A1[18] => V[31]) = (0:0:0, 0:0:0); + (A2A1[18] => V[32]) = (0:0:0, 0:0:0); + (A2A1[18] => V[33]) = (0:0:0, 0:0:0); + (A2A1[18] => V[34]) = (0:0:0, 0:0:0); + (A2A1[18] => V[35]) = (0:0:0, 0:0:0); + (A2A1[18] => V[36]) = (0:0:0, 0:0:0); + (A2A1[18] => V[37]) = (0:0:0, 0:0:0); + (A2A1[19] => U[20]) = (0:0:0, 0:0:0); + (A2A1[19] => U[21]) = (0:0:0, 0:0:0); + (A2A1[19] => U[22]) = (0:0:0, 0:0:0); + (A2A1[19] => U[23]) = (0:0:0, 0:0:0); + (A2A1[19] => U[24]) = (0:0:0, 0:0:0); + (A2A1[19] => U[25]) = (0:0:0, 0:0:0); + (A2A1[19] => U[26]) = (0:0:0, 0:0:0); + (A2A1[19] => U[27]) = (0:0:0, 0:0:0); + (A2A1[19] => U[28]) = (0:0:0, 0:0:0); + (A2A1[19] => U[29]) = (0:0:0, 0:0:0); + (A2A1[19] => U[30]) = (0:0:0, 0:0:0); + (A2A1[19] => U[31]) = (0:0:0, 0:0:0); + (A2A1[19] => U[32]) = (0:0:0, 0:0:0); + (A2A1[19] => U[33]) = (0:0:0, 0:0:0); + (A2A1[19] => U[34]) = (0:0:0, 0:0:0); + (A2A1[19] => U[35]) = (0:0:0, 0:0:0); + (A2A1[19] => U[36]) = (0:0:0, 0:0:0); + (A2A1[19] => U[37]) = (0:0:0, 0:0:0); + (A2A1[19] => U[38]) = (0:0:0, 0:0:0); + (A2A1[19] => U[39]) = (0:0:0, 0:0:0); + (A2A1[19] => V[19]) = (0:0:0, 0:0:0); + (A2A1[19] => V[20]) = (0:0:0, 0:0:0); + (A2A1[19] => V[21]) = (0:0:0, 0:0:0); + (A2A1[19] => V[22]) = (0:0:0, 0:0:0); + (A2A1[19] => V[23]) = (0:0:0, 0:0:0); + (A2A1[19] => V[24]) = (0:0:0, 0:0:0); + (A2A1[19] => V[25]) = (0:0:0, 0:0:0); + (A2A1[19] => V[26]) = (0:0:0, 0:0:0); + (A2A1[19] => V[27]) = (0:0:0, 0:0:0); + (A2A1[19] => V[28]) = (0:0:0, 0:0:0); + (A2A1[19] => V[29]) = (0:0:0, 0:0:0); + (A2A1[19] => V[30]) = (0:0:0, 0:0:0); + (A2A1[19] => V[31]) = (0:0:0, 0:0:0); + (A2A1[19] => V[32]) = (0:0:0, 0:0:0); + (A2A1[19] => V[33]) = (0:0:0, 0:0:0); + (A2A1[19] => V[34]) = (0:0:0, 0:0:0); + (A2A1[19] => V[35]) = (0:0:0, 0:0:0); + (A2A1[19] => V[36]) = (0:0:0, 0:0:0); + (A2A1[19] => V[37]) = (0:0:0, 0:0:0); + (A2A1[19] => V[38]) = (0:0:0, 0:0:0); + (A2A1[1] => U[10]) = (0:0:0, 0:0:0); + (A2A1[1] => U[11]) = (0:0:0, 0:0:0); + (A2A1[1] => U[12]) = (0:0:0, 0:0:0); + (A2A1[1] => U[13]) = (0:0:0, 0:0:0); + (A2A1[1] => U[14]) = (0:0:0, 0:0:0); + (A2A1[1] => U[15]) = (0:0:0, 0:0:0); + (A2A1[1] => U[16]) = (0:0:0, 0:0:0); + (A2A1[1] => U[17]) = (0:0:0, 0:0:0); + (A2A1[1] => U[18]) = (0:0:0, 0:0:0); + (A2A1[1] => U[19]) = (0:0:0, 0:0:0); + (A2A1[1] => U[1]) = (0:0:0, 0:0:0); + (A2A1[1] => U[20]) = (0:0:0, 0:0:0); + (A2A1[1] => U[21]) = (0:0:0, 0:0:0); + (A2A1[1] => U[22]) = (0:0:0, 0:0:0); + (A2A1[1] => U[2]) = (0:0:0, 0:0:0); + (A2A1[1] => U[3]) = (0:0:0, 0:0:0); + (A2A1[1] => U[4]) = (0:0:0, 0:0:0); + (A2A1[1] => U[5]) = (0:0:0, 0:0:0); + (A2A1[1] => U[6]) = (0:0:0, 0:0:0); + (A2A1[1] => U[7]) = (0:0:0, 0:0:0); + (A2A1[1] => U[8]) = (0:0:0, 0:0:0); + (A2A1[1] => U[9]) = (0:0:0, 0:0:0); + (A2A1[1] => V[10]) = (0:0:0, 0:0:0); + (A2A1[1] => V[11]) = (0:0:0, 0:0:0); + (A2A1[1] => V[12]) = (0:0:0, 0:0:0); + (A2A1[1] => V[13]) = (0:0:0, 0:0:0); + (A2A1[1] => V[14]) = (0:0:0, 0:0:0); + (A2A1[1] => V[15]) = (0:0:0, 0:0:0); + (A2A1[1] => V[16]) = (0:0:0, 0:0:0); + (A2A1[1] => V[17]) = (0:0:0, 0:0:0); + (A2A1[1] => V[18]) = (0:0:0, 0:0:0); + (A2A1[1] => V[19]) = (0:0:0, 0:0:0); + (A2A1[1] => V[20]) = (0:0:0, 0:0:0); + (A2A1[1] => V[21]) = (0:0:0, 0:0:0); + (A2A1[1] => V[4]) = (0:0:0, 0:0:0); + (A2A1[1] => V[5]) = (0:0:0, 0:0:0); + (A2A1[1] => V[6]) = (0:0:0, 0:0:0); + (A2A1[1] => V[7]) = (0:0:0, 0:0:0); + (A2A1[1] => V[8]) = (0:0:0, 0:0:0); + (A2A1[1] => V[9]) = (0:0:0, 0:0:0); + (A2A1[20] => U[21]) = (0:0:0, 0:0:0); + (A2A1[20] => U[22]) = (0:0:0, 0:0:0); + (A2A1[20] => U[23]) = (0:0:0, 0:0:0); + (A2A1[20] => U[24]) = (0:0:0, 0:0:0); + (A2A1[20] => U[25]) = (0:0:0, 0:0:0); + (A2A1[20] => U[26]) = (0:0:0, 0:0:0); + (A2A1[20] => U[27]) = (0:0:0, 0:0:0); + (A2A1[20] => U[28]) = (0:0:0, 0:0:0); + (A2A1[20] => U[29]) = (0:0:0, 0:0:0); + (A2A1[20] => U[30]) = (0:0:0, 0:0:0); + (A2A1[20] => U[31]) = (0:0:0, 0:0:0); + (A2A1[20] => U[32]) = (0:0:0, 0:0:0); + (A2A1[20] => U[33]) = (0:0:0, 0:0:0); + (A2A1[20] => U[34]) = (0:0:0, 0:0:0); + (A2A1[20] => U[35]) = (0:0:0, 0:0:0); + (A2A1[20] => U[36]) = (0:0:0, 0:0:0); + (A2A1[20] => U[37]) = (0:0:0, 0:0:0); + (A2A1[20] => U[38]) = (0:0:0, 0:0:0); + (A2A1[20] => U[39]) = (0:0:0, 0:0:0); + (A2A1[20] => V[20]) = (0:0:0, 0:0:0); + (A2A1[20] => V[21]) = (0:0:0, 0:0:0); + (A2A1[20] => V[22]) = (0:0:0, 0:0:0); + (A2A1[20] => V[23]) = (0:0:0, 0:0:0); + (A2A1[20] => V[24]) = (0:0:0, 0:0:0); + (A2A1[20] => V[25]) = (0:0:0, 0:0:0); + (A2A1[20] => V[26]) = (0:0:0, 0:0:0); + (A2A1[20] => V[27]) = (0:0:0, 0:0:0); + (A2A1[20] => V[28]) = (0:0:0, 0:0:0); + (A2A1[20] => V[29]) = (0:0:0, 0:0:0); + (A2A1[20] => V[30]) = (0:0:0, 0:0:0); + (A2A1[20] => V[31]) = (0:0:0, 0:0:0); + (A2A1[20] => V[32]) = (0:0:0, 0:0:0); + (A2A1[20] => V[33]) = (0:0:0, 0:0:0); + (A2A1[20] => V[34]) = (0:0:0, 0:0:0); + (A2A1[20] => V[35]) = (0:0:0, 0:0:0); + (A2A1[20] => V[36]) = (0:0:0, 0:0:0); + (A2A1[20] => V[37]) = (0:0:0, 0:0:0); + (A2A1[20] => V[38]) = (0:0:0, 0:0:0); + (A2A1[21] => U[22]) = (0:0:0, 0:0:0); + (A2A1[21] => U[23]) = (0:0:0, 0:0:0); + (A2A1[21] => U[24]) = (0:0:0, 0:0:0); + (A2A1[21] => U[25]) = (0:0:0, 0:0:0); + (A2A1[21] => U[26]) = (0:0:0, 0:0:0); + (A2A1[21] => U[27]) = (0:0:0, 0:0:0); + (A2A1[21] => U[28]) = (0:0:0, 0:0:0); + (A2A1[21] => U[29]) = (0:0:0, 0:0:0); + (A2A1[21] => U[30]) = (0:0:0, 0:0:0); + (A2A1[21] => U[31]) = (0:0:0, 0:0:0); + (A2A1[21] => U[32]) = (0:0:0, 0:0:0); + (A2A1[21] => U[33]) = (0:0:0, 0:0:0); + (A2A1[21] => U[34]) = (0:0:0, 0:0:0); + (A2A1[21] => U[35]) = (0:0:0, 0:0:0); + (A2A1[21] => U[36]) = (0:0:0, 0:0:0); + (A2A1[21] => U[37]) = (0:0:0, 0:0:0); + (A2A1[21] => U[38]) = (0:0:0, 0:0:0); + (A2A1[21] => U[39]) = (0:0:0, 0:0:0); + (A2A1[21] => U[40]) = (0:0:0, 0:0:0); + (A2A1[21] => V[21]) = (0:0:0, 0:0:0); + (A2A1[21] => V[22]) = (0:0:0, 0:0:0); + (A2A1[21] => V[23]) = (0:0:0, 0:0:0); + (A2A1[21] => V[24]) = (0:0:0, 0:0:0); + (A2A1[21] => V[25]) = (0:0:0, 0:0:0); + (A2A1[21] => V[26]) = (0:0:0, 0:0:0); + (A2A1[21] => V[27]) = (0:0:0, 0:0:0); + (A2A1[21] => V[28]) = (0:0:0, 0:0:0); + (A2A1[21] => V[29]) = (0:0:0, 0:0:0); + (A2A1[21] => V[30]) = (0:0:0, 0:0:0); + (A2A1[21] => V[31]) = (0:0:0, 0:0:0); + (A2A1[21] => V[32]) = (0:0:0, 0:0:0); + (A2A1[21] => V[33]) = (0:0:0, 0:0:0); + (A2A1[21] => V[34]) = (0:0:0, 0:0:0); + (A2A1[21] => V[35]) = (0:0:0, 0:0:0); + (A2A1[21] => V[36]) = (0:0:0, 0:0:0); + (A2A1[21] => V[37]) = (0:0:0, 0:0:0); + (A2A1[21] => V[38]) = (0:0:0, 0:0:0); + (A2A1[21] => V[39]) = (0:0:0, 0:0:0); + (A2A1[22] => U[23]) = (0:0:0, 0:0:0); + (A2A1[22] => U[24]) = (0:0:0, 0:0:0); + (A2A1[22] => U[25]) = (0:0:0, 0:0:0); + (A2A1[22] => U[26]) = (0:0:0, 0:0:0); + (A2A1[22] => U[27]) = (0:0:0, 0:0:0); + (A2A1[22] => U[28]) = (0:0:0, 0:0:0); + (A2A1[22] => U[29]) = (0:0:0, 0:0:0); + (A2A1[22] => U[30]) = (0:0:0, 0:0:0); + (A2A1[22] => U[31]) = (0:0:0, 0:0:0); + (A2A1[22] => U[32]) = (0:0:0, 0:0:0); + (A2A1[22] => U[33]) = (0:0:0, 0:0:0); + (A2A1[22] => U[34]) = (0:0:0, 0:0:0); + (A2A1[22] => U[35]) = (0:0:0, 0:0:0); + (A2A1[22] => U[36]) = (0:0:0, 0:0:0); + (A2A1[22] => U[37]) = (0:0:0, 0:0:0); + (A2A1[22] => U[38]) = (0:0:0, 0:0:0); + (A2A1[22] => U[39]) = (0:0:0, 0:0:0); + (A2A1[22] => U[40]) = (0:0:0, 0:0:0); + (A2A1[22] => U[41]) = (0:0:0, 0:0:0); + (A2A1[22] => V[22]) = (0:0:0, 0:0:0); + (A2A1[22] => V[23]) = (0:0:0, 0:0:0); + (A2A1[22] => V[24]) = (0:0:0, 0:0:0); + (A2A1[22] => V[25]) = (0:0:0, 0:0:0); + (A2A1[22] => V[26]) = (0:0:0, 0:0:0); + (A2A1[22] => V[27]) = (0:0:0, 0:0:0); + (A2A1[22] => V[28]) = (0:0:0, 0:0:0); + (A2A1[22] => V[29]) = (0:0:0, 0:0:0); + (A2A1[22] => V[30]) = (0:0:0, 0:0:0); + (A2A1[22] => V[31]) = (0:0:0, 0:0:0); + (A2A1[22] => V[32]) = (0:0:0, 0:0:0); + (A2A1[22] => V[33]) = (0:0:0, 0:0:0); + (A2A1[22] => V[34]) = (0:0:0, 0:0:0); + (A2A1[22] => V[35]) = (0:0:0, 0:0:0); + (A2A1[22] => V[36]) = (0:0:0, 0:0:0); + (A2A1[22] => V[37]) = (0:0:0, 0:0:0); + (A2A1[22] => V[38]) = (0:0:0, 0:0:0); + (A2A1[22] => V[39]) = (0:0:0, 0:0:0); + (A2A1[22] => V[40]) = (0:0:0, 0:0:0); + (A2A1[23] => U[24]) = (0:0:0, 0:0:0); + (A2A1[23] => U[25]) = (0:0:0, 0:0:0); + (A2A1[23] => U[26]) = (0:0:0, 0:0:0); + (A2A1[23] => U[27]) = (0:0:0, 0:0:0); + (A2A1[23] => U[28]) = (0:0:0, 0:0:0); + (A2A1[23] => U[29]) = (0:0:0, 0:0:0); + (A2A1[23] => U[30]) = (0:0:0, 0:0:0); + (A2A1[23] => U[31]) = (0:0:0, 0:0:0); + (A2A1[23] => U[32]) = (0:0:0, 0:0:0); + (A2A1[23] => U[33]) = (0:0:0, 0:0:0); + (A2A1[23] => U[34]) = (0:0:0, 0:0:0); + (A2A1[23] => U[35]) = (0:0:0, 0:0:0); + (A2A1[23] => U[36]) = (0:0:0, 0:0:0); + (A2A1[23] => U[37]) = (0:0:0, 0:0:0); + (A2A1[23] => U[38]) = (0:0:0, 0:0:0); + (A2A1[23] => U[39]) = (0:0:0, 0:0:0); + (A2A1[23] => U[40]) = (0:0:0, 0:0:0); + (A2A1[23] => U[41]) = (0:0:0, 0:0:0); + (A2A1[23] => U[42]) = (0:0:0, 0:0:0); + (A2A1[23] => V[23]) = (0:0:0, 0:0:0); + (A2A1[23] => V[24]) = (0:0:0, 0:0:0); + (A2A1[23] => V[25]) = (0:0:0, 0:0:0); + (A2A1[23] => V[26]) = (0:0:0, 0:0:0); + (A2A1[23] => V[27]) = (0:0:0, 0:0:0); + (A2A1[23] => V[28]) = (0:0:0, 0:0:0); + (A2A1[23] => V[29]) = (0:0:0, 0:0:0); + (A2A1[23] => V[30]) = (0:0:0, 0:0:0); + (A2A1[23] => V[31]) = (0:0:0, 0:0:0); + (A2A1[23] => V[32]) = (0:0:0, 0:0:0); + (A2A1[23] => V[33]) = (0:0:0, 0:0:0); + (A2A1[23] => V[34]) = (0:0:0, 0:0:0); + (A2A1[23] => V[35]) = (0:0:0, 0:0:0); + (A2A1[23] => V[36]) = (0:0:0, 0:0:0); + (A2A1[23] => V[37]) = (0:0:0, 0:0:0); + (A2A1[23] => V[38]) = (0:0:0, 0:0:0); + (A2A1[23] => V[39]) = (0:0:0, 0:0:0); + (A2A1[23] => V[40]) = (0:0:0, 0:0:0); + (A2A1[23] => V[41]) = (0:0:0, 0:0:0); + (A2A1[24] => U[25]) = (0:0:0, 0:0:0); + (A2A1[24] => U[26]) = (0:0:0, 0:0:0); + (A2A1[24] => U[27]) = (0:0:0, 0:0:0); + (A2A1[24] => U[28]) = (0:0:0, 0:0:0); + (A2A1[24] => U[29]) = (0:0:0, 0:0:0); + (A2A1[24] => U[30]) = (0:0:0, 0:0:0); + (A2A1[24] => U[31]) = (0:0:0, 0:0:0); + (A2A1[24] => U[32]) = (0:0:0, 0:0:0); + (A2A1[24] => U[33]) = (0:0:0, 0:0:0); + (A2A1[24] => U[34]) = (0:0:0, 0:0:0); + (A2A1[24] => U[35]) = (0:0:0, 0:0:0); + (A2A1[24] => U[36]) = (0:0:0, 0:0:0); + (A2A1[24] => U[37]) = (0:0:0, 0:0:0); + (A2A1[24] => U[38]) = (0:0:0, 0:0:0); + (A2A1[24] => U[39]) = (0:0:0, 0:0:0); + (A2A1[24] => U[40]) = (0:0:0, 0:0:0); + (A2A1[24] => U[41]) = (0:0:0, 0:0:0); + (A2A1[24] => U[42]) = (0:0:0, 0:0:0); + (A2A1[24] => V[24]) = (0:0:0, 0:0:0); + (A2A1[24] => V[25]) = (0:0:0, 0:0:0); + (A2A1[24] => V[26]) = (0:0:0, 0:0:0); + (A2A1[24] => V[27]) = (0:0:0, 0:0:0); + (A2A1[24] => V[28]) = (0:0:0, 0:0:0); + (A2A1[24] => V[29]) = (0:0:0, 0:0:0); + (A2A1[24] => V[30]) = (0:0:0, 0:0:0); + (A2A1[24] => V[31]) = (0:0:0, 0:0:0); + (A2A1[24] => V[32]) = (0:0:0, 0:0:0); + (A2A1[24] => V[33]) = (0:0:0, 0:0:0); + (A2A1[24] => V[34]) = (0:0:0, 0:0:0); + (A2A1[24] => V[35]) = (0:0:0, 0:0:0); + (A2A1[24] => V[36]) = (0:0:0, 0:0:0); + (A2A1[24] => V[37]) = (0:0:0, 0:0:0); + (A2A1[24] => V[38]) = (0:0:0, 0:0:0); + (A2A1[24] => V[39]) = (0:0:0, 0:0:0); + (A2A1[24] => V[40]) = (0:0:0, 0:0:0); + (A2A1[24] => V[41]) = (0:0:0, 0:0:0); + (A2A1[25] => U[26]) = (0:0:0, 0:0:0); + (A2A1[25] => U[27]) = (0:0:0, 0:0:0); + (A2A1[25] => U[28]) = (0:0:0, 0:0:0); + (A2A1[25] => U[29]) = (0:0:0, 0:0:0); + (A2A1[25] => U[30]) = (0:0:0, 0:0:0); + (A2A1[25] => U[31]) = (0:0:0, 0:0:0); + (A2A1[25] => U[32]) = (0:0:0, 0:0:0); + (A2A1[25] => U[33]) = (0:0:0, 0:0:0); + (A2A1[25] => U[34]) = (0:0:0, 0:0:0); + (A2A1[25] => U[35]) = (0:0:0, 0:0:0); + (A2A1[25] => U[36]) = (0:0:0, 0:0:0); + (A2A1[25] => U[37]) = (0:0:0, 0:0:0); + (A2A1[25] => U[38]) = (0:0:0, 0:0:0); + (A2A1[25] => U[39]) = (0:0:0, 0:0:0); + (A2A1[25] => U[40]) = (0:0:0, 0:0:0); + (A2A1[25] => U[41]) = (0:0:0, 0:0:0); + (A2A1[25] => U[42]) = (0:0:0, 0:0:0); + (A2A1[25] => U[43]) = (0:0:0, 0:0:0); + (A2A1[25] => V[25]) = (0:0:0, 0:0:0); + (A2A1[25] => V[26]) = (0:0:0, 0:0:0); + (A2A1[25] => V[27]) = (0:0:0, 0:0:0); + (A2A1[25] => V[28]) = (0:0:0, 0:0:0); + (A2A1[25] => V[29]) = (0:0:0, 0:0:0); + (A2A1[25] => V[30]) = (0:0:0, 0:0:0); + (A2A1[25] => V[31]) = (0:0:0, 0:0:0); + (A2A1[25] => V[32]) = (0:0:0, 0:0:0); + (A2A1[25] => V[33]) = (0:0:0, 0:0:0); + (A2A1[25] => V[34]) = (0:0:0, 0:0:0); + (A2A1[25] => V[35]) = (0:0:0, 0:0:0); + (A2A1[25] => V[36]) = (0:0:0, 0:0:0); + (A2A1[25] => V[37]) = (0:0:0, 0:0:0); + (A2A1[25] => V[38]) = (0:0:0, 0:0:0); + (A2A1[25] => V[39]) = (0:0:0, 0:0:0); + (A2A1[25] => V[40]) = (0:0:0, 0:0:0); + (A2A1[25] => V[41]) = (0:0:0, 0:0:0); + (A2A1[25] => V[42]) = (0:0:0, 0:0:0); + (A2A1[26] => AMULT26) = (0:0:0, 0:0:0); + (A2A1[26] => U[27]) = (0:0:0, 0:0:0); + (A2A1[26] => U[28]) = (0:0:0, 0:0:0); + (A2A1[26] => U[29]) = (0:0:0, 0:0:0); + (A2A1[26] => U[30]) = (0:0:0, 0:0:0); + (A2A1[26] => U[31]) = (0:0:0, 0:0:0); + (A2A1[26] => U[32]) = (0:0:0, 0:0:0); + (A2A1[26] => U[33]) = (0:0:0, 0:0:0); + (A2A1[26] => U[34]) = (0:0:0, 0:0:0); + (A2A1[26] => U[35]) = (0:0:0, 0:0:0); + (A2A1[26] => U[36]) = (0:0:0, 0:0:0); + (A2A1[26] => U[37]) = (0:0:0, 0:0:0); + (A2A1[26] => U[38]) = (0:0:0, 0:0:0); + (A2A1[26] => U[39]) = (0:0:0, 0:0:0); + (A2A1[26] => U[40]) = (0:0:0, 0:0:0); + (A2A1[26] => U[41]) = (0:0:0, 0:0:0); + (A2A1[26] => U[42]) = (0:0:0, 0:0:0); + (A2A1[26] => U[43]) = (0:0:0, 0:0:0); + (A2A1[26] => V[26]) = (0:0:0, 0:0:0); + (A2A1[26] => V[27]) = (0:0:0, 0:0:0); + (A2A1[26] => V[28]) = (0:0:0, 0:0:0); + (A2A1[26] => V[29]) = (0:0:0, 0:0:0); + (A2A1[26] => V[30]) = (0:0:0, 0:0:0); + (A2A1[26] => V[31]) = (0:0:0, 0:0:0); + (A2A1[26] => V[32]) = (0:0:0, 0:0:0); + (A2A1[26] => V[33]) = (0:0:0, 0:0:0); + (A2A1[26] => V[34]) = (0:0:0, 0:0:0); + (A2A1[26] => V[35]) = (0:0:0, 0:0:0); + (A2A1[26] => V[36]) = (0:0:0, 0:0:0); + (A2A1[26] => V[37]) = (0:0:0, 0:0:0); + (A2A1[26] => V[38]) = (0:0:0, 0:0:0); + (A2A1[26] => V[39]) = (0:0:0, 0:0:0); + (A2A1[26] => V[40]) = (0:0:0, 0:0:0); + (A2A1[26] => V[41]) = (0:0:0, 0:0:0); + (A2A1[26] => V[42]) = (0:0:0, 0:0:0); + (A2A1[26] => V[43]) = (0:0:0, 0:0:0); + (A2A1[2] => U[10]) = (0:0:0, 0:0:0); + (A2A1[2] => U[11]) = (0:0:0, 0:0:0); + (A2A1[2] => U[12]) = (0:0:0, 0:0:0); + (A2A1[2] => U[13]) = (0:0:0, 0:0:0); + (A2A1[2] => U[14]) = (0:0:0, 0:0:0); + (A2A1[2] => U[15]) = (0:0:0, 0:0:0); + (A2A1[2] => U[16]) = (0:0:0, 0:0:0); + (A2A1[2] => U[17]) = (0:0:0, 0:0:0); + (A2A1[2] => U[18]) = (0:0:0, 0:0:0); + (A2A1[2] => U[19]) = (0:0:0, 0:0:0); + (A2A1[2] => U[20]) = (0:0:0, 0:0:0); + (A2A1[2] => U[21]) = (0:0:0, 0:0:0); + (A2A1[2] => U[22]) = (0:0:0, 0:0:0); + (A2A1[2] => U[23]) = (0:0:0, 0:0:0); + (A2A1[2] => U[2]) = (0:0:0, 0:0:0); + (A2A1[2] => U[3]) = (0:0:0, 0:0:0); + (A2A1[2] => U[4]) = (0:0:0, 0:0:0); + (A2A1[2] => U[5]) = (0:0:0, 0:0:0); + (A2A1[2] => U[6]) = (0:0:0, 0:0:0); + (A2A1[2] => U[7]) = (0:0:0, 0:0:0); + (A2A1[2] => U[8]) = (0:0:0, 0:0:0); + (A2A1[2] => U[9]) = (0:0:0, 0:0:0); + (A2A1[2] => V[10]) = (0:0:0, 0:0:0); + (A2A1[2] => V[11]) = (0:0:0, 0:0:0); + (A2A1[2] => V[12]) = (0:0:0, 0:0:0); + (A2A1[2] => V[13]) = (0:0:0, 0:0:0); + (A2A1[2] => V[14]) = (0:0:0, 0:0:0); + (A2A1[2] => V[15]) = (0:0:0, 0:0:0); + (A2A1[2] => V[16]) = (0:0:0, 0:0:0); + (A2A1[2] => V[17]) = (0:0:0, 0:0:0); + (A2A1[2] => V[18]) = (0:0:0, 0:0:0); + (A2A1[2] => V[19]) = (0:0:0, 0:0:0); + (A2A1[2] => V[20]) = (0:0:0, 0:0:0); + (A2A1[2] => V[21]) = (0:0:0, 0:0:0); + (A2A1[2] => V[22]) = (0:0:0, 0:0:0); + (A2A1[2] => V[4]) = (0:0:0, 0:0:0); + (A2A1[2] => V[5]) = (0:0:0, 0:0:0); + (A2A1[2] => V[6]) = (0:0:0, 0:0:0); + (A2A1[2] => V[7]) = (0:0:0, 0:0:0); + (A2A1[2] => V[8]) = (0:0:0, 0:0:0); + (A2A1[2] => V[9]) = (0:0:0, 0:0:0); + (A2A1[3] => U[10]) = (0:0:0, 0:0:0); + (A2A1[3] => U[11]) = (0:0:0, 0:0:0); + (A2A1[3] => U[12]) = (0:0:0, 0:0:0); + (A2A1[3] => U[13]) = (0:0:0, 0:0:0); + (A2A1[3] => U[14]) = (0:0:0, 0:0:0); + (A2A1[3] => U[15]) = (0:0:0, 0:0:0); + (A2A1[3] => U[16]) = (0:0:0, 0:0:0); + (A2A1[3] => U[17]) = (0:0:0, 0:0:0); + (A2A1[3] => U[18]) = (0:0:0, 0:0:0); + (A2A1[3] => U[19]) = (0:0:0, 0:0:0); + (A2A1[3] => U[20]) = (0:0:0, 0:0:0); + (A2A1[3] => U[21]) = (0:0:0, 0:0:0); + (A2A1[3] => U[22]) = (0:0:0, 0:0:0); + (A2A1[3] => U[23]) = (0:0:0, 0:0:0); + (A2A1[3] => U[24]) = (0:0:0, 0:0:0); + (A2A1[3] => U[3]) = (0:0:0, 0:0:0); + (A2A1[3] => U[4]) = (0:0:0, 0:0:0); + (A2A1[3] => U[5]) = (0:0:0, 0:0:0); + (A2A1[3] => U[6]) = (0:0:0, 0:0:0); + (A2A1[3] => U[7]) = (0:0:0, 0:0:0); + (A2A1[3] => U[8]) = (0:0:0, 0:0:0); + (A2A1[3] => U[9]) = (0:0:0, 0:0:0); + (A2A1[3] => V[10]) = (0:0:0, 0:0:0); + (A2A1[3] => V[11]) = (0:0:0, 0:0:0); + (A2A1[3] => V[12]) = (0:0:0, 0:0:0); + (A2A1[3] => V[13]) = (0:0:0, 0:0:0); + (A2A1[3] => V[14]) = (0:0:0, 0:0:0); + (A2A1[3] => V[15]) = (0:0:0, 0:0:0); + (A2A1[3] => V[16]) = (0:0:0, 0:0:0); + (A2A1[3] => V[17]) = (0:0:0, 0:0:0); + (A2A1[3] => V[18]) = (0:0:0, 0:0:0); + (A2A1[3] => V[19]) = (0:0:0, 0:0:0); + (A2A1[3] => V[20]) = (0:0:0, 0:0:0); + (A2A1[3] => V[21]) = (0:0:0, 0:0:0); + (A2A1[3] => V[22]) = (0:0:0, 0:0:0); + (A2A1[3] => V[23]) = (0:0:0, 0:0:0); + (A2A1[3] => V[4]) = (0:0:0, 0:0:0); + (A2A1[3] => V[5]) = (0:0:0, 0:0:0); + (A2A1[3] => V[6]) = (0:0:0, 0:0:0); + (A2A1[3] => V[7]) = (0:0:0, 0:0:0); + (A2A1[3] => V[8]) = (0:0:0, 0:0:0); + (A2A1[3] => V[9]) = (0:0:0, 0:0:0); + (A2A1[4] => U[10]) = (0:0:0, 0:0:0); + (A2A1[4] => U[11]) = (0:0:0, 0:0:0); + (A2A1[4] => U[12]) = (0:0:0, 0:0:0); + (A2A1[4] => U[13]) = (0:0:0, 0:0:0); + (A2A1[4] => U[14]) = (0:0:0, 0:0:0); + (A2A1[4] => U[15]) = (0:0:0, 0:0:0); + (A2A1[4] => U[16]) = (0:0:0, 0:0:0); + (A2A1[4] => U[17]) = (0:0:0, 0:0:0); + (A2A1[4] => U[18]) = (0:0:0, 0:0:0); + (A2A1[4] => U[19]) = (0:0:0, 0:0:0); + (A2A1[4] => U[20]) = (0:0:0, 0:0:0); + (A2A1[4] => U[21]) = (0:0:0, 0:0:0); + (A2A1[4] => U[22]) = (0:0:0, 0:0:0); + (A2A1[4] => U[23]) = (0:0:0, 0:0:0); + (A2A1[4] => U[24]) = (0:0:0, 0:0:0); + (A2A1[4] => U[25]) = (0:0:0, 0:0:0); + (A2A1[4] => U[5]) = (0:0:0, 0:0:0); + (A2A1[4] => U[6]) = (0:0:0, 0:0:0); + (A2A1[4] => U[7]) = (0:0:0, 0:0:0); + (A2A1[4] => U[8]) = (0:0:0, 0:0:0); + (A2A1[4] => U[9]) = (0:0:0, 0:0:0); + (A2A1[4] => V[10]) = (0:0:0, 0:0:0); + (A2A1[4] => V[11]) = (0:0:0, 0:0:0); + (A2A1[4] => V[12]) = (0:0:0, 0:0:0); + (A2A1[4] => V[13]) = (0:0:0, 0:0:0); + (A2A1[4] => V[14]) = (0:0:0, 0:0:0); + (A2A1[4] => V[15]) = (0:0:0, 0:0:0); + (A2A1[4] => V[16]) = (0:0:0, 0:0:0); + (A2A1[4] => V[17]) = (0:0:0, 0:0:0); + (A2A1[4] => V[18]) = (0:0:0, 0:0:0); + (A2A1[4] => V[19]) = (0:0:0, 0:0:0); + (A2A1[4] => V[20]) = (0:0:0, 0:0:0); + (A2A1[4] => V[21]) = (0:0:0, 0:0:0); + (A2A1[4] => V[22]) = (0:0:0, 0:0:0); + (A2A1[4] => V[23]) = (0:0:0, 0:0:0); + (A2A1[4] => V[24]) = (0:0:0, 0:0:0); + (A2A1[4] => V[4]) = (0:0:0, 0:0:0); + (A2A1[4] => V[5]) = (0:0:0, 0:0:0); + (A2A1[4] => V[6]) = (0:0:0, 0:0:0); + (A2A1[4] => V[7]) = (0:0:0, 0:0:0); + (A2A1[4] => V[8]) = (0:0:0, 0:0:0); + (A2A1[4] => V[9]) = (0:0:0, 0:0:0); + (A2A1[5] => U[10]) = (0:0:0, 0:0:0); + (A2A1[5] => U[11]) = (0:0:0, 0:0:0); + (A2A1[5] => U[12]) = (0:0:0, 0:0:0); + (A2A1[5] => U[13]) = (0:0:0, 0:0:0); + (A2A1[5] => U[14]) = (0:0:0, 0:0:0); + (A2A1[5] => U[15]) = (0:0:0, 0:0:0); + (A2A1[5] => U[16]) = (0:0:0, 0:0:0); + (A2A1[5] => U[17]) = (0:0:0, 0:0:0); + (A2A1[5] => U[18]) = (0:0:0, 0:0:0); + (A2A1[5] => U[19]) = (0:0:0, 0:0:0); + (A2A1[5] => U[20]) = (0:0:0, 0:0:0); + (A2A1[5] => U[21]) = (0:0:0, 0:0:0); + (A2A1[5] => U[22]) = (0:0:0, 0:0:0); + (A2A1[5] => U[23]) = (0:0:0, 0:0:0); + (A2A1[5] => U[24]) = (0:0:0, 0:0:0); + (A2A1[5] => U[25]) = (0:0:0, 0:0:0); + (A2A1[5] => U[26]) = (0:0:0, 0:0:0); + (A2A1[5] => U[6]) = (0:0:0, 0:0:0); + (A2A1[5] => U[7]) = (0:0:0, 0:0:0); + (A2A1[5] => U[8]) = (0:0:0, 0:0:0); + (A2A1[5] => U[9]) = (0:0:0, 0:0:0); + (A2A1[5] => V[10]) = (0:0:0, 0:0:0); + (A2A1[5] => V[11]) = (0:0:0, 0:0:0); + (A2A1[5] => V[12]) = (0:0:0, 0:0:0); + (A2A1[5] => V[13]) = (0:0:0, 0:0:0); + (A2A1[5] => V[14]) = (0:0:0, 0:0:0); + (A2A1[5] => V[15]) = (0:0:0, 0:0:0); + (A2A1[5] => V[16]) = (0:0:0, 0:0:0); + (A2A1[5] => V[17]) = (0:0:0, 0:0:0); + (A2A1[5] => V[18]) = (0:0:0, 0:0:0); + (A2A1[5] => V[19]) = (0:0:0, 0:0:0); + (A2A1[5] => V[20]) = (0:0:0, 0:0:0); + (A2A1[5] => V[21]) = (0:0:0, 0:0:0); + (A2A1[5] => V[22]) = (0:0:0, 0:0:0); + (A2A1[5] => V[23]) = (0:0:0, 0:0:0); + (A2A1[5] => V[24]) = (0:0:0, 0:0:0); + (A2A1[5] => V[25]) = (0:0:0, 0:0:0); + (A2A1[5] => V[5]) = (0:0:0, 0:0:0); + (A2A1[5] => V[6]) = (0:0:0, 0:0:0); + (A2A1[5] => V[7]) = (0:0:0, 0:0:0); + (A2A1[5] => V[8]) = (0:0:0, 0:0:0); + (A2A1[5] => V[9]) = (0:0:0, 0:0:0); + (A2A1[6] => U[10]) = (0:0:0, 0:0:0); + (A2A1[6] => U[11]) = (0:0:0, 0:0:0); + (A2A1[6] => U[12]) = (0:0:0, 0:0:0); + (A2A1[6] => U[13]) = (0:0:0, 0:0:0); + (A2A1[6] => U[14]) = (0:0:0, 0:0:0); + (A2A1[6] => U[15]) = (0:0:0, 0:0:0); + (A2A1[6] => U[16]) = (0:0:0, 0:0:0); + (A2A1[6] => U[17]) = (0:0:0, 0:0:0); + (A2A1[6] => U[18]) = (0:0:0, 0:0:0); + (A2A1[6] => U[19]) = (0:0:0, 0:0:0); + (A2A1[6] => U[20]) = (0:0:0, 0:0:0); + (A2A1[6] => U[21]) = (0:0:0, 0:0:0); + (A2A1[6] => U[22]) = (0:0:0, 0:0:0); + (A2A1[6] => U[23]) = (0:0:0, 0:0:0); + (A2A1[6] => U[24]) = (0:0:0, 0:0:0); + (A2A1[6] => U[25]) = (0:0:0, 0:0:0); + (A2A1[6] => U[26]) = (0:0:0, 0:0:0); + (A2A1[6] => U[27]) = (0:0:0, 0:0:0); + (A2A1[6] => U[7]) = (0:0:0, 0:0:0); + (A2A1[6] => U[8]) = (0:0:0, 0:0:0); + (A2A1[6] => U[9]) = (0:0:0, 0:0:0); + (A2A1[6] => V[10]) = (0:0:0, 0:0:0); + (A2A1[6] => V[11]) = (0:0:0, 0:0:0); + (A2A1[6] => V[12]) = (0:0:0, 0:0:0); + (A2A1[6] => V[13]) = (0:0:0, 0:0:0); + (A2A1[6] => V[14]) = (0:0:0, 0:0:0); + (A2A1[6] => V[15]) = (0:0:0, 0:0:0); + (A2A1[6] => V[16]) = (0:0:0, 0:0:0); + (A2A1[6] => V[17]) = (0:0:0, 0:0:0); + (A2A1[6] => V[18]) = (0:0:0, 0:0:0); + (A2A1[6] => V[19]) = (0:0:0, 0:0:0); + (A2A1[6] => V[20]) = (0:0:0, 0:0:0); + (A2A1[6] => V[21]) = (0:0:0, 0:0:0); + (A2A1[6] => V[22]) = (0:0:0, 0:0:0); + (A2A1[6] => V[23]) = (0:0:0, 0:0:0); + (A2A1[6] => V[24]) = (0:0:0, 0:0:0); + (A2A1[6] => V[25]) = (0:0:0, 0:0:0); + (A2A1[6] => V[26]) = (0:0:0, 0:0:0); + (A2A1[6] => V[6]) = (0:0:0, 0:0:0); + (A2A1[6] => V[7]) = (0:0:0, 0:0:0); + (A2A1[6] => V[8]) = (0:0:0, 0:0:0); + (A2A1[6] => V[9]) = (0:0:0, 0:0:0); + (A2A1[7] => U[10]) = (0:0:0, 0:0:0); + (A2A1[7] => U[11]) = (0:0:0, 0:0:0); + (A2A1[7] => U[12]) = (0:0:0, 0:0:0); + (A2A1[7] => U[13]) = (0:0:0, 0:0:0); + (A2A1[7] => U[14]) = (0:0:0, 0:0:0); + (A2A1[7] => U[15]) = (0:0:0, 0:0:0); + (A2A1[7] => U[16]) = (0:0:0, 0:0:0); + (A2A1[7] => U[17]) = (0:0:0, 0:0:0); + (A2A1[7] => U[18]) = (0:0:0, 0:0:0); + (A2A1[7] => U[19]) = (0:0:0, 0:0:0); + (A2A1[7] => U[20]) = (0:0:0, 0:0:0); + (A2A1[7] => U[21]) = (0:0:0, 0:0:0); + (A2A1[7] => U[22]) = (0:0:0, 0:0:0); + (A2A1[7] => U[23]) = (0:0:0, 0:0:0); + (A2A1[7] => U[24]) = (0:0:0, 0:0:0); + (A2A1[7] => U[25]) = (0:0:0, 0:0:0); + (A2A1[7] => U[26]) = (0:0:0, 0:0:0); + (A2A1[7] => U[27]) = (0:0:0, 0:0:0); + (A2A1[7] => U[28]) = (0:0:0, 0:0:0); + (A2A1[7] => U[8]) = (0:0:0, 0:0:0); + (A2A1[7] => U[9]) = (0:0:0, 0:0:0); + (A2A1[7] => V[10]) = (0:0:0, 0:0:0); + (A2A1[7] => V[11]) = (0:0:0, 0:0:0); + (A2A1[7] => V[12]) = (0:0:0, 0:0:0); + (A2A1[7] => V[13]) = (0:0:0, 0:0:0); + (A2A1[7] => V[14]) = (0:0:0, 0:0:0); + (A2A1[7] => V[15]) = (0:0:0, 0:0:0); + (A2A1[7] => V[16]) = (0:0:0, 0:0:0); + (A2A1[7] => V[17]) = (0:0:0, 0:0:0); + (A2A1[7] => V[18]) = (0:0:0, 0:0:0); + (A2A1[7] => V[19]) = (0:0:0, 0:0:0); + (A2A1[7] => V[20]) = (0:0:0, 0:0:0); + (A2A1[7] => V[21]) = (0:0:0, 0:0:0); + (A2A1[7] => V[22]) = (0:0:0, 0:0:0); + (A2A1[7] => V[23]) = (0:0:0, 0:0:0); + (A2A1[7] => V[24]) = (0:0:0, 0:0:0); + (A2A1[7] => V[25]) = (0:0:0, 0:0:0); + (A2A1[7] => V[26]) = (0:0:0, 0:0:0); + (A2A1[7] => V[27]) = (0:0:0, 0:0:0); + (A2A1[7] => V[7]) = (0:0:0, 0:0:0); + (A2A1[7] => V[8]) = (0:0:0, 0:0:0); + (A2A1[7] => V[9]) = (0:0:0, 0:0:0); + (A2A1[8] => U[10]) = (0:0:0, 0:0:0); + (A2A1[8] => U[11]) = (0:0:0, 0:0:0); + (A2A1[8] => U[12]) = (0:0:0, 0:0:0); + (A2A1[8] => U[13]) = (0:0:0, 0:0:0); + (A2A1[8] => U[14]) = (0:0:0, 0:0:0); + (A2A1[8] => U[15]) = (0:0:0, 0:0:0); + (A2A1[8] => U[16]) = (0:0:0, 0:0:0); + (A2A1[8] => U[17]) = (0:0:0, 0:0:0); + (A2A1[8] => U[18]) = (0:0:0, 0:0:0); + (A2A1[8] => U[19]) = (0:0:0, 0:0:0); + (A2A1[8] => U[20]) = (0:0:0, 0:0:0); + (A2A1[8] => U[21]) = (0:0:0, 0:0:0); + (A2A1[8] => U[22]) = (0:0:0, 0:0:0); + (A2A1[8] => U[23]) = (0:0:0, 0:0:0); + (A2A1[8] => U[24]) = (0:0:0, 0:0:0); + (A2A1[8] => U[25]) = (0:0:0, 0:0:0); + (A2A1[8] => U[26]) = (0:0:0, 0:0:0); + (A2A1[8] => U[27]) = (0:0:0, 0:0:0); + (A2A1[8] => U[28]) = (0:0:0, 0:0:0); + (A2A1[8] => U[29]) = (0:0:0, 0:0:0); + (A2A1[8] => U[9]) = (0:0:0, 0:0:0); + (A2A1[8] => V[10]) = (0:0:0, 0:0:0); + (A2A1[8] => V[11]) = (0:0:0, 0:0:0); + (A2A1[8] => V[12]) = (0:0:0, 0:0:0); + (A2A1[8] => V[13]) = (0:0:0, 0:0:0); + (A2A1[8] => V[14]) = (0:0:0, 0:0:0); + (A2A1[8] => V[15]) = (0:0:0, 0:0:0); + (A2A1[8] => V[16]) = (0:0:0, 0:0:0); + (A2A1[8] => V[17]) = (0:0:0, 0:0:0); + (A2A1[8] => V[18]) = (0:0:0, 0:0:0); + (A2A1[8] => V[19]) = (0:0:0, 0:0:0); + (A2A1[8] => V[20]) = (0:0:0, 0:0:0); + (A2A1[8] => V[21]) = (0:0:0, 0:0:0); + (A2A1[8] => V[22]) = (0:0:0, 0:0:0); + (A2A1[8] => V[23]) = (0:0:0, 0:0:0); + (A2A1[8] => V[24]) = (0:0:0, 0:0:0); + (A2A1[8] => V[25]) = (0:0:0, 0:0:0); + (A2A1[8] => V[26]) = (0:0:0, 0:0:0); + (A2A1[8] => V[27]) = (0:0:0, 0:0:0); + (A2A1[8] => V[28]) = (0:0:0, 0:0:0); + (A2A1[8] => V[8]) = (0:0:0, 0:0:0); + (A2A1[8] => V[9]) = (0:0:0, 0:0:0); + (A2A1[9] => U[10]) = (0:0:0, 0:0:0); + (A2A1[9] => U[11]) = (0:0:0, 0:0:0); + (A2A1[9] => U[12]) = (0:0:0, 0:0:0); + (A2A1[9] => U[13]) = (0:0:0, 0:0:0); + (A2A1[9] => U[14]) = (0:0:0, 0:0:0); + (A2A1[9] => U[15]) = (0:0:0, 0:0:0); + (A2A1[9] => U[16]) = (0:0:0, 0:0:0); + (A2A1[9] => U[17]) = (0:0:0, 0:0:0); + (A2A1[9] => U[18]) = (0:0:0, 0:0:0); + (A2A1[9] => U[19]) = (0:0:0, 0:0:0); + (A2A1[9] => U[20]) = (0:0:0, 0:0:0); + (A2A1[9] => U[21]) = (0:0:0, 0:0:0); + (A2A1[9] => U[22]) = (0:0:0, 0:0:0); + (A2A1[9] => U[23]) = (0:0:0, 0:0:0); + (A2A1[9] => U[24]) = (0:0:0, 0:0:0); + (A2A1[9] => U[25]) = (0:0:0, 0:0:0); + (A2A1[9] => U[26]) = (0:0:0, 0:0:0); + (A2A1[9] => U[27]) = (0:0:0, 0:0:0); + (A2A1[9] => U[28]) = (0:0:0, 0:0:0); + (A2A1[9] => U[29]) = (0:0:0, 0:0:0); + (A2A1[9] => U[30]) = (0:0:0, 0:0:0); + (A2A1[9] => V[10]) = (0:0:0, 0:0:0); + (A2A1[9] => V[11]) = (0:0:0, 0:0:0); + (A2A1[9] => V[12]) = (0:0:0, 0:0:0); + (A2A1[9] => V[13]) = (0:0:0, 0:0:0); + (A2A1[9] => V[14]) = (0:0:0, 0:0:0); + (A2A1[9] => V[15]) = (0:0:0, 0:0:0); + (A2A1[9] => V[16]) = (0:0:0, 0:0:0); + (A2A1[9] => V[17]) = (0:0:0, 0:0:0); + (A2A1[9] => V[18]) = (0:0:0, 0:0:0); + (A2A1[9] => V[19]) = (0:0:0, 0:0:0); + (A2A1[9] => V[20]) = (0:0:0, 0:0:0); + (A2A1[9] => V[21]) = (0:0:0, 0:0:0); + (A2A1[9] => V[22]) = (0:0:0, 0:0:0); + (A2A1[9] => V[23]) = (0:0:0, 0:0:0); + (A2A1[9] => V[24]) = (0:0:0, 0:0:0); + (A2A1[9] => V[25]) = (0:0:0, 0:0:0); + (A2A1[9] => V[26]) = (0:0:0, 0:0:0); + (A2A1[9] => V[27]) = (0:0:0, 0:0:0); + (A2A1[9] => V[28]) = (0:0:0, 0:0:0); + (A2A1[9] => V[29]) = (0:0:0, 0:0:0); + (A2A1[9] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[1]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[2]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[3]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[4]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[0] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[0]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[0] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[10] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[10] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[11] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[11] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[12] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[12] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[13] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[13] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[14] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[14] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[15] => U[43]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[42]) = (0:0:0, 0:0:0); + (AD_DATA[15] => V[43]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[16] => U[43]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[42]) = (0:0:0, 0:0:0); + (AD_DATA[16] => V[43]) = (0:0:0, 0:0:0); + (AD_DATA[17] => BMULT17) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[17] => U[43]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[42]) = (0:0:0, 0:0:0); + (AD_DATA[17] => V[43]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[18] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[18] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[19] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[19] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[0]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[1]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[2]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[3]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[4]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[1] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[0]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[1] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[20] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[20] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[21] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[21] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[22] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[22] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[23] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[23] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[24] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[24] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[25] => U[43]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[25] => V[42]) = (0:0:0, 0:0:0); + (AD_DATA[26] => AMULT26) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[41]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[42]) = (0:0:0, 0:0:0); + (AD_DATA[26] => U[43]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[40]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[41]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[42]) = (0:0:0, 0:0:0); + (AD_DATA[26] => V[43]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[2]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[3]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[4]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[2] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[2] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[2]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[3]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[4]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[3] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[3] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[4] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[4] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[5]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[6]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[5] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[4]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[5]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[5] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[6] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[6] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[7]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[8]) = (0:0:0, 0:0:0); + (AD_DATA[7] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[6]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[7]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[7] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[8] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[8] => V[9]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[10]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[11]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[12]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[13]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[14]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[15]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[16]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[17]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[18]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[19]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[20]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[21]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[22]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[23]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[24]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[25]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[26]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[27]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[28]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[29]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[30]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[31]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[32]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[33]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[34]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[35]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[36]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[37]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[38]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[39]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[40]) = (0:0:0, 0:0:0); + (AD_DATA[9] => U[9]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[10]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[11]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[12]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[13]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[14]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[15]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[16]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[17]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[18]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[19]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[20]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[21]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[22]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[23]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[24]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[25]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[26]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[27]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[28]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[29]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[30]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[31]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[32]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[33]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[34]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[35]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[36]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[37]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[38]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[39]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[8]) = (0:0:0, 0:0:0); + (AD_DATA[9] => V[9]) = (0:0:0, 0:0:0); + (B2B1[0] => U[10]) = (0:0:0, 0:0:0); + (B2B1[0] => U[11]) = (0:0:0, 0:0:0); + (B2B1[0] => U[12]) = (0:0:0, 0:0:0); + (B2B1[0] => U[13]) = (0:0:0, 0:0:0); + (B2B1[0] => U[14]) = (0:0:0, 0:0:0); + (B2B1[0] => U[15]) = (0:0:0, 0:0:0); + (B2B1[0] => U[16]) = (0:0:0, 0:0:0); + (B2B1[0] => U[17]) = (0:0:0, 0:0:0); + (B2B1[0] => U[18]) = (0:0:0, 0:0:0); + (B2B1[0] => U[19]) = (0:0:0, 0:0:0); + (B2B1[0] => U[1]) = (0:0:0, 0:0:0); + (B2B1[0] => U[20]) = (0:0:0, 0:0:0); + (B2B1[0] => U[21]) = (0:0:0, 0:0:0); + (B2B1[0] => U[22]) = (0:0:0, 0:0:0); + (B2B1[0] => U[23]) = (0:0:0, 0:0:0); + (B2B1[0] => U[24]) = (0:0:0, 0:0:0); + (B2B1[0] => U[25]) = (0:0:0, 0:0:0); + (B2B1[0] => U[26]) = (0:0:0, 0:0:0); + (B2B1[0] => U[27]) = (0:0:0, 0:0:0); + (B2B1[0] => U[28]) = (0:0:0, 0:0:0); + (B2B1[0] => U[29]) = (0:0:0, 0:0:0); + (B2B1[0] => U[2]) = (0:0:0, 0:0:0); + (B2B1[0] => U[30]) = (0:0:0, 0:0:0); + (B2B1[0] => U[31]) = (0:0:0, 0:0:0); + (B2B1[0] => U[3]) = (0:0:0, 0:0:0); + (B2B1[0] => U[4]) = (0:0:0, 0:0:0); + (B2B1[0] => U[5]) = (0:0:0, 0:0:0); + (B2B1[0] => U[6]) = (0:0:0, 0:0:0); + (B2B1[0] => U[7]) = (0:0:0, 0:0:0); + (B2B1[0] => U[8]) = (0:0:0, 0:0:0); + (B2B1[0] => U[9]) = (0:0:0, 0:0:0); + (B2B1[0] => V[0]) = (0:0:0, 0:0:0); + (B2B1[0] => V[10]) = (0:0:0, 0:0:0); + (B2B1[0] => V[11]) = (0:0:0, 0:0:0); + (B2B1[0] => V[12]) = (0:0:0, 0:0:0); + (B2B1[0] => V[13]) = (0:0:0, 0:0:0); + (B2B1[0] => V[14]) = (0:0:0, 0:0:0); + (B2B1[0] => V[15]) = (0:0:0, 0:0:0); + (B2B1[0] => V[16]) = (0:0:0, 0:0:0); + (B2B1[0] => V[17]) = (0:0:0, 0:0:0); + (B2B1[0] => V[18]) = (0:0:0, 0:0:0); + (B2B1[0] => V[19]) = (0:0:0, 0:0:0); + (B2B1[0] => V[20]) = (0:0:0, 0:0:0); + (B2B1[0] => V[21]) = (0:0:0, 0:0:0); + (B2B1[0] => V[22]) = (0:0:0, 0:0:0); + (B2B1[0] => V[23]) = (0:0:0, 0:0:0); + (B2B1[0] => V[24]) = (0:0:0, 0:0:0); + (B2B1[0] => V[25]) = (0:0:0, 0:0:0); + (B2B1[0] => V[26]) = (0:0:0, 0:0:0); + (B2B1[0] => V[27]) = (0:0:0, 0:0:0); + (B2B1[0] => V[28]) = (0:0:0, 0:0:0); + (B2B1[0] => V[29]) = (0:0:0, 0:0:0); + (B2B1[0] => V[30]) = (0:0:0, 0:0:0); + (B2B1[0] => V[4]) = (0:0:0, 0:0:0); + (B2B1[0] => V[5]) = (0:0:0, 0:0:0); + (B2B1[0] => V[6]) = (0:0:0, 0:0:0); + (B2B1[0] => V[7]) = (0:0:0, 0:0:0); + (B2B1[0] => V[8]) = (0:0:0, 0:0:0); + (B2B1[0] => V[9]) = (0:0:0, 0:0:0); + (B2B1[10] => U[11]) = (0:0:0, 0:0:0); + (B2B1[10] => U[12]) = (0:0:0, 0:0:0); + (B2B1[10] => U[13]) = (0:0:0, 0:0:0); + (B2B1[10] => U[14]) = (0:0:0, 0:0:0); + (B2B1[10] => U[15]) = (0:0:0, 0:0:0); + (B2B1[10] => U[16]) = (0:0:0, 0:0:0); + (B2B1[10] => U[17]) = (0:0:0, 0:0:0); + (B2B1[10] => U[18]) = (0:0:0, 0:0:0); + (B2B1[10] => U[19]) = (0:0:0, 0:0:0); + (B2B1[10] => U[20]) = (0:0:0, 0:0:0); + (B2B1[10] => U[21]) = (0:0:0, 0:0:0); + (B2B1[10] => U[22]) = (0:0:0, 0:0:0); + (B2B1[10] => U[23]) = (0:0:0, 0:0:0); + (B2B1[10] => U[24]) = (0:0:0, 0:0:0); + (B2B1[10] => U[25]) = (0:0:0, 0:0:0); + (B2B1[10] => U[26]) = (0:0:0, 0:0:0); + (B2B1[10] => U[27]) = (0:0:0, 0:0:0); + (B2B1[10] => U[28]) = (0:0:0, 0:0:0); + (B2B1[10] => U[29]) = (0:0:0, 0:0:0); + (B2B1[10] => U[30]) = (0:0:0, 0:0:0); + (B2B1[10] => U[31]) = (0:0:0, 0:0:0); + (B2B1[10] => U[32]) = (0:0:0, 0:0:0); + (B2B1[10] => U[33]) = (0:0:0, 0:0:0); + (B2B1[10] => U[34]) = (0:0:0, 0:0:0); + (B2B1[10] => U[35]) = (0:0:0, 0:0:0); + (B2B1[10] => U[36]) = (0:0:0, 0:0:0); + (B2B1[10] => U[37]) = (0:0:0, 0:0:0); + (B2B1[10] => U[38]) = (0:0:0, 0:0:0); + (B2B1[10] => U[39]) = (0:0:0, 0:0:0); + (B2B1[10] => U[40]) = (0:0:0, 0:0:0); + (B2B1[10] => V[10]) = (0:0:0, 0:0:0); + (B2B1[10] => V[11]) = (0:0:0, 0:0:0); + (B2B1[10] => V[12]) = (0:0:0, 0:0:0); + (B2B1[10] => V[13]) = (0:0:0, 0:0:0); + (B2B1[10] => V[14]) = (0:0:0, 0:0:0); + (B2B1[10] => V[15]) = (0:0:0, 0:0:0); + (B2B1[10] => V[16]) = (0:0:0, 0:0:0); + (B2B1[10] => V[17]) = (0:0:0, 0:0:0); + (B2B1[10] => V[18]) = (0:0:0, 0:0:0); + (B2B1[10] => V[19]) = (0:0:0, 0:0:0); + (B2B1[10] => V[20]) = (0:0:0, 0:0:0); + (B2B1[10] => V[21]) = (0:0:0, 0:0:0); + (B2B1[10] => V[22]) = (0:0:0, 0:0:0); + (B2B1[10] => V[23]) = (0:0:0, 0:0:0); + (B2B1[10] => V[24]) = (0:0:0, 0:0:0); + (B2B1[10] => V[25]) = (0:0:0, 0:0:0); + (B2B1[10] => V[26]) = (0:0:0, 0:0:0); + (B2B1[10] => V[27]) = (0:0:0, 0:0:0); + (B2B1[10] => V[28]) = (0:0:0, 0:0:0); + (B2B1[10] => V[29]) = (0:0:0, 0:0:0); + (B2B1[10] => V[30]) = (0:0:0, 0:0:0); + (B2B1[10] => V[31]) = (0:0:0, 0:0:0); + (B2B1[10] => V[32]) = (0:0:0, 0:0:0); + (B2B1[10] => V[33]) = (0:0:0, 0:0:0); + (B2B1[10] => V[34]) = (0:0:0, 0:0:0); + (B2B1[10] => V[35]) = (0:0:0, 0:0:0); + (B2B1[10] => V[36]) = (0:0:0, 0:0:0); + (B2B1[10] => V[37]) = (0:0:0, 0:0:0); + (B2B1[10] => V[38]) = (0:0:0, 0:0:0); + (B2B1[10] => V[39]) = (0:0:0, 0:0:0); + (B2B1[11] => U[11]) = (0:0:0, 0:0:0); + (B2B1[11] => U[12]) = (0:0:0, 0:0:0); + (B2B1[11] => U[13]) = (0:0:0, 0:0:0); + (B2B1[11] => U[14]) = (0:0:0, 0:0:0); + (B2B1[11] => U[15]) = (0:0:0, 0:0:0); + (B2B1[11] => U[16]) = (0:0:0, 0:0:0); + (B2B1[11] => U[17]) = (0:0:0, 0:0:0); + (B2B1[11] => U[18]) = (0:0:0, 0:0:0); + (B2B1[11] => U[19]) = (0:0:0, 0:0:0); + (B2B1[11] => U[20]) = (0:0:0, 0:0:0); + (B2B1[11] => U[21]) = (0:0:0, 0:0:0); + (B2B1[11] => U[22]) = (0:0:0, 0:0:0); + (B2B1[11] => U[23]) = (0:0:0, 0:0:0); + (B2B1[11] => U[24]) = (0:0:0, 0:0:0); + (B2B1[11] => U[25]) = (0:0:0, 0:0:0); + (B2B1[11] => U[26]) = (0:0:0, 0:0:0); + (B2B1[11] => U[27]) = (0:0:0, 0:0:0); + (B2B1[11] => U[28]) = (0:0:0, 0:0:0); + (B2B1[11] => U[29]) = (0:0:0, 0:0:0); + (B2B1[11] => U[30]) = (0:0:0, 0:0:0); + (B2B1[11] => U[31]) = (0:0:0, 0:0:0); + (B2B1[11] => U[32]) = (0:0:0, 0:0:0); + (B2B1[11] => U[33]) = (0:0:0, 0:0:0); + (B2B1[11] => U[34]) = (0:0:0, 0:0:0); + (B2B1[11] => U[35]) = (0:0:0, 0:0:0); + (B2B1[11] => U[36]) = (0:0:0, 0:0:0); + (B2B1[11] => U[37]) = (0:0:0, 0:0:0); + (B2B1[11] => U[38]) = (0:0:0, 0:0:0); + (B2B1[11] => U[39]) = (0:0:0, 0:0:0); + (B2B1[11] => U[40]) = (0:0:0, 0:0:0); + (B2B1[11] => U[41]) = (0:0:0, 0:0:0); + (B2B1[11] => V[10]) = (0:0:0, 0:0:0); + (B2B1[11] => V[11]) = (0:0:0, 0:0:0); + (B2B1[11] => V[12]) = (0:0:0, 0:0:0); + (B2B1[11] => V[13]) = (0:0:0, 0:0:0); + (B2B1[11] => V[14]) = (0:0:0, 0:0:0); + (B2B1[11] => V[15]) = (0:0:0, 0:0:0); + (B2B1[11] => V[16]) = (0:0:0, 0:0:0); + (B2B1[11] => V[17]) = (0:0:0, 0:0:0); + (B2B1[11] => V[18]) = (0:0:0, 0:0:0); + (B2B1[11] => V[19]) = (0:0:0, 0:0:0); + (B2B1[11] => V[20]) = (0:0:0, 0:0:0); + (B2B1[11] => V[21]) = (0:0:0, 0:0:0); + (B2B1[11] => V[22]) = (0:0:0, 0:0:0); + (B2B1[11] => V[23]) = (0:0:0, 0:0:0); + (B2B1[11] => V[24]) = (0:0:0, 0:0:0); + (B2B1[11] => V[25]) = (0:0:0, 0:0:0); + (B2B1[11] => V[26]) = (0:0:0, 0:0:0); + (B2B1[11] => V[27]) = (0:0:0, 0:0:0); + (B2B1[11] => V[28]) = (0:0:0, 0:0:0); + (B2B1[11] => V[29]) = (0:0:0, 0:0:0); + (B2B1[11] => V[30]) = (0:0:0, 0:0:0); + (B2B1[11] => V[31]) = (0:0:0, 0:0:0); + (B2B1[11] => V[32]) = (0:0:0, 0:0:0); + (B2B1[11] => V[33]) = (0:0:0, 0:0:0); + (B2B1[11] => V[34]) = (0:0:0, 0:0:0); + (B2B1[11] => V[35]) = (0:0:0, 0:0:0); + (B2B1[11] => V[36]) = (0:0:0, 0:0:0); + (B2B1[11] => V[37]) = (0:0:0, 0:0:0); + (B2B1[11] => V[38]) = (0:0:0, 0:0:0); + (B2B1[11] => V[39]) = (0:0:0, 0:0:0); + (B2B1[11] => V[40]) = (0:0:0, 0:0:0); + (B2B1[12] => U[13]) = (0:0:0, 0:0:0); + (B2B1[12] => U[14]) = (0:0:0, 0:0:0); + (B2B1[12] => U[15]) = (0:0:0, 0:0:0); + (B2B1[12] => U[16]) = (0:0:0, 0:0:0); + (B2B1[12] => U[17]) = (0:0:0, 0:0:0); + (B2B1[12] => U[18]) = (0:0:0, 0:0:0); + (B2B1[12] => U[19]) = (0:0:0, 0:0:0); + (B2B1[12] => U[20]) = (0:0:0, 0:0:0); + (B2B1[12] => U[21]) = (0:0:0, 0:0:0); + (B2B1[12] => U[22]) = (0:0:0, 0:0:0); + (B2B1[12] => U[23]) = (0:0:0, 0:0:0); + (B2B1[12] => U[24]) = (0:0:0, 0:0:0); + (B2B1[12] => U[25]) = (0:0:0, 0:0:0); + (B2B1[12] => U[26]) = (0:0:0, 0:0:0); + (B2B1[12] => U[27]) = (0:0:0, 0:0:0); + (B2B1[12] => U[28]) = (0:0:0, 0:0:0); + (B2B1[12] => U[29]) = (0:0:0, 0:0:0); + (B2B1[12] => U[30]) = (0:0:0, 0:0:0); + (B2B1[12] => U[31]) = (0:0:0, 0:0:0); + (B2B1[12] => U[32]) = (0:0:0, 0:0:0); + (B2B1[12] => U[33]) = (0:0:0, 0:0:0); + (B2B1[12] => U[34]) = (0:0:0, 0:0:0); + (B2B1[12] => U[35]) = (0:0:0, 0:0:0); + (B2B1[12] => U[36]) = (0:0:0, 0:0:0); + (B2B1[12] => U[37]) = (0:0:0, 0:0:0); + (B2B1[12] => U[38]) = (0:0:0, 0:0:0); + (B2B1[12] => U[39]) = (0:0:0, 0:0:0); + (B2B1[12] => U[40]) = (0:0:0, 0:0:0); + (B2B1[12] => U[41]) = (0:0:0, 0:0:0); + (B2B1[12] => V[12]) = (0:0:0, 0:0:0); + (B2B1[12] => V[13]) = (0:0:0, 0:0:0); + (B2B1[12] => V[14]) = (0:0:0, 0:0:0); + (B2B1[12] => V[15]) = (0:0:0, 0:0:0); + (B2B1[12] => V[16]) = (0:0:0, 0:0:0); + (B2B1[12] => V[17]) = (0:0:0, 0:0:0); + (B2B1[12] => V[18]) = (0:0:0, 0:0:0); + (B2B1[12] => V[19]) = (0:0:0, 0:0:0); + (B2B1[12] => V[20]) = (0:0:0, 0:0:0); + (B2B1[12] => V[21]) = (0:0:0, 0:0:0); + (B2B1[12] => V[22]) = (0:0:0, 0:0:0); + (B2B1[12] => V[23]) = (0:0:0, 0:0:0); + (B2B1[12] => V[24]) = (0:0:0, 0:0:0); + (B2B1[12] => V[25]) = (0:0:0, 0:0:0); + (B2B1[12] => V[26]) = (0:0:0, 0:0:0); + (B2B1[12] => V[27]) = (0:0:0, 0:0:0); + (B2B1[12] => V[28]) = (0:0:0, 0:0:0); + (B2B1[12] => V[29]) = (0:0:0, 0:0:0); + (B2B1[12] => V[30]) = (0:0:0, 0:0:0); + (B2B1[12] => V[31]) = (0:0:0, 0:0:0); + (B2B1[12] => V[32]) = (0:0:0, 0:0:0); + (B2B1[12] => V[33]) = (0:0:0, 0:0:0); + (B2B1[12] => V[34]) = (0:0:0, 0:0:0); + (B2B1[12] => V[35]) = (0:0:0, 0:0:0); + (B2B1[12] => V[36]) = (0:0:0, 0:0:0); + (B2B1[12] => V[37]) = (0:0:0, 0:0:0); + (B2B1[12] => V[38]) = (0:0:0, 0:0:0); + (B2B1[12] => V[39]) = (0:0:0, 0:0:0); + (B2B1[12] => V[40]) = (0:0:0, 0:0:0); + (B2B1[13] => U[13]) = (0:0:0, 0:0:0); + (B2B1[13] => U[14]) = (0:0:0, 0:0:0); + (B2B1[13] => U[15]) = (0:0:0, 0:0:0); + (B2B1[13] => U[16]) = (0:0:0, 0:0:0); + (B2B1[13] => U[17]) = (0:0:0, 0:0:0); + (B2B1[13] => U[18]) = (0:0:0, 0:0:0); + (B2B1[13] => U[19]) = (0:0:0, 0:0:0); + (B2B1[13] => U[20]) = (0:0:0, 0:0:0); + (B2B1[13] => U[21]) = (0:0:0, 0:0:0); + (B2B1[13] => U[22]) = (0:0:0, 0:0:0); + (B2B1[13] => U[23]) = (0:0:0, 0:0:0); + (B2B1[13] => U[24]) = (0:0:0, 0:0:0); + (B2B1[13] => U[25]) = (0:0:0, 0:0:0); + (B2B1[13] => U[26]) = (0:0:0, 0:0:0); + (B2B1[13] => U[27]) = (0:0:0, 0:0:0); + (B2B1[13] => U[28]) = (0:0:0, 0:0:0); + (B2B1[13] => U[29]) = (0:0:0, 0:0:0); + (B2B1[13] => U[30]) = (0:0:0, 0:0:0); + (B2B1[13] => U[31]) = (0:0:0, 0:0:0); + (B2B1[13] => U[32]) = (0:0:0, 0:0:0); + (B2B1[13] => U[33]) = (0:0:0, 0:0:0); + (B2B1[13] => U[34]) = (0:0:0, 0:0:0); + (B2B1[13] => U[35]) = (0:0:0, 0:0:0); + (B2B1[13] => U[36]) = (0:0:0, 0:0:0); + (B2B1[13] => U[37]) = (0:0:0, 0:0:0); + (B2B1[13] => U[38]) = (0:0:0, 0:0:0); + (B2B1[13] => U[39]) = (0:0:0, 0:0:0); + (B2B1[13] => U[40]) = (0:0:0, 0:0:0); + (B2B1[13] => U[41]) = (0:0:0, 0:0:0); + (B2B1[13] => U[42]) = (0:0:0, 0:0:0); + (B2B1[13] => V[12]) = (0:0:0, 0:0:0); + (B2B1[13] => V[13]) = (0:0:0, 0:0:0); + (B2B1[13] => V[14]) = (0:0:0, 0:0:0); + (B2B1[13] => V[15]) = (0:0:0, 0:0:0); + (B2B1[13] => V[16]) = (0:0:0, 0:0:0); + (B2B1[13] => V[17]) = (0:0:0, 0:0:0); + (B2B1[13] => V[18]) = (0:0:0, 0:0:0); + (B2B1[13] => V[19]) = (0:0:0, 0:0:0); + (B2B1[13] => V[20]) = (0:0:0, 0:0:0); + (B2B1[13] => V[21]) = (0:0:0, 0:0:0); + (B2B1[13] => V[22]) = (0:0:0, 0:0:0); + (B2B1[13] => V[23]) = (0:0:0, 0:0:0); + (B2B1[13] => V[24]) = (0:0:0, 0:0:0); + (B2B1[13] => V[25]) = (0:0:0, 0:0:0); + (B2B1[13] => V[26]) = (0:0:0, 0:0:0); + (B2B1[13] => V[27]) = (0:0:0, 0:0:0); + (B2B1[13] => V[28]) = (0:0:0, 0:0:0); + (B2B1[13] => V[29]) = (0:0:0, 0:0:0); + (B2B1[13] => V[30]) = (0:0:0, 0:0:0); + (B2B1[13] => V[31]) = (0:0:0, 0:0:0); + (B2B1[13] => V[32]) = (0:0:0, 0:0:0); + (B2B1[13] => V[33]) = (0:0:0, 0:0:0); + (B2B1[13] => V[34]) = (0:0:0, 0:0:0); + (B2B1[13] => V[35]) = (0:0:0, 0:0:0); + (B2B1[13] => V[36]) = (0:0:0, 0:0:0); + (B2B1[13] => V[37]) = (0:0:0, 0:0:0); + (B2B1[13] => V[38]) = (0:0:0, 0:0:0); + (B2B1[13] => V[39]) = (0:0:0, 0:0:0); + (B2B1[13] => V[40]) = (0:0:0, 0:0:0); + (B2B1[13] => V[41]) = (0:0:0, 0:0:0); + (B2B1[14] => U[15]) = (0:0:0, 0:0:0); + (B2B1[14] => U[16]) = (0:0:0, 0:0:0); + (B2B1[14] => U[17]) = (0:0:0, 0:0:0); + (B2B1[14] => U[18]) = (0:0:0, 0:0:0); + (B2B1[14] => U[19]) = (0:0:0, 0:0:0); + (B2B1[14] => U[20]) = (0:0:0, 0:0:0); + (B2B1[14] => U[21]) = (0:0:0, 0:0:0); + (B2B1[14] => U[22]) = (0:0:0, 0:0:0); + (B2B1[14] => U[23]) = (0:0:0, 0:0:0); + (B2B1[14] => U[24]) = (0:0:0, 0:0:0); + (B2B1[14] => U[25]) = (0:0:0, 0:0:0); + (B2B1[14] => U[26]) = (0:0:0, 0:0:0); + (B2B1[14] => U[27]) = (0:0:0, 0:0:0); + (B2B1[14] => U[28]) = (0:0:0, 0:0:0); + (B2B1[14] => U[29]) = (0:0:0, 0:0:0); + (B2B1[14] => U[30]) = (0:0:0, 0:0:0); + (B2B1[14] => U[31]) = (0:0:0, 0:0:0); + (B2B1[14] => U[32]) = (0:0:0, 0:0:0); + (B2B1[14] => U[33]) = (0:0:0, 0:0:0); + (B2B1[14] => U[34]) = (0:0:0, 0:0:0); + (B2B1[14] => U[35]) = (0:0:0, 0:0:0); + (B2B1[14] => U[36]) = (0:0:0, 0:0:0); + (B2B1[14] => U[37]) = (0:0:0, 0:0:0); + (B2B1[14] => U[38]) = (0:0:0, 0:0:0); + (B2B1[14] => U[39]) = (0:0:0, 0:0:0); + (B2B1[14] => U[40]) = (0:0:0, 0:0:0); + (B2B1[14] => U[41]) = (0:0:0, 0:0:0); + (B2B1[14] => U[42]) = (0:0:0, 0:0:0); + (B2B1[14] => V[14]) = (0:0:0, 0:0:0); + (B2B1[14] => V[15]) = (0:0:0, 0:0:0); + (B2B1[14] => V[16]) = (0:0:0, 0:0:0); + (B2B1[14] => V[17]) = (0:0:0, 0:0:0); + (B2B1[14] => V[18]) = (0:0:0, 0:0:0); + (B2B1[14] => V[19]) = (0:0:0, 0:0:0); + (B2B1[14] => V[20]) = (0:0:0, 0:0:0); + (B2B1[14] => V[21]) = (0:0:0, 0:0:0); + (B2B1[14] => V[22]) = (0:0:0, 0:0:0); + (B2B1[14] => V[23]) = (0:0:0, 0:0:0); + (B2B1[14] => V[24]) = (0:0:0, 0:0:0); + (B2B1[14] => V[25]) = (0:0:0, 0:0:0); + (B2B1[14] => V[26]) = (0:0:0, 0:0:0); + (B2B1[14] => V[27]) = (0:0:0, 0:0:0); + (B2B1[14] => V[28]) = (0:0:0, 0:0:0); + (B2B1[14] => V[29]) = (0:0:0, 0:0:0); + (B2B1[14] => V[30]) = (0:0:0, 0:0:0); + (B2B1[14] => V[31]) = (0:0:0, 0:0:0); + (B2B1[14] => V[32]) = (0:0:0, 0:0:0); + (B2B1[14] => V[33]) = (0:0:0, 0:0:0); + (B2B1[14] => V[34]) = (0:0:0, 0:0:0); + (B2B1[14] => V[35]) = (0:0:0, 0:0:0); + (B2B1[14] => V[36]) = (0:0:0, 0:0:0); + (B2B1[14] => V[37]) = (0:0:0, 0:0:0); + (B2B1[14] => V[38]) = (0:0:0, 0:0:0); + (B2B1[14] => V[39]) = (0:0:0, 0:0:0); + (B2B1[14] => V[40]) = (0:0:0, 0:0:0); + (B2B1[14] => V[41]) = (0:0:0, 0:0:0); + (B2B1[15] => U[15]) = (0:0:0, 0:0:0); + (B2B1[15] => U[16]) = (0:0:0, 0:0:0); + (B2B1[15] => U[17]) = (0:0:0, 0:0:0); + (B2B1[15] => U[18]) = (0:0:0, 0:0:0); + (B2B1[15] => U[19]) = (0:0:0, 0:0:0); + (B2B1[15] => U[20]) = (0:0:0, 0:0:0); + (B2B1[15] => U[21]) = (0:0:0, 0:0:0); + (B2B1[15] => U[22]) = (0:0:0, 0:0:0); + (B2B1[15] => U[23]) = (0:0:0, 0:0:0); + (B2B1[15] => U[24]) = (0:0:0, 0:0:0); + (B2B1[15] => U[25]) = (0:0:0, 0:0:0); + (B2B1[15] => U[26]) = (0:0:0, 0:0:0); + (B2B1[15] => U[27]) = (0:0:0, 0:0:0); + (B2B1[15] => U[28]) = (0:0:0, 0:0:0); + (B2B1[15] => U[29]) = (0:0:0, 0:0:0); + (B2B1[15] => U[30]) = (0:0:0, 0:0:0); + (B2B1[15] => U[31]) = (0:0:0, 0:0:0); + (B2B1[15] => U[32]) = (0:0:0, 0:0:0); + (B2B1[15] => U[33]) = (0:0:0, 0:0:0); + (B2B1[15] => U[34]) = (0:0:0, 0:0:0); + (B2B1[15] => U[35]) = (0:0:0, 0:0:0); + (B2B1[15] => U[36]) = (0:0:0, 0:0:0); + (B2B1[15] => U[37]) = (0:0:0, 0:0:0); + (B2B1[15] => U[38]) = (0:0:0, 0:0:0); + (B2B1[15] => U[39]) = (0:0:0, 0:0:0); + (B2B1[15] => U[40]) = (0:0:0, 0:0:0); + (B2B1[15] => U[41]) = (0:0:0, 0:0:0); + (B2B1[15] => U[42]) = (0:0:0, 0:0:0); + (B2B1[15] => U[43]) = (0:0:0, 0:0:0); + (B2B1[15] => V[14]) = (0:0:0, 0:0:0); + (B2B1[15] => V[15]) = (0:0:0, 0:0:0); + (B2B1[15] => V[16]) = (0:0:0, 0:0:0); + (B2B1[15] => V[17]) = (0:0:0, 0:0:0); + (B2B1[15] => V[18]) = (0:0:0, 0:0:0); + (B2B1[15] => V[19]) = (0:0:0, 0:0:0); + (B2B1[15] => V[20]) = (0:0:0, 0:0:0); + (B2B1[15] => V[21]) = (0:0:0, 0:0:0); + (B2B1[15] => V[22]) = (0:0:0, 0:0:0); + (B2B1[15] => V[23]) = (0:0:0, 0:0:0); + (B2B1[15] => V[24]) = (0:0:0, 0:0:0); + (B2B1[15] => V[25]) = (0:0:0, 0:0:0); + (B2B1[15] => V[26]) = (0:0:0, 0:0:0); + (B2B1[15] => V[27]) = (0:0:0, 0:0:0); + (B2B1[15] => V[28]) = (0:0:0, 0:0:0); + (B2B1[15] => V[29]) = (0:0:0, 0:0:0); + (B2B1[15] => V[30]) = (0:0:0, 0:0:0); + (B2B1[15] => V[31]) = (0:0:0, 0:0:0); + (B2B1[15] => V[32]) = (0:0:0, 0:0:0); + (B2B1[15] => V[33]) = (0:0:0, 0:0:0); + (B2B1[15] => V[34]) = (0:0:0, 0:0:0); + (B2B1[15] => V[35]) = (0:0:0, 0:0:0); + (B2B1[15] => V[36]) = (0:0:0, 0:0:0); + (B2B1[15] => V[37]) = (0:0:0, 0:0:0); + (B2B1[15] => V[38]) = (0:0:0, 0:0:0); + (B2B1[15] => V[39]) = (0:0:0, 0:0:0); + (B2B1[15] => V[40]) = (0:0:0, 0:0:0); + (B2B1[15] => V[41]) = (0:0:0, 0:0:0); + (B2B1[15] => V[42]) = (0:0:0, 0:0:0); + (B2B1[15] => V[43]) = (0:0:0, 0:0:0); + (B2B1[16] => U[17]) = (0:0:0, 0:0:0); + (B2B1[16] => U[18]) = (0:0:0, 0:0:0); + (B2B1[16] => U[19]) = (0:0:0, 0:0:0); + (B2B1[16] => U[20]) = (0:0:0, 0:0:0); + (B2B1[16] => U[21]) = (0:0:0, 0:0:0); + (B2B1[16] => U[22]) = (0:0:0, 0:0:0); + (B2B1[16] => U[23]) = (0:0:0, 0:0:0); + (B2B1[16] => U[24]) = (0:0:0, 0:0:0); + (B2B1[16] => U[25]) = (0:0:0, 0:0:0); + (B2B1[16] => U[26]) = (0:0:0, 0:0:0); + (B2B1[16] => U[27]) = (0:0:0, 0:0:0); + (B2B1[16] => U[28]) = (0:0:0, 0:0:0); + (B2B1[16] => U[29]) = (0:0:0, 0:0:0); + (B2B1[16] => U[30]) = (0:0:0, 0:0:0); + (B2B1[16] => U[31]) = (0:0:0, 0:0:0); + (B2B1[16] => U[32]) = (0:0:0, 0:0:0); + (B2B1[16] => U[33]) = (0:0:0, 0:0:0); + (B2B1[16] => U[34]) = (0:0:0, 0:0:0); + (B2B1[16] => U[35]) = (0:0:0, 0:0:0); + (B2B1[16] => U[36]) = (0:0:0, 0:0:0); + (B2B1[16] => U[37]) = (0:0:0, 0:0:0); + (B2B1[16] => U[38]) = (0:0:0, 0:0:0); + (B2B1[16] => U[39]) = (0:0:0, 0:0:0); + (B2B1[16] => U[40]) = (0:0:0, 0:0:0); + (B2B1[16] => U[41]) = (0:0:0, 0:0:0); + (B2B1[16] => U[42]) = (0:0:0, 0:0:0); + (B2B1[16] => U[43]) = (0:0:0, 0:0:0); + (B2B1[16] => V[16]) = (0:0:0, 0:0:0); + (B2B1[16] => V[17]) = (0:0:0, 0:0:0); + (B2B1[16] => V[18]) = (0:0:0, 0:0:0); + (B2B1[16] => V[19]) = (0:0:0, 0:0:0); + (B2B1[16] => V[20]) = (0:0:0, 0:0:0); + (B2B1[16] => V[21]) = (0:0:0, 0:0:0); + (B2B1[16] => V[22]) = (0:0:0, 0:0:0); + (B2B1[16] => V[23]) = (0:0:0, 0:0:0); + (B2B1[16] => V[24]) = (0:0:0, 0:0:0); + (B2B1[16] => V[25]) = (0:0:0, 0:0:0); + (B2B1[16] => V[26]) = (0:0:0, 0:0:0); + (B2B1[16] => V[27]) = (0:0:0, 0:0:0); + (B2B1[16] => V[28]) = (0:0:0, 0:0:0); + (B2B1[16] => V[29]) = (0:0:0, 0:0:0); + (B2B1[16] => V[30]) = (0:0:0, 0:0:0); + (B2B1[16] => V[31]) = (0:0:0, 0:0:0); + (B2B1[16] => V[32]) = (0:0:0, 0:0:0); + (B2B1[16] => V[33]) = (0:0:0, 0:0:0); + (B2B1[16] => V[34]) = (0:0:0, 0:0:0); + (B2B1[16] => V[35]) = (0:0:0, 0:0:0); + (B2B1[16] => V[36]) = (0:0:0, 0:0:0); + (B2B1[16] => V[37]) = (0:0:0, 0:0:0); + (B2B1[16] => V[38]) = (0:0:0, 0:0:0); + (B2B1[16] => V[39]) = (0:0:0, 0:0:0); + (B2B1[16] => V[40]) = (0:0:0, 0:0:0); + (B2B1[16] => V[41]) = (0:0:0, 0:0:0); + (B2B1[16] => V[42]) = (0:0:0, 0:0:0); + (B2B1[16] => V[43]) = (0:0:0, 0:0:0); + (B2B1[17] => BMULT17) = (0:0:0, 0:0:0); + (B2B1[17] => U[17]) = (0:0:0, 0:0:0); + (B2B1[17] => U[18]) = (0:0:0, 0:0:0); + (B2B1[17] => U[19]) = (0:0:0, 0:0:0); + (B2B1[17] => U[20]) = (0:0:0, 0:0:0); + (B2B1[17] => U[21]) = (0:0:0, 0:0:0); + (B2B1[17] => U[22]) = (0:0:0, 0:0:0); + (B2B1[17] => U[23]) = (0:0:0, 0:0:0); + (B2B1[17] => U[24]) = (0:0:0, 0:0:0); + (B2B1[17] => U[25]) = (0:0:0, 0:0:0); + (B2B1[17] => U[26]) = (0:0:0, 0:0:0); + (B2B1[17] => U[27]) = (0:0:0, 0:0:0); + (B2B1[17] => U[28]) = (0:0:0, 0:0:0); + (B2B1[17] => U[29]) = (0:0:0, 0:0:0); + (B2B1[17] => U[30]) = (0:0:0, 0:0:0); + (B2B1[17] => U[31]) = (0:0:0, 0:0:0); + (B2B1[17] => U[32]) = (0:0:0, 0:0:0); + (B2B1[17] => U[33]) = (0:0:0, 0:0:0); + (B2B1[17] => U[34]) = (0:0:0, 0:0:0); + (B2B1[17] => U[35]) = (0:0:0, 0:0:0); + (B2B1[17] => U[36]) = (0:0:0, 0:0:0); + (B2B1[17] => U[37]) = (0:0:0, 0:0:0); + (B2B1[17] => U[38]) = (0:0:0, 0:0:0); + (B2B1[17] => U[39]) = (0:0:0, 0:0:0); + (B2B1[17] => U[40]) = (0:0:0, 0:0:0); + (B2B1[17] => U[41]) = (0:0:0, 0:0:0); + (B2B1[17] => U[42]) = (0:0:0, 0:0:0); + (B2B1[17] => U[43]) = (0:0:0, 0:0:0); + (B2B1[17] => V[16]) = (0:0:0, 0:0:0); + (B2B1[17] => V[17]) = (0:0:0, 0:0:0); + (B2B1[17] => V[18]) = (0:0:0, 0:0:0); + (B2B1[17] => V[19]) = (0:0:0, 0:0:0); + (B2B1[17] => V[20]) = (0:0:0, 0:0:0); + (B2B1[17] => V[21]) = (0:0:0, 0:0:0); + (B2B1[17] => V[22]) = (0:0:0, 0:0:0); + (B2B1[17] => V[23]) = (0:0:0, 0:0:0); + (B2B1[17] => V[24]) = (0:0:0, 0:0:0); + (B2B1[17] => V[25]) = (0:0:0, 0:0:0); + (B2B1[17] => V[26]) = (0:0:0, 0:0:0); + (B2B1[17] => V[27]) = (0:0:0, 0:0:0); + (B2B1[17] => V[28]) = (0:0:0, 0:0:0); + (B2B1[17] => V[29]) = (0:0:0, 0:0:0); + (B2B1[17] => V[30]) = (0:0:0, 0:0:0); + (B2B1[17] => V[31]) = (0:0:0, 0:0:0); + (B2B1[17] => V[32]) = (0:0:0, 0:0:0); + (B2B1[17] => V[33]) = (0:0:0, 0:0:0); + (B2B1[17] => V[34]) = (0:0:0, 0:0:0); + (B2B1[17] => V[35]) = (0:0:0, 0:0:0); + (B2B1[17] => V[36]) = (0:0:0, 0:0:0); + (B2B1[17] => V[37]) = (0:0:0, 0:0:0); + (B2B1[17] => V[38]) = (0:0:0, 0:0:0); + (B2B1[17] => V[39]) = (0:0:0, 0:0:0); + (B2B1[17] => V[40]) = (0:0:0, 0:0:0); + (B2B1[17] => V[41]) = (0:0:0, 0:0:0); + (B2B1[17] => V[42]) = (0:0:0, 0:0:0); + (B2B1[17] => V[43]) = (0:0:0, 0:0:0); + (B2B1[1] => U[0]) = (0:0:0, 0:0:0); + (B2B1[1] => U[10]) = (0:0:0, 0:0:0); + (B2B1[1] => U[11]) = (0:0:0, 0:0:0); + (B2B1[1] => U[12]) = (0:0:0, 0:0:0); + (B2B1[1] => U[13]) = (0:0:0, 0:0:0); + (B2B1[1] => U[14]) = (0:0:0, 0:0:0); + (B2B1[1] => U[15]) = (0:0:0, 0:0:0); + (B2B1[1] => U[16]) = (0:0:0, 0:0:0); + (B2B1[1] => U[17]) = (0:0:0, 0:0:0); + (B2B1[1] => U[18]) = (0:0:0, 0:0:0); + (B2B1[1] => U[19]) = (0:0:0, 0:0:0); + (B2B1[1] => U[1]) = (0:0:0, 0:0:0); + (B2B1[1] => U[20]) = (0:0:0, 0:0:0); + (B2B1[1] => U[21]) = (0:0:0, 0:0:0); + (B2B1[1] => U[22]) = (0:0:0, 0:0:0); + (B2B1[1] => U[23]) = (0:0:0, 0:0:0); + (B2B1[1] => U[24]) = (0:0:0, 0:0:0); + (B2B1[1] => U[25]) = (0:0:0, 0:0:0); + (B2B1[1] => U[26]) = (0:0:0, 0:0:0); + (B2B1[1] => U[27]) = (0:0:0, 0:0:0); + (B2B1[1] => U[28]) = (0:0:0, 0:0:0); + (B2B1[1] => U[29]) = (0:0:0, 0:0:0); + (B2B1[1] => U[2]) = (0:0:0, 0:0:0); + (B2B1[1] => U[30]) = (0:0:0, 0:0:0); + (B2B1[1] => U[31]) = (0:0:0, 0:0:0); + (B2B1[1] => U[32]) = (0:0:0, 0:0:0); + (B2B1[1] => U[33]) = (0:0:0, 0:0:0); + (B2B1[1] => U[3]) = (0:0:0, 0:0:0); + (B2B1[1] => U[4]) = (0:0:0, 0:0:0); + (B2B1[1] => U[5]) = (0:0:0, 0:0:0); + (B2B1[1] => U[6]) = (0:0:0, 0:0:0); + (B2B1[1] => U[7]) = (0:0:0, 0:0:0); + (B2B1[1] => U[8]) = (0:0:0, 0:0:0); + (B2B1[1] => U[9]) = (0:0:0, 0:0:0); + (B2B1[1] => V[0]) = (0:0:0, 0:0:0); + (B2B1[1] => V[10]) = (0:0:0, 0:0:0); + (B2B1[1] => V[11]) = (0:0:0, 0:0:0); + (B2B1[1] => V[12]) = (0:0:0, 0:0:0); + (B2B1[1] => V[13]) = (0:0:0, 0:0:0); + (B2B1[1] => V[14]) = (0:0:0, 0:0:0); + (B2B1[1] => V[15]) = (0:0:0, 0:0:0); + (B2B1[1] => V[16]) = (0:0:0, 0:0:0); + (B2B1[1] => V[17]) = (0:0:0, 0:0:0); + (B2B1[1] => V[18]) = (0:0:0, 0:0:0); + (B2B1[1] => V[19]) = (0:0:0, 0:0:0); + (B2B1[1] => V[20]) = (0:0:0, 0:0:0); + (B2B1[1] => V[21]) = (0:0:0, 0:0:0); + (B2B1[1] => V[22]) = (0:0:0, 0:0:0); + (B2B1[1] => V[23]) = (0:0:0, 0:0:0); + (B2B1[1] => V[24]) = (0:0:0, 0:0:0); + (B2B1[1] => V[25]) = (0:0:0, 0:0:0); + (B2B1[1] => V[26]) = (0:0:0, 0:0:0); + (B2B1[1] => V[27]) = (0:0:0, 0:0:0); + (B2B1[1] => V[28]) = (0:0:0, 0:0:0); + (B2B1[1] => V[29]) = (0:0:0, 0:0:0); + (B2B1[1] => V[30]) = (0:0:0, 0:0:0); + (B2B1[1] => V[31]) = (0:0:0, 0:0:0); + (B2B1[1] => V[32]) = (0:0:0, 0:0:0); + (B2B1[1] => V[4]) = (0:0:0, 0:0:0); + (B2B1[1] => V[5]) = (0:0:0, 0:0:0); + (B2B1[1] => V[6]) = (0:0:0, 0:0:0); + (B2B1[1] => V[7]) = (0:0:0, 0:0:0); + (B2B1[1] => V[8]) = (0:0:0, 0:0:0); + (B2B1[1] => V[9]) = (0:0:0, 0:0:0); + (B2B1[2] => U[10]) = (0:0:0, 0:0:0); + (B2B1[2] => U[11]) = (0:0:0, 0:0:0); + (B2B1[2] => U[12]) = (0:0:0, 0:0:0); + (B2B1[2] => U[13]) = (0:0:0, 0:0:0); + (B2B1[2] => U[14]) = (0:0:0, 0:0:0); + (B2B1[2] => U[15]) = (0:0:0, 0:0:0); + (B2B1[2] => U[16]) = (0:0:0, 0:0:0); + (B2B1[2] => U[17]) = (0:0:0, 0:0:0); + (B2B1[2] => U[18]) = (0:0:0, 0:0:0); + (B2B1[2] => U[19]) = (0:0:0, 0:0:0); + (B2B1[2] => U[20]) = (0:0:0, 0:0:0); + (B2B1[2] => U[21]) = (0:0:0, 0:0:0); + (B2B1[2] => U[22]) = (0:0:0, 0:0:0); + (B2B1[2] => U[23]) = (0:0:0, 0:0:0); + (B2B1[2] => U[24]) = (0:0:0, 0:0:0); + (B2B1[2] => U[25]) = (0:0:0, 0:0:0); + (B2B1[2] => U[26]) = (0:0:0, 0:0:0); + (B2B1[2] => U[27]) = (0:0:0, 0:0:0); + (B2B1[2] => U[28]) = (0:0:0, 0:0:0); + (B2B1[2] => U[29]) = (0:0:0, 0:0:0); + (B2B1[2] => U[2]) = (0:0:0, 0:0:0); + (B2B1[2] => U[30]) = (0:0:0, 0:0:0); + (B2B1[2] => U[31]) = (0:0:0, 0:0:0); + (B2B1[2] => U[32]) = (0:0:0, 0:0:0); + (B2B1[2] => U[33]) = (0:0:0, 0:0:0); + (B2B1[2] => U[3]) = (0:0:0, 0:0:0); + (B2B1[2] => U[4]) = (0:0:0, 0:0:0); + (B2B1[2] => U[5]) = (0:0:0, 0:0:0); + (B2B1[2] => U[6]) = (0:0:0, 0:0:0); + (B2B1[2] => U[7]) = (0:0:0, 0:0:0); + (B2B1[2] => U[8]) = (0:0:0, 0:0:0); + (B2B1[2] => U[9]) = (0:0:0, 0:0:0); + (B2B1[2] => V[10]) = (0:0:0, 0:0:0); + (B2B1[2] => V[11]) = (0:0:0, 0:0:0); + (B2B1[2] => V[12]) = (0:0:0, 0:0:0); + (B2B1[2] => V[13]) = (0:0:0, 0:0:0); + (B2B1[2] => V[14]) = (0:0:0, 0:0:0); + (B2B1[2] => V[15]) = (0:0:0, 0:0:0); + (B2B1[2] => V[16]) = (0:0:0, 0:0:0); + (B2B1[2] => V[17]) = (0:0:0, 0:0:0); + (B2B1[2] => V[18]) = (0:0:0, 0:0:0); + (B2B1[2] => V[19]) = (0:0:0, 0:0:0); + (B2B1[2] => V[20]) = (0:0:0, 0:0:0); + (B2B1[2] => V[21]) = (0:0:0, 0:0:0); + (B2B1[2] => V[22]) = (0:0:0, 0:0:0); + (B2B1[2] => V[23]) = (0:0:0, 0:0:0); + (B2B1[2] => V[24]) = (0:0:0, 0:0:0); + (B2B1[2] => V[25]) = (0:0:0, 0:0:0); + (B2B1[2] => V[26]) = (0:0:0, 0:0:0); + (B2B1[2] => V[27]) = (0:0:0, 0:0:0); + (B2B1[2] => V[28]) = (0:0:0, 0:0:0); + (B2B1[2] => V[29]) = (0:0:0, 0:0:0); + (B2B1[2] => V[30]) = (0:0:0, 0:0:0); + (B2B1[2] => V[31]) = (0:0:0, 0:0:0); + (B2B1[2] => V[32]) = (0:0:0, 0:0:0); + (B2B1[2] => V[4]) = (0:0:0, 0:0:0); + (B2B1[2] => V[5]) = (0:0:0, 0:0:0); + (B2B1[2] => V[6]) = (0:0:0, 0:0:0); + (B2B1[2] => V[7]) = (0:0:0, 0:0:0); + (B2B1[2] => V[8]) = (0:0:0, 0:0:0); + (B2B1[2] => V[9]) = (0:0:0, 0:0:0); + (B2B1[3] => U[10]) = (0:0:0, 0:0:0); + (B2B1[3] => U[11]) = (0:0:0, 0:0:0); + (B2B1[3] => U[12]) = (0:0:0, 0:0:0); + (B2B1[3] => U[13]) = (0:0:0, 0:0:0); + (B2B1[3] => U[14]) = (0:0:0, 0:0:0); + (B2B1[3] => U[15]) = (0:0:0, 0:0:0); + (B2B1[3] => U[16]) = (0:0:0, 0:0:0); + (B2B1[3] => U[17]) = (0:0:0, 0:0:0); + (B2B1[3] => U[18]) = (0:0:0, 0:0:0); + (B2B1[3] => U[19]) = (0:0:0, 0:0:0); + (B2B1[3] => U[20]) = (0:0:0, 0:0:0); + (B2B1[3] => U[21]) = (0:0:0, 0:0:0); + (B2B1[3] => U[22]) = (0:0:0, 0:0:0); + (B2B1[3] => U[23]) = (0:0:0, 0:0:0); + (B2B1[3] => U[24]) = (0:0:0, 0:0:0); + (B2B1[3] => U[25]) = (0:0:0, 0:0:0); + (B2B1[3] => U[26]) = (0:0:0, 0:0:0); + (B2B1[3] => U[27]) = (0:0:0, 0:0:0); + (B2B1[3] => U[28]) = (0:0:0, 0:0:0); + (B2B1[3] => U[29]) = (0:0:0, 0:0:0); + (B2B1[3] => U[2]) = (0:0:0, 0:0:0); + (B2B1[3] => U[30]) = (0:0:0, 0:0:0); + (B2B1[3] => U[31]) = (0:0:0, 0:0:0); + (B2B1[3] => U[32]) = (0:0:0, 0:0:0); + (B2B1[3] => U[33]) = (0:0:0, 0:0:0); + (B2B1[3] => U[34]) = (0:0:0, 0:0:0); + (B2B1[3] => U[35]) = (0:0:0, 0:0:0); + (B2B1[3] => U[3]) = (0:0:0, 0:0:0); + (B2B1[3] => U[4]) = (0:0:0, 0:0:0); + (B2B1[3] => U[5]) = (0:0:0, 0:0:0); + (B2B1[3] => U[6]) = (0:0:0, 0:0:0); + (B2B1[3] => U[7]) = (0:0:0, 0:0:0); + (B2B1[3] => U[8]) = (0:0:0, 0:0:0); + (B2B1[3] => U[9]) = (0:0:0, 0:0:0); + (B2B1[3] => V[10]) = (0:0:0, 0:0:0); + (B2B1[3] => V[11]) = (0:0:0, 0:0:0); + (B2B1[3] => V[12]) = (0:0:0, 0:0:0); + (B2B1[3] => V[13]) = (0:0:0, 0:0:0); + (B2B1[3] => V[14]) = (0:0:0, 0:0:0); + (B2B1[3] => V[15]) = (0:0:0, 0:0:0); + (B2B1[3] => V[16]) = (0:0:0, 0:0:0); + (B2B1[3] => V[17]) = (0:0:0, 0:0:0); + (B2B1[3] => V[18]) = (0:0:0, 0:0:0); + (B2B1[3] => V[19]) = (0:0:0, 0:0:0); + (B2B1[3] => V[20]) = (0:0:0, 0:0:0); + (B2B1[3] => V[21]) = (0:0:0, 0:0:0); + (B2B1[3] => V[22]) = (0:0:0, 0:0:0); + (B2B1[3] => V[23]) = (0:0:0, 0:0:0); + (B2B1[3] => V[24]) = (0:0:0, 0:0:0); + (B2B1[3] => V[25]) = (0:0:0, 0:0:0); + (B2B1[3] => V[26]) = (0:0:0, 0:0:0); + (B2B1[3] => V[27]) = (0:0:0, 0:0:0); + (B2B1[3] => V[28]) = (0:0:0, 0:0:0); + (B2B1[3] => V[29]) = (0:0:0, 0:0:0); + (B2B1[3] => V[30]) = (0:0:0, 0:0:0); + (B2B1[3] => V[31]) = (0:0:0, 0:0:0); + (B2B1[3] => V[32]) = (0:0:0, 0:0:0); + (B2B1[3] => V[33]) = (0:0:0, 0:0:0); + (B2B1[3] => V[34]) = (0:0:0, 0:0:0); + (B2B1[3] => V[4]) = (0:0:0, 0:0:0); + (B2B1[3] => V[5]) = (0:0:0, 0:0:0); + (B2B1[3] => V[6]) = (0:0:0, 0:0:0); + (B2B1[3] => V[7]) = (0:0:0, 0:0:0); + (B2B1[3] => V[8]) = (0:0:0, 0:0:0); + (B2B1[3] => V[9]) = (0:0:0, 0:0:0); + (B2B1[4] => U[10]) = (0:0:0, 0:0:0); + (B2B1[4] => U[11]) = (0:0:0, 0:0:0); + (B2B1[4] => U[12]) = (0:0:0, 0:0:0); + (B2B1[4] => U[13]) = (0:0:0, 0:0:0); + (B2B1[4] => U[14]) = (0:0:0, 0:0:0); + (B2B1[4] => U[15]) = (0:0:0, 0:0:0); + (B2B1[4] => U[16]) = (0:0:0, 0:0:0); + (B2B1[4] => U[17]) = (0:0:0, 0:0:0); + (B2B1[4] => U[18]) = (0:0:0, 0:0:0); + (B2B1[4] => U[19]) = (0:0:0, 0:0:0); + (B2B1[4] => U[20]) = (0:0:0, 0:0:0); + (B2B1[4] => U[21]) = (0:0:0, 0:0:0); + (B2B1[4] => U[22]) = (0:0:0, 0:0:0); + (B2B1[4] => U[23]) = (0:0:0, 0:0:0); + (B2B1[4] => U[24]) = (0:0:0, 0:0:0); + (B2B1[4] => U[25]) = (0:0:0, 0:0:0); + (B2B1[4] => U[26]) = (0:0:0, 0:0:0); + (B2B1[4] => U[27]) = (0:0:0, 0:0:0); + (B2B1[4] => U[28]) = (0:0:0, 0:0:0); + (B2B1[4] => U[29]) = (0:0:0, 0:0:0); + (B2B1[4] => U[30]) = (0:0:0, 0:0:0); + (B2B1[4] => U[31]) = (0:0:0, 0:0:0); + (B2B1[4] => U[32]) = (0:0:0, 0:0:0); + (B2B1[4] => U[33]) = (0:0:0, 0:0:0); + (B2B1[4] => U[34]) = (0:0:0, 0:0:0); + (B2B1[4] => U[35]) = (0:0:0, 0:0:0); + (B2B1[4] => U[5]) = (0:0:0, 0:0:0); + (B2B1[4] => U[6]) = (0:0:0, 0:0:0); + (B2B1[4] => U[7]) = (0:0:0, 0:0:0); + (B2B1[4] => U[8]) = (0:0:0, 0:0:0); + (B2B1[4] => U[9]) = (0:0:0, 0:0:0); + (B2B1[4] => V[10]) = (0:0:0, 0:0:0); + (B2B1[4] => V[11]) = (0:0:0, 0:0:0); + (B2B1[4] => V[12]) = (0:0:0, 0:0:0); + (B2B1[4] => V[13]) = (0:0:0, 0:0:0); + (B2B1[4] => V[14]) = (0:0:0, 0:0:0); + (B2B1[4] => V[15]) = (0:0:0, 0:0:0); + (B2B1[4] => V[16]) = (0:0:0, 0:0:0); + (B2B1[4] => V[17]) = (0:0:0, 0:0:0); + (B2B1[4] => V[18]) = (0:0:0, 0:0:0); + (B2B1[4] => V[19]) = (0:0:0, 0:0:0); + (B2B1[4] => V[20]) = (0:0:0, 0:0:0); + (B2B1[4] => V[21]) = (0:0:0, 0:0:0); + (B2B1[4] => V[22]) = (0:0:0, 0:0:0); + (B2B1[4] => V[23]) = (0:0:0, 0:0:0); + (B2B1[4] => V[24]) = (0:0:0, 0:0:0); + (B2B1[4] => V[25]) = (0:0:0, 0:0:0); + (B2B1[4] => V[26]) = (0:0:0, 0:0:0); + (B2B1[4] => V[27]) = (0:0:0, 0:0:0); + (B2B1[4] => V[28]) = (0:0:0, 0:0:0); + (B2B1[4] => V[29]) = (0:0:0, 0:0:0); + (B2B1[4] => V[30]) = (0:0:0, 0:0:0); + (B2B1[4] => V[31]) = (0:0:0, 0:0:0); + (B2B1[4] => V[32]) = (0:0:0, 0:0:0); + (B2B1[4] => V[33]) = (0:0:0, 0:0:0); + (B2B1[4] => V[34]) = (0:0:0, 0:0:0); + (B2B1[4] => V[4]) = (0:0:0, 0:0:0); + (B2B1[4] => V[5]) = (0:0:0, 0:0:0); + (B2B1[4] => V[6]) = (0:0:0, 0:0:0); + (B2B1[4] => V[7]) = (0:0:0, 0:0:0); + (B2B1[4] => V[8]) = (0:0:0, 0:0:0); + (B2B1[4] => V[9]) = (0:0:0, 0:0:0); + (B2B1[5] => U[10]) = (0:0:0, 0:0:0); + (B2B1[5] => U[11]) = (0:0:0, 0:0:0); + (B2B1[5] => U[12]) = (0:0:0, 0:0:0); + (B2B1[5] => U[13]) = (0:0:0, 0:0:0); + (B2B1[5] => U[14]) = (0:0:0, 0:0:0); + (B2B1[5] => U[15]) = (0:0:0, 0:0:0); + (B2B1[5] => U[16]) = (0:0:0, 0:0:0); + (B2B1[5] => U[17]) = (0:0:0, 0:0:0); + (B2B1[5] => U[18]) = (0:0:0, 0:0:0); + (B2B1[5] => U[19]) = (0:0:0, 0:0:0); + (B2B1[5] => U[20]) = (0:0:0, 0:0:0); + (B2B1[5] => U[21]) = (0:0:0, 0:0:0); + (B2B1[5] => U[22]) = (0:0:0, 0:0:0); + (B2B1[5] => U[23]) = (0:0:0, 0:0:0); + (B2B1[5] => U[24]) = (0:0:0, 0:0:0); + (B2B1[5] => U[25]) = (0:0:0, 0:0:0); + (B2B1[5] => U[26]) = (0:0:0, 0:0:0); + (B2B1[5] => U[27]) = (0:0:0, 0:0:0); + (B2B1[5] => U[28]) = (0:0:0, 0:0:0); + (B2B1[5] => U[29]) = (0:0:0, 0:0:0); + (B2B1[5] => U[30]) = (0:0:0, 0:0:0); + (B2B1[5] => U[31]) = (0:0:0, 0:0:0); + (B2B1[5] => U[32]) = (0:0:0, 0:0:0); + (B2B1[5] => U[33]) = (0:0:0, 0:0:0); + (B2B1[5] => U[34]) = (0:0:0, 0:0:0); + (B2B1[5] => U[35]) = (0:0:0, 0:0:0); + (B2B1[5] => U[36]) = (0:0:0, 0:0:0); + (B2B1[5] => U[5]) = (0:0:0, 0:0:0); + (B2B1[5] => U[6]) = (0:0:0, 0:0:0); + (B2B1[5] => U[7]) = (0:0:0, 0:0:0); + (B2B1[5] => U[8]) = (0:0:0, 0:0:0); + (B2B1[5] => U[9]) = (0:0:0, 0:0:0); + (B2B1[5] => V[10]) = (0:0:0, 0:0:0); + (B2B1[5] => V[11]) = (0:0:0, 0:0:0); + (B2B1[5] => V[12]) = (0:0:0, 0:0:0); + (B2B1[5] => V[13]) = (0:0:0, 0:0:0); + (B2B1[5] => V[14]) = (0:0:0, 0:0:0); + (B2B1[5] => V[15]) = (0:0:0, 0:0:0); + (B2B1[5] => V[16]) = (0:0:0, 0:0:0); + (B2B1[5] => V[17]) = (0:0:0, 0:0:0); + (B2B1[5] => V[18]) = (0:0:0, 0:0:0); + (B2B1[5] => V[19]) = (0:0:0, 0:0:0); + (B2B1[5] => V[20]) = (0:0:0, 0:0:0); + (B2B1[5] => V[21]) = (0:0:0, 0:0:0); + (B2B1[5] => V[22]) = (0:0:0, 0:0:0); + (B2B1[5] => V[23]) = (0:0:0, 0:0:0); + (B2B1[5] => V[24]) = (0:0:0, 0:0:0); + (B2B1[5] => V[25]) = (0:0:0, 0:0:0); + (B2B1[5] => V[26]) = (0:0:0, 0:0:0); + (B2B1[5] => V[27]) = (0:0:0, 0:0:0); + (B2B1[5] => V[28]) = (0:0:0, 0:0:0); + (B2B1[5] => V[29]) = (0:0:0, 0:0:0); + (B2B1[5] => V[30]) = (0:0:0, 0:0:0); + (B2B1[5] => V[31]) = (0:0:0, 0:0:0); + (B2B1[5] => V[32]) = (0:0:0, 0:0:0); + (B2B1[5] => V[33]) = (0:0:0, 0:0:0); + (B2B1[5] => V[34]) = (0:0:0, 0:0:0); + (B2B1[5] => V[35]) = (0:0:0, 0:0:0); + (B2B1[5] => V[4]) = (0:0:0, 0:0:0); + (B2B1[5] => V[5]) = (0:0:0, 0:0:0); + (B2B1[5] => V[6]) = (0:0:0, 0:0:0); + (B2B1[5] => V[7]) = (0:0:0, 0:0:0); + (B2B1[5] => V[8]) = (0:0:0, 0:0:0); + (B2B1[5] => V[9]) = (0:0:0, 0:0:0); + (B2B1[6] => U[10]) = (0:0:0, 0:0:0); + (B2B1[6] => U[11]) = (0:0:0, 0:0:0); + (B2B1[6] => U[12]) = (0:0:0, 0:0:0); + (B2B1[6] => U[13]) = (0:0:0, 0:0:0); + (B2B1[6] => U[14]) = (0:0:0, 0:0:0); + (B2B1[6] => U[15]) = (0:0:0, 0:0:0); + (B2B1[6] => U[16]) = (0:0:0, 0:0:0); + (B2B1[6] => U[17]) = (0:0:0, 0:0:0); + (B2B1[6] => U[18]) = (0:0:0, 0:0:0); + (B2B1[6] => U[19]) = (0:0:0, 0:0:0); + (B2B1[6] => U[20]) = (0:0:0, 0:0:0); + (B2B1[6] => U[21]) = (0:0:0, 0:0:0); + (B2B1[6] => U[22]) = (0:0:0, 0:0:0); + (B2B1[6] => U[23]) = (0:0:0, 0:0:0); + (B2B1[6] => U[24]) = (0:0:0, 0:0:0); + (B2B1[6] => U[25]) = (0:0:0, 0:0:0); + (B2B1[6] => U[26]) = (0:0:0, 0:0:0); + (B2B1[6] => U[27]) = (0:0:0, 0:0:0); + (B2B1[6] => U[28]) = (0:0:0, 0:0:0); + (B2B1[6] => U[29]) = (0:0:0, 0:0:0); + (B2B1[6] => U[30]) = (0:0:0, 0:0:0); + (B2B1[6] => U[31]) = (0:0:0, 0:0:0); + (B2B1[6] => U[32]) = (0:0:0, 0:0:0); + (B2B1[6] => U[33]) = (0:0:0, 0:0:0); + (B2B1[6] => U[34]) = (0:0:0, 0:0:0); + (B2B1[6] => U[35]) = (0:0:0, 0:0:0); + (B2B1[6] => U[36]) = (0:0:0, 0:0:0); + (B2B1[6] => U[7]) = (0:0:0, 0:0:0); + (B2B1[6] => U[8]) = (0:0:0, 0:0:0); + (B2B1[6] => U[9]) = (0:0:0, 0:0:0); + (B2B1[6] => V[10]) = (0:0:0, 0:0:0); + (B2B1[6] => V[11]) = (0:0:0, 0:0:0); + (B2B1[6] => V[12]) = (0:0:0, 0:0:0); + (B2B1[6] => V[13]) = (0:0:0, 0:0:0); + (B2B1[6] => V[14]) = (0:0:0, 0:0:0); + (B2B1[6] => V[15]) = (0:0:0, 0:0:0); + (B2B1[6] => V[16]) = (0:0:0, 0:0:0); + (B2B1[6] => V[17]) = (0:0:0, 0:0:0); + (B2B1[6] => V[18]) = (0:0:0, 0:0:0); + (B2B1[6] => V[19]) = (0:0:0, 0:0:0); + (B2B1[6] => V[20]) = (0:0:0, 0:0:0); + (B2B1[6] => V[21]) = (0:0:0, 0:0:0); + (B2B1[6] => V[22]) = (0:0:0, 0:0:0); + (B2B1[6] => V[23]) = (0:0:0, 0:0:0); + (B2B1[6] => V[24]) = (0:0:0, 0:0:0); + (B2B1[6] => V[25]) = (0:0:0, 0:0:0); + (B2B1[6] => V[26]) = (0:0:0, 0:0:0); + (B2B1[6] => V[27]) = (0:0:0, 0:0:0); + (B2B1[6] => V[28]) = (0:0:0, 0:0:0); + (B2B1[6] => V[29]) = (0:0:0, 0:0:0); + (B2B1[6] => V[30]) = (0:0:0, 0:0:0); + (B2B1[6] => V[31]) = (0:0:0, 0:0:0); + (B2B1[6] => V[32]) = (0:0:0, 0:0:0); + (B2B1[6] => V[33]) = (0:0:0, 0:0:0); + (B2B1[6] => V[34]) = (0:0:0, 0:0:0); + (B2B1[6] => V[35]) = (0:0:0, 0:0:0); + (B2B1[6] => V[6]) = (0:0:0, 0:0:0); + (B2B1[6] => V[7]) = (0:0:0, 0:0:0); + (B2B1[6] => V[8]) = (0:0:0, 0:0:0); + (B2B1[6] => V[9]) = (0:0:0, 0:0:0); + (B2B1[7] => U[10]) = (0:0:0, 0:0:0); + (B2B1[7] => U[11]) = (0:0:0, 0:0:0); + (B2B1[7] => U[12]) = (0:0:0, 0:0:0); + (B2B1[7] => U[13]) = (0:0:0, 0:0:0); + (B2B1[7] => U[14]) = (0:0:0, 0:0:0); + (B2B1[7] => U[15]) = (0:0:0, 0:0:0); + (B2B1[7] => U[16]) = (0:0:0, 0:0:0); + (B2B1[7] => U[17]) = (0:0:0, 0:0:0); + (B2B1[7] => U[18]) = (0:0:0, 0:0:0); + (B2B1[7] => U[19]) = (0:0:0, 0:0:0); + (B2B1[7] => U[20]) = (0:0:0, 0:0:0); + (B2B1[7] => U[21]) = (0:0:0, 0:0:0); + (B2B1[7] => U[22]) = (0:0:0, 0:0:0); + (B2B1[7] => U[23]) = (0:0:0, 0:0:0); + (B2B1[7] => U[24]) = (0:0:0, 0:0:0); + (B2B1[7] => U[25]) = (0:0:0, 0:0:0); + (B2B1[7] => U[26]) = (0:0:0, 0:0:0); + (B2B1[7] => U[27]) = (0:0:0, 0:0:0); + (B2B1[7] => U[28]) = (0:0:0, 0:0:0); + (B2B1[7] => U[29]) = (0:0:0, 0:0:0); + (B2B1[7] => U[30]) = (0:0:0, 0:0:0); + (B2B1[7] => U[31]) = (0:0:0, 0:0:0); + (B2B1[7] => U[32]) = (0:0:0, 0:0:0); + (B2B1[7] => U[33]) = (0:0:0, 0:0:0); + (B2B1[7] => U[34]) = (0:0:0, 0:0:0); + (B2B1[7] => U[35]) = (0:0:0, 0:0:0); + (B2B1[7] => U[36]) = (0:0:0, 0:0:0); + (B2B1[7] => U[37]) = (0:0:0, 0:0:0); + (B2B1[7] => U[38]) = (0:0:0, 0:0:0); + (B2B1[7] => U[7]) = (0:0:0, 0:0:0); + (B2B1[7] => U[8]) = (0:0:0, 0:0:0); + (B2B1[7] => U[9]) = (0:0:0, 0:0:0); + (B2B1[7] => V[10]) = (0:0:0, 0:0:0); + (B2B1[7] => V[11]) = (0:0:0, 0:0:0); + (B2B1[7] => V[12]) = (0:0:0, 0:0:0); + (B2B1[7] => V[13]) = (0:0:0, 0:0:0); + (B2B1[7] => V[14]) = (0:0:0, 0:0:0); + (B2B1[7] => V[15]) = (0:0:0, 0:0:0); + (B2B1[7] => V[16]) = (0:0:0, 0:0:0); + (B2B1[7] => V[17]) = (0:0:0, 0:0:0); + (B2B1[7] => V[18]) = (0:0:0, 0:0:0); + (B2B1[7] => V[19]) = (0:0:0, 0:0:0); + (B2B1[7] => V[20]) = (0:0:0, 0:0:0); + (B2B1[7] => V[21]) = (0:0:0, 0:0:0); + (B2B1[7] => V[22]) = (0:0:0, 0:0:0); + (B2B1[7] => V[23]) = (0:0:0, 0:0:0); + (B2B1[7] => V[24]) = (0:0:0, 0:0:0); + (B2B1[7] => V[25]) = (0:0:0, 0:0:0); + (B2B1[7] => V[26]) = (0:0:0, 0:0:0); + (B2B1[7] => V[27]) = (0:0:0, 0:0:0); + (B2B1[7] => V[28]) = (0:0:0, 0:0:0); + (B2B1[7] => V[29]) = (0:0:0, 0:0:0); + (B2B1[7] => V[30]) = (0:0:0, 0:0:0); + (B2B1[7] => V[31]) = (0:0:0, 0:0:0); + (B2B1[7] => V[32]) = (0:0:0, 0:0:0); + (B2B1[7] => V[33]) = (0:0:0, 0:0:0); + (B2B1[7] => V[34]) = (0:0:0, 0:0:0); + (B2B1[7] => V[35]) = (0:0:0, 0:0:0); + (B2B1[7] => V[36]) = (0:0:0, 0:0:0); + (B2B1[7] => V[37]) = (0:0:0, 0:0:0); + (B2B1[7] => V[6]) = (0:0:0, 0:0:0); + (B2B1[7] => V[7]) = (0:0:0, 0:0:0); + (B2B1[7] => V[8]) = (0:0:0, 0:0:0); + (B2B1[7] => V[9]) = (0:0:0, 0:0:0); + (B2B1[8] => U[10]) = (0:0:0, 0:0:0); + (B2B1[8] => U[11]) = (0:0:0, 0:0:0); + (B2B1[8] => U[12]) = (0:0:0, 0:0:0); + (B2B1[8] => U[13]) = (0:0:0, 0:0:0); + (B2B1[8] => U[14]) = (0:0:0, 0:0:0); + (B2B1[8] => U[15]) = (0:0:0, 0:0:0); + (B2B1[8] => U[16]) = (0:0:0, 0:0:0); + (B2B1[8] => U[17]) = (0:0:0, 0:0:0); + (B2B1[8] => U[18]) = (0:0:0, 0:0:0); + (B2B1[8] => U[19]) = (0:0:0, 0:0:0); + (B2B1[8] => U[20]) = (0:0:0, 0:0:0); + (B2B1[8] => U[21]) = (0:0:0, 0:0:0); + (B2B1[8] => U[22]) = (0:0:0, 0:0:0); + (B2B1[8] => U[23]) = (0:0:0, 0:0:0); + (B2B1[8] => U[24]) = (0:0:0, 0:0:0); + (B2B1[8] => U[25]) = (0:0:0, 0:0:0); + (B2B1[8] => U[26]) = (0:0:0, 0:0:0); + (B2B1[8] => U[27]) = (0:0:0, 0:0:0); + (B2B1[8] => U[28]) = (0:0:0, 0:0:0); + (B2B1[8] => U[29]) = (0:0:0, 0:0:0); + (B2B1[8] => U[30]) = (0:0:0, 0:0:0); + (B2B1[8] => U[31]) = (0:0:0, 0:0:0); + (B2B1[8] => U[32]) = (0:0:0, 0:0:0); + (B2B1[8] => U[33]) = (0:0:0, 0:0:0); + (B2B1[8] => U[34]) = (0:0:0, 0:0:0); + (B2B1[8] => U[35]) = (0:0:0, 0:0:0); + (B2B1[8] => U[36]) = (0:0:0, 0:0:0); + (B2B1[8] => U[37]) = (0:0:0, 0:0:0); + (B2B1[8] => U[38]) = (0:0:0, 0:0:0); + (B2B1[8] => U[9]) = (0:0:0, 0:0:0); + (B2B1[8] => V[10]) = (0:0:0, 0:0:0); + (B2B1[8] => V[11]) = (0:0:0, 0:0:0); + (B2B1[8] => V[12]) = (0:0:0, 0:0:0); + (B2B1[8] => V[13]) = (0:0:0, 0:0:0); + (B2B1[8] => V[14]) = (0:0:0, 0:0:0); + (B2B1[8] => V[15]) = (0:0:0, 0:0:0); + (B2B1[8] => V[16]) = (0:0:0, 0:0:0); + (B2B1[8] => V[17]) = (0:0:0, 0:0:0); + (B2B1[8] => V[18]) = (0:0:0, 0:0:0); + (B2B1[8] => V[19]) = (0:0:0, 0:0:0); + (B2B1[8] => V[20]) = (0:0:0, 0:0:0); + (B2B1[8] => V[21]) = (0:0:0, 0:0:0); + (B2B1[8] => V[22]) = (0:0:0, 0:0:0); + (B2B1[8] => V[23]) = (0:0:0, 0:0:0); + (B2B1[8] => V[24]) = (0:0:0, 0:0:0); + (B2B1[8] => V[25]) = (0:0:0, 0:0:0); + (B2B1[8] => V[26]) = (0:0:0, 0:0:0); + (B2B1[8] => V[27]) = (0:0:0, 0:0:0); + (B2B1[8] => V[28]) = (0:0:0, 0:0:0); + (B2B1[8] => V[29]) = (0:0:0, 0:0:0); + (B2B1[8] => V[30]) = (0:0:0, 0:0:0); + (B2B1[8] => V[31]) = (0:0:0, 0:0:0); + (B2B1[8] => V[32]) = (0:0:0, 0:0:0); + (B2B1[8] => V[33]) = (0:0:0, 0:0:0); + (B2B1[8] => V[34]) = (0:0:0, 0:0:0); + (B2B1[8] => V[35]) = (0:0:0, 0:0:0); + (B2B1[8] => V[36]) = (0:0:0, 0:0:0); + (B2B1[8] => V[37]) = (0:0:0, 0:0:0); + (B2B1[8] => V[8]) = (0:0:0, 0:0:0); + (B2B1[8] => V[9]) = (0:0:0, 0:0:0); + (B2B1[9] => U[10]) = (0:0:0, 0:0:0); + (B2B1[9] => U[11]) = (0:0:0, 0:0:0); + (B2B1[9] => U[12]) = (0:0:0, 0:0:0); + (B2B1[9] => U[13]) = (0:0:0, 0:0:0); + (B2B1[9] => U[14]) = (0:0:0, 0:0:0); + (B2B1[9] => U[15]) = (0:0:0, 0:0:0); + (B2B1[9] => U[16]) = (0:0:0, 0:0:0); + (B2B1[9] => U[17]) = (0:0:0, 0:0:0); + (B2B1[9] => U[18]) = (0:0:0, 0:0:0); + (B2B1[9] => U[19]) = (0:0:0, 0:0:0); + (B2B1[9] => U[20]) = (0:0:0, 0:0:0); + (B2B1[9] => U[21]) = (0:0:0, 0:0:0); + (B2B1[9] => U[22]) = (0:0:0, 0:0:0); + (B2B1[9] => U[23]) = (0:0:0, 0:0:0); + (B2B1[9] => U[24]) = (0:0:0, 0:0:0); + (B2B1[9] => U[25]) = (0:0:0, 0:0:0); + (B2B1[9] => U[26]) = (0:0:0, 0:0:0); + (B2B1[9] => U[27]) = (0:0:0, 0:0:0); + (B2B1[9] => U[28]) = (0:0:0, 0:0:0); + (B2B1[9] => U[29]) = (0:0:0, 0:0:0); + (B2B1[9] => U[30]) = (0:0:0, 0:0:0); + (B2B1[9] => U[31]) = (0:0:0, 0:0:0); + (B2B1[9] => U[32]) = (0:0:0, 0:0:0); + (B2B1[9] => U[33]) = (0:0:0, 0:0:0); + (B2B1[9] => U[34]) = (0:0:0, 0:0:0); + (B2B1[9] => U[35]) = (0:0:0, 0:0:0); + (B2B1[9] => U[36]) = (0:0:0, 0:0:0); + (B2B1[9] => U[37]) = (0:0:0, 0:0:0); + (B2B1[9] => U[38]) = (0:0:0, 0:0:0); + (B2B1[9] => U[39]) = (0:0:0, 0:0:0); + (B2B1[9] => U[40]) = (0:0:0, 0:0:0); + (B2B1[9] => U[9]) = (0:0:0, 0:0:0); + (B2B1[9] => V[10]) = (0:0:0, 0:0:0); + (B2B1[9] => V[11]) = (0:0:0, 0:0:0); + (B2B1[9] => V[12]) = (0:0:0, 0:0:0); + (B2B1[9] => V[13]) = (0:0:0, 0:0:0); + (B2B1[9] => V[14]) = (0:0:0, 0:0:0); + (B2B1[9] => V[15]) = (0:0:0, 0:0:0); + (B2B1[9] => V[16]) = (0:0:0, 0:0:0); + (B2B1[9] => V[17]) = (0:0:0, 0:0:0); + (B2B1[9] => V[18]) = (0:0:0, 0:0:0); + (B2B1[9] => V[19]) = (0:0:0, 0:0:0); + (B2B1[9] => V[20]) = (0:0:0, 0:0:0); + (B2B1[9] => V[21]) = (0:0:0, 0:0:0); + (B2B1[9] => V[22]) = (0:0:0, 0:0:0); + (B2B1[9] => V[23]) = (0:0:0, 0:0:0); + (B2B1[9] => V[24]) = (0:0:0, 0:0:0); + (B2B1[9] => V[25]) = (0:0:0, 0:0:0); + (B2B1[9] => V[26]) = (0:0:0, 0:0:0); + (B2B1[9] => V[27]) = (0:0:0, 0:0:0); + (B2B1[9] => V[28]) = (0:0:0, 0:0:0); + (B2B1[9] => V[29]) = (0:0:0, 0:0:0); + (B2B1[9] => V[30]) = (0:0:0, 0:0:0); + (B2B1[9] => V[31]) = (0:0:0, 0:0:0); + (B2B1[9] => V[32]) = (0:0:0, 0:0:0); + (B2B1[9] => V[33]) = (0:0:0, 0:0:0); + (B2B1[9] => V[34]) = (0:0:0, 0:0:0); + (B2B1[9] => V[35]) = (0:0:0, 0:0:0); + (B2B1[9] => V[36]) = (0:0:0, 0:0:0); + (B2B1[9] => V[37]) = (0:0:0, 0:0:0); + (B2B1[9] => V[38]) = (0:0:0, 0:0:0); + (B2B1[9] => V[39]) = (0:0:0, 0:0:0); + (B2B1[9] => V[8]) = (0:0:0, 0:0:0); + (B2B1[9] => V[9]) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_M_DATA.v b/verilog/src/unisims/DSP_M_DATA.v new file mode 100644 index 0000000..c6a4546 --- /dev/null +++ b/verilog/src/unisims/DSP_M_DATA.v @@ -0,0 +1,747 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_M_DATA +// /___/ /\ Filename : DSP_M_DATA.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 04/22/13 - 713695 - Zero mult result on USE_SIMD +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_M_DATA #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RSTM_INVERTED = 1'b0, + parameter integer MREG = 1 +)( + output [44:0] U_DATA, + output [44:0] V_DATA, + + input CEM, + input CLK, + input RSTM, + input [44:0] U, + input [44:0] V +); + +// define constants + localparam MODULE_NAME = "DSP_M_DATA"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_M_DATA_dr.v" +`else + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_RSTM_INVERTED_REG = IS_RSTM_INVERTED; + reg [31:0] MREG_REG = MREG; +`endif + +`ifdef XIL_XECLIB + wire MREG_BIN; +`else + reg MREG_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CEM_in; + wire CLK_in; + wire RSTM_in; + wire [44:0] U_in; + wire [44:0] V_in; + +`ifdef XIL_TIMING + wire CEM_delay; + wire CLK_delay; + wire RSTM_delay; + wire [44:0] U_delay; + wire [44:0] V_delay; +`endif + +`ifdef XIL_TIMING +// bus inputs with only partial timing checks + assign U_delay[44] = U[44]; + assign V_delay[1] = V[1]; + assign V_delay[2] = V[2]; + assign V_delay[3] = V[3]; + assign V_delay[44] = V[44]; +`endif + +`ifdef XIL_TIMING + assign CEM_in = (CEM !== 1'bz) && CEM_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign RSTM_in = (RSTM !== 1'bz) && (RSTM_delay ^ IS_RSTM_INVERTED_REG); // rv 0 + assign U_in = U_delay; + assign V_in = V_delay; +`else + assign CEM_in = (CEM !== 1'bz) && CEM; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign RSTM_in = (RSTM !== 1'bz) && (RSTM ^ IS_RSTM_INVERTED_REG); // rv 0 + assign U_in = U; + assign V_in = V; +`endif + + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign MREG_BIN = MREG_REG[0]; + +`else +always @(trig_attr) begin +#1; + MREG_BIN = MREG_REG[0]; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((MREG_REG != 1) && + (MREG_REG != 0))) begin + $display("Error: [Unisim %s-103] MREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, MREG_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam M_WIDTH = 45; + reg [M_WIDTH-1:0] U_DATA_reg; + reg [M_WIDTH-1:0] V_DATA_reg; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + U_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}}; + V_DATA_reg = {1'b0, {M_WIDTH-1{1'b0}}}; +end +`endif + +//********************************************************* +//*** Multiplier outputs U, V with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTM_in || (MREG_BIN == 1'b0) || glblGSR) begin + U_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}}; + V_DATA_reg <= {1'b0, {M_WIDTH-1{1'b0}}}; + end else if (CEM_in) begin + U_DATA_reg <= U_in; + V_DATA_reg <= V_in; + end + end + + assign U_DATA = (MREG_BIN == 1'b1) ? U_DATA_reg : U_in; + assign V_DATA = (MREG_BIN == 1'b1) ? V_DATA_reg : V_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (CLK => U_DATA[0]) = (0:0:0, 0:0:0); + (CLK => U_DATA[10]) = (0:0:0, 0:0:0); + (CLK => U_DATA[11]) = (0:0:0, 0:0:0); + (CLK => U_DATA[12]) = (0:0:0, 0:0:0); + (CLK => U_DATA[13]) = (0:0:0, 0:0:0); + (CLK => U_DATA[14]) = (0:0:0, 0:0:0); + (CLK => U_DATA[15]) = (0:0:0, 0:0:0); + (CLK => U_DATA[16]) = (0:0:0, 0:0:0); + (CLK => U_DATA[17]) = (0:0:0, 0:0:0); + (CLK => U_DATA[18]) = (0:0:0, 0:0:0); + (CLK => U_DATA[19]) = (0:0:0, 0:0:0); + (CLK => U_DATA[1]) = (0:0:0, 0:0:0); + (CLK => U_DATA[20]) = (0:0:0, 0:0:0); + (CLK => U_DATA[21]) = (0:0:0, 0:0:0); + (CLK => U_DATA[22]) = (0:0:0, 0:0:0); + (CLK => U_DATA[23]) = (0:0:0, 0:0:0); + (CLK => U_DATA[24]) = (0:0:0, 0:0:0); + (CLK => U_DATA[25]) = (0:0:0, 0:0:0); + (CLK => U_DATA[26]) = (0:0:0, 0:0:0); + (CLK => U_DATA[27]) = (0:0:0, 0:0:0); + (CLK => U_DATA[28]) = (0:0:0, 0:0:0); + (CLK => U_DATA[29]) = (0:0:0, 0:0:0); + (CLK => U_DATA[2]) = (0:0:0, 0:0:0); + (CLK => U_DATA[30]) = (0:0:0, 0:0:0); + (CLK => U_DATA[31]) = (0:0:0, 0:0:0); + (CLK => U_DATA[32]) = (0:0:0, 0:0:0); + (CLK => U_DATA[33]) = (0:0:0, 0:0:0); + (CLK => U_DATA[34]) = (0:0:0, 0:0:0); + (CLK => U_DATA[35]) = (0:0:0, 0:0:0); + (CLK => U_DATA[36]) = (0:0:0, 0:0:0); + (CLK => U_DATA[37]) = (0:0:0, 0:0:0); + (CLK => U_DATA[38]) = (0:0:0, 0:0:0); + (CLK => U_DATA[39]) = (0:0:0, 0:0:0); + (CLK => U_DATA[3]) = (0:0:0, 0:0:0); + (CLK => U_DATA[40]) = (0:0:0, 0:0:0); + (CLK => U_DATA[41]) = (0:0:0, 0:0:0); + (CLK => U_DATA[42]) = (0:0:0, 0:0:0); + (CLK => U_DATA[43]) = (0:0:0, 0:0:0); + (CLK => U_DATA[44]) = (0:0:0, 0:0:0); + (CLK => U_DATA[4]) = (0:0:0, 0:0:0); + (CLK => U_DATA[5]) = (0:0:0, 0:0:0); + (CLK => U_DATA[6]) = (0:0:0, 0:0:0); + (CLK => U_DATA[7]) = (0:0:0, 0:0:0); + (CLK => U_DATA[8]) = (0:0:0, 0:0:0); + (CLK => U_DATA[9]) = (0:0:0, 0:0:0); + (CLK => V_DATA[0]) = (0:0:0, 0:0:0); + (CLK => V_DATA[10]) = (0:0:0, 0:0:0); + (CLK => V_DATA[11]) = (0:0:0, 0:0:0); + (CLK => V_DATA[12]) = (0:0:0, 0:0:0); + (CLK => V_DATA[13]) = (0:0:0, 0:0:0); + (CLK => V_DATA[14]) = (0:0:0, 0:0:0); + (CLK => V_DATA[15]) = (0:0:0, 0:0:0); + (CLK => V_DATA[16]) = (0:0:0, 0:0:0); + (CLK => V_DATA[17]) = (0:0:0, 0:0:0); + (CLK => V_DATA[18]) = (0:0:0, 0:0:0); + (CLK => V_DATA[19]) = (0:0:0, 0:0:0); + (CLK => V_DATA[1]) = (0:0:0, 0:0:0); + (CLK => V_DATA[20]) = (0:0:0, 0:0:0); + (CLK => V_DATA[21]) = (0:0:0, 0:0:0); + (CLK => V_DATA[22]) = (0:0:0, 0:0:0); + (CLK => V_DATA[23]) = (0:0:0, 0:0:0); + (CLK => V_DATA[24]) = (0:0:0, 0:0:0); + (CLK => V_DATA[25]) = (0:0:0, 0:0:0); + (CLK => V_DATA[26]) = (0:0:0, 0:0:0); + (CLK => V_DATA[27]) = (0:0:0, 0:0:0); + (CLK => V_DATA[28]) = (0:0:0, 0:0:0); + (CLK => V_DATA[29]) = (0:0:0, 0:0:0); + (CLK => V_DATA[2]) = (0:0:0, 0:0:0); + (CLK => V_DATA[30]) = (0:0:0, 0:0:0); + (CLK => V_DATA[31]) = (0:0:0, 0:0:0); + (CLK => V_DATA[32]) = (0:0:0, 0:0:0); + (CLK => V_DATA[33]) = (0:0:0, 0:0:0); + (CLK => V_DATA[34]) = (0:0:0, 0:0:0); + (CLK => V_DATA[35]) = (0:0:0, 0:0:0); + (CLK => V_DATA[36]) = (0:0:0, 0:0:0); + (CLK => V_DATA[37]) = (0:0:0, 0:0:0); + (CLK => V_DATA[38]) = (0:0:0, 0:0:0); + (CLK => V_DATA[39]) = (0:0:0, 0:0:0); + (CLK => V_DATA[3]) = (0:0:0, 0:0:0); + (CLK => V_DATA[40]) = (0:0:0, 0:0:0); + (CLK => V_DATA[41]) = (0:0:0, 0:0:0); + (CLK => V_DATA[42]) = (0:0:0, 0:0:0); + (CLK => V_DATA[43]) = (0:0:0, 0:0:0); + (CLK => V_DATA[44]) = (0:0:0, 0:0:0); + (CLK => V_DATA[4]) = (0:0:0, 0:0:0); + (CLK => V_DATA[5]) = (0:0:0, 0:0:0); + (CLK => V_DATA[6]) = (0:0:0, 0:0:0); + (CLK => V_DATA[7]) = (0:0:0, 0:0:0); + (CLK => V_DATA[8]) = (0:0:0, 0:0:0); + (CLK => V_DATA[9]) = (0:0:0, 0:0:0); + (U[0] => U_DATA[0]) = (0:0:0, 0:0:0); + (U[10] => U_DATA[10]) = (0:0:0, 0:0:0); + (U[11] => U_DATA[11]) = (0:0:0, 0:0:0); + (U[12] => U_DATA[12]) = (0:0:0, 0:0:0); + (U[13] => U_DATA[13]) = (0:0:0, 0:0:0); + (U[14] => U_DATA[14]) = (0:0:0, 0:0:0); + (U[15] => U_DATA[15]) = (0:0:0, 0:0:0); + (U[16] => U_DATA[16]) = (0:0:0, 0:0:0); + (U[17] => U_DATA[17]) = (0:0:0, 0:0:0); + (U[18] => U_DATA[18]) = (0:0:0, 0:0:0); + (U[19] => U_DATA[19]) = (0:0:0, 0:0:0); + (U[1] => U_DATA[1]) = (0:0:0, 0:0:0); + (U[20] => U_DATA[20]) = (0:0:0, 0:0:0); + (U[21] => U_DATA[21]) = (0:0:0, 0:0:0); + (U[22] => U_DATA[22]) = (0:0:0, 0:0:0); + (U[23] => U_DATA[23]) = (0:0:0, 0:0:0); + (U[24] => U_DATA[24]) = (0:0:0, 0:0:0); + (U[25] => U_DATA[25]) = (0:0:0, 0:0:0); + (U[26] => U_DATA[26]) = (0:0:0, 0:0:0); + (U[27] => U_DATA[27]) = (0:0:0, 0:0:0); + (U[28] => U_DATA[28]) = (0:0:0, 0:0:0); + (U[29] => U_DATA[29]) = (0:0:0, 0:0:0); + (U[2] => U_DATA[2]) = (0:0:0, 0:0:0); + (U[30] => U_DATA[30]) = (0:0:0, 0:0:0); + (U[31] => U_DATA[31]) = (0:0:0, 0:0:0); + (U[32] => U_DATA[32]) = (0:0:0, 0:0:0); + (U[33] => U_DATA[33]) = (0:0:0, 0:0:0); + (U[34] => U_DATA[34]) = (0:0:0, 0:0:0); + (U[35] => U_DATA[35]) = (0:0:0, 0:0:0); + (U[36] => U_DATA[36]) = (0:0:0, 0:0:0); + (U[37] => U_DATA[37]) = (0:0:0, 0:0:0); + (U[38] => U_DATA[38]) = (0:0:0, 0:0:0); + (U[39] => U_DATA[39]) = (0:0:0, 0:0:0); + (U[3] => U_DATA[3]) = (0:0:0, 0:0:0); + (U[40] => U_DATA[40]) = (0:0:0, 0:0:0); + (U[41] => U_DATA[41]) = (0:0:0, 0:0:0); + (U[42] => U_DATA[42]) = (0:0:0, 0:0:0); + (U[43] => U_DATA[43]) = (0:0:0, 0:0:0); + (U[4] => U_DATA[4]) = (0:0:0, 0:0:0); + (U[5] => U_DATA[5]) = (0:0:0, 0:0:0); + (U[6] => U_DATA[6]) = (0:0:0, 0:0:0); + (U[7] => U_DATA[7]) = (0:0:0, 0:0:0); + (U[8] => U_DATA[8]) = (0:0:0, 0:0:0); + (U[9] => U_DATA[9]) = (0:0:0, 0:0:0); + (V[0] => V_DATA[0]) = (0:0:0, 0:0:0); + (V[10] => V_DATA[10]) = (0:0:0, 0:0:0); + (V[11] => V_DATA[11]) = (0:0:0, 0:0:0); + (V[12] => V_DATA[12]) = (0:0:0, 0:0:0); + (V[13] => V_DATA[13]) = (0:0:0, 0:0:0); + (V[14] => V_DATA[14]) = (0:0:0, 0:0:0); + (V[15] => V_DATA[15]) = (0:0:0, 0:0:0); + (V[16] => V_DATA[16]) = (0:0:0, 0:0:0); + (V[17] => V_DATA[17]) = (0:0:0, 0:0:0); + (V[18] => V_DATA[18]) = (0:0:0, 0:0:0); + (V[19] => V_DATA[19]) = (0:0:0, 0:0:0); + (V[20] => V_DATA[20]) = (0:0:0, 0:0:0); + (V[21] => V_DATA[21]) = (0:0:0, 0:0:0); + (V[22] => V_DATA[22]) = (0:0:0, 0:0:0); + (V[23] => V_DATA[23]) = (0:0:0, 0:0:0); + (V[24] => V_DATA[24]) = (0:0:0, 0:0:0); + (V[25] => V_DATA[25]) = (0:0:0, 0:0:0); + (V[26] => V_DATA[26]) = (0:0:0, 0:0:0); + (V[27] => V_DATA[27]) = (0:0:0, 0:0:0); + (V[28] => V_DATA[28]) = (0:0:0, 0:0:0); + (V[29] => V_DATA[29]) = (0:0:0, 0:0:0); + (V[30] => V_DATA[30]) = (0:0:0, 0:0:0); + (V[31] => V_DATA[31]) = (0:0:0, 0:0:0); + (V[32] => V_DATA[32]) = (0:0:0, 0:0:0); + (V[33] => V_DATA[33]) = (0:0:0, 0:0:0); + (V[34] => V_DATA[34]) = (0:0:0, 0:0:0); + (V[35] => V_DATA[35]) = (0:0:0, 0:0:0); + (V[36] => V_DATA[36]) = (0:0:0, 0:0:0); + (V[37] => V_DATA[37]) = (0:0:0, 0:0:0); + (V[38] => V_DATA[38]) = (0:0:0, 0:0:0); + (V[39] => V_DATA[39]) = (0:0:0, 0:0:0); + (V[40] => V_DATA[40]) = (0:0:0, 0:0:0); + (V[41] => V_DATA[41]) = (0:0:0, 0:0:0); + (V[42] => V_DATA[42]) = (0:0:0, 0:0:0); + (V[43] => V_DATA[43]) = (0:0:0, 0:0:0); + (V[4] => V_DATA[4]) = (0:0:0, 0:0:0); + (V[5] => V_DATA[5]) = (0:0:0, 0:0:0); + (V[6] => V_DATA[6]) = (0:0:0, 0:0:0); + (V[7] => V_DATA[7]) = (0:0:0, 0:0:0); + (V[8] => V_DATA[8]) = (0:0:0, 0:0:0); + (V[9] => V_DATA[9]) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEM_delay); + $setuphold (negedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTM_delay); + $setuphold (negedge CLK, negedge U[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[0]); + $setuphold (negedge CLK, negedge U[10], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[10]); + $setuphold (negedge CLK, negedge U[11], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[11]); + $setuphold (negedge CLK, negedge U[12], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[12]); + $setuphold (negedge CLK, negedge U[13], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[13]); + $setuphold (negedge CLK, negedge U[14], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[14]); + $setuphold (negedge CLK, negedge U[15], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[15]); + $setuphold (negedge CLK, negedge U[16], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[16]); + $setuphold (negedge CLK, negedge U[17], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[17]); + $setuphold (negedge CLK, negedge U[18], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[18]); + $setuphold (negedge CLK, negedge U[19], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[19]); + $setuphold (negedge CLK, negedge U[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[1]); + $setuphold (negedge CLK, negedge U[20], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[20]); + $setuphold (negedge CLK, negedge U[21], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[21]); + $setuphold (negedge CLK, negedge U[22], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[22]); + $setuphold (negedge CLK, negedge U[23], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[23]); + $setuphold (negedge CLK, negedge U[24], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[24]); + $setuphold (negedge CLK, negedge U[25], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[25]); + $setuphold (negedge CLK, negedge U[26], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[26]); + $setuphold (negedge CLK, negedge U[27], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[27]); + $setuphold (negedge CLK, negedge U[28], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[28]); + $setuphold (negedge CLK, negedge U[29], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[29]); + $setuphold (negedge CLK, negedge U[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[2]); + $setuphold (negedge CLK, negedge U[30], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[30]); + $setuphold (negedge CLK, negedge U[31], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[31]); + $setuphold (negedge CLK, negedge U[32], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[32]); + $setuphold (negedge CLK, negedge U[33], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[33]); + $setuphold (negedge CLK, negedge U[34], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[34]); + $setuphold (negedge CLK, negedge U[35], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[35]); + $setuphold (negedge CLK, negedge U[36], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[36]); + $setuphold (negedge CLK, negedge U[37], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[37]); + $setuphold (negedge CLK, negedge U[38], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[38]); + $setuphold (negedge CLK, negedge U[39], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[39]); + $setuphold (negedge CLK, negedge U[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[3]); + $setuphold (negedge CLK, negedge U[40], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[40]); + $setuphold (negedge CLK, negedge U[41], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[41]); + $setuphold (negedge CLK, negedge U[42], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[42]); + $setuphold (negedge CLK, negedge U[43], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[43]); + $setuphold (negedge CLK, negedge U[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[4]); + $setuphold (negedge CLK, negedge U[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[5]); + $setuphold (negedge CLK, negedge U[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[6]); + $setuphold (negedge CLK, negedge U[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[7]); + $setuphold (negedge CLK, negedge U[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[8]); + $setuphold (negedge CLK, negedge U[9], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[9]); + $setuphold (negedge CLK, negedge V[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[0]); + $setuphold (negedge CLK, negedge V[10], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[10]); + $setuphold (negedge CLK, negedge V[11], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[11]); + $setuphold (negedge CLK, negedge V[12], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[12]); + $setuphold (negedge CLK, negedge V[13], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[13]); + $setuphold (negedge CLK, negedge V[14], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[14]); + $setuphold (negedge CLK, negedge V[15], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[15]); + $setuphold (negedge CLK, negedge V[16], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[16]); + $setuphold (negedge CLK, negedge V[17], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[17]); + $setuphold (negedge CLK, negedge V[18], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[18]); + $setuphold (negedge CLK, negedge V[19], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[19]); + $setuphold (negedge CLK, negedge V[20], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[20]); + $setuphold (negedge CLK, negedge V[21], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[21]); + $setuphold (negedge CLK, negedge V[22], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[22]); + $setuphold (negedge CLK, negedge V[23], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[23]); + $setuphold (negedge CLK, negedge V[24], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[24]); + $setuphold (negedge CLK, negedge V[25], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[25]); + $setuphold (negedge CLK, negedge V[26], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[26]); + $setuphold (negedge CLK, negedge V[27], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[27]); + $setuphold (negedge CLK, negedge V[28], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[28]); + $setuphold (negedge CLK, negedge V[29], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[29]); + $setuphold (negedge CLK, negedge V[30], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[30]); + $setuphold (negedge CLK, negedge V[31], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[31]); + $setuphold (negedge CLK, negedge V[32], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[32]); + $setuphold (negedge CLK, negedge V[33], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[33]); + $setuphold (negedge CLK, negedge V[34], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[34]); + $setuphold (negedge CLK, negedge V[35], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[35]); + $setuphold (negedge CLK, negedge V[36], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[36]); + $setuphold (negedge CLK, negedge V[37], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[37]); + $setuphold (negedge CLK, negedge V[38], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[38]); + $setuphold (negedge CLK, negedge V[39], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[39]); + $setuphold (negedge CLK, negedge V[40], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[40]); + $setuphold (negedge CLK, negedge V[41], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[41]); + $setuphold (negedge CLK, negedge V[42], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[42]); + $setuphold (negedge CLK, negedge V[43], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[43]); + $setuphold (negedge CLK, negedge V[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[4]); + $setuphold (negedge CLK, negedge V[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[5]); + $setuphold (negedge CLK, negedge V[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[6]); + $setuphold (negedge CLK, negedge V[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[7]); + $setuphold (negedge CLK, negedge V[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[8]); + $setuphold (negedge CLK, negedge V[9], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[9]); + $setuphold (negedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEM_delay); + $setuphold (negedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTM_delay); + $setuphold (negedge CLK, posedge U[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[0]); + $setuphold (negedge CLK, posedge U[10], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[10]); + $setuphold (negedge CLK, posedge U[11], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[11]); + $setuphold (negedge CLK, posedge U[12], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[12]); + $setuphold (negedge CLK, posedge U[13], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[13]); + $setuphold (negedge CLK, posedge U[14], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[14]); + $setuphold (negedge CLK, posedge U[15], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[15]); + $setuphold (negedge CLK, posedge U[16], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[16]); + $setuphold (negedge CLK, posedge U[17], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[17]); + $setuphold (negedge CLK, posedge U[18], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[18]); + $setuphold (negedge CLK, posedge U[19], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[19]); + $setuphold (negedge CLK, posedge U[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[1]); + $setuphold (negedge CLK, posedge U[20], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[20]); + $setuphold (negedge CLK, posedge U[21], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[21]); + $setuphold (negedge CLK, posedge U[22], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[22]); + $setuphold (negedge CLK, posedge U[23], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[23]); + $setuphold (negedge CLK, posedge U[24], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[24]); + $setuphold (negedge CLK, posedge U[25], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[25]); + $setuphold (negedge CLK, posedge U[26], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[26]); + $setuphold (negedge CLK, posedge U[27], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[27]); + $setuphold (negedge CLK, posedge U[28], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[28]); + $setuphold (negedge CLK, posedge U[29], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[29]); + $setuphold (negedge CLK, posedge U[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[2]); + $setuphold (negedge CLK, posedge U[30], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[30]); + $setuphold (negedge CLK, posedge U[31], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[31]); + $setuphold (negedge CLK, posedge U[32], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[32]); + $setuphold (negedge CLK, posedge U[33], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[33]); + $setuphold (negedge CLK, posedge U[34], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[34]); + $setuphold (negedge CLK, posedge U[35], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[35]); + $setuphold (negedge CLK, posedge U[36], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[36]); + $setuphold (negedge CLK, posedge U[37], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[37]); + $setuphold (negedge CLK, posedge U[38], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[38]); + $setuphold (negedge CLK, posedge U[39], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[39]); + $setuphold (negedge CLK, posedge U[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[3]); + $setuphold (negedge CLK, posedge U[40], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[40]); + $setuphold (negedge CLK, posedge U[41], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[41]); + $setuphold (negedge CLK, posedge U[42], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[42]); + $setuphold (negedge CLK, posedge U[43], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[43]); + $setuphold (negedge CLK, posedge U[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[4]); + $setuphold (negedge CLK, posedge U[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[5]); + $setuphold (negedge CLK, posedge U[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[6]); + $setuphold (negedge CLK, posedge U[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[7]); + $setuphold (negedge CLK, posedge U[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[8]); + $setuphold (negedge CLK, posedge U[9], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, U_delay[9]); + $setuphold (negedge CLK, posedge V[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[0]); + $setuphold (negedge CLK, posedge V[10], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[10]); + $setuphold (negedge CLK, posedge V[11], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[11]); + $setuphold (negedge CLK, posedge V[12], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[12]); + $setuphold (negedge CLK, posedge V[13], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[13]); + $setuphold (negedge CLK, posedge V[14], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[14]); + $setuphold (negedge CLK, posedge V[15], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[15]); + $setuphold (negedge CLK, posedge V[16], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[16]); + $setuphold (negedge CLK, posedge V[17], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[17]); + $setuphold (negedge CLK, posedge V[18], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[18]); + $setuphold (negedge CLK, posedge V[19], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[19]); + $setuphold (negedge CLK, posedge V[20], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[20]); + $setuphold (negedge CLK, posedge V[21], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[21]); + $setuphold (negedge CLK, posedge V[22], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[22]); + $setuphold (negedge CLK, posedge V[23], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[23]); + $setuphold (negedge CLK, posedge V[24], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[24]); + $setuphold (negedge CLK, posedge V[25], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[25]); + $setuphold (negedge CLK, posedge V[26], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[26]); + $setuphold (negedge CLK, posedge V[27], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[27]); + $setuphold (negedge CLK, posedge V[28], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[28]); + $setuphold (negedge CLK, posedge V[29], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[29]); + $setuphold (negedge CLK, posedge V[30], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[30]); + $setuphold (negedge CLK, posedge V[31], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[31]); + $setuphold (negedge CLK, posedge V[32], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[32]); + $setuphold (negedge CLK, posedge V[33], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[33]); + $setuphold (negedge CLK, posedge V[34], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[34]); + $setuphold (negedge CLK, posedge V[35], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[35]); + $setuphold (negedge CLK, posedge V[36], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[36]); + $setuphold (negedge CLK, posedge V[37], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[37]); + $setuphold (negedge CLK, posedge V[38], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[38]); + $setuphold (negedge CLK, posedge V[39], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[39]); + $setuphold (negedge CLK, posedge V[40], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[40]); + $setuphold (negedge CLK, posedge V[41], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[41]); + $setuphold (negedge CLK, posedge V[42], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[42]); + $setuphold (negedge CLK, posedge V[43], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[43]); + $setuphold (negedge CLK, posedge V[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[4]); + $setuphold (negedge CLK, posedge V[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[5]); + $setuphold (negedge CLK, posedge V[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[6]); + $setuphold (negedge CLK, posedge V[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[7]); + $setuphold (negedge CLK, posedge V[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[8]); + $setuphold (negedge CLK, posedge V[9], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, V_delay[9]); + $setuphold (posedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEM_delay); + $setuphold (posedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTM_delay); + $setuphold (posedge CLK, negedge U[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[0]); + $setuphold (posedge CLK, negedge U[10], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[10]); + $setuphold (posedge CLK, negedge U[11], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[11]); + $setuphold (posedge CLK, negedge U[12], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[12]); + $setuphold (posedge CLK, negedge U[13], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[13]); + $setuphold (posedge CLK, negedge U[14], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[14]); + $setuphold (posedge CLK, negedge U[15], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[15]); + $setuphold (posedge CLK, negedge U[16], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[16]); + $setuphold (posedge CLK, negedge U[17], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[17]); + $setuphold (posedge CLK, negedge U[18], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[18]); + $setuphold (posedge CLK, negedge U[19], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[19]); + $setuphold (posedge CLK, negedge U[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[1]); + $setuphold (posedge CLK, negedge U[20], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[20]); + $setuphold (posedge CLK, negedge U[21], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[21]); + $setuphold (posedge CLK, negedge U[22], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[22]); + $setuphold (posedge CLK, negedge U[23], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[23]); + $setuphold (posedge CLK, negedge U[24], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[24]); + $setuphold (posedge CLK, negedge U[25], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[25]); + $setuphold (posedge CLK, negedge U[26], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[26]); + $setuphold (posedge CLK, negedge U[27], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[27]); + $setuphold (posedge CLK, negedge U[28], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[28]); + $setuphold (posedge CLK, negedge U[29], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[29]); + $setuphold (posedge CLK, negedge U[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[2]); + $setuphold (posedge CLK, negedge U[30], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[30]); + $setuphold (posedge CLK, negedge U[31], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[31]); + $setuphold (posedge CLK, negedge U[32], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[32]); + $setuphold (posedge CLK, negedge U[33], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[33]); + $setuphold (posedge CLK, negedge U[34], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[34]); + $setuphold (posedge CLK, negedge U[35], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[35]); + $setuphold (posedge CLK, negedge U[36], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[36]); + $setuphold (posedge CLK, negedge U[37], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[37]); + $setuphold (posedge CLK, negedge U[38], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[38]); + $setuphold (posedge CLK, negedge U[39], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[39]); + $setuphold (posedge CLK, negedge U[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[3]); + $setuphold (posedge CLK, negedge U[40], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[40]); + $setuphold (posedge CLK, negedge U[41], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[41]); + $setuphold (posedge CLK, negedge U[42], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[42]); + $setuphold (posedge CLK, negedge U[43], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[43]); + $setuphold (posedge CLK, negedge U[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[4]); + $setuphold (posedge CLK, negedge U[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[5]); + $setuphold (posedge CLK, negedge U[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[6]); + $setuphold (posedge CLK, negedge U[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[7]); + $setuphold (posedge CLK, negedge U[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[8]); + $setuphold (posedge CLK, negedge U[9], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[9]); + $setuphold (posedge CLK, negedge V[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[0]); + $setuphold (posedge CLK, negedge V[10], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[10]); + $setuphold (posedge CLK, negedge V[11], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[11]); + $setuphold (posedge CLK, negedge V[12], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[12]); + $setuphold (posedge CLK, negedge V[13], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[13]); + $setuphold (posedge CLK, negedge V[14], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[14]); + $setuphold (posedge CLK, negedge V[15], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[15]); + $setuphold (posedge CLK, negedge V[16], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[16]); + $setuphold (posedge CLK, negedge V[17], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[17]); + $setuphold (posedge CLK, negedge V[18], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[18]); + $setuphold (posedge CLK, negedge V[19], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[19]); + $setuphold (posedge CLK, negedge V[20], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[20]); + $setuphold (posedge CLK, negedge V[21], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[21]); + $setuphold (posedge CLK, negedge V[22], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[22]); + $setuphold (posedge CLK, negedge V[23], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[23]); + $setuphold (posedge CLK, negedge V[24], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[24]); + $setuphold (posedge CLK, negedge V[25], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[25]); + $setuphold (posedge CLK, negedge V[26], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[26]); + $setuphold (posedge CLK, negedge V[27], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[27]); + $setuphold (posedge CLK, negedge V[28], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[28]); + $setuphold (posedge CLK, negedge V[29], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[29]); + $setuphold (posedge CLK, negedge V[30], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[30]); + $setuphold (posedge CLK, negedge V[31], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[31]); + $setuphold (posedge CLK, negedge V[32], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[32]); + $setuphold (posedge CLK, negedge V[33], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[33]); + $setuphold (posedge CLK, negedge V[34], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[34]); + $setuphold (posedge CLK, negedge V[35], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[35]); + $setuphold (posedge CLK, negedge V[36], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[36]); + $setuphold (posedge CLK, negedge V[37], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[37]); + $setuphold (posedge CLK, negedge V[38], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[38]); + $setuphold (posedge CLK, negedge V[39], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[39]); + $setuphold (posedge CLK, negedge V[40], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[40]); + $setuphold (posedge CLK, negedge V[41], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[41]); + $setuphold (posedge CLK, negedge V[42], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[42]); + $setuphold (posedge CLK, negedge V[43], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[43]); + $setuphold (posedge CLK, negedge V[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[4]); + $setuphold (posedge CLK, negedge V[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[5]); + $setuphold (posedge CLK, negedge V[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[6]); + $setuphold (posedge CLK, negedge V[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[7]); + $setuphold (posedge CLK, negedge V[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[8]); + $setuphold (posedge CLK, negedge V[9], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[9]); + $setuphold (posedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEM_delay); + $setuphold (posedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTM_delay); + $setuphold (posedge CLK, posedge U[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[0]); + $setuphold (posedge CLK, posedge U[10], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[10]); + $setuphold (posedge CLK, posedge U[11], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[11]); + $setuphold (posedge CLK, posedge U[12], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[12]); + $setuphold (posedge CLK, posedge U[13], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[13]); + $setuphold (posedge CLK, posedge U[14], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[14]); + $setuphold (posedge CLK, posedge U[15], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[15]); + $setuphold (posedge CLK, posedge U[16], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[16]); + $setuphold (posedge CLK, posedge U[17], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[17]); + $setuphold (posedge CLK, posedge U[18], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[18]); + $setuphold (posedge CLK, posedge U[19], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[19]); + $setuphold (posedge CLK, posedge U[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[1]); + $setuphold (posedge CLK, posedge U[20], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[20]); + $setuphold (posedge CLK, posedge U[21], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[21]); + $setuphold (posedge CLK, posedge U[22], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[22]); + $setuphold (posedge CLK, posedge U[23], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[23]); + $setuphold (posedge CLK, posedge U[24], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[24]); + $setuphold (posedge CLK, posedge U[25], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[25]); + $setuphold (posedge CLK, posedge U[26], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[26]); + $setuphold (posedge CLK, posedge U[27], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[27]); + $setuphold (posedge CLK, posedge U[28], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[28]); + $setuphold (posedge CLK, posedge U[29], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[29]); + $setuphold (posedge CLK, posedge U[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[2]); + $setuphold (posedge CLK, posedge U[30], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[30]); + $setuphold (posedge CLK, posedge U[31], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[31]); + $setuphold (posedge CLK, posedge U[32], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[32]); + $setuphold (posedge CLK, posedge U[33], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[33]); + $setuphold (posedge CLK, posedge U[34], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[34]); + $setuphold (posedge CLK, posedge U[35], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[35]); + $setuphold (posedge CLK, posedge U[36], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[36]); + $setuphold (posedge CLK, posedge U[37], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[37]); + $setuphold (posedge CLK, posedge U[38], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[38]); + $setuphold (posedge CLK, posedge U[39], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[39]); + $setuphold (posedge CLK, posedge U[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[3]); + $setuphold (posedge CLK, posedge U[40], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[40]); + $setuphold (posedge CLK, posedge U[41], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[41]); + $setuphold (posedge CLK, posedge U[42], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[42]); + $setuphold (posedge CLK, posedge U[43], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[43]); + $setuphold (posedge CLK, posedge U[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[4]); + $setuphold (posedge CLK, posedge U[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[5]); + $setuphold (posedge CLK, posedge U[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[6]); + $setuphold (posedge CLK, posedge U[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[7]); + $setuphold (posedge CLK, posedge U[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[8]); + $setuphold (posedge CLK, posedge U[9], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, U_delay[9]); + $setuphold (posedge CLK, posedge V[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[0]); + $setuphold (posedge CLK, posedge V[10], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[10]); + $setuphold (posedge CLK, posedge V[11], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[11]); + $setuphold (posedge CLK, posedge V[12], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[12]); + $setuphold (posedge CLK, posedge V[13], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[13]); + $setuphold (posedge CLK, posedge V[14], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[14]); + $setuphold (posedge CLK, posedge V[15], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[15]); + $setuphold (posedge CLK, posedge V[16], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[16]); + $setuphold (posedge CLK, posedge V[17], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[17]); + $setuphold (posedge CLK, posedge V[18], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[18]); + $setuphold (posedge CLK, posedge V[19], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[19]); + $setuphold (posedge CLK, posedge V[20], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[20]); + $setuphold (posedge CLK, posedge V[21], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[21]); + $setuphold (posedge CLK, posedge V[22], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[22]); + $setuphold (posedge CLK, posedge V[23], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[23]); + $setuphold (posedge CLK, posedge V[24], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[24]); + $setuphold (posedge CLK, posedge V[25], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[25]); + $setuphold (posedge CLK, posedge V[26], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[26]); + $setuphold (posedge CLK, posedge V[27], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[27]); + $setuphold (posedge CLK, posedge V[28], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[28]); + $setuphold (posedge CLK, posedge V[29], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[29]); + $setuphold (posedge CLK, posedge V[30], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[30]); + $setuphold (posedge CLK, posedge V[31], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[31]); + $setuphold (posedge CLK, posedge V[32], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[32]); + $setuphold (posedge CLK, posedge V[33], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[33]); + $setuphold (posedge CLK, posedge V[34], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[34]); + $setuphold (posedge CLK, posedge V[35], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[35]); + $setuphold (posedge CLK, posedge V[36], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[36]); + $setuphold (posedge CLK, posedge V[37], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[37]); + $setuphold (posedge CLK, posedge V[38], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[38]); + $setuphold (posedge CLK, posedge V[39], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[39]); + $setuphold (posedge CLK, posedge V[40], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[40]); + $setuphold (posedge CLK, posedge V[41], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[41]); + $setuphold (posedge CLK, posedge V[42], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[42]); + $setuphold (posedge CLK, posedge V[43], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[43]); + $setuphold (posedge CLK, posedge V[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[4]); + $setuphold (posedge CLK, posedge V[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[5]); + $setuphold (posedge CLK, posedge V[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[6]); + $setuphold (posedge CLK, posedge V[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[7]); + $setuphold (posedge CLK, posedge V[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[8]); + $setuphold (posedge CLK, posedge V[9], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, V_delay[9]); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_OUTPUT.v b/verilog/src/unisims/DSP_OUTPUT.v new file mode 100644 index 0000000..0d4a204 --- /dev/null +++ b/verilog/src/unisims/DSP_OUTPUT.v @@ -0,0 +1,543 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_OUTPUT +// /___/ /\ Filename : DSP_OUTPUT.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 04/03/13 - yaml update +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 04/23/13 - 713706 - change P_PDBK connection +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_OUTPUT #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter AUTORESET_PATDET = "NO_RESET", + parameter AUTORESET_PRIORITY = "RESET", + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RSTP_INVERTED = 1'b0, + parameter [47:0] MASK = 48'h3FFFFFFFFFFF, + parameter [47:0] PATTERN = 48'h000000000000, + parameter integer PREG = 1, + parameter SEL_MASK = "MASK", + parameter SEL_PATTERN = "PATTERN", + parameter USE_PATTERN_DETECT = "NO_PATDET" +)( + output CARRYCASCOUT, + output [3:0] CARRYOUT, + output CCOUT_FB, + output MULTSIGNOUT, + output OVERFLOW, + output [47:0] P, + output PATTERN_B_DETECT, + output PATTERN_DETECT, + output [47:0] PCOUT, + output [47:0] P_FDBK, + output P_FDBK_47, + output UNDERFLOW, + output [7:0] XOROUT, + + input ALUMODE10, + input [47:0] ALU_OUT, + input CEP, + input CLK, + input [3:0] COUT, + input [47:0] C_DATA, + input MULTSIGN_ALU, + input RSTP, + input [7:0] XOR_MX +); + +// define constants + localparam MODULE_NAME = "DSP_OUTPUT"; + +// Parameter encodings and registers + localparam AUTORESET_PATDET_NO_RESET = 0; + localparam AUTORESET_PATDET_RESET_MATCH = 1; + localparam AUTORESET_PATDET_RESET_NOT_MATCH = 2; + localparam AUTORESET_PRIORITY_CEP = 1; + localparam AUTORESET_PRIORITY_RESET = 0; + localparam SEL_MASK_C = 1; + localparam SEL_MASK_MASK = 0; + localparam SEL_MASK_ROUNDING_MODE1 = 2; + localparam SEL_MASK_ROUNDING_MODE2 = 3; + localparam SEL_PATTERN_C = 1; + localparam SEL_PATTERN_PATTERN = 0; + localparam USE_PATTERN_DETECT_NO_PATDET = 0; + localparam USE_PATTERN_DETECT_PATDET = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_OUTPUT_dr.v" +`else + reg [120:1] AUTORESET_PATDET_REG = AUTORESET_PATDET; + reg [40:1] AUTORESET_PRIORITY_REG = AUTORESET_PRIORITY; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_RSTP_INVERTED_REG = IS_RSTP_INVERTED; + reg [47:0] MASK_REG = MASK; + reg [47:0] PATTERN_REG = PATTERN; + reg [31:0] PREG_REG = PREG; + reg [112:1] SEL_MASK_REG = SEL_MASK; + reg [56:1] SEL_PATTERN_REG = SEL_PATTERN; + reg [72:1] USE_PATTERN_DETECT_REG = USE_PATTERN_DETECT; +`endif + +`ifdef XIL_XECLIB + wire [1:0] AUTORESET_PATDET_BIN; + wire AUTORESET_PRIORITY_BIN; + wire PREG_BIN; + wire [1:0] SEL_MASK_BIN; + wire SEL_PATTERN_BIN; + wire USE_PATTERN_DETECT_BIN; +`else + reg [1:0] AUTORESET_PATDET_BIN; + reg AUTORESET_PRIORITY_BIN; + reg PREG_BIN; + reg [1:0] SEL_MASK_BIN; + reg SEL_PATTERN_BIN; + reg USE_PATTERN_DETECT_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire ALUMODE10_in; + wire CEP_in; + wire CLK_in; + wire MULTSIGN_ALU_in; + wire RSTP_in; + wire [3:0] COUT_in; + wire [47:0] ALU_OUT_in; + wire [47:0] C_DATA_in; + wire [7:0] XOR_MX_in; + +`ifdef XIL_TIMING + wire ALUMODE10_delay; + wire CEP_delay; + wire CLK_delay; + wire MULTSIGN_ALU_delay; + wire RSTP_delay; + wire [3:0] COUT_delay; + wire [47:0] ALU_OUT_delay; + wire [47:0] C_DATA_delay; + wire [7:0] XOR_MX_delay; +`endif + +`ifdef XIL_TIMING + assign ALUMODE10_in = ALUMODE10_delay; + assign ALU_OUT_in = ALU_OUT_delay; + assign CEP_in = (CEP !== 1'bz) && CEP_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign COUT_in = COUT_delay; + assign C_DATA_in = C_DATA_delay; + assign MULTSIGN_ALU_in = MULTSIGN_ALU_delay; + assign RSTP_in = (RSTP !== 1'bz) && (RSTP_delay ^ IS_RSTP_INVERTED_REG); // rv 0 + assign XOR_MX_in = XOR_MX_delay; +`else + assign ALUMODE10_in = ALUMODE10; + assign ALU_OUT_in = ALU_OUT; + assign CEP_in = (CEP !== 1'bz) && CEP; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign COUT_in = COUT; + assign C_DATA_in = C_DATA; + assign MULTSIGN_ALU_in = MULTSIGN_ALU; + assign RSTP_in = (RSTP !== 1'bz) && (RSTP ^ IS_RSTP_INVERTED_REG); // rv 0 + assign XOR_MX_in = XOR_MX; +`endif + + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign AUTORESET_PATDET_BIN = + (AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET : + (AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH : + (AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH : + AUTORESET_PATDET_NO_RESET; + + assign AUTORESET_PRIORITY_BIN = + (AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET : + (AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP : + AUTORESET_PRIORITY_RESET; + + assign PREG_BIN = PREG_REG[0]; + + assign SEL_MASK_BIN = + (SEL_MASK_REG == "MASK") ? SEL_MASK_MASK : + (SEL_MASK_REG == "C") ? SEL_MASK_C : + (SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 : + (SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 : + SEL_MASK_MASK; + + assign SEL_PATTERN_BIN = + (SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN : + (SEL_PATTERN_REG == "C") ? SEL_PATTERN_C : + SEL_PATTERN_PATTERN; + + assign USE_PATTERN_DETECT_BIN = + (USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET : + (USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET : + USE_PATTERN_DETECT_NO_PATDET; + +`else +always @(trig_attr) begin +#1; + AUTORESET_PATDET_BIN = + (AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET : + (AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH : + (AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH : + AUTORESET_PATDET_NO_RESET; + + AUTORESET_PRIORITY_BIN = + (AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET : + (AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP : + AUTORESET_PRIORITY_RESET; + + PREG_BIN = PREG_REG[0]; + + SEL_MASK_BIN = + (SEL_MASK_REG == "MASK") ? SEL_MASK_MASK : + (SEL_MASK_REG == "C") ? SEL_MASK_C : + (SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 : + (SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 : + SEL_MASK_MASK; + + SEL_PATTERN_BIN = + (SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN : + (SEL_PATTERN_REG == "C") ? SEL_PATTERN_C : + SEL_PATTERN_PATTERN; + + USE_PATTERN_DETECT_BIN = + (USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET : + (USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET : + USE_PATTERN_DETECT_NO_PATDET; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((AUTORESET_PATDET_REG != "NO_RESET") && + (AUTORESET_PATDET_REG != "RESET_MATCH") && + (AUTORESET_PATDET_REG != "RESET_NOT_MATCH"))) begin + $display("Error: [Unisim %s-101] AUTORESET_PATDET attribute is set to %s. Legal values for this attribute are NO_RESET, RESET_MATCH or RESET_NOT_MATCH. Instance: %m", MODULE_NAME, AUTORESET_PATDET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AUTORESET_PRIORITY_REG != "RESET") && + (AUTORESET_PRIORITY_REG != "CEP"))) begin + $display("Error: [Unisim %s-102] AUTORESET_PRIORITY attribute is set to %s. Legal values for this attribute are RESET or CEP. Instance: %m", MODULE_NAME, AUTORESET_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREG_REG != 1) && + (PREG_REG != 0))) begin + $display("Error: [Unisim %s-107] PREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, PREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SEL_MASK_REG != "MASK") && + (SEL_MASK_REG != "C") && + (SEL_MASK_REG != "ROUNDING_MODE1") && + (SEL_MASK_REG != "ROUNDING_MODE2"))) begin + $display("Error: [Unisim %s-108] SEL_MASK attribute is set to %s. Legal values for this attribute are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2. Instance: %m", MODULE_NAME, SEL_MASK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SEL_PATTERN_REG != "PATTERN") && + (SEL_PATTERN_REG != "C"))) begin + $display("Error: [Unisim %s-109] SEL_PATTERN attribute is set to %s. Legal values for this attribute are PATTERN or C. Instance: %m", MODULE_NAME, SEL_PATTERN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_PATTERN_DETECT_REG != "NO_PATDET") && + (USE_PATTERN_DETECT_REG != "PATDET"))) begin + $display("Error: [Unisim %s-110] USE_PATTERN_DETECT attribute is set to %s. Legal values for this attribute are NO_PATDET or PATDET. Instance: %m", MODULE_NAME, USE_PATTERN_DETECT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam C_WIDTH = 48; + localparam P_WIDTH = 48; + wire the_auto_reset_patdet; + wire auto_reset_pri; + wire [47:0] the_mask; + wire [47:0] the_pattern; + reg opmode_valid_flag_dou = 1'b1; // TODO + + reg [3:0] COUT_reg; + reg ALUMODE10_reg; + wire ALUMODE10_mux; + reg MULTSIGN_ALU_reg; + reg [47:0] ALU_OUT_reg; + reg [7:0] XOR_MX_reg; + + wire pdet_o; + wire pdetb_o; + wire pdet_o_mux; + wire pdetb_o_mux; + wire overflow_data; + wire underflow_data; + reg pdet_o_reg1; + reg pdet_o_reg2; + reg pdetb_o_reg1; + reg pdetb_o_reg2; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + COUT_reg = 4'b0000; + ALUMODE10_reg = 1'b0; + MULTSIGN_ALU_reg = 1'b0; + ALU_OUT_reg = 48'b0; + XOR_MX_reg = 8'b0; + pdet_o_reg1 = 1'b0; + pdet_o_reg2 = 1'b0; + pdetb_o_reg1 = 1'b0; + pdetb_o_reg2 = 1'b0; +end +`endif + +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + + // select pattern + assign the_pattern = (SEL_PATTERN_BIN == SEL_PATTERN_PATTERN) ? PATTERN_REG : C_DATA_in; + + // select mask + assign the_mask = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_NO_PATDET) ? {C_WIDTH{1'b1}} : + (SEL_MASK_BIN == SEL_MASK_C) ? C_DATA_in : + (SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE1) ? {~(C_DATA_in[C_WIDTH-2:0]),1'b0} : + (SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE2) ? {~(C_DATA_in[C_WIDTH-3:0]),2'b0} : + MASK_REG; // default or (SEL_MASK_BIN == SEL_MASK_MASK) + + //-- now do the pattern detection + + assign pdet_o = &(~(the_pattern ^ ALU_OUT_in) | the_mask); + assign pdetb_o = &( (the_pattern ^ ALU_OUT_in) | the_mask); + + assign PATTERN_DETECT = opmode_valid_flag_dou ? pdet_o_mux : 1'bx; + assign PATTERN_B_DETECT = opmode_valid_flag_dou ? pdetb_o_mux : 1'bx; + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + + always @(posedge CLK_in) begin + if (RSTP_in || glblGSR || the_auto_reset_patdet) begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end else if (CEP_in && PREG_BIN) begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdetb_o_reg2 <= pdetb_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg1 <= pdetb_o; + end + end + + assign pdet_o_mux = (PREG_BIN == 1'b1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = (PREG_BIN == 1'b1) ? pdetb_o_reg1 : pdetb_o; + assign overflow_data = (PREG_BIN == 1'b1) ? pdet_o_reg2 : pdet_o; + assign underflow_data = (PREG_BIN == 1'b1) ? pdetb_o_reg2 : pdetb_o; + +//--#################################################################### +//--##### AUTORESET_PATDET ##### +//--#################################################################### + assign auto_reset_pri = (AUTORESET_PRIORITY_BIN == AUTORESET_PRIORITY_RESET) || CEP_in; + + assign the_auto_reset_patdet = + (AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_MATCH) ? + auto_reset_pri && pdet_o_mux : + (AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_NOT_MATCH) ? + auto_reset_pri && overflow_data && ~pdet_o_mux : 1'b0; // NO_RESET + +//--#################################################################### +//--#### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT, PCOUT and XOROUT reg ##### +//--#################################################################### +//*** register with 1 level of register + always @(posedge CLK_in) begin + if (RSTP_in || glblGSR || the_auto_reset_patdet) begin + COUT_reg <= 4'b0000; + ALUMODE10_reg <= 1'b0; + MULTSIGN_ALU_reg <= 1'b0; + ALU_OUT_reg <= 48'b0; + XOR_MX_reg <= 8'b0; + end else if (CEP_in && PREG_BIN) begin + COUT_reg <= COUT_in; + ALUMODE10_reg <= ALUMODE10_in; + MULTSIGN_ALU_reg <= MULTSIGN_ALU_in; + ALU_OUT_reg <= ALU_OUT_in; + XOR_MX_reg <= XOR_MX_in; + end + end + + assign ALUMODE10_mux = (PREG_BIN == 1'b1) ? ALUMODE10_reg : ALUMODE10_in; + assign CARRYOUT = (PREG_BIN == 1'b1) ? COUT_reg : COUT_in; + assign MULTSIGNOUT = (PREG_BIN == 1'b1) ? MULTSIGN_ALU_reg : MULTSIGN_ALU_in; + assign P = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in; + assign XOROUT = (PREG_BIN == 1'b1) ? XOR_MX_reg : XOR_MX_in; + assign CCOUT_FB = ALUMODE10_reg ^ COUT_reg[3]; + assign CARRYCASCOUT = ALUMODE10_mux ^ CARRYOUT[3]; + assign P_FDBK = ALU_OUT_reg; + assign P_FDBK_47 = ALU_OUT_reg[47]; + assign PCOUT = (PREG_BIN == 1'b1) ? ALU_OUT_reg : ALU_OUT_in; + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + assign OVERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ? + ~pdet_o_mux && ~pdetb_o_mux && overflow_data : 1'bx; + assign UNDERFLOW = (USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ? + ~pdet_o_mux && ~pdetb_o_mux && underflow_data : 1'bx; +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (ALUMODE10 => CARRYCASCOUT) = (0:0:0, 0:0:0); + (ALU_OUT *> P) = (0:0:0, 0:0:0); + (ALU_OUT *> PATTERN_B_DETECT) = (0:0:0, 0:0:0); + (ALU_OUT *> PATTERN_DETECT) = (0:0:0, 0:0:0); + (ALU_OUT *> PCOUT) = (0:0:0, 0:0:0); + (CLK *> CARRYOUT) = (0:0:0, 0:0:0); + (CLK *> P) = (0:0:0, 0:0:0); + (CLK *> PCOUT) = (0:0:0, 0:0:0); + (CLK *> P_FDBK) = (0:0:0, 0:0:0); + (CLK *> XOROUT) = (0:0:0, 0:0:0); + (CLK => CARRYCASCOUT) = (0:0:0, 0:0:0); + (CLK => CCOUT_FB) = (0:0:0, 0:0:0); + (CLK => MULTSIGNOUT) = (0:0:0, 0:0:0); + (CLK => OVERFLOW) = (0:0:0, 0:0:0); + (CLK => PATTERN_B_DETECT) = (0:0:0, 0:0:0); + (CLK => PATTERN_DETECT) = (0:0:0, 0:0:0); + (CLK => P_FDBK_47) = (0:0:0, 0:0:0); + (CLK => UNDERFLOW) = (0:0:0, 0:0:0); + (COUT *> CARRYCASCOUT) = (0:0:0, 0:0:0); + (COUT *> CARRYOUT) = (0:0:0, 0:0:0); + (C_DATA *> PATTERN_B_DETECT) = (0:0:0, 0:0:0); + (C_DATA *> PATTERN_DETECT) = (0:0:0, 0:0:0); + (MULTSIGN_ALU => MULTSIGNOUT) = (0:0:0, 0:0:0); + (XOR_MX *> XOROUT) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge ALUMODE10, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALUMODE10_delay); + $setuphold (negedge CLK, negedge ALU_OUT, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALU_OUT_delay); + $setuphold (negedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEP_delay); + $setuphold (negedge CLK, negedge COUT, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, COUT_delay); + $setuphold (negedge CLK, negedge C_DATA, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, C_DATA_delay); + $setuphold (negedge CLK, negedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, MULTSIGN_ALU_delay); + $setuphold (negedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTP_delay); + $setuphold (negedge CLK, negedge XOR_MX, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, XOR_MX_delay); + $setuphold (negedge CLK, posedge ALUMODE10, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALUMODE10_delay); + $setuphold (negedge CLK, posedge ALU_OUT, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ALU_OUT_delay); + $setuphold (negedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEP_delay); + $setuphold (negedge CLK, posedge COUT, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, COUT_delay); + $setuphold (negedge CLK, posedge C_DATA, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, C_DATA_delay); + $setuphold (negedge CLK, posedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, MULTSIGN_ALU_delay); + $setuphold (negedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTP_delay); + $setuphold (negedge CLK, posedge XOR_MX, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, XOR_MX_delay); + $setuphold (posedge CLK, negedge ALUMODE10, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALUMODE10_delay); + $setuphold (posedge CLK, negedge ALU_OUT, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALU_OUT_delay); + $setuphold (posedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEP_delay); + $setuphold (posedge CLK, negedge COUT, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, COUT_delay); + $setuphold (posedge CLK, negedge C_DATA, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, C_DATA_delay); + $setuphold (posedge CLK, negedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, MULTSIGN_ALU_delay); + $setuphold (posedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTP_delay); + $setuphold (posedge CLK, negedge XOR_MX, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, XOR_MX_delay); + $setuphold (posedge CLK, posedge ALUMODE10, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALUMODE10_delay); + $setuphold (posedge CLK, posedge ALU_OUT, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ALU_OUT_delay); + $setuphold (posedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEP_delay); + $setuphold (posedge CLK, posedge COUT, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, COUT_delay); + $setuphold (posedge CLK, posedge C_DATA, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, C_DATA_delay); + $setuphold (posedge CLK, posedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, MULTSIGN_ALU_delay); + $setuphold (posedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTP_delay); + $setuphold (posedge CLK, posedge XOR_MX, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, XOR_MX_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_PREADD.v b/verilog/src/unisims/DSP_PREADD.v new file mode 100644 index 0000000..dee4023 --- /dev/null +++ b/verilog/src/unisims/DSP_PREADD.v @@ -0,0 +1,95 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_PREADD +// /___/ /\ Filename : DSP_PREADD.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_PREADD +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output [26:0] AD, + + input ADDSUB, + input [26:0] D_DATA, + input INMODE2, + input [26:0] PREADD_AB +); + +// define constants + localparam MODULE_NAME = "DSP_PREADD"; + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +// begin behavioral model + + wire [26:0] D_DATA_mux; + +//********************************************************* +//*** Preaddsub AD +//********************************************************* + assign D_DATA_mux = INMODE2 ? D_DATA : 27'b0; + assign AD = ADDSUB ? (D_DATA_mux - PREADD_AB) : (D_DATA_mux + PREADD_AB); + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (ADDSUB *> AD) = (0:0:0, 0:0:0); + (D_DATA *> AD) = (0:0:0, 0:0:0); + (INMODE2 *> AD) = (0:0:0, 0:0:0); + (PREADD_AB *> AD) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/DSP_PREADD_DATA.v b/verilog/src/unisims/DSP_PREADD_DATA.v new file mode 100644 index 0000000..810e84d --- /dev/null +++ b/verilog/src/unisims/DSP_PREADD_DATA.v @@ -0,0 +1,560 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / DSP_PREADD_DATA +// /___/ /\ Filename : DSP_PREADD_DATA.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/15/12 - Migrate from E1. +// 12/10/12 - Add dynamic registers +// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml +// 04/23/13 - 714772 - remove sensitivity to negedge GSR +// 05/07/13 - 716896 - INMODE_INV_REG mis sized +// 10/22/14 - 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module DSP_PREADD_DATA #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer ADREG = 1, + parameter AMULTSEL = "A", + parameter BMULTSEL = "B", + parameter integer DREG = 1, + parameter integer INMODEREG = 1, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [4:0] IS_INMODE_INVERTED = 5'b00000, + parameter [0:0] IS_RSTD_INVERTED = 1'b0, + parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0, + parameter PREADDINSEL = "A", + parameter USE_MULT = "MULTIPLY" +)( + output [26:0] A2A1, + output ADDSUB, + output [26:0] AD_DATA, + output [17:0] B2B1, + output [26:0] D_DATA, + output INMODE_2, + output [26:0] PREADD_AB, + + input [26:0] A1_DATA, + input [26:0] A2_DATA, + input [26:0] AD, + input [17:0] B1_DATA, + input [17:0] B2_DATA, + input CEAD, + input CED, + input CEINMODE, + input CLK, + input [26:0] DIN, + input [4:0] INMODE, + input RSTD, + input RSTINMODE +); + +// define constants + localparam MODULE_NAME = "DSP_PREADD_DATA"; + +// Parameter encodings and registers + localparam AMULTSEL_A = 0; + localparam AMULTSEL_AD = 1; + localparam BMULTSEL_AD = 1; + localparam BMULTSEL_B = 0; + localparam PREADDINSEL_A = 0; + localparam PREADDINSEL_B = 1; + localparam USE_MULT_DYNAMIC = 1; + localparam USE_MULT_MULTIPLY = 0; + localparam USE_MULT_NONE = 2; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "DSP_PREADD_DATA_dr.v" +`else + reg [31:0] ADREG_REG = ADREG; + reg [16:1] AMULTSEL_REG = AMULTSEL; + reg [16:1] BMULTSEL_REG = BMULTSEL; + reg [31:0] DREG_REG = DREG; + reg [31:0] INMODEREG_REG = INMODEREG; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED; + reg [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED; + reg [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED; + reg [8:1] PREADDINSEL_REG = PREADDINSEL; + reg [64:1] USE_MULT_REG = USE_MULT; +`endif + +`ifdef XIL_XECLIB + wire ADREG_BIN; + wire AMULTSEL_BIN; + wire BMULTSEL_BIN; + wire DREG_BIN; + wire INMODEREG_BIN; + wire PREADDINSEL_BIN; + wire [1:0] USE_MULT_BIN; +`else + reg ADREG_BIN; + reg AMULTSEL_BIN; + reg BMULTSEL_BIN; + reg DREG_BIN; + reg INMODEREG_BIN; + reg PREADDINSEL_BIN; + reg [1:0] USE_MULT_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CEAD_in; + wire CED_in; + wire CEINMODE_in; + wire CLK_in; + wire RSTD_in; + wire RSTINMODE_in; + wire [17:0] B1_DATA_in; + wire [17:0] B2_DATA_in; + wire [26:0] A1_DATA_in; + wire [26:0] A2_DATA_in; + wire [26:0] AD_in; + wire [26:0] DIN_in; + wire [4:0] INMODE_in; + +`ifdef XIL_TIMING + wire CEAD_delay; + wire CED_delay; + wire CEINMODE_delay; + wire CLK_delay; + wire RSTD_delay; + wire RSTINMODE_delay; + wire [26:0] AD_delay; + wire [26:0] DIN_delay; + wire [4:0] INMODE_delay; +`endif + +`ifdef XIL_TIMING + assign AD_in = AD_delay; + assign CEAD_in = (CEAD !== 1'bz) && CEAD_delay; // rv 0 + assign CED_in = (CED !== 1'bz) && CED_delay; // rv 0 + assign CEINMODE_in = CEINMODE_delay; + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_in[0] = (DIN[0] !== 1'bz) && DIN_delay[0]; // rv 0 + assign DIN_in[10] = (DIN[10] !== 1'bz) && DIN_delay[10]; // rv 0 + assign DIN_in[11] = (DIN[11] !== 1'bz) && DIN_delay[11]; // rv 0 + assign DIN_in[12] = (DIN[12] !== 1'bz) && DIN_delay[12]; // rv 0 + assign DIN_in[13] = (DIN[13] !== 1'bz) && DIN_delay[13]; // rv 0 + assign DIN_in[14] = (DIN[14] !== 1'bz) && DIN_delay[14]; // rv 0 + assign DIN_in[15] = (DIN[15] !== 1'bz) && DIN_delay[15]; // rv 0 + assign DIN_in[16] = (DIN[16] !== 1'bz) && DIN_delay[16]; // rv 0 + assign DIN_in[17] = (DIN[17] !== 1'bz) && DIN_delay[17]; // rv 0 + assign DIN_in[18] = (DIN[18] !== 1'bz) && DIN_delay[18]; // rv 0 + assign DIN_in[19] = (DIN[19] !== 1'bz) && DIN_delay[19]; // rv 0 + assign DIN_in[1] = (DIN[1] !== 1'bz) && DIN_delay[1]; // rv 0 + assign DIN_in[20] = (DIN[20] !== 1'bz) && DIN_delay[20]; // rv 0 + assign DIN_in[21] = (DIN[21] !== 1'bz) && DIN_delay[21]; // rv 0 + assign DIN_in[22] = (DIN[22] !== 1'bz) && DIN_delay[22]; // rv 0 + assign DIN_in[23] = (DIN[23] !== 1'bz) && DIN_delay[23]; // rv 0 + assign DIN_in[24] = (DIN[24] !== 1'bz) && DIN_delay[24]; // rv 0 + assign DIN_in[25] = (DIN[25] !== 1'bz) && DIN_delay[25]; // rv 0 + assign DIN_in[26] = (DIN[26] !== 1'bz) && DIN_delay[26]; // rv 0 + assign DIN_in[2] = (DIN[2] !== 1'bz) && DIN_delay[2]; // rv 0 + assign DIN_in[3] = (DIN[3] !== 1'bz) && DIN_delay[3]; // rv 0 + assign DIN_in[4] = (DIN[4] !== 1'bz) && DIN_delay[4]; // rv 0 + assign DIN_in[5] = (DIN[5] !== 1'bz) && DIN_delay[5]; // rv 0 + assign DIN_in[6] = (DIN[6] !== 1'bz) && DIN_delay[6]; // rv 0 + assign DIN_in[7] = (DIN[7] !== 1'bz) && DIN_delay[7]; // rv 0 + assign DIN_in[8] = (DIN[8] !== 1'bz) && DIN_delay[8]; // rv 0 + assign DIN_in[9] = (DIN[9] !== 1'bz) && DIN_delay[9]; // rv 0 + assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE_delay[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0 + assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE_delay[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0 + assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE_delay[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0 + assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE_delay[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0 + assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE_delay[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0 + assign RSTD_in = (RSTD !== 1'bz) && (RSTD_delay ^ IS_RSTD_INVERTED_REG); // rv 0 + assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE_delay ^ IS_RSTINMODE_INVERTED_REG); // rv 0 +`else + assign AD_in = AD; + assign CEAD_in = (CEAD !== 1'bz) && CEAD; // rv 0 + assign CED_in = (CED !== 1'bz) && CED; // rv 0 + assign CEINMODE_in = CEINMODE; + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_in[0] = (DIN[0] !== 1'bz) && DIN[0]; // rv 0 + assign DIN_in[10] = (DIN[10] !== 1'bz) && DIN[10]; // rv 0 + assign DIN_in[11] = (DIN[11] !== 1'bz) && DIN[11]; // rv 0 + assign DIN_in[12] = (DIN[12] !== 1'bz) && DIN[12]; // rv 0 + assign DIN_in[13] = (DIN[13] !== 1'bz) && DIN[13]; // rv 0 + assign DIN_in[14] = (DIN[14] !== 1'bz) && DIN[14]; // rv 0 + assign DIN_in[15] = (DIN[15] !== 1'bz) && DIN[15]; // rv 0 + assign DIN_in[16] = (DIN[16] !== 1'bz) && DIN[16]; // rv 0 + assign DIN_in[17] = (DIN[17] !== 1'bz) && DIN[17]; // rv 0 + assign DIN_in[18] = (DIN[18] !== 1'bz) && DIN[18]; // rv 0 + assign DIN_in[19] = (DIN[19] !== 1'bz) && DIN[19]; // rv 0 + assign DIN_in[1] = (DIN[1] !== 1'bz) && DIN[1]; // rv 0 + assign DIN_in[20] = (DIN[20] !== 1'bz) && DIN[20]; // rv 0 + assign DIN_in[21] = (DIN[21] !== 1'bz) && DIN[21]; // rv 0 + assign DIN_in[22] = (DIN[22] !== 1'bz) && DIN[22]; // rv 0 + assign DIN_in[23] = (DIN[23] !== 1'bz) && DIN[23]; // rv 0 + assign DIN_in[24] = (DIN[24] !== 1'bz) && DIN[24]; // rv 0 + assign DIN_in[25] = (DIN[25] !== 1'bz) && DIN[25]; // rv 0 + assign DIN_in[26] = (DIN[26] !== 1'bz) && DIN[26]; // rv 0 + assign DIN_in[2] = (DIN[2] !== 1'bz) && DIN[2]; // rv 0 + assign DIN_in[3] = (DIN[3] !== 1'bz) && DIN[3]; // rv 0 + assign DIN_in[4] = (DIN[4] !== 1'bz) && DIN[4]; // rv 0 + assign DIN_in[5] = (DIN[5] !== 1'bz) && DIN[5]; // rv 0 + assign DIN_in[6] = (DIN[6] !== 1'bz) && DIN[6]; // rv 0 + assign DIN_in[7] = (DIN[7] !== 1'bz) && DIN[7]; // rv 0 + assign DIN_in[8] = (DIN[8] !== 1'bz) && DIN[8]; // rv 0 + assign DIN_in[9] = (DIN[9] !== 1'bz) && DIN[9]; // rv 0 + assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0 + assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0 + assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0 + assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0 + assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0 + assign RSTD_in = (RSTD !== 1'bz) && (RSTD ^ IS_RSTD_INVERTED_REG); // rv 0 + assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE ^ IS_RSTINMODE_INVERTED_REG); // rv 0 +`endif + + assign A1_DATA_in = A1_DATA; + assign A2_DATA_in = A2_DATA; + assign B1_DATA_in = B1_DATA; + assign B2_DATA_in = B2_DATA; + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + +initial begin + trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + attr_test = 1'b1; +`else + attr_test = 1'b0; +`endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifdef XIL_XECLIB + assign ADREG_BIN = ADREG_REG[0]; + + assign AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + assign BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + assign DREG_BIN = DREG_REG[0]; + + assign INMODEREG_BIN = INMODEREG_REG[0]; + + assign PREADDINSEL_BIN = + (PREADDINSEL_REG == "A") ? PREADDINSEL_A : + (PREADDINSEL_REG == "B") ? PREADDINSEL_B : + PREADDINSEL_A; + + assign USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + +`else +always @(trig_attr) begin +#1; + ADREG_BIN = ADREG_REG[0]; + + AMULTSEL_BIN = + (AMULTSEL_REG == "A") ? AMULTSEL_A : + (AMULTSEL_REG == "AD") ? AMULTSEL_AD : + AMULTSEL_A; + + BMULTSEL_BIN = + (BMULTSEL_REG == "B") ? BMULTSEL_B : + (BMULTSEL_REG == "AD") ? BMULTSEL_AD : + BMULTSEL_B; + + DREG_BIN = DREG_REG[0]; + + INMODEREG_BIN = INMODEREG_REG[0]; + + PREADDINSEL_BIN = + (PREADDINSEL_REG == "A") ? PREADDINSEL_A : + (PREADDINSEL_REG == "B") ? PREADDINSEL_B : + PREADDINSEL_A; + + USE_MULT_BIN = + (USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY : + (USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC : + (USE_MULT_REG == "NONE") ? USE_MULT_NONE : + USE_MULT_MULTIPLY; + +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB + always @(trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ADREG_REG != 1) && + (ADREG_REG != 0))) begin + $display("Error: [Unisim %s-101] ADREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ADREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AMULTSEL_REG != "A") && + (AMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-102] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BMULTSEL_REG != "B") && + (BMULTSEL_REG != "AD"))) begin + $display("Error: [Unisim %s-103] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DREG_REG != 1) && + (DREG_REG != 0))) begin + $display("Error: [Unisim %s-104] DREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((INMODEREG_REG != 1) && + (INMODEREG_REG != 0))) begin + $display("Error: [Unisim %s-105] INMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, INMODEREG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREADDINSEL_REG != "A") && + (PREADDINSEL_REG != "B"))) begin + $display("Error: [Unisim %s-110] PREADDINSEL attribute is set to %s. Legal values for this attribute are A or B. Instance: %m", MODULE_NAME, PREADDINSEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_MULT_REG != "MULTIPLY") && + (USE_MULT_REG != "DYNAMIC") && + (USE_MULT_REG != "NONE"))) begin + $display("Error: [Unisim %s-111] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam D_WIDTH = 27; + wire [26:0] a1a2_i_mux; + wire [17:0] b1b2_i_mux; + wire [4:0] INMODE_mux; + reg [4:0] INMODE_reg; + reg [D_WIDTH-1:0] AD_DATA_reg; + reg [D_WIDTH-1:0] D_DATA_reg; + + reg DREG_INT; + reg ADREG_INT; + +// initialize regs +`ifndef XIL_XECLIB +initial begin + INMODE_reg = 5'b0; + AD_DATA_reg = {D_WIDTH{1'b0}}; + D_DATA_reg = {D_WIDTH{1'b0}}; +end +`endif + + always @ (*) begin + if (((AMULTSEL_BIN == AMULTSEL_A) && + (BMULTSEL_BIN == BMULTSEL_B)) || + (USE_MULT_BIN == USE_MULT_NONE)) begin + DREG_INT = 1'b0; + end else begin + DREG_INT = DREG_BIN; + end + end + + always @ (*) begin + if (((AMULTSEL_BIN == AMULTSEL_A) && (BMULTSEL_BIN == BMULTSEL_B)) || + (USE_MULT_BIN == USE_MULT_NONE)) begin + ADREG_INT = 1'b0; + end else begin + ADREG_INT = ADREG_BIN; + end + end + + assign a1a2_i_mux = INMODE_mux[0] ? A1_DATA_in : A2_DATA_in; + assign b1b2_i_mux = INMODE_mux[4] ? B1_DATA_in : B2_DATA_in; + assign A2A1 = ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) ? 27'b0 : a1a2_i_mux; + assign B2B1 = ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) ? 18'b0 : b1b2_i_mux; + assign ADDSUB = INMODE_mux[3]; + + assign INMODE_2 = INMODE_mux[2]; + + assign PREADD_AB = (PREADDINSEL_BIN==PREADDINSEL_B) ? {{9{B2B1[17]}}, B2B1} : A2A1; + +//********************************************************* +//********** INMODE signal registering ************ +//********************************************************* +// new + + always @(posedge CLK_in) begin + if (RSTINMODE_in || (INMODEREG_BIN == 1'b0) || glblGSR) begin + INMODE_reg <= 5'b0; + end else if (CEINMODE_in) begin + INMODE_reg <= INMODE_in; + end + end + + assign INMODE_mux = (INMODEREG_BIN == 1'b1) ? INMODE_reg : INMODE_in; + +//********************************************************* +//*** Input register D with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTD_in || (DREG_INT == 1'b0) || glblGSR) begin + D_DATA_reg <= {D_WIDTH{1'b0}}; + end else if (CED_in) begin + D_DATA_reg <= DIN_in; + end + end + + assign D_DATA = (DREG_INT == 1'b1) ? D_DATA_reg : DIN_in; + +//********************************************************* +//*** Input register AD with 1 level deep of register +//********************************************************* + + always @(posedge CLK_in) begin + if (RSTD_in || glblGSR) begin + AD_DATA_reg <= 27'b0; + end else if (CEAD_in) AD_DATA_reg <= AD_in; + end + + assign AD_DATA = (ADREG_INT == 1'b1) ? AD_DATA_reg : AD_in; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + specify + (A1_DATA *> A2A1) = (0:0:0, 0:0:0); + (A1_DATA *> PREADD_AB) = (0:0:0, 0:0:0); + (A2_DATA *> A2A1) = (0:0:0, 0:0:0); + (A2_DATA *> PREADD_AB) = (0:0:0, 0:0:0); + (AD *> AD_DATA) = (0:0:0, 0:0:0); + (B1_DATA *> B2B1) = (0:0:0, 0:0:0); + (B1_DATA *> PREADD_AB) = (0:0:0, 0:0:0); + (B2_DATA *> B2B1) = (0:0:0, 0:0:0); + (B2_DATA *> PREADD_AB) = (0:0:0, 0:0:0); + (CLK *> A2A1) = (0:0:0, 0:0:0); + (CLK *> AD_DATA) = (0:0:0, 0:0:0); + (CLK *> B2B1) = (0:0:0, 0:0:0); + (CLK *> D_DATA) = (0:0:0, 0:0:0); + (CLK *> PREADD_AB) = (0:0:0, 0:0:0); + (CLK => ADDSUB) = (0:0:0, 0:0:0); + (CLK => INMODE_2) = (0:0:0, 0:0:0); + (DIN *> D_DATA) = (0:0:0, 0:0:0); + (INMODE *> A2A1) = (0:0:0, 0:0:0); + (INMODE *> ADDSUB) = (0:0:0, 0:0:0); + (INMODE *> B2B1) = (0:0:0, 0:0:0); + (INMODE *> INMODE_2) = (0:0:0, 0:0:0); + (INMODE *> PREADD_AB) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge CLK, negedge AD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AD_delay); + $setuphold (negedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEAD_delay); + $setuphold (negedge CLK, negedge CED, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CED_delay); + $setuphold (negedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEINMODE_delay); + $setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_delay); + $setuphold (negedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INMODE_delay); + $setuphold (negedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTD_delay); + $setuphold (negedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTINMODE_delay); + $setuphold (negedge CLK, posedge AD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AD_delay); + $setuphold (negedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEAD_delay); + $setuphold (negedge CLK, posedge CED, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CED_delay); + $setuphold (negedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEINMODE_delay); + $setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_delay); + $setuphold (negedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INMODE_delay); + $setuphold (negedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTD_delay); + $setuphold (negedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTINMODE_delay); + $setuphold (posedge CLK, negedge AD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AD_delay); + $setuphold (posedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEAD_delay); + $setuphold (posedge CLK, negedge CED, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CED_delay); + $setuphold (posedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEINMODE_delay); + $setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_delay); + $setuphold (posedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INMODE_delay); + $setuphold (posedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTD_delay); + $setuphold (posedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTINMODE_delay); + $setuphold (posedge CLK, posedge AD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AD_delay); + $setuphold (posedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEAD_delay); + $setuphold (posedge CLK, posedge CED, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CED_delay); + $setuphold (posedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEINMODE_delay); + $setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_delay); + $setuphold (posedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INMODE_delay); + $setuphold (posedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTD_delay); + $setuphold (posedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTINMODE_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/EFUSE_USR.v b/verilog/src/unisims/EFUSE_USR.v new file mode 100644 index 0000000..4a1e463 --- /dev/null +++ b/verilog/src/unisims/EFUSE_USR.v @@ -0,0 +1,60 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : EFUSE_USR.v +// \ \ / \ Timestamp : Wed Mar 19 12:34:06 2008 +// \__\/\__ \ +// +// Revision: +// 03/19/08 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module EFUSE_USR ( + EFUSEUSR +); + + parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output [31:0] EFUSEUSR; + + assign EFUSEUSR = SIM_EFUSE_VALUE; + + specify + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FDCE.v b/verilog/src/unisims/FDCE.v new file mode 100644 index 0000000..9d02932 --- /dev/null +++ b/verilog/src/unisims/FDCE.v @@ -0,0 +1,191 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / D Flip-Flop with Clock Enable and Asynchronous Clear +// /___/ /\ Filename : FDCE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/24/10 - Initial version. +// 10/20/10 - remove unused pin line from table. +// 11/01/11 - Disable timing check when set reset active (CR632017) +// 12/08/11 - add MSGON and XON attributes (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module FDCE #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b0, + parameter [0:0] IS_CLR_INVERTED = 1'b0, + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D_INVERTED = 1'b0 +)( + output Q, + + input C, + input CE, + input CLR, + input D +); + + reg [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED; + reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; + + tri0 glblGSR = glbl.GSR; + +`ifdef XIL_TIMING + wire D_dly, C_dly, CE_dly; + wire CLR_dly; +`endif + + wire CLR_in; + +`ifdef XIL_TIMING + assign CLR_in = (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz); +`else + assign CLR_in = (CLR ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz); +`endif + +// begin behavioral model + + reg Q_out; + + assign #100 Q = Q_out; + + always @(glblGSR or CLR_in) + if (glblGSR) + assign Q_out = INIT; + else if (CLR_in === 1'b1) + assign Q_out = 1'b0; + else if (CLR_in === 1'bx) + assign Q_out = 1'bx; + else + deassign Q_out; + +`ifdef XIL_TIMING +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C_dly or posedge CLR_in) + if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C_dly or posedge CLR_in) + if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end +endgenerate +`else +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C or posedge CLR_in) + if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C or posedge CLR_in) + if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end +endgenerate +`endif + +`ifdef XIL_TIMING + reg notifier; + wire notifier1; +`endif + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nrst; + wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; + wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; + reg init_enable = 1'b1; + wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n; +`endif + +`ifdef XIL_TIMING + not (ngsr, glblGSR); + xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); + not (nrst, (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz)); + + and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz)); + and (ce_clk_enable, ngsr, nrst, in_out); + and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); + always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); + assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1); + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); + assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0); +`endif + +// end behavioral model + +`ifdef XIL_TIMING + specify + (C => Q) = (100:100:100, 100:100:100); + (negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); + (posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); + (CLR => Q) = (0:0:0, 0:0:0); + $period (negedge C &&& CE, 0:0:0, notifier); + $period (posedge C &&& CE, 0:0:0, notifier); + $recrem (negedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly); + $recrem (negedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly); + $recrem (posedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly); + $recrem (posedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $width (negedge C &&& CE, 0:0:0, 0, notifier); + $width (negedge CLR &&& init_enable, 0:0:0, 0, notifier); + $width (posedge C &&& CE, 0:0:0, 0, notifier); + $width (posedge CLR &&& init_enable, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FDPE.v b/verilog/src/unisims/FDPE.v new file mode 100644 index 0000000..2597c6c --- /dev/null +++ b/verilog/src/unisims/FDPE.v @@ -0,0 +1,191 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / D Flip-Flop with Clock Enable and Asynchronous Preset +// /___/ /\ Filename : FDPE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/25/10 - Initial version. +// 10/20/10 - remove unused pin line from table. +// 11/01/11 - Disable timing check when set reset active (CR632017) +// 12/08/11 - add MSGON and XON attributes (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module FDPE #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D_INVERTED = 1'b0, + parameter [0:0] IS_PRE_INVERTED = 1'b0 +)( + output Q, + + input C, + input CE, + input D, + input PRE +); + + reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; + reg [0:0] IS_PRE_INVERTED_REG = IS_PRE_INVERTED; + + tri0 glblGSR = glbl.GSR; + +`ifdef XIL_TIMING + wire D_dly, C_dly, CE_dly; + wire PRE_dly; +`endif + + wire PRE_in; + +`ifdef XIL_TIMING + assign PRE_in = (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz); +`else + assign PRE_in = (PRE ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz); +`endif + +// begin behavioral model + + reg Q_out; + + assign #100 Q = Q_out; + + always @(glblGSR or PRE_in) + if (glblGSR) + assign Q_out = INIT; + else if (PRE_in === 1'b1) + assign Q_out = 1'b1; + else if (PRE_in === 1'bx) + assign Q_out = 1'bx; + else + deassign Q_out; + +`ifdef XIL_TIMING +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C_dly or posedge PRE_in) + if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C_dly or posedge PRE_in) + if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end +endgenerate +`else +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C or posedge PRE_in) + if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C or posedge PRE_in) + if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end +endgenerate +`endif + +`ifdef XIL_TIMING + reg notifier; + wire notifier1; +`endif + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nset; + wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; + wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; + reg init_enable = 1'b1; + wire set_clk_enable, set_clk_enable_p, set_clk_enable_n; +`endif + +`ifdef XIL_TIMING + not (ngsr, glblGSR); + xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); + not (nset, (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz)); + + and (in_clk_enable, ngsr, nset, CE || (CE === 1'bz)); + and (ce_clk_enable, ngsr, nset, in_out); + and (set_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); + always @(negedge nset) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); + assign set_clk_enable_n = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b1); + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); + assign set_clk_enable_p = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b0); +`endif + +// end behavioral model + +`ifdef XIL_TIMING + specify + (C => Q) = (100:100:100, 100:100:100); + (negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); + (posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); + (PRE => Q) = (0:0:0, 0:0:0); + $period (negedge C &&& CE, 0:0:0, notifier); + $period (posedge C &&& CE, 0:0:0, notifier); + $recrem (negedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly); + $recrem (negedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly); + $recrem (posedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly); + $recrem (posedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $width (negedge C &&& CE, 0:0:0, 0, notifier); + $width (negedge PRE &&& init_enable, 0:0:0, 0, notifier); + $width (posedge C &&& CE, 0:0:0, 0, notifier); + $width (posedge PRE &&& init_enable, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FDRE.v b/verilog/src/unisims/FDRE.v new file mode 100644 index 0000000..6f3fb7f --- /dev/null +++ b/verilog/src/unisims/FDRE.v @@ -0,0 +1,175 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / D Flip-Flop with Clock Enable and Synchronous Reset +// /___/ /\ Filename : FDRE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/25/10 - Initial version. +// 10/20/10 - remove unused pin line from table. +// 12/08/11 - add MSGON and XON attributes (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module FDRE #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b0, + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D_INVERTED = 1'b0, + parameter [0:0] IS_R_INVERTED = 1'b0 +)( + output Q, + + input C, + input CE, + input D, + input R +); + + reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; + reg [0:0] IS_R_INVERTED_REG = IS_R_INVERTED; + + tri0 glblGSR = glbl.GSR; + +`ifdef XIL_TIMING + wire D_dly, C_dly, CE_dly; + wire R_dly; +`endif + +// begin behavioral model + + reg Q_out; + + assign #100 Q = Q_out; + + always @(glblGSR) + if (glblGSR) + assign Q_out = INIT; + else + deassign Q_out; + +`ifdef XIL_TIMING +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C_dly) + if (((R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C_dly) + if (((R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end +endgenerate +`else +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C) + if (((R ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C) + if (((R ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0)) + Q_out <= 1'b0; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end +endgenerate +`endif + +`ifdef XIL_TIMING + reg notifier; + wire notifier1; +`endif + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nrst; + wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; + wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; + reg init_enable = 1'b1; + wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n; +`endif + +`ifdef XIL_TIMING + not (ngsr, glblGSR); + xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); + not (nrst, (R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz)); + + and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz)); + and (ce_clk_enable, ngsr, nrst, in_out); + and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); + always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); + assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1); + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); + assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0); +`endif + +// end behavioral model + +`ifdef XIL_TIMING + specify + (C => Q) = (100:100:100, 100:100:100); + $period (negedge C &&& CE, 0:0:0, notifier); + $period (posedge C &&& CE, 0:0:0, notifier); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, negedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,C_dly,R_dly); + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, posedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,C_dly,R_dly); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, negedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,C_dly,R_dly); + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, posedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,C_dly,R_dly); + $width (negedge C &&& CE, 0:0:0, 0, notifier); + $width (negedge R &&& init_enable, 0:0:0, 0, notifier); + $width (posedge C &&& CE, 0:0:0, 0, notifier); + $width (posedge R &&& init_enable, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FDSE.v b/verilog/src/unisims/FDSE.v new file mode 100644 index 0000000..0233912 --- /dev/null +++ b/verilog/src/unisims/FDSE.v @@ -0,0 +1,175 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / D Flip-Flop with Clock Enable and Synchronous Set +// /___/ /\ Filename : FDSE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/25/10 - Initial version. +// 10/20/10 - remove unused pin line from table. +// 12/08/11 - add MSGON and XON attributes (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module FDSE #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D_INVERTED = 1'b0, + parameter [0:0] IS_S_INVERTED = 1'b0 +)( + output Q, + + input C, + input CE, + input D, + input S +); + + reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; + reg [0:0] IS_S_INVERTED_REG = IS_S_INVERTED; + + tri0 glblGSR = glbl.GSR; + +`ifdef XIL_TIMING + wire D_dly, C_dly, CE_dly; + wire S_dly; +`endif + +// begin behavioral model + + reg Q_out; + + assign #100 Q = Q_out; + +// end behavioral model + + always @(glblGSR) + if (glblGSR) + assign Q_out = INIT; + else + deassign Q_out; + +`ifdef XIL_TIMING +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C_dly) + if (((S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C_dly) + if (((S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) + Q_out <= D_dly ^ IS_D_INVERTED_REG; +end +endgenerate +`else +generate +if (IS_C_INVERTED == 1'b0) begin : generate_block1 + always @(posedge C) + if (((S ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end else begin : generate_block1 + always @(negedge C) + if (((S ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1)) + Q_out <= 1'b1; + else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) + Q_out <= D ^ IS_D_INVERTED_REG; +end +endgenerate +`endif + +`ifdef XIL_TIMING + reg notifier; + wire notifier1; +`endif + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nset; + wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; + wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; + reg init_enable = 1'b1; + wire set_clk_enable, set_clk_enable_p, set_clk_enable_n; +`endif + +`ifdef XIL_TIMING + not (ngsr, glblGSR); + xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); + not (nset, (S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz)); + + and (in_clk_enable, ngsr, nset, CE || (CE === 1'bz)); + and (ce_clk_enable, ngsr, nset, in_out); + and (set_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); + always @(negedge nset) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); + assign set_clk_enable_n = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b1); + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); + assign set_clk_enable_p = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b0); +`endif + +`ifdef XIL_TIMING + specify + (C => Q) = (100:100:100, 100:100:100); + $period (negedge C &&& CE, 0:0:0, notifier); + $period (posedge C &&& CE, 0:0:0, notifier); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, negedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,C_dly,S_dly); + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); + $setuphold (negedge C, posedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,C_dly,S_dly); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, negedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,C_dly,S_dly); + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); + $setuphold (posedge C, posedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,C_dly,S_dly); + $width (negedge C &&& CE, 0:0:0, 0, notifier); + $width (negedge S &&& init_enable, 0:0:0, 0, notifier); + $width (posedge C &&& CE, 0:0:0, 0, notifier); + $width (posedge S &&& init_enable, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FE.v b/verilog/src/unisims/FE.v new file mode 100644 index 0000000..b45b67a --- /dev/null +++ b/verilog/src/unisims/FE.v @@ -0,0 +1,4235 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / FE +// /___/ /\ Filename : FE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module FE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter MODE = "TURBO_DECODE", + parameter real PHYSICAL_UTILIZATION = 100.00, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter STANDARD = "LTE", + parameter real THROUGHPUT_UTILIZATION = 100.00 +)( + output [399:0] DEBUG_DOUT, + output DEBUG_PHASE, + output INTERRUPT, + output [511:0] M_AXIS_DOUT_TDATA, + output M_AXIS_DOUT_TLAST, + output M_AXIS_DOUT_TVALID, + output [31:0] M_AXIS_STATUS_TDATA, + output M_AXIS_STATUS_TVALID, + output [15:0] SPARE_OUT, + output S_AXIS_CTRL_TREADY, + output S_AXIS_DIN_TREADY, + output S_AXIS_DIN_WORDS_TREADY, + output S_AXIS_DOUT_WORDS_TREADY, + output S_AXI_ARREADY, + output S_AXI_AWREADY, + output S_AXI_BVALID, + output [31:0] S_AXI_RDATA, + output S_AXI_RVALID, + output S_AXI_WREADY, + + input CORE_CLK, + input DEBUG_CLK_EN, + input DEBUG_EN, + input [3:0] DEBUG_SEL_IN, + input M_AXIS_DOUT_ACLK, + input M_AXIS_DOUT_TREADY, + input M_AXIS_STATUS_ACLK, + input M_AXIS_STATUS_TREADY, + input RESET_N, + input [15:0] SPARE_IN, + input S_AXIS_CTRL_ACLK, + input [31:0] S_AXIS_CTRL_TDATA, + input S_AXIS_CTRL_TVALID, + input S_AXIS_DIN_ACLK, + input [511:0] S_AXIS_DIN_TDATA, + input S_AXIS_DIN_TLAST, + input S_AXIS_DIN_TVALID, + input S_AXIS_DIN_WORDS_ACLK, + input [31:0] S_AXIS_DIN_WORDS_TDATA, + input S_AXIS_DIN_WORDS_TLAST, + input S_AXIS_DIN_WORDS_TVALID, + input S_AXIS_DOUT_WORDS_ACLK, + input [31:0] S_AXIS_DOUT_WORDS_TDATA, + input S_AXIS_DOUT_WORDS_TLAST, + input S_AXIS_DOUT_WORDS_TVALID, + input S_AXI_ACLK, + input [17:0] S_AXI_ARADDR, + input S_AXI_ARVALID, + input [17:0] S_AXI_AWADDR, + input S_AXI_AWVALID, + input S_AXI_BREADY, + input S_AXI_RREADY, + input [31:0] S_AXI_WDATA, + input S_AXI_WVALID +); + +// define constants + localparam MODULE_NAME = "FE"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "FE_dr.v" +`else + reg [96:1] MODE_REG = MODE; + real PHYSICAL_UTILIZATION_REG = PHYSICAL_UTILIZATION; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [48:1] STANDARD_REG = STANDARD; + real THROUGHPUT_UTILIZATION_REG = THROUGHPUT_UTILIZATION; +`endif + +`ifdef XIL_XECLIB + wire [63:0] PHYSICAL_UTILIZATION_BIN; + wire [63:0] THROUGHPUT_UTILIZATION_BIN; +`else + reg [63:0] PHYSICAL_UTILIZATION_BIN; + reg [63:0] THROUGHPUT_UTILIZATION_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CSSD_CLK_STOP_DONE_out; + wire DEBUG_PHASE_out; + wire INTERRUPT_out; + wire MBIST_COMPSTAT_out; + wire MBIST_TDO_out; + wire M_AXIS_DOUT_TLAST_out; + wire M_AXIS_DOUT_TVALID_out; + wire M_AXIS_STATUS_TVALID_out; + wire S_AXIS_CTRL_TREADY_out; + wire S_AXIS_DIN_TREADY_out; + wire S_AXIS_DIN_WORDS_TREADY_out; + wire S_AXIS_DOUT_WORDS_TREADY_out; + wire S_AXI_ARREADY_out; + wire S_AXI_AWREADY_out; + wire S_AXI_BVALID_out; + wire S_AXI_RVALID_out; + wire S_AXI_WREADY_out; + wire [15:0] SPARE_OUT_out; + wire [199:0] SCANOUT_out; + wire [31:0] M_AXIS_STATUS_TDATA_out; + wire [31:0] S_AXI_RDATA_out; + wire [399:0] DEBUG_DOUT_out; + wire [511:0] M_AXIS_DOUT_TDATA_out; + wire [710:0] XIL_UNCONN_OUT_out; + + wire CORE_CLK_in; + wire CSSD_RST_N_in; + wire CTL_CSSD_EN_N_in; + wire CTL_CSSD_SNGL_CHAIN_MD_N_in; + wire DEBUG_CLK_EN_in; + wire DEBUG_EN_in; + wire DFTRAM_BYPASS_N_in; + wire MBIST_TCK_in; + wire MBIST_TDI_in; + wire MBIST_TMS_in; + wire MBIST_TRST_in; + wire M_AXIS_DOUT_ACLK_in; + wire M_AXIS_DOUT_TREADY_in; + wire M_AXIS_STATUS_ACLK_in; + wire M_AXIS_STATUS_TREADY_in; + wire RESET_N_in; + wire SCANENABLE_N_in; + wire SCANMODE_N_in; + wire SCAN_CLK_in; + wire S_AXIS_CTRL_ACLK_in; + wire S_AXIS_CTRL_TVALID_in; + wire S_AXIS_DIN_ACLK_in; + wire S_AXIS_DIN_TLAST_in; + wire S_AXIS_DIN_TVALID_in; + wire S_AXIS_DIN_WORDS_ACLK_in; + wire S_AXIS_DIN_WORDS_TLAST_in; + wire S_AXIS_DIN_WORDS_TVALID_in; + wire S_AXIS_DOUT_WORDS_ACLK_in; + wire S_AXIS_DOUT_WORDS_TLAST_in; + wire S_AXIS_DOUT_WORDS_TVALID_in; + wire S_AXI_ACLK_in; + wire S_AXI_ARVALID_in; + wire S_AXI_AWVALID_in; + wire S_AXI_BREADY_in; + wire S_AXI_RREADY_in; + wire S_AXI_WVALID_in; + wire TEST_MODE_PIN_CHAR_N_in; + wire [15:0] CTL_CSSD_MRKR_START_INIT_in; + wire [15:0] CTL_CSSD_MRKR_STOP_INIT_in; + wire [15:0] SPARE_IN_in; + wire [17:0] S_AXI_ARADDR_in; + wire [17:0] S_AXI_AWADDR_in; + wire [1861:0] XIL_UNCONN_IN_in; + wire [199:0] SCANIN_in; + wire [2:0] CTL_CSSD_ROOT_CLK_SEL_in; + wire [31:0] S_AXIS_CTRL_TDATA_in; + wire [31:0] S_AXIS_DIN_WORDS_TDATA_in; + wire [31:0] S_AXIS_DOUT_WORDS_TDATA_in; + wire [31:0] S_AXI_WDATA_in; + wire [3:0] CSSD_CLK_STOP_EVENT_in; + wire [3:0] DEBUG_SEL_IN_in; + wire [469:0] XIL_UNCONN_CLK_in; + wire [47:0] CTL_CSSD_STOP_COUNT_in; + wire [511:0] S_AXIS_DIN_TDATA_in; + wire [7:0] CTL_CSSD_ROOT_CLK_DIS_in; + +`ifdef XIL_TIMING + wire CORE_CLK_delay; + wire DEBUG_EN_delay; + wire M_AXIS_DOUT_ACLK_delay; + wire M_AXIS_DOUT_TREADY_delay; + wire M_AXIS_STATUS_ACLK_delay; + wire M_AXIS_STATUS_TREADY_delay; + wire S_AXIS_CTRL_ACLK_delay; + wire S_AXIS_CTRL_TVALID_delay; + wire S_AXIS_DIN_ACLK_delay; + wire S_AXIS_DIN_TLAST_delay; + wire S_AXIS_DIN_TVALID_delay; + wire S_AXIS_DIN_WORDS_ACLK_delay; + wire S_AXIS_DIN_WORDS_TLAST_delay; + wire S_AXIS_DIN_WORDS_TVALID_delay; + wire S_AXIS_DOUT_WORDS_ACLK_delay; + wire S_AXIS_DOUT_WORDS_TLAST_delay; + wire S_AXIS_DOUT_WORDS_TVALID_delay; + wire S_AXI_ACLK_delay; + wire S_AXI_ARVALID_delay; + wire S_AXI_AWVALID_delay; + wire S_AXI_BREADY_delay; + wire S_AXI_RREADY_delay; + wire S_AXI_WVALID_delay; + wire [17:0] S_AXI_ARADDR_delay; + wire [17:0] S_AXI_AWADDR_delay; + wire [31:0] S_AXIS_CTRL_TDATA_delay; + wire [31:0] S_AXIS_DIN_WORDS_TDATA_delay; + wire [31:0] S_AXIS_DOUT_WORDS_TDATA_delay; + wire [31:0] S_AXI_WDATA_delay; + wire [511:0] S_AXIS_DIN_TDATA_delay; +`endif + + assign DEBUG_DOUT = DEBUG_DOUT_out; + assign DEBUG_PHASE = DEBUG_PHASE_out; + assign INTERRUPT = INTERRUPT_out; + assign M_AXIS_DOUT_TDATA = M_AXIS_DOUT_TDATA_out; + assign M_AXIS_DOUT_TLAST = M_AXIS_DOUT_TLAST_out; + assign M_AXIS_DOUT_TVALID = M_AXIS_DOUT_TVALID_out; + assign M_AXIS_STATUS_TDATA = M_AXIS_STATUS_TDATA_out; + assign M_AXIS_STATUS_TVALID = M_AXIS_STATUS_TVALID_out; + assign SPARE_OUT = SPARE_OUT_out; + assign S_AXIS_CTRL_TREADY = S_AXIS_CTRL_TREADY_out; + assign S_AXIS_DIN_TREADY = S_AXIS_DIN_TREADY_out; + assign S_AXIS_DIN_WORDS_TREADY = S_AXIS_DIN_WORDS_TREADY_out; + assign S_AXIS_DOUT_WORDS_TREADY = S_AXIS_DOUT_WORDS_TREADY_out; + assign S_AXI_ARREADY = S_AXI_ARREADY_out; + assign S_AXI_AWREADY = S_AXI_AWREADY_out; + assign S_AXI_BVALID = S_AXI_BVALID_out; + assign S_AXI_RDATA = S_AXI_RDATA_out; + assign S_AXI_RVALID = S_AXI_RVALID_out; + assign S_AXI_WREADY = S_AXI_WREADY_out; + +`ifdef XIL_TIMING + assign CORE_CLK_in = (CORE_CLK !== 1'bz) && CORE_CLK_delay; // rv 0 + assign DEBUG_EN_in = (DEBUG_EN === 1'bz) || DEBUG_EN_delay; // rv 1 + assign M_AXIS_DOUT_ACLK_in = (M_AXIS_DOUT_ACLK !== 1'bz) && M_AXIS_DOUT_ACLK_delay; // rv 0 + assign M_AXIS_DOUT_TREADY_in = (M_AXIS_DOUT_TREADY !== 1'bz) && M_AXIS_DOUT_TREADY_delay; // rv 0 + assign M_AXIS_STATUS_ACLK_in = (M_AXIS_STATUS_ACLK !== 1'bz) && M_AXIS_STATUS_ACLK_delay; // rv 0 + assign M_AXIS_STATUS_TREADY_in = (M_AXIS_STATUS_TREADY !== 1'bz) && M_AXIS_STATUS_TREADY_delay; // rv 0 + assign S_AXIS_CTRL_ACLK_in = (S_AXIS_CTRL_ACLK !== 1'bz) && S_AXIS_CTRL_ACLK_delay; // rv 0 + assign S_AXIS_CTRL_TDATA_in[0] = (S_AXIS_CTRL_TDATA[0] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[0]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[10] = (S_AXIS_CTRL_TDATA[10] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[10]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[11] = (S_AXIS_CTRL_TDATA[11] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[11]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[12] = (S_AXIS_CTRL_TDATA[12] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[12]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[13] = (S_AXIS_CTRL_TDATA[13] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[13]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[14] = (S_AXIS_CTRL_TDATA[14] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[14]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[15] = (S_AXIS_CTRL_TDATA[15] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[15]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[16] = (S_AXIS_CTRL_TDATA[16] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[16]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[17] = (S_AXIS_CTRL_TDATA[17] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[17]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[18] = (S_AXIS_CTRL_TDATA[18] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[18]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[19] = (S_AXIS_CTRL_TDATA[19] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[19]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[1] = (S_AXIS_CTRL_TDATA[1] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[1]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[20] = (S_AXIS_CTRL_TDATA[20] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[20]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[21] = (S_AXIS_CTRL_TDATA[21] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[21]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[22] = (S_AXIS_CTRL_TDATA[22] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[22]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[23] = (S_AXIS_CTRL_TDATA[23] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[23]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[24] = (S_AXIS_CTRL_TDATA[24] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[24]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[25] = (S_AXIS_CTRL_TDATA[25] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[25]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[26] = (S_AXIS_CTRL_TDATA[26] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[26]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[27] = (S_AXIS_CTRL_TDATA[27] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[27]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[28] = (S_AXIS_CTRL_TDATA[28] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[28]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[29] = (S_AXIS_CTRL_TDATA[29] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[29]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[2] = (S_AXIS_CTRL_TDATA[2] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[2]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[30] = (S_AXIS_CTRL_TDATA[30] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[30]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[31] = (S_AXIS_CTRL_TDATA[31] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[31]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[3] = (S_AXIS_CTRL_TDATA[3] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[3]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[4] = (S_AXIS_CTRL_TDATA[4] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[4]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[5] = (S_AXIS_CTRL_TDATA[5] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[5]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[6] = (S_AXIS_CTRL_TDATA[6] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[6]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[7] = (S_AXIS_CTRL_TDATA[7] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[7]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[8] = (S_AXIS_CTRL_TDATA[8] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[8]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[9] = (S_AXIS_CTRL_TDATA[9] !== 1'bz) && S_AXIS_CTRL_TDATA_delay[9]; // rv 0 + assign S_AXIS_CTRL_TVALID_in = (S_AXIS_CTRL_TVALID !== 1'bz) && S_AXIS_CTRL_TVALID_delay; // rv 0 + assign S_AXIS_DIN_ACLK_in = (S_AXIS_DIN_ACLK !== 1'bz) && S_AXIS_DIN_ACLK_delay; // rv 0 + assign S_AXIS_DIN_TDATA_in[0] = (S_AXIS_DIN_TDATA[0] !== 1'bz) && S_AXIS_DIN_TDATA_delay[0]; // rv 0 + assign S_AXIS_DIN_TDATA_in[100] = (S_AXIS_DIN_TDATA[100] !== 1'bz) && S_AXIS_DIN_TDATA_delay[100]; // rv 0 + assign S_AXIS_DIN_TDATA_in[101] = (S_AXIS_DIN_TDATA[101] !== 1'bz) && S_AXIS_DIN_TDATA_delay[101]; // rv 0 + assign S_AXIS_DIN_TDATA_in[102] = (S_AXIS_DIN_TDATA[102] !== 1'bz) && S_AXIS_DIN_TDATA_delay[102]; // rv 0 + assign S_AXIS_DIN_TDATA_in[103] = (S_AXIS_DIN_TDATA[103] !== 1'bz) && S_AXIS_DIN_TDATA_delay[103]; // rv 0 + assign S_AXIS_DIN_TDATA_in[104] = (S_AXIS_DIN_TDATA[104] !== 1'bz) && S_AXIS_DIN_TDATA_delay[104]; // rv 0 + assign S_AXIS_DIN_TDATA_in[105] = (S_AXIS_DIN_TDATA[105] !== 1'bz) && S_AXIS_DIN_TDATA_delay[105]; // rv 0 + assign S_AXIS_DIN_TDATA_in[106] = (S_AXIS_DIN_TDATA[106] !== 1'bz) && S_AXIS_DIN_TDATA_delay[106]; // rv 0 + assign S_AXIS_DIN_TDATA_in[107] = (S_AXIS_DIN_TDATA[107] !== 1'bz) && S_AXIS_DIN_TDATA_delay[107]; // rv 0 + assign S_AXIS_DIN_TDATA_in[108] = (S_AXIS_DIN_TDATA[108] !== 1'bz) && S_AXIS_DIN_TDATA_delay[108]; // rv 0 + assign S_AXIS_DIN_TDATA_in[109] = (S_AXIS_DIN_TDATA[109] !== 1'bz) && S_AXIS_DIN_TDATA_delay[109]; // rv 0 + assign S_AXIS_DIN_TDATA_in[10] = (S_AXIS_DIN_TDATA[10] !== 1'bz) && S_AXIS_DIN_TDATA_delay[10]; // rv 0 + assign S_AXIS_DIN_TDATA_in[110] = (S_AXIS_DIN_TDATA[110] !== 1'bz) && S_AXIS_DIN_TDATA_delay[110]; // rv 0 + assign S_AXIS_DIN_TDATA_in[111] = (S_AXIS_DIN_TDATA[111] !== 1'bz) && S_AXIS_DIN_TDATA_delay[111]; // rv 0 + assign S_AXIS_DIN_TDATA_in[112] = (S_AXIS_DIN_TDATA[112] !== 1'bz) && S_AXIS_DIN_TDATA_delay[112]; // rv 0 + assign S_AXIS_DIN_TDATA_in[113] = (S_AXIS_DIN_TDATA[113] !== 1'bz) && S_AXIS_DIN_TDATA_delay[113]; // rv 0 + assign S_AXIS_DIN_TDATA_in[114] = (S_AXIS_DIN_TDATA[114] !== 1'bz) && S_AXIS_DIN_TDATA_delay[114]; // rv 0 + assign S_AXIS_DIN_TDATA_in[115] = (S_AXIS_DIN_TDATA[115] !== 1'bz) && S_AXIS_DIN_TDATA_delay[115]; // rv 0 + assign S_AXIS_DIN_TDATA_in[116] = (S_AXIS_DIN_TDATA[116] !== 1'bz) && S_AXIS_DIN_TDATA_delay[116]; // rv 0 + assign S_AXIS_DIN_TDATA_in[117] = (S_AXIS_DIN_TDATA[117] !== 1'bz) && S_AXIS_DIN_TDATA_delay[117]; // rv 0 + assign S_AXIS_DIN_TDATA_in[118] = (S_AXIS_DIN_TDATA[118] !== 1'bz) && S_AXIS_DIN_TDATA_delay[118]; // rv 0 + assign S_AXIS_DIN_TDATA_in[119] = (S_AXIS_DIN_TDATA[119] !== 1'bz) && S_AXIS_DIN_TDATA_delay[119]; // rv 0 + assign S_AXIS_DIN_TDATA_in[11] = (S_AXIS_DIN_TDATA[11] !== 1'bz) && S_AXIS_DIN_TDATA_delay[11]; // rv 0 + assign S_AXIS_DIN_TDATA_in[120] = (S_AXIS_DIN_TDATA[120] !== 1'bz) && S_AXIS_DIN_TDATA_delay[120]; // rv 0 + assign S_AXIS_DIN_TDATA_in[121] = (S_AXIS_DIN_TDATA[121] !== 1'bz) && S_AXIS_DIN_TDATA_delay[121]; // rv 0 + assign S_AXIS_DIN_TDATA_in[122] = (S_AXIS_DIN_TDATA[122] !== 1'bz) && S_AXIS_DIN_TDATA_delay[122]; // rv 0 + assign S_AXIS_DIN_TDATA_in[123] = (S_AXIS_DIN_TDATA[123] !== 1'bz) && S_AXIS_DIN_TDATA_delay[123]; // rv 0 + assign S_AXIS_DIN_TDATA_in[124] = (S_AXIS_DIN_TDATA[124] !== 1'bz) && S_AXIS_DIN_TDATA_delay[124]; // rv 0 + assign S_AXIS_DIN_TDATA_in[125] = (S_AXIS_DIN_TDATA[125] !== 1'bz) && S_AXIS_DIN_TDATA_delay[125]; // rv 0 + assign S_AXIS_DIN_TDATA_in[126] = (S_AXIS_DIN_TDATA[126] !== 1'bz) && S_AXIS_DIN_TDATA_delay[126]; // rv 0 + assign S_AXIS_DIN_TDATA_in[127] = (S_AXIS_DIN_TDATA[127] !== 1'bz) && S_AXIS_DIN_TDATA_delay[127]; // rv 0 + assign S_AXIS_DIN_TDATA_in[128] = (S_AXIS_DIN_TDATA[128] !== 1'bz) && S_AXIS_DIN_TDATA_delay[128]; // rv 0 + assign S_AXIS_DIN_TDATA_in[129] = (S_AXIS_DIN_TDATA[129] !== 1'bz) && S_AXIS_DIN_TDATA_delay[129]; // rv 0 + assign S_AXIS_DIN_TDATA_in[12] = (S_AXIS_DIN_TDATA[12] !== 1'bz) && S_AXIS_DIN_TDATA_delay[12]; // rv 0 + assign S_AXIS_DIN_TDATA_in[130] = (S_AXIS_DIN_TDATA[130] !== 1'bz) && S_AXIS_DIN_TDATA_delay[130]; // rv 0 + assign S_AXIS_DIN_TDATA_in[131] = (S_AXIS_DIN_TDATA[131] !== 1'bz) && S_AXIS_DIN_TDATA_delay[131]; // rv 0 + assign S_AXIS_DIN_TDATA_in[132] = (S_AXIS_DIN_TDATA[132] !== 1'bz) && S_AXIS_DIN_TDATA_delay[132]; // rv 0 + assign S_AXIS_DIN_TDATA_in[133] = (S_AXIS_DIN_TDATA[133] !== 1'bz) && S_AXIS_DIN_TDATA_delay[133]; // rv 0 + assign S_AXIS_DIN_TDATA_in[134] = (S_AXIS_DIN_TDATA[134] !== 1'bz) && S_AXIS_DIN_TDATA_delay[134]; // rv 0 + assign S_AXIS_DIN_TDATA_in[135] = (S_AXIS_DIN_TDATA[135] !== 1'bz) && S_AXIS_DIN_TDATA_delay[135]; // rv 0 + assign S_AXIS_DIN_TDATA_in[136] = (S_AXIS_DIN_TDATA[136] !== 1'bz) && S_AXIS_DIN_TDATA_delay[136]; // rv 0 + assign S_AXIS_DIN_TDATA_in[137] = (S_AXIS_DIN_TDATA[137] !== 1'bz) && S_AXIS_DIN_TDATA_delay[137]; // rv 0 + assign S_AXIS_DIN_TDATA_in[138] = (S_AXIS_DIN_TDATA[138] !== 1'bz) && S_AXIS_DIN_TDATA_delay[138]; // rv 0 + assign S_AXIS_DIN_TDATA_in[139] = (S_AXIS_DIN_TDATA[139] !== 1'bz) && S_AXIS_DIN_TDATA_delay[139]; // rv 0 + assign S_AXIS_DIN_TDATA_in[13] = (S_AXIS_DIN_TDATA[13] !== 1'bz) && S_AXIS_DIN_TDATA_delay[13]; // rv 0 + assign S_AXIS_DIN_TDATA_in[140] = (S_AXIS_DIN_TDATA[140] !== 1'bz) && S_AXIS_DIN_TDATA_delay[140]; // rv 0 + assign S_AXIS_DIN_TDATA_in[141] = (S_AXIS_DIN_TDATA[141] !== 1'bz) && S_AXIS_DIN_TDATA_delay[141]; // rv 0 + assign S_AXIS_DIN_TDATA_in[142] = (S_AXIS_DIN_TDATA[142] !== 1'bz) && S_AXIS_DIN_TDATA_delay[142]; // rv 0 + assign S_AXIS_DIN_TDATA_in[143] = (S_AXIS_DIN_TDATA[143] !== 1'bz) && S_AXIS_DIN_TDATA_delay[143]; // rv 0 + assign S_AXIS_DIN_TDATA_in[144] = (S_AXIS_DIN_TDATA[144] !== 1'bz) && S_AXIS_DIN_TDATA_delay[144]; // rv 0 + assign S_AXIS_DIN_TDATA_in[145] = (S_AXIS_DIN_TDATA[145] !== 1'bz) && S_AXIS_DIN_TDATA_delay[145]; // rv 0 + assign S_AXIS_DIN_TDATA_in[146] = (S_AXIS_DIN_TDATA[146] !== 1'bz) && S_AXIS_DIN_TDATA_delay[146]; // rv 0 + assign S_AXIS_DIN_TDATA_in[147] = (S_AXIS_DIN_TDATA[147] !== 1'bz) && S_AXIS_DIN_TDATA_delay[147]; // rv 0 + assign S_AXIS_DIN_TDATA_in[148] = (S_AXIS_DIN_TDATA[148] !== 1'bz) && S_AXIS_DIN_TDATA_delay[148]; // rv 0 + assign S_AXIS_DIN_TDATA_in[149] = (S_AXIS_DIN_TDATA[149] !== 1'bz) && S_AXIS_DIN_TDATA_delay[149]; // rv 0 + assign S_AXIS_DIN_TDATA_in[14] = (S_AXIS_DIN_TDATA[14] !== 1'bz) && S_AXIS_DIN_TDATA_delay[14]; // rv 0 + assign S_AXIS_DIN_TDATA_in[150] = (S_AXIS_DIN_TDATA[150] !== 1'bz) && S_AXIS_DIN_TDATA_delay[150]; // rv 0 + assign S_AXIS_DIN_TDATA_in[151] = (S_AXIS_DIN_TDATA[151] !== 1'bz) && S_AXIS_DIN_TDATA_delay[151]; // rv 0 + assign S_AXIS_DIN_TDATA_in[152] = (S_AXIS_DIN_TDATA[152] !== 1'bz) && S_AXIS_DIN_TDATA_delay[152]; // rv 0 + assign S_AXIS_DIN_TDATA_in[153] = (S_AXIS_DIN_TDATA[153] !== 1'bz) && S_AXIS_DIN_TDATA_delay[153]; // rv 0 + assign S_AXIS_DIN_TDATA_in[154] = (S_AXIS_DIN_TDATA[154] !== 1'bz) && S_AXIS_DIN_TDATA_delay[154]; // rv 0 + assign S_AXIS_DIN_TDATA_in[155] = (S_AXIS_DIN_TDATA[155] !== 1'bz) && S_AXIS_DIN_TDATA_delay[155]; // rv 0 + assign S_AXIS_DIN_TDATA_in[156] = (S_AXIS_DIN_TDATA[156] !== 1'bz) && S_AXIS_DIN_TDATA_delay[156]; // rv 0 + assign S_AXIS_DIN_TDATA_in[157] = (S_AXIS_DIN_TDATA[157] !== 1'bz) && S_AXIS_DIN_TDATA_delay[157]; // rv 0 + assign S_AXIS_DIN_TDATA_in[158] = (S_AXIS_DIN_TDATA[158] !== 1'bz) && S_AXIS_DIN_TDATA_delay[158]; // rv 0 + assign S_AXIS_DIN_TDATA_in[159] = (S_AXIS_DIN_TDATA[159] !== 1'bz) && S_AXIS_DIN_TDATA_delay[159]; // rv 0 + assign S_AXIS_DIN_TDATA_in[15] = (S_AXIS_DIN_TDATA[15] !== 1'bz) && S_AXIS_DIN_TDATA_delay[15]; // rv 0 + assign S_AXIS_DIN_TDATA_in[160] = (S_AXIS_DIN_TDATA[160] !== 1'bz) && S_AXIS_DIN_TDATA_delay[160]; // rv 0 + assign S_AXIS_DIN_TDATA_in[161] = (S_AXIS_DIN_TDATA[161] !== 1'bz) && S_AXIS_DIN_TDATA_delay[161]; // rv 0 + assign S_AXIS_DIN_TDATA_in[162] = (S_AXIS_DIN_TDATA[162] !== 1'bz) && S_AXIS_DIN_TDATA_delay[162]; // rv 0 + assign S_AXIS_DIN_TDATA_in[163] = (S_AXIS_DIN_TDATA[163] !== 1'bz) && S_AXIS_DIN_TDATA_delay[163]; // rv 0 + assign S_AXIS_DIN_TDATA_in[164] = (S_AXIS_DIN_TDATA[164] !== 1'bz) && S_AXIS_DIN_TDATA_delay[164]; // rv 0 + assign S_AXIS_DIN_TDATA_in[165] = (S_AXIS_DIN_TDATA[165] !== 1'bz) && S_AXIS_DIN_TDATA_delay[165]; // rv 0 + assign S_AXIS_DIN_TDATA_in[166] = (S_AXIS_DIN_TDATA[166] !== 1'bz) && S_AXIS_DIN_TDATA_delay[166]; // rv 0 + assign S_AXIS_DIN_TDATA_in[167] = (S_AXIS_DIN_TDATA[167] !== 1'bz) && S_AXIS_DIN_TDATA_delay[167]; // rv 0 + assign S_AXIS_DIN_TDATA_in[168] = (S_AXIS_DIN_TDATA[168] !== 1'bz) && S_AXIS_DIN_TDATA_delay[168]; // rv 0 + assign S_AXIS_DIN_TDATA_in[169] = (S_AXIS_DIN_TDATA[169] !== 1'bz) && S_AXIS_DIN_TDATA_delay[169]; // rv 0 + assign S_AXIS_DIN_TDATA_in[16] = (S_AXIS_DIN_TDATA[16] !== 1'bz) && S_AXIS_DIN_TDATA_delay[16]; // rv 0 + assign S_AXIS_DIN_TDATA_in[170] = (S_AXIS_DIN_TDATA[170] !== 1'bz) && S_AXIS_DIN_TDATA_delay[170]; // rv 0 + assign S_AXIS_DIN_TDATA_in[171] = (S_AXIS_DIN_TDATA[171] !== 1'bz) && S_AXIS_DIN_TDATA_delay[171]; // rv 0 + assign S_AXIS_DIN_TDATA_in[172] = (S_AXIS_DIN_TDATA[172] !== 1'bz) && S_AXIS_DIN_TDATA_delay[172]; // rv 0 + assign S_AXIS_DIN_TDATA_in[173] = (S_AXIS_DIN_TDATA[173] !== 1'bz) && S_AXIS_DIN_TDATA_delay[173]; // rv 0 + assign S_AXIS_DIN_TDATA_in[174] = (S_AXIS_DIN_TDATA[174] !== 1'bz) && S_AXIS_DIN_TDATA_delay[174]; // rv 0 + assign S_AXIS_DIN_TDATA_in[175] = (S_AXIS_DIN_TDATA[175] !== 1'bz) && S_AXIS_DIN_TDATA_delay[175]; // rv 0 + assign S_AXIS_DIN_TDATA_in[176] = (S_AXIS_DIN_TDATA[176] !== 1'bz) && S_AXIS_DIN_TDATA_delay[176]; // rv 0 + assign S_AXIS_DIN_TDATA_in[177] = (S_AXIS_DIN_TDATA[177] !== 1'bz) && S_AXIS_DIN_TDATA_delay[177]; // rv 0 + assign S_AXIS_DIN_TDATA_in[178] = (S_AXIS_DIN_TDATA[178] !== 1'bz) && S_AXIS_DIN_TDATA_delay[178]; // rv 0 + assign S_AXIS_DIN_TDATA_in[179] = (S_AXIS_DIN_TDATA[179] !== 1'bz) && S_AXIS_DIN_TDATA_delay[179]; // rv 0 + assign S_AXIS_DIN_TDATA_in[17] = (S_AXIS_DIN_TDATA[17] !== 1'bz) && S_AXIS_DIN_TDATA_delay[17]; // rv 0 + assign S_AXIS_DIN_TDATA_in[180] = (S_AXIS_DIN_TDATA[180] !== 1'bz) && S_AXIS_DIN_TDATA_delay[180]; // rv 0 + assign S_AXIS_DIN_TDATA_in[181] = (S_AXIS_DIN_TDATA[181] !== 1'bz) && S_AXIS_DIN_TDATA_delay[181]; // rv 0 + assign S_AXIS_DIN_TDATA_in[182] = (S_AXIS_DIN_TDATA[182] !== 1'bz) && S_AXIS_DIN_TDATA_delay[182]; // rv 0 + assign S_AXIS_DIN_TDATA_in[183] = (S_AXIS_DIN_TDATA[183] !== 1'bz) && S_AXIS_DIN_TDATA_delay[183]; // rv 0 + assign S_AXIS_DIN_TDATA_in[184] = (S_AXIS_DIN_TDATA[184] !== 1'bz) && S_AXIS_DIN_TDATA_delay[184]; // rv 0 + assign S_AXIS_DIN_TDATA_in[185] = (S_AXIS_DIN_TDATA[185] !== 1'bz) && S_AXIS_DIN_TDATA_delay[185]; // rv 0 + assign S_AXIS_DIN_TDATA_in[186] = (S_AXIS_DIN_TDATA[186] !== 1'bz) && S_AXIS_DIN_TDATA_delay[186]; // rv 0 + assign S_AXIS_DIN_TDATA_in[187] = (S_AXIS_DIN_TDATA[187] !== 1'bz) && S_AXIS_DIN_TDATA_delay[187]; // rv 0 + assign S_AXIS_DIN_TDATA_in[188] = (S_AXIS_DIN_TDATA[188] !== 1'bz) && S_AXIS_DIN_TDATA_delay[188]; // rv 0 + assign S_AXIS_DIN_TDATA_in[189] = (S_AXIS_DIN_TDATA[189] !== 1'bz) && S_AXIS_DIN_TDATA_delay[189]; // rv 0 + assign S_AXIS_DIN_TDATA_in[18] = (S_AXIS_DIN_TDATA[18] !== 1'bz) && S_AXIS_DIN_TDATA_delay[18]; // rv 0 + assign S_AXIS_DIN_TDATA_in[190] = (S_AXIS_DIN_TDATA[190] !== 1'bz) && S_AXIS_DIN_TDATA_delay[190]; // rv 0 + assign S_AXIS_DIN_TDATA_in[191] = (S_AXIS_DIN_TDATA[191] !== 1'bz) && S_AXIS_DIN_TDATA_delay[191]; // rv 0 + assign S_AXIS_DIN_TDATA_in[192] = (S_AXIS_DIN_TDATA[192] !== 1'bz) && S_AXIS_DIN_TDATA_delay[192]; // rv 0 + assign S_AXIS_DIN_TDATA_in[193] = (S_AXIS_DIN_TDATA[193] !== 1'bz) && S_AXIS_DIN_TDATA_delay[193]; // rv 0 + assign S_AXIS_DIN_TDATA_in[194] = (S_AXIS_DIN_TDATA[194] !== 1'bz) && S_AXIS_DIN_TDATA_delay[194]; // rv 0 + assign S_AXIS_DIN_TDATA_in[195] = (S_AXIS_DIN_TDATA[195] !== 1'bz) && S_AXIS_DIN_TDATA_delay[195]; // rv 0 + assign S_AXIS_DIN_TDATA_in[196] = (S_AXIS_DIN_TDATA[196] !== 1'bz) && S_AXIS_DIN_TDATA_delay[196]; // rv 0 + assign S_AXIS_DIN_TDATA_in[197] = (S_AXIS_DIN_TDATA[197] !== 1'bz) && S_AXIS_DIN_TDATA_delay[197]; // rv 0 + assign S_AXIS_DIN_TDATA_in[198] = (S_AXIS_DIN_TDATA[198] !== 1'bz) && S_AXIS_DIN_TDATA_delay[198]; // rv 0 + assign S_AXIS_DIN_TDATA_in[199] = (S_AXIS_DIN_TDATA[199] !== 1'bz) && S_AXIS_DIN_TDATA_delay[199]; // rv 0 + assign S_AXIS_DIN_TDATA_in[19] = (S_AXIS_DIN_TDATA[19] !== 1'bz) && S_AXIS_DIN_TDATA_delay[19]; // rv 0 + assign S_AXIS_DIN_TDATA_in[1] = (S_AXIS_DIN_TDATA[1] !== 1'bz) && S_AXIS_DIN_TDATA_delay[1]; // rv 0 + assign S_AXIS_DIN_TDATA_in[200] = (S_AXIS_DIN_TDATA[200] !== 1'bz) && S_AXIS_DIN_TDATA_delay[200]; // rv 0 + assign S_AXIS_DIN_TDATA_in[201] = (S_AXIS_DIN_TDATA[201] !== 1'bz) && S_AXIS_DIN_TDATA_delay[201]; // rv 0 + assign S_AXIS_DIN_TDATA_in[202] = (S_AXIS_DIN_TDATA[202] !== 1'bz) && S_AXIS_DIN_TDATA_delay[202]; // rv 0 + assign S_AXIS_DIN_TDATA_in[203] = (S_AXIS_DIN_TDATA[203] !== 1'bz) && S_AXIS_DIN_TDATA_delay[203]; // rv 0 + assign S_AXIS_DIN_TDATA_in[204] = (S_AXIS_DIN_TDATA[204] !== 1'bz) && S_AXIS_DIN_TDATA_delay[204]; // rv 0 + assign S_AXIS_DIN_TDATA_in[205] = (S_AXIS_DIN_TDATA[205] !== 1'bz) && S_AXIS_DIN_TDATA_delay[205]; // rv 0 + assign S_AXIS_DIN_TDATA_in[206] = (S_AXIS_DIN_TDATA[206] !== 1'bz) && S_AXIS_DIN_TDATA_delay[206]; // rv 0 + assign S_AXIS_DIN_TDATA_in[207] = (S_AXIS_DIN_TDATA[207] !== 1'bz) && S_AXIS_DIN_TDATA_delay[207]; // rv 0 + assign S_AXIS_DIN_TDATA_in[208] = (S_AXIS_DIN_TDATA[208] !== 1'bz) && S_AXIS_DIN_TDATA_delay[208]; // rv 0 + assign S_AXIS_DIN_TDATA_in[209] = (S_AXIS_DIN_TDATA[209] !== 1'bz) && S_AXIS_DIN_TDATA_delay[209]; // rv 0 + assign S_AXIS_DIN_TDATA_in[20] = (S_AXIS_DIN_TDATA[20] !== 1'bz) && S_AXIS_DIN_TDATA_delay[20]; // rv 0 + assign S_AXIS_DIN_TDATA_in[210] = (S_AXIS_DIN_TDATA[210] !== 1'bz) && S_AXIS_DIN_TDATA_delay[210]; // rv 0 + assign S_AXIS_DIN_TDATA_in[211] = (S_AXIS_DIN_TDATA[211] !== 1'bz) && S_AXIS_DIN_TDATA_delay[211]; // rv 0 + assign S_AXIS_DIN_TDATA_in[212] = (S_AXIS_DIN_TDATA[212] !== 1'bz) && S_AXIS_DIN_TDATA_delay[212]; // rv 0 + assign S_AXIS_DIN_TDATA_in[213] = (S_AXIS_DIN_TDATA[213] !== 1'bz) && S_AXIS_DIN_TDATA_delay[213]; // rv 0 + assign S_AXIS_DIN_TDATA_in[214] = (S_AXIS_DIN_TDATA[214] !== 1'bz) && S_AXIS_DIN_TDATA_delay[214]; // rv 0 + assign S_AXIS_DIN_TDATA_in[215] = (S_AXIS_DIN_TDATA[215] !== 1'bz) && S_AXIS_DIN_TDATA_delay[215]; // rv 0 + assign S_AXIS_DIN_TDATA_in[216] = (S_AXIS_DIN_TDATA[216] !== 1'bz) && S_AXIS_DIN_TDATA_delay[216]; // rv 0 + assign S_AXIS_DIN_TDATA_in[217] = (S_AXIS_DIN_TDATA[217] !== 1'bz) && S_AXIS_DIN_TDATA_delay[217]; // rv 0 + assign S_AXIS_DIN_TDATA_in[218] = (S_AXIS_DIN_TDATA[218] !== 1'bz) && S_AXIS_DIN_TDATA_delay[218]; // rv 0 + assign S_AXIS_DIN_TDATA_in[219] = (S_AXIS_DIN_TDATA[219] !== 1'bz) && S_AXIS_DIN_TDATA_delay[219]; // rv 0 + assign S_AXIS_DIN_TDATA_in[21] = (S_AXIS_DIN_TDATA[21] !== 1'bz) && S_AXIS_DIN_TDATA_delay[21]; // rv 0 + assign S_AXIS_DIN_TDATA_in[220] = (S_AXIS_DIN_TDATA[220] !== 1'bz) && S_AXIS_DIN_TDATA_delay[220]; // rv 0 + assign S_AXIS_DIN_TDATA_in[221] = (S_AXIS_DIN_TDATA[221] !== 1'bz) && S_AXIS_DIN_TDATA_delay[221]; // rv 0 + assign S_AXIS_DIN_TDATA_in[222] = (S_AXIS_DIN_TDATA[222] !== 1'bz) && S_AXIS_DIN_TDATA_delay[222]; // rv 0 + assign S_AXIS_DIN_TDATA_in[223] = (S_AXIS_DIN_TDATA[223] !== 1'bz) && S_AXIS_DIN_TDATA_delay[223]; // rv 0 + assign S_AXIS_DIN_TDATA_in[224] = (S_AXIS_DIN_TDATA[224] !== 1'bz) && S_AXIS_DIN_TDATA_delay[224]; // rv 0 + assign S_AXIS_DIN_TDATA_in[225] = (S_AXIS_DIN_TDATA[225] !== 1'bz) && S_AXIS_DIN_TDATA_delay[225]; // rv 0 + assign S_AXIS_DIN_TDATA_in[226] = (S_AXIS_DIN_TDATA[226] !== 1'bz) && S_AXIS_DIN_TDATA_delay[226]; // rv 0 + assign S_AXIS_DIN_TDATA_in[227] = (S_AXIS_DIN_TDATA[227] !== 1'bz) && S_AXIS_DIN_TDATA_delay[227]; // rv 0 + assign S_AXIS_DIN_TDATA_in[228] = (S_AXIS_DIN_TDATA[228] !== 1'bz) && S_AXIS_DIN_TDATA_delay[228]; // rv 0 + assign S_AXIS_DIN_TDATA_in[229] = (S_AXIS_DIN_TDATA[229] !== 1'bz) && S_AXIS_DIN_TDATA_delay[229]; // rv 0 + assign S_AXIS_DIN_TDATA_in[22] = (S_AXIS_DIN_TDATA[22] !== 1'bz) && S_AXIS_DIN_TDATA_delay[22]; // rv 0 + assign S_AXIS_DIN_TDATA_in[230] = (S_AXIS_DIN_TDATA[230] !== 1'bz) && S_AXIS_DIN_TDATA_delay[230]; // rv 0 + assign S_AXIS_DIN_TDATA_in[231] = (S_AXIS_DIN_TDATA[231] !== 1'bz) && S_AXIS_DIN_TDATA_delay[231]; // rv 0 + assign S_AXIS_DIN_TDATA_in[232] = (S_AXIS_DIN_TDATA[232] !== 1'bz) && S_AXIS_DIN_TDATA_delay[232]; // rv 0 + assign S_AXIS_DIN_TDATA_in[233] = (S_AXIS_DIN_TDATA[233] !== 1'bz) && S_AXIS_DIN_TDATA_delay[233]; // rv 0 + assign S_AXIS_DIN_TDATA_in[234] = (S_AXIS_DIN_TDATA[234] !== 1'bz) && S_AXIS_DIN_TDATA_delay[234]; // rv 0 + assign S_AXIS_DIN_TDATA_in[235] = (S_AXIS_DIN_TDATA[235] !== 1'bz) && S_AXIS_DIN_TDATA_delay[235]; // rv 0 + assign S_AXIS_DIN_TDATA_in[236] = (S_AXIS_DIN_TDATA[236] !== 1'bz) && S_AXIS_DIN_TDATA_delay[236]; // rv 0 + assign S_AXIS_DIN_TDATA_in[237] = (S_AXIS_DIN_TDATA[237] !== 1'bz) && S_AXIS_DIN_TDATA_delay[237]; // rv 0 + assign S_AXIS_DIN_TDATA_in[238] = (S_AXIS_DIN_TDATA[238] !== 1'bz) && S_AXIS_DIN_TDATA_delay[238]; // rv 0 + assign S_AXIS_DIN_TDATA_in[239] = (S_AXIS_DIN_TDATA[239] !== 1'bz) && S_AXIS_DIN_TDATA_delay[239]; // rv 0 + assign S_AXIS_DIN_TDATA_in[23] = (S_AXIS_DIN_TDATA[23] !== 1'bz) && S_AXIS_DIN_TDATA_delay[23]; // rv 0 + assign S_AXIS_DIN_TDATA_in[240] = (S_AXIS_DIN_TDATA[240] !== 1'bz) && S_AXIS_DIN_TDATA_delay[240]; // rv 0 + assign S_AXIS_DIN_TDATA_in[241] = (S_AXIS_DIN_TDATA[241] !== 1'bz) && S_AXIS_DIN_TDATA_delay[241]; // rv 0 + assign S_AXIS_DIN_TDATA_in[242] = (S_AXIS_DIN_TDATA[242] !== 1'bz) && S_AXIS_DIN_TDATA_delay[242]; // rv 0 + assign S_AXIS_DIN_TDATA_in[243] = (S_AXIS_DIN_TDATA[243] !== 1'bz) && S_AXIS_DIN_TDATA_delay[243]; // rv 0 + assign S_AXIS_DIN_TDATA_in[244] = (S_AXIS_DIN_TDATA[244] !== 1'bz) && S_AXIS_DIN_TDATA_delay[244]; // rv 0 + assign S_AXIS_DIN_TDATA_in[245] = (S_AXIS_DIN_TDATA[245] !== 1'bz) && S_AXIS_DIN_TDATA_delay[245]; // rv 0 + assign S_AXIS_DIN_TDATA_in[246] = (S_AXIS_DIN_TDATA[246] !== 1'bz) && S_AXIS_DIN_TDATA_delay[246]; // rv 0 + assign S_AXIS_DIN_TDATA_in[247] = (S_AXIS_DIN_TDATA[247] !== 1'bz) && S_AXIS_DIN_TDATA_delay[247]; // rv 0 + assign S_AXIS_DIN_TDATA_in[248] = (S_AXIS_DIN_TDATA[248] !== 1'bz) && S_AXIS_DIN_TDATA_delay[248]; // rv 0 + assign S_AXIS_DIN_TDATA_in[249] = (S_AXIS_DIN_TDATA[249] !== 1'bz) && S_AXIS_DIN_TDATA_delay[249]; // rv 0 + assign S_AXIS_DIN_TDATA_in[24] = (S_AXIS_DIN_TDATA[24] !== 1'bz) && S_AXIS_DIN_TDATA_delay[24]; // rv 0 + assign S_AXIS_DIN_TDATA_in[250] = (S_AXIS_DIN_TDATA[250] !== 1'bz) && S_AXIS_DIN_TDATA_delay[250]; // rv 0 + assign S_AXIS_DIN_TDATA_in[251] = (S_AXIS_DIN_TDATA[251] !== 1'bz) && S_AXIS_DIN_TDATA_delay[251]; // rv 0 + assign S_AXIS_DIN_TDATA_in[252] = (S_AXIS_DIN_TDATA[252] !== 1'bz) && S_AXIS_DIN_TDATA_delay[252]; // rv 0 + assign S_AXIS_DIN_TDATA_in[253] = (S_AXIS_DIN_TDATA[253] !== 1'bz) && S_AXIS_DIN_TDATA_delay[253]; // rv 0 + assign S_AXIS_DIN_TDATA_in[254] = (S_AXIS_DIN_TDATA[254] !== 1'bz) && S_AXIS_DIN_TDATA_delay[254]; // rv 0 + assign S_AXIS_DIN_TDATA_in[255] = (S_AXIS_DIN_TDATA[255] !== 1'bz) && S_AXIS_DIN_TDATA_delay[255]; // rv 0 + assign S_AXIS_DIN_TDATA_in[256] = (S_AXIS_DIN_TDATA[256] !== 1'bz) && S_AXIS_DIN_TDATA_delay[256]; // rv 0 + assign S_AXIS_DIN_TDATA_in[257] = (S_AXIS_DIN_TDATA[257] !== 1'bz) && S_AXIS_DIN_TDATA_delay[257]; // rv 0 + assign S_AXIS_DIN_TDATA_in[258] = (S_AXIS_DIN_TDATA[258] !== 1'bz) && S_AXIS_DIN_TDATA_delay[258]; // rv 0 + assign S_AXIS_DIN_TDATA_in[259] = (S_AXIS_DIN_TDATA[259] !== 1'bz) && S_AXIS_DIN_TDATA_delay[259]; // rv 0 + assign S_AXIS_DIN_TDATA_in[25] = (S_AXIS_DIN_TDATA[25] !== 1'bz) && S_AXIS_DIN_TDATA_delay[25]; // rv 0 + assign S_AXIS_DIN_TDATA_in[260] = (S_AXIS_DIN_TDATA[260] !== 1'bz) && S_AXIS_DIN_TDATA_delay[260]; // rv 0 + assign S_AXIS_DIN_TDATA_in[261] = (S_AXIS_DIN_TDATA[261] !== 1'bz) && S_AXIS_DIN_TDATA_delay[261]; // rv 0 + assign S_AXIS_DIN_TDATA_in[262] = (S_AXIS_DIN_TDATA[262] !== 1'bz) && S_AXIS_DIN_TDATA_delay[262]; // rv 0 + assign S_AXIS_DIN_TDATA_in[263] = (S_AXIS_DIN_TDATA[263] !== 1'bz) && S_AXIS_DIN_TDATA_delay[263]; // rv 0 + assign S_AXIS_DIN_TDATA_in[264] = (S_AXIS_DIN_TDATA[264] !== 1'bz) && S_AXIS_DIN_TDATA_delay[264]; // rv 0 + assign S_AXIS_DIN_TDATA_in[265] = (S_AXIS_DIN_TDATA[265] !== 1'bz) && S_AXIS_DIN_TDATA_delay[265]; // rv 0 + assign S_AXIS_DIN_TDATA_in[266] = (S_AXIS_DIN_TDATA[266] !== 1'bz) && S_AXIS_DIN_TDATA_delay[266]; // rv 0 + assign S_AXIS_DIN_TDATA_in[267] = (S_AXIS_DIN_TDATA[267] !== 1'bz) && S_AXIS_DIN_TDATA_delay[267]; // rv 0 + assign S_AXIS_DIN_TDATA_in[268] = (S_AXIS_DIN_TDATA[268] !== 1'bz) && S_AXIS_DIN_TDATA_delay[268]; // rv 0 + assign S_AXIS_DIN_TDATA_in[269] = (S_AXIS_DIN_TDATA[269] !== 1'bz) && S_AXIS_DIN_TDATA_delay[269]; // rv 0 + assign S_AXIS_DIN_TDATA_in[26] = (S_AXIS_DIN_TDATA[26] !== 1'bz) && S_AXIS_DIN_TDATA_delay[26]; // rv 0 + assign S_AXIS_DIN_TDATA_in[270] = (S_AXIS_DIN_TDATA[270] !== 1'bz) && S_AXIS_DIN_TDATA_delay[270]; // rv 0 + assign S_AXIS_DIN_TDATA_in[271] = (S_AXIS_DIN_TDATA[271] !== 1'bz) && S_AXIS_DIN_TDATA_delay[271]; // rv 0 + assign S_AXIS_DIN_TDATA_in[272] = (S_AXIS_DIN_TDATA[272] !== 1'bz) && S_AXIS_DIN_TDATA_delay[272]; // rv 0 + assign S_AXIS_DIN_TDATA_in[273] = (S_AXIS_DIN_TDATA[273] !== 1'bz) && S_AXIS_DIN_TDATA_delay[273]; // rv 0 + assign S_AXIS_DIN_TDATA_in[274] = (S_AXIS_DIN_TDATA[274] !== 1'bz) && S_AXIS_DIN_TDATA_delay[274]; // rv 0 + assign S_AXIS_DIN_TDATA_in[275] = (S_AXIS_DIN_TDATA[275] !== 1'bz) && S_AXIS_DIN_TDATA_delay[275]; // rv 0 + assign S_AXIS_DIN_TDATA_in[276] = (S_AXIS_DIN_TDATA[276] !== 1'bz) && S_AXIS_DIN_TDATA_delay[276]; // rv 0 + assign S_AXIS_DIN_TDATA_in[277] = (S_AXIS_DIN_TDATA[277] !== 1'bz) && S_AXIS_DIN_TDATA_delay[277]; // rv 0 + assign S_AXIS_DIN_TDATA_in[278] = (S_AXIS_DIN_TDATA[278] !== 1'bz) && S_AXIS_DIN_TDATA_delay[278]; // rv 0 + assign S_AXIS_DIN_TDATA_in[279] = (S_AXIS_DIN_TDATA[279] !== 1'bz) && S_AXIS_DIN_TDATA_delay[279]; // rv 0 + assign S_AXIS_DIN_TDATA_in[27] = (S_AXIS_DIN_TDATA[27] !== 1'bz) && S_AXIS_DIN_TDATA_delay[27]; // rv 0 + assign S_AXIS_DIN_TDATA_in[280] = (S_AXIS_DIN_TDATA[280] !== 1'bz) && S_AXIS_DIN_TDATA_delay[280]; // rv 0 + assign S_AXIS_DIN_TDATA_in[281] = (S_AXIS_DIN_TDATA[281] !== 1'bz) && S_AXIS_DIN_TDATA_delay[281]; // rv 0 + assign S_AXIS_DIN_TDATA_in[282] = (S_AXIS_DIN_TDATA[282] !== 1'bz) && S_AXIS_DIN_TDATA_delay[282]; // rv 0 + assign S_AXIS_DIN_TDATA_in[283] = (S_AXIS_DIN_TDATA[283] !== 1'bz) && S_AXIS_DIN_TDATA_delay[283]; // rv 0 + assign S_AXIS_DIN_TDATA_in[284] = (S_AXIS_DIN_TDATA[284] !== 1'bz) && S_AXIS_DIN_TDATA_delay[284]; // rv 0 + assign S_AXIS_DIN_TDATA_in[285] = (S_AXIS_DIN_TDATA[285] !== 1'bz) && S_AXIS_DIN_TDATA_delay[285]; // rv 0 + assign S_AXIS_DIN_TDATA_in[286] = (S_AXIS_DIN_TDATA[286] !== 1'bz) && S_AXIS_DIN_TDATA_delay[286]; // rv 0 + assign S_AXIS_DIN_TDATA_in[287] = (S_AXIS_DIN_TDATA[287] !== 1'bz) && S_AXIS_DIN_TDATA_delay[287]; // rv 0 + assign S_AXIS_DIN_TDATA_in[288] = (S_AXIS_DIN_TDATA[288] !== 1'bz) && S_AXIS_DIN_TDATA_delay[288]; // rv 0 + assign S_AXIS_DIN_TDATA_in[289] = (S_AXIS_DIN_TDATA[289] !== 1'bz) && S_AXIS_DIN_TDATA_delay[289]; // rv 0 + assign S_AXIS_DIN_TDATA_in[28] = (S_AXIS_DIN_TDATA[28] !== 1'bz) && S_AXIS_DIN_TDATA_delay[28]; // rv 0 + assign S_AXIS_DIN_TDATA_in[290] = (S_AXIS_DIN_TDATA[290] !== 1'bz) && S_AXIS_DIN_TDATA_delay[290]; // rv 0 + assign S_AXIS_DIN_TDATA_in[291] = (S_AXIS_DIN_TDATA[291] !== 1'bz) && S_AXIS_DIN_TDATA_delay[291]; // rv 0 + assign S_AXIS_DIN_TDATA_in[292] = (S_AXIS_DIN_TDATA[292] !== 1'bz) && S_AXIS_DIN_TDATA_delay[292]; // rv 0 + assign S_AXIS_DIN_TDATA_in[293] = (S_AXIS_DIN_TDATA[293] !== 1'bz) && S_AXIS_DIN_TDATA_delay[293]; // rv 0 + assign S_AXIS_DIN_TDATA_in[294] = (S_AXIS_DIN_TDATA[294] !== 1'bz) && S_AXIS_DIN_TDATA_delay[294]; // rv 0 + assign S_AXIS_DIN_TDATA_in[295] = (S_AXIS_DIN_TDATA[295] !== 1'bz) && S_AXIS_DIN_TDATA_delay[295]; // rv 0 + assign S_AXIS_DIN_TDATA_in[296] = (S_AXIS_DIN_TDATA[296] !== 1'bz) && S_AXIS_DIN_TDATA_delay[296]; // rv 0 + assign S_AXIS_DIN_TDATA_in[297] = (S_AXIS_DIN_TDATA[297] !== 1'bz) && S_AXIS_DIN_TDATA_delay[297]; // rv 0 + assign S_AXIS_DIN_TDATA_in[298] = (S_AXIS_DIN_TDATA[298] !== 1'bz) && S_AXIS_DIN_TDATA_delay[298]; // rv 0 + assign S_AXIS_DIN_TDATA_in[299] = (S_AXIS_DIN_TDATA[299] !== 1'bz) && S_AXIS_DIN_TDATA_delay[299]; // rv 0 + assign S_AXIS_DIN_TDATA_in[29] = (S_AXIS_DIN_TDATA[29] !== 1'bz) && S_AXIS_DIN_TDATA_delay[29]; // rv 0 + assign S_AXIS_DIN_TDATA_in[2] = (S_AXIS_DIN_TDATA[2] !== 1'bz) && S_AXIS_DIN_TDATA_delay[2]; // rv 0 + assign S_AXIS_DIN_TDATA_in[300] = (S_AXIS_DIN_TDATA[300] !== 1'bz) && S_AXIS_DIN_TDATA_delay[300]; // rv 0 + assign S_AXIS_DIN_TDATA_in[301] = (S_AXIS_DIN_TDATA[301] !== 1'bz) && S_AXIS_DIN_TDATA_delay[301]; // rv 0 + assign S_AXIS_DIN_TDATA_in[302] = (S_AXIS_DIN_TDATA[302] !== 1'bz) && S_AXIS_DIN_TDATA_delay[302]; // rv 0 + assign S_AXIS_DIN_TDATA_in[303] = (S_AXIS_DIN_TDATA[303] !== 1'bz) && S_AXIS_DIN_TDATA_delay[303]; // rv 0 + assign S_AXIS_DIN_TDATA_in[304] = (S_AXIS_DIN_TDATA[304] !== 1'bz) && S_AXIS_DIN_TDATA_delay[304]; // rv 0 + assign S_AXIS_DIN_TDATA_in[305] = (S_AXIS_DIN_TDATA[305] !== 1'bz) && S_AXIS_DIN_TDATA_delay[305]; // rv 0 + assign S_AXIS_DIN_TDATA_in[306] = (S_AXIS_DIN_TDATA[306] !== 1'bz) && S_AXIS_DIN_TDATA_delay[306]; // rv 0 + assign S_AXIS_DIN_TDATA_in[307] = (S_AXIS_DIN_TDATA[307] !== 1'bz) && S_AXIS_DIN_TDATA_delay[307]; // rv 0 + assign S_AXIS_DIN_TDATA_in[308] = (S_AXIS_DIN_TDATA[308] !== 1'bz) && S_AXIS_DIN_TDATA_delay[308]; // rv 0 + assign S_AXIS_DIN_TDATA_in[309] = (S_AXIS_DIN_TDATA[309] !== 1'bz) && S_AXIS_DIN_TDATA_delay[309]; // rv 0 + assign S_AXIS_DIN_TDATA_in[30] = (S_AXIS_DIN_TDATA[30] !== 1'bz) && S_AXIS_DIN_TDATA_delay[30]; // rv 0 + assign S_AXIS_DIN_TDATA_in[310] = (S_AXIS_DIN_TDATA[310] !== 1'bz) && S_AXIS_DIN_TDATA_delay[310]; // rv 0 + assign S_AXIS_DIN_TDATA_in[311] = (S_AXIS_DIN_TDATA[311] !== 1'bz) && S_AXIS_DIN_TDATA_delay[311]; // rv 0 + assign S_AXIS_DIN_TDATA_in[312] = (S_AXIS_DIN_TDATA[312] !== 1'bz) && S_AXIS_DIN_TDATA_delay[312]; // rv 0 + assign S_AXIS_DIN_TDATA_in[313] = (S_AXIS_DIN_TDATA[313] !== 1'bz) && S_AXIS_DIN_TDATA_delay[313]; // rv 0 + assign S_AXIS_DIN_TDATA_in[314] = (S_AXIS_DIN_TDATA[314] !== 1'bz) && S_AXIS_DIN_TDATA_delay[314]; // rv 0 + assign S_AXIS_DIN_TDATA_in[315] = (S_AXIS_DIN_TDATA[315] !== 1'bz) && S_AXIS_DIN_TDATA_delay[315]; // rv 0 + assign S_AXIS_DIN_TDATA_in[316] = (S_AXIS_DIN_TDATA[316] !== 1'bz) && S_AXIS_DIN_TDATA_delay[316]; // rv 0 + assign S_AXIS_DIN_TDATA_in[317] = (S_AXIS_DIN_TDATA[317] !== 1'bz) && S_AXIS_DIN_TDATA_delay[317]; // rv 0 + assign S_AXIS_DIN_TDATA_in[318] = (S_AXIS_DIN_TDATA[318] !== 1'bz) && S_AXIS_DIN_TDATA_delay[318]; // rv 0 + assign S_AXIS_DIN_TDATA_in[319] = (S_AXIS_DIN_TDATA[319] !== 1'bz) && S_AXIS_DIN_TDATA_delay[319]; // rv 0 + assign S_AXIS_DIN_TDATA_in[31] = (S_AXIS_DIN_TDATA[31] !== 1'bz) && S_AXIS_DIN_TDATA_delay[31]; // rv 0 + assign S_AXIS_DIN_TDATA_in[320] = (S_AXIS_DIN_TDATA[320] !== 1'bz) && S_AXIS_DIN_TDATA_delay[320]; // rv 0 + assign S_AXIS_DIN_TDATA_in[321] = (S_AXIS_DIN_TDATA[321] !== 1'bz) && S_AXIS_DIN_TDATA_delay[321]; // rv 0 + assign S_AXIS_DIN_TDATA_in[322] = (S_AXIS_DIN_TDATA[322] !== 1'bz) && S_AXIS_DIN_TDATA_delay[322]; // rv 0 + assign S_AXIS_DIN_TDATA_in[323] = (S_AXIS_DIN_TDATA[323] !== 1'bz) && S_AXIS_DIN_TDATA_delay[323]; // rv 0 + assign S_AXIS_DIN_TDATA_in[324] = (S_AXIS_DIN_TDATA[324] !== 1'bz) && S_AXIS_DIN_TDATA_delay[324]; // rv 0 + assign S_AXIS_DIN_TDATA_in[325] = (S_AXIS_DIN_TDATA[325] !== 1'bz) && S_AXIS_DIN_TDATA_delay[325]; // rv 0 + assign S_AXIS_DIN_TDATA_in[326] = (S_AXIS_DIN_TDATA[326] !== 1'bz) && S_AXIS_DIN_TDATA_delay[326]; // rv 0 + assign S_AXIS_DIN_TDATA_in[327] = (S_AXIS_DIN_TDATA[327] !== 1'bz) && S_AXIS_DIN_TDATA_delay[327]; // rv 0 + assign S_AXIS_DIN_TDATA_in[328] = (S_AXIS_DIN_TDATA[328] !== 1'bz) && S_AXIS_DIN_TDATA_delay[328]; // rv 0 + assign S_AXIS_DIN_TDATA_in[329] = (S_AXIS_DIN_TDATA[329] !== 1'bz) && S_AXIS_DIN_TDATA_delay[329]; // rv 0 + assign S_AXIS_DIN_TDATA_in[32] = (S_AXIS_DIN_TDATA[32] !== 1'bz) && S_AXIS_DIN_TDATA_delay[32]; // rv 0 + assign S_AXIS_DIN_TDATA_in[330] = (S_AXIS_DIN_TDATA[330] !== 1'bz) && S_AXIS_DIN_TDATA_delay[330]; // rv 0 + assign S_AXIS_DIN_TDATA_in[331] = (S_AXIS_DIN_TDATA[331] !== 1'bz) && S_AXIS_DIN_TDATA_delay[331]; // rv 0 + assign S_AXIS_DIN_TDATA_in[332] = (S_AXIS_DIN_TDATA[332] !== 1'bz) && S_AXIS_DIN_TDATA_delay[332]; // rv 0 + assign S_AXIS_DIN_TDATA_in[333] = (S_AXIS_DIN_TDATA[333] !== 1'bz) && S_AXIS_DIN_TDATA_delay[333]; // rv 0 + assign S_AXIS_DIN_TDATA_in[334] = (S_AXIS_DIN_TDATA[334] !== 1'bz) && S_AXIS_DIN_TDATA_delay[334]; // rv 0 + assign S_AXIS_DIN_TDATA_in[335] = (S_AXIS_DIN_TDATA[335] !== 1'bz) && S_AXIS_DIN_TDATA_delay[335]; // rv 0 + assign S_AXIS_DIN_TDATA_in[336] = (S_AXIS_DIN_TDATA[336] !== 1'bz) && S_AXIS_DIN_TDATA_delay[336]; // rv 0 + assign S_AXIS_DIN_TDATA_in[337] = (S_AXIS_DIN_TDATA[337] !== 1'bz) && S_AXIS_DIN_TDATA_delay[337]; // rv 0 + assign S_AXIS_DIN_TDATA_in[338] = (S_AXIS_DIN_TDATA[338] !== 1'bz) && S_AXIS_DIN_TDATA_delay[338]; // rv 0 + assign S_AXIS_DIN_TDATA_in[339] = (S_AXIS_DIN_TDATA[339] !== 1'bz) && S_AXIS_DIN_TDATA_delay[339]; // rv 0 + assign S_AXIS_DIN_TDATA_in[33] = (S_AXIS_DIN_TDATA[33] !== 1'bz) && S_AXIS_DIN_TDATA_delay[33]; // rv 0 + assign S_AXIS_DIN_TDATA_in[340] = (S_AXIS_DIN_TDATA[340] !== 1'bz) && S_AXIS_DIN_TDATA_delay[340]; // rv 0 + assign S_AXIS_DIN_TDATA_in[341] = (S_AXIS_DIN_TDATA[341] !== 1'bz) && S_AXIS_DIN_TDATA_delay[341]; // rv 0 + assign S_AXIS_DIN_TDATA_in[342] = (S_AXIS_DIN_TDATA[342] !== 1'bz) && S_AXIS_DIN_TDATA_delay[342]; // rv 0 + assign S_AXIS_DIN_TDATA_in[343] = (S_AXIS_DIN_TDATA[343] !== 1'bz) && S_AXIS_DIN_TDATA_delay[343]; // rv 0 + assign S_AXIS_DIN_TDATA_in[344] = (S_AXIS_DIN_TDATA[344] !== 1'bz) && S_AXIS_DIN_TDATA_delay[344]; // rv 0 + assign S_AXIS_DIN_TDATA_in[345] = (S_AXIS_DIN_TDATA[345] !== 1'bz) && S_AXIS_DIN_TDATA_delay[345]; // rv 0 + assign S_AXIS_DIN_TDATA_in[346] = (S_AXIS_DIN_TDATA[346] !== 1'bz) && S_AXIS_DIN_TDATA_delay[346]; // rv 0 + assign S_AXIS_DIN_TDATA_in[347] = (S_AXIS_DIN_TDATA[347] !== 1'bz) && S_AXIS_DIN_TDATA_delay[347]; // rv 0 + assign S_AXIS_DIN_TDATA_in[348] = (S_AXIS_DIN_TDATA[348] !== 1'bz) && S_AXIS_DIN_TDATA_delay[348]; // rv 0 + assign S_AXIS_DIN_TDATA_in[349] = (S_AXIS_DIN_TDATA[349] !== 1'bz) && S_AXIS_DIN_TDATA_delay[349]; // rv 0 + assign S_AXIS_DIN_TDATA_in[34] = (S_AXIS_DIN_TDATA[34] !== 1'bz) && S_AXIS_DIN_TDATA_delay[34]; // rv 0 + assign S_AXIS_DIN_TDATA_in[350] = (S_AXIS_DIN_TDATA[350] !== 1'bz) && S_AXIS_DIN_TDATA_delay[350]; // rv 0 + assign S_AXIS_DIN_TDATA_in[351] = (S_AXIS_DIN_TDATA[351] !== 1'bz) && S_AXIS_DIN_TDATA_delay[351]; // rv 0 + assign S_AXIS_DIN_TDATA_in[352] = (S_AXIS_DIN_TDATA[352] !== 1'bz) && S_AXIS_DIN_TDATA_delay[352]; // rv 0 + assign S_AXIS_DIN_TDATA_in[353] = (S_AXIS_DIN_TDATA[353] !== 1'bz) && S_AXIS_DIN_TDATA_delay[353]; // rv 0 + assign S_AXIS_DIN_TDATA_in[354] = (S_AXIS_DIN_TDATA[354] !== 1'bz) && S_AXIS_DIN_TDATA_delay[354]; // rv 0 + assign S_AXIS_DIN_TDATA_in[355] = (S_AXIS_DIN_TDATA[355] !== 1'bz) && S_AXIS_DIN_TDATA_delay[355]; // rv 0 + assign S_AXIS_DIN_TDATA_in[356] = (S_AXIS_DIN_TDATA[356] !== 1'bz) && S_AXIS_DIN_TDATA_delay[356]; // rv 0 + assign S_AXIS_DIN_TDATA_in[357] = (S_AXIS_DIN_TDATA[357] !== 1'bz) && S_AXIS_DIN_TDATA_delay[357]; // rv 0 + assign S_AXIS_DIN_TDATA_in[358] = (S_AXIS_DIN_TDATA[358] !== 1'bz) && S_AXIS_DIN_TDATA_delay[358]; // rv 0 + assign S_AXIS_DIN_TDATA_in[359] = (S_AXIS_DIN_TDATA[359] !== 1'bz) && S_AXIS_DIN_TDATA_delay[359]; // rv 0 + assign S_AXIS_DIN_TDATA_in[35] = (S_AXIS_DIN_TDATA[35] !== 1'bz) && S_AXIS_DIN_TDATA_delay[35]; // rv 0 + assign S_AXIS_DIN_TDATA_in[360] = (S_AXIS_DIN_TDATA[360] !== 1'bz) && S_AXIS_DIN_TDATA_delay[360]; // rv 0 + assign S_AXIS_DIN_TDATA_in[361] = (S_AXIS_DIN_TDATA[361] !== 1'bz) && S_AXIS_DIN_TDATA_delay[361]; // rv 0 + assign S_AXIS_DIN_TDATA_in[362] = (S_AXIS_DIN_TDATA[362] !== 1'bz) && S_AXIS_DIN_TDATA_delay[362]; // rv 0 + assign S_AXIS_DIN_TDATA_in[363] = (S_AXIS_DIN_TDATA[363] !== 1'bz) && S_AXIS_DIN_TDATA_delay[363]; // rv 0 + assign S_AXIS_DIN_TDATA_in[364] = (S_AXIS_DIN_TDATA[364] !== 1'bz) && S_AXIS_DIN_TDATA_delay[364]; // rv 0 + assign S_AXIS_DIN_TDATA_in[365] = (S_AXIS_DIN_TDATA[365] !== 1'bz) && S_AXIS_DIN_TDATA_delay[365]; // rv 0 + assign S_AXIS_DIN_TDATA_in[366] = (S_AXIS_DIN_TDATA[366] !== 1'bz) && S_AXIS_DIN_TDATA_delay[366]; // rv 0 + assign S_AXIS_DIN_TDATA_in[367] = (S_AXIS_DIN_TDATA[367] !== 1'bz) && S_AXIS_DIN_TDATA_delay[367]; // rv 0 + assign S_AXIS_DIN_TDATA_in[368] = (S_AXIS_DIN_TDATA[368] !== 1'bz) && S_AXIS_DIN_TDATA_delay[368]; // rv 0 + assign S_AXIS_DIN_TDATA_in[369] = (S_AXIS_DIN_TDATA[369] !== 1'bz) && S_AXIS_DIN_TDATA_delay[369]; // rv 0 + assign S_AXIS_DIN_TDATA_in[36] = (S_AXIS_DIN_TDATA[36] !== 1'bz) && S_AXIS_DIN_TDATA_delay[36]; // rv 0 + assign S_AXIS_DIN_TDATA_in[370] = (S_AXIS_DIN_TDATA[370] !== 1'bz) && S_AXIS_DIN_TDATA_delay[370]; // rv 0 + assign S_AXIS_DIN_TDATA_in[371] = (S_AXIS_DIN_TDATA[371] !== 1'bz) && S_AXIS_DIN_TDATA_delay[371]; // rv 0 + assign S_AXIS_DIN_TDATA_in[372] = (S_AXIS_DIN_TDATA[372] !== 1'bz) && S_AXIS_DIN_TDATA_delay[372]; // rv 0 + assign S_AXIS_DIN_TDATA_in[373] = (S_AXIS_DIN_TDATA[373] !== 1'bz) && S_AXIS_DIN_TDATA_delay[373]; // rv 0 + assign S_AXIS_DIN_TDATA_in[374] = (S_AXIS_DIN_TDATA[374] !== 1'bz) && S_AXIS_DIN_TDATA_delay[374]; // rv 0 + assign S_AXIS_DIN_TDATA_in[375] = (S_AXIS_DIN_TDATA[375] !== 1'bz) && S_AXIS_DIN_TDATA_delay[375]; // rv 0 + assign S_AXIS_DIN_TDATA_in[376] = (S_AXIS_DIN_TDATA[376] !== 1'bz) && S_AXIS_DIN_TDATA_delay[376]; // rv 0 + assign S_AXIS_DIN_TDATA_in[377] = (S_AXIS_DIN_TDATA[377] !== 1'bz) && S_AXIS_DIN_TDATA_delay[377]; // rv 0 + assign S_AXIS_DIN_TDATA_in[378] = (S_AXIS_DIN_TDATA[378] !== 1'bz) && S_AXIS_DIN_TDATA_delay[378]; // rv 0 + assign S_AXIS_DIN_TDATA_in[379] = (S_AXIS_DIN_TDATA[379] !== 1'bz) && S_AXIS_DIN_TDATA_delay[379]; // rv 0 + assign S_AXIS_DIN_TDATA_in[37] = (S_AXIS_DIN_TDATA[37] !== 1'bz) && S_AXIS_DIN_TDATA_delay[37]; // rv 0 + assign S_AXIS_DIN_TDATA_in[380] = (S_AXIS_DIN_TDATA[380] !== 1'bz) && S_AXIS_DIN_TDATA_delay[380]; // rv 0 + assign S_AXIS_DIN_TDATA_in[381] = (S_AXIS_DIN_TDATA[381] !== 1'bz) && S_AXIS_DIN_TDATA_delay[381]; // rv 0 + assign S_AXIS_DIN_TDATA_in[382] = (S_AXIS_DIN_TDATA[382] !== 1'bz) && S_AXIS_DIN_TDATA_delay[382]; // rv 0 + assign S_AXIS_DIN_TDATA_in[383] = (S_AXIS_DIN_TDATA[383] !== 1'bz) && S_AXIS_DIN_TDATA_delay[383]; // rv 0 + assign S_AXIS_DIN_TDATA_in[384] = (S_AXIS_DIN_TDATA[384] !== 1'bz) && S_AXIS_DIN_TDATA_delay[384]; // rv 0 + assign S_AXIS_DIN_TDATA_in[385] = (S_AXIS_DIN_TDATA[385] !== 1'bz) && S_AXIS_DIN_TDATA_delay[385]; // rv 0 + assign S_AXIS_DIN_TDATA_in[386] = (S_AXIS_DIN_TDATA[386] !== 1'bz) && S_AXIS_DIN_TDATA_delay[386]; // rv 0 + assign S_AXIS_DIN_TDATA_in[387] = (S_AXIS_DIN_TDATA[387] !== 1'bz) && S_AXIS_DIN_TDATA_delay[387]; // rv 0 + assign S_AXIS_DIN_TDATA_in[388] = (S_AXIS_DIN_TDATA[388] !== 1'bz) && S_AXIS_DIN_TDATA_delay[388]; // rv 0 + assign S_AXIS_DIN_TDATA_in[389] = (S_AXIS_DIN_TDATA[389] !== 1'bz) && S_AXIS_DIN_TDATA_delay[389]; // rv 0 + assign S_AXIS_DIN_TDATA_in[38] = (S_AXIS_DIN_TDATA[38] !== 1'bz) && S_AXIS_DIN_TDATA_delay[38]; // rv 0 + assign S_AXIS_DIN_TDATA_in[390] = (S_AXIS_DIN_TDATA[390] !== 1'bz) && S_AXIS_DIN_TDATA_delay[390]; // rv 0 + assign S_AXIS_DIN_TDATA_in[391] = (S_AXIS_DIN_TDATA[391] !== 1'bz) && S_AXIS_DIN_TDATA_delay[391]; // rv 0 + assign S_AXIS_DIN_TDATA_in[392] = (S_AXIS_DIN_TDATA[392] !== 1'bz) && S_AXIS_DIN_TDATA_delay[392]; // rv 0 + assign S_AXIS_DIN_TDATA_in[393] = (S_AXIS_DIN_TDATA[393] !== 1'bz) && S_AXIS_DIN_TDATA_delay[393]; // rv 0 + assign S_AXIS_DIN_TDATA_in[394] = (S_AXIS_DIN_TDATA[394] !== 1'bz) && S_AXIS_DIN_TDATA_delay[394]; // rv 0 + assign S_AXIS_DIN_TDATA_in[395] = (S_AXIS_DIN_TDATA[395] !== 1'bz) && S_AXIS_DIN_TDATA_delay[395]; // rv 0 + assign S_AXIS_DIN_TDATA_in[396] = (S_AXIS_DIN_TDATA[396] !== 1'bz) && S_AXIS_DIN_TDATA_delay[396]; // rv 0 + assign S_AXIS_DIN_TDATA_in[397] = (S_AXIS_DIN_TDATA[397] !== 1'bz) && S_AXIS_DIN_TDATA_delay[397]; // rv 0 + assign S_AXIS_DIN_TDATA_in[398] = (S_AXIS_DIN_TDATA[398] !== 1'bz) && S_AXIS_DIN_TDATA_delay[398]; // rv 0 + assign S_AXIS_DIN_TDATA_in[399] = (S_AXIS_DIN_TDATA[399] !== 1'bz) && S_AXIS_DIN_TDATA_delay[399]; // rv 0 + assign S_AXIS_DIN_TDATA_in[39] = (S_AXIS_DIN_TDATA[39] !== 1'bz) && S_AXIS_DIN_TDATA_delay[39]; // rv 0 + assign S_AXIS_DIN_TDATA_in[3] = (S_AXIS_DIN_TDATA[3] !== 1'bz) && S_AXIS_DIN_TDATA_delay[3]; // rv 0 + assign S_AXIS_DIN_TDATA_in[400] = (S_AXIS_DIN_TDATA[400] !== 1'bz) && S_AXIS_DIN_TDATA_delay[400]; // rv 0 + assign S_AXIS_DIN_TDATA_in[401] = (S_AXIS_DIN_TDATA[401] !== 1'bz) && S_AXIS_DIN_TDATA_delay[401]; // rv 0 + assign S_AXIS_DIN_TDATA_in[402] = (S_AXIS_DIN_TDATA[402] !== 1'bz) && S_AXIS_DIN_TDATA_delay[402]; // rv 0 + assign S_AXIS_DIN_TDATA_in[403] = (S_AXIS_DIN_TDATA[403] !== 1'bz) && S_AXIS_DIN_TDATA_delay[403]; // rv 0 + assign S_AXIS_DIN_TDATA_in[404] = (S_AXIS_DIN_TDATA[404] !== 1'bz) && S_AXIS_DIN_TDATA_delay[404]; // rv 0 + assign S_AXIS_DIN_TDATA_in[405] = (S_AXIS_DIN_TDATA[405] !== 1'bz) && S_AXIS_DIN_TDATA_delay[405]; // rv 0 + assign S_AXIS_DIN_TDATA_in[406] = (S_AXIS_DIN_TDATA[406] !== 1'bz) && S_AXIS_DIN_TDATA_delay[406]; // rv 0 + assign S_AXIS_DIN_TDATA_in[407] = (S_AXIS_DIN_TDATA[407] !== 1'bz) && S_AXIS_DIN_TDATA_delay[407]; // rv 0 + assign S_AXIS_DIN_TDATA_in[408] = (S_AXIS_DIN_TDATA[408] !== 1'bz) && S_AXIS_DIN_TDATA_delay[408]; // rv 0 + assign S_AXIS_DIN_TDATA_in[409] = (S_AXIS_DIN_TDATA[409] !== 1'bz) && S_AXIS_DIN_TDATA_delay[409]; // rv 0 + assign S_AXIS_DIN_TDATA_in[40] = (S_AXIS_DIN_TDATA[40] !== 1'bz) && S_AXIS_DIN_TDATA_delay[40]; // rv 0 + assign S_AXIS_DIN_TDATA_in[410] = (S_AXIS_DIN_TDATA[410] !== 1'bz) && S_AXIS_DIN_TDATA_delay[410]; // rv 0 + assign S_AXIS_DIN_TDATA_in[411] = (S_AXIS_DIN_TDATA[411] !== 1'bz) && S_AXIS_DIN_TDATA_delay[411]; // rv 0 + assign S_AXIS_DIN_TDATA_in[412] = (S_AXIS_DIN_TDATA[412] !== 1'bz) && S_AXIS_DIN_TDATA_delay[412]; // rv 0 + assign S_AXIS_DIN_TDATA_in[413] = (S_AXIS_DIN_TDATA[413] !== 1'bz) && S_AXIS_DIN_TDATA_delay[413]; // rv 0 + assign S_AXIS_DIN_TDATA_in[414] = (S_AXIS_DIN_TDATA[414] !== 1'bz) && S_AXIS_DIN_TDATA_delay[414]; // rv 0 + assign S_AXIS_DIN_TDATA_in[415] = (S_AXIS_DIN_TDATA[415] !== 1'bz) && S_AXIS_DIN_TDATA_delay[415]; // rv 0 + assign S_AXIS_DIN_TDATA_in[416] = (S_AXIS_DIN_TDATA[416] !== 1'bz) && S_AXIS_DIN_TDATA_delay[416]; // rv 0 + assign S_AXIS_DIN_TDATA_in[417] = (S_AXIS_DIN_TDATA[417] !== 1'bz) && S_AXIS_DIN_TDATA_delay[417]; // rv 0 + assign S_AXIS_DIN_TDATA_in[418] = (S_AXIS_DIN_TDATA[418] !== 1'bz) && S_AXIS_DIN_TDATA_delay[418]; // rv 0 + assign S_AXIS_DIN_TDATA_in[419] = (S_AXIS_DIN_TDATA[419] !== 1'bz) && S_AXIS_DIN_TDATA_delay[419]; // rv 0 + assign S_AXIS_DIN_TDATA_in[41] = (S_AXIS_DIN_TDATA[41] !== 1'bz) && S_AXIS_DIN_TDATA_delay[41]; // rv 0 + assign S_AXIS_DIN_TDATA_in[420] = (S_AXIS_DIN_TDATA[420] !== 1'bz) && S_AXIS_DIN_TDATA_delay[420]; // rv 0 + assign S_AXIS_DIN_TDATA_in[421] = (S_AXIS_DIN_TDATA[421] !== 1'bz) && S_AXIS_DIN_TDATA_delay[421]; // rv 0 + assign S_AXIS_DIN_TDATA_in[422] = (S_AXIS_DIN_TDATA[422] !== 1'bz) && S_AXIS_DIN_TDATA_delay[422]; // rv 0 + assign S_AXIS_DIN_TDATA_in[423] = (S_AXIS_DIN_TDATA[423] !== 1'bz) && S_AXIS_DIN_TDATA_delay[423]; // rv 0 + assign S_AXIS_DIN_TDATA_in[424] = (S_AXIS_DIN_TDATA[424] !== 1'bz) && S_AXIS_DIN_TDATA_delay[424]; // rv 0 + assign S_AXIS_DIN_TDATA_in[425] = (S_AXIS_DIN_TDATA[425] !== 1'bz) && S_AXIS_DIN_TDATA_delay[425]; // rv 0 + assign S_AXIS_DIN_TDATA_in[426] = (S_AXIS_DIN_TDATA[426] !== 1'bz) && S_AXIS_DIN_TDATA_delay[426]; // rv 0 + assign S_AXIS_DIN_TDATA_in[427] = (S_AXIS_DIN_TDATA[427] !== 1'bz) && S_AXIS_DIN_TDATA_delay[427]; // rv 0 + assign S_AXIS_DIN_TDATA_in[428] = (S_AXIS_DIN_TDATA[428] !== 1'bz) && S_AXIS_DIN_TDATA_delay[428]; // rv 0 + assign S_AXIS_DIN_TDATA_in[429] = (S_AXIS_DIN_TDATA[429] !== 1'bz) && S_AXIS_DIN_TDATA_delay[429]; // rv 0 + assign S_AXIS_DIN_TDATA_in[42] = (S_AXIS_DIN_TDATA[42] !== 1'bz) && S_AXIS_DIN_TDATA_delay[42]; // rv 0 + assign S_AXIS_DIN_TDATA_in[430] = (S_AXIS_DIN_TDATA[430] !== 1'bz) && S_AXIS_DIN_TDATA_delay[430]; // rv 0 + assign S_AXIS_DIN_TDATA_in[431] = (S_AXIS_DIN_TDATA[431] !== 1'bz) && S_AXIS_DIN_TDATA_delay[431]; // rv 0 + assign S_AXIS_DIN_TDATA_in[432] = (S_AXIS_DIN_TDATA[432] !== 1'bz) && S_AXIS_DIN_TDATA_delay[432]; // rv 0 + assign S_AXIS_DIN_TDATA_in[433] = (S_AXIS_DIN_TDATA[433] !== 1'bz) && S_AXIS_DIN_TDATA_delay[433]; // rv 0 + assign S_AXIS_DIN_TDATA_in[434] = (S_AXIS_DIN_TDATA[434] !== 1'bz) && S_AXIS_DIN_TDATA_delay[434]; // rv 0 + assign S_AXIS_DIN_TDATA_in[435] = (S_AXIS_DIN_TDATA[435] !== 1'bz) && S_AXIS_DIN_TDATA_delay[435]; // rv 0 + assign S_AXIS_DIN_TDATA_in[436] = (S_AXIS_DIN_TDATA[436] !== 1'bz) && S_AXIS_DIN_TDATA_delay[436]; // rv 0 + assign S_AXIS_DIN_TDATA_in[437] = (S_AXIS_DIN_TDATA[437] !== 1'bz) && S_AXIS_DIN_TDATA_delay[437]; // rv 0 + assign S_AXIS_DIN_TDATA_in[438] = (S_AXIS_DIN_TDATA[438] !== 1'bz) && S_AXIS_DIN_TDATA_delay[438]; // rv 0 + assign S_AXIS_DIN_TDATA_in[439] = (S_AXIS_DIN_TDATA[439] !== 1'bz) && S_AXIS_DIN_TDATA_delay[439]; // rv 0 + assign S_AXIS_DIN_TDATA_in[43] = (S_AXIS_DIN_TDATA[43] !== 1'bz) && S_AXIS_DIN_TDATA_delay[43]; // rv 0 + assign S_AXIS_DIN_TDATA_in[440] = (S_AXIS_DIN_TDATA[440] !== 1'bz) && S_AXIS_DIN_TDATA_delay[440]; // rv 0 + assign S_AXIS_DIN_TDATA_in[441] = (S_AXIS_DIN_TDATA[441] !== 1'bz) && S_AXIS_DIN_TDATA_delay[441]; // rv 0 + assign S_AXIS_DIN_TDATA_in[442] = (S_AXIS_DIN_TDATA[442] !== 1'bz) && S_AXIS_DIN_TDATA_delay[442]; // rv 0 + assign S_AXIS_DIN_TDATA_in[443] = (S_AXIS_DIN_TDATA[443] !== 1'bz) && S_AXIS_DIN_TDATA_delay[443]; // rv 0 + assign S_AXIS_DIN_TDATA_in[444] = (S_AXIS_DIN_TDATA[444] !== 1'bz) && S_AXIS_DIN_TDATA_delay[444]; // rv 0 + assign S_AXIS_DIN_TDATA_in[445] = (S_AXIS_DIN_TDATA[445] !== 1'bz) && S_AXIS_DIN_TDATA_delay[445]; // rv 0 + assign S_AXIS_DIN_TDATA_in[446] = (S_AXIS_DIN_TDATA[446] !== 1'bz) && S_AXIS_DIN_TDATA_delay[446]; // rv 0 + assign S_AXIS_DIN_TDATA_in[447] = (S_AXIS_DIN_TDATA[447] !== 1'bz) && S_AXIS_DIN_TDATA_delay[447]; // rv 0 + assign S_AXIS_DIN_TDATA_in[448] = (S_AXIS_DIN_TDATA[448] !== 1'bz) && S_AXIS_DIN_TDATA_delay[448]; // rv 0 + assign S_AXIS_DIN_TDATA_in[449] = (S_AXIS_DIN_TDATA[449] !== 1'bz) && S_AXIS_DIN_TDATA_delay[449]; // rv 0 + assign S_AXIS_DIN_TDATA_in[44] = (S_AXIS_DIN_TDATA[44] !== 1'bz) && S_AXIS_DIN_TDATA_delay[44]; // rv 0 + assign S_AXIS_DIN_TDATA_in[450] = (S_AXIS_DIN_TDATA[450] !== 1'bz) && S_AXIS_DIN_TDATA_delay[450]; // rv 0 + assign S_AXIS_DIN_TDATA_in[451] = (S_AXIS_DIN_TDATA[451] !== 1'bz) && S_AXIS_DIN_TDATA_delay[451]; // rv 0 + assign S_AXIS_DIN_TDATA_in[452] = (S_AXIS_DIN_TDATA[452] !== 1'bz) && S_AXIS_DIN_TDATA_delay[452]; // rv 0 + assign S_AXIS_DIN_TDATA_in[453] = (S_AXIS_DIN_TDATA[453] !== 1'bz) && S_AXIS_DIN_TDATA_delay[453]; // rv 0 + assign S_AXIS_DIN_TDATA_in[454] = (S_AXIS_DIN_TDATA[454] !== 1'bz) && S_AXIS_DIN_TDATA_delay[454]; // rv 0 + assign S_AXIS_DIN_TDATA_in[455] = (S_AXIS_DIN_TDATA[455] !== 1'bz) && S_AXIS_DIN_TDATA_delay[455]; // rv 0 + assign S_AXIS_DIN_TDATA_in[456] = (S_AXIS_DIN_TDATA[456] !== 1'bz) && S_AXIS_DIN_TDATA_delay[456]; // rv 0 + assign S_AXIS_DIN_TDATA_in[457] = (S_AXIS_DIN_TDATA[457] !== 1'bz) && S_AXIS_DIN_TDATA_delay[457]; // rv 0 + assign S_AXIS_DIN_TDATA_in[458] = (S_AXIS_DIN_TDATA[458] !== 1'bz) && S_AXIS_DIN_TDATA_delay[458]; // rv 0 + assign S_AXIS_DIN_TDATA_in[459] = (S_AXIS_DIN_TDATA[459] !== 1'bz) && S_AXIS_DIN_TDATA_delay[459]; // rv 0 + assign S_AXIS_DIN_TDATA_in[45] = (S_AXIS_DIN_TDATA[45] !== 1'bz) && S_AXIS_DIN_TDATA_delay[45]; // rv 0 + assign S_AXIS_DIN_TDATA_in[460] = (S_AXIS_DIN_TDATA[460] !== 1'bz) && S_AXIS_DIN_TDATA_delay[460]; // rv 0 + assign S_AXIS_DIN_TDATA_in[461] = (S_AXIS_DIN_TDATA[461] !== 1'bz) && S_AXIS_DIN_TDATA_delay[461]; // rv 0 + assign S_AXIS_DIN_TDATA_in[462] = (S_AXIS_DIN_TDATA[462] !== 1'bz) && S_AXIS_DIN_TDATA_delay[462]; // rv 0 + assign S_AXIS_DIN_TDATA_in[463] = (S_AXIS_DIN_TDATA[463] !== 1'bz) && S_AXIS_DIN_TDATA_delay[463]; // rv 0 + assign S_AXIS_DIN_TDATA_in[464] = (S_AXIS_DIN_TDATA[464] !== 1'bz) && S_AXIS_DIN_TDATA_delay[464]; // rv 0 + assign S_AXIS_DIN_TDATA_in[465] = (S_AXIS_DIN_TDATA[465] !== 1'bz) && S_AXIS_DIN_TDATA_delay[465]; // rv 0 + assign S_AXIS_DIN_TDATA_in[466] = (S_AXIS_DIN_TDATA[466] !== 1'bz) && S_AXIS_DIN_TDATA_delay[466]; // rv 0 + assign S_AXIS_DIN_TDATA_in[467] = (S_AXIS_DIN_TDATA[467] !== 1'bz) && S_AXIS_DIN_TDATA_delay[467]; // rv 0 + assign S_AXIS_DIN_TDATA_in[468] = (S_AXIS_DIN_TDATA[468] !== 1'bz) && S_AXIS_DIN_TDATA_delay[468]; // rv 0 + assign S_AXIS_DIN_TDATA_in[469] = (S_AXIS_DIN_TDATA[469] !== 1'bz) && S_AXIS_DIN_TDATA_delay[469]; // rv 0 + assign S_AXIS_DIN_TDATA_in[46] = (S_AXIS_DIN_TDATA[46] !== 1'bz) && S_AXIS_DIN_TDATA_delay[46]; // rv 0 + assign S_AXIS_DIN_TDATA_in[470] = (S_AXIS_DIN_TDATA[470] !== 1'bz) && S_AXIS_DIN_TDATA_delay[470]; // rv 0 + assign S_AXIS_DIN_TDATA_in[471] = (S_AXIS_DIN_TDATA[471] !== 1'bz) && S_AXIS_DIN_TDATA_delay[471]; // rv 0 + assign S_AXIS_DIN_TDATA_in[472] = (S_AXIS_DIN_TDATA[472] !== 1'bz) && S_AXIS_DIN_TDATA_delay[472]; // rv 0 + assign S_AXIS_DIN_TDATA_in[473] = (S_AXIS_DIN_TDATA[473] !== 1'bz) && S_AXIS_DIN_TDATA_delay[473]; // rv 0 + assign S_AXIS_DIN_TDATA_in[474] = (S_AXIS_DIN_TDATA[474] !== 1'bz) && S_AXIS_DIN_TDATA_delay[474]; // rv 0 + assign S_AXIS_DIN_TDATA_in[475] = (S_AXIS_DIN_TDATA[475] !== 1'bz) && S_AXIS_DIN_TDATA_delay[475]; // rv 0 + assign S_AXIS_DIN_TDATA_in[476] = (S_AXIS_DIN_TDATA[476] !== 1'bz) && S_AXIS_DIN_TDATA_delay[476]; // rv 0 + assign S_AXIS_DIN_TDATA_in[477] = (S_AXIS_DIN_TDATA[477] !== 1'bz) && S_AXIS_DIN_TDATA_delay[477]; // rv 0 + assign S_AXIS_DIN_TDATA_in[478] = (S_AXIS_DIN_TDATA[478] !== 1'bz) && S_AXIS_DIN_TDATA_delay[478]; // rv 0 + assign S_AXIS_DIN_TDATA_in[479] = (S_AXIS_DIN_TDATA[479] !== 1'bz) && S_AXIS_DIN_TDATA_delay[479]; // rv 0 + assign S_AXIS_DIN_TDATA_in[47] = (S_AXIS_DIN_TDATA[47] !== 1'bz) && S_AXIS_DIN_TDATA_delay[47]; // rv 0 + assign S_AXIS_DIN_TDATA_in[480] = (S_AXIS_DIN_TDATA[480] !== 1'bz) && S_AXIS_DIN_TDATA_delay[480]; // rv 0 + assign S_AXIS_DIN_TDATA_in[481] = (S_AXIS_DIN_TDATA[481] !== 1'bz) && S_AXIS_DIN_TDATA_delay[481]; // rv 0 + assign S_AXIS_DIN_TDATA_in[482] = (S_AXIS_DIN_TDATA[482] !== 1'bz) && S_AXIS_DIN_TDATA_delay[482]; // rv 0 + assign S_AXIS_DIN_TDATA_in[483] = (S_AXIS_DIN_TDATA[483] !== 1'bz) && S_AXIS_DIN_TDATA_delay[483]; // rv 0 + assign S_AXIS_DIN_TDATA_in[484] = (S_AXIS_DIN_TDATA[484] !== 1'bz) && S_AXIS_DIN_TDATA_delay[484]; // rv 0 + assign S_AXIS_DIN_TDATA_in[485] = (S_AXIS_DIN_TDATA[485] !== 1'bz) && S_AXIS_DIN_TDATA_delay[485]; // rv 0 + assign S_AXIS_DIN_TDATA_in[486] = (S_AXIS_DIN_TDATA[486] !== 1'bz) && S_AXIS_DIN_TDATA_delay[486]; // rv 0 + assign S_AXIS_DIN_TDATA_in[487] = (S_AXIS_DIN_TDATA[487] !== 1'bz) && S_AXIS_DIN_TDATA_delay[487]; // rv 0 + assign S_AXIS_DIN_TDATA_in[488] = (S_AXIS_DIN_TDATA[488] !== 1'bz) && S_AXIS_DIN_TDATA_delay[488]; // rv 0 + assign S_AXIS_DIN_TDATA_in[489] = (S_AXIS_DIN_TDATA[489] !== 1'bz) && S_AXIS_DIN_TDATA_delay[489]; // rv 0 + assign S_AXIS_DIN_TDATA_in[48] = (S_AXIS_DIN_TDATA[48] !== 1'bz) && S_AXIS_DIN_TDATA_delay[48]; // rv 0 + assign S_AXIS_DIN_TDATA_in[490] = (S_AXIS_DIN_TDATA[490] !== 1'bz) && S_AXIS_DIN_TDATA_delay[490]; // rv 0 + assign S_AXIS_DIN_TDATA_in[491] = (S_AXIS_DIN_TDATA[491] !== 1'bz) && S_AXIS_DIN_TDATA_delay[491]; // rv 0 + assign S_AXIS_DIN_TDATA_in[492] = (S_AXIS_DIN_TDATA[492] !== 1'bz) && S_AXIS_DIN_TDATA_delay[492]; // rv 0 + assign S_AXIS_DIN_TDATA_in[493] = (S_AXIS_DIN_TDATA[493] !== 1'bz) && S_AXIS_DIN_TDATA_delay[493]; // rv 0 + assign S_AXIS_DIN_TDATA_in[494] = (S_AXIS_DIN_TDATA[494] !== 1'bz) && S_AXIS_DIN_TDATA_delay[494]; // rv 0 + assign S_AXIS_DIN_TDATA_in[495] = (S_AXIS_DIN_TDATA[495] !== 1'bz) && S_AXIS_DIN_TDATA_delay[495]; // rv 0 + assign S_AXIS_DIN_TDATA_in[496] = (S_AXIS_DIN_TDATA[496] !== 1'bz) && S_AXIS_DIN_TDATA_delay[496]; // rv 0 + assign S_AXIS_DIN_TDATA_in[497] = (S_AXIS_DIN_TDATA[497] !== 1'bz) && S_AXIS_DIN_TDATA_delay[497]; // rv 0 + assign S_AXIS_DIN_TDATA_in[498] = (S_AXIS_DIN_TDATA[498] !== 1'bz) && S_AXIS_DIN_TDATA_delay[498]; // rv 0 + assign S_AXIS_DIN_TDATA_in[499] = (S_AXIS_DIN_TDATA[499] !== 1'bz) && S_AXIS_DIN_TDATA_delay[499]; // rv 0 + assign S_AXIS_DIN_TDATA_in[49] = (S_AXIS_DIN_TDATA[49] !== 1'bz) && S_AXIS_DIN_TDATA_delay[49]; // rv 0 + assign S_AXIS_DIN_TDATA_in[4] = (S_AXIS_DIN_TDATA[4] !== 1'bz) && S_AXIS_DIN_TDATA_delay[4]; // rv 0 + assign S_AXIS_DIN_TDATA_in[500] = (S_AXIS_DIN_TDATA[500] !== 1'bz) && S_AXIS_DIN_TDATA_delay[500]; // rv 0 + assign S_AXIS_DIN_TDATA_in[501] = (S_AXIS_DIN_TDATA[501] !== 1'bz) && S_AXIS_DIN_TDATA_delay[501]; // rv 0 + assign S_AXIS_DIN_TDATA_in[502] = (S_AXIS_DIN_TDATA[502] !== 1'bz) && S_AXIS_DIN_TDATA_delay[502]; // rv 0 + assign S_AXIS_DIN_TDATA_in[503] = (S_AXIS_DIN_TDATA[503] !== 1'bz) && S_AXIS_DIN_TDATA_delay[503]; // rv 0 + assign S_AXIS_DIN_TDATA_in[504] = (S_AXIS_DIN_TDATA[504] !== 1'bz) && S_AXIS_DIN_TDATA_delay[504]; // rv 0 + assign S_AXIS_DIN_TDATA_in[505] = (S_AXIS_DIN_TDATA[505] !== 1'bz) && S_AXIS_DIN_TDATA_delay[505]; // rv 0 + assign S_AXIS_DIN_TDATA_in[506] = (S_AXIS_DIN_TDATA[506] !== 1'bz) && S_AXIS_DIN_TDATA_delay[506]; // rv 0 + assign S_AXIS_DIN_TDATA_in[507] = (S_AXIS_DIN_TDATA[507] !== 1'bz) && S_AXIS_DIN_TDATA_delay[507]; // rv 0 + assign S_AXIS_DIN_TDATA_in[508] = (S_AXIS_DIN_TDATA[508] !== 1'bz) && S_AXIS_DIN_TDATA_delay[508]; // rv 0 + assign S_AXIS_DIN_TDATA_in[509] = (S_AXIS_DIN_TDATA[509] !== 1'bz) && S_AXIS_DIN_TDATA_delay[509]; // rv 0 + assign S_AXIS_DIN_TDATA_in[50] = (S_AXIS_DIN_TDATA[50] !== 1'bz) && S_AXIS_DIN_TDATA_delay[50]; // rv 0 + assign S_AXIS_DIN_TDATA_in[510] = (S_AXIS_DIN_TDATA[510] !== 1'bz) && S_AXIS_DIN_TDATA_delay[510]; // rv 0 + assign S_AXIS_DIN_TDATA_in[511] = (S_AXIS_DIN_TDATA[511] !== 1'bz) && S_AXIS_DIN_TDATA_delay[511]; // rv 0 + assign S_AXIS_DIN_TDATA_in[51] = (S_AXIS_DIN_TDATA[51] !== 1'bz) && S_AXIS_DIN_TDATA_delay[51]; // rv 0 + assign S_AXIS_DIN_TDATA_in[52] = (S_AXIS_DIN_TDATA[52] !== 1'bz) && S_AXIS_DIN_TDATA_delay[52]; // rv 0 + assign S_AXIS_DIN_TDATA_in[53] = (S_AXIS_DIN_TDATA[53] !== 1'bz) && S_AXIS_DIN_TDATA_delay[53]; // rv 0 + assign S_AXIS_DIN_TDATA_in[54] = (S_AXIS_DIN_TDATA[54] !== 1'bz) && S_AXIS_DIN_TDATA_delay[54]; // rv 0 + assign S_AXIS_DIN_TDATA_in[55] = (S_AXIS_DIN_TDATA[55] !== 1'bz) && S_AXIS_DIN_TDATA_delay[55]; // rv 0 + assign S_AXIS_DIN_TDATA_in[56] = (S_AXIS_DIN_TDATA[56] !== 1'bz) && S_AXIS_DIN_TDATA_delay[56]; // rv 0 + assign S_AXIS_DIN_TDATA_in[57] = (S_AXIS_DIN_TDATA[57] !== 1'bz) && S_AXIS_DIN_TDATA_delay[57]; // rv 0 + assign S_AXIS_DIN_TDATA_in[58] = (S_AXIS_DIN_TDATA[58] !== 1'bz) && S_AXIS_DIN_TDATA_delay[58]; // rv 0 + assign S_AXIS_DIN_TDATA_in[59] = (S_AXIS_DIN_TDATA[59] !== 1'bz) && S_AXIS_DIN_TDATA_delay[59]; // rv 0 + assign S_AXIS_DIN_TDATA_in[5] = (S_AXIS_DIN_TDATA[5] !== 1'bz) && S_AXIS_DIN_TDATA_delay[5]; // rv 0 + assign S_AXIS_DIN_TDATA_in[60] = (S_AXIS_DIN_TDATA[60] !== 1'bz) && S_AXIS_DIN_TDATA_delay[60]; // rv 0 + assign S_AXIS_DIN_TDATA_in[61] = (S_AXIS_DIN_TDATA[61] !== 1'bz) && S_AXIS_DIN_TDATA_delay[61]; // rv 0 + assign S_AXIS_DIN_TDATA_in[62] = (S_AXIS_DIN_TDATA[62] !== 1'bz) && S_AXIS_DIN_TDATA_delay[62]; // rv 0 + assign S_AXIS_DIN_TDATA_in[63] = (S_AXIS_DIN_TDATA[63] !== 1'bz) && S_AXIS_DIN_TDATA_delay[63]; // rv 0 + assign S_AXIS_DIN_TDATA_in[64] = (S_AXIS_DIN_TDATA[64] !== 1'bz) && S_AXIS_DIN_TDATA_delay[64]; // rv 0 + assign S_AXIS_DIN_TDATA_in[65] = (S_AXIS_DIN_TDATA[65] !== 1'bz) && S_AXIS_DIN_TDATA_delay[65]; // rv 0 + assign S_AXIS_DIN_TDATA_in[66] = (S_AXIS_DIN_TDATA[66] !== 1'bz) && S_AXIS_DIN_TDATA_delay[66]; // rv 0 + assign S_AXIS_DIN_TDATA_in[67] = (S_AXIS_DIN_TDATA[67] !== 1'bz) && S_AXIS_DIN_TDATA_delay[67]; // rv 0 + assign S_AXIS_DIN_TDATA_in[68] = (S_AXIS_DIN_TDATA[68] !== 1'bz) && S_AXIS_DIN_TDATA_delay[68]; // rv 0 + assign S_AXIS_DIN_TDATA_in[69] = (S_AXIS_DIN_TDATA[69] !== 1'bz) && S_AXIS_DIN_TDATA_delay[69]; // rv 0 + assign S_AXIS_DIN_TDATA_in[6] = (S_AXIS_DIN_TDATA[6] !== 1'bz) && S_AXIS_DIN_TDATA_delay[6]; // rv 0 + assign S_AXIS_DIN_TDATA_in[70] = (S_AXIS_DIN_TDATA[70] !== 1'bz) && S_AXIS_DIN_TDATA_delay[70]; // rv 0 + assign S_AXIS_DIN_TDATA_in[71] = (S_AXIS_DIN_TDATA[71] !== 1'bz) && S_AXIS_DIN_TDATA_delay[71]; // rv 0 + assign S_AXIS_DIN_TDATA_in[72] = (S_AXIS_DIN_TDATA[72] !== 1'bz) && S_AXIS_DIN_TDATA_delay[72]; // rv 0 + assign S_AXIS_DIN_TDATA_in[73] = (S_AXIS_DIN_TDATA[73] !== 1'bz) && S_AXIS_DIN_TDATA_delay[73]; // rv 0 + assign S_AXIS_DIN_TDATA_in[74] = (S_AXIS_DIN_TDATA[74] !== 1'bz) && S_AXIS_DIN_TDATA_delay[74]; // rv 0 + assign S_AXIS_DIN_TDATA_in[75] = (S_AXIS_DIN_TDATA[75] !== 1'bz) && S_AXIS_DIN_TDATA_delay[75]; // rv 0 + assign S_AXIS_DIN_TDATA_in[76] = (S_AXIS_DIN_TDATA[76] !== 1'bz) && S_AXIS_DIN_TDATA_delay[76]; // rv 0 + assign S_AXIS_DIN_TDATA_in[77] = (S_AXIS_DIN_TDATA[77] !== 1'bz) && S_AXIS_DIN_TDATA_delay[77]; // rv 0 + assign S_AXIS_DIN_TDATA_in[78] = (S_AXIS_DIN_TDATA[78] !== 1'bz) && S_AXIS_DIN_TDATA_delay[78]; // rv 0 + assign S_AXIS_DIN_TDATA_in[79] = (S_AXIS_DIN_TDATA[79] !== 1'bz) && S_AXIS_DIN_TDATA_delay[79]; // rv 0 + assign S_AXIS_DIN_TDATA_in[7] = (S_AXIS_DIN_TDATA[7] !== 1'bz) && S_AXIS_DIN_TDATA_delay[7]; // rv 0 + assign S_AXIS_DIN_TDATA_in[80] = (S_AXIS_DIN_TDATA[80] !== 1'bz) && S_AXIS_DIN_TDATA_delay[80]; // rv 0 + assign S_AXIS_DIN_TDATA_in[81] = (S_AXIS_DIN_TDATA[81] !== 1'bz) && S_AXIS_DIN_TDATA_delay[81]; // rv 0 + assign S_AXIS_DIN_TDATA_in[82] = (S_AXIS_DIN_TDATA[82] !== 1'bz) && S_AXIS_DIN_TDATA_delay[82]; // rv 0 + assign S_AXIS_DIN_TDATA_in[83] = (S_AXIS_DIN_TDATA[83] !== 1'bz) && S_AXIS_DIN_TDATA_delay[83]; // rv 0 + assign S_AXIS_DIN_TDATA_in[84] = (S_AXIS_DIN_TDATA[84] !== 1'bz) && S_AXIS_DIN_TDATA_delay[84]; // rv 0 + assign S_AXIS_DIN_TDATA_in[85] = (S_AXIS_DIN_TDATA[85] !== 1'bz) && S_AXIS_DIN_TDATA_delay[85]; // rv 0 + assign S_AXIS_DIN_TDATA_in[86] = (S_AXIS_DIN_TDATA[86] !== 1'bz) && S_AXIS_DIN_TDATA_delay[86]; // rv 0 + assign S_AXIS_DIN_TDATA_in[87] = (S_AXIS_DIN_TDATA[87] !== 1'bz) && S_AXIS_DIN_TDATA_delay[87]; // rv 0 + assign S_AXIS_DIN_TDATA_in[88] = (S_AXIS_DIN_TDATA[88] !== 1'bz) && S_AXIS_DIN_TDATA_delay[88]; // rv 0 + assign S_AXIS_DIN_TDATA_in[89] = (S_AXIS_DIN_TDATA[89] !== 1'bz) && S_AXIS_DIN_TDATA_delay[89]; // rv 0 + assign S_AXIS_DIN_TDATA_in[8] = (S_AXIS_DIN_TDATA[8] !== 1'bz) && S_AXIS_DIN_TDATA_delay[8]; // rv 0 + assign S_AXIS_DIN_TDATA_in[90] = (S_AXIS_DIN_TDATA[90] !== 1'bz) && S_AXIS_DIN_TDATA_delay[90]; // rv 0 + assign S_AXIS_DIN_TDATA_in[91] = (S_AXIS_DIN_TDATA[91] !== 1'bz) && S_AXIS_DIN_TDATA_delay[91]; // rv 0 + assign S_AXIS_DIN_TDATA_in[92] = (S_AXIS_DIN_TDATA[92] !== 1'bz) && S_AXIS_DIN_TDATA_delay[92]; // rv 0 + assign S_AXIS_DIN_TDATA_in[93] = (S_AXIS_DIN_TDATA[93] !== 1'bz) && S_AXIS_DIN_TDATA_delay[93]; // rv 0 + assign S_AXIS_DIN_TDATA_in[94] = (S_AXIS_DIN_TDATA[94] !== 1'bz) && S_AXIS_DIN_TDATA_delay[94]; // rv 0 + assign S_AXIS_DIN_TDATA_in[95] = (S_AXIS_DIN_TDATA[95] !== 1'bz) && S_AXIS_DIN_TDATA_delay[95]; // rv 0 + assign S_AXIS_DIN_TDATA_in[96] = (S_AXIS_DIN_TDATA[96] !== 1'bz) && S_AXIS_DIN_TDATA_delay[96]; // rv 0 + assign S_AXIS_DIN_TDATA_in[97] = (S_AXIS_DIN_TDATA[97] !== 1'bz) && S_AXIS_DIN_TDATA_delay[97]; // rv 0 + assign S_AXIS_DIN_TDATA_in[98] = (S_AXIS_DIN_TDATA[98] !== 1'bz) && S_AXIS_DIN_TDATA_delay[98]; // rv 0 + assign S_AXIS_DIN_TDATA_in[99] = (S_AXIS_DIN_TDATA[99] !== 1'bz) && S_AXIS_DIN_TDATA_delay[99]; // rv 0 + assign S_AXIS_DIN_TDATA_in[9] = (S_AXIS_DIN_TDATA[9] !== 1'bz) && S_AXIS_DIN_TDATA_delay[9]; // rv 0 + assign S_AXIS_DIN_TLAST_in = (S_AXIS_DIN_TLAST !== 1'bz) && S_AXIS_DIN_TLAST_delay; // rv 0 + assign S_AXIS_DIN_TVALID_in = (S_AXIS_DIN_TVALID !== 1'bz) && S_AXIS_DIN_TVALID_delay; // rv 0 + assign S_AXIS_DIN_WORDS_ACLK_in = (S_AXIS_DIN_WORDS_ACLK !== 1'bz) && S_AXIS_DIN_WORDS_ACLK_delay; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[0] = (S_AXIS_DIN_WORDS_TDATA[0] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[0]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[10] = (S_AXIS_DIN_WORDS_TDATA[10] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[10]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[11] = (S_AXIS_DIN_WORDS_TDATA[11] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[11]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[12] = (S_AXIS_DIN_WORDS_TDATA[12] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[12]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[13] = (S_AXIS_DIN_WORDS_TDATA[13] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[13]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[14] = (S_AXIS_DIN_WORDS_TDATA[14] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[14]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[15] = (S_AXIS_DIN_WORDS_TDATA[15] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[15]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[16] = (S_AXIS_DIN_WORDS_TDATA[16] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[16]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[17] = (S_AXIS_DIN_WORDS_TDATA[17] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[17]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[18] = (S_AXIS_DIN_WORDS_TDATA[18] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[18]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[19] = (S_AXIS_DIN_WORDS_TDATA[19] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[19]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[1] = (S_AXIS_DIN_WORDS_TDATA[1] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[1]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[20] = (S_AXIS_DIN_WORDS_TDATA[20] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[20]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[21] = (S_AXIS_DIN_WORDS_TDATA[21] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[21]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[22] = (S_AXIS_DIN_WORDS_TDATA[22] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[22]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[23] = (S_AXIS_DIN_WORDS_TDATA[23] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[23]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[24] = (S_AXIS_DIN_WORDS_TDATA[24] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[24]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[25] = (S_AXIS_DIN_WORDS_TDATA[25] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[25]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[26] = (S_AXIS_DIN_WORDS_TDATA[26] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[26]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[27] = (S_AXIS_DIN_WORDS_TDATA[27] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[27]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[28] = (S_AXIS_DIN_WORDS_TDATA[28] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[28]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[29] = (S_AXIS_DIN_WORDS_TDATA[29] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[29]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[2] = (S_AXIS_DIN_WORDS_TDATA[2] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[2]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[30] = (S_AXIS_DIN_WORDS_TDATA[30] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[30]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[31] = (S_AXIS_DIN_WORDS_TDATA[31] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[31]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[3] = (S_AXIS_DIN_WORDS_TDATA[3] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[3]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[4] = (S_AXIS_DIN_WORDS_TDATA[4] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[4]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[5] = (S_AXIS_DIN_WORDS_TDATA[5] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[5]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[6] = (S_AXIS_DIN_WORDS_TDATA[6] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[6]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[7] = (S_AXIS_DIN_WORDS_TDATA[7] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[7]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[8] = (S_AXIS_DIN_WORDS_TDATA[8] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[8]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[9] = (S_AXIS_DIN_WORDS_TDATA[9] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA_delay[9]; // rv 0 + assign S_AXIS_DIN_WORDS_TLAST_in = (S_AXIS_DIN_WORDS_TLAST !== 1'bz) && S_AXIS_DIN_WORDS_TLAST_delay; // rv 0 + assign S_AXIS_DIN_WORDS_TVALID_in = (S_AXIS_DIN_WORDS_TVALID !== 1'bz) && S_AXIS_DIN_WORDS_TVALID_delay; // rv 0 + assign S_AXIS_DOUT_WORDS_ACLK_in = (S_AXIS_DOUT_WORDS_ACLK !== 1'bz) && S_AXIS_DOUT_WORDS_ACLK_delay; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[0] = (S_AXIS_DOUT_WORDS_TDATA[0] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[0]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[10] = (S_AXIS_DOUT_WORDS_TDATA[10] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[10]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[11] = (S_AXIS_DOUT_WORDS_TDATA[11] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[11]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[12] = (S_AXIS_DOUT_WORDS_TDATA[12] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[12]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[13] = (S_AXIS_DOUT_WORDS_TDATA[13] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[13]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[14] = (S_AXIS_DOUT_WORDS_TDATA[14] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[14]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[15] = (S_AXIS_DOUT_WORDS_TDATA[15] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[15]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[16] = (S_AXIS_DOUT_WORDS_TDATA[16] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[16]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[17] = (S_AXIS_DOUT_WORDS_TDATA[17] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[17]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[18] = (S_AXIS_DOUT_WORDS_TDATA[18] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[18]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[19] = (S_AXIS_DOUT_WORDS_TDATA[19] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[19]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[1] = (S_AXIS_DOUT_WORDS_TDATA[1] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[1]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[20] = (S_AXIS_DOUT_WORDS_TDATA[20] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[20]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[21] = (S_AXIS_DOUT_WORDS_TDATA[21] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[21]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[22] = (S_AXIS_DOUT_WORDS_TDATA[22] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[22]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[23] = (S_AXIS_DOUT_WORDS_TDATA[23] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[23]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[24] = (S_AXIS_DOUT_WORDS_TDATA[24] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[24]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[25] = (S_AXIS_DOUT_WORDS_TDATA[25] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[25]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[26] = (S_AXIS_DOUT_WORDS_TDATA[26] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[26]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[27] = (S_AXIS_DOUT_WORDS_TDATA[27] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[27]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[28] = (S_AXIS_DOUT_WORDS_TDATA[28] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[28]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[29] = (S_AXIS_DOUT_WORDS_TDATA[29] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[29]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[2] = (S_AXIS_DOUT_WORDS_TDATA[2] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[2]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[30] = (S_AXIS_DOUT_WORDS_TDATA[30] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[30]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[31] = (S_AXIS_DOUT_WORDS_TDATA[31] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[31]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[3] = (S_AXIS_DOUT_WORDS_TDATA[3] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[3]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[4] = (S_AXIS_DOUT_WORDS_TDATA[4] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[4]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[5] = (S_AXIS_DOUT_WORDS_TDATA[5] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[5]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[6] = (S_AXIS_DOUT_WORDS_TDATA[6] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[6]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[7] = (S_AXIS_DOUT_WORDS_TDATA[7] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[7]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[8] = (S_AXIS_DOUT_WORDS_TDATA[8] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[8]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[9] = (S_AXIS_DOUT_WORDS_TDATA[9] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA_delay[9]; // rv 0 + assign S_AXIS_DOUT_WORDS_TLAST_in = (S_AXIS_DOUT_WORDS_TLAST !== 1'bz) && S_AXIS_DOUT_WORDS_TLAST_delay; // rv 0 + assign S_AXIS_DOUT_WORDS_TVALID_in = (S_AXIS_DOUT_WORDS_TVALID !== 1'bz) && S_AXIS_DOUT_WORDS_TVALID_delay; // rv 0 + assign S_AXI_ACLK_in = (S_AXI_ACLK !== 1'bz) && S_AXI_ACLK_delay; // rv 0 + assign S_AXI_ARADDR_in[0] = (S_AXI_ARADDR[0] !== 1'bz) && S_AXI_ARADDR_delay[0]; // rv 0 + assign S_AXI_ARADDR_in[10] = (S_AXI_ARADDR[10] !== 1'bz) && S_AXI_ARADDR_delay[10]; // rv 0 + assign S_AXI_ARADDR_in[11] = (S_AXI_ARADDR[11] !== 1'bz) && S_AXI_ARADDR_delay[11]; // rv 0 + assign S_AXI_ARADDR_in[12] = (S_AXI_ARADDR[12] !== 1'bz) && S_AXI_ARADDR_delay[12]; // rv 0 + assign S_AXI_ARADDR_in[13] = (S_AXI_ARADDR[13] !== 1'bz) && S_AXI_ARADDR_delay[13]; // rv 0 + assign S_AXI_ARADDR_in[14] = (S_AXI_ARADDR[14] !== 1'bz) && S_AXI_ARADDR_delay[14]; // rv 0 + assign S_AXI_ARADDR_in[15] = (S_AXI_ARADDR[15] !== 1'bz) && S_AXI_ARADDR_delay[15]; // rv 0 + assign S_AXI_ARADDR_in[16] = (S_AXI_ARADDR[16] !== 1'bz) && S_AXI_ARADDR_delay[16]; // rv 0 + assign S_AXI_ARADDR_in[17] = (S_AXI_ARADDR[17] !== 1'bz) && S_AXI_ARADDR_delay[17]; // rv 0 + assign S_AXI_ARADDR_in[1] = (S_AXI_ARADDR[1] !== 1'bz) && S_AXI_ARADDR_delay[1]; // rv 0 + assign S_AXI_ARADDR_in[2] = (S_AXI_ARADDR[2] !== 1'bz) && S_AXI_ARADDR_delay[2]; // rv 0 + assign S_AXI_ARADDR_in[3] = (S_AXI_ARADDR[3] !== 1'bz) && S_AXI_ARADDR_delay[3]; // rv 0 + assign S_AXI_ARADDR_in[4] = (S_AXI_ARADDR[4] !== 1'bz) && S_AXI_ARADDR_delay[4]; // rv 0 + assign S_AXI_ARADDR_in[5] = (S_AXI_ARADDR[5] !== 1'bz) && S_AXI_ARADDR_delay[5]; // rv 0 + assign S_AXI_ARADDR_in[6] = (S_AXI_ARADDR[6] !== 1'bz) && S_AXI_ARADDR_delay[6]; // rv 0 + assign S_AXI_ARADDR_in[7] = (S_AXI_ARADDR[7] !== 1'bz) && S_AXI_ARADDR_delay[7]; // rv 0 + assign S_AXI_ARADDR_in[8] = (S_AXI_ARADDR[8] !== 1'bz) && S_AXI_ARADDR_delay[8]; // rv 0 + assign S_AXI_ARADDR_in[9] = (S_AXI_ARADDR[9] !== 1'bz) && S_AXI_ARADDR_delay[9]; // rv 0 + assign S_AXI_ARVALID_in = (S_AXI_ARVALID !== 1'bz) && S_AXI_ARVALID_delay; // rv 0 + assign S_AXI_AWADDR_in[0] = (S_AXI_AWADDR[0] !== 1'bz) && S_AXI_AWADDR_delay[0]; // rv 0 + assign S_AXI_AWADDR_in[10] = (S_AXI_AWADDR[10] !== 1'bz) && S_AXI_AWADDR_delay[10]; // rv 0 + assign S_AXI_AWADDR_in[11] = (S_AXI_AWADDR[11] !== 1'bz) && S_AXI_AWADDR_delay[11]; // rv 0 + assign S_AXI_AWADDR_in[12] = (S_AXI_AWADDR[12] !== 1'bz) && S_AXI_AWADDR_delay[12]; // rv 0 + assign S_AXI_AWADDR_in[13] = (S_AXI_AWADDR[13] !== 1'bz) && S_AXI_AWADDR_delay[13]; // rv 0 + assign S_AXI_AWADDR_in[14] = (S_AXI_AWADDR[14] !== 1'bz) && S_AXI_AWADDR_delay[14]; // rv 0 + assign S_AXI_AWADDR_in[15] = (S_AXI_AWADDR[15] !== 1'bz) && S_AXI_AWADDR_delay[15]; // rv 0 + assign S_AXI_AWADDR_in[16] = (S_AXI_AWADDR[16] !== 1'bz) && S_AXI_AWADDR_delay[16]; // rv 0 + assign S_AXI_AWADDR_in[17] = (S_AXI_AWADDR[17] !== 1'bz) && S_AXI_AWADDR_delay[17]; // rv 0 + assign S_AXI_AWADDR_in[1] = (S_AXI_AWADDR[1] !== 1'bz) && S_AXI_AWADDR_delay[1]; // rv 0 + assign S_AXI_AWADDR_in[2] = (S_AXI_AWADDR[2] !== 1'bz) && S_AXI_AWADDR_delay[2]; // rv 0 + assign S_AXI_AWADDR_in[3] = (S_AXI_AWADDR[3] !== 1'bz) && S_AXI_AWADDR_delay[3]; // rv 0 + assign S_AXI_AWADDR_in[4] = (S_AXI_AWADDR[4] !== 1'bz) && S_AXI_AWADDR_delay[4]; // rv 0 + assign S_AXI_AWADDR_in[5] = (S_AXI_AWADDR[5] !== 1'bz) && S_AXI_AWADDR_delay[5]; // rv 0 + assign S_AXI_AWADDR_in[6] = (S_AXI_AWADDR[6] !== 1'bz) && S_AXI_AWADDR_delay[6]; // rv 0 + assign S_AXI_AWADDR_in[7] = (S_AXI_AWADDR[7] !== 1'bz) && S_AXI_AWADDR_delay[7]; // rv 0 + assign S_AXI_AWADDR_in[8] = (S_AXI_AWADDR[8] !== 1'bz) && S_AXI_AWADDR_delay[8]; // rv 0 + assign S_AXI_AWADDR_in[9] = (S_AXI_AWADDR[9] !== 1'bz) && S_AXI_AWADDR_delay[9]; // rv 0 + assign S_AXI_AWVALID_in = (S_AXI_AWVALID !== 1'bz) && S_AXI_AWVALID_delay; // rv 0 + assign S_AXI_BREADY_in = (S_AXI_BREADY !== 1'bz) && S_AXI_BREADY_delay; // rv 0 + assign S_AXI_RREADY_in = (S_AXI_RREADY !== 1'bz) && S_AXI_RREADY_delay; // rv 0 + assign S_AXI_WDATA_in[0] = (S_AXI_WDATA[0] !== 1'bz) && S_AXI_WDATA_delay[0]; // rv 0 + assign S_AXI_WDATA_in[10] = (S_AXI_WDATA[10] !== 1'bz) && S_AXI_WDATA_delay[10]; // rv 0 + assign S_AXI_WDATA_in[11] = (S_AXI_WDATA[11] !== 1'bz) && S_AXI_WDATA_delay[11]; // rv 0 + assign S_AXI_WDATA_in[12] = (S_AXI_WDATA[12] !== 1'bz) && S_AXI_WDATA_delay[12]; // rv 0 + assign S_AXI_WDATA_in[13] = (S_AXI_WDATA[13] !== 1'bz) && S_AXI_WDATA_delay[13]; // rv 0 + assign S_AXI_WDATA_in[14] = (S_AXI_WDATA[14] !== 1'bz) && S_AXI_WDATA_delay[14]; // rv 0 + assign S_AXI_WDATA_in[15] = (S_AXI_WDATA[15] !== 1'bz) && S_AXI_WDATA_delay[15]; // rv 0 + assign S_AXI_WDATA_in[16] = (S_AXI_WDATA[16] !== 1'bz) && S_AXI_WDATA_delay[16]; // rv 0 + assign S_AXI_WDATA_in[17] = (S_AXI_WDATA[17] !== 1'bz) && S_AXI_WDATA_delay[17]; // rv 0 + assign S_AXI_WDATA_in[18] = (S_AXI_WDATA[18] !== 1'bz) && S_AXI_WDATA_delay[18]; // rv 0 + assign S_AXI_WDATA_in[19] = (S_AXI_WDATA[19] !== 1'bz) && S_AXI_WDATA_delay[19]; // rv 0 + assign S_AXI_WDATA_in[1] = (S_AXI_WDATA[1] !== 1'bz) && S_AXI_WDATA_delay[1]; // rv 0 + assign S_AXI_WDATA_in[20] = (S_AXI_WDATA[20] !== 1'bz) && S_AXI_WDATA_delay[20]; // rv 0 + assign S_AXI_WDATA_in[21] = (S_AXI_WDATA[21] !== 1'bz) && S_AXI_WDATA_delay[21]; // rv 0 + assign S_AXI_WDATA_in[22] = (S_AXI_WDATA[22] !== 1'bz) && S_AXI_WDATA_delay[22]; // rv 0 + assign S_AXI_WDATA_in[23] = (S_AXI_WDATA[23] !== 1'bz) && S_AXI_WDATA_delay[23]; // rv 0 + assign S_AXI_WDATA_in[24] = (S_AXI_WDATA[24] !== 1'bz) && S_AXI_WDATA_delay[24]; // rv 0 + assign S_AXI_WDATA_in[25] = (S_AXI_WDATA[25] !== 1'bz) && S_AXI_WDATA_delay[25]; // rv 0 + assign S_AXI_WDATA_in[26] = (S_AXI_WDATA[26] !== 1'bz) && S_AXI_WDATA_delay[26]; // rv 0 + assign S_AXI_WDATA_in[27] = (S_AXI_WDATA[27] !== 1'bz) && S_AXI_WDATA_delay[27]; // rv 0 + assign S_AXI_WDATA_in[28] = (S_AXI_WDATA[28] !== 1'bz) && S_AXI_WDATA_delay[28]; // rv 0 + assign S_AXI_WDATA_in[29] = (S_AXI_WDATA[29] !== 1'bz) && S_AXI_WDATA_delay[29]; // rv 0 + assign S_AXI_WDATA_in[2] = (S_AXI_WDATA[2] !== 1'bz) && S_AXI_WDATA_delay[2]; // rv 0 + assign S_AXI_WDATA_in[30] = (S_AXI_WDATA[30] !== 1'bz) && S_AXI_WDATA_delay[30]; // rv 0 + assign S_AXI_WDATA_in[31] = (S_AXI_WDATA[31] !== 1'bz) && S_AXI_WDATA_delay[31]; // rv 0 + assign S_AXI_WDATA_in[3] = (S_AXI_WDATA[3] !== 1'bz) && S_AXI_WDATA_delay[3]; // rv 0 + assign S_AXI_WDATA_in[4] = (S_AXI_WDATA[4] !== 1'bz) && S_AXI_WDATA_delay[4]; // rv 0 + assign S_AXI_WDATA_in[5] = (S_AXI_WDATA[5] !== 1'bz) && S_AXI_WDATA_delay[5]; // rv 0 + assign S_AXI_WDATA_in[6] = (S_AXI_WDATA[6] !== 1'bz) && S_AXI_WDATA_delay[6]; // rv 0 + assign S_AXI_WDATA_in[7] = (S_AXI_WDATA[7] !== 1'bz) && S_AXI_WDATA_delay[7]; // rv 0 + assign S_AXI_WDATA_in[8] = (S_AXI_WDATA[8] !== 1'bz) && S_AXI_WDATA_delay[8]; // rv 0 + assign S_AXI_WDATA_in[9] = (S_AXI_WDATA[9] !== 1'bz) && S_AXI_WDATA_delay[9]; // rv 0 + assign S_AXI_WVALID_in = (S_AXI_WVALID !== 1'bz) && S_AXI_WVALID_delay; // rv 0 +`else + assign CORE_CLK_in = (CORE_CLK !== 1'bz) && CORE_CLK; // rv 0 + assign DEBUG_EN_in = (DEBUG_EN === 1'bz) || DEBUG_EN; // rv 1 + assign M_AXIS_DOUT_ACLK_in = (M_AXIS_DOUT_ACLK !== 1'bz) && M_AXIS_DOUT_ACLK; // rv 0 + assign M_AXIS_DOUT_TREADY_in = (M_AXIS_DOUT_TREADY !== 1'bz) && M_AXIS_DOUT_TREADY; // rv 0 + assign M_AXIS_STATUS_ACLK_in = (M_AXIS_STATUS_ACLK !== 1'bz) && M_AXIS_STATUS_ACLK; // rv 0 + assign M_AXIS_STATUS_TREADY_in = (M_AXIS_STATUS_TREADY !== 1'bz) && M_AXIS_STATUS_TREADY; // rv 0 + assign S_AXIS_CTRL_ACLK_in = (S_AXIS_CTRL_ACLK !== 1'bz) && S_AXIS_CTRL_ACLK; // rv 0 + assign S_AXIS_CTRL_TDATA_in[0] = (S_AXIS_CTRL_TDATA[0] !== 1'bz) && S_AXIS_CTRL_TDATA[0]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[10] = (S_AXIS_CTRL_TDATA[10] !== 1'bz) && S_AXIS_CTRL_TDATA[10]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[11] = (S_AXIS_CTRL_TDATA[11] !== 1'bz) && S_AXIS_CTRL_TDATA[11]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[12] = (S_AXIS_CTRL_TDATA[12] !== 1'bz) && S_AXIS_CTRL_TDATA[12]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[13] = (S_AXIS_CTRL_TDATA[13] !== 1'bz) && S_AXIS_CTRL_TDATA[13]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[14] = (S_AXIS_CTRL_TDATA[14] !== 1'bz) && S_AXIS_CTRL_TDATA[14]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[15] = (S_AXIS_CTRL_TDATA[15] !== 1'bz) && S_AXIS_CTRL_TDATA[15]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[16] = (S_AXIS_CTRL_TDATA[16] !== 1'bz) && S_AXIS_CTRL_TDATA[16]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[17] = (S_AXIS_CTRL_TDATA[17] !== 1'bz) && S_AXIS_CTRL_TDATA[17]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[18] = (S_AXIS_CTRL_TDATA[18] !== 1'bz) && S_AXIS_CTRL_TDATA[18]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[19] = (S_AXIS_CTRL_TDATA[19] !== 1'bz) && S_AXIS_CTRL_TDATA[19]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[1] = (S_AXIS_CTRL_TDATA[1] !== 1'bz) && S_AXIS_CTRL_TDATA[1]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[20] = (S_AXIS_CTRL_TDATA[20] !== 1'bz) && S_AXIS_CTRL_TDATA[20]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[21] = (S_AXIS_CTRL_TDATA[21] !== 1'bz) && S_AXIS_CTRL_TDATA[21]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[22] = (S_AXIS_CTRL_TDATA[22] !== 1'bz) && S_AXIS_CTRL_TDATA[22]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[23] = (S_AXIS_CTRL_TDATA[23] !== 1'bz) && S_AXIS_CTRL_TDATA[23]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[24] = (S_AXIS_CTRL_TDATA[24] !== 1'bz) && S_AXIS_CTRL_TDATA[24]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[25] = (S_AXIS_CTRL_TDATA[25] !== 1'bz) && S_AXIS_CTRL_TDATA[25]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[26] = (S_AXIS_CTRL_TDATA[26] !== 1'bz) && S_AXIS_CTRL_TDATA[26]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[27] = (S_AXIS_CTRL_TDATA[27] !== 1'bz) && S_AXIS_CTRL_TDATA[27]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[28] = (S_AXIS_CTRL_TDATA[28] !== 1'bz) && S_AXIS_CTRL_TDATA[28]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[29] = (S_AXIS_CTRL_TDATA[29] !== 1'bz) && S_AXIS_CTRL_TDATA[29]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[2] = (S_AXIS_CTRL_TDATA[2] !== 1'bz) && S_AXIS_CTRL_TDATA[2]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[30] = (S_AXIS_CTRL_TDATA[30] !== 1'bz) && S_AXIS_CTRL_TDATA[30]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[31] = (S_AXIS_CTRL_TDATA[31] !== 1'bz) && S_AXIS_CTRL_TDATA[31]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[3] = (S_AXIS_CTRL_TDATA[3] !== 1'bz) && S_AXIS_CTRL_TDATA[3]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[4] = (S_AXIS_CTRL_TDATA[4] !== 1'bz) && S_AXIS_CTRL_TDATA[4]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[5] = (S_AXIS_CTRL_TDATA[5] !== 1'bz) && S_AXIS_CTRL_TDATA[5]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[6] = (S_AXIS_CTRL_TDATA[6] !== 1'bz) && S_AXIS_CTRL_TDATA[6]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[7] = (S_AXIS_CTRL_TDATA[7] !== 1'bz) && S_AXIS_CTRL_TDATA[7]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[8] = (S_AXIS_CTRL_TDATA[8] !== 1'bz) && S_AXIS_CTRL_TDATA[8]; // rv 0 + assign S_AXIS_CTRL_TDATA_in[9] = (S_AXIS_CTRL_TDATA[9] !== 1'bz) && S_AXIS_CTRL_TDATA[9]; // rv 0 + assign S_AXIS_CTRL_TVALID_in = (S_AXIS_CTRL_TVALID !== 1'bz) && S_AXIS_CTRL_TVALID; // rv 0 + assign S_AXIS_DIN_ACLK_in = (S_AXIS_DIN_ACLK !== 1'bz) && S_AXIS_DIN_ACLK; // rv 0 + assign S_AXIS_DIN_TDATA_in[0] = (S_AXIS_DIN_TDATA[0] !== 1'bz) && S_AXIS_DIN_TDATA[0]; // rv 0 + assign S_AXIS_DIN_TDATA_in[100] = (S_AXIS_DIN_TDATA[100] !== 1'bz) && S_AXIS_DIN_TDATA[100]; // rv 0 + assign S_AXIS_DIN_TDATA_in[101] = (S_AXIS_DIN_TDATA[101] !== 1'bz) && S_AXIS_DIN_TDATA[101]; // rv 0 + assign S_AXIS_DIN_TDATA_in[102] = (S_AXIS_DIN_TDATA[102] !== 1'bz) && S_AXIS_DIN_TDATA[102]; // rv 0 + assign S_AXIS_DIN_TDATA_in[103] = (S_AXIS_DIN_TDATA[103] !== 1'bz) && S_AXIS_DIN_TDATA[103]; // rv 0 + assign S_AXIS_DIN_TDATA_in[104] = (S_AXIS_DIN_TDATA[104] !== 1'bz) && S_AXIS_DIN_TDATA[104]; // rv 0 + assign S_AXIS_DIN_TDATA_in[105] = (S_AXIS_DIN_TDATA[105] !== 1'bz) && S_AXIS_DIN_TDATA[105]; // rv 0 + assign S_AXIS_DIN_TDATA_in[106] = (S_AXIS_DIN_TDATA[106] !== 1'bz) && S_AXIS_DIN_TDATA[106]; // rv 0 + assign S_AXIS_DIN_TDATA_in[107] = (S_AXIS_DIN_TDATA[107] !== 1'bz) && S_AXIS_DIN_TDATA[107]; // rv 0 + assign S_AXIS_DIN_TDATA_in[108] = (S_AXIS_DIN_TDATA[108] !== 1'bz) && S_AXIS_DIN_TDATA[108]; // rv 0 + assign S_AXIS_DIN_TDATA_in[109] = (S_AXIS_DIN_TDATA[109] !== 1'bz) && S_AXIS_DIN_TDATA[109]; // rv 0 + assign S_AXIS_DIN_TDATA_in[10] = (S_AXIS_DIN_TDATA[10] !== 1'bz) && S_AXIS_DIN_TDATA[10]; // rv 0 + assign S_AXIS_DIN_TDATA_in[110] = (S_AXIS_DIN_TDATA[110] !== 1'bz) && S_AXIS_DIN_TDATA[110]; // rv 0 + assign S_AXIS_DIN_TDATA_in[111] = (S_AXIS_DIN_TDATA[111] !== 1'bz) && S_AXIS_DIN_TDATA[111]; // rv 0 + assign S_AXIS_DIN_TDATA_in[112] = (S_AXIS_DIN_TDATA[112] !== 1'bz) && S_AXIS_DIN_TDATA[112]; // rv 0 + assign S_AXIS_DIN_TDATA_in[113] = (S_AXIS_DIN_TDATA[113] !== 1'bz) && S_AXIS_DIN_TDATA[113]; // rv 0 + assign S_AXIS_DIN_TDATA_in[114] = (S_AXIS_DIN_TDATA[114] !== 1'bz) && S_AXIS_DIN_TDATA[114]; // rv 0 + assign S_AXIS_DIN_TDATA_in[115] = (S_AXIS_DIN_TDATA[115] !== 1'bz) && S_AXIS_DIN_TDATA[115]; // rv 0 + assign S_AXIS_DIN_TDATA_in[116] = (S_AXIS_DIN_TDATA[116] !== 1'bz) && S_AXIS_DIN_TDATA[116]; // rv 0 + assign S_AXIS_DIN_TDATA_in[117] = (S_AXIS_DIN_TDATA[117] !== 1'bz) && S_AXIS_DIN_TDATA[117]; // rv 0 + assign S_AXIS_DIN_TDATA_in[118] = (S_AXIS_DIN_TDATA[118] !== 1'bz) && S_AXIS_DIN_TDATA[118]; // rv 0 + assign S_AXIS_DIN_TDATA_in[119] = (S_AXIS_DIN_TDATA[119] !== 1'bz) && S_AXIS_DIN_TDATA[119]; // rv 0 + assign S_AXIS_DIN_TDATA_in[11] = (S_AXIS_DIN_TDATA[11] !== 1'bz) && S_AXIS_DIN_TDATA[11]; // rv 0 + assign S_AXIS_DIN_TDATA_in[120] = (S_AXIS_DIN_TDATA[120] !== 1'bz) && S_AXIS_DIN_TDATA[120]; // rv 0 + assign S_AXIS_DIN_TDATA_in[121] = (S_AXIS_DIN_TDATA[121] !== 1'bz) && S_AXIS_DIN_TDATA[121]; // rv 0 + assign S_AXIS_DIN_TDATA_in[122] = (S_AXIS_DIN_TDATA[122] !== 1'bz) && S_AXIS_DIN_TDATA[122]; // rv 0 + assign S_AXIS_DIN_TDATA_in[123] = (S_AXIS_DIN_TDATA[123] !== 1'bz) && S_AXIS_DIN_TDATA[123]; // rv 0 + assign S_AXIS_DIN_TDATA_in[124] = (S_AXIS_DIN_TDATA[124] !== 1'bz) && S_AXIS_DIN_TDATA[124]; // rv 0 + assign S_AXIS_DIN_TDATA_in[125] = (S_AXIS_DIN_TDATA[125] !== 1'bz) && S_AXIS_DIN_TDATA[125]; // rv 0 + assign S_AXIS_DIN_TDATA_in[126] = (S_AXIS_DIN_TDATA[126] !== 1'bz) && S_AXIS_DIN_TDATA[126]; // rv 0 + assign S_AXIS_DIN_TDATA_in[127] = (S_AXIS_DIN_TDATA[127] !== 1'bz) && S_AXIS_DIN_TDATA[127]; // rv 0 + assign S_AXIS_DIN_TDATA_in[128] = (S_AXIS_DIN_TDATA[128] !== 1'bz) && S_AXIS_DIN_TDATA[128]; // rv 0 + assign S_AXIS_DIN_TDATA_in[129] = (S_AXIS_DIN_TDATA[129] !== 1'bz) && S_AXIS_DIN_TDATA[129]; // rv 0 + assign S_AXIS_DIN_TDATA_in[12] = (S_AXIS_DIN_TDATA[12] !== 1'bz) && S_AXIS_DIN_TDATA[12]; // rv 0 + assign S_AXIS_DIN_TDATA_in[130] = (S_AXIS_DIN_TDATA[130] !== 1'bz) && S_AXIS_DIN_TDATA[130]; // rv 0 + assign S_AXIS_DIN_TDATA_in[131] = (S_AXIS_DIN_TDATA[131] !== 1'bz) && S_AXIS_DIN_TDATA[131]; // rv 0 + assign S_AXIS_DIN_TDATA_in[132] = (S_AXIS_DIN_TDATA[132] !== 1'bz) && S_AXIS_DIN_TDATA[132]; // rv 0 + assign S_AXIS_DIN_TDATA_in[133] = (S_AXIS_DIN_TDATA[133] !== 1'bz) && S_AXIS_DIN_TDATA[133]; // rv 0 + assign S_AXIS_DIN_TDATA_in[134] = (S_AXIS_DIN_TDATA[134] !== 1'bz) && S_AXIS_DIN_TDATA[134]; // rv 0 + assign S_AXIS_DIN_TDATA_in[135] = (S_AXIS_DIN_TDATA[135] !== 1'bz) && S_AXIS_DIN_TDATA[135]; // rv 0 + assign S_AXIS_DIN_TDATA_in[136] = (S_AXIS_DIN_TDATA[136] !== 1'bz) && S_AXIS_DIN_TDATA[136]; // rv 0 + assign S_AXIS_DIN_TDATA_in[137] = (S_AXIS_DIN_TDATA[137] !== 1'bz) && S_AXIS_DIN_TDATA[137]; // rv 0 + assign S_AXIS_DIN_TDATA_in[138] = (S_AXIS_DIN_TDATA[138] !== 1'bz) && S_AXIS_DIN_TDATA[138]; // rv 0 + assign S_AXIS_DIN_TDATA_in[139] = (S_AXIS_DIN_TDATA[139] !== 1'bz) && S_AXIS_DIN_TDATA[139]; // rv 0 + assign S_AXIS_DIN_TDATA_in[13] = (S_AXIS_DIN_TDATA[13] !== 1'bz) && S_AXIS_DIN_TDATA[13]; // rv 0 + assign S_AXIS_DIN_TDATA_in[140] = (S_AXIS_DIN_TDATA[140] !== 1'bz) && S_AXIS_DIN_TDATA[140]; // rv 0 + assign S_AXIS_DIN_TDATA_in[141] = (S_AXIS_DIN_TDATA[141] !== 1'bz) && S_AXIS_DIN_TDATA[141]; // rv 0 + assign S_AXIS_DIN_TDATA_in[142] = (S_AXIS_DIN_TDATA[142] !== 1'bz) && S_AXIS_DIN_TDATA[142]; // rv 0 + assign S_AXIS_DIN_TDATA_in[143] = (S_AXIS_DIN_TDATA[143] !== 1'bz) && S_AXIS_DIN_TDATA[143]; // rv 0 + assign S_AXIS_DIN_TDATA_in[144] = (S_AXIS_DIN_TDATA[144] !== 1'bz) && S_AXIS_DIN_TDATA[144]; // rv 0 + assign S_AXIS_DIN_TDATA_in[145] = (S_AXIS_DIN_TDATA[145] !== 1'bz) && S_AXIS_DIN_TDATA[145]; // rv 0 + assign S_AXIS_DIN_TDATA_in[146] = (S_AXIS_DIN_TDATA[146] !== 1'bz) && S_AXIS_DIN_TDATA[146]; // rv 0 + assign S_AXIS_DIN_TDATA_in[147] = (S_AXIS_DIN_TDATA[147] !== 1'bz) && S_AXIS_DIN_TDATA[147]; // rv 0 + assign S_AXIS_DIN_TDATA_in[148] = (S_AXIS_DIN_TDATA[148] !== 1'bz) && S_AXIS_DIN_TDATA[148]; // rv 0 + assign S_AXIS_DIN_TDATA_in[149] = (S_AXIS_DIN_TDATA[149] !== 1'bz) && S_AXIS_DIN_TDATA[149]; // rv 0 + assign S_AXIS_DIN_TDATA_in[14] = (S_AXIS_DIN_TDATA[14] !== 1'bz) && S_AXIS_DIN_TDATA[14]; // rv 0 + assign S_AXIS_DIN_TDATA_in[150] = (S_AXIS_DIN_TDATA[150] !== 1'bz) && S_AXIS_DIN_TDATA[150]; // rv 0 + assign S_AXIS_DIN_TDATA_in[151] = (S_AXIS_DIN_TDATA[151] !== 1'bz) && S_AXIS_DIN_TDATA[151]; // rv 0 + assign S_AXIS_DIN_TDATA_in[152] = (S_AXIS_DIN_TDATA[152] !== 1'bz) && S_AXIS_DIN_TDATA[152]; // rv 0 + assign S_AXIS_DIN_TDATA_in[153] = (S_AXIS_DIN_TDATA[153] !== 1'bz) && S_AXIS_DIN_TDATA[153]; // rv 0 + assign S_AXIS_DIN_TDATA_in[154] = (S_AXIS_DIN_TDATA[154] !== 1'bz) && S_AXIS_DIN_TDATA[154]; // rv 0 + assign S_AXIS_DIN_TDATA_in[155] = (S_AXIS_DIN_TDATA[155] !== 1'bz) && S_AXIS_DIN_TDATA[155]; // rv 0 + assign S_AXIS_DIN_TDATA_in[156] = (S_AXIS_DIN_TDATA[156] !== 1'bz) && S_AXIS_DIN_TDATA[156]; // rv 0 + assign S_AXIS_DIN_TDATA_in[157] = (S_AXIS_DIN_TDATA[157] !== 1'bz) && S_AXIS_DIN_TDATA[157]; // rv 0 + assign S_AXIS_DIN_TDATA_in[158] = (S_AXIS_DIN_TDATA[158] !== 1'bz) && S_AXIS_DIN_TDATA[158]; // rv 0 + assign S_AXIS_DIN_TDATA_in[159] = (S_AXIS_DIN_TDATA[159] !== 1'bz) && S_AXIS_DIN_TDATA[159]; // rv 0 + assign S_AXIS_DIN_TDATA_in[15] = (S_AXIS_DIN_TDATA[15] !== 1'bz) && S_AXIS_DIN_TDATA[15]; // rv 0 + assign S_AXIS_DIN_TDATA_in[160] = (S_AXIS_DIN_TDATA[160] !== 1'bz) && S_AXIS_DIN_TDATA[160]; // rv 0 + assign S_AXIS_DIN_TDATA_in[161] = (S_AXIS_DIN_TDATA[161] !== 1'bz) && S_AXIS_DIN_TDATA[161]; // rv 0 + assign S_AXIS_DIN_TDATA_in[162] = (S_AXIS_DIN_TDATA[162] !== 1'bz) && S_AXIS_DIN_TDATA[162]; // rv 0 + assign S_AXIS_DIN_TDATA_in[163] = (S_AXIS_DIN_TDATA[163] !== 1'bz) && S_AXIS_DIN_TDATA[163]; // rv 0 + assign S_AXIS_DIN_TDATA_in[164] = (S_AXIS_DIN_TDATA[164] !== 1'bz) && S_AXIS_DIN_TDATA[164]; // rv 0 + assign S_AXIS_DIN_TDATA_in[165] = (S_AXIS_DIN_TDATA[165] !== 1'bz) && S_AXIS_DIN_TDATA[165]; // rv 0 + assign S_AXIS_DIN_TDATA_in[166] = (S_AXIS_DIN_TDATA[166] !== 1'bz) && S_AXIS_DIN_TDATA[166]; // rv 0 + assign S_AXIS_DIN_TDATA_in[167] = (S_AXIS_DIN_TDATA[167] !== 1'bz) && S_AXIS_DIN_TDATA[167]; // rv 0 + assign S_AXIS_DIN_TDATA_in[168] = (S_AXIS_DIN_TDATA[168] !== 1'bz) && S_AXIS_DIN_TDATA[168]; // rv 0 + assign S_AXIS_DIN_TDATA_in[169] = (S_AXIS_DIN_TDATA[169] !== 1'bz) && S_AXIS_DIN_TDATA[169]; // rv 0 + assign S_AXIS_DIN_TDATA_in[16] = (S_AXIS_DIN_TDATA[16] !== 1'bz) && S_AXIS_DIN_TDATA[16]; // rv 0 + assign S_AXIS_DIN_TDATA_in[170] = (S_AXIS_DIN_TDATA[170] !== 1'bz) && S_AXIS_DIN_TDATA[170]; // rv 0 + assign S_AXIS_DIN_TDATA_in[171] = (S_AXIS_DIN_TDATA[171] !== 1'bz) && S_AXIS_DIN_TDATA[171]; // rv 0 + assign S_AXIS_DIN_TDATA_in[172] = (S_AXIS_DIN_TDATA[172] !== 1'bz) && S_AXIS_DIN_TDATA[172]; // rv 0 + assign S_AXIS_DIN_TDATA_in[173] = (S_AXIS_DIN_TDATA[173] !== 1'bz) && S_AXIS_DIN_TDATA[173]; // rv 0 + assign S_AXIS_DIN_TDATA_in[174] = (S_AXIS_DIN_TDATA[174] !== 1'bz) && S_AXIS_DIN_TDATA[174]; // rv 0 + assign S_AXIS_DIN_TDATA_in[175] = (S_AXIS_DIN_TDATA[175] !== 1'bz) && S_AXIS_DIN_TDATA[175]; // rv 0 + assign S_AXIS_DIN_TDATA_in[176] = (S_AXIS_DIN_TDATA[176] !== 1'bz) && S_AXIS_DIN_TDATA[176]; // rv 0 + assign S_AXIS_DIN_TDATA_in[177] = (S_AXIS_DIN_TDATA[177] !== 1'bz) && S_AXIS_DIN_TDATA[177]; // rv 0 + assign S_AXIS_DIN_TDATA_in[178] = (S_AXIS_DIN_TDATA[178] !== 1'bz) && S_AXIS_DIN_TDATA[178]; // rv 0 + assign S_AXIS_DIN_TDATA_in[179] = (S_AXIS_DIN_TDATA[179] !== 1'bz) && S_AXIS_DIN_TDATA[179]; // rv 0 + assign S_AXIS_DIN_TDATA_in[17] = (S_AXIS_DIN_TDATA[17] !== 1'bz) && S_AXIS_DIN_TDATA[17]; // rv 0 + assign S_AXIS_DIN_TDATA_in[180] = (S_AXIS_DIN_TDATA[180] !== 1'bz) && S_AXIS_DIN_TDATA[180]; // rv 0 + assign S_AXIS_DIN_TDATA_in[181] = (S_AXIS_DIN_TDATA[181] !== 1'bz) && S_AXIS_DIN_TDATA[181]; // rv 0 + assign S_AXIS_DIN_TDATA_in[182] = (S_AXIS_DIN_TDATA[182] !== 1'bz) && S_AXIS_DIN_TDATA[182]; // rv 0 + assign S_AXIS_DIN_TDATA_in[183] = (S_AXIS_DIN_TDATA[183] !== 1'bz) && S_AXIS_DIN_TDATA[183]; // rv 0 + assign S_AXIS_DIN_TDATA_in[184] = (S_AXIS_DIN_TDATA[184] !== 1'bz) && S_AXIS_DIN_TDATA[184]; // rv 0 + assign S_AXIS_DIN_TDATA_in[185] = (S_AXIS_DIN_TDATA[185] !== 1'bz) && S_AXIS_DIN_TDATA[185]; // rv 0 + assign S_AXIS_DIN_TDATA_in[186] = (S_AXIS_DIN_TDATA[186] !== 1'bz) && S_AXIS_DIN_TDATA[186]; // rv 0 + assign S_AXIS_DIN_TDATA_in[187] = (S_AXIS_DIN_TDATA[187] !== 1'bz) && S_AXIS_DIN_TDATA[187]; // rv 0 + assign S_AXIS_DIN_TDATA_in[188] = (S_AXIS_DIN_TDATA[188] !== 1'bz) && S_AXIS_DIN_TDATA[188]; // rv 0 + assign S_AXIS_DIN_TDATA_in[189] = (S_AXIS_DIN_TDATA[189] !== 1'bz) && S_AXIS_DIN_TDATA[189]; // rv 0 + assign S_AXIS_DIN_TDATA_in[18] = (S_AXIS_DIN_TDATA[18] !== 1'bz) && S_AXIS_DIN_TDATA[18]; // rv 0 + assign S_AXIS_DIN_TDATA_in[190] = (S_AXIS_DIN_TDATA[190] !== 1'bz) && S_AXIS_DIN_TDATA[190]; // rv 0 + assign S_AXIS_DIN_TDATA_in[191] = (S_AXIS_DIN_TDATA[191] !== 1'bz) && S_AXIS_DIN_TDATA[191]; // rv 0 + assign S_AXIS_DIN_TDATA_in[192] = (S_AXIS_DIN_TDATA[192] !== 1'bz) && S_AXIS_DIN_TDATA[192]; // rv 0 + assign S_AXIS_DIN_TDATA_in[193] = (S_AXIS_DIN_TDATA[193] !== 1'bz) && S_AXIS_DIN_TDATA[193]; // rv 0 + assign S_AXIS_DIN_TDATA_in[194] = (S_AXIS_DIN_TDATA[194] !== 1'bz) && S_AXIS_DIN_TDATA[194]; // rv 0 + assign S_AXIS_DIN_TDATA_in[195] = (S_AXIS_DIN_TDATA[195] !== 1'bz) && S_AXIS_DIN_TDATA[195]; // rv 0 + assign S_AXIS_DIN_TDATA_in[196] = (S_AXIS_DIN_TDATA[196] !== 1'bz) && S_AXIS_DIN_TDATA[196]; // rv 0 + assign S_AXIS_DIN_TDATA_in[197] = (S_AXIS_DIN_TDATA[197] !== 1'bz) && S_AXIS_DIN_TDATA[197]; // rv 0 + assign S_AXIS_DIN_TDATA_in[198] = (S_AXIS_DIN_TDATA[198] !== 1'bz) && S_AXIS_DIN_TDATA[198]; // rv 0 + assign S_AXIS_DIN_TDATA_in[199] = (S_AXIS_DIN_TDATA[199] !== 1'bz) && S_AXIS_DIN_TDATA[199]; // rv 0 + assign S_AXIS_DIN_TDATA_in[19] = (S_AXIS_DIN_TDATA[19] !== 1'bz) && S_AXIS_DIN_TDATA[19]; // rv 0 + assign S_AXIS_DIN_TDATA_in[1] = (S_AXIS_DIN_TDATA[1] !== 1'bz) && S_AXIS_DIN_TDATA[1]; // rv 0 + assign S_AXIS_DIN_TDATA_in[200] = (S_AXIS_DIN_TDATA[200] !== 1'bz) && S_AXIS_DIN_TDATA[200]; // rv 0 + assign S_AXIS_DIN_TDATA_in[201] = (S_AXIS_DIN_TDATA[201] !== 1'bz) && S_AXIS_DIN_TDATA[201]; // rv 0 + assign S_AXIS_DIN_TDATA_in[202] = (S_AXIS_DIN_TDATA[202] !== 1'bz) && S_AXIS_DIN_TDATA[202]; // rv 0 + assign S_AXIS_DIN_TDATA_in[203] = (S_AXIS_DIN_TDATA[203] !== 1'bz) && S_AXIS_DIN_TDATA[203]; // rv 0 + assign S_AXIS_DIN_TDATA_in[204] = (S_AXIS_DIN_TDATA[204] !== 1'bz) && S_AXIS_DIN_TDATA[204]; // rv 0 + assign S_AXIS_DIN_TDATA_in[205] = (S_AXIS_DIN_TDATA[205] !== 1'bz) && S_AXIS_DIN_TDATA[205]; // rv 0 + assign S_AXIS_DIN_TDATA_in[206] = (S_AXIS_DIN_TDATA[206] !== 1'bz) && S_AXIS_DIN_TDATA[206]; // rv 0 + assign S_AXIS_DIN_TDATA_in[207] = (S_AXIS_DIN_TDATA[207] !== 1'bz) && S_AXIS_DIN_TDATA[207]; // rv 0 + assign S_AXIS_DIN_TDATA_in[208] = (S_AXIS_DIN_TDATA[208] !== 1'bz) && S_AXIS_DIN_TDATA[208]; // rv 0 + assign S_AXIS_DIN_TDATA_in[209] = (S_AXIS_DIN_TDATA[209] !== 1'bz) && S_AXIS_DIN_TDATA[209]; // rv 0 + assign S_AXIS_DIN_TDATA_in[20] = (S_AXIS_DIN_TDATA[20] !== 1'bz) && S_AXIS_DIN_TDATA[20]; // rv 0 + assign S_AXIS_DIN_TDATA_in[210] = (S_AXIS_DIN_TDATA[210] !== 1'bz) && S_AXIS_DIN_TDATA[210]; // rv 0 + assign S_AXIS_DIN_TDATA_in[211] = (S_AXIS_DIN_TDATA[211] !== 1'bz) && S_AXIS_DIN_TDATA[211]; // rv 0 + assign S_AXIS_DIN_TDATA_in[212] = (S_AXIS_DIN_TDATA[212] !== 1'bz) && S_AXIS_DIN_TDATA[212]; // rv 0 + assign S_AXIS_DIN_TDATA_in[213] = (S_AXIS_DIN_TDATA[213] !== 1'bz) && S_AXIS_DIN_TDATA[213]; // rv 0 + assign S_AXIS_DIN_TDATA_in[214] = (S_AXIS_DIN_TDATA[214] !== 1'bz) && S_AXIS_DIN_TDATA[214]; // rv 0 + assign S_AXIS_DIN_TDATA_in[215] = (S_AXIS_DIN_TDATA[215] !== 1'bz) && S_AXIS_DIN_TDATA[215]; // rv 0 + assign S_AXIS_DIN_TDATA_in[216] = (S_AXIS_DIN_TDATA[216] !== 1'bz) && S_AXIS_DIN_TDATA[216]; // rv 0 + assign S_AXIS_DIN_TDATA_in[217] = (S_AXIS_DIN_TDATA[217] !== 1'bz) && S_AXIS_DIN_TDATA[217]; // rv 0 + assign S_AXIS_DIN_TDATA_in[218] = (S_AXIS_DIN_TDATA[218] !== 1'bz) && S_AXIS_DIN_TDATA[218]; // rv 0 + assign S_AXIS_DIN_TDATA_in[219] = (S_AXIS_DIN_TDATA[219] !== 1'bz) && S_AXIS_DIN_TDATA[219]; // rv 0 + assign S_AXIS_DIN_TDATA_in[21] = (S_AXIS_DIN_TDATA[21] !== 1'bz) && S_AXIS_DIN_TDATA[21]; // rv 0 + assign S_AXIS_DIN_TDATA_in[220] = (S_AXIS_DIN_TDATA[220] !== 1'bz) && S_AXIS_DIN_TDATA[220]; // rv 0 + assign S_AXIS_DIN_TDATA_in[221] = (S_AXIS_DIN_TDATA[221] !== 1'bz) && S_AXIS_DIN_TDATA[221]; // rv 0 + assign S_AXIS_DIN_TDATA_in[222] = (S_AXIS_DIN_TDATA[222] !== 1'bz) && S_AXIS_DIN_TDATA[222]; // rv 0 + assign S_AXIS_DIN_TDATA_in[223] = (S_AXIS_DIN_TDATA[223] !== 1'bz) && S_AXIS_DIN_TDATA[223]; // rv 0 + assign S_AXIS_DIN_TDATA_in[224] = (S_AXIS_DIN_TDATA[224] !== 1'bz) && S_AXIS_DIN_TDATA[224]; // rv 0 + assign S_AXIS_DIN_TDATA_in[225] = (S_AXIS_DIN_TDATA[225] !== 1'bz) && S_AXIS_DIN_TDATA[225]; // rv 0 + assign S_AXIS_DIN_TDATA_in[226] = (S_AXIS_DIN_TDATA[226] !== 1'bz) && S_AXIS_DIN_TDATA[226]; // rv 0 + assign S_AXIS_DIN_TDATA_in[227] = (S_AXIS_DIN_TDATA[227] !== 1'bz) && S_AXIS_DIN_TDATA[227]; // rv 0 + assign S_AXIS_DIN_TDATA_in[228] = (S_AXIS_DIN_TDATA[228] !== 1'bz) && S_AXIS_DIN_TDATA[228]; // rv 0 + assign S_AXIS_DIN_TDATA_in[229] = (S_AXIS_DIN_TDATA[229] !== 1'bz) && S_AXIS_DIN_TDATA[229]; // rv 0 + assign S_AXIS_DIN_TDATA_in[22] = (S_AXIS_DIN_TDATA[22] !== 1'bz) && S_AXIS_DIN_TDATA[22]; // rv 0 + assign S_AXIS_DIN_TDATA_in[230] = (S_AXIS_DIN_TDATA[230] !== 1'bz) && S_AXIS_DIN_TDATA[230]; // rv 0 + assign S_AXIS_DIN_TDATA_in[231] = (S_AXIS_DIN_TDATA[231] !== 1'bz) && S_AXIS_DIN_TDATA[231]; // rv 0 + assign S_AXIS_DIN_TDATA_in[232] = (S_AXIS_DIN_TDATA[232] !== 1'bz) && S_AXIS_DIN_TDATA[232]; // rv 0 + assign S_AXIS_DIN_TDATA_in[233] = (S_AXIS_DIN_TDATA[233] !== 1'bz) && S_AXIS_DIN_TDATA[233]; // rv 0 + assign S_AXIS_DIN_TDATA_in[234] = (S_AXIS_DIN_TDATA[234] !== 1'bz) && S_AXIS_DIN_TDATA[234]; // rv 0 + assign S_AXIS_DIN_TDATA_in[235] = (S_AXIS_DIN_TDATA[235] !== 1'bz) && S_AXIS_DIN_TDATA[235]; // rv 0 + assign S_AXIS_DIN_TDATA_in[236] = (S_AXIS_DIN_TDATA[236] !== 1'bz) && S_AXIS_DIN_TDATA[236]; // rv 0 + assign S_AXIS_DIN_TDATA_in[237] = (S_AXIS_DIN_TDATA[237] !== 1'bz) && S_AXIS_DIN_TDATA[237]; // rv 0 + assign S_AXIS_DIN_TDATA_in[238] = (S_AXIS_DIN_TDATA[238] !== 1'bz) && S_AXIS_DIN_TDATA[238]; // rv 0 + assign S_AXIS_DIN_TDATA_in[239] = (S_AXIS_DIN_TDATA[239] !== 1'bz) && S_AXIS_DIN_TDATA[239]; // rv 0 + assign S_AXIS_DIN_TDATA_in[23] = (S_AXIS_DIN_TDATA[23] !== 1'bz) && S_AXIS_DIN_TDATA[23]; // rv 0 + assign S_AXIS_DIN_TDATA_in[240] = (S_AXIS_DIN_TDATA[240] !== 1'bz) && S_AXIS_DIN_TDATA[240]; // rv 0 + assign S_AXIS_DIN_TDATA_in[241] = (S_AXIS_DIN_TDATA[241] !== 1'bz) && S_AXIS_DIN_TDATA[241]; // rv 0 + assign S_AXIS_DIN_TDATA_in[242] = (S_AXIS_DIN_TDATA[242] !== 1'bz) && S_AXIS_DIN_TDATA[242]; // rv 0 + assign S_AXIS_DIN_TDATA_in[243] = (S_AXIS_DIN_TDATA[243] !== 1'bz) && S_AXIS_DIN_TDATA[243]; // rv 0 + assign S_AXIS_DIN_TDATA_in[244] = (S_AXIS_DIN_TDATA[244] !== 1'bz) && S_AXIS_DIN_TDATA[244]; // rv 0 + assign S_AXIS_DIN_TDATA_in[245] = (S_AXIS_DIN_TDATA[245] !== 1'bz) && S_AXIS_DIN_TDATA[245]; // rv 0 + assign S_AXIS_DIN_TDATA_in[246] = (S_AXIS_DIN_TDATA[246] !== 1'bz) && S_AXIS_DIN_TDATA[246]; // rv 0 + assign S_AXIS_DIN_TDATA_in[247] = (S_AXIS_DIN_TDATA[247] !== 1'bz) && S_AXIS_DIN_TDATA[247]; // rv 0 + assign S_AXIS_DIN_TDATA_in[248] = (S_AXIS_DIN_TDATA[248] !== 1'bz) && S_AXIS_DIN_TDATA[248]; // rv 0 + assign S_AXIS_DIN_TDATA_in[249] = (S_AXIS_DIN_TDATA[249] !== 1'bz) && S_AXIS_DIN_TDATA[249]; // rv 0 + assign S_AXIS_DIN_TDATA_in[24] = (S_AXIS_DIN_TDATA[24] !== 1'bz) && S_AXIS_DIN_TDATA[24]; // rv 0 + assign S_AXIS_DIN_TDATA_in[250] = (S_AXIS_DIN_TDATA[250] !== 1'bz) && S_AXIS_DIN_TDATA[250]; // rv 0 + assign S_AXIS_DIN_TDATA_in[251] = (S_AXIS_DIN_TDATA[251] !== 1'bz) && S_AXIS_DIN_TDATA[251]; // rv 0 + assign S_AXIS_DIN_TDATA_in[252] = (S_AXIS_DIN_TDATA[252] !== 1'bz) && S_AXIS_DIN_TDATA[252]; // rv 0 + assign S_AXIS_DIN_TDATA_in[253] = (S_AXIS_DIN_TDATA[253] !== 1'bz) && S_AXIS_DIN_TDATA[253]; // rv 0 + assign S_AXIS_DIN_TDATA_in[254] = (S_AXIS_DIN_TDATA[254] !== 1'bz) && S_AXIS_DIN_TDATA[254]; // rv 0 + assign S_AXIS_DIN_TDATA_in[255] = (S_AXIS_DIN_TDATA[255] !== 1'bz) && S_AXIS_DIN_TDATA[255]; // rv 0 + assign S_AXIS_DIN_TDATA_in[256] = (S_AXIS_DIN_TDATA[256] !== 1'bz) && S_AXIS_DIN_TDATA[256]; // rv 0 + assign S_AXIS_DIN_TDATA_in[257] = (S_AXIS_DIN_TDATA[257] !== 1'bz) && S_AXIS_DIN_TDATA[257]; // rv 0 + assign S_AXIS_DIN_TDATA_in[258] = (S_AXIS_DIN_TDATA[258] !== 1'bz) && S_AXIS_DIN_TDATA[258]; // rv 0 + assign S_AXIS_DIN_TDATA_in[259] = (S_AXIS_DIN_TDATA[259] !== 1'bz) && S_AXIS_DIN_TDATA[259]; // rv 0 + assign S_AXIS_DIN_TDATA_in[25] = (S_AXIS_DIN_TDATA[25] !== 1'bz) && S_AXIS_DIN_TDATA[25]; // rv 0 + assign S_AXIS_DIN_TDATA_in[260] = (S_AXIS_DIN_TDATA[260] !== 1'bz) && S_AXIS_DIN_TDATA[260]; // rv 0 + assign S_AXIS_DIN_TDATA_in[261] = (S_AXIS_DIN_TDATA[261] !== 1'bz) && S_AXIS_DIN_TDATA[261]; // rv 0 + assign S_AXIS_DIN_TDATA_in[262] = (S_AXIS_DIN_TDATA[262] !== 1'bz) && S_AXIS_DIN_TDATA[262]; // rv 0 + assign S_AXIS_DIN_TDATA_in[263] = (S_AXIS_DIN_TDATA[263] !== 1'bz) && S_AXIS_DIN_TDATA[263]; // rv 0 + assign S_AXIS_DIN_TDATA_in[264] = (S_AXIS_DIN_TDATA[264] !== 1'bz) && S_AXIS_DIN_TDATA[264]; // rv 0 + assign S_AXIS_DIN_TDATA_in[265] = (S_AXIS_DIN_TDATA[265] !== 1'bz) && S_AXIS_DIN_TDATA[265]; // rv 0 + assign S_AXIS_DIN_TDATA_in[266] = (S_AXIS_DIN_TDATA[266] !== 1'bz) && S_AXIS_DIN_TDATA[266]; // rv 0 + assign S_AXIS_DIN_TDATA_in[267] = (S_AXIS_DIN_TDATA[267] !== 1'bz) && S_AXIS_DIN_TDATA[267]; // rv 0 + assign S_AXIS_DIN_TDATA_in[268] = (S_AXIS_DIN_TDATA[268] !== 1'bz) && S_AXIS_DIN_TDATA[268]; // rv 0 + assign S_AXIS_DIN_TDATA_in[269] = (S_AXIS_DIN_TDATA[269] !== 1'bz) && S_AXIS_DIN_TDATA[269]; // rv 0 + assign S_AXIS_DIN_TDATA_in[26] = (S_AXIS_DIN_TDATA[26] !== 1'bz) && S_AXIS_DIN_TDATA[26]; // rv 0 + assign S_AXIS_DIN_TDATA_in[270] = (S_AXIS_DIN_TDATA[270] !== 1'bz) && S_AXIS_DIN_TDATA[270]; // rv 0 + assign S_AXIS_DIN_TDATA_in[271] = (S_AXIS_DIN_TDATA[271] !== 1'bz) && S_AXIS_DIN_TDATA[271]; // rv 0 + assign S_AXIS_DIN_TDATA_in[272] = (S_AXIS_DIN_TDATA[272] !== 1'bz) && S_AXIS_DIN_TDATA[272]; // rv 0 + assign S_AXIS_DIN_TDATA_in[273] = (S_AXIS_DIN_TDATA[273] !== 1'bz) && S_AXIS_DIN_TDATA[273]; // rv 0 + assign S_AXIS_DIN_TDATA_in[274] = (S_AXIS_DIN_TDATA[274] !== 1'bz) && S_AXIS_DIN_TDATA[274]; // rv 0 + assign S_AXIS_DIN_TDATA_in[275] = (S_AXIS_DIN_TDATA[275] !== 1'bz) && S_AXIS_DIN_TDATA[275]; // rv 0 + assign S_AXIS_DIN_TDATA_in[276] = (S_AXIS_DIN_TDATA[276] !== 1'bz) && S_AXIS_DIN_TDATA[276]; // rv 0 + assign S_AXIS_DIN_TDATA_in[277] = (S_AXIS_DIN_TDATA[277] !== 1'bz) && S_AXIS_DIN_TDATA[277]; // rv 0 + assign S_AXIS_DIN_TDATA_in[278] = (S_AXIS_DIN_TDATA[278] !== 1'bz) && S_AXIS_DIN_TDATA[278]; // rv 0 + assign S_AXIS_DIN_TDATA_in[279] = (S_AXIS_DIN_TDATA[279] !== 1'bz) && S_AXIS_DIN_TDATA[279]; // rv 0 + assign S_AXIS_DIN_TDATA_in[27] = (S_AXIS_DIN_TDATA[27] !== 1'bz) && S_AXIS_DIN_TDATA[27]; // rv 0 + assign S_AXIS_DIN_TDATA_in[280] = (S_AXIS_DIN_TDATA[280] !== 1'bz) && S_AXIS_DIN_TDATA[280]; // rv 0 + assign S_AXIS_DIN_TDATA_in[281] = (S_AXIS_DIN_TDATA[281] !== 1'bz) && S_AXIS_DIN_TDATA[281]; // rv 0 + assign S_AXIS_DIN_TDATA_in[282] = (S_AXIS_DIN_TDATA[282] !== 1'bz) && S_AXIS_DIN_TDATA[282]; // rv 0 + assign S_AXIS_DIN_TDATA_in[283] = (S_AXIS_DIN_TDATA[283] !== 1'bz) && S_AXIS_DIN_TDATA[283]; // rv 0 + assign S_AXIS_DIN_TDATA_in[284] = (S_AXIS_DIN_TDATA[284] !== 1'bz) && S_AXIS_DIN_TDATA[284]; // rv 0 + assign S_AXIS_DIN_TDATA_in[285] = (S_AXIS_DIN_TDATA[285] !== 1'bz) && S_AXIS_DIN_TDATA[285]; // rv 0 + assign S_AXIS_DIN_TDATA_in[286] = (S_AXIS_DIN_TDATA[286] !== 1'bz) && S_AXIS_DIN_TDATA[286]; // rv 0 + assign S_AXIS_DIN_TDATA_in[287] = (S_AXIS_DIN_TDATA[287] !== 1'bz) && S_AXIS_DIN_TDATA[287]; // rv 0 + assign S_AXIS_DIN_TDATA_in[288] = (S_AXIS_DIN_TDATA[288] !== 1'bz) && S_AXIS_DIN_TDATA[288]; // rv 0 + assign S_AXIS_DIN_TDATA_in[289] = (S_AXIS_DIN_TDATA[289] !== 1'bz) && S_AXIS_DIN_TDATA[289]; // rv 0 + assign S_AXIS_DIN_TDATA_in[28] = (S_AXIS_DIN_TDATA[28] !== 1'bz) && S_AXIS_DIN_TDATA[28]; // rv 0 + assign S_AXIS_DIN_TDATA_in[290] = (S_AXIS_DIN_TDATA[290] !== 1'bz) && S_AXIS_DIN_TDATA[290]; // rv 0 + assign S_AXIS_DIN_TDATA_in[291] = (S_AXIS_DIN_TDATA[291] !== 1'bz) && S_AXIS_DIN_TDATA[291]; // rv 0 + assign S_AXIS_DIN_TDATA_in[292] = (S_AXIS_DIN_TDATA[292] !== 1'bz) && S_AXIS_DIN_TDATA[292]; // rv 0 + assign S_AXIS_DIN_TDATA_in[293] = (S_AXIS_DIN_TDATA[293] !== 1'bz) && S_AXIS_DIN_TDATA[293]; // rv 0 + assign S_AXIS_DIN_TDATA_in[294] = (S_AXIS_DIN_TDATA[294] !== 1'bz) && S_AXIS_DIN_TDATA[294]; // rv 0 + assign S_AXIS_DIN_TDATA_in[295] = (S_AXIS_DIN_TDATA[295] !== 1'bz) && S_AXIS_DIN_TDATA[295]; // rv 0 + assign S_AXIS_DIN_TDATA_in[296] = (S_AXIS_DIN_TDATA[296] !== 1'bz) && S_AXIS_DIN_TDATA[296]; // rv 0 + assign S_AXIS_DIN_TDATA_in[297] = (S_AXIS_DIN_TDATA[297] !== 1'bz) && S_AXIS_DIN_TDATA[297]; // rv 0 + assign S_AXIS_DIN_TDATA_in[298] = (S_AXIS_DIN_TDATA[298] !== 1'bz) && S_AXIS_DIN_TDATA[298]; // rv 0 + assign S_AXIS_DIN_TDATA_in[299] = (S_AXIS_DIN_TDATA[299] !== 1'bz) && S_AXIS_DIN_TDATA[299]; // rv 0 + assign S_AXIS_DIN_TDATA_in[29] = (S_AXIS_DIN_TDATA[29] !== 1'bz) && S_AXIS_DIN_TDATA[29]; // rv 0 + assign S_AXIS_DIN_TDATA_in[2] = (S_AXIS_DIN_TDATA[2] !== 1'bz) && S_AXIS_DIN_TDATA[2]; // rv 0 + assign S_AXIS_DIN_TDATA_in[300] = (S_AXIS_DIN_TDATA[300] !== 1'bz) && S_AXIS_DIN_TDATA[300]; // rv 0 + assign S_AXIS_DIN_TDATA_in[301] = (S_AXIS_DIN_TDATA[301] !== 1'bz) && S_AXIS_DIN_TDATA[301]; // rv 0 + assign S_AXIS_DIN_TDATA_in[302] = (S_AXIS_DIN_TDATA[302] !== 1'bz) && S_AXIS_DIN_TDATA[302]; // rv 0 + assign S_AXIS_DIN_TDATA_in[303] = (S_AXIS_DIN_TDATA[303] !== 1'bz) && S_AXIS_DIN_TDATA[303]; // rv 0 + assign S_AXIS_DIN_TDATA_in[304] = (S_AXIS_DIN_TDATA[304] !== 1'bz) && S_AXIS_DIN_TDATA[304]; // rv 0 + assign S_AXIS_DIN_TDATA_in[305] = (S_AXIS_DIN_TDATA[305] !== 1'bz) && S_AXIS_DIN_TDATA[305]; // rv 0 + assign S_AXIS_DIN_TDATA_in[306] = (S_AXIS_DIN_TDATA[306] !== 1'bz) && S_AXIS_DIN_TDATA[306]; // rv 0 + assign S_AXIS_DIN_TDATA_in[307] = (S_AXIS_DIN_TDATA[307] !== 1'bz) && S_AXIS_DIN_TDATA[307]; // rv 0 + assign S_AXIS_DIN_TDATA_in[308] = (S_AXIS_DIN_TDATA[308] !== 1'bz) && S_AXIS_DIN_TDATA[308]; // rv 0 + assign S_AXIS_DIN_TDATA_in[309] = (S_AXIS_DIN_TDATA[309] !== 1'bz) && S_AXIS_DIN_TDATA[309]; // rv 0 + assign S_AXIS_DIN_TDATA_in[30] = (S_AXIS_DIN_TDATA[30] !== 1'bz) && S_AXIS_DIN_TDATA[30]; // rv 0 + assign S_AXIS_DIN_TDATA_in[310] = (S_AXIS_DIN_TDATA[310] !== 1'bz) && S_AXIS_DIN_TDATA[310]; // rv 0 + assign S_AXIS_DIN_TDATA_in[311] = (S_AXIS_DIN_TDATA[311] !== 1'bz) && S_AXIS_DIN_TDATA[311]; // rv 0 + assign S_AXIS_DIN_TDATA_in[312] = (S_AXIS_DIN_TDATA[312] !== 1'bz) && S_AXIS_DIN_TDATA[312]; // rv 0 + assign S_AXIS_DIN_TDATA_in[313] = (S_AXIS_DIN_TDATA[313] !== 1'bz) && S_AXIS_DIN_TDATA[313]; // rv 0 + assign S_AXIS_DIN_TDATA_in[314] = (S_AXIS_DIN_TDATA[314] !== 1'bz) && S_AXIS_DIN_TDATA[314]; // rv 0 + assign S_AXIS_DIN_TDATA_in[315] = (S_AXIS_DIN_TDATA[315] !== 1'bz) && S_AXIS_DIN_TDATA[315]; // rv 0 + assign S_AXIS_DIN_TDATA_in[316] = (S_AXIS_DIN_TDATA[316] !== 1'bz) && S_AXIS_DIN_TDATA[316]; // rv 0 + assign S_AXIS_DIN_TDATA_in[317] = (S_AXIS_DIN_TDATA[317] !== 1'bz) && S_AXIS_DIN_TDATA[317]; // rv 0 + assign S_AXIS_DIN_TDATA_in[318] = (S_AXIS_DIN_TDATA[318] !== 1'bz) && S_AXIS_DIN_TDATA[318]; // rv 0 + assign S_AXIS_DIN_TDATA_in[319] = (S_AXIS_DIN_TDATA[319] !== 1'bz) && S_AXIS_DIN_TDATA[319]; // rv 0 + assign S_AXIS_DIN_TDATA_in[31] = (S_AXIS_DIN_TDATA[31] !== 1'bz) && S_AXIS_DIN_TDATA[31]; // rv 0 + assign S_AXIS_DIN_TDATA_in[320] = (S_AXIS_DIN_TDATA[320] !== 1'bz) && S_AXIS_DIN_TDATA[320]; // rv 0 + assign S_AXIS_DIN_TDATA_in[321] = (S_AXIS_DIN_TDATA[321] !== 1'bz) && S_AXIS_DIN_TDATA[321]; // rv 0 + assign S_AXIS_DIN_TDATA_in[322] = (S_AXIS_DIN_TDATA[322] !== 1'bz) && S_AXIS_DIN_TDATA[322]; // rv 0 + assign S_AXIS_DIN_TDATA_in[323] = (S_AXIS_DIN_TDATA[323] !== 1'bz) && S_AXIS_DIN_TDATA[323]; // rv 0 + assign S_AXIS_DIN_TDATA_in[324] = (S_AXIS_DIN_TDATA[324] !== 1'bz) && S_AXIS_DIN_TDATA[324]; // rv 0 + assign S_AXIS_DIN_TDATA_in[325] = (S_AXIS_DIN_TDATA[325] !== 1'bz) && S_AXIS_DIN_TDATA[325]; // rv 0 + assign S_AXIS_DIN_TDATA_in[326] = (S_AXIS_DIN_TDATA[326] !== 1'bz) && S_AXIS_DIN_TDATA[326]; // rv 0 + assign S_AXIS_DIN_TDATA_in[327] = (S_AXIS_DIN_TDATA[327] !== 1'bz) && S_AXIS_DIN_TDATA[327]; // rv 0 + assign S_AXIS_DIN_TDATA_in[328] = (S_AXIS_DIN_TDATA[328] !== 1'bz) && S_AXIS_DIN_TDATA[328]; // rv 0 + assign S_AXIS_DIN_TDATA_in[329] = (S_AXIS_DIN_TDATA[329] !== 1'bz) && S_AXIS_DIN_TDATA[329]; // rv 0 + assign S_AXIS_DIN_TDATA_in[32] = (S_AXIS_DIN_TDATA[32] !== 1'bz) && S_AXIS_DIN_TDATA[32]; // rv 0 + assign S_AXIS_DIN_TDATA_in[330] = (S_AXIS_DIN_TDATA[330] !== 1'bz) && S_AXIS_DIN_TDATA[330]; // rv 0 + assign S_AXIS_DIN_TDATA_in[331] = (S_AXIS_DIN_TDATA[331] !== 1'bz) && S_AXIS_DIN_TDATA[331]; // rv 0 + assign S_AXIS_DIN_TDATA_in[332] = (S_AXIS_DIN_TDATA[332] !== 1'bz) && S_AXIS_DIN_TDATA[332]; // rv 0 + assign S_AXIS_DIN_TDATA_in[333] = (S_AXIS_DIN_TDATA[333] !== 1'bz) && S_AXIS_DIN_TDATA[333]; // rv 0 + assign S_AXIS_DIN_TDATA_in[334] = (S_AXIS_DIN_TDATA[334] !== 1'bz) && S_AXIS_DIN_TDATA[334]; // rv 0 + assign S_AXIS_DIN_TDATA_in[335] = (S_AXIS_DIN_TDATA[335] !== 1'bz) && S_AXIS_DIN_TDATA[335]; // rv 0 + assign S_AXIS_DIN_TDATA_in[336] = (S_AXIS_DIN_TDATA[336] !== 1'bz) && S_AXIS_DIN_TDATA[336]; // rv 0 + assign S_AXIS_DIN_TDATA_in[337] = (S_AXIS_DIN_TDATA[337] !== 1'bz) && S_AXIS_DIN_TDATA[337]; // rv 0 + assign S_AXIS_DIN_TDATA_in[338] = (S_AXIS_DIN_TDATA[338] !== 1'bz) && S_AXIS_DIN_TDATA[338]; // rv 0 + assign S_AXIS_DIN_TDATA_in[339] = (S_AXIS_DIN_TDATA[339] !== 1'bz) && S_AXIS_DIN_TDATA[339]; // rv 0 + assign S_AXIS_DIN_TDATA_in[33] = (S_AXIS_DIN_TDATA[33] !== 1'bz) && S_AXIS_DIN_TDATA[33]; // rv 0 + assign S_AXIS_DIN_TDATA_in[340] = (S_AXIS_DIN_TDATA[340] !== 1'bz) && S_AXIS_DIN_TDATA[340]; // rv 0 + assign S_AXIS_DIN_TDATA_in[341] = (S_AXIS_DIN_TDATA[341] !== 1'bz) && S_AXIS_DIN_TDATA[341]; // rv 0 + assign S_AXIS_DIN_TDATA_in[342] = (S_AXIS_DIN_TDATA[342] !== 1'bz) && S_AXIS_DIN_TDATA[342]; // rv 0 + assign S_AXIS_DIN_TDATA_in[343] = (S_AXIS_DIN_TDATA[343] !== 1'bz) && S_AXIS_DIN_TDATA[343]; // rv 0 + assign S_AXIS_DIN_TDATA_in[344] = (S_AXIS_DIN_TDATA[344] !== 1'bz) && S_AXIS_DIN_TDATA[344]; // rv 0 + assign S_AXIS_DIN_TDATA_in[345] = (S_AXIS_DIN_TDATA[345] !== 1'bz) && S_AXIS_DIN_TDATA[345]; // rv 0 + assign S_AXIS_DIN_TDATA_in[346] = (S_AXIS_DIN_TDATA[346] !== 1'bz) && S_AXIS_DIN_TDATA[346]; // rv 0 + assign S_AXIS_DIN_TDATA_in[347] = (S_AXIS_DIN_TDATA[347] !== 1'bz) && S_AXIS_DIN_TDATA[347]; // rv 0 + assign S_AXIS_DIN_TDATA_in[348] = (S_AXIS_DIN_TDATA[348] !== 1'bz) && S_AXIS_DIN_TDATA[348]; // rv 0 + assign S_AXIS_DIN_TDATA_in[349] = (S_AXIS_DIN_TDATA[349] !== 1'bz) && S_AXIS_DIN_TDATA[349]; // rv 0 + assign S_AXIS_DIN_TDATA_in[34] = (S_AXIS_DIN_TDATA[34] !== 1'bz) && S_AXIS_DIN_TDATA[34]; // rv 0 + assign S_AXIS_DIN_TDATA_in[350] = (S_AXIS_DIN_TDATA[350] !== 1'bz) && S_AXIS_DIN_TDATA[350]; // rv 0 + assign S_AXIS_DIN_TDATA_in[351] = (S_AXIS_DIN_TDATA[351] !== 1'bz) && S_AXIS_DIN_TDATA[351]; // rv 0 + assign S_AXIS_DIN_TDATA_in[352] = (S_AXIS_DIN_TDATA[352] !== 1'bz) && S_AXIS_DIN_TDATA[352]; // rv 0 + assign S_AXIS_DIN_TDATA_in[353] = (S_AXIS_DIN_TDATA[353] !== 1'bz) && S_AXIS_DIN_TDATA[353]; // rv 0 + assign S_AXIS_DIN_TDATA_in[354] = (S_AXIS_DIN_TDATA[354] !== 1'bz) && S_AXIS_DIN_TDATA[354]; // rv 0 + assign S_AXIS_DIN_TDATA_in[355] = (S_AXIS_DIN_TDATA[355] !== 1'bz) && S_AXIS_DIN_TDATA[355]; // rv 0 + assign S_AXIS_DIN_TDATA_in[356] = (S_AXIS_DIN_TDATA[356] !== 1'bz) && S_AXIS_DIN_TDATA[356]; // rv 0 + assign S_AXIS_DIN_TDATA_in[357] = (S_AXIS_DIN_TDATA[357] !== 1'bz) && S_AXIS_DIN_TDATA[357]; // rv 0 + assign S_AXIS_DIN_TDATA_in[358] = (S_AXIS_DIN_TDATA[358] !== 1'bz) && S_AXIS_DIN_TDATA[358]; // rv 0 + assign S_AXIS_DIN_TDATA_in[359] = (S_AXIS_DIN_TDATA[359] !== 1'bz) && S_AXIS_DIN_TDATA[359]; // rv 0 + assign S_AXIS_DIN_TDATA_in[35] = (S_AXIS_DIN_TDATA[35] !== 1'bz) && S_AXIS_DIN_TDATA[35]; // rv 0 + assign S_AXIS_DIN_TDATA_in[360] = (S_AXIS_DIN_TDATA[360] !== 1'bz) && S_AXIS_DIN_TDATA[360]; // rv 0 + assign S_AXIS_DIN_TDATA_in[361] = (S_AXIS_DIN_TDATA[361] !== 1'bz) && S_AXIS_DIN_TDATA[361]; // rv 0 + assign S_AXIS_DIN_TDATA_in[362] = (S_AXIS_DIN_TDATA[362] !== 1'bz) && S_AXIS_DIN_TDATA[362]; // rv 0 + assign S_AXIS_DIN_TDATA_in[363] = (S_AXIS_DIN_TDATA[363] !== 1'bz) && S_AXIS_DIN_TDATA[363]; // rv 0 + assign S_AXIS_DIN_TDATA_in[364] = (S_AXIS_DIN_TDATA[364] !== 1'bz) && S_AXIS_DIN_TDATA[364]; // rv 0 + assign S_AXIS_DIN_TDATA_in[365] = (S_AXIS_DIN_TDATA[365] !== 1'bz) && S_AXIS_DIN_TDATA[365]; // rv 0 + assign S_AXIS_DIN_TDATA_in[366] = (S_AXIS_DIN_TDATA[366] !== 1'bz) && S_AXIS_DIN_TDATA[366]; // rv 0 + assign S_AXIS_DIN_TDATA_in[367] = (S_AXIS_DIN_TDATA[367] !== 1'bz) && S_AXIS_DIN_TDATA[367]; // rv 0 + assign S_AXIS_DIN_TDATA_in[368] = (S_AXIS_DIN_TDATA[368] !== 1'bz) && S_AXIS_DIN_TDATA[368]; // rv 0 + assign S_AXIS_DIN_TDATA_in[369] = (S_AXIS_DIN_TDATA[369] !== 1'bz) && S_AXIS_DIN_TDATA[369]; // rv 0 + assign S_AXIS_DIN_TDATA_in[36] = (S_AXIS_DIN_TDATA[36] !== 1'bz) && S_AXIS_DIN_TDATA[36]; // rv 0 + assign S_AXIS_DIN_TDATA_in[370] = (S_AXIS_DIN_TDATA[370] !== 1'bz) && S_AXIS_DIN_TDATA[370]; // rv 0 + assign S_AXIS_DIN_TDATA_in[371] = (S_AXIS_DIN_TDATA[371] !== 1'bz) && S_AXIS_DIN_TDATA[371]; // rv 0 + assign S_AXIS_DIN_TDATA_in[372] = (S_AXIS_DIN_TDATA[372] !== 1'bz) && S_AXIS_DIN_TDATA[372]; // rv 0 + assign S_AXIS_DIN_TDATA_in[373] = (S_AXIS_DIN_TDATA[373] !== 1'bz) && S_AXIS_DIN_TDATA[373]; // rv 0 + assign S_AXIS_DIN_TDATA_in[374] = (S_AXIS_DIN_TDATA[374] !== 1'bz) && S_AXIS_DIN_TDATA[374]; // rv 0 + assign S_AXIS_DIN_TDATA_in[375] = (S_AXIS_DIN_TDATA[375] !== 1'bz) && S_AXIS_DIN_TDATA[375]; // rv 0 + assign S_AXIS_DIN_TDATA_in[376] = (S_AXIS_DIN_TDATA[376] !== 1'bz) && S_AXIS_DIN_TDATA[376]; // rv 0 + assign S_AXIS_DIN_TDATA_in[377] = (S_AXIS_DIN_TDATA[377] !== 1'bz) && S_AXIS_DIN_TDATA[377]; // rv 0 + assign S_AXIS_DIN_TDATA_in[378] = (S_AXIS_DIN_TDATA[378] !== 1'bz) && S_AXIS_DIN_TDATA[378]; // rv 0 + assign S_AXIS_DIN_TDATA_in[379] = (S_AXIS_DIN_TDATA[379] !== 1'bz) && S_AXIS_DIN_TDATA[379]; // rv 0 + assign S_AXIS_DIN_TDATA_in[37] = (S_AXIS_DIN_TDATA[37] !== 1'bz) && S_AXIS_DIN_TDATA[37]; // rv 0 + assign S_AXIS_DIN_TDATA_in[380] = (S_AXIS_DIN_TDATA[380] !== 1'bz) && S_AXIS_DIN_TDATA[380]; // rv 0 + assign S_AXIS_DIN_TDATA_in[381] = (S_AXIS_DIN_TDATA[381] !== 1'bz) && S_AXIS_DIN_TDATA[381]; // rv 0 + assign S_AXIS_DIN_TDATA_in[382] = (S_AXIS_DIN_TDATA[382] !== 1'bz) && S_AXIS_DIN_TDATA[382]; // rv 0 + assign S_AXIS_DIN_TDATA_in[383] = (S_AXIS_DIN_TDATA[383] !== 1'bz) && S_AXIS_DIN_TDATA[383]; // rv 0 + assign S_AXIS_DIN_TDATA_in[384] = (S_AXIS_DIN_TDATA[384] !== 1'bz) && S_AXIS_DIN_TDATA[384]; // rv 0 + assign S_AXIS_DIN_TDATA_in[385] = (S_AXIS_DIN_TDATA[385] !== 1'bz) && S_AXIS_DIN_TDATA[385]; // rv 0 + assign S_AXIS_DIN_TDATA_in[386] = (S_AXIS_DIN_TDATA[386] !== 1'bz) && S_AXIS_DIN_TDATA[386]; // rv 0 + assign S_AXIS_DIN_TDATA_in[387] = (S_AXIS_DIN_TDATA[387] !== 1'bz) && S_AXIS_DIN_TDATA[387]; // rv 0 + assign S_AXIS_DIN_TDATA_in[388] = (S_AXIS_DIN_TDATA[388] !== 1'bz) && S_AXIS_DIN_TDATA[388]; // rv 0 + assign S_AXIS_DIN_TDATA_in[389] = (S_AXIS_DIN_TDATA[389] !== 1'bz) && S_AXIS_DIN_TDATA[389]; // rv 0 + assign S_AXIS_DIN_TDATA_in[38] = (S_AXIS_DIN_TDATA[38] !== 1'bz) && S_AXIS_DIN_TDATA[38]; // rv 0 + assign S_AXIS_DIN_TDATA_in[390] = (S_AXIS_DIN_TDATA[390] !== 1'bz) && S_AXIS_DIN_TDATA[390]; // rv 0 + assign S_AXIS_DIN_TDATA_in[391] = (S_AXIS_DIN_TDATA[391] !== 1'bz) && S_AXIS_DIN_TDATA[391]; // rv 0 + assign S_AXIS_DIN_TDATA_in[392] = (S_AXIS_DIN_TDATA[392] !== 1'bz) && S_AXIS_DIN_TDATA[392]; // rv 0 + assign S_AXIS_DIN_TDATA_in[393] = (S_AXIS_DIN_TDATA[393] !== 1'bz) && S_AXIS_DIN_TDATA[393]; // rv 0 + assign S_AXIS_DIN_TDATA_in[394] = (S_AXIS_DIN_TDATA[394] !== 1'bz) && S_AXIS_DIN_TDATA[394]; // rv 0 + assign S_AXIS_DIN_TDATA_in[395] = (S_AXIS_DIN_TDATA[395] !== 1'bz) && S_AXIS_DIN_TDATA[395]; // rv 0 + assign S_AXIS_DIN_TDATA_in[396] = (S_AXIS_DIN_TDATA[396] !== 1'bz) && S_AXIS_DIN_TDATA[396]; // rv 0 + assign S_AXIS_DIN_TDATA_in[397] = (S_AXIS_DIN_TDATA[397] !== 1'bz) && S_AXIS_DIN_TDATA[397]; // rv 0 + assign S_AXIS_DIN_TDATA_in[398] = (S_AXIS_DIN_TDATA[398] !== 1'bz) && S_AXIS_DIN_TDATA[398]; // rv 0 + assign S_AXIS_DIN_TDATA_in[399] = (S_AXIS_DIN_TDATA[399] !== 1'bz) && S_AXIS_DIN_TDATA[399]; // rv 0 + assign S_AXIS_DIN_TDATA_in[39] = (S_AXIS_DIN_TDATA[39] !== 1'bz) && S_AXIS_DIN_TDATA[39]; // rv 0 + assign S_AXIS_DIN_TDATA_in[3] = (S_AXIS_DIN_TDATA[3] !== 1'bz) && S_AXIS_DIN_TDATA[3]; // rv 0 + assign S_AXIS_DIN_TDATA_in[400] = (S_AXIS_DIN_TDATA[400] !== 1'bz) && S_AXIS_DIN_TDATA[400]; // rv 0 + assign S_AXIS_DIN_TDATA_in[401] = (S_AXIS_DIN_TDATA[401] !== 1'bz) && S_AXIS_DIN_TDATA[401]; // rv 0 + assign S_AXIS_DIN_TDATA_in[402] = (S_AXIS_DIN_TDATA[402] !== 1'bz) && S_AXIS_DIN_TDATA[402]; // rv 0 + assign S_AXIS_DIN_TDATA_in[403] = (S_AXIS_DIN_TDATA[403] !== 1'bz) && S_AXIS_DIN_TDATA[403]; // rv 0 + assign S_AXIS_DIN_TDATA_in[404] = (S_AXIS_DIN_TDATA[404] !== 1'bz) && S_AXIS_DIN_TDATA[404]; // rv 0 + assign S_AXIS_DIN_TDATA_in[405] = (S_AXIS_DIN_TDATA[405] !== 1'bz) && S_AXIS_DIN_TDATA[405]; // rv 0 + assign S_AXIS_DIN_TDATA_in[406] = (S_AXIS_DIN_TDATA[406] !== 1'bz) && S_AXIS_DIN_TDATA[406]; // rv 0 + assign S_AXIS_DIN_TDATA_in[407] = (S_AXIS_DIN_TDATA[407] !== 1'bz) && S_AXIS_DIN_TDATA[407]; // rv 0 + assign S_AXIS_DIN_TDATA_in[408] = (S_AXIS_DIN_TDATA[408] !== 1'bz) && S_AXIS_DIN_TDATA[408]; // rv 0 + assign S_AXIS_DIN_TDATA_in[409] = (S_AXIS_DIN_TDATA[409] !== 1'bz) && S_AXIS_DIN_TDATA[409]; // rv 0 + assign S_AXIS_DIN_TDATA_in[40] = (S_AXIS_DIN_TDATA[40] !== 1'bz) && S_AXIS_DIN_TDATA[40]; // rv 0 + assign S_AXIS_DIN_TDATA_in[410] = (S_AXIS_DIN_TDATA[410] !== 1'bz) && S_AXIS_DIN_TDATA[410]; // rv 0 + assign S_AXIS_DIN_TDATA_in[411] = (S_AXIS_DIN_TDATA[411] !== 1'bz) && S_AXIS_DIN_TDATA[411]; // rv 0 + assign S_AXIS_DIN_TDATA_in[412] = (S_AXIS_DIN_TDATA[412] !== 1'bz) && S_AXIS_DIN_TDATA[412]; // rv 0 + assign S_AXIS_DIN_TDATA_in[413] = (S_AXIS_DIN_TDATA[413] !== 1'bz) && S_AXIS_DIN_TDATA[413]; // rv 0 + assign S_AXIS_DIN_TDATA_in[414] = (S_AXIS_DIN_TDATA[414] !== 1'bz) && S_AXIS_DIN_TDATA[414]; // rv 0 + assign S_AXIS_DIN_TDATA_in[415] = (S_AXIS_DIN_TDATA[415] !== 1'bz) && S_AXIS_DIN_TDATA[415]; // rv 0 + assign S_AXIS_DIN_TDATA_in[416] = (S_AXIS_DIN_TDATA[416] !== 1'bz) && S_AXIS_DIN_TDATA[416]; // rv 0 + assign S_AXIS_DIN_TDATA_in[417] = (S_AXIS_DIN_TDATA[417] !== 1'bz) && S_AXIS_DIN_TDATA[417]; // rv 0 + assign S_AXIS_DIN_TDATA_in[418] = (S_AXIS_DIN_TDATA[418] !== 1'bz) && S_AXIS_DIN_TDATA[418]; // rv 0 + assign S_AXIS_DIN_TDATA_in[419] = (S_AXIS_DIN_TDATA[419] !== 1'bz) && S_AXIS_DIN_TDATA[419]; // rv 0 + assign S_AXIS_DIN_TDATA_in[41] = (S_AXIS_DIN_TDATA[41] !== 1'bz) && S_AXIS_DIN_TDATA[41]; // rv 0 + assign S_AXIS_DIN_TDATA_in[420] = (S_AXIS_DIN_TDATA[420] !== 1'bz) && S_AXIS_DIN_TDATA[420]; // rv 0 + assign S_AXIS_DIN_TDATA_in[421] = (S_AXIS_DIN_TDATA[421] !== 1'bz) && S_AXIS_DIN_TDATA[421]; // rv 0 + assign S_AXIS_DIN_TDATA_in[422] = (S_AXIS_DIN_TDATA[422] !== 1'bz) && S_AXIS_DIN_TDATA[422]; // rv 0 + assign S_AXIS_DIN_TDATA_in[423] = (S_AXIS_DIN_TDATA[423] !== 1'bz) && S_AXIS_DIN_TDATA[423]; // rv 0 + assign S_AXIS_DIN_TDATA_in[424] = (S_AXIS_DIN_TDATA[424] !== 1'bz) && S_AXIS_DIN_TDATA[424]; // rv 0 + assign S_AXIS_DIN_TDATA_in[425] = (S_AXIS_DIN_TDATA[425] !== 1'bz) && S_AXIS_DIN_TDATA[425]; // rv 0 + assign S_AXIS_DIN_TDATA_in[426] = (S_AXIS_DIN_TDATA[426] !== 1'bz) && S_AXIS_DIN_TDATA[426]; // rv 0 + assign S_AXIS_DIN_TDATA_in[427] = (S_AXIS_DIN_TDATA[427] !== 1'bz) && S_AXIS_DIN_TDATA[427]; // rv 0 + assign S_AXIS_DIN_TDATA_in[428] = (S_AXIS_DIN_TDATA[428] !== 1'bz) && S_AXIS_DIN_TDATA[428]; // rv 0 + assign S_AXIS_DIN_TDATA_in[429] = (S_AXIS_DIN_TDATA[429] !== 1'bz) && S_AXIS_DIN_TDATA[429]; // rv 0 + assign S_AXIS_DIN_TDATA_in[42] = (S_AXIS_DIN_TDATA[42] !== 1'bz) && S_AXIS_DIN_TDATA[42]; // rv 0 + assign S_AXIS_DIN_TDATA_in[430] = (S_AXIS_DIN_TDATA[430] !== 1'bz) && S_AXIS_DIN_TDATA[430]; // rv 0 + assign S_AXIS_DIN_TDATA_in[431] = (S_AXIS_DIN_TDATA[431] !== 1'bz) && S_AXIS_DIN_TDATA[431]; // rv 0 + assign S_AXIS_DIN_TDATA_in[432] = (S_AXIS_DIN_TDATA[432] !== 1'bz) && S_AXIS_DIN_TDATA[432]; // rv 0 + assign S_AXIS_DIN_TDATA_in[433] = (S_AXIS_DIN_TDATA[433] !== 1'bz) && S_AXIS_DIN_TDATA[433]; // rv 0 + assign S_AXIS_DIN_TDATA_in[434] = (S_AXIS_DIN_TDATA[434] !== 1'bz) && S_AXIS_DIN_TDATA[434]; // rv 0 + assign S_AXIS_DIN_TDATA_in[435] = (S_AXIS_DIN_TDATA[435] !== 1'bz) && S_AXIS_DIN_TDATA[435]; // rv 0 + assign S_AXIS_DIN_TDATA_in[436] = (S_AXIS_DIN_TDATA[436] !== 1'bz) && S_AXIS_DIN_TDATA[436]; // rv 0 + assign S_AXIS_DIN_TDATA_in[437] = (S_AXIS_DIN_TDATA[437] !== 1'bz) && S_AXIS_DIN_TDATA[437]; // rv 0 + assign S_AXIS_DIN_TDATA_in[438] = (S_AXIS_DIN_TDATA[438] !== 1'bz) && S_AXIS_DIN_TDATA[438]; // rv 0 + assign S_AXIS_DIN_TDATA_in[439] = (S_AXIS_DIN_TDATA[439] !== 1'bz) && S_AXIS_DIN_TDATA[439]; // rv 0 + assign S_AXIS_DIN_TDATA_in[43] = (S_AXIS_DIN_TDATA[43] !== 1'bz) && S_AXIS_DIN_TDATA[43]; // rv 0 + assign S_AXIS_DIN_TDATA_in[440] = (S_AXIS_DIN_TDATA[440] !== 1'bz) && S_AXIS_DIN_TDATA[440]; // rv 0 + assign S_AXIS_DIN_TDATA_in[441] = (S_AXIS_DIN_TDATA[441] !== 1'bz) && S_AXIS_DIN_TDATA[441]; // rv 0 + assign S_AXIS_DIN_TDATA_in[442] = (S_AXIS_DIN_TDATA[442] !== 1'bz) && S_AXIS_DIN_TDATA[442]; // rv 0 + assign S_AXIS_DIN_TDATA_in[443] = (S_AXIS_DIN_TDATA[443] !== 1'bz) && S_AXIS_DIN_TDATA[443]; // rv 0 + assign S_AXIS_DIN_TDATA_in[444] = (S_AXIS_DIN_TDATA[444] !== 1'bz) && S_AXIS_DIN_TDATA[444]; // rv 0 + assign S_AXIS_DIN_TDATA_in[445] = (S_AXIS_DIN_TDATA[445] !== 1'bz) && S_AXIS_DIN_TDATA[445]; // rv 0 + assign S_AXIS_DIN_TDATA_in[446] = (S_AXIS_DIN_TDATA[446] !== 1'bz) && S_AXIS_DIN_TDATA[446]; // rv 0 + assign S_AXIS_DIN_TDATA_in[447] = (S_AXIS_DIN_TDATA[447] !== 1'bz) && S_AXIS_DIN_TDATA[447]; // rv 0 + assign S_AXIS_DIN_TDATA_in[448] = (S_AXIS_DIN_TDATA[448] !== 1'bz) && S_AXIS_DIN_TDATA[448]; // rv 0 + assign S_AXIS_DIN_TDATA_in[449] = (S_AXIS_DIN_TDATA[449] !== 1'bz) && S_AXIS_DIN_TDATA[449]; // rv 0 + assign S_AXIS_DIN_TDATA_in[44] = (S_AXIS_DIN_TDATA[44] !== 1'bz) && S_AXIS_DIN_TDATA[44]; // rv 0 + assign S_AXIS_DIN_TDATA_in[450] = (S_AXIS_DIN_TDATA[450] !== 1'bz) && S_AXIS_DIN_TDATA[450]; // rv 0 + assign S_AXIS_DIN_TDATA_in[451] = (S_AXIS_DIN_TDATA[451] !== 1'bz) && S_AXIS_DIN_TDATA[451]; // rv 0 + assign S_AXIS_DIN_TDATA_in[452] = (S_AXIS_DIN_TDATA[452] !== 1'bz) && S_AXIS_DIN_TDATA[452]; // rv 0 + assign S_AXIS_DIN_TDATA_in[453] = (S_AXIS_DIN_TDATA[453] !== 1'bz) && S_AXIS_DIN_TDATA[453]; // rv 0 + assign S_AXIS_DIN_TDATA_in[454] = (S_AXIS_DIN_TDATA[454] !== 1'bz) && S_AXIS_DIN_TDATA[454]; // rv 0 + assign S_AXIS_DIN_TDATA_in[455] = (S_AXIS_DIN_TDATA[455] !== 1'bz) && S_AXIS_DIN_TDATA[455]; // rv 0 + assign S_AXIS_DIN_TDATA_in[456] = (S_AXIS_DIN_TDATA[456] !== 1'bz) && S_AXIS_DIN_TDATA[456]; // rv 0 + assign S_AXIS_DIN_TDATA_in[457] = (S_AXIS_DIN_TDATA[457] !== 1'bz) && S_AXIS_DIN_TDATA[457]; // rv 0 + assign S_AXIS_DIN_TDATA_in[458] = (S_AXIS_DIN_TDATA[458] !== 1'bz) && S_AXIS_DIN_TDATA[458]; // rv 0 + assign S_AXIS_DIN_TDATA_in[459] = (S_AXIS_DIN_TDATA[459] !== 1'bz) && S_AXIS_DIN_TDATA[459]; // rv 0 + assign S_AXIS_DIN_TDATA_in[45] = (S_AXIS_DIN_TDATA[45] !== 1'bz) && S_AXIS_DIN_TDATA[45]; // rv 0 + assign S_AXIS_DIN_TDATA_in[460] = (S_AXIS_DIN_TDATA[460] !== 1'bz) && S_AXIS_DIN_TDATA[460]; // rv 0 + assign S_AXIS_DIN_TDATA_in[461] = (S_AXIS_DIN_TDATA[461] !== 1'bz) && S_AXIS_DIN_TDATA[461]; // rv 0 + assign S_AXIS_DIN_TDATA_in[462] = (S_AXIS_DIN_TDATA[462] !== 1'bz) && S_AXIS_DIN_TDATA[462]; // rv 0 + assign S_AXIS_DIN_TDATA_in[463] = (S_AXIS_DIN_TDATA[463] !== 1'bz) && S_AXIS_DIN_TDATA[463]; // rv 0 + assign S_AXIS_DIN_TDATA_in[464] = (S_AXIS_DIN_TDATA[464] !== 1'bz) && S_AXIS_DIN_TDATA[464]; // rv 0 + assign S_AXIS_DIN_TDATA_in[465] = (S_AXIS_DIN_TDATA[465] !== 1'bz) && S_AXIS_DIN_TDATA[465]; // rv 0 + assign S_AXIS_DIN_TDATA_in[466] = (S_AXIS_DIN_TDATA[466] !== 1'bz) && S_AXIS_DIN_TDATA[466]; // rv 0 + assign S_AXIS_DIN_TDATA_in[467] = (S_AXIS_DIN_TDATA[467] !== 1'bz) && S_AXIS_DIN_TDATA[467]; // rv 0 + assign S_AXIS_DIN_TDATA_in[468] = (S_AXIS_DIN_TDATA[468] !== 1'bz) && S_AXIS_DIN_TDATA[468]; // rv 0 + assign S_AXIS_DIN_TDATA_in[469] = (S_AXIS_DIN_TDATA[469] !== 1'bz) && S_AXIS_DIN_TDATA[469]; // rv 0 + assign S_AXIS_DIN_TDATA_in[46] = (S_AXIS_DIN_TDATA[46] !== 1'bz) && S_AXIS_DIN_TDATA[46]; // rv 0 + assign S_AXIS_DIN_TDATA_in[470] = (S_AXIS_DIN_TDATA[470] !== 1'bz) && S_AXIS_DIN_TDATA[470]; // rv 0 + assign S_AXIS_DIN_TDATA_in[471] = (S_AXIS_DIN_TDATA[471] !== 1'bz) && S_AXIS_DIN_TDATA[471]; // rv 0 + assign S_AXIS_DIN_TDATA_in[472] = (S_AXIS_DIN_TDATA[472] !== 1'bz) && S_AXIS_DIN_TDATA[472]; // rv 0 + assign S_AXIS_DIN_TDATA_in[473] = (S_AXIS_DIN_TDATA[473] !== 1'bz) && S_AXIS_DIN_TDATA[473]; // rv 0 + assign S_AXIS_DIN_TDATA_in[474] = (S_AXIS_DIN_TDATA[474] !== 1'bz) && S_AXIS_DIN_TDATA[474]; // rv 0 + assign S_AXIS_DIN_TDATA_in[475] = (S_AXIS_DIN_TDATA[475] !== 1'bz) && S_AXIS_DIN_TDATA[475]; // rv 0 + assign S_AXIS_DIN_TDATA_in[476] = (S_AXIS_DIN_TDATA[476] !== 1'bz) && S_AXIS_DIN_TDATA[476]; // rv 0 + assign S_AXIS_DIN_TDATA_in[477] = (S_AXIS_DIN_TDATA[477] !== 1'bz) && S_AXIS_DIN_TDATA[477]; // rv 0 + assign S_AXIS_DIN_TDATA_in[478] = (S_AXIS_DIN_TDATA[478] !== 1'bz) && S_AXIS_DIN_TDATA[478]; // rv 0 + assign S_AXIS_DIN_TDATA_in[479] = (S_AXIS_DIN_TDATA[479] !== 1'bz) && S_AXIS_DIN_TDATA[479]; // rv 0 + assign S_AXIS_DIN_TDATA_in[47] = (S_AXIS_DIN_TDATA[47] !== 1'bz) && S_AXIS_DIN_TDATA[47]; // rv 0 + assign S_AXIS_DIN_TDATA_in[480] = (S_AXIS_DIN_TDATA[480] !== 1'bz) && S_AXIS_DIN_TDATA[480]; // rv 0 + assign S_AXIS_DIN_TDATA_in[481] = (S_AXIS_DIN_TDATA[481] !== 1'bz) && S_AXIS_DIN_TDATA[481]; // rv 0 + assign S_AXIS_DIN_TDATA_in[482] = (S_AXIS_DIN_TDATA[482] !== 1'bz) && S_AXIS_DIN_TDATA[482]; // rv 0 + assign S_AXIS_DIN_TDATA_in[483] = (S_AXIS_DIN_TDATA[483] !== 1'bz) && S_AXIS_DIN_TDATA[483]; // rv 0 + assign S_AXIS_DIN_TDATA_in[484] = (S_AXIS_DIN_TDATA[484] !== 1'bz) && S_AXIS_DIN_TDATA[484]; // rv 0 + assign S_AXIS_DIN_TDATA_in[485] = (S_AXIS_DIN_TDATA[485] !== 1'bz) && S_AXIS_DIN_TDATA[485]; // rv 0 + assign S_AXIS_DIN_TDATA_in[486] = (S_AXIS_DIN_TDATA[486] !== 1'bz) && S_AXIS_DIN_TDATA[486]; // rv 0 + assign S_AXIS_DIN_TDATA_in[487] = (S_AXIS_DIN_TDATA[487] !== 1'bz) && S_AXIS_DIN_TDATA[487]; // rv 0 + assign S_AXIS_DIN_TDATA_in[488] = (S_AXIS_DIN_TDATA[488] !== 1'bz) && S_AXIS_DIN_TDATA[488]; // rv 0 + assign S_AXIS_DIN_TDATA_in[489] = (S_AXIS_DIN_TDATA[489] !== 1'bz) && S_AXIS_DIN_TDATA[489]; // rv 0 + assign S_AXIS_DIN_TDATA_in[48] = (S_AXIS_DIN_TDATA[48] !== 1'bz) && S_AXIS_DIN_TDATA[48]; // rv 0 + assign S_AXIS_DIN_TDATA_in[490] = (S_AXIS_DIN_TDATA[490] !== 1'bz) && S_AXIS_DIN_TDATA[490]; // rv 0 + assign S_AXIS_DIN_TDATA_in[491] = (S_AXIS_DIN_TDATA[491] !== 1'bz) && S_AXIS_DIN_TDATA[491]; // rv 0 + assign S_AXIS_DIN_TDATA_in[492] = (S_AXIS_DIN_TDATA[492] !== 1'bz) && S_AXIS_DIN_TDATA[492]; // rv 0 + assign S_AXIS_DIN_TDATA_in[493] = (S_AXIS_DIN_TDATA[493] !== 1'bz) && S_AXIS_DIN_TDATA[493]; // rv 0 + assign S_AXIS_DIN_TDATA_in[494] = (S_AXIS_DIN_TDATA[494] !== 1'bz) && S_AXIS_DIN_TDATA[494]; // rv 0 + assign S_AXIS_DIN_TDATA_in[495] = (S_AXIS_DIN_TDATA[495] !== 1'bz) && S_AXIS_DIN_TDATA[495]; // rv 0 + assign S_AXIS_DIN_TDATA_in[496] = (S_AXIS_DIN_TDATA[496] !== 1'bz) && S_AXIS_DIN_TDATA[496]; // rv 0 + assign S_AXIS_DIN_TDATA_in[497] = (S_AXIS_DIN_TDATA[497] !== 1'bz) && S_AXIS_DIN_TDATA[497]; // rv 0 + assign S_AXIS_DIN_TDATA_in[498] = (S_AXIS_DIN_TDATA[498] !== 1'bz) && S_AXIS_DIN_TDATA[498]; // rv 0 + assign S_AXIS_DIN_TDATA_in[499] = (S_AXIS_DIN_TDATA[499] !== 1'bz) && S_AXIS_DIN_TDATA[499]; // rv 0 + assign S_AXIS_DIN_TDATA_in[49] = (S_AXIS_DIN_TDATA[49] !== 1'bz) && S_AXIS_DIN_TDATA[49]; // rv 0 + assign S_AXIS_DIN_TDATA_in[4] = (S_AXIS_DIN_TDATA[4] !== 1'bz) && S_AXIS_DIN_TDATA[4]; // rv 0 + assign S_AXIS_DIN_TDATA_in[500] = (S_AXIS_DIN_TDATA[500] !== 1'bz) && S_AXIS_DIN_TDATA[500]; // rv 0 + assign S_AXIS_DIN_TDATA_in[501] = (S_AXIS_DIN_TDATA[501] !== 1'bz) && S_AXIS_DIN_TDATA[501]; // rv 0 + assign S_AXIS_DIN_TDATA_in[502] = (S_AXIS_DIN_TDATA[502] !== 1'bz) && S_AXIS_DIN_TDATA[502]; // rv 0 + assign S_AXIS_DIN_TDATA_in[503] = (S_AXIS_DIN_TDATA[503] !== 1'bz) && S_AXIS_DIN_TDATA[503]; // rv 0 + assign S_AXIS_DIN_TDATA_in[504] = (S_AXIS_DIN_TDATA[504] !== 1'bz) && S_AXIS_DIN_TDATA[504]; // rv 0 + assign S_AXIS_DIN_TDATA_in[505] = (S_AXIS_DIN_TDATA[505] !== 1'bz) && S_AXIS_DIN_TDATA[505]; // rv 0 + assign S_AXIS_DIN_TDATA_in[506] = (S_AXIS_DIN_TDATA[506] !== 1'bz) && S_AXIS_DIN_TDATA[506]; // rv 0 + assign S_AXIS_DIN_TDATA_in[507] = (S_AXIS_DIN_TDATA[507] !== 1'bz) && S_AXIS_DIN_TDATA[507]; // rv 0 + assign S_AXIS_DIN_TDATA_in[508] = (S_AXIS_DIN_TDATA[508] !== 1'bz) && S_AXIS_DIN_TDATA[508]; // rv 0 + assign S_AXIS_DIN_TDATA_in[509] = (S_AXIS_DIN_TDATA[509] !== 1'bz) && S_AXIS_DIN_TDATA[509]; // rv 0 + assign S_AXIS_DIN_TDATA_in[50] = (S_AXIS_DIN_TDATA[50] !== 1'bz) && S_AXIS_DIN_TDATA[50]; // rv 0 + assign S_AXIS_DIN_TDATA_in[510] = (S_AXIS_DIN_TDATA[510] !== 1'bz) && S_AXIS_DIN_TDATA[510]; // rv 0 + assign S_AXIS_DIN_TDATA_in[511] = (S_AXIS_DIN_TDATA[511] !== 1'bz) && S_AXIS_DIN_TDATA[511]; // rv 0 + assign S_AXIS_DIN_TDATA_in[51] = (S_AXIS_DIN_TDATA[51] !== 1'bz) && S_AXIS_DIN_TDATA[51]; // rv 0 + assign S_AXIS_DIN_TDATA_in[52] = (S_AXIS_DIN_TDATA[52] !== 1'bz) && S_AXIS_DIN_TDATA[52]; // rv 0 + assign S_AXIS_DIN_TDATA_in[53] = (S_AXIS_DIN_TDATA[53] !== 1'bz) && S_AXIS_DIN_TDATA[53]; // rv 0 + assign S_AXIS_DIN_TDATA_in[54] = (S_AXIS_DIN_TDATA[54] !== 1'bz) && S_AXIS_DIN_TDATA[54]; // rv 0 + assign S_AXIS_DIN_TDATA_in[55] = (S_AXIS_DIN_TDATA[55] !== 1'bz) && S_AXIS_DIN_TDATA[55]; // rv 0 + assign S_AXIS_DIN_TDATA_in[56] = (S_AXIS_DIN_TDATA[56] !== 1'bz) && S_AXIS_DIN_TDATA[56]; // rv 0 + assign S_AXIS_DIN_TDATA_in[57] = (S_AXIS_DIN_TDATA[57] !== 1'bz) && S_AXIS_DIN_TDATA[57]; // rv 0 + assign S_AXIS_DIN_TDATA_in[58] = (S_AXIS_DIN_TDATA[58] !== 1'bz) && S_AXIS_DIN_TDATA[58]; // rv 0 + assign S_AXIS_DIN_TDATA_in[59] = (S_AXIS_DIN_TDATA[59] !== 1'bz) && S_AXIS_DIN_TDATA[59]; // rv 0 + assign S_AXIS_DIN_TDATA_in[5] = (S_AXIS_DIN_TDATA[5] !== 1'bz) && S_AXIS_DIN_TDATA[5]; // rv 0 + assign S_AXIS_DIN_TDATA_in[60] = (S_AXIS_DIN_TDATA[60] !== 1'bz) && S_AXIS_DIN_TDATA[60]; // rv 0 + assign S_AXIS_DIN_TDATA_in[61] = (S_AXIS_DIN_TDATA[61] !== 1'bz) && S_AXIS_DIN_TDATA[61]; // rv 0 + assign S_AXIS_DIN_TDATA_in[62] = (S_AXIS_DIN_TDATA[62] !== 1'bz) && S_AXIS_DIN_TDATA[62]; // rv 0 + assign S_AXIS_DIN_TDATA_in[63] = (S_AXIS_DIN_TDATA[63] !== 1'bz) && S_AXIS_DIN_TDATA[63]; // rv 0 + assign S_AXIS_DIN_TDATA_in[64] = (S_AXIS_DIN_TDATA[64] !== 1'bz) && S_AXIS_DIN_TDATA[64]; // rv 0 + assign S_AXIS_DIN_TDATA_in[65] = (S_AXIS_DIN_TDATA[65] !== 1'bz) && S_AXIS_DIN_TDATA[65]; // rv 0 + assign S_AXIS_DIN_TDATA_in[66] = (S_AXIS_DIN_TDATA[66] !== 1'bz) && S_AXIS_DIN_TDATA[66]; // rv 0 + assign S_AXIS_DIN_TDATA_in[67] = (S_AXIS_DIN_TDATA[67] !== 1'bz) && S_AXIS_DIN_TDATA[67]; // rv 0 + assign S_AXIS_DIN_TDATA_in[68] = (S_AXIS_DIN_TDATA[68] !== 1'bz) && S_AXIS_DIN_TDATA[68]; // rv 0 + assign S_AXIS_DIN_TDATA_in[69] = (S_AXIS_DIN_TDATA[69] !== 1'bz) && S_AXIS_DIN_TDATA[69]; // rv 0 + assign S_AXIS_DIN_TDATA_in[6] = (S_AXIS_DIN_TDATA[6] !== 1'bz) && S_AXIS_DIN_TDATA[6]; // rv 0 + assign S_AXIS_DIN_TDATA_in[70] = (S_AXIS_DIN_TDATA[70] !== 1'bz) && S_AXIS_DIN_TDATA[70]; // rv 0 + assign S_AXIS_DIN_TDATA_in[71] = (S_AXIS_DIN_TDATA[71] !== 1'bz) && S_AXIS_DIN_TDATA[71]; // rv 0 + assign S_AXIS_DIN_TDATA_in[72] = (S_AXIS_DIN_TDATA[72] !== 1'bz) && S_AXIS_DIN_TDATA[72]; // rv 0 + assign S_AXIS_DIN_TDATA_in[73] = (S_AXIS_DIN_TDATA[73] !== 1'bz) && S_AXIS_DIN_TDATA[73]; // rv 0 + assign S_AXIS_DIN_TDATA_in[74] = (S_AXIS_DIN_TDATA[74] !== 1'bz) && S_AXIS_DIN_TDATA[74]; // rv 0 + assign S_AXIS_DIN_TDATA_in[75] = (S_AXIS_DIN_TDATA[75] !== 1'bz) && S_AXIS_DIN_TDATA[75]; // rv 0 + assign S_AXIS_DIN_TDATA_in[76] = (S_AXIS_DIN_TDATA[76] !== 1'bz) && S_AXIS_DIN_TDATA[76]; // rv 0 + assign S_AXIS_DIN_TDATA_in[77] = (S_AXIS_DIN_TDATA[77] !== 1'bz) && S_AXIS_DIN_TDATA[77]; // rv 0 + assign S_AXIS_DIN_TDATA_in[78] = (S_AXIS_DIN_TDATA[78] !== 1'bz) && S_AXIS_DIN_TDATA[78]; // rv 0 + assign S_AXIS_DIN_TDATA_in[79] = (S_AXIS_DIN_TDATA[79] !== 1'bz) && S_AXIS_DIN_TDATA[79]; // rv 0 + assign S_AXIS_DIN_TDATA_in[7] = (S_AXIS_DIN_TDATA[7] !== 1'bz) && S_AXIS_DIN_TDATA[7]; // rv 0 + assign S_AXIS_DIN_TDATA_in[80] = (S_AXIS_DIN_TDATA[80] !== 1'bz) && S_AXIS_DIN_TDATA[80]; // rv 0 + assign S_AXIS_DIN_TDATA_in[81] = (S_AXIS_DIN_TDATA[81] !== 1'bz) && S_AXIS_DIN_TDATA[81]; // rv 0 + assign S_AXIS_DIN_TDATA_in[82] = (S_AXIS_DIN_TDATA[82] !== 1'bz) && S_AXIS_DIN_TDATA[82]; // rv 0 + assign S_AXIS_DIN_TDATA_in[83] = (S_AXIS_DIN_TDATA[83] !== 1'bz) && S_AXIS_DIN_TDATA[83]; // rv 0 + assign S_AXIS_DIN_TDATA_in[84] = (S_AXIS_DIN_TDATA[84] !== 1'bz) && S_AXIS_DIN_TDATA[84]; // rv 0 + assign S_AXIS_DIN_TDATA_in[85] = (S_AXIS_DIN_TDATA[85] !== 1'bz) && S_AXIS_DIN_TDATA[85]; // rv 0 + assign S_AXIS_DIN_TDATA_in[86] = (S_AXIS_DIN_TDATA[86] !== 1'bz) && S_AXIS_DIN_TDATA[86]; // rv 0 + assign S_AXIS_DIN_TDATA_in[87] = (S_AXIS_DIN_TDATA[87] !== 1'bz) && S_AXIS_DIN_TDATA[87]; // rv 0 + assign S_AXIS_DIN_TDATA_in[88] = (S_AXIS_DIN_TDATA[88] !== 1'bz) && S_AXIS_DIN_TDATA[88]; // rv 0 + assign S_AXIS_DIN_TDATA_in[89] = (S_AXIS_DIN_TDATA[89] !== 1'bz) && S_AXIS_DIN_TDATA[89]; // rv 0 + assign S_AXIS_DIN_TDATA_in[8] = (S_AXIS_DIN_TDATA[8] !== 1'bz) && S_AXIS_DIN_TDATA[8]; // rv 0 + assign S_AXIS_DIN_TDATA_in[90] = (S_AXIS_DIN_TDATA[90] !== 1'bz) && S_AXIS_DIN_TDATA[90]; // rv 0 + assign S_AXIS_DIN_TDATA_in[91] = (S_AXIS_DIN_TDATA[91] !== 1'bz) && S_AXIS_DIN_TDATA[91]; // rv 0 + assign S_AXIS_DIN_TDATA_in[92] = (S_AXIS_DIN_TDATA[92] !== 1'bz) && S_AXIS_DIN_TDATA[92]; // rv 0 + assign S_AXIS_DIN_TDATA_in[93] = (S_AXIS_DIN_TDATA[93] !== 1'bz) && S_AXIS_DIN_TDATA[93]; // rv 0 + assign S_AXIS_DIN_TDATA_in[94] = (S_AXIS_DIN_TDATA[94] !== 1'bz) && S_AXIS_DIN_TDATA[94]; // rv 0 + assign S_AXIS_DIN_TDATA_in[95] = (S_AXIS_DIN_TDATA[95] !== 1'bz) && S_AXIS_DIN_TDATA[95]; // rv 0 + assign S_AXIS_DIN_TDATA_in[96] = (S_AXIS_DIN_TDATA[96] !== 1'bz) && S_AXIS_DIN_TDATA[96]; // rv 0 + assign S_AXIS_DIN_TDATA_in[97] = (S_AXIS_DIN_TDATA[97] !== 1'bz) && S_AXIS_DIN_TDATA[97]; // rv 0 + assign S_AXIS_DIN_TDATA_in[98] = (S_AXIS_DIN_TDATA[98] !== 1'bz) && S_AXIS_DIN_TDATA[98]; // rv 0 + assign S_AXIS_DIN_TDATA_in[99] = (S_AXIS_DIN_TDATA[99] !== 1'bz) && S_AXIS_DIN_TDATA[99]; // rv 0 + assign S_AXIS_DIN_TDATA_in[9] = (S_AXIS_DIN_TDATA[9] !== 1'bz) && S_AXIS_DIN_TDATA[9]; // rv 0 + assign S_AXIS_DIN_TLAST_in = (S_AXIS_DIN_TLAST !== 1'bz) && S_AXIS_DIN_TLAST; // rv 0 + assign S_AXIS_DIN_TVALID_in = (S_AXIS_DIN_TVALID !== 1'bz) && S_AXIS_DIN_TVALID; // rv 0 + assign S_AXIS_DIN_WORDS_ACLK_in = (S_AXIS_DIN_WORDS_ACLK !== 1'bz) && S_AXIS_DIN_WORDS_ACLK; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[0] = (S_AXIS_DIN_WORDS_TDATA[0] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[0]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[10] = (S_AXIS_DIN_WORDS_TDATA[10] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[10]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[11] = (S_AXIS_DIN_WORDS_TDATA[11] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[11]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[12] = (S_AXIS_DIN_WORDS_TDATA[12] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[12]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[13] = (S_AXIS_DIN_WORDS_TDATA[13] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[13]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[14] = (S_AXIS_DIN_WORDS_TDATA[14] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[14]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[15] = (S_AXIS_DIN_WORDS_TDATA[15] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[15]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[16] = (S_AXIS_DIN_WORDS_TDATA[16] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[16]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[17] = (S_AXIS_DIN_WORDS_TDATA[17] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[17]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[18] = (S_AXIS_DIN_WORDS_TDATA[18] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[18]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[19] = (S_AXIS_DIN_WORDS_TDATA[19] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[19]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[1] = (S_AXIS_DIN_WORDS_TDATA[1] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[1]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[20] = (S_AXIS_DIN_WORDS_TDATA[20] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[20]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[21] = (S_AXIS_DIN_WORDS_TDATA[21] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[21]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[22] = (S_AXIS_DIN_WORDS_TDATA[22] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[22]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[23] = (S_AXIS_DIN_WORDS_TDATA[23] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[23]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[24] = (S_AXIS_DIN_WORDS_TDATA[24] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[24]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[25] = (S_AXIS_DIN_WORDS_TDATA[25] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[25]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[26] = (S_AXIS_DIN_WORDS_TDATA[26] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[26]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[27] = (S_AXIS_DIN_WORDS_TDATA[27] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[27]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[28] = (S_AXIS_DIN_WORDS_TDATA[28] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[28]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[29] = (S_AXIS_DIN_WORDS_TDATA[29] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[29]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[2] = (S_AXIS_DIN_WORDS_TDATA[2] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[2]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[30] = (S_AXIS_DIN_WORDS_TDATA[30] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[30]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[31] = (S_AXIS_DIN_WORDS_TDATA[31] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[31]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[3] = (S_AXIS_DIN_WORDS_TDATA[3] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[3]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[4] = (S_AXIS_DIN_WORDS_TDATA[4] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[4]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[5] = (S_AXIS_DIN_WORDS_TDATA[5] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[5]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[6] = (S_AXIS_DIN_WORDS_TDATA[6] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[6]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[7] = (S_AXIS_DIN_WORDS_TDATA[7] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[7]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[8] = (S_AXIS_DIN_WORDS_TDATA[8] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[8]; // rv 0 + assign S_AXIS_DIN_WORDS_TDATA_in[9] = (S_AXIS_DIN_WORDS_TDATA[9] !== 1'bz) && S_AXIS_DIN_WORDS_TDATA[9]; // rv 0 + assign S_AXIS_DIN_WORDS_TLAST_in = (S_AXIS_DIN_WORDS_TLAST !== 1'bz) && S_AXIS_DIN_WORDS_TLAST; // rv 0 + assign S_AXIS_DIN_WORDS_TVALID_in = (S_AXIS_DIN_WORDS_TVALID !== 1'bz) && S_AXIS_DIN_WORDS_TVALID; // rv 0 + assign S_AXIS_DOUT_WORDS_ACLK_in = (S_AXIS_DOUT_WORDS_ACLK !== 1'bz) && S_AXIS_DOUT_WORDS_ACLK; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[0] = (S_AXIS_DOUT_WORDS_TDATA[0] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[0]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[10] = (S_AXIS_DOUT_WORDS_TDATA[10] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[10]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[11] = (S_AXIS_DOUT_WORDS_TDATA[11] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[11]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[12] = (S_AXIS_DOUT_WORDS_TDATA[12] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[12]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[13] = (S_AXIS_DOUT_WORDS_TDATA[13] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[13]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[14] = (S_AXIS_DOUT_WORDS_TDATA[14] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[14]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[15] = (S_AXIS_DOUT_WORDS_TDATA[15] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[15]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[16] = (S_AXIS_DOUT_WORDS_TDATA[16] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[16]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[17] = (S_AXIS_DOUT_WORDS_TDATA[17] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[17]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[18] = (S_AXIS_DOUT_WORDS_TDATA[18] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[18]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[19] = (S_AXIS_DOUT_WORDS_TDATA[19] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[19]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[1] = (S_AXIS_DOUT_WORDS_TDATA[1] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[1]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[20] = (S_AXIS_DOUT_WORDS_TDATA[20] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[20]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[21] = (S_AXIS_DOUT_WORDS_TDATA[21] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[21]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[22] = (S_AXIS_DOUT_WORDS_TDATA[22] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[22]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[23] = (S_AXIS_DOUT_WORDS_TDATA[23] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[23]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[24] = (S_AXIS_DOUT_WORDS_TDATA[24] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[24]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[25] = (S_AXIS_DOUT_WORDS_TDATA[25] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[25]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[26] = (S_AXIS_DOUT_WORDS_TDATA[26] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[26]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[27] = (S_AXIS_DOUT_WORDS_TDATA[27] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[27]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[28] = (S_AXIS_DOUT_WORDS_TDATA[28] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[28]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[29] = (S_AXIS_DOUT_WORDS_TDATA[29] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[29]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[2] = (S_AXIS_DOUT_WORDS_TDATA[2] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[2]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[30] = (S_AXIS_DOUT_WORDS_TDATA[30] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[30]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[31] = (S_AXIS_DOUT_WORDS_TDATA[31] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[31]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[3] = (S_AXIS_DOUT_WORDS_TDATA[3] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[3]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[4] = (S_AXIS_DOUT_WORDS_TDATA[4] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[4]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[5] = (S_AXIS_DOUT_WORDS_TDATA[5] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[5]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[6] = (S_AXIS_DOUT_WORDS_TDATA[6] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[6]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[7] = (S_AXIS_DOUT_WORDS_TDATA[7] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[7]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[8] = (S_AXIS_DOUT_WORDS_TDATA[8] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[8]; // rv 0 + assign S_AXIS_DOUT_WORDS_TDATA_in[9] = (S_AXIS_DOUT_WORDS_TDATA[9] !== 1'bz) && S_AXIS_DOUT_WORDS_TDATA[9]; // rv 0 + assign S_AXIS_DOUT_WORDS_TLAST_in = (S_AXIS_DOUT_WORDS_TLAST !== 1'bz) && S_AXIS_DOUT_WORDS_TLAST; // rv 0 + assign S_AXIS_DOUT_WORDS_TVALID_in = (S_AXIS_DOUT_WORDS_TVALID !== 1'bz) && S_AXIS_DOUT_WORDS_TVALID; // rv 0 + assign S_AXI_ACLK_in = (S_AXI_ACLK !== 1'bz) && S_AXI_ACLK; // rv 0 + assign S_AXI_ARADDR_in[0] = (S_AXI_ARADDR[0] !== 1'bz) && S_AXI_ARADDR[0]; // rv 0 + assign S_AXI_ARADDR_in[10] = (S_AXI_ARADDR[10] !== 1'bz) && S_AXI_ARADDR[10]; // rv 0 + assign S_AXI_ARADDR_in[11] = (S_AXI_ARADDR[11] !== 1'bz) && S_AXI_ARADDR[11]; // rv 0 + assign S_AXI_ARADDR_in[12] = (S_AXI_ARADDR[12] !== 1'bz) && S_AXI_ARADDR[12]; // rv 0 + assign S_AXI_ARADDR_in[13] = (S_AXI_ARADDR[13] !== 1'bz) && S_AXI_ARADDR[13]; // rv 0 + assign S_AXI_ARADDR_in[14] = (S_AXI_ARADDR[14] !== 1'bz) && S_AXI_ARADDR[14]; // rv 0 + assign S_AXI_ARADDR_in[15] = (S_AXI_ARADDR[15] !== 1'bz) && S_AXI_ARADDR[15]; // rv 0 + assign S_AXI_ARADDR_in[16] = (S_AXI_ARADDR[16] !== 1'bz) && S_AXI_ARADDR[16]; // rv 0 + assign S_AXI_ARADDR_in[17] = (S_AXI_ARADDR[17] !== 1'bz) && S_AXI_ARADDR[17]; // rv 0 + assign S_AXI_ARADDR_in[1] = (S_AXI_ARADDR[1] !== 1'bz) && S_AXI_ARADDR[1]; // rv 0 + assign S_AXI_ARADDR_in[2] = (S_AXI_ARADDR[2] !== 1'bz) && S_AXI_ARADDR[2]; // rv 0 + assign S_AXI_ARADDR_in[3] = (S_AXI_ARADDR[3] !== 1'bz) && S_AXI_ARADDR[3]; // rv 0 + assign S_AXI_ARADDR_in[4] = (S_AXI_ARADDR[4] !== 1'bz) && S_AXI_ARADDR[4]; // rv 0 + assign S_AXI_ARADDR_in[5] = (S_AXI_ARADDR[5] !== 1'bz) && S_AXI_ARADDR[5]; // rv 0 + assign S_AXI_ARADDR_in[6] = (S_AXI_ARADDR[6] !== 1'bz) && S_AXI_ARADDR[6]; // rv 0 + assign S_AXI_ARADDR_in[7] = (S_AXI_ARADDR[7] !== 1'bz) && S_AXI_ARADDR[7]; // rv 0 + assign S_AXI_ARADDR_in[8] = (S_AXI_ARADDR[8] !== 1'bz) && S_AXI_ARADDR[8]; // rv 0 + assign S_AXI_ARADDR_in[9] = (S_AXI_ARADDR[9] !== 1'bz) && S_AXI_ARADDR[9]; // rv 0 + assign S_AXI_ARVALID_in = (S_AXI_ARVALID !== 1'bz) && S_AXI_ARVALID; // rv 0 + assign S_AXI_AWADDR_in[0] = (S_AXI_AWADDR[0] !== 1'bz) && S_AXI_AWADDR[0]; // rv 0 + assign S_AXI_AWADDR_in[10] = (S_AXI_AWADDR[10] !== 1'bz) && S_AXI_AWADDR[10]; // rv 0 + assign S_AXI_AWADDR_in[11] = (S_AXI_AWADDR[11] !== 1'bz) && S_AXI_AWADDR[11]; // rv 0 + assign S_AXI_AWADDR_in[12] = (S_AXI_AWADDR[12] !== 1'bz) && S_AXI_AWADDR[12]; // rv 0 + assign S_AXI_AWADDR_in[13] = (S_AXI_AWADDR[13] !== 1'bz) && S_AXI_AWADDR[13]; // rv 0 + assign S_AXI_AWADDR_in[14] = (S_AXI_AWADDR[14] !== 1'bz) && S_AXI_AWADDR[14]; // rv 0 + assign S_AXI_AWADDR_in[15] = (S_AXI_AWADDR[15] !== 1'bz) && S_AXI_AWADDR[15]; // rv 0 + assign S_AXI_AWADDR_in[16] = (S_AXI_AWADDR[16] !== 1'bz) && S_AXI_AWADDR[16]; // rv 0 + assign S_AXI_AWADDR_in[17] = (S_AXI_AWADDR[17] !== 1'bz) && S_AXI_AWADDR[17]; // rv 0 + assign S_AXI_AWADDR_in[1] = (S_AXI_AWADDR[1] !== 1'bz) && S_AXI_AWADDR[1]; // rv 0 + assign S_AXI_AWADDR_in[2] = (S_AXI_AWADDR[2] !== 1'bz) && S_AXI_AWADDR[2]; // rv 0 + assign S_AXI_AWADDR_in[3] = (S_AXI_AWADDR[3] !== 1'bz) && S_AXI_AWADDR[3]; // rv 0 + assign S_AXI_AWADDR_in[4] = (S_AXI_AWADDR[4] !== 1'bz) && S_AXI_AWADDR[4]; // rv 0 + assign S_AXI_AWADDR_in[5] = (S_AXI_AWADDR[5] !== 1'bz) && S_AXI_AWADDR[5]; // rv 0 + assign S_AXI_AWADDR_in[6] = (S_AXI_AWADDR[6] !== 1'bz) && S_AXI_AWADDR[6]; // rv 0 + assign S_AXI_AWADDR_in[7] = (S_AXI_AWADDR[7] !== 1'bz) && S_AXI_AWADDR[7]; // rv 0 + assign S_AXI_AWADDR_in[8] = (S_AXI_AWADDR[8] !== 1'bz) && S_AXI_AWADDR[8]; // rv 0 + assign S_AXI_AWADDR_in[9] = (S_AXI_AWADDR[9] !== 1'bz) && S_AXI_AWADDR[9]; // rv 0 + assign S_AXI_AWVALID_in = (S_AXI_AWVALID !== 1'bz) && S_AXI_AWVALID; // rv 0 + assign S_AXI_BREADY_in = (S_AXI_BREADY !== 1'bz) && S_AXI_BREADY; // rv 0 + assign S_AXI_RREADY_in = (S_AXI_RREADY !== 1'bz) && S_AXI_RREADY; // rv 0 + assign S_AXI_WDATA_in[0] = (S_AXI_WDATA[0] !== 1'bz) && S_AXI_WDATA[0]; // rv 0 + assign S_AXI_WDATA_in[10] = (S_AXI_WDATA[10] !== 1'bz) && S_AXI_WDATA[10]; // rv 0 + assign S_AXI_WDATA_in[11] = (S_AXI_WDATA[11] !== 1'bz) && S_AXI_WDATA[11]; // rv 0 + assign S_AXI_WDATA_in[12] = (S_AXI_WDATA[12] !== 1'bz) && S_AXI_WDATA[12]; // rv 0 + assign S_AXI_WDATA_in[13] = (S_AXI_WDATA[13] !== 1'bz) && S_AXI_WDATA[13]; // rv 0 + assign S_AXI_WDATA_in[14] = (S_AXI_WDATA[14] !== 1'bz) && S_AXI_WDATA[14]; // rv 0 + assign S_AXI_WDATA_in[15] = (S_AXI_WDATA[15] !== 1'bz) && S_AXI_WDATA[15]; // rv 0 + assign S_AXI_WDATA_in[16] = (S_AXI_WDATA[16] !== 1'bz) && S_AXI_WDATA[16]; // rv 0 + assign S_AXI_WDATA_in[17] = (S_AXI_WDATA[17] !== 1'bz) && S_AXI_WDATA[17]; // rv 0 + assign S_AXI_WDATA_in[18] = (S_AXI_WDATA[18] !== 1'bz) && S_AXI_WDATA[18]; // rv 0 + assign S_AXI_WDATA_in[19] = (S_AXI_WDATA[19] !== 1'bz) && S_AXI_WDATA[19]; // rv 0 + assign S_AXI_WDATA_in[1] = (S_AXI_WDATA[1] !== 1'bz) && S_AXI_WDATA[1]; // rv 0 + assign S_AXI_WDATA_in[20] = (S_AXI_WDATA[20] !== 1'bz) && S_AXI_WDATA[20]; // rv 0 + assign S_AXI_WDATA_in[21] = (S_AXI_WDATA[21] !== 1'bz) && S_AXI_WDATA[21]; // rv 0 + assign S_AXI_WDATA_in[22] = (S_AXI_WDATA[22] !== 1'bz) && S_AXI_WDATA[22]; // rv 0 + assign S_AXI_WDATA_in[23] = (S_AXI_WDATA[23] !== 1'bz) && S_AXI_WDATA[23]; // rv 0 + assign S_AXI_WDATA_in[24] = (S_AXI_WDATA[24] !== 1'bz) && S_AXI_WDATA[24]; // rv 0 + assign S_AXI_WDATA_in[25] = (S_AXI_WDATA[25] !== 1'bz) && S_AXI_WDATA[25]; // rv 0 + assign S_AXI_WDATA_in[26] = (S_AXI_WDATA[26] !== 1'bz) && S_AXI_WDATA[26]; // rv 0 + assign S_AXI_WDATA_in[27] = (S_AXI_WDATA[27] !== 1'bz) && S_AXI_WDATA[27]; // rv 0 + assign S_AXI_WDATA_in[28] = (S_AXI_WDATA[28] !== 1'bz) && S_AXI_WDATA[28]; // rv 0 + assign S_AXI_WDATA_in[29] = (S_AXI_WDATA[29] !== 1'bz) && S_AXI_WDATA[29]; // rv 0 + assign S_AXI_WDATA_in[2] = (S_AXI_WDATA[2] !== 1'bz) && S_AXI_WDATA[2]; // rv 0 + assign S_AXI_WDATA_in[30] = (S_AXI_WDATA[30] !== 1'bz) && S_AXI_WDATA[30]; // rv 0 + assign S_AXI_WDATA_in[31] = (S_AXI_WDATA[31] !== 1'bz) && S_AXI_WDATA[31]; // rv 0 + assign S_AXI_WDATA_in[3] = (S_AXI_WDATA[3] !== 1'bz) && S_AXI_WDATA[3]; // rv 0 + assign S_AXI_WDATA_in[4] = (S_AXI_WDATA[4] !== 1'bz) && S_AXI_WDATA[4]; // rv 0 + assign S_AXI_WDATA_in[5] = (S_AXI_WDATA[5] !== 1'bz) && S_AXI_WDATA[5]; // rv 0 + assign S_AXI_WDATA_in[6] = (S_AXI_WDATA[6] !== 1'bz) && S_AXI_WDATA[6]; // rv 0 + assign S_AXI_WDATA_in[7] = (S_AXI_WDATA[7] !== 1'bz) && S_AXI_WDATA[7]; // rv 0 + assign S_AXI_WDATA_in[8] = (S_AXI_WDATA[8] !== 1'bz) && S_AXI_WDATA[8]; // rv 0 + assign S_AXI_WDATA_in[9] = (S_AXI_WDATA[9] !== 1'bz) && S_AXI_WDATA[9]; // rv 0 + assign S_AXI_WVALID_in = (S_AXI_WVALID !== 1'bz) && S_AXI_WVALID; // rv 0 +`endif + + assign DEBUG_CLK_EN_in = (DEBUG_CLK_EN !== 1'bz) && DEBUG_CLK_EN; // rv 0 + assign DEBUG_SEL_IN_in[0] = (DEBUG_SEL_IN[0] !== 1'bz) && DEBUG_SEL_IN[0]; // rv 0 + assign DEBUG_SEL_IN_in[1] = (DEBUG_SEL_IN[1] !== 1'bz) && DEBUG_SEL_IN[1]; // rv 0 + assign DEBUG_SEL_IN_in[2] = (DEBUG_SEL_IN[2] !== 1'bz) && DEBUG_SEL_IN[2]; // rv 0 + assign DEBUG_SEL_IN_in[3] = (DEBUG_SEL_IN[3] !== 1'bz) && DEBUG_SEL_IN[3]; // rv 0 + assign RESET_N_in = (RESET_N === 1'bz) || RESET_N; // rv 1 + assign SPARE_IN_in[0] = (SPARE_IN[0] !== 1'bz) && SPARE_IN[0]; // rv 0 + assign SPARE_IN_in[10] = (SPARE_IN[10] !== 1'bz) && SPARE_IN[10]; // rv 0 + assign SPARE_IN_in[11] = (SPARE_IN[11] !== 1'bz) && SPARE_IN[11]; // rv 0 + assign SPARE_IN_in[12] = (SPARE_IN[12] !== 1'bz) && SPARE_IN[12]; // rv 0 + assign SPARE_IN_in[13] = (SPARE_IN[13] !== 1'bz) && SPARE_IN[13]; // rv 0 + assign SPARE_IN_in[14] = (SPARE_IN[14] !== 1'bz) && SPARE_IN[14]; // rv 0 + assign SPARE_IN_in[15] = (SPARE_IN[15] !== 1'bz) && SPARE_IN[15]; // rv 0 + assign SPARE_IN_in[1] = (SPARE_IN[1] !== 1'bz) && SPARE_IN[1]; // rv 0 + assign SPARE_IN_in[2] = (SPARE_IN[2] !== 1'bz) && SPARE_IN[2]; // rv 0 + assign SPARE_IN_in[3] = (SPARE_IN[3] !== 1'bz) && SPARE_IN[3]; // rv 0 + assign SPARE_IN_in[4] = (SPARE_IN[4] !== 1'bz) && SPARE_IN[4]; // rv 0 + assign SPARE_IN_in[5] = (SPARE_IN[5] !== 1'bz) && SPARE_IN[5]; // rv 0 + assign SPARE_IN_in[6] = (SPARE_IN[6] !== 1'bz) && SPARE_IN[6]; // rv 0 + assign SPARE_IN_in[7] = (SPARE_IN[7] !== 1'bz) && SPARE_IN[7]; // rv 0 + assign SPARE_IN_in[8] = (SPARE_IN[8] !== 1'bz) && SPARE_IN[8]; // rv 0 + assign SPARE_IN_in[9] = (SPARE_IN[9] !== 1'bz) && SPARE_IN[9]; // rv 0 + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign PHYSICAL_UTILIZATION_BIN = PHYSICAL_UTILIZATION_REG * 1000; + + assign THROUGHPUT_UTILIZATION_BIN = THROUGHPUT_UTILIZATION_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + PHYSICAL_UTILIZATION_BIN = PHYSICAL_UTILIZATION_REG * 1000; + + THROUGHPUT_UTILIZATION_BIN = THROUGHPUT_UTILIZATION_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((MODE_REG != "TURBO_DECODE") && + (MODE_REG != "LDPC_DECODE") && + (MODE_REG != "LDPC_ENCODE"))) begin + $display("Error: [Unisim %s-101] MODE attribute is set to %s. Legal values for this attribute are TURBO_DECODE, LDPC_DECODE or LDPC_ENCODE. Instance: %m", MODULE_NAME, MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (PHYSICAL_UTILIZATION_REG < 0.00 || PHYSICAL_UTILIZATION_REG > 100.00)) begin + $display("Error: [Unisim %s-102] PHYSICAL_UTILIZATION attribute is set to %f. Legal values for this attribute are 0.00 to 100.00. Instance: %m", MODULE_NAME, PHYSICAL_UTILIZATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-103] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STANDARD_REG != "LTE") && + (STANDARD_REG != "5G") && + (STANDARD_REG != "CUSTOM") && + (STANDARD_REG != "DOCSIS") && + (STANDARD_REG != "WIFI"))) begin + $display("Error: [Unisim %s-104] STANDARD attribute is set to %s. Legal values for this attribute are LTE, 5G, CUSTOM, DOCSIS or WIFI. Instance: %m", MODULE_NAME, STANDARD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (THROUGHPUT_UTILIZATION_REG < 0.00 || THROUGHPUT_UTILIZATION_REG > 100.00)) begin + $display("Error: [Unisim %s-105] THROUGHPUT_UTILIZATION attribute is set to %f. Legal values for this attribute are 0.00 to 100.00. Instance: %m", MODULE_NAME, THROUGHPUT_UTILIZATION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + +assign MBIST_TCK_in = 1'b1; // tie off +assign SCAN_CLK_in = 1'b1; // tie off +assign XIL_UNCONN_CLK_in = 470'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + +assign CSSD_CLK_STOP_EVENT_in = 4'b1111; // tie off +assign CSSD_RST_N_in = 1'b1; // tie off +assign CTL_CSSD_EN_N_in = 1'b1; // tie off +assign CTL_CSSD_MRKR_START_INIT_in = 16'b1111111111111111; // tie off +assign CTL_CSSD_MRKR_STOP_INIT_in = 16'b1111111111111111; // tie off +assign CTL_CSSD_ROOT_CLK_DIS_in = 8'b11111111; // tie off +assign CTL_CSSD_ROOT_CLK_SEL_in = 3'b111; // tie off +assign CTL_CSSD_SNGL_CHAIN_MD_N_in = 1'b1; // tie off +assign CTL_CSSD_STOP_COUNT_in = 48'b111111111111111111111111111111111111111111111111; // tie off +assign DFTRAM_BYPASS_N_in = 1'b1; // tie off +assign MBIST_TDI_in = 1'b1; // tie off +assign MBIST_TMS_in = 1'b1; // tie off +assign MBIST_TRST_in = 1'b1; // tie off +assign SCANENABLE_N_in = 1'b1; // tie off +assign SCANIN_in = 200'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off +assign SCANMODE_N_in = 1'b1; // tie off +assign TEST_MODE_PIN_CHAR_N_in = 1'b1; // tie off +assign XIL_UNCONN_IN_in = 1862'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + +SIP_FE SIP_FE_INST ( +.CSSD_CLK_STOP_DONE (CSSD_CLK_STOP_DONE_out), +.DEBUG_DOUT (DEBUG_DOUT_out), +.DEBUG_PHASE (DEBUG_PHASE_out), +.INTERRUPT (INTERRUPT_out), +.MBIST_COMPSTAT (MBIST_COMPSTAT_out), +.MBIST_TDO (MBIST_TDO_out), +.M_AXIS_DOUT_TDATA (M_AXIS_DOUT_TDATA_out), +.M_AXIS_DOUT_TLAST (M_AXIS_DOUT_TLAST_out), +.M_AXIS_DOUT_TVALID (M_AXIS_DOUT_TVALID_out), +.M_AXIS_STATUS_TDATA (M_AXIS_STATUS_TDATA_out), +.M_AXIS_STATUS_TVALID (M_AXIS_STATUS_TVALID_out), +.SCANOUT (SCANOUT_out), +.SPARE_OUT (SPARE_OUT_out), +.S_AXIS_CTRL_TREADY (S_AXIS_CTRL_TREADY_out), +.S_AXIS_DIN_TREADY (S_AXIS_DIN_TREADY_out), +.S_AXIS_DIN_WORDS_TREADY (S_AXIS_DIN_WORDS_TREADY_out), +.S_AXIS_DOUT_WORDS_TREADY (S_AXIS_DOUT_WORDS_TREADY_out), +.S_AXI_ARREADY (S_AXI_ARREADY_out), +.S_AXI_AWREADY (S_AXI_AWREADY_out), +.S_AXI_BVALID (S_AXI_BVALID_out), +.S_AXI_RDATA (S_AXI_RDATA_out), +.S_AXI_RVALID (S_AXI_RVALID_out), +.S_AXI_WREADY (S_AXI_WREADY_out), +.XIL_UNCONN_OUT (XIL_UNCONN_OUT_out), +.CORE_CLK (CORE_CLK_in), +.CSSD_CLK_STOP_EVENT (CSSD_CLK_STOP_EVENT_in), +.CSSD_RST_N (CSSD_RST_N_in), +.CTL_CSSD_EN_N (CTL_CSSD_EN_N_in), +.CTL_CSSD_MRKR_START_INIT (CTL_CSSD_MRKR_START_INIT_in), +.CTL_CSSD_MRKR_STOP_INIT (CTL_CSSD_MRKR_STOP_INIT_in), +.CTL_CSSD_ROOT_CLK_DIS (CTL_CSSD_ROOT_CLK_DIS_in), +.CTL_CSSD_ROOT_CLK_SEL (CTL_CSSD_ROOT_CLK_SEL_in), +.CTL_CSSD_SNGL_CHAIN_MD_N (CTL_CSSD_SNGL_CHAIN_MD_N_in), +.CTL_CSSD_STOP_COUNT (CTL_CSSD_STOP_COUNT_in), +.DEBUG_CLK_EN (DEBUG_CLK_EN_in), +.DEBUG_EN (DEBUG_EN_in), +.DEBUG_SEL_IN (DEBUG_SEL_IN_in), +.DFTRAM_BYPASS_N (DFTRAM_BYPASS_N_in), +.MBIST_TCK (MBIST_TCK_in), +.MBIST_TDI (MBIST_TDI_in), +.MBIST_TMS (MBIST_TMS_in), +.MBIST_TRST (MBIST_TRST_in), +.M_AXIS_DOUT_ACLK (M_AXIS_DOUT_ACLK_in), +.M_AXIS_DOUT_TREADY (M_AXIS_DOUT_TREADY_in), +.M_AXIS_STATUS_ACLK (M_AXIS_STATUS_ACLK_in), +.M_AXIS_STATUS_TREADY (M_AXIS_STATUS_TREADY_in), +.RESET_N (RESET_N_in), +.SCANENABLE_N (SCANENABLE_N_in), +.SCANIN (SCANIN_in), +.SCANMODE_N (SCANMODE_N_in), +.SCAN_CLK (SCAN_CLK_in), +.SPARE_IN (SPARE_IN_in), +.S_AXIS_CTRL_ACLK (S_AXIS_CTRL_ACLK_in), +.S_AXIS_CTRL_TDATA (S_AXIS_CTRL_TDATA_in), +.S_AXIS_CTRL_TVALID (S_AXIS_CTRL_TVALID_in), +.S_AXIS_DIN_ACLK (S_AXIS_DIN_ACLK_in), +.S_AXIS_DIN_TDATA (S_AXIS_DIN_TDATA_in), +.S_AXIS_DIN_TLAST (S_AXIS_DIN_TLAST_in), +.S_AXIS_DIN_TVALID (S_AXIS_DIN_TVALID_in), +.S_AXIS_DIN_WORDS_ACLK (S_AXIS_DIN_WORDS_ACLK_in), +.S_AXIS_DIN_WORDS_TDATA (S_AXIS_DIN_WORDS_TDATA_in), +.S_AXIS_DIN_WORDS_TLAST (S_AXIS_DIN_WORDS_TLAST_in), +.S_AXIS_DIN_WORDS_TVALID (S_AXIS_DIN_WORDS_TVALID_in), +.S_AXIS_DOUT_WORDS_ACLK (S_AXIS_DOUT_WORDS_ACLK_in), +.S_AXIS_DOUT_WORDS_TDATA (S_AXIS_DOUT_WORDS_TDATA_in), +.S_AXIS_DOUT_WORDS_TLAST (S_AXIS_DOUT_WORDS_TLAST_in), +.S_AXIS_DOUT_WORDS_TVALID (S_AXIS_DOUT_WORDS_TVALID_in), +.S_AXI_ACLK (S_AXI_ACLK_in), +.S_AXI_ARADDR (S_AXI_ARADDR_in), +.S_AXI_ARVALID (S_AXI_ARVALID_in), +.S_AXI_AWADDR (S_AXI_AWADDR_in), +.S_AXI_AWVALID (S_AXI_AWVALID_in), +.S_AXI_BREADY (S_AXI_BREADY_in), +.S_AXI_RREADY (S_AXI_RREADY_in), +.S_AXI_WDATA (S_AXI_WDATA_in), +.S_AXI_WVALID (S_AXI_WVALID_in), +.TEST_MODE_PIN_CHAR_N (TEST_MODE_PIN_CHAR_N_in), +.XIL_UNCONN_CLK (XIL_UNCONN_CLK_in), +.XIL_UNCONN_IN (XIL_UNCONN_IN_in), +.GSR (glblGSR) +); + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_XECLIB + specify + (CORE_CLK => DEBUG_DOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[100]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[101]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[102]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[103]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[104]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[105]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[106]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[107]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[108]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[109]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[110]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[111]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[112]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[113]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[114]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[115]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[116]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[117]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[118]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[119]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[120]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[121]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[122]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[123]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[124]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[125]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[126]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[127]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[128]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[129]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[12]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[130]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[131]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[132]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[133]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[134]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[135]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[136]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[137]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[138]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[139]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[13]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[140]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[141]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[142]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[143]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[144]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[145]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[146]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[147]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[148]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[149]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[14]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[150]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[151]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[152]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[153]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[154]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[155]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[156]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[157]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[158]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[159]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[15]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[160]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[161]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[162]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[163]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[164]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[165]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[166]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[167]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[168]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[169]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[16]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[170]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[171]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[172]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[173]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[174]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[175]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[176]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[177]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[178]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[179]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[17]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[180]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[181]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[182]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[183]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[184]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[185]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[186]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[187]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[188]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[189]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[18]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[190]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[191]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[192]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[193]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[194]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[195]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[196]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[197]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[198]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[199]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[19]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[200]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[201]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[202]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[203]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[204]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[205]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[206]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[207]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[208]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[209]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[20]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[210]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[211]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[212]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[213]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[214]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[215]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[216]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[217]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[218]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[219]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[21]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[220]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[221]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[222]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[223]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[224]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[225]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[226]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[227]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[228]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[229]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[22]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[230]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[231]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[232]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[233]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[234]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[235]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[236]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[237]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[238]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[239]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[23]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[240]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[241]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[242]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[243]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[244]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[245]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[246]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[247]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[248]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[249]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[24]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[250]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[251]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[252]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[253]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[254]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[255]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[256]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[257]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[258]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[259]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[25]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[260]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[261]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[262]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[263]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[264]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[265]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[266]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[267]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[268]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[269]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[26]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[270]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[271]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[272]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[273]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[274]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[275]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[276]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[277]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[278]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[279]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[27]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[280]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[281]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[282]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[283]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[284]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[285]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[286]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[287]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[288]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[289]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[28]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[290]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[291]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[292]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[293]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[294]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[295]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[296]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[297]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[298]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[299]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[29]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[300]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[301]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[302]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[303]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[304]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[305]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[306]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[307]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[308]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[309]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[30]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[310]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[311]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[312]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[313]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[314]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[315]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[316]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[317]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[318]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[319]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[31]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[320]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[321]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[322]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[323]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[324]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[325]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[326]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[327]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[328]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[329]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[32]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[330]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[331]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[332]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[333]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[334]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[335]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[336]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[337]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[338]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[339]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[33]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[340]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[341]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[342]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[343]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[344]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[345]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[346]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[347]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[348]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[349]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[34]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[350]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[351]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[352]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[353]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[354]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[355]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[356]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[357]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[358]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[359]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[35]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[360]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[361]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[362]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[363]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[364]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[365]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[366]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[367]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[368]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[369]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[36]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[370]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[371]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[372]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[373]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[374]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[375]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[376]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[377]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[378]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[379]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[37]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[380]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[381]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[382]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[383]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[384]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[385]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[386]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[387]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[388]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[389]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[38]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[390]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[391]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[392]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[393]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[394]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[395]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[396]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[397]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[398]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[399]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[39]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[40]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[41]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[42]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[43]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[44]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[45]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[46]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[47]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[48]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[49]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[50]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[51]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[52]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[53]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[54]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[55]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[56]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[57]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[58]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[59]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[60]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[61]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[62]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[63]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[64]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[65]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[66]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[67]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[68]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[69]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[70]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[71]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[72]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[73]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[74]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[75]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[76]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[77]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[78]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[79]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[80]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[81]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[82]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[83]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[84]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[85]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[86]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[87]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[88]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[89]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[90]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[91]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[92]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[93]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[94]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[95]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[96]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[97]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[98]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[99]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_DOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => DEBUG_PHASE) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[0]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[100]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[101]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[102]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[103]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[104]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[105]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[106]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[107]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[108]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[109]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[10]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[110]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[111]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[112]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[113]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[114]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[115]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[116]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[117]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[118]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[119]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[11]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[120]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[121]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[122]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[123]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[124]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[125]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[126]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[127]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[128]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[129]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[12]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[130]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[131]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[132]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[133]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[134]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[135]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[136]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[137]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[138]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[139]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[13]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[140]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[141]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[142]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[143]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[144]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[145]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[146]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[147]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[148]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[149]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[14]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[150]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[151]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[152]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[153]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[154]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[155]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[156]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[157]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[158]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[159]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[15]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[160]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[161]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[162]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[163]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[164]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[165]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[166]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[167]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[168]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[169]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[16]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[170]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[171]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[172]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[173]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[174]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[175]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[176]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[177]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[178]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[179]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[17]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[180]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[181]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[182]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[183]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[184]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[185]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[186]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[187]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[188]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[189]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[18]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[190]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[191]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[192]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[193]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[194]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[195]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[196]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[197]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[198]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[199]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[19]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[1]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[200]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[201]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[202]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[203]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[204]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[205]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[206]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[207]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[208]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[209]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[20]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[210]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[211]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[212]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[213]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[214]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[215]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[216]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[217]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[218]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[219]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[21]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[220]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[221]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[222]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[223]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[224]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[225]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[226]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[227]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[228]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[229]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[22]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[230]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[231]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[232]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[233]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[234]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[235]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[236]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[237]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[238]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[239]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[23]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[240]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[241]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[242]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[243]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[244]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[245]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[246]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[247]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[248]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[249]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[24]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[250]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[251]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[252]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[253]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[254]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[255]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[256]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[257]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[258]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[259]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[25]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[260]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[261]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[262]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[263]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[264]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[265]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[266]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[267]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[268]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[269]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[26]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[270]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[271]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[272]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[273]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[274]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[275]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[276]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[277]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[278]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[279]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[27]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[280]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[281]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[282]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[283]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[284]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[285]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[286]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[287]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[288]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[289]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[28]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[290]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[291]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[292]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[293]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[294]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[295]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[296]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[297]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[298]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[299]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[29]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[2]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[300]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[301]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[302]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[303]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[304]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[305]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[306]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[307]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[308]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[309]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[30]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[310]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[311]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[312]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[313]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[314]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[315]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[316]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[317]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[318]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[319]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[31]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[320]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[321]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[322]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[323]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[324]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[325]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[326]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[327]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[328]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[329]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[32]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[330]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[331]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[332]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[333]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[334]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[335]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[336]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[337]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[338]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[339]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[33]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[340]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[341]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[342]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[343]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[344]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[345]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[346]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[347]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[348]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[349]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[34]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[350]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[351]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[352]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[353]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[354]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[355]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[356]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[357]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[358]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[359]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[35]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[360]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[361]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[362]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[363]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[364]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[365]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[366]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[367]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[368]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[369]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[36]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[370]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[371]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[372]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[373]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[374]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[375]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[376]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[377]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[378]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[379]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[37]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[380]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[381]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[382]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[383]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[384]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[385]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[386]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[387]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[388]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[389]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[38]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[390]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[391]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[392]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[393]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[394]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[395]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[396]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[397]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[398]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[399]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[39]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[3]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[400]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[401]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[402]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[403]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[404]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[405]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[406]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[407]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[408]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[409]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[40]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[410]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[411]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[412]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[413]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[414]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[415]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[416]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[417]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[418]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[419]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[41]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[420]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[421]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[422]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[423]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[424]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[425]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[426]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[427]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[428]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[429]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[42]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[430]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[431]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[432]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[433]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[434]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[435]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[436]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[437]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[438]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[439]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[43]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[440]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[441]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[442]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[443]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[444]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[445]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[446]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[447]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[448]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[449]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[44]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[450]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[451]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[452]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[453]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[454]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[455]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[456]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[457]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[458]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[459]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[45]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[460]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[461]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[462]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[463]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[464]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[465]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[466]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[467]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[468]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[469]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[46]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[470]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[471]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[472]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[473]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[474]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[475]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[476]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[477]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[478]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[479]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[47]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[480]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[481]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[482]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[483]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[484]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[485]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[486]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[487]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[488]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[489]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[48]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[490]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[491]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[492]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[493]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[494]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[495]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[496]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[497]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[498]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[499]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[49]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[4]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[500]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[501]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[502]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[503]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[504]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[505]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[506]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[507]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[508]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[509]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[50]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[510]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[511]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[51]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[52]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[53]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[54]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[55]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[56]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[57]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[58]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[59]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[5]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[60]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[61]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[62]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[63]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[64]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[65]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[66]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[67]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[68]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[69]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[6]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[70]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[71]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[72]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[73]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[74]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[75]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[76]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[77]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[78]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[79]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[7]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[80]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[81]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[82]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[83]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[84]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[85]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[86]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[87]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[88]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[89]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[8]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[90]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[91]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[92]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[93]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[94]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[95]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[96]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[97]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[98]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[99]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TDATA[9]) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TLAST) = (100:100:100, 100:100:100); + (M_AXIS_DOUT_ACLK => M_AXIS_DOUT_TVALID) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[0]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[10]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[11]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[12]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[13]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[14]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[15]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[16]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[17]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[18]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[19]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[1]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[20]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[21]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[22]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[23]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[24]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[25]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[26]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[27]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[28]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[29]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[2]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[30]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[31]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[3]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[4]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[5]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[6]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[7]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[8]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TDATA[9]) = (100:100:100, 100:100:100); + (M_AXIS_STATUS_ACLK => M_AXIS_STATUS_TVALID) = (100:100:100, 100:100:100); + (S_AXIS_CTRL_ACLK => S_AXIS_CTRL_TREADY) = (100:100:100, 100:100:100); + (S_AXIS_DIN_ACLK => S_AXIS_DIN_TREADY) = (100:100:100, 100:100:100); + (S_AXIS_DIN_WORDS_ACLK => S_AXIS_DIN_WORDS_TREADY) = (100:100:100, 100:100:100); + (S_AXIS_DOUT_WORDS_ACLK => S_AXIS_DOUT_WORDS_TREADY) = (100:100:100, 100:100:100); + (S_AXI_ACLK => INTERRUPT) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_ARREADY) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_AWREADY) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_BVALID) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[0]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[10]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[11]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[12]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[13]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[14]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[15]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[16]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[17]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[18]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[19]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[1]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[20]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[21]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[22]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[23]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[24]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[25]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[26]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[27]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[28]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[29]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[2]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[30]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[31]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[3]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[4]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[5]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[6]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[7]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[8]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RDATA[9]) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_RVALID) = (100:100:100, 100:100:100); + (S_AXI_ACLK => S_AXI_WREADY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CORE_CLK, 0:0:0, notifier); + $period (negedge M_AXIS_DOUT_ACLK, 0:0:0, notifier); + $period (negedge M_AXIS_STATUS_ACLK, 0:0:0, notifier); + $period (negedge S_AXIS_CTRL_ACLK, 0:0:0, notifier); + $period (negedge S_AXIS_DIN_ACLK, 0:0:0, notifier); + $period (negedge S_AXIS_DIN_WORDS_ACLK, 0:0:0, notifier); + $period (negedge S_AXIS_DOUT_WORDS_ACLK, 0:0:0, notifier); + $period (negedge S_AXI_ACLK, 0:0:0, notifier); + $period (posedge CORE_CLK, 0:0:0, notifier); + $period (posedge M_AXIS_DOUT_ACLK, 0:0:0, notifier); + $period (posedge M_AXIS_STATUS_ACLK, 0:0:0, notifier); + $period (posedge S_AXIS_CTRL_ACLK, 0:0:0, notifier); + $period (posedge S_AXIS_DIN_ACLK, 0:0:0, notifier); + $period (posedge S_AXIS_DIN_WORDS_ACLK, 0:0:0, notifier); + $period (posedge S_AXIS_DOUT_WORDS_ACLK, 0:0:0, notifier); + $period (posedge S_AXI_ACLK, 0:0:0, notifier); + $setuphold (posedge CORE_CLK, negedge DEBUG_EN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, DEBUG_EN_delay); + $setuphold (posedge CORE_CLK, posedge DEBUG_EN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, DEBUG_EN_delay); + $setuphold (posedge M_AXIS_DOUT_ACLK, negedge M_AXIS_DOUT_TREADY, 0:0:0, 0:0:0, notifier, , , M_AXIS_DOUT_ACLK_delay, M_AXIS_DOUT_TREADY_delay); + $setuphold (posedge M_AXIS_DOUT_ACLK, posedge M_AXIS_DOUT_TREADY, 0:0:0, 0:0:0, notifier, , , M_AXIS_DOUT_ACLK_delay, M_AXIS_DOUT_TREADY_delay); + $setuphold (posedge M_AXIS_STATUS_ACLK, negedge M_AXIS_STATUS_TREADY, 0:0:0, 0:0:0, notifier, , , M_AXIS_STATUS_ACLK_delay, M_AXIS_STATUS_TREADY_delay); + $setuphold (posedge M_AXIS_STATUS_ACLK, posedge M_AXIS_STATUS_TREADY, 0:0:0, 0:0:0, notifier, , , M_AXIS_STATUS_ACLK_delay, M_AXIS_STATUS_TREADY_delay); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[0]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[10]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[11]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[12]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[13]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[14]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[15]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[16]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[17]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[18]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[19]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[1]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[20]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[21]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[22]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[23]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[24]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[25]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[26]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[27]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[28]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[29]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[2]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[30]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[31]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[3]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[4]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[5]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[6]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[7]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[8]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[9]); + $setuphold (posedge S_AXIS_CTRL_ACLK, negedge S_AXIS_CTRL_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TVALID_delay); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[0]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[10]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[11]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[12]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[13]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[14]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[15]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[16]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[17]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[18]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[19]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[1]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[20]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[21]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[22]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[23]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[24]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[25]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[26]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[27]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[28]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[29]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[2]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[30]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[31]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[3]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[4]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[5]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[6]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[7]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[8]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TDATA_delay[9]); + $setuphold (posedge S_AXIS_CTRL_ACLK, posedge S_AXIS_CTRL_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_CTRL_ACLK_delay, S_AXIS_CTRL_TVALID_delay); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[100], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[100]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[101], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[101]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[102], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[102]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[103], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[103]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[104], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[104]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[105], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[105]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[106], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[106]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[107], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[107]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[108], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[108]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[109], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[109]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[110], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[110]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[111], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[111]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[112], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[112]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[113], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[113]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[114], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[114]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[115], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[115]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[116], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[116]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[117], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[117]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[118], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[118]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[119], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[119]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[120], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[120]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[121], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[121]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[122], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[122]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[123], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[123]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[124], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[124]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[125], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[125]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[126], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[126]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[127], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[127]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[128], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[128]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[129], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[129]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[130], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[130]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[131], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[131]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[132], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[132]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[133], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[133]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[134], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[134]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[135], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[135]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[136], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[136]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[137], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[137]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[138], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[138]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[139], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[139]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[13]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[140], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[140]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[141], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[141]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[142], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[142]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[143], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[143]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[144], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[144]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[145], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[145]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[146], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[146]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[147], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[147]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[148], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[148]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[149], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[149]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[14]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[150], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[150]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[151], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[151]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[152], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[152]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[153], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[153]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[154], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[154]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[155], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[155]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[156], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[156]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[157], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[157]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[158], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[158]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[159], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[159]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[15]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[160], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[160]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[161], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[161]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[162], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[162]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[163], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[163]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[164], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[164]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[165], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[165]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[166], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[166]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[167], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[167]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[168], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[168]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[169], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[169]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[170], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[170]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[171], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[171]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[172], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[172]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[173], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[173]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[174], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[174]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[175], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[175]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[176], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[176]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[177], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[177]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[178], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[178]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[179], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[179]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[180], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[180]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[181], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[181]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[182], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[182]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[183], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[183]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[184], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[184]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[185], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[185]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[186], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[186]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[187], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[187]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[188], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[188]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[189], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[189]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[190], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[190]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[191], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[191]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[192], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[192]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[193], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[193]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[194], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[194]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[195], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[195]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[196], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[196]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[197], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[197]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[198], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[198]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[199], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[199]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[200], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[200]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[201], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[201]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[202], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[202]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[203], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[203]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[204], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[204]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[205], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[205]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[206], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[206]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[207], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[207]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[208], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[208]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[209], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[209]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[210], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[210]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[211], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[211]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[212], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[212]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[213], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[213]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[214], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[214]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[215], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[215]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[216], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[216]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[217], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[217]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[218], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[218]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[219], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[219]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[21]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[220], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[220]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[221], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[221]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[222], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[222]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[223], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[223]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[224], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[224]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[225], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[225]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[226], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[226]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[227], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[227]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[228], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[228]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[229], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[229]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[22]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[230], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[230]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[231], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[231]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[232], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[232]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[233], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[233]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[234], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[234]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[235], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[235]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[236], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[236]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[237], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[237]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[238], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[238]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[239], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[239]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[23]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[240], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[240]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[241], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[241]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[242], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[242]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[243], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[243]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[244], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[244]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[245], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[245]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[246], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[246]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[247], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[247]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[248], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[248]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[249], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[249]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[250], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[250]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[251], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[251]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[252], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[252]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[253], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[253]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[254], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[254]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[255], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[255]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[256], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[256]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[257], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[257]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[258], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[258]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[259], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[259]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[260], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[260]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[261], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[261]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[262], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[262]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[263], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[263]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[264], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[264]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[265], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[265]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[266], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[266]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[267], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[267]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[268], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[268]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[269], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[269]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[270], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[270]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[271], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[271]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[272], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[272]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[273], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[273]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[274], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[274]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[275], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[275]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[276], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[276]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[277], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[277]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[278], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[278]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[279], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[279]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[280], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[280]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[281], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[281]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[282], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[282]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[283], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[283]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[284], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[284]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[285], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[285]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[286], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[286]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[287], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[287]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[288], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[288]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[289], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[289]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[290], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[290]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[291], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[291]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[292], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[292]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[293], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[293]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[294], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[294]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[295], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[295]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[296], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[296]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[297], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[297]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[298], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[298]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[299], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[299]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[29]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[300], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[300]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[301], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[301]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[302], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[302]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[303], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[303]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[304], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[304]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[305], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[305]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[306], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[306]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[307], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[307]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[308], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[308]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[309], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[309]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[30]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[310], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[310]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[311], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[311]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[312], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[312]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[313], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[313]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[314], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[314]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[315], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[315]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[316], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[316]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[317], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[317]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[318], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[318]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[319], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[319]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[31]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[320], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[320]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[321], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[321]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[322], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[322]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[323], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[323]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[324], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[324]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[325], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[325]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[326], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[326]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[327], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[327]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[328], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[328]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[329], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[329]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[32], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[32]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[330], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[330]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[331], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[331]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[332], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[332]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[333], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[333]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[334], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[334]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[335], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[335]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[336], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[336]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[337], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[337]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[338], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[338]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[339], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[339]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[33], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[33]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[340], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[340]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[341], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[341]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[342], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[342]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[343], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[343]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[344], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[344]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[345], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[345]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[346], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[346]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[347], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[347]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[348], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[348]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[349], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[349]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[34], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[34]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[350], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[350]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[351], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[351]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[352], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[352]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[353], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[353]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[354], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[354]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[355], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[355]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[356], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[356]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[357], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[357]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[358], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[358]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[359], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[359]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[35], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[35]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[360], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[360]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[361], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[361]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[362], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[362]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[363], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[363]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[364], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[364]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[365], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[365]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[366], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[366]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[367], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[367]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[368], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[368]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[369], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[369]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[36], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[36]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[370], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[370]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[371], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[371]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[372], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[372]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[373], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[373]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[374], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[374]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[375], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[375]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[376], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[376]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[377], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[377]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[378], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[378]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[379], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[379]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[37], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[37]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[380], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[380]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[381], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[381]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[382], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[382]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[383], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[383]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[384], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[384]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[385], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[385]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[386], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[386]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[387], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[387]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[388], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[388]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[389], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[389]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[38], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[38]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[390], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[390]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[391], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[391]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[392], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[392]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[393], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[393]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[394], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[394]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[395], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[395]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[396], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[396]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[397], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[397]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[398], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[398]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[399], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[399]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[39], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[39]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[400], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[400]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[401], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[401]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[402], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[402]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[403], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[403]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[404], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[404]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[405], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[405]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[406], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[406]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[407], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[407]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[408], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[408]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[409], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[409]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[40], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[40]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[410], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[410]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[411], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[411]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[412], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[412]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[413], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[413]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[414], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[414]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[415], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[415]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[416], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[416]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[417], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[417]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[418], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[418]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[419], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[419]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[41], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[41]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[420], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[420]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[421], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[421]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[422], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[422]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[423], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[423]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[424], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[424]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[425], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[425]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[426], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[426]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[427], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[427]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[428], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[428]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[429], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[429]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[42], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[42]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[430], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[430]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[431], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[431]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[432], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[432]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[433], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[433]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[434], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[434]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[435], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[435]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[436], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[436]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[437], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[437]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[438], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[438]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[439], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[439]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[43], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[43]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[440], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[440]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[441], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[441]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[442], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[442]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[443], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[443]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[444], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[444]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[445], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[445]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[446], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[446]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[447], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[447]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[448], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[448]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[449], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[449]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[44], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[44]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[450], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[450]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[451], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[451]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[452], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[452]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[453], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[453]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[454], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[454]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[455], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[455]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[456], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[456]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[457], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[457]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[458], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[458]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[459], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[459]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[45], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[45]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[460], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[460]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[461], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[461]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[462], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[462]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[463], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[463]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[464], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[464]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[465], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[465]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[466], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[466]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[467], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[467]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[468], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[468]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[469], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[469]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[46], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[46]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[470], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[470]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[471], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[471]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[472], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[472]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[473], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[473]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[474], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[474]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[475], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[475]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[476], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[476]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[477], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[477]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[478], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[478]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[479], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[479]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[47], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[47]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[480], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[480]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[481], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[481]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[482], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[482]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[483], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[483]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[484], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[484]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[485], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[485]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[486], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[486]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[487], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[487]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[488], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[488]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[489], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[489]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[48], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[48]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[490], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[490]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[491], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[491]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[492], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[492]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[493], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[493]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[494], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[494]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[495], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[495]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[496], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[496]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[497], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[497]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[498], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[498]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[499], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[499]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[49], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[49]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[500], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[500]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[501], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[501]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[502], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[502]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[503], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[503]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[504], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[504]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[505], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[505]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[506], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[506]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[507], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[507]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[508], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[508]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[509], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[509]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[50], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[50]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[510], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[510]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[511], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[511]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[51], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[51]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[52], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[52]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[53], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[53]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[54], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[54]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[55], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[55]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[56], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[56]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[57], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[57]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[58], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[58]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[59], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[59]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[5]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[60], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[60]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[61], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[61]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[62], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[62]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[63], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[63]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[64], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[64]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[65], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[65]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[66], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[66]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[67], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[67]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[68], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[68]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[69], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[69]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[6]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[70], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[70]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[71], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[71]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[72], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[72]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[73], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[73]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[74], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[74]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[75], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[75]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[76], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[76]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[77], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[77]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[78], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[78]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[79], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[79]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[7]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[80], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[80]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[81], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[81]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[82], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[82]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[83], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[83]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[84], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[84]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[85], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[85]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[86], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[86]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[87], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[87]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[88], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[88]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[89], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[89]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[90], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[90]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[91], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[91]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[92], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[92]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[93], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[93]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[94], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[94]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[95], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[95]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[96], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[96]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[97], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[97]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[98], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[98]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[99], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[99]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TLAST_delay); + $setuphold (posedge S_AXIS_DIN_ACLK, negedge S_AXIS_DIN_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TVALID_delay); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[100], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[100]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[101], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[101]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[102], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[102]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[103], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[103]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[104], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[104]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[105], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[105]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[106], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[106]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[107], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[107]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[108], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[108]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[109], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[109]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[110], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[110]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[111], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[111]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[112], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[112]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[113], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[113]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[114], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[114]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[115], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[115]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[116], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[116]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[117], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[117]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[118], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[118]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[119], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[119]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[120], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[120]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[121], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[121]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[122], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[122]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[123], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[123]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[124], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[124]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[125], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[125]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[126], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[126]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[127], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[127]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[128], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[128]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[129], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[129]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[130], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[130]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[131], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[131]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[132], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[132]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[133], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[133]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[134], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[134]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[135], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[135]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[136], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[136]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[137], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[137]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[138], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[138]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[139], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[139]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[13]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[140], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[140]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[141], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[141]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[142], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[142]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[143], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[143]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[144], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[144]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[145], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[145]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[146], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[146]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[147], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[147]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[148], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[148]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[149], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[149]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[14]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[150], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[150]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[151], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[151]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[152], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[152]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[153], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[153]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[154], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[154]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[155], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[155]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[156], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[156]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[157], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[157]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[158], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[158]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[159], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[159]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[15]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[160], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[160]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[161], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[161]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[162], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[162]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[163], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[163]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[164], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[164]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[165], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[165]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[166], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[166]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[167], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[167]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[168], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[168]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[169], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[169]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[170], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[170]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[171], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[171]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[172], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[172]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[173], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[173]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[174], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[174]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[175], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[175]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[176], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[176]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[177], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[177]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[178], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[178]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[179], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[179]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[180], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[180]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[181], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[181]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[182], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[182]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[183], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[183]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[184], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[184]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[185], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[185]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[186], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[186]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[187], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[187]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[188], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[188]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[189], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[189]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[190], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[190]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[191], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[191]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[192], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[192]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[193], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[193]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[194], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[194]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[195], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[195]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[196], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[196]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[197], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[197]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[198], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[198]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[199], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[199]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[200], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[200]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[201], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[201]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[202], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[202]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[203], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[203]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[204], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[204]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[205], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[205]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[206], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[206]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[207], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[207]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[208], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[208]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[209], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[209]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[210], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[210]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[211], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[211]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[212], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[212]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[213], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[213]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[214], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[214]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[215], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[215]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[216], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[216]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[217], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[217]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[218], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[218]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[219], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[219]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[21]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[220], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[220]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[221], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[221]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[222], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[222]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[223], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[223]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[224], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[224]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[225], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[225]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[226], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[226]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[227], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[227]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[228], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[228]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[229], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[229]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[22]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[230], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[230]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[231], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[231]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[232], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[232]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[233], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[233]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[234], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[234]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[235], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[235]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[236], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[236]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[237], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[237]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[238], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[238]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[239], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[239]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[23]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[240], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[240]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[241], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[241]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[242], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[242]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[243], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[243]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[244], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[244]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[245], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[245]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[246], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[246]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[247], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[247]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[248], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[248]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[249], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[249]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[250], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[250]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[251], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[251]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[252], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[252]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[253], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[253]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[254], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[254]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[255], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[255]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[256], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[256]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[257], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[257]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[258], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[258]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[259], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[259]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[260], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[260]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[261], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[261]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[262], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[262]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[263], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[263]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[264], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[264]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[265], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[265]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[266], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[266]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[267], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[267]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[268], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[268]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[269], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[269]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[270], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[270]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[271], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[271]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[272], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[272]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[273], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[273]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[274], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[274]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[275], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[275]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[276], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[276]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[277], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[277]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[278], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[278]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[279], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[279]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[280], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[280]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[281], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[281]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[282], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[282]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[283], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[283]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[284], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[284]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[285], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[285]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[286], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[286]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[287], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[287]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[288], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[288]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[289], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[289]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[290], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[290]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[291], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[291]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[292], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[292]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[293], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[293]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[294], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[294]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[295], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[295]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[296], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[296]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[297], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[297]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[298], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[298]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[299], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[299]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[29]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[300], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[300]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[301], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[301]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[302], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[302]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[303], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[303]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[304], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[304]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[305], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[305]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[306], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[306]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[307], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[307]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[308], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[308]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[309], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[309]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[30]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[310], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[310]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[311], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[311]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[312], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[312]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[313], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[313]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[314], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[314]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[315], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[315]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[316], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[316]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[317], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[317]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[318], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[318]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[319], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[319]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[31]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[320], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[320]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[321], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[321]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[322], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[322]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[323], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[323]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[324], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[324]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[325], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[325]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[326], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[326]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[327], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[327]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[328], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[328]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[329], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[329]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[32], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[32]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[330], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[330]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[331], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[331]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[332], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[332]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[333], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[333]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[334], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[334]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[335], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[335]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[336], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[336]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[337], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[337]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[338], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[338]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[339], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[339]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[33], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[33]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[340], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[340]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[341], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[341]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[342], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[342]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[343], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[343]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[344], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[344]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[345], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[345]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[346], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[346]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[347], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[347]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[348], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[348]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[349], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[349]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[34], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[34]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[350], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[350]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[351], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[351]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[352], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[352]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[353], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[353]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[354], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[354]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[355], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[355]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[356], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[356]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[357], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[357]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[358], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[358]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[359], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[359]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[35], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[35]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[360], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[360]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[361], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[361]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[362], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[362]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[363], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[363]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[364], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[364]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[365], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[365]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[366], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[366]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[367], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[367]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[368], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[368]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[369], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[369]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[36], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[36]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[370], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[370]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[371], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[371]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[372], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[372]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[373], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[373]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[374], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[374]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[375], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[375]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[376], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[376]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[377], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[377]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[378], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[378]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[379], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[379]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[37], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[37]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[380], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[380]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[381], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[381]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[382], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[382]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[383], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[383]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[384], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[384]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[385], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[385]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[386], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[386]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[387], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[387]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[388], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[388]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[389], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[389]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[38], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[38]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[390], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[390]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[391], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[391]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[392], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[392]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[393], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[393]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[394], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[394]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[395], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[395]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[396], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[396]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[397], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[397]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[398], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[398]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[399], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[399]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[39], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[39]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[400], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[400]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[401], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[401]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[402], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[402]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[403], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[403]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[404], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[404]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[405], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[405]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[406], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[406]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[407], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[407]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[408], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[408]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[409], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[409]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[40], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[40]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[410], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[410]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[411], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[411]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[412], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[412]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[413], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[413]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[414], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[414]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[415], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[415]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[416], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[416]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[417], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[417]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[418], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[418]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[419], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[419]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[41], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[41]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[420], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[420]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[421], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[421]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[422], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[422]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[423], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[423]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[424], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[424]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[425], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[425]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[426], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[426]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[427], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[427]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[428], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[428]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[429], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[429]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[42], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[42]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[430], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[430]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[431], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[431]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[432], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[432]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[433], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[433]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[434], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[434]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[435], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[435]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[436], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[436]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[437], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[437]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[438], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[438]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[439], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[439]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[43], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[43]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[440], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[440]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[441], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[441]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[442], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[442]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[443], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[443]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[444], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[444]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[445], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[445]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[446], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[446]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[447], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[447]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[448], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[448]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[449], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[449]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[44], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[44]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[450], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[450]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[451], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[451]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[452], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[452]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[453], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[453]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[454], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[454]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[455], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[455]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[456], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[456]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[457], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[457]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[458], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[458]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[459], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[459]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[45], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[45]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[460], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[460]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[461], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[461]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[462], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[462]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[463], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[463]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[464], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[464]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[465], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[465]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[466], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[466]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[467], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[467]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[468], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[468]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[469], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[469]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[46], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[46]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[470], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[470]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[471], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[471]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[472], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[472]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[473], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[473]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[474], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[474]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[475], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[475]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[476], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[476]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[477], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[477]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[478], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[478]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[479], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[479]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[47], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[47]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[480], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[480]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[481], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[481]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[482], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[482]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[483], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[483]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[484], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[484]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[485], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[485]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[486], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[486]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[487], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[487]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[488], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[488]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[489], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[489]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[48], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[48]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[490], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[490]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[491], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[491]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[492], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[492]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[493], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[493]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[494], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[494]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[495], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[495]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[496], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[496]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[497], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[497]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[498], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[498]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[499], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[499]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[49], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[49]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[500], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[500]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[501], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[501]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[502], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[502]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[503], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[503]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[504], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[504]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[505], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[505]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[506], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[506]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[507], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[507]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[508], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[508]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[509], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[509]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[50], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[50]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[510], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[510]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[511], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[511]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[51], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[51]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[52], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[52]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[53], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[53]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[54], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[54]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[55], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[55]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[56], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[56]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[57], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[57]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[58], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[58]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[59], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[59]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[5]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[60], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[60]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[61], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[61]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[62], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[62]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[63], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[63]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[64], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[64]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[65], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[65]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[66], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[66]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[67], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[67]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[68], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[68]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[69], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[69]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[6]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[70], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[70]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[71], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[71]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[72], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[72]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[73], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[73]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[74], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[74]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[75], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[75]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[76], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[76]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[77], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[77]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[78], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[78]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[79], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[79]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[7]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[80], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[80]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[81], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[81]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[82], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[82]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[83], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[83]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[84], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[84]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[85], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[85]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[86], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[86]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[87], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[87]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[88], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[88]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[89], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[89]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[90], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[90]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[91], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[91]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[92], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[92]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[93], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[93]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[94], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[94]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[95], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[95]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[96], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[96]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[97], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[97]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[98], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[98]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[99], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[99]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TLAST_delay); + $setuphold (posedge S_AXIS_DIN_ACLK, posedge S_AXIS_DIN_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_ACLK_delay, S_AXIS_DIN_TVALID_delay); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TLAST_delay); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, negedge S_AXIS_DIN_WORDS_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TVALID_delay); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TLAST_delay); + $setuphold (posedge S_AXIS_DIN_WORDS_ACLK, posedge S_AXIS_DIN_WORDS_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DIN_WORDS_ACLK_delay, S_AXIS_DIN_WORDS_TVALID_delay); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TLAST_delay); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, negedge S_AXIS_DOUT_WORDS_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TVALID_delay); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[0]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[10]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[11]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[12]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[16]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[17]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[18]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[19]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[1]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[20]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[24]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[25]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[26]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[27]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[28]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[2]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[3]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[4]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[8]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TDATA_delay[9]); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TLAST, 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TLAST_delay); + $setuphold (posedge S_AXIS_DOUT_WORDS_ACLK, posedge S_AXIS_DOUT_WORDS_TVALID, 0:0:0, 0:0:0, notifier, , , S_AXIS_DOUT_WORDS_ACLK_delay, S_AXIS_DOUT_WORDS_TVALID_delay); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[10]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[11]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[12]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[13]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[14]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[15]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[16]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[17]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[2]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[3]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[4]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[5]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[6]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[7]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[8]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARADDR[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[9]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_ARVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARVALID_delay); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[10]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[11]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[12]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[13]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[14]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[15]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[16]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[17]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[2]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[3]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[4]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[5]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[6]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[7]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[8]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWADDR[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[9]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_AWVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWVALID_delay); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_BREADY, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_BREADY_delay); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_RREADY, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_RREADY_delay); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[0]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[10]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[11]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[12]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[13]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[14]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[15]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[16]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[17]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[18]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[19]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[1]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[20]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[21]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[22]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[23]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[24]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[25]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[26]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[27]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[28]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[29]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[2]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[30]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[31]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[3]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[4]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[5]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[6]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[7]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[8]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[9]); + $setuphold (posedge S_AXI_ACLK, negedge S_AXI_WVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WVALID_delay); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[10]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[11]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[12]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[13]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[14]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[15]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[16]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[17]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[2]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[3]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[4]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[5]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[6]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[7]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[8]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARADDR[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARADDR_delay[9]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_ARVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_ARVALID_delay); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[10]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[11]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[12]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[13]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[14]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[15]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[16]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[17]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[2]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[3]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[4]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[5]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[6]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[7]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[8]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWADDR[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWADDR_delay[9]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_AWVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_AWVALID_delay); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_BREADY, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_BREADY_delay); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_RREADY, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_RREADY_delay); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[0], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[0]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[10], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[10]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[11], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[11]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[12], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[12]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[13], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[13]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[14], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[14]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[15], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[15]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[16], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[16]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[17], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[17]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[18], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[18]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[19], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[19]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[1], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[1]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[20], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[20]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[21], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[21]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[22], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[22]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[23], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[23]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[24], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[24]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[25], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[25]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[26], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[26]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[27], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[27]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[28], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[28]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[29], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[29]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[2], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[2]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[30], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[30]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[31], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[31]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[3], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[3]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[4], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[4]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[5], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[5]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[6], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[6]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[7], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[7]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[8], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[8]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WDATA[9], 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WDATA_delay[9]); + $setuphold (posedge S_AXI_ACLK, posedge S_AXI_WVALID, 0:0:0, 0:0:0, notifier, , , S_AXI_ACLK_delay, S_AXI_WVALID_delay); + $width (negedge CORE_CLK, 0:0:0, 0, notifier); + $width (negedge M_AXIS_DOUT_ACLK, 0:0:0, 0, notifier); + $width (negedge M_AXIS_STATUS_ACLK, 0:0:0, 0, notifier); + $width (negedge S_AXIS_CTRL_ACLK, 0:0:0, 0, notifier); + $width (negedge S_AXIS_DIN_ACLK, 0:0:0, 0, notifier); + $width (negedge S_AXIS_DIN_WORDS_ACLK, 0:0:0, 0, notifier); + $width (negedge S_AXIS_DOUT_WORDS_ACLK, 0:0:0, 0, notifier); + $width (negedge S_AXI_ACLK, 0:0:0, 0, notifier); + $width (posedge CORE_CLK, 0:0:0, 0, notifier); + $width (posedge M_AXIS_DOUT_ACLK, 0:0:0, 0, notifier); + $width (posedge M_AXIS_STATUS_ACLK, 0:0:0, 0, notifier); + $width (posedge S_AXIS_CTRL_ACLK, 0:0:0, 0, notifier); + $width (posedge S_AXIS_DIN_ACLK, 0:0:0, 0, notifier); + $width (posedge S_AXIS_DIN_WORDS_ACLK, 0:0:0, 0, notifier); + $width (posedge S_AXIS_DOUT_WORDS_ACLK, 0:0:0, 0, notifier); + $width (posedge S_AXI_ACLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FIFO18E1.v b/verilog/src/unisims/FIFO18E1.v new file mode 100644 index 0000000..36fae0f --- /dev/null +++ b/verilog/src/unisims/FIFO18E1.v @@ -0,0 +1,3807 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 18K-Bit FIFO +// /___/ /\ Filename : FIFO18E1.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/18/08 - Initial version. +// 07/10/08 - IR476500 Add INIT parameter support, sync with FIFO36 internal +// 08/22/08 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO18_36. (IR 479958) +// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware. +// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127). +// 04/29/09 - Fixed timing violation for asynchronous reset (CR 519016). +// 10/07/09 - Fixed reset behavior (CR 532794). +// 10/23/09 - Fixed RST and RSTREG (CR 537067). +// 06/30/10 - Updated RESET behavior and added SIM_DEVICE (CR 567515). +// 07/16/10 - Fixed RESET behavior during startup (CR 568626). +// 08/19/10 - Fixed RESET DRC during startup (CR 570708). +// 09/16/10 - Updated from bit to bus timing (CR 575523). +// 12/02/10 - Added warning message for 7SERIES Aysnc mode (CR 584052). +// 12/07/10 - Error out if no reset before first use of the fifo (CR 583638). +// 01/12/11 - updated warning message for 7SERIES Aysnc mode (CR 589721). +// 05/11/11 - Fixed DO not suppose to be reseted when RST asserted (CR 586526). +// 05/26/11 - Update Aysnc fifo behavior (CR 599680). +// 06/06/11 - Fixed RST in standard mode (CR 613216). +// 06/07/11 - Update DRC equation for ALMOST_FULL_OFFSET (CR 611057). +// 06/09/11 - Fixed GSR behavior (CR 611989). +// 06/13/11 - Added setup/hold timing check for RST (CR 606107). +// 07/07/11 - Fixed Full flag (CR 615773). +// 08/26/11 - Fixed FULL and ALMOSTFULL during initial time (CR 622163). +// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 03/08/12 - Added DRC to check WREN/RDEN after RST deassertion (CR 644571). +// 05/16/12 - Added support of negative setup/hold/recovery/removal timing (CR 639991). +// 11/05/12 - Fixed full flag in async mode with sync clocks (CR 677254). +// 01/15/13 - Fixed index out of bound warnings for parity (CR 694713). +// 07/18/13 - Added invertible pins support (CR 715417). +// 08/01/13 - Fixed async mode with sync clocks (CR 728728). +// 10/31/13 - Fixed flags in async mode with sync clocks (CR 718734, 724006). +// 03/25/14 - Balanced all iniputs with xor (CR778933). +// 05/16/14 - Fixed empty flag (CR 799323). +// 06/12/14 - Fixed almost_*_offset DRC (CR 799864). +// 07/24/14 - Fixed DRC message error (CR 798755). +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/13/14 - Fixed almost_full_offset DRC (CR 824363). +// 10/22/14 - Added #1 to $finish (CR 808642). +// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module FIFO18E1 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO18"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 36'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + + parameter SIM_DEVICE = "7SERIES"; + parameter SRVAL = 36'h0; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire dangle_out, dangle_out1, dangle_out1_1, dangle_out1_2; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire [31:0] dangle_out32; + + + wire almostempty_wire, empty_wire, rderr_wire; + wire almostfull_wire, full_wire, wrerr_wire; + wire [11:0] wrcount_wire, rdcount_wire; + + reg notifier, notifier_wrclk, notifier_rdclk; + wire [31:0] do_wire; + wire [3:0] dop_wire; + reg finish_error = 0; + +`ifdef XIL_TIMING + wire [31:0] DI_dly; + wire [3:0] DIP_dly; + wire RDCLK_dly; + wire RDEN_dly; + wire REGCE_dly; + wire RST_dly; + wire RSTREG_dly; + wire WRCLK_dly; + wire WREN_dly; +`endif + + wire [31:0] di_in; + wire [3:0] dip_in; + wire rdclk_in; + wire rden_in; + wire regce_in; + wire rst_in; + wire rstreg_in; + wire wrclk_in; + wire wren_in; + + reg IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED; + reg IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED; + reg IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED; + reg IS_RST_INVERTED_REG = IS_RST_INVERTED; + reg IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED; + reg IS_WREN_INVERTED_REG = IS_WREN_INVERTED; + +`ifdef XIL_TIMING + assign di_in = DI_dly; + assign dip_in = DIP_dly; + assign regce_in = REGCE_dly; + assign rdclk_in = RDCLK_dly ^ IS_RDCLK_INVERTED_REG; + assign rden_in = RDEN_dly ^ IS_RDEN_INVERTED_REG; + assign rst_in = RST_dly ^ IS_RST_INVERTED_REG; + assign rstreg_in = RSTREG_dly ^ IS_RSTREG_INVERTED_REG; + assign wrclk_in = WRCLK_dly ^ IS_WRCLK_INVERTED_REG; + assign wren_in = WREN_dly ^ IS_WREN_INVERTED_REG; +`else + assign di_in = DI; + assign dip_in = DIP; + assign regce_in = REGCE; + assign rdclk_in = RDCLK ^ IS_RDCLK_INVERTED_REG; + assign rden_in = RDEN ^ IS_RDEN_INVERTED_REG; + assign rst_in = RST ^ IS_RST_INVERTED_REG; + assign rstreg_in = RSTREG ^ IS_RSTREG_INVERTED_REG; + assign wrclk_in = WRCLK ^ IS_WRCLK_INVERTED_REG; + assign wren_in = WREN ^ IS_WREN_INVERTED_REG; +`endif // `ifndef XIL_TIMING + + initial begin + + case (FIFO_MODE) + "FIFO18" : ; + "FIFO18_36" : if (DATA_WIDTH != 36) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 36 when attribute FIFO_MODE = FIFO18_36."); + finish_error = 1; + + end + default : begin + $display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are FIFO18 or FIFO18_36.", FIFO_MODE); + finish_error = 1; + end + + endcase // case(FIFO_MODE) + + + case (DATA_WIDTH) + + 4, 9, 18 : ; + 36 : if (FIFO_MODE != "FIFO18_36") begin + $display("DRC Error : The attribute FIFO_MODE must be set to FIFO18_36 when attribute DATA_WIDTH = 36."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH); + finish_error = 1; + + end + endcase + + if (!((IS_RDCLK_INVERTED >= 1'b0) && (IS_RDCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDCLK_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RDEN_INVERTED >= 1'b0) && (IS_RDEN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDEN_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RSTREG_INVERTED >= 1'b0) && (IS_RSTREG_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREG_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RST_INVERTED >= 1'b0) && (IS_RST_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RST_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RST_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_WRCLK_INVERTED >= 1'b0) && (IS_WRCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WRCLK_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_WREN_INVERTED >= 1'b0) && (IS_WREN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WREN_INVERTED); + finish_error = 1'b1; + end + + if (finish_error == 1) + #1 $finish; + + + end // initial begin + + + // Matching HW + localparam init_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,INIT[35:34],INIT[17:16],INIT[33:18],INIT[15:0]} : {36'h0, INIT}; + localparam srval_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,SRVAL[35:34],SRVAL[17:16],SRVAL[33:18],SRVAL[15:0]} : {36'h0, SRVAL}; + + + FF18_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), + .DATA_WIDTH(DATA_WIDTH), + .DO_REG(DO_REG), + .EN_SYN(EN_SYN), + .FIFO_MODE(FIFO_MODE), + .FIFO_SIZE(18), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .INIT({36'h0,init_sdp}), + .SIM_DEVICE(SIM_DEVICE), + .SRVAL({36'h0,srval_sdp})) + + INT_FIFO (.ALMOSTEMPTY(almostempty_wire), + .ALMOSTFULL(almostfull_wire), + .DBITERR(dangle_out), + .DI({32'b0,di_in}), + .DIP({4'b0,dip_in}), + .DO({dangle_out32,do_wire}), + .DOP({dangle_out4,dop_wire}), + .ECCPARITY(dangle_out8), + .EMPTY(empty_wire), + .FULL(full_wire), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDCLK(rdclk_in), + .RDCOUNT({dangle_out1,rdcount_wire}), + .RDEN(rden_in), + .RDERR(rderr_wire), + .REGCE(regce_in), + .RST(rst_in), + .RSTREG(rstreg_in), + .SBITERR(dangle_out1_2), + .WRCLK(wrclk_in), + .WRCOUNT({dangle_out1_1,wrcount_wire}), + .WREN(wren_in), + .WRERR(wrerr_wire)); + + + reg ALMOSTEMPTY_out; + reg ALMOSTFULL_out; + reg [31:0] DO_out; + reg [3:0] DOP_out; + reg EMPTY_out; + reg FULL_out; + reg [11:0] RDCOUNT_out; + reg RDERR_out; + reg [11:0] WRCOUNT_out; + reg WRERR_out; + + assign ALMOSTEMPTY = ALMOSTEMPTY_out; + assign ALMOSTFULL = ALMOSTFULL_out; + assign DO = DO_out; + assign DOP = DOP_out; + assign EMPTY = EMPTY_out; + assign FULL = FULL_out; + assign RDCOUNT = RDCOUNT_out; + assign RDERR = RDERR_out; + assign WRCOUNT = WRCOUNT_out; + assign WRERR = WRERR_out; + + //*** Timing Checks Start here + +//wrclk_in + always @(almostfull_wire or rst_in or GSR) ALMOSTFULL_out = almostfull_wire; + always @(full_wire or rst_in or GSR) FULL_out = full_wire; + always @(wrerr_wire or rst_in or GSR) WRERR_out = wrerr_wire; + always @(wrcount_wire or rst_in or GSR) WRCOUNT_out = wrcount_wire; + +//rdclk_in + always @(almostempty_wire or rst_in or GSR) ALMOSTEMPTY_out = almostempty_wire; + always @(empty_wire or rst_in or GSR) EMPTY_out = empty_wire; + always @(rderr_wire or rst_in or GSR) RDERR_out = rderr_wire; + always @(rdcount_wire or rst_in or GSR) RDCOUNT_out = rdcount_wire; + + always @(do_wire or rst_in or GSR) DO_out = do_wire; + always @(dop_wire or rst_in or GSR) DOP_out = dop_wire; + +`ifdef XIL_TIMING + + always @(notifier) begin + DO_out <= 32'bx; + DOP_out <= 4'bx; + end + + always @(notifier_wrclk) begin + ALMOSTFULL_out <= 1'bx; + FULL_out <= 1'bx; + WRCOUNT_out <= 12'bx; + WRERR_out <= 1'bx; + end + + always @(notifier_rdclk) begin + ALMOSTEMPTY_out <= 1'bx; + EMPTY_out <= 1'bx; + RDCOUNT_out <= 12'bx; + RDERR_out <= 1'bx; + end + + wire rdclk_en_n; + wire rdclk_en_p; + wire wrclk_en_n; + wire wrclk_en_p; + assign rdclk_en_n = IS_RDCLK_INVERTED_REG; + assign rdclk_en_p = ~IS_RDCLK_INVERTED_REG; + assign wrclk_en_n = IS_WRCLK_INVERTED_REG; + assign wrclk_en_p = ~IS_WRCLK_INVERTED_REG; + + wire nrst; + wire wren_enable; + not (nrst, RST); + and (wren_enable, WREN, nrst); + + wire rst_rdclk_n = nrst && rdclk_en_n; + wire rst_rdclk_p = nrst && rdclk_en_p; + wire rst_wrclk_n = nrst && wrclk_en_n; + wire rst_wrclk_p = nrst && wrclk_en_p; + wire wren_enable_p = wren_enable && wrclk_en_p; + wire wren_enable_n = wren_enable && wrclk_en_n; + +`endif // `ifdef XIL_TIMING + + specify + + (RDCLK *> DO) = (100:100:100, 100:100:100); + (RDCLK *> DOP) = (100:100:100, 100:100:100); + (RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100); + (RDCLK => EMPTY) = (100:100:100, 100:100:100); + (RDCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (RDCLK => RDERR) = (100:100:100, 100:100:100); + + (WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100); + (WRCLK => FULL) = (100:100:100, 100:100:100); + (WRCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (WRCLK => WRERR) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + (RST => ALMOSTEMPTY) = (0:0:0, 0:0:0); + (RST => ALMOSTFULL) = (0:0:0, 0:0:0); + (RST => EMPTY) = (0:0:0, 0:0:0); + (RST => FULL) = (0:0:0, 0:0:0); + (RST *> RDCOUNT) = (0:0:0, 0:0:0); + (RST => RDERR) = (0:0:0, 0:0:0); + (RST *> WRCOUNT) = (0:0:0, 0:0:0); + (RST => WRERR) = (0:0:0, 0:0:0); + + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly); + $setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly); + $setuphold (posedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly); + $setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly); + $setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly); + $setuphold (posedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly); + $setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly); + + $setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly); + $setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly); + $setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly); + $setuphold (negedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly); + $setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly); + $setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly); + $setuphold (negedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly); + $setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly); + + $setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly); + $setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly); + $setuphold (posedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly); + $setuphold (posedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly); + $setuphold (posedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly); + $setuphold (posedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly); + + $setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly); + $setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly); + $setuphold (negedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly); + $setuphold (negedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly); + $setuphold (negedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly); + $setuphold (negedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly); + $setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly); + $setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly); + + $recrem (negedge RST, posedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_p, rdclk_en_p, RST_dly, RDCLK_dly); + $recrem (negedge RST, posedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_p, wrclk_en_p, RST_dly, WRCLK_dly); + $recrem (negedge RST, negedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_n, rdclk_en_n, RST_dly, RDCLK_dly); + $recrem (negedge RST, negedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_n, wrclk_en_n, RST_dly, WRCLK_dly); + + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO18E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. FIFO18E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module FF18_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + output reg ALMOSTEMPTY; + output reg ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output reg EMPTY; + output reg FULL; + output reg [12:0] RDCOUNT; + output reg RDERR; + output SBITERR; + output reg [12:0] WRCOUNT; + output reg WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + input GSR; + input INJECTDBITERR; + input INJECTSBITERR; + + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter INIT = 72'h0; + parameter SIM_DEVICE = "7SERIES"; + parameter SRVAL = 72'h0; + + reg [63:0] do_in = 64'b0; + reg [63:0] do_out = 64'b0; + reg [63:0] do_outreg = 64'b0; + reg [63:0] do_out_mux = 64'b0; + reg [7:0] dop_in = 8'b0, dop_out = 8'b0; + reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0; + + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + reg [71:0] ecc_bit_position; + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, dop_buf = 8'b0, dip_ecc, dip_int; + reg [63:0] do_buf = 64'b0, di_in_ecc_corrected; + reg [7:0] syndrome, dip_in_ecc_corrected; + + wire full_v3; + + reg rden_reg, wren_reg; + reg fwft; + + integer addr_limit, rd_prefetch = 0; + integer wr1_addr = 0; + integer viol_rst_rden = 0, viol_rst_wren = 0; + + reg [3:0] rden_rdckreg = 4'b0, wren_wrckreg = 4'b0; + reg [12:0] rd_addr = 0; + reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0; + reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0; + reg wr1_flag = 0, awr_flag = 0; + reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111; + reg [3:0] full_int = 4'b0000; + reg [3:0] empty_ram = 4'b1111; + reg [8:0] i, j; + reg rst_tmp1 = 0, rst_tmp2 = 0; + reg [4:0] rst_rdckreg = 5'b0, rst_wrckreg = 5'b0; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + reg en_ecc_write_int, en_ecc_read_int, finish_error = 0; + reg [63:0] di_ecc_col; + reg first_rst_flag = 0; + reg rm1wp1_eq = 1'b0, rm1w_eq = 1'b0; + reg awr_flag_sync_1 = 0, awr_flag_sync_2 = 0; + integer after_rst_rdclk = 0, after_rst_wrclk = 0; + integer count_freq_rdclk = 0, count_freq_wrclk = 0; + integer roundup_int_period_rdclk_wrclk=0, roundup_int_period_wrclk_rdclk=0; + integer s7_roundup_int_period_rdclk_wrclk=0; + time rise_rdclk=0, period_rdclk=0, rise_wrclk=0, period_wrclk=0; + integer fwft_prefetch_flag = 1; + real real_period_rdclk=0.0, real_period_wrclk=0.0; + reg rst_trans_rden_1 = 1'b0, rst_trans_rden_2 = 1'b0; + reg rst_trans_wren_1 = 1'b0, rst_trans_wren_2 = 1'b0; + reg after_rst_rden_flag = 1'b0, after_rst_wren_flag = 1'b0, after_rst_x_flag = 1'b0; + time time_wrclk = 0, time_rdclk = 0; + time prev_time_wrclk = 0, prev_time_rdclk = 0; + reg sync_clk_async_mode = 1'b0; + reg sync_clk_async_mode_done = 1'b0; + reg count_freq_wrclk_reset = 0; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameter is changed. + parameter integer FIFO_SIZE = 36; +// xilinx_internal_parameter off + + + localparam counter_width = (FIFO_SIZE == 36) ? ((DATA_WIDTH == 4) ? 12 : + (DATA_WIDTH == 9) ? 11 : (DATA_WIDTH == 18) ? 10 : + (DATA_WIDTH == 36) ? 9 : (DATA_WIDTH == 72) ? 8 : 12) + : ((DATA_WIDTH == 4) ? 11 : (DATA_WIDTH == 9) ? 10 : + (DATA_WIDTH == 18) ? 9 : (DATA_WIDTH == 36) ? 8 : 11); + + reg [counter_width:0] rdcount_out = 13'b0, wr_addr = 13'b0; + reg [counter_width:0] ae_empty, ae_full; + reg [counter_width:0] rdcount_out_sync_3 = 13'h1fff, rdcount_out_sync_2 = 13'h1fff; + reg [counter_width:0] rdcount_out_sync_1 = 13'h1fff, rdcount_out_m1 = 13'h1fff; + reg [counter_width:0] wr_addr_sync_3 = 13'b0, wr_addr_sync_2 = 13'b0, wr_addr_sync_1 = 13'b0; + + + // Determinte memory size + localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0; + localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0; + localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0; + localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0; + localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0; + + + localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 : + (DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0; + + localparam memp_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 1 : + (DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0; + + reg [mem_width : 0] mem [mem_depth : 0]; + reg [memp_width : 0] memp [memp_depth : 0]; + reg sync; + + + // Input and output ports + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + + initial begin + ALMOSTEMPTY = 1'b1; + ALMOSTFULL = 1'b0; + EMPTY = 1'b1; + FULL = 1'b0; + RDCOUNT = 13'h0; + RDERR = 1'b0; + WRCOUNT = 13'h0; + WRERR = 1'b0; + end + + assign full_v3 = (rm1w_eq || (rm1wp1_eq && (WREN && !FULL))) ? 1 : 0; + + + initial begin + + // Determine address limit + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + end + endcase + + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + default : begin + $display("Attribute Syntax Error : The attribute EN_SYN on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN); + finish_error = 1; + end + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + finish_error = 1; + end + endcase + + + // DRC for fwft in sync mode + if (fwft == 1'b1 && EN_SYN == "TRUE") begin + $display("DRC Error : First word fall through is not supported in synchronous mode on FIFO18E1 instance %m."); + finish_error = 1; + end + + if (EN_SYN == "FALSE" && DO_REG == 0) begin + $display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FIFO18E1 instance %m."); + finish_error = 1; + end + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int <= 1; + "FALSE" : en_ecc_write_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int <= 1; + "FALSE" : en_ecc_read_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FIFO18E1 is configured in the ECC mode."); + finish_error = 1; + end + + + if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE); + finish_error = 1; + end + + + if (finish_error == 1) + #1 $finish; + + + end // initial begin + + + // GSR and RST + always @(GSR) + if (GSR === 1'b1) begin + if (DO_REG == 1'b1 && sync == 1'b1) begin + assign do_out = INIT[0 +: mem_width+1]; + assign dop_out = INIT[mem_width+1 +: memp_width+1]; + assign do_outreg = INIT[0 +: mem_width+1]; + assign dop_outreg = INIT[mem_width+1 +: memp_width+1]; + assign do_in = INIT[0 +: mem_width+1]; + assign dop_in = INIT[mem_width+1 +: memp_width+1]; + assign do_buf = INIT[0 +: mem_width+1]; + assign dop_buf = INIT[mem_width+1 +: memp_width+1]; + end + else begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + assign do_in = 64'b0; + assign dop_in = 8'b0; + assign do_buf = 64'b0; + assign dop_buf = 8'b0; + end + end + else if (GSR === 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + deassign do_in; + deassign dop_in; + deassign do_buf; + deassign dop_buf; + end + + + always @(RST) + if (RST === 1'b1) begin + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'b1; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'b0; + assign empty_ram = 4'b1111; + EMPTY = 1'b1; + assign full_int = 4'b0000; + FULL = 1'b0; + assign rdcount_out = 13'b0; + RDCOUNT = 13'b0; + WRCOUNT = 13'b0; + RDERR = 0; + WRERR = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'b1111111111111; + assign rdcount_out_m1 = 13'b1111111111111; + assign wr_addr_sync_3 = 13'b0; + end + else if (RST === 1'b0) begin + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; +// deassign EMPTY; + deassign full_int; +// deassign FULL; + deassign rdcount_out; +// deassign RDCOUNT; +// deassign WRCOUNT; +// deassign RDERR; +// deassign WRERR; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + end + + + // DRC + + generate + + case (SIM_DEVICE) + "VIRTEX6" : begin + + always @(posedge RDCLK) begin + + if (RST === 1'b1 && RDEN === 1'b1) + viol_rst_rden = 1; + + if (RST === 1'b0) + rden_rdckreg[3:0] <= {rden_rdckreg[2:0], RDEN}; + + if (rden_rdckreg == 4'h0) begin + rst_rdckreg[0] <= RST; + rst_rdckreg[1] <= rst_rdckreg[0] & RST; + rst_rdckreg[2] <= rst_rdckreg[1] & RST; + end + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK) begin + + if (RST === 1'b1 && WREN === 1'b1) + viol_rst_wren = 1; + + if (RST === 1'b0) + wren_wrckreg[3:0] <= {wren_wrckreg[2:0], WREN}; + + if (wren_wrckreg == 4'h0) begin + rst_wrckreg[0] <= RST; + rst_wrckreg[1] <= rst_wrckreg[0] & RST; + rst_wrckreg[2] <= rst_wrckreg[1] & RST; + end + + end // always @ (posedge WRCLK) + + + always @(RST) begin + + rst_tmp1 = RST; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + + if (((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.", $stime); + rst_rdclk_flag = 1; + #1 $finish; + end + + + if (((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle.", $stime); + + rst_wrclk_flag = 1; + #1 $finish; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end // if (RST == 1'b0) + + + viol_rst_rden = 0; + viol_rst_wren = 0; + rden_rdckreg = 4'h0; + wren_wrckreg = 4'h0; + + rst_rdckreg = 5'b0; + rst_wrckreg = 5'b0; + + + if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0) + first_rst_flag = 1; + + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + + rst_tmp2 = rst_tmp1; + + end // always @ (RST) + + end // case: "VIRTEX6" + "7SERIES" : begin + + always @(posedge RST) + rst_trans_rden_1 = RST; + + always @(negedge RST) + if (rst_trans_rden_1 == 1'b1) + rst_trans_rden_2 = ~RST; + + + always @(posedge RDCLK) begin + + if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) begin + + after_rst_rdclk = after_rst_rdclk + 1; + + if (RDEN === 1'b1 && after_rst_rdclk <= 2) begin + + after_rst_rden_flag = 1'b1; + + end + else if (after_rst_rdclk >= 3) begin + after_rst_rdclk = 0; + rst_trans_rden_1 = 1'b0; + rst_trans_rden_2 = 1'b0; + + if (after_rst_rden_flag == 1'b1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RDEN must be low for at least two RDCLK clock cycles after RST deasserted.", $stime); + after_rst_rden_flag = 1'b0; + after_rst_x_flag = 1'b1; + #1 $finish; + + end + end + end // if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) + end // always @ (posedge RDCLK) + + + always @(posedge RST) + rst_trans_wren_1 = RST; + + always @(negedge RST) + if (rst_trans_wren_1 == 1'b1) + rst_trans_wren_2 = ~RST; + + + always @(posedge WRCLK) begin + + if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) begin + + after_rst_wrclk = after_rst_wrclk + 1; + + if (WREN === 1'b1 && after_rst_wrclk <= 2) begin + + after_rst_wren_flag = 1'b1; + + end + else if (after_rst_wrclk >= 3) begin + + after_rst_wrclk = 0; + rst_trans_wren_1 = 1'b0; + rst_trans_wren_2 = 1'b0; + + + if (after_rst_wren_flag == 1'b1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. WREN must be low for at least two WRCLK clock cycles after RST deasserted.", $stime); + after_rst_wren_flag = 1'b0; + after_rst_x_flag = 1'b1; + #1 $finish; + + end + end + end // if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) + end // always @ (posedge WRCLK) + + + always @(posedge after_rst_x_flag or negedge RST) begin + + if (after_rst_x_flag == 1'b1) begin + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'bx; + assign rdcount_out_m1 = 13'bx; + assign wr_addr_sync_3 = 13'bx; + after_rst_x_flag = 1'b0; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; + deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + + end // if (RST == 1'b0) + + end // always @ (posedge after_rst_x_flag or negedge RST) + + + always @(posedge RDCLK) begin + + if (RST === 1'b1 && RDEN === 1'b1) + viol_rst_rden = 1; + + if (RDEN === 1'b0 && RST === 1'b1) begin + rst_rdckreg[0] <= RST; + rst_rdckreg[1] <= rst_rdckreg[0] & RST; + rst_rdckreg[2] <= rst_rdckreg[1] & RST; + rst_rdckreg[3] <= rst_rdckreg[2] & RST; + rst_rdckreg[4] <= rst_rdckreg[3] & RST; + end + else if (RDEN === 1'b1 && RST === 1'b1) begin + rst_rdckreg <= 5'b0; + end + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK) begin + + if (RST === 1'b1 && WREN === 1'b1) + viol_rst_wren = 1; + + if (WREN === 1'b0 && RST === 1'b1) begin + rst_wrckreg[0] <= RST; + rst_wrckreg[1] <= rst_wrckreg[0] & RST; + rst_wrckreg[2] <= rst_wrckreg[1] & RST; + rst_wrckreg[3] <= rst_wrckreg[2] & RST; + rst_wrckreg[4] <= rst_wrckreg[3] & RST; + end + else if (WREN === 1'b1 && RST === 1'b1) begin + rst_wrckreg <= 5'b0; + end + + end // always @ (posedge WRCLK) + + + always @(RST) begin + + rst_tmp1 = RST; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if (((rst_rdckreg[4] & rst_rdckreg[3] & rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five RDCLK clock cycles, and RDEN must be low before RST becomes active high, and RDEN remains low during this reset cycle.", $stime); + rst_rdclk_flag = 1; + #1 $finish; + + end + + if (((rst_wrckreg[4] & rst_wrckreg[3] & rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.", $stime); + + rst_wrclk_flag = 1; + #1 $finish; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'bx; + assign rdcount_out_m1 = 13'bx; + assign wr_addr_sync_3 = 13'bx; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + end // if (RST == 1'b0) + + + viol_rst_rden = 0; + viol_rst_wren = 0; + rst_rdckreg = 5'b0; + rst_wrckreg = 5'b0; + + if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0) + first_rst_flag = 1; + + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + rst_tmp2 = rst_tmp1; + + end // always @ (RST) + + end // case: "7SERIES" + + endcase // case(SIM_DEVICE) + + endgenerate + + + // DRC + always @(posedge RDEN or negedge GSR) + @(posedge RDCLK) + if (first_rst_flag == 0 && RDEN == 1'b1 && GSR == 1'b0) begin + $display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time); + #1 $finish; + end + + + always @(posedge WREN or negedge GSR) + @(posedge WRCLK) + if (first_rst_flag == 0 && WREN == 1'b1 && GSR == 1'b0) begin + $display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time); + #1 $finish; + end + + + always @(posedge RDCLK) begin + + if (((period_rdclk == 0) && (count_freq_rdclk < 152)) || + ((count_freq_rdclk == 0) && (GSR == 1 || RST == 1)) || + ((count_freq_rdclk > 0) && (count_freq_rdclk < 152))) begin + count_freq_rdclk = count_freq_rdclk + 1; + end else if (count_freq_wrclk == 152) begin + count_freq_rdclk = 0; + count_freq_wrclk_reset = 1; + end + + if (count_freq_rdclk == 150) + rise_rdclk = $time; + else if (count_freq_rdclk == 151) + period_rdclk = $time - rise_rdclk; + + if (count_freq_rdclk >= 151 && count_freq_wrclk >= 151 && RST === 1'b0 && GSR === 1'b0) begin + + // Setup ranges for almostempty + if (period_rdclk == period_wrclk) begin + + if (EN_SYN == "FALSE") begin + + if (SIM_DEVICE == "7SERIES") begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 6)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 6); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7); + finish_error = 1; + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + + end // if (SIM_DEVICE == "7SERIES") + else begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + end // else: !if(SIM_DEVICE == "7SERIES") + end // if (EN_SYN == "FALSE") + else begin + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + end // else: !if(EN_SYN == "FALSE") + + end // if (period_rdclk == period_wrclk) + else begin + + real_period_rdclk = period_rdclk * 1.0; + real_period_wrclk = period_wrclk * 1.0; + + roundup_int_period_rdclk_wrclk = (real_period_rdclk / real_period_wrclk) + 0.499; + roundup_int_period_wrclk_rdclk = (real_period_wrclk / real_period_rdclk) + 0.499; + + s7_roundup_int_period_rdclk_wrclk = (4.0 * (real_period_rdclk / real_period_wrclk)) + 0.499; + + + if (SIM_DEVICE == "7SERIES") begin + +// $display ("addr_limit (%h) period_rdclk (%d) period_wrclk (%d) real_period_rdclk (%f) real_period_wrclk (%f) roundup_int_period_rdclk_wrclk (%d) roundup_int_period_wrclk_rdclk (%d) s7_roundup_int_period_rdclk_wrclk (%d) instance %m\n",addr_limit,period_rdclk,period_wrclk,real_period_rdclk,real_period_wrclk,roundup_int_period_rdclk_wrclk,roundup_int_period_wrclk_rdclk,s7_roundup_int_period_rdclk_wrclk); + if (ALMOST_FULL_OFFSET > (addr_limit - (s7_roundup_int_period_rdclk_wrclk + 6))) begin + + $display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((roundup(4 * (WRCLK frequency / RDCLK frequency))) + 6)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET); + finish_error = 1; + + end + end + else begin + + if (ALMOST_FULL_OFFSET > (addr_limit - ((3 * roundup_int_period_wrclk_rdclk) + 3))) begin + + $display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (RDCLK frequency / WRCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET); + finish_error = 1; + + end + + if (ALMOST_EMPTY_OFFSET > (addr_limit - ((3 * roundup_int_period_rdclk_wrclk) + 3))) begin + + $display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (WRCLK frequency / RDCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_EMPTY_OFFSET); + finish_error = 1; + + end + + end // else: !if(SIM_DEVICE == "7SERIES") + + end // else: !if(period_rdclk == period_wrclk) + + count_freq_rdclk = 0; + count_freq_wrclk_reset = 1; + + if (finish_error == 1) + #100 $finish; + + end // if (count_freq_wrclk >= 151 && count_freq_rdclk >= 151 && RST === 1'b0 && GSR === 1'b0) + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK or posedge count_freq_wrclk_reset) begin + + if (count_freq_wrclk_reset == 1) begin + count_freq_wrclk = 0; + count_freq_wrclk_reset = 0; + end else if (((period_wrclk == 0) && (count_freq_wrclk < 152)) || + ((count_freq_wrclk == 0) && (GSR == 1 || RST == 1)) || + ((count_freq_wrclk > 0) && (count_freq_wrclk < 152))) + count_freq_wrclk = count_freq_wrclk + 1; + + + if (count_freq_wrclk == 150) + rise_wrclk = $time; + else if (count_freq_wrclk == 151) begin + period_wrclk = $time - rise_wrclk; + end + + end // always @ (posedge WRCLK) + + + + generate + case (SIM_DEVICE) + + "VIRTEX6" : begin + + // read clock + always @(posedge RDCLK) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (RDEN == 1'b1) begin + + if (EMPTY == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end // if (EMPTY == 1'b0) + end // if (RDEN == 1'b1) + + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + if (WREN == 1'b1) begin + EMPTY = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + EMPTY = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + ALMOSTEMPTY = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + ALMOSTFULL = 1'b0; + end + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rden_reg = RDEN; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1); + + ALMOSTEMPTY = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + + end // always @ (posedge RDCLK) + + + // Write clock + always @(posedge WRCLK) begin + + // DRC + if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m."); + + if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (WREN == 1'b1) begin + + if (FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (RST === 1'b0) begin + + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end // if (FULL == 1'b0) + end // if (WREN == 1'b1) + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + + if (RDEN == 1'b1) begin + FULL = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + FULL = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + ALMOSTEMPTY = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + ALMOSTFULL = 1'b1; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + wren_reg = WREN; + + if (wren_reg == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (wren_reg == 1'b1 && FULL == 1'b0) + + + if (RST === 1'b0) begin + + WRERR = (wren_reg == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || FULL == 1'b1) + FULL = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b0) + + end // always @ (posedge WRCLK) + + +end // case: "VIRTEX6" +"7SERIES" : begin + + always @(posedge RDCLK) begin + if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin + prev_time_rdclk = time_rdclk; + time_rdclk = $time; + end + end + + always @(posedge WRCLK) begin + if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin + prev_time_wrclk = time_wrclk; + time_wrclk = $time; + end + end + + always @(time_rdclk or time_wrclk) begin + if (((time_rdclk - time_wrclk == 0 && prev_time_rdclk - prev_time_wrclk == 0) || (time_wrclk - time_rdclk == 0 && prev_time_wrclk - prev_time_rdclk == 0)) && $time != 0) + sync_clk_async_mode = 1'b1; + if ((((period_wrclk > 0) && (period_rdclk > 0)) || (sync_clk_async_mode == 1'b1)) && (RST == 1'b0) && (GSR == 1'b0)) + sync_clk_async_mode_done = 1'b1; + end + + + // read clock + always @(posedge RDCLK) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (RDEN == 1'b1) begin + + if (EMPTY == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end // if (EMPTY == 1'b0) + end // if (RDEN == 1'b1) + + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + if (WREN == 1'b1) begin + EMPTY = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + EMPTY = 1'b1; + + if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + ALMOSTEMPTY = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + ALMOSTFULL = 1'b0; + end + + + end // if (sync == 1'b1) + + + // async mode + else if (sync == 1'b0) begin + + wr_addr_sync_3 = wr_addr_sync_2; + wr_addr_sync_2 = wr_addr_sync_1; + wr_addr_sync_1 = wr_addr; + + awr_flag_sync_2 = awr_flag_sync_1; + awr_flag_sync_1 = awr_flag; + + + if (sync_clk_async_mode == 1'b1) begin + + rden_reg = RDEN; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1); + + ALMOSTEMPTY = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[1] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + + end // if (sync_clk_async_mode == 1'b1) + else begin + + if (fwft == 1'b0) begin + if (RDEN == 1'b1 && (rd_addr != rdcount_out)) begin + + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + + + if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #0; + rdcount_out_m1 = rdcount_out; + + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((RDEN == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + + if ((rd_prefetch == rd_addr && rd_addr != rdcount_out) || (RST === 1'b1 && fwft_prefetch_flag == 1)) begin + + fwft_prefetch_flag = 0; + + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + + if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #0; + rdcount_out_m1 = rdcount_out; + + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + ALMOSTEMPTY = almostempty_int[0]; + + if (wr_addr_sync_3 - rdcount_out <= ae_empty) + almostempty_int[0] = 1'b1; + else + almostempty_int[0] = 1'b0; + + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr_sync_2) && (rdcount_flag == awr_flag_sync_2)) begin + empty_ram[0] = 1'b1; + end + else begin + empty_ram[0] = 1'b0; + end + + + end // else: !if(sync_clk_async_mode == 1'b1) + + end // if (sync == 1'b0) + + + end // always @ (posedge RDCLK) + + + // Write clock + always @(posedge WRCLK) begin + + // DRC + if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m."); + + if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (WREN == 1'b1) begin + + if (FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (RST === 1'b0) begin + + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end // if (FULL == 1'b0) + end // if (WREN == 1'b1) + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + + if (RDEN == 1'b1) begin + FULL = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + FULL = 1'b1; + + if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + ALMOSTEMPTY = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + ALMOSTFULL = 1'b1; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rdcount_out_sync_3 = rdcount_out_sync_2; + rdcount_out_sync_2 = rdcount_out_sync_1; + rdcount_out_sync_1 = rdcount_out_m1; + + + if (sync_clk_async_mode == 1'b1) begin + + wren_reg = WREN; + + if (wren_reg == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (wren_reg == 1'b1 && FULL == 1'b0) + + + if (RST === 1'b0) begin + + WRERR = (wren_reg == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full + 1)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full + 1)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || FULL == 1'b1) + FULL = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + // fix for 724006 + if (rdcount_out - 1 == wr_addr && (wren_reg == 1'b1 || FULL == 1'b1)) + FULL = full_int[1]; + + + end // if (RST === 1'b0) + + + end // if (sync_clk_async_mode == 1'b1) + + else begin + + + if (WREN == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #0; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (WREN == 1'b1 && FULL == 1'b0) + + + rm1w_eq = (rdcount_out_sync_2 == wr_addr) ? 1 : 0; + + if (wr_addr + 1 == addr_limit) // wr_addr(FF) + 1 != 0 + rm1wp1_eq = (rdcount_out_sync_2 == 0) ? 1 : 0; + else + rm1wp1_eq = (rdcount_out_sync_2 == wr_addr + 1) ? 1 : 0; + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[0]; + + if (rdcount_out_sync_3 - wr_addr <= ae_full) + almostfull_int[0] = 1'b1; + else + almostfull_int[0] = 1'b0; + + + FULL = full_v3; + + + //fwft prefetch + if (EMPTY == 1'b1 && WREN === 1'b1 && fwft_prefetch_flag == 0) + fwft_prefetch_flag = 1; + + + end // if (RST === 1'b0) + + end // else: !if(sync_clk_async_mode == 1'b1) + + end // if (sync == 1'b0) + + end // always @ (posedge WRCLK) + +end // case: "7SERIES" + + +endcase // case(SIM_DEVICE) +endgenerate + + + // output register + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + default : begin + $display("Attribute Syntax Error : The attribute DO_REG on FIFO18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG); + #1 $finish; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + // matching HW behavior to X the unused output bits + assign DO = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]} + : (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]} + : (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]} + : (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]} + : (DATA_WIDTH == 72) ? do_out_mux + : do_out_mux; + + // matching HW behavior to X the unused output bits + assign DOP = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]} + : (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]} + : (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]} + : (DATA_WIDTH == 72) ? dop_out_mux + : 8'bx; + + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : WRCOUNT = {1'b1, wr_addr[counter_width:0]}; + 9 : WRCOUNT = {2'b11, wr_addr[counter_width:0]}; + 18 : WRCOUNT = {3'b111, wr_addr[counter_width:0]}; + 36 : WRCOUNT = {4'hf, wr_addr[counter_width:0]}; + default : WRCOUNT = wr_addr; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : WRCOUNT = wr_addr; + 9 : WRCOUNT = {1'b1, wr_addr[counter_width:0]}; + 18 : WRCOUNT = {2'b11, wr_addr[counter_width:0]}; + 36 : WRCOUNT = {3'b111, wr_addr[counter_width:0]}; + 72 : WRCOUNT = {4'hf, wr_addr[counter_width:0]}; + default : WRCOUNT = wr_addr; + endcase // case(DATA_WIDTH) + + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]}; + 9 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]}; + 18 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]}; + 36 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]}; + default : RDCOUNT = rdcount_out; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : RDCOUNT = rdcount_out; + 9 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]}; + 18 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]}; + 36 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]}; + 72 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]}; + default : RDCOUNT = rdcount_out; + endcase // case(DATA_WIDTH) + + end // always @ (rdcount_out) + + +endmodule + +`endcelldefine + +// end of FF18_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/src/unisims/FIFO18E2.v b/verilog/src/unisims/FIFO18E2.v new file mode 100644 index 0000000..f17078a --- /dev/null +++ b/verilog/src/unisims/FIFO18E2.v @@ -0,0 +1,1759 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 18Kb FIFO (First-In-First-Out) Block RAM Memory +// /___/ /\ Filename : FIFO18E2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 11/30/2012 - intial +// 12/12/2012 - yaml update, 691724 and 691715 +// 02/07/2013 - 699628 - correction to DO_PIPELINED mode +// 02/28/2013 - update to keep in sync with RAMB models +// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC. +// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY +// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there. +// 03/25/2013 - 707719 - Add sync5 cascade feature +// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module FIFO18E2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE_ORDER = "NONE", + parameter CLOCK_DOMAINS = "INDEPENDENT", + parameter FIRST_WORD_FALL_THROUGH = "FALSE", + parameter [35:0] INIT = 36'h000000000, + parameter [0:0] IS_RDCLK_INVERTED = 1'b0, + parameter [0:0] IS_RDEN_INVERTED = 1'b0, + parameter [0:0] IS_RSTREG_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter [0:0] IS_WRCLK_INVERTED = 1'b0, + parameter [0:0] IS_WREN_INVERTED = 1'b0, + parameter integer PROG_EMPTY_THRESH = 256, + parameter integer PROG_FULL_THRESH = 256, + parameter RDCOUNT_TYPE = "RAW_PNTR", + parameter integer READ_WIDTH = 4, + parameter REGISTER_MODE = "UNREGISTERED", + parameter RSTREG_PRIORITY = "RSTREG", + parameter SLEEP_ASYNC = "FALSE", + parameter [35:0] SRVAL = 36'h000000000, + parameter WRCOUNT_TYPE = "RAW_PNTR", + parameter integer WRITE_WIDTH = 4 +)( + output [31:0] CASDOUT, + output [3:0] CASDOUTP, + output CASNXTEMPTY, + output CASPRVRDEN, + output [31:0] DOUT, + output [3:0] DOUTP, + output EMPTY, + output FULL, + output PROGEMPTY, + output PROGFULL, + output [12:0] RDCOUNT, + output RDERR, + output RDRSTBUSY, + output [12:0] WRCOUNT, + output WRERR, + output WRRSTBUSY, + + input [31:0] CASDIN, + input [3:0] CASDINP, + input CASDOMUX, + input CASDOMUXEN, + input CASNXTRDEN, + input CASOREGIMUX, + input CASOREGIMUXEN, + input CASPRVEMPTY, + input [31:0] DIN, + input [3:0] DINP, + input RDCLK, + input RDEN, + input REGCE, + input RST, + input RSTREG, + input SLEEP, + input WRCLK, + input WREN +); + +// define constants + localparam MODULE_NAME = "FIFO18E2"; + +// Parameter encodings and registers + localparam CASCADE_ORDER_FIRST = 1; + localparam CASCADE_ORDER_LAST = 2; + localparam CASCADE_ORDER_MIDDLE = 3; + localparam CASCADE_ORDER_NONE = 0; + localparam CASCADE_ORDER_PARALLEL = 4; + localparam CLOCK_DOMAINS_COMMON = 1; + localparam CLOCK_DOMAINS_INDEPENDENT = 0; + localparam FIRST_WORD_FALL_THROUGH_FALSE = 0; + localparam FIRST_WORD_FALL_THROUGH_TRUE = 1; + localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1; + localparam RDCOUNT_TYPE_RAW_PNTR = 0; + localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2; + localparam RDCOUNT_TYPE_SYNC_PNTR = 3; + localparam READ_WIDTH_18 = 16; + localparam READ_WIDTH_36 = 32; + localparam READ_WIDTH_4 = 4; + localparam READ_WIDTH_9 = 8; + localparam REGISTER_MODE_DO_PIPELINED = 1; + localparam REGISTER_MODE_REGISTERED = 2; + localparam REGISTER_MODE_UNREGISTERED = 0; + localparam RSTREG_PRIORITY_REGCE = 1; + localparam RSTREG_PRIORITY_RSTREG = 0; + localparam SLEEP_ASYNC_FALSE = 0; + localparam SLEEP_ASYNC_TRUE = 1; + localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1; + localparam WRCOUNT_TYPE_RAW_PNTR = 0; + localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2; + localparam WRCOUNT_TYPE_SYNC_PNTR = 3; + localparam WRITE_WIDTH_18 = 16; + localparam WRITE_WIDTH_36 = 32; + localparam WRITE_WIDTH_4 = 4; + localparam WRITE_WIDTH_9 = 8; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "FIFO18E2_dr.v" +`else + localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER; + localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS; + localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH; + localparam [35:0] INIT_REG = INIT; + localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED; + localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED; + localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED; + localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED; + localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH; + localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH; + localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE; + localparam [5:0] READ_WIDTH_REG = READ_WIDTH; + localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE; + localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY; + localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC; + localparam [35:0] SRVAL_REG = SRVAL; + localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE; + localparam [5:0] WRITE_WIDTH_REG = WRITE_WIDTH; +`endif + + wire [2:0] CASCADE_ORDER_BIN; + wire CLOCK_DOMAINS_BIN; + wire FIRST_WORD_FALL_THROUGH_BIN; + wire [35:0] INIT_BIN; + wire IS_RDCLK_INVERTED_BIN; + wire IS_RDEN_INVERTED_BIN; + wire IS_RSTREG_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire IS_WRCLK_INVERTED_BIN; + wire IS_WREN_INVERTED_BIN; + wire [12:0] PROG_EMPTY_THRESH_BIN; + wire [12:0] PROG_FULL_THRESH_BIN; + wire [1:0] RDCOUNT_TYPE_BIN; + wire [5:0] READ_WIDTH_BIN; + wire [1:0] REGISTER_MODE_BIN; + wire RSTREG_PRIORITY_BIN; + wire SLEEP_ASYNC_BIN; + wire [35:0] SRVAL_BIN; + wire [1:0] WRCOUNT_TYPE_BIN; + wire [6:0] WRITE_WIDTH_BIN; + reg INIT_MEM = 0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR || INIT_MEM; + + wire CASNXTEMPTY_out; + wire CASPRVRDEN_out; + wire EMPTY_out; + wire FULL_out; + wire PROGEMPTY_out; + wire PROGFULL_out; + wire RDERR_out; + wire RDRSTBUSY_out; + wire WRERR_out; + wire WRRSTBUSY_out; + wire [12:0] RDCOUNT_out; + wire [12:0] WRCOUNT_out; + wire [31:0] CASDOUT_out; + reg [31:0] DOUT_out; + wire [3:0] CASDOUTP_out; + reg [3:0] DOUTP_out; + + wire CASDOMUXEN_in; + wire CASDOMUX_in; + wire CASNXTRDEN_in; + wire CASOREGIMUXEN_in; + wire CASOREGIMUX_in; + wire CASPRVEMPTY_in; + wire RDCLK_in; + wire RDEN_in; + wire REGCE_in; + wire RSTREG_in; + wire RST_in; + wire SLEEP_in; + wire WRCLK_in; + wire WREN_in; + wire [31:0] CASDIN_in; + reg [31:0] DIN_in; + wire [3:0] CASDINP_in; + reg [3:0] DINP_in; + +`ifdef XIL_TIMING + wire CASDOMUXEN_delay; + wire CASDOMUX_delay; + wire CASNXTRDEN_delay; + wire CASOREGIMUXEN_delay; + wire CASOREGIMUX_delay; + wire CASPRVEMPTY_delay; + wire RDCLK_delay; + wire RDEN_delay; + wire REGCE_delay; + wire RSTREG_delay; + wire RST_delay; + wire SLEEP_delay; + wire WRCLK_delay; + wire WREN_delay; + wire [31:0] CASDIN_delay; + wire [31:0] DIN_delay; + wire [3:0] CASDINP_delay; + wire [3:0] DINP_delay; +`endif + + assign CASDOUT = CASDOUT_out; + assign CASDOUTP = CASDOUTP_out; + assign CASNXTEMPTY = CASNXTEMPTY_out; + assign CASPRVRDEN = CASPRVRDEN_out; + assign DOUT = DOUT_out; + assign DOUTP = DOUTP_out; + assign EMPTY = EMPTY_out; + assign FULL = FULL_out; + assign PROGEMPTY = PROGEMPTY_out; + assign PROGFULL = PROGFULL_out; + assign RDCOUNT = RDCOUNT_out; + assign RDERR = RDERR_out; + assign RDRSTBUSY = RDRSTBUSY_out; + assign WRCOUNT = WRCOUNT_out; + assign WRERR = WRERR_out; + assign WRRSTBUSY = WRRSTBUSY_out; + +`ifdef XIL_TIMING + assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP_delay[0]; // rv 0 + assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP_delay[1]; // rv 0 + assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP_delay[2]; // rv 0 + assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP_delay[3]; // rv 0 + assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN_delay[0]; // rv 0 + assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN_delay[10]; // rv 0 + assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN_delay[11]; // rv 0 + assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN_delay[12]; // rv 0 + assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN_delay[13]; // rv 0 + assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN_delay[14]; // rv 0 + assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN_delay[15]; // rv 0 + assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN_delay[16]; // rv 0 + assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN_delay[17]; // rv 0 + assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN_delay[18]; // rv 0 + assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN_delay[19]; // rv 0 + assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN_delay[1]; // rv 0 + assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN_delay[20]; // rv 0 + assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN_delay[21]; // rv 0 + assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN_delay[22]; // rv 0 + assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN_delay[23]; // rv 0 + assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN_delay[24]; // rv 0 + assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN_delay[25]; // rv 0 + assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN_delay[26]; // rv 0 + assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN_delay[27]; // rv 0 + assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN_delay[28]; // rv 0 + assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN_delay[29]; // rv 0 + assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN_delay[2]; // rv 0 + assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN_delay[30]; // rv 0 + assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN_delay[31]; // rv 0 + assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN_delay[3]; // rv 0 + assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN_delay[4]; // rv 0 + assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN_delay[5]; // rv 0 + assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN_delay[6]; // rv 0 + assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN_delay[7]; // rv 0 + assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN_delay[8]; // rv 0 + assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN_delay[9]; // rv 0 + assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN_delay; // rv 1 + assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX_delay; // rv 0 + assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN_delay; // rv 0 + assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN_delay; // rv 1 + assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX_delay; // rv 0 + assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY_delay; // rv 0 + always @ (*) DINP_in = DINP_delay; + always @ (*) DIN_in = DIN_delay; + assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK_delay ^ IS_RDCLK_INVERTED_BIN); // rv 0 + assign RDEN_in = (RDEN !== 1'bz) && (RDEN_delay ^ IS_RDEN_INVERTED_BIN); // rv 0 + assign REGCE_in = (REGCE === 1'bz) || REGCE_delay; // rv 1 + assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG_delay ^ IS_RSTREG_INVERTED_BIN); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST_delay ^ IS_RST_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 + assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK_delay ^ IS_WRCLK_INVERTED_BIN); // rv 0 + assign WREN_in = (WREN !== 1'bz) && (WREN_delay ^ IS_WREN_INVERTED_BIN); // rv 0 +`else + assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP[0]; // rv 0 + assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP[1]; // rv 0 + assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP[2]; // rv 0 + assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP[3]; // rv 0 + assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN[0]; // rv 0 + assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN[10]; // rv 0 + assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN[11]; // rv 0 + assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN[12]; // rv 0 + assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN[13]; // rv 0 + assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN[14]; // rv 0 + assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN[15]; // rv 0 + assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN[16]; // rv 0 + assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN[17]; // rv 0 + assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN[18]; // rv 0 + assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN[19]; // rv 0 + assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN[1]; // rv 0 + assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN[20]; // rv 0 + assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN[21]; // rv 0 + assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN[22]; // rv 0 + assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN[23]; // rv 0 + assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN[24]; // rv 0 + assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN[25]; // rv 0 + assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN[26]; // rv 0 + assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN[27]; // rv 0 + assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN[28]; // rv 0 + assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN[29]; // rv 0 + assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN[2]; // rv 0 + assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN[30]; // rv 0 + assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN[31]; // rv 0 + assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN[3]; // rv 0 + assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN[4]; // rv 0 + assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN[5]; // rv 0 + assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN[6]; // rv 0 + assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN[7]; // rv 0 + assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN[8]; // rv 0 + assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN[9]; // rv 0 + assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN; // rv 1 + assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX; // rv 0 + assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN; // rv 0 + assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN; // rv 1 + assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX; // rv 0 + assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY; // rv 0 + always @ (*) DINP_in = DINP; + always @ (*) DIN_in = DIN; + assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK ^ IS_RDCLK_INVERTED_BIN); // rv 0 + assign RDEN_in = (RDEN !== 1'bz) && (RDEN ^ IS_RDEN_INVERTED_BIN); // rv 0 + assign REGCE_in = (REGCE === 1'bz) || REGCE; // rv 1 + assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG ^ IS_RSTREG_INVERTED_BIN); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 + assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK ^ IS_WRCLK_INVERTED_BIN); // rv 0 + assign WREN_in = (WREN !== 1'bz) && (WREN ^ IS_WREN_INVERTED_BIN); // rv 0 +`endif + +// internal variables, signals, busses + localparam integer ADDR_WIDTH = 14; + localparam integer INIT_WIDTH = 36; + localparam integer D_WIDTH = 32; + localparam integer DP_WIDTH = 4; + + localparam mem_width = 1; + localparam memp_width = 1; + localparam mem_size = 16384; + localparam mem_depth = mem_size; + localparam memp_depth = mem_size/8; + localparam mem_pad = 32; + localparam memp_pad = 4; + integer i=0; + integer j=0; + integer k=0; + integer ra=0; + integer raa=0; + integer raw=0; + integer wb=0; + integer rd_loops_a = 1; + integer wr_loops_b = 1; + localparam max_rd_loops = D_WIDTH; + localparam max_wr_loops = D_WIDTH; + integer rdcount_adj = 0; + integer wrcount_adj = 0; + integer wr_adj = 0; + wire RDEN_int; + wire RDEN_lat; + wire WREN_int; + wire WREN_lat; + wire RDEN_reg; + reg fill_lat=0; + reg fill_reg=0; + wire SLEEP_A_int; + wire SLEEP_B_int; + reg [1:0] SLEEP_A_reg = 2'b0; + reg [1:0] SLEEP_B_reg = 2'b0; + wire RSTREG_A_int; + wire REGCE_A_int; + wire [3:0] DINP_int; + reg CASDOMUXA_reg = 1'b0; + reg CASOREGIMUXA_reg = 1'b0; + wire prog_empty; + reg prog_empty_cc = 1; + reg ram_full_c = 0; + wire ram_empty; + reg ram_empty_i = 1; + reg ram_empty_c = 1; + reg o_lat_empty = 1; + reg o_reg_empty = 1; + wire [1:0] output_stages; + wire o_stages_full; + wire o_stages_empty; + reg o_stages_full_sync=0; + reg o_stages_full_sync1=0; + reg o_stages_full_sync2=0; + reg o_stages_full_sync3=0; + wire prog_full; + reg prog_full_reg = 1'b0; + reg rderr_reg = 1'b0; + reg wrerr_reg = 1'b0; + wire [INIT_WIDTH-1:0] INIT_A_int; + wire [INIT_WIDTH-1:0] SRVAL_A_int; + + wire mem_wr_en_b; + reg mem_wr_en_b_wf = 1'b0; + wire [D_WIDTH-1:0] mem_we_b; + wire [DP_WIDTH-1:0] memp_we_b; + wire [D_WIDTH-1:0] mem_rm_douta; + wire [DP_WIDTH-1:0] memp_rm_douta; + wire mem_rd_en_a; + wire mem_rst_a; + reg mem_is_rst_a = 1'b0; + reg rdcount_en = 1'b0; + + reg mem [0 : mem_depth+mem_pad-1]; + reg [D_WIDTH-1 : 0] ram_rd_a; + reg [D_WIDTH-1 : 0] mem_wr_b; + reg wr_b_event = 1'b0; + reg [D_WIDTH-1 : 0] mem_rd_b_rf; + reg [D_WIDTH-1 : 0] mem_rd_b_wf; + reg [D_WIDTH-1 : 0] mem_a_reg; + reg [D_WIDTH-1 : 0] mem_a_reg_mux; + reg [D_WIDTH-1 : 0] mem_a_lat; + reg memp [0 : memp_depth+memp_pad-1]; + reg [DP_WIDTH-1 : 0] ramp_rd_a; + wire [DP_WIDTH-1 : 0] memp_wr_b; + reg [DP_WIDTH-1 : 0] memp_rd_b_rf; + reg [DP_WIDTH-1 : 0] memp_rd_b_wf; + reg [DP_WIDTH-1 : 0] memp_a_reg; + reg [DP_WIDTH-1 : 0] memp_a_reg_mux; + reg [DP_WIDTH-1 : 0] memp_a_lat; + reg [DP_WIDTH-1 : 0] memp_a_out; + wire [ADDR_WIDTH-1:0] wr_addr_b_mask; + reg [ADDR_WIDTH-1:0] rd_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b = 0; + reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0; + wire [ADDR_WIDTH-1:0] rd_addr_wr; + wire [ADDR_WIDTH-1:0] next_rd_addr_wr; + wire [ADDR_WIDTH-1:0] wr_addr_rd; + wire [ADDR_WIDTH-1:0] next_wr_addr_rd; + wire [ADDR_WIDTH:0] wr_simple_raw; +// wire [ADDR_WIDTH:0] rd_simple_raw; + wire [ADDR_WIDTH-1:0] wr_simple; + wire [ADDR_WIDTH:0] rd_simple; + reg [ADDR_WIDTH-1:0] rd_simple_cc = 0; + reg [ADDR_WIDTH-1:0] wr_simple_sync = 0; + reg [ADDR_WIDTH-1:0] rd_simple_sync = 0; + +//reset logic variables + reg WRRST_int = 1'b0; + reg RST_sync = 1'b0; + reg WRRST_done = 1'b0; + reg WRRST_done1 = 1'b0; + reg WRRST_done2 = 1'b0; + wire RDRST_int; + reg RDRST_done = 1'b0; + reg RDRST_done1 = 1'b0; + reg RDRST_done2 = 1'b0; + wire WRRST_done_wr; + reg WRRST_in_sync_rd = 1'b0; + reg WRRST_in_sync_rd1 = 1'b0; + reg WRRSTBUSY_dly = 1'b0; + reg WRRSTBUSY_dly1 = 1'b0; + reg RDRSTBUSY_dly = 1'b0; + reg RDRSTBUSY_dly1 = 1'b0; + reg RDRSTBUSY_dly2 = 1'b0; + + reg sdp_mode = 1'b1; + reg sdp_mode_wr = 1'b1; + reg sdp_mode_rd = 1'b1; + +// full/empty variables + wire [ADDR_WIDTH-1:0] full_count; + wire [ADDR_WIDTH-1:0] next_full_count; + wire [ADDR_WIDTH-1:0] full_count_masked; + wire [8:0] m_full; + wire [8:0] m_full_raw; + wire [5:0] n_empty; + wire [5:0] unr_ratio; + wire [ADDR_WIDTH+1:0] prog_full_val; + wire [ADDR_WIDTH+1:0] prog_empty_val; + + reg ram_full_i; + wire ram_one_from_full_i; + wire ram_two_from_full_i; + wire ram_one_from_full; + wire ram_two_from_full; + wire ram_one_read_from_not_full; + + wire [ADDR_WIDTH-1:0] empty_count; + wire [ADDR_WIDTH-1:0] next_empty_count; + wire ram_one_read_from_empty_i; + wire ram_one_read_from_empty; + wire ram_one_write_from_not_empty; + wire ram_one_write_from_not_empty_i; + +reg en_clk_sync = 1'b0; + +reg cas_warning = 1'b0; +task is_cas_connected; +integer i; +begin + for (i=0;i<=31;i=i+1) begin + if (CASDIN[i] === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDIN[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + for (i=0;i<=3;i=i+1) begin + if (CASDINP[i] === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDINP[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + if (CASDOMUX === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDOMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASDOMUXEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDOMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASNXTRDEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASNXTRDEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASOREGIMUX === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASOREGIMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASOREGIMUXEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASOREGIMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end +end +endtask // is_cas_connected + + assign RDEN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + CASNXTRDEN_in && ~SLEEP_A_int : RDEN_in; + assign WREN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + ~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : WREN_in; + assign DINP_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_in : DINP_in; + assign mem_wr_en_b = WREN_int && ~FULL_out && ~WRRSTBUSY_out; + assign mem_rd_en_a = (RDEN_int || + ((fill_lat || fill_reg) && ~SLEEP_A_int)) && + ~ram_empty && ~RDRST_int; + always @ (*) begin + if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) + mem_wr_b = CASDIN_in; + else + mem_wr_b = DIN_in; + end + assign memp_wr_b = DINP_int; + +//victor DRC +reg sleep_is_asserted; +reg sleep_is_deasserted; +reg RDEN_p1; +reg RDEN_p2; +reg RDEN_p3; +reg RDEN_p4; +reg RDEN_p5; +reg RDEN_p6; +reg WREN_p1; +reg WREN_p2; +reg WREN_p3; +reg SLEEPA_p1; +reg SLEEPA_p2; +reg SLEEPB_p1; +reg SLEEPB_p2; + + always @(SLEEP_in) begin + sleep_is_asserted <= 1'b0; + sleep_is_deasserted <= 1'b0; + if (SLEEP_in == 1'b1) + sleep_is_asserted <= 1'b1; + else if (SLEEP_in == 1'b0) + sleep_is_deasserted <= 1'b1; + end + + //victor drc #5 + always @(posedge RDCLK_in) begin + if (sleep_is_asserted && RDEN_in) begin + $display("Error: [Unisim %s-23] DRC : RDEN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + always @(posedge WRCLK_in) begin + if (sleep_is_asserted && WREN_in) begin + $display("Error: [Unisim %s-23] DRC : WREN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in) begin + if (glblGSR) begin + RDEN_p1 <= 1'b0; + RDEN_p2 <= 1'b0; + RDEN_p3 <= 1'b0; + RDEN_p4 <= 1'b0; + RDEN_p5 <= 1'b0; + RDEN_p6 <= 1'b0; + end + else begin + RDEN_p1 <= RDEN_in; + RDEN_p2 <= RDEN_p1; + RDEN_p3 <= RDEN_p2; + RDEN_p4 <= RDEN_p3; + RDEN_p5 <= RDEN_p4; + RDEN_p6 <= RDEN_p5; + end + end + always @(posedge WRCLK_in) begin + if (glblGSR) begin + WREN_p1 <= 1'b0; + WREN_p2 <= 1'b0; + WREN_p3 <= 1'b0; + end + else begin + WREN_p1 <= WREN_in; + WREN_p2 <= WREN_p1; + WREN_p3 <= WREN_p2; + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if (FIRST_WORD_FALL_THROUGH_REG == "FALSE") begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one RDCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "COMMON")) begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p3) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least three cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "INDEPENDENT")) begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p3 && RDEN_p6) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK plus six RDCLK cycles before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + //victor drc #6 + always @(posedge RDCLK_in) begin + if (glblGSR) begin + SLEEPA_p1 <= 1'b0; + SLEEPA_p2 <= 1'b0; + end + else begin + SLEEPA_p1 <= SLEEP_in; + SLEEPA_p2 <= SLEEPA_p1; + end + end + always @(posedge WRCLK_in) begin + if (glblGSR) begin + SLEEPB_p1 <= 1'b0; + SLEEPB_p2 <= 1'b0; + end + else begin + SLEEPB_p1 <= SLEEP_in; + SLEEPB_p2 <= SLEEPB_p1; + end + end + always @(RDEN_in) begin + if (RDEN_in && SLEEPA_p2) + $display("Error: [Unisim %s-23] DRC : RDEN can be asserted at least 2 cycles RDCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME); + end + always @(WREN_in) begin + if (WREN_in && SLEEPB_p2) + $display("Error: [Unisim %s-23] DRC : WREN can be asserted at least 2 cycles WRCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME); + end + + assign CASCADE_ORDER_BIN = + (CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE : + (CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST : + (CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST : + (CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE : + (CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL : + CASCADE_ORDER_NONE; + + assign CLOCK_DOMAINS_BIN = + (CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT : + (CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON : + CLOCK_DOMAINS_INDEPENDENT; + + assign FIRST_WORD_FALL_THROUGH_BIN = + (FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE : + (FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE : + FIRST_WORD_FALL_THROUGH_FALSE; + + assign INIT_BIN = INIT_REG; + + assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG; + + assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG; + + assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG; + + assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG; + + assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG; + + assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG; + + assign RDCOUNT_TYPE_BIN = + (RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR : + (RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT : + (RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT : + (RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR : + RDCOUNT_TYPE_RAW_PNTR; + + assign READ_WIDTH_BIN = + (READ_WIDTH_REG == 4) ? READ_WIDTH_4 : + (READ_WIDTH_REG == 9) ? READ_WIDTH_9 : + (READ_WIDTH_REG == 18) ? READ_WIDTH_18 : + (READ_WIDTH_REG == 36) ? READ_WIDTH_36 : + READ_WIDTH_4; + + assign REGISTER_MODE_BIN = + (REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED : + (REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED : + (REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED : + REGISTER_MODE_UNREGISTERED; + + assign RSTREG_PRIORITY_BIN = + (RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG : + (RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE : + RSTREG_PRIORITY_RSTREG; + + assign SLEEP_ASYNC_BIN = + (SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE : + (SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE : + SLEEP_ASYNC_FALSE; + + assign SRVAL_BIN = SRVAL_REG; + + assign WRCOUNT_TYPE_BIN = + (WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR : + (WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT : + (WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT : + (WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR : + WRCOUNT_TYPE_RAW_PNTR; + + assign WRITE_WIDTH_BIN = + (WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 : + (WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 : + (WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 : + (WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 : + WRITE_WIDTH_4; + + initial begin + #1; + trig_attr = 1'b1; + #100; + trig_attr = 1'b0; + end + + always @ (posedge trig_attr) begin + INIT_MEM <= #100 1'b1; + INIT_MEM <= #200 1'b0; + + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_REG != "NONE") && + (CASCADE_ORDER_REG != "FIRST") && + (CASCADE_ORDER_REG != "LAST") && + (CASCADE_ORDER_REG != "MIDDLE") && + (CASCADE_ORDER_REG != "PARALLEL"))) begin + $display("Error: [Unisim %s-101] CASCADE_ORDER attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLOCK_DOMAINS_REG != "INDEPENDENT") && + (CLOCK_DOMAINS_REG != "COMMON"))) begin + $display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIRST_WORD_FALL_THROUGH_REG != "FALSE") && + (FIRST_WORD_FALL_THROUGH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] FIRST_WORD_FALL_THROUGH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191))) begin + $display("Error: [Unisim %s-114] PROG_EMPTY_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191))) begin + $display("Error: [Unisim %s-115] PROG_FULL_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RDCOUNT_TYPE_REG != "RAW_PNTR") && + (RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") && + (RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") && + (RDCOUNT_TYPE_REG != "SYNC_PNTR"))) begin + $display("Error: [Unisim %s-116] RDCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, RDCOUNT_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_WIDTH_REG != 4) && + (READ_WIDTH_REG != 9) && + (READ_WIDTH_REG != 18) && + (READ_WIDTH_REG != 36))) begin + $display("Error: [Unisim %s-117] READ_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18 or 36. Instance: %m", MODULE_NAME, READ_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REGISTER_MODE_REG != "UNREGISTERED") && + (REGISTER_MODE_REG != "DO_PIPELINED") && + (REGISTER_MODE_REG != "REGISTERED"))) begin + $display("Error: [Unisim %s-118] REGISTER_MODE attribute is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED. Instance: %m", MODULE_NAME, REGISTER_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RSTREG_PRIORITY_REG != "RSTREG") && + (RSTREG_PRIORITY_REG != "REGCE"))) begin + $display("Error: [Unisim %s-119] RSTREG_PRIORITY attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SLEEP_ASYNC_REG != "FALSE") && + (SLEEP_ASYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRCOUNT_TYPE_REG != "RAW_PNTR") && + (WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") && + (WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") && + (WRCOUNT_TYPE_REG != "SYNC_PNTR"))) begin + $display("Error: [Unisim %s-122] WRCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, WRCOUNT_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_WIDTH_REG != 4) && + (WRITE_WIDTH_REG != 9) && + (WRITE_WIDTH_REG != 18) && + (WRITE_WIDTH_REG != 36))) begin + $display("Error: [Unisim %s-123] WRITE_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18 or 36. Instance: %m", MODULE_NAME, WRITE_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (PROG_EMPTY_THRESH_REG < 1) || + (PROG_EMPTY_THRESH_REG >= mem_depth/READ_WIDTH_BIN)) begin + $display("Error: [Unisim %s-124] PROG_EMPTY_THRESH is set to %d. When READ_WIDTH is set to %d PROG_EMPTY_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG, READ_WIDTH_REG, mem_depth/READ_WIDTH_BIN); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (PROG_FULL_THRESH_REG < 1) || + (PROG_FULL_THRESH_REG >= mem_depth/WRITE_WIDTH_BIN)) begin + $display("Error: [Unisim %s-125] PROG_FULL_THRESH is set to %d. When WRITE_WIDTH is set to %d PROG_FULL_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG, WRITE_WIDTH_REG, mem_depth/WRITE_WIDTH_BIN); + attr_err = 1'b1; + end + + if ((CASCADE_ORDER_REG == "LAST") || + (CASCADE_ORDER_REG == "MIDDLE") || + (CASCADE_ORDER_REG == "PARALLEL")) begin + is_cas_connected; + if (cas_warning) $display("Warning: [Unisim %s-126] CASCADE_ORDER attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG); + end + + if (attr_err == 1'b1) #100 $finish; + end + + initial begin + INIT_MEM <= #100 1'b1; + INIT_MEM <= #200 1'b0; + end + + assign output_stages = + ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) && + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b10 : + ((REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) && + (FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 : 2'b01; + + assign wr_addr_b_mask = + (WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} : + (WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} : + (WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} : + (WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} : + {{ADDR_WIDTH-6{1'b1}}, 6'h3f}; + + always @(READ_WIDTH_BIN) rd_loops_a <= READ_WIDTH_BIN; + always @(WRITE_WIDTH_BIN) wr_loops_b <= WRITE_WIDTH_BIN; + + always @ (posedge RDCLK_in) begin + if (glblGSR) begin + SLEEP_A_reg <= 2'b0; + end + else begin + SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in}; + end + end + + always @ (posedge WRCLK_in) begin + if (glblGSR) begin + SLEEP_B_reg <= 2'b0; + end + else begin + SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in}; + end + end + + assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in; + assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in; + + assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg : + REGCE_in; + assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int : + (RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in : + (RSTREG_in && REGCE_in); + assign RDEN_lat = RDEN_int || ((fill_reg || fill_lat) && ~SLEEP_A_int); + assign WREN_lat = mem_rd_en_a; + assign RDEN_reg = RDEN_int || fill_reg ; + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) + DOUT_out = CASDIN_in; + else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) + DOUT_out = mem_a_reg ^ mem_rm_douta; + else + DOUT_out = mem_a_lat ^ mem_rm_douta; + end + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) + DOUTP_out = CASDINP_in; + else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) + DOUTP_out = memp_a_reg ^ memp_rm_douta; + else + DOUTP_out = memp_a_lat ^ memp_rm_douta; + end + assign INIT_A_int = + (READ_WIDTH_BIN <= READ_WIDTH_9) ? {{4{INIT_BIN[8]}}, {4{INIT_BIN[7:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_18) ? {{2{INIT_BIN[17:16]}}, {2{INIT_BIN[15:0]}}} : + INIT_BIN; + + assign SRVAL_A_int = + (READ_WIDTH_BIN <= READ_WIDTH_9) ? {{4{SRVAL_BIN[8]}}, {4{SRVAL_BIN[7:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_18) ? {{2{SRVAL_BIN[17:16]}}, {2{SRVAL_BIN[15:0]}}} : + SRVAL_BIN; + + + assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr; + assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd; +// in clock domains common what is important is the result of the next clock edge. + assign next_rd_addr_wr = (mem_rd_en_a == 1'b1) ? rd_addr_a + rd_loops_a : rd_addr_a; + assign next_wr_addr_rd = (mem_wr_en_b == 1'b1) ? wr_addr_b + wr_loops_b : wr_addr_b; + + assign o_stages_empty = + (output_stages==2'b00) ? ram_empty : + (output_stages==2'b01) ? o_lat_empty : + o_reg_empty; // 2 + assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync; + +// cascade out + assign CASDOUT_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + DOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTP_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + DOUTP_out : {DP_WIDTH-1{1'b0}}; + assign CASNXTEMPTY_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + EMPTY_out || SLEEP_A_int : 1'b0; + assign CASPRVRDEN_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + ~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : 1'b0; + +// start model internals + +// integers / constants + always begin + if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b; + else wr_adj = 1; + @(wr_loops_b or rd_loops_a); + end + + always begin + if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) || + ((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0))) + wrcount_adj = 1; + else if ((output_stages>1) || + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) + wrcount_adj = output_stages*wr_adj; + else + wrcount_adj = 0; + if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) + rdcount_adj = 0; + else if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) + rdcount_adj = output_stages; + @(wr_adj or output_stages or wr_loops_b or rd_loops_a or FIRST_WORD_FALL_THROUGH_BIN or RDCOUNT_TYPE_BIN); + end + +// reset logic + assign RDRSTBUSY_out = RDRST_int; + assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly; + assign mem_rst_a = RDRST_int; + + +// RST_in sampled by WRCLK cleared by WR done + always @ (posedge WRCLK_in) begin + if (RST_in && ~RST_sync) begin + RST_sync <= 1'b1; + end + else if (WRRST_done) begin + RST_sync <= 1'b0; + end + end + + assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done; + always @ (posedge WRCLK_in) begin + if (RST_in && ~WRRSTBUSY_out) begin + WRRST_int <= #1 1'b1; + end + else if (WRRST_done_wr) begin + WRRST_int <= #1 1'b0; + end + end + +// WRRST_int sampled by RDCLK twice => RDRST_int in CDI + assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd; + always @ (posedge RDCLK_in) begin + if (glblGSR) begin + WRRST_in_sync_rd1 <= 1'b0; + WRRST_in_sync_rd <= 1'b0; + end + else begin + WRRST_in_sync_rd1 <= #1 WRRST_int; + WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1; + end + end + +// 3 rdclks to be done RD side + always @ (posedge RDCLK_in) begin + if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin + RDRST_done2 <= 1'b0; + RDRST_done1 <= 1'b0; + RDRST_done <= 1'b0; + end + else begin + RDRST_done2 <= RDRST_int; + RDRST_done1 <= RDRST_done2; + RDRST_done <= RDRST_done1; + end + end + +// 3 wrclks to be done WR side after RDRST_done + always @ (posedge WRCLK_in) begin + if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin + WRRST_done2 <= 1'b0; + WRRST_done1 <= 1'b0; + WRRST_done <= 1'b0; + end + else if (WRRST_int) begin + WRRST_done2 <= RDRST_done; + WRRST_done1 <= WRRST_done2; + WRRST_done <= WRRST_done1; + end + end + +// bug fix - 3 rd 2 wr. rtl verified + always @ (posedge RDCLK_in) begin + if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin + RDRSTBUSY_dly2 <= 1'b0; + RDRSTBUSY_dly1 <= 1'b0; + RDRSTBUSY_dly <= 1'b0; + end + else begin + RDRSTBUSY_dly2 <= RDRST_int; + RDRSTBUSY_dly1 <= RDRSTBUSY_dly2; + RDRSTBUSY_dly <= RDRSTBUSY_dly1; + end + end + + always @ (posedge WRCLK_in) begin + if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin + WRRSTBUSY_dly1 <= 1'b0; + WRRSTBUSY_dly <= 1'b0; + end + else begin + WRRSTBUSY_dly1 <= RDRSTBUSY_dly; + WRRSTBUSY_dly <= WRRSTBUSY_dly1; + end + end + +// cascade control + always @ (posedge RDCLK_in) begin + if (glblGSR) CASDOMUXA_reg <= 1'b0; + else CASDOMUXA_reg <= CASDOMUX_in; // EN tied to 1 in FIFO + end + + always @ (posedge RDCLK_in) begin + if (glblGSR) CASOREGIMUXA_reg <= 1'b0; + else CASOREGIMUXA_reg <= CASOREGIMUX_in; // EN tied to 1 in FIFO + end + +// output register + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && + CASOREGIMUXA_reg) mem_a_reg_mux = CASDIN_in; + else mem_a_reg_mux = mem_a_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && + CASOREGIMUXA_reg) memp_a_reg_mux = CASDINP_in; + else memp_a_reg_mux = memp_a_lat; + end + + always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_reg, mem_a_reg} <= #100 INIT_A_int; + end + else if (RSTREG_A_int) begin + {memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int; + end + else if (REGCE_A_int) begin + mem_a_reg <= #100 mem_a_reg_mux; + memp_a_reg <= #100 memp_a_reg_mux; + end + end + + wire fifo_cc_count; + assign fifo_cc_count = (WRITE_WIDTH_BIN==READ_WIDTH_BIN) && (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON); + +// RDCOUNT sync to RDCLK +// assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a}; + assign rd_simple = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a}; +// assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0]; + assign RDCOUNT_out = + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && ~fifo_cc_count ? rd_simple_sync : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && fifo_cc_count ? rd_simple_cc : + (rd_addr_a/rd_loops_a); + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + rd_simple_cc <= 0; + else if (fifo_cc_count) + if ((RDEN_int && ~EMPTY_out) && ~mem_wr_en_b) + rd_simple_cc <= rd_simple_cc - 1; + else if ((~RDEN_int || EMPTY_out) && mem_wr_en_b) + rd_simple_cc <= rd_simple_cc + 1; + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + rd_simple_sync <= 0; + else if (rdcount_en) + if (rd_simple[ADDR_WIDTH-1:0] == {ADDR_WIDTH-1{1'b0}}) + rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]}/rd_loops_a + rdcount_adj; + else + rd_simple_sync <= rd_simple[ADDR_WIDTH-1:0]/rd_loops_a + rdcount_adj; + end + +// WRCOUNT sync to WRCLK + assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr}; + assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0]; + assign WRCOUNT_out = + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? wr_addr_b/wr_loops_b : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? wr_addr_rd/wr_loops_b : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync : + wr_addr_b/wr_loops_b; + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) + wr_simple_sync <= 0; + else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) + wr_simple_sync <= wr_simple/wr_loops_b; + else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) + wr_simple_sync <= (wr_simple/wr_loops_b) + wrcount_adj; + end + +// with any output stage or FWFT fill the ouptut latch +// when ram not empty and o_latch empty + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + o_lat_empty <= 1; + end + else if (RDEN_lat) begin + o_lat_empty <= ram_empty; + end + else if (WREN_lat == 1) begin + o_lat_empty <= 0; + end + end + + always @ (negedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int || SLEEP_A_int) begin + fill_lat <= 0; + end + else if (o_lat_empty == 1) begin + if (output_stages>0) begin + fill_lat <= ~ram_empty; + end + end + else begin + fill_lat <= 0; + end + end + +// FWFT and +// REGISTERED fill the ouptut register when o_latch not empty. +// Empty on external read and prev stage also empty + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + o_reg_empty <= 1; + end + else if ((o_lat_empty == 0) && RDEN_reg) begin + o_reg_empty <= 0; + end + else if ((o_lat_empty == 1) && RDEN_reg) begin + o_reg_empty <= 1; + end + end + + always @ (negedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int || SLEEP_A_int) begin + fill_reg <= 0; + end + else if ((o_lat_empty == 0) && (o_reg_empty == 1) && + (output_stages==2)) begin + fill_reg <= 1; + end + else begin + fill_reg <= 0; + end + end + +// read engine + always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin + if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin + for (raa=0;raa= 8) begin + for (raa=0;raa> ra; + if (ra> (D_WIDTH+ra); + end + end + rdcount_en <= 1'b0; + end + else if (SLEEP_A_int && mem_rd_en_a) begin + $display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_a <= 1'b0; + for (ra=0;ra> ra; + if (ra> (D_WIDTH+ra); + end + end + end + end + else if (WREN_lat) begin + mem_is_rst_a <= 1'b0; + mem_a_lat <= #100 ram_rd_a; + memp_a_lat <= #100 ramp_rd_a; + rdcount_en <= 1'b1; + end + else if (RDEN_int) begin + rdcount_en <= 1'b1; + end + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + rd_addr_a <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}}; + end + else begin + if (mem_rd_en_a) begin + rd_addr_a <= rd_addr_a + rd_loops_a; + end + rd_addr_a_wr <= rd_addr_a; + wr_addr_sync_rd2 <= wr_addr_b_rd; + wr_addr_sync_rd1 <= wr_addr_sync_rd2; + wr_addr_sync_rd <= wr_addr_sync_rd1; + end + end + +// write engine + always @ (posedge WRCLK_in or posedge INIT_MEM) begin + if (INIT_MEM == 1'b1) begin +// initialize memory + for (i=0;i WRITE_WIDTH_4) begin + for (wb=0;wb WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}}; + assign WRERR_out = wrerr_reg; + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR) + wrerr_reg <= 1'b0; + else if (WREN_int && (FULL_out || WRRSTBUSY_out)) + wrerr_reg <= 1'b1; + else + wrerr_reg <= 1'b0; + end + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + wr_addr_b <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}}; + o_stages_full_sync2 <= 1'b0; + o_stages_full_sync1 <= 1'b0; + o_stages_full_sync <= 1'b0; + rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}}; + end + else begin + if (mem_wr_en_b) begin + wr_addr_b <= wr_addr_b + wr_loops_b; + end + wr_addr_b_rd <= wr_addr_b; + o_stages_full_sync2 <= ~o_stages_empty; + o_stages_full_sync1 <= o_stages_full_sync2; + o_stages_full_sync <= o_stages_full_sync1; + rd_addr_sync_wr2 <= rd_addr_a_wr; + rd_addr_sync_wr1 <= rd_addr_sync_wr2; + rd_addr_sync_wr <= rd_addr_sync_wr1; + end + end + +// full flag + assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out)); + assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full; + assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0; + assign m_full = (output_stages == 0) ? 0 : ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b); + assign m_full_raw = output_stages*rd_loops_a; + assign n_empty = output_stages; + assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a; + + assign full_count_masked = full_count & wr_addr_b_mask; + assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b}; + assign next_full_count = {1'b1, next_rd_addr_wr} - {1'b0, next_wr_addr_rd}; + + assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i; +// ram_full independent clocks is one_from_full common clocks + assign ram_one_from_full_i = ((full_count < 2*wr_loops_b) && (full_count > 0)); + assign ram_two_from_full_i = ((full_count < 3*wr_loops_b) && (full_count > 0)); + assign ram_one_from_full = (next_full_count < wr_loops_b) && ~ram_full_c; + assign ram_two_from_full = (next_full_count < 2*wr_loops_b) && ~ram_full_c; +// when full common clocks, next read makes it not full +// assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c); + assign ram_one_read_from_not_full = (next_full_count >= wr_loops_b) && ram_full_c; + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + ram_full_c <= 1'b0; + end + else if (mem_wr_en_b && + (mem_rd_en_a && (rd_loops_a < wr_loops_b)) && + ram_one_from_full) begin + ram_full_c <= 1'b1; + end + else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin + ram_full_c <= 1'b1; + end + else if (mem_rd_en_a && ram_one_read_from_not_full) begin + ram_full_c <= 1'b0; + end + else begin + ram_full_c <= ram_full_c; + end + end + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + ram_full_i <= 1'b0; + end + else if (mem_wr_en_b && ram_two_from_full_i && ~ram_full_i) begin + ram_full_i <= 1'b1; + end + else if (~ram_one_from_full_i) begin + ram_full_i <= 1'b0; + end + else begin + ram_full_i <= ram_full_i; + end + end + + assign PROGFULL_out = prog_full_reg; + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + prog_full_reg <= 1'b0; + end + else begin + prog_full_reg <= prog_full; + end + end + +// empty flag + assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a}; + assign next_empty_count = {1'b1, next_wr_addr_rd} - {1'b0, next_rd_addr_wr}; + assign EMPTY_out = o_stages_empty; + assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i; + assign ram_one_read_from_empty_i = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty; + assign ram_one_read_from_empty = (next_empty_count < rd_loops_a) && ~ram_empty; + assign ram_one_write_from_not_empty = (next_empty_count >= rd_loops_a) && ram_empty; + assign ram_one_write_from_not_empty_i = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a); + assign prog_empty = ((empty_count < prog_empty_val) || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON && ram_empty)) && (~FULL_out || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT)); + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + ram_empty_c <= 1'b1; +// RD only makes empty + else if (~mem_wr_en_b && + mem_rd_en_a && + (ram_one_read_from_empty || ram_empty_c)) + ram_empty_c <= 1'b1; +// RD and WR when one read from empty and RD more than WR makes empty + else if (mem_wr_en_b && + (mem_rd_en_a && (rd_loops_a > wr_loops_b)) && + (ram_one_read_from_empty || ram_empty_c)) + ram_empty_c <= 1'b1; +// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR + else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c)) + ram_empty_c <= 1'b0; + else + ram_empty_c <= ram_empty_c; + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + ram_empty_i <= 1'b1; + else if (mem_rd_en_a && ram_one_read_from_empty_i) // RDEN_in ? + ram_empty_i <= 1'b1; + else if (empty_count < rd_loops_a) + ram_empty_i <= 1'b1; + else + ram_empty_i <= 1'b0; + end + +// assign PROGEMPTY_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? prog_empty_cc : prog_empty; + assign PROGEMPTY_out = prog_empty_cc; + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + prog_empty_cc <= 1'b1; + else + prog_empty_cc <= prog_empty; + end + +`ifdef XIL_TIMING + reg notifier; + wire rdclk_en_n; + wire rdclk_en_p; + wire wrclk_en_n; + wire wrclk_en_p; + assign rdclk_en_n = IS_RDCLK_INVERTED_BIN; + assign rdclk_en_p = ~IS_RDCLK_INVERTED_BIN; + assign wrclk_en_n = IS_WRCLK_INVERTED_BIN; + assign wrclk_en_p = ~IS_WRCLK_INVERTED_BIN; +`endif + + specify + (CASDIN *> CASDOUT) = (0:0:0, 0:0:0); + (CASDIN *> DOUT) = (0:0:0, 0:0:0); + (CASDINP *> CASDOUTP) = (0:0:0, 0:0:0); + (CASDINP *> DOUTP) = (0:0:0, 0:0:0); + (CASPRVEMPTY => CASPRVRDEN) = (0:0:0, 0:0:0); + (RDCLK *> CASDOUT) = (100:100:100, 100:100:100); + (RDCLK *> CASDOUTP) = (100:100:100, 100:100:100); + (RDCLK *> DOUT) = (100:100:100, 100:100:100); + (RDCLK *> DOUTP) = (100:100:100, 100:100:100); + (RDCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (RDCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (RDCLK => CASNXTEMPTY) = (100:100:100, 100:100:100); + (RDCLK => EMPTY) = (100:100:100, 100:100:100); + (RDCLK => PROGEMPTY) = (100:100:100, 100:100:100); + (RDCLK => RDERR) = (100:100:100, 100:100:100); + (RDCLK => RDRSTBUSY) = (100:100:100, 100:100:100); + (WRCLK *> CASDOUT) = (100:100:100, 100:100:100); + (WRCLK *> CASDOUTP) = (100:100:100, 100:100:100); + (WRCLK *> DOUT) = (100:100:100, 100:100:100); + (WRCLK *> DOUTP) = (100:100:100, 100:100:100); + (WRCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (WRCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (WRCLK => CASPRVRDEN) = (100:100:100, 100:100:100); + (WRCLK => FULL) = (100:100:100, 100:100:100); + (WRCLK => PROGFULL) = (100:100:100, 100:100:100); + (WRCLK => RDRSTBUSY) = (100:100:100, 100:100:100); + (WRCLK => WRERR) = (100:100:100, 100:100:100); + (WRCLK => WRRSTBUSY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay); + $setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay); + $setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay); + $setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay); + $setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay); + $setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay); + $setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay); + $setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay); + $setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay); + $setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay); + $setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay); + $setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay); + $setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay); + $setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay); + $setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay); + $setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay); + $setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay); + $setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay); + $setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay); + $setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay); + $setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay); + $setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay); + $setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay); + $setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay); + $setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay); + $setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay); + $setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay); + $setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay); + $setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay); + $setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay); + $setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay); + $setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay); + $setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay); + $setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay); + $setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay); + $setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay); + $setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay); + $setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay); + $setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay); + $setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay); + $setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay); + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay); + $setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay); + $setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay); + $setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay); + $setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay); + $setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay); + $setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay); + $setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay); + $setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay); + $setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay); + $setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay); + $setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay); + $setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay); + $setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay); + $setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay); + $setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay); + $setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay); + $setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay); + $setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay); + $setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay); + $setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay); + $setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay); + $setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay); + $setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay); + $setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay); + $setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay); + $setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay); + $setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FIFO36E1.v b/verilog/src/unisims/FIFO36E1.v new file mode 100644 index 0000000..6e9d5d7 --- /dev/null +++ b/verilog/src/unisims/FIFO36E1.v @@ -0,0 +1,3837 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36E1.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/18/08 - Initial version. +// 07/10/08 - IR476500 Add INIT parameter support +// 08/08/08 - Updated ECC to match hardware. (IR 479250) +// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware. +// 09/02/08 - Fixed ECC mismatch with hardware. (IR 479250) +// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 01/30/09 - Fixed eccparity when reset (IR 501358). +// 03/17/09 - Undo IR 501358 (CR 511331). +// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127). +// 04/29/09 - Fixed timing violation for asynchronous reset (CR 519016). +// 10/07/09 - Fixed reset behavior (CR 532794). +// 10/23/09 - Fixed RST and RSTREG (CR 537067). +// 11/17/09 - Fixed ECCPARITY behavior during RST (CR 537360). +// 12/02/09 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO36_72 (CR 539776). +// 06/30/10 - Updated RESET behavior and added SIM_DEVICE (CR 567515). +// 07/09/10 - Fixed INJECTSBITERR and INJECTDBITERR behaviors (CR 565234). +// 07/16/10 - Fixed RESET behavior during startup (CR 568626). +// 08/19/10 - Fixed RESET DRC during startup (CR 570708). +// 09/16/10 - Updated from bit to bus timing (CR 575523). +// 12/02/10 - Added warning message for 7SERIES Aysnc mode (CR 584052). +// 12/07/10 - Error out if no reset before first use of the fifo (CR 583638). +// 01/12/11 - updated warning message for 7SERIES Aysnc mode (CR 589721). +// 05/11/11 - Fixed DO not suppose to be reseted when RST asserted (CR 586526). +// 05/26/11 - Update Aysnc fifo behavior (CR 599680). +// 06/06/11 - Fixed RST in standard mode (CR 613216). +// 06/07/11 - Update DRC equation for ALMOST_FULL_OFFSET (CR 611057). +// 06/09/11 - Fixed GSR behavior (CR 611989). +// 06/13/11 - Added setup/hold timing check for RST (CR 606107). +// 07/07/11 - Fixed Full flag (CR 615773). +// 08/26/11 - Fixed FULL and ALMOSTFULL during initial time (CR 622163). +// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 03/08/12 - Added DRC to check WREN/RDEN after RST deassertion (CR 644571). +// 05/16/12 - Added support of negative setup/hold/recovery/removal timing (CR 639991). +// 11/05/12 - Fixed full flag in async mode with sync clocks (CR 677254). +// 01/15/13 - Fixed index out of bound warnings for parity (CR 694713). +// 07/18/13 - Added invertible pins support (CR 715417). +// 08/01/13 - Fixed async mode with sync clocks (CR 728728). +// 10/31/13 - Fixed flags in async mode with sync clocks (CR 718734, 724006). +// 03/25/14 - Balanced all iniputs with xor (CR778933). +// 05/16/14 - Fixed empty flag (CR 799323). +// 06/12/14 - Fixed almost_*_offset DRC (CR 799864). +// 07/24/14 - Fixed DRC message error (CR 798755). +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/13/14 - Fixed almost_full_offset DRC (CR 824363). +// 10/22/14 - Added #1 to $finish (CR 808642). +// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module FIFO36E1 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 72'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + + parameter SIM_DEVICE = "7SERIES"; + parameter SRVAL = 72'h0; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input INJECTDBITERR; + input INJECTSBITERR; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + + wire almostempty_wire, empty_wire, rderr_wire; + wire almostfull_wire, full_wire, wrerr_wire; + wire [12:0] wrcount_wire, rdcount_wire; + + reg notifier, notifier_wrclk, notifier_rdclk; + wire [63:0] do_wire; + wire [7:0] dop_wire; + reg finish_error = 0; + +`ifdef XIL_TIMING + wire [63:0] DI_dly; + wire [7:0] DIP_dly; + wire INJECTDBITERR_dly; + wire INJECTSBITERR_dly; + + wire RDCLK_dly; + wire RDEN_dly; + wire REGCE_dly; + wire RST_dly; + wire RSTREG_dly; + wire WRCLK_dly; + wire WREN_dly; +`endif + + wire [63:0] di_in; + wire [7:0] dip_in; + wire injectdbiterr_in; + wire injectsbiterr_in; + wire rdclk_in; + wire rden_in; + wire regce_in; + wire rst_in; + wire rstreg_in; + wire wrclk_in; + wire wren_in; + + reg IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED; + reg IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED; + reg IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED; + reg IS_RST_INVERTED_REG = IS_RST_INVERTED; + reg IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED; + reg IS_WREN_INVERTED_REG = IS_WREN_INVERTED; + +`ifdef XIL_TIMING + assign di_in = DI_dly; + assign dip_in = DIP_dly; + assign injectdbiterr_in = INJECTDBITERR_dly; + assign injectsbiterr_in = INJECTSBITERR_dly; + assign regce_in = REGCE_dly; + assign rdclk_in = RDCLK_dly ^ IS_RDCLK_INVERTED_REG; + assign rden_in = RDEN_dly ^ IS_RDEN_INVERTED_REG; + assign rstreg_in = RSTREG_dly ^ IS_RSTREG_INVERTED_REG; + assign rst_in = RST_dly ^ IS_RST_INVERTED_REG; + assign wrclk_in = WRCLK_dly ^ IS_WRCLK_INVERTED_REG; + assign wren_in = WREN_dly ^ IS_WREN_INVERTED_REG; +`else + assign di_in = DI; + assign dip_in = DIP; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign regce_in = REGCE; + assign rdclk_in = RDCLK ^ IS_RDCLK_INVERTED_REG; + assign rden_in = RDEN ^ IS_RDEN_INVERTED_REG; + assign rstreg_in = RSTREG ^ IS_RSTREG_INVERTED_REG; + assign rst_in = RST ^ IS_RST_INVERTED_REG; + assign wrclk_in = WRCLK ^ IS_WRCLK_INVERTED_REG; + assign wren_in = WREN ^ IS_WREN_INVERTED_REG; +`endif // `ifndef XIL_TIMING + + initial begin + + case (FIFO_MODE) + "FIFO36" : ; + "FIFO36_72" : if (DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when attribute FIFO_MODE = FIFO36_72."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are FIFO36 or FIFO36_72.", FIFO_MODE); + finish_error = 1; + end + + endcase // case(FIFO_MODE) + + + case (DATA_WIDTH) + + 4, 9, 18, 36 : ; + 72 : if (FIFO_MODE != "FIFO36_72") begin + $display("DRC Error : The attribute FIFO_MODE must be set to FIFO36_72 when attribute DATA_WIDTH = 72."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + + end + endcase + + + + if (!((IS_RDCLK_INVERTED >= 1'b0) && (IS_RDCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDCLK_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RDEN_INVERTED >= 1'b0) && (IS_RDEN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDEN_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RSTREG_INVERTED >= 1'b0) && (IS_RSTREG_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREG_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_RST_INVERTED >= 1'b0) && (IS_RST_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RST_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RST_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_WRCLK_INVERTED >= 1'b0) && (IS_WRCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WRCLK_INVERTED); + finish_error = 1'b1; + end + + if (!((IS_WREN_INVERTED >= 1'b0) && (IS_WREN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WREN_INVERTED); + finish_error = 1'b1; + end + + if (finish_error == 1) + #1 $finish; + + end // initial begin + + + // Matching HW + localparam init_sdp = (FIFO_MODE == "FIFO36_72") ? {INIT[71:68],INIT[35:32],INIT[67:36],INIT[31:0]} : INIT; + localparam srval_sdp = (FIFO_MODE == "FIFO36_72") ? {SRVAL[71:68],SRVAL[35:32],SRVAL[67:36],SRVAL[31:0]} : SRVAL; + + + FF36_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), + .DATA_WIDTH(DATA_WIDTH), + .DO_REG(DO_REG), + .EN_ECC_WRITE(EN_ECC_WRITE), + .EN_ECC_READ(EN_ECC_READ), + .EN_SYN(EN_SYN), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .FIFO_MODE(FIFO_MODE), + .INIT(init_sdp), + .SIM_DEVICE(SIM_DEVICE), + .SRVAL(srval_sdp)) + + INT_FIFO (.ALMOSTEMPTY(almostempty_wire), + .ALMOSTFULL(almostfull_wire), + .DBITERR(DBITERR), + .DI(di_in), + .DIP(dip_in), + .DO(do_wire), + .DOP(dop_wire), + .ECCPARITY(ECCPARITY), + .EMPTY(empty_wire), + .FULL(full_wire), + .GSR(GSR), + .INJECTDBITERR(injectdbiterr_in), + .INJECTSBITERR(injectsbiterr_in), + .RDCLK(rdclk_in), + .RDCOUNT(rdcount_wire), + .RDEN(rden_in), + .RDERR(rderr_wire), + .REGCE(regce_in), + .RST(rst_in), + .RSTREG(rstreg_in), + .SBITERR(SBITERR), + .WRCLK(wrclk_in), + .WRCOUNT(wrcount_wire), + .WREN(wren_in), + .WRERR(wrerr_wire)); + + + reg ALMOSTEMPTY_out; + reg ALMOSTFULL_out; + reg [63:0] DO_out; + reg [7:0] DOP_out; + reg EMPTY_out; + reg FULL_out; + reg [12:0] RDCOUNT_out; + reg RDERR_out; + reg [12:0] WRCOUNT_out; + reg WRERR_out; + + assign ALMOSTEMPTY = ALMOSTEMPTY_out; + assign ALMOSTFULL = ALMOSTFULL_out; + assign DO = DO_out; + assign DOP = DOP_out; + assign EMPTY = EMPTY_out; + assign FULL = FULL_out; + assign RDCOUNT = RDCOUNT_out; + assign RDERR = RDERR_out; + assign WRCOUNT = WRCOUNT_out; + assign WRERR = WRERR_out; + + //*** Timing Checks Start here + +//wrclk_in + always @(almostfull_wire or rst_in or GSR) ALMOSTFULL_out = almostfull_wire; + always @(full_wire or rst_in or GSR) FULL_out = full_wire; + always @(wrerr_wire or rst_in or GSR) WRERR_out = wrerr_wire; + always @(wrcount_wire or rst_in or GSR) WRCOUNT_out = wrcount_wire; + +//rdclk_in + always @(almostempty_wire or rst_in or GSR) ALMOSTEMPTY_out = almostempty_wire; + always @(empty_wire or rst_in or GSR) EMPTY_out = empty_wire; + always @(rderr_wire or rst_in or GSR) RDERR_out = rderr_wire; + always @(rdcount_wire or rst_in or GSR) RDCOUNT_out = rdcount_wire; + + always @(do_wire or rst_in or GSR) DO_out = do_wire; + always @(dop_wire or rst_in or GSR) DOP_out = dop_wire; + +`ifdef XIL_TIMING + + always @(notifier) begin + DO_out <= 64'bx; + DOP_out <= 8'bx; + end + + always @(notifier_wrclk) begin + ALMOSTFULL_out <= 1'bx; + FULL_out <= 1'bx; + WRCOUNT_out <= 13'bx; + WRERR_out <= 1'bx; + end + + always @(notifier_rdclk) begin + ALMOSTEMPTY_out <= 1'bx; + EMPTY_out <= 1'bx; + RDCOUNT_out <= 13'bx; + RDERR_out <= 1'bx; + end + + wire rdclk_en_n; + wire rdclk_en_p; + wire wrclk_en_n; + wire wrclk_en_p; + assign rdclk_en_n = IS_RDCLK_INVERTED_REG; + assign rdclk_en_p = ~IS_RDCLK_INVERTED_REG; + assign wrclk_en_n = IS_WRCLK_INVERTED_REG; + assign wrclk_en_p = ~IS_WRCLK_INVERTED_REG; + + wire nrst; + wire wren_enable; + not (nrst, RST); + and (wren_enable, WREN, nrst); + + wire rst_rdclk_n = nrst && rdclk_en_n; + wire rst_rdclk_p = nrst && rdclk_en_p; + wire rst_wrclk_n = nrst && wrclk_en_n; + wire rst_wrclk_p = nrst && wrclk_en_p; + wire wren_enable_p = wren_enable && wrclk_en_p; + wire wren_enable_n = wren_enable && wrclk_en_n; + +`endif // `ifdef XIL_TIMING + + specify + + (RDCLK *> DO) = (100:100:100, 100:100:100); + (RDCLK *> DOP) = (100:100:100, 100:100:100); + (RDCLK => DBITERR) = (100:100:100, 100:100:100); + (RDCLK => SBITERR) = (100:100:100, 100:100:100); + (RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100); + (RDCLK => EMPTY) = (100:100:100, 100:100:100); + (RDCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (RDCLK => RDERR) = (100:100:100, 100:100:100); + + (WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100); + (WRCLK => FULL) = (100:100:100, 100:100:100); + (WRCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (WRCLK => WRERR) = (100:100:100, 100:100:100); + (WRCLK *> ECCPARITY) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + (RST => ALMOSTEMPTY) = (0:0:0, 0:0:0); + (RST => ALMOSTFULL) = (0:0:0, 0:0:0); + (RST => EMPTY) = (0:0:0, 0:0:0); + (RST => FULL) = (0:0:0, 0:0:0); + (RST *> RDCOUNT) = (0:0:0, 0:0:0); + (RST => RDERR) = (0:0:0, 0:0:0); + (RST *> WRCOUNT) = (0:0:0, 0:0:0); + (RST => WRERR) = (0:0:0, 0:0:0); + + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly); + $setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly); + $setuphold (posedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly); + $setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly); + $setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly); + $setuphold (posedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly); + $setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly); + + $setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly); + $setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly); + $setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly); + $setuphold (negedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly); + $setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly); + $setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly); + $setuphold (negedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly); + $setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly); + + $setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly); + $setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly); + $setuphold (posedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly); + $setuphold (posedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly); + $setuphold (posedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly); + $setuphold (posedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly); + $setuphold (posedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, INJECTDBITERR_dly); + $setuphold (posedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, INJECTSBITERR_dly); + $setuphold (posedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, INJECTDBITERR_dly); + $setuphold (posedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, INJECTSBITERR_dly); + + $setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly); + $setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly); + $setuphold (negedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly); + $setuphold (negedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly); + $setuphold (negedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly); + $setuphold (negedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly); + $setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly); + $setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly); + $setuphold (negedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, INJECTDBITERR_dly); + $setuphold (negedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, INJECTSBITERR_dly); + $setuphold (negedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, INJECTDBITERR_dly); + $setuphold (negedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, INJECTSBITERR_dly); + + $recrem (negedge RST, posedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_p, rdclk_en_p, RST_dly, RDCLK_dly); + $recrem (negedge RST, posedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_p, wrclk_en_p, RST_dly, WRCLK_dly); + $recrem (negedge RST, negedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_n, rdclk_en_n, RST_dly, RDCLK_dly); + $recrem (negedge RST, negedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_n, wrclk_en_n, RST_dly, WRCLK_dly); + + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. FIFO36E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module FF36_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + output reg ALMOSTEMPTY; + output reg ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output reg EMPTY; + output reg FULL; + output reg [12:0] RDCOUNT; + output reg RDERR; + output SBITERR; + output reg [12:0] WRCOUNT; + output reg WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + input GSR; + input INJECTDBITERR; + input INJECTSBITERR; + + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter INIT = 72'h0; + parameter SIM_DEVICE = "7SERIES"; + parameter SRVAL = 72'h0; + + reg [63:0] do_in = 64'b0; + reg [63:0] do_out = 64'b0; + reg [63:0] do_outreg = 64'b0; + reg [63:0] do_out_mux = 64'b0; + reg [7:0] dop_in = 8'b0, dop_out = 8'b0; + reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0; + + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + reg [71:0] ecc_bit_position; + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, dop_buf = 8'b0, dip_ecc, dip_int; + reg [63:0] do_buf = 64'b0, di_in_ecc_corrected; + reg [7:0] syndrome, dip_in_ecc_corrected; + + wire full_v3; + + reg rden_reg, wren_reg; + reg fwft; + + integer addr_limit, rd_prefetch = 0; + integer wr1_addr = 0; + integer viol_rst_rden = 0, viol_rst_wren = 0; + + reg [3:0] rden_rdckreg = 4'b0, wren_wrckreg = 4'b0; + reg [12:0] rd_addr = 0; + reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0; + reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0; + reg wr1_flag = 0, awr_flag = 0; + reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111; + reg [3:0] full_int = 4'b0000; + reg [3:0] empty_ram = 4'b1111; + reg [8:0] i, j; + reg rst_tmp1 = 0, rst_tmp2 = 0; + reg [4:0] rst_rdckreg = 5'b0, rst_wrckreg = 5'b0; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + reg en_ecc_write_int, en_ecc_read_int, finish_error = 0; + reg [63:0] di_ecc_col; + reg first_rst_flag = 0; + reg rm1wp1_eq = 1'b0, rm1w_eq = 1'b0; + reg awr_flag_sync_1 = 0, awr_flag_sync_2 = 0; + integer after_rst_rdclk = 0, after_rst_wrclk = 0; + integer count_freq_rdclk = 0, count_freq_wrclk = 0; + integer roundup_int_period_rdclk_wrclk=0, roundup_int_period_wrclk_rdclk=0; + integer s7_roundup_int_period_rdclk_wrclk=0; + time rise_rdclk=0, period_rdclk=0, rise_wrclk=0, period_wrclk=0; + integer fwft_prefetch_flag = 1; + real real_period_rdclk=0.0, real_period_wrclk=0.0; + reg rst_trans_rden_1 = 1'b0, rst_trans_rden_2 = 1'b0; + reg rst_trans_wren_1 = 1'b0, rst_trans_wren_2 = 1'b0; + reg after_rst_rden_flag = 1'b0, after_rst_wren_flag = 1'b0, after_rst_x_flag = 1'b0; + time time_wrclk = 0, time_rdclk = 0; + time prev_time_wrclk = 0, prev_time_rdclk = 0; + reg sync_clk_async_mode = 1'b0; + reg sync_clk_async_mode_done = 1'b0; + reg count_freq_wrclk_reset = 0; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameter is changed. + parameter integer FIFO_SIZE = 36; +// xilinx_internal_parameter off + + + localparam counter_width = (FIFO_SIZE == 36) ? ((DATA_WIDTH == 4) ? 12 : + (DATA_WIDTH == 9) ? 11 : (DATA_WIDTH == 18) ? 10 : + (DATA_WIDTH == 36) ? 9 : (DATA_WIDTH == 72) ? 8 : 12) + : ((DATA_WIDTH == 4) ? 11 : (DATA_WIDTH == 9) ? 10 : + (DATA_WIDTH == 18) ? 9 : (DATA_WIDTH == 36) ? 8 : 11); + + reg [counter_width:0] rdcount_out = 13'b0, wr_addr = 13'b0; + reg [counter_width:0] ae_empty, ae_full; + reg [counter_width:0] rdcount_out_sync_3 = 13'h1fff, rdcount_out_sync_2 = 13'h1fff; + reg [counter_width:0] rdcount_out_sync_1 = 13'h1fff, rdcount_out_m1 = 13'h1fff; + reg [counter_width:0] wr_addr_sync_3 = 13'b0, wr_addr_sync_2 = 13'b0, wr_addr_sync_1 = 13'b0; + + + // Determinte memory size + localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0; + localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0; + localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0; + localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0; + localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0; + + + localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 : + (DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0; + + localparam memp_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 1 : + (DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0; + + reg [mem_width : 0] mem [mem_depth : 0]; + reg [memp_width : 0] memp [memp_depth : 0]; + reg sync; + + + // Input and output ports + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + + initial begin + ALMOSTEMPTY = 1'b1; + ALMOSTFULL = 1'b0; + EMPTY = 1'b1; + FULL = 1'b0; + RDCOUNT = 13'h0; + RDERR = 1'b0; + WRCOUNT = 13'h0; + WRERR = 1'b0; + end + + assign full_v3 = (rm1w_eq || (rm1wp1_eq && (WREN && !FULL))) ? 1 : 0; + + + initial begin + + // Determine address limit + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + end + endcase + + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + default : begin + $display("Attribute Syntax Error : The attribute EN_SYN on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN); + finish_error = 1; + end + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + finish_error = 1; + end + endcase + + + // DRC for fwft in sync mode + if (fwft == 1'b1 && EN_SYN == "TRUE") begin + $display("DRC Error : First word fall through is not supported in synchronous mode on FIFO36E1 instance %m."); + finish_error = 1; + end + + if (EN_SYN == "FALSE" && DO_REG == 0) begin + $display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FIFO36E1 instance %m."); + finish_error = 1; + end + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int <= 1; + "FALSE" : en_ecc_write_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int <= 1; + "FALSE" : en_ecc_read_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FIFO36E1 is configured in the ECC mode."); + finish_error = 1; + end + + + if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE); + finish_error = 1; + end + + + if (finish_error == 1) + #1 $finish; + + + end // initial begin + + + // GSR and RST + always @(GSR) + if (GSR === 1'b1) begin + if (DO_REG == 1'b1 && sync == 1'b1) begin + assign do_out = INIT[0 +: mem_width+1]; + assign dop_out = INIT[mem_width+1 +: memp_width+1]; + assign do_outreg = INIT[0 +: mem_width+1]; + assign dop_outreg = INIT[mem_width+1 +: memp_width+1]; + assign do_in = INIT[0 +: mem_width+1]; + assign dop_in = INIT[mem_width+1 +: memp_width+1]; + assign do_buf = INIT[0 +: mem_width+1]; + assign dop_buf = INIT[mem_width+1 +: memp_width+1]; + end + else begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + assign do_in = 64'b0; + assign dop_in = 8'b0; + assign do_buf = 64'b0; + assign dop_buf = 8'b0; + end + end + else if (GSR === 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + deassign do_in; + deassign dop_in; + deassign do_buf; + deassign dop_buf; + end + + + always @(RST) + if (RST === 1'b1) begin + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'b1; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'b0; + assign empty_ram = 4'b1111; + EMPTY = 1'b1; + assign full_int = 4'b0000; + FULL = 1'b0; + assign rdcount_out = 13'b0; + RDCOUNT = 13'b0; + WRCOUNT = 13'b0; + RDERR = 0; + WRERR = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'b1111111111111; + assign rdcount_out_m1 = 13'b1111111111111; + assign wr_addr_sync_3 = 13'b0; + end + else if (RST === 1'b0) begin + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; +// deassign EMPTY; + deassign full_int; +// deassign FULL; + deassign rdcount_out; +// deassign RDCOUNT; +// deassign WRCOUNT; +// deassign RDERR; +// deassign WRERR; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + end + + + // DRC + + generate + + case (SIM_DEVICE) + "VIRTEX6" : begin + + always @(posedge RDCLK) begin + + if (RST === 1'b1 && RDEN === 1'b1) + viol_rst_rden = 1; + + if (RST === 1'b0) + rden_rdckreg[3:0] <= {rden_rdckreg[2:0], RDEN}; + + if (rden_rdckreg == 4'h0) begin + rst_rdckreg[0] <= RST; + rst_rdckreg[1] <= rst_rdckreg[0] & RST; + rst_rdckreg[2] <= rst_rdckreg[1] & RST; + end + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK) begin + + if (RST === 1'b1 && WREN === 1'b1) + viol_rst_wren = 1; + + if (RST === 1'b0) + wren_wrckreg[3:0] <= {wren_wrckreg[2:0], WREN}; + + if (wren_wrckreg == 4'h0) begin + rst_wrckreg[0] <= RST; + rst_wrckreg[1] <= rst_wrckreg[0] & RST; + rst_wrckreg[2] <= rst_wrckreg[1] & RST; + end + + end // always @ (posedge WRCLK) + + + always @(RST) begin + + rst_tmp1 = RST; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + + if (((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.", $stime); + rst_rdclk_flag = 1; + #1 $finish; + end + + + if (((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle.", $stime); + + rst_wrclk_flag = 1; + #1 $finish; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end // if (RST == 1'b0) + + + viol_rst_rden = 0; + viol_rst_wren = 0; + rden_rdckreg = 4'h0; + wren_wrckreg = 4'h0; + + rst_rdckreg = 5'b0; + rst_wrckreg = 5'b0; + + + if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0) + first_rst_flag = 1; + + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + + rst_tmp2 = rst_tmp1; + + end // always @ (RST) + + end // case: "VIRTEX6" + "7SERIES" : begin + + always @(posedge RST) + rst_trans_rden_1 = RST; + + always @(negedge RST) + if (rst_trans_rden_1 == 1'b1) + rst_trans_rden_2 = ~RST; + + + always @(posedge RDCLK) begin + + if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) begin + + after_rst_rdclk = after_rst_rdclk + 1; + + if (RDEN === 1'b1 && after_rst_rdclk <= 2) begin + + after_rst_rden_flag = 1'b1; + + end + else if (after_rst_rdclk >= 3) begin + after_rst_rdclk = 0; + rst_trans_rden_1 = 1'b0; + rst_trans_rden_2 = 1'b0; + + if (after_rst_rden_flag == 1'b1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RDEN must be low for at least two RDCLK clock cycles after RST deasserted.", $stime); + after_rst_rden_flag = 1'b0; + after_rst_x_flag = 1'b1; + #1 $finish; + + end + end + end // if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) + end // always @ (posedge RDCLK) + + + always @(posedge RST) + rst_trans_wren_1 = RST; + + always @(negedge RST) + if (rst_trans_wren_1 == 1'b1) + rst_trans_wren_2 = ~RST; + + + always @(posedge WRCLK) begin + + if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) begin + + after_rst_wrclk = after_rst_wrclk + 1; + + if (WREN === 1'b1 && after_rst_wrclk <= 2) begin + + after_rst_wren_flag = 1'b1; + + end + else if (after_rst_wrclk >= 3) begin + + after_rst_wrclk = 0; + rst_trans_wren_1 = 1'b0; + rst_trans_wren_2 = 1'b0; + + + if (after_rst_wren_flag == 1'b1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. WREN must be low for at least two WRCLK clock cycles after RST deasserted.", $stime); + after_rst_wren_flag = 1'b0; + after_rst_x_flag = 1'b1; + #1 $finish; + + end + end + end // if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) + end // always @ (posedge WRCLK) + + + always @(posedge after_rst_x_flag or negedge RST) begin + + if (after_rst_x_flag == 1'b1) begin + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'bx; + assign rdcount_out_m1 = 13'bx; + assign wr_addr_sync_3 = 13'bx; + after_rst_x_flag = 1'b0; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; + deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + + end // if (RST == 1'b0) + + end // always @ (posedge after_rst_x_flag or negedge RST) + + + always @(posedge RDCLK) begin + + if (RST === 1'b1 && RDEN === 1'b1) + viol_rst_rden = 1; + + if (RDEN === 1'b0 && RST === 1'b1) begin + rst_rdckreg[0] <= RST; + rst_rdckreg[1] <= rst_rdckreg[0] & RST; + rst_rdckreg[2] <= rst_rdckreg[1] & RST; + rst_rdckreg[3] <= rst_rdckreg[2] & RST; + rst_rdckreg[4] <= rst_rdckreg[3] & RST; + end + else if (RDEN === 1'b1 && RST === 1'b1) begin + rst_rdckreg <= 5'b0; + end + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK) begin + + if (RST === 1'b1 && WREN === 1'b1) + viol_rst_wren = 1; + + if (WREN === 1'b0 && RST === 1'b1) begin + rst_wrckreg[0] <= RST; + rst_wrckreg[1] <= rst_wrckreg[0] & RST; + rst_wrckreg[2] <= rst_wrckreg[1] & RST; + rst_wrckreg[3] <= rst_wrckreg[2] & RST; + rst_wrckreg[4] <= rst_wrckreg[3] & RST; + end + else if (WREN === 1'b1 && RST === 1'b1) begin + rst_wrckreg <= 5'b0; + end + + end // always @ (posedge WRCLK) + + + always @(RST) begin + + rst_tmp1 = RST; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if (((rst_rdckreg[4] & rst_rdckreg[3] & rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five RDCLK clock cycles, and RDEN must be low before RST becomes active high, and RDEN remains low during this reset cycle.", $stime); + rst_rdclk_flag = 1; + #1 $finish; + + end + + if (((rst_wrckreg[4] & rst_wrckreg[3] & rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin + + $display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.", $stime); + + rst_wrclk_flag = 1; + #1 $finish; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + FULL = 1'bX; + EMPTY = 1'bX; + RDERR = 1'bX; + WRERR = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + RDCOUNT = 13'bx; + WRCOUNT = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + ALMOSTEMPTY = 1'bx; + assign almostfull_int = 4'b0000; + ALMOSTFULL = 1'bx; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + assign rdcount_out_sync_3 = 13'bx; + assign rdcount_out_m1 = 13'bx; + assign wr_addr_sync_3 = 13'bx; + end + else if (RST == 1'b0) begin +// deassign FULL; +// deassign EMPTY; +// deassign RDERR; +// deassign WRERR; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; +// deassign RDCOUNT; +// deassign WRCOUNT; + deassign wr1_addr; + deassign almostempty_int; +// deassign ALMOSTEMPTY; + deassign almostfull_int; +// deassign ALMOSTFULL; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + deassign rdcount_out_sync_3; + deassign rdcount_out_m1; + deassign wr_addr_sync_3; + end // if (RST == 1'b0) + + + viol_rst_rden = 0; + viol_rst_wren = 0; + rst_rdckreg = 5'b0; + rst_wrckreg = 5'b0; + + if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0) + first_rst_flag = 1; + + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + rst_tmp2 = rst_tmp1; + + end // always @ (RST) + + end // case: "7SERIES" + + endcase // case(SIM_DEVICE) + + endgenerate + + + // DRC + always @(posedge RDEN or negedge GSR) + @(posedge RDCLK) + if (first_rst_flag == 0 && RDEN == 1'b1 && GSR == 1'b0) begin + $display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time); + #1 $finish; + end + + + always @(posedge WREN or negedge GSR) + @(posedge WRCLK) + if (first_rst_flag == 0 && WREN == 1'b1 && GSR == 1'b0) begin + $display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time); + #1 $finish; + end + + + always @(posedge RDCLK) begin + + if (((period_rdclk == 0) && (count_freq_rdclk < 152)) || + ((count_freq_rdclk == 0) && (GSR == 1 || RST == 1)) || + ((count_freq_rdclk > 0) && (count_freq_rdclk < 152))) begin + count_freq_rdclk = count_freq_rdclk + 1; + end else if (count_freq_wrclk == 152) begin + count_freq_rdclk = 0; + count_freq_wrclk_reset = 1; + end + + if (count_freq_rdclk == 150) + rise_rdclk = $time; + else if (count_freq_rdclk == 151) + period_rdclk = $time - rise_rdclk; + + if (count_freq_rdclk >= 151 && count_freq_wrclk >= 151 && RST === 1'b0 && GSR === 1'b0) begin + + // Setup ranges for almostempty + if (period_rdclk == period_wrclk) begin + + if (EN_SYN == "FALSE") begin + + if (SIM_DEVICE == "7SERIES") begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 6)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 6); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7); + finish_error = 1; + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + + end // if (SIM_DEVICE == "7SERIES") + else begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + end // else: !if(SIM_DEVICE == "7SERIES") + end // if (EN_SYN == "FALSE") + else begin + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + end // else: !if(EN_SYN == "FALSE") + + end // if (period_rdclk == period_wrclk) + else begin + + real_period_rdclk = period_rdclk * 1.0; + real_period_wrclk = period_wrclk * 1.0; + + roundup_int_period_rdclk_wrclk = (real_period_rdclk / real_period_wrclk) + 0.499; + roundup_int_period_wrclk_rdclk = (real_period_wrclk / real_period_rdclk) + 0.499; + + s7_roundup_int_period_rdclk_wrclk = (4.0 * (real_period_rdclk / real_period_wrclk)) + 0.499; + + + if (SIM_DEVICE == "7SERIES") begin + +// $display ("addr_limit (%h) period_rdclk (%d) period_wrclk (%d) real_period_rdclk (%f) real_period_wrclk (%f) roundup_int_period_rdclk_wrclk (%d) roundup_int_period_wrclk_rdclk (%d) s7_roundup_int_period_rdclk_wrclk (%d) instance %m\n",addr_limit,period_rdclk,period_wrclk,real_period_rdclk,real_period_wrclk,roundup_int_period_rdclk_wrclk,roundup_int_period_wrclk_rdclk,s7_roundup_int_period_rdclk_wrclk); + if (ALMOST_FULL_OFFSET > (addr_limit - (s7_roundup_int_period_rdclk_wrclk + 6))) begin + + $display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((roundup(4 * (WRCLK frequency / RDCLK frequency))) + 6)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET); + finish_error = 1; + + end + end + else begin + + if (ALMOST_FULL_OFFSET > (addr_limit - ((3 * roundup_int_period_wrclk_rdclk) + 3))) begin + + $display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (RDCLK frequency / WRCLK frequency)) + 3)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET); + finish_error = 1; + + end + + if (ALMOST_EMPTY_OFFSET > (addr_limit - ((3 * roundup_int_period_rdclk_wrclk) + 3))) begin + + $display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (WRCLK frequency / RDCLK frequency)) + 3)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_EMPTY_OFFSET); + finish_error = 1; + + end + + end // else: !if(SIM_DEVICE == "7SERIES") + + end // else: !if(period_rdclk == period_wrclk) + + count_freq_rdclk = 0; + count_freq_wrclk_reset = 1; + + if (finish_error == 1) + #100 $finish; + + end // if (count_freq_wrclk >= 151 && count_freq_rdclk >= 151 && RST === 1'b0 && GSR === 1'b0) + + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK or posedge count_freq_wrclk_reset) begin + + if (count_freq_wrclk_reset == 1) begin + count_freq_wrclk = 0; + count_freq_wrclk_reset = 0; + end else if (((period_wrclk == 0) && (count_freq_wrclk < 152)) || + ((count_freq_wrclk == 0) && (GSR == 1 || RST == 1)) || + ((count_freq_wrclk > 0) && (count_freq_wrclk < 152))) + count_freq_wrclk = count_freq_wrclk + 1; + + + if (count_freq_wrclk == 150) + rise_wrclk = $time; + else if (count_freq_wrclk == 151) begin + period_wrclk = $time - rise_wrclk; + end + + end // always @ (posedge WRCLK) + + + + generate + case (SIM_DEVICE) + + "VIRTEX6" : begin + + // read clock + always @(posedge RDCLK) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (RDEN == 1'b1) begin + + if (EMPTY == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end // if (EMPTY == 1'b0) + end // if (RDEN == 1'b1) + + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + if (WREN == 1'b1) begin + EMPTY = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + EMPTY = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + ALMOSTEMPTY = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + ALMOSTFULL = 1'b0; + end + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rden_reg = RDEN; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1); + + ALMOSTEMPTY = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + + end // always @ (posedge RDCLK) + + + // Write clock + always @(posedge WRCLK) begin + + // DRC + if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m."); + + if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (WREN == 1'b1) begin + + if (FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (RST === 1'b0) begin + + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end // if (FULL == 1'b0) + end // if (WREN == 1'b1) + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + + if (RDEN == 1'b1) begin + FULL = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + FULL = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + ALMOSTEMPTY = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + ALMOSTFULL = 1'b1; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + wren_reg = WREN; + + if (wren_reg == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (wren_reg == 1'b1 && FULL == 1'b0) + + + if (RST === 1'b0) begin + + WRERR = (wren_reg == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || FULL == 1'b1) + FULL = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b0) + + end // always @ (posedge WRCLK) + + +end // case: "VIRTEX6" +"7SERIES" : begin + + always @(posedge RDCLK) begin + if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin + prev_time_rdclk = time_rdclk; + time_rdclk = $time; + end + end + + always @(posedge WRCLK) begin + if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin + prev_time_wrclk = time_wrclk; + time_wrclk = $time; + end + end + + always @(time_rdclk or time_wrclk) begin + if (((time_rdclk - time_wrclk == 0 && prev_time_rdclk - prev_time_wrclk == 0) || (time_wrclk - time_rdclk == 0 && prev_time_wrclk - prev_time_rdclk == 0)) && $time != 0) + sync_clk_async_mode = 1'b1; + if ((((period_wrclk > 0) && (period_rdclk > 0)) || (sync_clk_async_mode == 1'b1)) && (RST == 1'b0) && (GSR == 1'b0)) + sync_clk_async_mode_done = 1'b1; + end + + + // read clock + always @(posedge RDCLK) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (RDEN == 1'b1) begin + + if (EMPTY == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end // if (EMPTY == 1'b0) + end // if (RDEN == 1'b1) + + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + if (WREN == 1'b1) begin + EMPTY = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + EMPTY = 1'b1; + + if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + ALMOSTEMPTY = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + ALMOSTFULL = 1'b0; + end + + + end // if (sync == 1'b1) + + + // async mode + else if (sync == 1'b0) begin + + wr_addr_sync_3 = wr_addr_sync_2; + wr_addr_sync_2 = wr_addr_sync_1; + wr_addr_sync_1 = wr_addr; + + awr_flag_sync_2 = awr_flag_sync_1; + awr_flag_sync_1 = awr_flag; + + + if (sync_clk_async_mode == 1'b1) begin + + rden_reg = RDEN; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1); + + ALMOSTEMPTY = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[1] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + + end // if (sync_clk_async_mode == 1'b1) + else begin + + if (fwft == 1'b0) begin + if (RDEN == 1'b1 && (rd_addr != rdcount_out)) begin + + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + + + if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #0; + rdcount_out_m1 = rdcount_out; + + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((RDEN == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + + if ((rd_prefetch == rd_addr && rd_addr != rdcount_out) || (RST === 1'b1 && fwft_prefetch_flag == 1)) begin + + fwft_prefetch_flag = 0; + + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + + if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + #1 $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #0; + rdcount_out_m1 = rdcount_out; + + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1); + + + ALMOSTEMPTY = almostempty_int[0]; + + if (wr_addr_sync_3 - rdcount_out <= ae_empty) + almostempty_int[0] = 1'b1; + else + almostempty_int[0] = 1'b0; + + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + EMPTY = 1'b1; + end + else begin + EMPTY = 1'b0; + end + end + + + if ((rdcount_out == wr_addr_sync_2) && (rdcount_flag == awr_flag_sync_2)) begin + empty_ram[0] = 1'b1; + end + else begin + empty_ram[0] = 1'b0; + end + + + end // else: !if(sync_clk_async_mode == 1'b1) + + end // if (sync == 1'b0) + + + end // always @ (posedge RDCLK) + + + // Write clock + always @(posedge WRCLK) begin + + // DRC + if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m."); + + if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (WREN == 1'b1) begin + + if (FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (RST === 1'b0) begin + + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end // if (FULL == 1'b0) + end // if (WREN == 1'b1) + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + + if (RDEN == 1'b1) begin + FULL = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + FULL = 1'b1; + + if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + ALMOSTEMPTY = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + ALMOSTFULL = 1'b1; + end + + end // if (RST === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rdcount_out_sync_3 = rdcount_out_sync_2; + rdcount_out_sync_2 = rdcount_out_sync_1; + rdcount_out_sync_1 = rdcount_out_m1; + + + if (sync_clk_async_mode == 1'b1) begin + + wren_reg = WREN; + + if (wren_reg == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (wren_reg == 1'b1 && FULL == 1'b0) + + + if (RST === 1'b0) begin + + WRERR = (wren_reg == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full + 1)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full + 1)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || FULL == 1'b1) + FULL = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + // fix for 724006 + if (rdcount_out - 1 == wr_addr && (wren_reg == 1'b1 || FULL == 1'b1)) + FULL = full_int[1]; + + + end // if (RST === 1'b0) + + + end // if (sync_clk_async_mode == 1'b1) + + else begin + + + if (WREN == 1'b1 && FULL == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8] + ^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19] + ^DI[21]^DI[23]^DI[25]^DI[26]^DI[28] + ^DI[30]^DI[32]^DI[34]^DI[36]^DI[38] + ^DI[40]^DI[42]^DI[44]^DI[46]^DI[48] + ^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59] + ^DI[61]^DI[63]; + + dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9] + ^DI[10]^DI[12]^DI[13]^DI[16]^DI[17] + ^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28] + ^DI[31]^DI[32]^DI[35]^DI[36]^DI[39] + ^DI[40]^DI[43]^DI[44]^DI[47]^DI[48] + ^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59] + ^DI[62]^DI[63]; + + dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[14]^DI[15]^DI[16]^DI[17] + ^DI[22]^DI[23]^DI[24]^DI[25]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[45]^DI[46]^DI[47]^DI[48] + ^DI[53]^DI[54]^DI[55]^DI[56] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25] + ^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + + dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]; + + dip_ecc[6] = DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9] + ^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19] + ^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29] + ^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39] + ^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49] + ^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59] + ^DI[60]^DI[61]^DI[62]^DI[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = DIP; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (RST === 1'b0) begin + + // injecting error + di_ecc_col = DI; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (INJECTDBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (INJECTSBITERR === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #0; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (RST === 1'b0) + + end // if (WREN == 1'b1 && FULL == 1'b0) + + + rm1w_eq = (rdcount_out_sync_2 == wr_addr) ? 1 : 0; + + if (wr_addr + 1 == addr_limit) // wr_addr(FF) + 1 != 0 + rm1wp1_eq = (rdcount_out_sync_2 == 0) ? 1 : 0; + else + rm1wp1_eq = (rdcount_out_sync_2 == wr_addr + 1) ? 1 : 0; + + + if (RST === 1'b0) begin + + WRERR = (WREN == 1'b1) && (FULL == 1'b1); + + ALMOSTFULL = almostfull_int[0]; + + if (rdcount_out_sync_3 - wr_addr <= ae_full) + almostfull_int[0] = 1'b1; + else + almostfull_int[0] = 1'b0; + + + FULL = full_v3; + + + //fwft prefetch + if (EMPTY == 1'b1 && WREN === 1'b1 && fwft_prefetch_flag == 0) + fwft_prefetch_flag = 1; + + + end // if (RST === 1'b0) + + end // else: !if(sync_clk_async_mode == 1'b1) + + end // if (sync == 1'b0) + + end // always @ (posedge WRCLK) + +end // case: "7SERIES" + + +endcase // case(SIM_DEVICE) +endgenerate + + + // output register + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + default : begin + $display("Attribute Syntax Error : The attribute DO_REG on FIFO36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG); + #1 $finish; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + // matching HW behavior to X the unused output bits + assign DO = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]} + : (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]} + : (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]} + : (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]} + : (DATA_WIDTH == 72) ? do_out_mux + : do_out_mux; + + // matching HW behavior to X the unused output bits + assign DOP = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]} + : (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]} + : (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]} + : (DATA_WIDTH == 72) ? dop_out_mux + : 8'bx; + + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : WRCOUNT = {1'b1, wr_addr[counter_width:0]}; + 9 : WRCOUNT = {2'b11, wr_addr[counter_width:0]}; + 18 : WRCOUNT = {3'b111, wr_addr[counter_width:0]}; + 36 : WRCOUNT = {4'hf, wr_addr[counter_width:0]}; + default : WRCOUNT = wr_addr; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : WRCOUNT = wr_addr; + 9 : WRCOUNT = {1'b1, wr_addr[counter_width:0]}; + 18 : WRCOUNT = {2'b11, wr_addr[counter_width:0]}; + 36 : WRCOUNT = {3'b111, wr_addr[counter_width:0]}; + 72 : WRCOUNT = {4'hf, wr_addr[counter_width:0]}; + default : WRCOUNT = wr_addr; + endcase // case(DATA_WIDTH) + + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]}; + 9 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]}; + 18 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]}; + 36 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]}; + default : RDCOUNT = rdcount_out; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : RDCOUNT = rdcount_out; + 9 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]}; + 18 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]}; + 36 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]}; + 72 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]}; + default : RDCOUNT = rdcount_out; + endcase // case(DATA_WIDTH) + + end // always @ (rdcount_out) + + +endmodule + +`endcelldefine + +// end of FF36_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/src/unisims/FIFO36E2.v b/verilog/src/unisims/FIFO36E2.v new file mode 100644 index 0000000..ca9b16d --- /dev/null +++ b/verilog/src/unisims/FIFO36E2.v @@ -0,0 +1,2237 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 36Kb FIFO (First-In-First-Out) Block RAM Memory +// /___/ /\ Filename : FIFO36E2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 11/30/2012 - intial +// 12/12/2012 - yaml update, 691724 and 691715 +// 02/07/2013 - 699628 - correction to DO_PIPELINED mode +// 02/28/2013 - update to keep in sync with RAMB models +// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC. +// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY +// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there. +// 03/25/2013 - 707719 - Add sync5 cascade feature +// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module FIFO36E2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE_ORDER = "NONE", + parameter CLOCK_DOMAINS = "INDEPENDENT", + parameter EN_ECC_PIPE = "FALSE", + parameter EN_ECC_READ = "FALSE", + parameter EN_ECC_WRITE = "FALSE", + parameter FIRST_WORD_FALL_THROUGH = "FALSE", + parameter [71:0] INIT = 72'h000000000000000000, + parameter [0:0] IS_RDCLK_INVERTED = 1'b0, + parameter [0:0] IS_RDEN_INVERTED = 1'b0, + parameter [0:0] IS_RSTREG_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter [0:0] IS_WRCLK_INVERTED = 1'b0, + parameter [0:0] IS_WREN_INVERTED = 1'b0, + parameter integer PROG_EMPTY_THRESH = 256, + parameter integer PROG_FULL_THRESH = 256, + parameter RDCOUNT_TYPE = "RAW_PNTR", + parameter integer READ_WIDTH = 4, + parameter REGISTER_MODE = "UNREGISTERED", + parameter RSTREG_PRIORITY = "RSTREG", + parameter SLEEP_ASYNC = "FALSE", + parameter [71:0] SRVAL = 72'h000000000000000000, + parameter WRCOUNT_TYPE = "RAW_PNTR", + parameter integer WRITE_WIDTH = 4 +)( + output [63:0] CASDOUT, + output [7:0] CASDOUTP, + output CASNXTEMPTY, + output CASPRVRDEN, + output DBITERR, + output [63:0] DOUT, + output [7:0] DOUTP, + output [7:0] ECCPARITY, + output EMPTY, + output FULL, + output PROGEMPTY, + output PROGFULL, + output [13:0] RDCOUNT, + output RDERR, + output RDRSTBUSY, + output SBITERR, + output [13:0] WRCOUNT, + output WRERR, + output WRRSTBUSY, + + input [63:0] CASDIN, + input [7:0] CASDINP, + input CASDOMUX, + input CASDOMUXEN, + input CASNXTRDEN, + input CASOREGIMUX, + input CASOREGIMUXEN, + input CASPRVEMPTY, + input [63:0] DIN, + input [7:0] DINP, + input INJECTDBITERR, + input INJECTSBITERR, + input RDCLK, + input RDEN, + input REGCE, + input RST, + input RSTREG, + input SLEEP, + input WRCLK, + input WREN +); + +// define constants + localparam MODULE_NAME = "FIFO36E2"; + +// Parameter encodings and registers + localparam CASCADE_ORDER_FIRST = 1; + localparam CASCADE_ORDER_LAST = 2; + localparam CASCADE_ORDER_MIDDLE = 3; + localparam CASCADE_ORDER_NONE = 0; + localparam CASCADE_ORDER_PARALLEL = 4; + localparam CLOCK_DOMAINS_COMMON = 1; + localparam CLOCK_DOMAINS_INDEPENDENT = 0; + localparam EN_ECC_PIPE_FALSE = 0; + localparam EN_ECC_PIPE_TRUE = 1; + localparam EN_ECC_READ_FALSE = 0; + localparam EN_ECC_READ_TRUE = 1; + localparam EN_ECC_WRITE_FALSE = 0; + localparam EN_ECC_WRITE_TRUE = 1; + localparam FIRST_WORD_FALL_THROUGH_FALSE = 0; + localparam FIRST_WORD_FALL_THROUGH_TRUE = 1; + localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1; + localparam RDCOUNT_TYPE_RAW_PNTR = 0; + localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2; + localparam RDCOUNT_TYPE_SYNC_PNTR = 3; + localparam READ_WIDTH_18 = 16; + localparam READ_WIDTH_36 = 32; + localparam READ_WIDTH_4 = 4; + localparam READ_WIDTH_72 = 64; + localparam READ_WIDTH_9 = 8; + localparam REGISTER_MODE_DO_PIPELINED = 1; + localparam REGISTER_MODE_REGISTERED = 2; + localparam REGISTER_MODE_UNREGISTERED = 0; + localparam RSTREG_PRIORITY_REGCE = 1; + localparam RSTREG_PRIORITY_RSTREG = 0; + localparam SLEEP_ASYNC_FALSE = 0; + localparam SLEEP_ASYNC_TRUE = 1; + localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1; + localparam WRCOUNT_TYPE_RAW_PNTR = 0; + localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2; + localparam WRCOUNT_TYPE_SYNC_PNTR = 3; + localparam WRITE_WIDTH_18 = 16; + localparam WRITE_WIDTH_36 = 32; + localparam WRITE_WIDTH_4 = 4; + localparam WRITE_WIDTH_72 = 64; + localparam WRITE_WIDTH_9 = 8; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "FIFO36E2_dr.v" +`else + localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER; + localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS; + localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE; + localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ; + localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE; + localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH; + localparam [71:0] INIT_REG = INIT; + localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED; + localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED; + localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED; + localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED; + localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH; + localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH; + localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE; + localparam [6:0] READ_WIDTH_REG = READ_WIDTH; + localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE; + localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY; + localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC; + localparam [71:0] SRVAL_REG = SRVAL; + localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE; + localparam [6:0] WRITE_WIDTH_REG = WRITE_WIDTH; +`endif + + wire [2:0] CASCADE_ORDER_BIN; + wire CLOCK_DOMAINS_BIN; + wire EN_ECC_PIPE_BIN; + wire EN_ECC_READ_BIN; + wire EN_ECC_WRITE_BIN; + wire FIRST_WORD_FALL_THROUGH_BIN; + wire [71:0] INIT_BIN; + wire IS_RDCLK_INVERTED_BIN; + wire IS_RDEN_INVERTED_BIN; + wire IS_RSTREG_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire IS_WRCLK_INVERTED_BIN; + wire IS_WREN_INVERTED_BIN; + wire [12:0] PROG_EMPTY_THRESH_BIN; + wire [12:0] PROG_FULL_THRESH_BIN; + wire [1:0] RDCOUNT_TYPE_BIN; + wire [6:0] READ_WIDTH_BIN; + wire [1:0] REGISTER_MODE_BIN; + wire RSTREG_PRIORITY_BIN; + wire SLEEP_ASYNC_BIN; + wire [71:0] SRVAL_BIN; + wire [1:0] WRCOUNT_TYPE_BIN; + wire [6:0] WRITE_WIDTH_BIN; + reg INIT_MEM = 0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR || INIT_MEM; + + wire CASNXTEMPTY_out; + wire CASPRVRDEN_out; + wire DBITERR_out; + wire EMPTY_out; + wire FULL_out; + wire PROGEMPTY_out; + wire PROGFULL_out; + wire RDERR_out; + wire RDRSTBUSY_out; + wire SBITERR_out; + wire WRERR_out; + wire WRRSTBUSY_out; + wire [13:0] RDCOUNT_out; + wire [13:0] WRCOUNT_out; + wire [63:0] CASDOUT_out; + reg [63:0] DOUT_out; + wire [7:0] CASDOUTP_out; + reg [7:0] DOUTP_out; + wire [7:0] ECCPARITY_out; + + wire CASDOMUXEN_in; + wire CASDOMUX_in; + wire CASNXTRDEN_in; + wire CASOREGIMUXEN_in; + wire CASOREGIMUX_in; + wire CASPRVEMPTY_in; + wire INJECTDBITERR_in; + wire INJECTSBITERR_in; + wire RDCLK_in; + wire RDEN_in; + wire REGCE_in; + wire RSTREG_in; + wire RST_in; + wire RST_in_pulse; + + wire SLEEP_in; + wire WRCLK_in; + wire WREN_in; + wire [63:0] CASDIN_in; + reg [63:0] DIN_in; + wire [7:0] CASDINP_in; + reg [7:0] DINP_in; + +`ifdef XIL_TIMING + wire CASDOMUXEN_delay; + wire CASDOMUX_delay; + wire CASNXTRDEN_delay; + wire CASOREGIMUXEN_delay; + wire CASOREGIMUX_delay; + wire CASPRVEMPTY_delay; + wire INJECTDBITERR_delay; + wire INJECTSBITERR_delay; + wire RDCLK_delay; + wire RDEN_delay; + wire REGCE_delay; + wire RSTREG_delay; + wire RST_delay; + wire SLEEP_delay; + wire WRCLK_delay; + wire WREN_delay; + wire [63:0] CASDIN_delay; + wire [63:0] DIN_delay; + wire [7:0] CASDINP_delay; + wire [7:0] DINP_delay; +`endif + + assign CASDOUT = CASDOUT_out; + assign CASDOUTP = CASDOUTP_out; + assign CASNXTEMPTY = CASNXTEMPTY_out; + assign CASPRVRDEN = CASPRVRDEN_out; + assign DBITERR = DBITERR_out; + assign DOUT = DOUT_out; + assign DOUTP = DOUTP_out; + assign ECCPARITY = ECCPARITY_out; + assign EMPTY = EMPTY_out; + assign FULL = FULL_out; + assign PROGEMPTY = PROGEMPTY_out; + assign PROGFULL = PROGFULL_out; + assign RDCOUNT = RDCOUNT_out; + assign RDERR = RDERR_out; + assign RDRSTBUSY = RDRSTBUSY_out; + assign SBITERR = SBITERR_out; + assign WRCOUNT = WRCOUNT_out; + assign WRERR = WRERR_out; + assign WRRSTBUSY = WRRSTBUSY_out; + +`ifdef XIL_TIMING + assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP_delay[0]; // rv 0 + assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP_delay[1]; // rv 0 + assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP_delay[2]; // rv 0 + assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP_delay[3]; // rv 0 + assign CASDINP_in[4] = (CASDINP[4] !== 1'bz) && CASDINP_delay[4]; // rv 0 + assign CASDINP_in[5] = (CASDINP[5] !== 1'bz) && CASDINP_delay[5]; // rv 0 + assign CASDINP_in[6] = (CASDINP[6] !== 1'bz) && CASDINP_delay[6]; // rv 0 + assign CASDINP_in[7] = (CASDINP[7] !== 1'bz) && CASDINP_delay[7]; // rv 0 + assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN_delay[0]; // rv 0 + assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN_delay[10]; // rv 0 + assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN_delay[11]; // rv 0 + assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN_delay[12]; // rv 0 + assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN_delay[13]; // rv 0 + assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN_delay[14]; // rv 0 + assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN_delay[15]; // rv 0 + assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN_delay[16]; // rv 0 + assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN_delay[17]; // rv 0 + assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN_delay[18]; // rv 0 + assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN_delay[19]; // rv 0 + assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN_delay[1]; // rv 0 + assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN_delay[20]; // rv 0 + assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN_delay[21]; // rv 0 + assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN_delay[22]; // rv 0 + assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN_delay[23]; // rv 0 + assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN_delay[24]; // rv 0 + assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN_delay[25]; // rv 0 + assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN_delay[26]; // rv 0 + assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN_delay[27]; // rv 0 + assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN_delay[28]; // rv 0 + assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN_delay[29]; // rv 0 + assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN_delay[2]; // rv 0 + assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN_delay[30]; // rv 0 + assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN_delay[31]; // rv 0 + assign CASDIN_in[32] = (CASDIN[32] !== 1'bz) && CASDIN_delay[32]; // rv 0 + assign CASDIN_in[33] = (CASDIN[33] !== 1'bz) && CASDIN_delay[33]; // rv 0 + assign CASDIN_in[34] = (CASDIN[34] !== 1'bz) && CASDIN_delay[34]; // rv 0 + assign CASDIN_in[35] = (CASDIN[35] !== 1'bz) && CASDIN_delay[35]; // rv 0 + assign CASDIN_in[36] = (CASDIN[36] !== 1'bz) && CASDIN_delay[36]; // rv 0 + assign CASDIN_in[37] = (CASDIN[37] !== 1'bz) && CASDIN_delay[37]; // rv 0 + assign CASDIN_in[38] = (CASDIN[38] !== 1'bz) && CASDIN_delay[38]; // rv 0 + assign CASDIN_in[39] = (CASDIN[39] !== 1'bz) && CASDIN_delay[39]; // rv 0 + assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN_delay[3]; // rv 0 + assign CASDIN_in[40] = (CASDIN[40] !== 1'bz) && CASDIN_delay[40]; // rv 0 + assign CASDIN_in[41] = (CASDIN[41] !== 1'bz) && CASDIN_delay[41]; // rv 0 + assign CASDIN_in[42] = (CASDIN[42] !== 1'bz) && CASDIN_delay[42]; // rv 0 + assign CASDIN_in[43] = (CASDIN[43] !== 1'bz) && CASDIN_delay[43]; // rv 0 + assign CASDIN_in[44] = (CASDIN[44] !== 1'bz) && CASDIN_delay[44]; // rv 0 + assign CASDIN_in[45] = (CASDIN[45] !== 1'bz) && CASDIN_delay[45]; // rv 0 + assign CASDIN_in[46] = (CASDIN[46] !== 1'bz) && CASDIN_delay[46]; // rv 0 + assign CASDIN_in[47] = (CASDIN[47] !== 1'bz) && CASDIN_delay[47]; // rv 0 + assign CASDIN_in[48] = (CASDIN[48] !== 1'bz) && CASDIN_delay[48]; // rv 0 + assign CASDIN_in[49] = (CASDIN[49] !== 1'bz) && CASDIN_delay[49]; // rv 0 + assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN_delay[4]; // rv 0 + assign CASDIN_in[50] = (CASDIN[50] !== 1'bz) && CASDIN_delay[50]; // rv 0 + assign CASDIN_in[51] = (CASDIN[51] !== 1'bz) && CASDIN_delay[51]; // rv 0 + assign CASDIN_in[52] = (CASDIN[52] !== 1'bz) && CASDIN_delay[52]; // rv 0 + assign CASDIN_in[53] = (CASDIN[53] !== 1'bz) && CASDIN_delay[53]; // rv 0 + assign CASDIN_in[54] = (CASDIN[54] !== 1'bz) && CASDIN_delay[54]; // rv 0 + assign CASDIN_in[55] = (CASDIN[55] !== 1'bz) && CASDIN_delay[55]; // rv 0 + assign CASDIN_in[56] = (CASDIN[56] !== 1'bz) && CASDIN_delay[56]; // rv 0 + assign CASDIN_in[57] = (CASDIN[57] !== 1'bz) && CASDIN_delay[57]; // rv 0 + assign CASDIN_in[58] = (CASDIN[58] !== 1'bz) && CASDIN_delay[58]; // rv 0 + assign CASDIN_in[59] = (CASDIN[59] !== 1'bz) && CASDIN_delay[59]; // rv 0 + assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN_delay[5]; // rv 0 + assign CASDIN_in[60] = (CASDIN[60] !== 1'bz) && CASDIN_delay[60]; // rv 0 + assign CASDIN_in[61] = (CASDIN[61] !== 1'bz) && CASDIN_delay[61]; // rv 0 + assign CASDIN_in[62] = (CASDIN[62] !== 1'bz) && CASDIN_delay[62]; // rv 0 + assign CASDIN_in[63] = (CASDIN[63] !== 1'bz) && CASDIN_delay[63]; // rv 0 + assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN_delay[6]; // rv 0 + assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN_delay[7]; // rv 0 + assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN_delay[8]; // rv 0 + assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN_delay[9]; // rv 0 + assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN_delay; // rv 1 + assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX_delay; // rv 0 + assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN_delay; // rv 0 + assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN_delay; // rv 1 + assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX_delay; // rv 0 + assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY_delay; // rv 0 + always @ (*) DINP_in = DINP_delay; + always @ (*) DIN_in = DIN_delay; + assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR_delay; // rv 0 + assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR_delay; // rv 0 + assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK_delay ^ IS_RDCLK_INVERTED_BIN); // rv 0 + assign RDEN_in = (RDEN !== 1'bz) && (RDEN_delay ^ IS_RDEN_INVERTED_BIN); // rv 0 + assign REGCE_in = (REGCE === 1'bz) || REGCE_delay; // rv 1 + assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG_delay ^ IS_RSTREG_INVERTED_BIN); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST_delay ^ IS_RST_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 + assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK_delay ^ IS_WRCLK_INVERTED_BIN); // rv 0 + assign WREN_in = (WREN !== 1'bz) && (WREN_delay ^ IS_WREN_INVERTED_BIN); // rv 0 +`else + assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP[0]; // rv 0 + assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP[1]; // rv 0 + assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP[2]; // rv 0 + assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP[3]; // rv 0 + assign CASDINP_in[4] = (CASDINP[4] !== 1'bz) && CASDINP[4]; // rv 0 + assign CASDINP_in[5] = (CASDINP[5] !== 1'bz) && CASDINP[5]; // rv 0 + assign CASDINP_in[6] = (CASDINP[6] !== 1'bz) && CASDINP[6]; // rv 0 + assign CASDINP_in[7] = (CASDINP[7] !== 1'bz) && CASDINP[7]; // rv 0 + assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN[0]; // rv 0 + assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN[10]; // rv 0 + assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN[11]; // rv 0 + assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN[12]; // rv 0 + assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN[13]; // rv 0 + assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN[14]; // rv 0 + assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN[15]; // rv 0 + assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN[16]; // rv 0 + assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN[17]; // rv 0 + assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN[18]; // rv 0 + assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN[19]; // rv 0 + assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN[1]; // rv 0 + assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN[20]; // rv 0 + assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN[21]; // rv 0 + assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN[22]; // rv 0 + assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN[23]; // rv 0 + assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN[24]; // rv 0 + assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN[25]; // rv 0 + assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN[26]; // rv 0 + assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN[27]; // rv 0 + assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN[28]; // rv 0 + assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN[29]; // rv 0 + assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN[2]; // rv 0 + assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN[30]; // rv 0 + assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN[31]; // rv 0 + assign CASDIN_in[32] = (CASDIN[32] !== 1'bz) && CASDIN[32]; // rv 0 + assign CASDIN_in[33] = (CASDIN[33] !== 1'bz) && CASDIN[33]; // rv 0 + assign CASDIN_in[34] = (CASDIN[34] !== 1'bz) && CASDIN[34]; // rv 0 + assign CASDIN_in[35] = (CASDIN[35] !== 1'bz) && CASDIN[35]; // rv 0 + assign CASDIN_in[36] = (CASDIN[36] !== 1'bz) && CASDIN[36]; // rv 0 + assign CASDIN_in[37] = (CASDIN[37] !== 1'bz) && CASDIN[37]; // rv 0 + assign CASDIN_in[38] = (CASDIN[38] !== 1'bz) && CASDIN[38]; // rv 0 + assign CASDIN_in[39] = (CASDIN[39] !== 1'bz) && CASDIN[39]; // rv 0 + assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN[3]; // rv 0 + assign CASDIN_in[40] = (CASDIN[40] !== 1'bz) && CASDIN[40]; // rv 0 + assign CASDIN_in[41] = (CASDIN[41] !== 1'bz) && CASDIN[41]; // rv 0 + assign CASDIN_in[42] = (CASDIN[42] !== 1'bz) && CASDIN[42]; // rv 0 + assign CASDIN_in[43] = (CASDIN[43] !== 1'bz) && CASDIN[43]; // rv 0 + assign CASDIN_in[44] = (CASDIN[44] !== 1'bz) && CASDIN[44]; // rv 0 + assign CASDIN_in[45] = (CASDIN[45] !== 1'bz) && CASDIN[45]; // rv 0 + assign CASDIN_in[46] = (CASDIN[46] !== 1'bz) && CASDIN[46]; // rv 0 + assign CASDIN_in[47] = (CASDIN[47] !== 1'bz) && CASDIN[47]; // rv 0 + assign CASDIN_in[48] = (CASDIN[48] !== 1'bz) && CASDIN[48]; // rv 0 + assign CASDIN_in[49] = (CASDIN[49] !== 1'bz) && CASDIN[49]; // rv 0 + assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN[4]; // rv 0 + assign CASDIN_in[50] = (CASDIN[50] !== 1'bz) && CASDIN[50]; // rv 0 + assign CASDIN_in[51] = (CASDIN[51] !== 1'bz) && CASDIN[51]; // rv 0 + assign CASDIN_in[52] = (CASDIN[52] !== 1'bz) && CASDIN[52]; // rv 0 + assign CASDIN_in[53] = (CASDIN[53] !== 1'bz) && CASDIN[53]; // rv 0 + assign CASDIN_in[54] = (CASDIN[54] !== 1'bz) && CASDIN[54]; // rv 0 + assign CASDIN_in[55] = (CASDIN[55] !== 1'bz) && CASDIN[55]; // rv 0 + assign CASDIN_in[56] = (CASDIN[56] !== 1'bz) && CASDIN[56]; // rv 0 + assign CASDIN_in[57] = (CASDIN[57] !== 1'bz) && CASDIN[57]; // rv 0 + assign CASDIN_in[58] = (CASDIN[58] !== 1'bz) && CASDIN[58]; // rv 0 + assign CASDIN_in[59] = (CASDIN[59] !== 1'bz) && CASDIN[59]; // rv 0 + assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN[5]; // rv 0 + assign CASDIN_in[60] = (CASDIN[60] !== 1'bz) && CASDIN[60]; // rv 0 + assign CASDIN_in[61] = (CASDIN[61] !== 1'bz) && CASDIN[61]; // rv 0 + assign CASDIN_in[62] = (CASDIN[62] !== 1'bz) && CASDIN[62]; // rv 0 + assign CASDIN_in[63] = (CASDIN[63] !== 1'bz) && CASDIN[63]; // rv 0 + assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN[6]; // rv 0 + assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN[7]; // rv 0 + assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN[8]; // rv 0 + assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN[9]; // rv 0 + assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN; // rv 1 + assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX; // rv 0 + assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN; // rv 0 + assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN; // rv 1 + assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX; // rv 0 + assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY; // rv 0 + always @ (*) DINP_in = DINP; + always @ (*) DIN_in = DIN; + assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR; // rv 0 + assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR; // rv 0 + assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK ^ IS_RDCLK_INVERTED_BIN); // rv 0 + assign RDEN_in = (RDEN !== 1'bz) && (RDEN ^ IS_RDEN_INVERTED_BIN); // rv 0 + assign REGCE_in = (REGCE === 1'bz) || REGCE; // rv 1 + assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG ^ IS_RSTREG_INVERTED_BIN); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 + assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK ^ IS_WRCLK_INVERTED_BIN); // rv 0 + assign WREN_in = (WREN !== 1'bz) && (WREN ^ IS_WREN_INVERTED_BIN); // rv 0 +`endif + +// internal variables, signals, busses + localparam integer ADDR_WIDTH = 15; + localparam integer INIT_WIDTH = 72; + localparam integer D_WIDTH = 64; + localparam integer DP_WIDTH = 8; + + localparam mem_width = 1; + localparam memp_width = 1; + localparam mem_size = 32768; + localparam mem_depth = mem_size; + localparam memp_depth = mem_size/8; + localparam mem_pad = 64; + localparam memp_pad = 8; + localparam encode = 1'b1; + localparam decode = 1'b0; + integer i=0; + integer j=0; + integer k=0; + integer ra=0; + integer raa=0; + integer raw=0; + integer wb=0; + integer rd_loops_a = 1; + integer wr_loops_b = 1; + localparam max_rd_loops = D_WIDTH; + localparam max_wr_loops = D_WIDTH; + integer rdcount_adj = 0; + integer wrcount_adj = 0; + integer wr_adj = 0; + wire RDEN_int; + wire RDEN_lat; + wire WREN_int; + wire WREN_lat; + wire RDEN_reg; + reg fill_lat=0; + reg fill_reg=0; + wire WREN_ecc; + wire RDEN_ecc; + reg fill_ecc=0; + wire SLEEP_A_int; + wire SLEEP_B_int; + reg [1:0] SLEEP_A_reg = 2'b0; + reg [1:0] SLEEP_B_reg = 2'b0; + wire RSTREG_A_int; + wire REGCE_A_int; + wire [7:0] DINP_int; + reg CASDOMUXA_reg = 1'b0; + reg CASOREGIMUXA_reg = 1'b0; + wire INJECTDBITERR_int; + wire INJECTSBITERR_int; + wire prog_empty; + reg prog_empty_cc = 1; + reg ram_full_c = 0; + wire ram_empty; + reg ram_empty_i = 1; + reg ram_empty_c = 1; + reg o_lat_empty = 1; + reg o_reg_empty = 1; + reg o_ecc_empty = 1; + wire [1:0] output_stages; + reg [6:0] error_bit = 7'b0; + reg [DP_WIDTH-1:0] eccparity_reg = 8'h00; + wire o_stages_full; + wire o_stages_empty; + reg o_stages_full_sync=0; + reg o_stages_full_sync1=0; + reg o_stages_full_sync2=0; + reg o_stages_full_sync3=0; + wire prog_full; + reg prog_full_reg = 1'b0; + reg rderr_reg = 1'b0; + reg wrerr_reg = 1'b0; + wire [INIT_WIDTH-1:0] INIT_A_int; + wire [INIT_WIDTH-1:0] SRVAL_A_int; + + wire mem_wr_en_b; + reg mem_wr_en_b_wf = 1'b0; + wire [D_WIDTH-1:0] mem_we_b; + wire [DP_WIDTH-1:0] memp_we_b; + wire [D_WIDTH-1:0] mem_rm_douta; + wire [DP_WIDTH-1:0] memp_rm_douta; + wire mem_rd_en_a; + wire mem_rst_a; + reg mem_is_rst_a = 1'b0; + reg first_read = 1'b0; + reg rdcount_en = 1'b0; + + reg mem [0 : mem_depth+mem_pad-1]; + reg [D_WIDTH-1 : 0] ram_rd_a; + reg [D_WIDTH-1 : 0] mem_wr_b; + reg wr_b_event = 1'b0; + reg [D_WIDTH-1 : 0] mem_rd_b_rf; + reg [D_WIDTH-1 : 0] mem_rd_b_wf; + reg [D_WIDTH-1 : 0] mem_a_reg; + reg [D_WIDTH-1 : 0] mem_a_reg_mux; + reg [D_WIDTH-1 : 0] mem_a_lat; + reg [D_WIDTH-1 : 0] mem_a_pipe; + reg memp [0 : memp_depth+memp_pad-1]; + reg [DP_WIDTH-1 : 0] ramp_rd_a; + wire [DP_WIDTH-1 : 0] memp_wr_b; + reg [DP_WIDTH-1 : 0] memp_rd_b_rf; + reg [DP_WIDTH-1 : 0] memp_rd_b_wf; + reg [DP_WIDTH-1 : 0] memp_a_reg; + reg [DP_WIDTH-1 : 0] memp_a_reg_mux; + reg [DP_WIDTH-1 : 0] memp_a_lat; + reg [DP_WIDTH-1 : 0] memp_a_out; + reg [DP_WIDTH-1 : 0] memp_a_pipe; + wire dbit_int; + wire sbit_int; + reg dbit_lat = 0; + reg sbit_lat = 0; + reg dbit_pipe = 0; + reg sbit_pipe = 0; + reg dbit_reg = 0; + reg sbit_reg = 0; + reg dbit_ecc; + reg sbit_ecc; + wire [ADDR_WIDTH-1:0] wr_addr_b_mask; + reg [ADDR_WIDTH-1:0] rd_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b = 0; + reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0; + reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0; + reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0; + wire [ADDR_WIDTH-1:0] rd_addr_wr; + wire [ADDR_WIDTH-1:0] next_rd_addr_wr; + wire [ADDR_WIDTH-1:0] wr_addr_rd; + wire [ADDR_WIDTH-1:0] next_wr_addr_rd; + wire [ADDR_WIDTH:0] wr_simple_raw; +// wire [ADDR_WIDTH:0] rd_simple_raw; + wire [ADDR_WIDTH-1:0] wr_simple; + wire [ADDR_WIDTH:0] rd_simple; + reg [ADDR_WIDTH-1:0] rd_simple_cc = 0; + reg [ADDR_WIDTH-1:0] wr_simple_sync = 0; + reg [ADDR_WIDTH-1:0] rd_simple_sync = 0; + +//reset logic variables + reg RST_in_p1 = 1'b0; + reg WRRST_int = 1'b0; + reg RST_sync = 1'b0; + reg WRRST_done = 1'b0; + reg WRRST_done1 = 1'b0; + reg WRRST_done2 = 1'b0; + wire RDRST_int; + reg RDRST_done = 1'b0; + reg RDRST_done1 = 1'b0; + reg RDRST_done2 = 1'b0; + wire WRRST_done_wr; + reg WRRST_in_sync_rd = 1'b0; + reg WRRST_in_sync_rd1 = 1'b0; + reg WRRSTBUSY_dly = 1'b0; + reg WRRSTBUSY_dly1 = 1'b0; + reg RDRSTBUSY_dly = 1'b0; + reg RDRSTBUSY_dly1 = 1'b0; + reg RDRSTBUSY_dly2 = 1'b0; + + reg [7:0] synd_wr; + reg [7:0] synd_rd; + reg [7:0] synd_ecc; + + reg sdp_mode = 1'b1; + reg sdp_mode_wr = 1'b1; + reg sdp_mode_rd = 1'b1; + +// full/empty variables + wire [ADDR_WIDTH-1:0] full_count; + wire [ADDR_WIDTH-1:0] next_full_count; + wire [ADDR_WIDTH-1:0] full_count_masked; + wire [8:0] m_full; + wire [8:0] m_full_raw; + wire [5:0] n_empty; + wire [5:0] unr_ratio; + wire [ADDR_WIDTH+1:0] prog_full_val; + wire [ADDR_WIDTH+1:0] prog_empty_val; + + reg ram_full_i; + wire ram_one_from_full_i; + wire ram_two_from_full_i; + wire ram_one_from_full; + wire ram_two_from_full; + wire ram_one_read_from_not_full; + + wire [ADDR_WIDTH-1:0] empty_count; + wire [ADDR_WIDTH-1:0] next_empty_count; + wire ram_one_read_from_empty_i; + wire ram_one_read_from_empty; + wire ram_one_write_from_not_empty; + wire ram_one_write_from_not_empty_i; + +reg en_clk_sync = 1'b0; + +// define tasks, functions + +function [7:0] fn_ecc ( + input encode, + input [63:0] d_i, + input [7:0] dp_i + ); + reg ecc_7; +begin + fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^ + d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^ + d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^ + d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^ + d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^ + d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^ + d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63]; + + fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^ + d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^ + d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^ + d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^ + d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^ + d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^ + d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63]; + + fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ + d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^ + d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ + d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ + d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ + d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ + d_i[62] ^ d_i[63]; + + ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^ + d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ + d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ + d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ + d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ + d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ + d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ + d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ + d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ + d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ + d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ + d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^ + d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + if (encode) begin + fn_ecc[7] = ecc_7 ^ + fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^ + fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6]; + end + else begin + fn_ecc[7] = ecc_7 ^ + dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^ + dp_i[4] ^ dp_i[5] ^ dp_i[6]; + end +end +endfunction // fn_ecc + +function [71:0] fn_cor_bit ( + input [6:0] error_bit, + input [63:0] d_i, + input [7:0] dp_i + ); + reg [71:0] cor_int; +begin + cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4], + d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0], + dp_i[7]}; + cor_int[error_bit] = ~cor_int[error_bit]; + fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16], + cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65], + cor_int[63:33], cor_int[31:17], cor_int[15:9], + cor_int[7:5], cor_int[3]}; +end +endfunction // fn_cor_bit + +reg cas_warning = 1'b0; +task is_cas_connected; +integer i; +begin + for (i=0;i<=63;i=i+1) begin + if (CASDIN[i] === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDIN[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + for (i=0;i<=7;i=i+1) begin + if (CASDINP[i] === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDINP[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + if (CASDOMUX === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDOMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASDOMUXEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASDOMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASNXTRDEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASNXTRDEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASOREGIMUX === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASOREGIMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CASOREGIMUXEN === 1'bz) begin + cas_warning = 1'b1; + $display("Warning: [Unisim %s-130] CASOREGIMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end +end +endtask // is_cas_connected + + assign RDEN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + CASNXTRDEN_in && ~SLEEP_A_int : RDEN_in; + assign WREN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + ~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : WREN_in; + assign DINP_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_in : DINP_in; + assign mem_wr_en_b = WREN_int && ~FULL_out && ~WRRSTBUSY_out; + assign mem_rd_en_a = (RDEN_int || + ((fill_lat || fill_reg || fill_ecc) && ~SLEEP_A_int)) && + ~ram_empty && ~RDRST_int; + + assign INJECTDBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 : + INJECTDBITERR_in; + assign INJECTSBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 : + INJECTSBITERR_in || INJECTDBITERR_in; + wire [35:0] bit_err_pat; + assign bit_err_pat = INJECTDBITERR_int ? 36'h400000004 : INJECTSBITERR_int ? 36'h000000004 : 36'h0; + always @ (*) begin + if (INJECTDBITERR_int || INJECTSBITERR_int) begin + if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) + mem_wr_b = CASDIN_in ^ {bit_err_pat, 28'h0}; + else + mem_wr_b = DIN_in ^ {bit_err_pat, 28'h0}; + end + else begin + if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) + mem_wr_b = CASDIN_in; + else + mem_wr_b = DIN_in; + end + end + assign memp_wr_b = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr : DINP_int; + +//victor DRC +reg sleep_is_asserted; +reg sleep_is_deasserted; +reg RDEN_p1; +reg RDEN_p2; +reg RDEN_p3; +reg RDEN_p4; +reg RDEN_p5; +reg RDEN_p6; +reg WREN_p1; +reg WREN_p2; +reg WREN_p3; +reg SLEEPA_p1; +reg SLEEPA_p2; +reg SLEEPB_p1; +reg SLEEPB_p2; + + always @(SLEEP_in) begin + sleep_is_asserted <= 1'b0; + sleep_is_deasserted <= 1'b0; + if (SLEEP_in == 1'b1) + sleep_is_asserted <= 1'b1; + else if (SLEEP_in == 1'b0) + sleep_is_deasserted <= 1'b1; + end + + //victor drc #5 + always @(posedge RDCLK_in) begin + if (sleep_is_asserted && RDEN_in) begin + $display("Error: [Unisim %s-23] DRC : RDEN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + always @(posedge WRCLK_in) begin + if (sleep_is_asserted && WREN_in) begin + $display("Error: [Unisim %s-23] DRC : WREN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in) begin + if (glblGSR) begin + RDEN_p1 <= 1'b0; + RDEN_p2 <= 1'b0; + RDEN_p3 <= 1'b0; + RDEN_p4 <= 1'b0; + RDEN_p5 <= 1'b0; + RDEN_p6 <= 1'b0; + end + else begin + RDEN_p1 <= RDEN_in; + RDEN_p2 <= RDEN_p1; + RDEN_p3 <= RDEN_p2; + RDEN_p4 <= RDEN_p3; + RDEN_p5 <= RDEN_p4; + RDEN_p6 <= RDEN_p5; + end + end + always @(posedge WRCLK_in) begin + if (glblGSR) begin + WREN_p1 <= 1'b0; + WREN_p2 <= 1'b0; + WREN_p3 <= 1'b0; + end + else begin + WREN_p1 <= WREN_in; + WREN_p2 <= WREN_p1; + WREN_p3 <= WREN_p2; + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if (FIRST_WORD_FALL_THROUGH_REG == "FALSE") begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one RDCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "COMMON")) begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p3) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least three cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + always @(posedge RDCLK_in or posedge WRCLK_in) begin + if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "INDEPENDENT")) begin + if (sleep_is_asserted && RDEN_p1) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + if (sleep_is_asserted && WREN_p3 && RDEN_p6) + $display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK plus six RDCLK cycles before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME); + end + end + + //victor drc #6 + always @(posedge RDCLK_in) begin + if (glblGSR) begin + SLEEPA_p1 <= 1'b0; + SLEEPA_p2 <= 1'b0; + end + else begin + SLEEPA_p1 <= SLEEP_in; + SLEEPA_p2 <= SLEEPA_p1; + end + end + always @(posedge WRCLK_in) begin + if (glblGSR) begin + SLEEPB_p1 <= 1'b0; + SLEEPB_p2 <= 1'b0; + end + else begin + SLEEPB_p1 <= SLEEP_in; + SLEEPB_p2 <= SLEEPB_p1; + end + end + always @(RDEN_in) begin + if (RDEN_in && SLEEPA_p2) + $display("Error: [Unisim %s-23] DRC : RDEN can be asserted at least 2 cycles RDCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME); + end + always @(WREN_in) begin + if (WREN_in && SLEEPB_p2) + $display("Error: [Unisim %s-23] DRC : WREN can be asserted at least 2 cycles WRCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME); + end + + assign CASCADE_ORDER_BIN = + (CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE : + (CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST : + (CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST : + (CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE : + (CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL : + CASCADE_ORDER_NONE; + + assign CLOCK_DOMAINS_BIN = + (CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT : + (CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON : + CLOCK_DOMAINS_INDEPENDENT; + + assign EN_ECC_PIPE_BIN = + (EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE : + (EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE : + EN_ECC_PIPE_FALSE; + + assign EN_ECC_READ_BIN = + (EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE : + (EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE : + EN_ECC_READ_FALSE; + + assign EN_ECC_WRITE_BIN = + (EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE : + (EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE : + EN_ECC_WRITE_FALSE; + + assign FIRST_WORD_FALL_THROUGH_BIN = + (FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE : + (FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE : + FIRST_WORD_FALL_THROUGH_FALSE; + + assign INIT_BIN = INIT_REG; + + assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG; + + assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG; + + assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG; + + assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG; + + assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG; + + assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG; + + assign RDCOUNT_TYPE_BIN = + (RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR : + (RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT : + (RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT : + (RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR : + RDCOUNT_TYPE_RAW_PNTR; + + assign READ_WIDTH_BIN = + (READ_WIDTH_REG == 4) ? READ_WIDTH_4 : + (READ_WIDTH_REG == 9) ? READ_WIDTH_9 : + (READ_WIDTH_REG == 18) ? READ_WIDTH_18 : + (READ_WIDTH_REG == 36) ? READ_WIDTH_36 : + (READ_WIDTH_REG == 72) ? READ_WIDTH_72 : + READ_WIDTH_4; + + assign REGISTER_MODE_BIN = + (REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED : + (REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED : + (REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED : + REGISTER_MODE_UNREGISTERED; + + assign RSTREG_PRIORITY_BIN = + (RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG : + (RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE : + RSTREG_PRIORITY_RSTREG; + + assign SLEEP_ASYNC_BIN = + (SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE : + (SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE : + SLEEP_ASYNC_FALSE; + + assign SRVAL_BIN = SRVAL_REG; + + assign WRCOUNT_TYPE_BIN = + (WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR : + (WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT : + (WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT : + (WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR : + WRCOUNT_TYPE_RAW_PNTR; + + assign WRITE_WIDTH_BIN = + (WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 : + (WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 : + (WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 : + (WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 : + (WRITE_WIDTH_REG == 72) ? WRITE_WIDTH_72 : + WRITE_WIDTH_4; + + initial begin + #1; + trig_attr = 1'b1; + #100; + trig_attr = 1'b0; + end + + always @ (posedge trig_attr) begin + INIT_MEM <= #100 1'b1; + INIT_MEM <= #200 1'b0; + + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_REG != "NONE") && + (CASCADE_ORDER_REG != "FIRST") && + (CASCADE_ORDER_REG != "LAST") && + (CASCADE_ORDER_REG != "MIDDLE") && + (CASCADE_ORDER_REG != "PARALLEL"))) begin + $display("Error: [Unisim %s-101] CASCADE_ORDER attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLOCK_DOMAINS_REG != "INDEPENDENT") && + (CLOCK_DOMAINS_REG != "COMMON"))) begin + $display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_PIPE_REG != "FALSE") && + (EN_ECC_PIPE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] EN_ECC_PIPE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_PIPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_READ_REG != "FALSE") && + (EN_ECC_READ_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] EN_ECC_READ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_READ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_WRITE_REG != "FALSE") && + (EN_ECC_WRITE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] EN_ECC_WRITE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WRITE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIRST_WORD_FALL_THROUGH_REG != "FALSE") && + (FIRST_WORD_FALL_THROUGH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] FIRST_WORD_FALL_THROUGH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191))) begin + $display("Error: [Unisim %s-114] PROG_EMPTY_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191))) begin + $display("Error: [Unisim %s-115] PROG_FULL_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RDCOUNT_TYPE_REG != "RAW_PNTR") && + (RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") && + (RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") && + (RDCOUNT_TYPE_REG != "SYNC_PNTR"))) begin + $display("Error: [Unisim %s-116] RDCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, RDCOUNT_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_WIDTH_REG != 4) && + (READ_WIDTH_REG != 9) && + (READ_WIDTH_REG != 18) && + (READ_WIDTH_REG != 36) && + (READ_WIDTH_REG != 72))) begin + $display("Error: [Unisim %s-117] READ_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, READ_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REGISTER_MODE_REG != "UNREGISTERED") && + (REGISTER_MODE_REG != "DO_PIPELINED") && + (REGISTER_MODE_REG != "REGISTERED"))) begin + $display("Error: [Unisim %s-118] REGISTER_MODE attribute is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED. Instance: %m", MODULE_NAME, REGISTER_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RSTREG_PRIORITY_REG != "RSTREG") && + (RSTREG_PRIORITY_REG != "REGCE"))) begin + $display("Error: [Unisim %s-119] RSTREG_PRIORITY attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SLEEP_ASYNC_REG != "FALSE") && + (SLEEP_ASYNC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRCOUNT_TYPE_REG != "RAW_PNTR") && + (WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") && + (WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") && + (WRCOUNT_TYPE_REG != "SYNC_PNTR"))) begin + $display("Error: [Unisim %s-122] WRCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, WRCOUNT_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_WIDTH_REG != 4) && + (WRITE_WIDTH_REG != 9) && + (WRITE_WIDTH_REG != 18) && + (WRITE_WIDTH_REG != 36) && + (WRITE_WIDTH_REG != 72))) begin + $display("Error: [Unisim %s-123] WRITE_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, WRITE_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (PROG_EMPTY_THRESH_REG < 1) || + (PROG_EMPTY_THRESH_REG >= mem_depth/READ_WIDTH_BIN)) begin + $display("Error: [Unisim %s-124] PROG_EMPTY_THRESH is set to %d. When READ_WIDTH is set to %d PROG_EMPTY_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG, READ_WIDTH_REG, mem_depth/READ_WIDTH_BIN); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (PROG_FULL_THRESH_REG < 1) || + (PROG_FULL_THRESH_REG >= mem_depth/WRITE_WIDTH_BIN)) begin + $display("Error: [Unisim %s-125] PROG_FULL_THRESH is set to %d. When WRITE_WIDTH is set to %d PROG_FULL_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG, WRITE_WIDTH_REG, mem_depth/WRITE_WIDTH_BIN); + attr_err = 1'b1; + end + + if ((CASCADE_ORDER_REG == "LAST") || + (CASCADE_ORDER_REG == "MIDDLE") || + (CASCADE_ORDER_REG == "PARALLEL")) begin + is_cas_connected; + if (cas_warning) $display("Warning: [Unisim %s-126] CASCADE_ORDER attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG); + end + + if (attr_err == 1'b1) #100 $finish; + end + + initial begin + INIT_MEM <= #100 1'b1; + INIT_MEM <= #200 1'b0; + end + + assign output_stages = + ((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && + (REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) && + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b11 : + ((EN_ECC_PIPE_BIN != EN_ECC_PIPE_TRUE) && + (REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) && + (FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 : + ((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ^ + (REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ^ + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b01 : 2'b10; + + assign wr_addr_b_mask = + (WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} : + (WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} : + (WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} : + (WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} : + (WRITE_WIDTH_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} : + {{ADDR_WIDTH-6{1'b1}}, 6'h3f}; + + always @(READ_WIDTH_BIN) rd_loops_a <= READ_WIDTH_BIN; + always @(WRITE_WIDTH_BIN) wr_loops_b <= WRITE_WIDTH_BIN; + + always @ (posedge RDCLK_in) begin + if (glblGSR) begin + SLEEP_A_reg <= 2'b0; + end + else begin + SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in}; + end + end + + always @ (posedge WRCLK_in) begin + if (glblGSR) begin + SLEEP_B_reg <= 2'b0; + end + else begin + SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in}; + end + end + + assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in; + assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in; + + assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg : + REGCE_in; + assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int : + (RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in : + (RSTREG_in && REGCE_in); + assign RDEN_lat = RDEN_int || ((fill_reg || fill_ecc || fill_lat) && ~SLEEP_A_int); + assign WREN_lat = mem_rd_en_a; + assign RDEN_ecc = (RDEN_int || fill_reg) && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE); + assign WREN_ecc = (RDEN_int || fill_reg || fill_ecc) && ~o_lat_empty && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && first_read; + assign RDEN_reg = RDEN_int || fill_reg ; + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) + DOUT_out = CASDIN_in; + else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) + DOUT_out = mem_a_reg ^ mem_rm_douta; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) + DOUT_out = mem_a_pipe ^ mem_rm_douta; + else + DOUT_out = mem_a_lat ^ mem_rm_douta; + end + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) + DOUTP_out = CASDINP_in; + else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) + DOUTP_out = memp_a_reg ^ memp_rm_douta; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) + DOUTP_out = memp_a_pipe ^ memp_rm_douta; + else + DOUTP_out = memp_a_lat ^ memp_rm_douta; + end + assign ECCPARITY_out = eccparity_reg; + always @ (*) begin + if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) dbit_ecc = dbit_pipe; + else dbit_ecc = dbit_lat; + end + always @ (*) begin + if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) sbit_ecc = sbit_pipe; + else sbit_ecc = sbit_lat; + end + assign DBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? dbit_reg : dbit_ecc; + assign SBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? sbit_reg : sbit_ecc; + assign INIT_A_int = + (READ_WIDTH_BIN <= READ_WIDTH_9) ? {{8{INIT_BIN[8]}}, {8{INIT_BIN[7:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_18) ? {{4{INIT_BIN[17:16]}}, {4{INIT_BIN[15:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_36) ? {{2{INIT_BIN[35:32]}}, {2{INIT_BIN[31:0]}}} : + INIT_BIN; + + assign SRVAL_A_int = + (READ_WIDTH_BIN <= READ_WIDTH_9) ? {{8{SRVAL_BIN[8]}}, {8{SRVAL_BIN[7:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_18) ? {{4{SRVAL_BIN[17:16]}}, {4{SRVAL_BIN[15:0]}}} : + (READ_WIDTH_BIN == READ_WIDTH_36) ? {{2{SRVAL_BIN[35:32]}}, {2{SRVAL_BIN[31:0]}}} : + SRVAL_BIN; + + + assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr; + assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd; +// in clock domains common what is important is the result of the next clock edge. + assign next_rd_addr_wr = (mem_rd_en_a == 1'b1) ? rd_addr_a + rd_loops_a : rd_addr_a; + assign next_wr_addr_rd = (mem_wr_en_b == 1'b1) ? wr_addr_b + wr_loops_b : wr_addr_b; + + assign o_stages_empty = + (output_stages==2'b00) ? ram_empty : + (output_stages==2'b01) ? o_lat_empty : + (output_stages==2'b11) ? o_reg_empty : //3 FWFT + ECC + REG + ((output_stages==2'b10) && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) ? + o_reg_empty : // 2 FWFT + REG + o_ecc_empty ; // 2 FWFT + ECC // 2 REG + ECC + assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync; + +// cascade out + assign CASDOUT_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + DOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTP_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + DOUTP_out : {DP_WIDTH-1{1'b0}}; + assign CASNXTEMPTY_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + EMPTY_out || SLEEP_A_int : 1'b0; + assign CASPRVRDEN_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? + ~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : 1'b0; + +// start model internals + +// integers / constants + always begin + if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b; + else wr_adj = 1; + @(wr_loops_b or rd_loops_a); + end + + always begin + if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) || + ((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0))) + wrcount_adj = 1; + else if ((output_stages>1) || + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) + wrcount_adj = output_stages*wr_adj; + else + wrcount_adj = 0; + if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) + rdcount_adj = 0; + else if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) + rdcount_adj = output_stages; + @(wr_adj or output_stages or wr_loops_b or rd_loops_a or FIRST_WORD_FALL_THROUGH_BIN or RDCOUNT_TYPE_BIN); + end + +// reset logic + assign RDRSTBUSY_out = RDRST_int; + assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly; + assign mem_rst_a = RDRST_int; + + +//vc capture a reset event, does not matter how long the user keep it asserted + always @ (posedge WRCLK_in) begin + RST_in_p1 <= RST_in; + end + + assign RST_in_pulse = RST_in & ~RST_in_p1; + + + +// RST_in sampled by WRCLK cleared by WR done +//vc RST_sync is not used + always @ (posedge WRCLK_in) begin + if (RST_in && ~RST_sync) begin + RST_sync <= 1'b1; + end + else if (WRRST_done) begin + RST_sync <= 1'b0; + end + end + + assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done; + always @ (posedge WRCLK_in) begin + //vc old method would repeat reset sequence + //if (RST_in && ~WRRSTBUSY_out) begin + if (RST_in_pulse && ~WRRSTBUSY_out) begin + WRRST_int <= #1 1'b1; + end + else if (WRRST_done_wr) begin + WRRST_int <= #1 1'b0; + end + end + +// WRRST_int sampled by RDCLK twice => RDRST_int in CDI + assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd; + always @ (posedge RDCLK_in) begin + if (glblGSR) begin + WRRST_in_sync_rd1 <= 1'b0; + WRRST_in_sync_rd <= 1'b0; + end + else begin + WRRST_in_sync_rd1 <= #1 WRRST_int; + WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1; + end + end + +// 3 rdclks to be done RD side + always @ (posedge RDCLK_in) begin + if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin + RDRST_done2 <= 1'b0; + RDRST_done1 <= 1'b0; + RDRST_done <= 1'b0; + end + else begin + RDRST_done2 <= RDRST_int; + RDRST_done1 <= RDRST_done2; + RDRST_done <= RDRST_done1; + end + end + +// 3 wrclks to be done WR side after RDRST_done + always @ (posedge WRCLK_in) begin + if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin + WRRST_done2 <= 1'b0; + WRRST_done1 <= 1'b0; + WRRST_done <= 1'b0; + end + else if (WRRST_int) begin + WRRST_done2 <= RDRST_done; + WRRST_done1 <= WRRST_done2; + WRRST_done <= WRRST_done1; + end + end + +// bug fix - 3 rd 2 wr. rtl verified + always @ (posedge RDCLK_in) begin + if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin + RDRSTBUSY_dly2 <= 1'b0; + RDRSTBUSY_dly1 <= 1'b0; + RDRSTBUSY_dly <= 1'b0; + end + else begin + RDRSTBUSY_dly2 <= RDRST_int; + RDRSTBUSY_dly1 <= RDRSTBUSY_dly2; + RDRSTBUSY_dly <= RDRSTBUSY_dly1; + end + end + + always @ (posedge WRCLK_in) begin + if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin + WRRSTBUSY_dly1 <= 1'b0; + WRRSTBUSY_dly <= 1'b0; + end + else begin + WRRSTBUSY_dly1 <= RDRSTBUSY_dly; + WRRSTBUSY_dly <= WRRSTBUSY_dly1; + end + end + +// cascade control + always @ (posedge RDCLK_in) begin + if (glblGSR) CASDOMUXA_reg <= 1'b0; + else CASDOMUXA_reg <= CASDOMUX_in; // EN tied to 1 in FIFO + end + + always @ (posedge RDCLK_in) begin + if (glblGSR) CASOREGIMUXA_reg <= 1'b0; + else CASOREGIMUXA_reg <= CASOREGIMUX_in; // EN tied to 1 in FIFO + end + +// output register + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && + CASOREGIMUXA_reg) mem_a_reg_mux = CASDIN_in; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) mem_a_reg_mux = mem_a_pipe; + else mem_a_reg_mux = mem_a_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && + CASOREGIMUXA_reg) memp_a_reg_mux = CASDINP_in; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) memp_a_reg_mux = memp_a_pipe; + else memp_a_reg_mux = memp_a_lat; + end + + always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_reg, mem_a_reg} <= #100 INIT_A_int; + end + else if (RSTREG_A_int) begin + {memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int; + end + else if (REGCE_A_int) begin + mem_a_reg <= #100 mem_a_reg_mux; + memp_a_reg <= #100 memp_a_reg_mux; + end + end + +// bit err reg + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || mem_rst_a) begin + dbit_reg <= 1'b0; + sbit_reg <= 1'b0; + end + else if (REGCE_A_int) begin + dbit_reg <= dbit_ecc; + sbit_reg <= sbit_ecc; + end + end + +// ecc pipe register + always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_pipe, mem_a_pipe} <= #100 INIT_A_int; + dbit_pipe <= #100 1'b0; + sbit_pipe <= #100 1'b0; + end + else if (mem_rst_a) begin + {memp_a_pipe, mem_a_pipe} <= #100 SRVAL_A_int; + dbit_pipe <= #100 1'b0; + sbit_pipe <= #100 1'b0; + end + else if (WREN_ecc) begin + mem_a_pipe <= #100 mem_a_lat; + memp_a_pipe <= #100 memp_a_lat; + dbit_pipe <= #100 dbit_lat; + sbit_pipe <= #100 sbit_lat; + end + end + + wire fifo_cc_count; + assign fifo_cc_count = (WRITE_WIDTH_BIN==READ_WIDTH_BIN) && (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON); + +// RDCOUNT sync to RDCLK +// assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a}; + assign rd_simple = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a}; +// assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0]; + assign RDCOUNT_out = + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && ~fifo_cc_count ? rd_simple_sync : + (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && fifo_cc_count ? rd_simple_cc : + (rd_addr_a/rd_loops_a); + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + rd_simple_cc <= 0; + else if (fifo_cc_count) + if ((RDEN_int && ~EMPTY_out) && ~mem_wr_en_b) + rd_simple_cc <= rd_simple_cc - 1; + else if ((~RDEN_int || EMPTY_out) && mem_wr_en_b) + rd_simple_cc <= rd_simple_cc + 1; + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + rd_simple_sync <= 0; + else if (rdcount_en) + if (rd_simple[ADDR_WIDTH-1:0] == {ADDR_WIDTH-1{1'b0}}) + rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]}/rd_loops_a + rdcount_adj; + else + rd_simple_sync <= rd_simple[ADDR_WIDTH-1:0]/rd_loops_a + rdcount_adj; + end + +// WRCOUNT sync to WRCLK + assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr}; + assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0]; + assign WRCOUNT_out = + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? wr_addr_b/wr_loops_b : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? wr_addr_rd/wr_loops_b : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync : + (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync : + wr_addr_b/wr_loops_b; + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) + wr_simple_sync <= 0; + else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) + wr_simple_sync <= wr_simple/wr_loops_b; + else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) + wr_simple_sync <= (wr_simple/wr_loops_b) + wrcount_adj; + end + +// with any output stage or FWFT fill the ouptut latch +// when ram not empty and o_latch empty + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + o_lat_empty <= 1; + end + else if (RDEN_lat) begin + o_lat_empty <= ram_empty; + end + else if (WREN_lat == 1) begin + o_lat_empty <= 0; + end + end + + always @ (negedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int || SLEEP_A_int) begin + fill_lat <= 0; + end + else if (o_lat_empty == 1) begin + if (output_stages>0) begin + fill_lat <= ~ram_empty; + end + end + else begin + fill_lat <= 0; + end + end + +// FWFT and +// REGISTERED not ECC_PIPE fill the ouptut register when o_latch not empty. +// REGISTERED and ECC_PIPE fill the ouptut register when o_ecc not empty. +// Empty on external read and prev stage also empty + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + o_reg_empty <= 1; + end + else if ((o_lat_empty == 0) && RDEN_reg && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin + o_reg_empty <= 0; + end + else if ((o_ecc_empty == 0) && RDEN_reg && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin + o_reg_empty <= 0; + end + else if ((o_lat_empty == 1) && RDEN_reg && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin + o_reg_empty <= 1; + end + else if ((o_ecc_empty == 1) && RDEN_reg && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin + o_reg_empty <= 1; + end + end + + always @ (negedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int || SLEEP_A_int) begin + fill_reg <= 0; + end + else if ((o_lat_empty == 0) && (o_reg_empty == 1) && + (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE) && + (output_stages==2)) begin + fill_reg <= 1; + end + else if ((o_ecc_empty == 0) && (o_reg_empty == 1) && + (output_stages==3)) begin + fill_reg <= first_read; + end + else begin + fill_reg <= 0; + end + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + o_ecc_empty <= 1; + end + else if (RDEN_ecc || WREN_ecc) begin + o_ecc_empty <= o_lat_empty; + end + end + + always @ (negedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int || SLEEP_A_int) begin + fill_ecc <= 0; + end + else if ((o_lat_empty == 0) && (o_ecc_empty == 1) && first_read && + ((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && + ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) || + (FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)))) begin + fill_ecc <= 1; + end + else begin + fill_ecc <= 0; + end + end + +// read engine + always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin + if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin + for (raa=0;raa= 8) begin + for (raa=0;raa> ra; + if (ra> (D_WIDTH+ra); + end + end + first_read <= 1'b0; + rdcount_en <= 1'b0; + end + else if (SLEEP_A_int && mem_rd_en_a) begin + $display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_a <= 1'b0; + for (ra=0;ra> ra; + if (ra> (D_WIDTH+ra); + end + end + end + end + else if (WREN_lat) begin + mem_is_rst_a <= 1'b0; + if ((EN_ECC_READ_BIN == EN_ECC_READ_TRUE) && sbit_int) begin + {memp_a_lat, mem_a_lat} <= #100 fn_cor_bit(synd_ecc[6:0], ram_rd_a, ramp_rd_a); + end + else begin + mem_a_lat <= #100 ram_rd_a; + memp_a_lat <= #100 ramp_rd_a; + end + first_read <= 1'b1; + rdcount_en <= 1'b1; + end + else if (RDEN_int) begin + rdcount_en <= 1'b1; + end + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) begin + rd_addr_a <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}}; + end + else begin + if (mem_rd_en_a) begin + rd_addr_a <= rd_addr_a + rd_loops_a; + end + rd_addr_a_wr <= rd_addr_a; + wr_addr_sync_rd2 <= wr_addr_b_rd; + wr_addr_sync_rd1 <= wr_addr_sync_rd2; + wr_addr_sync_rd <= wr_addr_sync_rd1; + end + end + +// write engine + always @ (posedge WRCLK_in or posedge INIT_MEM) begin + if (INIT_MEM == 1'b1) begin +// initialize memory + for (i=0;i WRITE_WIDTH_4) begin + for (wb=0;wb WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}}; + assign WRERR_out = wrerr_reg; + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR) + wrerr_reg <= 1'b0; + else if (WREN_int && (FULL_out || WRRSTBUSY_out)) + wrerr_reg <= 1'b1; + else + wrerr_reg <= 1'b0; + end + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + wr_addr_b <= {ADDR_WIDTH-1{1'b0}}; + wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}}; + o_stages_full_sync2 <= 1'b0; + o_stages_full_sync1 <= 1'b0; + o_stages_full_sync <= 1'b0; + rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}}; + rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}}; + end + else begin + if (mem_wr_en_b) begin + wr_addr_b <= wr_addr_b + wr_loops_b; + end + wr_addr_b_rd <= wr_addr_b; + o_stages_full_sync2 <= ~o_stages_empty; + o_stages_full_sync1 <= o_stages_full_sync2; + o_stages_full_sync <= o_stages_full_sync1; + rd_addr_sync_wr2 <= rd_addr_a_wr; + rd_addr_sync_wr1 <= rd_addr_sync_wr2; + rd_addr_sync_wr <= rd_addr_sync_wr1; + end + end + +// full flag + assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out)); + assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full; + assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0; + assign m_full = (output_stages == 0) ? 0 : ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b); + assign m_full_raw = output_stages*rd_loops_a; + assign n_empty = output_stages; + assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a; + + assign full_count_masked = full_count & wr_addr_b_mask; + assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b}; + assign next_full_count = {1'b1, next_rd_addr_wr} - {1'b0, next_wr_addr_rd}; + + assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i; +// ram_full independent clocks is one_from_full common clocks + assign ram_one_from_full_i = ((full_count < 2*wr_loops_b) && (full_count > 0)); + assign ram_two_from_full_i = ((full_count < 3*wr_loops_b) && (full_count > 0)); + assign ram_one_from_full = (next_full_count < wr_loops_b) && ~ram_full_c; + assign ram_two_from_full = (next_full_count < 2*wr_loops_b) && ~ram_full_c; +// when full common clocks, next read makes it not full +// assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c); + assign ram_one_read_from_not_full = (next_full_count >= wr_loops_b) && ram_full_c; + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + ram_full_c <= 1'b0; + end + else if (mem_wr_en_b && + (mem_rd_en_a && (rd_loops_a < wr_loops_b)) && + ram_one_from_full) begin + ram_full_c <= 1'b1; + end + else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin + ram_full_c <= 1'b1; + end + else if (mem_rd_en_a && ram_one_read_from_not_full) begin + ram_full_c <= 1'b0; + end + else begin + ram_full_c <= ram_full_c; + end + end + + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + ram_full_i <= 1'b0; + end + else if (mem_wr_en_b && ram_two_from_full_i && ~ram_full_i) begin + ram_full_i <= 1'b1; + end + else if (~ram_one_from_full_i) begin + ram_full_i <= 1'b0; + end + else begin + ram_full_i <= ram_full_i; + end + end + + assign PROGFULL_out = prog_full_reg; + always @ (posedge WRCLK_in or glblGSR) begin + if (glblGSR || WRRSTBUSY_out) begin + prog_full_reg <= 1'b0; + end + else begin + prog_full_reg <= prog_full; + end + end + +// empty flag + assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a}; + assign next_empty_count = {1'b1, next_wr_addr_rd} - {1'b0, next_rd_addr_wr}; + assign EMPTY_out = o_stages_empty; + assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i; + assign ram_one_read_from_empty_i = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty; + assign ram_one_read_from_empty = (next_empty_count < rd_loops_a) && ~ram_empty; + assign ram_one_write_from_not_empty = (next_empty_count >= rd_loops_a) && ram_empty; + assign ram_one_write_from_not_empty_i = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a); + assign prog_empty = ((empty_count < prog_empty_val) || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON && ram_empty)) && (~FULL_out || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT)); + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + ram_empty_c <= 1'b1; +// RD only makes empty + else if (~mem_wr_en_b && + mem_rd_en_a && + (ram_one_read_from_empty || ram_empty_c)) + ram_empty_c <= 1'b1; +// RD and WR when one read from empty and RD more than WR makes empty + else if (mem_wr_en_b && + (mem_rd_en_a && (rd_loops_a > wr_loops_b)) && + (ram_one_read_from_empty || ram_empty_c)) + ram_empty_c <= 1'b1; +// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR + else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c)) + ram_empty_c <= 1'b0; + else + ram_empty_c <= ram_empty_c; + end + + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + ram_empty_i <= 1'b1; + else if (mem_rd_en_a && ram_one_read_from_empty_i) // RDEN_in ? + ram_empty_i <= 1'b1; + else if (empty_count < rd_loops_a) + ram_empty_i <= 1'b1; + else + ram_empty_i <= 1'b0; + end + +// assign PROGEMPTY_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? prog_empty_cc : prog_empty; + assign PROGEMPTY_out = prog_empty_cc; + always @ (posedge RDCLK_in or glblGSR) begin + if (glblGSR || RDRST_int) + prog_empty_cc <= 1'b1; + else + prog_empty_cc <= prog_empty; + end +// eccparity is flopped + always @ (*) begin + if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) synd_wr = 8'b0; + else begin + if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) || + (CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) + synd_wr = fn_ecc(encode, CASDIN_in, CASDINP_in); + else + synd_wr = fn_ecc(encode, DIN_in, DINP_in); + end + end + always @ (*) begin + if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) synd_rd = fn_ecc(decode, ram_rd_a, ramp_rd_a); + else synd_rd = 8'b0; + end + always @ (*) begin + if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) synd_ecc = synd_rd ^ ramp_rd_a; + else synd_ecc = 8'b0; + end + assign sbit_int = (|synd_ecc && synd_ecc[7]); + assign dbit_int = (|synd_ecc && ~synd_ecc[7]); + always @(posedge RDCLK_in) begin + if (mem_rst_a) begin + sbit_lat <= 1'b0; + dbit_lat <= 1'b0; + error_bit <= 7'b0; + end + else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin + sbit_lat <= sbit_int; + dbit_lat <= dbit_int; + error_bit <= synd_ecc[6:0]; + end + end + +// assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ? +// fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) : +// {memp_rd_a, mem_rd_a}; + + always @ (posedge WRCLK_in or glblGSR) begin + if(glblGSR || (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE)) + eccparity_reg <= 8'h00; + else if (mem_wr_en_b) + eccparity_reg <= synd_wr; + end + +`ifdef XIL_TIMING + reg notifier; + wire rdclk_en_n; + wire rdclk_en_p; + wire wrclk_en_n; + wire wrclk_en_p; + assign rdclk_en_n = IS_RDCLK_INVERTED_BIN; + assign rdclk_en_p = ~IS_RDCLK_INVERTED_BIN; + assign wrclk_en_n = IS_WRCLK_INVERTED_BIN; + assign wrclk_en_p = ~IS_WRCLK_INVERTED_BIN; +`endif + + specify + (CASDIN *> CASDOUT) = (0:0:0, 0:0:0); + (CASDIN *> DOUT) = (0:0:0, 0:0:0); + (CASDINP *> CASDOUTP) = (0:0:0, 0:0:0); + (CASDINP *> DOUTP) = (0:0:0, 0:0:0); + (CASPRVEMPTY => CASPRVRDEN) = (0:0:0, 0:0:0); + (RDCLK *> CASDOUT) = (100:100:100, 100:100:100); + (RDCLK *> CASDOUTP) = (100:100:100, 100:100:100); + (RDCLK *> DOUT) = (100:100:100, 100:100:100); + (RDCLK *> DOUTP) = (100:100:100, 100:100:100); + (RDCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (RDCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (RDCLK => CASNXTEMPTY) = (100:100:100, 100:100:100); + (RDCLK => DBITERR) = (100:100:100, 100:100:100); + (RDCLK => EMPTY) = (100:100:100, 100:100:100); + (RDCLK => PROGEMPTY) = (100:100:100, 100:100:100); + (RDCLK => RDERR) = (100:100:100, 100:100:100); + (RDCLK => RDRSTBUSY) = (100:100:100, 100:100:100); + (RDCLK => SBITERR) = (100:100:100, 100:100:100); + (WRCLK *> CASDOUT) = (100:100:100, 100:100:100); + (WRCLK *> CASDOUTP) = (100:100:100, 100:100:100); + (WRCLK *> DOUT) = (100:100:100, 100:100:100); + (WRCLK *> DOUTP) = (100:100:100, 100:100:100); + (WRCLK *> ECCPARITY) = (100:100:100, 100:100:100); + (WRCLK *> RDCOUNT) = (100:100:100, 100:100:100); + (WRCLK *> WRCOUNT) = (100:100:100, 100:100:100); + (WRCLK => CASPRVRDEN) = (100:100:100, 100:100:100); + (WRCLK => FULL) = (100:100:100, 100:100:100); + (WRCLK => PROGFULL) = (100:100:100, 100:100:100); + (WRCLK => RDRSTBUSY) = (100:100:100, 100:100:100); + (WRCLK => WRERR) = (100:100:100, 100:100:100); + (WRCLK => WRRSTBUSY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay); + $setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay); + $setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay); + $setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay); + $setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay); + $setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay); + $setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay); + $setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay); + $setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay); + $setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay); + $setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay); + $setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay); + $setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay); + $setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay); + $setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay); + $setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay); + $setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay); + $setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay); + $setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay); + $setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay); + $setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay); + $setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay); + $setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay); + $setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay); + $setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay); + $setuphold (negedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay); + $setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay); + $setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay); + $setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay); + $setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay); + $setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay); + $setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay); + $setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay); + $setuphold (negedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay); + $setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay); + $setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay); + $setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay); + $setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay); + $setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay); + $setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay); + $setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay); + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay); + $setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay); + $setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay); + $setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay); + $setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay); + $setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay); + $setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay); + $setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay); + $setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay); + $setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay); + $setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay); + $setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay); + $setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay); + $setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay); + $setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay); + $setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay); + $setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay); + $setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay); + $setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay); + $setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay); + $setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay); + $setuphold (posedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay); + $setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay); + $setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay); + $setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay); + $setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay); + $setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay); + $setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay); + $setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay); + $setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay); + $setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay); + $setuphold (posedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay); + $setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FRAME_ECCE2.v b/verilog/src/unisims/FRAME_ECCE2.v new file mode 100644 index 0000000..cd8fa03 --- /dev/null +++ b/verilog/src/unisims/FRAME_ECCE2.v @@ -0,0 +1,487 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +///////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i (O.71) +// \ \ Description : +// / / +// /__/ /\ Filename : FRAME_ECCE2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 07/22/10 - Change Error to Message for input rbt file check (CR568991) +// 08/04/11 - Change FRAME_RBT_IN_FILENAME ot NONE (CR618399) +////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module FRAME_ECCE2 ( + CRCERROR, + ECCERROR, + ECCERRORSINGLE, + FAR, + SYNBIT, + SYNDROME, + SYNDROMEVALID, + SYNWORD +); + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif // + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "NONE"; + localparam FRAME_ECC_OUT_RBT_FILENAME = "frame_rbt_out_e2.txt"; + localparam FRAME_ECC_OUT_ECC_FILENAME = "frame_ecc_out_e2.txt"; + + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [25:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; + + reg clk_osc = 0; + integer rbt_fd; + integer ecc_ecc_out_fd; + integer ecc_rbt_out_fd; + reg [31:0] rb_data = 32'b0; + reg [31:0] data_rbt; + reg [31:0] tmpwd1; + reg [31:0] tmpwd2; + reg sim_file_flag = 0; + reg [31:0] frame_data_bak[255:174]; + reg [31:0] frame_data[255:174]; + integer frame_addr_i; + reg [31:0] frame_addr; + reg [31:0] rb_crc_rbt; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg rbcrc_err = 0; + reg rd_rbt_hold = 0; + reg rd_rbt_hold1 = 0; + reg rd_rbt_hold2 = 0; + reg [6:0] ecc_wadr; + reg [4:0] ecc_badr; + reg [31:0] corr_wd; + reg [31:0] corr_wd1; + reg rb_data_en = 0; + reg end_rbt = 0; + reg rd_rbt_en = 0; + reg hamming_rst = 0; + integer i = 0; + integer bi = 174; + integer nbi = 174; + integer n = 174; + + reg ecc_run = 0; + reg calc_syndrome = 1; + wire [12:0] new_S; + wire [12:0] next_S; + reg [12:0] S = 13'd0; + reg S_valid = 0; + reg S_valid_ungated = 0; + reg [31:0] ecc_corr_mask = 32'b0; + reg ecc_error = 0; + reg ecc_error_single = 0; + reg ecc_error_ungated = 0; + reg [4:0] ecc_synbit = 5'b0; + reg [6:0] ecc_synword = 7'b0; + reg [4:0] ecc_synbit_next = 5'b0; + reg [6:0] ecc_synword_next = 7'b0; + reg efar_save = 0; + reg [11:5] hiaddr = 7'd46; + wire [11:5] hiaddrp1; + wire hiaddr63; + wire hiaddr127; + wire hclk; + wire xorall; + wire overall; + wire S_valid_next; + wire S_valid_ungated_next; + wire next_error; + wire [12:0] new_S_xor_S; + wire [6:0] ecc_synword_next_not_par; + reg [160:0] tmps1; + reg [160:0] tmps2; + reg [160:0] tmps3; + + + initial begin + case (FARSRC) + "EFAR" : ; + "FAR" : ; + default : begin + $display("Attribute Syntax Error : The Attribute FARSRC on FRAME_ECCE2 instance %m is set to %s. Legal values for this attribute are EFAR, or FAR.", FARSRC); + #1 $finish; + end + endcase + + sim_file_flag = 0; + if (FRAME_RBT_IN_FILENAME == "NONE") + $display(" Message: The configuration frame data file for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n"); + else begin + rbt_fd = $fopen(FRAME_RBT_IN_FILENAME, "r"); + ecc_ecc_out_fd = $fopen(FRAME_ECC_OUT_ECC_FILENAME, "w"); + ecc_rbt_out_fd = $fopen(FRAME_ECC_OUT_RBT_FILENAME, "w"); + if (rbt_fd == 0) + $display(" Message: The configuration frame data file %s for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n", FRAME_RBT_IN_FILENAME); + else + if ($fscanf(rbt_fd, "%s\t%s\t%s", tmps1, tmps2, tmps3) != -1) + rd_rbt_en <= #1 1; + + if (ecc_ecc_out_fd == 0) + $display(" Error: The ecc frame data out file frame_ecc_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n"); + if (ecc_rbt_out_fd == 0) + $display(" Error: The rbt frame data out file frame_rbt_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n"); + if (rbt_fd !=0 && ecc_ecc_out_fd != 0 && ecc_rbt_out_fd != 0 ) + sim_file_flag = 1; + end + end + + assign CRCERROR = rbcrc_err; + assign ECCERROR = ecc_error; + assign ECCERRORSINGLE = ecc_error_single; + assign SYNDROMEVALID = S_valid; + assign SYNDROME = S; + assign FAR = frame_addr[25:0]; + assign SYNBIT = ecc_synbit; + assign SYNWORD = ecc_synword; + + + always + #2000 clk_osc <= ~clk_osc; + + always @(negedge clk_osc ) + if (sim_file_flag == 1 && rd_rbt_en == 1 && rd_rbt_hold1 == 0 ) begin + if ( $fscanf(rbt_fd, "%d\t%b\t%b", frame_addr_i, data_rbt, rb_crc_rbt) != -1) begin + rb_data_en <= 1; + frame_addr <= frame_addr_i; + rb_data <= data_rbt; + crc_input[36:0] = {5'b00011, data_rbt}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + if (n <= 255) begin + frame_data[n] <= data_rbt[31:0]; + if (n == 255) + n <= 174; + else if (n==191) + n <= 193; + else + n <= n+ 1; + end + end + else begin + rb_data_en <= 0; + end_rbt <= 1; + n <= 173; + if ( crc_new != rb_crc_rbt) + rbcrc_err <= 1; + else + rbcrc_err <= 0; + $fclose(rbt_fd); + end + end + + always @(negedge clk_osc) + if (rb_data_en == 1) begin + if ( rd_rbt_hold1 == 1 && rd_rbt_hold == 1 && rd_rbt_hold2 == 0) begin + for (bi = 174; bi<= 255; bi=bi+1) + frame_data_bak[bi] = frame_data[bi]; + if (ecc_error_single == 1) begin + ecc_wadr[6:0] = SYNDROME[11:5]; + ecc_badr[4:0] = SYNDROME[4:0]; + corr_wd = frame_data[ecc_wadr]; + corr_wd1 = frame_data[ecc_wadr]; + corr_wd[ecc_badr] = ~corr_wd1[ecc_badr]; + frame_data_bak[ecc_wadr] = corr_wd; + end + for (nbi = 174; nbi<= 255; nbi=nbi+1) begin + if (nbi != 192) begin + tmpwd1 = frame_data[nbi]; + tmpwd2 = frame_data_bak[nbi]; + $fwriteb(ecc_rbt_out_fd, tmpwd1); + $fwriteb(ecc_rbt_out_fd, "\n"); + $fwriteb(ecc_ecc_out_fd, tmpwd2); + $fwriteb(ecc_ecc_out_fd, "\n"); + end + end + end + end + else if (end_rbt ==1) begin + $fclose(ecc_ecc_out_fd); + $fclose(ecc_rbt_out_fd); + end + + always @(posedge clk_osc) + if (rb_data_en == 1) begin + if (n == 255) + rd_rbt_hold <= 1; + rd_rbt_hold2 <= rd_rbt_hold1; + rd_rbt_hold1 <= rd_rbt_hold; + if (rd_rbt_hold2 ==1) begin + rd_rbt_hold <= 0; + rd_rbt_hold1 <= 0; + rd_rbt_hold2 <= 0; + end + end + else if ( end_rbt == 1) begin + rd_rbt_hold <= 1; + rd_rbt_hold1 <= 1; + rd_rbt_hold2 <= 1; + end + + always @(negedge clk_osc) + if (rd_rbt_hold2 == 1 && hamming_rst == 0) + hamming_rst <= 1; + else + hamming_rst <= 0; + + assign S_valid_next = rb_data_en & hiaddr127 & ~ecc_run; + assign S_valid_ungated_next = rb_data_en & hiaddr127; + assign next_error = (| next_S); + assign hiaddrp1 = hiaddr + 1; + assign hiaddr63 = & hiaddr[10:5]; + assign hiaddr127 = & hiaddr[11:5]; + assign hclk = ( hiaddr == 7'd87 ) ? 1 : 0; + + always @( posedge clk_osc or posedge hamming_rst) + if (hamming_rst == 1) + hiaddr <= 7'd46; + else if ( rb_data_en == 1 ) begin + if ( hiaddr127 ) + hiaddr <= 7'd46; + else + hiaddr <= { hiaddrp1[11:6], ( hiaddr63 | hiaddrp1[5] ) }; + end + + assign xorall = ( ^ rb_data[31:13] ) ^ ( ( ~ hclk ) & ( ^ rb_data[12:0] ) ); + assign overall = ( ^ rb_data[31:13] ) ^ ( ~(hclk & calc_syndrome) & ( ^ rb_data[12:0] ) ); + + assign new_S[12] = overall; + + assign new_S[4] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^ + rb_data[19] ^ rb_data[18] ^ rb_data[17] ^ rb_data[16] ^ + ( hclk & ~calc_syndrome & rb_data[4] ); + assign new_S[3] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^ + rb_data[15] ^ rb_data[14] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[3] : + ( rb_data[12] ^ rb_data[11] ^ rb_data[10] ^ rb_data[9] ^ rb_data[8]) ); + assign new_S[2] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^ + rb_data[15] ^ rb_data[14] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[2] : + ( rb_data[12] ^ rb_data[7] ^ rb_data[6] ^ rb_data[5] ^ rb_data[4] ) ); + assign new_S[1] = rb_data[31] ^ rb_data[30] ^ rb_data[27] ^ rb_data[26] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[19] ^ rb_data[18] ^ + rb_data[15] ^ rb_data[14] ^ + ( hclk ? ~calc_syndrome & rb_data[1] : + ( rb_data[11] ^ rb_data[10] ^ rb_data[7] ^ rb_data[6] ^ rb_data[3] ^ rb_data[2] )); + assign new_S[0] = rb_data[31] ^ rb_data[29] ^ rb_data[27] ^ rb_data[25] ^ + rb_data[23] ^ rb_data[21] ^ rb_data[19] ^ rb_data[17] ^ + rb_data[15] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[0] : + ( rb_data[11] ^ rb_data[9] ^ rb_data[7] ^ rb_data[5] ^ rb_data[3] ^ rb_data[1] ) ); + + assign new_S[11:5] = ( hiaddr & { 7 { xorall } } ) ^ + ( { 7 { hclk & ~calc_syndrome } } & + { rb_data[11], rb_data[10], rb_data[9], rb_data[8], + rb_data[7], rb_data[6], rb_data[5] } ); + + assign new_S_xor_S = S ^ new_S; + assign next_S = (hiaddr127 & calc_syndrome) ? {(^new_S_xor_S), new_S_xor_S[11:0]} : + (hiaddr == 7'd46) ? new_S : new_S_xor_S; + + assign ecc_synword_next_not_par = new_S_xor_S[11:5] - 7'd46 - {6'b0, new_S_xor_S[11]}; + + always @(ecc_synword_next_not_par, new_S_xor_S) begin + if (!new_S_xor_S[12]) begin + ecc_synword_next = 7'd0; + ecc_synbit_next = 5'd0; + end else begin + case (new_S_xor_S[11:0]) + 12'h000 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd12; + end + 12'h001 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd0; + end + 12'h002 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd1; + end + 12'h004 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd2; + end + 12'h008 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd3; + end + 12'h010 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd4; + end + 12'h020 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd5; + end + 12'h040 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd6; + end + 12'h080 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd7; + end + 12'h100 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd8; + end + 12'h200 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd9; + end + 12'h400 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd10; + end + 12'h800 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd11; + end + default : begin + ecc_synword_next = ecc_synword_next_not_par; + ecc_synbit_next = new_S_xor_S[4:0]; + end + endcase + end + end + + always @( posedge clk_osc or posedge hamming_rst) begin + if ( hamming_rst == 1 ) begin + S_valid <= 0; + S_valid_ungated <= 0; + S <= 13'd0; + end + else if ( rb_data_en == 1 ) begin + S_valid_ungated <= S_valid_ungated_next; + S_valid <= S_valid_next; + S <= next_S; + end else begin + S_valid_ungated <= 0; + S_valid <= 0; + end + + if (hamming_rst == 1 ) begin + ecc_synword <= 7'd0; + ecc_synbit <= 5'd0; + end + else if ( S_valid_next & ~efar_save ) begin + ecc_synword <= ecc_synword_next; + ecc_synbit <= ecc_synbit_next; + end + + if (hamming_rst == 1) begin + ecc_error <= 0; + ecc_error_single <= 0; + end + else if (S_valid_next == 1) begin + ecc_error <= next_error; + ecc_error_single <= next_S[12]; + end + + if (hamming_rst == 1) + ecc_error_ungated <= 0; + else if (S_valid_ungated_next == 1) + ecc_error_ungated <= next_error; + + if (hamming_rst == 1) + efar_save <= 0; + else if (ecc_error == 1 | ((S_valid_ungated_next & next_error) == 1)) + efar_save <= 1; + + end + + + function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; + reg [31:0] x; + reg [36:0] m; + begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + end + endfunction + + specify + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FRAME_ECCE3.v b/verilog/src/unisims/FRAME_ECCE3.v new file mode 100644 index 0000000..6ca8814 --- /dev/null +++ b/verilog/src/unisims/FRAME_ECCE3.v @@ -0,0 +1,82 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2013.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : FRAME_ECCE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/30/13 - Initial version. +// 02/26/14 - Pulldown all outputs (CR 775504). +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine +module FRAME_ECCE3 + `ifdef XIL_TIMING //Simprim + #( + parameter LOC = "UNPLACED" +) + `endif +( + output CRCERROR, + output ECCERRORNOTSINGLE, + output ECCERRORSINGLE, + output ENDOFFRAME, + output ENDOFSCAN, + output [25:0] FAR, + + input [1:0] FARSEL, + input ICAPBOTCLK, + input ICAPTOPCLK + +); + + pulldown (CRCERROR); + pulldown (ECCERRORNOTSINGLE); + pulldown (ECCERRORSINGLE); + pulldown (ENDOFFRAME); + pulldown (ENDOFSCAN); + pulldown far_net[25:0] (FAR); + + tri0 glblGSR = glbl.GSR; + + specify + (ICAPBOTCLK *> FAR) = (0:0:0, 0:0:0); + (ICAPBOTCLK => ECCERRORNOTSINGLE) = (0:0:0, 0:0:0); + (ICAPBOTCLK => ECCERRORSINGLE) = (0:0:0, 0:0:0); + (ICAPBOTCLK => ENDOFFRAME) = (0:0:0, 0:0:0); + (ICAPBOTCLK => ENDOFSCAN) = (0:0:0, 0:0:0); + (ICAPTOPCLK *> FAR) = (0:0:0, 0:0:0); + (ICAPTOPCLK => ECCERRORNOTSINGLE) = (0:0:0, 0:0:0); + (ICAPTOPCLK => ECCERRORSINGLE) = (0:0:0, 0:0:0); + (ICAPTOPCLK => ENDOFFRAME) = (0:0:0, 0:0:0); + (ICAPTOPCLK => ENDOFSCAN) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/FRAME_ECCE4.v b/verilog/src/unisims/FRAME_ECCE4.v new file mode 100644 index 0000000..4267156 --- /dev/null +++ b/verilog/src/unisims/FRAME_ECCE4.v @@ -0,0 +1,57 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : FRAME_ECCE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module FRAME_ECCE4 +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output CRCERROR, + output ECCERRORNOTSINGLE, + output ECCERRORSINGLE, + output ENDOFFRAME, + output ENDOFSCAN, + output [26:0] FAR, + + input [1:0] FARSEL, + input ICAPBOTCLK, + input ICAPTOPCLK +); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GND.v b/verilog/src/unisims/GND.v new file mode 100644 index 0000000..07d05db --- /dev/null +++ b/verilog/src/unisims/GND.v @@ -0,0 +1,51 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / GND Connection +// /___/ /\ Filename : GND.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +`celldefine + +module GND(G); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + output G; + + assign G = 1'b0; + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/GTHE2_CHANNEL.v b/verilog/src/unisims/GTHE2_CHANNEL.v new file mode 100644 index 0000000..1350c9e --- /dev/null +++ b/verilog/src/unisims/GTHE2_CHANNEL.v @@ -0,0 +1,4625 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTHE2_CHANNEL.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// Initial version +// 09/22/11 - 624065 - YML update +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 11/08/12 - 686590 - YML default attribute changes +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine + +module GTHE2_CHANNEL ( + CPLLFBCLKLOST, + CPLLLOCK, + CPLLREFCLKLOST, + DMONITOROUT, + DRPDO, + DRPRDY, + EYESCANDATAERROR, + GTHTXN, + GTHTXP, + GTREFCLKMONITOR, + PCSRSVDOUT, + PHYSTATUS, + RSOSINTDONE, + RXBUFSTATUS, + RXBYTEISALIGNED, + RXBYTEREALIGN, + RXCDRLOCK, + RXCHANBONDSEQ, + RXCHANISALIGNED, + RXCHANREALIGN, + RXCHARISCOMMA, + RXCHARISK, + RXCHBONDO, + RXCLKCORCNT, + RXCOMINITDET, + RXCOMMADET, + RXCOMSASDET, + RXCOMWAKEDET, + RXDATA, + RXDATAVALID, + RXDFESLIDETAPSTARTED, + RXDFESLIDETAPSTROBEDONE, + RXDFESLIDETAPSTROBESTARTED, + RXDFESTADAPTDONE, + RXDISPERR, + RXDLYSRESETDONE, + RXELECIDLE, + RXHEADER, + RXHEADERVALID, + RXMONITOROUT, + RXNOTINTABLE, + RXOSINTSTARTED, + RXOSINTSTROBEDONE, + RXOSINTSTROBESTARTED, + RXOUTCLK, + RXOUTCLKFABRIC, + RXOUTCLKPCS, + RXPHALIGNDONE, + RXPHMONITOR, + RXPHSLIPMONITOR, + RXPMARESETDONE, + RXPRBSERR, + RXQPISENN, + RXQPISENP, + RXRATEDONE, + RXRESETDONE, + RXSTARTOFSEQ, + RXSTATUS, + RXSYNCDONE, + RXSYNCOUT, + RXVALID, + TXBUFSTATUS, + TXCOMFINISH, + TXDLYSRESETDONE, + TXGEARBOXREADY, + TXOUTCLK, + TXOUTCLKFABRIC, + TXOUTCLKPCS, + TXPHALIGNDONE, + TXPHINITDONE, + TXPMARESETDONE, + TXQPISENN, + TXQPISENP, + TXRATEDONE, + TXRESETDONE, + TXSYNCDONE, + TXSYNCOUT, + + CFGRESET, + CLKRSVD0, + CLKRSVD1, + CPLLLOCKDETCLK, + CPLLLOCKEN, + CPLLPD, + CPLLREFCLKSEL, + CPLLRESET, + DMONFIFORESET, + DMONITORCLK, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + EYESCANMODE, + EYESCANRESET, + EYESCANTRIGGER, + GTGREFCLK, + GTHRXN, + GTHRXP, + GTNORTHREFCLK0, + GTNORTHREFCLK1, + GTREFCLK0, + GTREFCLK1, + GTRESETSEL, + GTRSVD, + GTRXRESET, + GTSOUTHREFCLK0, + GTSOUTHREFCLK1, + GTTXRESET, + LOOPBACK, + PCSRSVDIN, + PCSRSVDIN2, + PMARSVDIN, + QPLLCLK, + QPLLREFCLK, + RESETOVRD, + RX8B10BEN, + RXADAPTSELTEST, + RXBUFRESET, + RXCDRFREQRESET, + RXCDRHOLD, + RXCDROVRDEN, + RXCDRRESET, + RXCDRRESETRSV, + RXCHBONDEN, + RXCHBONDI, + RXCHBONDLEVEL, + RXCHBONDMASTER, + RXCHBONDSLAVE, + RXCOMMADETEN, + RXDDIEN, + RXDFEAGCHOLD, + RXDFEAGCOVRDEN, + RXDFEAGCTRL, + RXDFECM1EN, + RXDFELFHOLD, + RXDFELFOVRDEN, + RXDFELPMRESET, + RXDFESLIDETAP, + RXDFESLIDETAPADAPTEN, + RXDFESLIDETAPHOLD, + RXDFESLIDETAPID, + RXDFESLIDETAPINITOVRDEN, + RXDFESLIDETAPONLYADAPTEN, + RXDFESLIDETAPOVRDEN, + RXDFESLIDETAPSTROBE, + RXDFETAP2HOLD, + RXDFETAP2OVRDEN, + RXDFETAP3HOLD, + RXDFETAP3OVRDEN, + RXDFETAP4HOLD, + RXDFETAP4OVRDEN, + RXDFETAP5HOLD, + RXDFETAP5OVRDEN, + RXDFETAP6HOLD, + RXDFETAP6OVRDEN, + RXDFETAP7HOLD, + RXDFETAP7OVRDEN, + RXDFEUTHOLD, + RXDFEUTOVRDEN, + RXDFEVPHOLD, + RXDFEVPOVRDEN, + RXDFEVSEN, + RXDFEXYDEN, + RXDLYBYPASS, + RXDLYEN, + RXDLYOVRDEN, + RXDLYSRESET, + RXELECIDLEMODE, + RXGEARBOXSLIP, + RXLPMEN, + RXLPMHFHOLD, + RXLPMHFOVRDEN, + RXLPMLFHOLD, + RXLPMLFKLOVRDEN, + RXMCOMMAALIGNEN, + RXMONITORSEL, + RXOOBRESET, + RXOSCALRESET, + RXOSHOLD, + RXOSINTCFG, + RXOSINTEN, + RXOSINTHOLD, + RXOSINTID0, + RXOSINTNTRLEN, + RXOSINTOVRDEN, + RXOSINTSTROBE, + RXOSINTTESTOVRDEN, + RXOSOVRDEN, + RXOUTCLKSEL, + RXPCOMMAALIGNEN, + RXPCSRESET, + RXPD, + RXPHALIGN, + RXPHALIGNEN, + RXPHDLYPD, + RXPHDLYRESET, + RXPHOVRDEN, + RXPMARESET, + RXPOLARITY, + RXPRBSCNTRESET, + RXPRBSSEL, + RXQPIEN, + RXRATE, + RXRATEMODE, + RXSLIDE, + RXSYNCALLIN, + RXSYNCIN, + RXSYNCMODE, + RXSYSCLKSEL, + RXUSERRDY, + RXUSRCLK, + RXUSRCLK2, + SETERRSTATUS, + SIGVALIDCLK, + TSTIN, + TX8B10BBYPASS, + TX8B10BEN, + TXBUFDIFFCTRL, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCOMINIT, + TXCOMSAS, + TXCOMWAKE, + TXDATA, + TXDEEMPH, + TXDETECTRX, + TXDIFFCTRL, + TXDIFFPD, + TXDLYBYPASS, + TXDLYEN, + TXDLYHOLD, + TXDLYOVRDEN, + TXDLYSRESET, + TXDLYUPDOWN, + TXELECIDLE, + TXHEADER, + TXINHIBIT, + TXMAINCURSOR, + TXMARGIN, + TXOUTCLKSEL, + TXPCSRESET, + TXPD, + TXPDELECIDLEMODE, + TXPHALIGN, + TXPHALIGNEN, + TXPHDLYPD, + TXPHDLYRESET, + TXPHDLYTSTCLK, + TXPHINIT, + TXPHOVRDEN, + TXPIPPMEN, + TXPIPPMOVRDEN, + TXPIPPMPD, + TXPIPPMSEL, + TXPIPPMSTEPSIZE, + TXPISOPD, + TXPMARESET, + TXPOLARITY, + TXPOSTCURSOR, + TXPOSTCURSORINV, + TXPRBSFORCEERR, + TXPRBSSEL, + TXPRECURSOR, + TXPRECURSORINV, + TXQPIBIASEN, + TXQPISTRONGPDOWN, + TXQPIWEAKPUP, + TXRATE, + TXRATEMODE, + TXSEQUENCE, + TXSTARTSEQ, + TXSWING, + TXSYNCALLIN, + TXSYNCIN, + TXSYNCMODE, + TXSYSCLKSEL, + TXUSERRDY, + TXUSRCLK, + TXUSRCLK2 +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'h00C10; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [41:0] CFOK_CFG = 42'h24800040E80; + parameter [5:0] CFOK_CFG2 = 6'b100000; + parameter [5:0] CFOK_CFG3 = 6'b100000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [28:0] CPLL_CFG = 29'h00BC07DC; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "TRUE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000; + parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [14:0] PMA_RSV4 = 15'b000000000001000; + parameter [3:0] PMA_RSV5 = 4'b0000; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000; + parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] RXPI_CFG0 = 2'b00; + parameter [1:0] RXPI_CFG1 = 2'b00; + parameter [1:0] RXPI_CFG2 = 2'b00; + parameter [1:0] RXPI_CFG3 = 2'b00; + parameter [0:0] RXPI_CFG4 = 1'b0; + parameter [0:0] RXPI_CFG5 = 1'b0; + parameter [2:0] RXPI_CFG6 = 3'b100; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010; + parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000; + parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0; + parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000; + parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000; + parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000; + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0080; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F; + parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0000010000000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.1"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b100; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTREFCLKMONITOR; + output PHYSTATUS; + output RSOSINTDONE; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDFESLIDETAPSTARTED; + output RXDFESLIDETAPSTROBEDONE; + output RXDFESLIDETAPSTROBESTARTED; + output RXDFESTADAPTDONE; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXHEADERVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [5:0] RXHEADER; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFESLIDETAPADAPTEN; + input RXDFESLIDETAPHOLD; + input RXDFESLIDETAPINITOVRDEN; + input RXDFESLIDETAPONLYADAPTEN; + input RXDFESLIDETAPOVRDEN; + input RXDFESLIDETAPSTROBE; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + input RXUSRCLK2; + input RXUSRCLK; + input SETERRSTATUS; + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + input TXUSRCLK2; + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] RXDFEAGCTRL; + input [4:0] RXDFESLIDETAP; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [5:0] RXDFESLIDETAPID; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; + + reg SIM_RECEIVER_DETECT_PASS_BINARY; + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] ACJTAG_DEBUG_MODE_BINARY; + reg [0:0] ACJTAG_MODE_BINARY; + reg [0:0] ACJTAG_RESET_BINARY; + reg [0:0] ALIGN_COMMA_DOUBLE_BINARY; + reg [0:0] ALIGN_MCOMMA_DET_BINARY; + reg [0:0] ALIGN_PCOMMA_DET_BINARY; + reg [0:0] A_RXOSCALRESET_BINARY; + reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY; + reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY; + reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY; + reg [0:0] CLK_CORRECT_USE_BINARY; + reg [0:0] CLK_COR_KEEP_IDLE_BINARY; + reg [0:0] CLK_COR_PRECEDENCE_BINARY; + reg [0:0] CLK_COR_SEQ_2_USE_BINARY; + reg [0:0] CPLL_FBDIV_45_BINARY; + reg [0:0] DEC_MCOMMA_DETECT_BINARY; + reg [0:0] DEC_PCOMMA_DETECT_BINARY; + reg [0:0] DEC_VALID_COMMA_ONLY_BINARY; + reg [0:0] ES_CLK_PHASE_SEL_BINARY; + reg [0:0] ES_ERRDET_EN_BINARY; + reg [0:0] ES_EYE_SCAN_EN_BINARY; + reg [0:0] FTS_LANE_DESKEW_EN_BINARY; + reg [0:0] LOOPBACK_CFG_BINARY; + reg [0:0] PCS_PCIE_EN_BINARY; + reg [0:0] RESET_POWERSAVE_DISABLE_BINARY; + reg [0:0] RXBUF_ADDR_MODE_BINARY; + reg [0:0] RXBUF_EN_BINARY; + reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY; + reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY; + reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY; + reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] RXBUF_THRESH_OVRD_BINARY; + reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY; + reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY; + reg [0:0] RXGEARBOX_EN_BINARY; + reg [0:0] RXOOB_CLK_CFG_BINARY; + reg [0:0] RXPI_CFG4_BINARY; + reg [0:0] RXPI_CFG5_BINARY; + reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY; + reg [0:0] RXSYNC_MULTILANE_BINARY; + reg [0:0] RXSYNC_OVRD_BINARY; + reg [0:0] RXSYNC_SKIP_DA_BINARY; + reg [0:0] RX_CLKMUX_PD_BINARY; + reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY; + reg [0:0] RX_DFELPM_CFG1_BINARY; + reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_BINARY; + reg [0:0] RX_DFE_AGC_OVRDEN_BINARY; + reg [0:0] RX_DFE_KL_LPM_KH_OVRDEN_BINARY; + reg [0:0] RX_DFE_KL_LPM_KL_OVRDEN_BINARY; + reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY; + reg [0:0] RX_INT_DATAWIDTH_BINARY; + reg [0:0] RX_XCLK_SEL_BINARY; + reg [0:0] SHOW_REALIGN_COMMA_BINARY; + reg [0:0] TXBUF_EN_BINARY; + reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] TXGEARBOX_EN_BINARY; + reg [0:0] TXOOB_CFG_BINARY; + reg [0:0] TXPI_CFG3_BINARY; + reg [0:0] TXPI_CFG4_BINARY; + reg [0:0] TXPI_GREY_SEL_BINARY; + reg [0:0] TXPI_INVSTROBE_SEL_BINARY; + reg [0:0] TXPI_PPMCLK_SEL_BINARY; + reg [0:0] TXSYNC_MULTILANE_BINARY; + reg [0:0] TXSYNC_OVRD_BINARY; + reg [0:0] TXSYNC_SKIP_DA_BINARY; + reg [0:0] TX_CLKMUX_PD_BINARY; + reg [0:0] TX_INT_DATAWIDTH_BINARY; + reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY; + reg [0:0] TX_MAINCURSOR_SEL_BINARY; + reg [0:0] TX_QPI_STATUS_EN_BINARY; + reg [0:0] TX_XCLK_SEL_BINARY; + reg [0:0] UCODEER_CLR_BINARY; + reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY; + reg [10:0] RX_DFE_H4_CFG_BINARY; + reg [10:0] RX_DFE_H5_CFG_BINARY; + reg [10:0] RX_DFE_H6_CFG_BINARY; + reg [10:0] RX_DFE_H7_CFG_BINARY; + reg [11:0] RX_DFE_H2_CFG_BINARY; + reg [11:0] RX_DFE_H3_CFG_BINARY; + reg [12:0] RX_OS_CFG_BINARY; + reg [13:0] RXLPM_HF_CFG_BINARY; + reg [13:0] RX_DEBUG_CFG_BINARY; + reg [14:0] PMA_RSV4_BINARY; + reg [14:0] TERM_RCAL_CFG_BINARY; + reg [16:0] RX_DFE_UT_CFG_BINARY; + reg [16:0] RX_DFE_VP_CFG_BINARY; + reg [17:0] RXLPM_LF_CFG_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_BINARY; + reg [1:0] CLK_COR_SEQ_LEN_BINARY; + reg [1:0] OUTREFCLK_SEL_INV_BINARY; + reg [1:0] PMA_RSV3_BINARY; + reg [1:0] RXPI_CFG0_BINARY; + reg [1:0] RXPI_CFG1_BINARY; + reg [1:0] RXPI_CFG2_BINARY; + reg [1:0] RXPI_CFG3_BINARY; + reg [1:0] RXSLIDE_MODE_BINARY; + reg [1:0] RX_CM_SEL_BINARY; + reg [1:0] RX_DFE_AGC_CFG0_BINARY; + reg [1:0] RX_DFE_KL_LPM_KH_CFG0_BINARY; + reg [1:0] RX_DFE_KL_LPM_KL_CFG0_BINARY; + reg [1:0] SATA_CPLL_CFG_BINARY; + reg [1:0] TXPI_CFG0_BINARY; + reg [1:0] TXPI_CFG1_BINARY; + reg [1:0] TXPI_CFG2_BINARY; + reg [23:0] RX_BIAS_CFG_BINARY; + reg [2:0] ALIGN_COMMA_WORD_BINARY; + reg [2:0] GEARBOX_MODE_BINARY; + reg [2:0] RXOUT_DIV_BINARY; + reg [2:0] RXPI_CFG6_BINARY; + reg [2:0] RX_DATA_WIDTH_BINARY; + reg [2:0] RX_DFE_AGC_CFG1_BINARY; + reg [2:0] RX_DFE_KL_LPM_KH_CFG1_BINARY; + reg [2:0] RX_DFE_KL_LPM_KL_CFG1_BINARY; + reg [2:0] SATA_BURST_VAL_BINARY; + reg [2:0] SATA_EIDLE_VAL_BINARY; + reg [2:0] SIM_CPLLREFCLK_SEL_BINARY; + reg [2:0] TERM_RCAL_OVRD_BINARY; + reg [2:0] TXOUT_DIV_BINARY; + reg [2:0] TXPI_CFG5_BINARY; + reg [2:0] TXPI_SYNFREQ_PPM_BINARY; + reg [2:0] TX_DATA_WIDTH_BINARY; + reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY; + reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY; + reg [2:0] TX_RXDETECT_REF_BINARY; + reg [31:0] PMA_RSV2_BINARY; + reg [31:0] PMA_RSV_BINARY; + reg [32:0] RX_DFE_KL_CFG_BINARY; + reg [3:0] CHAN_BOND_MAX_SKEW_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY; + reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY; + reg [3:0] FTS_LANE_DESKEW_CFG_BINARY; + reg [3:0] PMA_RSV5_BINARY; + reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY; + reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY; + reg [3:0] RXSLIDE_AUTO_WAIT_BINARY; + reg [3:0] RX_CM_TRIM_BINARY; + reg [3:0] RX_DFELPM_CFG0_BINARY; + reg [3:0] RX_DFE_AGC_CFG2_BINARY; + reg [3:0] RX_DFE_KL_LPM_KH_CFG2_BINARY; + reg [3:0] RX_DFE_KL_LPM_KL_CFG2_BINARY; + reg [3:0] SATA_BURST_SEQ_LEN_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_BINARY; + reg [4:0] CPLL_REFCLK_DIV_BINARY; + reg [4:0] ES_PRESCALE_BINARY; + reg [4:0] RXBUFRESET_TIME_BINARY; + reg [4:0] RXCDRFREQRESET_TIME_BINARY; + reg [4:0] RXCDRPHRESET_TIME_BINARY; + reg [4:0] RXISCANRESET_TIME_BINARY; + reg [4:0] RXOSCALRESET_TIMEOUT_BINARY; + reg [4:0] RXOSCALRESET_TIME_BINARY; + reg [4:0] RXPCSRESET_TIME_BINARY; + reg [4:0] RXPH_MONITOR_SEL_BINARY; + reg [4:0] RXPMARESET_TIME_BINARY; + reg [4:0] RX_CLK25_DIV_BINARY; + reg [4:0] RX_SIG_VALID_DLY_BINARY; + reg [4:0] TXPCSRESET_TIME_BINARY; + reg [4:0] TXPH_MONITOR_SEL_BINARY; + reg [4:0] TXPMARESET_TIME_BINARY; + reg [4:0] TX_CLK25_DIV_BINARY; + reg [4:0] TX_DRIVE_MODE_BINARY; + reg [5:0] CFOK_CFG2_BINARY; + reg [5:0] CFOK_CFG3_BINARY; + reg [5:0] CLK_COR_MAX_LAT_BINARY; + reg [5:0] CLK_COR_MIN_LAT_BINARY; + reg [5:0] ES_CONTROL_BINARY; + reg [5:0] RXBUF_THRESH_OVFLW_BINARY; + reg [5:0] RXBUF_THRESH_UNDFLW_BINARY; + reg [5:0] RXCDR_LOCK_CFG_BINARY; + reg [5:0] RX_BUFFER_CFG_BINARY; + reg [5:0] RX_DDI_SEL_BINARY; + reg [5:0] SAS_MIN_COM_BINARY; + reg [5:0] SATA_MAX_BURST_BINARY; + reg [5:0] SATA_MAX_INIT_BINARY; + reg [5:0] SATA_MAX_WAKE_BINARY; + reg [5:0] SATA_MIN_BURST_BINARY; + reg [5:0] SATA_MIN_INIT_BINARY; + reg [5:0] SATA_MIN_WAKE_BINARY; + reg [5:0] TX_DEEMPH0_BINARY; + reg [5:0] TX_DEEMPH1_BINARY; + reg [6:0] CPLL_FBDIV_BINARY; + reg [6:0] RXDFELPMRESET_TIME_BINARY; + reg [6:0] RXOOB_CFG_BINARY; + reg [6:0] SAS_MAX_COM_BINARY; + reg [6:0] TX_MARGIN_FULL_0_BINARY; + reg [6:0] TX_MARGIN_FULL_1_BINARY; + reg [6:0] TX_MARGIN_FULL_2_BINARY; + reg [6:0] TX_MARGIN_FULL_3_BINARY; + reg [6:0] TX_MARGIN_FULL_4_BINARY; + reg [6:0] TX_MARGIN_LOW_0_BINARY; + reg [6:0] TX_MARGIN_LOW_1_BINARY; + reg [6:0] TX_MARGIN_LOW_2_BINARY; + reg [6:0] TX_MARGIN_LOW_3_BINARY; + reg [6:0] TX_MARGIN_LOW_4_BINARY; + reg [7:0] TXPI_PPM_CFG_BINARY; + reg [8:0] ES_VERT_OFFSET_BINARY; + reg [9:0] ALIGN_COMMA_ENABLE_BINARY; + reg [9:0] ALIGN_MCOMMA_VALUE_BINARY; + reg [9:0] ALIGN_PCOMMA_VALUE_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_BINARY; + reg [9:0] ES_PMA_CFG_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (ALIGN_COMMA_DOUBLE) + "FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0; + "TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE); + #1 $finish; + end + endcase + + case (ALIGN_COMMA_WORD) + 1 : ALIGN_COMMA_WORD_BINARY = 3'b001; + 2 : ALIGN_COMMA_WORD_BINARY = 3'b010; + 4 : ALIGN_COMMA_WORD_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", ALIGN_COMMA_WORD, 1); + #1 $finish; + end + endcase + + case (ALIGN_MCOMMA_DET) + "TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET); + #1 $finish; + end + endcase + + case (ALIGN_PCOMMA_DET) + "TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET); + #1 $finish; + end + endcase + + case (CBCC_DATA_SOURCE_SEL) + "DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1; + "ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL); + #1 $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN) + "FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE) + "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN) + 1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (CLK_CORRECT_USE) + "TRUE" : CLK_CORRECT_USE_BINARY = 1'b1; + "FALSE" : CLK_CORRECT_USE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE); + #1 $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE) + "FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE); + #1 $finish; + end + endcase + + case (CLK_COR_PRECEDENCE) + "TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1; + "FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE) + "FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_LEN) + 1 : CLK_COR_SEQ_LEN_BINARY = 2'b00; + 2 : CLK_COR_SEQ_LEN_BINARY = 2'b01; + 3 : CLK_COR_SEQ_LEN_BINARY = 2'b10; + 4 : CLK_COR_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (CPLL_FBDIV) + 4 : CPLL_FBDIV_BINARY = 7'b0000010; + 1 : CPLL_FBDIV_BINARY = 7'b0010000; + 2 : CPLL_FBDIV_BINARY = 7'b0000000; + 3 : CPLL_FBDIV_BINARY = 7'b0000001; + 5 : CPLL_FBDIV_BINARY = 7'b0000011; + 6 : CPLL_FBDIV_BINARY = 7'b0000101; + 8 : CPLL_FBDIV_BINARY = 7'b0000110; + 10 : CPLL_FBDIV_BINARY = 7'b0000111; + 12 : CPLL_FBDIV_BINARY = 7'b0001101; + 16 : CPLL_FBDIV_BINARY = 7'b0001110; + 20 : CPLL_FBDIV_BINARY = 7'b0001111; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_FBDIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_FBDIV, 4); + #1 $finish; + end + endcase + + case (CPLL_FBDIV_45) + 5 : CPLL_FBDIV_45_BINARY = 1'b1; + 4 : CPLL_FBDIV_45_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_FBDIV_45 on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 4 to 5.", CPLL_FBDIV_45, 5); + #1 $finish; + end + endcase + + case (CPLL_REFCLK_DIV) + 1 : CPLL_REFCLK_DIV_BINARY = 5'b10000; + 2 : CPLL_REFCLK_DIV_BINARY = 5'b00000; + 3 : CPLL_REFCLK_DIV_BINARY = 5'b00001; + 4 : CPLL_REFCLK_DIV_BINARY = 5'b00010; + 5 : CPLL_REFCLK_DIV_BINARY = 5'b00011; + 6 : CPLL_REFCLK_DIV_BINARY = 5'b00101; + 8 : CPLL_REFCLK_DIV_BINARY = 5'b00110; + 10 : CPLL_REFCLK_DIV_BINARY = 5'b00111; + 12 : CPLL_REFCLK_DIV_BINARY = 5'b01101; + 16 : CPLL_REFCLK_DIV_BINARY = 5'b01110; + 20 : CPLL_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_REFCLK_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_REFCLK_DIV, 1); + #1 $finish; + end + endcase + + case (DEC_MCOMMA_DETECT) + "TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_PCOMMA_DETECT) + "TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY) + "TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1; + "FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY); + #1 $finish; + end + endcase + + case (ES_ERRDET_EN) + "FALSE" : ES_ERRDET_EN_BINARY = 1'b0; + "TRUE" : ES_ERRDET_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN); + #1 $finish; + end + endcase + + case (ES_EYE_SCAN_EN) + "TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1; + "FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ES_EYE_SCAN_EN); + #1 $finish; + end + endcase + + case (FTS_LANE_DESKEW_EN) + "FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0; + "TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN); + #1 $finish; + end + endcase + + case (PCS_PCIE_EN) + "FALSE" : PCS_PCIE_EN_BINARY = 1'b0; + "TRUE" : PCS_PCIE_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN); + #1 $finish; + end + endcase + + case (RXBUF_ADDR_MODE) + "FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0; + "FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE); + #1 $finish; + end + endcase + + case (RXBUF_EN) + "TRUE" : RXBUF_EN_BINARY = 1'b1; + "FALSE" : RXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_CB_CHANGE) + "TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_COMMAALIGN) + "FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_EIDLE) + "FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_RATE_CHANGE) + "TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_THRESH_OVRD) + "FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0; + "TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD); + #1 $finish; + end + endcase + + case (RXGEARBOX_EN) + "FALSE" : RXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : RXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN); + #1 $finish; + end + endcase + + case (RXOOB_CLK_CFG) + "PMA" : RXOOB_CLK_CFG_BINARY = 1'b0; + "FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG); + #1 $finish; + end + endcase + + case (RXOUT_DIV) + 2 : RXOUT_DIV_BINARY = 3'b001; + 1 : RXOUT_DIV_BINARY = 3'b000; + 4 : RXOUT_DIV_BINARY = 3'b010; + 8 : RXOUT_DIV_BINARY = 3'b011; + 16 : RXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute RXOUT_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (RXSLIDE_MODE) + "OFF" : RXSLIDE_MODE_BINARY = 2'b00; + "AUTO" : RXSLIDE_MODE_BINARY = 2'b01; + "PCS" : RXSLIDE_MODE_BINARY = 2'b10; + "PMA" : RXSLIDE_MODE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE); + #1 $finish; + end + endcase + + case (RX_CLK25_DIV) + 7 : RX_CLK25_DIV_BINARY = 5'b00110; + 1 : RX_CLK25_DIV_BINARY = 5'b00000; + 2 : RX_CLK25_DIV_BINARY = 5'b00001; + 3 : RX_CLK25_DIV_BINARY = 5'b00010; + 4 : RX_CLK25_DIV_BINARY = 5'b00011; + 5 : RX_CLK25_DIV_BINARY = 5'b00100; + 6 : RX_CLK25_DIV_BINARY = 5'b00101; + 8 : RX_CLK25_DIV_BINARY = 5'b00111; + 9 : RX_CLK25_DIV_BINARY = 5'b01000; + 10 : RX_CLK25_DIV_BINARY = 5'b01001; + 11 : RX_CLK25_DIV_BINARY = 5'b01010; + 12 : RX_CLK25_DIV_BINARY = 5'b01011; + 13 : RX_CLK25_DIV_BINARY = 5'b01100; + 14 : RX_CLK25_DIV_BINARY = 5'b01101; + 15 : RX_CLK25_DIV_BINARY = 5'b01110; + 16 : RX_CLK25_DIV_BINARY = 5'b01111; + 17 : RX_CLK25_DIV_BINARY = 5'b10000; + 18 : RX_CLK25_DIV_BINARY = 5'b10001; + 19 : RX_CLK25_DIV_BINARY = 5'b10010; + 20 : RX_CLK25_DIV_BINARY = 5'b10011; + 21 : RX_CLK25_DIV_BINARY = 5'b10100; + 22 : RX_CLK25_DIV_BINARY = 5'b10101; + 23 : RX_CLK25_DIV_BINARY = 5'b10110; + 24 : RX_CLK25_DIV_BINARY = 5'b10111; + 25 : RX_CLK25_DIV_BINARY = 5'b11000; + 26 : RX_CLK25_DIV_BINARY = 5'b11001; + 27 : RX_CLK25_DIV_BINARY = 5'b11010; + 28 : RX_CLK25_DIV_BINARY = 5'b11011; + 29 : RX_CLK25_DIV_BINARY = 5'b11100; + 30 : RX_CLK25_DIV_BINARY = 5'b11101; + 31 : RX_CLK25_DIV_BINARY = 5'b11110; + 32 : RX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (RX_DATA_WIDTH) + 20 : RX_DATA_WIDTH_BINARY = 3'b011; + 16 : RX_DATA_WIDTH_BINARY = 3'b010; + 32 : RX_DATA_WIDTH_BINARY = 3'b100; + 40 : RX_DATA_WIDTH_BINARY = 3'b101; + 64 : RX_DATA_WIDTH_BINARY = 3'b110; + 80 : RX_DATA_WIDTH_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", RX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (RX_DEFER_RESET_BUF_EN) + "TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1; + "FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN); + #1 $finish; + end + endcase + + case (RX_DISPERR_SEQ_MATCH) + "TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1; + "FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH); + #1 $finish; + end + endcase + + case (RX_SIG_VALID_DLY) + 10 : RX_SIG_VALID_DLY_BINARY = 5'b01001; + 1 : RX_SIG_VALID_DLY_BINARY = 5'b00000; + 2 : RX_SIG_VALID_DLY_BINARY = 5'b00001; + 3 : RX_SIG_VALID_DLY_BINARY = 5'b00010; + 4 : RX_SIG_VALID_DLY_BINARY = 5'b00011; + 5 : RX_SIG_VALID_DLY_BINARY = 5'b00100; + 6 : RX_SIG_VALID_DLY_BINARY = 5'b00101; + 7 : RX_SIG_VALID_DLY_BINARY = 5'b00110; + 8 : RX_SIG_VALID_DLY_BINARY = 5'b00111; + 9 : RX_SIG_VALID_DLY_BINARY = 5'b01000; + 11 : RX_SIG_VALID_DLY_BINARY = 5'b01010; + 12 : RX_SIG_VALID_DLY_BINARY = 5'b01011; + 13 : RX_SIG_VALID_DLY_BINARY = 5'b01100; + 14 : RX_SIG_VALID_DLY_BINARY = 5'b01101; + 15 : RX_SIG_VALID_DLY_BINARY = 5'b01110; + 16 : RX_SIG_VALID_DLY_BINARY = 5'b01111; + 17 : RX_SIG_VALID_DLY_BINARY = 5'b10000; + 18 : RX_SIG_VALID_DLY_BINARY = 5'b10001; + 19 : RX_SIG_VALID_DLY_BINARY = 5'b10010; + 20 : RX_SIG_VALID_DLY_BINARY = 5'b10011; + 21 : RX_SIG_VALID_DLY_BINARY = 5'b10100; + 22 : RX_SIG_VALID_DLY_BINARY = 5'b10101; + 23 : RX_SIG_VALID_DLY_BINARY = 5'b10110; + 24 : RX_SIG_VALID_DLY_BINARY = 5'b10111; + 25 : RX_SIG_VALID_DLY_BINARY = 5'b11000; + 26 : RX_SIG_VALID_DLY_BINARY = 5'b11001; + 27 : RX_SIG_VALID_DLY_BINARY = 5'b11010; + 28 : RX_SIG_VALID_DLY_BINARY = 5'b11011; + 29 : RX_SIG_VALID_DLY_BINARY = 5'b11100; + 30 : RX_SIG_VALID_DLY_BINARY = 5'b11101; + 31 : RX_SIG_VALID_DLY_BINARY = 5'b11110; + 32 : RX_SIG_VALID_DLY_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10); + #1 $finish; + end + endcase + + case (RX_XCLK_SEL) + "RXREC" : RX_XCLK_SEL_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL); + #1 $finish; + end + endcase + + case (SATA_CPLL_CFG) + "VCO_3000MHZ" : SATA_CPLL_CFG_BINARY = 2'b00; + "VCO_750MHZ" : SATA_CPLL_CFG_BINARY = 2'b10; + "VCO_1500MHZ" : SATA_CPLL_CFG_BINARY = 2'b01; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_CPLL_CFG on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_CPLL_CFG); + #1 $finish; + end + endcase + + case (SHOW_REALIGN_COMMA) + "TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1; + "FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA); + #1 $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS) + "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + "FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + + case (SIM_TX_EIDLE_DRIVE_LEVEL) + "X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL); + #1 $finish; + end + endcase + + + case (SIM_VERSION) + "1.1" : SIM_VERSION_BINARY = 0; + "1.0" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.1, 1.0, or 2.0.", SIM_VERSION); + #1 $finish; + end +endcase + + case (TXBUF_EN) + "TRUE" : TXBUF_EN_BINARY = 1'b1; + "FALSE" : TXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN); + #1 $finish; + end + endcase + + case (TXBUF_RESET_ON_RATE_CHANGE) + "FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + "TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (TXGEARBOX_EN) + "FALSE" : TXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : TXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN); + #1 $finish; + end + endcase + + case (TXOUT_DIV) + 2 : TXOUT_DIV_BINARY = 3'b001; + 1 : TXOUT_DIV_BINARY = 3'b000; + 4 : TXOUT_DIV_BINARY = 3'b010; + 8 : TXOUT_DIV_BINARY = 3'b011; + 16 : TXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUT_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (TXPI_PPMCLK_SEL) + "TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1; + "TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL); + #1 $finish; + end + endcase + + case (TX_CLK25_DIV) + 7 : TX_CLK25_DIV_BINARY = 5'b00110; + 1 : TX_CLK25_DIV_BINARY = 5'b00000; + 2 : TX_CLK25_DIV_BINARY = 5'b00001; + 3 : TX_CLK25_DIV_BINARY = 5'b00010; + 4 : TX_CLK25_DIV_BINARY = 5'b00011; + 5 : TX_CLK25_DIV_BINARY = 5'b00100; + 6 : TX_CLK25_DIV_BINARY = 5'b00101; + 8 : TX_CLK25_DIV_BINARY = 5'b00111; + 9 : TX_CLK25_DIV_BINARY = 5'b01000; + 10 : TX_CLK25_DIV_BINARY = 5'b01001; + 11 : TX_CLK25_DIV_BINARY = 5'b01010; + 12 : TX_CLK25_DIV_BINARY = 5'b01011; + 13 : TX_CLK25_DIV_BINARY = 5'b01100; + 14 : TX_CLK25_DIV_BINARY = 5'b01101; + 15 : TX_CLK25_DIV_BINARY = 5'b01110; + 16 : TX_CLK25_DIV_BINARY = 5'b01111; + 17 : TX_CLK25_DIV_BINARY = 5'b10000; + 18 : TX_CLK25_DIV_BINARY = 5'b10001; + 19 : TX_CLK25_DIV_BINARY = 5'b10010; + 20 : TX_CLK25_DIV_BINARY = 5'b10011; + 21 : TX_CLK25_DIV_BINARY = 5'b10100; + 22 : TX_CLK25_DIV_BINARY = 5'b10101; + 23 : TX_CLK25_DIV_BINARY = 5'b10110; + 24 : TX_CLK25_DIV_BINARY = 5'b10111; + 25 : TX_CLK25_DIV_BINARY = 5'b11000; + 26 : TX_CLK25_DIV_BINARY = 5'b11001; + 27 : TX_CLK25_DIV_BINARY = 5'b11010; + 28 : TX_CLK25_DIV_BINARY = 5'b11011; + 29 : TX_CLK25_DIV_BINARY = 5'b11100; + 30 : TX_CLK25_DIV_BINARY = 5'b11101; + 31 : TX_CLK25_DIV_BINARY = 5'b11110; + 32 : TX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (TX_DATA_WIDTH) + 20 : TX_DATA_WIDTH_BINARY = 3'b011; + 16 : TX_DATA_WIDTH_BINARY = 3'b010; + 32 : TX_DATA_WIDTH_BINARY = 3'b100; + 40 : TX_DATA_WIDTH_BINARY = 3'b101; + 64 : TX_DATA_WIDTH_BINARY = 3'b110; + 80 : TX_DATA_WIDTH_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", TX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (TX_DRIVE_MODE) + "DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000; + "PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001; + "PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE); + #1 $finish; + end + endcase + + case (TX_LOOPBACK_DRIVE_HIZ) + "FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0; + "TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ); + #1 $finish; + end + endcase + + case (TX_XCLK_SEL) + "TXUSR" : TX_XCLK_SEL_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL); + #1 $finish; + end + endcase + + if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1)) + ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE); + #1 $finish; + end + + if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1)) + ACJTAG_MODE_BINARY = ACJTAG_MODE; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE); + #1 $finish; + end + + if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1)) + ACJTAG_RESET_BINARY = ACJTAG_RESET; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_RESET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET); + #1 $finish; + end + + if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111)) + ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE); + #1 $finish; + end + + if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111)) + ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE); + #1 $finish; + end + + if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111)) + ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE); + #1 $finish; + end + + if ((A_RXOSCALRESET >= 1'b0) && (A_RXOSCALRESET <= 1'b1)) + A_RXOSCALRESET_BINARY = A_RXOSCALRESET; + else begin + $display("Attribute Syntax Error : The Attribute A_RXOSCALRESET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", A_RXOSCALRESET); + #1 $finish; + end + + if ((CFOK_CFG2 >= 6'b000000) && (CFOK_CFG2 <= 6'b111111)) + CFOK_CFG2_BINARY = CFOK_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", CFOK_CFG2); + #1 $finish; + end + + if ((CFOK_CFG3 >= 6'b000000) && (CFOK_CFG3 <= 6'b111111)) + CFOK_CFG3_BINARY = CFOK_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", CFOK_CFG3); + #1 $finish; + end + + if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14)) + CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE); + #1 $finish; + end + + if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60)) + CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT); + #1 $finish; + end + + if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60)) + CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT); + #1 $finish; + end + + if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31)) + CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111)) + CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111)) + CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111)) + CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111)) + CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111)) + CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111)) + CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111)) + CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111)) + CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111)) + CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111)) + CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE); + #1 $finish; + end + + if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1)) + ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL); + #1 $finish; + end + + if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111)) + ES_CONTROL_BINARY = ES_CONTROL; + else begin + $display("Attribute Syntax Error : The Attribute ES_CONTROL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL); + #1 $finish; + end + + if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111)) + ES_PMA_CFG_BINARY = ES_PMA_CFG; + else begin + $display("Attribute Syntax Error : The Attribute ES_PMA_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG); + #1 $finish; + end + + if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111)) + ES_PRESCALE_BINARY = ES_PRESCALE; + else begin + $display("Attribute Syntax Error : The Attribute ES_PRESCALE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE); + #1 $finish; + end + + if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111)) + ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET; + else begin + $display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET); + #1 $finish; + end + + if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111)) + FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE); + #1 $finish; + end + + if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111)) + FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG; + else begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG); + #1 $finish; + end + + if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111)) + GEARBOX_MODE_BINARY = GEARBOX_MODE; + else begin + $display("Attribute Syntax Error : The Attribute GEARBOX_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE); + #1 $finish; + end + + if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1)) + LOOPBACK_CFG_BINARY = LOOPBACK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG); + #1 $finish; + end + + if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11)) + OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV; + else begin + $display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV); + #1 $finish; + end + + if ((PMA_RSV >= 32'b00000000000000000000000000000000) && (PMA_RSV <= 32'b11111111111111111111111111111111)) + PMA_RSV_BINARY = PMA_RSV; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 32'b00000000000000000000000000000000 to 32'b11111111111111111111111111111111.", PMA_RSV); + #1 $finish; + end + + if ((PMA_RSV2 >= 32'b00000000000000000000000000000000) && (PMA_RSV2 <= 32'b11111111111111111111111111111111)) + PMA_RSV2_BINARY = PMA_RSV2; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 32'b00000000000000000000000000000000 to 32'b11111111111111111111111111111111.", PMA_RSV2); + #1 $finish; + end + + if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11)) + PMA_RSV3_BINARY = PMA_RSV3; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3); + #1 $finish; + end + + if ((PMA_RSV4 >= 15'b000000000000000) && (PMA_RSV4 <= 15'b111111111111111)) + PMA_RSV4_BINARY = PMA_RSV4; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", PMA_RSV4); + #1 $finish; + end + + if ((PMA_RSV5 >= 4'b0000) && (PMA_RSV5 <= 4'b1111)) + PMA_RSV5_BINARY = PMA_RSV5; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV5); + #1 $finish; + end + + if ((RESET_POWERSAVE_DISABLE >= 1'b0) && (RESET_POWERSAVE_DISABLE <= 1'b1)) + RESET_POWERSAVE_DISABLE_BINARY = RESET_POWERSAVE_DISABLE; + else begin + $display("Attribute Syntax Error : The Attribute RESET_POWERSAVE_DISABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RESET_POWERSAVE_DISABLE); + #1 $finish; + end + + if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111)) + RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME); + #1 $finish; + end + + if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111)) + RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT); + #1 $finish; + end + + if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111)) + RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT); + #1 $finish; + end + + if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63)) + RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW); + #1 $finish; + end + + if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63)) + RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW); + #1 $finish; + end + + if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111)) + RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME); + #1 $finish; + end + + if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111)) + RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME); + #1 $finish; + end + + if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1)) + RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1)) + RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111)) + RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG); + #1 $finish; + end + + if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1)) + RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXDFELPMRESET_TIME >= 7'b0000000) && (RXDFELPMRESET_TIME <= 7'b1111111)) + RXDFELPMRESET_TIME_BINARY = RXDFELPMRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXDFELPMRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXDFELPMRESET_TIME); + #1 $finish; + end + + if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111)) + RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME); + #1 $finish; + end + + if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111)) + RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG); + #1 $finish; + end + + if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111)) + RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG); + #1 $finish; + end + + if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111)) + RXOOB_CFG_BINARY = RXOOB_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXOOB_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG); + #1 $finish; + end + + if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111)) + RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME); + #1 $finish; + end + + if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111)) + RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT; + else begin + $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT); + #1 $finish; + end + + if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111)) + RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME); + #1 $finish; + end + + if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111)) + RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL); + #1 $finish; + end + + if ((RXPI_CFG0 >= 2'b00) && (RXPI_CFG0 <= 2'b11)) + RXPI_CFG0_BINARY = RXPI_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG0); + #1 $finish; + end + + if ((RXPI_CFG1 >= 2'b00) && (RXPI_CFG1 <= 2'b11)) + RXPI_CFG1_BINARY = RXPI_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG1); + #1 $finish; + end + + if ((RXPI_CFG2 >= 2'b00) && (RXPI_CFG2 <= 2'b11)) + RXPI_CFG2_BINARY = RXPI_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG2); + #1 $finish; + end + + if ((RXPI_CFG3 >= 2'b00) && (RXPI_CFG3 <= 2'b11)) + RXPI_CFG3_BINARY = RXPI_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG3); + #1 $finish; + end + + if ((RXPI_CFG4 >= 1'b0) && (RXPI_CFG4 <= 1'b1)) + RXPI_CFG4_BINARY = RXPI_CFG4; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG4); + #1 $finish; + end + + if ((RXPI_CFG5 >= 1'b0) && (RXPI_CFG5 <= 1'b1)) + RXPI_CFG5_BINARY = RXPI_CFG5; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG5); + #1 $finish; + end + + if ((RXPI_CFG6 >= 3'b000) && (RXPI_CFG6 <= 3'b111)) + RXPI_CFG6_BINARY = RXPI_CFG6; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG6 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG6); + #1 $finish; + end + + if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111)) + RXPMARESET_TIME_BINARY = RXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME); + #1 $finish; + end + + if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1)) + RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK); + #1 $finish; + end + + if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15)) + RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT); + #1 $finish; + end + + if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1)) + RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE); + #1 $finish; + end + + if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1)) + RXSYNC_OVRD_BINARY = RXSYNC_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD); + #1 $finish; + end + + if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1)) + RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA); + #1 $finish; + end + + if ((RX_BIAS_CFG >= 24'b000000000000000000000000) && (RX_BIAS_CFG <= 24'b111111111111111111111111)) + RX_BIAS_CFG_BINARY = RX_BIAS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 24'b000000000000000000000000 to 24'b111111111111111111111111.", RX_BIAS_CFG); + #1 $finish; + end + + if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111)) + RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG); + #1 $finish; + end + + if ((RX_CLKMUX_PD >= 1'b0) && (RX_CLKMUX_PD <= 1'b1)) + RX_CLKMUX_PD_BINARY = RX_CLKMUX_PD; + else begin + $display("Attribute Syntax Error : The Attribute RX_CLKMUX_PD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_PD); + #1 $finish; + end + + if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11)) + RX_CM_SEL_BINARY = RX_CM_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL); + #1 $finish; + end + + if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111)) + RX_CM_TRIM_BINARY = RX_CM_TRIM; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_TRIM on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM); + #1 $finish; + end + + if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111)) + RX_DDI_SEL_BINARY = RX_DDI_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_DDI_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL); + #1 $finish; + end + + if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111)) + RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG); + #1 $finish; + end + + if ((RX_DFELPM_CFG0 >= 4'b0000) && (RX_DFELPM_CFG0 <= 4'b1111)) + RX_DFELPM_CFG0_BINARY = RX_DFELPM_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFELPM_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFELPM_CFG0); + #1 $finish; + end + + if ((RX_DFELPM_CFG1 >= 1'b0) && (RX_DFELPM_CFG1 <= 1'b1)) + RX_DFELPM_CFG1_BINARY = RX_DFELPM_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFELPM_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFELPM_CFG1); + #1 $finish; + end + + if ((RX_DFELPM_KLKH_AGC_STUP_EN >= 1'b0) && (RX_DFELPM_KLKH_AGC_STUP_EN <= 1'b1)) + RX_DFELPM_KLKH_AGC_STUP_EN_BINARY = RX_DFELPM_KLKH_AGC_STUP_EN; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFELPM_KLKH_AGC_STUP_EN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFELPM_KLKH_AGC_STUP_EN); + #1 $finish; + end + + if ((RX_DFE_AGC_CFG0 >= 2'b00) && (RX_DFE_AGC_CFG0 <= 2'b11)) + RX_DFE_AGC_CFG0_BINARY = RX_DFE_AGC_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_AGC_CFG0); + #1 $finish; + end + + if ((RX_DFE_AGC_CFG1 >= 3'b000) && (RX_DFE_AGC_CFG1 <= 3'b111)) + RX_DFE_AGC_CFG1_BINARY = RX_DFE_AGC_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_AGC_CFG1); + #1 $finish; + end + + if ((RX_DFE_AGC_CFG2 >= 4'b0000) && (RX_DFE_AGC_CFG2 <= 4'b1111)) + RX_DFE_AGC_CFG2_BINARY = RX_DFE_AGC_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_AGC_CFG2); + #1 $finish; + end + + if ((RX_DFE_AGC_OVRDEN >= 1'b0) && (RX_DFE_AGC_OVRDEN <= 1'b1)) + RX_DFE_AGC_OVRDEN_BINARY = RX_DFE_AGC_OVRDEN; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_AGC_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_AGC_OVRDEN); + #1 $finish; + end + + if ((RX_DFE_H2_CFG >= 12'b000000000000) && (RX_DFE_H2_CFG <= 12'b111111111111)) + RX_DFE_H2_CFG_BINARY = RX_DFE_H2_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H2_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H2_CFG); + #1 $finish; + end + + if ((RX_DFE_H3_CFG >= 12'b000000000000) && (RX_DFE_H3_CFG <= 12'b111111111111)) + RX_DFE_H3_CFG_BINARY = RX_DFE_H3_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H3_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H3_CFG); + #1 $finish; + end + + if ((RX_DFE_H4_CFG >= 11'b00000000000) && (RX_DFE_H4_CFG <= 11'b11111111111)) + RX_DFE_H4_CFG_BINARY = RX_DFE_H4_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H4_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H4_CFG); + #1 $finish; + end + + if ((RX_DFE_H5_CFG >= 11'b00000000000) && (RX_DFE_H5_CFG <= 11'b11111111111)) + RX_DFE_H5_CFG_BINARY = RX_DFE_H5_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H5_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H5_CFG); + #1 $finish; + end + + if ((RX_DFE_H6_CFG >= 11'b00000000000) && (RX_DFE_H6_CFG <= 11'b11111111111)) + RX_DFE_H6_CFG_BINARY = RX_DFE_H6_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H6_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H6_CFG); + #1 $finish; + end + + if ((RX_DFE_H7_CFG >= 11'b00000000000) && (RX_DFE_H7_CFG <= 11'b11111111111)) + RX_DFE_H7_CFG_BINARY = RX_DFE_H7_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H7_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H7_CFG); + #1 $finish; + end + + if ((RX_DFE_KL_CFG >= 33'b000000000000000000000000000000000) && (RX_DFE_KL_CFG <= 33'b111111111111111111111111111111111)) + RX_DFE_KL_CFG_BINARY = RX_DFE_KL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 33'b000000000000000000000000000000000 to 33'b111111111111111111111111111111111.", RX_DFE_KL_CFG); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KH_CFG0 >= 2'b00) && (RX_DFE_KL_LPM_KH_CFG0 <= 2'b11)) + RX_DFE_KL_LPM_KH_CFG0_BINARY = RX_DFE_KL_LPM_KH_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_KL_LPM_KH_CFG0); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KH_CFG1 >= 3'b000) && (RX_DFE_KL_LPM_KH_CFG1 <= 3'b111)) + RX_DFE_KL_LPM_KH_CFG1_BINARY = RX_DFE_KL_LPM_KH_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_KL_LPM_KH_CFG1); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KH_CFG2 >= 4'b0000) && (RX_DFE_KL_LPM_KH_CFG2 <= 4'b1111)) + RX_DFE_KL_LPM_KH_CFG2_BINARY = RX_DFE_KL_LPM_KH_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_KL_LPM_KH_CFG2); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KH_OVRDEN >= 1'b0) && (RX_DFE_KL_LPM_KH_OVRDEN <= 1'b1)) + RX_DFE_KL_LPM_KH_OVRDEN_BINARY = RX_DFE_KL_LPM_KH_OVRDEN; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_KL_LPM_KH_OVRDEN); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KL_CFG0 >= 2'b00) && (RX_DFE_KL_LPM_KL_CFG0 <= 2'b11)) + RX_DFE_KL_LPM_KL_CFG0_BINARY = RX_DFE_KL_LPM_KL_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_KL_LPM_KL_CFG0); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KL_CFG1 >= 3'b000) && (RX_DFE_KL_LPM_KL_CFG1 <= 3'b111)) + RX_DFE_KL_LPM_KL_CFG1_BINARY = RX_DFE_KL_LPM_KL_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_KL_LPM_KL_CFG1); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KL_CFG2 >= 4'b0000) && (RX_DFE_KL_LPM_KL_CFG2 <= 4'b1111)) + RX_DFE_KL_LPM_KL_CFG2_BINARY = RX_DFE_KL_LPM_KL_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_KL_LPM_KL_CFG2); + #1 $finish; + end + + if ((RX_DFE_KL_LPM_KL_OVRDEN >= 1'b0) && (RX_DFE_KL_LPM_KL_OVRDEN <= 1'b1)) + RX_DFE_KL_LPM_KL_OVRDEN_BINARY = RX_DFE_KL_LPM_KL_OVRDEN; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_KL_LPM_KL_OVRDEN); + #1 $finish; + end + + if ((RX_DFE_LPM_HOLD_DURING_EIDLE >= 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE <= 1'b1)) + RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY = RX_DFE_LPM_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_LPM_HOLD_DURING_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_LPM_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RX_DFE_UT_CFG >= 17'b00000000000000000) && (RX_DFE_UT_CFG <= 17'b11111111111111111)) + RX_DFE_UT_CFG_BINARY = RX_DFE_UT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_UT_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_UT_CFG); + #1 $finish; + end + + if ((RX_DFE_VP_CFG >= 17'b00000000000000000) && (RX_DFE_VP_CFG <= 17'b11111111111111111)) + RX_DFE_VP_CFG_BINARY = RX_DFE_VP_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_VP_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_VP_CFG); + #1 $finish; + end + + if ((RX_INT_DATAWIDTH >= 0) && (RX_INT_DATAWIDTH <= 1)) + RX_INT_DATAWIDTH_BINARY = RX_INT_DATAWIDTH; + else begin + $display("Attribute Syntax Error : The Attribute RX_INT_DATAWIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", RX_INT_DATAWIDTH); + #1 $finish; + end + + if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111)) + RX_OS_CFG_BINARY = RX_OS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_OS_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG); + #1 $finish; + end + + if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127)) + SAS_MAX_COM_BINARY = SAS_MAX_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MAX_COM on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM); + #1 $finish; + end + + if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63)) + SAS_MIN_COM_BINARY = SAS_MIN_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MIN_COM on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM); + #1 $finish; + end + + if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111)) + SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN); + #1 $finish; + end + + if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111)) + SATA_BURST_VAL_BINARY = SATA_BURST_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL); + #1 $finish; + end + + if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111)) + SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL); + #1 $finish; + end + + if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63)) + SATA_MAX_BURST_BINARY = SATA_MAX_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST); + #1 $finish; + end + + if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63)) + SATA_MAX_INIT_BINARY = SATA_MAX_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT); + #1 $finish; + end + + if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63)) + SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE); + #1 $finish; + end + + if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61)) + SATA_MIN_BURST_BINARY = SATA_MIN_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST); + #1 $finish; + end + + if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63)) + SATA_MIN_INIT_BINARY = SATA_MIN_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT); + #1 $finish; + end + + if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63)) + SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE); + #1 $finish; + end + + if ((SIM_CPLLREFCLK_SEL >= 3'b0) && (SIM_CPLLREFCLK_SEL <= 3'b111)) + SIM_CPLLREFCLK_SEL_BINARY = SIM_CPLLREFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_CPLLREFCLK_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_CPLLREFCLK_SEL); + #1 $finish; + end + + if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111)) + TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG); + #1 $finish; + end + + if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111)) + TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD); + #1 $finish; + end + + if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1)) + TXOOB_CFG_BINARY = TXOOB_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TXOOB_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG); + #1 $finish; + end + + if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111)) + TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME); + #1 $finish; + end + + if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111)) + TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL); + #1 $finish; + end + + if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11)) + TXPI_CFG0_BINARY = TXPI_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0); + #1 $finish; + end + + if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11)) + TXPI_CFG1_BINARY = TXPI_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1); + #1 $finish; + end + + if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11)) + TXPI_CFG2_BINARY = TXPI_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2); + #1 $finish; + end + + if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1)) + TXPI_CFG3_BINARY = TXPI_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3); + #1 $finish; + end + + if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1)) + TXPI_CFG4_BINARY = TXPI_CFG4; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4); + #1 $finish; + end + + if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111)) + TXPI_CFG5_BINARY = TXPI_CFG5; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5); + #1 $finish; + end + + if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1)) + TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL); + #1 $finish; + end + + if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1)) + TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL); + #1 $finish; + end + + if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111)) + TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG); + #1 $finish; + end + + if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111)) + TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM); + #1 $finish; + end + + if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111)) + TXPMARESET_TIME_BINARY = TXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME); + #1 $finish; + end + + if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1)) + TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE); + #1 $finish; + end + + if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1)) + TXSYNC_OVRD_BINARY = TXSYNC_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD); + #1 $finish; + end + + if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1)) + TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA); + #1 $finish; + end + + if ((TX_CLKMUX_PD >= 1'b0) && (TX_CLKMUX_PD <= 1'b1)) + TX_CLKMUX_PD_BINARY = TX_CLKMUX_PD; + else begin + $display("Attribute Syntax Error : The Attribute TX_CLKMUX_PD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_PD); + #1 $finish; + end + + if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111)) + TX_DEEMPH0_BINARY = TX_DEEMPH0; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0); + #1 $finish; + end + + if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111)) + TX_DEEMPH1_BINARY = TX_DEEMPH1; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1); + #1 $finish; + end + + if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111)) + TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY); + #1 $finish; + end + + if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111)) + TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY); + #1 $finish; + end + + if ((TX_INT_DATAWIDTH >= 0) && (TX_INT_DATAWIDTH <= 1)) + TX_INT_DATAWIDTH_BINARY = TX_INT_DATAWIDTH; + else begin + $display("Attribute Syntax Error : The Attribute TX_INT_DATAWIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", TX_INT_DATAWIDTH); + #1 $finish; + end + + if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1)) + TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL); + #1 $finish; + end + + if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111)) + TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0); + #1 $finish; + end + + if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111)) + TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1); + #1 $finish; + end + + if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111)) + TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2); + #1 $finish; + end + + if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111)) + TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3); + #1 $finish; + end + + if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111)) + TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4); + #1 $finish; + end + + if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111)) + TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0); + #1 $finish; + end + + if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111)) + TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1); + #1 $finish; + end + + if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111)) + TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2); + #1 $finish; + end + + if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111)) + TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3); + #1 $finish; + end + + if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111)) + TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4); + #1 $finish; + end + + if ((TX_QPI_STATUS_EN >= 1'b0) && (TX_QPI_STATUS_EN <= 1'b1)) + TX_QPI_STATUS_EN_BINARY = TX_QPI_STATUS_EN; + else begin + $display("Attribute Syntax Error : The Attribute TX_QPI_STATUS_EN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_QPI_STATUS_EN); + #1 $finish; + end + + if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111)) + TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF; + else begin + $display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF); + #1 $finish; + end + + if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1)) + UCODEER_CLR_BINARY = UCODEER_CLR; + else begin + $display("Attribute Syntax Error : The Attribute UCODEER_CLR on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR); + #1 $finish; + end + + if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1)) + USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL); + #1 $finish; + end + + end + + wire [14:0] delay_DMONITOROUT; + wire [15:0] delay_DRPDO; + wire [15:0] delay_PCSRSVDOUT; + wire [1:0] delay_RXCLKCORCNT; + wire [1:0] delay_RXDATAVALID; + wire [1:0] delay_RXHEADERVALID; + wire [1:0] delay_RXSTARTOFSEQ; + wire [1:0] delay_TXBUFSTATUS; + wire [2:0] delay_RXBUFSTATUS; + wire [2:0] delay_RXSTATUS; + wire [4:0] delay_RXCHBONDO; + wire [4:0] delay_RXPHMONITOR; + wire [4:0] delay_RXPHSLIPMONITOR; + wire [5:0] delay_RXHEADER; + wire [63:0] delay_RXDATA; + wire [6:0] delay_RXMONITOROUT; + wire [7:0] delay_RXCHARISCOMMA; + wire [7:0] delay_RXCHARISK; + wire [7:0] delay_RXDISPERR; + wire [7:0] delay_RXNOTINTABLE; + wire delay_CPLLFBCLKLOST; + wire delay_CPLLLOCK; + wire delay_CPLLREFCLKLOST; + wire delay_DRPRDY; + wire delay_EYESCANDATAERROR; + wire delay_GTHTXN; + wire delay_GTHTXP; + wire delay_GTREFCLKMONITOR; + wire delay_PHYSTATUS; + wire delay_RSOSINTDONE; + wire delay_RXBYTEISALIGNED; + wire delay_RXBYTEREALIGN; + wire delay_RXCDRLOCK; + wire delay_RXCHANBONDSEQ; + wire delay_RXCHANISALIGNED; + wire delay_RXCHANREALIGN; + wire delay_RXCOMINITDET; + wire delay_RXCOMMADET; + wire delay_RXCOMSASDET; + wire delay_RXCOMWAKEDET; + wire delay_RXDFESLIDETAPSTARTED; + wire delay_RXDFESLIDETAPSTROBEDONE; + wire delay_RXDFESLIDETAPSTROBESTARTED; + wire delay_RXDFESTADAPTDONE; + wire delay_RXDLYSRESETDONE; + wire delay_RXELECIDLE; + wire delay_RXOSINTSTARTED; + wire delay_RXOSINTSTROBEDONE; + wire delay_RXOSINTSTROBESTARTED; + wire delay_RXOUTCLK; + wire delay_RXOUTCLKFABRIC; + wire delay_RXOUTCLKPCS; + wire delay_RXPHALIGNDONE; + wire delay_RXPMARESETDONE; + wire delay_RXPRBSERR; + wire delay_RXQPISENN; + wire delay_RXQPISENP; + wire delay_RXRATEDONE; + wire delay_RXRESETDONE; + wire delay_RXSYNCDONE; + wire delay_RXSYNCOUT; + wire delay_RXVALID; + wire delay_TXCOMFINISH; + wire delay_TXDLYSRESETDONE; + wire delay_TXGEARBOXREADY; + wire delay_TXOUTCLK; + wire delay_TXOUTCLKFABRIC; + wire delay_TXOUTCLKPCS; + wire delay_TXPHALIGNDONE; + wire delay_TXPHINITDONE; + wire delay_TXPMARESETDONE; + wire delay_TXQPISENN; + wire delay_TXQPISENP; + wire delay_TXRATEDONE; + wire delay_TXRESETDONE; + wire delay_TXSYNCDONE; + wire delay_TXSYNCOUT; + + wire [13:0] delay_RXADAPTSELTEST; + wire [15:0] delay_DRPDI; + wire [15:0] delay_GTRSVD; + wire [15:0] delay_PCSRSVDIN; + wire [19:0] delay_TSTIN; + wire [1:0] delay_RXELECIDLEMODE; + wire [1:0] delay_RXMONITORSEL; + wire [1:0] delay_RXPD; + wire [1:0] delay_RXSYSCLKSEL; + wire [1:0] delay_TXPD; + wire [1:0] delay_TXSYSCLKSEL; + wire [2:0] delay_CPLLREFCLKSEL; + wire [2:0] delay_LOOPBACK; + wire [2:0] delay_RXCHBONDLEVEL; + wire [2:0] delay_RXOUTCLKSEL; + wire [2:0] delay_RXPRBSSEL; + wire [2:0] delay_RXRATE; + wire [2:0] delay_TXBUFDIFFCTRL; + wire [2:0] delay_TXHEADER; + wire [2:0] delay_TXMARGIN; + wire [2:0] delay_TXOUTCLKSEL; + wire [2:0] delay_TXPRBSSEL; + wire [2:0] delay_TXRATE; + wire [3:0] delay_RXOSINTCFG; + wire [3:0] delay_RXOSINTID0; + wire [3:0] delay_TXDIFFCTRL; + wire [4:0] delay_PCSRSVDIN2; + wire [4:0] delay_PMARSVDIN; + wire [4:0] delay_RXCHBONDI; + wire [4:0] delay_RXDFEAGCTRL; + wire [4:0] delay_RXDFESLIDETAP; + wire [4:0] delay_TXPIPPMSTEPSIZE; + wire [4:0] delay_TXPOSTCURSOR; + wire [4:0] delay_TXPRECURSOR; + wire [5:0] delay_RXDFESLIDETAPID; + wire [63:0] delay_TXDATA; + wire [6:0] delay_TXMAINCURSOR; + wire [6:0] delay_TXSEQUENCE; + wire [7:0] delay_TX8B10BBYPASS; + wire [7:0] delay_TXCHARDISPMODE; + wire [7:0] delay_TXCHARDISPVAL; + wire [7:0] delay_TXCHARISK; + wire [8:0] delay_DRPADDR; + wire delay_CFGRESET; + wire delay_CLKRSVD0; + wire delay_CLKRSVD1; + wire delay_CPLLLOCKDETCLK; + wire delay_CPLLLOCKEN; + wire delay_CPLLPD; + wire delay_CPLLRESET; + wire delay_DMONFIFORESET; + wire delay_DMONITORCLK; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_EYESCANMODE; + wire delay_EYESCANRESET; + wire delay_EYESCANTRIGGER; + wire delay_GTGREFCLK; + wire delay_GTHRXN; + wire delay_GTHRXP; + wire delay_GTNORTHREFCLK0; + wire delay_GTNORTHREFCLK1; + wire delay_GTREFCLK0; + wire delay_GTREFCLK1; + wire delay_GTRESETSEL; + wire delay_GTRXRESET; + wire delay_GTSOUTHREFCLK0; + wire delay_GTSOUTHREFCLK1; + wire delay_GTTXRESET; + wire delay_QPLLCLK; + wire delay_QPLLREFCLK; + wire delay_RESETOVRD; + wire delay_RX8B10BEN; + wire delay_RXBUFRESET; + wire delay_RXCDRFREQRESET; + wire delay_RXCDRHOLD; + wire delay_RXCDROVRDEN; + wire delay_RXCDRRESET; + wire delay_RXCDRRESETRSV; + wire delay_RXCHBONDEN; + wire delay_RXCHBONDMASTER; + wire delay_RXCHBONDSLAVE; + wire delay_RXCOMMADETEN; + wire delay_RXDDIEN; + wire delay_RXDFEAGCHOLD; + wire delay_RXDFEAGCOVRDEN; + wire delay_RXDFECM1EN; + wire delay_RXDFELFHOLD; + wire delay_RXDFELFOVRDEN; + wire delay_RXDFELPMRESET; + wire delay_RXDFESLIDETAPADAPTEN; + wire delay_RXDFESLIDETAPHOLD; + wire delay_RXDFESLIDETAPINITOVRDEN; + wire delay_RXDFESLIDETAPONLYADAPTEN; + wire delay_RXDFESLIDETAPOVRDEN; + wire delay_RXDFESLIDETAPSTROBE; + wire delay_RXDFETAP2HOLD; + wire delay_RXDFETAP2OVRDEN; + wire delay_RXDFETAP3HOLD; + wire delay_RXDFETAP3OVRDEN; + wire delay_RXDFETAP4HOLD; + wire delay_RXDFETAP4OVRDEN; + wire delay_RXDFETAP5HOLD; + wire delay_RXDFETAP5OVRDEN; + wire delay_RXDFETAP6HOLD; + wire delay_RXDFETAP6OVRDEN; + wire delay_RXDFETAP7HOLD; + wire delay_RXDFETAP7OVRDEN; + wire delay_RXDFEUTHOLD; + wire delay_RXDFEUTOVRDEN; + wire delay_RXDFEVPHOLD; + wire delay_RXDFEVPOVRDEN; + wire delay_RXDFEVSEN; + wire delay_RXDFEXYDEN; + wire delay_RXDLYBYPASS; + wire delay_RXDLYEN; + wire delay_RXDLYOVRDEN; + wire delay_RXDLYSRESET; + wire delay_RXGEARBOXSLIP; + wire delay_RXLPMEN; + wire delay_RXLPMHFHOLD; + wire delay_RXLPMHFOVRDEN; + wire delay_RXLPMLFHOLD; + wire delay_RXLPMLFKLOVRDEN; + wire delay_RXMCOMMAALIGNEN; + wire delay_RXOOBRESET; + wire delay_RXOSCALRESET; + wire delay_RXOSHOLD; + wire delay_RXOSINTEN; + wire delay_RXOSINTHOLD; + wire delay_RXOSINTNTRLEN; + wire delay_RXOSINTOVRDEN; + wire delay_RXOSINTSTROBE; + wire delay_RXOSINTTESTOVRDEN; + wire delay_RXOSOVRDEN; + wire delay_RXPCOMMAALIGNEN; + wire delay_RXPCSRESET; + wire delay_RXPHALIGN; + wire delay_RXPHALIGNEN; + wire delay_RXPHDLYPD; + wire delay_RXPHDLYRESET; + wire delay_RXPHOVRDEN; + wire delay_RXPMARESET; + wire delay_RXPOLARITY; + wire delay_RXPRBSCNTRESET; + wire delay_RXQPIEN; + wire delay_RXRATEMODE; + wire delay_RXSLIDE; + wire delay_RXSYNCALLIN; + wire delay_RXSYNCIN; + wire delay_RXSYNCMODE; + wire delay_RXUSERRDY; + wire delay_RXUSRCLK2; + wire delay_RXUSRCLK; + wire delay_SETERRSTATUS; + wire delay_SIGVALIDCLK; + wire delay_TX8B10BEN; + wire delay_TXCOMINIT; + wire delay_TXCOMSAS; + wire delay_TXCOMWAKE; + wire delay_TXDEEMPH; + wire delay_TXDETECTRX; + wire delay_TXDIFFPD; + wire delay_TXDLYBYPASS; + wire delay_TXDLYEN; + wire delay_TXDLYHOLD; + wire delay_TXDLYOVRDEN; + wire delay_TXDLYSRESET; + wire delay_TXDLYUPDOWN; + wire delay_TXELECIDLE; + wire delay_TXINHIBIT; + wire delay_TXPCSRESET; + wire delay_TXPDELECIDLEMODE; + wire delay_TXPHALIGN; + wire delay_TXPHALIGNEN; + wire delay_TXPHDLYPD; + wire delay_TXPHDLYRESET; + wire delay_TXPHDLYTSTCLK; + wire delay_TXPHINIT; + wire delay_TXPHOVRDEN; + wire delay_TXPIPPMEN; + wire delay_TXPIPPMOVRDEN; + wire delay_TXPIPPMPD; + wire delay_TXPIPPMSEL; + wire delay_TXPISOPD; + wire delay_TXPMARESET; + wire delay_TXPOLARITY; + wire delay_TXPOSTCURSORINV; + wire delay_TXPRBSFORCEERR; + wire delay_TXPRECURSORINV; + wire delay_TXQPIBIASEN; + wire delay_TXQPISTRONGPDOWN; + wire delay_TXQPIWEAKPUP; + wire delay_TXRATEMODE; + wire delay_TXSTARTSEQ; + wire delay_TXSWING; + wire delay_TXSYNCALLIN; + wire delay_TXSYNCIN; + wire delay_TXSYNCMODE; + wire delay_TXUSERRDY; + wire delay_TXUSRCLK2; + wire delay_TXUSRCLK; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + + reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED; + reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED; + reg [0:0] IS_CPLLLOCKDETCLK_INVERTED_REG = IS_CPLLLOCKDETCLK_INVERTED; + reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED; + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED; + reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED; + reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED; + reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED; + reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED; + reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED; + reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED; + + + assign GTREFCLKMONITOR = delay_GTREFCLKMONITOR; + assign RXOUTCLK = delay_RXOUTCLK; + assign TXOUTCLK = delay_TXOUTCLK; + + assign CPLLFBCLKLOST = delay_CPLLFBCLKLOST; + assign CPLLLOCK = delay_CPLLLOCK; + assign CPLLREFCLKLOST = delay_CPLLREFCLKLOST; + assign DMONITOROUT = delay_DMONITOROUT; + assign DRPDO = delay_DRPDO; + assign DRPRDY = delay_DRPRDY; + assign EYESCANDATAERROR = delay_EYESCANDATAERROR; + assign GTHTXN = delay_GTHTXN; + assign GTHTXP = delay_GTHTXP; + assign PCSRSVDOUT = delay_PCSRSVDOUT; + assign PHYSTATUS = delay_PHYSTATUS; + assign RSOSINTDONE = delay_RSOSINTDONE; + assign RXBUFSTATUS = delay_RXBUFSTATUS; + assign RXBYTEISALIGNED = delay_RXBYTEISALIGNED; + assign RXBYTEREALIGN = delay_RXBYTEREALIGN; + assign RXCDRLOCK = delay_RXCDRLOCK; + assign RXCHANBONDSEQ = delay_RXCHANBONDSEQ; + assign RXCHANISALIGNED = delay_RXCHANISALIGNED; + assign RXCHANREALIGN = delay_RXCHANREALIGN; + assign RXCHARISCOMMA = delay_RXCHARISCOMMA; + assign RXCHARISK = delay_RXCHARISK; + assign RXCHBONDO = delay_RXCHBONDO; + assign RXCLKCORCNT = delay_RXCLKCORCNT; + assign RXCOMINITDET = delay_RXCOMINITDET; + assign RXCOMMADET = delay_RXCOMMADET; + assign RXCOMSASDET = delay_RXCOMSASDET; + assign RXCOMWAKEDET = delay_RXCOMWAKEDET; + assign RXDATA = delay_RXDATA; + assign RXDATAVALID = delay_RXDATAVALID; + assign RXDFESLIDETAPSTARTED = delay_RXDFESLIDETAPSTARTED; + assign RXDFESLIDETAPSTROBEDONE = delay_RXDFESLIDETAPSTROBEDONE; + assign RXDFESLIDETAPSTROBESTARTED = delay_RXDFESLIDETAPSTROBESTARTED; + assign RXDFESTADAPTDONE = delay_RXDFESTADAPTDONE; + assign RXDISPERR = delay_RXDISPERR; + assign RXDLYSRESETDONE = delay_RXDLYSRESETDONE; + assign RXELECIDLE = delay_RXELECIDLE; + assign RXHEADER = delay_RXHEADER; + assign RXHEADERVALID = delay_RXHEADERVALID; + assign RXMONITOROUT = delay_RXMONITOROUT; + assign RXNOTINTABLE = delay_RXNOTINTABLE; + assign RXOSINTSTARTED = delay_RXOSINTSTARTED; + assign RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE; + assign RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED; + assign RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC; + assign RXOUTCLKPCS = delay_RXOUTCLKPCS; + assign RXPHALIGNDONE = delay_RXPHALIGNDONE; + assign RXPHMONITOR = delay_RXPHMONITOR; + assign RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR; + assign RXPMARESETDONE = delay_RXPMARESETDONE; + assign RXPRBSERR = delay_RXPRBSERR; + assign RXQPISENN = delay_RXQPISENN; + assign RXQPISENP = delay_RXQPISENP; + assign RXRATEDONE = delay_RXRATEDONE; + assign RXRESETDONE = delay_RXRESETDONE; + assign RXSTARTOFSEQ = delay_RXSTARTOFSEQ; + assign RXSTATUS = delay_RXSTATUS; + assign RXSYNCDONE = delay_RXSYNCDONE; + assign RXSYNCOUT = delay_RXSYNCOUT; + assign RXVALID = delay_RXVALID; + assign TXBUFSTATUS = delay_TXBUFSTATUS; + assign TXCOMFINISH = delay_TXCOMFINISH; + assign TXDLYSRESETDONE = delay_TXDLYSRESETDONE; + assign TXGEARBOXREADY = delay_TXGEARBOXREADY; + assign TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC; + assign TXOUTCLKPCS = delay_TXOUTCLKPCS; + assign TXPHALIGNDONE = delay_TXPHALIGNDONE; + assign TXPHINITDONE = delay_TXPHINITDONE; + assign TXPMARESETDONE = delay_TXPMARESETDONE; + assign TXQPISENN = delay_TXQPISENN; + assign TXQPISENP = delay_TXQPISENP; + assign TXRATEDONE = delay_TXRATEDONE; + assign TXRESETDONE = delay_TXRESETDONE; + assign TXSYNCDONE = delay_TXSYNCDONE; + assign TXSYNCOUT = delay_TXSYNCOUT; + +`ifndef XIL_TIMING // unisim + assign delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG; + assign delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG; + assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK; + assign delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG; + assign delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_QPLLCLK = QPLLCLK; + assign delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK_INVERTED_REG; + assign delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG; + assign delay_SIGVALIDCLK = SIGVALIDCLK ^ IS_SIGVALIDCLK_INVERTED_REG; + assign delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG; + assign delay_TXUSRCLK = TXUSRCLK ^ IS_TXUSRCLK_INVERTED_REG; + assign delay_TXUSRCLK2 = TXUSRCLK2 ^ IS_TXUSRCLK2_INVERTED_REG; + + assign delay_CFGRESET = CFGRESET; + assign delay_CPLLLOCKEN = CPLLLOCKEN; + assign delay_CPLLPD = CPLLPD; + assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL; + assign delay_CPLLRESET = CPLLRESET; + assign delay_DMONFIFORESET = DMONFIFORESET; + assign delay_DRPADDR = DRPADDR; + assign delay_DRPDI = DRPDI; + assign delay_DRPEN = DRPEN; + assign delay_DRPWE = DRPWE; + assign delay_EYESCANMODE = EYESCANMODE; + assign delay_EYESCANRESET = EYESCANRESET; + assign delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign delay_GTHRXN = GTHRXN; + assign delay_GTHRXP = GTHRXP; + assign delay_GTRESETSEL = GTRESETSEL; + assign delay_GTRSVD = GTRSVD; + assign delay_GTRXRESET = GTRXRESET; + assign delay_GTTXRESET = GTTXRESET; + assign delay_LOOPBACK = LOOPBACK; + assign delay_PCSRSVDIN = PCSRSVDIN; + assign delay_PCSRSVDIN2 = PCSRSVDIN2; + assign delay_PMARSVDIN = PMARSVDIN; + assign delay_QPLLREFCLK = QPLLREFCLK; + assign delay_RESETOVRD = RESETOVRD; + assign delay_RX8B10BEN = RX8B10BEN; + assign delay_RXADAPTSELTEST = RXADAPTSELTEST; + assign delay_RXBUFRESET = RXBUFRESET; + assign delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign delay_RXCDRHOLD = RXCDRHOLD; + assign delay_RXCDROVRDEN = RXCDROVRDEN; + assign delay_RXCDRRESET = RXCDRRESET; + assign delay_RXCDRRESETRSV = RXCDRRESETRSV; + assign delay_RXCHBONDEN = RXCHBONDEN; + assign delay_RXCHBONDI = RXCHBONDI; + assign delay_RXCHBONDLEVEL = RXCHBONDLEVEL; + assign delay_RXCHBONDMASTER = RXCHBONDMASTER; + assign delay_RXCHBONDSLAVE = RXCHBONDSLAVE; + assign delay_RXCOMMADETEN = RXCOMMADETEN; + assign delay_RXDDIEN = RXDDIEN; + assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD; + assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN; + assign delay_RXDFEAGCTRL = RXDFEAGCTRL; + assign delay_RXDFECM1EN = RXDFECM1EN; + assign delay_RXDFELFHOLD = RXDFELFHOLD; + assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN; + assign delay_RXDFELPMRESET = RXDFELPMRESET; + assign delay_RXDFESLIDETAP = RXDFESLIDETAP; + assign delay_RXDFESLIDETAPADAPTEN = RXDFESLIDETAPADAPTEN; + assign delay_RXDFESLIDETAPHOLD = RXDFESLIDETAPHOLD; + assign delay_RXDFESLIDETAPID = RXDFESLIDETAPID; + assign delay_RXDFESLIDETAPINITOVRDEN = RXDFESLIDETAPINITOVRDEN; + assign delay_RXDFESLIDETAPONLYADAPTEN = RXDFESLIDETAPONLYADAPTEN; + assign delay_RXDFESLIDETAPOVRDEN = RXDFESLIDETAPOVRDEN; + assign delay_RXDFESLIDETAPSTROBE = RXDFESLIDETAPSTROBE; + assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD; + assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN; + assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD; + assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN; + assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD; + assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN; + assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD; + assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN; + assign delay_RXDFETAP6HOLD = RXDFETAP6HOLD; + assign delay_RXDFETAP6OVRDEN = RXDFETAP6OVRDEN; + assign delay_RXDFETAP7HOLD = RXDFETAP7HOLD; + assign delay_RXDFETAP7OVRDEN = RXDFETAP7OVRDEN; + assign delay_RXDFEUTHOLD = RXDFEUTHOLD; + assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN; + assign delay_RXDFEVPHOLD = RXDFEVPHOLD; + assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN; + assign delay_RXDFEVSEN = RXDFEVSEN; + assign delay_RXDFEXYDEN = RXDFEXYDEN; + assign delay_RXDLYBYPASS = RXDLYBYPASS; + assign delay_RXDLYEN = RXDLYEN; + assign delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign delay_RXDLYSRESET = RXDLYSRESET; + assign delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign delay_RXGEARBOXSLIP = RXGEARBOXSLIP; + assign delay_RXLPMEN = RXLPMEN; + assign delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN; + assign delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN; + assign delay_RXMONITORSEL = RXMONITORSEL; + assign delay_RXOOBRESET = RXOOBRESET; + assign delay_RXOSCALRESET = RXOSCALRESET; + assign delay_RXOSHOLD = RXOSHOLD; + assign delay_RXOSINTCFG = RXOSINTCFG; + assign delay_RXOSINTEN = RXOSINTEN; + assign delay_RXOSINTHOLD = RXOSINTHOLD; + assign delay_RXOSINTID0 = RXOSINTID0; + assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN; + assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN; + assign delay_RXOSINTSTROBE = RXOSINTSTROBE; + assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; + assign delay_RXOSOVRDEN = RXOSOVRDEN; + assign delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN; + assign delay_RXPCSRESET = RXPCSRESET; + assign delay_RXPD = RXPD; + assign delay_RXPHALIGN = RXPHALIGN; + assign delay_RXPHALIGNEN = RXPHALIGNEN; + assign delay_RXPHDLYPD = RXPHDLYPD; + assign delay_RXPHDLYRESET = RXPHDLYRESET; + assign delay_RXPHOVRDEN = RXPHOVRDEN; + assign delay_RXPMARESET = RXPMARESET; + assign delay_RXPOLARITY = RXPOLARITY; + assign delay_RXPRBSCNTRESET = RXPRBSCNTRESET; + assign delay_RXPRBSSEL = RXPRBSSEL; + assign delay_RXQPIEN = RXQPIEN; + assign delay_RXRATE = RXRATE; + assign delay_RXRATEMODE = RXRATEMODE; + assign delay_RXSLIDE = RXSLIDE; + assign delay_RXSYNCALLIN = RXSYNCALLIN; + assign delay_RXSYNCIN = RXSYNCIN; + assign delay_RXSYNCMODE = RXSYNCMODE; + assign delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign delay_RXUSERRDY = RXUSERRDY; + assign delay_SETERRSTATUS = SETERRSTATUS; + assign delay_TSTIN = TSTIN; + assign delay_TX8B10BBYPASS = TX8B10BBYPASS; + assign delay_TX8B10BEN = TX8B10BEN; + assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign delay_TXCHARDISPMODE = TXCHARDISPMODE; + assign delay_TXCHARDISPVAL = TXCHARDISPVAL; + assign delay_TXCHARISK = TXCHARISK; + assign delay_TXCOMINIT = TXCOMINIT; + assign delay_TXCOMSAS = TXCOMSAS; + assign delay_TXCOMWAKE = TXCOMWAKE; + assign delay_TXDATA = TXDATA; + assign delay_TXDEEMPH = TXDEEMPH; + assign delay_TXDETECTRX = TXDETECTRX; + assign delay_TXDIFFCTRL = TXDIFFCTRL; + assign delay_TXDIFFPD = TXDIFFPD; + assign delay_TXDLYBYPASS = TXDLYBYPASS; + assign delay_TXDLYEN = TXDLYEN; + assign delay_TXDLYHOLD = TXDLYHOLD; + assign delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign delay_TXDLYSRESET = TXDLYSRESET; + assign delay_TXDLYUPDOWN = TXDLYUPDOWN; + assign delay_TXELECIDLE = TXELECIDLE; + assign delay_TXHEADER = TXHEADER; + assign delay_TXINHIBIT = TXINHIBIT; + assign delay_TXMAINCURSOR = TXMAINCURSOR; + assign delay_TXMARGIN = TXMARGIN; + assign delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign delay_TXPCSRESET = TXPCSRESET; + assign delay_TXPD = TXPD; + assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign delay_TXPHALIGN = TXPHALIGN; + assign delay_TXPHALIGNEN = TXPHALIGNEN; + assign delay_TXPHDLYPD = TXPHDLYPD; + assign delay_TXPHDLYRESET = TXPHDLYRESET; + assign delay_TXPHINIT = TXPHINIT; + assign delay_TXPHOVRDEN = TXPHOVRDEN; + assign delay_TXPIPPMEN = TXPIPPMEN; + assign delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN; + assign delay_TXPIPPMPD = TXPIPPMPD; + assign delay_TXPIPPMSEL = TXPIPPMSEL; + assign delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE; + assign delay_TXPISOPD = TXPISOPD; + assign delay_TXPMARESET = TXPMARESET; + assign delay_TXPOLARITY = TXPOLARITY; + assign delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign delay_TXPRBSFORCEERR = TXPRBSFORCEERR; + assign delay_TXPRBSSEL = TXPRBSSEL; + assign delay_TXPRECURSOR = TXPRECURSOR; + assign delay_TXPRECURSORINV = TXPRECURSORINV; + assign delay_TXQPIBIASEN = TXQPIBIASEN; + assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN; + assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP; + assign delay_TXRATE = TXRATE; + assign delay_TXRATEMODE = TXRATEMODE; + assign delay_TXSEQUENCE = TXSEQUENCE; + assign delay_TXSTARTSEQ = TXSTARTSEQ; + assign delay_TXSWING = TXSWING; + assign delay_TXSYNCALLIN = TXSYNCALLIN; + assign delay_TXSYNCIN = TXSYNCIN; + assign delay_TXSYNCMODE = TXSYNCMODE; + assign delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign delay_TXUSERRDY = TXUSERRDY; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_CFGRESET = CFGRESET; + assign delay_CLKRSVD0 = CLKRSVD0; + assign delay_CLKRSVD1 = CLKRSVD1; + assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK; + assign delay_CPLLLOCKEN = CPLLLOCKEN; + assign delay_CPLLPD = CPLLPD; + assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL; + assign delay_CPLLRESET = CPLLRESET; + assign delay_DMONFIFORESET = DMONFIFORESET; + assign delay_DMONITORCLK = DMONITORCLK; + assign delay_EYESCANMODE = EYESCANMODE; + assign delay_EYESCANRESET = EYESCANRESET; + assign delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign delay_GTGREFCLK = GTGREFCLK; + assign delay_GTHRXN = GTHRXN; + assign delay_GTHRXP = GTHRXP; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTRESETSEL = GTRESETSEL; + assign delay_GTRSVD = GTRSVD; + assign delay_GTRXRESET = GTRXRESET; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_GTTXRESET = GTTXRESET; + assign delay_LOOPBACK = LOOPBACK; + assign delay_PCSRSVDIN = PCSRSVDIN; + assign delay_PCSRSVDIN2 = PCSRSVDIN2; + assign delay_PMARSVDIN = PMARSVDIN; + assign delay_QPLLCLK = QPLLCLK; + assign delay_QPLLREFCLK = QPLLREFCLK; + assign delay_RESETOVRD = RESETOVRD; + assign delay_RXADAPTSELTEST = RXADAPTSELTEST; + assign delay_RXBUFRESET = RXBUFRESET; + assign delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign delay_RXCDRHOLD = RXCDRHOLD; + assign delay_RXCDROVRDEN = RXCDROVRDEN; + assign delay_RXCDRRESET = RXCDRRESET; + assign delay_RXCDRRESETRSV = RXCDRRESETRSV; +// assign delay_RXCHBONDI = RXCHBONDI; + assign delay_RXDDIEN = RXDDIEN; + assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD; + assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN; + assign delay_RXDFEAGCTRL = RXDFEAGCTRL; + assign delay_RXDFECM1EN = RXDFECM1EN; + assign delay_RXDFELFHOLD = RXDFELFHOLD; + assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN; + assign delay_RXDFELPMRESET = RXDFELPMRESET; + assign delay_RXDFESLIDETAP = RXDFESLIDETAP; + assign delay_RXDFESLIDETAPADAPTEN = RXDFESLIDETAPADAPTEN; + assign delay_RXDFESLIDETAPHOLD = RXDFESLIDETAPHOLD; + assign delay_RXDFESLIDETAPID = RXDFESLIDETAPID; + assign delay_RXDFESLIDETAPINITOVRDEN = RXDFESLIDETAPINITOVRDEN; + assign delay_RXDFESLIDETAPONLYADAPTEN = RXDFESLIDETAPONLYADAPTEN; + assign delay_RXDFESLIDETAPOVRDEN = RXDFESLIDETAPOVRDEN; + assign delay_RXDFESLIDETAPSTROBE = RXDFESLIDETAPSTROBE; + assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD; + assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN; + assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD; + assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN; + assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD; + assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN; + assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD; + assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN; + assign delay_RXDFETAP6HOLD = RXDFETAP6HOLD; + assign delay_RXDFETAP6OVRDEN = RXDFETAP6OVRDEN; + assign delay_RXDFETAP7HOLD = RXDFETAP7HOLD; + assign delay_RXDFETAP7OVRDEN = RXDFETAP7OVRDEN; + assign delay_RXDFEUTHOLD = RXDFEUTHOLD; + assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN; + assign delay_RXDFEVPHOLD = RXDFEVPHOLD; + assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN; + assign delay_RXDFEVSEN = RXDFEVSEN; + assign delay_RXDFEXYDEN = RXDFEXYDEN; + assign delay_RXDLYBYPASS = RXDLYBYPASS; + assign delay_RXDLYEN = RXDLYEN; + assign delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign delay_RXDLYSRESET = RXDLYSRESET; + assign delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign delay_RXLPMEN = RXLPMEN; + assign delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN; + assign delay_RXMONITORSEL = RXMONITORSEL; + assign delay_RXOOBRESET = RXOOBRESET; + assign delay_RXOSCALRESET = RXOSCALRESET; + assign delay_RXOSHOLD = RXOSHOLD; + assign delay_RXOSINTCFG = RXOSINTCFG; + assign delay_RXOSINTEN = RXOSINTEN; + assign delay_RXOSINTHOLD = RXOSINTHOLD; + assign delay_RXOSINTID0 = RXOSINTID0; + assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN; + assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN; + assign delay_RXOSINTSTROBE = RXOSINTSTROBE; + assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; + assign delay_RXOSOVRDEN = RXOSOVRDEN; + assign delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign delay_RXPCSRESET = RXPCSRESET; + assign delay_RXPD = RXPD; + assign delay_RXPHALIGN = RXPHALIGN; + assign delay_RXPHALIGNEN = RXPHALIGNEN; + assign delay_RXPHDLYPD = RXPHDLYPD; + assign delay_RXPHDLYRESET = RXPHDLYRESET; + assign delay_RXPHOVRDEN = RXPHOVRDEN; + assign delay_RXPMARESET = RXPMARESET; + assign delay_RXQPIEN = RXQPIEN; + assign delay_RXRATEMODE = RXRATEMODE; + assign delay_RXSYNCALLIN = RXSYNCALLIN; + assign delay_RXSYNCIN = RXSYNCIN; + assign delay_RXSYNCMODE = RXSYNCMODE; + assign delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign delay_RXUSERRDY = RXUSERRDY; +// assign delay_RXUSRCLK = RXUSRCLK; + assign delay_SIGVALIDCLK = SIGVALIDCLK; + assign delay_TSTIN = TSTIN; + assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign delay_TXDEEMPH = TXDEEMPH; + assign delay_TXDIFFCTRL = TXDIFFCTRL; + assign delay_TXDIFFPD = TXDIFFPD; + assign delay_TXDLYBYPASS = TXDLYBYPASS; + assign delay_TXDLYEN = TXDLYEN; + assign delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign delay_TXDLYSRESET = TXDLYSRESET; + assign delay_TXMAINCURSOR = TXMAINCURSOR; + assign delay_TXMARGIN = TXMARGIN; + assign delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign delay_TXPCSRESET = TXPCSRESET; + assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign delay_TXPHALIGN = TXPHALIGN; + assign delay_TXPHALIGNEN = TXPHALIGNEN; + assign delay_TXPHDLYPD = TXPHDLYPD; + assign delay_TXPHDLYRESET = TXPHDLYRESET; + assign delay_TXPHINIT = TXPHINIT; + assign delay_TXPHOVRDEN = TXPHOVRDEN; + assign delay_TXPISOPD = TXPISOPD; + assign delay_TXPMARESET = TXPMARESET; + assign delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign delay_TXPRECURSOR = TXPRECURSOR; + assign delay_TXPRECURSORINV = TXPRECURSORINV; + assign delay_TXQPIBIASEN = TXQPIBIASEN; + assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN; + assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP; + assign delay_TXRATEMODE = TXRATEMODE; + assign delay_TXSWING = TXSWING; + assign delay_TXSYNCALLIN = TXSYNCALLIN; + assign delay_TXSYNCIN = TXSYNCIN; + assign delay_TXSYNCMODE = TXSYNCMODE; + assign delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign delay_TXUSERRDY = TXUSERRDY; + + wire drpclk_en_p; + wire drpclk_en_n; + wire rxusrclk2_en_p; + wire rxusrclk2_en_n; + wire rxusrclk_en_p; + wire rxusrclk_en_n; + wire txphdlytstclk_en_p; + wire txphdlytstclk_en_n; + wire txusrclk2_en_p; + wire txusrclk2_en_n; + wire txusrclk_en_p; + wire txusrclk_en_n; + + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; + assign rxusrclk2_en_p = ~IS_RXUSRCLK2_INVERTED; + assign rxusrclk2_en_n = IS_RXUSRCLK2_INVERTED; + assign rxusrclk_en_p = ~IS_RXUSRCLK_INVERTED; + assign rxusrclk_en_n = IS_RXUSRCLK_INVERTED; + assign txphdlytstclk_en_p = ~IS_TXPHDLYTSTCLK_INVERTED; + assign txphdlytstclk_en_n = IS_TXPHDLYTSTCLK_INVERTED; + assign txusrclk2_en_p = ~IS_TXUSRCLK2_INVERTED; + assign txusrclk2_en_n = IS_TXUSRCLK2_INVERTED; + assign txusrclk_en_p = ~IS_TXUSRCLK_INVERTED; + assign txusrclk_en_n = IS_TXUSRCLK_INVERTED; +`endif + + B_GTHE2_CHANNEL #( + .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE), + .ACJTAG_MODE (ACJTAG_MODE), + .ACJTAG_RESET (ACJTAG_RESET), + .ADAPT_CFG0 (ADAPT_CFG0), + .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE), + .A_RXOSCALRESET (A_RXOSCALRESET), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CFOK_CFG (CFOK_CFG), + .CFOK_CFG2 (CFOK_CFG2), + .CFOK_CFG3 (CFOK_CFG3), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN), + .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN), + .CLK_CORRECT_USE (CLK_CORRECT_USE), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE), + .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN), + .CPLL_CFG (CPLL_CFG), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_45), + .CPLL_INIT_CFG (CPLL_INIT_CFG), + .CPLL_LOCK_CFG (CPLL_LOCK_CFG), + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY), + .DMONITOR_CFG (DMONITOR_CFG), + .ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL), + .ES_CONTROL (ES_CONTROL), + .ES_ERRDET_EN (ES_ERRDET_EN), + .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN), + .ES_HORZ_OFFSET (ES_HORZ_OFFSET), + .ES_PMA_CFG (ES_PMA_CFG), + .ES_PRESCALE (ES_PRESCALE), + .ES_QUALIFIER (ES_QUALIFIER), + .ES_QUAL_MASK (ES_QUAL_MASK), + .ES_SDATA_MASK (ES_SDATA_MASK), + .ES_VERT_OFFSET (ES_VERT_OFFSET), + .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE), + .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG), + .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN), + .GEARBOX_MODE (GEARBOX_MODE), + .LOOPBACK_CFG (LOOPBACK_CFG), + .OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV), + .PCS_PCIE_EN (PCS_PCIE_EN), + .PCS_RSVD_ATTR (PCS_RSVD_ATTR), + .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2), + .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2), + .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2), + .PMA_RSV (PMA_RSV), + .PMA_RSV2 (PMA_RSV2), + .PMA_RSV3 (PMA_RSV3), + .PMA_RSV4 (PMA_RSV4), + .PMA_RSV5 (PMA_RSV5), + .RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE), + .RXBUFRESET_TIME (RXBUFRESET_TIME), + .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE), + .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT), + .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE), + .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN), + .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE), + .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE), + .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW), + .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME), + .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME), + .RXCDR_CFG (RXCDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE), + .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE), + .RXCDR_LOCK_CFG (RXCDR_LOCK_CFG), + .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE), + .RXDFELPMRESET_TIME (RXDFELPMRESET_TIME), + .RXDLY_CFG (RXDLY_CFG), + .RXDLY_LCFG (RXDLY_LCFG), + .RXDLY_TAP_CFG (RXDLY_TAP_CFG), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (RXISCANRESET_TIME), + .RXLPM_HF_CFG (RXLPM_HF_CFG), + .RXLPM_LF_CFG (RXLPM_LF_CFG), + .RXOOB_CFG (RXOOB_CFG), + .RXOOB_CLK_CFG (RXOOB_CLK_CFG), + .RXOSCALRESET_TIME (RXOSCALRESET_TIME), + .RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT), + .RXOUT_DIV (RXOUT_DIV), + .RXPCSRESET_TIME (RXPCSRESET_TIME), + .RXPHDLY_CFG (RXPHDLY_CFG), + .RXPH_CFG (RXPH_CFG), + .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RXPI_CFG2 (RXPI_CFG2), + .RXPI_CFG3 (RXPI_CFG3), + .RXPI_CFG4 (RXPI_CFG4), + .RXPI_CFG5 (RXPI_CFG5), + .RXPI_CFG6 (RXPI_CFG6), + .RXPMARESET_TIME (RXPMARESET_TIME), + .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK), + .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT), + .RXSLIDE_MODE (RXSLIDE_MODE), + .RXSYNC_MULTILANE (RXSYNC_MULTILANE), + .RXSYNC_OVRD (RXSYNC_OVRD), + .RXSYNC_SKIP_DA (RXSYNC_SKIP_DA), + .RX_BIAS_CFG (RX_BIAS_CFG), + .RX_BUFFER_CFG (RX_BUFFER_CFG), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_PD (RX_CLKMUX_PD), + .RX_CM_SEL (RX_CM_SEL), + .RX_CM_TRIM (RX_CM_TRIM), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (RX_DDI_SEL), + .RX_DEBUG_CFG (RX_DEBUG_CFG), + .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN), + .RX_DFELPM_CFG0 (RX_DFELPM_CFG0), + .RX_DFELPM_CFG1 (RX_DFELPM_CFG1), + .RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN), + .RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0), + .RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1), + .RX_DFE_AGC_CFG2 (RX_DFE_AGC_CFG2), + .RX_DFE_AGC_OVRDEN (RX_DFE_AGC_OVRDEN), + .RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG), + .RX_DFE_H2_CFG (RX_DFE_H2_CFG), + .RX_DFE_H3_CFG (RX_DFE_H3_CFG), + .RX_DFE_H4_CFG (RX_DFE_H4_CFG), + .RX_DFE_H5_CFG (RX_DFE_H5_CFG), + .RX_DFE_H6_CFG (RX_DFE_H6_CFG), + .RX_DFE_H7_CFG (RX_DFE_H7_CFG), + .RX_DFE_KL_CFG (RX_DFE_KL_CFG), + .RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0), + .RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1), + .RX_DFE_KL_LPM_KH_CFG2 (RX_DFE_KL_LPM_KH_CFG2), + .RX_DFE_KL_LPM_KH_OVRDEN (RX_DFE_KL_LPM_KH_OVRDEN), + .RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0), + .RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1), + .RX_DFE_KL_LPM_KL_CFG2 (RX_DFE_KL_LPM_KL_CFG2), + .RX_DFE_KL_LPM_KL_OVRDEN (RX_DFE_KL_LPM_KL_OVRDEN), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE), + .RX_DFE_ST_CFG (RX_DFE_ST_CFG), + .RX_DFE_UT_CFG (RX_DFE_UT_CFG), + .RX_DFE_VP_CFG (RX_DFE_VP_CFG), + .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), + .RX_OS_CFG (RX_OS_CFG), + .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY), + .RX_XCLK_SEL (RX_XCLK_SEL), + .SAS_MAX_COM (SAS_MAX_COM), + .SAS_MIN_COM (SAS_MIN_COM), + .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN), + .SATA_BURST_VAL (SATA_BURST_VAL), + .SATA_CPLL_CFG (SATA_CPLL_CFG), + .SATA_EIDLE_VAL (SATA_EIDLE_VAL), + .SATA_MAX_BURST (SATA_MAX_BURST), + .SATA_MAX_INIT (SATA_MAX_INIT), + .SATA_MAX_WAKE (SATA_MAX_WAKE), + .SATA_MIN_BURST (SATA_MIN_BURST), + .SATA_MIN_INIT (SATA_MIN_INIT), + .SATA_MIN_WAKE (SATA_MIN_WAKE), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA), + .SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL), + .SIM_VERSION (SIM_VERSION), + .TERM_RCAL_CFG (TERM_RCAL_CFG), + .TERM_RCAL_OVRD (TERM_RCAL_OVRD), + .TRANS_TIME_RATE (TRANS_TIME_RATE), + .TST_RSV (TST_RSV), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE), + .TXDLY_CFG (TXDLY_CFG), + .TXDLY_LCFG (TXDLY_LCFG), + .TXDLY_TAP_CFG (TXDLY_TAP_CFG), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOOB_CFG (TXOOB_CFG), + .TXOUT_DIV (TXOUT_DIV), + .TXPCSRESET_TIME (TXPCSRESET_TIME), + .TXPHDLY_CFG (TXPHDLY_CFG), + .TXPH_CFG (TXPH_CFG), + .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXPI_CFG2 (TXPI_CFG2), + .TXPI_CFG3 (TXPI_CFG3), + .TXPI_CFG4 (TXPI_CFG4), + .TXPI_CFG5 (TXPI_CFG5), + .TXPI_GREY_SEL (TXPI_GREY_SEL), + .TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL), + .TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL), + .TXPI_PPM_CFG (TXPI_PPM_CFG), + .TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM), + .TXPMARESET_TIME (TXPMARESET_TIME), + .TXSYNC_MULTILANE (TXSYNC_MULTILANE), + .TXSYNC_OVRD (TXSYNC_OVRD), + .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_PD (TX_CLKMUX_PD), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DEEMPH0 (TX_DEEMPH0), + .TX_DEEMPH1 (TX_DEEMPH1), + .TX_DRIVE_MODE (TX_DRIVE_MODE), + .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY), + .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH), + .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ), + .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), + .TX_QPI_STATUS_EN (TX_QPI_STATUS_EN), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), + .TX_RXDETECT_PRECHARGE_TIME (TX_RXDETECT_PRECHARGE_TIME), + .TX_RXDETECT_REF (TX_RXDETECT_REF), + .TX_XCLK_SEL (TX_XCLK_SEL), + .UCODEER_CLR (UCODEER_CLR), + .USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL)) + + B_GTHE2_CHANNEL_INST ( + .CPLLFBCLKLOST (delay_CPLLFBCLKLOST), + .CPLLLOCK (delay_CPLLLOCK), + .CPLLREFCLKLOST (delay_CPLLREFCLKLOST), + .DMONITOROUT (delay_DMONITOROUT), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .EYESCANDATAERROR (delay_EYESCANDATAERROR), + .GTHTXN (delay_GTHTXN), + .GTHTXP (delay_GTHTXP), + .GTREFCLKMONITOR (delay_GTREFCLKMONITOR), + .PCSRSVDOUT (delay_PCSRSVDOUT), + .PHYSTATUS (delay_PHYSTATUS), + .RSOSINTDONE (delay_RSOSINTDONE), + .RXBUFSTATUS (delay_RXBUFSTATUS), + .RXBYTEISALIGNED (delay_RXBYTEISALIGNED), + .RXBYTEREALIGN (delay_RXBYTEREALIGN), + .RXCDRLOCK (delay_RXCDRLOCK), + .RXCHANBONDSEQ (delay_RXCHANBONDSEQ), + .RXCHANISALIGNED (delay_RXCHANISALIGNED), + .RXCHANREALIGN (delay_RXCHANREALIGN), + .RXCHARISCOMMA (delay_RXCHARISCOMMA), + .RXCHARISK (delay_RXCHARISK), + .RXCHBONDO (delay_RXCHBONDO), + .RXCLKCORCNT (delay_RXCLKCORCNT), + .RXCOMINITDET (delay_RXCOMINITDET), + .RXCOMMADET (delay_RXCOMMADET), + .RXCOMSASDET (delay_RXCOMSASDET), + .RXCOMWAKEDET (delay_RXCOMWAKEDET), + .RXDATA (delay_RXDATA), + .RXDATAVALID (delay_RXDATAVALID), + .RXDFESLIDETAPSTARTED (delay_RXDFESLIDETAPSTARTED), + .RXDFESLIDETAPSTROBEDONE (delay_RXDFESLIDETAPSTROBEDONE), + .RXDFESLIDETAPSTROBESTARTED (delay_RXDFESLIDETAPSTROBESTARTED), + .RXDFESTADAPTDONE (delay_RXDFESTADAPTDONE), + .RXDISPERR (delay_RXDISPERR), + .RXDLYSRESETDONE (delay_RXDLYSRESETDONE), + .RXELECIDLE (delay_RXELECIDLE), + .RXHEADER (delay_RXHEADER), + .RXHEADERVALID (delay_RXHEADERVALID), + .RXMONITOROUT (delay_RXMONITOROUT), + .RXNOTINTABLE (delay_RXNOTINTABLE), + .RXOSINTSTARTED (delay_RXOSINTSTARTED), + .RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE), + .RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED), + .RXOUTCLK (delay_RXOUTCLK), + .RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC), + .RXOUTCLKPCS (delay_RXOUTCLKPCS), + .RXPHALIGNDONE (delay_RXPHALIGNDONE), + .RXPHMONITOR (delay_RXPHMONITOR), + .RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR), + .RXPMARESETDONE (delay_RXPMARESETDONE), + .RXPRBSERR (delay_RXPRBSERR), + .RXQPISENN (delay_RXQPISENN), + .RXQPISENP (delay_RXQPISENP), + .RXRATEDONE (delay_RXRATEDONE), + .RXRESETDONE (delay_RXRESETDONE), + .RXSTARTOFSEQ (delay_RXSTARTOFSEQ), + .RXSTATUS (delay_RXSTATUS), + .RXSYNCDONE (delay_RXSYNCDONE), + .RXSYNCOUT (delay_RXSYNCOUT), + .RXVALID (delay_RXVALID), + .TXBUFSTATUS (delay_TXBUFSTATUS), + .TXCOMFINISH (delay_TXCOMFINISH), + .TXDLYSRESETDONE (delay_TXDLYSRESETDONE), + .TXGEARBOXREADY (delay_TXGEARBOXREADY), + .TXOUTCLK (delay_TXOUTCLK), + .TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC), + .TXOUTCLKPCS (delay_TXOUTCLKPCS), + .TXPHALIGNDONE (delay_TXPHALIGNDONE), + .TXPHINITDONE (delay_TXPHINITDONE), + .TXPMARESETDONE (delay_TXPMARESETDONE), + .TXQPISENN (delay_TXQPISENN), + .TXQPISENP (delay_TXQPISENP), + .TXRATEDONE (delay_TXRATEDONE), + .TXRESETDONE (delay_TXRESETDONE), + .TXSYNCDONE (delay_TXSYNCDONE), + .TXSYNCOUT (delay_TXSYNCOUT), + .CFGRESET (delay_CFGRESET), + .CLKRSVD0 (delay_CLKRSVD0), + .CLKRSVD1 (delay_CLKRSVD1), + .CPLLLOCKDETCLK (delay_CPLLLOCKDETCLK), + .CPLLLOCKEN (delay_CPLLLOCKEN), + .CPLLPD (delay_CPLLPD), + .CPLLREFCLKSEL (delay_CPLLREFCLKSEL), + .CPLLRESET (delay_CPLLRESET), + .DMONFIFORESET (delay_DMONFIFORESET), + .DMONITORCLK (delay_DMONITORCLK), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .EYESCANMODE (delay_EYESCANMODE), + .EYESCANRESET (delay_EYESCANRESET), + .EYESCANTRIGGER (delay_EYESCANTRIGGER), + .GTGREFCLK (delay_GTGREFCLK), + .GTHRXN (delay_GTHRXN), + .GTHRXP (delay_GTHRXP), + .GTNORTHREFCLK0 (delay_GTNORTHREFCLK0), + .GTNORTHREFCLK1 (delay_GTNORTHREFCLK1), + .GTREFCLK0 (delay_GTREFCLK0), + .GTREFCLK1 (delay_GTREFCLK1), + .GTRESETSEL (delay_GTRESETSEL), + .GTRSVD (delay_GTRSVD), + .GTRXRESET (delay_GTRXRESET), + .GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0), + .GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1), + .GTTXRESET (delay_GTTXRESET), + .LOOPBACK (delay_LOOPBACK), + .PCSRSVDIN (delay_PCSRSVDIN), + .PCSRSVDIN2 (delay_PCSRSVDIN2), + .PMARSVDIN (delay_PMARSVDIN), + .QPLLCLK (delay_QPLLCLK), + .QPLLREFCLK (delay_QPLLREFCLK), + .RESETOVRD (delay_RESETOVRD), + .RX8B10BEN (delay_RX8B10BEN), + .RXADAPTSELTEST (delay_RXADAPTSELTEST), + .RXBUFRESET (delay_RXBUFRESET), + .RXCDRFREQRESET (delay_RXCDRFREQRESET), + .RXCDRHOLD (delay_RXCDRHOLD), + .RXCDROVRDEN (delay_RXCDROVRDEN), + .RXCDRRESET (delay_RXCDRRESET), + .RXCDRRESETRSV (delay_RXCDRRESETRSV), + .RXCHBONDEN (delay_RXCHBONDEN), + .RXCHBONDI (delay_RXCHBONDI), + .RXCHBONDLEVEL (delay_RXCHBONDLEVEL), + .RXCHBONDMASTER (delay_RXCHBONDMASTER), + .RXCHBONDSLAVE (delay_RXCHBONDSLAVE), + .RXCOMMADETEN (delay_RXCOMMADETEN), + .RXDDIEN (delay_RXDDIEN), + .RXDFEAGCHOLD (delay_RXDFEAGCHOLD), + .RXDFEAGCOVRDEN (delay_RXDFEAGCOVRDEN), + .RXDFEAGCTRL (delay_RXDFEAGCTRL), + .RXDFECM1EN (delay_RXDFECM1EN), + .RXDFELFHOLD (delay_RXDFELFHOLD), + .RXDFELFOVRDEN (delay_RXDFELFOVRDEN), + .RXDFELPMRESET (delay_RXDFELPMRESET), + .RXDFESLIDETAP (delay_RXDFESLIDETAP), + .RXDFESLIDETAPADAPTEN (delay_RXDFESLIDETAPADAPTEN), + .RXDFESLIDETAPHOLD (delay_RXDFESLIDETAPHOLD), + .RXDFESLIDETAPID (delay_RXDFESLIDETAPID), + .RXDFESLIDETAPINITOVRDEN (delay_RXDFESLIDETAPINITOVRDEN), + .RXDFESLIDETAPONLYADAPTEN (delay_RXDFESLIDETAPONLYADAPTEN), + .RXDFESLIDETAPOVRDEN (delay_RXDFESLIDETAPOVRDEN), + .RXDFESLIDETAPSTROBE (delay_RXDFESLIDETAPSTROBE), + .RXDFETAP2HOLD (delay_RXDFETAP2HOLD), + .RXDFETAP2OVRDEN (delay_RXDFETAP2OVRDEN), + .RXDFETAP3HOLD (delay_RXDFETAP3HOLD), + .RXDFETAP3OVRDEN (delay_RXDFETAP3OVRDEN), + .RXDFETAP4HOLD (delay_RXDFETAP4HOLD), + .RXDFETAP4OVRDEN (delay_RXDFETAP4OVRDEN), + .RXDFETAP5HOLD (delay_RXDFETAP5HOLD), + .RXDFETAP5OVRDEN (delay_RXDFETAP5OVRDEN), + .RXDFETAP6HOLD (delay_RXDFETAP6HOLD), + .RXDFETAP6OVRDEN (delay_RXDFETAP6OVRDEN), + .RXDFETAP7HOLD (delay_RXDFETAP7HOLD), + .RXDFETAP7OVRDEN (delay_RXDFETAP7OVRDEN), + .RXDFEUTHOLD (delay_RXDFEUTHOLD), + .RXDFEUTOVRDEN (delay_RXDFEUTOVRDEN), + .RXDFEVPHOLD (delay_RXDFEVPHOLD), + .RXDFEVPOVRDEN (delay_RXDFEVPOVRDEN), + .RXDFEVSEN (delay_RXDFEVSEN), + .RXDFEXYDEN (delay_RXDFEXYDEN), + .RXDLYBYPASS (delay_RXDLYBYPASS), + .RXDLYEN (delay_RXDLYEN), + .RXDLYOVRDEN (delay_RXDLYOVRDEN), + .RXDLYSRESET (delay_RXDLYSRESET), + .RXELECIDLEMODE (delay_RXELECIDLEMODE), + .RXGEARBOXSLIP (delay_RXGEARBOXSLIP), + .RXLPMEN (delay_RXLPMEN), + .RXLPMHFHOLD (delay_RXLPMHFHOLD), + .RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN), + .RXLPMLFHOLD (delay_RXLPMLFHOLD), + .RXLPMLFKLOVRDEN (delay_RXLPMLFKLOVRDEN), + .RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN), + .RXMONITORSEL (delay_RXMONITORSEL), + .RXOOBRESET (delay_RXOOBRESET), + .RXOSCALRESET (delay_RXOSCALRESET), + .RXOSHOLD (delay_RXOSHOLD), + .RXOSINTCFG (delay_RXOSINTCFG), + .RXOSINTEN (delay_RXOSINTEN), + .RXOSINTHOLD (delay_RXOSINTHOLD), + .RXOSINTID0 (delay_RXOSINTID0), + .RXOSINTNTRLEN (delay_RXOSINTNTRLEN), + .RXOSINTOVRDEN (delay_RXOSINTOVRDEN), + .RXOSINTSTROBE (delay_RXOSINTSTROBE), + .RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN), + .RXOSOVRDEN (delay_RXOSOVRDEN), + .RXOUTCLKSEL (delay_RXOUTCLKSEL), + .RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN), + .RXPCSRESET (delay_RXPCSRESET), + .RXPD (delay_RXPD), + .RXPHALIGN (delay_RXPHALIGN), + .RXPHALIGNEN (delay_RXPHALIGNEN), + .RXPHDLYPD (delay_RXPHDLYPD), + .RXPHDLYRESET (delay_RXPHDLYRESET), + .RXPHOVRDEN (delay_RXPHOVRDEN), + .RXPMARESET (delay_RXPMARESET), + .RXPOLARITY (delay_RXPOLARITY), + .RXPRBSCNTRESET (delay_RXPRBSCNTRESET), + .RXPRBSSEL (delay_RXPRBSSEL), + .RXQPIEN (delay_RXQPIEN), + .RXRATE (delay_RXRATE), + .RXRATEMODE (delay_RXRATEMODE), + .RXSLIDE (delay_RXSLIDE), + .RXSYNCALLIN (delay_RXSYNCALLIN), + .RXSYNCIN (delay_RXSYNCIN), + .RXSYNCMODE (delay_RXSYNCMODE), + .RXSYSCLKSEL (delay_RXSYSCLKSEL), + .RXUSERRDY (delay_RXUSERRDY), + .RXUSRCLK (delay_RXUSRCLK), + .RXUSRCLK2 (delay_RXUSRCLK2), + .SETERRSTATUS (delay_SETERRSTATUS), + .SIGVALIDCLK (delay_SIGVALIDCLK), + .TSTIN (delay_TSTIN), + .TX8B10BBYPASS (delay_TX8B10BBYPASS), + .TX8B10BEN (delay_TX8B10BEN), + .TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL), + .TXCHARDISPMODE (delay_TXCHARDISPMODE), + .TXCHARDISPVAL (delay_TXCHARDISPVAL), + .TXCHARISK (delay_TXCHARISK), + .TXCOMINIT (delay_TXCOMINIT), + .TXCOMSAS (delay_TXCOMSAS), + .TXCOMWAKE (delay_TXCOMWAKE), + .TXDATA (delay_TXDATA), + .TXDEEMPH (delay_TXDEEMPH), + .TXDETECTRX (delay_TXDETECTRX), + .TXDIFFCTRL (delay_TXDIFFCTRL), + .TXDIFFPD (delay_TXDIFFPD), + .TXDLYBYPASS (delay_TXDLYBYPASS), + .TXDLYEN (delay_TXDLYEN), + .TXDLYHOLD (delay_TXDLYHOLD), + .TXDLYOVRDEN (delay_TXDLYOVRDEN), + .TXDLYSRESET (delay_TXDLYSRESET), + .TXDLYUPDOWN (delay_TXDLYUPDOWN), + .TXELECIDLE (delay_TXELECIDLE), + .TXHEADER (delay_TXHEADER), + .TXINHIBIT (delay_TXINHIBIT), + .TXMAINCURSOR (delay_TXMAINCURSOR), + .TXMARGIN (delay_TXMARGIN), + .TXOUTCLKSEL (delay_TXOUTCLKSEL), + .TXPCSRESET (delay_TXPCSRESET), + .TXPD (delay_TXPD), + .TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE), + .TXPHALIGN (delay_TXPHALIGN), + .TXPHALIGNEN (delay_TXPHALIGNEN), + .TXPHDLYPD (delay_TXPHDLYPD), + .TXPHDLYRESET (delay_TXPHDLYRESET), + .TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK), + .TXPHINIT (delay_TXPHINIT), + .TXPHOVRDEN (delay_TXPHOVRDEN), + .TXPIPPMEN (delay_TXPIPPMEN), + .TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN), + .TXPIPPMPD (delay_TXPIPPMPD), + .TXPIPPMSEL (delay_TXPIPPMSEL), + .TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE), + .TXPISOPD (delay_TXPISOPD), + .TXPMARESET (delay_TXPMARESET), + .TXPOLARITY (delay_TXPOLARITY), + .TXPOSTCURSOR (delay_TXPOSTCURSOR), + .TXPOSTCURSORINV (delay_TXPOSTCURSORINV), + .TXPRBSFORCEERR (delay_TXPRBSFORCEERR), + .TXPRBSSEL (delay_TXPRBSSEL), + .TXPRECURSOR (delay_TXPRECURSOR), + .TXPRECURSORINV (delay_TXPRECURSORINV), + .TXQPIBIASEN (delay_TXQPIBIASEN), + .TXQPISTRONGPDOWN (delay_TXQPISTRONGPDOWN), + .TXQPIWEAKPUP (delay_TXQPIWEAKPUP), + .TXRATE (delay_TXRATE), + .TXRATEMODE (delay_TXRATEMODE), + .TXSEQUENCE (delay_TXSEQUENCE), + .TXSTARTSEQ (delay_TXSTARTSEQ), + .TXSWING (delay_TXSWING), + .TXSYNCALLIN (delay_TXSYNCALLIN), + .TXSYNCIN (delay_TXSYNCIN), + .TXSYNCMODE (delay_TXSYNCMODE), + .TXSYSCLKSEL (delay_TXSYSCLKSEL), + .TXUSERRDY (delay_TXUSERRDY), + .TXUSRCLK (delay_TXUSRCLK), + .TXUSRCLK2 (delay_TXUSRCLK2), + .GSR(GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge CLKRSVD0, 0:0:0, notifier); + $period (negedge CLKRSVD0, 0:0:0, notifier); + $period (posedge CLKRSVD1, 0:0:0, notifier); + $period (negedge CLKRSVD1, 0:0:0, notifier); + $period (posedge CPLLLOCKDETCLK, 0:0:0, notifier); + $period (negedge CPLLLOCKDETCLK, 0:0:0, notifier); + $period (posedge DMONITORCLK, 0:0:0, notifier); + $period (negedge DMONITORCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge GTGREFCLK, 0:0:0, notifier); + $period (negedge GTGREFCLK, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK0, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLK0, 0:0:0, notifier); + $period (posedge GTREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLKMONITOR, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK0, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK1, 0:0:0, notifier); + $period (posedge QPLLCLK, 0:0:0, notifier); + $period (posedge RXOUTCLK, 0:0:0, notifier); + $period (posedge RXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge RXOUTCLKPCS, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge SIGVALIDCLK, 0:0:0, notifier); + $period (negedge SIGVALIDCLK, 0:0:0, notifier); + $period (posedge TXOUTCLK, 0:0:0, notifier); + $period (posedge TXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge TXOUTCLKPCS, 0:0:0, notifier); + $period (posedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (negedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMOVRDEN); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMPD); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSEL); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMOVRDEN); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMPD); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSEL); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMOVRDEN); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMPD); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSEL); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMOVRDEN); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMPD); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSEL); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMPD); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSEL); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMPD); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSEL); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p,, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMPD); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSEL); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMPD); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSEL); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); + +`endif + + ( DMONITORCLK *> DMONITOROUT) = (0, 0); + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( GTNORTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTNORTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( GTREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( GTSOUTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTSOUTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( QPLLCLK *> GTREFCLKMONITOR) = (0, 0); + ( RXUSRCLK *> RXCHBONDO) = (0, 0); + ( RXUSRCLK2 *> RXCHBONDO) = (0, 0); + ( RXUSRCLK2 *> PHYSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0); + ( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0); + ( RXUSRCLK2 *> RXCHARISK) = (0, 0); + ( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0); + ( RXUSRCLK2 *> RXCOMINITDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMMADET) = (0, 0); + ( RXUSRCLK2 *> RXCOMSASDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0); + ( RXUSRCLK2 *> RXDATA) = (0, 0); + ( RXUSRCLK2 *> RXDATAVALID) = (0, 0); + ( RXUSRCLK2 *> RXDISPERR) = (0, 0); + ( RXUSRCLK2 *> RXHEADER) = (0, 0); + ( RXUSRCLK2 *> RXHEADERVALID) = (0, 0); + ( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0); + ( RXUSRCLK2 *> RXPRBSERR) = (0, 0); + ( RXUSRCLK2 *> RXRATEDONE) = (0, 0); + ( RXUSRCLK2 *> RXRESETDONE) = (0, 0); + ( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0); + ( RXUSRCLK2 *> RXSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXVALID) = (0, 0); + ( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0); + ( TXUSRCLK2 *> TXCOMFINISH) = (0, 0); + ( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0); + ( TXUSRCLK2 *> TXRATEDONE) = (0, 0); + ( TXUSRCLK2 *> TXRESETDONE) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTHE2_COMMON.v b/verilog/src/unisims/GTHE2_COMMON.v new file mode 100644 index 0000000..4fe4ca1 --- /dev/null +++ b/verilog/src/unisims/GTHE2_COMMON.v @@ -0,0 +1,636 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTHE2_COMMON.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// Initial version +// 09/22/11 - 624065 - YML update +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 06/12/12 - 664920 - YML update +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine + +module GTHE2_COMMON ( + DRPDO, + DRPRDY, + PMARSVDOUT, + QPLLDMONITOR, + QPLLFBCLKLOST, + QPLLLOCK, + QPLLOUTCLK, + QPLLOUTREFCLK, + QPLLREFCLKLOST, + REFCLKOUTMONITOR, + + BGBYPASSB, + BGMONITORENB, + BGPDB, + BGRCALOVRD, + BGRCALOVRDENB, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + GTGREFCLK, + GTNORTHREFCLK0, + GTNORTHREFCLK1, + GTREFCLK0, + GTREFCLK1, + GTSOUTHREFCLK0, + GTSOUTHREFCLK1, + PMARSVD, + QPLLLOCKDETCLK, + QPLLLOCKEN, + QPLLOUTRESET, + QPLLPD, + QPLLREFCLKSEL, + QPLLRESET, + QPLLRSVD1, + QPLLRSVD2, + RCALENB +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h0000001C; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0480181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h01E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [0:0] QPLL_RP_COMP = 1'b0; + parameter [1:0] QPLL_VTRL_RESET = 2'b00; + parameter [1:0] RCAL_CFG = 2'b00; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.1"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] QPLLDMONITOR; + + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + input DRPCLK; + input DRPEN; + input DRPWE; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; + + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY; + reg [0:0] QPLL_CP_MONITOR_EN_BINARY; + reg [0:0] QPLL_DMONITOR_SEL_BINARY; + reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY; + reg [0:0] QPLL_FBDIV_RATIO_BINARY; + reg [0:0] QPLL_RP_COMP_BINARY; + reg [1:0] QPLL_VTRL_RESET_BINARY; + reg [1:0] RCAL_CFG_BINARY; + reg [2:0] SIM_QPLLREFCLK_SEL_BINARY; + reg [3:0] QPLL_CLKOUT_CFG_BINARY; + reg [3:0] QPLL_LPF_BINARY; + reg [4:0] QPLL_REFCLK_DIV_BINARY; + reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY; + reg [9:0] QPLL_CP_BINARY; + reg [9:0] QPLL_FBDIV_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (QPLL_REFCLK_DIV) + 2 : QPLL_REFCLK_DIV_BINARY = 5'b00000; + 1 : QPLL_REFCLK_DIV_BINARY = 5'b10000; + 3 : QPLL_REFCLK_DIV_BINARY = 5'b00001; + 4 : QPLL_REFCLK_DIV_BINARY = 5'b00010; + 5 : QPLL_REFCLK_DIV_BINARY = 5'b00011; + 6 : QPLL_REFCLK_DIV_BINARY = 5'b00101; + 8 : QPLL_REFCLK_DIV_BINARY = 5'b00110; + 10 : QPLL_REFCLK_DIV_BINARY = 5'b00111; + 12 : QPLL_REFCLK_DIV_BINARY = 5'b01101; + 16 : QPLL_REFCLK_DIV_BINARY = 5'b01110; + 20 : QPLL_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on GTHE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTHE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + case (SIM_VERSION) + "1.1" : SIM_VERSION_BINARY = 0; + "1.0" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.1, 1.0, or 2.0.", SIM_VERSION); + #1 $finish; + end +endcase + + + if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111)) + QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG); + #1 $finish; + end + + if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111)) + QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD); + #1 $finish; + end + + if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1)) + QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN); + #1 $finish; + end + + if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111)) + QPLL_CP_BINARY = QPLL_CP; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP); + #1 $finish; + end + + if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1)) + QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN); + #1 $finish; + end + + if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1)) + QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL); + #1 $finish; + end + + if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111)) + QPLL_FBDIV_BINARY = QPLL_FBDIV; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV); + #1 $finish; + end + + if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1)) + QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN); + #1 $finish; + end + + if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1)) + QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO); + #1 $finish; + end + + if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111)) + QPLL_LPF_BINARY = QPLL_LPF; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_LPF on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF); + #1 $finish; + end + + if ((QPLL_RP_COMP >= 1'b0) && (QPLL_RP_COMP <= 1'b1)) + QPLL_RP_COMP_BINARY = QPLL_RP_COMP; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_RP_COMP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_RP_COMP); + #1 $finish; + end + + if ((QPLL_VTRL_RESET >= 2'b00) && (QPLL_VTRL_RESET <= 2'b11)) + QPLL_VTRL_RESET_BINARY = QPLL_VTRL_RESET; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_VTRL_RESET on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", QPLL_VTRL_RESET); + #1 $finish; + end + + if ((RCAL_CFG >= 2'b00) && (RCAL_CFG <= 2'b11)) + RCAL_CFG_BINARY = RCAL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RCAL_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RCAL_CFG); + #1 $finish; + end + + if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111)) + SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL); + #1 $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [15:0] delay_PMARSVDOUT; + wire [7:0] delay_QPLLDMONITOR; + wire delay_DRPRDY; + wire delay_QPLLFBCLKLOST; + wire delay_QPLLLOCK; + wire delay_QPLLOUTCLK; + wire delay_QPLLOUTREFCLK; + wire delay_QPLLREFCLKLOST; + wire delay_REFCLKOUTMONITOR; + + wire [15:0] delay_DRPDI; + wire [15:0] delay_QPLLRSVD1; + wire [2:0] delay_QPLLREFCLKSEL; + wire [4:0] delay_BGRCALOVRD; + wire [4:0] delay_QPLLRSVD2; + wire [7:0] delay_DRPADDR; + wire [7:0] delay_PMARSVD; + wire delay_BGBYPASSB; + wire delay_BGMONITORENB; + wire delay_BGPDB; + wire delay_BGRCALOVRDENB; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_GTGREFCLK; + wire delay_GTNORTHREFCLK0; + wire delay_GTNORTHREFCLK1; + wire delay_GTREFCLK0; + wire delay_GTREFCLK1; + wire delay_GTSOUTHREFCLK0; + wire delay_GTSOUTHREFCLK1; + wire delay_QPLLLOCKDETCLK; + wire delay_QPLLLOCKEN; + wire delay_QPLLOUTRESET; + wire delay_QPLLPD; + wire delay_QPLLRESET; + wire delay_RCALENB; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED; + reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED; + + + assign QPLLOUTCLK = delay_QPLLOUTCLK; + assign REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR; + + assign DRPDO = delay_DRPDO; + assign DRPRDY = delay_DRPRDY; + assign PMARSVDOUT = delay_PMARSVDOUT; + assign QPLLDMONITOR = delay_QPLLDMONITOR; + assign QPLLFBCLKLOST = delay_QPLLFBCLKLOST; + assign QPLLLOCK = delay_QPLLLOCK; + assign QPLLOUTREFCLK = delay_QPLLOUTREFCLK; + assign QPLLREFCLKLOST = delay_QPLLREFCLKLOST; + +`ifndef XIL_TIMING // unisim + assign delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG; + + assign delay_BGBYPASSB = BGBYPASSB; + assign delay_BGMONITORENB = BGMONITORENB; + assign delay_BGPDB = BGPDB; + assign delay_BGRCALOVRD = BGRCALOVRD; + assign delay_BGRCALOVRDENB = BGRCALOVRDENB; + assign delay_DRPADDR = DRPADDR; + assign delay_DRPDI = DRPDI; + assign delay_DRPEN = DRPEN; + assign delay_DRPWE = DRPWE; + assign delay_PMARSVD = PMARSVD; + assign delay_QPLLLOCKEN = QPLLLOCKEN; + assign delay_QPLLOUTRESET = QPLLOUTRESET; + assign delay_QPLLPD = QPLLPD; + assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL; + assign delay_QPLLRESET = QPLLRESET; + assign delay_QPLLRSVD1 = QPLLRSVD1; + assign delay_QPLLRSVD2 = QPLLRSVD2; + assign delay_RCALENB = RCALENB; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_BGBYPASSB = BGBYPASSB; + assign delay_BGMONITORENB = BGMONITORENB; + assign delay_BGPDB = BGPDB; + assign delay_BGRCALOVRD = BGRCALOVRD; + assign delay_BGRCALOVRDENB = BGRCALOVRDENB; + assign delay_GTGREFCLK = GTGREFCLK; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_PMARSVD = PMARSVD; + assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK; + assign delay_QPLLLOCKEN = QPLLLOCKEN; + assign delay_QPLLOUTRESET = QPLLOUTRESET; + assign delay_QPLLPD = QPLLPD; + assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL; + assign delay_QPLLRESET = QPLLRESET; + assign delay_QPLLRSVD1 = QPLLRSVD1; + assign delay_QPLLRSVD2 = QPLLRSVD2; + assign delay_RCALENB = RCALENB; + + wire drpclk_en_p; + wire drpclk_en_n; + + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; +`endif + + B_GTHE2_COMMON #( + .BIAS_CFG (BIAS_CFG), + .COMMON_CFG (COMMON_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG), + .QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD), + .QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN), + .QPLL_CP (QPLL_CP), + .QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN), + .QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (QPLL_INIT_CFG), + .QPLL_LOCK_CFG (QPLL_LOCK_CFG), + .QPLL_LPF (QPLL_LPF), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_RP_COMP (QPLL_RP_COMP), + .QPLL_VTRL_RESET (QPLL_VTRL_RESET), + .RCAL_CFG (RCAL_CFG), + .RSVD_ATTR0 (RSVD_ATTR0), + .RSVD_ATTR1 (RSVD_ATTR1), + .SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION)) + + B_GTHE2_COMMON_INST ( + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .PMARSVDOUT (delay_PMARSVDOUT), + .QPLLDMONITOR (delay_QPLLDMONITOR), + .QPLLFBCLKLOST (delay_QPLLFBCLKLOST), + .QPLLLOCK (delay_QPLLLOCK), + .QPLLOUTCLK (delay_QPLLOUTCLK), + .QPLLOUTREFCLK (delay_QPLLOUTREFCLK), + .QPLLREFCLKLOST (delay_QPLLREFCLKLOST), + .REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR), + .BGBYPASSB (delay_BGBYPASSB), + .BGMONITORENB (delay_BGMONITORENB), + .BGPDB (delay_BGPDB), + .BGRCALOVRD (delay_BGRCALOVRD), + .BGRCALOVRDENB (delay_BGRCALOVRDENB), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .GTGREFCLK (delay_GTGREFCLK), + .GTNORTHREFCLK0 (delay_GTNORTHREFCLK0), + .GTNORTHREFCLK1 (delay_GTNORTHREFCLK1), + .GTREFCLK0 (delay_GTREFCLK0), + .GTREFCLK1 (delay_GTREFCLK1), + .GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0), + .GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1), + .PMARSVD (delay_PMARSVD), + .QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK), + .QPLLLOCKEN (delay_QPLLLOCKEN), + .QPLLOUTRESET (delay_QPLLOUTRESET), + .QPLLPD (delay_QPLLPD), + .QPLLREFCLKSEL (delay_QPLLREFCLKSEL), + .QPLLRESET (delay_QPLLRESET), + .QPLLRSVD1 (delay_QPLLRSVD1), + .QPLLRSVD2 (delay_QPLLRSVD2), + .RCALENB (delay_RCALENB), + .GSR(GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge GTGREFCLK, 0:0:0, notifier); + $period (negedge GTGREFCLK, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK0, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLK0, 0:0:0, notifier); + $period (posedge GTREFCLK1, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK0, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK1, 0:0:0, notifier); + $period (posedge QPLLLOCKDETCLK, 0:0:0, notifier); + $period (negedge QPLLLOCKDETCLK, 0:0:0, notifier); + $period (posedge QPLLOUTCLK, 0:0:0, notifier); + $period (posedge REFCLKOUTMONITOR, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + +`endif + + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0); + ( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + ( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + ( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTHE3_CHANNEL.v b/verilog/src/unisims/GTHE3_CHANNEL.v new file mode 100644 index 0000000..bab8681 --- /dev/null +++ b/verilog/src/unisims/GTHE3_CHANNEL.v @@ -0,0 +1,5246 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : GTHE3_CHANNEL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTHE3_CHANNEL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0, + parameter [0:0] ACJTAG_MODE = 1'b0, + parameter [0:0] ACJTAG_RESET = 1'b0, + parameter [15:0] ADAPT_CFG0 = 16'hF800, + parameter [15:0] ADAPT_CFG1 = 16'h0000, + parameter ALIGN_COMMA_DOUBLE = "FALSE", + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111, + parameter integer ALIGN_COMMA_WORD = 1, + parameter ALIGN_MCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011, + parameter ALIGN_PCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100, + parameter [0:0] A_RXOSCALRESET = 1'b0, + parameter [0:0] A_RXPROGDIVRESET = 1'b0, + parameter [0:0] A_TXPROGDIVRESET = 1'b0, + parameter CBCC_DATA_SOURCE_SEL = "DECODED", + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0, + parameter CHAN_BOND_KEEP_ALIGN = "FALSE", + parameter integer CHAN_BOND_MAX_SKEW = 7, + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100, + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111, + parameter CHAN_BOND_SEQ_2_USE = "FALSE", + parameter integer CHAN_BOND_SEQ_LEN = 2, + parameter CLK_CORRECT_USE = "TRUE", + parameter CLK_COR_KEEP_IDLE = "FALSE", + parameter integer CLK_COR_MAX_LAT = 20, + parameter integer CLK_COR_MIN_LAT = 18, + parameter CLK_COR_PRECEDENCE = "TRUE", + parameter integer CLK_COR_REPEAT_WAIT = 0, + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100, + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111, + parameter CLK_COR_SEQ_2_USE = "FALSE", + parameter integer CLK_COR_SEQ_LEN = 2, + parameter [15:0] CPLL_CFG0 = 16'h20F8, + parameter [15:0] CPLL_CFG1 = 16'hA494, + parameter [15:0] CPLL_CFG2 = 16'hF001, + parameter [5:0] CPLL_CFG3 = 6'h00, + parameter integer CPLL_FBDIV = 4, + parameter integer CPLL_FBDIV_45 = 4, + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E, + parameter [7:0] CPLL_INIT_CFG1 = 8'h00, + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8, + parameter integer CPLL_REFCLK_DIV = 1, + parameter [1:0] DDI_CTRL = 2'b00, + parameter integer DDI_REALIGN_WAIT = 15, + parameter DEC_MCOMMA_DETECT = "TRUE", + parameter DEC_PCOMMA_DETECT = "TRUE", + parameter DEC_VALID_COMMA_ONLY = "TRUE", + parameter [0:0] DFE_D_X_REL_POS = 1'b0, + parameter [0:0] DFE_VCM_COMP_EN = 1'b0, + parameter [9:0] DMONITOR_CFG0 = 10'h000, + parameter [7:0] DMONITOR_CFG1 = 8'h00, + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0, + parameter [5:0] ES_CONTROL = 6'b000000, + parameter ES_ERRDET_EN = "FALSE", + parameter ES_EYE_SCAN_EN = "FALSE", + parameter [11:0] ES_HORZ_OFFSET = 12'h000, + parameter [9:0] ES_PMA_CFG = 10'b0000000000, + parameter [4:0] ES_PRESCALE = 5'b00000, + parameter [15:0] ES_QUALIFIER0 = 16'h0000, + parameter [15:0] ES_QUALIFIER1 = 16'h0000, + parameter [15:0] ES_QUALIFIER2 = 16'h0000, + parameter [15:0] ES_QUALIFIER3 = 16'h0000, + parameter [15:0] ES_QUALIFIER4 = 16'h0000, + parameter [15:0] ES_QUAL_MASK0 = 16'h0000, + parameter [15:0] ES_QUAL_MASK1 = 16'h0000, + parameter [15:0] ES_QUAL_MASK2 = 16'h0000, + parameter [15:0] ES_QUAL_MASK3 = 16'h0000, + parameter [15:0] ES_QUAL_MASK4 = 16'h0000, + parameter [15:0] ES_SDATA_MASK0 = 16'h0000, + parameter [15:0] ES_SDATA_MASK1 = 16'h0000, + parameter [15:0] ES_SDATA_MASK2 = 16'h0000, + parameter [15:0] ES_SDATA_MASK3 = 16'h0000, + parameter [15:0] ES_SDATA_MASK4 = 16'h0000, + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000, + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0, + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111, + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111, + parameter FTS_LANE_DESKEW_EN = "FALSE", + parameter [4:0] GEARBOX_MODE = 5'b00000, + parameter [0:0] GM_BIAS_SELECT = 1'b0, + parameter [0:0] LOCAL_MASTER = 1'b0, + parameter [1:0] OOBDIVCTL = 2'b00, + parameter [0:0] OOB_PWRUP = 1'b0, + parameter PCI3_AUTO_REALIGN = "FRST_SMPL", + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1, + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00, + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0, + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000, + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000, + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000, + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0, + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0, + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000, + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000, + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000, + parameter PCS_PCIE_EN = "FALSE", + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000, + parameter [2:0] PCS_RSVD1 = 3'b000, + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C, + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19, + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64, + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0, + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0, + parameter [15:0] PMA_RSV1 = 16'h0000, + parameter [2:0] PROCESS_PAR = 3'b010, + parameter [0:0] RATE_SW_USE_DRP = 1'b0, + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0, + parameter [4:0] RXBUFRESET_TIME = 5'b00001, + parameter RXBUF_ADDR_MODE = "FULL", + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000, + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000, + parameter RXBUF_EN = "TRUE", + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE", + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE", + parameter RXBUF_RESET_ON_EIDLE = "FALSE", + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE", + parameter integer RXBUF_THRESH_OVFLW = 0, + parameter RXBUF_THRESH_OVRD = "FALSE", + parameter integer RXBUF_THRESH_UNDFLW = 4, + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001, + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001, + parameter [15:0] RXCDR_CFG0 = 16'h0000, + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG1 = 16'h0080, + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG2 = 16'h07E6, + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG3 = 16'h0000, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG4 = 16'h0000, + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG5 = 16'h0000, + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000, + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0, + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0, + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080, + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0, + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42, + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0, + parameter [15:0] RXCFOK_CFG0 = 16'h4000, + parameter [15:0] RXCFOK_CFG1 = 16'h0060, + parameter [15:0] RXCFOK_CFG2 = 16'h000E, + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111, + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000, + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032, + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000, + parameter [15:0] RXDFE_CFG0 = 16'h0A00, + parameter [15:0] RXDFE_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG1 = 16'h7840, + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG1 = 16'h0000, + parameter [15:0] RXDFE_H3_CFG0 = 16'h4000, + parameter [15:0] RXDFE_H3_CFG1 = 16'h0000, + parameter [15:0] RXDFE_H4_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003, + parameter [15:0] RXDFE_H5_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H5_CFG1 = 16'h0003, + parameter [15:0] RXDFE_H6_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H6_CFG1 = 16'h0000, + parameter [15:0] RXDFE_H7_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H7_CFG1 = 16'h0000, + parameter [15:0] RXDFE_H8_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H8_CFG1 = 16'h0000, + parameter [15:0] RXDFE_H9_CFG0 = 16'h2000, + parameter [15:0] RXDFE_H9_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HA_CFG0 = 16'h2000, + parameter [15:0] RXDFE_HA_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HB_CFG0 = 16'h2000, + parameter [15:0] RXDFE_HB_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HC_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HD_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HE_CFG1 = 16'h0000, + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HF_CFG1 = 16'h0000, + parameter [15:0] RXDFE_OS_CFG0 = 16'h8000, + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000, + parameter [15:0] RXDFE_UT_CFG0 = 16'h8000, + parameter [15:0] RXDFE_UT_CFG1 = 16'h0003, + parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00, + parameter [15:0] RXDFE_VP_CFG1 = 16'h0033, + parameter [15:0] RXDLY_CFG = 16'h001F, + parameter [15:0] RXDLY_LCFG = 16'h0030, + parameter RXELECIDLE_CFG = "Sigcfg_4", + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter RXGEARBOX_EN = "FALSE", + parameter [4:0] RXISCANRESET_TIME = 5'b00001, + parameter [15:0] RXLPM_CFG = 16'h0000, + parameter [15:0] RXLPM_GC_CFG = 16'h0000, + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000, + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002, + parameter [15:0] RXLPM_OS_CFG0 = 16'h8000, + parameter [15:0] RXLPM_OS_CFG1 = 16'h0002, + parameter [8:0] RXOOB_CFG = 9'b000000110, + parameter RXOOB_CLK_CFG = "PMA", + parameter [4:0] RXOSCALRESET_TIME = 5'b00011, + parameter integer RXOUT_DIV = 4, + parameter [4:0] RXPCSRESET_TIME = 5'b00001, + parameter [15:0] RXPHBEACON_CFG = 16'h0000, + parameter [15:0] RXPHDLY_CFG = 16'h2020, + parameter [15:0] RXPHSAMP_CFG = 16'h2100, + parameter [15:0] RXPHSLIP_CFG = 16'h6622, + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000, + parameter [1:0] RXPI_CFG0 = 2'b00, + parameter [1:0] RXPI_CFG1 = 2'b00, + parameter [1:0] RXPI_CFG2 = 2'b00, + parameter [1:0] RXPI_CFG3 = 2'b00, + parameter [0:0] RXPI_CFG4 = 1'b0, + parameter [0:0] RXPI_CFG5 = 1'b1, + parameter [2:0] RXPI_CFG6 = 3'b000, + parameter [0:0] RXPI_LPM = 1'b0, + parameter [0:0] RXPI_VREFSEL = 1'b0, + parameter RXPMACLK_SEL = "DATA", + parameter [4:0] RXPMARESET_TIME = 5'b00001, + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0, + parameter integer RXPRBS_LINKACQ_CNT = 15, + parameter integer RXSLIDE_AUTO_WAIT = 7, + parameter RXSLIDE_MODE = "OFF", + parameter [0:0] RXSYNC_MULTILANE = 1'b0, + parameter [0:0] RXSYNC_OVRD = 1'b0, + parameter [0:0] RXSYNC_SKIP_DA = 1'b0, + parameter [0:0] RX_AFE_CM_EN = 1'b0, + parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4, + parameter [5:0] RX_BUFFER_CFG = 6'b000000, + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0, + parameter integer RX_CLK25_DIV = 8, + parameter [0:0] RX_CLKMUX_EN = 1'b1, + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000, + parameter [3:0] RX_CM_BUF_CFG = 4'b1010, + parameter [0:0] RX_CM_BUF_PD = 1'b0, + parameter [1:0] RX_CM_SEL = 2'b11, + parameter [3:0] RX_CM_TRIM = 4'b0100, + parameter [7:0] RX_CTLE3_LPF = 8'b00000000, + parameter integer RX_DATA_WIDTH = 20, + parameter [5:0] RX_DDI_SEL = 6'b000000, + parameter RX_DEFER_RESET_BUF_EN = "TRUE", + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110, + parameter [0:0] RX_DFELPM_CFG1 = 1'b0, + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1, + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00, + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100, + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01, + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010, + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01, + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010, + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0, + parameter RX_DISPERR_SEQ_MATCH = "TRUE", + parameter [4:0] RX_DIVRESET_TIME = 5'b00001, + parameter [0:0] RX_EN_HI_LR = 1'b0, + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000, + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0, + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00, + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0, + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0, + parameter integer RX_INT_DATAWIDTH = 1, + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0, + parameter real RX_PROGDIV_CFG = 0.0, + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101, + parameter integer RX_SIG_VALID_DLY = 11, + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0, + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000, + parameter [1:0] RX_SUM_RES_CTRL = 2'b00, + parameter [3:0] RX_SUM_VCMTUNE = 4'b0000, + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0, + parameter [2:0] RX_SUM_VREF_TUNE = 3'b000, + parameter [1:0] RX_TUNE_AFE_OS = 2'b00, + parameter [0:0] RX_WIDEMODE_CDR = 1'b0, + parameter RX_XCLK_SEL = "RXDES", + parameter integer SAS_MAX_COM = 64, + parameter integer SAS_MIN_COM = 36, + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111, + parameter [2:0] SATA_BURST_VAL = 3'b100, + parameter SATA_CPLL_CFG = "VCO_3000MHZ", + parameter [2:0] SATA_EIDLE_VAL = 3'b100, + parameter integer SATA_MAX_BURST = 8, + parameter integer SATA_MAX_INIT = 21, + parameter integer SATA_MAX_WAKE = 7, + parameter integer SATA_MIN_BURST = 4, + parameter integer SATA_MIN_INIT = 12, + parameter integer SATA_MIN_WAKE = 4, + parameter SHOW_REALIGN_COMMA = "TRUE", + parameter SIM_MODE = "FAST", + parameter SIM_RECEIVER_DETECT_PASS = "TRUE", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0, + parameter integer SIM_VERSION = 2, + parameter [1:0] TAPDLY_SET_TX = 2'h0, + parameter [3:0] TEMPERATUR_PAR = 4'b0010, + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000, + parameter [2:0] TERM_RCAL_OVRD = 3'b000, + parameter [7:0] TRANS_TIME_RATE = 8'h0E, + parameter [7:0] TST_RSV0 = 8'h00, + parameter [7:0] TST_RSV1 = 8'h00, + parameter TXBUF_EN = "TRUE", + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE", + parameter [15:0] TXDLY_CFG = 16'h001F, + parameter [15:0] TXDLY_LCFG = 16'h0030, + parameter [3:0] TXDRVBIAS_N = 4'b1010, + parameter [3:0] TXDRVBIAS_P = 4'b1100, + parameter TXFIFO_ADDR_CFG = "LOW", + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter TXGEARBOX_EN = "FALSE", + parameter integer TXOUT_DIV = 4, + parameter [4:0] TXPCSRESET_TIME = 5'b00001, + parameter [15:0] TXPHDLY_CFG0 = 16'h2020, + parameter [15:0] TXPHDLY_CFG1 = 16'h0001, + parameter [15:0] TXPH_CFG = 16'h0980, + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000, + parameter [1:0] TXPI_CFG0 = 2'b00, + parameter [1:0] TXPI_CFG1 = 2'b00, + parameter [1:0] TXPI_CFG2 = 2'b00, + parameter [0:0] TXPI_CFG3 = 1'b0, + parameter [0:0] TXPI_CFG4 = 1'b1, + parameter [2:0] TXPI_CFG5 = 3'b000, + parameter [0:0] TXPI_GRAY_SEL = 1'b0, + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0, + parameter [0:0] TXPI_LPM = 1'b0, + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2", + parameter [7:0] TXPI_PPM_CFG = 8'b00000000, + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000, + parameter [0:0] TXPI_VREFSEL = 1'b0, + parameter [4:0] TXPMARESET_TIME = 5'b00001, + parameter [0:0] TXSYNC_MULTILANE = 1'b0, + parameter [0:0] TXSYNC_OVRD = 1'b0, + parameter [0:0] TXSYNC_SKIP_DA = 1'b0, + parameter integer TX_CLK25_DIV = 8, + parameter [0:0] TX_CLKMUX_EN = 1'b1, + parameter integer TX_DATA_WIDTH = 20, + parameter [5:0] TX_DCD_CFG = 6'b000010, + parameter [0:0] TX_DCD_EN = 1'b0, + parameter [5:0] TX_DEEMPH0 = 6'b000000, + parameter [5:0] TX_DEEMPH1 = 6'b000000, + parameter [4:0] TX_DIVRESET_TIME = 5'b00001, + parameter TX_DRIVE_MODE = "DIRECT", + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110, + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100, + parameter [0:0] TX_EML_PHI_TUNE = 1'b0, + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0, + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0, + parameter integer TX_INT_DATAWIDTH = 1, + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE", + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0, + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110, + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001, + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101, + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010, + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110, + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100, + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010, + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000, + parameter [2:0] TX_MODE_SEL = 3'b000, + parameter [0:0] TX_PMADATA_OPT = 1'b0, + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0, + parameter TX_PROGCLK_SEL = "POSTPI", + parameter real TX_PROGDIV_CFG = 0.0, + parameter [0:0] TX_QPI_STATUS_EN = 1'b0, + parameter [13:0] TX_RXDETECT_CFG = 14'h0032, + parameter [2:0] TX_RXDETECT_REF = 3'b100, + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101, + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0, + parameter TX_XCLK_SEL = "TXOUT", + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0, + parameter [1:0] WB_MODE = 2'b00 +)( + output [2:0] BUFGTCE, + output [2:0] BUFGTCEMASK, + output [8:0] BUFGTDIV, + output [2:0] BUFGTRESET, + output [2:0] BUFGTRSTMASK, + output CPLLFBCLKLOST, + output CPLLLOCK, + output CPLLREFCLKLOST, + output [16:0] DMONITOROUT, + output [15:0] DRPDO, + output DRPRDY, + output EYESCANDATAERROR, + output GTHTXN, + output GTHTXP, + output GTPOWERGOOD, + output GTREFCLKMONITOR, + output PCIERATEGEN3, + output PCIERATEIDLE, + output [1:0] PCIERATEQPLLPD, + output [1:0] PCIERATEQPLLRESET, + output PCIESYNCTXSYNCDONE, + output PCIEUSERGEN3RDY, + output PCIEUSERPHYSTATUSRST, + output PCIEUSERRATESTART, + output [11:0] PCSRSVDOUT, + output PHYSTATUS, + output [7:0] PINRSRVDAS, + output RESETEXCEPTION, + output [2:0] RXBUFSTATUS, + output RXBYTEISALIGNED, + output RXBYTEREALIGN, + output RXCDRLOCK, + output RXCDRPHDONE, + output RXCHANBONDSEQ, + output RXCHANISALIGNED, + output RXCHANREALIGN, + output [4:0] RXCHBONDO, + output [1:0] RXCLKCORCNT, + output RXCOMINITDET, + output RXCOMMADET, + output RXCOMSASDET, + output RXCOMWAKEDET, + output [15:0] RXCTRL0, + output [15:0] RXCTRL1, + output [7:0] RXCTRL2, + output [7:0] RXCTRL3, + output [127:0] RXDATA, + output [7:0] RXDATAEXTENDRSVD, + output [1:0] RXDATAVALID, + output RXDLYSRESETDONE, + output RXELECIDLE, + output [5:0] RXHEADER, + output [1:0] RXHEADERVALID, + output [6:0] RXMONITOROUT, + output RXOSINTDONE, + output RXOSINTSTARTED, + output RXOSINTSTROBEDONE, + output RXOSINTSTROBESTARTED, + output RXOUTCLK, + output RXOUTCLKFABRIC, + output RXOUTCLKPCS, + output RXPHALIGNDONE, + output RXPHALIGNERR, + output RXPMARESETDONE, + output RXPRBSERR, + output RXPRBSLOCKED, + output RXPRGDIVRESETDONE, + output RXQPISENN, + output RXQPISENP, + output RXRATEDONE, + output RXRECCLKOUT, + output RXRESETDONE, + output RXSLIDERDY, + output RXSLIPDONE, + output RXSLIPOUTCLKRDY, + output RXSLIPPMARDY, + output [1:0] RXSTARTOFSEQ, + output [2:0] RXSTATUS, + output RXSYNCDONE, + output RXSYNCOUT, + output RXVALID, + output [1:0] TXBUFSTATUS, + output TXCOMFINISH, + output TXDLYSRESETDONE, + output TXOUTCLK, + output TXOUTCLKFABRIC, + output TXOUTCLKPCS, + output TXPHALIGNDONE, + output TXPHINITDONE, + output TXPMARESETDONE, + output TXPRGDIVRESETDONE, + output TXQPISENN, + output TXQPISENP, + output TXRATEDONE, + output TXRESETDONE, + output TXSYNCDONE, + output TXSYNCOUT, + + input CFGRESET, + input CLKRSVD0, + input CLKRSVD1, + input CPLLLOCKDETCLK, + input CPLLLOCKEN, + input CPLLPD, + input [2:0] CPLLREFCLKSEL, + input CPLLRESET, + input DMONFIFORESET, + input DMONITORCLK, + input [8:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input EVODDPHICALDONE, + input EVODDPHICALSTART, + input EVODDPHIDRDEN, + input EVODDPHIDWREN, + input EVODDPHIXRDEN, + input EVODDPHIXWREN, + input EYESCANMODE, + input EYESCANRESET, + input EYESCANTRIGGER, + input GTGREFCLK, + input GTHRXN, + input GTHRXP, + input GTNORTHREFCLK0, + input GTNORTHREFCLK1, + input GTREFCLK0, + input GTREFCLK1, + input GTRESETSEL, + input [15:0] GTRSVD, + input GTRXRESET, + input GTSOUTHREFCLK0, + input GTSOUTHREFCLK1, + input GTTXRESET, + input [2:0] LOOPBACK, + input LPBKRXTXSEREN, + input LPBKTXRXSEREN, + input PCIEEQRXEQADAPTDONE, + input PCIERSTIDLE, + input PCIERSTTXSYNCSTART, + input PCIEUSERRATEDONE, + input [15:0] PCSRSVDIN, + input [4:0] PCSRSVDIN2, + input [4:0] PMARSVDIN, + input QPLL0CLK, + input QPLL0REFCLK, + input QPLL1CLK, + input QPLL1REFCLK, + input RESETOVRD, + input RSTCLKENTX, + input RX8B10BEN, + input RXBUFRESET, + input RXCDRFREQRESET, + input RXCDRHOLD, + input RXCDROVRDEN, + input RXCDRRESET, + input RXCDRRESETRSV, + input RXCHBONDEN, + input [4:0] RXCHBONDI, + input [2:0] RXCHBONDLEVEL, + input RXCHBONDMASTER, + input RXCHBONDSLAVE, + input RXCOMMADETEN, + input [1:0] RXDFEAGCCTRL, + input RXDFEAGCHOLD, + input RXDFEAGCOVRDEN, + input RXDFELFHOLD, + input RXDFELFOVRDEN, + input RXDFELPMRESET, + input RXDFETAP10HOLD, + input RXDFETAP10OVRDEN, + input RXDFETAP11HOLD, + input RXDFETAP11OVRDEN, + input RXDFETAP12HOLD, + input RXDFETAP12OVRDEN, + input RXDFETAP13HOLD, + input RXDFETAP13OVRDEN, + input RXDFETAP14HOLD, + input RXDFETAP14OVRDEN, + input RXDFETAP15HOLD, + input RXDFETAP15OVRDEN, + input RXDFETAP2HOLD, + input RXDFETAP2OVRDEN, + input RXDFETAP3HOLD, + input RXDFETAP3OVRDEN, + input RXDFETAP4HOLD, + input RXDFETAP4OVRDEN, + input RXDFETAP5HOLD, + input RXDFETAP5OVRDEN, + input RXDFETAP6HOLD, + input RXDFETAP6OVRDEN, + input RXDFETAP7HOLD, + input RXDFETAP7OVRDEN, + input RXDFETAP8HOLD, + input RXDFETAP8OVRDEN, + input RXDFETAP9HOLD, + input RXDFETAP9OVRDEN, + input RXDFEUTHOLD, + input RXDFEUTOVRDEN, + input RXDFEVPHOLD, + input RXDFEVPOVRDEN, + input RXDFEVSEN, + input RXDFEXYDEN, + input RXDLYBYPASS, + input RXDLYEN, + input RXDLYOVRDEN, + input RXDLYSRESET, + input [1:0] RXELECIDLEMODE, + input RXGEARBOXSLIP, + input RXLATCLK, + input RXLPMEN, + input RXLPMGCHOLD, + input RXLPMGCOVRDEN, + input RXLPMHFHOLD, + input RXLPMHFOVRDEN, + input RXLPMLFHOLD, + input RXLPMLFKLOVRDEN, + input RXLPMOSHOLD, + input RXLPMOSOVRDEN, + input RXMCOMMAALIGNEN, + input [1:0] RXMONITORSEL, + input RXOOBRESET, + input RXOSCALRESET, + input RXOSHOLD, + input [3:0] RXOSINTCFG, + input RXOSINTEN, + input RXOSINTHOLD, + input RXOSINTOVRDEN, + input RXOSINTSTROBE, + input RXOSINTTESTOVRDEN, + input RXOSOVRDEN, + input [2:0] RXOUTCLKSEL, + input RXPCOMMAALIGNEN, + input RXPCSRESET, + input [1:0] RXPD, + input RXPHALIGN, + input RXPHALIGNEN, + input RXPHDLYPD, + input RXPHDLYRESET, + input RXPHOVRDEN, + input [1:0] RXPLLCLKSEL, + input RXPMARESET, + input RXPOLARITY, + input RXPRBSCNTRESET, + input [3:0] RXPRBSSEL, + input RXPROGDIVRESET, + input RXQPIEN, + input [2:0] RXRATE, + input RXRATEMODE, + input RXSLIDE, + input RXSLIPOUTCLK, + input RXSLIPPMA, + input RXSYNCALLIN, + input RXSYNCIN, + input RXSYNCMODE, + input [1:0] RXSYSCLKSEL, + input RXUSERRDY, + input RXUSRCLK, + input RXUSRCLK2, + input SIGVALIDCLK, + input [19:0] TSTIN, + input [7:0] TX8B10BBYPASS, + input TX8B10BEN, + input [2:0] TXBUFDIFFCTRL, + input TXCOMINIT, + input TXCOMSAS, + input TXCOMWAKE, + input [15:0] TXCTRL0, + input [15:0] TXCTRL1, + input [7:0] TXCTRL2, + input [127:0] TXDATA, + input [7:0] TXDATAEXTENDRSVD, + input TXDEEMPH, + input TXDETECTRX, + input [3:0] TXDIFFCTRL, + input TXDIFFPD, + input TXDLYBYPASS, + input TXDLYEN, + input TXDLYHOLD, + input TXDLYOVRDEN, + input TXDLYSRESET, + input TXDLYUPDOWN, + input TXELECIDLE, + input [5:0] TXHEADER, + input TXINHIBIT, + input TXLATCLK, + input [6:0] TXMAINCURSOR, + input [2:0] TXMARGIN, + input [2:0] TXOUTCLKSEL, + input TXPCSRESET, + input [1:0] TXPD, + input TXPDELECIDLEMODE, + input TXPHALIGN, + input TXPHALIGNEN, + input TXPHDLYPD, + input TXPHDLYRESET, + input TXPHDLYTSTCLK, + input TXPHINIT, + input TXPHOVRDEN, + input TXPIPPMEN, + input TXPIPPMOVRDEN, + input TXPIPPMPD, + input TXPIPPMSEL, + input [4:0] TXPIPPMSTEPSIZE, + input TXPISOPD, + input [1:0] TXPLLCLKSEL, + input TXPMARESET, + input TXPOLARITY, + input [4:0] TXPOSTCURSOR, + input TXPOSTCURSORINV, + input TXPRBSFORCEERR, + input [3:0] TXPRBSSEL, + input [4:0] TXPRECURSOR, + input TXPRECURSORINV, + input TXPROGDIVRESET, + input TXQPIBIASEN, + input TXQPISTRONGPDOWN, + input TXQPIWEAKPUP, + input [2:0] TXRATE, + input TXRATEMODE, + input [6:0] TXSEQUENCE, + input TXSWING, + input TXSYNCALLIN, + input TXSYNCIN, + input TXSYNCMODE, + input [1:0] TXSYSCLKSEL, + input TXUSERRDY, + input TXUSRCLK, + input TXUSRCLK2 +); + +// define constants + localparam MODULE_NAME = "GTHE3_CHANNEL"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "GTHE3_CHANNEL_dr.v" +`else + localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE; + localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE; + localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET; + localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0; + localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1; + localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE; + localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE; + localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD; + localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET; + localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE; + localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET; + localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE; + localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET; + localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET; + localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET; + localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL; + localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN; + localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN; + localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW; + localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1; + localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2; + localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3; + localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4; + localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE; + localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1; + localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2; + localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3; + localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4; + localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE; + localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE; + localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN; + localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE; + localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE; + localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT; + localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT; + localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE; + localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT; + localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1; + localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2; + localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3; + localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4; + localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE; + localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1; + localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2; + localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3; + localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4; + localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE; + localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE; + localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN; + localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0; + localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1; + localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2; + localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3; + localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV; + localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45; + localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0; + localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1; + localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG; + localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV; + localparam [1:0] DDI_CTRL_REG = DDI_CTRL; + localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT; + localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT; + localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT; + localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY; + localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS; + localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN; + localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0; + localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1; + localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL; + localparam [5:0] ES_CONTROL_REG = ES_CONTROL; + localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN; + localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN; + localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET; + localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG; + localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE; + localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0; + localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1; + localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2; + localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3; + localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4; + localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0; + localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1; + localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2; + localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3; + localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4; + localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0; + localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1; + localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2; + localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3; + localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4; + localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG; + localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN; + localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE; + localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG; + localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN; + localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE; + localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT; + localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER; + localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL; + localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP; + localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN; + localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE; + localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS; + localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE; + localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT; + localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE; + localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT; + localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE; + localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE; + localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL; + localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3; + localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG; + localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3; + localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG; + localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN; + localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0; + localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1; + localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2; + localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2; + localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2; + localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12; + localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3; + localparam [15:0] PMA_RSV1_REG = PMA_RSV1; + localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR; + localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP; + localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE; + localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME; + localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE; + localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT; + localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT; + localparam [40:1] RXBUF_EN_REG = RXBUF_EN; + localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE; + localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN; + localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE; + localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE; + localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW; + localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD; + localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW; + localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME; + localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME; + localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0; + localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3; + localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1; + localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3; + localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2; + localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3; + localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3; + localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3; + localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4; + localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3; + localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5; + localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3; + localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE; + localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE; + localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0; + localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1; + localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2; + localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE; + localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0; + localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1; + localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2; + localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME; + localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0; + localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1; + localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2; + localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0; + localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1; + localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0; + localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1; + localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2; + localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0; + localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1; + localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0; + localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1; + localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0; + localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1; + localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0; + localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1; + localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0; + localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1; + localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0; + localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1; + localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0; + localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1; + localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0; + localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1; + localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0; + localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1; + localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0; + localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1; + localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0; + localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1; + localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0; + localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1; + localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0; + localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1; + localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0; + localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1; + localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0; + localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1; + localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0; + localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1; + localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0; + localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1; + localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG; + localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG; + localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG; + localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR; + localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN; + localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME; + localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG; + localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG; + localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0; + localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1; + localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0; + localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1; + localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG; + localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG; + localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME; + localparam [4:0] RXOUT_DIV_REG = RXOUT_DIV; + localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME; + localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG; + localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG; + localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG; + localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG; + localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL; + localparam [1:0] RXPI_CFG0_REG = RXPI_CFG0; + localparam [1:0] RXPI_CFG1_REG = RXPI_CFG1; + localparam [1:0] RXPI_CFG2_REG = RXPI_CFG2; + localparam [1:0] RXPI_CFG3_REG = RXPI_CFG3; + localparam [0:0] RXPI_CFG4_REG = RXPI_CFG4; + localparam [0:0] RXPI_CFG5_REG = RXPI_CFG5; + localparam [2:0] RXPI_CFG6_REG = RXPI_CFG6; + localparam [0:0] RXPI_LPM_REG = RXPI_LPM; + localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL; + localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL; + localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME; + localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK; + localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT; + localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT; + localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE; + localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE; + localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD; + localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA; + localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN; + localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0; + localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG; + localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB; + localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV; + localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN; + localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD; + localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG; + localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD; + localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL; + localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM; + localparam [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF; + localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH; + localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL; + localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN; + localparam [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0; + localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1; + localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN; + localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0; + localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1; + localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0; + localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1; + localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0; + localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1; + localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE; + localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH; + localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME; + localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR; + localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE; + localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR; + localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE; + localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN; + localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP; + localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH; + localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE; + localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG; + localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD; + localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY; + localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN; + localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE; + localparam [1:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL; + localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE; + localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR; + localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE; + localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS; + localparam [0:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR; + localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL; + localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM; + localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM; + localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN; + localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL; + localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG; + localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL; + localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST; + localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT; + localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE; + localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST; + localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT; + localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE; + localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA; + localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS; + localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL; + localparam [1:0] SIM_VERSION_REG = SIM_VERSION; + localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX; + localparam [3:0] TEMPERATUR_PAR_REG = TEMPERATUR_PAR; + localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG; + localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD; + localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE; + localparam [7:0] TST_RSV0_REG = TST_RSV0; + localparam [7:0] TST_RSV1_REG = TST_RSV1; + localparam [40:1] TXBUF_EN_REG = TXBUF_EN; + localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE; + localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG; + localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG; + localparam [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N; + localparam [3:0] TXDRVBIAS_P_REG = TXDRVBIAS_P; + localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG; + localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR; + localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN; + localparam [4:0] TXOUT_DIV_REG = TXOUT_DIV; + localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME; + localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0; + localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1; + localparam [15:0] TXPH_CFG_REG = TXPH_CFG; + localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL; + localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0; + localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1; + localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2; + localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3; + localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4; + localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5; + localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL; + localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL; + localparam [0:0] TXPI_LPM_REG = TXPI_LPM; + localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL; + localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG; + localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM; + localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL; + localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME; + localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE; + localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD; + localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA; + localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV; + localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN; + localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH; + localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG; + localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN; + localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0; + localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1; + localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME; + localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE; + localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY; + localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY; + localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE; + localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP; + localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO; + localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH; + localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ; + localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL; + localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0; + localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1; + localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2; + localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3; + localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4; + localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0; + localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1; + localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2; + localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3; + localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4; + localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL; + localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT; + localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE; + localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL; + localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG; + localparam [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN; + localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG; + localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF; + localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD; + localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB; + localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL; + localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL; + localparam [1:0] WB_MODE_REG = WB_MODE; + localparam [80:1] SIM_MODE_REG = SIM_MODE; +`endif + + localparam [0:0] AEN_CPLL_REG = 1'b0; + localparam [0:0] AEN_EYESCAN_REG = 1'b1; + localparam [0:0] AEN_LOOPBACK_REG = 1'b0; + localparam [0:0] AEN_MASTER_REG = 1'b0; + localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0; + localparam [0:0] AEN_POLARITY_REG = 1'b0; + localparam [0:0] AEN_PRBS_REG = 1'b0; + localparam [0:0] AEN_QPI_REG = 1'b0; + localparam [0:0] AEN_RESET_REG = 1'b0; + localparam [0:0] AEN_RXCDR_REG = 1'b0; + localparam [0:0] AEN_RXDFE_REG = 1'b0; + localparam [0:0] AEN_RXDFELPM_REG = 1'b0; + localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_RXPHDLY_REG = 1'b0; + localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXPHDLY_REG = 1'b0; + localparam [0:0] AEN_TXPI_PPM_REG = 1'b0; + localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0; + localparam [15:0] AMONITOR_CFG_REG = 16'h0000; + localparam [0:0] A_AFECFOKEN_REG = 1'b0; + localparam [0:0] A_CPLLLOCKEN_REG = 1'b0; + localparam [0:0] A_CPLLPD_REG = 1'b0; + localparam [0:0] A_CPLLRESET_REG = 1'b0; + localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000; + localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000; + localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0; + localparam [0:0] A_DFECFOKHOLD_REG = 1'b0; + localparam [0:0] A_DFECFOKOVREN_REG = 1'b0; + localparam [0:0] A_EYESCANMODE_REG = 1'b0; + localparam [0:0] A_EYESCANRESET_REG = 1'b0; + localparam [0:0] A_GTRESETSEL_REG = 1'b0; + localparam [0:0] A_GTRXRESET_REG = 1'b0; + localparam [0:0] A_GTTXRESET_REG = 1'b0; + localparam [80:1] A_LOOPBACK_REG = "NoLoopBack"; + localparam [0:0] A_LPMGCHOLD_REG = 1'b0; + localparam [0:0] A_LPMGCOVREN_REG = 1'b0; + localparam [0:0] A_LPMOSHOLD_REG = 1'b0; + localparam [0:0] A_LPMOSOVREN_REG = 1'b0; + localparam [0:0] A_RXBUFRESET_REG = 1'b0; + localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0; + localparam [0:0] A_RXCDRHOLD_REG = 1'b0; + localparam [0:0] A_RXCDROVRDEN_REG = 1'b0; + localparam [0:0] A_RXCDRRESET_REG = 1'b0; + localparam [1:0] A_RXDFEAGCCTRL_REG = 2'b00; + localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0; + localparam [0:0] A_RXDFELFHOLD_REG = 1'b0; + localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFELPMRESET_REG = 1'b0; + localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEVSEN_REG = 1'b0; + localparam [0:0] A_RXDFEXYDEN_REG = 1'b0; + localparam [0:0] A_RXDLYBYPASS_REG = 1'b0; + localparam [0:0] A_RXDLYEN_REG = 1'b0; + localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDLYSRESET_REG = 1'b0; + localparam [0:0] A_RXLPMEN_REG = 1'b0; + localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0; + localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0; + localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0; + localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0; + localparam [1:0] A_RXMONITORSEL_REG = 2'b00; + localparam [0:0] A_RXOOBRESET_REG = 1'b0; + localparam [0:0] A_RXOSHOLD_REG = 1'b0; + localparam [0:0] A_RXOSOVRDEN_REG = 1'b0; + localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled"; + localparam [0:0] A_RXPCSRESET_REG = 1'b0; + localparam [24:1] A_RXPD_REG = "P0"; + localparam [0:0] A_RXPHALIGN_REG = 1'b0; + localparam [0:0] A_RXPHALIGNEN_REG = 1'b0; + localparam [0:0] A_RXPHDLYPD_REG = 1'b0; + localparam [0:0] A_RXPHDLYRESET_REG = 1'b0; + localparam [0:0] A_RXPHOVRDEN_REG = 1'b0; + localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK"; + localparam [0:0] A_RXPMARESET_REG = 1'b0; + localparam [0:0] A_RXPOLARITY_REG = 1'b0; + localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0; + localparam [48:1] A_RXPRBSSEL_REG = "PRBS7"; + localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK"; + localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100; + localparam [0:0] A_TXDEEMPH_REG = 1'b0; + localparam [3:0] A_TXDIFFCTRL_REG = 4'b1100; + localparam [0:0] A_TXDLYBYPASS_REG = 1'b0; + localparam [0:0] A_TXDLYEN_REG = 1'b0; + localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0; + localparam [0:0] A_TXDLYSRESET_REG = 1'b0; + localparam [0:0] A_TXELECIDLE_REG = 1'b0; + localparam [0:0] A_TXINHIBIT_REG = 1'b0; + localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000; + localparam [2:0] A_TXMARGIN_REG = 3'b000; + localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled"; + localparam [0:0] A_TXPCSRESET_REG = 1'b0; + localparam [24:1] A_TXPD_REG = "P0"; + localparam [0:0] A_TXPHALIGN_REG = 1'b0; + localparam [0:0] A_TXPHALIGNEN_REG = 1'b0; + localparam [0:0] A_TXPHDLYPD_REG = 1'b0; + localparam [0:0] A_TXPHDLYRESET_REG = 1'b0; + localparam [0:0] A_TXPHINIT_REG = 1'b0; + localparam [0:0] A_TXPHOVRDEN_REG = 1'b0; + localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0; + localparam [0:0] A_TXPIPPMPD_REG = 1'b0; + localparam [0:0] A_TXPIPPMSEL_REG = 1'b0; + localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK"; + localparam [0:0] A_TXPMARESET_REG = 1'b0; + localparam [0:0] A_TXPOLARITY_REG = 1'b0; + localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000; + localparam [0:0] A_TXPOSTCURSORINV_REG = 1'b0; + localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0; + localparam [96:1] A_TXPRBSSEL_REG = "PRBS7"; + localparam [4:0] A_TXPRECURSOR_REG = 5'b00000; + localparam [0:0] A_TXPRECURSORINV_REG = 1'b0; + localparam [0:0] A_TXQPIBIASEN_REG = 1'b0; + localparam [0:0] A_TXSWING_REG = 1'b0; + localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK"; + localparam [40:1] GEN_RXUSRCLK_REG = "TRUE"; + localparam [40:1] GEN_TXUSRCLK_REG = "TRUE"; + localparam [0:0] GT_INSTANTIATED_REG = 1'b1; + localparam [40:1] RXPLL_SEL_REG = "CPLL"; + localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0; + localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100; + localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101; + localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011; + localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010; + + wire [63:0] RX_PROGDIV_CFG_BIN; + wire [63:0] TX_PROGDIV_CFG_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CPLLFBCLKLOST_out; + wire CPLLLOCK_out; + wire CPLLREFCLKLOST_out; + wire DRPRDY_out; + wire EYESCANDATAERROR_out; + wire GTHTXN_out; + wire GTHTXP_out; + wire GTPOWERGOOD_out; + wire GTREFCLKMONITOR_out; + wire PCIERATEGEN3_out; + wire PCIERATEIDLE_out; + wire PCIESYNCTXSYNCDONE_out; + wire PCIEUSERGEN3RDY_out; + wire PCIEUSERPHYSTATUSRST_out; + wire PCIEUSERRATESTART_out; + wire PHYSTATUS_out; + wire RESETEXCEPTION_out; + wire RXBYTEISALIGNED_out; + wire RXBYTEREALIGN_out; + wire RXCDRLOCK_out; + wire RXCDRPHDONE_out; + wire RXCHANBONDSEQ_out; + wire RXCHANISALIGNED_out; + wire RXCHANREALIGN_out; + wire RXCOMINITDET_out; + wire RXCOMMADET_out; + wire RXCOMSASDET_out; + wire RXCOMWAKEDET_out; + wire RXDLYSRESETDONE_out; + wire RXELECIDLE_out; + wire RXOSINTDONE_out; + wire RXOSINTSTARTED_out; + wire RXOSINTSTROBEDONE_out; + wire RXOSINTSTROBESTARTED_out; + wire RXOUTCLKFABRIC_out; + wire RXOUTCLKPCS_out; + wire RXOUTCLK_out; + wire RXPHALIGNDONE_out; + wire RXPHALIGNERR_out; + wire RXPMARESETDONE_out; + wire RXPRBSERR_out; + wire RXPRBSLOCKED_out; + wire RXPRGDIVRESETDONE_out; + wire RXQPISENN_out; + wire RXQPISENP_out; + wire RXRATEDONE_out; + wire RXRECCLKOUT_out; + wire RXRESETDONE_out; + wire RXSLIDERDY_out; + wire RXSLIPDONE_out; + wire RXSLIPOUTCLKRDY_out; + wire RXSLIPPMARDY_out; + wire RXSYNCDONE_out; + wire RXSYNCOUT_out; + wire RXVALID_out; + wire TXCOMFINISH_out; + wire TXDLYSRESETDONE_out; + wire TXOUTCLKFABRIC_out; + wire TXOUTCLKPCS_out; + wire TXOUTCLK_out; + wire TXPHALIGNDONE_out; + wire TXPHINITDONE_out; + wire TXPMARESETDONE_out; + wire TXPRGDIVRESETDONE_out; + wire TXQPISENN_out; + wire TXQPISENP_out; + wire TXRATEDONE_out; + wire TXRESETDONE_out; + wire TXSYNCDONE_out; + wire TXSYNCOUT_out; + wire [11:0] PCSRSVDOUT_out; + wire [11:0] PMASCANOUT_out; + wire [127:0] RXDATA_out; + wire [15:0] DRPDO_out; + wire [15:0] RXCTRL0_out; + wire [15:0] RXCTRL1_out; + wire [16:0] DMONITOROUT_out; + wire [18:0] SCANOUT_out; + wire [1:0] PCIERATEQPLLPD_out; + wire [1:0] PCIERATEQPLLRESET_out; + wire [1:0] RXCLKCORCNT_out; + wire [1:0] RXDATAVALID_out; + wire [1:0] RXHEADERVALID_out; + wire [1:0] RXSTARTOFSEQ_out; + wire [1:0] TXBUFSTATUS_out; + wire [2:0] BUFGTCEMASK_out; + wire [2:0] BUFGTCE_out; + wire [2:0] BUFGTRESET_out; + wire [2:0] BUFGTRSTMASK_out; + wire [2:0] RXBUFSTATUS_out; + wire [2:0] RXSTATUS_out; + wire [4:0] RXCHBONDO_out; + wire [5:0] RXHEADER_out; + wire [6:0] RXMONITOROUT_out; + wire [7:0] PINRSRVDAS_out; + wire [7:0] RXCTRL2_out; + wire [7:0] RXCTRL3_out; + wire [7:0] RXDATAEXTENDRSVD_out; + wire [8:0] BUFGTDIV_out; + + wire CPLLFBCLKLOST_delay; + wire CPLLLOCK_delay; + wire CPLLREFCLKLOST_delay; + wire DRPRDY_delay; + wire EYESCANDATAERROR_delay; + wire GTHTXN_delay; + wire GTHTXP_delay; + wire GTPOWERGOOD_delay; + wire GTREFCLKMONITOR_delay; + wire PCIERATEGEN3_delay; + wire PCIERATEIDLE_delay; + wire PCIESYNCTXSYNCDONE_delay; + wire PCIEUSERGEN3RDY_delay; + wire PCIEUSERPHYSTATUSRST_delay; + wire PCIEUSERRATESTART_delay; + wire PHYSTATUS_delay; + wire RESETEXCEPTION_delay; + wire RXBYTEISALIGNED_delay; + wire RXBYTEREALIGN_delay; + wire RXCDRLOCK_delay; + wire RXCDRPHDONE_delay; + wire RXCHANBONDSEQ_delay; + wire RXCHANISALIGNED_delay; + wire RXCHANREALIGN_delay; + wire RXCOMINITDET_delay; + wire RXCOMMADET_delay; + wire RXCOMSASDET_delay; + wire RXCOMWAKEDET_delay; + wire RXDLYSRESETDONE_delay; + wire RXELECIDLE_delay; + wire RXOSINTDONE_delay; + wire RXOSINTSTARTED_delay; + wire RXOSINTSTROBEDONE_delay; + wire RXOSINTSTROBESTARTED_delay; + wire RXOUTCLKFABRIC_delay; + wire RXOUTCLKPCS_delay; + wire RXOUTCLK_delay; + wire RXPHALIGNDONE_delay; + wire RXPHALIGNERR_delay; + wire RXPMARESETDONE_delay; + wire RXPRBSERR_delay; + wire RXPRBSLOCKED_delay; + wire RXPRGDIVRESETDONE_delay; + wire RXQPISENN_delay; + wire RXQPISENP_delay; + wire RXRATEDONE_delay; + wire RXRECCLKOUT_delay; + wire RXRESETDONE_delay; + wire RXSLIDERDY_delay; + wire RXSLIPDONE_delay; + wire RXSLIPOUTCLKRDY_delay; + wire RXSLIPPMARDY_delay; + wire RXSYNCDONE_delay; + wire RXSYNCOUT_delay; + wire RXVALID_delay; + wire TXCOMFINISH_delay; + wire TXDLYSRESETDONE_delay; + wire TXOUTCLKFABRIC_delay; + wire TXOUTCLKPCS_delay; + wire TXOUTCLK_delay; + wire TXPHALIGNDONE_delay; + wire TXPHINITDONE_delay; + wire TXPMARESETDONE_delay; + wire TXPRGDIVRESETDONE_delay; + wire TXQPISENN_delay; + wire TXQPISENP_delay; + wire TXRATEDONE_delay; + wire TXRESETDONE_delay; + wire TXSYNCDONE_delay; + wire TXSYNCOUT_delay; + wire [11:0] PCSRSVDOUT_delay; + wire [127:0] RXDATA_delay; + wire [15:0] DRPDO_delay; + wire [15:0] RXCTRL0_delay; + wire [15:0] RXCTRL1_delay; + wire [16:0] DMONITOROUT_delay; + wire [1:0] PCIERATEQPLLPD_delay; + wire [1:0] PCIERATEQPLLRESET_delay; + wire [1:0] RXCLKCORCNT_delay; + wire [1:0] RXDATAVALID_delay; + wire [1:0] RXHEADERVALID_delay; + wire [1:0] RXSTARTOFSEQ_delay; + wire [1:0] TXBUFSTATUS_delay; + wire [2:0] BUFGTCEMASK_delay; + wire [2:0] BUFGTCE_delay; + wire [2:0] BUFGTRESET_delay; + wire [2:0] BUFGTRSTMASK_delay; + wire [2:0] RXBUFSTATUS_delay; + wire [2:0] RXSTATUS_delay; + wire [4:0] RXCHBONDO_delay; + wire [5:0] RXHEADER_delay; + wire [6:0] RXMONITOROUT_delay; + wire [7:0] PINRSRVDAS_delay; + wire [7:0] RXCTRL2_delay; + wire [7:0] RXCTRL3_delay; + wire [7:0] RXDATAEXTENDRSVD_delay; + wire [8:0] BUFGTDIV_delay; + + wire CFGRESET_in; + wire CLKRSVD0_in; + wire CLKRSVD1_in; + wire CPLLLOCKDETCLK_in; + wire CPLLLOCKEN_in; + wire CPLLPD_in; + wire CPLLRESET_in; + wire DMONFIFORESET_in; + wire DMONITORCLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire EVODDPHICALDONE_in; + wire EVODDPHICALSTART_in; + wire EVODDPHIDRDEN_in; + wire EVODDPHIDWREN_in; + wire EVODDPHIXRDEN_in; + wire EVODDPHIXWREN_in; + wire EYESCANMODE_in; + wire EYESCANRESET_in; + wire EYESCANTRIGGER_in; + wire GTGREFCLK_in; + wire GTHRXN_in; + wire GTHRXP_in; + wire GTNORTHREFCLK0_in; + wire GTNORTHREFCLK1_in; + wire GTREFCLK0_in; + wire GTREFCLK1_in; + wire GTRESETSEL_in; + wire GTRXRESET_in; + wire GTSOUTHREFCLK0_in; + wire GTSOUTHREFCLK1_in; + wire GTTXRESET_in; + wire LPBKRXTXSEREN_in; + wire LPBKTXRXSEREN_in; + wire PCIEEQRXEQADAPTDONE_in; + wire PCIERSTIDLE_in; + wire PCIERSTTXSYNCSTART_in; + wire PCIEUSERRATEDONE_in; + wire PMASCANCLK0_in; + wire PMASCANCLK1_in; + wire PMASCANCLK2_in; + wire PMASCANCLK3_in; + wire PMASCANCLK4_in; + wire PMASCANCLK5_in; + wire PMASCANENB_in; + wire PMASCANMODEB_in; + wire PMASCANRSTEN_in; + wire QPLL0CLK_in; + wire QPLL0REFCLK_in; + wire QPLL1CLK_in; + wire QPLL1REFCLK_in; + wire RESETOVRD_in; + wire RSTCLKENTX_in; + wire RX8B10BEN_in; + wire RXBUFRESET_in; + wire RXCDRFREQRESET_in; + wire RXCDRHOLD_in; + wire RXCDROVRDEN_in; + wire RXCDRRESETRSV_in; + wire RXCDRRESET_in; + wire RXCHBONDEN_in; + wire RXCHBONDMASTER_in; + wire RXCHBONDSLAVE_in; + wire RXCOMMADETEN_in; + wire RXDFEAGCHOLD_in; + wire RXDFEAGCOVRDEN_in; + wire RXDFELFHOLD_in; + wire RXDFELFOVRDEN_in; + wire RXDFELPMRESET_in; + wire RXDFETAP10HOLD_in; + wire RXDFETAP10OVRDEN_in; + wire RXDFETAP11HOLD_in; + wire RXDFETAP11OVRDEN_in; + wire RXDFETAP12HOLD_in; + wire RXDFETAP12OVRDEN_in; + wire RXDFETAP13HOLD_in; + wire RXDFETAP13OVRDEN_in; + wire RXDFETAP14HOLD_in; + wire RXDFETAP14OVRDEN_in; + wire RXDFETAP15HOLD_in; + wire RXDFETAP15OVRDEN_in; + wire RXDFETAP2HOLD_in; + wire RXDFETAP2OVRDEN_in; + wire RXDFETAP3HOLD_in; + wire RXDFETAP3OVRDEN_in; + wire RXDFETAP4HOLD_in; + wire RXDFETAP4OVRDEN_in; + wire RXDFETAP5HOLD_in; + wire RXDFETAP5OVRDEN_in; + wire RXDFETAP6HOLD_in; + wire RXDFETAP6OVRDEN_in; + wire RXDFETAP7HOLD_in; + wire RXDFETAP7OVRDEN_in; + wire RXDFETAP8HOLD_in; + wire RXDFETAP8OVRDEN_in; + wire RXDFETAP9HOLD_in; + wire RXDFETAP9OVRDEN_in; + wire RXDFEUTHOLD_in; + wire RXDFEUTOVRDEN_in; + wire RXDFEVPHOLD_in; + wire RXDFEVPOVRDEN_in; + wire RXDFEVSEN_in; + wire RXDFEXYDEN_in; + wire RXDLYBYPASS_in; + wire RXDLYEN_in; + wire RXDLYOVRDEN_in; + wire RXDLYSRESET_in; + wire RXGEARBOXSLIP_in; + wire RXLATCLK_in; + wire RXLPMEN_in; + wire RXLPMGCHOLD_in; + wire RXLPMGCOVRDEN_in; + wire RXLPMHFHOLD_in; + wire RXLPMHFOVRDEN_in; + wire RXLPMLFHOLD_in; + wire RXLPMLFKLOVRDEN_in; + wire RXLPMOSHOLD_in; + wire RXLPMOSOVRDEN_in; + wire RXMCOMMAALIGNEN_in; + wire RXOOBRESET_in; + wire RXOSCALRESET_in; + wire RXOSHOLD_in; + wire RXOSINTEN_in; + wire RXOSINTHOLD_in; + wire RXOSINTOVRDEN_in; + wire RXOSINTSTROBE_in; + wire RXOSINTTESTOVRDEN_in; + wire RXOSOVRDEN_in; + wire RXPCOMMAALIGNEN_in; + wire RXPCSRESET_in; + wire RXPHALIGNEN_in; + wire RXPHALIGN_in; + wire RXPHDLYPD_in; + wire RXPHDLYRESET_in; + wire RXPHOVRDEN_in; + wire RXPMARESET_in; + wire RXPOLARITY_in; + wire RXPRBSCNTRESET_in; + wire RXPROGDIVRESET_in; + wire RXQPIEN_in; + wire RXRATEMODE_in; + wire RXSLIDE_in; + wire RXSLIPOUTCLK_in; + wire RXSLIPPMA_in; + wire RXSYNCALLIN_in; + wire RXSYNCIN_in; + wire RXSYNCMODE_in; + wire RXUSERRDY_in; + wire RXUSRCLK2_in; + wire RXUSRCLK_in; + wire SARCCLK_in; + wire SCANCLK_in; + wire SCANENB_in; + wire SCANMODEB_in; + wire SIGVALIDCLK_in; + wire TSTCLK0_in; + wire TSTCLK1_in; + wire TSTPDOVRDB_in; + wire TX8B10BEN_in; + wire TXCOMINIT_in; + wire TXCOMSAS_in; + wire TXCOMWAKE_in; + wire TXDEEMPH_in; + wire TXDETECTRX_in; + wire TXDIFFPD_in; + wire TXDLYBYPASS_in; + wire TXDLYEN_in; + wire TXDLYHOLD_in; + wire TXDLYOVRDEN_in; + wire TXDLYSRESET_in; + wire TXDLYUPDOWN_in; + wire TXELECIDLE_in; + wire TXINHIBIT_in; + wire TXLATCLK_in; + wire TXPCSRESET_in; + wire TXPDELECIDLEMODE_in; + wire TXPHALIGNEN_in; + wire TXPHALIGN_in; + wire TXPHDLYPD_in; + wire TXPHDLYRESET_in; + wire TXPHDLYTSTCLK_in; + wire TXPHINIT_in; + wire TXPHOVRDEN_in; + wire TXPIPPMEN_in; + wire TXPIPPMOVRDEN_in; + wire TXPIPPMPD_in; + wire TXPIPPMSEL_in; + wire TXPISOPD_in; + wire TXPMARESET_in; + wire TXPOLARITY_in; + wire TXPOSTCURSORINV_in; + wire TXPRBSFORCEERR_in; + wire TXPRECURSORINV_in; + wire TXPROGDIVRESET_in; + wire TXQPIBIASEN_in; + wire TXQPISTRONGPDOWN_in; + wire TXQPIWEAKPUP_in; + wire TXRATEMODE_in; + wire TXSWING_in; + wire TXSYNCALLIN_in; + wire TXSYNCIN_in; + wire TXSYNCMODE_in; + wire TXUSERRDY_in; + wire TXUSRCLK2_in; + wire TXUSRCLK_in; + wire [11:0] PMASCANIN_in; + wire [127:0] TXDATA_in; + wire [15:0] DRPDI_in; + wire [15:0] GTRSVD_in; + wire [15:0] PCSRSVDIN_in; + wire [15:0] TXCTRL0_in; + wire [15:0] TXCTRL1_in; + wire [18:0] SCANIN_in; + wire [19:0] TSTIN_in; + wire [1:0] RXDFEAGCCTRL_in; + wire [1:0] RXELECIDLEMODE_in; + wire [1:0] RXMONITORSEL_in; + wire [1:0] RXPD_in; + wire [1:0] RXPLLCLKSEL_in; + wire [1:0] RXSYSCLKSEL_in; + wire [1:0] TXPD_in; + wire [1:0] TXPLLCLKSEL_in; + wire [1:0] TXSYSCLKSEL_in; + wire [2:0] CPLLREFCLKSEL_in; + wire [2:0] LOOPBACK_in; + wire [2:0] RXCHBONDLEVEL_in; + wire [2:0] RXOUTCLKSEL_in; + wire [2:0] RXRATE_in; + wire [2:0] TXBUFDIFFCTRL_in; + wire [2:0] TXMARGIN_in; + wire [2:0] TXOUTCLKSEL_in; + wire [2:0] TXRATE_in; + wire [3:0] RXOSINTCFG_in; + wire [3:0] RXPRBSSEL_in; + wire [3:0] TXDIFFCTRL_in; + wire [3:0] TXPRBSSEL_in; + wire [4:0] PCSRSVDIN2_in; + wire [4:0] PMARSVDIN_in; + wire [4:0] RXCHBONDI_in; + wire [4:0] TSTPD_in; + wire [4:0] TXPIPPMSTEPSIZE_in; + wire [4:0] TXPOSTCURSOR_in; + wire [4:0] TXPRECURSOR_in; + wire [5:0] TXHEADER_in; + wire [6:0] TXMAINCURSOR_in; + wire [6:0] TXSEQUENCE_in; + wire [7:0] TX8B10BBYPASS_in; + wire [7:0] TXCTRL2_in; + wire [7:0] TXDATAEXTENDRSVD_in; + wire [8:0] DRPADDR_in; + + wire CFGRESET_delay; + wire CLKRSVD0_delay; + wire CLKRSVD1_delay; + wire CPLLLOCKDETCLK_delay; + wire CPLLLOCKEN_delay; + wire CPLLPD_delay; + wire CPLLRESET_delay; + wire DMONFIFORESET_delay; + wire DMONITORCLK_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire EVODDPHICALDONE_delay; + wire EVODDPHICALSTART_delay; + wire EVODDPHIDRDEN_delay; + wire EVODDPHIDWREN_delay; + wire EVODDPHIXRDEN_delay; + wire EVODDPHIXWREN_delay; + wire EYESCANMODE_delay; + wire EYESCANRESET_delay; + wire EYESCANTRIGGER_delay; + wire GTGREFCLK_delay; + wire GTHRXN_delay; + wire GTHRXP_delay; + wire GTNORTHREFCLK0_delay; + wire GTNORTHREFCLK1_delay; + wire GTREFCLK0_delay; + wire GTREFCLK1_delay; + wire GTRESETSEL_delay; + wire GTRXRESET_delay; + wire GTSOUTHREFCLK0_delay; + wire GTSOUTHREFCLK1_delay; + wire GTTXRESET_delay; + wire LPBKRXTXSEREN_delay; + wire LPBKTXRXSEREN_delay; + wire PCIEEQRXEQADAPTDONE_delay; + wire PCIERSTIDLE_delay; + wire PCIERSTTXSYNCSTART_delay; + wire PCIEUSERRATEDONE_delay; + wire QPLL0CLK_delay; + wire QPLL0REFCLK_delay; + wire QPLL1CLK_delay; + wire QPLL1REFCLK_delay; + wire RESETOVRD_delay; + wire RSTCLKENTX_delay; + wire RX8B10BEN_delay; + wire RXBUFRESET_delay; + wire RXCDRFREQRESET_delay; + wire RXCDRHOLD_delay; + wire RXCDROVRDEN_delay; + wire RXCDRRESETRSV_delay; + wire RXCDRRESET_delay; + wire RXCHBONDEN_delay; + wire RXCHBONDMASTER_delay; + wire RXCHBONDSLAVE_delay; + wire RXCOMMADETEN_delay; + wire RXDFEAGCHOLD_delay; + wire RXDFEAGCOVRDEN_delay; + wire RXDFELFHOLD_delay; + wire RXDFELFOVRDEN_delay; + wire RXDFELPMRESET_delay; + wire RXDFETAP10HOLD_delay; + wire RXDFETAP10OVRDEN_delay; + wire RXDFETAP11HOLD_delay; + wire RXDFETAP11OVRDEN_delay; + wire RXDFETAP12HOLD_delay; + wire RXDFETAP12OVRDEN_delay; + wire RXDFETAP13HOLD_delay; + wire RXDFETAP13OVRDEN_delay; + wire RXDFETAP14HOLD_delay; + wire RXDFETAP14OVRDEN_delay; + wire RXDFETAP15HOLD_delay; + wire RXDFETAP15OVRDEN_delay; + wire RXDFETAP2HOLD_delay; + wire RXDFETAP2OVRDEN_delay; + wire RXDFETAP3HOLD_delay; + wire RXDFETAP3OVRDEN_delay; + wire RXDFETAP4HOLD_delay; + wire RXDFETAP4OVRDEN_delay; + wire RXDFETAP5HOLD_delay; + wire RXDFETAP5OVRDEN_delay; + wire RXDFETAP6HOLD_delay; + wire RXDFETAP6OVRDEN_delay; + wire RXDFETAP7HOLD_delay; + wire RXDFETAP7OVRDEN_delay; + wire RXDFETAP8HOLD_delay; + wire RXDFETAP8OVRDEN_delay; + wire RXDFETAP9HOLD_delay; + wire RXDFETAP9OVRDEN_delay; + wire RXDFEUTHOLD_delay; + wire RXDFEUTOVRDEN_delay; + wire RXDFEVPHOLD_delay; + wire RXDFEVPOVRDEN_delay; + wire RXDFEVSEN_delay; + wire RXDFEXYDEN_delay; + wire RXDLYBYPASS_delay; + wire RXDLYEN_delay; + wire RXDLYOVRDEN_delay; + wire RXDLYSRESET_delay; + wire RXGEARBOXSLIP_delay; + wire RXLATCLK_delay; + wire RXLPMEN_delay; + wire RXLPMGCHOLD_delay; + wire RXLPMGCOVRDEN_delay; + wire RXLPMHFHOLD_delay; + wire RXLPMHFOVRDEN_delay; + wire RXLPMLFHOLD_delay; + wire RXLPMLFKLOVRDEN_delay; + wire RXLPMOSHOLD_delay; + wire RXLPMOSOVRDEN_delay; + wire RXMCOMMAALIGNEN_delay; + wire RXOOBRESET_delay; + wire RXOSCALRESET_delay; + wire RXOSHOLD_delay; + wire RXOSINTEN_delay; + wire RXOSINTHOLD_delay; + wire RXOSINTOVRDEN_delay; + wire RXOSINTSTROBE_delay; + wire RXOSINTTESTOVRDEN_delay; + wire RXOSOVRDEN_delay; + wire RXPCOMMAALIGNEN_delay; + wire RXPCSRESET_delay; + wire RXPHALIGNEN_delay; + wire RXPHALIGN_delay; + wire RXPHDLYPD_delay; + wire RXPHDLYRESET_delay; + wire RXPHOVRDEN_delay; + wire RXPMARESET_delay; + wire RXPOLARITY_delay; + wire RXPRBSCNTRESET_delay; + wire RXPROGDIVRESET_delay; + wire RXQPIEN_delay; + wire RXRATEMODE_delay; + wire RXSLIDE_delay; + wire RXSLIPOUTCLK_delay; + wire RXSLIPPMA_delay; + wire RXSYNCALLIN_delay; + wire RXSYNCIN_delay; + wire RXSYNCMODE_delay; + wire RXUSERRDY_delay; + wire RXUSRCLK2_delay; + wire RXUSRCLK_delay; + wire SIGVALIDCLK_delay; + wire TX8B10BEN_delay; + wire TXCOMINIT_delay; + wire TXCOMSAS_delay; + wire TXCOMWAKE_delay; + wire TXDEEMPH_delay; + wire TXDETECTRX_delay; + wire TXDIFFPD_delay; + wire TXDLYBYPASS_delay; + wire TXDLYEN_delay; + wire TXDLYHOLD_delay; + wire TXDLYOVRDEN_delay; + wire TXDLYSRESET_delay; + wire TXDLYUPDOWN_delay; + wire TXELECIDLE_delay; + wire TXINHIBIT_delay; + wire TXLATCLK_delay; + wire TXPCSRESET_delay; + wire TXPDELECIDLEMODE_delay; + wire TXPHALIGNEN_delay; + wire TXPHALIGN_delay; + wire TXPHDLYPD_delay; + wire TXPHDLYRESET_delay; + wire TXPHDLYTSTCLK_delay; + wire TXPHINIT_delay; + wire TXPHOVRDEN_delay; + wire TXPIPPMEN_delay; + wire TXPIPPMOVRDEN_delay; + wire TXPIPPMPD_delay; + wire TXPIPPMSEL_delay; + wire TXPISOPD_delay; + wire TXPMARESET_delay; + wire TXPOLARITY_delay; + wire TXPOSTCURSORINV_delay; + wire TXPRBSFORCEERR_delay; + wire TXPRECURSORINV_delay; + wire TXPROGDIVRESET_delay; + wire TXQPIBIASEN_delay; + wire TXQPISTRONGPDOWN_delay; + wire TXQPIWEAKPUP_delay; + wire TXRATEMODE_delay; + wire TXSWING_delay; + wire TXSYNCALLIN_delay; + wire TXSYNCIN_delay; + wire TXSYNCMODE_delay; + wire TXUSERRDY_delay; + wire TXUSRCLK2_delay; + wire TXUSRCLK_delay; + wire [127:0] TXDATA_delay; + wire [15:0] DRPDI_delay; + wire [15:0] GTRSVD_delay; + wire [15:0] PCSRSVDIN_delay; + wire [15:0] TXCTRL0_delay; + wire [15:0] TXCTRL1_delay; + wire [19:0] TSTIN_delay; + wire [1:0] RXDFEAGCCTRL_delay; + wire [1:0] RXELECIDLEMODE_delay; + wire [1:0] RXMONITORSEL_delay; + wire [1:0] RXPD_delay; + wire [1:0] RXPLLCLKSEL_delay; + wire [1:0] RXSYSCLKSEL_delay; + wire [1:0] TXPD_delay; + wire [1:0] TXPLLCLKSEL_delay; + wire [1:0] TXSYSCLKSEL_delay; + wire [2:0] CPLLREFCLKSEL_delay; + wire [2:0] LOOPBACK_delay; + wire [2:0] RXCHBONDLEVEL_delay; + wire [2:0] RXOUTCLKSEL_delay; + wire [2:0] RXRATE_delay; + wire [2:0] TXBUFDIFFCTRL_delay; + wire [2:0] TXMARGIN_delay; + wire [2:0] TXOUTCLKSEL_delay; + wire [2:0] TXRATE_delay; + wire [3:0] RXOSINTCFG_delay; + wire [3:0] RXPRBSSEL_delay; + wire [3:0] TXDIFFCTRL_delay; + wire [3:0] TXPRBSSEL_delay; + wire [4:0] PCSRSVDIN2_delay; + wire [4:0] PMARSVDIN_delay; + wire [4:0] RXCHBONDI_delay; + wire [4:0] TXPIPPMSTEPSIZE_delay; + wire [4:0] TXPOSTCURSOR_delay; + wire [4:0] TXPRECURSOR_delay; + wire [5:0] TXHEADER_delay; + wire [6:0] TXMAINCURSOR_delay; + wire [6:0] TXSEQUENCE_delay; + wire [7:0] TX8B10BBYPASS_delay; + wire [7:0] TXCTRL2_delay; + wire [7:0] TXDATAEXTENDRSVD_delay; + wire [8:0] DRPADDR_delay; + + assign #(out_delay) BUFGTCE = BUFGTCE_delay; + assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay; + assign #(out_delay) BUFGTDIV = BUFGTDIV_delay; + assign #(out_delay) BUFGTRESET = BUFGTRESET_delay; + assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay; + assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay; + assign #(out_delay) CPLLLOCK = CPLLLOCK_delay; + assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay; + assign #(out_delay) DMONITOROUT = DMONITOROUT_delay; + assign #(out_delay) DRPDO = DRPDO_delay; + assign #(out_delay) DRPRDY = DRPRDY_delay; + assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay; + assign #(out_delay) GTHTXN = GTHTXN_delay; + assign #(out_delay) GTHTXP = GTHTXP_delay; + assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay; + assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay; + assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay; + assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay; + assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay; + assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay; + assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay; + assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay; + assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay; + assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay; + assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay; + assign #(out_delay) PHYSTATUS = PHYSTATUS_delay; + assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay; + assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay; + assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay; + assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay; + assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay; + assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay; + assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay; + assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay; + assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay; + assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay; + assign #(out_delay) RXCHBONDO = RXCHBONDO_delay; + assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay; + assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay; + assign #(out_delay) RXCOMMADET = RXCOMMADET_delay; + assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay; + assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay; + assign #(out_delay) RXCTRL0 = RXCTRL0_delay; + assign #(out_delay) RXCTRL1 = RXCTRL1_delay; + assign #(out_delay) RXCTRL2 = RXCTRL2_delay; + assign #(out_delay) RXCTRL3 = RXCTRL3_delay; + assign #(out_delay) RXDATA = RXDATA_delay; + assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay; + assign #(out_delay) RXDATAVALID = RXDATAVALID_delay; + assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay; + assign #(out_delay) RXELECIDLE = RXELECIDLE_delay; + assign #(out_delay) RXHEADER = RXHEADER_delay; + assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay; + assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay; + assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay; + assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay; + assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay; + assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay; + assign #(out_delay) RXOUTCLK = RXOUTCLK_delay; + assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay; + assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay; + assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay; + assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay; + assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay; + assign #(out_delay) RXPRBSERR = RXPRBSERR_delay; + assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay; + assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay; + assign #(out_delay) RXQPISENN = RXQPISENN_delay; + assign #(out_delay) RXQPISENP = RXQPISENP_delay; + assign #(out_delay) RXRATEDONE = RXRATEDONE_delay; + assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay; + assign #(out_delay) RXRESETDONE = RXRESETDONE_delay; + assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay; + assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay; + assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay; + assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay; + assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay; + assign #(out_delay) RXSTATUS = RXSTATUS_delay; + assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay; + assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay; + assign #(out_delay) RXVALID = RXVALID_delay; + assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay; + assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay; + assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay; + assign #(out_delay) TXOUTCLK = TXOUTCLK_delay; + assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay; + assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay; + assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay; + assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay; + assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay; + assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay; + assign #(out_delay) TXQPISENN = TXQPISENN_delay; + assign #(out_delay) TXQPISENP = TXQPISENP_delay; + assign #(out_delay) TXRATEDONE = TXRATEDONE_delay; + assign #(out_delay) TXRESETDONE = TXRESETDONE_delay; + assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay; + assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) DRPCLK_delay = DRPCLK; + assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2; + assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK; + assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2; + + assign #(in_delay) DRPADDR_delay = DRPADDR; + assign #(in_delay) DRPDI_delay = DRPDI; + assign #(in_delay) DRPEN_delay = DRPEN; + assign #(in_delay) DRPWE_delay = DRPWE; + assign #(in_delay) RX8B10BEN_delay = RX8B10BEN; + assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN; + assign #(in_delay) RXCHBONDI_delay = RXCHBONDI; + assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL; + assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER; + assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE; + assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN; + assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP; + assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN; + assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN; + assign #(in_delay) RXPOLARITY_delay = RXPOLARITY; + assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET; + assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL; + assign #(in_delay) RXRATE_delay = RXRATE; + assign #(in_delay) RXSLIDE_delay = RXSLIDE; + assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK; + assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA; + assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS; + assign #(in_delay) TX8B10BEN_delay = TX8B10BEN; + assign #(in_delay) TXCOMINIT_delay = TXCOMINIT; + assign #(in_delay) TXCOMSAS_delay = TXCOMSAS; + assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE; + assign #(in_delay) TXCTRL0_delay = TXCTRL0; + assign #(in_delay) TXCTRL1_delay = TXCTRL1; + assign #(in_delay) TXCTRL2_delay = TXCTRL2; + assign #(in_delay) TXDATA_delay = TXDATA; + assign #(in_delay) TXDETECTRX_delay = TXDETECTRX; + assign #(in_delay) TXELECIDLE_delay = TXELECIDLE; + assign #(in_delay) TXHEADER_delay = TXHEADER; + assign #(in_delay) TXINHIBIT_delay = TXINHIBIT; + assign #(in_delay) TXPD_delay = TXPD; + assign #(in_delay) TXPOLARITY_delay = TXPOLARITY; + assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR; + assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL; + assign #(in_delay) TXRATE_delay = TXRATE; + assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE; +`endif + +// inputs with no timing checks + assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0; + assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1; + assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK; + assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK; + assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK; + assign #(inclk_delay) RXLATCLK_delay = RXLATCLK; + assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK; + assign #(inclk_delay) TXLATCLK_delay = TXLATCLK; + assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK; + assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK; + + assign #(in_delay) CFGRESET_delay = CFGRESET; + assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN; + assign #(in_delay) CPLLPD_delay = CPLLPD; + assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL; + assign #(in_delay) CPLLRESET_delay = CPLLRESET; + assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET; + assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE; + assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART; + assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN; + assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN; + assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN; + assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN; + assign #(in_delay) EYESCANMODE_delay = EYESCANMODE; + assign #(in_delay) EYESCANRESET_delay = EYESCANRESET; + assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER; + assign #(in_delay) GTHRXN_delay = GTHRXN; + assign #(in_delay) GTHRXP_delay = GTHRXP; + assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0; + assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1; + assign #(in_delay) GTREFCLK0_delay = GTREFCLK0; + assign #(in_delay) GTREFCLK1_delay = GTREFCLK1; + assign #(in_delay) GTRESETSEL_delay = GTRESETSEL; + assign #(in_delay) GTRSVD_delay = GTRSVD; + assign #(in_delay) GTRXRESET_delay = GTRXRESET; + assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0; + assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1; + assign #(in_delay) GTTXRESET_delay = GTTXRESET; + assign #(in_delay) LOOPBACK_delay = LOOPBACK; + assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN; + assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN; + assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE; + assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE; + assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART; + assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE; + assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2; + assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN; + assign #(in_delay) PMARSVDIN_delay = PMARSVDIN; + assign #(in_delay) QPLL0CLK_delay = QPLL0CLK; + assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK; + assign #(in_delay) QPLL1CLK_delay = QPLL1CLK; + assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK; + assign #(in_delay) RESETOVRD_delay = RESETOVRD; + assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX; + assign #(in_delay) RXBUFRESET_delay = RXBUFRESET; + assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET; + assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD; + assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN; + assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV; + assign #(in_delay) RXCDRRESET_delay = RXCDRRESET; + assign #(in_delay) RXDFEAGCCTRL_delay = RXDFEAGCCTRL; + assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD; + assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN; + assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD; + assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN; + assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET; + assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD; + assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN; + assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD; + assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN; + assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD; + assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN; + assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD; + assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN; + assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD; + assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN; + assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD; + assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN; + assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD; + assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN; + assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD; + assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN; + assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD; + assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN; + assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD; + assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN; + assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD; + assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN; + assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD; + assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN; + assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD; + assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN; + assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD; + assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN; + assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD; + assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN; + assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD; + assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN; + assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN; + assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN; + assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS; + assign #(in_delay) RXDLYEN_delay = RXDLYEN; + assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN; + assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET; + assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE; + assign #(in_delay) RXLPMEN_delay = RXLPMEN; + assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD; + assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN; + assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD; + assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN; + assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD; + assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN; + assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD; + assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN; + assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL; + assign #(in_delay) RXOOBRESET_delay = RXOOBRESET; + assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET; + assign #(in_delay) RXOSHOLD_delay = RXOSHOLD; + assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG; + assign #(in_delay) RXOSINTEN_delay = RXOSINTEN; + assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD; + assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN; + assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE; + assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN; + assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN; + assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL; + assign #(in_delay) RXPCSRESET_delay = RXPCSRESET; + assign #(in_delay) RXPD_delay = RXPD; + assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN; + assign #(in_delay) RXPHALIGN_delay = RXPHALIGN; + assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD; + assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET; + assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN; + assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL; + assign #(in_delay) RXPMARESET_delay = RXPMARESET; + assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET; + assign #(in_delay) RXQPIEN_delay = RXQPIEN; + assign #(in_delay) RXRATEMODE_delay = RXRATEMODE; + assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN; + assign #(in_delay) RXSYNCIN_delay = RXSYNCIN; + assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE; + assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL; + assign #(in_delay) RXUSERRDY_delay = RXUSERRDY; + assign #(in_delay) TSTIN_delay = TSTIN; + assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL; + assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD; + assign #(in_delay) TXDEEMPH_delay = TXDEEMPH; + assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL; + assign #(in_delay) TXDIFFPD_delay = TXDIFFPD; + assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS; + assign #(in_delay) TXDLYEN_delay = TXDLYEN; + assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD; + assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN; + assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET; + assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN; + assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR; + assign #(in_delay) TXMARGIN_delay = TXMARGIN; + assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL; + assign #(in_delay) TXPCSRESET_delay = TXPCSRESET; + assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE; + assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN; + assign #(in_delay) TXPHALIGN_delay = TXPHALIGN; + assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD; + assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET; + assign #(in_delay) TXPHINIT_delay = TXPHINIT; + assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN; + assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN; + assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN; + assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD; + assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL; + assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE; + assign #(in_delay) TXPISOPD_delay = TXPISOPD; + assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL; + assign #(in_delay) TXPMARESET_delay = TXPMARESET; + assign #(in_delay) TXPOSTCURSORINV_delay = TXPOSTCURSORINV; + assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR; + assign #(in_delay) TXPRECURSORINV_delay = TXPRECURSORINV; + assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR; + assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET; + assign #(in_delay) TXQPIBIASEN_delay = TXQPIBIASEN; + assign #(in_delay) TXQPISTRONGPDOWN_delay = TXQPISTRONGPDOWN; + assign #(in_delay) TXQPIWEAKPUP_delay = TXQPIWEAKPUP; + assign #(in_delay) TXRATEMODE_delay = TXRATEMODE; + assign #(in_delay) TXSWING_delay = TXSWING; + assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN; + assign #(in_delay) TXSYNCIN_delay = TXSYNCIN; + assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE; + assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL; + assign #(in_delay) TXUSERRDY_delay = TXUSERRDY; + + assign BUFGTCEMASK_delay = BUFGTCEMASK_out; + assign BUFGTCE_delay = BUFGTCE_out; + assign BUFGTDIV_delay = BUFGTDIV_out; + assign BUFGTRESET_delay = BUFGTRESET_out; + assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out; + assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out; + assign CPLLLOCK_delay = CPLLLOCK_out; + assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out; + assign DMONITOROUT_delay = DMONITOROUT_out; + assign DRPDO_delay = DRPDO_out; + assign DRPRDY_delay = DRPRDY_out; + assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out; + assign GTHTXN_delay = GTHTXN_out; + assign GTHTXP_delay = GTHTXP_out; + assign GTPOWERGOOD_delay = GTPOWERGOOD_out; + assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out; + assign PCIERATEGEN3_delay = PCIERATEGEN3_out; + assign PCIERATEIDLE_delay = PCIERATEIDLE_out; + assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out; + assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out; + assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out; + assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out; + assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out; + assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out; + assign PCSRSVDOUT_delay = PCSRSVDOUT_out; + assign PHYSTATUS_delay = PHYSTATUS_out; + assign PINRSRVDAS_delay = PINRSRVDAS_out; + assign RESETEXCEPTION_delay = RESETEXCEPTION_out; + assign RXBUFSTATUS_delay = RXBUFSTATUS_out; + assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out; + assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out; + assign RXCDRLOCK_delay = RXCDRLOCK_out; + assign RXCDRPHDONE_delay = RXCDRPHDONE_out; + assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out; + assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out; + assign RXCHANREALIGN_delay = RXCHANREALIGN_out; + assign RXCHBONDO_delay = RXCHBONDO_out; + assign RXCLKCORCNT_delay = RXCLKCORCNT_out; + assign RXCOMINITDET_delay = RXCOMINITDET_out; + assign RXCOMMADET_delay = RXCOMMADET_out; + assign RXCOMSASDET_delay = RXCOMSASDET_out; + assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out; + assign RXCTRL0_delay = RXCTRL0_out; + assign RXCTRL1_delay = RXCTRL1_out; + assign RXCTRL2_delay = RXCTRL2_out; + assign RXCTRL3_delay = RXCTRL3_out; + assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out; + assign RXDATAVALID_delay = RXDATAVALID_out; + assign RXDATA_delay = RXDATA_out; + assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out; + assign RXELECIDLE_delay = RXELECIDLE_out; + assign RXHEADERVALID_delay = RXHEADERVALID_out; + assign RXHEADER_delay = RXHEADER_out; + assign RXMONITOROUT_delay = RXMONITOROUT_out; + assign RXOSINTDONE_delay = RXOSINTDONE_out; + assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out; + assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out; + assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out; + assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out; + assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out; + assign RXOUTCLK_delay = RXOUTCLK_out; + assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out; + assign RXPHALIGNERR_delay = RXPHALIGNERR_out; + assign RXPMARESETDONE_delay = RXPMARESETDONE_out; + assign RXPRBSERR_delay = RXPRBSERR_out; + assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out; + assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out; + assign RXQPISENN_delay = RXQPISENN_out; + assign RXQPISENP_delay = RXQPISENP_out; + assign RXRATEDONE_delay = RXRATEDONE_out; + assign RXRECCLKOUT_delay = RXRECCLKOUT_out; + assign RXRESETDONE_delay = RXRESETDONE_out; + assign RXSLIDERDY_delay = RXSLIDERDY_out; + assign RXSLIPDONE_delay = RXSLIPDONE_out; + assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out; + assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out; + assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out; + assign RXSTATUS_delay = RXSTATUS_out; + assign RXSYNCDONE_delay = RXSYNCDONE_out; + assign RXSYNCOUT_delay = RXSYNCOUT_out; + assign RXVALID_delay = RXVALID_out; + assign TXBUFSTATUS_delay = TXBUFSTATUS_out; + assign TXCOMFINISH_delay = TXCOMFINISH_out; + assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out; + assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out; + assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out; + assign TXOUTCLK_delay = TXOUTCLK_out; + assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out; + assign TXPHINITDONE_delay = TXPHINITDONE_out; + assign TXPMARESETDONE_delay = TXPMARESETDONE_out; + assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out; + assign TXQPISENN_delay = TXQPISENN_out; + assign TXQPISENP_delay = TXQPISENP_out; + assign TXRATEDONE_delay = TXRATEDONE_out; + assign TXRESETDONE_delay = TXRESETDONE_out; + assign TXSYNCDONE_delay = TXSYNCDONE_out; + assign TXSYNCOUT_delay = TXSYNCOUT_out; + + assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET_delay; // rv 0 + assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0_delay; // rv 0 + assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1_delay; // rv 0 + assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK_delay; // rv 0 + assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN_delay; // rv 0 + assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD_delay; // rv 0 + assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL_delay[0]; // rv 1 + assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL_delay[1]; // rv 0 + assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL_delay[2]; // rv 0 + assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET_delay; // rv 0 + assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET_delay; // rv 0 + assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK_delay; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign EVODDPHICALDONE_in = (EVODDPHICALDONE !== 1'bz) && EVODDPHICALDONE_delay; // rv 0 + assign EVODDPHICALSTART_in = (EVODDPHICALSTART !== 1'bz) && EVODDPHICALSTART_delay; // rv 0 + assign EVODDPHIDRDEN_in = (EVODDPHIDRDEN !== 1'bz) && EVODDPHIDRDEN_delay; // rv 0 + assign EVODDPHIDWREN_in = (EVODDPHIDWREN !== 1'bz) && EVODDPHIDWREN_delay; // rv 0 + assign EVODDPHIXRDEN_in = (EVODDPHIXRDEN !== 1'bz) && EVODDPHIXRDEN_delay; // rv 0 + assign EVODDPHIXWREN_in = (EVODDPHIXWREN !== 1'bz) && EVODDPHIXWREN_delay; // rv 0 + assign EYESCANMODE_in = (EYESCANMODE !== 1'bz) && EYESCANMODE_delay; // rv 0 + assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET_delay; // rv 0 + assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER_delay; // rv 0 + assign GTGREFCLK_in = GTGREFCLK_delay; + assign GTHRXN_in = GTHRXN_delay; + assign GTHRXP_in = GTHRXP_delay; + assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay; + assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay; + assign GTREFCLK0_in = GTREFCLK0_delay; + assign GTREFCLK1_in = GTREFCLK1_delay; + assign GTRESETSEL_in = (GTRESETSEL !== 1'bz) && GTRESETSEL_delay; // rv 0 + assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD_delay[0]; // rv 0 + assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD_delay[10]; // rv 0 + assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD_delay[11]; // rv 0 + assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD_delay[12]; // rv 0 + assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD_delay[13]; // rv 0 + assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD_delay[14]; // rv 0 + assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD_delay[15]; // rv 0 + assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD_delay[1]; // rv 0 + assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD_delay[2]; // rv 0 + assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD_delay[3]; // rv 0 + assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD_delay[4]; // rv 0 + assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD_delay[5]; // rv 0 + assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD_delay[6]; // rv 0 + assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD_delay[7]; // rv 0 + assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD_delay[8]; // rv 0 + assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD_delay[9]; // rv 0 + assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET_delay; // rv 0 + assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay; + assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay; + assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET_delay; // rv 0 + assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK_delay[0]; // rv 0 + assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK_delay[1]; // rv 0 + assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK_delay[2]; // rv 0 + assign LPBKRXTXSEREN_in = (LPBKRXTXSEREN !== 1'bz) && LPBKRXTXSEREN_delay; // rv 0 + assign LPBKTXRXSEREN_in = (LPBKTXRXSEREN !== 1'bz) && LPBKTXRXSEREN_delay; // rv 0 + assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE_delay; // rv 0 + assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE_delay; // rv 0 + assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART_delay; // rv 0 + assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE_delay; // rv 0 + assign PCSRSVDIN2_in[0] = (PCSRSVDIN2[0] !== 1'bz) && PCSRSVDIN2_delay[0]; // rv 0 + assign PCSRSVDIN2_in[1] = (PCSRSVDIN2[1] !== 1'bz) && PCSRSVDIN2_delay[1]; // rv 0 + assign PCSRSVDIN2_in[2] = (PCSRSVDIN2[2] !== 1'bz) && PCSRSVDIN2_delay[2]; // rv 0 + assign PCSRSVDIN2_in[3] = (PCSRSVDIN2[3] !== 1'bz) && PCSRSVDIN2_delay[3]; // rv 0 + assign PCSRSVDIN2_in[4] = (PCSRSVDIN2[4] !== 1'bz) && PCSRSVDIN2_delay[4]; // rv 0 + assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] !== 1'bz) && PCSRSVDIN_delay[0]; // rv 0 + assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN_delay[10]; // rv 0 + assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN_delay[11]; // rv 0 + assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN_delay[12]; // rv 0 + assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN_delay[13]; // rv 0 + assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN_delay[14]; // rv 0 + assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN_delay[15]; // rv 0 + assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN_delay[1]; // rv 0 + assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN_delay[2]; // rv 0 + assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN_delay[3]; // rv 0 + assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN_delay[4]; // rv 0 + assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN_delay[5]; // rv 0 + assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN_delay[6]; // rv 0 + assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN_delay[7]; // rv 0 + assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN_delay[8]; // rv 0 + assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN_delay[9]; // rv 0 + assign PMARSVDIN_in[0] = (PMARSVDIN[0] !== 1'bz) && PMARSVDIN_delay[0]; // rv 0 + assign PMARSVDIN_in[1] = (PMARSVDIN[1] !== 1'bz) && PMARSVDIN_delay[1]; // rv 0 + assign PMARSVDIN_in[2] = (PMARSVDIN[2] !== 1'bz) && PMARSVDIN_delay[2]; // rv 0 + assign PMARSVDIN_in[3] = (PMARSVDIN[3] !== 1'bz) && PMARSVDIN_delay[3]; // rv 0 + assign PMARSVDIN_in[4] = (PMARSVDIN[4] !== 1'bz) && PMARSVDIN_delay[4]; // rv 0 + assign QPLL0CLK_in = QPLL0CLK_delay; + assign QPLL0REFCLK_in = QPLL0REFCLK_delay; + assign QPLL1CLK_in = QPLL1CLK_delay; + assign QPLL1REFCLK_in = QPLL1REFCLK_delay; + assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD_delay; // rv 0 + assign RSTCLKENTX_in = (RSTCLKENTX !== 1'bz) && RSTCLKENTX_delay; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0 + assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET_delay; // rv 0 + assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET_delay; // rv 0 + assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD_delay; // rv 0 + assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN_delay; // rv 0 + assign RXCDRRESETRSV_in = (RXCDRRESETRSV !== 1'bz) && RXCDRRESETRSV_delay; // rv 0 + assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET_delay; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0 + assign RXDFEAGCCTRL_in[0] = (RXDFEAGCCTRL[0] !== 1'bz) && RXDFEAGCCTRL_delay[0]; // rv 0 + assign RXDFEAGCCTRL_in[1] = (RXDFEAGCCTRL[1] !== 1'bz) && RXDFEAGCCTRL_delay[1]; // rv 0 + assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD_delay; // rv 0 + assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN_delay; // rv 0 + assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD_delay; // rv 0 + assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN_delay; // rv 0 + assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET_delay; // rv 0 + assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD_delay; // rv 0 + assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN_delay; // rv 0 + assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD_delay; // rv 0 + assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN_delay; // rv 0 + assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD_delay; // rv 0 + assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN_delay; // rv 0 + assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD_delay; // rv 0 + assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN_delay; // rv 0 + assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD_delay; // rv 0 + assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN_delay; // rv 0 + assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD_delay; // rv 0 + assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN_delay; // rv 0 + assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD_delay; // rv 0 + assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN_delay; // rv 0 + assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD_delay; // rv 0 + assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN_delay; // rv 0 + assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD_delay; // rv 0 + assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN_delay; // rv 0 + assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD_delay; // rv 0 + assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN_delay; // rv 0 + assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD_delay; // rv 0 + assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN_delay; // rv 0 + assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD_delay; // rv 0 + assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN_delay; // rv 0 + assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD_delay; // rv 0 + assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN_delay; // rv 0 + assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD_delay; // rv 0 + assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN_delay; // rv 0 + assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD_delay; // rv 0 + assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN_delay; // rv 0 + assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD_delay; // rv 0 + assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN_delay; // rv 0 + assign RXDFEVSEN_in = (RXDFEVSEN !== 1'bz) && RXDFEVSEN_delay; // rv 0 + assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN_delay; // rv 0 + assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS_delay; // rv 0 + assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN_delay; // rv 0 + assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN_delay; // rv 0 + assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET_delay; // rv 0 + assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE_delay[0]; // rv 0 + assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE_delay[1]; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0 + assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK_delay; // rv 0 + assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN_delay; // rv 0 + assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD_delay; // rv 0 + assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN_delay; // rv 0 + assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD_delay; // rv 0 + assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN_delay; // rv 0 + assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD_delay; // rv 0 + assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN_delay; // rv 0 + assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD_delay; // rv 0 + assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN_delay; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0 + assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL_delay[0]; // rv 0 + assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL_delay[1]; // rv 0 + assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET_delay; // rv 0 + assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET_delay; // rv 0 + assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD_delay; // rv 0 + assign RXOSINTCFG_in[0] = (RXOSINTCFG[0] !== 1'bz) && RXOSINTCFG_delay[0]; // rv 0 + assign RXOSINTCFG_in[1] = (RXOSINTCFG[1] === 1'bz) || RXOSINTCFG_delay[1]; // rv 1 + assign RXOSINTCFG_in[2] = (RXOSINTCFG[2] === 1'bz) || RXOSINTCFG_delay[2]; // rv 1 + assign RXOSINTCFG_in[3] = (RXOSINTCFG[3] !== 1'bz) && RXOSINTCFG_delay[3]; // rv 0 + assign RXOSINTEN_in = (RXOSINTEN === 1'bz) || RXOSINTEN_delay; // rv 1 + assign RXOSINTHOLD_in = (RXOSINTHOLD !== 1'bz) && RXOSINTHOLD_delay; // rv 0 + assign RXOSINTOVRDEN_in = (RXOSINTOVRDEN !== 1'bz) && RXOSINTOVRDEN_delay; // rv 0 + assign RXOSINTSTROBE_in = (RXOSINTSTROBE !== 1'bz) && RXOSINTSTROBE_delay; // rv 0 + assign RXOSINTTESTOVRDEN_in = (RXOSINTTESTOVRDEN !== 1'bz) && RXOSINTTESTOVRDEN_delay; // rv 0 + assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN_delay; // rv 0 + assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL_delay[0]; // rv 0 + assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL_delay[1]; // rv 0 + assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL_delay[2]; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0 + assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET_delay; // rv 0 + assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD_delay[0]; // rv 0 + assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD_delay[1]; // rv 0 + assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN_delay; // rv 0 + assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN_delay; // rv 0 + assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD_delay; // rv 0 + assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET_delay; // rv 0 + assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN_delay; // rv 0 + assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL_delay[0]; // rv 0 + assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL_delay[1]; // rv 0 + assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET_delay; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0 + assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET_delay; // rv 0 + assign RXQPIEN_in = (RXQPIEN !== 1'bz) && RXQPIEN_delay; // rv 0 + assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE_delay; // rv 0 + assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0 + assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0 + assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0 + assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0 + assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN_delay; // rv 0 + assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN_delay; // rv 0 + assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE_delay; // rv 1 + assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL_delay[0]; // rv 0 + assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL_delay[1]; // rv 0 + assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY_delay; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0 + assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK_delay; // rv 0 + assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN_delay[0]; // rv 0 + assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN_delay[10]; // rv 0 + assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN_delay[11]; // rv 0 + assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN_delay[12]; // rv 0 + assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN_delay[13]; // rv 0 + assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN_delay[14]; // rv 0 + assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN_delay[15]; // rv 0 + assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN_delay[16]; // rv 0 + assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN_delay[17]; // rv 0 + assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN_delay[18]; // rv 0 + assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN_delay[19]; // rv 0 + assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN_delay[1]; // rv 0 + assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN_delay[2]; // rv 0 + assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN_delay[3]; // rv 0 + assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN_delay[4]; // rv 0 + assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN_delay[5]; // rv 0 + assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN_delay[6]; // rv 0 + assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN_delay[7]; // rv 0 + assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN_delay[8]; // rv 0 + assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN_delay[9]; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0 + assign TXBUFDIFFCTRL_in[0] = (TXBUFDIFFCTRL[0] !== 1'bz) && TXBUFDIFFCTRL_delay[0]; // rv 0 + assign TXBUFDIFFCTRL_in[1] = (TXBUFDIFFCTRL[1] !== 1'bz) && TXBUFDIFFCTRL_delay[1]; // rv 0 + assign TXBUFDIFFCTRL_in[2] = (TXBUFDIFFCTRL[2] !== 1'bz) && TXBUFDIFFCTRL_delay[2]; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0 + assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD_delay[0]; // rv 0 + assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD_delay[1]; // rv 0 + assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD_delay[2]; // rv 0 + assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD_delay[3]; // rv 0 + assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD_delay[4]; // rv 0 + assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD_delay[5]; // rv 0 + assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD_delay[6]; // rv 0 + assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD_delay[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0 + assign TXDEEMPH_in = (TXDEEMPH !== 1'bz) && TXDEEMPH_delay; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0 + assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL_delay[0]; // rv 0 + assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL_delay[1]; // rv 0 + assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL_delay[2]; // rv 0 + assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL_delay[3]; // rv 0 + assign TXDIFFPD_in = (TXDIFFPD !== 1'bz) && TXDIFFPD_delay; // rv 0 + assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS_delay; // rv 0 + assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN_delay; // rv 0 + assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD_delay; // rv 0 + assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN_delay; // rv 0 + assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET_delay; // rv 0 + assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN_delay; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0 + assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK_delay; // rv 0 + assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR_delay[0]; // rv 0 + assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR_delay[1]; // rv 0 + assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR_delay[2]; // rv 0 + assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR_delay[3]; // rv 0 + assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR_delay[4]; // rv 0 + assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR_delay[5]; // rv 0 + assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR_delay[6]; // rv 0 + assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN_delay[0]; // rv 0 + assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN_delay[1]; // rv 0 + assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN_delay[2]; // rv 0 + assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL_delay[0]; // rv 0 + assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL_delay[1]; // rv 0 + assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL_delay[2]; // rv 0 + assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET_delay; // rv 0 + assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE_delay; // rv 0 + assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0 + assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0 + assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN_delay; // rv 0 + assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN_delay; // rv 0 + assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD_delay; // rv 0 + assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET_delay; // rv 0 + assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK_delay; // rv 0 + assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT_delay; // rv 0 + assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN_delay; // rv 0 + assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN_delay; // rv 0 + assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN_delay; // rv 0 + assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD_delay; // rv 0 + assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL_delay; // rv 0 + assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE_delay[0]; // rv 0 + assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE_delay[1]; // rv 0 + assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE_delay[2]; // rv 0 + assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE_delay[3]; // rv 0 + assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE_delay[4]; // rv 0 + assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD_delay; // rv 0 + assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL_delay[0]; // rv 0 + assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL_delay[1]; // rv 0 + assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET_delay; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0 + assign TXPOSTCURSORINV_in = (TXPOSTCURSORINV !== 1'bz) && TXPOSTCURSORINV_delay; // rv 0 + assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR_delay[0]; // rv 0 + assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR_delay[1]; // rv 0 + assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR_delay[2]; // rv 0 + assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR_delay[3]; // rv 0 + assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR_delay[4]; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0 + assign TXPRECURSORINV_in = (TXPRECURSORINV !== 1'bz) && TXPRECURSORINV_delay; // rv 0 + assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR_delay[0]; // rv 0 + assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR_delay[1]; // rv 0 + assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR_delay[2]; // rv 0 + assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR_delay[3]; // rv 0 + assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR_delay[4]; // rv 0 + assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET_delay; // rv 0 + assign TXQPIBIASEN_in = (TXQPIBIASEN !== 1'bz) && TXQPIBIASEN_delay; // rv 0 + assign TXQPISTRONGPDOWN_in = (TXQPISTRONGPDOWN !== 1'bz) && TXQPISTRONGPDOWN_delay; // rv 0 + assign TXQPIWEAKPUP_in = (TXQPIWEAKPUP !== 1'bz) && TXQPIWEAKPUP_delay; // rv 0 + assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE_delay; // rv 0 + assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0 + assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0 + assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0 + assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING_delay; // rv 0 + assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN_delay; // rv 0 + assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN_delay; // rv 0 + assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE_delay; // rv 1 + assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL_delay[0]; // rv 0 + assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL_delay[1]; // rv 0 + assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY_delay; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0 + assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK_delay; // rv 0 + + assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_DOUBLE_REG != "FALSE") && + (ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-128] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_WORD_REG != 1) && + (ALIGN_COMMA_WORD_REG != 2) && + (ALIGN_COMMA_WORD_REG != 4))) begin + $display("Error: [Unisim %s-130] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_MCOMMA_DET_REG != "TRUE") && + (ALIGN_MCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-131] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_PCOMMA_DET_REG != "TRUE") && + (ALIGN_PCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-133] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") && + (CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin + $display("Error: [Unisim %s-258] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") && + (CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-260] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_MAX_SKEW_REG != 7) && + (CHAN_BOND_MAX_SKEW_REG != 1) && + (CHAN_BOND_MAX_SKEW_REG != 2) && + (CHAN_BOND_MAX_SKEW_REG != 3) && + (CHAN_BOND_MAX_SKEW_REG != 4) && + (CHAN_BOND_MAX_SKEW_REG != 5) && + (CHAN_BOND_MAX_SKEW_REG != 6) && + (CHAN_BOND_MAX_SKEW_REG != 8) && + (CHAN_BOND_MAX_SKEW_REG != 9) && + (CHAN_BOND_MAX_SKEW_REG != 10) && + (CHAN_BOND_MAX_SKEW_REG != 11) && + (CHAN_BOND_MAX_SKEW_REG != 12) && + (CHAN_BOND_MAX_SKEW_REG != 13) && + (CHAN_BOND_MAX_SKEW_REG != 14))) begin + $display("Error: [Unisim %s-261] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") && + (CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-272] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_LEN_REG != 2) && + (CHAN_BOND_SEQ_LEN_REG != 1) && + (CHAN_BOND_SEQ_LEN_REG != 3) && + (CHAN_BOND_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-273] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_CORRECT_USE_REG != "TRUE") && + (CLK_CORRECT_USE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-274] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_KEEP_IDLE_REG != "FALSE") && + (CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-275] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin + $display("Error: [Unisim %s-276] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin + $display("Error: [Unisim %s-277] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_PRECEDENCE_REG != "TRUE") && + (CLK_COR_PRECEDENCE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-278] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-279] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_2_USE_REG != "FALSE") && + (CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-290] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_LEN_REG != 2) && + (CLK_COR_SEQ_LEN_REG != 1) && + (CLK_COR_SEQ_LEN_REG != 3) && + (CLK_COR_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-291] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_REG != 4) && + (CPLL_FBDIV_REG != 1) && + (CPLL_FBDIV_REG != 2) && + (CPLL_FBDIV_REG != 3) && + (CPLL_FBDIV_REG != 5) && + (CPLL_FBDIV_REG != 6) && + (CPLL_FBDIV_REG != 8) && + (CPLL_FBDIV_REG != 10) && + (CPLL_FBDIV_REG != 12) && + (CPLL_FBDIV_REG != 16) && + (CPLL_FBDIV_REG != 20))) begin + $display("Error: [Unisim %s-296] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_45_REG != 4) && + (CPLL_FBDIV_45_REG != 5))) begin + $display("Error: [Unisim %s-297] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_REFCLK_DIV_REG != 1) && + (CPLL_REFCLK_DIV_REG != 2) && + (CPLL_REFCLK_DIV_REG != 3) && + (CPLL_REFCLK_DIV_REG != 4) && + (CPLL_REFCLK_DIV_REG != 5) && + (CPLL_REFCLK_DIV_REG != 6) && + (CPLL_REFCLK_DIV_REG != 8) && + (CPLL_REFCLK_DIV_REG != 10) && + (CPLL_REFCLK_DIV_REG != 12) && + (CPLL_REFCLK_DIV_REG != 16) && + (CPLL_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-301] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-303] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_MCOMMA_DETECT_REG != "TRUE") && + (DEC_MCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-304] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_PCOMMA_DETECT_REG != "TRUE") && + (DEC_PCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-305] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_VALID_COMMA_ONLY_REG != "TRUE") && + (DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-306] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_ERRDET_EN_REG != "FALSE") && + (ES_ERRDET_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-313] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_EYE_SCAN_EN_REG != "FALSE") && + (ES_EYE_SCAN_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-314] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FTS_LANE_DESKEW_EN_REG != "FALSE") && + (FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-337] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") && + (PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin + $display("Error: [Unisim %s-346] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCS_PCIE_EN_REG != "FALSE") && + (PCS_PCIE_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-360] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_ADDR_MODE_REG != "FULL") && + (RXBUF_ADDR_MODE_REG != "FAST"))) begin + $display("Error: [Unisim %s-373] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_EN_REG != "TRUE") && + (RXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-376] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-377] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") && + (RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-378] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") && + (RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-379] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-380] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin + $display("Error: [Unisim %s-381] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVRD_REG != "FALSE") && + (RXBUF_THRESH_OVRD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-382] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin + $display("Error: [Unisim %s-383] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXELECIDLE_CFG_REG != "Sigcfg_4") && + (RXELECIDLE_CFG_REG != "Sigcfg_1") && + (RXELECIDLE_CFG_REG != "Sigcfg_2") && + (RXELECIDLE_CFG_REG != "Sigcfg_3") && + (RXELECIDLE_CFG_REG != "Sigcfg_6") && + (RXELECIDLE_CFG_REG != "Sigcfg_8") && + (RXELECIDLE_CFG_REG != "Sigcfg_12") && + (RXELECIDLE_CFG_REG != "Sigcfg_16"))) begin + $display("Error: [Unisim %s-452] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are Sigcfg_4, Sigcfg_1, Sigcfg_2, Sigcfg_3, Sigcfg_6, Sigcfg_8, Sigcfg_12 or Sigcfg_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin + $display("Error: [Unisim %s-453] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGEARBOX_EN_REG != "FALSE") && + (RXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-454] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOOB_CLK_CFG_REG != "PMA") && + (RXOOB_CLK_CFG_REG != "FABRIC"))) begin + $display("Error: [Unisim %s-463] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOUT_DIV_REG != 4) && + (RXOUT_DIV_REG != 1) && + (RXOUT_DIV_REG != 2) && + (RXOUT_DIV_REG != 8) && + (RXOUT_DIV_REG != 16))) begin + $display("Error: [Unisim %s-465] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, RXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPMACLK_SEL_REG != "DATA") && + (RXPMACLK_SEL_REG != "CROSSING") && + (RXPMACLK_SEL_REG != "EYESCAN"))) begin + $display("Error: [Unisim %s-482] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin + $display("Error: [Unisim %s-485] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_AUTO_WAIT_REG != 7) && + (RXSLIDE_AUTO_WAIT_REG != 1) && + (RXSLIDE_AUTO_WAIT_REG != 2) && + (RXSLIDE_AUTO_WAIT_REG != 3) && + (RXSLIDE_AUTO_WAIT_REG != 4) && + (RXSLIDE_AUTO_WAIT_REG != 5) && + (RXSLIDE_AUTO_WAIT_REG != 6) && + (RXSLIDE_AUTO_WAIT_REG != 8) && + (RXSLIDE_AUTO_WAIT_REG != 9) && + (RXSLIDE_AUTO_WAIT_REG != 10) && + (RXSLIDE_AUTO_WAIT_REG != 11) && + (RXSLIDE_AUTO_WAIT_REG != 12) && + (RXSLIDE_AUTO_WAIT_REG != 13) && + (RXSLIDE_AUTO_WAIT_REG != 14) && + (RXSLIDE_AUTO_WAIT_REG != 15))) begin + $display("Error: [Unisim %s-486] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_MODE_REG != "OFF") && + (RXSLIDE_MODE_REG != "AUTO") && + (RXSLIDE_MODE_REG != "PCS") && + (RXSLIDE_MODE_REG != "PMA"))) begin + $display("Error: [Unisim %s-487] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-495] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_WIDTH_REG != 20) && + (RX_DATA_WIDTH_REG != 16) && + (RX_DATA_WIDTH_REG != 32) && + (RX_DATA_WIDTH_REG != 40) && + (RX_DATA_WIDTH_REG != 64) && + (RX_DATA_WIDTH_REG != 80) && + (RX_DATA_WIDTH_REG != 128) && + (RX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-503] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") && + (RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-505] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") && + (RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin + $display("Error: [Unisim %s-516] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_INT_DATAWIDTH_REG != 1) && + (RX_INT_DATAWIDTH_REG != 0) && + (RX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-524] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_PROGDIV_CFG_REG != 0.0) && + (RX_PROGDIV_CFG_REG != 4.0) && + (RX_PROGDIV_CFG_REG != 5.0) && + (RX_PROGDIV_CFG_REG != 8.0) && + (RX_PROGDIV_CFG_REG != 10.0) && + (RX_PROGDIV_CFG_REG != 16.0) && + (RX_PROGDIV_CFG_REG != 16.5) && + (RX_PROGDIV_CFG_REG != 20.0) && + (RX_PROGDIV_CFG_REG != 32.0) && + (RX_PROGDIV_CFG_REG != 33.0) && + (RX_PROGDIV_CFG_REG != 40.0) && + (RX_PROGDIV_CFG_REG != 64.0) && + (RX_PROGDIV_CFG_REG != 66.0) && + (RX_PROGDIV_CFG_REG != 80.0) && + (RX_PROGDIV_CFG_REG != 100.0))) begin + $display("Error: [Unisim %s-526] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin + $display("Error: [Unisim %s-528] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_XCLK_SEL_REG != "RXDES") && + (RX_XCLK_SEL_REG != "RXPMA") && + (RX_XCLK_SEL_REG != "RXUSR"))) begin + $display("Error: [Unisim %s-537] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127))) begin + $display("Error: [Unisim %s-538] SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, SAS_MAX_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63))) begin + $display("Error: [Unisim %s-539] SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SAS_MIN_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") && + (SATA_CPLL_CFG_REG != "VCO_750MHZ") && + (SATA_CPLL_CFG_REG != "VCO_1500MHZ"))) begin + $display("Error: [Unisim %s-542] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63))) begin + $display("Error: [Unisim %s-544] SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63))) begin + $display("Error: [Unisim %s-545] SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-546] SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61))) begin + $display("Error: [Unisim %s-547] SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, SATA_MIN_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63))) begin + $display("Error: [Unisim %s-548] SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-549] SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SHOW_REALIGN_COMMA_REG != "TRUE") && + (SHOW_REALIGN_COMMA_REG != "FALSE"))) begin + $display("Error: [Unisim %s-550] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_MODE_REG != "FAST")) begin + $display("Error: [Unisim %s-551] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") && + (SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-552] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-553] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE, or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2) && + (SIM_VERSION_REG != 1) && + (SIM_VERSION_REG != 3))) begin + $display("Error: [Unisim %s-555] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_EN_REG != "TRUE") && + (TXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-563] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") && + (TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-564] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXFIFO_ADDR_CFG_REG != "LOW") && + (TXFIFO_ADDR_CFG_REG != "HIGH"))) begin + $display("Error: [Unisim %s-569] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin + $display("Error: [Unisim %s-570] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGEARBOX_EN_REG != "FALSE") && + (TXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-571] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXOUT_DIV_REG != 4) && + (TXOUT_DIV_REG != 1) && + (TXOUT_DIV_REG != 2) && + (TXOUT_DIV_REG != 8) && + (TXOUT_DIV_REG != 16))) begin + $display("Error: [Unisim %s-573] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, TXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") && + (TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin + $display("Error: [Unisim %s-588] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-596] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DATA_WIDTH_REG != 20) && + (TX_DATA_WIDTH_REG != 16) && + (TX_DATA_WIDTH_REG != 32) && + (TX_DATA_WIDTH_REG != 40) && + (TX_DATA_WIDTH_REG != 64) && + (TX_DATA_WIDTH_REG != 80) && + (TX_DATA_WIDTH_REG != 128) && + (TX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-598] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRIVE_MODE_REG != "DIRECT") && + (TX_DRIVE_MODE_REG != "PIPE") && + (TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin + $display("Error: [Unisim %s-604] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_INT_DATAWIDTH_REG != 1) && + (TX_INT_DATAWIDTH_REG != 0) && + (TX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-610] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") && + (TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin + $display("Error: [Unisim %s-611] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGCLK_SEL_REG != "POSTPI") && + (TX_PROGCLK_SEL_REG != "CPLL") && + (TX_PROGCLK_SEL_REG != "PREPI"))) begin + $display("Error: [Unisim %s-626] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGDIV_CFG_REG != 0.0) && + (TX_PROGDIV_CFG_REG != 4.0) && + (TX_PROGDIV_CFG_REG != 5.0) && + (TX_PROGDIV_CFG_REG != 8.0) && + (TX_PROGDIV_CFG_REG != 10.0) && + (TX_PROGDIV_CFG_REG != 16.0) && + (TX_PROGDIV_CFG_REG != 16.5) && + (TX_PROGDIV_CFG_REG != 20.0) && + (TX_PROGDIV_CFG_REG != 32.0) && + (TX_PROGDIV_CFG_REG != 33.0) && + (TX_PROGDIV_CFG_REG != 40.0) && + (TX_PROGDIV_CFG_REG != 64.0) && + (TX_PROGDIV_CFG_REG != 66.0) && + (TX_PROGDIV_CFG_REG != 80.0) && + (TX_PROGDIV_CFG_REG != 100.0))) begin + $display("Error: [Unisim %s-627] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_XCLK_SEL_REG != "TXOUT") && + (TX_XCLK_SEL_REG != "TXUSR"))) begin + $display("Error: [Unisim %s-637] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign PMASCANCLK0_in = 1'b1; // tie off + assign PMASCANCLK1_in = 1'b1; // tie off + assign PMASCANCLK2_in = 1'b1; // tie off + assign PMASCANCLK3_in = 1'b1; // tie off + assign PMASCANCLK4_in = 1'b1; // tie off + assign PMASCANCLK5_in = 1'b1; // tie off + assign SCANCLK_in = 1'b1; // tie off + assign TSTCLK0_in = 1'b1; // tie off + assign TSTCLK1_in = 1'b1; // tie off + + assign PMASCANENB_in = 1'b1; // tie off + assign PMASCANIN_in = 12'b111111111111; // tie off + assign PMASCANMODEB_in = 1'b1; // tie off + assign PMASCANRSTEN_in = 1'b1; // tie off + assign SARCCLK_in = 1'b1; // tie off + assign SCANENB_in = 1'b1; // tie off + assign SCANIN_in = 19'b1111111111111111111; // tie off + assign SCANMODEB_in = 1'b1; // tie off + assign TSTPDOVRDB_in = 1'b1; // tie off + assign TSTPD_in = 5'b11111; // tie off + + SIP_GTHE3_CHANNEL #( + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), + .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG), + .SIM_VERSION (SIM_VERSION_REG) + ) SIP_GTHE3_CHANNEL_INST ( + .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG), + .ACJTAG_MODE (ACJTAG_MODE_REG), + .ACJTAG_RESET (ACJTAG_RESET_REG), + .ADAPT_CFG0 (ADAPT_CFG0_REG), + .ADAPT_CFG1 (ADAPT_CFG1_REG), + .AEN_CPLL (AEN_CPLL_REG), + .AEN_EYESCAN (AEN_EYESCAN_REG), + .AEN_LOOPBACK (AEN_LOOPBACK_REG), + .AEN_MASTER (AEN_MASTER_REG), + .AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG), + .AEN_POLARITY (AEN_POLARITY_REG), + .AEN_PRBS (AEN_PRBS_REG), + .AEN_QPI (AEN_QPI_REG), + .AEN_RESET (AEN_RESET_REG), + .AEN_RXCDR (AEN_RXCDR_REG), + .AEN_RXDFE (AEN_RXDFE_REG), + .AEN_RXDFELPM (AEN_RXDFELPM_REG), + .AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG), + .AEN_RXPHDLY (AEN_RXPHDLY_REG), + .AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG), + .AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG), + .AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG), + .AEN_TXPHDLY (AEN_TXPHDLY_REG), + .AEN_TXPI_PPM (AEN_TXPI_PPM_REG), + .AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG), + .AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG), + .AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG), + .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG), + .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG), + .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG), + .AMONITOR_CFG (AMONITOR_CFG_REG), + .A_AFECFOKEN (A_AFECFOKEN_REG), + .A_CPLLLOCKEN (A_CPLLLOCKEN_REG), + .A_CPLLPD (A_CPLLPD_REG), + .A_CPLLRESET (A_CPLLRESET_REG), + .A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG), + .A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG), + .A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG), + .A_DFECFOKHOLD (A_DFECFOKHOLD_REG), + .A_DFECFOKOVREN (A_DFECFOKOVREN_REG), + .A_EYESCANMODE (A_EYESCANMODE_REG), + .A_EYESCANRESET (A_EYESCANRESET_REG), + .A_GTRESETSEL (A_GTRESETSEL_REG), + .A_GTRXRESET (A_GTRXRESET_REG), + .A_GTTXRESET (A_GTTXRESET_REG), + .A_LOOPBACK (A_LOOPBACK_REG), + .A_LPMGCHOLD (A_LPMGCHOLD_REG), + .A_LPMGCOVREN (A_LPMGCOVREN_REG), + .A_LPMOSHOLD (A_LPMOSHOLD_REG), + .A_LPMOSOVREN (A_LPMOSOVREN_REG), + .A_RXBUFRESET (A_RXBUFRESET_REG), + .A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG), + .A_RXCDRHOLD (A_RXCDRHOLD_REG), + .A_RXCDROVRDEN (A_RXCDROVRDEN_REG), + .A_RXCDRRESET (A_RXCDRRESET_REG), + .A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG), + .A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG), + .A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG), + .A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG), + .A_RXDFELFHOLD (A_RXDFELFHOLD_REG), + .A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG), + .A_RXDFELPMRESET (A_RXDFELPMRESET_REG), + .A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG), + .A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG), + .A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG), + .A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG), + .A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG), + .A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG), + .A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG), + .A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG), + .A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG), + .A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG), + .A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG), + .A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG), + .A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG), + .A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG), + .A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG), + .A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG), + .A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG), + .A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG), + .A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG), + .A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG), + .A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG), + .A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG), + .A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG), + .A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG), + .A_RXDFEVSEN (A_RXDFEVSEN_REG), + .A_RXDFEXYDEN (A_RXDFEXYDEN_REG), + .A_RXDLYBYPASS (A_RXDLYBYPASS_REG), + .A_RXDLYEN (A_RXDLYEN_REG), + .A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG), + .A_RXDLYSRESET (A_RXDLYSRESET_REG), + .A_RXLPMEN (A_RXLPMEN_REG), + .A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG), + .A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG), + .A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG), + .A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG), + .A_RXMONITORSEL (A_RXMONITORSEL_REG), + .A_RXOOBRESET (A_RXOOBRESET_REG), + .A_RXOSCALRESET (A_RXOSCALRESET_REG), + .A_RXOSHOLD (A_RXOSHOLD_REG), + .A_RXOSOVRDEN (A_RXOSOVRDEN_REG), + .A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG), + .A_RXPCSRESET (A_RXPCSRESET_REG), + .A_RXPD (A_RXPD_REG), + .A_RXPHALIGN (A_RXPHALIGN_REG), + .A_RXPHALIGNEN (A_RXPHALIGNEN_REG), + .A_RXPHDLYPD (A_RXPHDLYPD_REG), + .A_RXPHDLYRESET (A_RXPHDLYRESET_REG), + .A_RXPHOVRDEN (A_RXPHOVRDEN_REG), + .A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG), + .A_RXPMARESET (A_RXPMARESET_REG), + .A_RXPOLARITY (A_RXPOLARITY_REG), + .A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG), + .A_RXPRBSSEL (A_RXPRBSSEL_REG), + .A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG), + .A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG), + .A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG), + .A_TXDEEMPH (A_TXDEEMPH_REG), + .A_TXDIFFCTRL (A_TXDIFFCTRL_REG), + .A_TXDLYBYPASS (A_TXDLYBYPASS_REG), + .A_TXDLYEN (A_TXDLYEN_REG), + .A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG), + .A_TXDLYSRESET (A_TXDLYSRESET_REG), + .A_TXELECIDLE (A_TXELECIDLE_REG), + .A_TXINHIBIT (A_TXINHIBIT_REG), + .A_TXMAINCURSOR (A_TXMAINCURSOR_REG), + .A_TXMARGIN (A_TXMARGIN_REG), + .A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG), + .A_TXPCSRESET (A_TXPCSRESET_REG), + .A_TXPD (A_TXPD_REG), + .A_TXPHALIGN (A_TXPHALIGN_REG), + .A_TXPHALIGNEN (A_TXPHALIGNEN_REG), + .A_TXPHDLYPD (A_TXPHDLYPD_REG), + .A_TXPHDLYRESET (A_TXPHDLYRESET_REG), + .A_TXPHINIT (A_TXPHINIT_REG), + .A_TXPHOVRDEN (A_TXPHOVRDEN_REG), + .A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG), + .A_TXPIPPMPD (A_TXPIPPMPD_REG), + .A_TXPIPPMSEL (A_TXPIPPMSEL_REG), + .A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG), + .A_TXPMARESET (A_TXPMARESET_REG), + .A_TXPOLARITY (A_TXPOLARITY_REG), + .A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG), + .A_TXPOSTCURSORINV (A_TXPOSTCURSORINV_REG), + .A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG), + .A_TXPRBSSEL (A_TXPRBSSEL_REG), + .A_TXPRECURSOR (A_TXPRECURSOR_REG), + .A_TXPRECURSORINV (A_TXPRECURSORINV_REG), + .A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG), + .A_TXQPIBIASEN (A_TXQPIBIASEN_REG), + .A_TXSWING (A_TXSWING_REG), + .A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG), + .CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG), + .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG), + .CLK_CORRECT_USE (CLK_CORRECT_USE_REG), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG), + .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG), + .CPLL_CFG0 (CPLL_CFG0_REG), + .CPLL_CFG1 (CPLL_CFG1_REG), + .CPLL_CFG2 (CPLL_CFG2_REG), + .CPLL_CFG3 (CPLL_CFG3_REG), + .CPLL_FBDIV (CPLL_FBDIV_REG), + .CPLL_FBDIV_45 (CPLL_FBDIV_45_REG), + .CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG), + .CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG), + .CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG), + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG), + .DDI_CTRL (DDI_CTRL_REG), + .DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG), + .DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG), + .DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG), + .DMONITOR_CFG0 (DMONITOR_CFG0_REG), + .DMONITOR_CFG1 (DMONITOR_CFG1_REG), + .ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG), + .ES_CONTROL (ES_CONTROL_REG), + .ES_ERRDET_EN (ES_ERRDET_EN_REG), + .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG), + .ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG), + .ES_PMA_CFG (ES_PMA_CFG_REG), + .ES_PRESCALE (ES_PRESCALE_REG), + .ES_QUALIFIER0 (ES_QUALIFIER0_REG), + .ES_QUALIFIER1 (ES_QUALIFIER1_REG), + .ES_QUALIFIER2 (ES_QUALIFIER2_REG), + .ES_QUALIFIER3 (ES_QUALIFIER3_REG), + .ES_QUALIFIER4 (ES_QUALIFIER4_REG), + .ES_QUAL_MASK0 (ES_QUAL_MASK0_REG), + .ES_QUAL_MASK1 (ES_QUAL_MASK1_REG), + .ES_QUAL_MASK2 (ES_QUAL_MASK2_REG), + .ES_QUAL_MASK3 (ES_QUAL_MASK3_REG), + .ES_QUAL_MASK4 (ES_QUAL_MASK4_REG), + .ES_SDATA_MASK0 (ES_SDATA_MASK0_REG), + .ES_SDATA_MASK1 (ES_SDATA_MASK1_REG), + .ES_SDATA_MASK2 (ES_SDATA_MASK2_REG), + .ES_SDATA_MASK3 (ES_SDATA_MASK3_REG), + .ES_SDATA_MASK4 (ES_SDATA_MASK4_REG), + .EVODD_PHI_CFG (EVODD_PHI_CFG_REG), + .EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG), + .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG), + .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG), + .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG), + .GEARBOX_MODE (GEARBOX_MODE_REG), + .GEN_RXUSRCLK (GEN_RXUSRCLK_REG), + .GEN_TXUSRCLK (GEN_TXUSRCLK_REG), + .GM_BIAS_SELECT (GM_BIAS_SELECT_REG), + .GT_INSTANTIATED (GT_INSTANTIATED_REG), + .LOCAL_MASTER (LOCAL_MASTER_REG), + .OOBDIVCTL (OOBDIVCTL_REG), + .OOB_PWRUP (OOB_PWRUP_REG), + .PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG), + .PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG), + .PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG), + .PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG), + .PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG), + .PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG), + .PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG), + .PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG), + .PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG), + .PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG), + .PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG), + .PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG), + .PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG), + .PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG), + .PCS_PCIE_EN (PCS_PCIE_EN_REG), + .PCS_RSVD0 (PCS_RSVD0_REG), + .PCS_RSVD1 (PCS_RSVD1_REG), + .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG), + .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG), + .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG), + .PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG), + .PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG), + .PMA_RSV1 (PMA_RSV1_REG), + .PROCESS_PAR (PROCESS_PAR_REG), + .RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG), + .RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG), + .RXBUFRESET_TIME (RXBUFRESET_TIME_REG), + .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG), + .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG), + .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG), + .RXBUF_EN (RXBUF_EN_REG), + .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG), + .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG), + .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG), + .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG), + .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG), + .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG), + .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG), + .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG), + .RXCDR_CFG0 (RXCDR_CFG0_REG), + .RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG), + .RXCDR_CFG1 (RXCDR_CFG1_REG), + .RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG), + .RXCDR_CFG2 (RXCDR_CFG2_REG), + .RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG), + .RXCDR_CFG3 (RXCDR_CFG3_REG), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG), + .RXCDR_CFG4 (RXCDR_CFG4_REG), + .RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG), + .RXCDR_CFG5 (RXCDR_CFG5_REG), + .RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG), + .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG), + .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG), + .RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG), + .RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG), + .RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG), + .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG), + .RXCFOK_CFG0 (RXCFOK_CFG0_REG), + .RXCFOK_CFG1 (RXCFOK_CFG1_REG), + .RXCFOK_CFG2 (RXCFOK_CFG2_REG), + .RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG), + .RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG), + .RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG), + .RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG), + .RXDFE_CFG0 (RXDFE_CFG0_REG), + .RXDFE_CFG1 (RXDFE_CFG1_REG), + .RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG), + .RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG), + .RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG), + .RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG), + .RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG), + .RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG), + .RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG), + .RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG), + .RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG), + .RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG), + .RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG), + .RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG), + .RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG), + .RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG), + .RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG), + .RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG), + .RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG), + .RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG), + .RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG), + .RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG), + .RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG), + .RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG), + .RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG), + .RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG), + .RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG), + .RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG), + .RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG), + .RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG), + .RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG), + .RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG), + .RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG), + .RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG), + .RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG), + .RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG), + .RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG), + .RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG), + .RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG), + .RXDLY_CFG (RXDLY_CFG_REG), + .RXDLY_LCFG (RXDLY_LCFG_REG), + .RXELECIDLE_CFG (RXELECIDLE_CFG_REG), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG), + .RXGEARBOX_EN (RXGEARBOX_EN_REG), + .RXISCANRESET_TIME (RXISCANRESET_TIME_REG), + .RXLPM_CFG (RXLPM_CFG_REG), + .RXLPM_GC_CFG (RXLPM_GC_CFG_REG), + .RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG), + .RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG), + .RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG), + .RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG), + .RXOOB_CFG (RXOOB_CFG_REG), + .RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG), + .RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG), + .RXOUT_DIV (RXOUT_DIV_REG), + .RXPCSRESET_TIME (RXPCSRESET_TIME_REG), + .RXPHBEACON_CFG (RXPHBEACON_CFG_REG), + .RXPHDLY_CFG (RXPHDLY_CFG_REG), + .RXPHSAMP_CFG (RXPHSAMP_CFG_REG), + .RXPHSLIP_CFG (RXPHSLIP_CFG_REG), + .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG), + .RXPI_CFG0 (RXPI_CFG0_REG), + .RXPI_CFG1 (RXPI_CFG1_REG), + .RXPI_CFG2 (RXPI_CFG2_REG), + .RXPI_CFG3 (RXPI_CFG3_REG), + .RXPI_CFG4 (RXPI_CFG4_REG), + .RXPI_CFG5 (RXPI_CFG5_REG), + .RXPI_CFG6 (RXPI_CFG6_REG), + .RXPI_LPM (RXPI_LPM_REG), + .RXPI_VREFSEL (RXPI_VREFSEL_REG), + .RXPLL_SEL (RXPLL_SEL_REG), + .RXPMACLK_SEL (RXPMACLK_SEL_REG), + .RXPMARESET_TIME (RXPMARESET_TIME_REG), + .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG), + .RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG), + .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG), + .RXSLIDE_MODE (RXSLIDE_MODE_REG), + .RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG), + .RXSYNC_OVRD (RXSYNC_OVRD_REG), + .RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG), + .RX_AFE_CM_EN (RX_AFE_CM_EN_REG), + .RX_BIAS_CFG0 (RX_BIAS_CFG0_REG), + .RX_BUFFER_CFG (RX_BUFFER_CFG_REG), + .RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG), + .RX_CLK25_DIV (RX_CLK25_DIV_REG), + .RX_CLKMUX_EN (RX_CLKMUX_EN_REG), + .RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG), + .RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG), + .RX_CM_BUF_PD (RX_CM_BUF_PD_REG), + .RX_CM_SEL (RX_CM_SEL_REG), + .RX_CM_TRIM (RX_CM_TRIM_REG), + .RX_CTLE3_LPF (RX_CTLE3_LPF_REG), + .RX_DATA_WIDTH (RX_DATA_WIDTH_REG), + .RX_DDI_SEL (RX_DDI_SEL_REG), + .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG), + .RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG), + .RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG), + .RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG), + .RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG), + .RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG), + .RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG), + .RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG), + .RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG), + .RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG), + .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG), + .RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG), + .RX_EN_HI_LR (RX_EN_HI_LR_REG), + .RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG), + .RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG), + .RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG), + .RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG), + .RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG), + .RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG), + .RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN), + .RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG), + .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG), + .RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG), + .RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG), + .RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG), + .RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG), + .RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG), + .RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG), + .RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG), + .RX_XCLK_SEL (RX_XCLK_SEL_REG), + .SAS_MAX_COM (SAS_MAX_COM_REG), + .SAS_MIN_COM (SAS_MIN_COM_REG), + .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG), + .SATA_BURST_VAL (SATA_BURST_VAL_REG), + .SATA_CPLL_CFG (SATA_CPLL_CFG_REG), + .SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG), + .SATA_MAX_BURST (SATA_MAX_BURST_REG), + .SATA_MAX_INIT (SATA_MAX_INIT_REG), + .SATA_MAX_WAKE (SATA_MAX_WAKE_REG), + .SATA_MIN_BURST (SATA_MIN_BURST_REG), + .SATA_MIN_INIT (SATA_MIN_INIT_REG), + .SATA_MIN_WAKE (SATA_MIN_WAKE_REG), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG), + .TAPDLY_SET_TX (TAPDLY_SET_TX_REG), + .TEMPERATUR_PAR (TEMPERATUR_PAR_REG), + .TERM_RCAL_CFG (TERM_RCAL_CFG_REG), + .TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG), + .TRANS_TIME_RATE (TRANS_TIME_RATE_REG), + .TST_RSV0 (TST_RSV0_REG), + .TST_RSV1 (TST_RSV1_REG), + .TXBUF_EN (TXBUF_EN_REG), + .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG), + .TXDLY_CFG (TXDLY_CFG_REG), + .TXDLY_LCFG (TXDLY_LCFG_REG), + .TXDRVBIAS_N (TXDRVBIAS_N_REG), + .TXDRVBIAS_P (TXDRVBIAS_P_REG), + .TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG), + .TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG), + .TXGEARBOX_EN (TXGEARBOX_EN_REG), + .TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG), + .TXOUT_DIV (TXOUT_DIV_REG), + .TXPCSRESET_TIME (TXPCSRESET_TIME_REG), + .TXPHDLY_CFG0 (TXPHDLY_CFG0_REG), + .TXPHDLY_CFG1 (TXPHDLY_CFG1_REG), + .TXPH_CFG (TXPH_CFG_REG), + .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG), + .TXPI_CFG0 (TXPI_CFG0_REG), + .TXPI_CFG1 (TXPI_CFG1_REG), + .TXPI_CFG2 (TXPI_CFG2_REG), + .TXPI_CFG3 (TXPI_CFG3_REG), + .TXPI_CFG4 (TXPI_CFG4_REG), + .TXPI_CFG5 (TXPI_CFG5_REG), + .TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG), + .TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG), + .TXPI_LPM (TXPI_LPM_REG), + .TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG), + .TXPI_PPM_CFG (TXPI_PPM_CFG_REG), + .TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG), + .TXPI_VREFSEL (TXPI_VREFSEL_REG), + .TXPMARESET_TIME (TXPMARESET_TIME_REG), + .TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG), + .TXSYNC_OVRD (TXSYNC_OVRD_REG), + .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG), + .TX_CLK25_DIV (TX_CLK25_DIV_REG), + .TX_CLKMUX_EN (TX_CLKMUX_EN_REG), + .TX_DATA_WIDTH (TX_DATA_WIDTH_REG), + .TX_DCD_CFG (TX_DCD_CFG_REG), + .TX_DCD_EN (TX_DCD_EN_REG), + .TX_DEEMPH0 (TX_DEEMPH0_REG), + .TX_DEEMPH1 (TX_DEEMPH1_REG), + .TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG), + .TX_DRIVE_MODE (TX_DRIVE_MODE_REG), + .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG), + .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG), + .TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG), + .TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG), + .TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG), + .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG), + .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG), + .TX_MODE_SEL (TX_MODE_SEL_REG), + .TX_PMADATA_OPT (TX_PMADATA_OPT_REG), + .TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG), + .TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG), + .TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN), + .TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG), + .TX_RXDETECT_REF (TX_RXDETECT_REF_REG), + .TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG), + .TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG), + .TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG), + .TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG), + .TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG), + .TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG), + .TX_XCLK_SEL (TX_XCLK_SEL_REG), + .USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG), + .WB_MODE (WB_MODE_REG), + .BUFGTCE (BUFGTCE_out), + .BUFGTCEMASK (BUFGTCEMASK_out), + .BUFGTDIV (BUFGTDIV_out), + .BUFGTRESET (BUFGTRESET_out), + .BUFGTRSTMASK (BUFGTRSTMASK_out), + .CPLLFBCLKLOST (CPLLFBCLKLOST_out), + .CPLLLOCK (CPLLLOCK_out), + .CPLLREFCLKLOST (CPLLREFCLKLOST_out), + .DMONITOROUT (DMONITOROUT_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .EYESCANDATAERROR (EYESCANDATAERROR_out), + .GTHTXN (GTHTXN_out), + .GTHTXP (GTHTXP_out), + .GTPOWERGOOD (GTPOWERGOOD_out), + .GTREFCLKMONITOR (GTREFCLKMONITOR_out), + .PCIERATEGEN3 (PCIERATEGEN3_out), + .PCIERATEIDLE (PCIERATEIDLE_out), + .PCIERATEQPLLPD (PCIERATEQPLLPD_out), + .PCIERATEQPLLRESET (PCIERATEQPLLRESET_out), + .PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out), + .PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out), + .PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out), + .PCIEUSERRATESTART (PCIEUSERRATESTART_out), + .PCSRSVDOUT (PCSRSVDOUT_out), + .PHYSTATUS (PHYSTATUS_out), + .PINRSRVDAS (PINRSRVDAS_out), + .PMASCANOUT (PMASCANOUT_out), + .RESETEXCEPTION (RESETEXCEPTION_out), + .RXBUFSTATUS (RXBUFSTATUS_out), + .RXBYTEISALIGNED (RXBYTEISALIGNED_out), + .RXBYTEREALIGN (RXBYTEREALIGN_out), + .RXCDRLOCK (RXCDRLOCK_out), + .RXCDRPHDONE (RXCDRPHDONE_out), + .RXCHANBONDSEQ (RXCHANBONDSEQ_out), + .RXCHANISALIGNED (RXCHANISALIGNED_out), + .RXCHANREALIGN (RXCHANREALIGN_out), + .RXCHBONDO (RXCHBONDO_out), + .RXCLKCORCNT (RXCLKCORCNT_out), + .RXCOMINITDET (RXCOMINITDET_out), + .RXCOMMADET (RXCOMMADET_out), + .RXCOMSASDET (RXCOMSASDET_out), + .RXCOMWAKEDET (RXCOMWAKEDET_out), + .RXCTRL0 (RXCTRL0_out), + .RXCTRL1 (RXCTRL1_out), + .RXCTRL2 (RXCTRL2_out), + .RXCTRL3 (RXCTRL3_out), + .RXDATA (RXDATA_out), + .RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out), + .RXDATAVALID (RXDATAVALID_out), + .RXDLYSRESETDONE (RXDLYSRESETDONE_out), + .RXELECIDLE (RXELECIDLE_out), + .RXHEADER (RXHEADER_out), + .RXHEADERVALID (RXHEADERVALID_out), + .RXMONITOROUT (RXMONITOROUT_out), + .RXOSINTDONE (RXOSINTDONE_out), + .RXOSINTSTARTED (RXOSINTSTARTED_out), + .RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out), + .RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out), + .RXOUTCLK (RXOUTCLK_out), + .RXOUTCLKFABRIC (RXOUTCLKFABRIC_out), + .RXOUTCLKPCS (RXOUTCLKPCS_out), + .RXPHALIGNDONE (RXPHALIGNDONE_out), + .RXPHALIGNERR (RXPHALIGNERR_out), + .RXPMARESETDONE (RXPMARESETDONE_out), + .RXPRBSERR (RXPRBSERR_out), + .RXPRBSLOCKED (RXPRBSLOCKED_out), + .RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out), + .RXQPISENN (RXQPISENN_out), + .RXQPISENP (RXQPISENP_out), + .RXRATEDONE (RXRATEDONE_out), + .RXRECCLKOUT (RXRECCLKOUT_out), + .RXRESETDONE (RXRESETDONE_out), + .RXSLIDERDY (RXSLIDERDY_out), + .RXSLIPDONE (RXSLIPDONE_out), + .RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out), + .RXSLIPPMARDY (RXSLIPPMARDY_out), + .RXSTARTOFSEQ (RXSTARTOFSEQ_out), + .RXSTATUS (RXSTATUS_out), + .RXSYNCDONE (RXSYNCDONE_out), + .RXSYNCOUT (RXSYNCOUT_out), + .RXVALID (RXVALID_out), + .SCANOUT (SCANOUT_out), + .TXBUFSTATUS (TXBUFSTATUS_out), + .TXCOMFINISH (TXCOMFINISH_out), + .TXDLYSRESETDONE (TXDLYSRESETDONE_out), + .TXOUTCLK (TXOUTCLK_out), + .TXOUTCLKFABRIC (TXOUTCLKFABRIC_out), + .TXOUTCLKPCS (TXOUTCLKPCS_out), + .TXPHALIGNDONE (TXPHALIGNDONE_out), + .TXPHINITDONE (TXPHINITDONE_out), + .TXPMARESETDONE (TXPMARESETDONE_out), + .TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out), + .TXQPISENN (TXQPISENN_out), + .TXQPISENP (TXQPISENP_out), + .TXRATEDONE (TXRATEDONE_out), + .TXRESETDONE (TXRESETDONE_out), + .TXSYNCDONE (TXSYNCDONE_out), + .TXSYNCOUT (TXSYNCOUT_out), + .CFGRESET (CFGRESET_in), + .CLKRSVD0 (CLKRSVD0_in), + .CLKRSVD1 (CLKRSVD1_in), + .CPLLLOCKDETCLK (CPLLLOCKDETCLK_in), + .CPLLLOCKEN (CPLLLOCKEN_in), + .CPLLPD (CPLLPD_in), + .CPLLREFCLKSEL (CPLLREFCLKSEL_in), + .CPLLRESET (CPLLRESET_in), + .DMONFIFORESET (DMONFIFORESET_in), + .DMONITORCLK (DMONITORCLK_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .EVODDPHICALDONE (EVODDPHICALDONE_in), + .EVODDPHICALSTART (EVODDPHICALSTART_in), + .EVODDPHIDRDEN (EVODDPHIDRDEN_in), + .EVODDPHIDWREN (EVODDPHIDWREN_in), + .EVODDPHIXRDEN (EVODDPHIXRDEN_in), + .EVODDPHIXWREN (EVODDPHIXWREN_in), + .EYESCANMODE (EYESCANMODE_in), + .EYESCANRESET (EYESCANRESET_in), + .EYESCANTRIGGER (EYESCANTRIGGER_in), + .GTGREFCLK (GTGREFCLK_in), + .GTHRXN (GTHRXN_in), + .GTHRXP (GTHRXP_in), + .GTNORTHREFCLK0 (GTNORTHREFCLK0_in), + .GTNORTHREFCLK1 (GTNORTHREFCLK1_in), + .GTREFCLK0 (GTREFCLK0_in), + .GTREFCLK1 (GTREFCLK1_in), + .GTRESETSEL (GTRESETSEL_in), + .GTRSVD (GTRSVD_in), + .GTRXRESET (GTRXRESET_in), + .GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in), + .GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in), + .GTTXRESET (GTTXRESET_in), + .LOOPBACK (LOOPBACK_in), + .LPBKRXTXSEREN (LPBKRXTXSEREN_in), + .LPBKTXRXSEREN (LPBKTXRXSEREN_in), + .PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in), + .PCIERSTIDLE (PCIERSTIDLE_in), + .PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in), + .PCIEUSERRATEDONE (PCIEUSERRATEDONE_in), + .PCSRSVDIN (PCSRSVDIN_in), + .PCSRSVDIN2 (PCSRSVDIN2_in), + .PMARSVDIN (PMARSVDIN_in), + .PMASCANCLK0 (PMASCANCLK0_in), + .PMASCANCLK1 (PMASCANCLK1_in), + .PMASCANCLK2 (PMASCANCLK2_in), + .PMASCANCLK3 (PMASCANCLK3_in), + .PMASCANCLK4 (PMASCANCLK4_in), + .PMASCANCLK5 (PMASCANCLK5_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .PMASCANMODEB (PMASCANMODEB_in), + .PMASCANRSTEN (PMASCANRSTEN_in), + .QPLL0CLK (QPLL0CLK_in), + .QPLL0REFCLK (QPLL0REFCLK_in), + .QPLL1CLK (QPLL1CLK_in), + .QPLL1REFCLK (QPLL1REFCLK_in), + .RESETOVRD (RESETOVRD_in), + .RSTCLKENTX (RSTCLKENTX_in), + .RX8B10BEN (RX8B10BEN_in), + .RXBUFRESET (RXBUFRESET_in), + .RXCDRFREQRESET (RXCDRFREQRESET_in), + .RXCDRHOLD (RXCDRHOLD_in), + .RXCDROVRDEN (RXCDROVRDEN_in), + .RXCDRRESET (RXCDRRESET_in), + .RXCDRRESETRSV (RXCDRRESETRSV_in), + .RXCHBONDEN (RXCHBONDEN_in), + .RXCHBONDI (RXCHBONDI_in), + .RXCHBONDLEVEL (RXCHBONDLEVEL_in), + .RXCHBONDMASTER (RXCHBONDMASTER_in), + .RXCHBONDSLAVE (RXCHBONDSLAVE_in), + .RXCOMMADETEN (RXCOMMADETEN_in), + .RXDFEAGCCTRL (RXDFEAGCCTRL_in), + .RXDFEAGCHOLD (RXDFEAGCHOLD_in), + .RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in), + .RXDFELFHOLD (RXDFELFHOLD_in), + .RXDFELFOVRDEN (RXDFELFOVRDEN_in), + .RXDFELPMRESET (RXDFELPMRESET_in), + .RXDFETAP10HOLD (RXDFETAP10HOLD_in), + .RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in), + .RXDFETAP11HOLD (RXDFETAP11HOLD_in), + .RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in), + .RXDFETAP12HOLD (RXDFETAP12HOLD_in), + .RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in), + .RXDFETAP13HOLD (RXDFETAP13HOLD_in), + .RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in), + .RXDFETAP14HOLD (RXDFETAP14HOLD_in), + .RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in), + .RXDFETAP15HOLD (RXDFETAP15HOLD_in), + .RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in), + .RXDFETAP2HOLD (RXDFETAP2HOLD_in), + .RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in), + .RXDFETAP3HOLD (RXDFETAP3HOLD_in), + .RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in), + .RXDFETAP4HOLD (RXDFETAP4HOLD_in), + .RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in), + .RXDFETAP5HOLD (RXDFETAP5HOLD_in), + .RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in), + .RXDFETAP6HOLD (RXDFETAP6HOLD_in), + .RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in), + .RXDFETAP7HOLD (RXDFETAP7HOLD_in), + .RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in), + .RXDFETAP8HOLD (RXDFETAP8HOLD_in), + .RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in), + .RXDFETAP9HOLD (RXDFETAP9HOLD_in), + .RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in), + .RXDFEUTHOLD (RXDFEUTHOLD_in), + .RXDFEUTOVRDEN (RXDFEUTOVRDEN_in), + .RXDFEVPHOLD (RXDFEVPHOLD_in), + .RXDFEVPOVRDEN (RXDFEVPOVRDEN_in), + .RXDFEVSEN (RXDFEVSEN_in), + .RXDFEXYDEN (RXDFEXYDEN_in), + .RXDLYBYPASS (RXDLYBYPASS_in), + .RXDLYEN (RXDLYEN_in), + .RXDLYOVRDEN (RXDLYOVRDEN_in), + .RXDLYSRESET (RXDLYSRESET_in), + .RXELECIDLEMODE (RXELECIDLEMODE_in), + .RXGEARBOXSLIP (RXGEARBOXSLIP_in), + .RXLATCLK (RXLATCLK_in), + .RXLPMEN (RXLPMEN_in), + .RXLPMGCHOLD (RXLPMGCHOLD_in), + .RXLPMGCOVRDEN (RXLPMGCOVRDEN_in), + .RXLPMHFHOLD (RXLPMHFHOLD_in), + .RXLPMHFOVRDEN (RXLPMHFOVRDEN_in), + .RXLPMLFHOLD (RXLPMLFHOLD_in), + .RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in), + .RXLPMOSHOLD (RXLPMOSHOLD_in), + .RXLPMOSOVRDEN (RXLPMOSOVRDEN_in), + .RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in), + .RXMONITORSEL (RXMONITORSEL_in), + .RXOOBRESET (RXOOBRESET_in), + .RXOSCALRESET (RXOSCALRESET_in), + .RXOSHOLD (RXOSHOLD_in), + .RXOSINTCFG (RXOSINTCFG_in), + .RXOSINTEN (RXOSINTEN_in), + .RXOSINTHOLD (RXOSINTHOLD_in), + .RXOSINTOVRDEN (RXOSINTOVRDEN_in), + .RXOSINTSTROBE (RXOSINTSTROBE_in), + .RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in), + .RXOSOVRDEN (RXOSOVRDEN_in), + .RXOUTCLKSEL (RXOUTCLKSEL_in), + .RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in), + .RXPCSRESET (RXPCSRESET_in), + .RXPD (RXPD_in), + .RXPHALIGN (RXPHALIGN_in), + .RXPHALIGNEN (RXPHALIGNEN_in), + .RXPHDLYPD (RXPHDLYPD_in), + .RXPHDLYRESET (RXPHDLYRESET_in), + .RXPHOVRDEN (RXPHOVRDEN_in), + .RXPLLCLKSEL (RXPLLCLKSEL_in), + .RXPMARESET (RXPMARESET_in), + .RXPOLARITY (RXPOLARITY_in), + .RXPRBSCNTRESET (RXPRBSCNTRESET_in), + .RXPRBSSEL (RXPRBSSEL_in), + .RXPROGDIVRESET (RXPROGDIVRESET_in), + .RXQPIEN (RXQPIEN_in), + .RXRATE (RXRATE_in), + .RXRATEMODE (RXRATEMODE_in), + .RXSLIDE (RXSLIDE_in), + .RXSLIPOUTCLK (RXSLIPOUTCLK_in), + .RXSLIPPMA (RXSLIPPMA_in), + .RXSYNCALLIN (RXSYNCALLIN_in), + .RXSYNCIN (RXSYNCIN_in), + .RXSYNCMODE (RXSYNCMODE_in), + .RXSYSCLKSEL (RXSYSCLKSEL_in), + .RXUSERRDY (RXUSERRDY_in), + .RXUSRCLK (RXUSRCLK_in), + .RXUSRCLK2 (RXUSRCLK2_in), + .SARCCLK (SARCCLK_in), + .SCANCLK (SCANCLK_in), + .SCANENB (SCANENB_in), + .SCANIN (SCANIN_in), + .SCANMODEB (SCANMODEB_in), + .SIGVALIDCLK (SIGVALIDCLK_in), + .TSTCLK0 (TSTCLK0_in), + .TSTCLK1 (TSTCLK1_in), + .TSTIN (TSTIN_in), + .TSTPD (TSTPD_in), + .TSTPDOVRDB (TSTPDOVRDB_in), + .TX8B10BBYPASS (TX8B10BBYPASS_in), + .TX8B10BEN (TX8B10BEN_in), + .TXBUFDIFFCTRL (TXBUFDIFFCTRL_in), + .TXCOMINIT (TXCOMINIT_in), + .TXCOMSAS (TXCOMSAS_in), + .TXCOMWAKE (TXCOMWAKE_in), + .TXCTRL0 (TXCTRL0_in), + .TXCTRL1 (TXCTRL1_in), + .TXCTRL2 (TXCTRL2_in), + .TXDATA (TXDATA_in), + .TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in), + .TXDEEMPH (TXDEEMPH_in), + .TXDETECTRX (TXDETECTRX_in), + .TXDIFFCTRL (TXDIFFCTRL_in), + .TXDIFFPD (TXDIFFPD_in), + .TXDLYBYPASS (TXDLYBYPASS_in), + .TXDLYEN (TXDLYEN_in), + .TXDLYHOLD (TXDLYHOLD_in), + .TXDLYOVRDEN (TXDLYOVRDEN_in), + .TXDLYSRESET (TXDLYSRESET_in), + .TXDLYUPDOWN (TXDLYUPDOWN_in), + .TXELECIDLE (TXELECIDLE_in), + .TXHEADER (TXHEADER_in), + .TXINHIBIT (TXINHIBIT_in), + .TXLATCLK (TXLATCLK_in), + .TXMAINCURSOR (TXMAINCURSOR_in), + .TXMARGIN (TXMARGIN_in), + .TXOUTCLKSEL (TXOUTCLKSEL_in), + .TXPCSRESET (TXPCSRESET_in), + .TXPD (TXPD_in), + .TXPDELECIDLEMODE (TXPDELECIDLEMODE_in), + .TXPHALIGN (TXPHALIGN_in), + .TXPHALIGNEN (TXPHALIGNEN_in), + .TXPHDLYPD (TXPHDLYPD_in), + .TXPHDLYRESET (TXPHDLYRESET_in), + .TXPHDLYTSTCLK (TXPHDLYTSTCLK_in), + .TXPHINIT (TXPHINIT_in), + .TXPHOVRDEN (TXPHOVRDEN_in), + .TXPIPPMEN (TXPIPPMEN_in), + .TXPIPPMOVRDEN (TXPIPPMOVRDEN_in), + .TXPIPPMPD (TXPIPPMPD_in), + .TXPIPPMSEL (TXPIPPMSEL_in), + .TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in), + .TXPISOPD (TXPISOPD_in), + .TXPLLCLKSEL (TXPLLCLKSEL_in), + .TXPMARESET (TXPMARESET_in), + .TXPOLARITY (TXPOLARITY_in), + .TXPOSTCURSOR (TXPOSTCURSOR_in), + .TXPOSTCURSORINV (TXPOSTCURSORINV_in), + .TXPRBSFORCEERR (TXPRBSFORCEERR_in), + .TXPRBSSEL (TXPRBSSEL_in), + .TXPRECURSOR (TXPRECURSOR_in), + .TXPRECURSORINV (TXPRECURSORINV_in), + .TXPROGDIVRESET (TXPROGDIVRESET_in), + .TXQPIBIASEN (TXQPIBIASEN_in), + .TXQPISTRONGPDOWN (TXQPISTRONGPDOWN_in), + .TXQPIWEAKPUP (TXQPIWEAKPUP_in), + .TXRATE (TXRATE_in), + .TXRATEMODE (TXRATEMODE_in), + .TXSEQUENCE (TXSEQUENCE_in), + .TXSWING (TXSWING_in), + .TXSYNCALLIN (TXSYNCALLIN_in), + .TXSYNCIN (TXSYNCIN_in), + .TXSYNCMODE (TXSYNCMODE_in), + .TXSYSCLKSEL (TXSYSCLKSEL_in), + .TXUSERRDY (TXUSERRDY_in), + .TXUSRCLK (TXUSRCLK_in), + .TXUSRCLK2 (TXUSRCLK2_in), + .GSR (glblGSR) + ); + + specify + (DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRESETDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRESETDONE) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK2, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTHE3_COMMON.v b/verilog/src/unisims/GTHE3_COMMON.v new file mode 100644 index 0000000..e898aea --- /dev/null +++ b/verilog/src/unisims/GTHE3_COMMON.v @@ -0,0 +1,997 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : GTHE3_COMMON.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTHE3_COMMON #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] BIAS_CFG0 = 16'h0000, + parameter [15:0] BIAS_CFG1 = 16'h0000, + parameter [15:0] BIAS_CFG2 = 16'h0000, + parameter [15:0] BIAS_CFG3 = 16'h0040, + parameter [15:0] BIAS_CFG4 = 16'h0000, + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000, + parameter [15:0] COMMON_CFG0 = 16'h0000, + parameter [15:0] COMMON_CFG1 = 16'h0000, + parameter [15:0] POR_CFG = 16'h0004, + parameter [15:0] QPLL0_CFG0 = 16'h3018, + parameter [15:0] QPLL0_CFG1 = 16'h0000, + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL0_CFG2 = 16'h0000, + parameter [15:0] QPLL0_CFG2_G3 = 16'h0000, + parameter [15:0] QPLL0_CFG3 = 16'h0120, + parameter [15:0] QPLL0_CFG4 = 16'h0009, + parameter [9:0] QPLL0_CP = 10'b0000011111, + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111, + parameter integer QPLL0_FBDIV = 66, + parameter integer QPLL0_FBDIV_G3 = 80, + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8, + parameter [9:0] QPLL0_LPF = 10'b1111111111, + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111, + parameter integer QPLL0_REFCLK_DIV = 2, + parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000, + parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000, + parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000, + parameter [15:0] QPLL1_CFG0 = 16'h3018, + parameter [15:0] QPLL1_CFG1 = 16'h0000, + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL1_CFG2 = 16'h0000, + parameter [15:0] QPLL1_CFG2_G3 = 16'h0000, + parameter [15:0] QPLL1_CFG3 = 16'h0120, + parameter [15:0] QPLL1_CFG4 = 16'h0009, + parameter [9:0] QPLL1_CP = 10'b0000011111, + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111, + parameter integer QPLL1_FBDIV = 66, + parameter integer QPLL1_FBDIV_G3 = 80, + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL1_LPF = 10'b1111111111, + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111, + parameter integer QPLL1_REFCLK_DIV = 2, + parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000, + parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000, + parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000, + parameter [15:0] RSVD_ATTR0 = 16'h0000, + parameter [15:0] RSVD_ATTR1 = 16'h0000, + parameter [15:0] RSVD_ATTR2 = 16'h0000, + parameter [15:0] RSVD_ATTR3 = 16'h0000, + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00, + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00, + parameter [0:0] SARC_EN = 1'b1, + parameter [0:0] SARC_SEL = 1'b0, + parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000, + parameter [8:0] SDM0DATA1_1 = 9'b000000000, + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000, + parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0, + parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0, + parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000, + parameter [8:0] SDM1DATA1_1 = 9'b000000000, + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000, + parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0, + parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0, + parameter SIM_MODE = "FAST", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter integer SIM_VERSION = 2 +)( + output [15:0] DRPDO, + output DRPRDY, + output [7:0] PMARSVDOUT0, + output [7:0] PMARSVDOUT1, + output QPLL0FBCLKLOST, + output QPLL0LOCK, + output QPLL0OUTCLK, + output QPLL0OUTREFCLK, + output QPLL0REFCLKLOST, + output QPLL1FBCLKLOST, + output QPLL1LOCK, + output QPLL1OUTCLK, + output QPLL1OUTREFCLK, + output QPLL1REFCLKLOST, + output [7:0] QPLLDMONITOR0, + output [7:0] QPLLDMONITOR1, + output REFCLKOUTMONITOR0, + output REFCLKOUTMONITOR1, + output [1:0] RXRECCLK0_SEL, + output [1:0] RXRECCLK1_SEL, + + input BGBYPASSB, + input BGMONITORENB, + input BGPDB, + input [4:0] BGRCALOVRD, + input BGRCALOVRDENB, + input [8:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input GTGREFCLK0, + input GTGREFCLK1, + input GTNORTHREFCLK00, + input GTNORTHREFCLK01, + input GTNORTHREFCLK10, + input GTNORTHREFCLK11, + input GTREFCLK00, + input GTREFCLK01, + input GTREFCLK10, + input GTREFCLK11, + input GTSOUTHREFCLK00, + input GTSOUTHREFCLK01, + input GTSOUTHREFCLK10, + input GTSOUTHREFCLK11, + input [7:0] PMARSVD0, + input [7:0] PMARSVD1, + input QPLL0CLKRSVD0, + input QPLL0CLKRSVD1, + input QPLL0LOCKDETCLK, + input QPLL0LOCKEN, + input QPLL0PD, + input [2:0] QPLL0REFCLKSEL, + input QPLL0RESET, + input QPLL1CLKRSVD0, + input QPLL1CLKRSVD1, + input QPLL1LOCKDETCLK, + input QPLL1LOCKEN, + input QPLL1PD, + input [2:0] QPLL1REFCLKSEL, + input QPLL1RESET, + input [7:0] QPLLRSVD1, + input [4:0] QPLLRSVD2, + input [4:0] QPLLRSVD3, + input [7:0] QPLLRSVD4, + input RCALENB +); + +// define constants + localparam MODULE_NAME = "GTHE3_COMMON"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "GTHE3_COMMON_dr.v" +`else + localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0; + localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1; + localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2; + localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3; + localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4; + localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD; + localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0; + localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1; + localparam [15:0] POR_CFG_REG = POR_CFG; + localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0; + localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1; + localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3; + localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2; + localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3; + localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3; + localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4; + localparam [9:0] QPLL0_CP_REG = QPLL0_CP; + localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3; + localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV; + localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3; + localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0; + localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1; + localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG; + localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3; + localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF; + localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3; + localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV; + localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0; + localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1; + localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2; + localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0; + localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1; + localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3; + localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2; + localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3; + localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3; + localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4; + localparam [9:0] QPLL1_CP_REG = QPLL1_CP; + localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3; + localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV; + localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3; + localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0; + localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1; + localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG; + localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3; + localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF; + localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3; + localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV; + localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0; + localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1; + localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2; + localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0; + localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1; + localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2; + localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3; + localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL; + localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL; + localparam [0:0] SARC_EN_REG = SARC_EN; + localparam [0:0] SARC_SEL_REG = SARC_SEL; + localparam [15:0] SDM0DATA1_0_REG = SDM0DATA1_0; + localparam [8:0] SDM0DATA1_1_REG = SDM0DATA1_1; + localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0; + localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1; + localparam [0:0] SDM0_DATA_PIN_SEL_REG = SDM0_DATA_PIN_SEL; + localparam [0:0] SDM0_WIDTH_PIN_SEL_REG = SDM0_WIDTH_PIN_SEL; + localparam [15:0] SDM1DATA1_0_REG = SDM1DATA1_0; + localparam [8:0] SDM1DATA1_1_REG = SDM1DATA1_1; + localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0; + localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1; + localparam [0:0] SDM1_DATA_PIN_SEL_REG = SDM1_DATA_PIN_SEL; + localparam [0:0] SDM1_WIDTH_PIN_SEL_REG = SDM1_WIDTH_PIN_SEL; + localparam [80:1] SIM_MODE_REG = SIM_MODE; + localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + localparam [1:0] SIM_VERSION_REG = SIM_VERSION; +`endif + + localparam [0:0] AEN_BGBS0_REG = 1'b0; + localparam [0:0] AEN_BGBS1_REG = 1'b0; + localparam [0:0] AEN_MASTER0_REG = 1'b0; + localparam [0:0] AEN_MASTER1_REG = 1'b0; + localparam [0:0] AEN_PD0_REG = 1'b0; + localparam [0:0] AEN_PD1_REG = 1'b0; + localparam [0:0] AEN_QPLL0_REG = 1'b0; + localparam [0:0] AEN_QPLL1_REG = 1'b0; + localparam [0:0] AEN_REFCLK0_REG = 1'b0; + localparam [0:0] AEN_REFCLK1_REG = 1'b0; + localparam [0:0] AEN_RESET0_REG = 1'b0; + localparam [0:0] AEN_RESET1_REG = 1'b0; + localparam [3:0] AQDMUXSEL1_REG = 4'b0000; + localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000; + localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000; + localparam [0:0] A_BGMONITOREN_REG = 1'b0; + localparam [0:0] A_BGPD_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD0_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD1_REG = 1'b0; + localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL0PD_REG = 1'b0; + localparam [0:0] A_QPLL0RESET_REG = 1'b0; + localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL1PD_REG = 1'b0; + localparam [0:0] A_QPLL1RESET_REG = 1'b0; + localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00; + localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00; + localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1; + localparam [15:0] PPF0_CFG_REG = 16'h0000; + localparam [15:0] PPF1_CFG_REG = 16'h0000; + localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000; + localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000; + localparam [0:0] RCALSAP_TESTEN_REG = 1'b0; + localparam [0:0] RCAL_APROBE_REG = 1'b0; + localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0; + localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0; + localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire DRPRDY_out; + wire QPLL0FBCLKLOST_out; + wire QPLL0LOCK_out; + wire QPLL0OUTCLK_out; + wire QPLL0OUTREFCLK_out; + wire QPLL0REFCLKLOST_out; + wire QPLL1FBCLKLOST_out; + wire QPLL1LOCK_out; + wire QPLL1OUTCLK_out; + wire QPLL1OUTREFCLK_out; + wire QPLL1REFCLKLOST_out; + wire REFCLKOUTMONITOR0_out; + wire REFCLKOUTMONITOR1_out; + wire [15:0] DRPDO_out; + wire [1:0] RXRECCLK0_SEL_out; + wire [1:0] RXRECCLK1_SEL_out; + wire [3:0] SARCCLK_out; + wire [7:0] PMARSVDOUT0_out; + wire [7:0] PMARSVDOUT1_out; + wire [7:0] PMASCANOUT_out; + wire [7:0] QPLLDMONITOR0_out; + wire [7:0] QPLLDMONITOR1_out; + + wire DRPRDY_delay; + wire QPLL0FBCLKLOST_delay; + wire QPLL0LOCK_delay; + wire QPLL0OUTCLK_delay; + wire QPLL0OUTREFCLK_delay; + wire QPLL0REFCLKLOST_delay; + wire QPLL1FBCLKLOST_delay; + wire QPLL1LOCK_delay; + wire QPLL1OUTCLK_delay; + wire QPLL1OUTREFCLK_delay; + wire QPLL1REFCLKLOST_delay; + wire REFCLKOUTMONITOR0_delay; + wire REFCLKOUTMONITOR1_delay; + wire [15:0] DRPDO_delay; + wire [1:0] RXRECCLK0_SEL_delay; + wire [1:0] RXRECCLK1_SEL_delay; + wire [7:0] PMARSVDOUT0_delay; + wire [7:0] PMARSVDOUT1_delay; + wire [7:0] QPLLDMONITOR0_delay; + wire [7:0] QPLLDMONITOR1_delay; + + wire BGBYPASSB_in; + wire BGMONITORENB_in; + wire BGPDB_in; + wire BGRCALOVRDENB_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire GTGREFCLK0_in; + wire GTGREFCLK1_in; + wire GTNORTHREFCLK00_in; + wire GTNORTHREFCLK01_in; + wire GTNORTHREFCLK10_in; + wire GTNORTHREFCLK11_in; + wire GTREFCLK00_in; + wire GTREFCLK01_in; + wire GTREFCLK10_in; + wire GTREFCLK11_in; + wire GTSOUTHREFCLK00_in; + wire GTSOUTHREFCLK01_in; + wire GTSOUTHREFCLK10_in; + wire GTSOUTHREFCLK11_in; + wire PMASCANENB_in; + wire QDPMASCANMODEB_in; + wire QDPMASCANRSTEN_in; + wire QPLL0CLKRSVD0_in; + wire QPLL0CLKRSVD1_in; + wire QPLL0LOCKDETCLK_in; + wire QPLL0LOCKEN_in; + wire QPLL0PD_in; + wire QPLL0RESET_in; + wire QPLL1CLKRSVD0_in; + wire QPLL1CLKRSVD1_in; + wire QPLL1LOCKDETCLK_in; + wire QPLL1LOCKEN_in; + wire QPLL1PD_in; + wire QPLL1RESET_in; + wire RCALENB_in; + wire [15:0] DRPDI_in; + wire [2:0] QPLL0REFCLKSEL_in; + wire [2:0] QPLL1REFCLKSEL_in; + wire [3:0] RXRECCLK_in; + wire [4:0] BGRCALOVRD_in; + wire [4:0] QPLLRSVD2_in; + wire [4:0] QPLLRSVD3_in; + wire [7:0] PMARSVD0_in; + wire [7:0] PMARSVD1_in; + wire [7:0] PMASCANCLK_in; + wire [7:0] PMASCANIN_in; + wire [7:0] QPLLRSVD1_in; + wire [7:0] QPLLRSVD4_in; + wire [8:0] DRPADDR_in; + + wire BGBYPASSB_delay; + wire BGMONITORENB_delay; + wire BGPDB_delay; + wire BGRCALOVRDENB_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire GTGREFCLK0_delay; + wire GTGREFCLK1_delay; + wire GTNORTHREFCLK00_delay; + wire GTNORTHREFCLK01_delay; + wire GTNORTHREFCLK10_delay; + wire GTNORTHREFCLK11_delay; + wire GTREFCLK00_delay; + wire GTREFCLK01_delay; + wire GTREFCLK10_delay; + wire GTREFCLK11_delay; + wire GTSOUTHREFCLK00_delay; + wire GTSOUTHREFCLK01_delay; + wire GTSOUTHREFCLK10_delay; + wire GTSOUTHREFCLK11_delay; + wire QPLL0CLKRSVD0_delay; + wire QPLL0CLKRSVD1_delay; + wire QPLL0LOCKDETCLK_delay; + wire QPLL0LOCKEN_delay; + wire QPLL0PD_delay; + wire QPLL0RESET_delay; + wire QPLL1CLKRSVD0_delay; + wire QPLL1CLKRSVD1_delay; + wire QPLL1LOCKDETCLK_delay; + wire QPLL1LOCKEN_delay; + wire QPLL1PD_delay; + wire QPLL1RESET_delay; + wire RCALENB_delay; + wire [15:0] DRPDI_delay; + wire [2:0] QPLL0REFCLKSEL_delay; + wire [2:0] QPLL1REFCLKSEL_delay; + wire [4:0] BGRCALOVRD_delay; + wire [4:0] QPLLRSVD2_delay; + wire [4:0] QPLLRSVD3_delay; + wire [7:0] PMARSVD0_delay; + wire [7:0] PMARSVD1_delay; + wire [7:0] QPLLRSVD1_delay; + wire [7:0] QPLLRSVD4_delay; + wire [8:0] DRPADDR_delay; + + assign #(out_delay) DRPDO = DRPDO_delay; + assign #(out_delay) DRPRDY = DRPRDY_delay; + assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay; + assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay; + assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay; + assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay; + assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay; + assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay; + assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay; + assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay; + assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay; + assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay; + assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay; + assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay; + assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay; + assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay; + assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay; + assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay; + assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay; + assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) DRPCLK_delay = DRPCLK; + + assign #(in_delay) DRPADDR_delay = DRPADDR; + assign #(in_delay) DRPDI_delay = DRPDI; + assign #(in_delay) DRPEN_delay = DRPEN; + assign #(in_delay) DRPWE_delay = DRPWE; +`endif + +// inputs with no timing checks + assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0; + assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1; + assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00; + assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01; + assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10; + assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11; + assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00; + assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01; + assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10; + assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11; + assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00; + assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01; + assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10; + assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11; + assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0; + assign #(inclk_delay) QPLL0CLKRSVD1_delay = QPLL0CLKRSVD1; + assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK; + assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0; + assign #(inclk_delay) QPLL1CLKRSVD1_delay = QPLL1CLKRSVD1; + assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK; + + assign #(in_delay) BGBYPASSB_delay = BGBYPASSB; + assign #(in_delay) BGMONITORENB_delay = BGMONITORENB; + assign #(in_delay) BGPDB_delay = BGPDB; + assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB; + assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD; + assign #(in_delay) PMARSVD0_delay = PMARSVD0; + assign #(in_delay) PMARSVD1_delay = PMARSVD1; + assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN; + assign #(in_delay) QPLL0PD_delay = QPLL0PD; + assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL; + assign #(in_delay) QPLL0RESET_delay = QPLL0RESET; + assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN; + assign #(in_delay) QPLL1PD_delay = QPLL1PD; + assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL; + assign #(in_delay) QPLL1RESET_delay = QPLL1RESET; + assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1; + assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2; + assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3; + assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4; + assign #(in_delay) RCALENB_delay = RCALENB; + + assign DRPDO_delay = DRPDO_out; + assign DRPRDY_delay = DRPRDY_out; + assign PMARSVDOUT0_delay = PMARSVDOUT0_out; + assign PMARSVDOUT1_delay = PMARSVDOUT1_out; + assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out; + assign QPLL0LOCK_delay = QPLL0LOCK_out; + assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out; + assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out; + assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out; + assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out; + assign QPLL1LOCK_delay = QPLL1LOCK_out; + assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out; + assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out; + assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out; + assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out; + assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out; + assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out; + assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out; + assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out; + assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out; + + assign BGBYPASSB_in = BGBYPASSB_delay; + assign BGMONITORENB_in = BGMONITORENB_delay; + assign BGPDB_in = BGPDB_delay; + assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay; + assign BGRCALOVRD_in = BGRCALOVRD_delay; + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign GTGREFCLK0_in = GTGREFCLK0_delay; + assign GTGREFCLK1_in = GTGREFCLK1_delay; + assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay; + assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay; + assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay; + assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay; + assign GTREFCLK00_in = GTREFCLK00_delay; + assign GTREFCLK01_in = GTREFCLK01_delay; + assign GTREFCLK10_in = GTREFCLK10_delay; + assign GTREFCLK11_in = GTREFCLK11_delay; + assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay; + assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay; + assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay; + assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay; + assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0_delay[0]; // rv 0 + assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0_delay[1]; // rv 0 + assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0_delay[2]; // rv 0 + assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0_delay[3]; // rv 0 + assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0_delay[4]; // rv 0 + assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0_delay[5]; // rv 0 + assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0_delay[6]; // rv 0 + assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0_delay[7]; // rv 0 + assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1_delay[0]; // rv 0 + assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1_delay[1]; // rv 0 + assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1_delay[2]; // rv 0 + assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1_delay[3]; // rv 0 + assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1_delay[4]; // rv 0 + assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1_delay[5]; // rv 0 + assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1_delay[6]; // rv 0 + assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1_delay[7]; // rv 0 + assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 === 1'bz) || QPLL0CLKRSVD0_delay; // rv 1 + assign QPLL0CLKRSVD1_in = (QPLL0CLKRSVD1 === 1'bz) || QPLL0CLKRSVD1_delay; // rv 1 + assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK === 1'bz) || QPLL0LOCKDETCLK_delay; // rv 1 + assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN_delay; // rv 0 + assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD_delay; // rv 0 + assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL_delay[0]; // rv 1 + assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL_delay[1]; // rv 0 + assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL_delay[2]; // rv 0 + assign QPLL0RESET_in = (QPLL0RESET !== 1'bz) && QPLL0RESET_delay; // rv 0 + assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 === 1'bz) || QPLL1CLKRSVD0_delay; // rv 1 + assign QPLL1CLKRSVD1_in = (QPLL1CLKRSVD1 === 1'bz) || QPLL1CLKRSVD1_delay; // rv 1 + assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK === 1'bz) || QPLL1LOCKDETCLK_delay; // rv 1 + assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN_delay; // rv 0 + assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD_delay; // rv 0 + assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL_delay[0]; // rv 1 + assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL_delay[1]; // rv 0 + assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL_delay[2]; // rv 0 + assign QPLL1RESET_in = (QPLL1RESET !== 1'bz) && QPLL1RESET_delay; // rv 0 + assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1_delay[0]; // rv 0 + assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1_delay[1]; // rv 0 + assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1_delay[2]; // rv 0 + assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1_delay[3]; // rv 0 + assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1_delay[4]; // rv 0 + assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1_delay[5]; // rv 0 + assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1_delay[6]; // rv 0 + assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1_delay[7]; // rv 0 + assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2_delay[0]; // rv 0 + assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2_delay[1]; // rv 0 + assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2_delay[2]; // rv 0 + assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2_delay[3]; // rv 0 + assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2_delay[4]; // rv 0 + assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3_delay[0]; // rv 0 + assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3_delay[1]; // rv 0 + assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3_delay[2]; // rv 0 + assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3_delay[3]; // rv 0 + assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3_delay[4]; // rv 0 + assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4_delay[0]; // rv 0 + assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4_delay[1]; // rv 0 + assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4_delay[2]; // rv 0 + assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4_delay[3]; // rv 0 + assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4_delay[4]; // rv 0 + assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4_delay[5]; // rv 0 + assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4_delay[6]; // rv 0 + assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4_delay[7]; // rv 0 + assign RCALENB_in = RCALENB_delay; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-150] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-151] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_REFCLK_DIV_REG != 2) && + (QPLL0_REFCLK_DIV_REG != 1) && + (QPLL0_REFCLK_DIV_REG != 3) && + (QPLL0_REFCLK_DIV_REG != 4) && + (QPLL0_REFCLK_DIV_REG != 5) && + (QPLL0_REFCLK_DIV_REG != 6) && + (QPLL0_REFCLK_DIV_REG != 8) && + (QPLL0_REFCLK_DIV_REG != 10) && + (QPLL0_REFCLK_DIV_REG != 12) && + (QPLL0_REFCLK_DIV_REG != 16) && + (QPLL0_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-158] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-172] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-173] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_REFCLK_DIV_REG != 2) && + (QPLL1_REFCLK_DIV_REG != 1) && + (QPLL1_REFCLK_DIV_REG != 3) && + (QPLL1_REFCLK_DIV_REG != 4) && + (QPLL1_REFCLK_DIV_REG != 5) && + (QPLL1_REFCLK_DIV_REG != 6) && + (QPLL1_REFCLK_DIV_REG != 8) && + (QPLL1_REFCLK_DIV_REG != 10) && + (QPLL1_REFCLK_DIV_REG != 12) && + (QPLL1_REFCLK_DIV_REG != 16) && + (QPLL1_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-180] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_MODE_REG != "FAST")) begin + $display("Error: [Unisim %s-212] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-213] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE, or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2) && + (SIM_VERSION_REG != 1) && + (SIM_VERSION_REG != 3))) begin + $display("Error: [Unisim %s-214] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign PMASCANCLK_in = 8'b11111111; // tie off + + assign PMASCANENB_in = 1'b1; // tie off + assign PMASCANIN_in = 8'b11111111; // tie off + assign QDPMASCANMODEB_in = 1'b1; // tie off + assign QDPMASCANRSTEN_in = 1'b1; // tie off + assign RXRECCLK_in = 4'b1111; // tie off + + SIP_GTHE3_COMMON #( + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), + .SIM_VERSION (SIM_VERSION_REG) +) SIP_GTHE3_COMMON_INST ( + .AEN_BGBS0 (AEN_BGBS0_REG), + .AEN_BGBS1 (AEN_BGBS1_REG), + .AEN_MASTER0 (AEN_MASTER0_REG), + .AEN_MASTER1 (AEN_MASTER1_REG), + .AEN_PD0 (AEN_PD0_REG), + .AEN_PD1 (AEN_PD1_REG), + .AEN_QPLL0 (AEN_QPLL0_REG), + .AEN_QPLL1 (AEN_QPLL1_REG), + .AEN_REFCLK0 (AEN_REFCLK0_REG), + .AEN_REFCLK1 (AEN_REFCLK1_REG), + .AEN_RESET0 (AEN_RESET0_REG), + .AEN_RESET1 (AEN_RESET1_REG), + .AQDMUXSEL1 (AQDMUXSEL1_REG), + .AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG), + .AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG), + .A_BGMONITOREN (A_BGMONITOREN_REG), + .A_BGPD (A_BGPD_REG), + .A_GTREFCLKPD0 (A_GTREFCLKPD0_REG), + .A_GTREFCLKPD1 (A_GTREFCLKPD1_REG), + .A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG), + .A_QPLL0PD (A_QPLL0PD_REG), + .A_QPLL0RESET (A_QPLL0RESET_REG), + .A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG), + .A_QPLL1PD (A_QPLL1PD_REG), + .A_QPLL1RESET (A_QPLL1RESET_REG), + .BIAS_CFG0 (BIAS_CFG0_REG), + .BIAS_CFG1 (BIAS_CFG1_REG), + .BIAS_CFG2 (BIAS_CFG2_REG), + .BIAS_CFG3 (BIAS_CFG3_REG), + .BIAS_CFG4 (BIAS_CFG4_REG), + .BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG), + .COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG), + .COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG), + .COMMON_CFG0 (COMMON_CFG0_REG), + .COMMON_CFG1 (COMMON_CFG1_REG), + .COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG), + .POR_CFG (POR_CFG_REG), + .PPF0_CFG (PPF0_CFG_REG), + .PPF1_CFG (PPF1_CFG_REG), + .QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG), + .QPLL0_CFG0 (QPLL0_CFG0_REG), + .QPLL0_CFG1 (QPLL0_CFG1_REG), + .QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG), + .QPLL0_CFG2 (QPLL0_CFG2_REG), + .QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG), + .QPLL0_CFG3 (QPLL0_CFG3_REG), + .QPLL0_CFG4 (QPLL0_CFG4_REG), + .QPLL0_CP (QPLL0_CP_REG), + .QPLL0_CP_G3 (QPLL0_CP_G3_REG), + .QPLL0_FBDIV (QPLL0_FBDIV_REG), + .QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG), + .QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG), + .QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG), + .QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG), + .QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG), + .QPLL0_LPF (QPLL0_LPF_REG), + .QPLL0_LPF_G3 (QPLL0_LPF_G3_REG), + .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG), + .QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG), + .QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG), + .QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG), + .QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG), + .QPLL1_CFG0 (QPLL1_CFG0_REG), + .QPLL1_CFG1 (QPLL1_CFG1_REG), + .QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG), + .QPLL1_CFG2 (QPLL1_CFG2_REG), + .QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG), + .QPLL1_CFG3 (QPLL1_CFG3_REG), + .QPLL1_CFG4 (QPLL1_CFG4_REG), + .QPLL1_CP (QPLL1_CP_REG), + .QPLL1_CP_G3 (QPLL1_CP_G3_REG), + .QPLL1_FBDIV (QPLL1_FBDIV_REG), + .QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG), + .QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG), + .QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG), + .QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG), + .QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG), + .QPLL1_LPF (QPLL1_LPF_REG), + .QPLL1_LPF_G3 (QPLL1_LPF_G3_REG), + .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG), + .QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG), + .QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG), + .QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG), + .RCALSAP_TESTEN (RCALSAP_TESTEN_REG), + .RCAL_APROBE (RCAL_APROBE_REG), + .REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG), + .REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG), + .REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG), + .REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG), + .REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG), + .REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG), + .RSVD_ATTR0 (RSVD_ATTR0_REG), + .RSVD_ATTR1 (RSVD_ATTR1_REG), + .RSVD_ATTR2 (RSVD_ATTR2_REG), + .RSVD_ATTR3 (RSVD_ATTR3_REG), + .RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG), + .RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG), + .SARC_EN (SARC_EN_REG), + .SARC_SEL (SARC_SEL_REG), + .SDM0DATA1_0 (SDM0DATA1_0_REG), + .SDM0DATA1_1 (SDM0DATA1_1_REG), + .SDM0INITSEED0_0 (SDM0INITSEED0_0_REG), + .SDM0INITSEED0_1 (SDM0INITSEED0_1_REG), + .SDM0_DATA_PIN_SEL (SDM0_DATA_PIN_SEL_REG), + .SDM0_WIDTH_PIN_SEL (SDM0_WIDTH_PIN_SEL_REG), + .SDM1DATA1_0 (SDM1DATA1_0_REG), + .SDM1DATA1_1 (SDM1DATA1_1_REG), + .SDM1INITSEED0_0 (SDM1INITSEED0_0_REG), + .SDM1INITSEED0_1 (SDM1INITSEED0_1_REG), + .SDM1_DATA_PIN_SEL (SDM1_DATA_PIN_SEL_REG), + .SDM1_WIDTH_PIN_SEL (SDM1_WIDTH_PIN_SEL_REG), + .VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .PMARSVDOUT0 (PMARSVDOUT0_out), + .PMARSVDOUT1 (PMARSVDOUT1_out), + .PMASCANOUT (PMASCANOUT_out), + .QPLL0FBCLKLOST (QPLL0FBCLKLOST_out), + .QPLL0LOCK (QPLL0LOCK_out), + .QPLL0OUTCLK (QPLL0OUTCLK_out), + .QPLL0OUTREFCLK (QPLL0OUTREFCLK_out), + .QPLL0REFCLKLOST (QPLL0REFCLKLOST_out), + .QPLL1FBCLKLOST (QPLL1FBCLKLOST_out), + .QPLL1LOCK (QPLL1LOCK_out), + .QPLL1OUTCLK (QPLL1OUTCLK_out), + .QPLL1OUTREFCLK (QPLL1OUTREFCLK_out), + .QPLL1REFCLKLOST (QPLL1REFCLKLOST_out), + .QPLLDMONITOR0 (QPLLDMONITOR0_out), + .QPLLDMONITOR1 (QPLLDMONITOR1_out), + .REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out), + .REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out), + .RXRECCLK0_SEL (RXRECCLK0_SEL_out), + .RXRECCLK1_SEL (RXRECCLK1_SEL_out), + .SARCCLK (SARCCLK_out), + .BGBYPASSB (BGBYPASSB_in), + .BGMONITORENB (BGMONITORENB_in), + .BGPDB (BGPDB_in), + .BGRCALOVRD (BGRCALOVRD_in), + .BGRCALOVRDENB (BGRCALOVRDENB_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .GTGREFCLK0 (GTGREFCLK0_in), + .GTGREFCLK1 (GTGREFCLK1_in), + .GTNORTHREFCLK00 (GTNORTHREFCLK00_in), + .GTNORTHREFCLK01 (GTNORTHREFCLK01_in), + .GTNORTHREFCLK10 (GTNORTHREFCLK10_in), + .GTNORTHREFCLK11 (GTNORTHREFCLK11_in), + .GTREFCLK00 (GTREFCLK00_in), + .GTREFCLK01 (GTREFCLK01_in), + .GTREFCLK10 (GTREFCLK10_in), + .GTREFCLK11 (GTREFCLK11_in), + .GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in), + .GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in), + .GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in), + .GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in), + .PMARSVD0 (PMARSVD0_in), + .PMARSVD1 (PMARSVD1_in), + .PMASCANCLK (PMASCANCLK_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .QDPMASCANMODEB (QDPMASCANMODEB_in), + .QDPMASCANRSTEN (QDPMASCANRSTEN_in), + .QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in), + .QPLL0CLKRSVD1 (QPLL0CLKRSVD1_in), + .QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in), + .QPLL0LOCKEN (QPLL0LOCKEN_in), + .QPLL0PD (QPLL0PD_in), + .QPLL0REFCLKSEL (QPLL0REFCLKSEL_in), + .QPLL0RESET (QPLL0RESET_in), + .QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in), + .QPLL1CLKRSVD1 (QPLL1CLKRSVD1_in), + .QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in), + .QPLL1LOCKEN (QPLL1LOCKEN_in), + .QPLL1PD (QPLL1PD_in), + .QPLL1REFCLKSEL (QPLL1REFCLKSEL_in), + .QPLL1RESET (QPLL1RESET_in), + .QPLLRSVD1 (QPLLRSVD1_in), + .QPLLRSVD2 (QPLLRSVD2_in), + .QPLLRSVD3 (QPLLRSVD3_in), + .QPLLRSVD4 (QPLLRSVD4_in), + .RCALENB (RCALENB_in), + .RXRECCLK (RXRECCLK_in), + .GSR (glblGSR) + ); + + specify + (DRPCLK *> DRPDO) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTGREFCLK0 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTGREFCLK1 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + // (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output + // (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTHE4_CHANNEL.v b/verilog/src/unisims/GTHE4_CHANNEL.v new file mode 100644 index 0000000..9d6f704 --- /dev/null +++ b/verilog/src/unisims/GTHE4_CHANNEL.v @@ -0,0 +1,5566 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver for UltraScale+ devices +// /___/ /\ Filename : GTHE4_CHANNEL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTHE4_CHANNEL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0, + parameter [0:0] ACJTAG_MODE = 1'b0, + parameter [0:0] ACJTAG_RESET = 1'b0, + parameter [15:0] ADAPT_CFG0 = 16'h9200, + parameter [15:0] ADAPT_CFG1 = 16'h801C, + parameter [15:0] ADAPT_CFG2 = 16'h0000, + parameter ALIGN_COMMA_DOUBLE = "FALSE", + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111, + parameter integer ALIGN_COMMA_WORD = 1, + parameter ALIGN_MCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011, + parameter ALIGN_PCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100, + parameter [0:0] A_RXOSCALRESET = 1'b0, + parameter [0:0] A_RXPROGDIVRESET = 1'b0, + parameter [0:0] A_RXTERMINATION = 1'b1, + parameter [4:0] A_TXDIFFCTRL = 5'b01100, + parameter [0:0] A_TXPROGDIVRESET = 1'b0, + parameter [0:0] CAPBYPASS_FORCE = 1'b0, + parameter CBCC_DATA_SOURCE_SEL = "DECODED", + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0, + parameter [0:0] CFOK_PWRSVE_EN = 1'b1, + parameter CHAN_BOND_KEEP_ALIGN = "FALSE", + parameter integer CHAN_BOND_MAX_SKEW = 7, + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100, + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111, + parameter CHAN_BOND_SEQ_2_USE = "FALSE", + parameter integer CHAN_BOND_SEQ_LEN = 2, + parameter [15:0] CH_HSPMUX = 16'h2424, + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000, + parameter [15:0] CKCAL_RSVD0 = 16'h4000, + parameter [15:0] CKCAL_RSVD1 = 16'h0000, + parameter CLK_CORRECT_USE = "TRUE", + parameter CLK_COR_KEEP_IDLE = "FALSE", + parameter integer CLK_COR_MAX_LAT = 20, + parameter integer CLK_COR_MIN_LAT = 18, + parameter CLK_COR_PRECEDENCE = "TRUE", + parameter integer CLK_COR_REPEAT_WAIT = 0, + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100, + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111, + parameter CLK_COR_SEQ_2_USE = "FALSE", + parameter integer CLK_COR_SEQ_LEN = 2, + parameter [15:0] CPLL_CFG0 = 16'h01FA, + parameter [15:0] CPLL_CFG1 = 16'h24A9, + parameter [15:0] CPLL_CFG2 = 16'h6807, + parameter [15:0] CPLL_CFG3 = 16'h0000, + parameter integer CPLL_FBDIV = 4, + parameter integer CPLL_FBDIV_45 = 4, + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E, + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8, + parameter integer CPLL_REFCLK_DIV = 1, + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000, + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0, + parameter [1:0] DDI_CTRL = 2'b00, + parameter integer DDI_REALIGN_WAIT = 15, + parameter DEC_MCOMMA_DETECT = "TRUE", + parameter DEC_PCOMMA_DETECT = "TRUE", + parameter DEC_VALID_COMMA_ONLY = "TRUE", + parameter [0:0] DELAY_ELEC = 1'b0, + parameter [9:0] DMONITOR_CFG0 = 10'h000, + parameter [7:0] DMONITOR_CFG1 = 8'h00, + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0, + parameter [5:0] ES_CONTROL = 6'b000000, + parameter ES_ERRDET_EN = "FALSE", + parameter ES_EYE_SCAN_EN = "FALSE", + parameter [11:0] ES_HORZ_OFFSET = 12'h800, + parameter [4:0] ES_PRESCALE = 5'b00000, + parameter [15:0] ES_QUALIFIER0 = 16'h0000, + parameter [15:0] ES_QUALIFIER1 = 16'h0000, + parameter [15:0] ES_QUALIFIER2 = 16'h0000, + parameter [15:0] ES_QUALIFIER3 = 16'h0000, + parameter [15:0] ES_QUALIFIER4 = 16'h0000, + parameter [15:0] ES_QUALIFIER5 = 16'h0000, + parameter [15:0] ES_QUALIFIER6 = 16'h0000, + parameter [15:0] ES_QUALIFIER7 = 16'h0000, + parameter [15:0] ES_QUALIFIER8 = 16'h0000, + parameter [15:0] ES_QUALIFIER9 = 16'h0000, + parameter [15:0] ES_QUAL_MASK0 = 16'h0000, + parameter [15:0] ES_QUAL_MASK1 = 16'h0000, + parameter [15:0] ES_QUAL_MASK2 = 16'h0000, + parameter [15:0] ES_QUAL_MASK3 = 16'h0000, + parameter [15:0] ES_QUAL_MASK4 = 16'h0000, + parameter [15:0] ES_QUAL_MASK5 = 16'h0000, + parameter [15:0] ES_QUAL_MASK6 = 16'h0000, + parameter [15:0] ES_QUAL_MASK7 = 16'h0000, + parameter [15:0] ES_QUAL_MASK8 = 16'h0000, + parameter [15:0] ES_QUAL_MASK9 = 16'h0000, + parameter [15:0] ES_SDATA_MASK0 = 16'h0000, + parameter [15:0] ES_SDATA_MASK1 = 16'h0000, + parameter [15:0] ES_SDATA_MASK2 = 16'h0000, + parameter [15:0] ES_SDATA_MASK3 = 16'h0000, + parameter [15:0] ES_SDATA_MASK4 = 16'h0000, + parameter [15:0] ES_SDATA_MASK5 = 16'h0000, + parameter [15:0] ES_SDATA_MASK6 = 16'h0000, + parameter [15:0] ES_SDATA_MASK7 = 16'h0000, + parameter [15:0] ES_SDATA_MASK8 = 16'h0000, + parameter [15:0] ES_SDATA_MASK9 = 16'h0000, + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0, + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111, + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111, + parameter FTS_LANE_DESKEW_EN = "FALSE", + parameter [4:0] GEARBOX_MODE = 5'b00000, + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0, + parameter [0:0] LOCAL_MASTER = 1'b0, + parameter [2:0] LPBK_BIAS_CTRL = 3'b000, + parameter [0:0] LPBK_EN_RCAL_B = 1'b0, + parameter [3:0] LPBK_EXT_RCAL = 4'b0000, + parameter [2:0] LPBK_IND_CTRL0 = 3'b000, + parameter [2:0] LPBK_IND_CTRL1 = 3'b000, + parameter [2:0] LPBK_IND_CTRL2 = 3'b000, + parameter [3:0] LPBK_RG_CTRL = 4'b0000, + parameter [1:0] OOBDIVCTL = 2'b00, + parameter [0:0] OOB_PWRUP = 1'b0, + parameter PCI3_AUTO_REALIGN = "FRST_SMPL", + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1, + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00, + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0, + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000, + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000, + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000, + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0, + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0, + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000, + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000, + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000, + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100, + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000, + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000, + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0, + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0, + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0, + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000, + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000, + parameter PCS_PCIE_EN = "FALSE", + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000, + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C, + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19, + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64, + parameter integer PREIQ_FREQ_BST = 0, + parameter [2:0] PROCESS_PAR = 3'b010, + parameter [0:0] RATE_SW_USE_DRP = 1'b0, + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0, + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0, + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0, + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010, + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00, + parameter [4:0] RXBUFRESET_TIME = 5'b00001, + parameter RXBUF_ADDR_MODE = "FULL", + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000, + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000, + parameter RXBUF_EN = "TRUE", + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE", + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE", + parameter RXBUF_RESET_ON_EIDLE = "FALSE", + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE", + parameter integer RXBUF_THRESH_OVFLW = 0, + parameter RXBUF_THRESH_OVRD = "FALSE", + parameter integer RXBUF_THRESH_UNDFLW = 4, + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001, + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001, + parameter [15:0] RXCDR_CFG0 = 16'h0003, + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003, + parameter [15:0] RXCDR_CFG1 = 16'h0000, + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG2 = 16'h0164, + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164, + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034, + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034, + parameter [15:0] RXCDR_CFG3 = 16'h0024, + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024, + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024, + parameter [15:0] RXCDR_CFG4 = 16'h5CF6, + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6, + parameter [15:0] RXCDR_CFG5 = 16'hB46B, + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B, + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0, + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0, + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040, + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000, + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000, + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0, + parameter [15:0] RXCFOK_CFG0 = 16'h0000, + parameter [15:0] RXCFOK_CFG1 = 16'h0002, + parameter [15:0] RXCFOK_CFG2 = 16'h002D, + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000, + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111, + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000, + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022, + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100, + parameter [15:0] RXDFE_CFG0 = 16'h4000, + parameter [15:0] RXDFE_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003, + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002, + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG3 = 16'h0000, + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000, + parameter [15:0] RXDFE_OS_CFG1 = 16'h0002, + parameter [0:0] RXDFE_PWR_SAVING = 1'b0, + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000, + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002, + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000, + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000, + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022, + parameter [15:0] RXDLY_CFG = 16'h0010, + parameter [15:0] RXDLY_LCFG = 16'h0030, + parameter RXELECIDLE_CFG = "SIGCFG_4", + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter RXGEARBOX_EN = "FALSE", + parameter [4:0] RXISCANRESET_TIME = 5'b00001, + parameter [15:0] RXLPM_CFG = 16'h0000, + parameter [15:0] RXLPM_GC_CFG = 16'h1000, + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000, + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002, + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000, + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000, + parameter [8:0] RXOOB_CFG = 9'b000110000, + parameter RXOOB_CLK_CFG = "PMA", + parameter [4:0] RXOSCALRESET_TIME = 5'b00011, + parameter integer RXOUT_DIV = 4, + parameter [4:0] RXPCSRESET_TIME = 5'b00001, + parameter [15:0] RXPHBEACON_CFG = 16'h0000, + parameter [15:0] RXPHDLY_CFG = 16'h2020, + parameter [15:0] RXPHSAMP_CFG = 16'h2100, + parameter [15:0] RXPHSLIP_CFG = 16'h9933, + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000, + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0, + parameter [15:0] RXPI_CFG0 = 16'h0002, + parameter [15:0] RXPI_CFG1 = 16'b0000000000000000, + parameter [0:0] RXPI_LPM = 1'b0, + parameter [1:0] RXPI_SEL_LC = 2'b00, + parameter [1:0] RXPI_STARTCODE = 2'b00, + parameter [0:0] RXPI_VREFSEL = 1'b0, + parameter RXPMACLK_SEL = "DATA", + parameter [4:0] RXPMARESET_TIME = 5'b00001, + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0, + parameter integer RXPRBS_LINKACQ_CNT = 15, + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0, + parameter integer RXSLIDE_AUTO_WAIT = 7, + parameter RXSLIDE_MODE = "OFF", + parameter [0:0] RXSYNC_MULTILANE = 1'b0, + parameter [0:0] RXSYNC_OVRD = 1'b0, + parameter [0:0] RXSYNC_SKIP_DA = 1'b0, + parameter [0:0] RX_AFE_CM_EN = 1'b0, + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0, + parameter [5:0] RX_BUFFER_CFG = 6'b000000, + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0, + parameter integer RX_CLK25_DIV = 8, + parameter [0:0] RX_CLKMUX_EN = 1'b1, + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000, + parameter [3:0] RX_CM_BUF_CFG = 4'b1010, + parameter [0:0] RX_CM_BUF_PD = 1'b0, + parameter integer RX_CM_SEL = 3, + parameter integer RX_CM_TRIM = 12, + parameter [7:0] RX_CTLE3_LPF = 8'b00000000, + parameter integer RX_DATA_WIDTH = 20, + parameter [5:0] RX_DDI_SEL = 6'b000000, + parameter RX_DEFER_RESET_BUF_EN = "TRUE", + parameter [2:0] RX_DEGEN_CTRL = 3'b011, + parameter integer RX_DFELPM_CFG0 = 0, + parameter [0:0] RX_DFELPM_CFG1 = 1'b1, + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1, + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00, + parameter integer RX_DFE_AGC_CFG1 = 4, + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1, + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4, + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01, + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4, + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0, + parameter RX_DISPERR_SEQ_MATCH = "TRUE", + parameter [0:0] RX_DIV2_MODE_B = 1'b0, + parameter [4:0] RX_DIVRESET_TIME = 5'b00001, + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0, + parameter [0:0] RX_EN_HI_LR = 1'b1, + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000, + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000, + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0, + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00, + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0, + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0, + parameter integer RX_INT_DATAWIDTH = 1, + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0, + parameter [15:0] RX_PMA_RSV0 = 16'h0000, + parameter real RX_PROGDIV_CFG = 0.0, + parameter [15:0] RX_PROGDIV_RATE = 16'h0001, + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000, + parameter [0:0] RX_RESLOAD_OVRD = 1'b0, + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101, + parameter integer RX_SIG_VALID_DLY = 11, + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0, + parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001, + parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000, + parameter [3:0] RX_SUM_VCMTUNE = 4'b1010, + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0, + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100, + parameter [1:0] RX_TUNE_AFE_OS = 2'b00, + parameter [2:0] RX_VREG_CTRL = 3'b101, + parameter [0:0] RX_VREG_PDB = 1'b1, + parameter [1:0] RX_WIDEMODE_CDR = 2'b01, + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01, + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01, + parameter RX_XCLK_SEL = "RXDES", + parameter [0:0] RX_XMODE_SEL = 1'b0, + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0, + parameter [0:0] SAS_12G_MODE = 1'b0, + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111, + parameter [2:0] SATA_BURST_VAL = 3'b100, + parameter SATA_CPLL_CFG = "VCO_3000MHZ", + parameter [2:0] SATA_EIDLE_VAL = 3'b100, + parameter SHOW_REALIGN_COMMA = "TRUE", + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SIM_MODE = "FAST", + parameter SIM_RECEIVER_DETECT_PASS = "TRUE", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z", + parameter [0:0] SRSTMODE = 1'b0, + parameter [1:0] TAPDLY_SET_TX = 2'h0, + parameter [3:0] TEMPERATURE_PAR = 4'b0010, + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000, + parameter [2:0] TERM_RCAL_OVRD = 3'b000, + parameter [7:0] TRANS_TIME_RATE = 8'h0E, + parameter [7:0] TST_RSV0 = 8'h00, + parameter [7:0] TST_RSV1 = 8'h00, + parameter TXBUF_EN = "TRUE", + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE", + parameter [15:0] TXDLY_CFG = 16'h0010, + parameter [15:0] TXDLY_LCFG = 16'h0030, + parameter [3:0] TXDRVBIAS_N = 4'b1010, + parameter TXFIFO_ADDR_CFG = "LOW", + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter TXGEARBOX_EN = "FALSE", + parameter integer TXOUT_DIV = 4, + parameter [4:0] TXPCSRESET_TIME = 5'b00001, + parameter [15:0] TXPHDLY_CFG0 = 16'h6020, + parameter [15:0] TXPHDLY_CFG1 = 16'h0002, + parameter [15:0] TXPH_CFG = 16'h0123, + parameter [15:0] TXPH_CFG2 = 16'h0000, + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000, + parameter [15:0] TXPI_CFG = 16'h0000, + parameter [1:0] TXPI_CFG0 = 2'b00, + parameter [1:0] TXPI_CFG1 = 2'b00, + parameter [1:0] TXPI_CFG2 = 2'b00, + parameter [0:0] TXPI_CFG3 = 1'b0, + parameter [0:0] TXPI_CFG4 = 1'b1, + parameter [2:0] TXPI_CFG5 = 3'b000, + parameter [0:0] TXPI_GRAY_SEL = 1'b0, + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0, + parameter [0:0] TXPI_LPM = 1'b0, + parameter [0:0] TXPI_PPM = 1'b0, + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2", + parameter [7:0] TXPI_PPM_CFG = 8'b00000000, + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000, + parameter [0:0] TXPI_VREFSEL = 1'b0, + parameter [4:0] TXPMARESET_TIME = 5'b00001, + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0, + parameter [0:0] TXSYNC_MULTILANE = 1'b0, + parameter [0:0] TXSYNC_OVRD = 1'b0, + parameter [0:0] TXSYNC_SKIP_DA = 1'b0, + parameter integer TX_CLK25_DIV = 8, + parameter [0:0] TX_CLKMUX_EN = 1'b1, + parameter integer TX_DATA_WIDTH = 20, + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000, + parameter [5:0] TX_DEEMPH0 = 6'b000000, + parameter [5:0] TX_DEEMPH1 = 6'b000000, + parameter [5:0] TX_DEEMPH2 = 6'b000000, + parameter [5:0] TX_DEEMPH3 = 6'b000000, + parameter [4:0] TX_DIVRESET_TIME = 5'b00001, + parameter TX_DRIVE_MODE = "DIRECT", + parameter integer TX_DRVMUX_CTRL = 2, + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110, + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100, + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0, + parameter [0:0] TX_FIFO_BYP_EN = 1'b0, + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0, + parameter integer TX_INT_DATAWIDTH = 1, + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE", + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0, + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110, + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001, + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101, + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010, + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110, + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100, + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010, + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000, + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000, + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F, + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000, + parameter integer TX_PI_BIASSET = 0, + parameter [1:0] TX_PI_IBIAS_MID = 2'b00, + parameter [0:0] TX_PMADATA_OPT = 1'b0, + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0, + parameter [15:0] TX_PMA_RSV0 = 16'h0008, + parameter integer TX_PREDRV_CTRL = 2, + parameter TX_PROGCLK_SEL = "POSTPI", + parameter real TX_PROGDIV_CFG = 0.0, + parameter [15:0] TX_PROGDIV_RATE = 16'h0001, + parameter [0:0] TX_QPI_STATUS_EN = 1'b0, + parameter [13:0] TX_RXDETECT_CFG = 14'h0032, + parameter integer TX_RXDETECT_REF = 3, + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101, + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0, + parameter [1:0] TX_SW_MEAS = 2'b00, + parameter [2:0] TX_VREG_CTRL = 3'b000, + parameter [0:0] TX_VREG_PDB = 1'b0, + parameter [1:0] TX_VREG_VREFSEL = 2'b00, + parameter TX_XCLK_SEL = "TXOUT", + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0, + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111, + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011, + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0, + parameter [0:0] USB_EXT_CNTL = 1'b1, + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011, + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011, + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101, + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001, + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100, + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101, + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011, + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011, + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011, + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1, + parameter [0:0] USB_MODE = 1'b0, + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0, + parameter integer USB_PING_SATA_MAX_INIT = 21, + parameter integer USB_PING_SATA_MIN_INIT = 12, + parameter integer USB_POLL_SATA_MAX_BURST = 8, + parameter integer USB_POLL_SATA_MIN_BURST = 4, + parameter [0:0] USB_RAW_ELEC = 1'b0, + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1, + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1, + parameter integer USB_U1_SATA_MAX_WAKE = 7, + parameter integer USB_U1_SATA_MIN_WAKE = 4, + parameter integer USB_U2_SAS_MAX_COM = 64, + parameter integer USB_U2_SAS_MIN_COM = 36, + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0, + parameter [0:0] Y_ALL_MODE = 1'b0 +)( + output BUFGTCE, + output [2:0] BUFGTCEMASK, + output [8:0] BUFGTDIV, + output BUFGTRESET, + output [2:0] BUFGTRSTMASK, + output CPLLFBCLKLOST, + output CPLLLOCK, + output CPLLREFCLKLOST, + output [15:0] DMONITOROUT, + output DMONITOROUTCLK, + output [15:0] DRPDO, + output DRPRDY, + output EYESCANDATAERROR, + output GTHTXN, + output GTHTXP, + output GTPOWERGOOD, + output GTREFCLKMONITOR, + output PCIERATEGEN3, + output PCIERATEIDLE, + output [1:0] PCIERATEQPLLPD, + output [1:0] PCIERATEQPLLRESET, + output PCIESYNCTXSYNCDONE, + output PCIEUSERGEN3RDY, + output PCIEUSERPHYSTATUSRST, + output PCIEUSERRATESTART, + output [15:0] PCSRSVDOUT, + output PHYSTATUS, + output [15:0] PINRSRVDAS, + output POWERPRESENT, + output RESETEXCEPTION, + output [2:0] RXBUFSTATUS, + output RXBYTEISALIGNED, + output RXBYTEREALIGN, + output RXCDRLOCK, + output RXCDRPHDONE, + output RXCHANBONDSEQ, + output RXCHANISALIGNED, + output RXCHANREALIGN, + output [4:0] RXCHBONDO, + output RXCKCALDONE, + output [1:0] RXCLKCORCNT, + output RXCOMINITDET, + output RXCOMMADET, + output RXCOMSASDET, + output RXCOMWAKEDET, + output [15:0] RXCTRL0, + output [15:0] RXCTRL1, + output [7:0] RXCTRL2, + output [7:0] RXCTRL3, + output [127:0] RXDATA, + output [7:0] RXDATAEXTENDRSVD, + output [1:0] RXDATAVALID, + output RXDLYSRESETDONE, + output RXELECIDLE, + output [5:0] RXHEADER, + output [1:0] RXHEADERVALID, + output RXLFPSTRESETDET, + output RXLFPSU2LPEXITDET, + output RXLFPSU3WAKEDET, + output [7:0] RXMONITOROUT, + output RXOSINTDONE, + output RXOSINTSTARTED, + output RXOSINTSTROBEDONE, + output RXOSINTSTROBESTARTED, + output RXOUTCLK, + output RXOUTCLKFABRIC, + output RXOUTCLKPCS, + output RXPHALIGNDONE, + output RXPHALIGNERR, + output RXPMARESETDONE, + output RXPRBSERR, + output RXPRBSLOCKED, + output RXPRGDIVRESETDONE, + output RXQPISENN, + output RXQPISENP, + output RXRATEDONE, + output RXRECCLKOUT, + output RXRESETDONE, + output RXSLIDERDY, + output RXSLIPDONE, + output RXSLIPOUTCLKRDY, + output RXSLIPPMARDY, + output [1:0] RXSTARTOFSEQ, + output [2:0] RXSTATUS, + output RXSYNCDONE, + output RXSYNCOUT, + output RXVALID, + output [1:0] TXBUFSTATUS, + output TXCOMFINISH, + output TXDCCDONE, + output TXDLYSRESETDONE, + output TXOUTCLK, + output TXOUTCLKFABRIC, + output TXOUTCLKPCS, + output TXPHALIGNDONE, + output TXPHINITDONE, + output TXPMARESETDONE, + output TXPRGDIVRESETDONE, + output TXQPISENN, + output TXQPISENP, + output TXRATEDONE, + output TXRESETDONE, + output TXSYNCDONE, + output TXSYNCOUT, + + input CDRSTEPDIR, + input CDRSTEPSQ, + input CDRSTEPSX, + input CFGRESET, + input CLKRSVD0, + input CLKRSVD1, + input CPLLFREQLOCK, + input CPLLLOCKDETCLK, + input CPLLLOCKEN, + input CPLLPD, + input [2:0] CPLLREFCLKSEL, + input CPLLRESET, + input DMONFIFORESET, + input DMONITORCLK, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPRST, + input DRPWE, + input EYESCANRESET, + input EYESCANTRIGGER, + input FREQOS, + input GTGREFCLK, + input GTHRXN, + input GTHRXP, + input GTNORTHREFCLK0, + input GTNORTHREFCLK1, + input GTREFCLK0, + input GTREFCLK1, + input [15:0] GTRSVD, + input GTRXRESET, + input GTRXRESETSEL, + input GTSOUTHREFCLK0, + input GTSOUTHREFCLK1, + input GTTXRESET, + input GTTXRESETSEL, + input INCPCTRL, + input [2:0] LOOPBACK, + input PCIEEQRXEQADAPTDONE, + input PCIERSTIDLE, + input PCIERSTTXSYNCSTART, + input PCIEUSERRATEDONE, + input [15:0] PCSRSVDIN, + input QPLL0CLK, + input QPLL0FREQLOCK, + input QPLL0REFCLK, + input QPLL1CLK, + input QPLL1FREQLOCK, + input QPLL1REFCLK, + input RESETOVRD, + input RX8B10BEN, + input RXAFECFOKEN, + input RXBUFRESET, + input RXCDRFREQRESET, + input RXCDRHOLD, + input RXCDROVRDEN, + input RXCDRRESET, + input RXCHBONDEN, + input [4:0] RXCHBONDI, + input [2:0] RXCHBONDLEVEL, + input RXCHBONDMASTER, + input RXCHBONDSLAVE, + input RXCKCALRESET, + input [6:0] RXCKCALSTART, + input RXCOMMADETEN, + input [1:0] RXDFEAGCCTRL, + input RXDFEAGCHOLD, + input RXDFEAGCOVRDEN, + input [3:0] RXDFECFOKFCNUM, + input RXDFECFOKFEN, + input RXDFECFOKFPULSE, + input RXDFECFOKHOLD, + input RXDFECFOKOVREN, + input RXDFEKHHOLD, + input RXDFEKHOVRDEN, + input RXDFELFHOLD, + input RXDFELFOVRDEN, + input RXDFELPMRESET, + input RXDFETAP10HOLD, + input RXDFETAP10OVRDEN, + input RXDFETAP11HOLD, + input RXDFETAP11OVRDEN, + input RXDFETAP12HOLD, + input RXDFETAP12OVRDEN, + input RXDFETAP13HOLD, + input RXDFETAP13OVRDEN, + input RXDFETAP14HOLD, + input RXDFETAP14OVRDEN, + input RXDFETAP15HOLD, + input RXDFETAP15OVRDEN, + input RXDFETAP2HOLD, + input RXDFETAP2OVRDEN, + input RXDFETAP3HOLD, + input RXDFETAP3OVRDEN, + input RXDFETAP4HOLD, + input RXDFETAP4OVRDEN, + input RXDFETAP5HOLD, + input RXDFETAP5OVRDEN, + input RXDFETAP6HOLD, + input RXDFETAP6OVRDEN, + input RXDFETAP7HOLD, + input RXDFETAP7OVRDEN, + input RXDFETAP8HOLD, + input RXDFETAP8OVRDEN, + input RXDFETAP9HOLD, + input RXDFETAP9OVRDEN, + input RXDFEUTHOLD, + input RXDFEUTOVRDEN, + input RXDFEVPHOLD, + input RXDFEVPOVRDEN, + input RXDFEXYDEN, + input RXDLYBYPASS, + input RXDLYEN, + input RXDLYOVRDEN, + input RXDLYSRESET, + input [1:0] RXELECIDLEMODE, + input RXEQTRAINING, + input RXGEARBOXSLIP, + input RXLATCLK, + input RXLPMEN, + input RXLPMGCHOLD, + input RXLPMGCOVRDEN, + input RXLPMHFHOLD, + input RXLPMHFOVRDEN, + input RXLPMLFHOLD, + input RXLPMLFKLOVRDEN, + input RXLPMOSHOLD, + input RXLPMOSOVRDEN, + input RXMCOMMAALIGNEN, + input [1:0] RXMONITORSEL, + input RXOOBRESET, + input RXOSCALRESET, + input RXOSHOLD, + input RXOSOVRDEN, + input [2:0] RXOUTCLKSEL, + input RXPCOMMAALIGNEN, + input RXPCSRESET, + input [1:0] RXPD, + input RXPHALIGN, + input RXPHALIGNEN, + input RXPHDLYPD, + input RXPHDLYRESET, + input RXPHOVRDEN, + input [1:0] RXPLLCLKSEL, + input RXPMARESET, + input RXPOLARITY, + input RXPRBSCNTRESET, + input [3:0] RXPRBSSEL, + input RXPROGDIVRESET, + input RXQPIEN, + input [2:0] RXRATE, + input RXRATEMODE, + input RXSLIDE, + input RXSLIPOUTCLK, + input RXSLIPPMA, + input RXSYNCALLIN, + input RXSYNCIN, + input RXSYNCMODE, + input [1:0] RXSYSCLKSEL, + input RXTERMINATION, + input RXUSERRDY, + input RXUSRCLK, + input RXUSRCLK2, + input SIGVALIDCLK, + input [19:0] TSTIN, + input [7:0] TX8B10BBYPASS, + input TX8B10BEN, + input TXCOMINIT, + input TXCOMSAS, + input TXCOMWAKE, + input [15:0] TXCTRL0, + input [15:0] TXCTRL1, + input [7:0] TXCTRL2, + input [127:0] TXDATA, + input [7:0] TXDATAEXTENDRSVD, + input TXDCCFORCESTART, + input TXDCCRESET, + input [1:0] TXDEEMPH, + input TXDETECTRX, + input [4:0] TXDIFFCTRL, + input TXDLYBYPASS, + input TXDLYEN, + input TXDLYHOLD, + input TXDLYOVRDEN, + input TXDLYSRESET, + input TXDLYUPDOWN, + input TXELECIDLE, + input [5:0] TXHEADER, + input TXINHIBIT, + input TXLATCLK, + input TXLFPSTRESET, + input TXLFPSU2LPEXIT, + input TXLFPSU3WAKE, + input [6:0] TXMAINCURSOR, + input [2:0] TXMARGIN, + input TXMUXDCDEXHOLD, + input TXMUXDCDORWREN, + input TXONESZEROS, + input [2:0] TXOUTCLKSEL, + input TXPCSRESET, + input [1:0] TXPD, + input TXPDELECIDLEMODE, + input TXPHALIGN, + input TXPHALIGNEN, + input TXPHDLYPD, + input TXPHDLYRESET, + input TXPHDLYTSTCLK, + input TXPHINIT, + input TXPHOVRDEN, + input TXPIPPMEN, + input TXPIPPMOVRDEN, + input TXPIPPMPD, + input TXPIPPMSEL, + input [4:0] TXPIPPMSTEPSIZE, + input TXPISOPD, + input [1:0] TXPLLCLKSEL, + input TXPMARESET, + input TXPOLARITY, + input [4:0] TXPOSTCURSOR, + input TXPRBSFORCEERR, + input [3:0] TXPRBSSEL, + input [4:0] TXPRECURSOR, + input TXPROGDIVRESET, + input TXQPIBIASEN, + input TXQPIWEAKPUP, + input [2:0] TXRATE, + input TXRATEMODE, + input [6:0] TXSEQUENCE, + input TXSWING, + input TXSYNCALLIN, + input TXSYNCIN, + input TXSYNCMODE, + input [1:0] TXSYSCLKSEL, + input TXUSERRDY, + input TXUSRCLK, + input TXUSRCLK2 +); + +// define constants + localparam MODULE_NAME = "GTHE4_CHANNEL"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "GTHE4_CHANNEL_dr.v" +`else + reg [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE; + reg [0:0] ACJTAG_MODE_REG = ACJTAG_MODE; + reg [0:0] ACJTAG_RESET_REG = ACJTAG_RESET; + reg [15:0] ADAPT_CFG0_REG = ADAPT_CFG0; + reg [15:0] ADAPT_CFG1_REG = ADAPT_CFG1; + reg [15:0] ADAPT_CFG2_REG = ADAPT_CFG2; + reg [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE; + reg [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE; + reg [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD; + reg [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET; + reg [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE; + reg [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET; + reg [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE; + reg [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET; + reg [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET; + reg [0:0] A_RXTERMINATION_REG = A_RXTERMINATION; + reg [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL; + reg [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET; + reg [0:0] CAPBYPASS_FORCE_REG = CAPBYPASS_FORCE; + reg [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL; + reg [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN; + reg [0:0] CFOK_PWRSVE_EN_REG = CFOK_PWRSVE_EN; + reg [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN; + reg [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW; + reg [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1; + reg [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2; + reg [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3; + reg [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE; + reg [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1; + reg [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2; + reg [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3; + reg [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE; + reg [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE; + reg [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN; + reg [15:0] CH_HSPMUX_REG = CH_HSPMUX; + reg [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0; + reg [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1; + reg [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2; + reg [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3; + reg [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0; + reg [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1; + reg [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2; + reg [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3; + reg [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4; + reg [15:0] CKCAL_RSVD0_REG = CKCAL_RSVD0; + reg [15:0] CKCAL_RSVD1_REG = CKCAL_RSVD1; + reg [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE; + reg [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE; + reg [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT; + reg [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT; + reg [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE; + reg [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT; + reg [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1; + reg [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2; + reg [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3; + reg [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4; + reg [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE; + reg [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1; + reg [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2; + reg [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3; + reg [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4; + reg [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE; + reg [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE; + reg [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN; + reg [15:0] CPLL_CFG0_REG = CPLL_CFG0; + reg [15:0] CPLL_CFG1_REG = CPLL_CFG1; + reg [15:0] CPLL_CFG2_REG = CPLL_CFG2; + reg [15:0] CPLL_CFG3_REG = CPLL_CFG3; + reg [4:0] CPLL_FBDIV_REG = CPLL_FBDIV; + reg [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45; + reg [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0; + reg [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG; + reg [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV; + reg [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL; + reg [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN; + reg [1:0] DDI_CTRL_REG = DDI_CTRL; + reg [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT; + reg [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT; + reg [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT; + reg [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY; + reg [0:0] DELAY_ELEC_REG = DELAY_ELEC; + reg [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0; + reg [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1; + reg [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL; + reg [5:0] ES_CONTROL_REG = ES_CONTROL; + reg [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN; + reg [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN; + reg [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET; + reg [4:0] ES_PRESCALE_REG = ES_PRESCALE; + reg [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0; + reg [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1; + reg [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2; + reg [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3; + reg [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4; + reg [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5; + reg [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6; + reg [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7; + reg [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8; + reg [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9; + reg [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0; + reg [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1; + reg [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2; + reg [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3; + reg [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4; + reg [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5; + reg [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6; + reg [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7; + reg [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8; + reg [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9; + reg [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0; + reg [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1; + reg [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2; + reg [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3; + reg [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4; + reg [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5; + reg [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6; + reg [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7; + reg [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8; + reg [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9; + reg [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN; + reg [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE; + reg [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG; + reg [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN; + reg [4:0] GEARBOX_MODE_REG = GEARBOX_MODE; + reg [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2; + reg [0:0] LOCAL_MASTER_REG = LOCAL_MASTER; + reg [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL; + reg [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B; + reg [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL; + reg [2:0] LPBK_IND_CTRL0_REG = LPBK_IND_CTRL0; + reg [2:0] LPBK_IND_CTRL1_REG = LPBK_IND_CTRL1; + reg [2:0] LPBK_IND_CTRL2_REG = LPBK_IND_CTRL2; + reg [3:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL; + reg [1:0] OOBDIVCTL_REG = OOBDIVCTL; + reg [0:0] OOB_PWRUP_REG = OOB_PWRUP; + reg [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN; + reg [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE; + reg [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS; + reg [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE; + reg [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT; + reg [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE; + reg [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT; + reg [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE; + reg [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE; + reg [4:0] PCIE3_CLK_COR_EMPTY_THRSH_REG = PCIE3_CLK_COR_EMPTY_THRSH; + reg [5:0] PCIE3_CLK_COR_FULL_THRSH_REG = PCIE3_CLK_COR_FULL_THRSH; + reg [4:0] PCIE3_CLK_COR_MAX_LAT_REG = PCIE3_CLK_COR_MAX_LAT; + reg [4:0] PCIE3_CLK_COR_MIN_LAT_REG = PCIE3_CLK_COR_MIN_LAT; + reg [5:0] PCIE3_CLK_COR_THRSH_TIMER_REG = PCIE3_CLK_COR_THRSH_TIMER; + reg [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL; + reg [1:0] PCIE_PLL_SEL_MODE_GEN12_REG = PCIE_PLL_SEL_MODE_GEN12; + reg [1:0] PCIE_PLL_SEL_MODE_GEN3_REG = PCIE_PLL_SEL_MODE_GEN3; + reg [1:0] PCIE_PLL_SEL_MODE_GEN4_REG = PCIE_PLL_SEL_MODE_GEN4; + reg [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3; + reg [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG; + reg [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3; + reg [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG; + reg [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN; + reg [15:0] PCS_RSVD0_REG = PCS_RSVD0; + reg [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2; + reg [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2; + reg [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2; + reg [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST; + reg [2:0] PROCESS_PAR_REG = PROCESS_PAR; + reg [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP; + reg [0:0] RCLK_SIPO_DLY_ENB_REG = RCLK_SIPO_DLY_ENB; + reg [0:0] RCLK_SIPO_INV_EN_REG = RCLK_SIPO_INV_EN; + reg [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE; + reg [2:0] RTX_BUF_CML_CTRL_REG = RTX_BUF_CML_CTRL; + reg [1:0] RTX_BUF_TERM_CTRL_REG = RTX_BUF_TERM_CTRL; + reg [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME; + reg [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE; + reg [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT; + reg [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT; + reg [40:1] RXBUF_EN_REG = RXBUF_EN; + reg [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE; + reg [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN; + reg [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE; + reg [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE; + reg [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW; + reg [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD; + reg [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW; + reg [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME; + reg [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME; + reg [15:0] RXCDR_CFG0_REG = RXCDR_CFG0; + reg [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3; + reg [15:0] RXCDR_CFG1_REG = RXCDR_CFG1; + reg [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3; + reg [15:0] RXCDR_CFG2_REG = RXCDR_CFG2; + reg [9:0] RXCDR_CFG2_GEN2_REG = RXCDR_CFG2_GEN2; + reg [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3; + reg [15:0] RXCDR_CFG2_GEN4_REG = RXCDR_CFG2_GEN4; + reg [15:0] RXCDR_CFG3_REG = RXCDR_CFG3; + reg [5:0] RXCDR_CFG3_GEN2_REG = RXCDR_CFG3_GEN2; + reg [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3; + reg [15:0] RXCDR_CFG3_GEN4_REG = RXCDR_CFG3_GEN4; + reg [15:0] RXCDR_CFG4_REG = RXCDR_CFG4; + reg [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3; + reg [15:0] RXCDR_CFG5_REG = RXCDR_CFG5; + reg [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3; + reg [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE; + reg [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE; + reg [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0; + reg [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1; + reg [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2; + reg [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3; + reg [15:0] RXCDR_LOCK_CFG4_REG = RXCDR_LOCK_CFG4; + reg [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE; + reg [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0; + reg [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1; + reg [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2; + reg [15:0] RXCKCAL1_IQ_LOOP_RST_CFG_REG = RXCKCAL1_IQ_LOOP_RST_CFG; + reg [15:0] RXCKCAL1_I_LOOP_RST_CFG_REG = RXCKCAL1_I_LOOP_RST_CFG; + reg [15:0] RXCKCAL1_Q_LOOP_RST_CFG_REG = RXCKCAL1_Q_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_DX_LOOP_RST_CFG_REG = RXCKCAL2_DX_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_D_LOOP_RST_CFG_REG = RXCKCAL2_D_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_S_LOOP_RST_CFG_REG = RXCKCAL2_S_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_X_LOOP_RST_CFG_REG = RXCKCAL2_X_LOOP_RST_CFG; + reg [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME; + reg [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0; + reg [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1; + reg [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2; + reg [15:0] RXDFE_CFG0_REG = RXDFE_CFG0; + reg [15:0] RXDFE_CFG1_REG = RXDFE_CFG1; + reg [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0; + reg [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1; + reg [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2; + reg [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0; + reg [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1; + reg [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0; + reg [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1; + reg [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0; + reg [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1; + reg [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0; + reg [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1; + reg [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0; + reg [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1; + reg [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0; + reg [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1; + reg [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0; + reg [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1; + reg [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0; + reg [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1; + reg [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0; + reg [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1; + reg [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0; + reg [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1; + reg [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0; + reg [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1; + reg [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0; + reg [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1; + reg [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0; + reg [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1; + reg [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0; + reg [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1; + reg [15:0] RXDFE_KH_CFG0_REG = RXDFE_KH_CFG0; + reg [15:0] RXDFE_KH_CFG1_REG = RXDFE_KH_CFG1; + reg [15:0] RXDFE_KH_CFG2_REG = RXDFE_KH_CFG2; + reg [15:0] RXDFE_KH_CFG3_REG = RXDFE_KH_CFG3; + reg [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0; + reg [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1; + reg [0:0] RXDFE_PWR_SAVING_REG = RXDFE_PWR_SAVING; + reg [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0; + reg [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1; + reg [15:0] RXDFE_UT_CFG2_REG = RXDFE_UT_CFG2; + reg [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0; + reg [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1; + reg [15:0] RXDLY_CFG_REG = RXDLY_CFG; + reg [15:0] RXDLY_LCFG_REG = RXDLY_LCFG; + reg [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG; + reg [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR; + reg [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN; + reg [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME; + reg [15:0] RXLPM_CFG_REG = RXLPM_CFG; + reg [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG; + reg [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0; + reg [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1; + reg [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0; + reg [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1; + reg [8:0] RXOOB_CFG_REG = RXOOB_CFG; + reg [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG; + reg [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME; + reg [4:0] RXOUT_DIV_REG = RXOUT_DIV; + reg [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME; + reg [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG; + reg [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG; + reg [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG; + reg [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG; + reg [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL; + reg [0:0] RXPI_AUTO_BW_SEL_BYPASS_REG = RXPI_AUTO_BW_SEL_BYPASS; + reg [15:0] RXPI_CFG0_REG = RXPI_CFG0; + reg [15:0] RXPI_CFG1_REG = RXPI_CFG1; + reg [0:0] RXPI_LPM_REG = RXPI_LPM; + reg [1:0] RXPI_SEL_LC_REG = RXPI_SEL_LC; + reg [1:0] RXPI_STARTCODE_REG = RXPI_STARTCODE; + reg [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL; + reg [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL; + reg [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME; + reg [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK; + reg [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT; + reg [0:0] RXREFCLKDIV2_SEL_REG = RXREFCLKDIV2_SEL; + reg [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT; + reg [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE; + reg [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE; + reg [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD; + reg [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA; + reg [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN; + reg [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0; + reg [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG; + reg [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB; + reg [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV; + reg [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN; + reg [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD; + reg [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG; + reg [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD; + reg [1:0] RX_CM_SEL_REG = RX_CM_SEL; + reg [3:0] RX_CM_TRIM_REG = RX_CM_TRIM; + reg [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF; + reg [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH; + reg [5:0] RX_DDI_SEL_REG = RX_DDI_SEL; + reg [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN; + reg [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL; + reg [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0; + reg [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1; + reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN; + reg [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0; + reg [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1; + reg [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0; + reg [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1; + reg [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0; + reg [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1; + reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE; + reg [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH; + reg [0:0] RX_DIV2_MODE_B_REG = RX_DIV2_MODE_B; + reg [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME; + reg [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B; + reg [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR; + reg [8:0] RX_EXT_RL_CTRL_REG = RX_EXT_RL_CTRL; + reg [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE; + reg [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR; + reg [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE; + reg [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN; + reg [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP; + reg [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH; + reg [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE; + reg [15:0] RX_PMA_RSV0_REG = RX_PMA_RSV0; + real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG; + reg [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE; + reg [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL; + reg [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD; + reg [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD; + reg [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY; + reg [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN; + reg [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE; + reg [3:0] RX_SUM_RESLOAD_CTRL_REG = RX_SUM_RESLOAD_CTRL; + reg [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE; + reg [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR; + reg [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE; + reg [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS; + reg [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL; + reg [0:0] RX_VREG_PDB_REG = RX_VREG_PDB; + reg [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR; + reg [1:0] RX_WIDEMODE_CDR_GEN3_REG = RX_WIDEMODE_CDR_GEN3; + reg [1:0] RX_WIDEMODE_CDR_GEN4_REG = RX_WIDEMODE_CDR_GEN4; + reg [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL; + reg [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL; + reg [0:0] SAMPLE_CLK_PHASE_REG = SAMPLE_CLK_PHASE; + reg [0:0] SAS_12G_MODE_REG = SAS_12G_MODE; + reg [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN; + reg [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL; + reg [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG; + reg [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL; + reg [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA; + reg [160:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [48:1] SIM_MODE_REG = SIM_MODE; + reg [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS; + reg [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + reg [32:1] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL; + reg [0:0] SRSTMODE_REG = SRSTMODE; + reg [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX; + reg [3:0] TEMPERATURE_PAR_REG = TEMPERATURE_PAR; + reg [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG; + reg [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD; + reg [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE; + reg [7:0] TST_RSV0_REG = TST_RSV0; + reg [7:0] TST_RSV1_REG = TST_RSV1; + reg [40:1] TXBUF_EN_REG = TXBUF_EN; + reg [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE; + reg [15:0] TXDLY_CFG_REG = TXDLY_CFG; + reg [15:0] TXDLY_LCFG_REG = TXDLY_LCFG; + reg [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N; + reg [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG; + reg [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR; + reg [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN; + reg [4:0] TXOUT_DIV_REG = TXOUT_DIV; + reg [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME; + reg [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0; + reg [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1; + reg [15:0] TXPH_CFG_REG = TXPH_CFG; + reg [15:0] TXPH_CFG2_REG = TXPH_CFG2; + reg [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL; + reg [15:0] TXPI_CFG_REG = TXPI_CFG; + reg [1:0] TXPI_CFG0_REG = TXPI_CFG0; + reg [1:0] TXPI_CFG1_REG = TXPI_CFG1; + reg [1:0] TXPI_CFG2_REG = TXPI_CFG2; + reg [0:0] TXPI_CFG3_REG = TXPI_CFG3; + reg [0:0] TXPI_CFG4_REG = TXPI_CFG4; + reg [2:0] TXPI_CFG5_REG = TXPI_CFG5; + reg [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL; + reg [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL; + reg [0:0] TXPI_LPM_REG = TXPI_LPM; + reg [0:0] TXPI_PPM_REG = TXPI_PPM; + reg [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL; + reg [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG; + reg [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM; + reg [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL; + reg [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME; + reg [0:0] TXREFCLKDIV2_SEL_REG = TXREFCLKDIV2_SEL; + reg [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE; + reg [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD; + reg [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA; + reg [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV; + reg [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN; + reg [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH; + reg [15:0] TX_DCC_LOOP_RST_CFG_REG = TX_DCC_LOOP_RST_CFG; + reg [5:0] TX_DEEMPH0_REG = TX_DEEMPH0; + reg [5:0] TX_DEEMPH1_REG = TX_DEEMPH1; + reg [5:0] TX_DEEMPH2_REG = TX_DEEMPH2; + reg [5:0] TX_DEEMPH3_REG = TX_DEEMPH3; + reg [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME; + reg [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE; + reg [1:0] TX_DRVMUX_CTRL_REG = TX_DRVMUX_CTRL; + reg [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY; + reg [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY; + reg [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP; + reg [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN; + reg [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO; + reg [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH; + reg [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ; + reg [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL; + reg [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0; + reg [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1; + reg [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2; + reg [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3; + reg [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4; + reg [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0; + reg [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1; + reg [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2; + reg [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3; + reg [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4; + reg [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0; + reg [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1; + reg [15:0] TX_PHICAL_CFG2_REG = TX_PHICAL_CFG2; + reg [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET; + reg [1:0] TX_PI_IBIAS_MID_REG = TX_PI_IBIAS_MID; + reg [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT; + reg [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE; + reg [15:0] TX_PMA_RSV0_REG = TX_PMA_RSV0; + reg [1:0] TX_PREDRV_CTRL_REG = TX_PREDRV_CTRL; + reg [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL; + real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG; + reg [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE; + reg [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN; + reg [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG; + reg [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF; + reg [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD; + reg [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB; + reg [1:0] TX_SW_MEAS_REG = TX_SW_MEAS; + reg [2:0] TX_VREG_CTRL_REG = TX_VREG_CTRL; + reg [0:0] TX_VREG_PDB_REG = TX_VREG_PDB; + reg [1:0] TX_VREG_VREFSEL_REG = TX_VREG_VREFSEL; + reg [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL; + reg [0:0] USB_BOTH_BURST_IDLE_REG = USB_BOTH_BURST_IDLE; + reg [6:0] USB_BURSTMAX_U3WAKE_REG = USB_BURSTMAX_U3WAKE; + reg [6:0] USB_BURSTMIN_U3WAKE_REG = USB_BURSTMIN_U3WAKE; + reg [0:0] USB_CLK_COR_EQ_EN_REG = USB_CLK_COR_EQ_EN; + reg [0:0] USB_EXT_CNTL_REG = USB_EXT_CNTL; + reg [9:0] USB_IDLEMAX_POLLING_REG = USB_IDLEMAX_POLLING; + reg [9:0] USB_IDLEMIN_POLLING_REG = USB_IDLEMIN_POLLING; + reg [8:0] USB_LFPSPING_BURST_REG = USB_LFPSPING_BURST; + reg [8:0] USB_LFPSPOLLING_BURST_REG = USB_LFPSPOLLING_BURST; + reg [8:0] USB_LFPSPOLLING_IDLE_MS_REG = USB_LFPSPOLLING_IDLE_MS; + reg [8:0] USB_LFPSU1EXIT_BURST_REG = USB_LFPSU1EXIT_BURST; + reg [8:0] USB_LFPSU2LPEXIT_BURST_MS_REG = USB_LFPSU2LPEXIT_BURST_MS; + reg [8:0] USB_LFPSU3WAKE_BURST_MS_REG = USB_LFPSU3WAKE_BURST_MS; + reg [3:0] USB_LFPS_TPERIOD_REG = USB_LFPS_TPERIOD; + reg [0:0] USB_LFPS_TPERIOD_ACCURATE_REG = USB_LFPS_TPERIOD_ACCURATE; + reg [0:0] USB_MODE_REG = USB_MODE; + reg [0:0] USB_PCIE_ERR_REP_DIS_REG = USB_PCIE_ERR_REP_DIS; + reg [5:0] USB_PING_SATA_MAX_INIT_REG = USB_PING_SATA_MAX_INIT; + reg [5:0] USB_PING_SATA_MIN_INIT_REG = USB_PING_SATA_MIN_INIT; + reg [5:0] USB_POLL_SATA_MAX_BURST_REG = USB_POLL_SATA_MAX_BURST; + reg [5:0] USB_POLL_SATA_MIN_BURST_REG = USB_POLL_SATA_MIN_BURST; + reg [0:0] USB_RAW_ELEC_REG = USB_RAW_ELEC; + reg [0:0] USB_RXIDLE_P0_CTRL_REG = USB_RXIDLE_P0_CTRL; + reg [0:0] USB_TXIDLE_TUNE_ENABLE_REG = USB_TXIDLE_TUNE_ENABLE; + reg [5:0] USB_U1_SATA_MAX_WAKE_REG = USB_U1_SATA_MAX_WAKE; + reg [5:0] USB_U1_SATA_MIN_WAKE_REG = USB_U1_SATA_MIN_WAKE; + reg [6:0] USB_U2_SAS_MAX_COM_REG = USB_U2_SAS_MAX_COM; + reg [5:0] USB_U2_SAS_MIN_COM_REG = USB_U2_SAS_MIN_COM; + reg [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL; + reg [0:0] Y_ALL_MODE_REG = Y_ALL_MODE; +`endif + + reg [0:0] AEN_CDRSTEPSEL_REG = 1'b0; + reg [0:0] AEN_CPLL_REG = 1'b0; + reg [0:0] AEN_LOOPBACK_REG = 1'b0; + reg [0:0] AEN_MASTER_REG = 1'b0; + reg [0:0] AEN_PD_AND_EIDLE_REG = 1'b0; + reg [0:0] AEN_POLARITY_REG = 1'b0; + reg [0:0] AEN_PRBS_REG = 1'b0; + reg [0:0] AEN_QPI_REG = 1'b0; + reg [0:0] AEN_RESET_REG = 1'b0; + reg [0:0] AEN_RXCDR_REG = 1'b0; + reg [0:0] AEN_RXDFE_REG = 1'b0; + reg [0:0] AEN_RXDFELPM_REG = 1'b0; + reg [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0; + reg [0:0] AEN_RXPHDLY_REG = 1'b0; + reg [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0; + reg [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXMUXDCD_REG = 1'b0; + reg [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXPHDLY_REG = 1'b0; + reg [0:0] AEN_TXPI_PPM_REG = 1'b0; + reg [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0; + reg [15:0] AMONITOR_CFG_REG = 16'h0000; + reg [0:0] A_CPLLLOCKEN_REG = 1'b0; + reg [0:0] A_CPLLPD_REG = 1'b0; + reg [0:0] A_CPLLRESET_REG = 1'b0; + reg [0:0] A_EYESCANRESET_REG = 1'b0; + reg [0:0] A_GTRESETSEL_REG = 1'b0; + reg [0:0] A_GTRXRESET_REG = 1'b0; + reg [0:0] A_GTTXRESET_REG = 1'b0; + reg [80:1] A_LOOPBACK_REG = "NOLOOPBACK"; + reg [0:0] A_RXAFECFOKEN_REG = 1'b1; + reg [0:0] A_RXBUFRESET_REG = 1'b0; + reg [0:0] A_RXCDRFREQRESET_REG = 1'b0; + reg [0:0] A_RXCDRHOLD_REG = 1'b0; + reg [0:0] A_RXCDROVRDEN_REG = 1'b0; + reg [0:0] A_RXCDRRESET_REG = 1'b0; + reg [0:0] A_RXCKCALRESET_REG = 1'b0; + reg [1:0] A_RXDFEAGCCTRL_REG = 2'b01; + reg [0:0] A_RXDFEAGCHOLD_REG = 1'b0; + reg [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0; + reg [3:0] A_RXDFECFOKFCNUM_REG = 4'b0000; + reg [0:0] A_RXDFECFOKFEN_REG = 1'b0; + reg [0:0] A_RXDFECFOKFPULSE_REG = 1'b0; + reg [0:0] A_RXDFECFOKHOLD_REG = 1'b0; + reg [0:0] A_RXDFECFOKOVREN_REG = 1'b0; + reg [0:0] A_RXDFEKHHOLD_REG = 0; + reg [0:0] A_RXDFEKHOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFELFHOLD_REG = 1'b0; + reg [0:0] A_RXDFELFOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFELPMRESET_REG = 1'b0; + reg [0:0] A_RXDFETAP10HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP11HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP12HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP13HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP14HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP15HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP2HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP3HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP4HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP5HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP6HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP7HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP8HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP9HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEUTHOLD_REG = 1'b0; + reg [0:0] A_RXDFEUTOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEVPHOLD_REG = 1'b0; + reg [0:0] A_RXDFEVPOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEXYDEN_REG = 1'b0; + reg [0:0] A_RXDLYBYPASS_REG = 1'b0; + reg [0:0] A_RXDLYEN_REG = 1'b0; + reg [0:0] A_RXDLYOVRDEN_REG = 1'b0; + reg [0:0] A_RXDLYSRESET_REG = 1'b0; + reg [0:0] A_RXLPMEN_REG = 1'b0; + reg [0:0] A_RXLPMGCHOLD_REG = 1'b0; + reg [0:0] A_RXLPMGCOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMHFHOLD_REG = 1'b0; + reg [0:0] A_RXLPMHFOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMLFHOLD_REG = 1'b0; + reg [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMOSHOLD_REG = 1'b0; + reg [0:0] A_RXLPMOSOVRDEN_REG = 1'b0; + reg [1:0] A_RXMONITORSEL_REG = 2'b00; + reg [0:0] A_RXOOBRESET_REG = 1'b0; + reg [0:0] A_RXOSHOLD_REG = 1'b0; + reg [0:0] A_RXOSOVRDEN_REG = 1'b0; + reg [128:1] A_RXOUTCLKSEL_REG = "DISABLED"; + reg [0:0] A_RXPCSRESET_REG = 1'b0; + reg [24:1] A_RXPD_REG = "P0"; + reg [0:0] A_RXPHALIGN_REG = 1'b0; + reg [0:0] A_RXPHALIGNEN_REG = 1'b0; + reg [0:0] A_RXPHDLYPD_REG = 1'b0; + reg [0:0] A_RXPHDLYRESET_REG = 1'b0; + reg [0:0] A_RXPHOVRDEN_REG = 1'b0; + reg [64:1] A_RXPLLCLKSEL_REG = "QPLLCLK1"; + reg [0:0] A_RXPMARESET_REG = 1'b0; + reg [0:0] A_RXPOLARITY_REG = 1'b0; + reg [0:0] A_RXPRBSCNTRESET_REG = 1'b0; + reg [48:1] A_RXPRBSSEL_REG = "PRBS7"; + reg [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK"; + reg [2:0] A_TXBUFDIFFCTRL_REG = 3'b100; + reg [0:0] A_TXDCCRESET_REG = 1'b0; + reg [1:0] A_TXDEEMPH_REG = 2'b00; + reg [0:0] A_TXDLYBYPASS_REG = 1'b0; + reg [0:0] A_TXDLYEN_REG = 1'b0; + reg [0:0] A_TXDLYOVRDEN_REG = 1'b0; + reg [0:0] A_TXDLYSRESET_REG = 1'b0; + reg [0:0] A_TXELECIDLE_REG = 1'b0; + reg [0:0] A_TXINHIBIT_REG = 1'b0; + reg [6:0] A_TXMAINCURSOR_REG = 7'b0000000; + reg [2:0] A_TXMARGIN_REG = 3'b000; + reg [0:0] A_TXMUXDCDEXHOLD_REG = 1'b0; + reg [0:0] A_TXMUXDCDORWREN_REG = 1'b0; + reg [128:1] A_TXOUTCLKSEL_REG = "DISABLED"; + reg [0:0] A_TXPCSRESET_REG = 1'b0; + reg [24:1] A_TXPD_REG = "P0"; + reg [0:0] A_TXPHALIGN_REG = 1'b0; + reg [0:0] A_TXPHALIGNEN_REG = 1'b0; + reg [0:0] A_TXPHDLYPD_REG = 1'b0; + reg [0:0] A_TXPHDLYRESET_REG = 1'b0; + reg [0:0] A_TXPHINIT_REG = 1'b0; + reg [0:0] A_TXPHOVRDEN_REG = 1'b0; + reg [0:0] A_TXPIPPMOVRDEN_REG = 1'b0; + reg [0:0] A_TXPIPPMPD_REG = 1'b0; + reg [0:0] A_TXPIPPMSEL_REG = 1'b0; + reg [64:1] A_TXPLLCLKSEL_REG = "QPLLCLK1"; + reg [0:0] A_TXPMARESET_REG = 1'b0; + reg [0:0] A_TXPOLARITY_REG = 1'b0; + reg [4:0] A_TXPOSTCURSOR_REG = 5'b00000; + reg [0:0] A_TXPRBSFORCEERR_REG = 1'b0; + reg [96:1] A_TXPRBSSEL_REG = "PRBS7"; + reg [4:0] A_TXPRECURSOR_REG = 5'b00000; + reg [0:0] A_TXQPIBIASEN_REG = 1'b0; + reg [0:0] A_TXRESETSEL_REG = 1'b0; + reg [0:0] A_TXSWING_REG = 1'b0; + reg [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK"; + reg [1:0] BSR_ENABLE_REG = 2'b00; + reg [0:0] COEREG_CLKCTRL_REG = 1'b0; + reg [15:0] CSSD_CLK_MASK0_REG = 16'b0000000000000000; + reg [15:0] CSSD_CLK_MASK1_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG0_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG1_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG10_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG2_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG3_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG4_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG5_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG6_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG7_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG8_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG9_REG = 16'b0000000000000000; + reg [40:1] GEN_RXUSRCLK_REG = "TRUE"; + reg [40:1] GEN_TXUSRCLK_REG = "TRUE"; + reg [0:0] GT_INSTANTIATED_REG = 1'b1; + reg [15:0] INT_MASK_CFG0_REG = 16'b0000000000000000; + reg [15:0] INT_MASK_CFG1_REG = 16'b0000000000000000; + reg [5:0] RX_DFECFOKFCDAC_REG = 6'b000000; + reg [0:0] TXOUTCLKPCS_SEL_REG = 1'b0; + reg [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100; + reg [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101; + reg [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011; + reg [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010; + reg [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100; + reg [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101; + reg [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011; + reg [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010; + +`ifdef XIL_XECLIB + wire [63:0] RX_PROGDIV_CFG_BIN; + wire [63:0] TX_PROGDIV_CFG_BIN; +`else + reg [63:0] RX_PROGDIV_CFG_BIN; + reg [63:0] TX_PROGDIV_CFG_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire BUFGTCE_out; + wire BUFGTRESET_out; + wire CPLLFBCLKLOST_out; + wire CPLLLOCK_out; + wire CPLLREFCLKLOST_out; + wire CSSDSTOPCLKDONE_out; + wire DMONITOROUTCLK_out; + wire DRPRDY_out; + wire EYESCANDATAERROR_out; + wire GTHTXN_out; + wire GTHTXP_out; + wire GTPOWERGOOD_out; + wire GTREFCLKMONITOR_out; + wire PCIERATEGEN3_out; + wire PCIERATEIDLE_out; + wire PCIESYNCTXSYNCDONE_out; + wire PCIEUSERGEN3RDY_out; + wire PCIEUSERPHYSTATUSRST_out; + wire PCIEUSERRATESTART_out; + wire PHYSTATUS_out; + wire POWERPRESENT_out; + wire RESETEXCEPTION_out; + wire RXBYTEISALIGNED_out; + wire RXBYTEREALIGN_out; + wire RXCDRLOCK_out; + wire RXCDRPHDONE_out; + wire RXCHANBONDSEQ_out; + wire RXCHANISALIGNED_out; + wire RXCHANREALIGN_out; + wire RXCKCALDONE_out; + wire RXCOMINITDET_out; + wire RXCOMMADET_out; + wire RXCOMSASDET_out; + wire RXCOMWAKEDET_out; + wire RXDLYSRESETDONE_out; + wire RXELECIDLE_out; + wire RXLFPSTRESETDET_out; + wire RXLFPSU2LPEXITDET_out; + wire RXLFPSU3WAKEDET_out; + wire RXOSINTDONE_out; + wire RXOSINTSTARTED_out; + wire RXOSINTSTROBEDONE_out; + wire RXOSINTSTROBESTARTED_out; + wire RXOUTCLKFABRIC_out; + wire RXOUTCLKPCS_out; + wire RXOUTCLK_out; + wire RXPHALIGNDONE_out; + wire RXPHALIGNERR_out; + wire RXPMARESETDONE_out; + wire RXPRBSERR_out; + wire RXPRBSLOCKED_out; + wire RXPRGDIVRESETDONE_out; + wire RXQPISENN_out; + wire RXQPISENP_out; + wire RXRATEDONE_out; + wire RXRECCLKOUT_out; + wire RXRESETDONE_out; + wire RXSLIDERDY_out; + wire RXSLIPDONE_out; + wire RXSLIPOUTCLKRDY_out; + wire RXSLIPPMARDY_out; + wire RXSYNCDONE_out; + wire RXSYNCOUT_out; + wire RXVALID_out; + wire TXCOMFINISH_out; + wire TXDCCDONE_out; + wire TXDLYSRESETDONE_out; + wire TXOUTCLKFABRIC_out; + wire TXOUTCLKPCS_out; + wire TXOUTCLK_out; + wire TXPHALIGNDONE_out; + wire TXPHINITDONE_out; + wire TXPMARESETDONE_out; + wire TXPRGDIVRESETDONE_out; + wire TXQPISENN_out; + wire TXQPISENP_out; + wire TXRATEDONE_out; + wire TXRESETDONE_out; + wire TXSYNCDONE_out; + wire TXSYNCOUT_out; + wire [127:0] RXDATA_out; + wire [15:0] DMONITOROUT_out; + wire [15:0] DRPDO_out; + wire [15:0] PCSRSVDOUT_out; + wire [15:0] PINRSRVDAS_out; + wire [15:0] RXCTRL0_out; + wire [15:0] RXCTRL1_out; + wire [17:0] PMASCANOUT_out; + wire [18:0] SCANOUT_out; + wire [1:0] PCIERATEQPLLPD_out; + wire [1:0] PCIERATEQPLLRESET_out; + wire [1:0] RXCLKCORCNT_out; + wire [1:0] RXDATAVALID_out; + wire [1:0] RXHEADERVALID_out; + wire [1:0] RXSTARTOFSEQ_out; + wire [1:0] TXBUFSTATUS_out; + wire [2:0] BUFGTCEMASK_out; + wire [2:0] BUFGTRSTMASK_out; + wire [2:0] RXBUFSTATUS_out; + wire [2:0] RXSTATUS_out; + wire [4:0] RXCHBONDO_out; + wire [5:0] RXHEADER_out; + wire [7:0] RXCTRL2_out; + wire [7:0] RXCTRL3_out; + wire [7:0] RXDATAEXTENDRSVD_out; + wire [7:0] RXMONITOROUT_out; + wire [8:0] BUFGTDIV_out; + + wire BSR_SERIAL_in; + wire CDRSTEPDIR_in; + wire CDRSTEPSQ_in; + wire CDRSTEPSX_in; + wire CFGRESET_in; + wire CLKRSVD0_in; + wire CLKRSVD1_in; + wire CPLLFREQLOCK_in; + wire CPLLLOCKDETCLK_in; + wire CPLLLOCKEN_in; + wire CPLLPD_in; + wire CPLLRESET_in; + wire CSSDRSTB_in; + wire CSSDSTOPCLK_in; + wire DMONFIFORESET_in; + wire DMONITORCLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPRST_in; + wire DRPWE_in; + wire EYESCANRESET_in; + wire EYESCANTRIGGER_in; + wire FREQOS_in; + wire GTGREFCLK_in; + wire GTHRXN_in; + wire GTHRXP_in; + wire GTNORTHREFCLK0_in; + wire GTNORTHREFCLK1_in; + wire GTREFCLK0_in; + wire GTREFCLK1_in; + wire GTRXRESETSEL_in; + wire GTRXRESET_in; + wire GTSOUTHREFCLK0_in; + wire GTSOUTHREFCLK1_in; + wire GTTXRESETSEL_in; + wire GTTXRESET_in; + wire INCPCTRL_in; + wire PCIEEQRXEQADAPTDONE_in; + wire PCIERSTIDLE_in; + wire PCIERSTTXSYNCSTART_in; + wire PCIEUSERRATEDONE_in; + wire PMASCANCLK0_in; + wire PMASCANCLK1_in; + wire PMASCANCLK2_in; + wire PMASCANCLK3_in; + wire PMASCANCLK4_in; + wire PMASCANCLK5_in; + wire PMASCANCLK6_in; + wire PMASCANCLK7_in; + wire PMASCANCLK8_in; + wire PMASCANENB_in; + wire PMASCANMODEB_in; + wire PMASCANRSTEN_in; + wire QPLL0CLK_in; + wire QPLL0FREQLOCK_in; + wire QPLL0REFCLK_in; + wire QPLL1CLK_in; + wire QPLL1FREQLOCK_in; + wire QPLL1REFCLK_in; + wire RESETOVRD_in; + wire RX8B10BEN_in; + wire RXAFECFOKEN_in; + wire RXBUFRESET_in; + wire RXCDRFREQRESET_in; + wire RXCDRHOLD_in; + wire RXCDROVRDEN_in; + wire RXCDRRESET_in; + wire RXCHBONDEN_in; + wire RXCHBONDMASTER_in; + wire RXCHBONDSLAVE_in; + wire RXCKCALRESET_in; + wire RXCOMMADETEN_in; + wire RXDFEAGCHOLD_in; + wire RXDFEAGCOVRDEN_in; + wire RXDFECFOKFEN_in; + wire RXDFECFOKFPULSE_in; + wire RXDFECFOKHOLD_in; + wire RXDFECFOKOVREN_in; + wire RXDFEKHHOLD_in; + wire RXDFEKHOVRDEN_in; + wire RXDFELFHOLD_in; + wire RXDFELFOVRDEN_in; + wire RXDFELPMRESET_in; + wire RXDFETAP10HOLD_in; + wire RXDFETAP10OVRDEN_in; + wire RXDFETAP11HOLD_in; + wire RXDFETAP11OVRDEN_in; + wire RXDFETAP12HOLD_in; + wire RXDFETAP12OVRDEN_in; + wire RXDFETAP13HOLD_in; + wire RXDFETAP13OVRDEN_in; + wire RXDFETAP14HOLD_in; + wire RXDFETAP14OVRDEN_in; + wire RXDFETAP15HOLD_in; + wire RXDFETAP15OVRDEN_in; + wire RXDFETAP2HOLD_in; + wire RXDFETAP2OVRDEN_in; + wire RXDFETAP3HOLD_in; + wire RXDFETAP3OVRDEN_in; + wire RXDFETAP4HOLD_in; + wire RXDFETAP4OVRDEN_in; + wire RXDFETAP5HOLD_in; + wire RXDFETAP5OVRDEN_in; + wire RXDFETAP6HOLD_in; + wire RXDFETAP6OVRDEN_in; + wire RXDFETAP7HOLD_in; + wire RXDFETAP7OVRDEN_in; + wire RXDFETAP8HOLD_in; + wire RXDFETAP8OVRDEN_in; + wire RXDFETAP9HOLD_in; + wire RXDFETAP9OVRDEN_in; + wire RXDFEUTHOLD_in; + wire RXDFEUTOVRDEN_in; + wire RXDFEVPHOLD_in; + wire RXDFEVPOVRDEN_in; + wire RXDFEXYDEN_in; + wire RXDLYBYPASS_in; + wire RXDLYEN_in; + wire RXDLYOVRDEN_in; + wire RXDLYSRESET_in; + wire RXEQTRAINING_in; + wire RXGEARBOXSLIP_in; + wire RXLATCLK_in; + wire RXLPMEN_in; + wire RXLPMGCHOLD_in; + wire RXLPMGCOVRDEN_in; + wire RXLPMHFHOLD_in; + wire RXLPMHFOVRDEN_in; + wire RXLPMLFHOLD_in; + wire RXLPMLFKLOVRDEN_in; + wire RXLPMOSHOLD_in; + wire RXLPMOSOVRDEN_in; + wire RXMCOMMAALIGNEN_in; + wire RXOOBRESET_in; + wire RXOSCALRESET_in; + wire RXOSHOLD_in; + wire RXOSOVRDEN_in; + wire RXPCOMMAALIGNEN_in; + wire RXPCSRESET_in; + wire RXPHALIGNEN_in; + wire RXPHALIGN_in; + wire RXPHDLYPD_in; + wire RXPHDLYRESET_in; + wire RXPHOVRDEN_in; + wire RXPMARESET_in; + wire RXPOLARITY_in; + wire RXPRBSCNTRESET_in; + wire RXPROGDIVRESET_in; + wire RXQPIEN_in; + wire RXRATEMODE_in; + wire RXSLIDE_in; + wire RXSLIPOUTCLK_in; + wire RXSLIPPMA_in; + wire RXSYNCALLIN_in; + wire RXSYNCIN_in; + wire RXSYNCMODE_in; + wire RXTERMINATION_in; + wire RXUSERRDY_in; + wire RXUSRCLK2_in; + wire RXUSRCLK_in; + wire SARCCLK_in; + wire SCANCLK_in; + wire SCANENB_in; + wire SCANMODEB_in; + wire SCANRSTB_in; + wire SCANRSTEN_in; + wire SIGVALIDCLK_in; + wire TSTCLK0_in; + wire TSTCLK1_in; + wire TSTPDOVRDB_in; + wire TX8B10BEN_in; + wire TXCOMINIT_in; + wire TXCOMSAS_in; + wire TXCOMWAKE_in; + wire TXDCCFORCESTART_in; + wire TXDCCRESET_in; + wire TXDETECTRX_in; + wire TXDLYBYPASS_in; + wire TXDLYEN_in; + wire TXDLYHOLD_in; + wire TXDLYOVRDEN_in; + wire TXDLYSRESET_in; + wire TXDLYUPDOWN_in; + wire TXELECIDLE_in; + wire TXINHIBIT_in; + wire TXLATCLK_in; + wire TXLFPSTRESET_in; + wire TXLFPSU2LPEXIT_in; + wire TXLFPSU3WAKE_in; + wire TXMUXDCDEXHOLD_in; + wire TXMUXDCDORWREN_in; + wire TXONESZEROS_in; + wire TXPCSRESET_in; + wire TXPDELECIDLEMODE_in; + wire TXPHALIGNEN_in; + wire TXPHALIGN_in; + wire TXPHDLYPD_in; + wire TXPHDLYRESET_in; + wire TXPHDLYTSTCLK_in; + wire TXPHINIT_in; + wire TXPHOVRDEN_in; + wire TXPIPPMEN_in; + wire TXPIPPMOVRDEN_in; + wire TXPIPPMPD_in; + wire TXPIPPMSEL_in; + wire TXPISOPD_in; + wire TXPMARESET_in; + wire TXPOLARITY_in; + wire TXPRBSFORCEERR_in; + wire TXPROGDIVRESET_in; + wire TXQPIBIASEN_in; + wire TXQPIWEAKPUP_in; + wire TXRATEMODE_in; + wire TXSWING_in; + wire TXSYNCALLIN_in; + wire TXSYNCIN_in; + wire TXSYNCMODE_in; + wire TXUSERRDY_in; + wire TXUSRCLK2_in; + wire TXUSRCLK_in; + wire [127:0] TXDATA_in; + wire [15:0] DRPDI_in; + wire [15:0] GTRSVD_in; + wire [15:0] PCSRSVDIN_in; + wire [15:0] TXCTRL0_in; + wire [15:0] TXCTRL1_in; + wire [17:0] PMASCANIN_in; + wire [18:0] SCANIN_in; + wire [19:0] TSTIN_in; + wire [1:0] RXDFEAGCCTRL_in; + wire [1:0] RXELECIDLEMODE_in; + wire [1:0] RXMONITORSEL_in; + wire [1:0] RXPD_in; + wire [1:0] RXPLLCLKSEL_in; + wire [1:0] RXSYSCLKSEL_in; + wire [1:0] TXDEEMPH_in; + wire [1:0] TXPD_in; + wire [1:0] TXPLLCLKSEL_in; + wire [1:0] TXSYSCLKSEL_in; + wire [2:0] CPLLREFCLKSEL_in; + wire [2:0] LOOPBACK_in; + wire [2:0] RXCHBONDLEVEL_in; + wire [2:0] RXOUTCLKSEL_in; + wire [2:0] RXRATE_in; + wire [2:0] TXMARGIN_in; + wire [2:0] TXOUTCLKSEL_in; + wire [2:0] TXRATE_in; + wire [3:0] RXDFECFOKFCNUM_in; + wire [3:0] RXPRBSSEL_in; + wire [3:0] TXPRBSSEL_in; + wire [4:0] RXCHBONDI_in; + wire [4:0] TSTPD_in; + wire [4:0] TXDIFFCTRL_in; + wire [4:0] TXPIPPMSTEPSIZE_in; + wire [4:0] TXPOSTCURSOR_in; + wire [4:0] TXPRECURSOR_in; + wire [5:0] TXHEADER_in; + wire [6:0] RXCKCALSTART_in; + wire [6:0] TXMAINCURSOR_in; + wire [6:0] TXSEQUENCE_in; + wire [7:0] TX8B10BBYPASS_in; + wire [7:0] TXCTRL2_in; + wire [7:0] TXDATAEXTENDRSVD_in; + wire [9:0] DRPADDR_in; + + wire gt_intclk; + reg gt_clk_int; + +`ifdef XIL_TIMING + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire RX8B10BEN_delay; + wire RXCHBONDEN_delay; + wire RXCHBONDMASTER_delay; + wire RXCHBONDSLAVE_delay; + wire RXCOMMADETEN_delay; + wire RXGEARBOXSLIP_delay; + wire RXMCOMMAALIGNEN_delay; + wire RXPCOMMAALIGNEN_delay; + wire RXPOLARITY_delay; + wire RXPRBSCNTRESET_delay; + wire RXSLIDE_delay; + wire RXSLIPOUTCLK_delay; + wire RXUSRCLK2_delay; + wire RXUSRCLK_delay; + wire TX8B10BEN_delay; + wire TXCOMINIT_delay; + wire TXCOMSAS_delay; + wire TXCOMWAKE_delay; + wire TXDETECTRX_delay; + wire TXELECIDLE_delay; + wire TXINHIBIT_delay; + wire TXPOLARITY_delay; + wire TXPRBSFORCEERR_delay; + wire TXUSRCLK2_delay; + wire [127:0] TXDATA_delay; + wire [15:0] DRPDI_delay; + wire [15:0] TXCTRL0_delay; + wire [15:0] TXCTRL1_delay; + wire [2:0] RXCHBONDLEVEL_delay; + wire [3:0] RXPRBSSEL_delay; + wire [3:0] TXPRBSSEL_delay; + wire [4:0] RXCHBONDI_delay; + wire [5:0] TXHEADER_delay; + wire [6:0] TXSEQUENCE_delay; + wire [7:0] TX8B10BBYPASS_delay; + wire [7:0] TXCTRL2_delay; + wire [9:0] DRPADDR_delay; +`endif + + assign BUFGTCE = BUFGTCE_out; + assign BUFGTCEMASK = BUFGTCEMASK_out; + assign BUFGTDIV = BUFGTDIV_out; + assign BUFGTRESET = BUFGTRESET_out; + assign BUFGTRSTMASK = BUFGTRSTMASK_out; + assign CPLLFBCLKLOST = CPLLFBCLKLOST_out; + assign CPLLLOCK = CPLLLOCK_out; + assign CPLLREFCLKLOST = CPLLREFCLKLOST_out; + assign DMONITOROUT = DMONITOROUT_out; + assign DMONITOROUTCLK = DMONITOROUTCLK_out; + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign EYESCANDATAERROR = EYESCANDATAERROR_out; + assign GTHTXN = GTHTXN_out; + assign GTHTXP = GTHTXP_out; + assign GTPOWERGOOD = GTPOWERGOOD_out; + assign GTREFCLKMONITOR = GTREFCLKMONITOR_out; + assign PCIERATEGEN3 = PCIERATEGEN3_out; + assign PCIERATEIDLE = PCIERATEIDLE_out; + assign PCIERATEQPLLPD = PCIERATEQPLLPD_out; + assign PCIERATEQPLLRESET = PCIERATEQPLLRESET_out; + assign PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_out; + assign PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_out; + assign PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_out; + assign PCIEUSERRATESTART = PCIEUSERRATESTART_out; + assign PCSRSVDOUT = PCSRSVDOUT_out; + assign PHYSTATUS = PHYSTATUS_out; + assign PINRSRVDAS = PINRSRVDAS_out; + assign POWERPRESENT = POWERPRESENT_out; + assign RESETEXCEPTION = RESETEXCEPTION_out; + assign RXBUFSTATUS = RXBUFSTATUS_out; + assign RXBYTEISALIGNED = RXBYTEISALIGNED_out; + assign RXBYTEREALIGN = RXBYTEREALIGN_out; + assign RXCDRLOCK = RXCDRLOCK_out; + assign RXCDRPHDONE = RXCDRPHDONE_out; + assign RXCHANBONDSEQ = RXCHANBONDSEQ_out; + assign RXCHANISALIGNED = RXCHANISALIGNED_out; + assign RXCHANREALIGN = RXCHANREALIGN_out; + assign RXCHBONDO = RXCHBONDO_out; + assign RXCKCALDONE = RXCKCALDONE_out; + assign RXCLKCORCNT = RXCLKCORCNT_out; + assign RXCOMINITDET = RXCOMINITDET_out; + assign RXCOMMADET = RXCOMMADET_out; + assign RXCOMSASDET = RXCOMSASDET_out; + assign RXCOMWAKEDET = RXCOMWAKEDET_out; + assign RXCTRL0 = RXCTRL0_out; + assign RXCTRL1 = RXCTRL1_out; + assign RXCTRL2 = RXCTRL2_out; + assign RXCTRL3 = RXCTRL3_out; + assign RXDATA = RXDATA_out; + assign RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_out; + assign RXDATAVALID = RXDATAVALID_out; + assign RXDLYSRESETDONE = RXDLYSRESETDONE_out; + assign RXELECIDLE = RXELECIDLE_out; + assign RXHEADER = RXHEADER_out; + assign RXHEADERVALID = RXHEADERVALID_out; + assign RXLFPSTRESETDET = RXLFPSTRESETDET_out; + assign RXLFPSU2LPEXITDET = RXLFPSU2LPEXITDET_out; + assign RXLFPSU3WAKEDET = RXLFPSU3WAKEDET_out; + assign RXMONITOROUT = RXMONITOROUT_out; + assign RXOSINTDONE = RXOSINTDONE_out; + assign RXOSINTSTARTED = RXOSINTSTARTED_out; + assign RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_out; + assign RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_out; + assign RXOUTCLK = RXOUTCLK_out; + assign RXOUTCLKFABRIC = RXOUTCLKFABRIC_out; + + //EL + //assign RXOUTCLKPCS = RXOUTCLKPCS_out; + assign RXOUTCLKPCS = (RXPD_in == 2'b11) ? gt_intclk : RXOUTCLKPCS_out; + + assign RXPHALIGNDONE = RXPHALIGNDONE_out; + assign RXPHALIGNERR = RXPHALIGNERR_out; + assign RXPMARESETDONE = RXPMARESETDONE_out; + assign RXPRBSERR = RXPRBSERR_out; + assign RXPRBSLOCKED = RXPRBSLOCKED_out; + assign RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_out; + assign RXQPISENN = RXQPISENN_out; + assign RXQPISENP = RXQPISENP_out; + assign RXRATEDONE = RXRATEDONE_out; + assign RXRECCLKOUT = RXRECCLKOUT_out; + assign RXRESETDONE = RXRESETDONE_out; + assign RXSLIDERDY = RXSLIDERDY_out; + assign RXSLIPDONE = RXSLIPDONE_out; + assign RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_out; + assign RXSLIPPMARDY = RXSLIPPMARDY_out; + assign RXSTARTOFSEQ = RXSTARTOFSEQ_out; + assign RXSTATUS = RXSTATUS_out; + assign RXSYNCDONE = RXSYNCDONE_out; + assign RXSYNCOUT = RXSYNCOUT_out; + assign RXVALID = RXVALID_out; + assign TXBUFSTATUS = TXBUFSTATUS_out; + assign TXCOMFINISH = TXCOMFINISH_out; + assign TXDCCDONE = TXDCCDONE_out; + assign TXDLYSRESETDONE = TXDLYSRESETDONE_out; + + //EL + //assign TXOUTCLK = TXOUTCLK_out; + assign TXOUTCLK = (TXPISOPD_in && TXOUTCLKSEL_in == 3'b101) ? gt_intclk : TXOUTCLK_out; + + assign TXOUTCLKFABRIC = TXOUTCLKFABRIC_out; + + //EL + // assign TXOUTCLKPCS = TXPISOPD_in ? gt_intclk : TXOUTCLKPCS_out; + assign TXOUTCLKPCS = TXOUTCLKPCS_out; + + assign TXPHALIGNDONE = TXPHALIGNDONE_out; + assign TXPHINITDONE = TXPHINITDONE_out; + assign TXPMARESETDONE = TXPMARESETDONE_out; + assign TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_out; + assign TXQPISENN = TXQPISENN_out; + assign TXQPISENP = TXQPISENP_out; + assign TXRATEDONE = TXRATEDONE_out; + assign TXRESETDONE = TXRESETDONE_out; + assign TXSYNCDONE = TXSYNCDONE_out; + assign TXSYNCOUT = TXSYNCOUT_out; + +`ifdef XIL_TIMING + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0 +`else + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL[3]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA[9]; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL[3]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE[6]; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2; // rv 0 +`endif + + assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR; // rv 0 + assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ; // rv 0 + assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX; // rv 0 + assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET; // rv 0 + assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0; // rv 0 + assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1; // rv 0 + assign CPLLFREQLOCK_in = (CPLLFREQLOCK !== 1'bz) && CPLLFREQLOCK; // rv 0 + assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK; // rv 0 + assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN; // rv 0 + assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD; // rv 0 + assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL[0]; // rv 1 + assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL[1]; // rv 0 + assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL[2]; // rv 0 + assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET; // rv 0 + assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET; // rv 0 + assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK; // rv 0 + assign DRPRST_in = (DRPRST === 1'bz) || DRPRST; // rv 1 + assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET; // rv 0 + assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER; // rv 0 + assign FREQOS_in = (FREQOS !== 1'bz) && FREQOS; // rv 0 + assign GTGREFCLK_in = GTGREFCLK; + assign GTHRXN_in = GTHRXN; + assign GTHRXP_in = GTHRXP; + assign GTNORTHREFCLK0_in = GTNORTHREFCLK0; + assign GTNORTHREFCLK1_in = GTNORTHREFCLK1; + assign GTREFCLK0_in = GTREFCLK0; + assign GTREFCLK1_in = GTREFCLK1; + assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD[0]; // rv 0 + assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD[10]; // rv 0 + assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD[11]; // rv 0 + assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD[12]; // rv 0 + assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD[13]; // rv 0 + assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD[14]; // rv 0 + assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD[15]; // rv 0 + assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD[1]; // rv 0 + assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD[2]; // rv 0 + assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD[3]; // rv 0 + assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD[4]; // rv 0 + assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD[5]; // rv 0 + assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD[6]; // rv 0 + assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD[7]; // rv 0 + assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD[8]; // rv 0 + assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD[9]; // rv 0 + assign GTRXRESETSEL_in = (GTRXRESETSEL !== 1'bz) && GTRXRESETSEL; // rv 0 + assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET; // rv 0 + assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0; + assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1; + assign GTTXRESETSEL_in = (GTTXRESETSEL !== 1'bz) && GTTXRESETSEL; // rv 0 + assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET; // rv 0 + assign INCPCTRL_in = (INCPCTRL !== 1'bz) && INCPCTRL; // rv 0 + assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK[0]; // rv 0 + assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK[1]; // rv 0 + assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK[2]; // rv 0 + assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE; // rv 0 + assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE; // rv 0 + assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART; // rv 0 + assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE; // rv 0 + assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] === 1'bz) || PCSRSVDIN[0]; // rv 1 + assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN[10]; // rv 0 + assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN[11]; // rv 0 + assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN[12]; // rv 0 + assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN[13]; // rv 0 + assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN[14]; // rv 0 + assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN[15]; // rv 0 + assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN[1]; // rv 0 + assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN[2]; // rv 0 + assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN[3]; // rv 0 + assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN[4]; // rv 0 + assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN[5]; // rv 0 + assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN[6]; // rv 0 + assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN[7]; // rv 0 + assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN[8]; // rv 0 + assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN[9]; // rv 0 + assign QPLL0CLK_in = QPLL0CLK; + assign QPLL0FREQLOCK_in = (QPLL0FREQLOCK !== 1'bz) && QPLL0FREQLOCK; // rv 0 + assign QPLL0REFCLK_in = QPLL0REFCLK; + assign QPLL1CLK_in = QPLL1CLK; + assign QPLL1FREQLOCK_in = (QPLL1FREQLOCK !== 1'bz) && QPLL1FREQLOCK; // rv 0 + assign QPLL1REFCLK_in = QPLL1REFCLK; + assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD; // rv 0 + assign RXAFECFOKEN_in = (RXAFECFOKEN === 1'bz) || RXAFECFOKEN; // rv 1 + assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET; // rv 0 + assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET; // rv 0 + assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD; // rv 0 + assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN; // rv 0 + assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET; // rv 0 + assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET; // rv 0 + assign RXCKCALSTART_in[0] = (RXCKCALSTART[0] !== 1'bz) && RXCKCALSTART[0]; // rv 0 + assign RXCKCALSTART_in[1] = (RXCKCALSTART[1] !== 1'bz) && RXCKCALSTART[1]; // rv 0 + assign RXCKCALSTART_in[2] = (RXCKCALSTART[2] !== 1'bz) && RXCKCALSTART[2]; // rv 0 + assign RXCKCALSTART_in[3] = (RXCKCALSTART[3] !== 1'bz) && RXCKCALSTART[3]; // rv 0 + assign RXCKCALSTART_in[4] = (RXCKCALSTART[4] !== 1'bz) && RXCKCALSTART[4]; // rv 0 + assign RXCKCALSTART_in[5] = (RXCKCALSTART[5] !== 1'bz) && RXCKCALSTART[5]; // rv 0 + assign RXCKCALSTART_in[6] = (RXCKCALSTART[6] !== 1'bz) && RXCKCALSTART[6]; // rv 0 + assign RXDFEAGCCTRL_in[0] = (RXDFEAGCCTRL[0] !== 1'bz) && RXDFEAGCCTRL[0]; // rv 0 + assign RXDFEAGCCTRL_in[1] = (RXDFEAGCCTRL[1] !== 1'bz) && RXDFEAGCCTRL[1]; // rv 0 + assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD; // rv 0 + assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN; // rv 0 + assign RXDFECFOKFCNUM_in[0] = (RXDFECFOKFCNUM[0] !== 1'bz) && RXDFECFOKFCNUM[0]; // rv 0 + assign RXDFECFOKFCNUM_in[1] = (RXDFECFOKFCNUM[1] === 1'bz) || RXDFECFOKFCNUM[1]; // rv 1 + assign RXDFECFOKFCNUM_in[2] = (RXDFECFOKFCNUM[2] === 1'bz) || RXDFECFOKFCNUM[2]; // rv 1 + assign RXDFECFOKFCNUM_in[3] = (RXDFECFOKFCNUM[3] !== 1'bz) && RXDFECFOKFCNUM[3]; // rv 0 + assign RXDFECFOKFEN_in = (RXDFECFOKFEN !== 1'bz) && RXDFECFOKFEN; // rv 0 + assign RXDFECFOKFPULSE_in = (RXDFECFOKFPULSE !== 1'bz) && RXDFECFOKFPULSE; // rv 0 + assign RXDFECFOKHOLD_in = (RXDFECFOKHOLD !== 1'bz) && RXDFECFOKHOLD; // rv 0 + assign RXDFECFOKOVREN_in = (RXDFECFOKOVREN !== 1'bz) && RXDFECFOKOVREN; // rv 0 + assign RXDFEKHHOLD_in = (RXDFEKHHOLD !== 1'bz) && RXDFEKHHOLD; // rv 0 + assign RXDFEKHOVRDEN_in = (RXDFEKHOVRDEN !== 1'bz) && RXDFEKHOVRDEN; // rv 0 + assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD; // rv 0 + assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN; // rv 0 + assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET; // rv 0 + assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD; // rv 0 + assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN; // rv 0 + assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD; // rv 0 + assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN; // rv 0 + assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD; // rv 0 + assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN; // rv 0 + assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD; // rv 0 + assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN; // rv 0 + assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD; // rv 0 + assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN; // rv 0 + assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD; // rv 0 + assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN; // rv 0 + assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD; // rv 0 + assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN; // rv 0 + assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD; // rv 0 + assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN; // rv 0 + assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD; // rv 0 + assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN; // rv 0 + assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD; // rv 0 + assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN; // rv 0 + assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD; // rv 0 + assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN; // rv 0 + assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD; // rv 0 + assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN; // rv 0 + assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD; // rv 0 + assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN; // rv 0 + assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD; // rv 0 + assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN; // rv 0 + assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD; // rv 0 + assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN; // rv 0 + assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD; // rv 0 + assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN; // rv 0 + assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN; // rv 0 + assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS; // rv 0 + assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN; // rv 0 + assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN; // rv 0 + assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET; // rv 0 + assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE[0]; // rv 0 + assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE[1]; // rv 0 + assign RXEQTRAINING_in = (RXEQTRAINING !== 1'bz) && RXEQTRAINING; // rv 0 + assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK; // rv 0 + assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN; // rv 0 + assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD; // rv 0 + assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN; // rv 0 + assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD; // rv 0 + assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN; // rv 0 + assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD; // rv 0 + assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN; // rv 0 + assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD; // rv 0 + assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN; // rv 0 + assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL[0]; // rv 0 + assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL[1]; // rv 0 + assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET; // rv 0 + assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET; // rv 0 + assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD; // rv 0 + assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN; // rv 0 + assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL[0]; // rv 0 + assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL[1]; // rv 0 + assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL[2]; // rv 0 + assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET; // rv 0 + assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD[0]; // rv 0 + assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD[1]; // rv 0 + assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN; // rv 0 + assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN; // rv 0 + assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD; // rv 0 + assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET; // rv 0 + assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN; // rv 0 + assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL[0]; // rv 0 + assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL[1]; // rv 0 + assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET; // rv 0 + assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET; // rv 0 + assign RXQPIEN_in = (RXQPIEN !== 1'bz) && RXQPIEN; // rv 0 + assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE; // rv 0 + assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE[0]; // rv 0 + assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE[1]; // rv 0 + assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE[2]; // rv 0 + assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA; // rv 0 + assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN; // rv 0 + assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN; // rv 0 + assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE; // rv 1 + assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL[0]; // rv 0 + assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL[1]; // rv 0 + assign RXTERMINATION_in = (RXTERMINATION !== 1'bz) && RXTERMINATION; // rv 0 + assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY; // rv 0 + assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK; // rv 0 + assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN[0]; // rv 0 + assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN[10]; // rv 0 + assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN[11]; // rv 0 + assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN[12]; // rv 0 + assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN[13]; // rv 0 + assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN[14]; // rv 0 + assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN[15]; // rv 0 + assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN[16]; // rv 0 + assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN[17]; // rv 0 + assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN[18]; // rv 0 + assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN[19]; // rv 0 + assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN[1]; // rv 0 + assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN[2]; // rv 0 + assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN[3]; // rv 0 + assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN[4]; // rv 0 + assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN[5]; // rv 0 + assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN[6]; // rv 0 + assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN[7]; // rv 0 + assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN[8]; // rv 0 + assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN[9]; // rv 0 + assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD[0]; // rv 0 + assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD[1]; // rv 0 + assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD[2]; // rv 0 + assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD[3]; // rv 0 + assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD[4]; // rv 0 + assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD[5]; // rv 0 + assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD[6]; // rv 0 + assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD[7]; // rv 0 + assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART; // rv 0 + assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET; // rv 0 + assign TXDEEMPH_in[0] = (TXDEEMPH[0] !== 1'bz) && TXDEEMPH[0]; // rv 0 + assign TXDEEMPH_in[1] = (TXDEEMPH[1] !== 1'bz) && TXDEEMPH[1]; // rv 0 + assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL[0]; // rv 0 + assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL[1]; // rv 0 + assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL[2]; // rv 0 + assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL[3]; // rv 0 + assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL[4]; // rv 0 + assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS; // rv 0 + assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN; // rv 0 + assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD; // rv 0 + assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN; // rv 0 + assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET; // rv 0 + assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN; // rv 0 + assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK; // rv 0 + assign TXLFPSTRESET_in = (TXLFPSTRESET !== 1'bz) && TXLFPSTRESET; // rv 0 + assign TXLFPSU2LPEXIT_in = (TXLFPSU2LPEXIT !== 1'bz) && TXLFPSU2LPEXIT; // rv 0 + assign TXLFPSU3WAKE_in = (TXLFPSU3WAKE !== 1'bz) && TXLFPSU3WAKE; // rv 0 + assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR[0]; // rv 0 + assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR[1]; // rv 0 + assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR[2]; // rv 0 + assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR[3]; // rv 0 + assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR[4]; // rv 0 + assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR[5]; // rv 0 + assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR[6]; // rv 0 + assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN[0]; // rv 0 + assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN[1]; // rv 0 + assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN[2]; // rv 0 + assign TXMUXDCDEXHOLD_in = (TXMUXDCDEXHOLD !== 1'bz) && TXMUXDCDEXHOLD; // rv 0 + assign TXMUXDCDORWREN_in = (TXMUXDCDORWREN !== 1'bz) && TXMUXDCDORWREN; // rv 0 + assign TXONESZEROS_in = (TXONESZEROS !== 1'bz) && TXONESZEROS; // rv 0 + assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL[0]; // rv 0 + assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL[1]; // rv 0 + assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL[2]; // rv 0 + assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET; // rv 0 + assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE; // rv 0 + assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD[0]; // rv 0 + assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD[1]; // rv 0 + assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN; // rv 0 + assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN; // rv 0 + assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD; // rv 0 + assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET; // rv 0 + assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK; // rv 0 + assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT; // rv 0 + assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN; // rv 0 + assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN; // rv 0 + assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN; // rv 0 + assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD; // rv 0 + assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL; // rv 0 + assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE[0]; // rv 0 + assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE[1]; // rv 0 + assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE[2]; // rv 0 + assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE[3]; // rv 0 + assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE[4]; // rv 0 + assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD; // rv 0 + assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL[0]; // rv 0 + assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL[1]; // rv 0 + assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET; // rv 0 + assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR[0]; // rv 0 + assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR[1]; // rv 0 + assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR[2]; // rv 0 + assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR[3]; // rv 0 + assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR[4]; // rv 0 + assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR[0]; // rv 0 + assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR[1]; // rv 0 + assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR[2]; // rv 0 + assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR[3]; // rv 0 + assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR[4]; // rv 0 + assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET; // rv 0 + assign TXQPIBIASEN_in = (TXQPIBIASEN !== 1'bz) && TXQPIBIASEN; // rv 0 + assign TXQPIWEAKPUP_in = (TXQPIWEAKPUP !== 1'bz) && TXQPIWEAKPUP; // rv 0 + assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE; // rv 0 + assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE[0]; // rv 0 + assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE[1]; // rv 0 + assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE[2]; // rv 0 + assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING; // rv 0 + assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN; // rv 0 + assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN; // rv 0 + assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE; // rv 1 + assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL[0]; // rv 0 + assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL[1]; // rv 0 + assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY; // rv 0 + assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK; // rv 0 + + assign gt_intclk = gt_clk_int; + + initial begin + + #1; + trig_attr = ~trig_attr; + + gt_clk_int = 1'b0; + forever #10000 gt_clk_int = ~gt_clk_int; + + end + + +`ifdef XIL_XECLIB + assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_DOUBLE_REG != "FALSE") && + (ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_WORD_REG != 1) && + (ALIGN_COMMA_WORD_REG != 2) && + (ALIGN_COMMA_WORD_REG != 4))) begin + $display("Error: [Unisim %s-132] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_MCOMMA_DET_REG != "TRUE") && + (ALIGN_MCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-133] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_PCOMMA_DET_REG != "TRUE") && + (ALIGN_PCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-135] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") && + (CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin + $display("Error: [Unisim %s-273] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") && + (CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-276] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_MAX_SKEW_REG != 7) && + (CHAN_BOND_MAX_SKEW_REG != 1) && + (CHAN_BOND_MAX_SKEW_REG != 2) && + (CHAN_BOND_MAX_SKEW_REG != 3) && + (CHAN_BOND_MAX_SKEW_REG != 4) && + (CHAN_BOND_MAX_SKEW_REG != 5) && + (CHAN_BOND_MAX_SKEW_REG != 6) && + (CHAN_BOND_MAX_SKEW_REG != 8) && + (CHAN_BOND_MAX_SKEW_REG != 9) && + (CHAN_BOND_MAX_SKEW_REG != 10) && + (CHAN_BOND_MAX_SKEW_REG != 11) && + (CHAN_BOND_MAX_SKEW_REG != 12) && + (CHAN_BOND_MAX_SKEW_REG != 13) && + (CHAN_BOND_MAX_SKEW_REG != 14))) begin + $display("Error: [Unisim %s-277] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") && + (CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-288] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_LEN_REG != 2) && + (CHAN_BOND_SEQ_LEN_REG != 1) && + (CHAN_BOND_SEQ_LEN_REG != 3) && + (CHAN_BOND_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-289] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_CORRECT_USE_REG != "TRUE") && + (CLK_CORRECT_USE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-302] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_KEEP_IDLE_REG != "FALSE") && + (CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-303] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin + $display("Error: [Unisim %s-304] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin + $display("Error: [Unisim %s-305] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_PRECEDENCE_REG != "TRUE") && + (CLK_COR_PRECEDENCE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-306] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-307] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_2_USE_REG != "FALSE") && + (CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-318] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_LEN_REG != 2) && + (CLK_COR_SEQ_LEN_REG != 1) && + (CLK_COR_SEQ_LEN_REG != 3) && + (CLK_COR_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-319] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_REG != 4) && + (CPLL_FBDIV_REG != 1) && + (CPLL_FBDIV_REG != 2) && + (CPLL_FBDIV_REG != 3) && + (CPLL_FBDIV_REG != 5) && + (CPLL_FBDIV_REG != 6) && + (CPLL_FBDIV_REG != 8) && + (CPLL_FBDIV_REG != 10) && + (CPLL_FBDIV_REG != 12) && + (CPLL_FBDIV_REG != 16) && + (CPLL_FBDIV_REG != 20))) begin + $display("Error: [Unisim %s-325] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_45_REG != 4) && + (CPLL_FBDIV_45_REG != 5))) begin + $display("Error: [Unisim %s-326] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_REFCLK_DIV_REG != 1) && + (CPLL_REFCLK_DIV_REG != 2) && + (CPLL_REFCLK_DIV_REG != 3) && + (CPLL_REFCLK_DIV_REG != 4) && + (CPLL_REFCLK_DIV_REG != 5) && + (CPLL_REFCLK_DIV_REG != 6) && + (CPLL_REFCLK_DIV_REG != 8) && + (CPLL_REFCLK_DIV_REG != 10) && + (CPLL_REFCLK_DIV_REG != 12) && + (CPLL_REFCLK_DIV_REG != 16) && + (CPLL_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-329] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-346] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_MCOMMA_DETECT_REG != "TRUE") && + (DEC_MCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-347] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_PCOMMA_DETECT_REG != "TRUE") && + (DEC_PCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-348] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_VALID_COMMA_ONLY_REG != "TRUE") && + (DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-349] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_ERRDET_EN_REG != "FALSE") && + (ES_ERRDET_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-355] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_EYE_SCAN_EN_REG != "FALSE") && + (ES_EYE_SCAN_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-356] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FTS_LANE_DESKEW_EN_REG != "FALSE") && + (FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-392] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") && + (PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin + $display("Error: [Unisim %s-410] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCS_PCIE_EN_REG != "FALSE") && + (PCS_PCIE_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-432] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREIQ_FREQ_BST_REG != 0) && + (PREIQ_FREQ_BST_REG != 1) && + (PREIQ_FREQ_BST_REG != 2) && + (PREIQ_FREQ_BST_REG != 3))) begin + $display("Error: [Unisim %s-437] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_ADDR_MODE_REG != "FULL") && + (RXBUF_ADDR_MODE_REG != "FAST"))) begin + $display("Error: [Unisim %s-446] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_EN_REG != "TRUE") && + (RXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-449] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-450] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") && + (RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-451] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") && + (RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-452] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-453] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin + $display("Error: [Unisim %s-454] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVRD_REG != "FALSE") && + (RXBUF_THRESH_OVRD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-455] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin + $display("Error: [Unisim %s-456] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXELECIDLE_CFG_REG != "SIGCFG_4") && + (RXELECIDLE_CFG_REG != "SIGCFG_1") && + (RXELECIDLE_CFG_REG != "SIGCFG_2") && + (RXELECIDLE_CFG_REG != "SIGCFG_3") && + (RXELECIDLE_CFG_REG != "SIGCFG_6") && + (RXELECIDLE_CFG_REG != "SIGCFG_8") && + (RXELECIDLE_CFG_REG != "SIGCFG_12") && + (RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin + $display("Error: [Unisim %s-544] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin + $display("Error: [Unisim %s-545] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGEARBOX_EN_REG != "FALSE") && + (RXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-546] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOOB_CLK_CFG_REG != "PMA") && + (RXOOB_CLK_CFG_REG != "FABRIC"))) begin + $display("Error: [Unisim %s-555] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOUT_DIV_REG != 4) && + (RXOUT_DIV_REG != 1) && + (RXOUT_DIV_REG != 2) && + (RXOUT_DIV_REG != 8) && + (RXOUT_DIV_REG != 16))) begin + $display("Error: [Unisim %s-557] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, RXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPMACLK_SEL_REG != "DATA") && + (RXPMACLK_SEL_REG != "CROSSING") && + (RXPMACLK_SEL_REG != "EYESCAN"))) begin + $display("Error: [Unisim %s-571] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin + $display("Error: [Unisim %s-574] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_AUTO_WAIT_REG != 7) && + (RXSLIDE_AUTO_WAIT_REG != 1) && + (RXSLIDE_AUTO_WAIT_REG != 2) && + (RXSLIDE_AUTO_WAIT_REG != 3) && + (RXSLIDE_AUTO_WAIT_REG != 4) && + (RXSLIDE_AUTO_WAIT_REG != 5) && + (RXSLIDE_AUTO_WAIT_REG != 6) && + (RXSLIDE_AUTO_WAIT_REG != 8) && + (RXSLIDE_AUTO_WAIT_REG != 9) && + (RXSLIDE_AUTO_WAIT_REG != 10) && + (RXSLIDE_AUTO_WAIT_REG != 11) && + (RXSLIDE_AUTO_WAIT_REG != 12) && + (RXSLIDE_AUTO_WAIT_REG != 13) && + (RXSLIDE_AUTO_WAIT_REG != 14) && + (RXSLIDE_AUTO_WAIT_REG != 15))) begin + $display("Error: [Unisim %s-576] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_MODE_REG != "OFF") && + (RXSLIDE_MODE_REG != "AUTO") && + (RXSLIDE_MODE_REG != "PCS") && + (RXSLIDE_MODE_REG != "PMA"))) begin + $display("Error: [Unisim %s-577] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-585] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_SEL_REG != 3) && + (RX_CM_SEL_REG != 0) && + (RX_CM_SEL_REG != 1) && + (RX_CM_SEL_REG != 2))) begin + $display("Error: [Unisim %s-590] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 3, 0, 1 or 2. Instance: %m", MODULE_NAME, RX_CM_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_TRIM_REG != 12) && + (RX_CM_TRIM_REG != 0) && + (RX_CM_TRIM_REG != 1) && + (RX_CM_TRIM_REG != 2) && + (RX_CM_TRIM_REG != 3) && + (RX_CM_TRIM_REG != 4) && + (RX_CM_TRIM_REG != 5) && + (RX_CM_TRIM_REG != 6) && + (RX_CM_TRIM_REG != 7) && + (RX_CM_TRIM_REG != 8) && + (RX_CM_TRIM_REG != 9) && + (RX_CM_TRIM_REG != 10) && + (RX_CM_TRIM_REG != 11) && + (RX_CM_TRIM_REG != 13) && + (RX_CM_TRIM_REG != 14) && + (RX_CM_TRIM_REG != 15))) begin + $display("Error: [Unisim %s-591] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_WIDTH_REG != 20) && + (RX_DATA_WIDTH_REG != 16) && + (RX_DATA_WIDTH_REG != 32) && + (RX_DATA_WIDTH_REG != 40) && + (RX_DATA_WIDTH_REG != 64) && + (RX_DATA_WIDTH_REG != 80) && + (RX_DATA_WIDTH_REG != 128) && + (RX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-593] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") && + (RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-595] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFELPM_CFG0_REG != 0) && + (RX_DFELPM_CFG0_REG != 1) && + (RX_DFELPM_CFG0_REG != 2) && + (RX_DFELPM_CFG0_REG != 3) && + (RX_DFELPM_CFG0_REG != 4) && + (RX_DFELPM_CFG0_REG != 5) && + (RX_DFELPM_CFG0_REG != 6) && + (RX_DFELPM_CFG0_REG != 7) && + (RX_DFELPM_CFG0_REG != 8) && + (RX_DFELPM_CFG0_REG != 9) && + (RX_DFELPM_CFG0_REG != 10) && + (RX_DFELPM_CFG0_REG != 11) && + (RX_DFELPM_CFG0_REG != 12) && + (RX_DFELPM_CFG0_REG != 13) && + (RX_DFELPM_CFG0_REG != 14) && + (RX_DFELPM_CFG0_REG != 15))) begin + $display("Error: [Unisim %s-598] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_AGC_CFG1_REG != 4) && + (RX_DFE_AGC_CFG1_REG != 0) && + (RX_DFE_AGC_CFG1_REG != 1) && + (RX_DFE_AGC_CFG1_REG != 2) && + (RX_DFE_AGC_CFG1_REG != 3) && + (RX_DFE_AGC_CFG1_REG != 5) && + (RX_DFE_AGC_CFG1_REG != 6) && + (RX_DFE_AGC_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-602] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG0_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 0) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin + $display("Error: [Unisim %s-603] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG1_REG != 4) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 0) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 3) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 5) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 6) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-604] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KL_CFG1_REG != 4) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 0) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 1) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 2) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 3) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 5) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 6) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-606] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") && + (RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin + $display("Error: [Unisim %s-608] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_INT_DATAWIDTH_REG != 1) && + (RX_INT_DATAWIDTH_REG != 0) && + (RX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-619] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_PROGDIV_CFG_REG != 0.0) && + (RX_PROGDIV_CFG_REG != 4.0) && + (RX_PROGDIV_CFG_REG != 5.0) && + (RX_PROGDIV_CFG_REG != 8.0) && + (RX_PROGDIV_CFG_REG != 10.0) && + (RX_PROGDIV_CFG_REG != 16.0) && + (RX_PROGDIV_CFG_REG != 16.5) && + (RX_PROGDIV_CFG_REG != 20.0) && + (RX_PROGDIV_CFG_REG != 32.0) && + (RX_PROGDIV_CFG_REG != 33.0) && + (RX_PROGDIV_CFG_REG != 40.0) && + (RX_PROGDIV_CFG_REG != 64.0) && + (RX_PROGDIV_CFG_REG != 66.0) && + (RX_PROGDIV_CFG_REG != 80.0) && + (RX_PROGDIV_CFG_REG != 100.0) && + (RX_PROGDIV_CFG_REG != 128.0) && + (RX_PROGDIV_CFG_REG != 132.0))) begin + $display("Error: [Unisim %s-622] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin + $display("Error: [Unisim %s-627] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_XCLK_SEL_REG != "RXDES") && + (RX_XCLK_SEL_REG != "RXPMA") && + (RX_XCLK_SEL_REG != "RXUSR"))) begin + $display("Error: [Unisim %s-640] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") && + (SATA_CPLL_CFG_REG != "VCO_750MHZ") && + (SATA_CPLL_CFG_REG != "VCO_1500MHZ") && + (SATA_CPLL_CFG_REG != "VCO_6000MHZ"))) begin + $display("Error: [Unisim %s-646] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ or VCO_6000MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SHOW_REALIGN_COMMA_REG != "TRUE") && + (SHOW_REALIGN_COMMA_REG != "FALSE"))) begin + $display("Error: [Unisim %s-648] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-649] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_MODE_REG != "FAST") && + (SIM_MODE_REG != "LEGACY"))) begin + $display("Error: [Unisim %s-650] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") && + (SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-651] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-652] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_TX_EIDLE_DRIVE_LEVEL_REG != "Z") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "HIGH") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "LOW") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "X"))) begin + $display("Error: [Unisim %s-653] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %s. Legal values for this attribute are Z, HIGH, LOW or X. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_EN_REG != "TRUE") && + (TXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-662] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") && + (TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-663] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXFIFO_ADDR_CFG_REG != "LOW") && + (TXFIFO_ADDR_CFG_REG != "HIGH"))) begin + $display("Error: [Unisim %s-667] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin + $display("Error: [Unisim %s-668] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGEARBOX_EN_REG != "FALSE") && + (TXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-669] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXOUT_DIV_REG != 4) && + (TXOUT_DIV_REG != 1) && + (TXOUT_DIV_REG != 2) && + (TXOUT_DIV_REG != 8) && + (TXOUT_DIV_REG != 16))) begin + $display("Error: [Unisim %s-671] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, TXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") && + (TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin + $display("Error: [Unisim %s-689] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-698] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DATA_WIDTH_REG != 20) && + (TX_DATA_WIDTH_REG != 16) && + (TX_DATA_WIDTH_REG != 32) && + (TX_DATA_WIDTH_REG != 40) && + (TX_DATA_WIDTH_REG != 64) && + (TX_DATA_WIDTH_REG != 80) && + (TX_DATA_WIDTH_REG != 128) && + (TX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-700] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRIVE_MODE_REG != "DIRECT") && + (TX_DRIVE_MODE_REG != "PIPE") && + (TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin + $display("Error: [Unisim %s-707] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRVMUX_CTRL_REG != 2) && + (TX_DRVMUX_CTRL_REG != 0) && + (TX_DRVMUX_CTRL_REG != 1) && + (TX_DRVMUX_CTRL_REG != 3))) begin + $display("Error: [Unisim %s-708] TX_DRVMUX_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_DRVMUX_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_INT_DATAWIDTH_REG != 1) && + (TX_INT_DATAWIDTH_REG != 0) && + (TX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-714] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") && + (TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin + $display("Error: [Unisim %s-715] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PI_BIASSET_REG != 0) && + (TX_PI_BIASSET_REG != 1) && + (TX_PI_BIASSET_REG != 2) && + (TX_PI_BIASSET_REG != 3))) begin + $display("Error: [Unisim %s-730] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PREDRV_CTRL_REG != 2) && + (TX_PREDRV_CTRL_REG != 0) && + (TX_PREDRV_CTRL_REG != 1) && + (TX_PREDRV_CTRL_REG != 3))) begin + $display("Error: [Unisim %s-735] TX_PREDRV_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_PREDRV_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGCLK_SEL_REG != "POSTPI") && + (TX_PROGCLK_SEL_REG != "CPLL") && + (TX_PROGCLK_SEL_REG != "PREPI"))) begin + $display("Error: [Unisim %s-736] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGDIV_CFG_REG != 0.0) && + (TX_PROGDIV_CFG_REG != 4.0) && + (TX_PROGDIV_CFG_REG != 5.0) && + (TX_PROGDIV_CFG_REG != 8.0) && + (TX_PROGDIV_CFG_REG != 10.0) && + (TX_PROGDIV_CFG_REG != 16.0) && + (TX_PROGDIV_CFG_REG != 16.5) && + (TX_PROGDIV_CFG_REG != 20.0) && + (TX_PROGDIV_CFG_REG != 32.0) && + (TX_PROGDIV_CFG_REG != 33.0) && + (TX_PROGDIV_CFG_REG != 40.0) && + (TX_PROGDIV_CFG_REG != 64.0) && + (TX_PROGDIV_CFG_REG != 66.0) && + (TX_PROGDIV_CFG_REG != 80.0) && + (TX_PROGDIV_CFG_REG != 100.0) && + (TX_PROGDIV_CFG_REG != 128.0) && + (TX_PROGDIV_CFG_REG != 132.0))) begin + $display("Error: [Unisim %s-737] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_RXDETECT_REF_REG != 3) && + (TX_RXDETECT_REF_REG != 0) && + (TX_RXDETECT_REF_REG != 1) && + (TX_RXDETECT_REF_REG != 2) && + (TX_RXDETECT_REF_REG != 4) && + (TX_RXDETECT_REF_REG != 5) && + (TX_RXDETECT_REF_REG != 6) && + (TX_RXDETECT_REF_REG != 7))) begin + $display("Error: [Unisim %s-741] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 3, 0, 1, 2, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_XCLK_SEL_REG != "TXOUT") && + (TX_XCLK_SEL_REG != "TXUSR"))) begin + $display("Error: [Unisim %s-756] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_PING_SATA_MAX_INIT_REG < 1) || (USB_PING_SATA_MAX_INIT_REG > 63))) begin + $display("Error: [Unisim %s-774] USB_PING_SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MAX_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_PING_SATA_MIN_INIT_REG < 1) || (USB_PING_SATA_MIN_INIT_REG > 63))) begin + $display("Error: [Unisim %s-775] USB_PING_SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MIN_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_POLL_SATA_MAX_BURST_REG < 1) || (USB_POLL_SATA_MAX_BURST_REG > 63))) begin + $display("Error: [Unisim %s-776] USB_POLL_SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_POLL_SATA_MAX_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_POLL_SATA_MIN_BURST_REG < 1) || (USB_POLL_SATA_MIN_BURST_REG > 61))) begin + $display("Error: [Unisim %s-777] USB_POLL_SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, USB_POLL_SATA_MIN_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U1_SATA_MAX_WAKE_REG < 1) || (USB_U1_SATA_MAX_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-781] USB_U1_SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MAX_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U1_SATA_MIN_WAKE_REG < 1) || (USB_U1_SATA_MIN_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-782] USB_U1_SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MIN_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U2_SAS_MAX_COM_REG < 1) || (USB_U2_SAS_MAX_COM_REG > 127))) begin + $display("Error: [Unisim %s-783] USB_U2_SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, USB_U2_SAS_MAX_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U2_SAS_MIN_COM_REG < 1) || (USB_U2_SAS_MIN_COM_REG > 63))) begin + $display("Error: [Unisim %s-784] USB_U2_SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U2_SAS_MIN_COM_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + +assign PMASCANCLK0_in = 1'b1; // tie off +assign PMASCANCLK1_in = 1'b1; // tie off +assign PMASCANCLK2_in = 1'b1; // tie off +assign PMASCANCLK3_in = 1'b1; // tie off +assign PMASCANCLK4_in = 1'b1; // tie off +assign PMASCANCLK5_in = 1'b1; // tie off +assign PMASCANCLK6_in = 1'b1; // tie off +assign PMASCANCLK7_in = 1'b1; // tie off +assign PMASCANCLK8_in = 1'b1; // tie off +assign SCANCLK_in = 1'b1; // tie off +assign TSTCLK0_in = 1'b1; // tie off +assign TSTCLK1_in = 1'b1; // tie off + +assign BSR_SERIAL_in = 1'b1; // tie off +assign CSSDRSTB_in = 1'b1; // tie off +assign CSSDSTOPCLK_in = 1'b1; // tie off +assign PMASCANENB_in = 1'b1; // tie off +assign PMASCANIN_in = 18'b111111111111111111; // tie off +assign PMASCANMODEB_in = 1'b1; // tie off +assign PMASCANRSTEN_in = 1'b1; // tie off +assign SARCCLK_in = 1'b1; // tie off +assign SCANENB_in = 1'b1; // tie off +assign SCANIN_in = 19'b1111111111111111111; // tie off +assign SCANMODEB_in = 1'b1; // tie off +assign SCANRSTB_in = 1'b1; // tie off +assign SCANRSTEN_in = 1'b1; // tie off +assign TSTPDOVRDB_in = 1'b1; // tie off +assign TSTPD_in = 5'b11111; // tie off + +SIP_GTHE4_CHANNEL SIP_GTHE4_CHANNEL_INST ( +.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG), +.ACJTAG_MODE (ACJTAG_MODE_REG), +.ACJTAG_RESET (ACJTAG_RESET_REG), +.ADAPT_CFG0 (ADAPT_CFG0_REG), +.ADAPT_CFG1 (ADAPT_CFG1_REG), +.ADAPT_CFG2 (ADAPT_CFG2_REG), +.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG), +.AEN_CPLL (AEN_CPLL_REG), +.AEN_LOOPBACK (AEN_LOOPBACK_REG), +.AEN_MASTER (AEN_MASTER_REG), +.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG), +.AEN_POLARITY (AEN_POLARITY_REG), +.AEN_PRBS (AEN_PRBS_REG), +.AEN_QPI (AEN_QPI_REG), +.AEN_RESET (AEN_RESET_REG), +.AEN_RXCDR (AEN_RXCDR_REG), +.AEN_RXDFE (AEN_RXDFE_REG), +.AEN_RXDFELPM (AEN_RXDFELPM_REG), +.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG), +.AEN_RXPHDLY (AEN_RXPHDLY_REG), +.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG), +.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG), +.AEN_TXMUXDCD (AEN_TXMUXDCD_REG), +.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG), +.AEN_TXPHDLY (AEN_TXPHDLY_REG), +.AEN_TXPI_PPM (AEN_TXPI_PPM_REG), +.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG), +.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG), +.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG), +.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG), +.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG), +.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG), +.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG), +.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG), +.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG), +.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG), +.AMONITOR_CFG (AMONITOR_CFG_REG), +.A_CPLLLOCKEN (A_CPLLLOCKEN_REG), +.A_CPLLPD (A_CPLLPD_REG), +.A_CPLLRESET (A_CPLLRESET_REG), +.A_EYESCANRESET (A_EYESCANRESET_REG), +.A_GTRESETSEL (A_GTRESETSEL_REG), +.A_GTRXRESET (A_GTRXRESET_REG), +.A_GTTXRESET (A_GTTXRESET_REG), +.A_LOOPBACK (A_LOOPBACK_REG), +.A_RXAFECFOKEN (A_RXAFECFOKEN_REG), +.A_RXBUFRESET (A_RXBUFRESET_REG), +.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG), +.A_RXCDRHOLD (A_RXCDRHOLD_REG), +.A_RXCDROVRDEN (A_RXCDROVRDEN_REG), +.A_RXCDRRESET (A_RXCDRRESET_REG), +.A_RXCKCALRESET (A_RXCKCALRESET_REG), +.A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG), +.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG), +.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG), +.A_RXDFECFOKFCNUM (A_RXDFECFOKFCNUM_REG), +.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG), +.A_RXDFECFOKFPULSE (A_RXDFECFOKFPULSE_REG), +.A_RXDFECFOKHOLD (A_RXDFECFOKHOLD_REG), +.A_RXDFECFOKOVREN (A_RXDFECFOKOVREN_REG), +.A_RXDFEKHHOLD (A_RXDFEKHHOLD_REG), +.A_RXDFEKHOVRDEN (A_RXDFEKHOVRDEN_REG), +.A_RXDFELFHOLD (A_RXDFELFHOLD_REG), +.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG), +.A_RXDFELPMRESET (A_RXDFELPMRESET_REG), +.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG), +.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG), +.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG), +.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG), +.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG), +.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG), +.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG), +.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG), +.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG), +.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG), +.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG), +.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG), +.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG), +.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG), +.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG), +.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG), +.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG), +.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG), +.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG), +.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG), +.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG), +.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG), +.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG), +.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG), +.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG), +.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG), +.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG), +.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG), +.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG), +.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG), +.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG), +.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG), +.A_RXDFEXYDEN (A_RXDFEXYDEN_REG), +.A_RXDLYBYPASS (A_RXDLYBYPASS_REG), +.A_RXDLYEN (A_RXDLYEN_REG), +.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG), +.A_RXDLYSRESET (A_RXDLYSRESET_REG), +.A_RXLPMEN (A_RXLPMEN_REG), +.A_RXLPMGCHOLD (A_RXLPMGCHOLD_REG), +.A_RXLPMGCOVRDEN (A_RXLPMGCOVRDEN_REG), +.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG), +.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG), +.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG), +.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG), +.A_RXLPMOSHOLD (A_RXLPMOSHOLD_REG), +.A_RXLPMOSOVRDEN (A_RXLPMOSOVRDEN_REG), +.A_RXMONITORSEL (A_RXMONITORSEL_REG), +.A_RXOOBRESET (A_RXOOBRESET_REG), +.A_RXOSCALRESET (A_RXOSCALRESET_REG), +.A_RXOSHOLD (A_RXOSHOLD_REG), +.A_RXOSOVRDEN (A_RXOSOVRDEN_REG), +.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG), +.A_RXPCSRESET (A_RXPCSRESET_REG), +.A_RXPD (A_RXPD_REG), +.A_RXPHALIGN (A_RXPHALIGN_REG), +.A_RXPHALIGNEN (A_RXPHALIGNEN_REG), +.A_RXPHDLYPD (A_RXPHDLYPD_REG), +.A_RXPHDLYRESET (A_RXPHDLYRESET_REG), +.A_RXPHOVRDEN (A_RXPHOVRDEN_REG), +.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG), +.A_RXPMARESET (A_RXPMARESET_REG), +.A_RXPOLARITY (A_RXPOLARITY_REG), +.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG), +.A_RXPRBSSEL (A_RXPRBSSEL_REG), +.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG), +.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG), +.A_RXTERMINATION (A_RXTERMINATION_REG), +.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG), +.A_TXDCCRESET (A_TXDCCRESET_REG), +.A_TXDEEMPH (A_TXDEEMPH_REG), +.A_TXDIFFCTRL (A_TXDIFFCTRL_REG), +.A_TXDLYBYPASS (A_TXDLYBYPASS_REG), +.A_TXDLYEN (A_TXDLYEN_REG), +.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG), +.A_TXDLYSRESET (A_TXDLYSRESET_REG), +.A_TXELECIDLE (A_TXELECIDLE_REG), +.A_TXINHIBIT (A_TXINHIBIT_REG), +.A_TXMAINCURSOR (A_TXMAINCURSOR_REG), +.A_TXMARGIN (A_TXMARGIN_REG), +.A_TXMUXDCDEXHOLD (A_TXMUXDCDEXHOLD_REG), +.A_TXMUXDCDORWREN (A_TXMUXDCDORWREN_REG), +.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG), +.A_TXPCSRESET (A_TXPCSRESET_REG), +.A_TXPD (A_TXPD_REG), +.A_TXPHALIGN (A_TXPHALIGN_REG), +.A_TXPHALIGNEN (A_TXPHALIGNEN_REG), +.A_TXPHDLYPD (A_TXPHDLYPD_REG), +.A_TXPHDLYRESET (A_TXPHDLYRESET_REG), +.A_TXPHINIT (A_TXPHINIT_REG), +.A_TXPHOVRDEN (A_TXPHOVRDEN_REG), +.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG), +.A_TXPIPPMPD (A_TXPIPPMPD_REG), +.A_TXPIPPMSEL (A_TXPIPPMSEL_REG), +.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG), +.A_TXPMARESET (A_TXPMARESET_REG), +.A_TXPOLARITY (A_TXPOLARITY_REG), +.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG), +.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG), +.A_TXPRBSSEL (A_TXPRBSSEL_REG), +.A_TXPRECURSOR (A_TXPRECURSOR_REG), +.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG), +.A_TXQPIBIASEN (A_TXQPIBIASEN_REG), +.A_TXRESETSEL (A_TXRESETSEL_REG), +.A_TXSWING (A_TXSWING_REG), +.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG), +.BSR_ENABLE (BSR_ENABLE_REG), +.CAPBYPASS_FORCE (CAPBYPASS_FORCE_REG), +.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG), +.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG), +.CFOK_PWRSVE_EN (CFOK_PWRSVE_EN_REG), +.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG), +.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG), +.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG), +.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG), +.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG), +.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG), +.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG), +.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG), +.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG), +.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG), +.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG), +.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG), +.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG), +.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG), +.CH_HSPMUX (CH_HSPMUX_REG), +.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG), +.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG), +.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG), +.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG), +.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG), +.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG), +.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG), +.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG), +.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG), +.CKCAL_RSVD0 (CKCAL_RSVD0_REG), +.CKCAL_RSVD1 (CKCAL_RSVD1_REG), +.CLK_CORRECT_USE (CLK_CORRECT_USE_REG), +.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG), +.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG), +.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG), +.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG), +.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG), +.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG), +.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG), +.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG), +.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG), +.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG), +.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG), +.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG), +.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG), +.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG), +.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG), +.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG), +.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG), +.COEREG_CLKCTRL (COEREG_CLKCTRL_REG), +.CPLL_CFG0 (CPLL_CFG0_REG), +.CPLL_CFG1 (CPLL_CFG1_REG), +.CPLL_CFG2 (CPLL_CFG2_REG), +.CPLL_CFG3 (CPLL_CFG3_REG), +.CPLL_FBDIV (CPLL_FBDIV_REG), +.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG), +.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG), +.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG), +.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG), +.CSSD_CLK_MASK0 (CSSD_CLK_MASK0_REG), +.CSSD_CLK_MASK1 (CSSD_CLK_MASK1_REG), +.CSSD_REG0 (CSSD_REG0_REG), +.CSSD_REG1 (CSSD_REG1_REG), +.CSSD_REG10 (CSSD_REG10_REG), +.CSSD_REG2 (CSSD_REG2_REG), +.CSSD_REG3 (CSSD_REG3_REG), +.CSSD_REG4 (CSSD_REG4_REG), +.CSSD_REG5 (CSSD_REG5_REG), +.CSSD_REG6 (CSSD_REG6_REG), +.CSSD_REG7 (CSSD_REG7_REG), +.CSSD_REG8 (CSSD_REG8_REG), +.CSSD_REG9 (CSSD_REG9_REG), +.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG), +.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG), +.DDI_CTRL (DDI_CTRL_REG), +.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG), +.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG), +.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG), +.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG), +.DELAY_ELEC (DELAY_ELEC_REG), +.DMONITOR_CFG0 (DMONITOR_CFG0_REG), +.DMONITOR_CFG1 (DMONITOR_CFG1_REG), +.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG), +.ES_CONTROL (ES_CONTROL_REG), +.ES_ERRDET_EN (ES_ERRDET_EN_REG), +.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG), +.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG), +.ES_PRESCALE (ES_PRESCALE_REG), +.ES_QUALIFIER0 (ES_QUALIFIER0_REG), +.ES_QUALIFIER1 (ES_QUALIFIER1_REG), +.ES_QUALIFIER2 (ES_QUALIFIER2_REG), +.ES_QUALIFIER3 (ES_QUALIFIER3_REG), +.ES_QUALIFIER4 (ES_QUALIFIER4_REG), +.ES_QUALIFIER5 (ES_QUALIFIER5_REG), +.ES_QUALIFIER6 (ES_QUALIFIER6_REG), +.ES_QUALIFIER7 (ES_QUALIFIER7_REG), +.ES_QUALIFIER8 (ES_QUALIFIER8_REG), +.ES_QUALIFIER9 (ES_QUALIFIER9_REG), +.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG), +.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG), +.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG), +.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG), +.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG), +.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG), +.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG), +.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG), +.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG), +.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG), +.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG), +.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG), +.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG), +.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG), +.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG), +.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG), +.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG), +.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG), +.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG), +.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG), +.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG), +.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG), +.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG), +.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG), +.GEARBOX_MODE (GEARBOX_MODE_REG), +.GEN_RXUSRCLK (GEN_RXUSRCLK_REG), +.GEN_TXUSRCLK (GEN_TXUSRCLK_REG), +.GT_INSTANTIATED (GT_INSTANTIATED_REG), +.INT_MASK_CFG0 (INT_MASK_CFG0_REG), +.INT_MASK_CFG1 (INT_MASK_CFG1_REG), +.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG), +.LOCAL_MASTER (LOCAL_MASTER_REG), +.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG), +.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG), +.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG), +.LPBK_IND_CTRL0 (LPBK_IND_CTRL0_REG), +.LPBK_IND_CTRL1 (LPBK_IND_CTRL1_REG), +.LPBK_IND_CTRL2 (LPBK_IND_CTRL2_REG), +.LPBK_RG_CTRL (LPBK_RG_CTRL_REG), +.OOBDIVCTL (OOBDIVCTL_REG), +.OOB_PWRUP (OOB_PWRUP_REG), +.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG), +.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG), +.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG), +.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG), +.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG), +.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG), +.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG), +.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG), +.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG), +.PCIE3_CLK_COR_EMPTY_THRSH (PCIE3_CLK_COR_EMPTY_THRSH_REG), +.PCIE3_CLK_COR_FULL_THRSH (PCIE3_CLK_COR_FULL_THRSH_REG), +.PCIE3_CLK_COR_MAX_LAT (PCIE3_CLK_COR_MAX_LAT_REG), +.PCIE3_CLK_COR_MIN_LAT (PCIE3_CLK_COR_MIN_LAT_REG), +.PCIE3_CLK_COR_THRSH_TIMER (PCIE3_CLK_COR_THRSH_TIMER_REG), +.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG), +.PCIE_PLL_SEL_MODE_GEN12 (PCIE_PLL_SEL_MODE_GEN12_REG), +.PCIE_PLL_SEL_MODE_GEN3 (PCIE_PLL_SEL_MODE_GEN3_REG), +.PCIE_PLL_SEL_MODE_GEN4 (PCIE_PLL_SEL_MODE_GEN4_REG), +.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG), +.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG), +.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG), +.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG), +.PCS_PCIE_EN (PCS_PCIE_EN_REG), +.PCS_RSVD0 (PCS_RSVD0_REG), +.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG), +.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG), +.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG), +.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG), +.PROCESS_PAR (PROCESS_PAR_REG), +.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG), +.RCLK_SIPO_DLY_ENB (RCLK_SIPO_DLY_ENB_REG), +.RCLK_SIPO_INV_EN (RCLK_SIPO_INV_EN_REG), +.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG), +.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL_REG), +.RTX_BUF_TERM_CTRL (RTX_BUF_TERM_CTRL_REG), +.RXBUFRESET_TIME (RXBUFRESET_TIME_REG), +.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG), +.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG), +.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG), +.RXBUF_EN (RXBUF_EN_REG), +.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG), +.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG), +.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG), +.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG), +.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG), +.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG), +.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG), +.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG), +.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG), +.RXCDR_CFG0 (RXCDR_CFG0_REG), +.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG), +.RXCDR_CFG1 (RXCDR_CFG1_REG), +.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG), +.RXCDR_CFG2 (RXCDR_CFG2_REG), +.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2_REG), +.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG), +.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4_REG), +.RXCDR_CFG3 (RXCDR_CFG3_REG), +.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2_REG), +.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG), +.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4_REG), +.RXCDR_CFG4 (RXCDR_CFG4_REG), +.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG), +.RXCDR_CFG5 (RXCDR_CFG5_REG), +.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG), +.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG), +.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG), +.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG), +.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG), +.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG), +.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG), +.RXCDR_LOCK_CFG4 (RXCDR_LOCK_CFG4_REG), +.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG), +.RXCFOK_CFG0 (RXCFOK_CFG0_REG), +.RXCFOK_CFG1 (RXCFOK_CFG1_REG), +.RXCFOK_CFG2 (RXCFOK_CFG2_REG), +.RXCKCAL1_IQ_LOOP_RST_CFG (RXCKCAL1_IQ_LOOP_RST_CFG_REG), +.RXCKCAL1_I_LOOP_RST_CFG (RXCKCAL1_I_LOOP_RST_CFG_REG), +.RXCKCAL1_Q_LOOP_RST_CFG (RXCKCAL1_Q_LOOP_RST_CFG_REG), +.RXCKCAL2_DX_LOOP_RST_CFG (RXCKCAL2_DX_LOOP_RST_CFG_REG), +.RXCKCAL2_D_LOOP_RST_CFG (RXCKCAL2_D_LOOP_RST_CFG_REG), +.RXCKCAL2_S_LOOP_RST_CFG (RXCKCAL2_S_LOOP_RST_CFG_REG), +.RXCKCAL2_X_LOOP_RST_CFG (RXCKCAL2_X_LOOP_RST_CFG_REG), +.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG), +.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG), +.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG), +.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG), +.RXDFE_CFG0 (RXDFE_CFG0_REG), +.RXDFE_CFG1 (RXDFE_CFG1_REG), +.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG), +.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG), +.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG), +.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG), +.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG), +.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG), +.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG), +.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG), +.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG), +.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG), +.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG), +.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG), +.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG), +.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG), +.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG), +.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG), +.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG), +.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG), +.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG), +.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG), +.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG), +.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG), +.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG), +.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG), +.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG), +.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG), +.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG), +.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG), +.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG), +.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG), +.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG), +.RXDFE_KH_CFG0 (RXDFE_KH_CFG0_REG), +.RXDFE_KH_CFG1 (RXDFE_KH_CFG1_REG), +.RXDFE_KH_CFG2 (RXDFE_KH_CFG2_REG), +.RXDFE_KH_CFG3 (RXDFE_KH_CFG3_REG), +.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG), +.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG), +.RXDFE_PWR_SAVING (RXDFE_PWR_SAVING_REG), +.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG), +.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG), +.RXDFE_UT_CFG2 (RXDFE_UT_CFG2_REG), +.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG), +.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG), +.RXDLY_CFG (RXDLY_CFG_REG), +.RXDLY_LCFG (RXDLY_LCFG_REG), +.RXELECIDLE_CFG (RXELECIDLE_CFG_REG), +.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG), +.RXGEARBOX_EN (RXGEARBOX_EN_REG), +.RXISCANRESET_TIME (RXISCANRESET_TIME_REG), +.RXLPM_CFG (RXLPM_CFG_REG), +.RXLPM_GC_CFG (RXLPM_GC_CFG_REG), +.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG), +.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG), +.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG), +.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG), +.RXOOB_CFG (RXOOB_CFG_REG), +.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG), +.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG), +.RXOUT_DIV (RXOUT_DIV_REG), +.RXPCSRESET_TIME (RXPCSRESET_TIME_REG), +.RXPHBEACON_CFG (RXPHBEACON_CFG_REG), +.RXPHDLY_CFG (RXPHDLY_CFG_REG), +.RXPHSAMP_CFG (RXPHSAMP_CFG_REG), +.RXPHSLIP_CFG (RXPHSLIP_CFG_REG), +.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG), +.RXPI_AUTO_BW_SEL_BYPASS (RXPI_AUTO_BW_SEL_BYPASS_REG), +.RXPI_CFG0 (RXPI_CFG0_REG), +.RXPI_CFG1 (RXPI_CFG1_REG), +.RXPI_LPM (RXPI_LPM_REG), +.RXPI_SEL_LC (RXPI_SEL_LC_REG), +.RXPI_STARTCODE (RXPI_STARTCODE_REG), +.RXPI_VREFSEL (RXPI_VREFSEL_REG), +.RXPMACLK_SEL (RXPMACLK_SEL_REG), +.RXPMARESET_TIME (RXPMARESET_TIME_REG), +.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG), +.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG), +.RXREFCLKDIV2_SEL (RXREFCLKDIV2_SEL_REG), +.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG), +.RXSLIDE_MODE (RXSLIDE_MODE_REG), +.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG), +.RXSYNC_OVRD (RXSYNC_OVRD_REG), +.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG), +.RX_AFE_CM_EN (RX_AFE_CM_EN_REG), +.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG), +.RX_BUFFER_CFG (RX_BUFFER_CFG_REG), +.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG), +.RX_CLK25_DIV (RX_CLK25_DIV_REG), +.RX_CLKMUX_EN (RX_CLKMUX_EN_REG), +.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG), +.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG), +.RX_CM_BUF_PD (RX_CM_BUF_PD_REG), +.RX_CM_SEL (RX_CM_SEL_REG), +.RX_CM_TRIM (RX_CM_TRIM_REG), +.RX_CTLE3_LPF (RX_CTLE3_LPF_REG), +.RX_DATA_WIDTH (RX_DATA_WIDTH_REG), +.RX_DDI_SEL (RX_DDI_SEL_REG), +.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG), +.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG), +.RX_DFECFOKFCDAC (RX_DFECFOKFCDAC_REG), +.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG), +.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG), +.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG), +.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG), +.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG), +.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG), +.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG), +.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG), +.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG), +.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG), +.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG), +.RX_DIV2_MODE_B (RX_DIV2_MODE_B_REG), +.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG), +.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG), +.RX_EN_HI_LR (RX_EN_HI_LR_REG), +.RX_EXT_RL_CTRL (RX_EXT_RL_CTRL_REG), +.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG), +.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG), +.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG), +.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG), +.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG), +.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG), +.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG), +.RX_PMA_RSV0 (RX_PMA_RSV0_REG), +.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN), +.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG), +.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG), +.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG), +.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG), +.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG), +.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG), +.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG), +.RX_SUM_RESLOAD_CTRL (RX_SUM_RESLOAD_CTRL_REG), +.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG), +.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG), +.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG), +.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG), +.RX_VREG_CTRL (RX_VREG_CTRL_REG), +.RX_VREG_PDB (RX_VREG_PDB_REG), +.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG), +.RX_WIDEMODE_CDR_GEN3 (RX_WIDEMODE_CDR_GEN3_REG), +.RX_WIDEMODE_CDR_GEN4 (RX_WIDEMODE_CDR_GEN4_REG), +.RX_XCLK_SEL (RX_XCLK_SEL_REG), +.RX_XMODE_SEL (RX_XMODE_SEL_REG), +.SAMPLE_CLK_PHASE (SAMPLE_CLK_PHASE_REG), +.SAS_12G_MODE (SAS_12G_MODE_REG), +.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG), +.SATA_BURST_VAL (SATA_BURST_VAL_REG), +.SATA_CPLL_CFG (SATA_CPLL_CFG_REG), +.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG), +.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG), +.SIM_DEVICE (SIM_DEVICE_REG), +.SIM_MODE (SIM_MODE_REG), +.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG), +.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), +.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG), +.SRSTMODE (SRSTMODE_REG), +.TAPDLY_SET_TX (TAPDLY_SET_TX_REG), +.TEMPERATURE_PAR (TEMPERATURE_PAR_REG), +.TERM_RCAL_CFG (TERM_RCAL_CFG_REG), +.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG), +.TRANS_TIME_RATE (TRANS_TIME_RATE_REG), +.TST_RSV0 (TST_RSV0_REG), +.TST_RSV1 (TST_RSV1_REG), +.TXBUF_EN (TXBUF_EN_REG), +.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG), +.TXDLY_CFG (TXDLY_CFG_REG), +.TXDLY_LCFG (TXDLY_LCFG_REG), +.TXDRVBIAS_N (TXDRVBIAS_N_REG), +.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG), +.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG), +.TXGEARBOX_EN (TXGEARBOX_EN_REG), +.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG), +.TXOUT_DIV (TXOUT_DIV_REG), +.TXPCSRESET_TIME (TXPCSRESET_TIME_REG), +.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG), +.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG), +.TXPH_CFG (TXPH_CFG_REG), +.TXPH_CFG2 (TXPH_CFG2_REG), +.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG), +.TXPI_CFG (TXPI_CFG_REG), +.TXPI_CFG0 (TXPI_CFG0_REG), +.TXPI_CFG1 (TXPI_CFG1_REG), +.TXPI_CFG2 (TXPI_CFG2_REG), +.TXPI_CFG3 (TXPI_CFG3_REG), +.TXPI_CFG4 (TXPI_CFG4_REG), +.TXPI_CFG5 (TXPI_CFG5_REG), +.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG), +.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG), +.TXPI_LPM (TXPI_LPM_REG), +.TXPI_PPM (TXPI_PPM_REG), +.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG), +.TXPI_PPM_CFG (TXPI_PPM_CFG_REG), +.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG), +.TXPI_VREFSEL (TXPI_VREFSEL_REG), +.TXPMARESET_TIME (TXPMARESET_TIME_REG), +.TXREFCLKDIV2_SEL (TXREFCLKDIV2_SEL_REG), +.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG), +.TXSYNC_OVRD (TXSYNC_OVRD_REG), +.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG), +.TX_CLK25_DIV (TX_CLK25_DIV_REG), +.TX_CLKMUX_EN (TX_CLKMUX_EN_REG), +.TX_DATA_WIDTH (TX_DATA_WIDTH_REG), +.TX_DCC_LOOP_RST_CFG (TX_DCC_LOOP_RST_CFG_REG), +.TX_DEEMPH0 (TX_DEEMPH0_REG), +.TX_DEEMPH1 (TX_DEEMPH1_REG), +.TX_DEEMPH2 (TX_DEEMPH2_REG), +.TX_DEEMPH3 (TX_DEEMPH3_REG), +.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG), +.TX_DRIVE_MODE (TX_DRIVE_MODE_REG), +.TX_DRVMUX_CTRL (TX_DRVMUX_CTRL_REG), +.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG), +.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG), +.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG), +.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG), +.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG), +.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG), +.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG), +.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG), +.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG), +.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG), +.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG), +.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG), +.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG), +.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG), +.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG), +.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG), +.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG), +.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG), +.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG), +.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG), +.TX_PHICAL_CFG2 (TX_PHICAL_CFG2_REG), +.TX_PI_BIASSET (TX_PI_BIASSET_REG), +.TX_PI_IBIAS_MID (TX_PI_IBIAS_MID_REG), +.TX_PMADATA_OPT (TX_PMADATA_OPT_REG), +.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG), +.TX_PMA_RSV0 (TX_PMA_RSV0_REG), +.TX_PREDRV_CTRL (TX_PREDRV_CTRL_REG), +.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG), +.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN), +.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG), +.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG), +.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG), +.TX_RXDETECT_REF (TX_RXDETECT_REF_REG), +.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG), +.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG), +.TX_SW_MEAS (TX_SW_MEAS_REG), +.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG), +.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG), +.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG), +.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG), +.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG), +.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG), +.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG), +.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG), +.TX_VREG_CTRL (TX_VREG_CTRL_REG), +.TX_VREG_PDB (TX_VREG_PDB_REG), +.TX_VREG_VREFSEL (TX_VREG_VREFSEL_REG), +.TX_XCLK_SEL (TX_XCLK_SEL_REG), +.USB_BOTH_BURST_IDLE (USB_BOTH_BURST_IDLE_REG), +.USB_BURSTMAX_U3WAKE (USB_BURSTMAX_U3WAKE_REG), +.USB_BURSTMIN_U3WAKE (USB_BURSTMIN_U3WAKE_REG), +.USB_CLK_COR_EQ_EN (USB_CLK_COR_EQ_EN_REG), +.USB_EXT_CNTL (USB_EXT_CNTL_REG), +.USB_IDLEMAX_POLLING (USB_IDLEMAX_POLLING_REG), +.USB_IDLEMIN_POLLING (USB_IDLEMIN_POLLING_REG), +.USB_LFPSPING_BURST (USB_LFPSPING_BURST_REG), +.USB_LFPSPOLLING_BURST (USB_LFPSPOLLING_BURST_REG), +.USB_LFPSPOLLING_IDLE_MS (USB_LFPSPOLLING_IDLE_MS_REG), +.USB_LFPSU1EXIT_BURST (USB_LFPSU1EXIT_BURST_REG), +.USB_LFPSU2LPEXIT_BURST_MS (USB_LFPSU2LPEXIT_BURST_MS_REG), +.USB_LFPSU3WAKE_BURST_MS (USB_LFPSU3WAKE_BURST_MS_REG), +.USB_LFPS_TPERIOD (USB_LFPS_TPERIOD_REG), +.USB_LFPS_TPERIOD_ACCURATE (USB_LFPS_TPERIOD_ACCURATE_REG), +.USB_MODE (USB_MODE_REG), +.USB_PCIE_ERR_REP_DIS (USB_PCIE_ERR_REP_DIS_REG), +.USB_PING_SATA_MAX_INIT (USB_PING_SATA_MAX_INIT_REG), +.USB_PING_SATA_MIN_INIT (USB_PING_SATA_MIN_INIT_REG), +.USB_POLL_SATA_MAX_BURST (USB_POLL_SATA_MAX_BURST_REG), +.USB_POLL_SATA_MIN_BURST (USB_POLL_SATA_MIN_BURST_REG), +.USB_RAW_ELEC (USB_RAW_ELEC_REG), +.USB_RXIDLE_P0_CTRL (USB_RXIDLE_P0_CTRL_REG), +.USB_TXIDLE_TUNE_ENABLE (USB_TXIDLE_TUNE_ENABLE_REG), +.USB_U1_SATA_MAX_WAKE (USB_U1_SATA_MAX_WAKE_REG), +.USB_U1_SATA_MIN_WAKE (USB_U1_SATA_MIN_WAKE_REG), +.USB_U2_SAS_MAX_COM (USB_U2_SAS_MAX_COM_REG), +.USB_U2_SAS_MIN_COM (USB_U2_SAS_MIN_COM_REG), +.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG), +.Y_ALL_MODE (Y_ALL_MODE_REG), +.BUFGTCE (BUFGTCE_out), +.BUFGTCEMASK (BUFGTCEMASK_out), +.BUFGTDIV (BUFGTDIV_out), +.BUFGTRESET (BUFGTRESET_out), +.BUFGTRSTMASK (BUFGTRSTMASK_out), +.CPLLFBCLKLOST (CPLLFBCLKLOST_out), +.CPLLLOCK (CPLLLOCK_out), +.CPLLREFCLKLOST (CPLLREFCLKLOST_out), +.CSSDSTOPCLKDONE (CSSDSTOPCLKDONE_out), +.DMONITOROUT (DMONITOROUT_out), +.DMONITOROUTCLK (DMONITOROUTCLK_out), +.DRPDO (DRPDO_out), +.DRPRDY (DRPRDY_out), +.EYESCANDATAERROR (EYESCANDATAERROR_out), +.GTHTXN (GTHTXN_out), +.GTHTXP (GTHTXP_out), +.GTPOWERGOOD (GTPOWERGOOD_out), +.GTREFCLKMONITOR (GTREFCLKMONITOR_out), +.PCIERATEGEN3 (PCIERATEGEN3_out), +.PCIERATEIDLE (PCIERATEIDLE_out), +.PCIERATEQPLLPD (PCIERATEQPLLPD_out), +.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out), +.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out), +.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out), +.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out), +.PCIEUSERRATESTART (PCIEUSERRATESTART_out), +.PCSRSVDOUT (PCSRSVDOUT_out), +.PHYSTATUS (PHYSTATUS_out), +.PINRSRVDAS (PINRSRVDAS_out), +.PMASCANOUT (PMASCANOUT_out), +.POWERPRESENT (POWERPRESENT_out), +.RESETEXCEPTION (RESETEXCEPTION_out), +.RXBUFSTATUS (RXBUFSTATUS_out), +.RXBYTEISALIGNED (RXBYTEISALIGNED_out), +.RXBYTEREALIGN (RXBYTEREALIGN_out), +.RXCDRLOCK (RXCDRLOCK_out), +.RXCDRPHDONE (RXCDRPHDONE_out), +.RXCHANBONDSEQ (RXCHANBONDSEQ_out), +.RXCHANISALIGNED (RXCHANISALIGNED_out), +.RXCHANREALIGN (RXCHANREALIGN_out), +.RXCHBONDO (RXCHBONDO_out), +.RXCKCALDONE (RXCKCALDONE_out), +.RXCLKCORCNT (RXCLKCORCNT_out), +.RXCOMINITDET (RXCOMINITDET_out), +.RXCOMMADET (RXCOMMADET_out), +.RXCOMSASDET (RXCOMSASDET_out), +.RXCOMWAKEDET (RXCOMWAKEDET_out), +.RXCTRL0 (RXCTRL0_out), +.RXCTRL1 (RXCTRL1_out), +.RXCTRL2 (RXCTRL2_out), +.RXCTRL3 (RXCTRL3_out), +.RXDATA (RXDATA_out), +.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out), +.RXDATAVALID (RXDATAVALID_out), +.RXDLYSRESETDONE (RXDLYSRESETDONE_out), +.RXELECIDLE (RXELECIDLE_out), +.RXHEADER (RXHEADER_out), +.RXHEADERVALID (RXHEADERVALID_out), +.RXLFPSTRESETDET (RXLFPSTRESETDET_out), +.RXLFPSU2LPEXITDET (RXLFPSU2LPEXITDET_out), +.RXLFPSU3WAKEDET (RXLFPSU3WAKEDET_out), +.RXMONITOROUT (RXMONITOROUT_out), +.RXOSINTDONE (RXOSINTDONE_out), +.RXOSINTSTARTED (RXOSINTSTARTED_out), +.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out), +.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out), +.RXOUTCLK (RXOUTCLK_out), +.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out), +.RXOUTCLKPCS (RXOUTCLKPCS_out), +.RXPHALIGNDONE (RXPHALIGNDONE_out), +.RXPHALIGNERR (RXPHALIGNERR_out), +.RXPMARESETDONE (RXPMARESETDONE_out), +.RXPRBSERR (RXPRBSERR_out), +.RXPRBSLOCKED (RXPRBSLOCKED_out), +.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out), +.RXQPISENN (RXQPISENN_out), +.RXQPISENP (RXQPISENP_out), +.RXRATEDONE (RXRATEDONE_out), +.RXRECCLKOUT (RXRECCLKOUT_out), +.RXRESETDONE (RXRESETDONE_out), +.RXSLIDERDY (RXSLIDERDY_out), +.RXSLIPDONE (RXSLIPDONE_out), +.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out), +.RXSLIPPMARDY (RXSLIPPMARDY_out), +.RXSTARTOFSEQ (RXSTARTOFSEQ_out), +.RXSTATUS (RXSTATUS_out), +.RXSYNCDONE (RXSYNCDONE_out), +.RXSYNCOUT (RXSYNCOUT_out), +.RXVALID (RXVALID_out), +.SCANOUT (SCANOUT_out), +.TXBUFSTATUS (TXBUFSTATUS_out), +.TXCOMFINISH (TXCOMFINISH_out), +.TXDCCDONE (TXDCCDONE_out), +.TXDLYSRESETDONE (TXDLYSRESETDONE_out), +.TXOUTCLK (TXOUTCLK_out), +.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out), +.TXOUTCLKPCS (TXOUTCLKPCS_out), +.TXPHALIGNDONE (TXPHALIGNDONE_out), +.TXPHINITDONE (TXPHINITDONE_out), +.TXPMARESETDONE (TXPMARESETDONE_out), +.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out), +.TXQPISENN (TXQPISENN_out), +.TXQPISENP (TXQPISENP_out), +.TXRATEDONE (TXRATEDONE_out), +.TXRESETDONE (TXRESETDONE_out), +.TXSYNCDONE (TXSYNCDONE_out), +.TXSYNCOUT (TXSYNCOUT_out), +.BSR_SERIAL (BSR_SERIAL_in), +.CDRSTEPDIR (CDRSTEPDIR_in), +.CDRSTEPSQ (CDRSTEPSQ_in), +.CDRSTEPSX (CDRSTEPSX_in), +.CFGRESET (CFGRESET_in), +.CLKRSVD0 (CLKRSVD0_in), +.CLKRSVD1 (CLKRSVD1_in), +.CPLLFREQLOCK (CPLLFREQLOCK_in), +.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in), +.CPLLLOCKEN (CPLLLOCKEN_in), +.CPLLPD (CPLLPD_in), +.CPLLREFCLKSEL (CPLLREFCLKSEL_in), +.CPLLRESET (CPLLRESET_in), +.CSSDRSTB (CSSDRSTB_in), +.CSSDSTOPCLK (CSSDSTOPCLK_in), +.DMONFIFORESET (DMONFIFORESET_in), +.DMONITORCLK (DMONITORCLK_in), +.DRPADDR (DRPADDR_in), +.DRPCLK (DRPCLK_in), +.DRPDI (DRPDI_in), +.DRPEN (DRPEN_in), +.DRPRST (DRPRST_in), +.DRPWE (DRPWE_in), +.EYESCANRESET (EYESCANRESET_in), +.EYESCANTRIGGER (EYESCANTRIGGER_in), +.FREQOS (FREQOS_in), +.GTGREFCLK (GTGREFCLK_in), +.GTHRXN (GTHRXN_in), +.GTHRXP (GTHRXP_in), +.GTNORTHREFCLK0 (GTNORTHREFCLK0_in), +.GTNORTHREFCLK1 (GTNORTHREFCLK1_in), +.GTREFCLK0 (GTREFCLK0_in), +.GTREFCLK1 (GTREFCLK1_in), +.GTRSVD (GTRSVD_in), +.GTRXRESET (GTRXRESET_in), +.GTRXRESETSEL (GTRXRESETSEL_in), +.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in), +.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in), +.GTTXRESET (GTTXRESET_in), +.GTTXRESETSEL (GTTXRESETSEL_in), +.INCPCTRL (INCPCTRL_in), +.LOOPBACK (LOOPBACK_in), +.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in), +.PCIERSTIDLE (PCIERSTIDLE_in), +.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in), +.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in), +.PCSRSVDIN (PCSRSVDIN_in), +.PMASCANCLK0 (PMASCANCLK0_in), +.PMASCANCLK1 (PMASCANCLK1_in), +.PMASCANCLK2 (PMASCANCLK2_in), +.PMASCANCLK3 (PMASCANCLK3_in), +.PMASCANCLK4 (PMASCANCLK4_in), +.PMASCANCLK5 (PMASCANCLK5_in), +.PMASCANCLK6 (PMASCANCLK6_in), +.PMASCANCLK7 (PMASCANCLK7_in), +.PMASCANCLK8 (PMASCANCLK8_in), +.PMASCANENB (PMASCANENB_in), +.PMASCANIN (PMASCANIN_in), +.PMASCANMODEB (PMASCANMODEB_in), +.PMASCANRSTEN (PMASCANRSTEN_in), +.QPLL0CLK (QPLL0CLK_in), +.QPLL0FREQLOCK (QPLL0FREQLOCK_in), +.QPLL0REFCLK (QPLL0REFCLK_in), +.QPLL1CLK (QPLL1CLK_in), +.QPLL1FREQLOCK (QPLL1FREQLOCK_in), +.QPLL1REFCLK (QPLL1REFCLK_in), +.RESETOVRD (RESETOVRD_in), +.RX8B10BEN (RX8B10BEN_in), +.RXAFECFOKEN (RXAFECFOKEN_in), +.RXBUFRESET (RXBUFRESET_in), +.RXCDRFREQRESET (RXCDRFREQRESET_in), +.RXCDRHOLD (RXCDRHOLD_in), +.RXCDROVRDEN (RXCDROVRDEN_in), +.RXCDRRESET (RXCDRRESET_in), +.RXCHBONDEN (RXCHBONDEN_in), +.RXCHBONDI (RXCHBONDI_in), +.RXCHBONDLEVEL (RXCHBONDLEVEL_in), +.RXCHBONDMASTER (RXCHBONDMASTER_in), +.RXCHBONDSLAVE (RXCHBONDSLAVE_in), +.RXCKCALRESET (RXCKCALRESET_in), +.RXCKCALSTART (RXCKCALSTART_in), +.RXCOMMADETEN (RXCOMMADETEN_in), +.RXDFEAGCCTRL (RXDFEAGCCTRL_in), +.RXDFEAGCHOLD (RXDFEAGCHOLD_in), +.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in), +.RXDFECFOKFCNUM (RXDFECFOKFCNUM_in), +.RXDFECFOKFEN (RXDFECFOKFEN_in), +.RXDFECFOKFPULSE (RXDFECFOKFPULSE_in), +.RXDFECFOKHOLD (RXDFECFOKHOLD_in), +.RXDFECFOKOVREN (RXDFECFOKOVREN_in), +.RXDFEKHHOLD (RXDFEKHHOLD_in), +.RXDFEKHOVRDEN (RXDFEKHOVRDEN_in), +.RXDFELFHOLD (RXDFELFHOLD_in), +.RXDFELFOVRDEN (RXDFELFOVRDEN_in), +.RXDFELPMRESET (RXDFELPMRESET_in), +.RXDFETAP10HOLD (RXDFETAP10HOLD_in), +.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in), +.RXDFETAP11HOLD (RXDFETAP11HOLD_in), +.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in), +.RXDFETAP12HOLD (RXDFETAP12HOLD_in), +.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in), +.RXDFETAP13HOLD (RXDFETAP13HOLD_in), +.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in), +.RXDFETAP14HOLD (RXDFETAP14HOLD_in), +.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in), +.RXDFETAP15HOLD (RXDFETAP15HOLD_in), +.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in), +.RXDFETAP2HOLD (RXDFETAP2HOLD_in), +.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in), +.RXDFETAP3HOLD (RXDFETAP3HOLD_in), +.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in), +.RXDFETAP4HOLD (RXDFETAP4HOLD_in), +.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in), +.RXDFETAP5HOLD (RXDFETAP5HOLD_in), +.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in), +.RXDFETAP6HOLD (RXDFETAP6HOLD_in), +.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in), +.RXDFETAP7HOLD (RXDFETAP7HOLD_in), +.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in), +.RXDFETAP8HOLD (RXDFETAP8HOLD_in), +.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in), +.RXDFETAP9HOLD (RXDFETAP9HOLD_in), +.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in), +.RXDFEUTHOLD (RXDFEUTHOLD_in), +.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in), +.RXDFEVPHOLD (RXDFEVPHOLD_in), +.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in), +.RXDFEXYDEN (RXDFEXYDEN_in), +.RXDLYBYPASS (RXDLYBYPASS_in), +.RXDLYEN (RXDLYEN_in), +.RXDLYOVRDEN (RXDLYOVRDEN_in), +.RXDLYSRESET (RXDLYSRESET_in), +.RXELECIDLEMODE (RXELECIDLEMODE_in), +.RXEQTRAINING (RXEQTRAINING_in), +.RXGEARBOXSLIP (RXGEARBOXSLIP_in), +.RXLATCLK (RXLATCLK_in), +.RXLPMEN (RXLPMEN_in), +.RXLPMGCHOLD (RXLPMGCHOLD_in), +.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in), +.RXLPMHFHOLD (RXLPMHFHOLD_in), +.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in), +.RXLPMLFHOLD (RXLPMLFHOLD_in), +.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in), +.RXLPMOSHOLD (RXLPMOSHOLD_in), +.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in), +.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in), +.RXMONITORSEL (RXMONITORSEL_in), +.RXOOBRESET (RXOOBRESET_in), +.RXOSCALRESET (RXOSCALRESET_in), +.RXOSHOLD (RXOSHOLD_in), +.RXOSOVRDEN (RXOSOVRDEN_in), +.RXOUTCLKSEL (RXOUTCLKSEL_in), +.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in), +.RXPCSRESET (RXPCSRESET_in), +.RXPD (RXPD_in), +.RXPHALIGN (RXPHALIGN_in), +.RXPHALIGNEN (RXPHALIGNEN_in), +.RXPHDLYPD (RXPHDLYPD_in), +.RXPHDLYRESET (RXPHDLYRESET_in), +.RXPHOVRDEN (RXPHOVRDEN_in), +.RXPLLCLKSEL (RXPLLCLKSEL_in), +.RXPMARESET (RXPMARESET_in), +.RXPOLARITY (RXPOLARITY_in), +.RXPRBSCNTRESET (RXPRBSCNTRESET_in), +.RXPRBSSEL (RXPRBSSEL_in), +.RXPROGDIVRESET (RXPROGDIVRESET_in), +.RXQPIEN (RXQPIEN_in), +.RXRATE (RXRATE_in), +.RXRATEMODE (RXRATEMODE_in), +.RXSLIDE (RXSLIDE_in), +.RXSLIPOUTCLK (RXSLIPOUTCLK_in), +.RXSLIPPMA (RXSLIPPMA_in), +.RXSYNCALLIN (RXSYNCALLIN_in), +.RXSYNCIN (RXSYNCIN_in), +.RXSYNCMODE (RXSYNCMODE_in), +.RXSYSCLKSEL (RXSYSCLKSEL_in), +.RXTERMINATION (RXTERMINATION_in), +.RXUSERRDY (RXUSERRDY_in), +.RXUSRCLK (RXUSRCLK_in), +.RXUSRCLK2 (RXUSRCLK2_in), +.SARCCLK (SARCCLK_in), +.SCANCLK (SCANCLK_in), +.SCANENB (SCANENB_in), +.SCANIN (SCANIN_in), +.SCANMODEB (SCANMODEB_in), +.SCANRSTB (SCANRSTB_in), +.SCANRSTEN (SCANRSTEN_in), +.SIGVALIDCLK (SIGVALIDCLK_in), +.TSTCLK0 (TSTCLK0_in), +.TSTCLK1 (TSTCLK1_in), +.TSTIN (TSTIN_in), +.TSTPD (TSTPD_in), +.TSTPDOVRDB (TSTPDOVRDB_in), +.TX8B10BBYPASS (TX8B10BBYPASS_in), +.TX8B10BEN (TX8B10BEN_in), +.TXCOMINIT (TXCOMINIT_in), +.TXCOMSAS (TXCOMSAS_in), +.TXCOMWAKE (TXCOMWAKE_in), +.TXCTRL0 (TXCTRL0_in), +.TXCTRL1 (TXCTRL1_in), +.TXCTRL2 (TXCTRL2_in), +.TXDATA (TXDATA_in), +.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in), +.TXDCCFORCESTART (TXDCCFORCESTART_in), +.TXDCCRESET (TXDCCRESET_in), +.TXDEEMPH (TXDEEMPH_in), +.TXDETECTRX (TXDETECTRX_in), +.TXDIFFCTRL (TXDIFFCTRL_in), +.TXDLYBYPASS (TXDLYBYPASS_in), +.TXDLYEN (TXDLYEN_in), +.TXDLYHOLD (TXDLYHOLD_in), +.TXDLYOVRDEN (TXDLYOVRDEN_in), +.TXDLYSRESET (TXDLYSRESET_in), +.TXDLYUPDOWN (TXDLYUPDOWN_in), +.TXELECIDLE (TXELECIDLE_in), +.TXHEADER (TXHEADER_in), +.TXINHIBIT (TXINHIBIT_in), +.TXLATCLK (TXLATCLK_in), +.TXLFPSTRESET (TXLFPSTRESET_in), +.TXLFPSU2LPEXIT (TXLFPSU2LPEXIT_in), +.TXLFPSU3WAKE (TXLFPSU3WAKE_in), +.TXMAINCURSOR (TXMAINCURSOR_in), +.TXMARGIN (TXMARGIN_in), +.TXMUXDCDEXHOLD (TXMUXDCDEXHOLD_in), +.TXMUXDCDORWREN (TXMUXDCDORWREN_in), +.TXONESZEROS (TXONESZEROS_in), +.TXOUTCLKSEL (TXOUTCLKSEL_in), +.TXPCSRESET (TXPCSRESET_in), +.TXPD (TXPD_in), +.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in), +.TXPHALIGN (TXPHALIGN_in), +.TXPHALIGNEN (TXPHALIGNEN_in), +.TXPHDLYPD (TXPHDLYPD_in), +.TXPHDLYRESET (TXPHDLYRESET_in), +.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in), +.TXPHINIT (TXPHINIT_in), +.TXPHOVRDEN (TXPHOVRDEN_in), +.TXPIPPMEN (TXPIPPMEN_in), +.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in), +.TXPIPPMPD (TXPIPPMPD_in), +.TXPIPPMSEL (TXPIPPMSEL_in), +.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in), +.TXPISOPD (TXPISOPD_in), +.TXPLLCLKSEL (TXPLLCLKSEL_in), +.TXPMARESET (TXPMARESET_in), +.TXPOLARITY (TXPOLARITY_in), +.TXPOSTCURSOR (TXPOSTCURSOR_in), +.TXPRBSFORCEERR (TXPRBSFORCEERR_in), +.TXPRBSSEL (TXPRBSSEL_in), +.TXPRECURSOR (TXPRECURSOR_in), +.TXPROGDIVRESET (TXPROGDIVRESET_in), +.TXQPIBIASEN (TXQPIBIASEN_in), +.TXQPIWEAKPUP (TXQPIWEAKPUP_in), +.TXRATE (TXRATE_in), +.TXRATEMODE (TXRATEMODE_in), +.TXSEQUENCE (TXSEQUENCE_in), +.TXSWING (TXSWING_in), +.TXSYNCALLIN (TXSYNCALLIN_in), +.TXSYNCIN (TXSYNCIN_in), +.TXSYNCMODE (TXSYNCMODE_in), +.TXSYSCLKSEL (TXSYSCLKSEL_in), +.TXUSERRDY (TXUSERRDY_in), +.TXUSRCLK (TXUSRCLK_in), +.TXUSRCLK2 (TXUSRCLK2_in), +.GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0); + (DRPCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (QPLL0REFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (QPLL0REFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (QPLL0REFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (QPLL0REFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (QPLL1REFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (QPLL1REFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (QPLL1REFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (QPLL1REFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (RXUSRCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXPHALIGNERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => DMONITOROUTCLK) = (100:100:100, 100:100:100); + (RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPHALIGNERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100); + (TXUSRCLK => BUFGTRSTMASK[1]) = (0:0:0, 0:0:0); + (TXUSRCLK => DMONITOROUTCLK) = (0:0:0, 0:0:0); + (TXUSRCLK => RXPHALIGNERR) = (0:0:0, 0:0:0); + (TXUSRCLK2 => DMONITOROUTCLK) = (100:100:100, 100:100:100); + (TXUSRCLK2 => RXPHALIGNERR) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK2, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTHE4_COMMON.v b/verilog/src/unisims/GTHE4_COMMON.v new file mode 100644 index 0000000..226a783 --- /dev/null +++ b/verilog/src/unisims/GTHE4_COMMON.v @@ -0,0 +1,1223 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver for UltraScale+ devices +// /___/ /\ Filename : GTHE4_COMMON.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTHE4_COMMON #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1, + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1, + parameter [0:0] AEN_SDM0TOGGLE = 1'b0, + parameter [0:0] AEN_SDM1TOGGLE = 1'b0, + parameter [0:0] A_SDM0TOGGLE = 1'b0, + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000, + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000, + parameter [0:0] A_SDM1TOGGLE = 1'b0, + parameter [15:0] BIAS_CFG0 = 16'h0000, + parameter [15:0] BIAS_CFG1 = 16'h0000, + parameter [15:0] BIAS_CFG2 = 16'h0000, + parameter [15:0] BIAS_CFG3 = 16'h0000, + parameter [15:0] BIAS_CFG4 = 16'h0000, + parameter [15:0] BIAS_CFG_RSVD = 16'h0000, + parameter [15:0] COMMON_CFG0 = 16'h0000, + parameter [15:0] COMMON_CFG1 = 16'h0000, + parameter [15:0] POR_CFG = 16'h0000, + parameter [15:0] PPF0_CFG = 16'h0F00, + parameter [15:0] PPF1_CFG = 16'h0F00, + parameter QPLL0CLKOUT_RATE = "FULL", + parameter [15:0] QPLL0_CFG0 = 16'h391C, + parameter [15:0] QPLL0_CFG1 = 16'h0000, + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL0_CFG2 = 16'h0F80, + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80, + parameter [15:0] QPLL0_CFG3 = 16'h0120, + parameter [15:0] QPLL0_CFG4 = 16'h0002, + parameter [9:0] QPLL0_CP = 10'b0000011111, + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111, + parameter integer QPLL0_FBDIV = 66, + parameter integer QPLL0_FBDIV_G3 = 80, + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL0_LPF = 10'b1011111111, + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111, + parameter [0:0] QPLL0_PCI_EN = 1'b0, + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0, + parameter integer QPLL0_REFCLK_DIV = 1, + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040, + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000, + parameter QPLL1CLKOUT_RATE = "FULL", + parameter [15:0] QPLL1_CFG0 = 16'h691C, + parameter [15:0] QPLL1_CFG1 = 16'h0020, + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL1_CFG2 = 16'h0F80, + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80, + parameter [15:0] QPLL1_CFG3 = 16'h0120, + parameter [15:0] QPLL1_CFG4 = 16'h0002, + parameter [9:0] QPLL1_CP = 10'b0000011111, + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111, + parameter integer QPLL1_FBDIV = 66, + parameter integer QPLL1_FBDIV_G3 = 80, + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL1_LPF = 10'b1011111111, + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111, + parameter [0:0] QPLL1_PCI_EN = 1'b0, + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0, + parameter integer QPLL1_REFCLK_DIV = 1, + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000, + parameter [15:0] RSVD_ATTR0 = 16'h0000, + parameter [15:0] RSVD_ATTR1 = 16'h0000, + parameter [15:0] RSVD_ATTR2 = 16'h0000, + parameter [15:0] RSVD_ATTR3 = 16'h0000, + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00, + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00, + parameter [0:0] SARC_ENB = 1'b0, + parameter [0:0] SARC_SEL = 1'b0, + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000, + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SIM_MODE = "FAST", + parameter SIM_RESET_SPEEDUP = "TRUE" +)( + output [15:0] DRPDO, + output DRPRDY, + output [7:0] PMARSVDOUT0, + output [7:0] PMARSVDOUT1, + output QPLL0FBCLKLOST, + output QPLL0LOCK, + output QPLL0OUTCLK, + output QPLL0OUTREFCLK, + output QPLL0REFCLKLOST, + output QPLL1FBCLKLOST, + output QPLL1LOCK, + output QPLL1OUTCLK, + output QPLL1OUTREFCLK, + output QPLL1REFCLKLOST, + output [7:0] QPLLDMONITOR0, + output [7:0] QPLLDMONITOR1, + output REFCLKOUTMONITOR0, + output REFCLKOUTMONITOR1, + output [1:0] RXRECCLK0SEL, + output [1:0] RXRECCLK1SEL, + output [3:0] SDM0FINALOUT, + output [14:0] SDM0TESTDATA, + output [3:0] SDM1FINALOUT, + output [14:0] SDM1TESTDATA, + output [9:0] TCONGPO, + output TCONRSVDOUT0, + + input BGBYPASSB, + input BGMONITORENB, + input BGPDB, + input [4:0] BGRCALOVRD, + input BGRCALOVRDENB, + input [15:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input GTGREFCLK0, + input GTGREFCLK1, + input GTNORTHREFCLK00, + input GTNORTHREFCLK01, + input GTNORTHREFCLK10, + input GTNORTHREFCLK11, + input GTREFCLK00, + input GTREFCLK01, + input GTREFCLK10, + input GTREFCLK11, + input GTSOUTHREFCLK00, + input GTSOUTHREFCLK01, + input GTSOUTHREFCLK10, + input GTSOUTHREFCLK11, + input [2:0] PCIERATEQPLL0, + input [2:0] PCIERATEQPLL1, + input [7:0] PMARSVD0, + input [7:0] PMARSVD1, + input QPLL0CLKRSVD0, + input QPLL0CLKRSVD1, + input [7:0] QPLL0FBDIV, + input QPLL0LOCKDETCLK, + input QPLL0LOCKEN, + input QPLL0PD, + input [2:0] QPLL0REFCLKSEL, + input QPLL0RESET, + input QPLL1CLKRSVD0, + input QPLL1CLKRSVD1, + input [7:0] QPLL1FBDIV, + input QPLL1LOCKDETCLK, + input QPLL1LOCKEN, + input QPLL1PD, + input [2:0] QPLL1REFCLKSEL, + input QPLL1RESET, + input [7:0] QPLLRSVD1, + input [4:0] QPLLRSVD2, + input [4:0] QPLLRSVD3, + input [7:0] QPLLRSVD4, + input RCALENB, + input [24:0] SDM0DATA, + input SDM0RESET, + input SDM0TOGGLE, + input [1:0] SDM0WIDTH, + input [24:0] SDM1DATA, + input SDM1RESET, + input SDM1TOGGLE, + input [1:0] SDM1WIDTH, + input [9:0] TCONGPI, + input TCONPOWERUP, + input [1:0] TCONRESET, + input [1:0] TCONRSVDIN1 +); + +// define constants + localparam MODULE_NAME = "GTHE4_COMMON"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "GTHE4_COMMON_dr.v" +`else + localparam [0:0] AEN_QPLL0_FBDIV_REG = AEN_QPLL0_FBDIV; + localparam [0:0] AEN_QPLL1_FBDIV_REG = AEN_QPLL1_FBDIV; + localparam [0:0] AEN_SDM0TOGGLE_REG = AEN_SDM0TOGGLE; + localparam [0:0] AEN_SDM1TOGGLE_REG = AEN_SDM1TOGGLE; + localparam [0:0] A_SDM0TOGGLE_REG = A_SDM0TOGGLE; + localparam [8:0] A_SDM1DATA_HIGH_REG = A_SDM1DATA_HIGH; + localparam [15:0] A_SDM1DATA_LOW_REG = A_SDM1DATA_LOW; + localparam [0:0] A_SDM1TOGGLE_REG = A_SDM1TOGGLE; + localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0; + localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1; + localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2; + localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3; + localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4; + localparam [15:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD; + localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0; + localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1; + localparam [15:0] POR_CFG_REG = POR_CFG; + localparam [15:0] PPF0_CFG_REG = PPF0_CFG; + localparam [15:0] PPF1_CFG_REG = PPF1_CFG; + localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE; + localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0; + localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1; + localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3; + localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2; + localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3; + localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3; + localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4; + localparam [9:0] QPLL0_CP_REG = QPLL0_CP; + localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3; + localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV; + localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3; + localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0; + localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1; + localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG; + localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3; + localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF; + localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3; + localparam [0:0] QPLL0_PCI_EN_REG = QPLL0_PCI_EN; + localparam [0:0] QPLL0_RATE_SW_USE_DRP_REG = QPLL0_RATE_SW_USE_DRP; + localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV; + localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0; + localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1; + localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2; + localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE; + localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0; + localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1; + localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3; + localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2; + localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3; + localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3; + localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4; + localparam [9:0] QPLL1_CP_REG = QPLL1_CP; + localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3; + localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV; + localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3; + localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0; + localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1; + localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG; + localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3; + localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF; + localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3; + localparam [0:0] QPLL1_PCI_EN_REG = QPLL1_PCI_EN; + localparam [0:0] QPLL1_RATE_SW_USE_DRP_REG = QPLL1_RATE_SW_USE_DRP; + localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV; + localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0; + localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1; + localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2; + localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0; + localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1; + localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2; + localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3; + localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL; + localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL; + localparam [0:0] SARC_ENB_REG = SARC_ENB; + localparam [0:0] SARC_SEL_REG = SARC_SEL; + localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0; + localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1; + localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0; + localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1; + localparam [160:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [48:1] SIM_MODE_REG = SIM_MODE; + localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; +`endif + + localparam [0:0] AEN_BGBS0_REG = 1'b0; + localparam [0:0] AEN_BGBS1_REG = 1'b0; + localparam [0:0] AEN_MASTER0_REG = 1'b0; + localparam [0:0] AEN_MASTER1_REG = 1'b0; + localparam [0:0] AEN_PD0_REG = 1'b0; + localparam [0:0] AEN_PD1_REG = 1'b0; + localparam [0:0] AEN_QPLL0_REG = 1'b0; + localparam [0:0] AEN_QPLL1_REG = 1'b0; + localparam [0:0] AEN_REFCLK0_REG = 1'b0; + localparam [0:0] AEN_REFCLK1_REG = 1'b0; + localparam [0:0] AEN_RESET0_REG = 1'b0; + localparam [0:0] AEN_RESET1_REG = 1'b0; + localparam [0:0] AEN_SDM0DATA_REG = 1'b0; + localparam [0:0] AEN_SDM0RESET_REG = 1'b0; + localparam [0:0] AEN_SDM0WIDTH_REG = 1'b0; + localparam [0:0] AEN_SDM1DATA_REG = 1'b0; + localparam [0:0] AEN_SDM1RESET_REG = 1'b0; + localparam [0:0] AEN_SDM1WIDTH_REG = 1'b0; + localparam [3:0] AQDMUXSEL1_REG = 4'b0000; + localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000; + localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000; + localparam [0:0] A_BGMONITOREN_REG = 1'b0; + localparam [0:0] A_BGPD_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD0_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD1_REG = 1'b0; + localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL0PD_REG = 1'b0; + localparam [0:0] A_QPLL0RESET_REG = 1'b0; + localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL1PD_REG = 1'b0; + localparam [0:0] A_QPLL1RESET_REG = 1'b0; + localparam [8:0] A_SDM0DATA_HIGH_REG = 9'b000000000; + localparam [15:0] A_SDM0DATA_LOW_REG = 16'b0000000000000000; + localparam [0:0] A_SDM0RESET_REG = 1'b0; + localparam [0:0] A_SDM1RESET_REG = 1'b0; + localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00; + localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00; + localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1; + localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000; + localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000; + localparam [0:0] RCALSAP_TESTEN_REG = 1'b0; + localparam [0:0] RCAL_APROBE_REG = 1'b0; + localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0; + localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0; + localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CSSDSTOPCLKDONE0_out; + wire CSSDSTOPCLKDONE1_out; + wire DRPRDY_out; + wire QPLL0FBCLKLOST_out; + wire QPLL0LOCK_out; + wire QPLL0OUTCLK_out; + wire QPLL0OUTREFCLK_out; + wire QPLL0REFCLKLOST_out; + wire QPLL1FBCLKLOST_out; + wire QPLL1LOCK_out; + wire QPLL1OUTCLK_out; + wire QPLL1OUTREFCLK_out; + wire QPLL1REFCLKLOST_out; + wire REFCLKOUTMONITOR0_out; + wire REFCLKOUTMONITOR1_out; + wire TCONRSVDOUT0_out; + wire TCONTDO_out; + wire [14:0] SDM0TESTDATA_out; + wire [14:0] SDM1TESTDATA_out; + wire [15:0] DRPDO_out; + wire [1:0] RXRECCLK0SEL_out; + wire [1:0] RXRECCLK1SEL_out; + wire [3:0] SARCCLK_out; + wire [3:0] SDM0FINALOUT_out; + wire [3:0] SDM1FINALOUT_out; + wire [7:0] PMARSVDOUT0_out; + wire [7:0] PMARSVDOUT1_out; + wire [7:0] QPLLDMONITOR0_out; + wire [7:0] QPLLDMONITOR1_out; + wire [9:0] PMASCANOUT_out; + wire [9:0] TCONGPO_out; + + wire BGBYPASSB_in; + wire BGMONITORENB_in; + wire BGPDB_in; + wire BGRCALOVRDENB_in; + wire CSSDSTOPCLK0_in; + wire CSSDSTOPCLK1_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire GTGREFCLK0_in; + wire GTGREFCLK1_in; + wire GTNORTHREFCLK00_in; + wire GTNORTHREFCLK01_in; + wire GTNORTHREFCLK10_in; + wire GTNORTHREFCLK11_in; + wire GTREFCLK00_in; + wire GTREFCLK01_in; + wire GTREFCLK10_in; + wire GTREFCLK11_in; + wire GTSOUTHREFCLK00_in; + wire GTSOUTHREFCLK01_in; + wire GTSOUTHREFCLK10_in; + wire GTSOUTHREFCLK11_in; + wire PMASCANENB_in; + wire QDPMASCANMODEB_in; + wire QDPMASCANRSTEN_in; + wire QPLL0CLKRSVD0_in; + wire QPLL0CLKRSVD1_in; + wire QPLL0LOCKDETCLK_in; + wire QPLL0LOCKEN_in; + wire QPLL0PD_in; + wire QPLL0RESET_in; + wire QPLL1CLKRSVD0_in; + wire QPLL1CLKRSVD1_in; + wire QPLL1LOCKDETCLK_in; + wire QPLL1LOCKEN_in; + wire QPLL1PD_in; + wire QPLL1RESET_in; + wire RCALENB_in; + wire SDM0RESET_in; + wire SDM0TOGGLE_in; + wire SDM1RESET_in; + wire SDM1TOGGLE_in; + wire TCONMBISTMODE_in; + wire TCONPOWERUP_in; + wire TCONTCK_in; + wire TCONTDI_in; + wire TCONTMS_in; + wire TCONTRST_in; + wire [15:0] DRPADDR_in; + wire [15:0] DRPDI_in; + wire [1:0] SDM0WIDTH_in; + wire [1:0] SDM1WIDTH_in; + wire [1:0] TCONRESET_in; + wire [1:0] TCONRSVDIN1_in; + wire [1:0] TCONSPD_in; + wire [24:0] SDM0DATA_in; + wire [24:0] SDM1DATA_in; + wire [2:0] PCIERATEQPLL0_in; + wire [2:0] PCIERATEQPLL1_in; + wire [2:0] QPLL0REFCLKSEL_in; + wire [2:0] QPLL1REFCLKSEL_in; + wire [3:0] RXRECCLK_in; + wire [4:0] BGRCALOVRD_in; + wire [4:0] QPLLRSVD2_in; + wire [4:0] QPLLRSVD3_in; + wire [4:0] TCONRSVDIN0_in; + wire [7:0] PMARSVD0_in; + wire [7:0] PMARSVD1_in; + wire [7:0] QPLL0FBDIV_in; + wire [7:0] QPLL1FBDIV_in; + wire [7:0] QPLLRSVD1_in; + wire [7:0] QPLLRSVD4_in; + wire [9:0] PMASCANCLK_in; + wire [9:0] PMASCANIN_in; + wire [9:0] TCONGPI_in; + +`ifdef XIL_TIMING + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire [15:0] DRPADDR_delay; + wire [15:0] DRPDI_delay; +`endif + + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign PMARSVDOUT0 = PMARSVDOUT0_out; + assign PMARSVDOUT1 = PMARSVDOUT1_out; + assign QPLL0FBCLKLOST = QPLL0FBCLKLOST_out; + assign QPLL0LOCK = QPLL0LOCK_out; + assign QPLL0OUTCLK = QPLL0OUTCLK_out; + assign QPLL0OUTREFCLK = QPLL0OUTREFCLK_out; + assign QPLL0REFCLKLOST = QPLL0REFCLKLOST_out; + assign QPLL1FBCLKLOST = QPLL1FBCLKLOST_out; + assign QPLL1LOCK = QPLL1LOCK_out; + assign QPLL1OUTCLK = QPLL1OUTCLK_out; + assign QPLL1OUTREFCLK = QPLL1OUTREFCLK_out; + assign QPLL1REFCLKLOST = QPLL1REFCLKLOST_out; + assign QPLLDMONITOR0 = QPLLDMONITOR0_out; + assign QPLLDMONITOR1 = QPLLDMONITOR1_out; + assign REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_out; + assign REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_out; + assign RXRECCLK0SEL = RXRECCLK0SEL_out; + assign RXRECCLK1SEL = RXRECCLK1SEL_out; + assign SDM0FINALOUT = SDM0FINALOUT_out; + assign SDM0TESTDATA = SDM0TESTDATA_out; + assign SDM1FINALOUT = SDM1FINALOUT_out; + assign SDM1TESTDATA = SDM1TESTDATA_out; + assign TCONGPO = TCONGPO_out; + assign TCONRSVDOUT0 = TCONRSVDOUT0_out; + +`ifdef XIL_TIMING + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR_delay[10]; // rv 0 + assign DRPADDR_in[11] = (DRPADDR[11] !== 1'bz) && DRPADDR_delay[11]; // rv 0 + assign DRPADDR_in[12] = (DRPADDR[12] !== 1'bz) && DRPADDR_delay[12]; // rv 0 + assign DRPADDR_in[13] = (DRPADDR[13] !== 1'bz) && DRPADDR_delay[13]; // rv 0 + assign DRPADDR_in[14] = (DRPADDR[14] !== 1'bz) && DRPADDR_delay[14]; // rv 0 + assign DRPADDR_in[15] = (DRPADDR[15] !== 1'bz) && DRPADDR_delay[15]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 +`else + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR[10]; // rv 0 + assign DRPADDR_in[11] = (DRPADDR[11] !== 1'bz) && DRPADDR[11]; // rv 0 + assign DRPADDR_in[12] = (DRPADDR[12] !== 1'bz) && DRPADDR[12]; // rv 0 + assign DRPADDR_in[13] = (DRPADDR[13] !== 1'bz) && DRPADDR[13]; // rv 0 + assign DRPADDR_in[14] = (DRPADDR[14] !== 1'bz) && DRPADDR[14]; // rv 0 + assign DRPADDR_in[15] = (DRPADDR[15] !== 1'bz) && DRPADDR[15]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 +`endif + + assign BGBYPASSB_in = BGBYPASSB; + assign BGMONITORENB_in = BGMONITORENB; + assign BGPDB_in = BGPDB; + assign BGRCALOVRDENB_in = (BGRCALOVRDENB === 1'bz) || BGRCALOVRDENB; // rv 1 + assign BGRCALOVRD_in = BGRCALOVRD; + assign GTGREFCLK0_in = GTGREFCLK0; + assign GTGREFCLK1_in = GTGREFCLK1; + assign GTNORTHREFCLK00_in = GTNORTHREFCLK00; + assign GTNORTHREFCLK01_in = GTNORTHREFCLK01; + assign GTNORTHREFCLK10_in = GTNORTHREFCLK10; + assign GTNORTHREFCLK11_in = GTNORTHREFCLK11; + assign GTREFCLK00_in = GTREFCLK00; + assign GTREFCLK01_in = GTREFCLK01; + assign GTREFCLK10_in = GTREFCLK10; + assign GTREFCLK11_in = GTREFCLK11; + assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00; + assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01; + assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10; + assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11; + assign PCIERATEQPLL0_in[0] = (PCIERATEQPLL0[0] !== 1'bz) && PCIERATEQPLL0[0]; // rv 0 + assign PCIERATEQPLL0_in[1] = (PCIERATEQPLL0[1] !== 1'bz) && PCIERATEQPLL0[1]; // rv 0 + assign PCIERATEQPLL0_in[2] = (PCIERATEQPLL0[2] !== 1'bz) && PCIERATEQPLL0[2]; // rv 0 + assign PCIERATEQPLL1_in[0] = (PCIERATEQPLL1[0] !== 1'bz) && PCIERATEQPLL1[0]; // rv 0 + assign PCIERATEQPLL1_in[1] = (PCIERATEQPLL1[1] !== 1'bz) && PCIERATEQPLL1[1]; // rv 0 + assign PCIERATEQPLL1_in[2] = (PCIERATEQPLL1[2] !== 1'bz) && PCIERATEQPLL1[2]; // rv 0 + assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0[0]; // rv 0 + assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0[1]; // rv 0 + assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0[2]; // rv 0 + assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0[3]; // rv 0 + assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0[4]; // rv 0 + assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0[5]; // rv 0 + assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0[6]; // rv 0 + assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0[7]; // rv 0 + assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1[0]; // rv 0 + assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1[1]; // rv 0 + assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1[2]; // rv 0 + assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1[3]; // rv 0 + assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1[4]; // rv 0 + assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1[5]; // rv 0 + assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1[6]; // rv 0 + assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1[7]; // rv 0 + assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 !== 1'bz) && QPLL0CLKRSVD0; // rv 0 + assign QPLL0CLKRSVD1_in = (QPLL0CLKRSVD1 !== 1'bz) && QPLL0CLKRSVD1; // rv 0 + assign QPLL0FBDIV_in[0] = (QPLL0FBDIV[0] !== 1'bz) && QPLL0FBDIV[0]; // rv 0 + assign QPLL0FBDIV_in[1] = (QPLL0FBDIV[1] !== 1'bz) && QPLL0FBDIV[1]; // rv 0 + assign QPLL0FBDIV_in[2] = (QPLL0FBDIV[2] !== 1'bz) && QPLL0FBDIV[2]; // rv 0 + assign QPLL0FBDIV_in[3] = (QPLL0FBDIV[3] !== 1'bz) && QPLL0FBDIV[3]; // rv 0 + assign QPLL0FBDIV_in[4] = (QPLL0FBDIV[4] !== 1'bz) && QPLL0FBDIV[4]; // rv 0 + assign QPLL0FBDIV_in[5] = (QPLL0FBDIV[5] !== 1'bz) && QPLL0FBDIV[5]; // rv 0 + assign QPLL0FBDIV_in[6] = (QPLL0FBDIV[6] !== 1'bz) && QPLL0FBDIV[6]; // rv 0 + assign QPLL0FBDIV_in[7] = (QPLL0FBDIV[7] !== 1'bz) && QPLL0FBDIV[7]; // rv 0 + assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK !== 1'bz) && QPLL0LOCKDETCLK; // rv 0 + assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN; // rv 0 + assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD; // rv 0 + assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL[0]; // rv 1 + assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL[1]; // rv 0 + assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL[2]; // rv 0 + assign QPLL0RESET_in = (QPLL0RESET === 1'bz) || QPLL0RESET; // rv 1 + assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 !== 1'bz) && QPLL1CLKRSVD0; // rv 0 + assign QPLL1CLKRSVD1_in = (QPLL1CLKRSVD1 !== 1'bz) && QPLL1CLKRSVD1; // rv 0 + assign QPLL1FBDIV_in[0] = (QPLL1FBDIV[0] !== 1'bz) && QPLL1FBDIV[0]; // rv 0 + assign QPLL1FBDIV_in[1] = (QPLL1FBDIV[1] !== 1'bz) && QPLL1FBDIV[1]; // rv 0 + assign QPLL1FBDIV_in[2] = (QPLL1FBDIV[2] !== 1'bz) && QPLL1FBDIV[2]; // rv 0 + assign QPLL1FBDIV_in[3] = (QPLL1FBDIV[3] !== 1'bz) && QPLL1FBDIV[3]; // rv 0 + assign QPLL1FBDIV_in[4] = (QPLL1FBDIV[4] !== 1'bz) && QPLL1FBDIV[4]; // rv 0 + assign QPLL1FBDIV_in[5] = (QPLL1FBDIV[5] !== 1'bz) && QPLL1FBDIV[5]; // rv 0 + assign QPLL1FBDIV_in[6] = (QPLL1FBDIV[6] !== 1'bz) && QPLL1FBDIV[6]; // rv 0 + assign QPLL1FBDIV_in[7] = (QPLL1FBDIV[7] !== 1'bz) && QPLL1FBDIV[7]; // rv 0 + assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK !== 1'bz) && QPLL1LOCKDETCLK; // rv 0 + assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN; // rv 0 + assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD; // rv 0 + assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL[0]; // rv 1 + assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL[1]; // rv 0 + assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL[2]; // rv 0 + assign QPLL1RESET_in = (QPLL1RESET === 1'bz) || QPLL1RESET; // rv 1 + assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1[0]; // rv 0 + assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1[1]; // rv 0 + assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1[2]; // rv 0 + assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1[3]; // rv 0 + assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1[4]; // rv 0 + assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1[5]; // rv 0 + assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1[6]; // rv 0 + assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1[7]; // rv 0 + assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2[0]; // rv 0 + assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2[1]; // rv 0 + assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2[2]; // rv 0 + assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2[3]; // rv 0 + assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2[4]; // rv 0 + assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3[0]; // rv 0 + assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3[1]; // rv 0 + assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3[2]; // rv 0 + assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3[3]; // rv 0 + assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3[4]; // rv 0 + assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4[0]; // rv 0 + assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4[1]; // rv 0 + assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4[2]; // rv 0 + assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4[3]; // rv 0 + assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4[4]; // rv 0 + assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4[5]; // rv 0 + assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4[6]; // rv 0 + assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4[7]; // rv 0 + assign RCALENB_in = RCALENB; + assign SDM0DATA_in[0] = (SDM0DATA[0] !== 1'bz) && SDM0DATA[0]; // rv 0 + assign SDM0DATA_in[10] = (SDM0DATA[10] !== 1'bz) && SDM0DATA[10]; // rv 0 + assign SDM0DATA_in[11] = (SDM0DATA[11] !== 1'bz) && SDM0DATA[11]; // rv 0 + assign SDM0DATA_in[12] = (SDM0DATA[12] !== 1'bz) && SDM0DATA[12]; // rv 0 + assign SDM0DATA_in[13] = (SDM0DATA[13] !== 1'bz) && SDM0DATA[13]; // rv 0 + assign SDM0DATA_in[14] = (SDM0DATA[14] !== 1'bz) && SDM0DATA[14]; // rv 0 + assign SDM0DATA_in[15] = (SDM0DATA[15] !== 1'bz) && SDM0DATA[15]; // rv 0 + assign SDM0DATA_in[16] = (SDM0DATA[16] !== 1'bz) && SDM0DATA[16]; // rv 0 + assign SDM0DATA_in[17] = (SDM0DATA[17] !== 1'bz) && SDM0DATA[17]; // rv 0 + assign SDM0DATA_in[18] = (SDM0DATA[18] !== 1'bz) && SDM0DATA[18]; // rv 0 + assign SDM0DATA_in[19] = (SDM0DATA[19] !== 1'bz) && SDM0DATA[19]; // rv 0 + assign SDM0DATA_in[1] = (SDM0DATA[1] !== 1'bz) && SDM0DATA[1]; // rv 0 + assign SDM0DATA_in[20] = (SDM0DATA[20] !== 1'bz) && SDM0DATA[20]; // rv 0 + assign SDM0DATA_in[21] = (SDM0DATA[21] !== 1'bz) && SDM0DATA[21]; // rv 0 + assign SDM0DATA_in[22] = (SDM0DATA[22] !== 1'bz) && SDM0DATA[22]; // rv 0 + assign SDM0DATA_in[23] = (SDM0DATA[23] !== 1'bz) && SDM0DATA[23]; // rv 0 + assign SDM0DATA_in[24] = (SDM0DATA[24] !== 1'bz) && SDM0DATA[24]; // rv 0 + assign SDM0DATA_in[2] = (SDM0DATA[2] !== 1'bz) && SDM0DATA[2]; // rv 0 + assign SDM0DATA_in[3] = (SDM0DATA[3] !== 1'bz) && SDM0DATA[3]; // rv 0 + assign SDM0DATA_in[4] = (SDM0DATA[4] !== 1'bz) && SDM0DATA[4]; // rv 0 + assign SDM0DATA_in[5] = (SDM0DATA[5] !== 1'bz) && SDM0DATA[5]; // rv 0 + assign SDM0DATA_in[6] = (SDM0DATA[6] !== 1'bz) && SDM0DATA[6]; // rv 0 + assign SDM0DATA_in[7] = (SDM0DATA[7] !== 1'bz) && SDM0DATA[7]; // rv 0 + assign SDM0DATA_in[8] = (SDM0DATA[8] !== 1'bz) && SDM0DATA[8]; // rv 0 + assign SDM0DATA_in[9] = (SDM0DATA[9] !== 1'bz) && SDM0DATA[9]; // rv 0 + assign SDM0RESET_in = (SDM0RESET === 1'bz) || SDM0RESET; // rv 1 + assign SDM0TOGGLE_in = (SDM0TOGGLE !== 1'bz) && SDM0TOGGLE; // rv 0 + assign SDM0WIDTH_in[0] = (SDM0WIDTH[0] !== 1'bz) && SDM0WIDTH[0]; // rv 0 + assign SDM0WIDTH_in[1] = (SDM0WIDTH[1] !== 1'bz) && SDM0WIDTH[1]; // rv 0 + assign SDM1DATA_in[0] = (SDM1DATA[0] !== 1'bz) && SDM1DATA[0]; // rv 0 + assign SDM1DATA_in[10] = (SDM1DATA[10] !== 1'bz) && SDM1DATA[10]; // rv 0 + assign SDM1DATA_in[11] = (SDM1DATA[11] !== 1'bz) && SDM1DATA[11]; // rv 0 + assign SDM1DATA_in[12] = (SDM1DATA[12] !== 1'bz) && SDM1DATA[12]; // rv 0 + assign SDM1DATA_in[13] = (SDM1DATA[13] !== 1'bz) && SDM1DATA[13]; // rv 0 + assign SDM1DATA_in[14] = (SDM1DATA[14] !== 1'bz) && SDM1DATA[14]; // rv 0 + assign SDM1DATA_in[15] = (SDM1DATA[15] !== 1'bz) && SDM1DATA[15]; // rv 0 + assign SDM1DATA_in[16] = (SDM1DATA[16] !== 1'bz) && SDM1DATA[16]; // rv 0 + assign SDM1DATA_in[17] = (SDM1DATA[17] !== 1'bz) && SDM1DATA[17]; // rv 0 + assign SDM1DATA_in[18] = (SDM1DATA[18] !== 1'bz) && SDM1DATA[18]; // rv 0 + assign SDM1DATA_in[19] = (SDM1DATA[19] !== 1'bz) && SDM1DATA[19]; // rv 0 + assign SDM1DATA_in[1] = (SDM1DATA[1] !== 1'bz) && SDM1DATA[1]; // rv 0 + assign SDM1DATA_in[20] = (SDM1DATA[20] !== 1'bz) && SDM1DATA[20]; // rv 0 + assign SDM1DATA_in[21] = (SDM1DATA[21] !== 1'bz) && SDM1DATA[21]; // rv 0 + assign SDM1DATA_in[22] = (SDM1DATA[22] !== 1'bz) && SDM1DATA[22]; // rv 0 + assign SDM1DATA_in[23] = (SDM1DATA[23] !== 1'bz) && SDM1DATA[23]; // rv 0 + assign SDM1DATA_in[24] = (SDM1DATA[24] !== 1'bz) && SDM1DATA[24]; // rv 0 + assign SDM1DATA_in[2] = (SDM1DATA[2] !== 1'bz) && SDM1DATA[2]; // rv 0 + assign SDM1DATA_in[3] = (SDM1DATA[3] !== 1'bz) && SDM1DATA[3]; // rv 0 + assign SDM1DATA_in[4] = (SDM1DATA[4] !== 1'bz) && SDM1DATA[4]; // rv 0 + assign SDM1DATA_in[5] = (SDM1DATA[5] !== 1'bz) && SDM1DATA[5]; // rv 0 + assign SDM1DATA_in[6] = (SDM1DATA[6] !== 1'bz) && SDM1DATA[6]; // rv 0 + assign SDM1DATA_in[7] = (SDM1DATA[7] !== 1'bz) && SDM1DATA[7]; // rv 0 + assign SDM1DATA_in[8] = (SDM1DATA[8] !== 1'bz) && SDM1DATA[8]; // rv 0 + assign SDM1DATA_in[9] = (SDM1DATA[9] !== 1'bz) && SDM1DATA[9]; // rv 0 + assign SDM1RESET_in = (SDM1RESET === 1'bz) || SDM1RESET; // rv 1 + assign SDM1TOGGLE_in = (SDM1TOGGLE !== 1'bz) && SDM1TOGGLE; // rv 0 + assign SDM1WIDTH_in[0] = (SDM1WIDTH[0] !== 1'bz) && SDM1WIDTH[0]; // rv 0 + assign SDM1WIDTH_in[1] = (SDM1WIDTH[1] !== 1'bz) && SDM1WIDTH[1]; // rv 0 + assign TCONGPI_in[0] = (TCONGPI[0] !== 1'bz) && TCONGPI[0]; // rv 0 + assign TCONGPI_in[1] = (TCONGPI[1] !== 1'bz) && TCONGPI[1]; // rv 0 + assign TCONGPI_in[2] = (TCONGPI[2] !== 1'bz) && TCONGPI[2]; // rv 0 + assign TCONGPI_in[3] = (TCONGPI[3] !== 1'bz) && TCONGPI[3]; // rv 0 + assign TCONGPI_in[4] = (TCONGPI[4] !== 1'bz) && TCONGPI[4]; // rv 0 + assign TCONGPI_in[5] = (TCONGPI[5] !== 1'bz) && TCONGPI[5]; // rv 0 + assign TCONGPI_in[6] = (TCONGPI[6] !== 1'bz) && TCONGPI[6]; // rv 0 + assign TCONGPI_in[7] = (TCONGPI[7] !== 1'bz) && TCONGPI[7]; // rv 0 + assign TCONGPI_in[8] = (TCONGPI[8] !== 1'bz) && TCONGPI[8]; // rv 0 + assign TCONGPI_in[9] = (TCONGPI[9] !== 1'bz) && TCONGPI[9]; // rv 0 + assign TCONPOWERUP_in = (TCONPOWERUP !== 1'bz) && TCONPOWERUP; // rv 0 + assign TCONRESET_in[0] = (TCONRESET[0] !== 1'bz) && TCONRESET[0]; // rv 0 + assign TCONRESET_in[1] = (TCONRESET[1] !== 1'bz) && TCONRESET[1]; // rv 0 + assign TCONRSVDIN1_in[0] = (TCONRSVDIN1[0] !== 1'bz) && TCONRSVDIN1[0]; // rv 0 + assign TCONRSVDIN1_in[1] = (TCONRSVDIN1[1] !== 1'bz) && TCONRSVDIN1[1]; // rv 0 + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((QPLL0CLKOUT_RATE_REG != "FULL") && + (QPLL0CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-158] QPLL0CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL0CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-169] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-170] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_REFCLK_DIV_REG != 1) && + (QPLL0_REFCLK_DIV_REG != 2) && + (QPLL0_REFCLK_DIV_REG != 3) && + (QPLL0_REFCLK_DIV_REG != 4) && + (QPLL0_REFCLK_DIV_REG != 5) && + (QPLL0_REFCLK_DIV_REG != 6) && + (QPLL0_REFCLK_DIV_REG != 8) && + (QPLL0_REFCLK_DIV_REG != 10) && + (QPLL0_REFCLK_DIV_REG != 12) && + (QPLL0_REFCLK_DIV_REG != 16) && + (QPLL0_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-179] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1CLKOUT_RATE_REG != "FULL") && + (QPLL1CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-183] QPLL1CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL1CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-194] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-195] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_REFCLK_DIV_REG != 1) && + (QPLL1_REFCLK_DIV_REG != 2) && + (QPLL1_REFCLK_DIV_REG != 3) && + (QPLL1_REFCLK_DIV_REG != 4) && + (QPLL1_REFCLK_DIV_REG != 5) && + (QPLL1_REFCLK_DIV_REG != 6) && + (QPLL1_REFCLK_DIV_REG != 8) && + (QPLL1_REFCLK_DIV_REG != 10) && + (QPLL1_REFCLK_DIV_REG != 12) && + (QPLL1_REFCLK_DIV_REG != 16) && + (QPLL1_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-204] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-228] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_MODE_REG != "FAST") && + (SIM_MODE_REG != "LEGACY"))) begin + $display("Error: [Unisim %s-229] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-230] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +assign PMASCANCLK_in = 10'b1111111111; // tie off + +assign CSSDSTOPCLK0_in = 1'b1; // tie off +assign CSSDSTOPCLK1_in = 1'b1; // tie off +assign PMASCANENB_in = 1'b1; // tie off +assign PMASCANIN_in = 10'b1111111111; // tie off +assign QDPMASCANMODEB_in = 1'b1; // tie off +assign QDPMASCANRSTEN_in = 1'b1; // tie off +assign RXRECCLK_in = 4'b1111; // tie off +assign TCONMBISTMODE_in = 1'b1; // tie off +assign TCONRSVDIN0_in = 5'b11111; // tie off +assign TCONSPD_in = 2'b11; // tie off +assign TCONTCK_in = 1'b1; // tie off +assign TCONTDI_in = 1'b1; // tie off +assign TCONTMS_in = 1'b1; // tie off +assign TCONTRST_in = 1'b1; // tie off + +SIP_GTHE4_COMMON SIP_GTHE4_COMMON_INST ( + .AEN_BGBS0 (AEN_BGBS0_REG), + .AEN_BGBS1 (AEN_BGBS1_REG), + .AEN_MASTER0 (AEN_MASTER0_REG), + .AEN_MASTER1 (AEN_MASTER1_REG), + .AEN_PD0 (AEN_PD0_REG), + .AEN_PD1 (AEN_PD1_REG), + .AEN_QPLL0 (AEN_QPLL0_REG), + .AEN_QPLL0_FBDIV (AEN_QPLL0_FBDIV_REG), + .AEN_QPLL1 (AEN_QPLL1_REG), + .AEN_QPLL1_FBDIV (AEN_QPLL1_FBDIV_REG), + .AEN_REFCLK0 (AEN_REFCLK0_REG), + .AEN_REFCLK1 (AEN_REFCLK1_REG), + .AEN_RESET0 (AEN_RESET0_REG), + .AEN_RESET1 (AEN_RESET1_REG), + .AEN_SDM0DATA (AEN_SDM0DATA_REG), + .AEN_SDM0RESET (AEN_SDM0RESET_REG), + .AEN_SDM0TOGGLE (AEN_SDM0TOGGLE_REG), + .AEN_SDM0WIDTH (AEN_SDM0WIDTH_REG), + .AEN_SDM1DATA (AEN_SDM1DATA_REG), + .AEN_SDM1RESET (AEN_SDM1RESET_REG), + .AEN_SDM1TOGGLE (AEN_SDM1TOGGLE_REG), + .AEN_SDM1WIDTH (AEN_SDM1WIDTH_REG), + .AQDMUXSEL1 (AQDMUXSEL1_REG), + .AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG), + .AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG), + .A_BGMONITOREN (A_BGMONITOREN_REG), + .A_BGPD (A_BGPD_REG), + .A_GTREFCLKPD0 (A_GTREFCLKPD0_REG), + .A_GTREFCLKPD1 (A_GTREFCLKPD1_REG), + .A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG), + .A_QPLL0PD (A_QPLL0PD_REG), + .A_QPLL0RESET (A_QPLL0RESET_REG), + .A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG), + .A_QPLL1PD (A_QPLL1PD_REG), + .A_QPLL1RESET (A_QPLL1RESET_REG), + .A_SDM0DATA_HIGH (A_SDM0DATA_HIGH_REG), + .A_SDM0DATA_LOW (A_SDM0DATA_LOW_REG), + .A_SDM0RESET (A_SDM0RESET_REG), + .A_SDM0TOGGLE (A_SDM0TOGGLE_REG), + .A_SDM1DATA_HIGH (A_SDM1DATA_HIGH_REG), + .A_SDM1DATA_LOW (A_SDM1DATA_LOW_REG), + .A_SDM1RESET (A_SDM1RESET_REG), + .A_SDM1TOGGLE (A_SDM1TOGGLE_REG), + .BIAS_CFG0 (BIAS_CFG0_REG), + .BIAS_CFG1 (BIAS_CFG1_REG), + .BIAS_CFG2 (BIAS_CFG2_REG), + .BIAS_CFG3 (BIAS_CFG3_REG), + .BIAS_CFG4 (BIAS_CFG4_REG), + .BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG), + .COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG), + .COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG), + .COMMON_CFG0 (COMMON_CFG0_REG), + .COMMON_CFG1 (COMMON_CFG1_REG), + .COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG), + .POR_CFG (POR_CFG_REG), + .PPF0_CFG (PPF0_CFG_REG), + .PPF1_CFG (PPF1_CFG_REG), + .QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG), + .QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG), + .QPLL0_CFG0 (QPLL0_CFG0_REG), + .QPLL0_CFG1 (QPLL0_CFG1_REG), + .QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG), + .QPLL0_CFG2 (QPLL0_CFG2_REG), + .QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG), + .QPLL0_CFG3 (QPLL0_CFG3_REG), + .QPLL0_CFG4 (QPLL0_CFG4_REG), + .QPLL0_CP (QPLL0_CP_REG), + .QPLL0_CP_G3 (QPLL0_CP_G3_REG), + .QPLL0_FBDIV (QPLL0_FBDIV_REG), + .QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG), + .QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG), + .QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG), + .QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG), + .QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG), + .QPLL0_LPF (QPLL0_LPF_REG), + .QPLL0_LPF_G3 (QPLL0_LPF_G3_REG), + .QPLL0_PCI_EN (QPLL0_PCI_EN_REG), + .QPLL0_RATE_SW_USE_DRP (QPLL0_RATE_SW_USE_DRP_REG), + .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG), + .QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG), + .QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG), + .QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG), + .QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG), + .QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG), + .QPLL1_CFG0 (QPLL1_CFG0_REG), + .QPLL1_CFG1 (QPLL1_CFG1_REG), + .QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG), + .QPLL1_CFG2 (QPLL1_CFG2_REG), + .QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG), + .QPLL1_CFG3 (QPLL1_CFG3_REG), + .QPLL1_CFG4 (QPLL1_CFG4_REG), + .QPLL1_CP (QPLL1_CP_REG), + .QPLL1_CP_G3 (QPLL1_CP_G3_REG), + .QPLL1_FBDIV (QPLL1_FBDIV_REG), + .QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG), + .QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG), + .QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG), + .QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG), + .QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG), + .QPLL1_LPF (QPLL1_LPF_REG), + .QPLL1_LPF_G3 (QPLL1_LPF_G3_REG), + .QPLL1_PCI_EN (QPLL1_PCI_EN_REG), + .QPLL1_RATE_SW_USE_DRP (QPLL1_RATE_SW_USE_DRP_REG), + .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG), + .QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG), + .QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG), + .QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG), + .RCALSAP_TESTEN (RCALSAP_TESTEN_REG), + .RCAL_APROBE (RCAL_APROBE_REG), + .REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG), + .REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG), + .REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG), + .REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG), + .REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG), + .REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG), + .RSVD_ATTR0 (RSVD_ATTR0_REG), + .RSVD_ATTR1 (RSVD_ATTR1_REG), + .RSVD_ATTR2 (RSVD_ATTR2_REG), + .RSVD_ATTR3 (RSVD_ATTR3_REG), + .RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG), + .RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG), + .SARC_ENB (SARC_ENB_REG), + .SARC_SEL (SARC_SEL_REG), + .SDM0INITSEED0_0 (SDM0INITSEED0_0_REG), + .SDM0INITSEED0_1 (SDM0INITSEED0_1_REG), + .SDM1INITSEED0_0 (SDM1INITSEED0_0_REG), + .SDM1INITSEED0_1 (SDM1INITSEED0_1_REG), + .SIM_DEVICE (SIM_DEVICE_REG), + .SIM_MODE (SIM_MODE_REG), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), + .VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG), + .CSSDSTOPCLKDONE0 (CSSDSTOPCLKDONE0_out), + .CSSDSTOPCLKDONE1 (CSSDSTOPCLKDONE1_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .PMARSVDOUT0 (PMARSVDOUT0_out), + .PMARSVDOUT1 (PMARSVDOUT1_out), + .PMASCANOUT (PMASCANOUT_out), + .QPLL0FBCLKLOST (QPLL0FBCLKLOST_out), + .QPLL0LOCK (QPLL0LOCK_out), + .QPLL0OUTCLK (QPLL0OUTCLK_out), + .QPLL0OUTREFCLK (QPLL0OUTREFCLK_out), + .QPLL0REFCLKLOST (QPLL0REFCLKLOST_out), + .QPLL1FBCLKLOST (QPLL1FBCLKLOST_out), + .QPLL1LOCK (QPLL1LOCK_out), + .QPLL1OUTCLK (QPLL1OUTCLK_out), + .QPLL1OUTREFCLK (QPLL1OUTREFCLK_out), + .QPLL1REFCLKLOST (QPLL1REFCLKLOST_out), + .QPLLDMONITOR0 (QPLLDMONITOR0_out), + .QPLLDMONITOR1 (QPLLDMONITOR1_out), + .REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out), + .REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out), + .RXRECCLK0SEL (RXRECCLK0SEL_out), + .RXRECCLK1SEL (RXRECCLK1SEL_out), + .SARCCLK (SARCCLK_out), + .SDM0FINALOUT (SDM0FINALOUT_out), + .SDM0TESTDATA (SDM0TESTDATA_out), + .SDM1FINALOUT (SDM1FINALOUT_out), + .SDM1TESTDATA (SDM1TESTDATA_out), + .TCONGPO (TCONGPO_out), + .TCONRSVDOUT0 (TCONRSVDOUT0_out), + .TCONTDO (TCONTDO_out), + .BGBYPASSB (BGBYPASSB_in), + .BGMONITORENB (BGMONITORENB_in), + .BGPDB (BGPDB_in), + .BGRCALOVRD (BGRCALOVRD_in), + .BGRCALOVRDENB (BGRCALOVRDENB_in), + .CSSDSTOPCLK0 (CSSDSTOPCLK0_in), + .CSSDSTOPCLK1 (CSSDSTOPCLK1_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .GTGREFCLK0 (GTGREFCLK0_in), + .GTGREFCLK1 (GTGREFCLK1_in), + .GTNORTHREFCLK00 (GTNORTHREFCLK00_in), + .GTNORTHREFCLK01 (GTNORTHREFCLK01_in), + .GTNORTHREFCLK10 (GTNORTHREFCLK10_in), + .GTNORTHREFCLK11 (GTNORTHREFCLK11_in), + .GTREFCLK00 (GTREFCLK00_in), + .GTREFCLK01 (GTREFCLK01_in), + .GTREFCLK10 (GTREFCLK10_in), + .GTREFCLK11 (GTREFCLK11_in), + .GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in), + .GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in), + .GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in), + .GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in), + .PCIERATEQPLL0 (PCIERATEQPLL0_in), + .PCIERATEQPLL1 (PCIERATEQPLL1_in), + .PMARSVD0 (PMARSVD0_in), + .PMARSVD1 (PMARSVD1_in), + .PMASCANCLK (PMASCANCLK_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .QDPMASCANMODEB (QDPMASCANMODEB_in), + .QDPMASCANRSTEN (QDPMASCANRSTEN_in), + .QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in), + .QPLL0CLKRSVD1 (QPLL0CLKRSVD1_in), + .QPLL0FBDIV (QPLL0FBDIV_in), + .QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in), + .QPLL0LOCKEN (QPLL0LOCKEN_in), + .QPLL0PD (QPLL0PD_in), + .QPLL0REFCLKSEL (QPLL0REFCLKSEL_in), + .QPLL0RESET (QPLL0RESET_in), + .QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in), + .QPLL1CLKRSVD1 (QPLL1CLKRSVD1_in), + .QPLL1FBDIV (QPLL1FBDIV_in), + .QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in), + .QPLL1LOCKEN (QPLL1LOCKEN_in), + .QPLL1PD (QPLL1PD_in), + .QPLL1REFCLKSEL (QPLL1REFCLKSEL_in), + .QPLL1RESET (QPLL1RESET_in), + .QPLLRSVD1 (QPLLRSVD1_in), + .QPLLRSVD2 (QPLLRSVD2_in), + .QPLLRSVD3 (QPLLRSVD3_in), + .QPLLRSVD4 (QPLLRSVD4_in), + .RCALENB (RCALENB_in), + .RXRECCLK (RXRECCLK_in), + .SDM0DATA (SDM0DATA_in), + .SDM0RESET (SDM0RESET_in), + .SDM0TOGGLE (SDM0TOGGLE_in), + .SDM0WIDTH (SDM0WIDTH_in), + .SDM1DATA (SDM1DATA_in), + .SDM1RESET (SDM1RESET_in), + .SDM1TOGGLE (SDM1TOGGLE_in), + .SDM1WIDTH (SDM1WIDTH_in), + .TCONGPI (TCONGPI_in), + .TCONMBISTMODE (TCONMBISTMODE_in), + .TCONPOWERUP (TCONPOWERUP_in), + .TCONRESET (TCONRESET_in), + .TCONRSVDIN0 (TCONRSVDIN0_in), + .TCONRSVDIN1 (TCONRSVDIN1_in), + .TCONSPD (TCONSPD_in), + .TCONTCK (TCONTCK_in), + .TCONTDI (TCONTDI_in), + .TCONTMS (TCONTMS_in), + .TCONTRST (TCONTRST_in), + .GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (QPLL0LOCKDETCLK => QPLL0FBCLKLOST) = (0:0:0, 0:0:0); + (QPLL1LOCKDETCLK => QPLL1FBCLKLOST) = (0:0:0, 0:0:0); + // (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output + // (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTM_DUAL.sv b/verilog/src/unisims/GTM_DUAL.sv new file mode 100644 index 0000000..2e10e60 --- /dev/null +++ b/verilog/src/unisims/GTM_DUAL.sv @@ -0,0 +1,6920 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / GTM_DUAL +// /___/ /\ Filename : GTM_DUAL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +(* hier_bypass_ports="in:integer:CH0_GTMRXN:CH0_GTMRXN_integer in:integer:CH0_GTMRXP:CH0_GTMRXP_integer in:integer:CH1_GTMRXN:CH1_GTMRXN_integer in:integer:CH1_GTMRXP:CH1_GTMRXP_integer out:integer:CH0_GTMTXN:CH0_GTMTXN_integer out:integer:CH0_GTMTXP:CH0_GTMTXP_integer out:integer:CH1_GTMTXN:CH1_GTMTXN_integer out:integer:CH1_GTMTXP:CH1_GTMTXP_integer" *) +module GTM_DUAL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] A_CFG = 16'b0000100001000000, + parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000, + parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000, + parameter [15:0] BIAS_CFG0 = 16'b0000000000000000, + parameter [15:0] BIAS_CFG1 = 16'b0000000000000000, + parameter [15:0] BIAS_CFG2 = 16'b0001000000000000, + parameter [15:0] BIAS_CFG3 = 16'b0000000000000001, + parameter [15:0] BIAS_CFG4 = 16'b0000000000000000, + parameter [15:0] BIAS_CFG5 = 16'b0000000000000000, + parameter [15:0] BIAS_CFG6 = 16'b0000000010000000, + parameter [15:0] BIAS_CFG7 = 16'b0000000000000000, + parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011, + parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000, + parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000, + parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000, + parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000, + parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000, + parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000, + parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000, + parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000, + parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100, + parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000, + parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100, + parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000, + parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000, + parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001, + parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001, + parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001, + parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000, + parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001, + parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001, + parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001, + parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111, + parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101, + parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101, + parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000, + parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010, + parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000, + parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000, + parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000, + parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000, + parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000, + parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000, + parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000, + parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000, + parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000, + parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000, + parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100, + parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000, + parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000, + parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000, + parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000, + parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000, + parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000, + parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000, + parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100, + parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000, + parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000, + parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000, + parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001, + parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100, + parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000, + parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000, + parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011, + parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000, + parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000, + parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000, + parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100, + parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100, + parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110, + parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011, + parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110, + parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000, + parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000, + parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000, + parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000, + parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010, + parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000, + parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000, + parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000, + parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000, + parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000, + parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010, + parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000, + parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000, + parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111, + parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000, + parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100, + parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010, + parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000, + parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000, + parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000, + parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000, + parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111, + parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000, + parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000, + parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101, + parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000, + parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011, + parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000, + parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000, + parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000, + parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011, + parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000, + parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000, + parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000, + parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000, + parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000, + parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000, + parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000, + parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000, + parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100, + parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000, + parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100, + parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000, + parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000, + parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001, + parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001, + parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001, + parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000, + parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001, + parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001, + parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001, + parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111, + parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101, + parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101, + parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000, + parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010, + parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000, + parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000, + parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000, + parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000, + parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000, + parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000, + parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000, + parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000, + parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000, + parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100, + parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000, + parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000, + parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000, + parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000, + parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000, + parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100, + parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000, + parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000, + parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000, + parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001, + parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100, + parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000, + parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000, + parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011, + parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000, + parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000, + parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000, + parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100, + parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100, + parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110, + parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011, + parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110, + parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000, + parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000, + parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000, + parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000, + parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010, + parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000, + parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000, + parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000, + parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000, + parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000, + parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010, + parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000, + parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000, + parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111, + parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000, + parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100, + parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010, + parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000, + parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000, + parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000, + parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000, + parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111, + parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000, + parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000, + parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101, + parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000, + parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011, + parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000, + parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000, + parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000, + parameter real DATARATE = 10.000, + parameter [15:0] DRPEN_CFG = 16'b0000000000000000, + parameter [15:0] FEC_CFG0 = 16'b0000000000000000, + parameter [15:0] FEC_CFG1 = 16'b0000000000000000, + parameter [15:0] FEC_CFG10 = 16'b0000000000000000, + parameter [15:0] FEC_CFG11 = 16'b0000000000000000, + parameter [15:0] FEC_CFG12 = 16'b0000000000000000, + parameter [15:0] FEC_CFG13 = 16'b0000000000000000, + parameter [15:0] FEC_CFG14 = 16'b0000000000000000, + parameter [15:0] FEC_CFG15 = 16'b0000000000000000, + parameter [15:0] FEC_CFG16 = 16'b0000000000000000, + parameter [15:0] FEC_CFG17 = 16'b0000000000000000, + parameter [15:0] FEC_CFG18 = 16'b0000000000000000, + parameter [15:0] FEC_CFG19 = 16'b0000000000000000, + parameter [15:0] FEC_CFG2 = 16'b0000000000000000, + parameter [15:0] FEC_CFG20 = 16'b0000000000000000, + parameter [15:0] FEC_CFG21 = 16'b0000000000000000, + parameter [15:0] FEC_CFG22 = 16'b0000000000000000, + parameter [15:0] FEC_CFG23 = 16'b0000000000000000, + parameter [15:0] FEC_CFG24 = 16'b0000000000000000, + parameter [15:0] FEC_CFG25 = 16'b0000000000000000, + parameter [15:0] FEC_CFG26 = 16'b0000000000000000, + parameter [15:0] FEC_CFG27 = 16'b0000000000000000, + parameter [15:0] FEC_CFG3 = 16'b0000000000000000, + parameter [15:0] FEC_CFG4 = 16'b0000000000000000, + parameter [15:0] FEC_CFG5 = 16'b0000000000000000, + parameter [15:0] FEC_CFG6 = 16'b0000000000000000, + parameter [15:0] FEC_CFG7 = 16'b0000000000000000, + parameter [15:0] FEC_CFG8 = 16'b0000000000000000, + parameter [15:0] FEC_CFG9 = 16'b0000000000000000, + parameter FEC_MODE = "BYPASS", + parameter real INS_LOSS_NYQ = 20.000, + parameter integer INTERFACE_WIDTH = 64, + parameter MODULATION_MODE = "NRZ", + parameter [15:0] PLL_CFG0 = 16'b0001100111110000, + parameter [15:0] PLL_CFG1 = 16'b0000111101110000, + parameter [15:0] PLL_CFG2 = 16'b1000000111101000, + parameter [15:0] PLL_CFG3 = 16'b0100000000000000, + parameter [15:0] PLL_CFG4 = 16'b0111111111101010, + parameter [15:0] PLL_CFG5 = 16'b0100101100111000, + parameter [15:0] PLL_CFG6 = 16'b0000000000100101, + parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000, + parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100, + parameter [0:0] PLL_IPS_PIN_EN = 1'b1, + parameter integer PLL_IPS_REFCLK_SEL = 0, + parameter [0:0] RCALSAP_TESTEN = 1'b0, + parameter [0:0] RCAL_APROBE = 1'b0, + parameter [15:0] RST_CFG = 16'b0000000000000010, + parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100, + parameter [15:0] SAP_CFG0 = 16'b0000000000000000, + parameter [15:0] SDM_CFG0 = 16'b0001100001000000, + parameter [15:0] SDM_CFG1 = 16'b0000000000000000, + parameter [15:0] SDM_CFG2 = 16'b0000000000000000, + parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000, + parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000, + parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter integer TX_AMPLITUDE_SWING = 250 +)( + output [27:0] CH0_AXISTDATA, + output CH0_AXISTLAST, + output CH0_AXISTVALID, + output [31:0] CH0_DMONITOROUT, + output CH0_DMONITOROUTCLK, + output CH0_GTMTXN, + output CH0_GTMTXP, + output [15:0] CH0_PCSRSVDOUT, + output [15:0] CH0_PMARSVDOUT, + output CH0_RESETEXCEPTION, + output [2:0] CH0_RXBUFSTATUS, + output [255:0] CH0_RXDATA, + output [3:0] CH0_RXDATAFLAGS, + output CH0_RXDATAISAM, + output CH0_RXDATASTART, + output CH0_RXOUTCLK, + output CH0_RXPMARESETDONE, + output CH0_RXPRBSERR, + output CH0_RXPRBSLOCKED, + output CH0_RXPRGDIVRESETDONE, + output CH0_RXPROGDIVCLK, + output CH0_RXRESETDONE, + output [1:0] CH0_TXBUFSTATUS, + output CH0_TXOUTCLK, + output CH0_TXPMARESETDONE, + output CH0_TXPRGDIVRESETDONE, + output CH0_TXPROGDIVCLK, + output CH0_TXRESETDONE, + output [27:0] CH1_AXISTDATA, + output CH1_AXISTLAST, + output CH1_AXISTVALID, + output [31:0] CH1_DMONITOROUT, + output CH1_DMONITOROUTCLK, + output CH1_GTMTXN, + output CH1_GTMTXP, + output [15:0] CH1_PCSRSVDOUT, + output [15:0] CH1_PMARSVDOUT, + output CH1_RESETEXCEPTION, + output [2:0] CH1_RXBUFSTATUS, + output [255:0] CH1_RXDATA, + output [3:0] CH1_RXDATAFLAGS, + output CH1_RXDATAISAM, + output CH1_RXDATASTART, + output CH1_RXOUTCLK, + output CH1_RXPMARESETDONE, + output CH1_RXPRBSERR, + output CH1_RXPRBSLOCKED, + output CH1_RXPRGDIVRESETDONE, + output CH1_RXPROGDIVCLK, + output CH1_RXRESETDONE, + output [1:0] CH1_TXBUFSTATUS, + output CH1_TXOUTCLK, + output CH1_TXPMARESETDONE, + output CH1_TXPRGDIVRESETDONE, + output CH1_TXPROGDIVCLK, + output CH1_TXRESETDONE, + output CLKTESTSIG2PAD, + output DMONITOROUTPLLCLK, + output [15:0] DRPDO, + output DRPRDY, + output FECRX0ALIGNED, + output FECRX0CORRCWINC, + output FECRX0CWINC, + output FECRX0UNCORRCWINC, + output FECRX1ALIGNED, + output FECRX1CORRCWINC, + output FECRX1CWINC, + output FECRX1UNCORRCWINC, + output [7:0] FECRXLN0BITERR0TO1INC, + output [7:0] FECRXLN0BITERR1TO0INC, + output [14:0] FECRXLN0DLY, + output [3:0] FECRXLN0ERRCNTINC, + output [1:0] FECRXLN0MAPPING, + output [7:0] FECRXLN1BITERR0TO1INC, + output [7:0] FECRXLN1BITERR1TO0INC, + output [14:0] FECRXLN1DLY, + output [3:0] FECRXLN1ERRCNTINC, + output [1:0] FECRXLN1MAPPING, + output [7:0] FECRXLN2BITERR0TO1INC, + output [7:0] FECRXLN2BITERR1TO0INC, + output [14:0] FECRXLN2DLY, + output [3:0] FECRXLN2ERRCNTINC, + output [1:0] FECRXLN2MAPPING, + output [7:0] FECRXLN3BITERR0TO1INC, + output [7:0] FECRXLN3BITERR1TO0INC, + output [14:0] FECRXLN3DLY, + output [3:0] FECRXLN3ERRCNTINC, + output [1:0] FECRXLN3MAPPING, + output FECTRXLN0LOCK, + output FECTRXLN1LOCK, + output FECTRXLN2LOCK, + output FECTRXLN3LOCK, + output GTPOWERGOOD, + output PLLFBCLKLOST, + output PLLLOCK, + output PLLREFCLKLOST, + output PLLREFCLKMONITOR, + output PLLRESETDONE, + output [15:0] PLLRSVDOUT, + output RCALCMP, + output [4:0] RCALOUT, + output RXRECCLK0, + output RXRECCLK1, + + input BGBYPASSB, + input BGMONITORENB, + input BGPDB, + input [4:0] BGRCALOVRD, + input BGRCALOVRDENB, + input CH0_AXISEN, + input CH0_AXISRST, + input CH0_AXISTRDY, + input CH0_CFGRESET, + input CH0_DMONFIFORESET, + input CH0_DMONITORCLK, + input CH0_GTMRXN, + input CH0_GTMRXP, + input CH0_GTRXRESET, + input CH0_GTTXRESET, + input [2:0] CH0_LOOPBACK, + input [15:0] CH0_PCSRSVDIN, + input [15:0] CH0_PMARSVDIN, + input CH0_RESETOVRD, + input CH0_RXADAPTRESET, + input CH0_RXADCCALRESET, + input CH0_RXADCCLKGENRESET, + input CH0_RXBUFRESET, + input CH0_RXCDRFREQOS, + input CH0_RXCDRFRRESET, + input CH0_RXCDRHOLD, + input CH0_RXCDRINCPCTRL, + input CH0_RXCDROVRDEN, + input CH0_RXCDRPHRESET, + input CH0_RXDFERESET, + input CH0_RXDSPRESET, + input CH0_RXEQTRAINING, + input CH0_RXEYESCANRESET, + input CH0_RXFECRESET, + input [2:0] CH0_RXOUTCLKSEL, + input CH0_RXPCSRESET, + input [3:0] CH0_RXPCSRESETMASK, + input CH0_RXPMARESET, + input [7:0] CH0_RXPMARESETMASK, + input CH0_RXPOLARITY, + input CH0_RXPRBSCNTSTOP, + input CH0_RXPRBSCSCNTRST, + input [3:0] CH0_RXPRBSPTN, + input CH0_RXPROGDIVRESET, + input CH0_RXQPRBSEN, + input [1:0] CH0_RXRESETMODE, + input CH0_RXSPCSEQADV, + input CH0_RXUSRCLK, + input CH0_RXUSRCLK2, + input CH0_RXUSRRDY, + input CH0_RXUSRSTART, + input CH0_RXUSRSTOP, + input CH0_TXCKALRESET, + input [5:0] CH0_TXCTLFIRDAT, + input [255:0] CH0_TXDATA, + input CH0_TXDATASTART, + input [4:0] CH0_TXDRVAMP, + input [5:0] CH0_TXEMPMAIN, + input [4:0] CH0_TXEMPPOST, + input [4:0] CH0_TXEMPPRE, + input [3:0] CH0_TXEMPPRE2, + input CH0_TXFECRESET, + input CH0_TXINHIBIT, + input CH0_TXMUXDCDEXHOLD, + input CH0_TXMUXDCDORWREN, + input [2:0] CH0_TXOUTCLKSEL, + input CH0_TXPCSRESET, + input [1:0] CH0_TXPCSRESETMASK, + input CH0_TXPMARESET, + input [1:0] CH0_TXPMARESETMASK, + input CH0_TXPOLARITY, + input CH0_TXPRBSINERR, + input [3:0] CH0_TXPRBSPTN, + input CH0_TXPROGDIVRESET, + input CH0_TXQPRBSEN, + input [1:0] CH0_TXRESETMODE, + input CH0_TXSPCSEQADV, + input CH0_TXUSRCLK, + input CH0_TXUSRCLK2, + input CH0_TXUSRRDY, + input CH1_AXISEN, + input CH1_AXISRST, + input CH1_AXISTRDY, + input CH1_CFGRESET, + input CH1_DMONFIFORESET, + input CH1_DMONITORCLK, + input CH1_GTMRXN, + input CH1_GTMRXP, + input CH1_GTRXRESET, + input CH1_GTTXRESET, + input [2:0] CH1_LOOPBACK, + input [15:0] CH1_PCSRSVDIN, + input [15:0] CH1_PMARSVDIN, + input CH1_RESETOVRD, + input CH1_RXADAPTRESET, + input CH1_RXADCCALRESET, + input CH1_RXADCCLKGENRESET, + input CH1_RXBUFRESET, + input CH1_RXCDRFREQOS, + input CH1_RXCDRFRRESET, + input CH1_RXCDRHOLD, + input CH1_RXCDRINCPCTRL, + input CH1_RXCDROVRDEN, + input CH1_RXCDRPHRESET, + input CH1_RXDFERESET, + input CH1_RXDSPRESET, + input CH1_RXEQTRAINING, + input CH1_RXEYESCANRESET, + input CH1_RXFECRESET, + input [2:0] CH1_RXOUTCLKSEL, + input CH1_RXPCSRESET, + input [3:0] CH1_RXPCSRESETMASK, + input CH1_RXPMARESET, + input [7:0] CH1_RXPMARESETMASK, + input CH1_RXPOLARITY, + input CH1_RXPRBSCNTSTOP, + input CH1_RXPRBSCSCNTRST, + input [3:0] CH1_RXPRBSPTN, + input CH1_RXPROGDIVRESET, + input CH1_RXQPRBSEN, + input [1:0] CH1_RXRESETMODE, + input CH1_RXSPCSEQADV, + input CH1_RXUSRCLK, + input CH1_RXUSRCLK2, + input CH1_RXUSRRDY, + input CH1_RXUSRSTART, + input CH1_RXUSRSTOP, + input CH1_TXCKALRESET, + input [5:0] CH1_TXCTLFIRDAT, + input [255:0] CH1_TXDATA, + input CH1_TXDATASTART, + input [4:0] CH1_TXDRVAMP, + input [5:0] CH1_TXEMPMAIN, + input [4:0] CH1_TXEMPPOST, + input [4:0] CH1_TXEMPPRE, + input [3:0] CH1_TXEMPPRE2, + input CH1_TXFECRESET, + input CH1_TXINHIBIT, + input CH1_TXMUXDCDEXHOLD, + input CH1_TXMUXDCDORWREN, + input [2:0] CH1_TXOUTCLKSEL, + input CH1_TXPCSRESET, + input [1:0] CH1_TXPCSRESETMASK, + input CH1_TXPMARESET, + input [1:0] CH1_TXPMARESETMASK, + input CH1_TXPOLARITY, + input CH1_TXPRBSINERR, + input [3:0] CH1_TXPRBSPTN, + input CH1_TXPROGDIVRESET, + input CH1_TXQPRBSEN, + input [1:0] CH1_TXRESETMODE, + input CH1_TXSPCSEQADV, + input CH1_TXUSRCLK, + input CH1_TXUSRCLK2, + input CH1_TXUSRRDY, + input [10:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPRST, + input DRPWE, + input FECCTRLRX0BITSLIPFS, + input FECCTRLRX1BITSLIPFS, + input GTGREFCLK2PLL, + input GTNORTHREFCLK, + input GTREFCLK, + input GTSOUTHREFCLK, + input [7:0] PLLFBDIV, + input PLLMONCLK, + input PLLPD, + input [2:0] PLLREFCLKSEL, + input PLLRESET, + input PLLRESETBYPASSMODE, + input [1:0] PLLRESETMASK, + input [15:0] PLLRSVDIN, + input RCALENB, + input [25:0] SDMDATA, + input SDMTOGGLE +); + +// define constants + localparam MODULE_NAME = "GTM_DUAL"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "GTM_DUAL_dr.v" +`else + reg [15:0] A_CFG_REG = A_CFG; + reg [15:0] A_SDM_DATA_CFG0_REG = A_SDM_DATA_CFG0; + reg [15:0] A_SDM_DATA_CFG1_REG = A_SDM_DATA_CFG1; + reg [15:0] BIAS_CFG0_REG = BIAS_CFG0; + reg [15:0] BIAS_CFG1_REG = BIAS_CFG1; + reg [15:0] BIAS_CFG2_REG = BIAS_CFG2; + reg [15:0] BIAS_CFG3_REG = BIAS_CFG3; + reg [15:0] BIAS_CFG4_REG = BIAS_CFG4; + reg [15:0] BIAS_CFG5_REG = BIAS_CFG5; + reg [15:0] BIAS_CFG6_REG = BIAS_CFG6; + reg [15:0] BIAS_CFG7_REG = BIAS_CFG7; + reg [15:0] CH0_A_CH_CFG0_REG = CH0_A_CH_CFG0; + reg [15:0] CH0_A_CH_CFG1_REG = CH0_A_CH_CFG1; + reg [15:0] CH0_A_CH_CFG2_REG = CH0_A_CH_CFG2; + reg [15:0] CH0_A_CH_CFG3_REG = CH0_A_CH_CFG3; + reg [15:0] CH0_A_CH_CFG4_REG = CH0_A_CH_CFG4; + reg [15:0] CH0_A_CH_CFG5_REG = CH0_A_CH_CFG5; + reg [15:0] CH0_A_CH_CFG6_REG = CH0_A_CH_CFG6; + reg [15:0] CH0_RST_LP_CFG0_REG = CH0_RST_LP_CFG0; + reg [15:0] CH0_RST_LP_CFG1_REG = CH0_RST_LP_CFG1; + reg [15:0] CH0_RST_LP_CFG2_REG = CH0_RST_LP_CFG2; + reg [15:0] CH0_RST_LP_CFG3_REG = CH0_RST_LP_CFG3; + reg [15:0] CH0_RST_LP_CFG4_REG = CH0_RST_LP_CFG4; + reg [15:0] CH0_RST_LP_ID_CFG0_REG = CH0_RST_LP_ID_CFG0; + reg [15:0] CH0_RST_LP_ID_CFG1_REG = CH0_RST_LP_ID_CFG1; + reg [15:0] CH0_RST_TIME_CFG0_REG = CH0_RST_TIME_CFG0; + reg [15:0] CH0_RST_TIME_CFG1_REG = CH0_RST_TIME_CFG1; + reg [15:0] CH0_RST_TIME_CFG2_REG = CH0_RST_TIME_CFG2; + reg [15:0] CH0_RST_TIME_CFG3_REG = CH0_RST_TIME_CFG3; + reg [15:0] CH0_RST_TIME_CFG4_REG = CH0_RST_TIME_CFG4; + reg [15:0] CH0_RST_TIME_CFG5_REG = CH0_RST_TIME_CFG5; + reg [15:0] CH0_RST_TIME_CFG6_REG = CH0_RST_TIME_CFG6; + reg [15:0] CH0_RX_ADC_CFG0_REG = CH0_RX_ADC_CFG0; + reg [15:0] CH0_RX_ADC_CFG1_REG = CH0_RX_ADC_CFG1; + reg [15:0] CH0_RX_ANA_CFG0_REG = CH0_RX_ANA_CFG0; + reg [15:0] CH0_RX_ANA_CFG1_REG = CH0_RX_ANA_CFG1; + reg [15:0] CH0_RX_ANA_CFG2_REG = CH0_RX_ANA_CFG2; + reg [15:0] CH0_RX_APT_CFG0A_REG = CH0_RX_APT_CFG0A; + reg [15:0] CH0_RX_APT_CFG0B_REG = CH0_RX_APT_CFG0B; + reg [15:0] CH0_RX_APT_CFG10A_REG = CH0_RX_APT_CFG10A; + reg [15:0] CH0_RX_APT_CFG10B_REG = CH0_RX_APT_CFG10B; + reg [15:0] CH0_RX_APT_CFG11A_REG = CH0_RX_APT_CFG11A; + reg [15:0] CH0_RX_APT_CFG11B_REG = CH0_RX_APT_CFG11B; + reg [15:0] CH0_RX_APT_CFG12A_REG = CH0_RX_APT_CFG12A; + reg [15:0] CH0_RX_APT_CFG12B_REG = CH0_RX_APT_CFG12B; + reg [15:0] CH0_RX_APT_CFG13A_REG = CH0_RX_APT_CFG13A; + reg [15:0] CH0_RX_APT_CFG13B_REG = CH0_RX_APT_CFG13B; + reg [15:0] CH0_RX_APT_CFG14A_REG = CH0_RX_APT_CFG14A; + reg [15:0] CH0_RX_APT_CFG14B_REG = CH0_RX_APT_CFG14B; + reg [15:0] CH0_RX_APT_CFG15A_REG = CH0_RX_APT_CFG15A; + reg [15:0] CH0_RX_APT_CFG15B_REG = CH0_RX_APT_CFG15B; + reg [15:0] CH0_RX_APT_CFG16A_REG = CH0_RX_APT_CFG16A; + reg [15:0] CH0_RX_APT_CFG16B_REG = CH0_RX_APT_CFG16B; + reg [15:0] CH0_RX_APT_CFG17A_REG = CH0_RX_APT_CFG17A; + reg [15:0] CH0_RX_APT_CFG17B_REG = CH0_RX_APT_CFG17B; + reg [15:0] CH0_RX_APT_CFG18A_REG = CH0_RX_APT_CFG18A; + reg [15:0] CH0_RX_APT_CFG18B_REG = CH0_RX_APT_CFG18B; + reg [15:0] CH0_RX_APT_CFG19A_REG = CH0_RX_APT_CFG19A; + reg [15:0] CH0_RX_APT_CFG19B_REG = CH0_RX_APT_CFG19B; + reg [15:0] CH0_RX_APT_CFG1A_REG = CH0_RX_APT_CFG1A; + reg [15:0] CH0_RX_APT_CFG1B_REG = CH0_RX_APT_CFG1B; + reg [15:0] CH0_RX_APT_CFG20A_REG = CH0_RX_APT_CFG20A; + reg [15:0] CH0_RX_APT_CFG20B_REG = CH0_RX_APT_CFG20B; + reg [15:0] CH0_RX_APT_CFG21A_REG = CH0_RX_APT_CFG21A; + reg [15:0] CH0_RX_APT_CFG21B_REG = CH0_RX_APT_CFG21B; + reg [15:0] CH0_RX_APT_CFG22A_REG = CH0_RX_APT_CFG22A; + reg [15:0] CH0_RX_APT_CFG22B_REG = CH0_RX_APT_CFG22B; + reg [15:0] CH0_RX_APT_CFG23A_REG = CH0_RX_APT_CFG23A; + reg [15:0] CH0_RX_APT_CFG23B_REG = CH0_RX_APT_CFG23B; + reg [15:0] CH0_RX_APT_CFG24A_REG = CH0_RX_APT_CFG24A; + reg [15:0] CH0_RX_APT_CFG24B_REG = CH0_RX_APT_CFG24B; + reg [15:0] CH0_RX_APT_CFG25A_REG = CH0_RX_APT_CFG25A; + reg [15:0] CH0_RX_APT_CFG25B_REG = CH0_RX_APT_CFG25B; + reg [15:0] CH0_RX_APT_CFG26A_REG = CH0_RX_APT_CFG26A; + reg [15:0] CH0_RX_APT_CFG26B_REG = CH0_RX_APT_CFG26B; + reg [15:0] CH0_RX_APT_CFG27A_REG = CH0_RX_APT_CFG27A; + reg [15:0] CH0_RX_APT_CFG27B_REG = CH0_RX_APT_CFG27B; + reg [15:0] CH0_RX_APT_CFG28A_REG = CH0_RX_APT_CFG28A; + reg [15:0] CH0_RX_APT_CFG28B_REG = CH0_RX_APT_CFG28B; + reg [15:0] CH0_RX_APT_CFG2A_REG = CH0_RX_APT_CFG2A; + reg [15:0] CH0_RX_APT_CFG2B_REG = CH0_RX_APT_CFG2B; + reg [15:0] CH0_RX_APT_CFG3A_REG = CH0_RX_APT_CFG3A; + reg [15:0] CH0_RX_APT_CFG3B_REG = CH0_RX_APT_CFG3B; + reg [15:0] CH0_RX_APT_CFG4A_REG = CH0_RX_APT_CFG4A; + reg [15:0] CH0_RX_APT_CFG4B_REG = CH0_RX_APT_CFG4B; + reg [15:0] CH0_RX_APT_CFG5A_REG = CH0_RX_APT_CFG5A; + reg [15:0] CH0_RX_APT_CFG5B_REG = CH0_RX_APT_CFG5B; + reg [15:0] CH0_RX_APT_CFG6A_REG = CH0_RX_APT_CFG6A; + reg [15:0] CH0_RX_APT_CFG6B_REG = CH0_RX_APT_CFG6B; + reg [15:0] CH0_RX_APT_CFG7A_REG = CH0_RX_APT_CFG7A; + reg [15:0] CH0_RX_APT_CFG7B_REG = CH0_RX_APT_CFG7B; + reg [15:0] CH0_RX_APT_CFG8A_REG = CH0_RX_APT_CFG8A; + reg [15:0] CH0_RX_APT_CFG8B_REG = CH0_RX_APT_CFG8B; + reg [15:0] CH0_RX_APT_CFG9A_REG = CH0_RX_APT_CFG9A; + reg [15:0] CH0_RX_APT_CFG9B_REG = CH0_RX_APT_CFG9B; + reg [15:0] CH0_RX_APT_CTRL_CFG2_REG = CH0_RX_APT_CTRL_CFG2; + reg [15:0] CH0_RX_APT_CTRL_CFG3_REG = CH0_RX_APT_CTRL_CFG3; + reg [15:0] CH0_RX_CAL_CFG0A_REG = CH0_RX_CAL_CFG0A; + reg [15:0] CH0_RX_CAL_CFG0B_REG = CH0_RX_CAL_CFG0B; + reg [15:0] CH0_RX_CAL_CFG1A_REG = CH0_RX_CAL_CFG1A; + reg [15:0] CH0_RX_CAL_CFG1B_REG = CH0_RX_CAL_CFG1B; + reg [15:0] CH0_RX_CAL_CFG2A_REG = CH0_RX_CAL_CFG2A; + reg [15:0] CH0_RX_CAL_CFG2B_REG = CH0_RX_CAL_CFG2B; + reg [15:0] CH0_RX_CDR_CFG0A_REG = CH0_RX_CDR_CFG0A; + reg [15:0] CH0_RX_CDR_CFG0B_REG = CH0_RX_CDR_CFG0B; + reg [15:0] CH0_RX_CDR_CFG1A_REG = CH0_RX_CDR_CFG1A; + reg [15:0] CH0_RX_CDR_CFG1B_REG = CH0_RX_CDR_CFG1B; + reg [15:0] CH0_RX_CDR_CFG2A_REG = CH0_RX_CDR_CFG2A; + reg [15:0] CH0_RX_CDR_CFG2B_REG = CH0_RX_CDR_CFG2B; + reg [15:0] CH0_RX_CDR_CFG3A_REG = CH0_RX_CDR_CFG3A; + reg [15:0] CH0_RX_CDR_CFG3B_REG = CH0_RX_CDR_CFG3B; + reg [15:0] CH0_RX_CDR_CFG4A_REG = CH0_RX_CDR_CFG4A; + reg [15:0] CH0_RX_CDR_CFG4B_REG = CH0_RX_CDR_CFG4B; + reg [15:0] CH0_RX_CLKGN_CFG0_REG = CH0_RX_CLKGN_CFG0; + reg [15:0] CH0_RX_CLKGN_CFG1_REG = CH0_RX_CLKGN_CFG1; + reg [15:0] CH0_RX_CTLE_CFG0_REG = CH0_RX_CTLE_CFG0; + reg [15:0] CH0_RX_CTLE_CFG1_REG = CH0_RX_CTLE_CFG1; + reg [15:0] CH0_RX_CTLE_CFG2_REG = CH0_RX_CTLE_CFG2; + reg [15:0] CH0_RX_CTLE_CFG3_REG = CH0_RX_CTLE_CFG3; + reg [15:0] CH0_RX_DSP_CFG_REG = CH0_RX_DSP_CFG; + reg [15:0] CH0_RX_MON_CFG_REG = CH0_RX_MON_CFG; + reg [15:0] CH0_RX_PAD_CFG0_REG = CH0_RX_PAD_CFG0; + reg [15:0] CH0_RX_PAD_CFG1_REG = CH0_RX_PAD_CFG1; + reg [15:0] CH0_RX_PCS_CFG0_REG = CH0_RX_PCS_CFG0; + reg [15:0] CH0_RX_PCS_CFG1_REG = CH0_RX_PCS_CFG1; + reg [15:0] CH0_TX_ANA_CFG0_REG = CH0_TX_ANA_CFG0; + reg [15:0] CH0_TX_ANA_CFG1_REG = CH0_TX_ANA_CFG1; + reg [15:0] CH0_TX_ANA_CFG2_REG = CH0_TX_ANA_CFG2; + reg [15:0] CH0_TX_ANA_CFG3_REG = CH0_TX_ANA_CFG3; + reg [15:0] CH0_TX_ANA_CFG4_REG = CH0_TX_ANA_CFG4; + reg [15:0] CH0_TX_CAL_CFG0_REG = CH0_TX_CAL_CFG0; + reg [15:0] CH0_TX_CAL_CFG1_REG = CH0_TX_CAL_CFG1; + reg [15:0] CH0_TX_DRV_CFG0_REG = CH0_TX_DRV_CFG0; + reg [15:0] CH0_TX_DRV_CFG1_REG = CH0_TX_DRV_CFG1; + reg [15:0] CH0_TX_DRV_CFG2_REG = CH0_TX_DRV_CFG2; + reg [15:0] CH0_TX_DRV_CFG3_REG = CH0_TX_DRV_CFG3; + reg [15:0] CH0_TX_DRV_CFG4_REG = CH0_TX_DRV_CFG4; + reg [15:0] CH0_TX_DRV_CFG5_REG = CH0_TX_DRV_CFG5; + reg [15:0] CH0_TX_LPBK_CFG0_REG = CH0_TX_LPBK_CFG0; + reg [15:0] CH0_TX_LPBK_CFG1_REG = CH0_TX_LPBK_CFG1; + reg [15:0] CH0_TX_PCS_CFG0_REG = CH0_TX_PCS_CFG0; + reg [15:0] CH0_TX_PCS_CFG1_REG = CH0_TX_PCS_CFG1; + reg [15:0] CH0_TX_PCS_CFG10_REG = CH0_TX_PCS_CFG10; + reg [15:0] CH0_TX_PCS_CFG11_REG = CH0_TX_PCS_CFG11; + reg [15:0] CH0_TX_PCS_CFG12_REG = CH0_TX_PCS_CFG12; + reg [15:0] CH0_TX_PCS_CFG13_REG = CH0_TX_PCS_CFG13; + reg [15:0] CH0_TX_PCS_CFG14_REG = CH0_TX_PCS_CFG14; + reg [15:0] CH0_TX_PCS_CFG15_REG = CH0_TX_PCS_CFG15; + reg [15:0] CH0_TX_PCS_CFG16_REG = CH0_TX_PCS_CFG16; + reg [15:0] CH0_TX_PCS_CFG17_REG = CH0_TX_PCS_CFG17; + reg [15:0] CH0_TX_PCS_CFG2_REG = CH0_TX_PCS_CFG2; + reg [15:0] CH0_TX_PCS_CFG3_REG = CH0_TX_PCS_CFG3; + reg [15:0] CH0_TX_PCS_CFG4_REG = CH0_TX_PCS_CFG4; + reg [15:0] CH0_TX_PCS_CFG5_REG = CH0_TX_PCS_CFG5; + reg [15:0] CH0_TX_PCS_CFG6_REG = CH0_TX_PCS_CFG6; + reg [15:0] CH0_TX_PCS_CFG7_REG = CH0_TX_PCS_CFG7; + reg [15:0] CH0_TX_PCS_CFG8_REG = CH0_TX_PCS_CFG8; + reg [15:0] CH0_TX_PCS_CFG9_REG = CH0_TX_PCS_CFG9; + reg [15:0] CH1_A_CH_CFG0_REG = CH1_A_CH_CFG0; + reg [15:0] CH1_A_CH_CFG1_REG = CH1_A_CH_CFG1; + reg [15:0] CH1_A_CH_CFG2_REG = CH1_A_CH_CFG2; + reg [15:0] CH1_A_CH_CFG3_REG = CH1_A_CH_CFG3; + reg [15:0] CH1_A_CH_CFG4_REG = CH1_A_CH_CFG4; + reg [15:0] CH1_A_CH_CFG5_REG = CH1_A_CH_CFG5; + reg [15:0] CH1_A_CH_CFG6_REG = CH1_A_CH_CFG6; + reg [15:0] CH1_RST_LP_CFG0_REG = CH1_RST_LP_CFG0; + reg [15:0] CH1_RST_LP_CFG1_REG = CH1_RST_LP_CFG1; + reg [15:0] CH1_RST_LP_CFG2_REG = CH1_RST_LP_CFG2; + reg [15:0] CH1_RST_LP_CFG3_REG = CH1_RST_LP_CFG3; + reg [15:0] CH1_RST_LP_CFG4_REG = CH1_RST_LP_CFG4; + reg [15:0] CH1_RST_LP_ID_CFG0_REG = CH1_RST_LP_ID_CFG0; + reg [15:0] CH1_RST_LP_ID_CFG1_REG = CH1_RST_LP_ID_CFG1; + reg [15:0] CH1_RST_TIME_CFG0_REG = CH1_RST_TIME_CFG0; + reg [15:0] CH1_RST_TIME_CFG1_REG = CH1_RST_TIME_CFG1; + reg [15:0] CH1_RST_TIME_CFG2_REG = CH1_RST_TIME_CFG2; + reg [15:0] CH1_RST_TIME_CFG3_REG = CH1_RST_TIME_CFG3; + reg [15:0] CH1_RST_TIME_CFG4_REG = CH1_RST_TIME_CFG4; + reg [15:0] CH1_RST_TIME_CFG5_REG = CH1_RST_TIME_CFG5; + reg [15:0] CH1_RST_TIME_CFG6_REG = CH1_RST_TIME_CFG6; + reg [15:0] CH1_RX_ADC_CFG0_REG = CH1_RX_ADC_CFG0; + reg [15:0] CH1_RX_ADC_CFG1_REG = CH1_RX_ADC_CFG1; + reg [15:0] CH1_RX_ANA_CFG0_REG = CH1_RX_ANA_CFG0; + reg [15:0] CH1_RX_ANA_CFG1_REG = CH1_RX_ANA_CFG1; + reg [15:0] CH1_RX_ANA_CFG2_REG = CH1_RX_ANA_CFG2; + reg [15:0] CH1_RX_APT_CFG0A_REG = CH1_RX_APT_CFG0A; + reg [15:0] CH1_RX_APT_CFG0B_REG = CH1_RX_APT_CFG0B; + reg [15:0] CH1_RX_APT_CFG10A_REG = CH1_RX_APT_CFG10A; + reg [15:0] CH1_RX_APT_CFG10B_REG = CH1_RX_APT_CFG10B; + reg [15:0] CH1_RX_APT_CFG11A_REG = CH1_RX_APT_CFG11A; + reg [15:0] CH1_RX_APT_CFG11B_REG = CH1_RX_APT_CFG11B; + reg [15:0] CH1_RX_APT_CFG12A_REG = CH1_RX_APT_CFG12A; + reg [15:0] CH1_RX_APT_CFG12B_REG = CH1_RX_APT_CFG12B; + reg [15:0] CH1_RX_APT_CFG13A_REG = CH1_RX_APT_CFG13A; + reg [15:0] CH1_RX_APT_CFG13B_REG = CH1_RX_APT_CFG13B; + reg [15:0] CH1_RX_APT_CFG14A_REG = CH1_RX_APT_CFG14A; + reg [15:0] CH1_RX_APT_CFG14B_REG = CH1_RX_APT_CFG14B; + reg [15:0] CH1_RX_APT_CFG15A_REG = CH1_RX_APT_CFG15A; + reg [15:0] CH1_RX_APT_CFG15B_REG = CH1_RX_APT_CFG15B; + reg [15:0] CH1_RX_APT_CFG16A_REG = CH1_RX_APT_CFG16A; + reg [15:0] CH1_RX_APT_CFG16B_REG = CH1_RX_APT_CFG16B; + reg [15:0] CH1_RX_APT_CFG17A_REG = CH1_RX_APT_CFG17A; + reg [15:0] CH1_RX_APT_CFG17B_REG = CH1_RX_APT_CFG17B; + reg [15:0] CH1_RX_APT_CFG18A_REG = CH1_RX_APT_CFG18A; + reg [15:0] CH1_RX_APT_CFG18B_REG = CH1_RX_APT_CFG18B; + reg [15:0] CH1_RX_APT_CFG19A_REG = CH1_RX_APT_CFG19A; + reg [15:0] CH1_RX_APT_CFG19B_REG = CH1_RX_APT_CFG19B; + reg [15:0] CH1_RX_APT_CFG1A_REG = CH1_RX_APT_CFG1A; + reg [15:0] CH1_RX_APT_CFG1B_REG = CH1_RX_APT_CFG1B; + reg [15:0] CH1_RX_APT_CFG20A_REG = CH1_RX_APT_CFG20A; + reg [15:0] CH1_RX_APT_CFG20B_REG = CH1_RX_APT_CFG20B; + reg [15:0] CH1_RX_APT_CFG21A_REG = CH1_RX_APT_CFG21A; + reg [15:0] CH1_RX_APT_CFG21B_REG = CH1_RX_APT_CFG21B; + reg [15:0] CH1_RX_APT_CFG22A_REG = CH1_RX_APT_CFG22A; + reg [15:0] CH1_RX_APT_CFG22B_REG = CH1_RX_APT_CFG22B; + reg [15:0] CH1_RX_APT_CFG23A_REG = CH1_RX_APT_CFG23A; + reg [15:0] CH1_RX_APT_CFG23B_REG = CH1_RX_APT_CFG23B; + reg [15:0] CH1_RX_APT_CFG24A_REG = CH1_RX_APT_CFG24A; + reg [15:0] CH1_RX_APT_CFG24B_REG = CH1_RX_APT_CFG24B; + reg [15:0] CH1_RX_APT_CFG25A_REG = CH1_RX_APT_CFG25A; + reg [15:0] CH1_RX_APT_CFG25B_REG = CH1_RX_APT_CFG25B; + reg [15:0] CH1_RX_APT_CFG26A_REG = CH1_RX_APT_CFG26A; + reg [15:0] CH1_RX_APT_CFG26B_REG = CH1_RX_APT_CFG26B; + reg [15:0] CH1_RX_APT_CFG27A_REG = CH1_RX_APT_CFG27A; + reg [15:0] CH1_RX_APT_CFG27B_REG = CH1_RX_APT_CFG27B; + reg [15:0] CH1_RX_APT_CFG28A_REG = CH1_RX_APT_CFG28A; + reg [15:0] CH1_RX_APT_CFG28B_REG = CH1_RX_APT_CFG28B; + reg [15:0] CH1_RX_APT_CFG2A_REG = CH1_RX_APT_CFG2A; + reg [15:0] CH1_RX_APT_CFG2B_REG = CH1_RX_APT_CFG2B; + reg [15:0] CH1_RX_APT_CFG3A_REG = CH1_RX_APT_CFG3A; + reg [15:0] CH1_RX_APT_CFG3B_REG = CH1_RX_APT_CFG3B; + reg [15:0] CH1_RX_APT_CFG4A_REG = CH1_RX_APT_CFG4A; + reg [15:0] CH1_RX_APT_CFG4B_REG = CH1_RX_APT_CFG4B; + reg [15:0] CH1_RX_APT_CFG5A_REG = CH1_RX_APT_CFG5A; + reg [15:0] CH1_RX_APT_CFG5B_REG = CH1_RX_APT_CFG5B; + reg [15:0] CH1_RX_APT_CFG6A_REG = CH1_RX_APT_CFG6A; + reg [15:0] CH1_RX_APT_CFG6B_REG = CH1_RX_APT_CFG6B; + reg [15:0] CH1_RX_APT_CFG7A_REG = CH1_RX_APT_CFG7A; + reg [15:0] CH1_RX_APT_CFG7B_REG = CH1_RX_APT_CFG7B; + reg [15:0] CH1_RX_APT_CFG8A_REG = CH1_RX_APT_CFG8A; + reg [15:0] CH1_RX_APT_CFG8B_REG = CH1_RX_APT_CFG8B; + reg [15:0] CH1_RX_APT_CFG9A_REG = CH1_RX_APT_CFG9A; + reg [15:0] CH1_RX_APT_CFG9B_REG = CH1_RX_APT_CFG9B; + reg [15:0] CH1_RX_APT_CTRL_CFG2_REG = CH1_RX_APT_CTRL_CFG2; + reg [15:0] CH1_RX_APT_CTRL_CFG3_REG = CH1_RX_APT_CTRL_CFG3; + reg [15:0] CH1_RX_CAL_CFG0A_REG = CH1_RX_CAL_CFG0A; + reg [15:0] CH1_RX_CAL_CFG0B_REG = CH1_RX_CAL_CFG0B; + reg [15:0] CH1_RX_CAL_CFG1A_REG = CH1_RX_CAL_CFG1A; + reg [15:0] CH1_RX_CAL_CFG1B_REG = CH1_RX_CAL_CFG1B; + reg [15:0] CH1_RX_CAL_CFG2A_REG = CH1_RX_CAL_CFG2A; + reg [15:0] CH1_RX_CAL_CFG2B_REG = CH1_RX_CAL_CFG2B; + reg [15:0] CH1_RX_CDR_CFG0A_REG = CH1_RX_CDR_CFG0A; + reg [15:0] CH1_RX_CDR_CFG0B_REG = CH1_RX_CDR_CFG0B; + reg [15:0] CH1_RX_CDR_CFG1A_REG = CH1_RX_CDR_CFG1A; + reg [15:0] CH1_RX_CDR_CFG1B_REG = CH1_RX_CDR_CFG1B; + reg [15:0] CH1_RX_CDR_CFG2A_REG = CH1_RX_CDR_CFG2A; + reg [15:0] CH1_RX_CDR_CFG2B_REG = CH1_RX_CDR_CFG2B; + reg [15:0] CH1_RX_CDR_CFG3A_REG = CH1_RX_CDR_CFG3A; + reg [15:0] CH1_RX_CDR_CFG3B_REG = CH1_RX_CDR_CFG3B; + reg [15:0] CH1_RX_CDR_CFG4A_REG = CH1_RX_CDR_CFG4A; + reg [15:0] CH1_RX_CDR_CFG4B_REG = CH1_RX_CDR_CFG4B; + reg [15:0] CH1_RX_CLKGN_CFG0_REG = CH1_RX_CLKGN_CFG0; + reg [15:0] CH1_RX_CLKGN_CFG1_REG = CH1_RX_CLKGN_CFG1; + reg [15:0] CH1_RX_CTLE_CFG0_REG = CH1_RX_CTLE_CFG0; + reg [15:0] CH1_RX_CTLE_CFG1_REG = CH1_RX_CTLE_CFG1; + reg [15:0] CH1_RX_CTLE_CFG2_REG = CH1_RX_CTLE_CFG2; + reg [15:0] CH1_RX_CTLE_CFG3_REG = CH1_RX_CTLE_CFG3; + reg [15:0] CH1_RX_DSP_CFG_REG = CH1_RX_DSP_CFG; + reg [15:0] CH1_RX_MON_CFG_REG = CH1_RX_MON_CFG; + reg [15:0] CH1_RX_PAD_CFG0_REG = CH1_RX_PAD_CFG0; + reg [15:0] CH1_RX_PAD_CFG1_REG = CH1_RX_PAD_CFG1; + reg [15:0] CH1_RX_PCS_CFG0_REG = CH1_RX_PCS_CFG0; + reg [15:0] CH1_RX_PCS_CFG1_REG = CH1_RX_PCS_CFG1; + reg [15:0] CH1_TX_ANA_CFG0_REG = CH1_TX_ANA_CFG0; + reg [15:0] CH1_TX_ANA_CFG1_REG = CH1_TX_ANA_CFG1; + reg [15:0] CH1_TX_ANA_CFG2_REG = CH1_TX_ANA_CFG2; + reg [15:0] CH1_TX_ANA_CFG3_REG = CH1_TX_ANA_CFG3; + reg [15:0] CH1_TX_ANA_CFG4_REG = CH1_TX_ANA_CFG4; + reg [15:0] CH1_TX_CAL_CFG0_REG = CH1_TX_CAL_CFG0; + reg [15:0] CH1_TX_CAL_CFG1_REG = CH1_TX_CAL_CFG1; + reg [15:0] CH1_TX_DRV_CFG0_REG = CH1_TX_DRV_CFG0; + reg [15:0] CH1_TX_DRV_CFG1_REG = CH1_TX_DRV_CFG1; + reg [15:0] CH1_TX_DRV_CFG2_REG = CH1_TX_DRV_CFG2; + reg [15:0] CH1_TX_DRV_CFG3_REG = CH1_TX_DRV_CFG3; + reg [15:0] CH1_TX_DRV_CFG4_REG = CH1_TX_DRV_CFG4; + reg [15:0] CH1_TX_DRV_CFG5_REG = CH1_TX_DRV_CFG5; + reg [15:0] CH1_TX_LPBK_CFG0_REG = CH1_TX_LPBK_CFG0; + reg [15:0] CH1_TX_LPBK_CFG1_REG = CH1_TX_LPBK_CFG1; + reg [15:0] CH1_TX_PCS_CFG0_REG = CH1_TX_PCS_CFG0; + reg [15:0] CH1_TX_PCS_CFG1_REG = CH1_TX_PCS_CFG1; + reg [15:0] CH1_TX_PCS_CFG10_REG = CH1_TX_PCS_CFG10; + reg [15:0] CH1_TX_PCS_CFG11_REG = CH1_TX_PCS_CFG11; + reg [15:0] CH1_TX_PCS_CFG12_REG = CH1_TX_PCS_CFG12; + reg [15:0] CH1_TX_PCS_CFG13_REG = CH1_TX_PCS_CFG13; + reg [15:0] CH1_TX_PCS_CFG14_REG = CH1_TX_PCS_CFG14; + reg [15:0] CH1_TX_PCS_CFG15_REG = CH1_TX_PCS_CFG15; + reg [15:0] CH1_TX_PCS_CFG16_REG = CH1_TX_PCS_CFG16; + reg [15:0] CH1_TX_PCS_CFG17_REG = CH1_TX_PCS_CFG17; + reg [15:0] CH1_TX_PCS_CFG2_REG = CH1_TX_PCS_CFG2; + reg [15:0] CH1_TX_PCS_CFG3_REG = CH1_TX_PCS_CFG3; + reg [15:0] CH1_TX_PCS_CFG4_REG = CH1_TX_PCS_CFG4; + reg [15:0] CH1_TX_PCS_CFG5_REG = CH1_TX_PCS_CFG5; + reg [15:0] CH1_TX_PCS_CFG6_REG = CH1_TX_PCS_CFG6; + reg [15:0] CH1_TX_PCS_CFG7_REG = CH1_TX_PCS_CFG7; + reg [15:0] CH1_TX_PCS_CFG8_REG = CH1_TX_PCS_CFG8; + reg [15:0] CH1_TX_PCS_CFG9_REG = CH1_TX_PCS_CFG9; + real DATARATE_REG = DATARATE; + reg [15:0] DRPEN_CFG_REG = DRPEN_CFG; + reg [15:0] FEC_CFG0_REG = FEC_CFG0; + reg [15:0] FEC_CFG1_REG = FEC_CFG1; + reg [15:0] FEC_CFG10_REG = FEC_CFG10; + reg [15:0] FEC_CFG11_REG = FEC_CFG11; + reg [15:0] FEC_CFG12_REG = FEC_CFG12; + reg [15:0] FEC_CFG13_REG = FEC_CFG13; + reg [15:0] FEC_CFG14_REG = FEC_CFG14; + reg [15:0] FEC_CFG15_REG = FEC_CFG15; + reg [15:0] FEC_CFG16_REG = FEC_CFG16; + reg [15:0] FEC_CFG17_REG = FEC_CFG17; + reg [15:0] FEC_CFG18_REG = FEC_CFG18; + reg [15:0] FEC_CFG19_REG = FEC_CFG19; + reg [15:0] FEC_CFG2_REG = FEC_CFG2; + reg [15:0] FEC_CFG20_REG = FEC_CFG20; + reg [15:0] FEC_CFG21_REG = FEC_CFG21; + reg [15:0] FEC_CFG22_REG = FEC_CFG22; + reg [15:0] FEC_CFG23_REG = FEC_CFG23; + reg [15:0] FEC_CFG24_REG = FEC_CFG24; + reg [15:0] FEC_CFG25_REG = FEC_CFG25; + reg [15:0] FEC_CFG26_REG = FEC_CFG26; + reg [15:0] FEC_CFG27_REG = FEC_CFG27; + reg [15:0] FEC_CFG3_REG = FEC_CFG3; + reg [15:0] FEC_CFG4_REG = FEC_CFG4; + reg [15:0] FEC_CFG5_REG = FEC_CFG5; + reg [15:0] FEC_CFG6_REG = FEC_CFG6; + reg [15:0] FEC_CFG7_REG = FEC_CFG7; + reg [15:0] FEC_CFG8_REG = FEC_CFG8; + reg [15:0] FEC_CFG9_REG = FEC_CFG9; + reg [48:1] FEC_MODE_REG = FEC_MODE; + real INS_LOSS_NYQ_REG = INS_LOSS_NYQ; + reg [8:0] INTERFACE_WIDTH_REG = INTERFACE_WIDTH; + reg [32:1] MODULATION_MODE_REG = MODULATION_MODE; + reg [15:0] PLL_CFG0_REG = PLL_CFG0; + reg [15:0] PLL_CFG1_REG = PLL_CFG1; + reg [15:0] PLL_CFG2_REG = PLL_CFG2; + reg [15:0] PLL_CFG3_REG = PLL_CFG3; + reg [15:0] PLL_CFG4_REG = PLL_CFG4; + reg [15:0] PLL_CFG5_REG = PLL_CFG5; + reg [15:0] PLL_CFG6_REG = PLL_CFG6; + reg [15:0] PLL_CRS_CTRL_CFG0_REG = PLL_CRS_CTRL_CFG0; + reg [15:0] PLL_CRS_CTRL_CFG1_REG = PLL_CRS_CTRL_CFG1; + reg [0:0] PLL_IPS_PIN_EN_REG = PLL_IPS_PIN_EN; + reg [2:0] PLL_IPS_REFCLK_SEL_REG = PLL_IPS_REFCLK_SEL; + reg [0:0] RCALSAP_TESTEN_REG = RCALSAP_TESTEN; + reg [0:0] RCAL_APROBE_REG = RCAL_APROBE; + reg [15:0] RST_CFG_REG = {RST_CFG[15:1], (SIM_RESET_SPEEDUP != "FALSE"? 1'b1 : 1'b0)}; + reg [15:0] RST_PLL_CFG0_REG = RST_PLL_CFG0; + reg [15:0] SAP_CFG0_REG = SAP_CFG0; + reg [15:0] SDM_CFG0_REG = SDM_CFG0; + reg [15:0] SDM_CFG1_REG = SDM_CFG1; + reg [15:0] SDM_CFG2_REG = SDM_CFG2; + reg [15:0] SDM_SEED_CFG0_REG = SDM_SEED_CFG0; + reg [15:0] SDM_SEED_CFG1_REG = SDM_SEED_CFG1; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + reg [10:0] TX_AMPLITUDE_SWING_REG = TX_AMPLITUDE_SWING; +`endif + +`ifdef XIL_XECLIB + wire [63:0] DATARATE_BIN; + wire [63:0] INS_LOSS_NYQ_BIN; +`else + reg [63:0] DATARATE_BIN; + reg [63:0] INS_LOSS_NYQ_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CH0_AXISTLAST_out; + wire CH0_AXISTVALID_out; + wire CH0_DMONITOROUTCLK_out; + wire CH0_GTMTXN_out; + wire CH0_GTMTXP_out; + wire CH0_RESETEXCEPTION_out; + wire CH0_RXDATAISAM_out; + wire CH0_RXDATASTART_out; + wire CH0_RXOUTCLK_out; + wire CH0_RXPMARESETDONE_out; + wire CH0_RXPRBSERR_out; + wire CH0_RXPRBSLOCKED_out; + wire CH0_RXPRGDIVRESETDONE_out; + wire CH0_RXPROGDIVCLK_out; + wire CH0_RXRESETDONE_out; + wire CH0_TXOUTCLK_out; + wire CH0_TXPMARESETDONE_out; + wire CH0_TXPRGDIVRESETDONE_out; + wire CH0_TXPROGDIVCLK_out; + wire CH0_TXRESETDONE_out; + wire CH1_AXISTLAST_out; + wire CH1_AXISTVALID_out; + wire CH1_DMONITOROUTCLK_out; + wire CH1_GTMTXN_out; + wire CH1_GTMTXP_out; + wire CH1_RESETEXCEPTION_out; + wire CH1_RXDATAISAM_out; + wire CH1_RXDATASTART_out; + wire CH1_RXOUTCLK_out; + wire CH1_RXPMARESETDONE_out; + wire CH1_RXPRBSERR_out; + wire CH1_RXPRBSLOCKED_out; + wire CH1_RXPRGDIVRESETDONE_out; + wire CH1_RXPROGDIVCLK_out; + wire CH1_RXRESETDONE_out; + wire CH1_TXOUTCLK_out; + wire CH1_TXPMARESETDONE_out; + wire CH1_TXPRGDIVRESETDONE_out; + wire CH1_TXPROGDIVCLK_out; + wire CH1_TXRESETDONE_out; + wire CLKTESTSIG2PAD_out; + wire DMONITOROUTPLLCLK_out; + wire DRPRDY_out; + wire FECRX0ALIGNED_out; + wire FECRX0CORRCWINC_out; + wire FECRX0CWINC_out; + wire FECRX0UNCORRCWINC_out; + wire FECRX1ALIGNED_out; + wire FECRX1CORRCWINC_out; + wire FECRX1CWINC_out; + wire FECRX1UNCORRCWINC_out; + wire FECTRXLN0LOCK_out; + wire FECTRXLN1LOCK_out; + wire FECTRXLN2LOCK_out; + wire FECTRXLN3LOCK_out; + wire GTPOWERGOOD_out; + wire PLLFBCLKLOST_out; + wire PLLLOCK_out; + wire PLLREFCLKLOST_out; + wire PLLREFCLKMONITOR_out; + wire PLLRESETDONE_out; + wire RCALCMP_out; + wire REFCLK2BUFG_out; + wire REFCLKPDB_SA_out; + wire RXRECCLK0_out; + wire RXRECCLK1_out; + wire [14:0] CH0_PCSSCANOUT_out; + wire [14:0] CH1_PCSSCANOUT_out; + wire [14:0] FECRXLN0DLY_out; + wire [14:0] FECRXLN1DLY_out; + wire [14:0] FECRXLN2DLY_out; + wire [14:0] FECRXLN3DLY_out; + wire [15:0] CH0_PCSRSVDOUT_out; + wire [15:0] CH0_PMARSVDOUT_out; + wire [15:0] CH1_PCSRSVDOUT_out; + wire [15:0] CH1_PMARSVDOUT_out; + wire [15:0] DRPDO_out; + wire [15:0] PLLRSVDOUT_out; + wire [199:0] FECSCANOUT_out; + wire [1:0] CH0_TXBUFSTATUS_out; + wire [1:0] CH1_TXBUFSTATUS_out; + wire [1:0] FECRXLN0MAPPING_out; + wire [1:0] FECRXLN1MAPPING_out; + wire [1:0] FECRXLN2MAPPING_out; + wire [1:0] FECRXLN3MAPPING_out; + wire [24:0] CH0_PMASCANOUT_out; + wire [24:0] CH1_PMASCANOUT_out; + wire [255:0] CH0_RXDATA_out; + wire [255:0] CH1_RXDATA_out; + wire [27:0] CH0_AXISTDATA_out; + wire [27:0] CH1_AXISTDATA_out; + wire [2:0] CH0_RXBUFSTATUS_out; + wire [2:0] CH1_RXBUFSTATUS_out; + wire [31:0] CH0_DMONITOROUT_out; + wire [31:0] CH1_DMONITOROUT_out; + wire [3:0] CH0_RXDATAFLAGS_out; + wire [3:0] CH1_RXDATAFLAGS_out; + wire [3:0] FECRXLN0ERRCNTINC_out; + wire [3:0] FECRXLN1ERRCNTINC_out; + wire [3:0] FECRXLN2ERRCNTINC_out; + wire [3:0] FECRXLN3ERRCNTINC_out; + wire [4:0] RCALOUT_out; + wire [7:0] FECRXLN0BITERR0TO1INC_out; + wire [7:0] FECRXLN0BITERR1TO0INC_out; + wire [7:0] FECRXLN1BITERR0TO1INC_out; + wire [7:0] FECRXLN1BITERR1TO0INC_out; + wire [7:0] FECRXLN2BITERR0TO1INC_out; + wire [7:0] FECRXLN2BITERR1TO0INC_out; + wire [7:0] FECRXLN3BITERR0TO1INC_out; + wire [7:0] FECRXLN3BITERR1TO0INC_out; + wire [7:0] PLLSCANOUT_out; + + wire BGBYPASSB_in; + wire BGMONITORENB_in; + wire BGPDB_in; + wire BGRCALOVRDENB_in; + wire CH0_AXISEN_in; + wire CH0_AXISRST_in; + wire CH0_AXISTRDY_in; + wire CH0_BSRSERIAL_in; + wire CH0_CFGRESET_in; + wire CH0_DMONFIFORESET_in; + wire CH0_DMONITORCLK_in; + wire CH0_GTMRXN_in; + wire CH0_GTMRXP_in; + wire CH0_GTRXRESET_in; + wire CH0_GTTXRESET_in; + wire CH0_PCSSCANENB_in; + wire CH0_PCSSCANMODEB_in; + wire CH0_PCSSCANRSTB_in; + wire CH0_PCSSCANRSTEN_in; + wire CH0_PMASCANENB_in; + wire CH0_PMASCANMODEB_in; + wire CH0_PMASCANRSTEN_in; + wire CH0_RESETOVRD_in; + wire CH0_RXADAPTRESET_in; + wire CH0_RXADCCALRESET_in; + wire CH0_RXADCCLKGENRESET_in; + wire CH0_RXBUFRESET_in; + wire CH0_RXCDRFREQOS_in; + wire CH0_RXCDRFRRESET_in; + wire CH0_RXCDRHOLD_in; + wire CH0_RXCDRINCPCTRL_in; + wire CH0_RXCDROVRDEN_in; + wire CH0_RXCDRPHRESET_in; + wire CH0_RXDFERESET_in; + wire CH0_RXDSPRESET_in; + wire CH0_RXEQTRAINING_in; + wire CH0_RXEYESCANRESET_in; + wire CH0_RXFECRESET_in; + wire CH0_RXPCSRESET_in; + wire CH0_RXPMARESET_in; + wire CH0_RXPOLARITY_in; + wire CH0_RXPRBSCNTSTOP_in; + wire CH0_RXPRBSCSCNTRST_in; + wire CH0_RXPROGDIVRESET_in; + wire CH0_RXQPRBSEN_in; + wire CH0_RXSPCSEQADV_in; + wire CH0_RXUSRCLK2_in; + wire CH0_RXUSRCLK_in; + wire CH0_RXUSRRDY_in; + wire CH0_RXUSRSTART_in; + wire CH0_RXUSRSTOP_in; + wire CH0_TSTCLK0_in; + wire CH0_TSTCLK1_in; + wire CH0_TXCKALRESET_in; + wire CH0_TXDATASTART_in; + wire CH0_TXFECRESET_in; + wire CH0_TXINHIBIT_in; + wire CH0_TXMUXDCDEXHOLD_in; + wire CH0_TXMUXDCDORWREN_in; + wire CH0_TXPCSRESET_in; + wire CH0_TXPMARESET_in; + wire CH0_TXPOLARITY_in; + wire CH0_TXPRBSINERR_in; + wire CH0_TXPROGDIVRESET_in; + wire CH0_TXQPRBSEN_in; + wire CH0_TXSPCSEQADV_in; + wire CH0_TXUSRCLK2_in; + wire CH0_TXUSRCLK_in; + wire CH0_TXUSRRDY_in; + wire CH1_AXISEN_in; + wire CH1_AXISRST_in; + wire CH1_AXISTRDY_in; + wire CH1_BSRSERIAL_in; + wire CH1_CFGRESET_in; + wire CH1_DMONFIFORESET_in; + wire CH1_DMONITORCLK_in; + wire CH1_GTMRXN_in; + wire CH1_GTMRXP_in; + wire CH1_GTRXRESET_in; + wire CH1_GTTXRESET_in; + wire CH1_PCSSCANENB_in; + wire CH1_PCSSCANMODEB_in; + wire CH1_PCSSCANRSTB_in; + wire CH1_PCSSCANRSTEN_in; + wire CH1_PMASCANENB_in; + wire CH1_PMASCANMODEB_in; + wire CH1_PMASCANRSTEN_in; + wire CH1_RESETOVRD_in; + wire CH1_RXADAPTRESET_in; + wire CH1_RXADCCALRESET_in; + wire CH1_RXADCCLKGENRESET_in; + wire CH1_RXBUFRESET_in; + wire CH1_RXCDRFREQOS_in; + wire CH1_RXCDRFRRESET_in; + wire CH1_RXCDRHOLD_in; + wire CH1_RXCDRINCPCTRL_in; + wire CH1_RXCDROVRDEN_in; + wire CH1_RXCDRPHRESET_in; + wire CH1_RXDFERESET_in; + wire CH1_RXDSPRESET_in; + wire CH1_RXEQTRAINING_in; + wire CH1_RXEYESCANRESET_in; + wire CH1_RXFECRESET_in; + wire CH1_RXPCSRESET_in; + wire CH1_RXPMARESET_in; + wire CH1_RXPOLARITY_in; + wire CH1_RXPRBSCNTSTOP_in; + wire CH1_RXPRBSCSCNTRST_in; + wire CH1_RXPROGDIVRESET_in; + wire CH1_RXQPRBSEN_in; + wire CH1_RXSPCSEQADV_in; + wire CH1_RXUSRCLK2_in; + wire CH1_RXUSRCLK_in; + wire CH1_RXUSRRDY_in; + wire CH1_RXUSRSTART_in; + wire CH1_RXUSRSTOP_in; + wire CH1_TSTCLK0_in; + wire CH1_TSTCLK1_in; + wire CH1_TXCKALRESET_in; + wire CH1_TXDATASTART_in; + wire CH1_TXFECRESET_in; + wire CH1_TXINHIBIT_in; + wire CH1_TXMUXDCDEXHOLD_in; + wire CH1_TXMUXDCDORWREN_in; + wire CH1_TXPCSRESET_in; + wire CH1_TXPMARESET_in; + wire CH1_TXPOLARITY_in; + wire CH1_TXPRBSINERR_in; + wire CH1_TXPROGDIVRESET_in; + wire CH1_TXQPRBSEN_in; + wire CH1_TXSPCSEQADV_in; + wire CH1_TXUSRCLK2_in; + wire CH1_TXUSRCLK_in; + wire CH1_TXUSRRDY_in; + wire CLKTESTSIG_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPRST_in; + wire DRPWE_in; + wire FECCTRLRX0BITSLIPFS_in; + wire FECCTRLRX1BITSLIPFS_in; + wire FECSCANCLK_in; + wire FECSCANENB_in; + wire FECSCANMODEB_in; + wire FECSCANRSTB_in; + wire GTGREFCLK2PLL_in; + wire GTNORTHREFCLK_in; + wire GTREFCLKPD_in; + wire GTREFCLK_in; + wire GTSOUTHREFCLK_in; + wire PLLMONCLK_in; + wire PLLPD_in; + wire PLLRESETBYPASSMODE_in; + wire PLLRESET_in; + wire PLLSCANENB_in; + wire PLLSCANMODEB_in; + wire PLLSCANRSTEN_in; + wire RCALENB_in; + wire REFCLK2HROW_in; + wire SDMTOGGLE_in; + wire [10:0] DRPADDR_in; + wire [14:0] CH0_PCSSCANIN_in; + wire [14:0] CH1_PCSSCANIN_in; + wire [15:0] CH0_PCSRSVDIN_in; + wire [15:0] CH0_PMARSVDIN_in; + wire [15:0] CH1_PCSRSVDIN_in; + wire [15:0] CH1_PMARSVDIN_in; + wire [15:0] DRPDI_in; + wire [15:0] PLLRSVDIN_in; + wire [199:0] FECSCANIN_in; + wire [1:0] CH0_PCSSCANCLK_in; + wire [1:0] CH0_RXRESETMODE_in; + wire [1:0] CH0_TXPCSRESETMASK_in; + wire [1:0] CH0_TXPMARESETMASK_in; + wire [1:0] CH0_TXRESETMODE_in; + wire [1:0] CH1_PCSSCANCLK_in; + wire [1:0] CH1_RXRESETMODE_in; + wire [1:0] CH1_TXPCSRESETMASK_in; + wire [1:0] CH1_TXPMARESETMASK_in; + wire [1:0] CH1_TXRESETMODE_in; + wire [1:0] PLLRESETMASK_in; + wire [1:0] RCALSEL_in; + wire [24:0] CH0_PMASCANIN_in; + wire [24:0] CH1_PMASCANIN_in; + wire [255:0] CH0_TXDATA_in; + wire [255:0] CH1_TXDATA_in; + wire [25:0] SDMDATA_in; + wire [2:0] CH0_LOOPBACK_in; + wire [2:0] CH0_RXOUTCLKSEL_in; + wire [2:0] CH0_TXOUTCLKSEL_in; + wire [2:0] CH1_LOOPBACK_in; + wire [2:0] CH1_RXOUTCLKSEL_in; + wire [2:0] CH1_TXOUTCLKSEL_in; + wire [2:0] PLLREFCLKSEL_in; + wire [3:0] CH0_RXPCSRESETMASK_in; + wire [3:0] CH0_RXPRBSPTN_in; + wire [3:0] CH0_TXEMPPRE2_in; + wire [3:0] CH0_TXPRBSPTN_in; + wire [3:0] CH1_RXPCSRESETMASK_in; + wire [3:0] CH1_RXPRBSPTN_in; + wire [3:0] CH1_TXEMPPRE2_in; + wire [3:0] CH1_TXPRBSPTN_in; + wire [3:0] PLLSCANCLK_in; + wire [4:0] BGRCALOVRD_in; + wire [4:0] CH0_TXDRVAMP_in; + wire [4:0] CH0_TXEMPPOST_in; + wire [4:0] CH0_TXEMPPRE_in; + wire [4:0] CH1_TXDRVAMP_in; + wire [4:0] CH1_TXEMPPOST_in; + wire [4:0] CH1_TXEMPPRE_in; + wire [5:0] CH0_TXCTLFIRDAT_in; + wire [5:0] CH0_TXEMPMAIN_in; + wire [5:0] CH1_TXCTLFIRDAT_in; + wire [5:0] CH1_TXEMPMAIN_in; + wire [7:0] CH0_RXPMARESETMASK_in; + wire [7:0] CH1_RXPMARESETMASK_in; + wire [7:0] PLLFBDIV_in; + wire [7:0] PLLSCANIN_in; + wire [8:0] CH0_PMASCANCLK_in; + wire [8:0] CH1_PMASCANCLK_in; + +`ifdef XIL_TIMING + wire CH0_AXISEN_delay; + wire CH0_AXISTRDY_delay; + wire CH0_RXEQTRAINING_delay; + wire CH0_RXPOLARITY_delay; + wire CH0_RXPRBSCNTSTOP_delay; + wire CH0_RXQPRBSEN_delay; + wire CH0_RXUSRCLK2_delay; + wire CH0_RXUSRCLK_delay; + wire CH0_TXDATASTART_delay; + wire CH0_TXINHIBIT_delay; + wire CH0_TXPOLARITY_delay; + wire CH0_TXPRBSINERR_delay; + wire CH0_TXQPRBSEN_delay; + wire CH0_TXUSRCLK2_delay; + wire CH0_TXUSRCLK_delay; + wire CH1_AXISEN_delay; + wire CH1_AXISTRDY_delay; + wire CH1_RXEQTRAINING_delay; + wire CH1_RXPOLARITY_delay; + wire CH1_RXPRBSCNTSTOP_delay; + wire CH1_RXQPRBSEN_delay; + wire CH1_RXUSRCLK2_delay; + wire CH1_RXUSRCLK_delay; + wire CH1_TXDATASTART_delay; + wire CH1_TXINHIBIT_delay; + wire CH1_TXPOLARITY_delay; + wire CH1_TXPRBSINERR_delay; + wire CH1_TXQPRBSEN_delay; + wire CH1_TXUSRCLK2_delay; + wire CH1_TXUSRCLK_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire FECCTRLRX0BITSLIPFS_delay; + wire FECCTRLRX1BITSLIPFS_delay; + wire [10:0] DRPADDR_delay; + wire [15:0] DRPDI_delay; + wire [255:0] CH0_TXDATA_delay; + wire [255:0] CH1_TXDATA_delay; + wire [3:0] CH0_RXPRBSPTN_delay; + wire [3:0] CH0_TXPRBSPTN_delay; + wire [3:0] CH1_RXPRBSPTN_delay; + wire [3:0] CH1_TXPRBSPTN_delay; +`endif + + + //declare internal signals + integer CH0_GTMTXN_integer; + integer CH0_GTMTXP_integer; + integer CH1_GTMTXN_integer; + integer CH1_GTMTXP_integer; + integer CH0_GTMRXN_integer; + integer CH0_GTMRXP_integer; + integer CH1_GTMRXN_integer; + integer CH1_GTMRXP_integer; + + + assign CH0_AXISTDATA = CH0_AXISTDATA_out; + assign CH0_AXISTLAST = CH0_AXISTLAST_out; + assign CH0_AXISTVALID = CH0_AXISTVALID_out; + assign CH0_DMONITOROUT = CH0_DMONITOROUT_out; + assign CH0_DMONITOROUTCLK = CH0_DMONITOROUTCLK_out; + assign CH0_GTMTXN = CH0_GTMTXN_out; + assign CH0_GTMTXP = CH0_GTMTXP_out; + assign CH0_PCSRSVDOUT = CH0_PCSRSVDOUT_out; + assign CH0_PMARSVDOUT = CH0_PMARSVDOUT_out; + assign CH0_RESETEXCEPTION = CH0_RESETEXCEPTION_out; + assign CH0_RXBUFSTATUS = CH0_RXBUFSTATUS_out; + assign CH0_RXDATA = CH0_RXDATA_out; + assign CH0_RXDATAFLAGS = CH0_RXDATAFLAGS_out; + assign CH0_RXDATAISAM = CH0_RXDATAISAM_out; + assign CH0_RXDATASTART = CH0_RXDATASTART_out; + assign CH0_RXOUTCLK = CH0_RXOUTCLK_out; + assign CH0_RXPMARESETDONE = CH0_RXPMARESETDONE_out; + assign CH0_RXPRBSERR = CH0_RXPRBSERR_out; + assign CH0_RXPRBSLOCKED = CH0_RXPRBSLOCKED_out; + assign CH0_RXPRGDIVRESETDONE = CH0_RXPRGDIVRESETDONE_out; + assign CH0_RXPROGDIVCLK = CH0_RXPROGDIVCLK_out; + assign CH0_RXRESETDONE = CH0_RXRESETDONE_out; + assign CH0_TXBUFSTATUS = CH0_TXBUFSTATUS_out; + assign CH0_TXOUTCLK = CH0_TXOUTCLK_out; + assign CH0_TXPMARESETDONE = CH0_TXPMARESETDONE_out; + assign CH0_TXPRGDIVRESETDONE = CH0_TXPRGDIVRESETDONE_out; + assign CH0_TXPROGDIVCLK = CH0_TXPROGDIVCLK_out; + assign CH0_TXRESETDONE = CH0_TXRESETDONE_out; + assign CH1_AXISTDATA = CH1_AXISTDATA_out; + assign CH1_AXISTLAST = CH1_AXISTLAST_out; + assign CH1_AXISTVALID = CH1_AXISTVALID_out; + assign CH1_DMONITOROUT = CH1_DMONITOROUT_out; + assign CH1_DMONITOROUTCLK = CH1_DMONITOROUTCLK_out; + assign CH1_GTMTXN = CH1_GTMTXN_out; + assign CH1_GTMTXP = CH1_GTMTXP_out; + assign CH1_PCSRSVDOUT = CH1_PCSRSVDOUT_out; + assign CH1_PMARSVDOUT = CH1_PMARSVDOUT_out; + assign CH1_RESETEXCEPTION = CH1_RESETEXCEPTION_out; + assign CH1_RXBUFSTATUS = CH1_RXBUFSTATUS_out; + assign CH1_RXDATA = CH1_RXDATA_out; + assign CH1_RXDATAFLAGS = CH1_RXDATAFLAGS_out; + assign CH1_RXDATAISAM = CH1_RXDATAISAM_out; + assign CH1_RXDATASTART = CH1_RXDATASTART_out; + assign CH1_RXOUTCLK = CH1_RXOUTCLK_out; + assign CH1_RXPMARESETDONE = CH1_RXPMARESETDONE_out; + assign CH1_RXPRBSERR = CH1_RXPRBSERR_out; + assign CH1_RXPRBSLOCKED = CH1_RXPRBSLOCKED_out; + assign CH1_RXPRGDIVRESETDONE = CH1_RXPRGDIVRESETDONE_out; + assign CH1_RXPROGDIVCLK = CH1_RXPROGDIVCLK_out; + assign CH1_RXRESETDONE = CH1_RXRESETDONE_out; + assign CH1_TXBUFSTATUS = CH1_TXBUFSTATUS_out; + assign CH1_TXOUTCLK = CH1_TXOUTCLK_out; + assign CH1_TXPMARESETDONE = CH1_TXPMARESETDONE_out; + assign CH1_TXPRGDIVRESETDONE = CH1_TXPRGDIVRESETDONE_out; + assign CH1_TXPROGDIVCLK = CH1_TXPROGDIVCLK_out; + assign CH1_TXRESETDONE = CH1_TXRESETDONE_out; + assign CLKTESTSIG2PAD = CLKTESTSIG2PAD_out; + assign DMONITOROUTPLLCLK = DMONITOROUTPLLCLK_out; + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign FECRX0ALIGNED = FECRX0ALIGNED_out; + assign FECRX0CORRCWINC = FECRX0CORRCWINC_out; + assign FECRX0CWINC = FECRX0CWINC_out; + assign FECRX0UNCORRCWINC = FECRX0UNCORRCWINC_out; + assign FECRX1ALIGNED = FECRX1ALIGNED_out; + assign FECRX1CORRCWINC = FECRX1CORRCWINC_out; + assign FECRX1CWINC = FECRX1CWINC_out; + assign FECRX1UNCORRCWINC = FECRX1UNCORRCWINC_out; + assign FECRXLN0BITERR0TO1INC = FECRXLN0BITERR0TO1INC_out; + assign FECRXLN0BITERR1TO0INC = FECRXLN0BITERR1TO0INC_out; + assign FECRXLN0DLY = FECRXLN0DLY_out; + assign FECRXLN0ERRCNTINC = FECRXLN0ERRCNTINC_out; + assign FECRXLN0MAPPING = FECRXLN0MAPPING_out; + assign FECRXLN1BITERR0TO1INC = FECRXLN1BITERR0TO1INC_out; + assign FECRXLN1BITERR1TO0INC = FECRXLN1BITERR1TO0INC_out; + assign FECRXLN1DLY = FECRXLN1DLY_out; + assign FECRXLN1ERRCNTINC = FECRXLN1ERRCNTINC_out; + assign FECRXLN1MAPPING = FECRXLN1MAPPING_out; + assign FECRXLN2BITERR0TO1INC = FECRXLN2BITERR0TO1INC_out; + assign FECRXLN2BITERR1TO0INC = FECRXLN2BITERR1TO0INC_out; + assign FECRXLN2DLY = FECRXLN2DLY_out; + assign FECRXLN2ERRCNTINC = FECRXLN2ERRCNTINC_out; + assign FECRXLN2MAPPING = FECRXLN2MAPPING_out; + assign FECRXLN3BITERR0TO1INC = FECRXLN3BITERR0TO1INC_out; + assign FECRXLN3BITERR1TO0INC = FECRXLN3BITERR1TO0INC_out; + assign FECRXLN3DLY = FECRXLN3DLY_out; + assign FECRXLN3ERRCNTINC = FECRXLN3ERRCNTINC_out; + assign FECRXLN3MAPPING = FECRXLN3MAPPING_out; + assign FECTRXLN0LOCK = FECTRXLN0LOCK_out; + assign FECTRXLN1LOCK = FECTRXLN1LOCK_out; + assign FECTRXLN2LOCK = FECTRXLN2LOCK_out; + assign FECTRXLN3LOCK = FECTRXLN3LOCK_out; + assign GTPOWERGOOD = GTPOWERGOOD_out; + assign PLLFBCLKLOST = PLLFBCLKLOST_out; + assign PLLLOCK = PLLLOCK_out; + assign PLLREFCLKLOST = PLLREFCLKLOST_out; + assign PLLREFCLKMONITOR = PLLREFCLKMONITOR_out; + assign PLLRESETDONE = PLLRESETDONE_out; + assign PLLRSVDOUT = PLLRSVDOUT_out; + assign RCALCMP = RCALCMP_out; + assign RCALOUT = RCALOUT_out; + assign RXRECCLK0 = RXRECCLK0_out; + assign RXRECCLK1 = RXRECCLK1_out; + +`ifdef XIL_TIMING + assign CH0_AXISEN_in = (CH0_AXISEN !== 1'bz) && CH0_AXISEN_delay; // rv 0 + assign CH0_AXISTRDY_in = (CH0_AXISTRDY !== 1'bz) && CH0_AXISTRDY_delay; // rv 0 + assign CH0_RXEQTRAINING_in = (CH0_RXEQTRAINING !== 1'bz) && CH0_RXEQTRAINING_delay; // rv 0 + assign CH0_RXPOLARITY_in = (CH0_RXPOLARITY !== 1'bz) && CH0_RXPOLARITY_delay; // rv 0 + assign CH0_RXPRBSCNTSTOP_in = (CH0_RXPRBSCNTSTOP !== 1'bz) && CH0_RXPRBSCNTSTOP_delay; // rv 0 + assign CH0_RXPRBSPTN_in[0] = (CH0_RXPRBSPTN[0] !== 1'bz) && CH0_RXPRBSPTN_delay[0]; // rv 0 + assign CH0_RXPRBSPTN_in[1] = (CH0_RXPRBSPTN[1] !== 1'bz) && CH0_RXPRBSPTN_delay[1]; // rv 0 + assign CH0_RXPRBSPTN_in[2] = (CH0_RXPRBSPTN[2] !== 1'bz) && CH0_RXPRBSPTN_delay[2]; // rv 0 + assign CH0_RXPRBSPTN_in[3] = (CH0_RXPRBSPTN[3] !== 1'bz) && CH0_RXPRBSPTN_delay[3]; // rv 0 + assign CH0_RXQPRBSEN_in = (CH0_RXQPRBSEN !== 1'bz) && CH0_RXQPRBSEN_delay; // rv 0 + assign CH0_RXUSRCLK2_in = (CH0_RXUSRCLK2 !== 1'bz) && CH0_RXUSRCLK2_delay; // rv 0 + assign CH0_RXUSRCLK_in = (CH0_RXUSRCLK !== 1'bz) && CH0_RXUSRCLK_delay; // rv 0 + assign CH0_TXDATASTART_in = (CH0_TXDATASTART !== 1'bz) && CH0_TXDATASTART_delay; // rv 0 + assign CH0_TXDATA_in[0] = (CH0_TXDATA[0] !== 1'bz) && CH0_TXDATA_delay[0]; // rv 0 + assign CH0_TXDATA_in[100] = (CH0_TXDATA[100] !== 1'bz) && CH0_TXDATA_delay[100]; // rv 0 + assign CH0_TXDATA_in[101] = (CH0_TXDATA[101] !== 1'bz) && CH0_TXDATA_delay[101]; // rv 0 + assign CH0_TXDATA_in[102] = (CH0_TXDATA[102] !== 1'bz) && CH0_TXDATA_delay[102]; // rv 0 + assign CH0_TXDATA_in[103] = (CH0_TXDATA[103] !== 1'bz) && CH0_TXDATA_delay[103]; // rv 0 + assign CH0_TXDATA_in[104] = (CH0_TXDATA[104] !== 1'bz) && CH0_TXDATA_delay[104]; // rv 0 + assign CH0_TXDATA_in[105] = (CH0_TXDATA[105] !== 1'bz) && CH0_TXDATA_delay[105]; // rv 0 + assign CH0_TXDATA_in[106] = (CH0_TXDATA[106] !== 1'bz) && CH0_TXDATA_delay[106]; // rv 0 + assign CH0_TXDATA_in[107] = (CH0_TXDATA[107] !== 1'bz) && CH0_TXDATA_delay[107]; // rv 0 + assign CH0_TXDATA_in[108] = (CH0_TXDATA[108] !== 1'bz) && CH0_TXDATA_delay[108]; // rv 0 + assign CH0_TXDATA_in[109] = (CH0_TXDATA[109] !== 1'bz) && CH0_TXDATA_delay[109]; // rv 0 + assign CH0_TXDATA_in[10] = (CH0_TXDATA[10] !== 1'bz) && CH0_TXDATA_delay[10]; // rv 0 + assign CH0_TXDATA_in[110] = (CH0_TXDATA[110] !== 1'bz) && CH0_TXDATA_delay[110]; // rv 0 + assign CH0_TXDATA_in[111] = (CH0_TXDATA[111] !== 1'bz) && CH0_TXDATA_delay[111]; // rv 0 + assign CH0_TXDATA_in[112] = (CH0_TXDATA[112] !== 1'bz) && CH0_TXDATA_delay[112]; // rv 0 + assign CH0_TXDATA_in[113] = (CH0_TXDATA[113] !== 1'bz) && CH0_TXDATA_delay[113]; // rv 0 + assign CH0_TXDATA_in[114] = (CH0_TXDATA[114] !== 1'bz) && CH0_TXDATA_delay[114]; // rv 0 + assign CH0_TXDATA_in[115] = (CH0_TXDATA[115] !== 1'bz) && CH0_TXDATA_delay[115]; // rv 0 + assign CH0_TXDATA_in[116] = (CH0_TXDATA[116] !== 1'bz) && CH0_TXDATA_delay[116]; // rv 0 + assign CH0_TXDATA_in[117] = (CH0_TXDATA[117] !== 1'bz) && CH0_TXDATA_delay[117]; // rv 0 + assign CH0_TXDATA_in[118] = (CH0_TXDATA[118] !== 1'bz) && CH0_TXDATA_delay[118]; // rv 0 + assign CH0_TXDATA_in[119] = (CH0_TXDATA[119] !== 1'bz) && CH0_TXDATA_delay[119]; // rv 0 + assign CH0_TXDATA_in[11] = (CH0_TXDATA[11] !== 1'bz) && CH0_TXDATA_delay[11]; // rv 0 + assign CH0_TXDATA_in[120] = (CH0_TXDATA[120] !== 1'bz) && CH0_TXDATA_delay[120]; // rv 0 + assign CH0_TXDATA_in[121] = (CH0_TXDATA[121] !== 1'bz) && CH0_TXDATA_delay[121]; // rv 0 + assign CH0_TXDATA_in[122] = (CH0_TXDATA[122] !== 1'bz) && CH0_TXDATA_delay[122]; // rv 0 + assign CH0_TXDATA_in[123] = (CH0_TXDATA[123] !== 1'bz) && CH0_TXDATA_delay[123]; // rv 0 + assign CH0_TXDATA_in[124] = (CH0_TXDATA[124] !== 1'bz) && CH0_TXDATA_delay[124]; // rv 0 + assign CH0_TXDATA_in[125] = (CH0_TXDATA[125] !== 1'bz) && CH0_TXDATA_delay[125]; // rv 0 + assign CH0_TXDATA_in[126] = (CH0_TXDATA[126] !== 1'bz) && CH0_TXDATA_delay[126]; // rv 0 + assign CH0_TXDATA_in[127] = (CH0_TXDATA[127] !== 1'bz) && CH0_TXDATA_delay[127]; // rv 0 + assign CH0_TXDATA_in[128] = (CH0_TXDATA[128] !== 1'bz) && CH0_TXDATA_delay[128]; // rv 0 + assign CH0_TXDATA_in[129] = (CH0_TXDATA[129] !== 1'bz) && CH0_TXDATA_delay[129]; // rv 0 + assign CH0_TXDATA_in[12] = (CH0_TXDATA[12] !== 1'bz) && CH0_TXDATA_delay[12]; // rv 0 + assign CH0_TXDATA_in[130] = (CH0_TXDATA[130] !== 1'bz) && CH0_TXDATA_delay[130]; // rv 0 + assign CH0_TXDATA_in[131] = (CH0_TXDATA[131] !== 1'bz) && CH0_TXDATA_delay[131]; // rv 0 + assign CH0_TXDATA_in[132] = (CH0_TXDATA[132] !== 1'bz) && CH0_TXDATA_delay[132]; // rv 0 + assign CH0_TXDATA_in[133] = (CH0_TXDATA[133] !== 1'bz) && CH0_TXDATA_delay[133]; // rv 0 + assign CH0_TXDATA_in[134] = (CH0_TXDATA[134] !== 1'bz) && CH0_TXDATA_delay[134]; // rv 0 + assign CH0_TXDATA_in[135] = (CH0_TXDATA[135] !== 1'bz) && CH0_TXDATA_delay[135]; // rv 0 + assign CH0_TXDATA_in[136] = (CH0_TXDATA[136] !== 1'bz) && CH0_TXDATA_delay[136]; // rv 0 + assign CH0_TXDATA_in[137] = (CH0_TXDATA[137] !== 1'bz) && CH0_TXDATA_delay[137]; // rv 0 + assign CH0_TXDATA_in[138] = (CH0_TXDATA[138] !== 1'bz) && CH0_TXDATA_delay[138]; // rv 0 + assign CH0_TXDATA_in[139] = (CH0_TXDATA[139] !== 1'bz) && CH0_TXDATA_delay[139]; // rv 0 + assign CH0_TXDATA_in[13] = (CH0_TXDATA[13] !== 1'bz) && CH0_TXDATA_delay[13]; // rv 0 + assign CH0_TXDATA_in[140] = (CH0_TXDATA[140] !== 1'bz) && CH0_TXDATA_delay[140]; // rv 0 + assign CH0_TXDATA_in[141] = (CH0_TXDATA[141] !== 1'bz) && CH0_TXDATA_delay[141]; // rv 0 + assign CH0_TXDATA_in[142] = (CH0_TXDATA[142] !== 1'bz) && CH0_TXDATA_delay[142]; // rv 0 + assign CH0_TXDATA_in[143] = (CH0_TXDATA[143] !== 1'bz) && CH0_TXDATA_delay[143]; // rv 0 + assign CH0_TXDATA_in[144] = (CH0_TXDATA[144] !== 1'bz) && CH0_TXDATA_delay[144]; // rv 0 + assign CH0_TXDATA_in[145] = (CH0_TXDATA[145] !== 1'bz) && CH0_TXDATA_delay[145]; // rv 0 + assign CH0_TXDATA_in[146] = (CH0_TXDATA[146] !== 1'bz) && CH0_TXDATA_delay[146]; // rv 0 + assign CH0_TXDATA_in[147] = (CH0_TXDATA[147] !== 1'bz) && CH0_TXDATA_delay[147]; // rv 0 + assign CH0_TXDATA_in[148] = (CH0_TXDATA[148] !== 1'bz) && CH0_TXDATA_delay[148]; // rv 0 + assign CH0_TXDATA_in[149] = (CH0_TXDATA[149] !== 1'bz) && CH0_TXDATA_delay[149]; // rv 0 + assign CH0_TXDATA_in[14] = (CH0_TXDATA[14] !== 1'bz) && CH0_TXDATA_delay[14]; // rv 0 + assign CH0_TXDATA_in[150] = (CH0_TXDATA[150] !== 1'bz) && CH0_TXDATA_delay[150]; // rv 0 + assign CH0_TXDATA_in[151] = (CH0_TXDATA[151] !== 1'bz) && CH0_TXDATA_delay[151]; // rv 0 + assign CH0_TXDATA_in[152] = (CH0_TXDATA[152] !== 1'bz) && CH0_TXDATA_delay[152]; // rv 0 + assign CH0_TXDATA_in[153] = (CH0_TXDATA[153] !== 1'bz) && CH0_TXDATA_delay[153]; // rv 0 + assign CH0_TXDATA_in[154] = (CH0_TXDATA[154] !== 1'bz) && CH0_TXDATA_delay[154]; // rv 0 + assign CH0_TXDATA_in[155] = (CH0_TXDATA[155] !== 1'bz) && CH0_TXDATA_delay[155]; // rv 0 + assign CH0_TXDATA_in[156] = (CH0_TXDATA[156] !== 1'bz) && CH0_TXDATA_delay[156]; // rv 0 + assign CH0_TXDATA_in[157] = (CH0_TXDATA[157] !== 1'bz) && CH0_TXDATA_delay[157]; // rv 0 + assign CH0_TXDATA_in[158] = (CH0_TXDATA[158] !== 1'bz) && CH0_TXDATA_delay[158]; // rv 0 + assign CH0_TXDATA_in[159] = (CH0_TXDATA[159] !== 1'bz) && CH0_TXDATA_delay[159]; // rv 0 + assign CH0_TXDATA_in[15] = (CH0_TXDATA[15] !== 1'bz) && CH0_TXDATA_delay[15]; // rv 0 + assign CH0_TXDATA_in[160] = (CH0_TXDATA[160] !== 1'bz) && CH0_TXDATA_delay[160]; // rv 0 + assign CH0_TXDATA_in[161] = (CH0_TXDATA[161] !== 1'bz) && CH0_TXDATA_delay[161]; // rv 0 + assign CH0_TXDATA_in[162] = (CH0_TXDATA[162] !== 1'bz) && CH0_TXDATA_delay[162]; // rv 0 + assign CH0_TXDATA_in[163] = (CH0_TXDATA[163] !== 1'bz) && CH0_TXDATA_delay[163]; // rv 0 + assign CH0_TXDATA_in[164] = (CH0_TXDATA[164] !== 1'bz) && CH0_TXDATA_delay[164]; // rv 0 + assign CH0_TXDATA_in[165] = (CH0_TXDATA[165] !== 1'bz) && CH0_TXDATA_delay[165]; // rv 0 + assign CH0_TXDATA_in[166] = (CH0_TXDATA[166] !== 1'bz) && CH0_TXDATA_delay[166]; // rv 0 + assign CH0_TXDATA_in[167] = (CH0_TXDATA[167] !== 1'bz) && CH0_TXDATA_delay[167]; // rv 0 + assign CH0_TXDATA_in[168] = (CH0_TXDATA[168] !== 1'bz) && CH0_TXDATA_delay[168]; // rv 0 + assign CH0_TXDATA_in[169] = (CH0_TXDATA[169] !== 1'bz) && CH0_TXDATA_delay[169]; // rv 0 + assign CH0_TXDATA_in[16] = (CH0_TXDATA[16] !== 1'bz) && CH0_TXDATA_delay[16]; // rv 0 + assign CH0_TXDATA_in[170] = (CH0_TXDATA[170] !== 1'bz) && CH0_TXDATA_delay[170]; // rv 0 + assign CH0_TXDATA_in[171] = (CH0_TXDATA[171] !== 1'bz) && CH0_TXDATA_delay[171]; // rv 0 + assign CH0_TXDATA_in[172] = (CH0_TXDATA[172] !== 1'bz) && CH0_TXDATA_delay[172]; // rv 0 + assign CH0_TXDATA_in[173] = (CH0_TXDATA[173] !== 1'bz) && CH0_TXDATA_delay[173]; // rv 0 + assign CH0_TXDATA_in[174] = (CH0_TXDATA[174] !== 1'bz) && CH0_TXDATA_delay[174]; // rv 0 + assign CH0_TXDATA_in[175] = (CH0_TXDATA[175] !== 1'bz) && CH0_TXDATA_delay[175]; // rv 0 + assign CH0_TXDATA_in[176] = (CH0_TXDATA[176] !== 1'bz) && CH0_TXDATA_delay[176]; // rv 0 + assign CH0_TXDATA_in[177] = (CH0_TXDATA[177] !== 1'bz) && CH0_TXDATA_delay[177]; // rv 0 + assign CH0_TXDATA_in[178] = (CH0_TXDATA[178] !== 1'bz) && CH0_TXDATA_delay[178]; // rv 0 + assign CH0_TXDATA_in[179] = (CH0_TXDATA[179] !== 1'bz) && CH0_TXDATA_delay[179]; // rv 0 + assign CH0_TXDATA_in[17] = (CH0_TXDATA[17] !== 1'bz) && CH0_TXDATA_delay[17]; // rv 0 + assign CH0_TXDATA_in[180] = (CH0_TXDATA[180] !== 1'bz) && CH0_TXDATA_delay[180]; // rv 0 + assign CH0_TXDATA_in[181] = (CH0_TXDATA[181] !== 1'bz) && CH0_TXDATA_delay[181]; // rv 0 + assign CH0_TXDATA_in[182] = (CH0_TXDATA[182] !== 1'bz) && CH0_TXDATA_delay[182]; // rv 0 + assign CH0_TXDATA_in[183] = (CH0_TXDATA[183] !== 1'bz) && CH0_TXDATA_delay[183]; // rv 0 + assign CH0_TXDATA_in[184] = (CH0_TXDATA[184] !== 1'bz) && CH0_TXDATA_delay[184]; // rv 0 + assign CH0_TXDATA_in[185] = (CH0_TXDATA[185] !== 1'bz) && CH0_TXDATA_delay[185]; // rv 0 + assign CH0_TXDATA_in[186] = (CH0_TXDATA[186] !== 1'bz) && CH0_TXDATA_delay[186]; // rv 0 + assign CH0_TXDATA_in[187] = (CH0_TXDATA[187] !== 1'bz) && CH0_TXDATA_delay[187]; // rv 0 + assign CH0_TXDATA_in[188] = (CH0_TXDATA[188] !== 1'bz) && CH0_TXDATA_delay[188]; // rv 0 + assign CH0_TXDATA_in[189] = (CH0_TXDATA[189] !== 1'bz) && CH0_TXDATA_delay[189]; // rv 0 + assign CH0_TXDATA_in[18] = (CH0_TXDATA[18] !== 1'bz) && CH0_TXDATA_delay[18]; // rv 0 + assign CH0_TXDATA_in[190] = (CH0_TXDATA[190] !== 1'bz) && CH0_TXDATA_delay[190]; // rv 0 + assign CH0_TXDATA_in[191] = (CH0_TXDATA[191] !== 1'bz) && CH0_TXDATA_delay[191]; // rv 0 + assign CH0_TXDATA_in[192] = (CH0_TXDATA[192] !== 1'bz) && CH0_TXDATA_delay[192]; // rv 0 + assign CH0_TXDATA_in[193] = (CH0_TXDATA[193] !== 1'bz) && CH0_TXDATA_delay[193]; // rv 0 + assign CH0_TXDATA_in[194] = (CH0_TXDATA[194] !== 1'bz) && CH0_TXDATA_delay[194]; // rv 0 + assign CH0_TXDATA_in[195] = (CH0_TXDATA[195] !== 1'bz) && CH0_TXDATA_delay[195]; // rv 0 + assign CH0_TXDATA_in[196] = (CH0_TXDATA[196] !== 1'bz) && CH0_TXDATA_delay[196]; // rv 0 + assign CH0_TXDATA_in[197] = (CH0_TXDATA[197] !== 1'bz) && CH0_TXDATA_delay[197]; // rv 0 + assign CH0_TXDATA_in[198] = (CH0_TXDATA[198] !== 1'bz) && CH0_TXDATA_delay[198]; // rv 0 + assign CH0_TXDATA_in[199] = (CH0_TXDATA[199] !== 1'bz) && CH0_TXDATA_delay[199]; // rv 0 + assign CH0_TXDATA_in[19] = (CH0_TXDATA[19] !== 1'bz) && CH0_TXDATA_delay[19]; // rv 0 + assign CH0_TXDATA_in[1] = (CH0_TXDATA[1] !== 1'bz) && CH0_TXDATA_delay[1]; // rv 0 + assign CH0_TXDATA_in[200] = (CH0_TXDATA[200] !== 1'bz) && CH0_TXDATA_delay[200]; // rv 0 + assign CH0_TXDATA_in[201] = (CH0_TXDATA[201] !== 1'bz) && CH0_TXDATA_delay[201]; // rv 0 + assign CH0_TXDATA_in[202] = (CH0_TXDATA[202] !== 1'bz) && CH0_TXDATA_delay[202]; // rv 0 + assign CH0_TXDATA_in[203] = (CH0_TXDATA[203] !== 1'bz) && CH0_TXDATA_delay[203]; // rv 0 + assign CH0_TXDATA_in[204] = (CH0_TXDATA[204] !== 1'bz) && CH0_TXDATA_delay[204]; // rv 0 + assign CH0_TXDATA_in[205] = (CH0_TXDATA[205] !== 1'bz) && CH0_TXDATA_delay[205]; // rv 0 + assign CH0_TXDATA_in[206] = (CH0_TXDATA[206] !== 1'bz) && CH0_TXDATA_delay[206]; // rv 0 + assign CH0_TXDATA_in[207] = (CH0_TXDATA[207] !== 1'bz) && CH0_TXDATA_delay[207]; // rv 0 + assign CH0_TXDATA_in[208] = (CH0_TXDATA[208] !== 1'bz) && CH0_TXDATA_delay[208]; // rv 0 + assign CH0_TXDATA_in[209] = (CH0_TXDATA[209] !== 1'bz) && CH0_TXDATA_delay[209]; // rv 0 + assign CH0_TXDATA_in[20] = (CH0_TXDATA[20] !== 1'bz) && CH0_TXDATA_delay[20]; // rv 0 + assign CH0_TXDATA_in[210] = (CH0_TXDATA[210] !== 1'bz) && CH0_TXDATA_delay[210]; // rv 0 + assign CH0_TXDATA_in[211] = (CH0_TXDATA[211] !== 1'bz) && CH0_TXDATA_delay[211]; // rv 0 + assign CH0_TXDATA_in[212] = (CH0_TXDATA[212] !== 1'bz) && CH0_TXDATA_delay[212]; // rv 0 + assign CH0_TXDATA_in[213] = (CH0_TXDATA[213] !== 1'bz) && CH0_TXDATA_delay[213]; // rv 0 + assign CH0_TXDATA_in[214] = (CH0_TXDATA[214] !== 1'bz) && CH0_TXDATA_delay[214]; // rv 0 + assign CH0_TXDATA_in[215] = (CH0_TXDATA[215] !== 1'bz) && CH0_TXDATA_delay[215]; // rv 0 + assign CH0_TXDATA_in[216] = (CH0_TXDATA[216] !== 1'bz) && CH0_TXDATA_delay[216]; // rv 0 + assign CH0_TXDATA_in[217] = (CH0_TXDATA[217] !== 1'bz) && CH0_TXDATA_delay[217]; // rv 0 + assign CH0_TXDATA_in[218] = (CH0_TXDATA[218] !== 1'bz) && CH0_TXDATA_delay[218]; // rv 0 + assign CH0_TXDATA_in[219] = (CH0_TXDATA[219] !== 1'bz) && CH0_TXDATA_delay[219]; // rv 0 + assign CH0_TXDATA_in[21] = (CH0_TXDATA[21] !== 1'bz) && CH0_TXDATA_delay[21]; // rv 0 + assign CH0_TXDATA_in[220] = (CH0_TXDATA[220] !== 1'bz) && CH0_TXDATA_delay[220]; // rv 0 + assign CH0_TXDATA_in[221] = (CH0_TXDATA[221] !== 1'bz) && CH0_TXDATA_delay[221]; // rv 0 + assign CH0_TXDATA_in[222] = (CH0_TXDATA[222] !== 1'bz) && CH0_TXDATA_delay[222]; // rv 0 + assign CH0_TXDATA_in[223] = (CH0_TXDATA[223] !== 1'bz) && CH0_TXDATA_delay[223]; // rv 0 + assign CH0_TXDATA_in[224] = (CH0_TXDATA[224] !== 1'bz) && CH0_TXDATA_delay[224]; // rv 0 + assign CH0_TXDATA_in[225] = (CH0_TXDATA[225] !== 1'bz) && CH0_TXDATA_delay[225]; // rv 0 + assign CH0_TXDATA_in[226] = (CH0_TXDATA[226] !== 1'bz) && CH0_TXDATA_delay[226]; // rv 0 + assign CH0_TXDATA_in[227] = (CH0_TXDATA[227] !== 1'bz) && CH0_TXDATA_delay[227]; // rv 0 + assign CH0_TXDATA_in[228] = (CH0_TXDATA[228] !== 1'bz) && CH0_TXDATA_delay[228]; // rv 0 + assign CH0_TXDATA_in[229] = (CH0_TXDATA[229] !== 1'bz) && CH0_TXDATA_delay[229]; // rv 0 + assign CH0_TXDATA_in[22] = (CH0_TXDATA[22] !== 1'bz) && CH0_TXDATA_delay[22]; // rv 0 + assign CH0_TXDATA_in[230] = (CH0_TXDATA[230] !== 1'bz) && CH0_TXDATA_delay[230]; // rv 0 + assign CH0_TXDATA_in[231] = (CH0_TXDATA[231] !== 1'bz) && CH0_TXDATA_delay[231]; // rv 0 + assign CH0_TXDATA_in[232] = (CH0_TXDATA[232] !== 1'bz) && CH0_TXDATA_delay[232]; // rv 0 + assign CH0_TXDATA_in[233] = (CH0_TXDATA[233] !== 1'bz) && CH0_TXDATA_delay[233]; // rv 0 + assign CH0_TXDATA_in[234] = (CH0_TXDATA[234] !== 1'bz) && CH0_TXDATA_delay[234]; // rv 0 + assign CH0_TXDATA_in[235] = (CH0_TXDATA[235] !== 1'bz) && CH0_TXDATA_delay[235]; // rv 0 + assign CH0_TXDATA_in[236] = (CH0_TXDATA[236] !== 1'bz) && CH0_TXDATA_delay[236]; // rv 0 + assign CH0_TXDATA_in[237] = (CH0_TXDATA[237] !== 1'bz) && CH0_TXDATA_delay[237]; // rv 0 + assign CH0_TXDATA_in[238] = (CH0_TXDATA[238] !== 1'bz) && CH0_TXDATA_delay[238]; // rv 0 + assign CH0_TXDATA_in[239] = (CH0_TXDATA[239] !== 1'bz) && CH0_TXDATA_delay[239]; // rv 0 + assign CH0_TXDATA_in[23] = (CH0_TXDATA[23] !== 1'bz) && CH0_TXDATA_delay[23]; // rv 0 + assign CH0_TXDATA_in[240] = (CH0_TXDATA[240] !== 1'bz) && CH0_TXDATA_delay[240]; // rv 0 + assign CH0_TXDATA_in[241] = (CH0_TXDATA[241] !== 1'bz) && CH0_TXDATA_delay[241]; // rv 0 + assign CH0_TXDATA_in[242] = (CH0_TXDATA[242] !== 1'bz) && CH0_TXDATA_delay[242]; // rv 0 + assign CH0_TXDATA_in[243] = (CH0_TXDATA[243] !== 1'bz) && CH0_TXDATA_delay[243]; // rv 0 + assign CH0_TXDATA_in[244] = (CH0_TXDATA[244] !== 1'bz) && CH0_TXDATA_delay[244]; // rv 0 + assign CH0_TXDATA_in[245] = (CH0_TXDATA[245] !== 1'bz) && CH0_TXDATA_delay[245]; // rv 0 + assign CH0_TXDATA_in[246] = (CH0_TXDATA[246] !== 1'bz) && CH0_TXDATA_delay[246]; // rv 0 + assign CH0_TXDATA_in[247] = (CH0_TXDATA[247] !== 1'bz) && CH0_TXDATA_delay[247]; // rv 0 + assign CH0_TXDATA_in[248] = (CH0_TXDATA[248] !== 1'bz) && CH0_TXDATA_delay[248]; // rv 0 + assign CH0_TXDATA_in[249] = (CH0_TXDATA[249] !== 1'bz) && CH0_TXDATA_delay[249]; // rv 0 + assign CH0_TXDATA_in[24] = (CH0_TXDATA[24] !== 1'bz) && CH0_TXDATA_delay[24]; // rv 0 + assign CH0_TXDATA_in[250] = (CH0_TXDATA[250] !== 1'bz) && CH0_TXDATA_delay[250]; // rv 0 + assign CH0_TXDATA_in[251] = (CH0_TXDATA[251] !== 1'bz) && CH0_TXDATA_delay[251]; // rv 0 + assign CH0_TXDATA_in[252] = (CH0_TXDATA[252] !== 1'bz) && CH0_TXDATA_delay[252]; // rv 0 + assign CH0_TXDATA_in[253] = (CH0_TXDATA[253] !== 1'bz) && CH0_TXDATA_delay[253]; // rv 0 + assign CH0_TXDATA_in[254] = (CH0_TXDATA[254] !== 1'bz) && CH0_TXDATA_delay[254]; // rv 0 + assign CH0_TXDATA_in[255] = (CH0_TXDATA[255] !== 1'bz) && CH0_TXDATA_delay[255]; // rv 0 + assign CH0_TXDATA_in[25] = (CH0_TXDATA[25] !== 1'bz) && CH0_TXDATA_delay[25]; // rv 0 + assign CH0_TXDATA_in[26] = (CH0_TXDATA[26] !== 1'bz) && CH0_TXDATA_delay[26]; // rv 0 + assign CH0_TXDATA_in[27] = (CH0_TXDATA[27] !== 1'bz) && CH0_TXDATA_delay[27]; // rv 0 + assign CH0_TXDATA_in[28] = (CH0_TXDATA[28] !== 1'bz) && CH0_TXDATA_delay[28]; // rv 0 + assign CH0_TXDATA_in[29] = (CH0_TXDATA[29] !== 1'bz) && CH0_TXDATA_delay[29]; // rv 0 + assign CH0_TXDATA_in[2] = (CH0_TXDATA[2] !== 1'bz) && CH0_TXDATA_delay[2]; // rv 0 + assign CH0_TXDATA_in[30] = (CH0_TXDATA[30] !== 1'bz) && CH0_TXDATA_delay[30]; // rv 0 + assign CH0_TXDATA_in[31] = (CH0_TXDATA[31] !== 1'bz) && CH0_TXDATA_delay[31]; // rv 0 + assign CH0_TXDATA_in[32] = (CH0_TXDATA[32] !== 1'bz) && CH0_TXDATA_delay[32]; // rv 0 + assign CH0_TXDATA_in[33] = (CH0_TXDATA[33] !== 1'bz) && CH0_TXDATA_delay[33]; // rv 0 + assign CH0_TXDATA_in[34] = (CH0_TXDATA[34] !== 1'bz) && CH0_TXDATA_delay[34]; // rv 0 + assign CH0_TXDATA_in[35] = (CH0_TXDATA[35] !== 1'bz) && CH0_TXDATA_delay[35]; // rv 0 + assign CH0_TXDATA_in[36] = (CH0_TXDATA[36] !== 1'bz) && CH0_TXDATA_delay[36]; // rv 0 + assign CH0_TXDATA_in[37] = (CH0_TXDATA[37] !== 1'bz) && CH0_TXDATA_delay[37]; // rv 0 + assign CH0_TXDATA_in[38] = (CH0_TXDATA[38] !== 1'bz) && CH0_TXDATA_delay[38]; // rv 0 + assign CH0_TXDATA_in[39] = (CH0_TXDATA[39] !== 1'bz) && CH0_TXDATA_delay[39]; // rv 0 + assign CH0_TXDATA_in[3] = (CH0_TXDATA[3] !== 1'bz) && CH0_TXDATA_delay[3]; // rv 0 + assign CH0_TXDATA_in[40] = (CH0_TXDATA[40] !== 1'bz) && CH0_TXDATA_delay[40]; // rv 0 + assign CH0_TXDATA_in[41] = (CH0_TXDATA[41] !== 1'bz) && CH0_TXDATA_delay[41]; // rv 0 + assign CH0_TXDATA_in[42] = (CH0_TXDATA[42] !== 1'bz) && CH0_TXDATA_delay[42]; // rv 0 + assign CH0_TXDATA_in[43] = (CH0_TXDATA[43] !== 1'bz) && CH0_TXDATA_delay[43]; // rv 0 + assign CH0_TXDATA_in[44] = (CH0_TXDATA[44] !== 1'bz) && CH0_TXDATA_delay[44]; // rv 0 + assign CH0_TXDATA_in[45] = (CH0_TXDATA[45] !== 1'bz) && CH0_TXDATA_delay[45]; // rv 0 + assign CH0_TXDATA_in[46] = (CH0_TXDATA[46] !== 1'bz) && CH0_TXDATA_delay[46]; // rv 0 + assign CH0_TXDATA_in[47] = (CH0_TXDATA[47] !== 1'bz) && CH0_TXDATA_delay[47]; // rv 0 + assign CH0_TXDATA_in[48] = (CH0_TXDATA[48] !== 1'bz) && CH0_TXDATA_delay[48]; // rv 0 + assign CH0_TXDATA_in[49] = (CH0_TXDATA[49] !== 1'bz) && CH0_TXDATA_delay[49]; // rv 0 + assign CH0_TXDATA_in[4] = (CH0_TXDATA[4] !== 1'bz) && CH0_TXDATA_delay[4]; // rv 0 + assign CH0_TXDATA_in[50] = (CH0_TXDATA[50] !== 1'bz) && CH0_TXDATA_delay[50]; // rv 0 + assign CH0_TXDATA_in[51] = (CH0_TXDATA[51] !== 1'bz) && CH0_TXDATA_delay[51]; // rv 0 + assign CH0_TXDATA_in[52] = (CH0_TXDATA[52] !== 1'bz) && CH0_TXDATA_delay[52]; // rv 0 + assign CH0_TXDATA_in[53] = (CH0_TXDATA[53] !== 1'bz) && CH0_TXDATA_delay[53]; // rv 0 + assign CH0_TXDATA_in[54] = (CH0_TXDATA[54] !== 1'bz) && CH0_TXDATA_delay[54]; // rv 0 + assign CH0_TXDATA_in[55] = (CH0_TXDATA[55] !== 1'bz) && CH0_TXDATA_delay[55]; // rv 0 + assign CH0_TXDATA_in[56] = (CH0_TXDATA[56] !== 1'bz) && CH0_TXDATA_delay[56]; // rv 0 + assign CH0_TXDATA_in[57] = (CH0_TXDATA[57] !== 1'bz) && CH0_TXDATA_delay[57]; // rv 0 + assign CH0_TXDATA_in[58] = (CH0_TXDATA[58] !== 1'bz) && CH0_TXDATA_delay[58]; // rv 0 + assign CH0_TXDATA_in[59] = (CH0_TXDATA[59] !== 1'bz) && CH0_TXDATA_delay[59]; // rv 0 + assign CH0_TXDATA_in[5] = (CH0_TXDATA[5] !== 1'bz) && CH0_TXDATA_delay[5]; // rv 0 + assign CH0_TXDATA_in[60] = (CH0_TXDATA[60] !== 1'bz) && CH0_TXDATA_delay[60]; // rv 0 + assign CH0_TXDATA_in[61] = (CH0_TXDATA[61] !== 1'bz) && CH0_TXDATA_delay[61]; // rv 0 + assign CH0_TXDATA_in[62] = (CH0_TXDATA[62] !== 1'bz) && CH0_TXDATA_delay[62]; // rv 0 + assign CH0_TXDATA_in[63] = (CH0_TXDATA[63] !== 1'bz) && CH0_TXDATA_delay[63]; // rv 0 + assign CH0_TXDATA_in[64] = (CH0_TXDATA[64] !== 1'bz) && CH0_TXDATA_delay[64]; // rv 0 + assign CH0_TXDATA_in[65] = (CH0_TXDATA[65] !== 1'bz) && CH0_TXDATA_delay[65]; // rv 0 + assign CH0_TXDATA_in[66] = (CH0_TXDATA[66] !== 1'bz) && CH0_TXDATA_delay[66]; // rv 0 + assign CH0_TXDATA_in[67] = (CH0_TXDATA[67] !== 1'bz) && CH0_TXDATA_delay[67]; // rv 0 + assign CH0_TXDATA_in[68] = (CH0_TXDATA[68] !== 1'bz) && CH0_TXDATA_delay[68]; // rv 0 + assign CH0_TXDATA_in[69] = (CH0_TXDATA[69] !== 1'bz) && CH0_TXDATA_delay[69]; // rv 0 + assign CH0_TXDATA_in[6] = (CH0_TXDATA[6] !== 1'bz) && CH0_TXDATA_delay[6]; // rv 0 + assign CH0_TXDATA_in[70] = (CH0_TXDATA[70] !== 1'bz) && CH0_TXDATA_delay[70]; // rv 0 + assign CH0_TXDATA_in[71] = (CH0_TXDATA[71] !== 1'bz) && CH0_TXDATA_delay[71]; // rv 0 + assign CH0_TXDATA_in[72] = (CH0_TXDATA[72] !== 1'bz) && CH0_TXDATA_delay[72]; // rv 0 + assign CH0_TXDATA_in[73] = (CH0_TXDATA[73] !== 1'bz) && CH0_TXDATA_delay[73]; // rv 0 + assign CH0_TXDATA_in[74] = (CH0_TXDATA[74] !== 1'bz) && CH0_TXDATA_delay[74]; // rv 0 + assign CH0_TXDATA_in[75] = (CH0_TXDATA[75] !== 1'bz) && CH0_TXDATA_delay[75]; // rv 0 + assign CH0_TXDATA_in[76] = (CH0_TXDATA[76] !== 1'bz) && CH0_TXDATA_delay[76]; // rv 0 + assign CH0_TXDATA_in[77] = (CH0_TXDATA[77] !== 1'bz) && CH0_TXDATA_delay[77]; // rv 0 + assign CH0_TXDATA_in[78] = (CH0_TXDATA[78] !== 1'bz) && CH0_TXDATA_delay[78]; // rv 0 + assign CH0_TXDATA_in[79] = (CH0_TXDATA[79] !== 1'bz) && CH0_TXDATA_delay[79]; // rv 0 + assign CH0_TXDATA_in[7] = (CH0_TXDATA[7] !== 1'bz) && CH0_TXDATA_delay[7]; // rv 0 + assign CH0_TXDATA_in[80] = (CH0_TXDATA[80] !== 1'bz) && CH0_TXDATA_delay[80]; // rv 0 + assign CH0_TXDATA_in[81] = (CH0_TXDATA[81] !== 1'bz) && CH0_TXDATA_delay[81]; // rv 0 + assign CH0_TXDATA_in[82] = (CH0_TXDATA[82] !== 1'bz) && CH0_TXDATA_delay[82]; // rv 0 + assign CH0_TXDATA_in[83] = (CH0_TXDATA[83] !== 1'bz) && CH0_TXDATA_delay[83]; // rv 0 + assign CH0_TXDATA_in[84] = (CH0_TXDATA[84] !== 1'bz) && CH0_TXDATA_delay[84]; // rv 0 + assign CH0_TXDATA_in[85] = (CH0_TXDATA[85] !== 1'bz) && CH0_TXDATA_delay[85]; // rv 0 + assign CH0_TXDATA_in[86] = (CH0_TXDATA[86] !== 1'bz) && CH0_TXDATA_delay[86]; // rv 0 + assign CH0_TXDATA_in[87] = (CH0_TXDATA[87] !== 1'bz) && CH0_TXDATA_delay[87]; // rv 0 + assign CH0_TXDATA_in[88] = (CH0_TXDATA[88] !== 1'bz) && CH0_TXDATA_delay[88]; // rv 0 + assign CH0_TXDATA_in[89] = (CH0_TXDATA[89] !== 1'bz) && CH0_TXDATA_delay[89]; // rv 0 + assign CH0_TXDATA_in[8] = (CH0_TXDATA[8] !== 1'bz) && CH0_TXDATA_delay[8]; // rv 0 + assign CH0_TXDATA_in[90] = (CH0_TXDATA[90] !== 1'bz) && CH0_TXDATA_delay[90]; // rv 0 + assign CH0_TXDATA_in[91] = (CH0_TXDATA[91] !== 1'bz) && CH0_TXDATA_delay[91]; // rv 0 + assign CH0_TXDATA_in[92] = (CH0_TXDATA[92] !== 1'bz) && CH0_TXDATA_delay[92]; // rv 0 + assign CH0_TXDATA_in[93] = (CH0_TXDATA[93] !== 1'bz) && CH0_TXDATA_delay[93]; // rv 0 + assign CH0_TXDATA_in[94] = (CH0_TXDATA[94] !== 1'bz) && CH0_TXDATA_delay[94]; // rv 0 + assign CH0_TXDATA_in[95] = (CH0_TXDATA[95] !== 1'bz) && CH0_TXDATA_delay[95]; // rv 0 + assign CH0_TXDATA_in[96] = (CH0_TXDATA[96] !== 1'bz) && CH0_TXDATA_delay[96]; // rv 0 + assign CH0_TXDATA_in[97] = (CH0_TXDATA[97] !== 1'bz) && CH0_TXDATA_delay[97]; // rv 0 + assign CH0_TXDATA_in[98] = (CH0_TXDATA[98] !== 1'bz) && CH0_TXDATA_delay[98]; // rv 0 + assign CH0_TXDATA_in[99] = (CH0_TXDATA[99] !== 1'bz) && CH0_TXDATA_delay[99]; // rv 0 + assign CH0_TXDATA_in[9] = (CH0_TXDATA[9] !== 1'bz) && CH0_TXDATA_delay[9]; // rv 0 + assign CH0_TXINHIBIT_in = (CH0_TXINHIBIT !== 1'bz) && CH0_TXINHIBIT_delay; // rv 0 + assign CH0_TXPOLARITY_in = (CH0_TXPOLARITY !== 1'bz) && CH0_TXPOLARITY_delay; // rv 0 + assign CH0_TXPRBSINERR_in = (CH0_TXPRBSINERR !== 1'bz) && CH0_TXPRBSINERR_delay; // rv 0 + assign CH0_TXPRBSPTN_in[0] = (CH0_TXPRBSPTN[0] !== 1'bz) && CH0_TXPRBSPTN_delay[0]; // rv 0 + assign CH0_TXPRBSPTN_in[1] = (CH0_TXPRBSPTN[1] !== 1'bz) && CH0_TXPRBSPTN_delay[1]; // rv 0 + assign CH0_TXPRBSPTN_in[2] = (CH0_TXPRBSPTN[2] !== 1'bz) && CH0_TXPRBSPTN_delay[2]; // rv 0 + assign CH0_TXPRBSPTN_in[3] = (CH0_TXPRBSPTN[3] !== 1'bz) && CH0_TXPRBSPTN_delay[3]; // rv 0 + assign CH0_TXQPRBSEN_in = (CH0_TXQPRBSEN !== 1'bz) && CH0_TXQPRBSEN_delay; // rv 0 + assign CH0_TXUSRCLK2_in = (CH0_TXUSRCLK2 !== 1'bz) && CH0_TXUSRCLK2_delay; // rv 0 + assign CH0_TXUSRCLK_in = (CH0_TXUSRCLK !== 1'bz) && CH0_TXUSRCLK_delay; // rv 0 + assign CH1_AXISEN_in = (CH1_AXISEN !== 1'bz) && CH1_AXISEN_delay; // rv 0 + assign CH1_AXISTRDY_in = (CH1_AXISTRDY !== 1'bz) && CH1_AXISTRDY_delay; // rv 0 + assign CH1_RXEQTRAINING_in = (CH1_RXEQTRAINING !== 1'bz) && CH1_RXEQTRAINING_delay; // rv 0 + assign CH1_RXPOLARITY_in = (CH1_RXPOLARITY !== 1'bz) && CH1_RXPOLARITY_delay; // rv 0 + assign CH1_RXPRBSCNTSTOP_in = (CH1_RXPRBSCNTSTOP !== 1'bz) && CH1_RXPRBSCNTSTOP_delay; // rv 0 + assign CH1_RXPRBSPTN_in[0] = (CH1_RXPRBSPTN[0] !== 1'bz) && CH1_RXPRBSPTN_delay[0]; // rv 0 + assign CH1_RXPRBSPTN_in[1] = (CH1_RXPRBSPTN[1] !== 1'bz) && CH1_RXPRBSPTN_delay[1]; // rv 0 + assign CH1_RXPRBSPTN_in[2] = (CH1_RXPRBSPTN[2] !== 1'bz) && CH1_RXPRBSPTN_delay[2]; // rv 0 + assign CH1_RXPRBSPTN_in[3] = (CH1_RXPRBSPTN[3] !== 1'bz) && CH1_RXPRBSPTN_delay[3]; // rv 0 + assign CH1_RXQPRBSEN_in = (CH1_RXQPRBSEN !== 1'bz) && CH1_RXQPRBSEN_delay; // rv 0 + assign CH1_RXUSRCLK2_in = (CH1_RXUSRCLK2 !== 1'bz) && CH1_RXUSRCLK2_delay; // rv 0 + assign CH1_RXUSRCLK_in = (CH1_RXUSRCLK !== 1'bz) && CH1_RXUSRCLK_delay; // rv 0 + assign CH1_TXDATASTART_in = (CH1_TXDATASTART !== 1'bz) && CH1_TXDATASTART_delay; // rv 0 + assign CH1_TXDATA_in[0] = (CH1_TXDATA[0] !== 1'bz) && CH1_TXDATA_delay[0]; // rv 0 + assign CH1_TXDATA_in[100] = (CH1_TXDATA[100] !== 1'bz) && CH1_TXDATA_delay[100]; // rv 0 + assign CH1_TXDATA_in[101] = (CH1_TXDATA[101] !== 1'bz) && CH1_TXDATA_delay[101]; // rv 0 + assign CH1_TXDATA_in[102] = (CH1_TXDATA[102] !== 1'bz) && CH1_TXDATA_delay[102]; // rv 0 + assign CH1_TXDATA_in[103] = (CH1_TXDATA[103] !== 1'bz) && CH1_TXDATA_delay[103]; // rv 0 + assign CH1_TXDATA_in[104] = (CH1_TXDATA[104] !== 1'bz) && CH1_TXDATA_delay[104]; // rv 0 + assign CH1_TXDATA_in[105] = (CH1_TXDATA[105] !== 1'bz) && CH1_TXDATA_delay[105]; // rv 0 + assign CH1_TXDATA_in[106] = (CH1_TXDATA[106] !== 1'bz) && CH1_TXDATA_delay[106]; // rv 0 + assign CH1_TXDATA_in[107] = (CH1_TXDATA[107] !== 1'bz) && CH1_TXDATA_delay[107]; // rv 0 + assign CH1_TXDATA_in[108] = (CH1_TXDATA[108] !== 1'bz) && CH1_TXDATA_delay[108]; // rv 0 + assign CH1_TXDATA_in[109] = (CH1_TXDATA[109] !== 1'bz) && CH1_TXDATA_delay[109]; // rv 0 + assign CH1_TXDATA_in[10] = (CH1_TXDATA[10] !== 1'bz) && CH1_TXDATA_delay[10]; // rv 0 + assign CH1_TXDATA_in[110] = (CH1_TXDATA[110] !== 1'bz) && CH1_TXDATA_delay[110]; // rv 0 + assign CH1_TXDATA_in[111] = (CH1_TXDATA[111] !== 1'bz) && CH1_TXDATA_delay[111]; // rv 0 + assign CH1_TXDATA_in[112] = (CH1_TXDATA[112] !== 1'bz) && CH1_TXDATA_delay[112]; // rv 0 + assign CH1_TXDATA_in[113] = (CH1_TXDATA[113] !== 1'bz) && CH1_TXDATA_delay[113]; // rv 0 + assign CH1_TXDATA_in[114] = (CH1_TXDATA[114] !== 1'bz) && CH1_TXDATA_delay[114]; // rv 0 + assign CH1_TXDATA_in[115] = (CH1_TXDATA[115] !== 1'bz) && CH1_TXDATA_delay[115]; // rv 0 + assign CH1_TXDATA_in[116] = (CH1_TXDATA[116] !== 1'bz) && CH1_TXDATA_delay[116]; // rv 0 + assign CH1_TXDATA_in[117] = (CH1_TXDATA[117] !== 1'bz) && CH1_TXDATA_delay[117]; // rv 0 + assign CH1_TXDATA_in[118] = (CH1_TXDATA[118] !== 1'bz) && CH1_TXDATA_delay[118]; // rv 0 + assign CH1_TXDATA_in[119] = (CH1_TXDATA[119] !== 1'bz) && CH1_TXDATA_delay[119]; // rv 0 + assign CH1_TXDATA_in[11] = (CH1_TXDATA[11] !== 1'bz) && CH1_TXDATA_delay[11]; // rv 0 + assign CH1_TXDATA_in[120] = (CH1_TXDATA[120] !== 1'bz) && CH1_TXDATA_delay[120]; // rv 0 + assign CH1_TXDATA_in[121] = (CH1_TXDATA[121] !== 1'bz) && CH1_TXDATA_delay[121]; // rv 0 + assign CH1_TXDATA_in[122] = (CH1_TXDATA[122] !== 1'bz) && CH1_TXDATA_delay[122]; // rv 0 + assign CH1_TXDATA_in[123] = (CH1_TXDATA[123] !== 1'bz) && CH1_TXDATA_delay[123]; // rv 0 + assign CH1_TXDATA_in[124] = (CH1_TXDATA[124] !== 1'bz) && CH1_TXDATA_delay[124]; // rv 0 + assign CH1_TXDATA_in[125] = (CH1_TXDATA[125] !== 1'bz) && CH1_TXDATA_delay[125]; // rv 0 + assign CH1_TXDATA_in[126] = (CH1_TXDATA[126] !== 1'bz) && CH1_TXDATA_delay[126]; // rv 0 + assign CH1_TXDATA_in[127] = (CH1_TXDATA[127] !== 1'bz) && CH1_TXDATA_delay[127]; // rv 0 + assign CH1_TXDATA_in[128] = (CH1_TXDATA[128] !== 1'bz) && CH1_TXDATA_delay[128]; // rv 0 + assign CH1_TXDATA_in[129] = (CH1_TXDATA[129] !== 1'bz) && CH1_TXDATA_delay[129]; // rv 0 + assign CH1_TXDATA_in[12] = (CH1_TXDATA[12] !== 1'bz) && CH1_TXDATA_delay[12]; // rv 0 + assign CH1_TXDATA_in[130] = (CH1_TXDATA[130] !== 1'bz) && CH1_TXDATA_delay[130]; // rv 0 + assign CH1_TXDATA_in[131] = (CH1_TXDATA[131] !== 1'bz) && CH1_TXDATA_delay[131]; // rv 0 + assign CH1_TXDATA_in[132] = (CH1_TXDATA[132] !== 1'bz) && CH1_TXDATA_delay[132]; // rv 0 + assign CH1_TXDATA_in[133] = (CH1_TXDATA[133] !== 1'bz) && CH1_TXDATA_delay[133]; // rv 0 + assign CH1_TXDATA_in[134] = (CH1_TXDATA[134] !== 1'bz) && CH1_TXDATA_delay[134]; // rv 0 + assign CH1_TXDATA_in[135] = (CH1_TXDATA[135] !== 1'bz) && CH1_TXDATA_delay[135]; // rv 0 + assign CH1_TXDATA_in[136] = (CH1_TXDATA[136] !== 1'bz) && CH1_TXDATA_delay[136]; // rv 0 + assign CH1_TXDATA_in[137] = (CH1_TXDATA[137] !== 1'bz) && CH1_TXDATA_delay[137]; // rv 0 + assign CH1_TXDATA_in[138] = (CH1_TXDATA[138] !== 1'bz) && CH1_TXDATA_delay[138]; // rv 0 + assign CH1_TXDATA_in[139] = (CH1_TXDATA[139] !== 1'bz) && CH1_TXDATA_delay[139]; // rv 0 + assign CH1_TXDATA_in[13] = (CH1_TXDATA[13] !== 1'bz) && CH1_TXDATA_delay[13]; // rv 0 + assign CH1_TXDATA_in[140] = (CH1_TXDATA[140] !== 1'bz) && CH1_TXDATA_delay[140]; // rv 0 + assign CH1_TXDATA_in[141] = (CH1_TXDATA[141] !== 1'bz) && CH1_TXDATA_delay[141]; // rv 0 + assign CH1_TXDATA_in[142] = (CH1_TXDATA[142] !== 1'bz) && CH1_TXDATA_delay[142]; // rv 0 + assign CH1_TXDATA_in[143] = (CH1_TXDATA[143] !== 1'bz) && CH1_TXDATA_delay[143]; // rv 0 + assign CH1_TXDATA_in[144] = (CH1_TXDATA[144] !== 1'bz) && CH1_TXDATA_delay[144]; // rv 0 + assign CH1_TXDATA_in[145] = (CH1_TXDATA[145] !== 1'bz) && CH1_TXDATA_delay[145]; // rv 0 + assign CH1_TXDATA_in[146] = (CH1_TXDATA[146] !== 1'bz) && CH1_TXDATA_delay[146]; // rv 0 + assign CH1_TXDATA_in[147] = (CH1_TXDATA[147] !== 1'bz) && CH1_TXDATA_delay[147]; // rv 0 + assign CH1_TXDATA_in[148] = (CH1_TXDATA[148] !== 1'bz) && CH1_TXDATA_delay[148]; // rv 0 + assign CH1_TXDATA_in[149] = (CH1_TXDATA[149] !== 1'bz) && CH1_TXDATA_delay[149]; // rv 0 + assign CH1_TXDATA_in[14] = (CH1_TXDATA[14] !== 1'bz) && CH1_TXDATA_delay[14]; // rv 0 + assign CH1_TXDATA_in[150] = (CH1_TXDATA[150] !== 1'bz) && CH1_TXDATA_delay[150]; // rv 0 + assign CH1_TXDATA_in[151] = (CH1_TXDATA[151] !== 1'bz) && CH1_TXDATA_delay[151]; // rv 0 + assign CH1_TXDATA_in[152] = (CH1_TXDATA[152] !== 1'bz) && CH1_TXDATA_delay[152]; // rv 0 + assign CH1_TXDATA_in[153] = (CH1_TXDATA[153] !== 1'bz) && CH1_TXDATA_delay[153]; // rv 0 + assign CH1_TXDATA_in[154] = (CH1_TXDATA[154] !== 1'bz) && CH1_TXDATA_delay[154]; // rv 0 + assign CH1_TXDATA_in[155] = (CH1_TXDATA[155] !== 1'bz) && CH1_TXDATA_delay[155]; // rv 0 + assign CH1_TXDATA_in[156] = (CH1_TXDATA[156] !== 1'bz) && CH1_TXDATA_delay[156]; // rv 0 + assign CH1_TXDATA_in[157] = (CH1_TXDATA[157] !== 1'bz) && CH1_TXDATA_delay[157]; // rv 0 + assign CH1_TXDATA_in[158] = (CH1_TXDATA[158] !== 1'bz) && CH1_TXDATA_delay[158]; // rv 0 + assign CH1_TXDATA_in[159] = (CH1_TXDATA[159] !== 1'bz) && CH1_TXDATA_delay[159]; // rv 0 + assign CH1_TXDATA_in[15] = (CH1_TXDATA[15] !== 1'bz) && CH1_TXDATA_delay[15]; // rv 0 + assign CH1_TXDATA_in[160] = (CH1_TXDATA[160] !== 1'bz) && CH1_TXDATA_delay[160]; // rv 0 + assign CH1_TXDATA_in[161] = (CH1_TXDATA[161] !== 1'bz) && CH1_TXDATA_delay[161]; // rv 0 + assign CH1_TXDATA_in[162] = (CH1_TXDATA[162] !== 1'bz) && CH1_TXDATA_delay[162]; // rv 0 + assign CH1_TXDATA_in[163] = (CH1_TXDATA[163] !== 1'bz) && CH1_TXDATA_delay[163]; // rv 0 + assign CH1_TXDATA_in[164] = (CH1_TXDATA[164] !== 1'bz) && CH1_TXDATA_delay[164]; // rv 0 + assign CH1_TXDATA_in[165] = (CH1_TXDATA[165] !== 1'bz) && CH1_TXDATA_delay[165]; // rv 0 + assign CH1_TXDATA_in[166] = (CH1_TXDATA[166] !== 1'bz) && CH1_TXDATA_delay[166]; // rv 0 + assign CH1_TXDATA_in[167] = (CH1_TXDATA[167] !== 1'bz) && CH1_TXDATA_delay[167]; // rv 0 + assign CH1_TXDATA_in[168] = (CH1_TXDATA[168] !== 1'bz) && CH1_TXDATA_delay[168]; // rv 0 + assign CH1_TXDATA_in[169] = (CH1_TXDATA[169] !== 1'bz) && CH1_TXDATA_delay[169]; // rv 0 + assign CH1_TXDATA_in[16] = (CH1_TXDATA[16] !== 1'bz) && CH1_TXDATA_delay[16]; // rv 0 + assign CH1_TXDATA_in[170] = (CH1_TXDATA[170] !== 1'bz) && CH1_TXDATA_delay[170]; // rv 0 + assign CH1_TXDATA_in[171] = (CH1_TXDATA[171] !== 1'bz) && CH1_TXDATA_delay[171]; // rv 0 + assign CH1_TXDATA_in[172] = (CH1_TXDATA[172] !== 1'bz) && CH1_TXDATA_delay[172]; // rv 0 + assign CH1_TXDATA_in[173] = (CH1_TXDATA[173] !== 1'bz) && CH1_TXDATA_delay[173]; // rv 0 + assign CH1_TXDATA_in[174] = (CH1_TXDATA[174] !== 1'bz) && CH1_TXDATA_delay[174]; // rv 0 + assign CH1_TXDATA_in[175] = (CH1_TXDATA[175] !== 1'bz) && CH1_TXDATA_delay[175]; // rv 0 + assign CH1_TXDATA_in[176] = (CH1_TXDATA[176] !== 1'bz) && CH1_TXDATA_delay[176]; // rv 0 + assign CH1_TXDATA_in[177] = (CH1_TXDATA[177] !== 1'bz) && CH1_TXDATA_delay[177]; // rv 0 + assign CH1_TXDATA_in[178] = (CH1_TXDATA[178] !== 1'bz) && CH1_TXDATA_delay[178]; // rv 0 + assign CH1_TXDATA_in[179] = (CH1_TXDATA[179] !== 1'bz) && CH1_TXDATA_delay[179]; // rv 0 + assign CH1_TXDATA_in[17] = (CH1_TXDATA[17] !== 1'bz) && CH1_TXDATA_delay[17]; // rv 0 + assign CH1_TXDATA_in[180] = (CH1_TXDATA[180] !== 1'bz) && CH1_TXDATA_delay[180]; // rv 0 + assign CH1_TXDATA_in[181] = (CH1_TXDATA[181] !== 1'bz) && CH1_TXDATA_delay[181]; // rv 0 + assign CH1_TXDATA_in[182] = (CH1_TXDATA[182] !== 1'bz) && CH1_TXDATA_delay[182]; // rv 0 + assign CH1_TXDATA_in[183] = (CH1_TXDATA[183] !== 1'bz) && CH1_TXDATA_delay[183]; // rv 0 + assign CH1_TXDATA_in[184] = (CH1_TXDATA[184] !== 1'bz) && CH1_TXDATA_delay[184]; // rv 0 + assign CH1_TXDATA_in[185] = (CH1_TXDATA[185] !== 1'bz) && CH1_TXDATA_delay[185]; // rv 0 + assign CH1_TXDATA_in[186] = (CH1_TXDATA[186] !== 1'bz) && CH1_TXDATA_delay[186]; // rv 0 + assign CH1_TXDATA_in[187] = (CH1_TXDATA[187] !== 1'bz) && CH1_TXDATA_delay[187]; // rv 0 + assign CH1_TXDATA_in[188] = (CH1_TXDATA[188] !== 1'bz) && CH1_TXDATA_delay[188]; // rv 0 + assign CH1_TXDATA_in[189] = (CH1_TXDATA[189] !== 1'bz) && CH1_TXDATA_delay[189]; // rv 0 + assign CH1_TXDATA_in[18] = (CH1_TXDATA[18] !== 1'bz) && CH1_TXDATA_delay[18]; // rv 0 + assign CH1_TXDATA_in[190] = (CH1_TXDATA[190] !== 1'bz) && CH1_TXDATA_delay[190]; // rv 0 + assign CH1_TXDATA_in[191] = (CH1_TXDATA[191] !== 1'bz) && CH1_TXDATA_delay[191]; // rv 0 + assign CH1_TXDATA_in[192] = (CH1_TXDATA[192] !== 1'bz) && CH1_TXDATA_delay[192]; // rv 0 + assign CH1_TXDATA_in[193] = (CH1_TXDATA[193] !== 1'bz) && CH1_TXDATA_delay[193]; // rv 0 + assign CH1_TXDATA_in[194] = (CH1_TXDATA[194] !== 1'bz) && CH1_TXDATA_delay[194]; // rv 0 + assign CH1_TXDATA_in[195] = (CH1_TXDATA[195] !== 1'bz) && CH1_TXDATA_delay[195]; // rv 0 + assign CH1_TXDATA_in[196] = (CH1_TXDATA[196] !== 1'bz) && CH1_TXDATA_delay[196]; // rv 0 + assign CH1_TXDATA_in[197] = (CH1_TXDATA[197] !== 1'bz) && CH1_TXDATA_delay[197]; // rv 0 + assign CH1_TXDATA_in[198] = (CH1_TXDATA[198] !== 1'bz) && CH1_TXDATA_delay[198]; // rv 0 + assign CH1_TXDATA_in[199] = (CH1_TXDATA[199] !== 1'bz) && CH1_TXDATA_delay[199]; // rv 0 + assign CH1_TXDATA_in[19] = (CH1_TXDATA[19] !== 1'bz) && CH1_TXDATA_delay[19]; // rv 0 + assign CH1_TXDATA_in[1] = (CH1_TXDATA[1] !== 1'bz) && CH1_TXDATA_delay[1]; // rv 0 + assign CH1_TXDATA_in[200] = (CH1_TXDATA[200] !== 1'bz) && CH1_TXDATA_delay[200]; // rv 0 + assign CH1_TXDATA_in[201] = (CH1_TXDATA[201] !== 1'bz) && CH1_TXDATA_delay[201]; // rv 0 + assign CH1_TXDATA_in[202] = (CH1_TXDATA[202] !== 1'bz) && CH1_TXDATA_delay[202]; // rv 0 + assign CH1_TXDATA_in[203] = (CH1_TXDATA[203] !== 1'bz) && CH1_TXDATA_delay[203]; // rv 0 + assign CH1_TXDATA_in[204] = (CH1_TXDATA[204] !== 1'bz) && CH1_TXDATA_delay[204]; // rv 0 + assign CH1_TXDATA_in[205] = (CH1_TXDATA[205] !== 1'bz) && CH1_TXDATA_delay[205]; // rv 0 + assign CH1_TXDATA_in[206] = (CH1_TXDATA[206] !== 1'bz) && CH1_TXDATA_delay[206]; // rv 0 + assign CH1_TXDATA_in[207] = (CH1_TXDATA[207] !== 1'bz) && CH1_TXDATA_delay[207]; // rv 0 + assign CH1_TXDATA_in[208] = (CH1_TXDATA[208] !== 1'bz) && CH1_TXDATA_delay[208]; // rv 0 + assign CH1_TXDATA_in[209] = (CH1_TXDATA[209] !== 1'bz) && CH1_TXDATA_delay[209]; // rv 0 + assign CH1_TXDATA_in[20] = (CH1_TXDATA[20] !== 1'bz) && CH1_TXDATA_delay[20]; // rv 0 + assign CH1_TXDATA_in[210] = (CH1_TXDATA[210] !== 1'bz) && CH1_TXDATA_delay[210]; // rv 0 + assign CH1_TXDATA_in[211] = (CH1_TXDATA[211] !== 1'bz) && CH1_TXDATA_delay[211]; // rv 0 + assign CH1_TXDATA_in[212] = (CH1_TXDATA[212] !== 1'bz) && CH1_TXDATA_delay[212]; // rv 0 + assign CH1_TXDATA_in[213] = (CH1_TXDATA[213] !== 1'bz) && CH1_TXDATA_delay[213]; // rv 0 + assign CH1_TXDATA_in[214] = (CH1_TXDATA[214] !== 1'bz) && CH1_TXDATA_delay[214]; // rv 0 + assign CH1_TXDATA_in[215] = (CH1_TXDATA[215] !== 1'bz) && CH1_TXDATA_delay[215]; // rv 0 + assign CH1_TXDATA_in[216] = (CH1_TXDATA[216] !== 1'bz) && CH1_TXDATA_delay[216]; // rv 0 + assign CH1_TXDATA_in[217] = (CH1_TXDATA[217] !== 1'bz) && CH1_TXDATA_delay[217]; // rv 0 + assign CH1_TXDATA_in[218] = (CH1_TXDATA[218] !== 1'bz) && CH1_TXDATA_delay[218]; // rv 0 + assign CH1_TXDATA_in[219] = (CH1_TXDATA[219] !== 1'bz) && CH1_TXDATA_delay[219]; // rv 0 + assign CH1_TXDATA_in[21] = (CH1_TXDATA[21] !== 1'bz) && CH1_TXDATA_delay[21]; // rv 0 + assign CH1_TXDATA_in[220] = (CH1_TXDATA[220] !== 1'bz) && CH1_TXDATA_delay[220]; // rv 0 + assign CH1_TXDATA_in[221] = (CH1_TXDATA[221] !== 1'bz) && CH1_TXDATA_delay[221]; // rv 0 + assign CH1_TXDATA_in[222] = (CH1_TXDATA[222] !== 1'bz) && CH1_TXDATA_delay[222]; // rv 0 + assign CH1_TXDATA_in[223] = (CH1_TXDATA[223] !== 1'bz) && CH1_TXDATA_delay[223]; // rv 0 + assign CH1_TXDATA_in[224] = (CH1_TXDATA[224] !== 1'bz) && CH1_TXDATA_delay[224]; // rv 0 + assign CH1_TXDATA_in[225] = (CH1_TXDATA[225] !== 1'bz) && CH1_TXDATA_delay[225]; // rv 0 + assign CH1_TXDATA_in[226] = (CH1_TXDATA[226] !== 1'bz) && CH1_TXDATA_delay[226]; // rv 0 + assign CH1_TXDATA_in[227] = (CH1_TXDATA[227] !== 1'bz) && CH1_TXDATA_delay[227]; // rv 0 + assign CH1_TXDATA_in[228] = (CH1_TXDATA[228] !== 1'bz) && CH1_TXDATA_delay[228]; // rv 0 + assign CH1_TXDATA_in[229] = (CH1_TXDATA[229] !== 1'bz) && CH1_TXDATA_delay[229]; // rv 0 + assign CH1_TXDATA_in[22] = (CH1_TXDATA[22] !== 1'bz) && CH1_TXDATA_delay[22]; // rv 0 + assign CH1_TXDATA_in[230] = (CH1_TXDATA[230] !== 1'bz) && CH1_TXDATA_delay[230]; // rv 0 + assign CH1_TXDATA_in[231] = (CH1_TXDATA[231] !== 1'bz) && CH1_TXDATA_delay[231]; // rv 0 + assign CH1_TXDATA_in[232] = (CH1_TXDATA[232] !== 1'bz) && CH1_TXDATA_delay[232]; // rv 0 + assign CH1_TXDATA_in[233] = (CH1_TXDATA[233] !== 1'bz) && CH1_TXDATA_delay[233]; // rv 0 + assign CH1_TXDATA_in[234] = (CH1_TXDATA[234] !== 1'bz) && CH1_TXDATA_delay[234]; // rv 0 + assign CH1_TXDATA_in[235] = (CH1_TXDATA[235] !== 1'bz) && CH1_TXDATA_delay[235]; // rv 0 + assign CH1_TXDATA_in[236] = (CH1_TXDATA[236] !== 1'bz) && CH1_TXDATA_delay[236]; // rv 0 + assign CH1_TXDATA_in[237] = (CH1_TXDATA[237] !== 1'bz) && CH1_TXDATA_delay[237]; // rv 0 + assign CH1_TXDATA_in[238] = (CH1_TXDATA[238] !== 1'bz) && CH1_TXDATA_delay[238]; // rv 0 + assign CH1_TXDATA_in[239] = (CH1_TXDATA[239] !== 1'bz) && CH1_TXDATA_delay[239]; // rv 0 + assign CH1_TXDATA_in[23] = (CH1_TXDATA[23] !== 1'bz) && CH1_TXDATA_delay[23]; // rv 0 + assign CH1_TXDATA_in[240] = (CH1_TXDATA[240] !== 1'bz) && CH1_TXDATA_delay[240]; // rv 0 + assign CH1_TXDATA_in[241] = (CH1_TXDATA[241] !== 1'bz) && CH1_TXDATA_delay[241]; // rv 0 + assign CH1_TXDATA_in[242] = (CH1_TXDATA[242] !== 1'bz) && CH1_TXDATA_delay[242]; // rv 0 + assign CH1_TXDATA_in[243] = (CH1_TXDATA[243] !== 1'bz) && CH1_TXDATA_delay[243]; // rv 0 + assign CH1_TXDATA_in[244] = (CH1_TXDATA[244] !== 1'bz) && CH1_TXDATA_delay[244]; // rv 0 + assign CH1_TXDATA_in[245] = (CH1_TXDATA[245] !== 1'bz) && CH1_TXDATA_delay[245]; // rv 0 + assign CH1_TXDATA_in[246] = (CH1_TXDATA[246] !== 1'bz) && CH1_TXDATA_delay[246]; // rv 0 + assign CH1_TXDATA_in[247] = (CH1_TXDATA[247] !== 1'bz) && CH1_TXDATA_delay[247]; // rv 0 + assign CH1_TXDATA_in[248] = (CH1_TXDATA[248] !== 1'bz) && CH1_TXDATA_delay[248]; // rv 0 + assign CH1_TXDATA_in[249] = (CH1_TXDATA[249] !== 1'bz) && CH1_TXDATA_delay[249]; // rv 0 + assign CH1_TXDATA_in[24] = (CH1_TXDATA[24] !== 1'bz) && CH1_TXDATA_delay[24]; // rv 0 + assign CH1_TXDATA_in[250] = (CH1_TXDATA[250] !== 1'bz) && CH1_TXDATA_delay[250]; // rv 0 + assign CH1_TXDATA_in[251] = (CH1_TXDATA[251] !== 1'bz) && CH1_TXDATA_delay[251]; // rv 0 + assign CH1_TXDATA_in[252] = (CH1_TXDATA[252] !== 1'bz) && CH1_TXDATA_delay[252]; // rv 0 + assign CH1_TXDATA_in[253] = (CH1_TXDATA[253] !== 1'bz) && CH1_TXDATA_delay[253]; // rv 0 + assign CH1_TXDATA_in[254] = (CH1_TXDATA[254] !== 1'bz) && CH1_TXDATA_delay[254]; // rv 0 + assign CH1_TXDATA_in[255] = (CH1_TXDATA[255] !== 1'bz) && CH1_TXDATA_delay[255]; // rv 0 + assign CH1_TXDATA_in[25] = (CH1_TXDATA[25] !== 1'bz) && CH1_TXDATA_delay[25]; // rv 0 + assign CH1_TXDATA_in[26] = (CH1_TXDATA[26] !== 1'bz) && CH1_TXDATA_delay[26]; // rv 0 + assign CH1_TXDATA_in[27] = (CH1_TXDATA[27] !== 1'bz) && CH1_TXDATA_delay[27]; // rv 0 + assign CH1_TXDATA_in[28] = (CH1_TXDATA[28] !== 1'bz) && CH1_TXDATA_delay[28]; // rv 0 + assign CH1_TXDATA_in[29] = (CH1_TXDATA[29] !== 1'bz) && CH1_TXDATA_delay[29]; // rv 0 + assign CH1_TXDATA_in[2] = (CH1_TXDATA[2] !== 1'bz) && CH1_TXDATA_delay[2]; // rv 0 + assign CH1_TXDATA_in[30] = (CH1_TXDATA[30] !== 1'bz) && CH1_TXDATA_delay[30]; // rv 0 + assign CH1_TXDATA_in[31] = (CH1_TXDATA[31] !== 1'bz) && CH1_TXDATA_delay[31]; // rv 0 + assign CH1_TXDATA_in[32] = (CH1_TXDATA[32] !== 1'bz) && CH1_TXDATA_delay[32]; // rv 0 + assign CH1_TXDATA_in[33] = (CH1_TXDATA[33] !== 1'bz) && CH1_TXDATA_delay[33]; // rv 0 + assign CH1_TXDATA_in[34] = (CH1_TXDATA[34] !== 1'bz) && CH1_TXDATA_delay[34]; // rv 0 + assign CH1_TXDATA_in[35] = (CH1_TXDATA[35] !== 1'bz) && CH1_TXDATA_delay[35]; // rv 0 + assign CH1_TXDATA_in[36] = (CH1_TXDATA[36] !== 1'bz) && CH1_TXDATA_delay[36]; // rv 0 + assign CH1_TXDATA_in[37] = (CH1_TXDATA[37] !== 1'bz) && CH1_TXDATA_delay[37]; // rv 0 + assign CH1_TXDATA_in[38] = (CH1_TXDATA[38] !== 1'bz) && CH1_TXDATA_delay[38]; // rv 0 + assign CH1_TXDATA_in[39] = (CH1_TXDATA[39] !== 1'bz) && CH1_TXDATA_delay[39]; // rv 0 + assign CH1_TXDATA_in[3] = (CH1_TXDATA[3] !== 1'bz) && CH1_TXDATA_delay[3]; // rv 0 + assign CH1_TXDATA_in[40] = (CH1_TXDATA[40] !== 1'bz) && CH1_TXDATA_delay[40]; // rv 0 + assign CH1_TXDATA_in[41] = (CH1_TXDATA[41] !== 1'bz) && CH1_TXDATA_delay[41]; // rv 0 + assign CH1_TXDATA_in[42] = (CH1_TXDATA[42] !== 1'bz) && CH1_TXDATA_delay[42]; // rv 0 + assign CH1_TXDATA_in[43] = (CH1_TXDATA[43] !== 1'bz) && CH1_TXDATA_delay[43]; // rv 0 + assign CH1_TXDATA_in[44] = (CH1_TXDATA[44] !== 1'bz) && CH1_TXDATA_delay[44]; // rv 0 + assign CH1_TXDATA_in[45] = (CH1_TXDATA[45] !== 1'bz) && CH1_TXDATA_delay[45]; // rv 0 + assign CH1_TXDATA_in[46] = (CH1_TXDATA[46] !== 1'bz) && CH1_TXDATA_delay[46]; // rv 0 + assign CH1_TXDATA_in[47] = (CH1_TXDATA[47] !== 1'bz) && CH1_TXDATA_delay[47]; // rv 0 + assign CH1_TXDATA_in[48] = (CH1_TXDATA[48] !== 1'bz) && CH1_TXDATA_delay[48]; // rv 0 + assign CH1_TXDATA_in[49] = (CH1_TXDATA[49] !== 1'bz) && CH1_TXDATA_delay[49]; // rv 0 + assign CH1_TXDATA_in[4] = (CH1_TXDATA[4] !== 1'bz) && CH1_TXDATA_delay[4]; // rv 0 + assign CH1_TXDATA_in[50] = (CH1_TXDATA[50] !== 1'bz) && CH1_TXDATA_delay[50]; // rv 0 + assign CH1_TXDATA_in[51] = (CH1_TXDATA[51] !== 1'bz) && CH1_TXDATA_delay[51]; // rv 0 + assign CH1_TXDATA_in[52] = (CH1_TXDATA[52] !== 1'bz) && CH1_TXDATA_delay[52]; // rv 0 + assign CH1_TXDATA_in[53] = (CH1_TXDATA[53] !== 1'bz) && CH1_TXDATA_delay[53]; // rv 0 + assign CH1_TXDATA_in[54] = (CH1_TXDATA[54] !== 1'bz) && CH1_TXDATA_delay[54]; // rv 0 + assign CH1_TXDATA_in[55] = (CH1_TXDATA[55] !== 1'bz) && CH1_TXDATA_delay[55]; // rv 0 + assign CH1_TXDATA_in[56] = (CH1_TXDATA[56] !== 1'bz) && CH1_TXDATA_delay[56]; // rv 0 + assign CH1_TXDATA_in[57] = (CH1_TXDATA[57] !== 1'bz) && CH1_TXDATA_delay[57]; // rv 0 + assign CH1_TXDATA_in[58] = (CH1_TXDATA[58] !== 1'bz) && CH1_TXDATA_delay[58]; // rv 0 + assign CH1_TXDATA_in[59] = (CH1_TXDATA[59] !== 1'bz) && CH1_TXDATA_delay[59]; // rv 0 + assign CH1_TXDATA_in[5] = (CH1_TXDATA[5] !== 1'bz) && CH1_TXDATA_delay[5]; // rv 0 + assign CH1_TXDATA_in[60] = (CH1_TXDATA[60] !== 1'bz) && CH1_TXDATA_delay[60]; // rv 0 + assign CH1_TXDATA_in[61] = (CH1_TXDATA[61] !== 1'bz) && CH1_TXDATA_delay[61]; // rv 0 + assign CH1_TXDATA_in[62] = (CH1_TXDATA[62] !== 1'bz) && CH1_TXDATA_delay[62]; // rv 0 + assign CH1_TXDATA_in[63] = (CH1_TXDATA[63] !== 1'bz) && CH1_TXDATA_delay[63]; // rv 0 + assign CH1_TXDATA_in[64] = (CH1_TXDATA[64] !== 1'bz) && CH1_TXDATA_delay[64]; // rv 0 + assign CH1_TXDATA_in[65] = (CH1_TXDATA[65] !== 1'bz) && CH1_TXDATA_delay[65]; // rv 0 + assign CH1_TXDATA_in[66] = (CH1_TXDATA[66] !== 1'bz) && CH1_TXDATA_delay[66]; // rv 0 + assign CH1_TXDATA_in[67] = (CH1_TXDATA[67] !== 1'bz) && CH1_TXDATA_delay[67]; // rv 0 + assign CH1_TXDATA_in[68] = (CH1_TXDATA[68] !== 1'bz) && CH1_TXDATA_delay[68]; // rv 0 + assign CH1_TXDATA_in[69] = (CH1_TXDATA[69] !== 1'bz) && CH1_TXDATA_delay[69]; // rv 0 + assign CH1_TXDATA_in[6] = (CH1_TXDATA[6] !== 1'bz) && CH1_TXDATA_delay[6]; // rv 0 + assign CH1_TXDATA_in[70] = (CH1_TXDATA[70] !== 1'bz) && CH1_TXDATA_delay[70]; // rv 0 + assign CH1_TXDATA_in[71] = (CH1_TXDATA[71] !== 1'bz) && CH1_TXDATA_delay[71]; // rv 0 + assign CH1_TXDATA_in[72] = (CH1_TXDATA[72] !== 1'bz) && CH1_TXDATA_delay[72]; // rv 0 + assign CH1_TXDATA_in[73] = (CH1_TXDATA[73] !== 1'bz) && CH1_TXDATA_delay[73]; // rv 0 + assign CH1_TXDATA_in[74] = (CH1_TXDATA[74] !== 1'bz) && CH1_TXDATA_delay[74]; // rv 0 + assign CH1_TXDATA_in[75] = (CH1_TXDATA[75] !== 1'bz) && CH1_TXDATA_delay[75]; // rv 0 + assign CH1_TXDATA_in[76] = (CH1_TXDATA[76] !== 1'bz) && CH1_TXDATA_delay[76]; // rv 0 + assign CH1_TXDATA_in[77] = (CH1_TXDATA[77] !== 1'bz) && CH1_TXDATA_delay[77]; // rv 0 + assign CH1_TXDATA_in[78] = (CH1_TXDATA[78] !== 1'bz) && CH1_TXDATA_delay[78]; // rv 0 + assign CH1_TXDATA_in[79] = (CH1_TXDATA[79] !== 1'bz) && CH1_TXDATA_delay[79]; // rv 0 + assign CH1_TXDATA_in[7] = (CH1_TXDATA[7] !== 1'bz) && CH1_TXDATA_delay[7]; // rv 0 + assign CH1_TXDATA_in[80] = (CH1_TXDATA[80] !== 1'bz) && CH1_TXDATA_delay[80]; // rv 0 + assign CH1_TXDATA_in[81] = (CH1_TXDATA[81] !== 1'bz) && CH1_TXDATA_delay[81]; // rv 0 + assign CH1_TXDATA_in[82] = (CH1_TXDATA[82] !== 1'bz) && CH1_TXDATA_delay[82]; // rv 0 + assign CH1_TXDATA_in[83] = (CH1_TXDATA[83] !== 1'bz) && CH1_TXDATA_delay[83]; // rv 0 + assign CH1_TXDATA_in[84] = (CH1_TXDATA[84] !== 1'bz) && CH1_TXDATA_delay[84]; // rv 0 + assign CH1_TXDATA_in[85] = (CH1_TXDATA[85] !== 1'bz) && CH1_TXDATA_delay[85]; // rv 0 + assign CH1_TXDATA_in[86] = (CH1_TXDATA[86] !== 1'bz) && CH1_TXDATA_delay[86]; // rv 0 + assign CH1_TXDATA_in[87] = (CH1_TXDATA[87] !== 1'bz) && CH1_TXDATA_delay[87]; // rv 0 + assign CH1_TXDATA_in[88] = (CH1_TXDATA[88] !== 1'bz) && CH1_TXDATA_delay[88]; // rv 0 + assign CH1_TXDATA_in[89] = (CH1_TXDATA[89] !== 1'bz) && CH1_TXDATA_delay[89]; // rv 0 + assign CH1_TXDATA_in[8] = (CH1_TXDATA[8] !== 1'bz) && CH1_TXDATA_delay[8]; // rv 0 + assign CH1_TXDATA_in[90] = (CH1_TXDATA[90] !== 1'bz) && CH1_TXDATA_delay[90]; // rv 0 + assign CH1_TXDATA_in[91] = (CH1_TXDATA[91] !== 1'bz) && CH1_TXDATA_delay[91]; // rv 0 + assign CH1_TXDATA_in[92] = (CH1_TXDATA[92] !== 1'bz) && CH1_TXDATA_delay[92]; // rv 0 + assign CH1_TXDATA_in[93] = (CH1_TXDATA[93] !== 1'bz) && CH1_TXDATA_delay[93]; // rv 0 + assign CH1_TXDATA_in[94] = (CH1_TXDATA[94] !== 1'bz) && CH1_TXDATA_delay[94]; // rv 0 + assign CH1_TXDATA_in[95] = (CH1_TXDATA[95] !== 1'bz) && CH1_TXDATA_delay[95]; // rv 0 + assign CH1_TXDATA_in[96] = (CH1_TXDATA[96] !== 1'bz) && CH1_TXDATA_delay[96]; // rv 0 + assign CH1_TXDATA_in[97] = (CH1_TXDATA[97] !== 1'bz) && CH1_TXDATA_delay[97]; // rv 0 + assign CH1_TXDATA_in[98] = (CH1_TXDATA[98] !== 1'bz) && CH1_TXDATA_delay[98]; // rv 0 + assign CH1_TXDATA_in[99] = (CH1_TXDATA[99] !== 1'bz) && CH1_TXDATA_delay[99]; // rv 0 + assign CH1_TXDATA_in[9] = (CH1_TXDATA[9] !== 1'bz) && CH1_TXDATA_delay[9]; // rv 0 + assign CH1_TXINHIBIT_in = (CH1_TXINHIBIT !== 1'bz) && CH1_TXINHIBIT_delay; // rv 0 + assign CH1_TXPOLARITY_in = (CH1_TXPOLARITY !== 1'bz) && CH1_TXPOLARITY_delay; // rv 0 + assign CH1_TXPRBSINERR_in = (CH1_TXPRBSINERR !== 1'bz) && CH1_TXPRBSINERR_delay; // rv 0 + assign CH1_TXPRBSPTN_in[0] = (CH1_TXPRBSPTN[0] !== 1'bz) && CH1_TXPRBSPTN_delay[0]; // rv 0 + assign CH1_TXPRBSPTN_in[1] = (CH1_TXPRBSPTN[1] !== 1'bz) && CH1_TXPRBSPTN_delay[1]; // rv 0 + assign CH1_TXPRBSPTN_in[2] = (CH1_TXPRBSPTN[2] !== 1'bz) && CH1_TXPRBSPTN_delay[2]; // rv 0 + assign CH1_TXPRBSPTN_in[3] = (CH1_TXPRBSPTN[3] !== 1'bz) && CH1_TXPRBSPTN_delay[3]; // rv 0 + assign CH1_TXQPRBSEN_in = (CH1_TXQPRBSEN !== 1'bz) && CH1_TXQPRBSEN_delay; // rv 0 + assign CH1_TXUSRCLK2_in = (CH1_TXUSRCLK2 !== 1'bz) && CH1_TXUSRCLK2_delay; // rv 0 + assign CH1_TXUSRCLK_in = (CH1_TXUSRCLK !== 1'bz) && CH1_TXUSRCLK_delay; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR_delay[10]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign FECCTRLRX0BITSLIPFS_in = (FECCTRLRX0BITSLIPFS !== 1'bz) && FECCTRLRX0BITSLIPFS_delay; // rv 0 + assign FECCTRLRX1BITSLIPFS_in = (FECCTRLRX1BITSLIPFS !== 1'bz) && FECCTRLRX1BITSLIPFS_delay; // rv 0 +`else + assign CH0_AXISEN_in = (CH0_AXISEN !== 1'bz) && CH0_AXISEN; // rv 0 + assign CH0_AXISTRDY_in = (CH0_AXISTRDY !== 1'bz) && CH0_AXISTRDY; // rv 0 + assign CH0_RXEQTRAINING_in = (CH0_RXEQTRAINING !== 1'bz) && CH0_RXEQTRAINING; // rv 0 + assign CH0_RXPOLARITY_in = (CH0_RXPOLARITY !== 1'bz) && CH0_RXPOLARITY; // rv 0 + assign CH0_RXPRBSCNTSTOP_in = (CH0_RXPRBSCNTSTOP !== 1'bz) && CH0_RXPRBSCNTSTOP; // rv 0 + assign CH0_RXPRBSPTN_in[0] = (CH0_RXPRBSPTN[0] !== 1'bz) && CH0_RXPRBSPTN[0]; // rv 0 + assign CH0_RXPRBSPTN_in[1] = (CH0_RXPRBSPTN[1] !== 1'bz) && CH0_RXPRBSPTN[1]; // rv 0 + assign CH0_RXPRBSPTN_in[2] = (CH0_RXPRBSPTN[2] !== 1'bz) && CH0_RXPRBSPTN[2]; // rv 0 + assign CH0_RXPRBSPTN_in[3] = (CH0_RXPRBSPTN[3] !== 1'bz) && CH0_RXPRBSPTN[3]; // rv 0 + assign CH0_RXQPRBSEN_in = (CH0_RXQPRBSEN !== 1'bz) && CH0_RXQPRBSEN; // rv 0 + assign CH0_RXUSRCLK2_in = (CH0_RXUSRCLK2 !== 1'bz) && CH0_RXUSRCLK2; // rv 0 + assign CH0_RXUSRCLK_in = (CH0_RXUSRCLK !== 1'bz) && CH0_RXUSRCLK; // rv 0 + assign CH0_TXDATASTART_in = (CH0_TXDATASTART !== 1'bz) && CH0_TXDATASTART; // rv 0 + assign CH0_TXDATA_in[0] = (CH0_TXDATA[0] !== 1'bz) && CH0_TXDATA[0]; // rv 0 + assign CH0_TXDATA_in[100] = (CH0_TXDATA[100] !== 1'bz) && CH0_TXDATA[100]; // rv 0 + assign CH0_TXDATA_in[101] = (CH0_TXDATA[101] !== 1'bz) && CH0_TXDATA[101]; // rv 0 + assign CH0_TXDATA_in[102] = (CH0_TXDATA[102] !== 1'bz) && CH0_TXDATA[102]; // rv 0 + assign CH0_TXDATA_in[103] = (CH0_TXDATA[103] !== 1'bz) && CH0_TXDATA[103]; // rv 0 + assign CH0_TXDATA_in[104] = (CH0_TXDATA[104] !== 1'bz) && CH0_TXDATA[104]; // rv 0 + assign CH0_TXDATA_in[105] = (CH0_TXDATA[105] !== 1'bz) && CH0_TXDATA[105]; // rv 0 + assign CH0_TXDATA_in[106] = (CH0_TXDATA[106] !== 1'bz) && CH0_TXDATA[106]; // rv 0 + assign CH0_TXDATA_in[107] = (CH0_TXDATA[107] !== 1'bz) && CH0_TXDATA[107]; // rv 0 + assign CH0_TXDATA_in[108] = (CH0_TXDATA[108] !== 1'bz) && CH0_TXDATA[108]; // rv 0 + assign CH0_TXDATA_in[109] = (CH0_TXDATA[109] !== 1'bz) && CH0_TXDATA[109]; // rv 0 + assign CH0_TXDATA_in[10] = (CH0_TXDATA[10] !== 1'bz) && CH0_TXDATA[10]; // rv 0 + assign CH0_TXDATA_in[110] = (CH0_TXDATA[110] !== 1'bz) && CH0_TXDATA[110]; // rv 0 + assign CH0_TXDATA_in[111] = (CH0_TXDATA[111] !== 1'bz) && CH0_TXDATA[111]; // rv 0 + assign CH0_TXDATA_in[112] = (CH0_TXDATA[112] !== 1'bz) && CH0_TXDATA[112]; // rv 0 + assign CH0_TXDATA_in[113] = (CH0_TXDATA[113] !== 1'bz) && CH0_TXDATA[113]; // rv 0 + assign CH0_TXDATA_in[114] = (CH0_TXDATA[114] !== 1'bz) && CH0_TXDATA[114]; // rv 0 + assign CH0_TXDATA_in[115] = (CH0_TXDATA[115] !== 1'bz) && CH0_TXDATA[115]; // rv 0 + assign CH0_TXDATA_in[116] = (CH0_TXDATA[116] !== 1'bz) && CH0_TXDATA[116]; // rv 0 + assign CH0_TXDATA_in[117] = (CH0_TXDATA[117] !== 1'bz) && CH0_TXDATA[117]; // rv 0 + assign CH0_TXDATA_in[118] = (CH0_TXDATA[118] !== 1'bz) && CH0_TXDATA[118]; // rv 0 + assign CH0_TXDATA_in[119] = (CH0_TXDATA[119] !== 1'bz) && CH0_TXDATA[119]; // rv 0 + assign CH0_TXDATA_in[11] = (CH0_TXDATA[11] !== 1'bz) && CH0_TXDATA[11]; // rv 0 + assign CH0_TXDATA_in[120] = (CH0_TXDATA[120] !== 1'bz) && CH0_TXDATA[120]; // rv 0 + assign CH0_TXDATA_in[121] = (CH0_TXDATA[121] !== 1'bz) && CH0_TXDATA[121]; // rv 0 + assign CH0_TXDATA_in[122] = (CH0_TXDATA[122] !== 1'bz) && CH0_TXDATA[122]; // rv 0 + assign CH0_TXDATA_in[123] = (CH0_TXDATA[123] !== 1'bz) && CH0_TXDATA[123]; // rv 0 + assign CH0_TXDATA_in[124] = (CH0_TXDATA[124] !== 1'bz) && CH0_TXDATA[124]; // rv 0 + assign CH0_TXDATA_in[125] = (CH0_TXDATA[125] !== 1'bz) && CH0_TXDATA[125]; // rv 0 + assign CH0_TXDATA_in[126] = (CH0_TXDATA[126] !== 1'bz) && CH0_TXDATA[126]; // rv 0 + assign CH0_TXDATA_in[127] = (CH0_TXDATA[127] !== 1'bz) && CH0_TXDATA[127]; // rv 0 + assign CH0_TXDATA_in[128] = (CH0_TXDATA[128] !== 1'bz) && CH0_TXDATA[128]; // rv 0 + assign CH0_TXDATA_in[129] = (CH0_TXDATA[129] !== 1'bz) && CH0_TXDATA[129]; // rv 0 + assign CH0_TXDATA_in[12] = (CH0_TXDATA[12] !== 1'bz) && CH0_TXDATA[12]; // rv 0 + assign CH0_TXDATA_in[130] = (CH0_TXDATA[130] !== 1'bz) && CH0_TXDATA[130]; // rv 0 + assign CH0_TXDATA_in[131] = (CH0_TXDATA[131] !== 1'bz) && CH0_TXDATA[131]; // rv 0 + assign CH0_TXDATA_in[132] = (CH0_TXDATA[132] !== 1'bz) && CH0_TXDATA[132]; // rv 0 + assign CH0_TXDATA_in[133] = (CH0_TXDATA[133] !== 1'bz) && CH0_TXDATA[133]; // rv 0 + assign CH0_TXDATA_in[134] = (CH0_TXDATA[134] !== 1'bz) && CH0_TXDATA[134]; // rv 0 + assign CH0_TXDATA_in[135] = (CH0_TXDATA[135] !== 1'bz) && CH0_TXDATA[135]; // rv 0 + assign CH0_TXDATA_in[136] = (CH0_TXDATA[136] !== 1'bz) && CH0_TXDATA[136]; // rv 0 + assign CH0_TXDATA_in[137] = (CH0_TXDATA[137] !== 1'bz) && CH0_TXDATA[137]; // rv 0 + assign CH0_TXDATA_in[138] = (CH0_TXDATA[138] !== 1'bz) && CH0_TXDATA[138]; // rv 0 + assign CH0_TXDATA_in[139] = (CH0_TXDATA[139] !== 1'bz) && CH0_TXDATA[139]; // rv 0 + assign CH0_TXDATA_in[13] = (CH0_TXDATA[13] !== 1'bz) && CH0_TXDATA[13]; // rv 0 + assign CH0_TXDATA_in[140] = (CH0_TXDATA[140] !== 1'bz) && CH0_TXDATA[140]; // rv 0 + assign CH0_TXDATA_in[141] = (CH0_TXDATA[141] !== 1'bz) && CH0_TXDATA[141]; // rv 0 + assign CH0_TXDATA_in[142] = (CH0_TXDATA[142] !== 1'bz) && CH0_TXDATA[142]; // rv 0 + assign CH0_TXDATA_in[143] = (CH0_TXDATA[143] !== 1'bz) && CH0_TXDATA[143]; // rv 0 + assign CH0_TXDATA_in[144] = (CH0_TXDATA[144] !== 1'bz) && CH0_TXDATA[144]; // rv 0 + assign CH0_TXDATA_in[145] = (CH0_TXDATA[145] !== 1'bz) && CH0_TXDATA[145]; // rv 0 + assign CH0_TXDATA_in[146] = (CH0_TXDATA[146] !== 1'bz) && CH0_TXDATA[146]; // rv 0 + assign CH0_TXDATA_in[147] = (CH0_TXDATA[147] !== 1'bz) && CH0_TXDATA[147]; // rv 0 + assign CH0_TXDATA_in[148] = (CH0_TXDATA[148] !== 1'bz) && CH0_TXDATA[148]; // rv 0 + assign CH0_TXDATA_in[149] = (CH0_TXDATA[149] !== 1'bz) && CH0_TXDATA[149]; // rv 0 + assign CH0_TXDATA_in[14] = (CH0_TXDATA[14] !== 1'bz) && CH0_TXDATA[14]; // rv 0 + assign CH0_TXDATA_in[150] = (CH0_TXDATA[150] !== 1'bz) && CH0_TXDATA[150]; // rv 0 + assign CH0_TXDATA_in[151] = (CH0_TXDATA[151] !== 1'bz) && CH0_TXDATA[151]; // rv 0 + assign CH0_TXDATA_in[152] = (CH0_TXDATA[152] !== 1'bz) && CH0_TXDATA[152]; // rv 0 + assign CH0_TXDATA_in[153] = (CH0_TXDATA[153] !== 1'bz) && CH0_TXDATA[153]; // rv 0 + assign CH0_TXDATA_in[154] = (CH0_TXDATA[154] !== 1'bz) && CH0_TXDATA[154]; // rv 0 + assign CH0_TXDATA_in[155] = (CH0_TXDATA[155] !== 1'bz) && CH0_TXDATA[155]; // rv 0 + assign CH0_TXDATA_in[156] = (CH0_TXDATA[156] !== 1'bz) && CH0_TXDATA[156]; // rv 0 + assign CH0_TXDATA_in[157] = (CH0_TXDATA[157] !== 1'bz) && CH0_TXDATA[157]; // rv 0 + assign CH0_TXDATA_in[158] = (CH0_TXDATA[158] !== 1'bz) && CH0_TXDATA[158]; // rv 0 + assign CH0_TXDATA_in[159] = (CH0_TXDATA[159] !== 1'bz) && CH0_TXDATA[159]; // rv 0 + assign CH0_TXDATA_in[15] = (CH0_TXDATA[15] !== 1'bz) && CH0_TXDATA[15]; // rv 0 + assign CH0_TXDATA_in[160] = (CH0_TXDATA[160] !== 1'bz) && CH0_TXDATA[160]; // rv 0 + assign CH0_TXDATA_in[161] = (CH0_TXDATA[161] !== 1'bz) && CH0_TXDATA[161]; // rv 0 + assign CH0_TXDATA_in[162] = (CH0_TXDATA[162] !== 1'bz) && CH0_TXDATA[162]; // rv 0 + assign CH0_TXDATA_in[163] = (CH0_TXDATA[163] !== 1'bz) && CH0_TXDATA[163]; // rv 0 + assign CH0_TXDATA_in[164] = (CH0_TXDATA[164] !== 1'bz) && CH0_TXDATA[164]; // rv 0 + assign CH0_TXDATA_in[165] = (CH0_TXDATA[165] !== 1'bz) && CH0_TXDATA[165]; // rv 0 + assign CH0_TXDATA_in[166] = (CH0_TXDATA[166] !== 1'bz) && CH0_TXDATA[166]; // rv 0 + assign CH0_TXDATA_in[167] = (CH0_TXDATA[167] !== 1'bz) && CH0_TXDATA[167]; // rv 0 + assign CH0_TXDATA_in[168] = (CH0_TXDATA[168] !== 1'bz) && CH0_TXDATA[168]; // rv 0 + assign CH0_TXDATA_in[169] = (CH0_TXDATA[169] !== 1'bz) && CH0_TXDATA[169]; // rv 0 + assign CH0_TXDATA_in[16] = (CH0_TXDATA[16] !== 1'bz) && CH0_TXDATA[16]; // rv 0 + assign CH0_TXDATA_in[170] = (CH0_TXDATA[170] !== 1'bz) && CH0_TXDATA[170]; // rv 0 + assign CH0_TXDATA_in[171] = (CH0_TXDATA[171] !== 1'bz) && CH0_TXDATA[171]; // rv 0 + assign CH0_TXDATA_in[172] = (CH0_TXDATA[172] !== 1'bz) && CH0_TXDATA[172]; // rv 0 + assign CH0_TXDATA_in[173] = (CH0_TXDATA[173] !== 1'bz) && CH0_TXDATA[173]; // rv 0 + assign CH0_TXDATA_in[174] = (CH0_TXDATA[174] !== 1'bz) && CH0_TXDATA[174]; // rv 0 + assign CH0_TXDATA_in[175] = (CH0_TXDATA[175] !== 1'bz) && CH0_TXDATA[175]; // rv 0 + assign CH0_TXDATA_in[176] = (CH0_TXDATA[176] !== 1'bz) && CH0_TXDATA[176]; // rv 0 + assign CH0_TXDATA_in[177] = (CH0_TXDATA[177] !== 1'bz) && CH0_TXDATA[177]; // rv 0 + assign CH0_TXDATA_in[178] = (CH0_TXDATA[178] !== 1'bz) && CH0_TXDATA[178]; // rv 0 + assign CH0_TXDATA_in[179] = (CH0_TXDATA[179] !== 1'bz) && CH0_TXDATA[179]; // rv 0 + assign CH0_TXDATA_in[17] = (CH0_TXDATA[17] !== 1'bz) && CH0_TXDATA[17]; // rv 0 + assign CH0_TXDATA_in[180] = (CH0_TXDATA[180] !== 1'bz) && CH0_TXDATA[180]; // rv 0 + assign CH0_TXDATA_in[181] = (CH0_TXDATA[181] !== 1'bz) && CH0_TXDATA[181]; // rv 0 + assign CH0_TXDATA_in[182] = (CH0_TXDATA[182] !== 1'bz) && CH0_TXDATA[182]; // rv 0 + assign CH0_TXDATA_in[183] = (CH0_TXDATA[183] !== 1'bz) && CH0_TXDATA[183]; // rv 0 + assign CH0_TXDATA_in[184] = (CH0_TXDATA[184] !== 1'bz) && CH0_TXDATA[184]; // rv 0 + assign CH0_TXDATA_in[185] = (CH0_TXDATA[185] !== 1'bz) && CH0_TXDATA[185]; // rv 0 + assign CH0_TXDATA_in[186] = (CH0_TXDATA[186] !== 1'bz) && CH0_TXDATA[186]; // rv 0 + assign CH0_TXDATA_in[187] = (CH0_TXDATA[187] !== 1'bz) && CH0_TXDATA[187]; // rv 0 + assign CH0_TXDATA_in[188] = (CH0_TXDATA[188] !== 1'bz) && CH0_TXDATA[188]; // rv 0 + assign CH0_TXDATA_in[189] = (CH0_TXDATA[189] !== 1'bz) && CH0_TXDATA[189]; // rv 0 + assign CH0_TXDATA_in[18] = (CH0_TXDATA[18] !== 1'bz) && CH0_TXDATA[18]; // rv 0 + assign CH0_TXDATA_in[190] = (CH0_TXDATA[190] !== 1'bz) && CH0_TXDATA[190]; // rv 0 + assign CH0_TXDATA_in[191] = (CH0_TXDATA[191] !== 1'bz) && CH0_TXDATA[191]; // rv 0 + assign CH0_TXDATA_in[192] = (CH0_TXDATA[192] !== 1'bz) && CH0_TXDATA[192]; // rv 0 + assign CH0_TXDATA_in[193] = (CH0_TXDATA[193] !== 1'bz) && CH0_TXDATA[193]; // rv 0 + assign CH0_TXDATA_in[194] = (CH0_TXDATA[194] !== 1'bz) && CH0_TXDATA[194]; // rv 0 + assign CH0_TXDATA_in[195] = (CH0_TXDATA[195] !== 1'bz) && CH0_TXDATA[195]; // rv 0 + assign CH0_TXDATA_in[196] = (CH0_TXDATA[196] !== 1'bz) && CH0_TXDATA[196]; // rv 0 + assign CH0_TXDATA_in[197] = (CH0_TXDATA[197] !== 1'bz) && CH0_TXDATA[197]; // rv 0 + assign CH0_TXDATA_in[198] = (CH0_TXDATA[198] !== 1'bz) && CH0_TXDATA[198]; // rv 0 + assign CH0_TXDATA_in[199] = (CH0_TXDATA[199] !== 1'bz) && CH0_TXDATA[199]; // rv 0 + assign CH0_TXDATA_in[19] = (CH0_TXDATA[19] !== 1'bz) && CH0_TXDATA[19]; // rv 0 + assign CH0_TXDATA_in[1] = (CH0_TXDATA[1] !== 1'bz) && CH0_TXDATA[1]; // rv 0 + assign CH0_TXDATA_in[200] = (CH0_TXDATA[200] !== 1'bz) && CH0_TXDATA[200]; // rv 0 + assign CH0_TXDATA_in[201] = (CH0_TXDATA[201] !== 1'bz) && CH0_TXDATA[201]; // rv 0 + assign CH0_TXDATA_in[202] = (CH0_TXDATA[202] !== 1'bz) && CH0_TXDATA[202]; // rv 0 + assign CH0_TXDATA_in[203] = (CH0_TXDATA[203] !== 1'bz) && CH0_TXDATA[203]; // rv 0 + assign CH0_TXDATA_in[204] = (CH0_TXDATA[204] !== 1'bz) && CH0_TXDATA[204]; // rv 0 + assign CH0_TXDATA_in[205] = (CH0_TXDATA[205] !== 1'bz) && CH0_TXDATA[205]; // rv 0 + assign CH0_TXDATA_in[206] = (CH0_TXDATA[206] !== 1'bz) && CH0_TXDATA[206]; // rv 0 + assign CH0_TXDATA_in[207] = (CH0_TXDATA[207] !== 1'bz) && CH0_TXDATA[207]; // rv 0 + assign CH0_TXDATA_in[208] = (CH0_TXDATA[208] !== 1'bz) && CH0_TXDATA[208]; // rv 0 + assign CH0_TXDATA_in[209] = (CH0_TXDATA[209] !== 1'bz) && CH0_TXDATA[209]; // rv 0 + assign CH0_TXDATA_in[20] = (CH0_TXDATA[20] !== 1'bz) && CH0_TXDATA[20]; // rv 0 + assign CH0_TXDATA_in[210] = (CH0_TXDATA[210] !== 1'bz) && CH0_TXDATA[210]; // rv 0 + assign CH0_TXDATA_in[211] = (CH0_TXDATA[211] !== 1'bz) && CH0_TXDATA[211]; // rv 0 + assign CH0_TXDATA_in[212] = (CH0_TXDATA[212] !== 1'bz) && CH0_TXDATA[212]; // rv 0 + assign CH0_TXDATA_in[213] = (CH0_TXDATA[213] !== 1'bz) && CH0_TXDATA[213]; // rv 0 + assign CH0_TXDATA_in[214] = (CH0_TXDATA[214] !== 1'bz) && CH0_TXDATA[214]; // rv 0 + assign CH0_TXDATA_in[215] = (CH0_TXDATA[215] !== 1'bz) && CH0_TXDATA[215]; // rv 0 + assign CH0_TXDATA_in[216] = (CH0_TXDATA[216] !== 1'bz) && CH0_TXDATA[216]; // rv 0 + assign CH0_TXDATA_in[217] = (CH0_TXDATA[217] !== 1'bz) && CH0_TXDATA[217]; // rv 0 + assign CH0_TXDATA_in[218] = (CH0_TXDATA[218] !== 1'bz) && CH0_TXDATA[218]; // rv 0 + assign CH0_TXDATA_in[219] = (CH0_TXDATA[219] !== 1'bz) && CH0_TXDATA[219]; // rv 0 + assign CH0_TXDATA_in[21] = (CH0_TXDATA[21] !== 1'bz) && CH0_TXDATA[21]; // rv 0 + assign CH0_TXDATA_in[220] = (CH0_TXDATA[220] !== 1'bz) && CH0_TXDATA[220]; // rv 0 + assign CH0_TXDATA_in[221] = (CH0_TXDATA[221] !== 1'bz) && CH0_TXDATA[221]; // rv 0 + assign CH0_TXDATA_in[222] = (CH0_TXDATA[222] !== 1'bz) && CH0_TXDATA[222]; // rv 0 + assign CH0_TXDATA_in[223] = (CH0_TXDATA[223] !== 1'bz) && CH0_TXDATA[223]; // rv 0 + assign CH0_TXDATA_in[224] = (CH0_TXDATA[224] !== 1'bz) && CH0_TXDATA[224]; // rv 0 + assign CH0_TXDATA_in[225] = (CH0_TXDATA[225] !== 1'bz) && CH0_TXDATA[225]; // rv 0 + assign CH0_TXDATA_in[226] = (CH0_TXDATA[226] !== 1'bz) && CH0_TXDATA[226]; // rv 0 + assign CH0_TXDATA_in[227] = (CH0_TXDATA[227] !== 1'bz) && CH0_TXDATA[227]; // rv 0 + assign CH0_TXDATA_in[228] = (CH0_TXDATA[228] !== 1'bz) && CH0_TXDATA[228]; // rv 0 + assign CH0_TXDATA_in[229] = (CH0_TXDATA[229] !== 1'bz) && CH0_TXDATA[229]; // rv 0 + assign CH0_TXDATA_in[22] = (CH0_TXDATA[22] !== 1'bz) && CH0_TXDATA[22]; // rv 0 + assign CH0_TXDATA_in[230] = (CH0_TXDATA[230] !== 1'bz) && CH0_TXDATA[230]; // rv 0 + assign CH0_TXDATA_in[231] = (CH0_TXDATA[231] !== 1'bz) && CH0_TXDATA[231]; // rv 0 + assign CH0_TXDATA_in[232] = (CH0_TXDATA[232] !== 1'bz) && CH0_TXDATA[232]; // rv 0 + assign CH0_TXDATA_in[233] = (CH0_TXDATA[233] !== 1'bz) && CH0_TXDATA[233]; // rv 0 + assign CH0_TXDATA_in[234] = (CH0_TXDATA[234] !== 1'bz) && CH0_TXDATA[234]; // rv 0 + assign CH0_TXDATA_in[235] = (CH0_TXDATA[235] !== 1'bz) && CH0_TXDATA[235]; // rv 0 + assign CH0_TXDATA_in[236] = (CH0_TXDATA[236] !== 1'bz) && CH0_TXDATA[236]; // rv 0 + assign CH0_TXDATA_in[237] = (CH0_TXDATA[237] !== 1'bz) && CH0_TXDATA[237]; // rv 0 + assign CH0_TXDATA_in[238] = (CH0_TXDATA[238] !== 1'bz) && CH0_TXDATA[238]; // rv 0 + assign CH0_TXDATA_in[239] = (CH0_TXDATA[239] !== 1'bz) && CH0_TXDATA[239]; // rv 0 + assign CH0_TXDATA_in[23] = (CH0_TXDATA[23] !== 1'bz) && CH0_TXDATA[23]; // rv 0 + assign CH0_TXDATA_in[240] = (CH0_TXDATA[240] !== 1'bz) && CH0_TXDATA[240]; // rv 0 + assign CH0_TXDATA_in[241] = (CH0_TXDATA[241] !== 1'bz) && CH0_TXDATA[241]; // rv 0 + assign CH0_TXDATA_in[242] = (CH0_TXDATA[242] !== 1'bz) && CH0_TXDATA[242]; // rv 0 + assign CH0_TXDATA_in[243] = (CH0_TXDATA[243] !== 1'bz) && CH0_TXDATA[243]; // rv 0 + assign CH0_TXDATA_in[244] = (CH0_TXDATA[244] !== 1'bz) && CH0_TXDATA[244]; // rv 0 + assign CH0_TXDATA_in[245] = (CH0_TXDATA[245] !== 1'bz) && CH0_TXDATA[245]; // rv 0 + assign CH0_TXDATA_in[246] = (CH0_TXDATA[246] !== 1'bz) && CH0_TXDATA[246]; // rv 0 + assign CH0_TXDATA_in[247] = (CH0_TXDATA[247] !== 1'bz) && CH0_TXDATA[247]; // rv 0 + assign CH0_TXDATA_in[248] = (CH0_TXDATA[248] !== 1'bz) && CH0_TXDATA[248]; // rv 0 + assign CH0_TXDATA_in[249] = (CH0_TXDATA[249] !== 1'bz) && CH0_TXDATA[249]; // rv 0 + assign CH0_TXDATA_in[24] = (CH0_TXDATA[24] !== 1'bz) && CH0_TXDATA[24]; // rv 0 + assign CH0_TXDATA_in[250] = (CH0_TXDATA[250] !== 1'bz) && CH0_TXDATA[250]; // rv 0 + assign CH0_TXDATA_in[251] = (CH0_TXDATA[251] !== 1'bz) && CH0_TXDATA[251]; // rv 0 + assign CH0_TXDATA_in[252] = (CH0_TXDATA[252] !== 1'bz) && CH0_TXDATA[252]; // rv 0 + assign CH0_TXDATA_in[253] = (CH0_TXDATA[253] !== 1'bz) && CH0_TXDATA[253]; // rv 0 + assign CH0_TXDATA_in[254] = (CH0_TXDATA[254] !== 1'bz) && CH0_TXDATA[254]; // rv 0 + assign CH0_TXDATA_in[255] = (CH0_TXDATA[255] !== 1'bz) && CH0_TXDATA[255]; // rv 0 + assign CH0_TXDATA_in[25] = (CH0_TXDATA[25] !== 1'bz) && CH0_TXDATA[25]; // rv 0 + assign CH0_TXDATA_in[26] = (CH0_TXDATA[26] !== 1'bz) && CH0_TXDATA[26]; // rv 0 + assign CH0_TXDATA_in[27] = (CH0_TXDATA[27] !== 1'bz) && CH0_TXDATA[27]; // rv 0 + assign CH0_TXDATA_in[28] = (CH0_TXDATA[28] !== 1'bz) && CH0_TXDATA[28]; // rv 0 + assign CH0_TXDATA_in[29] = (CH0_TXDATA[29] !== 1'bz) && CH0_TXDATA[29]; // rv 0 + assign CH0_TXDATA_in[2] = (CH0_TXDATA[2] !== 1'bz) && CH0_TXDATA[2]; // rv 0 + assign CH0_TXDATA_in[30] = (CH0_TXDATA[30] !== 1'bz) && CH0_TXDATA[30]; // rv 0 + assign CH0_TXDATA_in[31] = (CH0_TXDATA[31] !== 1'bz) && CH0_TXDATA[31]; // rv 0 + assign CH0_TXDATA_in[32] = (CH0_TXDATA[32] !== 1'bz) && CH0_TXDATA[32]; // rv 0 + assign CH0_TXDATA_in[33] = (CH0_TXDATA[33] !== 1'bz) && CH0_TXDATA[33]; // rv 0 + assign CH0_TXDATA_in[34] = (CH0_TXDATA[34] !== 1'bz) && CH0_TXDATA[34]; // rv 0 + assign CH0_TXDATA_in[35] = (CH0_TXDATA[35] !== 1'bz) && CH0_TXDATA[35]; // rv 0 + assign CH0_TXDATA_in[36] = (CH0_TXDATA[36] !== 1'bz) && CH0_TXDATA[36]; // rv 0 + assign CH0_TXDATA_in[37] = (CH0_TXDATA[37] !== 1'bz) && CH0_TXDATA[37]; // rv 0 + assign CH0_TXDATA_in[38] = (CH0_TXDATA[38] !== 1'bz) && CH0_TXDATA[38]; // rv 0 + assign CH0_TXDATA_in[39] = (CH0_TXDATA[39] !== 1'bz) && CH0_TXDATA[39]; // rv 0 + assign CH0_TXDATA_in[3] = (CH0_TXDATA[3] !== 1'bz) && CH0_TXDATA[3]; // rv 0 + assign CH0_TXDATA_in[40] = (CH0_TXDATA[40] !== 1'bz) && CH0_TXDATA[40]; // rv 0 + assign CH0_TXDATA_in[41] = (CH0_TXDATA[41] !== 1'bz) && CH0_TXDATA[41]; // rv 0 + assign CH0_TXDATA_in[42] = (CH0_TXDATA[42] !== 1'bz) && CH0_TXDATA[42]; // rv 0 + assign CH0_TXDATA_in[43] = (CH0_TXDATA[43] !== 1'bz) && CH0_TXDATA[43]; // rv 0 + assign CH0_TXDATA_in[44] = (CH0_TXDATA[44] !== 1'bz) && CH0_TXDATA[44]; // rv 0 + assign CH0_TXDATA_in[45] = (CH0_TXDATA[45] !== 1'bz) && CH0_TXDATA[45]; // rv 0 + assign CH0_TXDATA_in[46] = (CH0_TXDATA[46] !== 1'bz) && CH0_TXDATA[46]; // rv 0 + assign CH0_TXDATA_in[47] = (CH0_TXDATA[47] !== 1'bz) && CH0_TXDATA[47]; // rv 0 + assign CH0_TXDATA_in[48] = (CH0_TXDATA[48] !== 1'bz) && CH0_TXDATA[48]; // rv 0 + assign CH0_TXDATA_in[49] = (CH0_TXDATA[49] !== 1'bz) && CH0_TXDATA[49]; // rv 0 + assign CH0_TXDATA_in[4] = (CH0_TXDATA[4] !== 1'bz) && CH0_TXDATA[4]; // rv 0 + assign CH0_TXDATA_in[50] = (CH0_TXDATA[50] !== 1'bz) && CH0_TXDATA[50]; // rv 0 + assign CH0_TXDATA_in[51] = (CH0_TXDATA[51] !== 1'bz) && CH0_TXDATA[51]; // rv 0 + assign CH0_TXDATA_in[52] = (CH0_TXDATA[52] !== 1'bz) && CH0_TXDATA[52]; // rv 0 + assign CH0_TXDATA_in[53] = (CH0_TXDATA[53] !== 1'bz) && CH0_TXDATA[53]; // rv 0 + assign CH0_TXDATA_in[54] = (CH0_TXDATA[54] !== 1'bz) && CH0_TXDATA[54]; // rv 0 + assign CH0_TXDATA_in[55] = (CH0_TXDATA[55] !== 1'bz) && CH0_TXDATA[55]; // rv 0 + assign CH0_TXDATA_in[56] = (CH0_TXDATA[56] !== 1'bz) && CH0_TXDATA[56]; // rv 0 + assign CH0_TXDATA_in[57] = (CH0_TXDATA[57] !== 1'bz) && CH0_TXDATA[57]; // rv 0 + assign CH0_TXDATA_in[58] = (CH0_TXDATA[58] !== 1'bz) && CH0_TXDATA[58]; // rv 0 + assign CH0_TXDATA_in[59] = (CH0_TXDATA[59] !== 1'bz) && CH0_TXDATA[59]; // rv 0 + assign CH0_TXDATA_in[5] = (CH0_TXDATA[5] !== 1'bz) && CH0_TXDATA[5]; // rv 0 + assign CH0_TXDATA_in[60] = (CH0_TXDATA[60] !== 1'bz) && CH0_TXDATA[60]; // rv 0 + assign CH0_TXDATA_in[61] = (CH0_TXDATA[61] !== 1'bz) && CH0_TXDATA[61]; // rv 0 + assign CH0_TXDATA_in[62] = (CH0_TXDATA[62] !== 1'bz) && CH0_TXDATA[62]; // rv 0 + assign CH0_TXDATA_in[63] = (CH0_TXDATA[63] !== 1'bz) && CH0_TXDATA[63]; // rv 0 + assign CH0_TXDATA_in[64] = (CH0_TXDATA[64] !== 1'bz) && CH0_TXDATA[64]; // rv 0 + assign CH0_TXDATA_in[65] = (CH0_TXDATA[65] !== 1'bz) && CH0_TXDATA[65]; // rv 0 + assign CH0_TXDATA_in[66] = (CH0_TXDATA[66] !== 1'bz) && CH0_TXDATA[66]; // rv 0 + assign CH0_TXDATA_in[67] = (CH0_TXDATA[67] !== 1'bz) && CH0_TXDATA[67]; // rv 0 + assign CH0_TXDATA_in[68] = (CH0_TXDATA[68] !== 1'bz) && CH0_TXDATA[68]; // rv 0 + assign CH0_TXDATA_in[69] = (CH0_TXDATA[69] !== 1'bz) && CH0_TXDATA[69]; // rv 0 + assign CH0_TXDATA_in[6] = (CH0_TXDATA[6] !== 1'bz) && CH0_TXDATA[6]; // rv 0 + assign CH0_TXDATA_in[70] = (CH0_TXDATA[70] !== 1'bz) && CH0_TXDATA[70]; // rv 0 + assign CH0_TXDATA_in[71] = (CH0_TXDATA[71] !== 1'bz) && CH0_TXDATA[71]; // rv 0 + assign CH0_TXDATA_in[72] = (CH0_TXDATA[72] !== 1'bz) && CH0_TXDATA[72]; // rv 0 + assign CH0_TXDATA_in[73] = (CH0_TXDATA[73] !== 1'bz) && CH0_TXDATA[73]; // rv 0 + assign CH0_TXDATA_in[74] = (CH0_TXDATA[74] !== 1'bz) && CH0_TXDATA[74]; // rv 0 + assign CH0_TXDATA_in[75] = (CH0_TXDATA[75] !== 1'bz) && CH0_TXDATA[75]; // rv 0 + assign CH0_TXDATA_in[76] = (CH0_TXDATA[76] !== 1'bz) && CH0_TXDATA[76]; // rv 0 + assign CH0_TXDATA_in[77] = (CH0_TXDATA[77] !== 1'bz) && CH0_TXDATA[77]; // rv 0 + assign CH0_TXDATA_in[78] = (CH0_TXDATA[78] !== 1'bz) && CH0_TXDATA[78]; // rv 0 + assign CH0_TXDATA_in[79] = (CH0_TXDATA[79] !== 1'bz) && CH0_TXDATA[79]; // rv 0 + assign CH0_TXDATA_in[7] = (CH0_TXDATA[7] !== 1'bz) && CH0_TXDATA[7]; // rv 0 + assign CH0_TXDATA_in[80] = (CH0_TXDATA[80] !== 1'bz) && CH0_TXDATA[80]; // rv 0 + assign CH0_TXDATA_in[81] = (CH0_TXDATA[81] !== 1'bz) && CH0_TXDATA[81]; // rv 0 + assign CH0_TXDATA_in[82] = (CH0_TXDATA[82] !== 1'bz) && CH0_TXDATA[82]; // rv 0 + assign CH0_TXDATA_in[83] = (CH0_TXDATA[83] !== 1'bz) && CH0_TXDATA[83]; // rv 0 + assign CH0_TXDATA_in[84] = (CH0_TXDATA[84] !== 1'bz) && CH0_TXDATA[84]; // rv 0 + assign CH0_TXDATA_in[85] = (CH0_TXDATA[85] !== 1'bz) && CH0_TXDATA[85]; // rv 0 + assign CH0_TXDATA_in[86] = (CH0_TXDATA[86] !== 1'bz) && CH0_TXDATA[86]; // rv 0 + assign CH0_TXDATA_in[87] = (CH0_TXDATA[87] !== 1'bz) && CH0_TXDATA[87]; // rv 0 + assign CH0_TXDATA_in[88] = (CH0_TXDATA[88] !== 1'bz) && CH0_TXDATA[88]; // rv 0 + assign CH0_TXDATA_in[89] = (CH0_TXDATA[89] !== 1'bz) && CH0_TXDATA[89]; // rv 0 + assign CH0_TXDATA_in[8] = (CH0_TXDATA[8] !== 1'bz) && CH0_TXDATA[8]; // rv 0 + assign CH0_TXDATA_in[90] = (CH0_TXDATA[90] !== 1'bz) && CH0_TXDATA[90]; // rv 0 + assign CH0_TXDATA_in[91] = (CH0_TXDATA[91] !== 1'bz) && CH0_TXDATA[91]; // rv 0 + assign CH0_TXDATA_in[92] = (CH0_TXDATA[92] !== 1'bz) && CH0_TXDATA[92]; // rv 0 + assign CH0_TXDATA_in[93] = (CH0_TXDATA[93] !== 1'bz) && CH0_TXDATA[93]; // rv 0 + assign CH0_TXDATA_in[94] = (CH0_TXDATA[94] !== 1'bz) && CH0_TXDATA[94]; // rv 0 + assign CH0_TXDATA_in[95] = (CH0_TXDATA[95] !== 1'bz) && CH0_TXDATA[95]; // rv 0 + assign CH0_TXDATA_in[96] = (CH0_TXDATA[96] !== 1'bz) && CH0_TXDATA[96]; // rv 0 + assign CH0_TXDATA_in[97] = (CH0_TXDATA[97] !== 1'bz) && CH0_TXDATA[97]; // rv 0 + assign CH0_TXDATA_in[98] = (CH0_TXDATA[98] !== 1'bz) && CH0_TXDATA[98]; // rv 0 + assign CH0_TXDATA_in[99] = (CH0_TXDATA[99] !== 1'bz) && CH0_TXDATA[99]; // rv 0 + assign CH0_TXDATA_in[9] = (CH0_TXDATA[9] !== 1'bz) && CH0_TXDATA[9]; // rv 0 + assign CH0_TXINHIBIT_in = (CH0_TXINHIBIT !== 1'bz) && CH0_TXINHIBIT; // rv 0 + assign CH0_TXPOLARITY_in = (CH0_TXPOLARITY !== 1'bz) && CH0_TXPOLARITY; // rv 0 + assign CH0_TXPRBSINERR_in = (CH0_TXPRBSINERR !== 1'bz) && CH0_TXPRBSINERR; // rv 0 + assign CH0_TXPRBSPTN_in[0] = (CH0_TXPRBSPTN[0] !== 1'bz) && CH0_TXPRBSPTN[0]; // rv 0 + assign CH0_TXPRBSPTN_in[1] = (CH0_TXPRBSPTN[1] !== 1'bz) && CH0_TXPRBSPTN[1]; // rv 0 + assign CH0_TXPRBSPTN_in[2] = (CH0_TXPRBSPTN[2] !== 1'bz) && CH0_TXPRBSPTN[2]; // rv 0 + assign CH0_TXPRBSPTN_in[3] = (CH0_TXPRBSPTN[3] !== 1'bz) && CH0_TXPRBSPTN[3]; // rv 0 + assign CH0_TXQPRBSEN_in = (CH0_TXQPRBSEN !== 1'bz) && CH0_TXQPRBSEN; // rv 0 + assign CH0_TXUSRCLK2_in = (CH0_TXUSRCLK2 !== 1'bz) && CH0_TXUSRCLK2; // rv 0 + assign CH0_TXUSRCLK_in = (CH0_TXUSRCLK !== 1'bz) && CH0_TXUSRCLK; // rv 0 + assign CH1_AXISEN_in = (CH1_AXISEN !== 1'bz) && CH1_AXISEN; // rv 0 + assign CH1_AXISTRDY_in = (CH1_AXISTRDY !== 1'bz) && CH1_AXISTRDY; // rv 0 + assign CH1_RXEQTRAINING_in = (CH1_RXEQTRAINING !== 1'bz) && CH1_RXEQTRAINING; // rv 0 + assign CH1_RXPOLARITY_in = (CH1_RXPOLARITY !== 1'bz) && CH1_RXPOLARITY; // rv 0 + assign CH1_RXPRBSCNTSTOP_in = (CH1_RXPRBSCNTSTOP !== 1'bz) && CH1_RXPRBSCNTSTOP; // rv 0 + assign CH1_RXPRBSPTN_in[0] = (CH1_RXPRBSPTN[0] !== 1'bz) && CH1_RXPRBSPTN[0]; // rv 0 + assign CH1_RXPRBSPTN_in[1] = (CH1_RXPRBSPTN[1] !== 1'bz) && CH1_RXPRBSPTN[1]; // rv 0 + assign CH1_RXPRBSPTN_in[2] = (CH1_RXPRBSPTN[2] !== 1'bz) && CH1_RXPRBSPTN[2]; // rv 0 + assign CH1_RXPRBSPTN_in[3] = (CH1_RXPRBSPTN[3] !== 1'bz) && CH1_RXPRBSPTN[3]; // rv 0 + assign CH1_RXQPRBSEN_in = (CH1_RXQPRBSEN !== 1'bz) && CH1_RXQPRBSEN; // rv 0 + assign CH1_RXUSRCLK2_in = (CH1_RXUSRCLK2 !== 1'bz) && CH1_RXUSRCLK2; // rv 0 + assign CH1_RXUSRCLK_in = (CH1_RXUSRCLK !== 1'bz) && CH1_RXUSRCLK; // rv 0 + assign CH1_TXDATASTART_in = (CH1_TXDATASTART !== 1'bz) && CH1_TXDATASTART; // rv 0 + assign CH1_TXDATA_in[0] = (CH1_TXDATA[0] !== 1'bz) && CH1_TXDATA[0]; // rv 0 + assign CH1_TXDATA_in[100] = (CH1_TXDATA[100] !== 1'bz) && CH1_TXDATA[100]; // rv 0 + assign CH1_TXDATA_in[101] = (CH1_TXDATA[101] !== 1'bz) && CH1_TXDATA[101]; // rv 0 + assign CH1_TXDATA_in[102] = (CH1_TXDATA[102] !== 1'bz) && CH1_TXDATA[102]; // rv 0 + assign CH1_TXDATA_in[103] = (CH1_TXDATA[103] !== 1'bz) && CH1_TXDATA[103]; // rv 0 + assign CH1_TXDATA_in[104] = (CH1_TXDATA[104] !== 1'bz) && CH1_TXDATA[104]; // rv 0 + assign CH1_TXDATA_in[105] = (CH1_TXDATA[105] !== 1'bz) && CH1_TXDATA[105]; // rv 0 + assign CH1_TXDATA_in[106] = (CH1_TXDATA[106] !== 1'bz) && CH1_TXDATA[106]; // rv 0 + assign CH1_TXDATA_in[107] = (CH1_TXDATA[107] !== 1'bz) && CH1_TXDATA[107]; // rv 0 + assign CH1_TXDATA_in[108] = (CH1_TXDATA[108] !== 1'bz) && CH1_TXDATA[108]; // rv 0 + assign CH1_TXDATA_in[109] = (CH1_TXDATA[109] !== 1'bz) && CH1_TXDATA[109]; // rv 0 + assign CH1_TXDATA_in[10] = (CH1_TXDATA[10] !== 1'bz) && CH1_TXDATA[10]; // rv 0 + assign CH1_TXDATA_in[110] = (CH1_TXDATA[110] !== 1'bz) && CH1_TXDATA[110]; // rv 0 + assign CH1_TXDATA_in[111] = (CH1_TXDATA[111] !== 1'bz) && CH1_TXDATA[111]; // rv 0 + assign CH1_TXDATA_in[112] = (CH1_TXDATA[112] !== 1'bz) && CH1_TXDATA[112]; // rv 0 + assign CH1_TXDATA_in[113] = (CH1_TXDATA[113] !== 1'bz) && CH1_TXDATA[113]; // rv 0 + assign CH1_TXDATA_in[114] = (CH1_TXDATA[114] !== 1'bz) && CH1_TXDATA[114]; // rv 0 + assign CH1_TXDATA_in[115] = (CH1_TXDATA[115] !== 1'bz) && CH1_TXDATA[115]; // rv 0 + assign CH1_TXDATA_in[116] = (CH1_TXDATA[116] !== 1'bz) && CH1_TXDATA[116]; // rv 0 + assign CH1_TXDATA_in[117] = (CH1_TXDATA[117] !== 1'bz) && CH1_TXDATA[117]; // rv 0 + assign CH1_TXDATA_in[118] = (CH1_TXDATA[118] !== 1'bz) && CH1_TXDATA[118]; // rv 0 + assign CH1_TXDATA_in[119] = (CH1_TXDATA[119] !== 1'bz) && CH1_TXDATA[119]; // rv 0 + assign CH1_TXDATA_in[11] = (CH1_TXDATA[11] !== 1'bz) && CH1_TXDATA[11]; // rv 0 + assign CH1_TXDATA_in[120] = (CH1_TXDATA[120] !== 1'bz) && CH1_TXDATA[120]; // rv 0 + assign CH1_TXDATA_in[121] = (CH1_TXDATA[121] !== 1'bz) && CH1_TXDATA[121]; // rv 0 + assign CH1_TXDATA_in[122] = (CH1_TXDATA[122] !== 1'bz) && CH1_TXDATA[122]; // rv 0 + assign CH1_TXDATA_in[123] = (CH1_TXDATA[123] !== 1'bz) && CH1_TXDATA[123]; // rv 0 + assign CH1_TXDATA_in[124] = (CH1_TXDATA[124] !== 1'bz) && CH1_TXDATA[124]; // rv 0 + assign CH1_TXDATA_in[125] = (CH1_TXDATA[125] !== 1'bz) && CH1_TXDATA[125]; // rv 0 + assign CH1_TXDATA_in[126] = (CH1_TXDATA[126] !== 1'bz) && CH1_TXDATA[126]; // rv 0 + assign CH1_TXDATA_in[127] = (CH1_TXDATA[127] !== 1'bz) && CH1_TXDATA[127]; // rv 0 + assign CH1_TXDATA_in[128] = (CH1_TXDATA[128] !== 1'bz) && CH1_TXDATA[128]; // rv 0 + assign CH1_TXDATA_in[129] = (CH1_TXDATA[129] !== 1'bz) && CH1_TXDATA[129]; // rv 0 + assign CH1_TXDATA_in[12] = (CH1_TXDATA[12] !== 1'bz) && CH1_TXDATA[12]; // rv 0 + assign CH1_TXDATA_in[130] = (CH1_TXDATA[130] !== 1'bz) && CH1_TXDATA[130]; // rv 0 + assign CH1_TXDATA_in[131] = (CH1_TXDATA[131] !== 1'bz) && CH1_TXDATA[131]; // rv 0 + assign CH1_TXDATA_in[132] = (CH1_TXDATA[132] !== 1'bz) && CH1_TXDATA[132]; // rv 0 + assign CH1_TXDATA_in[133] = (CH1_TXDATA[133] !== 1'bz) && CH1_TXDATA[133]; // rv 0 + assign CH1_TXDATA_in[134] = (CH1_TXDATA[134] !== 1'bz) && CH1_TXDATA[134]; // rv 0 + assign CH1_TXDATA_in[135] = (CH1_TXDATA[135] !== 1'bz) && CH1_TXDATA[135]; // rv 0 + assign CH1_TXDATA_in[136] = (CH1_TXDATA[136] !== 1'bz) && CH1_TXDATA[136]; // rv 0 + assign CH1_TXDATA_in[137] = (CH1_TXDATA[137] !== 1'bz) && CH1_TXDATA[137]; // rv 0 + assign CH1_TXDATA_in[138] = (CH1_TXDATA[138] !== 1'bz) && CH1_TXDATA[138]; // rv 0 + assign CH1_TXDATA_in[139] = (CH1_TXDATA[139] !== 1'bz) && CH1_TXDATA[139]; // rv 0 + assign CH1_TXDATA_in[13] = (CH1_TXDATA[13] !== 1'bz) && CH1_TXDATA[13]; // rv 0 + assign CH1_TXDATA_in[140] = (CH1_TXDATA[140] !== 1'bz) && CH1_TXDATA[140]; // rv 0 + assign CH1_TXDATA_in[141] = (CH1_TXDATA[141] !== 1'bz) && CH1_TXDATA[141]; // rv 0 + assign CH1_TXDATA_in[142] = (CH1_TXDATA[142] !== 1'bz) && CH1_TXDATA[142]; // rv 0 + assign CH1_TXDATA_in[143] = (CH1_TXDATA[143] !== 1'bz) && CH1_TXDATA[143]; // rv 0 + assign CH1_TXDATA_in[144] = (CH1_TXDATA[144] !== 1'bz) && CH1_TXDATA[144]; // rv 0 + assign CH1_TXDATA_in[145] = (CH1_TXDATA[145] !== 1'bz) && CH1_TXDATA[145]; // rv 0 + assign CH1_TXDATA_in[146] = (CH1_TXDATA[146] !== 1'bz) && CH1_TXDATA[146]; // rv 0 + assign CH1_TXDATA_in[147] = (CH1_TXDATA[147] !== 1'bz) && CH1_TXDATA[147]; // rv 0 + assign CH1_TXDATA_in[148] = (CH1_TXDATA[148] !== 1'bz) && CH1_TXDATA[148]; // rv 0 + assign CH1_TXDATA_in[149] = (CH1_TXDATA[149] !== 1'bz) && CH1_TXDATA[149]; // rv 0 + assign CH1_TXDATA_in[14] = (CH1_TXDATA[14] !== 1'bz) && CH1_TXDATA[14]; // rv 0 + assign CH1_TXDATA_in[150] = (CH1_TXDATA[150] !== 1'bz) && CH1_TXDATA[150]; // rv 0 + assign CH1_TXDATA_in[151] = (CH1_TXDATA[151] !== 1'bz) && CH1_TXDATA[151]; // rv 0 + assign CH1_TXDATA_in[152] = (CH1_TXDATA[152] !== 1'bz) && CH1_TXDATA[152]; // rv 0 + assign CH1_TXDATA_in[153] = (CH1_TXDATA[153] !== 1'bz) && CH1_TXDATA[153]; // rv 0 + assign CH1_TXDATA_in[154] = (CH1_TXDATA[154] !== 1'bz) && CH1_TXDATA[154]; // rv 0 + assign CH1_TXDATA_in[155] = (CH1_TXDATA[155] !== 1'bz) && CH1_TXDATA[155]; // rv 0 + assign CH1_TXDATA_in[156] = (CH1_TXDATA[156] !== 1'bz) && CH1_TXDATA[156]; // rv 0 + assign CH1_TXDATA_in[157] = (CH1_TXDATA[157] !== 1'bz) && CH1_TXDATA[157]; // rv 0 + assign CH1_TXDATA_in[158] = (CH1_TXDATA[158] !== 1'bz) && CH1_TXDATA[158]; // rv 0 + assign CH1_TXDATA_in[159] = (CH1_TXDATA[159] !== 1'bz) && CH1_TXDATA[159]; // rv 0 + assign CH1_TXDATA_in[15] = (CH1_TXDATA[15] !== 1'bz) && CH1_TXDATA[15]; // rv 0 + assign CH1_TXDATA_in[160] = (CH1_TXDATA[160] !== 1'bz) && CH1_TXDATA[160]; // rv 0 + assign CH1_TXDATA_in[161] = (CH1_TXDATA[161] !== 1'bz) && CH1_TXDATA[161]; // rv 0 + assign CH1_TXDATA_in[162] = (CH1_TXDATA[162] !== 1'bz) && CH1_TXDATA[162]; // rv 0 + assign CH1_TXDATA_in[163] = (CH1_TXDATA[163] !== 1'bz) && CH1_TXDATA[163]; // rv 0 + assign CH1_TXDATA_in[164] = (CH1_TXDATA[164] !== 1'bz) && CH1_TXDATA[164]; // rv 0 + assign CH1_TXDATA_in[165] = (CH1_TXDATA[165] !== 1'bz) && CH1_TXDATA[165]; // rv 0 + assign CH1_TXDATA_in[166] = (CH1_TXDATA[166] !== 1'bz) && CH1_TXDATA[166]; // rv 0 + assign CH1_TXDATA_in[167] = (CH1_TXDATA[167] !== 1'bz) && CH1_TXDATA[167]; // rv 0 + assign CH1_TXDATA_in[168] = (CH1_TXDATA[168] !== 1'bz) && CH1_TXDATA[168]; // rv 0 + assign CH1_TXDATA_in[169] = (CH1_TXDATA[169] !== 1'bz) && CH1_TXDATA[169]; // rv 0 + assign CH1_TXDATA_in[16] = (CH1_TXDATA[16] !== 1'bz) && CH1_TXDATA[16]; // rv 0 + assign CH1_TXDATA_in[170] = (CH1_TXDATA[170] !== 1'bz) && CH1_TXDATA[170]; // rv 0 + assign CH1_TXDATA_in[171] = (CH1_TXDATA[171] !== 1'bz) && CH1_TXDATA[171]; // rv 0 + assign CH1_TXDATA_in[172] = (CH1_TXDATA[172] !== 1'bz) && CH1_TXDATA[172]; // rv 0 + assign CH1_TXDATA_in[173] = (CH1_TXDATA[173] !== 1'bz) && CH1_TXDATA[173]; // rv 0 + assign CH1_TXDATA_in[174] = (CH1_TXDATA[174] !== 1'bz) && CH1_TXDATA[174]; // rv 0 + assign CH1_TXDATA_in[175] = (CH1_TXDATA[175] !== 1'bz) && CH1_TXDATA[175]; // rv 0 + assign CH1_TXDATA_in[176] = (CH1_TXDATA[176] !== 1'bz) && CH1_TXDATA[176]; // rv 0 + assign CH1_TXDATA_in[177] = (CH1_TXDATA[177] !== 1'bz) && CH1_TXDATA[177]; // rv 0 + assign CH1_TXDATA_in[178] = (CH1_TXDATA[178] !== 1'bz) && CH1_TXDATA[178]; // rv 0 + assign CH1_TXDATA_in[179] = (CH1_TXDATA[179] !== 1'bz) && CH1_TXDATA[179]; // rv 0 + assign CH1_TXDATA_in[17] = (CH1_TXDATA[17] !== 1'bz) && CH1_TXDATA[17]; // rv 0 + assign CH1_TXDATA_in[180] = (CH1_TXDATA[180] !== 1'bz) && CH1_TXDATA[180]; // rv 0 + assign CH1_TXDATA_in[181] = (CH1_TXDATA[181] !== 1'bz) && CH1_TXDATA[181]; // rv 0 + assign CH1_TXDATA_in[182] = (CH1_TXDATA[182] !== 1'bz) && CH1_TXDATA[182]; // rv 0 + assign CH1_TXDATA_in[183] = (CH1_TXDATA[183] !== 1'bz) && CH1_TXDATA[183]; // rv 0 + assign CH1_TXDATA_in[184] = (CH1_TXDATA[184] !== 1'bz) && CH1_TXDATA[184]; // rv 0 + assign CH1_TXDATA_in[185] = (CH1_TXDATA[185] !== 1'bz) && CH1_TXDATA[185]; // rv 0 + assign CH1_TXDATA_in[186] = (CH1_TXDATA[186] !== 1'bz) && CH1_TXDATA[186]; // rv 0 + assign CH1_TXDATA_in[187] = (CH1_TXDATA[187] !== 1'bz) && CH1_TXDATA[187]; // rv 0 + assign CH1_TXDATA_in[188] = (CH1_TXDATA[188] !== 1'bz) && CH1_TXDATA[188]; // rv 0 + assign CH1_TXDATA_in[189] = (CH1_TXDATA[189] !== 1'bz) && CH1_TXDATA[189]; // rv 0 + assign CH1_TXDATA_in[18] = (CH1_TXDATA[18] !== 1'bz) && CH1_TXDATA[18]; // rv 0 + assign CH1_TXDATA_in[190] = (CH1_TXDATA[190] !== 1'bz) && CH1_TXDATA[190]; // rv 0 + assign CH1_TXDATA_in[191] = (CH1_TXDATA[191] !== 1'bz) && CH1_TXDATA[191]; // rv 0 + assign CH1_TXDATA_in[192] = (CH1_TXDATA[192] !== 1'bz) && CH1_TXDATA[192]; // rv 0 + assign CH1_TXDATA_in[193] = (CH1_TXDATA[193] !== 1'bz) && CH1_TXDATA[193]; // rv 0 + assign CH1_TXDATA_in[194] = (CH1_TXDATA[194] !== 1'bz) && CH1_TXDATA[194]; // rv 0 + assign CH1_TXDATA_in[195] = (CH1_TXDATA[195] !== 1'bz) && CH1_TXDATA[195]; // rv 0 + assign CH1_TXDATA_in[196] = (CH1_TXDATA[196] !== 1'bz) && CH1_TXDATA[196]; // rv 0 + assign CH1_TXDATA_in[197] = (CH1_TXDATA[197] !== 1'bz) && CH1_TXDATA[197]; // rv 0 + assign CH1_TXDATA_in[198] = (CH1_TXDATA[198] !== 1'bz) && CH1_TXDATA[198]; // rv 0 + assign CH1_TXDATA_in[199] = (CH1_TXDATA[199] !== 1'bz) && CH1_TXDATA[199]; // rv 0 + assign CH1_TXDATA_in[19] = (CH1_TXDATA[19] !== 1'bz) && CH1_TXDATA[19]; // rv 0 + assign CH1_TXDATA_in[1] = (CH1_TXDATA[1] !== 1'bz) && CH1_TXDATA[1]; // rv 0 + assign CH1_TXDATA_in[200] = (CH1_TXDATA[200] !== 1'bz) && CH1_TXDATA[200]; // rv 0 + assign CH1_TXDATA_in[201] = (CH1_TXDATA[201] !== 1'bz) && CH1_TXDATA[201]; // rv 0 + assign CH1_TXDATA_in[202] = (CH1_TXDATA[202] !== 1'bz) && CH1_TXDATA[202]; // rv 0 + assign CH1_TXDATA_in[203] = (CH1_TXDATA[203] !== 1'bz) && CH1_TXDATA[203]; // rv 0 + assign CH1_TXDATA_in[204] = (CH1_TXDATA[204] !== 1'bz) && CH1_TXDATA[204]; // rv 0 + assign CH1_TXDATA_in[205] = (CH1_TXDATA[205] !== 1'bz) && CH1_TXDATA[205]; // rv 0 + assign CH1_TXDATA_in[206] = (CH1_TXDATA[206] !== 1'bz) && CH1_TXDATA[206]; // rv 0 + assign CH1_TXDATA_in[207] = (CH1_TXDATA[207] !== 1'bz) && CH1_TXDATA[207]; // rv 0 + assign CH1_TXDATA_in[208] = (CH1_TXDATA[208] !== 1'bz) && CH1_TXDATA[208]; // rv 0 + assign CH1_TXDATA_in[209] = (CH1_TXDATA[209] !== 1'bz) && CH1_TXDATA[209]; // rv 0 + assign CH1_TXDATA_in[20] = (CH1_TXDATA[20] !== 1'bz) && CH1_TXDATA[20]; // rv 0 + assign CH1_TXDATA_in[210] = (CH1_TXDATA[210] !== 1'bz) && CH1_TXDATA[210]; // rv 0 + assign CH1_TXDATA_in[211] = (CH1_TXDATA[211] !== 1'bz) && CH1_TXDATA[211]; // rv 0 + assign CH1_TXDATA_in[212] = (CH1_TXDATA[212] !== 1'bz) && CH1_TXDATA[212]; // rv 0 + assign CH1_TXDATA_in[213] = (CH1_TXDATA[213] !== 1'bz) && CH1_TXDATA[213]; // rv 0 + assign CH1_TXDATA_in[214] = (CH1_TXDATA[214] !== 1'bz) && CH1_TXDATA[214]; // rv 0 + assign CH1_TXDATA_in[215] = (CH1_TXDATA[215] !== 1'bz) && CH1_TXDATA[215]; // rv 0 + assign CH1_TXDATA_in[216] = (CH1_TXDATA[216] !== 1'bz) && CH1_TXDATA[216]; // rv 0 + assign CH1_TXDATA_in[217] = (CH1_TXDATA[217] !== 1'bz) && CH1_TXDATA[217]; // rv 0 + assign CH1_TXDATA_in[218] = (CH1_TXDATA[218] !== 1'bz) && CH1_TXDATA[218]; // rv 0 + assign CH1_TXDATA_in[219] = (CH1_TXDATA[219] !== 1'bz) && CH1_TXDATA[219]; // rv 0 + assign CH1_TXDATA_in[21] = (CH1_TXDATA[21] !== 1'bz) && CH1_TXDATA[21]; // rv 0 + assign CH1_TXDATA_in[220] = (CH1_TXDATA[220] !== 1'bz) && CH1_TXDATA[220]; // rv 0 + assign CH1_TXDATA_in[221] = (CH1_TXDATA[221] !== 1'bz) && CH1_TXDATA[221]; // rv 0 + assign CH1_TXDATA_in[222] = (CH1_TXDATA[222] !== 1'bz) && CH1_TXDATA[222]; // rv 0 + assign CH1_TXDATA_in[223] = (CH1_TXDATA[223] !== 1'bz) && CH1_TXDATA[223]; // rv 0 + assign CH1_TXDATA_in[224] = (CH1_TXDATA[224] !== 1'bz) && CH1_TXDATA[224]; // rv 0 + assign CH1_TXDATA_in[225] = (CH1_TXDATA[225] !== 1'bz) && CH1_TXDATA[225]; // rv 0 + assign CH1_TXDATA_in[226] = (CH1_TXDATA[226] !== 1'bz) && CH1_TXDATA[226]; // rv 0 + assign CH1_TXDATA_in[227] = (CH1_TXDATA[227] !== 1'bz) && CH1_TXDATA[227]; // rv 0 + assign CH1_TXDATA_in[228] = (CH1_TXDATA[228] !== 1'bz) && CH1_TXDATA[228]; // rv 0 + assign CH1_TXDATA_in[229] = (CH1_TXDATA[229] !== 1'bz) && CH1_TXDATA[229]; // rv 0 + assign CH1_TXDATA_in[22] = (CH1_TXDATA[22] !== 1'bz) && CH1_TXDATA[22]; // rv 0 + assign CH1_TXDATA_in[230] = (CH1_TXDATA[230] !== 1'bz) && CH1_TXDATA[230]; // rv 0 + assign CH1_TXDATA_in[231] = (CH1_TXDATA[231] !== 1'bz) && CH1_TXDATA[231]; // rv 0 + assign CH1_TXDATA_in[232] = (CH1_TXDATA[232] !== 1'bz) && CH1_TXDATA[232]; // rv 0 + assign CH1_TXDATA_in[233] = (CH1_TXDATA[233] !== 1'bz) && CH1_TXDATA[233]; // rv 0 + assign CH1_TXDATA_in[234] = (CH1_TXDATA[234] !== 1'bz) && CH1_TXDATA[234]; // rv 0 + assign CH1_TXDATA_in[235] = (CH1_TXDATA[235] !== 1'bz) && CH1_TXDATA[235]; // rv 0 + assign CH1_TXDATA_in[236] = (CH1_TXDATA[236] !== 1'bz) && CH1_TXDATA[236]; // rv 0 + assign CH1_TXDATA_in[237] = (CH1_TXDATA[237] !== 1'bz) && CH1_TXDATA[237]; // rv 0 + assign CH1_TXDATA_in[238] = (CH1_TXDATA[238] !== 1'bz) && CH1_TXDATA[238]; // rv 0 + assign CH1_TXDATA_in[239] = (CH1_TXDATA[239] !== 1'bz) && CH1_TXDATA[239]; // rv 0 + assign CH1_TXDATA_in[23] = (CH1_TXDATA[23] !== 1'bz) && CH1_TXDATA[23]; // rv 0 + assign CH1_TXDATA_in[240] = (CH1_TXDATA[240] !== 1'bz) && CH1_TXDATA[240]; // rv 0 + assign CH1_TXDATA_in[241] = (CH1_TXDATA[241] !== 1'bz) && CH1_TXDATA[241]; // rv 0 + assign CH1_TXDATA_in[242] = (CH1_TXDATA[242] !== 1'bz) && CH1_TXDATA[242]; // rv 0 + assign CH1_TXDATA_in[243] = (CH1_TXDATA[243] !== 1'bz) && CH1_TXDATA[243]; // rv 0 + assign CH1_TXDATA_in[244] = (CH1_TXDATA[244] !== 1'bz) && CH1_TXDATA[244]; // rv 0 + assign CH1_TXDATA_in[245] = (CH1_TXDATA[245] !== 1'bz) && CH1_TXDATA[245]; // rv 0 + assign CH1_TXDATA_in[246] = (CH1_TXDATA[246] !== 1'bz) && CH1_TXDATA[246]; // rv 0 + assign CH1_TXDATA_in[247] = (CH1_TXDATA[247] !== 1'bz) && CH1_TXDATA[247]; // rv 0 + assign CH1_TXDATA_in[248] = (CH1_TXDATA[248] !== 1'bz) && CH1_TXDATA[248]; // rv 0 + assign CH1_TXDATA_in[249] = (CH1_TXDATA[249] !== 1'bz) && CH1_TXDATA[249]; // rv 0 + assign CH1_TXDATA_in[24] = (CH1_TXDATA[24] !== 1'bz) && CH1_TXDATA[24]; // rv 0 + assign CH1_TXDATA_in[250] = (CH1_TXDATA[250] !== 1'bz) && CH1_TXDATA[250]; // rv 0 + assign CH1_TXDATA_in[251] = (CH1_TXDATA[251] !== 1'bz) && CH1_TXDATA[251]; // rv 0 + assign CH1_TXDATA_in[252] = (CH1_TXDATA[252] !== 1'bz) && CH1_TXDATA[252]; // rv 0 + assign CH1_TXDATA_in[253] = (CH1_TXDATA[253] !== 1'bz) && CH1_TXDATA[253]; // rv 0 + assign CH1_TXDATA_in[254] = (CH1_TXDATA[254] !== 1'bz) && CH1_TXDATA[254]; // rv 0 + assign CH1_TXDATA_in[255] = (CH1_TXDATA[255] !== 1'bz) && CH1_TXDATA[255]; // rv 0 + assign CH1_TXDATA_in[25] = (CH1_TXDATA[25] !== 1'bz) && CH1_TXDATA[25]; // rv 0 + assign CH1_TXDATA_in[26] = (CH1_TXDATA[26] !== 1'bz) && CH1_TXDATA[26]; // rv 0 + assign CH1_TXDATA_in[27] = (CH1_TXDATA[27] !== 1'bz) && CH1_TXDATA[27]; // rv 0 + assign CH1_TXDATA_in[28] = (CH1_TXDATA[28] !== 1'bz) && CH1_TXDATA[28]; // rv 0 + assign CH1_TXDATA_in[29] = (CH1_TXDATA[29] !== 1'bz) && CH1_TXDATA[29]; // rv 0 + assign CH1_TXDATA_in[2] = (CH1_TXDATA[2] !== 1'bz) && CH1_TXDATA[2]; // rv 0 + assign CH1_TXDATA_in[30] = (CH1_TXDATA[30] !== 1'bz) && CH1_TXDATA[30]; // rv 0 + assign CH1_TXDATA_in[31] = (CH1_TXDATA[31] !== 1'bz) && CH1_TXDATA[31]; // rv 0 + assign CH1_TXDATA_in[32] = (CH1_TXDATA[32] !== 1'bz) && CH1_TXDATA[32]; // rv 0 + assign CH1_TXDATA_in[33] = (CH1_TXDATA[33] !== 1'bz) && CH1_TXDATA[33]; // rv 0 + assign CH1_TXDATA_in[34] = (CH1_TXDATA[34] !== 1'bz) && CH1_TXDATA[34]; // rv 0 + assign CH1_TXDATA_in[35] = (CH1_TXDATA[35] !== 1'bz) && CH1_TXDATA[35]; // rv 0 + assign CH1_TXDATA_in[36] = (CH1_TXDATA[36] !== 1'bz) && CH1_TXDATA[36]; // rv 0 + assign CH1_TXDATA_in[37] = (CH1_TXDATA[37] !== 1'bz) && CH1_TXDATA[37]; // rv 0 + assign CH1_TXDATA_in[38] = (CH1_TXDATA[38] !== 1'bz) && CH1_TXDATA[38]; // rv 0 + assign CH1_TXDATA_in[39] = (CH1_TXDATA[39] !== 1'bz) && CH1_TXDATA[39]; // rv 0 + assign CH1_TXDATA_in[3] = (CH1_TXDATA[3] !== 1'bz) && CH1_TXDATA[3]; // rv 0 + assign CH1_TXDATA_in[40] = (CH1_TXDATA[40] !== 1'bz) && CH1_TXDATA[40]; // rv 0 + assign CH1_TXDATA_in[41] = (CH1_TXDATA[41] !== 1'bz) && CH1_TXDATA[41]; // rv 0 + assign CH1_TXDATA_in[42] = (CH1_TXDATA[42] !== 1'bz) && CH1_TXDATA[42]; // rv 0 + assign CH1_TXDATA_in[43] = (CH1_TXDATA[43] !== 1'bz) && CH1_TXDATA[43]; // rv 0 + assign CH1_TXDATA_in[44] = (CH1_TXDATA[44] !== 1'bz) && CH1_TXDATA[44]; // rv 0 + assign CH1_TXDATA_in[45] = (CH1_TXDATA[45] !== 1'bz) && CH1_TXDATA[45]; // rv 0 + assign CH1_TXDATA_in[46] = (CH1_TXDATA[46] !== 1'bz) && CH1_TXDATA[46]; // rv 0 + assign CH1_TXDATA_in[47] = (CH1_TXDATA[47] !== 1'bz) && CH1_TXDATA[47]; // rv 0 + assign CH1_TXDATA_in[48] = (CH1_TXDATA[48] !== 1'bz) && CH1_TXDATA[48]; // rv 0 + assign CH1_TXDATA_in[49] = (CH1_TXDATA[49] !== 1'bz) && CH1_TXDATA[49]; // rv 0 + assign CH1_TXDATA_in[4] = (CH1_TXDATA[4] !== 1'bz) && CH1_TXDATA[4]; // rv 0 + assign CH1_TXDATA_in[50] = (CH1_TXDATA[50] !== 1'bz) && CH1_TXDATA[50]; // rv 0 + assign CH1_TXDATA_in[51] = (CH1_TXDATA[51] !== 1'bz) && CH1_TXDATA[51]; // rv 0 + assign CH1_TXDATA_in[52] = (CH1_TXDATA[52] !== 1'bz) && CH1_TXDATA[52]; // rv 0 + assign CH1_TXDATA_in[53] = (CH1_TXDATA[53] !== 1'bz) && CH1_TXDATA[53]; // rv 0 + assign CH1_TXDATA_in[54] = (CH1_TXDATA[54] !== 1'bz) && CH1_TXDATA[54]; // rv 0 + assign CH1_TXDATA_in[55] = (CH1_TXDATA[55] !== 1'bz) && CH1_TXDATA[55]; // rv 0 + assign CH1_TXDATA_in[56] = (CH1_TXDATA[56] !== 1'bz) && CH1_TXDATA[56]; // rv 0 + assign CH1_TXDATA_in[57] = (CH1_TXDATA[57] !== 1'bz) && CH1_TXDATA[57]; // rv 0 + assign CH1_TXDATA_in[58] = (CH1_TXDATA[58] !== 1'bz) && CH1_TXDATA[58]; // rv 0 + assign CH1_TXDATA_in[59] = (CH1_TXDATA[59] !== 1'bz) && CH1_TXDATA[59]; // rv 0 + assign CH1_TXDATA_in[5] = (CH1_TXDATA[5] !== 1'bz) && CH1_TXDATA[5]; // rv 0 + assign CH1_TXDATA_in[60] = (CH1_TXDATA[60] !== 1'bz) && CH1_TXDATA[60]; // rv 0 + assign CH1_TXDATA_in[61] = (CH1_TXDATA[61] !== 1'bz) && CH1_TXDATA[61]; // rv 0 + assign CH1_TXDATA_in[62] = (CH1_TXDATA[62] !== 1'bz) && CH1_TXDATA[62]; // rv 0 + assign CH1_TXDATA_in[63] = (CH1_TXDATA[63] !== 1'bz) && CH1_TXDATA[63]; // rv 0 + assign CH1_TXDATA_in[64] = (CH1_TXDATA[64] !== 1'bz) && CH1_TXDATA[64]; // rv 0 + assign CH1_TXDATA_in[65] = (CH1_TXDATA[65] !== 1'bz) && CH1_TXDATA[65]; // rv 0 + assign CH1_TXDATA_in[66] = (CH1_TXDATA[66] !== 1'bz) && CH1_TXDATA[66]; // rv 0 + assign CH1_TXDATA_in[67] = (CH1_TXDATA[67] !== 1'bz) && CH1_TXDATA[67]; // rv 0 + assign CH1_TXDATA_in[68] = (CH1_TXDATA[68] !== 1'bz) && CH1_TXDATA[68]; // rv 0 + assign CH1_TXDATA_in[69] = (CH1_TXDATA[69] !== 1'bz) && CH1_TXDATA[69]; // rv 0 + assign CH1_TXDATA_in[6] = (CH1_TXDATA[6] !== 1'bz) && CH1_TXDATA[6]; // rv 0 + assign CH1_TXDATA_in[70] = (CH1_TXDATA[70] !== 1'bz) && CH1_TXDATA[70]; // rv 0 + assign CH1_TXDATA_in[71] = (CH1_TXDATA[71] !== 1'bz) && CH1_TXDATA[71]; // rv 0 + assign CH1_TXDATA_in[72] = (CH1_TXDATA[72] !== 1'bz) && CH1_TXDATA[72]; // rv 0 + assign CH1_TXDATA_in[73] = (CH1_TXDATA[73] !== 1'bz) && CH1_TXDATA[73]; // rv 0 + assign CH1_TXDATA_in[74] = (CH1_TXDATA[74] !== 1'bz) && CH1_TXDATA[74]; // rv 0 + assign CH1_TXDATA_in[75] = (CH1_TXDATA[75] !== 1'bz) && CH1_TXDATA[75]; // rv 0 + assign CH1_TXDATA_in[76] = (CH1_TXDATA[76] !== 1'bz) && CH1_TXDATA[76]; // rv 0 + assign CH1_TXDATA_in[77] = (CH1_TXDATA[77] !== 1'bz) && CH1_TXDATA[77]; // rv 0 + assign CH1_TXDATA_in[78] = (CH1_TXDATA[78] !== 1'bz) && CH1_TXDATA[78]; // rv 0 + assign CH1_TXDATA_in[79] = (CH1_TXDATA[79] !== 1'bz) && CH1_TXDATA[79]; // rv 0 + assign CH1_TXDATA_in[7] = (CH1_TXDATA[7] !== 1'bz) && CH1_TXDATA[7]; // rv 0 + assign CH1_TXDATA_in[80] = (CH1_TXDATA[80] !== 1'bz) && CH1_TXDATA[80]; // rv 0 + assign CH1_TXDATA_in[81] = (CH1_TXDATA[81] !== 1'bz) && CH1_TXDATA[81]; // rv 0 + assign CH1_TXDATA_in[82] = (CH1_TXDATA[82] !== 1'bz) && CH1_TXDATA[82]; // rv 0 + assign CH1_TXDATA_in[83] = (CH1_TXDATA[83] !== 1'bz) && CH1_TXDATA[83]; // rv 0 + assign CH1_TXDATA_in[84] = (CH1_TXDATA[84] !== 1'bz) && CH1_TXDATA[84]; // rv 0 + assign CH1_TXDATA_in[85] = (CH1_TXDATA[85] !== 1'bz) && CH1_TXDATA[85]; // rv 0 + assign CH1_TXDATA_in[86] = (CH1_TXDATA[86] !== 1'bz) && CH1_TXDATA[86]; // rv 0 + assign CH1_TXDATA_in[87] = (CH1_TXDATA[87] !== 1'bz) && CH1_TXDATA[87]; // rv 0 + assign CH1_TXDATA_in[88] = (CH1_TXDATA[88] !== 1'bz) && CH1_TXDATA[88]; // rv 0 + assign CH1_TXDATA_in[89] = (CH1_TXDATA[89] !== 1'bz) && CH1_TXDATA[89]; // rv 0 + assign CH1_TXDATA_in[8] = (CH1_TXDATA[8] !== 1'bz) && CH1_TXDATA[8]; // rv 0 + assign CH1_TXDATA_in[90] = (CH1_TXDATA[90] !== 1'bz) && CH1_TXDATA[90]; // rv 0 + assign CH1_TXDATA_in[91] = (CH1_TXDATA[91] !== 1'bz) && CH1_TXDATA[91]; // rv 0 + assign CH1_TXDATA_in[92] = (CH1_TXDATA[92] !== 1'bz) && CH1_TXDATA[92]; // rv 0 + assign CH1_TXDATA_in[93] = (CH1_TXDATA[93] !== 1'bz) && CH1_TXDATA[93]; // rv 0 + assign CH1_TXDATA_in[94] = (CH1_TXDATA[94] !== 1'bz) && CH1_TXDATA[94]; // rv 0 + assign CH1_TXDATA_in[95] = (CH1_TXDATA[95] !== 1'bz) && CH1_TXDATA[95]; // rv 0 + assign CH1_TXDATA_in[96] = (CH1_TXDATA[96] !== 1'bz) && CH1_TXDATA[96]; // rv 0 + assign CH1_TXDATA_in[97] = (CH1_TXDATA[97] !== 1'bz) && CH1_TXDATA[97]; // rv 0 + assign CH1_TXDATA_in[98] = (CH1_TXDATA[98] !== 1'bz) && CH1_TXDATA[98]; // rv 0 + assign CH1_TXDATA_in[99] = (CH1_TXDATA[99] !== 1'bz) && CH1_TXDATA[99]; // rv 0 + assign CH1_TXDATA_in[9] = (CH1_TXDATA[9] !== 1'bz) && CH1_TXDATA[9]; // rv 0 + assign CH1_TXINHIBIT_in = (CH1_TXINHIBIT !== 1'bz) && CH1_TXINHIBIT; // rv 0 + assign CH1_TXPOLARITY_in = (CH1_TXPOLARITY !== 1'bz) && CH1_TXPOLARITY; // rv 0 + assign CH1_TXPRBSINERR_in = (CH1_TXPRBSINERR !== 1'bz) && CH1_TXPRBSINERR; // rv 0 + assign CH1_TXPRBSPTN_in[0] = (CH1_TXPRBSPTN[0] !== 1'bz) && CH1_TXPRBSPTN[0]; // rv 0 + assign CH1_TXPRBSPTN_in[1] = (CH1_TXPRBSPTN[1] !== 1'bz) && CH1_TXPRBSPTN[1]; // rv 0 + assign CH1_TXPRBSPTN_in[2] = (CH1_TXPRBSPTN[2] !== 1'bz) && CH1_TXPRBSPTN[2]; // rv 0 + assign CH1_TXPRBSPTN_in[3] = (CH1_TXPRBSPTN[3] !== 1'bz) && CH1_TXPRBSPTN[3]; // rv 0 + assign CH1_TXQPRBSEN_in = (CH1_TXQPRBSEN !== 1'bz) && CH1_TXQPRBSEN; // rv 0 + assign CH1_TXUSRCLK2_in = (CH1_TXUSRCLK2 !== 1'bz) && CH1_TXUSRCLK2; // rv 0 + assign CH1_TXUSRCLK_in = (CH1_TXUSRCLK !== 1'bz) && CH1_TXUSRCLK; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR[10]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign FECCTRLRX0BITSLIPFS_in = (FECCTRLRX0BITSLIPFS !== 1'bz) && FECCTRLRX0BITSLIPFS; // rv 0 + assign FECCTRLRX1BITSLIPFS_in = (FECCTRLRX1BITSLIPFS !== 1'bz) && FECCTRLRX1BITSLIPFS; // rv 0 +`endif + + assign BGBYPASSB_in = BGBYPASSB; + assign BGMONITORENB_in = BGMONITORENB; + assign BGPDB_in = BGPDB; + assign BGRCALOVRDENB_in = (BGRCALOVRDENB === 1'bz) || BGRCALOVRDENB; // rv 1 + assign BGRCALOVRD_in = BGRCALOVRD; + assign CH0_AXISRST_in = (CH0_AXISRST !== 1'bz) && CH0_AXISRST; // rv 0 + assign CH0_CFGRESET_in = (CH0_CFGRESET !== 1'bz) && CH0_CFGRESET; // rv 0 + assign CH0_DMONFIFORESET_in = (CH0_DMONFIFORESET !== 1'bz) && CH0_DMONFIFORESET; // rv 0 + assign CH0_DMONITORCLK_in = (CH0_DMONITORCLK !== 1'bz) && CH0_DMONITORCLK; // rv 0 + assign CH0_GTMRXN_in = CH0_GTMRXN; + assign CH0_GTMRXP_in = CH0_GTMRXP; + assign CH0_GTRXRESET_in = (CH0_GTRXRESET !== 1'bz) && CH0_GTRXRESET; // rv 0 + assign CH0_GTTXRESET_in = (CH0_GTTXRESET !== 1'bz) && CH0_GTTXRESET; // rv 0 + assign CH0_LOOPBACK_in[0] = (CH0_LOOPBACK[0] !== 1'bz) && CH0_LOOPBACK[0]; // rv 0 + assign CH0_LOOPBACK_in[1] = (CH0_LOOPBACK[1] !== 1'bz) && CH0_LOOPBACK[1]; // rv 0 + assign CH0_LOOPBACK_in[2] = (CH0_LOOPBACK[2] !== 1'bz) && CH0_LOOPBACK[2]; // rv 0 + assign CH0_PCSRSVDIN_in[0] = (CH0_PCSRSVDIN[0] !== 1'bz) && CH0_PCSRSVDIN[0]; // rv 0 + assign CH0_PCSRSVDIN_in[10] = (CH0_PCSRSVDIN[10] !== 1'bz) && CH0_PCSRSVDIN[10]; // rv 0 + assign CH0_PCSRSVDIN_in[11] = (CH0_PCSRSVDIN[11] !== 1'bz) && CH0_PCSRSVDIN[11]; // rv 0 + assign CH0_PCSRSVDIN_in[12] = (CH0_PCSRSVDIN[12] !== 1'bz) && CH0_PCSRSVDIN[12]; // rv 0 + assign CH0_PCSRSVDIN_in[13] = (CH0_PCSRSVDIN[13] !== 1'bz) && CH0_PCSRSVDIN[13]; // rv 0 + assign CH0_PCSRSVDIN_in[14] = (CH0_PCSRSVDIN[14] !== 1'bz) && CH0_PCSRSVDIN[14]; // rv 0 + assign CH0_PCSRSVDIN_in[15] = (CH0_PCSRSVDIN[15] !== 1'bz) && CH0_PCSRSVDIN[15]; // rv 0 + assign CH0_PCSRSVDIN_in[1] = (CH0_PCSRSVDIN[1] !== 1'bz) && CH0_PCSRSVDIN[1]; // rv 0 + assign CH0_PCSRSVDIN_in[2] = (CH0_PCSRSVDIN[2] !== 1'bz) && CH0_PCSRSVDIN[2]; // rv 0 + assign CH0_PCSRSVDIN_in[3] = (CH0_PCSRSVDIN[3] !== 1'bz) && CH0_PCSRSVDIN[3]; // rv 0 + assign CH0_PCSRSVDIN_in[4] = (CH0_PCSRSVDIN[4] !== 1'bz) && CH0_PCSRSVDIN[4]; // rv 0 + assign CH0_PCSRSVDIN_in[5] = (CH0_PCSRSVDIN[5] !== 1'bz) && CH0_PCSRSVDIN[5]; // rv 0 + assign CH0_PCSRSVDIN_in[6] = (CH0_PCSRSVDIN[6] !== 1'bz) && CH0_PCSRSVDIN[6]; // rv 0 + assign CH0_PCSRSVDIN_in[7] = (CH0_PCSRSVDIN[7] !== 1'bz) && CH0_PCSRSVDIN[7]; // rv 0 + assign CH0_PCSRSVDIN_in[8] = (CH0_PCSRSVDIN[8] !== 1'bz) && CH0_PCSRSVDIN[8]; // rv 0 + assign CH0_PCSRSVDIN_in[9] = (CH0_PCSRSVDIN[9] !== 1'bz) && CH0_PCSRSVDIN[9]; // rv 0 + assign CH0_PMARSVDIN_in[0] = (CH0_PMARSVDIN[0] === 1'bz) || CH0_PMARSVDIN[0]; // rv 1 + assign CH0_PMARSVDIN_in[10] = (CH0_PMARSVDIN[10] !== 1'bz) && CH0_PMARSVDIN[10]; // rv 0 + assign CH0_PMARSVDIN_in[11] = (CH0_PMARSVDIN[11] !== 1'bz) && CH0_PMARSVDIN[11]; // rv 0 + assign CH0_PMARSVDIN_in[12] = (CH0_PMARSVDIN[12] !== 1'bz) && CH0_PMARSVDIN[12]; // rv 0 + assign CH0_PMARSVDIN_in[13] = (CH0_PMARSVDIN[13] !== 1'bz) && CH0_PMARSVDIN[13]; // rv 0 + assign CH0_PMARSVDIN_in[14] = (CH0_PMARSVDIN[14] !== 1'bz) && CH0_PMARSVDIN[14]; // rv 0 + assign CH0_PMARSVDIN_in[15] = (CH0_PMARSVDIN[15] !== 1'bz) && CH0_PMARSVDIN[15]; // rv 0 + assign CH0_PMARSVDIN_in[1] = (CH0_PMARSVDIN[1] !== 1'bz) && CH0_PMARSVDIN[1]; // rv 0 + assign CH0_PMARSVDIN_in[2] = (CH0_PMARSVDIN[2] !== 1'bz) && CH0_PMARSVDIN[2]; // rv 0 + assign CH0_PMARSVDIN_in[3] = (CH0_PMARSVDIN[3] !== 1'bz) && CH0_PMARSVDIN[3]; // rv 0 + assign CH0_PMARSVDIN_in[4] = (CH0_PMARSVDIN[4] !== 1'bz) && CH0_PMARSVDIN[4]; // rv 0 + assign CH0_PMARSVDIN_in[5] = (CH0_PMARSVDIN[5] !== 1'bz) && CH0_PMARSVDIN[5]; // rv 0 + assign CH0_PMARSVDIN_in[6] = (CH0_PMARSVDIN[6] !== 1'bz) && CH0_PMARSVDIN[6]; // rv 0 + assign CH0_PMARSVDIN_in[7] = (CH0_PMARSVDIN[7] !== 1'bz) && CH0_PMARSVDIN[7]; // rv 0 + assign CH0_PMARSVDIN_in[8] = (CH0_PMARSVDIN[8] !== 1'bz) && CH0_PMARSVDIN[8]; // rv 0 + assign CH0_PMARSVDIN_in[9] = (CH0_PMARSVDIN[9] !== 1'bz) && CH0_PMARSVDIN[9]; // rv 0 + assign CH0_RESETOVRD_in = (CH0_RESETOVRD !== 1'bz) && CH0_RESETOVRD; // rv 0 + assign CH0_RXADAPTRESET_in = (CH0_RXADAPTRESET !== 1'bz) && CH0_RXADAPTRESET; // rv 0 + assign CH0_RXADCCALRESET_in = (CH0_RXADCCALRESET !== 1'bz) && CH0_RXADCCALRESET; // rv 0 + assign CH0_RXADCCLKGENRESET_in = (CH0_RXADCCLKGENRESET !== 1'bz) && CH0_RXADCCLKGENRESET; // rv 0 + assign CH0_RXBUFRESET_in = (CH0_RXBUFRESET !== 1'bz) && CH0_RXBUFRESET; // rv 0 + assign CH0_RXCDRFREQOS_in = (CH0_RXCDRFREQOS !== 1'bz) && CH0_RXCDRFREQOS; // rv 0 + assign CH0_RXCDRFRRESET_in = (CH0_RXCDRFRRESET !== 1'bz) && CH0_RXCDRFRRESET; // rv 0 + assign CH0_RXCDRHOLD_in = (CH0_RXCDRHOLD !== 1'bz) && CH0_RXCDRHOLD; // rv 0 + assign CH0_RXCDRINCPCTRL_in = (CH0_RXCDRINCPCTRL !== 1'bz) && CH0_RXCDRINCPCTRL; // rv 0 + assign CH0_RXCDROVRDEN_in = (CH0_RXCDROVRDEN !== 1'bz) && CH0_RXCDROVRDEN; // rv 0 + assign CH0_RXCDRPHRESET_in = (CH0_RXCDRPHRESET !== 1'bz) && CH0_RXCDRPHRESET; // rv 0 + assign CH0_RXDFERESET_in = (CH0_RXDFERESET !== 1'bz) && CH0_RXDFERESET; // rv 0 + assign CH0_RXDSPRESET_in = (CH0_RXDSPRESET !== 1'bz) && CH0_RXDSPRESET; // rv 0 + assign CH0_RXEYESCANRESET_in = (CH0_RXEYESCANRESET !== 1'bz) && CH0_RXEYESCANRESET; // rv 0 + assign CH0_RXFECRESET_in = (CH0_RXFECRESET !== 1'bz) && CH0_RXFECRESET; // rv 0 + assign CH0_RXOUTCLKSEL_in[0] = (CH0_RXOUTCLKSEL[0] !== 1'bz) && CH0_RXOUTCLKSEL[0]; // rv 0 + assign CH0_RXOUTCLKSEL_in[1] = (CH0_RXOUTCLKSEL[1] !== 1'bz) && CH0_RXOUTCLKSEL[1]; // rv 0 + assign CH0_RXOUTCLKSEL_in[2] = (CH0_RXOUTCLKSEL[2] !== 1'bz) && CH0_RXOUTCLKSEL[2]; // rv 0 + assign CH0_RXPCSRESETMASK_in[0] = (CH0_RXPCSRESETMASK[0] !== 1'bz) && CH0_RXPCSRESETMASK[0]; // rv 0 + assign CH0_RXPCSRESETMASK_in[1] = (CH0_RXPCSRESETMASK[1] !== 1'bz) && CH0_RXPCSRESETMASK[1]; // rv 0 + assign CH0_RXPCSRESETMASK_in[2] = (CH0_RXPCSRESETMASK[2] !== 1'bz) && CH0_RXPCSRESETMASK[2]; // rv 0 + assign CH0_RXPCSRESETMASK_in[3] = (CH0_RXPCSRESETMASK[3] !== 1'bz) && CH0_RXPCSRESETMASK[3]; // rv 0 + assign CH0_RXPCSRESET_in = (CH0_RXPCSRESET !== 1'bz) && CH0_RXPCSRESET; // rv 0 + assign CH0_RXPMARESETMASK_in[0] = (CH0_RXPMARESETMASK[0] !== 1'bz) && CH0_RXPMARESETMASK[0]; // rv 0 + assign CH0_RXPMARESETMASK_in[1] = (CH0_RXPMARESETMASK[1] !== 1'bz) && CH0_RXPMARESETMASK[1]; // rv 0 + assign CH0_RXPMARESETMASK_in[2] = (CH0_RXPMARESETMASK[2] !== 1'bz) && CH0_RXPMARESETMASK[2]; // rv 0 + assign CH0_RXPMARESETMASK_in[3] = (CH0_RXPMARESETMASK[3] !== 1'bz) && CH0_RXPMARESETMASK[3]; // rv 0 + assign CH0_RXPMARESETMASK_in[4] = (CH0_RXPMARESETMASK[4] !== 1'bz) && CH0_RXPMARESETMASK[4]; // rv 0 + assign CH0_RXPMARESETMASK_in[5] = (CH0_RXPMARESETMASK[5] !== 1'bz) && CH0_RXPMARESETMASK[5]; // rv 0 + assign CH0_RXPMARESETMASK_in[6] = (CH0_RXPMARESETMASK[6] !== 1'bz) && CH0_RXPMARESETMASK[6]; // rv 0 + assign CH0_RXPMARESETMASK_in[7] = (CH0_RXPMARESETMASK[7] !== 1'bz) && CH0_RXPMARESETMASK[7]; // rv 0 + assign CH0_RXPMARESET_in = (CH0_RXPMARESET !== 1'bz) && CH0_RXPMARESET; // rv 0 + assign CH0_RXPRBSCSCNTRST_in = (CH0_RXPRBSCSCNTRST !== 1'bz) && CH0_RXPRBSCSCNTRST; // rv 0 + assign CH0_RXPROGDIVRESET_in = (CH0_RXPROGDIVRESET !== 1'bz) && CH0_RXPROGDIVRESET; // rv 0 + assign CH0_RXRESETMODE_in[0] = (CH0_RXRESETMODE[0] !== 1'bz) && CH0_RXRESETMODE[0]; // rv 0 + assign CH0_RXRESETMODE_in[1] = (CH0_RXRESETMODE[1] !== 1'bz) && CH0_RXRESETMODE[1]; // rv 0 + assign CH0_RXSPCSEQADV_in = (CH0_RXSPCSEQADV !== 1'bz) && CH0_RXSPCSEQADV; // rv 0 + assign CH0_RXUSRRDY_in = (CH0_RXUSRRDY !== 1'bz) && CH0_RXUSRRDY; // rv 0 + assign CH0_RXUSRSTART_in = (CH0_RXUSRSTART !== 1'bz) && CH0_RXUSRSTART; // rv 0 + assign CH0_RXUSRSTOP_in = (CH0_RXUSRSTOP !== 1'bz) && CH0_RXUSRSTOP; // rv 0 + assign CH0_TXCKALRESET_in = (CH0_TXCKALRESET !== 1'bz) && CH0_TXCKALRESET; // rv 0 + assign CH0_TXCTLFIRDAT_in[0] = (CH0_TXCTLFIRDAT[0] !== 1'bz) && CH0_TXCTLFIRDAT[0]; // rv 0 + assign CH0_TXCTLFIRDAT_in[1] = (CH0_TXCTLFIRDAT[1] !== 1'bz) && CH0_TXCTLFIRDAT[1]; // rv 0 + assign CH0_TXCTLFIRDAT_in[2] = (CH0_TXCTLFIRDAT[2] !== 1'bz) && CH0_TXCTLFIRDAT[2]; // rv 0 + assign CH0_TXCTLFIRDAT_in[3] = (CH0_TXCTLFIRDAT[3] !== 1'bz) && CH0_TXCTLFIRDAT[3]; // rv 0 + assign CH0_TXCTLFIRDAT_in[4] = (CH0_TXCTLFIRDAT[4] !== 1'bz) && CH0_TXCTLFIRDAT[4]; // rv 0 + assign CH0_TXCTLFIRDAT_in[5] = (CH0_TXCTLFIRDAT[5] !== 1'bz) && CH0_TXCTLFIRDAT[5]; // rv 0 + assign CH0_TXDRVAMP_in[0] = (CH0_TXDRVAMP[0] !== 1'bz) && CH0_TXDRVAMP[0]; // rv 0 + assign CH0_TXDRVAMP_in[1] = (CH0_TXDRVAMP[1] !== 1'bz) && CH0_TXDRVAMP[1]; // rv 0 + assign CH0_TXDRVAMP_in[2] = (CH0_TXDRVAMP[2] !== 1'bz) && CH0_TXDRVAMP[2]; // rv 0 + assign CH0_TXDRVAMP_in[3] = (CH0_TXDRVAMP[3] !== 1'bz) && CH0_TXDRVAMP[3]; // rv 0 + assign CH0_TXDRVAMP_in[4] = (CH0_TXDRVAMP[4] !== 1'bz) && CH0_TXDRVAMP[4]; // rv 0 + assign CH0_TXEMPMAIN_in[0] = (CH0_TXEMPMAIN[0] !== 1'bz) && CH0_TXEMPMAIN[0]; // rv 0 + assign CH0_TXEMPMAIN_in[1] = (CH0_TXEMPMAIN[1] !== 1'bz) && CH0_TXEMPMAIN[1]; // rv 0 + assign CH0_TXEMPMAIN_in[2] = (CH0_TXEMPMAIN[2] !== 1'bz) && CH0_TXEMPMAIN[2]; // rv 0 + assign CH0_TXEMPMAIN_in[3] = (CH0_TXEMPMAIN[3] !== 1'bz) && CH0_TXEMPMAIN[3]; // rv 0 + assign CH0_TXEMPMAIN_in[4] = (CH0_TXEMPMAIN[4] !== 1'bz) && CH0_TXEMPMAIN[4]; // rv 0 + assign CH0_TXEMPMAIN_in[5] = (CH0_TXEMPMAIN[5] !== 1'bz) && CH0_TXEMPMAIN[5]; // rv 0 + assign CH0_TXEMPPOST_in[0] = (CH0_TXEMPPOST[0] !== 1'bz) && CH0_TXEMPPOST[0]; // rv 0 + assign CH0_TXEMPPOST_in[1] = (CH0_TXEMPPOST[1] !== 1'bz) && CH0_TXEMPPOST[1]; // rv 0 + assign CH0_TXEMPPOST_in[2] = (CH0_TXEMPPOST[2] !== 1'bz) && CH0_TXEMPPOST[2]; // rv 0 + assign CH0_TXEMPPOST_in[3] = (CH0_TXEMPPOST[3] !== 1'bz) && CH0_TXEMPPOST[3]; // rv 0 + assign CH0_TXEMPPOST_in[4] = (CH0_TXEMPPOST[4] !== 1'bz) && CH0_TXEMPPOST[4]; // rv 0 + assign CH0_TXEMPPRE2_in[0] = (CH0_TXEMPPRE2[0] !== 1'bz) && CH0_TXEMPPRE2[0]; // rv 0 + assign CH0_TXEMPPRE2_in[1] = (CH0_TXEMPPRE2[1] !== 1'bz) && CH0_TXEMPPRE2[1]; // rv 0 + assign CH0_TXEMPPRE2_in[2] = (CH0_TXEMPPRE2[2] !== 1'bz) && CH0_TXEMPPRE2[2]; // rv 0 + assign CH0_TXEMPPRE2_in[3] = (CH0_TXEMPPRE2[3] !== 1'bz) && CH0_TXEMPPRE2[3]; // rv 0 + assign CH0_TXEMPPRE_in[0] = (CH0_TXEMPPRE[0] !== 1'bz) && CH0_TXEMPPRE[0]; // rv 0 + assign CH0_TXEMPPRE_in[1] = (CH0_TXEMPPRE[1] !== 1'bz) && CH0_TXEMPPRE[1]; // rv 0 + assign CH0_TXEMPPRE_in[2] = (CH0_TXEMPPRE[2] !== 1'bz) && CH0_TXEMPPRE[2]; // rv 0 + assign CH0_TXEMPPRE_in[3] = (CH0_TXEMPPRE[3] !== 1'bz) && CH0_TXEMPPRE[3]; // rv 0 + assign CH0_TXEMPPRE_in[4] = (CH0_TXEMPPRE[4] !== 1'bz) && CH0_TXEMPPRE[4]; // rv 0 + assign CH0_TXFECRESET_in = (CH0_TXFECRESET !== 1'bz) && CH0_TXFECRESET; // rv 0 + assign CH0_TXMUXDCDEXHOLD_in = (CH0_TXMUXDCDEXHOLD !== 1'bz) && CH0_TXMUXDCDEXHOLD; // rv 0 + assign CH0_TXMUXDCDORWREN_in = (CH0_TXMUXDCDORWREN !== 1'bz) && CH0_TXMUXDCDORWREN; // rv 0 + assign CH0_TXOUTCLKSEL_in[0] = (CH0_TXOUTCLKSEL[0] !== 1'bz) && CH0_TXOUTCLKSEL[0]; // rv 0 + assign CH0_TXOUTCLKSEL_in[1] = (CH0_TXOUTCLKSEL[1] !== 1'bz) && CH0_TXOUTCLKSEL[1]; // rv 0 + assign CH0_TXOUTCLKSEL_in[2] = (CH0_TXOUTCLKSEL[2] !== 1'bz) && CH0_TXOUTCLKSEL[2]; // rv 0 + assign CH0_TXPCSRESETMASK_in[0] = (CH0_TXPCSRESETMASK[0] !== 1'bz) && CH0_TXPCSRESETMASK[0]; // rv 0 + assign CH0_TXPCSRESETMASK_in[1] = (CH0_TXPCSRESETMASK[1] !== 1'bz) && CH0_TXPCSRESETMASK[1]; // rv 0 + assign CH0_TXPCSRESET_in = (CH0_TXPCSRESET !== 1'bz) && CH0_TXPCSRESET; // rv 0 + assign CH0_TXPMARESETMASK_in[0] = (CH0_TXPMARESETMASK[0] !== 1'bz) && CH0_TXPMARESETMASK[0]; // rv 0 + assign CH0_TXPMARESETMASK_in[1] = (CH0_TXPMARESETMASK[1] !== 1'bz) && CH0_TXPMARESETMASK[1]; // rv 0 + assign CH0_TXPMARESET_in = (CH0_TXPMARESET !== 1'bz) && CH0_TXPMARESET; // rv 0 + assign CH0_TXPROGDIVRESET_in = (CH0_TXPROGDIVRESET !== 1'bz) && CH0_TXPROGDIVRESET; // rv 0 + assign CH0_TXRESETMODE_in[0] = (CH0_TXRESETMODE[0] !== 1'bz) && CH0_TXRESETMODE[0]; // rv 0 + assign CH0_TXRESETMODE_in[1] = (CH0_TXRESETMODE[1] !== 1'bz) && CH0_TXRESETMODE[1]; // rv 0 + assign CH0_TXSPCSEQADV_in = (CH0_TXSPCSEQADV !== 1'bz) && CH0_TXSPCSEQADV; // rv 0 + assign CH0_TXUSRRDY_in = (CH0_TXUSRRDY !== 1'bz) && CH0_TXUSRRDY; // rv 0 + assign CH1_AXISRST_in = (CH1_AXISRST !== 1'bz) && CH1_AXISRST; // rv 0 + assign CH1_CFGRESET_in = (CH1_CFGRESET !== 1'bz) && CH1_CFGRESET; // rv 0 + assign CH1_DMONFIFORESET_in = (CH1_DMONFIFORESET !== 1'bz) && CH1_DMONFIFORESET; // rv 0 + assign CH1_DMONITORCLK_in = (CH1_DMONITORCLK !== 1'bz) && CH1_DMONITORCLK; // rv 0 + assign CH1_GTMRXN_in = CH1_GTMRXN; + assign CH1_GTMRXP_in = CH1_GTMRXP; + assign CH1_GTRXRESET_in = (CH1_GTRXRESET !== 1'bz) && CH1_GTRXRESET; // rv 0 + assign CH1_GTTXRESET_in = (CH1_GTTXRESET !== 1'bz) && CH1_GTTXRESET; // rv 0 + assign CH1_LOOPBACK_in[0] = (CH1_LOOPBACK[0] !== 1'bz) && CH1_LOOPBACK[0]; // rv 0 + assign CH1_LOOPBACK_in[1] = (CH1_LOOPBACK[1] !== 1'bz) && CH1_LOOPBACK[1]; // rv 0 + assign CH1_LOOPBACK_in[2] = (CH1_LOOPBACK[2] !== 1'bz) && CH1_LOOPBACK[2]; // rv 0 + assign CH1_PCSRSVDIN_in[0] = (CH1_PCSRSVDIN[0] !== 1'bz) && CH1_PCSRSVDIN[0]; // rv 0 + assign CH1_PCSRSVDIN_in[10] = (CH1_PCSRSVDIN[10] !== 1'bz) && CH1_PCSRSVDIN[10]; // rv 0 + assign CH1_PCSRSVDIN_in[11] = (CH1_PCSRSVDIN[11] !== 1'bz) && CH1_PCSRSVDIN[11]; // rv 0 + assign CH1_PCSRSVDIN_in[12] = (CH1_PCSRSVDIN[12] !== 1'bz) && CH1_PCSRSVDIN[12]; // rv 0 + assign CH1_PCSRSVDIN_in[13] = (CH1_PCSRSVDIN[13] !== 1'bz) && CH1_PCSRSVDIN[13]; // rv 0 + assign CH1_PCSRSVDIN_in[14] = (CH1_PCSRSVDIN[14] !== 1'bz) && CH1_PCSRSVDIN[14]; // rv 0 + assign CH1_PCSRSVDIN_in[15] = (CH1_PCSRSVDIN[15] !== 1'bz) && CH1_PCSRSVDIN[15]; // rv 0 + assign CH1_PCSRSVDIN_in[1] = (CH1_PCSRSVDIN[1] !== 1'bz) && CH1_PCSRSVDIN[1]; // rv 0 + assign CH1_PCSRSVDIN_in[2] = (CH1_PCSRSVDIN[2] !== 1'bz) && CH1_PCSRSVDIN[2]; // rv 0 + assign CH1_PCSRSVDIN_in[3] = (CH1_PCSRSVDIN[3] !== 1'bz) && CH1_PCSRSVDIN[3]; // rv 0 + assign CH1_PCSRSVDIN_in[4] = (CH1_PCSRSVDIN[4] !== 1'bz) && CH1_PCSRSVDIN[4]; // rv 0 + assign CH1_PCSRSVDIN_in[5] = (CH1_PCSRSVDIN[5] !== 1'bz) && CH1_PCSRSVDIN[5]; // rv 0 + assign CH1_PCSRSVDIN_in[6] = (CH1_PCSRSVDIN[6] !== 1'bz) && CH1_PCSRSVDIN[6]; // rv 0 + assign CH1_PCSRSVDIN_in[7] = (CH1_PCSRSVDIN[7] !== 1'bz) && CH1_PCSRSVDIN[7]; // rv 0 + assign CH1_PCSRSVDIN_in[8] = (CH1_PCSRSVDIN[8] !== 1'bz) && CH1_PCSRSVDIN[8]; // rv 0 + assign CH1_PCSRSVDIN_in[9] = (CH1_PCSRSVDIN[9] !== 1'bz) && CH1_PCSRSVDIN[9]; // rv 0 + assign CH1_PMARSVDIN_in[0] = (CH1_PMARSVDIN[0] === 1'bz) || CH1_PMARSVDIN[0]; // rv 1 + assign CH1_PMARSVDIN_in[10] = (CH1_PMARSVDIN[10] !== 1'bz) && CH1_PMARSVDIN[10]; // rv 0 + assign CH1_PMARSVDIN_in[11] = (CH1_PMARSVDIN[11] !== 1'bz) && CH1_PMARSVDIN[11]; // rv 0 + assign CH1_PMARSVDIN_in[12] = (CH1_PMARSVDIN[12] !== 1'bz) && CH1_PMARSVDIN[12]; // rv 0 + assign CH1_PMARSVDIN_in[13] = (CH1_PMARSVDIN[13] !== 1'bz) && CH1_PMARSVDIN[13]; // rv 0 + assign CH1_PMARSVDIN_in[14] = (CH1_PMARSVDIN[14] !== 1'bz) && CH1_PMARSVDIN[14]; // rv 0 + assign CH1_PMARSVDIN_in[15] = (CH1_PMARSVDIN[15] !== 1'bz) && CH1_PMARSVDIN[15]; // rv 0 + assign CH1_PMARSVDIN_in[1] = (CH1_PMARSVDIN[1] !== 1'bz) && CH1_PMARSVDIN[1]; // rv 0 + assign CH1_PMARSVDIN_in[2] = (CH1_PMARSVDIN[2] !== 1'bz) && CH1_PMARSVDIN[2]; // rv 0 + assign CH1_PMARSVDIN_in[3] = (CH1_PMARSVDIN[3] !== 1'bz) && CH1_PMARSVDIN[3]; // rv 0 + assign CH1_PMARSVDIN_in[4] = (CH1_PMARSVDIN[4] !== 1'bz) && CH1_PMARSVDIN[4]; // rv 0 + assign CH1_PMARSVDIN_in[5] = (CH1_PMARSVDIN[5] !== 1'bz) && CH1_PMARSVDIN[5]; // rv 0 + assign CH1_PMARSVDIN_in[6] = (CH1_PMARSVDIN[6] !== 1'bz) && CH1_PMARSVDIN[6]; // rv 0 + assign CH1_PMARSVDIN_in[7] = (CH1_PMARSVDIN[7] !== 1'bz) && CH1_PMARSVDIN[7]; // rv 0 + assign CH1_PMARSVDIN_in[8] = (CH1_PMARSVDIN[8] !== 1'bz) && CH1_PMARSVDIN[8]; // rv 0 + assign CH1_PMARSVDIN_in[9] = (CH1_PMARSVDIN[9] !== 1'bz) && CH1_PMARSVDIN[9]; // rv 0 + assign CH1_RESETOVRD_in = (CH1_RESETOVRD !== 1'bz) && CH1_RESETOVRD; // rv 0 + assign CH1_RXADAPTRESET_in = (CH1_RXADAPTRESET !== 1'bz) && CH1_RXADAPTRESET; // rv 0 + assign CH1_RXADCCALRESET_in = (CH1_RXADCCALRESET !== 1'bz) && CH1_RXADCCALRESET; // rv 0 + assign CH1_RXADCCLKGENRESET_in = (CH1_RXADCCLKGENRESET !== 1'bz) && CH1_RXADCCLKGENRESET; // rv 0 + assign CH1_RXBUFRESET_in = (CH1_RXBUFRESET !== 1'bz) && CH1_RXBUFRESET; // rv 0 + assign CH1_RXCDRFREQOS_in = (CH1_RXCDRFREQOS !== 1'bz) && CH1_RXCDRFREQOS; // rv 0 + assign CH1_RXCDRFRRESET_in = (CH1_RXCDRFRRESET !== 1'bz) && CH1_RXCDRFRRESET; // rv 0 + assign CH1_RXCDRHOLD_in = (CH1_RXCDRHOLD !== 1'bz) && CH1_RXCDRHOLD; // rv 0 + assign CH1_RXCDRINCPCTRL_in = (CH1_RXCDRINCPCTRL !== 1'bz) && CH1_RXCDRINCPCTRL; // rv 0 + assign CH1_RXCDROVRDEN_in = (CH1_RXCDROVRDEN !== 1'bz) && CH1_RXCDROVRDEN; // rv 0 + assign CH1_RXCDRPHRESET_in = (CH1_RXCDRPHRESET !== 1'bz) && CH1_RXCDRPHRESET; // rv 0 + assign CH1_RXDFERESET_in = (CH1_RXDFERESET !== 1'bz) && CH1_RXDFERESET; // rv 0 + assign CH1_RXDSPRESET_in = (CH1_RXDSPRESET !== 1'bz) && CH1_RXDSPRESET; // rv 0 + assign CH1_RXEYESCANRESET_in = (CH1_RXEYESCANRESET !== 1'bz) && CH1_RXEYESCANRESET; // rv 0 + assign CH1_RXFECRESET_in = (CH1_RXFECRESET !== 1'bz) && CH1_RXFECRESET; // rv 0 + assign CH1_RXOUTCLKSEL_in[0] = (CH1_RXOUTCLKSEL[0] !== 1'bz) && CH1_RXOUTCLKSEL[0]; // rv 0 + assign CH1_RXOUTCLKSEL_in[1] = (CH1_RXOUTCLKSEL[1] !== 1'bz) && CH1_RXOUTCLKSEL[1]; // rv 0 + assign CH1_RXOUTCLKSEL_in[2] = (CH1_RXOUTCLKSEL[2] !== 1'bz) && CH1_RXOUTCLKSEL[2]; // rv 0 + assign CH1_RXPCSRESETMASK_in[0] = (CH1_RXPCSRESETMASK[0] !== 1'bz) && CH1_RXPCSRESETMASK[0]; // rv 0 + assign CH1_RXPCSRESETMASK_in[1] = (CH1_RXPCSRESETMASK[1] !== 1'bz) && CH1_RXPCSRESETMASK[1]; // rv 0 + assign CH1_RXPCSRESETMASK_in[2] = (CH1_RXPCSRESETMASK[2] !== 1'bz) && CH1_RXPCSRESETMASK[2]; // rv 0 + assign CH1_RXPCSRESETMASK_in[3] = (CH1_RXPCSRESETMASK[3] !== 1'bz) && CH1_RXPCSRESETMASK[3]; // rv 0 + assign CH1_RXPCSRESET_in = (CH1_RXPCSRESET !== 1'bz) && CH1_RXPCSRESET; // rv 0 + assign CH1_RXPMARESETMASK_in[0] = (CH1_RXPMARESETMASK[0] !== 1'bz) && CH1_RXPMARESETMASK[0]; // rv 0 + assign CH1_RXPMARESETMASK_in[1] = (CH1_RXPMARESETMASK[1] !== 1'bz) && CH1_RXPMARESETMASK[1]; // rv 0 + assign CH1_RXPMARESETMASK_in[2] = (CH1_RXPMARESETMASK[2] !== 1'bz) && CH1_RXPMARESETMASK[2]; // rv 0 + assign CH1_RXPMARESETMASK_in[3] = (CH1_RXPMARESETMASK[3] !== 1'bz) && CH1_RXPMARESETMASK[3]; // rv 0 + assign CH1_RXPMARESETMASK_in[4] = (CH1_RXPMARESETMASK[4] !== 1'bz) && CH1_RXPMARESETMASK[4]; // rv 0 + assign CH1_RXPMARESETMASK_in[5] = (CH1_RXPMARESETMASK[5] !== 1'bz) && CH1_RXPMARESETMASK[5]; // rv 0 + assign CH1_RXPMARESETMASK_in[6] = (CH1_RXPMARESETMASK[6] !== 1'bz) && CH1_RXPMARESETMASK[6]; // rv 0 + assign CH1_RXPMARESETMASK_in[7] = (CH1_RXPMARESETMASK[7] !== 1'bz) && CH1_RXPMARESETMASK[7]; // rv 0 + assign CH1_RXPMARESET_in = (CH1_RXPMARESET !== 1'bz) && CH1_RXPMARESET; // rv 0 + assign CH1_RXPRBSCSCNTRST_in = (CH1_RXPRBSCSCNTRST !== 1'bz) && CH1_RXPRBSCSCNTRST; // rv 0 + assign CH1_RXPROGDIVRESET_in = (CH1_RXPROGDIVRESET !== 1'bz) && CH1_RXPROGDIVRESET; // rv 0 + assign CH1_RXRESETMODE_in[0] = (CH1_RXRESETMODE[0] !== 1'bz) && CH1_RXRESETMODE[0]; // rv 0 + assign CH1_RXRESETMODE_in[1] = (CH1_RXRESETMODE[1] !== 1'bz) && CH1_RXRESETMODE[1]; // rv 0 + assign CH1_RXSPCSEQADV_in = (CH1_RXSPCSEQADV !== 1'bz) && CH1_RXSPCSEQADV; // rv 0 + assign CH1_RXUSRRDY_in = (CH1_RXUSRRDY !== 1'bz) && CH1_RXUSRRDY; // rv 0 + assign CH1_RXUSRSTART_in = (CH1_RXUSRSTART !== 1'bz) && CH1_RXUSRSTART; // rv 0 + assign CH1_RXUSRSTOP_in = (CH1_RXUSRSTOP !== 1'bz) && CH1_RXUSRSTOP; // rv 0 + assign CH1_TXCKALRESET_in = (CH1_TXCKALRESET !== 1'bz) && CH1_TXCKALRESET; // rv 0 + assign CH1_TXCTLFIRDAT_in[0] = (CH1_TXCTLFIRDAT[0] !== 1'bz) && CH1_TXCTLFIRDAT[0]; // rv 0 + assign CH1_TXCTLFIRDAT_in[1] = (CH1_TXCTLFIRDAT[1] !== 1'bz) && CH1_TXCTLFIRDAT[1]; // rv 0 + assign CH1_TXCTLFIRDAT_in[2] = (CH1_TXCTLFIRDAT[2] !== 1'bz) && CH1_TXCTLFIRDAT[2]; // rv 0 + assign CH1_TXCTLFIRDAT_in[3] = (CH1_TXCTLFIRDAT[3] !== 1'bz) && CH1_TXCTLFIRDAT[3]; // rv 0 + assign CH1_TXCTLFIRDAT_in[4] = (CH1_TXCTLFIRDAT[4] !== 1'bz) && CH1_TXCTLFIRDAT[4]; // rv 0 + assign CH1_TXCTLFIRDAT_in[5] = (CH1_TXCTLFIRDAT[5] !== 1'bz) && CH1_TXCTLFIRDAT[5]; // rv 0 + assign CH1_TXDRVAMP_in[0] = (CH1_TXDRVAMP[0] !== 1'bz) && CH1_TXDRVAMP[0]; // rv 0 + assign CH1_TXDRVAMP_in[1] = (CH1_TXDRVAMP[1] !== 1'bz) && CH1_TXDRVAMP[1]; // rv 0 + assign CH1_TXDRVAMP_in[2] = (CH1_TXDRVAMP[2] !== 1'bz) && CH1_TXDRVAMP[2]; // rv 0 + assign CH1_TXDRVAMP_in[3] = (CH1_TXDRVAMP[3] !== 1'bz) && CH1_TXDRVAMP[3]; // rv 0 + assign CH1_TXDRVAMP_in[4] = (CH1_TXDRVAMP[4] !== 1'bz) && CH1_TXDRVAMP[4]; // rv 0 + assign CH1_TXEMPMAIN_in[0] = (CH1_TXEMPMAIN[0] !== 1'bz) && CH1_TXEMPMAIN[0]; // rv 0 + assign CH1_TXEMPMAIN_in[1] = (CH1_TXEMPMAIN[1] !== 1'bz) && CH1_TXEMPMAIN[1]; // rv 0 + assign CH1_TXEMPMAIN_in[2] = (CH1_TXEMPMAIN[2] !== 1'bz) && CH1_TXEMPMAIN[2]; // rv 0 + assign CH1_TXEMPMAIN_in[3] = (CH1_TXEMPMAIN[3] !== 1'bz) && CH1_TXEMPMAIN[3]; // rv 0 + assign CH1_TXEMPMAIN_in[4] = (CH1_TXEMPMAIN[4] !== 1'bz) && CH1_TXEMPMAIN[4]; // rv 0 + assign CH1_TXEMPMAIN_in[5] = (CH1_TXEMPMAIN[5] !== 1'bz) && CH1_TXEMPMAIN[5]; // rv 0 + assign CH1_TXEMPPOST_in[0] = (CH1_TXEMPPOST[0] !== 1'bz) && CH1_TXEMPPOST[0]; // rv 0 + assign CH1_TXEMPPOST_in[1] = (CH1_TXEMPPOST[1] !== 1'bz) && CH1_TXEMPPOST[1]; // rv 0 + assign CH1_TXEMPPOST_in[2] = (CH1_TXEMPPOST[2] !== 1'bz) && CH1_TXEMPPOST[2]; // rv 0 + assign CH1_TXEMPPOST_in[3] = (CH1_TXEMPPOST[3] !== 1'bz) && CH1_TXEMPPOST[3]; // rv 0 + assign CH1_TXEMPPOST_in[4] = (CH1_TXEMPPOST[4] !== 1'bz) && CH1_TXEMPPOST[4]; // rv 0 + assign CH1_TXEMPPRE2_in[0] = (CH1_TXEMPPRE2[0] !== 1'bz) && CH1_TXEMPPRE2[0]; // rv 0 + assign CH1_TXEMPPRE2_in[1] = (CH1_TXEMPPRE2[1] !== 1'bz) && CH1_TXEMPPRE2[1]; // rv 0 + assign CH1_TXEMPPRE2_in[2] = (CH1_TXEMPPRE2[2] !== 1'bz) && CH1_TXEMPPRE2[2]; // rv 0 + assign CH1_TXEMPPRE2_in[3] = (CH1_TXEMPPRE2[3] !== 1'bz) && CH1_TXEMPPRE2[3]; // rv 0 + assign CH1_TXEMPPRE_in[0] = (CH1_TXEMPPRE[0] !== 1'bz) && CH1_TXEMPPRE[0]; // rv 0 + assign CH1_TXEMPPRE_in[1] = (CH1_TXEMPPRE[1] !== 1'bz) && CH1_TXEMPPRE[1]; // rv 0 + assign CH1_TXEMPPRE_in[2] = (CH1_TXEMPPRE[2] !== 1'bz) && CH1_TXEMPPRE[2]; // rv 0 + assign CH1_TXEMPPRE_in[3] = (CH1_TXEMPPRE[3] !== 1'bz) && CH1_TXEMPPRE[3]; // rv 0 + assign CH1_TXEMPPRE_in[4] = (CH1_TXEMPPRE[4] !== 1'bz) && CH1_TXEMPPRE[4]; // rv 0 + assign CH1_TXFECRESET_in = (CH1_TXFECRESET !== 1'bz) && CH1_TXFECRESET; // rv 0 + assign CH1_TXMUXDCDEXHOLD_in = (CH1_TXMUXDCDEXHOLD !== 1'bz) && CH1_TXMUXDCDEXHOLD; // rv 0 + assign CH1_TXMUXDCDORWREN_in = (CH1_TXMUXDCDORWREN !== 1'bz) && CH1_TXMUXDCDORWREN; // rv 0 + assign CH1_TXOUTCLKSEL_in[0] = (CH1_TXOUTCLKSEL[0] !== 1'bz) && CH1_TXOUTCLKSEL[0]; // rv 0 + assign CH1_TXOUTCLKSEL_in[1] = (CH1_TXOUTCLKSEL[1] !== 1'bz) && CH1_TXOUTCLKSEL[1]; // rv 0 + assign CH1_TXOUTCLKSEL_in[2] = (CH1_TXOUTCLKSEL[2] !== 1'bz) && CH1_TXOUTCLKSEL[2]; // rv 0 + assign CH1_TXPCSRESETMASK_in[0] = (CH1_TXPCSRESETMASK[0] !== 1'bz) && CH1_TXPCSRESETMASK[0]; // rv 0 + assign CH1_TXPCSRESETMASK_in[1] = (CH1_TXPCSRESETMASK[1] !== 1'bz) && CH1_TXPCSRESETMASK[1]; // rv 0 + assign CH1_TXPCSRESET_in = (CH1_TXPCSRESET !== 1'bz) && CH1_TXPCSRESET; // rv 0 + assign CH1_TXPMARESETMASK_in[0] = (CH1_TXPMARESETMASK[0] !== 1'bz) && CH1_TXPMARESETMASK[0]; // rv 0 + assign CH1_TXPMARESETMASK_in[1] = (CH1_TXPMARESETMASK[1] !== 1'bz) && CH1_TXPMARESETMASK[1]; // rv 0 + assign CH1_TXPMARESET_in = (CH1_TXPMARESET !== 1'bz) && CH1_TXPMARESET; // rv 0 + assign CH1_TXPROGDIVRESET_in = (CH1_TXPROGDIVRESET !== 1'bz) && CH1_TXPROGDIVRESET; // rv 0 + assign CH1_TXRESETMODE_in[0] = (CH1_TXRESETMODE[0] !== 1'bz) && CH1_TXRESETMODE[0]; // rv 0 + assign CH1_TXRESETMODE_in[1] = (CH1_TXRESETMODE[1] !== 1'bz) && CH1_TXRESETMODE[1]; // rv 0 + assign CH1_TXSPCSEQADV_in = (CH1_TXSPCSEQADV !== 1'bz) && CH1_TXSPCSEQADV; // rv 0 + assign CH1_TXUSRRDY_in = (CH1_TXUSRRDY !== 1'bz) && CH1_TXUSRRDY; // rv 0 + assign DRPRST_in = (DRPRST !== 1'bz) && DRPRST; // rv 0 + assign GTGREFCLK2PLL_in = GTGREFCLK2PLL; + assign GTNORTHREFCLK_in = GTNORTHREFCLK; + assign GTREFCLK_in = GTREFCLK; + assign GTSOUTHREFCLK_in = GTSOUTHREFCLK; + assign PLLFBDIV_in[0] = (PLLFBDIV[0] !== 1'bz) && PLLFBDIV[0]; // rv 0 + assign PLLFBDIV_in[1] = (PLLFBDIV[1] !== 1'bz) && PLLFBDIV[1]; // rv 0 + assign PLLFBDIV_in[2] = (PLLFBDIV[2] !== 1'bz) && PLLFBDIV[2]; // rv 0 + assign PLLFBDIV_in[3] = (PLLFBDIV[3] !== 1'bz) && PLLFBDIV[3]; // rv 0 + assign PLLFBDIV_in[4] = (PLLFBDIV[4] !== 1'bz) && PLLFBDIV[4]; // rv 0 + assign PLLFBDIV_in[5] = (PLLFBDIV[5] !== 1'bz) && PLLFBDIV[5]; // rv 0 + assign PLLFBDIV_in[6] = (PLLFBDIV[6] !== 1'bz) && PLLFBDIV[6]; // rv 0 + assign PLLFBDIV_in[7] = (PLLFBDIV[7] !== 1'bz) && PLLFBDIV[7]; // rv 0 + assign PLLMONCLK_in = (PLLMONCLK === 1'bz) || PLLMONCLK; // rv 1 + assign PLLPD_in = (PLLPD !== 1'bz) && PLLPD; // rv 0 + assign PLLREFCLKSEL_in[0] = (PLLREFCLKSEL[0] === 1'bz) || PLLREFCLKSEL[0]; // rv 1 + assign PLLREFCLKSEL_in[1] = (PLLREFCLKSEL[1] !== 1'bz) && PLLREFCLKSEL[1]; // rv 0 + assign PLLREFCLKSEL_in[2] = (PLLREFCLKSEL[2] !== 1'bz) && PLLREFCLKSEL[2]; // rv 0 + assign PLLRESETBYPASSMODE_in = (PLLRESETBYPASSMODE !== 1'bz) && PLLRESETBYPASSMODE; // rv 0 + assign PLLRESETMASK_in[0] = (PLLRESETMASK[0] !== 1'bz) && PLLRESETMASK[0]; // rv 0 + assign PLLRESETMASK_in[1] = (PLLRESETMASK[1] !== 1'bz) && PLLRESETMASK[1]; // rv 0 + assign PLLRESET_in = (PLLRESET === 1'bz) || PLLRESET; // rv 1 + assign PLLRSVDIN_in[0] = (PLLRSVDIN[0] === 1'bz) || PLLRSVDIN[0]; // rv 1 + assign PLLRSVDIN_in[10] = (PLLRSVDIN[10] !== 1'bz) && PLLRSVDIN[10]; // rv 0 + assign PLLRSVDIN_in[11] = (PLLRSVDIN[11] !== 1'bz) && PLLRSVDIN[11]; // rv 0 + assign PLLRSVDIN_in[12] = (PLLRSVDIN[12] !== 1'bz) && PLLRSVDIN[12]; // rv 0 + assign PLLRSVDIN_in[13] = (PLLRSVDIN[13] !== 1'bz) && PLLRSVDIN[13]; // rv 0 + assign PLLRSVDIN_in[14] = (PLLRSVDIN[14] !== 1'bz) && PLLRSVDIN[14]; // rv 0 + assign PLLRSVDIN_in[15] = (PLLRSVDIN[15] !== 1'bz) && PLLRSVDIN[15]; // rv 0 + assign PLLRSVDIN_in[1] = (PLLRSVDIN[1] !== 1'bz) && PLLRSVDIN[1]; // rv 0 + assign PLLRSVDIN_in[2] = (PLLRSVDIN[2] !== 1'bz) && PLLRSVDIN[2]; // rv 0 + assign PLLRSVDIN_in[3] = (PLLRSVDIN[3] !== 1'bz) && PLLRSVDIN[3]; // rv 0 + assign PLLRSVDIN_in[4] = (PLLRSVDIN[4] !== 1'bz) && PLLRSVDIN[4]; // rv 0 + assign PLLRSVDIN_in[5] = (PLLRSVDIN[5] !== 1'bz) && PLLRSVDIN[5]; // rv 0 + assign PLLRSVDIN_in[6] = (PLLRSVDIN[6] !== 1'bz) && PLLRSVDIN[6]; // rv 0 + assign PLLRSVDIN_in[7] = (PLLRSVDIN[7] !== 1'bz) && PLLRSVDIN[7]; // rv 0 + assign PLLRSVDIN_in[8] = (PLLRSVDIN[8] !== 1'bz) && PLLRSVDIN[8]; // rv 0 + assign PLLRSVDIN_in[9] = (PLLRSVDIN[9] !== 1'bz) && PLLRSVDIN[9]; // rv 0 + assign RCALENB_in = RCALENB; + assign SDMDATA_in[0] = (SDMDATA[0] !== 1'bz) && SDMDATA[0]; // rv 0 + assign SDMDATA_in[10] = (SDMDATA[10] !== 1'bz) && SDMDATA[10]; // rv 0 + assign SDMDATA_in[11] = (SDMDATA[11] !== 1'bz) && SDMDATA[11]; // rv 0 + assign SDMDATA_in[12] = (SDMDATA[12] !== 1'bz) && SDMDATA[12]; // rv 0 + assign SDMDATA_in[13] = (SDMDATA[13] !== 1'bz) && SDMDATA[13]; // rv 0 + assign SDMDATA_in[14] = (SDMDATA[14] !== 1'bz) && SDMDATA[14]; // rv 0 + assign SDMDATA_in[15] = (SDMDATA[15] !== 1'bz) && SDMDATA[15]; // rv 0 + assign SDMDATA_in[16] = (SDMDATA[16] !== 1'bz) && SDMDATA[16]; // rv 0 + assign SDMDATA_in[17] = (SDMDATA[17] !== 1'bz) && SDMDATA[17]; // rv 0 + assign SDMDATA_in[18] = (SDMDATA[18] !== 1'bz) && SDMDATA[18]; // rv 0 + assign SDMDATA_in[19] = (SDMDATA[19] !== 1'bz) && SDMDATA[19]; // rv 0 + assign SDMDATA_in[1] = (SDMDATA[1] !== 1'bz) && SDMDATA[1]; // rv 0 + assign SDMDATA_in[20] = (SDMDATA[20] !== 1'bz) && SDMDATA[20]; // rv 0 + assign SDMDATA_in[21] = (SDMDATA[21] !== 1'bz) && SDMDATA[21]; // rv 0 + assign SDMDATA_in[22] = (SDMDATA[22] !== 1'bz) && SDMDATA[22]; // rv 0 + assign SDMDATA_in[23] = (SDMDATA[23] !== 1'bz) && SDMDATA[23]; // rv 0 + assign SDMDATA_in[24] = (SDMDATA[24] !== 1'bz) && SDMDATA[24]; // rv 0 + assign SDMDATA_in[25] = (SDMDATA[25] !== 1'bz) && SDMDATA[25]; // rv 0 + assign SDMDATA_in[2] = (SDMDATA[2] !== 1'bz) && SDMDATA[2]; // rv 0 + assign SDMDATA_in[3] = (SDMDATA[3] !== 1'bz) && SDMDATA[3]; // rv 0 + assign SDMDATA_in[4] = (SDMDATA[4] !== 1'bz) && SDMDATA[4]; // rv 0 + assign SDMDATA_in[5] = (SDMDATA[5] !== 1'bz) && SDMDATA[5]; // rv 0 + assign SDMDATA_in[6] = (SDMDATA[6] !== 1'bz) && SDMDATA[6]; // rv 0 + assign SDMDATA_in[7] = (SDMDATA[7] !== 1'bz) && SDMDATA[7]; // rv 0 + assign SDMDATA_in[8] = (SDMDATA[8] !== 1'bz) && SDMDATA[8]; // rv 0 + assign SDMDATA_in[9] = (SDMDATA[9] !== 1'bz) && SDMDATA[9]; // rv 0 + assign SDMTOGGLE_in = (SDMTOGGLE !== 1'bz) && SDMTOGGLE; // rv 0 + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign DATARATE_BIN = DATARATE_REG * 1000; + + assign INS_LOSS_NYQ_BIN = INS_LOSS_NYQ_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + DATARATE_BIN = DATARATE_REG * 1000; + + INS_LOSS_NYQ_BIN = INS_LOSS_NYQ_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + (DATARATE_REG < 9.800 || DATARATE_REG > 58.000)) begin + $display("Error: [Unisim %s-406] DATARATE attribute is set to %f. Legal values for this attribute are 9.800 to 58.000. Instance: %m", MODULE_NAME, DATARATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FEC_MODE_REG != "BYPASS") && + (FEC_MODE_REG != "KP4"))) begin + $display("Error: [Unisim %s-436] FEC_MODE attribute is set to %s. Legal values for this attribute are BYPASS or KP4. Instance: %m", MODULE_NAME, FEC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (INS_LOSS_NYQ_REG < 0.000 || INS_LOSS_NYQ_REG > 60.000)) begin + $display("Error: [Unisim %s-437] INS_LOSS_NYQ attribute is set to %f. Legal values for this attribute are 0.000 to 60.000. Instance: %m", MODULE_NAME, INS_LOSS_NYQ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((INTERFACE_WIDTH_REG < 64) || (INTERFACE_WIDTH_REG > 256))) begin + $display("Error: [Unisim %s-438] INTERFACE_WIDTH attribute is set to %d. Legal values for this attribute are 64 to 256. Instance: %m", MODULE_NAME, INTERFACE_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MODULATION_MODE_REG != "NRZ") && + (MODULATION_MODE_REG != "PAM4"))) begin + $display("Error: [Unisim %s-439] MODULATION_MODE attribute is set to %s. Legal values for this attribute are NRZ or PAM4. Instance: %m", MODULE_NAME, MODULATION_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PLL_IPS_REFCLK_SEL_REG != 0) && + (PLL_IPS_REFCLK_SEL_REG != 1) && + (PLL_IPS_REFCLK_SEL_REG != 2) && + (PLL_IPS_REFCLK_SEL_REG != 3) && + (PLL_IPS_REFCLK_SEL_REG != 4) && + (PLL_IPS_REFCLK_SEL_REG != 5) && + (PLL_IPS_REFCLK_SEL_REG != 6) && + (PLL_IPS_REFCLK_SEL_REG != 7))) begin + $display("Error: [Unisim %s-450] PLL_IPS_REFCLK_SEL attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PLL_IPS_REFCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-461] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-462] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_AMPLITUDE_SWING_REG < 250) || (TX_AMPLITUDE_SWING_REG > 1025))) begin + $display("Error: [Unisim %s-463] TX_AMPLITUDE_SWING attribute is set to %d. Legal values for this attribute are 250 to 1025. Instance: %m", MODULE_NAME, TX_AMPLITUDE_SWING_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + + +assign CH0_PCSSCANCLK_in = 2'b11; // tie off +assign CH0_PMASCANCLK_in = 9'b111111111; // tie off +assign CH0_TSTCLK0_in = 1'b1; // tie off +assign CH0_TSTCLK1_in = 1'b1; // tie off +assign CH1_PCSSCANCLK_in = 2'b11; // tie off +assign CH1_PMASCANCLK_in = 9'b111111111; // tie off +assign CH1_TSTCLK0_in = 1'b1; // tie off +assign CH1_TSTCLK1_in = 1'b1; // tie off +assign CLKTESTSIG_in = 1'b1; // tie off +assign FECSCANCLK_in = 1'b1; // tie off +assign PLLSCANCLK_in = 4'b1111; // tie off + +assign CH0_BSRSERIAL_in = 1'b1; // tie off +assign CH0_PCSSCANENB_in = 1'b1; // tie off +assign CH0_PCSSCANIN_in = 15'b111111111111111; // tie off +assign CH0_PCSSCANMODEB_in = 1'b1; // tie off +assign CH0_PCSSCANRSTB_in = 1'b1; // tie off +assign CH0_PCSSCANRSTEN_in = 1'b1; // tie off +assign CH0_PMASCANENB_in = 1'b1; // tie off +assign CH0_PMASCANIN_in = 25'b1111111111111111111111111; // tie off +assign CH0_PMASCANMODEB_in = 1'b1; // tie off +assign CH0_PMASCANRSTEN_in = 1'b1; // tie off +assign CH1_BSRSERIAL_in = 1'b1; // tie off +assign CH1_PCSSCANENB_in = 1'b1; // tie off +assign CH1_PCSSCANIN_in = 15'b111111111111111; // tie off +assign CH1_PCSSCANMODEB_in = 1'b1; // tie off +assign CH1_PCSSCANRSTB_in = 1'b1; // tie off +assign CH1_PCSSCANRSTEN_in = 1'b1; // tie off +assign CH1_PMASCANENB_in = 1'b1; // tie off +assign CH1_PMASCANIN_in = 25'b1111111111111111111111111; // tie off +assign CH1_PMASCANMODEB_in = 1'b1; // tie off +assign CH1_PMASCANRSTEN_in = 1'b1; // tie off +assign FECSCANENB_in = 1'b1; // tie off +assign FECSCANIN_in = 200'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off +assign FECSCANMODEB_in = 1'b1; // tie off +assign FECSCANRSTB_in = 1'b1; // tie off +assign GTREFCLKPD_in = 1'b1; // tie off +assign PLLSCANENB_in = 1'b1; // tie off +assign PLLSCANIN_in = 8'b11111111; // tie off +assign PLLSCANMODEB_in = 1'b1; // tie off +assign PLLSCANRSTEN_in = 1'b1; // tie off +assign RCALSEL_in = 2'b11; // tie off +assign REFCLK2HROW_in = 1'b1; // tie off + +// HIERARCHICAL BYPASS +// A zero time simulation adds hierarchy and port information to the log file +// to be later processed by a tcl script to generate sidefiles for users +// not using Vivado. +initial begin + if ($test$plusargs ("GEN_BYPASS")) begin + $display("xilinx_hier_bypass_ports:%m XIL_PORT_SPEC:in:integer:CH0_GTMRXN:CH0_GTMRXN_integer in:integer:CH0_GTMRXP:CH0_GTMRXP_integer in:integer:CH1_GTMRXN:CH1_GTMRXN_integer in:integer:CH1_GTMRXP:CH1_GTMRXP_integer out:integer:CH0_GTMTXN:CH0_GTMTXN_integer out:integer:CH0_GTMTXP:CH0_GTMTXP_integer out:integer:CH1_GTMTXN:CH1_GTMTXN_integer out:integer:CH1_GTMTXP:CH1_GTMTXP_integer"); + #0 $finish; + end +end + + SIP_GTM_DUAL SIP_GTM_DUAL_INST ( + .A_CFG (A_CFG_REG), + .A_SDM_DATA_CFG0 (A_SDM_DATA_CFG0_REG), + .A_SDM_DATA_CFG1 (A_SDM_DATA_CFG1_REG), + .BIAS_CFG0 (BIAS_CFG0_REG), + .BIAS_CFG1 (BIAS_CFG1_REG), + .BIAS_CFG2 (BIAS_CFG2_REG), + .BIAS_CFG3 (BIAS_CFG3_REG), + .BIAS_CFG4 (BIAS_CFG4_REG), + .BIAS_CFG5 (BIAS_CFG5_REG), + .BIAS_CFG6 (BIAS_CFG6_REG), + .BIAS_CFG7 (BIAS_CFG7_REG), + .CH0_A_CH_CFG0 (CH0_A_CH_CFG0_REG), + .CH0_A_CH_CFG1 (CH0_A_CH_CFG1_REG), + .CH0_A_CH_CFG2 (CH0_A_CH_CFG2_REG), + .CH0_A_CH_CFG3 (CH0_A_CH_CFG3_REG), + .CH0_A_CH_CFG4 (CH0_A_CH_CFG4_REG), + .CH0_A_CH_CFG5 (CH0_A_CH_CFG5_REG), + .CH0_A_CH_CFG6 (CH0_A_CH_CFG6_REG), + .CH0_RST_LP_CFG0 (CH0_RST_LP_CFG0_REG), + .CH0_RST_LP_CFG1 (CH0_RST_LP_CFG1_REG), + .CH0_RST_LP_CFG2 (CH0_RST_LP_CFG2_REG), + .CH0_RST_LP_CFG3 (CH0_RST_LP_CFG3_REG), + .CH0_RST_LP_CFG4 (CH0_RST_LP_CFG4_REG), + .CH0_RST_LP_ID_CFG0 (CH0_RST_LP_ID_CFG0_REG), + .CH0_RST_LP_ID_CFG1 (CH0_RST_LP_ID_CFG1_REG), + .CH0_RST_TIME_CFG0 (CH0_RST_TIME_CFG0_REG), + .CH0_RST_TIME_CFG1 (CH0_RST_TIME_CFG1_REG), + .CH0_RST_TIME_CFG2 (CH0_RST_TIME_CFG2_REG), + .CH0_RST_TIME_CFG3 (CH0_RST_TIME_CFG3_REG), + .CH0_RST_TIME_CFG4 (CH0_RST_TIME_CFG4_REG), + .CH0_RST_TIME_CFG5 (CH0_RST_TIME_CFG5_REG), + .CH0_RST_TIME_CFG6 (CH0_RST_TIME_CFG6_REG), + .CH0_RX_ADC_CFG0 (CH0_RX_ADC_CFG0_REG), + .CH0_RX_ADC_CFG1 (CH0_RX_ADC_CFG1_REG), + .CH0_RX_ANA_CFG0 (CH0_RX_ANA_CFG0_REG), + .CH0_RX_ANA_CFG1 (CH0_RX_ANA_CFG1_REG), + .CH0_RX_ANA_CFG2 (CH0_RX_ANA_CFG2_REG), + .CH0_RX_APT_CFG0A (CH0_RX_APT_CFG0A_REG), + .CH0_RX_APT_CFG0B (CH0_RX_APT_CFG0B_REG), + .CH0_RX_APT_CFG10A (CH0_RX_APT_CFG10A_REG), + .CH0_RX_APT_CFG10B (CH0_RX_APT_CFG10B_REG), + .CH0_RX_APT_CFG11A (CH0_RX_APT_CFG11A_REG), + .CH0_RX_APT_CFG11B (CH0_RX_APT_CFG11B_REG), + .CH0_RX_APT_CFG12A (CH0_RX_APT_CFG12A_REG), + .CH0_RX_APT_CFG12B (CH0_RX_APT_CFG12B_REG), + .CH0_RX_APT_CFG13A (CH0_RX_APT_CFG13A_REG), + .CH0_RX_APT_CFG13B (CH0_RX_APT_CFG13B_REG), + .CH0_RX_APT_CFG14A (CH0_RX_APT_CFG14A_REG), + .CH0_RX_APT_CFG14B (CH0_RX_APT_CFG14B_REG), + .CH0_RX_APT_CFG15A (CH0_RX_APT_CFG15A_REG), + .CH0_RX_APT_CFG15B (CH0_RX_APT_CFG15B_REG), + .CH0_RX_APT_CFG16A (CH0_RX_APT_CFG16A_REG), + .CH0_RX_APT_CFG16B (CH0_RX_APT_CFG16B_REG), + .CH0_RX_APT_CFG17A (CH0_RX_APT_CFG17A_REG), + .CH0_RX_APT_CFG17B (CH0_RX_APT_CFG17B_REG), + .CH0_RX_APT_CFG18A (CH0_RX_APT_CFG18A_REG), + .CH0_RX_APT_CFG18B (CH0_RX_APT_CFG18B_REG), + .CH0_RX_APT_CFG19A (CH0_RX_APT_CFG19A_REG), + .CH0_RX_APT_CFG19B (CH0_RX_APT_CFG19B_REG), + .CH0_RX_APT_CFG1A (CH0_RX_APT_CFG1A_REG), + .CH0_RX_APT_CFG1B (CH0_RX_APT_CFG1B_REG), + .CH0_RX_APT_CFG20A (CH0_RX_APT_CFG20A_REG), + .CH0_RX_APT_CFG20B (CH0_RX_APT_CFG20B_REG), + .CH0_RX_APT_CFG21A (CH0_RX_APT_CFG21A_REG), + .CH0_RX_APT_CFG21B (CH0_RX_APT_CFG21B_REG), + .CH0_RX_APT_CFG22A (CH0_RX_APT_CFG22A_REG), + .CH0_RX_APT_CFG22B (CH0_RX_APT_CFG22B_REG), + .CH0_RX_APT_CFG23A (CH0_RX_APT_CFG23A_REG), + .CH0_RX_APT_CFG23B (CH0_RX_APT_CFG23B_REG), + .CH0_RX_APT_CFG24A (CH0_RX_APT_CFG24A_REG), + .CH0_RX_APT_CFG24B (CH0_RX_APT_CFG24B_REG), + .CH0_RX_APT_CFG25A (CH0_RX_APT_CFG25A_REG), + .CH0_RX_APT_CFG25B (CH0_RX_APT_CFG25B_REG), + .CH0_RX_APT_CFG26A (CH0_RX_APT_CFG26A_REG), + .CH0_RX_APT_CFG26B (CH0_RX_APT_CFG26B_REG), + .CH0_RX_APT_CFG27A (CH0_RX_APT_CFG27A_REG), + .CH0_RX_APT_CFG27B (CH0_RX_APT_CFG27B_REG), + .CH0_RX_APT_CFG28A (CH0_RX_APT_CFG28A_REG), + .CH0_RX_APT_CFG28B (CH0_RX_APT_CFG28B_REG), + .CH0_RX_APT_CFG2A (CH0_RX_APT_CFG2A_REG), + .CH0_RX_APT_CFG2B (CH0_RX_APT_CFG2B_REG), + .CH0_RX_APT_CFG3A (CH0_RX_APT_CFG3A_REG), + .CH0_RX_APT_CFG3B (CH0_RX_APT_CFG3B_REG), + .CH0_RX_APT_CFG4A (CH0_RX_APT_CFG4A_REG), + .CH0_RX_APT_CFG4B (CH0_RX_APT_CFG4B_REG), + .CH0_RX_APT_CFG5A (CH0_RX_APT_CFG5A_REG), + .CH0_RX_APT_CFG5B (CH0_RX_APT_CFG5B_REG), + .CH0_RX_APT_CFG6A (CH0_RX_APT_CFG6A_REG), + .CH0_RX_APT_CFG6B (CH0_RX_APT_CFG6B_REG), + .CH0_RX_APT_CFG7A (CH0_RX_APT_CFG7A_REG), + .CH0_RX_APT_CFG7B (CH0_RX_APT_CFG7B_REG), + .CH0_RX_APT_CFG8A (CH0_RX_APT_CFG8A_REG), + .CH0_RX_APT_CFG8B (CH0_RX_APT_CFG8B_REG), + .CH0_RX_APT_CFG9A (CH0_RX_APT_CFG9A_REG), + .CH0_RX_APT_CFG9B (CH0_RX_APT_CFG9B_REG), + .CH0_RX_APT_CTRL_CFG2 (CH0_RX_APT_CTRL_CFG2_REG), + .CH0_RX_APT_CTRL_CFG3 (CH0_RX_APT_CTRL_CFG3_REG), + .CH0_RX_CAL_CFG0A (CH0_RX_CAL_CFG0A_REG), + .CH0_RX_CAL_CFG0B (CH0_RX_CAL_CFG0B_REG), + .CH0_RX_CAL_CFG1A (CH0_RX_CAL_CFG1A_REG), + .CH0_RX_CAL_CFG1B (CH0_RX_CAL_CFG1B_REG), + .CH0_RX_CAL_CFG2A (CH0_RX_CAL_CFG2A_REG), + .CH0_RX_CAL_CFG2B (CH0_RX_CAL_CFG2B_REG), + .CH0_RX_CDR_CFG0A (CH0_RX_CDR_CFG0A_REG), + .CH0_RX_CDR_CFG0B (CH0_RX_CDR_CFG0B_REG), + .CH0_RX_CDR_CFG1A (CH0_RX_CDR_CFG1A_REG), + .CH0_RX_CDR_CFG1B (CH0_RX_CDR_CFG1B_REG), + .CH0_RX_CDR_CFG2A (CH0_RX_CDR_CFG2A_REG), + .CH0_RX_CDR_CFG2B (CH0_RX_CDR_CFG2B_REG), + .CH0_RX_CDR_CFG3A (CH0_RX_CDR_CFG3A_REG), + .CH0_RX_CDR_CFG3B (CH0_RX_CDR_CFG3B_REG), + .CH0_RX_CDR_CFG4A (CH0_RX_CDR_CFG4A_REG), + .CH0_RX_CDR_CFG4B (CH0_RX_CDR_CFG4B_REG), + .CH0_RX_CLKGN_CFG0 (CH0_RX_CLKGN_CFG0_REG), + .CH0_RX_CLKGN_CFG1 (CH0_RX_CLKGN_CFG1_REG), + .CH0_RX_CTLE_CFG0 (CH0_RX_CTLE_CFG0_REG), + .CH0_RX_CTLE_CFG1 (CH0_RX_CTLE_CFG1_REG), + .CH0_RX_CTLE_CFG2 (CH0_RX_CTLE_CFG2_REG), + .CH0_RX_CTLE_CFG3 (CH0_RX_CTLE_CFG3_REG), + .CH0_RX_DSP_CFG (CH0_RX_DSP_CFG_REG), + .CH0_RX_MON_CFG (CH0_RX_MON_CFG_REG), + .CH0_RX_PAD_CFG0 (CH0_RX_PAD_CFG0_REG), + .CH0_RX_PAD_CFG1 (CH0_RX_PAD_CFG1_REG), + .CH0_RX_PCS_CFG0 (CH0_RX_PCS_CFG0_REG), + .CH0_RX_PCS_CFG1 (CH0_RX_PCS_CFG1_REG), + .CH0_TX_ANA_CFG0 (CH0_TX_ANA_CFG0_REG), + .CH0_TX_ANA_CFG1 (CH0_TX_ANA_CFG1_REG), + .CH0_TX_ANA_CFG2 (CH0_TX_ANA_CFG2_REG), + .CH0_TX_ANA_CFG3 (CH0_TX_ANA_CFG3_REG), + .CH0_TX_ANA_CFG4 (CH0_TX_ANA_CFG4_REG), + .CH0_TX_CAL_CFG0 (CH0_TX_CAL_CFG0_REG), + .CH0_TX_CAL_CFG1 (CH0_TX_CAL_CFG1_REG), + .CH0_TX_DRV_CFG0 (CH0_TX_DRV_CFG0_REG), + .CH0_TX_DRV_CFG1 (CH0_TX_DRV_CFG1_REG), + .CH0_TX_DRV_CFG2 (CH0_TX_DRV_CFG2_REG), + .CH0_TX_DRV_CFG3 (CH0_TX_DRV_CFG3_REG), + .CH0_TX_DRV_CFG4 (CH0_TX_DRV_CFG4_REG), + .CH0_TX_DRV_CFG5 (CH0_TX_DRV_CFG5_REG), + .CH0_TX_LPBK_CFG0 (CH0_TX_LPBK_CFG0_REG), + .CH0_TX_LPBK_CFG1 (CH0_TX_LPBK_CFG1_REG), + .CH0_TX_PCS_CFG0 (CH0_TX_PCS_CFG0_REG), + .CH0_TX_PCS_CFG1 (CH0_TX_PCS_CFG1_REG), + .CH0_TX_PCS_CFG10 (CH0_TX_PCS_CFG10_REG), + .CH0_TX_PCS_CFG11 (CH0_TX_PCS_CFG11_REG), + .CH0_TX_PCS_CFG12 (CH0_TX_PCS_CFG12_REG), + .CH0_TX_PCS_CFG13 (CH0_TX_PCS_CFG13_REG), + .CH0_TX_PCS_CFG14 (CH0_TX_PCS_CFG14_REG), + .CH0_TX_PCS_CFG15 (CH0_TX_PCS_CFG15_REG), + .CH0_TX_PCS_CFG16 (CH0_TX_PCS_CFG16_REG), + .CH0_TX_PCS_CFG17 (CH0_TX_PCS_CFG17_REG), + .CH0_TX_PCS_CFG2 (CH0_TX_PCS_CFG2_REG), + .CH0_TX_PCS_CFG3 (CH0_TX_PCS_CFG3_REG), + .CH0_TX_PCS_CFG4 (CH0_TX_PCS_CFG4_REG), + .CH0_TX_PCS_CFG5 (CH0_TX_PCS_CFG5_REG), + .CH0_TX_PCS_CFG6 (CH0_TX_PCS_CFG6_REG), + .CH0_TX_PCS_CFG7 (CH0_TX_PCS_CFG7_REG), + .CH0_TX_PCS_CFG8 (CH0_TX_PCS_CFG8_REG), + .CH0_TX_PCS_CFG9 (CH0_TX_PCS_CFG9_REG), + .CH1_A_CH_CFG0 (CH1_A_CH_CFG0_REG), + .CH1_A_CH_CFG1 (CH1_A_CH_CFG1_REG), + .CH1_A_CH_CFG2 (CH1_A_CH_CFG2_REG), + .CH1_A_CH_CFG3 (CH1_A_CH_CFG3_REG), + .CH1_A_CH_CFG4 (CH1_A_CH_CFG4_REG), + .CH1_A_CH_CFG5 (CH1_A_CH_CFG5_REG), + .CH1_A_CH_CFG6 (CH1_A_CH_CFG6_REG), + .CH1_RST_LP_CFG0 (CH1_RST_LP_CFG0_REG), + .CH1_RST_LP_CFG1 (CH1_RST_LP_CFG1_REG), + .CH1_RST_LP_CFG2 (CH1_RST_LP_CFG2_REG), + .CH1_RST_LP_CFG3 (CH1_RST_LP_CFG3_REG), + .CH1_RST_LP_CFG4 (CH1_RST_LP_CFG4_REG), + .CH1_RST_LP_ID_CFG0 (CH1_RST_LP_ID_CFG0_REG), + .CH1_RST_LP_ID_CFG1 (CH1_RST_LP_ID_CFG1_REG), + .CH1_RST_TIME_CFG0 (CH1_RST_TIME_CFG0_REG), + .CH1_RST_TIME_CFG1 (CH1_RST_TIME_CFG1_REG), + .CH1_RST_TIME_CFG2 (CH1_RST_TIME_CFG2_REG), + .CH1_RST_TIME_CFG3 (CH1_RST_TIME_CFG3_REG), + .CH1_RST_TIME_CFG4 (CH1_RST_TIME_CFG4_REG), + .CH1_RST_TIME_CFG5 (CH1_RST_TIME_CFG5_REG), + .CH1_RST_TIME_CFG6 (CH1_RST_TIME_CFG6_REG), + .CH1_RX_ADC_CFG0 (CH1_RX_ADC_CFG0_REG), + .CH1_RX_ADC_CFG1 (CH1_RX_ADC_CFG1_REG), + .CH1_RX_ANA_CFG0 (CH1_RX_ANA_CFG0_REG), + .CH1_RX_ANA_CFG1 (CH1_RX_ANA_CFG1_REG), + .CH1_RX_ANA_CFG2 (CH1_RX_ANA_CFG2_REG), + .CH1_RX_APT_CFG0A (CH1_RX_APT_CFG0A_REG), + .CH1_RX_APT_CFG0B (CH1_RX_APT_CFG0B_REG), + .CH1_RX_APT_CFG10A (CH1_RX_APT_CFG10A_REG), + .CH1_RX_APT_CFG10B (CH1_RX_APT_CFG10B_REG), + .CH1_RX_APT_CFG11A (CH1_RX_APT_CFG11A_REG), + .CH1_RX_APT_CFG11B (CH1_RX_APT_CFG11B_REG), + .CH1_RX_APT_CFG12A (CH1_RX_APT_CFG12A_REG), + .CH1_RX_APT_CFG12B (CH1_RX_APT_CFG12B_REG), + .CH1_RX_APT_CFG13A (CH1_RX_APT_CFG13A_REG), + .CH1_RX_APT_CFG13B (CH1_RX_APT_CFG13B_REG), + .CH1_RX_APT_CFG14A (CH1_RX_APT_CFG14A_REG), + .CH1_RX_APT_CFG14B (CH1_RX_APT_CFG14B_REG), + .CH1_RX_APT_CFG15A (CH1_RX_APT_CFG15A_REG), + .CH1_RX_APT_CFG15B (CH1_RX_APT_CFG15B_REG), + .CH1_RX_APT_CFG16A (CH1_RX_APT_CFG16A_REG), + .CH1_RX_APT_CFG16B (CH1_RX_APT_CFG16B_REG), + .CH1_RX_APT_CFG17A (CH1_RX_APT_CFG17A_REG), + .CH1_RX_APT_CFG17B (CH1_RX_APT_CFG17B_REG), + .CH1_RX_APT_CFG18A (CH1_RX_APT_CFG18A_REG), + .CH1_RX_APT_CFG18B (CH1_RX_APT_CFG18B_REG), + .CH1_RX_APT_CFG19A (CH1_RX_APT_CFG19A_REG), + .CH1_RX_APT_CFG19B (CH1_RX_APT_CFG19B_REG), + .CH1_RX_APT_CFG1A (CH1_RX_APT_CFG1A_REG), + .CH1_RX_APT_CFG1B (CH1_RX_APT_CFG1B_REG), + .CH1_RX_APT_CFG20A (CH1_RX_APT_CFG20A_REG), + .CH1_RX_APT_CFG20B (CH1_RX_APT_CFG20B_REG), + .CH1_RX_APT_CFG21A (CH1_RX_APT_CFG21A_REG), + .CH1_RX_APT_CFG21B (CH1_RX_APT_CFG21B_REG), + .CH1_RX_APT_CFG22A (CH1_RX_APT_CFG22A_REG), + .CH1_RX_APT_CFG22B (CH1_RX_APT_CFG22B_REG), + .CH1_RX_APT_CFG23A (CH1_RX_APT_CFG23A_REG), + .CH1_RX_APT_CFG23B (CH1_RX_APT_CFG23B_REG), + .CH1_RX_APT_CFG24A (CH1_RX_APT_CFG24A_REG), + .CH1_RX_APT_CFG24B (CH1_RX_APT_CFG24B_REG), + .CH1_RX_APT_CFG25A (CH1_RX_APT_CFG25A_REG), + .CH1_RX_APT_CFG25B (CH1_RX_APT_CFG25B_REG), + .CH1_RX_APT_CFG26A (CH1_RX_APT_CFG26A_REG), + .CH1_RX_APT_CFG26B (CH1_RX_APT_CFG26B_REG), + .CH1_RX_APT_CFG27A (CH1_RX_APT_CFG27A_REG), + .CH1_RX_APT_CFG27B (CH1_RX_APT_CFG27B_REG), + .CH1_RX_APT_CFG28A (CH1_RX_APT_CFG28A_REG), + .CH1_RX_APT_CFG28B (CH1_RX_APT_CFG28B_REG), + .CH1_RX_APT_CFG2A (CH1_RX_APT_CFG2A_REG), + .CH1_RX_APT_CFG2B (CH1_RX_APT_CFG2B_REG), + .CH1_RX_APT_CFG3A (CH1_RX_APT_CFG3A_REG), + .CH1_RX_APT_CFG3B (CH1_RX_APT_CFG3B_REG), + .CH1_RX_APT_CFG4A (CH1_RX_APT_CFG4A_REG), + .CH1_RX_APT_CFG4B (CH1_RX_APT_CFG4B_REG), + .CH1_RX_APT_CFG5A (CH1_RX_APT_CFG5A_REG), + .CH1_RX_APT_CFG5B (CH1_RX_APT_CFG5B_REG), + .CH1_RX_APT_CFG6A (CH1_RX_APT_CFG6A_REG), + .CH1_RX_APT_CFG6B (CH1_RX_APT_CFG6B_REG), + .CH1_RX_APT_CFG7A (CH1_RX_APT_CFG7A_REG), + .CH1_RX_APT_CFG7B (CH1_RX_APT_CFG7B_REG), + .CH1_RX_APT_CFG8A (CH1_RX_APT_CFG8A_REG), + .CH1_RX_APT_CFG8B (CH1_RX_APT_CFG8B_REG), + .CH1_RX_APT_CFG9A (CH1_RX_APT_CFG9A_REG), + .CH1_RX_APT_CFG9B (CH1_RX_APT_CFG9B_REG), + .CH1_RX_APT_CTRL_CFG2 (CH1_RX_APT_CTRL_CFG2_REG), + .CH1_RX_APT_CTRL_CFG3 (CH1_RX_APT_CTRL_CFG3_REG), + .CH1_RX_CAL_CFG0A (CH1_RX_CAL_CFG0A_REG), + .CH1_RX_CAL_CFG0B (CH1_RX_CAL_CFG0B_REG), + .CH1_RX_CAL_CFG1A (CH1_RX_CAL_CFG1A_REG), + .CH1_RX_CAL_CFG1B (CH1_RX_CAL_CFG1B_REG), + .CH1_RX_CAL_CFG2A (CH1_RX_CAL_CFG2A_REG), + .CH1_RX_CAL_CFG2B (CH1_RX_CAL_CFG2B_REG), + .CH1_RX_CDR_CFG0A (CH1_RX_CDR_CFG0A_REG), + .CH1_RX_CDR_CFG0B (CH1_RX_CDR_CFG0B_REG), + .CH1_RX_CDR_CFG1A (CH1_RX_CDR_CFG1A_REG), + .CH1_RX_CDR_CFG1B (CH1_RX_CDR_CFG1B_REG), + .CH1_RX_CDR_CFG2A (CH1_RX_CDR_CFG2A_REG), + .CH1_RX_CDR_CFG2B (CH1_RX_CDR_CFG2B_REG), + .CH1_RX_CDR_CFG3A (CH1_RX_CDR_CFG3A_REG), + .CH1_RX_CDR_CFG3B (CH1_RX_CDR_CFG3B_REG), + .CH1_RX_CDR_CFG4A (CH1_RX_CDR_CFG4A_REG), + .CH1_RX_CDR_CFG4B (CH1_RX_CDR_CFG4B_REG), + .CH1_RX_CLKGN_CFG0 (CH1_RX_CLKGN_CFG0_REG), + .CH1_RX_CLKGN_CFG1 (CH1_RX_CLKGN_CFG1_REG), + .CH1_RX_CTLE_CFG0 (CH1_RX_CTLE_CFG0_REG), + .CH1_RX_CTLE_CFG1 (CH1_RX_CTLE_CFG1_REG), + .CH1_RX_CTLE_CFG2 (CH1_RX_CTLE_CFG2_REG), + .CH1_RX_CTLE_CFG3 (CH1_RX_CTLE_CFG3_REG), + .CH1_RX_DSP_CFG (CH1_RX_DSP_CFG_REG), + .CH1_RX_MON_CFG (CH1_RX_MON_CFG_REG), + .CH1_RX_PAD_CFG0 (CH1_RX_PAD_CFG0_REG), + .CH1_RX_PAD_CFG1 (CH1_RX_PAD_CFG1_REG), + .CH1_RX_PCS_CFG0 (CH1_RX_PCS_CFG0_REG), + .CH1_RX_PCS_CFG1 (CH1_RX_PCS_CFG1_REG), + .CH1_TX_ANA_CFG0 (CH1_TX_ANA_CFG0_REG), + .CH1_TX_ANA_CFG1 (CH1_TX_ANA_CFG1_REG), + .CH1_TX_ANA_CFG2 (CH1_TX_ANA_CFG2_REG), + .CH1_TX_ANA_CFG3 (CH1_TX_ANA_CFG3_REG), + .CH1_TX_ANA_CFG4 (CH1_TX_ANA_CFG4_REG), + .CH1_TX_CAL_CFG0 (CH1_TX_CAL_CFG0_REG), + .CH1_TX_CAL_CFG1 (CH1_TX_CAL_CFG1_REG), + .CH1_TX_DRV_CFG0 (CH1_TX_DRV_CFG0_REG), + .CH1_TX_DRV_CFG1 (CH1_TX_DRV_CFG1_REG), + .CH1_TX_DRV_CFG2 (CH1_TX_DRV_CFG2_REG), + .CH1_TX_DRV_CFG3 (CH1_TX_DRV_CFG3_REG), + .CH1_TX_DRV_CFG4 (CH1_TX_DRV_CFG4_REG), + .CH1_TX_DRV_CFG5 (CH1_TX_DRV_CFG5_REG), + .CH1_TX_LPBK_CFG0 (CH1_TX_LPBK_CFG0_REG), + .CH1_TX_LPBK_CFG1 (CH1_TX_LPBK_CFG1_REG), + .CH1_TX_PCS_CFG0 (CH1_TX_PCS_CFG0_REG), + .CH1_TX_PCS_CFG1 (CH1_TX_PCS_CFG1_REG), + .CH1_TX_PCS_CFG10 (CH1_TX_PCS_CFG10_REG), + .CH1_TX_PCS_CFG11 (CH1_TX_PCS_CFG11_REG), + .CH1_TX_PCS_CFG12 (CH1_TX_PCS_CFG12_REG), + .CH1_TX_PCS_CFG13 (CH1_TX_PCS_CFG13_REG), + .CH1_TX_PCS_CFG14 (CH1_TX_PCS_CFG14_REG), + .CH1_TX_PCS_CFG15 (CH1_TX_PCS_CFG15_REG), + .CH1_TX_PCS_CFG16 (CH1_TX_PCS_CFG16_REG), + .CH1_TX_PCS_CFG17 (CH1_TX_PCS_CFG17_REG), + .CH1_TX_PCS_CFG2 (CH1_TX_PCS_CFG2_REG), + .CH1_TX_PCS_CFG3 (CH1_TX_PCS_CFG3_REG), + .CH1_TX_PCS_CFG4 (CH1_TX_PCS_CFG4_REG), + .CH1_TX_PCS_CFG5 (CH1_TX_PCS_CFG5_REG), + .CH1_TX_PCS_CFG6 (CH1_TX_PCS_CFG6_REG), + .CH1_TX_PCS_CFG7 (CH1_TX_PCS_CFG7_REG), + .CH1_TX_PCS_CFG8 (CH1_TX_PCS_CFG8_REG), + .CH1_TX_PCS_CFG9 (CH1_TX_PCS_CFG9_REG), + .DRPEN_CFG (DRPEN_CFG_REG), + .FEC_CFG0 (FEC_CFG0_REG), + .FEC_CFG1 (FEC_CFG1_REG), + .FEC_CFG10 (FEC_CFG10_REG), + .FEC_CFG11 (FEC_CFG11_REG), + .FEC_CFG12 (FEC_CFG12_REG), + .FEC_CFG13 (FEC_CFG13_REG), + .FEC_CFG14 (FEC_CFG14_REG), + .FEC_CFG15 (FEC_CFG15_REG), + .FEC_CFG16 (FEC_CFG16_REG), + .FEC_CFG17 (FEC_CFG17_REG), + .FEC_CFG18 (FEC_CFG18_REG), + .FEC_CFG19 (FEC_CFG19_REG), + .FEC_CFG2 (FEC_CFG2_REG), + .FEC_CFG20 (FEC_CFG20_REG), + .FEC_CFG21 (FEC_CFG21_REG), + .FEC_CFG22 (FEC_CFG22_REG), + .FEC_CFG23 (FEC_CFG23_REG), + .FEC_CFG24 (FEC_CFG24_REG), + .FEC_CFG25 (FEC_CFG25_REG), + .FEC_CFG26 (FEC_CFG26_REG), + .FEC_CFG27 (FEC_CFG27_REG), + .FEC_CFG3 (FEC_CFG3_REG), + .FEC_CFG4 (FEC_CFG4_REG), + .FEC_CFG5 (FEC_CFG5_REG), + .FEC_CFG6 (FEC_CFG6_REG), + .FEC_CFG7 (FEC_CFG7_REG), + .FEC_CFG8 (FEC_CFG8_REG), + .FEC_CFG9 (FEC_CFG9_REG), + .PLL_CFG0 (PLL_CFG0_REG), + .PLL_CFG1 (PLL_CFG1_REG), + .PLL_CFG2 (PLL_CFG2_REG), + .PLL_CFG3 (PLL_CFG3_REG), + .PLL_CFG4 (PLL_CFG4_REG), + .PLL_CFG5 (PLL_CFG5_REG), + .PLL_CFG6 (PLL_CFG6_REG), + .PLL_CRS_CTRL_CFG0 (PLL_CRS_CTRL_CFG0_REG), + .PLL_CRS_CTRL_CFG1 (PLL_CRS_CTRL_CFG1_REG), + .PLL_IPS_PIN_EN (PLL_IPS_PIN_EN_REG), + .PLL_IPS_REFCLK_SEL (PLL_IPS_REFCLK_SEL_REG), + .RCALSAP_TESTEN (RCALSAP_TESTEN_REG), + .RCAL_APROBE (RCAL_APROBE_REG), + .RST_CFG (RST_CFG_REG), + .RST_PLL_CFG0 (RST_PLL_CFG0_REG), + .SAP_CFG0 (SAP_CFG0_REG), + .SDM_CFG0 (SDM_CFG0_REG), + .SDM_CFG1 (SDM_CFG1_REG), + .SDM_CFG2 (SDM_CFG2_REG), + .SDM_SEED_CFG0 (SDM_SEED_CFG0_REG), + .SDM_SEED_CFG1 (SDM_SEED_CFG1_REG), + .SIM_DEVICE (SIM_DEVICE_REG), + .CH0_AXISTDATA (CH0_AXISTDATA_out), + .CH0_AXISTLAST (CH0_AXISTLAST_out), + .CH0_AXISTVALID (CH0_AXISTVALID_out), + .CH0_DMONITOROUT (CH0_DMONITOROUT_out), + .CH0_DMONITOROUTCLK (CH0_DMONITOROUTCLK_out), + //.CH0_GTMTXN (CH0_GTMTXN_out), + //.CH0_GTMTXP (CH0_GTMTXP_out), + .CH0_GTMTXN (CH0_GTMTXN_integer), + .CH0_GTMTXP (CH0_GTMTXP_integer), + .CH0_PCSRSVDOUT (CH0_PCSRSVDOUT_out), + .CH0_PCSSCANOUT (CH0_PCSSCANOUT_out), + .CH0_PMARSVDOUT (CH0_PMARSVDOUT_out), + .CH0_PMASCANOUT (CH0_PMASCANOUT_out), + .CH0_RESETEXCEPTION (CH0_RESETEXCEPTION_out), + .CH0_RXBUFSTATUS (CH0_RXBUFSTATUS_out), + .CH0_RXDATA (CH0_RXDATA_out), + .CH0_RXDATAFLAGS (CH0_RXDATAFLAGS_out), + .CH0_RXDATAISAM (CH0_RXDATAISAM_out), + .CH0_RXDATASTART (CH0_RXDATASTART_out), + .CH0_RXOUTCLK (CH0_RXOUTCLK_out), + .CH0_RXPMARESETDONE (CH0_RXPMARESETDONE_out), + .CH0_RXPRBSERR (CH0_RXPRBSERR_out), + .CH0_RXPRBSLOCKED (CH0_RXPRBSLOCKED_out), + .CH0_RXPRGDIVRESETDONE (CH0_RXPRGDIVRESETDONE_out), + .CH0_RXPROGDIVCLK (CH0_RXPROGDIVCLK_out), + .CH0_RXRESETDONE (CH0_RXRESETDONE_out), + .CH0_TXBUFSTATUS (CH0_TXBUFSTATUS_out), + .CH0_TXOUTCLK (CH0_TXOUTCLK_out), + .CH0_TXPMARESETDONE (CH0_TXPMARESETDONE_out), + .CH0_TXPRGDIVRESETDONE (CH0_TXPRGDIVRESETDONE_out), + .CH0_TXPROGDIVCLK (CH0_TXPROGDIVCLK_out), + .CH0_TXRESETDONE (CH0_TXRESETDONE_out), + .CH1_AXISTDATA (CH1_AXISTDATA_out), + .CH1_AXISTLAST (CH1_AXISTLAST_out), + .CH1_AXISTVALID (CH1_AXISTVALID_out), + .CH1_DMONITOROUT (CH1_DMONITOROUT_out), + .CH1_DMONITOROUTCLK (CH1_DMONITOROUTCLK_out), + //.CH1_GTMTXN (CH1_GTMTXN_out), + //.CH1_GTMTXP (CH1_GTMTXP_out), + .CH1_GTMTXN (CH1_GTMTXN_integer), + .CH1_GTMTXP (CH1_GTMTXP_integer), + .CH1_PCSRSVDOUT (CH1_PCSRSVDOUT_out), + .CH1_PCSSCANOUT (CH1_PCSSCANOUT_out), + .CH1_PMARSVDOUT (CH1_PMARSVDOUT_out), + .CH1_PMASCANOUT (CH1_PMASCANOUT_out), + .CH1_RESETEXCEPTION (CH1_RESETEXCEPTION_out), + .CH1_RXBUFSTATUS (CH1_RXBUFSTATUS_out), + .CH1_RXDATA (CH1_RXDATA_out), + .CH1_RXDATAFLAGS (CH1_RXDATAFLAGS_out), + .CH1_RXDATAISAM (CH1_RXDATAISAM_out), + .CH1_RXDATASTART (CH1_RXDATASTART_out), + .CH1_RXOUTCLK (CH1_RXOUTCLK_out), + .CH1_RXPMARESETDONE (CH1_RXPMARESETDONE_out), + .CH1_RXPRBSERR (CH1_RXPRBSERR_out), + .CH1_RXPRBSLOCKED (CH1_RXPRBSLOCKED_out), + .CH1_RXPRGDIVRESETDONE (CH1_RXPRGDIVRESETDONE_out), + .CH1_RXPROGDIVCLK (CH1_RXPROGDIVCLK_out), + .CH1_RXRESETDONE (CH1_RXRESETDONE_out), + .CH1_TXBUFSTATUS (CH1_TXBUFSTATUS_out), + .CH1_TXOUTCLK (CH1_TXOUTCLK_out), + .CH1_TXPMARESETDONE (CH1_TXPMARESETDONE_out), + .CH1_TXPRGDIVRESETDONE (CH1_TXPRGDIVRESETDONE_out), + .CH1_TXPROGDIVCLK (CH1_TXPROGDIVCLK_out), + .CH1_TXRESETDONE (CH1_TXRESETDONE_out), + .CLKTESTSIG2PAD (CLKTESTSIG2PAD_out), + .DMONITOROUTPLLCLK (DMONITOROUTPLLCLK_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .FECRX0ALIGNED (FECRX0ALIGNED_out), + .FECRX0CORRCWINC (FECRX0CORRCWINC_out), + .FECRX0CWINC (FECRX0CWINC_out), + .FECRX0UNCORRCWINC (FECRX0UNCORRCWINC_out), + .FECRX1ALIGNED (FECRX1ALIGNED_out), + .FECRX1CORRCWINC (FECRX1CORRCWINC_out), + .FECRX1CWINC (FECRX1CWINC_out), + .FECRX1UNCORRCWINC (FECRX1UNCORRCWINC_out), + .FECRXLN0BITERR0TO1INC (FECRXLN0BITERR0TO1INC_out), + .FECRXLN0BITERR1TO0INC (FECRXLN0BITERR1TO0INC_out), + .FECRXLN0DLY (FECRXLN0DLY_out), + .FECRXLN0ERRCNTINC (FECRXLN0ERRCNTINC_out), + .FECRXLN0MAPPING (FECRXLN0MAPPING_out), + .FECRXLN1BITERR0TO1INC (FECRXLN1BITERR0TO1INC_out), + .FECRXLN1BITERR1TO0INC (FECRXLN1BITERR1TO0INC_out), + .FECRXLN1DLY (FECRXLN1DLY_out), + .FECRXLN1ERRCNTINC (FECRXLN1ERRCNTINC_out), + .FECRXLN1MAPPING (FECRXLN1MAPPING_out), + .FECRXLN2BITERR0TO1INC (FECRXLN2BITERR0TO1INC_out), + .FECRXLN2BITERR1TO0INC (FECRXLN2BITERR1TO0INC_out), + .FECRXLN2DLY (FECRXLN2DLY_out), + .FECRXLN2ERRCNTINC (FECRXLN2ERRCNTINC_out), + .FECRXLN2MAPPING (FECRXLN2MAPPING_out), + .FECRXLN3BITERR0TO1INC (FECRXLN3BITERR0TO1INC_out), + .FECRXLN3BITERR1TO0INC (FECRXLN3BITERR1TO0INC_out), + .FECRXLN3DLY (FECRXLN3DLY_out), + .FECRXLN3ERRCNTINC (FECRXLN3ERRCNTINC_out), + .FECRXLN3MAPPING (FECRXLN3MAPPING_out), + .FECSCANOUT (FECSCANOUT_out), + .FECTRXLN0LOCK (FECTRXLN0LOCK_out), + .FECTRXLN1LOCK (FECTRXLN1LOCK_out), + .FECTRXLN2LOCK (FECTRXLN2LOCK_out), + .FECTRXLN3LOCK (FECTRXLN3LOCK_out), + .GTPOWERGOOD (GTPOWERGOOD_out), + .PLLFBCLKLOST (PLLFBCLKLOST_out), + .PLLLOCK (PLLLOCK_out), + .PLLREFCLKLOST (PLLREFCLKLOST_out), + .PLLREFCLKMONITOR (PLLREFCLKMONITOR_out), + .PLLRESETDONE (PLLRESETDONE_out), + .PLLRSVDOUT (PLLRSVDOUT_out), + .PLLSCANOUT (PLLSCANOUT_out), + .RCALCMP (RCALCMP_out), + .RCALOUT (RCALOUT_out), + .REFCLK2BUFG (REFCLK2BUFG_out), + .REFCLKPDB_SA (REFCLKPDB_SA_out), + .RXRECCLK0 (RXRECCLK0_out), + .RXRECCLK1 (RXRECCLK1_out), + .BGBYPASSB (BGBYPASSB_in), + .BGMONITORENB (BGMONITORENB_in), + .BGPDB (BGPDB_in), + .BGRCALOVRD (BGRCALOVRD_in), + .BGRCALOVRDENB (BGRCALOVRDENB_in), + .CH0_AXISEN (CH0_AXISEN_in), + .CH0_AXISRST (CH0_AXISRST_in), + .CH0_AXISTRDY (CH0_AXISTRDY_in), + .CH0_BSRSERIAL (CH0_BSRSERIAL_in), + .CH0_CFGRESET (CH0_CFGRESET_in), + .CH0_DMONFIFORESET (CH0_DMONFIFORESET_in), + .CH0_DMONITORCLK (CH0_DMONITORCLK_in), + //.CH0_GTMRXN (CH0_GTMRXN_in), + //.CH0_GTMRXP (CH0_GTMRXP_in), + .CH0_GTMRXN (CH0_GTMRXN_integer), + .CH0_GTMRXP (CH0_GTMRXP_integer), + .CH0_GTRXRESET (CH0_GTRXRESET_in), + .CH0_GTTXRESET (CH0_GTTXRESET_in), + .CH0_LOOPBACK (CH0_LOOPBACK_in), + .CH0_PCSRSVDIN (CH0_PCSRSVDIN_in), + .CH0_PCSSCANCLK (CH0_PCSSCANCLK_in), + .CH0_PCSSCANENB (CH0_PCSSCANENB_in), + .CH0_PCSSCANIN (CH0_PCSSCANIN_in), + .CH0_PCSSCANMODEB (CH0_PCSSCANMODEB_in), + .CH0_PCSSCANRSTB (CH0_PCSSCANRSTB_in), + .CH0_PCSSCANRSTEN (CH0_PCSSCANRSTEN_in), + .CH0_PMARSVDIN (CH0_PMARSVDIN_in), + .CH0_PMASCANCLK (CH0_PMASCANCLK_in), + .CH0_PMASCANENB (CH0_PMASCANENB_in), + .CH0_PMASCANIN (CH0_PMASCANIN_in), + .CH0_PMASCANMODEB (CH0_PMASCANMODEB_in), + .CH0_PMASCANRSTEN (CH0_PMASCANRSTEN_in), + .CH0_RESETOVRD (CH0_RESETOVRD_in), + .CH0_RXADAPTRESET (CH0_RXADAPTRESET_in), + .CH0_RXADCCALRESET (CH0_RXADCCALRESET_in), + .CH0_RXADCCLKGENRESET (CH0_RXADCCLKGENRESET_in), + .CH0_RXBUFRESET (CH0_RXBUFRESET_in), + .CH0_RXCDRFREQOS (CH0_RXCDRFREQOS_in), + .CH0_RXCDRFRRESET (CH0_RXCDRFRRESET_in), + .CH0_RXCDRHOLD (CH0_RXCDRHOLD_in), + .CH0_RXCDRINCPCTRL (CH0_RXCDRINCPCTRL_in), + .CH0_RXCDROVRDEN (CH0_RXCDROVRDEN_in), + .CH0_RXCDRPHRESET (CH0_RXCDRPHRESET_in), + .CH0_RXDFERESET (CH0_RXDFERESET_in), + .CH0_RXDSPRESET (CH0_RXDSPRESET_in), + .CH0_RXEQTRAINING (CH0_RXEQTRAINING_in), + .CH0_RXEYESCANRESET (CH0_RXEYESCANRESET_in), + .CH0_RXFECRESET (CH0_RXFECRESET_in), + .CH0_RXOUTCLKSEL (CH0_RXOUTCLKSEL_in), + .CH0_RXPCSRESET (CH0_RXPCSRESET_in), + .CH0_RXPCSRESETMASK (CH0_RXPCSRESETMASK_in), + .CH0_RXPMARESET (CH0_RXPMARESET_in), + .CH0_RXPMARESETMASK (CH0_RXPMARESETMASK_in), + .CH0_RXPOLARITY (CH0_RXPOLARITY_in), + .CH0_RXPRBSCNTSTOP (CH0_RXPRBSCNTSTOP_in), + .CH0_RXPRBSCSCNTRST (CH0_RXPRBSCSCNTRST_in), + .CH0_RXPRBSPTN (CH0_RXPRBSPTN_in), + .CH0_RXPROGDIVRESET (CH0_RXPROGDIVRESET_in), + .CH0_RXQPRBSEN (CH0_RXQPRBSEN_in), + .CH0_RXRESETMODE (CH0_RXRESETMODE_in), + .CH0_RXSPCSEQADV (CH0_RXSPCSEQADV_in), + .CH0_RXUSRCLK (CH0_RXUSRCLK_in), + .CH0_RXUSRCLK2 (CH0_RXUSRCLK2_in), + .CH0_RXUSRRDY (CH0_RXUSRRDY_in), + .CH0_RXUSRSTART (CH0_RXUSRSTART_in), + .CH0_RXUSRSTOP (CH0_RXUSRSTOP_in), + .CH0_TSTCLK0 (CH0_TSTCLK0_in), + .CH0_TSTCLK1 (CH0_TSTCLK1_in), + .CH0_TXCKALRESET (CH0_TXCKALRESET_in), + .CH0_TXCTLFIRDAT (CH0_TXCTLFIRDAT_in), + .CH0_TXDATA (CH0_TXDATA_in), + .CH0_TXDATASTART (CH0_TXDATASTART_in), + .CH0_TXDRVAMP (CH0_TXDRVAMP_in), + .CH0_TXEMPMAIN (CH0_TXEMPMAIN_in), + .CH0_TXEMPPOST (CH0_TXEMPPOST_in), + .CH0_TXEMPPRE (CH0_TXEMPPRE_in), + .CH0_TXEMPPRE2 (CH0_TXEMPPRE2_in), + .CH0_TXFECRESET (CH0_TXFECRESET_in), + .CH0_TXINHIBIT (CH0_TXINHIBIT_in), + .CH0_TXMUXDCDEXHOLD (CH0_TXMUXDCDEXHOLD_in), + .CH0_TXMUXDCDORWREN (CH0_TXMUXDCDORWREN_in), + .CH0_TXOUTCLKSEL (CH0_TXOUTCLKSEL_in), + .CH0_TXPCSRESET (CH0_TXPCSRESET_in), + .CH0_TXPCSRESETMASK (CH0_TXPCSRESETMASK_in), + .CH0_TXPMARESET (CH0_TXPMARESET_in), + .CH0_TXPMARESETMASK (CH0_TXPMARESETMASK_in), + .CH0_TXPOLARITY (CH0_TXPOLARITY_in), + .CH0_TXPRBSINERR (CH0_TXPRBSINERR_in), + .CH0_TXPRBSPTN (CH0_TXPRBSPTN_in), + .CH0_TXPROGDIVRESET (CH0_TXPROGDIVRESET_in), + .CH0_TXQPRBSEN (CH0_TXQPRBSEN_in), + .CH0_TXRESETMODE (CH0_TXRESETMODE_in), + .CH0_TXSPCSEQADV (CH0_TXSPCSEQADV_in), + .CH0_TXUSRCLK (CH0_TXUSRCLK_in), + .CH0_TXUSRCLK2 (CH0_TXUSRCLK2_in), + .CH0_TXUSRRDY (CH0_TXUSRRDY_in), + .CH1_AXISEN (CH1_AXISEN_in), + .CH1_AXISRST (CH1_AXISRST_in), + .CH1_AXISTRDY (CH1_AXISTRDY_in), + .CH1_BSRSERIAL (CH1_BSRSERIAL_in), + .CH1_CFGRESET (CH1_CFGRESET_in), + .CH1_DMONFIFORESET (CH1_DMONFIFORESET_in), + .CH1_DMONITORCLK (CH1_DMONITORCLK_in), + //.CH1_GTMRXN (CH1_GTMRXN_in), + //.CH1_GTMRXP (CH1_GTMRXP_in), + .CH1_GTMRXN (CH1_GTMRXN_integer), + .CH1_GTMRXP (CH1_GTMRXP_integer), + .CH1_GTRXRESET (CH1_GTRXRESET_in), + .CH1_GTTXRESET (CH1_GTTXRESET_in), + .CH1_LOOPBACK (CH1_LOOPBACK_in), + .CH1_PCSRSVDIN (CH1_PCSRSVDIN_in), + .CH1_PCSSCANCLK (CH1_PCSSCANCLK_in), + .CH1_PCSSCANENB (CH1_PCSSCANENB_in), + .CH1_PCSSCANIN (CH1_PCSSCANIN_in), + .CH1_PCSSCANMODEB (CH1_PCSSCANMODEB_in), + .CH1_PCSSCANRSTB (CH1_PCSSCANRSTB_in), + .CH1_PCSSCANRSTEN (CH1_PCSSCANRSTEN_in), + .CH1_PMARSVDIN (CH1_PMARSVDIN_in), + .CH1_PMASCANCLK (CH1_PMASCANCLK_in), + .CH1_PMASCANENB (CH1_PMASCANENB_in), + .CH1_PMASCANIN (CH1_PMASCANIN_in), + .CH1_PMASCANMODEB (CH1_PMASCANMODEB_in), + .CH1_PMASCANRSTEN (CH1_PMASCANRSTEN_in), + .CH1_RESETOVRD (CH1_RESETOVRD_in), + .CH1_RXADAPTRESET (CH1_RXADAPTRESET_in), + .CH1_RXADCCALRESET (CH1_RXADCCALRESET_in), + .CH1_RXADCCLKGENRESET (CH1_RXADCCLKGENRESET_in), + .CH1_RXBUFRESET (CH1_RXBUFRESET_in), + .CH1_RXCDRFREQOS (CH1_RXCDRFREQOS_in), + .CH1_RXCDRFRRESET (CH1_RXCDRFRRESET_in), + .CH1_RXCDRHOLD (CH1_RXCDRHOLD_in), + .CH1_RXCDRINCPCTRL (CH1_RXCDRINCPCTRL_in), + .CH1_RXCDROVRDEN (CH1_RXCDROVRDEN_in), + .CH1_RXCDRPHRESET (CH1_RXCDRPHRESET_in), + .CH1_RXDFERESET (CH1_RXDFERESET_in), + .CH1_RXDSPRESET (CH1_RXDSPRESET_in), + .CH1_RXEQTRAINING (CH1_RXEQTRAINING_in), + .CH1_RXEYESCANRESET (CH1_RXEYESCANRESET_in), + .CH1_RXFECRESET (CH1_RXFECRESET_in), + .CH1_RXOUTCLKSEL (CH1_RXOUTCLKSEL_in), + .CH1_RXPCSRESET (CH1_RXPCSRESET_in), + .CH1_RXPCSRESETMASK (CH1_RXPCSRESETMASK_in), + .CH1_RXPMARESET (CH1_RXPMARESET_in), + .CH1_RXPMARESETMASK (CH1_RXPMARESETMASK_in), + .CH1_RXPOLARITY (CH1_RXPOLARITY_in), + .CH1_RXPRBSCNTSTOP (CH1_RXPRBSCNTSTOP_in), + .CH1_RXPRBSCSCNTRST (CH1_RXPRBSCSCNTRST_in), + .CH1_RXPRBSPTN (CH1_RXPRBSPTN_in), + .CH1_RXPROGDIVRESET (CH1_RXPROGDIVRESET_in), + .CH1_RXQPRBSEN (CH1_RXQPRBSEN_in), + .CH1_RXRESETMODE (CH1_RXRESETMODE_in), + .CH1_RXSPCSEQADV (CH1_RXSPCSEQADV_in), + .CH1_RXUSRCLK (CH1_RXUSRCLK_in), + .CH1_RXUSRCLK2 (CH1_RXUSRCLK2_in), + .CH1_RXUSRRDY (CH1_RXUSRRDY_in), + .CH1_RXUSRSTART (CH1_RXUSRSTART_in), + .CH1_RXUSRSTOP (CH1_RXUSRSTOP_in), + .CH1_TSTCLK0 (CH1_TSTCLK0_in), + .CH1_TSTCLK1 (CH1_TSTCLK1_in), + .CH1_TXCKALRESET (CH1_TXCKALRESET_in), + .CH1_TXCTLFIRDAT (CH1_TXCTLFIRDAT_in), + .CH1_TXDATA (CH1_TXDATA_in), + .CH1_TXDATASTART (CH1_TXDATASTART_in), + .CH1_TXDRVAMP (CH1_TXDRVAMP_in), + .CH1_TXEMPMAIN (CH1_TXEMPMAIN_in), + .CH1_TXEMPPOST (CH1_TXEMPPOST_in), + .CH1_TXEMPPRE (CH1_TXEMPPRE_in), + .CH1_TXEMPPRE2 (CH1_TXEMPPRE2_in), + .CH1_TXFECRESET (CH1_TXFECRESET_in), + .CH1_TXINHIBIT (CH1_TXINHIBIT_in), + .CH1_TXMUXDCDEXHOLD (CH1_TXMUXDCDEXHOLD_in), + .CH1_TXMUXDCDORWREN (CH1_TXMUXDCDORWREN_in), + .CH1_TXOUTCLKSEL (CH1_TXOUTCLKSEL_in), + .CH1_TXPCSRESET (CH1_TXPCSRESET_in), + .CH1_TXPCSRESETMASK (CH1_TXPCSRESETMASK_in), + .CH1_TXPMARESET (CH1_TXPMARESET_in), + .CH1_TXPMARESETMASK (CH1_TXPMARESETMASK_in), + .CH1_TXPOLARITY (CH1_TXPOLARITY_in), + .CH1_TXPRBSINERR (CH1_TXPRBSINERR_in), + .CH1_TXPRBSPTN (CH1_TXPRBSPTN_in), + .CH1_TXPROGDIVRESET (CH1_TXPROGDIVRESET_in), + .CH1_TXQPRBSEN (CH1_TXQPRBSEN_in), + .CH1_TXRESETMODE (CH1_TXRESETMODE_in), + .CH1_TXSPCSEQADV (CH1_TXSPCSEQADV_in), + .CH1_TXUSRCLK (CH1_TXUSRCLK_in), + .CH1_TXUSRCLK2 (CH1_TXUSRCLK2_in), + .CH1_TXUSRRDY (CH1_TXUSRRDY_in), + .CLKTESTSIG (CLKTESTSIG_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPRST (DRPRST_in), + .DRPWE (DRPWE_in), + .FECCTRLRX0BITSLIPFS (FECCTRLRX0BITSLIPFS_in), + .FECCTRLRX1BITSLIPFS (FECCTRLRX1BITSLIPFS_in), + .FECSCANCLK (FECSCANCLK_in), + .FECSCANENB (FECSCANENB_in), + .FECSCANIN (FECSCANIN_in), + .FECSCANMODEB (FECSCANMODEB_in), + .FECSCANRSTB (FECSCANRSTB_in), + .GTGREFCLK2PLL (GTGREFCLK2PLL_in), + .GTNORTHREFCLK (GTNORTHREFCLK_in), + .GTREFCLK (GTREFCLK_in), + .GTREFCLKPD (GTREFCLKPD_in), + .GTSOUTHREFCLK (GTSOUTHREFCLK_in), + .PLLFBDIV (PLLFBDIV_in), + .PLLMONCLK (PLLMONCLK_in), + .PLLPD (PLLPD_in), + .PLLREFCLKSEL (PLLREFCLKSEL_in), + .PLLRESET (PLLRESET_in), + .PLLRESETBYPASSMODE (PLLRESETBYPASSMODE_in), + .PLLRESETMASK (PLLRESETMASK_in), + .PLLRSVDIN (PLLRSVDIN_in), + .PLLSCANCLK (PLLSCANCLK_in), + .PLLSCANENB (PLLSCANENB_in), + .PLLSCANIN (PLLSCANIN_in), + .PLLSCANMODEB (PLLSCANMODEB_in), + .PLLSCANRSTEN (PLLSCANRSTEN_in), + .RCALENB (RCALENB_in), + .RCALSEL (RCALSEL_in), + .REFCLK2HROW (REFCLK2HROW_in), + .SDMDATA (SDMDATA_in), + .SDMTOGGLE (SDMTOGGLE_in), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_XECLIB + specify + (CH0_DMONITORCLK => CH0_DMONITOROUT[0]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[10]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[11]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[12]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[13]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[14]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[15]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[16]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[17]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[18]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[19]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[1]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[20]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[21]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[22]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[23]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[24]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[25]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[26]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[27]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[28]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[29]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[2]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[30]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[31]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[3]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[4]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[5]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[6]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[7]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[8]) = (0:0:0, 0:0:0); + (CH0_DMONITORCLK => CH0_DMONITOROUT[9]) = (0:0:0, 0:0:0); + (CH0_RXUSRCLK2 => CH0_RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATAFLAGS[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATAFLAGS[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATAFLAGS[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATAFLAGS[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATAISAM) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATASTART) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[100]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[101]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[102]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[103]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[104]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[105]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[106]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[107]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[108]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[109]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[110]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[111]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[112]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[113]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[114]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[115]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[116]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[117]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[118]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[119]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[120]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[121]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[122]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[123]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[124]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[125]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[126]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[127]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[128]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[129]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[130]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[131]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[132]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[133]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[134]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[135]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[136]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[137]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[138]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[139]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[140]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[141]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[142]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[143]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[144]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[145]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[146]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[147]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[148]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[149]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[150]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[151]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[152]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[153]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[154]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[155]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[156]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[157]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[158]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[159]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[15]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[160]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[161]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[162]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[163]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[164]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[165]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[166]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[167]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[168]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[169]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[16]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[170]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[171]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[172]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[173]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[174]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[175]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[176]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[177]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[178]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[179]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[17]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[180]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[181]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[182]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[183]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[184]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[185]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[186]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[187]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[188]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[189]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[18]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[190]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[191]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[192]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[193]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[194]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[195]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[196]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[197]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[198]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[199]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[19]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[200]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[201]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[202]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[203]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[204]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[205]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[206]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[207]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[208]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[209]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[20]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[210]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[211]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[212]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[213]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[214]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[215]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[216]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[217]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[218]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[219]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[21]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[220]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[221]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[222]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[223]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[224]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[225]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[226]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[227]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[228]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[229]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[22]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[230]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[231]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[232]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[233]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[234]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[235]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[236]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[237]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[238]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[239]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[23]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[240]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[241]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[242]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[243]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[244]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[245]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[246]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[247]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[248]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[249]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[24]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[250]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[251]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[252]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[253]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[254]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[255]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[25]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[26]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[27]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[28]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[29]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[30]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[31]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[32]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[33]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[34]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[35]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[36]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[37]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[38]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[39]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[40]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[41]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[42]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[43]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[44]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[45]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[46]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[47]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[48]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[49]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[50]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[51]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[52]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[53]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[54]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[55]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[56]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[57]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[58]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[59]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[60]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[61]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[62]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[63]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[64]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[65]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[66]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[67]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[68]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[69]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[70]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[71]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[72]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[73]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[74]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[75]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[76]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[77]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[78]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[79]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[80]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[81]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[82]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[83]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[84]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[85]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[86]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[87]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[88]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[89]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[90]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[91]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[92]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[93]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[94]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[95]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[96]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[97]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[98]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[99]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXDATA[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXPRBSERR) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXPRBSLOCKED) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH0_RXRESETDONE) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATAFLAGS[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATAFLAGS[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATAFLAGS[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATAFLAGS[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATAISAM) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATASTART) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[100]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[101]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[102]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[103]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[104]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[105]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[106]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[107]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[108]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[109]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[110]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[111]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[112]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[113]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[114]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[115]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[116]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[117]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[118]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[119]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[120]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[121]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[122]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[123]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[124]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[125]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[126]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[127]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[128]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[129]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[130]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[131]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[132]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[133]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[134]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[135]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[136]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[137]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[138]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[139]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[140]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[141]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[142]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[143]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[144]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[145]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[146]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[147]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[148]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[149]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[150]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[151]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[152]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[153]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[154]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[155]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[156]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[157]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[158]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[159]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[15]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[160]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[161]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[162]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[163]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[164]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[165]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[166]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[167]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[168]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[169]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[16]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[170]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[171]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[172]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[173]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[174]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[175]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[176]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[177]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[178]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[179]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[17]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[180]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[181]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[182]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[183]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[184]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[185]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[186]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[187]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[188]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[189]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[18]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[190]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[191]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[192]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[193]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[194]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[195]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[196]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[197]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[198]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[199]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[19]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[200]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[201]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[202]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[203]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[204]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[205]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[206]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[207]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[208]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[209]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[20]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[210]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[211]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[212]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[213]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[214]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[215]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[216]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[217]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[218]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[219]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[21]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[220]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[221]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[222]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[223]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[224]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[225]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[226]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[227]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[228]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[229]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[22]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[230]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[231]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[232]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[233]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[234]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[235]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[236]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[237]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[238]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[239]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[23]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[240]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[241]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[242]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[243]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[244]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[245]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[246]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[247]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[248]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[249]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[24]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[250]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[251]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[252]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[253]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[254]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[255]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[25]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[26]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[27]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[28]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[29]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[30]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[31]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[32]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[33]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[34]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[35]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[36]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[37]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[38]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[39]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[40]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[41]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[42]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[43]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[44]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[45]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[46]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[47]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[48]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[49]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[50]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[51]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[52]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[53]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[54]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[55]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[56]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[57]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[58]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[59]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[60]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[61]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[62]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[63]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[64]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[65]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[66]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[67]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[68]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[69]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[70]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[71]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[72]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[73]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[74]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[75]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[76]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[77]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[78]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[79]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[80]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[81]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[82]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[83]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[84]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[85]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[86]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[87]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[88]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[89]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[90]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[91]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[92]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[93]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[94]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[95]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[96]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[97]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[98]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[99]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXDATA[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXPRBSERR) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXPRBSLOCKED) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => CH1_RXRESETDONE) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX0ALIGNED) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX0CORRCWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX0CWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX0UNCORRCWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX1ALIGNED) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX1CORRCWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX1CWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRX1UNCORRCWINC) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0DLY[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0MAPPING[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN0MAPPING[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1DLY[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1MAPPING[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN1MAPPING[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2DLY[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2MAPPING[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN2MAPPING[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[10]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[11]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[12]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[13]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[14]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[4]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[5]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[6]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[7]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[8]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3DLY[9]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3MAPPING[0]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECRXLN3MAPPING[1]) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECTRXLN0LOCK) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECTRXLN1LOCK) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECTRXLN2LOCK) = (100:100:100, 100:100:100); + (CH0_RXUSRCLK2 => FECTRXLN3LOCK) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH0_TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH0_TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH0_TXRESETDONE) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH1_TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH1_TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH0_TXUSRCLK2 => CH1_TXRESETDONE) = (100:100:100, 100:100:100); + (CH1_DMONITORCLK => CH1_DMONITOROUT[0]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[10]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[11]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[12]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[13]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[14]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[15]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[16]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[17]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[18]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[19]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[1]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[20]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[21]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[22]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[23]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[24]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[25]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[26]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[27]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[28]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[29]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[2]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[30]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[31]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[3]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[4]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[5]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[6]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[7]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[8]) = (0:0:0, 0:0:0); + (CH1_DMONITORCLK => CH1_DMONITOROUT[9]) = (0:0:0, 0:0:0); + (CH1_RXUSRCLK2 => CH1_RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATAFLAGS[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATAFLAGS[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATAFLAGS[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATAFLAGS[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATAISAM) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATASTART) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[100]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[101]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[102]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[103]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[104]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[105]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[106]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[107]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[108]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[109]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[10]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[110]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[111]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[112]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[113]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[114]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[115]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[116]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[117]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[118]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[119]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[11]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[120]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[121]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[122]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[123]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[124]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[125]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[126]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[127]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[128]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[129]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[12]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[130]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[131]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[132]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[133]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[134]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[135]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[136]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[137]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[138]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[139]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[13]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[140]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[141]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[142]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[143]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[144]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[145]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[146]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[147]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[148]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[149]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[14]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[150]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[151]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[152]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[153]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[154]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[155]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[156]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[157]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[158]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[159]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[15]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[160]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[161]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[162]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[163]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[164]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[165]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[166]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[167]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[168]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[169]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[16]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[170]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[171]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[172]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[173]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[174]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[175]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[176]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[177]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[178]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[179]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[17]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[180]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[181]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[182]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[183]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[184]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[185]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[186]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[187]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[188]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[189]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[18]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[190]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[191]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[192]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[193]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[194]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[195]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[196]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[197]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[198]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[199]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[19]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[200]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[201]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[202]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[203]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[204]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[205]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[206]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[207]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[208]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[209]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[20]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[210]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[211]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[212]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[213]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[214]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[215]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[216]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[217]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[218]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[219]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[21]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[220]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[221]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[222]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[223]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[224]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[225]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[226]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[227]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[228]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[229]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[22]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[230]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[231]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[232]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[233]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[234]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[235]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[236]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[237]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[238]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[239]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[23]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[240]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[241]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[242]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[243]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[244]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[245]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[246]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[247]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[248]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[249]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[24]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[250]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[251]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[252]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[253]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[254]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[255]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[25]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[26]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[27]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[28]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[29]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[30]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[31]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[32]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[33]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[34]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[35]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[36]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[37]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[38]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[39]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[40]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[41]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[42]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[43]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[44]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[45]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[46]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[47]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[48]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[49]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[50]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[51]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[52]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[53]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[54]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[55]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[56]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[57]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[58]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[59]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[60]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[61]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[62]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[63]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[64]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[65]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[66]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[67]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[68]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[69]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[70]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[71]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[72]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[73]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[74]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[75]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[76]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[77]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[78]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[79]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[80]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[81]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[82]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[83]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[84]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[85]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[86]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[87]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[88]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[89]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[8]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[90]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[91]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[92]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[93]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[94]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[95]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[96]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[97]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[98]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[99]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXDATA[9]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXPRBSERR) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXPRBSLOCKED) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => CH1_RXRESETDONE) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRX1ALIGNED) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRX1CORRCWINC) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRX1CWINC) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRX1UNCORRCWINC) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[10]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[11]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[12]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[13]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[14]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[8]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2DLY[9]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2MAPPING[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN2MAPPING[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR0TO1INC[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3BITERR1TO0INC[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[10]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[11]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[12]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[13]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[14]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[4]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[5]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[6]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[7]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[8]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3DLY[9]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3ERRCNTINC[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3ERRCNTINC[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3ERRCNTINC[2]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3ERRCNTINC[3]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3MAPPING[0]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECRXLN3MAPPING[1]) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECTRXLN2LOCK) = (100:100:100, 100:100:100); + (CH1_RXUSRCLK2 => FECTRXLN3LOCK) = (100:100:100, 100:100:100); + (CH1_TXUSRCLK2 => CH1_TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (CH1_TXUSRCLK2 => CH1_TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (CH1_TXUSRCLK2 => CH1_TXRESETDONE) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[0]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[10]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[11]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[12]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[13]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[14]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[15]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[16]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[17]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[18]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[19]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[1]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[20]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[21]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[22]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[23]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[24]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[25]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[26]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[27]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[2]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[3]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[4]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[5]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[6]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[7]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[8]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTDATA[9]) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTLAST) = (100:100:100, 100:100:100); + (DRPCLK => CH0_AXISTVALID) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[0]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[10]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[11]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[12]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[13]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[14]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[15]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[16]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[17]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[18]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[19]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[1]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[20]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[21]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[22]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[23]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[24]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[25]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[26]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[27]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[2]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[3]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[4]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[5]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[6]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[7]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[8]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTDATA[9]) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTLAST) = (100:100:100, 100:100:100); + (DRPCLK => CH1_AXISTVALID) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTREFCLK => PLLREFCLKMONITOR) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CH0_RXUSRCLK2, 0:0:0, notifier); + $period (negedge CH0_TXUSRCLK2, 0:0:0, notifier); + $period (negedge CH1_RXUSRCLK2, 0:0:0, notifier); + $period (negedge CH1_TXUSRCLK2, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge CH0_RXUSRCLK2, 0:0:0, notifier); + $period (posedge CH0_TXUSRCLK2, 0:0:0, notifier); + $period (posedge CH1_RXUSRCLK2, 0:0:0, notifier); + $period (posedge CH1_TXUSRCLK2, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $setuphold (negedge CH0_RXUSRCLK, negedge CH0_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK_delay, CH0_RXUSRCLK2_delay); + $setuphold (negedge CH0_RXUSRCLK, posedge CH0_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK_delay, CH0_RXUSRCLK2_delay); + $setuphold (negedge CH0_TXUSRCLK, negedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK, negedge CH0_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXUSRCLK2_delay); + $setuphold (negedge CH0_TXUSRCLK, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK, posedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK, posedge CH0_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXUSRCLK2_delay); + $setuphold (negedge CH0_TXUSRCLK, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK2, negedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK2, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK2, posedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXINHIBIT_delay); + $setuphold (negedge CH0_TXUSRCLK2, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH1_RXUSRCLK, negedge CH1_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK_delay, CH1_RXUSRCLK2_delay); + $setuphold (negedge CH1_RXUSRCLK, posedge CH1_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK_delay, CH1_RXUSRCLK2_delay); + $setuphold (negedge CH1_TXUSRCLK, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH1_TXUSRCLK, negedge CH1_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXUSRCLK2_delay); + $setuphold (negedge CH1_TXUSRCLK, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH1_TXUSRCLK, posedge CH1_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXUSRCLK2_delay); + $setuphold (negedge CH1_TXUSRCLK2, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (negedge CH1_TXUSRCLK2, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH0_RXUSRCLK, negedge CH0_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK_delay, CH0_RXUSRCLK2_delay); + $setuphold (posedge CH0_RXUSRCLK, posedge CH0_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK_delay, CH0_RXUSRCLK2_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXEQTRAINING_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPOLARITY_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[0]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[1]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[2]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[3]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH0_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXQPRBSEN_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXEQTRAINING_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPOLARITY_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[0]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[1]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[2]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[3]); + $setuphold (posedge CH0_RXUSRCLK2, negedge CH1_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXQPRBSEN_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge FECCTRLRX0BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, FECCTRLRX0BITSLIPFS_delay); + $setuphold (posedge CH0_RXUSRCLK2, negedge FECCTRLRX1BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, FECCTRLRX1BITSLIPFS_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXEQTRAINING_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPOLARITY_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[0]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[1]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[2]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXPRBSPTN_delay[3]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH0_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH0_RXQPRBSEN_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXEQTRAINING_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPOLARITY_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[0]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[1]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[2]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[3]); + $setuphold (posedge CH0_RXUSRCLK2, posedge CH1_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, CH1_RXQPRBSEN_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge FECCTRLRX0BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, FECCTRLRX0BITSLIPFS_delay); + $setuphold (posedge CH0_RXUSRCLK2, posedge FECCTRLRX1BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH0_RXUSRCLK2_delay, FECCTRLRX1BITSLIPFS_delay); + $setuphold (posedge CH0_TXUSRCLK, negedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK, negedge CH0_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXUSRCLK2_delay); + $setuphold (posedge CH0_TXUSRCLK, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK, posedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK, posedge CH0_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH0_TXUSRCLK2_delay); + $setuphold (posedge CH0_TXUSRCLK, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATASTART_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[100]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[101]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[102]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[103]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[104]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[105]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[106]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[107]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[108]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[109]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[10]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[110]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[111]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[112]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[113]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[114]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[115]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[116]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[117]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[118]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[119]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[11]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[120]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[121]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[122]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[123]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[124]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[125]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[126]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[127]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[128]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[129]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[12]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[130]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[131]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[132]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[133]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[134]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[135]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[136]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[137]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[138]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[139]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[13]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[140]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[141]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[142]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[143]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[144]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[145]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[146]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[147]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[148]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[149]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[14]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[150]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[151]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[152]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[153]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[154]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[155]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[156]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[157]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[158]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[159]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[15]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[160]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[161]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[162]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[163]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[164]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[165]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[166]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[167]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[168]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[169]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[16]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[170]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[171]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[172]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[173]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[174]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[175]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[176]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[177]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[178]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[179]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[17]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[180]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[181]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[182]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[183]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[184]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[185]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[186]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[187]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[188]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[189]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[18]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[190]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[191]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[192]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[193]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[194]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[195]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[196]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[197]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[198]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[199]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[19]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[200]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[201]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[202]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[203]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[204]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[205]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[206]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[207]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[208]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[209]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[20]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[210]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[211]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[212]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[213]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[214]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[215]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[216]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[217]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[218]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[219]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[21]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[220]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[221]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[222]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[223]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[224]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[225]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[226]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[227]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[228]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[229]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[22]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[230]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[231]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[232]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[233]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[234]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[235]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[236]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[237]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[238]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[239]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[23]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[240]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[241]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[242]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[243]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[244]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[245]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[246]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[247]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[248]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[249]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[24]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[250]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[251]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[252]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[253]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[254]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[255]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[25]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[26]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[27]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[28]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[29]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[30]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[31]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[32]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[33]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[34]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[35]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[36]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[37]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[38]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[39]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[40]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[41]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[42]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[43]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[44]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[45]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[46]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[47]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[48]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[49]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[4]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[50]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[51]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[52]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[53]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[54]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[55]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[56]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[57]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[58]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[59]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[5]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[60]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[61]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[62]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[63]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[64]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[65]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[66]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[67]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[68]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[69]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[6]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[70]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[71]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[72]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[73]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[74]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[75]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[76]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[77]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[78]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[79]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[7]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[80]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[81]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[82]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[83]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[84]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[85]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[86]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[87]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[88]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[89]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[8]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[90]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[91]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[92]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[93]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[94]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[95]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[96]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[97]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[98]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[99]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[9]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPOLARITY_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSINERR_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH0_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXQPRBSEN_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATASTART_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[100]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[101]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[102]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[103]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[104]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[105]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[106]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[107]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[108]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[109]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[10]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[110]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[111]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[112]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[113]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[114]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[115]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[116]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[117]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[118]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[119]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[11]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[120]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[121]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[122]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[123]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[124]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[125]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[126]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[127]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[128]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[129]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[12]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[130]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[131]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[132]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[133]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[134]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[135]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[136]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[137]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[138]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[139]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[13]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[140]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[141]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[142]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[143]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[144]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[145]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[146]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[147]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[148]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[149]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[14]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[150]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[151]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[152]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[153]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[154]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[155]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[156]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[157]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[158]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[159]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[15]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[160]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[161]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[162]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[163]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[164]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[165]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[166]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[167]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[168]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[169]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[16]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[170]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[171]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[172]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[173]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[174]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[175]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[176]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[177]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[178]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[179]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[17]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[180]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[181]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[182]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[183]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[184]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[185]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[186]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[187]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[188]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[189]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[18]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[190]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[191]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[192]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[193]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[194]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[195]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[196]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[197]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[198]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[199]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[19]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[200]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[201]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[202]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[203]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[204]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[205]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[206]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[207]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[208]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[209]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[20]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[210]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[211]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[212]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[213]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[214]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[215]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[216]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[217]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[218]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[219]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[21]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[220]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[221]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[222]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[223]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[224]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[225]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[226]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[227]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[228]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[229]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[22]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[230]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[231]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[232]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[233]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[234]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[235]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[236]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[237]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[238]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[239]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[23]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[240]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[241]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[242]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[243]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[244]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[245]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[246]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[247]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[248]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[249]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[24]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[250]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[251]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[252]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[253]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[254]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[255]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[25]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[26]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[27]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[28]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[29]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[30]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[31]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[32]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[33]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[34]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[35]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[36]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[37]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[38]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[39]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[40]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[41]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[42]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[43]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[44]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[45]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[46]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[47]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[48]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[49]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[4]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[50]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[51]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[52]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[53]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[54]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[55]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[56]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[57]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[58]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[59]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[5]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[60]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[61]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[62]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[63]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[64]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[65]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[66]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[67]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[68]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[69]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[6]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[70]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[71]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[72]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[73]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[74]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[75]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[76]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[77]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[78]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[79]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[7]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[80]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[81]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[82]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[83]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[84]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[85]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[86]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[87]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[88]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[89]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[8]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[90]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[91]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[92]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[93]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[94]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[95]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[96]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[97]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[98]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[99]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[9]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPOLARITY_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSINERR_delay); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, negedge CH1_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXQPRBSEN_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATASTART_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[100]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[101]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[102]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[103]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[104]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[105]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[106]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[107]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[108]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[109]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[10]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[110]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[111]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[112]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[113]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[114]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[115]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[116]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[117]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[118]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[119]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[11]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[120]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[121]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[122]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[123]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[124]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[125]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[126]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[127]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[128]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[129]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[12]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[130]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[131]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[132]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[133]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[134]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[135]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[136]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[137]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[138]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[139]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[13]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[140]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[141]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[142]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[143]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[144]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[145]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[146]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[147]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[148]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[149]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[14]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[150]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[151]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[152]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[153]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[154]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[155]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[156]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[157]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[158]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[159]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[15]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[160]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[161]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[162]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[163]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[164]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[165]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[166]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[167]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[168]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[169]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[16]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[170]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[171]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[172]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[173]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[174]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[175]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[176]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[177]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[178]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[179]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[17]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[180]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[181]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[182]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[183]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[184]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[185]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[186]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[187]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[188]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[189]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[18]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[190]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[191]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[192]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[193]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[194]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[195]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[196]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[197]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[198]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[199]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[19]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[200]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[201]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[202]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[203]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[204]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[205]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[206]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[207]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[208]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[209]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[20]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[210]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[211]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[212]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[213]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[214]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[215]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[216]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[217]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[218]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[219]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[21]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[220]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[221]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[222]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[223]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[224]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[225]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[226]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[227]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[228]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[229]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[22]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[230]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[231]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[232]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[233]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[234]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[235]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[236]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[237]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[238]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[239]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[23]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[240]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[241]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[242]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[243]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[244]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[245]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[246]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[247]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[248]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[249]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[24]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[250]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[251]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[252]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[253]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[254]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[255]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[25]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[26]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[27]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[28]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[29]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[30]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[31]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[32]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[33]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[34]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[35]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[36]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[37]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[38]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[39]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[40]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[41]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[42]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[43]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[44]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[45]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[46]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[47]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[48]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[49]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[4]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[50]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[51]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[52]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[53]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[54]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[55]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[56]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[57]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[58]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[59]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[5]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[60]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[61]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[62]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[63]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[64]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[65]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[66]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[67]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[68]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[69]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[6]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[70]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[71]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[72]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[73]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[74]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[75]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[76]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[77]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[78]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[79]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[7]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[80]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[81]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[82]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[83]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[84]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[85]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[86]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[87]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[88]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[89]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[8]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[90]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[91]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[92]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[93]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[94]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[95]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[96]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[97]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[98]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[99]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXDATA_delay[9]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPOLARITY_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSINERR_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXPRBSPTN_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH0_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH0_TXQPRBSEN_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATASTART_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[100]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[101]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[102]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[103]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[104]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[105]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[106]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[107]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[108]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[109]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[10]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[110]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[111]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[112]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[113]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[114]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[115]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[116]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[117]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[118]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[119]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[11]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[120]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[121]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[122]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[123]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[124]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[125]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[126]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[127]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[128]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[129]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[12]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[130]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[131]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[132]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[133]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[134]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[135]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[136]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[137]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[138]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[139]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[13]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[140]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[141]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[142]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[143]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[144]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[145]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[146]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[147]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[148]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[149]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[14]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[150]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[151]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[152]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[153]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[154]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[155]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[156]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[157]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[158]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[159]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[15]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[160]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[161]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[162]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[163]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[164]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[165]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[166]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[167]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[168]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[169]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[16]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[170]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[171]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[172]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[173]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[174]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[175]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[176]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[177]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[178]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[179]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[17]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[180]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[181]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[182]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[183]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[184]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[185]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[186]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[187]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[188]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[189]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[18]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[190]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[191]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[192]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[193]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[194]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[195]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[196]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[197]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[198]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[199]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[19]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[200]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[201]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[202]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[203]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[204]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[205]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[206]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[207]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[208]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[209]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[20]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[210]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[211]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[212]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[213]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[214]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[215]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[216]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[217]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[218]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[219]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[21]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[220]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[221]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[222]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[223]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[224]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[225]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[226]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[227]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[228]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[229]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[22]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[230]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[231]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[232]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[233]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[234]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[235]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[236]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[237]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[238]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[239]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[23]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[240]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[241]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[242]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[243]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[244]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[245]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[246]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[247]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[248]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[249]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[24]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[250]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[251]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[252]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[253]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[254]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[255]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[25]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[26]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[27]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[28]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[29]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[30]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[31]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[32]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[33]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[34]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[35]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[36]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[37]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[38]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[39]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[40]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[41]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[42]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[43]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[44]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[45]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[46]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[47]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[48]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[49]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[4]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[50]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[51]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[52]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[53]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[54]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[55]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[56]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[57]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[58]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[59]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[5]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[60]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[61]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[62]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[63]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[64]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[65]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[66]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[67]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[68]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[69]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[6]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[70]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[71]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[72]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[73]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[74]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[75]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[76]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[77]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[78]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[79]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[7]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[80]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[81]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[82]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[83]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[84]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[85]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[86]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[87]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[88]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[89]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[8]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[90]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[91]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[92]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[93]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[94]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[95]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[96]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[97]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[98]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[99]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXDATA_delay[9]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPOLARITY_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSINERR_delay); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[0]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[1]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[2]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[3]); + $setuphold (posedge CH0_TXUSRCLK2, posedge CH1_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH0_TXUSRCLK2_delay, CH1_TXQPRBSEN_delay); + $setuphold (posedge CH1_RXUSRCLK, negedge CH1_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK_delay, CH1_RXUSRCLK2_delay); + $setuphold (posedge CH1_RXUSRCLK, posedge CH1_RXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK_delay, CH1_RXUSRCLK2_delay); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXEQTRAINING_delay); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPOLARITY_delay); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[0]); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[1]); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[2]); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[3]); + $setuphold (posedge CH1_RXUSRCLK2, negedge CH1_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXQPRBSEN_delay); + $setuphold (posedge CH1_RXUSRCLK2, negedge FECCTRLRX1BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, FECCTRLRX1BITSLIPFS_delay); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXEQTRAINING, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXEQTRAINING_delay); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPOLARITY_delay); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPRBSCNTSTOP, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSCNTSTOP_delay); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[0]); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[1]); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[2]); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXPRBSPTN_delay[3]); + $setuphold (posedge CH1_RXUSRCLK2, posedge CH1_RXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, CH1_RXQPRBSEN_delay); + $setuphold (posedge CH1_RXUSRCLK2, posedge FECCTRLRX1BITSLIPFS, 0:0:0, 0:0:0, notifier, , , CH1_RXUSRCLK2_delay, FECCTRLRX1BITSLIPFS_delay); + $setuphold (posedge CH1_TXUSRCLK, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH1_TXUSRCLK, negedge CH1_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXUSRCLK2_delay); + $setuphold (posedge CH1_TXUSRCLK, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH1_TXUSRCLK, posedge CH1_TXUSRCLK2, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK_delay, CH1_TXUSRCLK2_delay); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATASTART_delay); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[0]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[100]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[101]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[102]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[103]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[104]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[105]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[106]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[107]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[108]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[109]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[10]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[110]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[111]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[112]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[113]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[114]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[115]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[116]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[117]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[118]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[119]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[11]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[120]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[121]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[122]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[123]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[124]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[125]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[126]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[127]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[128]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[129]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[12]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[130]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[131]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[132]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[133]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[134]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[135]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[136]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[137]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[138]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[139]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[13]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[140]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[141]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[142]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[143]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[144]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[145]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[146]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[147]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[148]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[149]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[14]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[150]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[151]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[152]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[153]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[154]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[155]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[156]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[157]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[158]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[159]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[15]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[160]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[161]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[162]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[163]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[164]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[165]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[166]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[167]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[168]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[169]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[16]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[170]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[171]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[172]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[173]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[174]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[175]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[176]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[177]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[178]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[179]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[17]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[180]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[181]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[182]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[183]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[184]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[185]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[186]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[187]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[188]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[189]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[18]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[190]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[191]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[192]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[193]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[194]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[195]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[196]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[197]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[198]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[199]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[19]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[1]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[200]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[201]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[202]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[203]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[204]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[205]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[206]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[207]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[208]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[209]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[20]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[210]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[211]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[212]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[213]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[214]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[215]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[216]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[217]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[218]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[219]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[21]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[220]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[221]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[222]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[223]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[224]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[225]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[226]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[227]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[228]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[229]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[22]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[230]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[231]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[232]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[233]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[234]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[235]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[236]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[237]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[238]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[239]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[23]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[240]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[241]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[242]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[243]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[244]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[245]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[246]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[247]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[248]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[249]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[24]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[250]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[251]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[252]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[253]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[254]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[255]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[25]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[26]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[27]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[28]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[29]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[2]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[30]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[31]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[32]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[33]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[34]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[35]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[36]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[37]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[38]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[39]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[3]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[40]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[41]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[42]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[43]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[44]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[45]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[46]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[47]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[48]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[49]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[4]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[50]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[51]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[52]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[53]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[54]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[55]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[56]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[57]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[58]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[59]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[5]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[60]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[61]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[62]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[63]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[64]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[65]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[66]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[67]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[68]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[69]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[6]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[70]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[71]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[72]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[73]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[74]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[75]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[76]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[77]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[78]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[79]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[7]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[80]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[81]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[82]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[83]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[84]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[85]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[86]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[87]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[88]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[89]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[8]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[90]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[91]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[92]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[93]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[94]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[95]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[96]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[97]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[98]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[99]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[9]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPOLARITY_delay); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSINERR_delay); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[0]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[1]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[2]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[3]); + $setuphold (posedge CH1_TXUSRCLK2, negedge CH1_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXQPRBSEN_delay); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATASTART, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATASTART_delay); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[0], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[0]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[100], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[100]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[101], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[101]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[102], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[102]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[103], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[103]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[104], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[104]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[105], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[105]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[106], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[106]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[107], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[107]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[108], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[108]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[109], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[109]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[10], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[10]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[110], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[110]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[111], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[111]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[112], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[112]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[113], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[113]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[114], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[114]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[115], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[115]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[116], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[116]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[117], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[117]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[118], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[118]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[119], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[119]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[11], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[11]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[120], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[120]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[121], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[121]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[122], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[122]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[123], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[123]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[124], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[124]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[125], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[125]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[126], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[126]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[127], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[127]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[128], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[128]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[129], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[129]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[12], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[12]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[130], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[130]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[131], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[131]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[132], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[132]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[133], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[133]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[134], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[134]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[135], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[135]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[136], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[136]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[137], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[137]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[138], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[138]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[139], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[139]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[13], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[13]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[140], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[140]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[141], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[141]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[142], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[142]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[143], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[143]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[144], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[144]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[145], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[145]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[146], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[146]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[147], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[147]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[148], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[148]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[149], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[149]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[14], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[14]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[150], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[150]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[151], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[151]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[152], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[152]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[153], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[153]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[154], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[154]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[155], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[155]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[156], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[156]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[157], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[157]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[158], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[158]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[159], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[159]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[15], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[15]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[160], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[160]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[161], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[161]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[162], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[162]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[163], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[163]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[164], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[164]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[165], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[165]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[166], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[166]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[167], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[167]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[168], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[168]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[169], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[169]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[16], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[16]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[170], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[170]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[171], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[171]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[172], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[172]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[173], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[173]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[174], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[174]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[175], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[175]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[176], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[176]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[177], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[177]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[178], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[178]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[179], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[179]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[17], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[17]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[180], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[180]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[181], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[181]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[182], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[182]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[183], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[183]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[184], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[184]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[185], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[185]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[186], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[186]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[187], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[187]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[188], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[188]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[189], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[189]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[18], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[18]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[190], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[190]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[191], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[191]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[192], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[192]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[193], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[193]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[194], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[194]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[195], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[195]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[196], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[196]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[197], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[197]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[198], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[198]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[199], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[199]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[19], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[19]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[1], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[1]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[200], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[200]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[201], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[201]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[202], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[202]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[203], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[203]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[204], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[204]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[205], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[205]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[206], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[206]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[207], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[207]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[208], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[208]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[209], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[209]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[20], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[20]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[210], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[210]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[211], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[211]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[212], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[212]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[213], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[213]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[214], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[214]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[215], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[215]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[216], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[216]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[217], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[217]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[218], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[218]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[219], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[219]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[21], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[21]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[220], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[220]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[221], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[221]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[222], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[222]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[223], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[223]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[224], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[224]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[225], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[225]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[226], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[226]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[227], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[227]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[228], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[228]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[229], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[229]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[22], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[22]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[230], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[230]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[231], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[231]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[232], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[232]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[233], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[233]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[234], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[234]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[235], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[235]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[236], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[236]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[237], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[237]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[238], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[238]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[239], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[239]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[23], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[23]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[240], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[240]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[241], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[241]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[242], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[242]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[243], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[243]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[244], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[244]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[245], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[245]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[246], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[246]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[247], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[247]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[248], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[248]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[249], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[249]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[24], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[24]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[250], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[250]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[251], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[251]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[252], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[252]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[253], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[253]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[254], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[254]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[255], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[255]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[25], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[25]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[26], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[26]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[27], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[27]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[28], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[28]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[29], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[29]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[2], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[2]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[30], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[30]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[31], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[31]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[32], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[32]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[33], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[33]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[34], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[34]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[35], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[35]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[36], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[36]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[37], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[37]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[38], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[38]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[39], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[39]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[3], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[3]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[40], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[40]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[41], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[41]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[42], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[42]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[43], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[43]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[44], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[44]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[45], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[45]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[46], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[46]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[47], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[47]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[48], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[48]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[49], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[49]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[4], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[4]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[50], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[50]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[51], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[51]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[52], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[52]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[53], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[53]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[54], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[54]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[55], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[55]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[56], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[56]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[57], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[57]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[58], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[58]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[59], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[59]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[5], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[5]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[60], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[60]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[61], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[61]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[62], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[62]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[63], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[63]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[64], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[64]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[65], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[65]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[66], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[66]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[67], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[67]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[68], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[68]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[69], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[69]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[6], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[6]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[70], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[70]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[71], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[71]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[72], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[72]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[73], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[73]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[74], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[74]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[75], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[75]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[76], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[76]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[77], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[77]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[78], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[78]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[79], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[79]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[7], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[7]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[80], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[80]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[81], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[81]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[82], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[82]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[83], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[83]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[84], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[84]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[85], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[85]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[86], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[86]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[87], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[87]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[88], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[88]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[89], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[89]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[8], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[8]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[90], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[90]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[91], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[91]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[92], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[92]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[93], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[93]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[94], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[94]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[95], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[95]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[96], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[96]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[97], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[97]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[98], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[98]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[99], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[99]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXDATA[9], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXDATA_delay[9]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXINHIBIT, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXINHIBIT_delay); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPOLARITY, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPOLARITY_delay); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPRBSINERR, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSINERR_delay); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPRBSPTN[0], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[0]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPRBSPTN[1], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[1]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPRBSPTN[2], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[2]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXPRBSPTN[3], 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXPRBSPTN_delay[3]); + $setuphold (posedge CH1_TXUSRCLK2, posedge CH1_TXQPRBSEN, 0:0:0, 0:0:0, notifier, , , CH1_TXUSRCLK2_delay, CH1_TXQPRBSEN_delay); + $setuphold (posedge DRPCLK, negedge CH0_AXISEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH0_AXISEN_delay); + $setuphold (posedge DRPCLK, negedge CH0_AXISTRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH0_AXISTRDY_delay); + $setuphold (posedge DRPCLK, negedge CH1_AXISEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH1_AXISEN_delay); + $setuphold (posedge DRPCLK, negedge CH1_AXISTRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH1_AXISTRDY_delay); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge CH0_AXISEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH0_AXISEN_delay); + $setuphold (posedge DRPCLK, posedge CH0_AXISTRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH0_AXISTRDY_delay); + $setuphold (posedge DRPCLK, posedge CH1_AXISEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH1_AXISEN_delay); + $setuphold (posedge DRPCLK, posedge CH1_AXISTRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, CH1_AXISTRDY_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $width (negedge CH0_RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge CH0_TXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge CH1_RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge CH1_TXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge CH0_RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge CH0_TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge CH1_RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge CH1_TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTPE2_CHANNEL.v b/verilog/src/unisims/GTPE2_CHANNEL.v new file mode 100644 index 0000000..52915a2 --- /dev/null +++ b/verilog/src/unisims/GTPE2_CHANNEL.v @@ -0,0 +1,4052 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTPE2_CHANNEL.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// 11/8/12 - 686589 - YML default changes +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine +module GTPE2_CHANNEL ( + DMONITOROUT, + DRPDO, + DRPRDY, + EYESCANDATAERROR, + GTPTXN, + GTPTXP, + PCSRSVDOUT, + PHYSTATUS, + PMARSVDOUT0, + PMARSVDOUT1, + RXBUFSTATUS, + RXBYTEISALIGNED, + RXBYTEREALIGN, + RXCDRLOCK, + RXCHANBONDSEQ, + RXCHANISALIGNED, + RXCHANREALIGN, + RXCHARISCOMMA, + RXCHARISK, + RXCHBONDO, + RXCLKCORCNT, + RXCOMINITDET, + RXCOMMADET, + RXCOMSASDET, + RXCOMWAKEDET, + RXDATA, + RXDATAVALID, + RXDISPERR, + RXDLYSRESETDONE, + RXELECIDLE, + RXHEADER, + RXHEADERVALID, + RXNOTINTABLE, + RXOSINTDONE, + RXOSINTSTARTED, + RXOSINTSTROBEDONE, + RXOSINTSTROBESTARTED, + RXOUTCLK, + RXOUTCLKFABRIC, + RXOUTCLKPCS, + RXPHALIGNDONE, + RXPHMONITOR, + RXPHSLIPMONITOR, + RXPMARESETDONE, + RXPRBSERR, + RXRATEDONE, + RXRESETDONE, + RXSTARTOFSEQ, + RXSTATUS, + RXSYNCDONE, + RXSYNCOUT, + RXVALID, + TXBUFSTATUS, + TXCOMFINISH, + TXDLYSRESETDONE, + TXGEARBOXREADY, + TXOUTCLK, + TXOUTCLKFABRIC, + TXOUTCLKPCS, + TXPHALIGNDONE, + TXPHINITDONE, + TXPMARESETDONE, + TXRATEDONE, + TXRESETDONE, + TXSYNCDONE, + TXSYNCOUT, + + CFGRESET, + CLKRSVD0, + CLKRSVD1, + DMONFIFORESET, + DMONITORCLK, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + EYESCANMODE, + EYESCANRESET, + EYESCANTRIGGER, + GTPRXN, + GTPRXP, + GTRESETSEL, + GTRSVD, + GTRXRESET, + GTTXRESET, + LOOPBACK, + PCSRSVDIN, + PLL0CLK, + PLL0REFCLK, + PLL1CLK, + PLL1REFCLK, + PMARSVDIN0, + PMARSVDIN1, + PMARSVDIN2, + PMARSVDIN3, + PMARSVDIN4, + RESETOVRD, + RX8B10BEN, + RXADAPTSELTEST, + RXBUFRESET, + RXCDRFREQRESET, + RXCDRHOLD, + RXCDROVRDEN, + RXCDRRESET, + RXCDRRESETRSV, + RXCHBONDEN, + RXCHBONDI, + RXCHBONDLEVEL, + RXCHBONDMASTER, + RXCHBONDSLAVE, + RXCOMMADETEN, + RXDDIEN, + RXDFEXYDEN, + RXDLYBYPASS, + RXDLYEN, + RXDLYOVRDEN, + RXDLYSRESET, + RXELECIDLEMODE, + RXGEARBOXSLIP, + RXLPMHFHOLD, + RXLPMHFOVRDEN, + RXLPMLFHOLD, + RXLPMLFOVRDEN, + RXLPMOSINTNTRLEN, + RXLPMRESET, + RXMCOMMAALIGNEN, + RXOOBRESET, + RXOSCALRESET, + RXOSHOLD, + RXOSINTCFG, + RXOSINTEN, + RXOSINTHOLD, + RXOSINTID0, + RXOSINTNTRLEN, + RXOSINTOVRDEN, + RXOSINTPD, + RXOSINTSTROBE, + RXOSINTTESTOVRDEN, + RXOSOVRDEN, + RXOUTCLKSEL, + RXPCOMMAALIGNEN, + RXPCSRESET, + RXPD, + RXPHALIGN, + RXPHALIGNEN, + RXPHDLYPD, + RXPHDLYRESET, + RXPHOVRDEN, + RXPMARESET, + RXPOLARITY, + RXPRBSCNTRESET, + RXPRBSSEL, + RXRATE, + RXRATEMODE, + RXSLIDE, + RXSYNCALLIN, + RXSYNCIN, + RXSYNCMODE, + RXSYSCLKSEL, + RXUSERRDY, + RXUSRCLK, + RXUSRCLK2, + SETERRSTATUS, + SIGVALIDCLK, + TSTIN, + TX8B10BBYPASS, + TX8B10BEN, + TXBUFDIFFCTRL, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCOMINIT, + TXCOMSAS, + TXCOMWAKE, + TXDATA, + TXDEEMPH, + TXDETECTRX, + TXDIFFCTRL, + TXDIFFPD, + TXDLYBYPASS, + TXDLYEN, + TXDLYHOLD, + TXDLYOVRDEN, + TXDLYSRESET, + TXDLYUPDOWN, + TXELECIDLE, + TXHEADER, + TXINHIBIT, + TXMAINCURSOR, + TXMARGIN, + TXOUTCLKSEL, + TXPCSRESET, + TXPD, + TXPDELECIDLEMODE, + TXPHALIGN, + TXPHALIGNEN, + TXPHDLYPD, + TXPHDLYRESET, + TXPHDLYTSTCLK, + TXPHINIT, + TXPHOVRDEN, + TXPIPPMEN, + TXPIPPMOVRDEN, + TXPIPPMPD, + TXPIPPMSEL, + TXPIPPMSTEPSIZE, + TXPISOPD, + TXPMARESET, + TXPOLARITY, + TXPOSTCURSOR, + TXPOSTCURSORINV, + TXPRBSFORCEERR, + TXPRBSSEL, + TXPRECURSOR, + TXPRECURSORINV, + TXRATE, + TXRATEMODE, + TXSEQUENCE, + TXSTARTSEQ, + TXSWING, + TXSYNCALLIN, + TXSYNCIN, + TXSYNCMODE, + TXSYSCLKSEL, + TXUSERRDY, + TXUSRCLK, + TXUSRCLK2 +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; + parameter [6:0] CFOK_CFG2 = 7'b0100000; + parameter [6:0] CFOK_CFG3 = 7'b0100000; + parameter [0:0] CFOK_CFG4 = 1'b0; + parameter [1:0] CFOK_CFG5 = 2'b00; + parameter [3:0] CFOK_CFG6 = 4'b0000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter [0:0] CLK_COMMON_SWING = 1'b0; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h010; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; + parameter [31:0] PMA_RSV = 32'h00000333; + parameter [31:0] PMA_RSV2 = 32'h00002050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [3:0] PMA_RSV4 = 4'b0000; + parameter [0:0] PMA_RSV5 = 1'b0; + parameter [0:0] PMA_RSV6 = 1'b0; + parameter [0:0] PMA_RSV7 = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [8:0] RXDLY_LCFG = 9'h020; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [6:0] RXLPMRESET_TIME = 7'b0001111; + parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; + parameter [3:0] RXLPM_CFG = 4'b0110; + parameter [0:0] RXLPM_CFG1 = 1'b0; + parameter [0:0] RXLPM_CM_CFG = 1'b0; + parameter [8:0] RXLPM_GC_CFG = 9'b111100010; + parameter [2:0] RXLPM_GC_CFG2 = 3'b001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; + parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; + parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; + parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; + parameter [0:0] RXLPM_INCM_CFG = 1'b0; + parameter [0:0] RXLPM_IPCM_CFG = 1'b0; + parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; + parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; + parameter [2:0] RXLPM_OSINT_CFG = 3'b100; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084000; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [2:0] RXPI_CFG0 = 3'b000; + parameter [0:0] RXPI_CFG1 = 1'b0; + parameter [0:0] RXPI_CFG2 = 1'b0; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SATA_PLL_CFG = "VCO_3000MHZ"; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.0"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [8:0] TXDLY_LCFG = 9'h020; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084000; + parameter [15:0] TXPH_CFG = 16'h0400; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output DRPRDY; + output EYESCANDATAERROR; + output GTPTXN; + output GTPTXP; + output PHYSTATUS; + output PMARSVDOUT0; + output PMARSVDOUT1; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input DMONFIFORESET; + input DMONITORCLK; + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTPRXN; + input GTPRXP; + input GTRESETSEL; + input GTRXRESET; + input GTTXRESET; + input PLL0CLK; + input PLL0REFCLK; + input PLL1CLK; + input PLL1REFCLK; + input PMARSVDIN0; + input PMARSVDIN1; + input PMARSVDIN2; + input PMARSVDIN3; + input PMARSVDIN4; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFOVRDEN; + input RXLPMOSINTNTRLEN; + input RXLPMRESET; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTPD; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + input RXUSRCLK2; + input RXUSRCLK; + input SETERRSTATUS; + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + input TXUSRCLK2; + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [31:0] TXDATA; + input [3:0] RXCHBONDI; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TX8B10BBYPASS; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [8:0] DRPADDR; + + reg SIM_RECEIVER_DETECT_PASS_BINARY; + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] ACJTAG_DEBUG_MODE_BINARY; + reg [0:0] ACJTAG_MODE_BINARY; + reg [0:0] ACJTAG_RESET_BINARY; + reg [0:0] ALIGN_COMMA_DOUBLE_BINARY; + reg [0:0] ALIGN_MCOMMA_DET_BINARY; + reg [0:0] ALIGN_PCOMMA_DET_BINARY; + reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY; + reg [0:0] CFOK_CFG4_BINARY; + reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY; + reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY; + reg [0:0] CLK_COMMON_SWING_BINARY; + reg [0:0] CLK_CORRECT_USE_BINARY; + reg [0:0] CLK_COR_KEEP_IDLE_BINARY; + reg [0:0] CLK_COR_PRECEDENCE_BINARY; + reg [0:0] CLK_COR_SEQ_2_USE_BINARY; + reg [0:0] DEC_MCOMMA_DETECT_BINARY; + reg [0:0] DEC_PCOMMA_DETECT_BINARY; + reg [0:0] DEC_VALID_COMMA_ONLY_BINARY; + reg [0:0] ES_CLK_PHASE_SEL_BINARY; + reg [0:0] ES_ERRDET_EN_BINARY; + reg [0:0] ES_EYE_SCAN_EN_BINARY; + reg [0:0] FTS_LANE_DESKEW_EN_BINARY; + reg [0:0] LOOPBACK_CFG_BINARY; + reg [0:0] PCS_PCIE_EN_BINARY; + reg [0:0] PMA_LOOPBACK_CFG_BINARY; + reg [0:0] PMA_RSV5_BINARY; + reg [0:0] PMA_RSV6_BINARY; + reg [0:0] PMA_RSV7_BINARY; + reg [0:0] RXBUF_ADDR_MODE_BINARY; + reg [0:0] RXBUF_EN_BINARY; + reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY; + reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY; + reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY; + reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] RXBUF_THRESH_OVRD_BINARY; + reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY; + reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY; + reg [0:0] RXGEARBOX_EN_BINARY; + reg [0:0] RXLPM_BIAS_STARTUP_DISABLE_BINARY; + reg [0:0] RXLPM_CFG1_BINARY; + reg [0:0] RXLPM_CM_CFG_BINARY; + reg [0:0] RXLPM_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RXLPM_INCM_CFG_BINARY; + reg [0:0] RXLPM_IPCM_CFG_BINARY; + reg [0:0] RXOOB_CLK_CFG_BINARY; + reg [0:0] RXPI_CFG1_BINARY; + reg [0:0] RXPI_CFG2_BINARY; + reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY; + reg [0:0] RXSYNC_MULTILANE_BINARY; + reg [0:0] RXSYNC_OVRD_BINARY; + reg [0:0] RXSYNC_SKIP_DA_BINARY; + reg [0:0] RX_CLKMUX_EN_BINARY; + reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY; + reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY; + reg [0:0] RX_XCLK_SEL_BINARY; + reg [0:0] SHOW_REALIGN_COMMA_BINARY; + reg [0:0] TXBUF_EN_BINARY; + reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] TXGEARBOX_EN_BINARY; + reg [0:0] TXOOB_CFG_BINARY; + reg [0:0] TXPI_CFG3_BINARY; + reg [0:0] TXPI_CFG4_BINARY; + reg [0:0] TXPI_GREY_SEL_BINARY; + reg [0:0] TXPI_INVSTROBE_SEL_BINARY; + reg [0:0] TXPI_PPMCLK_SEL_BINARY; + reg [0:0] TXSYNC_MULTILANE_BINARY; + reg [0:0] TXSYNC_OVRD_BINARY; + reg [0:0] TXSYNC_SKIP_DA_BINARY; + reg [0:0] TX_CLKMUX_EN_BINARY; + reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY; + reg [0:0] TX_MAINCURSOR_SEL_BINARY; + reg [0:0] TX_PREDRIVER_MODE_BINARY; + reg [0:0] TX_XCLK_SEL_BINARY; + reg [0:0] UCODEER_CLR_BINARY; + reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY; + reg [12:0] RX_OS_CFG_BINARY; + reg [13:0] RXLPM_HF_CFG_BINARY; + reg [13:0] RX_DEBUG_CFG_BINARY; + reg [14:0] TERM_RCAL_CFG_BINARY; + reg [15:0] RX_BIAS_CFG_BINARY; + reg [17:0] RXLPM_LF_CFG_BINARY; + reg [19:0] ADAPT_CFG0_BINARY; + reg [1:0] ALIGN_COMMA_WORD_BINARY; + reg [1:0] CFOK_CFG5_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_BINARY; + reg [1:0] CLK_COR_SEQ_LEN_BINARY; + reg [1:0] OUTREFCLK_SEL_INV_BINARY; + reg [1:0] PMA_RSV3_BINARY; + reg [1:0] RXSLIDE_MODE_BINARY; + reg [1:0] RX_CM_SEL_BINARY; + reg [1:0] SATA_PLL_CFG_BINARY; + reg [1:0] TXPI_CFG0_BINARY; + reg [1:0] TXPI_CFG1_BINARY; + reg [1:0] TXPI_CFG2_BINARY; + reg [2:0] GEARBOX_MODE_BINARY; + reg [2:0] RXLPM_GC_CFG2_BINARY; + reg [2:0] RXLPM_OSINT_CFG_BINARY; + reg [2:0] RXOUT_DIV_BINARY; + reg [2:0] RXPI_CFG0_BINARY; + reg [2:0] RX_DATA_WIDTH_BINARY; + reg [2:0] SATA_BURST_VAL_BINARY; + reg [2:0] SATA_EIDLE_VAL_BINARY; + reg [2:0] TERM_RCAL_OVRD_BINARY; + reg [2:0] TXOUT_DIV_BINARY; + reg [2:0] TXPI_CFG5_BINARY; + reg [2:0] TXPI_SYNFREQ_PPM_BINARY; + reg [2:0] TX_DATA_WIDTH_BINARY; + reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY; + reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY; + reg [2:0] TX_RXDETECT_REF_BINARY; + reg [3:0] CFOK_CFG6_BINARY; + reg [3:0] CHAN_BOND_MAX_SKEW_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY; + reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY; + reg [3:0] FTS_LANE_DESKEW_CFG_BINARY; + reg [3:0] PMA_RSV4_BINARY; + reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY; + reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY; + reg [3:0] RXLPM_CFG_BINARY; + reg [3:0] RXLPM_HF_CFG3_BINARY; + reg [3:0] RXSLIDE_AUTO_WAIT_BINARY; + reg [3:0] RX_CM_TRIM_BINARY; + reg [3:0] SATA_BURST_SEQ_LEN_BINARY; + reg [42:0] CFOK_CFG_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_BINARY; + reg [4:0] ES_PRESCALE_BINARY; + reg [4:0] RXBUFRESET_TIME_BINARY; + reg [4:0] RXCDRFREQRESET_TIME_BINARY; + reg [4:0] RXCDRPHRESET_TIME_BINARY; + reg [4:0] RXISCANRESET_TIME_BINARY; + reg [4:0] RXLPM_HF_CFG2_BINARY; + reg [4:0] RXLPM_LF_CFG2_BINARY; + reg [4:0] RXOSCALRESET_TIMEOUT_BINARY; + reg [4:0] RXOSCALRESET_TIME_BINARY; + reg [4:0] RXPCSRESET_TIME_BINARY; + reg [4:0] RXPH_MONITOR_SEL_BINARY; + reg [4:0] RXPMARESET_TIME_BINARY; + reg [4:0] RX_CLK25_DIV_BINARY; + reg [4:0] RX_SIG_VALID_DLY_BINARY; + reg [4:0] TXPCSRESET_TIME_BINARY; + reg [4:0] TXPH_MONITOR_SEL_BINARY; + reg [4:0] TXPMARESET_TIME_BINARY; + reg [4:0] TX_CLK25_DIV_BINARY; + reg [4:0] TX_DRIVE_MODE_BINARY; + reg [5:0] CLK_COR_MAX_LAT_BINARY; + reg [5:0] CLK_COR_MIN_LAT_BINARY; + reg [5:0] ES_CONTROL_BINARY; + reg [5:0] RXBUF_THRESH_OVFLW_BINARY; + reg [5:0] RXBUF_THRESH_UNDFLW_BINARY; + reg [5:0] RXCDR_LOCK_CFG_BINARY; + reg [5:0] RX_BUFFER_CFG_BINARY; + reg [5:0] RX_DDI_SEL_BINARY; + reg [5:0] SAS_MIN_COM_BINARY; + reg [5:0] SATA_MAX_BURST_BINARY; + reg [5:0] SATA_MAX_INIT_BINARY; + reg [5:0] SATA_MAX_WAKE_BINARY; + reg [5:0] SATA_MIN_BURST_BINARY; + reg [5:0] SATA_MIN_INIT_BINARY; + reg [5:0] SATA_MIN_WAKE_BINARY; + reg [5:0] TX_DEEMPH0_BINARY; + reg [5:0] TX_DEEMPH1_BINARY; + reg [6:0] CFOK_CFG2_BINARY; + reg [6:0] CFOK_CFG3_BINARY; + reg [6:0] RXLPMRESET_TIME_BINARY; + reg [6:0] RXOOB_CFG_BINARY; + reg [6:0] SAS_MAX_COM_BINARY; + reg [6:0] TX_MARGIN_FULL_0_BINARY; + reg [6:0] TX_MARGIN_FULL_1_BINARY; + reg [6:0] TX_MARGIN_FULL_2_BINARY; + reg [6:0] TX_MARGIN_FULL_3_BINARY; + reg [6:0] TX_MARGIN_FULL_4_BINARY; + reg [6:0] TX_MARGIN_LOW_0_BINARY; + reg [6:0] TX_MARGIN_LOW_1_BINARY; + reg [6:0] TX_MARGIN_LOW_2_BINARY; + reg [6:0] TX_MARGIN_LOW_3_BINARY; + reg [6:0] TX_MARGIN_LOW_4_BINARY; + reg [7:0] TXPI_PPM_CFG_BINARY; + reg [8:0] ES_VERT_OFFSET_BINARY; + reg [8:0] RXLPM_GC_CFG_BINARY; + reg [9:0] ALIGN_COMMA_ENABLE_BINARY; + reg [9:0] ALIGN_MCOMMA_VALUE_BINARY; + reg [9:0] ALIGN_PCOMMA_VALUE_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_BINARY; + reg [9:0] ES_PMA_CFG_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (ALIGN_COMMA_DOUBLE) + "FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0; + "TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE); + #1 $finish; + end + endcase + + case (ALIGN_MCOMMA_DET) + "TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET); + #1 $finish; + end + endcase + + case (ALIGN_PCOMMA_DET) + "TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET); + #1 $finish; + end + endcase + + case (CBCC_DATA_SOURCE_SEL) + "DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1; + "ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL); + #1 $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN) + "FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE) + "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN) + 1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (CLK_CORRECT_USE) + "TRUE" : CLK_CORRECT_USE_BINARY = 1'b1; + "FALSE" : CLK_CORRECT_USE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE); + #1 $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE) + "FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE); + #1 $finish; + end + endcase + + case (CLK_COR_PRECEDENCE) + "TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1; + "FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE) + "FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_LEN) + 1 : CLK_COR_SEQ_LEN_BINARY = 2'b00; + 2 : CLK_COR_SEQ_LEN_BINARY = 2'b01; + 3 : CLK_COR_SEQ_LEN_BINARY = 2'b10; + 4 : CLK_COR_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (DEC_MCOMMA_DETECT) + "TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_PCOMMA_DETECT) + "TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY) + "TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1; + "FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY); + #1 $finish; + end + endcase + + case (ES_ERRDET_EN) + "FALSE" : ES_ERRDET_EN_BINARY = 1'b0; + "TRUE" : ES_ERRDET_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN); + #1 $finish; + end + endcase + + case (ES_EYE_SCAN_EN) + "FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0; + "TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN); + #1 $finish; + end + endcase + + case (FTS_LANE_DESKEW_EN) + "FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0; + "TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN); + #1 $finish; + end + endcase + + case (PCS_PCIE_EN) + "FALSE" : PCS_PCIE_EN_BINARY = 1'b0; + "TRUE" : PCS_PCIE_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN); + #1 $finish; + end + endcase + + case (RXBUF_ADDR_MODE) + "FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0; + "FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE); + #1 $finish; + end + endcase + + case (RXBUF_EN) + "TRUE" : RXBUF_EN_BINARY = 1'b1; + "FALSE" : RXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_CB_CHANGE) + "TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_COMMAALIGN) + "FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_EIDLE) + "FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_RATE_CHANGE) + "TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_THRESH_OVRD) + "FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0; + "TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD); + #1 $finish; + end + endcase + + case (RXGEARBOX_EN) + "FALSE" : RXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : RXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN); + #1 $finish; + end + endcase + + case (RXOOB_CLK_CFG) + "PMA" : RXOOB_CLK_CFG_BINARY = 1'b0; + "FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG); + #1 $finish; + end + endcase + + case (RXOUT_DIV) + 2 : RXOUT_DIV_BINARY = 3'b001; + 1 : RXOUT_DIV_BINARY = 3'b000; + 4 : RXOUT_DIV_BINARY = 3'b010; + 8 : RXOUT_DIV_BINARY = 3'b011; + 16 : RXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute RXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (RXSLIDE_MODE) + "OFF" : RXSLIDE_MODE_BINARY = 2'b00; + "AUTO" : RXSLIDE_MODE_BINARY = 2'b01; + "PCS" : RXSLIDE_MODE_BINARY = 2'b10; + "PMA" : RXSLIDE_MODE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE); + #1 $finish; + end + endcase + + case (RX_CLK25_DIV) + 7 : RX_CLK25_DIV_BINARY = 5'b00110; + 1 : RX_CLK25_DIV_BINARY = 5'b00000; + 2 : RX_CLK25_DIV_BINARY = 5'b00001; + 3 : RX_CLK25_DIV_BINARY = 5'b00010; + 4 : RX_CLK25_DIV_BINARY = 5'b00011; + 5 : RX_CLK25_DIV_BINARY = 5'b00100; + 6 : RX_CLK25_DIV_BINARY = 5'b00101; + 8 : RX_CLK25_DIV_BINARY = 5'b00111; + 9 : RX_CLK25_DIV_BINARY = 5'b01000; + 10 : RX_CLK25_DIV_BINARY = 5'b01001; + 11 : RX_CLK25_DIV_BINARY = 5'b01010; + 12 : RX_CLK25_DIV_BINARY = 5'b01011; + 13 : RX_CLK25_DIV_BINARY = 5'b01100; + 14 : RX_CLK25_DIV_BINARY = 5'b01101; + 15 : RX_CLK25_DIV_BINARY = 5'b01110; + 16 : RX_CLK25_DIV_BINARY = 5'b01111; + 17 : RX_CLK25_DIV_BINARY = 5'b10000; + 18 : RX_CLK25_DIV_BINARY = 5'b10001; + 19 : RX_CLK25_DIV_BINARY = 5'b10010; + 20 : RX_CLK25_DIV_BINARY = 5'b10011; + 21 : RX_CLK25_DIV_BINARY = 5'b10100; + 22 : RX_CLK25_DIV_BINARY = 5'b10101; + 23 : RX_CLK25_DIV_BINARY = 5'b10110; + 24 : RX_CLK25_DIV_BINARY = 5'b10111; + 25 : RX_CLK25_DIV_BINARY = 5'b11000; + 26 : RX_CLK25_DIV_BINARY = 5'b11001; + 27 : RX_CLK25_DIV_BINARY = 5'b11010; + 28 : RX_CLK25_DIV_BINARY = 5'b11011; + 29 : RX_CLK25_DIV_BINARY = 5'b11100; + 30 : RX_CLK25_DIV_BINARY = 5'b11101; + 31 : RX_CLK25_DIV_BINARY = 5'b11110; + 32 : RX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (RX_DATA_WIDTH) + 20 : RX_DATA_WIDTH_BINARY = 3'b011; + 16 : RX_DATA_WIDTH_BINARY = 3'b010; + 32 : RX_DATA_WIDTH_BINARY = 3'b100; + 40 : RX_DATA_WIDTH_BINARY = 3'b101; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", RX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (RX_DEFER_RESET_BUF_EN) + "TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1; + "FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN); + #1 $finish; + end + endcase + + case (RX_DISPERR_SEQ_MATCH) + "TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1; + "FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH); + #1 $finish; + end + endcase + + case (RX_SIG_VALID_DLY) + 10 : RX_SIG_VALID_DLY_BINARY = 5'b01001; + 1 : RX_SIG_VALID_DLY_BINARY = 5'b00000; + 2 : RX_SIG_VALID_DLY_BINARY = 5'b00001; + 3 : RX_SIG_VALID_DLY_BINARY = 5'b00010; + 4 : RX_SIG_VALID_DLY_BINARY = 5'b00011; + 5 : RX_SIG_VALID_DLY_BINARY = 5'b00100; + 6 : RX_SIG_VALID_DLY_BINARY = 5'b00101; + 7 : RX_SIG_VALID_DLY_BINARY = 5'b00110; + 8 : RX_SIG_VALID_DLY_BINARY = 5'b00111; + 9 : RX_SIG_VALID_DLY_BINARY = 5'b01000; + 11 : RX_SIG_VALID_DLY_BINARY = 5'b01010; + 12 : RX_SIG_VALID_DLY_BINARY = 5'b01011; + 13 : RX_SIG_VALID_DLY_BINARY = 5'b01100; + 14 : RX_SIG_VALID_DLY_BINARY = 5'b01101; + 15 : RX_SIG_VALID_DLY_BINARY = 5'b01110; + 16 : RX_SIG_VALID_DLY_BINARY = 5'b01111; + 17 : RX_SIG_VALID_DLY_BINARY = 5'b10000; + 18 : RX_SIG_VALID_DLY_BINARY = 5'b10001; + 19 : RX_SIG_VALID_DLY_BINARY = 5'b10010; + 20 : RX_SIG_VALID_DLY_BINARY = 5'b10011; + 21 : RX_SIG_VALID_DLY_BINARY = 5'b10100; + 22 : RX_SIG_VALID_DLY_BINARY = 5'b10101; + 23 : RX_SIG_VALID_DLY_BINARY = 5'b10110; + 24 : RX_SIG_VALID_DLY_BINARY = 5'b10111; + 25 : RX_SIG_VALID_DLY_BINARY = 5'b11000; + 26 : RX_SIG_VALID_DLY_BINARY = 5'b11001; + 27 : RX_SIG_VALID_DLY_BINARY = 5'b11010; + 28 : RX_SIG_VALID_DLY_BINARY = 5'b11011; + 29 : RX_SIG_VALID_DLY_BINARY = 5'b11100; + 30 : RX_SIG_VALID_DLY_BINARY = 5'b11101; + 31 : RX_SIG_VALID_DLY_BINARY = 5'b11110; + 32 : RX_SIG_VALID_DLY_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10); + #1 $finish; + end + endcase + + case (RX_XCLK_SEL) + "RXREC" : RX_XCLK_SEL_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL); + #1 $finish; + end + endcase + + case (SATA_PLL_CFG) + "VCO_3000MHZ" : SATA_PLL_CFG_BINARY = 2'b00; + "VCO_750MHZ" : SATA_PLL_CFG_BINARY = 2'b10; + "VCO_1500MHZ" : SATA_PLL_CFG_BINARY = 2'b01; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_PLL_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_PLL_CFG); + #1 $finish; + end + endcase + + case (SHOW_REALIGN_COMMA) + "TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1; + "FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA); + #1 $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS) + "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + "FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + + case (SIM_TX_EIDLE_DRIVE_LEVEL) + "X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION); + #1 $finish; + end + endcase + + case (TXBUF_EN) + "TRUE" : TXBUF_EN_BINARY = 1'b1; + "FALSE" : TXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN); + #1 $finish; + end + endcase + + case (TXBUF_RESET_ON_RATE_CHANGE) + "FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + "TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (TXGEARBOX_EN) + "FALSE" : TXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : TXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN); + #1 $finish; + end + endcase + + case (TXOUT_DIV) + 2 : TXOUT_DIV_BINARY = 3'b001; + 1 : TXOUT_DIV_BINARY = 3'b000; + 4 : TXOUT_DIV_BINARY = 3'b010; + 8 : TXOUT_DIV_BINARY = 3'b011; + 16 : TXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (TXPI_PPMCLK_SEL) + "TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1; + "TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL); + #1 $finish; + end + endcase + + case (TX_CLK25_DIV) + 7 : TX_CLK25_DIV_BINARY = 5'b00110; + 1 : TX_CLK25_DIV_BINARY = 5'b00000; + 2 : TX_CLK25_DIV_BINARY = 5'b00001; + 3 : TX_CLK25_DIV_BINARY = 5'b00010; + 4 : TX_CLK25_DIV_BINARY = 5'b00011; + 5 : TX_CLK25_DIV_BINARY = 5'b00100; + 6 : TX_CLK25_DIV_BINARY = 5'b00101; + 8 : TX_CLK25_DIV_BINARY = 5'b00111; + 9 : TX_CLK25_DIV_BINARY = 5'b01000; + 10 : TX_CLK25_DIV_BINARY = 5'b01001; + 11 : TX_CLK25_DIV_BINARY = 5'b01010; + 12 : TX_CLK25_DIV_BINARY = 5'b01011; + 13 : TX_CLK25_DIV_BINARY = 5'b01100; + 14 : TX_CLK25_DIV_BINARY = 5'b01101; + 15 : TX_CLK25_DIV_BINARY = 5'b01110; + 16 : TX_CLK25_DIV_BINARY = 5'b01111; + 17 : TX_CLK25_DIV_BINARY = 5'b10000; + 18 : TX_CLK25_DIV_BINARY = 5'b10001; + 19 : TX_CLK25_DIV_BINARY = 5'b10010; + 20 : TX_CLK25_DIV_BINARY = 5'b10011; + 21 : TX_CLK25_DIV_BINARY = 5'b10100; + 22 : TX_CLK25_DIV_BINARY = 5'b10101; + 23 : TX_CLK25_DIV_BINARY = 5'b10110; + 24 : TX_CLK25_DIV_BINARY = 5'b10111; + 25 : TX_CLK25_DIV_BINARY = 5'b11000; + 26 : TX_CLK25_DIV_BINARY = 5'b11001; + 27 : TX_CLK25_DIV_BINARY = 5'b11010; + 28 : TX_CLK25_DIV_BINARY = 5'b11011; + 29 : TX_CLK25_DIV_BINARY = 5'b11100; + 30 : TX_CLK25_DIV_BINARY = 5'b11101; + 31 : TX_CLK25_DIV_BINARY = 5'b11110; + 32 : TX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (TX_DATA_WIDTH) + 20 : TX_DATA_WIDTH_BINARY = 3'b011; + 16 : TX_DATA_WIDTH_BINARY = 3'b010; + 32 : TX_DATA_WIDTH_BINARY = 3'b100; + 40 : TX_DATA_WIDTH_BINARY = 3'b101; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", TX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (TX_DRIVE_MODE) + "DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000; + "PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001; + "PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE); + #1 $finish; + end + endcase + + case (TX_LOOPBACK_DRIVE_HIZ) + "FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0; + "TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ); + #1 $finish; + end + endcase + + case (TX_XCLK_SEL) + "TXUSR" : TX_XCLK_SEL_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL); + #1 $finish; + end + endcase + + if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1)) + ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE); + #1 $finish; + end + + if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1)) + ACJTAG_MODE_BINARY = ACJTAG_MODE; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE); + #1 $finish; + end + + if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1)) + ACJTAG_RESET_BINARY = ACJTAG_RESET; + else begin + $display("Attribute Syntax Error : The Attribute ACJTAG_RESET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET); + #1 $finish; + end + + if ((ADAPT_CFG0 >= 20'b00000000000000000000) && (ADAPT_CFG0 <= 20'b11111111111111111111)) + ADAPT_CFG0_BINARY = ADAPT_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute ADAPT_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 20'b00000000000000000000 to 20'b11111111111111111111.", ADAPT_CFG0); + #1 $finish; + end + + if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111)) + ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE); + #1 $finish; + end + + if ((ALIGN_COMMA_WORD >= 1) && (ALIGN_COMMA_WORD <= 2)) + ALIGN_COMMA_WORD_BINARY = ALIGN_COMMA_WORD; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 2.", ALIGN_COMMA_WORD); + #1 $finish; + end + + if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111)) + ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE); + #1 $finish; + end + + if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111)) + ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE); + #1 $finish; + end + + if ((CFOK_CFG >= 43'b0000000000000000000000000000000000000000000) && (CFOK_CFG <= 43'b1111111111111111111111111111111111111111111)) + CFOK_CFG_BINARY = CFOK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 43'b0000000000000000000000000000000000000000000 to 43'b1111111111111111111111111111111111111111111.", CFOK_CFG); + #1 $finish; + end + + if ((CFOK_CFG2 >= 7'b0000000) && (CFOK_CFG2 <= 7'b1111111)) + CFOK_CFG2_BINARY = CFOK_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG2); + #1 $finish; + end + + if ((CFOK_CFG3 >= 7'b0000000) && (CFOK_CFG3 <= 7'b1111111)) + CFOK_CFG3_BINARY = CFOK_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG3); + #1 $finish; + end + + if ((CFOK_CFG4 >= 1'b0) && (CFOK_CFG4 <= 1'b1)) + CFOK_CFG4_BINARY = CFOK_CFG4; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CFOK_CFG4); + #1 $finish; + end + + if ((CFOK_CFG5 >= 2'b00) && (CFOK_CFG5 <= 2'b11)) + CFOK_CFG5_BINARY = CFOK_CFG5; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CFOK_CFG5); + #1 $finish; + end + + if ((CFOK_CFG6 >= 4'b0000) && (CFOK_CFG6 <= 4'b1111)) + CFOK_CFG6_BINARY = CFOK_CFG6; + else begin + $display("Attribute Syntax Error : The Attribute CFOK_CFG6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CFOK_CFG6); + #1 $finish; + end + + if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14)) + CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE); + #1 $finish; + end + + if ((CLK_COMMON_SWING >= 1'b0) && (CLK_COMMON_SWING <= 1'b1)) + CLK_COMMON_SWING_BINARY = CLK_COMMON_SWING; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COMMON_SWING on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CLK_COMMON_SWING); + #1 $finish; + end + + if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60)) + CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT); + #1 $finish; + end + + if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60)) + CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT); + #1 $finish; + end + + if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31)) + CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111)) + CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111)) + CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111)) + CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111)) + CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111)) + CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111)) + CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111)) + CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111)) + CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111)) + CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111)) + CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE); + #1 $finish; + end + + if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1)) + ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL); + #1 $finish; + end + + if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111)) + ES_CONTROL_BINARY = ES_CONTROL; + else begin + $display("Attribute Syntax Error : The Attribute ES_CONTROL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL); + #1 $finish; + end + + if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111)) + ES_PMA_CFG_BINARY = ES_PMA_CFG; + else begin + $display("Attribute Syntax Error : The Attribute ES_PMA_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG); + #1 $finish; + end + + if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111)) + ES_PRESCALE_BINARY = ES_PRESCALE; + else begin + $display("Attribute Syntax Error : The Attribute ES_PRESCALE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE); + #1 $finish; + end + + if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111)) + ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET; + else begin + $display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET); + #1 $finish; + end + + if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111)) + FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE); + #1 $finish; + end + + if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111)) + FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG; + else begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG); + #1 $finish; + end + + if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111)) + GEARBOX_MODE_BINARY = GEARBOX_MODE; + else begin + $display("Attribute Syntax Error : The Attribute GEARBOX_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE); + #1 $finish; + end + + if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1)) + LOOPBACK_CFG_BINARY = LOOPBACK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG); + #1 $finish; + end + + if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11)) + OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV; + else begin + $display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV); + #1 $finish; + end + + if ((PMA_LOOPBACK_CFG >= 1'b0) && (PMA_LOOPBACK_CFG <= 1'b1)) + PMA_LOOPBACK_CFG_BINARY = PMA_LOOPBACK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute PMA_LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_LOOPBACK_CFG); + #1 $finish; + end + + if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11)) + PMA_RSV3_BINARY = PMA_RSV3; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3); + #1 $finish; + end + + if ((PMA_RSV4 >= 4'b0000) && (PMA_RSV4 <= 4'b1111)) + PMA_RSV4_BINARY = PMA_RSV4; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV4); + #1 $finish; + end + + if ((PMA_RSV5 >= 1'b0) && (PMA_RSV5 <= 1'b1)) + PMA_RSV5_BINARY = PMA_RSV5; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV5); + #1 $finish; + end + + if ((PMA_RSV6 >= 1'b0) && (PMA_RSV6 <= 1'b1)) + PMA_RSV6_BINARY = PMA_RSV6; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV6); + #1 $finish; + end + + if ((PMA_RSV7 >= 1'b0) && (PMA_RSV7 <= 1'b1)) + PMA_RSV7_BINARY = PMA_RSV7; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV7 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV7); + #1 $finish; + end + + if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111)) + RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME); + #1 $finish; + end + + if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111)) + RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT); + #1 $finish; + end + + if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111)) + RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT); + #1 $finish; + end + + if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63)) + RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW); + #1 $finish; + end + + if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63)) + RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW); + #1 $finish; + end + + if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111)) + RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME); + #1 $finish; + end + + if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111)) + RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME); + #1 $finish; + end + + if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1)) + RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1)) + RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111)) + RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG); + #1 $finish; + end + + if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1)) + RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111)) + RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME); + #1 $finish; + end + + if ((RXLPMRESET_TIME >= 7'b0000000) && (RXLPMRESET_TIME <= 7'b1111111)) + RXLPMRESET_TIME_BINARY = RXLPMRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXLPMRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXLPMRESET_TIME); + #1 $finish; + end + + if ((RXLPM_BIAS_STARTUP_DISABLE >= 1'b0) && (RXLPM_BIAS_STARTUP_DISABLE <= 1'b1)) + RXLPM_BIAS_STARTUP_DISABLE_BINARY = RXLPM_BIAS_STARTUP_DISABLE; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_BIAS_STARTUP_DISABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_BIAS_STARTUP_DISABLE); + #1 $finish; + end + + if ((RXLPM_CFG >= 4'b0000) && (RXLPM_CFG <= 4'b1111)) + RXLPM_CFG_BINARY = RXLPM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_CFG); + #1 $finish; + end + + if ((RXLPM_CFG1 >= 1'b0) && (RXLPM_CFG1 <= 1'b1)) + RXLPM_CFG1_BINARY = RXLPM_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CFG1); + #1 $finish; + end + + if ((RXLPM_CM_CFG >= 1'b0) && (RXLPM_CM_CFG <= 1'b1)) + RXLPM_CM_CFG_BINARY = RXLPM_CM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_CM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CM_CFG); + #1 $finish; + end + + if ((RXLPM_GC_CFG >= 9'b000000000) && (RXLPM_GC_CFG <= 9'b111111111)) + RXLPM_GC_CFG_BINARY = RXLPM_GC_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", RXLPM_GC_CFG); + #1 $finish; + end + + if ((RXLPM_GC_CFG2 >= 3'b000) && (RXLPM_GC_CFG2 <= 3'b111)) + RXLPM_GC_CFG2_BINARY = RXLPM_GC_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_GC_CFG2); + #1 $finish; + end + + if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111)) + RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG); + #1 $finish; + end + + if ((RXLPM_HF_CFG2 >= 5'b00000) && (RXLPM_HF_CFG2 <= 5'b11111)) + RXLPM_HF_CFG2_BINARY = RXLPM_HF_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_HF_CFG2); + #1 $finish; + end + + if ((RXLPM_HF_CFG3 >= 4'b0000) && (RXLPM_HF_CFG3 <= 4'b1111)) + RXLPM_HF_CFG3_BINARY = RXLPM_HF_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_HF_CFG3); + #1 $finish; + end + + if ((RXLPM_HOLD_DURING_EIDLE >= 1'b0) && (RXLPM_HOLD_DURING_EIDLE <= 1'b1)) + RXLPM_HOLD_DURING_EIDLE_BINARY = RXLPM_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RXLPM_INCM_CFG >= 1'b0) && (RXLPM_INCM_CFG <= 1'b1)) + RXLPM_INCM_CFG_BINARY = RXLPM_INCM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_INCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_INCM_CFG); + #1 $finish; + end + + if ((RXLPM_IPCM_CFG >= 1'b0) && (RXLPM_IPCM_CFG <= 1'b1)) + RXLPM_IPCM_CFG_BINARY = RXLPM_IPCM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_IPCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_IPCM_CFG); + #1 $finish; + end + + if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111)) + RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG); + #1 $finish; + end + + if ((RXLPM_LF_CFG2 >= 5'b00000) && (RXLPM_LF_CFG2 <= 5'b11111)) + RXLPM_LF_CFG2_BINARY = RXLPM_LF_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_LF_CFG2); + #1 $finish; + end + + if ((RXLPM_OSINT_CFG >= 3'b000) && (RXLPM_OSINT_CFG <= 3'b111)) + RXLPM_OSINT_CFG_BINARY = RXLPM_OSINT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_OSINT_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_OSINT_CFG); + #1 $finish; + end + + if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111)) + RXOOB_CFG_BINARY = RXOOB_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG); + #1 $finish; + end + + if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111)) + RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME); + #1 $finish; + end + + if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111)) + RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT; + else begin + $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT); + #1 $finish; + end + + if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111)) + RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME); + #1 $finish; + end + + if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111)) + RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL); + #1 $finish; + end + + if ((RXPI_CFG0 >= 3'b000) && (RXPI_CFG0 <= 3'b111)) + RXPI_CFG0_BINARY = RXPI_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG0); + #1 $finish; + end + + if ((RXPI_CFG1 >= 1'b0) && (RXPI_CFG1 <= 1'b1)) + RXPI_CFG1_BINARY = RXPI_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG1); + #1 $finish; + end + + if ((RXPI_CFG2 >= 1'b0) && (RXPI_CFG2 <= 1'b1)) + RXPI_CFG2_BINARY = RXPI_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute RXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG2); + #1 $finish; + end + + if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111)) + RXPMARESET_TIME_BINARY = RXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME); + #1 $finish; + end + + if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1)) + RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK); + #1 $finish; + end + + if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15)) + RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT); + #1 $finish; + end + + if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1)) + RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE); + #1 $finish; + end + + if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1)) + RXSYNC_OVRD_BINARY = RXSYNC_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD); + #1 $finish; + end + + if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1)) + RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA; + else begin + $display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA); + #1 $finish; + end + + if ((RX_BIAS_CFG >= 16'b0000000000000000) && (RX_BIAS_CFG <= 16'b1111111111111111)) + RX_BIAS_CFG_BINARY = RX_BIAS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", RX_BIAS_CFG); + #1 $finish; + end + + if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111)) + RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG); + #1 $finish; + end + + if ((RX_CLKMUX_EN >= 1'b0) && (RX_CLKMUX_EN <= 1'b1)) + RX_CLKMUX_EN_BINARY = RX_CLKMUX_EN; + else begin + $display("Attribute Syntax Error : The Attribute RX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_EN); + #1 $finish; + end + + if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11)) + RX_CM_SEL_BINARY = RX_CM_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL); + #1 $finish; + end + + if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111)) + RX_CM_TRIM_BINARY = RX_CM_TRIM; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_TRIM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM); + #1 $finish; + end + + if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111)) + RX_DDI_SEL_BINARY = RX_DDI_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_DDI_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL); + #1 $finish; + end + + if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111)) + RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG); + #1 $finish; + end + + if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111)) + RX_OS_CFG_BINARY = RX_OS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_OS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG); + #1 $finish; + end + + if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127)) + SAS_MAX_COM_BINARY = SAS_MAX_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MAX_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM); + #1 $finish; + end + + if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63)) + SAS_MIN_COM_BINARY = SAS_MIN_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MIN_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM); + #1 $finish; + end + + if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111)) + SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN); + #1 $finish; + end + + if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111)) + SATA_BURST_VAL_BINARY = SATA_BURST_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL); + #1 $finish; + end + + if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111)) + SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL); + #1 $finish; + end + + if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63)) + SATA_MAX_BURST_BINARY = SATA_MAX_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST); + #1 $finish; + end + + if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63)) + SATA_MAX_INIT_BINARY = SATA_MAX_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT); + #1 $finish; + end + + if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63)) + SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE); + #1 $finish; + end + + if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61)) + SATA_MIN_BURST_BINARY = SATA_MIN_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST); + #1 $finish; + end + + if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63)) + SATA_MIN_INIT_BINARY = SATA_MIN_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT); + #1 $finish; + end + + if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63)) + SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE); + #1 $finish; + end + + if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111)) + TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG); + #1 $finish; + end + + if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111)) + TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD); + #1 $finish; + end + + if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1)) + TXOOB_CFG_BINARY = TXOOB_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG); + #1 $finish; + end + + if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111)) + TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME); + #1 $finish; + end + + if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111)) + TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL); + #1 $finish; + end + + if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11)) + TXPI_CFG0_BINARY = TXPI_CFG0; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0); + #1 $finish; + end + + if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11)) + TXPI_CFG1_BINARY = TXPI_CFG1; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1); + #1 $finish; + end + + if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11)) + TXPI_CFG2_BINARY = TXPI_CFG2; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2); + #1 $finish; + end + + if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1)) + TXPI_CFG3_BINARY = TXPI_CFG3; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3); + #1 $finish; + end + + if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1)) + TXPI_CFG4_BINARY = TXPI_CFG4; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4); + #1 $finish; + end + + if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111)) + TXPI_CFG5_BINARY = TXPI_CFG5; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5); + #1 $finish; + end + + if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1)) + TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL); + #1 $finish; + end + + if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1)) + TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL); + #1 $finish; + end + + if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111)) + TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG); + #1 $finish; + end + + if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111)) + TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM; + else begin + $display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM); + #1 $finish; + end + + if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111)) + TXPMARESET_TIME_BINARY = TXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME); + #1 $finish; + end + + if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1)) + TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE); + #1 $finish; + end + + if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1)) + TXSYNC_OVRD_BINARY = TXSYNC_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD); + #1 $finish; + end + + if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1)) + TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA; + else begin + $display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA); + #1 $finish; + end + + if ((TX_CLKMUX_EN >= 1'b0) && (TX_CLKMUX_EN <= 1'b1)) + TX_CLKMUX_EN_BINARY = TX_CLKMUX_EN; + else begin + $display("Attribute Syntax Error : The Attribute TX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_EN); + #1 $finish; + end + + if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111)) + TX_DEEMPH0_BINARY = TX_DEEMPH0; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0); + #1 $finish; + end + + if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111)) + TX_DEEMPH1_BINARY = TX_DEEMPH1; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1); + #1 $finish; + end + + if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111)) + TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY); + #1 $finish; + end + + if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111)) + TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY); + #1 $finish; + end + + if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1)) + TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL); + #1 $finish; + end + + if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111)) + TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0); + #1 $finish; + end + + if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111)) + TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1); + #1 $finish; + end + + if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111)) + TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2); + #1 $finish; + end + + if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111)) + TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3); + #1 $finish; + end + + if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111)) + TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4); + #1 $finish; + end + + if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111)) + TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0); + #1 $finish; + end + + if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111)) + TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1); + #1 $finish; + end + + if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111)) + TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2); + #1 $finish; + end + + if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111)) + TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3); + #1 $finish; + end + + if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111)) + TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4); + #1 $finish; + end + + if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1)) + TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE; + else begin + $display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE); + #1 $finish; + end + + if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111)) + TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF; + else begin + $display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF); + #1 $finish; + end + + if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1)) + UCODEER_CLR_BINARY = UCODEER_CLR; + else begin + $display("Attribute Syntax Error : The Attribute UCODEER_CLR on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR); + #1 $finish; + end + + if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1)) + USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL; + else begin + $display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL); + #1 $finish; + end + + end + + wire [14:0] delay_DMONITOROUT; + wire [15:0] delay_DRPDO; + wire [15:0] delay_PCSRSVDOUT; + wire [1:0] delay_RXCLKCORCNT; + wire [1:0] delay_RXDATAVALID; + wire [1:0] delay_RXSTARTOFSEQ; + wire [1:0] delay_TXBUFSTATUS; + wire [2:0] delay_RXBUFSTATUS; + wire [2:0] delay_RXHEADER; + wire [2:0] delay_RXSTATUS; + wire [31:0] delay_RXDATA; + wire [3:0] delay_RXCHARISCOMMA; + wire [3:0] delay_RXCHARISK; + wire [3:0] delay_RXCHBONDO; + wire [3:0] delay_RXDISPERR; + wire [3:0] delay_RXNOTINTABLE; + wire [4:0] delay_RXPHMONITOR; + wire [4:0] delay_RXPHSLIPMONITOR; + wire delay_DRPRDY; + wire delay_EYESCANDATAERROR; + wire delay_GTPTXN; + wire delay_GTPTXP; + wire delay_PHYSTATUS; + wire delay_PMARSVDOUT0; + wire delay_PMARSVDOUT1; + wire delay_RXBYTEISALIGNED; + wire delay_RXBYTEREALIGN; + wire delay_RXCDRLOCK; + wire delay_RXCHANBONDSEQ; + wire delay_RXCHANISALIGNED; + wire delay_RXCHANREALIGN; + wire delay_RXCOMINITDET; + wire delay_RXCOMMADET; + wire delay_RXCOMSASDET; + wire delay_RXCOMWAKEDET; + wire delay_RXDLYSRESETDONE; + wire delay_RXELECIDLE; + wire delay_RXHEADERVALID; + wire delay_RXOSINTDONE; + wire delay_RXOSINTSTARTED; + wire delay_RXOSINTSTROBEDONE; + wire delay_RXOSINTSTROBESTARTED; + wire delay_RXOUTCLK; + wire delay_RXOUTCLKFABRIC; + wire delay_RXOUTCLKPCS; + wire delay_RXPHALIGNDONE; + wire delay_RXPMARESETDONE; + wire delay_RXPRBSERR; + wire delay_RXRATEDONE; + wire delay_RXRESETDONE; + wire delay_RXSYNCDONE; + wire delay_RXSYNCOUT; + wire delay_RXVALID; + wire delay_TXCOMFINISH; + wire delay_TXDLYSRESETDONE; + wire delay_TXGEARBOXREADY; + wire delay_TXOUTCLK; + wire delay_TXOUTCLKFABRIC; + wire delay_TXOUTCLKPCS; + wire delay_TXPHALIGNDONE; + wire delay_TXPHINITDONE; + wire delay_TXPMARESETDONE; + wire delay_TXRATEDONE; + wire delay_TXRESETDONE; + wire delay_TXSYNCDONE; + wire delay_TXSYNCOUT; + + wire [13:0] delay_RXADAPTSELTEST; + wire [15:0] delay_DRPDI; + wire [15:0] delay_GTRSVD; + wire [15:0] delay_PCSRSVDIN; + wire [19:0] delay_TSTIN; + wire [1:0] delay_RXELECIDLEMODE; + wire [1:0] delay_RXPD; + wire [1:0] delay_RXSYSCLKSEL; + wire [1:0] delay_TXPD; + wire [1:0] delay_TXSYSCLKSEL; + wire [2:0] delay_LOOPBACK; + wire [2:0] delay_RXCHBONDLEVEL; + wire [2:0] delay_RXOUTCLKSEL; + wire [2:0] delay_RXPRBSSEL; + wire [2:0] delay_RXRATE; + wire [2:0] delay_TXBUFDIFFCTRL; + wire [2:0] delay_TXHEADER; + wire [2:0] delay_TXMARGIN; + wire [2:0] delay_TXOUTCLKSEL; + wire [2:0] delay_TXPRBSSEL; + wire [2:0] delay_TXRATE; + wire [31:0] delay_TXDATA; + wire [3:0] delay_RXCHBONDI; + wire [3:0] delay_RXOSINTCFG; + wire [3:0] delay_RXOSINTID0; + wire [3:0] delay_TX8B10BBYPASS; + wire [3:0] delay_TXCHARDISPMODE; + wire [3:0] delay_TXCHARDISPVAL; + wire [3:0] delay_TXCHARISK; + wire [3:0] delay_TXDIFFCTRL; + wire [4:0] delay_TXPIPPMSTEPSIZE; + wire [4:0] delay_TXPOSTCURSOR; + wire [4:0] delay_TXPRECURSOR; + wire [6:0] delay_TXMAINCURSOR; + wire [6:0] delay_TXSEQUENCE; + wire [8:0] delay_DRPADDR; + wire delay_CFGRESET; + wire delay_CLKRSVD0; + wire delay_CLKRSVD1; + wire delay_DMONFIFORESET; + wire delay_DMONITORCLK; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_EYESCANMODE; + wire delay_EYESCANRESET; + wire delay_EYESCANTRIGGER; + wire delay_GTPRXN; + wire delay_GTPRXP; + wire delay_GTRESETSEL; + wire delay_GTRXRESET; + wire delay_GTTXRESET; + wire delay_PLL0CLK; + wire delay_PLL0REFCLK; + wire delay_PLL1CLK; + wire delay_PLL1REFCLK; + wire delay_PMARSVDIN0; + wire delay_PMARSVDIN1; + wire delay_PMARSVDIN2; + wire delay_PMARSVDIN3; + wire delay_PMARSVDIN4; + wire delay_RESETOVRD; + wire delay_RX8B10BEN; + wire delay_RXBUFRESET; + wire delay_RXCDRFREQRESET; + wire delay_RXCDRHOLD; + wire delay_RXCDROVRDEN; + wire delay_RXCDRRESET; + wire delay_RXCDRRESETRSV; + wire delay_RXCHBONDEN; + wire delay_RXCHBONDMASTER; + wire delay_RXCHBONDSLAVE; + wire delay_RXCOMMADETEN; + wire delay_RXDDIEN; + wire delay_RXDFEXYDEN; + wire delay_RXDLYBYPASS; + wire delay_RXDLYEN; + wire delay_RXDLYOVRDEN; + wire delay_RXDLYSRESET; + wire delay_RXGEARBOXSLIP; + wire delay_RXLPMHFHOLD; + wire delay_RXLPMHFOVRDEN; + wire delay_RXLPMLFHOLD; + wire delay_RXLPMLFOVRDEN; + wire delay_RXLPMOSINTNTRLEN; + wire delay_RXLPMRESET; + wire delay_RXMCOMMAALIGNEN; + wire delay_RXOOBRESET; + wire delay_RXOSCALRESET; + wire delay_RXOSHOLD; + wire delay_RXOSINTEN; + wire delay_RXOSINTHOLD; + wire delay_RXOSINTNTRLEN; + wire delay_RXOSINTOVRDEN; + wire delay_RXOSINTPD; + wire delay_RXOSINTSTROBE; + wire delay_RXOSINTTESTOVRDEN; + wire delay_RXOSOVRDEN; + wire delay_RXPCOMMAALIGNEN; + wire delay_RXPCSRESET; + wire delay_RXPHALIGN; + wire delay_RXPHALIGNEN; + wire delay_RXPHDLYPD; + wire delay_RXPHDLYRESET; + wire delay_RXPHOVRDEN; + wire delay_RXPMARESET; + wire delay_RXPOLARITY; + wire delay_RXPRBSCNTRESET; + wire delay_RXRATEMODE; + wire delay_RXSLIDE; + wire delay_RXSYNCALLIN; + wire delay_RXSYNCIN; + wire delay_RXSYNCMODE; + wire delay_RXUSERRDY; + wire delay_RXUSRCLK2; + wire delay_RXUSRCLK; + wire delay_SETERRSTATUS; + wire delay_SIGVALIDCLK; + wire delay_TX8B10BEN; + wire delay_TXCOMINIT; + wire delay_TXCOMSAS; + wire delay_TXCOMWAKE; + wire delay_TXDEEMPH; + wire delay_TXDETECTRX; + wire delay_TXDIFFPD; + wire delay_TXDLYBYPASS; + wire delay_TXDLYEN; + wire delay_TXDLYHOLD; + wire delay_TXDLYOVRDEN; + wire delay_TXDLYSRESET; + wire delay_TXDLYUPDOWN; + wire delay_TXELECIDLE; + wire delay_TXINHIBIT; + wire delay_TXPCSRESET; + wire delay_TXPDELECIDLEMODE; + wire delay_TXPHALIGN; + wire delay_TXPHALIGNEN; + wire delay_TXPHDLYPD; + wire delay_TXPHDLYRESET; + wire delay_TXPHDLYTSTCLK; + wire delay_TXPHINIT; + wire delay_TXPHOVRDEN; + wire delay_TXPIPPMEN; + wire delay_TXPIPPMOVRDEN; + wire delay_TXPIPPMPD; + wire delay_TXPIPPMSEL; + wire delay_TXPISOPD; + wire delay_TXPMARESET; + wire delay_TXPOLARITY; + wire delay_TXPOSTCURSORINV; + wire delay_TXPRBSFORCEERR; + wire delay_TXPRECURSORINV; + wire delay_TXRATEMODE; + wire delay_TXSTARTSEQ; + wire delay_TXSWING; + wire delay_TXSYNCALLIN; + wire delay_TXSYNCIN; + wire delay_TXSYNCMODE; + wire delay_TXUSERRDY; + wire delay_TXUSRCLK2; + wire delay_TXUSRCLK; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= DRPEN; + drpwe_r1 <= DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((DRPWE === 1'b1) && (DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge DRPCLK) + //end drp monitor + + reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED; + reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED; + reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED; + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED; + reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED; + reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED; + reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED; + reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED; + reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED; + + assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK; + assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK; + + assign #(out_delay) DMONITOROUT = delay_DMONITOROUT; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPRDY = delay_DRPRDY; + assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR; + assign #(out_delay) GTPTXN = delay_GTPTXN; + assign #(out_delay) GTPTXP = delay_GTPTXP; + assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT; + assign #(out_delay) PHYSTATUS = delay_PHYSTATUS; + assign #(out_delay) PMARSVDOUT0 = delay_PMARSVDOUT0; + assign #(out_delay) PMARSVDOUT1 = delay_PMARSVDOUT1; + assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS; + assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED; + assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN; + assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK; + assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ; + assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED; + assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN; + assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA; + assign #(out_delay) RXCHARISK = delay_RXCHARISK; + assign #(out_delay) RXCHBONDO = delay_RXCHBONDO; + assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT; + assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET; + assign #(out_delay) RXCOMMADET = delay_RXCOMMADET; + assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET; + assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET; + assign #(out_delay) RXDATA = delay_RXDATA; + assign #(out_delay) RXDATAVALID = delay_RXDATAVALID; + assign #(out_delay) RXDISPERR = delay_RXDISPERR; + assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE; + assign #(out_delay) RXELECIDLE = delay_RXELECIDLE; + assign #(out_delay) RXHEADER = delay_RXHEADER; + assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID; + assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE; + assign #(out_delay) RXOSINTDONE = delay_RXOSINTDONE; + assign #(out_delay) RXOSINTSTARTED = delay_RXOSINTSTARTED; + assign #(out_delay) RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE; + assign #(out_delay) RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED; + assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC; + assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS; + assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE; + assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR; + assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR; + assign #(out_delay) RXPMARESETDONE = delay_RXPMARESETDONE; + assign #(out_delay) RXPRBSERR = delay_RXPRBSERR; + assign #(out_delay) RXRATEDONE = delay_RXRATEDONE; + assign #(out_delay) RXRESETDONE = delay_RXRESETDONE; + assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ; + assign #(out_delay) RXSTATUS = delay_RXSTATUS; + assign #(out_delay) RXSYNCDONE = delay_RXSYNCDONE; + assign #(out_delay) RXSYNCOUT = delay_RXSYNCOUT; + assign #(out_delay) RXVALID = delay_RXVALID; + assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS; + assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH; + assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE; + assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY; + assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC; + assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS; + assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE; + assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE; + assign #(out_delay) TXPMARESETDONE = delay_TXPMARESETDONE; + assign #(out_delay) TXRATEDONE = delay_TXRATEDONE; + assign #(out_delay) TXRESETDONE = delay_TXRESETDONE; + assign #(out_delay) TXSYNCDONE = delay_TXSYNCDONE; + assign #(out_delay) TXSYNCOUT = delay_TXSYNCOUT; + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG; + assign #(INCLK_DELAY) delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG; + assign #(INCLK_DELAY) delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_PLL0CLK = PLL0CLK; + assign #(INCLK_DELAY) delay_PLL1CLK = PLL1CLK; + assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK2_INVERTED_REG; + assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG; + assign #(INCLK_DELAY) delay_SIGVALIDCLK = SIGVALIDCLK^ IS_SIGVALIDCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK; + assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2; + + assign #(in_delay) delay_CFGRESET = CFGRESET; + assign #(in_delay) delay_DMONFIFORESET = DMONFIFORESET; + assign #(in_delay) delay_DRPADDR = DRPADDR; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPEN = DRPEN; + assign #(in_delay) delay_DRPWE = DRPWE; + assign #(in_delay) delay_EYESCANMODE = EYESCANMODE; + assign #(in_delay) delay_EYESCANRESET = EYESCANRESET; + assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign #(in_delay) delay_GTPRXN = GTPRXN; + assign #(in_delay) delay_GTPRXP = GTPRXP; + assign #(in_delay) delay_GTRESETSEL = GTRESETSEL; + assign #(in_delay) delay_GTRSVD = GTRSVD; + assign #(in_delay) delay_GTRXRESET = GTRXRESET; + assign #(in_delay) delay_GTTXRESET = GTTXRESET; + assign #(in_delay) delay_LOOPBACK = LOOPBACK; + assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN; + assign #(in_delay) delay_PLL0REFCLK = PLL0REFCLK; + assign #(in_delay) delay_PLL1REFCLK = PLL1REFCLK; + assign #(in_delay) delay_PMARSVDIN0 = PMARSVDIN0; + assign #(in_delay) delay_PMARSVDIN1 = PMARSVDIN1; + assign #(in_delay) delay_PMARSVDIN2 = PMARSVDIN2; + assign #(in_delay) delay_PMARSVDIN3 = PMARSVDIN3; + assign #(in_delay) delay_PMARSVDIN4 = PMARSVDIN4; + assign #(in_delay) delay_RESETOVRD = RESETOVRD; + assign #(in_delay) delay_RX8B10BEN = RX8B10BEN; + assign #(in_delay) delay_RXADAPTSELTEST = RXADAPTSELTEST; + assign #(in_delay) delay_RXBUFRESET = RXBUFRESET; + assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD; + assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN; + assign #(in_delay) delay_RXCDRRESET = RXCDRRESET; + assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV; + assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN; + assign #(in_delay) delay_RXCHBONDI = RXCHBONDI; + assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL; + assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER; + assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE; + assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN; + assign #(in_delay) delay_RXDDIEN = RXDDIEN; + assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN; + assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS; + assign #(in_delay) delay_RXDLYEN = RXDLYEN; + assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET; + assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP; + assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign #(in_delay) delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN; + assign #(in_delay) delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN; + assign #(in_delay) delay_RXLPMRESET = RXLPMRESET; + assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN; + assign #(in_delay) delay_RXOOBRESET = RXOOBRESET; + assign #(in_delay) delay_RXOSCALRESET = RXOSCALRESET; + assign #(in_delay) delay_RXOSHOLD = RXOSHOLD; + assign #(in_delay) delay_RXOSINTCFG = RXOSINTCFG; + assign #(in_delay) delay_RXOSINTEN = RXOSINTEN; + assign #(in_delay) delay_RXOSINTHOLD = RXOSINTHOLD; + assign #(in_delay) delay_RXOSINTID0 = RXOSINTID0; + assign #(in_delay) delay_RXOSINTNTRLEN = RXOSINTNTRLEN; + assign #(in_delay) delay_RXOSINTOVRDEN = RXOSINTOVRDEN; + assign #(in_delay) delay_RXOSINTPD = RXOSINTPD; + assign #(in_delay) delay_RXOSINTSTROBE = RXOSINTSTROBE; + assign #(in_delay) delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; + assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN; + assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN; + assign #(in_delay) delay_RXPCSRESET = RXPCSRESET; + assign #(in_delay) delay_RXPD = RXPD; + assign #(in_delay) delay_RXPHALIGN = RXPHALIGN; + assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN; + assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD; + assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET; + assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN; + assign #(in_delay) delay_RXPMARESET = RXPMARESET; + assign #(in_delay) delay_RXPOLARITY = RXPOLARITY; + assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET; + assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL; + assign #(in_delay) delay_RXRATE = RXRATE; + assign #(in_delay) delay_RXRATEMODE = RXRATEMODE; + assign #(in_delay) delay_RXSLIDE = RXSLIDE; + assign #(in_delay) delay_RXSYNCALLIN = RXSYNCALLIN; + assign #(in_delay) delay_RXSYNCIN = RXSYNCIN; + assign #(in_delay) delay_RXSYNCMODE = RXSYNCMODE; + assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign #(in_delay) delay_RXUSERRDY = RXUSERRDY; + assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS; + assign #(in_delay) delay_TSTIN = TSTIN; + assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS; + assign #(in_delay) delay_TX8B10BEN = TX8B10BEN; + assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE; + assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL; + assign #(in_delay) delay_TXCHARISK = TXCHARISK; + assign #(in_delay) delay_TXCOMINIT = TXCOMINIT; + assign #(in_delay) delay_TXCOMSAS = TXCOMSAS; + assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE; + assign #(in_delay) delay_TXDATA = TXDATA; + assign #(in_delay) delay_TXDEEMPH = TXDEEMPH; + assign #(in_delay) delay_TXDETECTRX = TXDETECTRX; + assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL; + assign #(in_delay) delay_TXDIFFPD = TXDIFFPD; + assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS; + assign #(in_delay) delay_TXDLYEN = TXDLYEN; + assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD; + assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET; + assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN; + assign #(in_delay) delay_TXELECIDLE = TXELECIDLE; + assign #(in_delay) delay_TXHEADER = TXHEADER; + assign #(in_delay) delay_TXINHIBIT = TXINHIBIT; + assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR; + assign #(in_delay) delay_TXMARGIN = TXMARGIN; + assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign #(in_delay) delay_TXPCSRESET = TXPCSRESET; + assign #(in_delay) delay_TXPD = TXPD; + assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign #(in_delay) delay_TXPHALIGN = TXPHALIGN; + assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN; + assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD; + assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET; + assign #(in_delay) delay_TXPHINIT = TXPHINIT; + assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN; + assign #(in_delay) delay_TXPIPPMEN = TXPIPPMEN; + assign #(in_delay) delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN; + assign #(in_delay) delay_TXPIPPMPD = TXPIPPMPD; + assign #(in_delay) delay_TXPIPPMSEL = TXPIPPMSEL; + assign #(in_delay) delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE; + assign #(in_delay) delay_TXPISOPD = TXPISOPD; + assign #(in_delay) delay_TXPMARESET = TXPMARESET; + assign #(in_delay) delay_TXPOLARITY = TXPOLARITY; + assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR; + assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL; + assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR; + assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV; + assign #(in_delay) delay_TXRATE = TXRATE; + assign #(in_delay) delay_TXRATEMODE = TXRATEMODE; + assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE; + assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ; + assign #(in_delay) delay_TXSWING = TXSWING; + assign #(in_delay) delay_TXSYNCALLIN = TXSYNCALLIN; + assign #(in_delay) delay_TXSYNCIN = TXSYNCIN; + assign #(in_delay) delay_TXSYNCMODE = TXSYNCMODE; + assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign #(in_delay) delay_TXUSERRDY = TXUSERRDY; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_CFGRESET = CFGRESET; + assign delay_CLKRSVD0 = CLKRSVD0; + assign delay_CLKRSVD1 = CLKRSVD1; + assign delay_DMONFIFORESET = DMONFIFORESET; + assign delay_DMONITORCLK = DMONITORCLK; + assign delay_EYESCANMODE = EYESCANMODE; + assign delay_EYESCANRESET = EYESCANRESET; + assign delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign delay_GTPRXN = GTPRXN; + assign delay_GTPRXP = GTPRXP; + assign delay_GTRESETSEL = GTRESETSEL; + assign delay_GTRSVD = GTRSVD; + assign delay_GTRXRESET = GTRXRESET; + assign delay_GTTXRESET = GTTXRESET; + assign delay_LOOPBACK = LOOPBACK; + assign delay_PCSRSVDIN = PCSRSVDIN; + assign delay_PLL0CLK = PLL0CLK; + assign delay_PLL0REFCLK = PLL0REFCLK; + assign delay_PLL1CLK = PLL1CLK; + assign delay_PLL1REFCLK = PLL1REFCLK; + assign delay_PMARSVDIN0 = PMARSVDIN0; + assign delay_PMARSVDIN1 = PMARSVDIN1; + assign delay_PMARSVDIN2 = PMARSVDIN2; + assign delay_PMARSVDIN3 = PMARSVDIN3; + assign delay_PMARSVDIN4 = PMARSVDIN4; + assign delay_RESETOVRD = RESETOVRD; + assign delay_RXADAPTSELTEST = RXADAPTSELTEST; + assign delay_RXBUFRESET = RXBUFRESET; + assign delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign delay_RXCDRHOLD = RXCDRHOLD; + assign delay_RXCDROVRDEN = RXCDROVRDEN; + assign delay_RXCDRRESET = RXCDRRESET; + assign delay_RXCDRRESETRSV = RXCDRRESETRSV; + assign delay_RXCHBONDI = RXCHBONDI; + assign delay_RXDDIEN = RXDDIEN; + assign delay_RXDFEXYDEN = RXDFEXYDEN; + assign delay_RXDLYBYPASS = RXDLYBYPASS; + assign delay_RXDLYEN = RXDLYEN; + assign delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign delay_RXDLYSRESET = RXDLYSRESET; + assign delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN; + assign delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN; + assign delay_RXLPMRESET = RXLPMRESET; + assign delay_RXOOBRESET = RXOOBRESET; + assign delay_RXOSCALRESET = RXOSCALRESET; + assign delay_RXOSHOLD = RXOSHOLD; + assign delay_RXOSINTCFG = RXOSINTCFG; + assign delay_RXOSINTEN = RXOSINTEN; + assign delay_RXOSINTHOLD = RXOSINTHOLD; + assign delay_RXOSINTID0 = RXOSINTID0; + assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN; + assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN; + assign delay_RXOSINTPD = RXOSINTPD; + assign delay_RXOSINTSTROBE = RXOSINTSTROBE; + assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; + assign delay_RXOSOVRDEN = RXOSOVRDEN; + assign delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign delay_RXPCSRESET = RXPCSRESET; + assign delay_RXPD = RXPD; + assign delay_RXPHALIGN = RXPHALIGN; + assign delay_RXPHALIGNEN = RXPHALIGNEN; + assign delay_RXPHDLYPD = RXPHDLYPD; + assign delay_RXPHDLYRESET = RXPHDLYRESET; + assign delay_RXPHOVRDEN = RXPHOVRDEN; + assign delay_RXPMARESET = RXPMARESET; + assign delay_RXRATEMODE = RXRATEMODE; + assign delay_RXSYNCALLIN = RXSYNCALLIN; + assign delay_RXSYNCIN = RXSYNCIN; + assign delay_RXSYNCMODE = RXSYNCMODE; + assign delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign delay_RXUSERRDY = RXUSERRDY; + assign delay_SIGVALIDCLK = SIGVALIDCLK; + assign delay_TSTIN = TSTIN; + assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign delay_TXDEEMPH = TXDEEMPH; + assign delay_TXDIFFCTRL = TXDIFFCTRL; + assign delay_TXDIFFPD = TXDIFFPD; + assign delay_TXDLYBYPASS = TXDLYBYPASS; + assign delay_TXDLYEN = TXDLYEN; + assign delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign delay_TXDLYSRESET = TXDLYSRESET; + assign delay_TXMAINCURSOR = TXMAINCURSOR; + assign delay_TXMARGIN = TXMARGIN; + assign delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign delay_TXPCSRESET = TXPCSRESET; + assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign delay_TXPHALIGN = TXPHALIGN; + assign delay_TXPHALIGNEN = TXPHALIGNEN; + assign delay_TXPHDLYPD = TXPHDLYPD; + assign delay_TXPHDLYRESET = TXPHDLYRESET; + assign delay_TXPHINIT = TXPHINIT; + assign delay_TXPHOVRDEN = TXPHOVRDEN; + assign delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN; + assign delay_TXPIPPMPD = TXPIPPMPD; + assign delay_TXPIPPMSEL = TXPIPPMSEL; + assign delay_TXPISOPD = TXPISOPD; + assign delay_TXPMARESET = TXPMARESET; + assign delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign delay_TXPRECURSOR = TXPRECURSOR; + assign delay_TXPRECURSORINV = TXPRECURSORINV; + assign delay_TXRATEMODE = TXRATEMODE; + assign delay_TXSWING = TXSWING; + assign delay_TXSYNCALLIN = TXSYNCALLIN; + assign delay_TXSYNCIN = TXSYNCIN; + assign delay_TXSYNCMODE = TXSYNCMODE; + assign delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign delay_TXUSERRDY = TXUSERRDY; + + wire drpclk_en_p; + wire drpclk_en_n; + wire rxusrclk2_en_p; + wire rxusrclk2_en_n; + wire rxusrclk_en_p; + wire rxusrclk_en_n; + wire txphdlytstclk_en_p; + wire txphdlytstclk_en_n; + wire txusrclk2_en_p; + wire txusrclk2_en_n; + wire txusrclk_en_p; + wire txusrclk_en_n; + + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; + assign rxusrclk2_en_p = ~IS_RXUSRCLK2_INVERTED; + assign rxusrclk2_en_n = IS_RXUSRCLK2_INVERTED; + assign rxusrclk_en_p = ~IS_RXUSRCLK_INVERTED; + assign rxusrclk_en_n = IS_RXUSRCLK_INVERTED; + assign txphdlytstclk_en_p = ~IS_TXPHDLYTSTCLK_INVERTED; + assign txphdlytstclk_en_n = IS_TXPHDLYTSTCLK_INVERTED; + assign txusrclk2_en_p = ~IS_TXUSRCLK2_INVERTED; + assign txusrclk2_en_n = IS_TXUSRCLK2_INVERTED; + assign txusrclk_en_p = ~IS_TXUSRCLK_INVERTED; + assign txusrclk_en_n = IS_TXUSRCLK_INVERTED; +`endif + + B_GTPE2_CHANNEL #( + .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE), + .ACJTAG_MODE (ACJTAG_MODE), + .ACJTAG_RESET (ACJTAG_RESET), + .ADAPT_CFG0 (ADAPT_CFG0), + .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CFOK_CFG (CFOK_CFG), + .CFOK_CFG2 (CFOK_CFG2), + .CFOK_CFG3 (CFOK_CFG3), + .CFOK_CFG4 (CFOK_CFG4), + .CFOK_CFG5 (CFOK_CFG5), + .CFOK_CFG6 (CFOK_CFG6), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN), + .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN), + .CLK_COMMON_SWING (CLK_COMMON_SWING), + .CLK_CORRECT_USE (CLK_CORRECT_USE), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE), + .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY), + .DMONITOR_CFG (DMONITOR_CFG), + .ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL), + .ES_CONTROL (ES_CONTROL), + .ES_ERRDET_EN (ES_ERRDET_EN), + .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN), + .ES_HORZ_OFFSET (ES_HORZ_OFFSET), + .ES_PMA_CFG (ES_PMA_CFG), + .ES_PRESCALE (ES_PRESCALE), + .ES_QUALIFIER (ES_QUALIFIER), + .ES_QUAL_MASK (ES_QUAL_MASK), + .ES_SDATA_MASK (ES_SDATA_MASK), + .ES_VERT_OFFSET (ES_VERT_OFFSET), + .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE), + .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG), + .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN), + .GEARBOX_MODE (GEARBOX_MODE), + .LOOPBACK_CFG (LOOPBACK_CFG), + .OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV), + .PCS_PCIE_EN (PCS_PCIE_EN), + .PCS_RSVD_ATTR (PCS_RSVD_ATTR), + .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2), + .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2), + .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2), + .PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG), + .PMA_RSV (PMA_RSV), + .PMA_RSV2 (PMA_RSV2), + .PMA_RSV3 (PMA_RSV3), + .PMA_RSV4 (PMA_RSV4), + .PMA_RSV5 (PMA_RSV5), + .PMA_RSV6 (PMA_RSV6), + .PMA_RSV7 (PMA_RSV7), + .RXBUFRESET_TIME (RXBUFRESET_TIME), + .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE), + .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT), + .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE), + .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN), + .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE), + .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE), + .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW), + .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME), + .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME), + .RXCDR_CFG (RXCDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE), + .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE), + .RXCDR_LOCK_CFG (RXCDR_LOCK_CFG), + .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE), + .RXDLY_CFG (RXDLY_CFG), + .RXDLY_LCFG (RXDLY_LCFG), + .RXDLY_TAP_CFG (RXDLY_TAP_CFG), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (RXISCANRESET_TIME), + .RXLPMRESET_TIME (RXLPMRESET_TIME), + .RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE), + .RXLPM_CFG (RXLPM_CFG), + .RXLPM_CFG1 (RXLPM_CFG1), + .RXLPM_CM_CFG (RXLPM_CM_CFG), + .RXLPM_GC_CFG (RXLPM_GC_CFG), + .RXLPM_GC_CFG2 (RXLPM_GC_CFG2), + .RXLPM_HF_CFG (RXLPM_HF_CFG), + .RXLPM_HF_CFG2 (RXLPM_HF_CFG2), + .RXLPM_HF_CFG3 (RXLPM_HF_CFG3), + .RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE), + .RXLPM_INCM_CFG (RXLPM_INCM_CFG), + .RXLPM_IPCM_CFG (RXLPM_IPCM_CFG), + .RXLPM_LF_CFG (RXLPM_LF_CFG), + .RXLPM_LF_CFG2 (RXLPM_LF_CFG2), + .RXLPM_OSINT_CFG (RXLPM_OSINT_CFG), + .RXOOB_CFG (RXOOB_CFG), + .RXOOB_CLK_CFG (RXOOB_CLK_CFG), + .RXOSCALRESET_TIME (RXOSCALRESET_TIME), + .RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT), + .RXOUT_DIV (RXOUT_DIV), + .RXPCSRESET_TIME (RXPCSRESET_TIME), + .RXPHDLY_CFG (RXPHDLY_CFG), + .RXPH_CFG (RXPH_CFG), + .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RXPI_CFG2 (RXPI_CFG2), + .RXPMARESET_TIME (RXPMARESET_TIME), + .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK), + .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT), + .RXSLIDE_MODE (RXSLIDE_MODE), + .RXSYNC_MULTILANE (RXSYNC_MULTILANE), + .RXSYNC_OVRD (RXSYNC_OVRD), + .RXSYNC_SKIP_DA (RXSYNC_SKIP_DA), + .RX_BIAS_CFG (RX_BIAS_CFG), + .RX_BUFFER_CFG (RX_BUFFER_CFG), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (RX_CLKMUX_EN), + .RX_CM_SEL (RX_CM_SEL), + .RX_CM_TRIM (RX_CM_TRIM), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (RX_DDI_SEL), + .RX_DEBUG_CFG (RX_DEBUG_CFG), + .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN), + .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH), + .RX_OS_CFG (RX_OS_CFG), + .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY), + .RX_XCLK_SEL (RX_XCLK_SEL), + .SAS_MAX_COM (SAS_MAX_COM), + .SAS_MIN_COM (SAS_MIN_COM), + .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN), + .SATA_BURST_VAL (SATA_BURST_VAL), + .SATA_EIDLE_VAL (SATA_EIDLE_VAL), + .SATA_MAX_BURST (SATA_MAX_BURST), + .SATA_MAX_INIT (SATA_MAX_INIT), + .SATA_MAX_WAKE (SATA_MAX_WAKE), + .SATA_MIN_BURST (SATA_MIN_BURST), + .SATA_MIN_INIT (SATA_MIN_INIT), + .SATA_MIN_WAKE (SATA_MIN_WAKE), + .SATA_PLL_CFG (SATA_PLL_CFG), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL), + .SIM_VERSION (SIM_VERSION), + .TERM_RCAL_CFG (TERM_RCAL_CFG), + .TERM_RCAL_OVRD (TERM_RCAL_OVRD), + .TRANS_TIME_RATE (TRANS_TIME_RATE), + .TST_RSV (TST_RSV), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE), + .TXDLY_CFG (TXDLY_CFG), + .TXDLY_LCFG (TXDLY_LCFG), + .TXDLY_TAP_CFG (TXDLY_TAP_CFG), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOOB_CFG (TXOOB_CFG), + .TXOUT_DIV (TXOUT_DIV), + .TXPCSRESET_TIME (TXPCSRESET_TIME), + .TXPHDLY_CFG (TXPHDLY_CFG), + .TXPH_CFG (TXPH_CFG), + .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXPI_CFG2 (TXPI_CFG2), + .TXPI_CFG3 (TXPI_CFG3), + .TXPI_CFG4 (TXPI_CFG4), + .TXPI_CFG5 (TXPI_CFG5), + .TXPI_GREY_SEL (TXPI_GREY_SEL), + .TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL), + .TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL), + .TXPI_PPM_CFG (TXPI_PPM_CFG), + .TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM), + .TXPMARESET_TIME (TXPMARESET_TIME), + .TXSYNC_MULTILANE (TXSYNC_MULTILANE), + .TXSYNC_OVRD (TXSYNC_OVRD), + .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (TX_CLKMUX_EN), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DEEMPH0 (TX_DEEMPH0), + .TX_DEEMPH1 (TX_DEEMPH1), + .TX_DRIVE_MODE (TX_DRIVE_MODE), + .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY), + .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY), + .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ), + .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), + .TX_PREDRIVER_MODE (TX_PREDRIVER_MODE), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), + .TX_RXDETECT_REF (TX_RXDETECT_REF), + .TX_XCLK_SEL (TX_XCLK_SEL), + .UCODEER_CLR (UCODEER_CLR), + .USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL)) + + B_GTPE2_CHANNEL_INST ( + .DMONITOROUT (delay_DMONITOROUT), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .EYESCANDATAERROR (delay_EYESCANDATAERROR), + .GTPTXN (delay_GTPTXN), + .GTPTXP (delay_GTPTXP), + .PCSRSVDOUT (delay_PCSRSVDOUT), + .PHYSTATUS (delay_PHYSTATUS), + .PMARSVDOUT0 (delay_PMARSVDOUT0), + .PMARSVDOUT1 (delay_PMARSVDOUT1), + .RXBUFSTATUS (delay_RXBUFSTATUS), + .RXBYTEISALIGNED (delay_RXBYTEISALIGNED), + .RXBYTEREALIGN (delay_RXBYTEREALIGN), + .RXCDRLOCK (delay_RXCDRLOCK), + .RXCHANBONDSEQ (delay_RXCHANBONDSEQ), + .RXCHANISALIGNED (delay_RXCHANISALIGNED), + .RXCHANREALIGN (delay_RXCHANREALIGN), + .RXCHARISCOMMA (delay_RXCHARISCOMMA), + .RXCHARISK (delay_RXCHARISK), + .RXCHBONDO (delay_RXCHBONDO), + .RXCLKCORCNT (delay_RXCLKCORCNT), + .RXCOMINITDET (delay_RXCOMINITDET), + .RXCOMMADET (delay_RXCOMMADET), + .RXCOMSASDET (delay_RXCOMSASDET), + .RXCOMWAKEDET (delay_RXCOMWAKEDET), + .RXDATA (delay_RXDATA), + .RXDATAVALID (delay_RXDATAVALID), + .RXDISPERR (delay_RXDISPERR), + .RXDLYSRESETDONE (delay_RXDLYSRESETDONE), + .RXELECIDLE (delay_RXELECIDLE), + .RXHEADER (delay_RXHEADER), + .RXHEADERVALID (delay_RXHEADERVALID), + .RXNOTINTABLE (delay_RXNOTINTABLE), + .RXOSINTDONE (delay_RXOSINTDONE), + .RXOSINTSTARTED (delay_RXOSINTSTARTED), + .RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE), + .RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED), + .RXOUTCLK (delay_RXOUTCLK), + .RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC), + .RXOUTCLKPCS (delay_RXOUTCLKPCS), + .RXPHALIGNDONE (delay_RXPHALIGNDONE), + .RXPHMONITOR (delay_RXPHMONITOR), + .RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR), + .RXPMARESETDONE (delay_RXPMARESETDONE), + .RXPRBSERR (delay_RXPRBSERR), + .RXRATEDONE (delay_RXRATEDONE), + .RXRESETDONE (delay_RXRESETDONE), + .RXSTARTOFSEQ (delay_RXSTARTOFSEQ), + .RXSTATUS (delay_RXSTATUS), + .RXSYNCDONE (delay_RXSYNCDONE), + .RXSYNCOUT (delay_RXSYNCOUT), + .RXVALID (delay_RXVALID), + .TXBUFSTATUS (delay_TXBUFSTATUS), + .TXCOMFINISH (delay_TXCOMFINISH), + .TXDLYSRESETDONE (delay_TXDLYSRESETDONE), + .TXGEARBOXREADY (delay_TXGEARBOXREADY), + .TXOUTCLK (delay_TXOUTCLK), + .TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC), + .TXOUTCLKPCS (delay_TXOUTCLKPCS), + .TXPHALIGNDONE (delay_TXPHALIGNDONE), + .TXPHINITDONE (delay_TXPHINITDONE), + .TXPMARESETDONE (delay_TXPMARESETDONE), + .TXRATEDONE (delay_TXRATEDONE), + .TXRESETDONE (delay_TXRESETDONE), + .TXSYNCDONE (delay_TXSYNCDONE), + .TXSYNCOUT (delay_TXSYNCOUT), + .CFGRESET (delay_CFGRESET), + .CLKRSVD0 (delay_CLKRSVD0), + .CLKRSVD1 (delay_CLKRSVD1), + .DMONFIFORESET (delay_DMONFIFORESET), + .DMONITORCLK (delay_DMONITORCLK), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .EYESCANMODE (delay_EYESCANMODE), + .EYESCANRESET (delay_EYESCANRESET), + .EYESCANTRIGGER (delay_EYESCANTRIGGER), + .GTPRXN (delay_GTPRXN), + .GTPRXP (delay_GTPRXP), + .GTRESETSEL (delay_GTRESETSEL), + .GTRSVD (delay_GTRSVD), + .GTRXRESET (delay_GTRXRESET), + .GTTXRESET (delay_GTTXRESET), + .LOOPBACK (delay_LOOPBACK), + .PCSRSVDIN (delay_PCSRSVDIN), + .PLL0CLK (delay_PLL0CLK), + .PLL0REFCLK (delay_PLL0REFCLK), + .PLL1CLK (delay_PLL1CLK), + .PLL1REFCLK (delay_PLL1REFCLK), + .PMARSVDIN0 (delay_PMARSVDIN0), + .PMARSVDIN1 (delay_PMARSVDIN1), + .PMARSVDIN2 (delay_PMARSVDIN2), + .PMARSVDIN3 (delay_PMARSVDIN3), + .PMARSVDIN4 (delay_PMARSVDIN4), + .RESETOVRD (delay_RESETOVRD), + .RX8B10BEN (delay_RX8B10BEN), + .RXADAPTSELTEST (delay_RXADAPTSELTEST), + .RXBUFRESET (delay_RXBUFRESET), + .RXCDRFREQRESET (delay_RXCDRFREQRESET), + .RXCDRHOLD (delay_RXCDRHOLD), + .RXCDROVRDEN (delay_RXCDROVRDEN), + .RXCDRRESET (delay_RXCDRRESET), + .RXCDRRESETRSV (delay_RXCDRRESETRSV), + .RXCHBONDEN (delay_RXCHBONDEN), + .RXCHBONDI (delay_RXCHBONDI), + .RXCHBONDLEVEL (delay_RXCHBONDLEVEL), + .RXCHBONDMASTER (delay_RXCHBONDMASTER), + .RXCHBONDSLAVE (delay_RXCHBONDSLAVE), + .RXCOMMADETEN (delay_RXCOMMADETEN), + .RXDDIEN (delay_RXDDIEN), + .RXDFEXYDEN (delay_RXDFEXYDEN), + .RXDLYBYPASS (delay_RXDLYBYPASS), + .RXDLYEN (delay_RXDLYEN), + .RXDLYOVRDEN (delay_RXDLYOVRDEN), + .RXDLYSRESET (delay_RXDLYSRESET), + .RXELECIDLEMODE (delay_RXELECIDLEMODE), + .RXGEARBOXSLIP (delay_RXGEARBOXSLIP), + .RXLPMHFHOLD (delay_RXLPMHFHOLD), + .RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN), + .RXLPMLFHOLD (delay_RXLPMLFHOLD), + .RXLPMLFOVRDEN (delay_RXLPMLFOVRDEN), + .RXLPMOSINTNTRLEN (delay_RXLPMOSINTNTRLEN), + .RXLPMRESET (delay_RXLPMRESET), + .RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN), + .RXOOBRESET (delay_RXOOBRESET), + .RXOSCALRESET (delay_RXOSCALRESET), + .RXOSHOLD (delay_RXOSHOLD), + .RXOSINTCFG (delay_RXOSINTCFG), + .RXOSINTEN (delay_RXOSINTEN), + .RXOSINTHOLD (delay_RXOSINTHOLD), + .RXOSINTID0 (delay_RXOSINTID0), + .RXOSINTNTRLEN (delay_RXOSINTNTRLEN), + .RXOSINTOVRDEN (delay_RXOSINTOVRDEN), + .RXOSINTPD (delay_RXOSINTPD), + .RXOSINTSTROBE (delay_RXOSINTSTROBE), + .RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN), + .RXOSOVRDEN (delay_RXOSOVRDEN), + .RXOUTCLKSEL (delay_RXOUTCLKSEL), + .RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN), + .RXPCSRESET (delay_RXPCSRESET), + .RXPD (delay_RXPD), + .RXPHALIGN (delay_RXPHALIGN), + .RXPHALIGNEN (delay_RXPHALIGNEN), + .RXPHDLYPD (delay_RXPHDLYPD), + .RXPHDLYRESET (delay_RXPHDLYRESET), + .RXPHOVRDEN (delay_RXPHOVRDEN), + .RXPMARESET (delay_RXPMARESET), + .RXPOLARITY (delay_RXPOLARITY), + .RXPRBSCNTRESET (delay_RXPRBSCNTRESET), + .RXPRBSSEL (delay_RXPRBSSEL), + .RXRATE (delay_RXRATE), + .RXRATEMODE (delay_RXRATEMODE), + .RXSLIDE (delay_RXSLIDE), + .RXSYNCALLIN (delay_RXSYNCALLIN), + .RXSYNCIN (delay_RXSYNCIN), + .RXSYNCMODE (delay_RXSYNCMODE), + .RXSYSCLKSEL (delay_RXSYSCLKSEL), + .RXUSERRDY (delay_RXUSERRDY), + .RXUSRCLK (delay_RXUSRCLK), + .RXUSRCLK2 (delay_RXUSRCLK2), + .SETERRSTATUS (delay_SETERRSTATUS), + .SIGVALIDCLK (delay_SIGVALIDCLK), + .TSTIN (delay_TSTIN), + .TX8B10BBYPASS (delay_TX8B10BBYPASS), + .TX8B10BEN (delay_TX8B10BEN), + .TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL), + .TXCHARDISPMODE (delay_TXCHARDISPMODE), + .TXCHARDISPVAL (delay_TXCHARDISPVAL), + .TXCHARISK (delay_TXCHARISK), + .TXCOMINIT (delay_TXCOMINIT), + .TXCOMSAS (delay_TXCOMSAS), + .TXCOMWAKE (delay_TXCOMWAKE), + .TXDATA (delay_TXDATA), + .TXDEEMPH (delay_TXDEEMPH), + .TXDETECTRX (delay_TXDETECTRX), + .TXDIFFCTRL (delay_TXDIFFCTRL), + .TXDIFFPD (delay_TXDIFFPD), + .TXDLYBYPASS (delay_TXDLYBYPASS), + .TXDLYEN (delay_TXDLYEN), + .TXDLYHOLD (delay_TXDLYHOLD), + .TXDLYOVRDEN (delay_TXDLYOVRDEN), + .TXDLYSRESET (delay_TXDLYSRESET), + .TXDLYUPDOWN (delay_TXDLYUPDOWN), + .TXELECIDLE (delay_TXELECIDLE), + .TXHEADER (delay_TXHEADER), + .TXINHIBIT (delay_TXINHIBIT), + .TXMAINCURSOR (delay_TXMAINCURSOR), + .TXMARGIN (delay_TXMARGIN), + .TXOUTCLKSEL (delay_TXOUTCLKSEL), + .TXPCSRESET (delay_TXPCSRESET), + .TXPD (delay_TXPD), + .TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE), + .TXPHALIGN (delay_TXPHALIGN), + .TXPHALIGNEN (delay_TXPHALIGNEN), + .TXPHDLYPD (delay_TXPHDLYPD), + .TXPHDLYRESET (delay_TXPHDLYRESET), + .TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK), + .TXPHINIT (delay_TXPHINIT), + .TXPHOVRDEN (delay_TXPHOVRDEN), + .TXPIPPMEN (delay_TXPIPPMEN), + .TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN), + .TXPIPPMPD (delay_TXPIPPMPD), + .TXPIPPMSEL (delay_TXPIPPMSEL), + .TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE), + .TXPISOPD (delay_TXPISOPD), + .TXPMARESET (delay_TXPMARESET), + .TXPOLARITY (delay_TXPOLARITY), + .TXPOSTCURSOR (delay_TXPOSTCURSOR), + .TXPOSTCURSORINV (delay_TXPOSTCURSORINV), + .TXPRBSFORCEERR (delay_TXPRBSFORCEERR), + .TXPRBSSEL (delay_TXPRBSSEL), + .TXPRECURSOR (delay_TXPRECURSOR), + .TXPRECURSORINV (delay_TXPRECURSORINV), + .TXRATE (delay_TXRATE), + .TXRATEMODE (delay_TXRATEMODE), + .TXSEQUENCE (delay_TXSEQUENCE), + .TXSTARTSEQ (delay_TXSTARTSEQ), + .TXSWING (delay_TXSWING), + .TXSYNCALLIN (delay_TXSYNCALLIN), + .TXSYNCIN (delay_TXSYNCIN), + .TXSYNCMODE (delay_TXSYNCMODE), + .TXSYSCLKSEL (delay_TXSYSCLKSEL), + .TXUSERRDY (delay_TXUSERRDY), + .TXUSRCLK (delay_TXUSRCLK), + .TXUSRCLK2 (delay_TXUSRCLK2), + .GSR (GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge CLKRSVD0, 0:0:0, notifier); + $period (negedge CLKRSVD0, 0:0:0, notifier); + $period (posedge CLKRSVD1, 0:0:0, notifier); + $period (negedge CLKRSVD1, 0:0:0, notifier); + $period (posedge DMONITORCLK, 0:0:0, notifier); + $period (negedge DMONITORCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge PLL0CLK, 0:0:0, notifier); + $period (posedge PLL1CLK, 0:0:0, notifier); + $period (posedge RXOUTCLK, 0:0:0, notifier); + $period (posedge RXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge RXOUTCLKPCS, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge SIGVALIDCLK, 0:0:0, notifier); + $period (negedge SIGVALIDCLK, 0:0:0, notifier); + $period (posedge TXOUTCLK, 0:0:0, notifier); + $period (posedge TXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge TXOUTCLKPCS, 0:0:0, notifier); + $period (posedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (negedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN); + $setuphold (negedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); + $setuphold (negedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); +`endif + + ( DMONITORCLK *> DMONITOROUT) = (0, 0); + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( RXUSRCLK2 *> PHYSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0); + ( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0); + ( RXUSRCLK2 *> RXCHARISK) = (0, 0); + ( RXUSRCLK2 *> RXCHBONDO) = (0, 0); + ( RXUSRCLK *> RXCHBONDO) = (0, 0); + ( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0); + ( RXUSRCLK2 *> RXCOMINITDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMMADET) = (0, 0); + ( RXUSRCLK2 *> RXCOMSASDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0); + ( RXUSRCLK2 *> RXDATA) = (0, 0); + ( RXUSRCLK2 *> RXDATAVALID) = (0, 0); + ( RXUSRCLK2 *> RXDISPERR) = (0, 0); + ( RXUSRCLK2 *> RXHEADER) = (0, 0); + ( RXUSRCLK2 *> RXHEADERVALID) = (0, 0); + ( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0); + ( RXUSRCLK2 *> RXPRBSERR) = (0, 0); + ( RXUSRCLK2 *> RXRATEDONE) = (0, 0); + ( RXUSRCLK2 *> RXRESETDONE) = (0, 0); + ( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0); + ( RXUSRCLK2 *> RXSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXVALID) = (0, 0); + ( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0); + ( TXUSRCLK2 *> TXCOMFINISH) = (0, 0); + ( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0); + ( TXUSRCLK2 *> TXRATEDONE) = (0, 0); + ( TXUSRCLK2 *> TXRESETDONE) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule +`endcelldefine diff --git a/verilog/src/unisims/GTPE2_COMMON.v b/verilog/src/unisims/GTPE2_COMMON.v new file mode 100644 index 0000000..fb0f88a --- /dev/null +++ b/verilog/src/unisims/GTPE2_COMMON.v @@ -0,0 +1,703 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTPE2_COMMON.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 11/8/12 - 686589 - YML default changes +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine +module GTPE2_COMMON ( + DMONITOROUT, + DRPDO, + DRPRDY, + PLL0FBCLKLOST, + PLL0LOCK, + PLL0OUTCLK, + PLL0OUTREFCLK, + PLL0REFCLKLOST, + PLL1FBCLKLOST, + PLL1LOCK, + PLL1OUTCLK, + PLL1OUTREFCLK, + PLL1REFCLKLOST, + PMARSVDOUT, + REFCLKOUTMONITOR0, + REFCLKOUTMONITOR1, + + BGBYPASSB, + BGMONITORENB, + BGPDB, + BGRCALOVRD, + BGRCALOVRDENB, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + GTEASTREFCLK0, + GTEASTREFCLK1, + GTGREFCLK0, + GTGREFCLK1, + GTREFCLK0, + GTREFCLK1, + GTWESTREFCLK0, + GTWESTREFCLK1, + PLL0LOCKDETCLK, + PLL0LOCKEN, + PLL0PD, + PLL0REFCLKSEL, + PLL0RESET, + PLL1LOCKDETCLK, + PLL1LOCKEN, + PLL1PD, + PLL1REFCLKSEL, + PLL1RESET, + PLLRSVD1, + PLLRSVD2, + PMARSVD, + RCALENB +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [63:0] BIAS_CFG = 64'h0000000000000000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0; + parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] PLL0_CFG = 27'h01F03DC; + parameter [0:0] PLL0_DMON_CFG = 1'b0; + parameter integer PLL0_FBDIV = 4; + parameter integer PLL0_FBDIV_45 = 5; + parameter [23:0] PLL0_INIT_CFG = 24'h00001E; + parameter [8:0] PLL0_LOCK_CFG = 9'h1E8; + parameter integer PLL0_REFCLK_DIV = 1; + parameter [26:0] PLL1_CFG = 27'h01F03DC; + parameter [0:0] PLL1_DMON_CFG = 1'b0; + parameter integer PLL1_FBDIV = 4; + parameter integer PLL1_FBDIV_45 = 5; + parameter [23:0] PLL1_INIT_CFG = 24'h00001E; + parameter [8:0] PLL1_LOCK_CFG = 9'h1E8; + parameter integer PLL1_REFCLK_DIV = 1; + parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001; + parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.0"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output DRPRDY; + output PLL0FBCLKLOST; + output PLL0LOCK; + output PLL0OUTCLK; + output PLL0OUTREFCLK; + output PLL0REFCLKLOST; + output PLL1FBCLKLOST; + output PLL1LOCK; + output PLL1OUTCLK; + output PLL1OUTREFCLK; + output PLL1REFCLKLOST; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] DMONITOROUT; + + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + input DRPCLK; + input DRPEN; + input DRPWE; + input GTEASTREFCLK0; + input GTEASTREFCLK1; + input GTGREFCLK0; + input GTGREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTWESTREFCLK0; + input GTWESTREFCLK1; + input PLL0LOCKDETCLK; + input PLL0LOCKEN; + input PLL0PD; + input PLL0RESET; + input PLL1LOCKDETCLK; + input PLL1LOCKEN; + input PLL1PD; + input PLL1RESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] PLLRSVD1; + input [2:0] PLL0REFCLKSEL; + input [2:0] PLL1REFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] PLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; + + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] PLL0_DMON_CFG_BINARY; + reg [0:0] PLL0_FBDIV_45_BINARY; + reg [0:0] PLL1_DMON_CFG_BINARY; + reg [0:0] PLL1_FBDIV_45_BINARY; + reg [2:0] SIM_PLL0REFCLK_SEL_BINARY; + reg [2:0] SIM_PLL1REFCLK_SEL_BINARY; + reg [4:0] PLL0_REFCLK_DIV_BINARY; + reg [4:0] PLL1_REFCLK_DIV_BINARY; + reg [5:0] PLL0_FBDIV_BINARY; + reg [5:0] PLL1_FBDIV_BINARY; + reg [7:0] PLL_CLKOUT_CFG_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (PLL0_FBDIV) + 4 : PLL0_FBDIV_BINARY = 6'b000010; + 1 : PLL0_FBDIV_BINARY = 6'b010000; + 2 : PLL0_FBDIV_BINARY = 6'b000000; + 3 : PLL0_FBDIV_BINARY = 6'b000001; + 5 : PLL0_FBDIV_BINARY = 6'b000011; + 6 : PLL0_FBDIV_BINARY = 6'b000101; + 8 : PLL0_FBDIV_BINARY = 6'b000110; + 10 : PLL0_FBDIV_BINARY = 6'b000111; + 12 : PLL0_FBDIV_BINARY = 6'b001101; + 16 : PLL0_FBDIV_BINARY = 6'b001110; + 20 : PLL0_FBDIV_BINARY = 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL0_FBDIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL0_FBDIV, 4); + #1 $finish; + end + endcase + + case (PLL0_FBDIV_45) + 5 : PLL0_FBDIV_45_BINARY = 1'b1; + 4 : PLL0_FBDIV_45_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PLL0_FBDIV_45 on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 4 to 5.", PLL0_FBDIV_45, 5); + #1 $finish; + end + endcase + + case (PLL0_REFCLK_DIV) + 1 : PLL0_REFCLK_DIV_BINARY = 5'b10000; + 2 : PLL0_REFCLK_DIV_BINARY = 5'b00000; + 3 : PLL0_REFCLK_DIV_BINARY = 5'b00001; + 4 : PLL0_REFCLK_DIV_BINARY = 5'b00010; + 5 : PLL0_REFCLK_DIV_BINARY = 5'b00011; + 6 : PLL0_REFCLK_DIV_BINARY = 5'b00101; + 8 : PLL0_REFCLK_DIV_BINARY = 5'b00110; + 10 : PLL0_REFCLK_DIV_BINARY = 5'b00111; + 12 : PLL0_REFCLK_DIV_BINARY = 5'b01101; + 16 : PLL0_REFCLK_DIV_BINARY = 5'b01110; + 20 : PLL0_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL0_REFCLK_DIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL0_REFCLK_DIV, 1); + #1 $finish; + end + endcase + + case (PLL1_FBDIV) + 4 : PLL1_FBDIV_BINARY = 6'b000010; + 1 : PLL1_FBDIV_BINARY = 6'b010000; + 2 : PLL1_FBDIV_BINARY = 6'b000000; + 3 : PLL1_FBDIV_BINARY = 6'b000001; + 5 : PLL1_FBDIV_BINARY = 6'b000011; + 6 : PLL1_FBDIV_BINARY = 6'b000101; + 8 : PLL1_FBDIV_BINARY = 6'b000110; + 10 : PLL1_FBDIV_BINARY = 6'b000111; + 12 : PLL1_FBDIV_BINARY = 6'b001101; + 16 : PLL1_FBDIV_BINARY = 6'b001110; + 20 : PLL1_FBDIV_BINARY = 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL1_FBDIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL1_FBDIV, 4); + #1 $finish; + end + endcase + + case (PLL1_FBDIV_45) + 5 : PLL1_FBDIV_45_BINARY = 1'b1; + 4 : PLL1_FBDIV_45_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PLL1_FBDIV_45 on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 4 to 5.", PLL1_FBDIV_45, 5); + #1 $finish; + end + endcase + + case (PLL1_REFCLK_DIV) + 1 : PLL1_REFCLK_DIV_BINARY = 5'b10000; + 2 : PLL1_REFCLK_DIV_BINARY = 5'b00000; + 3 : PLL1_REFCLK_DIV_BINARY = 5'b00001; + 4 : PLL1_REFCLK_DIV_BINARY = 5'b00010; + 5 : PLL1_REFCLK_DIV_BINARY = 5'b00011; + 6 : PLL1_REFCLK_DIV_BINARY = 5'b00101; + 8 : PLL1_REFCLK_DIV_BINARY = 5'b00110; + 10 : PLL1_REFCLK_DIV_BINARY = 5'b00111; + 12 : PLL1_REFCLK_DIV_BINARY = 5'b01101; + 16 : PLL1_REFCLK_DIV_BINARY = 5'b01110; + 20 : PLL1_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL1_REFCLK_DIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL1_REFCLK_DIV, 1); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_COMMON instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION); + #1 $finish; + end + endcase + + if ((PLL0_DMON_CFG >= 1'b0) && (PLL0_DMON_CFG <= 1'b1)) + PLL0_DMON_CFG_BINARY = PLL0_DMON_CFG; + else begin + $display("Attribute Syntax Error : The Attribute PLL0_DMON_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PLL0_DMON_CFG); + #1 $finish; + end + + if ((PLL1_DMON_CFG >= 1'b0) && (PLL1_DMON_CFG <= 1'b1)) + PLL1_DMON_CFG_BINARY = PLL1_DMON_CFG; + else begin + $display("Attribute Syntax Error : The Attribute PLL1_DMON_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PLL1_DMON_CFG); + #1 $finish; + end + + if ((PLL_CLKOUT_CFG >= 8'b00000000) && (PLL_CLKOUT_CFG <= 8'b11111111)) + PLL_CLKOUT_CFG_BINARY = PLL_CLKOUT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute PLL_CLKOUT_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", PLL_CLKOUT_CFG); + #1 $finish; + end + + if ((SIM_PLL0REFCLK_SEL >= 3'b0) && (SIM_PLL0REFCLK_SEL <= 3'b111)) + SIM_PLL0REFCLK_SEL_BINARY = SIM_PLL0REFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_PLL0REFCLK_SEL on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_PLL0REFCLK_SEL); + #1 $finish; + end + + if ((SIM_PLL1REFCLK_SEL >= 3'b0) && (SIM_PLL1REFCLK_SEL <= 3'b111)) + SIM_PLL1REFCLK_SEL_BINARY = SIM_PLL1REFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_PLL1REFCLK_SEL on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_PLL1REFCLK_SEL); + #1 $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [15:0] delay_PMARSVDOUT; + wire [7:0] delay_DMONITOROUT; + wire delay_DRPRDY; + wire delay_PLL0FBCLKLOST; + wire delay_PLL0LOCK; + wire delay_PLL0OUTCLK; + wire delay_PLL0OUTREFCLK; + wire delay_PLL0REFCLKLOST; + wire delay_PLL1FBCLKLOST; + wire delay_PLL1LOCK; + wire delay_PLL1OUTCLK; + wire delay_PLL1OUTREFCLK; + wire delay_PLL1REFCLKLOST; + wire delay_REFCLKOUTMONITOR0; + wire delay_REFCLKOUTMONITOR1; + + wire [15:0] delay_DRPDI; + wire [15:0] delay_PLLRSVD1; + wire [2:0] delay_PLL0REFCLKSEL; + wire [2:0] delay_PLL1REFCLKSEL; + wire [4:0] delay_BGRCALOVRD; + wire [4:0] delay_PLLRSVD2; + wire [7:0] delay_DRPADDR; + wire [7:0] delay_PMARSVD; + wire delay_BGBYPASSB; + wire delay_BGMONITORENB; + wire delay_BGPDB; + wire delay_BGRCALOVRDENB; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_GTEASTREFCLK0; + wire delay_GTEASTREFCLK1; + wire delay_GTGREFCLK0; + wire delay_GTGREFCLK1; + wire delay_GTREFCLK0; + wire delay_GTREFCLK1; + wire delay_GTWESTREFCLK0; + wire delay_GTWESTREFCLK1; + wire delay_PLL0LOCKDETCLK; + wire delay_PLL0LOCKEN; + wire delay_PLL0PD; + wire delay_PLL0RESET; + wire delay_PLL1LOCKDETCLK; + wire delay_PLL1LOCKEN; + wire delay_PLL1PD; + wire delay_PLL1RESET; + wire delay_RCALENB; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_GTGREFCLK0_INVERTED_REG = IS_GTGREFCLK0_INVERTED; + reg [0:0] IS_GTGREFCLK1_INVERTED_REG = IS_GTGREFCLK1_INVERTED; + reg [0:0] IS_PLL0LOCKDETCLK_INVERTED_REG = IS_PLL0LOCKDETCLK_INVERTED; + reg [0:0] IS_PLL1LOCKDETCLK_INVERTED_REG = IS_PLL1LOCKDETCLK_INVERTED; + + assign #(OUTCLK_DELAY) PLL0OUTCLK = delay_PLL0OUTCLK; + assign #(OUTCLK_DELAY) PLL1OUTCLK = delay_PLL1OUTCLK; + assign #(OUTCLK_DELAY) REFCLKOUTMONITOR0 = delay_REFCLKOUTMONITOR0; + assign #(OUTCLK_DELAY) REFCLKOUTMONITOR1 = delay_REFCLKOUTMONITOR1; + + assign #(out_delay) DMONITOROUT = delay_DMONITOROUT; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPRDY = delay_DRPRDY; + assign #(out_delay) PLL0FBCLKLOST = delay_PLL0FBCLKLOST; + assign #(out_delay) PLL0LOCK = delay_PLL0LOCK; + assign #(out_delay) PLL0OUTREFCLK = delay_PLL0OUTREFCLK; + assign #(out_delay) PLL0REFCLKLOST = delay_PLL0REFCLKLOST; + assign #(out_delay) PLL1FBCLKLOST = delay_PLL1FBCLKLOST; + assign #(out_delay) PLL1LOCK = delay_PLL1LOCK; + assign #(out_delay) PLL1OUTREFCLK = delay_PLL1OUTREFCLK; + assign #(out_delay) PLL1REFCLKLOST = delay_PLL1REFCLKLOST; + assign #(out_delay) PMARSVDOUT = delay_PMARSVDOUT; + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_GTEASTREFCLK0 = GTEASTREFCLK0 ^ IS_GTGREFCLK0_INVERTED_REG; + assign #(INCLK_DELAY) delay_GTEASTREFCLK1 = GTEASTREFCLK1 ^ IS_GTGREFCLK1_INVERTED_REG; + assign #(INCLK_DELAY) delay_GTGREFCLK0 = GTGREFCLK0; + assign #(INCLK_DELAY) delay_GTGREFCLK1 = GTGREFCLK1; + assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0; + assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1; + assign #(INCLK_DELAY) delay_GTWESTREFCLK0 = GTWESTREFCLK0; + assign #(INCLK_DELAY) delay_GTWESTREFCLK1 = GTWESTREFCLK1; + assign #(INCLK_DELAY) delay_PLL0LOCKDETCLK = PLL0LOCKDETCLK ^ IS_PLL0LOCKDETCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_PLL1LOCKDETCLK = PLL1LOCKDETCLK^ IS_PLL1LOCKDETCLK_INVERTED_REG; + + assign #(in_delay) delay_BGBYPASSB = BGBYPASSB; + assign #(in_delay) delay_BGMONITORENB = BGMONITORENB; + assign #(in_delay) delay_BGPDB = BGPDB; + assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD; + assign #(in_delay) delay_BGRCALOVRDENB = BGRCALOVRDENB; + assign #(in_delay) delay_DRPADDR = DRPADDR; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPEN = DRPEN; + assign #(in_delay) delay_DRPWE = DRPWE; + assign #(in_delay) delay_PLL0LOCKEN = PLL0LOCKEN; + assign #(in_delay) delay_PLL0PD = PLL0PD; + assign #(in_delay) delay_PLL0REFCLKSEL = PLL0REFCLKSEL; + assign #(in_delay) delay_PLL0RESET = PLL0RESET; + assign #(in_delay) delay_PLL1LOCKEN = PLL1LOCKEN; + assign #(in_delay) delay_PLL1PD = PLL1PD; + assign #(in_delay) delay_PLL1REFCLKSEL = PLL1REFCLKSEL; + assign #(in_delay) delay_PLL1RESET = PLL1RESET; + assign #(in_delay) delay_PLLRSVD1 = PLLRSVD1; + assign #(in_delay) delay_PLLRSVD2 = PLLRSVD2; + assign #(in_delay) delay_PMARSVD = PMARSVD; + assign #(in_delay) delay_RCALENB = RCALENB; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_BGBYPASSB = BGBYPASSB; + assign delay_BGMONITORENB = BGMONITORENB; + assign delay_BGPDB = BGPDB; + assign delay_BGRCALOVRD = BGRCALOVRD; + assign delay_BGRCALOVRDENB = BGRCALOVRDENB; + assign delay_GTEASTREFCLK0 = GTEASTREFCLK0; + assign delay_GTEASTREFCLK1 = GTEASTREFCLK1; + assign delay_GTGREFCLK0 = GTGREFCLK0; + assign delay_GTGREFCLK1 = GTGREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTWESTREFCLK0 = GTWESTREFCLK0; + assign delay_GTWESTREFCLK1 = GTWESTREFCLK1; + assign delay_PLL0LOCKDETCLK = PLL0LOCKDETCLK; + assign delay_PLL0LOCKEN = PLL0LOCKEN; + assign delay_PLL0PD = PLL0PD; + assign delay_PLL0REFCLKSEL = PLL0REFCLKSEL; + assign delay_PLL0RESET = PLL0RESET; + assign delay_PLL1LOCKDETCLK = PLL1LOCKDETCLK; + assign delay_PLL1LOCKEN = PLL1LOCKEN; + assign delay_PLL1PD = PLL1PD; + assign delay_PLL1REFCLKSEL = PLL1REFCLKSEL; + assign delay_PLL1RESET = PLL1RESET; + assign delay_PLLRSVD1 = PLLRSVD1; + assign delay_PLLRSVD2 = PLLRSVD2; + assign delay_PMARSVD = PMARSVD; + assign delay_RCALENB = RCALENB; + + wire drpclk_en_p; + wire drpclk_en_n; + + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; +`endif + + B_GTPE2_COMMON #( + .BIAS_CFG (BIAS_CFG), + .COMMON_CFG (COMMON_CFG), + .PLL0_CFG (PLL0_CFG), + .PLL0_DMON_CFG (PLL0_DMON_CFG), + .PLL0_FBDIV (PLL0_FBDIV), + .PLL0_FBDIV_45 (PLL0_FBDIV_45), + .PLL0_INIT_CFG (PLL0_INIT_CFG), + .PLL0_LOCK_CFG (PLL0_LOCK_CFG), + .PLL0_REFCLK_DIV (PLL0_REFCLK_DIV), + .PLL1_CFG (PLL1_CFG), + .PLL1_DMON_CFG (PLL1_DMON_CFG), + .PLL1_FBDIV (PLL1_FBDIV), + .PLL1_FBDIV_45 (PLL1_FBDIV_45), + .PLL1_INIT_CFG (PLL1_INIT_CFG), + .PLL1_LOCK_CFG (PLL1_LOCK_CFG), + .PLL1_REFCLK_DIV (PLL1_REFCLK_DIV), + .PLL_CLKOUT_CFG (PLL_CLKOUT_CFG), + .RSVD_ATTR0 (RSVD_ATTR0), + .RSVD_ATTR1 (RSVD_ATTR1), + .SIM_PLL0REFCLK_SEL (SIM_PLL0REFCLK_SEL), + .SIM_PLL1REFCLK_SEL (SIM_PLL1REFCLK_SEL), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION)) + + B_GTPE2_COMMON_INST ( + .DMONITOROUT (delay_DMONITOROUT), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .PLL0FBCLKLOST (delay_PLL0FBCLKLOST), + .PLL0LOCK (delay_PLL0LOCK), + .PLL0OUTCLK (delay_PLL0OUTCLK), + .PLL0OUTREFCLK (delay_PLL0OUTREFCLK), + .PLL0REFCLKLOST (delay_PLL0REFCLKLOST), + .PLL1FBCLKLOST (delay_PLL1FBCLKLOST), + .PLL1LOCK (delay_PLL1LOCK), + .PLL1OUTCLK (delay_PLL1OUTCLK), + .PLL1OUTREFCLK (delay_PLL1OUTREFCLK), + .PLL1REFCLKLOST (delay_PLL1REFCLKLOST), + .PMARSVDOUT (delay_PMARSVDOUT), + .REFCLKOUTMONITOR0 (delay_REFCLKOUTMONITOR0), + .REFCLKOUTMONITOR1 (delay_REFCLKOUTMONITOR1), + .BGBYPASSB (delay_BGBYPASSB), + .BGMONITORENB (delay_BGMONITORENB), + .BGPDB (delay_BGPDB), + .BGRCALOVRD (delay_BGRCALOVRD), + .BGRCALOVRDENB (delay_BGRCALOVRDENB), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .GTEASTREFCLK0 (delay_GTEASTREFCLK0), + .GTEASTREFCLK1 (delay_GTEASTREFCLK1), + .GTGREFCLK0 (delay_GTGREFCLK0), + .GTGREFCLK1 (delay_GTGREFCLK1), + .GTREFCLK0 (delay_GTREFCLK0), + .GTREFCLK1 (delay_GTREFCLK1), + .GTWESTREFCLK0 (delay_GTWESTREFCLK0), + .GTWESTREFCLK1 (delay_GTWESTREFCLK1), + .PLL0LOCKDETCLK (delay_PLL0LOCKDETCLK), + .PLL0LOCKEN (delay_PLL0LOCKEN), + .PLL0PD (delay_PLL0PD), + .PLL0REFCLKSEL (delay_PLL0REFCLKSEL), + .PLL0RESET (delay_PLL0RESET), + .PLL1LOCKDETCLK (delay_PLL1LOCKDETCLK), + .PLL1LOCKEN (delay_PLL1LOCKEN), + .PLL1PD (delay_PLL1PD), + .PLL1REFCLKSEL (delay_PLL1REFCLKSEL), + .PLL1RESET (delay_PLL1RESET), + .PLLRSVD1 (delay_PLLRSVD1), + .PLLRSVD2 (delay_PLLRSVD2), + .PMARSVD (delay_PMARSVD), + .RCALENB (delay_RCALENB), + .GSR (GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge GTEASTREFCLK0, 0:0:0, notifier); + $period (posedge GTEASTREFCLK1, 0:0:0, notifier); + $period (posedge GTGREFCLK0, 0:0:0, notifier); + $period (negedge GTGREFCLK0, 0:0:0, notifier); + $period (posedge GTGREFCLK1, 0:0:0, notifier); + $period (negedge GTGREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLK0, 0:0:0, notifier); + $period (posedge GTREFCLK1, 0:0:0, notifier); + $period (posedge GTWESTREFCLK0, 0:0:0, notifier); + $period (posedge GTWESTREFCLK1, 0:0:0, notifier); + $period (posedge PLL0LOCKDETCLK, 0:0:0, notifier); + $period (negedge PLL0LOCKDETCLK, 0:0:0, notifier); + $period (posedge PLL0OUTCLK, 0:0:0, notifier); + $period (posedge PLL1LOCKDETCLK, 0:0:0, notifier); + $period (negedge PLL1LOCKDETCLK, 0:0:0, notifier); + $period (posedge PLL1OUTCLK, 0:0:0, notifier); + $period (posedge REFCLKOUTMONITOR0, 0:0:0, notifier); + $period (posedge REFCLKOUTMONITOR1, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); +`endif + + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( GTGREFCLK0 *> REFCLKOUTMONITOR0) = (0, 0); + ( GTGREFCLK0 *> REFCLKOUTMONITOR1) = (0, 0); + ( GTGREFCLK1 *> REFCLKOUTMONITOR0) = (0, 0); + ( GTGREFCLK1 *> REFCLKOUTMONITOR1) = (0, 0); + ( GTREFCLK0 *> REFCLKOUTMONITOR0) = (0, 0); + ( GTREFCLK0 *> REFCLKOUTMONITOR1) = (0, 0); + ( GTREFCLK1 *> REFCLKOUTMONITOR0) = (0, 0); + ( GTREFCLK1 *> REFCLKOUTMONITOR1) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule +`endcelldefine diff --git a/verilog/src/unisims/GTXE2_CHANNEL.v b/verilog/src/unisims/GTXE2_CHANNEL.v new file mode 100644 index 0000000..117bbd9 --- /dev/null +++ b/verilog/src/unisims/GTXE2_CHANNEL.v @@ -0,0 +1,3725 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2012 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.3 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /__/ /\ Filename : GTXE2_CHANNEL.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 11/10/09 - CR - Initial version +// 02/28/11 - CR595054 - Add missing setuphold check - RXCHBONDI-RXUSRCLK2 +// 03/24/11 - CR596791 - CLKRSVD<1> minperiod & pathdelay added +// 04/01/11 - CR596791 - update CLKRSVD[1] bit to bus timing +// 05/12/11 - CR608414 - Attribute name YML update +// 05/19/11 - CR611019 - Added missing IOPATH RXUSRCLK_RXCHBONDO +// 06/02/11 - CR612815 - Add missing setuphold RXUSRCLK_RXCHBONDI +// 07/08/11 - CR616301 - Remove assign on RXUSRCLK for simprim +// 09/16/11 - CR624064 - YML update +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +///////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine + +module GTXE2_CHANNEL ( + CPLLFBCLKLOST, + CPLLLOCK, + CPLLREFCLKLOST, + DMONITOROUT, + DRPDO, + DRPRDY, + EYESCANDATAERROR, + GTREFCLKMONITOR, + GTXTXN, + GTXTXP, + PCSRSVDOUT, + PHYSTATUS, + RXBUFSTATUS, + RXBYTEISALIGNED, + RXBYTEREALIGN, + RXCDRLOCK, + RXCHANBONDSEQ, + RXCHANISALIGNED, + RXCHANREALIGN, + RXCHARISCOMMA, + RXCHARISK, + RXCHBONDO, + RXCLKCORCNT, + RXCOMINITDET, + RXCOMMADET, + RXCOMSASDET, + RXCOMWAKEDET, + RXDATA, + RXDATAVALID, + RXDISPERR, + RXDLYSRESETDONE, + RXELECIDLE, + RXHEADER, + RXHEADERVALID, + RXMONITOROUT, + RXNOTINTABLE, + RXOUTCLK, + RXOUTCLKFABRIC, + RXOUTCLKPCS, + RXPHALIGNDONE, + RXPHMONITOR, + RXPHSLIPMONITOR, + RXPRBSERR, + RXQPISENN, + RXQPISENP, + RXRATEDONE, + RXRESETDONE, + RXSTARTOFSEQ, + RXSTATUS, + RXVALID, + TSTOUT, + TXBUFSTATUS, + TXCOMFINISH, + TXDLYSRESETDONE, + TXGEARBOXREADY, + TXOUTCLK, + TXOUTCLKFABRIC, + TXOUTCLKPCS, + TXPHALIGNDONE, + TXPHINITDONE, + TXQPISENN, + TXQPISENP, + TXRATEDONE, + TXRESETDONE, + + CFGRESET, + CLKRSVD, + CPLLLOCKDETCLK, + CPLLLOCKEN, + CPLLPD, + CPLLREFCLKSEL, + CPLLRESET, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + EYESCANMODE, + EYESCANRESET, + EYESCANTRIGGER, + GTGREFCLK, + GTNORTHREFCLK0, + GTNORTHREFCLK1, + GTREFCLK0, + GTREFCLK1, + GTRESETSEL, + GTRSVD, + GTRXRESET, + GTSOUTHREFCLK0, + GTSOUTHREFCLK1, + GTTXRESET, + GTXRXN, + GTXRXP, + LOOPBACK, + PCSRSVDIN, + PCSRSVDIN2, + PMARSVDIN, + PMARSVDIN2, + QPLLCLK, + QPLLREFCLK, + RESETOVRD, + RX8B10BEN, + RXBUFRESET, + RXCDRFREQRESET, + RXCDRHOLD, + RXCDROVRDEN, + RXCDRRESET, + RXCDRRESETRSV, + RXCHBONDEN, + RXCHBONDI, + RXCHBONDLEVEL, + RXCHBONDMASTER, + RXCHBONDSLAVE, + RXCOMMADETEN, + RXDDIEN, + RXDFEAGCHOLD, + RXDFEAGCOVRDEN, + RXDFECM1EN, + RXDFELFHOLD, + RXDFELFOVRDEN, + RXDFELPMRESET, + RXDFETAP2HOLD, + RXDFETAP2OVRDEN, + RXDFETAP3HOLD, + RXDFETAP3OVRDEN, + RXDFETAP4HOLD, + RXDFETAP4OVRDEN, + RXDFETAP5HOLD, + RXDFETAP5OVRDEN, + RXDFEUTHOLD, + RXDFEUTOVRDEN, + RXDFEVPHOLD, + RXDFEVPOVRDEN, + RXDFEVSEN, + RXDFEXYDEN, + RXDFEXYDHOLD, + RXDFEXYDOVRDEN, + RXDLYBYPASS, + RXDLYEN, + RXDLYOVRDEN, + RXDLYSRESET, + RXELECIDLEMODE, + RXGEARBOXSLIP, + RXLPMEN, + RXLPMHFHOLD, + RXLPMHFOVRDEN, + RXLPMLFHOLD, + RXLPMLFKLOVRDEN, + RXMCOMMAALIGNEN, + RXMONITORSEL, + RXOOBRESET, + RXOSHOLD, + RXOSOVRDEN, + RXOUTCLKSEL, + RXPCOMMAALIGNEN, + RXPCSRESET, + RXPD, + RXPHALIGN, + RXPHALIGNEN, + RXPHDLYPD, + RXPHDLYRESET, + RXPHOVRDEN, + RXPMARESET, + RXPOLARITY, + RXPRBSCNTRESET, + RXPRBSSEL, + RXQPIEN, + RXRATE, + RXSLIDE, + RXSYSCLKSEL, + RXUSERRDY, + RXUSRCLK, + RXUSRCLK2, + SETERRSTATUS, + TSTIN, + TX8B10BBYPASS, + TX8B10BEN, + TXBUFDIFFCTRL, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCOMINIT, + TXCOMSAS, + TXCOMWAKE, + TXDATA, + TXDEEMPH, + TXDETECTRX, + TXDIFFCTRL, + TXDIFFPD, + TXDLYBYPASS, + TXDLYEN, + TXDLYHOLD, + TXDLYOVRDEN, + TXDLYSRESET, + TXDLYUPDOWN, + TXELECIDLE, + TXHEADER, + TXINHIBIT, + TXMAINCURSOR, + TXMARGIN, + TXOUTCLKSEL, + TXPCSRESET, + TXPD, + TXPDELECIDLEMODE, + TXPHALIGN, + TXPHALIGNEN, + TXPHDLYPD, + TXPHDLYRESET, + TXPHDLYTSTCLK, + TXPHINIT, + TXPHOVRDEN, + TXPISOPD, + TXPMARESET, + TXPOLARITY, + TXPOSTCURSOR, + TXPOSTCURSORINV, + TXPRBSFORCEERR, + TXPRBSSEL, + TXPRECURSOR, + TXPRECURSORINV, + TXQPIBIASEN, + TXQPISTRONGPDOWN, + TXQPIWEAKPUP, + TXRATE, + TXSEQUENCE, + TXSTARTSEQ, + TXSWING, + TXSYSCLKSEL, + TXUSERRDY, + TXUSRCLK, + TXUSRCLK2 +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [23:0] CPLL_CFG = 24'hB007D8; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'h00000000; + parameter [15:0] PMA_RSV2 = 16'h2050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [31:0] PMA_RSV4 = 32'h00000000; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b010101; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000; + parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'h000000; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [11:0] RX_BIAS_CFG = 12'b000000000000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [2:0] RX_CM_TRIM = 3'b100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [11:0] RX_DEBUG_CFG = 12'b000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F; + parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000; + parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000; + parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0904; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000; + parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "4.0"; + parameter [4:0] TERM_RCAL_CFG = 5'b10000; + parameter [0:0] TERM_RCAL_OVRD = 1'b0; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH0 = 5'b00000; + parameter [4:0] TX_DEEMPH1 = 5'b00000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTREFCLKMONITOR; + output GTXTXN; + output GTXTXP; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] DMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + output [9:0] TSTOUT; + + input CFGRESET; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTXRXN; + input GTXRXP; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDFEXYDHOLD; + input RXDFEXYDOVRDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXSLIDE; + input RXUSERRDY; + input RXUSRCLK2; + input RXUSRCLK; + input SETERRSTATUS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXSTARTSEQ; + input TXSWING; + input TXUSERRDY; + input TXUSRCLK2; + input TXUSRCLK; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] CLKRSVD; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; + + reg SIM_RECEIVER_DETECT_PASS_BINARY; + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] ALIGN_COMMA_DOUBLE_BINARY; + reg [0:0] ALIGN_MCOMMA_DET_BINARY; + reg [0:0] ALIGN_PCOMMA_DET_BINARY; + reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY; + reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY; + reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY; + reg [0:0] CLK_CORRECT_USE_BINARY; + reg [0:0] CLK_COR_KEEP_IDLE_BINARY; + reg [0:0] CLK_COR_PRECEDENCE_BINARY; + reg [0:0] CLK_COR_SEQ_2_USE_BINARY; + reg [0:0] CPLL_FBDIV_45_BINARY; + reg [0:0] DEC_MCOMMA_DETECT_BINARY; + reg [0:0] DEC_PCOMMA_DETECT_BINARY; + reg [0:0] DEC_VALID_COMMA_ONLY_BINARY; + reg [0:0] ES_ERRDET_EN_BINARY; + reg [0:0] ES_EYE_SCAN_EN_BINARY; + reg [0:0] FTS_LANE_DESKEW_EN_BINARY; + reg [0:0] PCS_PCIE_EN_BINARY; + reg [0:0] RXBUF_ADDR_MODE_BINARY; + reg [0:0] RXBUF_EN_BINARY; + reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY; + reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY; + reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY; + reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] RXBUF_THRESH_OVRD_BINARY; + reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY; + reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY; + reg [0:0] RXGEARBOX_EN_BINARY; + reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY; + reg [0:0] RX_CLKMUX_PD_BINARY; + reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY; + reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY; + reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY; + reg [0:0] RX_INT_DATAWIDTH_BINARY; + reg [0:0] RX_XCLK_SEL_BINARY; + reg [0:0] SHOW_REALIGN_COMMA_BINARY; + reg [0:0] TERM_RCAL_OVRD_BINARY; + reg [0:0] TXBUF_EN_BINARY; + reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY; + reg [0:0] TXGEARBOX_EN_BINARY; + reg [0:0] TX_CLKMUX_PD_BINARY; + reg [0:0] TX_INT_DATAWIDTH_BINARY; + reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY; + reg [0:0] TX_MAINCURSOR_SEL_BINARY; + reg [0:0] TX_PREDRIVER_MODE_BINARY; + reg [0:0] TX_QPI_STATUS_EN_BINARY; + reg [0:0] TX_XCLK_SEL_BINARY; + reg [0:0] UCODEER_CLR_BINARY; + reg [10:0] RX_DFE_H4_CFG_BINARY; + reg [10:0] RX_DFE_H5_CFG_BINARY; + reg [11:0] RX_BIAS_CFG_BINARY; + reg [11:0] RX_DEBUG_CFG_BINARY; + reg [11:0] RX_DFE_H2_CFG_BINARY; + reg [11:0] RX_DFE_H3_CFG_BINARY; + reg [12:0] RX_DFE_KL_CFG_BINARY; + reg [12:0] RX_DFE_XYD_CFG_BINARY; + reg [12:0] RX_OS_CFG_BINARY; + reg [13:0] RXLPM_HF_CFG_BINARY; + reg [13:0] RXLPM_LF_CFG_BINARY; + reg [16:0] RX_DFE_UT_CFG_BINARY; + reg [16:0] RX_DFE_VP_CFG_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_BINARY; + reg [1:0] CLK_COR_SEQ_LEN_BINARY; + reg [1:0] OUTREFCLK_SEL_INV_BINARY; + reg [1:0] PMA_RSV3_BINARY; + reg [1:0] RXSLIDE_MODE_BINARY; + reg [1:0] RX_CM_SEL_BINARY; + reg [1:0] SATA_CPLL_CFG_BINARY; + reg [2:0] ALIGN_COMMA_WORD_BINARY; + reg [2:0] GEARBOX_MODE_BINARY; + reg [2:0] RXOUT_DIV_BINARY; + reg [2:0] RX_CM_TRIM_BINARY; + reg [2:0] RX_DATA_WIDTH_BINARY; + reg [2:0] SATA_BURST_VAL_BINARY; + reg [2:0] SATA_EIDLE_VAL_BINARY; + reg [2:0] SIM_CPLLREFCLK_SEL_BINARY; + reg [2:0] TXOUT_DIV_BINARY; + reg [2:0] TX_DATA_WIDTH_BINARY; + reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY; + reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY; + reg [2:0] TX_RXDETECT_REF_BINARY; + reg [3:0] CHAN_BOND_MAX_SKEW_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY; + reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY; + reg [3:0] FTS_LANE_DESKEW_CFG_BINARY; + reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY; + reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY; + reg [3:0] RXSLIDE_AUTO_WAIT_BINARY; + reg [3:0] SATA_BURST_SEQ_LEN_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_BINARY; + reg [4:0] CPLL_REFCLK_DIV_BINARY; + reg [4:0] ES_PRESCALE_BINARY; + reg [4:0] RXBUFRESET_TIME_BINARY; + reg [4:0] RXCDRFREQRESET_TIME_BINARY; + reg [4:0] RXCDRPHRESET_TIME_BINARY; + reg [4:0] RXISCANRESET_TIME_BINARY; + reg [4:0] RXPCSRESET_TIME_BINARY; + reg [4:0] RXPH_MONITOR_SEL_BINARY; + reg [4:0] RXPMARESET_TIME_BINARY; + reg [4:0] RX_CLK25_DIV_BINARY; + reg [4:0] RX_SIG_VALID_DLY_BINARY; + reg [4:0] TERM_RCAL_CFG_BINARY; + reg [4:0] TXPCSRESET_TIME_BINARY; + reg [4:0] TXPH_MONITOR_SEL_BINARY; + reg [4:0] TXPMARESET_TIME_BINARY; + reg [4:0] TX_CLK25_DIV_BINARY; + reg [4:0] TX_DEEMPH0_BINARY; + reg [4:0] TX_DEEMPH1_BINARY; + reg [4:0] TX_DRIVE_MODE_BINARY; + reg [5:0] CLK_COR_MAX_LAT_BINARY; + reg [5:0] CLK_COR_MIN_LAT_BINARY; + reg [5:0] ES_CONTROL_BINARY; + reg [5:0] RXBUF_THRESH_OVFLW_BINARY; + reg [5:0] RXBUF_THRESH_UNDFLW_BINARY; + reg [5:0] RXCDR_LOCK_CFG_BINARY; + reg [5:0] RX_BUFFER_CFG_BINARY; + reg [5:0] RX_DDI_SEL_BINARY; + reg [5:0] SAS_MIN_COM_BINARY; + reg [5:0] SATA_MAX_BURST_BINARY; + reg [5:0] SATA_MAX_INIT_BINARY; + reg [5:0] SATA_MAX_WAKE_BINARY; + reg [5:0] SATA_MIN_BURST_BINARY; + reg [5:0] SATA_MIN_INIT_BINARY; + reg [5:0] SATA_MIN_WAKE_BINARY; + reg [6:0] CPLL_FBDIV_BINARY; + reg [6:0] RXDFELPMRESET_TIME_BINARY; + reg [6:0] RXOOB_CFG_BINARY; + reg [6:0] SAS_MAX_COM_BINARY; + reg [6:0] TX_MARGIN_FULL_0_BINARY; + reg [6:0] TX_MARGIN_FULL_1_BINARY; + reg [6:0] TX_MARGIN_FULL_2_BINARY; + reg [6:0] TX_MARGIN_FULL_3_BINARY; + reg [6:0] TX_MARGIN_FULL_4_BINARY; + reg [6:0] TX_MARGIN_LOW_0_BINARY; + reg [6:0] TX_MARGIN_LOW_1_BINARY; + reg [6:0] TX_MARGIN_LOW_2_BINARY; + reg [6:0] TX_MARGIN_LOW_3_BINARY; + reg [6:0] TX_MARGIN_LOW_4_BINARY; + reg [8:0] ES_VERT_OFFSET_BINARY; + reg [9:0] ALIGN_COMMA_ENABLE_BINARY; + reg [9:0] ALIGN_MCOMMA_VALUE_BINARY; + reg [9:0] ALIGN_PCOMMA_VALUE_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_BINARY; + reg [9:0] ES_PMA_CFG_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (ALIGN_COMMA_DOUBLE) + "FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0; + "TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE); + #1 $finish; + end + endcase + + case (ALIGN_COMMA_WORD) + 1 : ALIGN_COMMA_WORD_BINARY = 3'b001; + 2 : ALIGN_COMMA_WORD_BINARY = 3'b010; + 4 : ALIGN_COMMA_WORD_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", ALIGN_COMMA_WORD, 1); + #1 $finish; + end + endcase + + case (ALIGN_MCOMMA_DET) + "TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET); + #1 $finish; + end + endcase + + case (ALIGN_PCOMMA_DET) + "TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1; + "FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET); + #1 $finish; + end + endcase + + case (CBCC_DATA_SOURCE_SEL) + "DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1; + "ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL); + #1 $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN) + "FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE) + "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN) + 1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (CLK_CORRECT_USE) + "TRUE" : CLK_CORRECT_USE_BINARY = 1'b1; + "FALSE" : CLK_CORRECT_USE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE); + #1 $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE) + "FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE); + #1 $finish; + end + endcase + + case (CLK_COR_PRECEDENCE) + "TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1; + "FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE) + "FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE); + #1 $finish; + end + endcase + + case (CLK_COR_SEQ_LEN) + 1 : CLK_COR_SEQ_LEN_BINARY = 2'b00; + 2 : CLK_COR_SEQ_LEN_BINARY = 2'b01; + 3 : CLK_COR_SEQ_LEN_BINARY = 2'b10; + 4 : CLK_COR_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1); + #1 $finish; + end + endcase + + case (CPLL_FBDIV) + 4 : CPLL_FBDIV_BINARY = 7'b0000010; + 1 : CPLL_FBDIV_BINARY = 7'b0010000; + 2 : CPLL_FBDIV_BINARY = 7'b0000000; + 3 : CPLL_FBDIV_BINARY = 7'b0000001; + 5 : CPLL_FBDIV_BINARY = 7'b0000011; + 6 : CPLL_FBDIV_BINARY = 7'b0000101; + 8 : CPLL_FBDIV_BINARY = 7'b0000110; + 10 : CPLL_FBDIV_BINARY = 7'b0000111; + 12 : CPLL_FBDIV_BINARY = 7'b0001101; + 16 : CPLL_FBDIV_BINARY = 7'b0001110; + 20 : CPLL_FBDIV_BINARY = 7'b0001111; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_FBDIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_FBDIV, 4); + #1 $finish; + end + endcase + + case (CPLL_FBDIV_45) + 5 : CPLL_FBDIV_45_BINARY = 1'b1; + 4 : CPLL_FBDIV_45_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_FBDIV_45 on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 4 to 5.", CPLL_FBDIV_45, 5); + #1 $finish; + end + endcase + + case (CPLL_REFCLK_DIV) + 1 : CPLL_REFCLK_DIV_BINARY = 5'b10000; + 2 : CPLL_REFCLK_DIV_BINARY = 5'b00000; + 3 : CPLL_REFCLK_DIV_BINARY = 5'b00001; + 4 : CPLL_REFCLK_DIV_BINARY = 5'b00010; + 5 : CPLL_REFCLK_DIV_BINARY = 5'b00011; + 6 : CPLL_REFCLK_DIV_BINARY = 5'b00101; + 8 : CPLL_REFCLK_DIV_BINARY = 5'b00110; + 10 : CPLL_REFCLK_DIV_BINARY = 5'b00111; + 12 : CPLL_REFCLK_DIV_BINARY = 5'b01101; + 16 : CPLL_REFCLK_DIV_BINARY = 5'b01110; + 20 : CPLL_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute CPLL_REFCLK_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_REFCLK_DIV, 1); + #1 $finish; + end + endcase + + case (DEC_MCOMMA_DETECT) + "TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_PCOMMA_DETECT) + "TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1; + "FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT); + #1 $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY) + "TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1; + "FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY); + #1 $finish; + end + endcase + + case (ES_ERRDET_EN) + "FALSE" : ES_ERRDET_EN_BINARY = 1'b0; + "TRUE" : ES_ERRDET_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN); + #1 $finish; + end + endcase + + case (ES_EYE_SCAN_EN) + "FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0; + "TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN); + #1 $finish; + end + endcase + + case (FTS_LANE_DESKEW_EN) + "FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0; + "TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN); + #1 $finish; + end + endcase + + case (PCS_PCIE_EN) + "FALSE" : PCS_PCIE_EN_BINARY = 1'b0; + "TRUE" : PCS_PCIE_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN); + #1 $finish; + end + endcase + + case (RXBUF_ADDR_MODE) + "FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0; + "FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE); + #1 $finish; + end + endcase + + case (RXBUF_EN) + "TRUE" : RXBUF_EN_BINARY = 1'b1; + "FALSE" : RXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_CB_CHANGE) + "TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_COMMAALIGN) + "FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_EIDLE) + "FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0; + "TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE); + #1 $finish; + end + endcase + + case (RXBUF_RESET_ON_RATE_CHANGE) + "TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + "FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (RXBUF_THRESH_OVRD) + "FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0; + "TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD); + #1 $finish; + end + endcase + + case (RXGEARBOX_EN) + "FALSE" : RXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : RXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN); + #1 $finish; + end + endcase + + case (RXOUT_DIV) + 2 : RXOUT_DIV_BINARY = 3'b001; + 1 : RXOUT_DIV_BINARY = 3'b000; + 4 : RXOUT_DIV_BINARY = 3'b010; + 8 : RXOUT_DIV_BINARY = 3'b011; + 16 : RXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute RXOUT_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (RXSLIDE_MODE) + "OFF" : RXSLIDE_MODE_BINARY = 2'b00; + "AUTO" : RXSLIDE_MODE_BINARY = 2'b01; + "PCS" : RXSLIDE_MODE_BINARY = 2'b10; + "PMA" : RXSLIDE_MODE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE); + #1 $finish; + end + endcase + + case (RX_CLK25_DIV) + 7 : RX_CLK25_DIV_BINARY = 5'b00110; + 1 : RX_CLK25_DIV_BINARY = 5'b00000; + 2 : RX_CLK25_DIV_BINARY = 5'b00001; + 3 : RX_CLK25_DIV_BINARY = 5'b00010; + 4 : RX_CLK25_DIV_BINARY = 5'b00011; + 5 : RX_CLK25_DIV_BINARY = 5'b00100; + 6 : RX_CLK25_DIV_BINARY = 5'b00101; + 8 : RX_CLK25_DIV_BINARY = 5'b00111; + 9 : RX_CLK25_DIV_BINARY = 5'b01000; + 10 : RX_CLK25_DIV_BINARY = 5'b01001; + 11 : RX_CLK25_DIV_BINARY = 5'b01010; + 12 : RX_CLK25_DIV_BINARY = 5'b01011; + 13 : RX_CLK25_DIV_BINARY = 5'b01100; + 14 : RX_CLK25_DIV_BINARY = 5'b01101; + 15 : RX_CLK25_DIV_BINARY = 5'b01110; + 16 : RX_CLK25_DIV_BINARY = 5'b01111; + 17 : RX_CLK25_DIV_BINARY = 5'b10000; + 18 : RX_CLK25_DIV_BINARY = 5'b10001; + 19 : RX_CLK25_DIV_BINARY = 5'b10010; + 20 : RX_CLK25_DIV_BINARY = 5'b10011; + 21 : RX_CLK25_DIV_BINARY = 5'b10100; + 22 : RX_CLK25_DIV_BINARY = 5'b10101; + 23 : RX_CLK25_DIV_BINARY = 5'b10110; + 24 : RX_CLK25_DIV_BINARY = 5'b10111; + 25 : RX_CLK25_DIV_BINARY = 5'b11000; + 26 : RX_CLK25_DIV_BINARY = 5'b11001; + 27 : RX_CLK25_DIV_BINARY = 5'b11010; + 28 : RX_CLK25_DIV_BINARY = 5'b11011; + 29 : RX_CLK25_DIV_BINARY = 5'b11100; + 30 : RX_CLK25_DIV_BINARY = 5'b11101; + 31 : RX_CLK25_DIV_BINARY = 5'b11110; + 32 : RX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (RX_DATA_WIDTH) + 20 : RX_DATA_WIDTH_BINARY = 3'b011; + 16 : RX_DATA_WIDTH_BINARY = 3'b010; + 32 : RX_DATA_WIDTH_BINARY = 3'b100; + 40 : RX_DATA_WIDTH_BINARY = 3'b101; + 64 : RX_DATA_WIDTH_BINARY = 3'b110; + 80 : RX_DATA_WIDTH_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", RX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (RX_DEFER_RESET_BUF_EN) + "TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1; + "FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN); + #1 $finish; + end + endcase + + case (RX_DISPERR_SEQ_MATCH) + "TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1; + "FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH); + #1 $finish; + end + endcase + + case (RX_SIG_VALID_DLY) + 10 : RX_SIG_VALID_DLY_BINARY = 5'b01001; + 1 : RX_SIG_VALID_DLY_BINARY = 5'b00000; + 2 : RX_SIG_VALID_DLY_BINARY = 5'b00001; + 3 : RX_SIG_VALID_DLY_BINARY = 5'b00010; + 4 : RX_SIG_VALID_DLY_BINARY = 5'b00011; + 5 : RX_SIG_VALID_DLY_BINARY = 5'b00100; + 6 : RX_SIG_VALID_DLY_BINARY = 5'b00101; + 7 : RX_SIG_VALID_DLY_BINARY = 5'b00110; + 8 : RX_SIG_VALID_DLY_BINARY = 5'b00111; + 9 : RX_SIG_VALID_DLY_BINARY = 5'b01000; + 11 : RX_SIG_VALID_DLY_BINARY = 5'b01010; + 12 : RX_SIG_VALID_DLY_BINARY = 5'b01011; + 13 : RX_SIG_VALID_DLY_BINARY = 5'b01100; + 14 : RX_SIG_VALID_DLY_BINARY = 5'b01101; + 15 : RX_SIG_VALID_DLY_BINARY = 5'b01110; + 16 : RX_SIG_VALID_DLY_BINARY = 5'b01111; + 17 : RX_SIG_VALID_DLY_BINARY = 5'b10000; + 18 : RX_SIG_VALID_DLY_BINARY = 5'b10001; + 19 : RX_SIG_VALID_DLY_BINARY = 5'b10010; + 20 : RX_SIG_VALID_DLY_BINARY = 5'b10011; + 21 : RX_SIG_VALID_DLY_BINARY = 5'b10100; + 22 : RX_SIG_VALID_DLY_BINARY = 5'b10101; + 23 : RX_SIG_VALID_DLY_BINARY = 5'b10110; + 24 : RX_SIG_VALID_DLY_BINARY = 5'b10111; + 25 : RX_SIG_VALID_DLY_BINARY = 5'b11000; + 26 : RX_SIG_VALID_DLY_BINARY = 5'b11001; + 27 : RX_SIG_VALID_DLY_BINARY = 5'b11010; + 28 : RX_SIG_VALID_DLY_BINARY = 5'b11011; + 29 : RX_SIG_VALID_DLY_BINARY = 5'b11100; + 30 : RX_SIG_VALID_DLY_BINARY = 5'b11101; + 31 : RX_SIG_VALID_DLY_BINARY = 5'b11110; + 32 : RX_SIG_VALID_DLY_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10); + #1 $finish; + end + endcase + + case (RX_XCLK_SEL) + "RXREC" : RX_XCLK_SEL_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL); + #1 $finish; + end + endcase + + case (SATA_CPLL_CFG) + "VCO_3000MHZ" : SATA_CPLL_CFG_BINARY = 2'b00; + "VCO_750MHZ" : SATA_CPLL_CFG_BINARY = 2'b10; + "VCO_1500MHZ" : SATA_CPLL_CFG_BINARY = 2'b01; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_CPLL_CFG on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_CPLL_CFG); + #1 $finish; + end + endcase + + case (SHOW_REALIGN_COMMA) + "TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1; + "FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA); + #1 $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS) + "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + "FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + + case (SIM_TX_EIDLE_DRIVE_LEVEL) + "X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + "Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "4.0" : SIM_VERSION_BINARY = 0; + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + "3.0" : SIM_VERSION_BINARY = 0; + "4.1" : SIM_VERSION_BINARY = 0; + "5.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 4.0, 1.0, 1.1, 2.0, 3.0, 4.1, or 5.0.", SIM_VERSION); + #1 $finish; + end + endcase + + case (TXBUF_EN) + "TRUE" : TXBUF_EN_BINARY = 1'b1; + "FALSE" : TXBUF_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN); + #1 $finish; + end + endcase + + case (TXBUF_RESET_ON_RATE_CHANGE) + "FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; + "TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE); + #1 $finish; + end + endcase + + case (TXGEARBOX_EN) + "FALSE" : TXGEARBOX_EN_BINARY = 1'b0; + "TRUE" : TXGEARBOX_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN); + #1 $finish; + end + endcase + + case (TXOUT_DIV) + 2 : TXOUT_DIV_BINARY = 3'b001; + 1 : TXOUT_DIV_BINARY = 3'b000; + 4 : TXOUT_DIV_BINARY = 3'b010; + 8 : TXOUT_DIV_BINARY = 3'b011; + 16 : TXOUT_DIV_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUT_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2); + #1 $finish; + end + endcase + + case (TX_CLK25_DIV) + 7 : TX_CLK25_DIV_BINARY = 5'b00110; + 1 : TX_CLK25_DIV_BINARY = 5'b00000; + 2 : TX_CLK25_DIV_BINARY = 5'b00001; + 3 : TX_CLK25_DIV_BINARY = 5'b00010; + 4 : TX_CLK25_DIV_BINARY = 5'b00011; + 5 : TX_CLK25_DIV_BINARY = 5'b00100; + 6 : TX_CLK25_DIV_BINARY = 5'b00101; + 8 : TX_CLK25_DIV_BINARY = 5'b00111; + 9 : TX_CLK25_DIV_BINARY = 5'b01000; + 10 : TX_CLK25_DIV_BINARY = 5'b01001; + 11 : TX_CLK25_DIV_BINARY = 5'b01010; + 12 : TX_CLK25_DIV_BINARY = 5'b01011; + 13 : TX_CLK25_DIV_BINARY = 5'b01100; + 14 : TX_CLK25_DIV_BINARY = 5'b01101; + 15 : TX_CLK25_DIV_BINARY = 5'b01110; + 16 : TX_CLK25_DIV_BINARY = 5'b01111; + 17 : TX_CLK25_DIV_BINARY = 5'b10000; + 18 : TX_CLK25_DIV_BINARY = 5'b10001; + 19 : TX_CLK25_DIV_BINARY = 5'b10010; + 20 : TX_CLK25_DIV_BINARY = 5'b10011; + 21 : TX_CLK25_DIV_BINARY = 5'b10100; + 22 : TX_CLK25_DIV_BINARY = 5'b10101; + 23 : TX_CLK25_DIV_BINARY = 5'b10110; + 24 : TX_CLK25_DIV_BINARY = 5'b10111; + 25 : TX_CLK25_DIV_BINARY = 5'b11000; + 26 : TX_CLK25_DIV_BINARY = 5'b11001; + 27 : TX_CLK25_DIV_BINARY = 5'b11010; + 28 : TX_CLK25_DIV_BINARY = 5'b11011; + 29 : TX_CLK25_DIV_BINARY = 5'b11100; + 30 : TX_CLK25_DIV_BINARY = 5'b11101; + 31 : TX_CLK25_DIV_BINARY = 5'b11110; + 32 : TX_CLK25_DIV_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7); + #1 $finish; + end + endcase + + case (TX_DATA_WIDTH) + 20 : TX_DATA_WIDTH_BINARY = 3'b011; + 16 : TX_DATA_WIDTH_BINARY = 3'b010; + 32 : TX_DATA_WIDTH_BINARY = 3'b100; + 40 : TX_DATA_WIDTH_BINARY = 3'b101; + 64 : TX_DATA_WIDTH_BINARY = 3'b110; + 80 : TX_DATA_WIDTH_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", TX_DATA_WIDTH, 20); + #1 $finish; + end + endcase + + case (TX_DRIVE_MODE) + "DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000; + "PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001; + "PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE); + #1 $finish; + end + endcase + + case (TX_LOOPBACK_DRIVE_HIZ) + "FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0; + "TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ); + #1 $finish; + end + endcase + + case (TX_XCLK_SEL) + "TXUSR" : TX_XCLK_SEL_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL); + #1 $finish; + end + endcase + + if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111)) + ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE); + #1 $finish; + end + + if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111)) + ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE); + #1 $finish; + end + + if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111)) + ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE); + #1 $finish; + end + + if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14)) + CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111)) + CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4); + #1 $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111)) + CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE); + #1 $finish; + end + + if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60)) + CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT); + #1 $finish; + end + + if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60)) + CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT); + #1 $finish; + end + + if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31)) + CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111)) + CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111)) + CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111)) + CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111)) + CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111)) + CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111)) + CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111)) + CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111)) + CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111)) + CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4); + #1 $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111)) + CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE); + #1 $finish; + end + + if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111)) + ES_CONTROL_BINARY = ES_CONTROL; + else begin + $display("Attribute Syntax Error : The Attribute ES_CONTROL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL); + #1 $finish; + end + + if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111)) + ES_PMA_CFG_BINARY = ES_PMA_CFG; + else begin + $display("Attribute Syntax Error : The Attribute ES_PMA_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG); + #1 $finish; + end + + if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111)) + ES_PRESCALE_BINARY = ES_PRESCALE; + else begin + $display("Attribute Syntax Error : The Attribute ES_PRESCALE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE); + #1 $finish; + end + + if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111)) + ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET; + else begin + $display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET); + #1 $finish; + end + + if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111)) + FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE); + #1 $finish; + end + + if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111)) + FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG; + else begin + $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG); + #1 $finish; + end + + if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111)) + GEARBOX_MODE_BINARY = GEARBOX_MODE; + else begin + $display("Attribute Syntax Error : The Attribute GEARBOX_MODE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE); + #1 $finish; + end + + if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11)) + OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV; + else begin + $display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV); + #1 $finish; + end + + if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11)) + PMA_RSV3_BINARY = PMA_RSV3; + else begin + $display("Attribute Syntax Error : The Attribute PMA_RSV3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3); + #1 $finish; + end + + if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111)) + RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME); + #1 $finish; + end + + if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111)) + RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT); + #1 $finish; + end + + if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111)) + RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT); + #1 $finish; + end + + if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63)) + RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW); + #1 $finish; + end + + if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63)) + RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW; + else begin + $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW); + #1 $finish; + end + + if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111)) + RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME); + #1 $finish; + end + + if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111)) + RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME); + #1 $finish; + end + + if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1)) + RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1)) + RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111)) + RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG); + #1 $finish; + end + + if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1)) + RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE); + #1 $finish; + end + + if ((RXDFELPMRESET_TIME >= 7'b0000000) && (RXDFELPMRESET_TIME <= 7'b1111111)) + RXDFELPMRESET_TIME_BINARY = RXDFELPMRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXDFELPMRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXDFELPMRESET_TIME); + #1 $finish; + end + + if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111)) + RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME); + #1 $finish; + end + + if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111)) + RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG); + #1 $finish; + end + + if ((RXLPM_LF_CFG >= 14'b00000000000000) && (RXLPM_LF_CFG <= 14'b11111111111111)) + RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_LF_CFG); + #1 $finish; + end + + if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111)) + RXOOB_CFG_BINARY = RXOOB_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXOOB_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG); + #1 $finish; + end + + if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111)) + RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME); + #1 $finish; + end + + if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111)) + RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL); + #1 $finish; + end + + if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111)) + RXPMARESET_TIME_BINARY = RXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME); + #1 $finish; + end + + if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1)) + RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK); + #1 $finish; + end + + if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15)) + RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT); + #1 $finish; + end + + if ((RX_BIAS_CFG >= 12'b000000000000) && (RX_BIAS_CFG <= 12'b111111111111)) + RX_BIAS_CFG_BINARY = RX_BIAS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_BIAS_CFG); + #1 $finish; + end + + if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111)) + RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG); + #1 $finish; + end + + if ((RX_CLKMUX_PD >= 1'b0) && (RX_CLKMUX_PD <= 1'b1)) + RX_CLKMUX_PD_BINARY = RX_CLKMUX_PD; + else begin + $display("Attribute Syntax Error : The Attribute RX_CLKMUX_PD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_PD); + #1 $finish; + end + + if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11)) + RX_CM_SEL_BINARY = RX_CM_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL); + #1 $finish; + end + + if ((RX_CM_TRIM >= 3'b000) && (RX_CM_TRIM <= 3'b111)) + RX_CM_TRIM_BINARY = RX_CM_TRIM; + else begin + $display("Attribute Syntax Error : The Attribute RX_CM_TRIM on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_CM_TRIM); + #1 $finish; + end + + if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111)) + RX_DDI_SEL_BINARY = RX_DDI_SEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_DDI_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL); + #1 $finish; + end + + if ((RX_DEBUG_CFG >= 12'b000000000000) && (RX_DEBUG_CFG <= 12'b111111111111)) + RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DEBUG_CFG); + #1 $finish; + end + + if ((RX_DFE_H2_CFG >= 12'b000000000000) && (RX_DFE_H2_CFG <= 12'b111111111111)) + RX_DFE_H2_CFG_BINARY = RX_DFE_H2_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H2_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H2_CFG); + #1 $finish; + end + + if ((RX_DFE_H3_CFG >= 12'b000000000000) && (RX_DFE_H3_CFG <= 12'b111111111111)) + RX_DFE_H3_CFG_BINARY = RX_DFE_H3_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H3_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H3_CFG); + #1 $finish; + end + + if ((RX_DFE_H4_CFG >= 11'b00000000000) && (RX_DFE_H4_CFG <= 11'b11111111111)) + RX_DFE_H4_CFG_BINARY = RX_DFE_H4_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H4_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H4_CFG); + #1 $finish; + end + + if ((RX_DFE_H5_CFG >= 11'b00000000000) && (RX_DFE_H5_CFG <= 11'b11111111111)) + RX_DFE_H5_CFG_BINARY = RX_DFE_H5_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_H5_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H5_CFG); + #1 $finish; + end + + if ((RX_DFE_KL_CFG >= 13'b0000000000000) && (RX_DFE_KL_CFG <= 13'b1111111111111)) + RX_DFE_KL_CFG_BINARY = RX_DFE_KL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_KL_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_DFE_KL_CFG); + #1 $finish; + end + + if ((RX_DFE_LPM_HOLD_DURING_EIDLE >= 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE <= 1'b1)) + RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY = RX_DFE_LPM_HOLD_DURING_EIDLE; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_LPM_HOLD_DURING_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_LPM_HOLD_DURING_EIDLE); + #1 $finish; + end + + if ((RX_DFE_UT_CFG >= 17'b00000000000000000) && (RX_DFE_UT_CFG <= 17'b11111111111111111)) + RX_DFE_UT_CFG_BINARY = RX_DFE_UT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_UT_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_UT_CFG); + #1 $finish; + end + + if ((RX_DFE_VP_CFG >= 17'b00000000000000000) && (RX_DFE_VP_CFG <= 17'b11111111111111111)) + RX_DFE_VP_CFG_BINARY = RX_DFE_VP_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_VP_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_VP_CFG); + #1 $finish; + end + + if ((RX_DFE_XYD_CFG >= 13'b0000000000000) && (RX_DFE_XYD_CFG <= 13'b1111111111111)) + RX_DFE_XYD_CFG_BINARY = RX_DFE_XYD_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_DFE_XYD_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_DFE_XYD_CFG); + #1 $finish; + end + + if ((RX_INT_DATAWIDTH >= 0) && (RX_INT_DATAWIDTH <= 1)) + RX_INT_DATAWIDTH_BINARY = RX_INT_DATAWIDTH; + else begin + $display("Attribute Syntax Error : The Attribute RX_INT_DATAWIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", RX_INT_DATAWIDTH); + #1 $finish; + end + + if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111)) + RX_OS_CFG_BINARY = RX_OS_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RX_OS_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG); + #1 $finish; + end + + if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127)) + SAS_MAX_COM_BINARY = SAS_MAX_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MAX_COM on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM); + #1 $finish; + end + + if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63)) + SAS_MIN_COM_BINARY = SAS_MIN_COM; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MIN_COM on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM); + #1 $finish; + end + + if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111)) + SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN); + #1 $finish; + end + + if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111)) + SATA_BURST_VAL_BINARY = SATA_BURST_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL); + #1 $finish; + end + + if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111)) + SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL); + #1 $finish; + end + + if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63)) + SATA_MAX_BURST_BINARY = SATA_MAX_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST); + #1 $finish; + end + + if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63)) + SATA_MAX_INIT_BINARY = SATA_MAX_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT); + #1 $finish; + end + + if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63)) + SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE); + #1 $finish; + end + + if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61)) + SATA_MIN_BURST_BINARY = SATA_MIN_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST); + #1 $finish; + end + + if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63)) + SATA_MIN_INIT_BINARY = SATA_MIN_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT); + #1 $finish; + end + + if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63)) + SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE); + #1 $finish; + end + + if ((SIM_CPLLREFCLK_SEL >= 3'b0) && (SIM_CPLLREFCLK_SEL <= 3'b111)) + SIM_CPLLREFCLK_SEL_BINARY = SIM_CPLLREFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_CPLLREFCLK_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_CPLLREFCLK_SEL); + #1 $finish; + end + + if ((TERM_RCAL_CFG >= 5'b00000) && (TERM_RCAL_CFG <= 5'b11111)) + TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TERM_RCAL_CFG); + #1 $finish; + end + + if ((TERM_RCAL_OVRD >= 1'b0) && (TERM_RCAL_OVRD <= 1'b1)) + TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TERM_RCAL_OVRD); + #1 $finish; + end + + if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111)) + TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME); + #1 $finish; + end + + if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111)) + TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL); + #1 $finish; + end + + if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111)) + TXPMARESET_TIME_BINARY = TXPMARESET_TIME; + else begin + $display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME); + #1 $finish; + end + + if ((TX_CLKMUX_PD >= 1'b0) && (TX_CLKMUX_PD <= 1'b1)) + TX_CLKMUX_PD_BINARY = TX_CLKMUX_PD; + else begin + $display("Attribute Syntax Error : The Attribute TX_CLKMUX_PD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_PD); + #1 $finish; + end + + if ((TX_DEEMPH0 >= 5'b00000) && (TX_DEEMPH0 <= 5'b11111)) + TX_DEEMPH0_BINARY = TX_DEEMPH0; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TX_DEEMPH0); + #1 $finish; + end + + if ((TX_DEEMPH1 >= 5'b00000) && (TX_DEEMPH1 <= 5'b11111)) + TX_DEEMPH1_BINARY = TX_DEEMPH1; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TX_DEEMPH1); + #1 $finish; + end + + if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111)) + TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY); + #1 $finish; + end + + if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111)) + TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY); + #1 $finish; + end + + if ((TX_INT_DATAWIDTH >= 0) && (TX_INT_DATAWIDTH <= 1)) + TX_INT_DATAWIDTH_BINARY = TX_INT_DATAWIDTH; + else begin + $display("Attribute Syntax Error : The Attribute TX_INT_DATAWIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", TX_INT_DATAWIDTH); + #1 $finish; + end + + if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1)) + TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL); + #1 $finish; + end + + if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111)) + TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0); + #1 $finish; + end + + if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111)) + TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1); + #1 $finish; + end + + if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111)) + TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2); + #1 $finish; + end + + if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111)) + TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3); + #1 $finish; + end + + if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111)) + TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4); + #1 $finish; + end + + if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111)) + TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0); + #1 $finish; + end + + if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111)) + TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1); + #1 $finish; + end + + if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111)) + TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2); + #1 $finish; + end + + if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111)) + TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3); + #1 $finish; + end + + if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111)) + TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4); + #1 $finish; + end + + if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1)) + TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE; + else begin + $display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE); + #1 $finish; + end + + if ((TX_QPI_STATUS_EN >= 1'b0) && (TX_QPI_STATUS_EN <= 1'b1)) + TX_QPI_STATUS_EN_BINARY = TX_QPI_STATUS_EN; + else begin + $display("Attribute Syntax Error : The Attribute TX_QPI_STATUS_EN on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_QPI_STATUS_EN); + #1 $finish; + end + + if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111)) + TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF; + else begin + $display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF); + #1 $finish; + end + + if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1)) + UCODEER_CLR_BINARY = UCODEER_CLR; + else begin + $display("Attribute Syntax Error : The Attribute UCODEER_CLR on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR); + #1 $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [15:0] delay_PCSRSVDOUT; + wire [1:0] delay_RXCLKCORCNT; + wire [1:0] delay_TXBUFSTATUS; + wire [2:0] delay_RXBUFSTATUS; + wire [2:0] delay_RXHEADER; + wire [2:0] delay_RXSTATUS; + wire [4:0] delay_RXCHBONDO; + wire [4:0] delay_RXPHMONITOR; + wire [4:0] delay_RXPHSLIPMONITOR; + wire [63:0] delay_RXDATA; + wire [6:0] delay_RXMONITOROUT; + wire [7:0] delay_DMONITOROUT; + wire [7:0] delay_RXCHARISCOMMA; + wire [7:0] delay_RXCHARISK; + wire [7:0] delay_RXDISPERR; + wire [7:0] delay_RXNOTINTABLE; + wire [9:0] delay_TSTOUT; + wire delay_CPLLFBCLKLOST; + wire delay_CPLLLOCK; + wire delay_CPLLREFCLKLOST; + wire delay_DRPRDY; + wire delay_EYESCANDATAERROR; + wire delay_GTREFCLKMONITOR; + wire delay_GTXTXN; + wire delay_GTXTXP; + wire delay_PHYSTATUS; + wire delay_RXBYTEISALIGNED; + wire delay_RXBYTEREALIGN; + wire delay_RXCDRLOCK; + wire delay_RXCHANBONDSEQ; + wire delay_RXCHANISALIGNED; + wire delay_RXCHANREALIGN; + wire delay_RXCOMINITDET; + wire delay_RXCOMMADET; + wire delay_RXCOMSASDET; + wire delay_RXCOMWAKEDET; + wire delay_RXDATAVALID; + wire delay_RXDLYSRESETDONE; + wire delay_RXELECIDLE; + wire delay_RXHEADERVALID; + wire delay_RXOUTCLK; + wire delay_RXOUTCLKFABRIC; + wire delay_RXOUTCLKPCS; + wire delay_RXPHALIGNDONE; + wire delay_RXPRBSERR; + wire delay_RXQPISENN; + wire delay_RXQPISENP; + wire delay_RXRATEDONE; + wire delay_RXRESETDONE; + wire delay_RXSTARTOFSEQ; + wire delay_RXVALID; + wire delay_TXCOMFINISH; + wire delay_TXDLYSRESETDONE; + wire delay_TXGEARBOXREADY; + wire delay_TXOUTCLK; + wire delay_TXOUTCLKFABRIC; + wire delay_TXOUTCLKPCS; + wire delay_TXPHALIGNDONE; + wire delay_TXPHINITDONE; + wire delay_TXQPISENN; + wire delay_TXQPISENP; + wire delay_TXRATEDONE; + wire delay_TXRESETDONE; + + wire [15:0] delay_DRPDI; + wire [15:0] delay_GTRSVD; + wire [15:0] delay_PCSRSVDIN; + wire [19:0] delay_TSTIN; + wire [1:0] delay_RXELECIDLEMODE; + wire [1:0] delay_RXMONITORSEL; + wire [1:0] delay_RXPD; + wire [1:0] delay_RXSYSCLKSEL; + wire [1:0] delay_TXPD; + wire [1:0] delay_TXSYSCLKSEL; + wire [2:0] delay_CPLLREFCLKSEL; + wire [2:0] delay_LOOPBACK; + wire [2:0] delay_RXCHBONDLEVEL; + wire [2:0] delay_RXOUTCLKSEL; + wire [2:0] delay_RXPRBSSEL; + wire [2:0] delay_RXRATE; + wire [2:0] delay_TXBUFDIFFCTRL; + wire [2:0] delay_TXHEADER; + wire [2:0] delay_TXMARGIN; + wire [2:0] delay_TXOUTCLKSEL; + wire [2:0] delay_TXPRBSSEL; + wire [2:0] delay_TXRATE; + wire [3:0] delay_CLKRSVD; + wire [3:0] delay_TXDIFFCTRL; + wire [4:0] delay_PCSRSVDIN2; + wire [4:0] delay_PMARSVDIN2; + wire [4:0] delay_PMARSVDIN; + wire [4:0] delay_RXCHBONDI; + wire [4:0] delay_TXPOSTCURSOR; + wire [4:0] delay_TXPRECURSOR; + wire [63:0] delay_TXDATA; + wire [6:0] delay_TXMAINCURSOR; + wire [6:0] delay_TXSEQUENCE; + wire [7:0] delay_TX8B10BBYPASS; + wire [7:0] delay_TXCHARDISPMODE; + wire [7:0] delay_TXCHARDISPVAL; + wire [7:0] delay_TXCHARISK; + wire [8:0] delay_DRPADDR; + wire delay_CFGRESET; + wire delay_CPLLLOCKDETCLK; + wire delay_CPLLLOCKEN; + wire delay_CPLLPD; + wire delay_CPLLRESET; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_EYESCANMODE; + wire delay_EYESCANRESET; + wire delay_EYESCANTRIGGER; + wire delay_GTGREFCLK; + wire delay_GTNORTHREFCLK0; + wire delay_GTNORTHREFCLK1; + wire delay_GTREFCLK0; + wire delay_GTREFCLK1; + wire delay_GTRESETSEL; + wire delay_GTRXRESET; + wire delay_GTSOUTHREFCLK0; + wire delay_GTSOUTHREFCLK1; + wire delay_GTTXRESET; + wire delay_GTXRXN; + wire delay_GTXRXP; + wire delay_QPLLCLK; + wire delay_QPLLREFCLK; + wire delay_RESETOVRD; + wire delay_RX8B10BEN; + wire delay_RXBUFRESET; + wire delay_RXCDRFREQRESET; + wire delay_RXCDRHOLD; + wire delay_RXCDROVRDEN; + wire delay_RXCDRRESET; + wire delay_RXCDRRESETRSV; + wire delay_RXCHBONDEN; + wire delay_RXCHBONDMASTER; + wire delay_RXCHBONDSLAVE; + wire delay_RXCOMMADETEN; + wire delay_RXDDIEN; + wire delay_RXDFEAGCHOLD; + wire delay_RXDFEAGCOVRDEN; + wire delay_RXDFECM1EN; + wire delay_RXDFELFHOLD; + wire delay_RXDFELFOVRDEN; + wire delay_RXDFELPMRESET; + wire delay_RXDFETAP2HOLD; + wire delay_RXDFETAP2OVRDEN; + wire delay_RXDFETAP3HOLD; + wire delay_RXDFETAP3OVRDEN; + wire delay_RXDFETAP4HOLD; + wire delay_RXDFETAP4OVRDEN; + wire delay_RXDFETAP5HOLD; + wire delay_RXDFETAP5OVRDEN; + wire delay_RXDFEUTHOLD; + wire delay_RXDFEUTOVRDEN; + wire delay_RXDFEVPHOLD; + wire delay_RXDFEVPOVRDEN; + wire delay_RXDFEVSEN; + wire delay_RXDFEXYDEN; + wire delay_RXDFEXYDHOLD; + wire delay_RXDFEXYDOVRDEN; + wire delay_RXDLYBYPASS; + wire delay_RXDLYEN; + wire delay_RXDLYOVRDEN; + wire delay_RXDLYSRESET; + wire delay_RXGEARBOXSLIP; + wire delay_RXLPMEN; + wire delay_RXLPMHFHOLD; + wire delay_RXLPMHFOVRDEN; + wire delay_RXLPMLFHOLD; + wire delay_RXLPMLFKLOVRDEN; + wire delay_RXMCOMMAALIGNEN; + wire delay_RXOOBRESET; + wire delay_RXOSHOLD; + wire delay_RXOSOVRDEN; + wire delay_RXPCOMMAALIGNEN; + wire delay_RXPCSRESET; + wire delay_RXPHALIGN; + wire delay_RXPHALIGNEN; + wire delay_RXPHDLYPD; + wire delay_RXPHDLYRESET; + wire delay_RXPHOVRDEN; + wire delay_RXPMARESET; + wire delay_RXPOLARITY; + wire delay_RXPRBSCNTRESET; + wire delay_RXQPIEN; + wire delay_RXSLIDE; + wire delay_RXUSERRDY; + wire delay_RXUSRCLK2; + wire delay_RXUSRCLK; + wire delay_SETERRSTATUS; + wire delay_TX8B10BEN; + wire delay_TXCOMINIT; + wire delay_TXCOMSAS; + wire delay_TXCOMWAKE; + wire delay_TXDEEMPH; + wire delay_TXDETECTRX; + wire delay_TXDIFFPD; + wire delay_TXDLYBYPASS; + wire delay_TXDLYEN; + wire delay_TXDLYHOLD; + wire delay_TXDLYOVRDEN; + wire delay_TXDLYSRESET; + wire delay_TXDLYUPDOWN; + wire delay_TXELECIDLE; + wire delay_TXINHIBIT; + wire delay_TXPCSRESET; + wire delay_TXPDELECIDLEMODE; + wire delay_TXPHALIGN; + wire delay_TXPHALIGNEN; + wire delay_TXPHDLYPD; + wire delay_TXPHDLYRESET; + wire delay_TXPHDLYTSTCLK; + wire delay_TXPHINIT; + wire delay_TXPHOVRDEN; + wire delay_TXPISOPD; + wire delay_TXPMARESET; + wire delay_TXPOLARITY; + wire delay_TXPOSTCURSORINV; + wire delay_TXPRBSFORCEERR; + wire delay_TXPRECURSORINV; + wire delay_TXQPIBIASEN; + wire delay_TXQPISTRONGPDOWN; + wire delay_TXQPIWEAKPUP; + wire delay_TXSTARTSEQ; + wire delay_TXSWING; + wire delay_TXUSERRDY; + wire delay_TXUSRCLK2; + wire delay_TXUSRCLK; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + reg [0:0] IS_CPLLLOCKDETCLK_INVERTED_REG = IS_CPLLLOCKDETCLK_INVERTED; + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED; + reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED; + reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED; + reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED; + reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED; + reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED; + + assign GTREFCLKMONITOR = delay_GTREFCLKMONITOR; + assign RXOUTCLK = delay_RXOUTCLK; + assign TXOUTCLK = delay_TXOUTCLK; + + assign CPLLFBCLKLOST = delay_CPLLFBCLKLOST; + assign CPLLLOCK = delay_CPLLLOCK; + assign CPLLREFCLKLOST = delay_CPLLREFCLKLOST; + assign DMONITOROUT = delay_DMONITOROUT; + assign DRPDO = delay_DRPDO; + assign DRPRDY = delay_DRPRDY; + assign EYESCANDATAERROR = delay_EYESCANDATAERROR; + assign GTXTXN = delay_GTXTXN; + assign GTXTXP = delay_GTXTXP; + assign PCSRSVDOUT = delay_PCSRSVDOUT; + assign PHYSTATUS = delay_PHYSTATUS; + assign RXBUFSTATUS = delay_RXBUFSTATUS; + assign RXBYTEISALIGNED = delay_RXBYTEISALIGNED; + assign RXBYTEREALIGN = delay_RXBYTEREALIGN; + assign RXCDRLOCK = delay_RXCDRLOCK; + assign RXCHANBONDSEQ = delay_RXCHANBONDSEQ; + assign RXCHANISALIGNED = delay_RXCHANISALIGNED; + assign RXCHANREALIGN = delay_RXCHANREALIGN; + assign RXCHARISCOMMA = delay_RXCHARISCOMMA; + assign RXCHARISK = delay_RXCHARISK; + assign RXCHBONDO = delay_RXCHBONDO; + assign RXCLKCORCNT = delay_RXCLKCORCNT; + assign RXCOMINITDET = delay_RXCOMINITDET; + assign RXCOMMADET = delay_RXCOMMADET; + assign RXCOMSASDET = delay_RXCOMSASDET; + assign RXCOMWAKEDET = delay_RXCOMWAKEDET; + assign RXDATAVALID = delay_RXDATAVALID; + assign RXDATA = delay_RXDATA; + assign RXDISPERR = delay_RXDISPERR; + assign RXDLYSRESETDONE = delay_RXDLYSRESETDONE; + assign RXELECIDLE = delay_RXELECIDLE; + assign RXHEADERVALID = delay_RXHEADERVALID; + assign RXHEADER = delay_RXHEADER; + assign RXMONITOROUT = delay_RXMONITOROUT; + assign RXNOTINTABLE = delay_RXNOTINTABLE; + assign RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC; + assign RXOUTCLKPCS = delay_RXOUTCLKPCS; + assign RXPHALIGNDONE = delay_RXPHALIGNDONE; + assign RXPHMONITOR = delay_RXPHMONITOR; + assign RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR; + assign RXPRBSERR = delay_RXPRBSERR; + assign RXQPISENN = delay_RXQPISENN; + assign RXQPISENP = delay_RXQPISENP; + assign RXRATEDONE = delay_RXRATEDONE; + assign RXRESETDONE = delay_RXRESETDONE; + assign RXSTARTOFSEQ = delay_RXSTARTOFSEQ; + assign RXSTATUS = delay_RXSTATUS; + assign RXVALID = delay_RXVALID; + assign TSTOUT = delay_TSTOUT; + assign TXBUFSTATUS = delay_TXBUFSTATUS; + assign TXCOMFINISH = delay_TXCOMFINISH; + assign TXDLYSRESETDONE = delay_TXDLYSRESETDONE; + assign TXGEARBOXREADY = delay_TXGEARBOXREADY; + assign TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC; + assign TXOUTCLKPCS = delay_TXOUTCLKPCS; + assign TXPHALIGNDONE = delay_TXPHALIGNDONE; + assign TXPHINITDONE = delay_TXPHINITDONE; + assign TXQPISENN = delay_TXQPISENN; + assign TXQPISENP = delay_TXQPISENP; + assign TXRATEDONE = delay_TXRATEDONE; + assign TXRESETDONE = delay_TXRESETDONE; + +`ifndef XIL_TIMING // unisim + assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK ^ IS_CPLLLOCKDETCLK_INVERTED_REG; + assign delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_QPLLCLK = QPLLCLK; + assign delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK_INVERTED_REG; + assign delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG; + assign delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG; + assign delay_TXUSRCLK = TXUSRCLK ^ IS_TXUSRCLK_INVERTED_REG; + assign delay_TXUSRCLK2 = TXUSRCLK2 ^ IS_TXUSRCLK2_INVERTED_REG; + + assign delay_CFGRESET = CFGRESET; + assign delay_CLKRSVD = CLKRSVD; + assign delay_CPLLLOCKEN = CPLLLOCKEN; + assign delay_CPLLPD = CPLLPD; + assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL; + assign delay_CPLLRESET = CPLLRESET; + assign delay_DRPADDR = DRPADDR; + assign delay_DRPDI = DRPDI; + assign delay_DRPEN = DRPEN; + assign delay_DRPWE = DRPWE; + assign delay_EYESCANMODE = EYESCANMODE; + assign delay_EYESCANRESET = EYESCANRESET; + assign delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign delay_GTRESETSEL = GTRESETSEL; + assign delay_GTRSVD = GTRSVD; + assign delay_GTRXRESET = GTRXRESET; + assign delay_GTTXRESET = GTTXRESET; + assign delay_GTXRXN = GTXRXN; + assign delay_GTXRXP = GTXRXP; + assign delay_LOOPBACK = LOOPBACK; + assign delay_PCSRSVDIN = PCSRSVDIN; + assign delay_PCSRSVDIN2 = PCSRSVDIN2; + assign delay_PMARSVDIN = PMARSVDIN; + assign delay_PMARSVDIN2 = PMARSVDIN2; + assign delay_QPLLREFCLK = QPLLREFCLK; + assign delay_RESETOVRD = RESETOVRD; + assign delay_RX8B10BEN = RX8B10BEN; + assign delay_RXBUFRESET = RXBUFRESET; + assign delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign delay_RXCDRHOLD = RXCDRHOLD; + assign delay_RXCDROVRDEN = RXCDROVRDEN; + assign delay_RXCDRRESET = RXCDRRESET; + assign delay_RXCDRRESETRSV = RXCDRRESETRSV; + assign delay_RXCHBONDEN = RXCHBONDEN; + assign delay_RXCHBONDI = RXCHBONDI; + assign delay_RXCHBONDLEVEL = RXCHBONDLEVEL; + assign delay_RXCHBONDMASTER = RXCHBONDMASTER; + assign delay_RXCHBONDSLAVE = RXCHBONDSLAVE; + assign delay_RXCOMMADETEN = RXCOMMADETEN; + assign delay_RXDDIEN = RXDDIEN; + assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD; + assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN; + assign delay_RXDFECM1EN = RXDFECM1EN; + assign delay_RXDFELFHOLD = RXDFELFHOLD; + assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN; + assign delay_RXDFELPMRESET = RXDFELPMRESET; + assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD; + assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN; + assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD; + assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN; + assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD; + assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN; + assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD; + assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN; + assign delay_RXDFEUTHOLD = RXDFEUTHOLD; + assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN; + assign delay_RXDFEVPHOLD = RXDFEVPHOLD; + assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN; + assign delay_RXDFEVSEN = RXDFEVSEN; + assign delay_RXDFEXYDEN = RXDFEXYDEN; + assign delay_RXDFEXYDHOLD = RXDFEXYDHOLD; + assign delay_RXDFEXYDOVRDEN = RXDFEXYDOVRDEN; + assign delay_RXDLYBYPASS = RXDLYBYPASS; + assign delay_RXDLYEN = RXDLYEN; + assign delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign delay_RXDLYSRESET = RXDLYSRESET; + assign delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign delay_RXGEARBOXSLIP = RXGEARBOXSLIP; + assign delay_RXLPMEN = RXLPMEN; + assign delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN; + assign delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN; + assign delay_RXMONITORSEL = RXMONITORSEL; + assign delay_RXOOBRESET = RXOOBRESET; + assign delay_RXOSHOLD = RXOSHOLD; + assign delay_RXOSOVRDEN = RXOSOVRDEN; + assign delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN; + assign delay_RXPCSRESET = RXPCSRESET; + assign delay_RXPD = RXPD; + assign delay_RXPHALIGN = RXPHALIGN; + assign delay_RXPHALIGNEN = RXPHALIGNEN; + assign delay_RXPHDLYPD = RXPHDLYPD; + assign delay_RXPHDLYRESET = RXPHDLYRESET; + assign delay_RXPHOVRDEN = RXPHOVRDEN; + assign delay_RXPMARESET = RXPMARESET; + assign delay_RXPOLARITY = RXPOLARITY; + assign delay_RXPRBSCNTRESET = RXPRBSCNTRESET; + assign delay_RXPRBSSEL = RXPRBSSEL; + assign delay_RXQPIEN = RXQPIEN; + assign delay_RXRATE = RXRATE; + assign delay_RXSLIDE = RXSLIDE; + assign delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign delay_RXUSERRDY = RXUSERRDY; + assign delay_SETERRSTATUS = SETERRSTATUS; + assign delay_TSTIN = TSTIN; + assign delay_TX8B10BBYPASS = TX8B10BBYPASS; + assign delay_TX8B10BEN = TX8B10BEN; + assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign delay_TXCHARDISPMODE = TXCHARDISPMODE; + assign delay_TXCHARDISPVAL = TXCHARDISPVAL; + assign delay_TXCHARISK = TXCHARISK; + assign delay_TXCOMINIT = TXCOMINIT; + assign delay_TXCOMSAS = TXCOMSAS; + assign delay_TXCOMWAKE = TXCOMWAKE; + assign delay_TXDATA = TXDATA; + assign delay_TXDEEMPH = TXDEEMPH; + assign delay_TXDETECTRX = TXDETECTRX; + assign delay_TXDIFFCTRL = TXDIFFCTRL; + assign delay_TXDIFFPD = TXDIFFPD; + assign delay_TXDLYBYPASS = TXDLYBYPASS; + assign delay_TXDLYEN = TXDLYEN; + assign delay_TXDLYHOLD = TXDLYHOLD; + assign delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign delay_TXDLYSRESET = TXDLYSRESET; + assign delay_TXDLYUPDOWN = TXDLYUPDOWN; + assign delay_TXELECIDLE = TXELECIDLE; + assign delay_TXHEADER = TXHEADER; + assign delay_TXINHIBIT = TXINHIBIT; + assign delay_TXMAINCURSOR = TXMAINCURSOR; + assign delay_TXMARGIN = TXMARGIN; + assign delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign delay_TXPCSRESET = TXPCSRESET; + assign delay_TXPD = TXPD; + assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign delay_TXPHALIGN = TXPHALIGN; + assign delay_TXPHALIGNEN = TXPHALIGNEN; + assign delay_TXPHDLYPD = TXPHDLYPD; + assign delay_TXPHDLYRESET = TXPHDLYRESET; + assign delay_TXPHINIT = TXPHINIT; + assign delay_TXPHOVRDEN = TXPHOVRDEN; + assign delay_TXPISOPD = TXPISOPD; + assign delay_TXPMARESET = TXPMARESET; + assign delay_TXPOLARITY = TXPOLARITY; + assign delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign delay_TXPRBSFORCEERR = TXPRBSFORCEERR; + assign delay_TXPRBSSEL = TXPRBSSEL; + assign delay_TXPRECURSOR = TXPRECURSOR; + assign delay_TXPRECURSORINV = TXPRECURSORINV; + assign delay_TXQPIBIASEN = TXQPIBIASEN; + assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN; + assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP; + assign delay_TXRATE = TXRATE; + assign delay_TXSEQUENCE = TXSEQUENCE; + assign delay_TXSTARTSEQ = TXSTARTSEQ; + assign delay_TXSWING = TXSWING; + assign delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign delay_TXUSERRDY = TXUSERRDY; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_CFGRESET = CFGRESET; + assign delay_CLKRSVD = CLKRSVD; + assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK; + assign delay_CPLLLOCKEN = CPLLLOCKEN; + assign delay_CPLLPD = CPLLPD; + assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL; + assign delay_CPLLRESET = CPLLRESET; + assign delay_EYESCANMODE = EYESCANMODE; + assign delay_EYESCANRESET = EYESCANRESET; + assign delay_EYESCANTRIGGER = EYESCANTRIGGER; + assign delay_GTGREFCLK = GTGREFCLK; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTRESETSEL = GTRESETSEL; + assign delay_GTRSVD = GTRSVD; + assign delay_GTRXRESET = GTRXRESET; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_GTTXRESET = GTTXRESET; + assign delay_GTXRXN = GTXRXN; + assign delay_GTXRXP = GTXRXP; + assign delay_LOOPBACK = LOOPBACK; + assign delay_PCSRSVDIN = PCSRSVDIN; + assign delay_PCSRSVDIN2 = PCSRSVDIN2; + assign delay_PMARSVDIN = PMARSVDIN; + assign delay_PMARSVDIN2 = PMARSVDIN2; + assign delay_QPLLCLK = QPLLCLK; + assign delay_QPLLREFCLK = QPLLREFCLK; + assign delay_RESETOVRD = RESETOVRD; + assign delay_RXBUFRESET = RXBUFRESET; + assign delay_RXCDRFREQRESET = RXCDRFREQRESET; + assign delay_RXCDRHOLD = RXCDRHOLD; + assign delay_RXCDROVRDEN = RXCDROVRDEN; + assign delay_RXCDRRESET = RXCDRRESET; + assign delay_RXCDRRESETRSV = RXCDRRESETRSV; + assign delay_RXDDIEN = RXDDIEN; + assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD; + assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN; + assign delay_RXDFECM1EN = RXDFECM1EN; + assign delay_RXDFELFHOLD = RXDFELFHOLD; + assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN; + assign delay_RXDFELPMRESET = RXDFELPMRESET; + assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD; + assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN; + assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD; + assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN; + assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD; + assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN; + assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD; + assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN; + assign delay_RXDFEUTHOLD = RXDFEUTHOLD; + assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN; + assign delay_RXDFEVPHOLD = RXDFEVPHOLD; + assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN; + assign delay_RXDFEVSEN = RXDFEVSEN; + assign delay_RXDFEXYDEN = RXDFEXYDEN; + assign delay_RXDFEXYDHOLD = RXDFEXYDHOLD; + assign delay_RXDFEXYDOVRDEN = RXDFEXYDOVRDEN; + assign delay_RXDLYBYPASS = RXDLYBYPASS; + assign delay_RXDLYEN = RXDLYEN; + assign delay_RXDLYOVRDEN = RXDLYOVRDEN; + assign delay_RXDLYSRESET = RXDLYSRESET; + assign delay_RXELECIDLEMODE = RXELECIDLEMODE; + assign delay_RXLPMEN = RXLPMEN; + assign delay_RXLPMHFHOLD = RXLPMHFHOLD; + assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; + assign delay_RXLPMLFHOLD = RXLPMLFHOLD; + assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN; + assign delay_RXMONITORSEL = RXMONITORSEL; + assign delay_RXOOBRESET = RXOOBRESET; + assign delay_RXOSHOLD = RXOSHOLD; + assign delay_RXOSOVRDEN = RXOSOVRDEN; + assign delay_RXOUTCLKSEL = RXOUTCLKSEL; + assign delay_RXPCSRESET = RXPCSRESET; + assign delay_RXPHALIGN = RXPHALIGN; + assign delay_RXPHALIGNEN = RXPHALIGNEN; + assign delay_RXPHDLYPD = RXPHDLYPD; + assign delay_RXPHDLYRESET = RXPHDLYRESET; + assign delay_RXPHOVRDEN = RXPHOVRDEN; + assign delay_RXPMARESET = RXPMARESET; + assign delay_RXQPIEN = RXQPIEN; + assign delay_RXSYSCLKSEL = RXSYSCLKSEL; + assign delay_RXUSERRDY = RXUSERRDY; + //assign delay_RXUSRCLK = RXUSRCLK; + assign delay_TSTIN = TSTIN; + assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign delay_TXDEEMPH = TXDEEMPH; + assign delay_TXDIFFCTRL = TXDIFFCTRL; + assign delay_TXDIFFPD = TXDIFFPD; + assign delay_TXDLYBYPASS = TXDLYBYPASS; + assign delay_TXDLYEN = TXDLYEN; + assign delay_TXDLYOVRDEN = TXDLYOVRDEN; + assign delay_TXDLYSRESET = TXDLYSRESET; + assign delay_TXMAINCURSOR = TXMAINCURSOR; + assign delay_TXMARGIN = TXMARGIN; + assign delay_TXOUTCLKSEL = TXOUTCLKSEL; + assign delay_TXPCSRESET = TXPCSRESET; + assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; + assign delay_TXPHALIGN = TXPHALIGN; + assign delay_TXPHALIGNEN = TXPHALIGNEN; + assign delay_TXPHDLYPD = TXPHDLYPD; + assign delay_TXPHDLYRESET = TXPHDLYRESET; + assign delay_TXPHINIT = TXPHINIT; + assign delay_TXPHOVRDEN = TXPHOVRDEN; + assign delay_TXPISOPD = TXPISOPD; + assign delay_TXPMARESET = TXPMARESET; + assign delay_TXPOSTCURSOR = TXPOSTCURSOR; + assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; + assign delay_TXPRECURSOR = TXPRECURSOR; + assign delay_TXPRECURSORINV = TXPRECURSORINV; + assign delay_TXQPIBIASEN = TXQPIBIASEN; + assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN; + assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP; + assign delay_TXSWING = TXSWING; + assign delay_TXSYSCLKSEL = TXSYSCLKSEL; + assign delay_TXUSERRDY = TXUSERRDY; + assign delay_TXUSRCLK = TXUSRCLK; + + wire cplllockdetclk_en_p; + wire cplllockdetclk_en_n; + wire drpclk_en_p; + wire drpclk_en_n; + wire rxusrclk2_en_p; + wire rxusrclk2_en_n; + wire rxusrclk_en_p; + wire rxusrclk_en_n; + wire txphdlytstclk_en_p; + wire txphdlytstclk_en_n; + wire txusrclk2_en_p; + wire txusrclk2_en_n; + + assign cplllockdetclk_en_p = ~IS_CPLLLOCKDETCLK_INVERTED; + assign cplllockdetclk_en_n = IS_CPLLLOCKDETCLK_INVERTED; + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; + assign rxusrclk2_en_p = ~IS_RXUSRCLK2_INVERTED; + assign rxusrclk2_en_n = IS_RXUSRCLK2_INVERTED; + assign rxusrclk_en_p = ~IS_RXUSRCLK_INVERTED; + assign rxusrclk_en_n = IS_RXUSRCLK_INVERTED; + assign txphdlytstclk_en_p = ~IS_TXPHDLYTSTCLK_INVERTED; + assign txphdlytstclk_en_n = IS_TXPHDLYTSTCLK_INVERTED; + assign txusrclk2_en_p = ~IS_TXUSRCLK2_INVERTED; + assign txusrclk2_en_n = IS_TXUSRCLK2_INVERTED; +`endif + + B_GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN), + .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN), + .CLK_CORRECT_USE (CLK_CORRECT_USE), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE), + .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN), + .CPLL_CFG (CPLL_CFG), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_45), + .CPLL_INIT_CFG (CPLL_INIT_CFG), + .CPLL_LOCK_CFG (CPLL_LOCK_CFG), + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY), + .DMONITOR_CFG (DMONITOR_CFG), + .ES_CONTROL (ES_CONTROL), + .ES_ERRDET_EN (ES_ERRDET_EN), + .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN), + .ES_HORZ_OFFSET (ES_HORZ_OFFSET), + .ES_PMA_CFG (ES_PMA_CFG), + .ES_PRESCALE (ES_PRESCALE), + .ES_QUALIFIER (ES_QUALIFIER), + .ES_QUAL_MASK (ES_QUAL_MASK), + .ES_SDATA_MASK (ES_SDATA_MASK), + .ES_VERT_OFFSET (ES_VERT_OFFSET), + .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE), + .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG), + .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN), + .GEARBOX_MODE (GEARBOX_MODE), + .OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV), + .PCS_PCIE_EN (PCS_PCIE_EN), + .PCS_RSVD_ATTR (PCS_RSVD_ATTR), + .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2), + .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2), + .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2), + .PMA_RSV (PMA_RSV), + .PMA_RSV2 (PMA_RSV2), + .PMA_RSV3 (PMA_RSV3), + .PMA_RSV4 (PMA_RSV4), + .RXBUFRESET_TIME (RXBUFRESET_TIME), + .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE), + .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT), + .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE), + .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN), + .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE), + .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE), + .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW), + .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME), + .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME), + .RXCDR_CFG (RXCDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE), + .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE), + .RXCDR_LOCK_CFG (RXCDR_LOCK_CFG), + .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE), + .RXDFELPMRESET_TIME (RXDFELPMRESET_TIME), + .RXDLY_CFG (RXDLY_CFG), + .RXDLY_LCFG (RXDLY_LCFG), + .RXDLY_TAP_CFG (RXDLY_TAP_CFG), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (RXISCANRESET_TIME), + .RXLPM_HF_CFG (RXLPM_HF_CFG), + .RXLPM_LF_CFG (RXLPM_LF_CFG), + .RXOOB_CFG (RXOOB_CFG), + .RXOUT_DIV (RXOUT_DIV), + .RXPCSRESET_TIME (RXPCSRESET_TIME), + .RXPHDLY_CFG (RXPHDLY_CFG), + .RXPH_CFG (RXPH_CFG), + .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL), + .RXPMARESET_TIME (RXPMARESET_TIME), + .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK), + .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT), + .RXSLIDE_MODE (RXSLIDE_MODE), + .RX_BIAS_CFG (RX_BIAS_CFG), + .RX_BUFFER_CFG (RX_BUFFER_CFG), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_PD (RX_CLKMUX_PD), + .RX_CM_SEL (RX_CM_SEL), + .RX_CM_TRIM (RX_CM_TRIM), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (RX_DDI_SEL), + .RX_DEBUG_CFG (RX_DEBUG_CFG), + .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN), + .RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG), + .RX_DFE_H2_CFG (RX_DFE_H2_CFG), + .RX_DFE_H3_CFG (RX_DFE_H3_CFG), + .RX_DFE_H4_CFG (RX_DFE_H4_CFG), + .RX_DFE_H5_CFG (RX_DFE_H5_CFG), + .RX_DFE_KL_CFG (RX_DFE_KL_CFG), + .RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE), + .RX_DFE_UT_CFG (RX_DFE_UT_CFG), + .RX_DFE_VP_CFG (RX_DFE_VP_CFG), + .RX_DFE_XYD_CFG (RX_DFE_XYD_CFG), + .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), + .RX_OS_CFG (RX_OS_CFG), + .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY), + .RX_XCLK_SEL (RX_XCLK_SEL), + .SAS_MAX_COM (SAS_MAX_COM), + .SAS_MIN_COM (SAS_MIN_COM), + .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN), + .SATA_BURST_VAL (SATA_BURST_VAL), + .SATA_CPLL_CFG (SATA_CPLL_CFG), + .SATA_EIDLE_VAL (SATA_EIDLE_VAL), + .SATA_MAX_BURST (SATA_MAX_BURST), + .SATA_MAX_INIT (SATA_MAX_INIT), + .SATA_MAX_WAKE (SATA_MAX_WAKE), + .SATA_MIN_BURST (SATA_MIN_BURST), + .SATA_MIN_INIT (SATA_MIN_INIT), + .SATA_MIN_WAKE (SATA_MIN_WAKE), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA), + .SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL), + .SIM_VERSION (SIM_VERSION), + .TERM_RCAL_CFG (TERM_RCAL_CFG), + .TERM_RCAL_OVRD (TERM_RCAL_OVRD), + .TRANS_TIME_RATE (TRANS_TIME_RATE), + .TST_RSV (TST_RSV), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE), + .TXDLY_CFG (TXDLY_CFG), + .TXDLY_LCFG (TXDLY_LCFG), + .TXDLY_TAP_CFG (TXDLY_TAP_CFG), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOUT_DIV (TXOUT_DIV), + .TXPCSRESET_TIME (TXPCSRESET_TIME), + .TXPHDLY_CFG (TXPHDLY_CFG), + .TXPH_CFG (TXPH_CFG), + .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL), + .TXPMARESET_TIME (TXPMARESET_TIME), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_PD (TX_CLKMUX_PD), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DEEMPH0 (TX_DEEMPH0), + .TX_DEEMPH1 (TX_DEEMPH1), + .TX_DRIVE_MODE (TX_DRIVE_MODE), + .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY), + .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH), + .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ), + .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), + .TX_PREDRIVER_MODE (TX_PREDRIVER_MODE), + .TX_QPI_STATUS_EN (TX_QPI_STATUS_EN), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), + .TX_RXDETECT_REF (TX_RXDETECT_REF), + .TX_XCLK_SEL (TX_XCLK_SEL), + .UCODEER_CLR (UCODEER_CLR)) + + B_GTXE2_CHANNEL_INST ( + .CPLLFBCLKLOST (delay_CPLLFBCLKLOST), + .CPLLLOCK (delay_CPLLLOCK), + .CPLLREFCLKLOST (delay_CPLLREFCLKLOST), + .DMONITOROUT (delay_DMONITOROUT), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .EYESCANDATAERROR (delay_EYESCANDATAERROR), + .GTREFCLKMONITOR (delay_GTREFCLKMONITOR), + .GTXTXN (delay_GTXTXN), + .GTXTXP (delay_GTXTXP), + .PCSRSVDOUT (delay_PCSRSVDOUT), + .PHYSTATUS (delay_PHYSTATUS), + .RXBUFSTATUS (delay_RXBUFSTATUS), + .RXBYTEISALIGNED (delay_RXBYTEISALIGNED), + .RXBYTEREALIGN (delay_RXBYTEREALIGN), + .RXCDRLOCK (delay_RXCDRLOCK), + .RXCHANBONDSEQ (delay_RXCHANBONDSEQ), + .RXCHANISALIGNED (delay_RXCHANISALIGNED), + .RXCHANREALIGN (delay_RXCHANREALIGN), + .RXCHARISCOMMA (delay_RXCHARISCOMMA), + .RXCHARISK (delay_RXCHARISK), + .RXCHBONDO (delay_RXCHBONDO), + .RXCLKCORCNT (delay_RXCLKCORCNT), + .RXCOMINITDET (delay_RXCOMINITDET), + .RXCOMMADET (delay_RXCOMMADET), + .RXCOMSASDET (delay_RXCOMSASDET), + .RXCOMWAKEDET (delay_RXCOMWAKEDET), + .RXDATA (delay_RXDATA), + .RXDATAVALID (delay_RXDATAVALID), + .RXDISPERR (delay_RXDISPERR), + .RXDLYSRESETDONE (delay_RXDLYSRESETDONE), + .RXELECIDLE (delay_RXELECIDLE), + .RXHEADER (delay_RXHEADER), + .RXHEADERVALID (delay_RXHEADERVALID), + .RXMONITOROUT (delay_RXMONITOROUT), + .RXNOTINTABLE (delay_RXNOTINTABLE), + .RXOUTCLK (delay_RXOUTCLK), + .RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC), + .RXOUTCLKPCS (delay_RXOUTCLKPCS), + .RXPHALIGNDONE (delay_RXPHALIGNDONE), + .RXPHMONITOR (delay_RXPHMONITOR), + .RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR), + .RXPRBSERR (delay_RXPRBSERR), + .RXQPISENN (delay_RXQPISENN), + .RXQPISENP (delay_RXQPISENP), + .RXRATEDONE (delay_RXRATEDONE), + .RXRESETDONE (delay_RXRESETDONE), + .RXSTARTOFSEQ (delay_RXSTARTOFSEQ), + .RXSTATUS (delay_RXSTATUS), + .RXVALID (delay_RXVALID), + .TSTOUT (delay_TSTOUT), + .TXBUFSTATUS (delay_TXBUFSTATUS), + .TXCOMFINISH (delay_TXCOMFINISH), + .TXDLYSRESETDONE (delay_TXDLYSRESETDONE), + .TXGEARBOXREADY (delay_TXGEARBOXREADY), + .TXOUTCLK (delay_TXOUTCLK), + .TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC), + .TXOUTCLKPCS (delay_TXOUTCLKPCS), + .TXPHALIGNDONE (delay_TXPHALIGNDONE), + .TXPHINITDONE (delay_TXPHINITDONE), + .TXQPISENN (delay_TXQPISENN), + .TXQPISENP (delay_TXQPISENP), + .TXRATEDONE (delay_TXRATEDONE), + .TXRESETDONE (delay_TXRESETDONE), + .CFGRESET (delay_CFGRESET), + .CLKRSVD (delay_CLKRSVD), + .CPLLLOCKDETCLK (delay_CPLLLOCKDETCLK), + .CPLLLOCKEN (delay_CPLLLOCKEN), + .CPLLPD (delay_CPLLPD), + .CPLLREFCLKSEL (delay_CPLLREFCLKSEL), + .CPLLRESET (delay_CPLLRESET), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .EYESCANMODE (delay_EYESCANMODE), + .EYESCANRESET (delay_EYESCANRESET), + .EYESCANTRIGGER (delay_EYESCANTRIGGER), + .GTGREFCLK (delay_GTGREFCLK), + .GTNORTHREFCLK0 (delay_GTNORTHREFCLK0), + .GTNORTHREFCLK1 (delay_GTNORTHREFCLK1), + .GTREFCLK0 (delay_GTREFCLK0), + .GTREFCLK1 (delay_GTREFCLK1), + .GTRESETSEL (delay_GTRESETSEL), + .GTRSVD (delay_GTRSVD), + .GTRXRESET (delay_GTRXRESET), + .GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0), + .GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1), + .GTTXRESET (delay_GTTXRESET), + .GTXRXN (delay_GTXRXN), + .GTXRXP (delay_GTXRXP), + .LOOPBACK (delay_LOOPBACK), + .PCSRSVDIN (delay_PCSRSVDIN), + .PCSRSVDIN2 (delay_PCSRSVDIN2), + .PMARSVDIN (delay_PMARSVDIN), + .PMARSVDIN2 (delay_PMARSVDIN2), + .QPLLCLK (delay_QPLLCLK), + .QPLLREFCLK (delay_QPLLREFCLK), + .RESETOVRD (delay_RESETOVRD), + .RX8B10BEN (delay_RX8B10BEN), + .RXBUFRESET (delay_RXBUFRESET), + .RXCDRFREQRESET (delay_RXCDRFREQRESET), + .RXCDRHOLD (delay_RXCDRHOLD), + .RXCDROVRDEN (delay_RXCDROVRDEN), + .RXCDRRESET (delay_RXCDRRESET), + .RXCDRRESETRSV (delay_RXCDRRESETRSV), + .RXCHBONDEN (delay_RXCHBONDEN), + .RXCHBONDI (delay_RXCHBONDI), + .RXCHBONDLEVEL (delay_RXCHBONDLEVEL), + .RXCHBONDMASTER (delay_RXCHBONDMASTER), + .RXCHBONDSLAVE (delay_RXCHBONDSLAVE), + .RXCOMMADETEN (delay_RXCOMMADETEN), + .RXDDIEN (delay_RXDDIEN), + .RXDFEAGCHOLD (delay_RXDFEAGCHOLD), + .RXDFEAGCOVRDEN (delay_RXDFEAGCOVRDEN), + .RXDFECM1EN (delay_RXDFECM1EN), + .RXDFELFHOLD (delay_RXDFELFHOLD), + .RXDFELFOVRDEN (delay_RXDFELFOVRDEN), + .RXDFELPMRESET (delay_RXDFELPMRESET), + .RXDFETAP2HOLD (delay_RXDFETAP2HOLD), + .RXDFETAP2OVRDEN (delay_RXDFETAP2OVRDEN), + .RXDFETAP3HOLD (delay_RXDFETAP3HOLD), + .RXDFETAP3OVRDEN (delay_RXDFETAP3OVRDEN), + .RXDFETAP4HOLD (delay_RXDFETAP4HOLD), + .RXDFETAP4OVRDEN (delay_RXDFETAP4OVRDEN), + .RXDFETAP5HOLD (delay_RXDFETAP5HOLD), + .RXDFETAP5OVRDEN (delay_RXDFETAP5OVRDEN), + .RXDFEUTHOLD (delay_RXDFEUTHOLD), + .RXDFEUTOVRDEN (delay_RXDFEUTOVRDEN), + .RXDFEVPHOLD (delay_RXDFEVPHOLD), + .RXDFEVPOVRDEN (delay_RXDFEVPOVRDEN), + .RXDFEVSEN (delay_RXDFEVSEN), + .RXDFEXYDEN (delay_RXDFEXYDEN), + .RXDFEXYDHOLD (delay_RXDFEXYDHOLD), + .RXDFEXYDOVRDEN (delay_RXDFEXYDOVRDEN), + .RXDLYBYPASS (delay_RXDLYBYPASS), + .RXDLYEN (delay_RXDLYEN), + .RXDLYOVRDEN (delay_RXDLYOVRDEN), + .RXDLYSRESET (delay_RXDLYSRESET), + .RXELECIDLEMODE (delay_RXELECIDLEMODE), + .RXGEARBOXSLIP (delay_RXGEARBOXSLIP), + .RXLPMEN (delay_RXLPMEN), + .RXLPMHFHOLD (delay_RXLPMHFHOLD), + .RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN), + .RXLPMLFHOLD (delay_RXLPMLFHOLD), + .RXLPMLFKLOVRDEN (delay_RXLPMLFKLOVRDEN), + .RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN), + .RXMONITORSEL (delay_RXMONITORSEL), + .RXOOBRESET (delay_RXOOBRESET), + .RXOSHOLD (delay_RXOSHOLD), + .RXOSOVRDEN (delay_RXOSOVRDEN), + .RXOUTCLKSEL (delay_RXOUTCLKSEL), + .RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN), + .RXPCSRESET (delay_RXPCSRESET), + .RXPD (delay_RXPD), + .RXPHALIGN (delay_RXPHALIGN), + .RXPHALIGNEN (delay_RXPHALIGNEN), + .RXPHDLYPD (delay_RXPHDLYPD), + .RXPHDLYRESET (delay_RXPHDLYRESET), + .RXPHOVRDEN (delay_RXPHOVRDEN), + .RXPMARESET (delay_RXPMARESET), + .RXPOLARITY (delay_RXPOLARITY), + .RXPRBSCNTRESET (delay_RXPRBSCNTRESET), + .RXPRBSSEL (delay_RXPRBSSEL), + .RXQPIEN (delay_RXQPIEN), + .RXRATE (delay_RXRATE), + .RXSLIDE (delay_RXSLIDE), + .RXSYSCLKSEL (delay_RXSYSCLKSEL), + .RXUSERRDY (delay_RXUSERRDY), + .RXUSRCLK (delay_RXUSRCLK), + .RXUSRCLK2 (delay_RXUSRCLK2), + .SETERRSTATUS (delay_SETERRSTATUS), + .TSTIN (delay_TSTIN), + .TX8B10BBYPASS (delay_TX8B10BBYPASS), + .TX8B10BEN (delay_TX8B10BEN), + .TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL), + .TXCHARDISPMODE (delay_TXCHARDISPMODE), + .TXCHARDISPVAL (delay_TXCHARDISPVAL), + .TXCHARISK (delay_TXCHARISK), + .TXCOMINIT (delay_TXCOMINIT), + .TXCOMSAS (delay_TXCOMSAS), + .TXCOMWAKE (delay_TXCOMWAKE), + .TXDATA (delay_TXDATA), + .TXDEEMPH (delay_TXDEEMPH), + .TXDETECTRX (delay_TXDETECTRX), + .TXDIFFCTRL (delay_TXDIFFCTRL), + .TXDIFFPD (delay_TXDIFFPD), + .TXDLYBYPASS (delay_TXDLYBYPASS), + .TXDLYEN (delay_TXDLYEN), + .TXDLYHOLD (delay_TXDLYHOLD), + .TXDLYOVRDEN (delay_TXDLYOVRDEN), + .TXDLYSRESET (delay_TXDLYSRESET), + .TXDLYUPDOWN (delay_TXDLYUPDOWN), + .TXELECIDLE (delay_TXELECIDLE), + .TXHEADER (delay_TXHEADER), + .TXINHIBIT (delay_TXINHIBIT), + .TXMAINCURSOR (delay_TXMAINCURSOR), + .TXMARGIN (delay_TXMARGIN), + .TXOUTCLKSEL (delay_TXOUTCLKSEL), + .TXPCSRESET (delay_TXPCSRESET), + .TXPD (delay_TXPD), + .TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE), + .TXPHALIGN (delay_TXPHALIGN), + .TXPHALIGNEN (delay_TXPHALIGNEN), + .TXPHDLYPD (delay_TXPHDLYPD), + .TXPHDLYRESET (delay_TXPHDLYRESET), + .TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK), + .TXPHINIT (delay_TXPHINIT), + .TXPHOVRDEN (delay_TXPHOVRDEN), + .TXPISOPD (delay_TXPISOPD), + .TXPMARESET (delay_TXPMARESET), + .TXPOLARITY (delay_TXPOLARITY), + .TXPOSTCURSOR (delay_TXPOSTCURSOR), + .TXPOSTCURSORINV (delay_TXPOSTCURSORINV), + .TXPRBSFORCEERR (delay_TXPRBSFORCEERR), + .TXPRBSSEL (delay_TXPRBSSEL), + .TXPRECURSOR (delay_TXPRECURSOR), + .TXPRECURSORINV (delay_TXPRECURSORINV), + .TXQPIBIASEN (delay_TXQPIBIASEN), + .TXQPISTRONGPDOWN (delay_TXQPISTRONGPDOWN), + .TXQPIWEAKPUP (delay_TXQPIWEAKPUP), + .TXRATE (delay_TXRATE), + .TXSEQUENCE (delay_TXSEQUENCE), + .TXSTARTSEQ (delay_TXSTARTSEQ), + .TXSWING (delay_TXSWING), + .TXSYSCLKSEL (delay_TXSYSCLKSEL), + .TXUSERRDY (delay_TXUSERRDY), + .TXUSRCLK (delay_TXUSRCLK), + .TXUSRCLK2 (delay_TXUSRCLK2), + .GSR(GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge CLKRSVD[0], 0:0:0, notifier); + $period (posedge CLKRSVD[1], 0:0:0, notifier); + $period (posedge CPLLLOCKDETCLK, 0:0:0, notifier); + $period (negedge CPLLLOCKDETCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge GTGREFCLK, 0:0:0, notifier); + $period (negedge GTGREFCLK, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK0, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLK0, 0:0:0, notifier); + $period (posedge GTREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLKMONITOR, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK0, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK1, 0:0:0, notifier); + $period (posedge QPLLCLK, 0:0:0, notifier); + $period (posedge RXOUTCLK, 0:0:0, notifier); + $period (posedge RXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge RXOUTCLKPCS, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge TXOUTCLK, 0:0:0, notifier); + $period (posedge TXOUTCLKFABRIC, 0:0:0, notifier); + $period (posedge TXOUTCLKPCS, 0:0:0, notifier); + $period (posedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (negedge TXPHDLYTSTCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI); + + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, negedge RXPD, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPD); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (posedge RXUSRCLK2, posedge RXPD, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPD); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, negedge RXPD, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPD); + $setuphold (negedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (negedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER); + $setuphold (negedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); + $setuphold (negedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN); + $setuphold (negedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); + $setuphold (negedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); + $setuphold (negedge RXUSRCLK2, posedge RXPD, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPD); + $setuphold (negedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); + $setuphold (negedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL); + $setuphold (negedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE); + $setuphold (negedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE); + $setuphold (negedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); + $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS); + $setuphold (negedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE); + $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL); + $setuphold (negedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK); + $setuphold (negedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT); + $setuphold (negedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS); + $setuphold (negedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE); + $setuphold (negedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA); + $setuphold (negedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX); + $setuphold (negedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE); + $setuphold (negedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER); + $setuphold (negedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT); + $setuphold (negedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD); + $setuphold (negedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); + $setuphold (negedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL); + $setuphold (negedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE); + $setuphold (negedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE); + $setuphold (negedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ); +`endif + ( CLKRSVD[1:1] *> DMONITOROUT[7:0]) = (0, 0); + ( CLKRSVD[1:1] *> PCSRSVDOUT[8:2]) = (0, 0); + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( GTNORTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTNORTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( GTREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( GTSOUTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0); + ( GTSOUTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0); + ( QPLLCLK *> GTREFCLKMONITOR) = (0, 0); + ( RXUSRCLK *> RXCHBONDO) = (0, 0); + ( RXUSRCLK2 *> PHYSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0); + ( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0); + ( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0); + ( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0); + ( RXUSRCLK2 *> RXCHARISK) = (0, 0); + ( RXUSRCLK2 *> RXCHBONDO) = (0, 0); + ( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0); + ( RXUSRCLK2 *> RXCOMINITDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMMADET) = (0, 0); + ( RXUSRCLK2 *> RXCOMSASDET) = (0, 0); + ( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0); + ( RXUSRCLK2 *> RXDATA) = (0, 0); + ( RXUSRCLK2 *> RXDATAVALID) = (0, 0); + ( RXUSRCLK2 *> RXDISPERR) = (0, 0); + ( RXUSRCLK2 *> RXHEADER) = (0, 0); + ( RXUSRCLK2 *> RXHEADERVALID) = (0, 0); + ( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0); + ( RXUSRCLK2 *> RXPRBSERR) = (0, 0); + ( RXUSRCLK2 *> RXRATEDONE) = (0, 0); + ( RXUSRCLK2 *> RXRESETDONE) = (0, 0); + ( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0); + ( RXUSRCLK2 *> RXSTATUS) = (0, 0); + ( RXUSRCLK2 *> RXVALID) = (0, 0); + ( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0); + ( TXUSRCLK2 *> TXCOMFINISH) = (0, 0); + ( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0); + ( TXUSRCLK2 *> TXRATEDONE) = (0, 0); + ( TXUSRCLK2 *> TXRESETDONE) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/GTXE2_COMMON.v b/verilog/src/unisims/GTXE2_COMMON.v new file mode 100644 index 0000000..66144d6 --- /dev/null +++ b/verilog/src/unisims/GTXE2_COMMON.v @@ -0,0 +1,593 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTXE2_COMMON.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl +// Revision: 1.0 +// 01/18/13 - 695630 - added drp monitor +// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +`celldefine + +module GTXE2_COMMON ( + DRPDO, + DRPRDY, + QPLLDMONITOR, + QPLLFBCLKLOST, + QPLLLOCK, + QPLLOUTCLK, + QPLLOUTREFCLK, + QPLLREFCLKLOST, + REFCLKOUTMONITOR, + + BGBYPASSB, + BGMONITORENB, + BGPDB, + BGRCALOVRD, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + GTGREFCLK, + GTNORTHREFCLK0, + GTNORTHREFCLK1, + GTREFCLK0, + GTREFCLK1, + GTSOUTHREFCLK0, + GTSOUTHREFCLK1, + PMARSVD, + QPLLLOCKDETCLK, + QPLLLOCKEN, + QPLLOUTRESET, + QPLLPD, + QPLLREFCLKSEL, + QPLLRESET, + QPLLRSVD1, + QPLLRSVD2, + RCALENB +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0680181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h21E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "4.0"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [7:0] QPLLDMONITOR; + + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input DRPCLK; + input DRPEN; + input DRPWE; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; + + reg SIM_RESET_SPEEDUP_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY; + reg [0:0] QPLL_CP_MONITOR_EN_BINARY; + reg [0:0] QPLL_DMONITOR_SEL_BINARY; + reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY; + reg [0:0] QPLL_FBDIV_RATIO_BINARY; + reg [2:0] SIM_QPLLREFCLK_SEL_BINARY; + reg [3:0] QPLL_CLKOUT_CFG_BINARY; + reg [3:0] QPLL_LPF_BINARY; + reg [4:0] QPLL_REFCLK_DIV_BINARY; + reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY; + reg [9:0] QPLL_CP_BINARY; + reg [9:0] QPLL_FBDIV_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (QPLL_REFCLK_DIV) + 2 : QPLL_REFCLK_DIV_BINARY = 5'b00000; + 1 : QPLL_REFCLK_DIV_BINARY = 5'b10000; + 3 : QPLL_REFCLK_DIV_BINARY = 5'b00001; + 4 : QPLL_REFCLK_DIV_BINARY = 5'b00010; + 5 : QPLL_REFCLK_DIV_BINARY = 5'b00011; + 6 : QPLL_REFCLK_DIV_BINARY = 5'b00101; + 8 : QPLL_REFCLK_DIV_BINARY = 5'b00110; + 10 : QPLL_REFCLK_DIV_BINARY = 5'b00111; + 12 : QPLL_REFCLK_DIV_BINARY = 5'b01101; + 16 : QPLL_REFCLK_DIV_BINARY = 5'b01110; + 20 : QPLL_REFCLK_DIV_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on X_GTXE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2); + #1 $finish; + end + endcase + + case (SIM_RESET_SPEEDUP) + "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; + "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "4.0" : SIM_VERSION_BINARY = 0; + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + "3.0" : SIM_VERSION_BINARY = 0; + "4.1" : SIM_VERSION_BINARY = 0; + "5.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are 4.0, 1.0, 1.1, 2.0, 3.0, 4.1, or 5.0.", SIM_VERSION); + #1 $finish; + end + endcase + + + if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111)) + QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG); + #1 $finish; + end + + if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111)) + QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD); + #1 $finish; + end + + if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1)) + QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN); + #1 $finish; + end + + if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111)) + QPLL_CP_BINARY = QPLL_CP; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CP on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP); + #1 $finish; + end + + if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1)) + QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN); + #1 $finish; + end + + if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1)) + QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL); + #1 $finish; + end + + if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111)) + QPLL_FBDIV_BINARY = QPLL_FBDIV; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV); + #1 $finish; + end + + if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1)) + QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN); + #1 $finish; + end + + if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1)) + QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO); + #1 $finish; + end + + if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111)) + QPLL_LPF_BINARY = QPLL_LPF; + else begin + $display("Attribute Syntax Error : The Attribute QPLL_LPF on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF); + #1 $finish; + end + + if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111)) + SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL; + else begin + $display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL); + #1 $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [7:0] delay_QPLLDMONITOR; + wire delay_DRPRDY; + wire delay_QPLLFBCLKLOST; + wire delay_QPLLLOCK; + wire delay_QPLLOUTCLK; + wire delay_QPLLOUTREFCLK; + wire delay_QPLLREFCLKLOST; + wire delay_REFCLKOUTMONITOR; + + wire [15:0] delay_DRPDI; + wire [15:0] delay_QPLLRSVD1; + wire [2:0] delay_QPLLREFCLKSEL; + wire [4:0] delay_BGRCALOVRD; + wire [4:0] delay_QPLLRSVD2; + wire [7:0] delay_DRPADDR; + wire [7:0] delay_PMARSVD; + wire delay_BGBYPASSB; + wire delay_BGMONITORENB; + wire delay_BGPDB; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_GTGREFCLK; + wire delay_GTNORTHREFCLK0; + wire delay_GTNORTHREFCLK1; + wire delay_GTREFCLK0; + wire delay_GTREFCLK1; + wire delay_GTSOUTHREFCLK0; + wire delay_GTSOUTHREFCLK1; + wire delay_QPLLLOCKDETCLK; + wire delay_QPLLLOCKEN; + wire delay_QPLLOUTRESET; + wire delay_QPLLPD; + wire delay_QPLLRESET; + wire delay_RCALENB; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; + reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED; + reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED; + + + assign #(OUTCLK_DELAY) QPLLOUTCLK = delay_QPLLOUTCLK; + assign #(OUTCLK_DELAY) REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR; + + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPRDY = delay_DRPRDY; + assign #(out_delay) QPLLDMONITOR = delay_QPLLDMONITOR; + assign #(out_delay) QPLLFBCLKLOST = delay_QPLLFBCLKLOST; + assign #(out_delay) QPLLLOCK = delay_QPLLLOCK; + assign #(out_delay) QPLLOUTREFCLK = delay_QPLLOUTREFCLK; + assign #(out_delay) QPLLREFCLKLOST = delay_QPLLREFCLKLOST; + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG; + assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0; + assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1; + assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign #(INCLK_DELAY) delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG; + + assign #(in_delay) delay_BGBYPASSB = BGBYPASSB; + assign #(in_delay) delay_BGMONITORENB = BGMONITORENB; + assign #(in_delay) delay_BGPDB = BGPDB; + assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD; + assign #(in_delay) delay_DRPADDR = DRPADDR; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPEN = DRPEN; + assign #(in_delay) delay_DRPWE = DRPWE; + assign #(in_delay) delay_PMARSVD = PMARSVD; + assign #(in_delay) delay_QPLLLOCKEN = QPLLLOCKEN; + assign #(in_delay) delay_QPLLOUTRESET = QPLLOUTRESET; + assign #(in_delay) delay_QPLLPD = QPLLPD; + assign #(in_delay) delay_QPLLREFCLKSEL = QPLLREFCLKSEL; + assign #(in_delay) delay_QPLLRESET = QPLLRESET; + assign #(in_delay) delay_QPLLRSVD1 = QPLLRSVD1; + assign #(in_delay) delay_QPLLRSVD2 = QPLLRSVD2; + assign #(in_delay) delay_RCALENB = RCALENB; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_BGBYPASSB = BGBYPASSB; + assign delay_BGMONITORENB = BGMONITORENB; + assign delay_BGPDB = BGPDB; + assign delay_BGRCALOVRD = BGRCALOVRD; + assign delay_GTGREFCLK = GTGREFCLK; + assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0; + assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1; + assign delay_GTREFCLK0 = GTREFCLK0; + assign delay_GTREFCLK1 = GTREFCLK1; + assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0; + assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1; + assign delay_PMARSVD = PMARSVD; + assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK; + assign delay_QPLLLOCKEN = QPLLLOCKEN; + assign delay_QPLLOUTRESET = QPLLOUTRESET; + assign delay_QPLLPD = QPLLPD; + assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL; + assign delay_QPLLRESET = QPLLRESET; + assign delay_QPLLRSVD1 = QPLLRSVD1; + assign delay_QPLLRSVD2 = QPLLRSVD2; + assign delay_RCALENB = RCALENB; + + wire drpclk_en_p; + wire drpclk_en_n; + + assign drpclk_en_p = ~IS_DRPCLK_INVERTED; + assign drpclk_en_n = IS_DRPCLK_INVERTED; + +`endif + + B_GTXE2_COMMON #( + .BIAS_CFG (BIAS_CFG), + .COMMON_CFG (COMMON_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG), + .QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD), + .QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN), + .QPLL_CP (QPLL_CP), + .QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN), + .QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (QPLL_INIT_CFG), + .QPLL_LOCK_CFG (QPLL_LOCK_CFG), + .QPLL_LPF (QPLL_LPF), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION)) + + B_GTXE2_COMMON_INST ( + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .QPLLDMONITOR (delay_QPLLDMONITOR), + .QPLLFBCLKLOST (delay_QPLLFBCLKLOST), + .QPLLLOCK (delay_QPLLLOCK), + .QPLLOUTCLK (delay_QPLLOUTCLK), + .QPLLOUTREFCLK (delay_QPLLOUTREFCLK), + .QPLLREFCLKLOST (delay_QPLLREFCLKLOST), + .REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR), + .BGBYPASSB (delay_BGBYPASSB), + .BGMONITORENB (delay_BGMONITORENB), + .BGPDB (delay_BGPDB), + .BGRCALOVRD (delay_BGRCALOVRD), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .GTGREFCLK (delay_GTGREFCLK), + .GTNORTHREFCLK0 (delay_GTNORTHREFCLK0), + .GTNORTHREFCLK1 (delay_GTNORTHREFCLK1), + .GTREFCLK0 (delay_GTREFCLK0), + .GTREFCLK1 (delay_GTREFCLK1), + .GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0), + .GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1), + .PMARSVD (delay_PMARSVD), + .QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK), + .QPLLLOCKEN (delay_QPLLLOCKEN), + .QPLLOUTRESET (delay_QPLLOUTRESET), + .QPLLPD (delay_QPLLPD), + .QPLLREFCLKSEL (delay_QPLLREFCLKSEL), + .QPLLRESET (delay_QPLLRESET), + .QPLLRSVD1 (delay_QPLLRSVD1), + .QPLLRSVD2 (delay_QPLLRSVD2), + .RCALENB (delay_RCALENB), + .GSR(GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge DRPCLK, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge GTGREFCLK, 0:0:0, notifier); + $period (negedge GTGREFCLK, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK0, 0:0:0, notifier); + $period (posedge GTNORTHREFCLK1, 0:0:0, notifier); + $period (posedge GTREFCLK0, 0:0:0, notifier); + $period (posedge GTREFCLK1, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK0, 0:0:0, notifier); + $period (posedge GTSOUTHREFCLK1, 0:0:0, notifier); + $period (posedge QPLLLOCKDETCLK, 0:0:0, notifier); + $period (negedge QPLLLOCKDETCLK, 0:0:0, notifier); + $period (posedge QPLLOUTCLK, 0:0:0, notifier); + $period (posedge REFCLKOUTMONITOR, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR); + $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); + $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR); + $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI); + $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN); + $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE); +`endif + + ( DRPCLK *> DRPDO) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0); + ( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + ( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + ( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0); + ( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTYE3_CHANNEL.v b/verilog/src/unisims/GTYE3_CHANNEL.v new file mode 100644 index 0000000..c378972 --- /dev/null +++ b/verilog/src/unisims/GTYE3_CHANNEL.v @@ -0,0 +1,5924 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : GTYE3_CHANNEL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTYE3_CHANNEL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0, + parameter [0:0] ACJTAG_MODE = 1'b0, + parameter [0:0] ACJTAG_RESET = 1'b0, + parameter [15:0] ADAPT_CFG0 = 16'h9200, + parameter [15:0] ADAPT_CFG1 = 16'h801C, + parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000, + parameter ALIGN_COMMA_DOUBLE = "FALSE", + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111, + parameter integer ALIGN_COMMA_WORD = 1, + parameter ALIGN_MCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011, + parameter ALIGN_PCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100, + parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0, + parameter [0:0] A_RXOSCALRESET = 1'b0, + parameter [0:0] A_RXPROGDIVRESET = 1'b0, + parameter [4:0] A_TXDIFFCTRL = 5'b01100, + parameter [0:0] A_TXPROGDIVRESET = 1'b0, + parameter [0:0] CAPBYPASS_FORCE = 1'b0, + parameter CBCC_DATA_SOURCE_SEL = "DECODED", + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0, + parameter CHAN_BOND_KEEP_ALIGN = "FALSE", + parameter integer CHAN_BOND_MAX_SKEW = 7, + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100, + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111, + parameter CHAN_BOND_SEQ_2_USE = "FALSE", + parameter integer CHAN_BOND_SEQ_LEN = 2, + parameter [15:0] CH_HSPMUX = 16'h0000, + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000, + parameter [15:0] CKCAL_RSVD0 = 16'h4000, + parameter [15:0] CKCAL_RSVD1 = 16'h0000, + parameter CLK_CORRECT_USE = "TRUE", + parameter CLK_COR_KEEP_IDLE = "FALSE", + parameter integer CLK_COR_MAX_LAT = 20, + parameter integer CLK_COR_MIN_LAT = 18, + parameter CLK_COR_PRECEDENCE = "TRUE", + parameter integer CLK_COR_REPEAT_WAIT = 0, + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100, + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111, + parameter CLK_COR_SEQ_2_USE = "FALSE", + parameter integer CLK_COR_SEQ_LEN = 2, + parameter [15:0] CPLL_CFG0 = 16'h20FA, + parameter [15:0] CPLL_CFG1 = 16'h24AA, + parameter [15:0] CPLL_CFG2 = 16'hF007, + parameter [5:0] CPLL_CFG3 = 6'h00, + parameter integer CPLL_FBDIV = 4, + parameter integer CPLL_FBDIV_45 = 4, + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E, + parameter [7:0] CPLL_INIT_CFG1 = 8'h00, + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8, + parameter integer CPLL_REFCLK_DIV = 1, + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000, + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0, + parameter [1:0] DDI_CTRL = 2'b00, + parameter integer DDI_REALIGN_WAIT = 15, + parameter DEC_MCOMMA_DETECT = "TRUE", + parameter DEC_PCOMMA_DETECT = "TRUE", + parameter DEC_VALID_COMMA_ONLY = "TRUE", + parameter [0:0] DFE_D_X_REL_POS = 1'b0, + parameter [0:0] DFE_VCM_COMP_EN = 1'b0, + parameter [9:0] DMONITOR_CFG0 = 10'h000, + parameter [7:0] DMONITOR_CFG1 = 8'h00, + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0, + parameter [5:0] ES_CONTROL = 6'b000000, + parameter ES_ERRDET_EN = "FALSE", + parameter ES_EYE_SCAN_EN = "FALSE", + parameter [11:0] ES_HORZ_OFFSET = 12'h000, + parameter [9:0] ES_PMA_CFG = 10'b0000000000, + parameter [4:0] ES_PRESCALE = 5'b00000, + parameter [15:0] ES_QUALIFIER0 = 16'h0000, + parameter [15:0] ES_QUALIFIER1 = 16'h0000, + parameter [15:0] ES_QUALIFIER2 = 16'h0000, + parameter [15:0] ES_QUALIFIER3 = 16'h0000, + parameter [15:0] ES_QUALIFIER4 = 16'h0000, + parameter [15:0] ES_QUALIFIER5 = 16'h0000, + parameter [15:0] ES_QUALIFIER6 = 16'h0000, + parameter [15:0] ES_QUALIFIER7 = 16'h0000, + parameter [15:0] ES_QUALIFIER8 = 16'h0000, + parameter [15:0] ES_QUALIFIER9 = 16'h0000, + parameter [15:0] ES_QUAL_MASK0 = 16'h0000, + parameter [15:0] ES_QUAL_MASK1 = 16'h0000, + parameter [15:0] ES_QUAL_MASK2 = 16'h0000, + parameter [15:0] ES_QUAL_MASK3 = 16'h0000, + parameter [15:0] ES_QUAL_MASK4 = 16'h0000, + parameter [15:0] ES_QUAL_MASK5 = 16'h0000, + parameter [15:0] ES_QUAL_MASK6 = 16'h0000, + parameter [15:0] ES_QUAL_MASK7 = 16'h0000, + parameter [15:0] ES_QUAL_MASK8 = 16'h0000, + parameter [15:0] ES_QUAL_MASK9 = 16'h0000, + parameter [15:0] ES_SDATA_MASK0 = 16'h0000, + parameter [15:0] ES_SDATA_MASK1 = 16'h0000, + parameter [15:0] ES_SDATA_MASK2 = 16'h0000, + parameter [15:0] ES_SDATA_MASK3 = 16'h0000, + parameter [15:0] ES_SDATA_MASK4 = 16'h0000, + parameter [15:0] ES_SDATA_MASK5 = 16'h0000, + parameter [15:0] ES_SDATA_MASK6 = 16'h0000, + parameter [15:0] ES_SDATA_MASK7 = 16'h0000, + parameter [15:0] ES_SDATA_MASK8 = 16'h0000, + parameter [15:0] ES_SDATA_MASK9 = 16'h0000, + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000, + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0, + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111, + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111, + parameter FTS_LANE_DESKEW_EN = "FALSE", + parameter [4:0] GEARBOX_MODE = 5'b00000, + parameter [0:0] GM_BIAS_SELECT = 1'b0, + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0, + parameter [0:0] LOCAL_MASTER = 1'b0, + parameter [15:0] LOOP0_CFG = 16'h0000, + parameter [15:0] LOOP10_CFG = 16'h0000, + parameter [15:0] LOOP11_CFG = 16'h0000, + parameter [15:0] LOOP12_CFG = 16'h0000, + parameter [15:0] LOOP13_CFG = 16'h0000, + parameter [15:0] LOOP1_CFG = 16'h0000, + parameter [15:0] LOOP2_CFG = 16'h0000, + parameter [15:0] LOOP3_CFG = 16'h0000, + parameter [15:0] LOOP4_CFG = 16'h0000, + parameter [15:0] LOOP5_CFG = 16'h0000, + parameter [15:0] LOOP6_CFG = 16'h0000, + parameter [15:0] LOOP7_CFG = 16'h0000, + parameter [15:0] LOOP8_CFG = 16'h0000, + parameter [15:0] LOOP9_CFG = 16'h0000, + parameter [2:0] LPBK_BIAS_CTRL = 3'b000, + parameter [0:0] LPBK_EN_RCAL_B = 1'b0, + parameter [3:0] LPBK_EXT_RCAL = 4'b0000, + parameter [3:0] LPBK_RG_CTRL = 4'b0000, + parameter [1:0] OOBDIVCTL = 2'b00, + parameter [0:0] OOB_PWRUP = 1'b0, + parameter PCI3_AUTO_REALIGN = "FRST_SMPL", + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1, + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00, + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0, + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000, + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000, + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000, + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0, + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0, + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000, + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000, + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000, + parameter PCS_PCIE_EN = "FALSE", + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000, + parameter [2:0] PCS_RSVD1 = 3'b000, + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C, + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19, + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64, + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0, + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0, + parameter [15:0] PMA_RSV0 = 16'h00E0, + parameter [15:0] PMA_RSV1 = 16'h000A, + parameter integer PREIQ_FREQ_BST = 0, + parameter [2:0] PROCESS_PAR = 3'b010, + parameter [0:0] RATE_SW_USE_DRP = 1'b0, + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0, + parameter [4:0] RXBUFRESET_TIME = 5'b00001, + parameter RXBUF_ADDR_MODE = "FULL", + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000, + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000, + parameter RXBUF_EN = "TRUE", + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE", + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE", + parameter RXBUF_RESET_ON_EIDLE = "FALSE", + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE", + parameter integer RXBUF_THRESH_OVFLW = 0, + parameter RXBUF_THRESH_OVRD = "FALSE", + parameter integer RXBUF_THRESH_UNDFLW = 4, + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001, + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001, + parameter [15:0] RXCDR_CFG0 = 16'h0000, + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG1 = 16'h0300, + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300, + parameter [15:0] RXCDR_CFG2 = 16'h0060, + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060, + parameter [15:0] RXCDR_CFG3 = 16'h0000, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG4 = 16'h0002, + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002, + parameter [15:0] RXCDR_CFG5 = 16'h0000, + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000, + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0, + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0, + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001, + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000, + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0, + parameter [1:0] RXCFOKDONE_SRC = 2'b00, + parameter [15:0] RXCFOK_CFG0 = 16'h3E00, + parameter [15:0] RXCFOK_CFG1 = 16'h0042, + parameter [15:0] RXCFOK_CFG2 = 16'h002D, + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111, + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000, + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022, + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100, + parameter [15:0] RXDFE_CFG0 = 16'h4C00, + parameter [15:0] RXDFE_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00, + parameter [15:0] RXDFE_GC_CFG1 = 16'h1900, + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003, + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002, + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000, + parameter [15:0] RXDFE_OS_CFG1 = 16'h0200, + parameter [0:0] RXDFE_PWR_SAVING = 1'b0, + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000, + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002, + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000, + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022, + parameter [15:0] RXDLY_CFG = 16'h001F, + parameter [15:0] RXDLY_LCFG = 16'h0030, + parameter RXELECIDLE_CFG = "SIGCFG_4", + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter RXGEARBOX_EN = "FALSE", + parameter [4:0] RXISCANRESET_TIME = 5'b00001, + parameter [15:0] RXLPM_CFG = 16'h0000, + parameter [15:0] RXLPM_GC_CFG = 16'h0200, + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000, + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002, + parameter [15:0] RXLPM_OS_CFG0 = 16'h0400, + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000, + parameter [8:0] RXOOB_CFG = 9'b000000110, + parameter RXOOB_CLK_CFG = "PMA", + parameter [4:0] RXOSCALRESET_TIME = 5'b00011, + parameter integer RXOUT_DIV = 4, + parameter [4:0] RXPCSRESET_TIME = 5'b00001, + parameter [15:0] RXPHBEACON_CFG = 16'h0000, + parameter [15:0] RXPHDLY_CFG = 16'h2020, + parameter [15:0] RXPHSAMP_CFG = 16'h2100, + parameter [15:0] RXPHSLIP_CFG = 16'h9933, + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000, + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0, + parameter [15:0] RXPI_CFG = 16'h0100, + parameter [0:0] RXPI_LPM = 1'b0, + parameter [15:0] RXPI_RSV0 = 16'h0000, + parameter [1:0] RXPI_SEL_LC = 2'b00, + parameter [1:0] RXPI_STARTCODE = 2'b00, + parameter [0:0] RXPI_VREFSEL = 1'b0, + parameter RXPMACLK_SEL = "DATA", + parameter [4:0] RXPMARESET_TIME = 5'b00001, + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0, + parameter integer RXPRBS_LINKACQ_CNT = 15, + parameter integer RXSLIDE_AUTO_WAIT = 7, + parameter RXSLIDE_MODE = "OFF", + parameter [0:0] RXSYNC_MULTILANE = 1'b0, + parameter [0:0] RXSYNC_OVRD = 1'b0, + parameter [0:0] RXSYNC_SKIP_DA = 1'b0, + parameter [0:0] RX_AFE_CM_EN = 1'b0, + parameter [15:0] RX_BIAS_CFG0 = 16'h1534, + parameter [5:0] RX_BUFFER_CFG = 6'b000000, + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0, + parameter integer RX_CLK25_DIV = 8, + parameter [0:0] RX_CLKMUX_EN = 1'b1, + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000, + parameter [3:0] RX_CM_BUF_CFG = 4'b1010, + parameter [0:0] RX_CM_BUF_PD = 1'b0, + parameter integer RX_CM_SEL = 3, + parameter integer RX_CM_TRIM = 10, + parameter [0:0] RX_CTLE1_KHKL = 1'b0, + parameter [0:0] RX_CTLE2_KHKL = 1'b0, + parameter [0:0] RX_CTLE3_AGC = 1'b0, + parameter integer RX_DATA_WIDTH = 20, + parameter [5:0] RX_DDI_SEL = 6'b000000, + parameter RX_DEFER_RESET_BUF_EN = "TRUE", + parameter [2:0] RX_DEGEN_CTRL = 3'b011, + parameter integer RX_DFELPM_CFG0 = 0, + parameter [0:0] RX_DFELPM_CFG1 = 1'b1, + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1, + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00, + parameter integer RX_DFE_AGC_CFG1 = 2, + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1, + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2, + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01, + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010, + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0, + parameter RX_DISPERR_SEQ_MATCH = "TRUE", + parameter [0:0] RX_DIV2_MODE_B = 1'b0, + parameter [4:0] RX_DIVRESET_TIME = 5'b00001, + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0, + parameter [0:0] RX_EN_HI_LR = 1'b0, + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000, + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000, + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0, + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00, + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0, + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0, + parameter integer RX_INT_DATAWIDTH = 1, + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0, + parameter real RX_PROGDIV_CFG = 0.0, + parameter [15:0] RX_PROGDIV_RATE = 16'h0001, + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000, + parameter [0:0] RX_RESLOAD_OVRD = 1'b0, + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101, + parameter integer RX_SIG_VALID_DLY = 11, + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0, + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000, + parameter [3:0] RX_SUM_VCMTUNE = 4'b1000, + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0, + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100, + parameter [1:0] RX_TUNE_AFE_OS = 2'b00, + parameter [2:0] RX_VREG_CTRL = 3'b101, + parameter [0:0] RX_VREG_PDB = 1'b1, + parameter [1:0] RX_WIDEMODE_CDR = 2'b01, + parameter RX_XCLK_SEL = "RXDES", + parameter [0:0] RX_XMODE_SEL = 1'b0, + parameter integer SAS_MAX_COM = 64, + parameter integer SAS_MIN_COM = 36, + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111, + parameter [2:0] SATA_BURST_VAL = 3'b100, + parameter SATA_CPLL_CFG = "VCO_3000MHZ", + parameter [2:0] SATA_EIDLE_VAL = 3'b100, + parameter integer SATA_MAX_BURST = 8, + parameter integer SATA_MAX_INIT = 21, + parameter integer SATA_MAX_WAKE = 7, + parameter integer SATA_MIN_BURST = 4, + parameter integer SATA_MIN_INIT = 12, + parameter integer SATA_MIN_WAKE = 4, + parameter SHOW_REALIGN_COMMA = "TRUE", + parameter SIM_MODE = "FAST", + parameter SIM_RECEIVER_DETECT_PASS = "TRUE", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0, + parameter integer SIM_VERSION = 2, + parameter [1:0] TAPDLY_SET_TX = 2'h0, + parameter [3:0] TEMPERATURE_PAR = 4'b0010, + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000, + parameter [2:0] TERM_RCAL_OVRD = 3'b000, + parameter [7:0] TRANS_TIME_RATE = 8'h0E, + parameter [7:0] TST_RSV0 = 8'h00, + parameter [7:0] TST_RSV1 = 8'h00, + parameter TXBUF_EN = "TRUE", + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE", + parameter [15:0] TXDLY_CFG = 16'h001F, + parameter [15:0] TXDLY_LCFG = 16'h0030, + parameter TXFIFO_ADDR_CFG = "LOW", + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter TXGEARBOX_EN = "FALSE", + parameter integer TXOUT_DIV = 4, + parameter [4:0] TXPCSRESET_TIME = 5'b00001, + parameter [15:0] TXPHDLY_CFG0 = 16'h2020, + parameter [15:0] TXPHDLY_CFG1 = 16'h0001, + parameter [15:0] TXPH_CFG = 16'h0123, + parameter [15:0] TXPH_CFG2 = 16'h0000, + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000, + parameter [1:0] TXPI_CFG0 = 2'b00, + parameter [1:0] TXPI_CFG1 = 2'b00, + parameter [1:0] TXPI_CFG2 = 2'b00, + parameter [0:0] TXPI_CFG3 = 1'b0, + parameter [0:0] TXPI_CFG4 = 1'b1, + parameter [2:0] TXPI_CFG5 = 3'b000, + parameter [0:0] TXPI_GRAY_SEL = 1'b0, + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0, + parameter [0:0] TXPI_LPM = 1'b0, + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2", + parameter [7:0] TXPI_PPM_CFG = 8'b00000000, + parameter [15:0] TXPI_RSV0 = 16'h0000, + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000, + parameter [0:0] TXPI_VREFSEL = 1'b0, + parameter [4:0] TXPMARESET_TIME = 5'b00001, + parameter [0:0] TXSYNC_MULTILANE = 1'b0, + parameter [0:0] TXSYNC_OVRD = 1'b0, + parameter [0:0] TXSYNC_SKIP_DA = 1'b0, + parameter integer TX_CLK25_DIV = 8, + parameter [0:0] TX_CLKMUX_EN = 1'b1, + parameter [0:0] TX_CLKREG_PDB = 1'b0, + parameter [2:0] TX_CLKREG_SET = 3'b000, + parameter integer TX_DATA_WIDTH = 20, + parameter [5:0] TX_DCD_CFG = 6'b000010, + parameter [0:0] TX_DCD_EN = 1'b0, + parameter [5:0] TX_DEEMPH0 = 6'b000000, + parameter [5:0] TX_DEEMPH1 = 6'b000000, + parameter [4:0] TX_DIVRESET_TIME = 5'b00001, + parameter TX_DRIVE_MODE = "DIRECT", + parameter integer TX_DRVMUX_CTRL = 2, + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110, + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100, + parameter [0:0] TX_EML_PHI_TUNE = 1'b0, + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0, + parameter [0:0] TX_FIFO_BYP_EN = 1'b0, + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0, + parameter integer TX_INT_DATAWIDTH = 1, + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE", + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0, + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110, + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001, + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101, + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010, + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110, + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100, + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010, + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000, + parameter [2:0] TX_MODE_SEL = 3'b000, + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000, + parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00, + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000, + parameter integer TX_PI_BIASSET = 0, + parameter [15:0] TX_PI_CFG0 = 16'h0000, + parameter [15:0] TX_PI_CFG1 = 16'h0000, + parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0, + parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0, + parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0, + parameter [0:0] TX_PMADATA_OPT = 1'b0, + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0, + parameter integer TX_PREDRV_CTRL = 2, + parameter TX_PROGCLK_SEL = "POSTPI", + parameter real TX_PROGDIV_CFG = 0.0, + parameter [15:0] TX_PROGDIV_RATE = 16'h0001, + parameter [13:0] TX_RXDETECT_CFG = 14'h0032, + parameter integer TX_RXDETECT_REF = 3, + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101, + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0, + parameter TX_XCLK_SEL = "TXOUT", + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0 +)( + output [2:0] BUFGTCE, + output [2:0] BUFGTCEMASK, + output [8:0] BUFGTDIV, + output [2:0] BUFGTRESET, + output [2:0] BUFGTRSTMASK, + output CPLLFBCLKLOST, + output CPLLLOCK, + output CPLLREFCLKLOST, + output [16:0] DMONITOROUT, + output [15:0] DRPDO, + output DRPRDY, + output EYESCANDATAERROR, + output GTPOWERGOOD, + output GTREFCLKMONITOR, + output GTYTXN, + output GTYTXP, + output PCIERATEGEN3, + output PCIERATEIDLE, + output [1:0] PCIERATEQPLLPD, + output [1:0] PCIERATEQPLLRESET, + output PCIESYNCTXSYNCDONE, + output PCIEUSERGEN3RDY, + output PCIEUSERPHYSTATUSRST, + output PCIEUSERRATESTART, + output [15:0] PCSRSVDOUT, + output PHYSTATUS, + output [7:0] PINRSRVDAS, + output RESETEXCEPTION, + output [2:0] RXBUFSTATUS, + output RXBYTEISALIGNED, + output RXBYTEREALIGN, + output RXCDRLOCK, + output RXCDRPHDONE, + output RXCHANBONDSEQ, + output RXCHANISALIGNED, + output RXCHANREALIGN, + output [4:0] RXCHBONDO, + output RXCKCALDONE, + output [1:0] RXCLKCORCNT, + output RXCOMINITDET, + output RXCOMMADET, + output RXCOMSASDET, + output RXCOMWAKEDET, + output [15:0] RXCTRL0, + output [15:0] RXCTRL1, + output [7:0] RXCTRL2, + output [7:0] RXCTRL3, + output [127:0] RXDATA, + output [7:0] RXDATAEXTENDRSVD, + output [1:0] RXDATAVALID, + output RXDLYSRESETDONE, + output RXELECIDLE, + output [5:0] RXHEADER, + output [1:0] RXHEADERVALID, + output [6:0] RXMONITOROUT, + output RXOSINTDONE, + output RXOSINTSTARTED, + output RXOSINTSTROBEDONE, + output RXOSINTSTROBESTARTED, + output RXOUTCLK, + output RXOUTCLKFABRIC, + output RXOUTCLKPCS, + output RXPHALIGNDONE, + output RXPHALIGNERR, + output RXPMARESETDONE, + output RXPRBSERR, + output RXPRBSLOCKED, + output RXPRGDIVRESETDONE, + output RXRATEDONE, + output RXRECCLKOUT, + output RXRESETDONE, + output RXSLIDERDY, + output RXSLIPDONE, + output RXSLIPOUTCLKRDY, + output RXSLIPPMARDY, + output [1:0] RXSTARTOFSEQ, + output [2:0] RXSTATUS, + output RXSYNCDONE, + output RXSYNCOUT, + output RXVALID, + output [1:0] TXBUFSTATUS, + output TXCOMFINISH, + output TXDCCDONE, + output TXDLYSRESETDONE, + output TXOUTCLK, + output TXOUTCLKFABRIC, + output TXOUTCLKPCS, + output TXPHALIGNDONE, + output TXPHINITDONE, + output TXPMARESETDONE, + output TXPRGDIVRESETDONE, + output TXRATEDONE, + output TXRESETDONE, + output TXSYNCDONE, + output TXSYNCOUT, + + input CDRSTEPDIR, + input CDRSTEPSQ, + input CDRSTEPSX, + input CFGRESET, + input CLKRSVD0, + input CLKRSVD1, + input CPLLLOCKDETCLK, + input CPLLLOCKEN, + input CPLLPD, + input [2:0] CPLLREFCLKSEL, + input CPLLRESET, + input DMONFIFORESET, + input DMONITORCLK, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input ELPCALDVORWREN, + input ELPCALPAORWREN, + input EVODDPHICALDONE, + input EVODDPHICALSTART, + input EVODDPHIDRDEN, + input EVODDPHIDWREN, + input EVODDPHIXRDEN, + input EVODDPHIXWREN, + input EYESCANMODE, + input EYESCANRESET, + input EYESCANTRIGGER, + input GTGREFCLK, + input GTNORTHREFCLK0, + input GTNORTHREFCLK1, + input GTREFCLK0, + input GTREFCLK1, + input GTRESETSEL, + input [15:0] GTRSVD, + input GTRXRESET, + input GTSOUTHREFCLK0, + input GTSOUTHREFCLK1, + input GTTXRESET, + input GTYRXN, + input GTYRXP, + input [2:0] LOOPBACK, + input [15:0] LOOPRSVD, + input LPBKRXTXSEREN, + input LPBKTXRXSEREN, + input PCIEEQRXEQADAPTDONE, + input PCIERSTIDLE, + input PCIERSTTXSYNCSTART, + input PCIEUSERRATEDONE, + input [15:0] PCSRSVDIN, + input [4:0] PCSRSVDIN2, + input [4:0] PMARSVDIN, + input QPLL0CLK, + input QPLL0REFCLK, + input QPLL1CLK, + input QPLL1REFCLK, + input RESETOVRD, + input RSTCLKENTX, + input RX8B10BEN, + input RXBUFRESET, + input RXCDRFREQRESET, + input RXCDRHOLD, + input RXCDROVRDEN, + input RXCDRRESET, + input RXCDRRESETRSV, + input RXCHBONDEN, + input [4:0] RXCHBONDI, + input [2:0] RXCHBONDLEVEL, + input RXCHBONDMASTER, + input RXCHBONDSLAVE, + input RXCKCALRESET, + input RXCOMMADETEN, + input RXDCCFORCESTART, + input RXDFEAGCHOLD, + input RXDFEAGCOVRDEN, + input RXDFELFHOLD, + input RXDFELFOVRDEN, + input RXDFELPMRESET, + input RXDFETAP10HOLD, + input RXDFETAP10OVRDEN, + input RXDFETAP11HOLD, + input RXDFETAP11OVRDEN, + input RXDFETAP12HOLD, + input RXDFETAP12OVRDEN, + input RXDFETAP13HOLD, + input RXDFETAP13OVRDEN, + input RXDFETAP14HOLD, + input RXDFETAP14OVRDEN, + input RXDFETAP15HOLD, + input RXDFETAP15OVRDEN, + input RXDFETAP2HOLD, + input RXDFETAP2OVRDEN, + input RXDFETAP3HOLD, + input RXDFETAP3OVRDEN, + input RXDFETAP4HOLD, + input RXDFETAP4OVRDEN, + input RXDFETAP5HOLD, + input RXDFETAP5OVRDEN, + input RXDFETAP6HOLD, + input RXDFETAP6OVRDEN, + input RXDFETAP7HOLD, + input RXDFETAP7OVRDEN, + input RXDFETAP8HOLD, + input RXDFETAP8OVRDEN, + input RXDFETAP9HOLD, + input RXDFETAP9OVRDEN, + input RXDFEUTHOLD, + input RXDFEUTOVRDEN, + input RXDFEVPHOLD, + input RXDFEVPOVRDEN, + input RXDFEVSEN, + input RXDFEXYDEN, + input RXDLYBYPASS, + input RXDLYEN, + input RXDLYOVRDEN, + input RXDLYSRESET, + input [1:0] RXELECIDLEMODE, + input RXGEARBOXSLIP, + input RXLATCLK, + input RXLPMEN, + input RXLPMGCHOLD, + input RXLPMGCOVRDEN, + input RXLPMHFHOLD, + input RXLPMHFOVRDEN, + input RXLPMLFHOLD, + input RXLPMLFKLOVRDEN, + input RXLPMOSHOLD, + input RXLPMOSOVRDEN, + input RXMCOMMAALIGNEN, + input [1:0] RXMONITORSEL, + input RXOOBRESET, + input RXOSCALRESET, + input RXOSHOLD, + input [3:0] RXOSINTCFG, + input RXOSINTEN, + input RXOSINTHOLD, + input RXOSINTOVRDEN, + input RXOSINTSTROBE, + input RXOSINTTESTOVRDEN, + input RXOSOVRDEN, + input [2:0] RXOUTCLKSEL, + input RXPCOMMAALIGNEN, + input RXPCSRESET, + input [1:0] RXPD, + input RXPHALIGN, + input RXPHALIGNEN, + input RXPHDLYPD, + input RXPHDLYRESET, + input RXPHOVRDEN, + input [1:0] RXPLLCLKSEL, + input RXPMARESET, + input RXPOLARITY, + input RXPRBSCNTRESET, + input [3:0] RXPRBSSEL, + input RXPROGDIVRESET, + input [2:0] RXRATE, + input RXRATEMODE, + input RXSLIDE, + input RXSLIPOUTCLK, + input RXSLIPPMA, + input RXSYNCALLIN, + input RXSYNCIN, + input RXSYNCMODE, + input [1:0] RXSYSCLKSEL, + input RXUSERRDY, + input RXUSRCLK, + input RXUSRCLK2, + input SIGVALIDCLK, + input [19:0] TSTIN, + input [7:0] TX8B10BBYPASS, + input TX8B10BEN, + input [2:0] TXBUFDIFFCTRL, + input TXCOMINIT, + input TXCOMSAS, + input TXCOMWAKE, + input [15:0] TXCTRL0, + input [15:0] TXCTRL1, + input [7:0] TXCTRL2, + input [127:0] TXDATA, + input [7:0] TXDATAEXTENDRSVD, + input TXDCCFORCESTART, + input TXDCCRESET, + input TXDEEMPH, + input TXDETECTRX, + input [4:0] TXDIFFCTRL, + input TXDIFFPD, + input TXDLYBYPASS, + input TXDLYEN, + input TXDLYHOLD, + input TXDLYOVRDEN, + input TXDLYSRESET, + input TXDLYUPDOWN, + input TXELECIDLE, + input TXELFORCESTART, + input [5:0] TXHEADER, + input TXINHIBIT, + input TXLATCLK, + input [6:0] TXMAINCURSOR, + input [2:0] TXMARGIN, + input [2:0] TXOUTCLKSEL, + input TXPCSRESET, + input [1:0] TXPD, + input TXPDELECIDLEMODE, + input TXPHALIGN, + input TXPHALIGNEN, + input TXPHDLYPD, + input TXPHDLYRESET, + input TXPHDLYTSTCLK, + input TXPHINIT, + input TXPHOVRDEN, + input TXPIPPMEN, + input TXPIPPMOVRDEN, + input TXPIPPMPD, + input TXPIPPMSEL, + input [4:0] TXPIPPMSTEPSIZE, + input TXPISOPD, + input [1:0] TXPLLCLKSEL, + input TXPMARESET, + input TXPOLARITY, + input [4:0] TXPOSTCURSOR, + input TXPRBSFORCEERR, + input [3:0] TXPRBSSEL, + input [4:0] TXPRECURSOR, + input TXPROGDIVRESET, + input [2:0] TXRATE, + input TXRATEMODE, + input [6:0] TXSEQUENCE, + input TXSWING, + input TXSYNCALLIN, + input TXSYNCIN, + input TXSYNCMODE, + input [1:0] TXSYSCLKSEL, + input TXUSERRDY, + input TXUSRCLK, + input TXUSRCLK2 +); + +// define constants + localparam MODULE_NAME = "GTYE3_CHANNEL"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "GTYE3_CHANNEL_dr.v" +`else + localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE; + localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE; + localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET; + localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0; + localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1; + localparam [15:0] ADAPT_CFG2_REG = ADAPT_CFG2; + localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE; + localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE; + localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD; + localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET; + localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE; + localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET; + localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE; + localparam [0:0] AUTO_BW_SEL_BYPASS_REG = AUTO_BW_SEL_BYPASS; + localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET; + localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET; + localparam [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL; + localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET; + localparam [0:0] CAPBYPASS_FORCE_REG = CAPBYPASS_FORCE; + localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL; + localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN; + localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN; + localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW; + localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1; + localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2; + localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3; + localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4; + localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE; + localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1; + localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2; + localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3; + localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4; + localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE; + localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE; + localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN; + localparam [15:0] CH_HSPMUX_REG = CH_HSPMUX; + localparam [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0; + localparam [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1; + localparam [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2; + localparam [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3; + localparam [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0; + localparam [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1; + localparam [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2; + localparam [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3; + localparam [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4; + localparam [15:0] CKCAL_RSVD0_REG = CKCAL_RSVD0; + localparam [15:0] CKCAL_RSVD1_REG = CKCAL_RSVD1; + localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE; + localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE; + localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT; + localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT; + localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE; + localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT; + localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1; + localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2; + localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3; + localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4; + localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE; + localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1; + localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2; + localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3; + localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4; + localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE; + localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE; + localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN; + localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0; + localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1; + localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2; + localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3; + localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV; + localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45; + localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0; + localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1; + localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG; + localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV; + localparam [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL; + localparam [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN; + localparam [1:0] DDI_CTRL_REG = DDI_CTRL; + localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT; + localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT; + localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT; + localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY; + localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS; + localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN; + localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0; + localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1; + localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL; + localparam [5:0] ES_CONTROL_REG = ES_CONTROL; + localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN; + localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN; + localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET; + localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG; + localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE; + localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0; + localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1; + localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2; + localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3; + localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4; + localparam [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5; + localparam [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6; + localparam [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7; + localparam [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8; + localparam [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9; + localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0; + localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1; + localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2; + localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3; + localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4; + localparam [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5; + localparam [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6; + localparam [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7; + localparam [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8; + localparam [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9; + localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0; + localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1; + localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2; + localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3; + localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4; + localparam [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5; + localparam [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6; + localparam [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7; + localparam [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8; + localparam [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9; + localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG; + localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN; + localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE; + localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG; + localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN; + localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE; + localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT; + localparam [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2; + localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER; + localparam [15:0] LOOP0_CFG_REG = LOOP0_CFG; + localparam [15:0] LOOP10_CFG_REG = LOOP10_CFG; + localparam [15:0] LOOP11_CFG_REG = LOOP11_CFG; + localparam [15:0] LOOP12_CFG_REG = LOOP12_CFG; + localparam [15:0] LOOP13_CFG_REG = LOOP13_CFG; + localparam [15:0] LOOP1_CFG_REG = LOOP1_CFG; + localparam [15:0] LOOP2_CFG_REG = LOOP2_CFG; + localparam [15:0] LOOP3_CFG_REG = LOOP3_CFG; + localparam [15:0] LOOP4_CFG_REG = LOOP4_CFG; + localparam [15:0] LOOP5_CFG_REG = LOOP5_CFG; + localparam [15:0] LOOP6_CFG_REG = LOOP6_CFG; + localparam [15:0] LOOP7_CFG_REG = LOOP7_CFG; + localparam [15:0] LOOP8_CFG_REG = LOOP8_CFG; + localparam [15:0] LOOP9_CFG_REG = LOOP9_CFG; + localparam [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL; + localparam [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B; + localparam [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL; + localparam [3:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL; + localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL; + localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP; + localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN; + localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE; + localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS; + localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE; + localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT; + localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE; + localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT; + localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE; + localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE; + localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL; + localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3; + localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG; + localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3; + localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG; + localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN; + localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0; + localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1; + localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2; + localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2; + localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2; + localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12; + localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3; + localparam [15:0] PMA_RSV0_REG = PMA_RSV0; + localparam [15:0] PMA_RSV1_REG = PMA_RSV1; + localparam [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST; + localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR; + localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP; + localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE; + localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME; + localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE; + localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT; + localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT; + localparam [40:1] RXBUF_EN_REG = RXBUF_EN; + localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE; + localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN; + localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE; + localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE; + localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW; + localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD; + localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW; + localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME; + localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME; + localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0; + localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3; + localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1; + localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3; + localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2; + localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3; + localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3; + localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3; + localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4; + localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3; + localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5; + localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3; + localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE; + localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE; + localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0; + localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1; + localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2; + localparam [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3; + localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE; + localparam [1:0] RXCFOKDONE_SRC_REG = RXCFOKDONE_SRC; + localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0; + localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1; + localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2; + localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME; + localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0; + localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1; + localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2; + localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0; + localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1; + localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0; + localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1; + localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2; + localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0; + localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1; + localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0; + localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1; + localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0; + localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1; + localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0; + localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1; + localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0; + localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1; + localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0; + localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1; + localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0; + localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1; + localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0; + localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1; + localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0; + localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1; + localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0; + localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1; + localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0; + localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1; + localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0; + localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1; + localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0; + localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1; + localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0; + localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1; + localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0; + localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1; + localparam [0:0] RXDFE_PWR_SAVING_REG = RXDFE_PWR_SAVING; + localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0; + localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1; + localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0; + localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1; + localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG; + localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG; + localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG; + localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR; + localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN; + localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME; + localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG; + localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG; + localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0; + localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1; + localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0; + localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1; + localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG; + localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG; + localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME; + localparam [5:0] RXOUT_DIV_REG = RXOUT_DIV; + localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME; + localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG; + localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG; + localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG; + localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG; + localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL; + localparam [0:0] RXPI_AUTO_BW_SEL_BYPASS_REG = RXPI_AUTO_BW_SEL_BYPASS; + localparam [15:0] RXPI_CFG_REG = RXPI_CFG; + localparam [0:0] RXPI_LPM_REG = RXPI_LPM; + localparam [15:0] RXPI_RSV0_REG = RXPI_RSV0; + localparam [1:0] RXPI_SEL_LC_REG = RXPI_SEL_LC; + localparam [1:0] RXPI_STARTCODE_REG = RXPI_STARTCODE; + localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL; + localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL; + localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME; + localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK; + localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT; + localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT; + localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE; + localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE; + localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD; + localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA; + localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN; + localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0; + localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG; + localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB; + localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV; + localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN; + localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD; + localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG; + localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD; + localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL; + localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM; + localparam [0:0] RX_CTLE1_KHKL_REG = RX_CTLE1_KHKL; + localparam [0:0] RX_CTLE2_KHKL_REG = RX_CTLE2_KHKL; + localparam [0:0] RX_CTLE3_AGC_REG = RX_CTLE3_AGC; + localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH; + localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL; + localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN; + localparam [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL; + localparam [2:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0; + localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1; + localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN; + localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0; + localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1; + localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0; + localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1; + localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0; + localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1; + localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE; + localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH; + localparam [0:0] RX_DIV2_MODE_B_REG = RX_DIV2_MODE_B; + localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME; + localparam [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B; + localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR; + localparam [8:0] RX_EXT_RL_CTRL_REG = RX_EXT_RL_CTRL; + localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE; + localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR; + localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE; + localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN; + localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP; + localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH; + localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE; + localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG; + localparam [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE; + localparam [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL; + localparam [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD; + localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD; + localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY; + localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN; + localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE; + localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE; + localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR; + localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE; + localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS; + localparam [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL; + localparam [0:0] RX_VREG_PDB_REG = RX_VREG_PDB; + localparam [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR; + localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL; + localparam [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL; + localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM; + localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM; + localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN; + localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL; + localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG; + localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL; + localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST; + localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT; + localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE; + localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST; + localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT; + localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE; + localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA; +// localparam [80:1] SIM_MODE_REG = SIM_MODE; +// localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS; +// localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; +// localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL; +// localparam [1:0] SIM_VERSION_REG = SIM_VERSION; + localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX; + localparam [3:0] TEMPERATURE_PAR_REG = TEMPERATURE_PAR; + localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG; + localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD; + localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE; + localparam [7:0] TST_RSV0_REG = TST_RSV0; + localparam [7:0] TST_RSV1_REG = TST_RSV1; + localparam [40:1] TXBUF_EN_REG = TXBUF_EN; + localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE; + localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG; + localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG; + localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG; + localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR; + localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN; + localparam [5:0] TXOUT_DIV_REG = TXOUT_DIV; + localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME; + localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0; + localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1; + localparam [15:0] TXPH_CFG_REG = TXPH_CFG; + localparam [15:0] TXPH_CFG2_REG = TXPH_CFG2; + localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL; + localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0; + localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1; + localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2; + localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3; + localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4; + localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5; + localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL; + localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL; + localparam [0:0] TXPI_LPM_REG = TXPI_LPM; + localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL; + localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG; + localparam [15:0] TXPI_RSV0_REG = TXPI_RSV0; + localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM; + localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL; + localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME; + localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE; + localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD; + localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA; + localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV; + localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN; + localparam [0:0] TX_CLKREG_PDB_REG = TX_CLKREG_PDB; + localparam [2:0] TX_CLKREG_SET_REG = TX_CLKREG_SET; + localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH; + localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG; + localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN; + localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0; + localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1; + localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME; + localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE; + localparam [1:0] TX_DRVMUX_CTRL_REG = TX_DRVMUX_CTRL; + localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY; + localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY; + localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE; + localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP; + localparam [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN; + localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO; + localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH; + localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ; + localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL; + localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0; + localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1; + localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2; + localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3; + localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4; + localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0; + localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1; + localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2; + localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3; + localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4; + localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL; + localparam [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0; + localparam [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1; + localparam [15:0] TX_PHICAL_CFG2_REG = TX_PHICAL_CFG2; + localparam [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET; + localparam [15:0] TX_PI_CFG0_REG = TX_PI_CFG0; + localparam [15:0] TX_PI_CFG1_REG = TX_PI_CFG1; + localparam [0:0] TX_PI_DIV2_MODE_B_REG = TX_PI_DIV2_MODE_B; + localparam [0:0] TX_PI_SEL_QPLL0_REG = TX_PI_SEL_QPLL0; + localparam [0:0] TX_PI_SEL_QPLL1_REG = TX_PI_SEL_QPLL1; + localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT; + localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE; + localparam [1:0] TX_PREDRV_CTRL_REG = TX_PREDRV_CTRL; + localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL; + localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG; + localparam [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE; + localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG; + localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF; + localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD; + localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB; + localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL; + localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL; +`endif + + localparam [0:0] AEN_CDRSTEPSEL_REG = 1'b0; + localparam [0:0] AEN_CPLL_REG = 1'b0; + localparam [0:0] AEN_ELPCAL_REG = 1'b0; + localparam [0:0] AEN_EYESCAN_REG = 1'b1; + localparam [0:0] AEN_LOOPBACK_REG = 1'b0; + localparam [0:0] AEN_MASTER_REG = 1'b0; + localparam [0:0] AEN_MUXDCD_REG = 1'b0; + localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0; + localparam [0:0] AEN_POLARITY_REG = 1'b0; + localparam [0:0] AEN_PRBS_REG = 1'b0; + localparam [0:0] AEN_RESET_REG = 1'b0; + localparam [0:0] AEN_RXCDR_REG = 1'b0; + localparam [0:0] AEN_RXDFE_REG = 1'b0; + localparam [0:0] AEN_RXDFELPM_REG = 1'b0; + localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_RXPHDLY_REG = 1'b0; + localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXPHDLY_REG = 1'b0; + localparam [0:0] AEN_TXPI_PPM_REG = 1'b0; + localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0; + localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0; + localparam [15:0] AMONITOR_CFG_REG = 16'h0000; + localparam [0:0] A_AFECFOKEN_REG = 1'b0; + localparam [0:0] A_CPLLLOCKEN_REG = 1'b0; + localparam [0:0] A_CPLLPD_REG = 1'b0; + localparam [0:0] A_CPLLRESET_REG = 1'b0; + localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000; + localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000; + localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0; + localparam [0:0] A_DFECFOKHOLD_REG = 1'b0; + localparam [0:0] A_DFECFOKOVREN_REG = 1'b0; + localparam [0:0] A_ELPCALDVORWREN_REG = 1'b0; + localparam [0:0] A_ELPCALPAORWREN_REG = 1'b0; + localparam [0:0] A_EYESCANMODE_REG = 1'b0; + localparam [0:0] A_EYESCANRESET_REG = 1'b0; + localparam [0:0] A_GTRESETSEL_REG = 1'b0; + localparam [0:0] A_GTRXRESET_REG = 1'b0; + localparam [0:0] A_GTTXRESET_REG = 1'b0; + localparam [80:1] A_LOOPBACK_REG = "NoLoopBack"; + localparam [0:0] A_LPMGCHOLD_REG = 1'b0; + localparam [0:0] A_LPMGCOVREN_REG = 1'b0; + localparam [0:0] A_LPMOSHOLD_REG = 1'b0; + localparam [0:0] A_LPMOSOVREN_REG = 1'b0; + localparam [0:0] A_MUXDCDEXHOLD_REG = 1'b0; + localparam [0:0] A_MUXDCDORWREN_REG = 1'b0; + localparam [0:0] A_RXBUFRESET_REG = 1'b0; + localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0; + localparam [0:0] A_RXCDRHOLD_REG = 1'b0; + localparam [0:0] A_RXCDROVRDEN_REG = 1'b0; + localparam [0:0] A_RXCDRRESET_REG = 1'b0; + localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0; + localparam [0:0] A_RXDFELFHOLD_REG = 1'b0; + localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFELPMRESET_REG = 1'b0; + localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP12HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP13HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP14HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP15HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0; + localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0; + localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDFEVSEN_REG = 1'b0; + localparam [0:0] A_RXDFEXYDEN_REG = 1'b0; + localparam [0:0] A_RXDLYBYPASS_REG = 1'b0; + localparam [0:0] A_RXDLYEN_REG = 1'b0; + localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0; + localparam [0:0] A_RXDLYSRESET_REG = 1'b0; + localparam [0:0] A_RXLPMEN_REG = 1'b0; + localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0; + localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0; + localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0; + localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0; + localparam [1:0] A_RXMONITORSEL_REG = 2'b00; + localparam [0:0] A_RXOOBRESET_REG = 1'b0; + localparam [0:0] A_RXOSHOLD_REG = 1'b0; + localparam [0:0] A_RXOSOVRDEN_REG = 1'b0; + localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled"; + localparam [0:0] A_RXPCSRESET_REG = 1'b0; + localparam [24:1] A_RXPD_REG = "P0"; + localparam [0:0] A_RXPHALIGN_REG = 1'b0; + localparam [0:0] A_RXPHALIGNEN_REG = 1'b0; + localparam [0:0] A_RXPHDLYPD_REG = 1'b0; + localparam [0:0] A_RXPHDLYRESET_REG = 1'b0; + localparam [0:0] A_RXPHOVRDEN_REG = 1'b0; + localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK"; + localparam [0:0] A_RXPMARESET_REG = 1'b0; + localparam [0:0] A_RXPOLARITY_REG = 1'b0; + localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0; + localparam [48:1] A_RXPRBSSEL_REG = "PRBS7"; + localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK"; + localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100; + localparam [0:0] A_TXDEEMPH_REG = 1'b0; + localparam [0:0] A_TXDLYBYPASS_REG = 1'b0; + localparam [0:0] A_TXDLYEN_REG = 1'b0; + localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0; + localparam [0:0] A_TXDLYSRESET_REG = 1'b0; + localparam [0:0] A_TXELECIDLE_REG = 1'b0; + localparam [0:0] A_TXINHIBIT_REG = 1'b0; + localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000; + localparam [2:0] A_TXMARGIN_REG = 3'b000; + localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled"; + localparam [0:0] A_TXPCSRESET_REG = 1'b0; + localparam [24:1] A_TXPD_REG = "P0"; + localparam [0:0] A_TXPHALIGN_REG = 1'b0; + localparam [0:0] A_TXPHALIGNEN_REG = 1'b0; + localparam [0:0] A_TXPHDLYPD_REG = 1'b0; + localparam [0:0] A_TXPHDLYRESET_REG = 1'b0; + localparam [0:0] A_TXPHINIT_REG = 1'b0; + localparam [0:0] A_TXPHOVRDEN_REG = 1'b0; + localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0; + localparam [0:0] A_TXPIPPMPD_REG = 1'b0; + localparam [0:0] A_TXPIPPMSEL_REG = 1'b0; + localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK"; + localparam [0:0] A_TXPMARESET_REG = 1'b0; + localparam [0:0] A_TXPOLARITY_REG = 1'b0; + localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000; + localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0; + localparam [96:1] A_TXPRBSSEL_REG = "PRBS7"; + localparam [4:0] A_TXPRECURSOR_REG = 5'b00000; + localparam [0:0] A_TXSWING_REG = 1'b0; + localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK"; + localparam [40:1] GEN_RXUSRCLK_REG = "TRUE"; + localparam [40:1] GEN_TXUSRCLK_REG = "TRUE"; + localparam [0:0] GT_INSTANTIATED_REG = 1'b1; + localparam [40:1] RXPLL_SEL_REG = "CPLL"; + localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0; + localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100; + localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101; + localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011; + localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010; + localparam [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100; + localparam [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101; + localparam [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011; + localparam [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010; + + wire [63:0] RX_PROGDIV_CFG_BIN; + wire [63:0] TX_PROGDIV_CFG_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CPLLFBCLKLOST_out; + wire CPLLLOCK_out; + wire CPLLREFCLKLOST_out; + wire DRPRDY_out; + wire EYESCANDATAERROR_out; + wire GTPOWERGOOD_out; + wire GTREFCLKMONITOR_out; + wire GTYTXN_out; + wire GTYTXP_out; + wire PCIERATEGEN3_out; + wire PCIERATEIDLE_out; + wire PCIESYNCTXSYNCDONE_out; + wire PCIEUSERGEN3RDY_out; + wire PCIEUSERPHYSTATUSRST_out; + wire PCIEUSERRATESTART_out; + wire PHYSTATUS_out; + wire RESETEXCEPTION_out; + wire RXBYTEISALIGNED_out; + wire RXBYTEREALIGN_out; + wire RXCDRLOCK_out; + wire RXCDRPHDONE_out; + wire RXCHANBONDSEQ_out; + wire RXCHANISALIGNED_out; + wire RXCHANREALIGN_out; + wire RXCKCALDONE_out; + wire RXCOMINITDET_out; + wire RXCOMMADET_out; + wire RXCOMSASDET_out; + wire RXCOMWAKEDET_out; + wire RXDLYSRESETDONE_out; + wire RXELECIDLE_out; + wire RXOSINTDONE_out; + wire RXOSINTSTARTED_out; + wire RXOSINTSTROBEDONE_out; + wire RXOSINTSTROBESTARTED_out; + wire RXOUTCLKFABRIC_out; + wire RXOUTCLKPCS_out; + wire RXOUTCLK_out; + wire RXPHALIGNDONE_out; + wire RXPHALIGNERR_out; + wire RXPMARESETDONE_out; + wire RXPRBSERR_out; + wire RXPRBSLOCKED_out; + wire RXPRGDIVRESETDONE_out; + wire RXRATEDONE_out; + wire RXRECCLKOUT_out; + wire RXRESETDONE_out; + wire RXSLIDERDY_out; + wire RXSLIPDONE_out; + wire RXSLIPOUTCLKRDY_out; + wire RXSLIPPMARDY_out; + wire RXSYNCDONE_out; + wire RXSYNCOUT_out; + wire RXVALID_out; + wire TXCOMFINISH_out; + wire TXDCCDONE_out; + wire TXDLYSRESETDONE_out; + wire TXOUTCLKFABRIC_out; + wire TXOUTCLKPCS_out; + wire TXOUTCLK_out; + wire TXPHALIGNDONE_out; + wire TXPHINITDONE_out; + wire TXPMARESETDONE_out; + wire TXPRGDIVRESETDONE_out; + wire TXRATEDONE_out; + wire TXRESETDONE_out; + wire TXSYNCDONE_out; + wire TXSYNCOUT_out; + wire [11:0] PMASCANOUT_out; + wire [127:0] RXDATA_out; + wire [15:0] DRPDO_out; + wire [15:0] PCSRSVDOUT_out; + wire [15:0] RXCTRL0_out; + wire [15:0] RXCTRL1_out; + wire [16:0] DMONITOROUT_out; + wire [18:0] SCANOUT_out; + wire [1:0] PCIERATEQPLLPD_out; + wire [1:0] PCIERATEQPLLRESET_out; + wire [1:0] RXCLKCORCNT_out; + wire [1:0] RXDATAVALID_out; + wire [1:0] RXHEADERVALID_out; + wire [1:0] RXSTARTOFSEQ_out; + wire [1:0] TXBUFSTATUS_out; + wire [2:0] BUFGTCEMASK_out; + wire [2:0] BUFGTCE_out; + wire [2:0] BUFGTRESET_out; + wire [2:0] BUFGTRSTMASK_out; + wire [2:0] RXBUFSTATUS_out; + wire [2:0] RXSTATUS_out; + wire [4:0] RXCHBONDO_out; + wire [5:0] RXHEADER_out; + wire [6:0] RXMONITOROUT_out; + wire [7:0] PINRSRVDAS_out; + wire [7:0] RXCTRL2_out; + wire [7:0] RXCTRL3_out; + wire [7:0] RXDATAEXTENDRSVD_out; + wire [8:0] BUFGTDIV_out; + + wire CPLLFBCLKLOST_delay; + wire CPLLLOCK_delay; + wire CPLLREFCLKLOST_delay; + wire DRPRDY_delay; + wire EYESCANDATAERROR_delay; + wire GTPOWERGOOD_delay; + wire GTREFCLKMONITOR_delay; + wire GTYTXN_delay; + wire GTYTXP_delay; + wire PCIERATEGEN3_delay; + wire PCIERATEIDLE_delay; + wire PCIESYNCTXSYNCDONE_delay; + wire PCIEUSERGEN3RDY_delay; + wire PCIEUSERPHYSTATUSRST_delay; + wire PCIEUSERRATESTART_delay; + wire PHYSTATUS_delay; + wire RESETEXCEPTION_delay; + wire RXBYTEISALIGNED_delay; + wire RXBYTEREALIGN_delay; + wire RXCDRLOCK_delay; + wire RXCDRPHDONE_delay; + wire RXCHANBONDSEQ_delay; + wire RXCHANISALIGNED_delay; + wire RXCHANREALIGN_delay; + wire RXCKCALDONE_delay; + wire RXCOMINITDET_delay; + wire RXCOMMADET_delay; + wire RXCOMSASDET_delay; + wire RXCOMWAKEDET_delay; + wire RXDLYSRESETDONE_delay; + wire RXELECIDLE_delay; + wire RXOSINTDONE_delay; + wire RXOSINTSTARTED_delay; + wire RXOSINTSTROBEDONE_delay; + wire RXOSINTSTROBESTARTED_delay; + wire RXOUTCLKFABRIC_delay; + wire RXOUTCLKPCS_delay; + wire RXOUTCLK_delay; + wire RXPHALIGNDONE_delay; + wire RXPHALIGNERR_delay; + wire RXPMARESETDONE_delay; + wire RXPRBSERR_delay; + wire RXPRBSLOCKED_delay; + wire RXPRGDIVRESETDONE_delay; + wire RXRATEDONE_delay; + wire RXRECCLKOUT_delay; + wire RXRESETDONE_delay; + wire RXSLIDERDY_delay; + wire RXSLIPDONE_delay; + wire RXSLIPOUTCLKRDY_delay; + wire RXSLIPPMARDY_delay; + wire RXSYNCDONE_delay; + wire RXSYNCOUT_delay; + wire RXVALID_delay; + wire TXCOMFINISH_delay; + wire TXDCCDONE_delay; + wire TXDLYSRESETDONE_delay; + wire TXOUTCLKFABRIC_delay; + wire TXOUTCLKPCS_delay; + wire TXOUTCLK_delay; + wire TXPHALIGNDONE_delay; + wire TXPHINITDONE_delay; + wire TXPMARESETDONE_delay; + wire TXPRGDIVRESETDONE_delay; + wire TXRATEDONE_delay; + wire TXRESETDONE_delay; + wire TXSYNCDONE_delay; + wire TXSYNCOUT_delay; + wire [127:0] RXDATA_delay; + wire [15:0] DRPDO_delay; + wire [15:0] PCSRSVDOUT_delay; + wire [15:0] RXCTRL0_delay; + wire [15:0] RXCTRL1_delay; + wire [16:0] DMONITOROUT_delay; + wire [1:0] PCIERATEQPLLPD_delay; + wire [1:0] PCIERATEQPLLRESET_delay; + wire [1:0] RXCLKCORCNT_delay; + wire [1:0] RXDATAVALID_delay; + wire [1:0] RXHEADERVALID_delay; + wire [1:0] RXSTARTOFSEQ_delay; + wire [1:0] TXBUFSTATUS_delay; + wire [2:0] BUFGTCEMASK_delay; + wire [2:0] BUFGTCE_delay; + wire [2:0] BUFGTRESET_delay; + wire [2:0] BUFGTRSTMASK_delay; + wire [2:0] RXBUFSTATUS_delay; + wire [2:0] RXSTATUS_delay; + wire [4:0] RXCHBONDO_delay; + wire [5:0] RXHEADER_delay; + wire [6:0] RXMONITOROUT_delay; + wire [7:0] PINRSRVDAS_delay; + wire [7:0] RXCTRL2_delay; + wire [7:0] RXCTRL3_delay; + wire [7:0] RXDATAEXTENDRSVD_delay; + wire [8:0] BUFGTDIV_delay; + + wire CDRSTEPDIR_in; + wire CDRSTEPSQ_in; + wire CDRSTEPSX_in; + wire CFGRESET_in; + wire CLKRSVD0_in; + wire CLKRSVD1_in; + wire CPLLLOCKDETCLK_in; + wire CPLLLOCKEN_in; + wire CPLLPD_in; + wire CPLLRESET_in; + wire DMONFIFORESET_in; + wire DMONITORCLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire ELPCALDVORWREN_in; + wire ELPCALPAORWREN_in; + wire EVODDPHICALDONE_in; + wire EVODDPHICALSTART_in; + wire EVODDPHIDRDEN_in; + wire EVODDPHIDWREN_in; + wire EVODDPHIXRDEN_in; + wire EVODDPHIXWREN_in; + wire EYESCANMODE_in; + wire EYESCANRESET_in; + wire EYESCANTRIGGER_in; + wire GTGREFCLK_in; + wire GTNORTHREFCLK0_in; + wire GTNORTHREFCLK1_in; + wire GTREFCLK0_in; + wire GTREFCLK1_in; + wire GTRESETSEL_in; + wire GTRXRESET_in; + wire GTSOUTHREFCLK0_in; + wire GTSOUTHREFCLK1_in; + wire GTTXRESET_in; + wire GTYRXN_in; + wire GTYRXP_in; + wire LPBKRXTXSEREN_in; + wire LPBKTXRXSEREN_in; + wire PCIEEQRXEQADAPTDONE_in; + wire PCIERSTIDLE_in; + wire PCIERSTTXSYNCSTART_in; + wire PCIEUSERRATEDONE_in; + wire PMASCANCLK0_in; + wire PMASCANCLK1_in; + wire PMASCANCLK2_in; + wire PMASCANCLK3_in; + wire PMASCANCLK4_in; + wire PMASCANCLK5_in; + wire PMASCANENB_in; + wire PMASCANMODEB_in; + wire PMASCANRSTEN_in; + wire QPLL0CLK_in; + wire QPLL0REFCLK_in; + wire QPLL1CLK_in; + wire QPLL1REFCLK_in; + wire RESETOVRD_in; + wire RSTCLKENTX_in; + wire RX8B10BEN_in; + wire RXBUFRESET_in; + wire RXCDRFREQRESET_in; + wire RXCDRHOLD_in; + wire RXCDROVRDEN_in; + wire RXCDRRESETRSV_in; + wire RXCDRRESET_in; + wire RXCHBONDEN_in; + wire RXCHBONDMASTER_in; + wire RXCHBONDSLAVE_in; + wire RXCKCALRESET_in; + wire RXCOMMADETEN_in; + wire RXDCCFORCESTART_in; + wire RXDFEAGCHOLD_in; + wire RXDFEAGCOVRDEN_in; + wire RXDFELFHOLD_in; + wire RXDFELFOVRDEN_in; + wire RXDFELPMRESET_in; + wire RXDFETAP10HOLD_in; + wire RXDFETAP10OVRDEN_in; + wire RXDFETAP11HOLD_in; + wire RXDFETAP11OVRDEN_in; + wire RXDFETAP12HOLD_in; + wire RXDFETAP12OVRDEN_in; + wire RXDFETAP13HOLD_in; + wire RXDFETAP13OVRDEN_in; + wire RXDFETAP14HOLD_in; + wire RXDFETAP14OVRDEN_in; + wire RXDFETAP15HOLD_in; + wire RXDFETAP15OVRDEN_in; + wire RXDFETAP2HOLD_in; + wire RXDFETAP2OVRDEN_in; + wire RXDFETAP3HOLD_in; + wire RXDFETAP3OVRDEN_in; + wire RXDFETAP4HOLD_in; + wire RXDFETAP4OVRDEN_in; + wire RXDFETAP5HOLD_in; + wire RXDFETAP5OVRDEN_in; + wire RXDFETAP6HOLD_in; + wire RXDFETAP6OVRDEN_in; + wire RXDFETAP7HOLD_in; + wire RXDFETAP7OVRDEN_in; + wire RXDFETAP8HOLD_in; + wire RXDFETAP8OVRDEN_in; + wire RXDFETAP9HOLD_in; + wire RXDFETAP9OVRDEN_in; + wire RXDFEUTHOLD_in; + wire RXDFEUTOVRDEN_in; + wire RXDFEVPHOLD_in; + wire RXDFEVPOVRDEN_in; + wire RXDFEVSEN_in; + wire RXDFEXYDEN_in; + wire RXDLYBYPASS_in; + wire RXDLYEN_in; + wire RXDLYOVRDEN_in; + wire RXDLYSRESET_in; + wire RXGEARBOXSLIP_in; + wire RXLATCLK_in; + wire RXLPMEN_in; + wire RXLPMGCHOLD_in; + wire RXLPMGCOVRDEN_in; + wire RXLPMHFHOLD_in; + wire RXLPMHFOVRDEN_in; + wire RXLPMLFHOLD_in; + wire RXLPMLFKLOVRDEN_in; + wire RXLPMOSHOLD_in; + wire RXLPMOSOVRDEN_in; + wire RXMCOMMAALIGNEN_in; + wire RXOOBRESET_in; + wire RXOSCALRESET_in; + wire RXOSHOLD_in; + wire RXOSINTEN_in; + wire RXOSINTHOLD_in; + wire RXOSINTOVRDEN_in; + wire RXOSINTSTROBE_in; + wire RXOSINTTESTOVRDEN_in; + wire RXOSOVRDEN_in; + wire RXPCOMMAALIGNEN_in; + wire RXPCSRESET_in; + wire RXPHALIGNEN_in; + wire RXPHALIGN_in; + wire RXPHDLYPD_in; + wire RXPHDLYRESET_in; + wire RXPHOVRDEN_in; + wire RXPMARESET_in; + wire RXPOLARITY_in; + wire RXPRBSCNTRESET_in; + wire RXPROGDIVRESET_in; + wire RXRATEMODE_in; + wire RXSLIDE_in; + wire RXSLIPOUTCLK_in; + wire RXSLIPPMA_in; + wire RXSYNCALLIN_in; + wire RXSYNCIN_in; + wire RXSYNCMODE_in; + wire RXUSERRDY_in; + wire RXUSRCLK2_in; + wire RXUSRCLK_in; + wire SARCCLK_in; + wire SCANCLK_in; + wire SCANENB_in; + wire SCANMODEB_in; + wire SIGVALIDCLK_in; + wire TSTCLK0_in; + wire TSTCLK1_in; + wire TSTPDOVRDB_in; + wire TX8B10BEN_in; + wire TXCOMINIT_in; + wire TXCOMSAS_in; + wire TXCOMWAKE_in; + wire TXDCCFORCESTART_in; + wire TXDCCRESET_in; + wire TXDEEMPH_in; + wire TXDETECTRX_in; + wire TXDIFFPD_in; + wire TXDLYBYPASS_in; + wire TXDLYEN_in; + wire TXDLYHOLD_in; + wire TXDLYOVRDEN_in; + wire TXDLYSRESET_in; + wire TXDLYUPDOWN_in; + wire TXELECIDLE_in; + wire TXELFORCESTART_in; + wire TXINHIBIT_in; + wire TXLATCLK_in; + wire TXPCSRESET_in; + wire TXPDELECIDLEMODE_in; + wire TXPHALIGNEN_in; + wire TXPHALIGN_in; + wire TXPHDLYPD_in; + wire TXPHDLYRESET_in; + wire TXPHDLYTSTCLK_in; + wire TXPHINIT_in; + wire TXPHOVRDEN_in; + wire TXPIPPMEN_in; + wire TXPIPPMOVRDEN_in; + wire TXPIPPMPD_in; + wire TXPIPPMSEL_in; + wire TXPISOPD_in; + wire TXPMARESET_in; + wire TXPOLARITY_in; + wire TXPRBSFORCEERR_in; + wire TXPROGDIVRESET_in; + wire TXRATEMODE_in; + wire TXSWING_in; + wire TXSYNCALLIN_in; + wire TXSYNCIN_in; + wire TXSYNCMODE_in; + wire TXUSERRDY_in; + wire TXUSRCLK2_in; + wire TXUSRCLK_in; + wire [11:0] PMASCANIN_in; + wire [127:0] TXDATA_in; + wire [15:0] DRPDI_in; + wire [15:0] GTRSVD_in; + wire [15:0] LOOPRSVD_in; + wire [15:0] PCSRSVDIN_in; + wire [15:0] TXCTRL0_in; + wire [15:0] TXCTRL1_in; + wire [18:0] SCANIN_in; + wire [19:0] TSTIN_in; + wire [1:0] RXELECIDLEMODE_in; + wire [1:0] RXMONITORSEL_in; + wire [1:0] RXPD_in; + wire [1:0] RXPLLCLKSEL_in; + wire [1:0] RXSYSCLKSEL_in; + wire [1:0] TXPD_in; + wire [1:0] TXPLLCLKSEL_in; + wire [1:0] TXSYSCLKSEL_in; + wire [2:0] CPLLREFCLKSEL_in; + wire [2:0] LOOPBACK_in; + wire [2:0] RXCHBONDLEVEL_in; + wire [2:0] RXOUTCLKSEL_in; + wire [2:0] RXRATE_in; + wire [2:0] TXBUFDIFFCTRL_in; + wire [2:0] TXMARGIN_in; + wire [2:0] TXOUTCLKSEL_in; + wire [2:0] TXRATE_in; + wire [3:0] RXOSINTCFG_in; + wire [3:0] RXPRBSSEL_in; + wire [3:0] TXPRBSSEL_in; + wire [4:0] PCSRSVDIN2_in; + wire [4:0] PMARSVDIN_in; + wire [4:0] RXCHBONDI_in; + wire [4:0] TSTPD_in; + wire [4:0] TXDIFFCTRL_in; + wire [4:0] TXPIPPMSTEPSIZE_in; + wire [4:0] TXPOSTCURSOR_in; + wire [4:0] TXPRECURSOR_in; + wire [5:0] TXHEADER_in; + wire [6:0] TXMAINCURSOR_in; + wire [6:0] TXSEQUENCE_in; + wire [7:0] TX8B10BBYPASS_in; + wire [7:0] TXCTRL2_in; + wire [7:0] TXDATAEXTENDRSVD_in; + wire [9:0] DRPADDR_in; + + wire CDRSTEPDIR_delay; + wire CDRSTEPSQ_delay; + wire CDRSTEPSX_delay; + wire CFGRESET_delay; + wire CLKRSVD0_delay; + wire CLKRSVD1_delay; + wire CPLLLOCKDETCLK_delay; + wire CPLLLOCKEN_delay; + wire CPLLPD_delay; + wire CPLLRESET_delay; + wire DMONFIFORESET_delay; + wire DMONITORCLK_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire ELPCALDVORWREN_delay; + wire ELPCALPAORWREN_delay; + wire EVODDPHICALDONE_delay; + wire EVODDPHICALSTART_delay; + wire EVODDPHIDRDEN_delay; + wire EVODDPHIDWREN_delay; + wire EVODDPHIXRDEN_delay; + wire EVODDPHIXWREN_delay; + wire EYESCANMODE_delay; + wire EYESCANRESET_delay; + wire EYESCANTRIGGER_delay; + wire GTGREFCLK_delay; + wire GTNORTHREFCLK0_delay; + wire GTNORTHREFCLK1_delay; + wire GTREFCLK0_delay; + wire GTREFCLK1_delay; + wire GTRESETSEL_delay; + wire GTRXRESET_delay; + wire GTSOUTHREFCLK0_delay; + wire GTSOUTHREFCLK1_delay; + wire GTTXRESET_delay; + wire GTYRXN_delay; + wire GTYRXP_delay; + wire LPBKRXTXSEREN_delay; + wire LPBKTXRXSEREN_delay; + wire PCIEEQRXEQADAPTDONE_delay; + wire PCIERSTIDLE_delay; + wire PCIERSTTXSYNCSTART_delay; + wire PCIEUSERRATEDONE_delay; + wire QPLL0CLK_delay; + wire QPLL0REFCLK_delay; + wire QPLL1CLK_delay; + wire QPLL1REFCLK_delay; + wire RESETOVRD_delay; + wire RSTCLKENTX_delay; + wire RX8B10BEN_delay; + wire RXBUFRESET_delay; + wire RXCDRFREQRESET_delay; + wire RXCDRHOLD_delay; + wire RXCDROVRDEN_delay; + wire RXCDRRESETRSV_delay; + wire RXCDRRESET_delay; + wire RXCHBONDEN_delay; + wire RXCHBONDMASTER_delay; + wire RXCHBONDSLAVE_delay; + wire RXCKCALRESET_delay; + wire RXCOMMADETEN_delay; + wire RXDCCFORCESTART_delay; + wire RXDFEAGCHOLD_delay; + wire RXDFEAGCOVRDEN_delay; + wire RXDFELFHOLD_delay; + wire RXDFELFOVRDEN_delay; + wire RXDFELPMRESET_delay; + wire RXDFETAP10HOLD_delay; + wire RXDFETAP10OVRDEN_delay; + wire RXDFETAP11HOLD_delay; + wire RXDFETAP11OVRDEN_delay; + wire RXDFETAP12HOLD_delay; + wire RXDFETAP12OVRDEN_delay; + wire RXDFETAP13HOLD_delay; + wire RXDFETAP13OVRDEN_delay; + wire RXDFETAP14HOLD_delay; + wire RXDFETAP14OVRDEN_delay; + wire RXDFETAP15HOLD_delay; + wire RXDFETAP15OVRDEN_delay; + wire RXDFETAP2HOLD_delay; + wire RXDFETAP2OVRDEN_delay; + wire RXDFETAP3HOLD_delay; + wire RXDFETAP3OVRDEN_delay; + wire RXDFETAP4HOLD_delay; + wire RXDFETAP4OVRDEN_delay; + wire RXDFETAP5HOLD_delay; + wire RXDFETAP5OVRDEN_delay; + wire RXDFETAP6HOLD_delay; + wire RXDFETAP6OVRDEN_delay; + wire RXDFETAP7HOLD_delay; + wire RXDFETAP7OVRDEN_delay; + wire RXDFETAP8HOLD_delay; + wire RXDFETAP8OVRDEN_delay; + wire RXDFETAP9HOLD_delay; + wire RXDFETAP9OVRDEN_delay; + wire RXDFEUTHOLD_delay; + wire RXDFEUTOVRDEN_delay; + wire RXDFEVPHOLD_delay; + wire RXDFEVPOVRDEN_delay; + wire RXDFEVSEN_delay; + wire RXDFEXYDEN_delay; + wire RXDLYBYPASS_delay; + wire RXDLYEN_delay; + wire RXDLYOVRDEN_delay; + wire RXDLYSRESET_delay; + wire RXGEARBOXSLIP_delay; + wire RXLATCLK_delay; + wire RXLPMEN_delay; + wire RXLPMGCHOLD_delay; + wire RXLPMGCOVRDEN_delay; + wire RXLPMHFHOLD_delay; + wire RXLPMHFOVRDEN_delay; + wire RXLPMLFHOLD_delay; + wire RXLPMLFKLOVRDEN_delay; + wire RXLPMOSHOLD_delay; + wire RXLPMOSOVRDEN_delay; + wire RXMCOMMAALIGNEN_delay; + wire RXOOBRESET_delay; + wire RXOSCALRESET_delay; + wire RXOSHOLD_delay; + wire RXOSINTEN_delay; + wire RXOSINTHOLD_delay; + wire RXOSINTOVRDEN_delay; + wire RXOSINTSTROBE_delay; + wire RXOSINTTESTOVRDEN_delay; + wire RXOSOVRDEN_delay; + wire RXPCOMMAALIGNEN_delay; + wire RXPCSRESET_delay; + wire RXPHALIGNEN_delay; + wire RXPHALIGN_delay; + wire RXPHDLYPD_delay; + wire RXPHDLYRESET_delay; + wire RXPHOVRDEN_delay; + wire RXPMARESET_delay; + wire RXPOLARITY_delay; + wire RXPRBSCNTRESET_delay; + wire RXPROGDIVRESET_delay; + wire RXRATEMODE_delay; + wire RXSLIDE_delay; + wire RXSLIPOUTCLK_delay; + wire RXSLIPPMA_delay; + wire RXSYNCALLIN_delay; + wire RXSYNCIN_delay; + wire RXSYNCMODE_delay; + wire RXUSERRDY_delay; + wire RXUSRCLK2_delay; + wire RXUSRCLK_delay; + wire SIGVALIDCLK_delay; + wire TX8B10BEN_delay; + wire TXCOMINIT_delay; + wire TXCOMSAS_delay; + wire TXCOMWAKE_delay; + wire TXDCCFORCESTART_delay; + wire TXDCCRESET_delay; + wire TXDEEMPH_delay; + wire TXDETECTRX_delay; + wire TXDIFFPD_delay; + wire TXDLYBYPASS_delay; + wire TXDLYEN_delay; + wire TXDLYHOLD_delay; + wire TXDLYOVRDEN_delay; + wire TXDLYSRESET_delay; + wire TXDLYUPDOWN_delay; + wire TXELECIDLE_delay; + wire TXELFORCESTART_delay; + wire TXINHIBIT_delay; + wire TXLATCLK_delay; + wire TXPCSRESET_delay; + wire TXPDELECIDLEMODE_delay; + wire TXPHALIGNEN_delay; + wire TXPHALIGN_delay; + wire TXPHDLYPD_delay; + wire TXPHDLYRESET_delay; + wire TXPHDLYTSTCLK_delay; + wire TXPHINIT_delay; + wire TXPHOVRDEN_delay; + wire TXPIPPMEN_delay; + wire TXPIPPMOVRDEN_delay; + wire TXPIPPMPD_delay; + wire TXPIPPMSEL_delay; + wire TXPISOPD_delay; + wire TXPMARESET_delay; + wire TXPOLARITY_delay; + wire TXPRBSFORCEERR_delay; + wire TXPROGDIVRESET_delay; + wire TXRATEMODE_delay; + wire TXSWING_delay; + wire TXSYNCALLIN_delay; + wire TXSYNCIN_delay; + wire TXSYNCMODE_delay; + wire TXUSERRDY_delay; + wire TXUSRCLK2_delay; + wire TXUSRCLK_delay; + wire [127:0] TXDATA_delay; + wire [15:0] DRPDI_delay; + wire [15:0] GTRSVD_delay; + wire [15:0] LOOPRSVD_delay; + wire [15:0] PCSRSVDIN_delay; + wire [15:0] TXCTRL0_delay; + wire [15:0] TXCTRL1_delay; + wire [19:0] TSTIN_delay; + wire [1:0] RXELECIDLEMODE_delay; + wire [1:0] RXMONITORSEL_delay; + wire [1:0] RXPD_delay; + wire [1:0] RXPLLCLKSEL_delay; + wire [1:0] RXSYSCLKSEL_delay; + wire [1:0] TXPD_delay; + wire [1:0] TXPLLCLKSEL_delay; + wire [1:0] TXSYSCLKSEL_delay; + wire [2:0] CPLLREFCLKSEL_delay; + wire [2:0] LOOPBACK_delay; + wire [2:0] RXCHBONDLEVEL_delay; + wire [2:0] RXOUTCLKSEL_delay; + wire [2:0] RXRATE_delay; + wire [2:0] TXBUFDIFFCTRL_delay; + wire [2:0] TXMARGIN_delay; + wire [2:0] TXOUTCLKSEL_delay; + wire [2:0] TXRATE_delay; + wire [3:0] RXOSINTCFG_delay; + wire [3:0] RXPRBSSEL_delay; + wire [3:0] TXPRBSSEL_delay; + wire [4:0] PCSRSVDIN2_delay; + wire [4:0] PMARSVDIN_delay; + wire [4:0] RXCHBONDI_delay; + wire [4:0] TXDIFFCTRL_delay; + wire [4:0] TXPIPPMSTEPSIZE_delay; + wire [4:0] TXPOSTCURSOR_delay; + wire [4:0] TXPRECURSOR_delay; + wire [5:0] TXHEADER_delay; + wire [6:0] TXMAINCURSOR_delay; + wire [6:0] TXSEQUENCE_delay; + wire [7:0] TX8B10BBYPASS_delay; + wire [7:0] TXCTRL2_delay; + wire [7:0] TXDATAEXTENDRSVD_delay; + wire [9:0] DRPADDR_delay; + + assign #(out_delay) BUFGTCE = BUFGTCE_delay; + assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay; + assign #(out_delay) BUFGTDIV = BUFGTDIV_delay; + assign #(out_delay) BUFGTRESET = BUFGTRESET_delay; + assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay; + assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay; + assign #(out_delay) CPLLLOCK = CPLLLOCK_delay; + assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay; + assign #(out_delay) DMONITOROUT = DMONITOROUT_delay; + assign #(out_delay) DRPDO = DRPDO_delay; + assign #(out_delay) DRPRDY = DRPRDY_delay; + assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay; + assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay; + assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay; + assign #(out_delay) GTYTXN = GTYTXN_delay; + assign #(out_delay) GTYTXP = GTYTXP_delay; + assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay; + assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay; + assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay; + assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay; + assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay; + assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay; + assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay; + assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay; + assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay; + assign #(out_delay) PHYSTATUS = PHYSTATUS_delay; + assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay; + assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay; + assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay; + assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay; + assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay; + assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay; + assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay; + assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay; + assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay; + assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay; + assign #(out_delay) RXCHBONDO = RXCHBONDO_delay; + assign #(out_delay) RXCKCALDONE = RXCKCALDONE_delay; + assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay; + assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay; + assign #(out_delay) RXCOMMADET = RXCOMMADET_delay; + assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay; + assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay; + assign #(out_delay) RXCTRL0 = RXCTRL0_delay; + assign #(out_delay) RXCTRL1 = RXCTRL1_delay; + assign #(out_delay) RXCTRL2 = RXCTRL2_delay; + assign #(out_delay) RXCTRL3 = RXCTRL3_delay; + assign #(out_delay) RXDATA = RXDATA_delay; + assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay; + assign #(out_delay) RXDATAVALID = RXDATAVALID_delay; + assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay; + assign #(out_delay) RXELECIDLE = RXELECIDLE_delay; + assign #(out_delay) RXHEADER = RXHEADER_delay; + assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay; + assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay; + assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay; + assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay; + assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay; + assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay; + assign #(out_delay) RXOUTCLK = RXOUTCLK_delay; + assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay; + assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay; + assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay; + assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay; + assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay; + assign #(out_delay) RXPRBSERR = RXPRBSERR_delay; + assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay; + assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay; + assign #(out_delay) RXRATEDONE = RXRATEDONE_delay; + assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay; + assign #(out_delay) RXRESETDONE = RXRESETDONE_delay; + assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay; + assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay; + assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay; + assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay; + assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay; + assign #(out_delay) RXSTATUS = RXSTATUS_delay; + assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay; + assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay; + assign #(out_delay) RXVALID = RXVALID_delay; + assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay; + assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay; + assign #(out_delay) TXDCCDONE = TXDCCDONE_delay; + assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay; + assign #(out_delay) TXOUTCLK = TXOUTCLK_delay; + assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay; + assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay; + assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay; + assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay; + assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay; + assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay; + assign #(out_delay) TXRATEDONE = TXRATEDONE_delay; + assign #(out_delay) TXRESETDONE = TXRESETDONE_delay; + assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay; + assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) DRPCLK_delay = DRPCLK; + assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2; + assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK; + assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2; + + assign #(in_delay) DRPADDR_delay = DRPADDR; + assign #(in_delay) DRPDI_delay = DRPDI; + assign #(in_delay) DRPEN_delay = DRPEN; + assign #(in_delay) DRPWE_delay = DRPWE; + assign #(in_delay) RX8B10BEN_delay = RX8B10BEN; + assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN; + assign #(in_delay) RXCHBONDI_delay = RXCHBONDI; + assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL; + assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER; + assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE; + assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN; + assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP; + assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN; + assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN; + assign #(in_delay) RXPOLARITY_delay = RXPOLARITY; + assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL; + assign #(in_delay) RXRATE_delay = RXRATE; + assign #(in_delay) RXSLIDE_delay = RXSLIDE; + assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK; + assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA; + assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS; + assign #(in_delay) TX8B10BEN_delay = TX8B10BEN; + assign #(in_delay) TXCOMINIT_delay = TXCOMINIT; + assign #(in_delay) TXCOMSAS_delay = TXCOMSAS; + assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE; + assign #(in_delay) TXCTRL0_delay = TXCTRL0; + assign #(in_delay) TXCTRL1_delay = TXCTRL1; + assign #(in_delay) TXCTRL2_delay = TXCTRL2; + assign #(in_delay) TXDATA_delay = TXDATA; + assign #(in_delay) TXDETECTRX_delay = TXDETECTRX; + assign #(in_delay) TXELECIDLE_delay = TXELECIDLE; + assign #(in_delay) TXHEADER_delay = TXHEADER; + assign #(in_delay) TXINHIBIT_delay = TXINHIBIT; + assign #(in_delay) TXPD_delay = TXPD; + assign #(in_delay) TXPOLARITY_delay = TXPOLARITY; + assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR; + assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL; + assign #(in_delay) TXRATE_delay = TXRATE; + assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE; +`endif + +// inputs with no timing checks + assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0; + assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1; + assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK; + assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK; + assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK; + assign #(inclk_delay) RXLATCLK_delay = RXLATCLK; + assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK; + assign #(inclk_delay) TXLATCLK_delay = TXLATCLK; + assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK; + assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK; + + assign #(in_delay) CDRSTEPDIR_delay = CDRSTEPDIR; + assign #(in_delay) CDRSTEPSQ_delay = CDRSTEPSQ; + assign #(in_delay) CDRSTEPSX_delay = CDRSTEPSX; + assign #(in_delay) CFGRESET_delay = CFGRESET; + assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN; + assign #(in_delay) CPLLPD_delay = CPLLPD; + assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL; + assign #(in_delay) CPLLRESET_delay = CPLLRESET; + assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET; + assign #(in_delay) ELPCALDVORWREN_delay = ELPCALDVORWREN; + assign #(in_delay) ELPCALPAORWREN_delay = ELPCALPAORWREN; + assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE; + assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART; + assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN; + assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN; + assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN; + assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN; + assign #(in_delay) EYESCANMODE_delay = EYESCANMODE; + assign #(in_delay) EYESCANRESET_delay = EYESCANRESET; + assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER; + assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0; + assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1; + assign #(in_delay) GTREFCLK0_delay = GTREFCLK0; + assign #(in_delay) GTREFCLK1_delay = GTREFCLK1; + assign #(in_delay) GTRESETSEL_delay = GTRESETSEL; + assign #(in_delay) GTRSVD_delay = GTRSVD; + assign #(in_delay) GTRXRESET_delay = GTRXRESET; + assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0; + assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1; + assign #(in_delay) GTTXRESET_delay = GTTXRESET; + assign #(in_delay) GTYRXN_delay = GTYRXN; + assign #(in_delay) GTYRXP_delay = GTYRXP; + assign #(in_delay) LOOPBACK_delay = LOOPBACK; + assign #(in_delay) LOOPRSVD_delay = LOOPRSVD; + assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN; + assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN; + assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE; + assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE; + assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART; + assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE; + assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2; + assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN; + assign #(in_delay) PMARSVDIN_delay = PMARSVDIN; + assign #(in_delay) QPLL0CLK_delay = QPLL0CLK; + assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK; + assign #(in_delay) QPLL1CLK_delay = QPLL1CLK; + assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK; + assign #(in_delay) RESETOVRD_delay = RESETOVRD; + assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX; + assign #(in_delay) RXBUFRESET_delay = RXBUFRESET; + assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET; + assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD; + assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN; + assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV; + assign #(in_delay) RXCDRRESET_delay = RXCDRRESET; + assign #(in_delay) RXCKCALRESET_delay = RXCKCALRESET; + assign #(in_delay) RXDCCFORCESTART_delay = RXDCCFORCESTART; + assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD; + assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN; + assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD; + assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN; + assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET; + assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD; + assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN; + assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD; + assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN; + assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD; + assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN; + assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD; + assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN; + assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD; + assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN; + assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD; + assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN; + assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD; + assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN; + assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD; + assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN; + assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD; + assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN; + assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD; + assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN; + assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD; + assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN; + assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD; + assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN; + assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD; + assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN; + assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD; + assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN; + assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD; + assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN; + assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD; + assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN; + assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN; + assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN; + assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS; + assign #(in_delay) RXDLYEN_delay = RXDLYEN; + assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN; + assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET; + assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE; + assign #(in_delay) RXLPMEN_delay = RXLPMEN; + assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD; + assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN; + assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD; + assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN; + assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD; + assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN; + assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD; + assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN; + assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL; + assign #(in_delay) RXOOBRESET_delay = RXOOBRESET; + assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET; + assign #(in_delay) RXOSHOLD_delay = RXOSHOLD; + assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG; + assign #(in_delay) RXOSINTEN_delay = RXOSINTEN; + assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD; + assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN; + assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE; + assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN; + assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN; + assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL; + assign #(in_delay) RXPCSRESET_delay = RXPCSRESET; + assign #(in_delay) RXPD_delay = RXPD; + assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN; + assign #(in_delay) RXPHALIGN_delay = RXPHALIGN; + assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD; + assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET; + assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN; + assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL; + assign #(in_delay) RXPMARESET_delay = RXPMARESET; + assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET; + assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET; + assign #(in_delay) RXRATEMODE_delay = RXRATEMODE; + assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN; + assign #(in_delay) RXSYNCIN_delay = RXSYNCIN; + assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE; + assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL; + assign #(in_delay) RXUSERRDY_delay = RXUSERRDY; + assign #(in_delay) TSTIN_delay = TSTIN; + assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL; + assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD; + assign #(in_delay) TXDCCFORCESTART_delay = TXDCCFORCESTART; + assign #(in_delay) TXDCCRESET_delay = TXDCCRESET; + assign #(in_delay) TXDEEMPH_delay = TXDEEMPH; + assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL; + assign #(in_delay) TXDIFFPD_delay = TXDIFFPD; + assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS; + assign #(in_delay) TXDLYEN_delay = TXDLYEN; + assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD; + assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN; + assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET; + assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN; + assign #(in_delay) TXELFORCESTART_delay = TXELFORCESTART; + assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR; + assign #(in_delay) TXMARGIN_delay = TXMARGIN; + assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL; + assign #(in_delay) TXPCSRESET_delay = TXPCSRESET; + assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE; + assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN; + assign #(in_delay) TXPHALIGN_delay = TXPHALIGN; + assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD; + assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET; + assign #(in_delay) TXPHINIT_delay = TXPHINIT; + assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN; + assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN; + assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN; + assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD; + assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL; + assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE; + assign #(in_delay) TXPISOPD_delay = TXPISOPD; + assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL; + assign #(in_delay) TXPMARESET_delay = TXPMARESET; + assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR; + assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR; + assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET; + assign #(in_delay) TXRATEMODE_delay = TXRATEMODE; + assign #(in_delay) TXSWING_delay = TXSWING; + assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN; + assign #(in_delay) TXSYNCIN_delay = TXSYNCIN; + assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE; + assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL; + assign #(in_delay) TXUSERRDY_delay = TXUSERRDY; + + assign BUFGTCEMASK_delay = BUFGTCEMASK_out; + assign BUFGTCE_delay = BUFGTCE_out; + assign BUFGTDIV_delay = BUFGTDIV_out; + assign BUFGTRESET_delay = BUFGTRESET_out; + assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out; + assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out; + assign CPLLLOCK_delay = CPLLLOCK_out; + assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out; + assign DMONITOROUT_delay = DMONITOROUT_out; + assign DRPDO_delay = DRPDO_out; + assign DRPRDY_delay = DRPRDY_out; + assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out; + assign GTPOWERGOOD_delay = GTPOWERGOOD_out; + assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out; + assign GTYTXN_delay = GTYTXN_out; + assign GTYTXP_delay = GTYTXP_out; + assign PCIERATEGEN3_delay = PCIERATEGEN3_out; + assign PCIERATEIDLE_delay = PCIERATEIDLE_out; + assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out; + assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out; + assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out; + assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out; + assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out; + assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out; + assign PCSRSVDOUT_delay = PCSRSVDOUT_out; + assign PHYSTATUS_delay = PHYSTATUS_out; + assign PINRSRVDAS_delay = PINRSRVDAS_out; + assign RESETEXCEPTION_delay = RESETEXCEPTION_out; + assign RXBUFSTATUS_delay = RXBUFSTATUS_out; + assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out; + assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out; + assign RXCDRLOCK_delay = RXCDRLOCK_out; + assign RXCDRPHDONE_delay = RXCDRPHDONE_out; + assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out; + assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out; + assign RXCHANREALIGN_delay = RXCHANREALIGN_out; + assign RXCHBONDO_delay = RXCHBONDO_out; + assign RXCKCALDONE_delay = RXCKCALDONE_out; + assign RXCLKCORCNT_delay = RXCLKCORCNT_out; + assign RXCOMINITDET_delay = RXCOMINITDET_out; + assign RXCOMMADET_delay = RXCOMMADET_out; + assign RXCOMSASDET_delay = RXCOMSASDET_out; + assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out; + assign RXCTRL0_delay = RXCTRL0_out; + assign RXCTRL1_delay = RXCTRL1_out; + assign RXCTRL2_delay = RXCTRL2_out; + assign RXCTRL3_delay = RXCTRL3_out; + assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out; + assign RXDATAVALID_delay = RXDATAVALID_out; + assign RXDATA_delay = RXDATA_out; + assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out; + assign RXELECIDLE_delay = RXELECIDLE_out; + assign RXHEADERVALID_delay = RXHEADERVALID_out; + assign RXHEADER_delay = RXHEADER_out; + assign RXMONITOROUT_delay = RXMONITOROUT_out; + assign RXOSINTDONE_delay = RXOSINTDONE_out; + assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out; + assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out; + assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out; + assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out; + assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out; + assign RXOUTCLK_delay = RXOUTCLK_out; + assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out; + assign RXPHALIGNERR_delay = RXPHALIGNERR_out; + assign RXPMARESETDONE_delay = RXPMARESETDONE_out; + assign RXPRBSERR_delay = RXPRBSERR_out; + assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out; + assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out; + assign RXRATEDONE_delay = RXRATEDONE_out; + assign RXRECCLKOUT_delay = RXRECCLKOUT_out; + assign RXRESETDONE_delay = RXRESETDONE_out; + assign RXSLIDERDY_delay = RXSLIDERDY_out; + assign RXSLIPDONE_delay = RXSLIPDONE_out; + assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out; + assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out; + assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out; + assign RXSTATUS_delay = RXSTATUS_out; + assign RXSYNCDONE_delay = RXSYNCDONE_out; + assign RXSYNCOUT_delay = RXSYNCOUT_out; + assign RXVALID_delay = RXVALID_out; + assign TXBUFSTATUS_delay = TXBUFSTATUS_out; + assign TXCOMFINISH_delay = TXCOMFINISH_out; + assign TXDCCDONE_delay = TXDCCDONE_out; + assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out; + assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out; + assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out; + assign TXOUTCLK_delay = TXOUTCLK_out; + assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out; + assign TXPHINITDONE_delay = TXPHINITDONE_out; + assign TXPMARESETDONE_delay = TXPMARESETDONE_out; + assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out; + assign TXRATEDONE_delay = TXRATEDONE_out; + assign TXRESETDONE_delay = TXRESETDONE_out; + assign TXSYNCDONE_delay = TXSYNCDONE_out; + assign TXSYNCOUT_delay = TXSYNCOUT_out; + + assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR_delay; // rv 0 + assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ_delay; // rv 0 + assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX_delay; // rv 0 + assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET_delay; // rv 0 + assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0_delay; // rv 0 + assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1_delay; // rv 0 + assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK_delay; // rv 0 + assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN_delay; // rv 0 + assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD_delay; // rv 0 + assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL_delay[0]; // rv 1 + assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL_delay[1]; // rv 0 + assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL_delay[2]; // rv 0 + assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET_delay; // rv 0 + assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET_delay; // rv 0 + assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK_delay; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign ELPCALDVORWREN_in = (ELPCALDVORWREN !== 1'bz) && ELPCALDVORWREN_delay; // rv 0 + assign ELPCALPAORWREN_in = (ELPCALPAORWREN !== 1'bz) && ELPCALPAORWREN_delay; // rv 0 + assign EVODDPHICALDONE_in = (EVODDPHICALDONE !== 1'bz) && EVODDPHICALDONE_delay; // rv 0 + assign EVODDPHICALSTART_in = (EVODDPHICALSTART !== 1'bz) && EVODDPHICALSTART_delay; // rv 0 + assign EVODDPHIDRDEN_in = (EVODDPHIDRDEN !== 1'bz) && EVODDPHIDRDEN_delay; // rv 0 + assign EVODDPHIDWREN_in = (EVODDPHIDWREN !== 1'bz) && EVODDPHIDWREN_delay; // rv 0 + assign EVODDPHIXRDEN_in = (EVODDPHIXRDEN !== 1'bz) && EVODDPHIXRDEN_delay; // rv 0 + assign EVODDPHIXWREN_in = (EVODDPHIXWREN !== 1'bz) && EVODDPHIXWREN_delay; // rv 0 + assign EYESCANMODE_in = (EYESCANMODE !== 1'bz) && EYESCANMODE_delay; // rv 0 + assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET_delay; // rv 0 + assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER_delay; // rv 0 + assign GTGREFCLK_in = GTGREFCLK_delay; + assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay; + assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay; + assign GTREFCLK0_in = GTREFCLK0_delay; + assign GTREFCLK1_in = GTREFCLK1_delay; + assign GTRESETSEL_in = (GTRESETSEL !== 1'bz) && GTRESETSEL_delay; // rv 0 + assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD_delay[0]; // rv 0 + assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD_delay[10]; // rv 0 + assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD_delay[11]; // rv 0 + assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD_delay[12]; // rv 0 + assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD_delay[13]; // rv 0 + assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD_delay[14]; // rv 0 + assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD_delay[15]; // rv 0 + assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD_delay[1]; // rv 0 + assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD_delay[2]; // rv 0 + assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD_delay[3]; // rv 0 + assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD_delay[4]; // rv 0 + assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD_delay[5]; // rv 0 + assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD_delay[6]; // rv 0 + assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD_delay[7]; // rv 0 + assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD_delay[8]; // rv 0 + assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD_delay[9]; // rv 0 + assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET_delay; // rv 0 + assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay; + assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay; + assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET_delay; // rv 0 + assign GTYRXN_in = GTYRXN_delay; + assign GTYRXP_in = GTYRXP_delay; + assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK_delay[0]; // rv 0 + assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK_delay[1]; // rv 0 + assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK_delay[2]; // rv 0 + assign LOOPRSVD_in[0] = (LOOPRSVD[0] !== 1'bz) && LOOPRSVD_delay[0]; // rv 0 + assign LOOPRSVD_in[10] = (LOOPRSVD[10] !== 1'bz) && LOOPRSVD_delay[10]; // rv 0 + assign LOOPRSVD_in[11] = (LOOPRSVD[11] !== 1'bz) && LOOPRSVD_delay[11]; // rv 0 + assign LOOPRSVD_in[12] = (LOOPRSVD[12] !== 1'bz) && LOOPRSVD_delay[12]; // rv 0 + assign LOOPRSVD_in[13] = (LOOPRSVD[13] !== 1'bz) && LOOPRSVD_delay[13]; // rv 0 + assign LOOPRSVD_in[14] = (LOOPRSVD[14] !== 1'bz) && LOOPRSVD_delay[14]; // rv 0 + assign LOOPRSVD_in[15] = (LOOPRSVD[15] !== 1'bz) && LOOPRSVD_delay[15]; // rv 0 + assign LOOPRSVD_in[1] = (LOOPRSVD[1] !== 1'bz) && LOOPRSVD_delay[1]; // rv 0 + assign LOOPRSVD_in[2] = (LOOPRSVD[2] !== 1'bz) && LOOPRSVD_delay[2]; // rv 0 + assign LOOPRSVD_in[3] = (LOOPRSVD[3] !== 1'bz) && LOOPRSVD_delay[3]; // rv 0 + assign LOOPRSVD_in[4] = (LOOPRSVD[4] !== 1'bz) && LOOPRSVD_delay[4]; // rv 0 + assign LOOPRSVD_in[5] = (LOOPRSVD[5] !== 1'bz) && LOOPRSVD_delay[5]; // rv 0 + assign LOOPRSVD_in[6] = (LOOPRSVD[6] !== 1'bz) && LOOPRSVD_delay[6]; // rv 0 + assign LOOPRSVD_in[7] = (LOOPRSVD[7] !== 1'bz) && LOOPRSVD_delay[7]; // rv 0 + assign LOOPRSVD_in[8] = (LOOPRSVD[8] !== 1'bz) && LOOPRSVD_delay[8]; // rv 0 + assign LOOPRSVD_in[9] = (LOOPRSVD[9] !== 1'bz) && LOOPRSVD_delay[9]; // rv 0 + assign LPBKRXTXSEREN_in = (LPBKRXTXSEREN !== 1'bz) && LPBKRXTXSEREN_delay; // rv 0 + assign LPBKTXRXSEREN_in = (LPBKTXRXSEREN !== 1'bz) && LPBKTXRXSEREN_delay; // rv 0 + assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE_delay; // rv 0 + assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE_delay; // rv 0 + assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART_delay; // rv 0 + assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE_delay; // rv 0 + assign PCSRSVDIN2_in[0] = (PCSRSVDIN2[0] !== 1'bz) && PCSRSVDIN2_delay[0]; // rv 0 + assign PCSRSVDIN2_in[1] = (PCSRSVDIN2[1] !== 1'bz) && PCSRSVDIN2_delay[1]; // rv 0 + assign PCSRSVDIN2_in[2] = (PCSRSVDIN2[2] !== 1'bz) && PCSRSVDIN2_delay[2]; // rv 0 + assign PCSRSVDIN2_in[3] = (PCSRSVDIN2[3] !== 1'bz) && PCSRSVDIN2_delay[3]; // rv 0 + assign PCSRSVDIN2_in[4] = (PCSRSVDIN2[4] !== 1'bz) && PCSRSVDIN2_delay[4]; // rv 0 + assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] !== 1'bz) && PCSRSVDIN_delay[0]; // rv 0 + assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN_delay[10]; // rv 0 + assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN_delay[11]; // rv 0 + assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN_delay[12]; // rv 0 + assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN_delay[13]; // rv 0 + assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN_delay[14]; // rv 0 + assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN_delay[15]; // rv 0 + assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN_delay[1]; // rv 0 + assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN_delay[2]; // rv 0 + assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN_delay[3]; // rv 0 + assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN_delay[4]; // rv 0 + assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN_delay[5]; // rv 0 + assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN_delay[6]; // rv 0 + assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN_delay[7]; // rv 0 + assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN_delay[8]; // rv 0 + assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN_delay[9]; // rv 0 + assign PMARSVDIN_in[0] = (PMARSVDIN[0] !== 1'bz) && PMARSVDIN_delay[0]; // rv 0 + assign PMARSVDIN_in[1] = (PMARSVDIN[1] !== 1'bz) && PMARSVDIN_delay[1]; // rv 0 + assign PMARSVDIN_in[2] = (PMARSVDIN[2] !== 1'bz) && PMARSVDIN_delay[2]; // rv 0 + assign PMARSVDIN_in[3] = (PMARSVDIN[3] !== 1'bz) && PMARSVDIN_delay[3]; // rv 0 + assign PMARSVDIN_in[4] = (PMARSVDIN[4] !== 1'bz) && PMARSVDIN_delay[4]; // rv 0 + assign QPLL0CLK_in = QPLL0CLK_delay; + assign QPLL0REFCLK_in = QPLL0REFCLK_delay; + assign QPLL1CLK_in = QPLL1CLK_delay; + assign QPLL1REFCLK_in = QPLL1REFCLK_delay; + assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD_delay; // rv 0 + assign RSTCLKENTX_in = (RSTCLKENTX !== 1'bz) && RSTCLKENTX_delay; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0 + assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET_delay; // rv 0 + assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET_delay; // rv 0 + assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD_delay; // rv 0 + assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN_delay; // rv 0 + assign RXCDRRESETRSV_in = (RXCDRRESETRSV !== 1'bz) && RXCDRRESETRSV_delay; // rv 0 + assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET_delay; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0 + assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET_delay; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0 + assign RXDCCFORCESTART_in = (RXDCCFORCESTART !== 1'bz) && RXDCCFORCESTART_delay; // rv 0 + assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD_delay; // rv 0 + assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN_delay; // rv 0 + assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD_delay; // rv 0 + assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN_delay; // rv 0 + assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET_delay; // rv 0 + assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD_delay; // rv 0 + assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN_delay; // rv 0 + assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD_delay; // rv 0 + assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN_delay; // rv 0 + assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD_delay; // rv 0 + assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN_delay; // rv 0 + assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD_delay; // rv 0 + assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN_delay; // rv 0 + assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD_delay; // rv 0 + assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN_delay; // rv 0 + assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD_delay; // rv 0 + assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN_delay; // rv 0 + assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD_delay; // rv 0 + assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN_delay; // rv 0 + assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD_delay; // rv 0 + assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN_delay; // rv 0 + assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD_delay; // rv 0 + assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN_delay; // rv 0 + assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD_delay; // rv 0 + assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN_delay; // rv 0 + assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD_delay; // rv 0 + assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN_delay; // rv 0 + assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD_delay; // rv 0 + assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN_delay; // rv 0 + assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD_delay; // rv 0 + assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN_delay; // rv 0 + assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD_delay; // rv 0 + assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN_delay; // rv 0 + assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD_delay; // rv 0 + assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN_delay; // rv 0 + assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD_delay; // rv 0 + assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN_delay; // rv 0 + assign RXDFEVSEN_in = (RXDFEVSEN !== 1'bz) && RXDFEVSEN_delay; // rv 0 + assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN_delay; // rv 0 + assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS_delay; // rv 0 + assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN_delay; // rv 0 + assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN_delay; // rv 0 + assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET_delay; // rv 0 + assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE_delay[0]; // rv 0 + assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE_delay[1]; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0 + assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK_delay; // rv 0 + assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN_delay; // rv 0 + assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD_delay; // rv 0 + assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN_delay; // rv 0 + assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD_delay; // rv 0 + assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN_delay; // rv 0 + assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD_delay; // rv 0 + assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN_delay; // rv 0 + assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD_delay; // rv 0 + assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN_delay; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0 + assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL_delay[0]; // rv 0 + assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL_delay[1]; // rv 0 + assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET_delay; // rv 0 + assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET_delay; // rv 0 + assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD_delay; // rv 0 + assign RXOSINTCFG_in[0] = (RXOSINTCFG[0] !== 1'bz) && RXOSINTCFG_delay[0]; // rv 0 + assign RXOSINTCFG_in[1] = (RXOSINTCFG[1] === 1'bz) || RXOSINTCFG_delay[1]; // rv 1 + assign RXOSINTCFG_in[2] = (RXOSINTCFG[2] === 1'bz) || RXOSINTCFG_delay[2]; // rv 1 + assign RXOSINTCFG_in[3] = (RXOSINTCFG[3] !== 1'bz) && RXOSINTCFG_delay[3]; // rv 0 + assign RXOSINTEN_in = (RXOSINTEN === 1'bz) || RXOSINTEN_delay; // rv 1 + assign RXOSINTHOLD_in = (RXOSINTHOLD !== 1'bz) && RXOSINTHOLD_delay; // rv 0 + assign RXOSINTOVRDEN_in = (RXOSINTOVRDEN !== 1'bz) && RXOSINTOVRDEN_delay; // rv 0 + assign RXOSINTSTROBE_in = (RXOSINTSTROBE !== 1'bz) && RXOSINTSTROBE_delay; // rv 0 + assign RXOSINTTESTOVRDEN_in = (RXOSINTTESTOVRDEN !== 1'bz) && RXOSINTTESTOVRDEN_delay; // rv 0 + assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN_delay; // rv 0 + assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL_delay[0]; // rv 0 + assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL_delay[1]; // rv 0 + assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL_delay[2]; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0 + assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET_delay; // rv 0 + assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD_delay[0]; // rv 0 + assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD_delay[1]; // rv 0 + assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN_delay; // rv 0 + assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN_delay; // rv 0 + assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD_delay; // rv 0 + assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET_delay; // rv 0 + assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN_delay; // rv 0 + assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL_delay[0]; // rv 0 + assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL_delay[1]; // rv 0 + assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET_delay; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0 + assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET_delay; // rv 0 + assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE_delay; // rv 0 + assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0 + assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0 + assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0 + assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0 + assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN_delay; // rv 0 + assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN_delay; // rv 0 + assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE_delay; // rv 1 + assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL_delay[0]; // rv 0 + assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL_delay[1]; // rv 0 + assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY_delay; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0 + assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK_delay; // rv 0 + assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN_delay[0]; // rv 0 + assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN_delay[10]; // rv 0 + assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN_delay[11]; // rv 0 + assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN_delay[12]; // rv 0 + assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN_delay[13]; // rv 0 + assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN_delay[14]; // rv 0 + assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN_delay[15]; // rv 0 + assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN_delay[16]; // rv 0 + assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN_delay[17]; // rv 0 + assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN_delay[18]; // rv 0 + assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN_delay[19]; // rv 0 + assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN_delay[1]; // rv 0 + assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN_delay[2]; // rv 0 + assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN_delay[3]; // rv 0 + assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN_delay[4]; // rv 0 + assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN_delay[5]; // rv 0 + assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN_delay[6]; // rv 0 + assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN_delay[7]; // rv 0 + assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN_delay[8]; // rv 0 + assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN_delay[9]; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0 + assign TXBUFDIFFCTRL_in[0] = (TXBUFDIFFCTRL[0] !== 1'bz) && TXBUFDIFFCTRL_delay[0]; // rv 0 + assign TXBUFDIFFCTRL_in[1] = (TXBUFDIFFCTRL[1] !== 1'bz) && TXBUFDIFFCTRL_delay[1]; // rv 0 + assign TXBUFDIFFCTRL_in[2] = (TXBUFDIFFCTRL[2] !== 1'bz) && TXBUFDIFFCTRL_delay[2]; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0 + assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD_delay[0]; // rv 0 + assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD_delay[1]; // rv 0 + assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD_delay[2]; // rv 0 + assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD_delay[3]; // rv 0 + assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD_delay[4]; // rv 0 + assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD_delay[5]; // rv 0 + assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD_delay[6]; // rv 0 + assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD_delay[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0 + assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART_delay; // rv 0 + assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET_delay; // rv 0 + assign TXDEEMPH_in = (TXDEEMPH !== 1'bz) && TXDEEMPH_delay; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0 + assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL_delay[0]; // rv 0 + assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL_delay[1]; // rv 0 + assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL_delay[2]; // rv 0 + assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL_delay[3]; // rv 0 + assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL_delay[4]; // rv 0 + assign TXDIFFPD_in = (TXDIFFPD !== 1'bz) && TXDIFFPD_delay; // rv 0 + assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS_delay; // rv 0 + assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN_delay; // rv 0 + assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD_delay; // rv 0 + assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN_delay; // rv 0 + assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET_delay; // rv 0 + assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN_delay; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0 + assign TXELFORCESTART_in = (TXELFORCESTART !== 1'bz) && TXELFORCESTART_delay; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0 + assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK_delay; // rv 0 + assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR_delay[0]; // rv 0 + assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR_delay[1]; // rv 0 + assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR_delay[2]; // rv 0 + assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR_delay[3]; // rv 0 + assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR_delay[4]; // rv 0 + assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR_delay[5]; // rv 0 + assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR_delay[6]; // rv 0 + assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN_delay[0]; // rv 0 + assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN_delay[1]; // rv 0 + assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN_delay[2]; // rv 0 + assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL_delay[0]; // rv 0 + assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL_delay[1]; // rv 0 + assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL_delay[2]; // rv 0 + assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET_delay; // rv 0 + assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE_delay; // rv 0 + assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0 + assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0 + assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN_delay; // rv 0 + assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN_delay; // rv 0 + assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD_delay; // rv 0 + assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET_delay; // rv 0 + assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK_delay; // rv 0 + assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT_delay; // rv 0 + assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN_delay; // rv 0 + assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN_delay; // rv 0 + assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN_delay; // rv 0 + assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD_delay; // rv 0 + assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL_delay; // rv 0 + assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE_delay[0]; // rv 0 + assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE_delay[1]; // rv 0 + assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE_delay[2]; // rv 0 + assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE_delay[3]; // rv 0 + assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE_delay[4]; // rv 0 + assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD_delay; // rv 0 + assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL_delay[0]; // rv 0 + assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL_delay[1]; // rv 0 + assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET_delay; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0 + assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR_delay[0]; // rv 0 + assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR_delay[1]; // rv 0 + assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR_delay[2]; // rv 0 + assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR_delay[3]; // rv 0 + assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR_delay[4]; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0 + assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR_delay[0]; // rv 0 + assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR_delay[1]; // rv 0 + assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR_delay[2]; // rv 0 + assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR_delay[3]; // rv 0 + assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR_delay[4]; // rv 0 + assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET_delay; // rv 0 + assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE_delay; // rv 0 + assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0 + assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0 + assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0 + assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING_delay; // rv 0 + assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN_delay; // rv 0 + assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN_delay; // rv 0 + assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE_delay; // rv 1 + assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL_delay[0]; // rv 0 + assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL_delay[1]; // rv 0 + assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY_delay; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0 + assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK_delay; // rv 0 + + assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_DOUBLE_REG != "FALSE") && + (ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-131] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_WORD_REG != 1) && + (ALIGN_COMMA_WORD_REG != 2) && + (ALIGN_COMMA_WORD_REG != 4))) begin + $display("Error: [Unisim %s-133] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_MCOMMA_DET_REG != "TRUE") && + (ALIGN_MCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-134] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_PCOMMA_DET_REG != "TRUE") && + (ALIGN_PCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-136] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") && + (CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin + $display("Error: [Unisim %s-271] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") && + (CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-273] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_MAX_SKEW_REG != 7) && + (CHAN_BOND_MAX_SKEW_REG != 1) && + (CHAN_BOND_MAX_SKEW_REG != 2) && + (CHAN_BOND_MAX_SKEW_REG != 3) && + (CHAN_BOND_MAX_SKEW_REG != 4) && + (CHAN_BOND_MAX_SKEW_REG != 5) && + (CHAN_BOND_MAX_SKEW_REG != 6) && + (CHAN_BOND_MAX_SKEW_REG != 8) && + (CHAN_BOND_MAX_SKEW_REG != 9) && + (CHAN_BOND_MAX_SKEW_REG != 10) && + (CHAN_BOND_MAX_SKEW_REG != 11) && + (CHAN_BOND_MAX_SKEW_REG != 12) && + (CHAN_BOND_MAX_SKEW_REG != 13) && + (CHAN_BOND_MAX_SKEW_REG != 14))) begin + $display("Error: [Unisim %s-274] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") && + (CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-285] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_LEN_REG != 2) && + (CHAN_BOND_SEQ_LEN_REG != 1) && + (CHAN_BOND_SEQ_LEN_REG != 3) && + (CHAN_BOND_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-286] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_CORRECT_USE_REG != "TRUE") && + (CLK_CORRECT_USE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-299] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_KEEP_IDLE_REG != "FALSE") && + (CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-300] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin + $display("Error: [Unisim %s-301] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin + $display("Error: [Unisim %s-302] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_PRECEDENCE_REG != "TRUE") && + (CLK_COR_PRECEDENCE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-303] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-304] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_2_USE_REG != "FALSE") && + (CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-315] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_LEN_REG != 2) && + (CLK_COR_SEQ_LEN_REG != 1) && + (CLK_COR_SEQ_LEN_REG != 3) && + (CLK_COR_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-316] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_REG != 4) && + (CPLL_FBDIV_REG != 1) && + (CPLL_FBDIV_REG != 2) && + (CPLL_FBDIV_REG != 3) && + (CPLL_FBDIV_REG != 5) && + (CPLL_FBDIV_REG != 6) && + (CPLL_FBDIV_REG != 8) && + (CPLL_FBDIV_REG != 10) && + (CPLL_FBDIV_REG != 12) && + (CPLL_FBDIV_REG != 16) && + (CPLL_FBDIV_REG != 20))) begin + $display("Error: [Unisim %s-321] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_45_REG != 4) && + (CPLL_FBDIV_45_REG != 5))) begin + $display("Error: [Unisim %s-322] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_REFCLK_DIV_REG != 1) && + (CPLL_REFCLK_DIV_REG != 2) && + (CPLL_REFCLK_DIV_REG != 3) && + (CPLL_REFCLK_DIV_REG != 4) && + (CPLL_REFCLK_DIV_REG != 5) && + (CPLL_REFCLK_DIV_REG != 6) && + (CPLL_REFCLK_DIV_REG != 8) && + (CPLL_REFCLK_DIV_REG != 10) && + (CPLL_REFCLK_DIV_REG != 12) && + (CPLL_REFCLK_DIV_REG != 16) && + (CPLL_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-326] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-330] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_MCOMMA_DETECT_REG != "TRUE") && + (DEC_MCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-331] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_PCOMMA_DETECT_REG != "TRUE") && + (DEC_PCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-332] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_VALID_COMMA_ONLY_REG != "TRUE") && + (DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-333] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_ERRDET_EN_REG != "FALSE") && + (ES_ERRDET_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-340] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_EYE_SCAN_EN_REG != "FALSE") && + (ES_EYE_SCAN_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-341] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FTS_LANE_DESKEW_EN_REG != "FALSE") && + (FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-379] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") && + (PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin + $display("Error: [Unisim %s-407] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCS_PCIE_EN_REG != "FALSE") && + (PCS_PCIE_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-421] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREIQ_FREQ_BST_REG != 0) && + (PREIQ_FREQ_BST_REG != 1) && + (PREIQ_FREQ_BST_REG != 2) && + (PREIQ_FREQ_BST_REG != 3))) begin + $display("Error: [Unisim %s-431] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_ADDR_MODE_REG != "FULL") && + (RXBUF_ADDR_MODE_REG != "FAST"))) begin + $display("Error: [Unisim %s-436] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_EN_REG != "TRUE") && + (RXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-439] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-440] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") && + (RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-441] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") && + (RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-442] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-443] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin + $display("Error: [Unisim %s-444] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVRD_REG != "FALSE") && + (RXBUF_THRESH_OVRD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-445] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin + $display("Error: [Unisim %s-446] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXELECIDLE_CFG_REG != "SIGCFG_4") && + (RXELECIDLE_CFG_REG != "SIGCFG_1") && + (RXELECIDLE_CFG_REG != "SIGCFG_2") && + (RXELECIDLE_CFG_REG != "SIGCFG_3") && + (RXELECIDLE_CFG_REG != "SIGCFG_6") && + (RXELECIDLE_CFG_REG != "SIGCFG_8") && + (RXELECIDLE_CFG_REG != "SIGCFG_12") && + (RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin + $display("Error: [Unisim %s-518] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin + $display("Error: [Unisim %s-519] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGEARBOX_EN_REG != "FALSE") && + (RXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-520] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOOB_CLK_CFG_REG != "PMA") && + (RXOOB_CLK_CFG_REG != "FABRIC"))) begin + $display("Error: [Unisim %s-529] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOUT_DIV_REG != 4) && + (RXOUT_DIV_REG != 1) && + (RXOUT_DIV_REG != 2) && + (RXOUT_DIV_REG != 8) && + (RXOUT_DIV_REG != 16) && + (RXOUT_DIV_REG != 32))) begin + $display("Error: [Unisim %s-531] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, RXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPMACLK_SEL_REG != "DATA") && + (RXPMACLK_SEL_REG != "CROSSING") && + (RXPMACLK_SEL_REG != "EYESCAN"))) begin + $display("Error: [Unisim %s-546] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin + $display("Error: [Unisim %s-549] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_AUTO_WAIT_REG != 7) && + (RXSLIDE_AUTO_WAIT_REG != 1) && + (RXSLIDE_AUTO_WAIT_REG != 2) && + (RXSLIDE_AUTO_WAIT_REG != 3) && + (RXSLIDE_AUTO_WAIT_REG != 4) && + (RXSLIDE_AUTO_WAIT_REG != 5) && + (RXSLIDE_AUTO_WAIT_REG != 6) && + (RXSLIDE_AUTO_WAIT_REG != 8) && + (RXSLIDE_AUTO_WAIT_REG != 9) && + (RXSLIDE_AUTO_WAIT_REG != 10) && + (RXSLIDE_AUTO_WAIT_REG != 11) && + (RXSLIDE_AUTO_WAIT_REG != 12) && + (RXSLIDE_AUTO_WAIT_REG != 13) && + (RXSLIDE_AUTO_WAIT_REG != 14) && + (RXSLIDE_AUTO_WAIT_REG != 15))) begin + $display("Error: [Unisim %s-550] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_MODE_REG != "OFF") && + (RXSLIDE_MODE_REG != "AUTO") && + (RXSLIDE_MODE_REG != "PCS") && + (RXSLIDE_MODE_REG != "PMA"))) begin + $display("Error: [Unisim %s-551] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-559] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_SEL_REG != 3) && + (RX_CM_SEL_REG != 0) && + (RX_CM_SEL_REG != 1) && + (RX_CM_SEL_REG != 2))) begin + $display("Error: [Unisim %s-564] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 3, 0, 1 or 2. Instance: %m", MODULE_NAME, RX_CM_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_TRIM_REG != 10) && + (RX_CM_TRIM_REG != 0) && + (RX_CM_TRIM_REG != 1) && + (RX_CM_TRIM_REG != 2) && + (RX_CM_TRIM_REG != 3) && + (RX_CM_TRIM_REG != 4) && + (RX_CM_TRIM_REG != 5) && + (RX_CM_TRIM_REG != 6) && + (RX_CM_TRIM_REG != 7) && + (RX_CM_TRIM_REG != 8) && + (RX_CM_TRIM_REG != 9) && + (RX_CM_TRIM_REG != 11) && + (RX_CM_TRIM_REG != 12) && + (RX_CM_TRIM_REG != 13) && + (RX_CM_TRIM_REG != 14) && + (RX_CM_TRIM_REG != 15))) begin + $display("Error: [Unisim %s-565] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 10, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_WIDTH_REG != 20) && + (RX_DATA_WIDTH_REG != 16) && + (RX_DATA_WIDTH_REG != 32) && + (RX_DATA_WIDTH_REG != 40) && + (RX_DATA_WIDTH_REG != 64) && + (RX_DATA_WIDTH_REG != 80) && + (RX_DATA_WIDTH_REG != 128) && + (RX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-569] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") && + (RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-571] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFELPM_CFG0_REG != 0) && + (RX_DFELPM_CFG0_REG != 1) && + (RX_DFELPM_CFG0_REG != 2) && + (RX_DFELPM_CFG0_REG != 3) && + (RX_DFELPM_CFG0_REG != 4) && + (RX_DFELPM_CFG0_REG != 5) && + (RX_DFELPM_CFG0_REG != 6) && + (RX_DFELPM_CFG0_REG != 7))) begin + $display("Error: [Unisim %s-573] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_AGC_CFG1_REG != 2) && + (RX_DFE_AGC_CFG1_REG != 0) && + (RX_DFE_AGC_CFG1_REG != 1) && + (RX_DFE_AGC_CFG1_REG != 3) && + (RX_DFE_AGC_CFG1_REG != 4) && + (RX_DFE_AGC_CFG1_REG != 5) && + (RX_DFE_AGC_CFG1_REG != 6) && + (RX_DFE_AGC_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-577] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 2, 0, 1, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG0_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 0) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin + $display("Error: [Unisim %s-578] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG1_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 3) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 4) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 5) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 6) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-579] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") && + (RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin + $display("Error: [Unisim %s-583] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_INT_DATAWIDTH_REG != 1) && + (RX_INT_DATAWIDTH_REG != 0) && + (RX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-594] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_PROGDIV_CFG_REG != 0.0) && + (RX_PROGDIV_CFG_REG != 4.0) && + (RX_PROGDIV_CFG_REG != 5.0) && + (RX_PROGDIV_CFG_REG != 8.0) && + (RX_PROGDIV_CFG_REG != 10.0) && + (RX_PROGDIV_CFG_REG != 16.0) && + (RX_PROGDIV_CFG_REG != 16.5) && + (RX_PROGDIV_CFG_REG != 20.0) && + (RX_PROGDIV_CFG_REG != 32.0) && + (RX_PROGDIV_CFG_REG != 33.0) && + (RX_PROGDIV_CFG_REG != 40.0) && + (RX_PROGDIV_CFG_REG != 64.0) && + (RX_PROGDIV_CFG_REG != 66.0) && + (RX_PROGDIV_CFG_REG != 80.0) && + (RX_PROGDIV_CFG_REG != 100.0))) begin + $display("Error: [Unisim %s-596] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin + $display("Error: [Unisim %s-601] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_XCLK_SEL_REG != "RXDES") && + (RX_XCLK_SEL_REG != "RXPMA") && + (RX_XCLK_SEL_REG != "RXUSR"))) begin + $display("Error: [Unisim %s-611] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127))) begin + $display("Error: [Unisim %s-613] SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, SAS_MAX_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63))) begin + $display("Error: [Unisim %s-614] SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SAS_MIN_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") && + (SATA_CPLL_CFG_REG != "VCO_750MHZ") && + (SATA_CPLL_CFG_REG != "VCO_1500MHZ"))) begin + $display("Error: [Unisim %s-617] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63))) begin + $display("Error: [Unisim %s-619] SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63))) begin + $display("Error: [Unisim %s-620] SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-621] SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61))) begin + $display("Error: [Unisim %s-622] SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, SATA_MIN_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63))) begin + $display("Error: [Unisim %s-623] SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-624] SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SHOW_REALIGN_COMMA_REG != "TRUE") && + (SHOW_REALIGN_COMMA_REG != "FALSE"))) begin + $display("Error: [Unisim %s-625] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_MODE != "FAST")) begin + $display("Error: [Unisim %s-626] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RECEIVER_DETECT_PASS != "TRUE") && + (SIM_RECEIVER_DETECT_PASS != "FALSE"))) begin + $display("Error: [Unisim %s-627] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP != "TRUE") && + (SIM_RESET_SPEEDUP != "FALSE"))) begin + $display("Error: [Unisim %s-628] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION != 2) && + (SIM_VERSION != 1) && + (SIM_VERSION != 3))) begin + $display("Error: [Unisim %s-630] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_EN_REG != "TRUE") && + (TXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-638] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") && + (TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-639] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXFIFO_ADDR_CFG_REG != "LOW") && + (TXFIFO_ADDR_CFG_REG != "HIGH"))) begin + $display("Error: [Unisim %s-642] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin + $display("Error: [Unisim %s-643] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGEARBOX_EN_REG != "FALSE") && + (TXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-644] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXOUT_DIV_REG != 4) && + (TXOUT_DIV_REG != 1) && + (TXOUT_DIV_REG != 2) && + (TXOUT_DIV_REG != 8) && + (TXOUT_DIV_REG != 16) && + (TXOUT_DIV_REG != 32))) begin + $display("Error: [Unisim %s-646] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, TXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") && + (TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin + $display("Error: [Unisim %s-662] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-671] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DATA_WIDTH_REG != 20) && + (TX_DATA_WIDTH_REG != 16) && + (TX_DATA_WIDTH_REG != 32) && + (TX_DATA_WIDTH_REG != 40) && + (TX_DATA_WIDTH_REG != 64) && + (TX_DATA_WIDTH_REG != 80) && + (TX_DATA_WIDTH_REG != 128) && + (TX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-675] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRIVE_MODE_REG != "DIRECT") && + (TX_DRIVE_MODE_REG != "PIPE") && + (TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin + $display("Error: [Unisim %s-681] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRVMUX_CTRL_REG != 2) && + (TX_DRVMUX_CTRL_REG != 0) && + (TX_DRVMUX_CTRL_REG != 1) && + (TX_DRVMUX_CTRL_REG != 3))) begin + $display("Error: [Unisim %s-682] TX_DRVMUX_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_DRVMUX_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_INT_DATAWIDTH_REG != 1) && + (TX_INT_DATAWIDTH_REG != 0) && + (TX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-689] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") && + (TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin + $display("Error: [Unisim %s-690] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PI_BIASSET_REG != 0) && + (TX_PI_BIASSET_REG != 1) && + (TX_PI_BIASSET_REG != 2) && + (TX_PI_BIASSET_REG != 3))) begin + $display("Error: [Unisim %s-706] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PREDRV_CTRL_REG != 2) && + (TX_PREDRV_CTRL_REG != 0) && + (TX_PREDRV_CTRL_REG != 1) && + (TX_PREDRV_CTRL_REG != 3))) begin + $display("Error: [Unisim %s-714] TX_PREDRV_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_PREDRV_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGCLK_SEL_REG != "POSTPI") && + (TX_PROGCLK_SEL_REG != "CPLL") && + (TX_PROGCLK_SEL_REG != "PREPI"))) begin + $display("Error: [Unisim %s-715] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGDIV_CFG_REG != 0.0) && + (TX_PROGDIV_CFG_REG != 4.0) && + (TX_PROGDIV_CFG_REG != 5.0) && + (TX_PROGDIV_CFG_REG != 8.0) && + (TX_PROGDIV_CFG_REG != 10.0) && + (TX_PROGDIV_CFG_REG != 16.0) && + (TX_PROGDIV_CFG_REG != 16.5) && + (TX_PROGDIV_CFG_REG != 20.0) && + (TX_PROGDIV_CFG_REG != 32.0) && + (TX_PROGDIV_CFG_REG != 33.0) && + (TX_PROGDIV_CFG_REG != 40.0) && + (TX_PROGDIV_CFG_REG != 64.0) && + (TX_PROGDIV_CFG_REG != 66.0) && + (TX_PROGDIV_CFG_REG != 80.0) && + (TX_PROGDIV_CFG_REG != 100.0))) begin + $display("Error: [Unisim %s-716] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_RXDETECT_REF_REG != 3) && + (TX_RXDETECT_REF_REG != 0) && + (TX_RXDETECT_REF_REG != 1) && + (TX_RXDETECT_REF_REG != 2) && + (TX_RXDETECT_REF_REG != 4) && + (TX_RXDETECT_REF_REG != 5) && + (TX_RXDETECT_REF_REG != 6) && + (TX_RXDETECT_REF_REG != 7))) begin + $display("Error: [Unisim %s-719] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 3, 0, 1, 2, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_XCLK_SEL_REG != "TXOUT") && + (TX_XCLK_SEL_REG != "TXUSR"))) begin + $display("Error: [Unisim %s-730] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign PMASCANCLK0_in = 1'b1; // tie off + assign PMASCANCLK1_in = 1'b1; // tie off + assign PMASCANCLK2_in = 1'b1; // tie off + assign PMASCANCLK3_in = 1'b1; // tie off + assign PMASCANCLK4_in = 1'b1; // tie off + assign PMASCANCLK5_in = 1'b1; // tie off + assign SCANCLK_in = 1'b1; // tie off + assign TSTCLK0_in = 1'b1; // tie off + assign TSTCLK1_in = 1'b1; // tie off + + assign PMASCANENB_in = 1'b1; // tie off + assign PMASCANIN_in = 12'b111111111111; // tie off + assign PMASCANMODEB_in = 1'b1; // tie off + assign PMASCANRSTEN_in = 1'b1; // tie off + assign SARCCLK_in = 1'b1; // tie off + assign SCANENB_in = 1'b1; // tie off + assign SCANIN_in = 19'b1111111111111111111; // tie off + assign SCANMODEB_in = 1'b1; // tie off + assign TSTPDOVRDB_in = 1'b1; // tie off + assign TSTPD_in = 5'b11111; // tie off + + SIP_GTYE3_CHANNEL #( + .SIM_MODE (SIM_MODE), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL), + .SIM_VERSION (SIM_VERSION) +) SIP_GTYE3_CHANNEL_INST ( + .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG), + .ACJTAG_MODE (ACJTAG_MODE_REG), + .ACJTAG_RESET (ACJTAG_RESET_REG), + .ADAPT_CFG0 (ADAPT_CFG0_REG), + .ADAPT_CFG1 (ADAPT_CFG1_REG), + .ADAPT_CFG2 (ADAPT_CFG2_REG), + .AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG), + .AEN_CPLL (AEN_CPLL_REG), + .AEN_ELPCAL (AEN_ELPCAL_REG), + .AEN_EYESCAN (AEN_EYESCAN_REG), + .AEN_LOOPBACK (AEN_LOOPBACK_REG), + .AEN_MASTER (AEN_MASTER_REG), + .AEN_MUXDCD (AEN_MUXDCD_REG), + .AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG), + .AEN_POLARITY (AEN_POLARITY_REG), + .AEN_PRBS (AEN_PRBS_REG), + .AEN_RESET (AEN_RESET_REG), + .AEN_RXCDR (AEN_RXCDR_REG), + .AEN_RXDFE (AEN_RXDFE_REG), + .AEN_RXDFELPM (AEN_RXDFELPM_REG), + .AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG), + .AEN_RXPHDLY (AEN_RXPHDLY_REG), + .AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG), + .AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG), + .AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG), + .AEN_TXPHDLY (AEN_TXPHDLY_REG), + .AEN_TXPI_PPM (AEN_TXPI_PPM_REG), + .AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG), + .AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG), + .AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG), + .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG), + .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG), + .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG), + .AMONITOR_CFG (AMONITOR_CFG_REG), + .AUTO_BW_SEL_BYPASS (AUTO_BW_SEL_BYPASS_REG), + .A_AFECFOKEN (A_AFECFOKEN_REG), + .A_CPLLLOCKEN (A_CPLLLOCKEN_REG), + .A_CPLLPD (A_CPLLPD_REG), + .A_CPLLRESET (A_CPLLRESET_REG), + .A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG), + .A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG), + .A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG), + .A_DFECFOKHOLD (A_DFECFOKHOLD_REG), + .A_DFECFOKOVREN (A_DFECFOKOVREN_REG), + .A_ELPCALDVORWREN (A_ELPCALDVORWREN_REG), + .A_ELPCALPAORWREN (A_ELPCALPAORWREN_REG), + .A_EYESCANMODE (A_EYESCANMODE_REG), + .A_EYESCANRESET (A_EYESCANRESET_REG), + .A_GTRESETSEL (A_GTRESETSEL_REG), + .A_GTRXRESET (A_GTRXRESET_REG), + .A_GTTXRESET (A_GTTXRESET_REG), + .A_LOOPBACK (A_LOOPBACK_REG), + .A_LPMGCHOLD (A_LPMGCHOLD_REG), + .A_LPMGCOVREN (A_LPMGCOVREN_REG), + .A_LPMOSHOLD (A_LPMOSHOLD_REG), + .A_LPMOSOVREN (A_LPMOSOVREN_REG), + .A_MUXDCDEXHOLD (A_MUXDCDEXHOLD_REG), + .A_MUXDCDORWREN (A_MUXDCDORWREN_REG), + .A_RXBUFRESET (A_RXBUFRESET_REG), + .A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG), + .A_RXCDRHOLD (A_RXCDRHOLD_REG), + .A_RXCDROVRDEN (A_RXCDROVRDEN_REG), + .A_RXCDRRESET (A_RXCDRRESET_REG), + .A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG), + .A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG), + .A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG), + .A_RXDFELFHOLD (A_RXDFELFHOLD_REG), + .A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG), + .A_RXDFELPMRESET (A_RXDFELPMRESET_REG), + .A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG), + .A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG), + .A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG), + .A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG), + .A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG), + .A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG), + .A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG), + .A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG), + .A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG), + .A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG), + .A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG), + .A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG), + .A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG), + .A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG), + .A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG), + .A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG), + .A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG), + .A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG), + .A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG), + .A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG), + .A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG), + .A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG), + .A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG), + .A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG), + .A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG), + .A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG), + .A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG), + .A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG), + .A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG), + .A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG), + .A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG), + .A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG), + .A_RXDFEVSEN (A_RXDFEVSEN_REG), + .A_RXDFEXYDEN (A_RXDFEXYDEN_REG), + .A_RXDLYBYPASS (A_RXDLYBYPASS_REG), + .A_RXDLYEN (A_RXDLYEN_REG), + .A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG), + .A_RXDLYSRESET (A_RXDLYSRESET_REG), + .A_RXLPMEN (A_RXLPMEN_REG), + .A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG), + .A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG), + .A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG), + .A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG), + .A_RXMONITORSEL (A_RXMONITORSEL_REG), + .A_RXOOBRESET (A_RXOOBRESET_REG), + .A_RXOSCALRESET (A_RXOSCALRESET_REG), + .A_RXOSHOLD (A_RXOSHOLD_REG), + .A_RXOSOVRDEN (A_RXOSOVRDEN_REG), + .A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG), + .A_RXPCSRESET (A_RXPCSRESET_REG), + .A_RXPD (A_RXPD_REG), + .A_RXPHALIGN (A_RXPHALIGN_REG), + .A_RXPHALIGNEN (A_RXPHALIGNEN_REG), + .A_RXPHDLYPD (A_RXPHDLYPD_REG), + .A_RXPHDLYRESET (A_RXPHDLYRESET_REG), + .A_RXPHOVRDEN (A_RXPHOVRDEN_REG), + .A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG), + .A_RXPMARESET (A_RXPMARESET_REG), + .A_RXPOLARITY (A_RXPOLARITY_REG), + .A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG), + .A_RXPRBSSEL (A_RXPRBSSEL_REG), + .A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG), + .A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG), + .A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG), + .A_TXDEEMPH (A_TXDEEMPH_REG), + .A_TXDIFFCTRL (A_TXDIFFCTRL_REG), + .A_TXDLYBYPASS (A_TXDLYBYPASS_REG), + .A_TXDLYEN (A_TXDLYEN_REG), + .A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG), + .A_TXDLYSRESET (A_TXDLYSRESET_REG), + .A_TXELECIDLE (A_TXELECIDLE_REG), + .A_TXINHIBIT (A_TXINHIBIT_REG), + .A_TXMAINCURSOR (A_TXMAINCURSOR_REG), + .A_TXMARGIN (A_TXMARGIN_REG), + .A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG), + .A_TXPCSRESET (A_TXPCSRESET_REG), + .A_TXPD (A_TXPD_REG), + .A_TXPHALIGN (A_TXPHALIGN_REG), + .A_TXPHALIGNEN (A_TXPHALIGNEN_REG), + .A_TXPHDLYPD (A_TXPHDLYPD_REG), + .A_TXPHDLYRESET (A_TXPHDLYRESET_REG), + .A_TXPHINIT (A_TXPHINIT_REG), + .A_TXPHOVRDEN (A_TXPHOVRDEN_REG), + .A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG), + .A_TXPIPPMPD (A_TXPIPPMPD_REG), + .A_TXPIPPMSEL (A_TXPIPPMSEL_REG), + .A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG), + .A_TXPMARESET (A_TXPMARESET_REG), + .A_TXPOLARITY (A_TXPOLARITY_REG), + .A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG), + .A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG), + .A_TXPRBSSEL (A_TXPRBSSEL_REG), + .A_TXPRECURSOR (A_TXPRECURSOR_REG), + .A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG), + .A_TXSWING (A_TXSWING_REG), + .A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG), + .CAPBYPASS_FORCE (CAPBYPASS_FORCE_REG), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG), + .CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG), + .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG), + .CH_HSPMUX (CH_HSPMUX_REG), + .CKCAL1_CFG_0 (CKCAL1_CFG_0_REG), + .CKCAL1_CFG_1 (CKCAL1_CFG_1_REG), + .CKCAL1_CFG_2 (CKCAL1_CFG_2_REG), + .CKCAL1_CFG_3 (CKCAL1_CFG_3_REG), + .CKCAL2_CFG_0 (CKCAL2_CFG_0_REG), + .CKCAL2_CFG_1 (CKCAL2_CFG_1_REG), + .CKCAL2_CFG_2 (CKCAL2_CFG_2_REG), + .CKCAL2_CFG_3 (CKCAL2_CFG_3_REG), + .CKCAL2_CFG_4 (CKCAL2_CFG_4_REG), + .CKCAL_RSVD0 (CKCAL_RSVD0_REG), + .CKCAL_RSVD1 (CKCAL_RSVD1_REG), + .CLK_CORRECT_USE (CLK_CORRECT_USE_REG), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG), + .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG), + .CPLL_CFG0 (CPLL_CFG0_REG), + .CPLL_CFG1 (CPLL_CFG1_REG), + .CPLL_CFG2 (CPLL_CFG2_REG), + .CPLL_CFG3 (CPLL_CFG3_REG), + .CPLL_FBDIV (CPLL_FBDIV_REG), + .CPLL_FBDIV_45 (CPLL_FBDIV_45_REG), + .CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG), + .CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG), + .CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG), + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG), + .CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG), + .CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG), + .DDI_CTRL (DDI_CTRL_REG), + .DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG), + .DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG), + .DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG), + .DMONITOR_CFG0 (DMONITOR_CFG0_REG), + .DMONITOR_CFG1 (DMONITOR_CFG1_REG), + .ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG), + .ES_CONTROL (ES_CONTROL_REG), + .ES_ERRDET_EN (ES_ERRDET_EN_REG), + .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG), + .ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG), + .ES_PMA_CFG (ES_PMA_CFG_REG), + .ES_PRESCALE (ES_PRESCALE_REG), + .ES_QUALIFIER0 (ES_QUALIFIER0_REG), + .ES_QUALIFIER1 (ES_QUALIFIER1_REG), + .ES_QUALIFIER2 (ES_QUALIFIER2_REG), + .ES_QUALIFIER3 (ES_QUALIFIER3_REG), + .ES_QUALIFIER4 (ES_QUALIFIER4_REG), + .ES_QUALIFIER5 (ES_QUALIFIER5_REG), + .ES_QUALIFIER6 (ES_QUALIFIER6_REG), + .ES_QUALIFIER7 (ES_QUALIFIER7_REG), + .ES_QUALIFIER8 (ES_QUALIFIER8_REG), + .ES_QUALIFIER9 (ES_QUALIFIER9_REG), + .ES_QUAL_MASK0 (ES_QUAL_MASK0_REG), + .ES_QUAL_MASK1 (ES_QUAL_MASK1_REG), + .ES_QUAL_MASK2 (ES_QUAL_MASK2_REG), + .ES_QUAL_MASK3 (ES_QUAL_MASK3_REG), + .ES_QUAL_MASK4 (ES_QUAL_MASK4_REG), + .ES_QUAL_MASK5 (ES_QUAL_MASK5_REG), + .ES_QUAL_MASK6 (ES_QUAL_MASK6_REG), + .ES_QUAL_MASK7 (ES_QUAL_MASK7_REG), + .ES_QUAL_MASK8 (ES_QUAL_MASK8_REG), + .ES_QUAL_MASK9 (ES_QUAL_MASK9_REG), + .ES_SDATA_MASK0 (ES_SDATA_MASK0_REG), + .ES_SDATA_MASK1 (ES_SDATA_MASK1_REG), + .ES_SDATA_MASK2 (ES_SDATA_MASK2_REG), + .ES_SDATA_MASK3 (ES_SDATA_MASK3_REG), + .ES_SDATA_MASK4 (ES_SDATA_MASK4_REG), + .ES_SDATA_MASK5 (ES_SDATA_MASK5_REG), + .ES_SDATA_MASK6 (ES_SDATA_MASK6_REG), + .ES_SDATA_MASK7 (ES_SDATA_MASK7_REG), + .ES_SDATA_MASK8 (ES_SDATA_MASK8_REG), + .ES_SDATA_MASK9 (ES_SDATA_MASK9_REG), + .EVODD_PHI_CFG (EVODD_PHI_CFG_REG), + .EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG), + .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG), + .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG), + .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG), + .GEARBOX_MODE (GEARBOX_MODE_REG), + .GEN_RXUSRCLK (GEN_RXUSRCLK_REG), + .GEN_TXUSRCLK (GEN_TXUSRCLK_REG), + .GM_BIAS_SELECT (GM_BIAS_SELECT_REG), + .GT_INSTANTIATED (GT_INSTANTIATED_REG), + .ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG), + .LOCAL_MASTER (LOCAL_MASTER_REG), + .LOOP0_CFG (LOOP0_CFG_REG), + .LOOP10_CFG (LOOP10_CFG_REG), + .LOOP11_CFG (LOOP11_CFG_REG), + .LOOP12_CFG (LOOP12_CFG_REG), + .LOOP13_CFG (LOOP13_CFG_REG), + .LOOP1_CFG (LOOP1_CFG_REG), + .LOOP2_CFG (LOOP2_CFG_REG), + .LOOP3_CFG (LOOP3_CFG_REG), + .LOOP4_CFG (LOOP4_CFG_REG), + .LOOP5_CFG (LOOP5_CFG_REG), + .LOOP6_CFG (LOOP6_CFG_REG), + .LOOP7_CFG (LOOP7_CFG_REG), + .LOOP8_CFG (LOOP8_CFG_REG), + .LOOP9_CFG (LOOP9_CFG_REG), + .LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG), + .LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG), + .LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG), + .LPBK_RG_CTRL (LPBK_RG_CTRL_REG), + .OOBDIVCTL (OOBDIVCTL_REG), + .OOB_PWRUP (OOB_PWRUP_REG), + .PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG), + .PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG), + .PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG), + .PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG), + .PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG), + .PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG), + .PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG), + .PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG), + .PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG), + .PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG), + .PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG), + .PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG), + .PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG), + .PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG), + .PCS_PCIE_EN (PCS_PCIE_EN_REG), + .PCS_RSVD0 (PCS_RSVD0_REG), + .PCS_RSVD1 (PCS_RSVD1_REG), + .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG), + .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG), + .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG), + .PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG), + .PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG), + .PMA_RSV0 (PMA_RSV0_REG), + .PMA_RSV1 (PMA_RSV1_REG), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG), + .PROCESS_PAR (PROCESS_PAR_REG), + .RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG), + .RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG), + .RXBUFRESET_TIME (RXBUFRESET_TIME_REG), + .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG), + .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG), + .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG), + .RXBUF_EN (RXBUF_EN_REG), + .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG), + .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG), + .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG), + .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG), + .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG), + .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG), + .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG), + .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG), + .RXCDR_CFG0 (RXCDR_CFG0_REG), + .RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG), + .RXCDR_CFG1 (RXCDR_CFG1_REG), + .RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG), + .RXCDR_CFG2 (RXCDR_CFG2_REG), + .RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG), + .RXCDR_CFG3 (RXCDR_CFG3_REG), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG), + .RXCDR_CFG4 (RXCDR_CFG4_REG), + .RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG), + .RXCDR_CFG5 (RXCDR_CFG5_REG), + .RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG), + .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG), + .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG), + .RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG), + .RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG), + .RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG), + .RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG), + .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG), + .RXCFOKDONE_SRC (RXCFOKDONE_SRC_REG), + .RXCFOK_CFG0 (RXCFOK_CFG0_REG), + .RXCFOK_CFG1 (RXCFOK_CFG1_REG), + .RXCFOK_CFG2 (RXCFOK_CFG2_REG), + .RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG), + .RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG), + .RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG), + .RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG), + .RXDFE_CFG0 (RXDFE_CFG0_REG), + .RXDFE_CFG1 (RXDFE_CFG1_REG), + .RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG), + .RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG), + .RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG), + .RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG), + .RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG), + .RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG), + .RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG), + .RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG), + .RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG), + .RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG), + .RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG), + .RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG), + .RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG), + .RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG), + .RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG), + .RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG), + .RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG), + .RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG), + .RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG), + .RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG), + .RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG), + .RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG), + .RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG), + .RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG), + .RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG), + .RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG), + .RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG), + .RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG), + .RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG), + .RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG), + .RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG), + .RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG), + .RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG), + .RXDFE_PWR_SAVING (RXDFE_PWR_SAVING_REG), + .RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG), + .RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG), + .RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG), + .RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG), + .RXDLY_CFG (RXDLY_CFG_REG), + .RXDLY_LCFG (RXDLY_LCFG_REG), + .RXELECIDLE_CFG (RXELECIDLE_CFG_REG), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG), + .RXGEARBOX_EN (RXGEARBOX_EN_REG), + .RXISCANRESET_TIME (RXISCANRESET_TIME_REG), + .RXLPM_CFG (RXLPM_CFG_REG), + .RXLPM_GC_CFG (RXLPM_GC_CFG_REG), + .RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG), + .RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG), + .RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG), + .RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG), + .RXOOB_CFG (RXOOB_CFG_REG), + .RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG), + .RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG), + .RXOUT_DIV (RXOUT_DIV_REG), + .RXPCSRESET_TIME (RXPCSRESET_TIME_REG), + .RXPHBEACON_CFG (RXPHBEACON_CFG_REG), + .RXPHDLY_CFG (RXPHDLY_CFG_REG), + .RXPHSAMP_CFG (RXPHSAMP_CFG_REG), + .RXPHSLIP_CFG (RXPHSLIP_CFG_REG), + .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG), + .RXPI_AUTO_BW_SEL_BYPASS (RXPI_AUTO_BW_SEL_BYPASS_REG), + .RXPI_CFG (RXPI_CFG_REG), + .RXPI_LPM (RXPI_LPM_REG), + .RXPI_RSV0 (RXPI_RSV0_REG), + .RXPI_SEL_LC (RXPI_SEL_LC_REG), + .RXPI_STARTCODE (RXPI_STARTCODE_REG), + .RXPI_VREFSEL (RXPI_VREFSEL_REG), + .RXPLL_SEL (RXPLL_SEL_REG), + .RXPMACLK_SEL (RXPMACLK_SEL_REG), + .RXPMARESET_TIME (RXPMARESET_TIME_REG), + .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG), + .RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG), + .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG), + .RXSLIDE_MODE (RXSLIDE_MODE_REG), + .RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG), + .RXSYNC_OVRD (RXSYNC_OVRD_REG), + .RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG), + .RX_AFE_CM_EN (RX_AFE_CM_EN_REG), + .RX_BIAS_CFG0 (RX_BIAS_CFG0_REG), + .RX_BUFFER_CFG (RX_BUFFER_CFG_REG), + .RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG), + .RX_CLK25_DIV (RX_CLK25_DIV_REG), + .RX_CLKMUX_EN (RX_CLKMUX_EN_REG), + .RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG), + .RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG), + .RX_CM_BUF_PD (RX_CM_BUF_PD_REG), + .RX_CM_SEL (RX_CM_SEL_REG), + .RX_CM_TRIM (RX_CM_TRIM_REG), + .RX_CTLE1_KHKL (RX_CTLE1_KHKL_REG), + .RX_CTLE2_KHKL (RX_CTLE2_KHKL_REG), + .RX_CTLE3_AGC (RX_CTLE3_AGC_REG), + .RX_DATA_WIDTH (RX_DATA_WIDTH_REG), + .RX_DDI_SEL (RX_DDI_SEL_REG), + .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG), + .RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG), + .RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG), + .RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG), + .RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG), + .RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG), + .RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG), + .RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG), + .RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG), + .RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG), + .RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG), + .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG), + .RX_DIV2_MODE_B (RX_DIV2_MODE_B_REG), + .RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG), + .RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG), + .RX_EN_HI_LR (RX_EN_HI_LR_REG), + .RX_EXT_RL_CTRL (RX_EXT_RL_CTRL_REG), + .RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG), + .RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG), + .RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG), + .RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG), + .RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG), + .RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG), + .RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN), + .RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG), + .RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG), + .RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG), + .RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG), + .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG), + .RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG), + .RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG), + .RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG), + .RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG), + .RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG), + .RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG), + .RX_VREG_CTRL (RX_VREG_CTRL_REG), + .RX_VREG_PDB (RX_VREG_PDB_REG), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG), + .RX_XCLK_SEL (RX_XCLK_SEL_REG), + .RX_XMODE_SEL (RX_XMODE_SEL_REG), + .SAS_MAX_COM (SAS_MAX_COM_REG), + .SAS_MIN_COM (SAS_MIN_COM_REG), + .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG), + .SATA_BURST_VAL (SATA_BURST_VAL_REG), + .SATA_CPLL_CFG (SATA_CPLL_CFG_REG), + .SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG), + .SATA_MAX_BURST (SATA_MAX_BURST_REG), + .SATA_MAX_INIT (SATA_MAX_INIT_REG), + .SATA_MAX_WAKE (SATA_MAX_WAKE_REG), + .SATA_MIN_BURST (SATA_MIN_BURST_REG), + .SATA_MIN_INIT (SATA_MIN_INIT_REG), + .SATA_MIN_WAKE (SATA_MIN_WAKE_REG), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG), + .TAPDLY_SET_TX (TAPDLY_SET_TX_REG), + .TEMPERATURE_PAR (TEMPERATURE_PAR_REG), + .TERM_RCAL_CFG (TERM_RCAL_CFG_REG), + .TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG), + .TRANS_TIME_RATE (TRANS_TIME_RATE_REG), + .TST_RSV0 (TST_RSV0_REG), + .TST_RSV1 (TST_RSV1_REG), + .TXBUF_EN (TXBUF_EN_REG), + .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG), + .TXDLY_CFG (TXDLY_CFG_REG), + .TXDLY_LCFG (TXDLY_LCFG_REG), + .TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG), + .TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG), + .TXGEARBOX_EN (TXGEARBOX_EN_REG), + .TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG), + .TXOUT_DIV (TXOUT_DIV_REG), + .TXPCSRESET_TIME (TXPCSRESET_TIME_REG), + .TXPHDLY_CFG0 (TXPHDLY_CFG0_REG), + .TXPHDLY_CFG1 (TXPHDLY_CFG1_REG), + .TXPH_CFG (TXPH_CFG_REG), + .TXPH_CFG2 (TXPH_CFG2_REG), + .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG), + .TXPI_CFG0 (TXPI_CFG0_REG), + .TXPI_CFG1 (TXPI_CFG1_REG), + .TXPI_CFG2 (TXPI_CFG2_REG), + .TXPI_CFG3 (TXPI_CFG3_REG), + .TXPI_CFG4 (TXPI_CFG4_REG), + .TXPI_CFG5 (TXPI_CFG5_REG), + .TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG), + .TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG), + .TXPI_LPM (TXPI_LPM_REG), + .TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG), + .TXPI_PPM_CFG (TXPI_PPM_CFG_REG), + .TXPI_RSV0 (TXPI_RSV0_REG), + .TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG), + .TXPI_VREFSEL (TXPI_VREFSEL_REG), + .TXPMARESET_TIME (TXPMARESET_TIME_REG), + .TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG), + .TXSYNC_OVRD (TXSYNC_OVRD_REG), + .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG), + .TX_CLK25_DIV (TX_CLK25_DIV_REG), + .TX_CLKMUX_EN (TX_CLKMUX_EN_REG), + .TX_CLKREG_PDB (TX_CLKREG_PDB_REG), + .TX_CLKREG_SET (TX_CLKREG_SET_REG), + .TX_DATA_WIDTH (TX_DATA_WIDTH_REG), + .TX_DCD_CFG (TX_DCD_CFG_REG), + .TX_DCD_EN (TX_DCD_EN_REG), + .TX_DEEMPH0 (TX_DEEMPH0_REG), + .TX_DEEMPH1 (TX_DEEMPH1_REG), + .TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG), + .TX_DRIVE_MODE (TX_DRIVE_MODE_REG), + .TX_DRVMUX_CTRL (TX_DRVMUX_CTRL_REG), + .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG), + .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG), + .TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG), + .TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG), + .TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG), + .TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG), + .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG), + .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG), + .TX_MODE_SEL (TX_MODE_SEL_REG), + .TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG), + .TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG), + .TX_PHICAL_CFG2 (TX_PHICAL_CFG2_REG), + .TX_PI_BIASSET (TX_PI_BIASSET_REG), + .TX_PI_CFG0 (TX_PI_CFG0_REG), + .TX_PI_CFG1 (TX_PI_CFG1_REG), + .TX_PI_DIV2_MODE_B (TX_PI_DIV2_MODE_B_REG), + .TX_PI_SEL_QPLL0 (TX_PI_SEL_QPLL0_REG), + .TX_PI_SEL_QPLL1 (TX_PI_SEL_QPLL1_REG), + .TX_PMADATA_OPT (TX_PMADATA_OPT_REG), + .TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG), + .TX_PREDRV_CTRL (TX_PREDRV_CTRL_REG), + .TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG), + .TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN), + .TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG), + .TX_RXDETECT_REF (TX_RXDETECT_REF_REG), + .TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG), + .TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG), + .TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG), + .TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG), + .TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG), + .TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG), + .TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG), + .TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG), + .TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG), + .TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG), + .TX_XCLK_SEL (TX_XCLK_SEL_REG), + .USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG), + .BUFGTCE (BUFGTCE_out), + .BUFGTCEMASK (BUFGTCEMASK_out), + .BUFGTDIV (BUFGTDIV_out), + .BUFGTRESET (BUFGTRESET_out), + .BUFGTRSTMASK (BUFGTRSTMASK_out), + .CPLLFBCLKLOST (CPLLFBCLKLOST_out), + .CPLLLOCK (CPLLLOCK_out), + .CPLLREFCLKLOST (CPLLREFCLKLOST_out), + .DMONITOROUT (DMONITOROUT_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .EYESCANDATAERROR (EYESCANDATAERROR_out), + .GTPOWERGOOD (GTPOWERGOOD_out), + .GTREFCLKMONITOR (GTREFCLKMONITOR_out), + .GTYTXN (GTYTXN_out), + .GTYTXP (GTYTXP_out), + .PCIERATEGEN3 (PCIERATEGEN3_out), + .PCIERATEIDLE (PCIERATEIDLE_out), + .PCIERATEQPLLPD (PCIERATEQPLLPD_out), + .PCIERATEQPLLRESET (PCIERATEQPLLRESET_out), + .PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out), + .PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out), + .PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out), + .PCIEUSERRATESTART (PCIEUSERRATESTART_out), + .PCSRSVDOUT (PCSRSVDOUT_out), + .PHYSTATUS (PHYSTATUS_out), + .PINRSRVDAS (PINRSRVDAS_out), + .PMASCANOUT (PMASCANOUT_out), + .RESETEXCEPTION (RESETEXCEPTION_out), + .RXBUFSTATUS (RXBUFSTATUS_out), + .RXBYTEISALIGNED (RXBYTEISALIGNED_out), + .RXBYTEREALIGN (RXBYTEREALIGN_out), + .RXCDRLOCK (RXCDRLOCK_out), + .RXCDRPHDONE (RXCDRPHDONE_out), + .RXCHANBONDSEQ (RXCHANBONDSEQ_out), + .RXCHANISALIGNED (RXCHANISALIGNED_out), + .RXCHANREALIGN (RXCHANREALIGN_out), + .RXCHBONDO (RXCHBONDO_out), + .RXCKCALDONE (RXCKCALDONE_out), + .RXCLKCORCNT (RXCLKCORCNT_out), + .RXCOMINITDET (RXCOMINITDET_out), + .RXCOMMADET (RXCOMMADET_out), + .RXCOMSASDET (RXCOMSASDET_out), + .RXCOMWAKEDET (RXCOMWAKEDET_out), + .RXCTRL0 (RXCTRL0_out), + .RXCTRL1 (RXCTRL1_out), + .RXCTRL2 (RXCTRL2_out), + .RXCTRL3 (RXCTRL3_out), + .RXDATA (RXDATA_out), + .RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out), + .RXDATAVALID (RXDATAVALID_out), + .RXDLYSRESETDONE (RXDLYSRESETDONE_out), + .RXELECIDLE (RXELECIDLE_out), + .RXHEADER (RXHEADER_out), + .RXHEADERVALID (RXHEADERVALID_out), + .RXMONITOROUT (RXMONITOROUT_out), + .RXOSINTDONE (RXOSINTDONE_out), + .RXOSINTSTARTED (RXOSINTSTARTED_out), + .RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out), + .RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out), + .RXOUTCLK (RXOUTCLK_out), + .RXOUTCLKFABRIC (RXOUTCLKFABRIC_out), + .RXOUTCLKPCS (RXOUTCLKPCS_out), + .RXPHALIGNDONE (RXPHALIGNDONE_out), + .RXPHALIGNERR (RXPHALIGNERR_out), + .RXPMARESETDONE (RXPMARESETDONE_out), + .RXPRBSERR (RXPRBSERR_out), + .RXPRBSLOCKED (RXPRBSLOCKED_out), + .RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out), + .RXRATEDONE (RXRATEDONE_out), + .RXRECCLKOUT (RXRECCLKOUT_out), + .RXRESETDONE (RXRESETDONE_out), + .RXSLIDERDY (RXSLIDERDY_out), + .RXSLIPDONE (RXSLIPDONE_out), + .RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out), + .RXSLIPPMARDY (RXSLIPPMARDY_out), + .RXSTARTOFSEQ (RXSTARTOFSEQ_out), + .RXSTATUS (RXSTATUS_out), + .RXSYNCDONE (RXSYNCDONE_out), + .RXSYNCOUT (RXSYNCOUT_out), + .RXVALID (RXVALID_out), + .SCANOUT (SCANOUT_out), + .TXBUFSTATUS (TXBUFSTATUS_out), + .TXCOMFINISH (TXCOMFINISH_out), + .TXDCCDONE (TXDCCDONE_out), + .TXDLYSRESETDONE (TXDLYSRESETDONE_out), + .TXOUTCLK (TXOUTCLK_out), + .TXOUTCLKFABRIC (TXOUTCLKFABRIC_out), + .TXOUTCLKPCS (TXOUTCLKPCS_out), + .TXPHALIGNDONE (TXPHALIGNDONE_out), + .TXPHINITDONE (TXPHINITDONE_out), + .TXPMARESETDONE (TXPMARESETDONE_out), + .TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out), + .TXRATEDONE (TXRATEDONE_out), + .TXRESETDONE (TXRESETDONE_out), + .TXSYNCDONE (TXSYNCDONE_out), + .TXSYNCOUT (TXSYNCOUT_out), + .CDRSTEPDIR (CDRSTEPDIR_in), + .CDRSTEPSQ (CDRSTEPSQ_in), + .CDRSTEPSX (CDRSTEPSX_in), + .CFGRESET (CFGRESET_in), + .CLKRSVD0 (CLKRSVD0_in), + .CLKRSVD1 (CLKRSVD1_in), + .CPLLLOCKDETCLK (CPLLLOCKDETCLK_in), + .CPLLLOCKEN (CPLLLOCKEN_in), + .CPLLPD (CPLLPD_in), + .CPLLREFCLKSEL (CPLLREFCLKSEL_in), + .CPLLRESET (CPLLRESET_in), + .DMONFIFORESET (DMONFIFORESET_in), + .DMONITORCLK (DMONITORCLK_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .ELPCALDVORWREN (ELPCALDVORWREN_in), + .ELPCALPAORWREN (ELPCALPAORWREN_in), + .EVODDPHICALDONE (EVODDPHICALDONE_in), + .EVODDPHICALSTART (EVODDPHICALSTART_in), + .EVODDPHIDRDEN (EVODDPHIDRDEN_in), + .EVODDPHIDWREN (EVODDPHIDWREN_in), + .EVODDPHIXRDEN (EVODDPHIXRDEN_in), + .EVODDPHIXWREN (EVODDPHIXWREN_in), + .EYESCANMODE (EYESCANMODE_in), + .EYESCANRESET (EYESCANRESET_in), + .EYESCANTRIGGER (EYESCANTRIGGER_in), + .GTGREFCLK (GTGREFCLK_in), + .GTNORTHREFCLK0 (GTNORTHREFCLK0_in), + .GTNORTHREFCLK1 (GTNORTHREFCLK1_in), + .GTREFCLK0 (GTREFCLK0_in), + .GTREFCLK1 (GTREFCLK1_in), + .GTRESETSEL (GTRESETSEL_in), + .GTRSVD (GTRSVD_in), + .GTRXRESET (GTRXRESET_in), + .GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in), + .GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in), + .GTTXRESET (GTTXRESET_in), + .GTYRXN (GTYRXN_in), + .GTYRXP (GTYRXP_in), + .LOOPBACK (LOOPBACK_in), + .LOOPRSVD (LOOPRSVD_in), + .LPBKRXTXSEREN (LPBKRXTXSEREN_in), + .LPBKTXRXSEREN (LPBKTXRXSEREN_in), + .PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in), + .PCIERSTIDLE (PCIERSTIDLE_in), + .PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in), + .PCIEUSERRATEDONE (PCIEUSERRATEDONE_in), + .PCSRSVDIN (PCSRSVDIN_in), + .PCSRSVDIN2 (PCSRSVDIN2_in), + .PMARSVDIN (PMARSVDIN_in), + .PMASCANCLK0 (PMASCANCLK0_in), + .PMASCANCLK1 (PMASCANCLK1_in), + .PMASCANCLK2 (PMASCANCLK2_in), + .PMASCANCLK3 (PMASCANCLK3_in), + .PMASCANCLK4 (PMASCANCLK4_in), + .PMASCANCLK5 (PMASCANCLK5_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .PMASCANMODEB (PMASCANMODEB_in), + .PMASCANRSTEN (PMASCANRSTEN_in), + .QPLL0CLK (QPLL0CLK_in), + .QPLL0REFCLK (QPLL0REFCLK_in), + .QPLL1CLK (QPLL1CLK_in), + .QPLL1REFCLK (QPLL1REFCLK_in), + .RESETOVRD (RESETOVRD_in), + .RSTCLKENTX (RSTCLKENTX_in), + .RX8B10BEN (RX8B10BEN_in), + .RXBUFRESET (RXBUFRESET_in), + .RXCDRFREQRESET (RXCDRFREQRESET_in), + .RXCDRHOLD (RXCDRHOLD_in), + .RXCDROVRDEN (RXCDROVRDEN_in), + .RXCDRRESET (RXCDRRESET_in), + .RXCDRRESETRSV (RXCDRRESETRSV_in), + .RXCHBONDEN (RXCHBONDEN_in), + .RXCHBONDI (RXCHBONDI_in), + .RXCHBONDLEVEL (RXCHBONDLEVEL_in), + .RXCHBONDMASTER (RXCHBONDMASTER_in), + .RXCHBONDSLAVE (RXCHBONDSLAVE_in), + .RXCKCALRESET (RXCKCALRESET_in), + .RXCOMMADETEN (RXCOMMADETEN_in), + .RXDCCFORCESTART (RXDCCFORCESTART_in), + .RXDFEAGCHOLD (RXDFEAGCHOLD_in), + .RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in), + .RXDFELFHOLD (RXDFELFHOLD_in), + .RXDFELFOVRDEN (RXDFELFOVRDEN_in), + .RXDFELPMRESET (RXDFELPMRESET_in), + .RXDFETAP10HOLD (RXDFETAP10HOLD_in), + .RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in), + .RXDFETAP11HOLD (RXDFETAP11HOLD_in), + .RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in), + .RXDFETAP12HOLD (RXDFETAP12HOLD_in), + .RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in), + .RXDFETAP13HOLD (RXDFETAP13HOLD_in), + .RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in), + .RXDFETAP14HOLD (RXDFETAP14HOLD_in), + .RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in), + .RXDFETAP15HOLD (RXDFETAP15HOLD_in), + .RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in), + .RXDFETAP2HOLD (RXDFETAP2HOLD_in), + .RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in), + .RXDFETAP3HOLD (RXDFETAP3HOLD_in), + .RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in), + .RXDFETAP4HOLD (RXDFETAP4HOLD_in), + .RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in), + .RXDFETAP5HOLD (RXDFETAP5HOLD_in), + .RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in), + .RXDFETAP6HOLD (RXDFETAP6HOLD_in), + .RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in), + .RXDFETAP7HOLD (RXDFETAP7HOLD_in), + .RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in), + .RXDFETAP8HOLD (RXDFETAP8HOLD_in), + .RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in), + .RXDFETAP9HOLD (RXDFETAP9HOLD_in), + .RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in), + .RXDFEUTHOLD (RXDFEUTHOLD_in), + .RXDFEUTOVRDEN (RXDFEUTOVRDEN_in), + .RXDFEVPHOLD (RXDFEVPHOLD_in), + .RXDFEVPOVRDEN (RXDFEVPOVRDEN_in), + .RXDFEVSEN (RXDFEVSEN_in), + .RXDFEXYDEN (RXDFEXYDEN_in), + .RXDLYBYPASS (RXDLYBYPASS_in), + .RXDLYEN (RXDLYEN_in), + .RXDLYOVRDEN (RXDLYOVRDEN_in), + .RXDLYSRESET (RXDLYSRESET_in), + .RXELECIDLEMODE (RXELECIDLEMODE_in), + .RXGEARBOXSLIP (RXGEARBOXSLIP_in), + .RXLATCLK (RXLATCLK_in), + .RXLPMEN (RXLPMEN_in), + .RXLPMGCHOLD (RXLPMGCHOLD_in), + .RXLPMGCOVRDEN (RXLPMGCOVRDEN_in), + .RXLPMHFHOLD (RXLPMHFHOLD_in), + .RXLPMHFOVRDEN (RXLPMHFOVRDEN_in), + .RXLPMLFHOLD (RXLPMLFHOLD_in), + .RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in), + .RXLPMOSHOLD (RXLPMOSHOLD_in), + .RXLPMOSOVRDEN (RXLPMOSOVRDEN_in), + .RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in), + .RXMONITORSEL (RXMONITORSEL_in), + .RXOOBRESET (RXOOBRESET_in), + .RXOSCALRESET (RXOSCALRESET_in), + .RXOSHOLD (RXOSHOLD_in), + .RXOSINTCFG (RXOSINTCFG_in), + .RXOSINTEN (RXOSINTEN_in), + .RXOSINTHOLD (RXOSINTHOLD_in), + .RXOSINTOVRDEN (RXOSINTOVRDEN_in), + .RXOSINTSTROBE (RXOSINTSTROBE_in), + .RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in), + .RXOSOVRDEN (RXOSOVRDEN_in), + .RXOUTCLKSEL (RXOUTCLKSEL_in), + .RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in), + .RXPCSRESET (RXPCSRESET_in), + .RXPD (RXPD_in), + .RXPHALIGN (RXPHALIGN_in), + .RXPHALIGNEN (RXPHALIGNEN_in), + .RXPHDLYPD (RXPHDLYPD_in), + .RXPHDLYRESET (RXPHDLYRESET_in), + .RXPHOVRDEN (RXPHOVRDEN_in), + .RXPLLCLKSEL (RXPLLCLKSEL_in), + .RXPMARESET (RXPMARESET_in), + .RXPOLARITY (RXPOLARITY_in), + .RXPRBSCNTRESET (RXPRBSCNTRESET_in), + .RXPRBSSEL (RXPRBSSEL_in), + .RXPROGDIVRESET (RXPROGDIVRESET_in), + .RXRATE (RXRATE_in), + .RXRATEMODE (RXRATEMODE_in), + .RXSLIDE (RXSLIDE_in), + .RXSLIPOUTCLK (RXSLIPOUTCLK_in), + .RXSLIPPMA (RXSLIPPMA_in), + .RXSYNCALLIN (RXSYNCALLIN_in), + .RXSYNCIN (RXSYNCIN_in), + .RXSYNCMODE (RXSYNCMODE_in), + .RXSYSCLKSEL (RXSYSCLKSEL_in), + .RXUSERRDY (RXUSERRDY_in), + .RXUSRCLK (RXUSRCLK_in), + .RXUSRCLK2 (RXUSRCLK2_in), + .SARCCLK (SARCCLK_in), + .SCANCLK (SCANCLK_in), + .SCANENB (SCANENB_in), + .SCANIN (SCANIN_in), + .SCANMODEB (SCANMODEB_in), + .SIGVALIDCLK (SIGVALIDCLK_in), + .TSTCLK0 (TSTCLK0_in), + .TSTCLK1 (TSTCLK1_in), + .TSTIN (TSTIN_in), + .TSTPD (TSTPD_in), + .TSTPDOVRDB (TSTPDOVRDB_in), + .TX8B10BBYPASS (TX8B10BBYPASS_in), + .TX8B10BEN (TX8B10BEN_in), + .TXBUFDIFFCTRL (TXBUFDIFFCTRL_in), + .TXCOMINIT (TXCOMINIT_in), + .TXCOMSAS (TXCOMSAS_in), + .TXCOMWAKE (TXCOMWAKE_in), + .TXCTRL0 (TXCTRL0_in), + .TXCTRL1 (TXCTRL1_in), + .TXCTRL2 (TXCTRL2_in), + .TXDATA (TXDATA_in), + .TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in), + .TXDCCFORCESTART (TXDCCFORCESTART_in), + .TXDCCRESET (TXDCCRESET_in), + .TXDEEMPH (TXDEEMPH_in), + .TXDETECTRX (TXDETECTRX_in), + .TXDIFFCTRL (TXDIFFCTRL_in), + .TXDIFFPD (TXDIFFPD_in), + .TXDLYBYPASS (TXDLYBYPASS_in), + .TXDLYEN (TXDLYEN_in), + .TXDLYHOLD (TXDLYHOLD_in), + .TXDLYOVRDEN (TXDLYOVRDEN_in), + .TXDLYSRESET (TXDLYSRESET_in), + .TXDLYUPDOWN (TXDLYUPDOWN_in), + .TXELECIDLE (TXELECIDLE_in), + .TXELFORCESTART (TXELFORCESTART_in), + .TXHEADER (TXHEADER_in), + .TXINHIBIT (TXINHIBIT_in), + .TXLATCLK (TXLATCLK_in), + .TXMAINCURSOR (TXMAINCURSOR_in), + .TXMARGIN (TXMARGIN_in), + .TXOUTCLKSEL (TXOUTCLKSEL_in), + .TXPCSRESET (TXPCSRESET_in), + .TXPD (TXPD_in), + .TXPDELECIDLEMODE (TXPDELECIDLEMODE_in), + .TXPHALIGN (TXPHALIGN_in), + .TXPHALIGNEN (TXPHALIGNEN_in), + .TXPHDLYPD (TXPHDLYPD_in), + .TXPHDLYRESET (TXPHDLYRESET_in), + .TXPHDLYTSTCLK (TXPHDLYTSTCLK_in), + .TXPHINIT (TXPHINIT_in), + .TXPHOVRDEN (TXPHOVRDEN_in), + .TXPIPPMEN (TXPIPPMEN_in), + .TXPIPPMOVRDEN (TXPIPPMOVRDEN_in), + .TXPIPPMPD (TXPIPPMPD_in), + .TXPIPPMSEL (TXPIPPMSEL_in), + .TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in), + .TXPISOPD (TXPISOPD_in), + .TXPLLCLKSEL (TXPLLCLKSEL_in), + .TXPMARESET (TXPMARESET_in), + .TXPOLARITY (TXPOLARITY_in), + .TXPOSTCURSOR (TXPOSTCURSOR_in), + .TXPRBSFORCEERR (TXPRBSFORCEERR_in), + .TXPRBSSEL (TXPRBSSEL_in), + .TXPRECURSOR (TXPRECURSOR_in), + .TXPROGDIVRESET (TXPROGDIVRESET_in), + .TXRATE (TXRATE_in), + .TXRATEMODE (TXRATEMODE_in), + .TXSEQUENCE (TXSEQUENCE_in), + .TXSWING (TXSWING_in), + .TXSYNCALLIN (TXSYNCALLIN_in), + .TXSYNCIN (TXSYNCIN_in), + .TXSYNCMODE (TXSYNCMODE_in), + .TXSYSCLKSEL (TXSYSCLKSEL_in), + .TXUSERRDY (TXUSERRDY_in), + .TXUSRCLK (TXUSRCLK_in), + .TXUSRCLK2 (TXUSRCLK2_in), + .GSR (glblGSR) + ); + + specify + (DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTGREFCLK => RXCDRPHDONE) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLK) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTGREFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXCDRPHDONE) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXCDRPHDONE) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXCDRPHDONE) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXCDRPHDONE) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0); + (RXUSRCLK => RXCDRPHDONE) = (0:0:0, 0:0:0); + (RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCDRPHDONE) = (0:0:0, 0:0:0); + (RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[100]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[101]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[102]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[103]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[104]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[105]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[106]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[107]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[108]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[109]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[110]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[111]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[112]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[113]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[114]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[115]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[116]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[117]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[118]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[119]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[120]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[121]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[122]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[123]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[124]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[125]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[126]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[127]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[64]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[65]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[66]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[67]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[68]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[69]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[70]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[71]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[72]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[73]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[74]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[75]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[76]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[77]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[78]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[79]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[80]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[81]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[82]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[83]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[84]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[85]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[86]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[87]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[88]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[89]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[90]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[91]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[92]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[93]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[94]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[95]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[96]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[97]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[98]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[99]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRESETDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRESETDONE) = (100:100:100, 100:100:100); + (negedge RXCKCALRESET => (DMONITOROUT[0] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[10] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[11] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[12] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[13] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[16] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[1] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[2] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[3] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[4] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[5] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[6] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[7] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[8] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (DMONITOROUT[9] +: 1)) = (0:0:0, 0:0:0); + (negedge RXCKCALRESET => (RXCKCALDONE +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[0] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[16] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[1] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[2] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[3] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[4] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[5] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (DMONITOROUT[6] +: 1)) = (0:0:0, 0:0:0); + (negedge TXDCCRESET => (TXDCCDONE +: 1)) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK2, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTYE3_COMMON.v b/verilog/src/unisims/GTYE3_COMMON.v new file mode 100644 index 0000000..5f46380 --- /dev/null +++ b/verilog/src/unisims/GTYE3_COMMON.v @@ -0,0 +1,1185 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : GTYE3_COMMON.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTYE3_COMMON #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000, + parameter [8:0] A_SDM1DATA1_1 = 9'b000000000, + parameter [15:0] BIAS_CFG0 = 16'h0000, + parameter [15:0] BIAS_CFG1 = 16'h0000, + parameter [15:0] BIAS_CFG2 = 16'h0000, + parameter [15:0] BIAS_CFG3 = 16'h0000, + parameter [15:0] BIAS_CFG4 = 16'h0000, + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000, + parameter [15:0] COMMON_CFG0 = 16'h0000, + parameter [15:0] COMMON_CFG1 = 16'h0000, + parameter [15:0] POR_CFG = 16'h0004, + parameter [15:0] PPF0_CFG = 16'h0FFF, + parameter [15:0] PPF1_CFG = 16'h0FFF, + parameter QPLL0CLKOUT_RATE = "FULL", + parameter [15:0] QPLL0_CFG0 = 16'h301C, + parameter [15:0] QPLL0_CFG1 = 16'h0000, + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL0_CFG2 = 16'h0780, + parameter [15:0] QPLL0_CFG2_G3 = 16'h0780, + parameter [15:0] QPLL0_CFG3 = 16'h0120, + parameter [15:0] QPLL0_CFG4 = 16'h0021, + parameter [9:0] QPLL0_CP = 10'b0000011111, + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111, + parameter integer QPLL0_FBDIV = 66, + parameter integer QPLL0_FBDIV_G3 = 80, + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL0_LPF = 10'b1011111111, + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111, + parameter integer QPLL0_REFCLK_DIV = 2, + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0000, + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000, + parameter QPLL1CLKOUT_RATE = "FULL", + parameter [15:0] QPLL1_CFG0 = 16'h301C, + parameter [15:0] QPLL1_CFG1 = 16'h0000, + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL1_CFG2 = 16'h0780, + parameter [15:0] QPLL1_CFG2_G3 = 16'h0780, + parameter [15:0] QPLL1_CFG3 = 16'h0120, + parameter [15:0] QPLL1_CFG4 = 16'h0021, + parameter [9:0] QPLL1_CP = 10'b0000011111, + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111, + parameter integer QPLL1_FBDIV = 66, + parameter integer QPLL1_FBDIV_G3 = 80, + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL1_LPF = 10'b1011111111, + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111, + parameter integer QPLL1_REFCLK_DIV = 2, + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000, + parameter [15:0] RSVD_ATTR0 = 16'h0000, + parameter [15:0] RSVD_ATTR1 = 16'h0000, + parameter [15:0] RSVD_ATTR2 = 16'h0000, + parameter [15:0] RSVD_ATTR3 = 16'h0000, + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00, + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00, + parameter [0:0] SARC_EN = 1'b1, + parameter [0:0] SARC_SEL = 1'b0, + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000, + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000, + parameter SIM_MODE = "FAST", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter integer SIM_VERSION = 2 +)( + output [15:0] DRPDO, + output DRPRDY, + output [7:0] PMARSVDOUT0, + output [7:0] PMARSVDOUT1, + output QPLL0FBCLKLOST, + output QPLL0LOCK, + output QPLL0OUTCLK, + output QPLL0OUTREFCLK, + output QPLL0REFCLKLOST, + output QPLL1FBCLKLOST, + output QPLL1LOCK, + output QPLL1OUTCLK, + output QPLL1OUTREFCLK, + output QPLL1REFCLKLOST, + output [7:0] QPLLDMONITOR0, + output [7:0] QPLLDMONITOR1, + output REFCLKOUTMONITOR0, + output REFCLKOUTMONITOR1, + output [1:0] RXRECCLK0_SEL, + output [1:0] RXRECCLK1_SEL, + output [3:0] SDM0FINALOUT, + output [14:0] SDM0TESTDATA, + output [3:0] SDM1FINALOUT, + output [14:0] SDM1TESTDATA, + + input BGBYPASSB, + input BGMONITORENB, + input BGPDB, + input [4:0] BGRCALOVRD, + input BGRCALOVRDENB, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input GTGREFCLK0, + input GTGREFCLK1, + input GTNORTHREFCLK00, + input GTNORTHREFCLK01, + input GTNORTHREFCLK10, + input GTNORTHREFCLK11, + input GTREFCLK00, + input GTREFCLK01, + input GTREFCLK10, + input GTREFCLK11, + input GTSOUTHREFCLK00, + input GTSOUTHREFCLK01, + input GTSOUTHREFCLK10, + input GTSOUTHREFCLK11, + input [7:0] PMARSVD0, + input [7:0] PMARSVD1, + input QPLL0CLKRSVD0, + input QPLL0LOCKDETCLK, + input QPLL0LOCKEN, + input QPLL0PD, + input [2:0] QPLL0REFCLKSEL, + input QPLL0RESET, + input QPLL1CLKRSVD0, + input QPLL1LOCKDETCLK, + input QPLL1LOCKEN, + input QPLL1PD, + input [2:0] QPLL1REFCLKSEL, + input QPLL1RESET, + input [7:0] QPLLRSVD1, + input [4:0] QPLLRSVD2, + input [4:0] QPLLRSVD3, + input [7:0] QPLLRSVD4, + input RCALENB, + input [24:0] SDM0DATA, + input SDM0RESET, + input [1:0] SDM0WIDTH, + input [24:0] SDM1DATA, + input SDM1RESET, + input [1:0] SDM1WIDTH +); + +// define constants + localparam MODULE_NAME = "GTYE3_COMMON"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "GTYE3_COMMON_dr.v" +`else + localparam [15:0] A_SDM1DATA1_0_REG = A_SDM1DATA1_0; + localparam [8:0] A_SDM1DATA1_1_REG = A_SDM1DATA1_1; + localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0; + localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1; + localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2; + localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3; + localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4; + localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD; + localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0; + localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1; + localparam [15:0] POR_CFG_REG = POR_CFG; + localparam [15:0] PPF0_CFG_REG = PPF0_CFG; + localparam [15:0] PPF1_CFG_REG = PPF1_CFG; + localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE; + localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0; + localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1; + localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3; + localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2; + localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3; + localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3; + localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4; + localparam [9:0] QPLL0_CP_REG = QPLL0_CP; + localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3; + localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV; + localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3; + localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0; + localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1; + localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG; + localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3; + localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF; + localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3; + localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV; + localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0; + localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1; + localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2; + localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE; + localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0; + localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1; + localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3; + localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2; + localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3; + localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3; + localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4; + localparam [9:0] QPLL1_CP_REG = QPLL1_CP; + localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3; + localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV; + localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3; + localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0; + localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1; + localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG; + localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3; + localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF; + localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3; + localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV; + localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0; + localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1; + localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2; + localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0; + localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1; + localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2; + localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3; + localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL; + localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL; + localparam [0:0] SARC_EN_REG = SARC_EN; + localparam [0:0] SARC_SEL_REG = SARC_SEL; + localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0; + localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1; + localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0; + localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1; +// localparam [80:1] SIM_MODE_REG = SIM_MODE; +// localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; +// localparam [1:0] SIM_VERSION_REG = SIM_VERSION; +`endif + + localparam [0:0] AEN_BGBS0_REG = 1'b0; + localparam [0:0] AEN_BGBS1_REG = 1'b0; + localparam [0:0] AEN_MASTER0_REG = 1'b0; + localparam [0:0] AEN_MASTER1_REG = 1'b0; + localparam [0:0] AEN_PD0_REG = 1'b0; + localparam [0:0] AEN_PD1_REG = 1'b0; + localparam [0:0] AEN_QPLL0_REG = 1'b0; + localparam [0:0] AEN_QPLL1_REG = 1'b0; + localparam [0:0] AEN_REFCLK0_REG = 1'b0; + localparam [0:0] AEN_REFCLK1_REG = 1'b0; + localparam [0:0] AEN_RESET0_REG = 1'b0; + localparam [0:0] AEN_RESET1_REG = 1'b0; + localparam [0:0] AEN_SDMDATA0_REG = 1'b0; + localparam [0:0] AEN_SDMDATA1_REG = 1'b0; + localparam [0:0] AEN_SDMRESET0_REG = 1'b0; + localparam [0:0] AEN_SDMRESET1_REG = 1'b0; + localparam [0:0] AEN_SDMWIDTH0_REG = 1'b0; + localparam [0:0] AEN_SDMWIDTH1_REG = 1'b0; + localparam [3:0] AQDMUXSEL1_REG = 4'b0000; + localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000; + localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000; + localparam [0:0] A_BGMONITOREN_REG = 1'b0; + localparam [0:0] A_BGPD_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD0_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD1_REG = 1'b0; + localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL0PD_REG = 1'b0; + localparam [0:0] A_QPLL0RESET_REG = 1'b0; + localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL1PD_REG = 1'b0; + localparam [0:0] A_QPLL1RESET_REG = 1'b0; + localparam [15:0] A_SDM0DATA1_0_REG = 16'b0000000000000000; + localparam [8:0] A_SDM0DATA1_1_REG = 9'b000000000; + localparam [0:0] A_SDMRESET0_REG = 1'b0; + localparam [0:0] A_SDMRESET1_REG = 1'b0; + localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00; + localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00; + localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1; + localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000; + localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000; + localparam [0:0] RCALSAP_TESTEN_REG = 1'b0; + localparam [0:0] RCAL_APROBE_REG = 1'b0; + localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0; + localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0; + localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire DRPRDY_out; + wire QPLL0FBCLKLOST_out; + wire QPLL0LOCK_out; + wire QPLL0OUTCLK_out; + wire QPLL0OUTREFCLK_out; + wire QPLL0REFCLKLOST_out; + wire QPLL1FBCLKLOST_out; + wire QPLL1LOCK_out; + wire QPLL1OUTCLK_out; + wire QPLL1OUTREFCLK_out; + wire QPLL1REFCLKLOST_out; + wire REFCLKOUTMONITOR0_out; + wire REFCLKOUTMONITOR1_out; + wire [14:0] SDM0TESTDATA_out; + wire [14:0] SDM1TESTDATA_out; + wire [15:0] DRPDO_out; + wire [1:0] RXRECCLK0_SEL_out; + wire [1:0] RXRECCLK1_SEL_out; + wire [3:0] SARCCLK_out; + wire [3:0] SDM0FINALOUT_out; + wire [3:0] SDM1FINALOUT_out; + wire [7:0] PMARSVDOUT0_out; + wire [7:0] PMARSVDOUT1_out; + wire [7:0] PMASCANOUT_out; + wire [7:0] QPLLDMONITOR0_out; + wire [7:0] QPLLDMONITOR1_out; + + wire DRPRDY_delay; + wire QPLL0FBCLKLOST_delay; + wire QPLL0LOCK_delay; + wire QPLL0OUTCLK_delay; + wire QPLL0OUTREFCLK_delay; + wire QPLL0REFCLKLOST_delay; + wire QPLL1FBCLKLOST_delay; + wire QPLL1LOCK_delay; + wire QPLL1OUTCLK_delay; + wire QPLL1OUTREFCLK_delay; + wire QPLL1REFCLKLOST_delay; + wire REFCLKOUTMONITOR0_delay; + wire REFCLKOUTMONITOR1_delay; + wire [14:0] SDM0TESTDATA_delay; + wire [14:0] SDM1TESTDATA_delay; + wire [15:0] DRPDO_delay; + wire [1:0] RXRECCLK0_SEL_delay; + wire [1:0] RXRECCLK1_SEL_delay; + wire [3:0] SDM0FINALOUT_delay; + wire [3:0] SDM1FINALOUT_delay; + wire [7:0] PMARSVDOUT0_delay; + wire [7:0] PMARSVDOUT1_delay; + wire [7:0] QPLLDMONITOR0_delay; + wire [7:0] QPLLDMONITOR1_delay; + + wire BGBYPASSB_in; + wire BGMONITORENB_in; + wire BGPDB_in; + wire BGRCALOVRDENB_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire GTGREFCLK0_in; + wire GTGREFCLK1_in; + wire GTNORTHREFCLK00_in; + wire GTNORTHREFCLK01_in; + wire GTNORTHREFCLK10_in; + wire GTNORTHREFCLK11_in; + wire GTREFCLK00_in; + wire GTREFCLK01_in; + wire GTREFCLK10_in; + wire GTREFCLK11_in; + wire GTSOUTHREFCLK00_in; + wire GTSOUTHREFCLK01_in; + wire GTSOUTHREFCLK10_in; + wire GTSOUTHREFCLK11_in; + wire PMASCANENB_in; + wire QDPMASCANMODEB_in; + wire QDPMASCANRSTEN_in; + wire QPLL0CLKRSVD0_in; + wire QPLL0LOCKDETCLK_in; + wire QPLL0LOCKEN_in; + wire QPLL0PD_in; + wire QPLL0RESET_in; + wire QPLL1CLKRSVD0_in; + wire QPLL1LOCKDETCLK_in; + wire QPLL1LOCKEN_in; + wire QPLL1PD_in; + wire QPLL1RESET_in; + wire RCALENB_in; + wire SDM0RESET_in; + wire SDM1RESET_in; + wire [15:0] DRPDI_in; + wire [1:0] SDM0WIDTH_in; + wire [1:0] SDM1WIDTH_in; + wire [24:0] SDM0DATA_in; + wire [24:0] SDM1DATA_in; + wire [2:0] QPLL0REFCLKSEL_in; + wire [2:0] QPLL1REFCLKSEL_in; + wire [3:0] RXRECCLK_in; + wire [4:0] BGRCALOVRD_in; + wire [4:0] QPLLRSVD2_in; + wire [4:0] QPLLRSVD3_in; + wire [7:0] PMARSVD0_in; + wire [7:0] PMARSVD1_in; + wire [7:0] PMASCANCLK_in; + wire [7:0] PMASCANIN_in; + wire [7:0] QPLLRSVD1_in; + wire [7:0] QPLLRSVD4_in; + wire [9:0] DRPADDR_in; + + wire BGBYPASSB_delay; + wire BGMONITORENB_delay; + wire BGPDB_delay; + wire BGRCALOVRDENB_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire GTGREFCLK0_delay; + wire GTGREFCLK1_delay; + wire GTNORTHREFCLK00_delay; + wire GTNORTHREFCLK01_delay; + wire GTNORTHREFCLK10_delay; + wire GTNORTHREFCLK11_delay; + wire GTREFCLK00_delay; + wire GTREFCLK01_delay; + wire GTREFCLK10_delay; + wire GTREFCLK11_delay; + wire GTSOUTHREFCLK00_delay; + wire GTSOUTHREFCLK01_delay; + wire GTSOUTHREFCLK10_delay; + wire GTSOUTHREFCLK11_delay; + wire QPLL0CLKRSVD0_delay; + wire QPLL0LOCKDETCLK_delay; + wire QPLL0LOCKEN_delay; + wire QPLL0PD_delay; + wire QPLL0RESET_delay; + wire QPLL1CLKRSVD0_delay; + wire QPLL1LOCKDETCLK_delay; + wire QPLL1LOCKEN_delay; + wire QPLL1PD_delay; + wire QPLL1RESET_delay; + wire RCALENB_delay; + wire SDM0RESET_delay; + wire SDM1RESET_delay; + wire [15:0] DRPDI_delay; + wire [1:0] SDM0WIDTH_delay; + wire [1:0] SDM1WIDTH_delay; + wire [24:0] SDM0DATA_delay; + wire [24:0] SDM1DATA_delay; + wire [2:0] QPLL0REFCLKSEL_delay; + wire [2:0] QPLL1REFCLKSEL_delay; + wire [4:0] BGRCALOVRD_delay; + wire [4:0] QPLLRSVD2_delay; + wire [4:0] QPLLRSVD3_delay; + wire [7:0] PMARSVD0_delay; + wire [7:0] PMARSVD1_delay; + wire [7:0] QPLLRSVD1_delay; + wire [7:0] QPLLRSVD4_delay; + wire [9:0] DRPADDR_delay; + + assign #(out_delay) DRPDO = DRPDO_delay; + assign #(out_delay) DRPRDY = DRPRDY_delay; + assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay; + assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay; + assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay; + assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay; + assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay; + assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay; + assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay; + assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay; + assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay; + assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay; + assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay; + assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay; + assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay; + assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay; + assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay; + assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay; + assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay; + assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay; + assign #(out_delay) SDM0FINALOUT = SDM0FINALOUT_delay; + assign #(out_delay) SDM0TESTDATA = SDM0TESTDATA_delay; + assign #(out_delay) SDM1FINALOUT = SDM1FINALOUT_delay; + assign #(out_delay) SDM1TESTDATA = SDM1TESTDATA_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) DRPCLK_delay = DRPCLK; + + assign #(in_delay) DRPADDR_delay = DRPADDR; + assign #(in_delay) DRPDI_delay = DRPDI; + assign #(in_delay) DRPEN_delay = DRPEN; + assign #(in_delay) DRPWE_delay = DRPWE; +`endif + +// inputs with no timing checks + assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0; + assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1; + assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00; + assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01; + assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10; + assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11; + assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00; + assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01; + assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10; + assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11; + assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00; + assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01; + assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10; + assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11; + assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0; + assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK; + assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0; + assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK; + + assign #(in_delay) BGBYPASSB_delay = BGBYPASSB; + assign #(in_delay) BGMONITORENB_delay = BGMONITORENB; + assign #(in_delay) BGPDB_delay = BGPDB; + assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB; + assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD; + assign #(in_delay) PMARSVD0_delay = PMARSVD0; + assign #(in_delay) PMARSVD1_delay = PMARSVD1; + assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN; + assign #(in_delay) QPLL0PD_delay = QPLL0PD; + assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL; + assign #(in_delay) QPLL0RESET_delay = QPLL0RESET; + assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN; + assign #(in_delay) QPLL1PD_delay = QPLL1PD; + assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL; + assign #(in_delay) QPLL1RESET_delay = QPLL1RESET; + assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1; + assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2; + assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3; + assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4; + assign #(in_delay) RCALENB_delay = RCALENB; + assign #(in_delay) SDM0DATA_delay = SDM0DATA; + assign #(in_delay) SDM0RESET_delay = SDM0RESET; + assign #(in_delay) SDM0WIDTH_delay = SDM0WIDTH; + assign #(in_delay) SDM1DATA_delay = SDM1DATA; + assign #(in_delay) SDM1RESET_delay = SDM1RESET; + assign #(in_delay) SDM1WIDTH_delay = SDM1WIDTH; + + assign DRPDO_delay = DRPDO_out; + assign DRPRDY_delay = DRPRDY_out; + assign PMARSVDOUT0_delay = PMARSVDOUT0_out; + assign PMARSVDOUT1_delay = PMARSVDOUT1_out; + assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out; + assign QPLL0LOCK_delay = QPLL0LOCK_out; + assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out; + assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out; + assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out; + assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out; + assign QPLL1LOCK_delay = QPLL1LOCK_out; + assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out; + assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out; + assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out; + assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out; + assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out; + assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out; + assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out; + assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out; + assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out; + assign SDM0FINALOUT_delay = SDM0FINALOUT_out; + assign SDM0TESTDATA_delay = SDM0TESTDATA_out; + assign SDM1FINALOUT_delay = SDM1FINALOUT_out; + assign SDM1TESTDATA_delay = SDM1TESTDATA_out; + + assign BGBYPASSB_in = BGBYPASSB_delay; + assign BGMONITORENB_in = BGMONITORENB_delay; + assign BGPDB_in = BGPDB_delay; + assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay; + assign BGRCALOVRD_in = BGRCALOVRD_delay; + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign GTGREFCLK0_in = GTGREFCLK0_delay; + assign GTGREFCLK1_in = GTGREFCLK1_delay; + assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay; + assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay; + assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay; + assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay; + assign GTREFCLK00_in = GTREFCLK00_delay; + assign GTREFCLK01_in = GTREFCLK01_delay; + assign GTREFCLK10_in = GTREFCLK10_delay; + assign GTREFCLK11_in = GTREFCLK11_delay; + assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay; + assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay; + assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay; + assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay; + assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0_delay[0]; // rv 0 + assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0_delay[1]; // rv 0 + assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0_delay[2]; // rv 0 + assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0_delay[3]; // rv 0 + assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0_delay[4]; // rv 0 + assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0_delay[5]; // rv 0 + assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0_delay[6]; // rv 0 + assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0_delay[7]; // rv 0 + assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1_delay[0]; // rv 0 + assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1_delay[1]; // rv 0 + assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1_delay[2]; // rv 0 + assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1_delay[3]; // rv 0 + assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1_delay[4]; // rv 0 + assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1_delay[5]; // rv 0 + assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1_delay[6]; // rv 0 + assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1_delay[7]; // rv 0 + assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 === 1'bz) || QPLL0CLKRSVD0_delay; // rv 1 + assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK === 1'bz) || QPLL0LOCKDETCLK_delay; // rv 1 + assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN_delay; // rv 0 + assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD_delay; // rv 0 + assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL_delay[0]; // rv 1 + assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL_delay[1]; // rv 0 + assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL_delay[2]; // rv 0 + assign QPLL0RESET_in = (QPLL0RESET !== 1'bz) && QPLL0RESET_delay; // rv 0 + assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 === 1'bz) || QPLL1CLKRSVD0_delay; // rv 1 + assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK === 1'bz) || QPLL1LOCKDETCLK_delay; // rv 1 + assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN_delay; // rv 0 + assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD_delay; // rv 0 + assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL_delay[0]; // rv 1 + assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL_delay[1]; // rv 0 + assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL_delay[2]; // rv 0 + assign QPLL1RESET_in = (QPLL1RESET !== 1'bz) && QPLL1RESET_delay; // rv 0 + assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1_delay[0]; // rv 0 + assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1_delay[1]; // rv 0 + assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1_delay[2]; // rv 0 + assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1_delay[3]; // rv 0 + assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1_delay[4]; // rv 0 + assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1_delay[5]; // rv 0 + assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1_delay[6]; // rv 0 + assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1_delay[7]; // rv 0 + assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2_delay[0]; // rv 0 + assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2_delay[1]; // rv 0 + assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2_delay[2]; // rv 0 + assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2_delay[3]; // rv 0 + assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2_delay[4]; // rv 0 + assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3_delay[0]; // rv 0 + assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3_delay[1]; // rv 0 + assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3_delay[2]; // rv 0 + assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3_delay[3]; // rv 0 + assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3_delay[4]; // rv 0 + assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4_delay[0]; // rv 0 + assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4_delay[1]; // rv 0 + assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4_delay[2]; // rv 0 + assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4_delay[3]; // rv 0 + assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4_delay[4]; // rv 0 + assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4_delay[5]; // rv 0 + assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4_delay[6]; // rv 0 + assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4_delay[7]; // rv 0 + assign RCALENB_in = RCALENB_delay; + assign SDM0DATA_in[0] = (SDM0DATA[0] !== 1'bz) && SDM0DATA_delay[0]; // rv 0 + assign SDM0DATA_in[10] = (SDM0DATA[10] !== 1'bz) && SDM0DATA_delay[10]; // rv 0 + assign SDM0DATA_in[11] = (SDM0DATA[11] !== 1'bz) && SDM0DATA_delay[11]; // rv 0 + assign SDM0DATA_in[12] = (SDM0DATA[12] !== 1'bz) && SDM0DATA_delay[12]; // rv 0 + assign SDM0DATA_in[13] = (SDM0DATA[13] !== 1'bz) && SDM0DATA_delay[13]; // rv 0 + assign SDM0DATA_in[14] = (SDM0DATA[14] !== 1'bz) && SDM0DATA_delay[14]; // rv 0 + assign SDM0DATA_in[15] = (SDM0DATA[15] !== 1'bz) && SDM0DATA_delay[15]; // rv 0 + assign SDM0DATA_in[16] = (SDM0DATA[16] !== 1'bz) && SDM0DATA_delay[16]; // rv 0 + assign SDM0DATA_in[17] = (SDM0DATA[17] !== 1'bz) && SDM0DATA_delay[17]; // rv 0 + assign SDM0DATA_in[18] = (SDM0DATA[18] !== 1'bz) && SDM0DATA_delay[18]; // rv 0 + assign SDM0DATA_in[19] = (SDM0DATA[19] !== 1'bz) && SDM0DATA_delay[19]; // rv 0 + assign SDM0DATA_in[1] = (SDM0DATA[1] !== 1'bz) && SDM0DATA_delay[1]; // rv 0 + assign SDM0DATA_in[20] = (SDM0DATA[20] !== 1'bz) && SDM0DATA_delay[20]; // rv 0 + assign SDM0DATA_in[21] = (SDM0DATA[21] !== 1'bz) && SDM0DATA_delay[21]; // rv 0 + assign SDM0DATA_in[22] = (SDM0DATA[22] !== 1'bz) && SDM0DATA_delay[22]; // rv 0 + assign SDM0DATA_in[23] = (SDM0DATA[23] !== 1'bz) && SDM0DATA_delay[23]; // rv 0 + assign SDM0DATA_in[24] = (SDM0DATA[24] !== 1'bz) && SDM0DATA_delay[24]; // rv 0 + assign SDM0DATA_in[2] = (SDM0DATA[2] !== 1'bz) && SDM0DATA_delay[2]; // rv 0 + assign SDM0DATA_in[3] = (SDM0DATA[3] !== 1'bz) && SDM0DATA_delay[3]; // rv 0 + assign SDM0DATA_in[4] = (SDM0DATA[4] !== 1'bz) && SDM0DATA_delay[4]; // rv 0 + assign SDM0DATA_in[5] = (SDM0DATA[5] !== 1'bz) && SDM0DATA_delay[5]; // rv 0 + assign SDM0DATA_in[6] = (SDM0DATA[6] !== 1'bz) && SDM0DATA_delay[6]; // rv 0 + assign SDM0DATA_in[7] = (SDM0DATA[7] !== 1'bz) && SDM0DATA_delay[7]; // rv 0 + assign SDM0DATA_in[8] = (SDM0DATA[8] !== 1'bz) && SDM0DATA_delay[8]; // rv 0 + assign SDM0DATA_in[9] = (SDM0DATA[9] !== 1'bz) && SDM0DATA_delay[9]; // rv 0 + assign SDM0RESET_in = (SDM0RESET !== 1'bz) && SDM0RESET_delay; // rv 0 + assign SDM0WIDTH_in[0] = (SDM0WIDTH[0] !== 1'bz) && SDM0WIDTH_delay[0]; // rv 0 + assign SDM0WIDTH_in[1] = (SDM0WIDTH[1] !== 1'bz) && SDM0WIDTH_delay[1]; // rv 0 + assign SDM1DATA_in[0] = (SDM1DATA[0] !== 1'bz) && SDM1DATA_delay[0]; // rv 0 + assign SDM1DATA_in[10] = (SDM1DATA[10] !== 1'bz) && SDM1DATA_delay[10]; // rv 0 + assign SDM1DATA_in[11] = (SDM1DATA[11] !== 1'bz) && SDM1DATA_delay[11]; // rv 0 + assign SDM1DATA_in[12] = (SDM1DATA[12] !== 1'bz) && SDM1DATA_delay[12]; // rv 0 + assign SDM1DATA_in[13] = (SDM1DATA[13] !== 1'bz) && SDM1DATA_delay[13]; // rv 0 + assign SDM1DATA_in[14] = (SDM1DATA[14] !== 1'bz) && SDM1DATA_delay[14]; // rv 0 + assign SDM1DATA_in[15] = (SDM1DATA[15] !== 1'bz) && SDM1DATA_delay[15]; // rv 0 + assign SDM1DATA_in[16] = (SDM1DATA[16] !== 1'bz) && SDM1DATA_delay[16]; // rv 0 + assign SDM1DATA_in[17] = (SDM1DATA[17] !== 1'bz) && SDM1DATA_delay[17]; // rv 0 + assign SDM1DATA_in[18] = (SDM1DATA[18] !== 1'bz) && SDM1DATA_delay[18]; // rv 0 + assign SDM1DATA_in[19] = (SDM1DATA[19] !== 1'bz) && SDM1DATA_delay[19]; // rv 0 + assign SDM1DATA_in[1] = (SDM1DATA[1] !== 1'bz) && SDM1DATA_delay[1]; // rv 0 + assign SDM1DATA_in[20] = (SDM1DATA[20] !== 1'bz) && SDM1DATA_delay[20]; // rv 0 + assign SDM1DATA_in[21] = (SDM1DATA[21] !== 1'bz) && SDM1DATA_delay[21]; // rv 0 + assign SDM1DATA_in[22] = (SDM1DATA[22] !== 1'bz) && SDM1DATA_delay[22]; // rv 0 + assign SDM1DATA_in[23] = (SDM1DATA[23] !== 1'bz) && SDM1DATA_delay[23]; // rv 0 + assign SDM1DATA_in[24] = (SDM1DATA[24] !== 1'bz) && SDM1DATA_delay[24]; // rv 0 + assign SDM1DATA_in[2] = (SDM1DATA[2] !== 1'bz) && SDM1DATA_delay[2]; // rv 0 + assign SDM1DATA_in[3] = (SDM1DATA[3] !== 1'bz) && SDM1DATA_delay[3]; // rv 0 + assign SDM1DATA_in[4] = (SDM1DATA[4] !== 1'bz) && SDM1DATA_delay[4]; // rv 0 + assign SDM1DATA_in[5] = (SDM1DATA[5] !== 1'bz) && SDM1DATA_delay[5]; // rv 0 + assign SDM1DATA_in[6] = (SDM1DATA[6] !== 1'bz) && SDM1DATA_delay[6]; // rv 0 + assign SDM1DATA_in[7] = (SDM1DATA[7] !== 1'bz) && SDM1DATA_delay[7]; // rv 0 + assign SDM1DATA_in[8] = (SDM1DATA[8] !== 1'bz) && SDM1DATA_delay[8]; // rv 0 + assign SDM1DATA_in[9] = (SDM1DATA[9] !== 1'bz) && SDM1DATA_delay[9]; // rv 0 + assign SDM1RESET_in = (SDM1RESET !== 1'bz) && SDM1RESET_delay; // rv 0 + assign SDM1WIDTH_in[0] = (SDM1WIDTH[0] !== 1'bz) && SDM1WIDTH_delay[0]; // rv 0 + assign SDM1WIDTH_in[1] = (SDM1WIDTH[1] !== 1'bz) && SDM1WIDTH_delay[1]; // rv 0 + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((QPLL0CLKOUT_RATE_REG != "FULL") && + (QPLL0CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-152] QPLL0CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL0CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-163] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-164] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_REFCLK_DIV_REG != 2) && + (QPLL0_REFCLK_DIV_REG != 1) && + (QPLL0_REFCLK_DIV_REG != 3) && + (QPLL0_REFCLK_DIV_REG != 4) && + (QPLL0_REFCLK_DIV_REG != 5) && + (QPLL0_REFCLK_DIV_REG != 6) && + (QPLL0_REFCLK_DIV_REG != 8) && + (QPLL0_REFCLK_DIV_REG != 10) && + (QPLL0_REFCLK_DIV_REG != 12) && + (QPLL0_REFCLK_DIV_REG != 16) && + (QPLL0_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-171] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1CLKOUT_RATE_REG != "FULL") && + (QPLL1CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-175] QPLL1CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL1CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-186] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-187] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_REFCLK_DIV_REG != 2) && + (QPLL1_REFCLK_DIV_REG != 1) && + (QPLL1_REFCLK_DIV_REG != 3) && + (QPLL1_REFCLK_DIV_REG != 4) && + (QPLL1_REFCLK_DIV_REG != 5) && + (QPLL1_REFCLK_DIV_REG != 6) && + (QPLL1_REFCLK_DIV_REG != 8) && + (QPLL1_REFCLK_DIV_REG != 10) && + (QPLL1_REFCLK_DIV_REG != 12) && + (QPLL1_REFCLK_DIV_REG != 16) && + (QPLL1_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-194] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_MODE != "FAST")) begin + $display("Error: [Unisim %s-218] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP != "TRUE") && + (SIM_RESET_SPEEDUP != "FALSE"))) begin + $display("Error: [Unisim %s-219] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION != 2) && + (SIM_VERSION != 1) && + (SIM_VERSION != 3))) begin + $display("Error: [Unisim %s-220] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign PMASCANCLK_in = 8'b11111111; // tie off + + assign PMASCANENB_in = 1'b1; // tie off + assign PMASCANIN_in = 8'b11111111; // tie off + assign QDPMASCANMODEB_in = 1'b1; // tie off + assign QDPMASCANRSTEN_in = 1'b1; // tie off + assign RXRECCLK_in = 4'b1111; // tie off + + SIP_GTYE3_COMMON #( + .SIM_MODE (SIM_MODE), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION) +) SIP_GTYE3_COMMON_INST ( + .AEN_BGBS0 (AEN_BGBS0_REG), + .AEN_BGBS1 (AEN_BGBS1_REG), + .AEN_MASTER0 (AEN_MASTER0_REG), + .AEN_MASTER1 (AEN_MASTER1_REG), + .AEN_PD0 (AEN_PD0_REG), + .AEN_PD1 (AEN_PD1_REG), + .AEN_QPLL0 (AEN_QPLL0_REG), + .AEN_QPLL1 (AEN_QPLL1_REG), + .AEN_REFCLK0 (AEN_REFCLK0_REG), + .AEN_REFCLK1 (AEN_REFCLK1_REG), + .AEN_RESET0 (AEN_RESET0_REG), + .AEN_RESET1 (AEN_RESET1_REG), + .AEN_SDMDATA0 (AEN_SDMDATA0_REG), + .AEN_SDMDATA1 (AEN_SDMDATA1_REG), + .AEN_SDMRESET0 (AEN_SDMRESET0_REG), + .AEN_SDMRESET1 (AEN_SDMRESET1_REG), + .AEN_SDMWIDTH0 (AEN_SDMWIDTH0_REG), + .AEN_SDMWIDTH1 (AEN_SDMWIDTH1_REG), + .AQDMUXSEL1 (AQDMUXSEL1_REG), + .AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG), + .AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG), + .A_BGMONITOREN (A_BGMONITOREN_REG), + .A_BGPD (A_BGPD_REG), + .A_GTREFCLKPD0 (A_GTREFCLKPD0_REG), + .A_GTREFCLKPD1 (A_GTREFCLKPD1_REG), + .A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG), + .A_QPLL0PD (A_QPLL0PD_REG), + .A_QPLL0RESET (A_QPLL0RESET_REG), + .A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG), + .A_QPLL1PD (A_QPLL1PD_REG), + .A_QPLL1RESET (A_QPLL1RESET_REG), + .A_SDM0DATA1_0 (A_SDM0DATA1_0_REG), + .A_SDM0DATA1_1 (A_SDM0DATA1_1_REG), + .A_SDM1DATA1_0 (A_SDM1DATA1_0_REG), + .A_SDM1DATA1_1 (A_SDM1DATA1_1_REG), + .A_SDMRESET0 (A_SDMRESET0_REG), + .A_SDMRESET1 (A_SDMRESET1_REG), + .BIAS_CFG0 (BIAS_CFG0_REG), + .BIAS_CFG1 (BIAS_CFG1_REG), + .BIAS_CFG2 (BIAS_CFG2_REG), + .BIAS_CFG3 (BIAS_CFG3_REG), + .BIAS_CFG4 (BIAS_CFG4_REG), + .BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG), + .COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG), + .COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG), + .COMMON_CFG0 (COMMON_CFG0_REG), + .COMMON_CFG1 (COMMON_CFG1_REG), + .COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG), + .POR_CFG (POR_CFG_REG), + .PPF0_CFG (PPF0_CFG_REG), + .PPF1_CFG (PPF1_CFG_REG), + .QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG), + .QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG), + .QPLL0_CFG0 (QPLL0_CFG0_REG), + .QPLL0_CFG1 (QPLL0_CFG1_REG), + .QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG), + .QPLL0_CFG2 (QPLL0_CFG2_REG), + .QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG), + .QPLL0_CFG3 (QPLL0_CFG3_REG), + .QPLL0_CFG4 (QPLL0_CFG4_REG), + .QPLL0_CP (QPLL0_CP_REG), + .QPLL0_CP_G3 (QPLL0_CP_G3_REG), + .QPLL0_FBDIV (QPLL0_FBDIV_REG), + .QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG), + .QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG), + .QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG), + .QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG), + .QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG), + .QPLL0_LPF (QPLL0_LPF_REG), + .QPLL0_LPF_G3 (QPLL0_LPF_G3_REG), + .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG), + .QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG), + .QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG), + .QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG), + .QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG), + .QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG), + .QPLL1_CFG0 (QPLL1_CFG0_REG), + .QPLL1_CFG1 (QPLL1_CFG1_REG), + .QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG), + .QPLL1_CFG2 (QPLL1_CFG2_REG), + .QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG), + .QPLL1_CFG3 (QPLL1_CFG3_REG), + .QPLL1_CFG4 (QPLL1_CFG4_REG), + .QPLL1_CP (QPLL1_CP_REG), + .QPLL1_CP_G3 (QPLL1_CP_G3_REG), + .QPLL1_FBDIV (QPLL1_FBDIV_REG), + .QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG), + .QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG), + .QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG), + .QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG), + .QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG), + .QPLL1_LPF (QPLL1_LPF_REG), + .QPLL1_LPF_G3 (QPLL1_LPF_G3_REG), + .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG), + .QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG), + .QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG), + .QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG), + .RCALSAP_TESTEN (RCALSAP_TESTEN_REG), + .RCAL_APROBE (RCAL_APROBE_REG), + .REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG), + .REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG), + .REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG), + .REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG), + .REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG), + .REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG), + .RSVD_ATTR0 (RSVD_ATTR0_REG), + .RSVD_ATTR1 (RSVD_ATTR1_REG), + .RSVD_ATTR2 (RSVD_ATTR2_REG), + .RSVD_ATTR3 (RSVD_ATTR3_REG), + .RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG), + .RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG), + .SARC_EN (SARC_EN_REG), + .SARC_SEL (SARC_SEL_REG), + .SDM0INITSEED0_0 (SDM0INITSEED0_0_REG), + .SDM0INITSEED0_1 (SDM0INITSEED0_1_REG), + .SDM1INITSEED0_0 (SDM1INITSEED0_0_REG), + .SDM1INITSEED0_1 (SDM1INITSEED0_1_REG), + .VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .PMARSVDOUT0 (PMARSVDOUT0_out), + .PMARSVDOUT1 (PMARSVDOUT1_out), + .PMASCANOUT (PMASCANOUT_out), + .QPLL0FBCLKLOST (QPLL0FBCLKLOST_out), + .QPLL0LOCK (QPLL0LOCK_out), + .QPLL0OUTCLK (QPLL0OUTCLK_out), + .QPLL0OUTREFCLK (QPLL0OUTREFCLK_out), + .QPLL0REFCLKLOST (QPLL0REFCLKLOST_out), + .QPLL1FBCLKLOST (QPLL1FBCLKLOST_out), + .QPLL1LOCK (QPLL1LOCK_out), + .QPLL1OUTCLK (QPLL1OUTCLK_out), + .QPLL1OUTREFCLK (QPLL1OUTREFCLK_out), + .QPLL1REFCLKLOST (QPLL1REFCLKLOST_out), + .QPLLDMONITOR0 (QPLLDMONITOR0_out), + .QPLLDMONITOR1 (QPLLDMONITOR1_out), + .REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out), + .REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out), + .RXRECCLK0_SEL (RXRECCLK0_SEL_out), + .RXRECCLK1_SEL (RXRECCLK1_SEL_out), + .SARCCLK (SARCCLK_out), + .SDM0FINALOUT (SDM0FINALOUT_out), + .SDM0TESTDATA (SDM0TESTDATA_out), + .SDM1FINALOUT (SDM1FINALOUT_out), + .SDM1TESTDATA (SDM1TESTDATA_out), + .BGBYPASSB (BGBYPASSB_in), + .BGMONITORENB (BGMONITORENB_in), + .BGPDB (BGPDB_in), + .BGRCALOVRD (BGRCALOVRD_in), + .BGRCALOVRDENB (BGRCALOVRDENB_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .GTGREFCLK0 (GTGREFCLK0_in), + .GTGREFCLK1 (GTGREFCLK1_in), + .GTNORTHREFCLK00 (GTNORTHREFCLK00_in), + .GTNORTHREFCLK01 (GTNORTHREFCLK01_in), + .GTNORTHREFCLK10 (GTNORTHREFCLK10_in), + .GTNORTHREFCLK11 (GTNORTHREFCLK11_in), + .GTREFCLK00 (GTREFCLK00_in), + .GTREFCLK01 (GTREFCLK01_in), + .GTREFCLK10 (GTREFCLK10_in), + .GTREFCLK11 (GTREFCLK11_in), + .GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in), + .GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in), + .GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in), + .GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in), + .PMARSVD0 (PMARSVD0_in), + .PMARSVD1 (PMARSVD1_in), + .PMASCANCLK (PMASCANCLK_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .QDPMASCANMODEB (QDPMASCANMODEB_in), + .QDPMASCANRSTEN (QDPMASCANRSTEN_in), + .QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in), + .QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in), + .QPLL0LOCKEN (QPLL0LOCKEN_in), + .QPLL0PD (QPLL0PD_in), + .QPLL0REFCLKSEL (QPLL0REFCLKSEL_in), + .QPLL0RESET (QPLL0RESET_in), + .QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in), + .QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in), + .QPLL1LOCKEN (QPLL1LOCKEN_in), + .QPLL1PD (QPLL1PD_in), + .QPLL1REFCLKSEL (QPLL1REFCLKSEL_in), + .QPLL1RESET (QPLL1RESET_in), + .QPLLRSVD1 (QPLLRSVD1_in), + .QPLLRSVD2 (QPLLRSVD2_in), + .QPLLRSVD3 (QPLLRSVD3_in), + .QPLLRSVD4 (QPLLRSVD4_in), + .RCALENB (RCALENB_in), + .RXRECCLK (RXRECCLK_in), + .SDM0DATA (SDM0DATA_in), + .SDM0RESET (SDM0RESET_in), + .SDM0WIDTH (SDM0WIDTH_in), + .SDM1DATA (SDM1DATA_in), + .SDM1RESET (SDM1RESET_in), + .SDM1WIDTH (SDM1WIDTH_in), + .GSR (glblGSR) + ); + + specify + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (DRPCLK => RXRECCLK0_SEL[0]) = (100:100:100, 100:100:100); + (DRPCLK => RXRECCLK0_SEL[1]) = (100:100:100, 100:100:100); + (GTGREFCLK0 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTGREFCLK1 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + // (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output + // (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTYE4_CHANNEL.v b/verilog/src/unisims/GTYE4_CHANNEL.v new file mode 100644 index 0000000..1186d7e --- /dev/null +++ b/verilog/src/unisims/GTYE4_CHANNEL.v @@ -0,0 +1,5824 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver for UltraScale+ devices +// /___/ /\ Filename : GTYE4_CHANNEL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTYE4_CHANNEL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0, + parameter [0:0] ACJTAG_MODE = 1'b0, + parameter [0:0] ACJTAG_RESET = 1'b0, + parameter [15:0] ADAPT_CFG0 = 16'h9200, + parameter [15:0] ADAPT_CFG1 = 16'h801C, + parameter [15:0] ADAPT_CFG2 = 16'h0000, + parameter ALIGN_COMMA_DOUBLE = "FALSE", + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111, + parameter integer ALIGN_COMMA_WORD = 1, + parameter ALIGN_MCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011, + parameter ALIGN_PCOMMA_DET = "TRUE", + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100, + parameter [0:0] A_RXOSCALRESET = 1'b0, + parameter [0:0] A_RXPROGDIVRESET = 1'b0, + parameter [0:0] A_RXTERMINATION = 1'b1, + parameter [4:0] A_TXDIFFCTRL = 5'b01100, + parameter [0:0] A_TXPROGDIVRESET = 1'b0, + parameter CBCC_DATA_SOURCE_SEL = "DECODED", + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0, + parameter [0:0] CFOK_PWRSVE_EN = 1'b1, + parameter CHAN_BOND_KEEP_ALIGN = "FALSE", + parameter integer CHAN_BOND_MAX_SKEW = 7, + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100, + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111, + parameter CHAN_BOND_SEQ_2_USE = "FALSE", + parameter integer CHAN_BOND_SEQ_LEN = 2, + parameter [15:0] CH_HSPMUX = 16'h2424, + parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000, + parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000, + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000, + parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000, + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000, + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000, + parameter CLK_CORRECT_USE = "TRUE", + parameter CLK_COR_KEEP_IDLE = "FALSE", + parameter integer CLK_COR_MAX_LAT = 20, + parameter integer CLK_COR_MIN_LAT = 18, + parameter CLK_COR_PRECEDENCE = "TRUE", + parameter integer CLK_COR_REPEAT_WAIT = 0, + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100, + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000, + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000, + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111, + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000, + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000, + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111, + parameter CLK_COR_SEQ_2_USE = "FALSE", + parameter integer CLK_COR_SEQ_LEN = 2, + parameter [15:0] CPLL_CFG0 = 16'h01FA, + parameter [15:0] CPLL_CFG1 = 16'h24A9, + parameter [15:0] CPLL_CFG2 = 16'h6807, + parameter [15:0] CPLL_CFG3 = 16'h0000, + parameter integer CPLL_FBDIV = 4, + parameter integer CPLL_FBDIV_45 = 4, + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E, + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8, + parameter integer CPLL_REFCLK_DIV = 1, + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000, + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0, + parameter [1:0] DDI_CTRL = 2'b00, + parameter integer DDI_REALIGN_WAIT = 15, + parameter DEC_MCOMMA_DETECT = "TRUE", + parameter DEC_PCOMMA_DETECT = "TRUE", + parameter DEC_VALID_COMMA_ONLY = "TRUE", + parameter [0:0] DELAY_ELEC = 1'b0, + parameter [9:0] DMONITOR_CFG0 = 10'h000, + parameter [7:0] DMONITOR_CFG1 = 8'h00, + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0, + parameter [5:0] ES_CONTROL = 6'b000000, + parameter ES_ERRDET_EN = "FALSE", + parameter ES_EYE_SCAN_EN = "FALSE", + parameter [11:0] ES_HORZ_OFFSET = 12'h800, + parameter [4:0] ES_PRESCALE = 5'b00000, + parameter [15:0] ES_QUALIFIER0 = 16'h0000, + parameter [15:0] ES_QUALIFIER1 = 16'h0000, + parameter [15:0] ES_QUALIFIER2 = 16'h0000, + parameter [15:0] ES_QUALIFIER3 = 16'h0000, + parameter [15:0] ES_QUALIFIER4 = 16'h0000, + parameter [15:0] ES_QUALIFIER5 = 16'h0000, + parameter [15:0] ES_QUALIFIER6 = 16'h0000, + parameter [15:0] ES_QUALIFIER7 = 16'h0000, + parameter [15:0] ES_QUALIFIER8 = 16'h0000, + parameter [15:0] ES_QUALIFIER9 = 16'h0000, + parameter [15:0] ES_QUAL_MASK0 = 16'h0000, + parameter [15:0] ES_QUAL_MASK1 = 16'h0000, + parameter [15:0] ES_QUAL_MASK2 = 16'h0000, + parameter [15:0] ES_QUAL_MASK3 = 16'h0000, + parameter [15:0] ES_QUAL_MASK4 = 16'h0000, + parameter [15:0] ES_QUAL_MASK5 = 16'h0000, + parameter [15:0] ES_QUAL_MASK6 = 16'h0000, + parameter [15:0] ES_QUAL_MASK7 = 16'h0000, + parameter [15:0] ES_QUAL_MASK8 = 16'h0000, + parameter [15:0] ES_QUAL_MASK9 = 16'h0000, + parameter [15:0] ES_SDATA_MASK0 = 16'h0000, + parameter [15:0] ES_SDATA_MASK1 = 16'h0000, + parameter [15:0] ES_SDATA_MASK2 = 16'h0000, + parameter [15:0] ES_SDATA_MASK3 = 16'h0000, + parameter [15:0] ES_SDATA_MASK4 = 16'h0000, + parameter [15:0] ES_SDATA_MASK5 = 16'h0000, + parameter [15:0] ES_SDATA_MASK6 = 16'h0000, + parameter [15:0] ES_SDATA_MASK7 = 16'h0000, + parameter [15:0] ES_SDATA_MASK8 = 16'h0000, + parameter [15:0] ES_SDATA_MASK9 = 16'h0000, + parameter integer EYESCAN_VP_RANGE = 0, + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0, + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111, + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111, + parameter FTS_LANE_DESKEW_EN = "FALSE", + parameter [4:0] GEARBOX_MODE = 5'b00000, + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0, + parameter [0:0] LOCAL_MASTER = 1'b0, + parameter integer LPBK_BIAS_CTRL = 4, + parameter [0:0] LPBK_EN_RCAL_B = 1'b0, + parameter [3:0] LPBK_EXT_RCAL = 4'b0000, + parameter integer LPBK_IND_CTRL0 = 5, + parameter integer LPBK_IND_CTRL1 = 5, + parameter integer LPBK_IND_CTRL2 = 5, + parameter integer LPBK_RG_CTRL = 2, + parameter [1:0] OOBDIVCTL = 2'b00, + parameter [0:0] OOB_PWRUP = 1'b0, + parameter PCI3_AUTO_REALIGN = "FRST_SMPL", + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1, + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00, + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0, + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000, + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000, + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000, + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0, + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0, + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000, + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000, + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000, + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100, + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000, + parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE", + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000, + parameter PCIE_GEN4_64BIT_INT_EN = "FALSE", + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0, + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0, + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0, + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000, + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000, + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000, + parameter PCS_PCIE_EN = "FALSE", + parameter [15:0] PCS_RSVD0 = 16'h0000, + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C, + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19, + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64, + parameter integer PREIQ_FREQ_BST = 0, + parameter [0:0] RATE_SW_USE_DRP = 1'b0, + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0, + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0, + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010, + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00, + parameter [4:0] RXBUFRESET_TIME = 5'b00001, + parameter RXBUF_ADDR_MODE = "FULL", + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000, + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000, + parameter RXBUF_EN = "TRUE", + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE", + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE", + parameter RXBUF_RESET_ON_EIDLE = "FALSE", + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE", + parameter integer RXBUF_THRESH_OVFLW = 0, + parameter RXBUF_THRESH_OVRD = "FALSE", + parameter integer RXBUF_THRESH_UNDFLW = 4, + parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000, + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001, + parameter [15:0] RXCDR_CFG0 = 16'h0003, + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003, + parameter [15:0] RXCDR_CFG1 = 16'h0000, + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000, + parameter [15:0] RXCDR_CFG2 = 16'h0164, + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164, + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034, + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034, + parameter [15:0] RXCDR_CFG3 = 16'h0024, + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024, + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024, + parameter [15:0] RXCDR_CFG4 = 16'h5CF6, + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6, + parameter [15:0] RXCDR_CFG5 = 16'hB46B, + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B, + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0, + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0, + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040, + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000, + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000, + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000, + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0, + parameter [15:0] RXCFOK_CFG0 = 16'h0000, + parameter [15:0] RXCFOK_CFG1 = 16'h0002, + parameter [15:0] RXCFOK_CFG2 = 16'h002D, + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000, + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000, + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111, + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000, + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022, + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100, + parameter [15:0] RXDFE_CFG0 = 16'h4000, + parameter [15:0] RXDFE_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000, + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003, + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002, + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000, + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002, + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000, + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002, + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000, + parameter [15:0] RXDFE_KH_CFG3 = 16'h2000, + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000, + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000, + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000, + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002, + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000, + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000, + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022, + parameter [15:0] RXDLY_CFG = 16'h0010, + parameter [15:0] RXDLY_LCFG = 16'h0030, + parameter RXELECIDLE_CFG = "SIGCFG_4", + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter RXGEARBOX_EN = "FALSE", + parameter [4:0] RXISCANRESET_TIME = 5'b00001, + parameter [15:0] RXLPM_CFG = 16'h0000, + parameter [15:0] RXLPM_GC_CFG = 16'h1000, + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000, + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002, + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000, + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000, + parameter [8:0] RXOOB_CFG = 9'b000110000, + parameter RXOOB_CLK_CFG = "PMA", + parameter [4:0] RXOSCALRESET_TIME = 5'b00011, + parameter integer RXOUT_DIV = 4, + parameter [4:0] RXPCSRESET_TIME = 5'b00001, + parameter [15:0] RXPHBEACON_CFG = 16'h0000, + parameter [15:0] RXPHDLY_CFG = 16'h2020, + parameter [15:0] RXPHSAMP_CFG = 16'h2100, + parameter [15:0] RXPHSLIP_CFG = 16'h9933, + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000, + parameter [15:0] RXPI_CFG0 = 16'h0102, + parameter [15:0] RXPI_CFG1 = 16'b0000000001010100, + parameter RXPMACLK_SEL = "DATA", + parameter [4:0] RXPMARESET_TIME = 5'b00001, + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0, + parameter integer RXPRBS_LINKACQ_CNT = 15, + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0, + parameter integer RXSLIDE_AUTO_WAIT = 7, + parameter RXSLIDE_MODE = "OFF", + parameter [0:0] RXSYNC_MULTILANE = 1'b0, + parameter [0:0] RXSYNC_OVRD = 1'b0, + parameter [0:0] RXSYNC_SKIP_DA = 1'b0, + parameter [0:0] RX_AFE_CM_EN = 1'b0, + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0, + parameter [5:0] RX_BUFFER_CFG = 6'b000000, + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0, + parameter integer RX_CLK25_DIV = 8, + parameter [0:0] RX_CLKMUX_EN = 1'b1, + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000, + parameter [3:0] RX_CM_BUF_CFG = 4'b1010, + parameter [0:0] RX_CM_BUF_PD = 1'b0, + parameter integer RX_CM_SEL = 2, + parameter integer RX_CM_TRIM = 12, + parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0, + parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000, + parameter integer RX_DATA_WIDTH = 20, + parameter [5:0] RX_DDI_SEL = 6'b000000, + parameter RX_DEFER_RESET_BUF_EN = "TRUE", + parameter [2:0] RX_DEGEN_CTRL = 3'b100, + parameter integer RX_DFELPM_CFG0 = 10, + parameter [0:0] RX_DFELPM_CFG1 = 1'b1, + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1, + parameter integer RX_DFE_AGC_CFG1 = 4, + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1, + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2, + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01, + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4, + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0, + parameter RX_DISPERR_SEQ_MATCH = "TRUE", + parameter [4:0] RX_DIVRESET_TIME = 5'b00001, + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0, + parameter integer RX_EN_SUM_RCAL_B = 0, + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000, + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0, + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10, + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0, + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0, + parameter [0:0] RX_I2V_FILTER_EN = 1'b1, + parameter integer RX_INT_DATAWIDTH = 1, + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0, + parameter [15:0] RX_PMA_RSV0 = 16'h002F, + parameter real RX_PROGDIV_CFG = 0.0, + parameter [15:0] RX_PROGDIV_RATE = 16'h0001, + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000, + parameter [0:0] RX_RESLOAD_OVRD = 1'b0, + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101, + parameter integer RX_SIG_VALID_DLY = 11, + parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0, + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0, + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000, + parameter integer RX_SUM_PWR_SAVING = 0, + parameter [3:0] RX_SUM_RES_CTRL = 4'b0000, + parameter [3:0] RX_SUM_VCMTUNE = 4'b0011, + parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1, + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0, + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100, + parameter [1:0] RX_TUNE_AFE_OS = 2'b00, + parameter [2:0] RX_VREG_CTRL = 3'b010, + parameter [0:0] RX_VREG_PDB = 1'b1, + parameter [1:0] RX_WIDEMODE_CDR = 2'b01, + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01, + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01, + parameter RX_XCLK_SEL = "RXDES", + parameter [0:0] RX_XMODE_SEL = 1'b0, + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0, + parameter [0:0] SAS_12G_MODE = 1'b0, + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111, + parameter [2:0] SATA_BURST_VAL = 3'b100, + parameter SATA_CPLL_CFG = "VCO_3000MHZ", + parameter [2:0] SATA_EIDLE_VAL = 3'b100, + parameter SHOW_REALIGN_COMMA = "TRUE", + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SIM_MODE = "FAST", + parameter SIM_RECEIVER_DETECT_PASS = "TRUE", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z", + parameter [0:0] SRSTMODE = 1'b0, + parameter [1:0] TAPDLY_SET_TX = 2'h0, + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000, + parameter [2:0] TERM_RCAL_OVRD = 3'b000, + parameter [7:0] TRANS_TIME_RATE = 8'h0E, + parameter [7:0] TST_RSV0 = 8'h00, + parameter [7:0] TST_RSV1 = 8'h00, + parameter TXBUF_EN = "TRUE", + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE", + parameter [15:0] TXDLY_CFG = 16'h0010, + parameter [15:0] TXDLY_LCFG = 16'h0030, + parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG0 = 16'b0000000000000000, + parameter [15:0] TXFE_CFG1 = 16'b0000000000000000, + parameter [15:0] TXFE_CFG2 = 16'b0000000000000000, + parameter [15:0] TXFE_CFG3 = 16'b0000000000000000, + parameter TXFIFO_ADDR_CFG = "LOW", + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4, + parameter TXGEARBOX_EN = "FALSE", + parameter integer TXOUT_DIV = 4, + parameter [4:0] TXPCSRESET_TIME = 5'b00001, + parameter [15:0] TXPHDLY_CFG0 = 16'h6020, + parameter [15:0] TXPHDLY_CFG1 = 16'h0002, + parameter [15:0] TXPH_CFG = 16'h0123, + parameter [15:0] TXPH_CFG2 = 16'h0000, + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000, + parameter [15:0] TXPI_CFG0 = 16'b0000000100000000, + parameter [15:0] TXPI_CFG1 = 16'b0000000000000000, + parameter [0:0] TXPI_GRAY_SEL = 1'b0, + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0, + parameter [0:0] TXPI_PPM = 1'b0, + parameter [7:0] TXPI_PPM_CFG = 8'b00000000, + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000, + parameter [4:0] TXPMARESET_TIME = 5'b00001, + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0, + parameter integer TXSWBST_BST = 1, + parameter integer TXSWBST_EN = 0, + parameter integer TXSWBST_MAG = 6, + parameter [0:0] TXSYNC_MULTILANE = 1'b0, + parameter [0:0] TXSYNC_OVRD = 1'b0, + parameter [0:0] TXSYNC_SKIP_DA = 1'b0, + parameter integer TX_CLK25_DIV = 8, + parameter [0:0] TX_CLKMUX_EN = 1'b1, + parameter integer TX_DATA_WIDTH = 20, + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000, + parameter [5:0] TX_DEEMPH0 = 6'b000000, + parameter [5:0] TX_DEEMPH1 = 6'b000000, + parameter [5:0] TX_DEEMPH2 = 6'b000000, + parameter [5:0] TX_DEEMPH3 = 6'b000000, + parameter [4:0] TX_DIVRESET_TIME = 5'b00001, + parameter TX_DRIVE_MODE = "DIRECT", + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110, + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100, + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0, + parameter [0:0] TX_FIFO_BYP_EN = 1'b0, + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0, + parameter integer TX_INT_DATAWIDTH = 1, + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE", + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0, + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110, + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001, + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101, + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010, + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110, + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100, + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010, + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000, + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000, + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000, + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F, + parameter integer TX_PI_BIASSET = 0, + parameter [0:0] TX_PMADATA_OPT = 1'b0, + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0, + parameter [15:0] TX_PMA_RSV0 = 16'h0000, + parameter [15:0] TX_PMA_RSV1 = 16'h0000, + parameter TX_PROGCLK_SEL = "POSTPI", + parameter real TX_PROGDIV_CFG = 0.0, + parameter [15:0] TX_PROGDIV_RATE = 16'h0001, + parameter [13:0] TX_RXDETECT_CFG = 14'h0032, + parameter integer TX_RXDETECT_REF = 3, + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101, + parameter [1:0] TX_SW_MEAS = 2'b00, + parameter [2:0] TX_VREG_CTRL = 3'b000, + parameter [0:0] TX_VREG_PDB = 1'b0, + parameter [1:0] TX_VREG_VREFSEL = 2'b00, + parameter TX_XCLK_SEL = "TXOUT", + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0, + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111, + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011, + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0, + parameter [0:0] USB_EXT_CNTL = 1'b1, + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011, + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011, + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101, + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001, + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100, + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101, + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011, + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011, + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011, + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1, + parameter [0:0] USB_MODE = 1'b0, + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0, + parameter integer USB_PING_SATA_MAX_INIT = 21, + parameter integer USB_PING_SATA_MIN_INIT = 12, + parameter integer USB_POLL_SATA_MAX_BURST = 8, + parameter integer USB_POLL_SATA_MIN_BURST = 4, + parameter [0:0] USB_RAW_ELEC = 1'b0, + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1, + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1, + parameter integer USB_U1_SATA_MAX_WAKE = 7, + parameter integer USB_U1_SATA_MIN_WAKE = 4, + parameter integer USB_U2_SAS_MAX_COM = 64, + parameter integer USB_U2_SAS_MIN_COM = 36, + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0, + parameter [0:0] Y_ALL_MODE = 1'b0 +)( + output BUFGTCE, + output [2:0] BUFGTCEMASK, + output [8:0] BUFGTDIV, + output BUFGTRESET, + output [2:0] BUFGTRSTMASK, + output CPLLFBCLKLOST, + output CPLLLOCK, + output CPLLREFCLKLOST, + output [15:0] DMONITOROUT, + output DMONITOROUTCLK, + output [15:0] DRPDO, + output DRPRDY, + output EYESCANDATAERROR, + output GTPOWERGOOD, + output GTREFCLKMONITOR, + output GTYTXN, + output GTYTXP, + output PCIERATEGEN3, + output PCIERATEIDLE, + output [1:0] PCIERATEQPLLPD, + output [1:0] PCIERATEQPLLRESET, + output PCIESYNCTXSYNCDONE, + output PCIEUSERGEN3RDY, + output PCIEUSERPHYSTATUSRST, + output PCIEUSERRATESTART, + output [15:0] PCSRSVDOUT, + output PHYSTATUS, + output [15:0] PINRSRVDAS, + output POWERPRESENT, + output RESETEXCEPTION, + output [2:0] RXBUFSTATUS, + output RXBYTEISALIGNED, + output RXBYTEREALIGN, + output RXCDRLOCK, + output RXCDRPHDONE, + output RXCHANBONDSEQ, + output RXCHANISALIGNED, + output RXCHANREALIGN, + output [4:0] RXCHBONDO, + output RXCKCALDONE, + output [1:0] RXCLKCORCNT, + output RXCOMINITDET, + output RXCOMMADET, + output RXCOMSASDET, + output RXCOMWAKEDET, + output [15:0] RXCTRL0, + output [15:0] RXCTRL1, + output [7:0] RXCTRL2, + output [7:0] RXCTRL3, + output [127:0] RXDATA, + output [7:0] RXDATAEXTENDRSVD, + output [1:0] RXDATAVALID, + output RXDLYSRESETDONE, + output RXELECIDLE, + output [5:0] RXHEADER, + output [1:0] RXHEADERVALID, + output RXLFPSTRESETDET, + output RXLFPSU2LPEXITDET, + output RXLFPSU3WAKEDET, + output [7:0] RXMONITOROUT, + output RXOSINTDONE, + output RXOSINTSTARTED, + output RXOSINTSTROBEDONE, + output RXOSINTSTROBESTARTED, + output RXOUTCLK, + output RXOUTCLKFABRIC, + output RXOUTCLKPCS, + output RXPHALIGNDONE, + output RXPHALIGNERR, + output RXPMARESETDONE, + output RXPRBSERR, + output RXPRBSLOCKED, + output RXPRGDIVRESETDONE, + output RXRATEDONE, + output RXRECCLKOUT, + output RXRESETDONE, + output RXSLIDERDY, + output RXSLIPDONE, + output RXSLIPOUTCLKRDY, + output RXSLIPPMARDY, + output [1:0] RXSTARTOFSEQ, + output [2:0] RXSTATUS, + output RXSYNCDONE, + output RXSYNCOUT, + output RXVALID, + output [1:0] TXBUFSTATUS, + output TXCOMFINISH, + output TXDCCDONE, + output TXDLYSRESETDONE, + output TXOUTCLK, + output TXOUTCLKFABRIC, + output TXOUTCLKPCS, + output TXPHALIGNDONE, + output TXPHINITDONE, + output TXPMARESETDONE, + output TXPRGDIVRESETDONE, + output TXRATEDONE, + output TXRESETDONE, + output TXSYNCDONE, + output TXSYNCOUT, + + input CDRSTEPDIR, + input CDRSTEPSQ, + input CDRSTEPSX, + input CFGRESET, + input CLKRSVD0, + input CLKRSVD1, + input CPLLFREQLOCK, + input CPLLLOCKDETCLK, + input CPLLLOCKEN, + input CPLLPD, + input [2:0] CPLLREFCLKSEL, + input CPLLRESET, + input DMONFIFORESET, + input DMONITORCLK, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPRST, + input DRPWE, + input EYESCANRESET, + input EYESCANTRIGGER, + input FREQOS, + input GTGREFCLK, + input GTNORTHREFCLK0, + input GTNORTHREFCLK1, + input GTREFCLK0, + input GTREFCLK1, + input [15:0] GTRSVD, + input GTRXRESET, + input GTRXRESETSEL, + input GTSOUTHREFCLK0, + input GTSOUTHREFCLK1, + input GTTXRESET, + input GTTXRESETSEL, + input GTYRXN, + input GTYRXP, + input INCPCTRL, + input [2:0] LOOPBACK, + input PCIEEQRXEQADAPTDONE, + input PCIERSTIDLE, + input PCIERSTTXSYNCSTART, + input PCIEUSERRATEDONE, + input [15:0] PCSRSVDIN, + input QPLL0CLK, + input QPLL0FREQLOCK, + input QPLL0REFCLK, + input QPLL1CLK, + input QPLL1FREQLOCK, + input QPLL1REFCLK, + input RESETOVRD, + input RX8B10BEN, + input RXAFECFOKEN, + input RXBUFRESET, + input RXCDRFREQRESET, + input RXCDRHOLD, + input RXCDROVRDEN, + input RXCDRRESET, + input RXCHBONDEN, + input [4:0] RXCHBONDI, + input [2:0] RXCHBONDLEVEL, + input RXCHBONDMASTER, + input RXCHBONDSLAVE, + input RXCKCALRESET, + input [6:0] RXCKCALSTART, + input RXCOMMADETEN, + input RXDFEAGCHOLD, + input RXDFEAGCOVRDEN, + input [3:0] RXDFECFOKFCNUM, + input RXDFECFOKFEN, + input RXDFECFOKFPULSE, + input RXDFECFOKHOLD, + input RXDFECFOKOVREN, + input RXDFEKHHOLD, + input RXDFEKHOVRDEN, + input RXDFELFHOLD, + input RXDFELFOVRDEN, + input RXDFELPMRESET, + input RXDFETAP10HOLD, + input RXDFETAP10OVRDEN, + input RXDFETAP11HOLD, + input RXDFETAP11OVRDEN, + input RXDFETAP12HOLD, + input RXDFETAP12OVRDEN, + input RXDFETAP13HOLD, + input RXDFETAP13OVRDEN, + input RXDFETAP14HOLD, + input RXDFETAP14OVRDEN, + input RXDFETAP15HOLD, + input RXDFETAP15OVRDEN, + input RXDFETAP2HOLD, + input RXDFETAP2OVRDEN, + input RXDFETAP3HOLD, + input RXDFETAP3OVRDEN, + input RXDFETAP4HOLD, + input RXDFETAP4OVRDEN, + input RXDFETAP5HOLD, + input RXDFETAP5OVRDEN, + input RXDFETAP6HOLD, + input RXDFETAP6OVRDEN, + input RXDFETAP7HOLD, + input RXDFETAP7OVRDEN, + input RXDFETAP8HOLD, + input RXDFETAP8OVRDEN, + input RXDFETAP9HOLD, + input RXDFETAP9OVRDEN, + input RXDFEUTHOLD, + input RXDFEUTOVRDEN, + input RXDFEVPHOLD, + input RXDFEVPOVRDEN, + input RXDFEXYDEN, + input RXDLYBYPASS, + input RXDLYEN, + input RXDLYOVRDEN, + input RXDLYSRESET, + input [1:0] RXELECIDLEMODE, + input RXEQTRAINING, + input RXGEARBOXSLIP, + input RXLATCLK, + input RXLPMEN, + input RXLPMGCHOLD, + input RXLPMGCOVRDEN, + input RXLPMHFHOLD, + input RXLPMHFOVRDEN, + input RXLPMLFHOLD, + input RXLPMLFKLOVRDEN, + input RXLPMOSHOLD, + input RXLPMOSOVRDEN, + input RXMCOMMAALIGNEN, + input [1:0] RXMONITORSEL, + input RXOOBRESET, + input RXOSCALRESET, + input RXOSHOLD, + input RXOSOVRDEN, + input [2:0] RXOUTCLKSEL, + input RXPCOMMAALIGNEN, + input RXPCSRESET, + input [1:0] RXPD, + input RXPHALIGN, + input RXPHALIGNEN, + input RXPHDLYPD, + input RXPHDLYRESET, + input [1:0] RXPLLCLKSEL, + input RXPMARESET, + input RXPOLARITY, + input RXPRBSCNTRESET, + input [3:0] RXPRBSSEL, + input RXPROGDIVRESET, + input [2:0] RXRATE, + input RXRATEMODE, + input RXSLIDE, + input RXSLIPOUTCLK, + input RXSLIPPMA, + input RXSYNCALLIN, + input RXSYNCIN, + input RXSYNCMODE, + input [1:0] RXSYSCLKSEL, + input RXTERMINATION, + input RXUSERRDY, + input RXUSRCLK, + input RXUSRCLK2, + input SIGVALIDCLK, + input [19:0] TSTIN, + input [7:0] TX8B10BBYPASS, + input TX8B10BEN, + input TXCOMINIT, + input TXCOMSAS, + input TXCOMWAKE, + input [15:0] TXCTRL0, + input [15:0] TXCTRL1, + input [7:0] TXCTRL2, + input [127:0] TXDATA, + input [7:0] TXDATAEXTENDRSVD, + input TXDCCFORCESTART, + input TXDCCRESET, + input [1:0] TXDEEMPH, + input TXDETECTRX, + input [4:0] TXDIFFCTRL, + input TXDLYBYPASS, + input TXDLYEN, + input TXDLYHOLD, + input TXDLYOVRDEN, + input TXDLYSRESET, + input TXDLYUPDOWN, + input TXELECIDLE, + input [5:0] TXHEADER, + input TXINHIBIT, + input TXLATCLK, + input TXLFPSTRESET, + input TXLFPSU2LPEXIT, + input TXLFPSU3WAKE, + input [6:0] TXMAINCURSOR, + input [2:0] TXMARGIN, + input TXMUXDCDEXHOLD, + input TXMUXDCDORWREN, + input TXONESZEROS, + input [2:0] TXOUTCLKSEL, + input TXPCSRESET, + input [1:0] TXPD, + input TXPDELECIDLEMODE, + input TXPHALIGN, + input TXPHALIGNEN, + input TXPHDLYPD, + input TXPHDLYRESET, + input TXPHDLYTSTCLK, + input TXPHINIT, + input TXPHOVRDEN, + input TXPIPPMEN, + input TXPIPPMOVRDEN, + input TXPIPPMPD, + input TXPIPPMSEL, + input [4:0] TXPIPPMSTEPSIZE, + input TXPISOPD, + input [1:0] TXPLLCLKSEL, + input TXPMARESET, + input TXPOLARITY, + input [4:0] TXPOSTCURSOR, + input TXPRBSFORCEERR, + input [3:0] TXPRBSSEL, + input [4:0] TXPRECURSOR, + input TXPROGDIVRESET, + input [2:0] TXRATE, + input TXRATEMODE, + input [6:0] TXSEQUENCE, + input TXSWING, + input TXSYNCALLIN, + input TXSYNCIN, + input TXSYNCMODE, + input [1:0] TXSYSCLKSEL, + input TXUSERRDY, + input TXUSRCLK, + input TXUSRCLK2 +); + +// define constants + localparam MODULE_NAME = "GTYE4_CHANNEL"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "GTYE4_CHANNEL_dr.v" +`else + reg [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE; + reg [0:0] ACJTAG_MODE_REG = ACJTAG_MODE; + reg [0:0] ACJTAG_RESET_REG = ACJTAG_RESET; + reg [15:0] ADAPT_CFG0_REG = ADAPT_CFG0; + reg [15:0] ADAPT_CFG1_REG = ADAPT_CFG1; + reg [15:0] ADAPT_CFG2_REG = ADAPT_CFG2; + reg [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE; + reg [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE; + reg [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD; + reg [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET; + reg [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE; + reg [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET; + reg [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE; + reg [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET; + reg [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET; + reg [0:0] A_RXTERMINATION_REG = A_RXTERMINATION; + reg [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL; + reg [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET; + reg [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL; + reg [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN; + reg [0:0] CFOK_PWRSVE_EN_REG = CFOK_PWRSVE_EN; + reg [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN; + reg [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW; + reg [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1; + reg [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2; + reg [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3; + reg [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE; + reg [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1; + reg [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2; + reg [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3; + reg [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE; + reg [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE; + reg [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN; + reg [15:0] CH_HSPMUX_REG = CH_HSPMUX; + reg [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0; + reg [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1; + reg [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2; + reg [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3; + reg [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0; + reg [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1; + reg [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2; + reg [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3; + reg [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4; + reg [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE; + reg [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE; + reg [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT; + reg [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT; + reg [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE; + reg [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT; + reg [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1; + reg [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2; + reg [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3; + reg [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4; + reg [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE; + reg [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1; + reg [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2; + reg [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3; + reg [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4; + reg [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE; + reg [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE; + reg [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN; + reg [15:0] CPLL_CFG0_REG = CPLL_CFG0; + reg [15:0] CPLL_CFG1_REG = CPLL_CFG1; + reg [15:0] CPLL_CFG2_REG = CPLL_CFG2; + reg [15:0] CPLL_CFG3_REG = CPLL_CFG3; + reg [4:0] CPLL_FBDIV_REG = CPLL_FBDIV; + reg [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45; + reg [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0; + reg [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG; + reg [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV; + reg [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL; + reg [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN; + reg [1:0] DDI_CTRL_REG = DDI_CTRL; + reg [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT; + reg [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT; + reg [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT; + reg [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY; + reg [0:0] DELAY_ELEC_REG = DELAY_ELEC; + reg [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0; + reg [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1; + reg [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL; + reg [5:0] ES_CONTROL_REG = ES_CONTROL; + reg [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN; + reg [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN; + reg [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET; + reg [4:0] ES_PRESCALE_REG = ES_PRESCALE; + reg [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0; + reg [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1; + reg [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2; + reg [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3; + reg [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4; + reg [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5; + reg [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6; + reg [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7; + reg [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8; + reg [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9; + reg [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0; + reg [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1; + reg [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2; + reg [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3; + reg [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4; + reg [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5; + reg [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6; + reg [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7; + reg [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8; + reg [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9; + reg [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0; + reg [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1; + reg [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2; + reg [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3; + reg [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4; + reg [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5; + reg [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6; + reg [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7; + reg [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8; + reg [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9; + reg [1:0] EYESCAN_VP_RANGE_REG = EYESCAN_VP_RANGE; + reg [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN; + reg [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE; + reg [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG; + reg [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN; + reg [4:0] GEARBOX_MODE_REG = GEARBOX_MODE; + reg [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2; + reg [0:0] LOCAL_MASTER_REG = LOCAL_MASTER; + reg [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL; + reg [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B; + reg [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL; + reg [2:0] LPBK_IND_CTRL0_REG = LPBK_IND_CTRL0; + reg [2:0] LPBK_IND_CTRL1_REG = LPBK_IND_CTRL1; + reg [2:0] LPBK_IND_CTRL2_REG = LPBK_IND_CTRL2; + reg [1:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL; + reg [1:0] OOBDIVCTL_REG = OOBDIVCTL; + reg [0:0] OOB_PWRUP_REG = OOB_PWRUP; + reg [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN; + reg [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE; + reg [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS; + reg [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE; + reg [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT; + reg [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE; + reg [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT; + reg [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE; + reg [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE; + reg [4:0] PCIE3_CLK_COR_EMPTY_THRSH_REG = PCIE3_CLK_COR_EMPTY_THRSH; + reg [5:0] PCIE3_CLK_COR_FULL_THRSH_REG = PCIE3_CLK_COR_FULL_THRSH; + reg [4:0] PCIE3_CLK_COR_MAX_LAT_REG = PCIE3_CLK_COR_MAX_LAT; + reg [4:0] PCIE3_CLK_COR_MIN_LAT_REG = PCIE3_CLK_COR_MIN_LAT; + reg [5:0] PCIE3_CLK_COR_THRSH_TIMER_REG = PCIE3_CLK_COR_THRSH_TIMER; + reg [40:1] PCIE_64B_DYN_CLKSW_DIS_REG = PCIE_64B_DYN_CLKSW_DIS; + reg [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL; + reg [40:1] PCIE_GEN4_64BIT_INT_EN_REG = PCIE_GEN4_64BIT_INT_EN; + reg [1:0] PCIE_PLL_SEL_MODE_GEN12_REG = PCIE_PLL_SEL_MODE_GEN12; + reg [1:0] PCIE_PLL_SEL_MODE_GEN3_REG = PCIE_PLL_SEL_MODE_GEN3; + reg [1:0] PCIE_PLL_SEL_MODE_GEN4_REG = PCIE_PLL_SEL_MODE_GEN4; + reg [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3; + reg [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG; + reg [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3; + reg [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG; + reg [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN; + reg [15:0] PCS_RSVD0_REG = PCS_RSVD0; + reg [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2; + reg [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2; + reg [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2; + reg [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST; + reg [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP; + reg [0:0] RCLK_SIPO_DLY_ENB_REG = RCLK_SIPO_DLY_ENB; + reg [0:0] RCLK_SIPO_INV_EN_REG = RCLK_SIPO_INV_EN; + reg [2:0] RTX_BUF_CML_CTRL_REG = RTX_BUF_CML_CTRL; + reg [1:0] RTX_BUF_TERM_CTRL_REG = RTX_BUF_TERM_CTRL; + reg [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME; + reg [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE; + reg [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT; + reg [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT; + reg [40:1] RXBUF_EN_REG = RXBUF_EN; + reg [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE; + reg [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN; + reg [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE; + reg [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE; + reg [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW; + reg [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD; + reg [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW; + reg [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME; + reg [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME; + reg [15:0] RXCDR_CFG0_REG = RXCDR_CFG0; + reg [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3; + reg [15:0] RXCDR_CFG1_REG = RXCDR_CFG1; + reg [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3; + reg [15:0] RXCDR_CFG2_REG = RXCDR_CFG2; + reg [9:0] RXCDR_CFG2_GEN2_REG = RXCDR_CFG2_GEN2; + reg [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3; + reg [15:0] RXCDR_CFG2_GEN4_REG = RXCDR_CFG2_GEN4; + reg [15:0] RXCDR_CFG3_REG = RXCDR_CFG3; + reg [5:0] RXCDR_CFG3_GEN2_REG = RXCDR_CFG3_GEN2; + reg [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3; + reg [15:0] RXCDR_CFG3_GEN4_REG = RXCDR_CFG3_GEN4; + reg [15:0] RXCDR_CFG4_REG = RXCDR_CFG4; + reg [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3; + reg [15:0] RXCDR_CFG5_REG = RXCDR_CFG5; + reg [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3; + reg [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE; + reg [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE; + reg [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0; + reg [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1; + reg [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2; + reg [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3; + reg [15:0] RXCDR_LOCK_CFG4_REG = RXCDR_LOCK_CFG4; + reg [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE; + reg [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0; + reg [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1; + reg [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2; + reg [15:0] RXCKCAL1_IQ_LOOP_RST_CFG_REG = RXCKCAL1_IQ_LOOP_RST_CFG; + reg [15:0] RXCKCAL1_I_LOOP_RST_CFG_REG = RXCKCAL1_I_LOOP_RST_CFG; + reg [15:0] RXCKCAL1_Q_LOOP_RST_CFG_REG = RXCKCAL1_Q_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_DX_LOOP_RST_CFG_REG = RXCKCAL2_DX_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_D_LOOP_RST_CFG_REG = RXCKCAL2_D_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_S_LOOP_RST_CFG_REG = RXCKCAL2_S_LOOP_RST_CFG; + reg [15:0] RXCKCAL2_X_LOOP_RST_CFG_REG = RXCKCAL2_X_LOOP_RST_CFG; + reg [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME; + reg [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0; + reg [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1; + reg [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2; + reg [15:0] RXDFE_CFG0_REG = RXDFE_CFG0; + reg [15:0] RXDFE_CFG1_REG = RXDFE_CFG1; + reg [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0; + reg [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1; + reg [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2; + reg [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0; + reg [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1; + reg [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0; + reg [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1; + reg [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0; + reg [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1; + reg [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0; + reg [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1; + reg [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0; + reg [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1; + reg [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0; + reg [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1; + reg [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0; + reg [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1; + reg [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0; + reg [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1; + reg [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0; + reg [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1; + reg [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0; + reg [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1; + reg [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0; + reg [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1; + reg [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0; + reg [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1; + reg [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0; + reg [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1; + reg [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0; + reg [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1; + reg [15:0] RXDFE_KH_CFG0_REG = RXDFE_KH_CFG0; + reg [15:0] RXDFE_KH_CFG1_REG = RXDFE_KH_CFG1; + reg [15:0] RXDFE_KH_CFG2_REG = RXDFE_KH_CFG2; + reg [15:0] RXDFE_KH_CFG3_REG = RXDFE_KH_CFG3; + reg [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0; + reg [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1; + reg [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0; + reg [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1; + reg [15:0] RXDFE_UT_CFG2_REG = RXDFE_UT_CFG2; + reg [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0; + reg [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1; + reg [15:0] RXDLY_CFG_REG = RXDLY_CFG; + reg [15:0] RXDLY_LCFG_REG = RXDLY_LCFG; + reg [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG; + reg [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR; + reg [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN; + reg [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME; + reg [15:0] RXLPM_CFG_REG = RXLPM_CFG; + reg [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG; + reg [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0; + reg [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1; + reg [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0; + reg [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1; + reg [8:0] RXOOB_CFG_REG = RXOOB_CFG; + reg [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG; + reg [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME; + reg [5:0] RXOUT_DIV_REG = RXOUT_DIV; + reg [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME; + reg [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG; + reg [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG; + reg [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG; + reg [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG; + reg [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL; + reg [15:0] RXPI_CFG0_REG = RXPI_CFG0; + reg [15:0] RXPI_CFG1_REG = RXPI_CFG1; + reg [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL; + reg [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME; + reg [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK; + reg [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT; + reg [0:0] RXREFCLKDIV2_SEL_REG = RXREFCLKDIV2_SEL; + reg [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT; + reg [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE; + reg [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE; + reg [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD; + reg [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA; + reg [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN; + reg [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0; + reg [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG; + reg [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB; + reg [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV; + reg [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN; + reg [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD; + reg [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG; + reg [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD; + reg [1:0] RX_CM_SEL_REG = RX_CM_SEL; + reg [3:0] RX_CM_TRIM_REG = RX_CM_TRIM; + reg [0:0] RX_CTLE_PWR_SAVING_REG = RX_CTLE_PWR_SAVING; + reg [3:0] RX_CTLE_RES_CTRL_REG = RX_CTLE_RES_CTRL; + reg [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH; + reg [5:0] RX_DDI_SEL_REG = RX_DDI_SEL; + reg [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN; + reg [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL; + reg [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0; + reg [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1; + reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN; + reg [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1; + reg [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0; + reg [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1; + reg [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0; + reg [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1; + reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE; + reg [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH; + reg [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME; + reg [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B; + reg [0:0] RX_EN_SUM_RCAL_B_REG = RX_EN_SUM_RCAL_B; + reg [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE; + reg [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR; + reg [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE; + reg [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN; + reg [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP; + reg [0:0] RX_I2V_FILTER_EN_REG = RX_I2V_FILTER_EN; + reg [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH; + reg [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE; + reg [15:0] RX_PMA_RSV0_REG = RX_PMA_RSV0; + real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG; + reg [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE; + reg [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL; + reg [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD; + reg [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD; + reg [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY; + reg [0:0] RX_SUM_DEGEN_AVTT_OVERITE_REG = RX_SUM_DEGEN_AVTT_OVERITE; + reg [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN; + reg [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE; + reg [0:0] RX_SUM_PWR_SAVING_REG = RX_SUM_PWR_SAVING; + reg [3:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL; + reg [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE; + reg [0:0] RX_SUM_VCM_BIAS_TUNE_EN_REG = RX_SUM_VCM_BIAS_TUNE_EN; + reg [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR; + reg [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE; + reg [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS; + reg [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL; + reg [0:0] RX_VREG_PDB_REG = RX_VREG_PDB; + reg [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR; + reg [1:0] RX_WIDEMODE_CDR_GEN3_REG = RX_WIDEMODE_CDR_GEN3; + reg [1:0] RX_WIDEMODE_CDR_GEN4_REG = RX_WIDEMODE_CDR_GEN4; + reg [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL; + reg [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL; + reg [0:0] SAMPLE_CLK_PHASE_REG = SAMPLE_CLK_PHASE; + reg [0:0] SAS_12G_MODE_REG = SAS_12G_MODE; + reg [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN; + reg [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL; + reg [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG; + reg [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL; + reg [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA; + reg [160:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [48:1] SIM_MODE_REG = SIM_MODE; + reg [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS; + reg [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + reg [32:1] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL; + reg [0:0] SRSTMODE_REG = SRSTMODE; + reg [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX; + reg [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG; + reg [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD; + reg [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE; + reg [7:0] TST_RSV0_REG = TST_RSV0; + reg [7:0] TST_RSV1_REG = TST_RSV1; + reg [40:1] TXBUF_EN_REG = TXBUF_EN; + reg [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE; + reg [15:0] TXDLY_CFG_REG = TXDLY_CFG; + reg [15:0] TXDLY_LCFG_REG = TXDLY_LCFG; + reg [1:0] TXDRV_FREQBAND_REG = TXDRV_FREQBAND; + reg [15:0] TXFE_CFG0_REG = TXFE_CFG0; + reg [15:0] TXFE_CFG1_REG = TXFE_CFG1; + reg [15:0] TXFE_CFG2_REG = TXFE_CFG2; + reg [15:0] TXFE_CFG3_REG = TXFE_CFG3; + reg [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG; + reg [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR; + reg [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN; + reg [5:0] TXOUT_DIV_REG = TXOUT_DIV; + reg [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME; + reg [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0; + reg [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1; + reg [15:0] TXPH_CFG_REG = TXPH_CFG; + reg [15:0] TXPH_CFG2_REG = TXPH_CFG2; + reg [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL; + reg [15:0] TXPI_CFG0_REG = TXPI_CFG0; + reg [15:0] TXPI_CFG1_REG = TXPI_CFG1; + reg [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL; + reg [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL; + reg [0:0] TXPI_PPM_REG = TXPI_PPM; + reg [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG; + reg [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM; + reg [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME; + reg [0:0] TXREFCLKDIV2_SEL_REG = TXREFCLKDIV2_SEL; + reg [1:0] TXSWBST_BST_REG = TXSWBST_BST; + reg [0:0] TXSWBST_EN_REG = TXSWBST_EN; + reg [2:0] TXSWBST_MAG_REG = TXSWBST_MAG; + reg [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE; + reg [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD; + reg [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA; + reg [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV; + reg [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN; + reg [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH; + reg [15:0] TX_DCC_LOOP_RST_CFG_REG = TX_DCC_LOOP_RST_CFG; + reg [5:0] TX_DEEMPH0_REG = TX_DEEMPH0; + reg [5:0] TX_DEEMPH1_REG = TX_DEEMPH1; + reg [5:0] TX_DEEMPH2_REG = TX_DEEMPH2; + reg [5:0] TX_DEEMPH3_REG = TX_DEEMPH3; + reg [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME; + reg [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE; + reg [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY; + reg [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY; + reg [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP; + reg [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN; + reg [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO; + reg [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH; + reg [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ; + reg [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL; + reg [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0; + reg [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1; + reg [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2; + reg [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3; + reg [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4; + reg [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0; + reg [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1; + reg [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2; + reg [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3; + reg [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4; + reg [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0; + reg [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1; + reg [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET; + reg [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT; + reg [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE; + reg [15:0] TX_PMA_RSV0_REG = TX_PMA_RSV0; + reg [15:0] TX_PMA_RSV1_REG = TX_PMA_RSV1; + reg [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL; + real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG; + reg [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE; + reg [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG; + reg [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF; + reg [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD; + reg [1:0] TX_SW_MEAS_REG = TX_SW_MEAS; + reg [2:0] TX_VREG_CTRL_REG = TX_VREG_CTRL; + reg [0:0] TX_VREG_PDB_REG = TX_VREG_PDB; + reg [1:0] TX_VREG_VREFSEL_REG = TX_VREG_VREFSEL; + reg [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL; + reg [0:0] USB_BOTH_BURST_IDLE_REG = USB_BOTH_BURST_IDLE; + reg [6:0] USB_BURSTMAX_U3WAKE_REG = USB_BURSTMAX_U3WAKE; + reg [6:0] USB_BURSTMIN_U3WAKE_REG = USB_BURSTMIN_U3WAKE; + reg [0:0] USB_CLK_COR_EQ_EN_REG = USB_CLK_COR_EQ_EN; + reg [0:0] USB_EXT_CNTL_REG = USB_EXT_CNTL; + reg [9:0] USB_IDLEMAX_POLLING_REG = USB_IDLEMAX_POLLING; + reg [9:0] USB_IDLEMIN_POLLING_REG = USB_IDLEMIN_POLLING; + reg [8:0] USB_LFPSPING_BURST_REG = USB_LFPSPING_BURST; + reg [8:0] USB_LFPSPOLLING_BURST_REG = USB_LFPSPOLLING_BURST; + reg [8:0] USB_LFPSPOLLING_IDLE_MS_REG = USB_LFPSPOLLING_IDLE_MS; + reg [8:0] USB_LFPSU1EXIT_BURST_REG = USB_LFPSU1EXIT_BURST; + reg [8:0] USB_LFPSU2LPEXIT_BURST_MS_REG = USB_LFPSU2LPEXIT_BURST_MS; + reg [8:0] USB_LFPSU3WAKE_BURST_MS_REG = USB_LFPSU3WAKE_BURST_MS; + reg [3:0] USB_LFPS_TPERIOD_REG = USB_LFPS_TPERIOD; + reg [0:0] USB_LFPS_TPERIOD_ACCURATE_REG = USB_LFPS_TPERIOD_ACCURATE; + reg [0:0] USB_MODE_REG = USB_MODE; + reg [0:0] USB_PCIE_ERR_REP_DIS_REG = USB_PCIE_ERR_REP_DIS; + reg [5:0] USB_PING_SATA_MAX_INIT_REG = USB_PING_SATA_MAX_INIT; + reg [5:0] USB_PING_SATA_MIN_INIT_REG = USB_PING_SATA_MIN_INIT; + reg [5:0] USB_POLL_SATA_MAX_BURST_REG = USB_POLL_SATA_MAX_BURST; + reg [5:0] USB_POLL_SATA_MIN_BURST_REG = USB_POLL_SATA_MIN_BURST; + reg [0:0] USB_RAW_ELEC_REG = USB_RAW_ELEC; + reg [0:0] USB_RXIDLE_P0_CTRL_REG = USB_RXIDLE_P0_CTRL; + reg [0:0] USB_TXIDLE_TUNE_ENABLE_REG = USB_TXIDLE_TUNE_ENABLE; + reg [5:0] USB_U1_SATA_MAX_WAKE_REG = USB_U1_SATA_MAX_WAKE; + reg [5:0] USB_U1_SATA_MIN_WAKE_REG = USB_U1_SATA_MIN_WAKE; + reg [6:0] USB_U2_SAS_MAX_COM_REG = USB_U2_SAS_MAX_COM; + reg [5:0] USB_U2_SAS_MIN_COM_REG = USB_U2_SAS_MIN_COM; + reg [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL; + reg [0:0] Y_ALL_MODE_REG = Y_ALL_MODE; +`endif + + reg [0:0] AEN_CDRSTEPSEL_REG = 1'b0; + reg [0:0] AEN_CPLL_REG = 1'b0; + reg [0:0] AEN_LOOPBACK_REG = 1'b0; + reg [0:0] AEN_MASTER_REG = 1'b0; + reg [0:0] AEN_PD_AND_EIDLE_REG = 1'b0; + reg [0:0] AEN_POLARITY_REG = 1'b0; + reg [0:0] AEN_PRBS_REG = 1'b0; + reg [0:0] AEN_RESET_REG = 1'b0; + reg [0:0] AEN_RXCDR_REG = 1'b0; + reg [0:0] AEN_RXDFE_REG = 1'b0; + reg [0:0] AEN_RXDFELPM_REG = 1'b0; + reg [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0; + reg [0:0] AEN_RXPHDLY_REG = 1'b0; + reg [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0; + reg [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXMUXDCD_REG = 1'b0; + reg [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXPHDLY_REG = 1'b0; + reg [0:0] AEN_TXPI_PPM_REG = 1'b0; + reg [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0; + reg [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0; + reg [15:0] AMONITOR_CFG_REG = 16'h0FC0; + reg [0:0] A_CPLLLOCKEN_REG = 1'b0; + reg [0:0] A_CPLLPD_REG = 1'b0; + reg [0:0] A_CPLLRESET_REG = 1'b0; + reg [0:0] A_EYESCANRESET_REG = 1'b0; + reg [0:0] A_GTRESETSEL_REG = 1'b0; + reg [0:0] A_GTRXRESET_REG = 1'b0; + reg [0:0] A_GTTXRESET_REG = 1'b0; + reg [80:1] A_LOOPBACK_REG = "NOLOOPBACK"; + reg [0:0] A_RXAFECFOKEN_REG = 1'b1; + reg [0:0] A_RXBUFRESET_REG = 1'b0; + reg [0:0] A_RXCDRFREQRESET_REG = 1'b0; + reg [0:0] A_RXCDRHOLD_REG = 1'b0; + reg [0:0] A_RXCDROVRDEN_REG = 1'b0; + reg [0:0] A_RXCDRRESET_REG = 1'b0; + reg [0:0] A_RXCKCALRESET_REG = 1'b0; + reg [0:0] A_RXDFEAGCHOLD_REG = 1'b0; + reg [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0; + reg [3:0] A_RXDFECFOKFCNUM_REG = 4'b0000; + reg [0:0] A_RXDFECFOKFEN_REG = 1'b0; + reg [0:0] A_RXDFECFOKFPULSE_REG = 1'b0; + reg [0:0] A_RXDFECFOKHOLD_REG = 1'b0; + reg [0:0] A_RXDFECFOKOVREN_REG = 1'b0; + reg [0:0] A_RXDFEKHHOLD_REG = 0; + reg [0:0] A_RXDFEKHOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFELFHOLD_REG = 1'b0; + reg [0:0] A_RXDFELFOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFELPMRESET_REG = 1'b0; + reg [0:0] A_RXDFETAP10HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP11HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP12HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP13HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP14HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP15HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP2HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP3HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP4HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP5HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP6HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP7HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP8HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFETAP9HOLD_REG = 1'b0; + reg [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEUTHOLD_REG = 1'b0; + reg [0:0] A_RXDFEUTOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEVPHOLD_REG = 1'b0; + reg [0:0] A_RXDFEVPOVRDEN_REG = 1'b0; + reg [0:0] A_RXDFEXYDEN_REG = 1'b0; + reg [0:0] A_RXDLYBYPASS_REG = 1'b0; + reg [0:0] A_RXDLYEN_REG = 1'b0; + reg [0:0] A_RXDLYOVRDEN_REG = 1'b0; + reg [0:0] A_RXDLYSRESET_REG = 1'b0; + reg [0:0] A_RXLPMEN_REG = 1'b0; + reg [0:0] A_RXLPMGCHOLD_REG = 1'b0; + reg [0:0] A_RXLPMGCOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMHFHOLD_REG = 1'b0; + reg [0:0] A_RXLPMHFOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMLFHOLD_REG = 1'b0; + reg [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0; + reg [0:0] A_RXLPMOSHOLD_REG = 1'b0; + reg [0:0] A_RXLPMOSOVRDEN_REG = 1'b0; + reg [1:0] A_RXMONITORSEL_REG = 2'b00; + reg [0:0] A_RXOOBRESET_REG = 1'b0; + reg [0:0] A_RXOSHOLD_REG = 1'b0; + reg [0:0] A_RXOSOVRDEN_REG = 1'b0; + reg [128:1] A_RXOUTCLKSEL_REG = "DISABLED"; + reg [0:0] A_RXPCSRESET_REG = 1'b0; + reg [24:1] A_RXPD_REG = "P0"; + reg [0:0] A_RXPHALIGN_REG = 1'b0; + reg [0:0] A_RXPHALIGNEN_REG = 1'b0; + reg [0:0] A_RXPHDLYPD_REG = 1'b0; + reg [0:0] A_RXPHDLYRESET_REG = 1'b0; + reg [64:1] A_RXPLLCLKSEL_REG = "QPLLCLK1"; + reg [0:0] A_RXPMARESET_REG = 1'b0; + reg [0:0] A_RXPOLARITY_REG = 1'b0; + reg [0:0] A_RXPRBSCNTRESET_REG = 1'b0; + reg [48:1] A_RXPRBSSEL_REG = "PRBS7"; + reg [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK"; + reg [2:0] A_TXBUFDIFFCTRL_REG = 3'b100; + reg [0:0] A_TXDCCRESET_REG = 1'b0; + reg [1:0] A_TXDEEMPH_REG = 2'b00; + reg [0:0] A_TXDLYBYPASS_REG = 1'b0; + reg [0:0] A_TXDLYEN_REG = 1'b0; + reg [0:0] A_TXDLYOVRDEN_REG = 1'b0; + reg [0:0] A_TXDLYSRESET_REG = 1'b0; + reg [0:0] A_TXELECIDLE_REG = 1'b0; + reg [0:0] A_TXINHIBIT_REG = 1'b0; + reg [6:0] A_TXMAINCURSOR_REG = 7'b0000000; + reg [2:0] A_TXMARGIN_REG = 3'b000; + reg [0:0] A_TXMUXDCDEXHOLD_REG = 1'b0; + reg [0:0] A_TXMUXDCDORWREN_REG = 1'b0; + reg [128:1] A_TXOUTCLKSEL_REG = "DISABLED"; + reg [0:0] A_TXPCSRESET_REG = 1'b0; + reg [24:1] A_TXPD_REG = "P0"; + reg [0:0] A_TXPHALIGN_REG = 1'b0; + reg [0:0] A_TXPHALIGNEN_REG = 1'b0; + reg [0:0] A_TXPHDLYPD_REG = 1'b0; + reg [0:0] A_TXPHDLYRESET_REG = 1'b0; + reg [0:0] A_TXPHINIT_REG = 1'b0; + reg [0:0] A_TXPHOVRDEN_REG = 1'b0; + reg [0:0] A_TXPIPPMOVRDEN_REG = 1'b0; + reg [0:0] A_TXPIPPMPD_REG = 1'b0; + reg [0:0] A_TXPIPPMSEL_REG = 1'b0; + reg [64:1] A_TXPLLCLKSEL_REG = "QPLLCLK1"; + reg [0:0] A_TXPMARESET_REG = 1'b0; + reg [0:0] A_TXPOLARITY_REG = 1'b0; + reg [4:0] A_TXPOSTCURSOR_REG = 5'b00000; + reg [0:0] A_TXPRBSFORCEERR_REG = 1'b0; + reg [96:1] A_TXPRBSSEL_REG = "PRBS7"; + reg [4:0] A_TXPRECURSOR_REG = 5'b00000; + reg [0:0] A_TXRESETSEL_REG = 1'b0; + reg [0:0] A_TXSWING_REG = 1'b0; + reg [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK"; + reg [1:0] BSR_ENABLE_REG = 2'b00; + reg [15:0] CSSD_CLK_MASK0_REG = 16'b0000000000000000; + reg [15:0] CSSD_CLK_MASK1_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG0_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG1_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG10_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG2_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG3_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG4_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG5_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG6_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG7_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG8_REG = 16'b0000000000000000; + reg [15:0] CSSD_REG9_REG = 16'b0000000000000000; + reg [40:1] GEN_RXUSRCLK_REG = "TRUE"; + reg [40:1] GEN_TXUSRCLK_REG = "TRUE"; + reg [0:0] GT_INSTANTIATED_REG = 1'b1; + reg [15:0] INT_MASK_CFG0_REG = 16'b0000000000000000; + reg [15:0] INT_MASK_CFG1_REG = 16'b0000000000000000; + reg [5:0] RX_DFECFOKFCDAC_REG = 6'b000000; + reg [1:0] RX_VREG_VREFSEL_REG = 2'b01; + reg [0:0] TXOUTCLKPCS_SEL_REG = 1'b0; + reg [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100; + reg [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101; + reg [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011; + reg [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010; + reg [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100; + reg [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101; + reg [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011; + reg [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010; + +`ifdef XIL_XECLIB + wire [63:0] RX_PROGDIV_CFG_BIN; + wire [63:0] TX_PROGDIV_CFG_BIN; +`else + reg [63:0] RX_PROGDIV_CFG_BIN; + reg [63:0] TX_PROGDIV_CFG_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire BUFGTCE_out; + wire BUFGTRESET_out; + wire CPLLFBCLKLOST_out; + wire CPLLLOCK_out; + wire CPLLREFCLKLOST_out; + wire CSSDSTOPCLKDONE_out; + wire DMONITOROUTCLK_out; + wire DRPRDY_out; + wire EYESCANDATAERROR_out; + wire GTPOWERGOOD_out; + wire GTREFCLKMONITOR_out; + wire GTYTXN_out; + wire GTYTXP_out; + wire PCIERATEGEN3_out; + wire PCIERATEIDLE_out; + wire PCIESYNCTXSYNCDONE_out; + wire PCIEUSERGEN3RDY_out; + wire PCIEUSERPHYSTATUSRST_out; + wire PCIEUSERRATESTART_out; + wire PHYSTATUS_out; + wire POWERPRESENT_out; + wire RESETEXCEPTION_out; + wire RXBYTEISALIGNED_out; + wire RXBYTEREALIGN_out; + wire RXCDRLOCK_out; + wire RXCDRPHDONE_out; + wire RXCHANBONDSEQ_out; + wire RXCHANISALIGNED_out; + wire RXCHANREALIGN_out; + wire RXCKCALDONE_out; + wire RXCOMINITDET_out; + wire RXCOMMADET_out; + wire RXCOMSASDET_out; + wire RXCOMWAKEDET_out; + wire RXDLYSRESETDONE_out; + wire RXELECIDLE_out; + wire RXLFPSTRESETDET_out; + wire RXLFPSU2LPEXITDET_out; + wire RXLFPSU3WAKEDET_out; + wire RXOSINTDONE_out; + wire RXOSINTSTARTED_out; + wire RXOSINTSTROBEDONE_out; + wire RXOSINTSTROBESTARTED_out; + wire RXOUTCLKFABRIC_out; + wire RXOUTCLKPCS_out; + wire RXOUTCLK_out; + wire RXPHALIGNDONE_out; + wire RXPHALIGNERR_out; + wire RXPMARESETDONE_out; + wire RXPRBSERR_out; + wire RXPRBSLOCKED_out; + wire RXPRGDIVRESETDONE_out; + wire RXRATEDONE_out; + wire RXRECCLKOUT_out; + wire RXRESETDONE_out; + wire RXSLIDERDY_out; + wire RXSLIPDONE_out; + wire RXSLIPOUTCLKRDY_out; + wire RXSLIPPMARDY_out; + wire RXSYNCDONE_out; + wire RXSYNCOUT_out; + wire RXVALID_out; + wire TXCOMFINISH_out; + wire TXDCCDONE_out; + wire TXDLYSRESETDONE_out; + wire TXOUTCLKFABRIC_out; + wire TXOUTCLKPCS_out; + wire TXOUTCLK_out; + wire TXPHALIGNDONE_out; + wire TXPHINITDONE_out; + wire TXPMARESETDONE_out; + wire TXPRGDIVRESETDONE_out; + wire TXRATEDONE_out; + wire TXRESETDONE_out; + wire TXSYNCDONE_out; + wire TXSYNCOUT_out; + wire [127:0] RXDATA_out; + wire [15:0] DMONITOROUT_out; + wire [15:0] DRPDO_out; + wire [15:0] PCSRSVDOUT_out; + wire [15:0] PINRSRVDAS_out; + wire [15:0] RXCTRL0_out; + wire [15:0] RXCTRL1_out; + wire [17:0] PMASCANOUT_out; + wire [18:0] SCANOUT_out; + wire [1:0] PCIERATEQPLLPD_out; + wire [1:0] PCIERATEQPLLRESET_out; + wire [1:0] RXCLKCORCNT_out; + wire [1:0] RXDATAVALID_out; + wire [1:0] RXHEADERVALID_out; + wire [1:0] RXSTARTOFSEQ_out; + wire [1:0] TXBUFSTATUS_out; + wire [2:0] BUFGTCEMASK_out; + wire [2:0] BUFGTRSTMASK_out; + wire [2:0] RXBUFSTATUS_out; + wire [2:0] RXSTATUS_out; + wire [4:0] RXCHBONDO_out; + wire [5:0] RXHEADER_out; + wire [7:0] RXCTRL2_out; + wire [7:0] RXCTRL3_out; + wire [7:0] RXDATAEXTENDRSVD_out; + wire [7:0] RXMONITOROUT_out; + wire [8:0] BUFGTDIV_out; + + wire BSR_SERIAL_in; + wire CDRSTEPDIR_in; + wire CDRSTEPSQ_in; + wire CDRSTEPSX_in; + wire CFGRESET_in; + wire CLKRSVD0_in; + wire CLKRSVD1_in; + wire CPLLFREQLOCK_in; + wire CPLLLOCKDETCLK_in; + wire CPLLLOCKEN_in; + wire CPLLPD_in; + wire CPLLRESET_in; + wire CSSDRSTB_in; + wire CSSDSTOPCLK_in; + wire DMONFIFORESET_in; + wire DMONITORCLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPRST_in; + wire DRPWE_in; + wire EYESCANRESET_in; + wire EYESCANTRIGGER_in; + wire FREQOS_in; + wire GTGREFCLK_in; + wire GTNORTHREFCLK0_in; + wire GTNORTHREFCLK1_in; + wire GTREFCLK0_in; + wire GTREFCLK1_in; + wire GTRXRESETSEL_in; + wire GTRXRESET_in; + wire GTSOUTHREFCLK0_in; + wire GTSOUTHREFCLK1_in; + wire GTTXRESETSEL_in; + wire GTTXRESET_in; + wire GTYRXN_in; + wire GTYRXP_in; + wire INCPCTRL_in; + wire PCIEEQRXEQADAPTDONE_in; + wire PCIERSTIDLE_in; + wire PCIERSTTXSYNCSTART_in; + wire PCIEUSERRATEDONE_in; + wire PMASCANCLK0_in; + wire PMASCANCLK1_in; + wire PMASCANCLK2_in; + wire PMASCANCLK3_in; + wire PMASCANCLK4_in; + wire PMASCANCLK5_in; + wire PMASCANCLK6_in; + wire PMASCANCLK7_in; + wire PMASCANCLK8_in; + wire PMASCANENB_in; + wire PMASCANMODEB_in; + wire PMASCANRSTEN_in; + wire QPLL0CLK_in; + wire QPLL0FREQLOCK_in; + wire QPLL0REFCLK_in; + wire QPLL1CLK_in; + wire QPLL1FREQLOCK_in; + wire QPLL1REFCLK_in; + wire RESETOVRD_in; + wire RX8B10BEN_in; + wire RXAFECFOKEN_in; + wire RXBUFRESET_in; + wire RXCDRFREQRESET_in; + wire RXCDRHOLD_in; + wire RXCDROVRDEN_in; + wire RXCDRRESET_in; + wire RXCHBONDEN_in; + wire RXCHBONDMASTER_in; + wire RXCHBONDSLAVE_in; + wire RXCKCALRESET_in; + wire RXCOMMADETEN_in; + wire RXDFEAGCHOLD_in; + wire RXDFEAGCOVRDEN_in; + wire RXDFECFOKFEN_in; + wire RXDFECFOKFPULSE_in; + wire RXDFECFOKHOLD_in; + wire RXDFECFOKOVREN_in; + wire RXDFEKHHOLD_in; + wire RXDFEKHOVRDEN_in; + wire RXDFELFHOLD_in; + wire RXDFELFOVRDEN_in; + wire RXDFELPMRESET_in; + wire RXDFETAP10HOLD_in; + wire RXDFETAP10OVRDEN_in; + wire RXDFETAP11HOLD_in; + wire RXDFETAP11OVRDEN_in; + wire RXDFETAP12HOLD_in; + wire RXDFETAP12OVRDEN_in; + wire RXDFETAP13HOLD_in; + wire RXDFETAP13OVRDEN_in; + wire RXDFETAP14HOLD_in; + wire RXDFETAP14OVRDEN_in; + wire RXDFETAP15HOLD_in; + wire RXDFETAP15OVRDEN_in; + wire RXDFETAP2HOLD_in; + wire RXDFETAP2OVRDEN_in; + wire RXDFETAP3HOLD_in; + wire RXDFETAP3OVRDEN_in; + wire RXDFETAP4HOLD_in; + wire RXDFETAP4OVRDEN_in; + wire RXDFETAP5HOLD_in; + wire RXDFETAP5OVRDEN_in; + wire RXDFETAP6HOLD_in; + wire RXDFETAP6OVRDEN_in; + wire RXDFETAP7HOLD_in; + wire RXDFETAP7OVRDEN_in; + wire RXDFETAP8HOLD_in; + wire RXDFETAP8OVRDEN_in; + wire RXDFETAP9HOLD_in; + wire RXDFETAP9OVRDEN_in; + wire RXDFEUTHOLD_in; + wire RXDFEUTOVRDEN_in; + wire RXDFEVPHOLD_in; + wire RXDFEVPOVRDEN_in; + wire RXDFEXYDEN_in; + wire RXDLYBYPASS_in; + wire RXDLYEN_in; + wire RXDLYOVRDEN_in; + wire RXDLYSRESET_in; + wire RXEQTRAINING_in; + wire RXGEARBOXSLIP_in; + wire RXLATCLK_in; + wire RXLPMEN_in; + wire RXLPMGCHOLD_in; + wire RXLPMGCOVRDEN_in; + wire RXLPMHFHOLD_in; + wire RXLPMHFOVRDEN_in; + wire RXLPMLFHOLD_in; + wire RXLPMLFKLOVRDEN_in; + wire RXLPMOSHOLD_in; + wire RXLPMOSOVRDEN_in; + wire RXMCOMMAALIGNEN_in; + wire RXOOBRESET_in; + wire RXOSCALRESET_in; + wire RXOSHOLD_in; + wire RXOSOVRDEN_in; + wire RXPCOMMAALIGNEN_in; + wire RXPCSRESET_in; + wire RXPHALIGNEN_in; + wire RXPHALIGN_in; + wire RXPHDLYPD_in; + wire RXPHDLYRESET_in; + wire RXPMARESET_in; + wire RXPOLARITY_in; + wire RXPRBSCNTRESET_in; + wire RXPROGDIVRESET_in; + wire RXRATEMODE_in; + wire RXSLIDE_in; + wire RXSLIPOUTCLK_in; + wire RXSLIPPMA_in; + wire RXSYNCALLIN_in; + wire RXSYNCIN_in; + wire RXSYNCMODE_in; + wire RXTERMINATION_in; + wire RXUSERRDY_in; + wire RXUSRCLK2_in; + wire RXUSRCLK_in; + wire SARCCLK_in; + wire SCANCLK_in; + wire SCANENB_in; + wire SCANMODEB_in; + wire SCANRSTB_in; + wire SCANRSTEN_in; + wire SIGVALIDCLK_in; + wire TSTCLK0_in; + wire TSTCLK1_in; + wire TSTPDOVRDB_in; + wire TX8B10BEN_in; + wire TXCOMINIT_in; + wire TXCOMSAS_in; + wire TXCOMWAKE_in; + wire TXDCCFORCESTART_in; + wire TXDCCRESET_in; + wire TXDETECTRX_in; + wire TXDLYBYPASS_in; + wire TXDLYEN_in; + wire TXDLYHOLD_in; + wire TXDLYOVRDEN_in; + wire TXDLYSRESET_in; + wire TXDLYUPDOWN_in; + wire TXELECIDLE_in; + wire TXINHIBIT_in; + wire TXLATCLK_in; + wire TXLFPSTRESET_in; + wire TXLFPSU2LPEXIT_in; + wire TXLFPSU3WAKE_in; + wire TXMUXDCDEXHOLD_in; + wire TXMUXDCDORWREN_in; + wire TXONESZEROS_in; + wire TXPCSRESET_in; + wire TXPDELECIDLEMODE_in; + wire TXPHALIGNEN_in; + wire TXPHALIGN_in; + wire TXPHDLYPD_in; + wire TXPHDLYRESET_in; + wire TXPHDLYTSTCLK_in; + wire TXPHINIT_in; + wire TXPHOVRDEN_in; + wire TXPIPPMEN_in; + wire TXPIPPMOVRDEN_in; + wire TXPIPPMPD_in; + wire TXPIPPMSEL_in; + wire TXPISOPD_in; + wire TXPMARESET_in; + wire TXPOLARITY_in; + wire TXPRBSFORCEERR_in; + wire TXPROGDIVRESET_in; + wire TXRATEMODE_in; + wire TXSWING_in; + wire TXSYNCALLIN_in; + wire TXSYNCIN_in; + wire TXSYNCMODE_in; + wire TXUSERRDY_in; + wire TXUSRCLK2_in; + wire TXUSRCLK_in; + wire [127:0] TXDATA_in; + wire [15:0] DRPDI_in; + wire [15:0] GTRSVD_in; + wire [15:0] PCSRSVDIN_in; + wire [15:0] TXCTRL0_in; + wire [15:0] TXCTRL1_in; + wire [17:0] PMASCANIN_in; + wire [18:0] SCANIN_in; + wire [19:0] TSTIN_in; + wire [1:0] RXELECIDLEMODE_in; + wire [1:0] RXMONITORSEL_in; + wire [1:0] RXPD_in; + wire [1:0] RXPLLCLKSEL_in; + wire [1:0] RXSYSCLKSEL_in; + wire [1:0] TXDEEMPH_in; + wire [1:0] TXPD_in; + wire [1:0] TXPLLCLKSEL_in; + wire [1:0] TXSYSCLKSEL_in; + wire [2:0] CPLLREFCLKSEL_in; + wire [2:0] LOOPBACK_in; + wire [2:0] RXCHBONDLEVEL_in; + wire [2:0] RXOUTCLKSEL_in; + wire [2:0] RXRATE_in; + wire [2:0] TXMARGIN_in; + wire [2:0] TXOUTCLKSEL_in; + wire [2:0] TXRATE_in; + wire [3:0] RXDFECFOKFCNUM_in; + wire [3:0] RXPRBSSEL_in; + wire [3:0] TXPRBSSEL_in; + wire [4:0] RXCHBONDI_in; + wire [4:0] TSTPD_in; + wire [4:0] TXDIFFCTRL_in; + wire [4:0] TXPIPPMSTEPSIZE_in; + wire [4:0] TXPOSTCURSOR_in; + wire [4:0] TXPRECURSOR_in; + wire [5:0] TXHEADER_in; + wire [6:0] RXCKCALSTART_in; + wire [6:0] TXMAINCURSOR_in; + wire [6:0] TXSEQUENCE_in; + wire [7:0] TX8B10BBYPASS_in; + wire [7:0] TXCTRL2_in; + wire [7:0] TXDATAEXTENDRSVD_in; + wire [9:0] DRPADDR_in; + + wire gt_intclk; + reg gt_clk_int; + +`ifdef XIL_TIMING + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire RX8B10BEN_delay; + wire RXCHBONDEN_delay; + wire RXCHBONDMASTER_delay; + wire RXCHBONDSLAVE_delay; + wire RXCOMMADETEN_delay; + wire RXGEARBOXSLIP_delay; + wire RXMCOMMAALIGNEN_delay; + wire RXPCOMMAALIGNEN_delay; + wire RXPOLARITY_delay; + wire RXPRBSCNTRESET_delay; + wire RXSLIDE_delay; + wire RXSLIPOUTCLK_delay; + wire RXSLIPPMA_delay; + wire RXUSRCLK2_delay; + wire RXUSRCLK_delay; + wire TX8B10BEN_delay; + wire TXCOMINIT_delay; + wire TXCOMSAS_delay; + wire TXCOMWAKE_delay; + wire TXDETECTRX_delay; + wire TXELECIDLE_delay; + wire TXINHIBIT_delay; + wire TXPOLARITY_delay; + wire TXPRBSFORCEERR_delay; + wire TXUSRCLK2_delay; + wire [127:0] TXDATA_delay; + wire [15:0] DRPDI_delay; + wire [15:0] TXCTRL0_delay; + wire [15:0] TXCTRL1_delay; + wire [1:0] TXPD_delay; + wire [2:0] RXCHBONDLEVEL_delay; + wire [2:0] RXRATE_delay; + wire [2:0] TXRATE_delay; + wire [3:0] RXPRBSSEL_delay; + wire [3:0] TXPRBSSEL_delay; + wire [4:0] RXCHBONDI_delay; + wire [5:0] TXHEADER_delay; + wire [6:0] TXSEQUENCE_delay; + wire [7:0] TX8B10BBYPASS_delay; + wire [7:0] TXCTRL2_delay; + wire [9:0] DRPADDR_delay; +`endif + + assign BUFGTCE = BUFGTCE_out; + assign BUFGTCEMASK = BUFGTCEMASK_out; + assign BUFGTDIV = BUFGTDIV_out; + assign BUFGTRESET = BUFGTRESET_out; + assign BUFGTRSTMASK = BUFGTRSTMASK_out; + assign CPLLFBCLKLOST = CPLLFBCLKLOST_out; + assign CPLLLOCK = CPLLLOCK_out; + assign CPLLREFCLKLOST = CPLLREFCLKLOST_out; + assign DMONITOROUT = DMONITOROUT_out; + assign DMONITOROUTCLK = DMONITOROUTCLK_out; + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign EYESCANDATAERROR = EYESCANDATAERROR_out; + assign GTPOWERGOOD = GTPOWERGOOD_out; + assign GTREFCLKMONITOR = GTREFCLKMONITOR_out; + assign GTYTXN = GTYTXN_out; + assign GTYTXP = GTYTXP_out; + assign PCIERATEGEN3 = PCIERATEGEN3_out; + assign PCIERATEIDLE = PCIERATEIDLE_out; + assign PCIERATEQPLLPD = PCIERATEQPLLPD_out; + assign PCIERATEQPLLRESET = PCIERATEQPLLRESET_out; + assign PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_out; + assign PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_out; + assign PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_out; + assign PCIEUSERRATESTART = PCIEUSERRATESTART_out; + assign PCSRSVDOUT = PCSRSVDOUT_out; + assign PHYSTATUS = PHYSTATUS_out; + assign PINRSRVDAS = PINRSRVDAS_out; + assign POWERPRESENT = POWERPRESENT_out; + assign RESETEXCEPTION = RESETEXCEPTION_out; + assign RXBUFSTATUS = RXBUFSTATUS_out; + assign RXBYTEISALIGNED = RXBYTEISALIGNED_out; + assign RXBYTEREALIGN = RXBYTEREALIGN_out; + assign RXCDRLOCK = RXCDRLOCK_out; + assign RXCDRPHDONE = RXCDRPHDONE_out; + assign RXCHANBONDSEQ = RXCHANBONDSEQ_out; + assign RXCHANISALIGNED = RXCHANISALIGNED_out; + assign RXCHANREALIGN = RXCHANREALIGN_out; + assign RXCHBONDO = RXCHBONDO_out; + assign RXCKCALDONE = RXCKCALDONE_out; + assign RXCLKCORCNT = RXCLKCORCNT_out; + assign RXCOMINITDET = RXCOMINITDET_out; + assign RXCOMMADET = RXCOMMADET_out; + assign RXCOMSASDET = RXCOMSASDET_out; + assign RXCOMWAKEDET = RXCOMWAKEDET_out; + assign RXCTRL0 = RXCTRL0_out; + assign RXCTRL1 = RXCTRL1_out; + assign RXCTRL2 = RXCTRL2_out; + assign RXCTRL3 = RXCTRL3_out; + assign RXDATA = RXDATA_out; + assign RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_out; + assign RXDATAVALID = RXDATAVALID_out; + assign RXDLYSRESETDONE = RXDLYSRESETDONE_out; + assign RXELECIDLE = RXELECIDLE_out; + assign RXHEADER = RXHEADER_out; + assign RXHEADERVALID = RXHEADERVALID_out; + assign RXLFPSTRESETDET = RXLFPSTRESETDET_out; + assign RXLFPSU2LPEXITDET = RXLFPSU2LPEXITDET_out; + assign RXLFPSU3WAKEDET = RXLFPSU3WAKEDET_out; + assign RXMONITOROUT = RXMONITOROUT_out; + assign RXOSINTDONE = RXOSINTDONE_out; + assign RXOSINTSTARTED = RXOSINTSTARTED_out; + assign RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_out; + assign RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_out; + assign RXOUTCLK = RXOUTCLK_out; + assign RXOUTCLKFABRIC = RXOUTCLKFABRIC_out; + + //EL + //assign RXOUTCLKPCS = RXOUTCLKPCS_out; + assign RXOUTCLKPCS = (RXPD_in == 2'b11) ? gt_intclk : RXOUTCLKPCS_out; + + assign RXPHALIGNDONE = RXPHALIGNDONE_out; + assign RXPHALIGNERR = RXPHALIGNERR_out; + assign RXPMARESETDONE = RXPMARESETDONE_out; + assign RXPRBSERR = RXPRBSERR_out; + assign RXPRBSLOCKED = RXPRBSLOCKED_out; + assign RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_out; + assign RXRATEDONE = RXRATEDONE_out; + assign RXRECCLKOUT = RXRECCLKOUT_out; + assign RXRESETDONE = RXRESETDONE_out; + assign RXSLIDERDY = RXSLIDERDY_out; + assign RXSLIPDONE = RXSLIPDONE_out; + assign RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_out; + assign RXSLIPPMARDY = RXSLIPPMARDY_out; + assign RXSTARTOFSEQ = RXSTARTOFSEQ_out; + assign RXSTATUS = RXSTATUS_out; + assign RXSYNCDONE = RXSYNCDONE_out; + assign RXSYNCOUT = RXSYNCOUT_out; + assign RXVALID = RXVALID_out; + assign TXBUFSTATUS = TXBUFSTATUS_out; + assign TXCOMFINISH = TXCOMFINISH_out; + assign TXDCCDONE = TXDCCDONE_out; + assign TXDLYSRESETDONE = TXDLYSRESETDONE_out; + + //EL + //assign TXOUTCLK = TXOUTCLK_out; + assign TXOUTCLK = (TXPISOPD_in && TXOUTCLKSEL_in == 3'b101) ? gt_intclk : TXOUTCLK_out; + + assign TXOUTCLKFABRIC = TXOUTCLKFABRIC_out; + assign TXOUTCLKPCS = TXPISOPD_in ? gt_intclk : TXOUTCLKPCS_out; + assign TXPHALIGNDONE = TXPHALIGNDONE_out; + assign TXPHINITDONE = TXPHINITDONE_out; + assign TXPMARESETDONE = TXPMARESETDONE_out; + assign TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_out; + assign TXRATEDONE = TXRATEDONE_out; + assign TXRESETDONE = TXRESETDONE_out; + assign TXSYNCDONE = TXSYNCDONE_out; + assign TXSYNCOUT = TXSYNCOUT_out; + +`ifdef XIL_TIMING + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0 + assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0 + assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0 + assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0 + assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0 + assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0 + assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0 + assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0 + assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0 + assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0 +`else + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN; // rv 0 + assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN; // rv 0 + assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI[0]; // rv 0 + assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI[1]; // rv 0 + assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI[2]; // rv 0 + assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI[3]; // rv 0 + assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI[4]; // rv 0 + assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL[0]; // rv 0 + assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL[1]; // rv 0 + assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL[2]; // rv 0 + assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER; // rv 0 + assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE; // rv 0 + assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN; // rv 0 + assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP; // rv 0 + assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN; // rv 0 + assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN; // rv 0 + assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY; // rv 0 + assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET; // rv 0 + assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL[0]; // rv 0 + assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL[1]; // rv 0 + assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL[2]; // rv 0 + assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL[3]; // rv 0 + assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE[0]; // rv 0 + assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE[1]; // rv 0 + assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE[2]; // rv 0 + assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE; // rv 0 + assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK; // rv 0 + assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA; // rv 0 + assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2; // rv 0 + assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK; // rv 0 + assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS[0]; // rv 0 + assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS[1]; // rv 0 + assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS[2]; // rv 0 + assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS[3]; // rv 0 + assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS[4]; // rv 0 + assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS[5]; // rv 0 + assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS[6]; // rv 0 + assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS[7]; // rv 0 + assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN; // rv 0 + assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT; // rv 0 + assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS; // rv 0 + assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE; // rv 0 + assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0[0]; // rv 0 + assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0[10]; // rv 0 + assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0[11]; // rv 0 + assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0[12]; // rv 0 + assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0[13]; // rv 0 + assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0[14]; // rv 0 + assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0[15]; // rv 0 + assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0[1]; // rv 0 + assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0[2]; // rv 0 + assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0[3]; // rv 0 + assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0[4]; // rv 0 + assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0[5]; // rv 0 + assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0[6]; // rv 0 + assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0[7]; // rv 0 + assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0[8]; // rv 0 + assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0[9]; // rv 0 + assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1[0]; // rv 0 + assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1[10]; // rv 0 + assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1[11]; // rv 0 + assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1[12]; // rv 0 + assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1[13]; // rv 0 + assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1[14]; // rv 0 + assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1[15]; // rv 0 + assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1[1]; // rv 0 + assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1[2]; // rv 0 + assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1[3]; // rv 0 + assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1[4]; // rv 0 + assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1[5]; // rv 0 + assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1[6]; // rv 0 + assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1[7]; // rv 0 + assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1[8]; // rv 0 + assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1[9]; // rv 0 + assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2[0]; // rv 0 + assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2[1]; // rv 0 + assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2[2]; // rv 0 + assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2[3]; // rv 0 + assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2[4]; // rv 0 + assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2[5]; // rv 0 + assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2[6]; // rv 0 + assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2[7]; // rv 0 + assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA[0]; // rv 0 + assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA[100]; // rv 0 + assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA[101]; // rv 0 + assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA[102]; // rv 0 + assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA[103]; // rv 0 + assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA[104]; // rv 0 + assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA[105]; // rv 0 + assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA[106]; // rv 0 + assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA[107]; // rv 0 + assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA[108]; // rv 0 + assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA[109]; // rv 0 + assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA[10]; // rv 0 + assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA[110]; // rv 0 + assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA[111]; // rv 0 + assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA[112]; // rv 0 + assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA[113]; // rv 0 + assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA[114]; // rv 0 + assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA[115]; // rv 0 + assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA[116]; // rv 0 + assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA[117]; // rv 0 + assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA[118]; // rv 0 + assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA[119]; // rv 0 + assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA[11]; // rv 0 + assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA[120]; // rv 0 + assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA[121]; // rv 0 + assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA[122]; // rv 0 + assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA[123]; // rv 0 + assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA[124]; // rv 0 + assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA[125]; // rv 0 + assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA[126]; // rv 0 + assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA[127]; // rv 0 + assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA[12]; // rv 0 + assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA[13]; // rv 0 + assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA[14]; // rv 0 + assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA[15]; // rv 0 + assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA[16]; // rv 0 + assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA[17]; // rv 0 + assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA[18]; // rv 0 + assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA[19]; // rv 0 + assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA[1]; // rv 0 + assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA[20]; // rv 0 + assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA[21]; // rv 0 + assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA[22]; // rv 0 + assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA[23]; // rv 0 + assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA[24]; // rv 0 + assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA[25]; // rv 0 + assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA[26]; // rv 0 + assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA[27]; // rv 0 + assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA[28]; // rv 0 + assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA[29]; // rv 0 + assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA[2]; // rv 0 + assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA[30]; // rv 0 + assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA[31]; // rv 0 + assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA[32]; // rv 0 + assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA[33]; // rv 0 + assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA[34]; // rv 0 + assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA[35]; // rv 0 + assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA[36]; // rv 0 + assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA[37]; // rv 0 + assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA[38]; // rv 0 + assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA[39]; // rv 0 + assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA[3]; // rv 0 + assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA[40]; // rv 0 + assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA[41]; // rv 0 + assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA[42]; // rv 0 + assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA[43]; // rv 0 + assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA[44]; // rv 0 + assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA[45]; // rv 0 + assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA[46]; // rv 0 + assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA[47]; // rv 0 + assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA[48]; // rv 0 + assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA[49]; // rv 0 + assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA[4]; // rv 0 + assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA[50]; // rv 0 + assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA[51]; // rv 0 + assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA[52]; // rv 0 + assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA[53]; // rv 0 + assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA[54]; // rv 0 + assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA[55]; // rv 0 + assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA[56]; // rv 0 + assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA[57]; // rv 0 + assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA[58]; // rv 0 + assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA[59]; // rv 0 + assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA[5]; // rv 0 + assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA[60]; // rv 0 + assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA[61]; // rv 0 + assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA[62]; // rv 0 + assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA[63]; // rv 0 + assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA[64]; // rv 0 + assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA[65]; // rv 0 + assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA[66]; // rv 0 + assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA[67]; // rv 0 + assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA[68]; // rv 0 + assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA[69]; // rv 0 + assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA[6]; // rv 0 + assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA[70]; // rv 0 + assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA[71]; // rv 0 + assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA[72]; // rv 0 + assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA[73]; // rv 0 + assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA[74]; // rv 0 + assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA[75]; // rv 0 + assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA[76]; // rv 0 + assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA[77]; // rv 0 + assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA[78]; // rv 0 + assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA[79]; // rv 0 + assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA[7]; // rv 0 + assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA[80]; // rv 0 + assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA[81]; // rv 0 + assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA[82]; // rv 0 + assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA[83]; // rv 0 + assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA[84]; // rv 0 + assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA[85]; // rv 0 + assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA[86]; // rv 0 + assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA[87]; // rv 0 + assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA[88]; // rv 0 + assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA[89]; // rv 0 + assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA[8]; // rv 0 + assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA[90]; // rv 0 + assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA[91]; // rv 0 + assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA[92]; // rv 0 + assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA[93]; // rv 0 + assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA[94]; // rv 0 + assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA[95]; // rv 0 + assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA[96]; // rv 0 + assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA[97]; // rv 0 + assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA[98]; // rv 0 + assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA[99]; // rv 0 + assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA[9]; // rv 0 + assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX; // rv 0 + assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE; // rv 0 + assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER[0]; // rv 0 + assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER[1]; // rv 0 + assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER[2]; // rv 0 + assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER[3]; // rv 0 + assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER[4]; // rv 0 + assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER[5]; // rv 0 + assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT; // rv 0 + assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD[0]; // rv 0 + assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD[1]; // rv 0 + assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY; // rv 0 + assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR; // rv 0 + assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL[0]; // rv 0 + assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL[1]; // rv 0 + assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL[2]; // rv 0 + assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL[3]; // rv 0 + assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE[0]; // rv 0 + assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE[1]; // rv 0 + assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE[2]; // rv 0 + assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE[0]; // rv 0 + assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE[1]; // rv 0 + assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE[2]; // rv 0 + assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE[3]; // rv 0 + assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE[4]; // rv 0 + assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE[5]; // rv 0 + assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE[6]; // rv 0 + assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2; // rv 0 +`endif + + assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR; // rv 0 + assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ; // rv 0 + assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX; // rv 0 + assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET; // rv 0 + assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0; // rv 0 + assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1; // rv 0 + assign CPLLFREQLOCK_in = (CPLLFREQLOCK !== 1'bz) && CPLLFREQLOCK; // rv 0 + assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK; // rv 0 + assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN; // rv 0 + assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD; // rv 0 + assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL[0]; // rv 1 + assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL[1]; // rv 0 + assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL[2]; // rv 0 + assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET; // rv 0 + assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET; // rv 0 + assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK; // rv 0 + assign DRPRST_in = (DRPRST === 1'bz) || DRPRST; // rv 1 + assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET; // rv 0 + assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER; // rv 0 + assign FREQOS_in = (FREQOS !== 1'bz) && FREQOS; // rv 0 + assign GTGREFCLK_in = GTGREFCLK; + assign GTNORTHREFCLK0_in = GTNORTHREFCLK0; + assign GTNORTHREFCLK1_in = GTNORTHREFCLK1; + assign GTREFCLK0_in = GTREFCLK0; + assign GTREFCLK1_in = GTREFCLK1; + assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD[0]; // rv 0 + assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD[10]; // rv 0 + assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD[11]; // rv 0 + assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD[12]; // rv 0 + assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD[13]; // rv 0 + assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD[14]; // rv 0 + assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD[15]; // rv 0 + assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD[1]; // rv 0 + assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD[2]; // rv 0 + assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD[3]; // rv 0 + assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD[4]; // rv 0 + assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD[5]; // rv 0 + assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD[6]; // rv 0 + assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD[7]; // rv 0 + assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD[8]; // rv 0 + assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD[9]; // rv 0 + assign GTRXRESETSEL_in = (GTRXRESETSEL !== 1'bz) && GTRXRESETSEL; // rv 0 + assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET; // rv 0 + assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0; + assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1; + assign GTTXRESETSEL_in = (GTTXRESETSEL !== 1'bz) && GTTXRESETSEL; // rv 0 + assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET; // rv 0 + assign GTYRXN_in = GTYRXN; + assign GTYRXP_in = GTYRXP; + assign INCPCTRL_in = (INCPCTRL !== 1'bz) && INCPCTRL; // rv 0 + assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK[0]; // rv 0 + assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK[1]; // rv 0 + assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK[2]; // rv 0 + assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE; // rv 0 + assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE; // rv 0 + assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART; // rv 0 + assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE; // rv 0 + assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] === 1'bz) || PCSRSVDIN[0]; // rv 1 + assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN[10]; // rv 0 + assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN[11]; // rv 0 + assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN[12]; // rv 0 + assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN[13]; // rv 0 + assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN[14]; // rv 0 + assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN[15]; // rv 0 + assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN[1]; // rv 0 + assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN[2]; // rv 0 + assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN[3]; // rv 0 + assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN[4]; // rv 0 + assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN[5]; // rv 0 + assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN[6]; // rv 0 + assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN[7]; // rv 0 + assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN[8]; // rv 0 + assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN[9]; // rv 0 + assign QPLL0CLK_in = QPLL0CLK; + assign QPLL0FREQLOCK_in = (QPLL0FREQLOCK !== 1'bz) && QPLL0FREQLOCK; // rv 0 + assign QPLL0REFCLK_in = QPLL0REFCLK; + assign QPLL1CLK_in = QPLL1CLK; + assign QPLL1FREQLOCK_in = (QPLL1FREQLOCK !== 1'bz) && QPLL1FREQLOCK; // rv 0 + assign QPLL1REFCLK_in = QPLL1REFCLK; + assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD; // rv 0 + assign RXAFECFOKEN_in = (RXAFECFOKEN === 1'bz) || RXAFECFOKEN; // rv 1 + assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET; // rv 0 + assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET; // rv 0 + assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD; // rv 0 + assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN; // rv 0 + assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET; // rv 0 + assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET; // rv 0 + assign RXCKCALSTART_in[0] = (RXCKCALSTART[0] !== 1'bz) && RXCKCALSTART[0]; // rv 0 + assign RXCKCALSTART_in[1] = (RXCKCALSTART[1] !== 1'bz) && RXCKCALSTART[1]; // rv 0 + assign RXCKCALSTART_in[2] = (RXCKCALSTART[2] !== 1'bz) && RXCKCALSTART[2]; // rv 0 + assign RXCKCALSTART_in[3] = (RXCKCALSTART[3] !== 1'bz) && RXCKCALSTART[3]; // rv 0 + assign RXCKCALSTART_in[4] = (RXCKCALSTART[4] !== 1'bz) && RXCKCALSTART[4]; // rv 0 + assign RXCKCALSTART_in[5] = (RXCKCALSTART[5] !== 1'bz) && RXCKCALSTART[5]; // rv 0 + assign RXCKCALSTART_in[6] = (RXCKCALSTART[6] !== 1'bz) && RXCKCALSTART[6]; // rv 0 + assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD; // rv 0 + assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN; // rv 0 + assign RXDFECFOKFCNUM_in[0] = (RXDFECFOKFCNUM[0] !== 1'bz) && RXDFECFOKFCNUM[0]; // rv 0 + assign RXDFECFOKFCNUM_in[1] = (RXDFECFOKFCNUM[1] === 1'bz) || RXDFECFOKFCNUM[1]; // rv 1 + assign RXDFECFOKFCNUM_in[2] = (RXDFECFOKFCNUM[2] === 1'bz) || RXDFECFOKFCNUM[2]; // rv 1 + assign RXDFECFOKFCNUM_in[3] = (RXDFECFOKFCNUM[3] !== 1'bz) && RXDFECFOKFCNUM[3]; // rv 0 + assign RXDFECFOKFEN_in = (RXDFECFOKFEN !== 1'bz) && RXDFECFOKFEN; // rv 0 + assign RXDFECFOKFPULSE_in = (RXDFECFOKFPULSE !== 1'bz) && RXDFECFOKFPULSE; // rv 0 + assign RXDFECFOKHOLD_in = (RXDFECFOKHOLD !== 1'bz) && RXDFECFOKHOLD; // rv 0 + assign RXDFECFOKOVREN_in = (RXDFECFOKOVREN !== 1'bz) && RXDFECFOKOVREN; // rv 0 + assign RXDFEKHHOLD_in = (RXDFEKHHOLD !== 1'bz) && RXDFEKHHOLD; // rv 0 + assign RXDFEKHOVRDEN_in = (RXDFEKHOVRDEN !== 1'bz) && RXDFEKHOVRDEN; // rv 0 + assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD; // rv 0 + assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN; // rv 0 + assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET; // rv 0 + assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD; // rv 0 + assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN; // rv 0 + assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD; // rv 0 + assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN; // rv 0 + assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD; // rv 0 + assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN; // rv 0 + assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD; // rv 0 + assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN; // rv 0 + assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD; // rv 0 + assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN; // rv 0 + assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD; // rv 0 + assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN; // rv 0 + assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD; // rv 0 + assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN; // rv 0 + assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD; // rv 0 + assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN; // rv 0 + assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD; // rv 0 + assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN; // rv 0 + assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD; // rv 0 + assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN; // rv 0 + assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD; // rv 0 + assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN; // rv 0 + assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD; // rv 0 + assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN; // rv 0 + assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD; // rv 0 + assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN; // rv 0 + assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD; // rv 0 + assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN; // rv 0 + assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD; // rv 0 + assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN; // rv 0 + assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD; // rv 0 + assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN; // rv 0 + assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN; // rv 0 + assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS; // rv 0 + assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN; // rv 0 + assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN; // rv 0 + assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET; // rv 0 + assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE[0]; // rv 0 + assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE[1]; // rv 0 + assign RXEQTRAINING_in = (RXEQTRAINING !== 1'bz) && RXEQTRAINING; // rv 0 + assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK; // rv 0 + assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN; // rv 0 + assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD; // rv 0 + assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN; // rv 0 + assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD; // rv 0 + assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN; // rv 0 + assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD; // rv 0 + assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN; // rv 0 + assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD; // rv 0 + assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN; // rv 0 + assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL[0]; // rv 0 + assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL[1]; // rv 0 + assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET; // rv 0 + assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET; // rv 0 + assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD; // rv 0 + assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN; // rv 0 + assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL[0]; // rv 0 + assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL[1]; // rv 0 + assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL[2]; // rv 0 + assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET; // rv 0 + assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD[0]; // rv 0 + assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD[1]; // rv 0 + assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN; // rv 0 + assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN; // rv 0 + assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD; // rv 0 + assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET; // rv 0 + assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL[0]; // rv 0 + assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL[1]; // rv 0 + assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET; // rv 0 + assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET; // rv 0 + assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE; // rv 0 + assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN; // rv 0 + assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN; // rv 0 + assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE; // rv 1 + assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL[0]; // rv 0 + assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL[1]; // rv 0 + assign RXTERMINATION_in = (RXTERMINATION !== 1'bz) && RXTERMINATION; // rv 0 + assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY; // rv 0 + assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK; // rv 0 + assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN[0]; // rv 0 + assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN[10]; // rv 0 + assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN[11]; // rv 0 + assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN[12]; // rv 0 + assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN[13]; // rv 0 + assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN[14]; // rv 0 + assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN[15]; // rv 0 + assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN[16]; // rv 0 + assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN[17]; // rv 0 + assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN[18]; // rv 0 + assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN[19]; // rv 0 + assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN[1]; // rv 0 + assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN[2]; // rv 0 + assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN[3]; // rv 0 + assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN[4]; // rv 0 + assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN[5]; // rv 0 + assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN[6]; // rv 0 + assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN[7]; // rv 0 + assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN[8]; // rv 0 + assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN[9]; // rv 0 + assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD[0]; // rv 0 + assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD[1]; // rv 0 + assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD[2]; // rv 0 + assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD[3]; // rv 0 + assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD[4]; // rv 0 + assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD[5]; // rv 0 + assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD[6]; // rv 0 + assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD[7]; // rv 0 + assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART; // rv 0 + assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET; // rv 0 + assign TXDEEMPH_in[0] = (TXDEEMPH[0] !== 1'bz) && TXDEEMPH[0]; // rv 0 + assign TXDEEMPH_in[1] = (TXDEEMPH[1] !== 1'bz) && TXDEEMPH[1]; // rv 0 + assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL[0]; // rv 0 + assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL[1]; // rv 0 + assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL[2]; // rv 0 + assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL[3]; // rv 0 + assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL[4]; // rv 0 + assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS; // rv 0 + assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN; // rv 0 + assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD; // rv 0 + assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN; // rv 0 + assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET; // rv 0 + assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN; // rv 0 + assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK; // rv 0 + assign TXLFPSTRESET_in = (TXLFPSTRESET !== 1'bz) && TXLFPSTRESET; // rv 0 + assign TXLFPSU2LPEXIT_in = (TXLFPSU2LPEXIT !== 1'bz) && TXLFPSU2LPEXIT; // rv 0 + assign TXLFPSU3WAKE_in = (TXLFPSU3WAKE !== 1'bz) && TXLFPSU3WAKE; // rv 0 + assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR[0]; // rv 0 + assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR[1]; // rv 0 + assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR[2]; // rv 0 + assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR[3]; // rv 0 + assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR[4]; // rv 0 + assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR[5]; // rv 0 + assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR[6]; // rv 0 + assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN[0]; // rv 0 + assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN[1]; // rv 0 + assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN[2]; // rv 0 + assign TXMUXDCDEXHOLD_in = (TXMUXDCDEXHOLD !== 1'bz) && TXMUXDCDEXHOLD; // rv 0 + assign TXMUXDCDORWREN_in = (TXMUXDCDORWREN !== 1'bz) && TXMUXDCDORWREN; // rv 0 + assign TXONESZEROS_in = (TXONESZEROS !== 1'bz) && TXONESZEROS; // rv 0 + assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL[0]; // rv 0 + assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL[1]; // rv 0 + assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL[2]; // rv 0 + assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET; // rv 0 + assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE; // rv 0 + assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN; // rv 0 + assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN; // rv 0 + assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD; // rv 0 + assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET; // rv 0 + assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK; // rv 0 + assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT; // rv 0 + assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN; // rv 0 + assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN; // rv 0 + assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN; // rv 0 + assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD; // rv 0 + assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL; // rv 0 + assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE[0]; // rv 0 + assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE[1]; // rv 0 + assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE[2]; // rv 0 + assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE[3]; // rv 0 + assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE[4]; // rv 0 + assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD; // rv 0 + assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL[0]; // rv 0 + assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL[1]; // rv 0 + assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET; // rv 0 + assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR[0]; // rv 0 + assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR[1]; // rv 0 + assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR[2]; // rv 0 + assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR[3]; // rv 0 + assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR[4]; // rv 0 + assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR[0]; // rv 0 + assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR[1]; // rv 0 + assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR[2]; // rv 0 + assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR[3]; // rv 0 + assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR[4]; // rv 0 + assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET; // rv 0 + assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE; // rv 0 + assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING; // rv 0 + assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN; // rv 0 + assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN; // rv 0 + assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE; // rv 1 + assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL[0]; // rv 0 + assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL[1]; // rv 0 + assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY; // rv 0 + assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK; // rv 0 + + + assign gt_intclk = gt_clk_int; + + initial begin + + #1; + trig_attr = ~trig_attr; + + gt_clk_int = 1'b0; + forever #10000 gt_clk_int = ~gt_clk_int; + + end + + +`ifdef XIL_XECLIB + assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000; + + TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000; + + end +`endif + + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_DOUBLE_REG != "FALSE") && + (ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_COMMA_WORD_REG != 1) && + (ALIGN_COMMA_WORD_REG != 2) && + (ALIGN_COMMA_WORD_REG != 4))) begin + $display("Error: [Unisim %s-131] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_MCOMMA_DET_REG != "TRUE") && + (ALIGN_MCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-132] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ALIGN_PCOMMA_DET_REG != "TRUE") && + (ALIGN_PCOMMA_DET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-134] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") && + (CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin + $display("Error: [Unisim %s-268] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") && + (CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-271] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_MAX_SKEW_REG != 7) && + (CHAN_BOND_MAX_SKEW_REG != 1) && + (CHAN_BOND_MAX_SKEW_REG != 2) && + (CHAN_BOND_MAX_SKEW_REG != 3) && + (CHAN_BOND_MAX_SKEW_REG != 4) && + (CHAN_BOND_MAX_SKEW_REG != 5) && + (CHAN_BOND_MAX_SKEW_REG != 6) && + (CHAN_BOND_MAX_SKEW_REG != 8) && + (CHAN_BOND_MAX_SKEW_REG != 9) && + (CHAN_BOND_MAX_SKEW_REG != 10) && + (CHAN_BOND_MAX_SKEW_REG != 11) && + (CHAN_BOND_MAX_SKEW_REG != 12) && + (CHAN_BOND_MAX_SKEW_REG != 13) && + (CHAN_BOND_MAX_SKEW_REG != 14))) begin + $display("Error: [Unisim %s-272] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") && + (CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-283] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CHAN_BOND_SEQ_LEN_REG != 2) && + (CHAN_BOND_SEQ_LEN_REG != 1) && + (CHAN_BOND_SEQ_LEN_REG != 3) && + (CHAN_BOND_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-284] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_CORRECT_USE_REG != "TRUE") && + (CLK_CORRECT_USE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-295] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_KEEP_IDLE_REG != "FALSE") && + (CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-296] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin + $display("Error: [Unisim %s-297] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin + $display("Error: [Unisim %s-298] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_PRECEDENCE_REG != "TRUE") && + (CLK_COR_PRECEDENCE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-299] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-300] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_2_USE_REG != "FALSE") && + (CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-311] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_COR_SEQ_LEN_REG != 2) && + (CLK_COR_SEQ_LEN_REG != 1) && + (CLK_COR_SEQ_LEN_REG != 3) && + (CLK_COR_SEQ_LEN_REG != 4))) begin + $display("Error: [Unisim %s-312] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_REG != 4) && + (CPLL_FBDIV_REG != 1) && + (CPLL_FBDIV_REG != 2) && + (CPLL_FBDIV_REG != 3) && + (CPLL_FBDIV_REG != 5) && + (CPLL_FBDIV_REG != 6) && + (CPLL_FBDIV_REG != 8) && + (CPLL_FBDIV_REG != 10) && + (CPLL_FBDIV_REG != 12) && + (CPLL_FBDIV_REG != 16) && + (CPLL_FBDIV_REG != 20))) begin + $display("Error: [Unisim %s-317] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_FBDIV_45_REG != 4) && + (CPLL_FBDIV_45_REG != 5))) begin + $display("Error: [Unisim %s-318] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CPLL_REFCLK_DIV_REG != 1) && + (CPLL_REFCLK_DIV_REG != 2) && + (CPLL_REFCLK_DIV_REG != 3) && + (CPLL_REFCLK_DIV_REG != 4) && + (CPLL_REFCLK_DIV_REG != 5) && + (CPLL_REFCLK_DIV_REG != 6) && + (CPLL_REFCLK_DIV_REG != 8) && + (CPLL_REFCLK_DIV_REG != 10) && + (CPLL_REFCLK_DIV_REG != 12) && + (CPLL_REFCLK_DIV_REG != 16) && + (CPLL_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-321] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin + $display("Error: [Unisim %s-338] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_MCOMMA_DETECT_REG != "TRUE") && + (DEC_MCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-339] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_PCOMMA_DETECT_REG != "TRUE") && + (DEC_PCOMMA_DETECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-340] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEC_VALID_COMMA_ONLY_REG != "TRUE") && + (DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-341] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_ERRDET_EN_REG != "FALSE") && + (ES_ERRDET_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-347] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ES_EYE_SCAN_EN_REG != "FALSE") && + (ES_EYE_SCAN_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-348] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EYESCAN_VP_RANGE_REG != 0) && + (EYESCAN_VP_RANGE_REG != 1) && + (EYESCAN_VP_RANGE_REG != 2) && + (EYESCAN_VP_RANGE_REG != 3))) begin + $display("Error: [Unisim %s-381] EYESCAN_VP_RANGE attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, EYESCAN_VP_RANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FTS_LANE_DESKEW_EN_REG != "FALSE") && + (FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-385] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LPBK_BIAS_CTRL_REG != 4) && + (LPBK_BIAS_CTRL_REG != 0) && + (LPBK_BIAS_CTRL_REG != 1) && + (LPBK_BIAS_CTRL_REG != 2) && + (LPBK_BIAS_CTRL_REG != 3) && + (LPBK_BIAS_CTRL_REG != 5) && + (LPBK_BIAS_CTRL_REG != 6) && + (LPBK_BIAS_CTRL_REG != 7))) begin + $display("Error: [Unisim %s-394] LPBK_BIAS_CTRL attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, LPBK_BIAS_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LPBK_IND_CTRL0_REG != 5) && + (LPBK_IND_CTRL0_REG != 0) && + (LPBK_IND_CTRL0_REG != 1) && + (LPBK_IND_CTRL0_REG != 2) && + (LPBK_IND_CTRL0_REG != 3) && + (LPBK_IND_CTRL0_REG != 4) && + (LPBK_IND_CTRL0_REG != 6) && + (LPBK_IND_CTRL0_REG != 7))) begin + $display("Error: [Unisim %s-397] LPBK_IND_CTRL0 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LPBK_IND_CTRL1_REG != 5) && + (LPBK_IND_CTRL1_REG != 0) && + (LPBK_IND_CTRL1_REG != 1) && + (LPBK_IND_CTRL1_REG != 2) && + (LPBK_IND_CTRL1_REG != 3) && + (LPBK_IND_CTRL1_REG != 4) && + (LPBK_IND_CTRL1_REG != 6) && + (LPBK_IND_CTRL1_REG != 7))) begin + $display("Error: [Unisim %s-398] LPBK_IND_CTRL1 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LPBK_IND_CTRL2_REG != 5) && + (LPBK_IND_CTRL2_REG != 0) && + (LPBK_IND_CTRL2_REG != 1) && + (LPBK_IND_CTRL2_REG != 2) && + (LPBK_IND_CTRL2_REG != 3) && + (LPBK_IND_CTRL2_REG != 4) && + (LPBK_IND_CTRL2_REG != 6) && + (LPBK_IND_CTRL2_REG != 7))) begin + $display("Error: [Unisim %s-399] LPBK_IND_CTRL2 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LPBK_RG_CTRL_REG != 2) && + (LPBK_RG_CTRL_REG != 0) && + (LPBK_RG_CTRL_REG != 1) && + (LPBK_RG_CTRL_REG != 3))) begin + $display("Error: [Unisim %s-400] LPBK_RG_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, LPBK_RG_CTRL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") && + (PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") && + (PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin + $display("Error: [Unisim %s-403] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCIE_64B_DYN_CLKSW_DIS_REG != "FALSE") && + (PCIE_64B_DYN_CLKSW_DIS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-417] PCIE_64B_DYN_CLKSW_DIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCIE_64B_DYN_CLKSW_DIS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCIE_GEN4_64BIT_INT_EN_REG != "FALSE") && + (PCIE_GEN4_64BIT_INT_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-419] PCIE_GEN4_64BIT_INT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCIE_GEN4_64BIT_INT_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PCS_PCIE_EN_REG != "FALSE") && + (PCS_PCIE_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-427] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PREIQ_FREQ_BST_REG != 0) && + (PREIQ_FREQ_BST_REG != 1) && + (PREIQ_FREQ_BST_REG != 2) && + (PREIQ_FREQ_BST_REG != 3))) begin + $display("Error: [Unisim %s-432] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_ADDR_MODE_REG != "FULL") && + (RXBUF_ADDR_MODE_REG != "FAST"))) begin + $display("Error: [Unisim %s-439] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_EN_REG != "TRUE") && + (RXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-442] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-443] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") && + (RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-444] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") && + (RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-445] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") && + (RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-446] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin + $display("Error: [Unisim %s-447] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_OVRD_REG != "FALSE") && + (RXBUF_THRESH_OVRD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-448] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin + $display("Error: [Unisim %s-449] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXELECIDLE_CFG_REG != "SIGCFG_4") && + (RXELECIDLE_CFG_REG != "SIGCFG_1") && + (RXELECIDLE_CFG_REG != "SIGCFG_2") && + (RXELECIDLE_CFG_REG != "SIGCFG_3") && + (RXELECIDLE_CFG_REG != "SIGCFG_6") && + (RXELECIDLE_CFG_REG != "SIGCFG_8") && + (RXELECIDLE_CFG_REG != "SIGCFG_12") && + (RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin + $display("Error: [Unisim %s-536] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin + $display("Error: [Unisim %s-537] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXGEARBOX_EN_REG != "FALSE") && + (RXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-538] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOOB_CLK_CFG_REG != "PMA") && + (RXOOB_CLK_CFG_REG != "FABRIC"))) begin + $display("Error: [Unisim %s-547] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXOUT_DIV_REG != 4) && + (RXOUT_DIV_REG != 1) && + (RXOUT_DIV_REG != 2) && + (RXOUT_DIV_REG != 8) && + (RXOUT_DIV_REG != 16) && + (RXOUT_DIV_REG != 32))) begin + $display("Error: [Unisim %s-549] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, RXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPMACLK_SEL_REG != "DATA") && + (RXPMACLK_SEL_REG != "CROSSING") && + (RXPMACLK_SEL_REG != "EYESCAN"))) begin + $display("Error: [Unisim %s-558] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin + $display("Error: [Unisim %s-561] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_AUTO_WAIT_REG != 7) && + (RXSLIDE_AUTO_WAIT_REG != 1) && + (RXSLIDE_AUTO_WAIT_REG != 2) && + (RXSLIDE_AUTO_WAIT_REG != 3) && + (RXSLIDE_AUTO_WAIT_REG != 4) && + (RXSLIDE_AUTO_WAIT_REG != 5) && + (RXSLIDE_AUTO_WAIT_REG != 6) && + (RXSLIDE_AUTO_WAIT_REG != 8) && + (RXSLIDE_AUTO_WAIT_REG != 9) && + (RXSLIDE_AUTO_WAIT_REG != 10) && + (RXSLIDE_AUTO_WAIT_REG != 11) && + (RXSLIDE_AUTO_WAIT_REG != 12) && + (RXSLIDE_AUTO_WAIT_REG != 13) && + (RXSLIDE_AUTO_WAIT_REG != 14) && + (RXSLIDE_AUTO_WAIT_REG != 15))) begin + $display("Error: [Unisim %s-563] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RXSLIDE_MODE_REG != "OFF") && + (RXSLIDE_MODE_REG != "AUTO") && + (RXSLIDE_MODE_REG != "PCS") && + (RXSLIDE_MODE_REG != "PMA"))) begin + $display("Error: [Unisim %s-564] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-572] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_SEL_REG != 2) && + (RX_CM_SEL_REG != 0) && + (RX_CM_SEL_REG != 1) && + (RX_CM_SEL_REG != 3))) begin + $display("Error: [Unisim %s-577] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, RX_CM_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_CM_TRIM_REG != 12) && + (RX_CM_TRIM_REG != 0) && + (RX_CM_TRIM_REG != 1) && + (RX_CM_TRIM_REG != 2) && + (RX_CM_TRIM_REG != 3) && + (RX_CM_TRIM_REG != 4) && + (RX_CM_TRIM_REG != 5) && + (RX_CM_TRIM_REG != 6) && + (RX_CM_TRIM_REG != 7) && + (RX_CM_TRIM_REG != 8) && + (RX_CM_TRIM_REG != 9) && + (RX_CM_TRIM_REG != 10) && + (RX_CM_TRIM_REG != 11) && + (RX_CM_TRIM_REG != 13) && + (RX_CM_TRIM_REG != 14) && + (RX_CM_TRIM_REG != 15))) begin + $display("Error: [Unisim %s-578] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_WIDTH_REG != 20) && + (RX_DATA_WIDTH_REG != 16) && + (RX_DATA_WIDTH_REG != 32) && + (RX_DATA_WIDTH_REG != 40) && + (RX_DATA_WIDTH_REG != 64) && + (RX_DATA_WIDTH_REG != 80) && + (RX_DATA_WIDTH_REG != 128) && + (RX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-581] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") && + (RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-583] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFELPM_CFG0_REG != 10) && + (RX_DFELPM_CFG0_REG != 0) && + (RX_DFELPM_CFG0_REG != 1) && + (RX_DFELPM_CFG0_REG != 11) && + (RX_DFELPM_CFG0_REG != 12) && + (RX_DFELPM_CFG0_REG != 13) && + (RX_DFELPM_CFG0_REG != 14) && + (RX_DFELPM_CFG0_REG != 15))) begin + $display("Error: [Unisim %s-586] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 10, 0, 1, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_AGC_CFG1_REG != 4) && + (RX_DFE_AGC_CFG1_REG != 0) && + (RX_DFE_AGC_CFG1_REG != 1) && + (RX_DFE_AGC_CFG1_REG != 2) && + (RX_DFE_AGC_CFG1_REG != 3) && + (RX_DFE_AGC_CFG1_REG != 5) && + (RX_DFE_AGC_CFG1_REG != 6) && + (RX_DFE_AGC_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-589] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG0_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 0) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin + $display("Error: [Unisim %s-590] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KH_CFG1_REG != 2) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 0) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 1) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 3) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 4) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 5) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 6) && + (RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-591] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 2, 0, 1, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DFE_KL_LPM_KL_CFG1_REG != 4) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 0) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 1) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 2) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 3) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 5) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 6) && + (RX_DFE_KL_LPM_KL_CFG1_REG != 7))) begin + $display("Error: [Unisim %s-593] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") && + (RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin + $display("Error: [Unisim %s-595] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_EN_SUM_RCAL_B_REG != 0) && + (RX_EN_SUM_RCAL_B_REG != 1))) begin + $display("Error: [Unisim %s-598] RX_EN_SUM_RCAL_B attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_EN_SUM_RCAL_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_INT_DATAWIDTH_REG != 1) && + (RX_INT_DATAWIDTH_REG != 0) && + (RX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-605] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_PROGDIV_CFG_REG != 0.0) && + (RX_PROGDIV_CFG_REG != 4.0) && + (RX_PROGDIV_CFG_REG != 5.0) && + (RX_PROGDIV_CFG_REG != 8.0) && + (RX_PROGDIV_CFG_REG != 10.0) && + (RX_PROGDIV_CFG_REG != 16.0) && + (RX_PROGDIV_CFG_REG != 16.5) && + (RX_PROGDIV_CFG_REG != 20.0) && + (RX_PROGDIV_CFG_REG != 32.0) && + (RX_PROGDIV_CFG_REG != 33.0) && + (RX_PROGDIV_CFG_REG != 40.0) && + (RX_PROGDIV_CFG_REG != 64.0) && + (RX_PROGDIV_CFG_REG != 66.0) && + (RX_PROGDIV_CFG_REG != 80.0) && + (RX_PROGDIV_CFG_REG != 100.0) && + (RX_PROGDIV_CFG_REG != 128.0) && + (RX_PROGDIV_CFG_REG != 132.0))) begin + $display("Error: [Unisim %s-608] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin + $display("Error: [Unisim %s-613] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SUM_DEGEN_AVTT_OVERITE_REG != 0) && + (RX_SUM_DEGEN_AVTT_OVERITE_REG != 1))) begin + $display("Error: [Unisim %s-614] RX_SUM_DEGEN_AVTT_OVERITE attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_SUM_DEGEN_AVTT_OVERITE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_SUM_PWR_SAVING_REG != 0) && + (RX_SUM_PWR_SAVING_REG != 1))) begin + $display("Error: [Unisim %s-617] RX_SUM_PWR_SAVING attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_SUM_PWR_SAVING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_XCLK_SEL_REG != "RXDES") && + (RX_XCLK_SEL_REG != "RXPMA") && + (RX_XCLK_SEL_REG != "RXUSR"))) begin + $display("Error: [Unisim %s-630] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") && + (SATA_CPLL_CFG_REG != "VCO_750MHZ") && + (SATA_CPLL_CFG_REG != "VCO_1500MHZ") && + (SATA_CPLL_CFG_REG != "VCO_6000MHZ"))) begin + $display("Error: [Unisim %s-636] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ or VCO_6000MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SHOW_REALIGN_COMMA_REG != "TRUE") && + (SHOW_REALIGN_COMMA_REG != "FALSE"))) begin + $display("Error: [Unisim %s-638] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-639] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_MODE_REG != "FAST") && + (SIM_MODE_REG != "LEGACY"))) begin + $display("Error: [Unisim %s-640] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") && + (SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-641] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-642] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_TX_EIDLE_DRIVE_LEVEL_REG != "Z") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "HIGH") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "LOW") && + (SIM_TX_EIDLE_DRIVE_LEVEL_REG != "X"))) begin + $display("Error: [Unisim %s-643] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %s. Legal values for this attribute are Z, HIGH, LOW or X. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_EN_REG != "TRUE") && + (TXBUF_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-651] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") && + (TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-652] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXDRV_FREQBAND_REG != 0) && + (TXDRV_FREQBAND_REG != 1) && + (TXDRV_FREQBAND_REG != 2) && + (TXDRV_FREQBAND_REG != 3))) begin + $display("Error: [Unisim %s-655] TXDRV_FREQBAND attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TXDRV_FREQBAND_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXFIFO_ADDR_CFG_REG != "LOW") && + (TXFIFO_ADDR_CFG_REG != "HIGH"))) begin + $display("Error: [Unisim %s-660] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) && + (TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin + $display("Error: [Unisim %s-661] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXGEARBOX_EN_REG != "FALSE") && + (TXGEARBOX_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-662] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXOUT_DIV_REG != 4) && + (TXOUT_DIV_REG != 1) && + (TXOUT_DIV_REG != 2) && + (TXOUT_DIV_REG != 8) && + (TXOUT_DIV_REG != 16) && + (TXOUT_DIV_REG != 32))) begin + $display("Error: [Unisim %s-664] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, TXOUT_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXSWBST_BST_REG != 1) && + (TXSWBST_BST_REG != 0) && + (TXSWBST_BST_REG != 2) && + (TXSWBST_BST_REG != 3))) begin + $display("Error: [Unisim %s-680] TXSWBST_BST attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, TXSWBST_BST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXSWBST_EN_REG != 0) && + (TXSWBST_EN_REG != 1))) begin + $display("Error: [Unisim %s-681] TXSWBST_EN attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, TXSWBST_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TXSWBST_MAG_REG != 6) && + (TXSWBST_MAG_REG != 0) && + (TXSWBST_MAG_REG != 1) && + (TXSWBST_MAG_REG != 2) && + (TXSWBST_MAG_REG != 3) && + (TXSWBST_MAG_REG != 4) && + (TXSWBST_MAG_REG != 5) && + (TXSWBST_MAG_REG != 7))) begin + $display("Error: [Unisim %s-682] TXSWBST_MAG attribute is set to %d. Legal values for this attribute are 6, 0, 1, 2, 3, 4, 5 or 7. Instance: %m", MODULE_NAME, TXSWBST_MAG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin + $display("Error: [Unisim %s-686] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DATA_WIDTH_REG != 20) && + (TX_DATA_WIDTH_REG != 16) && + (TX_DATA_WIDTH_REG != 32) && + (TX_DATA_WIDTH_REG != 40) && + (TX_DATA_WIDTH_REG != 64) && + (TX_DATA_WIDTH_REG != 80) && + (TX_DATA_WIDTH_REG != 128) && + (TX_DATA_WIDTH_REG != 160))) begin + $display("Error: [Unisim %s-688] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DRIVE_MODE_REG != "DIRECT") && + (TX_DRIVE_MODE_REG != "PIPE") && + (TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin + $display("Error: [Unisim %s-695] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_INT_DATAWIDTH_REG != 1) && + (TX_INT_DATAWIDTH_REG != 0) && + (TX_INT_DATAWIDTH_REG != 2))) begin + $display("Error: [Unisim %s-701] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") && + (TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin + $display("Error: [Unisim %s-702] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PI_BIASSET_REG != 0) && + (TX_PI_BIASSET_REG != 1) && + (TX_PI_BIASSET_REG != 2) && + (TX_PI_BIASSET_REG != 3))) begin + $display("Error: [Unisim %s-716] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGCLK_SEL_REG != "POSTPI") && + (TX_PROGCLK_SEL_REG != "CPLL") && + (TX_PROGCLK_SEL_REG != "PREPI"))) begin + $display("Error: [Unisim %s-721] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_PROGDIV_CFG_REG != 0.0) && + (TX_PROGDIV_CFG_REG != 4.0) && + (TX_PROGDIV_CFG_REG != 5.0) && + (TX_PROGDIV_CFG_REG != 8.0) && + (TX_PROGDIV_CFG_REG != 10.0) && + (TX_PROGDIV_CFG_REG != 16.0) && + (TX_PROGDIV_CFG_REG != 16.5) && + (TX_PROGDIV_CFG_REG != 20.0) && + (TX_PROGDIV_CFG_REG != 32.0) && + (TX_PROGDIV_CFG_REG != 33.0) && + (TX_PROGDIV_CFG_REG != 40.0) && + (TX_PROGDIV_CFG_REG != 64.0) && + (TX_PROGDIV_CFG_REG != 66.0) && + (TX_PROGDIV_CFG_REG != 80.0) && + (TX_PROGDIV_CFG_REG != 100.0) && + (TX_PROGDIV_CFG_REG != 128.0) && + (TX_PROGDIV_CFG_REG != 132.0))) begin + $display("Error: [Unisim %s-722] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_RXDETECT_REF_REG != 3) && + (TX_RXDETECT_REF_REG != 0) && + (TX_RXDETECT_REF_REG != 1) && + (TX_RXDETECT_REF_REG != 2) && + (TX_RXDETECT_REF_REG != 4) && + (TX_RXDETECT_REF_REG != 5) && + (TX_RXDETECT_REF_REG != 6) && + (TX_RXDETECT_REF_REG != 7))) begin + $display("Error: [Unisim %s-725] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 3, 0, 1, 2, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_XCLK_SEL_REG != "TXOUT") && + (TX_XCLK_SEL_REG != "TXUSR"))) begin + $display("Error: [Unisim %s-739] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_PING_SATA_MAX_INIT_REG < 1) || (USB_PING_SATA_MAX_INIT_REG > 63))) begin + $display("Error: [Unisim %s-757] USB_PING_SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MAX_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_PING_SATA_MIN_INIT_REG < 1) || (USB_PING_SATA_MIN_INIT_REG > 63))) begin + $display("Error: [Unisim %s-758] USB_PING_SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MIN_INIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_POLL_SATA_MAX_BURST_REG < 1) || (USB_POLL_SATA_MAX_BURST_REG > 63))) begin + $display("Error: [Unisim %s-759] USB_POLL_SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_POLL_SATA_MAX_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_POLL_SATA_MIN_BURST_REG < 1) || (USB_POLL_SATA_MIN_BURST_REG > 61))) begin + $display("Error: [Unisim %s-760] USB_POLL_SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, USB_POLL_SATA_MIN_BURST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U1_SATA_MAX_WAKE_REG < 1) || (USB_U1_SATA_MAX_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-764] USB_U1_SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MAX_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U1_SATA_MIN_WAKE_REG < 1) || (USB_U1_SATA_MIN_WAKE_REG > 63))) begin + $display("Error: [Unisim %s-765] USB_U1_SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MIN_WAKE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U2_SAS_MAX_COM_REG < 1) || (USB_U2_SAS_MAX_COM_REG > 127))) begin + $display("Error: [Unisim %s-766] USB_U2_SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, USB_U2_SAS_MAX_COM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USB_U2_SAS_MIN_COM_REG < 1) || (USB_U2_SAS_MIN_COM_REG > 63))) begin + $display("Error: [Unisim %s-767] USB_U2_SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U2_SAS_MIN_COM_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + +assign PMASCANCLK0_in = 1'b1; // tie off +assign PMASCANCLK1_in = 1'b1; // tie off +assign PMASCANCLK2_in = 1'b1; // tie off +assign PMASCANCLK3_in = 1'b1; // tie off +assign PMASCANCLK4_in = 1'b1; // tie off +assign PMASCANCLK5_in = 1'b1; // tie off +assign PMASCANCLK6_in = 1'b1; // tie off +assign PMASCANCLK7_in = 1'b1; // tie off +assign PMASCANCLK8_in = 1'b1; // tie off +assign SCANCLK_in = 1'b1; // tie off +assign TSTCLK0_in = 1'b1; // tie off +assign TSTCLK1_in = 1'b1; // tie off + +assign BSR_SERIAL_in = 1'b1; // tie off +assign CSSDRSTB_in = 1'b1; // tie off +assign CSSDSTOPCLK_in = 1'b1; // tie off +assign PMASCANENB_in = 1'b1; // tie off +assign PMASCANIN_in = 18'b111111111111111111; // tie off +assign PMASCANMODEB_in = 1'b1; // tie off +assign PMASCANRSTEN_in = 1'b1; // tie off +assign SARCCLK_in = 1'b1; // tie off +assign SCANENB_in = 1'b1; // tie off +assign SCANIN_in = 19'b1111111111111111111; // tie off +assign SCANMODEB_in = 1'b1; // tie off +assign SCANRSTB_in = 1'b1; // tie off +assign SCANRSTEN_in = 1'b1; // tie off +assign TSTPDOVRDB_in = 1'b1; // tie off +assign TSTPD_in = 5'b11111; // tie off + +SIP_GTYE4_CHANNEL SIP_GTYE4_CHANNEL_INST ( +.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG), +.ACJTAG_MODE (ACJTAG_MODE_REG), +.ACJTAG_RESET (ACJTAG_RESET_REG), +.ADAPT_CFG0 (ADAPT_CFG0_REG), +.ADAPT_CFG1 (ADAPT_CFG1_REG), +.ADAPT_CFG2 (ADAPT_CFG2_REG), +.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG), +.AEN_CPLL (AEN_CPLL_REG), +.AEN_LOOPBACK (AEN_LOOPBACK_REG), +.AEN_MASTER (AEN_MASTER_REG), +.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG), +.AEN_POLARITY (AEN_POLARITY_REG), +.AEN_PRBS (AEN_PRBS_REG), +.AEN_RESET (AEN_RESET_REG), +.AEN_RXCDR (AEN_RXCDR_REG), +.AEN_RXDFE (AEN_RXDFE_REG), +.AEN_RXDFELPM (AEN_RXDFELPM_REG), +.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG), +.AEN_RXPHDLY (AEN_RXPHDLY_REG), +.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG), +.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG), +.AEN_TXMUXDCD (AEN_TXMUXDCD_REG), +.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG), +.AEN_TXPHDLY (AEN_TXPHDLY_REG), +.AEN_TXPI_PPM (AEN_TXPI_PPM_REG), +.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG), +.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG), +.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG), +.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG), +.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG), +.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG), +.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG), +.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG), +.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG), +.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG), +.AMONITOR_CFG (AMONITOR_CFG_REG), +.A_CPLLLOCKEN (A_CPLLLOCKEN_REG), +.A_CPLLPD (A_CPLLPD_REG), +.A_CPLLRESET (A_CPLLRESET_REG), +.A_EYESCANRESET (A_EYESCANRESET_REG), +.A_GTRESETSEL (A_GTRESETSEL_REG), +.A_GTRXRESET (A_GTRXRESET_REG), +.A_GTTXRESET (A_GTTXRESET_REG), +.A_LOOPBACK (A_LOOPBACK_REG), +.A_RXAFECFOKEN (A_RXAFECFOKEN_REG), +.A_RXBUFRESET (A_RXBUFRESET_REG), +.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG), +.A_RXCDRHOLD (A_RXCDRHOLD_REG), +.A_RXCDROVRDEN (A_RXCDROVRDEN_REG), +.A_RXCDRRESET (A_RXCDRRESET_REG), +.A_RXCKCALRESET (A_RXCKCALRESET_REG), +.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG), +.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG), +.A_RXDFECFOKFCNUM (A_RXDFECFOKFCNUM_REG), +.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG), +.A_RXDFECFOKFPULSE (A_RXDFECFOKFPULSE_REG), +.A_RXDFECFOKHOLD (A_RXDFECFOKHOLD_REG), +.A_RXDFECFOKOVREN (A_RXDFECFOKOVREN_REG), +.A_RXDFEKHHOLD (A_RXDFEKHHOLD_REG), +.A_RXDFEKHOVRDEN (A_RXDFEKHOVRDEN_REG), +.A_RXDFELFHOLD (A_RXDFELFHOLD_REG), +.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG), +.A_RXDFELPMRESET (A_RXDFELPMRESET_REG), +.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG), +.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG), +.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG), +.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG), +.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG), +.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG), +.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG), +.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG), +.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG), +.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG), +.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG), +.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG), +.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG), +.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG), +.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG), +.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG), +.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG), +.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG), +.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG), +.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG), +.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG), +.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG), +.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG), +.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG), +.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG), +.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG), +.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG), +.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG), +.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG), +.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG), +.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG), +.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG), +.A_RXDFEXYDEN (A_RXDFEXYDEN_REG), +.A_RXDLYBYPASS (A_RXDLYBYPASS_REG), +.A_RXDLYEN (A_RXDLYEN_REG), +.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG), +.A_RXDLYSRESET (A_RXDLYSRESET_REG), +.A_RXLPMEN (A_RXLPMEN_REG), +.A_RXLPMGCHOLD (A_RXLPMGCHOLD_REG), +.A_RXLPMGCOVRDEN (A_RXLPMGCOVRDEN_REG), +.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG), +.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG), +.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG), +.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG), +.A_RXLPMOSHOLD (A_RXLPMOSHOLD_REG), +.A_RXLPMOSOVRDEN (A_RXLPMOSOVRDEN_REG), +.A_RXMONITORSEL (A_RXMONITORSEL_REG), +.A_RXOOBRESET (A_RXOOBRESET_REG), +.A_RXOSCALRESET (A_RXOSCALRESET_REG), +.A_RXOSHOLD (A_RXOSHOLD_REG), +.A_RXOSOVRDEN (A_RXOSOVRDEN_REG), +.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG), +.A_RXPCSRESET (A_RXPCSRESET_REG), +.A_RXPD (A_RXPD_REG), +.A_RXPHALIGN (A_RXPHALIGN_REG), +.A_RXPHALIGNEN (A_RXPHALIGNEN_REG), +.A_RXPHDLYPD (A_RXPHDLYPD_REG), +.A_RXPHDLYRESET (A_RXPHDLYRESET_REG), +.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG), +.A_RXPMARESET (A_RXPMARESET_REG), +.A_RXPOLARITY (A_RXPOLARITY_REG), +.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG), +.A_RXPRBSSEL (A_RXPRBSSEL_REG), +.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG), +.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG), +.A_RXTERMINATION (A_RXTERMINATION_REG), +.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG), +.A_TXDCCRESET (A_TXDCCRESET_REG), +.A_TXDEEMPH (A_TXDEEMPH_REG), +.A_TXDIFFCTRL (A_TXDIFFCTRL_REG), +.A_TXDLYBYPASS (A_TXDLYBYPASS_REG), +.A_TXDLYEN (A_TXDLYEN_REG), +.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG), +.A_TXDLYSRESET (A_TXDLYSRESET_REG), +.A_TXELECIDLE (A_TXELECIDLE_REG), +.A_TXINHIBIT (A_TXINHIBIT_REG), +.A_TXMAINCURSOR (A_TXMAINCURSOR_REG), +.A_TXMARGIN (A_TXMARGIN_REG), +.A_TXMUXDCDEXHOLD (A_TXMUXDCDEXHOLD_REG), +.A_TXMUXDCDORWREN (A_TXMUXDCDORWREN_REG), +.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG), +.A_TXPCSRESET (A_TXPCSRESET_REG), +.A_TXPD (A_TXPD_REG), +.A_TXPHALIGN (A_TXPHALIGN_REG), +.A_TXPHALIGNEN (A_TXPHALIGNEN_REG), +.A_TXPHDLYPD (A_TXPHDLYPD_REG), +.A_TXPHDLYRESET (A_TXPHDLYRESET_REG), +.A_TXPHINIT (A_TXPHINIT_REG), +.A_TXPHOVRDEN (A_TXPHOVRDEN_REG), +.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG), +.A_TXPIPPMPD (A_TXPIPPMPD_REG), +.A_TXPIPPMSEL (A_TXPIPPMSEL_REG), +.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG), +.A_TXPMARESET (A_TXPMARESET_REG), +.A_TXPOLARITY (A_TXPOLARITY_REG), +.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG), +.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG), +.A_TXPRBSSEL (A_TXPRBSSEL_REG), +.A_TXPRECURSOR (A_TXPRECURSOR_REG), +.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG), +.A_TXRESETSEL (A_TXRESETSEL_REG), +.A_TXSWING (A_TXSWING_REG), +.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG), +.BSR_ENABLE (BSR_ENABLE_REG), +.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG), +.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG), +.CFOK_PWRSVE_EN (CFOK_PWRSVE_EN_REG), +.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG), +.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG), +.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG), +.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG), +.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG), +.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG), +.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG), +.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG), +.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG), +.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG), +.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG), +.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG), +.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG), +.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG), +.CH_HSPMUX (CH_HSPMUX_REG), +.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG), +.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG), +.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG), +.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG), +.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG), +.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG), +.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG), +.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG), +.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG), +.CLK_CORRECT_USE (CLK_CORRECT_USE_REG), +.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG), +.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG), +.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG), +.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG), +.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG), +.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG), +.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG), +.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG), +.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG), +.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG), +.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG), +.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG), +.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG), +.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG), +.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG), +.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG), +.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG), +.CPLL_CFG0 (CPLL_CFG0_REG), +.CPLL_CFG1 (CPLL_CFG1_REG), +.CPLL_CFG2 (CPLL_CFG2_REG), +.CPLL_CFG3 (CPLL_CFG3_REG), +.CPLL_FBDIV (CPLL_FBDIV_REG), +.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG), +.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG), +.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG), +.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG), +.CSSD_CLK_MASK0 (CSSD_CLK_MASK0_REG), +.CSSD_CLK_MASK1 (CSSD_CLK_MASK1_REG), +.CSSD_REG0 (CSSD_REG0_REG), +.CSSD_REG1 (CSSD_REG1_REG), +.CSSD_REG10 (CSSD_REG10_REG), +.CSSD_REG2 (CSSD_REG2_REG), +.CSSD_REG3 (CSSD_REG3_REG), +.CSSD_REG4 (CSSD_REG4_REG), +.CSSD_REG5 (CSSD_REG5_REG), +.CSSD_REG6 (CSSD_REG6_REG), +.CSSD_REG7 (CSSD_REG7_REG), +.CSSD_REG8 (CSSD_REG8_REG), +.CSSD_REG9 (CSSD_REG9_REG), +.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG), +.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG), +.DDI_CTRL (DDI_CTRL_REG), +.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG), +.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG), +.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG), +.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG), +.DELAY_ELEC (DELAY_ELEC_REG), +.DMONITOR_CFG0 (DMONITOR_CFG0_REG), +.DMONITOR_CFG1 (DMONITOR_CFG1_REG), +.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG), +.ES_CONTROL (ES_CONTROL_REG), +.ES_ERRDET_EN (ES_ERRDET_EN_REG), +.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG), +.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG), +.ES_PRESCALE (ES_PRESCALE_REG), +.ES_QUALIFIER0 (ES_QUALIFIER0_REG), +.ES_QUALIFIER1 (ES_QUALIFIER1_REG), +.ES_QUALIFIER2 (ES_QUALIFIER2_REG), +.ES_QUALIFIER3 (ES_QUALIFIER3_REG), +.ES_QUALIFIER4 (ES_QUALIFIER4_REG), +.ES_QUALIFIER5 (ES_QUALIFIER5_REG), +.ES_QUALIFIER6 (ES_QUALIFIER6_REG), +.ES_QUALIFIER7 (ES_QUALIFIER7_REG), +.ES_QUALIFIER8 (ES_QUALIFIER8_REG), +.ES_QUALIFIER9 (ES_QUALIFIER9_REG), +.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG), +.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG), +.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG), +.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG), +.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG), +.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG), +.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG), +.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG), +.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG), +.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG), +.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG), +.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG), +.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG), +.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG), +.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG), +.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG), +.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG), +.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG), +.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG), +.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG), +.EYESCAN_VP_RANGE (EYESCAN_VP_RANGE_REG), +.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG), +.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG), +.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG), +.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG), +.GEARBOX_MODE (GEARBOX_MODE_REG), +.GEN_RXUSRCLK (GEN_RXUSRCLK_REG), +.GEN_TXUSRCLK (GEN_TXUSRCLK_REG), +.GT_INSTANTIATED (GT_INSTANTIATED_REG), +.INT_MASK_CFG0 (INT_MASK_CFG0_REG), +.INT_MASK_CFG1 (INT_MASK_CFG1_REG), +.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG), +.LOCAL_MASTER (LOCAL_MASTER_REG), +.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG), +.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG), +.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG), +.LPBK_IND_CTRL0 (LPBK_IND_CTRL0_REG), +.LPBK_IND_CTRL1 (LPBK_IND_CTRL1_REG), +.LPBK_IND_CTRL2 (LPBK_IND_CTRL2_REG), +.LPBK_RG_CTRL (LPBK_RG_CTRL_REG), +.OOBDIVCTL (OOBDIVCTL_REG), +.OOB_PWRUP (OOB_PWRUP_REG), +.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG), +.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG), +.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG), +.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG), +.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG), +.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG), +.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG), +.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG), +.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG), +.PCIE3_CLK_COR_EMPTY_THRSH (PCIE3_CLK_COR_EMPTY_THRSH_REG), +.PCIE3_CLK_COR_FULL_THRSH (PCIE3_CLK_COR_FULL_THRSH_REG), +.PCIE3_CLK_COR_MAX_LAT (PCIE3_CLK_COR_MAX_LAT_REG), +.PCIE3_CLK_COR_MIN_LAT (PCIE3_CLK_COR_MIN_LAT_REG), +.PCIE3_CLK_COR_THRSH_TIMER (PCIE3_CLK_COR_THRSH_TIMER_REG), +.PCIE_64B_DYN_CLKSW_DIS (PCIE_64B_DYN_CLKSW_DIS_REG), +.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG), +.PCIE_GEN4_64BIT_INT_EN (PCIE_GEN4_64BIT_INT_EN_REG), +.PCIE_PLL_SEL_MODE_GEN12 (PCIE_PLL_SEL_MODE_GEN12_REG), +.PCIE_PLL_SEL_MODE_GEN3 (PCIE_PLL_SEL_MODE_GEN3_REG), +.PCIE_PLL_SEL_MODE_GEN4 (PCIE_PLL_SEL_MODE_GEN4_REG), +.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG), +.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG), +.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG), +.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG), +.PCS_PCIE_EN (PCS_PCIE_EN_REG), +.PCS_RSVD0 (PCS_RSVD0_REG), +.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG), +.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG), +.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG), +.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG), +.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG), +.RCLK_SIPO_DLY_ENB (RCLK_SIPO_DLY_ENB_REG), +.RCLK_SIPO_INV_EN (RCLK_SIPO_INV_EN_REG), +.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL_REG), +.RTX_BUF_TERM_CTRL (RTX_BUF_TERM_CTRL_REG), +.RXBUFRESET_TIME (RXBUFRESET_TIME_REG), +.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG), +.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG), +.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG), +.RXBUF_EN (RXBUF_EN_REG), +.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG), +.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG), +.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG), +.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG), +.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG), +.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG), +.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG), +.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG), +.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG), +.RXCDR_CFG0 (RXCDR_CFG0_REG), +.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG), +.RXCDR_CFG1 (RXCDR_CFG1_REG), +.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG), +.RXCDR_CFG2 (RXCDR_CFG2_REG), +.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2_REG), +.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG), +.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4_REG), +.RXCDR_CFG3 (RXCDR_CFG3_REG), +.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2_REG), +.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG), +.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4_REG), +.RXCDR_CFG4 (RXCDR_CFG4_REG), +.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG), +.RXCDR_CFG5 (RXCDR_CFG5_REG), +.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG), +.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG), +.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG), +.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG), +.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG), +.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG), +.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG), +.RXCDR_LOCK_CFG4 (RXCDR_LOCK_CFG4_REG), +.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG), +.RXCFOK_CFG0 (RXCFOK_CFG0_REG), +.RXCFOK_CFG1 (RXCFOK_CFG1_REG), +.RXCFOK_CFG2 (RXCFOK_CFG2_REG), +.RXCKCAL1_IQ_LOOP_RST_CFG (RXCKCAL1_IQ_LOOP_RST_CFG_REG), +.RXCKCAL1_I_LOOP_RST_CFG (RXCKCAL1_I_LOOP_RST_CFG_REG), +.RXCKCAL1_Q_LOOP_RST_CFG (RXCKCAL1_Q_LOOP_RST_CFG_REG), +.RXCKCAL2_DX_LOOP_RST_CFG (RXCKCAL2_DX_LOOP_RST_CFG_REG), +.RXCKCAL2_D_LOOP_RST_CFG (RXCKCAL2_D_LOOP_RST_CFG_REG), +.RXCKCAL2_S_LOOP_RST_CFG (RXCKCAL2_S_LOOP_RST_CFG_REG), +.RXCKCAL2_X_LOOP_RST_CFG (RXCKCAL2_X_LOOP_RST_CFG_REG), +.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG), +.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG), +.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG), +.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG), +.RXDFE_CFG0 (RXDFE_CFG0_REG), +.RXDFE_CFG1 (RXDFE_CFG1_REG), +.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG), +.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG), +.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG), +.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG), +.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG), +.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG), +.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG), +.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG), +.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG), +.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG), +.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG), +.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG), +.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG), +.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG), +.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG), +.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG), +.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG), +.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG), +.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG), +.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG), +.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG), +.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG), +.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG), +.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG), +.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG), +.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG), +.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG), +.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG), +.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG), +.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG), +.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG), +.RXDFE_KH_CFG0 (RXDFE_KH_CFG0_REG), +.RXDFE_KH_CFG1 (RXDFE_KH_CFG1_REG), +.RXDFE_KH_CFG2 (RXDFE_KH_CFG2_REG), +.RXDFE_KH_CFG3 (RXDFE_KH_CFG3_REG), +.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG), +.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG), +.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG), +.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG), +.RXDFE_UT_CFG2 (RXDFE_UT_CFG2_REG), +.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG), +.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG), +.RXDLY_CFG (RXDLY_CFG_REG), +.RXDLY_LCFG (RXDLY_LCFG_REG), +.RXELECIDLE_CFG (RXELECIDLE_CFG_REG), +.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG), +.RXGEARBOX_EN (RXGEARBOX_EN_REG), +.RXISCANRESET_TIME (RXISCANRESET_TIME_REG), +.RXLPM_CFG (RXLPM_CFG_REG), +.RXLPM_GC_CFG (RXLPM_GC_CFG_REG), +.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG), +.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG), +.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG), +.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG), +.RXOOB_CFG (RXOOB_CFG_REG), +.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG), +.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG), +.RXOUT_DIV (RXOUT_DIV_REG), +.RXPCSRESET_TIME (RXPCSRESET_TIME_REG), +.RXPHBEACON_CFG (RXPHBEACON_CFG_REG), +.RXPHDLY_CFG (RXPHDLY_CFG_REG), +.RXPHSAMP_CFG (RXPHSAMP_CFG_REG), +.RXPHSLIP_CFG (RXPHSLIP_CFG_REG), +.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG), +.RXPI_CFG0 (RXPI_CFG0_REG), +.RXPI_CFG1 (RXPI_CFG1_REG), +.RXPMACLK_SEL (RXPMACLK_SEL_REG), +.RXPMARESET_TIME (RXPMARESET_TIME_REG), +.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG), +.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG), +.RXREFCLKDIV2_SEL (RXREFCLKDIV2_SEL_REG), +.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG), +.RXSLIDE_MODE (RXSLIDE_MODE_REG), +.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG), +.RXSYNC_OVRD (RXSYNC_OVRD_REG), +.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG), +.RX_AFE_CM_EN (RX_AFE_CM_EN_REG), +.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG), +.RX_BUFFER_CFG (RX_BUFFER_CFG_REG), +.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG), +.RX_CLK25_DIV (RX_CLK25_DIV_REG), +.RX_CLKMUX_EN (RX_CLKMUX_EN_REG), +.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG), +.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG), +.RX_CM_BUF_PD (RX_CM_BUF_PD_REG), +.RX_CM_SEL (RX_CM_SEL_REG), +.RX_CM_TRIM (RX_CM_TRIM_REG), +.RX_CTLE_PWR_SAVING (RX_CTLE_PWR_SAVING_REG), +.RX_CTLE_RES_CTRL (RX_CTLE_RES_CTRL_REG), +.RX_DATA_WIDTH (RX_DATA_WIDTH_REG), +.RX_DDI_SEL (RX_DDI_SEL_REG), +.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG), +.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG), +.RX_DFECFOKFCDAC (RX_DFECFOKFCDAC_REG), +.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG), +.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG), +.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG), +.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG), +.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG), +.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG), +.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG), +.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG), +.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG), +.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG), +.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG), +.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG), +.RX_EN_SUM_RCAL_B (RX_EN_SUM_RCAL_B_REG), +.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG), +.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG), +.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG), +.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG), +.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG), +.RX_I2V_FILTER_EN (RX_I2V_FILTER_EN_REG), +.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG), +.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG), +.RX_PMA_RSV0 (RX_PMA_RSV0_REG), +.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN), +.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG), +.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG), +.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG), +.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG), +.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG), +.RX_SUM_DEGEN_AVTT_OVERITE (RX_SUM_DEGEN_AVTT_OVERITE_REG), +.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG), +.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG), +.RX_SUM_PWR_SAVING (RX_SUM_PWR_SAVING_REG), +.RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG), +.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG), +.RX_SUM_VCM_BIAS_TUNE_EN (RX_SUM_VCM_BIAS_TUNE_EN_REG), +.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG), +.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG), +.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG), +.RX_VREG_CTRL (RX_VREG_CTRL_REG), +.RX_VREG_PDB (RX_VREG_PDB_REG), +.RX_VREG_VREFSEL (RX_VREG_VREFSEL_REG), +.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG), +.RX_WIDEMODE_CDR_GEN3 (RX_WIDEMODE_CDR_GEN3_REG), +.RX_WIDEMODE_CDR_GEN4 (RX_WIDEMODE_CDR_GEN4_REG), +.RX_XCLK_SEL (RX_XCLK_SEL_REG), +.RX_XMODE_SEL (RX_XMODE_SEL_REG), +.SAMPLE_CLK_PHASE (SAMPLE_CLK_PHASE_REG), +.SAS_12G_MODE (SAS_12G_MODE_REG), +.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG), +.SATA_BURST_VAL (SATA_BURST_VAL_REG), +.SATA_CPLL_CFG (SATA_CPLL_CFG_REG), +.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG), +.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG), +.SIM_DEVICE (SIM_DEVICE_REG), +.SIM_MODE (SIM_MODE_REG), +.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG), +.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), +.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG), +.SRSTMODE (SRSTMODE_REG), +.TAPDLY_SET_TX (TAPDLY_SET_TX_REG), +.TERM_RCAL_CFG (TERM_RCAL_CFG_REG), +.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG), +.TRANS_TIME_RATE (TRANS_TIME_RATE_REG), +.TST_RSV0 (TST_RSV0_REG), +.TST_RSV1 (TST_RSV1_REG), +.TXBUF_EN (TXBUF_EN_REG), +.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG), +.TXDLY_CFG (TXDLY_CFG_REG), +.TXDLY_LCFG (TXDLY_LCFG_REG), +.TXDRV_FREQBAND (TXDRV_FREQBAND_REG), +.TXFE_CFG0 (TXFE_CFG0_REG), +.TXFE_CFG1 (TXFE_CFG1_REG), +.TXFE_CFG2 (TXFE_CFG2_REG), +.TXFE_CFG3 (TXFE_CFG3_REG), +.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG), +.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG), +.TXGEARBOX_EN (TXGEARBOX_EN_REG), +.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG), +.TXOUT_DIV (TXOUT_DIV_REG), +.TXPCSRESET_TIME (TXPCSRESET_TIME_REG), +.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG), +.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG), +.TXPH_CFG (TXPH_CFG_REG), +.TXPH_CFG2 (TXPH_CFG2_REG), +.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG), +.TXPI_CFG0 (TXPI_CFG0_REG), +.TXPI_CFG1 (TXPI_CFG1_REG), +.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG), +.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG), +.TXPI_PPM (TXPI_PPM_REG), +.TXPI_PPM_CFG (TXPI_PPM_CFG_REG), +.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG), +.TXPMARESET_TIME (TXPMARESET_TIME_REG), +.TXREFCLKDIV2_SEL (TXREFCLKDIV2_SEL_REG), +.TXSWBST_BST (TXSWBST_BST_REG), +.TXSWBST_EN (TXSWBST_EN_REG), +.TXSWBST_MAG (TXSWBST_MAG_REG), +.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG), +.TXSYNC_OVRD (TXSYNC_OVRD_REG), +.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG), +.TX_CLK25_DIV (TX_CLK25_DIV_REG), +.TX_CLKMUX_EN (TX_CLKMUX_EN_REG), +.TX_DATA_WIDTH (TX_DATA_WIDTH_REG), +.TX_DCC_LOOP_RST_CFG (TX_DCC_LOOP_RST_CFG_REG), +.TX_DEEMPH0 (TX_DEEMPH0_REG), +.TX_DEEMPH1 (TX_DEEMPH1_REG), +.TX_DEEMPH2 (TX_DEEMPH2_REG), +.TX_DEEMPH3 (TX_DEEMPH3_REG), +.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG), +.TX_DRIVE_MODE (TX_DRIVE_MODE_REG), +.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG), +.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG), +.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG), +.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG), +.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG), +.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG), +.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG), +.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG), +.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG), +.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG), +.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG), +.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG), +.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG), +.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG), +.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG), +.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG), +.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG), +.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG), +.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG), +.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG), +.TX_PI_BIASSET (TX_PI_BIASSET_REG), +.TX_PMADATA_OPT (TX_PMADATA_OPT_REG), +.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG), +.TX_PMA_RSV0 (TX_PMA_RSV0_REG), +.TX_PMA_RSV1 (TX_PMA_RSV1_REG), +.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG), +.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN), +.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG), +.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG), +.TX_RXDETECT_REF (TX_RXDETECT_REF_REG), +.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG), +.TX_SW_MEAS (TX_SW_MEAS_REG), +.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG), +.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG), +.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG), +.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG), +.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG), +.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG), +.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG), +.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG), +.TX_VREG_CTRL (TX_VREG_CTRL_REG), +.TX_VREG_PDB (TX_VREG_PDB_REG), +.TX_VREG_VREFSEL (TX_VREG_VREFSEL_REG), +.TX_XCLK_SEL (TX_XCLK_SEL_REG), +.USB_BOTH_BURST_IDLE (USB_BOTH_BURST_IDLE_REG), +.USB_BURSTMAX_U3WAKE (USB_BURSTMAX_U3WAKE_REG), +.USB_BURSTMIN_U3WAKE (USB_BURSTMIN_U3WAKE_REG), +.USB_CLK_COR_EQ_EN (USB_CLK_COR_EQ_EN_REG), +.USB_EXT_CNTL (USB_EXT_CNTL_REG), +.USB_IDLEMAX_POLLING (USB_IDLEMAX_POLLING_REG), +.USB_IDLEMIN_POLLING (USB_IDLEMIN_POLLING_REG), +.USB_LFPSPING_BURST (USB_LFPSPING_BURST_REG), +.USB_LFPSPOLLING_BURST (USB_LFPSPOLLING_BURST_REG), +.USB_LFPSPOLLING_IDLE_MS (USB_LFPSPOLLING_IDLE_MS_REG), +.USB_LFPSU1EXIT_BURST (USB_LFPSU1EXIT_BURST_REG), +.USB_LFPSU2LPEXIT_BURST_MS (USB_LFPSU2LPEXIT_BURST_MS_REG), +.USB_LFPSU3WAKE_BURST_MS (USB_LFPSU3WAKE_BURST_MS_REG), +.USB_LFPS_TPERIOD (USB_LFPS_TPERIOD_REG), +.USB_LFPS_TPERIOD_ACCURATE (USB_LFPS_TPERIOD_ACCURATE_REG), +.USB_MODE (USB_MODE_REG), +.USB_PCIE_ERR_REP_DIS (USB_PCIE_ERR_REP_DIS_REG), +.USB_PING_SATA_MAX_INIT (USB_PING_SATA_MAX_INIT_REG), +.USB_PING_SATA_MIN_INIT (USB_PING_SATA_MIN_INIT_REG), +.USB_POLL_SATA_MAX_BURST (USB_POLL_SATA_MAX_BURST_REG), +.USB_POLL_SATA_MIN_BURST (USB_POLL_SATA_MIN_BURST_REG), +.USB_RAW_ELEC (USB_RAW_ELEC_REG), +.USB_RXIDLE_P0_CTRL (USB_RXIDLE_P0_CTRL_REG), +.USB_TXIDLE_TUNE_ENABLE (USB_TXIDLE_TUNE_ENABLE_REG), +.USB_U1_SATA_MAX_WAKE (USB_U1_SATA_MAX_WAKE_REG), +.USB_U1_SATA_MIN_WAKE (USB_U1_SATA_MIN_WAKE_REG), +.USB_U2_SAS_MAX_COM (USB_U2_SAS_MAX_COM_REG), +.USB_U2_SAS_MIN_COM (USB_U2_SAS_MIN_COM_REG), +.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG), +.Y_ALL_MODE (Y_ALL_MODE_REG), +.BUFGTCE (BUFGTCE_out), +.BUFGTCEMASK (BUFGTCEMASK_out), +.BUFGTDIV (BUFGTDIV_out), +.BUFGTRESET (BUFGTRESET_out), +.BUFGTRSTMASK (BUFGTRSTMASK_out), +.CPLLFBCLKLOST (CPLLFBCLKLOST_out), +.CPLLLOCK (CPLLLOCK_out), +.CPLLREFCLKLOST (CPLLREFCLKLOST_out), +.CSSDSTOPCLKDONE (CSSDSTOPCLKDONE_out), +.DMONITOROUT (DMONITOROUT_out), +.DMONITOROUTCLK (DMONITOROUTCLK_out), +.DRPDO (DRPDO_out), +.DRPRDY (DRPRDY_out), +.EYESCANDATAERROR (EYESCANDATAERROR_out), +.GTPOWERGOOD (GTPOWERGOOD_out), +.GTREFCLKMONITOR (GTREFCLKMONITOR_out), +.GTYTXN (GTYTXN_out), +.GTYTXP (GTYTXP_out), +.PCIERATEGEN3 (PCIERATEGEN3_out), +.PCIERATEIDLE (PCIERATEIDLE_out), +.PCIERATEQPLLPD (PCIERATEQPLLPD_out), +.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out), +.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out), +.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out), +.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out), +.PCIEUSERRATESTART (PCIEUSERRATESTART_out), +.PCSRSVDOUT (PCSRSVDOUT_out), +.PHYSTATUS (PHYSTATUS_out), +.PINRSRVDAS (PINRSRVDAS_out), +.PMASCANOUT (PMASCANOUT_out), +.POWERPRESENT (POWERPRESENT_out), +.RESETEXCEPTION (RESETEXCEPTION_out), +.RXBUFSTATUS (RXBUFSTATUS_out), +.RXBYTEISALIGNED (RXBYTEISALIGNED_out), +.RXBYTEREALIGN (RXBYTEREALIGN_out), +.RXCDRLOCK (RXCDRLOCK_out), +.RXCDRPHDONE (RXCDRPHDONE_out), +.RXCHANBONDSEQ (RXCHANBONDSEQ_out), +.RXCHANISALIGNED (RXCHANISALIGNED_out), +.RXCHANREALIGN (RXCHANREALIGN_out), +.RXCHBONDO (RXCHBONDO_out), +.RXCKCALDONE (RXCKCALDONE_out), +.RXCLKCORCNT (RXCLKCORCNT_out), +.RXCOMINITDET (RXCOMINITDET_out), +.RXCOMMADET (RXCOMMADET_out), +.RXCOMSASDET (RXCOMSASDET_out), +.RXCOMWAKEDET (RXCOMWAKEDET_out), +.RXCTRL0 (RXCTRL0_out), +.RXCTRL1 (RXCTRL1_out), +.RXCTRL2 (RXCTRL2_out), +.RXCTRL3 (RXCTRL3_out), +.RXDATA (RXDATA_out), +.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out), +.RXDATAVALID (RXDATAVALID_out), +.RXDLYSRESETDONE (RXDLYSRESETDONE_out), +.RXELECIDLE (RXELECIDLE_out), +.RXHEADER (RXHEADER_out), +.RXHEADERVALID (RXHEADERVALID_out), +.RXLFPSTRESETDET (RXLFPSTRESETDET_out), +.RXLFPSU2LPEXITDET (RXLFPSU2LPEXITDET_out), +.RXLFPSU3WAKEDET (RXLFPSU3WAKEDET_out), +.RXMONITOROUT (RXMONITOROUT_out), +.RXOSINTDONE (RXOSINTDONE_out), +.RXOSINTSTARTED (RXOSINTSTARTED_out), +.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out), +.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out), +.RXOUTCLK (RXOUTCLK_out), +.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out), +.RXOUTCLKPCS (RXOUTCLKPCS_out), +.RXPHALIGNDONE (RXPHALIGNDONE_out), +.RXPHALIGNERR (RXPHALIGNERR_out), +.RXPMARESETDONE (RXPMARESETDONE_out), +.RXPRBSERR (RXPRBSERR_out), +.RXPRBSLOCKED (RXPRBSLOCKED_out), +.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out), +.RXRATEDONE (RXRATEDONE_out), +.RXRECCLKOUT (RXRECCLKOUT_out), +.RXRESETDONE (RXRESETDONE_out), +.RXSLIDERDY (RXSLIDERDY_out), +.RXSLIPDONE (RXSLIPDONE_out), +.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out), +.RXSLIPPMARDY (RXSLIPPMARDY_out), +.RXSTARTOFSEQ (RXSTARTOFSEQ_out), +.RXSTATUS (RXSTATUS_out), +.RXSYNCDONE (RXSYNCDONE_out), +.RXSYNCOUT (RXSYNCOUT_out), +.RXVALID (RXVALID_out), +.SCANOUT (SCANOUT_out), +.TXBUFSTATUS (TXBUFSTATUS_out), +.TXCOMFINISH (TXCOMFINISH_out), +.TXDCCDONE (TXDCCDONE_out), +.TXDLYSRESETDONE (TXDLYSRESETDONE_out), +.TXOUTCLK (TXOUTCLK_out), +.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out), +.TXOUTCLKPCS (TXOUTCLKPCS_out), +.TXPHALIGNDONE (TXPHALIGNDONE_out), +.TXPHINITDONE (TXPHINITDONE_out), +.TXPMARESETDONE (TXPMARESETDONE_out), +.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out), +.TXRATEDONE (TXRATEDONE_out), +.TXRESETDONE (TXRESETDONE_out), +.TXSYNCDONE (TXSYNCDONE_out), +.TXSYNCOUT (TXSYNCOUT_out), +.BSR_SERIAL (BSR_SERIAL_in), +.CDRSTEPDIR (CDRSTEPDIR_in), +.CDRSTEPSQ (CDRSTEPSQ_in), +.CDRSTEPSX (CDRSTEPSX_in), +.CFGRESET (CFGRESET_in), +.CLKRSVD0 (CLKRSVD0_in), +.CLKRSVD1 (CLKRSVD1_in), +.CPLLFREQLOCK (CPLLFREQLOCK_in), +.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in), +.CPLLLOCKEN (CPLLLOCKEN_in), +.CPLLPD (CPLLPD_in), +.CPLLREFCLKSEL (CPLLREFCLKSEL_in), +.CPLLRESET (CPLLRESET_in), +.CSSDRSTB (CSSDRSTB_in), +.CSSDSTOPCLK (CSSDSTOPCLK_in), +.DMONFIFORESET (DMONFIFORESET_in), +.DMONITORCLK (DMONITORCLK_in), +.DRPADDR (DRPADDR_in), +.DRPCLK (DRPCLK_in), +.DRPDI (DRPDI_in), +.DRPEN (DRPEN_in), +.DRPRST (DRPRST_in), +.DRPWE (DRPWE_in), +.EYESCANRESET (EYESCANRESET_in), +.EYESCANTRIGGER (EYESCANTRIGGER_in), +.FREQOS (FREQOS_in), +.GTGREFCLK (GTGREFCLK_in), +.GTNORTHREFCLK0 (GTNORTHREFCLK0_in), +.GTNORTHREFCLK1 (GTNORTHREFCLK1_in), +.GTREFCLK0 (GTREFCLK0_in), +.GTREFCLK1 (GTREFCLK1_in), +.GTRSVD (GTRSVD_in), +.GTRXRESET (GTRXRESET_in), +.GTRXRESETSEL (GTRXRESETSEL_in), +.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in), +.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in), +.GTTXRESET (GTTXRESET_in), +.GTTXRESETSEL (GTTXRESETSEL_in), +.GTYRXN (GTYRXN_in), +.GTYRXP (GTYRXP_in), +.INCPCTRL (INCPCTRL_in), +.LOOPBACK (LOOPBACK_in), +.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in), +.PCIERSTIDLE (PCIERSTIDLE_in), +.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in), +.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in), +.PCSRSVDIN (PCSRSVDIN_in), +.PMASCANCLK0 (PMASCANCLK0_in), +.PMASCANCLK1 (PMASCANCLK1_in), +.PMASCANCLK2 (PMASCANCLK2_in), +.PMASCANCLK3 (PMASCANCLK3_in), +.PMASCANCLK4 (PMASCANCLK4_in), +.PMASCANCLK5 (PMASCANCLK5_in), +.PMASCANCLK6 (PMASCANCLK6_in), +.PMASCANCLK7 (PMASCANCLK7_in), +.PMASCANCLK8 (PMASCANCLK8_in), +.PMASCANENB (PMASCANENB_in), +.PMASCANIN (PMASCANIN_in), +.PMASCANMODEB (PMASCANMODEB_in), +.PMASCANRSTEN (PMASCANRSTEN_in), +.QPLL0CLK (QPLL0CLK_in), +.QPLL0FREQLOCK (QPLL0FREQLOCK_in), +.QPLL0REFCLK (QPLL0REFCLK_in), +.QPLL1CLK (QPLL1CLK_in), +.QPLL1FREQLOCK (QPLL1FREQLOCK_in), +.QPLL1REFCLK (QPLL1REFCLK_in), +.RESETOVRD (RESETOVRD_in), +.RX8B10BEN (RX8B10BEN_in), +.RXAFECFOKEN (RXAFECFOKEN_in), +.RXBUFRESET (RXBUFRESET_in), +.RXCDRFREQRESET (RXCDRFREQRESET_in), +.RXCDRHOLD (RXCDRHOLD_in), +.RXCDROVRDEN (RXCDROVRDEN_in), +.RXCDRRESET (RXCDRRESET_in), +.RXCHBONDEN (RXCHBONDEN_in), +.RXCHBONDI (RXCHBONDI_in), +.RXCHBONDLEVEL (RXCHBONDLEVEL_in), +.RXCHBONDMASTER (RXCHBONDMASTER_in), +.RXCHBONDSLAVE (RXCHBONDSLAVE_in), +.RXCKCALRESET (RXCKCALRESET_in), +.RXCKCALSTART (RXCKCALSTART_in), +.RXCOMMADETEN (RXCOMMADETEN_in), +.RXDFEAGCHOLD (RXDFEAGCHOLD_in), +.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in), +.RXDFECFOKFCNUM (RXDFECFOKFCNUM_in), +.RXDFECFOKFEN (RXDFECFOKFEN_in), +.RXDFECFOKFPULSE (RXDFECFOKFPULSE_in), +.RXDFECFOKHOLD (RXDFECFOKHOLD_in), +.RXDFECFOKOVREN (RXDFECFOKOVREN_in), +.RXDFEKHHOLD (RXDFEKHHOLD_in), +.RXDFEKHOVRDEN (RXDFEKHOVRDEN_in), +.RXDFELFHOLD (RXDFELFHOLD_in), +.RXDFELFOVRDEN (RXDFELFOVRDEN_in), +.RXDFELPMRESET (RXDFELPMRESET_in), +.RXDFETAP10HOLD (RXDFETAP10HOLD_in), +.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in), +.RXDFETAP11HOLD (RXDFETAP11HOLD_in), +.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in), +.RXDFETAP12HOLD (RXDFETAP12HOLD_in), +.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in), +.RXDFETAP13HOLD (RXDFETAP13HOLD_in), +.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in), +.RXDFETAP14HOLD (RXDFETAP14HOLD_in), +.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in), +.RXDFETAP15HOLD (RXDFETAP15HOLD_in), +.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in), +.RXDFETAP2HOLD (RXDFETAP2HOLD_in), +.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in), +.RXDFETAP3HOLD (RXDFETAP3HOLD_in), +.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in), +.RXDFETAP4HOLD (RXDFETAP4HOLD_in), +.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in), +.RXDFETAP5HOLD (RXDFETAP5HOLD_in), +.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in), +.RXDFETAP6HOLD (RXDFETAP6HOLD_in), +.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in), +.RXDFETAP7HOLD (RXDFETAP7HOLD_in), +.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in), +.RXDFETAP8HOLD (RXDFETAP8HOLD_in), +.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in), +.RXDFETAP9HOLD (RXDFETAP9HOLD_in), +.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in), +.RXDFEUTHOLD (RXDFEUTHOLD_in), +.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in), +.RXDFEVPHOLD (RXDFEVPHOLD_in), +.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in), +.RXDFEXYDEN (RXDFEXYDEN_in), +.RXDLYBYPASS (RXDLYBYPASS_in), +.RXDLYEN (RXDLYEN_in), +.RXDLYOVRDEN (RXDLYOVRDEN_in), +.RXDLYSRESET (RXDLYSRESET_in), +.RXELECIDLEMODE (RXELECIDLEMODE_in), +.RXEQTRAINING (RXEQTRAINING_in), +.RXGEARBOXSLIP (RXGEARBOXSLIP_in), +.RXLATCLK (RXLATCLK_in), +.RXLPMEN (RXLPMEN_in), +.RXLPMGCHOLD (RXLPMGCHOLD_in), +.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in), +.RXLPMHFHOLD (RXLPMHFHOLD_in), +.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in), +.RXLPMLFHOLD (RXLPMLFHOLD_in), +.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in), +.RXLPMOSHOLD (RXLPMOSHOLD_in), +.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in), +.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in), +.RXMONITORSEL (RXMONITORSEL_in), +.RXOOBRESET (RXOOBRESET_in), +.RXOSCALRESET (RXOSCALRESET_in), +.RXOSHOLD (RXOSHOLD_in), +.RXOSOVRDEN (RXOSOVRDEN_in), +.RXOUTCLKSEL (RXOUTCLKSEL_in), +.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in), +.RXPCSRESET (RXPCSRESET_in), +.RXPD (RXPD_in), +.RXPHALIGN (RXPHALIGN_in), +.RXPHALIGNEN (RXPHALIGNEN_in), +.RXPHDLYPD (RXPHDLYPD_in), +.RXPHDLYRESET (RXPHDLYRESET_in), +.RXPLLCLKSEL (RXPLLCLKSEL_in), +.RXPMARESET (RXPMARESET_in), +.RXPOLARITY (RXPOLARITY_in), +.RXPRBSCNTRESET (RXPRBSCNTRESET_in), +.RXPRBSSEL (RXPRBSSEL_in), +.RXPROGDIVRESET (RXPROGDIVRESET_in), +.RXRATE (RXRATE_in), +.RXRATEMODE (RXRATEMODE_in), +.RXSLIDE (RXSLIDE_in), +.RXSLIPOUTCLK (RXSLIPOUTCLK_in), +.RXSLIPPMA (RXSLIPPMA_in), +.RXSYNCALLIN (RXSYNCALLIN_in), +.RXSYNCIN (RXSYNCIN_in), +.RXSYNCMODE (RXSYNCMODE_in), +.RXSYSCLKSEL (RXSYSCLKSEL_in), +.RXTERMINATION (RXTERMINATION_in), +.RXUSERRDY (RXUSERRDY_in), +.RXUSRCLK (RXUSRCLK_in), +.RXUSRCLK2 (RXUSRCLK2_in), +.SARCCLK (SARCCLK_in), +.SCANCLK (SCANCLK_in), +.SCANENB (SCANENB_in), +.SCANIN (SCANIN_in), +.SCANMODEB (SCANMODEB_in), +.SCANRSTB (SCANRSTB_in), +.SCANRSTEN (SCANRSTEN_in), +.SIGVALIDCLK (SIGVALIDCLK_in), +.TSTCLK0 (TSTCLK0_in), +.TSTCLK1 (TSTCLK1_in), +.TSTIN (TSTIN_in), +.TSTPD (TSTPD_in), +.TSTPDOVRDB (TSTPDOVRDB_in), +.TX8B10BBYPASS (TX8B10BBYPASS_in), +.TX8B10BEN (TX8B10BEN_in), +.TXCOMINIT (TXCOMINIT_in), +.TXCOMSAS (TXCOMSAS_in), +.TXCOMWAKE (TXCOMWAKE_in), +.TXCTRL0 (TXCTRL0_in), +.TXCTRL1 (TXCTRL1_in), +.TXCTRL2 (TXCTRL2_in), +.TXDATA (TXDATA_in), +.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in), +.TXDCCFORCESTART (TXDCCFORCESTART_in), +.TXDCCRESET (TXDCCRESET_in), +.TXDEEMPH (TXDEEMPH_in), +.TXDETECTRX (TXDETECTRX_in), +.TXDIFFCTRL (TXDIFFCTRL_in), +.TXDLYBYPASS (TXDLYBYPASS_in), +.TXDLYEN (TXDLYEN_in), +.TXDLYHOLD (TXDLYHOLD_in), +.TXDLYOVRDEN (TXDLYOVRDEN_in), +.TXDLYSRESET (TXDLYSRESET_in), +.TXDLYUPDOWN (TXDLYUPDOWN_in), +.TXELECIDLE (TXELECIDLE_in), +.TXHEADER (TXHEADER_in), +.TXINHIBIT (TXINHIBIT_in), +.TXLATCLK (TXLATCLK_in), +.TXLFPSTRESET (TXLFPSTRESET_in), +.TXLFPSU2LPEXIT (TXLFPSU2LPEXIT_in), +.TXLFPSU3WAKE (TXLFPSU3WAKE_in), +.TXMAINCURSOR (TXMAINCURSOR_in), +.TXMARGIN (TXMARGIN_in), +.TXMUXDCDEXHOLD (TXMUXDCDEXHOLD_in), +.TXMUXDCDORWREN (TXMUXDCDORWREN_in), +.TXONESZEROS (TXONESZEROS_in), +.TXOUTCLKSEL (TXOUTCLKSEL_in), +.TXPCSRESET (TXPCSRESET_in), +.TXPD (TXPD_in), +.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in), +.TXPHALIGN (TXPHALIGN_in), +.TXPHALIGNEN (TXPHALIGNEN_in), +.TXPHDLYPD (TXPHDLYPD_in), +.TXPHDLYRESET (TXPHDLYRESET_in), +.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in), +.TXPHINIT (TXPHINIT_in), +.TXPHOVRDEN (TXPHOVRDEN_in), +.TXPIPPMEN (TXPIPPMEN_in), +.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in), +.TXPIPPMPD (TXPIPPMPD_in), +.TXPIPPMSEL (TXPIPPMSEL_in), +.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in), +.TXPISOPD (TXPISOPD_in), +.TXPLLCLKSEL (TXPLLCLKSEL_in), +.TXPMARESET (TXPMARESET_in), +.TXPOLARITY (TXPOLARITY_in), +.TXPOSTCURSOR (TXPOSTCURSOR_in), +.TXPRBSFORCEERR (TXPRBSFORCEERR_in), +.TXPRBSSEL (TXPRBSSEL_in), +.TXPRECURSOR (TXPRECURSOR_in), +.TXPROGDIVRESET (TXPROGDIVRESET_in), +.TXRATE (TXRATE_in), +.TXRATEMODE (TXRATEMODE_in), +.TXSEQUENCE (TXSEQUENCE_in), +.TXSWING (TXSWING_in), +.TXSYNCALLIN (TXSYNCALLIN_in), +.TXSYNCIN (TXSYNCIN_in), +.TXSYNCMODE (TXSYNCMODE_in), +.TXSYSCLKSEL (TXSYSCLKSEL_in), +.TXUSERRDY (TXUSERRDY_in), +.TXUSRCLK (TXUSRCLK_in), +.TXUSRCLK2 (TXUSRCLK2_in), +.GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0); + (DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0); + (DRPCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (DRPCLK => RXLFPSTRESETDET) = (100:100:100, 100:100:100); + (GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0); + (RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK => RXLFPSTRESETDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCHBONDO[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL0[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL1[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[100]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[101]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[102]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[103]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[104]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[105]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[106]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[107]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[108]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[109]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[110]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[111]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[112]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[113]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[114]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[115]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[116]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[117]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[118]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[119]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[120]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[121]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[122]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[123]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[124]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[125]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[126]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[127]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[64]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[65]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[66]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[67]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[68]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[69]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[70]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[71]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[72]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[73]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[74]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[75]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[76]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[77]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[78]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[79]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[80]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[81]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[82]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[83]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[84]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[85]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[86]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[87]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[88]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[89]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[90]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[91]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[92]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[93]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[94]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[95]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[96]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[97]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[98]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[99]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXRESETDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100); + (RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100); + (TXUSRCLK => RXLFPSTRESETDET) = (0:0:0, 0:0:0); + (TXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100); + (TXUSRCLK2 => TXRESETDONE) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK, 0:0:0, notifier); + $period (negedge RXUSRCLK2, 0:0:0, notifier); + $period (negedge TXUSRCLK, 0:0:0, notifier); + $period (negedge TXUSRCLK2, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK, 0:0:0, notifier); + $period (posedge RXUSRCLK2, 0:0:0, notifier); + $period (posedge TXUSRCLK, 0:0:0, notifier); + $period (posedge TXUSRCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay); + $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]); + $setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]); + $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay); + $setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]); + $setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]); + $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay); + $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]); + $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK, 0:0:0, 0, notifier); + $width (negedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK, 0:0:0, 0, notifier); + $width (negedge TXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK, 0:0:0, 0, notifier); + $width (posedge RXUSRCLK2, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK, 0:0:0, 0, notifier); + $width (posedge TXUSRCLK2, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/GTYE4_COMMON.v b/verilog/src/unisims/GTYE4_COMMON.v new file mode 100644 index 0000000..01b61cb --- /dev/null +++ b/verilog/src/unisims/GTYE4_COMMON.v @@ -0,0 +1,1391 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver for UltraScale+ devices +// /___/ /\ Filename : GTYE4_COMMON.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module GTYE4_COMMON #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1, + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1, + parameter [0:0] AEN_SDM0TOGGLE = 1'b0, + parameter [0:0] AEN_SDM1TOGGLE = 1'b0, + parameter [0:0] A_SDM0TOGGLE = 1'b0, + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000, + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000, + parameter [0:0] A_SDM1TOGGLE = 1'b0, + parameter [15:0] BIAS_CFG0 = 16'h0000, + parameter [15:0] BIAS_CFG1 = 16'h0000, + parameter [15:0] BIAS_CFG2 = 16'h0000, + parameter [15:0] BIAS_CFG3 = 16'h0000, + parameter [15:0] BIAS_CFG4 = 16'h0000, + parameter [15:0] BIAS_CFG_RSVD = 16'h0000, + parameter [15:0] COMMON_CFG0 = 16'h0000, + parameter [15:0] COMMON_CFG1 = 16'h0000, + parameter [15:0] POR_CFG = 16'h0000, + parameter [15:0] PPF0_CFG = 16'h0F00, + parameter [15:0] PPF1_CFG = 16'h0F00, + parameter QPLL0CLKOUT_RATE = "FULL", + parameter [15:0] QPLL0_CFG0 = 16'h391C, + parameter [15:0] QPLL0_CFG1 = 16'h0000, + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL0_CFG2 = 16'h0F80, + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80, + parameter [15:0] QPLL0_CFG3 = 16'h0120, + parameter [15:0] QPLL0_CFG4 = 16'h0002, + parameter [9:0] QPLL0_CP = 10'b0000011111, + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111, + parameter integer QPLL0_FBDIV = 66, + parameter integer QPLL0_FBDIV_G3 = 80, + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL0_LPF = 10'b1011111111, + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111, + parameter [0:0] QPLL0_PCI_EN = 1'b0, + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0, + parameter integer QPLL0_REFCLK_DIV = 1, + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040, + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000, + parameter QPLL1CLKOUT_RATE = "FULL", + parameter [15:0] QPLL1_CFG0 = 16'h691C, + parameter [15:0] QPLL1_CFG1 = 16'h0020, + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020, + parameter [15:0] QPLL1_CFG2 = 16'h0F80, + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80, + parameter [15:0] QPLL1_CFG3 = 16'h0120, + parameter [15:0] QPLL1_CFG4 = 16'h0002, + parameter [9:0] QPLL1_CP = 10'b0000011111, + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111, + parameter integer QPLL1_FBDIV = 66, + parameter integer QPLL1_FBDIV_G3 = 80, + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000, + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00, + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8, + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8, + parameter [9:0] QPLL1_LPF = 10'b1011111111, + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111, + parameter [0:0] QPLL1_PCI_EN = 1'b0, + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0, + parameter integer QPLL1_REFCLK_DIV = 1, + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000, + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000, + parameter [15:0] RSVD_ATTR0 = 16'h0000, + parameter [15:0] RSVD_ATTR1 = 16'h0000, + parameter [15:0] RSVD_ATTR2 = 16'h0000, + parameter [15:0] RSVD_ATTR3 = 16'h0000, + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00, + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00, + parameter [0:0] SARC_ENB = 1'b0, + parameter [0:0] SARC_SEL = 1'b0, + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000, + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000, + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SIM_MODE = "FAST", + parameter SIM_RESET_SPEEDUP = "TRUE", + parameter [15:0] UB_CFG0 = 16'h0000, + parameter [15:0] UB_CFG1 = 16'h0000, + parameter [15:0] UB_CFG2 = 16'h0000, + parameter [15:0] UB_CFG3 = 16'h0000, + parameter [15:0] UB_CFG4 = 16'h0000, + parameter [15:0] UB_CFG5 = 16'h0400, + parameter [15:0] UB_CFG6 = 16'h0000 +)( + output [15:0] DRPDO, + output DRPRDY, + output [7:0] PMARSVDOUT0, + output [7:0] PMARSVDOUT1, + output QPLL0FBCLKLOST, + output QPLL0LOCK, + output QPLL0OUTCLK, + output QPLL0OUTREFCLK, + output QPLL0REFCLKLOST, + output QPLL1FBCLKLOST, + output QPLL1LOCK, + output QPLL1OUTCLK, + output QPLL1OUTREFCLK, + output QPLL1REFCLKLOST, + output [7:0] QPLLDMONITOR0, + output [7:0] QPLLDMONITOR1, + output REFCLKOUTMONITOR0, + output REFCLKOUTMONITOR1, + output [1:0] RXRECCLK0SEL, + output [1:0] RXRECCLK1SEL, + output [3:0] SDM0FINALOUT, + output [14:0] SDM0TESTDATA, + output [3:0] SDM1FINALOUT, + output [14:0] SDM1TESTDATA, + output [15:0] UBDADDR, + output UBDEN, + output [15:0] UBDI, + output UBDWE, + output UBMDMTDO, + output UBRSVDOUT, + output UBTXUART, + + input BGBYPASSB, + input BGMONITORENB, + input BGPDB, + input [4:0] BGRCALOVRD, + input BGRCALOVRDENB, + input [15:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input GTGREFCLK0, + input GTGREFCLK1, + input GTNORTHREFCLK00, + input GTNORTHREFCLK01, + input GTNORTHREFCLK10, + input GTNORTHREFCLK11, + input GTREFCLK00, + input GTREFCLK01, + input GTREFCLK10, + input GTREFCLK11, + input GTSOUTHREFCLK00, + input GTSOUTHREFCLK01, + input GTSOUTHREFCLK10, + input GTSOUTHREFCLK11, + input [2:0] PCIERATEQPLL0, + input [2:0] PCIERATEQPLL1, + input [7:0] PMARSVD0, + input [7:0] PMARSVD1, + input QPLL0CLKRSVD0, + input QPLL0CLKRSVD1, + input [7:0] QPLL0FBDIV, + input QPLL0LOCKDETCLK, + input QPLL0LOCKEN, + input QPLL0PD, + input [2:0] QPLL0REFCLKSEL, + input QPLL0RESET, + input QPLL1CLKRSVD0, + input QPLL1CLKRSVD1, + input [7:0] QPLL1FBDIV, + input QPLL1LOCKDETCLK, + input QPLL1LOCKEN, + input QPLL1PD, + input [2:0] QPLL1REFCLKSEL, + input QPLL1RESET, + input [7:0] QPLLRSVD1, + input [4:0] QPLLRSVD2, + input [4:0] QPLLRSVD3, + input [7:0] QPLLRSVD4, + input RCALENB, + input [24:0] SDM0DATA, + input SDM0RESET, + input SDM0TOGGLE, + input [1:0] SDM0WIDTH, + input [24:0] SDM1DATA, + input SDM1RESET, + input SDM1TOGGLE, + input [1:0] SDM1WIDTH, + input UBCFGSTREAMEN, + input [15:0] UBDO, + input UBDRDY, + input UBENABLE, + input [1:0] UBGPI, + input [1:0] UBINTR, + input UBIOLMBRST, + input UBMBRST, + input UBMDMCAPTURE, + input UBMDMDBGRST, + input UBMDMDBGUPDATE, + input [3:0] UBMDMREGEN, + input UBMDMSHIFT, + input UBMDMSYSRST, + input UBMDMTCK, + input UBMDMTDI +); + +// define constants + localparam MODULE_NAME = "GTYE4_COMMON"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "GTYE4_COMMON_dr.v" +`else + localparam [0:0] AEN_QPLL0_FBDIV_REG = AEN_QPLL0_FBDIV; + localparam [0:0] AEN_QPLL1_FBDIV_REG = AEN_QPLL1_FBDIV; + localparam [0:0] AEN_SDM0TOGGLE_REG = AEN_SDM0TOGGLE; + localparam [0:0] AEN_SDM1TOGGLE_REG = AEN_SDM1TOGGLE; + localparam [0:0] A_SDM0TOGGLE_REG = A_SDM0TOGGLE; + localparam [8:0] A_SDM1DATA_HIGH_REG = A_SDM1DATA_HIGH; + localparam [15:0] A_SDM1DATA_LOW_REG = A_SDM1DATA_LOW; + localparam [0:0] A_SDM1TOGGLE_REG = A_SDM1TOGGLE; + localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0; + localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1; + localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2; + localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3; + localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4; + localparam [15:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD; + localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0; + localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1; + localparam [15:0] POR_CFG_REG = POR_CFG; + localparam [15:0] PPF0_CFG_REG = PPF0_CFG; + localparam [15:0] PPF1_CFG_REG = PPF1_CFG; + localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE; + localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0; + localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1; + localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3; + localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2; + localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3; + localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3; + localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4; + localparam [9:0] QPLL0_CP_REG = QPLL0_CP; + localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3; + localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV; + localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3; + localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0; + localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1; + localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG; + localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3; + localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF; + localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3; + localparam [0:0] QPLL0_PCI_EN_REG = QPLL0_PCI_EN; + localparam [0:0] QPLL0_RATE_SW_USE_DRP_REG = QPLL0_RATE_SW_USE_DRP; + localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV; + localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0; + localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1; + localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2; + localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE; + localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0; + localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1; + localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3; + localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2; + localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3; + localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3; + localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4; + localparam [9:0] QPLL1_CP_REG = QPLL1_CP; + localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3; + localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV; + localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3; + localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0; + localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1; + localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG; + localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3; + localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF; + localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3; + localparam [0:0] QPLL1_PCI_EN_REG = QPLL1_PCI_EN; + localparam [0:0] QPLL1_RATE_SW_USE_DRP_REG = QPLL1_RATE_SW_USE_DRP; + localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV; + localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0; + localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1; + localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2; + localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0; + localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1; + localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2; + localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3; + localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL; + localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL; + localparam [0:0] SARC_ENB_REG = SARC_ENB; + localparam [0:0] SARC_SEL_REG = SARC_SEL; + localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0; + localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1; + localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0; + localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1; + localparam [160:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [48:1] SIM_MODE_REG = SIM_MODE; + localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP; + localparam [15:0] UB_CFG0_REG = UB_CFG0; + localparam [15:0] UB_CFG1_REG = UB_CFG1; + localparam [15:0] UB_CFG2_REG = UB_CFG2; + localparam [15:0] UB_CFG3_REG = UB_CFG3; + localparam [15:0] UB_CFG4_REG = UB_CFG4; + localparam [15:0] UB_CFG5_REG = UB_CFG5; + localparam [15:0] UB_CFG6_REG = UB_CFG6; +`endif + + localparam [0:0] AEN_BGBS0_REG = 1'b0; + localparam [0:0] AEN_BGBS1_REG = 1'b0; + localparam [0:0] AEN_MASTER0_REG = 1'b0; + localparam [0:0] AEN_MASTER1_REG = 1'b0; + localparam [0:0] AEN_PD0_REG = 1'b0; + localparam [0:0] AEN_PD1_REG = 1'b0; + localparam [0:0] AEN_QPLL0_REG = 1'b0; + localparam [0:0] AEN_QPLL1_REG = 1'b0; + localparam [0:0] AEN_REFCLK0_REG = 1'b0; + localparam [0:0] AEN_REFCLK1_REG = 1'b0; + localparam [0:0] AEN_RESET0_REG = 1'b0; + localparam [0:0] AEN_RESET1_REG = 1'b0; + localparam [0:0] AEN_SDM0DATA_REG = 1'b0; + localparam [0:0] AEN_SDM0RESET_REG = 1'b0; + localparam [0:0] AEN_SDM0WIDTH_REG = 1'b0; + localparam [0:0] AEN_SDM1DATA_REG = 1'b0; + localparam [0:0] AEN_SDM1RESET_REG = 1'b0; + localparam [0:0] AEN_SDM1WIDTH_REG = 1'b0; + localparam [3:0] AQDMUXSEL1_REG = 4'b0000; + localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000; + localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000; + localparam [0:0] A_BGMONITOREN_REG = 1'b0; + localparam [0:0] A_BGPD_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD0_REG = 1'b0; + localparam [0:0] A_GTREFCLKPD1_REG = 1'b0; + localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL0PD_REG = 1'b0; + localparam [0:0] A_QPLL0RESET_REG = 1'b0; + localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0; + localparam [0:0] A_QPLL1PD_REG = 1'b0; + localparam [0:0] A_QPLL1RESET_REG = 1'b0; + localparam [8:0] A_SDM0DATA_HIGH_REG = 9'b000000000; + localparam [15:0] A_SDM0DATA_LOW_REG = 16'b0000000000000000; + localparam [0:0] A_SDM0RESET_REG = 1'b0; + localparam [0:0] A_SDM1RESET_REG = 1'b0; + localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00; + localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00; + localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1; + localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000; + localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000; + localparam [0:0] RCALSAP_TESTEN_REG = 1'b0; + localparam [0:0] RCAL_APROBE_REG = 1'b0; + localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0; + localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0; + localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0; + localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CSSDSTOPCLKDONE0_out; + wire CSSDSTOPCLKDONE1_out; + wire DRPRDY_out; + wire QPLL0FBCLKLOST_out; + wire QPLL0LOCK_out; + wire QPLL0OUTCLK_out; + wire QPLL0OUTREFCLK_out; + wire QPLL0REFCLKLOST_out; + wire QPLL1FBCLKLOST_out; + wire QPLL1LOCK_out; + wire QPLL1OUTCLK_out; + wire QPLL1OUTREFCLK_out; + wire QPLL1REFCLKLOST_out; + wire REFCLKOUTMONITOR0_out; + wire REFCLKOUTMONITOR1_out; + wire UBDEN_out; + wire UBDWE_out; + wire UBMDMTDO_out; + wire UBRSVDOUT_out; + wire UBTXUART_out; + wire [13:0] PMASCANOUT_out; + wire [14:0] SDM0TESTDATA_out; + wire [14:0] SDM1TESTDATA_out; + wire [15:0] DRPDO_out; + wire [15:0] UBDADDR_out; + wire [15:0] UBDI_out; + wire [1:0] RXRECCLK0SEL_out; + wire [1:0] RXRECCLK1SEL_out; + wire [3:0] SARCCLK_out; + wire [3:0] SDM0FINALOUT_out; + wire [3:0] SDM1FINALOUT_out; + wire [7:0] PMARSVDOUT0_out; + wire [7:0] PMARSVDOUT1_out; + wire [7:0] QPLLDMONITOR0_out; + wire [7:0] QPLLDMONITOR1_out; + + wire BGBYPASSB_in; + wire BGMONITORENB_in; + wire BGPDB_in; + wire BGRCALOVRDENB_in; + wire CSSDSTOPCLK0_in; + wire CSSDSTOPCLK1_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire GTGREFCLK0_in; + wire GTGREFCLK1_in; + wire GTNORTHREFCLK00_in; + wire GTNORTHREFCLK01_in; + wire GTNORTHREFCLK10_in; + wire GTNORTHREFCLK11_in; + wire GTREFCLK00_in; + wire GTREFCLK01_in; + wire GTREFCLK10_in; + wire GTREFCLK11_in; + wire GTSOUTHREFCLK00_in; + wire GTSOUTHREFCLK01_in; + wire GTSOUTHREFCLK10_in; + wire GTSOUTHREFCLK11_in; + wire PMASCANENB_in; + wire QDPMASCANMODEB_in; + wire QDPMASCANRSTEN_in; + wire QPLL0CLKRSVD0_in; + wire QPLL0CLKRSVD1_in; + wire QPLL0LOCKDETCLK_in; + wire QPLL0LOCKEN_in; + wire QPLL0PD_in; + wire QPLL0RESET_in; + wire QPLL1CLKRSVD0_in; + wire QPLL1CLKRSVD1_in; + wire QPLL1LOCKDETCLK_in; + wire QPLL1LOCKEN_in; + wire QPLL1PD_in; + wire QPLL1RESET_in; + wire RCALENB_in; + wire SDM0RESET_in; + wire SDM0TOGGLE_in; + wire SDM1RESET_in; + wire SDM1TOGGLE_in; + wire UBCFGSTREAMEN_in; + wire UBDRDY_in; + wire UBENABLE_in; + wire UBIOLMBRST_in; + wire UBMBRST_in; + wire UBMDMCAPTURE_in; + wire UBMDMDBGRST_in; + wire UBMDMDBGUPDATE_in; + wire UBMDMSHIFT_in; + wire UBMDMSYSRST_in; + wire UBMDMTCK_in; + wire UBMDMTDI_in; + wire [13:0] PMASCANCLK_in; + wire [13:0] PMASCANIN_in; + wire [15:0] DRPADDR_in; + wire [15:0] DRPDI_in; + wire [15:0] UBDO_in; + wire [1:0] SDM0WIDTH_in; + wire [1:0] SDM1WIDTH_in; + wire [1:0] UBGPI_in; + wire [1:0] UBINTR_in; + wire [24:0] SDM0DATA_in; + wire [24:0] SDM1DATA_in; + wire [2:0] PCIERATEQPLL0_in; + wire [2:0] PCIERATEQPLL1_in; + wire [2:0] QPLL0REFCLKSEL_in; + wire [2:0] QPLL1REFCLKSEL_in; + wire [3:0] RXRECCLK_in; + wire [3:0] UBMDMREGEN_in; + wire [4:0] BGRCALOVRD_in; + wire [4:0] QPLLRSVD2_in; + wire [4:0] QPLLRSVD3_in; + wire [7:0] PMARSVD0_in; + wire [7:0] PMARSVD1_in; + wire [7:0] QPLL0FBDIV_in; + wire [7:0] QPLL1FBDIV_in; + wire [7:0] QPLLRSVD1_in; + wire [7:0] QPLLRSVD4_in; + +`ifdef XIL_TIMING + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire UBDRDY_delay; + wire [15:0] DRPADDR_delay; + wire [15:0] DRPDI_delay; + wire [15:0] UBDO_delay; +`endif + + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign PMARSVDOUT0 = PMARSVDOUT0_out; + assign PMARSVDOUT1 = PMARSVDOUT1_out; + assign QPLL0FBCLKLOST = QPLL0FBCLKLOST_out; + assign QPLL0LOCK = QPLL0LOCK_out; + assign QPLL0OUTCLK = QPLL0OUTCLK_out; + assign QPLL0OUTREFCLK = QPLL0OUTREFCLK_out; + assign QPLL0REFCLKLOST = QPLL0REFCLKLOST_out; + assign QPLL1FBCLKLOST = QPLL1FBCLKLOST_out; + assign QPLL1LOCK = QPLL1LOCK_out; + assign QPLL1OUTCLK = QPLL1OUTCLK_out; + assign QPLL1OUTREFCLK = QPLL1OUTREFCLK_out; + assign QPLL1REFCLKLOST = QPLL1REFCLKLOST_out; + assign QPLLDMONITOR0 = QPLLDMONITOR0_out; + assign QPLLDMONITOR1 = QPLLDMONITOR1_out; + assign REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_out; + assign REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_out; + assign RXRECCLK0SEL = RXRECCLK0SEL_out; + assign RXRECCLK1SEL = RXRECCLK1SEL_out; + assign SDM0FINALOUT = SDM0FINALOUT_out; + assign SDM0TESTDATA = SDM0TESTDATA_out; + assign SDM1FINALOUT = SDM1FINALOUT_out; + assign SDM1TESTDATA = SDM1TESTDATA_out; + assign UBDADDR = UBDADDR_out; + assign UBDEN = UBDEN_out; + assign UBDI = UBDI_out; + assign UBDWE = UBDWE_out; + assign UBMDMTDO = UBMDMTDO_out; + assign UBRSVDOUT = UBRSVDOUT_out; + assign UBTXUART = UBTXUART_out; + +`ifdef XIL_TIMING + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR_delay[10]; // rv 0 + assign DRPADDR_in[11] = (DRPADDR[11] !== 1'bz) && DRPADDR_delay[11]; // rv 0 + assign DRPADDR_in[12] = (DRPADDR[12] !== 1'bz) && DRPADDR_delay[12]; // rv 0 + assign DRPADDR_in[13] = (DRPADDR[13] !== 1'bz) && DRPADDR_delay[13]; // rv 0 + assign DRPADDR_in[14] = (DRPADDR[14] !== 1'bz) && DRPADDR_delay[14]; // rv 0 + assign DRPADDR_in[15] = (DRPADDR[15] !== 1'bz) && DRPADDR_delay[15]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign UBDO_in[0] = (UBDO[0] !== 1'bz) && UBDO_delay[0]; // rv 0 + assign UBDO_in[10] = (UBDO[10] !== 1'bz) && UBDO_delay[10]; // rv 0 + assign UBDO_in[11] = (UBDO[11] !== 1'bz) && UBDO_delay[11]; // rv 0 + assign UBDO_in[12] = (UBDO[12] !== 1'bz) && UBDO_delay[12]; // rv 0 + assign UBDO_in[13] = (UBDO[13] !== 1'bz) && UBDO_delay[13]; // rv 0 + assign UBDO_in[14] = (UBDO[14] !== 1'bz) && UBDO_delay[14]; // rv 0 + assign UBDO_in[15] = (UBDO[15] !== 1'bz) && UBDO_delay[15]; // rv 0 + assign UBDO_in[1] = (UBDO[1] !== 1'bz) && UBDO_delay[1]; // rv 0 + assign UBDO_in[2] = (UBDO[2] !== 1'bz) && UBDO_delay[2]; // rv 0 + assign UBDO_in[3] = (UBDO[3] !== 1'bz) && UBDO_delay[3]; // rv 0 + assign UBDO_in[4] = (UBDO[4] !== 1'bz) && UBDO_delay[4]; // rv 0 + assign UBDO_in[5] = (UBDO[5] !== 1'bz) && UBDO_delay[5]; // rv 0 + assign UBDO_in[6] = (UBDO[6] !== 1'bz) && UBDO_delay[6]; // rv 0 + assign UBDO_in[7] = (UBDO[7] !== 1'bz) && UBDO_delay[7]; // rv 0 + assign UBDO_in[8] = (UBDO[8] !== 1'bz) && UBDO_delay[8]; // rv 0 + assign UBDO_in[9] = (UBDO[9] !== 1'bz) && UBDO_delay[9]; // rv 0 + assign UBDRDY_in = (UBDRDY !== 1'bz) && UBDRDY_delay; // rv 0 +`else + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[10] = (DRPADDR[10] !== 1'bz) && DRPADDR[10]; // rv 0 + assign DRPADDR_in[11] = (DRPADDR[11] !== 1'bz) && DRPADDR[11]; // rv 0 + assign DRPADDR_in[12] = (DRPADDR[12] !== 1'bz) && DRPADDR[12]; // rv 0 + assign DRPADDR_in[13] = (DRPADDR[13] !== 1'bz) && DRPADDR[13]; // rv 0 + assign DRPADDR_in[14] = (DRPADDR[14] !== 1'bz) && DRPADDR[14]; // rv 0 + assign DRPADDR_in[15] = (DRPADDR[15] !== 1'bz) && DRPADDR[15]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign UBDO_in[0] = (UBDO[0] !== 1'bz) && UBDO[0]; // rv 0 + assign UBDO_in[10] = (UBDO[10] !== 1'bz) && UBDO[10]; // rv 0 + assign UBDO_in[11] = (UBDO[11] !== 1'bz) && UBDO[11]; // rv 0 + assign UBDO_in[12] = (UBDO[12] !== 1'bz) && UBDO[12]; // rv 0 + assign UBDO_in[13] = (UBDO[13] !== 1'bz) && UBDO[13]; // rv 0 + assign UBDO_in[14] = (UBDO[14] !== 1'bz) && UBDO[14]; // rv 0 + assign UBDO_in[15] = (UBDO[15] !== 1'bz) && UBDO[15]; // rv 0 + assign UBDO_in[1] = (UBDO[1] !== 1'bz) && UBDO[1]; // rv 0 + assign UBDO_in[2] = (UBDO[2] !== 1'bz) && UBDO[2]; // rv 0 + assign UBDO_in[3] = (UBDO[3] !== 1'bz) && UBDO[3]; // rv 0 + assign UBDO_in[4] = (UBDO[4] !== 1'bz) && UBDO[4]; // rv 0 + assign UBDO_in[5] = (UBDO[5] !== 1'bz) && UBDO[5]; // rv 0 + assign UBDO_in[6] = (UBDO[6] !== 1'bz) && UBDO[6]; // rv 0 + assign UBDO_in[7] = (UBDO[7] !== 1'bz) && UBDO[7]; // rv 0 + assign UBDO_in[8] = (UBDO[8] !== 1'bz) && UBDO[8]; // rv 0 + assign UBDO_in[9] = (UBDO[9] !== 1'bz) && UBDO[9]; // rv 0 + assign UBDRDY_in = (UBDRDY !== 1'bz) && UBDRDY; // rv 0 +`endif + + assign BGBYPASSB_in = BGBYPASSB; + assign BGMONITORENB_in = BGMONITORENB; + assign BGPDB_in = BGPDB; + assign BGRCALOVRDENB_in = (BGRCALOVRDENB === 1'bz) || BGRCALOVRDENB; // rv 1 + assign BGRCALOVRD_in = BGRCALOVRD; + assign GTGREFCLK0_in = GTGREFCLK0; + assign GTGREFCLK1_in = GTGREFCLK1; + assign GTNORTHREFCLK00_in = GTNORTHREFCLK00; + assign GTNORTHREFCLK01_in = GTNORTHREFCLK01; + assign GTNORTHREFCLK10_in = GTNORTHREFCLK10; + assign GTNORTHREFCLK11_in = GTNORTHREFCLK11; + assign GTREFCLK00_in = GTREFCLK00; + assign GTREFCLK01_in = GTREFCLK01; + assign GTREFCLK10_in = GTREFCLK10; + assign GTREFCLK11_in = GTREFCLK11; + assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00; + assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01; + assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10; + assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11; + assign PCIERATEQPLL0_in[0] = (PCIERATEQPLL0[0] !== 1'bz) && PCIERATEQPLL0[0]; // rv 0 + assign PCIERATEQPLL0_in[1] = (PCIERATEQPLL0[1] !== 1'bz) && PCIERATEQPLL0[1]; // rv 0 + assign PCIERATEQPLL0_in[2] = (PCIERATEQPLL0[2] !== 1'bz) && PCIERATEQPLL0[2]; // rv 0 + assign PCIERATEQPLL1_in[0] = (PCIERATEQPLL1[0] !== 1'bz) && PCIERATEQPLL1[0]; // rv 0 + assign PCIERATEQPLL1_in[1] = (PCIERATEQPLL1[1] !== 1'bz) && PCIERATEQPLL1[1]; // rv 0 + assign PCIERATEQPLL1_in[2] = (PCIERATEQPLL1[2] !== 1'bz) && PCIERATEQPLL1[2]; // rv 0 + assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0[0]; // rv 0 + assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0[1]; // rv 0 + assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0[2]; // rv 0 + assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0[3]; // rv 0 + assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0[4]; // rv 0 + assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0[5]; // rv 0 + assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0[6]; // rv 0 + assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0[7]; // rv 0 + assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1[0]; // rv 0 + assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1[1]; // rv 0 + assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1[2]; // rv 0 + assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1[3]; // rv 0 + assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1[4]; // rv 0 + assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1[5]; // rv 0 + assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1[6]; // rv 0 + assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1[7]; // rv 0 + assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 !== 1'bz) && QPLL0CLKRSVD0; // rv 0 + assign QPLL0CLKRSVD1_in = (QPLL0CLKRSVD1 !== 1'bz) && QPLL0CLKRSVD1; // rv 0 + assign QPLL0FBDIV_in[0] = (QPLL0FBDIV[0] !== 1'bz) && QPLL0FBDIV[0]; // rv 0 + assign QPLL0FBDIV_in[1] = (QPLL0FBDIV[1] !== 1'bz) && QPLL0FBDIV[1]; // rv 0 + assign QPLL0FBDIV_in[2] = (QPLL0FBDIV[2] !== 1'bz) && QPLL0FBDIV[2]; // rv 0 + assign QPLL0FBDIV_in[3] = (QPLL0FBDIV[3] !== 1'bz) && QPLL0FBDIV[3]; // rv 0 + assign QPLL0FBDIV_in[4] = (QPLL0FBDIV[4] !== 1'bz) && QPLL0FBDIV[4]; // rv 0 + assign QPLL0FBDIV_in[5] = (QPLL0FBDIV[5] !== 1'bz) && QPLL0FBDIV[5]; // rv 0 + assign QPLL0FBDIV_in[6] = (QPLL0FBDIV[6] !== 1'bz) && QPLL0FBDIV[6]; // rv 0 + assign QPLL0FBDIV_in[7] = (QPLL0FBDIV[7] !== 1'bz) && QPLL0FBDIV[7]; // rv 0 + assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK !== 1'bz) && QPLL0LOCKDETCLK; // rv 0 + assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN; // rv 0 + assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD; // rv 0 + assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL[0]; // rv 1 + assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL[1]; // rv 0 + assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL[2]; // rv 0 + assign QPLL0RESET_in = (QPLL0RESET === 1'bz) || QPLL0RESET; // rv 1 + assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 !== 1'bz) && QPLL1CLKRSVD0; // rv 0 + assign QPLL1CLKRSVD1_in = (QPLL1CLKRSVD1 !== 1'bz) && QPLL1CLKRSVD1; // rv 0 + assign QPLL1FBDIV_in[0] = (QPLL1FBDIV[0] !== 1'bz) && QPLL1FBDIV[0]; // rv 0 + assign QPLL1FBDIV_in[1] = (QPLL1FBDIV[1] !== 1'bz) && QPLL1FBDIV[1]; // rv 0 + assign QPLL1FBDIV_in[2] = (QPLL1FBDIV[2] !== 1'bz) && QPLL1FBDIV[2]; // rv 0 + assign QPLL1FBDIV_in[3] = (QPLL1FBDIV[3] !== 1'bz) && QPLL1FBDIV[3]; // rv 0 + assign QPLL1FBDIV_in[4] = (QPLL1FBDIV[4] !== 1'bz) && QPLL1FBDIV[4]; // rv 0 + assign QPLL1FBDIV_in[5] = (QPLL1FBDIV[5] !== 1'bz) && QPLL1FBDIV[5]; // rv 0 + assign QPLL1FBDIV_in[6] = (QPLL1FBDIV[6] !== 1'bz) && QPLL1FBDIV[6]; // rv 0 + assign QPLL1FBDIV_in[7] = (QPLL1FBDIV[7] !== 1'bz) && QPLL1FBDIV[7]; // rv 0 + assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK !== 1'bz) && QPLL1LOCKDETCLK; // rv 0 + assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN; // rv 0 + assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD; // rv 0 + assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL[0]; // rv 1 + assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL[1]; // rv 0 + assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL[2]; // rv 0 + assign QPLL1RESET_in = (QPLL1RESET === 1'bz) || QPLL1RESET; // rv 1 + assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1[0]; // rv 0 + assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1[1]; // rv 0 + assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1[2]; // rv 0 + assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1[3]; // rv 0 + assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1[4]; // rv 0 + assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1[5]; // rv 0 + assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1[6]; // rv 0 + assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1[7]; // rv 0 + assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2[0]; // rv 0 + assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2[1]; // rv 0 + assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2[2]; // rv 0 + assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2[3]; // rv 0 + assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2[4]; // rv 0 + assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3[0]; // rv 0 + assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3[1]; // rv 0 + assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3[2]; // rv 0 + assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3[3]; // rv 0 + assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3[4]; // rv 0 + assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4[0]; // rv 0 + assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4[1]; // rv 0 + assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4[2]; // rv 0 + assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4[3]; // rv 0 + assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4[4]; // rv 0 + assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4[5]; // rv 0 + assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4[6]; // rv 0 + assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4[7]; // rv 0 + assign RCALENB_in = RCALENB; + assign SDM0DATA_in[0] = (SDM0DATA[0] !== 1'bz) && SDM0DATA[0]; // rv 0 + assign SDM0DATA_in[10] = (SDM0DATA[10] !== 1'bz) && SDM0DATA[10]; // rv 0 + assign SDM0DATA_in[11] = (SDM0DATA[11] !== 1'bz) && SDM0DATA[11]; // rv 0 + assign SDM0DATA_in[12] = (SDM0DATA[12] !== 1'bz) && SDM0DATA[12]; // rv 0 + assign SDM0DATA_in[13] = (SDM0DATA[13] !== 1'bz) && SDM0DATA[13]; // rv 0 + assign SDM0DATA_in[14] = (SDM0DATA[14] !== 1'bz) && SDM0DATA[14]; // rv 0 + assign SDM0DATA_in[15] = (SDM0DATA[15] !== 1'bz) && SDM0DATA[15]; // rv 0 + assign SDM0DATA_in[16] = (SDM0DATA[16] !== 1'bz) && SDM0DATA[16]; // rv 0 + assign SDM0DATA_in[17] = (SDM0DATA[17] !== 1'bz) && SDM0DATA[17]; // rv 0 + assign SDM0DATA_in[18] = (SDM0DATA[18] !== 1'bz) && SDM0DATA[18]; // rv 0 + assign SDM0DATA_in[19] = (SDM0DATA[19] !== 1'bz) && SDM0DATA[19]; // rv 0 + assign SDM0DATA_in[1] = (SDM0DATA[1] !== 1'bz) && SDM0DATA[1]; // rv 0 + assign SDM0DATA_in[20] = (SDM0DATA[20] !== 1'bz) && SDM0DATA[20]; // rv 0 + assign SDM0DATA_in[21] = (SDM0DATA[21] !== 1'bz) && SDM0DATA[21]; // rv 0 + assign SDM0DATA_in[22] = (SDM0DATA[22] !== 1'bz) && SDM0DATA[22]; // rv 0 + assign SDM0DATA_in[23] = (SDM0DATA[23] !== 1'bz) && SDM0DATA[23]; // rv 0 + assign SDM0DATA_in[24] = (SDM0DATA[24] !== 1'bz) && SDM0DATA[24]; // rv 0 + assign SDM0DATA_in[2] = (SDM0DATA[2] !== 1'bz) && SDM0DATA[2]; // rv 0 + assign SDM0DATA_in[3] = (SDM0DATA[3] !== 1'bz) && SDM0DATA[3]; // rv 0 + assign SDM0DATA_in[4] = (SDM0DATA[4] !== 1'bz) && SDM0DATA[4]; // rv 0 + assign SDM0DATA_in[5] = (SDM0DATA[5] !== 1'bz) && SDM0DATA[5]; // rv 0 + assign SDM0DATA_in[6] = (SDM0DATA[6] !== 1'bz) && SDM0DATA[6]; // rv 0 + assign SDM0DATA_in[7] = (SDM0DATA[7] !== 1'bz) && SDM0DATA[7]; // rv 0 + assign SDM0DATA_in[8] = (SDM0DATA[8] !== 1'bz) && SDM0DATA[8]; // rv 0 + assign SDM0DATA_in[9] = (SDM0DATA[9] !== 1'bz) && SDM0DATA[9]; // rv 0 + assign SDM0RESET_in = (SDM0RESET === 1'bz) || SDM0RESET; // rv 1 + assign SDM0TOGGLE_in = (SDM0TOGGLE !== 1'bz) && SDM0TOGGLE; // rv 0 + assign SDM0WIDTH_in[0] = (SDM0WIDTH[0] !== 1'bz) && SDM0WIDTH[0]; // rv 0 + assign SDM0WIDTH_in[1] = (SDM0WIDTH[1] !== 1'bz) && SDM0WIDTH[1]; // rv 0 + assign SDM1DATA_in[0] = (SDM1DATA[0] !== 1'bz) && SDM1DATA[0]; // rv 0 + assign SDM1DATA_in[10] = (SDM1DATA[10] !== 1'bz) && SDM1DATA[10]; // rv 0 + assign SDM1DATA_in[11] = (SDM1DATA[11] !== 1'bz) && SDM1DATA[11]; // rv 0 + assign SDM1DATA_in[12] = (SDM1DATA[12] !== 1'bz) && SDM1DATA[12]; // rv 0 + assign SDM1DATA_in[13] = (SDM1DATA[13] !== 1'bz) && SDM1DATA[13]; // rv 0 + assign SDM1DATA_in[14] = (SDM1DATA[14] !== 1'bz) && SDM1DATA[14]; // rv 0 + assign SDM1DATA_in[15] = (SDM1DATA[15] !== 1'bz) && SDM1DATA[15]; // rv 0 + assign SDM1DATA_in[16] = (SDM1DATA[16] !== 1'bz) && SDM1DATA[16]; // rv 0 + assign SDM1DATA_in[17] = (SDM1DATA[17] !== 1'bz) && SDM1DATA[17]; // rv 0 + assign SDM1DATA_in[18] = (SDM1DATA[18] !== 1'bz) && SDM1DATA[18]; // rv 0 + assign SDM1DATA_in[19] = (SDM1DATA[19] !== 1'bz) && SDM1DATA[19]; // rv 0 + assign SDM1DATA_in[1] = (SDM1DATA[1] !== 1'bz) && SDM1DATA[1]; // rv 0 + assign SDM1DATA_in[20] = (SDM1DATA[20] !== 1'bz) && SDM1DATA[20]; // rv 0 + assign SDM1DATA_in[21] = (SDM1DATA[21] !== 1'bz) && SDM1DATA[21]; // rv 0 + assign SDM1DATA_in[22] = (SDM1DATA[22] !== 1'bz) && SDM1DATA[22]; // rv 0 + assign SDM1DATA_in[23] = (SDM1DATA[23] !== 1'bz) && SDM1DATA[23]; // rv 0 + assign SDM1DATA_in[24] = (SDM1DATA[24] !== 1'bz) && SDM1DATA[24]; // rv 0 + assign SDM1DATA_in[2] = (SDM1DATA[2] !== 1'bz) && SDM1DATA[2]; // rv 0 + assign SDM1DATA_in[3] = (SDM1DATA[3] !== 1'bz) && SDM1DATA[3]; // rv 0 + assign SDM1DATA_in[4] = (SDM1DATA[4] !== 1'bz) && SDM1DATA[4]; // rv 0 + assign SDM1DATA_in[5] = (SDM1DATA[5] !== 1'bz) && SDM1DATA[5]; // rv 0 + assign SDM1DATA_in[6] = (SDM1DATA[6] !== 1'bz) && SDM1DATA[6]; // rv 0 + assign SDM1DATA_in[7] = (SDM1DATA[7] !== 1'bz) && SDM1DATA[7]; // rv 0 + assign SDM1DATA_in[8] = (SDM1DATA[8] !== 1'bz) && SDM1DATA[8]; // rv 0 + assign SDM1DATA_in[9] = (SDM1DATA[9] !== 1'bz) && SDM1DATA[9]; // rv 0 + assign SDM1RESET_in = (SDM1RESET === 1'bz) || SDM1RESET; // rv 1 + assign SDM1TOGGLE_in = (SDM1TOGGLE !== 1'bz) && SDM1TOGGLE; // rv 0 + assign SDM1WIDTH_in[0] = (SDM1WIDTH[0] !== 1'bz) && SDM1WIDTH[0]; // rv 0 + assign SDM1WIDTH_in[1] = (SDM1WIDTH[1] !== 1'bz) && SDM1WIDTH[1]; // rv 0 + assign UBCFGSTREAMEN_in = (UBCFGSTREAMEN !== 1'bz) && UBCFGSTREAMEN; // rv 0 + assign UBENABLE_in = (UBENABLE !== 1'bz) && UBENABLE; // rv 0 + assign UBGPI_in[0] = (UBGPI[0] !== 1'bz) && UBGPI[0]; // rv 0 + assign UBGPI_in[1] = (UBGPI[1] !== 1'bz) && UBGPI[1]; // rv 0 + assign UBINTR_in[0] = (UBINTR[0] !== 1'bz) && UBINTR[0]; // rv 0 + assign UBINTR_in[1] = (UBINTR[1] !== 1'bz) && UBINTR[1]; // rv 0 + assign UBIOLMBRST_in = (UBIOLMBRST === 1'bz) || UBIOLMBRST; // rv 1 + assign UBMBRST_in = (UBMBRST === 1'bz) || UBMBRST; // rv 1 + assign UBMDMCAPTURE_in = (UBMDMCAPTURE !== 1'bz) && UBMDMCAPTURE; // rv 0 + assign UBMDMDBGRST_in = (UBMDMDBGRST !== 1'bz) && UBMDMDBGRST; // rv 0 + assign UBMDMDBGUPDATE_in = (UBMDMDBGUPDATE !== 1'bz) && UBMDMDBGUPDATE; // rv 0 + assign UBMDMREGEN_in[0] = (UBMDMREGEN[0] !== 1'bz) && UBMDMREGEN[0]; // rv 0 + assign UBMDMREGEN_in[1] = (UBMDMREGEN[1] !== 1'bz) && UBMDMREGEN[1]; // rv 0 + assign UBMDMREGEN_in[2] = (UBMDMREGEN[2] !== 1'bz) && UBMDMREGEN[2]; // rv 0 + assign UBMDMREGEN_in[3] = (UBMDMREGEN[3] !== 1'bz) && UBMDMREGEN[3]; // rv 0 + assign UBMDMSHIFT_in = (UBMDMSHIFT !== 1'bz) && UBMDMSHIFT; // rv 0 + assign UBMDMSYSRST_in = (UBMDMSYSRST !== 1'bz) && UBMDMSYSRST; // rv 0 + assign UBMDMTCK_in = (UBMDMTCK !== 1'bz) && UBMDMTCK; // rv 0 + assign UBMDMTDI_in = (UBMDMTDI !== 1'bz) && UBMDMTDI; // rv 0 + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((QPLL0CLKOUT_RATE_REG != "FULL") && + (QPLL0CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-158] QPLL0CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL0CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-169] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-170] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL0_REFCLK_DIV_REG != 1) && + (QPLL0_REFCLK_DIV_REG != 2) && + (QPLL0_REFCLK_DIV_REG != 3) && + (QPLL0_REFCLK_DIV_REG != 4) && + (QPLL0_REFCLK_DIV_REG != 5) && + (QPLL0_REFCLK_DIV_REG != 6) && + (QPLL0_REFCLK_DIV_REG != 8) && + (QPLL0_REFCLK_DIV_REG != 10) && + (QPLL0_REFCLK_DIV_REG != 12) && + (QPLL0_REFCLK_DIV_REG != 16) && + (QPLL0_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-179] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1CLKOUT_RATE_REG != "FULL") && + (QPLL1CLKOUT_RATE_REG != "HALF"))) begin + $display("Error: [Unisim %s-183] QPLL1CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL1CLKOUT_RATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin + $display("Error: [Unisim %s-194] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin + $display("Error: [Unisim %s-195] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((QPLL1_REFCLK_DIV_REG != 1) && + (QPLL1_REFCLK_DIV_REG != 2) && + (QPLL1_REFCLK_DIV_REG != 3) && + (QPLL1_REFCLK_DIV_REG != 4) && + (QPLL1_REFCLK_DIV_REG != 5) && + (QPLL1_REFCLK_DIV_REG != 6) && + (QPLL1_REFCLK_DIV_REG != 8) && + (QPLL1_REFCLK_DIV_REG != 10) && + (QPLL1_REFCLK_DIV_REG != 12) && + (QPLL1_REFCLK_DIV_REG != 16) && + (QPLL1_REFCLK_DIV_REG != 20))) begin + $display("Error: [Unisim %s-204] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-228] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_MODE_REG != "FAST") && + (SIM_MODE_REG != "LEGACY"))) begin + $display("Error: [Unisim %s-229] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_RESET_SPEEDUP_REG != "TRUE") && + (SIM_RESET_SPEEDUP_REG != "FALSE"))) begin + $display("Error: [Unisim %s-230] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +assign PMASCANCLK_in = 14'b11111111111111; // tie off + +assign CSSDSTOPCLK0_in = 1'b1; // tie off +assign CSSDSTOPCLK1_in = 1'b1; // tie off +assign PMASCANENB_in = 1'b1; // tie off +assign PMASCANIN_in = 14'b11111111111111; // tie off +assign QDPMASCANMODEB_in = 1'b1; // tie off +assign QDPMASCANRSTEN_in = 1'b1; // tie off +assign RXRECCLK_in = 4'b1111; // tie off + +SIP_GTYE4_COMMON SIP_GTYE4_COMMON_INST ( + .AEN_BGBS0 (AEN_BGBS0_REG), + .AEN_BGBS1 (AEN_BGBS1_REG), + .AEN_MASTER0 (AEN_MASTER0_REG), + .AEN_MASTER1 (AEN_MASTER1_REG), + .AEN_PD0 (AEN_PD0_REG), + .AEN_PD1 (AEN_PD1_REG), + .AEN_QPLL0 (AEN_QPLL0_REG), + .AEN_QPLL0_FBDIV (AEN_QPLL0_FBDIV_REG), + .AEN_QPLL1 (AEN_QPLL1_REG), + .AEN_QPLL1_FBDIV (AEN_QPLL1_FBDIV_REG), + .AEN_REFCLK0 (AEN_REFCLK0_REG), + .AEN_REFCLK1 (AEN_REFCLK1_REG), + .AEN_RESET0 (AEN_RESET0_REG), + .AEN_RESET1 (AEN_RESET1_REG), + .AEN_SDM0DATA (AEN_SDM0DATA_REG), + .AEN_SDM0RESET (AEN_SDM0RESET_REG), + .AEN_SDM0TOGGLE (AEN_SDM0TOGGLE_REG), + .AEN_SDM0WIDTH (AEN_SDM0WIDTH_REG), + .AEN_SDM1DATA (AEN_SDM1DATA_REG), + .AEN_SDM1RESET (AEN_SDM1RESET_REG), + .AEN_SDM1TOGGLE (AEN_SDM1TOGGLE_REG), + .AEN_SDM1WIDTH (AEN_SDM1WIDTH_REG), + .AQDMUXSEL1 (AQDMUXSEL1_REG), + .AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG), + .AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG), + .A_BGMONITOREN (A_BGMONITOREN_REG), + .A_BGPD (A_BGPD_REG), + .A_GTREFCLKPD0 (A_GTREFCLKPD0_REG), + .A_GTREFCLKPD1 (A_GTREFCLKPD1_REG), + .A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG), + .A_QPLL0PD (A_QPLL0PD_REG), + .A_QPLL0RESET (A_QPLL0RESET_REG), + .A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG), + .A_QPLL1PD (A_QPLL1PD_REG), + .A_QPLL1RESET (A_QPLL1RESET_REG), + .A_SDM0DATA_HIGH (A_SDM0DATA_HIGH_REG), + .A_SDM0DATA_LOW (A_SDM0DATA_LOW_REG), + .A_SDM0RESET (A_SDM0RESET_REG), + .A_SDM0TOGGLE (A_SDM0TOGGLE_REG), + .A_SDM1DATA_HIGH (A_SDM1DATA_HIGH_REG), + .A_SDM1DATA_LOW (A_SDM1DATA_LOW_REG), + .A_SDM1RESET (A_SDM1RESET_REG), + .A_SDM1TOGGLE (A_SDM1TOGGLE_REG), + .BIAS_CFG0 (BIAS_CFG0_REG), + .BIAS_CFG1 (BIAS_CFG1_REG), + .BIAS_CFG2 (BIAS_CFG2_REG), + .BIAS_CFG3 (BIAS_CFG3_REG), + .BIAS_CFG4 (BIAS_CFG4_REG), + .BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG), + .COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG), + .COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG), + .COMMON_CFG0 (COMMON_CFG0_REG), + .COMMON_CFG1 (COMMON_CFG1_REG), + .COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG), + .POR_CFG (POR_CFG_REG), + .PPF0_CFG (PPF0_CFG_REG), + .PPF1_CFG (PPF1_CFG_REG), + .QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG), + .QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG), + .QPLL0_CFG0 (QPLL0_CFG0_REG), + .QPLL0_CFG1 (QPLL0_CFG1_REG), + .QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG), + .QPLL0_CFG2 (QPLL0_CFG2_REG), + .QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG), + .QPLL0_CFG3 (QPLL0_CFG3_REG), + .QPLL0_CFG4 (QPLL0_CFG4_REG), + .QPLL0_CP (QPLL0_CP_REG), + .QPLL0_CP_G3 (QPLL0_CP_G3_REG), + .QPLL0_FBDIV (QPLL0_FBDIV_REG), + .QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG), + .QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG), + .QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG), + .QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG), + .QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG), + .QPLL0_LPF (QPLL0_LPF_REG), + .QPLL0_LPF_G3 (QPLL0_LPF_G3_REG), + .QPLL0_PCI_EN (QPLL0_PCI_EN_REG), + .QPLL0_RATE_SW_USE_DRP (QPLL0_RATE_SW_USE_DRP_REG), + .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG), + .QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG), + .QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG), + .QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG), + .QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG), + .QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG), + .QPLL1_CFG0 (QPLL1_CFG0_REG), + .QPLL1_CFG1 (QPLL1_CFG1_REG), + .QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG), + .QPLL1_CFG2 (QPLL1_CFG2_REG), + .QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG), + .QPLL1_CFG3 (QPLL1_CFG3_REG), + .QPLL1_CFG4 (QPLL1_CFG4_REG), + .QPLL1_CP (QPLL1_CP_REG), + .QPLL1_CP_G3 (QPLL1_CP_G3_REG), + .QPLL1_FBDIV (QPLL1_FBDIV_REG), + .QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG), + .QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG), + .QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG), + .QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG), + .QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG), + .QPLL1_LPF (QPLL1_LPF_REG), + .QPLL1_LPF_G3 (QPLL1_LPF_G3_REG), + .QPLL1_PCI_EN (QPLL1_PCI_EN_REG), + .QPLL1_RATE_SW_USE_DRP (QPLL1_RATE_SW_USE_DRP_REG), + .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG), + .QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG), + .QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG), + .QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG), + .RCALSAP_TESTEN (RCALSAP_TESTEN_REG), + .RCAL_APROBE (RCAL_APROBE_REG), + .REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG), + .REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG), + .REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG), + .REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG), + .REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG), + .REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG), + .RSVD_ATTR0 (RSVD_ATTR0_REG), + .RSVD_ATTR1 (RSVD_ATTR1_REG), + .RSVD_ATTR2 (RSVD_ATTR2_REG), + .RSVD_ATTR3 (RSVD_ATTR3_REG), + .RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG), + .RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG), + .SARC_ENB (SARC_ENB_REG), + .SARC_SEL (SARC_SEL_REG), + .SDM0INITSEED0_0 (SDM0INITSEED0_0_REG), + .SDM0INITSEED0_1 (SDM0INITSEED0_1_REG), + .SDM1INITSEED0_0 (SDM1INITSEED0_0_REG), + .SDM1INITSEED0_1 (SDM1INITSEED0_1_REG), + .SIM_DEVICE (SIM_DEVICE_REG), + .SIM_MODE (SIM_MODE_REG), + .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG), + .UB_CFG0 (UB_CFG0_REG), + .UB_CFG1 (UB_CFG1_REG), + .UB_CFG2 (UB_CFG2_REG), + .UB_CFG3 (UB_CFG3_REG), + .UB_CFG4 (UB_CFG4_REG), + .UB_CFG5 (UB_CFG5_REG), + .UB_CFG6 (UB_CFG6_REG), + .VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG), + .CSSDSTOPCLKDONE0 (CSSDSTOPCLKDONE0_out), + .CSSDSTOPCLKDONE1 (CSSDSTOPCLKDONE1_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .PMARSVDOUT0 (PMARSVDOUT0_out), + .PMARSVDOUT1 (PMARSVDOUT1_out), + .PMASCANOUT (PMASCANOUT_out), + .QPLL0FBCLKLOST (QPLL0FBCLKLOST_out), + .QPLL0LOCK (QPLL0LOCK_out), + .QPLL0OUTCLK (QPLL0OUTCLK_out), + .QPLL0OUTREFCLK (QPLL0OUTREFCLK_out), + .QPLL0REFCLKLOST (QPLL0REFCLKLOST_out), + .QPLL1FBCLKLOST (QPLL1FBCLKLOST_out), + .QPLL1LOCK (QPLL1LOCK_out), + .QPLL1OUTCLK (QPLL1OUTCLK_out), + .QPLL1OUTREFCLK (QPLL1OUTREFCLK_out), + .QPLL1REFCLKLOST (QPLL1REFCLKLOST_out), + .QPLLDMONITOR0 (QPLLDMONITOR0_out), + .QPLLDMONITOR1 (QPLLDMONITOR1_out), + .REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out), + .REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out), + .RXRECCLK0SEL (RXRECCLK0SEL_out), + .RXRECCLK1SEL (RXRECCLK1SEL_out), + .SARCCLK (SARCCLK_out), + .SDM0FINALOUT (SDM0FINALOUT_out), + .SDM0TESTDATA (SDM0TESTDATA_out), + .SDM1FINALOUT (SDM1FINALOUT_out), + .SDM1TESTDATA (SDM1TESTDATA_out), + .UBDADDR (UBDADDR_out), + .UBDEN (UBDEN_out), + .UBDI (UBDI_out), + .UBDWE (UBDWE_out), + .UBMDMTDO (UBMDMTDO_out), + .UBRSVDOUT (UBRSVDOUT_out), + .UBTXUART (UBTXUART_out), + .BGBYPASSB (BGBYPASSB_in), + .BGMONITORENB (BGMONITORENB_in), + .BGPDB (BGPDB_in), + .BGRCALOVRD (BGRCALOVRD_in), + .BGRCALOVRDENB (BGRCALOVRDENB_in), + .CSSDSTOPCLK0 (CSSDSTOPCLK0_in), + .CSSDSTOPCLK1 (CSSDSTOPCLK1_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .GTGREFCLK0 (GTGREFCLK0_in), + .GTGREFCLK1 (GTGREFCLK1_in), + .GTNORTHREFCLK00 (GTNORTHREFCLK00_in), + .GTNORTHREFCLK01 (GTNORTHREFCLK01_in), + .GTNORTHREFCLK10 (GTNORTHREFCLK10_in), + .GTNORTHREFCLK11 (GTNORTHREFCLK11_in), + .GTREFCLK00 (GTREFCLK00_in), + .GTREFCLK01 (GTREFCLK01_in), + .GTREFCLK10 (GTREFCLK10_in), + .GTREFCLK11 (GTREFCLK11_in), + .GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in), + .GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in), + .GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in), + .GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in), + .PCIERATEQPLL0 (PCIERATEQPLL0_in), + .PCIERATEQPLL1 (PCIERATEQPLL1_in), + .PMARSVD0 (PMARSVD0_in), + .PMARSVD1 (PMARSVD1_in), + .PMASCANCLK (PMASCANCLK_in), + .PMASCANENB (PMASCANENB_in), + .PMASCANIN (PMASCANIN_in), + .QDPMASCANMODEB (QDPMASCANMODEB_in), + .QDPMASCANRSTEN (QDPMASCANRSTEN_in), + .QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in), + .QPLL0CLKRSVD1 (QPLL0CLKRSVD1_in), + .QPLL0FBDIV (QPLL0FBDIV_in), + .QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in), + .QPLL0LOCKEN (QPLL0LOCKEN_in), + .QPLL0PD (QPLL0PD_in), + .QPLL0REFCLKSEL (QPLL0REFCLKSEL_in), + .QPLL0RESET (QPLL0RESET_in), + .QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in), + .QPLL1CLKRSVD1 (QPLL1CLKRSVD1_in), + .QPLL1FBDIV (QPLL1FBDIV_in), + .QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in), + .QPLL1LOCKEN (QPLL1LOCKEN_in), + .QPLL1PD (QPLL1PD_in), + .QPLL1REFCLKSEL (QPLL1REFCLKSEL_in), + .QPLL1RESET (QPLL1RESET_in), + .QPLLRSVD1 (QPLLRSVD1_in), + .QPLLRSVD2 (QPLLRSVD2_in), + .QPLLRSVD3 (QPLLRSVD3_in), + .QPLLRSVD4 (QPLLRSVD4_in), + .RCALENB (RCALENB_in), + .RXRECCLK (RXRECCLK_in), + .SDM0DATA (SDM0DATA_in), + .SDM0RESET (SDM0RESET_in), + .SDM0TOGGLE (SDM0TOGGLE_in), + .SDM0WIDTH (SDM0WIDTH_in), + .SDM1DATA (SDM1DATA_in), + .SDM1RESET (SDM1RESET_in), + .SDM1TOGGLE (SDM1TOGGLE_in), + .SDM1WIDTH (SDM1WIDTH_in), + .UBCFGSTREAMEN (UBCFGSTREAMEN_in), + .UBDO (UBDO_in), + .UBDRDY (UBDRDY_in), + .UBENABLE (UBENABLE_in), + .UBGPI (UBGPI_in), + .UBINTR (UBINTR_in), + .UBIOLMBRST (UBIOLMBRST_in), + .UBMBRST (UBMBRST_in), + .UBMDMCAPTURE (UBMDMCAPTURE_in), + .UBMDMDBGRST (UBMDMDBGRST_in), + .UBMDMDBGUPDATE (UBMDMDBGUPDATE_in), + .UBMDMREGEN (UBMDMREGEN_in), + .UBMDMSHIFT (UBMDMSHIFT_in), + .UBMDMSYSRST (UBMDMSYSRST_in), + .UBMDMTCK (UBMDMTCK_in), + .UBMDMTDI (UBMDMTDI_in), + .GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[0]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[10]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[11]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[12]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[13]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[14]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[15]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[1]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[2]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[3]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[4]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[5]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[6]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[7]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[8]) = (100:100:100, 100:100:100); + (DRPCLK => UBDADDR[9]) = (100:100:100, 100:100:100); + (DRPCLK => UBDEN) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[0]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[10]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[11]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[12]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[13]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[14]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[15]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[1]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[2]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[3]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[4]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[5]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[6]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[7]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[8]) = (100:100:100, 100:100:100); + (DRPCLK => UBDI[9]) = (100:100:100, 100:100:100); + (DRPCLK => UBDWE) = (100:100:100, 100:100:100); + (GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0); + (GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0); + // (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output + // (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge DRPCLK, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPADDR[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPADDR[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPADDR[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, negedge UBDO[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[0]); + $setuphold (posedge DRPCLK, negedge UBDO[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[10]); + $setuphold (posedge DRPCLK, negedge UBDO[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[11]); + $setuphold (posedge DRPCLK, negedge UBDO[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[12]); + $setuphold (posedge DRPCLK, negedge UBDO[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[13]); + $setuphold (posedge DRPCLK, negedge UBDO[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[14]); + $setuphold (posedge DRPCLK, negedge UBDO[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[15]); + $setuphold (posedge DRPCLK, negedge UBDO[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[1]); + $setuphold (posedge DRPCLK, negedge UBDO[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[2]); + $setuphold (posedge DRPCLK, negedge UBDO[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[3]); + $setuphold (posedge DRPCLK, negedge UBDO[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[4]); + $setuphold (posedge DRPCLK, negedge UBDO[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[5]); + $setuphold (posedge DRPCLK, negedge UBDO[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[6]); + $setuphold (posedge DRPCLK, negedge UBDO[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[7]); + $setuphold (posedge DRPCLK, negedge UBDO[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[8]); + $setuphold (posedge DRPCLK, negedge UBDO[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[9]); + $setuphold (posedge DRPCLK, negedge UBDRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDRDY_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPADDR[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPADDR[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPADDR[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge UBDO[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[0]); + $setuphold (posedge DRPCLK, posedge UBDO[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[10]); + $setuphold (posedge DRPCLK, posedge UBDO[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[11]); + $setuphold (posedge DRPCLK, posedge UBDO[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[12]); + $setuphold (posedge DRPCLK, posedge UBDO[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[13]); + $setuphold (posedge DRPCLK, posedge UBDO[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[14]); + $setuphold (posedge DRPCLK, posedge UBDO[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[15]); + $setuphold (posedge DRPCLK, posedge UBDO[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[1]); + $setuphold (posedge DRPCLK, posedge UBDO[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[2]); + $setuphold (posedge DRPCLK, posedge UBDO[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[3]); + $setuphold (posedge DRPCLK, posedge UBDO[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[4]); + $setuphold (posedge DRPCLK, posedge UBDO[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[5]); + $setuphold (posedge DRPCLK, posedge UBDO[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[6]); + $setuphold (posedge DRPCLK, posedge UBDO[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[7]); + $setuphold (posedge DRPCLK, posedge UBDO[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[8]); + $setuphold (posedge DRPCLK, posedge UBDO[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDO_delay[9]); + $setuphold (posedge DRPCLK, posedge UBDRDY, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, UBDRDY_delay); + $width (negedge DRPCLK, 0:0:0, 0, notifier); + $width (posedge DRPCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HARD_SYNC.v b/verilog/src/unisims/HARD_SYNC.v new file mode 100644 index 0000000..cf50f92 --- /dev/null +++ b/verilog/src/unisims/HARD_SYNC.v @@ -0,0 +1,177 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Metastability Hardened Registers +// /___/ /\ Filename : HARD_SYNC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 01/30/13 Initial version +// 05/08/13 712367 - fix blocking assignments +// 05/17/13 718960 - fix BIN encoding +// 05/17/13 719092 - remove SR, add IS_CLK_INVERTED +// 10/22/14 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HARD_SYNC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] INIT = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter integer LATENCY = 2 +)( + output DOUT, + + input CLK, + input DIN +); + +// define constants + localparam MODULE_NAME = "HARD_SYNC"; + +// Parameter encodings and registers + localparam LATENCY_2 = 0; + localparam LATENCY_3 = 1; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HARD_SYNC_dr.v" +`else + localparam [0:0] INIT_REG = INIT; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [1:0] LATENCY_REG = LATENCY; +`endif + + wire INIT_BIN; + wire IS_CLK_INVERTED_BIN; + wire LATENCY_BIN; + +`ifdef XIL_XECLIB + tri0 glblGSR = 1'b0; +`else + `ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; + `else + reg attr_test = 1'b0; + `endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_in; + wire DIN_in; + +`ifdef XIL_TIMING + wire CLK_delay; + wire DIN_delay; +`ifdef XIL_XECLIB + assign CLK_delay = CLK; + assign DIN_delay = DIN; +`endif +`endif + +`ifdef XIL_TIMING + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign DIN_in = DIN_delay; +`else + assign CLK_in = CLK ^ IS_CLK_INVERTED_BIN; + assign DIN_in = DIN; +`endif + + assign INIT_BIN = INIT_REG; + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign LATENCY_BIN = + (LATENCY_REG == 2) ? LATENCY_2 : + (LATENCY_REG == 3) ? LATENCY_3 : + LATENCY_2; + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((LATENCY_REG != 2) && + (LATENCY_REG != 3))) begin + $display("Error: [Unisim %s-103] LATENCY attribute is set to %d. Legal values for this attribute are 2 or 3. Instance: %m", MODULE_NAME, LATENCY_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +reg [2:0] DIN_reg; + +assign DOUT = (LATENCY_BIN == LATENCY_3) && DIN_reg[2] || (LATENCY_BIN == LATENCY_2) && DIN_reg[1]; + +always @ (posedge CLK_in or posedge glblGSR) begin + if (glblGSR == 1'b1) begin + DIN_reg <= {INIT_BIN, INIT_BIN, INIT_BIN}; + end + else begin + DIN_reg <= {DIN_reg[1:0], DIN_in}; + end + end + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; +`endif + + specify + (CLK => DOUT) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, CLK_delay, DIN_delay); + $setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, CLK_delay, DIN_delay); + $setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, CLK_delay, DIN_delay); + $setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, CLK_delay, DIN_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HBM_ONE_STACK_INTF.v b/verilog/src/unisims/HBM_ONE_STACK_INTF.v new file mode 100644 index 0000000..a42ab61 --- /dev/null +++ b/verilog/src/unisims/HBM_ONE_STACK_INTF.v @@ -0,0 +1,4518 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HBM_ONE_STACK_INTF +// /___/ /\ Filename : HBM_ONE_STACK_INTF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HBM_ONE_STACK_INTF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CLK_SEL_00 = "FALSE", + parameter CLK_SEL_01 = "FALSE", + parameter CLK_SEL_02 = "FALSE", + parameter CLK_SEL_03 = "FALSE", + parameter CLK_SEL_04 = "FALSE", + parameter CLK_SEL_05 = "FALSE", + parameter CLK_SEL_06 = "FALSE", + parameter CLK_SEL_07 = "FALSE", + parameter CLK_SEL_08 = "FALSE", + parameter CLK_SEL_09 = "FALSE", + parameter CLK_SEL_10 = "FALSE", + parameter CLK_SEL_11 = "FALSE", + parameter CLK_SEL_12 = "FALSE", + parameter CLK_SEL_13 = "FALSE", + parameter CLK_SEL_14 = "FALSE", + parameter CLK_SEL_15 = "FALSE", + parameter integer DATARATE_00 = 1800, + parameter integer DATARATE_01 = 1800, + parameter integer DATARATE_02 = 1800, + parameter integer DATARATE_03 = 1800, + parameter integer DATARATE_04 = 1800, + parameter integer DATARATE_05 = 1800, + parameter integer DATARATE_06 = 1800, + parameter integer DATARATE_07 = 1800, + parameter DA_LOCKOUT = "FALSE", + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0, + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0, + parameter MC_ENABLE_0 = "FALSE", + parameter MC_ENABLE_1 = "FALSE", + parameter MC_ENABLE_2 = "FALSE", + parameter MC_ENABLE_3 = "FALSE", + parameter MC_ENABLE_4 = "FALSE", + parameter MC_ENABLE_5 = "FALSE", + parameter MC_ENABLE_6 = "FALSE", + parameter MC_ENABLE_7 = "FALSE", + parameter MC_ENABLE_APB = "FALSE", + parameter integer PAGEHIT_PERCENT_00 = 75, + parameter PHY_ENABLE_00 = "FALSE", + parameter PHY_ENABLE_01 = "FALSE", + parameter PHY_ENABLE_02 = "FALSE", + parameter PHY_ENABLE_03 = "FALSE", + parameter PHY_ENABLE_04 = "FALSE", + parameter PHY_ENABLE_05 = "FALSE", + parameter PHY_ENABLE_06 = "FALSE", + parameter PHY_ENABLE_07 = "FALSE", + parameter PHY_ENABLE_08 = "FALSE", + parameter PHY_ENABLE_09 = "FALSE", + parameter PHY_ENABLE_10 = "FALSE", + parameter PHY_ENABLE_11 = "FALSE", + parameter PHY_ENABLE_12 = "FALSE", + parameter PHY_ENABLE_13 = "FALSE", + parameter PHY_ENABLE_14 = "FALSE", + parameter PHY_ENABLE_15 = "FALSE", + parameter PHY_ENABLE_APB = "FALSE", + parameter PHY_PCLK_INVERT_01 = "FALSE", + parameter integer READ_PERCENT_00 = 50, + parameter integer READ_PERCENT_01 = 50, + parameter integer READ_PERCENT_02 = 50, + parameter integer READ_PERCENT_03 = 50, + parameter integer READ_PERCENT_04 = 50, + parameter integer READ_PERCENT_05 = 50, + parameter integer READ_PERCENT_06 = 50, + parameter integer READ_PERCENT_07 = 50, + parameter integer READ_PERCENT_08 = 50, + parameter integer READ_PERCENT_09 = 50, + parameter integer READ_PERCENT_10 = 50, + parameter integer READ_PERCENT_11 = 50, + parameter integer READ_PERCENT_12 = 50, + parameter integer READ_PERCENT_13 = 50, + parameter integer READ_PERCENT_14 = 50, + parameter integer READ_PERCENT_15 = 50, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter integer STACK_LOCATION = 0, + parameter SWITCH_ENABLE = "FALSE", + parameter integer WRITE_PERCENT_00 = 50, + parameter integer WRITE_PERCENT_01 = 50, + parameter integer WRITE_PERCENT_02 = 50, + parameter integer WRITE_PERCENT_03 = 50, + parameter integer WRITE_PERCENT_04 = 50, + parameter integer WRITE_PERCENT_05 = 50, + parameter integer WRITE_PERCENT_06 = 50, + parameter integer WRITE_PERCENT_07 = 50, + parameter integer WRITE_PERCENT_08 = 50, + parameter integer WRITE_PERCENT_09 = 50, + parameter integer WRITE_PERCENT_10 = 50, + parameter integer WRITE_PERCENT_11 = 50, + parameter integer WRITE_PERCENT_12 = 50, + parameter integer WRITE_PERCENT_13 = 50, + parameter integer WRITE_PERCENT_14 = 50, + parameter integer WRITE_PERCENT_15 = 50 +)( + output [31:0] APB_0_PRDATA, + output APB_0_PREADY, + output APB_0_PSLVERR, + output AXI_00_ARREADY, + output AXI_00_AWREADY, + output [5:0] AXI_00_BID, + output [1:0] AXI_00_BRESP, + output AXI_00_BVALID, + output [1:0] AXI_00_DFI_AW_AERR_N, + output AXI_00_DFI_CLK_BUF, + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_00_DFI_DW_RDDATA_DBI, + output [7:0] AXI_00_DFI_DW_RDDATA_DERR, + output [1:0] AXI_00_DFI_DW_RDDATA_VALID, + output AXI_00_DFI_INIT_COMPLETE, + output AXI_00_DFI_PHYUPD_REQ, + output AXI_00_DFI_PHY_LP_STATE, + output AXI_00_DFI_RST_N_BUF, + output [5:0] AXI_00_MC_STATUS, + output [7:0] AXI_00_PHY_STATUS, + output [255:0] AXI_00_RDATA, + output [31:0] AXI_00_RDATA_PARITY, + output [5:0] AXI_00_RID, + output AXI_00_RLAST, + output [1:0] AXI_00_RRESP, + output AXI_00_RVALID, + output AXI_00_WREADY, + output AXI_01_ARREADY, + output AXI_01_AWREADY, + output [5:0] AXI_01_BID, + output [1:0] AXI_01_BRESP, + output AXI_01_BVALID, + output [1:0] AXI_01_DFI_AW_AERR_N, + output AXI_01_DFI_CLK_BUF, + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_01_DFI_DW_RDDATA_DBI, + output [7:0] AXI_01_DFI_DW_RDDATA_DERR, + output [1:0] AXI_01_DFI_DW_RDDATA_VALID, + output AXI_01_DFI_INIT_COMPLETE, + output AXI_01_DFI_PHYUPD_REQ, + output AXI_01_DFI_PHY_LP_STATE, + output AXI_01_DFI_RST_N_BUF, + output [255:0] AXI_01_RDATA, + output [31:0] AXI_01_RDATA_PARITY, + output [5:0] AXI_01_RID, + output AXI_01_RLAST, + output [1:0] AXI_01_RRESP, + output AXI_01_RVALID, + output AXI_01_WREADY, + output AXI_02_ARREADY, + output AXI_02_AWREADY, + output [5:0] AXI_02_BID, + output [1:0] AXI_02_BRESP, + output AXI_02_BVALID, + output [1:0] AXI_02_DFI_AW_AERR_N, + output AXI_02_DFI_CLK_BUF, + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_02_DFI_DW_RDDATA_DBI, + output [7:0] AXI_02_DFI_DW_RDDATA_DERR, + output [1:0] AXI_02_DFI_DW_RDDATA_VALID, + output AXI_02_DFI_INIT_COMPLETE, + output AXI_02_DFI_PHYUPD_REQ, + output AXI_02_DFI_PHY_LP_STATE, + output AXI_02_DFI_RST_N_BUF, + output [5:0] AXI_02_MC_STATUS, + output [7:0] AXI_02_PHY_STATUS, + output [255:0] AXI_02_RDATA, + output [31:0] AXI_02_RDATA_PARITY, + output [5:0] AXI_02_RID, + output AXI_02_RLAST, + output [1:0] AXI_02_RRESP, + output AXI_02_RVALID, + output AXI_02_WREADY, + output AXI_03_ARREADY, + output AXI_03_AWREADY, + output [5:0] AXI_03_BID, + output [1:0] AXI_03_BRESP, + output AXI_03_BVALID, + output [1:0] AXI_03_DFI_AW_AERR_N, + output AXI_03_DFI_CLK_BUF, + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_03_DFI_DW_RDDATA_DBI, + output [7:0] AXI_03_DFI_DW_RDDATA_DERR, + output [1:0] AXI_03_DFI_DW_RDDATA_VALID, + output AXI_03_DFI_INIT_COMPLETE, + output AXI_03_DFI_PHYUPD_REQ, + output AXI_03_DFI_PHY_LP_STATE, + output AXI_03_DFI_RST_N_BUF, + output [255:0] AXI_03_RDATA, + output [31:0] AXI_03_RDATA_PARITY, + output [5:0] AXI_03_RID, + output AXI_03_RLAST, + output [1:0] AXI_03_RRESP, + output AXI_03_RVALID, + output AXI_03_WREADY, + output AXI_04_ARREADY, + output AXI_04_AWREADY, + output [5:0] AXI_04_BID, + output [1:0] AXI_04_BRESP, + output AXI_04_BVALID, + output [1:0] AXI_04_DFI_AW_AERR_N, + output AXI_04_DFI_CLK_BUF, + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_04_DFI_DW_RDDATA_DBI, + output [7:0] AXI_04_DFI_DW_RDDATA_DERR, + output [1:0] AXI_04_DFI_DW_RDDATA_VALID, + output AXI_04_DFI_INIT_COMPLETE, + output AXI_04_DFI_PHYUPD_REQ, + output AXI_04_DFI_PHY_LP_STATE, + output AXI_04_DFI_RST_N_BUF, + output [5:0] AXI_04_MC_STATUS, + output [7:0] AXI_04_PHY_STATUS, + output [255:0] AXI_04_RDATA, + output [31:0] AXI_04_RDATA_PARITY, + output [5:0] AXI_04_RID, + output AXI_04_RLAST, + output [1:0] AXI_04_RRESP, + output AXI_04_RVALID, + output AXI_04_WREADY, + output AXI_05_ARREADY, + output AXI_05_AWREADY, + output [5:0] AXI_05_BID, + output [1:0] AXI_05_BRESP, + output AXI_05_BVALID, + output [1:0] AXI_05_DFI_AW_AERR_N, + output AXI_05_DFI_CLK_BUF, + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_05_DFI_DW_RDDATA_DBI, + output [7:0] AXI_05_DFI_DW_RDDATA_DERR, + output [1:0] AXI_05_DFI_DW_RDDATA_VALID, + output AXI_05_DFI_INIT_COMPLETE, + output AXI_05_DFI_PHYUPD_REQ, + output AXI_05_DFI_PHY_LP_STATE, + output AXI_05_DFI_RST_N_BUF, + output [255:0] AXI_05_RDATA, + output [31:0] AXI_05_RDATA_PARITY, + output [5:0] AXI_05_RID, + output AXI_05_RLAST, + output [1:0] AXI_05_RRESP, + output AXI_05_RVALID, + output AXI_05_WREADY, + output AXI_06_ARREADY, + output AXI_06_AWREADY, + output [5:0] AXI_06_BID, + output [1:0] AXI_06_BRESP, + output AXI_06_BVALID, + output [1:0] AXI_06_DFI_AW_AERR_N, + output AXI_06_DFI_CLK_BUF, + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_06_DFI_DW_RDDATA_DBI, + output [7:0] AXI_06_DFI_DW_RDDATA_DERR, + output [1:0] AXI_06_DFI_DW_RDDATA_VALID, + output AXI_06_DFI_INIT_COMPLETE, + output AXI_06_DFI_PHYUPD_REQ, + output AXI_06_DFI_PHY_LP_STATE, + output AXI_06_DFI_RST_N_BUF, + output [5:0] AXI_06_MC_STATUS, + output [7:0] AXI_06_PHY_STATUS, + output [255:0] AXI_06_RDATA, + output [31:0] AXI_06_RDATA_PARITY, + output [5:0] AXI_06_RID, + output AXI_06_RLAST, + output [1:0] AXI_06_RRESP, + output AXI_06_RVALID, + output AXI_06_WREADY, + output AXI_07_ARREADY, + output AXI_07_AWREADY, + output [5:0] AXI_07_BID, + output [1:0] AXI_07_BRESP, + output AXI_07_BVALID, + output [1:0] AXI_07_DFI_AW_AERR_N, + output AXI_07_DFI_CLK_BUF, + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_07_DFI_DW_RDDATA_DBI, + output [7:0] AXI_07_DFI_DW_RDDATA_DERR, + output [1:0] AXI_07_DFI_DW_RDDATA_VALID, + output AXI_07_DFI_INIT_COMPLETE, + output AXI_07_DFI_PHYUPD_REQ, + output AXI_07_DFI_PHY_LP_STATE, + output AXI_07_DFI_RST_N_BUF, + output [255:0] AXI_07_RDATA, + output [31:0] AXI_07_RDATA_PARITY, + output [5:0] AXI_07_RID, + output AXI_07_RLAST, + output [1:0] AXI_07_RRESP, + output AXI_07_RVALID, + output AXI_07_WREADY, + output AXI_08_ARREADY, + output AXI_08_AWREADY, + output [5:0] AXI_08_BID, + output [1:0] AXI_08_BRESP, + output AXI_08_BVALID, + output [1:0] AXI_08_DFI_AW_AERR_N, + output AXI_08_DFI_CLK_BUF, + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_08_DFI_DW_RDDATA_DBI, + output [7:0] AXI_08_DFI_DW_RDDATA_DERR, + output [1:0] AXI_08_DFI_DW_RDDATA_VALID, + output AXI_08_DFI_INIT_COMPLETE, + output AXI_08_DFI_PHYUPD_REQ, + output AXI_08_DFI_PHY_LP_STATE, + output AXI_08_DFI_RST_N_BUF, + output [5:0] AXI_08_MC_STATUS, + output [7:0] AXI_08_PHY_STATUS, + output [255:0] AXI_08_RDATA, + output [31:0] AXI_08_RDATA_PARITY, + output [5:0] AXI_08_RID, + output AXI_08_RLAST, + output [1:0] AXI_08_RRESP, + output AXI_08_RVALID, + output AXI_08_WREADY, + output AXI_09_ARREADY, + output AXI_09_AWREADY, + output [5:0] AXI_09_BID, + output [1:0] AXI_09_BRESP, + output AXI_09_BVALID, + output [1:0] AXI_09_DFI_AW_AERR_N, + output AXI_09_DFI_CLK_BUF, + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_09_DFI_DW_RDDATA_DBI, + output [7:0] AXI_09_DFI_DW_RDDATA_DERR, + output [1:0] AXI_09_DFI_DW_RDDATA_VALID, + output AXI_09_DFI_INIT_COMPLETE, + output AXI_09_DFI_PHYUPD_REQ, + output AXI_09_DFI_PHY_LP_STATE, + output AXI_09_DFI_RST_N_BUF, + output [255:0] AXI_09_RDATA, + output [31:0] AXI_09_RDATA_PARITY, + output [5:0] AXI_09_RID, + output AXI_09_RLAST, + output [1:0] AXI_09_RRESP, + output AXI_09_RVALID, + output AXI_09_WREADY, + output AXI_10_ARREADY, + output AXI_10_AWREADY, + output [5:0] AXI_10_BID, + output [1:0] AXI_10_BRESP, + output AXI_10_BVALID, + output [1:0] AXI_10_DFI_AW_AERR_N, + output AXI_10_DFI_CLK_BUF, + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_10_DFI_DW_RDDATA_DBI, + output [7:0] AXI_10_DFI_DW_RDDATA_DERR, + output [1:0] AXI_10_DFI_DW_RDDATA_VALID, + output AXI_10_DFI_INIT_COMPLETE, + output AXI_10_DFI_PHYUPD_REQ, + output AXI_10_DFI_PHY_LP_STATE, + output AXI_10_DFI_RST_N_BUF, + output [5:0] AXI_10_MC_STATUS, + output [7:0] AXI_10_PHY_STATUS, + output [255:0] AXI_10_RDATA, + output [31:0] AXI_10_RDATA_PARITY, + output [5:0] AXI_10_RID, + output AXI_10_RLAST, + output [1:0] AXI_10_RRESP, + output AXI_10_RVALID, + output AXI_10_WREADY, + output AXI_11_ARREADY, + output AXI_11_AWREADY, + output [5:0] AXI_11_BID, + output [1:0] AXI_11_BRESP, + output AXI_11_BVALID, + output [1:0] AXI_11_DFI_AW_AERR_N, + output AXI_11_DFI_CLK_BUF, + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_11_DFI_DW_RDDATA_DBI, + output [7:0] AXI_11_DFI_DW_RDDATA_DERR, + output [1:0] AXI_11_DFI_DW_RDDATA_VALID, + output AXI_11_DFI_INIT_COMPLETE, + output AXI_11_DFI_PHYUPD_REQ, + output AXI_11_DFI_PHY_LP_STATE, + output AXI_11_DFI_RST_N_BUF, + output [255:0] AXI_11_RDATA, + output [31:0] AXI_11_RDATA_PARITY, + output [5:0] AXI_11_RID, + output AXI_11_RLAST, + output [1:0] AXI_11_RRESP, + output AXI_11_RVALID, + output AXI_11_WREADY, + output AXI_12_ARREADY, + output AXI_12_AWREADY, + output [5:0] AXI_12_BID, + output [1:0] AXI_12_BRESP, + output AXI_12_BVALID, + output [1:0] AXI_12_DFI_AW_AERR_N, + output AXI_12_DFI_CLK_BUF, + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_12_DFI_DW_RDDATA_DBI, + output [7:0] AXI_12_DFI_DW_RDDATA_DERR, + output [1:0] AXI_12_DFI_DW_RDDATA_VALID, + output AXI_12_DFI_INIT_COMPLETE, + output AXI_12_DFI_PHYUPD_REQ, + output AXI_12_DFI_PHY_LP_STATE, + output AXI_12_DFI_RST_N_BUF, + output [5:0] AXI_12_MC_STATUS, + output [7:0] AXI_12_PHY_STATUS, + output [255:0] AXI_12_RDATA, + output [31:0] AXI_12_RDATA_PARITY, + output [5:0] AXI_12_RID, + output AXI_12_RLAST, + output [1:0] AXI_12_RRESP, + output AXI_12_RVALID, + output AXI_12_WREADY, + output AXI_13_ARREADY, + output AXI_13_AWREADY, + output [5:0] AXI_13_BID, + output [1:0] AXI_13_BRESP, + output AXI_13_BVALID, + output [1:0] AXI_13_DFI_AW_AERR_N, + output AXI_13_DFI_CLK_BUF, + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_13_DFI_DW_RDDATA_DBI, + output [7:0] AXI_13_DFI_DW_RDDATA_DERR, + output [1:0] AXI_13_DFI_DW_RDDATA_VALID, + output AXI_13_DFI_INIT_COMPLETE, + output AXI_13_DFI_PHYUPD_REQ, + output AXI_13_DFI_PHY_LP_STATE, + output AXI_13_DFI_RST_N_BUF, + output [255:0] AXI_13_RDATA, + output [31:0] AXI_13_RDATA_PARITY, + output [5:0] AXI_13_RID, + output AXI_13_RLAST, + output [1:0] AXI_13_RRESP, + output AXI_13_RVALID, + output AXI_13_WREADY, + output AXI_14_ARREADY, + output AXI_14_AWREADY, + output [5:0] AXI_14_BID, + output [1:0] AXI_14_BRESP, + output AXI_14_BVALID, + output [1:0] AXI_14_DFI_AW_AERR_N, + output AXI_14_DFI_CLK_BUF, + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_14_DFI_DW_RDDATA_DBI, + output [7:0] AXI_14_DFI_DW_RDDATA_DERR, + output [1:0] AXI_14_DFI_DW_RDDATA_VALID, + output AXI_14_DFI_INIT_COMPLETE, + output AXI_14_DFI_PHYUPD_REQ, + output AXI_14_DFI_PHY_LP_STATE, + output AXI_14_DFI_RST_N_BUF, + output [5:0] AXI_14_MC_STATUS, + output [7:0] AXI_14_PHY_STATUS, + output [255:0] AXI_14_RDATA, + output [31:0] AXI_14_RDATA_PARITY, + output [5:0] AXI_14_RID, + output AXI_14_RLAST, + output [1:0] AXI_14_RRESP, + output AXI_14_RVALID, + output AXI_14_WREADY, + output AXI_15_ARREADY, + output AXI_15_AWREADY, + output [5:0] AXI_15_BID, + output [1:0] AXI_15_BRESP, + output AXI_15_BVALID, + output [1:0] AXI_15_DFI_AW_AERR_N, + output AXI_15_DFI_CLK_BUF, + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_15_DFI_DW_RDDATA_DBI, + output [7:0] AXI_15_DFI_DW_RDDATA_DERR, + output [1:0] AXI_15_DFI_DW_RDDATA_VALID, + output AXI_15_DFI_INIT_COMPLETE, + output AXI_15_DFI_PHYUPD_REQ, + output AXI_15_DFI_PHY_LP_STATE, + output AXI_15_DFI_RST_N_BUF, + output [255:0] AXI_15_RDATA, + output [31:0] AXI_15_RDATA_PARITY, + output [5:0] AXI_15_RID, + output AXI_15_RLAST, + output [1:0] AXI_15_RRESP, + output AXI_15_RVALID, + output AXI_15_WREADY, + output DRAM_0_STAT_CATTRIP, + output [2:0] DRAM_0_STAT_TEMP, + + input [21:0] APB_0_PADDR, + input APB_0_PCLK, + input APB_0_PENABLE, + input APB_0_PRESET_N, + input APB_0_PSEL, + input [31:0] APB_0_PWDATA, + input APB_0_PWRITE, + input AXI_00_ACLK, + input [36:0] AXI_00_ARADDR, + input [1:0] AXI_00_ARBURST, + input AXI_00_ARESET_N, + input [5:0] AXI_00_ARID, + input [3:0] AXI_00_ARLEN, + input [2:0] AXI_00_ARSIZE, + input AXI_00_ARVALID, + input [36:0] AXI_00_AWADDR, + input [1:0] AXI_00_AWBURST, + input [5:0] AXI_00_AWID, + input [3:0] AXI_00_AWLEN, + input [2:0] AXI_00_AWSIZE, + input AXI_00_AWVALID, + input AXI_00_BREADY, + input AXI_00_DFI_LP_PWR_X_REQ, + input AXI_00_RREADY, + input [255:0] AXI_00_WDATA, + input [31:0] AXI_00_WDATA_PARITY, + input AXI_00_WLAST, + input [31:0] AXI_00_WSTRB, + input AXI_00_WVALID, + input AXI_01_ACLK, + input [36:0] AXI_01_ARADDR, + input [1:0] AXI_01_ARBURST, + input AXI_01_ARESET_N, + input [5:0] AXI_01_ARID, + input [3:0] AXI_01_ARLEN, + input [2:0] AXI_01_ARSIZE, + input AXI_01_ARVALID, + input [36:0] AXI_01_AWADDR, + input [1:0] AXI_01_AWBURST, + input [5:0] AXI_01_AWID, + input [3:0] AXI_01_AWLEN, + input [2:0] AXI_01_AWSIZE, + input AXI_01_AWVALID, + input AXI_01_BREADY, + input AXI_01_DFI_LP_PWR_X_REQ, + input AXI_01_RREADY, + input [255:0] AXI_01_WDATA, + input [31:0] AXI_01_WDATA_PARITY, + input AXI_01_WLAST, + input [31:0] AXI_01_WSTRB, + input AXI_01_WVALID, + input AXI_02_ACLK, + input [36:0] AXI_02_ARADDR, + input [1:0] AXI_02_ARBURST, + input AXI_02_ARESET_N, + input [5:0] AXI_02_ARID, + input [3:0] AXI_02_ARLEN, + input [2:0] AXI_02_ARSIZE, + input AXI_02_ARVALID, + input [36:0] AXI_02_AWADDR, + input [1:0] AXI_02_AWBURST, + input [5:0] AXI_02_AWID, + input [3:0] AXI_02_AWLEN, + input [2:0] AXI_02_AWSIZE, + input AXI_02_AWVALID, + input AXI_02_BREADY, + input AXI_02_DFI_LP_PWR_X_REQ, + input AXI_02_RREADY, + input [255:0] AXI_02_WDATA, + input [31:0] AXI_02_WDATA_PARITY, + input AXI_02_WLAST, + input [31:0] AXI_02_WSTRB, + input AXI_02_WVALID, + input AXI_03_ACLK, + input [36:0] AXI_03_ARADDR, + input [1:0] AXI_03_ARBURST, + input AXI_03_ARESET_N, + input [5:0] AXI_03_ARID, + input [3:0] AXI_03_ARLEN, + input [2:0] AXI_03_ARSIZE, + input AXI_03_ARVALID, + input [36:0] AXI_03_AWADDR, + input [1:0] AXI_03_AWBURST, + input [5:0] AXI_03_AWID, + input [3:0] AXI_03_AWLEN, + input [2:0] AXI_03_AWSIZE, + input AXI_03_AWVALID, + input AXI_03_BREADY, + input AXI_03_DFI_LP_PWR_X_REQ, + input AXI_03_RREADY, + input [255:0] AXI_03_WDATA, + input [31:0] AXI_03_WDATA_PARITY, + input AXI_03_WLAST, + input [31:0] AXI_03_WSTRB, + input AXI_03_WVALID, + input AXI_04_ACLK, + input [36:0] AXI_04_ARADDR, + input [1:0] AXI_04_ARBURST, + input AXI_04_ARESET_N, + input [5:0] AXI_04_ARID, + input [3:0] AXI_04_ARLEN, + input [2:0] AXI_04_ARSIZE, + input AXI_04_ARVALID, + input [36:0] AXI_04_AWADDR, + input [1:0] AXI_04_AWBURST, + input [5:0] AXI_04_AWID, + input [3:0] AXI_04_AWLEN, + input [2:0] AXI_04_AWSIZE, + input AXI_04_AWVALID, + input AXI_04_BREADY, + input AXI_04_DFI_LP_PWR_X_REQ, + input AXI_04_RREADY, + input [255:0] AXI_04_WDATA, + input [31:0] AXI_04_WDATA_PARITY, + input AXI_04_WLAST, + input [31:0] AXI_04_WSTRB, + input AXI_04_WVALID, + input AXI_05_ACLK, + input [36:0] AXI_05_ARADDR, + input [1:0] AXI_05_ARBURST, + input AXI_05_ARESET_N, + input [5:0] AXI_05_ARID, + input [3:0] AXI_05_ARLEN, + input [2:0] AXI_05_ARSIZE, + input AXI_05_ARVALID, + input [36:0] AXI_05_AWADDR, + input [1:0] AXI_05_AWBURST, + input [5:0] AXI_05_AWID, + input [3:0] AXI_05_AWLEN, + input [2:0] AXI_05_AWSIZE, + input AXI_05_AWVALID, + input AXI_05_BREADY, + input AXI_05_DFI_LP_PWR_X_REQ, + input AXI_05_RREADY, + input [255:0] AXI_05_WDATA, + input [31:0] AXI_05_WDATA_PARITY, + input AXI_05_WLAST, + input [31:0] AXI_05_WSTRB, + input AXI_05_WVALID, + input AXI_06_ACLK, + input [36:0] AXI_06_ARADDR, + input [1:0] AXI_06_ARBURST, + input AXI_06_ARESET_N, + input [5:0] AXI_06_ARID, + input [3:0] AXI_06_ARLEN, + input [2:0] AXI_06_ARSIZE, + input AXI_06_ARVALID, + input [36:0] AXI_06_AWADDR, + input [1:0] AXI_06_AWBURST, + input [5:0] AXI_06_AWID, + input [3:0] AXI_06_AWLEN, + input [2:0] AXI_06_AWSIZE, + input AXI_06_AWVALID, + input AXI_06_BREADY, + input AXI_06_DFI_LP_PWR_X_REQ, + input AXI_06_RREADY, + input [255:0] AXI_06_WDATA, + input [31:0] AXI_06_WDATA_PARITY, + input AXI_06_WLAST, + input [31:0] AXI_06_WSTRB, + input AXI_06_WVALID, + input AXI_07_ACLK, + input [36:0] AXI_07_ARADDR, + input [1:0] AXI_07_ARBURST, + input AXI_07_ARESET_N, + input [5:0] AXI_07_ARID, + input [3:0] AXI_07_ARLEN, + input [2:0] AXI_07_ARSIZE, + input AXI_07_ARVALID, + input [36:0] AXI_07_AWADDR, + input [1:0] AXI_07_AWBURST, + input [5:0] AXI_07_AWID, + input [3:0] AXI_07_AWLEN, + input [2:0] AXI_07_AWSIZE, + input AXI_07_AWVALID, + input AXI_07_BREADY, + input AXI_07_DFI_LP_PWR_X_REQ, + input AXI_07_RREADY, + input [255:0] AXI_07_WDATA, + input [31:0] AXI_07_WDATA_PARITY, + input AXI_07_WLAST, + input [31:0] AXI_07_WSTRB, + input AXI_07_WVALID, + input AXI_08_ACLK, + input [36:0] AXI_08_ARADDR, + input [1:0] AXI_08_ARBURST, + input AXI_08_ARESET_N, + input [5:0] AXI_08_ARID, + input [3:0] AXI_08_ARLEN, + input [2:0] AXI_08_ARSIZE, + input AXI_08_ARVALID, + input [36:0] AXI_08_AWADDR, + input [1:0] AXI_08_AWBURST, + input [5:0] AXI_08_AWID, + input [3:0] AXI_08_AWLEN, + input [2:0] AXI_08_AWSIZE, + input AXI_08_AWVALID, + input AXI_08_BREADY, + input AXI_08_DFI_LP_PWR_X_REQ, + input AXI_08_RREADY, + input [255:0] AXI_08_WDATA, + input [31:0] AXI_08_WDATA_PARITY, + input AXI_08_WLAST, + input [31:0] AXI_08_WSTRB, + input AXI_08_WVALID, + input AXI_09_ACLK, + input [36:0] AXI_09_ARADDR, + input [1:0] AXI_09_ARBURST, + input AXI_09_ARESET_N, + input [5:0] AXI_09_ARID, + input [3:0] AXI_09_ARLEN, + input [2:0] AXI_09_ARSIZE, + input AXI_09_ARVALID, + input [36:0] AXI_09_AWADDR, + input [1:0] AXI_09_AWBURST, + input [5:0] AXI_09_AWID, + input [3:0] AXI_09_AWLEN, + input [2:0] AXI_09_AWSIZE, + input AXI_09_AWVALID, + input AXI_09_BREADY, + input AXI_09_DFI_LP_PWR_X_REQ, + input AXI_09_RREADY, + input [255:0] AXI_09_WDATA, + input [31:0] AXI_09_WDATA_PARITY, + input AXI_09_WLAST, + input [31:0] AXI_09_WSTRB, + input AXI_09_WVALID, + input AXI_10_ACLK, + input [36:0] AXI_10_ARADDR, + input [1:0] AXI_10_ARBURST, + input AXI_10_ARESET_N, + input [5:0] AXI_10_ARID, + input [3:0] AXI_10_ARLEN, + input [2:0] AXI_10_ARSIZE, + input AXI_10_ARVALID, + input [36:0] AXI_10_AWADDR, + input [1:0] AXI_10_AWBURST, + input [5:0] AXI_10_AWID, + input [3:0] AXI_10_AWLEN, + input [2:0] AXI_10_AWSIZE, + input AXI_10_AWVALID, + input AXI_10_BREADY, + input AXI_10_DFI_LP_PWR_X_REQ, + input AXI_10_RREADY, + input [255:0] AXI_10_WDATA, + input [31:0] AXI_10_WDATA_PARITY, + input AXI_10_WLAST, + input [31:0] AXI_10_WSTRB, + input AXI_10_WVALID, + input AXI_11_ACLK, + input [36:0] AXI_11_ARADDR, + input [1:0] AXI_11_ARBURST, + input AXI_11_ARESET_N, + input [5:0] AXI_11_ARID, + input [3:0] AXI_11_ARLEN, + input [2:0] AXI_11_ARSIZE, + input AXI_11_ARVALID, + input [36:0] AXI_11_AWADDR, + input [1:0] AXI_11_AWBURST, + input [5:0] AXI_11_AWID, + input [3:0] AXI_11_AWLEN, + input [2:0] AXI_11_AWSIZE, + input AXI_11_AWVALID, + input AXI_11_BREADY, + input AXI_11_DFI_LP_PWR_X_REQ, + input AXI_11_RREADY, + input [255:0] AXI_11_WDATA, + input [31:0] AXI_11_WDATA_PARITY, + input AXI_11_WLAST, + input [31:0] AXI_11_WSTRB, + input AXI_11_WVALID, + input AXI_12_ACLK, + input [36:0] AXI_12_ARADDR, + input [1:0] AXI_12_ARBURST, + input AXI_12_ARESET_N, + input [5:0] AXI_12_ARID, + input [3:0] AXI_12_ARLEN, + input [2:0] AXI_12_ARSIZE, + input AXI_12_ARVALID, + input [36:0] AXI_12_AWADDR, + input [1:0] AXI_12_AWBURST, + input [5:0] AXI_12_AWID, + input [3:0] AXI_12_AWLEN, + input [2:0] AXI_12_AWSIZE, + input AXI_12_AWVALID, + input AXI_12_BREADY, + input AXI_12_DFI_LP_PWR_X_REQ, + input AXI_12_RREADY, + input [255:0] AXI_12_WDATA, + input [31:0] AXI_12_WDATA_PARITY, + input AXI_12_WLAST, + input [31:0] AXI_12_WSTRB, + input AXI_12_WVALID, + input AXI_13_ACLK, + input [36:0] AXI_13_ARADDR, + input [1:0] AXI_13_ARBURST, + input AXI_13_ARESET_N, + input [5:0] AXI_13_ARID, + input [3:0] AXI_13_ARLEN, + input [2:0] AXI_13_ARSIZE, + input AXI_13_ARVALID, + input [36:0] AXI_13_AWADDR, + input [1:0] AXI_13_AWBURST, + input [5:0] AXI_13_AWID, + input [3:0] AXI_13_AWLEN, + input [2:0] AXI_13_AWSIZE, + input AXI_13_AWVALID, + input AXI_13_BREADY, + input AXI_13_DFI_LP_PWR_X_REQ, + input AXI_13_RREADY, + input [255:0] AXI_13_WDATA, + input [31:0] AXI_13_WDATA_PARITY, + input AXI_13_WLAST, + input [31:0] AXI_13_WSTRB, + input AXI_13_WVALID, + input AXI_14_ACLK, + input [36:0] AXI_14_ARADDR, + input [1:0] AXI_14_ARBURST, + input AXI_14_ARESET_N, + input [5:0] AXI_14_ARID, + input [3:0] AXI_14_ARLEN, + input [2:0] AXI_14_ARSIZE, + input AXI_14_ARVALID, + input [36:0] AXI_14_AWADDR, + input [1:0] AXI_14_AWBURST, + input [5:0] AXI_14_AWID, + input [3:0] AXI_14_AWLEN, + input [2:0] AXI_14_AWSIZE, + input AXI_14_AWVALID, + input AXI_14_BREADY, + input AXI_14_DFI_LP_PWR_X_REQ, + input AXI_14_RREADY, + input [255:0] AXI_14_WDATA, + input [31:0] AXI_14_WDATA_PARITY, + input AXI_14_WLAST, + input [31:0] AXI_14_WSTRB, + input AXI_14_WVALID, + input AXI_15_ACLK, + input [36:0] AXI_15_ARADDR, + input [1:0] AXI_15_ARBURST, + input AXI_15_ARESET_N, + input [5:0] AXI_15_ARID, + input [3:0] AXI_15_ARLEN, + input [2:0] AXI_15_ARSIZE, + input AXI_15_ARVALID, + input [36:0] AXI_15_AWADDR, + input [1:0] AXI_15_AWBURST, + input [5:0] AXI_15_AWID, + input [3:0] AXI_15_AWLEN, + input [2:0] AXI_15_AWSIZE, + input AXI_15_AWVALID, + input AXI_15_BREADY, + input AXI_15_DFI_LP_PWR_X_REQ, + input AXI_15_RREADY, + input [255:0] AXI_15_WDATA, + input [31:0] AXI_15_WDATA_PARITY, + input AXI_15_WLAST, + input [31:0] AXI_15_WSTRB, + input AXI_15_WVALID, + input BSCAN_DRCK, + input BSCAN_TCK, + input HBM_REF_CLK, + input MBIST_EN_00, + input MBIST_EN_01, + input MBIST_EN_02, + input MBIST_EN_03, + input MBIST_EN_04, + input MBIST_EN_05, + input MBIST_EN_06, + input MBIST_EN_07 +); + +// define constants + localparam MODULE_NAME = "HBM_ONE_STACK_INTF"; + +// Parameter encodings and registers + localparam PHY_PCLK_INVERT_01_FALSE = 0; + localparam PHY_PCLK_INVERT_01_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HBM_ONE_STACK_INTF_dr.v" +`else + localparam [40:1] CLK_SEL_00_REG = CLK_SEL_00; + localparam [40:1] CLK_SEL_01_REG = CLK_SEL_01; + localparam [40:1] CLK_SEL_02_REG = CLK_SEL_02; + localparam [40:1] CLK_SEL_03_REG = CLK_SEL_03; + localparam [40:1] CLK_SEL_04_REG = CLK_SEL_04; + localparam [40:1] CLK_SEL_05_REG = CLK_SEL_05; + localparam [40:1] CLK_SEL_06_REG = CLK_SEL_06; + localparam [40:1] CLK_SEL_07_REG = CLK_SEL_07; + localparam [40:1] CLK_SEL_08_REG = CLK_SEL_08; + localparam [40:1] CLK_SEL_09_REG = CLK_SEL_09; + localparam [40:1] CLK_SEL_10_REG = CLK_SEL_10; + localparam [40:1] CLK_SEL_11_REG = CLK_SEL_11; + localparam [40:1] CLK_SEL_12_REG = CLK_SEL_12; + localparam [40:1] CLK_SEL_13_REG = CLK_SEL_13; + localparam [40:1] CLK_SEL_14_REG = CLK_SEL_14; + localparam [40:1] CLK_SEL_15_REG = CLK_SEL_15; + localparam [10:0] DATARATE_00_REG = DATARATE_00; + localparam [10:0] DATARATE_01_REG = DATARATE_01; + localparam [10:0] DATARATE_02_REG = DATARATE_02; + localparam [10:0] DATARATE_03_REG = DATARATE_03; + localparam [10:0] DATARATE_04_REG = DATARATE_04; + localparam [10:0] DATARATE_05_REG = DATARATE_05; + localparam [10:0] DATARATE_06_REG = DATARATE_06; + localparam [10:0] DATARATE_07_REG = DATARATE_07; + localparam [40:1] DA_LOCKOUT_REG = DA_LOCKOUT; + localparam [0:0] IS_APB_0_PCLK_INVERTED_REG = IS_APB_0_PCLK_INVERTED; + localparam [0:0] IS_APB_0_PRESET_N_INVERTED_REG = IS_APB_0_PRESET_N_INVERTED; + localparam [0:0] IS_AXI_00_ACLK_INVERTED_REG = IS_AXI_00_ACLK_INVERTED; + localparam [0:0] IS_AXI_00_ARESET_N_INVERTED_REG = IS_AXI_00_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_01_ACLK_INVERTED_REG = IS_AXI_01_ACLK_INVERTED; + localparam [0:0] IS_AXI_01_ARESET_N_INVERTED_REG = IS_AXI_01_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_02_ACLK_INVERTED_REG = IS_AXI_02_ACLK_INVERTED; + localparam [0:0] IS_AXI_02_ARESET_N_INVERTED_REG = IS_AXI_02_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_03_ACLK_INVERTED_REG = IS_AXI_03_ACLK_INVERTED; + localparam [0:0] IS_AXI_03_ARESET_N_INVERTED_REG = IS_AXI_03_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_04_ACLK_INVERTED_REG = IS_AXI_04_ACLK_INVERTED; + localparam [0:0] IS_AXI_04_ARESET_N_INVERTED_REG = IS_AXI_04_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_05_ACLK_INVERTED_REG = IS_AXI_05_ACLK_INVERTED; + localparam [0:0] IS_AXI_05_ARESET_N_INVERTED_REG = IS_AXI_05_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_06_ACLK_INVERTED_REG = IS_AXI_06_ACLK_INVERTED; + localparam [0:0] IS_AXI_06_ARESET_N_INVERTED_REG = IS_AXI_06_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_07_ACLK_INVERTED_REG = IS_AXI_07_ACLK_INVERTED; + localparam [0:0] IS_AXI_07_ARESET_N_INVERTED_REG = IS_AXI_07_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_08_ACLK_INVERTED_REG = IS_AXI_08_ACLK_INVERTED; + localparam [0:0] IS_AXI_08_ARESET_N_INVERTED_REG = IS_AXI_08_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_09_ACLK_INVERTED_REG = IS_AXI_09_ACLK_INVERTED; + localparam [0:0] IS_AXI_09_ARESET_N_INVERTED_REG = IS_AXI_09_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_10_ACLK_INVERTED_REG = IS_AXI_10_ACLK_INVERTED; + localparam [0:0] IS_AXI_10_ARESET_N_INVERTED_REG = IS_AXI_10_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_11_ACLK_INVERTED_REG = IS_AXI_11_ACLK_INVERTED; + localparam [0:0] IS_AXI_11_ARESET_N_INVERTED_REG = IS_AXI_11_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_12_ACLK_INVERTED_REG = IS_AXI_12_ACLK_INVERTED; + localparam [0:0] IS_AXI_12_ARESET_N_INVERTED_REG = IS_AXI_12_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_13_ACLK_INVERTED_REG = IS_AXI_13_ACLK_INVERTED; + localparam [0:0] IS_AXI_13_ARESET_N_INVERTED_REG = IS_AXI_13_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_14_ACLK_INVERTED_REG = IS_AXI_14_ACLK_INVERTED; + localparam [0:0] IS_AXI_14_ARESET_N_INVERTED_REG = IS_AXI_14_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_15_ACLK_INVERTED_REG = IS_AXI_15_ACLK_INVERTED; + localparam [0:0] IS_AXI_15_ARESET_N_INVERTED_REG = IS_AXI_15_ARESET_N_INVERTED; + localparam [40:1] MC_ENABLE_0_REG = MC_ENABLE_0; + localparam [40:1] MC_ENABLE_1_REG = MC_ENABLE_1; + localparam [40:1] MC_ENABLE_2_REG = MC_ENABLE_2; + localparam [40:1] MC_ENABLE_3_REG = MC_ENABLE_3; + localparam [40:1] MC_ENABLE_4_REG = MC_ENABLE_4; + localparam [40:1] MC_ENABLE_5_REG = MC_ENABLE_5; + localparam [40:1] MC_ENABLE_6_REG = MC_ENABLE_6; + localparam [40:1] MC_ENABLE_7_REG = MC_ENABLE_7; + localparam [40:1] MC_ENABLE_APB_REG = MC_ENABLE_APB; + localparam [6:0] PAGEHIT_PERCENT_00_REG = PAGEHIT_PERCENT_00; + localparam [40:1] PHY_ENABLE_00_REG = PHY_ENABLE_00; + localparam [40:1] PHY_ENABLE_01_REG = PHY_ENABLE_01; + localparam [40:1] PHY_ENABLE_02_REG = PHY_ENABLE_02; + localparam [40:1] PHY_ENABLE_03_REG = PHY_ENABLE_03; + localparam [40:1] PHY_ENABLE_04_REG = PHY_ENABLE_04; + localparam [40:1] PHY_ENABLE_05_REG = PHY_ENABLE_05; + localparam [40:1] PHY_ENABLE_06_REG = PHY_ENABLE_06; + localparam [40:1] PHY_ENABLE_07_REG = PHY_ENABLE_07; + localparam [40:1] PHY_ENABLE_08_REG = PHY_ENABLE_08; + localparam [40:1] PHY_ENABLE_09_REG = PHY_ENABLE_09; + localparam [40:1] PHY_ENABLE_10_REG = PHY_ENABLE_10; + localparam [40:1] PHY_ENABLE_11_REG = PHY_ENABLE_11; + localparam [40:1] PHY_ENABLE_12_REG = PHY_ENABLE_12; + localparam [40:1] PHY_ENABLE_13_REG = PHY_ENABLE_13; + localparam [40:1] PHY_ENABLE_14_REG = PHY_ENABLE_14; + localparam [40:1] PHY_ENABLE_15_REG = PHY_ENABLE_15; + localparam [40:1] PHY_ENABLE_APB_REG = PHY_ENABLE_APB; + localparam [40:1] PHY_PCLK_INVERT_01_REG = PHY_PCLK_INVERT_01; + localparam [6:0] READ_PERCENT_00_REG = READ_PERCENT_00; + localparam [6:0] READ_PERCENT_01_REG = READ_PERCENT_01; + localparam [6:0] READ_PERCENT_02_REG = READ_PERCENT_02; + localparam [6:0] READ_PERCENT_03_REG = READ_PERCENT_03; + localparam [6:0] READ_PERCENT_04_REG = READ_PERCENT_04; + localparam [6:0] READ_PERCENT_05_REG = READ_PERCENT_05; + localparam [6:0] READ_PERCENT_06_REG = READ_PERCENT_06; + localparam [6:0] READ_PERCENT_07_REG = READ_PERCENT_07; + localparam [6:0] READ_PERCENT_08_REG = READ_PERCENT_08; + localparam [6:0] READ_PERCENT_09_REG = READ_PERCENT_09; + localparam [6:0] READ_PERCENT_10_REG = READ_PERCENT_10; + localparam [6:0] READ_PERCENT_11_REG = READ_PERCENT_11; + localparam [6:0] READ_PERCENT_12_REG = READ_PERCENT_12; + localparam [6:0] READ_PERCENT_13_REG = READ_PERCENT_13; + localparam [6:0] READ_PERCENT_14_REG = READ_PERCENT_14; + localparam [6:0] READ_PERCENT_15_REG = READ_PERCENT_15; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [0:0] STACK_LOCATION_REG = STACK_LOCATION; + localparam [40:1] SWITCH_ENABLE_REG = SWITCH_ENABLE; + localparam [6:0] WRITE_PERCENT_00_REG = WRITE_PERCENT_00; + localparam [6:0] WRITE_PERCENT_01_REG = WRITE_PERCENT_01; + localparam [6:0] WRITE_PERCENT_02_REG = WRITE_PERCENT_02; + localparam [6:0] WRITE_PERCENT_03_REG = WRITE_PERCENT_03; + localparam [6:0] WRITE_PERCENT_04_REG = WRITE_PERCENT_04; + localparam [6:0] WRITE_PERCENT_05_REG = WRITE_PERCENT_05; + localparam [6:0] WRITE_PERCENT_06_REG = WRITE_PERCENT_06; + localparam [6:0] WRITE_PERCENT_07_REG = WRITE_PERCENT_07; + localparam [6:0] WRITE_PERCENT_08_REG = WRITE_PERCENT_08; + localparam [6:0] WRITE_PERCENT_09_REG = WRITE_PERCENT_09; + localparam [6:0] WRITE_PERCENT_10_REG = WRITE_PERCENT_10; + localparam [6:0] WRITE_PERCENT_11_REG = WRITE_PERCENT_11; + localparam [6:0] WRITE_PERCENT_12_REG = WRITE_PERCENT_12; + localparam [6:0] WRITE_PERCENT_13_REG = WRITE_PERCENT_13; + localparam [6:0] WRITE_PERCENT_14_REG = WRITE_PERCENT_14; + localparam [6:0] WRITE_PERCENT_15_REG = WRITE_PERCENT_15; +`endif + + localparam [7:0] ANALOG_MUX_SEL_0_REG = 8'h00; + localparam [40:1] APB_BYPASS_EN_REG = "FALSE"; + localparam [40:1] AXI_BYPASS_EN_REG = "FALSE"; + localparam [40:1] BLI_TESTMODE_SEL_REG = "FALSE"; + localparam [51:0] DBG_BYPASS_VAL_REG = 52'hFFFFFFFFFFFFF; + localparam [40:1] DEBUG_MODE_REG = "FALSE"; + localparam [51:0] DFI_BYPASS_VAL_REG = 52'h0000000000000; + localparam [40:1] DLL_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] IO_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_0_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_1_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_2_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_3_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_4_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_5_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_6_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_7_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_1_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_2_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_3_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_4_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_5_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_6_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_7_REG = "FALSE"; + localparam [40:1] PHY_CSSD_SEL_0_REG = "FALSE"; + localparam [40:1] PHY_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] SW_TESTMODE_SEL_0_REG = "FALSE"; + +`ifdef XIL_XECLIB + wire PHY_PCLK_INVERT_01_BIN; +`else + reg PHY_PCLK_INVERT_01_BIN; +`endif + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire APB_0_PREADY_out; + wire APB_0_PSLVERR_out; + wire AXI_00_ARREADY_out; + wire AXI_00_AWREADY_out; + wire AXI_00_BVALID_out; + wire AXI_00_DFI_CLK_BUF_out; + wire AXI_00_DFI_INIT_COMPLETE_out; + wire AXI_00_DFI_PHYUPD_REQ_out; + wire AXI_00_DFI_PHY_LP_STATE_out; + wire AXI_00_DFI_RST_N_BUF_out; + wire AXI_00_RLAST_out; + wire AXI_00_RVALID_out; + wire AXI_00_WREADY_out; + wire AXI_01_ARREADY_out; + wire AXI_01_AWREADY_out; + wire AXI_01_BVALID_out; + wire AXI_01_DFI_CLK_BUF_out; + wire AXI_01_DFI_INIT_COMPLETE_out; + wire AXI_01_DFI_PHYUPD_REQ_out; + wire AXI_01_DFI_PHY_LP_STATE_out; + wire AXI_01_DFI_RST_N_BUF_out; + wire AXI_01_RLAST_out; + wire AXI_01_RVALID_out; + wire AXI_01_WREADY_out; + wire AXI_02_ARREADY_out; + wire AXI_02_AWREADY_out; + wire AXI_02_BVALID_out; + wire AXI_02_DFI_CLK_BUF_out; + wire AXI_02_DFI_INIT_COMPLETE_out; + wire AXI_02_DFI_PHYUPD_REQ_out; + wire AXI_02_DFI_PHY_LP_STATE_out; + wire AXI_02_DFI_RST_N_BUF_out; + wire AXI_02_RLAST_out; + wire AXI_02_RVALID_out; + wire AXI_02_WREADY_out; + wire AXI_03_ARREADY_out; + wire AXI_03_AWREADY_out; + wire AXI_03_BVALID_out; + wire AXI_03_DFI_CLK_BUF_out; + wire AXI_03_DFI_INIT_COMPLETE_out; + wire AXI_03_DFI_PHYUPD_REQ_out; + wire AXI_03_DFI_PHY_LP_STATE_out; + wire AXI_03_DFI_RST_N_BUF_out; + wire AXI_03_RLAST_out; + wire AXI_03_RVALID_out; + wire AXI_03_WREADY_out; + wire AXI_04_ARREADY_out; + wire AXI_04_AWREADY_out; + wire AXI_04_BVALID_out; + wire AXI_04_DFI_CLK_BUF_out; + wire AXI_04_DFI_INIT_COMPLETE_out; + wire AXI_04_DFI_PHYUPD_REQ_out; + wire AXI_04_DFI_PHY_LP_STATE_out; + wire AXI_04_DFI_RST_N_BUF_out; + wire AXI_04_RLAST_out; + wire AXI_04_RVALID_out; + wire AXI_04_WREADY_out; + wire AXI_05_ARREADY_out; + wire AXI_05_AWREADY_out; + wire AXI_05_BVALID_out; + wire AXI_05_DFI_CLK_BUF_out; + wire AXI_05_DFI_INIT_COMPLETE_out; + wire AXI_05_DFI_PHYUPD_REQ_out; + wire AXI_05_DFI_PHY_LP_STATE_out; + wire AXI_05_DFI_RST_N_BUF_out; + wire AXI_05_RLAST_out; + wire AXI_05_RVALID_out; + wire AXI_05_WREADY_out; + wire AXI_06_ARREADY_out; + wire AXI_06_AWREADY_out; + wire AXI_06_BVALID_out; + wire AXI_06_DFI_CLK_BUF_out; + wire AXI_06_DFI_INIT_COMPLETE_out; + wire AXI_06_DFI_PHYUPD_REQ_out; + wire AXI_06_DFI_PHY_LP_STATE_out; + wire AXI_06_DFI_RST_N_BUF_out; + wire AXI_06_RLAST_out; + wire AXI_06_RVALID_out; + wire AXI_06_WREADY_out; + wire AXI_07_ARREADY_out; + wire AXI_07_AWREADY_out; + wire AXI_07_BVALID_out; + wire AXI_07_DFI_CLK_BUF_out; + wire AXI_07_DFI_INIT_COMPLETE_out; + wire AXI_07_DFI_PHYUPD_REQ_out; + wire AXI_07_DFI_PHY_LP_STATE_out; + wire AXI_07_DFI_RST_N_BUF_out; + wire AXI_07_RLAST_out; + wire AXI_07_RVALID_out; + wire AXI_07_WREADY_out; + wire AXI_08_ARREADY_out; + wire AXI_08_AWREADY_out; + wire AXI_08_BVALID_out; + wire AXI_08_DFI_CLK_BUF_out; + wire AXI_08_DFI_INIT_COMPLETE_out; + wire AXI_08_DFI_PHYUPD_REQ_out; + wire AXI_08_DFI_PHY_LP_STATE_out; + wire AXI_08_DFI_RST_N_BUF_out; + wire AXI_08_RLAST_out; + wire AXI_08_RVALID_out; + wire AXI_08_WREADY_out; + wire AXI_09_ARREADY_out; + wire AXI_09_AWREADY_out; + wire AXI_09_BVALID_out; + wire AXI_09_DFI_CLK_BUF_out; + wire AXI_09_DFI_INIT_COMPLETE_out; + wire AXI_09_DFI_PHYUPD_REQ_out; + wire AXI_09_DFI_PHY_LP_STATE_out; + wire AXI_09_DFI_RST_N_BUF_out; + wire AXI_09_RLAST_out; + wire AXI_09_RVALID_out; + wire AXI_09_WREADY_out; + wire AXI_10_ARREADY_out; + wire AXI_10_AWREADY_out; + wire AXI_10_BVALID_out; + wire AXI_10_DFI_CLK_BUF_out; + wire AXI_10_DFI_INIT_COMPLETE_out; + wire AXI_10_DFI_PHYUPD_REQ_out; + wire AXI_10_DFI_PHY_LP_STATE_out; + wire AXI_10_DFI_RST_N_BUF_out; + wire AXI_10_RLAST_out; + wire AXI_10_RVALID_out; + wire AXI_10_WREADY_out; + wire AXI_11_ARREADY_out; + wire AXI_11_AWREADY_out; + wire AXI_11_BVALID_out; + wire AXI_11_DFI_CLK_BUF_out; + wire AXI_11_DFI_INIT_COMPLETE_out; + wire AXI_11_DFI_PHYUPD_REQ_out; + wire AXI_11_DFI_PHY_LP_STATE_out; + wire AXI_11_DFI_RST_N_BUF_out; + wire AXI_11_RLAST_out; + wire AXI_11_RVALID_out; + wire AXI_11_WREADY_out; + wire AXI_12_ARREADY_out; + wire AXI_12_AWREADY_out; + wire AXI_12_BVALID_out; + wire AXI_12_DFI_CLK_BUF_out; + wire AXI_12_DFI_INIT_COMPLETE_out; + wire AXI_12_DFI_PHYUPD_REQ_out; + wire AXI_12_DFI_PHY_LP_STATE_out; + wire AXI_12_DFI_RST_N_BUF_out; + wire AXI_12_RLAST_out; + wire AXI_12_RVALID_out; + wire AXI_12_WREADY_out; + wire AXI_13_ARREADY_out; + wire AXI_13_AWREADY_out; + wire AXI_13_BVALID_out; + wire AXI_13_DFI_CLK_BUF_out; + wire AXI_13_DFI_INIT_COMPLETE_out; + wire AXI_13_DFI_PHYUPD_REQ_out; + wire AXI_13_DFI_PHY_LP_STATE_out; + wire AXI_13_DFI_RST_N_BUF_out; + wire AXI_13_RLAST_out; + wire AXI_13_RVALID_out; + wire AXI_13_WREADY_out; + wire AXI_14_ARREADY_out; + wire AXI_14_AWREADY_out; + wire AXI_14_BVALID_out; + wire AXI_14_DFI_CLK_BUF_out; + wire AXI_14_DFI_INIT_COMPLETE_out; + wire AXI_14_DFI_PHYUPD_REQ_out; + wire AXI_14_DFI_PHY_LP_STATE_out; + wire AXI_14_DFI_RST_N_BUF_out; + wire AXI_14_RLAST_out; + wire AXI_14_RVALID_out; + wire AXI_14_WREADY_out; + wire AXI_15_ARREADY_out; + wire AXI_15_AWREADY_out; + wire AXI_15_BVALID_out; + wire AXI_15_DFI_CLK_BUF_out; + wire AXI_15_DFI_INIT_COMPLETE_out; + wire AXI_15_DFI_PHYUPD_REQ_out; + wire AXI_15_DFI_PHY_LP_STATE_out; + wire AXI_15_DFI_RST_N_BUF_out; + wire AXI_15_RLAST_out; + wire AXI_15_RVALID_out; + wire AXI_15_WREADY_out; + wire DRAM_0_STAT_CATTRIP_out; + wire [17:0] DBG_OUT_00_out; + wire [17:0] DBG_OUT_01_out; + wire [17:0] DBG_OUT_02_out; + wire [17:0] DBG_OUT_03_out; + wire [17:0] DBG_OUT_04_out; + wire [17:0] DBG_OUT_05_out; + wire [17:0] DBG_OUT_06_out; + wire [17:0] DBG_OUT_07_out; + wire [17:0] DBG_OUT_08_out; + wire [17:0] DBG_OUT_09_out; + wire [17:0] DBG_OUT_10_out; + wire [17:0] DBG_OUT_11_out; + wire [17:0] DBG_OUT_12_out; + wire [17:0] DBG_OUT_13_out; + wire [17:0] DBG_OUT_14_out; + wire [17:0] DBG_OUT_15_out; + wire [1:0] AXI_00_BRESP_out; + wire [1:0] AXI_00_DFI_AW_AERR_N_out; + wire [1:0] AXI_00_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_00_RRESP_out; + wire [1:0] AXI_01_BRESP_out; + wire [1:0] AXI_01_DFI_AW_AERR_N_out; + wire [1:0] AXI_01_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_01_RRESP_out; + wire [1:0] AXI_02_BRESP_out; + wire [1:0] AXI_02_DFI_AW_AERR_N_out; + wire [1:0] AXI_02_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_02_RRESP_out; + wire [1:0] AXI_03_BRESP_out; + wire [1:0] AXI_03_DFI_AW_AERR_N_out; + wire [1:0] AXI_03_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_03_RRESP_out; + wire [1:0] AXI_04_BRESP_out; + wire [1:0] AXI_04_DFI_AW_AERR_N_out; + wire [1:0] AXI_04_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_04_RRESP_out; + wire [1:0] AXI_05_BRESP_out; + wire [1:0] AXI_05_DFI_AW_AERR_N_out; + wire [1:0] AXI_05_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_05_RRESP_out; + wire [1:0] AXI_06_BRESP_out; + wire [1:0] AXI_06_DFI_AW_AERR_N_out; + wire [1:0] AXI_06_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_06_RRESP_out; + wire [1:0] AXI_07_BRESP_out; + wire [1:0] AXI_07_DFI_AW_AERR_N_out; + wire [1:0] AXI_07_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_07_RRESP_out; + wire [1:0] AXI_08_BRESP_out; + wire [1:0] AXI_08_DFI_AW_AERR_N_out; + wire [1:0] AXI_08_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_08_RRESP_out; + wire [1:0] AXI_09_BRESP_out; + wire [1:0] AXI_09_DFI_AW_AERR_N_out; + wire [1:0] AXI_09_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_09_RRESP_out; + wire [1:0] AXI_10_BRESP_out; + wire [1:0] AXI_10_DFI_AW_AERR_N_out; + wire [1:0] AXI_10_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_10_RRESP_out; + wire [1:0] AXI_11_BRESP_out; + wire [1:0] AXI_11_DFI_AW_AERR_N_out; + wire [1:0] AXI_11_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_11_RRESP_out; + wire [1:0] AXI_12_BRESP_out; + wire [1:0] AXI_12_DFI_AW_AERR_N_out; + wire [1:0] AXI_12_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_12_RRESP_out; + wire [1:0] AXI_13_BRESP_out; + wire [1:0] AXI_13_DFI_AW_AERR_N_out; + wire [1:0] AXI_13_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_13_RRESP_out; + wire [1:0] AXI_14_BRESP_out; + wire [1:0] AXI_14_DFI_AW_AERR_N_out; + wire [1:0] AXI_14_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_14_RRESP_out; + wire [1:0] AXI_15_BRESP_out; + wire [1:0] AXI_15_DFI_AW_AERR_N_out; + wire [1:0] AXI_15_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_15_RRESP_out; + wire [1:0] DLL_SCAN_OUT_00_out; + wire [1:0] IO_SCAN_OUT_00_out; + wire [1:0] MC_SCAN_OUT_00_out; + wire [1:0] MC_SCAN_OUT_01_out; + wire [1:0] MC_SCAN_OUT_02_out; + wire [1:0] MC_SCAN_OUT_03_out; + wire [1:0] MC_SCAN_OUT_04_out; + wire [1:0] MC_SCAN_OUT_05_out; + wire [1:0] MC_SCAN_OUT_06_out; + wire [1:0] MC_SCAN_OUT_07_out; + wire [1:0] PHY_SCAN_OUT_00_out; + wire [1:0] STATUS_00_out; + wire [1:0] STATUS_01_out; + wire [1:0] STATUS_02_out; + wire [1:0] STATUS_03_out; + wire [1:0] STATUS_04_out; + wire [1:0] STATUS_05_out; + wire [1:0] STATUS_06_out; + wire [1:0] STATUS_07_out; + wire [1:0] SW_SCAN_OUT_00_out; + wire [1:0] SW_SCAN_OUT_01_out; + wire [1:0] SW_SCAN_OUT_02_out; + wire [1:0] SW_SCAN_OUT_03_out; + wire [20:0] AXI_00_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_01_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_02_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_03_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_04_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_05_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_06_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_07_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_08_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_09_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_10_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_11_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_12_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_13_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_14_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_15_DFI_DW_RDDATA_DBI_out; + wire [255:0] AXI_00_RDATA_out; + wire [255:0] AXI_01_RDATA_out; + wire [255:0] AXI_02_RDATA_out; + wire [255:0] AXI_03_RDATA_out; + wire [255:0] AXI_04_RDATA_out; + wire [255:0] AXI_05_RDATA_out; + wire [255:0] AXI_06_RDATA_out; + wire [255:0] AXI_07_RDATA_out; + wire [255:0] AXI_08_RDATA_out; + wire [255:0] AXI_09_RDATA_out; + wire [255:0] AXI_10_RDATA_out; + wire [255:0] AXI_11_RDATA_out; + wire [255:0] AXI_12_RDATA_out; + wire [255:0] AXI_13_RDATA_out; + wire [255:0] AXI_14_RDATA_out; + wire [255:0] AXI_15_RDATA_out; + wire [2:0] DRAM_0_STAT_TEMP_out; + wire [31:0] APB_0_PRDATA_out; + wire [31:0] AXI_00_RDATA_PARITY_out; + wire [31:0] AXI_01_RDATA_PARITY_out; + wire [31:0] AXI_02_RDATA_PARITY_out; + wire [31:0] AXI_03_RDATA_PARITY_out; + wire [31:0] AXI_04_RDATA_PARITY_out; + wire [31:0] AXI_05_RDATA_PARITY_out; + wire [31:0] AXI_06_RDATA_PARITY_out; + wire [31:0] AXI_07_RDATA_PARITY_out; + wire [31:0] AXI_08_RDATA_PARITY_out; + wire [31:0] AXI_09_RDATA_PARITY_out; + wire [31:0] AXI_10_RDATA_PARITY_out; + wire [31:0] AXI_11_RDATA_PARITY_out; + wire [31:0] AXI_12_RDATA_PARITY_out; + wire [31:0] AXI_13_RDATA_PARITY_out; + wire [31:0] AXI_14_RDATA_PARITY_out; + wire [31:0] AXI_15_RDATA_PARITY_out; + wire [5:0] AXI_00_BID_out; + wire [5:0] AXI_00_MC_STATUS_out; + wire [5:0] AXI_00_RID_out; + wire [5:0] AXI_01_BID_out; + wire [5:0] AXI_01_RID_out; + wire [5:0] AXI_02_BID_out; + wire [5:0] AXI_02_MC_STATUS_out; + wire [5:0] AXI_02_RID_out; + wire [5:0] AXI_03_BID_out; + wire [5:0] AXI_03_RID_out; + wire [5:0] AXI_04_BID_out; + wire [5:0] AXI_04_MC_STATUS_out; + wire [5:0] AXI_04_RID_out; + wire [5:0] AXI_05_BID_out; + wire [5:0] AXI_05_RID_out; + wire [5:0] AXI_06_BID_out; + wire [5:0] AXI_06_MC_STATUS_out; + wire [5:0] AXI_06_RID_out; + wire [5:0] AXI_07_BID_out; + wire [5:0] AXI_07_RID_out; + wire [5:0] AXI_08_BID_out; + wire [5:0] AXI_08_MC_STATUS_out; + wire [5:0] AXI_08_RID_out; + wire [5:0] AXI_09_BID_out; + wire [5:0] AXI_09_RID_out; + wire [5:0] AXI_10_BID_out; + wire [5:0] AXI_10_MC_STATUS_out; + wire [5:0] AXI_10_RID_out; + wire [5:0] AXI_11_BID_out; + wire [5:0] AXI_11_RID_out; + wire [5:0] AXI_12_BID_out; + wire [5:0] AXI_12_MC_STATUS_out; + wire [5:0] AXI_12_RID_out; + wire [5:0] AXI_13_BID_out; + wire [5:0] AXI_13_RID_out; + wire [5:0] AXI_14_BID_out; + wire [5:0] AXI_14_MC_STATUS_out; + wire [5:0] AXI_14_RID_out; + wire [5:0] AXI_15_BID_out; + wire [5:0] AXI_15_RID_out; + wire [7:0] AXI_00_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_00_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_00_PHY_STATUS_out; + wire [7:0] AXI_01_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_01_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_02_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_02_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_02_PHY_STATUS_out; + wire [7:0] AXI_03_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_03_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_04_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_04_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_04_PHY_STATUS_out; + wire [7:0] AXI_05_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_05_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_06_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_06_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_06_PHY_STATUS_out; + wire [7:0] AXI_07_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_07_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_08_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_08_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_08_PHY_STATUS_out; + wire [7:0] AXI_09_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_09_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_10_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_10_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_10_PHY_STATUS_out; + wire [7:0] AXI_11_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_11_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_12_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_12_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_12_PHY_STATUS_out; + wire [7:0] AXI_13_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_13_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_14_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_14_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_14_PHY_STATUS_out; + wire [7:0] AXI_15_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_15_DFI_DW_RDDATA_DERR_out; + wire [7:0] BLI_SCAN_OUT_00_out; + wire [7:0] BLI_SCAN_OUT_01_out; + wire [7:0] BLI_SCAN_OUT_02_out; + wire [7:0] BLI_SCAN_OUT_03_out; + wire [7:0] BLI_SCAN_OUT_04_out; + wire [7:0] BLI_SCAN_OUT_05_out; + wire [7:0] BLI_SCAN_OUT_06_out; + wire [7:0] BLI_SCAN_OUT_07_out; + wire [7:0] BLI_SCAN_OUT_08_out; + wire [7:0] BLI_SCAN_OUT_09_out; + wire [7:0] BLI_SCAN_OUT_10_out; + wire [7:0] BLI_SCAN_OUT_11_out; + wire [7:0] BLI_SCAN_OUT_12_out; + wire [7:0] BLI_SCAN_OUT_13_out; + wire [7:0] BLI_SCAN_OUT_14_out; + wire [7:0] BLI_SCAN_OUT_15_out; + + wire ANALOG_HBM_SEL_00_in; + wire APB_0_PCLK_in; + wire APB_0_PENABLE_in; + wire APB_0_PRESET_N_in; + wire APB_0_PSEL_in; + wire APB_0_PWRITE_in; + wire AXI_00_ACLK_in; + wire AXI_00_ARESET_N_in; + wire AXI_00_ARVALID_in; + wire AXI_00_AWVALID_in; + wire AXI_00_BREADY_in; + wire AXI_00_DFI_LP_PWR_X_REQ_in; + wire AXI_00_RREADY_in; + wire AXI_00_WLAST_in; + wire AXI_00_WVALID_in; + wire AXI_01_ACLK_in; + wire AXI_01_ARESET_N_in; + wire AXI_01_ARVALID_in; + wire AXI_01_AWVALID_in; + wire AXI_01_BREADY_in; + wire AXI_01_DFI_LP_PWR_X_REQ_in; + wire AXI_01_RREADY_in; + wire AXI_01_WLAST_in; + wire AXI_01_WVALID_in; + wire AXI_02_ACLK_in; + wire AXI_02_ARESET_N_in; + wire AXI_02_ARVALID_in; + wire AXI_02_AWVALID_in; + wire AXI_02_BREADY_in; + wire AXI_02_DFI_LP_PWR_X_REQ_in; + wire AXI_02_RREADY_in; + wire AXI_02_WLAST_in; + wire AXI_02_WVALID_in; + wire AXI_03_ACLK_in; + wire AXI_03_ARESET_N_in; + wire AXI_03_ARVALID_in; + wire AXI_03_AWVALID_in; + wire AXI_03_BREADY_in; + wire AXI_03_DFI_LP_PWR_X_REQ_in; + wire AXI_03_RREADY_in; + wire AXI_03_WLAST_in; + wire AXI_03_WVALID_in; + wire AXI_04_ACLK_in; + wire AXI_04_ARESET_N_in; + wire AXI_04_ARVALID_in; + wire AXI_04_AWVALID_in; + wire AXI_04_BREADY_in; + wire AXI_04_DFI_LP_PWR_X_REQ_in; + wire AXI_04_RREADY_in; + wire AXI_04_WLAST_in; + wire AXI_04_WVALID_in; + wire AXI_05_ACLK_in; + wire AXI_05_ARESET_N_in; + wire AXI_05_ARVALID_in; + wire AXI_05_AWVALID_in; + wire AXI_05_BREADY_in; + wire AXI_05_DFI_LP_PWR_X_REQ_in; + wire AXI_05_RREADY_in; + wire AXI_05_WLAST_in; + wire AXI_05_WVALID_in; + wire AXI_06_ACLK_in; + wire AXI_06_ARESET_N_in; + wire AXI_06_ARVALID_in; + wire AXI_06_AWVALID_in; + wire AXI_06_BREADY_in; + wire AXI_06_DFI_LP_PWR_X_REQ_in; + wire AXI_06_RREADY_in; + wire AXI_06_WLAST_in; + wire AXI_06_WVALID_in; + wire AXI_07_ACLK_in; + wire AXI_07_ARESET_N_in; + wire AXI_07_ARVALID_in; + wire AXI_07_AWVALID_in; + wire AXI_07_BREADY_in; + wire AXI_07_DFI_LP_PWR_X_REQ_in; + wire AXI_07_RREADY_in; + wire AXI_07_WLAST_in; + wire AXI_07_WVALID_in; + wire AXI_08_ACLK_in; + wire AXI_08_ARESET_N_in; + wire AXI_08_ARVALID_in; + wire AXI_08_AWVALID_in; + wire AXI_08_BREADY_in; + wire AXI_08_DFI_LP_PWR_X_REQ_in; + wire AXI_08_RREADY_in; + wire AXI_08_WLAST_in; + wire AXI_08_WVALID_in; + wire AXI_09_ACLK_in; + wire AXI_09_ARESET_N_in; + wire AXI_09_ARVALID_in; + wire AXI_09_AWVALID_in; + wire AXI_09_BREADY_in; + wire AXI_09_DFI_LP_PWR_X_REQ_in; + wire AXI_09_RREADY_in; + wire AXI_09_WLAST_in; + wire AXI_09_WVALID_in; + wire AXI_10_ACLK_in; + wire AXI_10_ARESET_N_in; + wire AXI_10_ARVALID_in; + wire AXI_10_AWVALID_in; + wire AXI_10_BREADY_in; + wire AXI_10_DFI_LP_PWR_X_REQ_in; + wire AXI_10_RREADY_in; + wire AXI_10_WLAST_in; + wire AXI_10_WVALID_in; + wire AXI_11_ACLK_in; + wire AXI_11_ARESET_N_in; + wire AXI_11_ARVALID_in; + wire AXI_11_AWVALID_in; + wire AXI_11_BREADY_in; + wire AXI_11_DFI_LP_PWR_X_REQ_in; + wire AXI_11_RREADY_in; + wire AXI_11_WLAST_in; + wire AXI_11_WVALID_in; + wire AXI_12_ACLK_in; + wire AXI_12_ARESET_N_in; + wire AXI_12_ARVALID_in; + wire AXI_12_AWVALID_in; + wire AXI_12_BREADY_in; + wire AXI_12_DFI_LP_PWR_X_REQ_in; + wire AXI_12_RREADY_in; + wire AXI_12_WLAST_in; + wire AXI_12_WVALID_in; + wire AXI_13_ACLK_in; + wire AXI_13_ARESET_N_in; + wire AXI_13_ARVALID_in; + wire AXI_13_AWVALID_in; + wire AXI_13_BREADY_in; + wire AXI_13_DFI_LP_PWR_X_REQ_in; + wire AXI_13_RREADY_in; + wire AXI_13_WLAST_in; + wire AXI_13_WVALID_in; + wire AXI_14_ACLK_in; + wire AXI_14_ARESET_N_in; + wire AXI_14_ARVALID_in; + wire AXI_14_AWVALID_in; + wire AXI_14_BREADY_in; + wire AXI_14_DFI_LP_PWR_X_REQ_in; + wire AXI_14_RREADY_in; + wire AXI_14_WLAST_in; + wire AXI_14_WVALID_in; + wire AXI_15_ACLK_in; + wire AXI_15_ARESET_N_in; + wire AXI_15_ARVALID_in; + wire AXI_15_AWVALID_in; + wire AXI_15_BREADY_in; + wire AXI_15_DFI_LP_PWR_X_REQ_in; + wire AXI_15_RREADY_in; + wire AXI_15_WLAST_in; + wire AXI_15_WVALID_in; + wire BLI_SCAN_ENABLE_00_in; + wire BLI_SCAN_ENABLE_01_in; + wire BLI_SCAN_ENABLE_02_in; + wire BLI_SCAN_ENABLE_03_in; + wire BLI_SCAN_ENABLE_04_in; + wire BLI_SCAN_ENABLE_05_in; + wire BLI_SCAN_ENABLE_06_in; + wire BLI_SCAN_ENABLE_07_in; + wire BLI_SCAN_ENABLE_08_in; + wire BLI_SCAN_ENABLE_09_in; + wire BLI_SCAN_ENABLE_10_in; + wire BLI_SCAN_ENABLE_11_in; + wire BLI_SCAN_ENABLE_12_in; + wire BLI_SCAN_ENABLE_13_in; + wire BLI_SCAN_ENABLE_14_in; + wire BLI_SCAN_ENABLE_15_in; + wire BSCAN_DRCK_in; + wire BSCAN_TCK_in; + wire DLL_SCAN_CK_00_in; + wire DLL_SCAN_ENABLE_00_in; + wire DLL_SCAN_MODE_00_in; + wire DLL_SCAN_RST_N_00_in; + wire HBM_REF_CLK_in; + wire IO_SCAN_CK_00_in; + wire IO_SCAN_ENABLE_00_in; + wire IO_SCAN_MODE_00_in; + wire IO_SCAN_RST_N_00_in; + wire MBIST_EN_00_in; + wire MBIST_EN_01_in; + wire MBIST_EN_02_in; + wire MBIST_EN_03_in; + wire MBIST_EN_04_in; + wire MBIST_EN_05_in; + wire MBIST_EN_06_in; + wire MBIST_EN_07_in; + wire MC_SCAN_CK_00_in; + wire MC_SCAN_CK_01_in; + wire MC_SCAN_CK_02_in; + wire MC_SCAN_CK_03_in; + wire MC_SCAN_CK_04_in; + wire MC_SCAN_CK_05_in; + wire MC_SCAN_CK_06_in; + wire MC_SCAN_CK_07_in; + wire MC_SCAN_ENABLE_00_in; + wire MC_SCAN_ENABLE_01_in; + wire MC_SCAN_ENABLE_02_in; + wire MC_SCAN_ENABLE_03_in; + wire MC_SCAN_ENABLE_04_in; + wire MC_SCAN_ENABLE_05_in; + wire MC_SCAN_ENABLE_06_in; + wire MC_SCAN_ENABLE_07_in; + wire MC_SCAN_MODE_00_in; + wire MC_SCAN_MODE_01_in; + wire MC_SCAN_MODE_02_in; + wire MC_SCAN_MODE_03_in; + wire MC_SCAN_MODE_04_in; + wire MC_SCAN_MODE_05_in; + wire MC_SCAN_MODE_06_in; + wire MC_SCAN_MODE_07_in; + wire MC_SCAN_RST_N_00_in; + wire MC_SCAN_RST_N_01_in; + wire MC_SCAN_RST_N_02_in; + wire MC_SCAN_RST_N_03_in; + wire MC_SCAN_RST_N_04_in; + wire MC_SCAN_RST_N_05_in; + wire MC_SCAN_RST_N_06_in; + wire MC_SCAN_RST_N_07_in; + wire PHY_SCAN_CK_00_in; + wire PHY_SCAN_ENABLE_00_in; + wire PHY_SCAN_MODE_00_in; + wire PHY_SCAN_RST_N_00_in; + wire SW_SCAN_CK_00_in; + wire SW_SCAN_ENABLE_00_in; + wire SW_SCAN_MODE_00_in; + wire SW_SCAN_RST_N_00_in; + wire [1:0] AXI_00_ARBURST_in; + wire [1:0] AXI_00_AWBURST_in; + wire [1:0] AXI_01_ARBURST_in; + wire [1:0] AXI_01_AWBURST_in; + wire [1:0] AXI_02_ARBURST_in; + wire [1:0] AXI_02_AWBURST_in; + wire [1:0] AXI_03_ARBURST_in; + wire [1:0] AXI_03_AWBURST_in; + wire [1:0] AXI_04_ARBURST_in; + wire [1:0] AXI_04_AWBURST_in; + wire [1:0] AXI_05_ARBURST_in; + wire [1:0] AXI_05_AWBURST_in; + wire [1:0] AXI_06_ARBURST_in; + wire [1:0] AXI_06_AWBURST_in; + wire [1:0] AXI_07_ARBURST_in; + wire [1:0] AXI_07_AWBURST_in; + wire [1:0] AXI_08_ARBURST_in; + wire [1:0] AXI_08_AWBURST_in; + wire [1:0] AXI_09_ARBURST_in; + wire [1:0] AXI_09_AWBURST_in; + wire [1:0] AXI_10_ARBURST_in; + wire [1:0] AXI_10_AWBURST_in; + wire [1:0] AXI_11_ARBURST_in; + wire [1:0] AXI_11_AWBURST_in; + wire [1:0] AXI_12_ARBURST_in; + wire [1:0] AXI_12_AWBURST_in; + wire [1:0] AXI_13_ARBURST_in; + wire [1:0] AXI_13_AWBURST_in; + wire [1:0] AXI_14_ARBURST_in; + wire [1:0] AXI_14_AWBURST_in; + wire [1:0] AXI_15_ARBURST_in; + wire [1:0] AXI_15_AWBURST_in; + wire [1:0] DLL_SCAN_IN_00_in; + wire [1:0] IO_SCAN_IN_00_in; + wire [1:0] MC_SCAN_IN_00_in; + wire [1:0] MC_SCAN_IN_01_in; + wire [1:0] MC_SCAN_IN_02_in; + wire [1:0] MC_SCAN_IN_03_in; + wire [1:0] MC_SCAN_IN_04_in; + wire [1:0] MC_SCAN_IN_05_in; + wire [1:0] MC_SCAN_IN_06_in; + wire [1:0] MC_SCAN_IN_07_in; + wire [1:0] PHY_SCAN_IN_00_in; + wire [1:0] SW_SCAN_IN_00_in; + wire [1:0] SW_SCAN_IN_01_in; + wire [1:0] SW_SCAN_IN_02_in; + wire [1:0] SW_SCAN_IN_03_in; + wire [21:0] APB_0_PADDR_in; + wire [23:0] DBG_IN_00_in; + wire [23:0] DBG_IN_01_in; + wire [23:0] DBG_IN_02_in; + wire [23:0] DBG_IN_03_in; + wire [23:0] DBG_IN_04_in; + wire [23:0] DBG_IN_05_in; + wire [23:0] DBG_IN_06_in; + wire [23:0] DBG_IN_07_in; + wire [23:0] DBG_IN_08_in; + wire [23:0] DBG_IN_09_in; + wire [23:0] DBG_IN_10_in; + wire [23:0] DBG_IN_11_in; + wire [23:0] DBG_IN_12_in; + wire [23:0] DBG_IN_13_in; + wire [23:0] DBG_IN_14_in; + wire [23:0] DBG_IN_15_in; + wire [255:0] AXI_00_WDATA_in; + wire [255:0] AXI_01_WDATA_in; + wire [255:0] AXI_02_WDATA_in; + wire [255:0] AXI_03_WDATA_in; + wire [255:0] AXI_04_WDATA_in; + wire [255:0] AXI_05_WDATA_in; + wire [255:0] AXI_06_WDATA_in; + wire [255:0] AXI_07_WDATA_in; + wire [255:0] AXI_08_WDATA_in; + wire [255:0] AXI_09_WDATA_in; + wire [255:0] AXI_10_WDATA_in; + wire [255:0] AXI_11_WDATA_in; + wire [255:0] AXI_12_WDATA_in; + wire [255:0] AXI_13_WDATA_in; + wire [255:0] AXI_14_WDATA_in; + wire [255:0] AXI_15_WDATA_in; + wire [2:0] AXI_00_ARSIZE_in; + wire [2:0] AXI_00_AWSIZE_in; + wire [2:0] AXI_01_ARSIZE_in; + wire [2:0] AXI_01_AWSIZE_in; + wire [2:0] AXI_02_ARSIZE_in; + wire [2:0] AXI_02_AWSIZE_in; + wire [2:0] AXI_03_ARSIZE_in; + wire [2:0] AXI_03_AWSIZE_in; + wire [2:0] AXI_04_ARSIZE_in; + wire [2:0] AXI_04_AWSIZE_in; + wire [2:0] AXI_05_ARSIZE_in; + wire [2:0] AXI_05_AWSIZE_in; + wire [2:0] AXI_06_ARSIZE_in; + wire [2:0] AXI_06_AWSIZE_in; + wire [2:0] AXI_07_ARSIZE_in; + wire [2:0] AXI_07_AWSIZE_in; + wire [2:0] AXI_08_ARSIZE_in; + wire [2:0] AXI_08_AWSIZE_in; + wire [2:0] AXI_09_ARSIZE_in; + wire [2:0] AXI_09_AWSIZE_in; + wire [2:0] AXI_10_ARSIZE_in; + wire [2:0] AXI_10_AWSIZE_in; + wire [2:0] AXI_11_ARSIZE_in; + wire [2:0] AXI_11_AWSIZE_in; + wire [2:0] AXI_12_ARSIZE_in; + wire [2:0] AXI_12_AWSIZE_in; + wire [2:0] AXI_13_ARSIZE_in; + wire [2:0] AXI_13_AWSIZE_in; + wire [2:0] AXI_14_ARSIZE_in; + wire [2:0] AXI_14_AWSIZE_in; + wire [2:0] AXI_15_ARSIZE_in; + wire [2:0] AXI_15_AWSIZE_in; + wire [31:0] APB_0_PWDATA_in; + wire [31:0] AXI_00_WDATA_PARITY_in; + wire [31:0] AXI_00_WSTRB_in; + wire [31:0] AXI_01_WDATA_PARITY_in; + wire [31:0] AXI_01_WSTRB_in; + wire [31:0] AXI_02_WDATA_PARITY_in; + wire [31:0] AXI_02_WSTRB_in; + wire [31:0] AXI_03_WDATA_PARITY_in; + wire [31:0] AXI_03_WSTRB_in; + wire [31:0] AXI_04_WDATA_PARITY_in; + wire [31:0] AXI_04_WSTRB_in; + wire [31:0] AXI_05_WDATA_PARITY_in; + wire [31:0] AXI_05_WSTRB_in; + wire [31:0] AXI_06_WDATA_PARITY_in; + wire [31:0] AXI_06_WSTRB_in; + wire [31:0] AXI_07_WDATA_PARITY_in; + wire [31:0] AXI_07_WSTRB_in; + wire [31:0] AXI_08_WDATA_PARITY_in; + wire [31:0] AXI_08_WSTRB_in; + wire [31:0] AXI_09_WDATA_PARITY_in; + wire [31:0] AXI_09_WSTRB_in; + wire [31:0] AXI_10_WDATA_PARITY_in; + wire [31:0] AXI_10_WSTRB_in; + wire [31:0] AXI_11_WDATA_PARITY_in; + wire [31:0] AXI_11_WSTRB_in; + wire [31:0] AXI_12_WDATA_PARITY_in; + wire [31:0] AXI_12_WSTRB_in; + wire [31:0] AXI_13_WDATA_PARITY_in; + wire [31:0] AXI_13_WSTRB_in; + wire [31:0] AXI_14_WDATA_PARITY_in; + wire [31:0] AXI_14_WSTRB_in; + wire [31:0] AXI_15_WDATA_PARITY_in; + wire [31:0] AXI_15_WSTRB_in; + wire [36:0] AXI_00_ARADDR_in; + wire [36:0] AXI_00_AWADDR_in; + wire [36:0] AXI_01_ARADDR_in; + wire [36:0] AXI_01_AWADDR_in; + wire [36:0] AXI_02_ARADDR_in; + wire [36:0] AXI_02_AWADDR_in; + wire [36:0] AXI_03_ARADDR_in; + wire [36:0] AXI_03_AWADDR_in; + wire [36:0] AXI_04_ARADDR_in; + wire [36:0] AXI_04_AWADDR_in; + wire [36:0] AXI_05_ARADDR_in; + wire [36:0] AXI_05_AWADDR_in; + wire [36:0] AXI_06_ARADDR_in; + wire [36:0] AXI_06_AWADDR_in; + wire [36:0] AXI_07_ARADDR_in; + wire [36:0] AXI_07_AWADDR_in; + wire [36:0] AXI_08_ARADDR_in; + wire [36:0] AXI_08_AWADDR_in; + wire [36:0] AXI_09_ARADDR_in; + wire [36:0] AXI_09_AWADDR_in; + wire [36:0] AXI_10_ARADDR_in; + wire [36:0] AXI_10_AWADDR_in; + wire [36:0] AXI_11_ARADDR_in; + wire [36:0] AXI_11_AWADDR_in; + wire [36:0] AXI_12_ARADDR_in; + wire [36:0] AXI_12_AWADDR_in; + wire [36:0] AXI_13_ARADDR_in; + wire [36:0] AXI_13_AWADDR_in; + wire [36:0] AXI_14_ARADDR_in; + wire [36:0] AXI_14_AWADDR_in; + wire [36:0] AXI_15_ARADDR_in; + wire [36:0] AXI_15_AWADDR_in; + wire [3:0] AXI_00_ARLEN_in; + wire [3:0] AXI_00_AWLEN_in; + wire [3:0] AXI_01_ARLEN_in; + wire [3:0] AXI_01_AWLEN_in; + wire [3:0] AXI_02_ARLEN_in; + wire [3:0] AXI_02_AWLEN_in; + wire [3:0] AXI_03_ARLEN_in; + wire [3:0] AXI_03_AWLEN_in; + wire [3:0] AXI_04_ARLEN_in; + wire [3:0] AXI_04_AWLEN_in; + wire [3:0] AXI_05_ARLEN_in; + wire [3:0] AXI_05_AWLEN_in; + wire [3:0] AXI_06_ARLEN_in; + wire [3:0] AXI_06_AWLEN_in; + wire [3:0] AXI_07_ARLEN_in; + wire [3:0] AXI_07_AWLEN_in; + wire [3:0] AXI_08_ARLEN_in; + wire [3:0] AXI_08_AWLEN_in; + wire [3:0] AXI_09_ARLEN_in; + wire [3:0] AXI_09_AWLEN_in; + wire [3:0] AXI_10_ARLEN_in; + wire [3:0] AXI_10_AWLEN_in; + wire [3:0] AXI_11_ARLEN_in; + wire [3:0] AXI_11_AWLEN_in; + wire [3:0] AXI_12_ARLEN_in; + wire [3:0] AXI_12_AWLEN_in; + wire [3:0] AXI_13_ARLEN_in; + wire [3:0] AXI_13_AWLEN_in; + wire [3:0] AXI_14_ARLEN_in; + wire [3:0] AXI_14_AWLEN_in; + wire [3:0] AXI_15_ARLEN_in; + wire [3:0] AXI_15_AWLEN_in; + wire [5:0] AXI_00_ARID_in; + wire [5:0] AXI_00_AWID_in; + wire [5:0] AXI_01_ARID_in; + wire [5:0] AXI_01_AWID_in; + wire [5:0] AXI_02_ARID_in; + wire [5:0] AXI_02_AWID_in; + wire [5:0] AXI_03_ARID_in; + wire [5:0] AXI_03_AWID_in; + wire [5:0] AXI_04_ARID_in; + wire [5:0] AXI_04_AWID_in; + wire [5:0] AXI_05_ARID_in; + wire [5:0] AXI_05_AWID_in; + wire [5:0] AXI_06_ARID_in; + wire [5:0] AXI_06_AWID_in; + wire [5:0] AXI_07_ARID_in; + wire [5:0] AXI_07_AWID_in; + wire [5:0] AXI_08_ARID_in; + wire [5:0] AXI_08_AWID_in; + wire [5:0] AXI_09_ARID_in; + wire [5:0] AXI_09_AWID_in; + wire [5:0] AXI_10_ARID_in; + wire [5:0] AXI_10_AWID_in; + wire [5:0] AXI_11_ARID_in; + wire [5:0] AXI_11_AWID_in; + wire [5:0] AXI_12_ARID_in; + wire [5:0] AXI_12_AWID_in; + wire [5:0] AXI_13_ARID_in; + wire [5:0] AXI_13_AWID_in; + wire [5:0] AXI_14_ARID_in; + wire [5:0] AXI_14_AWID_in; + wire [5:0] AXI_15_ARID_in; + wire [5:0] AXI_15_AWID_in; + wire [7:0] BLI_SCAN_IN_00_in; + wire [7:0] BLI_SCAN_IN_01_in; + wire [7:0] BLI_SCAN_IN_02_in; + wire [7:0] BLI_SCAN_IN_03_in; + wire [7:0] BLI_SCAN_IN_04_in; + wire [7:0] BLI_SCAN_IN_05_in; + wire [7:0] BLI_SCAN_IN_06_in; + wire [7:0] BLI_SCAN_IN_07_in; + wire [7:0] BLI_SCAN_IN_08_in; + wire [7:0] BLI_SCAN_IN_09_in; + wire [7:0] BLI_SCAN_IN_10_in; + wire [7:0] BLI_SCAN_IN_11_in; + wire [7:0] BLI_SCAN_IN_12_in; + wire [7:0] BLI_SCAN_IN_13_in; + wire [7:0] BLI_SCAN_IN_14_in; + wire [7:0] BLI_SCAN_IN_15_in; + + assign APB_0_PRDATA = APB_0_PRDATA_out; + assign APB_0_PREADY = APB_0_PREADY_out; + assign APB_0_PSLVERR = APB_0_PSLVERR_out; + assign AXI_00_ARREADY = AXI_00_ARREADY_out; + assign AXI_00_AWREADY = AXI_00_AWREADY_out; + assign AXI_00_BID = AXI_00_BID_out; + assign AXI_00_BRESP = AXI_00_BRESP_out; + assign AXI_00_BVALID = AXI_00_BVALID_out; + assign AXI_00_DFI_AW_AERR_N = AXI_00_DFI_AW_AERR_N_out; + assign AXI_00_DFI_CLK_BUF = AXI_00_DFI_CLK_BUF_out; + assign AXI_00_DFI_DBI_BYTE_DISABLE = AXI_00_DFI_DBI_BYTE_DISABLE_out; + assign AXI_00_DFI_DW_RDDATA_DBI = AXI_00_DFI_DW_RDDATA_DBI_out; + assign AXI_00_DFI_DW_RDDATA_DERR = AXI_00_DFI_DW_RDDATA_DERR_out; + assign AXI_00_DFI_DW_RDDATA_VALID = AXI_00_DFI_DW_RDDATA_VALID_out; + assign AXI_00_DFI_INIT_COMPLETE = AXI_00_DFI_INIT_COMPLETE_out; + assign AXI_00_DFI_PHYUPD_REQ = AXI_00_DFI_PHYUPD_REQ_out; + assign AXI_00_DFI_PHY_LP_STATE = AXI_00_DFI_PHY_LP_STATE_out; + assign AXI_00_DFI_RST_N_BUF = AXI_00_DFI_RST_N_BUF_out; + assign AXI_00_MC_STATUS = AXI_00_MC_STATUS_out; + assign AXI_00_PHY_STATUS = AXI_00_PHY_STATUS_out; + assign AXI_00_RDATA = AXI_00_RDATA_out; + assign AXI_00_RDATA_PARITY = AXI_00_RDATA_PARITY_out; + assign AXI_00_RID = AXI_00_RID_out; + assign AXI_00_RLAST = AXI_00_RLAST_out; + assign AXI_00_RRESP = AXI_00_RRESP_out; + assign AXI_00_RVALID = AXI_00_RVALID_out; + assign AXI_00_WREADY = AXI_00_WREADY_out; + assign AXI_01_ARREADY = AXI_01_ARREADY_out; + assign AXI_01_AWREADY = AXI_01_AWREADY_out; + assign AXI_01_BID = AXI_01_BID_out; + assign AXI_01_BRESP = AXI_01_BRESP_out; + assign AXI_01_BVALID = AXI_01_BVALID_out; + assign AXI_01_DFI_AW_AERR_N = AXI_01_DFI_AW_AERR_N_out; + assign AXI_01_DFI_CLK_BUF = AXI_01_DFI_CLK_BUF_out; + assign AXI_01_DFI_DBI_BYTE_DISABLE = AXI_01_DFI_DBI_BYTE_DISABLE_out; + assign AXI_01_DFI_DW_RDDATA_DBI = AXI_01_DFI_DW_RDDATA_DBI_out; + assign AXI_01_DFI_DW_RDDATA_DERR = AXI_01_DFI_DW_RDDATA_DERR_out; + assign AXI_01_DFI_DW_RDDATA_VALID = AXI_01_DFI_DW_RDDATA_VALID_out; + assign AXI_01_DFI_INIT_COMPLETE = AXI_01_DFI_INIT_COMPLETE_out; + assign AXI_01_DFI_PHYUPD_REQ = AXI_01_DFI_PHYUPD_REQ_out; + assign AXI_01_DFI_PHY_LP_STATE = AXI_01_DFI_PHY_LP_STATE_out; + assign AXI_01_DFI_RST_N_BUF = AXI_01_DFI_RST_N_BUF_out; + assign AXI_01_RDATA = AXI_01_RDATA_out; + assign AXI_01_RDATA_PARITY = AXI_01_RDATA_PARITY_out; + assign AXI_01_RID = AXI_01_RID_out; + assign AXI_01_RLAST = AXI_01_RLAST_out; + assign AXI_01_RRESP = AXI_01_RRESP_out; + assign AXI_01_RVALID = AXI_01_RVALID_out; + assign AXI_01_WREADY = AXI_01_WREADY_out; + assign AXI_02_ARREADY = AXI_02_ARREADY_out; + assign AXI_02_AWREADY = AXI_02_AWREADY_out; + assign AXI_02_BID = AXI_02_BID_out; + assign AXI_02_BRESP = AXI_02_BRESP_out; + assign AXI_02_BVALID = AXI_02_BVALID_out; + assign AXI_02_DFI_AW_AERR_N = AXI_02_DFI_AW_AERR_N_out; + assign AXI_02_DFI_CLK_BUF = AXI_02_DFI_CLK_BUF_out; + assign AXI_02_DFI_DBI_BYTE_DISABLE = AXI_02_DFI_DBI_BYTE_DISABLE_out; + assign AXI_02_DFI_DW_RDDATA_DBI = AXI_02_DFI_DW_RDDATA_DBI_out; + assign AXI_02_DFI_DW_RDDATA_DERR = AXI_02_DFI_DW_RDDATA_DERR_out; + assign AXI_02_DFI_DW_RDDATA_VALID = AXI_02_DFI_DW_RDDATA_VALID_out; + assign AXI_02_DFI_INIT_COMPLETE = AXI_02_DFI_INIT_COMPLETE_out; + assign AXI_02_DFI_PHYUPD_REQ = AXI_02_DFI_PHYUPD_REQ_out; + assign AXI_02_DFI_PHY_LP_STATE = AXI_02_DFI_PHY_LP_STATE_out; + assign AXI_02_DFI_RST_N_BUF = AXI_02_DFI_RST_N_BUF_out; + assign AXI_02_MC_STATUS = AXI_02_MC_STATUS_out; + assign AXI_02_PHY_STATUS = AXI_02_PHY_STATUS_out; + assign AXI_02_RDATA = AXI_02_RDATA_out; + assign AXI_02_RDATA_PARITY = AXI_02_RDATA_PARITY_out; + assign AXI_02_RID = AXI_02_RID_out; + assign AXI_02_RLAST = AXI_02_RLAST_out; + assign AXI_02_RRESP = AXI_02_RRESP_out; + assign AXI_02_RVALID = AXI_02_RVALID_out; + assign AXI_02_WREADY = AXI_02_WREADY_out; + assign AXI_03_ARREADY = AXI_03_ARREADY_out; + assign AXI_03_AWREADY = AXI_03_AWREADY_out; + assign AXI_03_BID = AXI_03_BID_out; + assign AXI_03_BRESP = AXI_03_BRESP_out; + assign AXI_03_BVALID = AXI_03_BVALID_out; + assign AXI_03_DFI_AW_AERR_N = AXI_03_DFI_AW_AERR_N_out; + assign AXI_03_DFI_CLK_BUF = AXI_03_DFI_CLK_BUF_out; + assign AXI_03_DFI_DBI_BYTE_DISABLE = AXI_03_DFI_DBI_BYTE_DISABLE_out; + assign AXI_03_DFI_DW_RDDATA_DBI = AXI_03_DFI_DW_RDDATA_DBI_out; + assign AXI_03_DFI_DW_RDDATA_DERR = AXI_03_DFI_DW_RDDATA_DERR_out; + assign AXI_03_DFI_DW_RDDATA_VALID = AXI_03_DFI_DW_RDDATA_VALID_out; + assign AXI_03_DFI_INIT_COMPLETE = AXI_03_DFI_INIT_COMPLETE_out; + assign AXI_03_DFI_PHYUPD_REQ = AXI_03_DFI_PHYUPD_REQ_out; + assign AXI_03_DFI_PHY_LP_STATE = AXI_03_DFI_PHY_LP_STATE_out; + assign AXI_03_DFI_RST_N_BUF = AXI_03_DFI_RST_N_BUF_out; + assign AXI_03_RDATA = AXI_03_RDATA_out; + assign AXI_03_RDATA_PARITY = AXI_03_RDATA_PARITY_out; + assign AXI_03_RID = AXI_03_RID_out; + assign AXI_03_RLAST = AXI_03_RLAST_out; + assign AXI_03_RRESP = AXI_03_RRESP_out; + assign AXI_03_RVALID = AXI_03_RVALID_out; + assign AXI_03_WREADY = AXI_03_WREADY_out; + assign AXI_04_ARREADY = AXI_04_ARREADY_out; + assign AXI_04_AWREADY = AXI_04_AWREADY_out; + assign AXI_04_BID = AXI_04_BID_out; + assign AXI_04_BRESP = AXI_04_BRESP_out; + assign AXI_04_BVALID = AXI_04_BVALID_out; + assign AXI_04_DFI_AW_AERR_N = AXI_04_DFI_AW_AERR_N_out; + assign AXI_04_DFI_CLK_BUF = AXI_04_DFI_CLK_BUF_out; + assign AXI_04_DFI_DBI_BYTE_DISABLE = AXI_04_DFI_DBI_BYTE_DISABLE_out; + assign AXI_04_DFI_DW_RDDATA_DBI = AXI_04_DFI_DW_RDDATA_DBI_out; + assign AXI_04_DFI_DW_RDDATA_DERR = AXI_04_DFI_DW_RDDATA_DERR_out; + assign AXI_04_DFI_DW_RDDATA_VALID = AXI_04_DFI_DW_RDDATA_VALID_out; + assign AXI_04_DFI_INIT_COMPLETE = AXI_04_DFI_INIT_COMPLETE_out; + assign AXI_04_DFI_PHYUPD_REQ = AXI_04_DFI_PHYUPD_REQ_out; + assign AXI_04_DFI_PHY_LP_STATE = AXI_04_DFI_PHY_LP_STATE_out; + assign AXI_04_DFI_RST_N_BUF = AXI_04_DFI_RST_N_BUF_out; + assign AXI_04_MC_STATUS = AXI_04_MC_STATUS_out; + assign AXI_04_PHY_STATUS = AXI_04_PHY_STATUS_out; + assign AXI_04_RDATA = AXI_04_RDATA_out; + assign AXI_04_RDATA_PARITY = AXI_04_RDATA_PARITY_out; + assign AXI_04_RID = AXI_04_RID_out; + assign AXI_04_RLAST = AXI_04_RLAST_out; + assign AXI_04_RRESP = AXI_04_RRESP_out; + assign AXI_04_RVALID = AXI_04_RVALID_out; + assign AXI_04_WREADY = AXI_04_WREADY_out; + assign AXI_05_ARREADY = AXI_05_ARREADY_out; + assign AXI_05_AWREADY = AXI_05_AWREADY_out; + assign AXI_05_BID = AXI_05_BID_out; + assign AXI_05_BRESP = AXI_05_BRESP_out; + assign AXI_05_BVALID = AXI_05_BVALID_out; + assign AXI_05_DFI_AW_AERR_N = AXI_05_DFI_AW_AERR_N_out; + assign AXI_05_DFI_CLK_BUF = AXI_05_DFI_CLK_BUF_out; + assign AXI_05_DFI_DBI_BYTE_DISABLE = AXI_05_DFI_DBI_BYTE_DISABLE_out; + assign AXI_05_DFI_DW_RDDATA_DBI = AXI_05_DFI_DW_RDDATA_DBI_out; + assign AXI_05_DFI_DW_RDDATA_DERR = AXI_05_DFI_DW_RDDATA_DERR_out; + assign AXI_05_DFI_DW_RDDATA_VALID = AXI_05_DFI_DW_RDDATA_VALID_out; + assign AXI_05_DFI_INIT_COMPLETE = AXI_05_DFI_INIT_COMPLETE_out; + assign AXI_05_DFI_PHYUPD_REQ = AXI_05_DFI_PHYUPD_REQ_out; + assign AXI_05_DFI_PHY_LP_STATE = AXI_05_DFI_PHY_LP_STATE_out; + assign AXI_05_DFI_RST_N_BUF = AXI_05_DFI_RST_N_BUF_out; + assign AXI_05_RDATA = AXI_05_RDATA_out; + assign AXI_05_RDATA_PARITY = AXI_05_RDATA_PARITY_out; + assign AXI_05_RID = AXI_05_RID_out; + assign AXI_05_RLAST = AXI_05_RLAST_out; + assign AXI_05_RRESP = AXI_05_RRESP_out; + assign AXI_05_RVALID = AXI_05_RVALID_out; + assign AXI_05_WREADY = AXI_05_WREADY_out; + assign AXI_06_ARREADY = AXI_06_ARREADY_out; + assign AXI_06_AWREADY = AXI_06_AWREADY_out; + assign AXI_06_BID = AXI_06_BID_out; + assign AXI_06_BRESP = AXI_06_BRESP_out; + assign AXI_06_BVALID = AXI_06_BVALID_out; + assign AXI_06_DFI_AW_AERR_N = AXI_06_DFI_AW_AERR_N_out; + assign AXI_06_DFI_CLK_BUF = AXI_06_DFI_CLK_BUF_out; + assign AXI_06_DFI_DBI_BYTE_DISABLE = AXI_06_DFI_DBI_BYTE_DISABLE_out; + assign AXI_06_DFI_DW_RDDATA_DBI = AXI_06_DFI_DW_RDDATA_DBI_out; + assign AXI_06_DFI_DW_RDDATA_DERR = AXI_06_DFI_DW_RDDATA_DERR_out; + assign AXI_06_DFI_DW_RDDATA_VALID = AXI_06_DFI_DW_RDDATA_VALID_out; + assign AXI_06_DFI_INIT_COMPLETE = AXI_06_DFI_INIT_COMPLETE_out; + assign AXI_06_DFI_PHYUPD_REQ = AXI_06_DFI_PHYUPD_REQ_out; + assign AXI_06_DFI_PHY_LP_STATE = AXI_06_DFI_PHY_LP_STATE_out; + assign AXI_06_DFI_RST_N_BUF = AXI_06_DFI_RST_N_BUF_out; + assign AXI_06_MC_STATUS = AXI_06_MC_STATUS_out; + assign AXI_06_PHY_STATUS = AXI_06_PHY_STATUS_out; + assign AXI_06_RDATA = AXI_06_RDATA_out; + assign AXI_06_RDATA_PARITY = AXI_06_RDATA_PARITY_out; + assign AXI_06_RID = AXI_06_RID_out; + assign AXI_06_RLAST = AXI_06_RLAST_out; + assign AXI_06_RRESP = AXI_06_RRESP_out; + assign AXI_06_RVALID = AXI_06_RVALID_out; + assign AXI_06_WREADY = AXI_06_WREADY_out; + assign AXI_07_ARREADY = AXI_07_ARREADY_out; + assign AXI_07_AWREADY = AXI_07_AWREADY_out; + assign AXI_07_BID = AXI_07_BID_out; + assign AXI_07_BRESP = AXI_07_BRESP_out; + assign AXI_07_BVALID = AXI_07_BVALID_out; + assign AXI_07_DFI_AW_AERR_N = AXI_07_DFI_AW_AERR_N_out; + assign AXI_07_DFI_CLK_BUF = AXI_07_DFI_CLK_BUF_out; + assign AXI_07_DFI_DBI_BYTE_DISABLE = AXI_07_DFI_DBI_BYTE_DISABLE_out; + assign AXI_07_DFI_DW_RDDATA_DBI = AXI_07_DFI_DW_RDDATA_DBI_out; + assign AXI_07_DFI_DW_RDDATA_DERR = AXI_07_DFI_DW_RDDATA_DERR_out; + assign AXI_07_DFI_DW_RDDATA_VALID = AXI_07_DFI_DW_RDDATA_VALID_out; + assign AXI_07_DFI_INIT_COMPLETE = AXI_07_DFI_INIT_COMPLETE_out; + assign AXI_07_DFI_PHYUPD_REQ = AXI_07_DFI_PHYUPD_REQ_out; + assign AXI_07_DFI_PHY_LP_STATE = AXI_07_DFI_PHY_LP_STATE_out; + assign AXI_07_DFI_RST_N_BUF = AXI_07_DFI_RST_N_BUF_out; + assign AXI_07_RDATA = AXI_07_RDATA_out; + assign AXI_07_RDATA_PARITY = AXI_07_RDATA_PARITY_out; + assign AXI_07_RID = AXI_07_RID_out; + assign AXI_07_RLAST = AXI_07_RLAST_out; + assign AXI_07_RRESP = AXI_07_RRESP_out; + assign AXI_07_RVALID = AXI_07_RVALID_out; + assign AXI_07_WREADY = AXI_07_WREADY_out; + assign AXI_08_ARREADY = AXI_08_ARREADY_out; + assign AXI_08_AWREADY = AXI_08_AWREADY_out; + assign AXI_08_BID = AXI_08_BID_out; + assign AXI_08_BRESP = AXI_08_BRESP_out; + assign AXI_08_BVALID = AXI_08_BVALID_out; + assign AXI_08_DFI_AW_AERR_N = AXI_08_DFI_AW_AERR_N_out; + assign AXI_08_DFI_CLK_BUF = AXI_08_DFI_CLK_BUF_out; + assign AXI_08_DFI_DBI_BYTE_DISABLE = AXI_08_DFI_DBI_BYTE_DISABLE_out; + assign AXI_08_DFI_DW_RDDATA_DBI = AXI_08_DFI_DW_RDDATA_DBI_out; + assign AXI_08_DFI_DW_RDDATA_DERR = AXI_08_DFI_DW_RDDATA_DERR_out; + assign AXI_08_DFI_DW_RDDATA_VALID = AXI_08_DFI_DW_RDDATA_VALID_out; + assign AXI_08_DFI_INIT_COMPLETE = AXI_08_DFI_INIT_COMPLETE_out; + assign AXI_08_DFI_PHYUPD_REQ = AXI_08_DFI_PHYUPD_REQ_out; + assign AXI_08_DFI_PHY_LP_STATE = AXI_08_DFI_PHY_LP_STATE_out; + assign AXI_08_DFI_RST_N_BUF = AXI_08_DFI_RST_N_BUF_out; + assign AXI_08_MC_STATUS = AXI_08_MC_STATUS_out; + assign AXI_08_PHY_STATUS = AXI_08_PHY_STATUS_out; + assign AXI_08_RDATA = AXI_08_RDATA_out; + assign AXI_08_RDATA_PARITY = AXI_08_RDATA_PARITY_out; + assign AXI_08_RID = AXI_08_RID_out; + assign AXI_08_RLAST = AXI_08_RLAST_out; + assign AXI_08_RRESP = AXI_08_RRESP_out; + assign AXI_08_RVALID = AXI_08_RVALID_out; + assign AXI_08_WREADY = AXI_08_WREADY_out; + assign AXI_09_ARREADY = AXI_09_ARREADY_out; + assign AXI_09_AWREADY = AXI_09_AWREADY_out; + assign AXI_09_BID = AXI_09_BID_out; + assign AXI_09_BRESP = AXI_09_BRESP_out; + assign AXI_09_BVALID = AXI_09_BVALID_out; + assign AXI_09_DFI_AW_AERR_N = AXI_09_DFI_AW_AERR_N_out; + assign AXI_09_DFI_CLK_BUF = AXI_09_DFI_CLK_BUF_out; + assign AXI_09_DFI_DBI_BYTE_DISABLE = AXI_09_DFI_DBI_BYTE_DISABLE_out; + assign AXI_09_DFI_DW_RDDATA_DBI = AXI_09_DFI_DW_RDDATA_DBI_out; + assign AXI_09_DFI_DW_RDDATA_DERR = AXI_09_DFI_DW_RDDATA_DERR_out; + assign AXI_09_DFI_DW_RDDATA_VALID = AXI_09_DFI_DW_RDDATA_VALID_out; + assign AXI_09_DFI_INIT_COMPLETE = AXI_09_DFI_INIT_COMPLETE_out; + assign AXI_09_DFI_PHYUPD_REQ = AXI_09_DFI_PHYUPD_REQ_out; + assign AXI_09_DFI_PHY_LP_STATE = AXI_09_DFI_PHY_LP_STATE_out; + assign AXI_09_DFI_RST_N_BUF = AXI_09_DFI_RST_N_BUF_out; + assign AXI_09_RDATA = AXI_09_RDATA_out; + assign AXI_09_RDATA_PARITY = AXI_09_RDATA_PARITY_out; + assign AXI_09_RID = AXI_09_RID_out; + assign AXI_09_RLAST = AXI_09_RLAST_out; + assign AXI_09_RRESP = AXI_09_RRESP_out; + assign AXI_09_RVALID = AXI_09_RVALID_out; + assign AXI_09_WREADY = AXI_09_WREADY_out; + assign AXI_10_ARREADY = AXI_10_ARREADY_out; + assign AXI_10_AWREADY = AXI_10_AWREADY_out; + assign AXI_10_BID = AXI_10_BID_out; + assign AXI_10_BRESP = AXI_10_BRESP_out; + assign AXI_10_BVALID = AXI_10_BVALID_out; + assign AXI_10_DFI_AW_AERR_N = AXI_10_DFI_AW_AERR_N_out; + assign AXI_10_DFI_CLK_BUF = AXI_10_DFI_CLK_BUF_out; + assign AXI_10_DFI_DBI_BYTE_DISABLE = AXI_10_DFI_DBI_BYTE_DISABLE_out; + assign AXI_10_DFI_DW_RDDATA_DBI = AXI_10_DFI_DW_RDDATA_DBI_out; + assign AXI_10_DFI_DW_RDDATA_DERR = AXI_10_DFI_DW_RDDATA_DERR_out; + assign AXI_10_DFI_DW_RDDATA_VALID = AXI_10_DFI_DW_RDDATA_VALID_out; + assign AXI_10_DFI_INIT_COMPLETE = AXI_10_DFI_INIT_COMPLETE_out; + assign AXI_10_DFI_PHYUPD_REQ = AXI_10_DFI_PHYUPD_REQ_out; + assign AXI_10_DFI_PHY_LP_STATE = AXI_10_DFI_PHY_LP_STATE_out; + assign AXI_10_DFI_RST_N_BUF = AXI_10_DFI_RST_N_BUF_out; + assign AXI_10_MC_STATUS = AXI_10_MC_STATUS_out; + assign AXI_10_PHY_STATUS = AXI_10_PHY_STATUS_out; + assign AXI_10_RDATA = AXI_10_RDATA_out; + assign AXI_10_RDATA_PARITY = AXI_10_RDATA_PARITY_out; + assign AXI_10_RID = AXI_10_RID_out; + assign AXI_10_RLAST = AXI_10_RLAST_out; + assign AXI_10_RRESP = AXI_10_RRESP_out; + assign AXI_10_RVALID = AXI_10_RVALID_out; + assign AXI_10_WREADY = AXI_10_WREADY_out; + assign AXI_11_ARREADY = AXI_11_ARREADY_out; + assign AXI_11_AWREADY = AXI_11_AWREADY_out; + assign AXI_11_BID = AXI_11_BID_out; + assign AXI_11_BRESP = AXI_11_BRESP_out; + assign AXI_11_BVALID = AXI_11_BVALID_out; + assign AXI_11_DFI_AW_AERR_N = AXI_11_DFI_AW_AERR_N_out; + assign AXI_11_DFI_CLK_BUF = AXI_11_DFI_CLK_BUF_out; + assign AXI_11_DFI_DBI_BYTE_DISABLE = AXI_11_DFI_DBI_BYTE_DISABLE_out; + assign AXI_11_DFI_DW_RDDATA_DBI = AXI_11_DFI_DW_RDDATA_DBI_out; + assign AXI_11_DFI_DW_RDDATA_DERR = AXI_11_DFI_DW_RDDATA_DERR_out; + assign AXI_11_DFI_DW_RDDATA_VALID = AXI_11_DFI_DW_RDDATA_VALID_out; + assign AXI_11_DFI_INIT_COMPLETE = AXI_11_DFI_INIT_COMPLETE_out; + assign AXI_11_DFI_PHYUPD_REQ = AXI_11_DFI_PHYUPD_REQ_out; + assign AXI_11_DFI_PHY_LP_STATE = AXI_11_DFI_PHY_LP_STATE_out; + assign AXI_11_DFI_RST_N_BUF = AXI_11_DFI_RST_N_BUF_out; + assign AXI_11_RDATA = AXI_11_RDATA_out; + assign AXI_11_RDATA_PARITY = AXI_11_RDATA_PARITY_out; + assign AXI_11_RID = AXI_11_RID_out; + assign AXI_11_RLAST = AXI_11_RLAST_out; + assign AXI_11_RRESP = AXI_11_RRESP_out; + assign AXI_11_RVALID = AXI_11_RVALID_out; + assign AXI_11_WREADY = AXI_11_WREADY_out; + assign AXI_12_ARREADY = AXI_12_ARREADY_out; + assign AXI_12_AWREADY = AXI_12_AWREADY_out; + assign AXI_12_BID = AXI_12_BID_out; + assign AXI_12_BRESP = AXI_12_BRESP_out; + assign AXI_12_BVALID = AXI_12_BVALID_out; + assign AXI_12_DFI_AW_AERR_N = AXI_12_DFI_AW_AERR_N_out; + assign AXI_12_DFI_CLK_BUF = AXI_12_DFI_CLK_BUF_out; + assign AXI_12_DFI_DBI_BYTE_DISABLE = AXI_12_DFI_DBI_BYTE_DISABLE_out; + assign AXI_12_DFI_DW_RDDATA_DBI = AXI_12_DFI_DW_RDDATA_DBI_out; + assign AXI_12_DFI_DW_RDDATA_DERR = AXI_12_DFI_DW_RDDATA_DERR_out; + assign AXI_12_DFI_DW_RDDATA_VALID = AXI_12_DFI_DW_RDDATA_VALID_out; + assign AXI_12_DFI_INIT_COMPLETE = AXI_12_DFI_INIT_COMPLETE_out; + assign AXI_12_DFI_PHYUPD_REQ = AXI_12_DFI_PHYUPD_REQ_out; + assign AXI_12_DFI_PHY_LP_STATE = AXI_12_DFI_PHY_LP_STATE_out; + assign AXI_12_DFI_RST_N_BUF = AXI_12_DFI_RST_N_BUF_out; + assign AXI_12_MC_STATUS = AXI_12_MC_STATUS_out; + assign AXI_12_PHY_STATUS = AXI_12_PHY_STATUS_out; + assign AXI_12_RDATA = AXI_12_RDATA_out; + assign AXI_12_RDATA_PARITY = AXI_12_RDATA_PARITY_out; + assign AXI_12_RID = AXI_12_RID_out; + assign AXI_12_RLAST = AXI_12_RLAST_out; + assign AXI_12_RRESP = AXI_12_RRESP_out; + assign AXI_12_RVALID = AXI_12_RVALID_out; + assign AXI_12_WREADY = AXI_12_WREADY_out; + assign AXI_13_ARREADY = AXI_13_ARREADY_out; + assign AXI_13_AWREADY = AXI_13_AWREADY_out; + assign AXI_13_BID = AXI_13_BID_out; + assign AXI_13_BRESP = AXI_13_BRESP_out; + assign AXI_13_BVALID = AXI_13_BVALID_out; + assign AXI_13_DFI_AW_AERR_N = AXI_13_DFI_AW_AERR_N_out; + assign AXI_13_DFI_CLK_BUF = AXI_13_DFI_CLK_BUF_out; + assign AXI_13_DFI_DBI_BYTE_DISABLE = AXI_13_DFI_DBI_BYTE_DISABLE_out; + assign AXI_13_DFI_DW_RDDATA_DBI = AXI_13_DFI_DW_RDDATA_DBI_out; + assign AXI_13_DFI_DW_RDDATA_DERR = AXI_13_DFI_DW_RDDATA_DERR_out; + assign AXI_13_DFI_DW_RDDATA_VALID = AXI_13_DFI_DW_RDDATA_VALID_out; + assign AXI_13_DFI_INIT_COMPLETE = AXI_13_DFI_INIT_COMPLETE_out; + assign AXI_13_DFI_PHYUPD_REQ = AXI_13_DFI_PHYUPD_REQ_out; + assign AXI_13_DFI_PHY_LP_STATE = AXI_13_DFI_PHY_LP_STATE_out; + assign AXI_13_DFI_RST_N_BUF = AXI_13_DFI_RST_N_BUF_out; + assign AXI_13_RDATA = AXI_13_RDATA_out; + assign AXI_13_RDATA_PARITY = AXI_13_RDATA_PARITY_out; + assign AXI_13_RID = AXI_13_RID_out; + assign AXI_13_RLAST = AXI_13_RLAST_out; + assign AXI_13_RRESP = AXI_13_RRESP_out; + assign AXI_13_RVALID = AXI_13_RVALID_out; + assign AXI_13_WREADY = AXI_13_WREADY_out; + assign AXI_14_ARREADY = AXI_14_ARREADY_out; + assign AXI_14_AWREADY = AXI_14_AWREADY_out; + assign AXI_14_BID = AXI_14_BID_out; + assign AXI_14_BRESP = AXI_14_BRESP_out; + assign AXI_14_BVALID = AXI_14_BVALID_out; + assign AXI_14_DFI_AW_AERR_N = AXI_14_DFI_AW_AERR_N_out; + assign AXI_14_DFI_CLK_BUF = AXI_14_DFI_CLK_BUF_out; + assign AXI_14_DFI_DBI_BYTE_DISABLE = AXI_14_DFI_DBI_BYTE_DISABLE_out; + assign AXI_14_DFI_DW_RDDATA_DBI = AXI_14_DFI_DW_RDDATA_DBI_out; + assign AXI_14_DFI_DW_RDDATA_DERR = AXI_14_DFI_DW_RDDATA_DERR_out; + assign AXI_14_DFI_DW_RDDATA_VALID = AXI_14_DFI_DW_RDDATA_VALID_out; + assign AXI_14_DFI_INIT_COMPLETE = AXI_14_DFI_INIT_COMPLETE_out; + assign AXI_14_DFI_PHYUPD_REQ = AXI_14_DFI_PHYUPD_REQ_out; + assign AXI_14_DFI_PHY_LP_STATE = AXI_14_DFI_PHY_LP_STATE_out; + assign AXI_14_DFI_RST_N_BUF = AXI_14_DFI_RST_N_BUF_out; + assign AXI_14_MC_STATUS = AXI_14_MC_STATUS_out; + assign AXI_14_PHY_STATUS = AXI_14_PHY_STATUS_out; + assign AXI_14_RDATA = AXI_14_RDATA_out; + assign AXI_14_RDATA_PARITY = AXI_14_RDATA_PARITY_out; + assign AXI_14_RID = AXI_14_RID_out; + assign AXI_14_RLAST = AXI_14_RLAST_out; + assign AXI_14_RRESP = AXI_14_RRESP_out; + assign AXI_14_RVALID = AXI_14_RVALID_out; + assign AXI_14_WREADY = AXI_14_WREADY_out; + assign AXI_15_ARREADY = AXI_15_ARREADY_out; + assign AXI_15_AWREADY = AXI_15_AWREADY_out; + assign AXI_15_BID = AXI_15_BID_out; + assign AXI_15_BRESP = AXI_15_BRESP_out; + assign AXI_15_BVALID = AXI_15_BVALID_out; + assign AXI_15_DFI_AW_AERR_N = AXI_15_DFI_AW_AERR_N_out; + assign AXI_15_DFI_CLK_BUF = AXI_15_DFI_CLK_BUF_out; + assign AXI_15_DFI_DBI_BYTE_DISABLE = AXI_15_DFI_DBI_BYTE_DISABLE_out; + assign AXI_15_DFI_DW_RDDATA_DBI = AXI_15_DFI_DW_RDDATA_DBI_out; + assign AXI_15_DFI_DW_RDDATA_DERR = AXI_15_DFI_DW_RDDATA_DERR_out; + assign AXI_15_DFI_DW_RDDATA_VALID = AXI_15_DFI_DW_RDDATA_VALID_out; + assign AXI_15_DFI_INIT_COMPLETE = AXI_15_DFI_INIT_COMPLETE_out; + assign AXI_15_DFI_PHYUPD_REQ = AXI_15_DFI_PHYUPD_REQ_out; + assign AXI_15_DFI_PHY_LP_STATE = AXI_15_DFI_PHY_LP_STATE_out; + assign AXI_15_DFI_RST_N_BUF = AXI_15_DFI_RST_N_BUF_out; + assign AXI_15_RDATA = AXI_15_RDATA_out; + assign AXI_15_RDATA_PARITY = AXI_15_RDATA_PARITY_out; + assign AXI_15_RID = AXI_15_RID_out; + assign AXI_15_RLAST = AXI_15_RLAST_out; + assign AXI_15_RRESP = AXI_15_RRESP_out; + assign AXI_15_RVALID = AXI_15_RVALID_out; + assign AXI_15_WREADY = AXI_15_WREADY_out; + assign DRAM_0_STAT_CATTRIP = DRAM_0_STAT_CATTRIP_out; + assign DRAM_0_STAT_TEMP = DRAM_0_STAT_TEMP_out; + + assign APB_0_PADDR_in = APB_0_PADDR; + assign APB_0_PCLK_in = APB_0_PCLK; + assign APB_0_PENABLE_in = APB_0_PENABLE; + assign APB_0_PRESET_N_in = APB_0_PRESET_N; + assign APB_0_PSEL_in = APB_0_PSEL; + assign APB_0_PWDATA_in = APB_0_PWDATA; + assign APB_0_PWRITE_in = APB_0_PWRITE; + assign AXI_00_ACLK_in = AXI_00_ACLK; + assign AXI_00_ARADDR_in = AXI_00_ARADDR; + assign AXI_00_ARBURST_in = AXI_00_ARBURST; + assign AXI_00_ARESET_N_in = AXI_00_ARESET_N; + assign AXI_00_ARID_in = AXI_00_ARID; + assign AXI_00_ARLEN_in = AXI_00_ARLEN; + assign AXI_00_ARSIZE_in = AXI_00_ARSIZE; + assign AXI_00_ARVALID_in = AXI_00_ARVALID; + assign AXI_00_AWADDR_in = AXI_00_AWADDR; + assign AXI_00_AWBURST_in = AXI_00_AWBURST; + assign AXI_00_AWID_in = AXI_00_AWID; + assign AXI_00_AWLEN_in = AXI_00_AWLEN; + assign AXI_00_AWSIZE_in = AXI_00_AWSIZE; + assign AXI_00_AWVALID_in = AXI_00_AWVALID; + assign AXI_00_BREADY_in = AXI_00_BREADY; + assign AXI_00_DFI_LP_PWR_X_REQ_in = AXI_00_DFI_LP_PWR_X_REQ; + assign AXI_00_RREADY_in = AXI_00_RREADY; + assign AXI_00_WDATA_PARITY_in = AXI_00_WDATA_PARITY; + assign AXI_00_WDATA_in = AXI_00_WDATA; + assign AXI_00_WLAST_in = AXI_00_WLAST; + assign AXI_00_WSTRB_in = AXI_00_WSTRB; + assign AXI_00_WVALID_in = AXI_00_WVALID; + assign AXI_01_ACLK_in = AXI_01_ACLK; + assign AXI_01_ARADDR_in = AXI_01_ARADDR; + assign AXI_01_ARBURST_in = AXI_01_ARBURST; + assign AXI_01_ARESET_N_in = AXI_01_ARESET_N; + assign AXI_01_ARID_in = AXI_01_ARID; + assign AXI_01_ARLEN_in = AXI_01_ARLEN; + assign AXI_01_ARSIZE_in = AXI_01_ARSIZE; + assign AXI_01_ARVALID_in = AXI_01_ARVALID; + assign AXI_01_AWADDR_in = AXI_01_AWADDR; + assign AXI_01_AWBURST_in = AXI_01_AWBURST; + assign AXI_01_AWID_in = AXI_01_AWID; + assign AXI_01_AWLEN_in = AXI_01_AWLEN; + assign AXI_01_AWSIZE_in = AXI_01_AWSIZE; + assign AXI_01_AWVALID_in = AXI_01_AWVALID; + assign AXI_01_BREADY_in = AXI_01_BREADY; + assign AXI_01_DFI_LP_PWR_X_REQ_in = AXI_01_DFI_LP_PWR_X_REQ; + assign AXI_01_RREADY_in = AXI_01_RREADY; + assign AXI_01_WDATA_PARITY_in = AXI_01_WDATA_PARITY; + assign AXI_01_WDATA_in = AXI_01_WDATA; + assign AXI_01_WLAST_in = AXI_01_WLAST; + assign AXI_01_WSTRB_in = AXI_01_WSTRB; + assign AXI_01_WVALID_in = AXI_01_WVALID; + assign AXI_02_ACLK_in = AXI_02_ACLK; + assign AXI_02_ARADDR_in = AXI_02_ARADDR; + assign AXI_02_ARBURST_in = AXI_02_ARBURST; + assign AXI_02_ARESET_N_in = AXI_02_ARESET_N; + assign AXI_02_ARID_in = AXI_02_ARID; + assign AXI_02_ARLEN_in = AXI_02_ARLEN; + assign AXI_02_ARSIZE_in = AXI_02_ARSIZE; + assign AXI_02_ARVALID_in = AXI_02_ARVALID; + assign AXI_02_AWADDR_in = AXI_02_AWADDR; + assign AXI_02_AWBURST_in = AXI_02_AWBURST; + assign AXI_02_AWID_in = AXI_02_AWID; + assign AXI_02_AWLEN_in = AXI_02_AWLEN; + assign AXI_02_AWSIZE_in = AXI_02_AWSIZE; + assign AXI_02_AWVALID_in = AXI_02_AWVALID; + assign AXI_02_BREADY_in = AXI_02_BREADY; + assign AXI_02_DFI_LP_PWR_X_REQ_in = AXI_02_DFI_LP_PWR_X_REQ; + assign AXI_02_RREADY_in = AXI_02_RREADY; + assign AXI_02_WDATA_PARITY_in = AXI_02_WDATA_PARITY; + assign AXI_02_WDATA_in = AXI_02_WDATA; + assign AXI_02_WLAST_in = AXI_02_WLAST; + assign AXI_02_WSTRB_in = AXI_02_WSTRB; + assign AXI_02_WVALID_in = AXI_02_WVALID; + assign AXI_03_ACLK_in = AXI_03_ACLK; + assign AXI_03_ARADDR_in = AXI_03_ARADDR; + assign AXI_03_ARBURST_in = AXI_03_ARBURST; + assign AXI_03_ARESET_N_in = AXI_03_ARESET_N; + assign AXI_03_ARID_in = AXI_03_ARID; + assign AXI_03_ARLEN_in = AXI_03_ARLEN; + assign AXI_03_ARSIZE_in = AXI_03_ARSIZE; + assign AXI_03_ARVALID_in = AXI_03_ARVALID; + assign AXI_03_AWADDR_in = AXI_03_AWADDR; + assign AXI_03_AWBURST_in = AXI_03_AWBURST; + assign AXI_03_AWID_in = AXI_03_AWID; + assign AXI_03_AWLEN_in = AXI_03_AWLEN; + assign AXI_03_AWSIZE_in = AXI_03_AWSIZE; + assign AXI_03_AWVALID_in = AXI_03_AWVALID; + assign AXI_03_BREADY_in = AXI_03_BREADY; + assign AXI_03_DFI_LP_PWR_X_REQ_in = AXI_03_DFI_LP_PWR_X_REQ; + assign AXI_03_RREADY_in = AXI_03_RREADY; + assign AXI_03_WDATA_PARITY_in = AXI_03_WDATA_PARITY; + assign AXI_03_WDATA_in = AXI_03_WDATA; + assign AXI_03_WLAST_in = AXI_03_WLAST; + assign AXI_03_WSTRB_in = AXI_03_WSTRB; + assign AXI_03_WVALID_in = AXI_03_WVALID; + assign AXI_04_ACLK_in = AXI_04_ACLK; + assign AXI_04_ARADDR_in = AXI_04_ARADDR; + assign AXI_04_ARBURST_in = AXI_04_ARBURST; + assign AXI_04_ARESET_N_in = AXI_04_ARESET_N; + assign AXI_04_ARID_in = AXI_04_ARID; + assign AXI_04_ARLEN_in = AXI_04_ARLEN; + assign AXI_04_ARSIZE_in = AXI_04_ARSIZE; + assign AXI_04_ARVALID_in = AXI_04_ARVALID; + assign AXI_04_AWADDR_in = AXI_04_AWADDR; + assign AXI_04_AWBURST_in = AXI_04_AWBURST; + assign AXI_04_AWID_in = AXI_04_AWID; + assign AXI_04_AWLEN_in = AXI_04_AWLEN; + assign AXI_04_AWSIZE_in = AXI_04_AWSIZE; + assign AXI_04_AWVALID_in = AXI_04_AWVALID; + assign AXI_04_BREADY_in = AXI_04_BREADY; + assign AXI_04_DFI_LP_PWR_X_REQ_in = AXI_04_DFI_LP_PWR_X_REQ; + assign AXI_04_RREADY_in = AXI_04_RREADY; + assign AXI_04_WDATA_PARITY_in = AXI_04_WDATA_PARITY; + assign AXI_04_WDATA_in = AXI_04_WDATA; + assign AXI_04_WLAST_in = AXI_04_WLAST; + assign AXI_04_WSTRB_in = AXI_04_WSTRB; + assign AXI_04_WVALID_in = AXI_04_WVALID; + assign AXI_05_ACLK_in = AXI_05_ACLK; + assign AXI_05_ARADDR_in = AXI_05_ARADDR; + assign AXI_05_ARBURST_in = AXI_05_ARBURST; + assign AXI_05_ARESET_N_in = AXI_05_ARESET_N; + assign AXI_05_ARID_in = AXI_05_ARID; + assign AXI_05_ARLEN_in = AXI_05_ARLEN; + assign AXI_05_ARSIZE_in = AXI_05_ARSIZE; + assign AXI_05_ARVALID_in = AXI_05_ARVALID; + assign AXI_05_AWADDR_in = AXI_05_AWADDR; + assign AXI_05_AWBURST_in = AXI_05_AWBURST; + assign AXI_05_AWID_in = AXI_05_AWID; + assign AXI_05_AWLEN_in = AXI_05_AWLEN; + assign AXI_05_AWSIZE_in = AXI_05_AWSIZE; + assign AXI_05_AWVALID_in = AXI_05_AWVALID; + assign AXI_05_BREADY_in = AXI_05_BREADY; + assign AXI_05_DFI_LP_PWR_X_REQ_in = AXI_05_DFI_LP_PWR_X_REQ; + assign AXI_05_RREADY_in = AXI_05_RREADY; + assign AXI_05_WDATA_PARITY_in = AXI_05_WDATA_PARITY; + assign AXI_05_WDATA_in = AXI_05_WDATA; + assign AXI_05_WLAST_in = AXI_05_WLAST; + assign AXI_05_WSTRB_in = AXI_05_WSTRB; + assign AXI_05_WVALID_in = AXI_05_WVALID; + assign AXI_06_ACLK_in = AXI_06_ACLK; + assign AXI_06_ARADDR_in = AXI_06_ARADDR; + assign AXI_06_ARBURST_in = AXI_06_ARBURST; + assign AXI_06_ARESET_N_in = AXI_06_ARESET_N; + assign AXI_06_ARID_in = AXI_06_ARID; + assign AXI_06_ARLEN_in = AXI_06_ARLEN; + assign AXI_06_ARSIZE_in = AXI_06_ARSIZE; + assign AXI_06_ARVALID_in = AXI_06_ARVALID; + assign AXI_06_AWADDR_in = AXI_06_AWADDR; + assign AXI_06_AWBURST_in = AXI_06_AWBURST; + assign AXI_06_AWID_in = AXI_06_AWID; + assign AXI_06_AWLEN_in = AXI_06_AWLEN; + assign AXI_06_AWSIZE_in = AXI_06_AWSIZE; + assign AXI_06_AWVALID_in = AXI_06_AWVALID; + assign AXI_06_BREADY_in = AXI_06_BREADY; + assign AXI_06_DFI_LP_PWR_X_REQ_in = AXI_06_DFI_LP_PWR_X_REQ; + assign AXI_06_RREADY_in = AXI_06_RREADY; + assign AXI_06_WDATA_PARITY_in = AXI_06_WDATA_PARITY; + assign AXI_06_WDATA_in = AXI_06_WDATA; + assign AXI_06_WLAST_in = AXI_06_WLAST; + assign AXI_06_WSTRB_in = AXI_06_WSTRB; + assign AXI_06_WVALID_in = AXI_06_WVALID; + assign AXI_07_ACLK_in = AXI_07_ACLK; + assign AXI_07_ARADDR_in = AXI_07_ARADDR; + assign AXI_07_ARBURST_in = AXI_07_ARBURST; + assign AXI_07_ARESET_N_in = AXI_07_ARESET_N; + assign AXI_07_ARID_in = AXI_07_ARID; + assign AXI_07_ARLEN_in = AXI_07_ARLEN; + assign AXI_07_ARSIZE_in = AXI_07_ARSIZE; + assign AXI_07_ARVALID_in = AXI_07_ARVALID; + assign AXI_07_AWADDR_in = AXI_07_AWADDR; + assign AXI_07_AWBURST_in = AXI_07_AWBURST; + assign AXI_07_AWID_in = AXI_07_AWID; + assign AXI_07_AWLEN_in = AXI_07_AWLEN; + assign AXI_07_AWSIZE_in = AXI_07_AWSIZE; + assign AXI_07_AWVALID_in = AXI_07_AWVALID; + assign AXI_07_BREADY_in = AXI_07_BREADY; + assign AXI_07_DFI_LP_PWR_X_REQ_in = AXI_07_DFI_LP_PWR_X_REQ; + assign AXI_07_RREADY_in = AXI_07_RREADY; + assign AXI_07_WDATA_PARITY_in = AXI_07_WDATA_PARITY; + assign AXI_07_WDATA_in = AXI_07_WDATA; + assign AXI_07_WLAST_in = AXI_07_WLAST; + assign AXI_07_WSTRB_in = AXI_07_WSTRB; + assign AXI_07_WVALID_in = AXI_07_WVALID; + assign AXI_08_ACLK_in = AXI_08_ACLK; + assign AXI_08_ARADDR_in = AXI_08_ARADDR; + assign AXI_08_ARBURST_in = AXI_08_ARBURST; + assign AXI_08_ARESET_N_in = AXI_08_ARESET_N; + assign AXI_08_ARID_in = AXI_08_ARID; + assign AXI_08_ARLEN_in = AXI_08_ARLEN; + assign AXI_08_ARSIZE_in = AXI_08_ARSIZE; + assign AXI_08_ARVALID_in = AXI_08_ARVALID; + assign AXI_08_AWADDR_in = AXI_08_AWADDR; + assign AXI_08_AWBURST_in = AXI_08_AWBURST; + assign AXI_08_AWID_in = AXI_08_AWID; + assign AXI_08_AWLEN_in = AXI_08_AWLEN; + assign AXI_08_AWSIZE_in = AXI_08_AWSIZE; + assign AXI_08_AWVALID_in = AXI_08_AWVALID; + assign AXI_08_BREADY_in = AXI_08_BREADY; + assign AXI_08_DFI_LP_PWR_X_REQ_in = AXI_08_DFI_LP_PWR_X_REQ; + assign AXI_08_RREADY_in = AXI_08_RREADY; + assign AXI_08_WDATA_PARITY_in = AXI_08_WDATA_PARITY; + assign AXI_08_WDATA_in = AXI_08_WDATA; + assign AXI_08_WLAST_in = AXI_08_WLAST; + assign AXI_08_WSTRB_in = AXI_08_WSTRB; + assign AXI_08_WVALID_in = AXI_08_WVALID; + assign AXI_09_ACLK_in = AXI_09_ACLK; + assign AXI_09_ARADDR_in = AXI_09_ARADDR; + assign AXI_09_ARBURST_in = AXI_09_ARBURST; + assign AXI_09_ARESET_N_in = AXI_09_ARESET_N; + assign AXI_09_ARID_in = AXI_09_ARID; + assign AXI_09_ARLEN_in = AXI_09_ARLEN; + assign AXI_09_ARSIZE_in = AXI_09_ARSIZE; + assign AXI_09_ARVALID_in = AXI_09_ARVALID; + assign AXI_09_AWADDR_in = AXI_09_AWADDR; + assign AXI_09_AWBURST_in = AXI_09_AWBURST; + assign AXI_09_AWID_in = AXI_09_AWID; + assign AXI_09_AWLEN_in = AXI_09_AWLEN; + assign AXI_09_AWSIZE_in = AXI_09_AWSIZE; + assign AXI_09_AWVALID_in = AXI_09_AWVALID; + assign AXI_09_BREADY_in = AXI_09_BREADY; + assign AXI_09_DFI_LP_PWR_X_REQ_in = AXI_09_DFI_LP_PWR_X_REQ; + assign AXI_09_RREADY_in = AXI_09_RREADY; + assign AXI_09_WDATA_PARITY_in = AXI_09_WDATA_PARITY; + assign AXI_09_WDATA_in = AXI_09_WDATA; + assign AXI_09_WLAST_in = AXI_09_WLAST; + assign AXI_09_WSTRB_in = AXI_09_WSTRB; + assign AXI_09_WVALID_in = AXI_09_WVALID; + assign AXI_10_ACLK_in = AXI_10_ACLK; + assign AXI_10_ARADDR_in = AXI_10_ARADDR; + assign AXI_10_ARBURST_in = AXI_10_ARBURST; + assign AXI_10_ARESET_N_in = AXI_10_ARESET_N; + assign AXI_10_ARID_in = AXI_10_ARID; + assign AXI_10_ARLEN_in = AXI_10_ARLEN; + assign AXI_10_ARSIZE_in = AXI_10_ARSIZE; + assign AXI_10_ARVALID_in = AXI_10_ARVALID; + assign AXI_10_AWADDR_in = AXI_10_AWADDR; + assign AXI_10_AWBURST_in = AXI_10_AWBURST; + assign AXI_10_AWID_in = AXI_10_AWID; + assign AXI_10_AWLEN_in = AXI_10_AWLEN; + assign AXI_10_AWSIZE_in = AXI_10_AWSIZE; + assign AXI_10_AWVALID_in = AXI_10_AWVALID; + assign AXI_10_BREADY_in = AXI_10_BREADY; + assign AXI_10_DFI_LP_PWR_X_REQ_in = AXI_10_DFI_LP_PWR_X_REQ; + assign AXI_10_RREADY_in = AXI_10_RREADY; + assign AXI_10_WDATA_PARITY_in = AXI_10_WDATA_PARITY; + assign AXI_10_WDATA_in = AXI_10_WDATA; + assign AXI_10_WLAST_in = AXI_10_WLAST; + assign AXI_10_WSTRB_in = AXI_10_WSTRB; + assign AXI_10_WVALID_in = AXI_10_WVALID; + assign AXI_11_ACLK_in = AXI_11_ACLK; + assign AXI_11_ARADDR_in = AXI_11_ARADDR; + assign AXI_11_ARBURST_in = AXI_11_ARBURST; + assign AXI_11_ARESET_N_in = AXI_11_ARESET_N; + assign AXI_11_ARID_in = AXI_11_ARID; + assign AXI_11_ARLEN_in = AXI_11_ARLEN; + assign AXI_11_ARSIZE_in = AXI_11_ARSIZE; + assign AXI_11_ARVALID_in = AXI_11_ARVALID; + assign AXI_11_AWADDR_in = AXI_11_AWADDR; + assign AXI_11_AWBURST_in = AXI_11_AWBURST; + assign AXI_11_AWID_in = AXI_11_AWID; + assign AXI_11_AWLEN_in = AXI_11_AWLEN; + assign AXI_11_AWSIZE_in = AXI_11_AWSIZE; + assign AXI_11_AWVALID_in = AXI_11_AWVALID; + assign AXI_11_BREADY_in = AXI_11_BREADY; + assign AXI_11_DFI_LP_PWR_X_REQ_in = AXI_11_DFI_LP_PWR_X_REQ; + assign AXI_11_RREADY_in = AXI_11_RREADY; + assign AXI_11_WDATA_PARITY_in = AXI_11_WDATA_PARITY; + assign AXI_11_WDATA_in = AXI_11_WDATA; + assign AXI_11_WLAST_in = AXI_11_WLAST; + assign AXI_11_WSTRB_in = AXI_11_WSTRB; + assign AXI_11_WVALID_in = AXI_11_WVALID; + assign AXI_12_ACLK_in = AXI_12_ACLK; + assign AXI_12_ARADDR_in = AXI_12_ARADDR; + assign AXI_12_ARBURST_in = AXI_12_ARBURST; + assign AXI_12_ARESET_N_in = AXI_12_ARESET_N; + assign AXI_12_ARID_in = AXI_12_ARID; + assign AXI_12_ARLEN_in = AXI_12_ARLEN; + assign AXI_12_ARSIZE_in = AXI_12_ARSIZE; + assign AXI_12_ARVALID_in = AXI_12_ARVALID; + assign AXI_12_AWADDR_in = AXI_12_AWADDR; + assign AXI_12_AWBURST_in = AXI_12_AWBURST; + assign AXI_12_AWID_in = AXI_12_AWID; + assign AXI_12_AWLEN_in = AXI_12_AWLEN; + assign AXI_12_AWSIZE_in = AXI_12_AWSIZE; + assign AXI_12_AWVALID_in = AXI_12_AWVALID; + assign AXI_12_BREADY_in = AXI_12_BREADY; + assign AXI_12_DFI_LP_PWR_X_REQ_in = AXI_12_DFI_LP_PWR_X_REQ; + assign AXI_12_RREADY_in = AXI_12_RREADY; + assign AXI_12_WDATA_PARITY_in = AXI_12_WDATA_PARITY; + assign AXI_12_WDATA_in = AXI_12_WDATA; + assign AXI_12_WLAST_in = AXI_12_WLAST; + assign AXI_12_WSTRB_in = AXI_12_WSTRB; + assign AXI_12_WVALID_in = AXI_12_WVALID; + assign AXI_13_ACLK_in = AXI_13_ACLK; + assign AXI_13_ARADDR_in = AXI_13_ARADDR; + assign AXI_13_ARBURST_in = AXI_13_ARBURST; + assign AXI_13_ARESET_N_in = AXI_13_ARESET_N; + assign AXI_13_ARID_in = AXI_13_ARID; + assign AXI_13_ARLEN_in = AXI_13_ARLEN; + assign AXI_13_ARSIZE_in = AXI_13_ARSIZE; + assign AXI_13_ARVALID_in = AXI_13_ARVALID; + assign AXI_13_AWADDR_in = AXI_13_AWADDR; + assign AXI_13_AWBURST_in = AXI_13_AWBURST; + assign AXI_13_AWID_in = AXI_13_AWID; + assign AXI_13_AWLEN_in = AXI_13_AWLEN; + assign AXI_13_AWSIZE_in = AXI_13_AWSIZE; + assign AXI_13_AWVALID_in = AXI_13_AWVALID; + assign AXI_13_BREADY_in = AXI_13_BREADY; + assign AXI_13_DFI_LP_PWR_X_REQ_in = AXI_13_DFI_LP_PWR_X_REQ; + assign AXI_13_RREADY_in = AXI_13_RREADY; + assign AXI_13_WDATA_PARITY_in = AXI_13_WDATA_PARITY; + assign AXI_13_WDATA_in = AXI_13_WDATA; + assign AXI_13_WLAST_in = AXI_13_WLAST; + assign AXI_13_WSTRB_in = AXI_13_WSTRB; + assign AXI_13_WVALID_in = AXI_13_WVALID; + assign AXI_14_ACLK_in = AXI_14_ACLK; + assign AXI_14_ARADDR_in = AXI_14_ARADDR; + assign AXI_14_ARBURST_in = AXI_14_ARBURST; + assign AXI_14_ARESET_N_in = AXI_14_ARESET_N; + assign AXI_14_ARID_in = AXI_14_ARID; + assign AXI_14_ARLEN_in = AXI_14_ARLEN; + assign AXI_14_ARSIZE_in = AXI_14_ARSIZE; + assign AXI_14_ARVALID_in = AXI_14_ARVALID; + assign AXI_14_AWADDR_in = AXI_14_AWADDR; + assign AXI_14_AWBURST_in = AXI_14_AWBURST; + assign AXI_14_AWID_in = AXI_14_AWID; + assign AXI_14_AWLEN_in = AXI_14_AWLEN; + assign AXI_14_AWSIZE_in = AXI_14_AWSIZE; + assign AXI_14_AWVALID_in = AXI_14_AWVALID; + assign AXI_14_BREADY_in = AXI_14_BREADY; + assign AXI_14_DFI_LP_PWR_X_REQ_in = AXI_14_DFI_LP_PWR_X_REQ; + assign AXI_14_RREADY_in = AXI_14_RREADY; + assign AXI_14_WDATA_PARITY_in = AXI_14_WDATA_PARITY; + assign AXI_14_WDATA_in = AXI_14_WDATA; + assign AXI_14_WLAST_in = AXI_14_WLAST; + assign AXI_14_WSTRB_in = AXI_14_WSTRB; + assign AXI_14_WVALID_in = AXI_14_WVALID; + assign AXI_15_ACLK_in = AXI_15_ACLK; + assign AXI_15_ARADDR_in = AXI_15_ARADDR; + assign AXI_15_ARBURST_in = AXI_15_ARBURST; + assign AXI_15_ARESET_N_in = AXI_15_ARESET_N; + assign AXI_15_ARID_in = AXI_15_ARID; + assign AXI_15_ARLEN_in = AXI_15_ARLEN; + assign AXI_15_ARSIZE_in = AXI_15_ARSIZE; + assign AXI_15_ARVALID_in = AXI_15_ARVALID; + assign AXI_15_AWADDR_in = AXI_15_AWADDR; + assign AXI_15_AWBURST_in = AXI_15_AWBURST; + assign AXI_15_AWID_in = AXI_15_AWID; + assign AXI_15_AWLEN_in = AXI_15_AWLEN; + assign AXI_15_AWSIZE_in = AXI_15_AWSIZE; + assign AXI_15_AWVALID_in = AXI_15_AWVALID; + assign AXI_15_BREADY_in = AXI_15_BREADY; + assign AXI_15_DFI_LP_PWR_X_REQ_in = AXI_15_DFI_LP_PWR_X_REQ; + assign AXI_15_RREADY_in = AXI_15_RREADY; + assign AXI_15_WDATA_PARITY_in = AXI_15_WDATA_PARITY; + assign AXI_15_WDATA_in = AXI_15_WDATA; + assign AXI_15_WLAST_in = AXI_15_WLAST; + assign AXI_15_WSTRB_in = AXI_15_WSTRB; + assign AXI_15_WVALID_in = AXI_15_WVALID; + assign BSCAN_DRCK_in = BSCAN_DRCK; + assign BSCAN_TCK_in = BSCAN_TCK; + assign HBM_REF_CLK_in = HBM_REF_CLK; + assign MBIST_EN_00_in = MBIST_EN_00; + assign MBIST_EN_01_in = MBIST_EN_01; + assign MBIST_EN_02_in = MBIST_EN_02; + assign MBIST_EN_03_in = MBIST_EN_03; + assign MBIST_EN_04_in = MBIST_EN_04; + assign MBIST_EN_05_in = MBIST_EN_05; + assign MBIST_EN_06_in = MBIST_EN_06; + assign MBIST_EN_07_in = MBIST_EN_07; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLK_SEL_00_REG != "FALSE") && + (CLK_SEL_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] CLK_SEL_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_01_REG != "FALSE") && + (CLK_SEL_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] CLK_SEL_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_02_REG != "FALSE") && + (CLK_SEL_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] CLK_SEL_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_03_REG != "FALSE") && + (CLK_SEL_03_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] CLK_SEL_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_04_REG != "FALSE") && + (CLK_SEL_04_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] CLK_SEL_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_05_REG != "FALSE") && + (CLK_SEL_05_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] CLK_SEL_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_06_REG != "FALSE") && + (CLK_SEL_06_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] CLK_SEL_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_07_REG != "FALSE") && + (CLK_SEL_07_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] CLK_SEL_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_08_REG != "FALSE") && + (CLK_SEL_08_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] CLK_SEL_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_09_REG != "FALSE") && + (CLK_SEL_09_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] CLK_SEL_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_10_REG != "FALSE") && + (CLK_SEL_10_REG != "TRUE"))) begin + $display("Error: [Unisim %s-115] CLK_SEL_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_11_REG != "FALSE") && + (CLK_SEL_11_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] CLK_SEL_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_12_REG != "FALSE") && + (CLK_SEL_12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-117] CLK_SEL_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_13_REG != "FALSE") && + (CLK_SEL_13_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] CLK_SEL_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_14_REG != "FALSE") && + (CLK_SEL_14_REG != "TRUE"))) begin + $display("Error: [Unisim %s-119] CLK_SEL_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_15_REG != "FALSE") && + (CLK_SEL_15_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] CLK_SEL_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_00_REG < 50) || (DATARATE_00_REG > 1800))) begin + $display("Error: [Unisim %s-121] DATARATE_00 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_01_REG < 50) || (DATARATE_01_REG > 1800))) begin + $display("Error: [Unisim %s-122] DATARATE_01 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_02_REG < 50) || (DATARATE_02_REG > 1800))) begin + $display("Error: [Unisim %s-123] DATARATE_02 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_03_REG < 50) || (DATARATE_03_REG > 1800))) begin + $display("Error: [Unisim %s-124] DATARATE_03 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_04_REG < 50) || (DATARATE_04_REG > 1800))) begin + $display("Error: [Unisim %s-125] DATARATE_04 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_05_REG < 50) || (DATARATE_05_REG > 1800))) begin + $display("Error: [Unisim %s-126] DATARATE_05 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_06_REG < 50) || (DATARATE_06_REG > 1800))) begin + $display("Error: [Unisim %s-127] DATARATE_06 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_07_REG < 50) || (DATARATE_07_REG > 1800))) begin + $display("Error: [Unisim %s-128] DATARATE_07 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DA_LOCKOUT_REG != "FALSE") && + (DA_LOCKOUT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] DA_LOCKOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DA_LOCKOUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_0_REG != "FALSE") && + (MC_ENABLE_0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-177] MC_ENABLE_0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_1_REG != "FALSE") && + (MC_ENABLE_1_REG != "TRUE"))) begin + $display("Error: [Unisim %s-178] MC_ENABLE_1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_2_REG != "FALSE") && + (MC_ENABLE_2_REG != "TRUE"))) begin + $display("Error: [Unisim %s-179] MC_ENABLE_2 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_3_REG != "FALSE") && + (MC_ENABLE_3_REG != "TRUE"))) begin + $display("Error: [Unisim %s-180] MC_ENABLE_3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_4_REG != "FALSE") && + (MC_ENABLE_4_REG != "TRUE"))) begin + $display("Error: [Unisim %s-181] MC_ENABLE_4 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_5_REG != "FALSE") && + (MC_ENABLE_5_REG != "TRUE"))) begin + $display("Error: [Unisim %s-182] MC_ENABLE_5 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_5_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_6_REG != "FALSE") && + (MC_ENABLE_6_REG != "TRUE"))) begin + $display("Error: [Unisim %s-183] MC_ENABLE_6 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_6_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_7_REG != "FALSE") && + (MC_ENABLE_7_REG != "TRUE"))) begin + $display("Error: [Unisim %s-184] MC_ENABLE_7 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_7_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_APB_REG != "FALSE") && + (MC_ENABLE_APB_REG != "TRUE"))) begin + $display("Error: [Unisim %s-185] MC_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_APB_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PAGEHIT_PERCENT_00_REG < 0) || (PAGEHIT_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-194] PAGEHIT_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_00_REG != "FALSE") && + (PHY_ENABLE_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-196] PHY_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_01_REG != "FALSE") && + (PHY_ENABLE_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-197] PHY_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_02_REG != "FALSE") && + (PHY_ENABLE_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-198] PHY_ENABLE_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_03_REG != "FALSE") && + (PHY_ENABLE_03_REG != "TRUE"))) begin + $display("Error: [Unisim %s-199] PHY_ENABLE_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_04_REG != "FALSE") && + (PHY_ENABLE_04_REG != "TRUE"))) begin + $display("Error: [Unisim %s-200] PHY_ENABLE_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_05_REG != "FALSE") && + (PHY_ENABLE_05_REG != "TRUE"))) begin + $display("Error: [Unisim %s-201] PHY_ENABLE_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_06_REG != "FALSE") && + (PHY_ENABLE_06_REG != "TRUE"))) begin + $display("Error: [Unisim %s-202] PHY_ENABLE_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_07_REG != "FALSE") && + (PHY_ENABLE_07_REG != "TRUE"))) begin + $display("Error: [Unisim %s-203] PHY_ENABLE_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_08_REG != "FALSE") && + (PHY_ENABLE_08_REG != "TRUE"))) begin + $display("Error: [Unisim %s-204] PHY_ENABLE_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_09_REG != "FALSE") && + (PHY_ENABLE_09_REG != "TRUE"))) begin + $display("Error: [Unisim %s-205] PHY_ENABLE_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_10_REG != "FALSE") && + (PHY_ENABLE_10_REG != "TRUE"))) begin + $display("Error: [Unisim %s-206] PHY_ENABLE_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_11_REG != "FALSE") && + (PHY_ENABLE_11_REG != "TRUE"))) begin + $display("Error: [Unisim %s-207] PHY_ENABLE_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_12_REG != "FALSE") && + (PHY_ENABLE_12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-208] PHY_ENABLE_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_13_REG != "FALSE") && + (PHY_ENABLE_13_REG != "TRUE"))) begin + $display("Error: [Unisim %s-209] PHY_ENABLE_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_14_REG != "FALSE") && + (PHY_ENABLE_14_REG != "TRUE"))) begin + $display("Error: [Unisim %s-210] PHY_ENABLE_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_15_REG != "FALSE") && + (PHY_ENABLE_15_REG != "TRUE"))) begin + $display("Error: [Unisim %s-211] PHY_ENABLE_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_APB_REG != "FALSE") && + (PHY_ENABLE_APB_REG != "TRUE"))) begin + $display("Error: [Unisim %s-212] PHY_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_APB_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_PCLK_INVERT_01_REG != "FALSE") && + (PHY_PCLK_INVERT_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-213] PHY_PCLK_INVERT_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_00_REG < 0) || (READ_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-215] READ_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_01_REG < 0) || (READ_PERCENT_01_REG > 100))) begin + $display("Error: [Unisim %s-216] READ_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_02_REG < 0) || (READ_PERCENT_02_REG > 100))) begin + $display("Error: [Unisim %s-217] READ_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_03_REG < 0) || (READ_PERCENT_03_REG > 100))) begin + $display("Error: [Unisim %s-218] READ_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_04_REG < 0) || (READ_PERCENT_04_REG > 100))) begin + $display("Error: [Unisim %s-219] READ_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_05_REG < 0) || (READ_PERCENT_05_REG > 100))) begin + $display("Error: [Unisim %s-220] READ_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_06_REG < 0) || (READ_PERCENT_06_REG > 100))) begin + $display("Error: [Unisim %s-221] READ_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_07_REG < 0) || (READ_PERCENT_07_REG > 100))) begin + $display("Error: [Unisim %s-222] READ_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_08_REG < 0) || (READ_PERCENT_08_REG > 100))) begin + $display("Error: [Unisim %s-223] READ_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_09_REG < 0) || (READ_PERCENT_09_REG > 100))) begin + $display("Error: [Unisim %s-224] READ_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_10_REG < 0) || (READ_PERCENT_10_REG > 100))) begin + $display("Error: [Unisim %s-225] READ_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_11_REG < 0) || (READ_PERCENT_11_REG > 100))) begin + $display("Error: [Unisim %s-226] READ_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_12_REG < 0) || (READ_PERCENT_12_REG > 100))) begin + $display("Error: [Unisim %s-227] READ_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_13_REG < 0) || (READ_PERCENT_13_REG > 100))) begin + $display("Error: [Unisim %s-228] READ_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_14_REG < 0) || (READ_PERCENT_14_REG > 100))) begin + $display("Error: [Unisim %s-229] READ_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_15_REG < 0) || (READ_PERCENT_15_REG > 100))) begin + $display("Error: [Unisim %s-230] READ_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-231] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STACK_LOCATION_REG != 0) && + (STACK_LOCATION_REG != 1))) begin + $display("Error: [Unisim %s-232] STACK_LOCATION attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, STACK_LOCATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SWITCH_ENABLE_REG != "FALSE") && + (SWITCH_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-233] SWITCH_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_00_REG < 0) || (WRITE_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-235] WRITE_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_01_REG < 0) || (WRITE_PERCENT_01_REG > 100))) begin + $display("Error: [Unisim %s-236] WRITE_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_02_REG < 0) || (WRITE_PERCENT_02_REG > 100))) begin + $display("Error: [Unisim %s-237] WRITE_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_03_REG < 0) || (WRITE_PERCENT_03_REG > 100))) begin + $display("Error: [Unisim %s-238] WRITE_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_04_REG < 0) || (WRITE_PERCENT_04_REG > 100))) begin + $display("Error: [Unisim %s-239] WRITE_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_05_REG < 0) || (WRITE_PERCENT_05_REG > 100))) begin + $display("Error: [Unisim %s-240] WRITE_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_06_REG < 0) || (WRITE_PERCENT_06_REG > 100))) begin + $display("Error: [Unisim %s-241] WRITE_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_07_REG < 0) || (WRITE_PERCENT_07_REG > 100))) begin + $display("Error: [Unisim %s-242] WRITE_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_08_REG < 0) || (WRITE_PERCENT_08_REG > 100))) begin + $display("Error: [Unisim %s-243] WRITE_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_09_REG < 0) || (WRITE_PERCENT_09_REG > 100))) begin + $display("Error: [Unisim %s-244] WRITE_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_10_REG < 0) || (WRITE_PERCENT_10_REG > 100))) begin + $display("Error: [Unisim %s-245] WRITE_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_11_REG < 0) || (WRITE_PERCENT_11_REG > 100))) begin + $display("Error: [Unisim %s-246] WRITE_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_12_REG < 0) || (WRITE_PERCENT_12_REG > 100))) begin + $display("Error: [Unisim %s-247] WRITE_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_13_REG < 0) || (WRITE_PERCENT_13_REG > 100))) begin + $display("Error: [Unisim %s-248] WRITE_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_14_REG < 0) || (WRITE_PERCENT_14_REG > 100))) begin + $display("Error: [Unisim %s-249] WRITE_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_15_REG < 0) || (WRITE_PERCENT_15_REG > 100))) begin + $display("Error: [Unisim %s-250] WRITE_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_15_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + + +assign ANALOG_HBM_SEL_00_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_00_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_01_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_02_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_03_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_04_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_05_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_06_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_07_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_08_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_09_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_10_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_11_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_12_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_13_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_14_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_15_in = 1'b1; // tie off +assign BLI_SCAN_IN_00_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_01_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_02_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_03_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_04_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_05_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_06_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_07_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_08_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_09_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_10_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_11_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_12_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_13_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_14_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_15_in = 8'b11111111; // tie off +assign DBG_IN_00_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_01_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_02_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_03_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_04_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_05_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_06_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_07_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_08_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_09_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_10_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_11_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_12_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_13_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_14_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_15_in = 24'b111111111111111111111111; // tie off +assign DLL_SCAN_CK_00_in = 1'b1; // tie off +assign DLL_SCAN_ENABLE_00_in = 1'b1; // tie off +assign DLL_SCAN_IN_00_in = 2'b11; // tie off +assign DLL_SCAN_MODE_00_in = 1'b1; // tie off +assign DLL_SCAN_RST_N_00_in = 1'b1; // tie off +assign IO_SCAN_CK_00_in = 1'b1; // tie off +assign IO_SCAN_ENABLE_00_in = 1'b1; // tie off +assign IO_SCAN_IN_00_in = 2'b11; // tie off +assign IO_SCAN_MODE_00_in = 1'b1; // tie off +assign IO_SCAN_RST_N_00_in = 1'b1; // tie off +assign MC_SCAN_CK_00_in = 1'b1; // tie off +assign MC_SCAN_CK_01_in = 1'b1; // tie off +assign MC_SCAN_CK_02_in = 1'b1; // tie off +assign MC_SCAN_CK_03_in = 1'b1; // tie off +assign MC_SCAN_CK_04_in = 1'b1; // tie off +assign MC_SCAN_CK_05_in = 1'b1; // tie off +assign MC_SCAN_CK_06_in = 1'b1; // tie off +assign MC_SCAN_CK_07_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_00_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_01_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_02_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_03_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_04_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_05_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_06_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_07_in = 1'b1; // tie off +assign MC_SCAN_IN_00_in = 2'b11; // tie off +assign MC_SCAN_IN_01_in = 2'b11; // tie off +assign MC_SCAN_IN_02_in = 2'b11; // tie off +assign MC_SCAN_IN_03_in = 2'b11; // tie off +assign MC_SCAN_IN_04_in = 2'b11; // tie off +assign MC_SCAN_IN_05_in = 2'b11; // tie off +assign MC_SCAN_IN_06_in = 2'b11; // tie off +assign MC_SCAN_IN_07_in = 2'b11; // tie off +assign MC_SCAN_MODE_00_in = 1'b1; // tie off +assign MC_SCAN_MODE_01_in = 1'b1; // tie off +assign MC_SCAN_MODE_02_in = 1'b1; // tie off +assign MC_SCAN_MODE_03_in = 1'b1; // tie off +assign MC_SCAN_MODE_04_in = 1'b1; // tie off +assign MC_SCAN_MODE_05_in = 1'b1; // tie off +assign MC_SCAN_MODE_06_in = 1'b1; // tie off +assign MC_SCAN_MODE_07_in = 1'b1; // tie off +assign MC_SCAN_RST_N_00_in = 1'b1; // tie off +assign MC_SCAN_RST_N_01_in = 1'b1; // tie off +assign MC_SCAN_RST_N_02_in = 1'b1; // tie off +assign MC_SCAN_RST_N_03_in = 1'b1; // tie off +assign MC_SCAN_RST_N_04_in = 1'b1; // tie off +assign MC_SCAN_RST_N_05_in = 1'b1; // tie off +assign MC_SCAN_RST_N_06_in = 1'b1; // tie off +assign MC_SCAN_RST_N_07_in = 1'b1; // tie off +assign PHY_SCAN_CK_00_in = 1'b1; // tie off +assign PHY_SCAN_ENABLE_00_in = 1'b1; // tie off +assign PHY_SCAN_IN_00_in = 2'b11; // tie off +assign PHY_SCAN_MODE_00_in = 1'b1; // tie off +assign PHY_SCAN_RST_N_00_in = 1'b1; // tie off +assign SW_SCAN_CK_00_in = 1'b1; // tie off +assign SW_SCAN_ENABLE_00_in = 1'b1; // tie off +assign SW_SCAN_IN_00_in = 2'b11; // tie off +assign SW_SCAN_IN_01_in = 2'b11; // tie off +assign SW_SCAN_IN_02_in = 2'b11; // tie off +assign SW_SCAN_IN_03_in = 2'b11; // tie off +assign SW_SCAN_MODE_00_in = 1'b1; // tie off +assign SW_SCAN_RST_N_00_in = 1'b1; // tie off + +SIP_HBM_ONE_STACK_INTF SIP_HBM_ONE_STACK_INTF_INST ( + .ANALOG_MUX_SEL_0 (ANALOG_MUX_SEL_0_REG), + .APB_BYPASS_EN (APB_BYPASS_EN_REG), + .AXI_BYPASS_EN (AXI_BYPASS_EN_REG), + .BLI_TESTMODE_SEL (BLI_TESTMODE_SEL_REG), + .CLK_SEL_00 (CLK_SEL_00_REG), + .CLK_SEL_01 (CLK_SEL_01_REG), + .CLK_SEL_02 (CLK_SEL_02_REG), + .CLK_SEL_03 (CLK_SEL_03_REG), + .CLK_SEL_04 (CLK_SEL_04_REG), + .CLK_SEL_05 (CLK_SEL_05_REG), + .CLK_SEL_06 (CLK_SEL_06_REG), + .CLK_SEL_07 (CLK_SEL_07_REG), + .CLK_SEL_08 (CLK_SEL_08_REG), + .CLK_SEL_09 (CLK_SEL_09_REG), + .CLK_SEL_10 (CLK_SEL_10_REG), + .CLK_SEL_11 (CLK_SEL_11_REG), + .CLK_SEL_12 (CLK_SEL_12_REG), + .CLK_SEL_13 (CLK_SEL_13_REG), + .CLK_SEL_14 (CLK_SEL_14_REG), + .CLK_SEL_15 (CLK_SEL_15_REG), + .DATARATE_00 (DATARATE_00_REG), + .DATARATE_01 (DATARATE_01_REG), + .DATARATE_02 (DATARATE_02_REG), + .DATARATE_03 (DATARATE_03_REG), + .DATARATE_04 (DATARATE_04_REG), + .DATARATE_05 (DATARATE_05_REG), + .DATARATE_06 (DATARATE_06_REG), + .DATARATE_07 (DATARATE_07_REG), + .DA_LOCKOUT (DA_LOCKOUT_REG), + .DBG_BYPASS_VAL (DBG_BYPASS_VAL_REG), + .DEBUG_MODE (DEBUG_MODE_REG), + .DFI_BYPASS_VAL (DFI_BYPASS_VAL_REG), + .DLL_TESTMODE_SEL_0 (DLL_TESTMODE_SEL_0_REG), + .IO_TESTMODE_SEL_0 (IO_TESTMODE_SEL_0_REG), + .IS_APB_0_PCLK_INVERTED (IS_APB_0_PCLK_INVERTED_REG), + .IS_APB_0_PRESET_N_INVERTED (IS_APB_0_PRESET_N_INVERTED_REG), + .IS_AXI_00_ACLK_INVERTED (IS_AXI_00_ACLK_INVERTED_REG), + .IS_AXI_00_ARESET_N_INVERTED (IS_AXI_00_ARESET_N_INVERTED_REG), + .IS_AXI_01_ACLK_INVERTED (IS_AXI_01_ACLK_INVERTED_REG), + .IS_AXI_01_ARESET_N_INVERTED (IS_AXI_01_ARESET_N_INVERTED_REG), + .IS_AXI_02_ACLK_INVERTED (IS_AXI_02_ACLK_INVERTED_REG), + .IS_AXI_02_ARESET_N_INVERTED (IS_AXI_02_ARESET_N_INVERTED_REG), + .IS_AXI_03_ACLK_INVERTED (IS_AXI_03_ACLK_INVERTED_REG), + .IS_AXI_03_ARESET_N_INVERTED (IS_AXI_03_ARESET_N_INVERTED_REG), + .IS_AXI_04_ACLK_INVERTED (IS_AXI_04_ACLK_INVERTED_REG), + .IS_AXI_04_ARESET_N_INVERTED (IS_AXI_04_ARESET_N_INVERTED_REG), + .IS_AXI_05_ACLK_INVERTED (IS_AXI_05_ACLK_INVERTED_REG), + .IS_AXI_05_ARESET_N_INVERTED (IS_AXI_05_ARESET_N_INVERTED_REG), + .IS_AXI_06_ACLK_INVERTED (IS_AXI_06_ACLK_INVERTED_REG), + .IS_AXI_06_ARESET_N_INVERTED (IS_AXI_06_ARESET_N_INVERTED_REG), + .IS_AXI_07_ACLK_INVERTED (IS_AXI_07_ACLK_INVERTED_REG), + .IS_AXI_07_ARESET_N_INVERTED (IS_AXI_07_ARESET_N_INVERTED_REG), + .IS_AXI_08_ACLK_INVERTED (IS_AXI_08_ACLK_INVERTED_REG), + .IS_AXI_08_ARESET_N_INVERTED (IS_AXI_08_ARESET_N_INVERTED_REG), + .IS_AXI_09_ACLK_INVERTED (IS_AXI_09_ACLK_INVERTED_REG), + .IS_AXI_09_ARESET_N_INVERTED (IS_AXI_09_ARESET_N_INVERTED_REG), + .IS_AXI_10_ACLK_INVERTED (IS_AXI_10_ACLK_INVERTED_REG), + .IS_AXI_10_ARESET_N_INVERTED (IS_AXI_10_ARESET_N_INVERTED_REG), + .IS_AXI_11_ACLK_INVERTED (IS_AXI_11_ACLK_INVERTED_REG), + .IS_AXI_11_ARESET_N_INVERTED (IS_AXI_11_ARESET_N_INVERTED_REG), + .IS_AXI_12_ACLK_INVERTED (IS_AXI_12_ACLK_INVERTED_REG), + .IS_AXI_12_ARESET_N_INVERTED (IS_AXI_12_ARESET_N_INVERTED_REG), + .IS_AXI_13_ACLK_INVERTED (IS_AXI_13_ACLK_INVERTED_REG), + .IS_AXI_13_ARESET_N_INVERTED (IS_AXI_13_ARESET_N_INVERTED_REG), + .IS_AXI_14_ACLK_INVERTED (IS_AXI_14_ACLK_INVERTED_REG), + .IS_AXI_14_ARESET_N_INVERTED (IS_AXI_14_ARESET_N_INVERTED_REG), + .IS_AXI_15_ACLK_INVERTED (IS_AXI_15_ACLK_INVERTED_REG), + .IS_AXI_15_ARESET_N_INVERTED (IS_AXI_15_ARESET_N_INVERTED_REG), + .MC_CSSD_SEL_0 (MC_CSSD_SEL_0_REG), + .MC_CSSD_SEL_1 (MC_CSSD_SEL_1_REG), + .MC_CSSD_SEL_2 (MC_CSSD_SEL_2_REG), + .MC_CSSD_SEL_3 (MC_CSSD_SEL_3_REG), + .MC_CSSD_SEL_4 (MC_CSSD_SEL_4_REG), + .MC_CSSD_SEL_5 (MC_CSSD_SEL_5_REG), + .MC_CSSD_SEL_6 (MC_CSSD_SEL_6_REG), + .MC_CSSD_SEL_7 (MC_CSSD_SEL_7_REG), + .MC_ENABLE_0 (MC_ENABLE_0_REG), + .MC_ENABLE_1 (MC_ENABLE_1_REG), + .MC_ENABLE_2 (MC_ENABLE_2_REG), + .MC_ENABLE_3 (MC_ENABLE_3_REG), + .MC_ENABLE_4 (MC_ENABLE_4_REG), + .MC_ENABLE_5 (MC_ENABLE_5_REG), + .MC_ENABLE_6 (MC_ENABLE_6_REG), + .MC_ENABLE_7 (MC_ENABLE_7_REG), + .MC_ENABLE_APB (MC_ENABLE_APB_REG), + .MC_TESTMODE_SEL_0 (MC_TESTMODE_SEL_0_REG), + .MC_TESTMODE_SEL_1 (MC_TESTMODE_SEL_1_REG), + .MC_TESTMODE_SEL_2 (MC_TESTMODE_SEL_2_REG), + .MC_TESTMODE_SEL_3 (MC_TESTMODE_SEL_3_REG), + .MC_TESTMODE_SEL_4 (MC_TESTMODE_SEL_4_REG), + .MC_TESTMODE_SEL_5 (MC_TESTMODE_SEL_5_REG), + .MC_TESTMODE_SEL_6 (MC_TESTMODE_SEL_6_REG), + .MC_TESTMODE_SEL_7 (MC_TESTMODE_SEL_7_REG), + .PAGEHIT_PERCENT_00 (PAGEHIT_PERCENT_00_REG), + .PHY_CSSD_SEL_0 (PHY_CSSD_SEL_0_REG), + .PHY_ENABLE_00 (PHY_ENABLE_00_REG), + .PHY_ENABLE_01 (PHY_ENABLE_01_REG), + .PHY_ENABLE_02 (PHY_ENABLE_02_REG), + .PHY_ENABLE_03 (PHY_ENABLE_03_REG), + .PHY_ENABLE_04 (PHY_ENABLE_04_REG), + .PHY_ENABLE_05 (PHY_ENABLE_05_REG), + .PHY_ENABLE_06 (PHY_ENABLE_06_REG), + .PHY_ENABLE_07 (PHY_ENABLE_07_REG), + .PHY_ENABLE_08 (PHY_ENABLE_08_REG), + .PHY_ENABLE_09 (PHY_ENABLE_09_REG), + .PHY_ENABLE_10 (PHY_ENABLE_10_REG), + .PHY_ENABLE_11 (PHY_ENABLE_11_REG), + .PHY_ENABLE_12 (PHY_ENABLE_12_REG), + .PHY_ENABLE_13 (PHY_ENABLE_13_REG), + .PHY_ENABLE_14 (PHY_ENABLE_14_REG), + .PHY_ENABLE_15 (PHY_ENABLE_15_REG), + .PHY_ENABLE_APB (PHY_ENABLE_APB_REG), + .PHY_PCLK_INVERT_01 (PHY_PCLK_INVERT_01_REG), + .PHY_TESTMODE_SEL_0 (PHY_TESTMODE_SEL_0_REG), + .READ_PERCENT_00 (READ_PERCENT_00_REG), + .READ_PERCENT_01 (READ_PERCENT_01_REG), + .READ_PERCENT_02 (READ_PERCENT_02_REG), + .READ_PERCENT_03 (READ_PERCENT_03_REG), + .READ_PERCENT_04 (READ_PERCENT_04_REG), + .READ_PERCENT_05 (READ_PERCENT_05_REG), + .READ_PERCENT_06 (READ_PERCENT_06_REG), + .READ_PERCENT_07 (READ_PERCENT_07_REG), + .READ_PERCENT_08 (READ_PERCENT_08_REG), + .READ_PERCENT_09 (READ_PERCENT_09_REG), + .READ_PERCENT_10 (READ_PERCENT_10_REG), + .READ_PERCENT_11 (READ_PERCENT_11_REG), + .READ_PERCENT_12 (READ_PERCENT_12_REG), + .READ_PERCENT_13 (READ_PERCENT_13_REG), + .READ_PERCENT_14 (READ_PERCENT_14_REG), + .READ_PERCENT_15 (READ_PERCENT_15_REG), + .STACK_LOCATION (STACK_LOCATION_REG), + .SWITCH_ENABLE (SWITCH_ENABLE_REG), + .SW_TESTMODE_SEL_0 (SW_TESTMODE_SEL_0_REG), + .WRITE_PERCENT_00 (WRITE_PERCENT_00_REG), + .WRITE_PERCENT_01 (WRITE_PERCENT_01_REG), + .WRITE_PERCENT_02 (WRITE_PERCENT_02_REG), + .WRITE_PERCENT_03 (WRITE_PERCENT_03_REG), + .WRITE_PERCENT_04 (WRITE_PERCENT_04_REG), + .WRITE_PERCENT_05 (WRITE_PERCENT_05_REG), + .WRITE_PERCENT_06 (WRITE_PERCENT_06_REG), + .WRITE_PERCENT_07 (WRITE_PERCENT_07_REG), + .WRITE_PERCENT_08 (WRITE_PERCENT_08_REG), + .WRITE_PERCENT_09 (WRITE_PERCENT_09_REG), + .WRITE_PERCENT_10 (WRITE_PERCENT_10_REG), + .WRITE_PERCENT_11 (WRITE_PERCENT_11_REG), + .WRITE_PERCENT_12 (WRITE_PERCENT_12_REG), + .WRITE_PERCENT_13 (WRITE_PERCENT_13_REG), + .WRITE_PERCENT_14 (WRITE_PERCENT_14_REG), + .WRITE_PERCENT_15 (WRITE_PERCENT_15_REG), + .APB_0_PRDATA (APB_0_PRDATA_out), + .APB_0_PREADY (APB_0_PREADY_out), + .APB_0_PSLVERR (APB_0_PSLVERR_out), + .AXI_00_ARREADY (AXI_00_ARREADY_out), + .AXI_00_AWREADY (AXI_00_AWREADY_out), + .AXI_00_BID (AXI_00_BID_out), + .AXI_00_BRESP (AXI_00_BRESP_out), + .AXI_00_BVALID (AXI_00_BVALID_out), + .AXI_00_DFI_AW_AERR_N (AXI_00_DFI_AW_AERR_N_out), + .AXI_00_DFI_CLK_BUF (AXI_00_DFI_CLK_BUF_out), + .AXI_00_DFI_DBI_BYTE_DISABLE (AXI_00_DFI_DBI_BYTE_DISABLE_out), + .AXI_00_DFI_DW_RDDATA_DBI (AXI_00_DFI_DW_RDDATA_DBI_out), + .AXI_00_DFI_DW_RDDATA_DERR (AXI_00_DFI_DW_RDDATA_DERR_out), + .AXI_00_DFI_DW_RDDATA_VALID (AXI_00_DFI_DW_RDDATA_VALID_out), + .AXI_00_DFI_INIT_COMPLETE (AXI_00_DFI_INIT_COMPLETE_out), + .AXI_00_DFI_PHYUPD_REQ (AXI_00_DFI_PHYUPD_REQ_out), + .AXI_00_DFI_PHY_LP_STATE (AXI_00_DFI_PHY_LP_STATE_out), + .AXI_00_DFI_RST_N_BUF (AXI_00_DFI_RST_N_BUF_out), + .AXI_00_MC_STATUS (AXI_00_MC_STATUS_out), + .AXI_00_PHY_STATUS (AXI_00_PHY_STATUS_out), + .AXI_00_RDATA (AXI_00_RDATA_out), + .AXI_00_RDATA_PARITY (AXI_00_RDATA_PARITY_out), + .AXI_00_RID (AXI_00_RID_out), + .AXI_00_RLAST (AXI_00_RLAST_out), + .AXI_00_RRESP (AXI_00_RRESP_out), + .AXI_00_RVALID (AXI_00_RVALID_out), + .AXI_00_WREADY (AXI_00_WREADY_out), + .AXI_01_ARREADY (AXI_01_ARREADY_out), + .AXI_01_AWREADY (AXI_01_AWREADY_out), + .AXI_01_BID (AXI_01_BID_out), + .AXI_01_BRESP (AXI_01_BRESP_out), + .AXI_01_BVALID (AXI_01_BVALID_out), + .AXI_01_DFI_AW_AERR_N (AXI_01_DFI_AW_AERR_N_out), + .AXI_01_DFI_CLK_BUF (AXI_01_DFI_CLK_BUF_out), + .AXI_01_DFI_DBI_BYTE_DISABLE (AXI_01_DFI_DBI_BYTE_DISABLE_out), + .AXI_01_DFI_DW_RDDATA_DBI (AXI_01_DFI_DW_RDDATA_DBI_out), + .AXI_01_DFI_DW_RDDATA_DERR (AXI_01_DFI_DW_RDDATA_DERR_out), + .AXI_01_DFI_DW_RDDATA_VALID (AXI_01_DFI_DW_RDDATA_VALID_out), + .AXI_01_DFI_INIT_COMPLETE (AXI_01_DFI_INIT_COMPLETE_out), + .AXI_01_DFI_PHYUPD_REQ (AXI_01_DFI_PHYUPD_REQ_out), + .AXI_01_DFI_PHY_LP_STATE (AXI_01_DFI_PHY_LP_STATE_out), + .AXI_01_DFI_RST_N_BUF (AXI_01_DFI_RST_N_BUF_out), + .AXI_01_RDATA (AXI_01_RDATA_out), + .AXI_01_RDATA_PARITY (AXI_01_RDATA_PARITY_out), + .AXI_01_RID (AXI_01_RID_out), + .AXI_01_RLAST (AXI_01_RLAST_out), + .AXI_01_RRESP (AXI_01_RRESP_out), + .AXI_01_RVALID (AXI_01_RVALID_out), + .AXI_01_WREADY (AXI_01_WREADY_out), + .AXI_02_ARREADY (AXI_02_ARREADY_out), + .AXI_02_AWREADY (AXI_02_AWREADY_out), + .AXI_02_BID (AXI_02_BID_out), + .AXI_02_BRESP (AXI_02_BRESP_out), + .AXI_02_BVALID (AXI_02_BVALID_out), + .AXI_02_DFI_AW_AERR_N (AXI_02_DFI_AW_AERR_N_out), + .AXI_02_DFI_CLK_BUF (AXI_02_DFI_CLK_BUF_out), + .AXI_02_DFI_DBI_BYTE_DISABLE (AXI_02_DFI_DBI_BYTE_DISABLE_out), + .AXI_02_DFI_DW_RDDATA_DBI (AXI_02_DFI_DW_RDDATA_DBI_out), + .AXI_02_DFI_DW_RDDATA_DERR (AXI_02_DFI_DW_RDDATA_DERR_out), + .AXI_02_DFI_DW_RDDATA_VALID (AXI_02_DFI_DW_RDDATA_VALID_out), + .AXI_02_DFI_INIT_COMPLETE (AXI_02_DFI_INIT_COMPLETE_out), + .AXI_02_DFI_PHYUPD_REQ (AXI_02_DFI_PHYUPD_REQ_out), + .AXI_02_DFI_PHY_LP_STATE (AXI_02_DFI_PHY_LP_STATE_out), + .AXI_02_DFI_RST_N_BUF (AXI_02_DFI_RST_N_BUF_out), + .AXI_02_MC_STATUS (AXI_02_MC_STATUS_out), + .AXI_02_PHY_STATUS (AXI_02_PHY_STATUS_out), + .AXI_02_RDATA (AXI_02_RDATA_out), + .AXI_02_RDATA_PARITY (AXI_02_RDATA_PARITY_out), + .AXI_02_RID (AXI_02_RID_out), + .AXI_02_RLAST (AXI_02_RLAST_out), + .AXI_02_RRESP (AXI_02_RRESP_out), + .AXI_02_RVALID (AXI_02_RVALID_out), + .AXI_02_WREADY (AXI_02_WREADY_out), + .AXI_03_ARREADY (AXI_03_ARREADY_out), + .AXI_03_AWREADY (AXI_03_AWREADY_out), + .AXI_03_BID (AXI_03_BID_out), + .AXI_03_BRESP (AXI_03_BRESP_out), + .AXI_03_BVALID (AXI_03_BVALID_out), + .AXI_03_DFI_AW_AERR_N (AXI_03_DFI_AW_AERR_N_out), + .AXI_03_DFI_CLK_BUF (AXI_03_DFI_CLK_BUF_out), + .AXI_03_DFI_DBI_BYTE_DISABLE (AXI_03_DFI_DBI_BYTE_DISABLE_out), + .AXI_03_DFI_DW_RDDATA_DBI (AXI_03_DFI_DW_RDDATA_DBI_out), + .AXI_03_DFI_DW_RDDATA_DERR (AXI_03_DFI_DW_RDDATA_DERR_out), + .AXI_03_DFI_DW_RDDATA_VALID (AXI_03_DFI_DW_RDDATA_VALID_out), + .AXI_03_DFI_INIT_COMPLETE (AXI_03_DFI_INIT_COMPLETE_out), + .AXI_03_DFI_PHYUPD_REQ (AXI_03_DFI_PHYUPD_REQ_out), + .AXI_03_DFI_PHY_LP_STATE (AXI_03_DFI_PHY_LP_STATE_out), + .AXI_03_DFI_RST_N_BUF (AXI_03_DFI_RST_N_BUF_out), + .AXI_03_RDATA (AXI_03_RDATA_out), + .AXI_03_RDATA_PARITY (AXI_03_RDATA_PARITY_out), + .AXI_03_RID (AXI_03_RID_out), + .AXI_03_RLAST (AXI_03_RLAST_out), + .AXI_03_RRESP (AXI_03_RRESP_out), + .AXI_03_RVALID (AXI_03_RVALID_out), + .AXI_03_WREADY (AXI_03_WREADY_out), + .AXI_04_ARREADY (AXI_04_ARREADY_out), + .AXI_04_AWREADY (AXI_04_AWREADY_out), + .AXI_04_BID (AXI_04_BID_out), + .AXI_04_BRESP (AXI_04_BRESP_out), + .AXI_04_BVALID (AXI_04_BVALID_out), + .AXI_04_DFI_AW_AERR_N (AXI_04_DFI_AW_AERR_N_out), + .AXI_04_DFI_CLK_BUF (AXI_04_DFI_CLK_BUF_out), + .AXI_04_DFI_DBI_BYTE_DISABLE (AXI_04_DFI_DBI_BYTE_DISABLE_out), + .AXI_04_DFI_DW_RDDATA_DBI (AXI_04_DFI_DW_RDDATA_DBI_out), + .AXI_04_DFI_DW_RDDATA_DERR (AXI_04_DFI_DW_RDDATA_DERR_out), + .AXI_04_DFI_DW_RDDATA_VALID (AXI_04_DFI_DW_RDDATA_VALID_out), + .AXI_04_DFI_INIT_COMPLETE (AXI_04_DFI_INIT_COMPLETE_out), + .AXI_04_DFI_PHYUPD_REQ (AXI_04_DFI_PHYUPD_REQ_out), + .AXI_04_DFI_PHY_LP_STATE (AXI_04_DFI_PHY_LP_STATE_out), + .AXI_04_DFI_RST_N_BUF (AXI_04_DFI_RST_N_BUF_out), + .AXI_04_MC_STATUS (AXI_04_MC_STATUS_out), + .AXI_04_PHY_STATUS (AXI_04_PHY_STATUS_out), + .AXI_04_RDATA (AXI_04_RDATA_out), + .AXI_04_RDATA_PARITY (AXI_04_RDATA_PARITY_out), + .AXI_04_RID (AXI_04_RID_out), + .AXI_04_RLAST (AXI_04_RLAST_out), + .AXI_04_RRESP (AXI_04_RRESP_out), + .AXI_04_RVALID (AXI_04_RVALID_out), + .AXI_04_WREADY (AXI_04_WREADY_out), + .AXI_05_ARREADY (AXI_05_ARREADY_out), + .AXI_05_AWREADY (AXI_05_AWREADY_out), + .AXI_05_BID (AXI_05_BID_out), + .AXI_05_BRESP (AXI_05_BRESP_out), + .AXI_05_BVALID (AXI_05_BVALID_out), + .AXI_05_DFI_AW_AERR_N (AXI_05_DFI_AW_AERR_N_out), + .AXI_05_DFI_CLK_BUF (AXI_05_DFI_CLK_BUF_out), + .AXI_05_DFI_DBI_BYTE_DISABLE (AXI_05_DFI_DBI_BYTE_DISABLE_out), + .AXI_05_DFI_DW_RDDATA_DBI (AXI_05_DFI_DW_RDDATA_DBI_out), + .AXI_05_DFI_DW_RDDATA_DERR (AXI_05_DFI_DW_RDDATA_DERR_out), + .AXI_05_DFI_DW_RDDATA_VALID (AXI_05_DFI_DW_RDDATA_VALID_out), + .AXI_05_DFI_INIT_COMPLETE (AXI_05_DFI_INIT_COMPLETE_out), + .AXI_05_DFI_PHYUPD_REQ (AXI_05_DFI_PHYUPD_REQ_out), + .AXI_05_DFI_PHY_LP_STATE (AXI_05_DFI_PHY_LP_STATE_out), + .AXI_05_DFI_RST_N_BUF (AXI_05_DFI_RST_N_BUF_out), + .AXI_05_RDATA (AXI_05_RDATA_out), + .AXI_05_RDATA_PARITY (AXI_05_RDATA_PARITY_out), + .AXI_05_RID (AXI_05_RID_out), + .AXI_05_RLAST (AXI_05_RLAST_out), + .AXI_05_RRESP (AXI_05_RRESP_out), + .AXI_05_RVALID (AXI_05_RVALID_out), + .AXI_05_WREADY (AXI_05_WREADY_out), + .AXI_06_ARREADY (AXI_06_ARREADY_out), + .AXI_06_AWREADY (AXI_06_AWREADY_out), + .AXI_06_BID (AXI_06_BID_out), + .AXI_06_BRESP (AXI_06_BRESP_out), + .AXI_06_BVALID (AXI_06_BVALID_out), + .AXI_06_DFI_AW_AERR_N (AXI_06_DFI_AW_AERR_N_out), + .AXI_06_DFI_CLK_BUF (AXI_06_DFI_CLK_BUF_out), + .AXI_06_DFI_DBI_BYTE_DISABLE (AXI_06_DFI_DBI_BYTE_DISABLE_out), + .AXI_06_DFI_DW_RDDATA_DBI (AXI_06_DFI_DW_RDDATA_DBI_out), + .AXI_06_DFI_DW_RDDATA_DERR (AXI_06_DFI_DW_RDDATA_DERR_out), + .AXI_06_DFI_DW_RDDATA_VALID (AXI_06_DFI_DW_RDDATA_VALID_out), + .AXI_06_DFI_INIT_COMPLETE (AXI_06_DFI_INIT_COMPLETE_out), + .AXI_06_DFI_PHYUPD_REQ (AXI_06_DFI_PHYUPD_REQ_out), + .AXI_06_DFI_PHY_LP_STATE (AXI_06_DFI_PHY_LP_STATE_out), + .AXI_06_DFI_RST_N_BUF (AXI_06_DFI_RST_N_BUF_out), + .AXI_06_MC_STATUS (AXI_06_MC_STATUS_out), + .AXI_06_PHY_STATUS (AXI_06_PHY_STATUS_out), + .AXI_06_RDATA (AXI_06_RDATA_out), + .AXI_06_RDATA_PARITY (AXI_06_RDATA_PARITY_out), + .AXI_06_RID (AXI_06_RID_out), + .AXI_06_RLAST (AXI_06_RLAST_out), + .AXI_06_RRESP (AXI_06_RRESP_out), + .AXI_06_RVALID (AXI_06_RVALID_out), + .AXI_06_WREADY (AXI_06_WREADY_out), + .AXI_07_ARREADY (AXI_07_ARREADY_out), + .AXI_07_AWREADY (AXI_07_AWREADY_out), + .AXI_07_BID (AXI_07_BID_out), + .AXI_07_BRESP (AXI_07_BRESP_out), + .AXI_07_BVALID (AXI_07_BVALID_out), + .AXI_07_DFI_AW_AERR_N (AXI_07_DFI_AW_AERR_N_out), + .AXI_07_DFI_CLK_BUF (AXI_07_DFI_CLK_BUF_out), + .AXI_07_DFI_DBI_BYTE_DISABLE (AXI_07_DFI_DBI_BYTE_DISABLE_out), + .AXI_07_DFI_DW_RDDATA_DBI (AXI_07_DFI_DW_RDDATA_DBI_out), + .AXI_07_DFI_DW_RDDATA_DERR (AXI_07_DFI_DW_RDDATA_DERR_out), + .AXI_07_DFI_DW_RDDATA_VALID (AXI_07_DFI_DW_RDDATA_VALID_out), + .AXI_07_DFI_INIT_COMPLETE (AXI_07_DFI_INIT_COMPLETE_out), + .AXI_07_DFI_PHYUPD_REQ (AXI_07_DFI_PHYUPD_REQ_out), + .AXI_07_DFI_PHY_LP_STATE (AXI_07_DFI_PHY_LP_STATE_out), + .AXI_07_DFI_RST_N_BUF (AXI_07_DFI_RST_N_BUF_out), + .AXI_07_RDATA (AXI_07_RDATA_out), + .AXI_07_RDATA_PARITY (AXI_07_RDATA_PARITY_out), + .AXI_07_RID (AXI_07_RID_out), + .AXI_07_RLAST (AXI_07_RLAST_out), + .AXI_07_RRESP (AXI_07_RRESP_out), + .AXI_07_RVALID (AXI_07_RVALID_out), + .AXI_07_WREADY (AXI_07_WREADY_out), + .AXI_08_ARREADY (AXI_08_ARREADY_out), + .AXI_08_AWREADY (AXI_08_AWREADY_out), + .AXI_08_BID (AXI_08_BID_out), + .AXI_08_BRESP (AXI_08_BRESP_out), + .AXI_08_BVALID (AXI_08_BVALID_out), + .AXI_08_DFI_AW_AERR_N (AXI_08_DFI_AW_AERR_N_out), + .AXI_08_DFI_CLK_BUF (AXI_08_DFI_CLK_BUF_out), + .AXI_08_DFI_DBI_BYTE_DISABLE (AXI_08_DFI_DBI_BYTE_DISABLE_out), + .AXI_08_DFI_DW_RDDATA_DBI (AXI_08_DFI_DW_RDDATA_DBI_out), + .AXI_08_DFI_DW_RDDATA_DERR (AXI_08_DFI_DW_RDDATA_DERR_out), + .AXI_08_DFI_DW_RDDATA_VALID (AXI_08_DFI_DW_RDDATA_VALID_out), + .AXI_08_DFI_INIT_COMPLETE (AXI_08_DFI_INIT_COMPLETE_out), + .AXI_08_DFI_PHYUPD_REQ (AXI_08_DFI_PHYUPD_REQ_out), + .AXI_08_DFI_PHY_LP_STATE (AXI_08_DFI_PHY_LP_STATE_out), + .AXI_08_DFI_RST_N_BUF (AXI_08_DFI_RST_N_BUF_out), + .AXI_08_MC_STATUS (AXI_08_MC_STATUS_out), + .AXI_08_PHY_STATUS (AXI_08_PHY_STATUS_out), + .AXI_08_RDATA (AXI_08_RDATA_out), + .AXI_08_RDATA_PARITY (AXI_08_RDATA_PARITY_out), + .AXI_08_RID (AXI_08_RID_out), + .AXI_08_RLAST (AXI_08_RLAST_out), + .AXI_08_RRESP (AXI_08_RRESP_out), + .AXI_08_RVALID (AXI_08_RVALID_out), + .AXI_08_WREADY (AXI_08_WREADY_out), + .AXI_09_ARREADY (AXI_09_ARREADY_out), + .AXI_09_AWREADY (AXI_09_AWREADY_out), + .AXI_09_BID (AXI_09_BID_out), + .AXI_09_BRESP (AXI_09_BRESP_out), + .AXI_09_BVALID (AXI_09_BVALID_out), + .AXI_09_DFI_AW_AERR_N (AXI_09_DFI_AW_AERR_N_out), + .AXI_09_DFI_CLK_BUF (AXI_09_DFI_CLK_BUF_out), + .AXI_09_DFI_DBI_BYTE_DISABLE (AXI_09_DFI_DBI_BYTE_DISABLE_out), + .AXI_09_DFI_DW_RDDATA_DBI (AXI_09_DFI_DW_RDDATA_DBI_out), + .AXI_09_DFI_DW_RDDATA_DERR (AXI_09_DFI_DW_RDDATA_DERR_out), + .AXI_09_DFI_DW_RDDATA_VALID (AXI_09_DFI_DW_RDDATA_VALID_out), + .AXI_09_DFI_INIT_COMPLETE (AXI_09_DFI_INIT_COMPLETE_out), + .AXI_09_DFI_PHYUPD_REQ (AXI_09_DFI_PHYUPD_REQ_out), + .AXI_09_DFI_PHY_LP_STATE (AXI_09_DFI_PHY_LP_STATE_out), + .AXI_09_DFI_RST_N_BUF (AXI_09_DFI_RST_N_BUF_out), + .AXI_09_RDATA (AXI_09_RDATA_out), + .AXI_09_RDATA_PARITY (AXI_09_RDATA_PARITY_out), + .AXI_09_RID (AXI_09_RID_out), + .AXI_09_RLAST (AXI_09_RLAST_out), + .AXI_09_RRESP (AXI_09_RRESP_out), + .AXI_09_RVALID (AXI_09_RVALID_out), + .AXI_09_WREADY (AXI_09_WREADY_out), + .AXI_10_ARREADY (AXI_10_ARREADY_out), + .AXI_10_AWREADY (AXI_10_AWREADY_out), + .AXI_10_BID (AXI_10_BID_out), + .AXI_10_BRESP (AXI_10_BRESP_out), + .AXI_10_BVALID (AXI_10_BVALID_out), + .AXI_10_DFI_AW_AERR_N (AXI_10_DFI_AW_AERR_N_out), + .AXI_10_DFI_CLK_BUF (AXI_10_DFI_CLK_BUF_out), + .AXI_10_DFI_DBI_BYTE_DISABLE (AXI_10_DFI_DBI_BYTE_DISABLE_out), + .AXI_10_DFI_DW_RDDATA_DBI (AXI_10_DFI_DW_RDDATA_DBI_out), + .AXI_10_DFI_DW_RDDATA_DERR (AXI_10_DFI_DW_RDDATA_DERR_out), + .AXI_10_DFI_DW_RDDATA_VALID (AXI_10_DFI_DW_RDDATA_VALID_out), + .AXI_10_DFI_INIT_COMPLETE (AXI_10_DFI_INIT_COMPLETE_out), + .AXI_10_DFI_PHYUPD_REQ (AXI_10_DFI_PHYUPD_REQ_out), + .AXI_10_DFI_PHY_LP_STATE (AXI_10_DFI_PHY_LP_STATE_out), + .AXI_10_DFI_RST_N_BUF (AXI_10_DFI_RST_N_BUF_out), + .AXI_10_MC_STATUS (AXI_10_MC_STATUS_out), + .AXI_10_PHY_STATUS (AXI_10_PHY_STATUS_out), + .AXI_10_RDATA (AXI_10_RDATA_out), + .AXI_10_RDATA_PARITY (AXI_10_RDATA_PARITY_out), + .AXI_10_RID (AXI_10_RID_out), + .AXI_10_RLAST (AXI_10_RLAST_out), + .AXI_10_RRESP (AXI_10_RRESP_out), + .AXI_10_RVALID (AXI_10_RVALID_out), + .AXI_10_WREADY (AXI_10_WREADY_out), + .AXI_11_ARREADY (AXI_11_ARREADY_out), + .AXI_11_AWREADY (AXI_11_AWREADY_out), + .AXI_11_BID (AXI_11_BID_out), + .AXI_11_BRESP (AXI_11_BRESP_out), + .AXI_11_BVALID (AXI_11_BVALID_out), + .AXI_11_DFI_AW_AERR_N (AXI_11_DFI_AW_AERR_N_out), + .AXI_11_DFI_CLK_BUF (AXI_11_DFI_CLK_BUF_out), + .AXI_11_DFI_DBI_BYTE_DISABLE (AXI_11_DFI_DBI_BYTE_DISABLE_out), + .AXI_11_DFI_DW_RDDATA_DBI (AXI_11_DFI_DW_RDDATA_DBI_out), + .AXI_11_DFI_DW_RDDATA_DERR (AXI_11_DFI_DW_RDDATA_DERR_out), + .AXI_11_DFI_DW_RDDATA_VALID (AXI_11_DFI_DW_RDDATA_VALID_out), + .AXI_11_DFI_INIT_COMPLETE (AXI_11_DFI_INIT_COMPLETE_out), + .AXI_11_DFI_PHYUPD_REQ (AXI_11_DFI_PHYUPD_REQ_out), + .AXI_11_DFI_PHY_LP_STATE (AXI_11_DFI_PHY_LP_STATE_out), + .AXI_11_DFI_RST_N_BUF (AXI_11_DFI_RST_N_BUF_out), + .AXI_11_RDATA (AXI_11_RDATA_out), + .AXI_11_RDATA_PARITY (AXI_11_RDATA_PARITY_out), + .AXI_11_RID (AXI_11_RID_out), + .AXI_11_RLAST (AXI_11_RLAST_out), + .AXI_11_RRESP (AXI_11_RRESP_out), + .AXI_11_RVALID (AXI_11_RVALID_out), + .AXI_11_WREADY (AXI_11_WREADY_out), + .AXI_12_ARREADY (AXI_12_ARREADY_out), + .AXI_12_AWREADY (AXI_12_AWREADY_out), + .AXI_12_BID (AXI_12_BID_out), + .AXI_12_BRESP (AXI_12_BRESP_out), + .AXI_12_BVALID (AXI_12_BVALID_out), + .AXI_12_DFI_AW_AERR_N (AXI_12_DFI_AW_AERR_N_out), + .AXI_12_DFI_CLK_BUF (AXI_12_DFI_CLK_BUF_out), + .AXI_12_DFI_DBI_BYTE_DISABLE (AXI_12_DFI_DBI_BYTE_DISABLE_out), + .AXI_12_DFI_DW_RDDATA_DBI (AXI_12_DFI_DW_RDDATA_DBI_out), + .AXI_12_DFI_DW_RDDATA_DERR (AXI_12_DFI_DW_RDDATA_DERR_out), + .AXI_12_DFI_DW_RDDATA_VALID (AXI_12_DFI_DW_RDDATA_VALID_out), + .AXI_12_DFI_INIT_COMPLETE (AXI_12_DFI_INIT_COMPLETE_out), + .AXI_12_DFI_PHYUPD_REQ (AXI_12_DFI_PHYUPD_REQ_out), + .AXI_12_DFI_PHY_LP_STATE (AXI_12_DFI_PHY_LP_STATE_out), + .AXI_12_DFI_RST_N_BUF (AXI_12_DFI_RST_N_BUF_out), + .AXI_12_MC_STATUS (AXI_12_MC_STATUS_out), + .AXI_12_PHY_STATUS (AXI_12_PHY_STATUS_out), + .AXI_12_RDATA (AXI_12_RDATA_out), + .AXI_12_RDATA_PARITY (AXI_12_RDATA_PARITY_out), + .AXI_12_RID (AXI_12_RID_out), + .AXI_12_RLAST (AXI_12_RLAST_out), + .AXI_12_RRESP (AXI_12_RRESP_out), + .AXI_12_RVALID (AXI_12_RVALID_out), + .AXI_12_WREADY (AXI_12_WREADY_out), + .AXI_13_ARREADY (AXI_13_ARREADY_out), + .AXI_13_AWREADY (AXI_13_AWREADY_out), + .AXI_13_BID (AXI_13_BID_out), + .AXI_13_BRESP (AXI_13_BRESP_out), + .AXI_13_BVALID (AXI_13_BVALID_out), + .AXI_13_DFI_AW_AERR_N (AXI_13_DFI_AW_AERR_N_out), + .AXI_13_DFI_CLK_BUF (AXI_13_DFI_CLK_BUF_out), + .AXI_13_DFI_DBI_BYTE_DISABLE (AXI_13_DFI_DBI_BYTE_DISABLE_out), + .AXI_13_DFI_DW_RDDATA_DBI (AXI_13_DFI_DW_RDDATA_DBI_out), + .AXI_13_DFI_DW_RDDATA_DERR (AXI_13_DFI_DW_RDDATA_DERR_out), + .AXI_13_DFI_DW_RDDATA_VALID (AXI_13_DFI_DW_RDDATA_VALID_out), + .AXI_13_DFI_INIT_COMPLETE (AXI_13_DFI_INIT_COMPLETE_out), + .AXI_13_DFI_PHYUPD_REQ (AXI_13_DFI_PHYUPD_REQ_out), + .AXI_13_DFI_PHY_LP_STATE (AXI_13_DFI_PHY_LP_STATE_out), + .AXI_13_DFI_RST_N_BUF (AXI_13_DFI_RST_N_BUF_out), + .AXI_13_RDATA (AXI_13_RDATA_out), + .AXI_13_RDATA_PARITY (AXI_13_RDATA_PARITY_out), + .AXI_13_RID (AXI_13_RID_out), + .AXI_13_RLAST (AXI_13_RLAST_out), + .AXI_13_RRESP (AXI_13_RRESP_out), + .AXI_13_RVALID (AXI_13_RVALID_out), + .AXI_13_WREADY (AXI_13_WREADY_out), + .AXI_14_ARREADY (AXI_14_ARREADY_out), + .AXI_14_AWREADY (AXI_14_AWREADY_out), + .AXI_14_BID (AXI_14_BID_out), + .AXI_14_BRESP (AXI_14_BRESP_out), + .AXI_14_BVALID (AXI_14_BVALID_out), + .AXI_14_DFI_AW_AERR_N (AXI_14_DFI_AW_AERR_N_out), + .AXI_14_DFI_CLK_BUF (AXI_14_DFI_CLK_BUF_out), + .AXI_14_DFI_DBI_BYTE_DISABLE (AXI_14_DFI_DBI_BYTE_DISABLE_out), + .AXI_14_DFI_DW_RDDATA_DBI (AXI_14_DFI_DW_RDDATA_DBI_out), + .AXI_14_DFI_DW_RDDATA_DERR (AXI_14_DFI_DW_RDDATA_DERR_out), + .AXI_14_DFI_DW_RDDATA_VALID (AXI_14_DFI_DW_RDDATA_VALID_out), + .AXI_14_DFI_INIT_COMPLETE (AXI_14_DFI_INIT_COMPLETE_out), + .AXI_14_DFI_PHYUPD_REQ (AXI_14_DFI_PHYUPD_REQ_out), + .AXI_14_DFI_PHY_LP_STATE (AXI_14_DFI_PHY_LP_STATE_out), + .AXI_14_DFI_RST_N_BUF (AXI_14_DFI_RST_N_BUF_out), + .AXI_14_MC_STATUS (AXI_14_MC_STATUS_out), + .AXI_14_PHY_STATUS (AXI_14_PHY_STATUS_out), + .AXI_14_RDATA (AXI_14_RDATA_out), + .AXI_14_RDATA_PARITY (AXI_14_RDATA_PARITY_out), + .AXI_14_RID (AXI_14_RID_out), + .AXI_14_RLAST (AXI_14_RLAST_out), + .AXI_14_RRESP (AXI_14_RRESP_out), + .AXI_14_RVALID (AXI_14_RVALID_out), + .AXI_14_WREADY (AXI_14_WREADY_out), + .AXI_15_ARREADY (AXI_15_ARREADY_out), + .AXI_15_AWREADY (AXI_15_AWREADY_out), + .AXI_15_BID (AXI_15_BID_out), + .AXI_15_BRESP (AXI_15_BRESP_out), + .AXI_15_BVALID (AXI_15_BVALID_out), + .AXI_15_DFI_AW_AERR_N (AXI_15_DFI_AW_AERR_N_out), + .AXI_15_DFI_CLK_BUF (AXI_15_DFI_CLK_BUF_out), + .AXI_15_DFI_DBI_BYTE_DISABLE (AXI_15_DFI_DBI_BYTE_DISABLE_out), + .AXI_15_DFI_DW_RDDATA_DBI (AXI_15_DFI_DW_RDDATA_DBI_out), + .AXI_15_DFI_DW_RDDATA_DERR (AXI_15_DFI_DW_RDDATA_DERR_out), + .AXI_15_DFI_DW_RDDATA_VALID (AXI_15_DFI_DW_RDDATA_VALID_out), + .AXI_15_DFI_INIT_COMPLETE (AXI_15_DFI_INIT_COMPLETE_out), + .AXI_15_DFI_PHYUPD_REQ (AXI_15_DFI_PHYUPD_REQ_out), + .AXI_15_DFI_PHY_LP_STATE (AXI_15_DFI_PHY_LP_STATE_out), + .AXI_15_DFI_RST_N_BUF (AXI_15_DFI_RST_N_BUF_out), + .AXI_15_RDATA (AXI_15_RDATA_out), + .AXI_15_RDATA_PARITY (AXI_15_RDATA_PARITY_out), + .AXI_15_RID (AXI_15_RID_out), + .AXI_15_RLAST (AXI_15_RLAST_out), + .AXI_15_RRESP (AXI_15_RRESP_out), + .AXI_15_RVALID (AXI_15_RVALID_out), + .AXI_15_WREADY (AXI_15_WREADY_out), + .BLI_SCAN_OUT_00 (BLI_SCAN_OUT_00_out), + .BLI_SCAN_OUT_01 (BLI_SCAN_OUT_01_out), + .BLI_SCAN_OUT_02 (BLI_SCAN_OUT_02_out), + .BLI_SCAN_OUT_03 (BLI_SCAN_OUT_03_out), + .BLI_SCAN_OUT_04 (BLI_SCAN_OUT_04_out), + .BLI_SCAN_OUT_05 (BLI_SCAN_OUT_05_out), + .BLI_SCAN_OUT_06 (BLI_SCAN_OUT_06_out), + .BLI_SCAN_OUT_07 (BLI_SCAN_OUT_07_out), + .BLI_SCAN_OUT_08 (BLI_SCAN_OUT_08_out), + .BLI_SCAN_OUT_09 (BLI_SCAN_OUT_09_out), + .BLI_SCAN_OUT_10 (BLI_SCAN_OUT_10_out), + .BLI_SCAN_OUT_11 (BLI_SCAN_OUT_11_out), + .BLI_SCAN_OUT_12 (BLI_SCAN_OUT_12_out), + .BLI_SCAN_OUT_13 (BLI_SCAN_OUT_13_out), + .BLI_SCAN_OUT_14 (BLI_SCAN_OUT_14_out), + .BLI_SCAN_OUT_15 (BLI_SCAN_OUT_15_out), + .DBG_OUT_00 (DBG_OUT_00_out), + .DBG_OUT_01 (DBG_OUT_01_out), + .DBG_OUT_02 (DBG_OUT_02_out), + .DBG_OUT_03 (DBG_OUT_03_out), + .DBG_OUT_04 (DBG_OUT_04_out), + .DBG_OUT_05 (DBG_OUT_05_out), + .DBG_OUT_06 (DBG_OUT_06_out), + .DBG_OUT_07 (DBG_OUT_07_out), + .DBG_OUT_08 (DBG_OUT_08_out), + .DBG_OUT_09 (DBG_OUT_09_out), + .DBG_OUT_10 (DBG_OUT_10_out), + .DBG_OUT_11 (DBG_OUT_11_out), + .DBG_OUT_12 (DBG_OUT_12_out), + .DBG_OUT_13 (DBG_OUT_13_out), + .DBG_OUT_14 (DBG_OUT_14_out), + .DBG_OUT_15 (DBG_OUT_15_out), + .DLL_SCAN_OUT_00 (DLL_SCAN_OUT_00_out), + .DRAM_0_STAT_CATTRIP (DRAM_0_STAT_CATTRIP_out), + .DRAM_0_STAT_TEMP (DRAM_0_STAT_TEMP_out), + .IO_SCAN_OUT_00 (IO_SCAN_OUT_00_out), + .MC_SCAN_OUT_00 (MC_SCAN_OUT_00_out), + .MC_SCAN_OUT_01 (MC_SCAN_OUT_01_out), + .MC_SCAN_OUT_02 (MC_SCAN_OUT_02_out), + .MC_SCAN_OUT_03 (MC_SCAN_OUT_03_out), + .MC_SCAN_OUT_04 (MC_SCAN_OUT_04_out), + .MC_SCAN_OUT_05 (MC_SCAN_OUT_05_out), + .MC_SCAN_OUT_06 (MC_SCAN_OUT_06_out), + .MC_SCAN_OUT_07 (MC_SCAN_OUT_07_out), + .PHY_SCAN_OUT_00 (PHY_SCAN_OUT_00_out), + .STATUS_00 (STATUS_00_out), + .STATUS_01 (STATUS_01_out), + .STATUS_02 (STATUS_02_out), + .STATUS_03 (STATUS_03_out), + .STATUS_04 (STATUS_04_out), + .STATUS_05 (STATUS_05_out), + .STATUS_06 (STATUS_06_out), + .STATUS_07 (STATUS_07_out), + .SW_SCAN_OUT_00 (SW_SCAN_OUT_00_out), + .SW_SCAN_OUT_01 (SW_SCAN_OUT_01_out), + .SW_SCAN_OUT_02 (SW_SCAN_OUT_02_out), + .SW_SCAN_OUT_03 (SW_SCAN_OUT_03_out), + .ANALOG_HBM_SEL_00 (ANALOG_HBM_SEL_00_in), + .APB_0_PADDR (APB_0_PADDR_in), + .APB_0_PCLK (APB_0_PCLK_in), + .APB_0_PENABLE (APB_0_PENABLE_in), + .APB_0_PRESET_N (APB_0_PRESET_N_in), + .APB_0_PSEL (APB_0_PSEL_in), + .APB_0_PWDATA (APB_0_PWDATA_in), + .APB_0_PWRITE (APB_0_PWRITE_in), + .AXI_00_ACLK (AXI_00_ACLK_in), + .AXI_00_ARADDR (AXI_00_ARADDR_in), + .AXI_00_ARBURST (AXI_00_ARBURST_in), + .AXI_00_ARESET_N (AXI_00_ARESET_N_in), + .AXI_00_ARID (AXI_00_ARID_in), + .AXI_00_ARLEN (AXI_00_ARLEN_in), + .AXI_00_ARSIZE (AXI_00_ARSIZE_in), + .AXI_00_ARVALID (AXI_00_ARVALID_in), + .AXI_00_AWADDR (AXI_00_AWADDR_in), + .AXI_00_AWBURST (AXI_00_AWBURST_in), + .AXI_00_AWID (AXI_00_AWID_in), + .AXI_00_AWLEN (AXI_00_AWLEN_in), + .AXI_00_AWSIZE (AXI_00_AWSIZE_in), + .AXI_00_AWVALID (AXI_00_AWVALID_in), + .AXI_00_BREADY (AXI_00_BREADY_in), + .AXI_00_DFI_LP_PWR_X_REQ (AXI_00_DFI_LP_PWR_X_REQ_in), + .AXI_00_RREADY (AXI_00_RREADY_in), + .AXI_00_WDATA (AXI_00_WDATA_in), + .AXI_00_WDATA_PARITY (AXI_00_WDATA_PARITY_in), + .AXI_00_WLAST (AXI_00_WLAST_in), + .AXI_00_WSTRB (AXI_00_WSTRB_in), + .AXI_00_WVALID (AXI_00_WVALID_in), + .AXI_01_ACLK (AXI_01_ACLK_in), + .AXI_01_ARADDR (AXI_01_ARADDR_in), + .AXI_01_ARBURST (AXI_01_ARBURST_in), + .AXI_01_ARESET_N (AXI_01_ARESET_N_in), + .AXI_01_ARID (AXI_01_ARID_in), + .AXI_01_ARLEN (AXI_01_ARLEN_in), + .AXI_01_ARSIZE (AXI_01_ARSIZE_in), + .AXI_01_ARVALID (AXI_01_ARVALID_in), + .AXI_01_AWADDR (AXI_01_AWADDR_in), + .AXI_01_AWBURST (AXI_01_AWBURST_in), + .AXI_01_AWID (AXI_01_AWID_in), + .AXI_01_AWLEN (AXI_01_AWLEN_in), + .AXI_01_AWSIZE (AXI_01_AWSIZE_in), + .AXI_01_AWVALID (AXI_01_AWVALID_in), + .AXI_01_BREADY (AXI_01_BREADY_in), + .AXI_01_DFI_LP_PWR_X_REQ (AXI_01_DFI_LP_PWR_X_REQ_in), + .AXI_01_RREADY (AXI_01_RREADY_in), + .AXI_01_WDATA (AXI_01_WDATA_in), + .AXI_01_WDATA_PARITY (AXI_01_WDATA_PARITY_in), + .AXI_01_WLAST (AXI_01_WLAST_in), + .AXI_01_WSTRB (AXI_01_WSTRB_in), + .AXI_01_WVALID (AXI_01_WVALID_in), + .AXI_02_ACLK (AXI_02_ACLK_in), + .AXI_02_ARADDR (AXI_02_ARADDR_in), + .AXI_02_ARBURST (AXI_02_ARBURST_in), + .AXI_02_ARESET_N (AXI_02_ARESET_N_in), + .AXI_02_ARID (AXI_02_ARID_in), + .AXI_02_ARLEN (AXI_02_ARLEN_in), + .AXI_02_ARSIZE (AXI_02_ARSIZE_in), + .AXI_02_ARVALID (AXI_02_ARVALID_in), + .AXI_02_AWADDR (AXI_02_AWADDR_in), + .AXI_02_AWBURST (AXI_02_AWBURST_in), + .AXI_02_AWID (AXI_02_AWID_in), + .AXI_02_AWLEN (AXI_02_AWLEN_in), + .AXI_02_AWSIZE (AXI_02_AWSIZE_in), + .AXI_02_AWVALID (AXI_02_AWVALID_in), + .AXI_02_BREADY (AXI_02_BREADY_in), + .AXI_02_DFI_LP_PWR_X_REQ (AXI_02_DFI_LP_PWR_X_REQ_in), + .AXI_02_RREADY (AXI_02_RREADY_in), + .AXI_02_WDATA (AXI_02_WDATA_in), + .AXI_02_WDATA_PARITY (AXI_02_WDATA_PARITY_in), + .AXI_02_WLAST (AXI_02_WLAST_in), + .AXI_02_WSTRB (AXI_02_WSTRB_in), + .AXI_02_WVALID (AXI_02_WVALID_in), + .AXI_03_ACLK (AXI_03_ACLK_in), + .AXI_03_ARADDR (AXI_03_ARADDR_in), + .AXI_03_ARBURST (AXI_03_ARBURST_in), + .AXI_03_ARESET_N (AXI_03_ARESET_N_in), + .AXI_03_ARID (AXI_03_ARID_in), + .AXI_03_ARLEN (AXI_03_ARLEN_in), + .AXI_03_ARSIZE (AXI_03_ARSIZE_in), + .AXI_03_ARVALID (AXI_03_ARVALID_in), + .AXI_03_AWADDR (AXI_03_AWADDR_in), + .AXI_03_AWBURST (AXI_03_AWBURST_in), + .AXI_03_AWID (AXI_03_AWID_in), + .AXI_03_AWLEN (AXI_03_AWLEN_in), + .AXI_03_AWSIZE (AXI_03_AWSIZE_in), + .AXI_03_AWVALID (AXI_03_AWVALID_in), + .AXI_03_BREADY (AXI_03_BREADY_in), + .AXI_03_DFI_LP_PWR_X_REQ (AXI_03_DFI_LP_PWR_X_REQ_in), + .AXI_03_RREADY (AXI_03_RREADY_in), + .AXI_03_WDATA (AXI_03_WDATA_in), + .AXI_03_WDATA_PARITY (AXI_03_WDATA_PARITY_in), + .AXI_03_WLAST (AXI_03_WLAST_in), + .AXI_03_WSTRB (AXI_03_WSTRB_in), + .AXI_03_WVALID (AXI_03_WVALID_in), + .AXI_04_ACLK (AXI_04_ACLK_in), + .AXI_04_ARADDR (AXI_04_ARADDR_in), + .AXI_04_ARBURST (AXI_04_ARBURST_in), + .AXI_04_ARESET_N (AXI_04_ARESET_N_in), + .AXI_04_ARID (AXI_04_ARID_in), + .AXI_04_ARLEN (AXI_04_ARLEN_in), + .AXI_04_ARSIZE (AXI_04_ARSIZE_in), + .AXI_04_ARVALID (AXI_04_ARVALID_in), + .AXI_04_AWADDR (AXI_04_AWADDR_in), + .AXI_04_AWBURST (AXI_04_AWBURST_in), + .AXI_04_AWID (AXI_04_AWID_in), + .AXI_04_AWLEN (AXI_04_AWLEN_in), + .AXI_04_AWSIZE (AXI_04_AWSIZE_in), + .AXI_04_AWVALID (AXI_04_AWVALID_in), + .AXI_04_BREADY (AXI_04_BREADY_in), + .AXI_04_DFI_LP_PWR_X_REQ (AXI_04_DFI_LP_PWR_X_REQ_in), + .AXI_04_RREADY (AXI_04_RREADY_in), + .AXI_04_WDATA (AXI_04_WDATA_in), + .AXI_04_WDATA_PARITY (AXI_04_WDATA_PARITY_in), + .AXI_04_WLAST (AXI_04_WLAST_in), + .AXI_04_WSTRB (AXI_04_WSTRB_in), + .AXI_04_WVALID (AXI_04_WVALID_in), + .AXI_05_ACLK (AXI_05_ACLK_in), + .AXI_05_ARADDR (AXI_05_ARADDR_in), + .AXI_05_ARBURST (AXI_05_ARBURST_in), + .AXI_05_ARESET_N (AXI_05_ARESET_N_in), + .AXI_05_ARID (AXI_05_ARID_in), + .AXI_05_ARLEN (AXI_05_ARLEN_in), + .AXI_05_ARSIZE (AXI_05_ARSIZE_in), + .AXI_05_ARVALID (AXI_05_ARVALID_in), + .AXI_05_AWADDR (AXI_05_AWADDR_in), + .AXI_05_AWBURST (AXI_05_AWBURST_in), + .AXI_05_AWID (AXI_05_AWID_in), + .AXI_05_AWLEN (AXI_05_AWLEN_in), + .AXI_05_AWSIZE (AXI_05_AWSIZE_in), + .AXI_05_AWVALID (AXI_05_AWVALID_in), + .AXI_05_BREADY (AXI_05_BREADY_in), + .AXI_05_DFI_LP_PWR_X_REQ (AXI_05_DFI_LP_PWR_X_REQ_in), + .AXI_05_RREADY (AXI_05_RREADY_in), + .AXI_05_WDATA (AXI_05_WDATA_in), + .AXI_05_WDATA_PARITY (AXI_05_WDATA_PARITY_in), + .AXI_05_WLAST (AXI_05_WLAST_in), + .AXI_05_WSTRB (AXI_05_WSTRB_in), + .AXI_05_WVALID (AXI_05_WVALID_in), + .AXI_06_ACLK (AXI_06_ACLK_in), + .AXI_06_ARADDR (AXI_06_ARADDR_in), + .AXI_06_ARBURST (AXI_06_ARBURST_in), + .AXI_06_ARESET_N (AXI_06_ARESET_N_in), + .AXI_06_ARID (AXI_06_ARID_in), + .AXI_06_ARLEN (AXI_06_ARLEN_in), + .AXI_06_ARSIZE (AXI_06_ARSIZE_in), + .AXI_06_ARVALID (AXI_06_ARVALID_in), + .AXI_06_AWADDR (AXI_06_AWADDR_in), + .AXI_06_AWBURST (AXI_06_AWBURST_in), + .AXI_06_AWID (AXI_06_AWID_in), + .AXI_06_AWLEN (AXI_06_AWLEN_in), + .AXI_06_AWSIZE (AXI_06_AWSIZE_in), + .AXI_06_AWVALID (AXI_06_AWVALID_in), + .AXI_06_BREADY (AXI_06_BREADY_in), + .AXI_06_DFI_LP_PWR_X_REQ (AXI_06_DFI_LP_PWR_X_REQ_in), + .AXI_06_RREADY (AXI_06_RREADY_in), + .AXI_06_WDATA (AXI_06_WDATA_in), + .AXI_06_WDATA_PARITY (AXI_06_WDATA_PARITY_in), + .AXI_06_WLAST (AXI_06_WLAST_in), + .AXI_06_WSTRB (AXI_06_WSTRB_in), + .AXI_06_WVALID (AXI_06_WVALID_in), + .AXI_07_ACLK (AXI_07_ACLK_in), + .AXI_07_ARADDR (AXI_07_ARADDR_in), + .AXI_07_ARBURST (AXI_07_ARBURST_in), + .AXI_07_ARESET_N (AXI_07_ARESET_N_in), + .AXI_07_ARID (AXI_07_ARID_in), + .AXI_07_ARLEN (AXI_07_ARLEN_in), + .AXI_07_ARSIZE (AXI_07_ARSIZE_in), + .AXI_07_ARVALID (AXI_07_ARVALID_in), + .AXI_07_AWADDR (AXI_07_AWADDR_in), + .AXI_07_AWBURST (AXI_07_AWBURST_in), + .AXI_07_AWID (AXI_07_AWID_in), + .AXI_07_AWLEN (AXI_07_AWLEN_in), + .AXI_07_AWSIZE (AXI_07_AWSIZE_in), + .AXI_07_AWVALID (AXI_07_AWVALID_in), + .AXI_07_BREADY (AXI_07_BREADY_in), + .AXI_07_DFI_LP_PWR_X_REQ (AXI_07_DFI_LP_PWR_X_REQ_in), + .AXI_07_RREADY (AXI_07_RREADY_in), + .AXI_07_WDATA (AXI_07_WDATA_in), + .AXI_07_WDATA_PARITY (AXI_07_WDATA_PARITY_in), + .AXI_07_WLAST (AXI_07_WLAST_in), + .AXI_07_WSTRB (AXI_07_WSTRB_in), + .AXI_07_WVALID (AXI_07_WVALID_in), + .AXI_08_ACLK (AXI_08_ACLK_in), + .AXI_08_ARADDR (AXI_08_ARADDR_in), + .AXI_08_ARBURST (AXI_08_ARBURST_in), + .AXI_08_ARESET_N (AXI_08_ARESET_N_in), + .AXI_08_ARID (AXI_08_ARID_in), + .AXI_08_ARLEN (AXI_08_ARLEN_in), + .AXI_08_ARSIZE (AXI_08_ARSIZE_in), + .AXI_08_ARVALID (AXI_08_ARVALID_in), + .AXI_08_AWADDR (AXI_08_AWADDR_in), + .AXI_08_AWBURST (AXI_08_AWBURST_in), + .AXI_08_AWID (AXI_08_AWID_in), + .AXI_08_AWLEN (AXI_08_AWLEN_in), + .AXI_08_AWSIZE (AXI_08_AWSIZE_in), + .AXI_08_AWVALID (AXI_08_AWVALID_in), + .AXI_08_BREADY (AXI_08_BREADY_in), + .AXI_08_DFI_LP_PWR_X_REQ (AXI_08_DFI_LP_PWR_X_REQ_in), + .AXI_08_RREADY (AXI_08_RREADY_in), + .AXI_08_WDATA (AXI_08_WDATA_in), + .AXI_08_WDATA_PARITY (AXI_08_WDATA_PARITY_in), + .AXI_08_WLAST (AXI_08_WLAST_in), + .AXI_08_WSTRB (AXI_08_WSTRB_in), + .AXI_08_WVALID (AXI_08_WVALID_in), + .AXI_09_ACLK (AXI_09_ACLK_in), + .AXI_09_ARADDR (AXI_09_ARADDR_in), + .AXI_09_ARBURST (AXI_09_ARBURST_in), + .AXI_09_ARESET_N (AXI_09_ARESET_N_in), + .AXI_09_ARID (AXI_09_ARID_in), + .AXI_09_ARLEN (AXI_09_ARLEN_in), + .AXI_09_ARSIZE (AXI_09_ARSIZE_in), + .AXI_09_ARVALID (AXI_09_ARVALID_in), + .AXI_09_AWADDR (AXI_09_AWADDR_in), + .AXI_09_AWBURST (AXI_09_AWBURST_in), + .AXI_09_AWID (AXI_09_AWID_in), + .AXI_09_AWLEN (AXI_09_AWLEN_in), + .AXI_09_AWSIZE (AXI_09_AWSIZE_in), + .AXI_09_AWVALID (AXI_09_AWVALID_in), + .AXI_09_BREADY (AXI_09_BREADY_in), + .AXI_09_DFI_LP_PWR_X_REQ (AXI_09_DFI_LP_PWR_X_REQ_in), + .AXI_09_RREADY (AXI_09_RREADY_in), + .AXI_09_WDATA (AXI_09_WDATA_in), + .AXI_09_WDATA_PARITY (AXI_09_WDATA_PARITY_in), + .AXI_09_WLAST (AXI_09_WLAST_in), + .AXI_09_WSTRB (AXI_09_WSTRB_in), + .AXI_09_WVALID (AXI_09_WVALID_in), + .AXI_10_ACLK (AXI_10_ACLK_in), + .AXI_10_ARADDR (AXI_10_ARADDR_in), + .AXI_10_ARBURST (AXI_10_ARBURST_in), + .AXI_10_ARESET_N (AXI_10_ARESET_N_in), + .AXI_10_ARID (AXI_10_ARID_in), + .AXI_10_ARLEN (AXI_10_ARLEN_in), + .AXI_10_ARSIZE (AXI_10_ARSIZE_in), + .AXI_10_ARVALID (AXI_10_ARVALID_in), + .AXI_10_AWADDR (AXI_10_AWADDR_in), + .AXI_10_AWBURST (AXI_10_AWBURST_in), + .AXI_10_AWID (AXI_10_AWID_in), + .AXI_10_AWLEN (AXI_10_AWLEN_in), + .AXI_10_AWSIZE (AXI_10_AWSIZE_in), + .AXI_10_AWVALID (AXI_10_AWVALID_in), + .AXI_10_BREADY (AXI_10_BREADY_in), + .AXI_10_DFI_LP_PWR_X_REQ (AXI_10_DFI_LP_PWR_X_REQ_in), + .AXI_10_RREADY (AXI_10_RREADY_in), + .AXI_10_WDATA (AXI_10_WDATA_in), + .AXI_10_WDATA_PARITY (AXI_10_WDATA_PARITY_in), + .AXI_10_WLAST (AXI_10_WLAST_in), + .AXI_10_WSTRB (AXI_10_WSTRB_in), + .AXI_10_WVALID (AXI_10_WVALID_in), + .AXI_11_ACLK (AXI_11_ACLK_in), + .AXI_11_ARADDR (AXI_11_ARADDR_in), + .AXI_11_ARBURST (AXI_11_ARBURST_in), + .AXI_11_ARESET_N (AXI_11_ARESET_N_in), + .AXI_11_ARID (AXI_11_ARID_in), + .AXI_11_ARLEN (AXI_11_ARLEN_in), + .AXI_11_ARSIZE (AXI_11_ARSIZE_in), + .AXI_11_ARVALID (AXI_11_ARVALID_in), + .AXI_11_AWADDR (AXI_11_AWADDR_in), + .AXI_11_AWBURST (AXI_11_AWBURST_in), + .AXI_11_AWID (AXI_11_AWID_in), + .AXI_11_AWLEN (AXI_11_AWLEN_in), + .AXI_11_AWSIZE (AXI_11_AWSIZE_in), + .AXI_11_AWVALID (AXI_11_AWVALID_in), + .AXI_11_BREADY (AXI_11_BREADY_in), + .AXI_11_DFI_LP_PWR_X_REQ (AXI_11_DFI_LP_PWR_X_REQ_in), + .AXI_11_RREADY (AXI_11_RREADY_in), + .AXI_11_WDATA (AXI_11_WDATA_in), + .AXI_11_WDATA_PARITY (AXI_11_WDATA_PARITY_in), + .AXI_11_WLAST (AXI_11_WLAST_in), + .AXI_11_WSTRB (AXI_11_WSTRB_in), + .AXI_11_WVALID (AXI_11_WVALID_in), + .AXI_12_ACLK (AXI_12_ACLK_in), + .AXI_12_ARADDR (AXI_12_ARADDR_in), + .AXI_12_ARBURST (AXI_12_ARBURST_in), + .AXI_12_ARESET_N (AXI_12_ARESET_N_in), + .AXI_12_ARID (AXI_12_ARID_in), + .AXI_12_ARLEN (AXI_12_ARLEN_in), + .AXI_12_ARSIZE (AXI_12_ARSIZE_in), + .AXI_12_ARVALID (AXI_12_ARVALID_in), + .AXI_12_AWADDR (AXI_12_AWADDR_in), + .AXI_12_AWBURST (AXI_12_AWBURST_in), + .AXI_12_AWID (AXI_12_AWID_in), + .AXI_12_AWLEN (AXI_12_AWLEN_in), + .AXI_12_AWSIZE (AXI_12_AWSIZE_in), + .AXI_12_AWVALID (AXI_12_AWVALID_in), + .AXI_12_BREADY (AXI_12_BREADY_in), + .AXI_12_DFI_LP_PWR_X_REQ (AXI_12_DFI_LP_PWR_X_REQ_in), + .AXI_12_RREADY (AXI_12_RREADY_in), + .AXI_12_WDATA (AXI_12_WDATA_in), + .AXI_12_WDATA_PARITY (AXI_12_WDATA_PARITY_in), + .AXI_12_WLAST (AXI_12_WLAST_in), + .AXI_12_WSTRB (AXI_12_WSTRB_in), + .AXI_12_WVALID (AXI_12_WVALID_in), + .AXI_13_ACLK (AXI_13_ACLK_in), + .AXI_13_ARADDR (AXI_13_ARADDR_in), + .AXI_13_ARBURST (AXI_13_ARBURST_in), + .AXI_13_ARESET_N (AXI_13_ARESET_N_in), + .AXI_13_ARID (AXI_13_ARID_in), + .AXI_13_ARLEN (AXI_13_ARLEN_in), + .AXI_13_ARSIZE (AXI_13_ARSIZE_in), + .AXI_13_ARVALID (AXI_13_ARVALID_in), + .AXI_13_AWADDR (AXI_13_AWADDR_in), + .AXI_13_AWBURST (AXI_13_AWBURST_in), + .AXI_13_AWID (AXI_13_AWID_in), + .AXI_13_AWLEN (AXI_13_AWLEN_in), + .AXI_13_AWSIZE (AXI_13_AWSIZE_in), + .AXI_13_AWVALID (AXI_13_AWVALID_in), + .AXI_13_BREADY (AXI_13_BREADY_in), + .AXI_13_DFI_LP_PWR_X_REQ (AXI_13_DFI_LP_PWR_X_REQ_in), + .AXI_13_RREADY (AXI_13_RREADY_in), + .AXI_13_WDATA (AXI_13_WDATA_in), + .AXI_13_WDATA_PARITY (AXI_13_WDATA_PARITY_in), + .AXI_13_WLAST (AXI_13_WLAST_in), + .AXI_13_WSTRB (AXI_13_WSTRB_in), + .AXI_13_WVALID (AXI_13_WVALID_in), + .AXI_14_ACLK (AXI_14_ACLK_in), + .AXI_14_ARADDR (AXI_14_ARADDR_in), + .AXI_14_ARBURST (AXI_14_ARBURST_in), + .AXI_14_ARESET_N (AXI_14_ARESET_N_in), + .AXI_14_ARID (AXI_14_ARID_in), + .AXI_14_ARLEN (AXI_14_ARLEN_in), + .AXI_14_ARSIZE (AXI_14_ARSIZE_in), + .AXI_14_ARVALID (AXI_14_ARVALID_in), + .AXI_14_AWADDR (AXI_14_AWADDR_in), + .AXI_14_AWBURST (AXI_14_AWBURST_in), + .AXI_14_AWID (AXI_14_AWID_in), + .AXI_14_AWLEN (AXI_14_AWLEN_in), + .AXI_14_AWSIZE (AXI_14_AWSIZE_in), + .AXI_14_AWVALID (AXI_14_AWVALID_in), + .AXI_14_BREADY (AXI_14_BREADY_in), + .AXI_14_DFI_LP_PWR_X_REQ (AXI_14_DFI_LP_PWR_X_REQ_in), + .AXI_14_RREADY (AXI_14_RREADY_in), + .AXI_14_WDATA (AXI_14_WDATA_in), + .AXI_14_WDATA_PARITY (AXI_14_WDATA_PARITY_in), + .AXI_14_WLAST (AXI_14_WLAST_in), + .AXI_14_WSTRB (AXI_14_WSTRB_in), + .AXI_14_WVALID (AXI_14_WVALID_in), + .AXI_15_ACLK (AXI_15_ACLK_in), + .AXI_15_ARADDR (AXI_15_ARADDR_in), + .AXI_15_ARBURST (AXI_15_ARBURST_in), + .AXI_15_ARESET_N (AXI_15_ARESET_N_in), + .AXI_15_ARID (AXI_15_ARID_in), + .AXI_15_ARLEN (AXI_15_ARLEN_in), + .AXI_15_ARSIZE (AXI_15_ARSIZE_in), + .AXI_15_ARVALID (AXI_15_ARVALID_in), + .AXI_15_AWADDR (AXI_15_AWADDR_in), + .AXI_15_AWBURST (AXI_15_AWBURST_in), + .AXI_15_AWID (AXI_15_AWID_in), + .AXI_15_AWLEN (AXI_15_AWLEN_in), + .AXI_15_AWSIZE (AXI_15_AWSIZE_in), + .AXI_15_AWVALID (AXI_15_AWVALID_in), + .AXI_15_BREADY (AXI_15_BREADY_in), + .AXI_15_DFI_LP_PWR_X_REQ (AXI_15_DFI_LP_PWR_X_REQ_in), + .AXI_15_RREADY (AXI_15_RREADY_in), + .AXI_15_WDATA (AXI_15_WDATA_in), + .AXI_15_WDATA_PARITY (AXI_15_WDATA_PARITY_in), + .AXI_15_WLAST (AXI_15_WLAST_in), + .AXI_15_WSTRB (AXI_15_WSTRB_in), + .AXI_15_WVALID (AXI_15_WVALID_in), + .BLI_SCAN_ENABLE_00 (BLI_SCAN_ENABLE_00_in), + .BLI_SCAN_ENABLE_01 (BLI_SCAN_ENABLE_01_in), + .BLI_SCAN_ENABLE_02 (BLI_SCAN_ENABLE_02_in), + .BLI_SCAN_ENABLE_03 (BLI_SCAN_ENABLE_03_in), + .BLI_SCAN_ENABLE_04 (BLI_SCAN_ENABLE_04_in), + .BLI_SCAN_ENABLE_05 (BLI_SCAN_ENABLE_05_in), + .BLI_SCAN_ENABLE_06 (BLI_SCAN_ENABLE_06_in), + .BLI_SCAN_ENABLE_07 (BLI_SCAN_ENABLE_07_in), + .BLI_SCAN_ENABLE_08 (BLI_SCAN_ENABLE_08_in), + .BLI_SCAN_ENABLE_09 (BLI_SCAN_ENABLE_09_in), + .BLI_SCAN_ENABLE_10 (BLI_SCAN_ENABLE_10_in), + .BLI_SCAN_ENABLE_11 (BLI_SCAN_ENABLE_11_in), + .BLI_SCAN_ENABLE_12 (BLI_SCAN_ENABLE_12_in), + .BLI_SCAN_ENABLE_13 (BLI_SCAN_ENABLE_13_in), + .BLI_SCAN_ENABLE_14 (BLI_SCAN_ENABLE_14_in), + .BLI_SCAN_ENABLE_15 (BLI_SCAN_ENABLE_15_in), + .BLI_SCAN_IN_00 (BLI_SCAN_IN_00_in), + .BLI_SCAN_IN_01 (BLI_SCAN_IN_01_in), + .BLI_SCAN_IN_02 (BLI_SCAN_IN_02_in), + .BLI_SCAN_IN_03 (BLI_SCAN_IN_03_in), + .BLI_SCAN_IN_04 (BLI_SCAN_IN_04_in), + .BLI_SCAN_IN_05 (BLI_SCAN_IN_05_in), + .BLI_SCAN_IN_06 (BLI_SCAN_IN_06_in), + .BLI_SCAN_IN_07 (BLI_SCAN_IN_07_in), + .BLI_SCAN_IN_08 (BLI_SCAN_IN_08_in), + .BLI_SCAN_IN_09 (BLI_SCAN_IN_09_in), + .BLI_SCAN_IN_10 (BLI_SCAN_IN_10_in), + .BLI_SCAN_IN_11 (BLI_SCAN_IN_11_in), + .BLI_SCAN_IN_12 (BLI_SCAN_IN_12_in), + .BLI_SCAN_IN_13 (BLI_SCAN_IN_13_in), + .BLI_SCAN_IN_14 (BLI_SCAN_IN_14_in), + .BLI_SCAN_IN_15 (BLI_SCAN_IN_15_in), + .BSCAN_DRCK (BSCAN_DRCK_in), + .BSCAN_TCK (BSCAN_TCK_in), + .DBG_IN_00 (DBG_IN_00_in), + .DBG_IN_01 (DBG_IN_01_in), + .DBG_IN_02 (DBG_IN_02_in), + .DBG_IN_03 (DBG_IN_03_in), + .DBG_IN_04 (DBG_IN_04_in), + .DBG_IN_05 (DBG_IN_05_in), + .DBG_IN_06 (DBG_IN_06_in), + .DBG_IN_07 (DBG_IN_07_in), + .DBG_IN_08 (DBG_IN_08_in), + .DBG_IN_09 (DBG_IN_09_in), + .DBG_IN_10 (DBG_IN_10_in), + .DBG_IN_11 (DBG_IN_11_in), + .DBG_IN_12 (DBG_IN_12_in), + .DBG_IN_13 (DBG_IN_13_in), + .DBG_IN_14 (DBG_IN_14_in), + .DBG_IN_15 (DBG_IN_15_in), + .DLL_SCAN_CK_00 (DLL_SCAN_CK_00_in), + .DLL_SCAN_ENABLE_00 (DLL_SCAN_ENABLE_00_in), + .DLL_SCAN_IN_00 (DLL_SCAN_IN_00_in), + .DLL_SCAN_MODE_00 (DLL_SCAN_MODE_00_in), + .DLL_SCAN_RST_N_00 (DLL_SCAN_RST_N_00_in), + .HBM_REF_CLK (HBM_REF_CLK_in), + .IO_SCAN_CK_00 (IO_SCAN_CK_00_in), + .IO_SCAN_ENABLE_00 (IO_SCAN_ENABLE_00_in), + .IO_SCAN_IN_00 (IO_SCAN_IN_00_in), + .IO_SCAN_MODE_00 (IO_SCAN_MODE_00_in), + .IO_SCAN_RST_N_00 (IO_SCAN_RST_N_00_in), + .MBIST_EN_00 (MBIST_EN_00_in), + .MBIST_EN_01 (MBIST_EN_01_in), + .MBIST_EN_02 (MBIST_EN_02_in), + .MBIST_EN_03 (MBIST_EN_03_in), + .MBIST_EN_04 (MBIST_EN_04_in), + .MBIST_EN_05 (MBIST_EN_05_in), + .MBIST_EN_06 (MBIST_EN_06_in), + .MBIST_EN_07 (MBIST_EN_07_in), + .MC_SCAN_CK_00 (MC_SCAN_CK_00_in), + .MC_SCAN_CK_01 (MC_SCAN_CK_01_in), + .MC_SCAN_CK_02 (MC_SCAN_CK_02_in), + .MC_SCAN_CK_03 (MC_SCAN_CK_03_in), + .MC_SCAN_CK_04 (MC_SCAN_CK_04_in), + .MC_SCAN_CK_05 (MC_SCAN_CK_05_in), + .MC_SCAN_CK_06 (MC_SCAN_CK_06_in), + .MC_SCAN_CK_07 (MC_SCAN_CK_07_in), + .MC_SCAN_ENABLE_00 (MC_SCAN_ENABLE_00_in), + .MC_SCAN_ENABLE_01 (MC_SCAN_ENABLE_01_in), + .MC_SCAN_ENABLE_02 (MC_SCAN_ENABLE_02_in), + .MC_SCAN_ENABLE_03 (MC_SCAN_ENABLE_03_in), + .MC_SCAN_ENABLE_04 (MC_SCAN_ENABLE_04_in), + .MC_SCAN_ENABLE_05 (MC_SCAN_ENABLE_05_in), + .MC_SCAN_ENABLE_06 (MC_SCAN_ENABLE_06_in), + .MC_SCAN_ENABLE_07 (MC_SCAN_ENABLE_07_in), + .MC_SCAN_IN_00 (MC_SCAN_IN_00_in), + .MC_SCAN_IN_01 (MC_SCAN_IN_01_in), + .MC_SCAN_IN_02 (MC_SCAN_IN_02_in), + .MC_SCAN_IN_03 (MC_SCAN_IN_03_in), + .MC_SCAN_IN_04 (MC_SCAN_IN_04_in), + .MC_SCAN_IN_05 (MC_SCAN_IN_05_in), + .MC_SCAN_IN_06 (MC_SCAN_IN_06_in), + .MC_SCAN_IN_07 (MC_SCAN_IN_07_in), + .MC_SCAN_MODE_00 (MC_SCAN_MODE_00_in), + .MC_SCAN_MODE_01 (MC_SCAN_MODE_01_in), + .MC_SCAN_MODE_02 (MC_SCAN_MODE_02_in), + .MC_SCAN_MODE_03 (MC_SCAN_MODE_03_in), + .MC_SCAN_MODE_04 (MC_SCAN_MODE_04_in), + .MC_SCAN_MODE_05 (MC_SCAN_MODE_05_in), + .MC_SCAN_MODE_06 (MC_SCAN_MODE_06_in), + .MC_SCAN_MODE_07 (MC_SCAN_MODE_07_in), + .MC_SCAN_RST_N_00 (MC_SCAN_RST_N_00_in), + .MC_SCAN_RST_N_01 (MC_SCAN_RST_N_01_in), + .MC_SCAN_RST_N_02 (MC_SCAN_RST_N_02_in), + .MC_SCAN_RST_N_03 (MC_SCAN_RST_N_03_in), + .MC_SCAN_RST_N_04 (MC_SCAN_RST_N_04_in), + .MC_SCAN_RST_N_05 (MC_SCAN_RST_N_05_in), + .MC_SCAN_RST_N_06 (MC_SCAN_RST_N_06_in), + .MC_SCAN_RST_N_07 (MC_SCAN_RST_N_07_in), + .PHY_SCAN_CK_00 (PHY_SCAN_CK_00_in), + .PHY_SCAN_ENABLE_00 (PHY_SCAN_ENABLE_00_in), + .PHY_SCAN_IN_00 (PHY_SCAN_IN_00_in), + .PHY_SCAN_MODE_00 (PHY_SCAN_MODE_00_in), + .PHY_SCAN_RST_N_00 (PHY_SCAN_RST_N_00_in), + .SW_SCAN_CK_00 (SW_SCAN_CK_00_in), + .SW_SCAN_ENABLE_00 (SW_SCAN_ENABLE_00_in), + .SW_SCAN_IN_00 (SW_SCAN_IN_00_in), + .SW_SCAN_IN_01 (SW_SCAN_IN_01_in), + .SW_SCAN_IN_02 (SW_SCAN_IN_02_in), + .SW_SCAN_IN_03 (SW_SCAN_IN_03_in), + .SW_SCAN_MODE_00 (SW_SCAN_MODE_00_in), + .SW_SCAN_RST_N_00 (SW_SCAN_RST_N_00_in), + .GSR (glblGSR) +); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HBM_REF_CLK.v b/verilog/src/unisims/HBM_REF_CLK.v new file mode 100644 index 0000000..6a79bb3 --- /dev/null +++ b/verilog/src/unisims/HBM_REF_CLK.v @@ -0,0 +1,64 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HBM_REF_CLK +// /___/ /\ Filename : HBM_REF_CLK.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HBM_REF_CLK +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + input REF_CLK +); + +// define constants + localparam MODULE_NAME = "HBM_REF_CLK"; + + tri0 glblGSR = glbl.GSR; + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +// begin behavioral model + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HBM_SNGLBLI_INTF_APB.v b/verilog/src/unisims/HBM_SNGLBLI_INTF_APB.v new file mode 100644 index 0000000..d7b3857 --- /dev/null +++ b/verilog/src/unisims/HBM_SNGLBLI_INTF_APB.v @@ -0,0 +1,615 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HBM_SNGLBLI_INTF_APB +// /___/ /\ Filename : HBM_SNGLBLI_INTF_APB.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HBM_SNGLBLI_INTF_APB #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CLK_SEL = "FALSE", + parameter [0:0] IS_PCLK_INVERTED = 1'b0, + parameter [0:0] IS_PRESET_N_INVERTED = 1'b0, + parameter MC_ENABLE = "FALSE", + parameter PHY_ENABLE = "FALSE", + parameter PHY_PCLK_INVERT = "FALSE", + parameter SWITCH_ENABLE = "FALSE" +)( + output CATTRIP_PIPE, + output [31:0] PRDATA_PIPE, + output PREADY_PIPE, + output PSLVERR_PIPE, + output [2:0] TEMP_PIPE, + + input [21:0] PADDR, + input PCLK, + input PENABLE, + input PRESET_N, + input PSEL, + input [31:0] PWDATA, + input PWRITE +); + +// define constants + localparam MODULE_NAME = "HBM_SNGLBLI_INTF_APB"; + +// Parameter encodings and registers + localparam CLK_SEL_FALSE = 0; + localparam CLK_SEL_TRUE = 1; + localparam MC_ENABLE_FALSE = 0; + localparam MC_ENABLE_TRUE = 1; + localparam PHY_ENABLE_FALSE = 0; + localparam PHY_ENABLE_TRUE = 1; + localparam SWITCH_ENABLE_FALSE = 0; + localparam SWITCH_ENABLE_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HBM_SNGLBLI_INTF_APB_dr.v" +`else + localparam [40:1] CLK_SEL_REG = CLK_SEL; + localparam [0:0] IS_PCLK_INVERTED_REG = IS_PCLK_INVERTED; + localparam [0:0] IS_PRESET_N_INVERTED_REG = IS_PRESET_N_INVERTED; + localparam [40:1] MC_ENABLE_REG = MC_ENABLE; + localparam [40:1] PHY_ENABLE_REG = PHY_ENABLE; + localparam [40:1] PHY_PCLK_INVERT_REG = PHY_PCLK_INVERT; + localparam [40:1] SWITCH_ENABLE_REG = SWITCH_ENABLE; +`endif + +`ifdef XIL_XECLIB + wire CLK_SEL_BIN; + wire MC_ENABLE_BIN; + wire PHY_ENABLE_BIN; + wire SWITCH_ENABLE_BIN; +`else + reg CLK_SEL_BIN; + reg MC_ENABLE_BIN; + reg PHY_ENABLE_BIN; + reg SWITCH_ENABLE_BIN; +`endif + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire PCLK_in; + wire PENABLE_in; + wire PRESET_N_in; + wire PSEL_in; + wire PWRITE_in; + wire [21:0] PADDR_in; + wire [31:0] PWDATA_in; + +`ifdef XIL_TIMING + wire PCLK_delay; + wire PENABLE_delay; + wire PRESET_N_delay; + wire PSEL_delay; + wire PWRITE_delay; + wire [21:0] PADDR_delay; + wire [31:0] PWDATA_delay; +`endif + +`ifdef XIL_TIMING + assign PADDR_in = PADDR_delay; + assign PCLK_in = PCLK_delay; + assign PENABLE_in = PENABLE_delay; + assign PRESET_N_in = PRESET_N_delay; + assign PSEL_in = PSEL_delay; + assign PWDATA_in = PWDATA_delay; + assign PWRITE_in = PWRITE_delay; +`else + assign PADDR_in = PADDR; + assign PCLK_in = PCLK; + assign PENABLE_in = PENABLE; + assign PRESET_N_in = PRESET_N; + assign PSEL_in = PSEL; + assign PWDATA_in = PWDATA; + assign PWRITE_in = PWRITE; +`endif + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CLK_SEL_BIN = + (CLK_SEL_REG == "FALSE") ? CLK_SEL_FALSE : + (CLK_SEL_REG == "TRUE") ? CLK_SEL_TRUE : + CLK_SEL_FALSE; + + assign MC_ENABLE_BIN = + (MC_ENABLE_REG == "FALSE") ? MC_ENABLE_FALSE : + (MC_ENABLE_REG == "TRUE") ? MC_ENABLE_TRUE : + MC_ENABLE_FALSE; + + assign PHY_ENABLE_BIN = + (PHY_ENABLE_REG == "FALSE") ? PHY_ENABLE_FALSE : + (PHY_ENABLE_REG == "TRUE") ? PHY_ENABLE_TRUE : + PHY_ENABLE_FALSE; + + assign SWITCH_ENABLE_BIN = + (SWITCH_ENABLE_REG == "FALSE") ? SWITCH_ENABLE_FALSE : + (SWITCH_ENABLE_REG == "TRUE") ? SWITCH_ENABLE_TRUE : + SWITCH_ENABLE_FALSE; + +`else + always @ (trig_attr) begin + #1; + CLK_SEL_BIN = + (CLK_SEL_REG == "FALSE") ? CLK_SEL_FALSE : + (CLK_SEL_REG == "TRUE") ? CLK_SEL_TRUE : + CLK_SEL_FALSE; + + MC_ENABLE_BIN = + (MC_ENABLE_REG == "FALSE") ? MC_ENABLE_FALSE : + (MC_ENABLE_REG == "TRUE") ? MC_ENABLE_TRUE : + MC_ENABLE_FALSE; + + PHY_ENABLE_BIN = + (PHY_ENABLE_REG == "FALSE") ? PHY_ENABLE_FALSE : + (PHY_ENABLE_REG == "TRUE") ? PHY_ENABLE_TRUE : + PHY_ENABLE_FALSE; + + SWITCH_ENABLE_BIN = + (SWITCH_ENABLE_REG == "FALSE") ? SWITCH_ENABLE_FALSE : + (SWITCH_ENABLE_REG == "TRUE") ? SWITCH_ENABLE_TRUE : + SWITCH_ENABLE_FALSE; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLK_SEL_REG != "FALSE") && + (CLK_SEL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] CLK_SEL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_REG != "FALSE") && + (MC_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] MC_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_REG != "FALSE") && + (PHY_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] PHY_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_PCLK_INVERT_REG != "FALSE") && + (PHY_PCLK_INVERT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] PHY_PCLK_INVERT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SWITCH_ENABLE_REG != "FALSE") && + (SWITCH_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] SWITCH_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + +// end behavioral model + +`ifndef XIL_XECLIB + specify + (PCLK => CATTRIP_PIPE) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[0]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[10]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[11]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[12]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[13]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[14]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[15]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[16]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[17]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[18]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[19]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[1]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[20]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[21]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[22]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[23]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[24]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[25]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[26]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[27]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[28]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[29]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[2]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[30]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[31]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[3]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[4]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[5]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[6]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[7]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[8]) = (100:100:100, 100:100:100); + (PCLK => PRDATA_PIPE[9]) = (100:100:100, 100:100:100); + (PCLK => PREADY_PIPE) = (100:100:100, 100:100:100); + (PCLK => PSLVERR_PIPE) = (100:100:100, 100:100:100); + (PCLK => TEMP_PIPE[0]) = (100:100:100, 100:100:100); + (PCLK => TEMP_PIPE[1]) = (100:100:100, 100:100:100); + (PCLK => TEMP_PIPE[2]) = (100:100:100, 100:100:100); + (negedge PRESET_N => (CATTRIP_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PRDATA_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (PSLVERR_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (TEMP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (TEMP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge PRESET_N => (TEMP_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (CATTRIP_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PRDATA_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (PSLVERR_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (TEMP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (TEMP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge PRESET_N => (TEMP_PIPE[2] +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $recrem (negedge PRESET_N, negedge PCLK, 0:0:0, 0:0:0, notifier, , , PRESET_N_delay, PCLK_delay); + $recrem (negedge PRESET_N, posedge PCLK, 0:0:0, 0:0:0, notifier, , , PRESET_N_delay, PCLK_delay); + $recrem (posedge PRESET_N, negedge PCLK, 0:0:0, 0:0:0, notifier, , , PRESET_N_delay, PCLK_delay); + $recrem (posedge PRESET_N, posedge PCLK, 0:0:0, 0:0:0, notifier, , , PRESET_N_delay, PCLK_delay); + $setuphold (negedge PCLK, negedge PADDR[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[0]); + $setuphold (negedge PCLK, negedge PADDR[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[10]); + $setuphold (negedge PCLK, negedge PADDR[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[11]); + $setuphold (negedge PCLK, negedge PADDR[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[12]); + $setuphold (negedge PCLK, negedge PADDR[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[13]); + $setuphold (negedge PCLK, negedge PADDR[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[14]); + $setuphold (negedge PCLK, negedge PADDR[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[15]); + $setuphold (negedge PCLK, negedge PADDR[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[16]); + $setuphold (negedge PCLK, negedge PADDR[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[17]); + $setuphold (negedge PCLK, negedge PADDR[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[18]); + $setuphold (negedge PCLK, negedge PADDR[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[19]); + $setuphold (negedge PCLK, negedge PADDR[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[1]); + $setuphold (negedge PCLK, negedge PADDR[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[20]); + $setuphold (negedge PCLK, negedge PADDR[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[21]); + $setuphold (negedge PCLK, negedge PADDR[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[2]); + $setuphold (negedge PCLK, negedge PADDR[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[3]); + $setuphold (negedge PCLK, negedge PADDR[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[4]); + $setuphold (negedge PCLK, negedge PADDR[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[5]); + $setuphold (negedge PCLK, negedge PADDR[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[6]); + $setuphold (negedge PCLK, negedge PADDR[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[7]); + $setuphold (negedge PCLK, negedge PADDR[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[8]); + $setuphold (negedge PCLK, negedge PADDR[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[9]); + $setuphold (negedge PCLK, negedge PENABLE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PENABLE_delay); + $setuphold (negedge PCLK, negedge PSEL, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PSEL_delay); + $setuphold (negedge PCLK, negedge PWDATA[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[0]); + $setuphold (negedge PCLK, negedge PWDATA[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[10]); + $setuphold (negedge PCLK, negedge PWDATA[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[11]); + $setuphold (negedge PCLK, negedge PWDATA[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[12]); + $setuphold (negedge PCLK, negedge PWDATA[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[13]); + $setuphold (negedge PCLK, negedge PWDATA[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[14]); + $setuphold (negedge PCLK, negedge PWDATA[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[15]); + $setuphold (negedge PCLK, negedge PWDATA[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[16]); + $setuphold (negedge PCLK, negedge PWDATA[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[17]); + $setuphold (negedge PCLK, negedge PWDATA[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[18]); + $setuphold (negedge PCLK, negedge PWDATA[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[19]); + $setuphold (negedge PCLK, negedge PWDATA[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[1]); + $setuphold (negedge PCLK, negedge PWDATA[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[20]); + $setuphold (negedge PCLK, negedge PWDATA[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[21]); + $setuphold (negedge PCLK, negedge PWDATA[22], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[22]); + $setuphold (negedge PCLK, negedge PWDATA[23], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[23]); + $setuphold (negedge PCLK, negedge PWDATA[24], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[24]); + $setuphold (negedge PCLK, negedge PWDATA[25], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[25]); + $setuphold (negedge PCLK, negedge PWDATA[26], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[26]); + $setuphold (negedge PCLK, negedge PWDATA[27], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[27]); + $setuphold (negedge PCLK, negedge PWDATA[28], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[28]); + $setuphold (negedge PCLK, negedge PWDATA[29], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[29]); + $setuphold (negedge PCLK, negedge PWDATA[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[2]); + $setuphold (negedge PCLK, negedge PWDATA[30], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[30]); + $setuphold (negedge PCLK, negedge PWDATA[31], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[31]); + $setuphold (negedge PCLK, negedge PWDATA[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[3]); + $setuphold (negedge PCLK, negedge PWDATA[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[4]); + $setuphold (negedge PCLK, negedge PWDATA[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[5]); + $setuphold (negedge PCLK, negedge PWDATA[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[6]); + $setuphold (negedge PCLK, negedge PWDATA[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[7]); + $setuphold (negedge PCLK, negedge PWDATA[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[8]); + $setuphold (negedge PCLK, negedge PWDATA[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[9]); + $setuphold (negedge PCLK, negedge PWRITE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWRITE_delay); + $setuphold (negedge PCLK, posedge PADDR[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[0]); + $setuphold (negedge PCLK, posedge PADDR[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[10]); + $setuphold (negedge PCLK, posedge PADDR[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[11]); + $setuphold (negedge PCLK, posedge PADDR[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[12]); + $setuphold (negedge PCLK, posedge PADDR[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[13]); + $setuphold (negedge PCLK, posedge PADDR[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[14]); + $setuphold (negedge PCLK, posedge PADDR[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[15]); + $setuphold (negedge PCLK, posedge PADDR[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[16]); + $setuphold (negedge PCLK, posedge PADDR[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[17]); + $setuphold (negedge PCLK, posedge PADDR[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[18]); + $setuphold (negedge PCLK, posedge PADDR[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[19]); + $setuphold (negedge PCLK, posedge PADDR[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[1]); + $setuphold (negedge PCLK, posedge PADDR[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[20]); + $setuphold (negedge PCLK, posedge PADDR[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[21]); + $setuphold (negedge PCLK, posedge PADDR[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[2]); + $setuphold (negedge PCLK, posedge PADDR[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[3]); + $setuphold (negedge PCLK, posedge PADDR[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[4]); + $setuphold (negedge PCLK, posedge PADDR[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[5]); + $setuphold (negedge PCLK, posedge PADDR[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[6]); + $setuphold (negedge PCLK, posedge PADDR[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[7]); + $setuphold (negedge PCLK, posedge PADDR[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[8]); + $setuphold (negedge PCLK, posedge PADDR[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[9]); + $setuphold (negedge PCLK, posedge PENABLE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PENABLE_delay); + $setuphold (negedge PCLK, posedge PSEL, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PSEL_delay); + $setuphold (negedge PCLK, posedge PWDATA[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[0]); + $setuphold (negedge PCLK, posedge PWDATA[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[10]); + $setuphold (negedge PCLK, posedge PWDATA[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[11]); + $setuphold (negedge PCLK, posedge PWDATA[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[12]); + $setuphold (negedge PCLK, posedge PWDATA[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[13]); + $setuphold (negedge PCLK, posedge PWDATA[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[14]); + $setuphold (negedge PCLK, posedge PWDATA[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[15]); + $setuphold (negedge PCLK, posedge PWDATA[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[16]); + $setuphold (negedge PCLK, posedge PWDATA[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[17]); + $setuphold (negedge PCLK, posedge PWDATA[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[18]); + $setuphold (negedge PCLK, posedge PWDATA[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[19]); + $setuphold (negedge PCLK, posedge PWDATA[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[1]); + $setuphold (negedge PCLK, posedge PWDATA[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[20]); + $setuphold (negedge PCLK, posedge PWDATA[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[21]); + $setuphold (negedge PCLK, posedge PWDATA[22], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[22]); + $setuphold (negedge PCLK, posedge PWDATA[23], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[23]); + $setuphold (negedge PCLK, posedge PWDATA[24], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[24]); + $setuphold (negedge PCLK, posedge PWDATA[25], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[25]); + $setuphold (negedge PCLK, posedge PWDATA[26], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[26]); + $setuphold (negedge PCLK, posedge PWDATA[27], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[27]); + $setuphold (negedge PCLK, posedge PWDATA[28], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[28]); + $setuphold (negedge PCLK, posedge PWDATA[29], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[29]); + $setuphold (negedge PCLK, posedge PWDATA[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[2]); + $setuphold (negedge PCLK, posedge PWDATA[30], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[30]); + $setuphold (negedge PCLK, posedge PWDATA[31], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[31]); + $setuphold (negedge PCLK, posedge PWDATA[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[3]); + $setuphold (negedge PCLK, posedge PWDATA[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[4]); + $setuphold (negedge PCLK, posedge PWDATA[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[5]); + $setuphold (negedge PCLK, posedge PWDATA[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[6]); + $setuphold (negedge PCLK, posedge PWDATA[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[7]); + $setuphold (negedge PCLK, posedge PWDATA[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[8]); + $setuphold (negedge PCLK, posedge PWDATA[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[9]); + $setuphold (negedge PCLK, posedge PWRITE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWRITE_delay); + $setuphold (posedge PCLK, negedge PADDR[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[0]); + $setuphold (posedge PCLK, negedge PADDR[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[10]); + $setuphold (posedge PCLK, negedge PADDR[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[11]); + $setuphold (posedge PCLK, negedge PADDR[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[12]); + $setuphold (posedge PCLK, negedge PADDR[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[13]); + $setuphold (posedge PCLK, negedge PADDR[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[14]); + $setuphold (posedge PCLK, negedge PADDR[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[15]); + $setuphold (posedge PCLK, negedge PADDR[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[16]); + $setuphold (posedge PCLK, negedge PADDR[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[17]); + $setuphold (posedge PCLK, negedge PADDR[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[18]); + $setuphold (posedge PCLK, negedge PADDR[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[19]); + $setuphold (posedge PCLK, negedge PADDR[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[1]); + $setuphold (posedge PCLK, negedge PADDR[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[20]); + $setuphold (posedge PCLK, negedge PADDR[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[21]); + $setuphold (posedge PCLK, negedge PADDR[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[2]); + $setuphold (posedge PCLK, negedge PADDR[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[3]); + $setuphold (posedge PCLK, negedge PADDR[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[4]); + $setuphold (posedge PCLK, negedge PADDR[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[5]); + $setuphold (posedge PCLK, negedge PADDR[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[6]); + $setuphold (posedge PCLK, negedge PADDR[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[7]); + $setuphold (posedge PCLK, negedge PADDR[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[8]); + $setuphold (posedge PCLK, negedge PADDR[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[9]); + $setuphold (posedge PCLK, negedge PENABLE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PENABLE_delay); + $setuphold (posedge PCLK, negedge PSEL, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PSEL_delay); + $setuphold (posedge PCLK, negedge PWDATA[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[0]); + $setuphold (posedge PCLK, negedge PWDATA[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[10]); + $setuphold (posedge PCLK, negedge PWDATA[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[11]); + $setuphold (posedge PCLK, negedge PWDATA[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[12]); + $setuphold (posedge PCLK, negedge PWDATA[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[13]); + $setuphold (posedge PCLK, negedge PWDATA[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[14]); + $setuphold (posedge PCLK, negedge PWDATA[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[15]); + $setuphold (posedge PCLK, negedge PWDATA[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[16]); + $setuphold (posedge PCLK, negedge PWDATA[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[17]); + $setuphold (posedge PCLK, negedge PWDATA[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[18]); + $setuphold (posedge PCLK, negedge PWDATA[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[19]); + $setuphold (posedge PCLK, negedge PWDATA[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[1]); + $setuphold (posedge PCLK, negedge PWDATA[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[20]); + $setuphold (posedge PCLK, negedge PWDATA[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[21]); + $setuphold (posedge PCLK, negedge PWDATA[22], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[22]); + $setuphold (posedge PCLK, negedge PWDATA[23], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[23]); + $setuphold (posedge PCLK, negedge PWDATA[24], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[24]); + $setuphold (posedge PCLK, negedge PWDATA[25], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[25]); + $setuphold (posedge PCLK, negedge PWDATA[26], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[26]); + $setuphold (posedge PCLK, negedge PWDATA[27], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[27]); + $setuphold (posedge PCLK, negedge PWDATA[28], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[28]); + $setuphold (posedge PCLK, negedge PWDATA[29], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[29]); + $setuphold (posedge PCLK, negedge PWDATA[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[2]); + $setuphold (posedge PCLK, negedge PWDATA[30], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[30]); + $setuphold (posedge PCLK, negedge PWDATA[31], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[31]); + $setuphold (posedge PCLK, negedge PWDATA[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[3]); + $setuphold (posedge PCLK, negedge PWDATA[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[4]); + $setuphold (posedge PCLK, negedge PWDATA[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[5]); + $setuphold (posedge PCLK, negedge PWDATA[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[6]); + $setuphold (posedge PCLK, negedge PWDATA[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[7]); + $setuphold (posedge PCLK, negedge PWDATA[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[8]); + $setuphold (posedge PCLK, negedge PWDATA[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[9]); + $setuphold (posedge PCLK, negedge PWRITE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWRITE_delay); + $setuphold (posedge PCLK, posedge PADDR[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[0]); + $setuphold (posedge PCLK, posedge PADDR[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[10]); + $setuphold (posedge PCLK, posedge PADDR[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[11]); + $setuphold (posedge PCLK, posedge PADDR[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[12]); + $setuphold (posedge PCLK, posedge PADDR[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[13]); + $setuphold (posedge PCLK, posedge PADDR[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[14]); + $setuphold (posedge PCLK, posedge PADDR[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[15]); + $setuphold (posedge PCLK, posedge PADDR[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[16]); + $setuphold (posedge PCLK, posedge PADDR[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[17]); + $setuphold (posedge PCLK, posedge PADDR[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[18]); + $setuphold (posedge PCLK, posedge PADDR[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[19]); + $setuphold (posedge PCLK, posedge PADDR[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[1]); + $setuphold (posedge PCLK, posedge PADDR[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[20]); + $setuphold (posedge PCLK, posedge PADDR[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[21]); + $setuphold (posedge PCLK, posedge PADDR[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[2]); + $setuphold (posedge PCLK, posedge PADDR[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[3]); + $setuphold (posedge PCLK, posedge PADDR[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[4]); + $setuphold (posedge PCLK, posedge PADDR[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[5]); + $setuphold (posedge PCLK, posedge PADDR[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[6]); + $setuphold (posedge PCLK, posedge PADDR[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[7]); + $setuphold (posedge PCLK, posedge PADDR[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[8]); + $setuphold (posedge PCLK, posedge PADDR[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PADDR_delay[9]); + $setuphold (posedge PCLK, posedge PENABLE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PENABLE_delay); + $setuphold (posedge PCLK, posedge PSEL, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PSEL_delay); + $setuphold (posedge PCLK, posedge PWDATA[0], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[0]); + $setuphold (posedge PCLK, posedge PWDATA[10], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[10]); + $setuphold (posedge PCLK, posedge PWDATA[11], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[11]); + $setuphold (posedge PCLK, posedge PWDATA[12], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[12]); + $setuphold (posedge PCLK, posedge PWDATA[13], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[13]); + $setuphold (posedge PCLK, posedge PWDATA[14], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[14]); + $setuphold (posedge PCLK, posedge PWDATA[15], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[15]); + $setuphold (posedge PCLK, posedge PWDATA[16], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[16]); + $setuphold (posedge PCLK, posedge PWDATA[17], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[17]); + $setuphold (posedge PCLK, posedge PWDATA[18], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[18]); + $setuphold (posedge PCLK, posedge PWDATA[19], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[19]); + $setuphold (posedge PCLK, posedge PWDATA[1], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[1]); + $setuphold (posedge PCLK, posedge PWDATA[20], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[20]); + $setuphold (posedge PCLK, posedge PWDATA[21], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[21]); + $setuphold (posedge PCLK, posedge PWDATA[22], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[22]); + $setuphold (posedge PCLK, posedge PWDATA[23], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[23]); + $setuphold (posedge PCLK, posedge PWDATA[24], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[24]); + $setuphold (posedge PCLK, posedge PWDATA[25], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[25]); + $setuphold (posedge PCLK, posedge PWDATA[26], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[26]); + $setuphold (posedge PCLK, posedge PWDATA[27], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[27]); + $setuphold (posedge PCLK, posedge PWDATA[28], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[28]); + $setuphold (posedge PCLK, posedge PWDATA[29], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[29]); + $setuphold (posedge PCLK, posedge PWDATA[2], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[2]); + $setuphold (posedge PCLK, posedge PWDATA[30], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[30]); + $setuphold (posedge PCLK, posedge PWDATA[31], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[31]); + $setuphold (posedge PCLK, posedge PWDATA[3], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[3]); + $setuphold (posedge PCLK, posedge PWDATA[4], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[4]); + $setuphold (posedge PCLK, posedge PWDATA[5], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[5]); + $setuphold (posedge PCLK, posedge PWDATA[6], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[6]); + $setuphold (posedge PCLK, posedge PWDATA[7], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[7]); + $setuphold (posedge PCLK, posedge PWDATA[8], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[8]); + $setuphold (posedge PCLK, posedge PWDATA[9], 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWDATA_delay[9]); + $setuphold (posedge PCLK, posedge PWRITE, 0:0:0, 0:0:0, notifier, , , PCLK_delay, PWRITE_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HBM_SNGLBLI_INTF_AXI.v b/verilog/src/unisims/HBM_SNGLBLI_INTF_AXI.v new file mode 100644 index 0000000..e2f51c5 --- /dev/null +++ b/verilog/src/unisims/HBM_SNGLBLI_INTF_AXI.v @@ -0,0 +1,3235 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HBM_SNGLBLI_INTF_AXI +// /___/ /\ Filename : HBM_SNGLBLI_INTF_AXI.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HBM_SNGLBLI_INTF_AXI #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CLK_SEL = "FALSE", + parameter integer DATARATE = 1800, + parameter [0:0] IS_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_ARESET_N_INVERTED = 1'b0, + parameter MC_ENABLE = "FALSE", + parameter integer PAGEHIT_PERCENT = 75, + parameter PHY_ENABLE = "FALSE", + parameter integer READ_PERCENT = 50, + parameter SWITCH_ENABLE = "FALSE", + parameter integer WRITE_PERCENT = 50 +)( + output ARREADY_PIPE, + output AWREADY_PIPE, + output [5:0] BID_PIPE, + output [1:0] BRESP_PIPE, + output BVALID_PIPE, + output [1:0] DFI_AW_AERR_N_PIPE, + output DFI_CLK_BUF, + output DFI_CTRLUPD_ACK_PIPE, + output [7:0] DFI_DBI_BYTE_DISABLE_PIPE, + output [20:0] DFI_DW_RDDATA_DBI_PIPE, + output [7:0] DFI_DW_RDDATA_DERR_PIPE, + output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE, + output [1:0] DFI_DW_RDDATA_VALID_PIPE, + output DFI_INIT_COMPLETE_PIPE, + output DFI_PHYUPD_REQ_PIPE, + output DFI_PHYUPD_TYPE_PIPE, + output DFI_PHY_LP_STATE_PIPE, + output DFI_RST_N_BUF, + output [5:0] MC_STATUS, + output [7:0] PHY_STATUS, + output [31:0] RDATA_PARITY_PIPE, + output [255:0] RDATA_PIPE, + output [5:0] RID_PIPE, + output RLAST_PIPE, + output [1:0] RRESP_PIPE, + output RVALID_PIPE, + output [5:0] STATUS, + output WREADY_PIPE, + + input ACLK, + input [36:0] ARADDR, + input [1:0] ARBURST, + input ARESET_N, + input [5:0] ARID, + input [3:0] ARLEN, + input [2:0] ARSIZE, + input ARVALID, + input [36:0] AWADDR, + input [1:0] AWBURST, + input [5:0] AWID, + input [3:0] AWLEN, + input [2:0] AWSIZE, + input AWVALID, + input BREADY, + input BSCAN_CK, + input DFI_LP_PWR_X_REQ, + input MBIST_EN, + input RREADY, + input [255:0] WDATA, + input [31:0] WDATA_PARITY, + input WLAST, + input [31:0] WSTRB, + input WVALID +); + +// define constants + localparam MODULE_NAME = "HBM_SNGLBLI_INTF_AXI"; + +// Parameter encodings and registers + localparam CLK_SEL_FALSE = 0; + localparam CLK_SEL_TRUE = 1; + localparam MC_ENABLE_FALSE = 0; + localparam MC_ENABLE_TRUE = 1; + localparam PHY_ENABLE_FALSE = 0; + localparam PHY_ENABLE_TRUE = 1; + localparam SWITCH_ENABLE_FALSE = 0; + localparam SWITCH_ENABLE_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HBM_SNGLBLI_INTF_AXI_dr.v" +`else + localparam [40:1] CLK_SEL_REG = CLK_SEL; + localparam [31:0] DATARATE_REG = DATARATE; + localparam [0:0] IS_ACLK_INVERTED_REG = IS_ACLK_INVERTED; + localparam [0:0] IS_ARESET_N_INVERTED_REG = IS_ARESET_N_INVERTED; + localparam [40:1] MC_ENABLE_REG = MC_ENABLE; + localparam [31:0] PAGEHIT_PERCENT_REG = PAGEHIT_PERCENT; + localparam [40:1] PHY_ENABLE_REG = PHY_ENABLE; + localparam [31:0] READ_PERCENT_REG = READ_PERCENT; + localparam [40:1] SWITCH_ENABLE_REG = SWITCH_ENABLE; + localparam [31:0] WRITE_PERCENT_REG = WRITE_PERCENT; +`endif + +`ifdef XIL_XECLIB + wire CLK_SEL_BIN; + wire [10:0] DATARATE_BIN; + wire MC_ENABLE_BIN; + wire [6:0] PAGEHIT_PERCENT_BIN; + wire PHY_ENABLE_BIN; + wire [6:0] READ_PERCENT_BIN; + wire SWITCH_ENABLE_BIN; + wire [6:0] WRITE_PERCENT_BIN; +`else + reg CLK_SEL_BIN; + reg [10:0] DATARATE_BIN; + reg MC_ENABLE_BIN; + reg [6:0] PAGEHIT_PERCENT_BIN; + reg PHY_ENABLE_BIN; + reg [6:0] READ_PERCENT_BIN; + reg SWITCH_ENABLE_BIN; + reg [6:0] WRITE_PERCENT_BIN; +`endif + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire ACLK_in; + wire ARESET_N_in; + wire ARVALID_in; + wire AWVALID_in; + wire BREADY_in; + wire BSCAN_CK_in; + wire DFI_LP_PWR_X_REQ_in; + wire MBIST_EN_in; + wire RREADY_in; + wire WLAST_in; + wire WVALID_in; + wire [1:0] ARBURST_in; + wire [1:0] AWBURST_in; + wire [255:0] WDATA_in; + wire [2:0] ARSIZE_in; + wire [2:0] AWSIZE_in; + wire [31:0] WDATA_PARITY_in; + wire [31:0] WSTRB_in; + wire [36:0] ARADDR_in; + wire [36:0] AWADDR_in; + wire [3:0] ARLEN_in; + wire [3:0] AWLEN_in; + wire [5:0] ARID_in; + wire [5:0] AWID_in; + +`ifdef XIL_TIMING + wire ACLK_delay; + wire ARESET_N_delay; + wire ARVALID_delay; + wire AWVALID_delay; + wire BREADY_delay; + wire DFI_LP_PWR_X_REQ_delay; + wire RREADY_delay; + wire WLAST_delay; + wire WVALID_delay; + wire [1:0] ARBURST_delay; + wire [1:0] AWBURST_delay; + wire [255:0] WDATA_delay; + wire [2:0] ARSIZE_delay; + wire [2:0] AWSIZE_delay; + wire [31:0] WDATA_PARITY_delay; + wire [31:0] WSTRB_delay; + wire [36:0] ARADDR_delay; + wire [36:0] AWADDR_delay; + wire [3:0] ARLEN_delay; + wire [3:0] AWLEN_delay; + wire [5:0] ARID_delay; + wire [5:0] AWID_delay; +`endif + +`ifdef XIL_TIMING + assign ACLK_in = ACLK_delay; + assign ARADDR_in = ARADDR_delay; + assign ARBURST_in = ARBURST_delay; + assign ARESET_N_in = ARESET_N_delay; + assign ARID_in = ARID_delay; + assign ARLEN_in = ARLEN_delay; + assign ARSIZE_in = ARSIZE_delay; + assign ARVALID_in = ARVALID_delay; + assign AWADDR_in = AWADDR_delay; + assign AWBURST_in = AWBURST_delay; + assign AWID_in = AWID_delay; + assign AWLEN_in = AWLEN_delay; + assign AWSIZE_in = AWSIZE_delay; + assign AWVALID_in = AWVALID_delay; + assign BREADY_in = BREADY_delay; + assign DFI_LP_PWR_X_REQ_in = DFI_LP_PWR_X_REQ_delay; + assign RREADY_in = RREADY_delay; + assign WDATA_PARITY_in = WDATA_PARITY_delay; + assign WDATA_in = WDATA_delay; + assign WLAST_in = WLAST_delay; + assign WSTRB_in = WSTRB_delay; + assign WVALID_in = WVALID_delay; +`else + assign ACLK_in = ACLK; + assign ARADDR_in = ARADDR; + assign ARBURST_in = ARBURST; + assign ARESET_N_in = ARESET_N; + assign ARID_in = ARID; + assign ARLEN_in = ARLEN; + assign ARSIZE_in = ARSIZE; + assign ARVALID_in = ARVALID; + assign AWADDR_in = AWADDR; + assign AWBURST_in = AWBURST; + assign AWID_in = AWID; + assign AWLEN_in = AWLEN; + assign AWSIZE_in = AWSIZE; + assign AWVALID_in = AWVALID; + assign BREADY_in = BREADY; + assign DFI_LP_PWR_X_REQ_in = DFI_LP_PWR_X_REQ; + assign RREADY_in = RREADY; + assign WDATA_PARITY_in = WDATA_PARITY; + assign WDATA_in = WDATA; + assign WLAST_in = WLAST; + assign WSTRB_in = WSTRB; + assign WVALID_in = WVALID; +`endif + + assign BSCAN_CK_in = BSCAN_CK; + assign MBIST_EN_in = MBIST_EN; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CLK_SEL_BIN = + (CLK_SEL_REG == "FALSE") ? CLK_SEL_FALSE : + (CLK_SEL_REG == "TRUE") ? CLK_SEL_TRUE : + CLK_SEL_FALSE; + + assign DATARATE_BIN = DATARATE_REG[10:0]; + + assign MC_ENABLE_BIN = + (MC_ENABLE_REG == "FALSE") ? MC_ENABLE_FALSE : + (MC_ENABLE_REG == "TRUE") ? MC_ENABLE_TRUE : + MC_ENABLE_FALSE; + + assign PAGEHIT_PERCENT_BIN = PAGEHIT_PERCENT_REG[6:0]; + + assign PHY_ENABLE_BIN = + (PHY_ENABLE_REG == "FALSE") ? PHY_ENABLE_FALSE : + (PHY_ENABLE_REG == "TRUE") ? PHY_ENABLE_TRUE : + PHY_ENABLE_FALSE; + + assign READ_PERCENT_BIN = READ_PERCENT_REG[6:0]; + + assign SWITCH_ENABLE_BIN = + (SWITCH_ENABLE_REG == "FALSE") ? SWITCH_ENABLE_FALSE : + (SWITCH_ENABLE_REG == "TRUE") ? SWITCH_ENABLE_TRUE : + SWITCH_ENABLE_FALSE; + + assign WRITE_PERCENT_BIN = WRITE_PERCENT_REG[6:0]; + +`else + always @ (trig_attr) begin + #1; + CLK_SEL_BIN = + (CLK_SEL_REG == "FALSE") ? CLK_SEL_FALSE : + (CLK_SEL_REG == "TRUE") ? CLK_SEL_TRUE : + CLK_SEL_FALSE; + + DATARATE_BIN = DATARATE_REG[10:0]; + + MC_ENABLE_BIN = + (MC_ENABLE_REG == "FALSE") ? MC_ENABLE_FALSE : + (MC_ENABLE_REG == "TRUE") ? MC_ENABLE_TRUE : + MC_ENABLE_FALSE; + + PAGEHIT_PERCENT_BIN = PAGEHIT_PERCENT_REG[6:0]; + + PHY_ENABLE_BIN = + (PHY_ENABLE_REG == "FALSE") ? PHY_ENABLE_FALSE : + (PHY_ENABLE_REG == "TRUE") ? PHY_ENABLE_TRUE : + PHY_ENABLE_FALSE; + + READ_PERCENT_BIN = READ_PERCENT_REG[6:0]; + + SWITCH_ENABLE_BIN = + (SWITCH_ENABLE_REG == "FALSE") ? SWITCH_ENABLE_FALSE : + (SWITCH_ENABLE_REG == "TRUE") ? SWITCH_ENABLE_TRUE : + SWITCH_ENABLE_FALSE; + + WRITE_PERCENT_BIN = WRITE_PERCENT_REG[6:0]; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLK_SEL_REG != "FALSE") && + (CLK_SEL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] CLK_SEL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_REG < 50) || (DATARATE_REG > 1800))) begin + $display("Error: [Unisim %s-102] DATARATE attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_REG != "FALSE") && + (MC_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] MC_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PAGEHIT_PERCENT_REG < 0) || (PAGEHIT_PERCENT_REG > 100))) begin + $display("Error: [Unisim %s-106] PAGEHIT_PERCENT attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_REG != "FALSE") && + (PHY_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] PHY_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_REG < 0) || (READ_PERCENT_REG > 100))) begin + $display("Error: [Unisim %s-108] READ_PERCENT attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SWITCH_ENABLE_REG != "FALSE") && + (SWITCH_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] SWITCH_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_REG < 0) || (WRITE_PERCENT_REG > 100))) begin + $display("Error: [Unisim %s-110] WRITE_PERCENT attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + +// end behavioral model + +`ifndef XIL_XECLIB + specify + (ACLK => ARREADY_PIPE) = (100:100:100, 100:100:100); + (ACLK => AWREADY_PIPE) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => BID_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => BRESP_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => BRESP_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => BVALID_PIPE) = (100:100:100, 100:100:100); + (ACLK => DFI_AW_AERR_N_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_AW_AERR_N_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_CTRLUPD_ACK_PIPE) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[6]) = (100:100:100, 100:100:100); + (ACLK => DFI_DBI_BYTE_DISABLE_PIPE[7]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[10]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[11]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[12]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[13]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[14]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[15]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[16]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[17]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[18]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[19]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[20]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[6]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[7]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[8]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DBI_PIPE[9]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[6]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_DERR_PIPE[7]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_PAR_VALID_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_PAR_VALID_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_VALID_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => DFI_DW_RDDATA_VALID_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => DFI_INIT_COMPLETE_PIPE) = (100:100:100, 100:100:100); + (ACLK => DFI_PHYUPD_REQ_PIPE) = (100:100:100, 100:100:100); + (ACLK => DFI_PHYUPD_TYPE_PIPE) = (100:100:100, 100:100:100); + (ACLK => DFI_PHY_LP_STATE_PIPE) = (100:100:100, 100:100:100); + (ACLK => PHY_STATUS[0]) = (100:100:100, 100:100:100); + (ACLK => PHY_STATUS[1]) = (100:100:100, 100:100:100); + (ACLK => PHY_STATUS[2]) = (100:100:100, 100:100:100); + (ACLK => PHY_STATUS[3]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[10]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[11]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[12]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[13]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[14]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[15]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[16]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[17]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[18]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[19]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[20]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[21]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[22]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[23]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[24]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[25]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[26]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[27]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[28]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[29]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[30]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[31]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[6]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[7]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[8]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PARITY_PIPE[9]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[100]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[101]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[102]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[103]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[104]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[105]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[106]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[107]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[108]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[109]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[10]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[110]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[111]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[112]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[113]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[114]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[115]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[116]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[117]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[118]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[119]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[11]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[120]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[121]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[122]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[123]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[124]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[125]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[126]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[127]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[128]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[129]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[12]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[130]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[131]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[132]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[133]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[134]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[135]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[136]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[137]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[138]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[139]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[13]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[140]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[141]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[142]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[143]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[144]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[145]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[146]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[147]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[148]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[149]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[14]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[150]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[151]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[152]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[153]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[154]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[155]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[156]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[157]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[158]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[159]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[15]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[160]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[161]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[162]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[163]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[164]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[165]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[166]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[167]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[168]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[169]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[16]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[170]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[171]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[172]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[173]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[174]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[175]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[176]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[177]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[178]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[179]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[17]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[180]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[181]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[182]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[183]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[184]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[185]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[186]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[187]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[188]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[189]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[18]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[190]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[191]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[192]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[193]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[194]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[195]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[196]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[197]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[198]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[199]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[19]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[200]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[201]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[202]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[203]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[204]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[205]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[206]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[207]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[208]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[209]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[20]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[210]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[211]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[212]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[213]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[214]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[215]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[216]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[217]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[218]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[219]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[21]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[220]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[221]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[222]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[223]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[224]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[225]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[226]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[227]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[228]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[229]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[22]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[230]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[231]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[232]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[233]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[234]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[235]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[236]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[237]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[238]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[239]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[23]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[240]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[241]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[242]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[243]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[244]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[245]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[246]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[247]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[248]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[249]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[24]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[250]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[251]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[252]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[253]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[254]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[255]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[25]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[26]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[27]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[28]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[29]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[30]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[31]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[32]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[33]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[34]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[35]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[36]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[37]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[38]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[39]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[40]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[41]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[42]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[43]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[44]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[45]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[46]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[47]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[48]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[49]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[50]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[51]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[52]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[53]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[54]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[55]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[56]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[57]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[58]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[59]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[60]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[61]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[62]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[63]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[64]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[65]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[66]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[67]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[68]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[69]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[6]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[70]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[71]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[72]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[73]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[74]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[75]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[76]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[77]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[78]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[79]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[7]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[80]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[81]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[82]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[83]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[84]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[85]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[86]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[87]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[88]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[89]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[8]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[90]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[91]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[92]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[93]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[94]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[95]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[96]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[97]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[98]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[99]) = (100:100:100, 100:100:100); + (ACLK => RDATA_PIPE[9]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[2]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[3]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[4]) = (100:100:100, 100:100:100); + (ACLK => RID_PIPE[5]) = (100:100:100, 100:100:100); + (ACLK => RLAST_PIPE) = (100:100:100, 100:100:100); + (ACLK => RRESP_PIPE[0]) = (100:100:100, 100:100:100); + (ACLK => RRESP_PIPE[1]) = (100:100:100, 100:100:100); + (ACLK => RVALID_PIPE) = (100:100:100, 100:100:100); + (ACLK => WREADY_PIPE) = (100:100:100, 100:100:100); + (negedge ARESET_N => (ARREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (AWREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BID_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BRESP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BRESP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (BVALID_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_AW_AERR_N_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_AW_AERR_N_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_CTRLUPD_ACK_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_PAR_VALID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_PAR_VALID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_VALID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_DW_RDDATA_VALID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_INIT_COMPLETE_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_PHYUPD_REQ_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_PHYUPD_TYPE_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (DFI_PHY_LP_STATE_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (PHY_STATUS[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (PHY_STATUS[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (PHY_STATUS[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (PHY_STATUS[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PARITY_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[100] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[101] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[102] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[103] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[104] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[105] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[106] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[107] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[108] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[109] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[110] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[111] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[112] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[113] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[114] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[115] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[116] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[117] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[118] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[119] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[120] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[121] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[122] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[123] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[124] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[125] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[126] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[127] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[128] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[129] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[130] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[131] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[132] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[133] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[134] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[135] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[136] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[137] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[138] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[139] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[140] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[141] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[142] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[143] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[144] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[145] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[146] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[147] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[148] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[149] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[150] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[151] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[152] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[153] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[154] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[155] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[156] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[157] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[158] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[159] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[160] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[161] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[162] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[163] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[164] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[165] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[166] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[167] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[168] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[169] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[170] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[171] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[172] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[173] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[174] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[175] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[176] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[177] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[178] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[179] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[180] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[181] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[182] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[183] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[184] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[185] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[186] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[187] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[188] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[189] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[190] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[191] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[192] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[193] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[194] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[195] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[196] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[197] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[198] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[199] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[200] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[201] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[202] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[203] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[204] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[205] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[206] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[207] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[208] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[209] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[210] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[211] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[212] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[213] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[214] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[215] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[216] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[217] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[218] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[219] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[220] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[221] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[222] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[223] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[224] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[225] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[226] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[227] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[228] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[229] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[230] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[231] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[232] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[233] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[234] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[235] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[236] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[237] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[238] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[239] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[240] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[241] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[242] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[243] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[244] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[245] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[246] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[247] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[248] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[249] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[250] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[251] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[252] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[253] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[254] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[255] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[32] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[33] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[34] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[35] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[36] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[37] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[38] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[39] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[40] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[41] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[42] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[43] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[44] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[45] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[46] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[47] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[48] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[49] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[50] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[51] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[52] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[53] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[54] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[55] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[56] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[57] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[58] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[59] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[60] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[61] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[62] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[63] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[64] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[65] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[66] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[67] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[68] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[69] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[70] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[71] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[72] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[73] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[74] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[75] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[76] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[77] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[78] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[79] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[80] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[81] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[82] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[83] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[84] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[85] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[86] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[87] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[88] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[89] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[90] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[91] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[92] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[93] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[94] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[95] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[96] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[97] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[98] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[99] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RDATA_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RID_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RLAST_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RRESP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RRESP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (RVALID_PIPE +: 1)) = (100:100:100, 100:100:100); + (negedge ARESET_N => (WREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (ARREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (AWREADY_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BID_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BRESP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BRESP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (BVALID_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_AW_AERR_N_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_AW_AERR_N_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_CTRLUPD_ACK_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DBI_BYTE_DISABLE_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DBI_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_DERR_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_PAR_VALID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_PAR_VALID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_VALID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_DW_RDDATA_VALID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_INIT_COMPLETE_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_PHYUPD_REQ_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_PHYUPD_TYPE_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (DFI_PHY_LP_STATE_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (PHY_STATUS[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (PHY_STATUS[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (PHY_STATUS[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (PHY_STATUS[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PARITY_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[100] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[101] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[102] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[103] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[104] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[105] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[106] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[107] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[108] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[109] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[10] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[110] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[111] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[112] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[113] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[114] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[115] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[116] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[117] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[118] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[119] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[11] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[120] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[121] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[122] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[123] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[124] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[125] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[126] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[127] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[128] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[129] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[12] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[130] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[131] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[132] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[133] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[134] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[135] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[136] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[137] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[138] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[139] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[13] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[140] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[141] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[142] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[143] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[144] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[145] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[146] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[147] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[148] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[149] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[14] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[150] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[151] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[152] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[153] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[154] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[155] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[156] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[157] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[158] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[159] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[15] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[160] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[161] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[162] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[163] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[164] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[165] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[166] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[167] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[168] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[169] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[16] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[170] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[171] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[172] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[173] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[174] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[175] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[176] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[177] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[178] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[179] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[17] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[180] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[181] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[182] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[183] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[184] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[185] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[186] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[187] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[188] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[189] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[18] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[190] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[191] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[192] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[193] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[194] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[195] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[196] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[197] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[198] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[199] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[19] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[200] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[201] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[202] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[203] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[204] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[205] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[206] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[207] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[208] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[209] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[20] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[210] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[211] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[212] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[213] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[214] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[215] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[216] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[217] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[218] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[219] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[21] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[220] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[221] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[222] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[223] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[224] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[225] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[226] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[227] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[228] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[229] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[22] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[230] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[231] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[232] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[233] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[234] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[235] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[236] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[237] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[238] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[239] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[23] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[240] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[241] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[242] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[243] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[244] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[245] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[246] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[247] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[248] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[249] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[24] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[250] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[251] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[252] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[253] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[254] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[255] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[25] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[26] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[27] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[28] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[29] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[30] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[31] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[32] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[33] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[34] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[35] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[36] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[37] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[38] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[39] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[40] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[41] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[42] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[43] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[44] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[45] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[46] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[47] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[48] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[49] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[50] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[51] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[52] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[53] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[54] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[55] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[56] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[57] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[58] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[59] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[60] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[61] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[62] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[63] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[64] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[65] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[66] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[67] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[68] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[69] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[6] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[70] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[71] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[72] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[73] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[74] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[75] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[76] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[77] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[78] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[79] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[7] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[80] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[81] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[82] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[83] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[84] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[85] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[86] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[87] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[88] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[89] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[8] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[90] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[91] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[92] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[93] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[94] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[95] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[96] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[97] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[98] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[99] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RDATA_PIPE[9] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[2] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[3] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[4] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RID_PIPE[5] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RLAST_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RRESP_PIPE[0] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RRESP_PIPE[1] +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (RVALID_PIPE +: 1)) = (100:100:100, 100:100:100); + (posedge ARESET_N => (WREADY_PIPE +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $recrem (negedge ARESET_N, negedge ACLK, 0:0:0, 0:0:0, notifier, , , ARESET_N_delay, ACLK_delay); + $recrem (negedge ARESET_N, posedge ACLK, 0:0:0, 0:0:0, notifier, , , ARESET_N_delay, ACLK_delay); + $recrem (posedge ARESET_N, negedge ACLK, 0:0:0, 0:0:0, notifier, , , ARESET_N_delay, ACLK_delay); + $recrem (posedge ARESET_N, posedge ACLK, 0:0:0, 0:0:0, notifier, , , ARESET_N_delay, ACLK_delay); + $setuphold (negedge ACLK, negedge ARADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[0]); + $setuphold (negedge ACLK, negedge ARADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[10]); + $setuphold (negedge ACLK, negedge ARADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[11]); + $setuphold (negedge ACLK, negedge ARADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[12]); + $setuphold (negedge ACLK, negedge ARADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[13]); + $setuphold (negedge ACLK, negedge ARADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[14]); + $setuphold (negedge ACLK, negedge ARADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[15]); + $setuphold (negedge ACLK, negedge ARADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[16]); + $setuphold (negedge ACLK, negedge ARADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[17]); + $setuphold (negedge ACLK, negedge ARADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[18]); + $setuphold (negedge ACLK, negedge ARADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[19]); + $setuphold (negedge ACLK, negedge ARADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[1]); + $setuphold (negedge ACLK, negedge ARADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[20]); + $setuphold (negedge ACLK, negedge ARADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[21]); + $setuphold (negedge ACLK, negedge ARADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[22]); + $setuphold (negedge ACLK, negedge ARADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[23]); + $setuphold (negedge ACLK, negedge ARADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[24]); + $setuphold (negedge ACLK, negedge ARADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[25]); + $setuphold (negedge ACLK, negedge ARADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[26]); + $setuphold (negedge ACLK, negedge ARADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[27]); + $setuphold (negedge ACLK, negedge ARADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[28]); + $setuphold (negedge ACLK, negedge ARADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[29]); + $setuphold (negedge ACLK, negedge ARADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[2]); + $setuphold (negedge ACLK, negedge ARADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[30]); + $setuphold (negedge ACLK, negedge ARADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[31]); + $setuphold (negedge ACLK, negedge ARADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[32]); + $setuphold (negedge ACLK, negedge ARADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[33]); + $setuphold (negedge ACLK, negedge ARADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[34]); + $setuphold (negedge ACLK, negedge ARADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[35]); + $setuphold (negedge ACLK, negedge ARADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[36]); + $setuphold (negedge ACLK, negedge ARADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[3]); + $setuphold (negedge ACLK, negedge ARADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[4]); + $setuphold (negedge ACLK, negedge ARADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[5]); + $setuphold (negedge ACLK, negedge ARADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[6]); + $setuphold (negedge ACLK, negedge ARADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[7]); + $setuphold (negedge ACLK, negedge ARADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[8]); + $setuphold (negedge ACLK, negedge ARADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[9]); + $setuphold (negedge ACLK, negedge ARBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[0]); + $setuphold (negedge ACLK, negedge ARBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[1]); + $setuphold (negedge ACLK, negedge ARID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[0]); + $setuphold (negedge ACLK, negedge ARID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[1]); + $setuphold (negedge ACLK, negedge ARID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[2]); + $setuphold (negedge ACLK, negedge ARID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[3]); + $setuphold (negedge ACLK, negedge ARID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[4]); + $setuphold (negedge ACLK, negedge ARID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[5]); + $setuphold (negedge ACLK, negedge ARLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[0]); + $setuphold (negedge ACLK, negedge ARLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[1]); + $setuphold (negedge ACLK, negedge ARLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[2]); + $setuphold (negedge ACLK, negedge ARLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[3]); + $setuphold (negedge ACLK, negedge ARSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[0]); + $setuphold (negedge ACLK, negedge ARSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[1]); + $setuphold (negedge ACLK, negedge ARSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[2]); + $setuphold (negedge ACLK, negedge ARVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARVALID_delay); + $setuphold (negedge ACLK, negedge AWADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[0]); + $setuphold (negedge ACLK, negedge AWADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[10]); + $setuphold (negedge ACLK, negedge AWADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[11]); + $setuphold (negedge ACLK, negedge AWADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[12]); + $setuphold (negedge ACLK, negedge AWADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[13]); + $setuphold (negedge ACLK, negedge AWADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[14]); + $setuphold (negedge ACLK, negedge AWADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[15]); + $setuphold (negedge ACLK, negedge AWADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[16]); + $setuphold (negedge ACLK, negedge AWADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[17]); + $setuphold (negedge ACLK, negedge AWADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[18]); + $setuphold (negedge ACLK, negedge AWADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[19]); + $setuphold (negedge ACLK, negedge AWADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[1]); + $setuphold (negedge ACLK, negedge AWADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[20]); + $setuphold (negedge ACLK, negedge AWADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[21]); + $setuphold (negedge ACLK, negedge AWADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[22]); + $setuphold (negedge ACLK, negedge AWADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[23]); + $setuphold (negedge ACLK, negedge AWADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[24]); + $setuphold (negedge ACLK, negedge AWADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[25]); + $setuphold (negedge ACLK, negedge AWADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[26]); + $setuphold (negedge ACLK, negedge AWADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[27]); + $setuphold (negedge ACLK, negedge AWADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[28]); + $setuphold (negedge ACLK, negedge AWADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[29]); + $setuphold (negedge ACLK, negedge AWADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[2]); + $setuphold (negedge ACLK, negedge AWADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[30]); + $setuphold (negedge ACLK, negedge AWADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[31]); + $setuphold (negedge ACLK, negedge AWADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[32]); + $setuphold (negedge ACLK, negedge AWADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[33]); + $setuphold (negedge ACLK, negedge AWADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[34]); + $setuphold (negedge ACLK, negedge AWADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[35]); + $setuphold (negedge ACLK, negedge AWADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[36]); + $setuphold (negedge ACLK, negedge AWADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[3]); + $setuphold (negedge ACLK, negedge AWADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[4]); + $setuphold (negedge ACLK, negedge AWADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[5]); + $setuphold (negedge ACLK, negedge AWADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[6]); + $setuphold (negedge ACLK, negedge AWADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[7]); + $setuphold (negedge ACLK, negedge AWADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[8]); + $setuphold (negedge ACLK, negedge AWADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[9]); + $setuphold (negedge ACLK, negedge AWBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[0]); + $setuphold (negedge ACLK, negedge AWBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[1]); + $setuphold (negedge ACLK, negedge AWID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[0]); + $setuphold (negedge ACLK, negedge AWID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[1]); + $setuphold (negedge ACLK, negedge AWID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[2]); + $setuphold (negedge ACLK, negedge AWID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[3]); + $setuphold (negedge ACLK, negedge AWID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[4]); + $setuphold (negedge ACLK, negedge AWID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[5]); + $setuphold (negedge ACLK, negedge AWLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[0]); + $setuphold (negedge ACLK, negedge AWLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[1]); + $setuphold (negedge ACLK, negedge AWLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[2]); + $setuphold (negedge ACLK, negedge AWLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[3]); + $setuphold (negedge ACLK, negedge AWSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[0]); + $setuphold (negedge ACLK, negedge AWSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[1]); + $setuphold (negedge ACLK, negedge AWSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[2]); + $setuphold (negedge ACLK, negedge AWVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWVALID_delay); + $setuphold (negedge ACLK, negedge BREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, BREADY_delay); + $setuphold (negedge ACLK, negedge DFI_LP_PWR_X_REQ, 0:0:0, 0:0:0, notifier, , , ACLK_delay, DFI_LP_PWR_X_REQ_delay); + $setuphold (negedge ACLK, negedge RREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, RREADY_delay); + $setuphold (negedge ACLK, negedge WDATA[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[0]); + $setuphold (negedge ACLK, negedge WDATA[100], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[100]); + $setuphold (negedge ACLK, negedge WDATA[101], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[101]); + $setuphold (negedge ACLK, negedge WDATA[102], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[102]); + $setuphold (negedge ACLK, negedge WDATA[103], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[103]); + $setuphold (negedge ACLK, negedge WDATA[104], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[104]); + $setuphold (negedge ACLK, negedge WDATA[105], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[105]); + $setuphold (negedge ACLK, negedge WDATA[106], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[106]); + $setuphold (negedge ACLK, negedge WDATA[107], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[107]); + $setuphold (negedge ACLK, negedge WDATA[108], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[108]); + $setuphold (negedge ACLK, negedge WDATA[109], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[109]); + $setuphold (negedge ACLK, negedge WDATA[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[10]); + $setuphold (negedge ACLK, negedge WDATA[110], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[110]); + $setuphold (negedge ACLK, negedge WDATA[111], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[111]); + $setuphold (negedge ACLK, negedge WDATA[112], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[112]); + $setuphold (negedge ACLK, negedge WDATA[113], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[113]); + $setuphold (negedge ACLK, negedge WDATA[114], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[114]); + $setuphold (negedge ACLK, negedge WDATA[115], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[115]); + $setuphold (negedge ACLK, negedge WDATA[116], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[116]); + $setuphold (negedge ACLK, negedge WDATA[117], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[117]); + $setuphold (negedge ACLK, negedge WDATA[118], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[118]); + $setuphold (negedge ACLK, negedge WDATA[119], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[119]); + $setuphold (negedge ACLK, negedge WDATA[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[11]); + $setuphold (negedge ACLK, negedge WDATA[120], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[120]); + $setuphold (negedge ACLK, negedge WDATA[121], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[121]); + $setuphold (negedge ACLK, negedge WDATA[122], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[122]); + $setuphold (negedge ACLK, negedge WDATA[123], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[123]); + $setuphold (negedge ACLK, negedge WDATA[124], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[124]); + $setuphold (negedge ACLK, negedge WDATA[125], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[125]); + $setuphold (negedge ACLK, negedge WDATA[126], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[126]); + $setuphold (negedge ACLK, negedge WDATA[127], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[127]); + $setuphold (negedge ACLK, negedge WDATA[128], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[128]); + $setuphold (negedge ACLK, negedge WDATA[129], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[129]); + $setuphold (negedge ACLK, negedge WDATA[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[12]); + $setuphold (negedge ACLK, negedge WDATA[130], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[130]); + $setuphold (negedge ACLK, negedge WDATA[131], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[131]); + $setuphold (negedge ACLK, negedge WDATA[132], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[132]); + $setuphold (negedge ACLK, negedge WDATA[133], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[133]); + $setuphold (negedge ACLK, negedge WDATA[134], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[134]); + $setuphold (negedge ACLK, negedge WDATA[135], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[135]); + $setuphold (negedge ACLK, negedge WDATA[136], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[136]); + $setuphold (negedge ACLK, negedge WDATA[137], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[137]); + $setuphold (negedge ACLK, negedge WDATA[138], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[138]); + $setuphold (negedge ACLK, negedge WDATA[139], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[139]); + $setuphold (negedge ACLK, negedge WDATA[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[13]); + $setuphold (negedge ACLK, negedge WDATA[140], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[140]); + $setuphold (negedge ACLK, negedge WDATA[141], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[141]); + $setuphold (negedge ACLK, negedge WDATA[142], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[142]); + $setuphold (negedge ACLK, negedge WDATA[143], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[143]); + $setuphold (negedge ACLK, negedge WDATA[144], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[144]); + $setuphold (negedge ACLK, negedge WDATA[145], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[145]); + $setuphold (negedge ACLK, negedge WDATA[146], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[146]); + $setuphold (negedge ACLK, negedge WDATA[147], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[147]); + $setuphold (negedge ACLK, negedge WDATA[148], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[148]); + $setuphold (negedge ACLK, negedge WDATA[149], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[149]); + $setuphold (negedge ACLK, negedge WDATA[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[14]); + $setuphold (negedge ACLK, negedge WDATA[150], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[150]); + $setuphold (negedge ACLK, negedge WDATA[151], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[151]); + $setuphold (negedge ACLK, negedge WDATA[152], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[152]); + $setuphold (negedge ACLK, negedge WDATA[153], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[153]); + $setuphold (negedge ACLK, negedge WDATA[154], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[154]); + $setuphold (negedge ACLK, negedge WDATA[155], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[155]); + $setuphold (negedge ACLK, negedge WDATA[156], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[156]); + $setuphold (negedge ACLK, negedge WDATA[157], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[157]); + $setuphold (negedge ACLK, negedge WDATA[158], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[158]); + $setuphold (negedge ACLK, negedge WDATA[159], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[159]); + $setuphold (negedge ACLK, negedge WDATA[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[15]); + $setuphold (negedge ACLK, negedge WDATA[160], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[160]); + $setuphold (negedge ACLK, negedge WDATA[161], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[161]); + $setuphold (negedge ACLK, negedge WDATA[162], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[162]); + $setuphold (negedge ACLK, negedge WDATA[163], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[163]); + $setuphold (negedge ACLK, negedge WDATA[164], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[164]); + $setuphold (negedge ACLK, negedge WDATA[165], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[165]); + $setuphold (negedge ACLK, negedge WDATA[166], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[166]); + $setuphold (negedge ACLK, negedge WDATA[167], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[167]); + $setuphold (negedge ACLK, negedge WDATA[168], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[168]); + $setuphold (negedge ACLK, negedge WDATA[169], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[169]); + $setuphold (negedge ACLK, negedge WDATA[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[16]); + $setuphold (negedge ACLK, negedge WDATA[170], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[170]); + $setuphold (negedge ACLK, negedge WDATA[171], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[171]); + $setuphold (negedge ACLK, negedge WDATA[172], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[172]); + $setuphold (negedge ACLK, negedge WDATA[173], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[173]); + $setuphold (negedge ACLK, negedge WDATA[174], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[174]); + $setuphold (negedge ACLK, negedge WDATA[175], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[175]); + $setuphold (negedge ACLK, negedge WDATA[176], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[176]); + $setuphold (negedge ACLK, negedge WDATA[177], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[177]); + $setuphold (negedge ACLK, negedge WDATA[178], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[178]); + $setuphold (negedge ACLK, negedge WDATA[179], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[179]); + $setuphold (negedge ACLK, negedge WDATA[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[17]); + $setuphold (negedge ACLK, negedge WDATA[180], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[180]); + $setuphold (negedge ACLK, negedge WDATA[181], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[181]); + $setuphold (negedge ACLK, negedge WDATA[182], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[182]); + $setuphold (negedge ACLK, negedge WDATA[183], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[183]); + $setuphold (negedge ACLK, negedge WDATA[184], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[184]); + $setuphold (negedge ACLK, negedge WDATA[185], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[185]); + $setuphold (negedge ACLK, negedge WDATA[186], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[186]); + $setuphold (negedge ACLK, negedge WDATA[187], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[187]); + $setuphold (negedge ACLK, negedge WDATA[188], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[188]); + $setuphold (negedge ACLK, negedge WDATA[189], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[189]); + $setuphold (negedge ACLK, negedge WDATA[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[18]); + $setuphold (negedge ACLK, negedge WDATA[190], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[190]); + $setuphold (negedge ACLK, negedge WDATA[191], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[191]); + $setuphold (negedge ACLK, negedge WDATA[192], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[192]); + $setuphold (negedge ACLK, negedge WDATA[193], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[193]); + $setuphold (negedge ACLK, negedge WDATA[194], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[194]); + $setuphold (negedge ACLK, negedge WDATA[195], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[195]); + $setuphold (negedge ACLK, negedge WDATA[196], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[196]); + $setuphold (negedge ACLK, negedge WDATA[197], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[197]); + $setuphold (negedge ACLK, negedge WDATA[198], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[198]); + $setuphold (negedge ACLK, negedge WDATA[199], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[199]); + $setuphold (negedge ACLK, negedge WDATA[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[19]); + $setuphold (negedge ACLK, negedge WDATA[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[1]); + $setuphold (negedge ACLK, negedge WDATA[200], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[200]); + $setuphold (negedge ACLK, negedge WDATA[201], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[201]); + $setuphold (negedge ACLK, negedge WDATA[202], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[202]); + $setuphold (negedge ACLK, negedge WDATA[203], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[203]); + $setuphold (negedge ACLK, negedge WDATA[204], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[204]); + $setuphold (negedge ACLK, negedge WDATA[205], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[205]); + $setuphold (negedge ACLK, negedge WDATA[206], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[206]); + $setuphold (negedge ACLK, negedge WDATA[207], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[207]); + $setuphold (negedge ACLK, negedge WDATA[208], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[208]); + $setuphold (negedge ACLK, negedge WDATA[209], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[209]); + $setuphold (negedge ACLK, negedge WDATA[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[20]); + $setuphold (negedge ACLK, negedge WDATA[210], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[210]); + $setuphold (negedge ACLK, negedge WDATA[211], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[211]); + $setuphold (negedge ACLK, negedge WDATA[212], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[212]); + $setuphold (negedge ACLK, negedge WDATA[213], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[213]); + $setuphold (negedge ACLK, negedge WDATA[214], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[214]); + $setuphold (negedge ACLK, negedge WDATA[215], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[215]); + $setuphold (negedge ACLK, negedge WDATA[216], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[216]); + $setuphold (negedge ACLK, negedge WDATA[217], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[217]); + $setuphold (negedge ACLK, negedge WDATA[218], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[218]); + $setuphold (negedge ACLK, negedge WDATA[219], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[219]); + $setuphold (negedge ACLK, negedge WDATA[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[21]); + $setuphold (negedge ACLK, negedge WDATA[220], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[220]); + $setuphold (negedge ACLK, negedge WDATA[221], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[221]); + $setuphold (negedge ACLK, negedge WDATA[222], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[222]); + $setuphold (negedge ACLK, negedge WDATA[223], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[223]); + $setuphold (negedge ACLK, negedge WDATA[224], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[224]); + $setuphold (negedge ACLK, negedge WDATA[225], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[225]); + $setuphold (negedge ACLK, negedge WDATA[226], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[226]); + $setuphold (negedge ACLK, negedge WDATA[227], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[227]); + $setuphold (negedge ACLK, negedge WDATA[228], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[228]); + $setuphold (negedge ACLK, negedge WDATA[229], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[229]); + $setuphold (negedge ACLK, negedge WDATA[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[22]); + $setuphold (negedge ACLK, negedge WDATA[230], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[230]); + $setuphold (negedge ACLK, negedge WDATA[231], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[231]); + $setuphold (negedge ACLK, negedge WDATA[232], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[232]); + $setuphold (negedge ACLK, negedge WDATA[233], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[233]); + $setuphold (negedge ACLK, negedge WDATA[234], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[234]); + $setuphold (negedge ACLK, negedge WDATA[235], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[235]); + $setuphold (negedge ACLK, negedge WDATA[236], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[236]); + $setuphold (negedge ACLK, negedge WDATA[237], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[237]); + $setuphold (negedge ACLK, negedge WDATA[238], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[238]); + $setuphold (negedge ACLK, negedge WDATA[239], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[239]); + $setuphold (negedge ACLK, negedge WDATA[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[23]); + $setuphold (negedge ACLK, negedge WDATA[240], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[240]); + $setuphold (negedge ACLK, negedge WDATA[241], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[241]); + $setuphold (negedge ACLK, negedge WDATA[242], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[242]); + $setuphold (negedge ACLK, negedge WDATA[243], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[243]); + $setuphold (negedge ACLK, negedge WDATA[244], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[244]); + $setuphold (negedge ACLK, negedge WDATA[245], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[245]); + $setuphold (negedge ACLK, negedge WDATA[246], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[246]); + $setuphold (negedge ACLK, negedge WDATA[247], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[247]); + $setuphold (negedge ACLK, negedge WDATA[248], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[248]); + $setuphold (negedge ACLK, negedge WDATA[249], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[249]); + $setuphold (negedge ACLK, negedge WDATA[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[24]); + $setuphold (negedge ACLK, negedge WDATA[250], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[250]); + $setuphold (negedge ACLK, negedge WDATA[251], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[251]); + $setuphold (negedge ACLK, negedge WDATA[252], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[252]); + $setuphold (negedge ACLK, negedge WDATA[253], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[253]); + $setuphold (negedge ACLK, negedge WDATA[254], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[254]); + $setuphold (negedge ACLK, negedge WDATA[255], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[255]); + $setuphold (negedge ACLK, negedge WDATA[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[25]); + $setuphold (negedge ACLK, negedge WDATA[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[26]); + $setuphold (negedge ACLK, negedge WDATA[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[27]); + $setuphold (negedge ACLK, negedge WDATA[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[28]); + $setuphold (negedge ACLK, negedge WDATA[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[29]); + $setuphold (negedge ACLK, negedge WDATA[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[2]); + $setuphold (negedge ACLK, negedge WDATA[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[30]); + $setuphold (negedge ACLK, negedge WDATA[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[31]); + $setuphold (negedge ACLK, negedge WDATA[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[32]); + $setuphold (negedge ACLK, negedge WDATA[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[33]); + $setuphold (negedge ACLK, negedge WDATA[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[34]); + $setuphold (negedge ACLK, negedge WDATA[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[35]); + $setuphold (negedge ACLK, negedge WDATA[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[36]); + $setuphold (negedge ACLK, negedge WDATA[37], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[37]); + $setuphold (negedge ACLK, negedge WDATA[38], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[38]); + $setuphold (negedge ACLK, negedge WDATA[39], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[39]); + $setuphold (negedge ACLK, negedge WDATA[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[3]); + $setuphold (negedge ACLK, negedge WDATA[40], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[40]); + $setuphold (negedge ACLK, negedge WDATA[41], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[41]); + $setuphold (negedge ACLK, negedge WDATA[42], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[42]); + $setuphold (negedge ACLK, negedge WDATA[43], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[43]); + $setuphold (negedge ACLK, negedge WDATA[44], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[44]); + $setuphold (negedge ACLK, negedge WDATA[45], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[45]); + $setuphold (negedge ACLK, negedge WDATA[46], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[46]); + $setuphold (negedge ACLK, negedge WDATA[47], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[47]); + $setuphold (negedge ACLK, negedge WDATA[48], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[48]); + $setuphold (negedge ACLK, negedge WDATA[49], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[49]); + $setuphold (negedge ACLK, negedge WDATA[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[4]); + $setuphold (negedge ACLK, negedge WDATA[50], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[50]); + $setuphold (negedge ACLK, negedge WDATA[51], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[51]); + $setuphold (negedge ACLK, negedge WDATA[52], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[52]); + $setuphold (negedge ACLK, negedge WDATA[53], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[53]); + $setuphold (negedge ACLK, negedge WDATA[54], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[54]); + $setuphold (negedge ACLK, negedge WDATA[55], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[55]); + $setuphold (negedge ACLK, negedge WDATA[56], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[56]); + $setuphold (negedge ACLK, negedge WDATA[57], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[57]); + $setuphold (negedge ACLK, negedge WDATA[58], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[58]); + $setuphold (negedge ACLK, negedge WDATA[59], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[59]); + $setuphold (negedge ACLK, negedge WDATA[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[5]); + $setuphold (negedge ACLK, negedge WDATA[60], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[60]); + $setuphold (negedge ACLK, negedge WDATA[61], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[61]); + $setuphold (negedge ACLK, negedge WDATA[62], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[62]); + $setuphold (negedge ACLK, negedge WDATA[63], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[63]); + $setuphold (negedge ACLK, negedge WDATA[64], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[64]); + $setuphold (negedge ACLK, negedge WDATA[65], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[65]); + $setuphold (negedge ACLK, negedge WDATA[66], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[66]); + $setuphold (negedge ACLK, negedge WDATA[67], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[67]); + $setuphold (negedge ACLK, negedge WDATA[68], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[68]); + $setuphold (negedge ACLK, negedge WDATA[69], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[69]); + $setuphold (negedge ACLK, negedge WDATA[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[6]); + $setuphold (negedge ACLK, negedge WDATA[70], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[70]); + $setuphold (negedge ACLK, negedge WDATA[71], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[71]); + $setuphold (negedge ACLK, negedge WDATA[72], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[72]); + $setuphold (negedge ACLK, negedge WDATA[73], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[73]); + $setuphold (negedge ACLK, negedge WDATA[74], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[74]); + $setuphold (negedge ACLK, negedge WDATA[75], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[75]); + $setuphold (negedge ACLK, negedge WDATA[76], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[76]); + $setuphold (negedge ACLK, negedge WDATA[77], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[77]); + $setuphold (negedge ACLK, negedge WDATA[78], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[78]); + $setuphold (negedge ACLK, negedge WDATA[79], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[79]); + $setuphold (negedge ACLK, negedge WDATA[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[7]); + $setuphold (negedge ACLK, negedge WDATA[80], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[80]); + $setuphold (negedge ACLK, negedge WDATA[81], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[81]); + $setuphold (negedge ACLK, negedge WDATA[82], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[82]); + $setuphold (negedge ACLK, negedge WDATA[83], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[83]); + $setuphold (negedge ACLK, negedge WDATA[84], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[84]); + $setuphold (negedge ACLK, negedge WDATA[85], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[85]); + $setuphold (negedge ACLK, negedge WDATA[86], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[86]); + $setuphold (negedge ACLK, negedge WDATA[87], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[87]); + $setuphold (negedge ACLK, negedge WDATA[88], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[88]); + $setuphold (negedge ACLK, negedge WDATA[89], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[89]); + $setuphold (negedge ACLK, negedge WDATA[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[8]); + $setuphold (negedge ACLK, negedge WDATA[90], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[90]); + $setuphold (negedge ACLK, negedge WDATA[91], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[91]); + $setuphold (negedge ACLK, negedge WDATA[92], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[92]); + $setuphold (negedge ACLK, negedge WDATA[93], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[93]); + $setuphold (negedge ACLK, negedge WDATA[94], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[94]); + $setuphold (negedge ACLK, negedge WDATA[95], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[95]); + $setuphold (negedge ACLK, negedge WDATA[96], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[96]); + $setuphold (negedge ACLK, negedge WDATA[97], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[97]); + $setuphold (negedge ACLK, negedge WDATA[98], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[98]); + $setuphold (negedge ACLK, negedge WDATA[99], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[99]); + $setuphold (negedge ACLK, negedge WDATA[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[9]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[0]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[10]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[11]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[12]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[13]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[14]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[15]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[16]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[17]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[18]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[19]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[1]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[20]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[21]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[22]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[23]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[24]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[25]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[26]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[27]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[28]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[29]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[2]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[30]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[31]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[3]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[4]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[5]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[6]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[7]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[8]); + $setuphold (negedge ACLK, negedge WDATA_PARITY[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[9]); + $setuphold (negedge ACLK, negedge WLAST, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WLAST_delay); + $setuphold (negedge ACLK, negedge WSTRB[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[0]); + $setuphold (negedge ACLK, negedge WSTRB[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[10]); + $setuphold (negedge ACLK, negedge WSTRB[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[11]); + $setuphold (negedge ACLK, negedge WSTRB[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[12]); + $setuphold (negedge ACLK, negedge WSTRB[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[13]); + $setuphold (negedge ACLK, negedge WSTRB[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[14]); + $setuphold (negedge ACLK, negedge WSTRB[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[15]); + $setuphold (negedge ACLK, negedge WSTRB[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[16]); + $setuphold (negedge ACLK, negedge WSTRB[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[17]); + $setuphold (negedge ACLK, negedge WSTRB[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[18]); + $setuphold (negedge ACLK, negedge WSTRB[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[19]); + $setuphold (negedge ACLK, negedge WSTRB[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[1]); + $setuphold (negedge ACLK, negedge WSTRB[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[20]); + $setuphold (negedge ACLK, negedge WSTRB[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[21]); + $setuphold (negedge ACLK, negedge WSTRB[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[22]); + $setuphold (negedge ACLK, negedge WSTRB[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[23]); + $setuphold (negedge ACLK, negedge WSTRB[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[24]); + $setuphold (negedge ACLK, negedge WSTRB[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[25]); + $setuphold (negedge ACLK, negedge WSTRB[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[26]); + $setuphold (negedge ACLK, negedge WSTRB[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[27]); + $setuphold (negedge ACLK, negedge WSTRB[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[28]); + $setuphold (negedge ACLK, negedge WSTRB[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[29]); + $setuphold (negedge ACLK, negedge WSTRB[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[2]); + $setuphold (negedge ACLK, negedge WSTRB[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[30]); + $setuphold (negedge ACLK, negedge WSTRB[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[31]); + $setuphold (negedge ACLK, negedge WSTRB[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[3]); + $setuphold (negedge ACLK, negedge WSTRB[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[4]); + $setuphold (negedge ACLK, negedge WSTRB[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[5]); + $setuphold (negedge ACLK, negedge WSTRB[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[6]); + $setuphold (negedge ACLK, negedge WSTRB[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[7]); + $setuphold (negedge ACLK, negedge WSTRB[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[8]); + $setuphold (negedge ACLK, negedge WSTRB[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[9]); + $setuphold (negedge ACLK, negedge WVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WVALID_delay); + $setuphold (negedge ACLK, posedge ARADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[0]); + $setuphold (negedge ACLK, posedge ARADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[10]); + $setuphold (negedge ACLK, posedge ARADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[11]); + $setuphold (negedge ACLK, posedge ARADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[12]); + $setuphold (negedge ACLK, posedge ARADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[13]); + $setuphold (negedge ACLK, posedge ARADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[14]); + $setuphold (negedge ACLK, posedge ARADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[15]); + $setuphold (negedge ACLK, posedge ARADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[16]); + $setuphold (negedge ACLK, posedge ARADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[17]); + $setuphold (negedge ACLK, posedge ARADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[18]); + $setuphold (negedge ACLK, posedge ARADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[19]); + $setuphold (negedge ACLK, posedge ARADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[1]); + $setuphold (negedge ACLK, posedge ARADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[20]); + $setuphold (negedge ACLK, posedge ARADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[21]); + $setuphold (negedge ACLK, posedge ARADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[22]); + $setuphold (negedge ACLK, posedge ARADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[23]); + $setuphold (negedge ACLK, posedge ARADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[24]); + $setuphold (negedge ACLK, posedge ARADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[25]); + $setuphold (negedge ACLK, posedge ARADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[26]); + $setuphold (negedge ACLK, posedge ARADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[27]); + $setuphold (negedge ACLK, posedge ARADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[28]); + $setuphold (negedge ACLK, posedge ARADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[29]); + $setuphold (negedge ACLK, posedge ARADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[2]); + $setuphold (negedge ACLK, posedge ARADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[30]); + $setuphold (negedge ACLK, posedge ARADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[31]); + $setuphold (negedge ACLK, posedge ARADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[32]); + $setuphold (negedge ACLK, posedge ARADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[33]); + $setuphold (negedge ACLK, posedge ARADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[34]); + $setuphold (negedge ACLK, posedge ARADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[35]); + $setuphold (negedge ACLK, posedge ARADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[36]); + $setuphold (negedge ACLK, posedge ARADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[3]); + $setuphold (negedge ACLK, posedge ARADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[4]); + $setuphold (negedge ACLK, posedge ARADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[5]); + $setuphold (negedge ACLK, posedge ARADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[6]); + $setuphold (negedge ACLK, posedge ARADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[7]); + $setuphold (negedge ACLK, posedge ARADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[8]); + $setuphold (negedge ACLK, posedge ARADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[9]); + $setuphold (negedge ACLK, posedge ARBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[0]); + $setuphold (negedge ACLK, posedge ARBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[1]); + $setuphold (negedge ACLK, posedge ARID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[0]); + $setuphold (negedge ACLK, posedge ARID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[1]); + $setuphold (negedge ACLK, posedge ARID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[2]); + $setuphold (negedge ACLK, posedge ARID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[3]); + $setuphold (negedge ACLK, posedge ARID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[4]); + $setuphold (negedge ACLK, posedge ARID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[5]); + $setuphold (negedge ACLK, posedge ARLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[0]); + $setuphold (negedge ACLK, posedge ARLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[1]); + $setuphold (negedge ACLK, posedge ARLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[2]); + $setuphold (negedge ACLK, posedge ARLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[3]); + $setuphold (negedge ACLK, posedge ARSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[0]); + $setuphold (negedge ACLK, posedge ARSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[1]); + $setuphold (negedge ACLK, posedge ARSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[2]); + $setuphold (negedge ACLK, posedge ARVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARVALID_delay); + $setuphold (negedge ACLK, posedge AWADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[0]); + $setuphold (negedge ACLK, posedge AWADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[10]); + $setuphold (negedge ACLK, posedge AWADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[11]); + $setuphold (negedge ACLK, posedge AWADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[12]); + $setuphold (negedge ACLK, posedge AWADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[13]); + $setuphold (negedge ACLK, posedge AWADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[14]); + $setuphold (negedge ACLK, posedge AWADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[15]); + $setuphold (negedge ACLK, posedge AWADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[16]); + $setuphold (negedge ACLK, posedge AWADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[17]); + $setuphold (negedge ACLK, posedge AWADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[18]); + $setuphold (negedge ACLK, posedge AWADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[19]); + $setuphold (negedge ACLK, posedge AWADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[1]); + $setuphold (negedge ACLK, posedge AWADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[20]); + $setuphold (negedge ACLK, posedge AWADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[21]); + $setuphold (negedge ACLK, posedge AWADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[22]); + $setuphold (negedge ACLK, posedge AWADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[23]); + $setuphold (negedge ACLK, posedge AWADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[24]); + $setuphold (negedge ACLK, posedge AWADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[25]); + $setuphold (negedge ACLK, posedge AWADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[26]); + $setuphold (negedge ACLK, posedge AWADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[27]); + $setuphold (negedge ACLK, posedge AWADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[28]); + $setuphold (negedge ACLK, posedge AWADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[29]); + $setuphold (negedge ACLK, posedge AWADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[2]); + $setuphold (negedge ACLK, posedge AWADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[30]); + $setuphold (negedge ACLK, posedge AWADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[31]); + $setuphold (negedge ACLK, posedge AWADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[32]); + $setuphold (negedge ACLK, posedge AWADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[33]); + $setuphold (negedge ACLK, posedge AWADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[34]); + $setuphold (negedge ACLK, posedge AWADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[35]); + $setuphold (negedge ACLK, posedge AWADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[36]); + $setuphold (negedge ACLK, posedge AWADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[3]); + $setuphold (negedge ACLK, posedge AWADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[4]); + $setuphold (negedge ACLK, posedge AWADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[5]); + $setuphold (negedge ACLK, posedge AWADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[6]); + $setuphold (negedge ACLK, posedge AWADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[7]); + $setuphold (negedge ACLK, posedge AWADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[8]); + $setuphold (negedge ACLK, posedge AWADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[9]); + $setuphold (negedge ACLK, posedge AWBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[0]); + $setuphold (negedge ACLK, posedge AWBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[1]); + $setuphold (negedge ACLK, posedge AWID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[0]); + $setuphold (negedge ACLK, posedge AWID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[1]); + $setuphold (negedge ACLK, posedge AWID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[2]); + $setuphold (negedge ACLK, posedge AWID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[3]); + $setuphold (negedge ACLK, posedge AWID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[4]); + $setuphold (negedge ACLK, posedge AWID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[5]); + $setuphold (negedge ACLK, posedge AWLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[0]); + $setuphold (negedge ACLK, posedge AWLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[1]); + $setuphold (negedge ACLK, posedge AWLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[2]); + $setuphold (negedge ACLK, posedge AWLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[3]); + $setuphold (negedge ACLK, posedge AWSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[0]); + $setuphold (negedge ACLK, posedge AWSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[1]); + $setuphold (negedge ACLK, posedge AWSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[2]); + $setuphold (negedge ACLK, posedge AWVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWVALID_delay); + $setuphold (negedge ACLK, posedge BREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, BREADY_delay); + $setuphold (negedge ACLK, posedge DFI_LP_PWR_X_REQ, 0:0:0, 0:0:0, notifier, , , ACLK_delay, DFI_LP_PWR_X_REQ_delay); + $setuphold (negedge ACLK, posedge RREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, RREADY_delay); + $setuphold (negedge ACLK, posedge WDATA[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[0]); + $setuphold (negedge ACLK, posedge WDATA[100], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[100]); + $setuphold (negedge ACLK, posedge WDATA[101], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[101]); + $setuphold (negedge ACLK, posedge WDATA[102], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[102]); + $setuphold (negedge ACLK, posedge WDATA[103], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[103]); + $setuphold (negedge ACLK, posedge WDATA[104], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[104]); + $setuphold (negedge ACLK, posedge WDATA[105], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[105]); + $setuphold (negedge ACLK, posedge WDATA[106], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[106]); + $setuphold (negedge ACLK, posedge WDATA[107], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[107]); + $setuphold (negedge ACLK, posedge WDATA[108], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[108]); + $setuphold (negedge ACLK, posedge WDATA[109], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[109]); + $setuphold (negedge ACLK, posedge WDATA[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[10]); + $setuphold (negedge ACLK, posedge WDATA[110], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[110]); + $setuphold (negedge ACLK, posedge WDATA[111], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[111]); + $setuphold (negedge ACLK, posedge WDATA[112], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[112]); + $setuphold (negedge ACLK, posedge WDATA[113], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[113]); + $setuphold (negedge ACLK, posedge WDATA[114], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[114]); + $setuphold (negedge ACLK, posedge WDATA[115], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[115]); + $setuphold (negedge ACLK, posedge WDATA[116], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[116]); + $setuphold (negedge ACLK, posedge WDATA[117], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[117]); + $setuphold (negedge ACLK, posedge WDATA[118], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[118]); + $setuphold (negedge ACLK, posedge WDATA[119], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[119]); + $setuphold (negedge ACLK, posedge WDATA[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[11]); + $setuphold (negedge ACLK, posedge WDATA[120], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[120]); + $setuphold (negedge ACLK, posedge WDATA[121], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[121]); + $setuphold (negedge ACLK, posedge WDATA[122], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[122]); + $setuphold (negedge ACLK, posedge WDATA[123], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[123]); + $setuphold (negedge ACLK, posedge WDATA[124], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[124]); + $setuphold (negedge ACLK, posedge WDATA[125], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[125]); + $setuphold (negedge ACLK, posedge WDATA[126], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[126]); + $setuphold (negedge ACLK, posedge WDATA[127], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[127]); + $setuphold (negedge ACLK, posedge WDATA[128], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[128]); + $setuphold (negedge ACLK, posedge WDATA[129], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[129]); + $setuphold (negedge ACLK, posedge WDATA[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[12]); + $setuphold (negedge ACLK, posedge WDATA[130], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[130]); + $setuphold (negedge ACLK, posedge WDATA[131], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[131]); + $setuphold (negedge ACLK, posedge WDATA[132], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[132]); + $setuphold (negedge ACLK, posedge WDATA[133], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[133]); + $setuphold (negedge ACLK, posedge WDATA[134], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[134]); + $setuphold (negedge ACLK, posedge WDATA[135], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[135]); + $setuphold (negedge ACLK, posedge WDATA[136], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[136]); + $setuphold (negedge ACLK, posedge WDATA[137], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[137]); + $setuphold (negedge ACLK, posedge WDATA[138], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[138]); + $setuphold (negedge ACLK, posedge WDATA[139], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[139]); + $setuphold (negedge ACLK, posedge WDATA[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[13]); + $setuphold (negedge ACLK, posedge WDATA[140], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[140]); + $setuphold (negedge ACLK, posedge WDATA[141], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[141]); + $setuphold (negedge ACLK, posedge WDATA[142], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[142]); + $setuphold (negedge ACLK, posedge WDATA[143], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[143]); + $setuphold (negedge ACLK, posedge WDATA[144], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[144]); + $setuphold (negedge ACLK, posedge WDATA[145], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[145]); + $setuphold (negedge ACLK, posedge WDATA[146], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[146]); + $setuphold (negedge ACLK, posedge WDATA[147], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[147]); + $setuphold (negedge ACLK, posedge WDATA[148], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[148]); + $setuphold (negedge ACLK, posedge WDATA[149], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[149]); + $setuphold (negedge ACLK, posedge WDATA[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[14]); + $setuphold (negedge ACLK, posedge WDATA[150], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[150]); + $setuphold (negedge ACLK, posedge WDATA[151], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[151]); + $setuphold (negedge ACLK, posedge WDATA[152], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[152]); + $setuphold (negedge ACLK, posedge WDATA[153], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[153]); + $setuphold (negedge ACLK, posedge WDATA[154], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[154]); + $setuphold (negedge ACLK, posedge WDATA[155], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[155]); + $setuphold (negedge ACLK, posedge WDATA[156], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[156]); + $setuphold (negedge ACLK, posedge WDATA[157], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[157]); + $setuphold (negedge ACLK, posedge WDATA[158], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[158]); + $setuphold (negedge ACLK, posedge WDATA[159], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[159]); + $setuphold (negedge ACLK, posedge WDATA[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[15]); + $setuphold (negedge ACLK, posedge WDATA[160], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[160]); + $setuphold (negedge ACLK, posedge WDATA[161], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[161]); + $setuphold (negedge ACLK, posedge WDATA[162], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[162]); + $setuphold (negedge ACLK, posedge WDATA[163], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[163]); + $setuphold (negedge ACLK, posedge WDATA[164], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[164]); + $setuphold (negedge ACLK, posedge WDATA[165], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[165]); + $setuphold (negedge ACLK, posedge WDATA[166], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[166]); + $setuphold (negedge ACLK, posedge WDATA[167], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[167]); + $setuphold (negedge ACLK, posedge WDATA[168], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[168]); + $setuphold (negedge ACLK, posedge WDATA[169], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[169]); + $setuphold (negedge ACLK, posedge WDATA[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[16]); + $setuphold (negedge ACLK, posedge WDATA[170], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[170]); + $setuphold (negedge ACLK, posedge WDATA[171], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[171]); + $setuphold (negedge ACLK, posedge WDATA[172], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[172]); + $setuphold (negedge ACLK, posedge WDATA[173], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[173]); + $setuphold (negedge ACLK, posedge WDATA[174], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[174]); + $setuphold (negedge ACLK, posedge WDATA[175], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[175]); + $setuphold (negedge ACLK, posedge WDATA[176], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[176]); + $setuphold (negedge ACLK, posedge WDATA[177], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[177]); + $setuphold (negedge ACLK, posedge WDATA[178], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[178]); + $setuphold (negedge ACLK, posedge WDATA[179], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[179]); + $setuphold (negedge ACLK, posedge WDATA[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[17]); + $setuphold (negedge ACLK, posedge WDATA[180], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[180]); + $setuphold (negedge ACLK, posedge WDATA[181], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[181]); + $setuphold (negedge ACLK, posedge WDATA[182], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[182]); + $setuphold (negedge ACLK, posedge WDATA[183], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[183]); + $setuphold (negedge ACLK, posedge WDATA[184], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[184]); + $setuphold (negedge ACLK, posedge WDATA[185], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[185]); + $setuphold (negedge ACLK, posedge WDATA[186], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[186]); + $setuphold (negedge ACLK, posedge WDATA[187], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[187]); + $setuphold (negedge ACLK, posedge WDATA[188], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[188]); + $setuphold (negedge ACLK, posedge WDATA[189], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[189]); + $setuphold (negedge ACLK, posedge WDATA[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[18]); + $setuphold (negedge ACLK, posedge WDATA[190], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[190]); + $setuphold (negedge ACLK, posedge WDATA[191], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[191]); + $setuphold (negedge ACLK, posedge WDATA[192], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[192]); + $setuphold (negedge ACLK, posedge WDATA[193], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[193]); + $setuphold (negedge ACLK, posedge WDATA[194], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[194]); + $setuphold (negedge ACLK, posedge WDATA[195], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[195]); + $setuphold (negedge ACLK, posedge WDATA[196], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[196]); + $setuphold (negedge ACLK, posedge WDATA[197], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[197]); + $setuphold (negedge ACLK, posedge WDATA[198], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[198]); + $setuphold (negedge ACLK, posedge WDATA[199], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[199]); + $setuphold (negedge ACLK, posedge WDATA[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[19]); + $setuphold (negedge ACLK, posedge WDATA[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[1]); + $setuphold (negedge ACLK, posedge WDATA[200], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[200]); + $setuphold (negedge ACLK, posedge WDATA[201], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[201]); + $setuphold (negedge ACLK, posedge WDATA[202], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[202]); + $setuphold (negedge ACLK, posedge WDATA[203], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[203]); + $setuphold (negedge ACLK, posedge WDATA[204], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[204]); + $setuphold (negedge ACLK, posedge WDATA[205], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[205]); + $setuphold (negedge ACLK, posedge WDATA[206], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[206]); + $setuphold (negedge ACLK, posedge WDATA[207], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[207]); + $setuphold (negedge ACLK, posedge WDATA[208], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[208]); + $setuphold (negedge ACLK, posedge WDATA[209], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[209]); + $setuphold (negedge ACLK, posedge WDATA[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[20]); + $setuphold (negedge ACLK, posedge WDATA[210], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[210]); + $setuphold (negedge ACLK, posedge WDATA[211], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[211]); + $setuphold (negedge ACLK, posedge WDATA[212], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[212]); + $setuphold (negedge ACLK, posedge WDATA[213], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[213]); + $setuphold (negedge ACLK, posedge WDATA[214], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[214]); + $setuphold (negedge ACLK, posedge WDATA[215], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[215]); + $setuphold (negedge ACLK, posedge WDATA[216], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[216]); + $setuphold (negedge ACLK, posedge WDATA[217], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[217]); + $setuphold (negedge ACLK, posedge WDATA[218], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[218]); + $setuphold (negedge ACLK, posedge WDATA[219], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[219]); + $setuphold (negedge ACLK, posedge WDATA[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[21]); + $setuphold (negedge ACLK, posedge WDATA[220], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[220]); + $setuphold (negedge ACLK, posedge WDATA[221], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[221]); + $setuphold (negedge ACLK, posedge WDATA[222], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[222]); + $setuphold (negedge ACLK, posedge WDATA[223], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[223]); + $setuphold (negedge ACLK, posedge WDATA[224], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[224]); + $setuphold (negedge ACLK, posedge WDATA[225], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[225]); + $setuphold (negedge ACLK, posedge WDATA[226], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[226]); + $setuphold (negedge ACLK, posedge WDATA[227], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[227]); + $setuphold (negedge ACLK, posedge WDATA[228], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[228]); + $setuphold (negedge ACLK, posedge WDATA[229], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[229]); + $setuphold (negedge ACLK, posedge WDATA[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[22]); + $setuphold (negedge ACLK, posedge WDATA[230], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[230]); + $setuphold (negedge ACLK, posedge WDATA[231], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[231]); + $setuphold (negedge ACLK, posedge WDATA[232], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[232]); + $setuphold (negedge ACLK, posedge WDATA[233], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[233]); + $setuphold (negedge ACLK, posedge WDATA[234], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[234]); + $setuphold (negedge ACLK, posedge WDATA[235], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[235]); + $setuphold (negedge ACLK, posedge WDATA[236], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[236]); + $setuphold (negedge ACLK, posedge WDATA[237], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[237]); + $setuphold (negedge ACLK, posedge WDATA[238], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[238]); + $setuphold (negedge ACLK, posedge WDATA[239], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[239]); + $setuphold (negedge ACLK, posedge WDATA[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[23]); + $setuphold (negedge ACLK, posedge WDATA[240], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[240]); + $setuphold (negedge ACLK, posedge WDATA[241], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[241]); + $setuphold (negedge ACLK, posedge WDATA[242], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[242]); + $setuphold (negedge ACLK, posedge WDATA[243], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[243]); + $setuphold (negedge ACLK, posedge WDATA[244], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[244]); + $setuphold (negedge ACLK, posedge WDATA[245], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[245]); + $setuphold (negedge ACLK, posedge WDATA[246], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[246]); + $setuphold (negedge ACLK, posedge WDATA[247], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[247]); + $setuphold (negedge ACLK, posedge WDATA[248], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[248]); + $setuphold (negedge ACLK, posedge WDATA[249], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[249]); + $setuphold (negedge ACLK, posedge WDATA[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[24]); + $setuphold (negedge ACLK, posedge WDATA[250], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[250]); + $setuphold (negedge ACLK, posedge WDATA[251], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[251]); + $setuphold (negedge ACLK, posedge WDATA[252], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[252]); + $setuphold (negedge ACLK, posedge WDATA[253], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[253]); + $setuphold (negedge ACLK, posedge WDATA[254], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[254]); + $setuphold (negedge ACLK, posedge WDATA[255], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[255]); + $setuphold (negedge ACLK, posedge WDATA[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[25]); + $setuphold (negedge ACLK, posedge WDATA[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[26]); + $setuphold (negedge ACLK, posedge WDATA[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[27]); + $setuphold (negedge ACLK, posedge WDATA[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[28]); + $setuphold (negedge ACLK, posedge WDATA[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[29]); + $setuphold (negedge ACLK, posedge WDATA[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[2]); + $setuphold (negedge ACLK, posedge WDATA[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[30]); + $setuphold (negedge ACLK, posedge WDATA[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[31]); + $setuphold (negedge ACLK, posedge WDATA[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[32]); + $setuphold (negedge ACLK, posedge WDATA[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[33]); + $setuphold (negedge ACLK, posedge WDATA[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[34]); + $setuphold (negedge ACLK, posedge WDATA[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[35]); + $setuphold (negedge ACLK, posedge WDATA[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[36]); + $setuphold (negedge ACLK, posedge WDATA[37], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[37]); + $setuphold (negedge ACLK, posedge WDATA[38], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[38]); + $setuphold (negedge ACLK, posedge WDATA[39], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[39]); + $setuphold (negedge ACLK, posedge WDATA[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[3]); + $setuphold (negedge ACLK, posedge WDATA[40], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[40]); + $setuphold (negedge ACLK, posedge WDATA[41], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[41]); + $setuphold (negedge ACLK, posedge WDATA[42], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[42]); + $setuphold (negedge ACLK, posedge WDATA[43], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[43]); + $setuphold (negedge ACLK, posedge WDATA[44], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[44]); + $setuphold (negedge ACLK, posedge WDATA[45], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[45]); + $setuphold (negedge ACLK, posedge WDATA[46], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[46]); + $setuphold (negedge ACLK, posedge WDATA[47], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[47]); + $setuphold (negedge ACLK, posedge WDATA[48], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[48]); + $setuphold (negedge ACLK, posedge WDATA[49], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[49]); + $setuphold (negedge ACLK, posedge WDATA[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[4]); + $setuphold (negedge ACLK, posedge WDATA[50], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[50]); + $setuphold (negedge ACLK, posedge WDATA[51], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[51]); + $setuphold (negedge ACLK, posedge WDATA[52], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[52]); + $setuphold (negedge ACLK, posedge WDATA[53], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[53]); + $setuphold (negedge ACLK, posedge WDATA[54], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[54]); + $setuphold (negedge ACLK, posedge WDATA[55], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[55]); + $setuphold (negedge ACLK, posedge WDATA[56], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[56]); + $setuphold (negedge ACLK, posedge WDATA[57], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[57]); + $setuphold (negedge ACLK, posedge WDATA[58], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[58]); + $setuphold (negedge ACLK, posedge WDATA[59], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[59]); + $setuphold (negedge ACLK, posedge WDATA[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[5]); + $setuphold (negedge ACLK, posedge WDATA[60], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[60]); + $setuphold (negedge ACLK, posedge WDATA[61], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[61]); + $setuphold (negedge ACLK, posedge WDATA[62], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[62]); + $setuphold (negedge ACLK, posedge WDATA[63], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[63]); + $setuphold (negedge ACLK, posedge WDATA[64], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[64]); + $setuphold (negedge ACLK, posedge WDATA[65], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[65]); + $setuphold (negedge ACLK, posedge WDATA[66], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[66]); + $setuphold (negedge ACLK, posedge WDATA[67], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[67]); + $setuphold (negedge ACLK, posedge WDATA[68], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[68]); + $setuphold (negedge ACLK, posedge WDATA[69], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[69]); + $setuphold (negedge ACLK, posedge WDATA[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[6]); + $setuphold (negedge ACLK, posedge WDATA[70], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[70]); + $setuphold (negedge ACLK, posedge WDATA[71], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[71]); + $setuphold (negedge ACLK, posedge WDATA[72], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[72]); + $setuphold (negedge ACLK, posedge WDATA[73], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[73]); + $setuphold (negedge ACLK, posedge WDATA[74], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[74]); + $setuphold (negedge ACLK, posedge WDATA[75], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[75]); + $setuphold (negedge ACLK, posedge WDATA[76], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[76]); + $setuphold (negedge ACLK, posedge WDATA[77], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[77]); + $setuphold (negedge ACLK, posedge WDATA[78], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[78]); + $setuphold (negedge ACLK, posedge WDATA[79], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[79]); + $setuphold (negedge ACLK, posedge WDATA[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[7]); + $setuphold (negedge ACLK, posedge WDATA[80], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[80]); + $setuphold (negedge ACLK, posedge WDATA[81], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[81]); + $setuphold (negedge ACLK, posedge WDATA[82], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[82]); + $setuphold (negedge ACLK, posedge WDATA[83], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[83]); + $setuphold (negedge ACLK, posedge WDATA[84], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[84]); + $setuphold (negedge ACLK, posedge WDATA[85], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[85]); + $setuphold (negedge ACLK, posedge WDATA[86], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[86]); + $setuphold (negedge ACLK, posedge WDATA[87], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[87]); + $setuphold (negedge ACLK, posedge WDATA[88], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[88]); + $setuphold (negedge ACLK, posedge WDATA[89], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[89]); + $setuphold (negedge ACLK, posedge WDATA[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[8]); + $setuphold (negedge ACLK, posedge WDATA[90], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[90]); + $setuphold (negedge ACLK, posedge WDATA[91], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[91]); + $setuphold (negedge ACLK, posedge WDATA[92], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[92]); + $setuphold (negedge ACLK, posedge WDATA[93], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[93]); + $setuphold (negedge ACLK, posedge WDATA[94], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[94]); + $setuphold (negedge ACLK, posedge WDATA[95], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[95]); + $setuphold (negedge ACLK, posedge WDATA[96], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[96]); + $setuphold (negedge ACLK, posedge WDATA[97], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[97]); + $setuphold (negedge ACLK, posedge WDATA[98], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[98]); + $setuphold (negedge ACLK, posedge WDATA[99], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[99]); + $setuphold (negedge ACLK, posedge WDATA[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[9]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[0]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[10]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[11]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[12]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[13]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[14]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[15]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[16]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[17]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[18]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[19]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[1]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[20]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[21]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[22]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[23]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[24]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[25]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[26]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[27]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[28]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[29]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[2]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[30]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[31]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[3]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[4]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[5]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[6]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[7]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[8]); + $setuphold (negedge ACLK, posedge WDATA_PARITY[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[9]); + $setuphold (negedge ACLK, posedge WLAST, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WLAST_delay); + $setuphold (negedge ACLK, posedge WSTRB[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[0]); + $setuphold (negedge ACLK, posedge WSTRB[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[10]); + $setuphold (negedge ACLK, posedge WSTRB[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[11]); + $setuphold (negedge ACLK, posedge WSTRB[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[12]); + $setuphold (negedge ACLK, posedge WSTRB[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[13]); + $setuphold (negedge ACLK, posedge WSTRB[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[14]); + $setuphold (negedge ACLK, posedge WSTRB[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[15]); + $setuphold (negedge ACLK, posedge WSTRB[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[16]); + $setuphold (negedge ACLK, posedge WSTRB[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[17]); + $setuphold (negedge ACLK, posedge WSTRB[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[18]); + $setuphold (negedge ACLK, posedge WSTRB[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[19]); + $setuphold (negedge ACLK, posedge WSTRB[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[1]); + $setuphold (negedge ACLK, posedge WSTRB[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[20]); + $setuphold (negedge ACLK, posedge WSTRB[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[21]); + $setuphold (negedge ACLK, posedge WSTRB[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[22]); + $setuphold (negedge ACLK, posedge WSTRB[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[23]); + $setuphold (negedge ACLK, posedge WSTRB[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[24]); + $setuphold (negedge ACLK, posedge WSTRB[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[25]); + $setuphold (negedge ACLK, posedge WSTRB[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[26]); + $setuphold (negedge ACLK, posedge WSTRB[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[27]); + $setuphold (negedge ACLK, posedge WSTRB[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[28]); + $setuphold (negedge ACLK, posedge WSTRB[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[29]); + $setuphold (negedge ACLK, posedge WSTRB[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[2]); + $setuphold (negedge ACLK, posedge WSTRB[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[30]); + $setuphold (negedge ACLK, posedge WSTRB[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[31]); + $setuphold (negedge ACLK, posedge WSTRB[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[3]); + $setuphold (negedge ACLK, posedge WSTRB[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[4]); + $setuphold (negedge ACLK, posedge WSTRB[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[5]); + $setuphold (negedge ACLK, posedge WSTRB[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[6]); + $setuphold (negedge ACLK, posedge WSTRB[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[7]); + $setuphold (negedge ACLK, posedge WSTRB[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[8]); + $setuphold (negedge ACLK, posedge WSTRB[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[9]); + $setuphold (negedge ACLK, posedge WVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WVALID_delay); + $setuphold (posedge ACLK, negedge ARADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[0]); + $setuphold (posedge ACLK, negedge ARADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[10]); + $setuphold (posedge ACLK, negedge ARADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[11]); + $setuphold (posedge ACLK, negedge ARADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[12]); + $setuphold (posedge ACLK, negedge ARADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[13]); + $setuphold (posedge ACLK, negedge ARADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[14]); + $setuphold (posedge ACLK, negedge ARADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[15]); + $setuphold (posedge ACLK, negedge ARADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[16]); + $setuphold (posedge ACLK, negedge ARADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[17]); + $setuphold (posedge ACLK, negedge ARADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[18]); + $setuphold (posedge ACLK, negedge ARADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[19]); + $setuphold (posedge ACLK, negedge ARADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[1]); + $setuphold (posedge ACLK, negedge ARADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[20]); + $setuphold (posedge ACLK, negedge ARADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[21]); + $setuphold (posedge ACLK, negedge ARADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[22]); + $setuphold (posedge ACLK, negedge ARADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[23]); + $setuphold (posedge ACLK, negedge ARADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[24]); + $setuphold (posedge ACLK, negedge ARADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[25]); + $setuphold (posedge ACLK, negedge ARADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[26]); + $setuphold (posedge ACLK, negedge ARADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[27]); + $setuphold (posedge ACLK, negedge ARADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[28]); + $setuphold (posedge ACLK, negedge ARADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[29]); + $setuphold (posedge ACLK, negedge ARADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[2]); + $setuphold (posedge ACLK, negedge ARADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[30]); + $setuphold (posedge ACLK, negedge ARADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[31]); + $setuphold (posedge ACLK, negedge ARADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[32]); + $setuphold (posedge ACLK, negedge ARADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[33]); + $setuphold (posedge ACLK, negedge ARADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[34]); + $setuphold (posedge ACLK, negedge ARADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[35]); + $setuphold (posedge ACLK, negedge ARADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[36]); + $setuphold (posedge ACLK, negedge ARADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[3]); + $setuphold (posedge ACLK, negedge ARADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[4]); + $setuphold (posedge ACLK, negedge ARADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[5]); + $setuphold (posedge ACLK, negedge ARADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[6]); + $setuphold (posedge ACLK, negedge ARADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[7]); + $setuphold (posedge ACLK, negedge ARADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[8]); + $setuphold (posedge ACLK, negedge ARADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[9]); + $setuphold (posedge ACLK, negedge ARBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[0]); + $setuphold (posedge ACLK, negedge ARBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[1]); + $setuphold (posedge ACLK, negedge ARID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[0]); + $setuphold (posedge ACLK, negedge ARID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[1]); + $setuphold (posedge ACLK, negedge ARID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[2]); + $setuphold (posedge ACLK, negedge ARID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[3]); + $setuphold (posedge ACLK, negedge ARID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[4]); + $setuphold (posedge ACLK, negedge ARID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[5]); + $setuphold (posedge ACLK, negedge ARLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[0]); + $setuphold (posedge ACLK, negedge ARLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[1]); + $setuphold (posedge ACLK, negedge ARLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[2]); + $setuphold (posedge ACLK, negedge ARLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[3]); + $setuphold (posedge ACLK, negedge ARSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[0]); + $setuphold (posedge ACLK, negedge ARSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[1]); + $setuphold (posedge ACLK, negedge ARSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[2]); + $setuphold (posedge ACLK, negedge ARVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARVALID_delay); + $setuphold (posedge ACLK, negedge AWADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[0]); + $setuphold (posedge ACLK, negedge AWADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[10]); + $setuphold (posedge ACLK, negedge AWADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[11]); + $setuphold (posedge ACLK, negedge AWADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[12]); + $setuphold (posedge ACLK, negedge AWADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[13]); + $setuphold (posedge ACLK, negedge AWADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[14]); + $setuphold (posedge ACLK, negedge AWADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[15]); + $setuphold (posedge ACLK, negedge AWADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[16]); + $setuphold (posedge ACLK, negedge AWADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[17]); + $setuphold (posedge ACLK, negedge AWADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[18]); + $setuphold (posedge ACLK, negedge AWADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[19]); + $setuphold (posedge ACLK, negedge AWADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[1]); + $setuphold (posedge ACLK, negedge AWADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[20]); + $setuphold (posedge ACLK, negedge AWADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[21]); + $setuphold (posedge ACLK, negedge AWADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[22]); + $setuphold (posedge ACLK, negedge AWADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[23]); + $setuphold (posedge ACLK, negedge AWADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[24]); + $setuphold (posedge ACLK, negedge AWADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[25]); + $setuphold (posedge ACLK, negedge AWADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[26]); + $setuphold (posedge ACLK, negedge AWADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[27]); + $setuphold (posedge ACLK, negedge AWADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[28]); + $setuphold (posedge ACLK, negedge AWADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[29]); + $setuphold (posedge ACLK, negedge AWADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[2]); + $setuphold (posedge ACLK, negedge AWADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[30]); + $setuphold (posedge ACLK, negedge AWADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[31]); + $setuphold (posedge ACLK, negedge AWADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[32]); + $setuphold (posedge ACLK, negedge AWADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[33]); + $setuphold (posedge ACLK, negedge AWADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[34]); + $setuphold (posedge ACLK, negedge AWADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[35]); + $setuphold (posedge ACLK, negedge AWADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[36]); + $setuphold (posedge ACLK, negedge AWADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[3]); + $setuphold (posedge ACLK, negedge AWADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[4]); + $setuphold (posedge ACLK, negedge AWADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[5]); + $setuphold (posedge ACLK, negedge AWADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[6]); + $setuphold (posedge ACLK, negedge AWADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[7]); + $setuphold (posedge ACLK, negedge AWADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[8]); + $setuphold (posedge ACLK, negedge AWADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[9]); + $setuphold (posedge ACLK, negedge AWBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[0]); + $setuphold (posedge ACLK, negedge AWBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[1]); + $setuphold (posedge ACLK, negedge AWID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[0]); + $setuphold (posedge ACLK, negedge AWID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[1]); + $setuphold (posedge ACLK, negedge AWID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[2]); + $setuphold (posedge ACLK, negedge AWID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[3]); + $setuphold (posedge ACLK, negedge AWID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[4]); + $setuphold (posedge ACLK, negedge AWID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[5]); + $setuphold (posedge ACLK, negedge AWLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[0]); + $setuphold (posedge ACLK, negedge AWLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[1]); + $setuphold (posedge ACLK, negedge AWLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[2]); + $setuphold (posedge ACLK, negedge AWLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[3]); + $setuphold (posedge ACLK, negedge AWSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[0]); + $setuphold (posedge ACLK, negedge AWSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[1]); + $setuphold (posedge ACLK, negedge AWSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[2]); + $setuphold (posedge ACLK, negedge AWVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWVALID_delay); + $setuphold (posedge ACLK, negedge BREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, BREADY_delay); + $setuphold (posedge ACLK, negedge DFI_LP_PWR_X_REQ, 0:0:0, 0:0:0, notifier, , , ACLK_delay, DFI_LP_PWR_X_REQ_delay); + $setuphold (posedge ACLK, negedge RREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, RREADY_delay); + $setuphold (posedge ACLK, negedge WDATA[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[0]); + $setuphold (posedge ACLK, negedge WDATA[100], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[100]); + $setuphold (posedge ACLK, negedge WDATA[101], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[101]); + $setuphold (posedge ACLK, negedge WDATA[102], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[102]); + $setuphold (posedge ACLK, negedge WDATA[103], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[103]); + $setuphold (posedge ACLK, negedge WDATA[104], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[104]); + $setuphold (posedge ACLK, negedge WDATA[105], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[105]); + $setuphold (posedge ACLK, negedge WDATA[106], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[106]); + $setuphold (posedge ACLK, negedge WDATA[107], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[107]); + $setuphold (posedge ACLK, negedge WDATA[108], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[108]); + $setuphold (posedge ACLK, negedge WDATA[109], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[109]); + $setuphold (posedge ACLK, negedge WDATA[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[10]); + $setuphold (posedge ACLK, negedge WDATA[110], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[110]); + $setuphold (posedge ACLK, negedge WDATA[111], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[111]); + $setuphold (posedge ACLK, negedge WDATA[112], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[112]); + $setuphold (posedge ACLK, negedge WDATA[113], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[113]); + $setuphold (posedge ACLK, negedge WDATA[114], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[114]); + $setuphold (posedge ACLK, negedge WDATA[115], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[115]); + $setuphold (posedge ACLK, negedge WDATA[116], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[116]); + $setuphold (posedge ACLK, negedge WDATA[117], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[117]); + $setuphold (posedge ACLK, negedge WDATA[118], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[118]); + $setuphold (posedge ACLK, negedge WDATA[119], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[119]); + $setuphold (posedge ACLK, negedge WDATA[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[11]); + $setuphold (posedge ACLK, negedge WDATA[120], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[120]); + $setuphold (posedge ACLK, negedge WDATA[121], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[121]); + $setuphold (posedge ACLK, negedge WDATA[122], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[122]); + $setuphold (posedge ACLK, negedge WDATA[123], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[123]); + $setuphold (posedge ACLK, negedge WDATA[124], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[124]); + $setuphold (posedge ACLK, negedge WDATA[125], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[125]); + $setuphold (posedge ACLK, negedge WDATA[126], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[126]); + $setuphold (posedge ACLK, negedge WDATA[127], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[127]); + $setuphold (posedge ACLK, negedge WDATA[128], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[128]); + $setuphold (posedge ACLK, negedge WDATA[129], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[129]); + $setuphold (posedge ACLK, negedge WDATA[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[12]); + $setuphold (posedge ACLK, negedge WDATA[130], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[130]); + $setuphold (posedge ACLK, negedge WDATA[131], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[131]); + $setuphold (posedge ACLK, negedge WDATA[132], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[132]); + $setuphold (posedge ACLK, negedge WDATA[133], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[133]); + $setuphold (posedge ACLK, negedge WDATA[134], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[134]); + $setuphold (posedge ACLK, negedge WDATA[135], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[135]); + $setuphold (posedge ACLK, negedge WDATA[136], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[136]); + $setuphold (posedge ACLK, negedge WDATA[137], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[137]); + $setuphold (posedge ACLK, negedge WDATA[138], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[138]); + $setuphold (posedge ACLK, negedge WDATA[139], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[139]); + $setuphold (posedge ACLK, negedge WDATA[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[13]); + $setuphold (posedge ACLK, negedge WDATA[140], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[140]); + $setuphold (posedge ACLK, negedge WDATA[141], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[141]); + $setuphold (posedge ACLK, negedge WDATA[142], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[142]); + $setuphold (posedge ACLK, negedge WDATA[143], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[143]); + $setuphold (posedge ACLK, negedge WDATA[144], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[144]); + $setuphold (posedge ACLK, negedge WDATA[145], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[145]); + $setuphold (posedge ACLK, negedge WDATA[146], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[146]); + $setuphold (posedge ACLK, negedge WDATA[147], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[147]); + $setuphold (posedge ACLK, negedge WDATA[148], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[148]); + $setuphold (posedge ACLK, negedge WDATA[149], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[149]); + $setuphold (posedge ACLK, negedge WDATA[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[14]); + $setuphold (posedge ACLK, negedge WDATA[150], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[150]); + $setuphold (posedge ACLK, negedge WDATA[151], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[151]); + $setuphold (posedge ACLK, negedge WDATA[152], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[152]); + $setuphold (posedge ACLK, negedge WDATA[153], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[153]); + $setuphold (posedge ACLK, negedge WDATA[154], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[154]); + $setuphold (posedge ACLK, negedge WDATA[155], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[155]); + $setuphold (posedge ACLK, negedge WDATA[156], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[156]); + $setuphold (posedge ACLK, negedge WDATA[157], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[157]); + $setuphold (posedge ACLK, negedge WDATA[158], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[158]); + $setuphold (posedge ACLK, negedge WDATA[159], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[159]); + $setuphold (posedge ACLK, negedge WDATA[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[15]); + $setuphold (posedge ACLK, negedge WDATA[160], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[160]); + $setuphold (posedge ACLK, negedge WDATA[161], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[161]); + $setuphold (posedge ACLK, negedge WDATA[162], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[162]); + $setuphold (posedge ACLK, negedge WDATA[163], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[163]); + $setuphold (posedge ACLK, negedge WDATA[164], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[164]); + $setuphold (posedge ACLK, negedge WDATA[165], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[165]); + $setuphold (posedge ACLK, negedge WDATA[166], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[166]); + $setuphold (posedge ACLK, negedge WDATA[167], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[167]); + $setuphold (posedge ACLK, negedge WDATA[168], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[168]); + $setuphold (posedge ACLK, negedge WDATA[169], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[169]); + $setuphold (posedge ACLK, negedge WDATA[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[16]); + $setuphold (posedge ACLK, negedge WDATA[170], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[170]); + $setuphold (posedge ACLK, negedge WDATA[171], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[171]); + $setuphold (posedge ACLK, negedge WDATA[172], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[172]); + $setuphold (posedge ACLK, negedge WDATA[173], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[173]); + $setuphold (posedge ACLK, negedge WDATA[174], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[174]); + $setuphold (posedge ACLK, negedge WDATA[175], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[175]); + $setuphold (posedge ACLK, negedge WDATA[176], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[176]); + $setuphold (posedge ACLK, negedge WDATA[177], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[177]); + $setuphold (posedge ACLK, negedge WDATA[178], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[178]); + $setuphold (posedge ACLK, negedge WDATA[179], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[179]); + $setuphold (posedge ACLK, negedge WDATA[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[17]); + $setuphold (posedge ACLK, negedge WDATA[180], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[180]); + $setuphold (posedge ACLK, negedge WDATA[181], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[181]); + $setuphold (posedge ACLK, negedge WDATA[182], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[182]); + $setuphold (posedge ACLK, negedge WDATA[183], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[183]); + $setuphold (posedge ACLK, negedge WDATA[184], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[184]); + $setuphold (posedge ACLK, negedge WDATA[185], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[185]); + $setuphold (posedge ACLK, negedge WDATA[186], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[186]); + $setuphold (posedge ACLK, negedge WDATA[187], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[187]); + $setuphold (posedge ACLK, negedge WDATA[188], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[188]); + $setuphold (posedge ACLK, negedge WDATA[189], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[189]); + $setuphold (posedge ACLK, negedge WDATA[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[18]); + $setuphold (posedge ACLK, negedge WDATA[190], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[190]); + $setuphold (posedge ACLK, negedge WDATA[191], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[191]); + $setuphold (posedge ACLK, negedge WDATA[192], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[192]); + $setuphold (posedge ACLK, negedge WDATA[193], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[193]); + $setuphold (posedge ACLK, negedge WDATA[194], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[194]); + $setuphold (posedge ACLK, negedge WDATA[195], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[195]); + $setuphold (posedge ACLK, negedge WDATA[196], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[196]); + $setuphold (posedge ACLK, negedge WDATA[197], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[197]); + $setuphold (posedge ACLK, negedge WDATA[198], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[198]); + $setuphold (posedge ACLK, negedge WDATA[199], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[199]); + $setuphold (posedge ACLK, negedge WDATA[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[19]); + $setuphold (posedge ACLK, negedge WDATA[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[1]); + $setuphold (posedge ACLK, negedge WDATA[200], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[200]); + $setuphold (posedge ACLK, negedge WDATA[201], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[201]); + $setuphold (posedge ACLK, negedge WDATA[202], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[202]); + $setuphold (posedge ACLK, negedge WDATA[203], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[203]); + $setuphold (posedge ACLK, negedge WDATA[204], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[204]); + $setuphold (posedge ACLK, negedge WDATA[205], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[205]); + $setuphold (posedge ACLK, negedge WDATA[206], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[206]); + $setuphold (posedge ACLK, negedge WDATA[207], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[207]); + $setuphold (posedge ACLK, negedge WDATA[208], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[208]); + $setuphold (posedge ACLK, negedge WDATA[209], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[209]); + $setuphold (posedge ACLK, negedge WDATA[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[20]); + $setuphold (posedge ACLK, negedge WDATA[210], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[210]); + $setuphold (posedge ACLK, negedge WDATA[211], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[211]); + $setuphold (posedge ACLK, negedge WDATA[212], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[212]); + $setuphold (posedge ACLK, negedge WDATA[213], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[213]); + $setuphold (posedge ACLK, negedge WDATA[214], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[214]); + $setuphold (posedge ACLK, negedge WDATA[215], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[215]); + $setuphold (posedge ACLK, negedge WDATA[216], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[216]); + $setuphold (posedge ACLK, negedge WDATA[217], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[217]); + $setuphold (posedge ACLK, negedge WDATA[218], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[218]); + $setuphold (posedge ACLK, negedge WDATA[219], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[219]); + $setuphold (posedge ACLK, negedge WDATA[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[21]); + $setuphold (posedge ACLK, negedge WDATA[220], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[220]); + $setuphold (posedge ACLK, negedge WDATA[221], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[221]); + $setuphold (posedge ACLK, negedge WDATA[222], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[222]); + $setuphold (posedge ACLK, negedge WDATA[223], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[223]); + $setuphold (posedge ACLK, negedge WDATA[224], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[224]); + $setuphold (posedge ACLK, negedge WDATA[225], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[225]); + $setuphold (posedge ACLK, negedge WDATA[226], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[226]); + $setuphold (posedge ACLK, negedge WDATA[227], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[227]); + $setuphold (posedge ACLK, negedge WDATA[228], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[228]); + $setuphold (posedge ACLK, negedge WDATA[229], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[229]); + $setuphold (posedge ACLK, negedge WDATA[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[22]); + $setuphold (posedge ACLK, negedge WDATA[230], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[230]); + $setuphold (posedge ACLK, negedge WDATA[231], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[231]); + $setuphold (posedge ACLK, negedge WDATA[232], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[232]); + $setuphold (posedge ACLK, negedge WDATA[233], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[233]); + $setuphold (posedge ACLK, negedge WDATA[234], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[234]); + $setuphold (posedge ACLK, negedge WDATA[235], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[235]); + $setuphold (posedge ACLK, negedge WDATA[236], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[236]); + $setuphold (posedge ACLK, negedge WDATA[237], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[237]); + $setuphold (posedge ACLK, negedge WDATA[238], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[238]); + $setuphold (posedge ACLK, negedge WDATA[239], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[239]); + $setuphold (posedge ACLK, negedge WDATA[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[23]); + $setuphold (posedge ACLK, negedge WDATA[240], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[240]); + $setuphold (posedge ACLK, negedge WDATA[241], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[241]); + $setuphold (posedge ACLK, negedge WDATA[242], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[242]); + $setuphold (posedge ACLK, negedge WDATA[243], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[243]); + $setuphold (posedge ACLK, negedge WDATA[244], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[244]); + $setuphold (posedge ACLK, negedge WDATA[245], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[245]); + $setuphold (posedge ACLK, negedge WDATA[246], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[246]); + $setuphold (posedge ACLK, negedge WDATA[247], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[247]); + $setuphold (posedge ACLK, negedge WDATA[248], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[248]); + $setuphold (posedge ACLK, negedge WDATA[249], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[249]); + $setuphold (posedge ACLK, negedge WDATA[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[24]); + $setuphold (posedge ACLK, negedge WDATA[250], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[250]); + $setuphold (posedge ACLK, negedge WDATA[251], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[251]); + $setuphold (posedge ACLK, negedge WDATA[252], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[252]); + $setuphold (posedge ACLK, negedge WDATA[253], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[253]); + $setuphold (posedge ACLK, negedge WDATA[254], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[254]); + $setuphold (posedge ACLK, negedge WDATA[255], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[255]); + $setuphold (posedge ACLK, negedge WDATA[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[25]); + $setuphold (posedge ACLK, negedge WDATA[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[26]); + $setuphold (posedge ACLK, negedge WDATA[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[27]); + $setuphold (posedge ACLK, negedge WDATA[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[28]); + $setuphold (posedge ACLK, negedge WDATA[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[29]); + $setuphold (posedge ACLK, negedge WDATA[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[2]); + $setuphold (posedge ACLK, negedge WDATA[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[30]); + $setuphold (posedge ACLK, negedge WDATA[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[31]); + $setuphold (posedge ACLK, negedge WDATA[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[32]); + $setuphold (posedge ACLK, negedge WDATA[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[33]); + $setuphold (posedge ACLK, negedge WDATA[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[34]); + $setuphold (posedge ACLK, negedge WDATA[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[35]); + $setuphold (posedge ACLK, negedge WDATA[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[36]); + $setuphold (posedge ACLK, negedge WDATA[37], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[37]); + $setuphold (posedge ACLK, negedge WDATA[38], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[38]); + $setuphold (posedge ACLK, negedge WDATA[39], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[39]); + $setuphold (posedge ACLK, negedge WDATA[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[3]); + $setuphold (posedge ACLK, negedge WDATA[40], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[40]); + $setuphold (posedge ACLK, negedge WDATA[41], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[41]); + $setuphold (posedge ACLK, negedge WDATA[42], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[42]); + $setuphold (posedge ACLK, negedge WDATA[43], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[43]); + $setuphold (posedge ACLK, negedge WDATA[44], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[44]); + $setuphold (posedge ACLK, negedge WDATA[45], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[45]); + $setuphold (posedge ACLK, negedge WDATA[46], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[46]); + $setuphold (posedge ACLK, negedge WDATA[47], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[47]); + $setuphold (posedge ACLK, negedge WDATA[48], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[48]); + $setuphold (posedge ACLK, negedge WDATA[49], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[49]); + $setuphold (posedge ACLK, negedge WDATA[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[4]); + $setuphold (posedge ACLK, negedge WDATA[50], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[50]); + $setuphold (posedge ACLK, negedge WDATA[51], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[51]); + $setuphold (posedge ACLK, negedge WDATA[52], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[52]); + $setuphold (posedge ACLK, negedge WDATA[53], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[53]); + $setuphold (posedge ACLK, negedge WDATA[54], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[54]); + $setuphold (posedge ACLK, negedge WDATA[55], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[55]); + $setuphold (posedge ACLK, negedge WDATA[56], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[56]); + $setuphold (posedge ACLK, negedge WDATA[57], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[57]); + $setuphold (posedge ACLK, negedge WDATA[58], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[58]); + $setuphold (posedge ACLK, negedge WDATA[59], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[59]); + $setuphold (posedge ACLK, negedge WDATA[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[5]); + $setuphold (posedge ACLK, negedge WDATA[60], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[60]); + $setuphold (posedge ACLK, negedge WDATA[61], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[61]); + $setuphold (posedge ACLK, negedge WDATA[62], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[62]); + $setuphold (posedge ACLK, negedge WDATA[63], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[63]); + $setuphold (posedge ACLK, negedge WDATA[64], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[64]); + $setuphold (posedge ACLK, negedge WDATA[65], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[65]); + $setuphold (posedge ACLK, negedge WDATA[66], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[66]); + $setuphold (posedge ACLK, negedge WDATA[67], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[67]); + $setuphold (posedge ACLK, negedge WDATA[68], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[68]); + $setuphold (posedge ACLK, negedge WDATA[69], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[69]); + $setuphold (posedge ACLK, negedge WDATA[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[6]); + $setuphold (posedge ACLK, negedge WDATA[70], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[70]); + $setuphold (posedge ACLK, negedge WDATA[71], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[71]); + $setuphold (posedge ACLK, negedge WDATA[72], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[72]); + $setuphold (posedge ACLK, negedge WDATA[73], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[73]); + $setuphold (posedge ACLK, negedge WDATA[74], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[74]); + $setuphold (posedge ACLK, negedge WDATA[75], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[75]); + $setuphold (posedge ACLK, negedge WDATA[76], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[76]); + $setuphold (posedge ACLK, negedge WDATA[77], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[77]); + $setuphold (posedge ACLK, negedge WDATA[78], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[78]); + $setuphold (posedge ACLK, negedge WDATA[79], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[79]); + $setuphold (posedge ACLK, negedge WDATA[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[7]); + $setuphold (posedge ACLK, negedge WDATA[80], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[80]); + $setuphold (posedge ACLK, negedge WDATA[81], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[81]); + $setuphold (posedge ACLK, negedge WDATA[82], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[82]); + $setuphold (posedge ACLK, negedge WDATA[83], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[83]); + $setuphold (posedge ACLK, negedge WDATA[84], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[84]); + $setuphold (posedge ACLK, negedge WDATA[85], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[85]); + $setuphold (posedge ACLK, negedge WDATA[86], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[86]); + $setuphold (posedge ACLK, negedge WDATA[87], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[87]); + $setuphold (posedge ACLK, negedge WDATA[88], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[88]); + $setuphold (posedge ACLK, negedge WDATA[89], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[89]); + $setuphold (posedge ACLK, negedge WDATA[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[8]); + $setuphold (posedge ACLK, negedge WDATA[90], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[90]); + $setuphold (posedge ACLK, negedge WDATA[91], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[91]); + $setuphold (posedge ACLK, negedge WDATA[92], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[92]); + $setuphold (posedge ACLK, negedge WDATA[93], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[93]); + $setuphold (posedge ACLK, negedge WDATA[94], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[94]); + $setuphold (posedge ACLK, negedge WDATA[95], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[95]); + $setuphold (posedge ACLK, negedge WDATA[96], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[96]); + $setuphold (posedge ACLK, negedge WDATA[97], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[97]); + $setuphold (posedge ACLK, negedge WDATA[98], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[98]); + $setuphold (posedge ACLK, negedge WDATA[99], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[99]); + $setuphold (posedge ACLK, negedge WDATA[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[9]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[0]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[10]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[11]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[12]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[13]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[14]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[15]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[16]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[17]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[18]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[19]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[1]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[20]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[21]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[22]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[23]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[24]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[25]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[26]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[27]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[28]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[29]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[2]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[30]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[31]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[3]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[4]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[5]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[6]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[7]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[8]); + $setuphold (posedge ACLK, negedge WDATA_PARITY[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[9]); + $setuphold (posedge ACLK, negedge WLAST, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WLAST_delay); + $setuphold (posedge ACLK, negedge WSTRB[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[0]); + $setuphold (posedge ACLK, negedge WSTRB[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[10]); + $setuphold (posedge ACLK, negedge WSTRB[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[11]); + $setuphold (posedge ACLK, negedge WSTRB[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[12]); + $setuphold (posedge ACLK, negedge WSTRB[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[13]); + $setuphold (posedge ACLK, negedge WSTRB[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[14]); + $setuphold (posedge ACLK, negedge WSTRB[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[15]); + $setuphold (posedge ACLK, negedge WSTRB[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[16]); + $setuphold (posedge ACLK, negedge WSTRB[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[17]); + $setuphold (posedge ACLK, negedge WSTRB[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[18]); + $setuphold (posedge ACLK, negedge WSTRB[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[19]); + $setuphold (posedge ACLK, negedge WSTRB[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[1]); + $setuphold (posedge ACLK, negedge WSTRB[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[20]); + $setuphold (posedge ACLK, negedge WSTRB[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[21]); + $setuphold (posedge ACLK, negedge WSTRB[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[22]); + $setuphold (posedge ACLK, negedge WSTRB[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[23]); + $setuphold (posedge ACLK, negedge WSTRB[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[24]); + $setuphold (posedge ACLK, negedge WSTRB[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[25]); + $setuphold (posedge ACLK, negedge WSTRB[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[26]); + $setuphold (posedge ACLK, negedge WSTRB[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[27]); + $setuphold (posedge ACLK, negedge WSTRB[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[28]); + $setuphold (posedge ACLK, negedge WSTRB[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[29]); + $setuphold (posedge ACLK, negedge WSTRB[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[2]); + $setuphold (posedge ACLK, negedge WSTRB[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[30]); + $setuphold (posedge ACLK, negedge WSTRB[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[31]); + $setuphold (posedge ACLK, negedge WSTRB[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[3]); + $setuphold (posedge ACLK, negedge WSTRB[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[4]); + $setuphold (posedge ACLK, negedge WSTRB[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[5]); + $setuphold (posedge ACLK, negedge WSTRB[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[6]); + $setuphold (posedge ACLK, negedge WSTRB[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[7]); + $setuphold (posedge ACLK, negedge WSTRB[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[8]); + $setuphold (posedge ACLK, negedge WSTRB[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[9]); + $setuphold (posedge ACLK, negedge WVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WVALID_delay); + $setuphold (posedge ACLK, posedge ARADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[0]); + $setuphold (posedge ACLK, posedge ARADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[10]); + $setuphold (posedge ACLK, posedge ARADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[11]); + $setuphold (posedge ACLK, posedge ARADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[12]); + $setuphold (posedge ACLK, posedge ARADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[13]); + $setuphold (posedge ACLK, posedge ARADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[14]); + $setuphold (posedge ACLK, posedge ARADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[15]); + $setuphold (posedge ACLK, posedge ARADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[16]); + $setuphold (posedge ACLK, posedge ARADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[17]); + $setuphold (posedge ACLK, posedge ARADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[18]); + $setuphold (posedge ACLK, posedge ARADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[19]); + $setuphold (posedge ACLK, posedge ARADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[1]); + $setuphold (posedge ACLK, posedge ARADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[20]); + $setuphold (posedge ACLK, posedge ARADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[21]); + $setuphold (posedge ACLK, posedge ARADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[22]); + $setuphold (posedge ACLK, posedge ARADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[23]); + $setuphold (posedge ACLK, posedge ARADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[24]); + $setuphold (posedge ACLK, posedge ARADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[25]); + $setuphold (posedge ACLK, posedge ARADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[26]); + $setuphold (posedge ACLK, posedge ARADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[27]); + $setuphold (posedge ACLK, posedge ARADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[28]); + $setuphold (posedge ACLK, posedge ARADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[29]); + $setuphold (posedge ACLK, posedge ARADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[2]); + $setuphold (posedge ACLK, posedge ARADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[30]); + $setuphold (posedge ACLK, posedge ARADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[31]); + $setuphold (posedge ACLK, posedge ARADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[32]); + $setuphold (posedge ACLK, posedge ARADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[33]); + $setuphold (posedge ACLK, posedge ARADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[34]); + $setuphold (posedge ACLK, posedge ARADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[35]); + $setuphold (posedge ACLK, posedge ARADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[36]); + $setuphold (posedge ACLK, posedge ARADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[3]); + $setuphold (posedge ACLK, posedge ARADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[4]); + $setuphold (posedge ACLK, posedge ARADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[5]); + $setuphold (posedge ACLK, posedge ARADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[6]); + $setuphold (posedge ACLK, posedge ARADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[7]); + $setuphold (posedge ACLK, posedge ARADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[8]); + $setuphold (posedge ACLK, posedge ARADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARADDR_delay[9]); + $setuphold (posedge ACLK, posedge ARBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[0]); + $setuphold (posedge ACLK, posedge ARBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARBURST_delay[1]); + $setuphold (posedge ACLK, posedge ARID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[0]); + $setuphold (posedge ACLK, posedge ARID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[1]); + $setuphold (posedge ACLK, posedge ARID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[2]); + $setuphold (posedge ACLK, posedge ARID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[3]); + $setuphold (posedge ACLK, posedge ARID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[4]); + $setuphold (posedge ACLK, posedge ARID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARID_delay[5]); + $setuphold (posedge ACLK, posedge ARLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[0]); + $setuphold (posedge ACLK, posedge ARLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[1]); + $setuphold (posedge ACLK, posedge ARLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[2]); + $setuphold (posedge ACLK, posedge ARLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARLEN_delay[3]); + $setuphold (posedge ACLK, posedge ARSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[0]); + $setuphold (posedge ACLK, posedge ARSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[1]); + $setuphold (posedge ACLK, posedge ARSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARSIZE_delay[2]); + $setuphold (posedge ACLK, posedge ARVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, ARVALID_delay); + $setuphold (posedge ACLK, posedge AWADDR[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[0]); + $setuphold (posedge ACLK, posedge AWADDR[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[10]); + $setuphold (posedge ACLK, posedge AWADDR[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[11]); + $setuphold (posedge ACLK, posedge AWADDR[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[12]); + $setuphold (posedge ACLK, posedge AWADDR[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[13]); + $setuphold (posedge ACLK, posedge AWADDR[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[14]); + $setuphold (posedge ACLK, posedge AWADDR[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[15]); + $setuphold (posedge ACLK, posedge AWADDR[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[16]); + $setuphold (posedge ACLK, posedge AWADDR[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[17]); + $setuphold (posedge ACLK, posedge AWADDR[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[18]); + $setuphold (posedge ACLK, posedge AWADDR[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[19]); + $setuphold (posedge ACLK, posedge AWADDR[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[1]); + $setuphold (posedge ACLK, posedge AWADDR[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[20]); + $setuphold (posedge ACLK, posedge AWADDR[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[21]); + $setuphold (posedge ACLK, posedge AWADDR[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[22]); + $setuphold (posedge ACLK, posedge AWADDR[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[23]); + $setuphold (posedge ACLK, posedge AWADDR[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[24]); + $setuphold (posedge ACLK, posedge AWADDR[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[25]); + $setuphold (posedge ACLK, posedge AWADDR[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[26]); + $setuphold (posedge ACLK, posedge AWADDR[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[27]); + $setuphold (posedge ACLK, posedge AWADDR[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[28]); + $setuphold (posedge ACLK, posedge AWADDR[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[29]); + $setuphold (posedge ACLK, posedge AWADDR[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[2]); + $setuphold (posedge ACLK, posedge AWADDR[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[30]); + $setuphold (posedge ACLK, posedge AWADDR[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[31]); + $setuphold (posedge ACLK, posedge AWADDR[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[32]); + $setuphold (posedge ACLK, posedge AWADDR[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[33]); + $setuphold (posedge ACLK, posedge AWADDR[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[34]); + $setuphold (posedge ACLK, posedge AWADDR[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[35]); + $setuphold (posedge ACLK, posedge AWADDR[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[36]); + $setuphold (posedge ACLK, posedge AWADDR[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[3]); + $setuphold (posedge ACLK, posedge AWADDR[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[4]); + $setuphold (posedge ACLK, posedge AWADDR[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[5]); + $setuphold (posedge ACLK, posedge AWADDR[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[6]); + $setuphold (posedge ACLK, posedge AWADDR[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[7]); + $setuphold (posedge ACLK, posedge AWADDR[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[8]); + $setuphold (posedge ACLK, posedge AWADDR[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWADDR_delay[9]); + $setuphold (posedge ACLK, posedge AWBURST[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[0]); + $setuphold (posedge ACLK, posedge AWBURST[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWBURST_delay[1]); + $setuphold (posedge ACLK, posedge AWID[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[0]); + $setuphold (posedge ACLK, posedge AWID[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[1]); + $setuphold (posedge ACLK, posedge AWID[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[2]); + $setuphold (posedge ACLK, posedge AWID[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[3]); + $setuphold (posedge ACLK, posedge AWID[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[4]); + $setuphold (posedge ACLK, posedge AWID[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWID_delay[5]); + $setuphold (posedge ACLK, posedge AWLEN[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[0]); + $setuphold (posedge ACLK, posedge AWLEN[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[1]); + $setuphold (posedge ACLK, posedge AWLEN[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[2]); + $setuphold (posedge ACLK, posedge AWLEN[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWLEN_delay[3]); + $setuphold (posedge ACLK, posedge AWSIZE[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[0]); + $setuphold (posedge ACLK, posedge AWSIZE[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[1]); + $setuphold (posedge ACLK, posedge AWSIZE[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWSIZE_delay[2]); + $setuphold (posedge ACLK, posedge AWVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, AWVALID_delay); + $setuphold (posedge ACLK, posedge BREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, BREADY_delay); + $setuphold (posedge ACLK, posedge DFI_LP_PWR_X_REQ, 0:0:0, 0:0:0, notifier, , , ACLK_delay, DFI_LP_PWR_X_REQ_delay); + $setuphold (posedge ACLK, posedge RREADY, 0:0:0, 0:0:0, notifier, , , ACLK_delay, RREADY_delay); + $setuphold (posedge ACLK, posedge WDATA[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[0]); + $setuphold (posedge ACLK, posedge WDATA[100], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[100]); + $setuphold (posedge ACLK, posedge WDATA[101], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[101]); + $setuphold (posedge ACLK, posedge WDATA[102], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[102]); + $setuphold (posedge ACLK, posedge WDATA[103], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[103]); + $setuphold (posedge ACLK, posedge WDATA[104], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[104]); + $setuphold (posedge ACLK, posedge WDATA[105], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[105]); + $setuphold (posedge ACLK, posedge WDATA[106], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[106]); + $setuphold (posedge ACLK, posedge WDATA[107], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[107]); + $setuphold (posedge ACLK, posedge WDATA[108], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[108]); + $setuphold (posedge ACLK, posedge WDATA[109], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[109]); + $setuphold (posedge ACLK, posedge WDATA[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[10]); + $setuphold (posedge ACLK, posedge WDATA[110], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[110]); + $setuphold (posedge ACLK, posedge WDATA[111], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[111]); + $setuphold (posedge ACLK, posedge WDATA[112], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[112]); + $setuphold (posedge ACLK, posedge WDATA[113], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[113]); + $setuphold (posedge ACLK, posedge WDATA[114], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[114]); + $setuphold (posedge ACLK, posedge WDATA[115], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[115]); + $setuphold (posedge ACLK, posedge WDATA[116], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[116]); + $setuphold (posedge ACLK, posedge WDATA[117], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[117]); + $setuphold (posedge ACLK, posedge WDATA[118], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[118]); + $setuphold (posedge ACLK, posedge WDATA[119], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[119]); + $setuphold (posedge ACLK, posedge WDATA[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[11]); + $setuphold (posedge ACLK, posedge WDATA[120], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[120]); + $setuphold (posedge ACLK, posedge WDATA[121], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[121]); + $setuphold (posedge ACLK, posedge WDATA[122], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[122]); + $setuphold (posedge ACLK, posedge WDATA[123], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[123]); + $setuphold (posedge ACLK, posedge WDATA[124], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[124]); + $setuphold (posedge ACLK, posedge WDATA[125], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[125]); + $setuphold (posedge ACLK, posedge WDATA[126], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[126]); + $setuphold (posedge ACLK, posedge WDATA[127], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[127]); + $setuphold (posedge ACLK, posedge WDATA[128], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[128]); + $setuphold (posedge ACLK, posedge WDATA[129], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[129]); + $setuphold (posedge ACLK, posedge WDATA[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[12]); + $setuphold (posedge ACLK, posedge WDATA[130], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[130]); + $setuphold (posedge ACLK, posedge WDATA[131], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[131]); + $setuphold (posedge ACLK, posedge WDATA[132], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[132]); + $setuphold (posedge ACLK, posedge WDATA[133], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[133]); + $setuphold (posedge ACLK, posedge WDATA[134], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[134]); + $setuphold (posedge ACLK, posedge WDATA[135], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[135]); + $setuphold (posedge ACLK, posedge WDATA[136], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[136]); + $setuphold (posedge ACLK, posedge WDATA[137], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[137]); + $setuphold (posedge ACLK, posedge WDATA[138], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[138]); + $setuphold (posedge ACLK, posedge WDATA[139], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[139]); + $setuphold (posedge ACLK, posedge WDATA[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[13]); + $setuphold (posedge ACLK, posedge WDATA[140], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[140]); + $setuphold (posedge ACLK, posedge WDATA[141], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[141]); + $setuphold (posedge ACLK, posedge WDATA[142], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[142]); + $setuphold (posedge ACLK, posedge WDATA[143], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[143]); + $setuphold (posedge ACLK, posedge WDATA[144], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[144]); + $setuphold (posedge ACLK, posedge WDATA[145], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[145]); + $setuphold (posedge ACLK, posedge WDATA[146], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[146]); + $setuphold (posedge ACLK, posedge WDATA[147], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[147]); + $setuphold (posedge ACLK, posedge WDATA[148], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[148]); + $setuphold (posedge ACLK, posedge WDATA[149], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[149]); + $setuphold (posedge ACLK, posedge WDATA[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[14]); + $setuphold (posedge ACLK, posedge WDATA[150], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[150]); + $setuphold (posedge ACLK, posedge WDATA[151], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[151]); + $setuphold (posedge ACLK, posedge WDATA[152], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[152]); + $setuphold (posedge ACLK, posedge WDATA[153], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[153]); + $setuphold (posedge ACLK, posedge WDATA[154], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[154]); + $setuphold (posedge ACLK, posedge WDATA[155], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[155]); + $setuphold (posedge ACLK, posedge WDATA[156], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[156]); + $setuphold (posedge ACLK, posedge WDATA[157], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[157]); + $setuphold (posedge ACLK, posedge WDATA[158], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[158]); + $setuphold (posedge ACLK, posedge WDATA[159], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[159]); + $setuphold (posedge ACLK, posedge WDATA[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[15]); + $setuphold (posedge ACLK, posedge WDATA[160], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[160]); + $setuphold (posedge ACLK, posedge WDATA[161], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[161]); + $setuphold (posedge ACLK, posedge WDATA[162], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[162]); + $setuphold (posedge ACLK, posedge WDATA[163], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[163]); + $setuphold (posedge ACLK, posedge WDATA[164], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[164]); + $setuphold (posedge ACLK, posedge WDATA[165], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[165]); + $setuphold (posedge ACLK, posedge WDATA[166], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[166]); + $setuphold (posedge ACLK, posedge WDATA[167], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[167]); + $setuphold (posedge ACLK, posedge WDATA[168], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[168]); + $setuphold (posedge ACLK, posedge WDATA[169], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[169]); + $setuphold (posedge ACLK, posedge WDATA[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[16]); + $setuphold (posedge ACLK, posedge WDATA[170], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[170]); + $setuphold (posedge ACLK, posedge WDATA[171], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[171]); + $setuphold (posedge ACLK, posedge WDATA[172], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[172]); + $setuphold (posedge ACLK, posedge WDATA[173], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[173]); + $setuphold (posedge ACLK, posedge WDATA[174], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[174]); + $setuphold (posedge ACLK, posedge WDATA[175], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[175]); + $setuphold (posedge ACLK, posedge WDATA[176], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[176]); + $setuphold (posedge ACLK, posedge WDATA[177], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[177]); + $setuphold (posedge ACLK, posedge WDATA[178], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[178]); + $setuphold (posedge ACLK, posedge WDATA[179], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[179]); + $setuphold (posedge ACLK, posedge WDATA[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[17]); + $setuphold (posedge ACLK, posedge WDATA[180], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[180]); + $setuphold (posedge ACLK, posedge WDATA[181], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[181]); + $setuphold (posedge ACLK, posedge WDATA[182], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[182]); + $setuphold (posedge ACLK, posedge WDATA[183], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[183]); + $setuphold (posedge ACLK, posedge WDATA[184], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[184]); + $setuphold (posedge ACLK, posedge WDATA[185], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[185]); + $setuphold (posedge ACLK, posedge WDATA[186], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[186]); + $setuphold (posedge ACLK, posedge WDATA[187], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[187]); + $setuphold (posedge ACLK, posedge WDATA[188], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[188]); + $setuphold (posedge ACLK, posedge WDATA[189], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[189]); + $setuphold (posedge ACLK, posedge WDATA[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[18]); + $setuphold (posedge ACLK, posedge WDATA[190], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[190]); + $setuphold (posedge ACLK, posedge WDATA[191], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[191]); + $setuphold (posedge ACLK, posedge WDATA[192], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[192]); + $setuphold (posedge ACLK, posedge WDATA[193], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[193]); + $setuphold (posedge ACLK, posedge WDATA[194], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[194]); + $setuphold (posedge ACLK, posedge WDATA[195], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[195]); + $setuphold (posedge ACLK, posedge WDATA[196], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[196]); + $setuphold (posedge ACLK, posedge WDATA[197], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[197]); + $setuphold (posedge ACLK, posedge WDATA[198], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[198]); + $setuphold (posedge ACLK, posedge WDATA[199], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[199]); + $setuphold (posedge ACLK, posedge WDATA[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[19]); + $setuphold (posedge ACLK, posedge WDATA[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[1]); + $setuphold (posedge ACLK, posedge WDATA[200], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[200]); + $setuphold (posedge ACLK, posedge WDATA[201], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[201]); + $setuphold (posedge ACLK, posedge WDATA[202], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[202]); + $setuphold (posedge ACLK, posedge WDATA[203], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[203]); + $setuphold (posedge ACLK, posedge WDATA[204], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[204]); + $setuphold (posedge ACLK, posedge WDATA[205], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[205]); + $setuphold (posedge ACLK, posedge WDATA[206], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[206]); + $setuphold (posedge ACLK, posedge WDATA[207], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[207]); + $setuphold (posedge ACLK, posedge WDATA[208], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[208]); + $setuphold (posedge ACLK, posedge WDATA[209], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[209]); + $setuphold (posedge ACLK, posedge WDATA[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[20]); + $setuphold (posedge ACLK, posedge WDATA[210], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[210]); + $setuphold (posedge ACLK, posedge WDATA[211], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[211]); + $setuphold (posedge ACLK, posedge WDATA[212], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[212]); + $setuphold (posedge ACLK, posedge WDATA[213], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[213]); + $setuphold (posedge ACLK, posedge WDATA[214], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[214]); + $setuphold (posedge ACLK, posedge WDATA[215], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[215]); + $setuphold (posedge ACLK, posedge WDATA[216], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[216]); + $setuphold (posedge ACLK, posedge WDATA[217], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[217]); + $setuphold (posedge ACLK, posedge WDATA[218], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[218]); + $setuphold (posedge ACLK, posedge WDATA[219], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[219]); + $setuphold (posedge ACLK, posedge WDATA[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[21]); + $setuphold (posedge ACLK, posedge WDATA[220], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[220]); + $setuphold (posedge ACLK, posedge WDATA[221], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[221]); + $setuphold (posedge ACLK, posedge WDATA[222], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[222]); + $setuphold (posedge ACLK, posedge WDATA[223], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[223]); + $setuphold (posedge ACLK, posedge WDATA[224], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[224]); + $setuphold (posedge ACLK, posedge WDATA[225], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[225]); + $setuphold (posedge ACLK, posedge WDATA[226], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[226]); + $setuphold (posedge ACLK, posedge WDATA[227], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[227]); + $setuphold (posedge ACLK, posedge WDATA[228], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[228]); + $setuphold (posedge ACLK, posedge WDATA[229], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[229]); + $setuphold (posedge ACLK, posedge WDATA[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[22]); + $setuphold (posedge ACLK, posedge WDATA[230], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[230]); + $setuphold (posedge ACLK, posedge WDATA[231], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[231]); + $setuphold (posedge ACLK, posedge WDATA[232], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[232]); + $setuphold (posedge ACLK, posedge WDATA[233], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[233]); + $setuphold (posedge ACLK, posedge WDATA[234], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[234]); + $setuphold (posedge ACLK, posedge WDATA[235], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[235]); + $setuphold (posedge ACLK, posedge WDATA[236], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[236]); + $setuphold (posedge ACLK, posedge WDATA[237], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[237]); + $setuphold (posedge ACLK, posedge WDATA[238], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[238]); + $setuphold (posedge ACLK, posedge WDATA[239], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[239]); + $setuphold (posedge ACLK, posedge WDATA[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[23]); + $setuphold (posedge ACLK, posedge WDATA[240], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[240]); + $setuphold (posedge ACLK, posedge WDATA[241], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[241]); + $setuphold (posedge ACLK, posedge WDATA[242], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[242]); + $setuphold (posedge ACLK, posedge WDATA[243], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[243]); + $setuphold (posedge ACLK, posedge WDATA[244], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[244]); + $setuphold (posedge ACLK, posedge WDATA[245], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[245]); + $setuphold (posedge ACLK, posedge WDATA[246], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[246]); + $setuphold (posedge ACLK, posedge WDATA[247], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[247]); + $setuphold (posedge ACLK, posedge WDATA[248], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[248]); + $setuphold (posedge ACLK, posedge WDATA[249], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[249]); + $setuphold (posedge ACLK, posedge WDATA[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[24]); + $setuphold (posedge ACLK, posedge WDATA[250], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[250]); + $setuphold (posedge ACLK, posedge WDATA[251], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[251]); + $setuphold (posedge ACLK, posedge WDATA[252], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[252]); + $setuphold (posedge ACLK, posedge WDATA[253], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[253]); + $setuphold (posedge ACLK, posedge WDATA[254], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[254]); + $setuphold (posedge ACLK, posedge WDATA[255], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[255]); + $setuphold (posedge ACLK, posedge WDATA[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[25]); + $setuphold (posedge ACLK, posedge WDATA[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[26]); + $setuphold (posedge ACLK, posedge WDATA[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[27]); + $setuphold (posedge ACLK, posedge WDATA[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[28]); + $setuphold (posedge ACLK, posedge WDATA[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[29]); + $setuphold (posedge ACLK, posedge WDATA[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[2]); + $setuphold (posedge ACLK, posedge WDATA[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[30]); + $setuphold (posedge ACLK, posedge WDATA[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[31]); + $setuphold (posedge ACLK, posedge WDATA[32], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[32]); + $setuphold (posedge ACLK, posedge WDATA[33], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[33]); + $setuphold (posedge ACLK, posedge WDATA[34], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[34]); + $setuphold (posedge ACLK, posedge WDATA[35], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[35]); + $setuphold (posedge ACLK, posedge WDATA[36], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[36]); + $setuphold (posedge ACLK, posedge WDATA[37], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[37]); + $setuphold (posedge ACLK, posedge WDATA[38], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[38]); + $setuphold (posedge ACLK, posedge WDATA[39], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[39]); + $setuphold (posedge ACLK, posedge WDATA[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[3]); + $setuphold (posedge ACLK, posedge WDATA[40], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[40]); + $setuphold (posedge ACLK, posedge WDATA[41], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[41]); + $setuphold (posedge ACLK, posedge WDATA[42], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[42]); + $setuphold (posedge ACLK, posedge WDATA[43], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[43]); + $setuphold (posedge ACLK, posedge WDATA[44], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[44]); + $setuphold (posedge ACLK, posedge WDATA[45], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[45]); + $setuphold (posedge ACLK, posedge WDATA[46], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[46]); + $setuphold (posedge ACLK, posedge WDATA[47], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[47]); + $setuphold (posedge ACLK, posedge WDATA[48], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[48]); + $setuphold (posedge ACLK, posedge WDATA[49], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[49]); + $setuphold (posedge ACLK, posedge WDATA[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[4]); + $setuphold (posedge ACLK, posedge WDATA[50], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[50]); + $setuphold (posedge ACLK, posedge WDATA[51], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[51]); + $setuphold (posedge ACLK, posedge WDATA[52], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[52]); + $setuphold (posedge ACLK, posedge WDATA[53], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[53]); + $setuphold (posedge ACLK, posedge WDATA[54], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[54]); + $setuphold (posedge ACLK, posedge WDATA[55], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[55]); + $setuphold (posedge ACLK, posedge WDATA[56], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[56]); + $setuphold (posedge ACLK, posedge WDATA[57], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[57]); + $setuphold (posedge ACLK, posedge WDATA[58], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[58]); + $setuphold (posedge ACLK, posedge WDATA[59], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[59]); + $setuphold (posedge ACLK, posedge WDATA[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[5]); + $setuphold (posedge ACLK, posedge WDATA[60], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[60]); + $setuphold (posedge ACLK, posedge WDATA[61], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[61]); + $setuphold (posedge ACLK, posedge WDATA[62], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[62]); + $setuphold (posedge ACLK, posedge WDATA[63], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[63]); + $setuphold (posedge ACLK, posedge WDATA[64], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[64]); + $setuphold (posedge ACLK, posedge WDATA[65], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[65]); + $setuphold (posedge ACLK, posedge WDATA[66], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[66]); + $setuphold (posedge ACLK, posedge WDATA[67], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[67]); + $setuphold (posedge ACLK, posedge WDATA[68], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[68]); + $setuphold (posedge ACLK, posedge WDATA[69], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[69]); + $setuphold (posedge ACLK, posedge WDATA[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[6]); + $setuphold (posedge ACLK, posedge WDATA[70], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[70]); + $setuphold (posedge ACLK, posedge WDATA[71], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[71]); + $setuphold (posedge ACLK, posedge WDATA[72], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[72]); + $setuphold (posedge ACLK, posedge WDATA[73], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[73]); + $setuphold (posedge ACLK, posedge WDATA[74], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[74]); + $setuphold (posedge ACLK, posedge WDATA[75], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[75]); + $setuphold (posedge ACLK, posedge WDATA[76], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[76]); + $setuphold (posedge ACLK, posedge WDATA[77], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[77]); + $setuphold (posedge ACLK, posedge WDATA[78], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[78]); + $setuphold (posedge ACLK, posedge WDATA[79], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[79]); + $setuphold (posedge ACLK, posedge WDATA[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[7]); + $setuphold (posedge ACLK, posedge WDATA[80], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[80]); + $setuphold (posedge ACLK, posedge WDATA[81], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[81]); + $setuphold (posedge ACLK, posedge WDATA[82], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[82]); + $setuphold (posedge ACLK, posedge WDATA[83], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[83]); + $setuphold (posedge ACLK, posedge WDATA[84], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[84]); + $setuphold (posedge ACLK, posedge WDATA[85], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[85]); + $setuphold (posedge ACLK, posedge WDATA[86], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[86]); + $setuphold (posedge ACLK, posedge WDATA[87], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[87]); + $setuphold (posedge ACLK, posedge WDATA[88], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[88]); + $setuphold (posedge ACLK, posedge WDATA[89], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[89]); + $setuphold (posedge ACLK, posedge WDATA[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[8]); + $setuphold (posedge ACLK, posedge WDATA[90], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[90]); + $setuphold (posedge ACLK, posedge WDATA[91], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[91]); + $setuphold (posedge ACLK, posedge WDATA[92], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[92]); + $setuphold (posedge ACLK, posedge WDATA[93], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[93]); + $setuphold (posedge ACLK, posedge WDATA[94], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[94]); + $setuphold (posedge ACLK, posedge WDATA[95], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[95]); + $setuphold (posedge ACLK, posedge WDATA[96], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[96]); + $setuphold (posedge ACLK, posedge WDATA[97], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[97]); + $setuphold (posedge ACLK, posedge WDATA[98], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[98]); + $setuphold (posedge ACLK, posedge WDATA[99], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[99]); + $setuphold (posedge ACLK, posedge WDATA[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_delay[9]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[0]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[10]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[11]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[12]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[13]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[14]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[15]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[16]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[17]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[18]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[19]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[1]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[20]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[21]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[22]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[23]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[24]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[25]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[26]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[27]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[28]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[29]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[2]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[30]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[31]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[3]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[4]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[5]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[6]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[7]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[8]); + $setuphold (posedge ACLK, posedge WDATA_PARITY[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WDATA_PARITY_delay[9]); + $setuphold (posedge ACLK, posedge WLAST, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WLAST_delay); + $setuphold (posedge ACLK, posedge WSTRB[0], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[0]); + $setuphold (posedge ACLK, posedge WSTRB[10], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[10]); + $setuphold (posedge ACLK, posedge WSTRB[11], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[11]); + $setuphold (posedge ACLK, posedge WSTRB[12], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[12]); + $setuphold (posedge ACLK, posedge WSTRB[13], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[13]); + $setuphold (posedge ACLK, posedge WSTRB[14], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[14]); + $setuphold (posedge ACLK, posedge WSTRB[15], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[15]); + $setuphold (posedge ACLK, posedge WSTRB[16], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[16]); + $setuphold (posedge ACLK, posedge WSTRB[17], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[17]); + $setuphold (posedge ACLK, posedge WSTRB[18], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[18]); + $setuphold (posedge ACLK, posedge WSTRB[19], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[19]); + $setuphold (posedge ACLK, posedge WSTRB[1], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[1]); + $setuphold (posedge ACLK, posedge WSTRB[20], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[20]); + $setuphold (posedge ACLK, posedge WSTRB[21], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[21]); + $setuphold (posedge ACLK, posedge WSTRB[22], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[22]); + $setuphold (posedge ACLK, posedge WSTRB[23], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[23]); + $setuphold (posedge ACLK, posedge WSTRB[24], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[24]); + $setuphold (posedge ACLK, posedge WSTRB[25], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[25]); + $setuphold (posedge ACLK, posedge WSTRB[26], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[26]); + $setuphold (posedge ACLK, posedge WSTRB[27], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[27]); + $setuphold (posedge ACLK, posedge WSTRB[28], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[28]); + $setuphold (posedge ACLK, posedge WSTRB[29], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[29]); + $setuphold (posedge ACLK, posedge WSTRB[2], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[2]); + $setuphold (posedge ACLK, posedge WSTRB[30], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[30]); + $setuphold (posedge ACLK, posedge WSTRB[31], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[31]); + $setuphold (posedge ACLK, posedge WSTRB[3], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[3]); + $setuphold (posedge ACLK, posedge WSTRB[4], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[4]); + $setuphold (posedge ACLK, posedge WSTRB[5], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[5]); + $setuphold (posedge ACLK, posedge WSTRB[6], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[6]); + $setuphold (posedge ACLK, posedge WSTRB[7], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[7]); + $setuphold (posedge ACLK, posedge WSTRB[8], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[8]); + $setuphold (posedge ACLK, posedge WSTRB[9], 0:0:0, 0:0:0, notifier, , , ACLK_delay, WSTRB_delay[9]); + $setuphold (posedge ACLK, posedge WVALID, 0:0:0, 0:0:0, notifier, , , ACLK_delay, WVALID_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HBM_TWO_STACK_INTF.v b/verilog/src/unisims/HBM_TWO_STACK_INTF.v new file mode 100644 index 0000000..75ec39f --- /dev/null +++ b/verilog/src/unisims/HBM_TWO_STACK_INTF.v @@ -0,0 +1,8911 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HBM_TWO_STACK_INTF +// /___/ /\ Filename : HBM_TWO_STACK_INTF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HBM_TWO_STACK_INTF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CLK_SEL_00 = "FALSE", + parameter CLK_SEL_01 = "FALSE", + parameter CLK_SEL_02 = "FALSE", + parameter CLK_SEL_03 = "FALSE", + parameter CLK_SEL_04 = "FALSE", + parameter CLK_SEL_05 = "FALSE", + parameter CLK_SEL_06 = "FALSE", + parameter CLK_SEL_07 = "FALSE", + parameter CLK_SEL_08 = "FALSE", + parameter CLK_SEL_09 = "FALSE", + parameter CLK_SEL_10 = "FALSE", + parameter CLK_SEL_11 = "FALSE", + parameter CLK_SEL_12 = "FALSE", + parameter CLK_SEL_13 = "FALSE", + parameter CLK_SEL_14 = "FALSE", + parameter CLK_SEL_15 = "FALSE", + parameter CLK_SEL_16 = "FALSE", + parameter CLK_SEL_17 = "FALSE", + parameter CLK_SEL_18 = "FALSE", + parameter CLK_SEL_19 = "FALSE", + parameter CLK_SEL_20 = "FALSE", + parameter CLK_SEL_21 = "FALSE", + parameter CLK_SEL_22 = "FALSE", + parameter CLK_SEL_23 = "FALSE", + parameter CLK_SEL_24 = "FALSE", + parameter CLK_SEL_25 = "FALSE", + parameter CLK_SEL_26 = "FALSE", + parameter CLK_SEL_27 = "FALSE", + parameter CLK_SEL_28 = "FALSE", + parameter CLK_SEL_29 = "FALSE", + parameter CLK_SEL_30 = "FALSE", + parameter CLK_SEL_31 = "FALSE", + parameter integer DATARATE_00 = 1800, + parameter integer DATARATE_01 = 1800, + parameter integer DATARATE_02 = 1800, + parameter integer DATARATE_03 = 1800, + parameter integer DATARATE_04 = 1800, + parameter integer DATARATE_05 = 1800, + parameter integer DATARATE_06 = 1800, + parameter integer DATARATE_07 = 1800, + parameter integer DATARATE_08 = 1800, + parameter integer DATARATE_09 = 1800, + parameter integer DATARATE_10 = 1800, + parameter integer DATARATE_11 = 1800, + parameter integer DATARATE_12 = 1800, + parameter integer DATARATE_13 = 1800, + parameter integer DATARATE_14 = 1800, + parameter integer DATARATE_15 = 1800, + parameter DA_LOCKOUT_0 = "FALSE", + parameter DA_LOCKOUT_1 = "FALSE", + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0, + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0, + parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0, + parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0, + parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0, + parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0, + parameter MC_ENABLE_00 = "FALSE", + parameter MC_ENABLE_01 = "FALSE", + parameter MC_ENABLE_02 = "FALSE", + parameter MC_ENABLE_03 = "FALSE", + parameter MC_ENABLE_04 = "FALSE", + parameter MC_ENABLE_05 = "FALSE", + parameter MC_ENABLE_06 = "FALSE", + parameter MC_ENABLE_07 = "FALSE", + parameter MC_ENABLE_08 = "FALSE", + parameter MC_ENABLE_09 = "FALSE", + parameter MC_ENABLE_10 = "FALSE", + parameter MC_ENABLE_11 = "FALSE", + parameter MC_ENABLE_12 = "FALSE", + parameter MC_ENABLE_13 = "FALSE", + parameter MC_ENABLE_14 = "FALSE", + parameter MC_ENABLE_15 = "FALSE", + parameter MC_ENABLE_APB_00 = "FALSE", + parameter MC_ENABLE_APB_01 = "FALSE", + parameter integer PAGEHIT_PERCENT_00 = 75, + parameter integer PAGEHIT_PERCENT_01 = 75, + parameter PHY_ENABLE_00 = "FALSE", + parameter PHY_ENABLE_01 = "FALSE", + parameter PHY_ENABLE_02 = "FALSE", + parameter PHY_ENABLE_03 = "FALSE", + parameter PHY_ENABLE_04 = "FALSE", + parameter PHY_ENABLE_05 = "FALSE", + parameter PHY_ENABLE_06 = "FALSE", + parameter PHY_ENABLE_07 = "FALSE", + parameter PHY_ENABLE_08 = "FALSE", + parameter PHY_ENABLE_09 = "FALSE", + parameter PHY_ENABLE_10 = "FALSE", + parameter PHY_ENABLE_11 = "FALSE", + parameter PHY_ENABLE_12 = "FALSE", + parameter PHY_ENABLE_13 = "FALSE", + parameter PHY_ENABLE_14 = "FALSE", + parameter PHY_ENABLE_15 = "FALSE", + parameter PHY_ENABLE_16 = "FALSE", + parameter PHY_ENABLE_17 = "FALSE", + parameter PHY_ENABLE_18 = "FALSE", + parameter PHY_ENABLE_19 = "FALSE", + parameter PHY_ENABLE_20 = "FALSE", + parameter PHY_ENABLE_21 = "FALSE", + parameter PHY_ENABLE_22 = "FALSE", + parameter PHY_ENABLE_23 = "FALSE", + parameter PHY_ENABLE_24 = "FALSE", + parameter PHY_ENABLE_25 = "FALSE", + parameter PHY_ENABLE_26 = "FALSE", + parameter PHY_ENABLE_27 = "FALSE", + parameter PHY_ENABLE_28 = "FALSE", + parameter PHY_ENABLE_29 = "FALSE", + parameter PHY_ENABLE_30 = "FALSE", + parameter PHY_ENABLE_31 = "FALSE", + parameter PHY_ENABLE_APB_00 = "FALSE", + parameter PHY_ENABLE_APB_01 = "FALSE", + parameter PHY_PCLK_INVERT_01 = "FALSE", + parameter PHY_PCLK_INVERT_02 = "FALSE", + parameter integer READ_PERCENT_00 = 50, + parameter integer READ_PERCENT_01 = 50, + parameter integer READ_PERCENT_02 = 50, + parameter integer READ_PERCENT_03 = 50, + parameter integer READ_PERCENT_04 = 50, + parameter integer READ_PERCENT_05 = 50, + parameter integer READ_PERCENT_06 = 50, + parameter integer READ_PERCENT_07 = 50, + parameter integer READ_PERCENT_08 = 50, + parameter integer READ_PERCENT_09 = 50, + parameter integer READ_PERCENT_10 = 50, + parameter integer READ_PERCENT_11 = 50, + parameter integer READ_PERCENT_12 = 50, + parameter integer READ_PERCENT_13 = 50, + parameter integer READ_PERCENT_14 = 50, + parameter integer READ_PERCENT_15 = 50, + parameter integer READ_PERCENT_16 = 50, + parameter integer READ_PERCENT_17 = 50, + parameter integer READ_PERCENT_18 = 50, + parameter integer READ_PERCENT_19 = 50, + parameter integer READ_PERCENT_20 = 50, + parameter integer READ_PERCENT_21 = 50, + parameter integer READ_PERCENT_22 = 50, + parameter integer READ_PERCENT_23 = 50, + parameter integer READ_PERCENT_24 = 50, + parameter integer READ_PERCENT_25 = 50, + parameter integer READ_PERCENT_26 = 50, + parameter integer READ_PERCENT_27 = 50, + parameter integer READ_PERCENT_28 = 50, + parameter integer READ_PERCENT_29 = 50, + parameter integer READ_PERCENT_30 = 50, + parameter integer READ_PERCENT_31 = 50, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SWITCH_ENABLE_00 = "FALSE", + parameter SWITCH_ENABLE_01 = "FALSE", + parameter integer WRITE_PERCENT_00 = 50, + parameter integer WRITE_PERCENT_01 = 50, + parameter integer WRITE_PERCENT_02 = 50, + parameter integer WRITE_PERCENT_03 = 50, + parameter integer WRITE_PERCENT_04 = 50, + parameter integer WRITE_PERCENT_05 = 50, + parameter integer WRITE_PERCENT_06 = 50, + parameter integer WRITE_PERCENT_07 = 50, + parameter integer WRITE_PERCENT_08 = 50, + parameter integer WRITE_PERCENT_09 = 50, + parameter integer WRITE_PERCENT_10 = 50, + parameter integer WRITE_PERCENT_11 = 50, + parameter integer WRITE_PERCENT_12 = 50, + parameter integer WRITE_PERCENT_13 = 50, + parameter integer WRITE_PERCENT_14 = 50, + parameter integer WRITE_PERCENT_15 = 50, + parameter integer WRITE_PERCENT_16 = 50, + parameter integer WRITE_PERCENT_17 = 50, + parameter integer WRITE_PERCENT_18 = 50, + parameter integer WRITE_PERCENT_19 = 50, + parameter integer WRITE_PERCENT_20 = 50, + parameter integer WRITE_PERCENT_21 = 50, + parameter integer WRITE_PERCENT_22 = 50, + parameter integer WRITE_PERCENT_23 = 50, + parameter integer WRITE_PERCENT_24 = 50, + parameter integer WRITE_PERCENT_25 = 50, + parameter integer WRITE_PERCENT_26 = 50, + parameter integer WRITE_PERCENT_27 = 50, + parameter integer WRITE_PERCENT_28 = 50, + parameter integer WRITE_PERCENT_29 = 50, + parameter integer WRITE_PERCENT_30 = 50, + parameter integer WRITE_PERCENT_31 = 50 +)( + output [31:0] APB_0_PRDATA, + output APB_0_PREADY, + output APB_0_PSLVERR, + output [31:0] APB_1_PRDATA, + output APB_1_PREADY, + output APB_1_PSLVERR, + output AXI_00_ARREADY, + output AXI_00_AWREADY, + output [5:0] AXI_00_BID, + output [1:0] AXI_00_BRESP, + output AXI_00_BVALID, + output [1:0] AXI_00_DFI_AW_AERR_N, + output AXI_00_DFI_CLK_BUF, + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_00_DFI_DW_RDDATA_DBI, + output [7:0] AXI_00_DFI_DW_RDDATA_DERR, + output [1:0] AXI_00_DFI_DW_RDDATA_VALID, + output AXI_00_DFI_INIT_COMPLETE, + output AXI_00_DFI_PHYUPD_REQ, + output AXI_00_DFI_PHY_LP_STATE, + output AXI_00_DFI_RST_N_BUF, + output [5:0] AXI_00_MC_STATUS, + output [7:0] AXI_00_PHY_STATUS, + output [255:0] AXI_00_RDATA, + output [31:0] AXI_00_RDATA_PARITY, + output [5:0] AXI_00_RID, + output AXI_00_RLAST, + output [1:0] AXI_00_RRESP, + output AXI_00_RVALID, + output AXI_00_WREADY, + output AXI_01_ARREADY, + output AXI_01_AWREADY, + output [5:0] AXI_01_BID, + output [1:0] AXI_01_BRESP, + output AXI_01_BVALID, + output [1:0] AXI_01_DFI_AW_AERR_N, + output AXI_01_DFI_CLK_BUF, + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_01_DFI_DW_RDDATA_DBI, + output [7:0] AXI_01_DFI_DW_RDDATA_DERR, + output [1:0] AXI_01_DFI_DW_RDDATA_VALID, + output AXI_01_DFI_INIT_COMPLETE, + output AXI_01_DFI_PHYUPD_REQ, + output AXI_01_DFI_PHY_LP_STATE, + output AXI_01_DFI_RST_N_BUF, + output [255:0] AXI_01_RDATA, + output [31:0] AXI_01_RDATA_PARITY, + output [5:0] AXI_01_RID, + output AXI_01_RLAST, + output [1:0] AXI_01_RRESP, + output AXI_01_RVALID, + output AXI_01_WREADY, + output AXI_02_ARREADY, + output AXI_02_AWREADY, + output [5:0] AXI_02_BID, + output [1:0] AXI_02_BRESP, + output AXI_02_BVALID, + output [1:0] AXI_02_DFI_AW_AERR_N, + output AXI_02_DFI_CLK_BUF, + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_02_DFI_DW_RDDATA_DBI, + output [7:0] AXI_02_DFI_DW_RDDATA_DERR, + output [1:0] AXI_02_DFI_DW_RDDATA_VALID, + output AXI_02_DFI_INIT_COMPLETE, + output AXI_02_DFI_PHYUPD_REQ, + output AXI_02_DFI_PHY_LP_STATE, + output AXI_02_DFI_RST_N_BUF, + output [5:0] AXI_02_MC_STATUS, + output [7:0] AXI_02_PHY_STATUS, + output [255:0] AXI_02_RDATA, + output [31:0] AXI_02_RDATA_PARITY, + output [5:0] AXI_02_RID, + output AXI_02_RLAST, + output [1:0] AXI_02_RRESP, + output AXI_02_RVALID, + output AXI_02_WREADY, + output AXI_03_ARREADY, + output AXI_03_AWREADY, + output [5:0] AXI_03_BID, + output [1:0] AXI_03_BRESP, + output AXI_03_BVALID, + output [1:0] AXI_03_DFI_AW_AERR_N, + output AXI_03_DFI_CLK_BUF, + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_03_DFI_DW_RDDATA_DBI, + output [7:0] AXI_03_DFI_DW_RDDATA_DERR, + output [1:0] AXI_03_DFI_DW_RDDATA_VALID, + output AXI_03_DFI_INIT_COMPLETE, + output AXI_03_DFI_PHYUPD_REQ, + output AXI_03_DFI_PHY_LP_STATE, + output AXI_03_DFI_RST_N_BUF, + output [255:0] AXI_03_RDATA, + output [31:0] AXI_03_RDATA_PARITY, + output [5:0] AXI_03_RID, + output AXI_03_RLAST, + output [1:0] AXI_03_RRESP, + output AXI_03_RVALID, + output AXI_03_WREADY, + output AXI_04_ARREADY, + output AXI_04_AWREADY, + output [5:0] AXI_04_BID, + output [1:0] AXI_04_BRESP, + output AXI_04_BVALID, + output [1:0] AXI_04_DFI_AW_AERR_N, + output AXI_04_DFI_CLK_BUF, + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_04_DFI_DW_RDDATA_DBI, + output [7:0] AXI_04_DFI_DW_RDDATA_DERR, + output [1:0] AXI_04_DFI_DW_RDDATA_VALID, + output AXI_04_DFI_INIT_COMPLETE, + output AXI_04_DFI_PHYUPD_REQ, + output AXI_04_DFI_PHY_LP_STATE, + output AXI_04_DFI_RST_N_BUF, + output [5:0] AXI_04_MC_STATUS, + output [7:0] AXI_04_PHY_STATUS, + output [255:0] AXI_04_RDATA, + output [31:0] AXI_04_RDATA_PARITY, + output [5:0] AXI_04_RID, + output AXI_04_RLAST, + output [1:0] AXI_04_RRESP, + output AXI_04_RVALID, + output AXI_04_WREADY, + output AXI_05_ARREADY, + output AXI_05_AWREADY, + output [5:0] AXI_05_BID, + output [1:0] AXI_05_BRESP, + output AXI_05_BVALID, + output [1:0] AXI_05_DFI_AW_AERR_N, + output AXI_05_DFI_CLK_BUF, + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_05_DFI_DW_RDDATA_DBI, + output [7:0] AXI_05_DFI_DW_RDDATA_DERR, + output [1:0] AXI_05_DFI_DW_RDDATA_VALID, + output AXI_05_DFI_INIT_COMPLETE, + output AXI_05_DFI_PHYUPD_REQ, + output AXI_05_DFI_PHY_LP_STATE, + output AXI_05_DFI_RST_N_BUF, + output [255:0] AXI_05_RDATA, + output [31:0] AXI_05_RDATA_PARITY, + output [5:0] AXI_05_RID, + output AXI_05_RLAST, + output [1:0] AXI_05_RRESP, + output AXI_05_RVALID, + output AXI_05_WREADY, + output AXI_06_ARREADY, + output AXI_06_AWREADY, + output [5:0] AXI_06_BID, + output [1:0] AXI_06_BRESP, + output AXI_06_BVALID, + output [1:0] AXI_06_DFI_AW_AERR_N, + output AXI_06_DFI_CLK_BUF, + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_06_DFI_DW_RDDATA_DBI, + output [7:0] AXI_06_DFI_DW_RDDATA_DERR, + output [1:0] AXI_06_DFI_DW_RDDATA_VALID, + output AXI_06_DFI_INIT_COMPLETE, + output AXI_06_DFI_PHYUPD_REQ, + output AXI_06_DFI_PHY_LP_STATE, + output AXI_06_DFI_RST_N_BUF, + output [5:0] AXI_06_MC_STATUS, + output [7:0] AXI_06_PHY_STATUS, + output [255:0] AXI_06_RDATA, + output [31:0] AXI_06_RDATA_PARITY, + output [5:0] AXI_06_RID, + output AXI_06_RLAST, + output [1:0] AXI_06_RRESP, + output AXI_06_RVALID, + output AXI_06_WREADY, + output AXI_07_ARREADY, + output AXI_07_AWREADY, + output [5:0] AXI_07_BID, + output [1:0] AXI_07_BRESP, + output AXI_07_BVALID, + output [1:0] AXI_07_DFI_AW_AERR_N, + output AXI_07_DFI_CLK_BUF, + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_07_DFI_DW_RDDATA_DBI, + output [7:0] AXI_07_DFI_DW_RDDATA_DERR, + output [1:0] AXI_07_DFI_DW_RDDATA_VALID, + output AXI_07_DFI_INIT_COMPLETE, + output AXI_07_DFI_PHYUPD_REQ, + output AXI_07_DFI_PHY_LP_STATE, + output AXI_07_DFI_RST_N_BUF, + output [255:0] AXI_07_RDATA, + output [31:0] AXI_07_RDATA_PARITY, + output [5:0] AXI_07_RID, + output AXI_07_RLAST, + output [1:0] AXI_07_RRESP, + output AXI_07_RVALID, + output AXI_07_WREADY, + output AXI_08_ARREADY, + output AXI_08_AWREADY, + output [5:0] AXI_08_BID, + output [1:0] AXI_08_BRESP, + output AXI_08_BVALID, + output [1:0] AXI_08_DFI_AW_AERR_N, + output AXI_08_DFI_CLK_BUF, + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_08_DFI_DW_RDDATA_DBI, + output [7:0] AXI_08_DFI_DW_RDDATA_DERR, + output [1:0] AXI_08_DFI_DW_RDDATA_VALID, + output AXI_08_DFI_INIT_COMPLETE, + output AXI_08_DFI_PHYUPD_REQ, + output AXI_08_DFI_PHY_LP_STATE, + output AXI_08_DFI_RST_N_BUF, + output [5:0] AXI_08_MC_STATUS, + output [7:0] AXI_08_PHY_STATUS, + output [255:0] AXI_08_RDATA, + output [31:0] AXI_08_RDATA_PARITY, + output [5:0] AXI_08_RID, + output AXI_08_RLAST, + output [1:0] AXI_08_RRESP, + output AXI_08_RVALID, + output AXI_08_WREADY, + output AXI_09_ARREADY, + output AXI_09_AWREADY, + output [5:0] AXI_09_BID, + output [1:0] AXI_09_BRESP, + output AXI_09_BVALID, + output [1:0] AXI_09_DFI_AW_AERR_N, + output AXI_09_DFI_CLK_BUF, + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_09_DFI_DW_RDDATA_DBI, + output [7:0] AXI_09_DFI_DW_RDDATA_DERR, + output [1:0] AXI_09_DFI_DW_RDDATA_VALID, + output AXI_09_DFI_INIT_COMPLETE, + output AXI_09_DFI_PHYUPD_REQ, + output AXI_09_DFI_PHY_LP_STATE, + output AXI_09_DFI_RST_N_BUF, + output [255:0] AXI_09_RDATA, + output [31:0] AXI_09_RDATA_PARITY, + output [5:0] AXI_09_RID, + output AXI_09_RLAST, + output [1:0] AXI_09_RRESP, + output AXI_09_RVALID, + output AXI_09_WREADY, + output AXI_10_ARREADY, + output AXI_10_AWREADY, + output [5:0] AXI_10_BID, + output [1:0] AXI_10_BRESP, + output AXI_10_BVALID, + output [1:0] AXI_10_DFI_AW_AERR_N, + output AXI_10_DFI_CLK_BUF, + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_10_DFI_DW_RDDATA_DBI, + output [7:0] AXI_10_DFI_DW_RDDATA_DERR, + output [1:0] AXI_10_DFI_DW_RDDATA_VALID, + output AXI_10_DFI_INIT_COMPLETE, + output AXI_10_DFI_PHYUPD_REQ, + output AXI_10_DFI_PHY_LP_STATE, + output AXI_10_DFI_RST_N_BUF, + output [5:0] AXI_10_MC_STATUS, + output [7:0] AXI_10_PHY_STATUS, + output [255:0] AXI_10_RDATA, + output [31:0] AXI_10_RDATA_PARITY, + output [5:0] AXI_10_RID, + output AXI_10_RLAST, + output [1:0] AXI_10_RRESP, + output AXI_10_RVALID, + output AXI_10_WREADY, + output AXI_11_ARREADY, + output AXI_11_AWREADY, + output [5:0] AXI_11_BID, + output [1:0] AXI_11_BRESP, + output AXI_11_BVALID, + output [1:0] AXI_11_DFI_AW_AERR_N, + output AXI_11_DFI_CLK_BUF, + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_11_DFI_DW_RDDATA_DBI, + output [7:0] AXI_11_DFI_DW_RDDATA_DERR, + output [1:0] AXI_11_DFI_DW_RDDATA_VALID, + output AXI_11_DFI_INIT_COMPLETE, + output AXI_11_DFI_PHYUPD_REQ, + output AXI_11_DFI_PHY_LP_STATE, + output AXI_11_DFI_RST_N_BUF, + output [255:0] AXI_11_RDATA, + output [31:0] AXI_11_RDATA_PARITY, + output [5:0] AXI_11_RID, + output AXI_11_RLAST, + output [1:0] AXI_11_RRESP, + output AXI_11_RVALID, + output AXI_11_WREADY, + output AXI_12_ARREADY, + output AXI_12_AWREADY, + output [5:0] AXI_12_BID, + output [1:0] AXI_12_BRESP, + output AXI_12_BVALID, + output [1:0] AXI_12_DFI_AW_AERR_N, + output AXI_12_DFI_CLK_BUF, + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_12_DFI_DW_RDDATA_DBI, + output [7:0] AXI_12_DFI_DW_RDDATA_DERR, + output [1:0] AXI_12_DFI_DW_RDDATA_VALID, + output AXI_12_DFI_INIT_COMPLETE, + output AXI_12_DFI_PHYUPD_REQ, + output AXI_12_DFI_PHY_LP_STATE, + output AXI_12_DFI_RST_N_BUF, + output [5:0] AXI_12_MC_STATUS, + output [7:0] AXI_12_PHY_STATUS, + output [255:0] AXI_12_RDATA, + output [31:0] AXI_12_RDATA_PARITY, + output [5:0] AXI_12_RID, + output AXI_12_RLAST, + output [1:0] AXI_12_RRESP, + output AXI_12_RVALID, + output AXI_12_WREADY, + output AXI_13_ARREADY, + output AXI_13_AWREADY, + output [5:0] AXI_13_BID, + output [1:0] AXI_13_BRESP, + output AXI_13_BVALID, + output [1:0] AXI_13_DFI_AW_AERR_N, + output AXI_13_DFI_CLK_BUF, + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_13_DFI_DW_RDDATA_DBI, + output [7:0] AXI_13_DFI_DW_RDDATA_DERR, + output [1:0] AXI_13_DFI_DW_RDDATA_VALID, + output AXI_13_DFI_INIT_COMPLETE, + output AXI_13_DFI_PHYUPD_REQ, + output AXI_13_DFI_PHY_LP_STATE, + output AXI_13_DFI_RST_N_BUF, + output [255:0] AXI_13_RDATA, + output [31:0] AXI_13_RDATA_PARITY, + output [5:0] AXI_13_RID, + output AXI_13_RLAST, + output [1:0] AXI_13_RRESP, + output AXI_13_RVALID, + output AXI_13_WREADY, + output AXI_14_ARREADY, + output AXI_14_AWREADY, + output [5:0] AXI_14_BID, + output [1:0] AXI_14_BRESP, + output AXI_14_BVALID, + output [1:0] AXI_14_DFI_AW_AERR_N, + output AXI_14_DFI_CLK_BUF, + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_14_DFI_DW_RDDATA_DBI, + output [7:0] AXI_14_DFI_DW_RDDATA_DERR, + output [1:0] AXI_14_DFI_DW_RDDATA_VALID, + output AXI_14_DFI_INIT_COMPLETE, + output AXI_14_DFI_PHYUPD_REQ, + output AXI_14_DFI_PHY_LP_STATE, + output AXI_14_DFI_RST_N_BUF, + output [5:0] AXI_14_MC_STATUS, + output [7:0] AXI_14_PHY_STATUS, + output [255:0] AXI_14_RDATA, + output [31:0] AXI_14_RDATA_PARITY, + output [5:0] AXI_14_RID, + output AXI_14_RLAST, + output [1:0] AXI_14_RRESP, + output AXI_14_RVALID, + output AXI_14_WREADY, + output AXI_15_ARREADY, + output AXI_15_AWREADY, + output [5:0] AXI_15_BID, + output [1:0] AXI_15_BRESP, + output AXI_15_BVALID, + output [1:0] AXI_15_DFI_AW_AERR_N, + output AXI_15_DFI_CLK_BUF, + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_15_DFI_DW_RDDATA_DBI, + output [7:0] AXI_15_DFI_DW_RDDATA_DERR, + output [1:0] AXI_15_DFI_DW_RDDATA_VALID, + output AXI_15_DFI_INIT_COMPLETE, + output AXI_15_DFI_PHYUPD_REQ, + output AXI_15_DFI_PHY_LP_STATE, + output AXI_15_DFI_RST_N_BUF, + output [255:0] AXI_15_RDATA, + output [31:0] AXI_15_RDATA_PARITY, + output [5:0] AXI_15_RID, + output AXI_15_RLAST, + output [1:0] AXI_15_RRESP, + output AXI_15_RVALID, + output AXI_15_WREADY, + output AXI_16_ARREADY, + output AXI_16_AWREADY, + output [5:0] AXI_16_BID, + output [1:0] AXI_16_BRESP, + output AXI_16_BVALID, + output [1:0] AXI_16_DFI_AW_AERR_N, + output AXI_16_DFI_CLK_BUF, + output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_16_DFI_DW_RDDATA_DBI, + output [7:0] AXI_16_DFI_DW_RDDATA_DERR, + output [1:0] AXI_16_DFI_DW_RDDATA_VALID, + output AXI_16_DFI_INIT_COMPLETE, + output AXI_16_DFI_PHYUPD_REQ, + output AXI_16_DFI_PHY_LP_STATE, + output AXI_16_DFI_RST_N_BUF, + output [5:0] AXI_16_MC_STATUS, + output [7:0] AXI_16_PHY_STATUS, + output [255:0] AXI_16_RDATA, + output [31:0] AXI_16_RDATA_PARITY, + output [5:0] AXI_16_RID, + output AXI_16_RLAST, + output [1:0] AXI_16_RRESP, + output AXI_16_RVALID, + output AXI_16_WREADY, + output AXI_17_ARREADY, + output AXI_17_AWREADY, + output [5:0] AXI_17_BID, + output [1:0] AXI_17_BRESP, + output AXI_17_BVALID, + output [1:0] AXI_17_DFI_AW_AERR_N, + output AXI_17_DFI_CLK_BUF, + output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_17_DFI_DW_RDDATA_DBI, + output [7:0] AXI_17_DFI_DW_RDDATA_DERR, + output [1:0] AXI_17_DFI_DW_RDDATA_VALID, + output AXI_17_DFI_INIT_COMPLETE, + output AXI_17_DFI_PHYUPD_REQ, + output AXI_17_DFI_PHY_LP_STATE, + output AXI_17_DFI_RST_N_BUF, + output [255:0] AXI_17_RDATA, + output [31:0] AXI_17_RDATA_PARITY, + output [5:0] AXI_17_RID, + output AXI_17_RLAST, + output [1:0] AXI_17_RRESP, + output AXI_17_RVALID, + output AXI_17_WREADY, + output AXI_18_ARREADY, + output AXI_18_AWREADY, + output [5:0] AXI_18_BID, + output [1:0] AXI_18_BRESP, + output AXI_18_BVALID, + output [1:0] AXI_18_DFI_AW_AERR_N, + output AXI_18_DFI_CLK_BUF, + output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_18_DFI_DW_RDDATA_DBI, + output [7:0] AXI_18_DFI_DW_RDDATA_DERR, + output [1:0] AXI_18_DFI_DW_RDDATA_VALID, + output AXI_18_DFI_INIT_COMPLETE, + output AXI_18_DFI_PHYUPD_REQ, + output AXI_18_DFI_PHY_LP_STATE, + output AXI_18_DFI_RST_N_BUF, + output [5:0] AXI_18_MC_STATUS, + output [7:0] AXI_18_PHY_STATUS, + output [255:0] AXI_18_RDATA, + output [31:0] AXI_18_RDATA_PARITY, + output [5:0] AXI_18_RID, + output AXI_18_RLAST, + output [1:0] AXI_18_RRESP, + output AXI_18_RVALID, + output AXI_18_WREADY, + output AXI_19_ARREADY, + output AXI_19_AWREADY, + output [5:0] AXI_19_BID, + output [1:0] AXI_19_BRESP, + output AXI_19_BVALID, + output [1:0] AXI_19_DFI_AW_AERR_N, + output AXI_19_DFI_CLK_BUF, + output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_19_DFI_DW_RDDATA_DBI, + output [7:0] AXI_19_DFI_DW_RDDATA_DERR, + output [1:0] AXI_19_DFI_DW_RDDATA_VALID, + output AXI_19_DFI_INIT_COMPLETE, + output AXI_19_DFI_PHYUPD_REQ, + output AXI_19_DFI_PHY_LP_STATE, + output AXI_19_DFI_RST_N_BUF, + output [255:0] AXI_19_RDATA, + output [31:0] AXI_19_RDATA_PARITY, + output [5:0] AXI_19_RID, + output AXI_19_RLAST, + output [1:0] AXI_19_RRESP, + output AXI_19_RVALID, + output AXI_19_WREADY, + output AXI_20_ARREADY, + output AXI_20_AWREADY, + output [5:0] AXI_20_BID, + output [1:0] AXI_20_BRESP, + output AXI_20_BVALID, + output [1:0] AXI_20_DFI_AW_AERR_N, + output AXI_20_DFI_CLK_BUF, + output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_20_DFI_DW_RDDATA_DBI, + output [7:0] AXI_20_DFI_DW_RDDATA_DERR, + output [1:0] AXI_20_DFI_DW_RDDATA_VALID, + output AXI_20_DFI_INIT_COMPLETE, + output AXI_20_DFI_PHYUPD_REQ, + output AXI_20_DFI_PHY_LP_STATE, + output AXI_20_DFI_RST_N_BUF, + output [5:0] AXI_20_MC_STATUS, + output [7:0] AXI_20_PHY_STATUS, + output [255:0] AXI_20_RDATA, + output [31:0] AXI_20_RDATA_PARITY, + output [5:0] AXI_20_RID, + output AXI_20_RLAST, + output [1:0] AXI_20_RRESP, + output AXI_20_RVALID, + output AXI_20_WREADY, + output AXI_21_ARREADY, + output AXI_21_AWREADY, + output [5:0] AXI_21_BID, + output [1:0] AXI_21_BRESP, + output AXI_21_BVALID, + output [1:0] AXI_21_DFI_AW_AERR_N, + output AXI_21_DFI_CLK_BUF, + output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_21_DFI_DW_RDDATA_DBI, + output [7:0] AXI_21_DFI_DW_RDDATA_DERR, + output [1:0] AXI_21_DFI_DW_RDDATA_VALID, + output AXI_21_DFI_INIT_COMPLETE, + output AXI_21_DFI_PHYUPD_REQ, + output AXI_21_DFI_PHY_LP_STATE, + output AXI_21_DFI_RST_N_BUF, + output [255:0] AXI_21_RDATA, + output [31:0] AXI_21_RDATA_PARITY, + output [5:0] AXI_21_RID, + output AXI_21_RLAST, + output [1:0] AXI_21_RRESP, + output AXI_21_RVALID, + output AXI_21_WREADY, + output AXI_22_ARREADY, + output AXI_22_AWREADY, + output [5:0] AXI_22_BID, + output [1:0] AXI_22_BRESP, + output AXI_22_BVALID, + output [1:0] AXI_22_DFI_AW_AERR_N, + output AXI_22_DFI_CLK_BUF, + output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_22_DFI_DW_RDDATA_DBI, + output [7:0] AXI_22_DFI_DW_RDDATA_DERR, + output [1:0] AXI_22_DFI_DW_RDDATA_VALID, + output AXI_22_DFI_INIT_COMPLETE, + output AXI_22_DFI_PHYUPD_REQ, + output AXI_22_DFI_PHY_LP_STATE, + output AXI_22_DFI_RST_N_BUF, + output [5:0] AXI_22_MC_STATUS, + output [7:0] AXI_22_PHY_STATUS, + output [255:0] AXI_22_RDATA, + output [31:0] AXI_22_RDATA_PARITY, + output [5:0] AXI_22_RID, + output AXI_22_RLAST, + output [1:0] AXI_22_RRESP, + output AXI_22_RVALID, + output AXI_22_WREADY, + output AXI_23_ARREADY, + output AXI_23_AWREADY, + output [5:0] AXI_23_BID, + output [1:0] AXI_23_BRESP, + output AXI_23_BVALID, + output [1:0] AXI_23_DFI_AW_AERR_N, + output AXI_23_DFI_CLK_BUF, + output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_23_DFI_DW_RDDATA_DBI, + output [7:0] AXI_23_DFI_DW_RDDATA_DERR, + output [1:0] AXI_23_DFI_DW_RDDATA_VALID, + output AXI_23_DFI_INIT_COMPLETE, + output AXI_23_DFI_PHYUPD_REQ, + output AXI_23_DFI_PHY_LP_STATE, + output AXI_23_DFI_RST_N_BUF, + output [255:0] AXI_23_RDATA, + output [31:0] AXI_23_RDATA_PARITY, + output [5:0] AXI_23_RID, + output AXI_23_RLAST, + output [1:0] AXI_23_RRESP, + output AXI_23_RVALID, + output AXI_23_WREADY, + output AXI_24_ARREADY, + output AXI_24_AWREADY, + output [5:0] AXI_24_BID, + output [1:0] AXI_24_BRESP, + output AXI_24_BVALID, + output [1:0] AXI_24_DFI_AW_AERR_N, + output AXI_24_DFI_CLK_BUF, + output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_24_DFI_DW_RDDATA_DBI, + output [7:0] AXI_24_DFI_DW_RDDATA_DERR, + output [1:0] AXI_24_DFI_DW_RDDATA_VALID, + output AXI_24_DFI_INIT_COMPLETE, + output AXI_24_DFI_PHYUPD_REQ, + output AXI_24_DFI_PHY_LP_STATE, + output AXI_24_DFI_RST_N_BUF, + output [5:0] AXI_24_MC_STATUS, + output [7:0] AXI_24_PHY_STATUS, + output [255:0] AXI_24_RDATA, + output [31:0] AXI_24_RDATA_PARITY, + output [5:0] AXI_24_RID, + output AXI_24_RLAST, + output [1:0] AXI_24_RRESP, + output AXI_24_RVALID, + output AXI_24_WREADY, + output AXI_25_ARREADY, + output AXI_25_AWREADY, + output [5:0] AXI_25_BID, + output [1:0] AXI_25_BRESP, + output AXI_25_BVALID, + output [1:0] AXI_25_DFI_AW_AERR_N, + output AXI_25_DFI_CLK_BUF, + output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_25_DFI_DW_RDDATA_DBI, + output [7:0] AXI_25_DFI_DW_RDDATA_DERR, + output [1:0] AXI_25_DFI_DW_RDDATA_VALID, + output AXI_25_DFI_INIT_COMPLETE, + output AXI_25_DFI_PHYUPD_REQ, + output AXI_25_DFI_PHY_LP_STATE, + output AXI_25_DFI_RST_N_BUF, + output [255:0] AXI_25_RDATA, + output [31:0] AXI_25_RDATA_PARITY, + output [5:0] AXI_25_RID, + output AXI_25_RLAST, + output [1:0] AXI_25_RRESP, + output AXI_25_RVALID, + output AXI_25_WREADY, + output AXI_26_ARREADY, + output AXI_26_AWREADY, + output [5:0] AXI_26_BID, + output [1:0] AXI_26_BRESP, + output AXI_26_BVALID, + output [1:0] AXI_26_DFI_AW_AERR_N, + output AXI_26_DFI_CLK_BUF, + output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_26_DFI_DW_RDDATA_DBI, + output [7:0] AXI_26_DFI_DW_RDDATA_DERR, + output [1:0] AXI_26_DFI_DW_RDDATA_VALID, + output AXI_26_DFI_INIT_COMPLETE, + output AXI_26_DFI_PHYUPD_REQ, + output AXI_26_DFI_PHY_LP_STATE, + output AXI_26_DFI_RST_N_BUF, + output [5:0] AXI_26_MC_STATUS, + output [7:0] AXI_26_PHY_STATUS, + output [255:0] AXI_26_RDATA, + output [31:0] AXI_26_RDATA_PARITY, + output [5:0] AXI_26_RID, + output AXI_26_RLAST, + output [1:0] AXI_26_RRESP, + output AXI_26_RVALID, + output AXI_26_WREADY, + output AXI_27_ARREADY, + output AXI_27_AWREADY, + output [5:0] AXI_27_BID, + output [1:0] AXI_27_BRESP, + output AXI_27_BVALID, + output [1:0] AXI_27_DFI_AW_AERR_N, + output AXI_27_DFI_CLK_BUF, + output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_27_DFI_DW_RDDATA_DBI, + output [7:0] AXI_27_DFI_DW_RDDATA_DERR, + output [1:0] AXI_27_DFI_DW_RDDATA_VALID, + output AXI_27_DFI_INIT_COMPLETE, + output AXI_27_DFI_PHYUPD_REQ, + output AXI_27_DFI_PHY_LP_STATE, + output AXI_27_DFI_RST_N_BUF, + output [255:0] AXI_27_RDATA, + output [31:0] AXI_27_RDATA_PARITY, + output [5:0] AXI_27_RID, + output AXI_27_RLAST, + output [1:0] AXI_27_RRESP, + output AXI_27_RVALID, + output AXI_27_WREADY, + output AXI_28_ARREADY, + output AXI_28_AWREADY, + output [5:0] AXI_28_BID, + output [1:0] AXI_28_BRESP, + output AXI_28_BVALID, + output [1:0] AXI_28_DFI_AW_AERR_N, + output AXI_28_DFI_CLK_BUF, + output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_28_DFI_DW_RDDATA_DBI, + output [7:0] AXI_28_DFI_DW_RDDATA_DERR, + output [1:0] AXI_28_DFI_DW_RDDATA_VALID, + output AXI_28_DFI_INIT_COMPLETE, + output AXI_28_DFI_PHYUPD_REQ, + output AXI_28_DFI_PHY_LP_STATE, + output AXI_28_DFI_RST_N_BUF, + output [5:0] AXI_28_MC_STATUS, + output [7:0] AXI_28_PHY_STATUS, + output [255:0] AXI_28_RDATA, + output [31:0] AXI_28_RDATA_PARITY, + output [5:0] AXI_28_RID, + output AXI_28_RLAST, + output [1:0] AXI_28_RRESP, + output AXI_28_RVALID, + output AXI_28_WREADY, + output AXI_29_ARREADY, + output AXI_29_AWREADY, + output [5:0] AXI_29_BID, + output [1:0] AXI_29_BRESP, + output AXI_29_BVALID, + output [1:0] AXI_29_DFI_AW_AERR_N, + output AXI_29_DFI_CLK_BUF, + output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_29_DFI_DW_RDDATA_DBI, + output [7:0] AXI_29_DFI_DW_RDDATA_DERR, + output [1:0] AXI_29_DFI_DW_RDDATA_VALID, + output AXI_29_DFI_INIT_COMPLETE, + output AXI_29_DFI_PHYUPD_REQ, + output AXI_29_DFI_PHY_LP_STATE, + output AXI_29_DFI_RST_N_BUF, + output [255:0] AXI_29_RDATA, + output [31:0] AXI_29_RDATA_PARITY, + output [5:0] AXI_29_RID, + output AXI_29_RLAST, + output [1:0] AXI_29_RRESP, + output AXI_29_RVALID, + output AXI_29_WREADY, + output AXI_30_ARREADY, + output AXI_30_AWREADY, + output [5:0] AXI_30_BID, + output [1:0] AXI_30_BRESP, + output AXI_30_BVALID, + output [1:0] AXI_30_DFI_AW_AERR_N, + output AXI_30_DFI_CLK_BUF, + output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_30_DFI_DW_RDDATA_DBI, + output [7:0] AXI_30_DFI_DW_RDDATA_DERR, + output [1:0] AXI_30_DFI_DW_RDDATA_VALID, + output AXI_30_DFI_INIT_COMPLETE, + output AXI_30_DFI_PHYUPD_REQ, + output AXI_30_DFI_PHY_LP_STATE, + output AXI_30_DFI_RST_N_BUF, + output [5:0] AXI_30_MC_STATUS, + output [7:0] AXI_30_PHY_STATUS, + output [255:0] AXI_30_RDATA, + output [31:0] AXI_30_RDATA_PARITY, + output [5:0] AXI_30_RID, + output AXI_30_RLAST, + output [1:0] AXI_30_RRESP, + output AXI_30_RVALID, + output AXI_30_WREADY, + output AXI_31_ARREADY, + output AXI_31_AWREADY, + output [5:0] AXI_31_BID, + output [1:0] AXI_31_BRESP, + output AXI_31_BVALID, + output [1:0] AXI_31_DFI_AW_AERR_N, + output AXI_31_DFI_CLK_BUF, + output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE, + output [20:0] AXI_31_DFI_DW_RDDATA_DBI, + output [7:0] AXI_31_DFI_DW_RDDATA_DERR, + output [1:0] AXI_31_DFI_DW_RDDATA_VALID, + output AXI_31_DFI_INIT_COMPLETE, + output AXI_31_DFI_PHYUPD_REQ, + output AXI_31_DFI_PHY_LP_STATE, + output AXI_31_DFI_RST_N_BUF, + output [255:0] AXI_31_RDATA, + output [31:0] AXI_31_RDATA_PARITY, + output [5:0] AXI_31_RID, + output AXI_31_RLAST, + output [1:0] AXI_31_RRESP, + output AXI_31_RVALID, + output AXI_31_WREADY, + output DRAM_0_STAT_CATTRIP, + output [2:0] DRAM_0_STAT_TEMP, + output DRAM_1_STAT_CATTRIP, + output [2:0] DRAM_1_STAT_TEMP, + + input [21:0] APB_0_PADDR, + input APB_0_PCLK, + input APB_0_PENABLE, + input APB_0_PRESET_N, + input APB_0_PSEL, + input [31:0] APB_0_PWDATA, + input APB_0_PWRITE, + input [21:0] APB_1_PADDR, + input APB_1_PCLK, + input APB_1_PENABLE, + input APB_1_PRESET_N, + input APB_1_PSEL, + input [31:0] APB_1_PWDATA, + input APB_1_PWRITE, + input AXI_00_ACLK, + input [36:0] AXI_00_ARADDR, + input [1:0] AXI_00_ARBURST, + input AXI_00_ARESET_N, + input [5:0] AXI_00_ARID, + input [3:0] AXI_00_ARLEN, + input [2:0] AXI_00_ARSIZE, + input AXI_00_ARVALID, + input [36:0] AXI_00_AWADDR, + input [1:0] AXI_00_AWBURST, + input [5:0] AXI_00_AWID, + input [3:0] AXI_00_AWLEN, + input [2:0] AXI_00_AWSIZE, + input AXI_00_AWVALID, + input AXI_00_BREADY, + input AXI_00_DFI_LP_PWR_X_REQ, + input AXI_00_RREADY, + input [255:0] AXI_00_WDATA, + input [31:0] AXI_00_WDATA_PARITY, + input AXI_00_WLAST, + input [31:0] AXI_00_WSTRB, + input AXI_00_WVALID, + input AXI_01_ACLK, + input [36:0] AXI_01_ARADDR, + input [1:0] AXI_01_ARBURST, + input AXI_01_ARESET_N, + input [5:0] AXI_01_ARID, + input [3:0] AXI_01_ARLEN, + input [2:0] AXI_01_ARSIZE, + input AXI_01_ARVALID, + input [36:0] AXI_01_AWADDR, + input [1:0] AXI_01_AWBURST, + input [5:0] AXI_01_AWID, + input [3:0] AXI_01_AWLEN, + input [2:0] AXI_01_AWSIZE, + input AXI_01_AWVALID, + input AXI_01_BREADY, + input AXI_01_DFI_LP_PWR_X_REQ, + input AXI_01_RREADY, + input [255:0] AXI_01_WDATA, + input [31:0] AXI_01_WDATA_PARITY, + input AXI_01_WLAST, + input [31:0] AXI_01_WSTRB, + input AXI_01_WVALID, + input AXI_02_ACLK, + input [36:0] AXI_02_ARADDR, + input [1:0] AXI_02_ARBURST, + input AXI_02_ARESET_N, + input [5:0] AXI_02_ARID, + input [3:0] AXI_02_ARLEN, + input [2:0] AXI_02_ARSIZE, + input AXI_02_ARVALID, + input [36:0] AXI_02_AWADDR, + input [1:0] AXI_02_AWBURST, + input [5:0] AXI_02_AWID, + input [3:0] AXI_02_AWLEN, + input [2:0] AXI_02_AWSIZE, + input AXI_02_AWVALID, + input AXI_02_BREADY, + input AXI_02_DFI_LP_PWR_X_REQ, + input AXI_02_RREADY, + input [255:0] AXI_02_WDATA, + input [31:0] AXI_02_WDATA_PARITY, + input AXI_02_WLAST, + input [31:0] AXI_02_WSTRB, + input AXI_02_WVALID, + input AXI_03_ACLK, + input [36:0] AXI_03_ARADDR, + input [1:0] AXI_03_ARBURST, + input AXI_03_ARESET_N, + input [5:0] AXI_03_ARID, + input [3:0] AXI_03_ARLEN, + input [2:0] AXI_03_ARSIZE, + input AXI_03_ARVALID, + input [36:0] AXI_03_AWADDR, + input [1:0] AXI_03_AWBURST, + input [5:0] AXI_03_AWID, + input [3:0] AXI_03_AWLEN, + input [2:0] AXI_03_AWSIZE, + input AXI_03_AWVALID, + input AXI_03_BREADY, + input AXI_03_DFI_LP_PWR_X_REQ, + input AXI_03_RREADY, + input [255:0] AXI_03_WDATA, + input [31:0] AXI_03_WDATA_PARITY, + input AXI_03_WLAST, + input [31:0] AXI_03_WSTRB, + input AXI_03_WVALID, + input AXI_04_ACLK, + input [36:0] AXI_04_ARADDR, + input [1:0] AXI_04_ARBURST, + input AXI_04_ARESET_N, + input [5:0] AXI_04_ARID, + input [3:0] AXI_04_ARLEN, + input [2:0] AXI_04_ARSIZE, + input AXI_04_ARVALID, + input [36:0] AXI_04_AWADDR, + input [1:0] AXI_04_AWBURST, + input [5:0] AXI_04_AWID, + input [3:0] AXI_04_AWLEN, + input [2:0] AXI_04_AWSIZE, + input AXI_04_AWVALID, + input AXI_04_BREADY, + input AXI_04_DFI_LP_PWR_X_REQ, + input AXI_04_RREADY, + input [255:0] AXI_04_WDATA, + input [31:0] AXI_04_WDATA_PARITY, + input AXI_04_WLAST, + input [31:0] AXI_04_WSTRB, + input AXI_04_WVALID, + input AXI_05_ACLK, + input [36:0] AXI_05_ARADDR, + input [1:0] AXI_05_ARBURST, + input AXI_05_ARESET_N, + input [5:0] AXI_05_ARID, + input [3:0] AXI_05_ARLEN, + input [2:0] AXI_05_ARSIZE, + input AXI_05_ARVALID, + input [36:0] AXI_05_AWADDR, + input [1:0] AXI_05_AWBURST, + input [5:0] AXI_05_AWID, + input [3:0] AXI_05_AWLEN, + input [2:0] AXI_05_AWSIZE, + input AXI_05_AWVALID, + input AXI_05_BREADY, + input AXI_05_DFI_LP_PWR_X_REQ, + input AXI_05_RREADY, + input [255:0] AXI_05_WDATA, + input [31:0] AXI_05_WDATA_PARITY, + input AXI_05_WLAST, + input [31:0] AXI_05_WSTRB, + input AXI_05_WVALID, + input AXI_06_ACLK, + input [36:0] AXI_06_ARADDR, + input [1:0] AXI_06_ARBURST, + input AXI_06_ARESET_N, + input [5:0] AXI_06_ARID, + input [3:0] AXI_06_ARLEN, + input [2:0] AXI_06_ARSIZE, + input AXI_06_ARVALID, + input [36:0] AXI_06_AWADDR, + input [1:0] AXI_06_AWBURST, + input [5:0] AXI_06_AWID, + input [3:0] AXI_06_AWLEN, + input [2:0] AXI_06_AWSIZE, + input AXI_06_AWVALID, + input AXI_06_BREADY, + input AXI_06_DFI_LP_PWR_X_REQ, + input AXI_06_RREADY, + input [255:0] AXI_06_WDATA, + input [31:0] AXI_06_WDATA_PARITY, + input AXI_06_WLAST, + input [31:0] AXI_06_WSTRB, + input AXI_06_WVALID, + input AXI_07_ACLK, + input [36:0] AXI_07_ARADDR, + input [1:0] AXI_07_ARBURST, + input AXI_07_ARESET_N, + input [5:0] AXI_07_ARID, + input [3:0] AXI_07_ARLEN, + input [2:0] AXI_07_ARSIZE, + input AXI_07_ARVALID, + input [36:0] AXI_07_AWADDR, + input [1:0] AXI_07_AWBURST, + input [5:0] AXI_07_AWID, + input [3:0] AXI_07_AWLEN, + input [2:0] AXI_07_AWSIZE, + input AXI_07_AWVALID, + input AXI_07_BREADY, + input AXI_07_DFI_LP_PWR_X_REQ, + input AXI_07_RREADY, + input [255:0] AXI_07_WDATA, + input [31:0] AXI_07_WDATA_PARITY, + input AXI_07_WLAST, + input [31:0] AXI_07_WSTRB, + input AXI_07_WVALID, + input AXI_08_ACLK, + input [36:0] AXI_08_ARADDR, + input [1:0] AXI_08_ARBURST, + input AXI_08_ARESET_N, + input [5:0] AXI_08_ARID, + input [3:0] AXI_08_ARLEN, + input [2:0] AXI_08_ARSIZE, + input AXI_08_ARVALID, + input [36:0] AXI_08_AWADDR, + input [1:0] AXI_08_AWBURST, + input [5:0] AXI_08_AWID, + input [3:0] AXI_08_AWLEN, + input [2:0] AXI_08_AWSIZE, + input AXI_08_AWVALID, + input AXI_08_BREADY, + input AXI_08_DFI_LP_PWR_X_REQ, + input AXI_08_RREADY, + input [255:0] AXI_08_WDATA, + input [31:0] AXI_08_WDATA_PARITY, + input AXI_08_WLAST, + input [31:0] AXI_08_WSTRB, + input AXI_08_WVALID, + input AXI_09_ACLK, + input [36:0] AXI_09_ARADDR, + input [1:0] AXI_09_ARBURST, + input AXI_09_ARESET_N, + input [5:0] AXI_09_ARID, + input [3:0] AXI_09_ARLEN, + input [2:0] AXI_09_ARSIZE, + input AXI_09_ARVALID, + input [36:0] AXI_09_AWADDR, + input [1:0] AXI_09_AWBURST, + input [5:0] AXI_09_AWID, + input [3:0] AXI_09_AWLEN, + input [2:0] AXI_09_AWSIZE, + input AXI_09_AWVALID, + input AXI_09_BREADY, + input AXI_09_DFI_LP_PWR_X_REQ, + input AXI_09_RREADY, + input [255:0] AXI_09_WDATA, + input [31:0] AXI_09_WDATA_PARITY, + input AXI_09_WLAST, + input [31:0] AXI_09_WSTRB, + input AXI_09_WVALID, + input AXI_10_ACLK, + input [36:0] AXI_10_ARADDR, + input [1:0] AXI_10_ARBURST, + input AXI_10_ARESET_N, + input [5:0] AXI_10_ARID, + input [3:0] AXI_10_ARLEN, + input [2:0] AXI_10_ARSIZE, + input AXI_10_ARVALID, + input [36:0] AXI_10_AWADDR, + input [1:0] AXI_10_AWBURST, + input [5:0] AXI_10_AWID, + input [3:0] AXI_10_AWLEN, + input [2:0] AXI_10_AWSIZE, + input AXI_10_AWVALID, + input AXI_10_BREADY, + input AXI_10_DFI_LP_PWR_X_REQ, + input AXI_10_RREADY, + input [255:0] AXI_10_WDATA, + input [31:0] AXI_10_WDATA_PARITY, + input AXI_10_WLAST, + input [31:0] AXI_10_WSTRB, + input AXI_10_WVALID, + input AXI_11_ACLK, + input [36:0] AXI_11_ARADDR, + input [1:0] AXI_11_ARBURST, + input AXI_11_ARESET_N, + input [5:0] AXI_11_ARID, + input [3:0] AXI_11_ARLEN, + input [2:0] AXI_11_ARSIZE, + input AXI_11_ARVALID, + input [36:0] AXI_11_AWADDR, + input [1:0] AXI_11_AWBURST, + input [5:0] AXI_11_AWID, + input [3:0] AXI_11_AWLEN, + input [2:0] AXI_11_AWSIZE, + input AXI_11_AWVALID, + input AXI_11_BREADY, + input AXI_11_DFI_LP_PWR_X_REQ, + input AXI_11_RREADY, + input [255:0] AXI_11_WDATA, + input [31:0] AXI_11_WDATA_PARITY, + input AXI_11_WLAST, + input [31:0] AXI_11_WSTRB, + input AXI_11_WVALID, + input AXI_12_ACLK, + input [36:0] AXI_12_ARADDR, + input [1:0] AXI_12_ARBURST, + input AXI_12_ARESET_N, + input [5:0] AXI_12_ARID, + input [3:0] AXI_12_ARLEN, + input [2:0] AXI_12_ARSIZE, + input AXI_12_ARVALID, + input [36:0] AXI_12_AWADDR, + input [1:0] AXI_12_AWBURST, + input [5:0] AXI_12_AWID, + input [3:0] AXI_12_AWLEN, + input [2:0] AXI_12_AWSIZE, + input AXI_12_AWVALID, + input AXI_12_BREADY, + input AXI_12_DFI_LP_PWR_X_REQ, + input AXI_12_RREADY, + input [255:0] AXI_12_WDATA, + input [31:0] AXI_12_WDATA_PARITY, + input AXI_12_WLAST, + input [31:0] AXI_12_WSTRB, + input AXI_12_WVALID, + input AXI_13_ACLK, + input [36:0] AXI_13_ARADDR, + input [1:0] AXI_13_ARBURST, + input AXI_13_ARESET_N, + input [5:0] AXI_13_ARID, + input [3:0] AXI_13_ARLEN, + input [2:0] AXI_13_ARSIZE, + input AXI_13_ARVALID, + input [36:0] AXI_13_AWADDR, + input [1:0] AXI_13_AWBURST, + input [5:0] AXI_13_AWID, + input [3:0] AXI_13_AWLEN, + input [2:0] AXI_13_AWSIZE, + input AXI_13_AWVALID, + input AXI_13_BREADY, + input AXI_13_DFI_LP_PWR_X_REQ, + input AXI_13_RREADY, + input [255:0] AXI_13_WDATA, + input [31:0] AXI_13_WDATA_PARITY, + input AXI_13_WLAST, + input [31:0] AXI_13_WSTRB, + input AXI_13_WVALID, + input AXI_14_ACLK, + input [36:0] AXI_14_ARADDR, + input [1:0] AXI_14_ARBURST, + input AXI_14_ARESET_N, + input [5:0] AXI_14_ARID, + input [3:0] AXI_14_ARLEN, + input [2:0] AXI_14_ARSIZE, + input AXI_14_ARVALID, + input [36:0] AXI_14_AWADDR, + input [1:0] AXI_14_AWBURST, + input [5:0] AXI_14_AWID, + input [3:0] AXI_14_AWLEN, + input [2:0] AXI_14_AWSIZE, + input AXI_14_AWVALID, + input AXI_14_BREADY, + input AXI_14_DFI_LP_PWR_X_REQ, + input AXI_14_RREADY, + input [255:0] AXI_14_WDATA, + input [31:0] AXI_14_WDATA_PARITY, + input AXI_14_WLAST, + input [31:0] AXI_14_WSTRB, + input AXI_14_WVALID, + input AXI_15_ACLK, + input [36:0] AXI_15_ARADDR, + input [1:0] AXI_15_ARBURST, + input AXI_15_ARESET_N, + input [5:0] AXI_15_ARID, + input [3:0] AXI_15_ARLEN, + input [2:0] AXI_15_ARSIZE, + input AXI_15_ARVALID, + input [36:0] AXI_15_AWADDR, + input [1:0] AXI_15_AWBURST, + input [5:0] AXI_15_AWID, + input [3:0] AXI_15_AWLEN, + input [2:0] AXI_15_AWSIZE, + input AXI_15_AWVALID, + input AXI_15_BREADY, + input AXI_15_DFI_LP_PWR_X_REQ, + input AXI_15_RREADY, + input [255:0] AXI_15_WDATA, + input [31:0] AXI_15_WDATA_PARITY, + input AXI_15_WLAST, + input [31:0] AXI_15_WSTRB, + input AXI_15_WVALID, + input AXI_16_ACLK, + input [36:0] AXI_16_ARADDR, + input [1:0] AXI_16_ARBURST, + input AXI_16_ARESET_N, + input [5:0] AXI_16_ARID, + input [3:0] AXI_16_ARLEN, + input [2:0] AXI_16_ARSIZE, + input AXI_16_ARVALID, + input [36:0] AXI_16_AWADDR, + input [1:0] AXI_16_AWBURST, + input [5:0] AXI_16_AWID, + input [3:0] AXI_16_AWLEN, + input [2:0] AXI_16_AWSIZE, + input AXI_16_AWVALID, + input AXI_16_BREADY, + input AXI_16_DFI_LP_PWR_X_REQ, + input AXI_16_RREADY, + input [255:0] AXI_16_WDATA, + input [31:0] AXI_16_WDATA_PARITY, + input AXI_16_WLAST, + input [31:0] AXI_16_WSTRB, + input AXI_16_WVALID, + input AXI_17_ACLK, + input [36:0] AXI_17_ARADDR, + input [1:0] AXI_17_ARBURST, + input AXI_17_ARESET_N, + input [5:0] AXI_17_ARID, + input [3:0] AXI_17_ARLEN, + input [2:0] AXI_17_ARSIZE, + input AXI_17_ARVALID, + input [36:0] AXI_17_AWADDR, + input [1:0] AXI_17_AWBURST, + input [5:0] AXI_17_AWID, + input [3:0] AXI_17_AWLEN, + input [2:0] AXI_17_AWSIZE, + input AXI_17_AWVALID, + input AXI_17_BREADY, + input AXI_17_DFI_LP_PWR_X_REQ, + input AXI_17_RREADY, + input [255:0] AXI_17_WDATA, + input [31:0] AXI_17_WDATA_PARITY, + input AXI_17_WLAST, + input [31:0] AXI_17_WSTRB, + input AXI_17_WVALID, + input AXI_18_ACLK, + input [36:0] AXI_18_ARADDR, + input [1:0] AXI_18_ARBURST, + input AXI_18_ARESET_N, + input [5:0] AXI_18_ARID, + input [3:0] AXI_18_ARLEN, + input [2:0] AXI_18_ARSIZE, + input AXI_18_ARVALID, + input [36:0] AXI_18_AWADDR, + input [1:0] AXI_18_AWBURST, + input [5:0] AXI_18_AWID, + input [3:0] AXI_18_AWLEN, + input [2:0] AXI_18_AWSIZE, + input AXI_18_AWVALID, + input AXI_18_BREADY, + input AXI_18_DFI_LP_PWR_X_REQ, + input AXI_18_RREADY, + input [255:0] AXI_18_WDATA, + input [31:0] AXI_18_WDATA_PARITY, + input AXI_18_WLAST, + input [31:0] AXI_18_WSTRB, + input AXI_18_WVALID, + input AXI_19_ACLK, + input [36:0] AXI_19_ARADDR, + input [1:0] AXI_19_ARBURST, + input AXI_19_ARESET_N, + input [5:0] AXI_19_ARID, + input [3:0] AXI_19_ARLEN, + input [2:0] AXI_19_ARSIZE, + input AXI_19_ARVALID, + input [36:0] AXI_19_AWADDR, + input [1:0] AXI_19_AWBURST, + input [5:0] AXI_19_AWID, + input [3:0] AXI_19_AWLEN, + input [2:0] AXI_19_AWSIZE, + input AXI_19_AWVALID, + input AXI_19_BREADY, + input AXI_19_DFI_LP_PWR_X_REQ, + input AXI_19_RREADY, + input [255:0] AXI_19_WDATA, + input [31:0] AXI_19_WDATA_PARITY, + input AXI_19_WLAST, + input [31:0] AXI_19_WSTRB, + input AXI_19_WVALID, + input AXI_20_ACLK, + input [36:0] AXI_20_ARADDR, + input [1:0] AXI_20_ARBURST, + input AXI_20_ARESET_N, + input [5:0] AXI_20_ARID, + input [3:0] AXI_20_ARLEN, + input [2:0] AXI_20_ARSIZE, + input AXI_20_ARVALID, + input [36:0] AXI_20_AWADDR, + input [1:0] AXI_20_AWBURST, + input [5:0] AXI_20_AWID, + input [3:0] AXI_20_AWLEN, + input [2:0] AXI_20_AWSIZE, + input AXI_20_AWVALID, + input AXI_20_BREADY, + input AXI_20_DFI_LP_PWR_X_REQ, + input AXI_20_RREADY, + input [255:0] AXI_20_WDATA, + input [31:0] AXI_20_WDATA_PARITY, + input AXI_20_WLAST, + input [31:0] AXI_20_WSTRB, + input AXI_20_WVALID, + input AXI_21_ACLK, + input [36:0] AXI_21_ARADDR, + input [1:0] AXI_21_ARBURST, + input AXI_21_ARESET_N, + input [5:0] AXI_21_ARID, + input [3:0] AXI_21_ARLEN, + input [2:0] AXI_21_ARSIZE, + input AXI_21_ARVALID, + input [36:0] AXI_21_AWADDR, + input [1:0] AXI_21_AWBURST, + input [5:0] AXI_21_AWID, + input [3:0] AXI_21_AWLEN, + input [2:0] AXI_21_AWSIZE, + input AXI_21_AWVALID, + input AXI_21_BREADY, + input AXI_21_DFI_LP_PWR_X_REQ, + input AXI_21_RREADY, + input [255:0] AXI_21_WDATA, + input [31:0] AXI_21_WDATA_PARITY, + input AXI_21_WLAST, + input [31:0] AXI_21_WSTRB, + input AXI_21_WVALID, + input AXI_22_ACLK, + input [36:0] AXI_22_ARADDR, + input [1:0] AXI_22_ARBURST, + input AXI_22_ARESET_N, + input [5:0] AXI_22_ARID, + input [3:0] AXI_22_ARLEN, + input [2:0] AXI_22_ARSIZE, + input AXI_22_ARVALID, + input [36:0] AXI_22_AWADDR, + input [1:0] AXI_22_AWBURST, + input [5:0] AXI_22_AWID, + input [3:0] AXI_22_AWLEN, + input [2:0] AXI_22_AWSIZE, + input AXI_22_AWVALID, + input AXI_22_BREADY, + input AXI_22_DFI_LP_PWR_X_REQ, + input AXI_22_RREADY, + input [255:0] AXI_22_WDATA, + input [31:0] AXI_22_WDATA_PARITY, + input AXI_22_WLAST, + input [31:0] AXI_22_WSTRB, + input AXI_22_WVALID, + input AXI_23_ACLK, + input [36:0] AXI_23_ARADDR, + input [1:0] AXI_23_ARBURST, + input AXI_23_ARESET_N, + input [5:0] AXI_23_ARID, + input [3:0] AXI_23_ARLEN, + input [2:0] AXI_23_ARSIZE, + input AXI_23_ARVALID, + input [36:0] AXI_23_AWADDR, + input [1:0] AXI_23_AWBURST, + input [5:0] AXI_23_AWID, + input [3:0] AXI_23_AWLEN, + input [2:0] AXI_23_AWSIZE, + input AXI_23_AWVALID, + input AXI_23_BREADY, + input AXI_23_DFI_LP_PWR_X_REQ, + input AXI_23_RREADY, + input [255:0] AXI_23_WDATA, + input [31:0] AXI_23_WDATA_PARITY, + input AXI_23_WLAST, + input [31:0] AXI_23_WSTRB, + input AXI_23_WVALID, + input AXI_24_ACLK, + input [36:0] AXI_24_ARADDR, + input [1:0] AXI_24_ARBURST, + input AXI_24_ARESET_N, + input [5:0] AXI_24_ARID, + input [3:0] AXI_24_ARLEN, + input [2:0] AXI_24_ARSIZE, + input AXI_24_ARVALID, + input [36:0] AXI_24_AWADDR, + input [1:0] AXI_24_AWBURST, + input [5:0] AXI_24_AWID, + input [3:0] AXI_24_AWLEN, + input [2:0] AXI_24_AWSIZE, + input AXI_24_AWVALID, + input AXI_24_BREADY, + input AXI_24_DFI_LP_PWR_X_REQ, + input AXI_24_RREADY, + input [255:0] AXI_24_WDATA, + input [31:0] AXI_24_WDATA_PARITY, + input AXI_24_WLAST, + input [31:0] AXI_24_WSTRB, + input AXI_24_WVALID, + input AXI_25_ACLK, + input [36:0] AXI_25_ARADDR, + input [1:0] AXI_25_ARBURST, + input AXI_25_ARESET_N, + input [5:0] AXI_25_ARID, + input [3:0] AXI_25_ARLEN, + input [2:0] AXI_25_ARSIZE, + input AXI_25_ARVALID, + input [36:0] AXI_25_AWADDR, + input [1:0] AXI_25_AWBURST, + input [5:0] AXI_25_AWID, + input [3:0] AXI_25_AWLEN, + input [2:0] AXI_25_AWSIZE, + input AXI_25_AWVALID, + input AXI_25_BREADY, + input AXI_25_DFI_LP_PWR_X_REQ, + input AXI_25_RREADY, + input [255:0] AXI_25_WDATA, + input [31:0] AXI_25_WDATA_PARITY, + input AXI_25_WLAST, + input [31:0] AXI_25_WSTRB, + input AXI_25_WVALID, + input AXI_26_ACLK, + input [36:0] AXI_26_ARADDR, + input [1:0] AXI_26_ARBURST, + input AXI_26_ARESET_N, + input [5:0] AXI_26_ARID, + input [3:0] AXI_26_ARLEN, + input [2:0] AXI_26_ARSIZE, + input AXI_26_ARVALID, + input [36:0] AXI_26_AWADDR, + input [1:0] AXI_26_AWBURST, + input [5:0] AXI_26_AWID, + input [3:0] AXI_26_AWLEN, + input [2:0] AXI_26_AWSIZE, + input AXI_26_AWVALID, + input AXI_26_BREADY, + input AXI_26_DFI_LP_PWR_X_REQ, + input AXI_26_RREADY, + input [255:0] AXI_26_WDATA, + input [31:0] AXI_26_WDATA_PARITY, + input AXI_26_WLAST, + input [31:0] AXI_26_WSTRB, + input AXI_26_WVALID, + input AXI_27_ACLK, + input [36:0] AXI_27_ARADDR, + input [1:0] AXI_27_ARBURST, + input AXI_27_ARESET_N, + input [5:0] AXI_27_ARID, + input [3:0] AXI_27_ARLEN, + input [2:0] AXI_27_ARSIZE, + input AXI_27_ARVALID, + input [36:0] AXI_27_AWADDR, + input [1:0] AXI_27_AWBURST, + input [5:0] AXI_27_AWID, + input [3:0] AXI_27_AWLEN, + input [2:0] AXI_27_AWSIZE, + input AXI_27_AWVALID, + input AXI_27_BREADY, + input AXI_27_DFI_LP_PWR_X_REQ, + input AXI_27_RREADY, + input [255:0] AXI_27_WDATA, + input [31:0] AXI_27_WDATA_PARITY, + input AXI_27_WLAST, + input [31:0] AXI_27_WSTRB, + input AXI_27_WVALID, + input AXI_28_ACLK, + input [36:0] AXI_28_ARADDR, + input [1:0] AXI_28_ARBURST, + input AXI_28_ARESET_N, + input [5:0] AXI_28_ARID, + input [3:0] AXI_28_ARLEN, + input [2:0] AXI_28_ARSIZE, + input AXI_28_ARVALID, + input [36:0] AXI_28_AWADDR, + input [1:0] AXI_28_AWBURST, + input [5:0] AXI_28_AWID, + input [3:0] AXI_28_AWLEN, + input [2:0] AXI_28_AWSIZE, + input AXI_28_AWVALID, + input AXI_28_BREADY, + input AXI_28_DFI_LP_PWR_X_REQ, + input AXI_28_RREADY, + input [255:0] AXI_28_WDATA, + input [31:0] AXI_28_WDATA_PARITY, + input AXI_28_WLAST, + input [31:0] AXI_28_WSTRB, + input AXI_28_WVALID, + input AXI_29_ACLK, + input [36:0] AXI_29_ARADDR, + input [1:0] AXI_29_ARBURST, + input AXI_29_ARESET_N, + input [5:0] AXI_29_ARID, + input [3:0] AXI_29_ARLEN, + input [2:0] AXI_29_ARSIZE, + input AXI_29_ARVALID, + input [36:0] AXI_29_AWADDR, + input [1:0] AXI_29_AWBURST, + input [5:0] AXI_29_AWID, + input [3:0] AXI_29_AWLEN, + input [2:0] AXI_29_AWSIZE, + input AXI_29_AWVALID, + input AXI_29_BREADY, + input AXI_29_DFI_LP_PWR_X_REQ, + input AXI_29_RREADY, + input [255:0] AXI_29_WDATA, + input [31:0] AXI_29_WDATA_PARITY, + input AXI_29_WLAST, + input [31:0] AXI_29_WSTRB, + input AXI_29_WVALID, + input AXI_30_ACLK, + input [36:0] AXI_30_ARADDR, + input [1:0] AXI_30_ARBURST, + input AXI_30_ARESET_N, + input [5:0] AXI_30_ARID, + input [3:0] AXI_30_ARLEN, + input [2:0] AXI_30_ARSIZE, + input AXI_30_ARVALID, + input [36:0] AXI_30_AWADDR, + input [1:0] AXI_30_AWBURST, + input [5:0] AXI_30_AWID, + input [3:0] AXI_30_AWLEN, + input [2:0] AXI_30_AWSIZE, + input AXI_30_AWVALID, + input AXI_30_BREADY, + input AXI_30_DFI_LP_PWR_X_REQ, + input AXI_30_RREADY, + input [255:0] AXI_30_WDATA, + input [31:0] AXI_30_WDATA_PARITY, + input AXI_30_WLAST, + input [31:0] AXI_30_WSTRB, + input AXI_30_WVALID, + input AXI_31_ACLK, + input [36:0] AXI_31_ARADDR, + input [1:0] AXI_31_ARBURST, + input AXI_31_ARESET_N, + input [5:0] AXI_31_ARID, + input [3:0] AXI_31_ARLEN, + input [2:0] AXI_31_ARSIZE, + input AXI_31_ARVALID, + input [36:0] AXI_31_AWADDR, + input [1:0] AXI_31_AWBURST, + input [5:0] AXI_31_AWID, + input [3:0] AXI_31_AWLEN, + input [2:0] AXI_31_AWSIZE, + input AXI_31_AWVALID, + input AXI_31_BREADY, + input AXI_31_DFI_LP_PWR_X_REQ, + input AXI_31_RREADY, + input [255:0] AXI_31_WDATA, + input [31:0] AXI_31_WDATA_PARITY, + input AXI_31_WLAST, + input [31:0] AXI_31_WSTRB, + input AXI_31_WVALID, + input BSCAN_DRCK_0, + input BSCAN_DRCK_1, + input BSCAN_TCK_0, + input BSCAN_TCK_1, + input HBM_REF_CLK_0, + input HBM_REF_CLK_1, + input MBIST_EN_00, + input MBIST_EN_01, + input MBIST_EN_02, + input MBIST_EN_03, + input MBIST_EN_04, + input MBIST_EN_05, + input MBIST_EN_06, + input MBIST_EN_07, + input MBIST_EN_08, + input MBIST_EN_09, + input MBIST_EN_10, + input MBIST_EN_11, + input MBIST_EN_12, + input MBIST_EN_13, + input MBIST_EN_14, + input MBIST_EN_15 +); + +// define constants + localparam MODULE_NAME = "HBM_TWO_STACK_INTF"; + +// Parameter encodings and registers + localparam PHY_PCLK_INVERT_01_FALSE = 0; + localparam PHY_PCLK_INVERT_01_TRUE = 1; + localparam PHY_PCLK_INVERT_02_FALSE = 0; + localparam PHY_PCLK_INVERT_02_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HBM_TWO_STACK_INTF_dr.v" +`else + localparam [40:1] CLK_SEL_00_REG = CLK_SEL_00; + localparam [40:1] CLK_SEL_01_REG = CLK_SEL_01; + localparam [40:1] CLK_SEL_02_REG = CLK_SEL_02; + localparam [40:1] CLK_SEL_03_REG = CLK_SEL_03; + localparam [40:1] CLK_SEL_04_REG = CLK_SEL_04; + localparam [40:1] CLK_SEL_05_REG = CLK_SEL_05; + localparam [40:1] CLK_SEL_06_REG = CLK_SEL_06; + localparam [40:1] CLK_SEL_07_REG = CLK_SEL_07; + localparam [40:1] CLK_SEL_08_REG = CLK_SEL_08; + localparam [40:1] CLK_SEL_09_REG = CLK_SEL_09; + localparam [40:1] CLK_SEL_10_REG = CLK_SEL_10; + localparam [40:1] CLK_SEL_11_REG = CLK_SEL_11; + localparam [40:1] CLK_SEL_12_REG = CLK_SEL_12; + localparam [40:1] CLK_SEL_13_REG = CLK_SEL_13; + localparam [40:1] CLK_SEL_14_REG = CLK_SEL_14; + localparam [40:1] CLK_SEL_15_REG = CLK_SEL_15; + localparam [40:1] CLK_SEL_16_REG = CLK_SEL_16; + localparam [40:1] CLK_SEL_17_REG = CLK_SEL_17; + localparam [40:1] CLK_SEL_18_REG = CLK_SEL_18; + localparam [40:1] CLK_SEL_19_REG = CLK_SEL_19; + localparam [40:1] CLK_SEL_20_REG = CLK_SEL_20; + localparam [40:1] CLK_SEL_21_REG = CLK_SEL_21; + localparam [40:1] CLK_SEL_22_REG = CLK_SEL_22; + localparam [40:1] CLK_SEL_23_REG = CLK_SEL_23; + localparam [40:1] CLK_SEL_24_REG = CLK_SEL_24; + localparam [40:1] CLK_SEL_25_REG = CLK_SEL_25; + localparam [40:1] CLK_SEL_26_REG = CLK_SEL_26; + localparam [40:1] CLK_SEL_27_REG = CLK_SEL_27; + localparam [40:1] CLK_SEL_28_REG = CLK_SEL_28; + localparam [40:1] CLK_SEL_29_REG = CLK_SEL_29; + localparam [40:1] CLK_SEL_30_REG = CLK_SEL_30; + localparam [40:1] CLK_SEL_31_REG = CLK_SEL_31; + localparam [10:0] DATARATE_00_REG = DATARATE_00; + localparam [10:0] DATARATE_01_REG = DATARATE_01; + localparam [10:0] DATARATE_02_REG = DATARATE_02; + localparam [10:0] DATARATE_03_REG = DATARATE_03; + localparam [10:0] DATARATE_04_REG = DATARATE_04; + localparam [10:0] DATARATE_05_REG = DATARATE_05; + localparam [10:0] DATARATE_06_REG = DATARATE_06; + localparam [10:0] DATARATE_07_REG = DATARATE_07; + localparam [10:0] DATARATE_08_REG = DATARATE_08; + localparam [10:0] DATARATE_09_REG = DATARATE_09; + localparam [10:0] DATARATE_10_REG = DATARATE_10; + localparam [10:0] DATARATE_11_REG = DATARATE_11; + localparam [10:0] DATARATE_12_REG = DATARATE_12; + localparam [10:0] DATARATE_13_REG = DATARATE_13; + localparam [10:0] DATARATE_14_REG = DATARATE_14; + localparam [10:0] DATARATE_15_REG = DATARATE_15; + localparam [40:1] DA_LOCKOUT_0_REG = DA_LOCKOUT_0; + localparam [40:1] DA_LOCKOUT_1_REG = DA_LOCKOUT_1; + localparam [0:0] IS_APB_0_PCLK_INVERTED_REG = IS_APB_0_PCLK_INVERTED; + localparam [0:0] IS_APB_0_PRESET_N_INVERTED_REG = IS_APB_0_PRESET_N_INVERTED; + localparam [0:0] IS_APB_1_PCLK_INVERTED_REG = IS_APB_1_PCLK_INVERTED; + localparam [0:0] IS_APB_1_PRESET_N_INVERTED_REG = IS_APB_1_PRESET_N_INVERTED; + localparam [0:0] IS_AXI_00_ACLK_INVERTED_REG = IS_AXI_00_ACLK_INVERTED; + localparam [0:0] IS_AXI_00_ARESET_N_INVERTED_REG = IS_AXI_00_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_01_ACLK_INVERTED_REG = IS_AXI_01_ACLK_INVERTED; + localparam [0:0] IS_AXI_01_ARESET_N_INVERTED_REG = IS_AXI_01_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_02_ACLK_INVERTED_REG = IS_AXI_02_ACLK_INVERTED; + localparam [0:0] IS_AXI_02_ARESET_N_INVERTED_REG = IS_AXI_02_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_03_ACLK_INVERTED_REG = IS_AXI_03_ACLK_INVERTED; + localparam [0:0] IS_AXI_03_ARESET_N_INVERTED_REG = IS_AXI_03_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_04_ACLK_INVERTED_REG = IS_AXI_04_ACLK_INVERTED; + localparam [0:0] IS_AXI_04_ARESET_N_INVERTED_REG = IS_AXI_04_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_05_ACLK_INVERTED_REG = IS_AXI_05_ACLK_INVERTED; + localparam [0:0] IS_AXI_05_ARESET_N_INVERTED_REG = IS_AXI_05_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_06_ACLK_INVERTED_REG = IS_AXI_06_ACLK_INVERTED; + localparam [0:0] IS_AXI_06_ARESET_N_INVERTED_REG = IS_AXI_06_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_07_ACLK_INVERTED_REG = IS_AXI_07_ACLK_INVERTED; + localparam [0:0] IS_AXI_07_ARESET_N_INVERTED_REG = IS_AXI_07_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_08_ACLK_INVERTED_REG = IS_AXI_08_ACLK_INVERTED; + localparam [0:0] IS_AXI_08_ARESET_N_INVERTED_REG = IS_AXI_08_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_09_ACLK_INVERTED_REG = IS_AXI_09_ACLK_INVERTED; + localparam [0:0] IS_AXI_09_ARESET_N_INVERTED_REG = IS_AXI_09_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_10_ACLK_INVERTED_REG = IS_AXI_10_ACLK_INVERTED; + localparam [0:0] IS_AXI_10_ARESET_N_INVERTED_REG = IS_AXI_10_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_11_ACLK_INVERTED_REG = IS_AXI_11_ACLK_INVERTED; + localparam [0:0] IS_AXI_11_ARESET_N_INVERTED_REG = IS_AXI_11_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_12_ACLK_INVERTED_REG = IS_AXI_12_ACLK_INVERTED; + localparam [0:0] IS_AXI_12_ARESET_N_INVERTED_REG = IS_AXI_12_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_13_ACLK_INVERTED_REG = IS_AXI_13_ACLK_INVERTED; + localparam [0:0] IS_AXI_13_ARESET_N_INVERTED_REG = IS_AXI_13_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_14_ACLK_INVERTED_REG = IS_AXI_14_ACLK_INVERTED; + localparam [0:0] IS_AXI_14_ARESET_N_INVERTED_REG = IS_AXI_14_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_15_ACLK_INVERTED_REG = IS_AXI_15_ACLK_INVERTED; + localparam [0:0] IS_AXI_15_ARESET_N_INVERTED_REG = IS_AXI_15_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_16_ACLK_INVERTED_REG = IS_AXI_16_ACLK_INVERTED; + localparam [0:0] IS_AXI_16_ARESET_N_INVERTED_REG = IS_AXI_16_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_17_ACLK_INVERTED_REG = IS_AXI_17_ACLK_INVERTED; + localparam [0:0] IS_AXI_17_ARESET_N_INVERTED_REG = IS_AXI_17_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_18_ACLK_INVERTED_REG = IS_AXI_18_ACLK_INVERTED; + localparam [0:0] IS_AXI_18_ARESET_N_INVERTED_REG = IS_AXI_18_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_19_ACLK_INVERTED_REG = IS_AXI_19_ACLK_INVERTED; + localparam [0:0] IS_AXI_19_ARESET_N_INVERTED_REG = IS_AXI_19_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_20_ACLK_INVERTED_REG = IS_AXI_20_ACLK_INVERTED; + localparam [0:0] IS_AXI_20_ARESET_N_INVERTED_REG = IS_AXI_20_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_21_ACLK_INVERTED_REG = IS_AXI_21_ACLK_INVERTED; + localparam [0:0] IS_AXI_21_ARESET_N_INVERTED_REG = IS_AXI_21_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_22_ACLK_INVERTED_REG = IS_AXI_22_ACLK_INVERTED; + localparam [0:0] IS_AXI_22_ARESET_N_INVERTED_REG = IS_AXI_22_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_23_ACLK_INVERTED_REG = IS_AXI_23_ACLK_INVERTED; + localparam [0:0] IS_AXI_23_ARESET_N_INVERTED_REG = IS_AXI_23_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_24_ACLK_INVERTED_REG = IS_AXI_24_ACLK_INVERTED; + localparam [0:0] IS_AXI_24_ARESET_N_INVERTED_REG = IS_AXI_24_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_25_ACLK_INVERTED_REG = IS_AXI_25_ACLK_INVERTED; + localparam [0:0] IS_AXI_25_ARESET_N_INVERTED_REG = IS_AXI_25_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_26_ACLK_INVERTED_REG = IS_AXI_26_ACLK_INVERTED; + localparam [0:0] IS_AXI_26_ARESET_N_INVERTED_REG = IS_AXI_26_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_27_ACLK_INVERTED_REG = IS_AXI_27_ACLK_INVERTED; + localparam [0:0] IS_AXI_27_ARESET_N_INVERTED_REG = IS_AXI_27_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_28_ACLK_INVERTED_REG = IS_AXI_28_ACLK_INVERTED; + localparam [0:0] IS_AXI_28_ARESET_N_INVERTED_REG = IS_AXI_28_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_29_ACLK_INVERTED_REG = IS_AXI_29_ACLK_INVERTED; + localparam [0:0] IS_AXI_29_ARESET_N_INVERTED_REG = IS_AXI_29_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_30_ACLK_INVERTED_REG = IS_AXI_30_ACLK_INVERTED; + localparam [0:0] IS_AXI_30_ARESET_N_INVERTED_REG = IS_AXI_30_ARESET_N_INVERTED; + localparam [0:0] IS_AXI_31_ACLK_INVERTED_REG = IS_AXI_31_ACLK_INVERTED; + localparam [0:0] IS_AXI_31_ARESET_N_INVERTED_REG = IS_AXI_31_ARESET_N_INVERTED; + localparam [40:1] MC_ENABLE_00_REG = MC_ENABLE_00; + localparam [40:1] MC_ENABLE_01_REG = MC_ENABLE_01; + localparam [40:1] MC_ENABLE_02_REG = MC_ENABLE_02; + localparam [40:1] MC_ENABLE_03_REG = MC_ENABLE_03; + localparam [40:1] MC_ENABLE_04_REG = MC_ENABLE_04; + localparam [40:1] MC_ENABLE_05_REG = MC_ENABLE_05; + localparam [40:1] MC_ENABLE_06_REG = MC_ENABLE_06; + localparam [40:1] MC_ENABLE_07_REG = MC_ENABLE_07; + localparam [40:1] MC_ENABLE_08_REG = MC_ENABLE_08; + localparam [40:1] MC_ENABLE_09_REG = MC_ENABLE_09; + localparam [40:1] MC_ENABLE_10_REG = MC_ENABLE_10; + localparam [40:1] MC_ENABLE_11_REG = MC_ENABLE_11; + localparam [40:1] MC_ENABLE_12_REG = MC_ENABLE_12; + localparam [40:1] MC_ENABLE_13_REG = MC_ENABLE_13; + localparam [40:1] MC_ENABLE_14_REG = MC_ENABLE_14; + localparam [40:1] MC_ENABLE_15_REG = MC_ENABLE_15; + localparam [40:1] MC_ENABLE_APB_00_REG = MC_ENABLE_APB_00; + localparam [40:1] MC_ENABLE_APB_01_REG = MC_ENABLE_APB_01; + localparam [6:0] PAGEHIT_PERCENT_00_REG = PAGEHIT_PERCENT_00; + localparam [6:0] PAGEHIT_PERCENT_01_REG = PAGEHIT_PERCENT_01; + localparam [40:1] PHY_ENABLE_00_REG = PHY_ENABLE_00; + localparam [40:1] PHY_ENABLE_01_REG = PHY_ENABLE_01; + localparam [40:1] PHY_ENABLE_02_REG = PHY_ENABLE_02; + localparam [40:1] PHY_ENABLE_03_REG = PHY_ENABLE_03; + localparam [40:1] PHY_ENABLE_04_REG = PHY_ENABLE_04; + localparam [40:1] PHY_ENABLE_05_REG = PHY_ENABLE_05; + localparam [40:1] PHY_ENABLE_06_REG = PHY_ENABLE_06; + localparam [40:1] PHY_ENABLE_07_REG = PHY_ENABLE_07; + localparam [40:1] PHY_ENABLE_08_REG = PHY_ENABLE_08; + localparam [40:1] PHY_ENABLE_09_REG = PHY_ENABLE_09; + localparam [40:1] PHY_ENABLE_10_REG = PHY_ENABLE_10; + localparam [40:1] PHY_ENABLE_11_REG = PHY_ENABLE_11; + localparam [40:1] PHY_ENABLE_12_REG = PHY_ENABLE_12; + localparam [40:1] PHY_ENABLE_13_REG = PHY_ENABLE_13; + localparam [40:1] PHY_ENABLE_14_REG = PHY_ENABLE_14; + localparam [40:1] PHY_ENABLE_15_REG = PHY_ENABLE_15; + localparam [40:1] PHY_ENABLE_16_REG = PHY_ENABLE_16; + localparam [40:1] PHY_ENABLE_17_REG = PHY_ENABLE_17; + localparam [40:1] PHY_ENABLE_18_REG = PHY_ENABLE_18; + localparam [40:1] PHY_ENABLE_19_REG = PHY_ENABLE_19; + localparam [40:1] PHY_ENABLE_20_REG = PHY_ENABLE_20; + localparam [40:1] PHY_ENABLE_21_REG = PHY_ENABLE_21; + localparam [40:1] PHY_ENABLE_22_REG = PHY_ENABLE_22; + localparam [40:1] PHY_ENABLE_23_REG = PHY_ENABLE_23; + localparam [40:1] PHY_ENABLE_24_REG = PHY_ENABLE_24; + localparam [40:1] PHY_ENABLE_25_REG = PHY_ENABLE_25; + localparam [40:1] PHY_ENABLE_26_REG = PHY_ENABLE_26; + localparam [40:1] PHY_ENABLE_27_REG = PHY_ENABLE_27; + localparam [40:1] PHY_ENABLE_28_REG = PHY_ENABLE_28; + localparam [40:1] PHY_ENABLE_29_REG = PHY_ENABLE_29; + localparam [40:1] PHY_ENABLE_30_REG = PHY_ENABLE_30; + localparam [40:1] PHY_ENABLE_31_REG = PHY_ENABLE_31; + localparam [40:1] PHY_ENABLE_APB_00_REG = PHY_ENABLE_APB_00; + localparam [40:1] PHY_ENABLE_APB_01_REG = PHY_ENABLE_APB_01; + localparam [40:1] PHY_PCLK_INVERT_01_REG = PHY_PCLK_INVERT_01; + localparam [40:1] PHY_PCLK_INVERT_02_REG = PHY_PCLK_INVERT_02; + localparam [6:0] READ_PERCENT_00_REG = READ_PERCENT_00; + localparam [6:0] READ_PERCENT_01_REG = READ_PERCENT_01; + localparam [6:0] READ_PERCENT_02_REG = READ_PERCENT_02; + localparam [6:0] READ_PERCENT_03_REG = READ_PERCENT_03; + localparam [6:0] READ_PERCENT_04_REG = READ_PERCENT_04; + localparam [6:0] READ_PERCENT_05_REG = READ_PERCENT_05; + localparam [6:0] READ_PERCENT_06_REG = READ_PERCENT_06; + localparam [6:0] READ_PERCENT_07_REG = READ_PERCENT_07; + localparam [6:0] READ_PERCENT_08_REG = READ_PERCENT_08; + localparam [6:0] READ_PERCENT_09_REG = READ_PERCENT_09; + localparam [6:0] READ_PERCENT_10_REG = READ_PERCENT_10; + localparam [6:0] READ_PERCENT_11_REG = READ_PERCENT_11; + localparam [6:0] READ_PERCENT_12_REG = READ_PERCENT_12; + localparam [6:0] READ_PERCENT_13_REG = READ_PERCENT_13; + localparam [6:0] READ_PERCENT_14_REG = READ_PERCENT_14; + localparam [6:0] READ_PERCENT_15_REG = READ_PERCENT_15; + localparam [6:0] READ_PERCENT_16_REG = READ_PERCENT_16; + localparam [6:0] READ_PERCENT_17_REG = READ_PERCENT_17; + localparam [6:0] READ_PERCENT_18_REG = READ_PERCENT_18; + localparam [6:0] READ_PERCENT_19_REG = READ_PERCENT_19; + localparam [6:0] READ_PERCENT_20_REG = READ_PERCENT_20; + localparam [6:0] READ_PERCENT_21_REG = READ_PERCENT_21; + localparam [6:0] READ_PERCENT_22_REG = READ_PERCENT_22; + localparam [6:0] READ_PERCENT_23_REG = READ_PERCENT_23; + localparam [6:0] READ_PERCENT_24_REG = READ_PERCENT_24; + localparam [6:0] READ_PERCENT_25_REG = READ_PERCENT_25; + localparam [6:0] READ_PERCENT_26_REG = READ_PERCENT_26; + localparam [6:0] READ_PERCENT_27_REG = READ_PERCENT_27; + localparam [6:0] READ_PERCENT_28_REG = READ_PERCENT_28; + localparam [6:0] READ_PERCENT_29_REG = READ_PERCENT_29; + localparam [6:0] READ_PERCENT_30_REG = READ_PERCENT_30; + localparam [6:0] READ_PERCENT_31_REG = READ_PERCENT_31; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [40:1] SWITCH_ENABLE_00_REG = SWITCH_ENABLE_00; + localparam [40:1] SWITCH_ENABLE_01_REG = SWITCH_ENABLE_01; + localparam [6:0] WRITE_PERCENT_00_REG = WRITE_PERCENT_00; + localparam [6:0] WRITE_PERCENT_01_REG = WRITE_PERCENT_01; + localparam [6:0] WRITE_PERCENT_02_REG = WRITE_PERCENT_02; + localparam [6:0] WRITE_PERCENT_03_REG = WRITE_PERCENT_03; + localparam [6:0] WRITE_PERCENT_04_REG = WRITE_PERCENT_04; + localparam [6:0] WRITE_PERCENT_05_REG = WRITE_PERCENT_05; + localparam [6:0] WRITE_PERCENT_06_REG = WRITE_PERCENT_06; + localparam [6:0] WRITE_PERCENT_07_REG = WRITE_PERCENT_07; + localparam [6:0] WRITE_PERCENT_08_REG = WRITE_PERCENT_08; + localparam [6:0] WRITE_PERCENT_09_REG = WRITE_PERCENT_09; + localparam [6:0] WRITE_PERCENT_10_REG = WRITE_PERCENT_10; + localparam [6:0] WRITE_PERCENT_11_REG = WRITE_PERCENT_11; + localparam [6:0] WRITE_PERCENT_12_REG = WRITE_PERCENT_12; + localparam [6:0] WRITE_PERCENT_13_REG = WRITE_PERCENT_13; + localparam [6:0] WRITE_PERCENT_14_REG = WRITE_PERCENT_14; + localparam [6:0] WRITE_PERCENT_15_REG = WRITE_PERCENT_15; + localparam [6:0] WRITE_PERCENT_16_REG = WRITE_PERCENT_16; + localparam [6:0] WRITE_PERCENT_17_REG = WRITE_PERCENT_17; + localparam [6:0] WRITE_PERCENT_18_REG = WRITE_PERCENT_18; + localparam [6:0] WRITE_PERCENT_19_REG = WRITE_PERCENT_19; + localparam [6:0] WRITE_PERCENT_20_REG = WRITE_PERCENT_20; + localparam [6:0] WRITE_PERCENT_21_REG = WRITE_PERCENT_21; + localparam [6:0] WRITE_PERCENT_22_REG = WRITE_PERCENT_22; + localparam [6:0] WRITE_PERCENT_23_REG = WRITE_PERCENT_23; + localparam [6:0] WRITE_PERCENT_24_REG = WRITE_PERCENT_24; + localparam [6:0] WRITE_PERCENT_25_REG = WRITE_PERCENT_25; + localparam [6:0] WRITE_PERCENT_26_REG = WRITE_PERCENT_26; + localparam [6:0] WRITE_PERCENT_27_REG = WRITE_PERCENT_27; + localparam [6:0] WRITE_PERCENT_28_REG = WRITE_PERCENT_28; + localparam [6:0] WRITE_PERCENT_29_REG = WRITE_PERCENT_29; + localparam [6:0] WRITE_PERCENT_30_REG = WRITE_PERCENT_30; + localparam [6:0] WRITE_PERCENT_31_REG = WRITE_PERCENT_31; +`endif + + localparam [7:0] ANALOG_MUX_SEL_0_REG = 8'h00; + localparam [7:0] ANALOG_MUX_SEL_1_REG = 8'h00; + localparam [40:1] APB_BYPASS_EN_0_REG = "FALSE"; + localparam [40:1] APB_BYPASS_EN_1_REG = "FALSE"; + localparam [40:1] AXI_BYPASS_EN_0_REG = "FALSE"; + localparam [40:1] AXI_BYPASS_EN_1_REG = "FALSE"; + localparam [40:1] BLI_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] BLI_TESTMODE_SEL_1_REG = "FALSE"; + localparam [51:0] DBG_BYPASS_VAL_0_REG = 52'hFFFFFFFFFFFFF; + localparam [51:0] DBG_BYPASS_VAL_1_REG = 52'hFFFFFFFFFFFFF; + localparam [40:1] DEBUG_MODE_0_REG = "FALSE"; + localparam [40:1] DEBUG_MODE_1_REG = "FALSE"; + localparam [51:0] DFI_BYPASS_VAL_0_REG = 52'h0000000000000; + localparam [51:0] DFI_BYPASS_VAL_1_REG = 52'h0000000000000; + localparam [40:1] DLL_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] DLL_TESTMODE_SEL_1_REG = "FALSE"; + localparam [40:1] IO_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] IO_TESTMODE_SEL_1_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_0_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_1_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_10_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_11_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_12_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_13_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_14_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_15_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_2_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_3_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_4_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_5_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_6_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_7_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_8_REG = "FALSE"; + localparam [40:1] MC_CSSD_SEL_9_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_1_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_10_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_11_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_12_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_13_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_14_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_15_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_2_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_3_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_4_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_5_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_6_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_7_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_8_REG = "FALSE"; + localparam [40:1] MC_TESTMODE_SEL_9_REG = "FALSE"; + localparam [40:1] PHY_CSSD_SEL_0_REG = "FALSE"; + localparam [40:1] PHY_CSSD_SEL_1_REG = "FALSE"; + localparam [40:1] PHY_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] PHY_TESTMODE_SEL_1_REG = "FALSE"; + localparam [40:1] SWITCH_ENABLE_0_REG = "FALSE"; + localparam [40:1] SWITCH_ENABLE_1_REG = "FALSE"; + localparam [40:1] SW_TESTMODE_SEL_0_REG = "FALSE"; + localparam [40:1] SW_TESTMODE_SEL_1_REG = "FALSE"; + +`ifdef XIL_XECLIB + wire PHY_PCLK_INVERT_01_BIN; + wire PHY_PCLK_INVERT_02_BIN; +`else + reg PHY_PCLK_INVERT_01_BIN; + reg PHY_PCLK_INVERT_02_BIN; +`endif + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire APB_0_PREADY_out; + wire APB_0_PSLVERR_out; + wire APB_1_PREADY_out; + wire APB_1_PSLVERR_out; + wire AXI_00_ARREADY_out; + wire AXI_00_AWREADY_out; + wire AXI_00_BVALID_out; + wire AXI_00_DFI_CLK_BUF_out; + wire AXI_00_DFI_INIT_COMPLETE_out; + wire AXI_00_DFI_PHYUPD_REQ_out; + wire AXI_00_DFI_PHY_LP_STATE_out; + wire AXI_00_DFI_RST_N_BUF_out; + wire AXI_00_RLAST_out; + wire AXI_00_RVALID_out; + wire AXI_00_WREADY_out; + wire AXI_01_ARREADY_out; + wire AXI_01_AWREADY_out; + wire AXI_01_BVALID_out; + wire AXI_01_DFI_CLK_BUF_out; + wire AXI_01_DFI_INIT_COMPLETE_out; + wire AXI_01_DFI_PHYUPD_REQ_out; + wire AXI_01_DFI_PHY_LP_STATE_out; + wire AXI_01_DFI_RST_N_BUF_out; + wire AXI_01_RLAST_out; + wire AXI_01_RVALID_out; + wire AXI_01_WREADY_out; + wire AXI_02_ARREADY_out; + wire AXI_02_AWREADY_out; + wire AXI_02_BVALID_out; + wire AXI_02_DFI_CLK_BUF_out; + wire AXI_02_DFI_INIT_COMPLETE_out; + wire AXI_02_DFI_PHYUPD_REQ_out; + wire AXI_02_DFI_PHY_LP_STATE_out; + wire AXI_02_DFI_RST_N_BUF_out; + wire AXI_02_RLAST_out; + wire AXI_02_RVALID_out; + wire AXI_02_WREADY_out; + wire AXI_03_ARREADY_out; + wire AXI_03_AWREADY_out; + wire AXI_03_BVALID_out; + wire AXI_03_DFI_CLK_BUF_out; + wire AXI_03_DFI_INIT_COMPLETE_out; + wire AXI_03_DFI_PHYUPD_REQ_out; + wire AXI_03_DFI_PHY_LP_STATE_out; + wire AXI_03_DFI_RST_N_BUF_out; + wire AXI_03_RLAST_out; + wire AXI_03_RVALID_out; + wire AXI_03_WREADY_out; + wire AXI_04_ARREADY_out; + wire AXI_04_AWREADY_out; + wire AXI_04_BVALID_out; + wire AXI_04_DFI_CLK_BUF_out; + wire AXI_04_DFI_INIT_COMPLETE_out; + wire AXI_04_DFI_PHYUPD_REQ_out; + wire AXI_04_DFI_PHY_LP_STATE_out; + wire AXI_04_DFI_RST_N_BUF_out; + wire AXI_04_RLAST_out; + wire AXI_04_RVALID_out; + wire AXI_04_WREADY_out; + wire AXI_05_ARREADY_out; + wire AXI_05_AWREADY_out; + wire AXI_05_BVALID_out; + wire AXI_05_DFI_CLK_BUF_out; + wire AXI_05_DFI_INIT_COMPLETE_out; + wire AXI_05_DFI_PHYUPD_REQ_out; + wire AXI_05_DFI_PHY_LP_STATE_out; + wire AXI_05_DFI_RST_N_BUF_out; + wire AXI_05_RLAST_out; + wire AXI_05_RVALID_out; + wire AXI_05_WREADY_out; + wire AXI_06_ARREADY_out; + wire AXI_06_AWREADY_out; + wire AXI_06_BVALID_out; + wire AXI_06_DFI_CLK_BUF_out; + wire AXI_06_DFI_INIT_COMPLETE_out; + wire AXI_06_DFI_PHYUPD_REQ_out; + wire AXI_06_DFI_PHY_LP_STATE_out; + wire AXI_06_DFI_RST_N_BUF_out; + wire AXI_06_RLAST_out; + wire AXI_06_RVALID_out; + wire AXI_06_WREADY_out; + wire AXI_07_ARREADY_out; + wire AXI_07_AWREADY_out; + wire AXI_07_BVALID_out; + wire AXI_07_DFI_CLK_BUF_out; + wire AXI_07_DFI_INIT_COMPLETE_out; + wire AXI_07_DFI_PHYUPD_REQ_out; + wire AXI_07_DFI_PHY_LP_STATE_out; + wire AXI_07_DFI_RST_N_BUF_out; + wire AXI_07_RLAST_out; + wire AXI_07_RVALID_out; + wire AXI_07_WREADY_out; + wire AXI_08_ARREADY_out; + wire AXI_08_AWREADY_out; + wire AXI_08_BVALID_out; + wire AXI_08_DFI_CLK_BUF_out; + wire AXI_08_DFI_INIT_COMPLETE_out; + wire AXI_08_DFI_PHYUPD_REQ_out; + wire AXI_08_DFI_PHY_LP_STATE_out; + wire AXI_08_DFI_RST_N_BUF_out; + wire AXI_08_RLAST_out; + wire AXI_08_RVALID_out; + wire AXI_08_WREADY_out; + wire AXI_09_ARREADY_out; + wire AXI_09_AWREADY_out; + wire AXI_09_BVALID_out; + wire AXI_09_DFI_CLK_BUF_out; + wire AXI_09_DFI_INIT_COMPLETE_out; + wire AXI_09_DFI_PHYUPD_REQ_out; + wire AXI_09_DFI_PHY_LP_STATE_out; + wire AXI_09_DFI_RST_N_BUF_out; + wire AXI_09_RLAST_out; + wire AXI_09_RVALID_out; + wire AXI_09_WREADY_out; + wire AXI_10_ARREADY_out; + wire AXI_10_AWREADY_out; + wire AXI_10_BVALID_out; + wire AXI_10_DFI_CLK_BUF_out; + wire AXI_10_DFI_INIT_COMPLETE_out; + wire AXI_10_DFI_PHYUPD_REQ_out; + wire AXI_10_DFI_PHY_LP_STATE_out; + wire AXI_10_DFI_RST_N_BUF_out; + wire AXI_10_RLAST_out; + wire AXI_10_RVALID_out; + wire AXI_10_WREADY_out; + wire AXI_11_ARREADY_out; + wire AXI_11_AWREADY_out; + wire AXI_11_BVALID_out; + wire AXI_11_DFI_CLK_BUF_out; + wire AXI_11_DFI_INIT_COMPLETE_out; + wire AXI_11_DFI_PHYUPD_REQ_out; + wire AXI_11_DFI_PHY_LP_STATE_out; + wire AXI_11_DFI_RST_N_BUF_out; + wire AXI_11_RLAST_out; + wire AXI_11_RVALID_out; + wire AXI_11_WREADY_out; + wire AXI_12_ARREADY_out; + wire AXI_12_AWREADY_out; + wire AXI_12_BVALID_out; + wire AXI_12_DFI_CLK_BUF_out; + wire AXI_12_DFI_INIT_COMPLETE_out; + wire AXI_12_DFI_PHYUPD_REQ_out; + wire AXI_12_DFI_PHY_LP_STATE_out; + wire AXI_12_DFI_RST_N_BUF_out; + wire AXI_12_RLAST_out; + wire AXI_12_RVALID_out; + wire AXI_12_WREADY_out; + wire AXI_13_ARREADY_out; + wire AXI_13_AWREADY_out; + wire AXI_13_BVALID_out; + wire AXI_13_DFI_CLK_BUF_out; + wire AXI_13_DFI_INIT_COMPLETE_out; + wire AXI_13_DFI_PHYUPD_REQ_out; + wire AXI_13_DFI_PHY_LP_STATE_out; + wire AXI_13_DFI_RST_N_BUF_out; + wire AXI_13_RLAST_out; + wire AXI_13_RVALID_out; + wire AXI_13_WREADY_out; + wire AXI_14_ARREADY_out; + wire AXI_14_AWREADY_out; + wire AXI_14_BVALID_out; + wire AXI_14_DFI_CLK_BUF_out; + wire AXI_14_DFI_INIT_COMPLETE_out; + wire AXI_14_DFI_PHYUPD_REQ_out; + wire AXI_14_DFI_PHY_LP_STATE_out; + wire AXI_14_DFI_RST_N_BUF_out; + wire AXI_14_RLAST_out; + wire AXI_14_RVALID_out; + wire AXI_14_WREADY_out; + wire AXI_15_ARREADY_out; + wire AXI_15_AWREADY_out; + wire AXI_15_BVALID_out; + wire AXI_15_DFI_CLK_BUF_out; + wire AXI_15_DFI_INIT_COMPLETE_out; + wire AXI_15_DFI_PHYUPD_REQ_out; + wire AXI_15_DFI_PHY_LP_STATE_out; + wire AXI_15_DFI_RST_N_BUF_out; + wire AXI_15_RLAST_out; + wire AXI_15_RVALID_out; + wire AXI_15_WREADY_out; + wire AXI_16_ARREADY_out; + wire AXI_16_AWREADY_out; + wire AXI_16_BVALID_out; + wire AXI_16_DFI_CLK_BUF_out; + wire AXI_16_DFI_INIT_COMPLETE_out; + wire AXI_16_DFI_PHYUPD_REQ_out; + wire AXI_16_DFI_PHY_LP_STATE_out; + wire AXI_16_DFI_RST_N_BUF_out; + wire AXI_16_RLAST_out; + wire AXI_16_RVALID_out; + wire AXI_16_WREADY_out; + wire AXI_17_ARREADY_out; + wire AXI_17_AWREADY_out; + wire AXI_17_BVALID_out; + wire AXI_17_DFI_CLK_BUF_out; + wire AXI_17_DFI_INIT_COMPLETE_out; + wire AXI_17_DFI_PHYUPD_REQ_out; + wire AXI_17_DFI_PHY_LP_STATE_out; + wire AXI_17_DFI_RST_N_BUF_out; + wire AXI_17_RLAST_out; + wire AXI_17_RVALID_out; + wire AXI_17_WREADY_out; + wire AXI_18_ARREADY_out; + wire AXI_18_AWREADY_out; + wire AXI_18_BVALID_out; + wire AXI_18_DFI_CLK_BUF_out; + wire AXI_18_DFI_INIT_COMPLETE_out; + wire AXI_18_DFI_PHYUPD_REQ_out; + wire AXI_18_DFI_PHY_LP_STATE_out; + wire AXI_18_DFI_RST_N_BUF_out; + wire AXI_18_RLAST_out; + wire AXI_18_RVALID_out; + wire AXI_18_WREADY_out; + wire AXI_19_ARREADY_out; + wire AXI_19_AWREADY_out; + wire AXI_19_BVALID_out; + wire AXI_19_DFI_CLK_BUF_out; + wire AXI_19_DFI_INIT_COMPLETE_out; + wire AXI_19_DFI_PHYUPD_REQ_out; + wire AXI_19_DFI_PHY_LP_STATE_out; + wire AXI_19_DFI_RST_N_BUF_out; + wire AXI_19_RLAST_out; + wire AXI_19_RVALID_out; + wire AXI_19_WREADY_out; + wire AXI_20_ARREADY_out; + wire AXI_20_AWREADY_out; + wire AXI_20_BVALID_out; + wire AXI_20_DFI_CLK_BUF_out; + wire AXI_20_DFI_INIT_COMPLETE_out; + wire AXI_20_DFI_PHYUPD_REQ_out; + wire AXI_20_DFI_PHY_LP_STATE_out; + wire AXI_20_DFI_RST_N_BUF_out; + wire AXI_20_RLAST_out; + wire AXI_20_RVALID_out; + wire AXI_20_WREADY_out; + wire AXI_21_ARREADY_out; + wire AXI_21_AWREADY_out; + wire AXI_21_BVALID_out; + wire AXI_21_DFI_CLK_BUF_out; + wire AXI_21_DFI_INIT_COMPLETE_out; + wire AXI_21_DFI_PHYUPD_REQ_out; + wire AXI_21_DFI_PHY_LP_STATE_out; + wire AXI_21_DFI_RST_N_BUF_out; + wire AXI_21_RLAST_out; + wire AXI_21_RVALID_out; + wire AXI_21_WREADY_out; + wire AXI_22_ARREADY_out; + wire AXI_22_AWREADY_out; + wire AXI_22_BVALID_out; + wire AXI_22_DFI_CLK_BUF_out; + wire AXI_22_DFI_INIT_COMPLETE_out; + wire AXI_22_DFI_PHYUPD_REQ_out; + wire AXI_22_DFI_PHY_LP_STATE_out; + wire AXI_22_DFI_RST_N_BUF_out; + wire AXI_22_RLAST_out; + wire AXI_22_RVALID_out; + wire AXI_22_WREADY_out; + wire AXI_23_ARREADY_out; + wire AXI_23_AWREADY_out; + wire AXI_23_BVALID_out; + wire AXI_23_DFI_CLK_BUF_out; + wire AXI_23_DFI_INIT_COMPLETE_out; + wire AXI_23_DFI_PHYUPD_REQ_out; + wire AXI_23_DFI_PHY_LP_STATE_out; + wire AXI_23_DFI_RST_N_BUF_out; + wire AXI_23_RLAST_out; + wire AXI_23_RVALID_out; + wire AXI_23_WREADY_out; + wire AXI_24_ARREADY_out; + wire AXI_24_AWREADY_out; + wire AXI_24_BVALID_out; + wire AXI_24_DFI_CLK_BUF_out; + wire AXI_24_DFI_INIT_COMPLETE_out; + wire AXI_24_DFI_PHYUPD_REQ_out; + wire AXI_24_DFI_PHY_LP_STATE_out; + wire AXI_24_DFI_RST_N_BUF_out; + wire AXI_24_RLAST_out; + wire AXI_24_RVALID_out; + wire AXI_24_WREADY_out; + wire AXI_25_ARREADY_out; + wire AXI_25_AWREADY_out; + wire AXI_25_BVALID_out; + wire AXI_25_DFI_CLK_BUF_out; + wire AXI_25_DFI_INIT_COMPLETE_out; + wire AXI_25_DFI_PHYUPD_REQ_out; + wire AXI_25_DFI_PHY_LP_STATE_out; + wire AXI_25_DFI_RST_N_BUF_out; + wire AXI_25_RLAST_out; + wire AXI_25_RVALID_out; + wire AXI_25_WREADY_out; + wire AXI_26_ARREADY_out; + wire AXI_26_AWREADY_out; + wire AXI_26_BVALID_out; + wire AXI_26_DFI_CLK_BUF_out; + wire AXI_26_DFI_INIT_COMPLETE_out; + wire AXI_26_DFI_PHYUPD_REQ_out; + wire AXI_26_DFI_PHY_LP_STATE_out; + wire AXI_26_DFI_RST_N_BUF_out; + wire AXI_26_RLAST_out; + wire AXI_26_RVALID_out; + wire AXI_26_WREADY_out; + wire AXI_27_ARREADY_out; + wire AXI_27_AWREADY_out; + wire AXI_27_BVALID_out; + wire AXI_27_DFI_CLK_BUF_out; + wire AXI_27_DFI_INIT_COMPLETE_out; + wire AXI_27_DFI_PHYUPD_REQ_out; + wire AXI_27_DFI_PHY_LP_STATE_out; + wire AXI_27_DFI_RST_N_BUF_out; + wire AXI_27_RLAST_out; + wire AXI_27_RVALID_out; + wire AXI_27_WREADY_out; + wire AXI_28_ARREADY_out; + wire AXI_28_AWREADY_out; + wire AXI_28_BVALID_out; + wire AXI_28_DFI_CLK_BUF_out; + wire AXI_28_DFI_INIT_COMPLETE_out; + wire AXI_28_DFI_PHYUPD_REQ_out; + wire AXI_28_DFI_PHY_LP_STATE_out; + wire AXI_28_DFI_RST_N_BUF_out; + wire AXI_28_RLAST_out; + wire AXI_28_RVALID_out; + wire AXI_28_WREADY_out; + wire AXI_29_ARREADY_out; + wire AXI_29_AWREADY_out; + wire AXI_29_BVALID_out; + wire AXI_29_DFI_CLK_BUF_out; + wire AXI_29_DFI_INIT_COMPLETE_out; + wire AXI_29_DFI_PHYUPD_REQ_out; + wire AXI_29_DFI_PHY_LP_STATE_out; + wire AXI_29_DFI_RST_N_BUF_out; + wire AXI_29_RLAST_out; + wire AXI_29_RVALID_out; + wire AXI_29_WREADY_out; + wire AXI_30_ARREADY_out; + wire AXI_30_AWREADY_out; + wire AXI_30_BVALID_out; + wire AXI_30_DFI_CLK_BUF_out; + wire AXI_30_DFI_INIT_COMPLETE_out; + wire AXI_30_DFI_PHYUPD_REQ_out; + wire AXI_30_DFI_PHY_LP_STATE_out; + wire AXI_30_DFI_RST_N_BUF_out; + wire AXI_30_RLAST_out; + wire AXI_30_RVALID_out; + wire AXI_30_WREADY_out; + wire AXI_31_ARREADY_out; + wire AXI_31_AWREADY_out; + wire AXI_31_BVALID_out; + wire AXI_31_DFI_CLK_BUF_out; + wire AXI_31_DFI_INIT_COMPLETE_out; + wire AXI_31_DFI_PHYUPD_REQ_out; + wire AXI_31_DFI_PHY_LP_STATE_out; + wire AXI_31_DFI_RST_N_BUF_out; + wire AXI_31_RLAST_out; + wire AXI_31_RVALID_out; + wire AXI_31_WREADY_out; + wire DRAM_0_STAT_CATTRIP_out; + wire DRAM_1_STAT_CATTRIP_out; + wire [17:0] DBG_OUT_00_out; + wire [17:0] DBG_OUT_01_out; + wire [17:0] DBG_OUT_02_out; + wire [17:0] DBG_OUT_03_out; + wire [17:0] DBG_OUT_04_out; + wire [17:0] DBG_OUT_05_out; + wire [17:0] DBG_OUT_06_out; + wire [17:0] DBG_OUT_07_out; + wire [17:0] DBG_OUT_08_out; + wire [17:0] DBG_OUT_09_out; + wire [17:0] DBG_OUT_10_out; + wire [17:0] DBG_OUT_11_out; + wire [17:0] DBG_OUT_12_out; + wire [17:0] DBG_OUT_13_out; + wire [17:0] DBG_OUT_14_out; + wire [17:0] DBG_OUT_15_out; + wire [17:0] DBG_OUT_16_out; + wire [17:0] DBG_OUT_17_out; + wire [17:0] DBG_OUT_18_out; + wire [17:0] DBG_OUT_19_out; + wire [17:0] DBG_OUT_20_out; + wire [17:0] DBG_OUT_21_out; + wire [17:0] DBG_OUT_22_out; + wire [17:0] DBG_OUT_23_out; + wire [17:0] DBG_OUT_24_out; + wire [17:0] DBG_OUT_25_out; + wire [17:0] DBG_OUT_26_out; + wire [17:0] DBG_OUT_27_out; + wire [17:0] DBG_OUT_28_out; + wire [17:0] DBG_OUT_29_out; + wire [17:0] DBG_OUT_30_out; + wire [17:0] DBG_OUT_31_out; + wire [1:0] AXI_00_BRESP_out; + wire [1:0] AXI_00_DFI_AW_AERR_N_out; + wire [1:0] AXI_00_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_00_RRESP_out; + wire [1:0] AXI_01_BRESP_out; + wire [1:0] AXI_01_DFI_AW_AERR_N_out; + wire [1:0] AXI_01_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_01_RRESP_out; + wire [1:0] AXI_02_BRESP_out; + wire [1:0] AXI_02_DFI_AW_AERR_N_out; + wire [1:0] AXI_02_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_02_RRESP_out; + wire [1:0] AXI_03_BRESP_out; + wire [1:0] AXI_03_DFI_AW_AERR_N_out; + wire [1:0] AXI_03_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_03_RRESP_out; + wire [1:0] AXI_04_BRESP_out; + wire [1:0] AXI_04_DFI_AW_AERR_N_out; + wire [1:0] AXI_04_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_04_RRESP_out; + wire [1:0] AXI_05_BRESP_out; + wire [1:0] AXI_05_DFI_AW_AERR_N_out; + wire [1:0] AXI_05_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_05_RRESP_out; + wire [1:0] AXI_06_BRESP_out; + wire [1:0] AXI_06_DFI_AW_AERR_N_out; + wire [1:0] AXI_06_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_06_RRESP_out; + wire [1:0] AXI_07_BRESP_out; + wire [1:0] AXI_07_DFI_AW_AERR_N_out; + wire [1:0] AXI_07_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_07_RRESP_out; + wire [1:0] AXI_08_BRESP_out; + wire [1:0] AXI_08_DFI_AW_AERR_N_out; + wire [1:0] AXI_08_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_08_RRESP_out; + wire [1:0] AXI_09_BRESP_out; + wire [1:0] AXI_09_DFI_AW_AERR_N_out; + wire [1:0] AXI_09_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_09_RRESP_out; + wire [1:0] AXI_10_BRESP_out; + wire [1:0] AXI_10_DFI_AW_AERR_N_out; + wire [1:0] AXI_10_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_10_RRESP_out; + wire [1:0] AXI_11_BRESP_out; + wire [1:0] AXI_11_DFI_AW_AERR_N_out; + wire [1:0] AXI_11_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_11_RRESP_out; + wire [1:0] AXI_12_BRESP_out; + wire [1:0] AXI_12_DFI_AW_AERR_N_out; + wire [1:0] AXI_12_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_12_RRESP_out; + wire [1:0] AXI_13_BRESP_out; + wire [1:0] AXI_13_DFI_AW_AERR_N_out; + wire [1:0] AXI_13_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_13_RRESP_out; + wire [1:0] AXI_14_BRESP_out; + wire [1:0] AXI_14_DFI_AW_AERR_N_out; + wire [1:0] AXI_14_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_14_RRESP_out; + wire [1:0] AXI_15_BRESP_out; + wire [1:0] AXI_15_DFI_AW_AERR_N_out; + wire [1:0] AXI_15_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_15_RRESP_out; + wire [1:0] AXI_16_BRESP_out; + wire [1:0] AXI_16_DFI_AW_AERR_N_out; + wire [1:0] AXI_16_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_16_RRESP_out; + wire [1:0] AXI_17_BRESP_out; + wire [1:0] AXI_17_DFI_AW_AERR_N_out; + wire [1:0] AXI_17_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_17_RRESP_out; + wire [1:0] AXI_18_BRESP_out; + wire [1:0] AXI_18_DFI_AW_AERR_N_out; + wire [1:0] AXI_18_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_18_RRESP_out; + wire [1:0] AXI_19_BRESP_out; + wire [1:0] AXI_19_DFI_AW_AERR_N_out; + wire [1:0] AXI_19_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_19_RRESP_out; + wire [1:0] AXI_20_BRESP_out; + wire [1:0] AXI_20_DFI_AW_AERR_N_out; + wire [1:0] AXI_20_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_20_RRESP_out; + wire [1:0] AXI_21_BRESP_out; + wire [1:0] AXI_21_DFI_AW_AERR_N_out; + wire [1:0] AXI_21_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_21_RRESP_out; + wire [1:0] AXI_22_BRESP_out; + wire [1:0] AXI_22_DFI_AW_AERR_N_out; + wire [1:0] AXI_22_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_22_RRESP_out; + wire [1:0] AXI_23_BRESP_out; + wire [1:0] AXI_23_DFI_AW_AERR_N_out; + wire [1:0] AXI_23_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_23_RRESP_out; + wire [1:0] AXI_24_BRESP_out; + wire [1:0] AXI_24_DFI_AW_AERR_N_out; + wire [1:0] AXI_24_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_24_RRESP_out; + wire [1:0] AXI_25_BRESP_out; + wire [1:0] AXI_25_DFI_AW_AERR_N_out; + wire [1:0] AXI_25_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_25_RRESP_out; + wire [1:0] AXI_26_BRESP_out; + wire [1:0] AXI_26_DFI_AW_AERR_N_out; + wire [1:0] AXI_26_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_26_RRESP_out; + wire [1:0] AXI_27_BRESP_out; + wire [1:0] AXI_27_DFI_AW_AERR_N_out; + wire [1:0] AXI_27_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_27_RRESP_out; + wire [1:0] AXI_28_BRESP_out; + wire [1:0] AXI_28_DFI_AW_AERR_N_out; + wire [1:0] AXI_28_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_28_RRESP_out; + wire [1:0] AXI_29_BRESP_out; + wire [1:0] AXI_29_DFI_AW_AERR_N_out; + wire [1:0] AXI_29_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_29_RRESP_out; + wire [1:0] AXI_30_BRESP_out; + wire [1:0] AXI_30_DFI_AW_AERR_N_out; + wire [1:0] AXI_30_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_30_RRESP_out; + wire [1:0] AXI_31_BRESP_out; + wire [1:0] AXI_31_DFI_AW_AERR_N_out; + wire [1:0] AXI_31_DFI_DW_RDDATA_VALID_out; + wire [1:0] AXI_31_RRESP_out; + wire [1:0] DLL_SCAN_OUT_00_out; + wire [1:0] DLL_SCAN_OUT_01_out; + wire [1:0] IO_SCAN_OUT_00_out; + wire [1:0] IO_SCAN_OUT_01_out; + wire [1:0] MC_SCAN_OUT_00_out; + wire [1:0] MC_SCAN_OUT_01_out; + wire [1:0] MC_SCAN_OUT_02_out; + wire [1:0] MC_SCAN_OUT_03_out; + wire [1:0] MC_SCAN_OUT_04_out; + wire [1:0] MC_SCAN_OUT_05_out; + wire [1:0] MC_SCAN_OUT_06_out; + wire [1:0] MC_SCAN_OUT_07_out; + wire [1:0] MC_SCAN_OUT_08_out; + wire [1:0] MC_SCAN_OUT_09_out; + wire [1:0] MC_SCAN_OUT_10_out; + wire [1:0] MC_SCAN_OUT_11_out; + wire [1:0] MC_SCAN_OUT_12_out; + wire [1:0] MC_SCAN_OUT_13_out; + wire [1:0] MC_SCAN_OUT_14_out; + wire [1:0] MC_SCAN_OUT_15_out; + wire [1:0] PHY_SCAN_OUT_00_out; + wire [1:0] PHY_SCAN_OUT_01_out; + wire [1:0] STATUS_00_out; + wire [1:0] STATUS_01_out; + wire [1:0] STATUS_02_out; + wire [1:0] STATUS_03_out; + wire [1:0] STATUS_04_out; + wire [1:0] STATUS_05_out; + wire [1:0] STATUS_06_out; + wire [1:0] STATUS_07_out; + wire [1:0] STATUS_08_out; + wire [1:0] STATUS_09_out; + wire [1:0] STATUS_10_out; + wire [1:0] STATUS_11_out; + wire [1:0] STATUS_12_out; + wire [1:0] STATUS_13_out; + wire [1:0] STATUS_14_out; + wire [1:0] STATUS_15_out; + wire [1:0] SW_SCAN_OUT_00_out; + wire [1:0] SW_SCAN_OUT_01_out; + wire [1:0] SW_SCAN_OUT_02_out; + wire [1:0] SW_SCAN_OUT_03_out; + wire [1:0] SW_SCAN_OUT_04_out; + wire [1:0] SW_SCAN_OUT_05_out; + wire [1:0] SW_SCAN_OUT_06_out; + wire [1:0] SW_SCAN_OUT_07_out; + wire [20:0] AXI_00_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_01_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_02_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_03_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_04_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_05_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_06_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_07_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_08_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_09_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_10_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_11_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_12_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_13_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_14_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_15_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_16_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_17_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_18_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_19_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_20_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_21_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_22_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_23_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_24_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_25_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_26_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_27_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_28_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_29_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_30_DFI_DW_RDDATA_DBI_out; + wire [20:0] AXI_31_DFI_DW_RDDATA_DBI_out; + wire [255:0] AXI_00_RDATA_out; + wire [255:0] AXI_01_RDATA_out; + wire [255:0] AXI_02_RDATA_out; + wire [255:0] AXI_03_RDATA_out; + wire [255:0] AXI_04_RDATA_out; + wire [255:0] AXI_05_RDATA_out; + wire [255:0] AXI_06_RDATA_out; + wire [255:0] AXI_07_RDATA_out; + wire [255:0] AXI_08_RDATA_out; + wire [255:0] AXI_09_RDATA_out; + wire [255:0] AXI_10_RDATA_out; + wire [255:0] AXI_11_RDATA_out; + wire [255:0] AXI_12_RDATA_out; + wire [255:0] AXI_13_RDATA_out; + wire [255:0] AXI_14_RDATA_out; + wire [255:0] AXI_15_RDATA_out; + wire [255:0] AXI_16_RDATA_out; + wire [255:0] AXI_17_RDATA_out; + wire [255:0] AXI_18_RDATA_out; + wire [255:0] AXI_19_RDATA_out; + wire [255:0] AXI_20_RDATA_out; + wire [255:0] AXI_21_RDATA_out; + wire [255:0] AXI_22_RDATA_out; + wire [255:0] AXI_23_RDATA_out; + wire [255:0] AXI_24_RDATA_out; + wire [255:0] AXI_25_RDATA_out; + wire [255:0] AXI_26_RDATA_out; + wire [255:0] AXI_27_RDATA_out; + wire [255:0] AXI_28_RDATA_out; + wire [255:0] AXI_29_RDATA_out; + wire [255:0] AXI_30_RDATA_out; + wire [255:0] AXI_31_RDATA_out; + wire [2:0] DRAM_0_STAT_TEMP_out; + wire [2:0] DRAM_1_STAT_TEMP_out; + wire [31:0] APB_0_PRDATA_out; + wire [31:0] APB_1_PRDATA_out; + wire [31:0] AXI_00_RDATA_PARITY_out; + wire [31:0] AXI_01_RDATA_PARITY_out; + wire [31:0] AXI_02_RDATA_PARITY_out; + wire [31:0] AXI_03_RDATA_PARITY_out; + wire [31:0] AXI_04_RDATA_PARITY_out; + wire [31:0] AXI_05_RDATA_PARITY_out; + wire [31:0] AXI_06_RDATA_PARITY_out; + wire [31:0] AXI_07_RDATA_PARITY_out; + wire [31:0] AXI_08_RDATA_PARITY_out; + wire [31:0] AXI_09_RDATA_PARITY_out; + wire [31:0] AXI_10_RDATA_PARITY_out; + wire [31:0] AXI_11_RDATA_PARITY_out; + wire [31:0] AXI_12_RDATA_PARITY_out; + wire [31:0] AXI_13_RDATA_PARITY_out; + wire [31:0] AXI_14_RDATA_PARITY_out; + wire [31:0] AXI_15_RDATA_PARITY_out; + wire [31:0] AXI_16_RDATA_PARITY_out; + wire [31:0] AXI_17_RDATA_PARITY_out; + wire [31:0] AXI_18_RDATA_PARITY_out; + wire [31:0] AXI_19_RDATA_PARITY_out; + wire [31:0] AXI_20_RDATA_PARITY_out; + wire [31:0] AXI_21_RDATA_PARITY_out; + wire [31:0] AXI_22_RDATA_PARITY_out; + wire [31:0] AXI_23_RDATA_PARITY_out; + wire [31:0] AXI_24_RDATA_PARITY_out; + wire [31:0] AXI_25_RDATA_PARITY_out; + wire [31:0] AXI_26_RDATA_PARITY_out; + wire [31:0] AXI_27_RDATA_PARITY_out; + wire [31:0] AXI_28_RDATA_PARITY_out; + wire [31:0] AXI_29_RDATA_PARITY_out; + wire [31:0] AXI_30_RDATA_PARITY_out; + wire [31:0] AXI_31_RDATA_PARITY_out; + wire [5:0] AXI_00_BID_out; + wire [5:0] AXI_00_MC_STATUS_out; + wire [5:0] AXI_00_RID_out; + wire [5:0] AXI_01_BID_out; + wire [5:0] AXI_01_RID_out; + wire [5:0] AXI_02_BID_out; + wire [5:0] AXI_02_MC_STATUS_out; + wire [5:0] AXI_02_RID_out; + wire [5:0] AXI_03_BID_out; + wire [5:0] AXI_03_RID_out; + wire [5:0] AXI_04_BID_out; + wire [5:0] AXI_04_MC_STATUS_out; + wire [5:0] AXI_04_RID_out; + wire [5:0] AXI_05_BID_out; + wire [5:0] AXI_05_RID_out; + wire [5:0] AXI_06_BID_out; + wire [5:0] AXI_06_MC_STATUS_out; + wire [5:0] AXI_06_RID_out; + wire [5:0] AXI_07_BID_out; + wire [5:0] AXI_07_RID_out; + wire [5:0] AXI_08_BID_out; + wire [5:0] AXI_08_MC_STATUS_out; + wire [5:0] AXI_08_RID_out; + wire [5:0] AXI_09_BID_out; + wire [5:0] AXI_09_RID_out; + wire [5:0] AXI_10_BID_out; + wire [5:0] AXI_10_MC_STATUS_out; + wire [5:0] AXI_10_RID_out; + wire [5:0] AXI_11_BID_out; + wire [5:0] AXI_11_RID_out; + wire [5:0] AXI_12_BID_out; + wire [5:0] AXI_12_MC_STATUS_out; + wire [5:0] AXI_12_RID_out; + wire [5:0] AXI_13_BID_out; + wire [5:0] AXI_13_RID_out; + wire [5:0] AXI_14_BID_out; + wire [5:0] AXI_14_MC_STATUS_out; + wire [5:0] AXI_14_RID_out; + wire [5:0] AXI_15_BID_out; + wire [5:0] AXI_15_RID_out; + wire [5:0] AXI_16_BID_out; + wire [5:0] AXI_16_MC_STATUS_out; + wire [5:0] AXI_16_RID_out; + wire [5:0] AXI_17_BID_out; + wire [5:0] AXI_17_RID_out; + wire [5:0] AXI_18_BID_out; + wire [5:0] AXI_18_MC_STATUS_out; + wire [5:0] AXI_18_RID_out; + wire [5:0] AXI_19_BID_out; + wire [5:0] AXI_19_RID_out; + wire [5:0] AXI_20_BID_out; + wire [5:0] AXI_20_MC_STATUS_out; + wire [5:0] AXI_20_RID_out; + wire [5:0] AXI_21_BID_out; + wire [5:0] AXI_21_RID_out; + wire [5:0] AXI_22_BID_out; + wire [5:0] AXI_22_MC_STATUS_out; + wire [5:0] AXI_22_RID_out; + wire [5:0] AXI_23_BID_out; + wire [5:0] AXI_23_RID_out; + wire [5:0] AXI_24_BID_out; + wire [5:0] AXI_24_MC_STATUS_out; + wire [5:0] AXI_24_RID_out; + wire [5:0] AXI_25_BID_out; + wire [5:0] AXI_25_RID_out; + wire [5:0] AXI_26_BID_out; + wire [5:0] AXI_26_MC_STATUS_out; + wire [5:0] AXI_26_RID_out; + wire [5:0] AXI_27_BID_out; + wire [5:0] AXI_27_RID_out; + wire [5:0] AXI_28_BID_out; + wire [5:0] AXI_28_MC_STATUS_out; + wire [5:0] AXI_28_RID_out; + wire [5:0] AXI_29_BID_out; + wire [5:0] AXI_29_RID_out; + wire [5:0] AXI_30_BID_out; + wire [5:0] AXI_30_MC_STATUS_out; + wire [5:0] AXI_30_RID_out; + wire [5:0] AXI_31_BID_out; + wire [5:0] AXI_31_RID_out; + wire [7:0] AXI_00_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_00_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_00_PHY_STATUS_out; + wire [7:0] AXI_01_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_01_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_02_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_02_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_02_PHY_STATUS_out; + wire [7:0] AXI_03_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_03_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_04_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_04_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_04_PHY_STATUS_out; + wire [7:0] AXI_05_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_05_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_06_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_06_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_06_PHY_STATUS_out; + wire [7:0] AXI_07_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_07_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_08_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_08_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_08_PHY_STATUS_out; + wire [7:0] AXI_09_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_09_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_10_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_10_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_10_PHY_STATUS_out; + wire [7:0] AXI_11_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_11_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_12_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_12_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_12_PHY_STATUS_out; + wire [7:0] AXI_13_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_13_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_14_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_14_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_14_PHY_STATUS_out; + wire [7:0] AXI_15_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_15_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_16_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_16_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_16_PHY_STATUS_out; + wire [7:0] AXI_17_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_17_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_18_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_18_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_18_PHY_STATUS_out; + wire [7:0] AXI_19_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_19_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_20_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_20_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_20_PHY_STATUS_out; + wire [7:0] AXI_21_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_21_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_22_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_22_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_22_PHY_STATUS_out; + wire [7:0] AXI_23_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_23_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_24_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_24_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_24_PHY_STATUS_out; + wire [7:0] AXI_25_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_25_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_26_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_26_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_26_PHY_STATUS_out; + wire [7:0] AXI_27_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_27_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_28_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_28_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_28_PHY_STATUS_out; + wire [7:0] AXI_29_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_29_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_30_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_30_DFI_DW_RDDATA_DERR_out; + wire [7:0] AXI_30_PHY_STATUS_out; + wire [7:0] AXI_31_DFI_DBI_BYTE_DISABLE_out; + wire [7:0] AXI_31_DFI_DW_RDDATA_DERR_out; + wire [7:0] BLI_SCAN_OUT_00_out; + wire [7:0] BLI_SCAN_OUT_01_out; + wire [7:0] BLI_SCAN_OUT_02_out; + wire [7:0] BLI_SCAN_OUT_03_out; + wire [7:0] BLI_SCAN_OUT_04_out; + wire [7:0] BLI_SCAN_OUT_05_out; + wire [7:0] BLI_SCAN_OUT_06_out; + wire [7:0] BLI_SCAN_OUT_07_out; + wire [7:0] BLI_SCAN_OUT_08_out; + wire [7:0] BLI_SCAN_OUT_09_out; + wire [7:0] BLI_SCAN_OUT_10_out; + wire [7:0] BLI_SCAN_OUT_11_out; + wire [7:0] BLI_SCAN_OUT_12_out; + wire [7:0] BLI_SCAN_OUT_13_out; + wire [7:0] BLI_SCAN_OUT_14_out; + wire [7:0] BLI_SCAN_OUT_15_out; + wire [7:0] BLI_SCAN_OUT_16_out; + wire [7:0] BLI_SCAN_OUT_17_out; + wire [7:0] BLI_SCAN_OUT_18_out; + wire [7:0] BLI_SCAN_OUT_19_out; + wire [7:0] BLI_SCAN_OUT_20_out; + wire [7:0] BLI_SCAN_OUT_21_out; + wire [7:0] BLI_SCAN_OUT_22_out; + wire [7:0] BLI_SCAN_OUT_23_out; + wire [7:0] BLI_SCAN_OUT_24_out; + wire [7:0] BLI_SCAN_OUT_25_out; + wire [7:0] BLI_SCAN_OUT_26_out; + wire [7:0] BLI_SCAN_OUT_27_out; + wire [7:0] BLI_SCAN_OUT_28_out; + wire [7:0] BLI_SCAN_OUT_29_out; + wire [7:0] BLI_SCAN_OUT_30_out; + wire [7:0] BLI_SCAN_OUT_31_out; + + wire ANALOG_HBM_SEL_00_in; + wire ANALOG_HBM_SEL_01_in; + wire APB_0_PCLK_in; + wire APB_0_PENABLE_in; + wire APB_0_PRESET_N_in; + wire APB_0_PSEL_in; + wire APB_0_PWRITE_in; + wire APB_1_PCLK_in; + wire APB_1_PENABLE_in; + wire APB_1_PRESET_N_in; + wire APB_1_PSEL_in; + wire APB_1_PWRITE_in; + wire AXI_00_ACLK_in; + wire AXI_00_ARESET_N_in; + wire AXI_00_ARVALID_in; + wire AXI_00_AWVALID_in; + wire AXI_00_BREADY_in; + wire AXI_00_DFI_LP_PWR_X_REQ_in; + wire AXI_00_RREADY_in; + wire AXI_00_WLAST_in; + wire AXI_00_WVALID_in; + wire AXI_01_ACLK_in; + wire AXI_01_ARESET_N_in; + wire AXI_01_ARVALID_in; + wire AXI_01_AWVALID_in; + wire AXI_01_BREADY_in; + wire AXI_01_DFI_LP_PWR_X_REQ_in; + wire AXI_01_RREADY_in; + wire AXI_01_WLAST_in; + wire AXI_01_WVALID_in; + wire AXI_02_ACLK_in; + wire AXI_02_ARESET_N_in; + wire AXI_02_ARVALID_in; + wire AXI_02_AWVALID_in; + wire AXI_02_BREADY_in; + wire AXI_02_DFI_LP_PWR_X_REQ_in; + wire AXI_02_RREADY_in; + wire AXI_02_WLAST_in; + wire AXI_02_WVALID_in; + wire AXI_03_ACLK_in; + wire AXI_03_ARESET_N_in; + wire AXI_03_ARVALID_in; + wire AXI_03_AWVALID_in; + wire AXI_03_BREADY_in; + wire AXI_03_DFI_LP_PWR_X_REQ_in; + wire AXI_03_RREADY_in; + wire AXI_03_WLAST_in; + wire AXI_03_WVALID_in; + wire AXI_04_ACLK_in; + wire AXI_04_ARESET_N_in; + wire AXI_04_ARVALID_in; + wire AXI_04_AWVALID_in; + wire AXI_04_BREADY_in; + wire AXI_04_DFI_LP_PWR_X_REQ_in; + wire AXI_04_RREADY_in; + wire AXI_04_WLAST_in; + wire AXI_04_WVALID_in; + wire AXI_05_ACLK_in; + wire AXI_05_ARESET_N_in; + wire AXI_05_ARVALID_in; + wire AXI_05_AWVALID_in; + wire AXI_05_BREADY_in; + wire AXI_05_DFI_LP_PWR_X_REQ_in; + wire AXI_05_RREADY_in; + wire AXI_05_WLAST_in; + wire AXI_05_WVALID_in; + wire AXI_06_ACLK_in; + wire AXI_06_ARESET_N_in; + wire AXI_06_ARVALID_in; + wire AXI_06_AWVALID_in; + wire AXI_06_BREADY_in; + wire AXI_06_DFI_LP_PWR_X_REQ_in; + wire AXI_06_RREADY_in; + wire AXI_06_WLAST_in; + wire AXI_06_WVALID_in; + wire AXI_07_ACLK_in; + wire AXI_07_ARESET_N_in; + wire AXI_07_ARVALID_in; + wire AXI_07_AWVALID_in; + wire AXI_07_BREADY_in; + wire AXI_07_DFI_LP_PWR_X_REQ_in; + wire AXI_07_RREADY_in; + wire AXI_07_WLAST_in; + wire AXI_07_WVALID_in; + wire AXI_08_ACLK_in; + wire AXI_08_ARESET_N_in; + wire AXI_08_ARVALID_in; + wire AXI_08_AWVALID_in; + wire AXI_08_BREADY_in; + wire AXI_08_DFI_LP_PWR_X_REQ_in; + wire AXI_08_RREADY_in; + wire AXI_08_WLAST_in; + wire AXI_08_WVALID_in; + wire AXI_09_ACLK_in; + wire AXI_09_ARESET_N_in; + wire AXI_09_ARVALID_in; + wire AXI_09_AWVALID_in; + wire AXI_09_BREADY_in; + wire AXI_09_DFI_LP_PWR_X_REQ_in; + wire AXI_09_RREADY_in; + wire AXI_09_WLAST_in; + wire AXI_09_WVALID_in; + wire AXI_10_ACLK_in; + wire AXI_10_ARESET_N_in; + wire AXI_10_ARVALID_in; + wire AXI_10_AWVALID_in; + wire AXI_10_BREADY_in; + wire AXI_10_DFI_LP_PWR_X_REQ_in; + wire AXI_10_RREADY_in; + wire AXI_10_WLAST_in; + wire AXI_10_WVALID_in; + wire AXI_11_ACLK_in; + wire AXI_11_ARESET_N_in; + wire AXI_11_ARVALID_in; + wire AXI_11_AWVALID_in; + wire AXI_11_BREADY_in; + wire AXI_11_DFI_LP_PWR_X_REQ_in; + wire AXI_11_RREADY_in; + wire AXI_11_WLAST_in; + wire AXI_11_WVALID_in; + wire AXI_12_ACLK_in; + wire AXI_12_ARESET_N_in; + wire AXI_12_ARVALID_in; + wire AXI_12_AWVALID_in; + wire AXI_12_BREADY_in; + wire AXI_12_DFI_LP_PWR_X_REQ_in; + wire AXI_12_RREADY_in; + wire AXI_12_WLAST_in; + wire AXI_12_WVALID_in; + wire AXI_13_ACLK_in; + wire AXI_13_ARESET_N_in; + wire AXI_13_ARVALID_in; + wire AXI_13_AWVALID_in; + wire AXI_13_BREADY_in; + wire AXI_13_DFI_LP_PWR_X_REQ_in; + wire AXI_13_RREADY_in; + wire AXI_13_WLAST_in; + wire AXI_13_WVALID_in; + wire AXI_14_ACLK_in; + wire AXI_14_ARESET_N_in; + wire AXI_14_ARVALID_in; + wire AXI_14_AWVALID_in; + wire AXI_14_BREADY_in; + wire AXI_14_DFI_LP_PWR_X_REQ_in; + wire AXI_14_RREADY_in; + wire AXI_14_WLAST_in; + wire AXI_14_WVALID_in; + wire AXI_15_ACLK_in; + wire AXI_15_ARESET_N_in; + wire AXI_15_ARVALID_in; + wire AXI_15_AWVALID_in; + wire AXI_15_BREADY_in; + wire AXI_15_DFI_LP_PWR_X_REQ_in; + wire AXI_15_RREADY_in; + wire AXI_15_WLAST_in; + wire AXI_15_WVALID_in; + wire AXI_16_ACLK_in; + wire AXI_16_ARESET_N_in; + wire AXI_16_ARVALID_in; + wire AXI_16_AWVALID_in; + wire AXI_16_BREADY_in; + wire AXI_16_DFI_LP_PWR_X_REQ_in; + wire AXI_16_RREADY_in; + wire AXI_16_WLAST_in; + wire AXI_16_WVALID_in; + wire AXI_17_ACLK_in; + wire AXI_17_ARESET_N_in; + wire AXI_17_ARVALID_in; + wire AXI_17_AWVALID_in; + wire AXI_17_BREADY_in; + wire AXI_17_DFI_LP_PWR_X_REQ_in; + wire AXI_17_RREADY_in; + wire AXI_17_WLAST_in; + wire AXI_17_WVALID_in; + wire AXI_18_ACLK_in; + wire AXI_18_ARESET_N_in; + wire AXI_18_ARVALID_in; + wire AXI_18_AWVALID_in; + wire AXI_18_BREADY_in; + wire AXI_18_DFI_LP_PWR_X_REQ_in; + wire AXI_18_RREADY_in; + wire AXI_18_WLAST_in; + wire AXI_18_WVALID_in; + wire AXI_19_ACLK_in; + wire AXI_19_ARESET_N_in; + wire AXI_19_ARVALID_in; + wire AXI_19_AWVALID_in; + wire AXI_19_BREADY_in; + wire AXI_19_DFI_LP_PWR_X_REQ_in; + wire AXI_19_RREADY_in; + wire AXI_19_WLAST_in; + wire AXI_19_WVALID_in; + wire AXI_20_ACLK_in; + wire AXI_20_ARESET_N_in; + wire AXI_20_ARVALID_in; + wire AXI_20_AWVALID_in; + wire AXI_20_BREADY_in; + wire AXI_20_DFI_LP_PWR_X_REQ_in; + wire AXI_20_RREADY_in; + wire AXI_20_WLAST_in; + wire AXI_20_WVALID_in; + wire AXI_21_ACLK_in; + wire AXI_21_ARESET_N_in; + wire AXI_21_ARVALID_in; + wire AXI_21_AWVALID_in; + wire AXI_21_BREADY_in; + wire AXI_21_DFI_LP_PWR_X_REQ_in; + wire AXI_21_RREADY_in; + wire AXI_21_WLAST_in; + wire AXI_21_WVALID_in; + wire AXI_22_ACLK_in; + wire AXI_22_ARESET_N_in; + wire AXI_22_ARVALID_in; + wire AXI_22_AWVALID_in; + wire AXI_22_BREADY_in; + wire AXI_22_DFI_LP_PWR_X_REQ_in; + wire AXI_22_RREADY_in; + wire AXI_22_WLAST_in; + wire AXI_22_WVALID_in; + wire AXI_23_ACLK_in; + wire AXI_23_ARESET_N_in; + wire AXI_23_ARVALID_in; + wire AXI_23_AWVALID_in; + wire AXI_23_BREADY_in; + wire AXI_23_DFI_LP_PWR_X_REQ_in; + wire AXI_23_RREADY_in; + wire AXI_23_WLAST_in; + wire AXI_23_WVALID_in; + wire AXI_24_ACLK_in; + wire AXI_24_ARESET_N_in; + wire AXI_24_ARVALID_in; + wire AXI_24_AWVALID_in; + wire AXI_24_BREADY_in; + wire AXI_24_DFI_LP_PWR_X_REQ_in; + wire AXI_24_RREADY_in; + wire AXI_24_WLAST_in; + wire AXI_24_WVALID_in; + wire AXI_25_ACLK_in; + wire AXI_25_ARESET_N_in; + wire AXI_25_ARVALID_in; + wire AXI_25_AWVALID_in; + wire AXI_25_BREADY_in; + wire AXI_25_DFI_LP_PWR_X_REQ_in; + wire AXI_25_RREADY_in; + wire AXI_25_WLAST_in; + wire AXI_25_WVALID_in; + wire AXI_26_ACLK_in; + wire AXI_26_ARESET_N_in; + wire AXI_26_ARVALID_in; + wire AXI_26_AWVALID_in; + wire AXI_26_BREADY_in; + wire AXI_26_DFI_LP_PWR_X_REQ_in; + wire AXI_26_RREADY_in; + wire AXI_26_WLAST_in; + wire AXI_26_WVALID_in; + wire AXI_27_ACLK_in; + wire AXI_27_ARESET_N_in; + wire AXI_27_ARVALID_in; + wire AXI_27_AWVALID_in; + wire AXI_27_BREADY_in; + wire AXI_27_DFI_LP_PWR_X_REQ_in; + wire AXI_27_RREADY_in; + wire AXI_27_WLAST_in; + wire AXI_27_WVALID_in; + wire AXI_28_ACLK_in; + wire AXI_28_ARESET_N_in; + wire AXI_28_ARVALID_in; + wire AXI_28_AWVALID_in; + wire AXI_28_BREADY_in; + wire AXI_28_DFI_LP_PWR_X_REQ_in; + wire AXI_28_RREADY_in; + wire AXI_28_WLAST_in; + wire AXI_28_WVALID_in; + wire AXI_29_ACLK_in; + wire AXI_29_ARESET_N_in; + wire AXI_29_ARVALID_in; + wire AXI_29_AWVALID_in; + wire AXI_29_BREADY_in; + wire AXI_29_DFI_LP_PWR_X_REQ_in; + wire AXI_29_RREADY_in; + wire AXI_29_WLAST_in; + wire AXI_29_WVALID_in; + wire AXI_30_ACLK_in; + wire AXI_30_ARESET_N_in; + wire AXI_30_ARVALID_in; + wire AXI_30_AWVALID_in; + wire AXI_30_BREADY_in; + wire AXI_30_DFI_LP_PWR_X_REQ_in; + wire AXI_30_RREADY_in; + wire AXI_30_WLAST_in; + wire AXI_30_WVALID_in; + wire AXI_31_ACLK_in; + wire AXI_31_ARESET_N_in; + wire AXI_31_ARVALID_in; + wire AXI_31_AWVALID_in; + wire AXI_31_BREADY_in; + wire AXI_31_DFI_LP_PWR_X_REQ_in; + wire AXI_31_RREADY_in; + wire AXI_31_WLAST_in; + wire AXI_31_WVALID_in; + wire BLI_SCAN_ENABLE_00_in; + wire BLI_SCAN_ENABLE_01_in; + wire BLI_SCAN_ENABLE_02_in; + wire BLI_SCAN_ENABLE_03_in; + wire BLI_SCAN_ENABLE_04_in; + wire BLI_SCAN_ENABLE_05_in; + wire BLI_SCAN_ENABLE_06_in; + wire BLI_SCAN_ENABLE_07_in; + wire BLI_SCAN_ENABLE_08_in; + wire BLI_SCAN_ENABLE_09_in; + wire BLI_SCAN_ENABLE_10_in; + wire BLI_SCAN_ENABLE_11_in; + wire BLI_SCAN_ENABLE_12_in; + wire BLI_SCAN_ENABLE_13_in; + wire BLI_SCAN_ENABLE_14_in; + wire BLI_SCAN_ENABLE_15_in; + wire BLI_SCAN_ENABLE_16_in; + wire BLI_SCAN_ENABLE_17_in; + wire BLI_SCAN_ENABLE_18_in; + wire BLI_SCAN_ENABLE_19_in; + wire BLI_SCAN_ENABLE_20_in; + wire BLI_SCAN_ENABLE_21_in; + wire BLI_SCAN_ENABLE_22_in; + wire BLI_SCAN_ENABLE_23_in; + wire BLI_SCAN_ENABLE_24_in; + wire BLI_SCAN_ENABLE_25_in; + wire BLI_SCAN_ENABLE_26_in; + wire BLI_SCAN_ENABLE_27_in; + wire BLI_SCAN_ENABLE_28_in; + wire BLI_SCAN_ENABLE_29_in; + wire BLI_SCAN_ENABLE_30_in; + wire BLI_SCAN_ENABLE_31_in; + wire BSCAN_DRCK_0_in; + wire BSCAN_DRCK_1_in; + wire BSCAN_TCK_0_in; + wire BSCAN_TCK_1_in; + wire DLL_SCAN_CK_00_in; + wire DLL_SCAN_CK_01_in; + wire DLL_SCAN_ENABLE_00_in; + wire DLL_SCAN_ENABLE_01_in; + wire DLL_SCAN_MODE_00_in; + wire DLL_SCAN_MODE_01_in; + wire DLL_SCAN_RST_N_00_in; + wire DLL_SCAN_RST_N_01_in; + wire HBM_REF_CLK_0_in; + wire HBM_REF_CLK_1_in; + wire IO_SCAN_CK_00_in; + wire IO_SCAN_CK_01_in; + wire IO_SCAN_ENABLE_00_in; + wire IO_SCAN_ENABLE_01_in; + wire IO_SCAN_MODE_00_in; + wire IO_SCAN_MODE_01_in; + wire IO_SCAN_RST_N_00_in; + wire IO_SCAN_RST_N_01_in; + wire MBIST_EN_00_in; + wire MBIST_EN_01_in; + wire MBIST_EN_02_in; + wire MBIST_EN_03_in; + wire MBIST_EN_04_in; + wire MBIST_EN_05_in; + wire MBIST_EN_06_in; + wire MBIST_EN_07_in; + wire MBIST_EN_08_in; + wire MBIST_EN_09_in; + wire MBIST_EN_10_in; + wire MBIST_EN_11_in; + wire MBIST_EN_12_in; + wire MBIST_EN_13_in; + wire MBIST_EN_14_in; + wire MBIST_EN_15_in; + wire MC_SCAN_CK_00_in; + wire MC_SCAN_CK_01_in; + wire MC_SCAN_CK_02_in; + wire MC_SCAN_CK_03_in; + wire MC_SCAN_CK_04_in; + wire MC_SCAN_CK_05_in; + wire MC_SCAN_CK_06_in; + wire MC_SCAN_CK_07_in; + wire MC_SCAN_CK_08_in; + wire MC_SCAN_CK_09_in; + wire MC_SCAN_CK_10_in; + wire MC_SCAN_CK_11_in; + wire MC_SCAN_CK_12_in; + wire MC_SCAN_CK_13_in; + wire MC_SCAN_CK_14_in; + wire MC_SCAN_CK_15_in; + wire MC_SCAN_ENABLE_00_in; + wire MC_SCAN_ENABLE_01_in; + wire MC_SCAN_ENABLE_02_in; + wire MC_SCAN_ENABLE_03_in; + wire MC_SCAN_ENABLE_04_in; + wire MC_SCAN_ENABLE_05_in; + wire MC_SCAN_ENABLE_06_in; + wire MC_SCAN_ENABLE_07_in; + wire MC_SCAN_ENABLE_08_in; + wire MC_SCAN_ENABLE_09_in; + wire MC_SCAN_ENABLE_10_in; + wire MC_SCAN_ENABLE_11_in; + wire MC_SCAN_ENABLE_12_in; + wire MC_SCAN_ENABLE_13_in; + wire MC_SCAN_ENABLE_14_in; + wire MC_SCAN_ENABLE_15_in; + wire MC_SCAN_MODE_00_in; + wire MC_SCAN_MODE_01_in; + wire MC_SCAN_MODE_02_in; + wire MC_SCAN_MODE_03_in; + wire MC_SCAN_MODE_04_in; + wire MC_SCAN_MODE_05_in; + wire MC_SCAN_MODE_06_in; + wire MC_SCAN_MODE_07_in; + wire MC_SCAN_MODE_08_in; + wire MC_SCAN_MODE_09_in; + wire MC_SCAN_MODE_10_in; + wire MC_SCAN_MODE_11_in; + wire MC_SCAN_MODE_12_in; + wire MC_SCAN_MODE_13_in; + wire MC_SCAN_MODE_14_in; + wire MC_SCAN_MODE_15_in; + wire MC_SCAN_RST_N_00_in; + wire MC_SCAN_RST_N_01_in; + wire MC_SCAN_RST_N_02_in; + wire MC_SCAN_RST_N_03_in; + wire MC_SCAN_RST_N_04_in; + wire MC_SCAN_RST_N_05_in; + wire MC_SCAN_RST_N_06_in; + wire MC_SCAN_RST_N_07_in; + wire MC_SCAN_RST_N_08_in; + wire MC_SCAN_RST_N_09_in; + wire MC_SCAN_RST_N_10_in; + wire MC_SCAN_RST_N_11_in; + wire MC_SCAN_RST_N_12_in; + wire MC_SCAN_RST_N_13_in; + wire MC_SCAN_RST_N_14_in; + wire MC_SCAN_RST_N_15_in; + wire PHY_SCAN_CK_00_in; + wire PHY_SCAN_CK_01_in; + wire PHY_SCAN_ENABLE_00_in; + wire PHY_SCAN_ENABLE_01_in; + wire PHY_SCAN_MODE_00_in; + wire PHY_SCAN_MODE_01_in; + wire PHY_SCAN_RST_N_00_in; + wire PHY_SCAN_RST_N_01_in; + wire SW_SCAN_CK_00_in; + wire SW_SCAN_CK_01_in; + wire SW_SCAN_ENABLE_00_in; + wire SW_SCAN_ENABLE_01_in; + wire SW_SCAN_MODE_00_in; + wire SW_SCAN_MODE_01_in; + wire SW_SCAN_RST_N_00_in; + wire SW_SCAN_RST_N_01_in; + wire [1:0] AXI_00_ARBURST_in; + wire [1:0] AXI_00_AWBURST_in; + wire [1:0] AXI_01_ARBURST_in; + wire [1:0] AXI_01_AWBURST_in; + wire [1:0] AXI_02_ARBURST_in; + wire [1:0] AXI_02_AWBURST_in; + wire [1:0] AXI_03_ARBURST_in; + wire [1:0] AXI_03_AWBURST_in; + wire [1:0] AXI_04_ARBURST_in; + wire [1:0] AXI_04_AWBURST_in; + wire [1:0] AXI_05_ARBURST_in; + wire [1:0] AXI_05_AWBURST_in; + wire [1:0] AXI_06_ARBURST_in; + wire [1:0] AXI_06_AWBURST_in; + wire [1:0] AXI_07_ARBURST_in; + wire [1:0] AXI_07_AWBURST_in; + wire [1:0] AXI_08_ARBURST_in; + wire [1:0] AXI_08_AWBURST_in; + wire [1:0] AXI_09_ARBURST_in; + wire [1:0] AXI_09_AWBURST_in; + wire [1:0] AXI_10_ARBURST_in; + wire [1:0] AXI_10_AWBURST_in; + wire [1:0] AXI_11_ARBURST_in; + wire [1:0] AXI_11_AWBURST_in; + wire [1:0] AXI_12_ARBURST_in; + wire [1:0] AXI_12_AWBURST_in; + wire [1:0] AXI_13_ARBURST_in; + wire [1:0] AXI_13_AWBURST_in; + wire [1:0] AXI_14_ARBURST_in; + wire [1:0] AXI_14_AWBURST_in; + wire [1:0] AXI_15_ARBURST_in; + wire [1:0] AXI_15_AWBURST_in; + wire [1:0] AXI_16_ARBURST_in; + wire [1:0] AXI_16_AWBURST_in; + wire [1:0] AXI_17_ARBURST_in; + wire [1:0] AXI_17_AWBURST_in; + wire [1:0] AXI_18_ARBURST_in; + wire [1:0] AXI_18_AWBURST_in; + wire [1:0] AXI_19_ARBURST_in; + wire [1:0] AXI_19_AWBURST_in; + wire [1:0] AXI_20_ARBURST_in; + wire [1:0] AXI_20_AWBURST_in; + wire [1:0] AXI_21_ARBURST_in; + wire [1:0] AXI_21_AWBURST_in; + wire [1:0] AXI_22_ARBURST_in; + wire [1:0] AXI_22_AWBURST_in; + wire [1:0] AXI_23_ARBURST_in; + wire [1:0] AXI_23_AWBURST_in; + wire [1:0] AXI_24_ARBURST_in; + wire [1:0] AXI_24_AWBURST_in; + wire [1:0] AXI_25_ARBURST_in; + wire [1:0] AXI_25_AWBURST_in; + wire [1:0] AXI_26_ARBURST_in; + wire [1:0] AXI_26_AWBURST_in; + wire [1:0] AXI_27_ARBURST_in; + wire [1:0] AXI_27_AWBURST_in; + wire [1:0] AXI_28_ARBURST_in; + wire [1:0] AXI_28_AWBURST_in; + wire [1:0] AXI_29_ARBURST_in; + wire [1:0] AXI_29_AWBURST_in; + wire [1:0] AXI_30_ARBURST_in; + wire [1:0] AXI_30_AWBURST_in; + wire [1:0] AXI_31_ARBURST_in; + wire [1:0] AXI_31_AWBURST_in; + wire [1:0] DLL_SCAN_IN_00_in; + wire [1:0] DLL_SCAN_IN_01_in; + wire [1:0] IO_SCAN_IN_00_in; + wire [1:0] IO_SCAN_IN_01_in; + wire [1:0] MC_SCAN_IN_00_in; + wire [1:0] MC_SCAN_IN_01_in; + wire [1:0] MC_SCAN_IN_02_in; + wire [1:0] MC_SCAN_IN_03_in; + wire [1:0] MC_SCAN_IN_04_in; + wire [1:0] MC_SCAN_IN_05_in; + wire [1:0] MC_SCAN_IN_06_in; + wire [1:0] MC_SCAN_IN_07_in; + wire [1:0] MC_SCAN_IN_08_in; + wire [1:0] MC_SCAN_IN_09_in; + wire [1:0] MC_SCAN_IN_10_in; + wire [1:0] MC_SCAN_IN_11_in; + wire [1:0] MC_SCAN_IN_12_in; + wire [1:0] MC_SCAN_IN_13_in; + wire [1:0] MC_SCAN_IN_14_in; + wire [1:0] MC_SCAN_IN_15_in; + wire [1:0] PHY_SCAN_IN_00_in; + wire [1:0] PHY_SCAN_IN_01_in; + wire [1:0] SW_SCAN_IN_00_in; + wire [1:0] SW_SCAN_IN_01_in; + wire [1:0] SW_SCAN_IN_02_in; + wire [1:0] SW_SCAN_IN_03_in; + wire [1:0] SW_SCAN_IN_04_in; + wire [1:0] SW_SCAN_IN_05_in; + wire [1:0] SW_SCAN_IN_06_in; + wire [1:0] SW_SCAN_IN_07_in; + wire [21:0] APB_0_PADDR_in; + wire [21:0] APB_1_PADDR_in; + wire [23:0] DBG_IN_00_in; + wire [23:0] DBG_IN_01_in; + wire [23:0] DBG_IN_02_in; + wire [23:0] DBG_IN_03_in; + wire [23:0] DBG_IN_04_in; + wire [23:0] DBG_IN_05_in; + wire [23:0] DBG_IN_06_in; + wire [23:0] DBG_IN_07_in; + wire [23:0] DBG_IN_08_in; + wire [23:0] DBG_IN_09_in; + wire [23:0] DBG_IN_10_in; + wire [23:0] DBG_IN_11_in; + wire [23:0] DBG_IN_12_in; + wire [23:0] DBG_IN_13_in; + wire [23:0] DBG_IN_14_in; + wire [23:0] DBG_IN_15_in; + wire [23:0] DBG_IN_16_in; + wire [23:0] DBG_IN_17_in; + wire [23:0] DBG_IN_18_in; + wire [23:0] DBG_IN_19_in; + wire [23:0] DBG_IN_20_in; + wire [23:0] DBG_IN_21_in; + wire [23:0] DBG_IN_22_in; + wire [23:0] DBG_IN_23_in; + wire [23:0] DBG_IN_24_in; + wire [23:0] DBG_IN_25_in; + wire [23:0] DBG_IN_26_in; + wire [23:0] DBG_IN_27_in; + wire [23:0] DBG_IN_28_in; + wire [23:0] DBG_IN_29_in; + wire [23:0] DBG_IN_30_in; + wire [23:0] DBG_IN_31_in; + wire [255:0] AXI_00_WDATA_in; + wire [255:0] AXI_01_WDATA_in; + wire [255:0] AXI_02_WDATA_in; + wire [255:0] AXI_03_WDATA_in; + wire [255:0] AXI_04_WDATA_in; + wire [255:0] AXI_05_WDATA_in; + wire [255:0] AXI_06_WDATA_in; + wire [255:0] AXI_07_WDATA_in; + wire [255:0] AXI_08_WDATA_in; + wire [255:0] AXI_09_WDATA_in; + wire [255:0] AXI_10_WDATA_in; + wire [255:0] AXI_11_WDATA_in; + wire [255:0] AXI_12_WDATA_in; + wire [255:0] AXI_13_WDATA_in; + wire [255:0] AXI_14_WDATA_in; + wire [255:0] AXI_15_WDATA_in; + wire [255:0] AXI_16_WDATA_in; + wire [255:0] AXI_17_WDATA_in; + wire [255:0] AXI_18_WDATA_in; + wire [255:0] AXI_19_WDATA_in; + wire [255:0] AXI_20_WDATA_in; + wire [255:0] AXI_21_WDATA_in; + wire [255:0] AXI_22_WDATA_in; + wire [255:0] AXI_23_WDATA_in; + wire [255:0] AXI_24_WDATA_in; + wire [255:0] AXI_25_WDATA_in; + wire [255:0] AXI_26_WDATA_in; + wire [255:0] AXI_27_WDATA_in; + wire [255:0] AXI_28_WDATA_in; + wire [255:0] AXI_29_WDATA_in; + wire [255:0] AXI_30_WDATA_in; + wire [255:0] AXI_31_WDATA_in; + wire [2:0] AXI_00_ARSIZE_in; + wire [2:0] AXI_00_AWSIZE_in; + wire [2:0] AXI_01_ARSIZE_in; + wire [2:0] AXI_01_AWSIZE_in; + wire [2:0] AXI_02_ARSIZE_in; + wire [2:0] AXI_02_AWSIZE_in; + wire [2:0] AXI_03_ARSIZE_in; + wire [2:0] AXI_03_AWSIZE_in; + wire [2:0] AXI_04_ARSIZE_in; + wire [2:0] AXI_04_AWSIZE_in; + wire [2:0] AXI_05_ARSIZE_in; + wire [2:0] AXI_05_AWSIZE_in; + wire [2:0] AXI_06_ARSIZE_in; + wire [2:0] AXI_06_AWSIZE_in; + wire [2:0] AXI_07_ARSIZE_in; + wire [2:0] AXI_07_AWSIZE_in; + wire [2:0] AXI_08_ARSIZE_in; + wire [2:0] AXI_08_AWSIZE_in; + wire [2:0] AXI_09_ARSIZE_in; + wire [2:0] AXI_09_AWSIZE_in; + wire [2:0] AXI_10_ARSIZE_in; + wire [2:0] AXI_10_AWSIZE_in; + wire [2:0] AXI_11_ARSIZE_in; + wire [2:0] AXI_11_AWSIZE_in; + wire [2:0] AXI_12_ARSIZE_in; + wire [2:0] AXI_12_AWSIZE_in; + wire [2:0] AXI_13_ARSIZE_in; + wire [2:0] AXI_13_AWSIZE_in; + wire [2:0] AXI_14_ARSIZE_in; + wire [2:0] AXI_14_AWSIZE_in; + wire [2:0] AXI_15_ARSIZE_in; + wire [2:0] AXI_15_AWSIZE_in; + wire [2:0] AXI_16_ARSIZE_in; + wire [2:0] AXI_16_AWSIZE_in; + wire [2:0] AXI_17_ARSIZE_in; + wire [2:0] AXI_17_AWSIZE_in; + wire [2:0] AXI_18_ARSIZE_in; + wire [2:0] AXI_18_AWSIZE_in; + wire [2:0] AXI_19_ARSIZE_in; + wire [2:0] AXI_19_AWSIZE_in; + wire [2:0] AXI_20_ARSIZE_in; + wire [2:0] AXI_20_AWSIZE_in; + wire [2:0] AXI_21_ARSIZE_in; + wire [2:0] AXI_21_AWSIZE_in; + wire [2:0] AXI_22_ARSIZE_in; + wire [2:0] AXI_22_AWSIZE_in; + wire [2:0] AXI_23_ARSIZE_in; + wire [2:0] AXI_23_AWSIZE_in; + wire [2:0] AXI_24_ARSIZE_in; + wire [2:0] AXI_24_AWSIZE_in; + wire [2:0] AXI_25_ARSIZE_in; + wire [2:0] AXI_25_AWSIZE_in; + wire [2:0] AXI_26_ARSIZE_in; + wire [2:0] AXI_26_AWSIZE_in; + wire [2:0] AXI_27_ARSIZE_in; + wire [2:0] AXI_27_AWSIZE_in; + wire [2:0] AXI_28_ARSIZE_in; + wire [2:0] AXI_28_AWSIZE_in; + wire [2:0] AXI_29_ARSIZE_in; + wire [2:0] AXI_29_AWSIZE_in; + wire [2:0] AXI_30_ARSIZE_in; + wire [2:0] AXI_30_AWSIZE_in; + wire [2:0] AXI_31_ARSIZE_in; + wire [2:0] AXI_31_AWSIZE_in; + wire [31:0] APB_0_PWDATA_in; + wire [31:0] APB_1_PWDATA_in; + wire [31:0] AXI_00_WDATA_PARITY_in; + wire [31:0] AXI_00_WSTRB_in; + wire [31:0] AXI_01_WDATA_PARITY_in; + wire [31:0] AXI_01_WSTRB_in; + wire [31:0] AXI_02_WDATA_PARITY_in; + wire [31:0] AXI_02_WSTRB_in; + wire [31:0] AXI_03_WDATA_PARITY_in; + wire [31:0] AXI_03_WSTRB_in; + wire [31:0] AXI_04_WDATA_PARITY_in; + wire [31:0] AXI_04_WSTRB_in; + wire [31:0] AXI_05_WDATA_PARITY_in; + wire [31:0] AXI_05_WSTRB_in; + wire [31:0] AXI_06_WDATA_PARITY_in; + wire [31:0] AXI_06_WSTRB_in; + wire [31:0] AXI_07_WDATA_PARITY_in; + wire [31:0] AXI_07_WSTRB_in; + wire [31:0] AXI_08_WDATA_PARITY_in; + wire [31:0] AXI_08_WSTRB_in; + wire [31:0] AXI_09_WDATA_PARITY_in; + wire [31:0] AXI_09_WSTRB_in; + wire [31:0] AXI_10_WDATA_PARITY_in; + wire [31:0] AXI_10_WSTRB_in; + wire [31:0] AXI_11_WDATA_PARITY_in; + wire [31:0] AXI_11_WSTRB_in; + wire [31:0] AXI_12_WDATA_PARITY_in; + wire [31:0] AXI_12_WSTRB_in; + wire [31:0] AXI_13_WDATA_PARITY_in; + wire [31:0] AXI_13_WSTRB_in; + wire [31:0] AXI_14_WDATA_PARITY_in; + wire [31:0] AXI_14_WSTRB_in; + wire [31:0] AXI_15_WDATA_PARITY_in; + wire [31:0] AXI_15_WSTRB_in; + wire [31:0] AXI_16_WDATA_PARITY_in; + wire [31:0] AXI_16_WSTRB_in; + wire [31:0] AXI_17_WDATA_PARITY_in; + wire [31:0] AXI_17_WSTRB_in; + wire [31:0] AXI_18_WDATA_PARITY_in; + wire [31:0] AXI_18_WSTRB_in; + wire [31:0] AXI_19_WDATA_PARITY_in; + wire [31:0] AXI_19_WSTRB_in; + wire [31:0] AXI_20_WDATA_PARITY_in; + wire [31:0] AXI_20_WSTRB_in; + wire [31:0] AXI_21_WDATA_PARITY_in; + wire [31:0] AXI_21_WSTRB_in; + wire [31:0] AXI_22_WDATA_PARITY_in; + wire [31:0] AXI_22_WSTRB_in; + wire [31:0] AXI_23_WDATA_PARITY_in; + wire [31:0] AXI_23_WSTRB_in; + wire [31:0] AXI_24_WDATA_PARITY_in; + wire [31:0] AXI_24_WSTRB_in; + wire [31:0] AXI_25_WDATA_PARITY_in; + wire [31:0] AXI_25_WSTRB_in; + wire [31:0] AXI_26_WDATA_PARITY_in; + wire [31:0] AXI_26_WSTRB_in; + wire [31:0] AXI_27_WDATA_PARITY_in; + wire [31:0] AXI_27_WSTRB_in; + wire [31:0] AXI_28_WDATA_PARITY_in; + wire [31:0] AXI_28_WSTRB_in; + wire [31:0] AXI_29_WDATA_PARITY_in; + wire [31:0] AXI_29_WSTRB_in; + wire [31:0] AXI_30_WDATA_PARITY_in; + wire [31:0] AXI_30_WSTRB_in; + wire [31:0] AXI_31_WDATA_PARITY_in; + wire [31:0] AXI_31_WSTRB_in; + wire [36:0] AXI_00_ARADDR_in; + wire [36:0] AXI_00_AWADDR_in; + wire [36:0] AXI_01_ARADDR_in; + wire [36:0] AXI_01_AWADDR_in; + wire [36:0] AXI_02_ARADDR_in; + wire [36:0] AXI_02_AWADDR_in; + wire [36:0] AXI_03_ARADDR_in; + wire [36:0] AXI_03_AWADDR_in; + wire [36:0] AXI_04_ARADDR_in; + wire [36:0] AXI_04_AWADDR_in; + wire [36:0] AXI_05_ARADDR_in; + wire [36:0] AXI_05_AWADDR_in; + wire [36:0] AXI_06_ARADDR_in; + wire [36:0] AXI_06_AWADDR_in; + wire [36:0] AXI_07_ARADDR_in; + wire [36:0] AXI_07_AWADDR_in; + wire [36:0] AXI_08_ARADDR_in; + wire [36:0] AXI_08_AWADDR_in; + wire [36:0] AXI_09_ARADDR_in; + wire [36:0] AXI_09_AWADDR_in; + wire [36:0] AXI_10_ARADDR_in; + wire [36:0] AXI_10_AWADDR_in; + wire [36:0] AXI_11_ARADDR_in; + wire [36:0] AXI_11_AWADDR_in; + wire [36:0] AXI_12_ARADDR_in; + wire [36:0] AXI_12_AWADDR_in; + wire [36:0] AXI_13_ARADDR_in; + wire [36:0] AXI_13_AWADDR_in; + wire [36:0] AXI_14_ARADDR_in; + wire [36:0] AXI_14_AWADDR_in; + wire [36:0] AXI_15_ARADDR_in; + wire [36:0] AXI_15_AWADDR_in; + wire [36:0] AXI_16_ARADDR_in; + wire [36:0] AXI_16_AWADDR_in; + wire [36:0] AXI_17_ARADDR_in; + wire [36:0] AXI_17_AWADDR_in; + wire [36:0] AXI_18_ARADDR_in; + wire [36:0] AXI_18_AWADDR_in; + wire [36:0] AXI_19_ARADDR_in; + wire [36:0] AXI_19_AWADDR_in; + wire [36:0] AXI_20_ARADDR_in; + wire [36:0] AXI_20_AWADDR_in; + wire [36:0] AXI_21_ARADDR_in; + wire [36:0] AXI_21_AWADDR_in; + wire [36:0] AXI_22_ARADDR_in; + wire [36:0] AXI_22_AWADDR_in; + wire [36:0] AXI_23_ARADDR_in; + wire [36:0] AXI_23_AWADDR_in; + wire [36:0] AXI_24_ARADDR_in; + wire [36:0] AXI_24_AWADDR_in; + wire [36:0] AXI_25_ARADDR_in; + wire [36:0] AXI_25_AWADDR_in; + wire [36:0] AXI_26_ARADDR_in; + wire [36:0] AXI_26_AWADDR_in; + wire [36:0] AXI_27_ARADDR_in; + wire [36:0] AXI_27_AWADDR_in; + wire [36:0] AXI_28_ARADDR_in; + wire [36:0] AXI_28_AWADDR_in; + wire [36:0] AXI_29_ARADDR_in; + wire [36:0] AXI_29_AWADDR_in; + wire [36:0] AXI_30_ARADDR_in; + wire [36:0] AXI_30_AWADDR_in; + wire [36:0] AXI_31_ARADDR_in; + wire [36:0] AXI_31_AWADDR_in; + wire [3:0] AXI_00_ARLEN_in; + wire [3:0] AXI_00_AWLEN_in; + wire [3:0] AXI_01_ARLEN_in; + wire [3:0] AXI_01_AWLEN_in; + wire [3:0] AXI_02_ARLEN_in; + wire [3:0] AXI_02_AWLEN_in; + wire [3:0] AXI_03_ARLEN_in; + wire [3:0] AXI_03_AWLEN_in; + wire [3:0] AXI_04_ARLEN_in; + wire [3:0] AXI_04_AWLEN_in; + wire [3:0] AXI_05_ARLEN_in; + wire [3:0] AXI_05_AWLEN_in; + wire [3:0] AXI_06_ARLEN_in; + wire [3:0] AXI_06_AWLEN_in; + wire [3:0] AXI_07_ARLEN_in; + wire [3:0] AXI_07_AWLEN_in; + wire [3:0] AXI_08_ARLEN_in; + wire [3:0] AXI_08_AWLEN_in; + wire [3:0] AXI_09_ARLEN_in; + wire [3:0] AXI_09_AWLEN_in; + wire [3:0] AXI_10_ARLEN_in; + wire [3:0] AXI_10_AWLEN_in; + wire [3:0] AXI_11_ARLEN_in; + wire [3:0] AXI_11_AWLEN_in; + wire [3:0] AXI_12_ARLEN_in; + wire [3:0] AXI_12_AWLEN_in; + wire [3:0] AXI_13_ARLEN_in; + wire [3:0] AXI_13_AWLEN_in; + wire [3:0] AXI_14_ARLEN_in; + wire [3:0] AXI_14_AWLEN_in; + wire [3:0] AXI_15_ARLEN_in; + wire [3:0] AXI_15_AWLEN_in; + wire [3:0] AXI_16_ARLEN_in; + wire [3:0] AXI_16_AWLEN_in; + wire [3:0] AXI_17_ARLEN_in; + wire [3:0] AXI_17_AWLEN_in; + wire [3:0] AXI_18_ARLEN_in; + wire [3:0] AXI_18_AWLEN_in; + wire [3:0] AXI_19_ARLEN_in; + wire [3:0] AXI_19_AWLEN_in; + wire [3:0] AXI_20_ARLEN_in; + wire [3:0] AXI_20_AWLEN_in; + wire [3:0] AXI_21_ARLEN_in; + wire [3:0] AXI_21_AWLEN_in; + wire [3:0] AXI_22_ARLEN_in; + wire [3:0] AXI_22_AWLEN_in; + wire [3:0] AXI_23_ARLEN_in; + wire [3:0] AXI_23_AWLEN_in; + wire [3:0] AXI_24_ARLEN_in; + wire [3:0] AXI_24_AWLEN_in; + wire [3:0] AXI_25_ARLEN_in; + wire [3:0] AXI_25_AWLEN_in; + wire [3:0] AXI_26_ARLEN_in; + wire [3:0] AXI_26_AWLEN_in; + wire [3:0] AXI_27_ARLEN_in; + wire [3:0] AXI_27_AWLEN_in; + wire [3:0] AXI_28_ARLEN_in; + wire [3:0] AXI_28_AWLEN_in; + wire [3:0] AXI_29_ARLEN_in; + wire [3:0] AXI_29_AWLEN_in; + wire [3:0] AXI_30_ARLEN_in; + wire [3:0] AXI_30_AWLEN_in; + wire [3:0] AXI_31_ARLEN_in; + wire [3:0] AXI_31_AWLEN_in; + wire [5:0] AXI_00_ARID_in; + wire [5:0] AXI_00_AWID_in; + wire [5:0] AXI_01_ARID_in; + wire [5:0] AXI_01_AWID_in; + wire [5:0] AXI_02_ARID_in; + wire [5:0] AXI_02_AWID_in; + wire [5:0] AXI_03_ARID_in; + wire [5:0] AXI_03_AWID_in; + wire [5:0] AXI_04_ARID_in; + wire [5:0] AXI_04_AWID_in; + wire [5:0] AXI_05_ARID_in; + wire [5:0] AXI_05_AWID_in; + wire [5:0] AXI_06_ARID_in; + wire [5:0] AXI_06_AWID_in; + wire [5:0] AXI_07_ARID_in; + wire [5:0] AXI_07_AWID_in; + wire [5:0] AXI_08_ARID_in; + wire [5:0] AXI_08_AWID_in; + wire [5:0] AXI_09_ARID_in; + wire [5:0] AXI_09_AWID_in; + wire [5:0] AXI_10_ARID_in; + wire [5:0] AXI_10_AWID_in; + wire [5:0] AXI_11_ARID_in; + wire [5:0] AXI_11_AWID_in; + wire [5:0] AXI_12_ARID_in; + wire [5:0] AXI_12_AWID_in; + wire [5:0] AXI_13_ARID_in; + wire [5:0] AXI_13_AWID_in; + wire [5:0] AXI_14_ARID_in; + wire [5:0] AXI_14_AWID_in; + wire [5:0] AXI_15_ARID_in; + wire [5:0] AXI_15_AWID_in; + wire [5:0] AXI_16_ARID_in; + wire [5:0] AXI_16_AWID_in; + wire [5:0] AXI_17_ARID_in; + wire [5:0] AXI_17_AWID_in; + wire [5:0] AXI_18_ARID_in; + wire [5:0] AXI_18_AWID_in; + wire [5:0] AXI_19_ARID_in; + wire [5:0] AXI_19_AWID_in; + wire [5:0] AXI_20_ARID_in; + wire [5:0] AXI_20_AWID_in; + wire [5:0] AXI_21_ARID_in; + wire [5:0] AXI_21_AWID_in; + wire [5:0] AXI_22_ARID_in; + wire [5:0] AXI_22_AWID_in; + wire [5:0] AXI_23_ARID_in; + wire [5:0] AXI_23_AWID_in; + wire [5:0] AXI_24_ARID_in; + wire [5:0] AXI_24_AWID_in; + wire [5:0] AXI_25_ARID_in; + wire [5:0] AXI_25_AWID_in; + wire [5:0] AXI_26_ARID_in; + wire [5:0] AXI_26_AWID_in; + wire [5:0] AXI_27_ARID_in; + wire [5:0] AXI_27_AWID_in; + wire [5:0] AXI_28_ARID_in; + wire [5:0] AXI_28_AWID_in; + wire [5:0] AXI_29_ARID_in; + wire [5:0] AXI_29_AWID_in; + wire [5:0] AXI_30_ARID_in; + wire [5:0] AXI_30_AWID_in; + wire [5:0] AXI_31_ARID_in; + wire [5:0] AXI_31_AWID_in; + wire [7:0] BLI_SCAN_IN_00_in; + wire [7:0] BLI_SCAN_IN_01_in; + wire [7:0] BLI_SCAN_IN_02_in; + wire [7:0] BLI_SCAN_IN_03_in; + wire [7:0] BLI_SCAN_IN_04_in; + wire [7:0] BLI_SCAN_IN_05_in; + wire [7:0] BLI_SCAN_IN_06_in; + wire [7:0] BLI_SCAN_IN_07_in; + wire [7:0] BLI_SCAN_IN_08_in; + wire [7:0] BLI_SCAN_IN_09_in; + wire [7:0] BLI_SCAN_IN_10_in; + wire [7:0] BLI_SCAN_IN_11_in; + wire [7:0] BLI_SCAN_IN_12_in; + wire [7:0] BLI_SCAN_IN_13_in; + wire [7:0] BLI_SCAN_IN_14_in; + wire [7:0] BLI_SCAN_IN_15_in; + wire [7:0] BLI_SCAN_IN_16_in; + wire [7:0] BLI_SCAN_IN_17_in; + wire [7:0] BLI_SCAN_IN_18_in; + wire [7:0] BLI_SCAN_IN_19_in; + wire [7:0] BLI_SCAN_IN_20_in; + wire [7:0] BLI_SCAN_IN_21_in; + wire [7:0] BLI_SCAN_IN_22_in; + wire [7:0] BLI_SCAN_IN_23_in; + wire [7:0] BLI_SCAN_IN_24_in; + wire [7:0] BLI_SCAN_IN_25_in; + wire [7:0] BLI_SCAN_IN_26_in; + wire [7:0] BLI_SCAN_IN_27_in; + wire [7:0] BLI_SCAN_IN_28_in; + wire [7:0] BLI_SCAN_IN_29_in; + wire [7:0] BLI_SCAN_IN_30_in; + wire [7:0] BLI_SCAN_IN_31_in; + + assign APB_0_PRDATA = APB_0_PRDATA_out; + assign APB_0_PREADY = APB_0_PREADY_out; + assign APB_0_PSLVERR = APB_0_PSLVERR_out; + assign APB_1_PRDATA = APB_1_PRDATA_out; + assign APB_1_PREADY = APB_1_PREADY_out; + assign APB_1_PSLVERR = APB_1_PSLVERR_out; + assign AXI_00_ARREADY = AXI_00_ARREADY_out; + assign AXI_00_AWREADY = AXI_00_AWREADY_out; + assign AXI_00_BID = AXI_00_BID_out; + assign AXI_00_BRESP = AXI_00_BRESP_out; + assign AXI_00_BVALID = AXI_00_BVALID_out; + assign AXI_00_DFI_AW_AERR_N = AXI_00_DFI_AW_AERR_N_out; + assign AXI_00_DFI_CLK_BUF = AXI_00_DFI_CLK_BUF_out; + assign AXI_00_DFI_DBI_BYTE_DISABLE = AXI_00_DFI_DBI_BYTE_DISABLE_out; + assign AXI_00_DFI_DW_RDDATA_DBI = AXI_00_DFI_DW_RDDATA_DBI_out; + assign AXI_00_DFI_DW_RDDATA_DERR = AXI_00_DFI_DW_RDDATA_DERR_out; + assign AXI_00_DFI_DW_RDDATA_VALID = AXI_00_DFI_DW_RDDATA_VALID_out; + assign AXI_00_DFI_INIT_COMPLETE = AXI_00_DFI_INIT_COMPLETE_out; + assign AXI_00_DFI_PHYUPD_REQ = AXI_00_DFI_PHYUPD_REQ_out; + assign AXI_00_DFI_PHY_LP_STATE = AXI_00_DFI_PHY_LP_STATE_out; + assign AXI_00_DFI_RST_N_BUF = AXI_00_DFI_RST_N_BUF_out; + assign AXI_00_MC_STATUS = AXI_00_MC_STATUS_out; + assign AXI_00_PHY_STATUS = AXI_00_PHY_STATUS_out; + assign AXI_00_RDATA = AXI_00_RDATA_out; + assign AXI_00_RDATA_PARITY = AXI_00_RDATA_PARITY_out; + assign AXI_00_RID = AXI_00_RID_out; + assign AXI_00_RLAST = AXI_00_RLAST_out; + assign AXI_00_RRESP = AXI_00_RRESP_out; + assign AXI_00_RVALID = AXI_00_RVALID_out; + assign AXI_00_WREADY = AXI_00_WREADY_out; + assign AXI_01_ARREADY = AXI_01_ARREADY_out; + assign AXI_01_AWREADY = AXI_01_AWREADY_out; + assign AXI_01_BID = AXI_01_BID_out; + assign AXI_01_BRESP = AXI_01_BRESP_out; + assign AXI_01_BVALID = AXI_01_BVALID_out; + assign AXI_01_DFI_AW_AERR_N = AXI_01_DFI_AW_AERR_N_out; + assign AXI_01_DFI_CLK_BUF = AXI_01_DFI_CLK_BUF_out; + assign AXI_01_DFI_DBI_BYTE_DISABLE = AXI_01_DFI_DBI_BYTE_DISABLE_out; + assign AXI_01_DFI_DW_RDDATA_DBI = AXI_01_DFI_DW_RDDATA_DBI_out; + assign AXI_01_DFI_DW_RDDATA_DERR = AXI_01_DFI_DW_RDDATA_DERR_out; + assign AXI_01_DFI_DW_RDDATA_VALID = AXI_01_DFI_DW_RDDATA_VALID_out; + assign AXI_01_DFI_INIT_COMPLETE = AXI_01_DFI_INIT_COMPLETE_out; + assign AXI_01_DFI_PHYUPD_REQ = AXI_01_DFI_PHYUPD_REQ_out; + assign AXI_01_DFI_PHY_LP_STATE = AXI_01_DFI_PHY_LP_STATE_out; + assign AXI_01_DFI_RST_N_BUF = AXI_01_DFI_RST_N_BUF_out; + assign AXI_01_RDATA = AXI_01_RDATA_out; + assign AXI_01_RDATA_PARITY = AXI_01_RDATA_PARITY_out; + assign AXI_01_RID = AXI_01_RID_out; + assign AXI_01_RLAST = AXI_01_RLAST_out; + assign AXI_01_RRESP = AXI_01_RRESP_out; + assign AXI_01_RVALID = AXI_01_RVALID_out; + assign AXI_01_WREADY = AXI_01_WREADY_out; + assign AXI_02_ARREADY = AXI_02_ARREADY_out; + assign AXI_02_AWREADY = AXI_02_AWREADY_out; + assign AXI_02_BID = AXI_02_BID_out; + assign AXI_02_BRESP = AXI_02_BRESP_out; + assign AXI_02_BVALID = AXI_02_BVALID_out; + assign AXI_02_DFI_AW_AERR_N = AXI_02_DFI_AW_AERR_N_out; + assign AXI_02_DFI_CLK_BUF = AXI_02_DFI_CLK_BUF_out; + assign AXI_02_DFI_DBI_BYTE_DISABLE = AXI_02_DFI_DBI_BYTE_DISABLE_out; + assign AXI_02_DFI_DW_RDDATA_DBI = AXI_02_DFI_DW_RDDATA_DBI_out; + assign AXI_02_DFI_DW_RDDATA_DERR = AXI_02_DFI_DW_RDDATA_DERR_out; + assign AXI_02_DFI_DW_RDDATA_VALID = AXI_02_DFI_DW_RDDATA_VALID_out; + assign AXI_02_DFI_INIT_COMPLETE = AXI_02_DFI_INIT_COMPLETE_out; + assign AXI_02_DFI_PHYUPD_REQ = AXI_02_DFI_PHYUPD_REQ_out; + assign AXI_02_DFI_PHY_LP_STATE = AXI_02_DFI_PHY_LP_STATE_out; + assign AXI_02_DFI_RST_N_BUF = AXI_02_DFI_RST_N_BUF_out; + assign AXI_02_MC_STATUS = AXI_02_MC_STATUS_out; + assign AXI_02_PHY_STATUS = AXI_02_PHY_STATUS_out; + assign AXI_02_RDATA = AXI_02_RDATA_out; + assign AXI_02_RDATA_PARITY = AXI_02_RDATA_PARITY_out; + assign AXI_02_RID = AXI_02_RID_out; + assign AXI_02_RLAST = AXI_02_RLAST_out; + assign AXI_02_RRESP = AXI_02_RRESP_out; + assign AXI_02_RVALID = AXI_02_RVALID_out; + assign AXI_02_WREADY = AXI_02_WREADY_out; + assign AXI_03_ARREADY = AXI_03_ARREADY_out; + assign AXI_03_AWREADY = AXI_03_AWREADY_out; + assign AXI_03_BID = AXI_03_BID_out; + assign AXI_03_BRESP = AXI_03_BRESP_out; + assign AXI_03_BVALID = AXI_03_BVALID_out; + assign AXI_03_DFI_AW_AERR_N = AXI_03_DFI_AW_AERR_N_out; + assign AXI_03_DFI_CLK_BUF = AXI_03_DFI_CLK_BUF_out; + assign AXI_03_DFI_DBI_BYTE_DISABLE = AXI_03_DFI_DBI_BYTE_DISABLE_out; + assign AXI_03_DFI_DW_RDDATA_DBI = AXI_03_DFI_DW_RDDATA_DBI_out; + assign AXI_03_DFI_DW_RDDATA_DERR = AXI_03_DFI_DW_RDDATA_DERR_out; + assign AXI_03_DFI_DW_RDDATA_VALID = AXI_03_DFI_DW_RDDATA_VALID_out; + assign AXI_03_DFI_INIT_COMPLETE = AXI_03_DFI_INIT_COMPLETE_out; + assign AXI_03_DFI_PHYUPD_REQ = AXI_03_DFI_PHYUPD_REQ_out; + assign AXI_03_DFI_PHY_LP_STATE = AXI_03_DFI_PHY_LP_STATE_out; + assign AXI_03_DFI_RST_N_BUF = AXI_03_DFI_RST_N_BUF_out; + assign AXI_03_RDATA = AXI_03_RDATA_out; + assign AXI_03_RDATA_PARITY = AXI_03_RDATA_PARITY_out; + assign AXI_03_RID = AXI_03_RID_out; + assign AXI_03_RLAST = AXI_03_RLAST_out; + assign AXI_03_RRESP = AXI_03_RRESP_out; + assign AXI_03_RVALID = AXI_03_RVALID_out; + assign AXI_03_WREADY = AXI_03_WREADY_out; + assign AXI_04_ARREADY = AXI_04_ARREADY_out; + assign AXI_04_AWREADY = AXI_04_AWREADY_out; + assign AXI_04_BID = AXI_04_BID_out; + assign AXI_04_BRESP = AXI_04_BRESP_out; + assign AXI_04_BVALID = AXI_04_BVALID_out; + assign AXI_04_DFI_AW_AERR_N = AXI_04_DFI_AW_AERR_N_out; + assign AXI_04_DFI_CLK_BUF = AXI_04_DFI_CLK_BUF_out; + assign AXI_04_DFI_DBI_BYTE_DISABLE = AXI_04_DFI_DBI_BYTE_DISABLE_out; + assign AXI_04_DFI_DW_RDDATA_DBI = AXI_04_DFI_DW_RDDATA_DBI_out; + assign AXI_04_DFI_DW_RDDATA_DERR = AXI_04_DFI_DW_RDDATA_DERR_out; + assign AXI_04_DFI_DW_RDDATA_VALID = AXI_04_DFI_DW_RDDATA_VALID_out; + assign AXI_04_DFI_INIT_COMPLETE = AXI_04_DFI_INIT_COMPLETE_out; + assign AXI_04_DFI_PHYUPD_REQ = AXI_04_DFI_PHYUPD_REQ_out; + assign AXI_04_DFI_PHY_LP_STATE = AXI_04_DFI_PHY_LP_STATE_out; + assign AXI_04_DFI_RST_N_BUF = AXI_04_DFI_RST_N_BUF_out; + assign AXI_04_MC_STATUS = AXI_04_MC_STATUS_out; + assign AXI_04_PHY_STATUS = AXI_04_PHY_STATUS_out; + assign AXI_04_RDATA = AXI_04_RDATA_out; + assign AXI_04_RDATA_PARITY = AXI_04_RDATA_PARITY_out; + assign AXI_04_RID = AXI_04_RID_out; + assign AXI_04_RLAST = AXI_04_RLAST_out; + assign AXI_04_RRESP = AXI_04_RRESP_out; + assign AXI_04_RVALID = AXI_04_RVALID_out; + assign AXI_04_WREADY = AXI_04_WREADY_out; + assign AXI_05_ARREADY = AXI_05_ARREADY_out; + assign AXI_05_AWREADY = AXI_05_AWREADY_out; + assign AXI_05_BID = AXI_05_BID_out; + assign AXI_05_BRESP = AXI_05_BRESP_out; + assign AXI_05_BVALID = AXI_05_BVALID_out; + assign AXI_05_DFI_AW_AERR_N = AXI_05_DFI_AW_AERR_N_out; + assign AXI_05_DFI_CLK_BUF = AXI_05_DFI_CLK_BUF_out; + assign AXI_05_DFI_DBI_BYTE_DISABLE = AXI_05_DFI_DBI_BYTE_DISABLE_out; + assign AXI_05_DFI_DW_RDDATA_DBI = AXI_05_DFI_DW_RDDATA_DBI_out; + assign AXI_05_DFI_DW_RDDATA_DERR = AXI_05_DFI_DW_RDDATA_DERR_out; + assign AXI_05_DFI_DW_RDDATA_VALID = AXI_05_DFI_DW_RDDATA_VALID_out; + assign AXI_05_DFI_INIT_COMPLETE = AXI_05_DFI_INIT_COMPLETE_out; + assign AXI_05_DFI_PHYUPD_REQ = AXI_05_DFI_PHYUPD_REQ_out; + assign AXI_05_DFI_PHY_LP_STATE = AXI_05_DFI_PHY_LP_STATE_out; + assign AXI_05_DFI_RST_N_BUF = AXI_05_DFI_RST_N_BUF_out; + assign AXI_05_RDATA = AXI_05_RDATA_out; + assign AXI_05_RDATA_PARITY = AXI_05_RDATA_PARITY_out; + assign AXI_05_RID = AXI_05_RID_out; + assign AXI_05_RLAST = AXI_05_RLAST_out; + assign AXI_05_RRESP = AXI_05_RRESP_out; + assign AXI_05_RVALID = AXI_05_RVALID_out; + assign AXI_05_WREADY = AXI_05_WREADY_out; + assign AXI_06_ARREADY = AXI_06_ARREADY_out; + assign AXI_06_AWREADY = AXI_06_AWREADY_out; + assign AXI_06_BID = AXI_06_BID_out; + assign AXI_06_BRESP = AXI_06_BRESP_out; + assign AXI_06_BVALID = AXI_06_BVALID_out; + assign AXI_06_DFI_AW_AERR_N = AXI_06_DFI_AW_AERR_N_out; + assign AXI_06_DFI_CLK_BUF = AXI_06_DFI_CLK_BUF_out; + assign AXI_06_DFI_DBI_BYTE_DISABLE = AXI_06_DFI_DBI_BYTE_DISABLE_out; + assign AXI_06_DFI_DW_RDDATA_DBI = AXI_06_DFI_DW_RDDATA_DBI_out; + assign AXI_06_DFI_DW_RDDATA_DERR = AXI_06_DFI_DW_RDDATA_DERR_out; + assign AXI_06_DFI_DW_RDDATA_VALID = AXI_06_DFI_DW_RDDATA_VALID_out; + assign AXI_06_DFI_INIT_COMPLETE = AXI_06_DFI_INIT_COMPLETE_out; + assign AXI_06_DFI_PHYUPD_REQ = AXI_06_DFI_PHYUPD_REQ_out; + assign AXI_06_DFI_PHY_LP_STATE = AXI_06_DFI_PHY_LP_STATE_out; + assign AXI_06_DFI_RST_N_BUF = AXI_06_DFI_RST_N_BUF_out; + assign AXI_06_MC_STATUS = AXI_06_MC_STATUS_out; + assign AXI_06_PHY_STATUS = AXI_06_PHY_STATUS_out; + assign AXI_06_RDATA = AXI_06_RDATA_out; + assign AXI_06_RDATA_PARITY = AXI_06_RDATA_PARITY_out; + assign AXI_06_RID = AXI_06_RID_out; + assign AXI_06_RLAST = AXI_06_RLAST_out; + assign AXI_06_RRESP = AXI_06_RRESP_out; + assign AXI_06_RVALID = AXI_06_RVALID_out; + assign AXI_06_WREADY = AXI_06_WREADY_out; + assign AXI_07_ARREADY = AXI_07_ARREADY_out; + assign AXI_07_AWREADY = AXI_07_AWREADY_out; + assign AXI_07_BID = AXI_07_BID_out; + assign AXI_07_BRESP = AXI_07_BRESP_out; + assign AXI_07_BVALID = AXI_07_BVALID_out; + assign AXI_07_DFI_AW_AERR_N = AXI_07_DFI_AW_AERR_N_out; + assign AXI_07_DFI_CLK_BUF = AXI_07_DFI_CLK_BUF_out; + assign AXI_07_DFI_DBI_BYTE_DISABLE = AXI_07_DFI_DBI_BYTE_DISABLE_out; + assign AXI_07_DFI_DW_RDDATA_DBI = AXI_07_DFI_DW_RDDATA_DBI_out; + assign AXI_07_DFI_DW_RDDATA_DERR = AXI_07_DFI_DW_RDDATA_DERR_out; + assign AXI_07_DFI_DW_RDDATA_VALID = AXI_07_DFI_DW_RDDATA_VALID_out; + assign AXI_07_DFI_INIT_COMPLETE = AXI_07_DFI_INIT_COMPLETE_out; + assign AXI_07_DFI_PHYUPD_REQ = AXI_07_DFI_PHYUPD_REQ_out; + assign AXI_07_DFI_PHY_LP_STATE = AXI_07_DFI_PHY_LP_STATE_out; + assign AXI_07_DFI_RST_N_BUF = AXI_07_DFI_RST_N_BUF_out; + assign AXI_07_RDATA = AXI_07_RDATA_out; + assign AXI_07_RDATA_PARITY = AXI_07_RDATA_PARITY_out; + assign AXI_07_RID = AXI_07_RID_out; + assign AXI_07_RLAST = AXI_07_RLAST_out; + assign AXI_07_RRESP = AXI_07_RRESP_out; + assign AXI_07_RVALID = AXI_07_RVALID_out; + assign AXI_07_WREADY = AXI_07_WREADY_out; + assign AXI_08_ARREADY = AXI_08_ARREADY_out; + assign AXI_08_AWREADY = AXI_08_AWREADY_out; + assign AXI_08_BID = AXI_08_BID_out; + assign AXI_08_BRESP = AXI_08_BRESP_out; + assign AXI_08_BVALID = AXI_08_BVALID_out; + assign AXI_08_DFI_AW_AERR_N = AXI_08_DFI_AW_AERR_N_out; + assign AXI_08_DFI_CLK_BUF = AXI_08_DFI_CLK_BUF_out; + assign AXI_08_DFI_DBI_BYTE_DISABLE = AXI_08_DFI_DBI_BYTE_DISABLE_out; + assign AXI_08_DFI_DW_RDDATA_DBI = AXI_08_DFI_DW_RDDATA_DBI_out; + assign AXI_08_DFI_DW_RDDATA_DERR = AXI_08_DFI_DW_RDDATA_DERR_out; + assign AXI_08_DFI_DW_RDDATA_VALID = AXI_08_DFI_DW_RDDATA_VALID_out; + assign AXI_08_DFI_INIT_COMPLETE = AXI_08_DFI_INIT_COMPLETE_out; + assign AXI_08_DFI_PHYUPD_REQ = AXI_08_DFI_PHYUPD_REQ_out; + assign AXI_08_DFI_PHY_LP_STATE = AXI_08_DFI_PHY_LP_STATE_out; + assign AXI_08_DFI_RST_N_BUF = AXI_08_DFI_RST_N_BUF_out; + assign AXI_08_MC_STATUS = AXI_08_MC_STATUS_out; + assign AXI_08_PHY_STATUS = AXI_08_PHY_STATUS_out; + assign AXI_08_RDATA = AXI_08_RDATA_out; + assign AXI_08_RDATA_PARITY = AXI_08_RDATA_PARITY_out; + assign AXI_08_RID = AXI_08_RID_out; + assign AXI_08_RLAST = AXI_08_RLAST_out; + assign AXI_08_RRESP = AXI_08_RRESP_out; + assign AXI_08_RVALID = AXI_08_RVALID_out; + assign AXI_08_WREADY = AXI_08_WREADY_out; + assign AXI_09_ARREADY = AXI_09_ARREADY_out; + assign AXI_09_AWREADY = AXI_09_AWREADY_out; + assign AXI_09_BID = AXI_09_BID_out; + assign AXI_09_BRESP = AXI_09_BRESP_out; + assign AXI_09_BVALID = AXI_09_BVALID_out; + assign AXI_09_DFI_AW_AERR_N = AXI_09_DFI_AW_AERR_N_out; + assign AXI_09_DFI_CLK_BUF = AXI_09_DFI_CLK_BUF_out; + assign AXI_09_DFI_DBI_BYTE_DISABLE = AXI_09_DFI_DBI_BYTE_DISABLE_out; + assign AXI_09_DFI_DW_RDDATA_DBI = AXI_09_DFI_DW_RDDATA_DBI_out; + assign AXI_09_DFI_DW_RDDATA_DERR = AXI_09_DFI_DW_RDDATA_DERR_out; + assign AXI_09_DFI_DW_RDDATA_VALID = AXI_09_DFI_DW_RDDATA_VALID_out; + assign AXI_09_DFI_INIT_COMPLETE = AXI_09_DFI_INIT_COMPLETE_out; + assign AXI_09_DFI_PHYUPD_REQ = AXI_09_DFI_PHYUPD_REQ_out; + assign AXI_09_DFI_PHY_LP_STATE = AXI_09_DFI_PHY_LP_STATE_out; + assign AXI_09_DFI_RST_N_BUF = AXI_09_DFI_RST_N_BUF_out; + assign AXI_09_RDATA = AXI_09_RDATA_out; + assign AXI_09_RDATA_PARITY = AXI_09_RDATA_PARITY_out; + assign AXI_09_RID = AXI_09_RID_out; + assign AXI_09_RLAST = AXI_09_RLAST_out; + assign AXI_09_RRESP = AXI_09_RRESP_out; + assign AXI_09_RVALID = AXI_09_RVALID_out; + assign AXI_09_WREADY = AXI_09_WREADY_out; + assign AXI_10_ARREADY = AXI_10_ARREADY_out; + assign AXI_10_AWREADY = AXI_10_AWREADY_out; + assign AXI_10_BID = AXI_10_BID_out; + assign AXI_10_BRESP = AXI_10_BRESP_out; + assign AXI_10_BVALID = AXI_10_BVALID_out; + assign AXI_10_DFI_AW_AERR_N = AXI_10_DFI_AW_AERR_N_out; + assign AXI_10_DFI_CLK_BUF = AXI_10_DFI_CLK_BUF_out; + assign AXI_10_DFI_DBI_BYTE_DISABLE = AXI_10_DFI_DBI_BYTE_DISABLE_out; + assign AXI_10_DFI_DW_RDDATA_DBI = AXI_10_DFI_DW_RDDATA_DBI_out; + assign AXI_10_DFI_DW_RDDATA_DERR = AXI_10_DFI_DW_RDDATA_DERR_out; + assign AXI_10_DFI_DW_RDDATA_VALID = AXI_10_DFI_DW_RDDATA_VALID_out; + assign AXI_10_DFI_INIT_COMPLETE = AXI_10_DFI_INIT_COMPLETE_out; + assign AXI_10_DFI_PHYUPD_REQ = AXI_10_DFI_PHYUPD_REQ_out; + assign AXI_10_DFI_PHY_LP_STATE = AXI_10_DFI_PHY_LP_STATE_out; + assign AXI_10_DFI_RST_N_BUF = AXI_10_DFI_RST_N_BUF_out; + assign AXI_10_MC_STATUS = AXI_10_MC_STATUS_out; + assign AXI_10_PHY_STATUS = AXI_10_PHY_STATUS_out; + assign AXI_10_RDATA = AXI_10_RDATA_out; + assign AXI_10_RDATA_PARITY = AXI_10_RDATA_PARITY_out; + assign AXI_10_RID = AXI_10_RID_out; + assign AXI_10_RLAST = AXI_10_RLAST_out; + assign AXI_10_RRESP = AXI_10_RRESP_out; + assign AXI_10_RVALID = AXI_10_RVALID_out; + assign AXI_10_WREADY = AXI_10_WREADY_out; + assign AXI_11_ARREADY = AXI_11_ARREADY_out; + assign AXI_11_AWREADY = AXI_11_AWREADY_out; + assign AXI_11_BID = AXI_11_BID_out; + assign AXI_11_BRESP = AXI_11_BRESP_out; + assign AXI_11_BVALID = AXI_11_BVALID_out; + assign AXI_11_DFI_AW_AERR_N = AXI_11_DFI_AW_AERR_N_out; + assign AXI_11_DFI_CLK_BUF = AXI_11_DFI_CLK_BUF_out; + assign AXI_11_DFI_DBI_BYTE_DISABLE = AXI_11_DFI_DBI_BYTE_DISABLE_out; + assign AXI_11_DFI_DW_RDDATA_DBI = AXI_11_DFI_DW_RDDATA_DBI_out; + assign AXI_11_DFI_DW_RDDATA_DERR = AXI_11_DFI_DW_RDDATA_DERR_out; + assign AXI_11_DFI_DW_RDDATA_VALID = AXI_11_DFI_DW_RDDATA_VALID_out; + assign AXI_11_DFI_INIT_COMPLETE = AXI_11_DFI_INIT_COMPLETE_out; + assign AXI_11_DFI_PHYUPD_REQ = AXI_11_DFI_PHYUPD_REQ_out; + assign AXI_11_DFI_PHY_LP_STATE = AXI_11_DFI_PHY_LP_STATE_out; + assign AXI_11_DFI_RST_N_BUF = AXI_11_DFI_RST_N_BUF_out; + assign AXI_11_RDATA = AXI_11_RDATA_out; + assign AXI_11_RDATA_PARITY = AXI_11_RDATA_PARITY_out; + assign AXI_11_RID = AXI_11_RID_out; + assign AXI_11_RLAST = AXI_11_RLAST_out; + assign AXI_11_RRESP = AXI_11_RRESP_out; + assign AXI_11_RVALID = AXI_11_RVALID_out; + assign AXI_11_WREADY = AXI_11_WREADY_out; + assign AXI_12_ARREADY = AXI_12_ARREADY_out; + assign AXI_12_AWREADY = AXI_12_AWREADY_out; + assign AXI_12_BID = AXI_12_BID_out; + assign AXI_12_BRESP = AXI_12_BRESP_out; + assign AXI_12_BVALID = AXI_12_BVALID_out; + assign AXI_12_DFI_AW_AERR_N = AXI_12_DFI_AW_AERR_N_out; + assign AXI_12_DFI_CLK_BUF = AXI_12_DFI_CLK_BUF_out; + assign AXI_12_DFI_DBI_BYTE_DISABLE = AXI_12_DFI_DBI_BYTE_DISABLE_out; + assign AXI_12_DFI_DW_RDDATA_DBI = AXI_12_DFI_DW_RDDATA_DBI_out; + assign AXI_12_DFI_DW_RDDATA_DERR = AXI_12_DFI_DW_RDDATA_DERR_out; + assign AXI_12_DFI_DW_RDDATA_VALID = AXI_12_DFI_DW_RDDATA_VALID_out; + assign AXI_12_DFI_INIT_COMPLETE = AXI_12_DFI_INIT_COMPLETE_out; + assign AXI_12_DFI_PHYUPD_REQ = AXI_12_DFI_PHYUPD_REQ_out; + assign AXI_12_DFI_PHY_LP_STATE = AXI_12_DFI_PHY_LP_STATE_out; + assign AXI_12_DFI_RST_N_BUF = AXI_12_DFI_RST_N_BUF_out; + assign AXI_12_MC_STATUS = AXI_12_MC_STATUS_out; + assign AXI_12_PHY_STATUS = AXI_12_PHY_STATUS_out; + assign AXI_12_RDATA = AXI_12_RDATA_out; + assign AXI_12_RDATA_PARITY = AXI_12_RDATA_PARITY_out; + assign AXI_12_RID = AXI_12_RID_out; + assign AXI_12_RLAST = AXI_12_RLAST_out; + assign AXI_12_RRESP = AXI_12_RRESP_out; + assign AXI_12_RVALID = AXI_12_RVALID_out; + assign AXI_12_WREADY = AXI_12_WREADY_out; + assign AXI_13_ARREADY = AXI_13_ARREADY_out; + assign AXI_13_AWREADY = AXI_13_AWREADY_out; + assign AXI_13_BID = AXI_13_BID_out; + assign AXI_13_BRESP = AXI_13_BRESP_out; + assign AXI_13_BVALID = AXI_13_BVALID_out; + assign AXI_13_DFI_AW_AERR_N = AXI_13_DFI_AW_AERR_N_out; + assign AXI_13_DFI_CLK_BUF = AXI_13_DFI_CLK_BUF_out; + assign AXI_13_DFI_DBI_BYTE_DISABLE = AXI_13_DFI_DBI_BYTE_DISABLE_out; + assign AXI_13_DFI_DW_RDDATA_DBI = AXI_13_DFI_DW_RDDATA_DBI_out; + assign AXI_13_DFI_DW_RDDATA_DERR = AXI_13_DFI_DW_RDDATA_DERR_out; + assign AXI_13_DFI_DW_RDDATA_VALID = AXI_13_DFI_DW_RDDATA_VALID_out; + assign AXI_13_DFI_INIT_COMPLETE = AXI_13_DFI_INIT_COMPLETE_out; + assign AXI_13_DFI_PHYUPD_REQ = AXI_13_DFI_PHYUPD_REQ_out; + assign AXI_13_DFI_PHY_LP_STATE = AXI_13_DFI_PHY_LP_STATE_out; + assign AXI_13_DFI_RST_N_BUF = AXI_13_DFI_RST_N_BUF_out; + assign AXI_13_RDATA = AXI_13_RDATA_out; + assign AXI_13_RDATA_PARITY = AXI_13_RDATA_PARITY_out; + assign AXI_13_RID = AXI_13_RID_out; + assign AXI_13_RLAST = AXI_13_RLAST_out; + assign AXI_13_RRESP = AXI_13_RRESP_out; + assign AXI_13_RVALID = AXI_13_RVALID_out; + assign AXI_13_WREADY = AXI_13_WREADY_out; + assign AXI_14_ARREADY = AXI_14_ARREADY_out; + assign AXI_14_AWREADY = AXI_14_AWREADY_out; + assign AXI_14_BID = AXI_14_BID_out; + assign AXI_14_BRESP = AXI_14_BRESP_out; + assign AXI_14_BVALID = AXI_14_BVALID_out; + assign AXI_14_DFI_AW_AERR_N = AXI_14_DFI_AW_AERR_N_out; + assign AXI_14_DFI_CLK_BUF = AXI_14_DFI_CLK_BUF_out; + assign AXI_14_DFI_DBI_BYTE_DISABLE = AXI_14_DFI_DBI_BYTE_DISABLE_out; + assign AXI_14_DFI_DW_RDDATA_DBI = AXI_14_DFI_DW_RDDATA_DBI_out; + assign AXI_14_DFI_DW_RDDATA_DERR = AXI_14_DFI_DW_RDDATA_DERR_out; + assign AXI_14_DFI_DW_RDDATA_VALID = AXI_14_DFI_DW_RDDATA_VALID_out; + assign AXI_14_DFI_INIT_COMPLETE = AXI_14_DFI_INIT_COMPLETE_out; + assign AXI_14_DFI_PHYUPD_REQ = AXI_14_DFI_PHYUPD_REQ_out; + assign AXI_14_DFI_PHY_LP_STATE = AXI_14_DFI_PHY_LP_STATE_out; + assign AXI_14_DFI_RST_N_BUF = AXI_14_DFI_RST_N_BUF_out; + assign AXI_14_MC_STATUS = AXI_14_MC_STATUS_out; + assign AXI_14_PHY_STATUS = AXI_14_PHY_STATUS_out; + assign AXI_14_RDATA = AXI_14_RDATA_out; + assign AXI_14_RDATA_PARITY = AXI_14_RDATA_PARITY_out; + assign AXI_14_RID = AXI_14_RID_out; + assign AXI_14_RLAST = AXI_14_RLAST_out; + assign AXI_14_RRESP = AXI_14_RRESP_out; + assign AXI_14_RVALID = AXI_14_RVALID_out; + assign AXI_14_WREADY = AXI_14_WREADY_out; + assign AXI_15_ARREADY = AXI_15_ARREADY_out; + assign AXI_15_AWREADY = AXI_15_AWREADY_out; + assign AXI_15_BID = AXI_15_BID_out; + assign AXI_15_BRESP = AXI_15_BRESP_out; + assign AXI_15_BVALID = AXI_15_BVALID_out; + assign AXI_15_DFI_AW_AERR_N = AXI_15_DFI_AW_AERR_N_out; + assign AXI_15_DFI_CLK_BUF = AXI_15_DFI_CLK_BUF_out; + assign AXI_15_DFI_DBI_BYTE_DISABLE = AXI_15_DFI_DBI_BYTE_DISABLE_out; + assign AXI_15_DFI_DW_RDDATA_DBI = AXI_15_DFI_DW_RDDATA_DBI_out; + assign AXI_15_DFI_DW_RDDATA_DERR = AXI_15_DFI_DW_RDDATA_DERR_out; + assign AXI_15_DFI_DW_RDDATA_VALID = AXI_15_DFI_DW_RDDATA_VALID_out; + assign AXI_15_DFI_INIT_COMPLETE = AXI_15_DFI_INIT_COMPLETE_out; + assign AXI_15_DFI_PHYUPD_REQ = AXI_15_DFI_PHYUPD_REQ_out; + assign AXI_15_DFI_PHY_LP_STATE = AXI_15_DFI_PHY_LP_STATE_out; + assign AXI_15_DFI_RST_N_BUF = AXI_15_DFI_RST_N_BUF_out; + assign AXI_15_RDATA = AXI_15_RDATA_out; + assign AXI_15_RDATA_PARITY = AXI_15_RDATA_PARITY_out; + assign AXI_15_RID = AXI_15_RID_out; + assign AXI_15_RLAST = AXI_15_RLAST_out; + assign AXI_15_RRESP = AXI_15_RRESP_out; + assign AXI_15_RVALID = AXI_15_RVALID_out; + assign AXI_15_WREADY = AXI_15_WREADY_out; + assign AXI_16_ARREADY = AXI_16_ARREADY_out; + assign AXI_16_AWREADY = AXI_16_AWREADY_out; + assign AXI_16_BID = AXI_16_BID_out; + assign AXI_16_BRESP = AXI_16_BRESP_out; + assign AXI_16_BVALID = AXI_16_BVALID_out; + assign AXI_16_DFI_AW_AERR_N = AXI_16_DFI_AW_AERR_N_out; + assign AXI_16_DFI_CLK_BUF = AXI_16_DFI_CLK_BUF_out; + assign AXI_16_DFI_DBI_BYTE_DISABLE = AXI_16_DFI_DBI_BYTE_DISABLE_out; + assign AXI_16_DFI_DW_RDDATA_DBI = AXI_16_DFI_DW_RDDATA_DBI_out; + assign AXI_16_DFI_DW_RDDATA_DERR = AXI_16_DFI_DW_RDDATA_DERR_out; + assign AXI_16_DFI_DW_RDDATA_VALID = AXI_16_DFI_DW_RDDATA_VALID_out; + assign AXI_16_DFI_INIT_COMPLETE = AXI_16_DFI_INIT_COMPLETE_out; + assign AXI_16_DFI_PHYUPD_REQ = AXI_16_DFI_PHYUPD_REQ_out; + assign AXI_16_DFI_PHY_LP_STATE = AXI_16_DFI_PHY_LP_STATE_out; + assign AXI_16_DFI_RST_N_BUF = AXI_16_DFI_RST_N_BUF_out; + assign AXI_16_MC_STATUS = AXI_16_MC_STATUS_out; + assign AXI_16_PHY_STATUS = AXI_16_PHY_STATUS_out; + assign AXI_16_RDATA = AXI_16_RDATA_out; + assign AXI_16_RDATA_PARITY = AXI_16_RDATA_PARITY_out; + assign AXI_16_RID = AXI_16_RID_out; + assign AXI_16_RLAST = AXI_16_RLAST_out; + assign AXI_16_RRESP = AXI_16_RRESP_out; + assign AXI_16_RVALID = AXI_16_RVALID_out; + assign AXI_16_WREADY = AXI_16_WREADY_out; + assign AXI_17_ARREADY = AXI_17_ARREADY_out; + assign AXI_17_AWREADY = AXI_17_AWREADY_out; + assign AXI_17_BID = AXI_17_BID_out; + assign AXI_17_BRESP = AXI_17_BRESP_out; + assign AXI_17_BVALID = AXI_17_BVALID_out; + assign AXI_17_DFI_AW_AERR_N = AXI_17_DFI_AW_AERR_N_out; + assign AXI_17_DFI_CLK_BUF = AXI_17_DFI_CLK_BUF_out; + assign AXI_17_DFI_DBI_BYTE_DISABLE = AXI_17_DFI_DBI_BYTE_DISABLE_out; + assign AXI_17_DFI_DW_RDDATA_DBI = AXI_17_DFI_DW_RDDATA_DBI_out; + assign AXI_17_DFI_DW_RDDATA_DERR = AXI_17_DFI_DW_RDDATA_DERR_out; + assign AXI_17_DFI_DW_RDDATA_VALID = AXI_17_DFI_DW_RDDATA_VALID_out; + assign AXI_17_DFI_INIT_COMPLETE = AXI_17_DFI_INIT_COMPLETE_out; + assign AXI_17_DFI_PHYUPD_REQ = AXI_17_DFI_PHYUPD_REQ_out; + assign AXI_17_DFI_PHY_LP_STATE = AXI_17_DFI_PHY_LP_STATE_out; + assign AXI_17_DFI_RST_N_BUF = AXI_17_DFI_RST_N_BUF_out; + assign AXI_17_RDATA = AXI_17_RDATA_out; + assign AXI_17_RDATA_PARITY = AXI_17_RDATA_PARITY_out; + assign AXI_17_RID = AXI_17_RID_out; + assign AXI_17_RLAST = AXI_17_RLAST_out; + assign AXI_17_RRESP = AXI_17_RRESP_out; + assign AXI_17_RVALID = AXI_17_RVALID_out; + assign AXI_17_WREADY = AXI_17_WREADY_out; + assign AXI_18_ARREADY = AXI_18_ARREADY_out; + assign AXI_18_AWREADY = AXI_18_AWREADY_out; + assign AXI_18_BID = AXI_18_BID_out; + assign AXI_18_BRESP = AXI_18_BRESP_out; + assign AXI_18_BVALID = AXI_18_BVALID_out; + assign AXI_18_DFI_AW_AERR_N = AXI_18_DFI_AW_AERR_N_out; + assign AXI_18_DFI_CLK_BUF = AXI_18_DFI_CLK_BUF_out; + assign AXI_18_DFI_DBI_BYTE_DISABLE = AXI_18_DFI_DBI_BYTE_DISABLE_out; + assign AXI_18_DFI_DW_RDDATA_DBI = AXI_18_DFI_DW_RDDATA_DBI_out; + assign AXI_18_DFI_DW_RDDATA_DERR = AXI_18_DFI_DW_RDDATA_DERR_out; + assign AXI_18_DFI_DW_RDDATA_VALID = AXI_18_DFI_DW_RDDATA_VALID_out; + assign AXI_18_DFI_INIT_COMPLETE = AXI_18_DFI_INIT_COMPLETE_out; + assign AXI_18_DFI_PHYUPD_REQ = AXI_18_DFI_PHYUPD_REQ_out; + assign AXI_18_DFI_PHY_LP_STATE = AXI_18_DFI_PHY_LP_STATE_out; + assign AXI_18_DFI_RST_N_BUF = AXI_18_DFI_RST_N_BUF_out; + assign AXI_18_MC_STATUS = AXI_18_MC_STATUS_out; + assign AXI_18_PHY_STATUS = AXI_18_PHY_STATUS_out; + assign AXI_18_RDATA = AXI_18_RDATA_out; + assign AXI_18_RDATA_PARITY = AXI_18_RDATA_PARITY_out; + assign AXI_18_RID = AXI_18_RID_out; + assign AXI_18_RLAST = AXI_18_RLAST_out; + assign AXI_18_RRESP = AXI_18_RRESP_out; + assign AXI_18_RVALID = AXI_18_RVALID_out; + assign AXI_18_WREADY = AXI_18_WREADY_out; + assign AXI_19_ARREADY = AXI_19_ARREADY_out; + assign AXI_19_AWREADY = AXI_19_AWREADY_out; + assign AXI_19_BID = AXI_19_BID_out; + assign AXI_19_BRESP = AXI_19_BRESP_out; + assign AXI_19_BVALID = AXI_19_BVALID_out; + assign AXI_19_DFI_AW_AERR_N = AXI_19_DFI_AW_AERR_N_out; + assign AXI_19_DFI_CLK_BUF = AXI_19_DFI_CLK_BUF_out; + assign AXI_19_DFI_DBI_BYTE_DISABLE = AXI_19_DFI_DBI_BYTE_DISABLE_out; + assign AXI_19_DFI_DW_RDDATA_DBI = AXI_19_DFI_DW_RDDATA_DBI_out; + assign AXI_19_DFI_DW_RDDATA_DERR = AXI_19_DFI_DW_RDDATA_DERR_out; + assign AXI_19_DFI_DW_RDDATA_VALID = AXI_19_DFI_DW_RDDATA_VALID_out; + assign AXI_19_DFI_INIT_COMPLETE = AXI_19_DFI_INIT_COMPLETE_out; + assign AXI_19_DFI_PHYUPD_REQ = AXI_19_DFI_PHYUPD_REQ_out; + assign AXI_19_DFI_PHY_LP_STATE = AXI_19_DFI_PHY_LP_STATE_out; + assign AXI_19_DFI_RST_N_BUF = AXI_19_DFI_RST_N_BUF_out; + assign AXI_19_RDATA = AXI_19_RDATA_out; + assign AXI_19_RDATA_PARITY = AXI_19_RDATA_PARITY_out; + assign AXI_19_RID = AXI_19_RID_out; + assign AXI_19_RLAST = AXI_19_RLAST_out; + assign AXI_19_RRESP = AXI_19_RRESP_out; + assign AXI_19_RVALID = AXI_19_RVALID_out; + assign AXI_19_WREADY = AXI_19_WREADY_out; + assign AXI_20_ARREADY = AXI_20_ARREADY_out; + assign AXI_20_AWREADY = AXI_20_AWREADY_out; + assign AXI_20_BID = AXI_20_BID_out; + assign AXI_20_BRESP = AXI_20_BRESP_out; + assign AXI_20_BVALID = AXI_20_BVALID_out; + assign AXI_20_DFI_AW_AERR_N = AXI_20_DFI_AW_AERR_N_out; + assign AXI_20_DFI_CLK_BUF = AXI_20_DFI_CLK_BUF_out; + assign AXI_20_DFI_DBI_BYTE_DISABLE = AXI_20_DFI_DBI_BYTE_DISABLE_out; + assign AXI_20_DFI_DW_RDDATA_DBI = AXI_20_DFI_DW_RDDATA_DBI_out; + assign AXI_20_DFI_DW_RDDATA_DERR = AXI_20_DFI_DW_RDDATA_DERR_out; + assign AXI_20_DFI_DW_RDDATA_VALID = AXI_20_DFI_DW_RDDATA_VALID_out; + assign AXI_20_DFI_INIT_COMPLETE = AXI_20_DFI_INIT_COMPLETE_out; + assign AXI_20_DFI_PHYUPD_REQ = AXI_20_DFI_PHYUPD_REQ_out; + assign AXI_20_DFI_PHY_LP_STATE = AXI_20_DFI_PHY_LP_STATE_out; + assign AXI_20_DFI_RST_N_BUF = AXI_20_DFI_RST_N_BUF_out; + assign AXI_20_MC_STATUS = AXI_20_MC_STATUS_out; + assign AXI_20_PHY_STATUS = AXI_20_PHY_STATUS_out; + assign AXI_20_RDATA = AXI_20_RDATA_out; + assign AXI_20_RDATA_PARITY = AXI_20_RDATA_PARITY_out; + assign AXI_20_RID = AXI_20_RID_out; + assign AXI_20_RLAST = AXI_20_RLAST_out; + assign AXI_20_RRESP = AXI_20_RRESP_out; + assign AXI_20_RVALID = AXI_20_RVALID_out; + assign AXI_20_WREADY = AXI_20_WREADY_out; + assign AXI_21_ARREADY = AXI_21_ARREADY_out; + assign AXI_21_AWREADY = AXI_21_AWREADY_out; + assign AXI_21_BID = AXI_21_BID_out; + assign AXI_21_BRESP = AXI_21_BRESP_out; + assign AXI_21_BVALID = AXI_21_BVALID_out; + assign AXI_21_DFI_AW_AERR_N = AXI_21_DFI_AW_AERR_N_out; + assign AXI_21_DFI_CLK_BUF = AXI_21_DFI_CLK_BUF_out; + assign AXI_21_DFI_DBI_BYTE_DISABLE = AXI_21_DFI_DBI_BYTE_DISABLE_out; + assign AXI_21_DFI_DW_RDDATA_DBI = AXI_21_DFI_DW_RDDATA_DBI_out; + assign AXI_21_DFI_DW_RDDATA_DERR = AXI_21_DFI_DW_RDDATA_DERR_out; + assign AXI_21_DFI_DW_RDDATA_VALID = AXI_21_DFI_DW_RDDATA_VALID_out; + assign AXI_21_DFI_INIT_COMPLETE = AXI_21_DFI_INIT_COMPLETE_out; + assign AXI_21_DFI_PHYUPD_REQ = AXI_21_DFI_PHYUPD_REQ_out; + assign AXI_21_DFI_PHY_LP_STATE = AXI_21_DFI_PHY_LP_STATE_out; + assign AXI_21_DFI_RST_N_BUF = AXI_21_DFI_RST_N_BUF_out; + assign AXI_21_RDATA = AXI_21_RDATA_out; + assign AXI_21_RDATA_PARITY = AXI_21_RDATA_PARITY_out; + assign AXI_21_RID = AXI_21_RID_out; + assign AXI_21_RLAST = AXI_21_RLAST_out; + assign AXI_21_RRESP = AXI_21_RRESP_out; + assign AXI_21_RVALID = AXI_21_RVALID_out; + assign AXI_21_WREADY = AXI_21_WREADY_out; + assign AXI_22_ARREADY = AXI_22_ARREADY_out; + assign AXI_22_AWREADY = AXI_22_AWREADY_out; + assign AXI_22_BID = AXI_22_BID_out; + assign AXI_22_BRESP = AXI_22_BRESP_out; + assign AXI_22_BVALID = AXI_22_BVALID_out; + assign AXI_22_DFI_AW_AERR_N = AXI_22_DFI_AW_AERR_N_out; + assign AXI_22_DFI_CLK_BUF = AXI_22_DFI_CLK_BUF_out; + assign AXI_22_DFI_DBI_BYTE_DISABLE = AXI_22_DFI_DBI_BYTE_DISABLE_out; + assign AXI_22_DFI_DW_RDDATA_DBI = AXI_22_DFI_DW_RDDATA_DBI_out; + assign AXI_22_DFI_DW_RDDATA_DERR = AXI_22_DFI_DW_RDDATA_DERR_out; + assign AXI_22_DFI_DW_RDDATA_VALID = AXI_22_DFI_DW_RDDATA_VALID_out; + assign AXI_22_DFI_INIT_COMPLETE = AXI_22_DFI_INIT_COMPLETE_out; + assign AXI_22_DFI_PHYUPD_REQ = AXI_22_DFI_PHYUPD_REQ_out; + assign AXI_22_DFI_PHY_LP_STATE = AXI_22_DFI_PHY_LP_STATE_out; + assign AXI_22_DFI_RST_N_BUF = AXI_22_DFI_RST_N_BUF_out; + assign AXI_22_MC_STATUS = AXI_22_MC_STATUS_out; + assign AXI_22_PHY_STATUS = AXI_22_PHY_STATUS_out; + assign AXI_22_RDATA = AXI_22_RDATA_out; + assign AXI_22_RDATA_PARITY = AXI_22_RDATA_PARITY_out; + assign AXI_22_RID = AXI_22_RID_out; + assign AXI_22_RLAST = AXI_22_RLAST_out; + assign AXI_22_RRESP = AXI_22_RRESP_out; + assign AXI_22_RVALID = AXI_22_RVALID_out; + assign AXI_22_WREADY = AXI_22_WREADY_out; + assign AXI_23_ARREADY = AXI_23_ARREADY_out; + assign AXI_23_AWREADY = AXI_23_AWREADY_out; + assign AXI_23_BID = AXI_23_BID_out; + assign AXI_23_BRESP = AXI_23_BRESP_out; + assign AXI_23_BVALID = AXI_23_BVALID_out; + assign AXI_23_DFI_AW_AERR_N = AXI_23_DFI_AW_AERR_N_out; + assign AXI_23_DFI_CLK_BUF = AXI_23_DFI_CLK_BUF_out; + assign AXI_23_DFI_DBI_BYTE_DISABLE = AXI_23_DFI_DBI_BYTE_DISABLE_out; + assign AXI_23_DFI_DW_RDDATA_DBI = AXI_23_DFI_DW_RDDATA_DBI_out; + assign AXI_23_DFI_DW_RDDATA_DERR = AXI_23_DFI_DW_RDDATA_DERR_out; + assign AXI_23_DFI_DW_RDDATA_VALID = AXI_23_DFI_DW_RDDATA_VALID_out; + assign AXI_23_DFI_INIT_COMPLETE = AXI_23_DFI_INIT_COMPLETE_out; + assign AXI_23_DFI_PHYUPD_REQ = AXI_23_DFI_PHYUPD_REQ_out; + assign AXI_23_DFI_PHY_LP_STATE = AXI_23_DFI_PHY_LP_STATE_out; + assign AXI_23_DFI_RST_N_BUF = AXI_23_DFI_RST_N_BUF_out; + assign AXI_23_RDATA = AXI_23_RDATA_out; + assign AXI_23_RDATA_PARITY = AXI_23_RDATA_PARITY_out; + assign AXI_23_RID = AXI_23_RID_out; + assign AXI_23_RLAST = AXI_23_RLAST_out; + assign AXI_23_RRESP = AXI_23_RRESP_out; + assign AXI_23_RVALID = AXI_23_RVALID_out; + assign AXI_23_WREADY = AXI_23_WREADY_out; + assign AXI_24_ARREADY = AXI_24_ARREADY_out; + assign AXI_24_AWREADY = AXI_24_AWREADY_out; + assign AXI_24_BID = AXI_24_BID_out; + assign AXI_24_BRESP = AXI_24_BRESP_out; + assign AXI_24_BVALID = AXI_24_BVALID_out; + assign AXI_24_DFI_AW_AERR_N = AXI_24_DFI_AW_AERR_N_out; + assign AXI_24_DFI_CLK_BUF = AXI_24_DFI_CLK_BUF_out; + assign AXI_24_DFI_DBI_BYTE_DISABLE = AXI_24_DFI_DBI_BYTE_DISABLE_out; + assign AXI_24_DFI_DW_RDDATA_DBI = AXI_24_DFI_DW_RDDATA_DBI_out; + assign AXI_24_DFI_DW_RDDATA_DERR = AXI_24_DFI_DW_RDDATA_DERR_out; + assign AXI_24_DFI_DW_RDDATA_VALID = AXI_24_DFI_DW_RDDATA_VALID_out; + assign AXI_24_DFI_INIT_COMPLETE = AXI_24_DFI_INIT_COMPLETE_out; + assign AXI_24_DFI_PHYUPD_REQ = AXI_24_DFI_PHYUPD_REQ_out; + assign AXI_24_DFI_PHY_LP_STATE = AXI_24_DFI_PHY_LP_STATE_out; + assign AXI_24_DFI_RST_N_BUF = AXI_24_DFI_RST_N_BUF_out; + assign AXI_24_MC_STATUS = AXI_24_MC_STATUS_out; + assign AXI_24_PHY_STATUS = AXI_24_PHY_STATUS_out; + assign AXI_24_RDATA = AXI_24_RDATA_out; + assign AXI_24_RDATA_PARITY = AXI_24_RDATA_PARITY_out; + assign AXI_24_RID = AXI_24_RID_out; + assign AXI_24_RLAST = AXI_24_RLAST_out; + assign AXI_24_RRESP = AXI_24_RRESP_out; + assign AXI_24_RVALID = AXI_24_RVALID_out; + assign AXI_24_WREADY = AXI_24_WREADY_out; + assign AXI_25_ARREADY = AXI_25_ARREADY_out; + assign AXI_25_AWREADY = AXI_25_AWREADY_out; + assign AXI_25_BID = AXI_25_BID_out; + assign AXI_25_BRESP = AXI_25_BRESP_out; + assign AXI_25_BVALID = AXI_25_BVALID_out; + assign AXI_25_DFI_AW_AERR_N = AXI_25_DFI_AW_AERR_N_out; + assign AXI_25_DFI_CLK_BUF = AXI_25_DFI_CLK_BUF_out; + assign AXI_25_DFI_DBI_BYTE_DISABLE = AXI_25_DFI_DBI_BYTE_DISABLE_out; + assign AXI_25_DFI_DW_RDDATA_DBI = AXI_25_DFI_DW_RDDATA_DBI_out; + assign AXI_25_DFI_DW_RDDATA_DERR = AXI_25_DFI_DW_RDDATA_DERR_out; + assign AXI_25_DFI_DW_RDDATA_VALID = AXI_25_DFI_DW_RDDATA_VALID_out; + assign AXI_25_DFI_INIT_COMPLETE = AXI_25_DFI_INIT_COMPLETE_out; + assign AXI_25_DFI_PHYUPD_REQ = AXI_25_DFI_PHYUPD_REQ_out; + assign AXI_25_DFI_PHY_LP_STATE = AXI_25_DFI_PHY_LP_STATE_out; + assign AXI_25_DFI_RST_N_BUF = AXI_25_DFI_RST_N_BUF_out; + assign AXI_25_RDATA = AXI_25_RDATA_out; + assign AXI_25_RDATA_PARITY = AXI_25_RDATA_PARITY_out; + assign AXI_25_RID = AXI_25_RID_out; + assign AXI_25_RLAST = AXI_25_RLAST_out; + assign AXI_25_RRESP = AXI_25_RRESP_out; + assign AXI_25_RVALID = AXI_25_RVALID_out; + assign AXI_25_WREADY = AXI_25_WREADY_out; + assign AXI_26_ARREADY = AXI_26_ARREADY_out; + assign AXI_26_AWREADY = AXI_26_AWREADY_out; + assign AXI_26_BID = AXI_26_BID_out; + assign AXI_26_BRESP = AXI_26_BRESP_out; + assign AXI_26_BVALID = AXI_26_BVALID_out; + assign AXI_26_DFI_AW_AERR_N = AXI_26_DFI_AW_AERR_N_out; + assign AXI_26_DFI_CLK_BUF = AXI_26_DFI_CLK_BUF_out; + assign AXI_26_DFI_DBI_BYTE_DISABLE = AXI_26_DFI_DBI_BYTE_DISABLE_out; + assign AXI_26_DFI_DW_RDDATA_DBI = AXI_26_DFI_DW_RDDATA_DBI_out; + assign AXI_26_DFI_DW_RDDATA_DERR = AXI_26_DFI_DW_RDDATA_DERR_out; + assign AXI_26_DFI_DW_RDDATA_VALID = AXI_26_DFI_DW_RDDATA_VALID_out; + assign AXI_26_DFI_INIT_COMPLETE = AXI_26_DFI_INIT_COMPLETE_out; + assign AXI_26_DFI_PHYUPD_REQ = AXI_26_DFI_PHYUPD_REQ_out; + assign AXI_26_DFI_PHY_LP_STATE = AXI_26_DFI_PHY_LP_STATE_out; + assign AXI_26_DFI_RST_N_BUF = AXI_26_DFI_RST_N_BUF_out; + assign AXI_26_MC_STATUS = AXI_26_MC_STATUS_out; + assign AXI_26_PHY_STATUS = AXI_26_PHY_STATUS_out; + assign AXI_26_RDATA = AXI_26_RDATA_out; + assign AXI_26_RDATA_PARITY = AXI_26_RDATA_PARITY_out; + assign AXI_26_RID = AXI_26_RID_out; + assign AXI_26_RLAST = AXI_26_RLAST_out; + assign AXI_26_RRESP = AXI_26_RRESP_out; + assign AXI_26_RVALID = AXI_26_RVALID_out; + assign AXI_26_WREADY = AXI_26_WREADY_out; + assign AXI_27_ARREADY = AXI_27_ARREADY_out; + assign AXI_27_AWREADY = AXI_27_AWREADY_out; + assign AXI_27_BID = AXI_27_BID_out; + assign AXI_27_BRESP = AXI_27_BRESP_out; + assign AXI_27_BVALID = AXI_27_BVALID_out; + assign AXI_27_DFI_AW_AERR_N = AXI_27_DFI_AW_AERR_N_out; + assign AXI_27_DFI_CLK_BUF = AXI_27_DFI_CLK_BUF_out; + assign AXI_27_DFI_DBI_BYTE_DISABLE = AXI_27_DFI_DBI_BYTE_DISABLE_out; + assign AXI_27_DFI_DW_RDDATA_DBI = AXI_27_DFI_DW_RDDATA_DBI_out; + assign AXI_27_DFI_DW_RDDATA_DERR = AXI_27_DFI_DW_RDDATA_DERR_out; + assign AXI_27_DFI_DW_RDDATA_VALID = AXI_27_DFI_DW_RDDATA_VALID_out; + assign AXI_27_DFI_INIT_COMPLETE = AXI_27_DFI_INIT_COMPLETE_out; + assign AXI_27_DFI_PHYUPD_REQ = AXI_27_DFI_PHYUPD_REQ_out; + assign AXI_27_DFI_PHY_LP_STATE = AXI_27_DFI_PHY_LP_STATE_out; + assign AXI_27_DFI_RST_N_BUF = AXI_27_DFI_RST_N_BUF_out; + assign AXI_27_RDATA = AXI_27_RDATA_out; + assign AXI_27_RDATA_PARITY = AXI_27_RDATA_PARITY_out; + assign AXI_27_RID = AXI_27_RID_out; + assign AXI_27_RLAST = AXI_27_RLAST_out; + assign AXI_27_RRESP = AXI_27_RRESP_out; + assign AXI_27_RVALID = AXI_27_RVALID_out; + assign AXI_27_WREADY = AXI_27_WREADY_out; + assign AXI_28_ARREADY = AXI_28_ARREADY_out; + assign AXI_28_AWREADY = AXI_28_AWREADY_out; + assign AXI_28_BID = AXI_28_BID_out; + assign AXI_28_BRESP = AXI_28_BRESP_out; + assign AXI_28_BVALID = AXI_28_BVALID_out; + assign AXI_28_DFI_AW_AERR_N = AXI_28_DFI_AW_AERR_N_out; + assign AXI_28_DFI_CLK_BUF = AXI_28_DFI_CLK_BUF_out; + assign AXI_28_DFI_DBI_BYTE_DISABLE = AXI_28_DFI_DBI_BYTE_DISABLE_out; + assign AXI_28_DFI_DW_RDDATA_DBI = AXI_28_DFI_DW_RDDATA_DBI_out; + assign AXI_28_DFI_DW_RDDATA_DERR = AXI_28_DFI_DW_RDDATA_DERR_out; + assign AXI_28_DFI_DW_RDDATA_VALID = AXI_28_DFI_DW_RDDATA_VALID_out; + assign AXI_28_DFI_INIT_COMPLETE = AXI_28_DFI_INIT_COMPLETE_out; + assign AXI_28_DFI_PHYUPD_REQ = AXI_28_DFI_PHYUPD_REQ_out; + assign AXI_28_DFI_PHY_LP_STATE = AXI_28_DFI_PHY_LP_STATE_out; + assign AXI_28_DFI_RST_N_BUF = AXI_28_DFI_RST_N_BUF_out; + assign AXI_28_MC_STATUS = AXI_28_MC_STATUS_out; + assign AXI_28_PHY_STATUS = AXI_28_PHY_STATUS_out; + assign AXI_28_RDATA = AXI_28_RDATA_out; + assign AXI_28_RDATA_PARITY = AXI_28_RDATA_PARITY_out; + assign AXI_28_RID = AXI_28_RID_out; + assign AXI_28_RLAST = AXI_28_RLAST_out; + assign AXI_28_RRESP = AXI_28_RRESP_out; + assign AXI_28_RVALID = AXI_28_RVALID_out; + assign AXI_28_WREADY = AXI_28_WREADY_out; + assign AXI_29_ARREADY = AXI_29_ARREADY_out; + assign AXI_29_AWREADY = AXI_29_AWREADY_out; + assign AXI_29_BID = AXI_29_BID_out; + assign AXI_29_BRESP = AXI_29_BRESP_out; + assign AXI_29_BVALID = AXI_29_BVALID_out; + assign AXI_29_DFI_AW_AERR_N = AXI_29_DFI_AW_AERR_N_out; + assign AXI_29_DFI_CLK_BUF = AXI_29_DFI_CLK_BUF_out; + assign AXI_29_DFI_DBI_BYTE_DISABLE = AXI_29_DFI_DBI_BYTE_DISABLE_out; + assign AXI_29_DFI_DW_RDDATA_DBI = AXI_29_DFI_DW_RDDATA_DBI_out; + assign AXI_29_DFI_DW_RDDATA_DERR = AXI_29_DFI_DW_RDDATA_DERR_out; + assign AXI_29_DFI_DW_RDDATA_VALID = AXI_29_DFI_DW_RDDATA_VALID_out; + assign AXI_29_DFI_INIT_COMPLETE = AXI_29_DFI_INIT_COMPLETE_out; + assign AXI_29_DFI_PHYUPD_REQ = AXI_29_DFI_PHYUPD_REQ_out; + assign AXI_29_DFI_PHY_LP_STATE = AXI_29_DFI_PHY_LP_STATE_out; + assign AXI_29_DFI_RST_N_BUF = AXI_29_DFI_RST_N_BUF_out; + assign AXI_29_RDATA = AXI_29_RDATA_out; + assign AXI_29_RDATA_PARITY = AXI_29_RDATA_PARITY_out; + assign AXI_29_RID = AXI_29_RID_out; + assign AXI_29_RLAST = AXI_29_RLAST_out; + assign AXI_29_RRESP = AXI_29_RRESP_out; + assign AXI_29_RVALID = AXI_29_RVALID_out; + assign AXI_29_WREADY = AXI_29_WREADY_out; + assign AXI_30_ARREADY = AXI_30_ARREADY_out; + assign AXI_30_AWREADY = AXI_30_AWREADY_out; + assign AXI_30_BID = AXI_30_BID_out; + assign AXI_30_BRESP = AXI_30_BRESP_out; + assign AXI_30_BVALID = AXI_30_BVALID_out; + assign AXI_30_DFI_AW_AERR_N = AXI_30_DFI_AW_AERR_N_out; + assign AXI_30_DFI_CLK_BUF = AXI_30_DFI_CLK_BUF_out; + assign AXI_30_DFI_DBI_BYTE_DISABLE = AXI_30_DFI_DBI_BYTE_DISABLE_out; + assign AXI_30_DFI_DW_RDDATA_DBI = AXI_30_DFI_DW_RDDATA_DBI_out; + assign AXI_30_DFI_DW_RDDATA_DERR = AXI_30_DFI_DW_RDDATA_DERR_out; + assign AXI_30_DFI_DW_RDDATA_VALID = AXI_30_DFI_DW_RDDATA_VALID_out; + assign AXI_30_DFI_INIT_COMPLETE = AXI_30_DFI_INIT_COMPLETE_out; + assign AXI_30_DFI_PHYUPD_REQ = AXI_30_DFI_PHYUPD_REQ_out; + assign AXI_30_DFI_PHY_LP_STATE = AXI_30_DFI_PHY_LP_STATE_out; + assign AXI_30_DFI_RST_N_BUF = AXI_30_DFI_RST_N_BUF_out; + assign AXI_30_MC_STATUS = AXI_30_MC_STATUS_out; + assign AXI_30_PHY_STATUS = AXI_30_PHY_STATUS_out; + assign AXI_30_RDATA = AXI_30_RDATA_out; + assign AXI_30_RDATA_PARITY = AXI_30_RDATA_PARITY_out; + assign AXI_30_RID = AXI_30_RID_out; + assign AXI_30_RLAST = AXI_30_RLAST_out; + assign AXI_30_RRESP = AXI_30_RRESP_out; + assign AXI_30_RVALID = AXI_30_RVALID_out; + assign AXI_30_WREADY = AXI_30_WREADY_out; + assign AXI_31_ARREADY = AXI_31_ARREADY_out; + assign AXI_31_AWREADY = AXI_31_AWREADY_out; + assign AXI_31_BID = AXI_31_BID_out; + assign AXI_31_BRESP = AXI_31_BRESP_out; + assign AXI_31_BVALID = AXI_31_BVALID_out; + assign AXI_31_DFI_AW_AERR_N = AXI_31_DFI_AW_AERR_N_out; + assign AXI_31_DFI_CLK_BUF = AXI_31_DFI_CLK_BUF_out; + assign AXI_31_DFI_DBI_BYTE_DISABLE = AXI_31_DFI_DBI_BYTE_DISABLE_out; + assign AXI_31_DFI_DW_RDDATA_DBI = AXI_31_DFI_DW_RDDATA_DBI_out; + assign AXI_31_DFI_DW_RDDATA_DERR = AXI_31_DFI_DW_RDDATA_DERR_out; + assign AXI_31_DFI_DW_RDDATA_VALID = AXI_31_DFI_DW_RDDATA_VALID_out; + assign AXI_31_DFI_INIT_COMPLETE = AXI_31_DFI_INIT_COMPLETE_out; + assign AXI_31_DFI_PHYUPD_REQ = AXI_31_DFI_PHYUPD_REQ_out; + assign AXI_31_DFI_PHY_LP_STATE = AXI_31_DFI_PHY_LP_STATE_out; + assign AXI_31_DFI_RST_N_BUF = AXI_31_DFI_RST_N_BUF_out; + assign AXI_31_RDATA = AXI_31_RDATA_out; + assign AXI_31_RDATA_PARITY = AXI_31_RDATA_PARITY_out; + assign AXI_31_RID = AXI_31_RID_out; + assign AXI_31_RLAST = AXI_31_RLAST_out; + assign AXI_31_RRESP = AXI_31_RRESP_out; + assign AXI_31_RVALID = AXI_31_RVALID_out; + assign AXI_31_WREADY = AXI_31_WREADY_out; + assign DRAM_0_STAT_CATTRIP = DRAM_0_STAT_CATTRIP_out; + assign DRAM_0_STAT_TEMP = DRAM_0_STAT_TEMP_out; + assign DRAM_1_STAT_CATTRIP = DRAM_1_STAT_CATTRIP_out; + assign DRAM_1_STAT_TEMP = DRAM_1_STAT_TEMP_out; + + assign APB_0_PADDR_in = APB_0_PADDR; + assign APB_0_PCLK_in = APB_0_PCLK; + assign APB_0_PENABLE_in = APB_0_PENABLE; + assign APB_0_PRESET_N_in = APB_0_PRESET_N; + assign APB_0_PSEL_in = APB_0_PSEL; + assign APB_0_PWDATA_in = APB_0_PWDATA; + assign APB_0_PWRITE_in = APB_0_PWRITE; + assign APB_1_PADDR_in = APB_1_PADDR; + assign APB_1_PCLK_in = APB_1_PCLK; + assign APB_1_PENABLE_in = APB_1_PENABLE; + assign APB_1_PRESET_N_in = APB_1_PRESET_N; + assign APB_1_PSEL_in = APB_1_PSEL; + assign APB_1_PWDATA_in = APB_1_PWDATA; + assign APB_1_PWRITE_in = APB_1_PWRITE; + assign AXI_00_ACLK_in = AXI_00_ACLK; + assign AXI_00_ARADDR_in = AXI_00_ARADDR; + assign AXI_00_ARBURST_in = AXI_00_ARBURST; + assign AXI_00_ARESET_N_in = AXI_00_ARESET_N; + assign AXI_00_ARID_in = AXI_00_ARID; + assign AXI_00_ARLEN_in = AXI_00_ARLEN; + assign AXI_00_ARSIZE_in = AXI_00_ARSIZE; + assign AXI_00_ARVALID_in = AXI_00_ARVALID; + assign AXI_00_AWADDR_in = AXI_00_AWADDR; + assign AXI_00_AWBURST_in = AXI_00_AWBURST; + assign AXI_00_AWID_in = AXI_00_AWID; + assign AXI_00_AWLEN_in = AXI_00_AWLEN; + assign AXI_00_AWSIZE_in = AXI_00_AWSIZE; + assign AXI_00_AWVALID_in = AXI_00_AWVALID; + assign AXI_00_BREADY_in = AXI_00_BREADY; + assign AXI_00_DFI_LP_PWR_X_REQ_in = AXI_00_DFI_LP_PWR_X_REQ; + assign AXI_00_RREADY_in = AXI_00_RREADY; + assign AXI_00_WDATA_PARITY_in = AXI_00_WDATA_PARITY; + assign AXI_00_WDATA_in = AXI_00_WDATA; + assign AXI_00_WLAST_in = AXI_00_WLAST; + assign AXI_00_WSTRB_in = AXI_00_WSTRB; + assign AXI_00_WVALID_in = AXI_00_WVALID; + assign AXI_01_ACLK_in = AXI_01_ACLK; + assign AXI_01_ARADDR_in = AXI_01_ARADDR; + assign AXI_01_ARBURST_in = AXI_01_ARBURST; + assign AXI_01_ARESET_N_in = AXI_01_ARESET_N; + assign AXI_01_ARID_in = AXI_01_ARID; + assign AXI_01_ARLEN_in = AXI_01_ARLEN; + assign AXI_01_ARSIZE_in = AXI_01_ARSIZE; + assign AXI_01_ARVALID_in = AXI_01_ARVALID; + assign AXI_01_AWADDR_in = AXI_01_AWADDR; + assign AXI_01_AWBURST_in = AXI_01_AWBURST; + assign AXI_01_AWID_in = AXI_01_AWID; + assign AXI_01_AWLEN_in = AXI_01_AWLEN; + assign AXI_01_AWSIZE_in = AXI_01_AWSIZE; + assign AXI_01_AWVALID_in = AXI_01_AWVALID; + assign AXI_01_BREADY_in = AXI_01_BREADY; + assign AXI_01_DFI_LP_PWR_X_REQ_in = AXI_01_DFI_LP_PWR_X_REQ; + assign AXI_01_RREADY_in = AXI_01_RREADY; + assign AXI_01_WDATA_PARITY_in = AXI_01_WDATA_PARITY; + assign AXI_01_WDATA_in = AXI_01_WDATA; + assign AXI_01_WLAST_in = AXI_01_WLAST; + assign AXI_01_WSTRB_in = AXI_01_WSTRB; + assign AXI_01_WVALID_in = AXI_01_WVALID; + assign AXI_02_ACLK_in = AXI_02_ACLK; + assign AXI_02_ARADDR_in = AXI_02_ARADDR; + assign AXI_02_ARBURST_in = AXI_02_ARBURST; + assign AXI_02_ARESET_N_in = AXI_02_ARESET_N; + assign AXI_02_ARID_in = AXI_02_ARID; + assign AXI_02_ARLEN_in = AXI_02_ARLEN; + assign AXI_02_ARSIZE_in = AXI_02_ARSIZE; + assign AXI_02_ARVALID_in = AXI_02_ARVALID; + assign AXI_02_AWADDR_in = AXI_02_AWADDR; + assign AXI_02_AWBURST_in = AXI_02_AWBURST; + assign AXI_02_AWID_in = AXI_02_AWID; + assign AXI_02_AWLEN_in = AXI_02_AWLEN; + assign AXI_02_AWSIZE_in = AXI_02_AWSIZE; + assign AXI_02_AWVALID_in = AXI_02_AWVALID; + assign AXI_02_BREADY_in = AXI_02_BREADY; + assign AXI_02_DFI_LP_PWR_X_REQ_in = AXI_02_DFI_LP_PWR_X_REQ; + assign AXI_02_RREADY_in = AXI_02_RREADY; + assign AXI_02_WDATA_PARITY_in = AXI_02_WDATA_PARITY; + assign AXI_02_WDATA_in = AXI_02_WDATA; + assign AXI_02_WLAST_in = AXI_02_WLAST; + assign AXI_02_WSTRB_in = AXI_02_WSTRB; + assign AXI_02_WVALID_in = AXI_02_WVALID; + assign AXI_03_ACLK_in = AXI_03_ACLK; + assign AXI_03_ARADDR_in = AXI_03_ARADDR; + assign AXI_03_ARBURST_in = AXI_03_ARBURST; + assign AXI_03_ARESET_N_in = AXI_03_ARESET_N; + assign AXI_03_ARID_in = AXI_03_ARID; + assign AXI_03_ARLEN_in = AXI_03_ARLEN; + assign AXI_03_ARSIZE_in = AXI_03_ARSIZE; + assign AXI_03_ARVALID_in = AXI_03_ARVALID; + assign AXI_03_AWADDR_in = AXI_03_AWADDR; + assign AXI_03_AWBURST_in = AXI_03_AWBURST; + assign AXI_03_AWID_in = AXI_03_AWID; + assign AXI_03_AWLEN_in = AXI_03_AWLEN; + assign AXI_03_AWSIZE_in = AXI_03_AWSIZE; + assign AXI_03_AWVALID_in = AXI_03_AWVALID; + assign AXI_03_BREADY_in = AXI_03_BREADY; + assign AXI_03_DFI_LP_PWR_X_REQ_in = AXI_03_DFI_LP_PWR_X_REQ; + assign AXI_03_RREADY_in = AXI_03_RREADY; + assign AXI_03_WDATA_PARITY_in = AXI_03_WDATA_PARITY; + assign AXI_03_WDATA_in = AXI_03_WDATA; + assign AXI_03_WLAST_in = AXI_03_WLAST; + assign AXI_03_WSTRB_in = AXI_03_WSTRB; + assign AXI_03_WVALID_in = AXI_03_WVALID; + assign AXI_04_ACLK_in = AXI_04_ACLK; + assign AXI_04_ARADDR_in = AXI_04_ARADDR; + assign AXI_04_ARBURST_in = AXI_04_ARBURST; + assign AXI_04_ARESET_N_in = AXI_04_ARESET_N; + assign AXI_04_ARID_in = AXI_04_ARID; + assign AXI_04_ARLEN_in = AXI_04_ARLEN; + assign AXI_04_ARSIZE_in = AXI_04_ARSIZE; + assign AXI_04_ARVALID_in = AXI_04_ARVALID; + assign AXI_04_AWADDR_in = AXI_04_AWADDR; + assign AXI_04_AWBURST_in = AXI_04_AWBURST; + assign AXI_04_AWID_in = AXI_04_AWID; + assign AXI_04_AWLEN_in = AXI_04_AWLEN; + assign AXI_04_AWSIZE_in = AXI_04_AWSIZE; + assign AXI_04_AWVALID_in = AXI_04_AWVALID; + assign AXI_04_BREADY_in = AXI_04_BREADY; + assign AXI_04_DFI_LP_PWR_X_REQ_in = AXI_04_DFI_LP_PWR_X_REQ; + assign AXI_04_RREADY_in = AXI_04_RREADY; + assign AXI_04_WDATA_PARITY_in = AXI_04_WDATA_PARITY; + assign AXI_04_WDATA_in = AXI_04_WDATA; + assign AXI_04_WLAST_in = AXI_04_WLAST; + assign AXI_04_WSTRB_in = AXI_04_WSTRB; + assign AXI_04_WVALID_in = AXI_04_WVALID; + assign AXI_05_ACLK_in = AXI_05_ACLK; + assign AXI_05_ARADDR_in = AXI_05_ARADDR; + assign AXI_05_ARBURST_in = AXI_05_ARBURST; + assign AXI_05_ARESET_N_in = AXI_05_ARESET_N; + assign AXI_05_ARID_in = AXI_05_ARID; + assign AXI_05_ARLEN_in = AXI_05_ARLEN; + assign AXI_05_ARSIZE_in = AXI_05_ARSIZE; + assign AXI_05_ARVALID_in = AXI_05_ARVALID; + assign AXI_05_AWADDR_in = AXI_05_AWADDR; + assign AXI_05_AWBURST_in = AXI_05_AWBURST; + assign AXI_05_AWID_in = AXI_05_AWID; + assign AXI_05_AWLEN_in = AXI_05_AWLEN; + assign AXI_05_AWSIZE_in = AXI_05_AWSIZE; + assign AXI_05_AWVALID_in = AXI_05_AWVALID; + assign AXI_05_BREADY_in = AXI_05_BREADY; + assign AXI_05_DFI_LP_PWR_X_REQ_in = AXI_05_DFI_LP_PWR_X_REQ; + assign AXI_05_RREADY_in = AXI_05_RREADY; + assign AXI_05_WDATA_PARITY_in = AXI_05_WDATA_PARITY; + assign AXI_05_WDATA_in = AXI_05_WDATA; + assign AXI_05_WLAST_in = AXI_05_WLAST; + assign AXI_05_WSTRB_in = AXI_05_WSTRB; + assign AXI_05_WVALID_in = AXI_05_WVALID; + assign AXI_06_ACLK_in = AXI_06_ACLK; + assign AXI_06_ARADDR_in = AXI_06_ARADDR; + assign AXI_06_ARBURST_in = AXI_06_ARBURST; + assign AXI_06_ARESET_N_in = AXI_06_ARESET_N; + assign AXI_06_ARID_in = AXI_06_ARID; + assign AXI_06_ARLEN_in = AXI_06_ARLEN; + assign AXI_06_ARSIZE_in = AXI_06_ARSIZE; + assign AXI_06_ARVALID_in = AXI_06_ARVALID; + assign AXI_06_AWADDR_in = AXI_06_AWADDR; + assign AXI_06_AWBURST_in = AXI_06_AWBURST; + assign AXI_06_AWID_in = AXI_06_AWID; + assign AXI_06_AWLEN_in = AXI_06_AWLEN; + assign AXI_06_AWSIZE_in = AXI_06_AWSIZE; + assign AXI_06_AWVALID_in = AXI_06_AWVALID; + assign AXI_06_BREADY_in = AXI_06_BREADY; + assign AXI_06_DFI_LP_PWR_X_REQ_in = AXI_06_DFI_LP_PWR_X_REQ; + assign AXI_06_RREADY_in = AXI_06_RREADY; + assign AXI_06_WDATA_PARITY_in = AXI_06_WDATA_PARITY; + assign AXI_06_WDATA_in = AXI_06_WDATA; + assign AXI_06_WLAST_in = AXI_06_WLAST; + assign AXI_06_WSTRB_in = AXI_06_WSTRB; + assign AXI_06_WVALID_in = AXI_06_WVALID; + assign AXI_07_ACLK_in = AXI_07_ACLK; + assign AXI_07_ARADDR_in = AXI_07_ARADDR; + assign AXI_07_ARBURST_in = AXI_07_ARBURST; + assign AXI_07_ARESET_N_in = AXI_07_ARESET_N; + assign AXI_07_ARID_in = AXI_07_ARID; + assign AXI_07_ARLEN_in = AXI_07_ARLEN; + assign AXI_07_ARSIZE_in = AXI_07_ARSIZE; + assign AXI_07_ARVALID_in = AXI_07_ARVALID; + assign AXI_07_AWADDR_in = AXI_07_AWADDR; + assign AXI_07_AWBURST_in = AXI_07_AWBURST; + assign AXI_07_AWID_in = AXI_07_AWID; + assign AXI_07_AWLEN_in = AXI_07_AWLEN; + assign AXI_07_AWSIZE_in = AXI_07_AWSIZE; + assign AXI_07_AWVALID_in = AXI_07_AWVALID; + assign AXI_07_BREADY_in = AXI_07_BREADY; + assign AXI_07_DFI_LP_PWR_X_REQ_in = AXI_07_DFI_LP_PWR_X_REQ; + assign AXI_07_RREADY_in = AXI_07_RREADY; + assign AXI_07_WDATA_PARITY_in = AXI_07_WDATA_PARITY; + assign AXI_07_WDATA_in = AXI_07_WDATA; + assign AXI_07_WLAST_in = AXI_07_WLAST; + assign AXI_07_WSTRB_in = AXI_07_WSTRB; + assign AXI_07_WVALID_in = AXI_07_WVALID; + assign AXI_08_ACLK_in = AXI_08_ACLK; + assign AXI_08_ARADDR_in = AXI_08_ARADDR; + assign AXI_08_ARBURST_in = AXI_08_ARBURST; + assign AXI_08_ARESET_N_in = AXI_08_ARESET_N; + assign AXI_08_ARID_in = AXI_08_ARID; + assign AXI_08_ARLEN_in = AXI_08_ARLEN; + assign AXI_08_ARSIZE_in = AXI_08_ARSIZE; + assign AXI_08_ARVALID_in = AXI_08_ARVALID; + assign AXI_08_AWADDR_in = AXI_08_AWADDR; + assign AXI_08_AWBURST_in = AXI_08_AWBURST; + assign AXI_08_AWID_in = AXI_08_AWID; + assign AXI_08_AWLEN_in = AXI_08_AWLEN; + assign AXI_08_AWSIZE_in = AXI_08_AWSIZE; + assign AXI_08_AWVALID_in = AXI_08_AWVALID; + assign AXI_08_BREADY_in = AXI_08_BREADY; + assign AXI_08_DFI_LP_PWR_X_REQ_in = AXI_08_DFI_LP_PWR_X_REQ; + assign AXI_08_RREADY_in = AXI_08_RREADY; + assign AXI_08_WDATA_PARITY_in = AXI_08_WDATA_PARITY; + assign AXI_08_WDATA_in = AXI_08_WDATA; + assign AXI_08_WLAST_in = AXI_08_WLAST; + assign AXI_08_WSTRB_in = AXI_08_WSTRB; + assign AXI_08_WVALID_in = AXI_08_WVALID; + assign AXI_09_ACLK_in = AXI_09_ACLK; + assign AXI_09_ARADDR_in = AXI_09_ARADDR; + assign AXI_09_ARBURST_in = AXI_09_ARBURST; + assign AXI_09_ARESET_N_in = AXI_09_ARESET_N; + assign AXI_09_ARID_in = AXI_09_ARID; + assign AXI_09_ARLEN_in = AXI_09_ARLEN; + assign AXI_09_ARSIZE_in = AXI_09_ARSIZE; + assign AXI_09_ARVALID_in = AXI_09_ARVALID; + assign AXI_09_AWADDR_in = AXI_09_AWADDR; + assign AXI_09_AWBURST_in = AXI_09_AWBURST; + assign AXI_09_AWID_in = AXI_09_AWID; + assign AXI_09_AWLEN_in = AXI_09_AWLEN; + assign AXI_09_AWSIZE_in = AXI_09_AWSIZE; + assign AXI_09_AWVALID_in = AXI_09_AWVALID; + assign AXI_09_BREADY_in = AXI_09_BREADY; + assign AXI_09_DFI_LP_PWR_X_REQ_in = AXI_09_DFI_LP_PWR_X_REQ; + assign AXI_09_RREADY_in = AXI_09_RREADY; + assign AXI_09_WDATA_PARITY_in = AXI_09_WDATA_PARITY; + assign AXI_09_WDATA_in = AXI_09_WDATA; + assign AXI_09_WLAST_in = AXI_09_WLAST; + assign AXI_09_WSTRB_in = AXI_09_WSTRB; + assign AXI_09_WVALID_in = AXI_09_WVALID; + assign AXI_10_ACLK_in = AXI_10_ACLK; + assign AXI_10_ARADDR_in = AXI_10_ARADDR; + assign AXI_10_ARBURST_in = AXI_10_ARBURST; + assign AXI_10_ARESET_N_in = AXI_10_ARESET_N; + assign AXI_10_ARID_in = AXI_10_ARID; + assign AXI_10_ARLEN_in = AXI_10_ARLEN; + assign AXI_10_ARSIZE_in = AXI_10_ARSIZE; + assign AXI_10_ARVALID_in = AXI_10_ARVALID; + assign AXI_10_AWADDR_in = AXI_10_AWADDR; + assign AXI_10_AWBURST_in = AXI_10_AWBURST; + assign AXI_10_AWID_in = AXI_10_AWID; + assign AXI_10_AWLEN_in = AXI_10_AWLEN; + assign AXI_10_AWSIZE_in = AXI_10_AWSIZE; + assign AXI_10_AWVALID_in = AXI_10_AWVALID; + assign AXI_10_BREADY_in = AXI_10_BREADY; + assign AXI_10_DFI_LP_PWR_X_REQ_in = AXI_10_DFI_LP_PWR_X_REQ; + assign AXI_10_RREADY_in = AXI_10_RREADY; + assign AXI_10_WDATA_PARITY_in = AXI_10_WDATA_PARITY; + assign AXI_10_WDATA_in = AXI_10_WDATA; + assign AXI_10_WLAST_in = AXI_10_WLAST; + assign AXI_10_WSTRB_in = AXI_10_WSTRB; + assign AXI_10_WVALID_in = AXI_10_WVALID; + assign AXI_11_ACLK_in = AXI_11_ACLK; + assign AXI_11_ARADDR_in = AXI_11_ARADDR; + assign AXI_11_ARBURST_in = AXI_11_ARBURST; + assign AXI_11_ARESET_N_in = AXI_11_ARESET_N; + assign AXI_11_ARID_in = AXI_11_ARID; + assign AXI_11_ARLEN_in = AXI_11_ARLEN; + assign AXI_11_ARSIZE_in = AXI_11_ARSIZE; + assign AXI_11_ARVALID_in = AXI_11_ARVALID; + assign AXI_11_AWADDR_in = AXI_11_AWADDR; + assign AXI_11_AWBURST_in = AXI_11_AWBURST; + assign AXI_11_AWID_in = AXI_11_AWID; + assign AXI_11_AWLEN_in = AXI_11_AWLEN; + assign AXI_11_AWSIZE_in = AXI_11_AWSIZE; + assign AXI_11_AWVALID_in = AXI_11_AWVALID; + assign AXI_11_BREADY_in = AXI_11_BREADY; + assign AXI_11_DFI_LP_PWR_X_REQ_in = AXI_11_DFI_LP_PWR_X_REQ; + assign AXI_11_RREADY_in = AXI_11_RREADY; + assign AXI_11_WDATA_PARITY_in = AXI_11_WDATA_PARITY; + assign AXI_11_WDATA_in = AXI_11_WDATA; + assign AXI_11_WLAST_in = AXI_11_WLAST; + assign AXI_11_WSTRB_in = AXI_11_WSTRB; + assign AXI_11_WVALID_in = AXI_11_WVALID; + assign AXI_12_ACLK_in = AXI_12_ACLK; + assign AXI_12_ARADDR_in = AXI_12_ARADDR; + assign AXI_12_ARBURST_in = AXI_12_ARBURST; + assign AXI_12_ARESET_N_in = AXI_12_ARESET_N; + assign AXI_12_ARID_in = AXI_12_ARID; + assign AXI_12_ARLEN_in = AXI_12_ARLEN; + assign AXI_12_ARSIZE_in = AXI_12_ARSIZE; + assign AXI_12_ARVALID_in = AXI_12_ARVALID; + assign AXI_12_AWADDR_in = AXI_12_AWADDR; + assign AXI_12_AWBURST_in = AXI_12_AWBURST; + assign AXI_12_AWID_in = AXI_12_AWID; + assign AXI_12_AWLEN_in = AXI_12_AWLEN; + assign AXI_12_AWSIZE_in = AXI_12_AWSIZE; + assign AXI_12_AWVALID_in = AXI_12_AWVALID; + assign AXI_12_BREADY_in = AXI_12_BREADY; + assign AXI_12_DFI_LP_PWR_X_REQ_in = AXI_12_DFI_LP_PWR_X_REQ; + assign AXI_12_RREADY_in = AXI_12_RREADY; + assign AXI_12_WDATA_PARITY_in = AXI_12_WDATA_PARITY; + assign AXI_12_WDATA_in = AXI_12_WDATA; + assign AXI_12_WLAST_in = AXI_12_WLAST; + assign AXI_12_WSTRB_in = AXI_12_WSTRB; + assign AXI_12_WVALID_in = AXI_12_WVALID; + assign AXI_13_ACLK_in = AXI_13_ACLK; + assign AXI_13_ARADDR_in = AXI_13_ARADDR; + assign AXI_13_ARBURST_in = AXI_13_ARBURST; + assign AXI_13_ARESET_N_in = AXI_13_ARESET_N; + assign AXI_13_ARID_in = AXI_13_ARID; + assign AXI_13_ARLEN_in = AXI_13_ARLEN; + assign AXI_13_ARSIZE_in = AXI_13_ARSIZE; + assign AXI_13_ARVALID_in = AXI_13_ARVALID; + assign AXI_13_AWADDR_in = AXI_13_AWADDR; + assign AXI_13_AWBURST_in = AXI_13_AWBURST; + assign AXI_13_AWID_in = AXI_13_AWID; + assign AXI_13_AWLEN_in = AXI_13_AWLEN; + assign AXI_13_AWSIZE_in = AXI_13_AWSIZE; + assign AXI_13_AWVALID_in = AXI_13_AWVALID; + assign AXI_13_BREADY_in = AXI_13_BREADY; + assign AXI_13_DFI_LP_PWR_X_REQ_in = AXI_13_DFI_LP_PWR_X_REQ; + assign AXI_13_RREADY_in = AXI_13_RREADY; + assign AXI_13_WDATA_PARITY_in = AXI_13_WDATA_PARITY; + assign AXI_13_WDATA_in = AXI_13_WDATA; + assign AXI_13_WLAST_in = AXI_13_WLAST; + assign AXI_13_WSTRB_in = AXI_13_WSTRB; + assign AXI_13_WVALID_in = AXI_13_WVALID; + assign AXI_14_ACLK_in = AXI_14_ACLK; + assign AXI_14_ARADDR_in = AXI_14_ARADDR; + assign AXI_14_ARBURST_in = AXI_14_ARBURST; + assign AXI_14_ARESET_N_in = AXI_14_ARESET_N; + assign AXI_14_ARID_in = AXI_14_ARID; + assign AXI_14_ARLEN_in = AXI_14_ARLEN; + assign AXI_14_ARSIZE_in = AXI_14_ARSIZE; + assign AXI_14_ARVALID_in = AXI_14_ARVALID; + assign AXI_14_AWADDR_in = AXI_14_AWADDR; + assign AXI_14_AWBURST_in = AXI_14_AWBURST; + assign AXI_14_AWID_in = AXI_14_AWID; + assign AXI_14_AWLEN_in = AXI_14_AWLEN; + assign AXI_14_AWSIZE_in = AXI_14_AWSIZE; + assign AXI_14_AWVALID_in = AXI_14_AWVALID; + assign AXI_14_BREADY_in = AXI_14_BREADY; + assign AXI_14_DFI_LP_PWR_X_REQ_in = AXI_14_DFI_LP_PWR_X_REQ; + assign AXI_14_RREADY_in = AXI_14_RREADY; + assign AXI_14_WDATA_PARITY_in = AXI_14_WDATA_PARITY; + assign AXI_14_WDATA_in = AXI_14_WDATA; + assign AXI_14_WLAST_in = AXI_14_WLAST; + assign AXI_14_WSTRB_in = AXI_14_WSTRB; + assign AXI_14_WVALID_in = AXI_14_WVALID; + assign AXI_15_ACLK_in = AXI_15_ACLK; + assign AXI_15_ARADDR_in = AXI_15_ARADDR; + assign AXI_15_ARBURST_in = AXI_15_ARBURST; + assign AXI_15_ARESET_N_in = AXI_15_ARESET_N; + assign AXI_15_ARID_in = AXI_15_ARID; + assign AXI_15_ARLEN_in = AXI_15_ARLEN; + assign AXI_15_ARSIZE_in = AXI_15_ARSIZE; + assign AXI_15_ARVALID_in = AXI_15_ARVALID; + assign AXI_15_AWADDR_in = AXI_15_AWADDR; + assign AXI_15_AWBURST_in = AXI_15_AWBURST; + assign AXI_15_AWID_in = AXI_15_AWID; + assign AXI_15_AWLEN_in = AXI_15_AWLEN; + assign AXI_15_AWSIZE_in = AXI_15_AWSIZE; + assign AXI_15_AWVALID_in = AXI_15_AWVALID; + assign AXI_15_BREADY_in = AXI_15_BREADY; + assign AXI_15_DFI_LP_PWR_X_REQ_in = AXI_15_DFI_LP_PWR_X_REQ; + assign AXI_15_RREADY_in = AXI_15_RREADY; + assign AXI_15_WDATA_PARITY_in = AXI_15_WDATA_PARITY; + assign AXI_15_WDATA_in = AXI_15_WDATA; + assign AXI_15_WLAST_in = AXI_15_WLAST; + assign AXI_15_WSTRB_in = AXI_15_WSTRB; + assign AXI_15_WVALID_in = AXI_15_WVALID; + assign AXI_16_ACLK_in = AXI_16_ACLK; + assign AXI_16_ARADDR_in = AXI_16_ARADDR; + assign AXI_16_ARBURST_in = AXI_16_ARBURST; + assign AXI_16_ARESET_N_in = AXI_16_ARESET_N; + assign AXI_16_ARID_in = AXI_16_ARID; + assign AXI_16_ARLEN_in = AXI_16_ARLEN; + assign AXI_16_ARSIZE_in = AXI_16_ARSIZE; + assign AXI_16_ARVALID_in = AXI_16_ARVALID; + assign AXI_16_AWADDR_in = AXI_16_AWADDR; + assign AXI_16_AWBURST_in = AXI_16_AWBURST; + assign AXI_16_AWID_in = AXI_16_AWID; + assign AXI_16_AWLEN_in = AXI_16_AWLEN; + assign AXI_16_AWSIZE_in = AXI_16_AWSIZE; + assign AXI_16_AWVALID_in = AXI_16_AWVALID; + assign AXI_16_BREADY_in = AXI_16_BREADY; + assign AXI_16_DFI_LP_PWR_X_REQ_in = AXI_16_DFI_LP_PWR_X_REQ; + assign AXI_16_RREADY_in = AXI_16_RREADY; + assign AXI_16_WDATA_PARITY_in = AXI_16_WDATA_PARITY; + assign AXI_16_WDATA_in = AXI_16_WDATA; + assign AXI_16_WLAST_in = AXI_16_WLAST; + assign AXI_16_WSTRB_in = AXI_16_WSTRB; + assign AXI_16_WVALID_in = AXI_16_WVALID; + assign AXI_17_ACLK_in = AXI_17_ACLK; + assign AXI_17_ARADDR_in = AXI_17_ARADDR; + assign AXI_17_ARBURST_in = AXI_17_ARBURST; + assign AXI_17_ARESET_N_in = AXI_17_ARESET_N; + assign AXI_17_ARID_in = AXI_17_ARID; + assign AXI_17_ARLEN_in = AXI_17_ARLEN; + assign AXI_17_ARSIZE_in = AXI_17_ARSIZE; + assign AXI_17_ARVALID_in = AXI_17_ARVALID; + assign AXI_17_AWADDR_in = AXI_17_AWADDR; + assign AXI_17_AWBURST_in = AXI_17_AWBURST; + assign AXI_17_AWID_in = AXI_17_AWID; + assign AXI_17_AWLEN_in = AXI_17_AWLEN; + assign AXI_17_AWSIZE_in = AXI_17_AWSIZE; + assign AXI_17_AWVALID_in = AXI_17_AWVALID; + assign AXI_17_BREADY_in = AXI_17_BREADY; + assign AXI_17_DFI_LP_PWR_X_REQ_in = AXI_17_DFI_LP_PWR_X_REQ; + assign AXI_17_RREADY_in = AXI_17_RREADY; + assign AXI_17_WDATA_PARITY_in = AXI_17_WDATA_PARITY; + assign AXI_17_WDATA_in = AXI_17_WDATA; + assign AXI_17_WLAST_in = AXI_17_WLAST; + assign AXI_17_WSTRB_in = AXI_17_WSTRB; + assign AXI_17_WVALID_in = AXI_17_WVALID; + assign AXI_18_ACLK_in = AXI_18_ACLK; + assign AXI_18_ARADDR_in = AXI_18_ARADDR; + assign AXI_18_ARBURST_in = AXI_18_ARBURST; + assign AXI_18_ARESET_N_in = AXI_18_ARESET_N; + assign AXI_18_ARID_in = AXI_18_ARID; + assign AXI_18_ARLEN_in = AXI_18_ARLEN; + assign AXI_18_ARSIZE_in = AXI_18_ARSIZE; + assign AXI_18_ARVALID_in = AXI_18_ARVALID; + assign AXI_18_AWADDR_in = AXI_18_AWADDR; + assign AXI_18_AWBURST_in = AXI_18_AWBURST; + assign AXI_18_AWID_in = AXI_18_AWID; + assign AXI_18_AWLEN_in = AXI_18_AWLEN; + assign AXI_18_AWSIZE_in = AXI_18_AWSIZE; + assign AXI_18_AWVALID_in = AXI_18_AWVALID; + assign AXI_18_BREADY_in = AXI_18_BREADY; + assign AXI_18_DFI_LP_PWR_X_REQ_in = AXI_18_DFI_LP_PWR_X_REQ; + assign AXI_18_RREADY_in = AXI_18_RREADY; + assign AXI_18_WDATA_PARITY_in = AXI_18_WDATA_PARITY; + assign AXI_18_WDATA_in = AXI_18_WDATA; + assign AXI_18_WLAST_in = AXI_18_WLAST; + assign AXI_18_WSTRB_in = AXI_18_WSTRB; + assign AXI_18_WVALID_in = AXI_18_WVALID; + assign AXI_19_ACLK_in = AXI_19_ACLK; + assign AXI_19_ARADDR_in = AXI_19_ARADDR; + assign AXI_19_ARBURST_in = AXI_19_ARBURST; + assign AXI_19_ARESET_N_in = AXI_19_ARESET_N; + assign AXI_19_ARID_in = AXI_19_ARID; + assign AXI_19_ARLEN_in = AXI_19_ARLEN; + assign AXI_19_ARSIZE_in = AXI_19_ARSIZE; + assign AXI_19_ARVALID_in = AXI_19_ARVALID; + assign AXI_19_AWADDR_in = AXI_19_AWADDR; + assign AXI_19_AWBURST_in = AXI_19_AWBURST; + assign AXI_19_AWID_in = AXI_19_AWID; + assign AXI_19_AWLEN_in = AXI_19_AWLEN; + assign AXI_19_AWSIZE_in = AXI_19_AWSIZE; + assign AXI_19_AWVALID_in = AXI_19_AWVALID; + assign AXI_19_BREADY_in = AXI_19_BREADY; + assign AXI_19_DFI_LP_PWR_X_REQ_in = AXI_19_DFI_LP_PWR_X_REQ; + assign AXI_19_RREADY_in = AXI_19_RREADY; + assign AXI_19_WDATA_PARITY_in = AXI_19_WDATA_PARITY; + assign AXI_19_WDATA_in = AXI_19_WDATA; + assign AXI_19_WLAST_in = AXI_19_WLAST; + assign AXI_19_WSTRB_in = AXI_19_WSTRB; + assign AXI_19_WVALID_in = AXI_19_WVALID; + assign AXI_20_ACLK_in = AXI_20_ACLK; + assign AXI_20_ARADDR_in = AXI_20_ARADDR; + assign AXI_20_ARBURST_in = AXI_20_ARBURST; + assign AXI_20_ARESET_N_in = AXI_20_ARESET_N; + assign AXI_20_ARID_in = AXI_20_ARID; + assign AXI_20_ARLEN_in = AXI_20_ARLEN; + assign AXI_20_ARSIZE_in = AXI_20_ARSIZE; + assign AXI_20_ARVALID_in = AXI_20_ARVALID; + assign AXI_20_AWADDR_in = AXI_20_AWADDR; + assign AXI_20_AWBURST_in = AXI_20_AWBURST; + assign AXI_20_AWID_in = AXI_20_AWID; + assign AXI_20_AWLEN_in = AXI_20_AWLEN; + assign AXI_20_AWSIZE_in = AXI_20_AWSIZE; + assign AXI_20_AWVALID_in = AXI_20_AWVALID; + assign AXI_20_BREADY_in = AXI_20_BREADY; + assign AXI_20_DFI_LP_PWR_X_REQ_in = AXI_20_DFI_LP_PWR_X_REQ; + assign AXI_20_RREADY_in = AXI_20_RREADY; + assign AXI_20_WDATA_PARITY_in = AXI_20_WDATA_PARITY; + assign AXI_20_WDATA_in = AXI_20_WDATA; + assign AXI_20_WLAST_in = AXI_20_WLAST; + assign AXI_20_WSTRB_in = AXI_20_WSTRB; + assign AXI_20_WVALID_in = AXI_20_WVALID; + assign AXI_21_ACLK_in = AXI_21_ACLK; + assign AXI_21_ARADDR_in = AXI_21_ARADDR; + assign AXI_21_ARBURST_in = AXI_21_ARBURST; + assign AXI_21_ARESET_N_in = AXI_21_ARESET_N; + assign AXI_21_ARID_in = AXI_21_ARID; + assign AXI_21_ARLEN_in = AXI_21_ARLEN; + assign AXI_21_ARSIZE_in = AXI_21_ARSIZE; + assign AXI_21_ARVALID_in = AXI_21_ARVALID; + assign AXI_21_AWADDR_in = AXI_21_AWADDR; + assign AXI_21_AWBURST_in = AXI_21_AWBURST; + assign AXI_21_AWID_in = AXI_21_AWID; + assign AXI_21_AWLEN_in = AXI_21_AWLEN; + assign AXI_21_AWSIZE_in = AXI_21_AWSIZE; + assign AXI_21_AWVALID_in = AXI_21_AWVALID; + assign AXI_21_BREADY_in = AXI_21_BREADY; + assign AXI_21_DFI_LP_PWR_X_REQ_in = AXI_21_DFI_LP_PWR_X_REQ; + assign AXI_21_RREADY_in = AXI_21_RREADY; + assign AXI_21_WDATA_PARITY_in = AXI_21_WDATA_PARITY; + assign AXI_21_WDATA_in = AXI_21_WDATA; + assign AXI_21_WLAST_in = AXI_21_WLAST; + assign AXI_21_WSTRB_in = AXI_21_WSTRB; + assign AXI_21_WVALID_in = AXI_21_WVALID; + assign AXI_22_ACLK_in = AXI_22_ACLK; + assign AXI_22_ARADDR_in = AXI_22_ARADDR; + assign AXI_22_ARBURST_in = AXI_22_ARBURST; + assign AXI_22_ARESET_N_in = AXI_22_ARESET_N; + assign AXI_22_ARID_in = AXI_22_ARID; + assign AXI_22_ARLEN_in = AXI_22_ARLEN; + assign AXI_22_ARSIZE_in = AXI_22_ARSIZE; + assign AXI_22_ARVALID_in = AXI_22_ARVALID; + assign AXI_22_AWADDR_in = AXI_22_AWADDR; + assign AXI_22_AWBURST_in = AXI_22_AWBURST; + assign AXI_22_AWID_in = AXI_22_AWID; + assign AXI_22_AWLEN_in = AXI_22_AWLEN; + assign AXI_22_AWSIZE_in = AXI_22_AWSIZE; + assign AXI_22_AWVALID_in = AXI_22_AWVALID; + assign AXI_22_BREADY_in = AXI_22_BREADY; + assign AXI_22_DFI_LP_PWR_X_REQ_in = AXI_22_DFI_LP_PWR_X_REQ; + assign AXI_22_RREADY_in = AXI_22_RREADY; + assign AXI_22_WDATA_PARITY_in = AXI_22_WDATA_PARITY; + assign AXI_22_WDATA_in = AXI_22_WDATA; + assign AXI_22_WLAST_in = AXI_22_WLAST; + assign AXI_22_WSTRB_in = AXI_22_WSTRB; + assign AXI_22_WVALID_in = AXI_22_WVALID; + assign AXI_23_ACLK_in = AXI_23_ACLK; + assign AXI_23_ARADDR_in = AXI_23_ARADDR; + assign AXI_23_ARBURST_in = AXI_23_ARBURST; + assign AXI_23_ARESET_N_in = AXI_23_ARESET_N; + assign AXI_23_ARID_in = AXI_23_ARID; + assign AXI_23_ARLEN_in = AXI_23_ARLEN; + assign AXI_23_ARSIZE_in = AXI_23_ARSIZE; + assign AXI_23_ARVALID_in = AXI_23_ARVALID; + assign AXI_23_AWADDR_in = AXI_23_AWADDR; + assign AXI_23_AWBURST_in = AXI_23_AWBURST; + assign AXI_23_AWID_in = AXI_23_AWID; + assign AXI_23_AWLEN_in = AXI_23_AWLEN; + assign AXI_23_AWSIZE_in = AXI_23_AWSIZE; + assign AXI_23_AWVALID_in = AXI_23_AWVALID; + assign AXI_23_BREADY_in = AXI_23_BREADY; + assign AXI_23_DFI_LP_PWR_X_REQ_in = AXI_23_DFI_LP_PWR_X_REQ; + assign AXI_23_RREADY_in = AXI_23_RREADY; + assign AXI_23_WDATA_PARITY_in = AXI_23_WDATA_PARITY; + assign AXI_23_WDATA_in = AXI_23_WDATA; + assign AXI_23_WLAST_in = AXI_23_WLAST; + assign AXI_23_WSTRB_in = AXI_23_WSTRB; + assign AXI_23_WVALID_in = AXI_23_WVALID; + assign AXI_24_ACLK_in = AXI_24_ACLK; + assign AXI_24_ARADDR_in = AXI_24_ARADDR; + assign AXI_24_ARBURST_in = AXI_24_ARBURST; + assign AXI_24_ARESET_N_in = AXI_24_ARESET_N; + assign AXI_24_ARID_in = AXI_24_ARID; + assign AXI_24_ARLEN_in = AXI_24_ARLEN; + assign AXI_24_ARSIZE_in = AXI_24_ARSIZE; + assign AXI_24_ARVALID_in = AXI_24_ARVALID; + assign AXI_24_AWADDR_in = AXI_24_AWADDR; + assign AXI_24_AWBURST_in = AXI_24_AWBURST; + assign AXI_24_AWID_in = AXI_24_AWID; + assign AXI_24_AWLEN_in = AXI_24_AWLEN; + assign AXI_24_AWSIZE_in = AXI_24_AWSIZE; + assign AXI_24_AWVALID_in = AXI_24_AWVALID; + assign AXI_24_BREADY_in = AXI_24_BREADY; + assign AXI_24_DFI_LP_PWR_X_REQ_in = AXI_24_DFI_LP_PWR_X_REQ; + assign AXI_24_RREADY_in = AXI_24_RREADY; + assign AXI_24_WDATA_PARITY_in = AXI_24_WDATA_PARITY; + assign AXI_24_WDATA_in = AXI_24_WDATA; + assign AXI_24_WLAST_in = AXI_24_WLAST; + assign AXI_24_WSTRB_in = AXI_24_WSTRB; + assign AXI_24_WVALID_in = AXI_24_WVALID; + assign AXI_25_ACLK_in = AXI_25_ACLK; + assign AXI_25_ARADDR_in = AXI_25_ARADDR; + assign AXI_25_ARBURST_in = AXI_25_ARBURST; + assign AXI_25_ARESET_N_in = AXI_25_ARESET_N; + assign AXI_25_ARID_in = AXI_25_ARID; + assign AXI_25_ARLEN_in = AXI_25_ARLEN; + assign AXI_25_ARSIZE_in = AXI_25_ARSIZE; + assign AXI_25_ARVALID_in = AXI_25_ARVALID; + assign AXI_25_AWADDR_in = AXI_25_AWADDR; + assign AXI_25_AWBURST_in = AXI_25_AWBURST; + assign AXI_25_AWID_in = AXI_25_AWID; + assign AXI_25_AWLEN_in = AXI_25_AWLEN; + assign AXI_25_AWSIZE_in = AXI_25_AWSIZE; + assign AXI_25_AWVALID_in = AXI_25_AWVALID; + assign AXI_25_BREADY_in = AXI_25_BREADY; + assign AXI_25_DFI_LP_PWR_X_REQ_in = AXI_25_DFI_LP_PWR_X_REQ; + assign AXI_25_RREADY_in = AXI_25_RREADY; + assign AXI_25_WDATA_PARITY_in = AXI_25_WDATA_PARITY; + assign AXI_25_WDATA_in = AXI_25_WDATA; + assign AXI_25_WLAST_in = AXI_25_WLAST; + assign AXI_25_WSTRB_in = AXI_25_WSTRB; + assign AXI_25_WVALID_in = AXI_25_WVALID; + assign AXI_26_ACLK_in = AXI_26_ACLK; + assign AXI_26_ARADDR_in = AXI_26_ARADDR; + assign AXI_26_ARBURST_in = AXI_26_ARBURST; + assign AXI_26_ARESET_N_in = AXI_26_ARESET_N; + assign AXI_26_ARID_in = AXI_26_ARID; + assign AXI_26_ARLEN_in = AXI_26_ARLEN; + assign AXI_26_ARSIZE_in = AXI_26_ARSIZE; + assign AXI_26_ARVALID_in = AXI_26_ARVALID; + assign AXI_26_AWADDR_in = AXI_26_AWADDR; + assign AXI_26_AWBURST_in = AXI_26_AWBURST; + assign AXI_26_AWID_in = AXI_26_AWID; + assign AXI_26_AWLEN_in = AXI_26_AWLEN; + assign AXI_26_AWSIZE_in = AXI_26_AWSIZE; + assign AXI_26_AWVALID_in = AXI_26_AWVALID; + assign AXI_26_BREADY_in = AXI_26_BREADY; + assign AXI_26_DFI_LP_PWR_X_REQ_in = AXI_26_DFI_LP_PWR_X_REQ; + assign AXI_26_RREADY_in = AXI_26_RREADY; + assign AXI_26_WDATA_PARITY_in = AXI_26_WDATA_PARITY; + assign AXI_26_WDATA_in = AXI_26_WDATA; + assign AXI_26_WLAST_in = AXI_26_WLAST; + assign AXI_26_WSTRB_in = AXI_26_WSTRB; + assign AXI_26_WVALID_in = AXI_26_WVALID; + assign AXI_27_ACLK_in = AXI_27_ACLK; + assign AXI_27_ARADDR_in = AXI_27_ARADDR; + assign AXI_27_ARBURST_in = AXI_27_ARBURST; + assign AXI_27_ARESET_N_in = AXI_27_ARESET_N; + assign AXI_27_ARID_in = AXI_27_ARID; + assign AXI_27_ARLEN_in = AXI_27_ARLEN; + assign AXI_27_ARSIZE_in = AXI_27_ARSIZE; + assign AXI_27_ARVALID_in = AXI_27_ARVALID; + assign AXI_27_AWADDR_in = AXI_27_AWADDR; + assign AXI_27_AWBURST_in = AXI_27_AWBURST; + assign AXI_27_AWID_in = AXI_27_AWID; + assign AXI_27_AWLEN_in = AXI_27_AWLEN; + assign AXI_27_AWSIZE_in = AXI_27_AWSIZE; + assign AXI_27_AWVALID_in = AXI_27_AWVALID; + assign AXI_27_BREADY_in = AXI_27_BREADY; + assign AXI_27_DFI_LP_PWR_X_REQ_in = AXI_27_DFI_LP_PWR_X_REQ; + assign AXI_27_RREADY_in = AXI_27_RREADY; + assign AXI_27_WDATA_PARITY_in = AXI_27_WDATA_PARITY; + assign AXI_27_WDATA_in = AXI_27_WDATA; + assign AXI_27_WLAST_in = AXI_27_WLAST; + assign AXI_27_WSTRB_in = AXI_27_WSTRB; + assign AXI_27_WVALID_in = AXI_27_WVALID; + assign AXI_28_ACLK_in = AXI_28_ACLK; + assign AXI_28_ARADDR_in = AXI_28_ARADDR; + assign AXI_28_ARBURST_in = AXI_28_ARBURST; + assign AXI_28_ARESET_N_in = AXI_28_ARESET_N; + assign AXI_28_ARID_in = AXI_28_ARID; + assign AXI_28_ARLEN_in = AXI_28_ARLEN; + assign AXI_28_ARSIZE_in = AXI_28_ARSIZE; + assign AXI_28_ARVALID_in = AXI_28_ARVALID; + assign AXI_28_AWADDR_in = AXI_28_AWADDR; + assign AXI_28_AWBURST_in = AXI_28_AWBURST; + assign AXI_28_AWID_in = AXI_28_AWID; + assign AXI_28_AWLEN_in = AXI_28_AWLEN; + assign AXI_28_AWSIZE_in = AXI_28_AWSIZE; + assign AXI_28_AWVALID_in = AXI_28_AWVALID; + assign AXI_28_BREADY_in = AXI_28_BREADY; + assign AXI_28_DFI_LP_PWR_X_REQ_in = AXI_28_DFI_LP_PWR_X_REQ; + assign AXI_28_RREADY_in = AXI_28_RREADY; + assign AXI_28_WDATA_PARITY_in = AXI_28_WDATA_PARITY; + assign AXI_28_WDATA_in = AXI_28_WDATA; + assign AXI_28_WLAST_in = AXI_28_WLAST; + assign AXI_28_WSTRB_in = AXI_28_WSTRB; + assign AXI_28_WVALID_in = AXI_28_WVALID; + assign AXI_29_ACLK_in = AXI_29_ACLK; + assign AXI_29_ARADDR_in = AXI_29_ARADDR; + assign AXI_29_ARBURST_in = AXI_29_ARBURST; + assign AXI_29_ARESET_N_in = AXI_29_ARESET_N; + assign AXI_29_ARID_in = AXI_29_ARID; + assign AXI_29_ARLEN_in = AXI_29_ARLEN; + assign AXI_29_ARSIZE_in = AXI_29_ARSIZE; + assign AXI_29_ARVALID_in = AXI_29_ARVALID; + assign AXI_29_AWADDR_in = AXI_29_AWADDR; + assign AXI_29_AWBURST_in = AXI_29_AWBURST; + assign AXI_29_AWID_in = AXI_29_AWID; + assign AXI_29_AWLEN_in = AXI_29_AWLEN; + assign AXI_29_AWSIZE_in = AXI_29_AWSIZE; + assign AXI_29_AWVALID_in = AXI_29_AWVALID; + assign AXI_29_BREADY_in = AXI_29_BREADY; + assign AXI_29_DFI_LP_PWR_X_REQ_in = AXI_29_DFI_LP_PWR_X_REQ; + assign AXI_29_RREADY_in = AXI_29_RREADY; + assign AXI_29_WDATA_PARITY_in = AXI_29_WDATA_PARITY; + assign AXI_29_WDATA_in = AXI_29_WDATA; + assign AXI_29_WLAST_in = AXI_29_WLAST; + assign AXI_29_WSTRB_in = AXI_29_WSTRB; + assign AXI_29_WVALID_in = AXI_29_WVALID; + assign AXI_30_ACLK_in = AXI_30_ACLK; + assign AXI_30_ARADDR_in = AXI_30_ARADDR; + assign AXI_30_ARBURST_in = AXI_30_ARBURST; + assign AXI_30_ARESET_N_in = AXI_30_ARESET_N; + assign AXI_30_ARID_in = AXI_30_ARID; + assign AXI_30_ARLEN_in = AXI_30_ARLEN; + assign AXI_30_ARSIZE_in = AXI_30_ARSIZE; + assign AXI_30_ARVALID_in = AXI_30_ARVALID; + assign AXI_30_AWADDR_in = AXI_30_AWADDR; + assign AXI_30_AWBURST_in = AXI_30_AWBURST; + assign AXI_30_AWID_in = AXI_30_AWID; + assign AXI_30_AWLEN_in = AXI_30_AWLEN; + assign AXI_30_AWSIZE_in = AXI_30_AWSIZE; + assign AXI_30_AWVALID_in = AXI_30_AWVALID; + assign AXI_30_BREADY_in = AXI_30_BREADY; + assign AXI_30_DFI_LP_PWR_X_REQ_in = AXI_30_DFI_LP_PWR_X_REQ; + assign AXI_30_RREADY_in = AXI_30_RREADY; + assign AXI_30_WDATA_PARITY_in = AXI_30_WDATA_PARITY; + assign AXI_30_WDATA_in = AXI_30_WDATA; + assign AXI_30_WLAST_in = AXI_30_WLAST; + assign AXI_30_WSTRB_in = AXI_30_WSTRB; + assign AXI_30_WVALID_in = AXI_30_WVALID; + assign AXI_31_ACLK_in = AXI_31_ACLK; + assign AXI_31_ARADDR_in = AXI_31_ARADDR; + assign AXI_31_ARBURST_in = AXI_31_ARBURST; + assign AXI_31_ARESET_N_in = AXI_31_ARESET_N; + assign AXI_31_ARID_in = AXI_31_ARID; + assign AXI_31_ARLEN_in = AXI_31_ARLEN; + assign AXI_31_ARSIZE_in = AXI_31_ARSIZE; + assign AXI_31_ARVALID_in = AXI_31_ARVALID; + assign AXI_31_AWADDR_in = AXI_31_AWADDR; + assign AXI_31_AWBURST_in = AXI_31_AWBURST; + assign AXI_31_AWID_in = AXI_31_AWID; + assign AXI_31_AWLEN_in = AXI_31_AWLEN; + assign AXI_31_AWSIZE_in = AXI_31_AWSIZE; + assign AXI_31_AWVALID_in = AXI_31_AWVALID; + assign AXI_31_BREADY_in = AXI_31_BREADY; + assign AXI_31_DFI_LP_PWR_X_REQ_in = AXI_31_DFI_LP_PWR_X_REQ; + assign AXI_31_RREADY_in = AXI_31_RREADY; + assign AXI_31_WDATA_PARITY_in = AXI_31_WDATA_PARITY; + assign AXI_31_WDATA_in = AXI_31_WDATA; + assign AXI_31_WLAST_in = AXI_31_WLAST; + assign AXI_31_WSTRB_in = AXI_31_WSTRB; + assign AXI_31_WVALID_in = AXI_31_WVALID; + assign BSCAN_DRCK_0_in = BSCAN_DRCK_0; + assign BSCAN_DRCK_1_in = BSCAN_DRCK_1; + assign BSCAN_TCK_0_in = BSCAN_TCK_0; + assign BSCAN_TCK_1_in = BSCAN_TCK_1; + assign HBM_REF_CLK_0_in = HBM_REF_CLK_0; + assign HBM_REF_CLK_1_in = HBM_REF_CLK_1; + assign MBIST_EN_00_in = MBIST_EN_00; + assign MBIST_EN_01_in = MBIST_EN_01; + assign MBIST_EN_02_in = MBIST_EN_02; + assign MBIST_EN_03_in = MBIST_EN_03; + assign MBIST_EN_04_in = MBIST_EN_04; + assign MBIST_EN_05_in = MBIST_EN_05; + assign MBIST_EN_06_in = MBIST_EN_06; + assign MBIST_EN_07_in = MBIST_EN_07; + assign MBIST_EN_08_in = MBIST_EN_08; + assign MBIST_EN_09_in = MBIST_EN_09; + assign MBIST_EN_10_in = MBIST_EN_10; + assign MBIST_EN_11_in = MBIST_EN_11; + assign MBIST_EN_12_in = MBIST_EN_12; + assign MBIST_EN_13_in = MBIST_EN_13; + assign MBIST_EN_14_in = MBIST_EN_14; + assign MBIST_EN_15_in = MBIST_EN_15; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLK_SEL_00_REG != "FALSE") && + (CLK_SEL_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] CLK_SEL_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_01_REG != "FALSE") && + (CLK_SEL_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] CLK_SEL_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_02_REG != "FALSE") && + (CLK_SEL_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] CLK_SEL_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_03_REG != "FALSE") && + (CLK_SEL_03_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] CLK_SEL_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_04_REG != "FALSE") && + (CLK_SEL_04_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] CLK_SEL_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_05_REG != "FALSE") && + (CLK_SEL_05_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] CLK_SEL_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_06_REG != "FALSE") && + (CLK_SEL_06_REG != "TRUE"))) begin + $display("Error: [Unisim %s-115] CLK_SEL_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_07_REG != "FALSE") && + (CLK_SEL_07_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] CLK_SEL_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_08_REG != "FALSE") && + (CLK_SEL_08_REG != "TRUE"))) begin + $display("Error: [Unisim %s-117] CLK_SEL_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_09_REG != "FALSE") && + (CLK_SEL_09_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] CLK_SEL_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_10_REG != "FALSE") && + (CLK_SEL_10_REG != "TRUE"))) begin + $display("Error: [Unisim %s-119] CLK_SEL_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_11_REG != "FALSE") && + (CLK_SEL_11_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] CLK_SEL_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_12_REG != "FALSE") && + (CLK_SEL_12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-121] CLK_SEL_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_13_REG != "FALSE") && + (CLK_SEL_13_REG != "TRUE"))) begin + $display("Error: [Unisim %s-122] CLK_SEL_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_14_REG != "FALSE") && + (CLK_SEL_14_REG != "TRUE"))) begin + $display("Error: [Unisim %s-123] CLK_SEL_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_15_REG != "FALSE") && + (CLK_SEL_15_REG != "TRUE"))) begin + $display("Error: [Unisim %s-124] CLK_SEL_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_16_REG != "FALSE") && + (CLK_SEL_16_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] CLK_SEL_16 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_16_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_17_REG != "FALSE") && + (CLK_SEL_17_REG != "TRUE"))) begin + $display("Error: [Unisim %s-126] CLK_SEL_17 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_17_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_18_REG != "FALSE") && + (CLK_SEL_18_REG != "TRUE"))) begin + $display("Error: [Unisim %s-127] CLK_SEL_18 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_18_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_19_REG != "FALSE") && + (CLK_SEL_19_REG != "TRUE"))) begin + $display("Error: [Unisim %s-128] CLK_SEL_19 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_19_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_20_REG != "FALSE") && + (CLK_SEL_20_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] CLK_SEL_20 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_20_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_21_REG != "FALSE") && + (CLK_SEL_21_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] CLK_SEL_21 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_21_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_22_REG != "FALSE") && + (CLK_SEL_22_REG != "TRUE"))) begin + $display("Error: [Unisim %s-131] CLK_SEL_22 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_22_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_23_REG != "FALSE") && + (CLK_SEL_23_REG != "TRUE"))) begin + $display("Error: [Unisim %s-132] CLK_SEL_23 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_23_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_24_REG != "FALSE") && + (CLK_SEL_24_REG != "TRUE"))) begin + $display("Error: [Unisim %s-133] CLK_SEL_24 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_24_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_25_REG != "FALSE") && + (CLK_SEL_25_REG != "TRUE"))) begin + $display("Error: [Unisim %s-134] CLK_SEL_25 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_25_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_26_REG != "FALSE") && + (CLK_SEL_26_REG != "TRUE"))) begin + $display("Error: [Unisim %s-135] CLK_SEL_26 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_26_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_27_REG != "FALSE") && + (CLK_SEL_27_REG != "TRUE"))) begin + $display("Error: [Unisim %s-136] CLK_SEL_27 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_27_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_28_REG != "FALSE") && + (CLK_SEL_28_REG != "TRUE"))) begin + $display("Error: [Unisim %s-137] CLK_SEL_28 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_28_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_29_REG != "FALSE") && + (CLK_SEL_29_REG != "TRUE"))) begin + $display("Error: [Unisim %s-138] CLK_SEL_29 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_29_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_30_REG != "FALSE") && + (CLK_SEL_30_REG != "TRUE"))) begin + $display("Error: [Unisim %s-139] CLK_SEL_30 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_30_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLK_SEL_31_REG != "FALSE") && + (CLK_SEL_31_REG != "TRUE"))) begin + $display("Error: [Unisim %s-140] CLK_SEL_31 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_31_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_00_REG < 50) || (DATARATE_00_REG > 1800))) begin + $display("Error: [Unisim %s-141] DATARATE_00 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_01_REG < 50) || (DATARATE_01_REG > 1800))) begin + $display("Error: [Unisim %s-142] DATARATE_01 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_02_REG < 50) || (DATARATE_02_REG > 1800))) begin + $display("Error: [Unisim %s-143] DATARATE_02 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_03_REG < 50) || (DATARATE_03_REG > 1800))) begin + $display("Error: [Unisim %s-144] DATARATE_03 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_04_REG < 50) || (DATARATE_04_REG > 1800))) begin + $display("Error: [Unisim %s-145] DATARATE_04 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_05_REG < 50) || (DATARATE_05_REG > 1800))) begin + $display("Error: [Unisim %s-146] DATARATE_05 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_06_REG < 50) || (DATARATE_06_REG > 1800))) begin + $display("Error: [Unisim %s-147] DATARATE_06 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_07_REG < 50) || (DATARATE_07_REG > 1800))) begin + $display("Error: [Unisim %s-148] DATARATE_07 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_08_REG < 50) || (DATARATE_08_REG > 1800))) begin + $display("Error: [Unisim %s-149] DATARATE_08 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_09_REG < 50) || (DATARATE_09_REG > 1800))) begin + $display("Error: [Unisim %s-150] DATARATE_09 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_10_REG < 50) || (DATARATE_10_REG > 1800))) begin + $display("Error: [Unisim %s-151] DATARATE_10 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_11_REG < 50) || (DATARATE_11_REG > 1800))) begin + $display("Error: [Unisim %s-152] DATARATE_11 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_12_REG < 50) || (DATARATE_12_REG > 1800))) begin + $display("Error: [Unisim %s-153] DATARATE_12 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_13_REG < 50) || (DATARATE_13_REG > 1800))) begin + $display("Error: [Unisim %s-154] DATARATE_13 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_14_REG < 50) || (DATARATE_14_REG > 1800))) begin + $display("Error: [Unisim %s-155] DATARATE_14 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATARATE_15_REG < 50) || (DATARATE_15_REG > 1800))) begin + $display("Error: [Unisim %s-156] DATARATE_15 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DA_LOCKOUT_0_REG != "FALSE") && + (DA_LOCKOUT_0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-157] DA_LOCKOUT_0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DA_LOCKOUT_0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DA_LOCKOUT_1_REG != "FALSE") && + (DA_LOCKOUT_1_REG != "TRUE"))) begin + $display("Error: [Unisim %s-158] DA_LOCKOUT_1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DA_LOCKOUT_1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_00_REG != "FALSE") && + (MC_ENABLE_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-253] MC_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_01_REG != "FALSE") && + (MC_ENABLE_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-254] MC_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_02_REG != "FALSE") && + (MC_ENABLE_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-255] MC_ENABLE_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_03_REG != "FALSE") && + (MC_ENABLE_03_REG != "TRUE"))) begin + $display("Error: [Unisim %s-256] MC_ENABLE_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_04_REG != "FALSE") && + (MC_ENABLE_04_REG != "TRUE"))) begin + $display("Error: [Unisim %s-257] MC_ENABLE_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_05_REG != "FALSE") && + (MC_ENABLE_05_REG != "TRUE"))) begin + $display("Error: [Unisim %s-258] MC_ENABLE_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_06_REG != "FALSE") && + (MC_ENABLE_06_REG != "TRUE"))) begin + $display("Error: [Unisim %s-259] MC_ENABLE_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_07_REG != "FALSE") && + (MC_ENABLE_07_REG != "TRUE"))) begin + $display("Error: [Unisim %s-260] MC_ENABLE_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_08_REG != "FALSE") && + (MC_ENABLE_08_REG != "TRUE"))) begin + $display("Error: [Unisim %s-261] MC_ENABLE_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_09_REG != "FALSE") && + (MC_ENABLE_09_REG != "TRUE"))) begin + $display("Error: [Unisim %s-262] MC_ENABLE_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_10_REG != "FALSE") && + (MC_ENABLE_10_REG != "TRUE"))) begin + $display("Error: [Unisim %s-263] MC_ENABLE_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_11_REG != "FALSE") && + (MC_ENABLE_11_REG != "TRUE"))) begin + $display("Error: [Unisim %s-264] MC_ENABLE_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_12_REG != "FALSE") && + (MC_ENABLE_12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-265] MC_ENABLE_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_13_REG != "FALSE") && + (MC_ENABLE_13_REG != "TRUE"))) begin + $display("Error: [Unisim %s-266] MC_ENABLE_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_14_REG != "FALSE") && + (MC_ENABLE_14_REG != "TRUE"))) begin + $display("Error: [Unisim %s-267] MC_ENABLE_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_15_REG != "FALSE") && + (MC_ENABLE_15_REG != "TRUE"))) begin + $display("Error: [Unisim %s-268] MC_ENABLE_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_APB_00_REG != "FALSE") && + (MC_ENABLE_APB_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-269] MC_ENABLE_APB_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_APB_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MC_ENABLE_APB_01_REG != "FALSE") && + (MC_ENABLE_APB_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-270] MC_ENABLE_APB_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_APB_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PAGEHIT_PERCENT_00_REG < 0) || (PAGEHIT_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-287] PAGEHIT_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PAGEHIT_PERCENT_01_REG < 0) || (PAGEHIT_PERCENT_01_REG > 100))) begin + $display("Error: [Unisim %s-288] PAGEHIT_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_00_REG != "FALSE") && + (PHY_ENABLE_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-291] PHY_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_01_REG != "FALSE") && + (PHY_ENABLE_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-292] PHY_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_02_REG != "FALSE") && + (PHY_ENABLE_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-293] PHY_ENABLE_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_03_REG != "FALSE") && + (PHY_ENABLE_03_REG != "TRUE"))) begin + $display("Error: [Unisim %s-294] PHY_ENABLE_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_04_REG != "FALSE") && + (PHY_ENABLE_04_REG != "TRUE"))) begin + $display("Error: [Unisim %s-295] PHY_ENABLE_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_05_REG != "FALSE") && + (PHY_ENABLE_05_REG != "TRUE"))) begin + $display("Error: [Unisim %s-296] PHY_ENABLE_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_06_REG != "FALSE") && + (PHY_ENABLE_06_REG != "TRUE"))) begin + $display("Error: [Unisim %s-297] PHY_ENABLE_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_07_REG != "FALSE") && + (PHY_ENABLE_07_REG != "TRUE"))) begin + $display("Error: [Unisim %s-298] PHY_ENABLE_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_08_REG != "FALSE") && + (PHY_ENABLE_08_REG != "TRUE"))) begin + $display("Error: [Unisim %s-299] PHY_ENABLE_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_09_REG != "FALSE") && + (PHY_ENABLE_09_REG != "TRUE"))) begin + $display("Error: [Unisim %s-300] PHY_ENABLE_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_10_REG != "FALSE") && + (PHY_ENABLE_10_REG != "TRUE"))) begin + $display("Error: [Unisim %s-301] PHY_ENABLE_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_11_REG != "FALSE") && + (PHY_ENABLE_11_REG != "TRUE"))) begin + $display("Error: [Unisim %s-302] PHY_ENABLE_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_12_REG != "FALSE") && + (PHY_ENABLE_12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-303] PHY_ENABLE_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_13_REG != "FALSE") && + (PHY_ENABLE_13_REG != "TRUE"))) begin + $display("Error: [Unisim %s-304] PHY_ENABLE_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_14_REG != "FALSE") && + (PHY_ENABLE_14_REG != "TRUE"))) begin + $display("Error: [Unisim %s-305] PHY_ENABLE_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_15_REG != "FALSE") && + (PHY_ENABLE_15_REG != "TRUE"))) begin + $display("Error: [Unisim %s-306] PHY_ENABLE_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_16_REG != "FALSE") && + (PHY_ENABLE_16_REG != "TRUE"))) begin + $display("Error: [Unisim %s-307] PHY_ENABLE_16 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_16_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_17_REG != "FALSE") && + (PHY_ENABLE_17_REG != "TRUE"))) begin + $display("Error: [Unisim %s-308] PHY_ENABLE_17 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_17_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_18_REG != "FALSE") && + (PHY_ENABLE_18_REG != "TRUE"))) begin + $display("Error: [Unisim %s-309] PHY_ENABLE_18 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_18_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_19_REG != "FALSE") && + (PHY_ENABLE_19_REG != "TRUE"))) begin + $display("Error: [Unisim %s-310] PHY_ENABLE_19 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_19_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_20_REG != "FALSE") && + (PHY_ENABLE_20_REG != "TRUE"))) begin + $display("Error: [Unisim %s-311] PHY_ENABLE_20 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_20_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_21_REG != "FALSE") && + (PHY_ENABLE_21_REG != "TRUE"))) begin + $display("Error: [Unisim %s-312] PHY_ENABLE_21 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_21_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_22_REG != "FALSE") && + (PHY_ENABLE_22_REG != "TRUE"))) begin + $display("Error: [Unisim %s-313] PHY_ENABLE_22 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_22_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_23_REG != "FALSE") && + (PHY_ENABLE_23_REG != "TRUE"))) begin + $display("Error: [Unisim %s-314] PHY_ENABLE_23 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_23_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_24_REG != "FALSE") && + (PHY_ENABLE_24_REG != "TRUE"))) begin + $display("Error: [Unisim %s-315] PHY_ENABLE_24 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_24_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_25_REG != "FALSE") && + (PHY_ENABLE_25_REG != "TRUE"))) begin + $display("Error: [Unisim %s-316] PHY_ENABLE_25 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_25_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_26_REG != "FALSE") && + (PHY_ENABLE_26_REG != "TRUE"))) begin + $display("Error: [Unisim %s-317] PHY_ENABLE_26 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_26_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_27_REG != "FALSE") && + (PHY_ENABLE_27_REG != "TRUE"))) begin + $display("Error: [Unisim %s-318] PHY_ENABLE_27 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_27_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_28_REG != "FALSE") && + (PHY_ENABLE_28_REG != "TRUE"))) begin + $display("Error: [Unisim %s-319] PHY_ENABLE_28 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_28_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_29_REG != "FALSE") && + (PHY_ENABLE_29_REG != "TRUE"))) begin + $display("Error: [Unisim %s-320] PHY_ENABLE_29 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_29_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_30_REG != "FALSE") && + (PHY_ENABLE_30_REG != "TRUE"))) begin + $display("Error: [Unisim %s-321] PHY_ENABLE_30 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_30_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_31_REG != "FALSE") && + (PHY_ENABLE_31_REG != "TRUE"))) begin + $display("Error: [Unisim %s-322] PHY_ENABLE_31 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_31_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_APB_00_REG != "FALSE") && + (PHY_ENABLE_APB_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-323] PHY_ENABLE_APB_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_APB_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_ENABLE_APB_01_REG != "FALSE") && + (PHY_ENABLE_APB_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-324] PHY_ENABLE_APB_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_APB_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_PCLK_INVERT_01_REG != "FALSE") && + (PHY_PCLK_INVERT_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-325] PHY_PCLK_INVERT_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PHY_PCLK_INVERT_02_REG != "FALSE") && + (PHY_PCLK_INVERT_02_REG != "TRUE"))) begin + $display("Error: [Unisim %s-326] PHY_PCLK_INVERT_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_00_REG < 0) || (READ_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-329] READ_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_01_REG < 0) || (READ_PERCENT_01_REG > 100))) begin + $display("Error: [Unisim %s-330] READ_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_02_REG < 0) || (READ_PERCENT_02_REG > 100))) begin + $display("Error: [Unisim %s-331] READ_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_03_REG < 0) || (READ_PERCENT_03_REG > 100))) begin + $display("Error: [Unisim %s-332] READ_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_04_REG < 0) || (READ_PERCENT_04_REG > 100))) begin + $display("Error: [Unisim %s-333] READ_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_05_REG < 0) || (READ_PERCENT_05_REG > 100))) begin + $display("Error: [Unisim %s-334] READ_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_06_REG < 0) || (READ_PERCENT_06_REG > 100))) begin + $display("Error: [Unisim %s-335] READ_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_07_REG < 0) || (READ_PERCENT_07_REG > 100))) begin + $display("Error: [Unisim %s-336] READ_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_08_REG < 0) || (READ_PERCENT_08_REG > 100))) begin + $display("Error: [Unisim %s-337] READ_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_09_REG < 0) || (READ_PERCENT_09_REG > 100))) begin + $display("Error: [Unisim %s-338] READ_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_10_REG < 0) || (READ_PERCENT_10_REG > 100))) begin + $display("Error: [Unisim %s-339] READ_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_11_REG < 0) || (READ_PERCENT_11_REG > 100))) begin + $display("Error: [Unisim %s-340] READ_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_12_REG < 0) || (READ_PERCENT_12_REG > 100))) begin + $display("Error: [Unisim %s-341] READ_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_13_REG < 0) || (READ_PERCENT_13_REG > 100))) begin + $display("Error: [Unisim %s-342] READ_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_14_REG < 0) || (READ_PERCENT_14_REG > 100))) begin + $display("Error: [Unisim %s-343] READ_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_15_REG < 0) || (READ_PERCENT_15_REG > 100))) begin + $display("Error: [Unisim %s-344] READ_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_16_REG < 0) || (READ_PERCENT_16_REG > 100))) begin + $display("Error: [Unisim %s-345] READ_PERCENT_16 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_16_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_17_REG < 0) || (READ_PERCENT_17_REG > 100))) begin + $display("Error: [Unisim %s-346] READ_PERCENT_17 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_17_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_18_REG < 0) || (READ_PERCENT_18_REG > 100))) begin + $display("Error: [Unisim %s-347] READ_PERCENT_18 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_18_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_19_REG < 0) || (READ_PERCENT_19_REG > 100))) begin + $display("Error: [Unisim %s-348] READ_PERCENT_19 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_19_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_20_REG < 0) || (READ_PERCENT_20_REG > 100))) begin + $display("Error: [Unisim %s-349] READ_PERCENT_20 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_20_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_21_REG < 0) || (READ_PERCENT_21_REG > 100))) begin + $display("Error: [Unisim %s-350] READ_PERCENT_21 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_21_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_22_REG < 0) || (READ_PERCENT_22_REG > 100))) begin + $display("Error: [Unisim %s-351] READ_PERCENT_22 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_22_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_23_REG < 0) || (READ_PERCENT_23_REG > 100))) begin + $display("Error: [Unisim %s-352] READ_PERCENT_23 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_23_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_24_REG < 0) || (READ_PERCENT_24_REG > 100))) begin + $display("Error: [Unisim %s-353] READ_PERCENT_24 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_24_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_25_REG < 0) || (READ_PERCENT_25_REG > 100))) begin + $display("Error: [Unisim %s-354] READ_PERCENT_25 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_25_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_26_REG < 0) || (READ_PERCENT_26_REG > 100))) begin + $display("Error: [Unisim %s-355] READ_PERCENT_26 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_26_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_27_REG < 0) || (READ_PERCENT_27_REG > 100))) begin + $display("Error: [Unisim %s-356] READ_PERCENT_27 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_27_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_28_REG < 0) || (READ_PERCENT_28_REG > 100))) begin + $display("Error: [Unisim %s-357] READ_PERCENT_28 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_28_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_29_REG < 0) || (READ_PERCENT_29_REG > 100))) begin + $display("Error: [Unisim %s-358] READ_PERCENT_29 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_29_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_30_REG < 0) || (READ_PERCENT_30_REG > 100))) begin + $display("Error: [Unisim %s-359] READ_PERCENT_30 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_30_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((READ_PERCENT_31_REG < 0) || (READ_PERCENT_31_REG > 100))) begin + $display("Error: [Unisim %s-360] READ_PERCENT_31 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_31_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-361] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SWITCH_ENABLE_00_REG != "FALSE") && + (SWITCH_ENABLE_00_REG != "TRUE"))) begin + $display("Error: [Unisim %s-363] SWITCH_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SWITCH_ENABLE_01_REG != "FALSE") && + (SWITCH_ENABLE_01_REG != "TRUE"))) begin + $display("Error: [Unisim %s-364] SWITCH_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_00_REG < 0) || (WRITE_PERCENT_00_REG > 100))) begin + $display("Error: [Unisim %s-368] WRITE_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_00_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_01_REG < 0) || (WRITE_PERCENT_01_REG > 100))) begin + $display("Error: [Unisim %s-369] WRITE_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_01_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_02_REG < 0) || (WRITE_PERCENT_02_REG > 100))) begin + $display("Error: [Unisim %s-370] WRITE_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_02_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_03_REG < 0) || (WRITE_PERCENT_03_REG > 100))) begin + $display("Error: [Unisim %s-371] WRITE_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_03_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_04_REG < 0) || (WRITE_PERCENT_04_REG > 100))) begin + $display("Error: [Unisim %s-372] WRITE_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_04_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_05_REG < 0) || (WRITE_PERCENT_05_REG > 100))) begin + $display("Error: [Unisim %s-373] WRITE_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_05_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_06_REG < 0) || (WRITE_PERCENT_06_REG > 100))) begin + $display("Error: [Unisim %s-374] WRITE_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_06_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_07_REG < 0) || (WRITE_PERCENT_07_REG > 100))) begin + $display("Error: [Unisim %s-375] WRITE_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_07_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_08_REG < 0) || (WRITE_PERCENT_08_REG > 100))) begin + $display("Error: [Unisim %s-376] WRITE_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_08_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_09_REG < 0) || (WRITE_PERCENT_09_REG > 100))) begin + $display("Error: [Unisim %s-377] WRITE_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_09_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_10_REG < 0) || (WRITE_PERCENT_10_REG > 100))) begin + $display("Error: [Unisim %s-378] WRITE_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_10_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_11_REG < 0) || (WRITE_PERCENT_11_REG > 100))) begin + $display("Error: [Unisim %s-379] WRITE_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_11_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_12_REG < 0) || (WRITE_PERCENT_12_REG > 100))) begin + $display("Error: [Unisim %s-380] WRITE_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_13_REG < 0) || (WRITE_PERCENT_13_REG > 100))) begin + $display("Error: [Unisim %s-381] WRITE_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_13_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_14_REG < 0) || (WRITE_PERCENT_14_REG > 100))) begin + $display("Error: [Unisim %s-382] WRITE_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_14_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_15_REG < 0) || (WRITE_PERCENT_15_REG > 100))) begin + $display("Error: [Unisim %s-383] WRITE_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_15_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_16_REG < 0) || (WRITE_PERCENT_16_REG > 100))) begin + $display("Error: [Unisim %s-384] WRITE_PERCENT_16 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_16_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_17_REG < 0) || (WRITE_PERCENT_17_REG > 100))) begin + $display("Error: [Unisim %s-385] WRITE_PERCENT_17 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_17_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_18_REG < 0) || (WRITE_PERCENT_18_REG > 100))) begin + $display("Error: [Unisim %s-386] WRITE_PERCENT_18 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_18_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_19_REG < 0) || (WRITE_PERCENT_19_REG > 100))) begin + $display("Error: [Unisim %s-387] WRITE_PERCENT_19 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_19_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_20_REG < 0) || (WRITE_PERCENT_20_REG > 100))) begin + $display("Error: [Unisim %s-388] WRITE_PERCENT_20 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_20_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_21_REG < 0) || (WRITE_PERCENT_21_REG > 100))) begin + $display("Error: [Unisim %s-389] WRITE_PERCENT_21 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_21_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_22_REG < 0) || (WRITE_PERCENT_22_REG > 100))) begin + $display("Error: [Unisim %s-390] WRITE_PERCENT_22 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_22_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_23_REG < 0) || (WRITE_PERCENT_23_REG > 100))) begin + $display("Error: [Unisim %s-391] WRITE_PERCENT_23 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_23_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_24_REG < 0) || (WRITE_PERCENT_24_REG > 100))) begin + $display("Error: [Unisim %s-392] WRITE_PERCENT_24 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_24_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_25_REG < 0) || (WRITE_PERCENT_25_REG > 100))) begin + $display("Error: [Unisim %s-393] WRITE_PERCENT_25 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_25_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_26_REG < 0) || (WRITE_PERCENT_26_REG > 100))) begin + $display("Error: [Unisim %s-394] WRITE_PERCENT_26 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_26_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_27_REG < 0) || (WRITE_PERCENT_27_REG > 100))) begin + $display("Error: [Unisim %s-395] WRITE_PERCENT_27 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_27_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_28_REG < 0) || (WRITE_PERCENT_28_REG > 100))) begin + $display("Error: [Unisim %s-396] WRITE_PERCENT_28 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_28_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_29_REG < 0) || (WRITE_PERCENT_29_REG > 100))) begin + $display("Error: [Unisim %s-397] WRITE_PERCENT_29 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_29_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_30_REG < 0) || (WRITE_PERCENT_30_REG > 100))) begin + $display("Error: [Unisim %s-398] WRITE_PERCENT_30 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_30_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((WRITE_PERCENT_31_REG < 0) || (WRITE_PERCENT_31_REG > 100))) begin + $display("Error: [Unisim %s-399] WRITE_PERCENT_31 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_31_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + + +assign ANALOG_HBM_SEL_00_in = 1'b1; // tie off +assign ANALOG_HBM_SEL_01_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_00_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_01_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_02_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_03_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_04_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_05_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_06_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_07_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_08_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_09_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_10_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_11_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_12_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_13_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_14_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_15_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_16_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_17_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_18_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_19_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_20_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_21_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_22_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_23_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_24_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_25_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_26_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_27_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_28_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_29_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_30_in = 1'b1; // tie off +assign BLI_SCAN_ENABLE_31_in = 1'b1; // tie off +assign BLI_SCAN_IN_00_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_01_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_02_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_03_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_04_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_05_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_06_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_07_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_08_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_09_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_10_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_11_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_12_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_13_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_14_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_15_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_16_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_17_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_18_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_19_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_20_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_21_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_22_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_23_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_24_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_25_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_26_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_27_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_28_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_29_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_30_in = 8'b11111111; // tie off +assign BLI_SCAN_IN_31_in = 8'b11111111; // tie off +assign DBG_IN_00_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_01_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_02_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_03_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_04_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_05_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_06_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_07_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_08_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_09_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_10_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_11_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_12_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_13_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_14_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_15_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_16_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_17_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_18_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_19_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_20_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_21_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_22_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_23_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_24_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_25_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_26_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_27_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_28_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_29_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_30_in = 24'b111111111111111111111111; // tie off +assign DBG_IN_31_in = 24'b111111111111111111111111; // tie off +assign DLL_SCAN_CK_00_in = 1'b1; // tie off +assign DLL_SCAN_CK_01_in = 1'b1; // tie off +assign DLL_SCAN_ENABLE_00_in = 1'b1; // tie off +assign DLL_SCAN_ENABLE_01_in = 1'b1; // tie off +assign DLL_SCAN_IN_00_in = 2'b11; // tie off +assign DLL_SCAN_IN_01_in = 2'b11; // tie off +assign DLL_SCAN_MODE_00_in = 1'b1; // tie off +assign DLL_SCAN_MODE_01_in = 1'b1; // tie off +assign DLL_SCAN_RST_N_00_in = 1'b1; // tie off +assign DLL_SCAN_RST_N_01_in = 1'b1; // tie off +assign IO_SCAN_CK_00_in = 1'b1; // tie off +assign IO_SCAN_CK_01_in = 1'b1; // tie off +assign IO_SCAN_ENABLE_00_in = 1'b1; // tie off +assign IO_SCAN_ENABLE_01_in = 1'b1; // tie off +assign IO_SCAN_IN_00_in = 2'b11; // tie off +assign IO_SCAN_IN_01_in = 2'b11; // tie off +assign IO_SCAN_MODE_00_in = 1'b1; // tie off +assign IO_SCAN_MODE_01_in = 1'b1; // tie off +assign IO_SCAN_RST_N_00_in = 1'b1; // tie off +assign IO_SCAN_RST_N_01_in = 1'b1; // tie off +assign MC_SCAN_CK_00_in = 1'b1; // tie off +assign MC_SCAN_CK_01_in = 1'b1; // tie off +assign MC_SCAN_CK_02_in = 1'b1; // tie off +assign MC_SCAN_CK_03_in = 1'b1; // tie off +assign MC_SCAN_CK_04_in = 1'b1; // tie off +assign MC_SCAN_CK_05_in = 1'b1; // tie off +assign MC_SCAN_CK_06_in = 1'b1; // tie off +assign MC_SCAN_CK_07_in = 1'b1; // tie off +assign MC_SCAN_CK_08_in = 1'b1; // tie off +assign MC_SCAN_CK_09_in = 1'b1; // tie off +assign MC_SCAN_CK_10_in = 1'b1; // tie off +assign MC_SCAN_CK_11_in = 1'b1; // tie off +assign MC_SCAN_CK_12_in = 1'b1; // tie off +assign MC_SCAN_CK_13_in = 1'b1; // tie off +assign MC_SCAN_CK_14_in = 1'b1; // tie off +assign MC_SCAN_CK_15_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_00_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_01_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_02_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_03_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_04_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_05_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_06_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_07_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_08_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_09_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_10_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_11_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_12_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_13_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_14_in = 1'b1; // tie off +assign MC_SCAN_ENABLE_15_in = 1'b1; // tie off +assign MC_SCAN_IN_00_in = 2'b11; // tie off +assign MC_SCAN_IN_01_in = 2'b11; // tie off +assign MC_SCAN_IN_02_in = 2'b11; // tie off +assign MC_SCAN_IN_03_in = 2'b11; // tie off +assign MC_SCAN_IN_04_in = 2'b11; // tie off +assign MC_SCAN_IN_05_in = 2'b11; // tie off +assign MC_SCAN_IN_06_in = 2'b11; // tie off +assign MC_SCAN_IN_07_in = 2'b11; // tie off +assign MC_SCAN_IN_08_in = 2'b11; // tie off +assign MC_SCAN_IN_09_in = 2'b11; // tie off +assign MC_SCAN_IN_10_in = 2'b11; // tie off +assign MC_SCAN_IN_11_in = 2'b11; // tie off +assign MC_SCAN_IN_12_in = 2'b11; // tie off +assign MC_SCAN_IN_13_in = 2'b11; // tie off +assign MC_SCAN_IN_14_in = 2'b11; // tie off +assign MC_SCAN_IN_15_in = 2'b11; // tie off +assign MC_SCAN_MODE_00_in = 1'b1; // tie off +assign MC_SCAN_MODE_01_in = 1'b1; // tie off +assign MC_SCAN_MODE_02_in = 1'b1; // tie off +assign MC_SCAN_MODE_03_in = 1'b1; // tie off +assign MC_SCAN_MODE_04_in = 1'b1; // tie off +assign MC_SCAN_MODE_05_in = 1'b1; // tie off +assign MC_SCAN_MODE_06_in = 1'b1; // tie off +assign MC_SCAN_MODE_07_in = 1'b1; // tie off +assign MC_SCAN_MODE_08_in = 1'b1; // tie off +assign MC_SCAN_MODE_09_in = 1'b1; // tie off +assign MC_SCAN_MODE_10_in = 1'b1; // tie off +assign MC_SCAN_MODE_11_in = 1'b1; // tie off +assign MC_SCAN_MODE_12_in = 1'b1; // tie off +assign MC_SCAN_MODE_13_in = 1'b1; // tie off +assign MC_SCAN_MODE_14_in = 1'b1; // tie off +assign MC_SCAN_MODE_15_in = 1'b1; // tie off +assign MC_SCAN_RST_N_00_in = 1'b1; // tie off +assign MC_SCAN_RST_N_01_in = 1'b1; // tie off +assign MC_SCAN_RST_N_02_in = 1'b1; // tie off +assign MC_SCAN_RST_N_03_in = 1'b1; // tie off +assign MC_SCAN_RST_N_04_in = 1'b1; // tie off +assign MC_SCAN_RST_N_05_in = 1'b1; // tie off +assign MC_SCAN_RST_N_06_in = 1'b1; // tie off +assign MC_SCAN_RST_N_07_in = 1'b1; // tie off +assign MC_SCAN_RST_N_08_in = 1'b1; // tie off +assign MC_SCAN_RST_N_09_in = 1'b1; // tie off +assign MC_SCAN_RST_N_10_in = 1'b1; // tie off +assign MC_SCAN_RST_N_11_in = 1'b1; // tie off +assign MC_SCAN_RST_N_12_in = 1'b1; // tie off +assign MC_SCAN_RST_N_13_in = 1'b1; // tie off +assign MC_SCAN_RST_N_14_in = 1'b1; // tie off +assign MC_SCAN_RST_N_15_in = 1'b1; // tie off +assign PHY_SCAN_CK_00_in = 1'b1; // tie off +assign PHY_SCAN_CK_01_in = 1'b1; // tie off +assign PHY_SCAN_ENABLE_00_in = 1'b1; // tie off +assign PHY_SCAN_ENABLE_01_in = 1'b1; // tie off +assign PHY_SCAN_IN_00_in = 2'b11; // tie off +assign PHY_SCAN_IN_01_in = 2'b11; // tie off +assign PHY_SCAN_MODE_00_in = 1'b1; // tie off +assign PHY_SCAN_MODE_01_in = 1'b1; // tie off +assign PHY_SCAN_RST_N_00_in = 1'b1; // tie off +assign PHY_SCAN_RST_N_01_in = 1'b1; // tie off +assign SW_SCAN_CK_00_in = 1'b1; // tie off +assign SW_SCAN_CK_01_in = 1'b1; // tie off +assign SW_SCAN_ENABLE_00_in = 1'b1; // tie off +assign SW_SCAN_ENABLE_01_in = 1'b1; // tie off +assign SW_SCAN_IN_00_in = 2'b11; // tie off +assign SW_SCAN_IN_01_in = 2'b11; // tie off +assign SW_SCAN_IN_02_in = 2'b11; // tie off +assign SW_SCAN_IN_03_in = 2'b11; // tie off +assign SW_SCAN_IN_04_in = 2'b11; // tie off +assign SW_SCAN_IN_05_in = 2'b11; // tie off +assign SW_SCAN_IN_06_in = 2'b11; // tie off +assign SW_SCAN_IN_07_in = 2'b11; // tie off +assign SW_SCAN_MODE_00_in = 1'b1; // tie off +assign SW_SCAN_MODE_01_in = 1'b1; // tie off +assign SW_SCAN_RST_N_00_in = 1'b1; // tie off +assign SW_SCAN_RST_N_01_in = 1'b1; // tie off + +SIP_HBM_TWO_STACK_INTF SIP_HBM_TWO_STACK_INTF_INST ( + .ANALOG_MUX_SEL_0 (ANALOG_MUX_SEL_0_REG), + .ANALOG_MUX_SEL_1 (ANALOG_MUX_SEL_1_REG), + .APB_BYPASS_EN_0 (APB_BYPASS_EN_0_REG), + .APB_BYPASS_EN_1 (APB_BYPASS_EN_1_REG), + .AXI_BYPASS_EN_0 (AXI_BYPASS_EN_0_REG), + .AXI_BYPASS_EN_1 (AXI_BYPASS_EN_1_REG), + .BLI_TESTMODE_SEL_0 (BLI_TESTMODE_SEL_0_REG), + .BLI_TESTMODE_SEL_1 (BLI_TESTMODE_SEL_1_REG), + .CLK_SEL_00 (CLK_SEL_00_REG), + .CLK_SEL_01 (CLK_SEL_01_REG), + .CLK_SEL_02 (CLK_SEL_02_REG), + .CLK_SEL_03 (CLK_SEL_03_REG), + .CLK_SEL_04 (CLK_SEL_04_REG), + .CLK_SEL_05 (CLK_SEL_05_REG), + .CLK_SEL_06 (CLK_SEL_06_REG), + .CLK_SEL_07 (CLK_SEL_07_REG), + .CLK_SEL_08 (CLK_SEL_08_REG), + .CLK_SEL_09 (CLK_SEL_09_REG), + .CLK_SEL_10 (CLK_SEL_10_REG), + .CLK_SEL_11 (CLK_SEL_11_REG), + .CLK_SEL_12 (CLK_SEL_12_REG), + .CLK_SEL_13 (CLK_SEL_13_REG), + .CLK_SEL_14 (CLK_SEL_14_REG), + .CLK_SEL_15 (CLK_SEL_15_REG), + .CLK_SEL_16 (CLK_SEL_16_REG), + .CLK_SEL_17 (CLK_SEL_17_REG), + .CLK_SEL_18 (CLK_SEL_18_REG), + .CLK_SEL_19 (CLK_SEL_19_REG), + .CLK_SEL_20 (CLK_SEL_20_REG), + .CLK_SEL_21 (CLK_SEL_21_REG), + .CLK_SEL_22 (CLK_SEL_22_REG), + .CLK_SEL_23 (CLK_SEL_23_REG), + .CLK_SEL_24 (CLK_SEL_24_REG), + .CLK_SEL_25 (CLK_SEL_25_REG), + .CLK_SEL_26 (CLK_SEL_26_REG), + .CLK_SEL_27 (CLK_SEL_27_REG), + .CLK_SEL_28 (CLK_SEL_28_REG), + .CLK_SEL_29 (CLK_SEL_29_REG), + .CLK_SEL_30 (CLK_SEL_30_REG), + .CLK_SEL_31 (CLK_SEL_31_REG), + .DATARATE_00 (DATARATE_00_REG), + .DATARATE_01 (DATARATE_01_REG), + .DATARATE_02 (DATARATE_02_REG), + .DATARATE_03 (DATARATE_03_REG), + .DATARATE_04 (DATARATE_04_REG), + .DATARATE_05 (DATARATE_05_REG), + .DATARATE_06 (DATARATE_06_REG), + .DATARATE_07 (DATARATE_07_REG), + .DATARATE_08 (DATARATE_08_REG), + .DATARATE_09 (DATARATE_09_REG), + .DATARATE_10 (DATARATE_10_REG), + .DATARATE_11 (DATARATE_11_REG), + .DATARATE_12 (DATARATE_12_REG), + .DATARATE_13 (DATARATE_13_REG), + .DATARATE_14 (DATARATE_14_REG), + .DATARATE_15 (DATARATE_15_REG), + .DA_LOCKOUT_0 (DA_LOCKOUT_0_REG), + .DA_LOCKOUT_1 (DA_LOCKOUT_1_REG), + .DBG_BYPASS_VAL_0 (DBG_BYPASS_VAL_0_REG), + .DBG_BYPASS_VAL_1 (DBG_BYPASS_VAL_1_REG), + .DEBUG_MODE_0 (DEBUG_MODE_0_REG), + .DEBUG_MODE_1 (DEBUG_MODE_1_REG), + .DFI_BYPASS_VAL_0 (DFI_BYPASS_VAL_0_REG), + .DFI_BYPASS_VAL_1 (DFI_BYPASS_VAL_1_REG), + .DLL_TESTMODE_SEL_0 (DLL_TESTMODE_SEL_0_REG), + .DLL_TESTMODE_SEL_1 (DLL_TESTMODE_SEL_1_REG), + .IO_TESTMODE_SEL_0 (IO_TESTMODE_SEL_0_REG), + .IO_TESTMODE_SEL_1 (IO_TESTMODE_SEL_1_REG), + .IS_APB_0_PCLK_INVERTED (IS_APB_0_PCLK_INVERTED_REG), + .IS_APB_0_PRESET_N_INVERTED (IS_APB_0_PRESET_N_INVERTED_REG), + .IS_APB_1_PCLK_INVERTED (IS_APB_1_PCLK_INVERTED_REG), + .IS_APB_1_PRESET_N_INVERTED (IS_APB_1_PRESET_N_INVERTED_REG), + .IS_AXI_00_ACLK_INVERTED (IS_AXI_00_ACLK_INVERTED_REG), + .IS_AXI_00_ARESET_N_INVERTED (IS_AXI_00_ARESET_N_INVERTED_REG), + .IS_AXI_01_ACLK_INVERTED (IS_AXI_01_ACLK_INVERTED_REG), + .IS_AXI_01_ARESET_N_INVERTED (IS_AXI_01_ARESET_N_INVERTED_REG), + .IS_AXI_02_ACLK_INVERTED (IS_AXI_02_ACLK_INVERTED_REG), + .IS_AXI_02_ARESET_N_INVERTED (IS_AXI_02_ARESET_N_INVERTED_REG), + .IS_AXI_03_ACLK_INVERTED (IS_AXI_03_ACLK_INVERTED_REG), + .IS_AXI_03_ARESET_N_INVERTED (IS_AXI_03_ARESET_N_INVERTED_REG), + .IS_AXI_04_ACLK_INVERTED (IS_AXI_04_ACLK_INVERTED_REG), + .IS_AXI_04_ARESET_N_INVERTED (IS_AXI_04_ARESET_N_INVERTED_REG), + .IS_AXI_05_ACLK_INVERTED (IS_AXI_05_ACLK_INVERTED_REG), + .IS_AXI_05_ARESET_N_INVERTED (IS_AXI_05_ARESET_N_INVERTED_REG), + .IS_AXI_06_ACLK_INVERTED (IS_AXI_06_ACLK_INVERTED_REG), + .IS_AXI_06_ARESET_N_INVERTED (IS_AXI_06_ARESET_N_INVERTED_REG), + .IS_AXI_07_ACLK_INVERTED (IS_AXI_07_ACLK_INVERTED_REG), + .IS_AXI_07_ARESET_N_INVERTED (IS_AXI_07_ARESET_N_INVERTED_REG), + .IS_AXI_08_ACLK_INVERTED (IS_AXI_08_ACLK_INVERTED_REG), + .IS_AXI_08_ARESET_N_INVERTED (IS_AXI_08_ARESET_N_INVERTED_REG), + .IS_AXI_09_ACLK_INVERTED (IS_AXI_09_ACLK_INVERTED_REG), + .IS_AXI_09_ARESET_N_INVERTED (IS_AXI_09_ARESET_N_INVERTED_REG), + .IS_AXI_10_ACLK_INVERTED (IS_AXI_10_ACLK_INVERTED_REG), + .IS_AXI_10_ARESET_N_INVERTED (IS_AXI_10_ARESET_N_INVERTED_REG), + .IS_AXI_11_ACLK_INVERTED (IS_AXI_11_ACLK_INVERTED_REG), + .IS_AXI_11_ARESET_N_INVERTED (IS_AXI_11_ARESET_N_INVERTED_REG), + .IS_AXI_12_ACLK_INVERTED (IS_AXI_12_ACLK_INVERTED_REG), + .IS_AXI_12_ARESET_N_INVERTED (IS_AXI_12_ARESET_N_INVERTED_REG), + .IS_AXI_13_ACLK_INVERTED (IS_AXI_13_ACLK_INVERTED_REG), + .IS_AXI_13_ARESET_N_INVERTED (IS_AXI_13_ARESET_N_INVERTED_REG), + .IS_AXI_14_ACLK_INVERTED (IS_AXI_14_ACLK_INVERTED_REG), + .IS_AXI_14_ARESET_N_INVERTED (IS_AXI_14_ARESET_N_INVERTED_REG), + .IS_AXI_15_ACLK_INVERTED (IS_AXI_15_ACLK_INVERTED_REG), + .IS_AXI_15_ARESET_N_INVERTED (IS_AXI_15_ARESET_N_INVERTED_REG), + .IS_AXI_16_ACLK_INVERTED (IS_AXI_16_ACLK_INVERTED_REG), + .IS_AXI_16_ARESET_N_INVERTED (IS_AXI_16_ARESET_N_INVERTED_REG), + .IS_AXI_17_ACLK_INVERTED (IS_AXI_17_ACLK_INVERTED_REG), + .IS_AXI_17_ARESET_N_INVERTED (IS_AXI_17_ARESET_N_INVERTED_REG), + .IS_AXI_18_ACLK_INVERTED (IS_AXI_18_ACLK_INVERTED_REG), + .IS_AXI_18_ARESET_N_INVERTED (IS_AXI_18_ARESET_N_INVERTED_REG), + .IS_AXI_19_ACLK_INVERTED (IS_AXI_19_ACLK_INVERTED_REG), + .IS_AXI_19_ARESET_N_INVERTED (IS_AXI_19_ARESET_N_INVERTED_REG), + .IS_AXI_20_ACLK_INVERTED (IS_AXI_20_ACLK_INVERTED_REG), + .IS_AXI_20_ARESET_N_INVERTED (IS_AXI_20_ARESET_N_INVERTED_REG), + .IS_AXI_21_ACLK_INVERTED (IS_AXI_21_ACLK_INVERTED_REG), + .IS_AXI_21_ARESET_N_INVERTED (IS_AXI_21_ARESET_N_INVERTED_REG), + .IS_AXI_22_ACLK_INVERTED (IS_AXI_22_ACLK_INVERTED_REG), + .IS_AXI_22_ARESET_N_INVERTED (IS_AXI_22_ARESET_N_INVERTED_REG), + .IS_AXI_23_ACLK_INVERTED (IS_AXI_23_ACLK_INVERTED_REG), + .IS_AXI_23_ARESET_N_INVERTED (IS_AXI_23_ARESET_N_INVERTED_REG), + .IS_AXI_24_ACLK_INVERTED (IS_AXI_24_ACLK_INVERTED_REG), + .IS_AXI_24_ARESET_N_INVERTED (IS_AXI_24_ARESET_N_INVERTED_REG), + .IS_AXI_25_ACLK_INVERTED (IS_AXI_25_ACLK_INVERTED_REG), + .IS_AXI_25_ARESET_N_INVERTED (IS_AXI_25_ARESET_N_INVERTED_REG), + .IS_AXI_26_ACLK_INVERTED (IS_AXI_26_ACLK_INVERTED_REG), + .IS_AXI_26_ARESET_N_INVERTED (IS_AXI_26_ARESET_N_INVERTED_REG), + .IS_AXI_27_ACLK_INVERTED (IS_AXI_27_ACLK_INVERTED_REG), + .IS_AXI_27_ARESET_N_INVERTED (IS_AXI_27_ARESET_N_INVERTED_REG), + .IS_AXI_28_ACLK_INVERTED (IS_AXI_28_ACLK_INVERTED_REG), + .IS_AXI_28_ARESET_N_INVERTED (IS_AXI_28_ARESET_N_INVERTED_REG), + .IS_AXI_29_ACLK_INVERTED (IS_AXI_29_ACLK_INVERTED_REG), + .IS_AXI_29_ARESET_N_INVERTED (IS_AXI_29_ARESET_N_INVERTED_REG), + .IS_AXI_30_ACLK_INVERTED (IS_AXI_30_ACLK_INVERTED_REG), + .IS_AXI_30_ARESET_N_INVERTED (IS_AXI_30_ARESET_N_INVERTED_REG), + .IS_AXI_31_ACLK_INVERTED (IS_AXI_31_ACLK_INVERTED_REG), + .IS_AXI_31_ARESET_N_INVERTED (IS_AXI_31_ARESET_N_INVERTED_REG), + .MC_CSSD_SEL_0 (MC_CSSD_SEL_0_REG), + .MC_CSSD_SEL_1 (MC_CSSD_SEL_1_REG), + .MC_CSSD_SEL_10 (MC_CSSD_SEL_10_REG), + .MC_CSSD_SEL_11 (MC_CSSD_SEL_11_REG), + .MC_CSSD_SEL_12 (MC_CSSD_SEL_12_REG), + .MC_CSSD_SEL_13 (MC_CSSD_SEL_13_REG), + .MC_CSSD_SEL_14 (MC_CSSD_SEL_14_REG), + .MC_CSSD_SEL_15 (MC_CSSD_SEL_15_REG), + .MC_CSSD_SEL_2 (MC_CSSD_SEL_2_REG), + .MC_CSSD_SEL_3 (MC_CSSD_SEL_3_REG), + .MC_CSSD_SEL_4 (MC_CSSD_SEL_4_REG), + .MC_CSSD_SEL_5 (MC_CSSD_SEL_5_REG), + .MC_CSSD_SEL_6 (MC_CSSD_SEL_6_REG), + .MC_CSSD_SEL_7 (MC_CSSD_SEL_7_REG), + .MC_CSSD_SEL_8 (MC_CSSD_SEL_8_REG), + .MC_CSSD_SEL_9 (MC_CSSD_SEL_9_REG), + .MC_ENABLE_00 (MC_ENABLE_00_REG), + .MC_ENABLE_01 (MC_ENABLE_01_REG), + .MC_ENABLE_02 (MC_ENABLE_02_REG), + .MC_ENABLE_03 (MC_ENABLE_03_REG), + .MC_ENABLE_04 (MC_ENABLE_04_REG), + .MC_ENABLE_05 (MC_ENABLE_05_REG), + .MC_ENABLE_06 (MC_ENABLE_06_REG), + .MC_ENABLE_07 (MC_ENABLE_07_REG), + .MC_ENABLE_08 (MC_ENABLE_08_REG), + .MC_ENABLE_09 (MC_ENABLE_09_REG), + .MC_ENABLE_10 (MC_ENABLE_10_REG), + .MC_ENABLE_11 (MC_ENABLE_11_REG), + .MC_ENABLE_12 (MC_ENABLE_12_REG), + .MC_ENABLE_13 (MC_ENABLE_13_REG), + .MC_ENABLE_14 (MC_ENABLE_14_REG), + .MC_ENABLE_15 (MC_ENABLE_15_REG), + .MC_ENABLE_APB_00 (MC_ENABLE_APB_00_REG), + .MC_ENABLE_APB_01 (MC_ENABLE_APB_01_REG), + .MC_TESTMODE_SEL_0 (MC_TESTMODE_SEL_0_REG), + .MC_TESTMODE_SEL_1 (MC_TESTMODE_SEL_1_REG), + .MC_TESTMODE_SEL_10 (MC_TESTMODE_SEL_10_REG), + .MC_TESTMODE_SEL_11 (MC_TESTMODE_SEL_11_REG), + .MC_TESTMODE_SEL_12 (MC_TESTMODE_SEL_12_REG), + .MC_TESTMODE_SEL_13 (MC_TESTMODE_SEL_13_REG), + .MC_TESTMODE_SEL_14 (MC_TESTMODE_SEL_14_REG), + .MC_TESTMODE_SEL_15 (MC_TESTMODE_SEL_15_REG), + .MC_TESTMODE_SEL_2 (MC_TESTMODE_SEL_2_REG), + .MC_TESTMODE_SEL_3 (MC_TESTMODE_SEL_3_REG), + .MC_TESTMODE_SEL_4 (MC_TESTMODE_SEL_4_REG), + .MC_TESTMODE_SEL_5 (MC_TESTMODE_SEL_5_REG), + .MC_TESTMODE_SEL_6 (MC_TESTMODE_SEL_6_REG), + .MC_TESTMODE_SEL_7 (MC_TESTMODE_SEL_7_REG), + .MC_TESTMODE_SEL_8 (MC_TESTMODE_SEL_8_REG), + .MC_TESTMODE_SEL_9 (MC_TESTMODE_SEL_9_REG), + .PAGEHIT_PERCENT_00 (PAGEHIT_PERCENT_00_REG), + .PAGEHIT_PERCENT_01 (PAGEHIT_PERCENT_01_REG), + .PHY_CSSD_SEL_0 (PHY_CSSD_SEL_0_REG), + .PHY_CSSD_SEL_1 (PHY_CSSD_SEL_1_REG), + .PHY_ENABLE_00 (PHY_ENABLE_00_REG), + .PHY_ENABLE_01 (PHY_ENABLE_01_REG), + .PHY_ENABLE_02 (PHY_ENABLE_02_REG), + .PHY_ENABLE_03 (PHY_ENABLE_03_REG), + .PHY_ENABLE_04 (PHY_ENABLE_04_REG), + .PHY_ENABLE_05 (PHY_ENABLE_05_REG), + .PHY_ENABLE_06 (PHY_ENABLE_06_REG), + .PHY_ENABLE_07 (PHY_ENABLE_07_REG), + .PHY_ENABLE_08 (PHY_ENABLE_08_REG), + .PHY_ENABLE_09 (PHY_ENABLE_09_REG), + .PHY_ENABLE_10 (PHY_ENABLE_10_REG), + .PHY_ENABLE_11 (PHY_ENABLE_11_REG), + .PHY_ENABLE_12 (PHY_ENABLE_12_REG), + .PHY_ENABLE_13 (PHY_ENABLE_13_REG), + .PHY_ENABLE_14 (PHY_ENABLE_14_REG), + .PHY_ENABLE_15 (PHY_ENABLE_15_REG), + .PHY_ENABLE_16 (PHY_ENABLE_16_REG), + .PHY_ENABLE_17 (PHY_ENABLE_17_REG), + .PHY_ENABLE_18 (PHY_ENABLE_18_REG), + .PHY_ENABLE_19 (PHY_ENABLE_19_REG), + .PHY_ENABLE_20 (PHY_ENABLE_20_REG), + .PHY_ENABLE_21 (PHY_ENABLE_21_REG), + .PHY_ENABLE_22 (PHY_ENABLE_22_REG), + .PHY_ENABLE_23 (PHY_ENABLE_23_REG), + .PHY_ENABLE_24 (PHY_ENABLE_24_REG), + .PHY_ENABLE_25 (PHY_ENABLE_25_REG), + .PHY_ENABLE_26 (PHY_ENABLE_26_REG), + .PHY_ENABLE_27 (PHY_ENABLE_27_REG), + .PHY_ENABLE_28 (PHY_ENABLE_28_REG), + .PHY_ENABLE_29 (PHY_ENABLE_29_REG), + .PHY_ENABLE_30 (PHY_ENABLE_30_REG), + .PHY_ENABLE_31 (PHY_ENABLE_31_REG), + .PHY_ENABLE_APB_00 (PHY_ENABLE_APB_00_REG), + .PHY_ENABLE_APB_01 (PHY_ENABLE_APB_01_REG), + .PHY_PCLK_INVERT_01 (PHY_PCLK_INVERT_01_REG), + .PHY_PCLK_INVERT_02 (PHY_PCLK_INVERT_02_REG), + .PHY_TESTMODE_SEL_0 (PHY_TESTMODE_SEL_0_REG), + .PHY_TESTMODE_SEL_1 (PHY_TESTMODE_SEL_1_REG), + .READ_PERCENT_00 (READ_PERCENT_00_REG), + .READ_PERCENT_01 (READ_PERCENT_01_REG), + .READ_PERCENT_02 (READ_PERCENT_02_REG), + .READ_PERCENT_03 (READ_PERCENT_03_REG), + .READ_PERCENT_04 (READ_PERCENT_04_REG), + .READ_PERCENT_05 (READ_PERCENT_05_REG), + .READ_PERCENT_06 (READ_PERCENT_06_REG), + .READ_PERCENT_07 (READ_PERCENT_07_REG), + .READ_PERCENT_08 (READ_PERCENT_08_REG), + .READ_PERCENT_09 (READ_PERCENT_09_REG), + .READ_PERCENT_10 (READ_PERCENT_10_REG), + .READ_PERCENT_11 (READ_PERCENT_11_REG), + .READ_PERCENT_12 (READ_PERCENT_12_REG), + .READ_PERCENT_13 (READ_PERCENT_13_REG), + .READ_PERCENT_14 (READ_PERCENT_14_REG), + .READ_PERCENT_15 (READ_PERCENT_15_REG), + .READ_PERCENT_16 (READ_PERCENT_16_REG), + .READ_PERCENT_17 (READ_PERCENT_17_REG), + .READ_PERCENT_18 (READ_PERCENT_18_REG), + .READ_PERCENT_19 (READ_PERCENT_19_REG), + .READ_PERCENT_20 (READ_PERCENT_20_REG), + .READ_PERCENT_21 (READ_PERCENT_21_REG), + .READ_PERCENT_22 (READ_PERCENT_22_REG), + .READ_PERCENT_23 (READ_PERCENT_23_REG), + .READ_PERCENT_24 (READ_PERCENT_24_REG), + .READ_PERCENT_25 (READ_PERCENT_25_REG), + .READ_PERCENT_26 (READ_PERCENT_26_REG), + .READ_PERCENT_27 (READ_PERCENT_27_REG), + .READ_PERCENT_28 (READ_PERCENT_28_REG), + .READ_PERCENT_29 (READ_PERCENT_29_REG), + .READ_PERCENT_30 (READ_PERCENT_30_REG), + .READ_PERCENT_31 (READ_PERCENT_31_REG), + .SWITCH_ENABLE_0 (SWITCH_ENABLE_0_REG), + .SWITCH_ENABLE_00 (SWITCH_ENABLE_00_REG), + .SWITCH_ENABLE_01 (SWITCH_ENABLE_01_REG), + .SWITCH_ENABLE_1 (SWITCH_ENABLE_1_REG), + .SW_TESTMODE_SEL_0 (SW_TESTMODE_SEL_0_REG), + .SW_TESTMODE_SEL_1 (SW_TESTMODE_SEL_1_REG), + .WRITE_PERCENT_00 (WRITE_PERCENT_00_REG), + .WRITE_PERCENT_01 (WRITE_PERCENT_01_REG), + .WRITE_PERCENT_02 (WRITE_PERCENT_02_REG), + .WRITE_PERCENT_03 (WRITE_PERCENT_03_REG), + .WRITE_PERCENT_04 (WRITE_PERCENT_04_REG), + .WRITE_PERCENT_05 (WRITE_PERCENT_05_REG), + .WRITE_PERCENT_06 (WRITE_PERCENT_06_REG), + .WRITE_PERCENT_07 (WRITE_PERCENT_07_REG), + .WRITE_PERCENT_08 (WRITE_PERCENT_08_REG), + .WRITE_PERCENT_09 (WRITE_PERCENT_09_REG), + .WRITE_PERCENT_10 (WRITE_PERCENT_10_REG), + .WRITE_PERCENT_11 (WRITE_PERCENT_11_REG), + .WRITE_PERCENT_12 (WRITE_PERCENT_12_REG), + .WRITE_PERCENT_13 (WRITE_PERCENT_13_REG), + .WRITE_PERCENT_14 (WRITE_PERCENT_14_REG), + .WRITE_PERCENT_15 (WRITE_PERCENT_15_REG), + .WRITE_PERCENT_16 (WRITE_PERCENT_16_REG), + .WRITE_PERCENT_17 (WRITE_PERCENT_17_REG), + .WRITE_PERCENT_18 (WRITE_PERCENT_18_REG), + .WRITE_PERCENT_19 (WRITE_PERCENT_19_REG), + .WRITE_PERCENT_20 (WRITE_PERCENT_20_REG), + .WRITE_PERCENT_21 (WRITE_PERCENT_21_REG), + .WRITE_PERCENT_22 (WRITE_PERCENT_22_REG), + .WRITE_PERCENT_23 (WRITE_PERCENT_23_REG), + .WRITE_PERCENT_24 (WRITE_PERCENT_24_REG), + .WRITE_PERCENT_25 (WRITE_PERCENT_25_REG), + .WRITE_PERCENT_26 (WRITE_PERCENT_26_REG), + .WRITE_PERCENT_27 (WRITE_PERCENT_27_REG), + .WRITE_PERCENT_28 (WRITE_PERCENT_28_REG), + .WRITE_PERCENT_29 (WRITE_PERCENT_29_REG), + .WRITE_PERCENT_30 (WRITE_PERCENT_30_REG), + .WRITE_PERCENT_31 (WRITE_PERCENT_31_REG), + .APB_0_PRDATA (APB_0_PRDATA_out), + .APB_0_PREADY (APB_0_PREADY_out), + .APB_0_PSLVERR (APB_0_PSLVERR_out), + .APB_1_PRDATA (APB_1_PRDATA_out), + .APB_1_PREADY (APB_1_PREADY_out), + .APB_1_PSLVERR (APB_1_PSLVERR_out), + .AXI_00_ARREADY (AXI_00_ARREADY_out), + .AXI_00_AWREADY (AXI_00_AWREADY_out), + .AXI_00_BID (AXI_00_BID_out), + .AXI_00_BRESP (AXI_00_BRESP_out), + .AXI_00_BVALID (AXI_00_BVALID_out), + .AXI_00_DFI_AW_AERR_N (AXI_00_DFI_AW_AERR_N_out), + .AXI_00_DFI_CLK_BUF (AXI_00_DFI_CLK_BUF_out), + .AXI_00_DFI_DBI_BYTE_DISABLE (AXI_00_DFI_DBI_BYTE_DISABLE_out), + .AXI_00_DFI_DW_RDDATA_DBI (AXI_00_DFI_DW_RDDATA_DBI_out), + .AXI_00_DFI_DW_RDDATA_DERR (AXI_00_DFI_DW_RDDATA_DERR_out), + .AXI_00_DFI_DW_RDDATA_VALID (AXI_00_DFI_DW_RDDATA_VALID_out), + .AXI_00_DFI_INIT_COMPLETE (AXI_00_DFI_INIT_COMPLETE_out), + .AXI_00_DFI_PHYUPD_REQ (AXI_00_DFI_PHYUPD_REQ_out), + .AXI_00_DFI_PHY_LP_STATE (AXI_00_DFI_PHY_LP_STATE_out), + .AXI_00_DFI_RST_N_BUF (AXI_00_DFI_RST_N_BUF_out), + .AXI_00_MC_STATUS (AXI_00_MC_STATUS_out), + .AXI_00_PHY_STATUS (AXI_00_PHY_STATUS_out), + .AXI_00_RDATA (AXI_00_RDATA_out), + .AXI_00_RDATA_PARITY (AXI_00_RDATA_PARITY_out), + .AXI_00_RID (AXI_00_RID_out), + .AXI_00_RLAST (AXI_00_RLAST_out), + .AXI_00_RRESP (AXI_00_RRESP_out), + .AXI_00_RVALID (AXI_00_RVALID_out), + .AXI_00_WREADY (AXI_00_WREADY_out), + .AXI_01_ARREADY (AXI_01_ARREADY_out), + .AXI_01_AWREADY (AXI_01_AWREADY_out), + .AXI_01_BID (AXI_01_BID_out), + .AXI_01_BRESP (AXI_01_BRESP_out), + .AXI_01_BVALID (AXI_01_BVALID_out), + .AXI_01_DFI_AW_AERR_N (AXI_01_DFI_AW_AERR_N_out), + .AXI_01_DFI_CLK_BUF (AXI_01_DFI_CLK_BUF_out), + .AXI_01_DFI_DBI_BYTE_DISABLE (AXI_01_DFI_DBI_BYTE_DISABLE_out), + .AXI_01_DFI_DW_RDDATA_DBI (AXI_01_DFI_DW_RDDATA_DBI_out), + .AXI_01_DFI_DW_RDDATA_DERR (AXI_01_DFI_DW_RDDATA_DERR_out), + .AXI_01_DFI_DW_RDDATA_VALID (AXI_01_DFI_DW_RDDATA_VALID_out), + .AXI_01_DFI_INIT_COMPLETE (AXI_01_DFI_INIT_COMPLETE_out), + .AXI_01_DFI_PHYUPD_REQ (AXI_01_DFI_PHYUPD_REQ_out), + .AXI_01_DFI_PHY_LP_STATE (AXI_01_DFI_PHY_LP_STATE_out), + .AXI_01_DFI_RST_N_BUF (AXI_01_DFI_RST_N_BUF_out), + .AXI_01_RDATA (AXI_01_RDATA_out), + .AXI_01_RDATA_PARITY (AXI_01_RDATA_PARITY_out), + .AXI_01_RID (AXI_01_RID_out), + .AXI_01_RLAST (AXI_01_RLAST_out), + .AXI_01_RRESP (AXI_01_RRESP_out), + .AXI_01_RVALID (AXI_01_RVALID_out), + .AXI_01_WREADY (AXI_01_WREADY_out), + .AXI_02_ARREADY (AXI_02_ARREADY_out), + .AXI_02_AWREADY (AXI_02_AWREADY_out), + .AXI_02_BID (AXI_02_BID_out), + .AXI_02_BRESP (AXI_02_BRESP_out), + .AXI_02_BVALID (AXI_02_BVALID_out), + .AXI_02_DFI_AW_AERR_N (AXI_02_DFI_AW_AERR_N_out), + .AXI_02_DFI_CLK_BUF (AXI_02_DFI_CLK_BUF_out), + .AXI_02_DFI_DBI_BYTE_DISABLE (AXI_02_DFI_DBI_BYTE_DISABLE_out), + .AXI_02_DFI_DW_RDDATA_DBI (AXI_02_DFI_DW_RDDATA_DBI_out), + .AXI_02_DFI_DW_RDDATA_DERR (AXI_02_DFI_DW_RDDATA_DERR_out), + .AXI_02_DFI_DW_RDDATA_VALID (AXI_02_DFI_DW_RDDATA_VALID_out), + .AXI_02_DFI_INIT_COMPLETE (AXI_02_DFI_INIT_COMPLETE_out), + .AXI_02_DFI_PHYUPD_REQ (AXI_02_DFI_PHYUPD_REQ_out), + .AXI_02_DFI_PHY_LP_STATE (AXI_02_DFI_PHY_LP_STATE_out), + .AXI_02_DFI_RST_N_BUF (AXI_02_DFI_RST_N_BUF_out), + .AXI_02_MC_STATUS (AXI_02_MC_STATUS_out), + .AXI_02_PHY_STATUS (AXI_02_PHY_STATUS_out), + .AXI_02_RDATA (AXI_02_RDATA_out), + .AXI_02_RDATA_PARITY (AXI_02_RDATA_PARITY_out), + .AXI_02_RID (AXI_02_RID_out), + .AXI_02_RLAST (AXI_02_RLAST_out), + .AXI_02_RRESP (AXI_02_RRESP_out), + .AXI_02_RVALID (AXI_02_RVALID_out), + .AXI_02_WREADY (AXI_02_WREADY_out), + .AXI_03_ARREADY (AXI_03_ARREADY_out), + .AXI_03_AWREADY (AXI_03_AWREADY_out), + .AXI_03_BID (AXI_03_BID_out), + .AXI_03_BRESP (AXI_03_BRESP_out), + .AXI_03_BVALID (AXI_03_BVALID_out), + .AXI_03_DFI_AW_AERR_N (AXI_03_DFI_AW_AERR_N_out), + .AXI_03_DFI_CLK_BUF (AXI_03_DFI_CLK_BUF_out), + .AXI_03_DFI_DBI_BYTE_DISABLE (AXI_03_DFI_DBI_BYTE_DISABLE_out), + .AXI_03_DFI_DW_RDDATA_DBI (AXI_03_DFI_DW_RDDATA_DBI_out), + .AXI_03_DFI_DW_RDDATA_DERR (AXI_03_DFI_DW_RDDATA_DERR_out), + .AXI_03_DFI_DW_RDDATA_VALID (AXI_03_DFI_DW_RDDATA_VALID_out), + .AXI_03_DFI_INIT_COMPLETE (AXI_03_DFI_INIT_COMPLETE_out), + .AXI_03_DFI_PHYUPD_REQ (AXI_03_DFI_PHYUPD_REQ_out), + .AXI_03_DFI_PHY_LP_STATE (AXI_03_DFI_PHY_LP_STATE_out), + .AXI_03_DFI_RST_N_BUF (AXI_03_DFI_RST_N_BUF_out), + .AXI_03_RDATA (AXI_03_RDATA_out), + .AXI_03_RDATA_PARITY (AXI_03_RDATA_PARITY_out), + .AXI_03_RID (AXI_03_RID_out), + .AXI_03_RLAST (AXI_03_RLAST_out), + .AXI_03_RRESP (AXI_03_RRESP_out), + .AXI_03_RVALID (AXI_03_RVALID_out), + .AXI_03_WREADY (AXI_03_WREADY_out), + .AXI_04_ARREADY (AXI_04_ARREADY_out), + .AXI_04_AWREADY (AXI_04_AWREADY_out), + .AXI_04_BID (AXI_04_BID_out), + .AXI_04_BRESP (AXI_04_BRESP_out), + .AXI_04_BVALID (AXI_04_BVALID_out), + .AXI_04_DFI_AW_AERR_N (AXI_04_DFI_AW_AERR_N_out), + .AXI_04_DFI_CLK_BUF (AXI_04_DFI_CLK_BUF_out), + .AXI_04_DFI_DBI_BYTE_DISABLE (AXI_04_DFI_DBI_BYTE_DISABLE_out), + .AXI_04_DFI_DW_RDDATA_DBI (AXI_04_DFI_DW_RDDATA_DBI_out), + .AXI_04_DFI_DW_RDDATA_DERR (AXI_04_DFI_DW_RDDATA_DERR_out), + .AXI_04_DFI_DW_RDDATA_VALID (AXI_04_DFI_DW_RDDATA_VALID_out), + .AXI_04_DFI_INIT_COMPLETE (AXI_04_DFI_INIT_COMPLETE_out), + .AXI_04_DFI_PHYUPD_REQ (AXI_04_DFI_PHYUPD_REQ_out), + .AXI_04_DFI_PHY_LP_STATE (AXI_04_DFI_PHY_LP_STATE_out), + .AXI_04_DFI_RST_N_BUF (AXI_04_DFI_RST_N_BUF_out), + .AXI_04_MC_STATUS (AXI_04_MC_STATUS_out), + .AXI_04_PHY_STATUS (AXI_04_PHY_STATUS_out), + .AXI_04_RDATA (AXI_04_RDATA_out), + .AXI_04_RDATA_PARITY (AXI_04_RDATA_PARITY_out), + .AXI_04_RID (AXI_04_RID_out), + .AXI_04_RLAST (AXI_04_RLAST_out), + .AXI_04_RRESP (AXI_04_RRESP_out), + .AXI_04_RVALID (AXI_04_RVALID_out), + .AXI_04_WREADY (AXI_04_WREADY_out), + .AXI_05_ARREADY (AXI_05_ARREADY_out), + .AXI_05_AWREADY (AXI_05_AWREADY_out), + .AXI_05_BID (AXI_05_BID_out), + .AXI_05_BRESP (AXI_05_BRESP_out), + .AXI_05_BVALID (AXI_05_BVALID_out), + .AXI_05_DFI_AW_AERR_N (AXI_05_DFI_AW_AERR_N_out), + .AXI_05_DFI_CLK_BUF (AXI_05_DFI_CLK_BUF_out), + .AXI_05_DFI_DBI_BYTE_DISABLE (AXI_05_DFI_DBI_BYTE_DISABLE_out), + .AXI_05_DFI_DW_RDDATA_DBI (AXI_05_DFI_DW_RDDATA_DBI_out), + .AXI_05_DFI_DW_RDDATA_DERR (AXI_05_DFI_DW_RDDATA_DERR_out), + .AXI_05_DFI_DW_RDDATA_VALID (AXI_05_DFI_DW_RDDATA_VALID_out), + .AXI_05_DFI_INIT_COMPLETE (AXI_05_DFI_INIT_COMPLETE_out), + .AXI_05_DFI_PHYUPD_REQ (AXI_05_DFI_PHYUPD_REQ_out), + .AXI_05_DFI_PHY_LP_STATE (AXI_05_DFI_PHY_LP_STATE_out), + .AXI_05_DFI_RST_N_BUF (AXI_05_DFI_RST_N_BUF_out), + .AXI_05_RDATA (AXI_05_RDATA_out), + .AXI_05_RDATA_PARITY (AXI_05_RDATA_PARITY_out), + .AXI_05_RID (AXI_05_RID_out), + .AXI_05_RLAST (AXI_05_RLAST_out), + .AXI_05_RRESP (AXI_05_RRESP_out), + .AXI_05_RVALID (AXI_05_RVALID_out), + .AXI_05_WREADY (AXI_05_WREADY_out), + .AXI_06_ARREADY (AXI_06_ARREADY_out), + .AXI_06_AWREADY (AXI_06_AWREADY_out), + .AXI_06_BID (AXI_06_BID_out), + .AXI_06_BRESP (AXI_06_BRESP_out), + .AXI_06_BVALID (AXI_06_BVALID_out), + .AXI_06_DFI_AW_AERR_N (AXI_06_DFI_AW_AERR_N_out), + .AXI_06_DFI_CLK_BUF (AXI_06_DFI_CLK_BUF_out), + .AXI_06_DFI_DBI_BYTE_DISABLE (AXI_06_DFI_DBI_BYTE_DISABLE_out), + .AXI_06_DFI_DW_RDDATA_DBI (AXI_06_DFI_DW_RDDATA_DBI_out), + .AXI_06_DFI_DW_RDDATA_DERR (AXI_06_DFI_DW_RDDATA_DERR_out), + .AXI_06_DFI_DW_RDDATA_VALID (AXI_06_DFI_DW_RDDATA_VALID_out), + .AXI_06_DFI_INIT_COMPLETE (AXI_06_DFI_INIT_COMPLETE_out), + .AXI_06_DFI_PHYUPD_REQ (AXI_06_DFI_PHYUPD_REQ_out), + .AXI_06_DFI_PHY_LP_STATE (AXI_06_DFI_PHY_LP_STATE_out), + .AXI_06_DFI_RST_N_BUF (AXI_06_DFI_RST_N_BUF_out), + .AXI_06_MC_STATUS (AXI_06_MC_STATUS_out), + .AXI_06_PHY_STATUS (AXI_06_PHY_STATUS_out), + .AXI_06_RDATA (AXI_06_RDATA_out), + .AXI_06_RDATA_PARITY (AXI_06_RDATA_PARITY_out), + .AXI_06_RID (AXI_06_RID_out), + .AXI_06_RLAST (AXI_06_RLAST_out), + .AXI_06_RRESP (AXI_06_RRESP_out), + .AXI_06_RVALID (AXI_06_RVALID_out), + .AXI_06_WREADY (AXI_06_WREADY_out), + .AXI_07_ARREADY (AXI_07_ARREADY_out), + .AXI_07_AWREADY (AXI_07_AWREADY_out), + .AXI_07_BID (AXI_07_BID_out), + .AXI_07_BRESP (AXI_07_BRESP_out), + .AXI_07_BVALID (AXI_07_BVALID_out), + .AXI_07_DFI_AW_AERR_N (AXI_07_DFI_AW_AERR_N_out), + .AXI_07_DFI_CLK_BUF (AXI_07_DFI_CLK_BUF_out), + .AXI_07_DFI_DBI_BYTE_DISABLE (AXI_07_DFI_DBI_BYTE_DISABLE_out), + .AXI_07_DFI_DW_RDDATA_DBI (AXI_07_DFI_DW_RDDATA_DBI_out), + .AXI_07_DFI_DW_RDDATA_DERR (AXI_07_DFI_DW_RDDATA_DERR_out), + .AXI_07_DFI_DW_RDDATA_VALID (AXI_07_DFI_DW_RDDATA_VALID_out), + .AXI_07_DFI_INIT_COMPLETE (AXI_07_DFI_INIT_COMPLETE_out), + .AXI_07_DFI_PHYUPD_REQ (AXI_07_DFI_PHYUPD_REQ_out), + .AXI_07_DFI_PHY_LP_STATE (AXI_07_DFI_PHY_LP_STATE_out), + .AXI_07_DFI_RST_N_BUF (AXI_07_DFI_RST_N_BUF_out), + .AXI_07_RDATA (AXI_07_RDATA_out), + .AXI_07_RDATA_PARITY (AXI_07_RDATA_PARITY_out), + .AXI_07_RID (AXI_07_RID_out), + .AXI_07_RLAST (AXI_07_RLAST_out), + .AXI_07_RRESP (AXI_07_RRESP_out), + .AXI_07_RVALID (AXI_07_RVALID_out), + .AXI_07_WREADY (AXI_07_WREADY_out), + .AXI_08_ARREADY (AXI_08_ARREADY_out), + .AXI_08_AWREADY (AXI_08_AWREADY_out), + .AXI_08_BID (AXI_08_BID_out), + .AXI_08_BRESP (AXI_08_BRESP_out), + .AXI_08_BVALID (AXI_08_BVALID_out), + .AXI_08_DFI_AW_AERR_N (AXI_08_DFI_AW_AERR_N_out), + .AXI_08_DFI_CLK_BUF (AXI_08_DFI_CLK_BUF_out), + .AXI_08_DFI_DBI_BYTE_DISABLE (AXI_08_DFI_DBI_BYTE_DISABLE_out), + .AXI_08_DFI_DW_RDDATA_DBI (AXI_08_DFI_DW_RDDATA_DBI_out), + .AXI_08_DFI_DW_RDDATA_DERR (AXI_08_DFI_DW_RDDATA_DERR_out), + .AXI_08_DFI_DW_RDDATA_VALID (AXI_08_DFI_DW_RDDATA_VALID_out), + .AXI_08_DFI_INIT_COMPLETE (AXI_08_DFI_INIT_COMPLETE_out), + .AXI_08_DFI_PHYUPD_REQ (AXI_08_DFI_PHYUPD_REQ_out), + .AXI_08_DFI_PHY_LP_STATE (AXI_08_DFI_PHY_LP_STATE_out), + .AXI_08_DFI_RST_N_BUF (AXI_08_DFI_RST_N_BUF_out), + .AXI_08_MC_STATUS (AXI_08_MC_STATUS_out), + .AXI_08_PHY_STATUS (AXI_08_PHY_STATUS_out), + .AXI_08_RDATA (AXI_08_RDATA_out), + .AXI_08_RDATA_PARITY (AXI_08_RDATA_PARITY_out), + .AXI_08_RID (AXI_08_RID_out), + .AXI_08_RLAST (AXI_08_RLAST_out), + .AXI_08_RRESP (AXI_08_RRESP_out), + .AXI_08_RVALID (AXI_08_RVALID_out), + .AXI_08_WREADY (AXI_08_WREADY_out), + .AXI_09_ARREADY (AXI_09_ARREADY_out), + .AXI_09_AWREADY (AXI_09_AWREADY_out), + .AXI_09_BID (AXI_09_BID_out), + .AXI_09_BRESP (AXI_09_BRESP_out), + .AXI_09_BVALID (AXI_09_BVALID_out), + .AXI_09_DFI_AW_AERR_N (AXI_09_DFI_AW_AERR_N_out), + .AXI_09_DFI_CLK_BUF (AXI_09_DFI_CLK_BUF_out), + .AXI_09_DFI_DBI_BYTE_DISABLE (AXI_09_DFI_DBI_BYTE_DISABLE_out), + .AXI_09_DFI_DW_RDDATA_DBI (AXI_09_DFI_DW_RDDATA_DBI_out), + .AXI_09_DFI_DW_RDDATA_DERR (AXI_09_DFI_DW_RDDATA_DERR_out), + .AXI_09_DFI_DW_RDDATA_VALID (AXI_09_DFI_DW_RDDATA_VALID_out), + .AXI_09_DFI_INIT_COMPLETE (AXI_09_DFI_INIT_COMPLETE_out), + .AXI_09_DFI_PHYUPD_REQ (AXI_09_DFI_PHYUPD_REQ_out), + .AXI_09_DFI_PHY_LP_STATE (AXI_09_DFI_PHY_LP_STATE_out), + .AXI_09_DFI_RST_N_BUF (AXI_09_DFI_RST_N_BUF_out), + .AXI_09_RDATA (AXI_09_RDATA_out), + .AXI_09_RDATA_PARITY (AXI_09_RDATA_PARITY_out), + .AXI_09_RID (AXI_09_RID_out), + .AXI_09_RLAST (AXI_09_RLAST_out), + .AXI_09_RRESP (AXI_09_RRESP_out), + .AXI_09_RVALID (AXI_09_RVALID_out), + .AXI_09_WREADY (AXI_09_WREADY_out), + .AXI_10_ARREADY (AXI_10_ARREADY_out), + .AXI_10_AWREADY (AXI_10_AWREADY_out), + .AXI_10_BID (AXI_10_BID_out), + .AXI_10_BRESP (AXI_10_BRESP_out), + .AXI_10_BVALID (AXI_10_BVALID_out), + .AXI_10_DFI_AW_AERR_N (AXI_10_DFI_AW_AERR_N_out), + .AXI_10_DFI_CLK_BUF (AXI_10_DFI_CLK_BUF_out), + .AXI_10_DFI_DBI_BYTE_DISABLE (AXI_10_DFI_DBI_BYTE_DISABLE_out), + .AXI_10_DFI_DW_RDDATA_DBI (AXI_10_DFI_DW_RDDATA_DBI_out), + .AXI_10_DFI_DW_RDDATA_DERR (AXI_10_DFI_DW_RDDATA_DERR_out), + .AXI_10_DFI_DW_RDDATA_VALID (AXI_10_DFI_DW_RDDATA_VALID_out), + .AXI_10_DFI_INIT_COMPLETE (AXI_10_DFI_INIT_COMPLETE_out), + .AXI_10_DFI_PHYUPD_REQ (AXI_10_DFI_PHYUPD_REQ_out), + .AXI_10_DFI_PHY_LP_STATE (AXI_10_DFI_PHY_LP_STATE_out), + .AXI_10_DFI_RST_N_BUF (AXI_10_DFI_RST_N_BUF_out), + .AXI_10_MC_STATUS (AXI_10_MC_STATUS_out), + .AXI_10_PHY_STATUS (AXI_10_PHY_STATUS_out), + .AXI_10_RDATA (AXI_10_RDATA_out), + .AXI_10_RDATA_PARITY (AXI_10_RDATA_PARITY_out), + .AXI_10_RID (AXI_10_RID_out), + .AXI_10_RLAST (AXI_10_RLAST_out), + .AXI_10_RRESP (AXI_10_RRESP_out), + .AXI_10_RVALID (AXI_10_RVALID_out), + .AXI_10_WREADY (AXI_10_WREADY_out), + .AXI_11_ARREADY (AXI_11_ARREADY_out), + .AXI_11_AWREADY (AXI_11_AWREADY_out), + .AXI_11_BID (AXI_11_BID_out), + .AXI_11_BRESP (AXI_11_BRESP_out), + .AXI_11_BVALID (AXI_11_BVALID_out), + .AXI_11_DFI_AW_AERR_N (AXI_11_DFI_AW_AERR_N_out), + .AXI_11_DFI_CLK_BUF (AXI_11_DFI_CLK_BUF_out), + .AXI_11_DFI_DBI_BYTE_DISABLE (AXI_11_DFI_DBI_BYTE_DISABLE_out), + .AXI_11_DFI_DW_RDDATA_DBI (AXI_11_DFI_DW_RDDATA_DBI_out), + .AXI_11_DFI_DW_RDDATA_DERR (AXI_11_DFI_DW_RDDATA_DERR_out), + .AXI_11_DFI_DW_RDDATA_VALID (AXI_11_DFI_DW_RDDATA_VALID_out), + .AXI_11_DFI_INIT_COMPLETE (AXI_11_DFI_INIT_COMPLETE_out), + .AXI_11_DFI_PHYUPD_REQ (AXI_11_DFI_PHYUPD_REQ_out), + .AXI_11_DFI_PHY_LP_STATE (AXI_11_DFI_PHY_LP_STATE_out), + .AXI_11_DFI_RST_N_BUF (AXI_11_DFI_RST_N_BUF_out), + .AXI_11_RDATA (AXI_11_RDATA_out), + .AXI_11_RDATA_PARITY (AXI_11_RDATA_PARITY_out), + .AXI_11_RID (AXI_11_RID_out), + .AXI_11_RLAST (AXI_11_RLAST_out), + .AXI_11_RRESP (AXI_11_RRESP_out), + .AXI_11_RVALID (AXI_11_RVALID_out), + .AXI_11_WREADY (AXI_11_WREADY_out), + .AXI_12_ARREADY (AXI_12_ARREADY_out), + .AXI_12_AWREADY (AXI_12_AWREADY_out), + .AXI_12_BID (AXI_12_BID_out), + .AXI_12_BRESP (AXI_12_BRESP_out), + .AXI_12_BVALID (AXI_12_BVALID_out), + .AXI_12_DFI_AW_AERR_N (AXI_12_DFI_AW_AERR_N_out), + .AXI_12_DFI_CLK_BUF (AXI_12_DFI_CLK_BUF_out), + .AXI_12_DFI_DBI_BYTE_DISABLE (AXI_12_DFI_DBI_BYTE_DISABLE_out), + .AXI_12_DFI_DW_RDDATA_DBI (AXI_12_DFI_DW_RDDATA_DBI_out), + .AXI_12_DFI_DW_RDDATA_DERR (AXI_12_DFI_DW_RDDATA_DERR_out), + .AXI_12_DFI_DW_RDDATA_VALID (AXI_12_DFI_DW_RDDATA_VALID_out), + .AXI_12_DFI_INIT_COMPLETE (AXI_12_DFI_INIT_COMPLETE_out), + .AXI_12_DFI_PHYUPD_REQ (AXI_12_DFI_PHYUPD_REQ_out), + .AXI_12_DFI_PHY_LP_STATE (AXI_12_DFI_PHY_LP_STATE_out), + .AXI_12_DFI_RST_N_BUF (AXI_12_DFI_RST_N_BUF_out), + .AXI_12_MC_STATUS (AXI_12_MC_STATUS_out), + .AXI_12_PHY_STATUS (AXI_12_PHY_STATUS_out), + .AXI_12_RDATA (AXI_12_RDATA_out), + .AXI_12_RDATA_PARITY (AXI_12_RDATA_PARITY_out), + .AXI_12_RID (AXI_12_RID_out), + .AXI_12_RLAST (AXI_12_RLAST_out), + .AXI_12_RRESP (AXI_12_RRESP_out), + .AXI_12_RVALID (AXI_12_RVALID_out), + .AXI_12_WREADY (AXI_12_WREADY_out), + .AXI_13_ARREADY (AXI_13_ARREADY_out), + .AXI_13_AWREADY (AXI_13_AWREADY_out), + .AXI_13_BID (AXI_13_BID_out), + .AXI_13_BRESP (AXI_13_BRESP_out), + .AXI_13_BVALID (AXI_13_BVALID_out), + .AXI_13_DFI_AW_AERR_N (AXI_13_DFI_AW_AERR_N_out), + .AXI_13_DFI_CLK_BUF (AXI_13_DFI_CLK_BUF_out), + .AXI_13_DFI_DBI_BYTE_DISABLE (AXI_13_DFI_DBI_BYTE_DISABLE_out), + .AXI_13_DFI_DW_RDDATA_DBI (AXI_13_DFI_DW_RDDATA_DBI_out), + .AXI_13_DFI_DW_RDDATA_DERR (AXI_13_DFI_DW_RDDATA_DERR_out), + .AXI_13_DFI_DW_RDDATA_VALID (AXI_13_DFI_DW_RDDATA_VALID_out), + .AXI_13_DFI_INIT_COMPLETE (AXI_13_DFI_INIT_COMPLETE_out), + .AXI_13_DFI_PHYUPD_REQ (AXI_13_DFI_PHYUPD_REQ_out), + .AXI_13_DFI_PHY_LP_STATE (AXI_13_DFI_PHY_LP_STATE_out), + .AXI_13_DFI_RST_N_BUF (AXI_13_DFI_RST_N_BUF_out), + .AXI_13_RDATA (AXI_13_RDATA_out), + .AXI_13_RDATA_PARITY (AXI_13_RDATA_PARITY_out), + .AXI_13_RID (AXI_13_RID_out), + .AXI_13_RLAST (AXI_13_RLAST_out), + .AXI_13_RRESP (AXI_13_RRESP_out), + .AXI_13_RVALID (AXI_13_RVALID_out), + .AXI_13_WREADY (AXI_13_WREADY_out), + .AXI_14_ARREADY (AXI_14_ARREADY_out), + .AXI_14_AWREADY (AXI_14_AWREADY_out), + .AXI_14_BID (AXI_14_BID_out), + .AXI_14_BRESP (AXI_14_BRESP_out), + .AXI_14_BVALID (AXI_14_BVALID_out), + .AXI_14_DFI_AW_AERR_N (AXI_14_DFI_AW_AERR_N_out), + .AXI_14_DFI_CLK_BUF (AXI_14_DFI_CLK_BUF_out), + .AXI_14_DFI_DBI_BYTE_DISABLE (AXI_14_DFI_DBI_BYTE_DISABLE_out), + .AXI_14_DFI_DW_RDDATA_DBI (AXI_14_DFI_DW_RDDATA_DBI_out), + .AXI_14_DFI_DW_RDDATA_DERR (AXI_14_DFI_DW_RDDATA_DERR_out), + .AXI_14_DFI_DW_RDDATA_VALID (AXI_14_DFI_DW_RDDATA_VALID_out), + .AXI_14_DFI_INIT_COMPLETE (AXI_14_DFI_INIT_COMPLETE_out), + .AXI_14_DFI_PHYUPD_REQ (AXI_14_DFI_PHYUPD_REQ_out), + .AXI_14_DFI_PHY_LP_STATE (AXI_14_DFI_PHY_LP_STATE_out), + .AXI_14_DFI_RST_N_BUF (AXI_14_DFI_RST_N_BUF_out), + .AXI_14_MC_STATUS (AXI_14_MC_STATUS_out), + .AXI_14_PHY_STATUS (AXI_14_PHY_STATUS_out), + .AXI_14_RDATA (AXI_14_RDATA_out), + .AXI_14_RDATA_PARITY (AXI_14_RDATA_PARITY_out), + .AXI_14_RID (AXI_14_RID_out), + .AXI_14_RLAST (AXI_14_RLAST_out), + .AXI_14_RRESP (AXI_14_RRESP_out), + .AXI_14_RVALID (AXI_14_RVALID_out), + .AXI_14_WREADY (AXI_14_WREADY_out), + .AXI_15_ARREADY (AXI_15_ARREADY_out), + .AXI_15_AWREADY (AXI_15_AWREADY_out), + .AXI_15_BID (AXI_15_BID_out), + .AXI_15_BRESP (AXI_15_BRESP_out), + .AXI_15_BVALID (AXI_15_BVALID_out), + .AXI_15_DFI_AW_AERR_N (AXI_15_DFI_AW_AERR_N_out), + .AXI_15_DFI_CLK_BUF (AXI_15_DFI_CLK_BUF_out), + .AXI_15_DFI_DBI_BYTE_DISABLE (AXI_15_DFI_DBI_BYTE_DISABLE_out), + .AXI_15_DFI_DW_RDDATA_DBI (AXI_15_DFI_DW_RDDATA_DBI_out), + .AXI_15_DFI_DW_RDDATA_DERR (AXI_15_DFI_DW_RDDATA_DERR_out), + .AXI_15_DFI_DW_RDDATA_VALID (AXI_15_DFI_DW_RDDATA_VALID_out), + .AXI_15_DFI_INIT_COMPLETE (AXI_15_DFI_INIT_COMPLETE_out), + .AXI_15_DFI_PHYUPD_REQ (AXI_15_DFI_PHYUPD_REQ_out), + .AXI_15_DFI_PHY_LP_STATE (AXI_15_DFI_PHY_LP_STATE_out), + .AXI_15_DFI_RST_N_BUF (AXI_15_DFI_RST_N_BUF_out), + .AXI_15_RDATA (AXI_15_RDATA_out), + .AXI_15_RDATA_PARITY (AXI_15_RDATA_PARITY_out), + .AXI_15_RID (AXI_15_RID_out), + .AXI_15_RLAST (AXI_15_RLAST_out), + .AXI_15_RRESP (AXI_15_RRESP_out), + .AXI_15_RVALID (AXI_15_RVALID_out), + .AXI_15_WREADY (AXI_15_WREADY_out), + .AXI_16_ARREADY (AXI_16_ARREADY_out), + .AXI_16_AWREADY (AXI_16_AWREADY_out), + .AXI_16_BID (AXI_16_BID_out), + .AXI_16_BRESP (AXI_16_BRESP_out), + .AXI_16_BVALID (AXI_16_BVALID_out), + .AXI_16_DFI_AW_AERR_N (AXI_16_DFI_AW_AERR_N_out), + .AXI_16_DFI_CLK_BUF (AXI_16_DFI_CLK_BUF_out), + .AXI_16_DFI_DBI_BYTE_DISABLE (AXI_16_DFI_DBI_BYTE_DISABLE_out), + .AXI_16_DFI_DW_RDDATA_DBI (AXI_16_DFI_DW_RDDATA_DBI_out), + .AXI_16_DFI_DW_RDDATA_DERR (AXI_16_DFI_DW_RDDATA_DERR_out), + .AXI_16_DFI_DW_RDDATA_VALID (AXI_16_DFI_DW_RDDATA_VALID_out), + .AXI_16_DFI_INIT_COMPLETE (AXI_16_DFI_INIT_COMPLETE_out), + .AXI_16_DFI_PHYUPD_REQ (AXI_16_DFI_PHYUPD_REQ_out), + .AXI_16_DFI_PHY_LP_STATE (AXI_16_DFI_PHY_LP_STATE_out), + .AXI_16_DFI_RST_N_BUF (AXI_16_DFI_RST_N_BUF_out), + .AXI_16_MC_STATUS (AXI_16_MC_STATUS_out), + .AXI_16_PHY_STATUS (AXI_16_PHY_STATUS_out), + .AXI_16_RDATA (AXI_16_RDATA_out), + .AXI_16_RDATA_PARITY (AXI_16_RDATA_PARITY_out), + .AXI_16_RID (AXI_16_RID_out), + .AXI_16_RLAST (AXI_16_RLAST_out), + .AXI_16_RRESP (AXI_16_RRESP_out), + .AXI_16_RVALID (AXI_16_RVALID_out), + .AXI_16_WREADY (AXI_16_WREADY_out), + .AXI_17_ARREADY (AXI_17_ARREADY_out), + .AXI_17_AWREADY (AXI_17_AWREADY_out), + .AXI_17_BID (AXI_17_BID_out), + .AXI_17_BRESP (AXI_17_BRESP_out), + .AXI_17_BVALID (AXI_17_BVALID_out), + .AXI_17_DFI_AW_AERR_N (AXI_17_DFI_AW_AERR_N_out), + .AXI_17_DFI_CLK_BUF (AXI_17_DFI_CLK_BUF_out), + .AXI_17_DFI_DBI_BYTE_DISABLE (AXI_17_DFI_DBI_BYTE_DISABLE_out), + .AXI_17_DFI_DW_RDDATA_DBI (AXI_17_DFI_DW_RDDATA_DBI_out), + .AXI_17_DFI_DW_RDDATA_DERR (AXI_17_DFI_DW_RDDATA_DERR_out), + .AXI_17_DFI_DW_RDDATA_VALID (AXI_17_DFI_DW_RDDATA_VALID_out), + .AXI_17_DFI_INIT_COMPLETE (AXI_17_DFI_INIT_COMPLETE_out), + .AXI_17_DFI_PHYUPD_REQ (AXI_17_DFI_PHYUPD_REQ_out), + .AXI_17_DFI_PHY_LP_STATE (AXI_17_DFI_PHY_LP_STATE_out), + .AXI_17_DFI_RST_N_BUF (AXI_17_DFI_RST_N_BUF_out), + .AXI_17_RDATA (AXI_17_RDATA_out), + .AXI_17_RDATA_PARITY (AXI_17_RDATA_PARITY_out), + .AXI_17_RID (AXI_17_RID_out), + .AXI_17_RLAST (AXI_17_RLAST_out), + .AXI_17_RRESP (AXI_17_RRESP_out), + .AXI_17_RVALID (AXI_17_RVALID_out), + .AXI_17_WREADY (AXI_17_WREADY_out), + .AXI_18_ARREADY (AXI_18_ARREADY_out), + .AXI_18_AWREADY (AXI_18_AWREADY_out), + .AXI_18_BID (AXI_18_BID_out), + .AXI_18_BRESP (AXI_18_BRESP_out), + .AXI_18_BVALID (AXI_18_BVALID_out), + .AXI_18_DFI_AW_AERR_N (AXI_18_DFI_AW_AERR_N_out), + .AXI_18_DFI_CLK_BUF (AXI_18_DFI_CLK_BUF_out), + .AXI_18_DFI_DBI_BYTE_DISABLE (AXI_18_DFI_DBI_BYTE_DISABLE_out), + .AXI_18_DFI_DW_RDDATA_DBI (AXI_18_DFI_DW_RDDATA_DBI_out), + .AXI_18_DFI_DW_RDDATA_DERR (AXI_18_DFI_DW_RDDATA_DERR_out), + .AXI_18_DFI_DW_RDDATA_VALID (AXI_18_DFI_DW_RDDATA_VALID_out), + .AXI_18_DFI_INIT_COMPLETE (AXI_18_DFI_INIT_COMPLETE_out), + .AXI_18_DFI_PHYUPD_REQ (AXI_18_DFI_PHYUPD_REQ_out), + .AXI_18_DFI_PHY_LP_STATE (AXI_18_DFI_PHY_LP_STATE_out), + .AXI_18_DFI_RST_N_BUF (AXI_18_DFI_RST_N_BUF_out), + .AXI_18_MC_STATUS (AXI_18_MC_STATUS_out), + .AXI_18_PHY_STATUS (AXI_18_PHY_STATUS_out), + .AXI_18_RDATA (AXI_18_RDATA_out), + .AXI_18_RDATA_PARITY (AXI_18_RDATA_PARITY_out), + .AXI_18_RID (AXI_18_RID_out), + .AXI_18_RLAST (AXI_18_RLAST_out), + .AXI_18_RRESP (AXI_18_RRESP_out), + .AXI_18_RVALID (AXI_18_RVALID_out), + .AXI_18_WREADY (AXI_18_WREADY_out), + .AXI_19_ARREADY (AXI_19_ARREADY_out), + .AXI_19_AWREADY (AXI_19_AWREADY_out), + .AXI_19_BID (AXI_19_BID_out), + .AXI_19_BRESP (AXI_19_BRESP_out), + .AXI_19_BVALID (AXI_19_BVALID_out), + .AXI_19_DFI_AW_AERR_N (AXI_19_DFI_AW_AERR_N_out), + .AXI_19_DFI_CLK_BUF (AXI_19_DFI_CLK_BUF_out), + .AXI_19_DFI_DBI_BYTE_DISABLE (AXI_19_DFI_DBI_BYTE_DISABLE_out), + .AXI_19_DFI_DW_RDDATA_DBI (AXI_19_DFI_DW_RDDATA_DBI_out), + .AXI_19_DFI_DW_RDDATA_DERR (AXI_19_DFI_DW_RDDATA_DERR_out), + .AXI_19_DFI_DW_RDDATA_VALID (AXI_19_DFI_DW_RDDATA_VALID_out), + .AXI_19_DFI_INIT_COMPLETE (AXI_19_DFI_INIT_COMPLETE_out), + .AXI_19_DFI_PHYUPD_REQ (AXI_19_DFI_PHYUPD_REQ_out), + .AXI_19_DFI_PHY_LP_STATE (AXI_19_DFI_PHY_LP_STATE_out), + .AXI_19_DFI_RST_N_BUF (AXI_19_DFI_RST_N_BUF_out), + .AXI_19_RDATA (AXI_19_RDATA_out), + .AXI_19_RDATA_PARITY (AXI_19_RDATA_PARITY_out), + .AXI_19_RID (AXI_19_RID_out), + .AXI_19_RLAST (AXI_19_RLAST_out), + .AXI_19_RRESP (AXI_19_RRESP_out), + .AXI_19_RVALID (AXI_19_RVALID_out), + .AXI_19_WREADY (AXI_19_WREADY_out), + .AXI_20_ARREADY (AXI_20_ARREADY_out), + .AXI_20_AWREADY (AXI_20_AWREADY_out), + .AXI_20_BID (AXI_20_BID_out), + .AXI_20_BRESP (AXI_20_BRESP_out), + .AXI_20_BVALID (AXI_20_BVALID_out), + .AXI_20_DFI_AW_AERR_N (AXI_20_DFI_AW_AERR_N_out), + .AXI_20_DFI_CLK_BUF (AXI_20_DFI_CLK_BUF_out), + .AXI_20_DFI_DBI_BYTE_DISABLE (AXI_20_DFI_DBI_BYTE_DISABLE_out), + .AXI_20_DFI_DW_RDDATA_DBI (AXI_20_DFI_DW_RDDATA_DBI_out), + .AXI_20_DFI_DW_RDDATA_DERR (AXI_20_DFI_DW_RDDATA_DERR_out), + .AXI_20_DFI_DW_RDDATA_VALID (AXI_20_DFI_DW_RDDATA_VALID_out), + .AXI_20_DFI_INIT_COMPLETE (AXI_20_DFI_INIT_COMPLETE_out), + .AXI_20_DFI_PHYUPD_REQ (AXI_20_DFI_PHYUPD_REQ_out), + .AXI_20_DFI_PHY_LP_STATE (AXI_20_DFI_PHY_LP_STATE_out), + .AXI_20_DFI_RST_N_BUF (AXI_20_DFI_RST_N_BUF_out), + .AXI_20_MC_STATUS (AXI_20_MC_STATUS_out), + .AXI_20_PHY_STATUS (AXI_20_PHY_STATUS_out), + .AXI_20_RDATA (AXI_20_RDATA_out), + .AXI_20_RDATA_PARITY (AXI_20_RDATA_PARITY_out), + .AXI_20_RID (AXI_20_RID_out), + .AXI_20_RLAST (AXI_20_RLAST_out), + .AXI_20_RRESP (AXI_20_RRESP_out), + .AXI_20_RVALID (AXI_20_RVALID_out), + .AXI_20_WREADY (AXI_20_WREADY_out), + .AXI_21_ARREADY (AXI_21_ARREADY_out), + .AXI_21_AWREADY (AXI_21_AWREADY_out), + .AXI_21_BID (AXI_21_BID_out), + .AXI_21_BRESP (AXI_21_BRESP_out), + .AXI_21_BVALID (AXI_21_BVALID_out), + .AXI_21_DFI_AW_AERR_N (AXI_21_DFI_AW_AERR_N_out), + .AXI_21_DFI_CLK_BUF (AXI_21_DFI_CLK_BUF_out), + .AXI_21_DFI_DBI_BYTE_DISABLE (AXI_21_DFI_DBI_BYTE_DISABLE_out), + .AXI_21_DFI_DW_RDDATA_DBI (AXI_21_DFI_DW_RDDATA_DBI_out), + .AXI_21_DFI_DW_RDDATA_DERR (AXI_21_DFI_DW_RDDATA_DERR_out), + .AXI_21_DFI_DW_RDDATA_VALID (AXI_21_DFI_DW_RDDATA_VALID_out), + .AXI_21_DFI_INIT_COMPLETE (AXI_21_DFI_INIT_COMPLETE_out), + .AXI_21_DFI_PHYUPD_REQ (AXI_21_DFI_PHYUPD_REQ_out), + .AXI_21_DFI_PHY_LP_STATE (AXI_21_DFI_PHY_LP_STATE_out), + .AXI_21_DFI_RST_N_BUF (AXI_21_DFI_RST_N_BUF_out), + .AXI_21_RDATA (AXI_21_RDATA_out), + .AXI_21_RDATA_PARITY (AXI_21_RDATA_PARITY_out), + .AXI_21_RID (AXI_21_RID_out), + .AXI_21_RLAST (AXI_21_RLAST_out), + .AXI_21_RRESP (AXI_21_RRESP_out), + .AXI_21_RVALID (AXI_21_RVALID_out), + .AXI_21_WREADY (AXI_21_WREADY_out), + .AXI_22_ARREADY (AXI_22_ARREADY_out), + .AXI_22_AWREADY (AXI_22_AWREADY_out), + .AXI_22_BID (AXI_22_BID_out), + .AXI_22_BRESP (AXI_22_BRESP_out), + .AXI_22_BVALID (AXI_22_BVALID_out), + .AXI_22_DFI_AW_AERR_N (AXI_22_DFI_AW_AERR_N_out), + .AXI_22_DFI_CLK_BUF (AXI_22_DFI_CLK_BUF_out), + .AXI_22_DFI_DBI_BYTE_DISABLE (AXI_22_DFI_DBI_BYTE_DISABLE_out), + .AXI_22_DFI_DW_RDDATA_DBI (AXI_22_DFI_DW_RDDATA_DBI_out), + .AXI_22_DFI_DW_RDDATA_DERR (AXI_22_DFI_DW_RDDATA_DERR_out), + .AXI_22_DFI_DW_RDDATA_VALID (AXI_22_DFI_DW_RDDATA_VALID_out), + .AXI_22_DFI_INIT_COMPLETE (AXI_22_DFI_INIT_COMPLETE_out), + .AXI_22_DFI_PHYUPD_REQ (AXI_22_DFI_PHYUPD_REQ_out), + .AXI_22_DFI_PHY_LP_STATE (AXI_22_DFI_PHY_LP_STATE_out), + .AXI_22_DFI_RST_N_BUF (AXI_22_DFI_RST_N_BUF_out), + .AXI_22_MC_STATUS (AXI_22_MC_STATUS_out), + .AXI_22_PHY_STATUS (AXI_22_PHY_STATUS_out), + .AXI_22_RDATA (AXI_22_RDATA_out), + .AXI_22_RDATA_PARITY (AXI_22_RDATA_PARITY_out), + .AXI_22_RID (AXI_22_RID_out), + .AXI_22_RLAST (AXI_22_RLAST_out), + .AXI_22_RRESP (AXI_22_RRESP_out), + .AXI_22_RVALID (AXI_22_RVALID_out), + .AXI_22_WREADY (AXI_22_WREADY_out), + .AXI_23_ARREADY (AXI_23_ARREADY_out), + .AXI_23_AWREADY (AXI_23_AWREADY_out), + .AXI_23_BID (AXI_23_BID_out), + .AXI_23_BRESP (AXI_23_BRESP_out), + .AXI_23_BVALID (AXI_23_BVALID_out), + .AXI_23_DFI_AW_AERR_N (AXI_23_DFI_AW_AERR_N_out), + .AXI_23_DFI_CLK_BUF (AXI_23_DFI_CLK_BUF_out), + .AXI_23_DFI_DBI_BYTE_DISABLE (AXI_23_DFI_DBI_BYTE_DISABLE_out), + .AXI_23_DFI_DW_RDDATA_DBI (AXI_23_DFI_DW_RDDATA_DBI_out), + .AXI_23_DFI_DW_RDDATA_DERR (AXI_23_DFI_DW_RDDATA_DERR_out), + .AXI_23_DFI_DW_RDDATA_VALID (AXI_23_DFI_DW_RDDATA_VALID_out), + .AXI_23_DFI_INIT_COMPLETE (AXI_23_DFI_INIT_COMPLETE_out), + .AXI_23_DFI_PHYUPD_REQ (AXI_23_DFI_PHYUPD_REQ_out), + .AXI_23_DFI_PHY_LP_STATE (AXI_23_DFI_PHY_LP_STATE_out), + .AXI_23_DFI_RST_N_BUF (AXI_23_DFI_RST_N_BUF_out), + .AXI_23_RDATA (AXI_23_RDATA_out), + .AXI_23_RDATA_PARITY (AXI_23_RDATA_PARITY_out), + .AXI_23_RID (AXI_23_RID_out), + .AXI_23_RLAST (AXI_23_RLAST_out), + .AXI_23_RRESP (AXI_23_RRESP_out), + .AXI_23_RVALID (AXI_23_RVALID_out), + .AXI_23_WREADY (AXI_23_WREADY_out), + .AXI_24_ARREADY (AXI_24_ARREADY_out), + .AXI_24_AWREADY (AXI_24_AWREADY_out), + .AXI_24_BID (AXI_24_BID_out), + .AXI_24_BRESP (AXI_24_BRESP_out), + .AXI_24_BVALID (AXI_24_BVALID_out), + .AXI_24_DFI_AW_AERR_N (AXI_24_DFI_AW_AERR_N_out), + .AXI_24_DFI_CLK_BUF (AXI_24_DFI_CLK_BUF_out), + .AXI_24_DFI_DBI_BYTE_DISABLE (AXI_24_DFI_DBI_BYTE_DISABLE_out), + .AXI_24_DFI_DW_RDDATA_DBI (AXI_24_DFI_DW_RDDATA_DBI_out), + .AXI_24_DFI_DW_RDDATA_DERR (AXI_24_DFI_DW_RDDATA_DERR_out), + .AXI_24_DFI_DW_RDDATA_VALID (AXI_24_DFI_DW_RDDATA_VALID_out), + .AXI_24_DFI_INIT_COMPLETE (AXI_24_DFI_INIT_COMPLETE_out), + .AXI_24_DFI_PHYUPD_REQ (AXI_24_DFI_PHYUPD_REQ_out), + .AXI_24_DFI_PHY_LP_STATE (AXI_24_DFI_PHY_LP_STATE_out), + .AXI_24_DFI_RST_N_BUF (AXI_24_DFI_RST_N_BUF_out), + .AXI_24_MC_STATUS (AXI_24_MC_STATUS_out), + .AXI_24_PHY_STATUS (AXI_24_PHY_STATUS_out), + .AXI_24_RDATA (AXI_24_RDATA_out), + .AXI_24_RDATA_PARITY (AXI_24_RDATA_PARITY_out), + .AXI_24_RID (AXI_24_RID_out), + .AXI_24_RLAST (AXI_24_RLAST_out), + .AXI_24_RRESP (AXI_24_RRESP_out), + .AXI_24_RVALID (AXI_24_RVALID_out), + .AXI_24_WREADY (AXI_24_WREADY_out), + .AXI_25_ARREADY (AXI_25_ARREADY_out), + .AXI_25_AWREADY (AXI_25_AWREADY_out), + .AXI_25_BID (AXI_25_BID_out), + .AXI_25_BRESP (AXI_25_BRESP_out), + .AXI_25_BVALID (AXI_25_BVALID_out), + .AXI_25_DFI_AW_AERR_N (AXI_25_DFI_AW_AERR_N_out), + .AXI_25_DFI_CLK_BUF (AXI_25_DFI_CLK_BUF_out), + .AXI_25_DFI_DBI_BYTE_DISABLE (AXI_25_DFI_DBI_BYTE_DISABLE_out), + .AXI_25_DFI_DW_RDDATA_DBI (AXI_25_DFI_DW_RDDATA_DBI_out), + .AXI_25_DFI_DW_RDDATA_DERR (AXI_25_DFI_DW_RDDATA_DERR_out), + .AXI_25_DFI_DW_RDDATA_VALID (AXI_25_DFI_DW_RDDATA_VALID_out), + .AXI_25_DFI_INIT_COMPLETE (AXI_25_DFI_INIT_COMPLETE_out), + .AXI_25_DFI_PHYUPD_REQ (AXI_25_DFI_PHYUPD_REQ_out), + .AXI_25_DFI_PHY_LP_STATE (AXI_25_DFI_PHY_LP_STATE_out), + .AXI_25_DFI_RST_N_BUF (AXI_25_DFI_RST_N_BUF_out), + .AXI_25_RDATA (AXI_25_RDATA_out), + .AXI_25_RDATA_PARITY (AXI_25_RDATA_PARITY_out), + .AXI_25_RID (AXI_25_RID_out), + .AXI_25_RLAST (AXI_25_RLAST_out), + .AXI_25_RRESP (AXI_25_RRESP_out), + .AXI_25_RVALID (AXI_25_RVALID_out), + .AXI_25_WREADY (AXI_25_WREADY_out), + .AXI_26_ARREADY (AXI_26_ARREADY_out), + .AXI_26_AWREADY (AXI_26_AWREADY_out), + .AXI_26_BID (AXI_26_BID_out), + .AXI_26_BRESP (AXI_26_BRESP_out), + .AXI_26_BVALID (AXI_26_BVALID_out), + .AXI_26_DFI_AW_AERR_N (AXI_26_DFI_AW_AERR_N_out), + .AXI_26_DFI_CLK_BUF (AXI_26_DFI_CLK_BUF_out), + .AXI_26_DFI_DBI_BYTE_DISABLE (AXI_26_DFI_DBI_BYTE_DISABLE_out), + .AXI_26_DFI_DW_RDDATA_DBI (AXI_26_DFI_DW_RDDATA_DBI_out), + .AXI_26_DFI_DW_RDDATA_DERR (AXI_26_DFI_DW_RDDATA_DERR_out), + .AXI_26_DFI_DW_RDDATA_VALID (AXI_26_DFI_DW_RDDATA_VALID_out), + .AXI_26_DFI_INIT_COMPLETE (AXI_26_DFI_INIT_COMPLETE_out), + .AXI_26_DFI_PHYUPD_REQ (AXI_26_DFI_PHYUPD_REQ_out), + .AXI_26_DFI_PHY_LP_STATE (AXI_26_DFI_PHY_LP_STATE_out), + .AXI_26_DFI_RST_N_BUF (AXI_26_DFI_RST_N_BUF_out), + .AXI_26_MC_STATUS (AXI_26_MC_STATUS_out), + .AXI_26_PHY_STATUS (AXI_26_PHY_STATUS_out), + .AXI_26_RDATA (AXI_26_RDATA_out), + .AXI_26_RDATA_PARITY (AXI_26_RDATA_PARITY_out), + .AXI_26_RID (AXI_26_RID_out), + .AXI_26_RLAST (AXI_26_RLAST_out), + .AXI_26_RRESP (AXI_26_RRESP_out), + .AXI_26_RVALID (AXI_26_RVALID_out), + .AXI_26_WREADY (AXI_26_WREADY_out), + .AXI_27_ARREADY (AXI_27_ARREADY_out), + .AXI_27_AWREADY (AXI_27_AWREADY_out), + .AXI_27_BID (AXI_27_BID_out), + .AXI_27_BRESP (AXI_27_BRESP_out), + .AXI_27_BVALID (AXI_27_BVALID_out), + .AXI_27_DFI_AW_AERR_N (AXI_27_DFI_AW_AERR_N_out), + .AXI_27_DFI_CLK_BUF (AXI_27_DFI_CLK_BUF_out), + .AXI_27_DFI_DBI_BYTE_DISABLE (AXI_27_DFI_DBI_BYTE_DISABLE_out), + .AXI_27_DFI_DW_RDDATA_DBI (AXI_27_DFI_DW_RDDATA_DBI_out), + .AXI_27_DFI_DW_RDDATA_DERR (AXI_27_DFI_DW_RDDATA_DERR_out), + .AXI_27_DFI_DW_RDDATA_VALID (AXI_27_DFI_DW_RDDATA_VALID_out), + .AXI_27_DFI_INIT_COMPLETE (AXI_27_DFI_INIT_COMPLETE_out), + .AXI_27_DFI_PHYUPD_REQ (AXI_27_DFI_PHYUPD_REQ_out), + .AXI_27_DFI_PHY_LP_STATE (AXI_27_DFI_PHY_LP_STATE_out), + .AXI_27_DFI_RST_N_BUF (AXI_27_DFI_RST_N_BUF_out), + .AXI_27_RDATA (AXI_27_RDATA_out), + .AXI_27_RDATA_PARITY (AXI_27_RDATA_PARITY_out), + .AXI_27_RID (AXI_27_RID_out), + .AXI_27_RLAST (AXI_27_RLAST_out), + .AXI_27_RRESP (AXI_27_RRESP_out), + .AXI_27_RVALID (AXI_27_RVALID_out), + .AXI_27_WREADY (AXI_27_WREADY_out), + .AXI_28_ARREADY (AXI_28_ARREADY_out), + .AXI_28_AWREADY (AXI_28_AWREADY_out), + .AXI_28_BID (AXI_28_BID_out), + .AXI_28_BRESP (AXI_28_BRESP_out), + .AXI_28_BVALID (AXI_28_BVALID_out), + .AXI_28_DFI_AW_AERR_N (AXI_28_DFI_AW_AERR_N_out), + .AXI_28_DFI_CLK_BUF (AXI_28_DFI_CLK_BUF_out), + .AXI_28_DFI_DBI_BYTE_DISABLE (AXI_28_DFI_DBI_BYTE_DISABLE_out), + .AXI_28_DFI_DW_RDDATA_DBI (AXI_28_DFI_DW_RDDATA_DBI_out), + .AXI_28_DFI_DW_RDDATA_DERR (AXI_28_DFI_DW_RDDATA_DERR_out), + .AXI_28_DFI_DW_RDDATA_VALID (AXI_28_DFI_DW_RDDATA_VALID_out), + .AXI_28_DFI_INIT_COMPLETE (AXI_28_DFI_INIT_COMPLETE_out), + .AXI_28_DFI_PHYUPD_REQ (AXI_28_DFI_PHYUPD_REQ_out), + .AXI_28_DFI_PHY_LP_STATE (AXI_28_DFI_PHY_LP_STATE_out), + .AXI_28_DFI_RST_N_BUF (AXI_28_DFI_RST_N_BUF_out), + .AXI_28_MC_STATUS (AXI_28_MC_STATUS_out), + .AXI_28_PHY_STATUS (AXI_28_PHY_STATUS_out), + .AXI_28_RDATA (AXI_28_RDATA_out), + .AXI_28_RDATA_PARITY (AXI_28_RDATA_PARITY_out), + .AXI_28_RID (AXI_28_RID_out), + .AXI_28_RLAST (AXI_28_RLAST_out), + .AXI_28_RRESP (AXI_28_RRESP_out), + .AXI_28_RVALID (AXI_28_RVALID_out), + .AXI_28_WREADY (AXI_28_WREADY_out), + .AXI_29_ARREADY (AXI_29_ARREADY_out), + .AXI_29_AWREADY (AXI_29_AWREADY_out), + .AXI_29_BID (AXI_29_BID_out), + .AXI_29_BRESP (AXI_29_BRESP_out), + .AXI_29_BVALID (AXI_29_BVALID_out), + .AXI_29_DFI_AW_AERR_N (AXI_29_DFI_AW_AERR_N_out), + .AXI_29_DFI_CLK_BUF (AXI_29_DFI_CLK_BUF_out), + .AXI_29_DFI_DBI_BYTE_DISABLE (AXI_29_DFI_DBI_BYTE_DISABLE_out), + .AXI_29_DFI_DW_RDDATA_DBI (AXI_29_DFI_DW_RDDATA_DBI_out), + .AXI_29_DFI_DW_RDDATA_DERR (AXI_29_DFI_DW_RDDATA_DERR_out), + .AXI_29_DFI_DW_RDDATA_VALID (AXI_29_DFI_DW_RDDATA_VALID_out), + .AXI_29_DFI_INIT_COMPLETE (AXI_29_DFI_INIT_COMPLETE_out), + .AXI_29_DFI_PHYUPD_REQ (AXI_29_DFI_PHYUPD_REQ_out), + .AXI_29_DFI_PHY_LP_STATE (AXI_29_DFI_PHY_LP_STATE_out), + .AXI_29_DFI_RST_N_BUF (AXI_29_DFI_RST_N_BUF_out), + .AXI_29_RDATA (AXI_29_RDATA_out), + .AXI_29_RDATA_PARITY (AXI_29_RDATA_PARITY_out), + .AXI_29_RID (AXI_29_RID_out), + .AXI_29_RLAST (AXI_29_RLAST_out), + .AXI_29_RRESP (AXI_29_RRESP_out), + .AXI_29_RVALID (AXI_29_RVALID_out), + .AXI_29_WREADY (AXI_29_WREADY_out), + .AXI_30_ARREADY (AXI_30_ARREADY_out), + .AXI_30_AWREADY (AXI_30_AWREADY_out), + .AXI_30_BID (AXI_30_BID_out), + .AXI_30_BRESP (AXI_30_BRESP_out), + .AXI_30_BVALID (AXI_30_BVALID_out), + .AXI_30_DFI_AW_AERR_N (AXI_30_DFI_AW_AERR_N_out), + .AXI_30_DFI_CLK_BUF (AXI_30_DFI_CLK_BUF_out), + .AXI_30_DFI_DBI_BYTE_DISABLE (AXI_30_DFI_DBI_BYTE_DISABLE_out), + .AXI_30_DFI_DW_RDDATA_DBI (AXI_30_DFI_DW_RDDATA_DBI_out), + .AXI_30_DFI_DW_RDDATA_DERR (AXI_30_DFI_DW_RDDATA_DERR_out), + .AXI_30_DFI_DW_RDDATA_VALID (AXI_30_DFI_DW_RDDATA_VALID_out), + .AXI_30_DFI_INIT_COMPLETE (AXI_30_DFI_INIT_COMPLETE_out), + .AXI_30_DFI_PHYUPD_REQ (AXI_30_DFI_PHYUPD_REQ_out), + .AXI_30_DFI_PHY_LP_STATE (AXI_30_DFI_PHY_LP_STATE_out), + .AXI_30_DFI_RST_N_BUF (AXI_30_DFI_RST_N_BUF_out), + .AXI_30_MC_STATUS (AXI_30_MC_STATUS_out), + .AXI_30_PHY_STATUS (AXI_30_PHY_STATUS_out), + .AXI_30_RDATA (AXI_30_RDATA_out), + .AXI_30_RDATA_PARITY (AXI_30_RDATA_PARITY_out), + .AXI_30_RID (AXI_30_RID_out), + .AXI_30_RLAST (AXI_30_RLAST_out), + .AXI_30_RRESP (AXI_30_RRESP_out), + .AXI_30_RVALID (AXI_30_RVALID_out), + .AXI_30_WREADY (AXI_30_WREADY_out), + .AXI_31_ARREADY (AXI_31_ARREADY_out), + .AXI_31_AWREADY (AXI_31_AWREADY_out), + .AXI_31_BID (AXI_31_BID_out), + .AXI_31_BRESP (AXI_31_BRESP_out), + .AXI_31_BVALID (AXI_31_BVALID_out), + .AXI_31_DFI_AW_AERR_N (AXI_31_DFI_AW_AERR_N_out), + .AXI_31_DFI_CLK_BUF (AXI_31_DFI_CLK_BUF_out), + .AXI_31_DFI_DBI_BYTE_DISABLE (AXI_31_DFI_DBI_BYTE_DISABLE_out), + .AXI_31_DFI_DW_RDDATA_DBI (AXI_31_DFI_DW_RDDATA_DBI_out), + .AXI_31_DFI_DW_RDDATA_DERR (AXI_31_DFI_DW_RDDATA_DERR_out), + .AXI_31_DFI_DW_RDDATA_VALID (AXI_31_DFI_DW_RDDATA_VALID_out), + .AXI_31_DFI_INIT_COMPLETE (AXI_31_DFI_INIT_COMPLETE_out), + .AXI_31_DFI_PHYUPD_REQ (AXI_31_DFI_PHYUPD_REQ_out), + .AXI_31_DFI_PHY_LP_STATE (AXI_31_DFI_PHY_LP_STATE_out), + .AXI_31_DFI_RST_N_BUF (AXI_31_DFI_RST_N_BUF_out), + .AXI_31_RDATA (AXI_31_RDATA_out), + .AXI_31_RDATA_PARITY (AXI_31_RDATA_PARITY_out), + .AXI_31_RID (AXI_31_RID_out), + .AXI_31_RLAST (AXI_31_RLAST_out), + .AXI_31_RRESP (AXI_31_RRESP_out), + .AXI_31_RVALID (AXI_31_RVALID_out), + .AXI_31_WREADY (AXI_31_WREADY_out), + .BLI_SCAN_OUT_00 (BLI_SCAN_OUT_00_out), + .BLI_SCAN_OUT_01 (BLI_SCAN_OUT_01_out), + .BLI_SCAN_OUT_02 (BLI_SCAN_OUT_02_out), + .BLI_SCAN_OUT_03 (BLI_SCAN_OUT_03_out), + .BLI_SCAN_OUT_04 (BLI_SCAN_OUT_04_out), + .BLI_SCAN_OUT_05 (BLI_SCAN_OUT_05_out), + .BLI_SCAN_OUT_06 (BLI_SCAN_OUT_06_out), + .BLI_SCAN_OUT_07 (BLI_SCAN_OUT_07_out), + .BLI_SCAN_OUT_08 (BLI_SCAN_OUT_08_out), + .BLI_SCAN_OUT_09 (BLI_SCAN_OUT_09_out), + .BLI_SCAN_OUT_10 (BLI_SCAN_OUT_10_out), + .BLI_SCAN_OUT_11 (BLI_SCAN_OUT_11_out), + .BLI_SCAN_OUT_12 (BLI_SCAN_OUT_12_out), + .BLI_SCAN_OUT_13 (BLI_SCAN_OUT_13_out), + .BLI_SCAN_OUT_14 (BLI_SCAN_OUT_14_out), + .BLI_SCAN_OUT_15 (BLI_SCAN_OUT_15_out), + .BLI_SCAN_OUT_16 (BLI_SCAN_OUT_16_out), + .BLI_SCAN_OUT_17 (BLI_SCAN_OUT_17_out), + .BLI_SCAN_OUT_18 (BLI_SCAN_OUT_18_out), + .BLI_SCAN_OUT_19 (BLI_SCAN_OUT_19_out), + .BLI_SCAN_OUT_20 (BLI_SCAN_OUT_20_out), + .BLI_SCAN_OUT_21 (BLI_SCAN_OUT_21_out), + .BLI_SCAN_OUT_22 (BLI_SCAN_OUT_22_out), + .BLI_SCAN_OUT_23 (BLI_SCAN_OUT_23_out), + .BLI_SCAN_OUT_24 (BLI_SCAN_OUT_24_out), + .BLI_SCAN_OUT_25 (BLI_SCAN_OUT_25_out), + .BLI_SCAN_OUT_26 (BLI_SCAN_OUT_26_out), + .BLI_SCAN_OUT_27 (BLI_SCAN_OUT_27_out), + .BLI_SCAN_OUT_28 (BLI_SCAN_OUT_28_out), + .BLI_SCAN_OUT_29 (BLI_SCAN_OUT_29_out), + .BLI_SCAN_OUT_30 (BLI_SCAN_OUT_30_out), + .BLI_SCAN_OUT_31 (BLI_SCAN_OUT_31_out), + .DBG_OUT_00 (DBG_OUT_00_out), + .DBG_OUT_01 (DBG_OUT_01_out), + .DBG_OUT_02 (DBG_OUT_02_out), + .DBG_OUT_03 (DBG_OUT_03_out), + .DBG_OUT_04 (DBG_OUT_04_out), + .DBG_OUT_05 (DBG_OUT_05_out), + .DBG_OUT_06 (DBG_OUT_06_out), + .DBG_OUT_07 (DBG_OUT_07_out), + .DBG_OUT_08 (DBG_OUT_08_out), + .DBG_OUT_09 (DBG_OUT_09_out), + .DBG_OUT_10 (DBG_OUT_10_out), + .DBG_OUT_11 (DBG_OUT_11_out), + .DBG_OUT_12 (DBG_OUT_12_out), + .DBG_OUT_13 (DBG_OUT_13_out), + .DBG_OUT_14 (DBG_OUT_14_out), + .DBG_OUT_15 (DBG_OUT_15_out), + .DBG_OUT_16 (DBG_OUT_16_out), + .DBG_OUT_17 (DBG_OUT_17_out), + .DBG_OUT_18 (DBG_OUT_18_out), + .DBG_OUT_19 (DBG_OUT_19_out), + .DBG_OUT_20 (DBG_OUT_20_out), + .DBG_OUT_21 (DBG_OUT_21_out), + .DBG_OUT_22 (DBG_OUT_22_out), + .DBG_OUT_23 (DBG_OUT_23_out), + .DBG_OUT_24 (DBG_OUT_24_out), + .DBG_OUT_25 (DBG_OUT_25_out), + .DBG_OUT_26 (DBG_OUT_26_out), + .DBG_OUT_27 (DBG_OUT_27_out), + .DBG_OUT_28 (DBG_OUT_28_out), + .DBG_OUT_29 (DBG_OUT_29_out), + .DBG_OUT_30 (DBG_OUT_30_out), + .DBG_OUT_31 (DBG_OUT_31_out), + .DLL_SCAN_OUT_00 (DLL_SCAN_OUT_00_out), + .DLL_SCAN_OUT_01 (DLL_SCAN_OUT_01_out), + .DRAM_0_STAT_CATTRIP (DRAM_0_STAT_CATTRIP_out), + .DRAM_0_STAT_TEMP (DRAM_0_STAT_TEMP_out), + .DRAM_1_STAT_CATTRIP (DRAM_1_STAT_CATTRIP_out), + .DRAM_1_STAT_TEMP (DRAM_1_STAT_TEMP_out), + .IO_SCAN_OUT_00 (IO_SCAN_OUT_00_out), + .IO_SCAN_OUT_01 (IO_SCAN_OUT_01_out), + .MC_SCAN_OUT_00 (MC_SCAN_OUT_00_out), + .MC_SCAN_OUT_01 (MC_SCAN_OUT_01_out), + .MC_SCAN_OUT_02 (MC_SCAN_OUT_02_out), + .MC_SCAN_OUT_03 (MC_SCAN_OUT_03_out), + .MC_SCAN_OUT_04 (MC_SCAN_OUT_04_out), + .MC_SCAN_OUT_05 (MC_SCAN_OUT_05_out), + .MC_SCAN_OUT_06 (MC_SCAN_OUT_06_out), + .MC_SCAN_OUT_07 (MC_SCAN_OUT_07_out), + .MC_SCAN_OUT_08 (MC_SCAN_OUT_08_out), + .MC_SCAN_OUT_09 (MC_SCAN_OUT_09_out), + .MC_SCAN_OUT_10 (MC_SCAN_OUT_10_out), + .MC_SCAN_OUT_11 (MC_SCAN_OUT_11_out), + .MC_SCAN_OUT_12 (MC_SCAN_OUT_12_out), + .MC_SCAN_OUT_13 (MC_SCAN_OUT_13_out), + .MC_SCAN_OUT_14 (MC_SCAN_OUT_14_out), + .MC_SCAN_OUT_15 (MC_SCAN_OUT_15_out), + .PHY_SCAN_OUT_00 (PHY_SCAN_OUT_00_out), + .PHY_SCAN_OUT_01 (PHY_SCAN_OUT_01_out), + .STATUS_00 (STATUS_00_out), + .STATUS_01 (STATUS_01_out), + .STATUS_02 (STATUS_02_out), + .STATUS_03 (STATUS_03_out), + .STATUS_04 (STATUS_04_out), + .STATUS_05 (STATUS_05_out), + .STATUS_06 (STATUS_06_out), + .STATUS_07 (STATUS_07_out), + .STATUS_08 (STATUS_08_out), + .STATUS_09 (STATUS_09_out), + .STATUS_10 (STATUS_10_out), + .STATUS_11 (STATUS_11_out), + .STATUS_12 (STATUS_12_out), + .STATUS_13 (STATUS_13_out), + .STATUS_14 (STATUS_14_out), + .STATUS_15 (STATUS_15_out), + .SW_SCAN_OUT_00 (SW_SCAN_OUT_00_out), + .SW_SCAN_OUT_01 (SW_SCAN_OUT_01_out), + .SW_SCAN_OUT_02 (SW_SCAN_OUT_02_out), + .SW_SCAN_OUT_03 (SW_SCAN_OUT_03_out), + .SW_SCAN_OUT_04 (SW_SCAN_OUT_04_out), + .SW_SCAN_OUT_05 (SW_SCAN_OUT_05_out), + .SW_SCAN_OUT_06 (SW_SCAN_OUT_06_out), + .SW_SCAN_OUT_07 (SW_SCAN_OUT_07_out), + .ANALOG_HBM_SEL_00 (ANALOG_HBM_SEL_00_in), + .ANALOG_HBM_SEL_01 (ANALOG_HBM_SEL_01_in), + .APB_0_PADDR (APB_0_PADDR_in), + .APB_0_PCLK (APB_0_PCLK_in), + .APB_0_PENABLE (APB_0_PENABLE_in), + .APB_0_PRESET_N (APB_0_PRESET_N_in), + .APB_0_PSEL (APB_0_PSEL_in), + .APB_0_PWDATA (APB_0_PWDATA_in), + .APB_0_PWRITE (APB_0_PWRITE_in), + .APB_1_PADDR (APB_1_PADDR_in), + .APB_1_PCLK (APB_1_PCLK_in), + .APB_1_PENABLE (APB_1_PENABLE_in), + .APB_1_PRESET_N (APB_1_PRESET_N_in), + .APB_1_PSEL (APB_1_PSEL_in), + .APB_1_PWDATA (APB_1_PWDATA_in), + .APB_1_PWRITE (APB_1_PWRITE_in), + .AXI_00_ACLK (AXI_00_ACLK_in), + .AXI_00_ARADDR (AXI_00_ARADDR_in), + .AXI_00_ARBURST (AXI_00_ARBURST_in), + .AXI_00_ARESET_N (AXI_00_ARESET_N_in), + .AXI_00_ARID (AXI_00_ARID_in), + .AXI_00_ARLEN (AXI_00_ARLEN_in), + .AXI_00_ARSIZE (AXI_00_ARSIZE_in), + .AXI_00_ARVALID (AXI_00_ARVALID_in), + .AXI_00_AWADDR (AXI_00_AWADDR_in), + .AXI_00_AWBURST (AXI_00_AWBURST_in), + .AXI_00_AWID (AXI_00_AWID_in), + .AXI_00_AWLEN (AXI_00_AWLEN_in), + .AXI_00_AWSIZE (AXI_00_AWSIZE_in), + .AXI_00_AWVALID (AXI_00_AWVALID_in), + .AXI_00_BREADY (AXI_00_BREADY_in), + .AXI_00_DFI_LP_PWR_X_REQ (AXI_00_DFI_LP_PWR_X_REQ_in), + .AXI_00_RREADY (AXI_00_RREADY_in), + .AXI_00_WDATA (AXI_00_WDATA_in), + .AXI_00_WDATA_PARITY (AXI_00_WDATA_PARITY_in), + .AXI_00_WLAST (AXI_00_WLAST_in), + .AXI_00_WSTRB (AXI_00_WSTRB_in), + .AXI_00_WVALID (AXI_00_WVALID_in), + .AXI_01_ACLK (AXI_01_ACLK_in), + .AXI_01_ARADDR (AXI_01_ARADDR_in), + .AXI_01_ARBURST (AXI_01_ARBURST_in), + .AXI_01_ARESET_N (AXI_01_ARESET_N_in), + .AXI_01_ARID (AXI_01_ARID_in), + .AXI_01_ARLEN (AXI_01_ARLEN_in), + .AXI_01_ARSIZE (AXI_01_ARSIZE_in), + .AXI_01_ARVALID (AXI_01_ARVALID_in), + .AXI_01_AWADDR (AXI_01_AWADDR_in), + .AXI_01_AWBURST (AXI_01_AWBURST_in), + .AXI_01_AWID (AXI_01_AWID_in), + .AXI_01_AWLEN (AXI_01_AWLEN_in), + .AXI_01_AWSIZE (AXI_01_AWSIZE_in), + .AXI_01_AWVALID (AXI_01_AWVALID_in), + .AXI_01_BREADY (AXI_01_BREADY_in), + .AXI_01_DFI_LP_PWR_X_REQ (AXI_01_DFI_LP_PWR_X_REQ_in), + .AXI_01_RREADY (AXI_01_RREADY_in), + .AXI_01_WDATA (AXI_01_WDATA_in), + .AXI_01_WDATA_PARITY (AXI_01_WDATA_PARITY_in), + .AXI_01_WLAST (AXI_01_WLAST_in), + .AXI_01_WSTRB (AXI_01_WSTRB_in), + .AXI_01_WVALID (AXI_01_WVALID_in), + .AXI_02_ACLK (AXI_02_ACLK_in), + .AXI_02_ARADDR (AXI_02_ARADDR_in), + .AXI_02_ARBURST (AXI_02_ARBURST_in), + .AXI_02_ARESET_N (AXI_02_ARESET_N_in), + .AXI_02_ARID (AXI_02_ARID_in), + .AXI_02_ARLEN (AXI_02_ARLEN_in), + .AXI_02_ARSIZE (AXI_02_ARSIZE_in), + .AXI_02_ARVALID (AXI_02_ARVALID_in), + .AXI_02_AWADDR (AXI_02_AWADDR_in), + .AXI_02_AWBURST (AXI_02_AWBURST_in), + .AXI_02_AWID (AXI_02_AWID_in), + .AXI_02_AWLEN (AXI_02_AWLEN_in), + .AXI_02_AWSIZE (AXI_02_AWSIZE_in), + .AXI_02_AWVALID (AXI_02_AWVALID_in), + .AXI_02_BREADY (AXI_02_BREADY_in), + .AXI_02_DFI_LP_PWR_X_REQ (AXI_02_DFI_LP_PWR_X_REQ_in), + .AXI_02_RREADY (AXI_02_RREADY_in), + .AXI_02_WDATA (AXI_02_WDATA_in), + .AXI_02_WDATA_PARITY (AXI_02_WDATA_PARITY_in), + .AXI_02_WLAST (AXI_02_WLAST_in), + .AXI_02_WSTRB (AXI_02_WSTRB_in), + .AXI_02_WVALID (AXI_02_WVALID_in), + .AXI_03_ACLK (AXI_03_ACLK_in), + .AXI_03_ARADDR (AXI_03_ARADDR_in), + .AXI_03_ARBURST (AXI_03_ARBURST_in), + .AXI_03_ARESET_N (AXI_03_ARESET_N_in), + .AXI_03_ARID (AXI_03_ARID_in), + .AXI_03_ARLEN (AXI_03_ARLEN_in), + .AXI_03_ARSIZE (AXI_03_ARSIZE_in), + .AXI_03_ARVALID (AXI_03_ARVALID_in), + .AXI_03_AWADDR (AXI_03_AWADDR_in), + .AXI_03_AWBURST (AXI_03_AWBURST_in), + .AXI_03_AWID (AXI_03_AWID_in), + .AXI_03_AWLEN (AXI_03_AWLEN_in), + .AXI_03_AWSIZE (AXI_03_AWSIZE_in), + .AXI_03_AWVALID (AXI_03_AWVALID_in), + .AXI_03_BREADY (AXI_03_BREADY_in), + .AXI_03_DFI_LP_PWR_X_REQ (AXI_03_DFI_LP_PWR_X_REQ_in), + .AXI_03_RREADY (AXI_03_RREADY_in), + .AXI_03_WDATA (AXI_03_WDATA_in), + .AXI_03_WDATA_PARITY (AXI_03_WDATA_PARITY_in), + .AXI_03_WLAST (AXI_03_WLAST_in), + .AXI_03_WSTRB (AXI_03_WSTRB_in), + .AXI_03_WVALID (AXI_03_WVALID_in), + .AXI_04_ACLK (AXI_04_ACLK_in), + .AXI_04_ARADDR (AXI_04_ARADDR_in), + .AXI_04_ARBURST (AXI_04_ARBURST_in), + .AXI_04_ARESET_N (AXI_04_ARESET_N_in), + .AXI_04_ARID (AXI_04_ARID_in), + .AXI_04_ARLEN (AXI_04_ARLEN_in), + .AXI_04_ARSIZE (AXI_04_ARSIZE_in), + .AXI_04_ARVALID (AXI_04_ARVALID_in), + .AXI_04_AWADDR (AXI_04_AWADDR_in), + .AXI_04_AWBURST (AXI_04_AWBURST_in), + .AXI_04_AWID (AXI_04_AWID_in), + .AXI_04_AWLEN (AXI_04_AWLEN_in), + .AXI_04_AWSIZE (AXI_04_AWSIZE_in), + .AXI_04_AWVALID (AXI_04_AWVALID_in), + .AXI_04_BREADY (AXI_04_BREADY_in), + .AXI_04_DFI_LP_PWR_X_REQ (AXI_04_DFI_LP_PWR_X_REQ_in), + .AXI_04_RREADY (AXI_04_RREADY_in), + .AXI_04_WDATA (AXI_04_WDATA_in), + .AXI_04_WDATA_PARITY (AXI_04_WDATA_PARITY_in), + .AXI_04_WLAST (AXI_04_WLAST_in), + .AXI_04_WSTRB (AXI_04_WSTRB_in), + .AXI_04_WVALID (AXI_04_WVALID_in), + .AXI_05_ACLK (AXI_05_ACLK_in), + .AXI_05_ARADDR (AXI_05_ARADDR_in), + .AXI_05_ARBURST (AXI_05_ARBURST_in), + .AXI_05_ARESET_N (AXI_05_ARESET_N_in), + .AXI_05_ARID (AXI_05_ARID_in), + .AXI_05_ARLEN (AXI_05_ARLEN_in), + .AXI_05_ARSIZE (AXI_05_ARSIZE_in), + .AXI_05_ARVALID (AXI_05_ARVALID_in), + .AXI_05_AWADDR (AXI_05_AWADDR_in), + .AXI_05_AWBURST (AXI_05_AWBURST_in), + .AXI_05_AWID (AXI_05_AWID_in), + .AXI_05_AWLEN (AXI_05_AWLEN_in), + .AXI_05_AWSIZE (AXI_05_AWSIZE_in), + .AXI_05_AWVALID (AXI_05_AWVALID_in), + .AXI_05_BREADY (AXI_05_BREADY_in), + .AXI_05_DFI_LP_PWR_X_REQ (AXI_05_DFI_LP_PWR_X_REQ_in), + .AXI_05_RREADY (AXI_05_RREADY_in), + .AXI_05_WDATA (AXI_05_WDATA_in), + .AXI_05_WDATA_PARITY (AXI_05_WDATA_PARITY_in), + .AXI_05_WLAST (AXI_05_WLAST_in), + .AXI_05_WSTRB (AXI_05_WSTRB_in), + .AXI_05_WVALID (AXI_05_WVALID_in), + .AXI_06_ACLK (AXI_06_ACLK_in), + .AXI_06_ARADDR (AXI_06_ARADDR_in), + .AXI_06_ARBURST (AXI_06_ARBURST_in), + .AXI_06_ARESET_N (AXI_06_ARESET_N_in), + .AXI_06_ARID (AXI_06_ARID_in), + .AXI_06_ARLEN (AXI_06_ARLEN_in), + .AXI_06_ARSIZE (AXI_06_ARSIZE_in), + .AXI_06_ARVALID (AXI_06_ARVALID_in), + .AXI_06_AWADDR (AXI_06_AWADDR_in), + .AXI_06_AWBURST (AXI_06_AWBURST_in), + .AXI_06_AWID (AXI_06_AWID_in), + .AXI_06_AWLEN (AXI_06_AWLEN_in), + .AXI_06_AWSIZE (AXI_06_AWSIZE_in), + .AXI_06_AWVALID (AXI_06_AWVALID_in), + .AXI_06_BREADY (AXI_06_BREADY_in), + .AXI_06_DFI_LP_PWR_X_REQ (AXI_06_DFI_LP_PWR_X_REQ_in), + .AXI_06_RREADY (AXI_06_RREADY_in), + .AXI_06_WDATA (AXI_06_WDATA_in), + .AXI_06_WDATA_PARITY (AXI_06_WDATA_PARITY_in), + .AXI_06_WLAST (AXI_06_WLAST_in), + .AXI_06_WSTRB (AXI_06_WSTRB_in), + .AXI_06_WVALID (AXI_06_WVALID_in), + .AXI_07_ACLK (AXI_07_ACLK_in), + .AXI_07_ARADDR (AXI_07_ARADDR_in), + .AXI_07_ARBURST (AXI_07_ARBURST_in), + .AXI_07_ARESET_N (AXI_07_ARESET_N_in), + .AXI_07_ARID (AXI_07_ARID_in), + .AXI_07_ARLEN (AXI_07_ARLEN_in), + .AXI_07_ARSIZE (AXI_07_ARSIZE_in), + .AXI_07_ARVALID (AXI_07_ARVALID_in), + .AXI_07_AWADDR (AXI_07_AWADDR_in), + .AXI_07_AWBURST (AXI_07_AWBURST_in), + .AXI_07_AWID (AXI_07_AWID_in), + .AXI_07_AWLEN (AXI_07_AWLEN_in), + .AXI_07_AWSIZE (AXI_07_AWSIZE_in), + .AXI_07_AWVALID (AXI_07_AWVALID_in), + .AXI_07_BREADY (AXI_07_BREADY_in), + .AXI_07_DFI_LP_PWR_X_REQ (AXI_07_DFI_LP_PWR_X_REQ_in), + .AXI_07_RREADY (AXI_07_RREADY_in), + .AXI_07_WDATA (AXI_07_WDATA_in), + .AXI_07_WDATA_PARITY (AXI_07_WDATA_PARITY_in), + .AXI_07_WLAST (AXI_07_WLAST_in), + .AXI_07_WSTRB (AXI_07_WSTRB_in), + .AXI_07_WVALID (AXI_07_WVALID_in), + .AXI_08_ACLK (AXI_08_ACLK_in), + .AXI_08_ARADDR (AXI_08_ARADDR_in), + .AXI_08_ARBURST (AXI_08_ARBURST_in), + .AXI_08_ARESET_N (AXI_08_ARESET_N_in), + .AXI_08_ARID (AXI_08_ARID_in), + .AXI_08_ARLEN (AXI_08_ARLEN_in), + .AXI_08_ARSIZE (AXI_08_ARSIZE_in), + .AXI_08_ARVALID (AXI_08_ARVALID_in), + .AXI_08_AWADDR (AXI_08_AWADDR_in), + .AXI_08_AWBURST (AXI_08_AWBURST_in), + .AXI_08_AWID (AXI_08_AWID_in), + .AXI_08_AWLEN (AXI_08_AWLEN_in), + .AXI_08_AWSIZE (AXI_08_AWSIZE_in), + .AXI_08_AWVALID (AXI_08_AWVALID_in), + .AXI_08_BREADY (AXI_08_BREADY_in), + .AXI_08_DFI_LP_PWR_X_REQ (AXI_08_DFI_LP_PWR_X_REQ_in), + .AXI_08_RREADY (AXI_08_RREADY_in), + .AXI_08_WDATA (AXI_08_WDATA_in), + .AXI_08_WDATA_PARITY (AXI_08_WDATA_PARITY_in), + .AXI_08_WLAST (AXI_08_WLAST_in), + .AXI_08_WSTRB (AXI_08_WSTRB_in), + .AXI_08_WVALID (AXI_08_WVALID_in), + .AXI_09_ACLK (AXI_09_ACLK_in), + .AXI_09_ARADDR (AXI_09_ARADDR_in), + .AXI_09_ARBURST (AXI_09_ARBURST_in), + .AXI_09_ARESET_N (AXI_09_ARESET_N_in), + .AXI_09_ARID (AXI_09_ARID_in), + .AXI_09_ARLEN (AXI_09_ARLEN_in), + .AXI_09_ARSIZE (AXI_09_ARSIZE_in), + .AXI_09_ARVALID (AXI_09_ARVALID_in), + .AXI_09_AWADDR (AXI_09_AWADDR_in), + .AXI_09_AWBURST (AXI_09_AWBURST_in), + .AXI_09_AWID (AXI_09_AWID_in), + .AXI_09_AWLEN (AXI_09_AWLEN_in), + .AXI_09_AWSIZE (AXI_09_AWSIZE_in), + .AXI_09_AWVALID (AXI_09_AWVALID_in), + .AXI_09_BREADY (AXI_09_BREADY_in), + .AXI_09_DFI_LP_PWR_X_REQ (AXI_09_DFI_LP_PWR_X_REQ_in), + .AXI_09_RREADY (AXI_09_RREADY_in), + .AXI_09_WDATA (AXI_09_WDATA_in), + .AXI_09_WDATA_PARITY (AXI_09_WDATA_PARITY_in), + .AXI_09_WLAST (AXI_09_WLAST_in), + .AXI_09_WSTRB (AXI_09_WSTRB_in), + .AXI_09_WVALID (AXI_09_WVALID_in), + .AXI_10_ACLK (AXI_10_ACLK_in), + .AXI_10_ARADDR (AXI_10_ARADDR_in), + .AXI_10_ARBURST (AXI_10_ARBURST_in), + .AXI_10_ARESET_N (AXI_10_ARESET_N_in), + .AXI_10_ARID (AXI_10_ARID_in), + .AXI_10_ARLEN (AXI_10_ARLEN_in), + .AXI_10_ARSIZE (AXI_10_ARSIZE_in), + .AXI_10_ARVALID (AXI_10_ARVALID_in), + .AXI_10_AWADDR (AXI_10_AWADDR_in), + .AXI_10_AWBURST (AXI_10_AWBURST_in), + .AXI_10_AWID (AXI_10_AWID_in), + .AXI_10_AWLEN (AXI_10_AWLEN_in), + .AXI_10_AWSIZE (AXI_10_AWSIZE_in), + .AXI_10_AWVALID (AXI_10_AWVALID_in), + .AXI_10_BREADY (AXI_10_BREADY_in), + .AXI_10_DFI_LP_PWR_X_REQ (AXI_10_DFI_LP_PWR_X_REQ_in), + .AXI_10_RREADY (AXI_10_RREADY_in), + .AXI_10_WDATA (AXI_10_WDATA_in), + .AXI_10_WDATA_PARITY (AXI_10_WDATA_PARITY_in), + .AXI_10_WLAST (AXI_10_WLAST_in), + .AXI_10_WSTRB (AXI_10_WSTRB_in), + .AXI_10_WVALID (AXI_10_WVALID_in), + .AXI_11_ACLK (AXI_11_ACLK_in), + .AXI_11_ARADDR (AXI_11_ARADDR_in), + .AXI_11_ARBURST (AXI_11_ARBURST_in), + .AXI_11_ARESET_N (AXI_11_ARESET_N_in), + .AXI_11_ARID (AXI_11_ARID_in), + .AXI_11_ARLEN (AXI_11_ARLEN_in), + .AXI_11_ARSIZE (AXI_11_ARSIZE_in), + .AXI_11_ARVALID (AXI_11_ARVALID_in), + .AXI_11_AWADDR (AXI_11_AWADDR_in), + .AXI_11_AWBURST (AXI_11_AWBURST_in), + .AXI_11_AWID (AXI_11_AWID_in), + .AXI_11_AWLEN (AXI_11_AWLEN_in), + .AXI_11_AWSIZE (AXI_11_AWSIZE_in), + .AXI_11_AWVALID (AXI_11_AWVALID_in), + .AXI_11_BREADY (AXI_11_BREADY_in), + .AXI_11_DFI_LP_PWR_X_REQ (AXI_11_DFI_LP_PWR_X_REQ_in), + .AXI_11_RREADY (AXI_11_RREADY_in), + .AXI_11_WDATA (AXI_11_WDATA_in), + .AXI_11_WDATA_PARITY (AXI_11_WDATA_PARITY_in), + .AXI_11_WLAST (AXI_11_WLAST_in), + .AXI_11_WSTRB (AXI_11_WSTRB_in), + .AXI_11_WVALID (AXI_11_WVALID_in), + .AXI_12_ACLK (AXI_12_ACLK_in), + .AXI_12_ARADDR (AXI_12_ARADDR_in), + .AXI_12_ARBURST (AXI_12_ARBURST_in), + .AXI_12_ARESET_N (AXI_12_ARESET_N_in), + .AXI_12_ARID (AXI_12_ARID_in), + .AXI_12_ARLEN (AXI_12_ARLEN_in), + .AXI_12_ARSIZE (AXI_12_ARSIZE_in), + .AXI_12_ARVALID (AXI_12_ARVALID_in), + .AXI_12_AWADDR (AXI_12_AWADDR_in), + .AXI_12_AWBURST (AXI_12_AWBURST_in), + .AXI_12_AWID (AXI_12_AWID_in), + .AXI_12_AWLEN (AXI_12_AWLEN_in), + .AXI_12_AWSIZE (AXI_12_AWSIZE_in), + .AXI_12_AWVALID (AXI_12_AWVALID_in), + .AXI_12_BREADY (AXI_12_BREADY_in), + .AXI_12_DFI_LP_PWR_X_REQ (AXI_12_DFI_LP_PWR_X_REQ_in), + .AXI_12_RREADY (AXI_12_RREADY_in), + .AXI_12_WDATA (AXI_12_WDATA_in), + .AXI_12_WDATA_PARITY (AXI_12_WDATA_PARITY_in), + .AXI_12_WLAST (AXI_12_WLAST_in), + .AXI_12_WSTRB (AXI_12_WSTRB_in), + .AXI_12_WVALID (AXI_12_WVALID_in), + .AXI_13_ACLK (AXI_13_ACLK_in), + .AXI_13_ARADDR (AXI_13_ARADDR_in), + .AXI_13_ARBURST (AXI_13_ARBURST_in), + .AXI_13_ARESET_N (AXI_13_ARESET_N_in), + .AXI_13_ARID (AXI_13_ARID_in), + .AXI_13_ARLEN (AXI_13_ARLEN_in), + .AXI_13_ARSIZE (AXI_13_ARSIZE_in), + .AXI_13_ARVALID (AXI_13_ARVALID_in), + .AXI_13_AWADDR (AXI_13_AWADDR_in), + .AXI_13_AWBURST (AXI_13_AWBURST_in), + .AXI_13_AWID (AXI_13_AWID_in), + .AXI_13_AWLEN (AXI_13_AWLEN_in), + .AXI_13_AWSIZE (AXI_13_AWSIZE_in), + .AXI_13_AWVALID (AXI_13_AWVALID_in), + .AXI_13_BREADY (AXI_13_BREADY_in), + .AXI_13_DFI_LP_PWR_X_REQ (AXI_13_DFI_LP_PWR_X_REQ_in), + .AXI_13_RREADY (AXI_13_RREADY_in), + .AXI_13_WDATA (AXI_13_WDATA_in), + .AXI_13_WDATA_PARITY (AXI_13_WDATA_PARITY_in), + .AXI_13_WLAST (AXI_13_WLAST_in), + .AXI_13_WSTRB (AXI_13_WSTRB_in), + .AXI_13_WVALID (AXI_13_WVALID_in), + .AXI_14_ACLK (AXI_14_ACLK_in), + .AXI_14_ARADDR (AXI_14_ARADDR_in), + .AXI_14_ARBURST (AXI_14_ARBURST_in), + .AXI_14_ARESET_N (AXI_14_ARESET_N_in), + .AXI_14_ARID (AXI_14_ARID_in), + .AXI_14_ARLEN (AXI_14_ARLEN_in), + .AXI_14_ARSIZE (AXI_14_ARSIZE_in), + .AXI_14_ARVALID (AXI_14_ARVALID_in), + .AXI_14_AWADDR (AXI_14_AWADDR_in), + .AXI_14_AWBURST (AXI_14_AWBURST_in), + .AXI_14_AWID (AXI_14_AWID_in), + .AXI_14_AWLEN (AXI_14_AWLEN_in), + .AXI_14_AWSIZE (AXI_14_AWSIZE_in), + .AXI_14_AWVALID (AXI_14_AWVALID_in), + .AXI_14_BREADY (AXI_14_BREADY_in), + .AXI_14_DFI_LP_PWR_X_REQ (AXI_14_DFI_LP_PWR_X_REQ_in), + .AXI_14_RREADY (AXI_14_RREADY_in), + .AXI_14_WDATA (AXI_14_WDATA_in), + .AXI_14_WDATA_PARITY (AXI_14_WDATA_PARITY_in), + .AXI_14_WLAST (AXI_14_WLAST_in), + .AXI_14_WSTRB (AXI_14_WSTRB_in), + .AXI_14_WVALID (AXI_14_WVALID_in), + .AXI_15_ACLK (AXI_15_ACLK_in), + .AXI_15_ARADDR (AXI_15_ARADDR_in), + .AXI_15_ARBURST (AXI_15_ARBURST_in), + .AXI_15_ARESET_N (AXI_15_ARESET_N_in), + .AXI_15_ARID (AXI_15_ARID_in), + .AXI_15_ARLEN (AXI_15_ARLEN_in), + .AXI_15_ARSIZE (AXI_15_ARSIZE_in), + .AXI_15_ARVALID (AXI_15_ARVALID_in), + .AXI_15_AWADDR (AXI_15_AWADDR_in), + .AXI_15_AWBURST (AXI_15_AWBURST_in), + .AXI_15_AWID (AXI_15_AWID_in), + .AXI_15_AWLEN (AXI_15_AWLEN_in), + .AXI_15_AWSIZE (AXI_15_AWSIZE_in), + .AXI_15_AWVALID (AXI_15_AWVALID_in), + .AXI_15_BREADY (AXI_15_BREADY_in), + .AXI_15_DFI_LP_PWR_X_REQ (AXI_15_DFI_LP_PWR_X_REQ_in), + .AXI_15_RREADY (AXI_15_RREADY_in), + .AXI_15_WDATA (AXI_15_WDATA_in), + .AXI_15_WDATA_PARITY (AXI_15_WDATA_PARITY_in), + .AXI_15_WLAST (AXI_15_WLAST_in), + .AXI_15_WSTRB (AXI_15_WSTRB_in), + .AXI_15_WVALID (AXI_15_WVALID_in), + .AXI_16_ACLK (AXI_16_ACLK_in), + .AXI_16_ARADDR (AXI_16_ARADDR_in), + .AXI_16_ARBURST (AXI_16_ARBURST_in), + .AXI_16_ARESET_N (AXI_16_ARESET_N_in), + .AXI_16_ARID (AXI_16_ARID_in), + .AXI_16_ARLEN (AXI_16_ARLEN_in), + .AXI_16_ARSIZE (AXI_16_ARSIZE_in), + .AXI_16_ARVALID (AXI_16_ARVALID_in), + .AXI_16_AWADDR (AXI_16_AWADDR_in), + .AXI_16_AWBURST (AXI_16_AWBURST_in), + .AXI_16_AWID (AXI_16_AWID_in), + .AXI_16_AWLEN (AXI_16_AWLEN_in), + .AXI_16_AWSIZE (AXI_16_AWSIZE_in), + .AXI_16_AWVALID (AXI_16_AWVALID_in), + .AXI_16_BREADY (AXI_16_BREADY_in), + .AXI_16_DFI_LP_PWR_X_REQ (AXI_16_DFI_LP_PWR_X_REQ_in), + .AXI_16_RREADY (AXI_16_RREADY_in), + .AXI_16_WDATA (AXI_16_WDATA_in), + .AXI_16_WDATA_PARITY (AXI_16_WDATA_PARITY_in), + .AXI_16_WLAST (AXI_16_WLAST_in), + .AXI_16_WSTRB (AXI_16_WSTRB_in), + .AXI_16_WVALID (AXI_16_WVALID_in), + .AXI_17_ACLK (AXI_17_ACLK_in), + .AXI_17_ARADDR (AXI_17_ARADDR_in), + .AXI_17_ARBURST (AXI_17_ARBURST_in), + .AXI_17_ARESET_N (AXI_17_ARESET_N_in), + .AXI_17_ARID (AXI_17_ARID_in), + .AXI_17_ARLEN (AXI_17_ARLEN_in), + .AXI_17_ARSIZE (AXI_17_ARSIZE_in), + .AXI_17_ARVALID (AXI_17_ARVALID_in), + .AXI_17_AWADDR (AXI_17_AWADDR_in), + .AXI_17_AWBURST (AXI_17_AWBURST_in), + .AXI_17_AWID (AXI_17_AWID_in), + .AXI_17_AWLEN (AXI_17_AWLEN_in), + .AXI_17_AWSIZE (AXI_17_AWSIZE_in), + .AXI_17_AWVALID (AXI_17_AWVALID_in), + .AXI_17_BREADY (AXI_17_BREADY_in), + .AXI_17_DFI_LP_PWR_X_REQ (AXI_17_DFI_LP_PWR_X_REQ_in), + .AXI_17_RREADY (AXI_17_RREADY_in), + .AXI_17_WDATA (AXI_17_WDATA_in), + .AXI_17_WDATA_PARITY (AXI_17_WDATA_PARITY_in), + .AXI_17_WLAST (AXI_17_WLAST_in), + .AXI_17_WSTRB (AXI_17_WSTRB_in), + .AXI_17_WVALID (AXI_17_WVALID_in), + .AXI_18_ACLK (AXI_18_ACLK_in), + .AXI_18_ARADDR (AXI_18_ARADDR_in), + .AXI_18_ARBURST (AXI_18_ARBURST_in), + .AXI_18_ARESET_N (AXI_18_ARESET_N_in), + .AXI_18_ARID (AXI_18_ARID_in), + .AXI_18_ARLEN (AXI_18_ARLEN_in), + .AXI_18_ARSIZE (AXI_18_ARSIZE_in), + .AXI_18_ARVALID (AXI_18_ARVALID_in), + .AXI_18_AWADDR (AXI_18_AWADDR_in), + .AXI_18_AWBURST (AXI_18_AWBURST_in), + .AXI_18_AWID (AXI_18_AWID_in), + .AXI_18_AWLEN (AXI_18_AWLEN_in), + .AXI_18_AWSIZE (AXI_18_AWSIZE_in), + .AXI_18_AWVALID (AXI_18_AWVALID_in), + .AXI_18_BREADY (AXI_18_BREADY_in), + .AXI_18_DFI_LP_PWR_X_REQ (AXI_18_DFI_LP_PWR_X_REQ_in), + .AXI_18_RREADY (AXI_18_RREADY_in), + .AXI_18_WDATA (AXI_18_WDATA_in), + .AXI_18_WDATA_PARITY (AXI_18_WDATA_PARITY_in), + .AXI_18_WLAST (AXI_18_WLAST_in), + .AXI_18_WSTRB (AXI_18_WSTRB_in), + .AXI_18_WVALID (AXI_18_WVALID_in), + .AXI_19_ACLK (AXI_19_ACLK_in), + .AXI_19_ARADDR (AXI_19_ARADDR_in), + .AXI_19_ARBURST (AXI_19_ARBURST_in), + .AXI_19_ARESET_N (AXI_19_ARESET_N_in), + .AXI_19_ARID (AXI_19_ARID_in), + .AXI_19_ARLEN (AXI_19_ARLEN_in), + .AXI_19_ARSIZE (AXI_19_ARSIZE_in), + .AXI_19_ARVALID (AXI_19_ARVALID_in), + .AXI_19_AWADDR (AXI_19_AWADDR_in), + .AXI_19_AWBURST (AXI_19_AWBURST_in), + .AXI_19_AWID (AXI_19_AWID_in), + .AXI_19_AWLEN (AXI_19_AWLEN_in), + .AXI_19_AWSIZE (AXI_19_AWSIZE_in), + .AXI_19_AWVALID (AXI_19_AWVALID_in), + .AXI_19_BREADY (AXI_19_BREADY_in), + .AXI_19_DFI_LP_PWR_X_REQ (AXI_19_DFI_LP_PWR_X_REQ_in), + .AXI_19_RREADY (AXI_19_RREADY_in), + .AXI_19_WDATA (AXI_19_WDATA_in), + .AXI_19_WDATA_PARITY (AXI_19_WDATA_PARITY_in), + .AXI_19_WLAST (AXI_19_WLAST_in), + .AXI_19_WSTRB (AXI_19_WSTRB_in), + .AXI_19_WVALID (AXI_19_WVALID_in), + .AXI_20_ACLK (AXI_20_ACLK_in), + .AXI_20_ARADDR (AXI_20_ARADDR_in), + .AXI_20_ARBURST (AXI_20_ARBURST_in), + .AXI_20_ARESET_N (AXI_20_ARESET_N_in), + .AXI_20_ARID (AXI_20_ARID_in), + .AXI_20_ARLEN (AXI_20_ARLEN_in), + .AXI_20_ARSIZE (AXI_20_ARSIZE_in), + .AXI_20_ARVALID (AXI_20_ARVALID_in), + .AXI_20_AWADDR (AXI_20_AWADDR_in), + .AXI_20_AWBURST (AXI_20_AWBURST_in), + .AXI_20_AWID (AXI_20_AWID_in), + .AXI_20_AWLEN (AXI_20_AWLEN_in), + .AXI_20_AWSIZE (AXI_20_AWSIZE_in), + .AXI_20_AWVALID (AXI_20_AWVALID_in), + .AXI_20_BREADY (AXI_20_BREADY_in), + .AXI_20_DFI_LP_PWR_X_REQ (AXI_20_DFI_LP_PWR_X_REQ_in), + .AXI_20_RREADY (AXI_20_RREADY_in), + .AXI_20_WDATA (AXI_20_WDATA_in), + .AXI_20_WDATA_PARITY (AXI_20_WDATA_PARITY_in), + .AXI_20_WLAST (AXI_20_WLAST_in), + .AXI_20_WSTRB (AXI_20_WSTRB_in), + .AXI_20_WVALID (AXI_20_WVALID_in), + .AXI_21_ACLK (AXI_21_ACLK_in), + .AXI_21_ARADDR (AXI_21_ARADDR_in), + .AXI_21_ARBURST (AXI_21_ARBURST_in), + .AXI_21_ARESET_N (AXI_21_ARESET_N_in), + .AXI_21_ARID (AXI_21_ARID_in), + .AXI_21_ARLEN (AXI_21_ARLEN_in), + .AXI_21_ARSIZE (AXI_21_ARSIZE_in), + .AXI_21_ARVALID (AXI_21_ARVALID_in), + .AXI_21_AWADDR (AXI_21_AWADDR_in), + .AXI_21_AWBURST (AXI_21_AWBURST_in), + .AXI_21_AWID (AXI_21_AWID_in), + .AXI_21_AWLEN (AXI_21_AWLEN_in), + .AXI_21_AWSIZE (AXI_21_AWSIZE_in), + .AXI_21_AWVALID (AXI_21_AWVALID_in), + .AXI_21_BREADY (AXI_21_BREADY_in), + .AXI_21_DFI_LP_PWR_X_REQ (AXI_21_DFI_LP_PWR_X_REQ_in), + .AXI_21_RREADY (AXI_21_RREADY_in), + .AXI_21_WDATA (AXI_21_WDATA_in), + .AXI_21_WDATA_PARITY (AXI_21_WDATA_PARITY_in), + .AXI_21_WLAST (AXI_21_WLAST_in), + .AXI_21_WSTRB (AXI_21_WSTRB_in), + .AXI_21_WVALID (AXI_21_WVALID_in), + .AXI_22_ACLK (AXI_22_ACLK_in), + .AXI_22_ARADDR (AXI_22_ARADDR_in), + .AXI_22_ARBURST (AXI_22_ARBURST_in), + .AXI_22_ARESET_N (AXI_22_ARESET_N_in), + .AXI_22_ARID (AXI_22_ARID_in), + .AXI_22_ARLEN (AXI_22_ARLEN_in), + .AXI_22_ARSIZE (AXI_22_ARSIZE_in), + .AXI_22_ARVALID (AXI_22_ARVALID_in), + .AXI_22_AWADDR (AXI_22_AWADDR_in), + .AXI_22_AWBURST (AXI_22_AWBURST_in), + .AXI_22_AWID (AXI_22_AWID_in), + .AXI_22_AWLEN (AXI_22_AWLEN_in), + .AXI_22_AWSIZE (AXI_22_AWSIZE_in), + .AXI_22_AWVALID (AXI_22_AWVALID_in), + .AXI_22_BREADY (AXI_22_BREADY_in), + .AXI_22_DFI_LP_PWR_X_REQ (AXI_22_DFI_LP_PWR_X_REQ_in), + .AXI_22_RREADY (AXI_22_RREADY_in), + .AXI_22_WDATA (AXI_22_WDATA_in), + .AXI_22_WDATA_PARITY (AXI_22_WDATA_PARITY_in), + .AXI_22_WLAST (AXI_22_WLAST_in), + .AXI_22_WSTRB (AXI_22_WSTRB_in), + .AXI_22_WVALID (AXI_22_WVALID_in), + .AXI_23_ACLK (AXI_23_ACLK_in), + .AXI_23_ARADDR (AXI_23_ARADDR_in), + .AXI_23_ARBURST (AXI_23_ARBURST_in), + .AXI_23_ARESET_N (AXI_23_ARESET_N_in), + .AXI_23_ARID (AXI_23_ARID_in), + .AXI_23_ARLEN (AXI_23_ARLEN_in), + .AXI_23_ARSIZE (AXI_23_ARSIZE_in), + .AXI_23_ARVALID (AXI_23_ARVALID_in), + .AXI_23_AWADDR (AXI_23_AWADDR_in), + .AXI_23_AWBURST (AXI_23_AWBURST_in), + .AXI_23_AWID (AXI_23_AWID_in), + .AXI_23_AWLEN (AXI_23_AWLEN_in), + .AXI_23_AWSIZE (AXI_23_AWSIZE_in), + .AXI_23_AWVALID (AXI_23_AWVALID_in), + .AXI_23_BREADY (AXI_23_BREADY_in), + .AXI_23_DFI_LP_PWR_X_REQ (AXI_23_DFI_LP_PWR_X_REQ_in), + .AXI_23_RREADY (AXI_23_RREADY_in), + .AXI_23_WDATA (AXI_23_WDATA_in), + .AXI_23_WDATA_PARITY (AXI_23_WDATA_PARITY_in), + .AXI_23_WLAST (AXI_23_WLAST_in), + .AXI_23_WSTRB (AXI_23_WSTRB_in), + .AXI_23_WVALID (AXI_23_WVALID_in), + .AXI_24_ACLK (AXI_24_ACLK_in), + .AXI_24_ARADDR (AXI_24_ARADDR_in), + .AXI_24_ARBURST (AXI_24_ARBURST_in), + .AXI_24_ARESET_N (AXI_24_ARESET_N_in), + .AXI_24_ARID (AXI_24_ARID_in), + .AXI_24_ARLEN (AXI_24_ARLEN_in), + .AXI_24_ARSIZE (AXI_24_ARSIZE_in), + .AXI_24_ARVALID (AXI_24_ARVALID_in), + .AXI_24_AWADDR (AXI_24_AWADDR_in), + .AXI_24_AWBURST (AXI_24_AWBURST_in), + .AXI_24_AWID (AXI_24_AWID_in), + .AXI_24_AWLEN (AXI_24_AWLEN_in), + .AXI_24_AWSIZE (AXI_24_AWSIZE_in), + .AXI_24_AWVALID (AXI_24_AWVALID_in), + .AXI_24_BREADY (AXI_24_BREADY_in), + .AXI_24_DFI_LP_PWR_X_REQ (AXI_24_DFI_LP_PWR_X_REQ_in), + .AXI_24_RREADY (AXI_24_RREADY_in), + .AXI_24_WDATA (AXI_24_WDATA_in), + .AXI_24_WDATA_PARITY (AXI_24_WDATA_PARITY_in), + .AXI_24_WLAST (AXI_24_WLAST_in), + .AXI_24_WSTRB (AXI_24_WSTRB_in), + .AXI_24_WVALID (AXI_24_WVALID_in), + .AXI_25_ACLK (AXI_25_ACLK_in), + .AXI_25_ARADDR (AXI_25_ARADDR_in), + .AXI_25_ARBURST (AXI_25_ARBURST_in), + .AXI_25_ARESET_N (AXI_25_ARESET_N_in), + .AXI_25_ARID (AXI_25_ARID_in), + .AXI_25_ARLEN (AXI_25_ARLEN_in), + .AXI_25_ARSIZE (AXI_25_ARSIZE_in), + .AXI_25_ARVALID (AXI_25_ARVALID_in), + .AXI_25_AWADDR (AXI_25_AWADDR_in), + .AXI_25_AWBURST (AXI_25_AWBURST_in), + .AXI_25_AWID (AXI_25_AWID_in), + .AXI_25_AWLEN (AXI_25_AWLEN_in), + .AXI_25_AWSIZE (AXI_25_AWSIZE_in), + .AXI_25_AWVALID (AXI_25_AWVALID_in), + .AXI_25_BREADY (AXI_25_BREADY_in), + .AXI_25_DFI_LP_PWR_X_REQ (AXI_25_DFI_LP_PWR_X_REQ_in), + .AXI_25_RREADY (AXI_25_RREADY_in), + .AXI_25_WDATA (AXI_25_WDATA_in), + .AXI_25_WDATA_PARITY (AXI_25_WDATA_PARITY_in), + .AXI_25_WLAST (AXI_25_WLAST_in), + .AXI_25_WSTRB (AXI_25_WSTRB_in), + .AXI_25_WVALID (AXI_25_WVALID_in), + .AXI_26_ACLK (AXI_26_ACLK_in), + .AXI_26_ARADDR (AXI_26_ARADDR_in), + .AXI_26_ARBURST (AXI_26_ARBURST_in), + .AXI_26_ARESET_N (AXI_26_ARESET_N_in), + .AXI_26_ARID (AXI_26_ARID_in), + .AXI_26_ARLEN (AXI_26_ARLEN_in), + .AXI_26_ARSIZE (AXI_26_ARSIZE_in), + .AXI_26_ARVALID (AXI_26_ARVALID_in), + .AXI_26_AWADDR (AXI_26_AWADDR_in), + .AXI_26_AWBURST (AXI_26_AWBURST_in), + .AXI_26_AWID (AXI_26_AWID_in), + .AXI_26_AWLEN (AXI_26_AWLEN_in), + .AXI_26_AWSIZE (AXI_26_AWSIZE_in), + .AXI_26_AWVALID (AXI_26_AWVALID_in), + .AXI_26_BREADY (AXI_26_BREADY_in), + .AXI_26_DFI_LP_PWR_X_REQ (AXI_26_DFI_LP_PWR_X_REQ_in), + .AXI_26_RREADY (AXI_26_RREADY_in), + .AXI_26_WDATA (AXI_26_WDATA_in), + .AXI_26_WDATA_PARITY (AXI_26_WDATA_PARITY_in), + .AXI_26_WLAST (AXI_26_WLAST_in), + .AXI_26_WSTRB (AXI_26_WSTRB_in), + .AXI_26_WVALID (AXI_26_WVALID_in), + .AXI_27_ACLK (AXI_27_ACLK_in), + .AXI_27_ARADDR (AXI_27_ARADDR_in), + .AXI_27_ARBURST (AXI_27_ARBURST_in), + .AXI_27_ARESET_N (AXI_27_ARESET_N_in), + .AXI_27_ARID (AXI_27_ARID_in), + .AXI_27_ARLEN (AXI_27_ARLEN_in), + .AXI_27_ARSIZE (AXI_27_ARSIZE_in), + .AXI_27_ARVALID (AXI_27_ARVALID_in), + .AXI_27_AWADDR (AXI_27_AWADDR_in), + .AXI_27_AWBURST (AXI_27_AWBURST_in), + .AXI_27_AWID (AXI_27_AWID_in), + .AXI_27_AWLEN (AXI_27_AWLEN_in), + .AXI_27_AWSIZE (AXI_27_AWSIZE_in), + .AXI_27_AWVALID (AXI_27_AWVALID_in), + .AXI_27_BREADY (AXI_27_BREADY_in), + .AXI_27_DFI_LP_PWR_X_REQ (AXI_27_DFI_LP_PWR_X_REQ_in), + .AXI_27_RREADY (AXI_27_RREADY_in), + .AXI_27_WDATA (AXI_27_WDATA_in), + .AXI_27_WDATA_PARITY (AXI_27_WDATA_PARITY_in), + .AXI_27_WLAST (AXI_27_WLAST_in), + .AXI_27_WSTRB (AXI_27_WSTRB_in), + .AXI_27_WVALID (AXI_27_WVALID_in), + .AXI_28_ACLK (AXI_28_ACLK_in), + .AXI_28_ARADDR (AXI_28_ARADDR_in), + .AXI_28_ARBURST (AXI_28_ARBURST_in), + .AXI_28_ARESET_N (AXI_28_ARESET_N_in), + .AXI_28_ARID (AXI_28_ARID_in), + .AXI_28_ARLEN (AXI_28_ARLEN_in), + .AXI_28_ARSIZE (AXI_28_ARSIZE_in), + .AXI_28_ARVALID (AXI_28_ARVALID_in), + .AXI_28_AWADDR (AXI_28_AWADDR_in), + .AXI_28_AWBURST (AXI_28_AWBURST_in), + .AXI_28_AWID (AXI_28_AWID_in), + .AXI_28_AWLEN (AXI_28_AWLEN_in), + .AXI_28_AWSIZE (AXI_28_AWSIZE_in), + .AXI_28_AWVALID (AXI_28_AWVALID_in), + .AXI_28_BREADY (AXI_28_BREADY_in), + .AXI_28_DFI_LP_PWR_X_REQ (AXI_28_DFI_LP_PWR_X_REQ_in), + .AXI_28_RREADY (AXI_28_RREADY_in), + .AXI_28_WDATA (AXI_28_WDATA_in), + .AXI_28_WDATA_PARITY (AXI_28_WDATA_PARITY_in), + .AXI_28_WLAST (AXI_28_WLAST_in), + .AXI_28_WSTRB (AXI_28_WSTRB_in), + .AXI_28_WVALID (AXI_28_WVALID_in), + .AXI_29_ACLK (AXI_29_ACLK_in), + .AXI_29_ARADDR (AXI_29_ARADDR_in), + .AXI_29_ARBURST (AXI_29_ARBURST_in), + .AXI_29_ARESET_N (AXI_29_ARESET_N_in), + .AXI_29_ARID (AXI_29_ARID_in), + .AXI_29_ARLEN (AXI_29_ARLEN_in), + .AXI_29_ARSIZE (AXI_29_ARSIZE_in), + .AXI_29_ARVALID (AXI_29_ARVALID_in), + .AXI_29_AWADDR (AXI_29_AWADDR_in), + .AXI_29_AWBURST (AXI_29_AWBURST_in), + .AXI_29_AWID (AXI_29_AWID_in), + .AXI_29_AWLEN (AXI_29_AWLEN_in), + .AXI_29_AWSIZE (AXI_29_AWSIZE_in), + .AXI_29_AWVALID (AXI_29_AWVALID_in), + .AXI_29_BREADY (AXI_29_BREADY_in), + .AXI_29_DFI_LP_PWR_X_REQ (AXI_29_DFI_LP_PWR_X_REQ_in), + .AXI_29_RREADY (AXI_29_RREADY_in), + .AXI_29_WDATA (AXI_29_WDATA_in), + .AXI_29_WDATA_PARITY (AXI_29_WDATA_PARITY_in), + .AXI_29_WLAST (AXI_29_WLAST_in), + .AXI_29_WSTRB (AXI_29_WSTRB_in), + .AXI_29_WVALID (AXI_29_WVALID_in), + .AXI_30_ACLK (AXI_30_ACLK_in), + .AXI_30_ARADDR (AXI_30_ARADDR_in), + .AXI_30_ARBURST (AXI_30_ARBURST_in), + .AXI_30_ARESET_N (AXI_30_ARESET_N_in), + .AXI_30_ARID (AXI_30_ARID_in), + .AXI_30_ARLEN (AXI_30_ARLEN_in), + .AXI_30_ARSIZE (AXI_30_ARSIZE_in), + .AXI_30_ARVALID (AXI_30_ARVALID_in), + .AXI_30_AWADDR (AXI_30_AWADDR_in), + .AXI_30_AWBURST (AXI_30_AWBURST_in), + .AXI_30_AWID (AXI_30_AWID_in), + .AXI_30_AWLEN (AXI_30_AWLEN_in), + .AXI_30_AWSIZE (AXI_30_AWSIZE_in), + .AXI_30_AWVALID (AXI_30_AWVALID_in), + .AXI_30_BREADY (AXI_30_BREADY_in), + .AXI_30_DFI_LP_PWR_X_REQ (AXI_30_DFI_LP_PWR_X_REQ_in), + .AXI_30_RREADY (AXI_30_RREADY_in), + .AXI_30_WDATA (AXI_30_WDATA_in), + .AXI_30_WDATA_PARITY (AXI_30_WDATA_PARITY_in), + .AXI_30_WLAST (AXI_30_WLAST_in), + .AXI_30_WSTRB (AXI_30_WSTRB_in), + .AXI_30_WVALID (AXI_30_WVALID_in), + .AXI_31_ACLK (AXI_31_ACLK_in), + .AXI_31_ARADDR (AXI_31_ARADDR_in), + .AXI_31_ARBURST (AXI_31_ARBURST_in), + .AXI_31_ARESET_N (AXI_31_ARESET_N_in), + .AXI_31_ARID (AXI_31_ARID_in), + .AXI_31_ARLEN (AXI_31_ARLEN_in), + .AXI_31_ARSIZE (AXI_31_ARSIZE_in), + .AXI_31_ARVALID (AXI_31_ARVALID_in), + .AXI_31_AWADDR (AXI_31_AWADDR_in), + .AXI_31_AWBURST (AXI_31_AWBURST_in), + .AXI_31_AWID (AXI_31_AWID_in), + .AXI_31_AWLEN (AXI_31_AWLEN_in), + .AXI_31_AWSIZE (AXI_31_AWSIZE_in), + .AXI_31_AWVALID (AXI_31_AWVALID_in), + .AXI_31_BREADY (AXI_31_BREADY_in), + .AXI_31_DFI_LP_PWR_X_REQ (AXI_31_DFI_LP_PWR_X_REQ_in), + .AXI_31_RREADY (AXI_31_RREADY_in), + .AXI_31_WDATA (AXI_31_WDATA_in), + .AXI_31_WDATA_PARITY (AXI_31_WDATA_PARITY_in), + .AXI_31_WLAST (AXI_31_WLAST_in), + .AXI_31_WSTRB (AXI_31_WSTRB_in), + .AXI_31_WVALID (AXI_31_WVALID_in), + .BLI_SCAN_ENABLE_00 (BLI_SCAN_ENABLE_00_in), + .BLI_SCAN_ENABLE_01 (BLI_SCAN_ENABLE_01_in), + .BLI_SCAN_ENABLE_02 (BLI_SCAN_ENABLE_02_in), + .BLI_SCAN_ENABLE_03 (BLI_SCAN_ENABLE_03_in), + .BLI_SCAN_ENABLE_04 (BLI_SCAN_ENABLE_04_in), + .BLI_SCAN_ENABLE_05 (BLI_SCAN_ENABLE_05_in), + .BLI_SCAN_ENABLE_06 (BLI_SCAN_ENABLE_06_in), + .BLI_SCAN_ENABLE_07 (BLI_SCAN_ENABLE_07_in), + .BLI_SCAN_ENABLE_08 (BLI_SCAN_ENABLE_08_in), + .BLI_SCAN_ENABLE_09 (BLI_SCAN_ENABLE_09_in), + .BLI_SCAN_ENABLE_10 (BLI_SCAN_ENABLE_10_in), + .BLI_SCAN_ENABLE_11 (BLI_SCAN_ENABLE_11_in), + .BLI_SCAN_ENABLE_12 (BLI_SCAN_ENABLE_12_in), + .BLI_SCAN_ENABLE_13 (BLI_SCAN_ENABLE_13_in), + .BLI_SCAN_ENABLE_14 (BLI_SCAN_ENABLE_14_in), + .BLI_SCAN_ENABLE_15 (BLI_SCAN_ENABLE_15_in), + .BLI_SCAN_ENABLE_16 (BLI_SCAN_ENABLE_16_in), + .BLI_SCAN_ENABLE_17 (BLI_SCAN_ENABLE_17_in), + .BLI_SCAN_ENABLE_18 (BLI_SCAN_ENABLE_18_in), + .BLI_SCAN_ENABLE_19 (BLI_SCAN_ENABLE_19_in), + .BLI_SCAN_ENABLE_20 (BLI_SCAN_ENABLE_20_in), + .BLI_SCAN_ENABLE_21 (BLI_SCAN_ENABLE_21_in), + .BLI_SCAN_ENABLE_22 (BLI_SCAN_ENABLE_22_in), + .BLI_SCAN_ENABLE_23 (BLI_SCAN_ENABLE_23_in), + .BLI_SCAN_ENABLE_24 (BLI_SCAN_ENABLE_24_in), + .BLI_SCAN_ENABLE_25 (BLI_SCAN_ENABLE_25_in), + .BLI_SCAN_ENABLE_26 (BLI_SCAN_ENABLE_26_in), + .BLI_SCAN_ENABLE_27 (BLI_SCAN_ENABLE_27_in), + .BLI_SCAN_ENABLE_28 (BLI_SCAN_ENABLE_28_in), + .BLI_SCAN_ENABLE_29 (BLI_SCAN_ENABLE_29_in), + .BLI_SCAN_ENABLE_30 (BLI_SCAN_ENABLE_30_in), + .BLI_SCAN_ENABLE_31 (BLI_SCAN_ENABLE_31_in), + .BLI_SCAN_IN_00 (BLI_SCAN_IN_00_in), + .BLI_SCAN_IN_01 (BLI_SCAN_IN_01_in), + .BLI_SCAN_IN_02 (BLI_SCAN_IN_02_in), + .BLI_SCAN_IN_03 (BLI_SCAN_IN_03_in), + .BLI_SCAN_IN_04 (BLI_SCAN_IN_04_in), + .BLI_SCAN_IN_05 (BLI_SCAN_IN_05_in), + .BLI_SCAN_IN_06 (BLI_SCAN_IN_06_in), + .BLI_SCAN_IN_07 (BLI_SCAN_IN_07_in), + .BLI_SCAN_IN_08 (BLI_SCAN_IN_08_in), + .BLI_SCAN_IN_09 (BLI_SCAN_IN_09_in), + .BLI_SCAN_IN_10 (BLI_SCAN_IN_10_in), + .BLI_SCAN_IN_11 (BLI_SCAN_IN_11_in), + .BLI_SCAN_IN_12 (BLI_SCAN_IN_12_in), + .BLI_SCAN_IN_13 (BLI_SCAN_IN_13_in), + .BLI_SCAN_IN_14 (BLI_SCAN_IN_14_in), + .BLI_SCAN_IN_15 (BLI_SCAN_IN_15_in), + .BLI_SCAN_IN_16 (BLI_SCAN_IN_16_in), + .BLI_SCAN_IN_17 (BLI_SCAN_IN_17_in), + .BLI_SCAN_IN_18 (BLI_SCAN_IN_18_in), + .BLI_SCAN_IN_19 (BLI_SCAN_IN_19_in), + .BLI_SCAN_IN_20 (BLI_SCAN_IN_20_in), + .BLI_SCAN_IN_21 (BLI_SCAN_IN_21_in), + .BLI_SCAN_IN_22 (BLI_SCAN_IN_22_in), + .BLI_SCAN_IN_23 (BLI_SCAN_IN_23_in), + .BLI_SCAN_IN_24 (BLI_SCAN_IN_24_in), + .BLI_SCAN_IN_25 (BLI_SCAN_IN_25_in), + .BLI_SCAN_IN_26 (BLI_SCAN_IN_26_in), + .BLI_SCAN_IN_27 (BLI_SCAN_IN_27_in), + .BLI_SCAN_IN_28 (BLI_SCAN_IN_28_in), + .BLI_SCAN_IN_29 (BLI_SCAN_IN_29_in), + .BLI_SCAN_IN_30 (BLI_SCAN_IN_30_in), + .BLI_SCAN_IN_31 (BLI_SCAN_IN_31_in), + .BSCAN_DRCK_0 (BSCAN_DRCK_0_in), + .BSCAN_DRCK_1 (BSCAN_DRCK_1_in), + .BSCAN_TCK_0 (BSCAN_TCK_0_in), + .BSCAN_TCK_1 (BSCAN_TCK_1_in), + .DBG_IN_00 (DBG_IN_00_in), + .DBG_IN_01 (DBG_IN_01_in), + .DBG_IN_02 (DBG_IN_02_in), + .DBG_IN_03 (DBG_IN_03_in), + .DBG_IN_04 (DBG_IN_04_in), + .DBG_IN_05 (DBG_IN_05_in), + .DBG_IN_06 (DBG_IN_06_in), + .DBG_IN_07 (DBG_IN_07_in), + .DBG_IN_08 (DBG_IN_08_in), + .DBG_IN_09 (DBG_IN_09_in), + .DBG_IN_10 (DBG_IN_10_in), + .DBG_IN_11 (DBG_IN_11_in), + .DBG_IN_12 (DBG_IN_12_in), + .DBG_IN_13 (DBG_IN_13_in), + .DBG_IN_14 (DBG_IN_14_in), + .DBG_IN_15 (DBG_IN_15_in), + .DBG_IN_16 (DBG_IN_16_in), + .DBG_IN_17 (DBG_IN_17_in), + .DBG_IN_18 (DBG_IN_18_in), + .DBG_IN_19 (DBG_IN_19_in), + .DBG_IN_20 (DBG_IN_20_in), + .DBG_IN_21 (DBG_IN_21_in), + .DBG_IN_22 (DBG_IN_22_in), + .DBG_IN_23 (DBG_IN_23_in), + .DBG_IN_24 (DBG_IN_24_in), + .DBG_IN_25 (DBG_IN_25_in), + .DBG_IN_26 (DBG_IN_26_in), + .DBG_IN_27 (DBG_IN_27_in), + .DBG_IN_28 (DBG_IN_28_in), + .DBG_IN_29 (DBG_IN_29_in), + .DBG_IN_30 (DBG_IN_30_in), + .DBG_IN_31 (DBG_IN_31_in), + .DLL_SCAN_CK_00 (DLL_SCAN_CK_00_in), + .DLL_SCAN_CK_01 (DLL_SCAN_CK_01_in), + .DLL_SCAN_ENABLE_00 (DLL_SCAN_ENABLE_00_in), + .DLL_SCAN_ENABLE_01 (DLL_SCAN_ENABLE_01_in), + .DLL_SCAN_IN_00 (DLL_SCAN_IN_00_in), + .DLL_SCAN_IN_01 (DLL_SCAN_IN_01_in), + .DLL_SCAN_MODE_00 (DLL_SCAN_MODE_00_in), + .DLL_SCAN_MODE_01 (DLL_SCAN_MODE_01_in), + .DLL_SCAN_RST_N_00 (DLL_SCAN_RST_N_00_in), + .DLL_SCAN_RST_N_01 (DLL_SCAN_RST_N_01_in), + .HBM_REF_CLK_0 (HBM_REF_CLK_0_in), + .HBM_REF_CLK_1 (HBM_REF_CLK_1_in), + .IO_SCAN_CK_00 (IO_SCAN_CK_00_in), + .IO_SCAN_CK_01 (IO_SCAN_CK_01_in), + .IO_SCAN_ENABLE_00 (IO_SCAN_ENABLE_00_in), + .IO_SCAN_ENABLE_01 (IO_SCAN_ENABLE_01_in), + .IO_SCAN_IN_00 (IO_SCAN_IN_00_in), + .IO_SCAN_IN_01 (IO_SCAN_IN_01_in), + .IO_SCAN_MODE_00 (IO_SCAN_MODE_00_in), + .IO_SCAN_MODE_01 (IO_SCAN_MODE_01_in), + .IO_SCAN_RST_N_00 (IO_SCAN_RST_N_00_in), + .IO_SCAN_RST_N_01 (IO_SCAN_RST_N_01_in), + .MBIST_EN_00 (MBIST_EN_00_in), + .MBIST_EN_01 (MBIST_EN_01_in), + .MBIST_EN_02 (MBIST_EN_02_in), + .MBIST_EN_03 (MBIST_EN_03_in), + .MBIST_EN_04 (MBIST_EN_04_in), + .MBIST_EN_05 (MBIST_EN_05_in), + .MBIST_EN_06 (MBIST_EN_06_in), + .MBIST_EN_07 (MBIST_EN_07_in), + .MBIST_EN_08 (MBIST_EN_08_in), + .MBIST_EN_09 (MBIST_EN_09_in), + .MBIST_EN_10 (MBIST_EN_10_in), + .MBIST_EN_11 (MBIST_EN_11_in), + .MBIST_EN_12 (MBIST_EN_12_in), + .MBIST_EN_13 (MBIST_EN_13_in), + .MBIST_EN_14 (MBIST_EN_14_in), + .MBIST_EN_15 (MBIST_EN_15_in), + .MC_SCAN_CK_00 (MC_SCAN_CK_00_in), + .MC_SCAN_CK_01 (MC_SCAN_CK_01_in), + .MC_SCAN_CK_02 (MC_SCAN_CK_02_in), + .MC_SCAN_CK_03 (MC_SCAN_CK_03_in), + .MC_SCAN_CK_04 (MC_SCAN_CK_04_in), + .MC_SCAN_CK_05 (MC_SCAN_CK_05_in), + .MC_SCAN_CK_06 (MC_SCAN_CK_06_in), + .MC_SCAN_CK_07 (MC_SCAN_CK_07_in), + .MC_SCAN_CK_08 (MC_SCAN_CK_08_in), + .MC_SCAN_CK_09 (MC_SCAN_CK_09_in), + .MC_SCAN_CK_10 (MC_SCAN_CK_10_in), + .MC_SCAN_CK_11 (MC_SCAN_CK_11_in), + .MC_SCAN_CK_12 (MC_SCAN_CK_12_in), + .MC_SCAN_CK_13 (MC_SCAN_CK_13_in), + .MC_SCAN_CK_14 (MC_SCAN_CK_14_in), + .MC_SCAN_CK_15 (MC_SCAN_CK_15_in), + .MC_SCAN_ENABLE_00 (MC_SCAN_ENABLE_00_in), + .MC_SCAN_ENABLE_01 (MC_SCAN_ENABLE_01_in), + .MC_SCAN_ENABLE_02 (MC_SCAN_ENABLE_02_in), + .MC_SCAN_ENABLE_03 (MC_SCAN_ENABLE_03_in), + .MC_SCAN_ENABLE_04 (MC_SCAN_ENABLE_04_in), + .MC_SCAN_ENABLE_05 (MC_SCAN_ENABLE_05_in), + .MC_SCAN_ENABLE_06 (MC_SCAN_ENABLE_06_in), + .MC_SCAN_ENABLE_07 (MC_SCAN_ENABLE_07_in), + .MC_SCAN_ENABLE_08 (MC_SCAN_ENABLE_08_in), + .MC_SCAN_ENABLE_09 (MC_SCAN_ENABLE_09_in), + .MC_SCAN_ENABLE_10 (MC_SCAN_ENABLE_10_in), + .MC_SCAN_ENABLE_11 (MC_SCAN_ENABLE_11_in), + .MC_SCAN_ENABLE_12 (MC_SCAN_ENABLE_12_in), + .MC_SCAN_ENABLE_13 (MC_SCAN_ENABLE_13_in), + .MC_SCAN_ENABLE_14 (MC_SCAN_ENABLE_14_in), + .MC_SCAN_ENABLE_15 (MC_SCAN_ENABLE_15_in), + .MC_SCAN_IN_00 (MC_SCAN_IN_00_in), + .MC_SCAN_IN_01 (MC_SCAN_IN_01_in), + .MC_SCAN_IN_02 (MC_SCAN_IN_02_in), + .MC_SCAN_IN_03 (MC_SCAN_IN_03_in), + .MC_SCAN_IN_04 (MC_SCAN_IN_04_in), + .MC_SCAN_IN_05 (MC_SCAN_IN_05_in), + .MC_SCAN_IN_06 (MC_SCAN_IN_06_in), + .MC_SCAN_IN_07 (MC_SCAN_IN_07_in), + .MC_SCAN_IN_08 (MC_SCAN_IN_08_in), + .MC_SCAN_IN_09 (MC_SCAN_IN_09_in), + .MC_SCAN_IN_10 (MC_SCAN_IN_10_in), + .MC_SCAN_IN_11 (MC_SCAN_IN_11_in), + .MC_SCAN_IN_12 (MC_SCAN_IN_12_in), + .MC_SCAN_IN_13 (MC_SCAN_IN_13_in), + .MC_SCAN_IN_14 (MC_SCAN_IN_14_in), + .MC_SCAN_IN_15 (MC_SCAN_IN_15_in), + .MC_SCAN_MODE_00 (MC_SCAN_MODE_00_in), + .MC_SCAN_MODE_01 (MC_SCAN_MODE_01_in), + .MC_SCAN_MODE_02 (MC_SCAN_MODE_02_in), + .MC_SCAN_MODE_03 (MC_SCAN_MODE_03_in), + .MC_SCAN_MODE_04 (MC_SCAN_MODE_04_in), + .MC_SCAN_MODE_05 (MC_SCAN_MODE_05_in), + .MC_SCAN_MODE_06 (MC_SCAN_MODE_06_in), + .MC_SCAN_MODE_07 (MC_SCAN_MODE_07_in), + .MC_SCAN_MODE_08 (MC_SCAN_MODE_08_in), + .MC_SCAN_MODE_09 (MC_SCAN_MODE_09_in), + .MC_SCAN_MODE_10 (MC_SCAN_MODE_10_in), + .MC_SCAN_MODE_11 (MC_SCAN_MODE_11_in), + .MC_SCAN_MODE_12 (MC_SCAN_MODE_12_in), + .MC_SCAN_MODE_13 (MC_SCAN_MODE_13_in), + .MC_SCAN_MODE_14 (MC_SCAN_MODE_14_in), + .MC_SCAN_MODE_15 (MC_SCAN_MODE_15_in), + .MC_SCAN_RST_N_00 (MC_SCAN_RST_N_00_in), + .MC_SCAN_RST_N_01 (MC_SCAN_RST_N_01_in), + .MC_SCAN_RST_N_02 (MC_SCAN_RST_N_02_in), + .MC_SCAN_RST_N_03 (MC_SCAN_RST_N_03_in), + .MC_SCAN_RST_N_04 (MC_SCAN_RST_N_04_in), + .MC_SCAN_RST_N_05 (MC_SCAN_RST_N_05_in), + .MC_SCAN_RST_N_06 (MC_SCAN_RST_N_06_in), + .MC_SCAN_RST_N_07 (MC_SCAN_RST_N_07_in), + .MC_SCAN_RST_N_08 (MC_SCAN_RST_N_08_in), + .MC_SCAN_RST_N_09 (MC_SCAN_RST_N_09_in), + .MC_SCAN_RST_N_10 (MC_SCAN_RST_N_10_in), + .MC_SCAN_RST_N_11 (MC_SCAN_RST_N_11_in), + .MC_SCAN_RST_N_12 (MC_SCAN_RST_N_12_in), + .MC_SCAN_RST_N_13 (MC_SCAN_RST_N_13_in), + .MC_SCAN_RST_N_14 (MC_SCAN_RST_N_14_in), + .MC_SCAN_RST_N_15 (MC_SCAN_RST_N_15_in), + .PHY_SCAN_CK_00 (PHY_SCAN_CK_00_in), + .PHY_SCAN_CK_01 (PHY_SCAN_CK_01_in), + .PHY_SCAN_ENABLE_00 (PHY_SCAN_ENABLE_00_in), + .PHY_SCAN_ENABLE_01 (PHY_SCAN_ENABLE_01_in), + .PHY_SCAN_IN_00 (PHY_SCAN_IN_00_in), + .PHY_SCAN_IN_01 (PHY_SCAN_IN_01_in), + .PHY_SCAN_MODE_00 (PHY_SCAN_MODE_00_in), + .PHY_SCAN_MODE_01 (PHY_SCAN_MODE_01_in), + .PHY_SCAN_RST_N_00 (PHY_SCAN_RST_N_00_in), + .PHY_SCAN_RST_N_01 (PHY_SCAN_RST_N_01_in), + .SW_SCAN_CK_00 (SW_SCAN_CK_00_in), + .SW_SCAN_CK_01 (SW_SCAN_CK_01_in), + .SW_SCAN_ENABLE_00 (SW_SCAN_ENABLE_00_in), + .SW_SCAN_ENABLE_01 (SW_SCAN_ENABLE_01_in), + .SW_SCAN_IN_00 (SW_SCAN_IN_00_in), + .SW_SCAN_IN_01 (SW_SCAN_IN_01_in), + .SW_SCAN_IN_02 (SW_SCAN_IN_02_in), + .SW_SCAN_IN_03 (SW_SCAN_IN_03_in), + .SW_SCAN_IN_04 (SW_SCAN_IN_04_in), + .SW_SCAN_IN_05 (SW_SCAN_IN_05_in), + .SW_SCAN_IN_06 (SW_SCAN_IN_06_in), + .SW_SCAN_IN_07 (SW_SCAN_IN_07_in), + .SW_SCAN_MODE_00 (SW_SCAN_MODE_00_in), + .SW_SCAN_MODE_01 (SW_SCAN_MODE_01_in), + .SW_SCAN_RST_N_00 (SW_SCAN_RST_N_00_in), + .SW_SCAN_RST_N_01 (SW_SCAN_RST_N_01_in), + .GSR (glblGSR) +); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HPIO_VREF.v b/verilog/src/unisims/HPIO_VREF.v new file mode 100644 index 0000000..5331d5d --- /dev/null +++ b/verilog/src/unisims/HPIO_VREF.v @@ -0,0 +1,127 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : HPIO_VREF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine +module HPIO_VREF #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter VREF_CNTR = "OFF" +)( + output VREF, + + input [6:0] FABRIC_VREF_TUNE +); + +// define constants + localparam MODULE_NAME = "HPIO_VREF"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam VREF_CNTR_FABRIC_RANGE1 = 1; + localparam VREF_CNTR_FABRIC_RANGE2 = 2; + localparam VREF_CNTR_OFF = 0; + + localparam [104:1] VREF_CNTR_REG = VREF_CNTR; + + wire [1:0] VREF_CNTR_BIN; + + tri0 glblGSR = glbl.GSR; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + reg trig_attr = 1'b0; +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire VREF_out = 1'b1; + + wire VREF_delay; + + wire [6:0] FABRIC_VREF_TUNE_in; + + wire [6:0] FABRIC_VREF_TUNE_delay; + + + assign #(out_delay) VREF = VREF_delay; + + +// inputs with no timing checks + + assign #(in_delay) FABRIC_VREF_TUNE_delay = FABRIC_VREF_TUNE; + + assign VREF_delay = VREF_out; + + assign FABRIC_VREF_TUNE_in = FABRIC_VREF_TUNE_delay; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((VREF_CNTR_REG != "OFF") && + (VREF_CNTR_REG != "FABRIC_RANGE1") && + (VREF_CNTR_REG != "FABRIC_RANGE2"))) begin + $display("Error: [Unisim %s-101] VREF_CNTR attribute is set to %s. Legal values for this attribute are OFF, FABRIC_RANGE1 or FABRIC_RANGE2. Instance: %m", MODULE_NAME, VREF_CNTR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign VREF_CNTR_BIN = + (VREF_CNTR_REG == "OFF") ? VREF_CNTR_OFF : + (VREF_CNTR_REG == "FABRIC_RANGE1") ? VREF_CNTR_FABRIC_RANGE1 : + (VREF_CNTR_REG == "FABRIC_RANGE2") ? VREF_CNTR_FABRIC_RANGE2 : + VREF_CNTR_OFF; + + always @ (FABRIC_VREF_TUNE_in) begin + $display("Info: [Unisim %s-1] Fabric Tune Value changed to %b. Instance: %m",MODULE_NAME, FABRIC_VREF_TUNE_in); + end + + endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HSADC.v b/verilog/src/unisims/HSADC.v new file mode 100644 index 0000000..9998171 --- /dev/null +++ b/verilog/src/unisims/HSADC.v @@ -0,0 +1,525 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HSADC +// /___/ /\ Filename : HSADC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HSADC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter integer XPA_CFG0 = 0, + parameter integer XPA_CFG1 = 0, + parameter XPA_NUM_ADCS = "0", + parameter integer XPA_NUM_DDCS = 0, + parameter XPA_PLL_USED = "No", + parameter integer XPA_SAMPLE_RATE_MSPS = 0 +)( + output CLK_ADC, + output [127:0] DATA_ADC0, + output [127:0] DATA_ADC1, + output [127:0] DATA_ADC2, + output [127:0] DATA_ADC3, + output [15:0] DOUT, + output DRDY, + output PLL_DMON_OUT, + output PLL_REFCLK_OUT, + output [15:0] STATUS_ADC0, + output [15:0] STATUS_ADC1, + output [15:0] STATUS_ADC2, + output [15:0] STATUS_ADC3, + output [15:0] STATUS_COMMON, + output SYSREF_OUT_NORTH, + output SYSREF_OUT_SOUTH, + + input ADC_CLK_N, + input ADC_CLK_P, + input CLK_FIFO_LM, + input [15:0] CONTROL_ADC0, + input [15:0] CONTROL_ADC1, + input [15:0] CONTROL_ADC2, + input [15:0] CONTROL_ADC3, + input [15:0] CONTROL_COMMON, + input [11:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input FABRIC_CLK, + input PLL_MONCLK, + input PLL_REFCLK_IN, + input SYSREF_IN_NORTH, + input SYSREF_IN_SOUTH, + input SYSREF_N, + input SYSREF_P, + input VIN0_N, + input VIN0_P, + input VIN1_N, + input VIN1_P, + input VIN2_N, + input VIN2_P, + input VIN3_N, + input VIN3_P, + input VIN_I01_N, + input VIN_I01_P, + input VIN_I23_N, + input VIN_I23_P +); + +// define constants + localparam MODULE_NAME = "HSADC"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HSADC_dr.v" +`else + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [15:0] XPA_CFG0_REG = XPA_CFG0; + localparam [15:0] XPA_CFG1_REG = XPA_CFG1; + localparam [16:1] XPA_NUM_ADCS_REG = XPA_NUM_ADCS; + localparam [2:0] XPA_NUM_DDCS_REG = XPA_NUM_DDCS; + localparam [24:1] XPA_PLL_USED_REG = XPA_PLL_USED; + localparam [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CLK_ADC_SPARE_out; + wire CLK_ADC_out; + wire DRDY_out; + wire PLL_DMON_OUT_out; + wire PLL_REFCLK_OUT_out; + wire SYSREF_OUT_NORTH_out; + wire SYSREF_OUT_SOUTH_out; + wire [127:0] DATA_ADC0_out; + wire [127:0] DATA_ADC1_out; + wire [127:0] DATA_ADC2_out; + wire [127:0] DATA_ADC3_out; + wire [15:0] DOUT_out; + wire [15:0] STATUS_ADC0_out; + wire [15:0] STATUS_ADC1_out; + wire [15:0] STATUS_ADC2_out; + wire [15:0] STATUS_ADC3_out; + wire [15:0] STATUS_COMMON_out; + wire [15:0] TEST_STATUS_out; + wire [1:0] PLL_SCAN_OUT_B_FD_out; + wire [299:0] TEST_SO_out; + + wire ADC_CLK_N_in; + wire ADC_CLK_P_in; + wire CLK_FIFO_LM_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire FABRIC_CLK_in; + wire PLL_MONCLK_in; + wire PLL_REFCLK_IN_in; + wire PLL_SCAN_EN_B_FD_in; + wire PLL_SCAN_MODE_B_FD_in; + wire PLL_SCAN_RST_EN_FD_in; + wire SYSREF_IN_NORTH_in; + wire SYSREF_IN_SOUTH_in; + wire SYSREF_N_in; + wire SYSREF_P_in; + wire TEST_SCAN_MODE_B_in; + wire TEST_SCAN_RESET_in; + wire TEST_SE_B_in; + wire VIN0_N_in; + wire VIN0_P_in; + wire VIN1_N_in; + wire VIN1_P_in; + wire VIN2_N_in; + wire VIN2_P_in; + wire VIN3_N_in; + wire VIN3_P_in; + wire VIN_I01_N_in; + wire VIN_I01_P_in; + wire VIN_I23_N_in; + wire VIN_I23_P_in; + wire [11:0] DADDR_in; + wire [15:0] CONTROL_ADC0_in; + wire [15:0] CONTROL_ADC1_in; + wire [15:0] CONTROL_ADC2_in; + wire [15:0] CONTROL_ADC3_in; + wire [15:0] CONTROL_COMMON_in; + wire [15:0] DI_in; + wire [15:0] TEST_SCAN_CTRL_in; + wire [1:0] PLL_SCAN_CLK_FD_in; + wire [1:0] PLL_SCAN_IN_FD_in; + wire [299:0] TEST_SI_in; + wire [4:0] TEST_SCAN_CLK_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire [11:0] DADDR_delay; + wire [15:0] DI_delay; +`endif + + real VIN0_N_real = 1.0; + real VIN0_P_real = 1.0; + real VIN1_N_real = 1.0; + real VIN1_P_real = 1.0; + real VIN2_N_real = 1.0; + real VIN2_P_real = 1.0; + real VIN3_N_real = 1.0; + real VIN3_P_real = 1.0; + real VIN_I01_N_real = 1.0; + real VIN_I01_P_real = 1.0; + real VIN_I23_N_real = 1.0; + real VIN_I23_P_real = 1.0; + + assign CLK_ADC = CLK_ADC_out; + assign DATA_ADC0 = DATA_ADC0_out; + assign DATA_ADC1 = DATA_ADC1_out; + assign DATA_ADC2 = DATA_ADC2_out; + assign DATA_ADC3 = DATA_ADC3_out; + assign DOUT = DOUT_out; + assign DRDY = DRDY_out; + assign PLL_DMON_OUT = PLL_DMON_OUT_out; + assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out; + assign STATUS_ADC0 = STATUS_ADC0_out; + assign STATUS_ADC1 = STATUS_ADC1_out; + assign STATUS_ADC2 = STATUS_ADC2_out; + assign STATUS_ADC3 = STATUS_ADC3_out; + assign STATUS_COMMON = STATUS_COMMON_out; + assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out; + assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out; + +`ifdef XIL_TIMING + assign DADDR_in = DADDR_delay; + assign DCLK_in = DCLK_delay; + assign DEN_in = DEN_delay; + assign DI_in = DI_delay; + assign DWE_in = DWE_delay; +`else + assign DADDR_in = DADDR; + assign DCLK_in = DCLK; + assign DEN_in = DEN; + assign DI_in = DI; + assign DWE_in = DWE; +`endif + + assign ADC_CLK_N_in = ADC_CLK_N; + assign ADC_CLK_P_in = ADC_CLK_P; + assign CLK_FIFO_LM_in = CLK_FIFO_LM; + assign CONTROL_ADC0_in = CONTROL_ADC0; + assign CONTROL_ADC1_in = CONTROL_ADC1; + assign CONTROL_ADC2_in = CONTROL_ADC2; + assign CONTROL_ADC3_in = CONTROL_ADC3; + assign CONTROL_COMMON_in = CONTROL_COMMON; + assign FABRIC_CLK_in = FABRIC_CLK; + assign PLL_MONCLK_in = PLL_MONCLK; + assign PLL_REFCLK_IN_in = PLL_REFCLK_IN; + assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH; + assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH; + assign SYSREF_N_in = SYSREF_N; + assign SYSREF_P_in = SYSREF_P; + assign VIN0_N_in = VIN0_N; + assign VIN0_P_in = VIN0_P; + assign VIN1_N_in = VIN1_N; + assign VIN1_P_in = VIN1_P; + assign VIN2_N_in = VIN2_N; + assign VIN2_P_in = VIN2_P; + assign VIN3_N_in = VIN3_N; + assign VIN3_P_in = VIN3_P; + assign VIN_I01_N_in = VIN_I01_N; + assign VIN_I01_P_in = VIN_I01_P; + assign VIN_I23_N_in = VIN_I23_N; + assign VIN_I23_P_in = VIN_I23_P; + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin + $display("Error: [Unisim %s-102] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin + $display("Error: [Unisim %s-103] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_ADCS_REG != "0") && + (XPA_NUM_ADCS_REG != "1") && + (XPA_NUM_ADCS_REG != "1I") && + (XPA_NUM_ADCS_REG != "2") && + (XPA_NUM_ADCS_REG != "2I") && + (XPA_NUM_ADCS_REG != "3") && + (XPA_NUM_ADCS_REG != "4"))) begin + $display("Error: [Unisim %s-104] XPA_NUM_ADCS attribute is set to %s. Legal values for this attribute are 0, 1, 1I, 2, 2I, 3 or 4. Instance: %m", MODULE_NAME, XPA_NUM_ADCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DDCS_REG < 0) || (XPA_NUM_DDCS_REG > 4))) begin + $display("Error: [Unisim %s-105] XPA_NUM_DDCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DDCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_PLL_USED_REG != "No") && + (XPA_PLL_USED_REG != "Yes"))) begin + $display("Error: [Unisim %s-106] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are No or Yes. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin + $display("Error: [Unisim %s-107] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off +assign TEST_SCAN_CLK_in = 5'b11111; // tie off + +assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_IN_FD_in = 2'b11; // tie off +assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off +assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off +assign TEST_SCAN_MODE_B_in = 1'b1; // tie off +assign TEST_SCAN_RESET_in = 1'b1; // tie off +assign TEST_SE_B_in = 1'b1; // tie off +assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + +SIP_HSADC SIP_HSADC_INST ( + .SIM_DEVICE (SIM_DEVICE_REG), + .CLK_ADC (CLK_ADC_out), + .CLK_ADC_SPARE (CLK_ADC_SPARE_out), + .DATA_ADC0 (DATA_ADC0_out), + .DATA_ADC1 (DATA_ADC1_out), + .DATA_ADC2 (DATA_ADC2_out), + .DATA_ADC3 (DATA_ADC3_out), + .DOUT (DOUT_out), + .DRDY (DRDY_out), + .PLL_DMON_OUT (PLL_DMON_OUT_out), + .PLL_REFCLK_OUT (PLL_REFCLK_OUT_out), + .PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out), + .STATUS_ADC0 (STATUS_ADC0_out), + .STATUS_ADC1 (STATUS_ADC1_out), + .STATUS_ADC2 (STATUS_ADC2_out), + .STATUS_ADC3 (STATUS_ADC3_out), + .STATUS_COMMON (STATUS_COMMON_out), + .SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out), + .SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out), + .TEST_SO (TEST_SO_out), + .TEST_STATUS (TEST_STATUS_out), + .ADC_CLK_N (ADC_CLK_N_in), + .ADC_CLK_P (ADC_CLK_P_in), + .CLK_FIFO_LM (CLK_FIFO_LM_in), + .CONTROL_ADC0 (CONTROL_ADC0_in), + .CONTROL_ADC1 (CONTROL_ADC1_in), + .CONTROL_ADC2 (CONTROL_ADC2_in), + .CONTROL_ADC3 (CONTROL_ADC3_in), + .CONTROL_COMMON (CONTROL_COMMON_in), + .DADDR (DADDR_in), + .DCLK (DCLK_in), + .DEN (DEN_in), + .DI (DI_in), + .DWE (DWE_in), + .FABRIC_CLK (FABRIC_CLK_in), + .PLL_MONCLK (PLL_MONCLK_in), + .PLL_REFCLK_IN (PLL_REFCLK_IN_in), + .PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in), + .PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in), + .PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in), + .PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in), + .PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in), + .SYSREF_IN_NORTH (SYSREF_IN_NORTH_in), + .SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in), + .SYSREF_N (SYSREF_N_in), + .SYSREF_P (SYSREF_P_in), + .TEST_SCAN_CLK (TEST_SCAN_CLK_in), + .TEST_SCAN_CTRL (TEST_SCAN_CTRL_in), + .TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in), + .TEST_SCAN_RESET (TEST_SCAN_RESET_in), + .TEST_SE_B (TEST_SE_B_in), + .TEST_SI (TEST_SI_in), + .VIN0_N (VIN0_N_real), + .VIN0_P (VIN0_P_real), + .VIN1_N (VIN1_N_real), + .VIN1_P (VIN1_P_real), + .VIN2_N (VIN2_N_real), + .VIN2_P (VIN2_P_real), + .VIN3_N (VIN3_N_real), + .VIN3_P (VIN3_P_real), + .VIN_I01_N (VIN_I01_N_real), + .VIN_I01_P (VIN_I01_P_real), + .VIN_I23_N (VIN_I23_N_real), + .VIN_I23_P (VIN_I23_P_real), + .GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DCLK => DOUT[0]) = (100:100:100, 100:100:100); + (DCLK => DOUT[10]) = (100:100:100, 100:100:100); + (DCLK => DOUT[11]) = (100:100:100, 100:100:100); + (DCLK => DOUT[12]) = (100:100:100, 100:100:100); + (DCLK => DOUT[13]) = (100:100:100, 100:100:100); + (DCLK => DOUT[14]) = (100:100:100, 100:100:100); + (DCLK => DOUT[15]) = (100:100:100, 100:100:100); + (DCLK => DOUT[1]) = (100:100:100, 100:100:100); + (DCLK => DOUT[2]) = (100:100:100, 100:100:100); + (DCLK => DOUT[3]) = (100:100:100, 100:100:100); + (DCLK => DOUT[4]) = (100:100:100, 100:100:100); + (DCLK => DOUT[5]) = (100:100:100, 100:100:100); + (DCLK => DOUT[6]) = (100:100:100, 100:100:100); + (DCLK => DOUT[7]) = (100:100:100, 100:100:100); + (DCLK => DOUT[8]) = (100:100:100, 100:100:100); + (DCLK => DOUT[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_COMMON[5]) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK_ADC, 0:0:0, notifier); + $period (negedge CLK_FIFO_LM, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge FABRIC_CLK, 0:0:0, notifier); + $period (negedge PLL_DMON_OUT, 0:0:0, notifier); + $period (negedge PLL_MONCLK, 0:0:0, notifier); + $period (negedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (negedge PLL_REFCLK_OUT, 0:0:0, notifier); + $period (posedge CLK_ADC, 0:0:0, notifier); + $period (posedge CLK_FIFO_LM, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge FABRIC_CLK, 0:0:0, notifier); + $period (posedge PLL_DMON_OUT, 0:0:0, notifier); + $period (posedge PLL_MONCLK, 0:0:0, notifier); + $period (posedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (posedge PLL_REFCLK_OUT, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $width (negedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (negedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier); + $width (posedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (posedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/HSDAC.v b/verilog/src/unisims/HSDAC.v new file mode 100644 index 0000000..2504584 --- /dev/null +++ b/verilog/src/unisims/HSDAC.v @@ -0,0 +1,504 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / HSDAC +// /___/ /\ Filename : HSDAC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module HSDAC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter integer XPA_CFG0 = 0, + parameter integer XPA_CFG1 = 0, + parameter integer XPA_NUM_DACS = 0, + parameter integer XPA_NUM_DUCS = 0, + parameter XPA_PLL_USED = "No", + parameter integer XPA_SAMPLE_RATE_MSPS = 0 +)( + output CLK_DAC, + output [15:0] DOUT, + output DRDY, + output PLL_DMON_OUT, + output PLL_REFCLK_OUT, + output [15:0] STATUS_COMMON, + output [15:0] STATUS_DAC0, + output [15:0] STATUS_DAC1, + output [15:0] STATUS_DAC2, + output [15:0] STATUS_DAC3, + output SYSREF_OUT_NORTH, + output SYSREF_OUT_SOUTH, + output VOUT0_N, + output VOUT0_P, + output VOUT1_N, + output VOUT1_P, + output VOUT2_N, + output VOUT2_P, + output VOUT3_N, + output VOUT3_P, + + input CLK_FIFO_LM, + input [15:0] CONTROL_COMMON, + input [15:0] CONTROL_DAC0, + input [15:0] CONTROL_DAC1, + input [15:0] CONTROL_DAC2, + input [15:0] CONTROL_DAC3, + input DAC_CLK_N, + input DAC_CLK_P, + input [11:0] DADDR, + input [255:0] DATA_DAC0, + input [255:0] DATA_DAC1, + input [255:0] DATA_DAC2, + input [255:0] DATA_DAC3, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input FABRIC_CLK, + input PLL_MONCLK, + input PLL_REFCLK_IN, + input SYSREF_IN_NORTH, + input SYSREF_IN_SOUTH, + input SYSREF_N, + input SYSREF_P +); + +// define constants + localparam MODULE_NAME = "HSDAC"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "HSDAC_dr.v" +`else + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [15:0] XPA_CFG0_REG = XPA_CFG0; + localparam [15:0] XPA_CFG1_REG = XPA_CFG1; + localparam [2:0] XPA_NUM_DACS_REG = XPA_NUM_DACS; + localparam [2:0] XPA_NUM_DUCS_REG = XPA_NUM_DUCS; + localparam [24:1] XPA_PLL_USED_REG = XPA_PLL_USED; + localparam [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CLK_DAC_SPARE_out; + wire CLK_DAC_out; + wire DRDY_out; + wire PLL_DMON_OUT_out; + wire PLL_REFCLK_OUT_out; + wire SYSREF_OUT_NORTH_out; + wire SYSREF_OUT_SOUTH_out; + wire VOUT0_N_out; + wire VOUT0_P_out; + wire VOUT1_N_out; + wire VOUT1_P_out; + wire VOUT2_N_out; + wire VOUT2_P_out; + wire VOUT3_N_out; + wire VOUT3_P_out; + wire [15:0] DOUT_out; + wire [15:0] STATUS_COMMON_out; + wire [15:0] STATUS_DAC0_out; + wire [15:0] STATUS_DAC1_out; + wire [15:0] STATUS_DAC2_out; + wire [15:0] STATUS_DAC3_out; + wire [15:0] TEST_STATUS_out; + wire [1:0] PLL_SCAN_OUT_B_FD_out; + wire [299:0] TEST_SO_out; + + wire CLK_FIFO_LM_in; + wire DAC_CLK_N_in; + wire DAC_CLK_P_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire FABRIC_CLK_in; + wire PLL_MONCLK_in; + wire PLL_REFCLK_IN_in; + wire PLL_SCAN_EN_B_FD_in; + wire PLL_SCAN_MODE_B_FD_in; + wire PLL_SCAN_RST_EN_FD_in; + wire SYSREF_IN_NORTH_in; + wire SYSREF_IN_SOUTH_in; + wire SYSREF_N_in; + wire SYSREF_P_in; + wire TEST_SCAN_MODE_B_in; + wire TEST_SCAN_RESET_in; + wire TEST_SE_B_in; + wire [11:0] DADDR_in; + wire [15:0] CONTROL_COMMON_in; + wire [15:0] CONTROL_DAC0_in; + wire [15:0] CONTROL_DAC1_in; + wire [15:0] CONTROL_DAC2_in; + wire [15:0] CONTROL_DAC3_in; + wire [15:0] DI_in; + wire [15:0] TEST_SCAN_CTRL_in; + wire [1:0] PLL_SCAN_CLK_FD_in; + wire [1:0] PLL_SCAN_IN_FD_in; + wire [255:0] DATA_DAC0_in; + wire [255:0] DATA_DAC1_in; + wire [255:0] DATA_DAC2_in; + wire [255:0] DATA_DAC3_in; + wire [299:0] TEST_SI_in; + wire [4:0] TEST_SCAN_CLK_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire FABRIC_CLK_delay; + wire [11:0] DADDR_delay; + wire [15:0] CONTROL_COMMON_delay; + wire [15:0] DI_delay; +`endif + + real VOUT0_N_real; + real VOUT0_P_real; + real VOUT1_N_real; + real VOUT1_P_real; + real VOUT2_N_real; + real VOUT2_P_real; + real VOUT3_N_real; + real VOUT3_P_real; + + assign CLK_DAC = CLK_DAC_out; + assign DOUT = DOUT_out; + assign DRDY = DRDY_out; + assign PLL_DMON_OUT = PLL_DMON_OUT_out; + assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out; + assign STATUS_COMMON = STATUS_COMMON_out; + assign STATUS_DAC0 = STATUS_DAC0_out; + assign STATUS_DAC1 = STATUS_DAC1_out; + assign STATUS_DAC2 = STATUS_DAC2_out; + assign STATUS_DAC3 = STATUS_DAC3_out; + assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out; + assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out; + assign VOUT0_N = VOUT0_N_out; + assign VOUT0_P = VOUT0_P_out; + assign VOUT1_N = VOUT1_N_out; + assign VOUT1_P = VOUT1_P_out; + assign VOUT2_N = VOUT2_N_out; + assign VOUT2_P = VOUT2_P_out; + assign VOUT3_N = VOUT3_N_out; + assign VOUT3_P = VOUT3_P_out; + +`ifdef XIL_TIMING + assign CONTROL_COMMON_in = CONTROL_COMMON_delay; + assign DADDR_in = DADDR_delay; + assign DCLK_in = DCLK_delay; + assign DEN_in = DEN_delay; + assign DI_in = DI_delay; + assign DWE_in = DWE_delay; + assign FABRIC_CLK_in = FABRIC_CLK_delay; +`else + assign CONTROL_COMMON_in = CONTROL_COMMON; + assign DADDR_in = DADDR; + assign DCLK_in = DCLK; + assign DEN_in = DEN; + assign DI_in = DI; + assign DWE_in = DWE; + assign FABRIC_CLK_in = FABRIC_CLK; +`endif + + assign CLK_FIFO_LM_in = CLK_FIFO_LM; + assign CONTROL_DAC0_in = CONTROL_DAC0; + assign CONTROL_DAC1_in = CONTROL_DAC1; + assign CONTROL_DAC2_in = CONTROL_DAC2; + assign CONTROL_DAC3_in = CONTROL_DAC3; + assign DAC_CLK_N_in = DAC_CLK_N; + assign DAC_CLK_P_in = DAC_CLK_P; + assign DATA_DAC0_in = DATA_DAC0; + assign DATA_DAC1_in = DATA_DAC1; + assign DATA_DAC2_in = DATA_DAC2; + assign DATA_DAC3_in = DATA_DAC3; + assign PLL_MONCLK_in = PLL_MONCLK; + assign PLL_REFCLK_IN_in = PLL_REFCLK_IN; + assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH; + assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH; + assign SYSREF_N_in = SYSREF_N; + assign SYSREF_P_in = SYSREF_P; + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin + $display("Error: [Unisim %s-102] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin + $display("Error: [Unisim %s-103] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DACS_REG < 0) || (XPA_NUM_DACS_REG > 4))) begin + $display("Error: [Unisim %s-104] XPA_NUM_DACS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DACS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DUCS_REG < 0) || (XPA_NUM_DUCS_REG > 4))) begin + $display("Error: [Unisim %s-105] XPA_NUM_DUCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DUCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_PLL_USED_REG != "No") && + (XPA_PLL_USED_REG != "Yes"))) begin + $display("Error: [Unisim %s-106] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are No or Yes. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin + $display("Error: [Unisim %s-107] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off +assign TEST_SCAN_CLK_in = 5'b11111; // tie off + +assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_IN_FD_in = 2'b11; // tie off +assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off +assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off +assign TEST_SCAN_MODE_B_in = 1'b1; // tie off +assign TEST_SCAN_RESET_in = 1'b1; // tie off +assign TEST_SE_B_in = 1'b1; // tie off +assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + +SIP_HSDAC SIP_HSDAC_INST ( + .SIM_DEVICE (SIM_DEVICE_REG), + .CLK_DAC (CLK_DAC_out), + .CLK_DAC_SPARE (CLK_DAC_SPARE_out), + .DOUT (DOUT_out), + .DRDY (DRDY_out), + .PLL_DMON_OUT (PLL_DMON_OUT_out), + .PLL_REFCLK_OUT (PLL_REFCLK_OUT_out), + .PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out), + .STATUS_COMMON (STATUS_COMMON_out), + .STATUS_DAC0 (STATUS_DAC0_out), + .STATUS_DAC1 (STATUS_DAC1_out), + .STATUS_DAC2 (STATUS_DAC2_out), + .STATUS_DAC3 (STATUS_DAC3_out), + .SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out), + .SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out), + .TEST_SO (TEST_SO_out), + .TEST_STATUS (TEST_STATUS_out), + .VOUT0_N (VOUT0_N_real), + .VOUT0_P (VOUT0_P_real), + .VOUT1_N (VOUT1_N_real), + .VOUT1_P (VOUT1_P_real), + .VOUT2_N (VOUT2_N_real), + .VOUT2_P (VOUT2_P_real), + .VOUT3_N (VOUT3_N_real), + .VOUT3_P (VOUT3_P_real), + .CLK_FIFO_LM (CLK_FIFO_LM_in), + .CONTROL_COMMON (CONTROL_COMMON_in), + .CONTROL_DAC0 (CONTROL_DAC0_in), + .CONTROL_DAC1 (CONTROL_DAC1_in), + .CONTROL_DAC2 (CONTROL_DAC2_in), + .CONTROL_DAC3 (CONTROL_DAC3_in), + .DAC_CLK_N (DAC_CLK_N_in), + .DAC_CLK_P (DAC_CLK_P_in), + .DADDR (DADDR_in), + .DATA_DAC0 (DATA_DAC0_in), + .DATA_DAC1 (DATA_DAC1_in), + .DATA_DAC2 (DATA_DAC2_in), + .DATA_DAC3 (DATA_DAC3_in), + .DCLK (DCLK_in), + .DEN (DEN_in), + .DI (DI_in), + .DWE (DWE_in), + .FABRIC_CLK (FABRIC_CLK_in), + .PLL_MONCLK (PLL_MONCLK_in), + .PLL_REFCLK_IN (PLL_REFCLK_IN_in), + .PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in), + .PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in), + .PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in), + .PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in), + .PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in), + .SYSREF_IN_NORTH (SYSREF_IN_NORTH_in), + .SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in), + .SYSREF_N (SYSREF_N_in), + .SYSREF_P (SYSREF_P_in), + .TEST_SCAN_CLK (TEST_SCAN_CLK_in), + .TEST_SCAN_CTRL (TEST_SCAN_CTRL_in), + .TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in), + .TEST_SCAN_RESET (TEST_SCAN_RESET_in), + .TEST_SE_B (TEST_SE_B_in), + .TEST_SI (TEST_SI_in), + .GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DCLK => DOUT[0]) = (100:100:100, 100:100:100); + (DCLK => DOUT[10]) = (100:100:100, 100:100:100); + (DCLK => DOUT[11]) = (100:100:100, 100:100:100); + (DCLK => DOUT[12]) = (100:100:100, 100:100:100); + (DCLK => DOUT[13]) = (100:100:100, 100:100:100); + (DCLK => DOUT[14]) = (100:100:100, 100:100:100); + (DCLK => DOUT[15]) = (100:100:100, 100:100:100); + (DCLK => DOUT[1]) = (100:100:100, 100:100:100); + (DCLK => DOUT[2]) = (100:100:100, 100:100:100); + (DCLK => DOUT[3]) = (100:100:100, 100:100:100); + (DCLK => DOUT[4]) = (100:100:100, 100:100:100); + (DCLK => DOUT[5]) = (100:100:100, 100:100:100); + (DCLK => DOUT[6]) = (100:100:100, 100:100:100); + (DCLK => DOUT[7]) = (100:100:100, 100:100:100); + (DCLK => DOUT[8]) = (100:100:100, 100:100:100); + (DCLK => DOUT[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK_DAC, 0:0:0, notifier); + $period (negedge CLK_FIFO_LM, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge FABRIC_CLK, 0:0:0, notifier); + $period (negedge PLL_DMON_OUT, 0:0:0, notifier); + $period (negedge PLL_MONCLK, 0:0:0, notifier); + $period (negedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (negedge PLL_REFCLK_OUT, 0:0:0, notifier); + $period (posedge CLK_DAC, 0:0:0, notifier); + $period (posedge CLK_FIFO_LM, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge FABRIC_CLK, 0:0:0, notifier); + $period (posedge PLL_DMON_OUT, 0:0:0, notifier); + $period (posedge PLL_MONCLK, 0:0:0, notifier); + $period (posedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (posedge PLL_REFCLK_OUT, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]); + $width (negedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (negedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier); + $width (posedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (posedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUF.v b/verilog/src/unisims/IBUF.v new file mode 100644 index 0000000..3dab104 --- /dev/null +++ b/verilog/src/unisims/IBUF.v @@ -0,0 +1,121 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer +// /___/ /\ Filename : IBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUF (O, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + + output O; + input I; + + buf B1 (O, I); + + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + #1 $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + #1 $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + #1 $finish; + end + + endcase + + end + + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/IBUFCTRL.v b/verilog/src/unisims/IBUFCTRL.v new file mode 100644 index 0000000..dbe5b5c --- /dev/null +++ b/verilog/src/unisims/IBUFCTRL.v @@ -0,0 +1,159 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : IBUFCTRL.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFCTRL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter ISTANDARD = "UNUSED", + parameter USE_IBUFDISABLE = "FALSE" +)( + output O, + + input I, + input IBUFDISABLE, + input INTERMDISABLE, + input T +); + +// define constants + localparam MODULE_NAME = "IBUFCTRL"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam USE_IBUFDISABLE_FALSE = 0; + localparam USE_IBUFDISABLE_TRUE = 1; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; + localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE; + + wire USE_IBUFDISABLE_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire O_out; + + wire O_delay; + + wire IBUFDISABLE_in; + wire INTERMDISABLE_in; + wire I_in; + wire T_in; + + wire IBUFDISABLE_delay; + wire INTERMDISABLE_delay; + wire I_delay; + wire T_delay; + wire NOT_T_OR_IBUFDISABLE; + + assign #(out_delay) O = O_delay; + + +// inputs with no timing checks + assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE; + assign #(in_delay) INTERMDISABLE_delay = INTERMDISABLE; + assign #(in_delay) I_delay = I; + assign #(in_delay) T_delay = T; + + assign O_delay = O_out; + + assign IBUFDISABLE_in = IBUFDISABLE_delay; + assign INTERMDISABLE_in = INTERMDISABLE_delay; + assign I_in = I_delay; + assign T_in = T_delay; + + assign USE_IBUFDISABLE_BIN = + (USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE : + (USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE : + USE_IBUFDISABLE_FALSE; + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-103] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((USE_IBUFDISABLE_REG != "FALSE") && + (USE_IBUFDISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign NOT_T_OR_IBUFDISABLE = ~T_in || IBUFDISABLE_in; + assign O_out = (NOT_T_OR_IBUFDISABLE == 0)? I_in : (NOT_T_OR_IBUFDISABLE == 1)? 1'b0 : 1'bx; + end + "FALSE" : begin + assign O_out = I_in; + end + endcase + endgenerate + + specify + (I => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS.v b/verilog/src/unisims/IBUFDS.v new file mode 100644 index 0000000..2aa6702 --- /dev/null +++ b/verilog/src/unisims/IBUFDS.v @@ -0,0 +1,159 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools +// 07/19/06 - Add else to handle x case for o_out (CR 234718). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/13/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + + +module IBUFDS (O, I, IB); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + + localparam MODULE_NAME = "IBUFDS"; + + output O; + input I, IB; + + wire i_in, ib_in; + reg o_out; + reg DQS_BIAS_BINARY = 1'b0; + + assign O = o_out; + + assign i_in = I; + assign ib_in = IB; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE); + #1 $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE); + #1 $finish; + end + + endcase + +end + + always @(i_in or ib_in or DQS_BIAS_BINARY) begin + if (i_in == 1'b1 && ib_in == 1'b0) + o_out <= 1'b1; + else if (i_in == 1'b0 && ib_in == 1'b1) + o_out <= 1'b0; + else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((i_in === 1'bx) || (ib_in === 1'bx)) + o_out <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDSE3.v b/verilog/src/unisims/IBUFDSE3.v new file mode 100644 index 0000000..64eb648 --- /dev/null +++ b/verilog/src/unisims/IBUFDSE3.v @@ -0,0 +1,334 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Input Buffer with Offset Calibration +// /___/ /\ Filename : IBUFDSE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDSE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DIFF_TERM = "FALSE", + parameter DQS_BIAS = "FALSE", + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SIM_DEVICE = "ULTRASCALE", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0, + parameter USE_IBUFDISABLE = "FALSE" +)( + output O, + + input I, + input IB, + input IBUFDISABLE, + input [3:0] OSC, + input [1:0] OSC_EN +); + +// define constants + localparam MODULE_NAME = "IBUFDSE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam DIFF_TERM_FALSE = 0; + localparam DIFF_TERM_TRUE = 1; + localparam DQS_BIAS_FALSE = 0; + localparam DQS_BIAS_TRUE = 1; + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_RF = 8; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10; + localparam SIM_DEVICE_VERSAL_HBM = 11; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 12; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 13; + localparam SIM_DEVICE_VERSAL_PREMIUM = 14; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PRIME = 17; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 19; + localparam USE_IBUFDISABLE_FALSE = 0; + localparam USE_IBUFDISABLE_TRUE = 1; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; + localparam [40:1] DIFF_TERM_REG = DIFF_TERM; + localparam [40:1] DQS_BIAS_REG = DQS_BIAS; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE; + localparam [144:1] SIM_DEVICE_REG = SIM_DEVICE; + + wire DIFF_TERM_BIN; + wire DQS_BIAS_BIN; + wire IBUF_LOW_PWR_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire USE_IBUFDISABLE_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg O_out; + reg O_OSC_in; + + wire O_delay; + + wire IBUFDISABLE_in; + wire IB_in; + wire I_in; + wire [1:0] OSC_EN_in; + wire [3:0] OSC_in; + + wire IBUFDISABLE_delay; + wire IB_delay; + wire I_delay; + wire [1:0] OSC_EN_delay; + wire [3:0] OSC_delay; + + assign #(out_delay) O = O_delay; + + +// inputs with no timing checks + assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE; + assign #(in_delay) IB_delay = IB; + assign #(in_delay) I_delay = I; + assign #(in_delay) OSC_EN_delay = OSC_EN; + assign #(in_delay) OSC_delay = OSC; + + assign IBUFDISABLE_in = IBUFDISABLE_delay; + assign IB_in = IB_delay; + assign I_in = I_delay; + assign OSC_EN_in = OSC_EN_delay; + assign OSC_in = OSC_delay; + + assign DIFF_TERM_BIN = + (DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE : + (DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE : + DIFF_TERM_FALSE; + + assign DQS_BIAS_BIN = + (DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE : + (DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE : + DQS_BIAS_FALSE; + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + + assign USE_IBUFDISABLE_BIN = + (USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE : + (USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE : + USE_IBUFDISABLE_FALSE; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-105] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin + $display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG); + attr_err = 1'b1; +end + + if ((attr_test == 1'b1) || + ((DQS_BIAS_REG != "FALSE") && + (DQS_BIAS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-103] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_IBUFDISABLE_REG != "FALSE") && + (USE_IBUFDISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +// begin behavioral model + + integer OSC_int = 0; + wire versal_or_later; + wire [1:0] OSC_EN_in_muxed; + wire [3:0] OSC_in_muxed; + + + assign versal_or_later = ( SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE || + SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE_PLUS ) ? 1'b0 : 1'b1; + + assign OSC_in_muxed = versal_or_later ? 4'd0 : OSC_in; + assign OSC_EN_in_muxed = versal_or_later ? 2'd0 : OSC_EN_in; + + + assign O_delay = (OSC_EN_in_muxed === 2'b11) ? O_OSC_in : + (OSC_EN_in_muxed === 2'b10 || OSC_EN_in_muxed === 2'b01) ? 1'bx : + O_out; + + always @ (OSC_in_muxed or OSC_EN_in_muxed) begin + OSC_int = OSC_in_muxed[2:0] * 5; + if (OSC_in_muxed[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in_muxed == 2'b11) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= ~O_OSC_in; + end + end + + + initial begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= 1'bx; + end + + + + always @(I_in or IB_in or DQS_BIAS_BIN or IBUFDISABLE_in or USE_IBUFDISABLE_BIN) begin + if (USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b1) + O_out <= 1'b0; + else if ((USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b0) || (USE_IBUFDISABLE_BIN == 1'b0)) begin + if (I_in == 1'b1 && IB_in == 1'b0) + O_out <= 1'b1; + else if (I_in == 1'b0 && IB_in == 1'b1) + O_out <= 1'b0; + else if ((I_in === 1'bz || I_in == 1'b0) && (IB_in === 1'bz || IB_in == 1'b1)) + if (DQS_BIAS_BIN == 1'b1) + O_out <= 1'b0; + else + O_out <= 1'bx; + else if ((I_in === 1'bx) || (IB_in === 1'bx)) + O_out <= 1'bx; + end + else begin + O_out <= 1'bx; + end + end + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_DIFF_OUT.v b/verilog/src/unisims/IBUFDS_DIFF_OUT.v new file mode 100644 index 0000000..353ef2a --- /dev/null +++ b/verilog/src/unisims/IBUFDS_DIFF_OUT.v @@ -0,0 +1,125 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with Differential Outputs +// /___/ /\ Filename : IBUFDS_DIFF_OUT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM. +// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR. +// 11/03/10 - CR 576577 -- changed default value of IOSTANDARD from LVDS_25 to DEFAULT. +// 09/30/11 - CR 626400 -- Added PATHPULSE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUFDS_DIFF_OUT (O, OB, I, IB); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; +`ifdef XIL_TIMING + parameter LOC = " UNPLACED"; +`endif + output O, OB; + + input I, IB; + + reg o_out; + reg DQS_BIAS_BINARY = 1'b0; + + + buf B0 (O, o_out); + not B1 (OB, o_out); + + initial begin + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + + endcase + + + end + + + always @(I or IB or DQS_BIAS_BINARY) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + `ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IB => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + + `endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_DIFF_OUT_IBUFDISABLE.v b/verilog/src/unisims/IBUFDS_DIFF_OUT_IBUFDISABLE.v new file mode 100644 index 0000000..1673717 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_DIFF_OUT_IBUFDISABLE.v @@ -0,0 +1,187 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Differential Signaling Input Buffer with Differential Outputs +// /___/ /\ Filename : IBUFDS_DIFF_OUT_IBUFDISABLE.v +// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010 +// \___\/\___\ +// +// Revision: +// 12/08/10 - Initial version. +// 04/04/11 - CR 604808 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUFDS_DIFF_OUT_IBUFDISABLE (O, OB, I, IB, IBUFDISABLE); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + output OB; + + input I; + input IB; + input IBUFDISABLE; + +// define constants + localparam MODULE_NAME = "IBUFDS_DIFF_OUT_IBUFDISABLE"; + + reg o_out; + reg DQS_BIAS_BINARY = 1'b0; + wire out_val; + wire out_b_val; + + + initial begin + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + end + + + always @(I or IB or DQS_BIAS_BINARY) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if (I === 1'bx || IB === 1'bx) + o_out <= 1'bx; + end + + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + assign out_b_val = 1'b1; + end + "ULTRASCALE" : begin + assign out_val = 1'b0; + assign out_b_val = 1'bx; + end + default : begin + assign out_val = 1'b0; + assign out_b_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx; + assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx; + end + "FALSE" : begin + assign O = o_out; + assign OB = ~o_out; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IB => OB) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_DIFF_OUT_INTERMDISABLE.v b/verilog/src/unisims/IBUFDS_DIFF_OUT_INTERMDISABLE.v new file mode 100644 index 0000000..a19c3c2 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_DIFF_OUT_INTERMDISABLE.v @@ -0,0 +1,187 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with Differential Outputs +// /___/ /\ Filename : IBUFDS_DIFF_OUT_INTERMDISABLE.v +// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011 +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, I, IB, IBUFDISABLE, INTERMDISABLE); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + + output O; + output OB; + + input I; + input IB; + input IBUFDISABLE; + input INTERMDISABLE; + + localparam MODULE_NAME = "IBUFDS_DIFF_OUT_INTERMDISABLE"; + + reg o_out; + reg DQS_BIAS_BINARY = 1'b0; + wire out_val; + wire out_b_val; + + + initial begin + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + end + + + always @(I or IB or DQS_BIAS_BINARY) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + assign out_b_val = 1'b1; + end + "ULTRASCALE" : begin + assign out_val = 1'b0; + assign out_b_val = 1'bx; + end + default : begin + assign out_val = 1'b0; + assign out_b_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx; + assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx; + end + "FALSE" : begin + assign O = o_out; + assign OB = ~o_out; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IB => OB) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => OB) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_DPHY.v b/verilog/src/unisims/IBUFDS_DPHY.v new file mode 100644 index 0000000..051426b --- /dev/null +++ b/verilog/src/unisims/IBUFDS_DPHY.v @@ -0,0 +1,196 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : IBUFDS_DPHY.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_DPHY #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DIFF_TERM = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SIM_DEVICE = "ULTRASCALE_PLUS" +)( + output HSRX_O, + output LPRX_O_N, + output LPRX_O_P, + + input HSRX_DISABLE, + input I, + input IB, + input LPRX_DISABLE +); + +// define constants + localparam MODULE_NAME = "IBUFDS_DPHY"; + +// Parameter encodings and registers + localparam DIFF_TERM_FALSE = 1; + localparam DIFF_TERM_TRUE = 0; + localparam IOSTANDARD_DEFAULT = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "IBUFDS_DPHY_dr.v" +`else + localparam [40:1] DIFF_TERM_REG = DIFF_TERM; + localparam [56:1] IOSTANDARD_REG = IOSTANDARD; +`endif + + wire DIFF_TERM_BIN; + wire IOSTANDARD_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire HSRX_O_out; + wire LPRX_O_N_out; + wire LPRX_O_P_out; + + wire HSRX_DISABLE_in; + wire IB_in; + wire I_in; + wire LPRX_DISABLE_in; + + assign HSRX_O = HSRX_O_out; + assign LPRX_O_N = LPRX_O_N_out; + assign LPRX_O_P = LPRX_O_P_out; + + assign HSRX_DISABLE_in = HSRX_DISABLE; + assign IB_in = IB; + assign I_in = I; + assign LPRX_DISABLE_in = LPRX_DISABLE; + + assign DIFF_TERM_BIN = + (DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE : + (DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE : + DIFF_TERM_TRUE; + + assign IOSTANDARD_BIN = + (IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT : + IOSTANDARD_DEFAULT; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DIFF_TERM_REG != "TRUE") && + (DIFF_TERM_REG != "FALSE"))) begin + $display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE != "ULTRASCALE_PLUS") && + (SIM_DEVICE != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE != "ULTRASCALE_PLUS_ES2") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + attr_err = 1'b1; + end + +// no check +// if ((attr_test == 1'b1) || +// ((IOSTANDARD_REG != "DEFAULT"))) begin +// $display("Error: [Unisim %s-102] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG); +// attr_err = 1'b1; +// end + + if (attr_err == 1'b1) #1 $finish; + end + + reg o_out; + wire [1:0] lp_out; + wire sim_mode; + wire lp_mode; + wire lp_rx_disable; + wire hs_mode; + wire hs_out; + reg [3*8:1] strP,strN; + + always @(*) + begin + $sformat(strP, "%v", I); + $sformat(strN, "%v", IB); + end + + assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong + //assign sim_mode = (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE== "ULTRASCALE_PLUS_ES1" || SIM_DEVICE== "ULTRASCALE_PLUS_ES2") ? 1'b0 : 1'b0; + assign sim_mode = 1'b0; + assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0; + assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0; + + assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0; + + assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode; + assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode; + + always @ (I_in or IB_in) begin + if (I_in == 1'b1 && IB_in == 1'b0) + o_out <= 1'b1; + else if (I_in == 1'b0 && IB_in == 1'b1) + o_out <= 1'b0; + else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz ) + o_out <= 1'bx; + end + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_GTE2.v b/verilog/src/unisims/IBUFDS_GTE2.v new file mode 100644 index 0000000..70e9949 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_GTE2.v @@ -0,0 +1,167 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS_GTE2.v +// \ \ / \ Timestamp : Tue Jun 1 14:31:01 PDT 2010 +// \___\/\___\ +// +// Revision: +// 06/01/10 - Initial version. +// 09/29/11 - 627247 -- Changed CLKSWING_CFG from blooean to bits +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps/1 ps + +`celldefine + +module IBUFDS_GTE2 ( + O, + ODIV2, + + CEB, + I, + IB + ); +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter [1:0] CLKSWING_CFG = 2'b11; + + output O; + output ODIV2; + + input CEB; + input I; + input IB; + + +// Output signals + reg O_out=0, ODIV2_out=0; + +// Counters and Flags + reg [2:0] ce_count = 1; + reg [2:0] edge_count = 0; + + reg allEqual; + +// Attribute settings + +// Other signals + reg clkcm_cfg_int = 0; + reg clkrcv_trst_int = 0; + reg clkswing_cfg_int = 0; + + reg [1:0] CLKSWING_CFG_BINARY; + reg notifier; + + initial begin + allEqual = 0; + +//------------------------------------------------- +//----- CLKCM_CFG check +//------------------------------------------------- + case (CLKCM_CFG) + + "FALSE" : clkcm_cfg_int <= 1'b0; + "TRUE" : clkcm_cfg_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG); + #1 $finish; + end + + endcase // case(CLKCM_CFG) + +//------------------------------------------------- +//----- CLKRCV_TRST check +//------------------------------------------------- + case (CLKRCV_TRST) + + "FALSE" : clkrcv_trst_int <= 1'b0; + "TRUE" : clkrcv_trst_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST); + #1 $finish; + end + + endcase // case(CLKRCV_TRST) + + end // initial begin + + +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge I) begin + if(allEqual) + edge_count <= 3'b000; + else + if (CEB == 1'b0) + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate ODIV2 +// ===================== + always @(posedge I) + ODIV2_out <= allEqual; + +// ===================== +// Generate O +// ===================== + always @(I) + O_out <= I & ~CEB; + + +// ===================== +// Outputs +// ===================== + + assign O = O_out; + assign ODIV2 = ODIV2_out; + + + specify +`ifdef XIL_TIMING + $period (posedge I, 0:0:0, notifier); + $period (posedge IB, 0:0:0, notifier); + ( I => O) = (100:100:100, 100:100:100); + ( I => ODIV2) = (100:100:100, 100:100:100); + ( IB => O) = (100:100:100, 100:100:100); + ( IB => ODIV2) = (100:100:100, 100:100:100); +`endif + specparam PATHPULSE$ = 0; + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_GTE3.v b/verilog/src/unisims/IBUFDS_GTE3.v new file mode 100644 index 0000000..522ff32 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_GTE3.v @@ -0,0 +1,169 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : IBUFDS_GTE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 12/11/2012 - Initial version +// 03/22/2013 - Model added +// 03/25/2013 - Sync 5 YML & model update +// 04/12/2013 - Add attribute section +// 08/28/2013 - Add specify section +// 06/02/2014 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + + +`timescale 1 ps / 1 ps + +`celldefine +module IBUFDS_GTE3 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00, + parameter [1:0] REFCLK_ICNTL_RX = 2'b00 +)( + output O, + output ODIV2, + + input CEB, + input I, + input IB +); + +// define constants + + localparam MODULE_NAME = "IBUFDS_GTE3"; + + // Parameter encodings and registers + `ifndef XIL_DR + localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + localparam [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL; + localparam [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX; + `endif + + wire REFCLK_EN_TX_PATH_BIN; + wire [1:0] REFCLK_HROW_CK_SEL_BIN; + wire [1:0] REFCLK_ICNTL_RX_BIN; + wire i_in, ib_in, ceb_in; + + + tri0 GSR = glbl.GSR; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + +// include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "IBUFDS_GTE3_dr.v" + `endif + + assign i_in = I; + assign ib_in = IB; + assign ceb_in = CEB; + + + assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG; + assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG; + assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG; + + reg ODIV2_out=0; + wire O_out; + + + reg [2:0] ce_count = 1; + reg [2:0] edge_count = 0; + + reg allEqual; + + initial begin + allEqual = 0; + end // initial begin + + +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge I) begin + if(allEqual) + edge_count <= 3'b000; + else + if (CEB == 1'b0) + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate ODIV2 +// ===================== + always @(*) begin + case (REFCLK_HROW_CK_SEL_BIN) + 2'b00: ODIV2_out <= O_out; + 2'b01: ODIV2_out <= allEqual; + 2'b10: ODIV2_out <= 1'b0; + 2'b11: ODIV2_out <= 1'b0; + default : ODIV2_out <= O_out; + endcase + end + +// ===================== +// Generate O +// ===================== + + assign O_out = (REFCLK_EN_TX_PATH_BIN | ceb_in) ? 1'b0 : i_in; + + + +// ===================== +// Outputs +// ===================== + + assign O = O_out; + assign ODIV2 = ODIV2_out; + + + specify + (CEB => O) = (0:0:0, 0:0:0); + (CEB => ODIV2) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (I => ODIV2) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IB => ODIV2) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_GTE4.v b/verilog/src/unisims/IBUFDS_GTE4.v new file mode 100644 index 0000000..318972c --- /dev/null +++ b/verilog/src/unisims/IBUFDS_GTE4.v @@ -0,0 +1,144 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver Buffer +// /___/ /\ Filename : IBUFDS_GTE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/27/2015 - Initial version from E3 +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_GTE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00, + parameter [1:0] REFCLK_ICNTL_RX = 2'b00 +)( + output O, + output ODIV2, + + input CEB, + input I, + input IB +); + +// define constants + localparam MODULE_NAME = "IBUFDS_GTE4"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "IBUFDS_GTE4_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL; + reg [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + +// wire CEB_in; +// wire IB_in; +// wire I_in; + +// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0 +// assign IB_in = IB; +// assign I_in = I; + + reg ODIV2_out = 1'b0; + assign ODIV2 = ODIV2_out; + + reg [2:0] ce_count = 3'b001; + reg [2:0] edge_count = 3'b000; + + reg allEqual = 1'b0; + +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge I) begin + if (allEqual) + edge_count <= 3'b000; + else + if ((CEB === 1'b0) || (CEB === 1'bz)) // rv = 0 + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate ODIV2 +// ===================== + always @(*) begin + case (REFCLK_HROW_CK_SEL_REG) + 2'b00: ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + 2'b01: ODIV2_out <= allEqual; + 2'b10: ODIV2_out <= 1'b0; + 2'b11: ODIV2_out <= 1'b0; + default : ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + endcase + end + +// ===================== +// Generate O +// ===================== + + assign O = ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + +`ifndef XIL_XECLIB +//`ifdef XIL_TIMING +// "I" is actually a CLK so need I -> O/ODIV2 delays in functional as well. + +// IB to O/ODIV2 delay added because this was creating confusion in some tools +// even though IB input behavior is not modeled. + specify + (I => O) = (100:100:100, 100:100:100); + (I => ODIV2) = (100:100:100, 100:100:100); + (IB => O) = (100:100:100, 100:100:100); + (IB => ODIV2) = (100:100:100, 100:100:100); + specparam PATHPULSE$ = 0; + endspecify +//`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_GTM.v b/verilog/src/unisims/IBUFDS_GTM.v new file mode 100644 index 0000000..8077e2f --- /dev/null +++ b/verilog/src/unisims/IBUFDS_GTM.v @@ -0,0 +1,200 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / IBUFDS_GTM +// /___/ /\ Filename : IBUFDS_GTM.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_GTM #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter integer REFCLK_HROW_CK_SEL = 0, + parameter integer REFCLK_ICNTL_RX = 0 +)( + output O, + output ODIV2, + + input CEB, + input I, + input IB +); + +// define constants + localparam MODULE_NAME = "IBUFDS_GTM"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "IBUFDS_GTM_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [31:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL; + reg [31:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX; +`endif + +`ifdef XIL_XECLIB + wire [1:0] REFCLK_HROW_CK_SEL_BIN; + wire [1:0] REFCLK_ICNTL_RX_BIN; +`else + reg [1:0] REFCLK_HROW_CK_SEL_BIN; + reg [1:0] REFCLK_ICNTL_RX_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG[1:0]; + + assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG[1:0]; + +`else + always @ (trig_attr) begin + #1; + REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG[1:0]; + + REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG[1:0]; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((REFCLK_HROW_CK_SEL_REG != 0) && + (REFCLK_HROW_CK_SEL_REG != 1) && + (REFCLK_HROW_CK_SEL_REG != 2) && + (REFCLK_HROW_CK_SEL_REG != 3))) begin + $display("Error: [Unisim %s-102] REFCLK_HROW_CK_SEL attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, REFCLK_HROW_CK_SEL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REFCLK_ICNTL_RX_REG != 0) && + (REFCLK_ICNTL_RX_REG != 1) && + (REFCLK_ICNTL_RX_REG != 2) && + (REFCLK_ICNTL_RX_REG != 3))) begin + $display("Error: [Unisim %s-103] REFCLK_ICNTL_RX attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, REFCLK_ICNTL_RX_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +// begin behavioral model + + reg ODIV2_out = 1'b0; + assign ODIV2 = ODIV2_out; + + reg [2:0] ce_count = 3'b001; + reg [2:0] edge_count = 3'b000; + + reg allEqual = 1'b0; + +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge I) begin + if (allEqual) + edge_count <= 3'b000; + else + if ((CEB === 1'b0) || (CEB === 1'bz)) // rv = 0 + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate ODIV2 +// ===================== + always @(*) begin + case (REFCLK_HROW_CK_SEL_REG) + 32'b00: ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + 32'b01: ODIV2_out <= allEqual; + 32'b10: ODIV2_out <= 1'b0; + 32'b11: ODIV2_out <= 1'b0; + default : ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + endcase + end + +// ===================== +// Generate O +// ===================== + + assign O = ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I; + +`ifndef XIL_XECLIB +//`ifdef XIL_TIMING +// "I" is actually a CLK so need I -> O/ODIV2 delays in functional as well. + specify + (I => O) = (100:100:100, 100:100:100); + (I => ODIV2) = (100:100:100, 100:100:100); + (IB => O) = (0:0:0, 0:0:0); + (IB => ODIV2) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +//`endif +`endif + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_IBUFDISABLE.v b/verilog/src/unisims/IBUFDS_IBUFDISABLE.v new file mode 100644 index 0000000..509af33 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_IBUFDISABLE.v @@ -0,0 +1,184 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS_IBUFDISABLE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 12/08/10 - Initial version. +// 04/04/11 - CR 604808 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/10/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_IBUFDISABLE (O, I, IB, IBUFDISABLE); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IBUFDS_IBUFDISABLE"; + + + output O; + + input I; + input IB; + input IBUFDISABLE; + + wire i_in, ib_in, ibufdisable_in; + reg o_out; + wire out_val; + + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((ibufdisable_in === 1'b1) ? out_val : ((ibufdisable_in === 1'b0) ? o_out : 1'bx)); + + assign i_in = I; + assign ib_in = IB; + assign ibufdisable_in = IBUFDISABLE; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + always @(i_in or ib_in or DQS_BIAS_BINARY) begin + if (i_in == 1'b1 && ib_in == 1'b0) + o_out <= 1'b1; + else if (i_in == 1'b0 && ib_in == 1'b1) + o_out <= 1'b0; + else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((i_in === 1'bx) || (ib_in === 1'bx)) + o_out <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_IBUFDISABLE_INT.v b/verilog/src/unisims/IBUFDS_IBUFDISABLE_INT.v new file mode 100644 index 0000000..eda5b45 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_IBUFDISABLE_INT.v @@ -0,0 +1,143 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS_IBUFDISABLE_INT.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/10/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_IBUFDISABLE_INT (O, I, IB, IBUFDISABLE); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IBUFDS_IBUFDISABLE_INT"; + + + output O; + + input I; + input IB; + input IBUFDISABLE; + + wire i_in, ib_in, ibufdisable_in; + reg o_out; + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx)); + + assign i_in = I; + assign ib_in = IB; + assign ibufdisable_in = IBUFDISABLE; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + end + + always @(i_in or ib_in or DQS_BIAS_BINARY) begin + if (i_in == 1'b1 && ib_in == 1'b0) + o_out <= 1'b1; + else if (i_in == 1'b0 && ib_in == 1'b1) + o_out <= 1'b0; + else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((i_in === 1'bx) || (ib_in === 1'bx)) + o_out <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_INTERMDISABLE.v b/verilog/src/unisims/IBUFDS_INTERMDISABLE.v new file mode 100644 index 0000000..c929132 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_INTERMDISABLE.v @@ -0,0 +1,185 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS_INTERMDISABLE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/13/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_INTERMDISABLE (O, I, IB, IBUFDISABLE, INTERMDISABLE); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IBUFDS_INTERMDISABLE"; + + + output O; + + input I; + input IB; + input IBUFDISABLE; + input INTERMDISABLE; + + wire i_in, ib_in, ibufdisable_in, intermdisable_in; + reg o_out; + wire out_val; + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((ibufdisable_in === 1'b1) ? out_val : ((ibufdisable_in === 1'b0) ? o_out : 1'bx)); + + assign i_in = I; + assign ib_in = IB; + assign ibufdisable_in = IBUFDISABLE; + assign intermdisable_in = INTERMDISABLE; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + always @(i_in or ib_in or DQS_BIAS_BINARY) begin + if (i_in == 1'b1 && ib_in == 1'b0) + o_out <= 1'b1; + else if (i_in == 1'b0 && ib_in == 1'b1) + o_out <= 1'b0; + else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((i_in === 1'bx) || (ib_in === 1'bx)) + o_out <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFDS_INTERMDISABLE_INT.v b/verilog/src/unisims/IBUFDS_INTERMDISABLE_INT.v new file mode 100644 index 0000000..78b9470 --- /dev/null +++ b/verilog/src/unisims/IBUFDS_INTERMDISABLE_INT.v @@ -0,0 +1,146 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS_INTERMDISABLE_INT.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/10/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFDS_INTERMDISABLE_INT (O, I, IB, IBUFDISABLE, INTERMDISABLE); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IBUFDS_INTERMDISABLE_INT"; + + + output O; + + input I; + input IB; + input IBUFDISABLE; + input INTERMDISABLE; + + wire i_in, ib_in, ibufdisable_in, intermdisable_in; + reg o_out; + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx)); + + assign i_in = I; + assign ib_in = IB; + assign ibufdisable_in = IBUFDISABLE; + assign intermdisable_in = INTERMDISABLE; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + end + + always @(i_in or ib_in or DQS_BIAS_BINARY) begin + if (i_in == 1'b1 && ib_in == 1'b0) + o_out <= 1'b1; + else if (i_in == 1'b0 && ib_in == 1'b1) + o_out <= 1'b0; + else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((i_in === 1'bx) || (ib_in === 1'bx)) + o_out <= 1'bx; + end + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (IB => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUFE3.v b/verilog/src/unisims/IBUFE3.v new file mode 100644 index 0000000..9a8b106 --- /dev/null +++ b/verilog/src/unisims/IBUFE3.v @@ -0,0 +1,291 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Input Buffer with Offset Calibration and VREF Tuning +// /___/ /\ Filename : IBUFE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUFE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SIM_DEVICE = "ULTRASCALE", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0, + parameter USE_IBUFDISABLE = "FALSE" +)( + output O, + + input I, + input IBUFDISABLE, + input [3:0] OSC, + input OSC_EN, + input VREF +); + +// define constants + localparam MODULE_NAME = "IBUFE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_RF = 8; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10; + localparam SIM_DEVICE_VERSAL_HBM = 11; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 12; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 13; + localparam SIM_DEVICE_VERSAL_PREMIUM = 14; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PRIME = 17; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 19; + localparam USE_IBUFDISABLE_FALSE = 0; + localparam USE_IBUFDISABLE_TRUE = 1; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE; + localparam [144:1] SIM_DEVICE_REG = SIM_DEVICE; + + wire IBUF_LOW_PWR_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire [6:0] SIM_INPUT_BUFFER_OFFSET_BIN; + wire USE_IBUFDISABLE_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire O_out; + reg O_OSC_in; + + wire O_delay; + + wire IBUFDISABLE_in; + wire I_in; + wire OSC_EN_in; + wire VREF_in; + wire [3:0] OSC_in; + + wire IBUFDISABLE_delay; + wire I_delay; + wire OSC_EN_delay; + wire VREF_delay; + wire [3:0] OSC_delay; + + assign #(out_delay) O = O_delay; + + +// inputs with no timing checks + assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE; + assign #(in_delay) I_delay = I; + assign #(in_delay) OSC_EN_delay = OSC_EN; + assign #(in_delay) OSC_delay = OSC; + assign #(in_delay) VREF_delay = VREF; + + assign O_delay = O_out; + + assign IBUFDISABLE_in = IBUFDISABLE_delay; + assign I_in = I_delay; + assign OSC_EN_in = OSC_EN_delay; + assign OSC_in = OSC_delay; + assign VREF_in = VREF_delay; + + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG; + + assign USE_IBUFDISABLE_BIN = + (USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE : + (USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE : + USE_IBUFDISABLE_FALSE; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-103] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-101] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_IBUFDISABLE_REG != "FALSE") && + (USE_IBUFDISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + +// begin behavioral model + + integer OSC_int = 0; + wire versal_or_later; + wire [1:0] OSC_EN_in_muxed; + wire [3:0] OSC_in_muxed; + + assign versal_or_later = ( SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE || + SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE_PLUS ) ? 1'b0 : 1'b1; + + assign OSC_in_muxed = versal_or_later ? 4'd0 : OSC_in; + assign OSC_EN_in_muxed = versal_or_later ? 2'd0 : OSC_EN_in; + + + generate + case (USE_IBUFDISABLE_REG) + "TRUE" : begin + assign O_out = (IBUFDISABLE_in == 0)? (OSC_EN_in_muxed) ? O_OSC_in : I_in : (IBUFDISABLE_in == 1 && OSC_EN_in_muxed != 1)? 1'b0 : 1'bx; + end + "FALSE" : begin + assign O_out = (OSC_EN_in_muxed) ? O_OSC_in : I_in; + end + endcase + endgenerate + + + always @ (OSC_in_muxed or OSC_EN_in_muxed) begin + OSC_int = OSC_in_muxed[2:0] * 5; + if (OSC_in_muxed[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in_muxed == 1'b1) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= ~O_OSC_in; + end + end + + initial begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= 1'bx; + + end + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUF_ANALOG.v b/verilog/src/unisims/IBUF_ANALOG.v new file mode 100644 index 0000000..7216fce --- /dev/null +++ b/verilog/src/unisims/IBUF_ANALOG.v @@ -0,0 +1,72 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Analog Auxiliary SYSMON Input Buffer +// /___/ /\ Filename : IBUF_ANALOG.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/30/13 - Initial version. +// 02/04/15 - 845545 - Remove pulldown and strength specification. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IBUF_ANALOG +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output O, + + input I +); + +// define constants + localparam MODULE_NAME = "IBUF_ANALOG"; + + tri0 glblGSR = glbl.GSR; + +// begin behavioral model + + assign O = I; + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING +specify + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; +endspecify +`endif +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUF_IBUFDISABLE.v b/verilog/src/unisims/IBUF_IBUFDISABLE.v new file mode 100644 index 0000000..49918dd --- /dev/null +++ b/verilog/src/unisims/IBUF_IBUFDISABLE.v @@ -0,0 +1,131 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Input Buffer +// /___/ /\ Filename : IBUF_IBUFDISABLE.v +// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010 +// \___\/\___\ +// +// Revision: +// 12/08/10 - Initial version. +// 04/04/11 - CR 604808 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUF_IBUFDISABLE (O, I, IBUFDISABLE); + + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + + input I; + input IBUFDISABLE; + +// define constants + localparam MODULE_NAME = "IBUF_IBUFDISABLE"; + + wire out_val; + initial begin + + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? out_val : 1'bx; + end + "FALSE" : begin + assign O = I; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + + (I => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IBUF_INTERMDISABLE.v b/verilog/src/unisims/IBUF_INTERMDISABLE.v new file mode 100644 index 0000000..3d1e69c --- /dev/null +++ b/verilog/src/unisims/IBUF_INTERMDISABLE.v @@ -0,0 +1,133 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Input Buffer +// /___/ /\ Filename : IBUF_INTERMDISABLE.v +// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011 +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IBUF_INTERMDISABLE (O, I, IBUFDISABLE, INTERMDISABLE); + + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + + input I; + input IBUFDISABLE; + input INTERMDISABLE; + +// define constants + localparam MODULE_NAME = "IBUF_INTERMDISABLE"; + + wire out_val; + initial begin + + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-103] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? out_val : 1'bx; + end + "FALSE" : begin + assign O = I; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + + (I => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ICAPE2.v b/verilog/src/unisims/ICAPE2.v new file mode 100644 index 0000000..1d6a112 --- /dev/null +++ b/verilog/src/unisims/ICAPE2.v @@ -0,0 +1,338 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.i (O.51) +// \ \ Description : +// / / +// /__/ /\ Filename : ICAPE2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: +// 04/30/10 - Initial version. +// 09/03/10 - Change to bus timing. +// 02/18/11 - Change DEVICE_ID default (CR593951) +// 02/10/14 - Fixed GSR deassertion (CR 772626). +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ICAPE2 ( + O, + CLK, + CSIB, + I, + RDWRB +); + parameter [31:0] DEVICE_ID = 32'h03651093; + parameter ICAP_WIDTH = "X32"; + parameter SIM_CFG_FILE_NAME = "NONE"; + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif // + + output [31:0] O; + + input CLK; + input CSIB; + input RDWRB; + input [31:0] I; + + wire cso_b; + reg prog_b; + reg init_b; + reg [3:0] bw = 4'b0000; + wire busy_out; + reg cs_bi = 0, rdwr_bi = 0; + wire cs_b_t; + wire clk_in; + wire rdwr_b_t; + wire [31:0] dix; + reg [31:0] di; + reg [31:0] data_rbt; + reg [7:0] tmp_byte0; + reg [7:0] tmp_byte1; + reg [7:0] tmp_byte2; + reg [7:0] tmp_byte3; + reg icap_idone = 0; + reg clk_osc = 0; + reg sim_file_flag; + integer icap_fd; + reg notifier; + wire delay_CLK; + wire delay_CSIB; + wire delay_RDWRB; + wire [31:0] delay_I; + tri1 p_up; + tri init_tri = (icap_idone == 0) ? init_b : p_up; + tri (weak1, strong0) done_o = p_up; + tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix; + + `ifndef XIL_TIMING + assign delay_I = I; + assign delay_RDWRB = RDWRB; + assign delay_CLK = CLK; + assign delay_CSIB = CSIB; + `endif + + assign dix = (icap_idone == 1) ? delay_I : di; + assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi; + assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc; + assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi; + assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0; + + always +// if (icap_idone == 0) + #1000 clk_osc <= ~clk_osc; + + always @(delay_CSIB or delay_RDWRB) + if ($time > 1 && icap_idone == 0) begin + $display (" Warning : ICAPE2 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time); + end + + + SIM_CONFIGE2 #( + .DEVICE_ID(DEVICE_ID), + .ICAP_SUPPORT("TRUE"), + .ICAP_WIDTH(ICAP_WIDTH) + ) + SIM_CONFIGE2_INST ( + .CSOB(cso_b), + .DONE(done_o), + .CCLK(clk_in), + .CSB(cs_b_t), + .D(di_t), + .INITB(init_tri), + .M(3'b110), + .PROGB(prog_b), + .RDWRB(rdwr_b_t) + ); + + + initial begin + + case (ICAP_WIDTH) + "X8" : bw = 4'b0000; + "X16" : bw = 4'b0010; + "X32" : bw = 4'b0011; + default : begin + $display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAPE2 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH); + end + endcase + + icap_idone = 0; + sim_file_flag = 0; + if (SIM_CFG_FILE_NAME == "NONE") begin + sim_file_flag = 1; + end + else begin + icap_fd = $fopen(SIM_CFG_FILE_NAME, "r"); + if (icap_fd == 0) + begin + $display(" Error: The configure rbt data file %s for ICAPE2 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME); + sim_file_flag = 1; + end + end + + init_b = 1; + prog_b = 1; + rdwr_bi = 0; + cs_bi = 1; + #600000; + @(posedge clk_in) + prog_b = 0; + @(negedge clk_in) + init_b = 0; + #600000; + @(posedge clk_in) + prog_b = 1; + @(negedge clk_in) begin + init_b = 1; + cs_bi = 0; + end + if (sim_file_flag == 0) begin + while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin + if (done_o == 0) begin + tmp_byte3 = bit_revers8(data_rbt[31:24]); + tmp_byte2 = bit_revers8(data_rbt[23:16]); + tmp_byte1 = bit_revers8(data_rbt[15:8]); + tmp_byte0 = bit_revers8(data_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tmp_byte3}; + @(negedge clk_in) + di = {24'b0, tmp_byte2}; + @(negedge clk_in) + di = {24'b0, tmp_byte1}; + @(negedge clk_in) + di = {24'b0, tmp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tmp_byte3, tmp_byte2}; + @(negedge clk_in) + di = {16'b0, tmp_byte1, tmp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0}; + end + end + else begin + @(negedge clk_in); + di = 32'hFFFFFFFF; + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + end + end + $fclose(icap_fd); + #1000; + end + else begin + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'h000000DD; + @(negedge clk_in) begin + if (bw == 4'b0000) + di = 32'h00000088; + else if (bw == 4'b0010) + di = 32'h00000044; + else if (bw == 4'b0011) + di = 32'h00000022; + end + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hAA995566); + rbt_data_wr(32'h30008001); + rbt_data_wr(32'h00000005); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + #1000; + end + end + + + task rbt_data_wr; + input [31:0] dat_rbt; + reg [7:0] tp_byte3; + reg [7:0] tp_byte2; + reg [7:0] tp_byte1; + reg [7:0] tp_byte0; + begin + tp_byte3 = bit_revers8(dat_rbt[31:24]); + tp_byte2 = bit_revers8(dat_rbt[23:16]); + tp_byte1 = bit_revers8(dat_rbt[15:8]); + tp_byte0 = bit_revers8(dat_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tp_byte3}; + @(negedge clk_in) + di = {24'b0, tp_byte2}; + @(negedge clk_in) + di = {24'b0, tp_byte1}; + @(negedge clk_in) + di = {24'b0, tp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tp_byte3, tp_byte2}; + @(negedge clk_in) + di = {16'b0, tp_byte1, tp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0}; + end + end + endtask + + function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end + endfunction + +specify + ( CLK => O) = (100:100:100, 100:100:100); + + `ifdef XIL_TIMING + + $period (posedge CLK, 0:0:0, notifier); + $setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB); + $setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I); + $setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB); + $setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB); + + `endif // + + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ICAPE3.v b/verilog/src/unisims/ICAPE3.v new file mode 100644 index 0000000..bdff212 --- /dev/null +++ b/verilog/src/unisims/ICAPE3.v @@ -0,0 +1,353 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2012 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.5 +// \ \ Description : +// / / +// /__/ /\ Filename : ICAPE3.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: +// 10/31/12 - Initial version. +// 02/10/14 - Fixed GSR deassertion (CR 772626). +// 02/28/14 - Updated timing (CR 778416). +// 05/28/14 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ICAPE3 #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [31:0] DEVICE_ID = 32'h03628093, + parameter ICAP_AUTO_SWITCH = "DISABLE", + parameter SIM_CFG_FILE_NAME = "NONE" +)( + output AVAIL, + output [31:0] O, + output PRDONE, + output PRERROR, + + input CLK, + input CSIB, + input [31:0] I, + input RDWRB +); + + localparam ICAP_WIDTH = "X32"; + + wire cso_b; + reg prog_b; + reg init_b; + reg [3:0] bw = 4'b0000; + wire busy_out; + reg cs_bi = 0, rdwr_bi = 0; + wire cs_b_t; + wire clk_in; + wire rdwr_b_t; + wire [31:0] dix; + wire dangle; + reg [31:0] di; + reg [31:0] data_rbt; + reg [7:0] tmp_byte0; + reg [7:0] tmp_byte1; + reg [7:0] tmp_byte2; + reg [7:0] tmp_byte3; + reg icap_idone = 0; + reg clk_osc = 0; + reg sim_file_flag; + integer icap_fd; + reg notifier; + reg AVAIL_reg = 1'b0; + wire delay_CLK; + wire delay_CSIB; + wire delay_RDWRB; + wire [31:0] delay_I; + tri1 p_up; + tri init_tri = (icap_idone == 0) ? init_b : p_up; + tri (weak1, strong0) done_o = p_up; + tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix; + localparam MODULE_NAME = "ICAPE3"; + + `ifndef XIL_TIMING + assign delay_I = I; + assign delay_RDWRB = RDWRB; + assign delay_CLK = CLK; + assign delay_CSIB = CSIB; + `endif + + assign dix = (icap_idone == 1) ? delay_I : di; + assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi; + assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc; + assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi; + assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0; + assign AVAIL = AVAIL_reg; + + + always @(posedge icap_idone) + AVAIL_reg = 1'b1; + + + always +// if (icap_idone == 0) + #1000 clk_osc <= ~clk_osc; + + always @(delay_CSIB or delay_RDWRB) + if ($time > 1 && icap_idone == 0) begin + $display ("Warning: [Unisim %s-1] ICAPE3 at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that. Instance: %m", MODULE_NAME, $time); + end + + + SIM_CONFIGE3 #( + .DEVICE_ID(DEVICE_ID), + .ICAP_SUPPORT("TRUE"), + .ICAP_WIDTH(ICAP_WIDTH) + ) + SIM_CONFIGE3_INST ( + .AVAIL(dangle), + .PRDONE(PRDONE), + .PRERROR(PRERROR), + .CSOB(cso_b), + .DONE(done_o), + .CCLK(clk_in), + .CSB(cs_b_t), + .D(di_t), + .INITB(init_tri), + .M(3'b110), + .PROGB(prog_b), + .RDWRB(rdwr_b_t) + ); + + + initial begin + + case (ICAP_AUTO_SWITCH) + "DISABLE", "ENABLE" : ; + default : begin + $display("Error: [Unisim %s-102] ICAP_AUTO_SWITCH attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, ICAP_AUTO_SWITCH); + #1 $finish; + end + endcase + + + icap_idone = 0; + sim_file_flag = 0; + if (SIM_CFG_FILE_NAME == "NONE") begin + sim_file_flag = 1; + end + else begin + icap_fd = $fopen(SIM_CFG_FILE_NAME, "r"); + if (icap_fd == 0) + begin + $display("Error: [Unisim %s-2] The configure rbt data file %s was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name. Instance: %m", MODULE_NAME, SIM_CFG_FILE_NAME); + sim_file_flag = 1; + end + end + + init_b = 1; + prog_b = 1; + rdwr_bi = 0; + cs_bi = 1; + #600000; + @(posedge clk_in) + prog_b = 0; + @(negedge clk_in) + init_b = 0; + #600000; + @(posedge clk_in) + prog_b = 1; + @(negedge clk_in) begin + init_b = 1; + cs_bi = 0; + end + if (sim_file_flag == 0) begin + while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin + if (done_o == 0) begin + tmp_byte3 = bit_revers8(data_rbt[31:24]); + tmp_byte2 = bit_revers8(data_rbt[23:16]); + tmp_byte1 = bit_revers8(data_rbt[15:8]); + tmp_byte0 = bit_revers8(data_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tmp_byte3}; + @(negedge clk_in) + di = {24'b0, tmp_byte2}; + @(negedge clk_in) + di = {24'b0, tmp_byte1}; + @(negedge clk_in) + di = {24'b0, tmp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tmp_byte3, tmp_byte2}; + @(negedge clk_in) + di = {16'b0, tmp_byte1, tmp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0}; + end + end + else begin + @(negedge clk_in); + di = 32'hFFFFFFFF; + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display ("Info: [Unisim %s-3] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time); + icap_idone = 1; + end + end + end + $fclose(icap_fd); + #1000; + end + else begin + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'h000000DD; + @(negedge clk_in) begin + if (bw == 4'b0000) + di = 32'h00000088; + else if (bw == 4'b0010) + di = 32'h00000044; + else if (bw == 4'b0011) + di = 32'h00000022; + end + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hAA995566); + rbt_data_wr(32'h30008001); + rbt_data_wr(32'h00000005); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display ("Info: [Unisim %s-4] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time); + icap_idone = 1; + end + #1000; + end + end + + + task rbt_data_wr; + input [31:0] dat_rbt; + reg [7:0] tp_byte3; + reg [7:0] tp_byte2; + reg [7:0] tp_byte1; + reg [7:0] tp_byte0; + begin + tp_byte3 = bit_revers8(dat_rbt[31:24]); + tp_byte2 = bit_revers8(dat_rbt[23:16]); + tp_byte1 = bit_revers8(dat_rbt[15:8]); + tp_byte0 = bit_revers8(dat_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tp_byte3}; + @(negedge clk_in) + di = {24'b0, tp_byte2}; + @(negedge clk_in) + di = {24'b0, tp_byte1}; + @(negedge clk_in) + di = {24'b0, tp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tp_byte3, tp_byte2}; + @(negedge clk_in) + di = {16'b0, tp_byte1, tp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0}; + end + end + endtask + + function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end + endfunction + +specify + (CLK *> O) = (100:100:100, 100:100:100); + (CLK => PRDONE) = (100:100:100, 100:100:100); + (CLK => PRERROR) = (100:100:100, 100:100:100); + + `ifdef XIL_TIMING + + $period (posedge CLK, 0:0:0, notifier); + $period (negedge CLK, 0:0:0, notifier); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB); + $setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I); + $setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB); + $setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB); + + `endif // + + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IDDR.v b/verilog/src/unisims/IDDR.v new file mode 100644 index 0000000..cb4b9d7 --- /dev/null +++ b/verilog/src/unisims/IDDR.v @@ -0,0 +1,335 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Dual Data Rate Input D Flip-Flop +// /___/ /\ Filename : IDDR.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus. +// 12/20/05 - Fixed setup and hold checks. +// 04/28/06 - Added c_in into the sensitivity list (CR 219840). +// 05/29/07 - Added wire declaration for internal signals +// 04/16/08 - CR 468871 Negative SetupHold fix +// 05/06/08 - CR 455447 add XON MSGON property to support async reg +// 12/03/08 - CR 498674 added pulldown on R/S. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 08/23/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IDDR (Q1, Q2, C, CE, D, R, S); + + output Q1; + output Q2; + + input C; + input CE; + input D; + input R; + input S; + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + +`endif + + + + pulldown P1 (R); + pulldown P2 (S); + + reg q1_out = INIT_Q1, q2_out = INIT_Q2; + reg q1_out_int, q2_out_int; + reg q1_out_pipelined, q2_out_same_edge_int; + reg notifier, notifier1, notifier2; + wire notifier1x, notifier2x; + + wire c_in,delay_c; + wire ce_in,delay_ce; + wire d_in,delay_d; + wire gsr_in; + wire r_in,delay_r; + wire s_in,delay_s; + + tri0 GSR = glbl.GSR; + + assign gsr_in = GSR; + assign Q1 = q1_out; + assign Q2 = q2_out; + + wire nr, ns, ngsr; + wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable; + wire ce_c_enable1, d_c_enable1, r_c_enable1, s_c_enable1; + not (nr, R); + not (ns, S); + not (ngsr, GSR); + + and (ce_c_enable, ngsr, nr, ns); + and (d_c_enable, ngsr, nr, ns, CE); + and (s_c_enable, ngsr, nr); + + +`ifdef XIL_TIMING + + assign notifier1x = (XON == "FALSE") ? 1'bx : notifier1; + assign notifier2x = (XON == "FALSE") ? 1'bx : notifier2; + + assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable; + assign d_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable; + assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr; + assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable; + +`endif + + + initial begin + + if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); + #1 $finish; + end + + if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2); + #1 $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + #1 $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + #1 $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q1_out_int = INIT_Q1; + assign q1_out_pipelined = INIT_Q1; + assign q2_out_same_edge_int = INIT_Q2; + assign q2_out_int = INIT_Q2; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b0; + assign q1_out_pipelined = 1'b0; + assign q2_out_same_edge_int = 1'b0; + assign q2_out_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b1; + assign q1_out_pipelined = 1'b1; + assign q2_out_same_edge_int = 1'b1; + assign q2_out_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q1_out_int <= 1'b0; + q1_out_pipelined <= 1'b0; + q2_out_same_edge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q1_out_int <= 1'b1; + q1_out_pipelined <= 1'b1; + q2_out_same_edge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q1_out_int <= d_in; + q1_out_pipelined <= q1_out_int; + q2_out_same_edge_int <= q2_out_int; + end + end // always @ (posedge c_in) + + + always @(negedge c_in) begin + if (r_in == 1'b1) + q2_out_int <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q2_out_int <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) + q2_out_int <= d_in; + end + + + always @(c_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin + case (DDR_CLK_EDGE) + "OPPOSITE_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_int; + end + "SAME_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_same_edge_int; + end + "SAME_EDGE_PIPELINED" : begin + q1_out <= q1_out_pipelined; + q2_out <= q2_out_same_edge_int; + end + default : begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + endcase // case(DDR_CLK_EDGE) + end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined) + + +`ifndef XIL_TIMING + + assign delay_c = C; + assign delay_ce = CE; + assign delay_d = D; + assign delay_r = R; + assign delay_s = S; + +`endif + assign c_in = IS_C_INVERTED ^ delay_c; + assign ce_in = delay_ce; + assign d_in = IS_D_INVERTED ^ delay_d; + assign r_in = delay_r; + assign s_in = delay_s; + + +//*** Timing Checks Start here + +`ifdef XIL_TIMING + + always @(notifier or notifier1x) begin + q1_out <= 1'bx; + end + + always @(notifier or notifier2x) begin + q2_out <= 1'bx; + end + +`endif + +`ifdef XIL_TIMING + wire c_en_n; + wire c_en_p; + wire ce_c_enable1_n,d_c_enable1_n,r_c_enable1_n,s_c_enable1_n; + wire ce_c_enable1_p,d_c_enable1_p,r_c_enable1_p,s_c_enable1_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + assign ce_c_enable1_n = ce_c_enable1 && c_en_n; + assign ce_c_enable1_p = ce_c_enable1 && c_en_p; + assign d_c_enable1_n = d_c_enable1 && c_en_n; + assign d_c_enable1_p = d_c_enable1 && c_en_p; + assign r_c_enable1_n = r_c_enable1 && c_en_n; + assign r_c_enable1_p = r_c_enable1 && c_en_p; + assign s_c_enable1_p = s_c_enable1 && c_en_p; + assign s_c_enable1_n = s_c_enable1 && c_en_n; +`endif + + specify + + (C => Q1) = (100:100:100, 100:100:100); + (C => Q2) = (100:100:100, 100:100:100); + (posedge R => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge R => (Q2 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q2 +: 0)) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + (R => Q1) = (0:0:0, 0:0:0); + (R => Q2) = (0:0:0, 0:0:0); + (S => Q1) = (0:0:0, 0:0:0); + (S => Q2) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + $recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n); + $recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n); + $recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem ( posedge R, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n); + $recrem ( posedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem ( posedge S, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n); + $recrem ( posedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $setuphold (negedge C, negedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce); + $setuphold (negedge C, negedge D &&& (d_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d); + $setuphold (negedge C, negedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r); + $setuphold (negedge C, negedge S &&& (s_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s); + $setuphold (negedge C, posedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce); + $setuphold (negedge C, posedge D &&& (d_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d); + $setuphold (negedge C, posedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r); + $setuphold (negedge C, posedge S &&& (s_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s); + $setuphold (posedge C, negedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce); + $setuphold (posedge C, negedge D &&& (d_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d); + $setuphold (posedge C, negedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r); + $setuphold (posedge C, negedge S &&& (s_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s); + $setuphold (posedge C, posedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce); + $setuphold (posedge C, posedge D &&& (d_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d); + $setuphold (posedge C, posedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r); + $setuphold (posedge C, posedge S &&& (s_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s); + $width (negedge C, 0:0:0, 0, notifier); + $width (negedge R, 0:0:0, 0, notifier); + $width (negedge S, 0:0:0, 0, notifier); + $width (posedge C, 0:0:0, 0, notifier); + $width (posedge R, 0:0:0, 0, notifier); + $width (posedge S, 0:0:0, 0, notifier); + +`endif + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule // IDDR + +`endcelldefine + diff --git a/verilog/src/unisims/IDDRE1.v b/verilog/src/unisims/IDDRE1.v new file mode 100644 index 0000000..c2ce298 --- /dev/null +++ b/verilog/src/unisims/IDDRE1.v @@ -0,0 +1,290 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Dedicated Dual Data Rate (DDR) Input Register +// /___/ /\ Filename : IDDRE1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/14 - Added #1 to $finish (CR 808642). +// 05/29/15 - Added IS_CB_INVERTED, specify block +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IDDRE1 #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", + parameter [0:0] IS_CB_INVERTED = 1'b0, + parameter [0:0] IS_C_INVERTED = 1'b0 +)( + output Q1, + output Q2, + + input C, + input CB, + input D, + input R +); + +// define constants + localparam MODULE_NAME = "IDDRE1"; + +// Parameter encodings and registers + localparam DDR_CLK_EDGE_OPPOSITE_EDGE = 0; + localparam DDR_CLK_EDGE_SAME_EDGE = 1; + localparam DDR_CLK_EDGE_SAME_EDGE_PIPELINED = 2; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "IDDRE1_dr.v" + `else + localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE; + localparam [0:0] IS_CB_INVERTED_REG = IS_CB_INVERTED; + localparam [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + `endif + + wire [1:0] DDR_CLK_EDGE_BIN; + wire IS_CB_INVERTED_BIN; + wire IS_C_INVERTED_BIN; + + `ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; + `else + reg attr_test = 1'b0; + `endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CB_in; + wire C_in; + wire D_in; + wire R_in; + +`ifdef XIL_TIMING + wire CB_delay; + wire C_delay; + wire D_delay; + wire R_delay; +`endif + + +`ifdef XIL_TIMING + assign CB_in = (CB === 1'bz) || (CB_delay ^ IS_CB_INVERTED_BIN); // rv 1 + assign C_in = C_delay ^ IS_C_INVERTED_BIN; + assign D_in = D_delay; + assign R_in = R_delay; +`else + assign CB_in = (CB === 1'bz) || (CB ^ IS_CB_INVERTED_BIN); // rv 1 + assign C_in = C ^ IS_C_INVERTED_BIN; + assign D_in = D; + assign R_in = R; +`endif + + assign DDR_CLK_EDGE_BIN = + (DDR_CLK_EDGE_REG == "OPPOSITE_EDGE") ? DDR_CLK_EDGE_OPPOSITE_EDGE : + (DDR_CLK_EDGE_REG == "SAME_EDGE") ? DDR_CLK_EDGE_SAME_EDGE : + (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? DDR_CLK_EDGE_SAME_EDGE_PIPELINED : + DDR_CLK_EDGE_OPPOSITE_EDGE; + + assign IS_CB_INVERTED_BIN = IS_CB_INVERTED_REG; + + assign IS_C_INVERTED_BIN = IS_C_INVERTED_REG; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") && + (DDR_CLK_EDGE_REG != "SAME_EDGE") && + (DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED"))) begin + $display("Error: [Unisim %s-101] DDR_CLK_EDGE attribute is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED. Instance: %m", MODULE_NAME, DDR_CLK_EDGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CB_INVERTED_REG !== 1'b0) && (IS_CB_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-103] IS_CB_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CB_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_C_INVERTED_REG !== 1'b0) && (IS_C_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-104] IS_C_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_C_INVERTED_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg Q1_out; + reg Q2_out; + + assign Q1 = Q1_out; + assign Q2 = Q2_out; + + reg q1_out_int,q1_out_pipelined,q2_out_same_edge_int,q2_out_int; + + always @(glblGSR or R_in) begin + if (glblGSR == 1'b1) begin + assign q1_out_int = 0; + assign q1_out_pipelined = 0; + assign q2_out_same_edge_int = 0; + assign q2_out_int = 0; + end else if (glblGSR == 1'b0) begin + if (R_in == 1'b1) begin + assign q1_out_int = 0; + assign q1_out_pipelined = 0; + assign q2_out_same_edge_int = 0; + assign q2_out_int = 0; + end else if (R_in == 1'b0) begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + end + end + + always @(posedge C_in) begin + if (R_in == 1'b1) begin + q1_out_int <= 1'b0; + q1_out_pipelined <= 1'b0; + q2_out_same_edge_int <= 1'b0; + end else if (R_in == 1'b0) begin + q1_out_int <= D_in; + q1_out_pipelined <= q1_out_int; + q2_out_same_edge_int <= q2_out_int; + end + end + + always @(posedge CB_in) begin + if (R_in == 1'b1) + q2_out_int <= 1'b0; + else if (R_in == 1'b0) + q2_out_int <= D_in; + end + + always @(C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin + case (DDR_CLK_EDGE_REG) + "OPPOSITE_EDGE" : begin + Q1_out <= q1_out_int; + Q2_out <= q2_out_int; + end + "SAME_EDGE" : begin + Q1_out <= q1_out_int; + Q2_out <= q2_out_same_edge_int; + end + "SAME_EDGE_PIPELINED" : begin + Q1_out <= q1_out_pipelined; + Q2_out <= q2_out_same_edge_int; + end + default : begin + $display("Error: [Unisim %s-104] Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDRE1 instance is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.Instance: %m", MODULE_NAME,DDR_CLK_EDGE); + $finish; + end + endcase // case(DDR_CLK_EDGE_REG) + end // always @ (C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) + +`ifdef XIL_TIMING + reg r_enable = 1'b1; + always @(posedge R_in) r_enable = ~glblGSR && ((Q1_out !== 1'b0) || (Q2_out !== 1'b0)); +`endif + +// end behavioral model + +`ifdef XIL_TIMING + + wire c_en_n; + wire c_en_p; + wire cb_en_n; + wire cb_en_p; + + assign c_en_n = IS_C_INVERTED_BIN; + assign c_en_p = ~IS_C_INVERTED_BIN; + assign cb_en_n = IS_CB_INVERTED_BIN; + assign cb_en_p = ~IS_CB_INVERTED_BIN; + +`endif + + specify + (C => Q1) = (100:100:100, 100:100:100); + (C => Q2) = (100:100:100, 100:100:100); + (CB => Q1) = (100:100:100, 100:100:100); + (CB => Q2) = (100:100:100, 100:100:100); + (D => Q1) = (0:0:0, 0:0:0); + (posedge R => (Q1 +: 0)) = (100:100:100, 100:100:100); + (posedge R => (Q2 +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge C, 0:0:0, notifier); + $period (negedge CB, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + $period (posedge CB, 0:0:0, notifier); + $recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, R_delay, C_delay); + $recrem (negedge R, negedge CB, 0:0:0, 0:0:0, notifier, cb_en_n, cb_en_n, R_delay, CB_delay); + $recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, R_delay, C_delay); + $recrem (negedge R, posedge CB, 0:0:0, 0:0:0, notifier, cb_en_p, cb_en_p, R_delay, CB_delay); + $recrem (posedge R, negedge C, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, R_delay, C_delay); + $recrem (posedge R, negedge CB, 0:0:0, 0:0:0, notifier, cb_en_n, cb_en_n, R_delay, CB_delay); + $recrem (posedge R, posedge C, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, R_delay, C_delay); + $recrem (posedge R, posedge CB, 0:0:0, 0:0:0, notifier, cb_en_p, cb_en_p, R_delay, CB_delay); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D_delay); + $setuphold (negedge C, negedge R, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, R_delay); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D_delay); + $setuphold (negedge C, posedge R, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, R_delay); + $setuphold (negedge CB, negedge D, 0:0:0, 0:0:0, notifier, cb_en_n, cb_en_n, CB_delay, D_delay); + $setuphold (negedge CB, posedge D, 0:0:0, 0:0:0, notifier, cb_en_n, cb_en_n, CB_delay, D_delay); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D_delay); + $setuphold (posedge C, negedge R, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, R_delay); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D_delay); + $setuphold (posedge C, posedge R, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, R_delay); + $setuphold (posedge CB, negedge D, 0:0:0, 0:0:0, notifier, cb_en_p, cb_en_p, CB_delay, D_delay); + $setuphold (posedge CB, posedge D, 0:0:0, 0:0:0, notifier, cb_en_p, cb_en_p, CB_delay, D_delay); + $width (negedge C, 0:0:0, 0, notifier); + $width (negedge CB, 0:0:0, 0, notifier); + $width (negedge R &&& r_enable, 0:0:0, 0, notifier); + $width (posedge C, 0:0:0, 0, notifier); + $width (posedge CB, 0:0:0, 0, notifier); + $width (posedge R &&& r_enable, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IDDR_2CLK.v b/verilog/src/unisims/IDDR_2CLK.v new file mode 100644 index 0000000..382ec50 --- /dev/null +++ b/verilog/src/unisims/IDDR_2CLK.v @@ -0,0 +1,333 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Input Dual Data-Rate Register with Dual Clock inputs +// /___/ /\ Filename : IDDR_2CLK.v +// \ \ / \ Timestamp : Mon Jun 26 16:44:06 PST 2006 +// \___\/\___\ +// +// Revision: +// 06/26/06 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 04/15/08 - CR 468871 Negative SetupHold fix +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 08/23/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IDDR_2CLK (Q1, Q2, C, CB, CE, D, R, S); + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_CB_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + + `ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + `endif + + output Q1; + output Q2; + + input C; + input CB; + input CE; + input D; + input R; + input S; + + reg q1_out = INIT_Q1, q2_out = INIT_Q2; + reg q1_out_int, q2_out_int; + reg q1_out_pipelined, q2_out_same_edge_int; + reg notifier, notifier1, notifier2; + + wire c_in,delay_c; + wire cb_in,delay_cb; + wire ce_in,delay_ce; + wire d_in,delay_d; + wire gsr_in; + wire r_in,delay_r; + wire s_in,delay_s; + + tri0 GSR = glbl.GSR; + + `ifndef XIL_TIMING + assign delay_c = C; + assign delay_cb = CB; + assign delay_ce = CE; + assign delay_d = D; + assign delay_r = R; + assign delay_s = S; + `endif + + //buf buf_c (c_in, C); + //buf buf_cb (cb_in, CB); + assign c_in = IS_C_INVERTED ^ delay_c; + assign cb_in = (CB === 1'bz) || (IS_CB_INVERTED ^ delay_cb); // rv 1 + + buf buf_ce (ce_in, delay_ce); + //buf buf_d (d_in, D); + assign d_in = IS_D_INVERTED ^ delay_d; + buf buf_gsr (gsr_in, GSR); + buf buf_q1 (Q1, q1_out); + buf buf_q2 (Q2, q2_out); + buf buf_r (r_in, delay_r); + buf buf_s (s_in, delay_s); + + + initial begin + + if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); + #1 $finish; + end + + if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2); + #1 $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + #1 $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + #1 $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q1_out_int = INIT_Q1; + assign q1_out_pipelined = INIT_Q1; + assign q2_out_same_edge_int = INIT_Q2; + assign q2_out_int = INIT_Q2; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b0; + assign q1_out_pipelined = 1'b0; + assign q2_out_same_edge_int = 1'b0; + assign q2_out_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b1; + assign q1_out_pipelined = 1'b1; + assign q2_out_same_edge_int = 1'b1; + assign q2_out_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q1_out_int <= 1'b0; + q1_out_pipelined <= 1'b0; + q2_out_same_edge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q1_out_int <= 1'b1; + q1_out_pipelined <= 1'b1; + q2_out_same_edge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q1_out_int <= d_in; + q1_out_pipelined <= q1_out_int; + q2_out_same_edge_int <= q2_out_int; + end + end // always @ (posedge c_in) + + + always @(posedge cb_in) begin + if (r_in == 1'b1) + q2_out_int <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q2_out_int <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) + q2_out_int <= d_in; + end // always @ (posedge cb_in) + + + always @(posedge c_in or posedge cb_in, q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin + case (DDR_CLK_EDGE) + "OPPOSITE_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_int; + end + "SAME_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_same_edge_int; + end + "SAME_EDGE_PIPELINED" : begin + q1_out <= q1_out_pipelined; + q2_out <= q2_out_same_edge_int; + end + default : begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + endcase // case(DDR_CLK_EDGE) + end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined) + +`ifndef XIL_TIMING + specify + + (C => Q1) = (100, 100); + (C => Q2) = (100, 100); + (CB => Q1) = (100, 100); + (CB => Q2) = (100, 100); + (posedge R => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge R => (Q2 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q2 +: 0)) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING + +//*** Timing Checks Start here + + always @(notifier or notifier1) begin + q1_out <= 1'bx; + end + + always @(notifier or notifier2) begin + q2_out <= 1'bx; + end + wire c_en_n; + wire c_en_p; + wire cb_en_n; + wire cb_en_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + assign cb_en_n = IS_CB_INVERTED; + assign cb_en_p = ~IS_CB_INVERTED; + + specify + + (C => Q1) = (100:100:100, 100:100:100); + (C => Q2) = (100:100:100, 100:100:100); + (CB => Q1) = (100:100:100, 100:100:100); + (CB => Q2) = (100:100:100, 100:100:100); + (R => Q1) = (0:0:0, 0:0:0); + (R => Q2) = (0:0:0, 0:0:0); + (S => Q1) = (0:0:0, 0:0:0); + (S => Q2) = (0:0:0, 0:0:0); + (posedge R => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge R => (Q2 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q1 +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q2 +: 0)) = (0:0:0, 0:0:0); + $period (negedge C, 0:0:0, notifier); + $period (negedge CB, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + $period (posedge CB, 0:0:0, notifier); + $recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n); + $recrem (negedge R, negedge CB, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n); + $recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem (negedge R, posedge CB, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p); + $recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n); + $recrem (negedge S, negedge CB, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n); + $recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem (negedge S, posedge CB, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p); + $recrem ( posedge R, negedge C, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n); + $recrem ( posedge R, negedge CB, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n); + $recrem ( posedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem ( posedge R, posedge CB, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p); + $recrem ( posedge S, negedge C, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n); + $recrem ( posedge S, negedge CB, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n); + $recrem ( posedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p); + $recrem ( posedge S, posedge CB, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_d); + $setuphold (negedge C, negedge R, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_r); + $setuphold (negedge C, negedge S, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_s); + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_d); + $setuphold (negedge C, posedge R, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_r); + $setuphold (negedge C, posedge S, 0:0:0, 0:0:0, notifier1, c_en_n, c_en_n, delay_c, delay_s); + $setuphold (negedge CB, negedge CE, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_ce); + $setuphold (negedge CB, negedge D, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_d); + $setuphold (negedge CB, negedge R, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_r); + $setuphold (negedge CB, negedge S, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_s); + $setuphold (negedge CB, posedge CE, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_ce); + $setuphold (negedge CB, posedge D, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_d); + $setuphold (negedge CB, posedge R, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_r); + $setuphold (negedge CB, posedge S, 0:0:0, 0:0:0, notifier2, cb_en_n, cb_en_n, delay_cb, delay_s); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_d); + $setuphold (posedge C, negedge R, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_r); + $setuphold (posedge C, negedge S, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_s); + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_d); + $setuphold (posedge C, posedge R, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_r); + $setuphold (posedge C, posedge S, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p, delay_c, delay_s); + $setuphold (posedge CB, negedge CE, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_ce); + $setuphold (posedge CB, negedge D, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_d); + $setuphold (posedge CB, negedge R, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_r); + $setuphold (posedge CB, negedge S, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_s); + $setuphold (posedge CB, posedge CE, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_ce); + $setuphold (posedge CB, posedge D, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_d); + $setuphold (posedge CB, posedge R, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_r); + $setuphold (posedge CB, posedge S, 0:0:0, 0:0:0, notifier2, cb_en_p, cb_en_p, delay_cb, delay_s); + $width (negedge C, 0:0:0, 0, notifier); + $width (negedge CB, 0:0:0, 0, notifier); + $width (negedge R, 0:0:0, 0, notifier); + $width (negedge S, 0:0:0, 0, notifier); + $width (posedge C, 0:0:0, 0, notifier); + $width (posedge CB, 0:0:0, 0, notifier); + $width (posedge R, 0:0:0, 0, notifier); + $width (posedge S, 0:0:0, 0, notifier); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifdef XIL_TIMING + + +endmodule // IDDR_2CLK + +`endcelldefine diff --git a/verilog/src/unisims/IDELAYCTRL.v b/verilog/src/unisims/IDELAYCTRL.v new file mode 100644 index 0000000..0a786ce --- /dev/null +++ b/verilog/src/unisims/IDELAYCTRL.v @@ -0,0 +1,209 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / IDELAYE3/ODELAYE3 Tap Delay Value Control +// /___/ /\ Filename : IDELAYCTRL.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter and initialized outpus. +// 04/10/07 - CR 436682 fix, disable activity when rst is high +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 06/01/15 - 850338 - Added SIM_DEVICE and warning +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IDELAYCTRL #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "7SERIES" +)( + output RDY, + + input REFCLK, + input RST +); + +// define constants + localparam MODULE_NAME = "IDELAYCTRL"; + +// Parameter encodings and registers + localparam SIM_DEVICE_7SERIES = 0; + localparam SIM_DEVICE_ULTRASCALE = 1; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +//`ifdef XIL_DR +// `include "IDELAYCTRL_dr.v" +//`else + localparam [80:1] SIM_DEVICE_REG = SIM_DEVICE; +//`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + reg RDY_out = 0; + + wire REFCLK_in; + wire RST_in; + +`ifdef XIL_TIMING + wire REFCLK_delay; + wire RST_delay; +`endif + + assign RDY = RDY_out; + +`ifdef XIL_TIMING + assign REFCLK_in = REFCLK_delay; + assign RST_in = RST_delay; +`else + assign REFCLK_in = REFCLK; + assign RST_in = RST; +`endif + + time clock_edge; + reg [63:0] period; + reg clock_low, clock_high; + reg clock_posedge, clock_negedge; + reg lost; + reg msg_flag = 1'b0; + + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "7SERIES") && + (SIM_DEVICE_REG != "ULTRASCALE"))) begin + $display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + always @(RST_in, lost) begin + + if (RST_in == 1'b1) begin + RDY_out <= 1'b0; + end else if (lost == 1) + RDY_out <= 1'b0; + else if (RST_in == 1'b0 && lost == 0) + RDY_out <= 1'b1; + end + + always @(posedge RST_in) begin + if (SIM_DEVICE_REG == "ULTRASCALE" && msg_flag == 1'b0) begin + $display("Info: [Unisim %s-1] RST simulation behaviour for SIM_DEVICE %s may not match hardware behaviour when I/ODELAY DELAY_FORMAT = TIME if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + msg_flag <= 1'b1; + end + end + initial begin + clock_edge <= 0; + clock_high <= 0; + clock_low <= 0; + lost <= 1; + period <= 0; + end + + + always @(posedge REFCLK_in) begin + if(RST_in == 1'b0) begin + clock_edge <= $time; + if (period != 0 && (($time - clock_edge) <= (1.5 * period))) + period <= $time - clock_edge; + else if (period != 0 && (($time - clock_edge) > (1.5 * period))) + period <= 0; + else if ((period == 0) && (clock_edge != 0)) + period <= $time - clock_edge; + end + end + + always @(posedge REFCLK_in) begin + clock_low <= 1'b0; + clock_high <= 1'b1; + if (period != 0) + lost <= 1'b0; + clock_posedge <= 1'b0; + #((period * 9.1) / 10) + if ((clock_low != 1'b1) && (clock_posedge != 1'b1)) + lost <= 1; + end + + always @(posedge REFCLK_in) begin + clock_negedge <= 1'b1; + end + + always @(negedge REFCLK_in) begin + clock_posedge <= 1'b1; + end + + always @(negedge REFCLK_in) begin + clock_high <= 1'b0; + clock_low <= 1'b1; + if (period != 0) + lost <= 1'b0; + clock_negedge <= 1'b0; + #((period * 9.1) / 10) + if ((clock_high != 1'b1) && (clock_negedge != 1'b1)) + lost <= 1; + end + +//*** Timing Checks Start here +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (RST => RDY) = (0:0:0, 0:0:0); + (posedge RST => (RDY +: 0)) = (0:0:0, 0:0:0); + (REFCLK => RDY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge REFCLK, 0:0:0, notifier); + $period (posedge REFCLK, 0:0:0, notifier); + $recrem (negedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay); + $recrem (posedge RST, posedge REFCLK, 0:0:0, 0:0:0, notifier, , , RST_delay, REFCLK_delay); + $width (negedge REFCLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge REFCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IDELAYE2.v b/verilog/src/unisims/IDELAYE2.v new file mode 100644 index 0000000..294b33e --- /dev/null +++ b/verilog/src/unisims/IDELAYE2.v @@ -0,0 +1,593 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / Input Fixed or Variable Delay Element. +// /___/ /\ Filename : IDELAYE2.v +// \ \ / \ Timestamp : Sat Sep 19 14:17:57 PDT 2009 +// \___\/\___\ +// +// Revision: +// 09/19/09 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IDELAYE2 (CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN, REGRST); + + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "IDATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "FIXED"; + parameter integer IDELAY_VALUE = 0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_DATAIN_INVERTED = 1'b0; + parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + parameter integer SIM_DELAY_D = 0; + localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0; +`endif // ifdef XIL_TIMING + +`ifndef XIL_TIMING + integer DELAY_D=0; +`endif // ifndef XIL_TIMING + + output [4:0] CNTVALUEOUT; + output DATAOUT; + + input C; + input CE; + input CINVCTRL; + input [4:0] CNTVALUEIN; + input DATAIN; + input IDATAIN; + input INC; + input LD; + input LDPIPEEN; + input REGRST; + + + tri0 GSR = glbl.GSR; + real CALC_TAPDELAY ; + real INIT_DELAY; + +//------------------- constants ------------------------------------ + + localparam MAX_DELAY_COUNT = 31; + localparam MIN_DELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCYL = 210.0; + localparam MIN_REFCLK_FREQUENCYL = 190.0; + + localparam MAX_REFCLK_FREQUENCYH = 410.0; + localparam MIN_REFCLK_FREQUENCYH = 290.0; + + +//------------------- variable declaration ------------------------- + + integer idelay_count; + integer CNTVALUEIN_INTEGER; + reg [4:0] cntvalueout_pre; + + reg notifier; + + reg data_mux = 0; + reg tap_out = 0; + reg DATAOUT_reg = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31; + + reg c_in; + wire ce_in,delay_CE,delay_C; + wire clkin_in; + wire [4:0] cntvaluein_in,delay_CNTVALUEIN; + wire datain_in,delay_DATAIN; + wire gsr_in; + wire idatain_in,delay_IDATAIN; + wire inc_in,delay_INC; + wire odatain_in; + wire ld_in,delay_LD; + wire t_in; + wire cinvctrl_in,delay_CINVCTRL; + wire ldpipeen_in,delay_LDPIPEEN; + wire regrst_in,delay_REGRST; + + wire c_in_pre; + + reg [4:0] qcntvalueout_reg = 5'b0; + reg [4:0] qcntvalueout_mux = 5'b0; + + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- +// CR 587496 +// assign #INIT_DELAY DATAOUT = tap_out; + always @(tap_out) + DATAOUT_reg <= #INIT_DELAY tap_out; + + assign DATAOUT = DATAOUT_reg; + + assign CNTVALUEOUT = cntvalueout_pre; + +`ifndef XIL_TIMING +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign delay_C = C; + assign delay_CE = CE; + assign delay_CNTVALUEIN = CNTVALUEIN; + assign delay_INC = INC; + assign delay_LD = LD; + assign delay_LDPIPEEN = LDPIPEEN; + assign delay_REGRST = REGRST; +`endif // ifndef XIL_TIMING + assign delay_CINVCTRL = CINVCTRL; + assign delay_DATAIN = DATAIN; + assign delay_IDATAIN = IDATAIN; + assign gsr_in = GSR; + + assign c_in_pre = delay_C ^ IS_C_INVERTED; + assign ce_in = delay_CE; + assign cntvaluein_in = delay_CNTVALUEIN; + assign inc_in = delay_INC; + assign ld_in = delay_LD; + assign ldpipeen_in = delay_LDPIPEEN; + assign regrst_in = delay_REGRST; + assign cinvctrl_in = delay_CINVCTRL; + assign datain_in = IS_DATAIN_INVERTED ^ delay_DATAIN; + assign idatain_in = IS_IDATAIN_INVERTED ^ delay_IDATAIN; + + + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin +// For simprims, the fixed/Default Delay values are taken from the sdf. + // if (IDELAY_TYPE == "FIXED") + // assign idelay_count = 0; + // else + // assign idelay_count = IDELAY_VALUE; + case (IDELAY_TYPE) + "VAR_LOAD", "VAR_LOAD_PIPE": assign idelay_count = 0; + "FIXED", "VARIABLE" : assign idelay_count = IDELAY_VALUE; + endcase + end + else if (gsr_in == 1'b0) begin + deassign idelay_count; + end + end + + +//------------------------------------------------------------ +//--------------------- Initialization -------------------- +//------------------------------------------------------------ + + initial begin + + //-------- CINVCTRL_SEL check + + case (CINVCTRL_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CINVCTRL_SEL on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL); + #1 $finish; + end + endcase + + //-------- DELAY_SRC check + + if (DELAY_SRC != "DATAIN" && DELAY_SRC != "IDATAIN") begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC); + #1 $finish; + end + + + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + #1 $finish; + end + endcase + + + //-------- IDELAY_TYPE check + + if (IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE" && IDELAY_TYPE != "VAR_LOAD" && IDELAY_TYPE != "VAR_LOAD_PIPE") begin + + $display("Attribute Syntax Error : The attribute IDELAY_TYPE on IDELAYE2 instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", IDELAY_TYPE); + #1 $finish; + + end + + + //-------- IDELAY_VALUE check + + if (IDELAY_VALUE < MIN_DELAY_COUNT || IDELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute IDELAY_VALUE on IDELAYE2 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", IDELAY_VALUE); + #1 $finish; + + end + + //-------- PIPE_SEL check + + case (PIPE_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute PIPE_SEL on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL); + #1 $finish; + end + endcase + + + //-------- REFCLK_FREQUENCY check + + if ((REFCLK_FREQUENCY >= 190.0 && REFCLK_FREQUENCY <= 210.0) || + (REFCLK_FREQUENCY >= 290.0 && REFCLK_FREQUENCY <= 310.0) || + (REFCLK_FREQUENCY >=390.0 && REFCLK_FREQUENCY <= 410.0)) + /* */; + else begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IDELAYE2 instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0 or between 390.0 and 410.0", REFCLK_FREQUENCY); + #1 $finish; + end + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IDELAYE2 instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + #1 $finish; + end + endcase + + + //-------- CALC_TAPDELAY check + + INIT_DELAY = 600; + + end // initial begin + + // CALC_TAPDELAY value + initial begin + if ((REFCLK_FREQUENCY <= 410.0) && (REFCLK_FREQUENCY >= 390.0)) + begin + CALC_TAPDELAY = 39; + end + else if ((REFCLK_FREQUENCY <= 310.0) && (REFCLK_FREQUENCY >= 290.0)) + begin + CALC_TAPDELAY = 52; + end + else + begin + CALC_TAPDELAY = 78; + end + end + +//---------------------------------------------------------------------- +//------------------------ Dynamic clock inversion --------------------- +//---------------------------------------------------------------------- + +// always @(c_in_pre or cinvctrl_in) begin +// case (CINVCTRL_SEL) +// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); +// "FALSE" : c_in = c_in_pre; +// endcase +// end + + generate + case (CINVCTRL_SEL) + "TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); + "FALSE" : always @(c_in_pre) c_in = c_in_pre; + endcase + endgenerate + +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- + always @(idelay_count) begin +// Fixed CNTVALUEOUT for when in FIXED mode because of simprim. + if(IDELAY_TYPE != "FIXED") + assign cntvalueout_pre = idelay_count; + else + assign cntvalueout_pre = IDELAY_VALUE; + end + +//---------------------------------------------------------------------- +//-------------------------- CNTVALUEIN LOAD -------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + if (regrst_in == 1'b1) + qcntvalueout_reg = 5'b0; + else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin + qcntvalueout_reg = CNTVALUEIN_INTEGER; + end + end // always @(posedge c_in) + + generate + case (PIPE_SEL) + "TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg; + "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; + endcase + endgenerate + +//---------------------------------------------------------------------- +//-------------------------- IDELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + + if (IDELAY_TYPE == "VARIABLE" | IDELAY_TYPE == "VAR_LOAD" | IDELAY_TYPE == "VAR_LOAD_PIPE") begin + if (ld_in == 1'b1) begin + case (IDELAY_TYPE) + "VARIABLE" : idelay_count = IDELAY_VALUE; + "VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux; + endcase + end + else if (ld_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + case (IDELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (idelay_count < MAX_DELAY_COUNT) + idelay_count = idelay_count + 1; + else if (idelay_count == MAX_DELAY_COUNT) + idelay_count = MIN_DELAY_COUNT; + end + endcase + end + else if (inc_in == 1'b0) begin + case (IDELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (idelay_count > MIN_DELAY_COUNT) + idelay_count = idelay_count - 1; + else if (idelay_count == MIN_DELAY_COUNT) + idelay_count = MAX_DELAY_COUNT; + end + endcase + end + end + end // + end // always @ (posedge c_in) + + always @(cntvaluein_in or gsr_in) begin + case (cntvaluein_in) + 5'b00000 : assign CNTVALUEIN_INTEGER = 0; + 5'b00001 : assign CNTVALUEIN_INTEGER = 1; + 5'b00010 : assign CNTVALUEIN_INTEGER = 2; + 5'b00011 : assign CNTVALUEIN_INTEGER = 3; + 5'b00100 : assign CNTVALUEIN_INTEGER = 4; + 5'b00101 : assign CNTVALUEIN_INTEGER = 5; + 5'b00110 : assign CNTVALUEIN_INTEGER = 6; + 5'b00111 : assign CNTVALUEIN_INTEGER = 7; + 5'b01000 : assign CNTVALUEIN_INTEGER = 8; + 5'b01001 : assign CNTVALUEIN_INTEGER = 9; + 5'b01010 : assign CNTVALUEIN_INTEGER = 10; + 5'b01011 : assign CNTVALUEIN_INTEGER = 11; + 5'b01100 : assign CNTVALUEIN_INTEGER = 12; + 5'b01101 : assign CNTVALUEIN_INTEGER = 13; + 5'b01110 : assign CNTVALUEIN_INTEGER = 14; + 5'b01111 : assign CNTVALUEIN_INTEGER = 15; + 5'b10000 : assign CNTVALUEIN_INTEGER = 16; + 5'b10001 : assign CNTVALUEIN_INTEGER = 17; + 5'b10010 : assign CNTVALUEIN_INTEGER = 18; + 5'b10011 : assign CNTVALUEIN_INTEGER = 19; + 5'b10100 : assign CNTVALUEIN_INTEGER = 20; + 5'b10101 : assign CNTVALUEIN_INTEGER = 21; + 5'b10110 : assign CNTVALUEIN_INTEGER = 22; + 5'b10111 : assign CNTVALUEIN_INTEGER = 23; + 5'b11000 : assign CNTVALUEIN_INTEGER = 24; + 5'b11001 : assign CNTVALUEIN_INTEGER = 25; + 5'b11010 : assign CNTVALUEIN_INTEGER = 26; + 5'b11011 : assign CNTVALUEIN_INTEGER = 27; + 5'b11100 : assign CNTVALUEIN_INTEGER = 28; + 5'b11101 : assign CNTVALUEIN_INTEGER = 29; + 5'b11110 : assign CNTVALUEIN_INTEGER = 30; + 5'b11111 : assign CNTVALUEIN_INTEGER = 31; + endcase + end + + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(datain_in or idatain_in) begin + + case (DELAY_SRC) + + "IDATAIN" : begin + data_mux <= idatain_in; + end + "DATAIN" : begin + data_mux <= datain_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on X_IODELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @(datain_in or idatain_in) + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* + assign #(DELAY_D) delay_chain_0 = data_mux; + assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(idelay_count) begin + case (idelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + end // always @ (idelay_count) + +`ifdef XIL_TIMING + wire c_en_n; + wire c_en_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + + wire d_en; + wire id_en; + assign d_en = (idelay_count == 0) && (DELAY_SRC == "DATAIN"); + assign id_en = (idelay_count == 0) && (DELAY_SRC == "IDATAIN"); + +//*** Timing Checks Start here + + always @(notifier) begin + tap_out <= 1'bx; + end +`endif // ifdef XIL_TIMING + + +`ifdef XIL_TIMING + specify + + ( C *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( C => DATAOUT) = (0:0:0, 0:0:0); + ( CINVCTRL *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( CINVCTRL => DATAOUT) = (0:0:0, 0:0:0); + if (d_en) ( DATAIN => DATAOUT) = (0:0:0, 0:0:0); + if (id_en) ( IDATAIN => DATAOUT) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CE); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CE); + $setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_INC); + $setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_INC); + $setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LD); + $setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LD); + $setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CNTVALUEIN); + $setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CNTVALUEIN); + $setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LDPIPEEN); + $setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LDPIPEEN); + $setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_REGRST); + $setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_REGRST); + + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CE); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CE); + $setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_INC); + $setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_INC); + $setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LD); + $setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LD); + $setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CNTVALUEIN); + $setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CNTVALUEIN); + $setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LDPIPEEN); + $setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LDPIPEEN); + $setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_REGRST); + $setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_REGRST); + + + + specparam PATHPULSE$ = 0; + + endspecify +`endif // ifdef XIL_TIMING + +endmodule // IDELAYE2 + +`endcelldefine diff --git a/verilog/src/unisims/IDELAYE2_FINEDELAY.v b/verilog/src/unisims/IDELAYE2_FINEDELAY.v new file mode 100644 index 0000000..ede34fc --- /dev/null +++ b/verilog/src/unisims/IDELAYE2_FINEDELAY.v @@ -0,0 +1,660 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / Input Fixed or Variable Delay Element with Fine Adjustment. +// /___/ /\ Filename : IDELAYE2_FINEDELAY.v +// \ \ / \ Timestamp : Tue Feb 15 15:52:17 PST 2011 +// \___\/\___\ +// +// Revision: +// 02/15/11 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IDELAYE2_FINEDELAY ( + CNTVALUEOUT, + DATAOUT, + + C, + CE, + CINVCTRL, + CNTVALUEIN, + DATAIN, + IDATAIN, + IFDLY, + INC, + LD, + LDPIPEEN, + REGRST +); + + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "IDATAIN"; + parameter FINEDELAY = "BYPASS"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "FIXED"; + parameter integer IDELAY_VALUE = 0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_DATAIN_INVERTED = 1'b0; + parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + parameter integer SIM_DELAY_D = 0; + localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0; +`endif // ifdef XIL_TIMING + +`ifndef XIL_TIMING + integer DELAY_D=0; +`endif // ifndef XIL_TIMING + + output [4:0] CNTVALUEOUT; + output DATAOUT; + + input C; + input CE; + input CINVCTRL; + input [4:0] CNTVALUEIN; + input DATAIN; + input IDATAIN; + input [2:0] IFDLY; + input INC; + input LD; + input LDPIPEEN; + input REGRST; + + + tri0 GSR = glbl.GSR; + + real CALC_TAPDELAY_RD ; // regular tap delay + real CALC_TAPDELAY_FD ; // fine tap delay + real INIT_DELAY_RD; + real INIT_DELAY_FD; + +//------------------- constants ------------------------------------ + + localparam MAX_DELAY_COUNT = 31; + localparam MIN_DELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCYL = 210.0; + localparam MIN_REFCLK_FREQUENCYL = 190.0; + + localparam MAX_REFCLK_FREQUENCYH = 410.0; + localparam MIN_REFCLK_FREQUENCYH = 290.0; + + +//------------------- variable declaration ------------------------- + + integer idelay_count; + integer CNTVALUEIN_INTEGER; + reg [4:0] cntvalueout_pre; + + reg notifier; + + reg data_mux = 0; + reg tap_out_rd = 0; + reg tap_out_fd = 0; + reg tap_out_final = 0; + reg DATAOUT_reg = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31; + + wire fine_delay_0, fine_delay_1, fine_delay_2, fine_delay_3, fine_delay_4, fine_delay_5; + + reg c_in; + wire ce_in,delay_ce,delay_c; + wire clkin_in; + wire [4:0] cntvaluein_in,delay_cntvaluein; + wire datain_in,delay_datain; + wire [2:0] ifdly_in,delay_ifdly; + wire gsr_in; + wire idatain_in,delay_idatain; + wire inc_in,delay_inc; + wire odatain_in; + wire ld_in,delay_ld; + wire t_in; + wire cinvctrl_in,delay_cinvctrl; + wire ldpipeen_in,delay_ldpipeen; + wire regrst_in,delay_regrst; + + wire c_in_pre; + + reg [4:0] qcntvalueout_reg = 5'b0; + reg [4:0] qcntvalueout_mux = 5'b0; + + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- + + generate + case (FINEDELAY) + "BYPASS" : always @(tap_out_rd) tap_out_final = tap_out_rd; + "ADD_DLY" : always @(tap_out_fd) tap_out_final = tap_out_fd; + endcase + endgenerate + +// CR 587496 +// assign #INIT_DELAY DATAOUT = tap_out_final; + always @(tap_out_final) + DATAOUT_reg <= #INIT_DELAY_RD tap_out_final; + + assign DATAOUT = DATAOUT_reg; + + assign CNTVALUEOUT = cntvalueout_pre; + +`ifndef XIL_TIMING +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign delay_c = C; + assign delay_ce = CE; + assign delay_cntvaluein = CNTVALUEIN; + assign delay_inc = INC; + assign delay_ld = LD; + assign delay_ldpipeen = LDPIPEEN; + assign delay_regrst = REGRST; +`endif // ifndef XIL_TIMING + assign delay_cinvctrl = CINVCTRL; + assign delay_datain = DATAIN; + assign delay_ifdly = IFDLY; + assign delay_idatain = IDATAIN; + assign gsr_in = GSR; + + assign c_in_pre = IS_C_INVERTED ^ delay_c; + assign ce_in = delay_ce; + assign cntvaluein_in = delay_cntvaluein; + assign inc_in = delay_inc; + assign ld_in = delay_ld; + assign ldpipeen_in = delay_ldpipeen; + assign regrst_in = delay_regrst; + assign cinvctrl_in = delay_cinvctrl; + assign datain_in = IS_DATAIN_INVERTED ^ delay_datain; + assign ifdly_in = delay_ifdly; + assign idatain_in = IS_IDATAIN_INVERTED ^ delay_idatain; + + + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin +// For simprims, the fixed/Default Delay values are taken from the sdf. + if (IDELAY_TYPE == "FIXED") + assign idelay_count = 0; + else + assign idelay_count = IDELAY_VALUE; + end + else if (gsr_in == 1'b0) begin + deassign idelay_count; + end + end + + +//------------------------------------------------------------ +//--------------------- Initialization -------------------- +//------------------------------------------------------------ + + initial begin + + //-------- CINVCTRL_SEL check + + case (CINVCTRL_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CINVCTRL_SEL on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL); + #1 $finish; + end + endcase + + //-------- DELAY_SRC check + + if (DELAY_SRC != "DATAIN" && DELAY_SRC != "IDATAIN") begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC); + #1 $finish; + end + + + //-------- FINEDELAY check + + if (FINEDELAY != "BYPASS" && FINEDELAY != "ADD_DLY") begin + $display("Attribute Syntax Error : The attribute FINEDELAY on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are BYPASS or ADD_DLY", FINEDELAY); + #1 $finish; + end + + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + #1 $finish; + end + endcase + + + //-------- IDELAY_TYPE check + + if (IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE" && IDELAY_TYPE != "VAR_LOAD" && IDELAY_TYPE != "VAR_LOAD_PIPE") begin + + $display("Attribute Syntax Error : The attribute IDELAY_TYPE on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", IDELAY_TYPE); + #1 $finish; + + end + + + //-------- IDELAY_VALUE check + + if (IDELAY_VALUE < MIN_DELAY_COUNT || IDELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute IDELAY_VALUE on IDELAYE2_FINEDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", IDELAY_VALUE); + #1 $finish; + + end + + //-------- PIPE_SEL check + + case (PIPE_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute PIPE_SEL on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL); + #1 $finish; + end + endcase + + + //-------- REFCLK_FREQUENCY check + + if ((REFCLK_FREQUENCY >= 190.0 && REFCLK_FREQUENCY <= 210.0) || + (REFCLK_FREQUENCY >= 290.0 && REFCLK_FREQUENCY <= 310.0) || + (REFCLK_FREQUENCY >=390.0 && REFCLK_FREQUENCY <= 410.0)) + /* */; + else begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IDELAYE2_FINEDELAY instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0 or between 390.0 and 410.0", REFCLK_FREQUENCY); + #1 $finish; + end + + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + #1 $finish; + end + endcase + + + //-------- CALC_TAPDELAY check + + INIT_DELAY_RD = 600; //regular delay + INIT_DELAY_FD = 40; //fine delay + + end // initial begin + + // CALC_TAPDELAY value + initial begin + if ((REFCLK_FREQUENCY <= 410.0) && (REFCLK_FREQUENCY >= 390.0)) + begin + CALC_TAPDELAY_RD = 39; + end + else if ((REFCLK_FREQUENCY <= 310.0) && (REFCLK_FREQUENCY >= 290.0)) + begin + CALC_TAPDELAY_RD = 52; + end + else + begin + CALC_TAPDELAY_RD = 78; + end + + CALC_TAPDELAY_FD = 10; //fine delay + end + +//---------------------------------------------------------------------- +//------------------------ Dynamic clock inversion --------------------- +//---------------------------------------------------------------------- + +// always @(c_in_pre or cinvctrl_in) begin +// case (CINVCTRL_SEL) +// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); +// "FALSE" : c_in = c_in_pre; +// endcase +// end + + generate + case (CINVCTRL_SEL) + "TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); + "FALSE" : always @(c_in_pre) c_in = c_in_pre; + endcase + endgenerate + +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- + always @(idelay_count) begin +// Fixed CNTVALUEOUT for when in FIXED mode because of simprim. + if(IDELAY_TYPE != "FIXED") + assign cntvalueout_pre = idelay_count; + else + assign cntvalueout_pre = IDELAY_VALUE; + end + +//---------------------------------------------------------------------- +//-------------------------- CNTVALUEIN LOAD -------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + if (regrst_in == 1'b1) + qcntvalueout_reg = 5'b0; + else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin + qcntvalueout_reg = CNTVALUEIN_INTEGER; + end + end // always @(posedge c_in) + + generate + case (PIPE_SEL) + "TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg; + "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; + endcase + endgenerate + +//---------------------------------------------------------------------- +//-------------------------- IDELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + + if (IDELAY_TYPE == "VARIABLE" | IDELAY_TYPE == "VAR_LOAD" | IDELAY_TYPE == "VAR_LOAD_PIPE") begin + if (ld_in == 1'b1) begin + case (IDELAY_TYPE) + "VARIABLE" : idelay_count = IDELAY_VALUE; + "VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux; + endcase + end + else if (ld_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + case (IDELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (idelay_count < MAX_DELAY_COUNT) + idelay_count = idelay_count + 1; + else if (idelay_count == MAX_DELAY_COUNT) + idelay_count = MIN_DELAY_COUNT; + end + endcase + end + else if (inc_in == 1'b0) begin + case (IDELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (idelay_count > MIN_DELAY_COUNT) + idelay_count = idelay_count - 1; + else if (idelay_count == MIN_DELAY_COUNT) + idelay_count = MAX_DELAY_COUNT; + end + endcase + end + end + end // + end // always @ (posedge c_in) + + always @(cntvaluein_in or gsr_in) begin + case (cntvaluein_in) + 5'b00000 : assign CNTVALUEIN_INTEGER = 0; + 5'b00001 : assign CNTVALUEIN_INTEGER = 1; + 5'b00010 : assign CNTVALUEIN_INTEGER = 2; + 5'b00011 : assign CNTVALUEIN_INTEGER = 3; + 5'b00100 : assign CNTVALUEIN_INTEGER = 4; + 5'b00101 : assign CNTVALUEIN_INTEGER = 5; + 5'b00110 : assign CNTVALUEIN_INTEGER = 6; + 5'b00111 : assign CNTVALUEIN_INTEGER = 7; + 5'b01000 : assign CNTVALUEIN_INTEGER = 8; + 5'b01001 : assign CNTVALUEIN_INTEGER = 9; + 5'b01010 : assign CNTVALUEIN_INTEGER = 10; + 5'b01011 : assign CNTVALUEIN_INTEGER = 11; + 5'b01100 : assign CNTVALUEIN_INTEGER = 12; + 5'b01101 : assign CNTVALUEIN_INTEGER = 13; + 5'b01110 : assign CNTVALUEIN_INTEGER = 14; + 5'b01111 : assign CNTVALUEIN_INTEGER = 15; + 5'b10000 : assign CNTVALUEIN_INTEGER = 16; + 5'b10001 : assign CNTVALUEIN_INTEGER = 17; + 5'b10010 : assign CNTVALUEIN_INTEGER = 18; + 5'b10011 : assign CNTVALUEIN_INTEGER = 19; + 5'b10100 : assign CNTVALUEIN_INTEGER = 20; + 5'b10101 : assign CNTVALUEIN_INTEGER = 21; + 5'b10110 : assign CNTVALUEIN_INTEGER = 22; + 5'b10111 : assign CNTVALUEIN_INTEGER = 23; + 5'b11000 : assign CNTVALUEIN_INTEGER = 24; + 5'b11001 : assign CNTVALUEIN_INTEGER = 25; + 5'b11010 : assign CNTVALUEIN_INTEGER = 26; + 5'b11011 : assign CNTVALUEIN_INTEGER = 27; + 5'b11100 : assign CNTVALUEIN_INTEGER = 28; + 5'b11101 : assign CNTVALUEIN_INTEGER = 29; + 5'b11110 : assign CNTVALUEIN_INTEGER = 30; + 5'b11111 : assign CNTVALUEIN_INTEGER = 31; + endcase + end + + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(datain_in or idatain_in) begin + + case (DELAY_SRC) + + "IDATAIN" : begin + data_mux <= idatain_in; + end + "DATAIN" : begin + data_mux <= datain_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on X_IODELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @(datain_in or idatain_in) + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* + assign #(DELAY_D) delay_chain_0 = data_mux; + assign #CALC_TAPDELAY_RD delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY_RD delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY_RD delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY_RD delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY_RD delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY_RD delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY_RD delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY_RD delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY_RD delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY_RD delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY_RD delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY_RD delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY_RD delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY_RD delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY_RD delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY_RD delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY_RD delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY_RD delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY_RD delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY_RD delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY_RD delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY_RD delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY_RD delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY_RD delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY_RD delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY_RD delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY_RD delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY_RD delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY_RD delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY_RD delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY_RD delay_chain_31 = delay_chain_30; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(idelay_count) begin + case (idelay_count) + 0: assign tap_out_rd = delay_chain_0; + 1: assign tap_out_rd = delay_chain_1; + 2: assign tap_out_rd = delay_chain_2; + 3: assign tap_out_rd = delay_chain_3; + 4: assign tap_out_rd = delay_chain_4; + 5: assign tap_out_rd = delay_chain_5; + 6: assign tap_out_rd = delay_chain_6; + 7: assign tap_out_rd = delay_chain_7; + 8: assign tap_out_rd = delay_chain_8; + 9: assign tap_out_rd = delay_chain_9; + 10: assign tap_out_rd = delay_chain_10; + 11: assign tap_out_rd = delay_chain_11; + 12: assign tap_out_rd = delay_chain_12; + 13: assign tap_out_rd = delay_chain_13; + 14: assign tap_out_rd = delay_chain_14; + 15: assign tap_out_rd = delay_chain_15; + 16: assign tap_out_rd = delay_chain_16; + 17: assign tap_out_rd = delay_chain_17; + 18: assign tap_out_rd = delay_chain_18; + 19: assign tap_out_rd = delay_chain_19; + 20: assign tap_out_rd = delay_chain_20; + 21: assign tap_out_rd = delay_chain_21; + 22: assign tap_out_rd = delay_chain_22; + 23: assign tap_out_rd = delay_chain_23; + 24: assign tap_out_rd = delay_chain_24; + 25: assign tap_out_rd = delay_chain_25; + 26: assign tap_out_rd = delay_chain_26; + 27: assign tap_out_rd = delay_chain_27; + 28: assign tap_out_rd = delay_chain_28; + 29: assign tap_out_rd = delay_chain_29; + 30: assign tap_out_rd = delay_chain_30; + 31: assign tap_out_rd = delay_chain_31; + default: + assign tap_out_rd = delay_chain_0; + endcase + end // always @ (idelay_count) + +//********************************************************* +//*** FINE DELAY signal +//********************************************************* + assign #(INIT_DELAY_FD) fine_delay_0 = tap_out_rd; + assign #CALC_TAPDELAY_FD fine_delay_1 = fine_delay_0; + assign #CALC_TAPDELAY_FD fine_delay_2 = fine_delay_1; + assign #CALC_TAPDELAY_FD fine_delay_3 = fine_delay_2; + assign #CALC_TAPDELAY_FD fine_delay_4 = fine_delay_3; + assign #CALC_TAPDELAY_FD fine_delay_5 = fine_delay_4; + + always @(ifdly_in) begin + case (ifdly_in) + 3'b000: assign tap_out_fd = fine_delay_0; + 3'b001: assign tap_out_fd = fine_delay_1; + 3'b010: assign tap_out_fd = fine_delay_2; + 3'b011: assign tap_out_fd = fine_delay_3; + 3'b100: assign tap_out_fd = fine_delay_4; + default: + assign tap_out_fd = 1'bx; + endcase + end // always @ (ifdly_in) + + +`ifdef XIL_TIMING +//*** Timing Checks Start here + wire c_en_n; + wire c_en_p; + + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + + wire d_d_en; + wire id_d_en; + + assign d_d_en = (idelay_count == 0) && (ifdly_in == 0) && (DELAY_SRC == "DATAIN"); + assign id_d_en = (idelay_count == 0) && (ifdly_in == 0) && (DELAY_SRC == "IDATAIN"); + + always @(notifier) begin + tap_out_rd <= 1'bx; + end +`endif // ifdef XIL_TIMING + + +`ifdef XIL_TIMING + specify + + ( C *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( C => DATAOUT) = (0:0:0, 0:0:0); + ( CINVCTRL *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( CINVCTRL => DATAOUT) = (0:0:0, 0:0:0); + if (d_d_en) ( DATAIN => DATAOUT) = (0:0:0, 0:0:0); + if (id_d_en) ( IDATAIN => DATAOUT) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc); + $setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc); + $setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld); + $setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld); + $setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein); + $setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein); + $setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen); + $setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen); + $setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst); + $setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst); + + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc); + $setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc); + $setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld); + $setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld); + $setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein); + $setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein); + $setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen); + $setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen); + $setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst); + $setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst); + + + + specparam PATHPULSE$ = 0; + + endspecify +`endif // ifdef XIL_TIMING + +endmodule // IDELAYE2_FINEDELAY + +`endcelldefine diff --git a/verilog/src/unisims/IDELAYE3.v b/verilog/src/unisims/IDELAYE3.v new file mode 100644 index 0000000..db61c22 --- /dev/null +++ b/verilog/src/unisims/IDELAYE3.v @@ -0,0 +1,826 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Input Fixed or Variable Delay Element +// /___/ /\ Filename : IDELAYE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IDELAYE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE = "NONE", + parameter DELAY_FORMAT = "TIME", + parameter DELAY_SRC = "IDATAIN", + parameter DELAY_TYPE = "FIXED", + parameter integer DELAY_VALUE = 0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter LOOPBACK = "FALSE", + parameter real REFCLK_FREQUENCY = 300.0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter UPDATE_MODE = "ASYNC" +)( + output CASC_OUT, + output [8:0] CNTVALUEOUT, + output DATAOUT, + + input CASC_IN, + input CASC_RETURN, + input CE, + input CLK, + input [8:0] CNTVALUEIN, + input DATAIN, + input EN_VTC, + input IDATAIN, + input INC, + input LOAD, + input RST +); + +// define constants + localparam MODULE_NAME = "IDELAYE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam CASCADE_MASTER = 1; + localparam CASCADE_NONE = 0; + localparam CASCADE_SLAVE_END = 2; + localparam CASCADE_SLAVE_MIDDLE = 3; + localparam DELAY_FORMAT_COUNT = 1; + localparam DELAY_FORMAT_TIME = 0; + localparam DELAY_SRC_DATAIN = 1; + localparam DELAY_SRC_IDATAIN = 0; + localparam DELAY_TYPE_FIXED = 0; + localparam DELAY_TYPE_VARIABLE = 1; + localparam DELAY_TYPE_VAR_LOAD = 2; + localparam LOOPBACK_FALSE = 0; + localparam LOOPBACK_TRUE = 1; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 2; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES2 = 3; + localparam UPDATE_MODE_ASYNC = 0; + localparam UPDATE_MODE_MANUAL = 1; + localparam UPDATE_MODE_SYNC = 2; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "IDELAYE3_dr.v" +`else + localparam [96:1] CASCADE_REG = CASCADE; + localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT; + localparam [56:1] DELAY_SRC_REG = DELAY_SRC; + localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE; + localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [40:1] LOOPBACK_REG = LOOPBACK; + localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE; +`endif + + wire [1:0] CASCADE_BIN; + wire DELAY_FORMAT_BIN; + wire DELAY_SRC_BIN; + wire [1:0] DELAY_TYPE_BIN; + wire [10:0] DELAY_VALUE_BIN; + wire LOOPBACK_BIN; + wire [63:0] REFCLK_FREQUENCY_BIN; + wire [1:0] SIM_DEVICE_BIN; + wire [63:0] SIM_VERSION_BIN; + wire [1:0] UPDATE_MODE_BIN; + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire CASC_IN_in; + wire CASC_RETURN_in; + wire CE_in; + wire CLK_in; + wire DATAIN_in; + wire EN_VTC_in; + wire IDATAIN_in; + wire INC_in; + wire LOAD_in; + wire RST_in; + wire [8:0] CNTVALUEIN_in; + + wire CASC_IN_delay; + wire CASC_RETURN_delay; + wire CE_delay; + wire CLK_delay; + wire DATAIN_delay; + wire EN_VTC_delay; + wire IDATAIN_delay; + wire INC_delay; + wire LOAD_delay; + wire RST_delay; + wire [8:0] CNTVALUEIN_delay; + + reg CASC_OUT_out; + reg DATAOUT_out; + reg [8:0] CNTVALUEOUT_out; + + wire CASC_OUT_delay; + wire DATAOUT_delay; + wire [8:0] CNTVALUEOUT_delay; + + assign #(out_delay) CASC_OUT = CASC_OUT_delay; + assign #(out_delay) CNTVALUEOUT = (EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : CNTVALUEOUT_delay; + assign #(out_delay) DATAOUT = DATAOUT_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLK_delay = CLK; + + assign #(in_delay) CE_delay = CE; + assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN; + assign #(in_delay) INC_delay = INC; + assign #(in_delay) LOAD_delay = LOAD; +`endif // `ifndef XIL_TIMING +// inputs with no timing checks + + assign #(in_delay) RST_delay = RST; + assign #(in_delay) CASC_IN_delay = CASC_IN; + assign #(in_delay) CASC_RETURN_delay = CASC_RETURN; + assign #(in_delay) DATAIN_delay = DATAIN; + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) IDATAIN_delay = IDATAIN; + + assign CASC_OUT_delay = CASC_OUT_out; + assign CNTVALUEOUT_delay = CNTVALUEOUT_out; + assign DATAOUT_delay = DATAOUT_out; + + assign CASC_IN_in = CASC_IN_delay; + assign CASC_RETURN_in = CASC_RETURN_delay; + assign CE_in = CE_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG; + assign CNTVALUEIN_in[0] = (CNTVALUEIN[0] === 1'bz) || CNTVALUEIN_delay[0]; // rv 1 + assign CNTVALUEIN_in[1] = (CNTVALUEIN[1] === 1'bz) || CNTVALUEIN_delay[1]; // rv 1 + assign CNTVALUEIN_in[2] = (CNTVALUEIN[2] === 1'bz) || CNTVALUEIN_delay[2]; // rv 1 + assign CNTVALUEIN_in[3] = (CNTVALUEIN[3] === 1'bz) || CNTVALUEIN_delay[3]; // rv 1 + assign CNTVALUEIN_in[4] = (CNTVALUEIN[4] === 1'bz) || CNTVALUEIN_delay[4]; // rv 1 + assign CNTVALUEIN_in[5] = (CNTVALUEIN[5] === 1'bz) || CNTVALUEIN_delay[5]; // rv 1 + assign CNTVALUEIN_in[6] = (CNTVALUEIN[6] === 1'bz) || CNTVALUEIN_delay[6]; // rv 1 + assign CNTVALUEIN_in[7] = (CNTVALUEIN[7] === 1'bz) || CNTVALUEIN_delay[7]; // rv 1 + assign CNTVALUEIN_in[8] = (CNTVALUEIN[8] === 1'bz) || CNTVALUEIN_delay[8]; // rv 1 + assign DATAIN_in = DATAIN_delay; + assign EN_VTC_in = EN_VTC_delay; + assign IDATAIN_in = IDATAIN_delay; + assign INC_in = INC_delay; + assign LOAD_in = LOAD_delay; + assign RST_in = RST_delay ^ IS_RST_INVERTED_REG; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + + assign CASCADE_BIN = + (CASCADE_REG == "NONE") ? CASCADE_NONE : + (CASCADE_REG == "MASTER") ? CASCADE_MASTER : + (CASCADE_REG == "SLAVE_END") ? CASCADE_SLAVE_END : + (CASCADE_REG == "SLAVE_MIDDLE") ? CASCADE_SLAVE_MIDDLE : + CASCADE_NONE; + + assign DELAY_FORMAT_BIN = + (DELAY_FORMAT_REG == "TIME") ? DELAY_FORMAT_TIME : + (DELAY_FORMAT_REG == "COUNT") ? DELAY_FORMAT_COUNT : + DELAY_FORMAT_TIME; + + assign DELAY_SRC_BIN = + (DELAY_SRC_REG == "IDATAIN") ? DELAY_SRC_IDATAIN : + (DELAY_SRC_REG == "DATAIN") ? DELAY_SRC_DATAIN : + DELAY_SRC_IDATAIN; + + assign DELAY_TYPE_BIN = + (DELAY_TYPE_REG == "FIXED") ? DELAY_TYPE_FIXED : + (DELAY_TYPE_REG == "VARIABLE") ? DELAY_TYPE_VARIABLE : + (DELAY_TYPE_REG == "VAR_LOAD") ? DELAY_TYPE_VAR_LOAD : + DELAY_TYPE_FIXED; + + assign DELAY_VALUE_BIN = DELAY_VALUE_REG[10:0]; + + assign LOOPBACK_BIN = + (LOOPBACK_REG == "FALSE") ? LOOPBACK_FALSE : + (LOOPBACK_REG == "TRUE") ? LOOPBACK_TRUE : + LOOPBACK_FALSE; + + assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + assign UPDATE_MODE_BIN = + (UPDATE_MODE_REG == "ASYNC") ? UPDATE_MODE_ASYNC : + (UPDATE_MODE_REG == "MANUAL") ? UPDATE_MODE_MANUAL : + (UPDATE_MODE_REG == "SYNC") ? UPDATE_MODE_SYNC : + UPDATE_MODE_ASYNC; + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CASCADE_REG != "NONE") && + (CASCADE_REG != "MASTER") && + (CASCADE_REG != "SLAVE_END") && + (CASCADE_REG != "SLAVE_MIDDLE"))) begin + $display("Error: [Unisim %s-101] CASCADE attribute is set to %s. Legal values for this attribute are NONE, MASTER, SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_FORMAT_REG != "TIME") && + (DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-102] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_SRC_REG != "IDATAIN") && + (DELAY_SRC_REG != "DATAIN"))) begin + $display("Error: [Unisim %s-103] DELAY_SRC attribute is set to %s. Legal values for this attribute are IDATAIN or DATAIN. Instance: %m", MODULE_NAME, DELAY_SRC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_TYPE_REG != "FIXED") && + (DELAY_TYPE_REG != "VAR_LOAD") && + (DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-104] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LOOPBACK_REG != "FALSE") && + (LOOPBACK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] LOOPBACK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LOOPBACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-109] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-109] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-110] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-111] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_REG != "ASYNC") && + (UPDATE_MODE_REG != "MANUAL") && + (UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-112] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam MAX_DELAY_COUNT = 511; + localparam MIN_DELAY_COUNT = 0; + + integer PER_BIT_FINE_DELAY; + integer PER_BIT_MEDIUM_DELAY; + integer INTRINSIC_FINE_DELAY; + integer INTRINSIC_MEDIUM_DELAY; + integer IDATAIN_INTRINSIC_DELAY; + integer DATAIN_INTRINSIC_DELAY; + integer CASC_IN_INTRINSIC_DELAY; + integer CASC_RET_INTRINSIC_DELAY; + integer DATA_OUT_INTRINSIC_DELAY; + integer CASC_OUT_INTRINSIC_DELAY; + + reg [17:0] gen_mc_fixed_dly_ratio; + reg tap_out; + reg clk_smux; + reg data_mux; + reg data_mux_sync; + reg data_mux_sync1; + reg data_mux_sync2; + reg data_mux_sync3; + reg data_mux_sync4; + reg cdataout_pre; + reg RST_sync1; + reg RST_sync2; + reg RST_sync3; + reg [8:0] idelay_count_async; + reg [8:0] idelay_count_sync; + reg [8:0] cntvalue_updated; + reg [8:0] cntvalue_updated_sync; + reg [8:0] cntvalue_updated_async; + reg [8:0] idelay_count_pre; + reg [8:0] CNTVALUEIN_INTEGER; + time delay_value; + + initial begin + case (SIM_DEVICE) + "ULTRASCALE" : begin + PER_BIT_FINE_DELAY = 5; + PER_BIT_MEDIUM_DELAY = 40; + INTRINSIC_FINE_DELAY = 75; + INTRINSIC_MEDIUM_DELAY = 40; + IDATAIN_INTRINSIC_DELAY = 20; + DATAIN_INTRINSIC_DELAY = 60; + CASC_IN_INTRINSIC_DELAY = 60; + CASC_RET_INTRINSIC_DELAY = 60; + DATA_OUT_INTRINSIC_DELAY = 25; + CASC_OUT_INTRINSIC_DELAY = 80; + end + "ULTRASCALE_PLUS","ULTRASCALE_PLUS_ES1","ULTRASCALE_PLUS_ES2" : begin + PER_BIT_FINE_DELAY = 4; + PER_BIT_MEDIUM_DELAY = 32; + INTRINSIC_FINE_DELAY = 60; + INTRINSIC_MEDIUM_DELAY = 32; + IDATAIN_INTRINSIC_DELAY = 15; + DATAIN_INTRINSIC_DELAY = 32; + CASC_IN_INTRINSIC_DELAY = 32; + CASC_RET_INTRINSIC_DELAY = 32; + DATA_OUT_INTRINSIC_DELAY = 20; + CASC_OUT_INTRINSIC_DELAY = 45; + end + default : begin + PER_BIT_FINE_DELAY = 5; + PER_BIT_MEDIUM_DELAY = 40; + INTRINSIC_FINE_DELAY = 75; + INTRINSIC_MEDIUM_DELAY = 40; + IDATAIN_INTRINSIC_DELAY = 20; + DATAIN_INTRINSIC_DELAY = 60; + CASC_IN_INTRINSIC_DELAY = 60; + CASC_RET_INTRINSIC_DELAY = 60; + DATA_OUT_INTRINSIC_DELAY = 25; + CASC_OUT_INTRINSIC_DELAY = 80; + end + endcase + CNTVALUEOUT_out = 9'b0; + DATAOUT_out = 1'b0; + CASC_OUT_out = 1'b0; + cdataout_pre = 1'b0; + end + + always @(RST_in) begin + if (RST_in === 1'b1 && DELAY_FORMAT_REG == "TIME") + $display("Warning: [Unisim %s-1] Ultrascale IDELAYCTRL and I/ODELAYE3, RST simulation behaviour may not match hardware behaviour when DELAY_FORMAT = TIME, if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide Instance: %m", MODULE_NAME); + end + + always @ (trig_attr) begin + #1; + if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME) begin + if ((DELAY_VALUE_REG == 0) || (REFCLK_FREQUENCY_REG == 0)) begin + idelay_count_pre = 0; + cntvalue_updated = idelay_count_pre; + end else begin + idelay_count_pre = DELAY_VALUE_REG/PER_BIT_FINE_DELAY; + cntvalue_updated = idelay_count_pre; + end + end else if (DELAY_FORMAT_BIN == DELAY_FORMAT_COUNT) begin + idelay_count_pre = DELAY_VALUE_REG; + cntvalue_updated = idelay_count_pre; + end + end + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- + always @(tap_out) begin + DATAOUT_out <= #(DATA_OUT_INTRINSIC_DELAY) tap_out; + end + + always @(cdataout_pre) begin + CASC_OUT_out <= #(CASC_OUT_INTRINSIC_DELAY) cdataout_pre; + end + +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + +//*** GLOBAL hidden GSR pin + always @(glblGSR or RST_in) begin + if (glblGSR == 1'b1 || RST_in == 1'b1) begin +// assign idelay_count_sync = idelay_count_pre; + assign idelay_count_async = idelay_count_pre; + assign cntvalue_updated_sync = idelay_count_pre; + assign cntvalue_updated_async = idelay_count_pre; + end else if (glblGSR == 1'b0 || RST_in == 1'b0) begin +// deassign idelay_count_sync; + deassign idelay_count_async; + deassign cntvalue_updated_sync; + deassign cntvalue_updated_async; + end + end + +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- +// always @(idelay_count_sync or idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin + always @(idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin + case (UPDATE_MODE_REG) + "SYNC" : begin + CNTVALUEOUT_out = idelay_count_async; + cntvalue_updated = cntvalue_updated_sync; + end + "ASYNC" , "MANUAL" : begin + CNTVALUEOUT_out = idelay_count_async; + cntvalue_updated = cntvalue_updated_async; + end + default: $display("Error: [Unisim %s-1] UPDATE_MODE_REG=%s is not valid value. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + endcase + end + +//---------------------------------------------------------------------- +//-------------------------- DELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(CLK_in or RST_in or RST_sync3 or RST_sync2 or RST_sync1) begin + if (RST_in == 1'b1 || RST_sync3 == 1'b1 || RST_sync2 == 1'b1 || RST_sync1 == 1'b1) + clk_smux = 1'b0; + else if (RST_sync3 == 1'b0) + clk_smux = CLK_in; + end + + always @(posedge CLK_in) begin + RST_sync1 <= RST_in; + RST_sync2 <= RST_sync1; + RST_sync3 <= RST_sync2; + end + + always @(posedge clk_smux) begin + if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin + case(DELAY_TYPE_REG) + "FIXED": ; //Do nothing. + "VAR_LOAD": + if (EN_VTC_in == 1'b0) begin + casex({LOAD_in, CE_in, INC_in}) + 3'b000: ; //Do nothing. + 3'b001: ; //Do nothing. + 3'b010: + begin //{ + if (idelay_count_async > MIN_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async-1; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= idelay_count_async-1; + end + else if (idelay_count_async == MIN_DELAY_COUNT) begin + idelay_count_async <= MAX_DELAY_COUNT; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= MAX_DELAY_COUNT; + end + end //} + 3'b011: + begin //{ + if (idelay_count_async < MAX_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async + 1; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= idelay_count_async + 1; + end + else if (idelay_count_async == MAX_DELAY_COUNT) begin + idelay_count_async <= MIN_DELAY_COUNT; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= MIN_DELAY_COUNT; + end + end //} + 3'b100, 3'b101: + begin //{ + idelay_count_async <= CNTVALUEIN_INTEGER; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= CNTVALUEIN_INTEGER; + end //} + 3'b110: + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + $display("Error: [Unisim %s-2] Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s. Instance: %m", MODULE_NAME, UPDATE_MODE_REG, DELAY_TYPE_REG); + else cntvalue_updated_async <= idelay_count_async; + 3'b111: + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + $display("Error: [Unisim %s-3] Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s. Instance: %m", MODULE_NAME, UPDATE_MODE_REG, DELAY_TYPE_REG); + else idelay_count_async <= idelay_count_async + CNTVALUEIN_INTEGER; + default: $display("Error: [Unisim %s-4] Invalid scenario. LOAD = %b, CE = %b INC = %b. Instance: %m", MODULE_NAME, LOAD_in, CE_in, INC_in); + endcase + end + "VARIABLE": + if (EN_VTC_in == 1'b0) begin + casex({LOAD_in, CE_in, INC_in}) + 3'b000: ; //Do nothing. + 3'b001: ; //Do nothing. + 3'b010: + begin //{ + if (idelay_count_async > MIN_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async-1; + cntvalue_updated_async <= idelay_count_async-1; + end + else if (idelay_count_async == MIN_DELAY_COUNT) begin + idelay_count_async <= MAX_DELAY_COUNT; + cntvalue_updated_async <= MAX_DELAY_COUNT; + end + end //} + 3'b011: + begin //{ + if (idelay_count_async < MAX_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async + 1; + cntvalue_updated_async <= idelay_count_async + 1; + end + else if (idelay_count_async == MAX_DELAY_COUNT) begin + idelay_count_async <= MIN_DELAY_COUNT; + cntvalue_updated_async <= MIN_DELAY_COUNT; + end + end //} + default: $display("Error: [Unisim %s-5] Invalid scenario. LOAD = %b, CE = %b, INC = %b, DELAY_TYPE=%s. Instance: %m", MODULE_NAME, LOAD_in, CE_in, INC_in, DELAY_TYPE_REG); + endcase + end + default: $display("Error: [Unisim %s-6] DELAY_TYPE=%s is not a valid value. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + endcase + end + end // always @ (posedge CLK_in) + + always @(data_mux) begin + data_mux_sync = data_mux_sync4; + data_mux_sync4 = data_mux_sync3; + data_mux_sync3 = data_mux_sync2; + data_mux_sync2 = data_mux_sync1; + data_mux_sync1 = data_mux; + end + + always @(data_mux_sync) begin + cntvalue_updated_sync = cntvalue_updated_async; + end + + always @(CNTVALUEIN_in or glblGSR) begin + CNTVALUEIN_INTEGER = CNTVALUEIN_in; + end + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(DATAIN_in or IDATAIN_in or CASC_IN_in or CASC_RETURN_in or CASCADE_REG or LOOPBACK_REG) begin + case (LOOPBACK_REG) + "TRUE" : begin + data_mux = CASC_RETURN_in; + cdataout_pre = 1'b0; + end + "FALSE": begin + case (CASCADE_REG) + "NONE": begin + case (DELAY_SRC_REG) + "IDATAIN" : begin + data_mux = IDATAIN_in; + cdataout_pre = IDATAIN_in; + end + "DATAIN" : begin + data_mux = DATAIN_in; + cdataout_pre = DATAIN_in; + end + default : begin + $display("Error: [Unisim %s-7] The attribute DELAY_SRC is set to %s. Legal values for this attribute are DATAIN or IDATAIN. Instance: %m", MODULE_NAME, DELAY_SRC_REG); + $finish; + end + endcase // case(IDELAY_SRC_reg) + end + "MASTER": begin + case (DELAY_SRC_REG) + "IDATAIN" : begin + data_mux = CASC_RETURN_in; + cdataout_pre = IDATAIN_in; + end + "DATAIN" : begin + data_mux = CASC_RETURN_in; + cdataout_pre = DATAIN_in; + end + default : begin + $display("Error: [Unisim %s-8] The attribute DELAY_SRC is set to %s. Legal values for this attribute are DATAIN or IDATAIN. Instance: %m", MODULE_NAME, DELAY_SRC_REG); + $finish; + end + endcase // case(IDELAY_SRC_reg) + end + "SLAVE_END" : begin + data_mux = CASC_IN_in; + cdataout_pre = 1'b0; + end + "SLAVE_MIDDLE" : begin + data_mux = CASC_RETURN_in; + cdataout_pre = CASC_IN_in; + end + default : begin + $display("Error: [Unisim %s-9] The attribute CASCADE is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + $finish; + end + endcase // case(CASCADE_REG) + end + default : begin + $display("Error: [Unisim %s-10] The attribute LOOPBACK is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LOOPBACK_REG); + $finish; + end + endcase + end // always @(DATAIN_in or IDATAIN_in or CASC_IN_in) + + always @ (cntvalue_updated or data_mux or CASC_RETURN_in or DELAY_FORMAT_REG) begin + delay_value = (cntvalue_updated[2:0]*PER_BIT_FINE_DELAY) + (cntvalue_updated[8:3]*PER_BIT_MEDIUM_DELAY) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ; + case (LOOPBACK_REG) + "TRUE" : begin + delay_value = delay_value + CASC_RET_INTRINSIC_DELAY; + end + "FALSE" : begin + case (CASCADE_REG) + "NONE" : begin + case (DELAY_SRC_REG) + "IDATAIN" : begin + delay_value = delay_value + IDATAIN_INTRINSIC_DELAY; + end + "DATAIN" : begin + delay_value = delay_value + DATAIN_INTRINSIC_DELAY; + end + default : begin + $display("Error: [Unisim %s-11] The attribute DELAY_SRC is set to %s. Legal values for this attribute are DATAIN or IDATAIN. Instance: %m", MODULE_NAME, DELAY_SRC_REG); + $finish; + end + endcase // case(DELAY_SRC_reg) + end + "MASTER","SLAVE_MIDDLE" : begin + delay_value = delay_value + CASC_RET_INTRINSIC_DELAY; + end + "SLAVE_END" : begin + delay_value = delay_value + CASC_IN_INTRINSIC_DELAY; + end + default : begin + $display("Error: [Unisim %s-12] The attribute CASCADE is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + $finish; + end + endcase // case(CASCADE_REG) + end + default : begin + $display("Error: [Unisim %s-13] The attribute LOOPBACK is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LOOPBACK_REG); + $finish; + end + endcase + + + end + + always @ (*) begin + tap_out <= #delay_value data_mux; + end + +// end behavioral model + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; +`endif + + wire ci_co_en; + wire ci_do_en; + wire cr_do_en; + wire d_co_en; + wire d_do_en; + wire id_co_en; + wire id_do_en; + + assign ci_co_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && (CASCADE_REG == "SLAVE_MIDDLE"); + assign ci_do_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && (CASCADE_REG == "SLAVE_END"); + assign cr_do_en = (delay_value == 0) && (LOOPBACK_REG == "TRUE") || + (CASCADE_REG == "SLAVE_MIDDLE") || (CASCADE_REG == "MASTER"); + assign d_co_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && + ((CASCADE_REG == "NONE") || (CASCADE_REG == "MASTER")) && + (DELAY_SRC_REG == "DATAIN"); + assign d_do_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && (CASCADE_REG == "NONE") && + (DELAY_SRC_REG == "DATAIN"); + assign id_co_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && + ((CASCADE_REG == "NONE") || (CASCADE_REG == "MASTER")) && + (DELAY_SRC_REG == "IDATAIN"); + assign id_do_en = (delay_value == 0) && (LOOPBACK_REG == "FALSE") && (CASCADE_REG == "NONE") && + (DELAY_SRC_REG == "IDATAIN"); + + specify + if (ci_co_en) (CASC_IN => CASC_OUT) = (0:0:0, 0:0:0); + if (ci_do_en) (CASC_IN => DATAOUT) = (0:0:0, 0:0:0); + if (cr_do_en) (CASC_RETURN => DATAOUT) = (0:0:0, 0:0:0); + (CLK *> CNTVALUEOUT) = (100:100:100, 100:100:100); + if (d_co_en) (DATAIN => CASC_OUT) = (0:0:0, 0:0:0); + if (d_do_en) (DATAIN => DATAOUT) = (0:0:0, 0:0:0); + if (id_co_en) (IDATAIN => CASC_OUT) = (0:0:0, 0:0:0); + if (id_do_en) (IDATAIN => DATAOUT) = (0:0:0, 0:0:0); + (negedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + (posedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] == 'b0) (negedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] != 'b0) (negedge RST *> (CNTVALUEOUT +: 1)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] == 'b0) (posedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] != 'b0) (posedge RST *> (CNTVALUEOUT +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ILKN.v b/verilog/src/unisims/ILKN.v new file mode 100644 index 0000000..b68ed2c --- /dev/null +++ b/verilog/src/unisims/ILKN.v @@ -0,0 +1,11722 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Interlaken MAC +// /___/ /\ Filename : ILKN.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ILKN #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter BYPASS = "FALSE", + parameter [1:0] CTL_RX_BURSTMAX = 2'h3, + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0, + parameter [3:0] CTL_RX_LAST_LANE = 4'hB, + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF, + parameter CTL_RX_PACKET_MODE = "TRUE", + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0, + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2, + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000, + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008, + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000, + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00, + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE", + parameter [1:0] CTL_TX_BURSTMAX = 2'h3, + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1, + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0, + parameter CTL_TX_DISABLE_SKIPWORD = "TRUE", + parameter [6:0] CTL_TX_FC_CALLEN = 7'h00, + parameter [3:0] CTL_TX_LAST_LANE = 4'hB, + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF, + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800, + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0, + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3, + parameter MODE = "TRUE", + parameter SIM_VERSION = "2.0", + parameter TEST_MODE_PIN_CHAR = "FALSE" +)( + output [15:0] DRP_DO, + output DRP_RDY, + output [65:0] RX_BYPASS_DATAOUT00, + output [65:0] RX_BYPASS_DATAOUT01, + output [65:0] RX_BYPASS_DATAOUT02, + output [65:0] RX_BYPASS_DATAOUT03, + output [65:0] RX_BYPASS_DATAOUT04, + output [65:0] RX_BYPASS_DATAOUT05, + output [65:0] RX_BYPASS_DATAOUT06, + output [65:0] RX_BYPASS_DATAOUT07, + output [65:0] RX_BYPASS_DATAOUT08, + output [65:0] RX_BYPASS_DATAOUT09, + output [65:0] RX_BYPASS_DATAOUT10, + output [65:0] RX_BYPASS_DATAOUT11, + output [11:0] RX_BYPASS_ENAOUT, + output [11:0] RX_BYPASS_IS_AVAILOUT, + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT, + output [11:0] RX_BYPASS_IS_OVERFLOWOUT, + output [11:0] RX_BYPASS_IS_SYNCEDOUT, + output [11:0] RX_BYPASS_IS_SYNCWORDOUT, + output [10:0] RX_CHANOUT0, + output [10:0] RX_CHANOUT1, + output [10:0] RX_CHANOUT2, + output [10:0] RX_CHANOUT3, + output [127:0] RX_DATAOUT0, + output [127:0] RX_DATAOUT1, + output [127:0] RX_DATAOUT2, + output [127:0] RX_DATAOUT3, + output RX_ENAOUT0, + output RX_ENAOUT1, + output RX_ENAOUT2, + output RX_ENAOUT3, + output RX_EOPOUT0, + output RX_EOPOUT1, + output RX_EOPOUT2, + output RX_EOPOUT3, + output RX_ERROUT0, + output RX_ERROUT1, + output RX_ERROUT2, + output RX_ERROUT3, + output [3:0] RX_MTYOUT0, + output [3:0] RX_MTYOUT1, + output [3:0] RX_MTYOUT2, + output [3:0] RX_MTYOUT3, + output RX_OVFOUT, + output RX_SOPOUT0, + output RX_SOPOUT1, + output RX_SOPOUT2, + output RX_SOPOUT3, + output STAT_RX_ALIGNED, + output STAT_RX_ALIGNED_ERR, + output [11:0] STAT_RX_BAD_TYPE_ERR, + output STAT_RX_BURSTMAX_ERR, + output STAT_RX_BURST_ERR, + output STAT_RX_CRC24_ERR, + output [11:0] STAT_RX_CRC32_ERR, + output [11:0] STAT_RX_CRC32_VALID, + output [11:0] STAT_RX_DESCRAM_ERR, + output [11:0] STAT_RX_DIAGWORD_INTFSTAT, + output [11:0] STAT_RX_DIAGWORD_LANESTAT, + output [255:0] STAT_RX_FC_STAT, + output [11:0] STAT_RX_FRAMING_ERR, + output STAT_RX_MEOP_ERR, + output [11:0] STAT_RX_MF_ERR, + output [11:0] STAT_RX_MF_LEN_ERR, + output [11:0] STAT_RX_MF_REPEAT_ERR, + output STAT_RX_MISALIGNED, + output STAT_RX_MSOP_ERR, + output [7:0] STAT_RX_MUBITS, + output STAT_RX_MUBITS_UPDATED, + output STAT_RX_OVERFLOW_ERR, + output STAT_RX_RETRANS_CRC24_ERR, + output STAT_RX_RETRANS_DISC, + output [15:0] STAT_RX_RETRANS_LATENCY, + output STAT_RX_RETRANS_REQ, + output STAT_RX_RETRANS_RETRY_ERR, + output [7:0] STAT_RX_RETRANS_SEQ, + output STAT_RX_RETRANS_SEQ_UPDATED, + output [2:0] STAT_RX_RETRANS_STATE, + output [4:0] STAT_RX_RETRANS_SUBSEQ, + output STAT_RX_RETRANS_WDOG_ERR, + output STAT_RX_RETRANS_WRAP_ERR, + output [11:0] STAT_RX_SYNCED, + output [11:0] STAT_RX_SYNCED_ERR, + output [11:0] STAT_RX_WORD_SYNC, + output STAT_TX_BURST_ERR, + output STAT_TX_ERRINJ_BITERR_DONE, + output STAT_TX_OVERFLOW_ERR, + output STAT_TX_RETRANS_BURST_ERR, + output STAT_TX_RETRANS_BUSY, + output STAT_TX_RETRANS_RAM_PERROUT, + output [8:0] STAT_TX_RETRANS_RAM_RADDR, + output STAT_TX_RETRANS_RAM_RD_B0, + output STAT_TX_RETRANS_RAM_RD_B1, + output STAT_TX_RETRANS_RAM_RD_B2, + output STAT_TX_RETRANS_RAM_RD_B3, + output [1:0] STAT_TX_RETRANS_RAM_RSEL, + output [8:0] STAT_TX_RETRANS_RAM_WADDR, + output [643:0] STAT_TX_RETRANS_RAM_WDATA, + output STAT_TX_RETRANS_RAM_WE_B0, + output STAT_TX_RETRANS_RAM_WE_B1, + output STAT_TX_RETRANS_RAM_WE_B2, + output STAT_TX_RETRANS_RAM_WE_B3, + output STAT_TX_UNDERFLOW_ERR, + output TX_OVFOUT, + output TX_RDYOUT, + output [63:0] TX_SERDES_DATA00, + output [63:0] TX_SERDES_DATA01, + output [63:0] TX_SERDES_DATA02, + output [63:0] TX_SERDES_DATA03, + output [63:0] TX_SERDES_DATA04, + output [63:0] TX_SERDES_DATA05, + output [63:0] TX_SERDES_DATA06, + output [63:0] TX_SERDES_DATA07, + output [63:0] TX_SERDES_DATA08, + output [63:0] TX_SERDES_DATA09, + output [63:0] TX_SERDES_DATA10, + output [63:0] TX_SERDES_DATA11, + + input CORE_CLK, + input CTL_RX_FORCE_RESYNC, + input CTL_RX_RETRANS_ACK, + input CTL_RX_RETRANS_ENABLE, + input CTL_RX_RETRANS_ERRIN, + input CTL_RX_RETRANS_FORCE_REQ, + input CTL_RX_RETRANS_RESET, + input CTL_RX_RETRANS_RESET_MODE, + input CTL_TX_DIAGWORD_INTFSTAT, + input [11:0] CTL_TX_DIAGWORD_LANESTAT, + input CTL_TX_ENABLE, + input CTL_TX_ERRINJ_BITERR_GO, + input [3:0] CTL_TX_ERRINJ_BITERR_LANE, + input [255:0] CTL_TX_FC_STAT, + input [7:0] CTL_TX_MUBITS, + input CTL_TX_RETRANS_ENABLE, + input CTL_TX_RETRANS_RAM_PERRIN, + input [643:0] CTL_TX_RETRANS_RAM_RDATA, + input CTL_TX_RETRANS_REQ, + input CTL_TX_RETRANS_REQ_VALID, + input [11:0] CTL_TX_RLIM_DELTA, + input CTL_TX_RLIM_ENABLE, + input [7:0] CTL_TX_RLIM_INTV, + input [11:0] CTL_TX_RLIM_MAX, + input [9:0] DRP_ADDR, + input DRP_CLK, + input [15:0] DRP_DI, + input DRP_EN, + input DRP_WE, + input LBUS_CLK, + input RX_BYPASS_FORCE_REALIGNIN, + input RX_BYPASS_RDIN, + input RX_RESET, + input [11:0] RX_SERDES_CLK, + input [63:0] RX_SERDES_DATA00, + input [63:0] RX_SERDES_DATA01, + input [63:0] RX_SERDES_DATA02, + input [63:0] RX_SERDES_DATA03, + input [63:0] RX_SERDES_DATA04, + input [63:0] RX_SERDES_DATA05, + input [63:0] RX_SERDES_DATA06, + input [63:0] RX_SERDES_DATA07, + input [63:0] RX_SERDES_DATA08, + input [63:0] RX_SERDES_DATA09, + input [63:0] RX_SERDES_DATA10, + input [63:0] RX_SERDES_DATA11, + input [11:0] RX_SERDES_RESET, + input TX_BCTLIN0, + input TX_BCTLIN1, + input TX_BCTLIN2, + input TX_BCTLIN3, + input [11:0] TX_BYPASS_CTRLIN, + input [63:0] TX_BYPASS_DATAIN00, + input [63:0] TX_BYPASS_DATAIN01, + input [63:0] TX_BYPASS_DATAIN02, + input [63:0] TX_BYPASS_DATAIN03, + input [63:0] TX_BYPASS_DATAIN04, + input [63:0] TX_BYPASS_DATAIN05, + input [63:0] TX_BYPASS_DATAIN06, + input [63:0] TX_BYPASS_DATAIN07, + input [63:0] TX_BYPASS_DATAIN08, + input [63:0] TX_BYPASS_DATAIN09, + input [63:0] TX_BYPASS_DATAIN10, + input [63:0] TX_BYPASS_DATAIN11, + input TX_BYPASS_ENAIN, + input [7:0] TX_BYPASS_GEARBOX_SEQIN, + input [3:0] TX_BYPASS_MFRAMER_STATEIN, + input [10:0] TX_CHANIN0, + input [10:0] TX_CHANIN1, + input [10:0] TX_CHANIN2, + input [10:0] TX_CHANIN3, + input [127:0] TX_DATAIN0, + input [127:0] TX_DATAIN1, + input [127:0] TX_DATAIN2, + input [127:0] TX_DATAIN3, + input TX_ENAIN0, + input TX_ENAIN1, + input TX_ENAIN2, + input TX_ENAIN3, + input TX_EOPIN0, + input TX_EOPIN1, + input TX_EOPIN2, + input TX_EOPIN3, + input TX_ERRIN0, + input TX_ERRIN1, + input TX_ERRIN2, + input TX_ERRIN3, + input [3:0] TX_MTYIN0, + input [3:0] TX_MTYIN1, + input [3:0] TX_MTYIN2, + input [3:0] TX_MTYIN3, + input TX_RESET, + input TX_SERDES_REFCLK, + input TX_SERDES_REFCLK_RESET, + input TX_SOPIN0, + input TX_SOPIN1, + input TX_SOPIN2, + input TX_SOPIN3 +); + +// define constants + localparam MODULE_NAME = "ILKN"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "ILKN_dr.v" +`else + localparam [40:1] BYPASS_REG = BYPASS; + localparam [1:0] CTL_RX_BURSTMAX_REG = CTL_RX_BURSTMAX; + localparam [1:0] CTL_RX_CHAN_EXT_REG = CTL_RX_CHAN_EXT; + localparam [3:0] CTL_RX_LAST_LANE_REG = CTL_RX_LAST_LANE; + localparam [15:0] CTL_RX_MFRAMELEN_MINUS1_REG = CTL_RX_MFRAMELEN_MINUS1; + localparam [40:1] CTL_RX_PACKET_MODE_REG = CTL_RX_PACKET_MODE; + localparam [2:0] CTL_RX_RETRANS_MULT_REG = CTL_RX_RETRANS_MULT; + localparam [3:0] CTL_RX_RETRANS_RETRY_REG = CTL_RX_RETRANS_RETRY; + localparam [15:0] CTL_RX_RETRANS_TIMER1_REG = CTL_RX_RETRANS_TIMER1; + localparam [15:0] CTL_RX_RETRANS_TIMER2_REG = CTL_RX_RETRANS_TIMER2; + localparam [11:0] CTL_RX_RETRANS_WDOG_REG = CTL_RX_RETRANS_WDOG; + localparam [7:0] CTL_RX_RETRANS_WRAP_TIMER_REG = CTL_RX_RETRANS_WRAP_TIMER; + localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR; + localparam [1:0] CTL_TX_BURSTMAX_REG = CTL_TX_BURSTMAX; + localparam [2:0] CTL_TX_BURSTSHORT_REG = CTL_TX_BURSTSHORT; + localparam [1:0] CTL_TX_CHAN_EXT_REG = CTL_TX_CHAN_EXT; + localparam [40:1] CTL_TX_DISABLE_SKIPWORD_REG = CTL_TX_DISABLE_SKIPWORD; + localparam [6:0] CTL_TX_FC_CALLEN_REG = CTL_TX_FC_CALLEN; + localparam [3:0] CTL_TX_LAST_LANE_REG = CTL_TX_LAST_LANE; + localparam [15:0] CTL_TX_MFRAMELEN_MINUS1_REG = CTL_TX_MFRAMELEN_MINUS1; + localparam [13:0] CTL_TX_RETRANS_DEPTH_REG = CTL_TX_RETRANS_DEPTH; + localparam [2:0] CTL_TX_RETRANS_MULT_REG = CTL_TX_RETRANS_MULT; + localparam [1:0] CTL_TX_RETRANS_RAM_BANKS_REG = CTL_TX_RETRANS_RAM_BANKS; + localparam [40:1] MODE_REG = MODE; + localparam [24:1] SIM_VERSION_REG = SIM_VERSION; + localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire DRP_RDY_out; + wire RX_ENAOUT0_out; + wire RX_ENAOUT1_out; + wire RX_ENAOUT2_out; + wire RX_ENAOUT3_out; + wire RX_EOPOUT0_out; + wire RX_EOPOUT1_out; + wire RX_EOPOUT2_out; + wire RX_EOPOUT3_out; + wire RX_ERROUT0_out; + wire RX_ERROUT1_out; + wire RX_ERROUT2_out; + wire RX_ERROUT3_out; + wire RX_OVFOUT_out; + wire RX_SOPOUT0_out; + wire RX_SOPOUT1_out; + wire RX_SOPOUT2_out; + wire RX_SOPOUT3_out; + wire STAT_RX_ALIGNED_ERR_out; + wire STAT_RX_ALIGNED_out; + wire STAT_RX_BURSTMAX_ERR_out; + wire STAT_RX_BURST_ERR_out; + wire STAT_RX_CRC24_ERR_out; + wire STAT_RX_MEOP_ERR_out; + wire STAT_RX_MISALIGNED_out; + wire STAT_RX_MSOP_ERR_out; + wire STAT_RX_MUBITS_UPDATED_out; + wire STAT_RX_OVERFLOW_ERR_out; + wire STAT_RX_RETRANS_CRC24_ERR_out; + wire STAT_RX_RETRANS_DISC_out; + wire STAT_RX_RETRANS_REQ_out; + wire STAT_RX_RETRANS_RETRY_ERR_out; + wire STAT_RX_RETRANS_SEQ_UPDATED_out; + wire STAT_RX_RETRANS_WDOG_ERR_out; + wire STAT_RX_RETRANS_WRAP_ERR_out; + wire STAT_TX_BURST_ERR_out; + wire STAT_TX_ERRINJ_BITERR_DONE_out; + wire STAT_TX_OVERFLOW_ERR_out; + wire STAT_TX_RETRANS_BURST_ERR_out; + wire STAT_TX_RETRANS_BUSY_out; + wire STAT_TX_RETRANS_RAM_PERROUT_out; + wire STAT_TX_RETRANS_RAM_RD_B0_out; + wire STAT_TX_RETRANS_RAM_RD_B1_out; + wire STAT_TX_RETRANS_RAM_RD_B2_out; + wire STAT_TX_RETRANS_RAM_RD_B3_out; + wire STAT_TX_RETRANS_RAM_WE_B0_out; + wire STAT_TX_RETRANS_RAM_WE_B1_out; + wire STAT_TX_RETRANS_RAM_WE_B2_out; + wire STAT_TX_RETRANS_RAM_WE_B3_out; + wire STAT_TX_UNDERFLOW_ERR_out; + wire TX_OVFOUT_out; + wire TX_RDYOUT_out; + wire [10:0] RX_CHANOUT0_out; + wire [10:0] RX_CHANOUT1_out; + wire [10:0] RX_CHANOUT2_out; + wire [10:0] RX_CHANOUT3_out; + wire [11:0] RX_BYPASS_ENAOUT_out; + wire [11:0] RX_BYPASS_IS_AVAILOUT_out; + wire [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT_out; + wire [11:0] RX_BYPASS_IS_OVERFLOWOUT_out; + wire [11:0] RX_BYPASS_IS_SYNCEDOUT_out; + wire [11:0] RX_BYPASS_IS_SYNCWORDOUT_out; + wire [11:0] STAT_RX_BAD_TYPE_ERR_out; + wire [11:0] STAT_RX_CRC32_ERR_out; + wire [11:0] STAT_RX_CRC32_VALID_out; + wire [11:0] STAT_RX_DESCRAM_ERR_out; + wire [11:0] STAT_RX_DIAGWORD_INTFSTAT_out; + wire [11:0] STAT_RX_DIAGWORD_LANESTAT_out; + wire [11:0] STAT_RX_FRAMING_ERR_out; + wire [11:0] STAT_RX_MF_ERR_out; + wire [11:0] STAT_RX_MF_LEN_ERR_out; + wire [11:0] STAT_RX_MF_REPEAT_ERR_out; + wire [11:0] STAT_RX_SYNCED_ERR_out; + wire [11:0] STAT_RX_SYNCED_out; + wire [11:0] STAT_RX_WORD_SYNC_out; + wire [127:0] RX_DATAOUT0_out; + wire [127:0] RX_DATAOUT1_out; + wire [127:0] RX_DATAOUT2_out; + wire [127:0] RX_DATAOUT3_out; + wire [14:0] SCAN_OUT_DRPCTRL_out; + wire [15:0] DRP_DO_out; + wire [15:0] STAT_RX_RETRANS_LATENCY_out; + wire [1:0] STAT_TX_RETRANS_RAM_RSEL_out; + wire [249:0] SCAN_OUT_ILMAC_out; + wire [255:0] STAT_RX_FC_STAT_out; + wire [2:0] STAT_RX_RETRANS_STATE_out; + wire [3:0] RX_MTYOUT0_out; + wire [3:0] RX_MTYOUT1_out; + wire [3:0] RX_MTYOUT2_out; + wire [3:0] RX_MTYOUT3_out; + wire [4:0] STAT_RX_RETRANS_SUBSEQ_out; + wire [63:0] TX_SERDES_DATA00_out; + wire [63:0] TX_SERDES_DATA01_out; + wire [63:0] TX_SERDES_DATA02_out; + wire [63:0] TX_SERDES_DATA03_out; + wire [63:0] TX_SERDES_DATA04_out; + wire [63:0] TX_SERDES_DATA05_out; + wire [63:0] TX_SERDES_DATA06_out; + wire [63:0] TX_SERDES_DATA07_out; + wire [63:0] TX_SERDES_DATA08_out; + wire [63:0] TX_SERDES_DATA09_out; + wire [63:0] TX_SERDES_DATA10_out; + wire [63:0] TX_SERDES_DATA11_out; + wire [643:0] STAT_TX_RETRANS_RAM_WDATA_out; + wire [65:0] RX_BYPASS_DATAOUT00_out; + wire [65:0] RX_BYPASS_DATAOUT01_out; + wire [65:0] RX_BYPASS_DATAOUT02_out; + wire [65:0] RX_BYPASS_DATAOUT03_out; + wire [65:0] RX_BYPASS_DATAOUT04_out; + wire [65:0] RX_BYPASS_DATAOUT05_out; + wire [65:0] RX_BYPASS_DATAOUT06_out; + wire [65:0] RX_BYPASS_DATAOUT07_out; + wire [65:0] RX_BYPASS_DATAOUT08_out; + wire [65:0] RX_BYPASS_DATAOUT09_out; + wire [65:0] RX_BYPASS_DATAOUT10_out; + wire [65:0] RX_BYPASS_DATAOUT11_out; + wire [7:0] STAT_RX_MUBITS_out; + wire [7:0] STAT_RX_RETRANS_SEQ_out; + wire [8:0] STAT_TX_RETRANS_RAM_RADDR_out; + wire [8:0] STAT_TX_RETRANS_RAM_WADDR_out; + + wire DRP_RDY_delay; + wire RX_ENAOUT0_delay; + wire RX_ENAOUT1_delay; + wire RX_ENAOUT2_delay; + wire RX_ENAOUT3_delay; + wire RX_EOPOUT0_delay; + wire RX_EOPOUT1_delay; + wire RX_EOPOUT2_delay; + wire RX_EOPOUT3_delay; + wire RX_ERROUT0_delay; + wire RX_ERROUT1_delay; + wire RX_ERROUT2_delay; + wire RX_ERROUT3_delay; + wire RX_OVFOUT_delay; + wire RX_SOPOUT0_delay; + wire RX_SOPOUT1_delay; + wire RX_SOPOUT2_delay; + wire RX_SOPOUT3_delay; + wire STAT_RX_ALIGNED_ERR_delay; + wire STAT_RX_ALIGNED_delay; + wire STAT_RX_BURSTMAX_ERR_delay; + wire STAT_RX_BURST_ERR_delay; + wire STAT_RX_CRC24_ERR_delay; + wire STAT_RX_MEOP_ERR_delay; + wire STAT_RX_MISALIGNED_delay; + wire STAT_RX_MSOP_ERR_delay; + wire STAT_RX_MUBITS_UPDATED_delay; + wire STAT_RX_OVERFLOW_ERR_delay; + wire STAT_RX_RETRANS_CRC24_ERR_delay; + wire STAT_RX_RETRANS_DISC_delay; + wire STAT_RX_RETRANS_REQ_delay; + wire STAT_RX_RETRANS_RETRY_ERR_delay; + wire STAT_RX_RETRANS_SEQ_UPDATED_delay; + wire STAT_RX_RETRANS_WDOG_ERR_delay; + wire STAT_RX_RETRANS_WRAP_ERR_delay; + wire STAT_TX_BURST_ERR_delay; + wire STAT_TX_ERRINJ_BITERR_DONE_delay; + wire STAT_TX_OVERFLOW_ERR_delay; + wire STAT_TX_RETRANS_BURST_ERR_delay; + wire STAT_TX_RETRANS_BUSY_delay; + wire STAT_TX_RETRANS_RAM_PERROUT_delay; + wire STAT_TX_RETRANS_RAM_RD_B0_delay; + wire STAT_TX_RETRANS_RAM_RD_B1_delay; + wire STAT_TX_RETRANS_RAM_RD_B2_delay; + wire STAT_TX_RETRANS_RAM_RD_B3_delay; + wire STAT_TX_RETRANS_RAM_WE_B0_delay; + wire STAT_TX_RETRANS_RAM_WE_B1_delay; + wire STAT_TX_RETRANS_RAM_WE_B2_delay; + wire STAT_TX_RETRANS_RAM_WE_B3_delay; + wire STAT_TX_UNDERFLOW_ERR_delay; + wire TX_OVFOUT_delay; + wire TX_RDYOUT_delay; + wire [10:0] RX_CHANOUT0_delay; + wire [10:0] RX_CHANOUT1_delay; + wire [10:0] RX_CHANOUT2_delay; + wire [10:0] RX_CHANOUT3_delay; + wire [11:0] RX_BYPASS_ENAOUT_delay; + wire [11:0] RX_BYPASS_IS_AVAILOUT_delay; + wire [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT_delay; + wire [11:0] RX_BYPASS_IS_OVERFLOWOUT_delay; + wire [11:0] RX_BYPASS_IS_SYNCEDOUT_delay; + wire [11:0] RX_BYPASS_IS_SYNCWORDOUT_delay; + wire [11:0] STAT_RX_BAD_TYPE_ERR_delay; + wire [11:0] STAT_RX_CRC32_ERR_delay; + wire [11:0] STAT_RX_CRC32_VALID_delay; + wire [11:0] STAT_RX_DESCRAM_ERR_delay; + wire [11:0] STAT_RX_DIAGWORD_INTFSTAT_delay; + wire [11:0] STAT_RX_DIAGWORD_LANESTAT_delay; + wire [11:0] STAT_RX_FRAMING_ERR_delay; + wire [11:0] STAT_RX_MF_ERR_delay; + wire [11:0] STAT_RX_MF_LEN_ERR_delay; + wire [11:0] STAT_RX_MF_REPEAT_ERR_delay; + wire [11:0] STAT_RX_SYNCED_ERR_delay; + wire [11:0] STAT_RX_SYNCED_delay; + wire [11:0] STAT_RX_WORD_SYNC_delay; + wire [127:0] RX_DATAOUT0_delay; + wire [127:0] RX_DATAOUT1_delay; + wire [127:0] RX_DATAOUT2_delay; + wire [127:0] RX_DATAOUT3_delay; + wire [15:0] DRP_DO_delay; + wire [15:0] STAT_RX_RETRANS_LATENCY_delay; + wire [1:0] STAT_TX_RETRANS_RAM_RSEL_delay; + wire [255:0] STAT_RX_FC_STAT_delay; + wire [2:0] STAT_RX_RETRANS_STATE_delay; + wire [3:0] RX_MTYOUT0_delay; + wire [3:0] RX_MTYOUT1_delay; + wire [3:0] RX_MTYOUT2_delay; + wire [3:0] RX_MTYOUT3_delay; + wire [4:0] STAT_RX_RETRANS_SUBSEQ_delay; + wire [63:0] TX_SERDES_DATA00_delay; + wire [63:0] TX_SERDES_DATA01_delay; + wire [63:0] TX_SERDES_DATA02_delay; + wire [63:0] TX_SERDES_DATA03_delay; + wire [63:0] TX_SERDES_DATA04_delay; + wire [63:0] TX_SERDES_DATA05_delay; + wire [63:0] TX_SERDES_DATA06_delay; + wire [63:0] TX_SERDES_DATA07_delay; + wire [63:0] TX_SERDES_DATA08_delay; + wire [63:0] TX_SERDES_DATA09_delay; + wire [63:0] TX_SERDES_DATA10_delay; + wire [63:0] TX_SERDES_DATA11_delay; + wire [643:0] STAT_TX_RETRANS_RAM_WDATA_delay; + wire [65:0] RX_BYPASS_DATAOUT00_delay; + wire [65:0] RX_BYPASS_DATAOUT01_delay; + wire [65:0] RX_BYPASS_DATAOUT02_delay; + wire [65:0] RX_BYPASS_DATAOUT03_delay; + wire [65:0] RX_BYPASS_DATAOUT04_delay; + wire [65:0] RX_BYPASS_DATAOUT05_delay; + wire [65:0] RX_BYPASS_DATAOUT06_delay; + wire [65:0] RX_BYPASS_DATAOUT07_delay; + wire [65:0] RX_BYPASS_DATAOUT08_delay; + wire [65:0] RX_BYPASS_DATAOUT09_delay; + wire [65:0] RX_BYPASS_DATAOUT10_delay; + wire [65:0] RX_BYPASS_DATAOUT11_delay; + wire [7:0] STAT_RX_MUBITS_delay; + wire [7:0] STAT_RX_RETRANS_SEQ_delay; + wire [8:0] STAT_TX_RETRANS_RAM_RADDR_delay; + wire [8:0] STAT_TX_RETRANS_RAM_WADDR_delay; + + wire CORE_CLK_in; + wire CTL_RX_FORCE_RESYNC_in; + wire CTL_RX_RETRANS_ACK_in; + wire CTL_RX_RETRANS_ENABLE_in; + wire CTL_RX_RETRANS_ERRIN_in; + wire CTL_RX_RETRANS_FORCE_REQ_in; + wire CTL_RX_RETRANS_RESET_MODE_in; + wire CTL_RX_RETRANS_RESET_in; + wire CTL_TX_DIAGWORD_INTFSTAT_in; + wire CTL_TX_ENABLE_in; + wire CTL_TX_ERRINJ_BITERR_GO_in; + wire CTL_TX_RETRANS_ENABLE_in; + wire CTL_TX_RETRANS_RAM_PERRIN_in; + wire CTL_TX_RETRANS_REQ_VALID_in; + wire CTL_TX_RETRANS_REQ_in; + wire CTL_TX_RLIM_ENABLE_in; + wire DRP_CLK_in; + wire DRP_EN_in; + wire DRP_WE_in; + wire LBUS_CLK_in; + wire RX_BYPASS_FORCE_REALIGNIN_in; + wire RX_BYPASS_RDIN_in; + wire RX_RESET_in; + wire SCAN_EN_in; + wire TEST_MODE_in; + wire TEST_RESET_in; + wire TX_BCTLIN0_in; + wire TX_BCTLIN1_in; + wire TX_BCTLIN2_in; + wire TX_BCTLIN3_in; + wire TX_BYPASS_ENAIN_in; + wire TX_ENAIN0_in; + wire TX_ENAIN1_in; + wire TX_ENAIN2_in; + wire TX_ENAIN3_in; + wire TX_EOPIN0_in; + wire TX_EOPIN1_in; + wire TX_EOPIN2_in; + wire TX_EOPIN3_in; + wire TX_ERRIN0_in; + wire TX_ERRIN1_in; + wire TX_ERRIN2_in; + wire TX_ERRIN3_in; + wire TX_RESET_in; + wire TX_SERDES_REFCLK_RESET_in; + wire TX_SERDES_REFCLK_in; + wire TX_SOPIN0_in; + wire TX_SOPIN1_in; + wire TX_SOPIN2_in; + wire TX_SOPIN3_in; + wire [10:0] TX_CHANIN0_in; + wire [10:0] TX_CHANIN1_in; + wire [10:0] TX_CHANIN2_in; + wire [10:0] TX_CHANIN3_in; + wire [11:0] CTL_TX_DIAGWORD_LANESTAT_in; + wire [11:0] CTL_TX_RLIM_DELTA_in; + wire [11:0] CTL_TX_RLIM_MAX_in; + wire [11:0] RX_SERDES_CLK_in; + wire [11:0] RX_SERDES_RESET_in; + wire [11:0] TX_BYPASS_CTRLIN_in; + wire [127:0] TX_DATAIN0_in; + wire [127:0] TX_DATAIN1_in; + wire [127:0] TX_DATAIN2_in; + wire [127:0] TX_DATAIN3_in; + wire [14:0] SCAN_IN_DRPCTRL_in; + wire [15:0] DRP_DI_in; + wire [249:0] SCAN_IN_ILMAC_in; + wire [255:0] CTL_TX_FC_STAT_in; + wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_in; + wire [3:0] TX_BYPASS_MFRAMER_STATEIN_in; + wire [3:0] TX_MTYIN0_in; + wire [3:0] TX_MTYIN1_in; + wire [3:0] TX_MTYIN2_in; + wire [3:0] TX_MTYIN3_in; + wire [63:0] RX_SERDES_DATA00_in; + wire [63:0] RX_SERDES_DATA01_in; + wire [63:0] RX_SERDES_DATA02_in; + wire [63:0] RX_SERDES_DATA03_in; + wire [63:0] RX_SERDES_DATA04_in; + wire [63:0] RX_SERDES_DATA05_in; + wire [63:0] RX_SERDES_DATA06_in; + wire [63:0] RX_SERDES_DATA07_in; + wire [63:0] RX_SERDES_DATA08_in; + wire [63:0] RX_SERDES_DATA09_in; + wire [63:0] RX_SERDES_DATA10_in; + wire [63:0] RX_SERDES_DATA11_in; + wire [63:0] TX_BYPASS_DATAIN00_in; + wire [63:0] TX_BYPASS_DATAIN01_in; + wire [63:0] TX_BYPASS_DATAIN02_in; + wire [63:0] TX_BYPASS_DATAIN03_in; + wire [63:0] TX_BYPASS_DATAIN04_in; + wire [63:0] TX_BYPASS_DATAIN05_in; + wire [63:0] TX_BYPASS_DATAIN06_in; + wire [63:0] TX_BYPASS_DATAIN07_in; + wire [63:0] TX_BYPASS_DATAIN08_in; + wire [63:0] TX_BYPASS_DATAIN09_in; + wire [63:0] TX_BYPASS_DATAIN10_in; + wire [63:0] TX_BYPASS_DATAIN11_in; + wire [643:0] CTL_TX_RETRANS_RAM_RDATA_in; + wire [7:0] CTL_TX_MUBITS_in; + wire [7:0] CTL_TX_RLIM_INTV_in; + wire [7:0] TX_BYPASS_GEARBOX_SEQIN_in; + wire [9:0] DRP_ADDR_in; + + wire CORE_CLK_delay; + wire CTL_RX_FORCE_RESYNC_delay; + wire CTL_RX_RETRANS_ACK_delay; + wire CTL_RX_RETRANS_ENABLE_delay; + wire CTL_RX_RETRANS_ERRIN_delay; + wire CTL_RX_RETRANS_FORCE_REQ_delay; + wire CTL_RX_RETRANS_RESET_MODE_delay; + wire CTL_RX_RETRANS_RESET_delay; + wire CTL_TX_DIAGWORD_INTFSTAT_delay; + wire CTL_TX_ENABLE_delay; + wire CTL_TX_ERRINJ_BITERR_GO_delay; + wire CTL_TX_RETRANS_ENABLE_delay; + wire CTL_TX_RETRANS_RAM_PERRIN_delay; + wire CTL_TX_RETRANS_REQ_VALID_delay; + wire CTL_TX_RETRANS_REQ_delay; + wire CTL_TX_RLIM_ENABLE_delay; + wire DRP_CLK_delay; + wire DRP_EN_delay; + wire DRP_WE_delay; + wire LBUS_CLK_delay; + wire RX_BYPASS_FORCE_REALIGNIN_delay; + wire RX_BYPASS_RDIN_delay; + wire RX_RESET_delay; + wire TX_BCTLIN0_delay; + wire TX_BCTLIN1_delay; + wire TX_BCTLIN2_delay; + wire TX_BCTLIN3_delay; + wire TX_BYPASS_ENAIN_delay; + wire TX_ENAIN0_delay; + wire TX_ENAIN1_delay; + wire TX_ENAIN2_delay; + wire TX_ENAIN3_delay; + wire TX_EOPIN0_delay; + wire TX_EOPIN1_delay; + wire TX_EOPIN2_delay; + wire TX_EOPIN3_delay; + wire TX_ERRIN0_delay; + wire TX_ERRIN1_delay; + wire TX_ERRIN2_delay; + wire TX_ERRIN3_delay; + wire TX_RESET_delay; + wire TX_SERDES_REFCLK_RESET_delay; + wire TX_SERDES_REFCLK_delay; + wire TX_SOPIN0_delay; + wire TX_SOPIN1_delay; + wire TX_SOPIN2_delay; + wire TX_SOPIN3_delay; + wire [10:0] TX_CHANIN0_delay; + wire [10:0] TX_CHANIN1_delay; + wire [10:0] TX_CHANIN2_delay; + wire [10:0] TX_CHANIN3_delay; + wire [11:0] CTL_TX_DIAGWORD_LANESTAT_delay; + wire [11:0] CTL_TX_RLIM_DELTA_delay; + wire [11:0] CTL_TX_RLIM_MAX_delay; + wire [11:0] RX_SERDES_CLK_delay; + wire [11:0] RX_SERDES_RESET_delay; + wire [11:0] TX_BYPASS_CTRLIN_delay; + wire [127:0] TX_DATAIN0_delay; + wire [127:0] TX_DATAIN1_delay; + wire [127:0] TX_DATAIN2_delay; + wire [127:0] TX_DATAIN3_delay; + wire [15:0] DRP_DI_delay; + wire [255:0] CTL_TX_FC_STAT_delay; + wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_delay; + wire [3:0] TX_BYPASS_MFRAMER_STATEIN_delay; + wire [3:0] TX_MTYIN0_delay; + wire [3:0] TX_MTYIN1_delay; + wire [3:0] TX_MTYIN2_delay; + wire [3:0] TX_MTYIN3_delay; + wire [63:0] RX_SERDES_DATA00_delay; + wire [63:0] RX_SERDES_DATA01_delay; + wire [63:0] RX_SERDES_DATA02_delay; + wire [63:0] RX_SERDES_DATA03_delay; + wire [63:0] RX_SERDES_DATA04_delay; + wire [63:0] RX_SERDES_DATA05_delay; + wire [63:0] RX_SERDES_DATA06_delay; + wire [63:0] RX_SERDES_DATA07_delay; + wire [63:0] RX_SERDES_DATA08_delay; + wire [63:0] RX_SERDES_DATA09_delay; + wire [63:0] RX_SERDES_DATA10_delay; + wire [63:0] RX_SERDES_DATA11_delay; + wire [63:0] TX_BYPASS_DATAIN00_delay; + wire [63:0] TX_BYPASS_DATAIN01_delay; + wire [63:0] TX_BYPASS_DATAIN02_delay; + wire [63:0] TX_BYPASS_DATAIN03_delay; + wire [63:0] TX_BYPASS_DATAIN04_delay; + wire [63:0] TX_BYPASS_DATAIN05_delay; + wire [63:0] TX_BYPASS_DATAIN06_delay; + wire [63:0] TX_BYPASS_DATAIN07_delay; + wire [63:0] TX_BYPASS_DATAIN08_delay; + wire [63:0] TX_BYPASS_DATAIN09_delay; + wire [63:0] TX_BYPASS_DATAIN10_delay; + wire [63:0] TX_BYPASS_DATAIN11_delay; + wire [643:0] CTL_TX_RETRANS_RAM_RDATA_delay; + wire [7:0] CTL_TX_MUBITS_delay; + wire [7:0] CTL_TX_RLIM_INTV_delay; + wire [7:0] TX_BYPASS_GEARBOX_SEQIN_delay; + wire [9:0] DRP_ADDR_delay; + + assign #(out_delay) DRP_DO = DRP_DO_delay; + assign #(out_delay) DRP_RDY = DRP_RDY_delay; + assign #(out_delay) RX_BYPASS_DATAOUT00 = RX_BYPASS_DATAOUT00_delay; + assign #(out_delay) RX_BYPASS_DATAOUT01 = RX_BYPASS_DATAOUT01_delay; + assign #(out_delay) RX_BYPASS_DATAOUT02 = RX_BYPASS_DATAOUT02_delay; + assign #(out_delay) RX_BYPASS_DATAOUT03 = RX_BYPASS_DATAOUT03_delay; + assign #(out_delay) RX_BYPASS_DATAOUT04 = RX_BYPASS_DATAOUT04_delay; + assign #(out_delay) RX_BYPASS_DATAOUT05 = RX_BYPASS_DATAOUT05_delay; + assign #(out_delay) RX_BYPASS_DATAOUT06 = RX_BYPASS_DATAOUT06_delay; + assign #(out_delay) RX_BYPASS_DATAOUT07 = RX_BYPASS_DATAOUT07_delay; + assign #(out_delay) RX_BYPASS_DATAOUT08 = RX_BYPASS_DATAOUT08_delay; + assign #(out_delay) RX_BYPASS_DATAOUT09 = RX_BYPASS_DATAOUT09_delay; + assign #(out_delay) RX_BYPASS_DATAOUT10 = RX_BYPASS_DATAOUT10_delay; + assign #(out_delay) RX_BYPASS_DATAOUT11 = RX_BYPASS_DATAOUT11_delay; + assign #(out_delay) RX_BYPASS_ENAOUT = RX_BYPASS_ENAOUT_delay; + assign #(out_delay) RX_BYPASS_IS_AVAILOUT = RX_BYPASS_IS_AVAILOUT_delay; + assign #(out_delay) RX_BYPASS_IS_BADLYFRAMEDOUT = RX_BYPASS_IS_BADLYFRAMEDOUT_delay; + assign #(out_delay) RX_BYPASS_IS_OVERFLOWOUT = RX_BYPASS_IS_OVERFLOWOUT_delay; + assign #(out_delay) RX_BYPASS_IS_SYNCEDOUT = RX_BYPASS_IS_SYNCEDOUT_delay; + assign #(out_delay) RX_BYPASS_IS_SYNCWORDOUT = RX_BYPASS_IS_SYNCWORDOUT_delay; + assign #(out_delay) RX_CHANOUT0 = RX_CHANOUT0_delay; + assign #(out_delay) RX_CHANOUT1 = RX_CHANOUT1_delay; + assign #(out_delay) RX_CHANOUT2 = RX_CHANOUT2_delay; + assign #(out_delay) RX_CHANOUT3 = RX_CHANOUT3_delay; + assign #(out_delay) RX_DATAOUT0 = RX_DATAOUT0_delay; + assign #(out_delay) RX_DATAOUT1 = RX_DATAOUT1_delay; + assign #(out_delay) RX_DATAOUT2 = RX_DATAOUT2_delay; + assign #(out_delay) RX_DATAOUT3 = RX_DATAOUT3_delay; + assign #(out_delay) RX_ENAOUT0 = RX_ENAOUT0_delay; + assign #(out_delay) RX_ENAOUT1 = RX_ENAOUT1_delay; + assign #(out_delay) RX_ENAOUT2 = RX_ENAOUT2_delay; + assign #(out_delay) RX_ENAOUT3 = RX_ENAOUT3_delay; + assign #(out_delay) RX_EOPOUT0 = RX_EOPOUT0_delay; + assign #(out_delay) RX_EOPOUT1 = RX_EOPOUT1_delay; + assign #(out_delay) RX_EOPOUT2 = RX_EOPOUT2_delay; + assign #(out_delay) RX_EOPOUT3 = RX_EOPOUT3_delay; + assign #(out_delay) RX_ERROUT0 = RX_ERROUT0_delay; + assign #(out_delay) RX_ERROUT1 = RX_ERROUT1_delay; + assign #(out_delay) RX_ERROUT2 = RX_ERROUT2_delay; + assign #(out_delay) RX_ERROUT3 = RX_ERROUT3_delay; + assign #(out_delay) RX_MTYOUT0 = RX_MTYOUT0_delay; + assign #(out_delay) RX_MTYOUT1 = RX_MTYOUT1_delay; + assign #(out_delay) RX_MTYOUT2 = RX_MTYOUT2_delay; + assign #(out_delay) RX_MTYOUT3 = RX_MTYOUT3_delay; + assign #(out_delay) RX_OVFOUT = RX_OVFOUT_delay; + assign #(out_delay) RX_SOPOUT0 = RX_SOPOUT0_delay; + assign #(out_delay) RX_SOPOUT1 = RX_SOPOUT1_delay; + assign #(out_delay) RX_SOPOUT2 = RX_SOPOUT2_delay; + assign #(out_delay) RX_SOPOUT3 = RX_SOPOUT3_delay; + assign #(out_delay) STAT_RX_ALIGNED = STAT_RX_ALIGNED_delay; + assign #(out_delay) STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_delay; + assign #(out_delay) STAT_RX_BAD_TYPE_ERR = STAT_RX_BAD_TYPE_ERR_delay; + assign #(out_delay) STAT_RX_BURSTMAX_ERR = STAT_RX_BURSTMAX_ERR_delay; + assign #(out_delay) STAT_RX_BURST_ERR = STAT_RX_BURST_ERR_delay; + assign #(out_delay) STAT_RX_CRC24_ERR = STAT_RX_CRC24_ERR_delay; + assign #(out_delay) STAT_RX_CRC32_ERR = STAT_RX_CRC32_ERR_delay; + assign #(out_delay) STAT_RX_CRC32_VALID = STAT_RX_CRC32_VALID_delay; + assign #(out_delay) STAT_RX_DESCRAM_ERR = STAT_RX_DESCRAM_ERR_delay; + assign #(out_delay) STAT_RX_DIAGWORD_INTFSTAT = STAT_RX_DIAGWORD_INTFSTAT_delay; + assign #(out_delay) STAT_RX_DIAGWORD_LANESTAT = STAT_RX_DIAGWORD_LANESTAT_delay; + assign #(out_delay) STAT_RX_FC_STAT = STAT_RX_FC_STAT_delay; + assign #(out_delay) STAT_RX_FRAMING_ERR = STAT_RX_FRAMING_ERR_delay; + assign #(out_delay) STAT_RX_MEOP_ERR = STAT_RX_MEOP_ERR_delay; + assign #(out_delay) STAT_RX_MF_ERR = STAT_RX_MF_ERR_delay; + assign #(out_delay) STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_delay; + assign #(out_delay) STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_delay; + assign #(out_delay) STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_delay; + assign #(out_delay) STAT_RX_MSOP_ERR = STAT_RX_MSOP_ERR_delay; + assign #(out_delay) STAT_RX_MUBITS = STAT_RX_MUBITS_delay; + assign #(out_delay) STAT_RX_MUBITS_UPDATED = STAT_RX_MUBITS_UPDATED_delay; + assign #(out_delay) STAT_RX_OVERFLOW_ERR = STAT_RX_OVERFLOW_ERR_delay; + assign #(out_delay) STAT_RX_RETRANS_CRC24_ERR = STAT_RX_RETRANS_CRC24_ERR_delay; + assign #(out_delay) STAT_RX_RETRANS_DISC = STAT_RX_RETRANS_DISC_delay; + assign #(out_delay) STAT_RX_RETRANS_LATENCY = STAT_RX_RETRANS_LATENCY_delay; + assign #(out_delay) STAT_RX_RETRANS_REQ = STAT_RX_RETRANS_REQ_delay; + assign #(out_delay) STAT_RX_RETRANS_RETRY_ERR = STAT_RX_RETRANS_RETRY_ERR_delay; + assign #(out_delay) STAT_RX_RETRANS_SEQ = STAT_RX_RETRANS_SEQ_delay; + assign #(out_delay) STAT_RX_RETRANS_SEQ_UPDATED = STAT_RX_RETRANS_SEQ_UPDATED_delay; + assign #(out_delay) STAT_RX_RETRANS_STATE = STAT_RX_RETRANS_STATE_delay; + assign #(out_delay) STAT_RX_RETRANS_SUBSEQ = STAT_RX_RETRANS_SUBSEQ_delay; + assign #(out_delay) STAT_RX_RETRANS_WDOG_ERR = STAT_RX_RETRANS_WDOG_ERR_delay; + assign #(out_delay) STAT_RX_RETRANS_WRAP_ERR = STAT_RX_RETRANS_WRAP_ERR_delay; + assign #(out_delay) STAT_RX_SYNCED = STAT_RX_SYNCED_delay; + assign #(out_delay) STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_delay; + assign #(out_delay) STAT_RX_WORD_SYNC = STAT_RX_WORD_SYNC_delay; + assign #(out_delay) STAT_TX_BURST_ERR = STAT_TX_BURST_ERR_delay; + assign #(out_delay) STAT_TX_ERRINJ_BITERR_DONE = STAT_TX_ERRINJ_BITERR_DONE_delay; + assign #(out_delay) STAT_TX_OVERFLOW_ERR = STAT_TX_OVERFLOW_ERR_delay; + assign #(out_delay) STAT_TX_RETRANS_BURST_ERR = STAT_TX_RETRANS_BURST_ERR_delay; + assign #(out_delay) STAT_TX_RETRANS_BUSY = STAT_TX_RETRANS_BUSY_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_PERROUT = STAT_TX_RETRANS_RAM_PERROUT_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RADDR = STAT_TX_RETRANS_RAM_RADDR_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B0 = STAT_TX_RETRANS_RAM_RD_B0_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B1 = STAT_TX_RETRANS_RAM_RD_B1_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B2 = STAT_TX_RETRANS_RAM_RD_B2_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B3 = STAT_TX_RETRANS_RAM_RD_B3_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_RSEL = STAT_TX_RETRANS_RAM_RSEL_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WADDR = STAT_TX_RETRANS_RAM_WADDR_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WDATA = STAT_TX_RETRANS_RAM_WDATA_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B0 = STAT_TX_RETRANS_RAM_WE_B0_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B1 = STAT_TX_RETRANS_RAM_WE_B1_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B2 = STAT_TX_RETRANS_RAM_WE_B2_delay; + assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B3 = STAT_TX_RETRANS_RAM_WE_B3_delay; + assign #(out_delay) STAT_TX_UNDERFLOW_ERR = STAT_TX_UNDERFLOW_ERR_delay; + assign #(out_delay) TX_OVFOUT = TX_OVFOUT_delay; + assign #(out_delay) TX_RDYOUT = TX_RDYOUT_delay; + assign #(out_delay) TX_SERDES_DATA00 = TX_SERDES_DATA00_delay; + assign #(out_delay) TX_SERDES_DATA01 = TX_SERDES_DATA01_delay; + assign #(out_delay) TX_SERDES_DATA02 = TX_SERDES_DATA02_delay; + assign #(out_delay) TX_SERDES_DATA03 = TX_SERDES_DATA03_delay; + assign #(out_delay) TX_SERDES_DATA04 = TX_SERDES_DATA04_delay; + assign #(out_delay) TX_SERDES_DATA05 = TX_SERDES_DATA05_delay; + assign #(out_delay) TX_SERDES_DATA06 = TX_SERDES_DATA06_delay; + assign #(out_delay) TX_SERDES_DATA07 = TX_SERDES_DATA07_delay; + assign #(out_delay) TX_SERDES_DATA08 = TX_SERDES_DATA08_delay; + assign #(out_delay) TX_SERDES_DATA09 = TX_SERDES_DATA09_delay; + assign #(out_delay) TX_SERDES_DATA10 = TX_SERDES_DATA10_delay; + assign #(out_delay) TX_SERDES_DATA11 = TX_SERDES_DATA11_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CORE_CLK_delay = CORE_CLK; + assign #(inclk_delay) DRP_CLK_delay = DRP_CLK; + assign #(inclk_delay) LBUS_CLK_delay = LBUS_CLK; + assign #(inclk_delay) TX_SERDES_REFCLK_delay = TX_SERDES_REFCLK; + + assign #(in_delay) CTL_RX_FORCE_RESYNC_delay = CTL_RX_FORCE_RESYNC; + assign #(in_delay) CTL_RX_RETRANS_ACK_delay = CTL_RX_RETRANS_ACK; + assign #(in_delay) CTL_RX_RETRANS_ENABLE_delay = CTL_RX_RETRANS_ENABLE; + assign #(in_delay) CTL_RX_RETRANS_ERRIN_delay = CTL_RX_RETRANS_ERRIN; + assign #(in_delay) CTL_RX_RETRANS_FORCE_REQ_delay = CTL_RX_RETRANS_FORCE_REQ; + assign #(in_delay) CTL_RX_RETRANS_RESET_MODE_delay = CTL_RX_RETRANS_RESET_MODE; + assign #(in_delay) CTL_RX_RETRANS_RESET_delay = CTL_RX_RETRANS_RESET; + assign #(in_delay) CTL_TX_DIAGWORD_INTFSTAT_delay = CTL_TX_DIAGWORD_INTFSTAT; + assign #(in_delay) CTL_TX_DIAGWORD_LANESTAT_delay = CTL_TX_DIAGWORD_LANESTAT; + assign #(in_delay) CTL_TX_ENABLE_delay = CTL_TX_ENABLE; + assign #(in_delay) CTL_TX_ERRINJ_BITERR_GO_delay = CTL_TX_ERRINJ_BITERR_GO; + assign #(in_delay) CTL_TX_ERRINJ_BITERR_LANE_delay = CTL_TX_ERRINJ_BITERR_LANE; + assign #(in_delay) CTL_TX_FC_STAT_delay = CTL_TX_FC_STAT; + assign #(in_delay) CTL_TX_MUBITS_delay = CTL_TX_MUBITS; + assign #(in_delay) CTL_TX_RETRANS_ENABLE_delay = CTL_TX_RETRANS_ENABLE; + assign #(in_delay) CTL_TX_RETRANS_RAM_PERRIN_delay = CTL_TX_RETRANS_RAM_PERRIN; + assign #(in_delay) CTL_TX_RETRANS_RAM_RDATA_delay = CTL_TX_RETRANS_RAM_RDATA; + assign #(in_delay) CTL_TX_RETRANS_REQ_VALID_delay = CTL_TX_RETRANS_REQ_VALID; + assign #(in_delay) CTL_TX_RETRANS_REQ_delay = CTL_TX_RETRANS_REQ; + assign #(in_delay) CTL_TX_RLIM_DELTA_delay = CTL_TX_RLIM_DELTA; + assign #(in_delay) CTL_TX_RLIM_ENABLE_delay = CTL_TX_RLIM_ENABLE; + assign #(in_delay) CTL_TX_RLIM_INTV_delay = CTL_TX_RLIM_INTV; + assign #(in_delay) CTL_TX_RLIM_MAX_delay = CTL_TX_RLIM_MAX; + assign #(in_delay) DRP_ADDR_delay = DRP_ADDR; + assign #(in_delay) DRP_DI_delay = DRP_DI; + assign #(in_delay) DRP_EN_delay = DRP_EN; + assign #(in_delay) DRP_WE_delay = DRP_WE; + assign #(in_delay) RX_BYPASS_FORCE_REALIGNIN_delay = RX_BYPASS_FORCE_REALIGNIN; + assign #(in_delay) RX_BYPASS_RDIN_delay = RX_BYPASS_RDIN; + assign #(in_delay) RX_RESET_delay = RX_RESET; + assign #(in_delay) RX_SERDES_DATA00_delay = RX_SERDES_DATA00; + assign #(in_delay) RX_SERDES_DATA01_delay = RX_SERDES_DATA01; + assign #(in_delay) RX_SERDES_DATA02_delay = RX_SERDES_DATA02; + assign #(in_delay) RX_SERDES_DATA03_delay = RX_SERDES_DATA03; + assign #(in_delay) RX_SERDES_DATA04_delay = RX_SERDES_DATA04; + assign #(in_delay) RX_SERDES_DATA05_delay = RX_SERDES_DATA05; + assign #(in_delay) RX_SERDES_DATA06_delay = RX_SERDES_DATA06; + assign #(in_delay) RX_SERDES_DATA07_delay = RX_SERDES_DATA07; + assign #(in_delay) RX_SERDES_DATA08_delay = RX_SERDES_DATA08; + assign #(in_delay) RX_SERDES_DATA09_delay = RX_SERDES_DATA09; + assign #(in_delay) RX_SERDES_DATA10_delay = RX_SERDES_DATA10; + assign #(in_delay) RX_SERDES_DATA11_delay = RX_SERDES_DATA11; + assign #(in_delay) RX_SERDES_RESET_delay = RX_SERDES_RESET; + assign #(in_delay) TX_BCTLIN0_delay = TX_BCTLIN0; + assign #(in_delay) TX_BCTLIN1_delay = TX_BCTLIN1; + assign #(in_delay) TX_BCTLIN2_delay = TX_BCTLIN2; + assign #(in_delay) TX_BCTLIN3_delay = TX_BCTLIN3; + assign #(in_delay) TX_BYPASS_CTRLIN_delay = TX_BYPASS_CTRLIN; + assign #(in_delay) TX_BYPASS_DATAIN00_delay = TX_BYPASS_DATAIN00; + assign #(in_delay) TX_BYPASS_DATAIN01_delay = TX_BYPASS_DATAIN01; + assign #(in_delay) TX_BYPASS_DATAIN02_delay = TX_BYPASS_DATAIN02; + assign #(in_delay) TX_BYPASS_DATAIN03_delay = TX_BYPASS_DATAIN03; + assign #(in_delay) TX_BYPASS_DATAIN04_delay = TX_BYPASS_DATAIN04; + assign #(in_delay) TX_BYPASS_DATAIN05_delay = TX_BYPASS_DATAIN05; + assign #(in_delay) TX_BYPASS_DATAIN06_delay = TX_BYPASS_DATAIN06; + assign #(in_delay) TX_BYPASS_DATAIN07_delay = TX_BYPASS_DATAIN07; + assign #(in_delay) TX_BYPASS_DATAIN08_delay = TX_BYPASS_DATAIN08; + assign #(in_delay) TX_BYPASS_DATAIN09_delay = TX_BYPASS_DATAIN09; + assign #(in_delay) TX_BYPASS_DATAIN10_delay = TX_BYPASS_DATAIN10; + assign #(in_delay) TX_BYPASS_DATAIN11_delay = TX_BYPASS_DATAIN11; + assign #(in_delay) TX_BYPASS_ENAIN_delay = TX_BYPASS_ENAIN; + assign #(in_delay) TX_BYPASS_GEARBOX_SEQIN_delay = TX_BYPASS_GEARBOX_SEQIN; + assign #(in_delay) TX_BYPASS_MFRAMER_STATEIN_delay = TX_BYPASS_MFRAMER_STATEIN; + assign #(in_delay) TX_CHANIN0_delay = TX_CHANIN0; + assign #(in_delay) TX_CHANIN1_delay = TX_CHANIN1; + assign #(in_delay) TX_CHANIN2_delay = TX_CHANIN2; + assign #(in_delay) TX_CHANIN3_delay = TX_CHANIN3; + assign #(in_delay) TX_DATAIN0_delay = TX_DATAIN0; + assign #(in_delay) TX_DATAIN1_delay = TX_DATAIN1; + assign #(in_delay) TX_DATAIN2_delay = TX_DATAIN2; + assign #(in_delay) TX_DATAIN3_delay = TX_DATAIN3; + assign #(in_delay) TX_ENAIN0_delay = TX_ENAIN0; + assign #(in_delay) TX_ENAIN1_delay = TX_ENAIN1; + assign #(in_delay) TX_ENAIN2_delay = TX_ENAIN2; + assign #(in_delay) TX_ENAIN3_delay = TX_ENAIN3; + assign #(in_delay) TX_EOPIN0_delay = TX_EOPIN0; + assign #(in_delay) TX_EOPIN1_delay = TX_EOPIN1; + assign #(in_delay) TX_EOPIN2_delay = TX_EOPIN2; + assign #(in_delay) TX_EOPIN3_delay = TX_EOPIN3; + assign #(in_delay) TX_ERRIN0_delay = TX_ERRIN0; + assign #(in_delay) TX_ERRIN1_delay = TX_ERRIN1; + assign #(in_delay) TX_ERRIN2_delay = TX_ERRIN2; + assign #(in_delay) TX_ERRIN3_delay = TX_ERRIN3; + assign #(in_delay) TX_MTYIN0_delay = TX_MTYIN0; + assign #(in_delay) TX_MTYIN1_delay = TX_MTYIN1; + assign #(in_delay) TX_MTYIN2_delay = TX_MTYIN2; + assign #(in_delay) TX_MTYIN3_delay = TX_MTYIN3; + assign #(in_delay) TX_RESET_delay = TX_RESET; + assign #(in_delay) TX_SERDES_REFCLK_RESET_delay = TX_SERDES_REFCLK_RESET; + assign #(in_delay) TX_SOPIN0_delay = TX_SOPIN0; + assign #(in_delay) TX_SOPIN1_delay = TX_SOPIN1; + assign #(in_delay) TX_SOPIN2_delay = TX_SOPIN2; + assign #(in_delay) TX_SOPIN3_delay = TX_SOPIN3; + assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK; +`endif + +// inputs with no timing checks + //assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK; + + + assign DRP_DO_delay = DRP_DO_out; + assign DRP_RDY_delay = DRP_RDY_out; + assign RX_BYPASS_DATAOUT00_delay = RX_BYPASS_DATAOUT00_out; + assign RX_BYPASS_DATAOUT01_delay = RX_BYPASS_DATAOUT01_out; + assign RX_BYPASS_DATAOUT02_delay = RX_BYPASS_DATAOUT02_out; + assign RX_BYPASS_DATAOUT03_delay = RX_BYPASS_DATAOUT03_out; + assign RX_BYPASS_DATAOUT04_delay = RX_BYPASS_DATAOUT04_out; + assign RX_BYPASS_DATAOUT05_delay = RX_BYPASS_DATAOUT05_out; + assign RX_BYPASS_DATAOUT06_delay = RX_BYPASS_DATAOUT06_out; + assign RX_BYPASS_DATAOUT07_delay = RX_BYPASS_DATAOUT07_out; + assign RX_BYPASS_DATAOUT08_delay = RX_BYPASS_DATAOUT08_out; + assign RX_BYPASS_DATAOUT09_delay = RX_BYPASS_DATAOUT09_out; + assign RX_BYPASS_DATAOUT10_delay = RX_BYPASS_DATAOUT10_out; + assign RX_BYPASS_DATAOUT11_delay = RX_BYPASS_DATAOUT11_out; + assign RX_BYPASS_ENAOUT_delay = RX_BYPASS_ENAOUT_out; + assign RX_BYPASS_IS_AVAILOUT_delay = RX_BYPASS_IS_AVAILOUT_out; + assign RX_BYPASS_IS_BADLYFRAMEDOUT_delay = RX_BYPASS_IS_BADLYFRAMEDOUT_out; + assign RX_BYPASS_IS_OVERFLOWOUT_delay = RX_BYPASS_IS_OVERFLOWOUT_out; + assign RX_BYPASS_IS_SYNCEDOUT_delay = RX_BYPASS_IS_SYNCEDOUT_out; + assign RX_BYPASS_IS_SYNCWORDOUT_delay = RX_BYPASS_IS_SYNCWORDOUT_out; + assign RX_CHANOUT0_delay = RX_CHANOUT0_out; + assign RX_CHANOUT1_delay = RX_CHANOUT1_out; + assign RX_CHANOUT2_delay = RX_CHANOUT2_out; + assign RX_CHANOUT3_delay = RX_CHANOUT3_out; + assign RX_DATAOUT0_delay = RX_DATAOUT0_out; + assign RX_DATAOUT1_delay = RX_DATAOUT1_out; + assign RX_DATAOUT2_delay = RX_DATAOUT2_out; + assign RX_DATAOUT3_delay = RX_DATAOUT3_out; + assign RX_ENAOUT0_delay = RX_ENAOUT0_out; + assign RX_ENAOUT1_delay = RX_ENAOUT1_out; + assign RX_ENAOUT2_delay = RX_ENAOUT2_out; + assign RX_ENAOUT3_delay = RX_ENAOUT3_out; + assign RX_EOPOUT0_delay = RX_EOPOUT0_out; + assign RX_EOPOUT1_delay = RX_EOPOUT1_out; + assign RX_EOPOUT2_delay = RX_EOPOUT2_out; + assign RX_EOPOUT3_delay = RX_EOPOUT3_out; + assign RX_ERROUT0_delay = RX_ERROUT0_out; + assign RX_ERROUT1_delay = RX_ERROUT1_out; + assign RX_ERROUT2_delay = RX_ERROUT2_out; + assign RX_ERROUT3_delay = RX_ERROUT3_out; + assign RX_MTYOUT0_delay = RX_MTYOUT0_out; + assign RX_MTYOUT1_delay = RX_MTYOUT1_out; + assign RX_MTYOUT2_delay = RX_MTYOUT2_out; + assign RX_MTYOUT3_delay = RX_MTYOUT3_out; + assign RX_OVFOUT_delay = RX_OVFOUT_out; + assign RX_SOPOUT0_delay = RX_SOPOUT0_out; + assign RX_SOPOUT1_delay = RX_SOPOUT1_out; + assign RX_SOPOUT2_delay = RX_SOPOUT2_out; + assign RX_SOPOUT3_delay = RX_SOPOUT3_out; + assign STAT_RX_ALIGNED_ERR_delay = STAT_RX_ALIGNED_ERR_out; + assign STAT_RX_ALIGNED_delay = STAT_RX_ALIGNED_out; + assign STAT_RX_BAD_TYPE_ERR_delay = STAT_RX_BAD_TYPE_ERR_out; + assign STAT_RX_BURSTMAX_ERR_delay = STAT_RX_BURSTMAX_ERR_out; + assign STAT_RX_BURST_ERR_delay = STAT_RX_BURST_ERR_out; + assign STAT_RX_CRC24_ERR_delay = STAT_RX_CRC24_ERR_out; + assign STAT_RX_CRC32_ERR_delay = STAT_RX_CRC32_ERR_out; + assign STAT_RX_CRC32_VALID_delay = STAT_RX_CRC32_VALID_out; + assign STAT_RX_DESCRAM_ERR_delay = STAT_RX_DESCRAM_ERR_out; + assign STAT_RX_DIAGWORD_INTFSTAT_delay = STAT_RX_DIAGWORD_INTFSTAT_out; + assign STAT_RX_DIAGWORD_LANESTAT_delay = STAT_RX_DIAGWORD_LANESTAT_out; + assign STAT_RX_FC_STAT_delay = STAT_RX_FC_STAT_out; + assign STAT_RX_FRAMING_ERR_delay = STAT_RX_FRAMING_ERR_out; + assign STAT_RX_MEOP_ERR_delay = STAT_RX_MEOP_ERR_out; + assign STAT_RX_MF_ERR_delay = STAT_RX_MF_ERR_out; + assign STAT_RX_MF_LEN_ERR_delay = STAT_RX_MF_LEN_ERR_out; + assign STAT_RX_MF_REPEAT_ERR_delay = STAT_RX_MF_REPEAT_ERR_out; + assign STAT_RX_MISALIGNED_delay = STAT_RX_MISALIGNED_out; + assign STAT_RX_MSOP_ERR_delay = STAT_RX_MSOP_ERR_out; + assign STAT_RX_MUBITS_UPDATED_delay = STAT_RX_MUBITS_UPDATED_out; + assign STAT_RX_MUBITS_delay = STAT_RX_MUBITS_out; + assign STAT_RX_OVERFLOW_ERR_delay = STAT_RX_OVERFLOW_ERR_out; + assign STAT_RX_RETRANS_CRC24_ERR_delay = STAT_RX_RETRANS_CRC24_ERR_out; + assign STAT_RX_RETRANS_DISC_delay = STAT_RX_RETRANS_DISC_out; + assign STAT_RX_RETRANS_LATENCY_delay = STAT_RX_RETRANS_LATENCY_out; + assign STAT_RX_RETRANS_REQ_delay = STAT_RX_RETRANS_REQ_out; + assign STAT_RX_RETRANS_RETRY_ERR_delay = STAT_RX_RETRANS_RETRY_ERR_out; + assign STAT_RX_RETRANS_SEQ_UPDATED_delay = STAT_RX_RETRANS_SEQ_UPDATED_out; + assign STAT_RX_RETRANS_SEQ_delay = STAT_RX_RETRANS_SEQ_out; + assign STAT_RX_RETRANS_STATE_delay = STAT_RX_RETRANS_STATE_out; + assign STAT_RX_RETRANS_SUBSEQ_delay = STAT_RX_RETRANS_SUBSEQ_out; + assign STAT_RX_RETRANS_WDOG_ERR_delay = STAT_RX_RETRANS_WDOG_ERR_out; + assign STAT_RX_RETRANS_WRAP_ERR_delay = STAT_RX_RETRANS_WRAP_ERR_out; + assign STAT_RX_SYNCED_ERR_delay = STAT_RX_SYNCED_ERR_out; + assign STAT_RX_SYNCED_delay = STAT_RX_SYNCED_out; + assign STAT_RX_WORD_SYNC_delay = STAT_RX_WORD_SYNC_out; + assign STAT_TX_BURST_ERR_delay = STAT_TX_BURST_ERR_out; + assign STAT_TX_ERRINJ_BITERR_DONE_delay = STAT_TX_ERRINJ_BITERR_DONE_out; + assign STAT_TX_OVERFLOW_ERR_delay = STAT_TX_OVERFLOW_ERR_out; + assign STAT_TX_RETRANS_BURST_ERR_delay = STAT_TX_RETRANS_BURST_ERR_out; + assign STAT_TX_RETRANS_BUSY_delay = STAT_TX_RETRANS_BUSY_out; + assign STAT_TX_RETRANS_RAM_PERROUT_delay = STAT_TX_RETRANS_RAM_PERROUT_out; + assign STAT_TX_RETRANS_RAM_RADDR_delay = STAT_TX_RETRANS_RAM_RADDR_out; + assign STAT_TX_RETRANS_RAM_RD_B0_delay = STAT_TX_RETRANS_RAM_RD_B0_out; + assign STAT_TX_RETRANS_RAM_RD_B1_delay = STAT_TX_RETRANS_RAM_RD_B1_out; + assign STAT_TX_RETRANS_RAM_RD_B2_delay = STAT_TX_RETRANS_RAM_RD_B2_out; + assign STAT_TX_RETRANS_RAM_RD_B3_delay = STAT_TX_RETRANS_RAM_RD_B3_out; + assign STAT_TX_RETRANS_RAM_RSEL_delay = STAT_TX_RETRANS_RAM_RSEL_out; + assign STAT_TX_RETRANS_RAM_WADDR_delay = STAT_TX_RETRANS_RAM_WADDR_out; + assign STAT_TX_RETRANS_RAM_WDATA_delay = STAT_TX_RETRANS_RAM_WDATA_out; + assign STAT_TX_RETRANS_RAM_WE_B0_delay = STAT_TX_RETRANS_RAM_WE_B0_out; + assign STAT_TX_RETRANS_RAM_WE_B1_delay = STAT_TX_RETRANS_RAM_WE_B1_out; + assign STAT_TX_RETRANS_RAM_WE_B2_delay = STAT_TX_RETRANS_RAM_WE_B2_out; + assign STAT_TX_RETRANS_RAM_WE_B3_delay = STAT_TX_RETRANS_RAM_WE_B3_out; + assign STAT_TX_UNDERFLOW_ERR_delay = STAT_TX_UNDERFLOW_ERR_out; + assign TX_OVFOUT_delay = TX_OVFOUT_out; + assign TX_RDYOUT_delay = TX_RDYOUT_out; + assign TX_SERDES_DATA00_delay = TX_SERDES_DATA00_out; + assign TX_SERDES_DATA01_delay = TX_SERDES_DATA01_out; + assign TX_SERDES_DATA02_delay = TX_SERDES_DATA02_out; + assign TX_SERDES_DATA03_delay = TX_SERDES_DATA03_out; + assign TX_SERDES_DATA04_delay = TX_SERDES_DATA04_out; + assign TX_SERDES_DATA05_delay = TX_SERDES_DATA05_out; + assign TX_SERDES_DATA06_delay = TX_SERDES_DATA06_out; + assign TX_SERDES_DATA07_delay = TX_SERDES_DATA07_out; + assign TX_SERDES_DATA08_delay = TX_SERDES_DATA08_out; + assign TX_SERDES_DATA09_delay = TX_SERDES_DATA09_out; + assign TX_SERDES_DATA10_delay = TX_SERDES_DATA10_out; + assign TX_SERDES_DATA11_delay = TX_SERDES_DATA11_out; + + assign CORE_CLK_in = CORE_CLK_delay; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay; + assign CTL_RX_RETRANS_ACK_in = CTL_RX_RETRANS_ACK_delay; + assign CTL_RX_RETRANS_ENABLE_in = CTL_RX_RETRANS_ENABLE_delay; + assign CTL_RX_RETRANS_ERRIN_in = CTL_RX_RETRANS_ERRIN_delay; + assign CTL_RX_RETRANS_FORCE_REQ_in = CTL_RX_RETRANS_FORCE_REQ_delay; + assign CTL_RX_RETRANS_RESET_MODE_in = CTL_RX_RETRANS_RESET_MODE_delay; + assign CTL_RX_RETRANS_RESET_in = CTL_RX_RETRANS_RESET_delay; + assign CTL_TX_DIAGWORD_INTFSTAT_in = CTL_TX_DIAGWORD_INTFSTAT_delay; + assign CTL_TX_DIAGWORD_LANESTAT_in = CTL_TX_DIAGWORD_LANESTAT_delay; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay; + assign CTL_TX_ERRINJ_BITERR_GO_in = CTL_TX_ERRINJ_BITERR_GO_delay; + assign CTL_TX_ERRINJ_BITERR_LANE_in = CTL_TX_ERRINJ_BITERR_LANE_delay; + assign CTL_TX_FC_STAT_in = CTL_TX_FC_STAT_delay; + assign CTL_TX_MUBITS_in = CTL_TX_MUBITS_delay; + assign CTL_TX_RETRANS_ENABLE_in = CTL_TX_RETRANS_ENABLE_delay; + assign CTL_TX_RETRANS_RAM_PERRIN_in = CTL_TX_RETRANS_RAM_PERRIN_delay; + assign CTL_TX_RETRANS_RAM_RDATA_in = CTL_TX_RETRANS_RAM_RDATA_delay; + assign CTL_TX_RETRANS_REQ_VALID_in = CTL_TX_RETRANS_REQ_VALID_delay; + assign CTL_TX_RETRANS_REQ_in = CTL_TX_RETRANS_REQ_delay; + assign CTL_TX_RLIM_DELTA_in = CTL_TX_RLIM_DELTA_delay; + assign CTL_TX_RLIM_ENABLE_in = CTL_TX_RLIM_ENABLE_delay; + assign CTL_TX_RLIM_INTV_in = CTL_TX_RLIM_INTV_delay; + assign CTL_TX_RLIM_MAX_in = CTL_TX_RLIM_MAX_delay; + assign DRP_ADDR_in = DRP_ADDR_delay; + assign DRP_CLK_in = DRP_CLK_delay; + assign DRP_DI_in = DRP_DI_delay; + assign DRP_EN_in = DRP_EN_delay; + assign DRP_WE_in = DRP_WE_delay; + assign LBUS_CLK_in = LBUS_CLK_delay; + assign RX_BYPASS_FORCE_REALIGNIN_in = RX_BYPASS_FORCE_REALIGNIN_delay; + assign RX_BYPASS_RDIN_in = RX_BYPASS_RDIN_delay; + assign RX_RESET_in = RX_RESET_delay; + assign RX_SERDES_CLK_in = RX_SERDES_CLK_delay; + assign RX_SERDES_DATA00_in = RX_SERDES_DATA00_delay; + assign RX_SERDES_DATA01_in = RX_SERDES_DATA01_delay; + assign RX_SERDES_DATA02_in = RX_SERDES_DATA02_delay; + assign RX_SERDES_DATA03_in = RX_SERDES_DATA03_delay; + assign RX_SERDES_DATA04_in = RX_SERDES_DATA04_delay; + assign RX_SERDES_DATA05_in = RX_SERDES_DATA05_delay; + assign RX_SERDES_DATA06_in = RX_SERDES_DATA06_delay; + assign RX_SERDES_DATA07_in = RX_SERDES_DATA07_delay; + assign RX_SERDES_DATA08_in = RX_SERDES_DATA08_delay; + assign RX_SERDES_DATA09_in = RX_SERDES_DATA09_delay; + assign RX_SERDES_DATA10_in = RX_SERDES_DATA10_delay; + assign RX_SERDES_DATA11_in = RX_SERDES_DATA11_delay; + assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay; + assign TX_BCTLIN0_in = TX_BCTLIN0_delay; + assign TX_BCTLIN1_in = TX_BCTLIN1_delay; + assign TX_BCTLIN2_in = TX_BCTLIN2_delay; + assign TX_BCTLIN3_in = TX_BCTLIN3_delay; + assign TX_BYPASS_CTRLIN_in = TX_BYPASS_CTRLIN_delay; + assign TX_BYPASS_DATAIN00_in = TX_BYPASS_DATAIN00_delay; + assign TX_BYPASS_DATAIN01_in = TX_BYPASS_DATAIN01_delay; + assign TX_BYPASS_DATAIN02_in = TX_BYPASS_DATAIN02_delay; + assign TX_BYPASS_DATAIN03_in = TX_BYPASS_DATAIN03_delay; + assign TX_BYPASS_DATAIN04_in = TX_BYPASS_DATAIN04_delay; + assign TX_BYPASS_DATAIN05_in = TX_BYPASS_DATAIN05_delay; + assign TX_BYPASS_DATAIN06_in = TX_BYPASS_DATAIN06_delay; + assign TX_BYPASS_DATAIN07_in = TX_BYPASS_DATAIN07_delay; + assign TX_BYPASS_DATAIN08_in = TX_BYPASS_DATAIN08_delay; + assign TX_BYPASS_DATAIN09_in = TX_BYPASS_DATAIN09_delay; + assign TX_BYPASS_DATAIN10_in = TX_BYPASS_DATAIN10_delay; + assign TX_BYPASS_DATAIN11_in = TX_BYPASS_DATAIN11_delay; + assign TX_BYPASS_ENAIN_in = TX_BYPASS_ENAIN_delay; + assign TX_BYPASS_GEARBOX_SEQIN_in = TX_BYPASS_GEARBOX_SEQIN_delay; + assign TX_BYPASS_MFRAMER_STATEIN_in = TX_BYPASS_MFRAMER_STATEIN_delay; + assign TX_CHANIN0_in = TX_CHANIN0_delay; + assign TX_CHANIN1_in = TX_CHANIN1_delay; + assign TX_CHANIN2_in = TX_CHANIN2_delay; + assign TX_CHANIN3_in = TX_CHANIN3_delay; + assign TX_DATAIN0_in = TX_DATAIN0_delay; + assign TX_DATAIN1_in = TX_DATAIN1_delay; + assign TX_DATAIN2_in = TX_DATAIN2_delay; + assign TX_DATAIN3_in = TX_DATAIN3_delay; + assign TX_ENAIN0_in = TX_ENAIN0_delay; + assign TX_ENAIN1_in = TX_ENAIN1_delay; + assign TX_ENAIN2_in = TX_ENAIN2_delay; + assign TX_ENAIN3_in = TX_ENAIN3_delay; + assign TX_EOPIN0_in = TX_EOPIN0_delay; + assign TX_EOPIN1_in = TX_EOPIN1_delay; + assign TX_EOPIN2_in = TX_EOPIN2_delay; + assign TX_EOPIN3_in = TX_EOPIN3_delay; + assign TX_ERRIN0_in = TX_ERRIN0_delay; + assign TX_ERRIN1_in = TX_ERRIN1_delay; + assign TX_ERRIN2_in = TX_ERRIN2_delay; + assign TX_ERRIN3_in = TX_ERRIN3_delay; + assign TX_MTYIN0_in = TX_MTYIN0_delay; + assign TX_MTYIN1_in = TX_MTYIN1_delay; + assign TX_MTYIN2_in = TX_MTYIN2_delay; + assign TX_MTYIN3_in = TX_MTYIN3_delay; + assign TX_RESET_in = TX_RESET_delay; + assign TX_SERDES_REFCLK_RESET_in = TX_SERDES_REFCLK_RESET_delay; + assign TX_SERDES_REFCLK_in = TX_SERDES_REFCLK_delay; + assign TX_SOPIN0_in = TX_SOPIN0_delay; + assign TX_SOPIN1_in = TX_SOPIN1_delay; + assign TX_SOPIN2_in = TX_SOPIN2_delay; + assign TX_SOPIN3_in = TX_SOPIN3_delay; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BYPASS_REG != "FALSE") && + (BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_LAST_LANE_REG < 4'h0) || (CTL_RX_LAST_LANE_REG > 4'hB))) begin + $display("Error: [Unisim %s-104] CTL_RX_LAST_LANE attribute is set to %h. Legal values for this attribute are 4'h0 to 4'hB. Instance: %m", MODULE_NAME, CTL_RX_LAST_LANE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_MFRAMELEN_MINUS1_REG < 16'h00FF) || (CTL_RX_MFRAMELEN_MINUS1_REG > 16'h1FFF))) begin + $display("Error: [Unisim %s-105] CTL_RX_MFRAMELEN_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h00FF to 16'h1FFF. Instance: %m", MODULE_NAME, CTL_RX_MFRAMELEN_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_PACKET_MODE_REG != "TRUE") && + (CTL_RX_PACKET_MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-106] CTL_RX_PACKET_MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_PACKET_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_RETRANS_MULT_REG < 3'h0) || (CTL_RX_RETRANS_MULT_REG > 3'h5))) begin + $display("Error: [Unisim %s-107] CTL_RX_RETRANS_MULT attribute is set to %h. Legal values for this attribute are 3'h0 to 3'h5. Instance: %m", MODULE_NAME, CTL_RX_RETRANS_MULT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_RETRANS_RETRY_REG < 4'h0) || (CTL_RX_RETRANS_RETRY_REG > 4'hF))) begin + $display("Error: [Unisim %s-108] CTL_RX_RETRANS_RETRY attribute is set to %h. Legal values for this attribute are 4'h0 to 4'hF. Instance: %m", MODULE_NAME, CTL_RX_RETRANS_RETRY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") && + (CTL_TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] CTL_TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_BURSTSHORT_REG < 3'h1) || (CTL_TX_BURSTSHORT_REG > 3'h7))) begin + $display("Error: [Unisim %s-115] CTL_TX_BURSTSHORT attribute is set to %h. Legal values for this attribute are 3'h1 to 3'h7. Instance: %m", MODULE_NAME, CTL_TX_BURSTSHORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_DISABLE_SKIPWORD_REG != "TRUE") && + (CTL_TX_DISABLE_SKIPWORD_REG != "FALSE"))) begin + $display("Error: [Unisim %s-117] CTL_TX_DISABLE_SKIPWORD attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_TX_DISABLE_SKIPWORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_FC_CALLEN_REG < 7'h00) || (CTL_TX_FC_CALLEN_REG > 7'h0F))) begin + $display("Error: [Unisim %s-118] CTL_TX_FC_CALLEN attribute is set to %h. Legal values for this attribute are 7'h00 to 7'h0F. Instance: %m", MODULE_NAME, CTL_TX_FC_CALLEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_LAST_LANE_REG < 4'h0) || (CTL_TX_LAST_LANE_REG > 4'hB))) begin + $display("Error: [Unisim %s-119] CTL_TX_LAST_LANE attribute is set to %h. Legal values for this attribute are 4'h0 to 4'hB. Instance: %m", MODULE_NAME, CTL_TX_LAST_LANE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_MFRAMELEN_MINUS1_REG < 16'h00FF) || (CTL_TX_MFRAMELEN_MINUS1_REG > 16'h1FFF))) begin + $display("Error: [Unisim %s-120] CTL_TX_MFRAMELEN_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h00FF to 16'h1FFF. Instance: %m", MODULE_NAME, CTL_TX_MFRAMELEN_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_RETRANS_DEPTH_REG < 14'h0015) || (CTL_TX_RETRANS_DEPTH_REG > 14'h0800))) begin + $display("Error: [Unisim %s-121] CTL_TX_RETRANS_DEPTH attribute is set to %h. Legal values for this attribute are 14'h0015 to 14'h0800. Instance: %m", MODULE_NAME, CTL_TX_RETRANS_DEPTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_RETRANS_MULT_REG < 3'h0) || (CTL_TX_RETRANS_MULT_REG > 3'h5))) begin + $display("Error: [Unisim %s-122] CTL_TX_RETRANS_MULT attribute is set to %h. Legal values for this attribute are 3'h0 to 3'h5. Instance: %m", MODULE_NAME, CTL_TX_RETRANS_MULT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MODE_REG != "TRUE") && + (MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-124] MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != "2.0") && + (SIM_VERSION_REG != "1.0"))) begin + $display("Error: [Unisim %s-125] SIM_VERSION attribute is set to %s. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TEST_MODE_PIN_CHAR_REG != "FALSE") && + (TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-126] TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign SCAN_EN_in = 1'b0; // tie off + assign SCAN_IN_DRPCTRL_in = 15'b111111111111111; // tie off + assign SCAN_IN_ILMAC_in = 250'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign TEST_MODE_in = 1'b0; // tie off + assign TEST_RESET_in = 1'b1; // tie off + +generate +if (SIM_VERSION == "2.0" ) begin : generate_block1 + + SIP_ILKN_ES2 SIP_ILKN_INST ( + .BYPASS (BYPASS_REG), + .CTL_RX_BURSTMAX (CTL_RX_BURSTMAX_REG), + .CTL_RX_CHAN_EXT (CTL_RX_CHAN_EXT_REG), + .CTL_RX_LAST_LANE (CTL_RX_LAST_LANE_REG), + .CTL_RX_MFRAMELEN_MINUS1 (CTL_RX_MFRAMELEN_MINUS1_REG), + .CTL_RX_PACKET_MODE (CTL_RX_PACKET_MODE_REG), + .CTL_RX_RETRANS_MULT (CTL_RX_RETRANS_MULT_REG), + .CTL_RX_RETRANS_RETRY (CTL_RX_RETRANS_RETRY_REG), + .CTL_RX_RETRANS_TIMER1 (CTL_RX_RETRANS_TIMER1_REG), + .CTL_RX_RETRANS_TIMER2 (CTL_RX_RETRANS_TIMER2_REG), + .CTL_RX_RETRANS_WDOG (CTL_RX_RETRANS_WDOG_REG), + .CTL_RX_RETRANS_WRAP_TIMER (CTL_RX_RETRANS_WRAP_TIMER_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_BURSTMAX (CTL_TX_BURSTMAX_REG), + .CTL_TX_BURSTSHORT (CTL_TX_BURSTSHORT_REG), + .CTL_TX_CHAN_EXT (CTL_TX_CHAN_EXT_REG), + .CTL_TX_DISABLE_SKIPWORD (CTL_TX_DISABLE_SKIPWORD_REG), + .CTL_TX_FC_CALLEN (CTL_TX_FC_CALLEN_REG), + .CTL_TX_LAST_LANE (CTL_TX_LAST_LANE_REG), + .CTL_TX_MFRAMELEN_MINUS1 (CTL_TX_MFRAMELEN_MINUS1_REG), + .CTL_TX_RETRANS_DEPTH (CTL_TX_RETRANS_DEPTH_REG), + .CTL_TX_RETRANS_MULT (CTL_TX_RETRANS_MULT_REG), + .CTL_TX_RETRANS_RAM_BANKS (CTL_TX_RETRANS_RAM_BANKS_REG), + .MODE (MODE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .RX_BYPASS_DATAOUT00 (RX_BYPASS_DATAOUT00_out), + .RX_BYPASS_DATAOUT01 (RX_BYPASS_DATAOUT01_out), + .RX_BYPASS_DATAOUT02 (RX_BYPASS_DATAOUT02_out), + .RX_BYPASS_DATAOUT03 (RX_BYPASS_DATAOUT03_out), + .RX_BYPASS_DATAOUT04 (RX_BYPASS_DATAOUT04_out), + .RX_BYPASS_DATAOUT05 (RX_BYPASS_DATAOUT05_out), + .RX_BYPASS_DATAOUT06 (RX_BYPASS_DATAOUT06_out), + .RX_BYPASS_DATAOUT07 (RX_BYPASS_DATAOUT07_out), + .RX_BYPASS_DATAOUT08 (RX_BYPASS_DATAOUT08_out), + .RX_BYPASS_DATAOUT09 (RX_BYPASS_DATAOUT09_out), + .RX_BYPASS_DATAOUT10 (RX_BYPASS_DATAOUT10_out), + .RX_BYPASS_DATAOUT11 (RX_BYPASS_DATAOUT11_out), + .RX_BYPASS_ENAOUT (RX_BYPASS_ENAOUT_out), + .RX_BYPASS_IS_AVAILOUT (RX_BYPASS_IS_AVAILOUT_out), + .RX_BYPASS_IS_BADLYFRAMEDOUT (RX_BYPASS_IS_BADLYFRAMEDOUT_out), + .RX_BYPASS_IS_OVERFLOWOUT (RX_BYPASS_IS_OVERFLOWOUT_out), + .RX_BYPASS_IS_SYNCEDOUT (RX_BYPASS_IS_SYNCEDOUT_out), + .RX_BYPASS_IS_SYNCWORDOUT (RX_BYPASS_IS_SYNCWORDOUT_out), + .RX_CHANOUT0 (RX_CHANOUT0_out), + .RX_CHANOUT1 (RX_CHANOUT1_out), + .RX_CHANOUT2 (RX_CHANOUT2_out), + .RX_CHANOUT3 (RX_CHANOUT3_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_OVFOUT (RX_OVFOUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT_DRPCTRL (SCAN_OUT_DRPCTRL_out), + .SCAN_OUT_ILMAC (SCAN_OUT_ILMAC_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_TYPE_ERR (STAT_RX_BAD_TYPE_ERR_out), + .STAT_RX_BURSTMAX_ERR (STAT_RX_BURSTMAX_ERR_out), + .STAT_RX_BURST_ERR (STAT_RX_BURST_ERR_out), + .STAT_RX_CRC24_ERR (STAT_RX_CRC24_ERR_out), + .STAT_RX_CRC32_ERR (STAT_RX_CRC32_ERR_out), + .STAT_RX_CRC32_VALID (STAT_RX_CRC32_VALID_out), + .STAT_RX_DESCRAM_ERR (STAT_RX_DESCRAM_ERR_out), + .STAT_RX_DIAGWORD_INTFSTAT (STAT_RX_DIAGWORD_INTFSTAT_out), + .STAT_RX_DIAGWORD_LANESTAT (STAT_RX_DIAGWORD_LANESTAT_out), + .STAT_RX_FC_STAT (STAT_RX_FC_STAT_out), + .STAT_RX_FRAMING_ERR (STAT_RX_FRAMING_ERR_out), + .STAT_RX_MEOP_ERR (STAT_RX_MEOP_ERR_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MSOP_ERR (STAT_RX_MSOP_ERR_out), + .STAT_RX_MUBITS (STAT_RX_MUBITS_out), + .STAT_RX_MUBITS_UPDATED (STAT_RX_MUBITS_UPDATED_out), + .STAT_RX_OVERFLOW_ERR (STAT_RX_OVERFLOW_ERR_out), + .STAT_RX_RETRANS_CRC24_ERR (STAT_RX_RETRANS_CRC24_ERR_out), + .STAT_RX_RETRANS_DISC (STAT_RX_RETRANS_DISC_out), + .STAT_RX_RETRANS_LATENCY (STAT_RX_RETRANS_LATENCY_out), + .STAT_RX_RETRANS_REQ (STAT_RX_RETRANS_REQ_out), + .STAT_RX_RETRANS_RETRY_ERR (STAT_RX_RETRANS_RETRY_ERR_out), + .STAT_RX_RETRANS_SEQ (STAT_RX_RETRANS_SEQ_out), + .STAT_RX_RETRANS_SEQ_UPDATED (STAT_RX_RETRANS_SEQ_UPDATED_out), + .STAT_RX_RETRANS_STATE (STAT_RX_RETRANS_STATE_out), + .STAT_RX_RETRANS_SUBSEQ (STAT_RX_RETRANS_SUBSEQ_out), + .STAT_RX_RETRANS_WDOG_ERR (STAT_RX_RETRANS_WDOG_ERR_out), + .STAT_RX_RETRANS_WRAP_ERR (STAT_RX_RETRANS_WRAP_ERR_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_WORD_SYNC (STAT_RX_WORD_SYNC_out), + .STAT_TX_BURST_ERR (STAT_TX_BURST_ERR_out), + .STAT_TX_ERRINJ_BITERR_DONE (STAT_TX_ERRINJ_BITERR_DONE_out), + .STAT_TX_OVERFLOW_ERR (STAT_TX_OVERFLOW_ERR_out), + .STAT_TX_RETRANS_BURST_ERR (STAT_TX_RETRANS_BURST_ERR_out), + .STAT_TX_RETRANS_BUSY (STAT_TX_RETRANS_BUSY_out), + .STAT_TX_RETRANS_RAM_PERROUT (STAT_TX_RETRANS_RAM_PERROUT_out), + .STAT_TX_RETRANS_RAM_RADDR (STAT_TX_RETRANS_RAM_RADDR_out), + .STAT_TX_RETRANS_RAM_RD_B0 (STAT_TX_RETRANS_RAM_RD_B0_out), + .STAT_TX_RETRANS_RAM_RD_B1 (STAT_TX_RETRANS_RAM_RD_B1_out), + .STAT_TX_RETRANS_RAM_RD_B2 (STAT_TX_RETRANS_RAM_RD_B2_out), + .STAT_TX_RETRANS_RAM_RD_B3 (STAT_TX_RETRANS_RAM_RD_B3_out), + .STAT_TX_RETRANS_RAM_RSEL (STAT_TX_RETRANS_RAM_RSEL_out), + .STAT_TX_RETRANS_RAM_WADDR (STAT_TX_RETRANS_RAM_WADDR_out), + .STAT_TX_RETRANS_RAM_WDATA (STAT_TX_RETRANS_RAM_WDATA_out), + .STAT_TX_RETRANS_RAM_WE_B0 (STAT_TX_RETRANS_RAM_WE_B0_out), + .STAT_TX_RETRANS_RAM_WE_B1 (STAT_TX_RETRANS_RAM_WE_B1_out), + .STAT_TX_RETRANS_RAM_WE_B2 (STAT_TX_RETRANS_RAM_WE_B2_out), + .STAT_TX_RETRANS_RAM_WE_B3 (STAT_TX_RETRANS_RAM_WE_B3_out), + .STAT_TX_UNDERFLOW_ERR (STAT_TX_UNDERFLOW_ERR_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_DATA00 (TX_SERDES_DATA00_out), + .TX_SERDES_DATA01 (TX_SERDES_DATA01_out), + .TX_SERDES_DATA02 (TX_SERDES_DATA02_out), + .TX_SERDES_DATA03 (TX_SERDES_DATA03_out), + .TX_SERDES_DATA04 (TX_SERDES_DATA04_out), + .TX_SERDES_DATA05 (TX_SERDES_DATA05_out), + .TX_SERDES_DATA06 (TX_SERDES_DATA06_out), + .TX_SERDES_DATA07 (TX_SERDES_DATA07_out), + .TX_SERDES_DATA08 (TX_SERDES_DATA08_out), + .TX_SERDES_DATA09 (TX_SERDES_DATA09_out), + .TX_SERDES_DATA10 (TX_SERDES_DATA10_out), + .TX_SERDES_DATA11 (TX_SERDES_DATA11_out), + .CORE_CLK (CORE_CLK_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_RETRANS_ACK (CTL_RX_RETRANS_ACK_in), + .CTL_RX_RETRANS_ENABLE (CTL_RX_RETRANS_ENABLE_in), + .CTL_RX_RETRANS_ERRIN (CTL_RX_RETRANS_ERRIN_in), + .CTL_RX_RETRANS_FORCE_REQ (CTL_RX_RETRANS_FORCE_REQ_in), + .CTL_RX_RETRANS_RESET (CTL_RX_RETRANS_RESET_in), + .CTL_RX_RETRANS_RESET_MODE (CTL_RX_RETRANS_RESET_MODE_in), + .CTL_TX_DIAGWORD_INTFSTAT (CTL_TX_DIAGWORD_INTFSTAT_in), + .CTL_TX_DIAGWORD_LANESTAT (CTL_TX_DIAGWORD_LANESTAT_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_ERRINJ_BITERR_GO (CTL_TX_ERRINJ_BITERR_GO_in), + .CTL_TX_ERRINJ_BITERR_LANE (CTL_TX_ERRINJ_BITERR_LANE_in), + .CTL_TX_FC_STAT (CTL_TX_FC_STAT_in), + .CTL_TX_MUBITS (CTL_TX_MUBITS_in), + .CTL_TX_RETRANS_ENABLE (CTL_TX_RETRANS_ENABLE_in), + .CTL_TX_RETRANS_RAM_PERRIN (CTL_TX_RETRANS_RAM_PERRIN_in), + .CTL_TX_RETRANS_RAM_RDATA (CTL_TX_RETRANS_RAM_RDATA_in), + .CTL_TX_RETRANS_REQ (CTL_TX_RETRANS_REQ_in), + .CTL_TX_RETRANS_REQ_VALID (CTL_TX_RETRANS_REQ_VALID_in), + .CTL_TX_RLIM_DELTA (CTL_TX_RLIM_DELTA_in), + .CTL_TX_RLIM_ENABLE (CTL_TX_RLIM_ENABLE_in), + .CTL_TX_RLIM_INTV (CTL_TX_RLIM_INTV_in), + .CTL_TX_RLIM_MAX (CTL_TX_RLIM_MAX_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .LBUS_CLK (LBUS_CLK_in), + .RX_BYPASS_FORCE_REALIGNIN (RX_BYPASS_FORCE_REALIGNIN_in), + .RX_BYPASS_RDIN (RX_BYPASS_RDIN_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA00 (RX_SERDES_DATA00_in), + .RX_SERDES_DATA01 (RX_SERDES_DATA01_in), + .RX_SERDES_DATA02 (RX_SERDES_DATA02_in), + .RX_SERDES_DATA03 (RX_SERDES_DATA03_in), + .RX_SERDES_DATA04 (RX_SERDES_DATA04_in), + .RX_SERDES_DATA05 (RX_SERDES_DATA05_in), + .RX_SERDES_DATA06 (RX_SERDES_DATA06_in), + .RX_SERDES_DATA07 (RX_SERDES_DATA07_in), + .RX_SERDES_DATA08 (RX_SERDES_DATA08_in), + .RX_SERDES_DATA09 (RX_SERDES_DATA09_in), + .RX_SERDES_DATA10 (RX_SERDES_DATA10_in), + .RX_SERDES_DATA11 (RX_SERDES_DATA11_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_EN (SCAN_EN_in), + .SCAN_IN_DRPCTRL (SCAN_IN_DRPCTRL_in), + .SCAN_IN_ILMAC (SCAN_IN_ILMAC_in), + .TEST_MODE (TEST_MODE_in), + .TEST_RESET (TEST_RESET_in), + .TX_BCTLIN0 (TX_BCTLIN0_in), + .TX_BCTLIN1 (TX_BCTLIN1_in), + .TX_BCTLIN2 (TX_BCTLIN2_in), + .TX_BCTLIN3 (TX_BCTLIN3_in), + .TX_BYPASS_CTRLIN (TX_BYPASS_CTRLIN_in), + .TX_BYPASS_DATAIN00 (TX_BYPASS_DATAIN00_in), + .TX_BYPASS_DATAIN01 (TX_BYPASS_DATAIN01_in), + .TX_BYPASS_DATAIN02 (TX_BYPASS_DATAIN02_in), + .TX_BYPASS_DATAIN03 (TX_BYPASS_DATAIN03_in), + .TX_BYPASS_DATAIN04 (TX_BYPASS_DATAIN04_in), + .TX_BYPASS_DATAIN05 (TX_BYPASS_DATAIN05_in), + .TX_BYPASS_DATAIN06 (TX_BYPASS_DATAIN06_in), + .TX_BYPASS_DATAIN07 (TX_BYPASS_DATAIN07_in), + .TX_BYPASS_DATAIN08 (TX_BYPASS_DATAIN08_in), + .TX_BYPASS_DATAIN09 (TX_BYPASS_DATAIN09_in), + .TX_BYPASS_DATAIN10 (TX_BYPASS_DATAIN10_in), + .TX_BYPASS_DATAIN11 (TX_BYPASS_DATAIN11_in), + .TX_BYPASS_ENAIN (TX_BYPASS_ENAIN_in), + .TX_BYPASS_GEARBOX_SEQIN (TX_BYPASS_GEARBOX_SEQIN_in), + .TX_BYPASS_MFRAMER_STATEIN (TX_BYPASS_MFRAMER_STATEIN_in), + .TX_CHANIN0 (TX_CHANIN0_in), + .TX_CHANIN1 (TX_CHANIN1_in), + .TX_CHANIN2 (TX_CHANIN2_in), + .TX_CHANIN3 (TX_CHANIN3_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_RESET (TX_RESET_in), + .TX_SERDES_REFCLK (TX_SERDES_REFCLK_in), + .TX_SERDES_REFCLK_RESET (TX_SERDES_REFCLK_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); +end else begin : generate_block1 + + SIP_ILKN SIP_ILKN_INST ( + .BYPASS (BYPASS_REG), + .CTL_RX_BURSTMAX (CTL_RX_BURSTMAX_REG), + .CTL_RX_CHAN_EXT (CTL_RX_CHAN_EXT_REG), + .CTL_RX_LAST_LANE (CTL_RX_LAST_LANE_REG), + .CTL_RX_MFRAMELEN_MINUS1 (CTL_RX_MFRAMELEN_MINUS1_REG), + .CTL_RX_PACKET_MODE (CTL_RX_PACKET_MODE_REG), + .CTL_RX_RETRANS_MULT (CTL_RX_RETRANS_MULT_REG), + .CTL_RX_RETRANS_RETRY (CTL_RX_RETRANS_RETRY_REG), + .CTL_RX_RETRANS_TIMER1 (CTL_RX_RETRANS_TIMER1_REG), + .CTL_RX_RETRANS_TIMER2 (CTL_RX_RETRANS_TIMER2_REG), + .CTL_RX_RETRANS_WDOG (CTL_RX_RETRANS_WDOG_REG), + .CTL_RX_RETRANS_WRAP_TIMER (CTL_RX_RETRANS_WRAP_TIMER_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_BURSTMAX (CTL_TX_BURSTMAX_REG), + .CTL_TX_BURSTSHORT (CTL_TX_BURSTSHORT_REG), + .CTL_TX_CHAN_EXT (CTL_TX_CHAN_EXT_REG), + .CTL_TX_DISABLE_SKIPWORD (CTL_TX_DISABLE_SKIPWORD_REG), + .CTL_TX_FC_CALLEN (CTL_TX_FC_CALLEN_REG), + .CTL_TX_LAST_LANE (CTL_TX_LAST_LANE_REG), + .CTL_TX_MFRAMELEN_MINUS1 (CTL_TX_MFRAMELEN_MINUS1_REG), + .CTL_TX_RETRANS_DEPTH (CTL_TX_RETRANS_DEPTH_REG), + .CTL_TX_RETRANS_MULT (CTL_TX_RETRANS_MULT_REG), + .CTL_TX_RETRANS_RAM_BANKS (CTL_TX_RETRANS_RAM_BANKS_REG), + .MODE (MODE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .RX_BYPASS_DATAOUT00 (RX_BYPASS_DATAOUT00_out), + .RX_BYPASS_DATAOUT01 (RX_BYPASS_DATAOUT01_out), + .RX_BYPASS_DATAOUT02 (RX_BYPASS_DATAOUT02_out), + .RX_BYPASS_DATAOUT03 (RX_BYPASS_DATAOUT03_out), + .RX_BYPASS_DATAOUT04 (RX_BYPASS_DATAOUT04_out), + .RX_BYPASS_DATAOUT05 (RX_BYPASS_DATAOUT05_out), + .RX_BYPASS_DATAOUT06 (RX_BYPASS_DATAOUT06_out), + .RX_BYPASS_DATAOUT07 (RX_BYPASS_DATAOUT07_out), + .RX_BYPASS_DATAOUT08 (RX_BYPASS_DATAOUT08_out), + .RX_BYPASS_DATAOUT09 (RX_BYPASS_DATAOUT09_out), + .RX_BYPASS_DATAOUT10 (RX_BYPASS_DATAOUT10_out), + .RX_BYPASS_DATAOUT11 (RX_BYPASS_DATAOUT11_out), + .RX_BYPASS_ENAOUT (RX_BYPASS_ENAOUT_out), + .RX_BYPASS_IS_AVAILOUT (RX_BYPASS_IS_AVAILOUT_out), + .RX_BYPASS_IS_BADLYFRAMEDOUT (RX_BYPASS_IS_BADLYFRAMEDOUT_out), + .RX_BYPASS_IS_OVERFLOWOUT (RX_BYPASS_IS_OVERFLOWOUT_out), + .RX_BYPASS_IS_SYNCEDOUT (RX_BYPASS_IS_SYNCEDOUT_out), + .RX_BYPASS_IS_SYNCWORDOUT (RX_BYPASS_IS_SYNCWORDOUT_out), + .RX_CHANOUT0 (RX_CHANOUT0_out), + .RX_CHANOUT1 (RX_CHANOUT1_out), + .RX_CHANOUT2 (RX_CHANOUT2_out), + .RX_CHANOUT3 (RX_CHANOUT3_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_OVFOUT (RX_OVFOUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT_DRPCTRL (SCAN_OUT_DRPCTRL_out), + .SCAN_OUT_ILMAC (SCAN_OUT_ILMAC_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_TYPE_ERR (STAT_RX_BAD_TYPE_ERR_out), + .STAT_RX_BURSTMAX_ERR (STAT_RX_BURSTMAX_ERR_out), + .STAT_RX_BURST_ERR (STAT_RX_BURST_ERR_out), + .STAT_RX_CRC24_ERR (STAT_RX_CRC24_ERR_out), + .STAT_RX_CRC32_ERR (STAT_RX_CRC32_ERR_out), + .STAT_RX_CRC32_VALID (STAT_RX_CRC32_VALID_out), + .STAT_RX_DESCRAM_ERR (STAT_RX_DESCRAM_ERR_out), + .STAT_RX_DIAGWORD_INTFSTAT (STAT_RX_DIAGWORD_INTFSTAT_out), + .STAT_RX_DIAGWORD_LANESTAT (STAT_RX_DIAGWORD_LANESTAT_out), + .STAT_RX_FC_STAT (STAT_RX_FC_STAT_out), + .STAT_RX_FRAMING_ERR (STAT_RX_FRAMING_ERR_out), + .STAT_RX_MEOP_ERR (STAT_RX_MEOP_ERR_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MSOP_ERR (STAT_RX_MSOP_ERR_out), + .STAT_RX_MUBITS (STAT_RX_MUBITS_out), + .STAT_RX_MUBITS_UPDATED (STAT_RX_MUBITS_UPDATED_out), + .STAT_RX_OVERFLOW_ERR (STAT_RX_OVERFLOW_ERR_out), + .STAT_RX_RETRANS_CRC24_ERR (STAT_RX_RETRANS_CRC24_ERR_out), + .STAT_RX_RETRANS_DISC (STAT_RX_RETRANS_DISC_out), + .STAT_RX_RETRANS_LATENCY (STAT_RX_RETRANS_LATENCY_out), + .STAT_RX_RETRANS_REQ (STAT_RX_RETRANS_REQ_out), + .STAT_RX_RETRANS_RETRY_ERR (STAT_RX_RETRANS_RETRY_ERR_out), + .STAT_RX_RETRANS_SEQ (STAT_RX_RETRANS_SEQ_out), + .STAT_RX_RETRANS_SEQ_UPDATED (STAT_RX_RETRANS_SEQ_UPDATED_out), + .STAT_RX_RETRANS_STATE (STAT_RX_RETRANS_STATE_out), + .STAT_RX_RETRANS_SUBSEQ (STAT_RX_RETRANS_SUBSEQ_out), + .STAT_RX_RETRANS_WDOG_ERR (STAT_RX_RETRANS_WDOG_ERR_out), + .STAT_RX_RETRANS_WRAP_ERR (STAT_RX_RETRANS_WRAP_ERR_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_WORD_SYNC (STAT_RX_WORD_SYNC_out), + .STAT_TX_BURST_ERR (STAT_TX_BURST_ERR_out), + .STAT_TX_ERRINJ_BITERR_DONE (STAT_TX_ERRINJ_BITERR_DONE_out), + .STAT_TX_OVERFLOW_ERR (STAT_TX_OVERFLOW_ERR_out), + .STAT_TX_RETRANS_BURST_ERR (STAT_TX_RETRANS_BURST_ERR_out), + .STAT_TX_RETRANS_BUSY (STAT_TX_RETRANS_BUSY_out), + .STAT_TX_RETRANS_RAM_PERROUT (STAT_TX_RETRANS_RAM_PERROUT_out), + .STAT_TX_RETRANS_RAM_RADDR (STAT_TX_RETRANS_RAM_RADDR_out), + .STAT_TX_RETRANS_RAM_RD_B0 (STAT_TX_RETRANS_RAM_RD_B0_out), + .STAT_TX_RETRANS_RAM_RD_B1 (STAT_TX_RETRANS_RAM_RD_B1_out), + .STAT_TX_RETRANS_RAM_RD_B2 (STAT_TX_RETRANS_RAM_RD_B2_out), + .STAT_TX_RETRANS_RAM_RD_B3 (STAT_TX_RETRANS_RAM_RD_B3_out), + .STAT_TX_RETRANS_RAM_RSEL (STAT_TX_RETRANS_RAM_RSEL_out), + .STAT_TX_RETRANS_RAM_WADDR (STAT_TX_RETRANS_RAM_WADDR_out), + .STAT_TX_RETRANS_RAM_WDATA (STAT_TX_RETRANS_RAM_WDATA_out), + .STAT_TX_RETRANS_RAM_WE_B0 (STAT_TX_RETRANS_RAM_WE_B0_out), + .STAT_TX_RETRANS_RAM_WE_B1 (STAT_TX_RETRANS_RAM_WE_B1_out), + .STAT_TX_RETRANS_RAM_WE_B2 (STAT_TX_RETRANS_RAM_WE_B2_out), + .STAT_TX_RETRANS_RAM_WE_B3 (STAT_TX_RETRANS_RAM_WE_B3_out), + .STAT_TX_UNDERFLOW_ERR (STAT_TX_UNDERFLOW_ERR_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_DATA00 (TX_SERDES_DATA00_out), + .TX_SERDES_DATA01 (TX_SERDES_DATA01_out), + .TX_SERDES_DATA02 (TX_SERDES_DATA02_out), + .TX_SERDES_DATA03 (TX_SERDES_DATA03_out), + .TX_SERDES_DATA04 (TX_SERDES_DATA04_out), + .TX_SERDES_DATA05 (TX_SERDES_DATA05_out), + .TX_SERDES_DATA06 (TX_SERDES_DATA06_out), + .TX_SERDES_DATA07 (TX_SERDES_DATA07_out), + .TX_SERDES_DATA08 (TX_SERDES_DATA08_out), + .TX_SERDES_DATA09 (TX_SERDES_DATA09_out), + .TX_SERDES_DATA10 (TX_SERDES_DATA10_out), + .TX_SERDES_DATA11 (TX_SERDES_DATA11_out), + .CORE_CLK (CORE_CLK_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_RETRANS_ACK (CTL_RX_RETRANS_ACK_in), + .CTL_RX_RETRANS_ENABLE (CTL_RX_RETRANS_ENABLE_in), + .CTL_RX_RETRANS_ERRIN (CTL_RX_RETRANS_ERRIN_in), + .CTL_RX_RETRANS_FORCE_REQ (CTL_RX_RETRANS_FORCE_REQ_in), + .CTL_RX_RETRANS_RESET (CTL_RX_RETRANS_RESET_in), + .CTL_RX_RETRANS_RESET_MODE (CTL_RX_RETRANS_RESET_MODE_in), + .CTL_TX_DIAGWORD_INTFSTAT (CTL_TX_DIAGWORD_INTFSTAT_in), + .CTL_TX_DIAGWORD_LANESTAT (CTL_TX_DIAGWORD_LANESTAT_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_ERRINJ_BITERR_GO (CTL_TX_ERRINJ_BITERR_GO_in), + .CTL_TX_ERRINJ_BITERR_LANE (CTL_TX_ERRINJ_BITERR_LANE_in), + .CTL_TX_FC_STAT (CTL_TX_FC_STAT_in), + .CTL_TX_MUBITS (CTL_TX_MUBITS_in), + .CTL_TX_RETRANS_ENABLE (CTL_TX_RETRANS_ENABLE_in), + .CTL_TX_RETRANS_RAM_PERRIN (CTL_TX_RETRANS_RAM_PERRIN_in), + .CTL_TX_RETRANS_RAM_RDATA (CTL_TX_RETRANS_RAM_RDATA_in), + .CTL_TX_RETRANS_REQ (CTL_TX_RETRANS_REQ_in), + .CTL_TX_RETRANS_REQ_VALID (CTL_TX_RETRANS_REQ_VALID_in), + .CTL_TX_RLIM_DELTA (CTL_TX_RLIM_DELTA_in), + .CTL_TX_RLIM_ENABLE (CTL_TX_RLIM_ENABLE_in), + .CTL_TX_RLIM_INTV (CTL_TX_RLIM_INTV_in), + .CTL_TX_RLIM_MAX (CTL_TX_RLIM_MAX_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .LBUS_CLK (LBUS_CLK_in), + .RX_BYPASS_FORCE_REALIGNIN (RX_BYPASS_FORCE_REALIGNIN_in), + .RX_BYPASS_RDIN (RX_BYPASS_RDIN_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA00 (RX_SERDES_DATA00_in), + .RX_SERDES_DATA01 (RX_SERDES_DATA01_in), + .RX_SERDES_DATA02 (RX_SERDES_DATA02_in), + .RX_SERDES_DATA03 (RX_SERDES_DATA03_in), + .RX_SERDES_DATA04 (RX_SERDES_DATA04_in), + .RX_SERDES_DATA05 (RX_SERDES_DATA05_in), + .RX_SERDES_DATA06 (RX_SERDES_DATA06_in), + .RX_SERDES_DATA07 (RX_SERDES_DATA07_in), + .RX_SERDES_DATA08 (RX_SERDES_DATA08_in), + .RX_SERDES_DATA09 (RX_SERDES_DATA09_in), + .RX_SERDES_DATA10 (RX_SERDES_DATA10_in), + .RX_SERDES_DATA11 (RX_SERDES_DATA11_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_EN (SCAN_EN_in), + .SCAN_IN_DRPCTRL (SCAN_IN_DRPCTRL_in), + .SCAN_IN_ILMAC (SCAN_IN_ILMAC_in), + .TEST_MODE (TEST_MODE_in), + .TEST_RESET (TEST_RESET_in), + .TX_BCTLIN0 (TX_BCTLIN0_in), + .TX_BCTLIN1 (TX_BCTLIN1_in), + .TX_BCTLIN2 (TX_BCTLIN2_in), + .TX_BCTLIN3 (TX_BCTLIN3_in), + .TX_BYPASS_CTRLIN (TX_BYPASS_CTRLIN_in), + .TX_BYPASS_DATAIN00 (TX_BYPASS_DATAIN00_in), + .TX_BYPASS_DATAIN01 (TX_BYPASS_DATAIN01_in), + .TX_BYPASS_DATAIN02 (TX_BYPASS_DATAIN02_in), + .TX_BYPASS_DATAIN03 (TX_BYPASS_DATAIN03_in), + .TX_BYPASS_DATAIN04 (TX_BYPASS_DATAIN04_in), + .TX_BYPASS_DATAIN05 (TX_BYPASS_DATAIN05_in), + .TX_BYPASS_DATAIN06 (TX_BYPASS_DATAIN06_in), + .TX_BYPASS_DATAIN07 (TX_BYPASS_DATAIN07_in), + .TX_BYPASS_DATAIN08 (TX_BYPASS_DATAIN08_in), + .TX_BYPASS_DATAIN09 (TX_BYPASS_DATAIN09_in), + .TX_BYPASS_DATAIN10 (TX_BYPASS_DATAIN10_in), + .TX_BYPASS_DATAIN11 (TX_BYPASS_DATAIN11_in), + .TX_BYPASS_ENAIN (TX_BYPASS_ENAIN_in), + .TX_BYPASS_GEARBOX_SEQIN (TX_BYPASS_GEARBOX_SEQIN_in), + .TX_BYPASS_MFRAMER_STATEIN (TX_BYPASS_MFRAMER_STATEIN_in), + .TX_CHANIN0 (TX_CHANIN0_in), + .TX_CHANIN1 (TX_CHANIN1_in), + .TX_CHANIN2 (TX_CHANIN2_in), + .TX_CHANIN3 (TX_CHANIN3_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_RESET (TX_RESET_in), + .TX_SERDES_REFCLK (TX_SERDES_REFCLK_in), + .TX_SERDES_REFCLK_RESET (TX_SERDES_REFCLK_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); + end + endgenerate + + specify + (CORE_CLK => RX_BYPASS_DATAOUT00[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[5]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[6]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[7]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS_UPDATED) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_CRC24_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_DISC) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[10]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[11]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[12]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[13]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[14]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[15]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[5]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[6]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[7]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[8]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_LATENCY[9]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_REQ) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_RETRY_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[5]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[6]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[7]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ_UPDATED) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_WDOG_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_WRAP_ERR) = (100:100:100, 100:100:100); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[0]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[1]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[2]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[3]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[4]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[5]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[6]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS[7]) = (0:0:0, 0:0:0); + (CTL_RX_RETRANS_ENABLE => STAT_RX_MUBITS_UPDATED) = (0:0:0, 0:0:0); + (CTL_TX_RETRANS_ENABLE => TX_OVFOUT) = (0:0:0, 0:0:0); + (CTL_TX_RETRANS_ENABLE => TX_RDYOUT) = (0:0:0, 0:0:0); + (DRP_CLK => DRP_DO[0]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[10]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[11]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[12]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[13]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[14]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[15]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[1]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[2]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[3]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[4]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[5]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[6]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[7]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[8]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[9]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_RDY) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_OVFOUT) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_ALIGNED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_ALIGNED_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BURSTMAX_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC24_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[128]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[129]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[130]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[131]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[132]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[133]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[134]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[135]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[136]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[137]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[138]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[139]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[140]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[141]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[142]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[143]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[144]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[145]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[146]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[147]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[148]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[149]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[150]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[151]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[152]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[153]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[154]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[155]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[156]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[157]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[158]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[159]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[160]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[161]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[162]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[163]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[164]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[165]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[166]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[167]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[168]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[169]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[170]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[171]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[172]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[173]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[174]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[175]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[176]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[177]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[178]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[179]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[180]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[181]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[182]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[183]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[184]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[185]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[186]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[187]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[188]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[189]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[190]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[191]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[192]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[193]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[194]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[195]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[196]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[197]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[198]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[199]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[200]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[201]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[202]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[203]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[204]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[205]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[206]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[207]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[208]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[209]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[210]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[211]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[212]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[213]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[214]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[215]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[216]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[217]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[218]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[219]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[220]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[221]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[222]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[223]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[224]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[225]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[226]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[227]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[228]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[229]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[230]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[231]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[232]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[233]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[234]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[235]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[236]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[237]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[238]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[239]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[240]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[241]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[242]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[243]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[244]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[245]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[246]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[247]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[248]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[249]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[250]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[251]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[252]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[253]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[254]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[255]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MEOP_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MISALIGNED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MSOP_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS_UPDATED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_OVERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_REQ) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_ERRINJ_BITERR_DONE) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_OVERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_BUSY) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_PERROUT) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B0) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B1) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B2) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RSEL[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RSEL[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[128]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[129]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[130]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[131]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[132]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[133]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[134]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[135]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[136]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[137]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[138]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[139]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[140]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[141]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[142]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[143]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[144]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[145]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[146]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[147]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[148]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[149]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[150]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[151]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[152]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[153]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[154]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[155]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[156]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[157]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[158]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[159]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[160]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[161]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[162]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[163]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[164]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[165]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[166]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[167]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[168]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[169]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[170]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[171]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[172]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[173]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[174]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[175]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[176]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[177]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[178]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[179]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[180]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[181]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[182]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[183]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[184]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[185]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[186]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[187]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[188]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[189]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[190]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[191]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[192]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[193]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[194]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[195]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[196]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[197]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[198]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[199]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[200]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[201]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[202]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[203]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[204]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[205]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[206]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[207]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[208]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[209]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[210]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[211]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[212]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[213]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[214]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[215]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[216]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[217]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[218]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[219]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[220]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[221]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[222]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[223]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[224]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[225]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[226]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[227]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[228]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[229]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[230]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[231]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[232]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[233]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[234]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[235]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[236]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[237]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[238]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[239]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[240]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[241]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[242]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[243]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[244]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[245]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[246]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[247]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[248]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[249]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[250]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[251]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[252]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[253]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[254]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[255]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[256]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[257]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[258]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[259]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[260]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[261]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[262]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[263]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[264]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[265]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[266]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[267]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[268]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[269]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[270]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[271]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[272]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[273]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[274]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[275]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[276]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[277]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[278]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[279]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[280]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[281]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[282]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[283]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[284]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[285]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[286]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[287]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[288]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[289]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[290]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[291]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[292]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[293]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[294]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[295]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[296]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[297]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[298]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[299]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[300]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[301]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[302]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[303]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[304]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[305]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[306]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[307]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[308]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[309]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[310]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[311]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[312]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[313]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[314]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[315]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[316]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[317]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[318]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[319]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[320]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[321]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[322]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[323]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[324]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[325]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[326]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[327]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[328]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[329]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[330]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[331]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[332]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[333]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[334]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[335]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[336]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[337]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[338]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[339]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[340]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[341]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[342]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[343]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[344]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[345]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[346]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[347]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[348]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[349]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[350]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[351]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[352]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[353]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[354]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[355]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[356]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[357]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[358]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[359]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[360]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[361]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[362]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[363]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[364]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[365]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[366]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[367]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[368]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[369]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[370]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[371]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[372]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[373]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[374]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[375]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[376]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[377]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[378]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[379]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[380]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[381]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[382]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[383]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[384]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[385]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[386]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[387]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[388]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[389]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[390]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[391]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[392]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[393]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[394]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[395]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[396]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[397]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[398]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[399]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[400]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[401]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[402]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[403]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[404]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[405]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[406]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[407]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[408]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[409]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[410]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[411]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[412]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[413]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[414]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[415]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[416]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[417]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[418]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[419]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[420]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[421]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[422]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[423]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[424]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[425]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[426]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[427]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[428]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[429]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[430]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[431]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[432]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[433]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[434]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[435]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[436]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[437]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[438]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[439]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[440]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[441]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[442]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[443]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[444]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[445]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[446]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[447]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[448]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[449]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[450]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[451]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[452]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[453]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[454]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[455]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[456]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[457]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[458]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[459]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[460]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[461]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[462]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[463]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[464]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[465]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[466]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[467]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[468]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[469]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[470]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[471]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[472]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[473]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[474]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[475]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[476]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[477]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[478]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[479]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[480]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[481]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[482]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[483]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[484]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[485]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[486]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[487]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[488]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[489]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[490]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[491]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[492]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[493]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[494]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[495]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[496]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[497]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[498]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[499]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[500]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[501]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[502]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[503]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[504]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[505]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[506]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[507]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[508]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[509]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[510]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[511]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[512]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[513]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[514]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[515]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[516]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[517]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[518]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[519]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[520]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[521]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[522]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[523]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[524]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[525]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[526]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[527]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[528]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[529]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[530]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[531]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[532]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[533]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[534]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[535]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[536]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[537]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[538]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[539]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[540]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[541]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[542]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[543]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[544]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[545]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[546]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[547]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[548]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[549]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[550]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[551]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[552]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[553]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[554]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[555]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[556]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[557]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[558]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[559]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[560]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[561]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[562]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[563]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[564]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[565]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[566]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[567]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[568]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[569]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[570]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[571]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[572]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[573]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[574]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[575]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[576]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[577]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[578]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[579]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[580]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[581]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[582]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[583]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[584]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[585]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[586]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[587]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[588]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[589]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[590]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[591]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[592]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[593]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[594]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[595]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[596]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[597]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[598]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[599]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[600]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[601]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[602]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[603]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[604]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[605]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[606]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[607]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[608]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[609]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[610]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[611]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[612]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[613]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[614]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[615]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[616]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[617]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[618]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[619]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[620]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[621]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[622]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[623]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[624]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[625]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[626]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[627]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[628]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[629]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[630]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[631]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[632]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[633]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[634]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[635]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[636]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[637]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[638]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[639]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[640]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[641]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[642]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[643]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B0) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B1) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B2) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_UNDERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => TX_OVFOUT) = (100:100:100, 100:100:100); + (LBUS_CLK => TX_RDYOUT) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[9]) = (100:100:100, 100:100:100); + `ifdef XIL_TIMING + $period (negedge CORE_CLK, 0:0:0, notifier); + $period (negedge DRP_CLK, 0:0:0, notifier); + $period (negedge LBUS_CLK, 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[10], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[11], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (negedge TX_SERDES_REFCLK, 0:0:0, notifier); + $period (posedge CORE_CLK, 0:0:0, notifier); + $period (posedge DRP_CLK, 0:0:0, notifier); + $period (posedge LBUS_CLK, 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[10], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[11], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (posedge TX_SERDES_REFCLK, 0:0:0, notifier); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[10]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[11]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_RESET, posedge CORE_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, CORE_CLK_delay); + $recrem (negedge RX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, LBUS_CLK_delay); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[10], posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[10], RX_SERDES_CLK_delay[10]); + $recrem (negedge RX_SERDES_RESET[11], posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[11], RX_SERDES_CLK_delay[11]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (negedge TX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, LBUS_CLK_delay); + $recrem (negedge TX_SERDES_REFCLK_RESET, posedge TX_SERDES_REFCLK, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_RESET_delay, TX_SERDES_REFCLK_delay); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[10]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[11]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_RESET, posedge CORE_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, CORE_CLK_delay); + $recrem (posedge RX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, LBUS_CLK_delay); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[10], posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[10], RX_SERDES_CLK_delay[10]); + $recrem (posedge RX_SERDES_RESET[11], posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[11], RX_SERDES_CLK_delay[11]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (posedge TX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, LBUS_CLK_delay); + $recrem (posedge TX_SERDES_REFCLK_RESET, posedge TX_SERDES_REFCLK, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_RESET_delay, TX_SERDES_REFCLK_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_ERRIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ERRIN_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_RESET, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_RESET_MODE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_MODE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[0]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[1]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[2]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[3]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[0]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[100], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[100]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[101], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[101]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[102], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[102]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[103], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[103]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[104], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[104]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[105], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[105]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[106], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[106]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[107], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[107]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[108], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[108]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[109], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[109]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[10], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[10]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[110], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[110]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[111], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[111]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[112], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[112]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[113], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[113]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[114], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[114]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[115], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[115]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[116], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[116]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[117], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[117]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[118], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[118]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[119], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[119]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[11], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[11]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[120], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[120]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[121], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[121]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[122], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[122]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[123], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[123]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[124], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[124]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[125], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[125]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[126], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[126]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[127], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[127]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[128], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[128]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[129], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[129]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[12], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[12]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[130], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[130]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[131], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[131]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[132], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[132]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[133], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[133]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[134], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[134]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[135], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[135]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[136], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[136]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[137], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[137]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[138], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[138]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[139], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[139]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[13], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[13]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[140], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[140]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[141], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[141]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[142], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[142]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[143], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[143]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[144], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[144]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[145], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[145]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[146], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[146]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[147], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[147]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[148], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[148]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[149], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[149]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[14], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[14]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[150], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[150]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[151], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[151]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[152], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[152]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[153], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[153]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[154], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[154]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[155], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[155]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[156], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[156]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[157], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[157]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[158], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[158]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[159], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[159]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[15], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[15]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[160], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[160]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[161], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[161]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[162], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[162]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[163], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[163]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[164], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[164]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[165], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[165]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[166], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[166]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[167], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[167]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[168], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[168]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[169], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[169]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[16], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[16]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[170], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[170]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[171], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[171]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[172], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[172]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[173], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[173]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[174], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[174]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[175], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[175]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[176], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[176]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[177], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[177]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[178], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[178]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[179], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[179]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[17], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[17]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[180], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[180]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[181], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[181]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[182], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[182]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[183], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[183]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[184], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[184]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[185], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[185]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[186], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[186]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[187], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[187]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[188], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[188]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[189], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[189]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[18], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[18]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[190], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[190]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[191], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[191]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[192], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[192]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[193], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[193]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[194], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[194]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[195], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[195]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[196], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[196]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[197], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[197]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[198], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[198]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[199], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[199]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[19], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[19]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[1]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[200], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[200]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[201], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[201]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[202], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[202]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[203], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[203]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[204], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[204]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[205], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[205]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[206], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[206]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[207], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[207]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[208], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[208]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[209], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[209]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[20], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[20]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[210], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[210]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[211], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[211]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[212], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[212]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[213], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[213]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[214], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[214]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[215], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[215]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[216], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[216]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[217], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[217]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[218], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[218]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[219], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[219]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[21], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[21]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[220], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[220]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[221], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[221]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[222], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[222]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[223], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[223]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[224], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[224]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[225], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[225]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[226], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[226]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[227], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[227]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[228], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[228]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[229], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[229]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[22], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[22]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[230], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[230]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[231], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[231]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[232], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[232]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[233], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[233]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[234], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[234]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[235], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[235]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[236], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[236]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[237], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[237]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[238], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[238]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[239], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[239]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[23], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[23]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[240], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[240]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[241], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[241]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[242], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[242]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[243], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[243]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[244], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[244]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[245], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[245]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[246], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[246]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[247], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[247]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[248], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[248]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[249], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[249]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[24], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[24]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[250], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[250]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[251], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[251]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[252], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[252]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[253], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[253]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[254], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[254]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[255], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[255]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[25], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[25]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[26], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[26]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[27], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[27]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[28], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[28]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[29], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[29]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[2]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[30], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[30]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[31], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[31]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[32], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[32]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[33], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[33]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[34], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[34]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[35], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[35]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[36], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[36]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[37], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[37]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[38], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[38]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[39], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[39]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[3]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[40], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[40]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[41], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[41]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[42], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[42]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[43], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[43]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[44], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[44]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[45], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[45]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[46], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[46]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[47], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[47]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[48], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[48]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[49], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[49]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[4], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[4]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[50], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[50]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[51], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[51]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[52], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[52]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[53], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[53]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[54], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[54]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[55], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[55]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[56], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[56]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[57], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[57]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[58], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[58]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[59], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[59]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[5], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[5]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[60], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[60]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[61], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[61]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[62], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[62]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[63], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[63]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[64], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[64]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[65], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[65]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[66], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[66]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[67], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[67]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[68], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[68]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[69], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[69]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[6], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[6]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[70], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[70]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[71], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[71]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[72], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[72]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[73], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[73]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[74], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[74]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[75], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[75]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[76], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[76]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[77], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[77]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[78], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[78]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[79], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[79]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[7], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[7]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[80], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[80]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[81], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[81]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[82], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[82]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[83], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[83]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[84], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[84]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[85], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[85]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[86], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[86]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[87], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[87]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[88], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[88]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[89], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[89]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[8], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[8]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[90], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[90]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[91], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[91]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[92], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[92]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[93], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[93]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[94], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[94]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[95], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[95]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[96], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[96]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[97], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[97]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[98], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[98]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[99], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[99]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_FC_STAT[9], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[9]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_RLIM_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RLIM_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge RX_BYPASS_FORCE_REALIGNIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_FORCE_REALIGNIN_delay); + $setuphold (posedge CORE_CLK, negedge RX_BYPASS_RDIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_RDIN_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_ERRIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ERRIN_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_RESET, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_RESET_MODE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_MODE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[0]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[1]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[2]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[3]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[0]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[100], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[100]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[101], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[101]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[102], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[102]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[103], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[103]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[104], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[104]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[105], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[105]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[106], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[106]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[107], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[107]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[108], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[108]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[109], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[109]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[10], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[10]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[110], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[110]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[111], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[111]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[112], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[112]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[113], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[113]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[114], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[114]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[115], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[115]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[116], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[116]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[117], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[117]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[118], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[118]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[119], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[119]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[11], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[11]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[120], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[120]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[121], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[121]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[122], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[122]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[123], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[123]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[124], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[124]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[125], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[125]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[126], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[126]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[127], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[127]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[128], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[128]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[129], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[129]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[12], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[12]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[130], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[130]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[131], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[131]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[132], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[132]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[133], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[133]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[134], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[134]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[135], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[135]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[136], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[136]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[137], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[137]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[138], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[138]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[139], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[139]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[13], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[13]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[140], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[140]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[141], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[141]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[142], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[142]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[143], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[143]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[144], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[144]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[145], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[145]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[146], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[146]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[147], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[147]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[148], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[148]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[149], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[149]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[14], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[14]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[150], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[150]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[151], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[151]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[152], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[152]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[153], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[153]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[154], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[154]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[155], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[155]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[156], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[156]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[157], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[157]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[158], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[158]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[159], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[159]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[15], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[15]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[160], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[160]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[161], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[161]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[162], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[162]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[163], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[163]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[164], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[164]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[165], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[165]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[166], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[166]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[167], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[167]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[168], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[168]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[169], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[169]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[16], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[16]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[170], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[170]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[171], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[171]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[172], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[172]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[173], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[173]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[174], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[174]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[175], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[175]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[176], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[176]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[177], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[177]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[178], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[178]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[179], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[179]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[17], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[17]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[180], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[180]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[181], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[181]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[182], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[182]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[183], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[183]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[184], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[184]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[185], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[185]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[186], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[186]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[187], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[187]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[188], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[188]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[189], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[189]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[18], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[18]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[190], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[190]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[191], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[191]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[192], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[192]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[193], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[193]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[194], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[194]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[195], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[195]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[196], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[196]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[197], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[197]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[198], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[198]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[199], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[199]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[19], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[19]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[1]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[200], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[200]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[201], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[201]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[202], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[202]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[203], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[203]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[204], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[204]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[205], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[205]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[206], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[206]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[207], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[207]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[208], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[208]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[209], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[209]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[20], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[20]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[210], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[210]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[211], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[211]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[212], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[212]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[213], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[213]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[214], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[214]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[215], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[215]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[216], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[216]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[217], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[217]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[218], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[218]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[219], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[219]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[21], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[21]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[220], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[220]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[221], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[221]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[222], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[222]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[223], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[223]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[224], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[224]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[225], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[225]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[226], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[226]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[227], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[227]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[228], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[228]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[229], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[229]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[22], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[22]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[230], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[230]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[231], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[231]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[232], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[232]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[233], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[233]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[234], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[234]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[235], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[235]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[236], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[236]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[237], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[237]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[238], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[238]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[239], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[239]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[23], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[23]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[240], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[240]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[241], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[241]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[242], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[242]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[243], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[243]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[244], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[244]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[245], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[245]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[246], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[246]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[247], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[247]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[248], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[248]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[249], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[249]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[24], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[24]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[250], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[250]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[251], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[251]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[252], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[252]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[253], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[253]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[254], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[254]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[255], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[255]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[25], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[25]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[26], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[26]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[27], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[27]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[28], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[28]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[29], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[29]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[2]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[30], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[30]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[31], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[31]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[32], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[32]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[33], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[33]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[34], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[34]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[35], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[35]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[36], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[36]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[37], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[37]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[38], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[38]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[39], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[39]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[3]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[40], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[40]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[41], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[41]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[42], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[42]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[43], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[43]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[44], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[44]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[45], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[45]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[46], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[46]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[47], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[47]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[48], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[48]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[49], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[49]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[4], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[4]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[50], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[50]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[51], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[51]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[52], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[52]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[53], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[53]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[54], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[54]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[55], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[55]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[56], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[56]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[57], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[57]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[58], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[58]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[59], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[59]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[5], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[5]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[60], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[60]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[61], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[61]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[62], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[62]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[63], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[63]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[64], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[64]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[65], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[65]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[66], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[66]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[67], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[67]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[68], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[68]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[69], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[69]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[6], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[6]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[70], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[70]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[71], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[71]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[72], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[72]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[73], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[73]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[74], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[74]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[75], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[75]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[76], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[76]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[77], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[77]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[78], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[78]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[79], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[79]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[7], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[7]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[80], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[80]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[81], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[81]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[82], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[82]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[83], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[83]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[84], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[84]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[85], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[85]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[86], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[86]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[87], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[87]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[88], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[88]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[89], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[89]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[8], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[8]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[90], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[90]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[91], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[91]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[92], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[92]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[93], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[93]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[94], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[94]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[95], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[95]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[96], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[96]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[97], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[97]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[98], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[98]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[99], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[99]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_FC_STAT[9], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_FC_STAT_delay[9]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_RLIM_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RLIM_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge RX_BYPASS_FORCE_REALIGNIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_FORCE_REALIGNIN_delay); + $setuphold (posedge CORE_CLK, posedge RX_BYPASS_RDIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_RDIN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, posedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_ERRINJ_BITERR_GO, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_ERRINJ_BITERR_GO_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_PERRIN, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_PERRIN_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[100]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[101]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[102]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[103]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[104]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[105]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[106]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[107]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[108]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[109]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[110]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[111]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[112]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[113]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[114]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[115]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[116]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[117]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[118]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[119]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[120]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[121]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[122]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[123]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[124]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[125]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[126]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[127]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[128]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[129]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[12]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[130]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[131]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[132]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[133]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[134]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[135]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[136]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[137]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[138]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[139]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[13]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[140]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[141]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[142]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[143]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[144]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[145]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[146]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[147]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[148]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[149]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[14]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[150]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[151]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[152]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[153]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[154]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[155]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[156]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[157]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[158]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[159]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[15]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[160]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[161]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[162]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[163]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[164]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[165]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[166]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[167]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[168]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[169]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[16]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[170]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[171]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[172]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[173]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[174]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[175]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[176]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[177]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[178]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[179]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[17]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[180]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[181]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[182]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[183]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[184]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[185]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[186]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[187]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[188]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[189]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[18]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[190]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[191]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[192]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[193]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[194]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[195]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[196]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[197]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[198]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[199]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[19]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[200]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[201]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[202]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[203]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[204]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[205]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[206]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[207]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[208]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[209]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[20]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[210]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[211]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[212]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[213]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[214]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[215]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[216]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[217]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[218]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[219]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[21]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[220]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[221]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[222]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[223]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[224]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[225]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[226]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[227]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[228]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[229]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[22]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[230]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[231]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[232]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[233]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[234]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[235]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[236]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[237]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[238]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[239]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[23]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[240]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[241]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[242]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[243]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[244]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[245]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[246]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[247]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[248]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[249]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[24]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[250]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[251]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[252]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[253]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[254]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[255]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[256], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[256]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[257], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[257]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[258], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[258]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[259], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[259]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[25]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[260], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[260]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[261], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[261]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[262], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[262]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[263], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[263]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[264], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[264]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[265], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[265]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[266], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[266]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[267], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[267]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[268], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[268]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[269], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[269]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[26]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[270], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[270]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[271], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[271]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[272], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[272]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[273], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[273]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[274], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[274]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[275], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[275]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[276], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[276]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[277], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[277]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[278], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[278]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[279], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[279]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[27]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[280], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[280]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[281], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[281]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[282], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[282]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[283], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[283]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[284], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[284]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[285], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[285]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[286], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[286]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[287], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[287]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[288], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[288]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[289], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[289]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[28]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[290], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[290]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[291], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[291]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[292], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[292]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[293], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[293]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[294], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[294]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[295], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[295]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[296], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[296]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[297], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[297]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[298], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[298]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[299], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[299]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[29]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[300], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[300]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[301], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[301]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[302], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[302]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[303], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[303]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[304], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[304]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[305], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[305]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[306], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[306]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[307], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[307]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[308], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[308]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[309], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[309]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[30]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[310], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[310]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[311], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[311]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[312], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[312]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[313], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[313]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[314], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[314]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[315], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[315]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[316], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[316]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[317], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[317]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[318], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[318]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[319], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[319]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[31]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[320], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[320]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[321], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[321]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[322], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[322]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[323], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[323]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[324], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[324]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[325], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[325]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[326], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[326]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[327], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[327]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[328], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[328]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[329], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[329]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[32]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[330], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[330]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[331], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[331]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[332], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[332]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[333], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[333]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[334], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[334]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[335], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[335]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[336], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[336]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[337], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[337]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[338], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[338]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[339], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[339]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[33]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[340], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[340]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[341], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[341]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[342], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[342]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[343], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[343]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[344], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[344]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[345], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[345]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[346], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[346]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[347], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[347]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[348], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[348]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[349], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[349]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[34]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[350], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[350]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[351], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[351]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[352], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[352]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[353], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[353]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[354], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[354]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[355], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[355]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[356], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[356]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[357], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[357]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[358], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[358]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[359], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[359]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[35]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[360], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[360]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[361], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[361]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[362], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[362]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[363], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[363]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[364], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[364]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[365], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[365]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[366], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[366]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[367], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[367]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[368], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[368]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[369], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[369]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[36]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[370], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[370]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[371], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[371]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[372], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[372]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[373], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[373]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[374], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[374]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[375], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[375]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[376], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[376]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[377], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[377]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[378], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[378]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[379], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[379]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[37]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[380], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[380]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[381], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[381]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[382], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[382]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[383], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[383]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[384], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[384]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[385], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[385]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[386], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[386]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[387], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[387]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[388], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[388]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[389], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[389]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[38]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[390], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[390]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[391], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[391]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[392], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[392]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[393], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[393]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[394], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[394]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[395], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[395]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[396], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[396]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[397], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[397]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[398], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[398]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[399], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[399]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[39]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[400], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[400]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[401], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[401]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[402], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[402]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[403], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[403]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[404], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[404]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[405], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[405]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[406], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[406]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[407], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[407]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[408], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[408]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[409], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[409]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[40]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[410], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[410]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[411], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[411]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[412], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[412]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[413], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[413]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[414], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[414]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[415], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[415]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[416], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[416]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[417], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[417]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[418], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[418]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[419], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[419]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[41]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[420], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[420]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[421], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[421]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[422], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[422]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[423], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[423]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[424], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[424]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[425], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[425]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[426], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[426]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[427], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[427]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[428], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[428]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[429], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[429]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[42]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[430], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[430]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[431], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[431]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[432], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[432]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[433], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[433]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[434], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[434]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[435], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[435]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[436], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[436]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[437], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[437]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[438], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[438]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[439], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[439]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[43]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[440], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[440]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[441], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[441]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[442], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[442]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[443], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[443]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[444], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[444]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[445], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[445]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[446], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[446]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[447], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[447]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[448], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[448]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[449], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[449]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[44]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[450], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[450]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[451], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[451]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[452], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[452]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[453], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[453]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[454], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[454]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[455], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[455]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[456], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[456]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[457], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[457]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[458], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[458]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[459], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[459]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[45]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[460], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[460]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[461], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[461]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[462], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[462]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[463], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[463]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[464], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[464]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[465], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[465]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[466], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[466]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[467], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[467]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[468], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[468]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[469], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[469]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[46]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[470], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[470]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[471], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[471]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[472], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[472]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[473], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[473]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[474], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[474]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[475], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[475]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[476], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[476]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[477], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[477]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[478], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[478]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[479], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[479]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[47]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[480], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[480]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[481], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[481]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[482], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[482]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[483], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[483]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[484], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[484]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[485], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[485]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[486], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[486]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[487], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[487]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[488], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[488]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[489], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[489]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[48]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[490], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[490]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[491], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[491]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[492], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[492]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[493], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[493]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[494], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[494]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[495], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[495]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[496], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[496]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[497], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[497]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[498], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[498]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[499], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[499]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[49]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[500], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[500]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[501], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[501]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[502], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[502]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[503], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[503]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[504], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[504]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[505], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[505]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[506], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[506]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[507], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[507]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[508], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[508]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[509], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[509]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[50]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[510], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[510]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[511], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[511]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[512], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[512]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[513], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[513]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[514], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[514]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[515], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[515]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[516], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[516]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[517], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[517]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[518], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[518]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[519], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[519]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[51]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[520], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[520]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[521], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[521]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[522], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[522]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[523], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[523]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[524], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[524]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[525], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[525]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[526], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[526]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[527], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[527]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[528], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[528]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[529], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[529]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[52]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[530], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[530]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[531], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[531]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[532], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[532]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[533], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[533]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[534], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[534]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[535], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[535]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[536], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[536]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[537], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[537]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[538], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[538]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[539], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[539]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[53]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[540], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[540]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[541], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[541]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[542], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[542]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[543], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[543]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[544], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[544]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[545], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[545]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[546], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[546]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[547], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[547]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[548], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[548]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[549], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[549]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[54]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[550], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[550]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[551], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[551]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[552], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[552]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[553], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[553]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[554], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[554]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[555], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[555]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[556], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[556]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[557], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[557]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[558], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[558]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[559], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[559]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[55]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[560], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[560]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[561], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[561]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[562], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[562]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[563], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[563]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[564], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[564]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[565], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[565]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[566], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[566]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[567], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[567]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[568], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[568]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[569], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[569]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[56]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[570], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[570]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[571], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[571]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[572], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[572]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[573], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[573]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[574], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[574]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[575], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[575]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[576], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[576]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[577], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[577]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[578], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[578]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[579], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[579]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[57]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[580], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[580]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[581], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[581]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[582], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[582]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[583], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[583]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[584], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[584]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[585], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[585]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[586], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[586]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[587], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[587]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[588], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[588]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[589], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[589]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[58]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[590], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[590]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[591], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[591]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[592], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[592]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[593], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[593]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[594], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[594]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[595], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[595]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[596], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[596]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[597], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[597]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[598], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[598]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[599], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[599]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[59]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[600], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[600]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[601], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[601]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[602], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[602]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[603], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[603]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[604], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[604]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[605], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[605]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[606], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[606]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[607], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[607]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[608], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[608]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[609], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[609]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[60]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[610], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[610]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[611], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[611]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[612], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[612]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[613], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[613]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[614], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[614]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[615], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[615]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[616], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[616]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[617], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[617]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[618], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[618]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[619], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[619]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[61]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[620], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[620]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[621], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[621]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[622], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[622]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[623], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[623]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[624], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[624]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[625], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[625]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[626], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[626]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[627], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[627]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[628], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[628]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[629], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[629]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[62]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[630], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[630]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[631], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[631]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[632], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[632]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[633], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[633]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[634], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[634]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[635], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[635]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[636], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[636]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[637], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[637]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[638], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[638]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[639], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[639]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[63]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[640], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[640]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[641], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[641]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[642], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[642]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[643], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[643]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[64]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[65]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[66]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[67]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[68]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[69]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[70]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[71]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[72]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[73]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[74]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[75]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[76]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[77]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[78]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[79]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[80]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[81]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[82]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[83]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[84]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[85]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[86]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[87]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[88]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[89]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[90]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[91]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[92]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[93]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[94]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[95]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[96]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[97]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[98]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[99]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[9]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_REQ_VALID, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_VALID_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[9]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_ERRINJ_BITERR_GO, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_ERRINJ_BITERR_GO_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_PERRIN, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_PERRIN_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[100]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[101]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[102]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[103]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[104]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[105]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[106]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[107]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[108]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[109]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[110]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[111]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[112]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[113]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[114]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[115]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[116]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[117]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[118]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[119]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[120]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[121]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[122]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[123]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[124]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[125]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[126]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[127]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[128]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[129]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[12]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[130]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[131]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[132]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[133]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[134]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[135]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[136]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[137]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[138]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[139]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[13]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[140]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[141]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[142]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[143]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[144]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[145]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[146]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[147]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[148]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[149]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[14]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[150]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[151]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[152]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[153]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[154]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[155]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[156]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[157]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[158]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[159]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[15]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[160]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[161]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[162]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[163]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[164]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[165]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[166]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[167]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[168]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[169]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[16]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[170]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[171]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[172]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[173]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[174]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[175]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[176]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[177]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[178]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[179]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[17]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[180]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[181]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[182]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[183]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[184]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[185]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[186]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[187]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[188]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[189]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[18]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[190]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[191]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[192]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[193]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[194]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[195]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[196]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[197]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[198]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[199]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[19]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[200]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[201]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[202]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[203]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[204]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[205]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[206]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[207]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[208]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[209]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[20]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[210]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[211]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[212]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[213]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[214]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[215]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[216]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[217]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[218]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[219]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[21]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[220]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[221]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[222]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[223]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[224]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[225]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[226]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[227]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[228]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[229]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[22]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[230]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[231]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[232]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[233]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[234]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[235]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[236]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[237]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[238]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[239]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[23]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[240]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[241]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[242]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[243]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[244]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[245]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[246]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[247]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[248]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[249]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[24]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[250]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[251]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[252]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[253]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[254]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[255]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[256], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[256]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[257], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[257]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[258], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[258]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[259], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[259]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[25]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[260], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[260]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[261], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[261]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[262], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[262]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[263], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[263]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[264], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[264]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[265], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[265]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[266], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[266]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[267], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[267]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[268], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[268]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[269], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[269]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[26]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[270], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[270]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[271], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[271]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[272], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[272]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[273], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[273]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[274], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[274]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[275], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[275]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[276], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[276]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[277], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[277]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[278], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[278]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[279], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[279]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[27]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[280], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[280]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[281], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[281]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[282], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[282]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[283], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[283]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[284], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[284]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[285], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[285]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[286], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[286]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[287], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[287]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[288], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[288]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[289], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[289]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[28]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[290], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[290]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[291], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[291]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[292], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[292]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[293], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[293]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[294], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[294]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[295], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[295]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[296], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[296]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[297], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[297]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[298], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[298]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[299], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[299]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[29]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[300], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[300]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[301], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[301]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[302], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[302]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[303], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[303]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[304], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[304]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[305], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[305]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[306], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[306]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[307], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[307]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[308], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[308]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[309], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[309]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[30]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[310], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[310]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[311], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[311]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[312], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[312]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[313], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[313]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[314], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[314]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[315], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[315]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[316], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[316]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[317], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[317]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[318], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[318]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[319], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[319]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[31]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[320], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[320]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[321], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[321]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[322], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[322]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[323], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[323]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[324], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[324]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[325], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[325]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[326], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[326]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[327], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[327]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[328], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[328]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[329], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[329]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[32]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[330], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[330]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[331], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[331]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[332], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[332]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[333], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[333]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[334], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[334]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[335], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[335]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[336], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[336]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[337], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[337]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[338], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[338]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[339], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[339]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[33]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[340], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[340]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[341], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[341]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[342], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[342]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[343], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[343]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[344], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[344]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[345], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[345]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[346], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[346]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[347], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[347]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[348], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[348]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[349], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[349]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[34]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[350], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[350]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[351], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[351]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[352], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[352]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[353], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[353]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[354], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[354]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[355], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[355]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[356], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[356]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[357], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[357]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[358], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[358]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[359], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[359]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[35]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[360], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[360]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[361], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[361]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[362], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[362]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[363], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[363]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[364], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[364]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[365], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[365]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[366], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[366]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[367], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[367]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[368], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[368]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[369], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[369]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[36]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[370], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[370]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[371], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[371]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[372], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[372]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[373], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[373]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[374], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[374]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[375], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[375]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[376], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[376]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[377], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[377]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[378], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[378]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[379], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[379]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[37]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[380], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[380]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[381], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[381]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[382], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[382]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[383], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[383]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[384], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[384]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[385], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[385]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[386], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[386]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[387], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[387]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[388], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[388]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[389], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[389]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[38]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[390], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[390]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[391], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[391]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[392], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[392]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[393], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[393]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[394], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[394]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[395], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[395]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[396], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[396]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[397], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[397]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[398], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[398]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[399], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[399]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[39]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[400], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[400]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[401], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[401]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[402], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[402]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[403], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[403]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[404], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[404]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[405], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[405]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[406], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[406]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[407], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[407]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[408], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[408]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[409], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[409]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[40]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[410], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[410]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[411], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[411]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[412], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[412]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[413], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[413]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[414], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[414]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[415], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[415]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[416], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[416]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[417], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[417]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[418], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[418]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[419], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[419]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[41]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[420], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[420]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[421], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[421]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[422], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[422]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[423], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[423]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[424], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[424]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[425], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[425]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[426], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[426]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[427], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[427]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[428], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[428]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[429], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[429]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[42]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[430], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[430]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[431], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[431]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[432], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[432]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[433], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[433]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[434], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[434]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[435], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[435]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[436], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[436]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[437], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[437]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[438], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[438]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[439], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[439]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[43]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[440], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[440]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[441], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[441]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[442], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[442]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[443], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[443]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[444], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[444]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[445], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[445]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[446], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[446]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[447], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[447]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[448], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[448]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[449], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[449]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[44]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[450], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[450]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[451], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[451]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[452], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[452]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[453], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[453]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[454], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[454]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[455], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[455]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[456], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[456]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[457], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[457]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[458], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[458]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[459], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[459]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[45]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[460], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[460]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[461], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[461]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[462], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[462]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[463], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[463]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[464], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[464]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[465], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[465]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[466], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[466]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[467], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[467]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[468], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[468]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[469], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[469]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[46]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[470], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[470]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[471], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[471]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[472], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[472]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[473], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[473]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[474], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[474]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[475], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[475]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[476], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[476]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[477], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[477]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[478], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[478]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[479], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[479]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[47]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[480], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[480]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[481], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[481]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[482], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[482]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[483], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[483]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[484], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[484]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[485], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[485]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[486], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[486]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[487], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[487]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[488], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[488]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[489], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[489]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[48]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[490], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[490]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[491], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[491]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[492], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[492]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[493], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[493]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[494], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[494]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[495], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[495]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[496], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[496]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[497], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[497]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[498], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[498]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[499], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[499]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[49]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[500], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[500]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[501], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[501]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[502], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[502]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[503], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[503]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[504], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[504]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[505], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[505]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[506], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[506]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[507], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[507]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[508], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[508]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[509], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[509]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[50]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[510], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[510]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[511], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[511]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[512], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[512]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[513], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[513]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[514], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[514]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[515], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[515]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[516], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[516]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[517], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[517]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[518], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[518]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[519], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[519]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[51]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[520], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[520]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[521], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[521]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[522], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[522]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[523], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[523]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[524], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[524]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[525], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[525]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[526], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[526]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[527], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[527]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[528], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[528]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[529], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[529]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[52]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[530], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[530]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[531], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[531]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[532], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[532]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[533], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[533]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[534], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[534]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[535], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[535]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[536], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[536]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[537], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[537]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[538], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[538]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[539], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[539]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[53]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[540], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[540]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[541], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[541]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[542], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[542]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[543], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[543]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[544], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[544]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[545], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[545]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[546], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[546]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[547], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[547]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[548], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[548]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[549], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[549]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[54]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[550], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[550]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[551], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[551]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[552], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[552]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[553], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[553]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[554], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[554]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[555], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[555]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[556], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[556]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[557], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[557]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[558], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[558]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[559], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[559]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[55]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[560], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[560]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[561], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[561]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[562], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[562]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[563], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[563]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[564], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[564]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[565], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[565]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[566], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[566]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[567], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[567]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[568], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[568]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[569], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[569]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[56]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[570], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[570]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[571], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[571]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[572], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[572]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[573], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[573]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[574], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[574]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[575], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[575]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[576], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[576]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[577], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[577]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[578], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[578]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[579], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[579]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[57]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[580], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[580]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[581], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[581]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[582], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[582]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[583], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[583]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[584], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[584]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[585], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[585]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[586], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[586]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[587], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[587]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[588], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[588]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[589], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[589]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[58]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[590], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[590]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[591], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[591]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[592], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[592]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[593], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[593]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[594], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[594]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[595], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[595]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[596], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[596]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[597], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[597]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[598], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[598]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[599], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[599]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[59]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[600], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[600]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[601], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[601]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[602], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[602]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[603], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[603]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[604], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[604]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[605], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[605]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[606], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[606]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[607], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[607]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[608], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[608]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[609], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[609]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[60]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[610], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[610]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[611], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[611]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[612], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[612]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[613], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[613]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[614], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[614]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[615], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[615]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[616], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[616]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[617], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[617]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[618], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[618]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[619], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[619]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[61]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[620], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[620]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[621], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[621]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[622], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[622]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[623], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[623]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[624], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[624]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[625], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[625]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[626], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[626]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[627], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[627]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[628], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[628]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[629], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[629]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[62]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[630], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[630]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[631], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[631]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[632], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[632]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[633], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[633]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[634], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[634]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[635], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[635]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[636], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[636]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[637], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[637]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[638], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[638]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[639], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[639]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[63]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[640], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[640]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[641], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[641]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[642], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[642]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[643], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[643]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[64]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[65]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[66]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[67]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[68]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[69]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[70]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[71]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[72]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[73]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[74]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[75]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[76]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[77]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[78]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[79]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[80]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[81]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[82]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[83]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[84]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[85]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[86]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[87]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[88]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[89]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[90]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[91]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[92]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[93]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[94]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[95]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[96]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[97]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[98]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[99]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[9]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_REQ_VALID, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_VALID_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[9]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[9]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[0]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[10]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[11]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[12]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[13]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[14]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[15]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[16]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[17]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[18]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[19]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[1]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[20]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[21]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[22]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[23]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[24]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[25]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[26]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[27]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[28]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[29]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[2]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[30]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[31]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[32]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[33]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[34]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[35]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[36]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[37]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[38]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[39]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[3]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[40]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[41]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[42]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[43]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[44]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[45]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[46]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[47]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[48]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[49]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[4]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[50]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[51]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[52]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[53]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[54]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[55]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[56]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[57]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[58]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[59]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[5]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[60]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[61]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[62]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[63]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[6]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[7]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[8]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[9]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[0]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[10]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[11]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[12]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[13]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[14]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[15]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[16]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[17]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[18]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[19]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[1]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[20]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[21]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[22]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[23]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[24]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[25]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[26]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[27]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[28]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[29]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[2]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[30]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[31]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[32]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[33]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[34]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[35]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[36]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[37]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[38]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[39]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[3]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[40]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[41]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[42]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[43]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[44]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[45]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[46]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[47]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[48]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[49]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[4]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[50]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[51]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[52]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[53]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[54]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[55]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[56]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[57]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[58]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[59]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[5]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[60]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[61]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[62]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[63]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[6]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[7]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[8]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[9]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[0]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[10]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[11]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[12]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[13]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[14]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[15]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[16]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[17]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[18]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[19]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[1]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[20]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[21]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[22]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[23]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[24]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[25]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[26]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[27]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[28]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[29]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[2]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[30]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[31]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[32]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[33]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[34]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[35]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[36]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[37]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[38]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[39]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[3]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[40]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[41]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[42]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[43]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[44]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[45]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[46]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[47]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[48]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[49]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[4]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[50]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[51]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[52]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[53]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[54]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[55]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[56]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[57]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[58]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[59]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[5]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[60]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[61]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[62]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[63]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[6]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[7]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[8]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[9]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[0]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[10]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[11]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[12]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[13]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[14]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[15]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[16]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[17]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[18]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[19]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[1]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[20]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[21]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[22]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[23]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[24]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[25]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[26]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[27]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[28]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[29]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[2]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[30]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[31]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[32]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[33]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[34]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[35]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[36]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[37]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[38]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[39]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[3]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[40]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[41]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[42]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[43]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[44]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[45]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[46]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[47]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[48]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[49]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[4]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[50]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[51]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[52]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[53]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[54]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[55]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[56]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[57]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[58]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[59]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[5]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[60]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[61]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[62]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[63]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[6]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[7]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[8]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[32]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[33]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[34]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[35]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[36]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[37]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[38]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[39]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[40]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[41]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[42]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[43]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[44]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[45]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[46]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[47]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[48]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[49]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[50]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[51]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[52]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[53]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[54]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[55]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[56]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[57]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[58]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[59]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[60]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[61]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[62]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[63]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[32]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[33]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[34]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[35]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[36]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[37]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[38]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[39]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[40]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[41]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[42]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[43]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[44]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[45]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[46]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[47]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[48]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[49]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[50]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[51]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[52]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[53]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[54]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[55]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[56]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[57]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[58]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[59]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[60]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[61]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[62]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[63]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[32]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[33]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[34]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[35]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[36]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[37]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[38]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[39]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[40]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[41]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[42]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[43]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[44]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[45]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[46]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[47]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[48]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[49]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[50]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[51]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[52]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[53]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[54]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[55]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[56]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[57]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[58]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[59]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[60]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[61]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[62]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[63]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[32]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[33]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[34]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[35]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[36]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[37]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[38]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[39]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[40]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[41]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[42]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[43]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[44]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[45]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[46]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[47]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[48]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[49]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[50]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[51]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[52]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[53]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[54]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[55]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[56]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[57]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[58]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[59]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[60]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[61]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[62]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[63]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[32]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[33]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[34]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[35]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[36]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[37]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[38]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[39]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[40]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[41]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[42]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[43]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[44]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[45]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[46]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[47]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[48]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[49]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[50]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[51]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[52]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[53]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[54]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[55]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[56]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[57]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[58]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[59]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[60]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[61]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[62]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[63]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[32]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[33]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[34]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[35]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[36]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[37]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[38]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[39]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[40]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[41]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[42]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[43]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[44]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[45]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[46]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[47]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[48]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[49]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[50]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[51]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[52]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[53]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[54]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[55]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[56]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[57]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[58]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[59]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[60]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[61]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[62]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[63]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[32]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[33]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[34]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[35]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[36]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[37]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[38]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[39]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[40]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[41]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[42]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[43]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[44]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[45]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[46]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[47]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[48]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[49]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[50]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[51]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[52]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[53]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[54]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[55]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[56]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[57]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[58]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[59]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[60]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[61]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[62]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[63]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[32]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[33]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[34]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[35]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[36]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[37]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[38]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[39]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[40]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[41]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[42]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[43]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[44]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[45]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[46]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[47]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[48]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[49]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[50]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[51]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[52]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[53]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[54]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[55]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[56]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[57]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[58]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[59]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[60]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[61]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[62]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[63]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[32]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[33]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[34]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[35]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[36]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[37]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[38]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[39]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[40]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[41]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[42]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[43]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[44]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[45]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[46]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[47]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[48]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[49]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[50]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[51]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[52]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[53]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[54]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[55]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[56]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[57]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[58]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[59]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[60]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[61]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[62]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[63]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[32]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[33]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[34]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[35]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[36]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[37]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[38]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[39]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[40]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[41]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[42]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[43]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[44]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[45]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[46]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[47]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[48]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[49]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[50]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[51]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[52]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[53]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[54]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[55]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[56]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[57]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[58]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[59]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[60]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[61]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[62]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[63]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[32]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[33]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[34]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[35]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[36]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[37]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[38]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[39]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[40]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[41]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[42]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[43]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[44]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[45]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[46]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[47]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[48]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[49]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[50]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[51]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[52]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[53]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[54]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[55]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[56]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[57]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[58]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[59]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[60]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[61]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[62]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[63]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[32]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[33]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[34]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[35]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[36]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[37]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[38]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[39]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[40]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[41]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[42]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[43]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[44]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[45]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[46]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[47]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[48]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[49]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[50]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[51]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[52]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[53]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[54]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[55]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[56]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[57]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[58]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[59]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[60]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[61]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[62]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[63]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_INTFSTAT, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_INTFSTAT_delay); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_ENAIN, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_ENAIN_delay); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_INTFSTAT, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_INTFSTAT_delay); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_ENAIN, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_ENAIN_delay); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[3]); + $width (negedge CORE_CLK, 0:0:0, 0, notifier); + $width (negedge DRP_CLK, 0:0:0, 0, notifier); + $width (negedge LBUS_CLK, 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[10], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[11], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (negedge TX_SERDES_REFCLK, 0:0:0, 0, notifier); + $width (posedge CORE_CLK, 0:0:0, 0, notifier); + $width (posedge DRP_CLK, 0:0:0, 0, notifier); + $width (posedge LBUS_CLK, 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[10], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[11], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (posedge TX_SERDES_REFCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ILKNE4.v b/verilog/src/unisims/ILKNE4.v new file mode 100644 index 0000000..d7fd80a --- /dev/null +++ b/verilog/src/unisims/ILKNE4.v @@ -0,0 +1,11244 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Interlaken MAC +// /___/ /\ Filename : ILKNE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ILKNE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter BYPASS = "FALSE", + parameter [1:0] CTL_RX_BURSTMAX = 2'h3, + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0, + parameter [3:0] CTL_RX_LAST_LANE = 4'hB, + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF, + parameter CTL_RX_PACKET_MODE = "FALSE", + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0, + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2, + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009, + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000, + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000, + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00, + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE", + parameter [1:0] CTL_TX_BURSTMAX = 2'h3, + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1, + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0, + parameter CTL_TX_DISABLE_SKIPWORD = "FALSE", + parameter [3:0] CTL_TX_FC_CALLEN = 4'hF, + parameter [3:0] CTL_TX_LAST_LANE = 4'hB, + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF, + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800, + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0, + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3, + parameter MODE = "TRUE", + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter TEST_MODE_PIN_CHAR = "FALSE" +)( + output [15:0] DRP_DO, + output DRP_RDY, + output [65:0] RX_BYPASS_DATAOUT00, + output [65:0] RX_BYPASS_DATAOUT01, + output [65:0] RX_BYPASS_DATAOUT02, + output [65:0] RX_BYPASS_DATAOUT03, + output [65:0] RX_BYPASS_DATAOUT04, + output [65:0] RX_BYPASS_DATAOUT05, + output [65:0] RX_BYPASS_DATAOUT06, + output [65:0] RX_BYPASS_DATAOUT07, + output [65:0] RX_BYPASS_DATAOUT08, + output [65:0] RX_BYPASS_DATAOUT09, + output [65:0] RX_BYPASS_DATAOUT10, + output [65:0] RX_BYPASS_DATAOUT11, + output [11:0] RX_BYPASS_ENAOUT, + output [11:0] RX_BYPASS_IS_AVAILOUT, + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT, + output [11:0] RX_BYPASS_IS_OVERFLOWOUT, + output [11:0] RX_BYPASS_IS_SYNCEDOUT, + output [11:0] RX_BYPASS_IS_SYNCWORDOUT, + output [10:0] RX_CHANOUT0, + output [10:0] RX_CHANOUT1, + output [10:0] RX_CHANOUT2, + output [10:0] RX_CHANOUT3, + output [127:0] RX_DATAOUT0, + output [127:0] RX_DATAOUT1, + output [127:0] RX_DATAOUT2, + output [127:0] RX_DATAOUT3, + output RX_ENAOUT0, + output RX_ENAOUT1, + output RX_ENAOUT2, + output RX_ENAOUT3, + output RX_EOPOUT0, + output RX_EOPOUT1, + output RX_EOPOUT2, + output RX_EOPOUT3, + output RX_ERROUT0, + output RX_ERROUT1, + output RX_ERROUT2, + output RX_ERROUT3, + output [3:0] RX_MTYOUT0, + output [3:0] RX_MTYOUT1, + output [3:0] RX_MTYOUT2, + output [3:0] RX_MTYOUT3, + output RX_OVFOUT, + output RX_SOPOUT0, + output RX_SOPOUT1, + output RX_SOPOUT2, + output RX_SOPOUT3, + output STAT_RX_ALIGNED, + output STAT_RX_ALIGNED_ERR, + output [11:0] STAT_RX_BAD_TYPE_ERR, + output STAT_RX_BURSTMAX_ERR, + output STAT_RX_BURST_ERR, + output STAT_RX_CRC24_ERR, + output [11:0] STAT_RX_CRC32_ERR, + output [11:0] STAT_RX_CRC32_VALID, + output [11:0] STAT_RX_DESCRAM_ERR, + output [11:0] STAT_RX_DIAGWORD_INTFSTAT, + output [11:0] STAT_RX_DIAGWORD_LANESTAT, + output [255:0] STAT_RX_FC_STAT, + output [11:0] STAT_RX_FRAMING_ERR, + output STAT_RX_MEOP_ERR, + output [11:0] STAT_RX_MF_ERR, + output [11:0] STAT_RX_MF_LEN_ERR, + output [11:0] STAT_RX_MF_REPEAT_ERR, + output STAT_RX_MISALIGNED, + output STAT_RX_MSOP_ERR, + output [7:0] STAT_RX_MUBITS, + output STAT_RX_MUBITS_UPDATED, + output STAT_RX_OVERFLOW_ERR, + output STAT_RX_RETRANS_CRC24_ERR, + output STAT_RX_RETRANS_DISC, + output [15:0] STAT_RX_RETRANS_LATENCY, + output STAT_RX_RETRANS_REQ, + output STAT_RX_RETRANS_RETRY_ERR, + output [7:0] STAT_RX_RETRANS_SEQ, + output STAT_RX_RETRANS_SEQ_UPDATED, + output [2:0] STAT_RX_RETRANS_STATE, + output [4:0] STAT_RX_RETRANS_SUBSEQ, + output STAT_RX_RETRANS_WDOG_ERR, + output STAT_RX_RETRANS_WRAP_ERR, + output [11:0] STAT_RX_SYNCED, + output [11:0] STAT_RX_SYNCED_ERR, + output [11:0] STAT_RX_WORD_SYNC, + output STAT_TX_BURST_ERR, + output STAT_TX_ERRINJ_BITERR_DONE, + output STAT_TX_OVERFLOW_ERR, + output STAT_TX_RETRANS_BURST_ERR, + output STAT_TX_RETRANS_BUSY, + output STAT_TX_RETRANS_RAM_PERROUT, + output [8:0] STAT_TX_RETRANS_RAM_RADDR, + output STAT_TX_RETRANS_RAM_RD_B0, + output STAT_TX_RETRANS_RAM_RD_B1, + output STAT_TX_RETRANS_RAM_RD_B2, + output STAT_TX_RETRANS_RAM_RD_B3, + output [1:0] STAT_TX_RETRANS_RAM_RSEL, + output [8:0] STAT_TX_RETRANS_RAM_WADDR, + output [643:0] STAT_TX_RETRANS_RAM_WDATA, + output STAT_TX_RETRANS_RAM_WE_B0, + output STAT_TX_RETRANS_RAM_WE_B1, + output STAT_TX_RETRANS_RAM_WE_B2, + output STAT_TX_RETRANS_RAM_WE_B3, + output STAT_TX_UNDERFLOW_ERR, + output TX_OVFOUT, + output TX_RDYOUT, + output [63:0] TX_SERDES_DATA00, + output [63:0] TX_SERDES_DATA01, + output [63:0] TX_SERDES_DATA02, + output [63:0] TX_SERDES_DATA03, + output [63:0] TX_SERDES_DATA04, + output [63:0] TX_SERDES_DATA05, + output [63:0] TX_SERDES_DATA06, + output [63:0] TX_SERDES_DATA07, + output [63:0] TX_SERDES_DATA08, + output [63:0] TX_SERDES_DATA09, + output [63:0] TX_SERDES_DATA10, + output [63:0] TX_SERDES_DATA11, + + input CORE_CLK, + input CTL_RX_FORCE_RESYNC, + input CTL_RX_RETRANS_ACK, + input CTL_RX_RETRANS_ENABLE, + input CTL_RX_RETRANS_ERRIN, + input CTL_RX_RETRANS_FORCE_REQ, + input CTL_RX_RETRANS_RESET, + input CTL_RX_RETRANS_RESET_MODE, + input CTL_TX_DIAGWORD_INTFSTAT, + input [11:0] CTL_TX_DIAGWORD_LANESTAT, + input CTL_TX_ENABLE, + input CTL_TX_ERRINJ_BITERR_GO, + input [3:0] CTL_TX_ERRINJ_BITERR_LANE, + input [255:0] CTL_TX_FC_STAT, + input [7:0] CTL_TX_MUBITS, + input CTL_TX_RETRANS_ENABLE, + input CTL_TX_RETRANS_RAM_PERRIN, + input [643:0] CTL_TX_RETRANS_RAM_RDATA, + input CTL_TX_RETRANS_REQ, + input CTL_TX_RETRANS_REQ_VALID, + input [11:0] CTL_TX_RLIM_DELTA, + input CTL_TX_RLIM_ENABLE, + input [7:0] CTL_TX_RLIM_INTV, + input [11:0] CTL_TX_RLIM_MAX, + input [9:0] DRP_ADDR, + input DRP_CLK, + input [15:0] DRP_DI, + input DRP_EN, + input DRP_WE, + input LBUS_CLK, + input RX_BYPASS_FORCE_REALIGNIN, + input RX_BYPASS_RDIN, + input RX_RESET, + input [11:0] RX_SERDES_CLK, + input [63:0] RX_SERDES_DATA00, + input [63:0] RX_SERDES_DATA01, + input [63:0] RX_SERDES_DATA02, + input [63:0] RX_SERDES_DATA03, + input [63:0] RX_SERDES_DATA04, + input [63:0] RX_SERDES_DATA05, + input [63:0] RX_SERDES_DATA06, + input [63:0] RX_SERDES_DATA07, + input [63:0] RX_SERDES_DATA08, + input [63:0] RX_SERDES_DATA09, + input [63:0] RX_SERDES_DATA10, + input [63:0] RX_SERDES_DATA11, + input [11:0] RX_SERDES_RESET, + input TX_BCTLIN0, + input TX_BCTLIN1, + input TX_BCTLIN2, + input TX_BCTLIN3, + input [11:0] TX_BYPASS_CTRLIN, + input [63:0] TX_BYPASS_DATAIN00, + input [63:0] TX_BYPASS_DATAIN01, + input [63:0] TX_BYPASS_DATAIN02, + input [63:0] TX_BYPASS_DATAIN03, + input [63:0] TX_BYPASS_DATAIN04, + input [63:0] TX_BYPASS_DATAIN05, + input [63:0] TX_BYPASS_DATAIN06, + input [63:0] TX_BYPASS_DATAIN07, + input [63:0] TX_BYPASS_DATAIN08, + input [63:0] TX_BYPASS_DATAIN09, + input [63:0] TX_BYPASS_DATAIN10, + input [63:0] TX_BYPASS_DATAIN11, + input TX_BYPASS_ENAIN, + input [7:0] TX_BYPASS_GEARBOX_SEQIN, + input [3:0] TX_BYPASS_MFRAMER_STATEIN, + input [10:0] TX_CHANIN0, + input [10:0] TX_CHANIN1, + input [10:0] TX_CHANIN2, + input [10:0] TX_CHANIN3, + input [127:0] TX_DATAIN0, + input [127:0] TX_DATAIN1, + input [127:0] TX_DATAIN2, + input [127:0] TX_DATAIN3, + input TX_ENAIN0, + input TX_ENAIN1, + input TX_ENAIN2, + input TX_ENAIN3, + input TX_EOPIN0, + input TX_EOPIN1, + input TX_EOPIN2, + input TX_EOPIN3, + input TX_ERRIN0, + input TX_ERRIN1, + input TX_ERRIN2, + input TX_ERRIN3, + input [3:0] TX_MTYIN0, + input [3:0] TX_MTYIN1, + input [3:0] TX_MTYIN2, + input [3:0] TX_MTYIN3, + input TX_RESET, + input TX_SERDES_REFCLK, + input TX_SERDES_REFCLK_RESET, + input TX_SOPIN0, + input TX_SOPIN1, + input TX_SOPIN2, + input TX_SOPIN3 +); + +// define constants + localparam MODULE_NAME = "ILKNE4"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "ILKNE4_dr.v" +`else + reg [40:1] BYPASS_REG = BYPASS; + reg [1:0] CTL_RX_BURSTMAX_REG = CTL_RX_BURSTMAX; + reg [1:0] CTL_RX_CHAN_EXT_REG = CTL_RX_CHAN_EXT; + reg [3:0] CTL_RX_LAST_LANE_REG = CTL_RX_LAST_LANE; + reg [15:0] CTL_RX_MFRAMELEN_MINUS1_REG = CTL_RX_MFRAMELEN_MINUS1; + reg [40:1] CTL_RX_PACKET_MODE_REG = CTL_RX_PACKET_MODE; + reg [2:0] CTL_RX_RETRANS_MULT_REG = CTL_RX_RETRANS_MULT; + reg [3:0] CTL_RX_RETRANS_RETRY_REG = CTL_RX_RETRANS_RETRY; + reg [15:0] CTL_RX_RETRANS_TIMER1_REG = CTL_RX_RETRANS_TIMER1; + reg [15:0] CTL_RX_RETRANS_TIMER2_REG = CTL_RX_RETRANS_TIMER2; + reg [11:0] CTL_RX_RETRANS_WDOG_REG = CTL_RX_RETRANS_WDOG; + reg [7:0] CTL_RX_RETRANS_WRAP_TIMER_REG = CTL_RX_RETRANS_WRAP_TIMER; + reg [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR; + reg [1:0] CTL_TX_BURSTMAX_REG = CTL_TX_BURSTMAX; + reg [2:0] CTL_TX_BURSTSHORT_REG = CTL_TX_BURSTSHORT; + reg [1:0] CTL_TX_CHAN_EXT_REG = CTL_TX_CHAN_EXT; + reg [40:1] CTL_TX_DISABLE_SKIPWORD_REG = CTL_TX_DISABLE_SKIPWORD; + reg [3:0] CTL_TX_FC_CALLEN_REG = CTL_TX_FC_CALLEN; + reg [3:0] CTL_TX_LAST_LANE_REG = CTL_TX_LAST_LANE; + reg [15:0] CTL_TX_MFRAMELEN_MINUS1_REG = CTL_TX_MFRAMELEN_MINUS1; + reg [13:0] CTL_TX_RETRANS_DEPTH_REG = CTL_TX_RETRANS_DEPTH; + reg [2:0] CTL_TX_RETRANS_MULT_REG = CTL_TX_RETRANS_MULT; + reg [1:0] CTL_TX_RETRANS_RAM_BANKS_REG = CTL_TX_RETRANS_RAM_BANKS; + reg [40:1] MODE_REG = MODE; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR; +`endif + + reg [40:1] CTL_CSSD_EN_REG = "FALSE"; + reg [15:0] CTL_CSSD_MRKR_INIT_REG = 16'h0000; + reg [14:0] CTL_CSSD_ROOT_CLK_DIS_REG = 15'h0000; + reg [3:0] CTL_CSSD_ROOT_CLK_SEL_REG = 4'h0; + reg [40:1] CTL_CSSD_SNGL_CHAIN_MD_REG = "FALSE"; + reg [15:0] CTL_CSSD_STOP_COUNT_0_REG = 16'h0FFF; + reg [15:0] CTL_CSSD_STOP_COUNT_1_REG = 16'h0000; + reg [15:0] CTL_CSSD_STOP_COUNT_2_REG = 16'h0000; + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CFG_RESET_CSSD_out; + wire CSSD_CLK_STOP_DONE_out; + wire DRP_RDY_out; + wire GRESTORE_CSSD_out; + wire GWE_CSSD_out; + wire RX_ENAOUT0_out; + wire RX_ENAOUT1_out; + wire RX_ENAOUT2_out; + wire RX_ENAOUT3_out; + wire RX_EOPOUT0_out; + wire RX_EOPOUT1_out; + wire RX_EOPOUT2_out; + wire RX_EOPOUT3_out; + wire RX_ERROUT0_out; + wire RX_ERROUT1_out; + wire RX_ERROUT2_out; + wire RX_ERROUT3_out; + wire RX_OVFOUT_out; + wire RX_SOPOUT0_out; + wire RX_SOPOUT1_out; + wire RX_SOPOUT2_out; + wire RX_SOPOUT3_out; + wire STAT_RX_ALIGNED_ERR_out; + wire STAT_RX_ALIGNED_out; + wire STAT_RX_BURSTMAX_ERR_out; + wire STAT_RX_BURST_ERR_out; + wire STAT_RX_CRC24_ERR_out; + wire STAT_RX_MEOP_ERR_out; + wire STAT_RX_MISALIGNED_out; + wire STAT_RX_MSOP_ERR_out; + wire STAT_RX_MUBITS_UPDATED_out; + wire STAT_RX_OVERFLOW_ERR_out; + wire STAT_RX_RETRANS_CRC24_ERR_out; + wire STAT_RX_RETRANS_DISC_out; + wire STAT_RX_RETRANS_REQ_out; + wire STAT_RX_RETRANS_RETRY_ERR_out; + wire STAT_RX_RETRANS_SEQ_UPDATED_out; + wire STAT_RX_RETRANS_WDOG_ERR_out; + wire STAT_RX_RETRANS_WRAP_ERR_out; + wire STAT_TX_BURST_ERR_out; + wire STAT_TX_ERRINJ_BITERR_DONE_out; + wire STAT_TX_OVERFLOW_ERR_out; + wire STAT_TX_RETRANS_BURST_ERR_out; + wire STAT_TX_RETRANS_BUSY_out; + wire STAT_TX_RETRANS_RAM_PERROUT_out; + wire STAT_TX_RETRANS_RAM_RD_B0_out; + wire STAT_TX_RETRANS_RAM_RD_B1_out; + wire STAT_TX_RETRANS_RAM_RD_B2_out; + wire STAT_TX_RETRANS_RAM_RD_B3_out; + wire STAT_TX_RETRANS_RAM_WE_B0_out; + wire STAT_TX_RETRANS_RAM_WE_B1_out; + wire STAT_TX_RETRANS_RAM_WE_B2_out; + wire STAT_TX_RETRANS_RAM_WE_B3_out; + wire STAT_TX_UNDERFLOW_ERR_out; + wire TX_OVFOUT_out; + wire TX_RDYOUT_out; + wire [10:0] RX_CHANOUT0_out; + wire [10:0] RX_CHANOUT1_out; + wire [10:0] RX_CHANOUT2_out; + wire [10:0] RX_CHANOUT3_out; + wire [11:0] RX_BYPASS_ENAOUT_out; + wire [11:0] RX_BYPASS_IS_AVAILOUT_out; + wire [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT_out; + wire [11:0] RX_BYPASS_IS_OVERFLOWOUT_out; + wire [11:0] RX_BYPASS_IS_SYNCEDOUT_out; + wire [11:0] RX_BYPASS_IS_SYNCWORDOUT_out; + wire [11:0] STAT_RX_BAD_TYPE_ERR_out; + wire [11:0] STAT_RX_CRC32_ERR_out; + wire [11:0] STAT_RX_CRC32_VALID_out; + wire [11:0] STAT_RX_DESCRAM_ERR_out; + wire [11:0] STAT_RX_DIAGWORD_INTFSTAT_out; + wire [11:0] STAT_RX_DIAGWORD_LANESTAT_out; + wire [11:0] STAT_RX_FRAMING_ERR_out; + wire [11:0] STAT_RX_MF_ERR_out; + wire [11:0] STAT_RX_MF_LEN_ERR_out; + wire [11:0] STAT_RX_MF_REPEAT_ERR_out; + wire [11:0] STAT_RX_SYNCED_ERR_out; + wire [11:0] STAT_RX_SYNCED_out; + wire [11:0] STAT_RX_WORD_SYNC_out; + wire [127:0] RX_DATAOUT0_out; + wire [127:0] RX_DATAOUT1_out; + wire [127:0] RX_DATAOUT2_out; + wire [127:0] RX_DATAOUT3_out; + wire [15:0] DRP_DO_out; + wire [15:0] STAT_RX_RETRANS_LATENCY_out; + wire [1:0] STAT_TX_RETRANS_RAM_RSEL_out; + wire [255:0] STAT_RX_FC_STAT_out; + wire [264:0] SCAN_OUT_out; + wire [2:0] STAT_RX_RETRANS_STATE_out; + wire [3:0] RX_MTYOUT0_out; + wire [3:0] RX_MTYOUT1_out; + wire [3:0] RX_MTYOUT2_out; + wire [3:0] RX_MTYOUT3_out; + wire [4:0] STAT_RX_RETRANS_SUBSEQ_out; + wire [63:0] TX_SERDES_DATA00_out; + wire [63:0] TX_SERDES_DATA01_out; + wire [63:0] TX_SERDES_DATA02_out; + wire [63:0] TX_SERDES_DATA03_out; + wire [63:0] TX_SERDES_DATA04_out; + wire [63:0] TX_SERDES_DATA05_out; + wire [63:0] TX_SERDES_DATA06_out; + wire [63:0] TX_SERDES_DATA07_out; + wire [63:0] TX_SERDES_DATA08_out; + wire [63:0] TX_SERDES_DATA09_out; + wire [63:0] TX_SERDES_DATA10_out; + wire [63:0] TX_SERDES_DATA11_out; + wire [643:0] STAT_TX_RETRANS_RAM_WDATA_out; + wire [65:0] RX_BYPASS_DATAOUT00_out; + wire [65:0] RX_BYPASS_DATAOUT01_out; + wire [65:0] RX_BYPASS_DATAOUT02_out; + wire [65:0] RX_BYPASS_DATAOUT03_out; + wire [65:0] RX_BYPASS_DATAOUT04_out; + wire [65:0] RX_BYPASS_DATAOUT05_out; + wire [65:0] RX_BYPASS_DATAOUT06_out; + wire [65:0] RX_BYPASS_DATAOUT07_out; + wire [65:0] RX_BYPASS_DATAOUT08_out; + wire [65:0] RX_BYPASS_DATAOUT09_out; + wire [65:0] RX_BYPASS_DATAOUT10_out; + wire [65:0] RX_BYPASS_DATAOUT11_out; + wire [7:0] STAT_RX_MUBITS_out; + wire [7:0] STAT_RX_RETRANS_SEQ_out; + wire [8:0] STAT_TX_RETRANS_RAM_RADDR_out; + wire [8:0] STAT_TX_RETRANS_RAM_WADDR_out; + + wire CORE_CLK_in; + wire CSSD_CLK_STOP_EVENT_in; + wire CSSD_RESETN_in; + wire CTL_RX_FORCE_RESYNC_in; + wire CTL_RX_RETRANS_ACK_in; + wire CTL_RX_RETRANS_ENABLE_in; + wire CTL_RX_RETRANS_ERRIN_in; + wire CTL_RX_RETRANS_FORCE_REQ_in; + wire CTL_RX_RETRANS_RESET_MODE_in; + wire CTL_RX_RETRANS_RESET_in; + wire CTL_TX_DIAGWORD_INTFSTAT_in; + wire CTL_TX_ENABLE_in; + wire CTL_TX_ERRINJ_BITERR_GO_in; + wire CTL_TX_RETRANS_ENABLE_in; + wire CTL_TX_RETRANS_RAM_PERRIN_in; + wire CTL_TX_RETRANS_REQ_VALID_in; + wire CTL_TX_RETRANS_REQ_in; + wire CTL_TX_RLIM_ENABLE_in; + wire DRP_CLK_in; + wire DRP_EN_in; + wire DRP_WE_in; + wire LBUS_CLK_in; + wire RX_BYPASS_FORCE_REALIGNIN_in; + wire RX_BYPASS_RDIN_in; + wire RX_RESET_in; + wire SCAN_CLK_in; + wire SCAN_EN_N_in; + wire TEST_MODE_N_in; + wire TEST_RESET_in; + wire TX_BCTLIN0_in; + wire TX_BCTLIN1_in; + wire TX_BCTLIN2_in; + wire TX_BCTLIN3_in; + wire TX_BYPASS_ENAIN_in; + wire TX_ENAIN0_in; + wire TX_ENAIN1_in; + wire TX_ENAIN2_in; + wire TX_ENAIN3_in; + wire TX_EOPIN0_in; + wire TX_EOPIN1_in; + wire TX_EOPIN2_in; + wire TX_EOPIN3_in; + wire TX_ERRIN0_in; + wire TX_ERRIN1_in; + wire TX_ERRIN2_in; + wire TX_ERRIN3_in; + wire TX_RESET_in; + wire TX_SERDES_REFCLK_RESET_in; + wire TX_SERDES_REFCLK_in; + wire TX_SOPIN0_in; + wire TX_SOPIN1_in; + wire TX_SOPIN2_in; + wire TX_SOPIN3_in; + wire [10:0] TX_CHANIN0_in; + wire [10:0] TX_CHANIN1_in; + wire [10:0] TX_CHANIN2_in; + wire [10:0] TX_CHANIN3_in; + wire [11:0] CTL_TX_DIAGWORD_LANESTAT_in; + wire [11:0] CTL_TX_RLIM_DELTA_in; + wire [11:0] CTL_TX_RLIM_MAX_in; + wire [11:0] RX_SERDES_CLK_in; + wire [11:0] RX_SERDES_RESET_in; + wire [11:0] TX_BYPASS_CTRLIN_in; + wire [127:0] TX_DATAIN0_in; + wire [127:0] TX_DATAIN1_in; + wire [127:0] TX_DATAIN2_in; + wire [127:0] TX_DATAIN3_in; + wire [15:0] DRP_DI_in; + wire [255:0] CTL_TX_FC_STAT_in; + wire [264:0] SCAN_IN_in; + wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_in; + wire [3:0] TX_BYPASS_MFRAMER_STATEIN_in; + wire [3:0] TX_MTYIN0_in; + wire [3:0] TX_MTYIN1_in; + wire [3:0] TX_MTYIN2_in; + wire [3:0] TX_MTYIN3_in; + wire [63:0] RX_SERDES_DATA00_in; + wire [63:0] RX_SERDES_DATA01_in; + wire [63:0] RX_SERDES_DATA02_in; + wire [63:0] RX_SERDES_DATA03_in; + wire [63:0] RX_SERDES_DATA04_in; + wire [63:0] RX_SERDES_DATA05_in; + wire [63:0] RX_SERDES_DATA06_in; + wire [63:0] RX_SERDES_DATA07_in; + wire [63:0] RX_SERDES_DATA08_in; + wire [63:0] RX_SERDES_DATA09_in; + wire [63:0] RX_SERDES_DATA10_in; + wire [63:0] RX_SERDES_DATA11_in; + wire [63:0] TX_BYPASS_DATAIN00_in; + wire [63:0] TX_BYPASS_DATAIN01_in; + wire [63:0] TX_BYPASS_DATAIN02_in; + wire [63:0] TX_BYPASS_DATAIN03_in; + wire [63:0] TX_BYPASS_DATAIN04_in; + wire [63:0] TX_BYPASS_DATAIN05_in; + wire [63:0] TX_BYPASS_DATAIN06_in; + wire [63:0] TX_BYPASS_DATAIN07_in; + wire [63:0] TX_BYPASS_DATAIN08_in; + wire [63:0] TX_BYPASS_DATAIN09_in; + wire [63:0] TX_BYPASS_DATAIN10_in; + wire [63:0] TX_BYPASS_DATAIN11_in; + wire [643:0] CTL_TX_RETRANS_RAM_RDATA_in; + wire [7:0] CTL_TX_MUBITS_in; + wire [7:0] CTL_TX_RLIM_INTV_in; + wire [7:0] TX_BYPASS_GEARBOX_SEQIN_in; + wire [9:0] DRP_ADDR_in; + +`ifdef XIL_TIMING + wire CORE_CLK_delay; + wire CTL_RX_FORCE_RESYNC_delay; + wire CTL_RX_RETRANS_ACK_delay; + wire CTL_RX_RETRANS_ENABLE_delay; + wire CTL_RX_RETRANS_ERRIN_delay; + wire CTL_RX_RETRANS_FORCE_REQ_delay; + wire CTL_RX_RETRANS_RESET_MODE_delay; + wire CTL_RX_RETRANS_RESET_delay; + wire CTL_TX_DIAGWORD_INTFSTAT_delay; + wire CTL_TX_ENABLE_delay; + wire CTL_TX_ERRINJ_BITERR_GO_delay; + wire CTL_TX_RETRANS_ENABLE_delay; + wire CTL_TX_RETRANS_RAM_PERRIN_delay; + wire CTL_TX_RETRANS_REQ_VALID_delay; + wire CTL_TX_RETRANS_REQ_delay; + wire CTL_TX_RLIM_ENABLE_delay; + wire DRP_CLK_delay; + wire DRP_EN_delay; + wire DRP_WE_delay; + wire LBUS_CLK_delay; + wire RX_BYPASS_FORCE_REALIGNIN_delay; + wire RX_BYPASS_RDIN_delay; + wire RX_RESET_delay; + wire TX_BCTLIN0_delay; + wire TX_BCTLIN1_delay; + wire TX_BCTLIN2_delay; + wire TX_BCTLIN3_delay; + wire TX_BYPASS_ENAIN_delay; + wire TX_ENAIN0_delay; + wire TX_ENAIN1_delay; + wire TX_ENAIN2_delay; + wire TX_ENAIN3_delay; + wire TX_EOPIN0_delay; + wire TX_EOPIN1_delay; + wire TX_EOPIN2_delay; + wire TX_EOPIN3_delay; + wire TX_ERRIN0_delay; + wire TX_ERRIN1_delay; + wire TX_ERRIN2_delay; + wire TX_ERRIN3_delay; + wire TX_RESET_delay; + wire TX_SERDES_REFCLK_RESET_delay; + wire TX_SERDES_REFCLK_delay; + wire TX_SOPIN0_delay; + wire TX_SOPIN1_delay; + wire TX_SOPIN2_delay; + wire TX_SOPIN3_delay; + wire [10:0] TX_CHANIN0_delay; + wire [10:0] TX_CHANIN1_delay; + wire [10:0] TX_CHANIN2_delay; + wire [10:0] TX_CHANIN3_delay; + wire [11:0] CTL_TX_DIAGWORD_LANESTAT_delay; + wire [11:0] CTL_TX_RLIM_DELTA_delay; + wire [11:0] CTL_TX_RLIM_MAX_delay; + wire [11:0] RX_SERDES_CLK_delay; + wire [11:0] RX_SERDES_RESET_delay; + wire [11:0] TX_BYPASS_CTRLIN_delay; + wire [127:0] TX_DATAIN0_delay; + wire [127:0] TX_DATAIN1_delay; + wire [127:0] TX_DATAIN2_delay; + wire [127:0] TX_DATAIN3_delay; + wire [15:0] DRP_DI_delay; + wire [255:0] CTL_TX_FC_STAT_delay; + wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_delay; + wire [3:0] TX_BYPASS_MFRAMER_STATEIN_delay; + wire [3:0] TX_MTYIN0_delay; + wire [3:0] TX_MTYIN1_delay; + wire [3:0] TX_MTYIN2_delay; + wire [3:0] TX_MTYIN3_delay; + wire [63:0] RX_SERDES_DATA00_delay; + wire [63:0] RX_SERDES_DATA01_delay; + wire [63:0] RX_SERDES_DATA02_delay; + wire [63:0] RX_SERDES_DATA03_delay; + wire [63:0] RX_SERDES_DATA04_delay; + wire [63:0] RX_SERDES_DATA05_delay; + wire [63:0] RX_SERDES_DATA06_delay; + wire [63:0] RX_SERDES_DATA07_delay; + wire [63:0] RX_SERDES_DATA08_delay; + wire [63:0] RX_SERDES_DATA09_delay; + wire [63:0] RX_SERDES_DATA10_delay; + wire [63:0] RX_SERDES_DATA11_delay; + wire [63:0] TX_BYPASS_DATAIN00_delay; + wire [63:0] TX_BYPASS_DATAIN01_delay; + wire [63:0] TX_BYPASS_DATAIN02_delay; + wire [63:0] TX_BYPASS_DATAIN03_delay; + wire [63:0] TX_BYPASS_DATAIN04_delay; + wire [63:0] TX_BYPASS_DATAIN05_delay; + wire [63:0] TX_BYPASS_DATAIN06_delay; + wire [63:0] TX_BYPASS_DATAIN07_delay; + wire [63:0] TX_BYPASS_DATAIN08_delay; + wire [63:0] TX_BYPASS_DATAIN09_delay; + wire [63:0] TX_BYPASS_DATAIN10_delay; + wire [63:0] TX_BYPASS_DATAIN11_delay; + wire [643:0] CTL_TX_RETRANS_RAM_RDATA_delay; + wire [7:0] CTL_TX_MUBITS_delay; + wire [7:0] CTL_TX_RLIM_INTV_delay; + wire [7:0] TX_BYPASS_GEARBOX_SEQIN_delay; + wire [9:0] DRP_ADDR_delay; +`endif + + assign DRP_DO = DRP_DO_out; + assign DRP_RDY = DRP_RDY_out; + assign RX_BYPASS_DATAOUT00 = RX_BYPASS_DATAOUT00_out; + assign RX_BYPASS_DATAOUT01 = RX_BYPASS_DATAOUT01_out; + assign RX_BYPASS_DATAOUT02 = RX_BYPASS_DATAOUT02_out; + assign RX_BYPASS_DATAOUT03 = RX_BYPASS_DATAOUT03_out; + assign RX_BYPASS_DATAOUT04 = RX_BYPASS_DATAOUT04_out; + assign RX_BYPASS_DATAOUT05 = RX_BYPASS_DATAOUT05_out; + assign RX_BYPASS_DATAOUT06 = RX_BYPASS_DATAOUT06_out; + assign RX_BYPASS_DATAOUT07 = RX_BYPASS_DATAOUT07_out; + assign RX_BYPASS_DATAOUT08 = RX_BYPASS_DATAOUT08_out; + assign RX_BYPASS_DATAOUT09 = RX_BYPASS_DATAOUT09_out; + assign RX_BYPASS_DATAOUT10 = RX_BYPASS_DATAOUT10_out; + assign RX_BYPASS_DATAOUT11 = RX_BYPASS_DATAOUT11_out; + assign RX_BYPASS_ENAOUT = RX_BYPASS_ENAOUT_out; + assign RX_BYPASS_IS_AVAILOUT = RX_BYPASS_IS_AVAILOUT_out; + assign RX_BYPASS_IS_BADLYFRAMEDOUT = RX_BYPASS_IS_BADLYFRAMEDOUT_out; + assign RX_BYPASS_IS_OVERFLOWOUT = RX_BYPASS_IS_OVERFLOWOUT_out; + assign RX_BYPASS_IS_SYNCEDOUT = RX_BYPASS_IS_SYNCEDOUT_out; + assign RX_BYPASS_IS_SYNCWORDOUT = RX_BYPASS_IS_SYNCWORDOUT_out; + assign RX_CHANOUT0 = RX_CHANOUT0_out; + assign RX_CHANOUT1 = RX_CHANOUT1_out; + assign RX_CHANOUT2 = RX_CHANOUT2_out; + assign RX_CHANOUT3 = RX_CHANOUT3_out; + assign RX_DATAOUT0 = RX_DATAOUT0_out; + assign RX_DATAOUT1 = RX_DATAOUT1_out; + assign RX_DATAOUT2 = RX_DATAOUT2_out; + assign RX_DATAOUT3 = RX_DATAOUT3_out; + assign RX_ENAOUT0 = RX_ENAOUT0_out; + assign RX_ENAOUT1 = RX_ENAOUT1_out; + assign RX_ENAOUT2 = RX_ENAOUT2_out; + assign RX_ENAOUT3 = RX_ENAOUT3_out; + assign RX_EOPOUT0 = RX_EOPOUT0_out; + assign RX_EOPOUT1 = RX_EOPOUT1_out; + assign RX_EOPOUT2 = RX_EOPOUT2_out; + assign RX_EOPOUT3 = RX_EOPOUT3_out; + assign RX_ERROUT0 = RX_ERROUT0_out; + assign RX_ERROUT1 = RX_ERROUT1_out; + assign RX_ERROUT2 = RX_ERROUT2_out; + assign RX_ERROUT3 = RX_ERROUT3_out; + assign RX_MTYOUT0 = RX_MTYOUT0_out; + assign RX_MTYOUT1 = RX_MTYOUT1_out; + assign RX_MTYOUT2 = RX_MTYOUT2_out; + assign RX_MTYOUT3 = RX_MTYOUT3_out; + assign RX_OVFOUT = RX_OVFOUT_out; + assign RX_SOPOUT0 = RX_SOPOUT0_out; + assign RX_SOPOUT1 = RX_SOPOUT1_out; + assign RX_SOPOUT2 = RX_SOPOUT2_out; + assign RX_SOPOUT3 = RX_SOPOUT3_out; + assign STAT_RX_ALIGNED = STAT_RX_ALIGNED_out; + assign STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_out; + assign STAT_RX_BAD_TYPE_ERR = STAT_RX_BAD_TYPE_ERR_out; + assign STAT_RX_BURSTMAX_ERR = STAT_RX_BURSTMAX_ERR_out; + assign STAT_RX_BURST_ERR = STAT_RX_BURST_ERR_out; + assign STAT_RX_CRC24_ERR = STAT_RX_CRC24_ERR_out; + assign STAT_RX_CRC32_ERR = STAT_RX_CRC32_ERR_out; + assign STAT_RX_CRC32_VALID = STAT_RX_CRC32_VALID_out; + assign STAT_RX_DESCRAM_ERR = STAT_RX_DESCRAM_ERR_out; + assign STAT_RX_DIAGWORD_INTFSTAT = STAT_RX_DIAGWORD_INTFSTAT_out; + assign STAT_RX_DIAGWORD_LANESTAT = STAT_RX_DIAGWORD_LANESTAT_out; + assign STAT_RX_FC_STAT = STAT_RX_FC_STAT_out; + assign STAT_RX_FRAMING_ERR = STAT_RX_FRAMING_ERR_out; + assign STAT_RX_MEOP_ERR = STAT_RX_MEOP_ERR_out; + assign STAT_RX_MF_ERR = STAT_RX_MF_ERR_out; + assign STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_out; + assign STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_out; + assign STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_out; + assign STAT_RX_MSOP_ERR = STAT_RX_MSOP_ERR_out; + assign STAT_RX_MUBITS = STAT_RX_MUBITS_out; + assign STAT_RX_MUBITS_UPDATED = STAT_RX_MUBITS_UPDATED_out; + assign STAT_RX_OVERFLOW_ERR = STAT_RX_OVERFLOW_ERR_out; + assign STAT_RX_RETRANS_CRC24_ERR = STAT_RX_RETRANS_CRC24_ERR_out; + assign STAT_RX_RETRANS_DISC = STAT_RX_RETRANS_DISC_out; + assign STAT_RX_RETRANS_LATENCY = STAT_RX_RETRANS_LATENCY_out; + assign STAT_RX_RETRANS_REQ = STAT_RX_RETRANS_REQ_out; + assign STAT_RX_RETRANS_RETRY_ERR = STAT_RX_RETRANS_RETRY_ERR_out; + assign STAT_RX_RETRANS_SEQ = STAT_RX_RETRANS_SEQ_out; + assign STAT_RX_RETRANS_SEQ_UPDATED = STAT_RX_RETRANS_SEQ_UPDATED_out; + assign STAT_RX_RETRANS_STATE = STAT_RX_RETRANS_STATE_out; + assign STAT_RX_RETRANS_SUBSEQ = STAT_RX_RETRANS_SUBSEQ_out; + assign STAT_RX_RETRANS_WDOG_ERR = STAT_RX_RETRANS_WDOG_ERR_out; + assign STAT_RX_RETRANS_WRAP_ERR = STAT_RX_RETRANS_WRAP_ERR_out; + assign STAT_RX_SYNCED = STAT_RX_SYNCED_out; + assign STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_out; + assign STAT_RX_WORD_SYNC = STAT_RX_WORD_SYNC_out; + assign STAT_TX_BURST_ERR = STAT_TX_BURST_ERR_out; + assign STAT_TX_ERRINJ_BITERR_DONE = STAT_TX_ERRINJ_BITERR_DONE_out; + assign STAT_TX_OVERFLOW_ERR = STAT_TX_OVERFLOW_ERR_out; + assign STAT_TX_RETRANS_BURST_ERR = STAT_TX_RETRANS_BURST_ERR_out; + assign STAT_TX_RETRANS_BUSY = STAT_TX_RETRANS_BUSY_out; + assign STAT_TX_RETRANS_RAM_PERROUT = STAT_TX_RETRANS_RAM_PERROUT_out; + assign STAT_TX_RETRANS_RAM_RADDR = STAT_TX_RETRANS_RAM_RADDR_out; + assign STAT_TX_RETRANS_RAM_RD_B0 = STAT_TX_RETRANS_RAM_RD_B0_out; + assign STAT_TX_RETRANS_RAM_RD_B1 = STAT_TX_RETRANS_RAM_RD_B1_out; + assign STAT_TX_RETRANS_RAM_RD_B2 = STAT_TX_RETRANS_RAM_RD_B2_out; + assign STAT_TX_RETRANS_RAM_RD_B3 = STAT_TX_RETRANS_RAM_RD_B3_out; + assign STAT_TX_RETRANS_RAM_RSEL = STAT_TX_RETRANS_RAM_RSEL_out; + assign STAT_TX_RETRANS_RAM_WADDR = STAT_TX_RETRANS_RAM_WADDR_out; + assign STAT_TX_RETRANS_RAM_WDATA = STAT_TX_RETRANS_RAM_WDATA_out; + assign STAT_TX_RETRANS_RAM_WE_B0 = STAT_TX_RETRANS_RAM_WE_B0_out; + assign STAT_TX_RETRANS_RAM_WE_B1 = STAT_TX_RETRANS_RAM_WE_B1_out; + assign STAT_TX_RETRANS_RAM_WE_B2 = STAT_TX_RETRANS_RAM_WE_B2_out; + assign STAT_TX_RETRANS_RAM_WE_B3 = STAT_TX_RETRANS_RAM_WE_B3_out; + assign STAT_TX_UNDERFLOW_ERR = STAT_TX_UNDERFLOW_ERR_out; + assign TX_OVFOUT = TX_OVFOUT_out; + assign TX_RDYOUT = TX_RDYOUT_out; + assign TX_SERDES_DATA00 = TX_SERDES_DATA00_out; + assign TX_SERDES_DATA01 = TX_SERDES_DATA01_out; + assign TX_SERDES_DATA02 = TX_SERDES_DATA02_out; + assign TX_SERDES_DATA03 = TX_SERDES_DATA03_out; + assign TX_SERDES_DATA04 = TX_SERDES_DATA04_out; + assign TX_SERDES_DATA05 = TX_SERDES_DATA05_out; + assign TX_SERDES_DATA06 = TX_SERDES_DATA06_out; + assign TX_SERDES_DATA07 = TX_SERDES_DATA07_out; + assign TX_SERDES_DATA08 = TX_SERDES_DATA08_out; + assign TX_SERDES_DATA09 = TX_SERDES_DATA09_out; + assign TX_SERDES_DATA10 = TX_SERDES_DATA10_out; + assign TX_SERDES_DATA11 = TX_SERDES_DATA11_out; + +`ifdef XIL_TIMING + assign CORE_CLK_in = CORE_CLK_delay; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay; + assign CTL_RX_RETRANS_ACK_in = CTL_RX_RETRANS_ACK_delay; + assign CTL_RX_RETRANS_ENABLE_in = CTL_RX_RETRANS_ENABLE_delay; + assign CTL_RX_RETRANS_ERRIN_in = CTL_RX_RETRANS_ERRIN_delay; + assign CTL_RX_RETRANS_FORCE_REQ_in = CTL_RX_RETRANS_FORCE_REQ_delay; + assign CTL_RX_RETRANS_RESET_MODE_in = CTL_RX_RETRANS_RESET_MODE_delay; + assign CTL_RX_RETRANS_RESET_in = CTL_RX_RETRANS_RESET_delay; + assign CTL_TX_DIAGWORD_INTFSTAT_in = CTL_TX_DIAGWORD_INTFSTAT_delay; + assign CTL_TX_DIAGWORD_LANESTAT_in = CTL_TX_DIAGWORD_LANESTAT_delay; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay; + assign CTL_TX_ERRINJ_BITERR_GO_in = CTL_TX_ERRINJ_BITERR_GO_delay; + assign CTL_TX_ERRINJ_BITERR_LANE_in = CTL_TX_ERRINJ_BITERR_LANE_delay; + assign CTL_TX_FC_STAT_in = CTL_TX_FC_STAT_delay; + assign CTL_TX_MUBITS_in = CTL_TX_MUBITS_delay; + assign CTL_TX_RETRANS_ENABLE_in = CTL_TX_RETRANS_ENABLE_delay; + assign CTL_TX_RETRANS_RAM_PERRIN_in = CTL_TX_RETRANS_RAM_PERRIN_delay; + assign CTL_TX_RETRANS_RAM_RDATA_in = CTL_TX_RETRANS_RAM_RDATA_delay; + assign CTL_TX_RETRANS_REQ_VALID_in = CTL_TX_RETRANS_REQ_VALID_delay; + assign CTL_TX_RETRANS_REQ_in = CTL_TX_RETRANS_REQ_delay; + assign CTL_TX_RLIM_DELTA_in = CTL_TX_RLIM_DELTA_delay; + assign CTL_TX_RLIM_ENABLE_in = CTL_TX_RLIM_ENABLE_delay; + assign CTL_TX_RLIM_INTV_in = CTL_TX_RLIM_INTV_delay; + assign CTL_TX_RLIM_MAX_in = CTL_TX_RLIM_MAX_delay; + assign DRP_ADDR_in = DRP_ADDR_delay; + assign DRP_CLK_in = DRP_CLK_delay; + assign DRP_DI_in = DRP_DI_delay; + assign DRP_EN_in = DRP_EN_delay; + assign DRP_WE_in = DRP_WE_delay; + assign LBUS_CLK_in = LBUS_CLK_delay; + assign RX_BYPASS_FORCE_REALIGNIN_in = RX_BYPASS_FORCE_REALIGNIN_delay; + assign RX_BYPASS_RDIN_in = RX_BYPASS_RDIN_delay; + assign RX_RESET_in = RX_RESET_delay; + assign RX_SERDES_CLK_in[0] = RX_SERDES_CLK_delay[0]; + assign RX_SERDES_CLK_in[10] = RX_SERDES_CLK_delay[10]; + assign RX_SERDES_CLK_in[11] = RX_SERDES_CLK_delay[11]; + assign RX_SERDES_CLK_in[1] = RX_SERDES_CLK_delay[1]; + assign RX_SERDES_CLK_in[2] = RX_SERDES_CLK_delay[2]; + assign RX_SERDES_CLK_in[3] = RX_SERDES_CLK_delay[3]; + assign RX_SERDES_CLK_in[4] = RX_SERDES_CLK_delay[4]; + assign RX_SERDES_CLK_in[5] = RX_SERDES_CLK_delay[5]; + assign RX_SERDES_CLK_in[6] = RX_SERDES_CLK_delay[6]; + assign RX_SERDES_CLK_in[7] = RX_SERDES_CLK_delay[7]; + assign RX_SERDES_CLK_in[8] = RX_SERDES_CLK_delay[8]; + assign RX_SERDES_CLK_in[9] = RX_SERDES_CLK_delay[9]; + assign RX_SERDES_DATA00_in = RX_SERDES_DATA00_delay; + assign RX_SERDES_DATA01_in = RX_SERDES_DATA01_delay; + assign RX_SERDES_DATA02_in = RX_SERDES_DATA02_delay; + assign RX_SERDES_DATA03_in = RX_SERDES_DATA03_delay; + assign RX_SERDES_DATA04_in = RX_SERDES_DATA04_delay; + assign RX_SERDES_DATA05_in = RX_SERDES_DATA05_delay; + assign RX_SERDES_DATA06_in = RX_SERDES_DATA06_delay; + assign RX_SERDES_DATA07_in = RX_SERDES_DATA07_delay; + assign RX_SERDES_DATA08_in = RX_SERDES_DATA08_delay; + assign RX_SERDES_DATA09_in = RX_SERDES_DATA09_delay; + assign RX_SERDES_DATA10_in = RX_SERDES_DATA10_delay; + assign RX_SERDES_DATA11_in = RX_SERDES_DATA11_delay; + assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay; + assign TX_BCTLIN0_in = TX_BCTLIN0_delay; + assign TX_BCTLIN1_in = TX_BCTLIN1_delay; + assign TX_BCTLIN2_in = TX_BCTLIN2_delay; + assign TX_BCTLIN3_in = TX_BCTLIN3_delay; + assign TX_BYPASS_CTRLIN_in = TX_BYPASS_CTRLIN_delay; + assign TX_BYPASS_DATAIN00_in = TX_BYPASS_DATAIN00_delay; + assign TX_BYPASS_DATAIN01_in = TX_BYPASS_DATAIN01_delay; + assign TX_BYPASS_DATAIN02_in = TX_BYPASS_DATAIN02_delay; + assign TX_BYPASS_DATAIN03_in = TX_BYPASS_DATAIN03_delay; + assign TX_BYPASS_DATAIN04_in = TX_BYPASS_DATAIN04_delay; + assign TX_BYPASS_DATAIN05_in = TX_BYPASS_DATAIN05_delay; + assign TX_BYPASS_DATAIN06_in = TX_BYPASS_DATAIN06_delay; + assign TX_BYPASS_DATAIN07_in = TX_BYPASS_DATAIN07_delay; + assign TX_BYPASS_DATAIN08_in = TX_BYPASS_DATAIN08_delay; + assign TX_BYPASS_DATAIN09_in = TX_BYPASS_DATAIN09_delay; + assign TX_BYPASS_DATAIN10_in = TX_BYPASS_DATAIN10_delay; + assign TX_BYPASS_DATAIN11_in = TX_BYPASS_DATAIN11_delay; + assign TX_BYPASS_ENAIN_in = TX_BYPASS_ENAIN_delay; + assign TX_BYPASS_GEARBOX_SEQIN_in = TX_BYPASS_GEARBOX_SEQIN_delay; + assign TX_BYPASS_MFRAMER_STATEIN_in = TX_BYPASS_MFRAMER_STATEIN_delay; + assign TX_CHANIN0_in = TX_CHANIN0_delay; + assign TX_CHANIN1_in = TX_CHANIN1_delay; + assign TX_CHANIN2_in = TX_CHANIN2_delay; + assign TX_CHANIN3_in = TX_CHANIN3_delay; + assign TX_DATAIN0_in = TX_DATAIN0_delay; + assign TX_DATAIN1_in = TX_DATAIN1_delay; + assign TX_DATAIN2_in = TX_DATAIN2_delay; + assign TX_DATAIN3_in = TX_DATAIN3_delay; + assign TX_ENAIN0_in = TX_ENAIN0_delay; + assign TX_ENAIN1_in = TX_ENAIN1_delay; + assign TX_ENAIN2_in = TX_ENAIN2_delay; + assign TX_ENAIN3_in = TX_ENAIN3_delay; + assign TX_EOPIN0_in = TX_EOPIN0_delay; + assign TX_EOPIN1_in = TX_EOPIN1_delay; + assign TX_EOPIN2_in = TX_EOPIN2_delay; + assign TX_EOPIN3_in = TX_EOPIN3_delay; + assign TX_ERRIN0_in = TX_ERRIN0_delay; + assign TX_ERRIN1_in = TX_ERRIN1_delay; + assign TX_ERRIN2_in = TX_ERRIN2_delay; + assign TX_ERRIN3_in = TX_ERRIN3_delay; + assign TX_MTYIN0_in = TX_MTYIN0_delay; + assign TX_MTYIN1_in = TX_MTYIN1_delay; + assign TX_MTYIN2_in = TX_MTYIN2_delay; + assign TX_MTYIN3_in = TX_MTYIN3_delay; + assign TX_RESET_in = TX_RESET_delay; + assign TX_SERDES_REFCLK_RESET_in = TX_SERDES_REFCLK_RESET_delay; + assign TX_SERDES_REFCLK_in = TX_SERDES_REFCLK_delay; + assign TX_SOPIN0_in = TX_SOPIN0_delay; + assign TX_SOPIN1_in = TX_SOPIN1_delay; + assign TX_SOPIN2_in = TX_SOPIN2_delay; + assign TX_SOPIN3_in = TX_SOPIN3_delay; +`else + assign CORE_CLK_in = CORE_CLK; + assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC; + assign CTL_RX_RETRANS_ACK_in = CTL_RX_RETRANS_ACK; + assign CTL_RX_RETRANS_ENABLE_in = CTL_RX_RETRANS_ENABLE; + assign CTL_RX_RETRANS_ERRIN_in = CTL_RX_RETRANS_ERRIN; + assign CTL_RX_RETRANS_FORCE_REQ_in = CTL_RX_RETRANS_FORCE_REQ; + assign CTL_RX_RETRANS_RESET_MODE_in = CTL_RX_RETRANS_RESET_MODE; + assign CTL_RX_RETRANS_RESET_in = CTL_RX_RETRANS_RESET; + assign CTL_TX_DIAGWORD_INTFSTAT_in = CTL_TX_DIAGWORD_INTFSTAT; + assign CTL_TX_DIAGWORD_LANESTAT_in = CTL_TX_DIAGWORD_LANESTAT; + assign CTL_TX_ENABLE_in = CTL_TX_ENABLE; + assign CTL_TX_ERRINJ_BITERR_GO_in = CTL_TX_ERRINJ_BITERR_GO; + assign CTL_TX_ERRINJ_BITERR_LANE_in = CTL_TX_ERRINJ_BITERR_LANE; + assign CTL_TX_FC_STAT_in = CTL_TX_FC_STAT; + assign CTL_TX_MUBITS_in = CTL_TX_MUBITS; + assign CTL_TX_RETRANS_ENABLE_in = CTL_TX_RETRANS_ENABLE; + assign CTL_TX_RETRANS_RAM_PERRIN_in = CTL_TX_RETRANS_RAM_PERRIN; + assign CTL_TX_RETRANS_RAM_RDATA_in = CTL_TX_RETRANS_RAM_RDATA; + assign CTL_TX_RETRANS_REQ_VALID_in = CTL_TX_RETRANS_REQ_VALID; + assign CTL_TX_RETRANS_REQ_in = CTL_TX_RETRANS_REQ; + assign CTL_TX_RLIM_DELTA_in = CTL_TX_RLIM_DELTA; + assign CTL_TX_RLIM_ENABLE_in = CTL_TX_RLIM_ENABLE; + assign CTL_TX_RLIM_INTV_in = CTL_TX_RLIM_INTV; + assign CTL_TX_RLIM_MAX_in = CTL_TX_RLIM_MAX; + assign DRP_ADDR_in = DRP_ADDR; + assign DRP_CLK_in = DRP_CLK; + assign DRP_DI_in = DRP_DI; + assign DRP_EN_in = DRP_EN; + assign DRP_WE_in = DRP_WE; + assign LBUS_CLK_in = LBUS_CLK; + assign RX_BYPASS_FORCE_REALIGNIN_in = RX_BYPASS_FORCE_REALIGNIN; + assign RX_BYPASS_RDIN_in = RX_BYPASS_RDIN; + assign RX_RESET_in = RX_RESET; + assign RX_SERDES_CLK_in[0] = RX_SERDES_CLK[0]; + assign RX_SERDES_CLK_in[10] = RX_SERDES_CLK[10]; + assign RX_SERDES_CLK_in[11] = RX_SERDES_CLK[11]; + assign RX_SERDES_CLK_in[1] = RX_SERDES_CLK[1]; + assign RX_SERDES_CLK_in[2] = RX_SERDES_CLK[2]; + assign RX_SERDES_CLK_in[3] = RX_SERDES_CLK[3]; + assign RX_SERDES_CLK_in[4] = RX_SERDES_CLK[4]; + assign RX_SERDES_CLK_in[5] = RX_SERDES_CLK[5]; + assign RX_SERDES_CLK_in[6] = RX_SERDES_CLK[6]; + assign RX_SERDES_CLK_in[7] = RX_SERDES_CLK[7]; + assign RX_SERDES_CLK_in[8] = RX_SERDES_CLK[8]; + assign RX_SERDES_CLK_in[9] = RX_SERDES_CLK[9]; + assign RX_SERDES_DATA00_in = RX_SERDES_DATA00; + assign RX_SERDES_DATA01_in = RX_SERDES_DATA01; + assign RX_SERDES_DATA02_in = RX_SERDES_DATA02; + assign RX_SERDES_DATA03_in = RX_SERDES_DATA03; + assign RX_SERDES_DATA04_in = RX_SERDES_DATA04; + assign RX_SERDES_DATA05_in = RX_SERDES_DATA05; + assign RX_SERDES_DATA06_in = RX_SERDES_DATA06; + assign RX_SERDES_DATA07_in = RX_SERDES_DATA07; + assign RX_SERDES_DATA08_in = RX_SERDES_DATA08; + assign RX_SERDES_DATA09_in = RX_SERDES_DATA09; + assign RX_SERDES_DATA10_in = RX_SERDES_DATA10; + assign RX_SERDES_DATA11_in = RX_SERDES_DATA11; + assign RX_SERDES_RESET_in = RX_SERDES_RESET; + assign TX_BCTLIN0_in = TX_BCTLIN0; + assign TX_BCTLIN1_in = TX_BCTLIN1; + assign TX_BCTLIN2_in = TX_BCTLIN2; + assign TX_BCTLIN3_in = TX_BCTLIN3; + assign TX_BYPASS_CTRLIN_in = TX_BYPASS_CTRLIN; + assign TX_BYPASS_DATAIN00_in = TX_BYPASS_DATAIN00; + assign TX_BYPASS_DATAIN01_in = TX_BYPASS_DATAIN01; + assign TX_BYPASS_DATAIN02_in = TX_BYPASS_DATAIN02; + assign TX_BYPASS_DATAIN03_in = TX_BYPASS_DATAIN03; + assign TX_BYPASS_DATAIN04_in = TX_BYPASS_DATAIN04; + assign TX_BYPASS_DATAIN05_in = TX_BYPASS_DATAIN05; + assign TX_BYPASS_DATAIN06_in = TX_BYPASS_DATAIN06; + assign TX_BYPASS_DATAIN07_in = TX_BYPASS_DATAIN07; + assign TX_BYPASS_DATAIN08_in = TX_BYPASS_DATAIN08; + assign TX_BYPASS_DATAIN09_in = TX_BYPASS_DATAIN09; + assign TX_BYPASS_DATAIN10_in = TX_BYPASS_DATAIN10; + assign TX_BYPASS_DATAIN11_in = TX_BYPASS_DATAIN11; + assign TX_BYPASS_ENAIN_in = TX_BYPASS_ENAIN; + assign TX_BYPASS_GEARBOX_SEQIN_in = TX_BYPASS_GEARBOX_SEQIN; + assign TX_BYPASS_MFRAMER_STATEIN_in = TX_BYPASS_MFRAMER_STATEIN; + assign TX_CHANIN0_in = TX_CHANIN0; + assign TX_CHANIN1_in = TX_CHANIN1; + assign TX_CHANIN2_in = TX_CHANIN2; + assign TX_CHANIN3_in = TX_CHANIN3; + assign TX_DATAIN0_in = TX_DATAIN0; + assign TX_DATAIN1_in = TX_DATAIN1; + assign TX_DATAIN2_in = TX_DATAIN2; + assign TX_DATAIN3_in = TX_DATAIN3; + assign TX_ENAIN0_in = TX_ENAIN0; + assign TX_ENAIN1_in = TX_ENAIN1; + assign TX_ENAIN2_in = TX_ENAIN2; + assign TX_ENAIN3_in = TX_ENAIN3; + assign TX_EOPIN0_in = TX_EOPIN0; + assign TX_EOPIN1_in = TX_EOPIN1; + assign TX_EOPIN2_in = TX_EOPIN2; + assign TX_EOPIN3_in = TX_EOPIN3; + assign TX_ERRIN0_in = TX_ERRIN0; + assign TX_ERRIN1_in = TX_ERRIN1; + assign TX_ERRIN2_in = TX_ERRIN2; + assign TX_ERRIN3_in = TX_ERRIN3; + assign TX_MTYIN0_in = TX_MTYIN0; + assign TX_MTYIN1_in = TX_MTYIN1; + assign TX_MTYIN2_in = TX_MTYIN2; + assign TX_MTYIN3_in = TX_MTYIN3; + assign TX_RESET_in = TX_RESET; + assign TX_SERDES_REFCLK_RESET_in = TX_SERDES_REFCLK_RESET; + assign TX_SERDES_REFCLK_in = TX_SERDES_REFCLK; + assign TX_SOPIN0_in = TX_SOPIN0; + assign TX_SOPIN1_in = TX_SOPIN1; + assign TX_SOPIN2_in = TX_SOPIN2; + assign TX_SOPIN3_in = TX_SOPIN3; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BYPASS_REG != "FALSE") && + (BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_LAST_LANE_REG < 4'h0) || (CTL_RX_LAST_LANE_REG > 4'hB))) begin + $display("Error: [Unisim %s-112] CTL_RX_LAST_LANE attribute is set to %h. Legal values for this attribute are 4'h0 to 4'hB. Instance: %m", MODULE_NAME, CTL_RX_LAST_LANE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_MFRAMELEN_MINUS1_REG < 16'h00FF) || (CTL_RX_MFRAMELEN_MINUS1_REG > 16'h1FFF))) begin + $display("Error: [Unisim %s-113] CTL_RX_MFRAMELEN_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h00FF to 16'h1FFF. Instance: %m", MODULE_NAME, CTL_RX_MFRAMELEN_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_PACKET_MODE_REG != "FALSE") && + (CTL_RX_PACKET_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] CTL_RX_PACKET_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_PACKET_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_RX_RETRANS_MULT_REG < 3'h0) || (CTL_RX_RETRANS_MULT_REG > 3'h5))) begin + $display("Error: [Unisim %s-115] CTL_RX_RETRANS_MULT attribute is set to %h. Legal values for this attribute are 3'h0 to 3'h5. Instance: %m", MODULE_NAME, CTL_RX_RETRANS_MULT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") && + (CTL_TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-121] CTL_TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_BURSTSHORT_REG < 3'h1) || (CTL_TX_BURSTSHORT_REG > 3'h7))) begin + $display("Error: [Unisim %s-123] CTL_TX_BURSTSHORT attribute is set to %h. Legal values for this attribute are 3'h1 to 3'h7. Instance: %m", MODULE_NAME, CTL_TX_BURSTSHORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_DISABLE_SKIPWORD_REG != "FALSE") && + (CTL_TX_DISABLE_SKIPWORD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] CTL_TX_DISABLE_SKIPWORD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_DISABLE_SKIPWORD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_LAST_LANE_REG < 4'h0) || (CTL_TX_LAST_LANE_REG > 4'hB))) begin + $display("Error: [Unisim %s-127] CTL_TX_LAST_LANE attribute is set to %h. Legal values for this attribute are 4'h0 to 4'hB. Instance: %m", MODULE_NAME, CTL_TX_LAST_LANE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_MFRAMELEN_MINUS1_REG < 16'h00FF) || (CTL_TX_MFRAMELEN_MINUS1_REG > 16'h1FFF))) begin + $display("Error: [Unisim %s-128] CTL_TX_MFRAMELEN_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h00FF to 16'h1FFF. Instance: %m", MODULE_NAME, CTL_TX_MFRAMELEN_MINUS1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_RETRANS_DEPTH_REG < 14'h0015) || (CTL_TX_RETRANS_DEPTH_REG > 14'h0800))) begin + $display("Error: [Unisim %s-129] CTL_TX_RETRANS_DEPTH attribute is set to %h. Legal values for this attribute are 14'h0015 to 14'h0800. Instance: %m", MODULE_NAME, CTL_TX_RETRANS_DEPTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CTL_TX_RETRANS_MULT_REG < 3'h0) || (CTL_TX_RETRANS_MULT_REG > 3'h5))) begin + $display("Error: [Unisim %s-130] CTL_TX_RETRANS_MULT attribute is set to %h. Legal values for this attribute are 3'h0 to 3'h5. Instance: %m", MODULE_NAME, CTL_TX_RETRANS_MULT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MODE_REG != "TRUE") && + (MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-132] MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-133] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TEST_MODE_PIN_CHAR_REG != "FALSE") && + (TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-134] TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TEST_MODE_PIN_CHAR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + + + +assign CSSD_CLK_STOP_EVENT_in = 1'b1; // tie off +assign CSSD_RESETN_in = 1'b1; // tie off +assign SCAN_CLK_in = 1'b1; // tie off +assign SCAN_EN_N_in = 1'b1; // tie off +assign SCAN_IN_in = 265'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off +assign TEST_MODE_N_in = 1'b1; // tie off +assign TEST_RESET_in = 1'b1; // tie off + + SIP_ILKNE4 SIP_ILKNE4_INST ( + .BYPASS (BYPASS_REG), + .CTL_CSSD_EN (CTL_CSSD_EN_REG), + .CTL_CSSD_MRKR_INIT (CTL_CSSD_MRKR_INIT_REG), + .CTL_CSSD_ROOT_CLK_DIS (CTL_CSSD_ROOT_CLK_DIS_REG), + .CTL_CSSD_ROOT_CLK_SEL (CTL_CSSD_ROOT_CLK_SEL_REG), + .CTL_CSSD_SNGL_CHAIN_MD (CTL_CSSD_SNGL_CHAIN_MD_REG), + .CTL_CSSD_STOP_COUNT_0 (CTL_CSSD_STOP_COUNT_0_REG), + .CTL_CSSD_STOP_COUNT_1 (CTL_CSSD_STOP_COUNT_1_REG), + .CTL_CSSD_STOP_COUNT_2 (CTL_CSSD_STOP_COUNT_2_REG), + .CTL_RX_BURSTMAX (CTL_RX_BURSTMAX_REG), + .CTL_RX_CHAN_EXT (CTL_RX_CHAN_EXT_REG), + .CTL_RX_LAST_LANE (CTL_RX_LAST_LANE_REG), + .CTL_RX_MFRAMELEN_MINUS1 (CTL_RX_MFRAMELEN_MINUS1_REG), + .CTL_RX_PACKET_MODE (CTL_RX_PACKET_MODE_REG), + .CTL_RX_RETRANS_MULT (CTL_RX_RETRANS_MULT_REG), + .CTL_RX_RETRANS_RETRY (CTL_RX_RETRANS_RETRY_REG), + .CTL_RX_RETRANS_TIMER1 (CTL_RX_RETRANS_TIMER1_REG), + .CTL_RX_RETRANS_TIMER2 (CTL_RX_RETRANS_TIMER2_REG), + .CTL_RX_RETRANS_WDOG (CTL_RX_RETRANS_WDOG_REG), + .CTL_RX_RETRANS_WRAP_TIMER (CTL_RX_RETRANS_WRAP_TIMER_REG), + .CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG), + .CTL_TX_BURSTMAX (CTL_TX_BURSTMAX_REG), + .CTL_TX_BURSTSHORT (CTL_TX_BURSTSHORT_REG), + .CTL_TX_CHAN_EXT (CTL_TX_CHAN_EXT_REG), + .CTL_TX_DISABLE_SKIPWORD (CTL_TX_DISABLE_SKIPWORD_REG), + .CTL_TX_FC_CALLEN (CTL_TX_FC_CALLEN_REG), + .CTL_TX_LAST_LANE (CTL_TX_LAST_LANE_REG), + .CTL_TX_MFRAMELEN_MINUS1 (CTL_TX_MFRAMELEN_MINUS1_REG), + .CTL_TX_RETRANS_DEPTH (CTL_TX_RETRANS_DEPTH_REG), + .CTL_TX_RETRANS_MULT (CTL_TX_RETRANS_MULT_REG), + .CTL_TX_RETRANS_RAM_BANKS (CTL_TX_RETRANS_RAM_BANKS_REG), + .MODE (MODE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .CFG_RESET_CSSD (CFG_RESET_CSSD_out), + .CSSD_CLK_STOP_DONE (CSSD_CLK_STOP_DONE_out), + .DRP_DO (DRP_DO_out), + .DRP_RDY (DRP_RDY_out), + .GRESTORE_CSSD (GRESTORE_CSSD_out), + .GWE_CSSD (GWE_CSSD_out), + .RX_BYPASS_DATAOUT00 (RX_BYPASS_DATAOUT00_out), + .RX_BYPASS_DATAOUT01 (RX_BYPASS_DATAOUT01_out), + .RX_BYPASS_DATAOUT02 (RX_BYPASS_DATAOUT02_out), + .RX_BYPASS_DATAOUT03 (RX_BYPASS_DATAOUT03_out), + .RX_BYPASS_DATAOUT04 (RX_BYPASS_DATAOUT04_out), + .RX_BYPASS_DATAOUT05 (RX_BYPASS_DATAOUT05_out), + .RX_BYPASS_DATAOUT06 (RX_BYPASS_DATAOUT06_out), + .RX_BYPASS_DATAOUT07 (RX_BYPASS_DATAOUT07_out), + .RX_BYPASS_DATAOUT08 (RX_BYPASS_DATAOUT08_out), + .RX_BYPASS_DATAOUT09 (RX_BYPASS_DATAOUT09_out), + .RX_BYPASS_DATAOUT10 (RX_BYPASS_DATAOUT10_out), + .RX_BYPASS_DATAOUT11 (RX_BYPASS_DATAOUT11_out), + .RX_BYPASS_ENAOUT (RX_BYPASS_ENAOUT_out), + .RX_BYPASS_IS_AVAILOUT (RX_BYPASS_IS_AVAILOUT_out), + .RX_BYPASS_IS_BADLYFRAMEDOUT (RX_BYPASS_IS_BADLYFRAMEDOUT_out), + .RX_BYPASS_IS_OVERFLOWOUT (RX_BYPASS_IS_OVERFLOWOUT_out), + .RX_BYPASS_IS_SYNCEDOUT (RX_BYPASS_IS_SYNCEDOUT_out), + .RX_BYPASS_IS_SYNCWORDOUT (RX_BYPASS_IS_SYNCWORDOUT_out), + .RX_CHANOUT0 (RX_CHANOUT0_out), + .RX_CHANOUT1 (RX_CHANOUT1_out), + .RX_CHANOUT2 (RX_CHANOUT2_out), + .RX_CHANOUT3 (RX_CHANOUT3_out), + .RX_DATAOUT0 (RX_DATAOUT0_out), + .RX_DATAOUT1 (RX_DATAOUT1_out), + .RX_DATAOUT2 (RX_DATAOUT2_out), + .RX_DATAOUT3 (RX_DATAOUT3_out), + .RX_ENAOUT0 (RX_ENAOUT0_out), + .RX_ENAOUT1 (RX_ENAOUT1_out), + .RX_ENAOUT2 (RX_ENAOUT2_out), + .RX_ENAOUT3 (RX_ENAOUT3_out), + .RX_EOPOUT0 (RX_EOPOUT0_out), + .RX_EOPOUT1 (RX_EOPOUT1_out), + .RX_EOPOUT2 (RX_EOPOUT2_out), + .RX_EOPOUT3 (RX_EOPOUT3_out), + .RX_ERROUT0 (RX_ERROUT0_out), + .RX_ERROUT1 (RX_ERROUT1_out), + .RX_ERROUT2 (RX_ERROUT2_out), + .RX_ERROUT3 (RX_ERROUT3_out), + .RX_MTYOUT0 (RX_MTYOUT0_out), + .RX_MTYOUT1 (RX_MTYOUT1_out), + .RX_MTYOUT2 (RX_MTYOUT2_out), + .RX_MTYOUT3 (RX_MTYOUT3_out), + .RX_OVFOUT (RX_OVFOUT_out), + .RX_SOPOUT0 (RX_SOPOUT0_out), + .RX_SOPOUT1 (RX_SOPOUT1_out), + .RX_SOPOUT2 (RX_SOPOUT2_out), + .RX_SOPOUT3 (RX_SOPOUT3_out), + .SCAN_OUT (SCAN_OUT_out), + .STAT_RX_ALIGNED (STAT_RX_ALIGNED_out), + .STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out), + .STAT_RX_BAD_TYPE_ERR (STAT_RX_BAD_TYPE_ERR_out), + .STAT_RX_BURSTMAX_ERR (STAT_RX_BURSTMAX_ERR_out), + .STAT_RX_BURST_ERR (STAT_RX_BURST_ERR_out), + .STAT_RX_CRC24_ERR (STAT_RX_CRC24_ERR_out), + .STAT_RX_CRC32_ERR (STAT_RX_CRC32_ERR_out), + .STAT_RX_CRC32_VALID (STAT_RX_CRC32_VALID_out), + .STAT_RX_DESCRAM_ERR (STAT_RX_DESCRAM_ERR_out), + .STAT_RX_DIAGWORD_INTFSTAT (STAT_RX_DIAGWORD_INTFSTAT_out), + .STAT_RX_DIAGWORD_LANESTAT (STAT_RX_DIAGWORD_LANESTAT_out), + .STAT_RX_FC_STAT (STAT_RX_FC_STAT_out), + .STAT_RX_FRAMING_ERR (STAT_RX_FRAMING_ERR_out), + .STAT_RX_MEOP_ERR (STAT_RX_MEOP_ERR_out), + .STAT_RX_MF_ERR (STAT_RX_MF_ERR_out), + .STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out), + .STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out), + .STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out), + .STAT_RX_MSOP_ERR (STAT_RX_MSOP_ERR_out), + .STAT_RX_MUBITS (STAT_RX_MUBITS_out), + .STAT_RX_MUBITS_UPDATED (STAT_RX_MUBITS_UPDATED_out), + .STAT_RX_OVERFLOW_ERR (STAT_RX_OVERFLOW_ERR_out), + .STAT_RX_RETRANS_CRC24_ERR (STAT_RX_RETRANS_CRC24_ERR_out), + .STAT_RX_RETRANS_DISC (STAT_RX_RETRANS_DISC_out), + .STAT_RX_RETRANS_LATENCY (STAT_RX_RETRANS_LATENCY_out), + .STAT_RX_RETRANS_REQ (STAT_RX_RETRANS_REQ_out), + .STAT_RX_RETRANS_RETRY_ERR (STAT_RX_RETRANS_RETRY_ERR_out), + .STAT_RX_RETRANS_SEQ (STAT_RX_RETRANS_SEQ_out), + .STAT_RX_RETRANS_SEQ_UPDATED (STAT_RX_RETRANS_SEQ_UPDATED_out), + .STAT_RX_RETRANS_STATE (STAT_RX_RETRANS_STATE_out), + .STAT_RX_RETRANS_SUBSEQ (STAT_RX_RETRANS_SUBSEQ_out), + .STAT_RX_RETRANS_WDOG_ERR (STAT_RX_RETRANS_WDOG_ERR_out), + .STAT_RX_RETRANS_WRAP_ERR (STAT_RX_RETRANS_WRAP_ERR_out), + .STAT_RX_SYNCED (STAT_RX_SYNCED_out), + .STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out), + .STAT_RX_WORD_SYNC (STAT_RX_WORD_SYNC_out), + .STAT_TX_BURST_ERR (STAT_TX_BURST_ERR_out), + .STAT_TX_ERRINJ_BITERR_DONE (STAT_TX_ERRINJ_BITERR_DONE_out), + .STAT_TX_OVERFLOW_ERR (STAT_TX_OVERFLOW_ERR_out), + .STAT_TX_RETRANS_BURST_ERR (STAT_TX_RETRANS_BURST_ERR_out), + .STAT_TX_RETRANS_BUSY (STAT_TX_RETRANS_BUSY_out), + .STAT_TX_RETRANS_RAM_PERROUT (STAT_TX_RETRANS_RAM_PERROUT_out), + .STAT_TX_RETRANS_RAM_RADDR (STAT_TX_RETRANS_RAM_RADDR_out), + .STAT_TX_RETRANS_RAM_RD_B0 (STAT_TX_RETRANS_RAM_RD_B0_out), + .STAT_TX_RETRANS_RAM_RD_B1 (STAT_TX_RETRANS_RAM_RD_B1_out), + .STAT_TX_RETRANS_RAM_RD_B2 (STAT_TX_RETRANS_RAM_RD_B2_out), + .STAT_TX_RETRANS_RAM_RD_B3 (STAT_TX_RETRANS_RAM_RD_B3_out), + .STAT_TX_RETRANS_RAM_RSEL (STAT_TX_RETRANS_RAM_RSEL_out), + .STAT_TX_RETRANS_RAM_WADDR (STAT_TX_RETRANS_RAM_WADDR_out), + .STAT_TX_RETRANS_RAM_WDATA (STAT_TX_RETRANS_RAM_WDATA_out), + .STAT_TX_RETRANS_RAM_WE_B0 (STAT_TX_RETRANS_RAM_WE_B0_out), + .STAT_TX_RETRANS_RAM_WE_B1 (STAT_TX_RETRANS_RAM_WE_B1_out), + .STAT_TX_RETRANS_RAM_WE_B2 (STAT_TX_RETRANS_RAM_WE_B2_out), + .STAT_TX_RETRANS_RAM_WE_B3 (STAT_TX_RETRANS_RAM_WE_B3_out), + .STAT_TX_UNDERFLOW_ERR (STAT_TX_UNDERFLOW_ERR_out), + .TX_OVFOUT (TX_OVFOUT_out), + .TX_RDYOUT (TX_RDYOUT_out), + .TX_SERDES_DATA00 (TX_SERDES_DATA00_out), + .TX_SERDES_DATA01 (TX_SERDES_DATA01_out), + .TX_SERDES_DATA02 (TX_SERDES_DATA02_out), + .TX_SERDES_DATA03 (TX_SERDES_DATA03_out), + .TX_SERDES_DATA04 (TX_SERDES_DATA04_out), + .TX_SERDES_DATA05 (TX_SERDES_DATA05_out), + .TX_SERDES_DATA06 (TX_SERDES_DATA06_out), + .TX_SERDES_DATA07 (TX_SERDES_DATA07_out), + .TX_SERDES_DATA08 (TX_SERDES_DATA08_out), + .TX_SERDES_DATA09 (TX_SERDES_DATA09_out), + .TX_SERDES_DATA10 (TX_SERDES_DATA10_out), + .TX_SERDES_DATA11 (TX_SERDES_DATA11_out), + .CORE_CLK (CORE_CLK_in), + .CSSD_CLK_STOP_EVENT (CSSD_CLK_STOP_EVENT_in), + .CSSD_RESETN (CSSD_RESETN_in), + .CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in), + .CTL_RX_RETRANS_ACK (CTL_RX_RETRANS_ACK_in), + .CTL_RX_RETRANS_ENABLE (CTL_RX_RETRANS_ENABLE_in), + .CTL_RX_RETRANS_ERRIN (CTL_RX_RETRANS_ERRIN_in), + .CTL_RX_RETRANS_FORCE_REQ (CTL_RX_RETRANS_FORCE_REQ_in), + .CTL_RX_RETRANS_RESET (CTL_RX_RETRANS_RESET_in), + .CTL_RX_RETRANS_RESET_MODE (CTL_RX_RETRANS_RESET_MODE_in), + .CTL_TX_DIAGWORD_INTFSTAT (CTL_TX_DIAGWORD_INTFSTAT_in), + .CTL_TX_DIAGWORD_LANESTAT (CTL_TX_DIAGWORD_LANESTAT_in), + .CTL_TX_ENABLE (CTL_TX_ENABLE_in), + .CTL_TX_ERRINJ_BITERR_GO (CTL_TX_ERRINJ_BITERR_GO_in), + .CTL_TX_ERRINJ_BITERR_LANE (CTL_TX_ERRINJ_BITERR_LANE_in), + .CTL_TX_FC_STAT (CTL_TX_FC_STAT_in), + .CTL_TX_MUBITS (CTL_TX_MUBITS_in), + .CTL_TX_RETRANS_ENABLE (CTL_TX_RETRANS_ENABLE_in), + .CTL_TX_RETRANS_RAM_PERRIN (CTL_TX_RETRANS_RAM_PERRIN_in), + .CTL_TX_RETRANS_RAM_RDATA (CTL_TX_RETRANS_RAM_RDATA_in), + .CTL_TX_RETRANS_REQ (CTL_TX_RETRANS_REQ_in), + .CTL_TX_RETRANS_REQ_VALID (CTL_TX_RETRANS_REQ_VALID_in), + .CTL_TX_RLIM_DELTA (CTL_TX_RLIM_DELTA_in), + .CTL_TX_RLIM_ENABLE (CTL_TX_RLIM_ENABLE_in), + .CTL_TX_RLIM_INTV (CTL_TX_RLIM_INTV_in), + .CTL_TX_RLIM_MAX (CTL_TX_RLIM_MAX_in), + .DRP_ADDR (DRP_ADDR_in), + .DRP_CLK (DRP_CLK_in), + .DRP_DI (DRP_DI_in), + .DRP_EN (DRP_EN_in), + .DRP_WE (DRP_WE_in), + .LBUS_CLK (LBUS_CLK_in), + .RX_BYPASS_FORCE_REALIGNIN (RX_BYPASS_FORCE_REALIGNIN_in), + .RX_BYPASS_RDIN (RX_BYPASS_RDIN_in), + .RX_RESET (RX_RESET_in), + .RX_SERDES_CLK (RX_SERDES_CLK_in), + .RX_SERDES_DATA00 (RX_SERDES_DATA00_in), + .RX_SERDES_DATA01 (RX_SERDES_DATA01_in), + .RX_SERDES_DATA02 (RX_SERDES_DATA02_in), + .RX_SERDES_DATA03 (RX_SERDES_DATA03_in), + .RX_SERDES_DATA04 (RX_SERDES_DATA04_in), + .RX_SERDES_DATA05 (RX_SERDES_DATA05_in), + .RX_SERDES_DATA06 (RX_SERDES_DATA06_in), + .RX_SERDES_DATA07 (RX_SERDES_DATA07_in), + .RX_SERDES_DATA08 (RX_SERDES_DATA08_in), + .RX_SERDES_DATA09 (RX_SERDES_DATA09_in), + .RX_SERDES_DATA10 (RX_SERDES_DATA10_in), + .RX_SERDES_DATA11 (RX_SERDES_DATA11_in), + .RX_SERDES_RESET (RX_SERDES_RESET_in), + .SCAN_CLK (SCAN_CLK_in), + .SCAN_EN_N (SCAN_EN_N_in), + .SCAN_IN (SCAN_IN_in), + .TEST_MODE_N (TEST_MODE_N_in), + .TEST_RESET (TEST_RESET_in), + .TX_BCTLIN0 (TX_BCTLIN0_in), + .TX_BCTLIN1 (TX_BCTLIN1_in), + .TX_BCTLIN2 (TX_BCTLIN2_in), + .TX_BCTLIN3 (TX_BCTLIN3_in), + .TX_BYPASS_CTRLIN (TX_BYPASS_CTRLIN_in), + .TX_BYPASS_DATAIN00 (TX_BYPASS_DATAIN00_in), + .TX_BYPASS_DATAIN01 (TX_BYPASS_DATAIN01_in), + .TX_BYPASS_DATAIN02 (TX_BYPASS_DATAIN02_in), + .TX_BYPASS_DATAIN03 (TX_BYPASS_DATAIN03_in), + .TX_BYPASS_DATAIN04 (TX_BYPASS_DATAIN04_in), + .TX_BYPASS_DATAIN05 (TX_BYPASS_DATAIN05_in), + .TX_BYPASS_DATAIN06 (TX_BYPASS_DATAIN06_in), + .TX_BYPASS_DATAIN07 (TX_BYPASS_DATAIN07_in), + .TX_BYPASS_DATAIN08 (TX_BYPASS_DATAIN08_in), + .TX_BYPASS_DATAIN09 (TX_BYPASS_DATAIN09_in), + .TX_BYPASS_DATAIN10 (TX_BYPASS_DATAIN10_in), + .TX_BYPASS_DATAIN11 (TX_BYPASS_DATAIN11_in), + .TX_BYPASS_ENAIN (TX_BYPASS_ENAIN_in), + .TX_BYPASS_GEARBOX_SEQIN (TX_BYPASS_GEARBOX_SEQIN_in), + .TX_BYPASS_MFRAMER_STATEIN (TX_BYPASS_MFRAMER_STATEIN_in), + .TX_CHANIN0 (TX_CHANIN0_in), + .TX_CHANIN1 (TX_CHANIN1_in), + .TX_CHANIN2 (TX_CHANIN2_in), + .TX_CHANIN3 (TX_CHANIN3_in), + .TX_DATAIN0 (TX_DATAIN0_in), + .TX_DATAIN1 (TX_DATAIN1_in), + .TX_DATAIN2 (TX_DATAIN2_in), + .TX_DATAIN3 (TX_DATAIN3_in), + .TX_ENAIN0 (TX_ENAIN0_in), + .TX_ENAIN1 (TX_ENAIN1_in), + .TX_ENAIN2 (TX_ENAIN2_in), + .TX_ENAIN3 (TX_ENAIN3_in), + .TX_EOPIN0 (TX_EOPIN0_in), + .TX_EOPIN1 (TX_EOPIN1_in), + .TX_EOPIN2 (TX_EOPIN2_in), + .TX_EOPIN3 (TX_EOPIN3_in), + .TX_ERRIN0 (TX_ERRIN0_in), + .TX_ERRIN1 (TX_ERRIN1_in), + .TX_ERRIN2 (TX_ERRIN2_in), + .TX_ERRIN3 (TX_ERRIN3_in), + .TX_MTYIN0 (TX_MTYIN0_in), + .TX_MTYIN1 (TX_MTYIN1_in), + .TX_MTYIN2 (TX_MTYIN2_in), + .TX_MTYIN3 (TX_MTYIN3_in), + .TX_RESET (TX_RESET_in), + .TX_SERDES_REFCLK (TX_SERDES_REFCLK_in), + .TX_SERDES_REFCLK_RESET (TX_SERDES_REFCLK_RESET_in), + .TX_SOPIN0 (TX_SOPIN0_in), + .TX_SOPIN1 (TX_SOPIN1_in), + .TX_SOPIN2 (TX_SOPIN2_in), + .TX_SOPIN3 (TX_SOPIN3_in), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_XECLIB + specify + (CORE_CLK => RX_BYPASS_DATAOUT00[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT00[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT01[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT02[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT03[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT04[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT05[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT06[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT07[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT08[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT09[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT10[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[12]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[13]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[14]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[15]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[16]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[17]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[18]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[19]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[20]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[21]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[22]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[23]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[24]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[25]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[26]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[27]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[28]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[29]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[30]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[31]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[32]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[33]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[34]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[35]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[36]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[37]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[38]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[39]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[40]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[41]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[42]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[43]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[44]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[45]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[46]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[47]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[48]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[49]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[50]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[51]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[52]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[53]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[54]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[55]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[56]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[57]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[58]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[59]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[60]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[61]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[62]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[63]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[64]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[65]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_DATAOUT11[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_ENAOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_AVAILOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_BADLYFRAMEDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_OVERFLOWOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCEDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[0]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[10]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[11]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[1]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[2]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[3]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[4]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[5]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[6]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[7]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[8]) = (100:100:100, 100:100:100); + (CORE_CLK => RX_BYPASS_IS_SYNCWORDOUT[9]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[5]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[6]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS[7]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_MUBITS_UPDATED) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_CRC24_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_DISC) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_RETRY_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[5]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[6]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ[7]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SEQ_UPDATED) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_STATE[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[0]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[1]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[2]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[3]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_SUBSEQ[4]) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_WDOG_ERR) = (100:100:100, 100:100:100); + (CORE_CLK => STAT_RX_RETRANS_WRAP_ERR) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[0]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[10]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[11]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[12]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[13]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[14]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[15]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[1]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[2]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[3]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[4]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[5]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[6]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[7]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[8]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_DO[9]) = (100:100:100, 100:100:100); + (DRP_CLK => DRP_RDY) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT0[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT1[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT2[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_CHANOUT3[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT0[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT1[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT2[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_DATAOUT3[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ENAOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_EOPOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_ERROUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT0[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT1[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT2[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_MTYOUT3[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_OVFOUT) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT0) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT1) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT2) = (100:100:100, 100:100:100); + (LBUS_CLK => RX_SOPOUT3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_ALIGNED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_ALIGNED_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BAD_TYPE_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BURSTMAX_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC24_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_CRC32_VALID[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DESCRAM_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_INTFSTAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_DIAGWORD_LANESTAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[128]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[129]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[130]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[131]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[132]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[133]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[134]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[135]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[136]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[137]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[138]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[139]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[140]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[141]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[142]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[143]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[144]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[145]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[146]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[147]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[148]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[149]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[150]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[151]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[152]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[153]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[154]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[155]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[156]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[157]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[158]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[159]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[160]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[161]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[162]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[163]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[164]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[165]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[166]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[167]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[168]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[169]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[170]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[171]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[172]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[173]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[174]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[175]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[176]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[177]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[178]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[179]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[180]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[181]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[182]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[183]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[184]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[185]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[186]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[187]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[188]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[189]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[190]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[191]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[192]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[193]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[194]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[195]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[196]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[197]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[198]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[199]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[200]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[201]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[202]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[203]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[204]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[205]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[206]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[207]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[208]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[209]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[210]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[211]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[212]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[213]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[214]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[215]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[216]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[217]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[218]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[219]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[220]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[221]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[222]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[223]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[224]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[225]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[226]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[227]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[228]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[229]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[230]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[231]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[232]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[233]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[234]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[235]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[236]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[237]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[238]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[239]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[240]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[241]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[242]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[243]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[244]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[245]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[246]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[247]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[248]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[249]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[250]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[251]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[252]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[253]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[254]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[255]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FC_STAT[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_FRAMING_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MEOP_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_LEN_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MF_REPEAT_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MISALIGNED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MSOP_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_MUBITS_UPDATED) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_OVERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_LATENCY[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_RETRANS_REQ) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_SYNCED_ERR[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_RX_WORD_SYNC[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_ERRINJ_BITERR_DONE) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_OVERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_BURST_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_BUSY) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_PERROUT) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RADDR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B0) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B1) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B2) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RD_B3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RSEL[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_RSEL[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WADDR[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[0]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[100]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[101]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[102]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[103]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[104]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[105]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[106]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[107]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[108]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[109]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[10]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[110]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[111]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[112]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[113]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[114]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[115]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[116]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[117]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[118]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[119]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[11]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[120]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[121]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[122]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[123]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[124]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[125]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[126]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[127]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[128]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[129]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[12]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[130]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[131]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[132]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[133]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[134]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[135]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[136]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[137]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[138]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[139]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[13]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[140]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[141]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[142]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[143]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[144]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[145]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[146]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[147]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[148]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[149]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[14]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[150]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[151]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[152]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[153]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[154]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[155]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[156]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[157]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[158]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[159]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[15]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[160]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[161]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[162]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[163]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[164]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[165]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[166]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[167]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[168]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[169]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[16]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[170]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[171]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[172]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[173]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[174]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[175]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[176]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[177]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[178]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[179]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[17]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[180]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[181]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[182]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[183]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[184]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[185]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[186]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[187]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[188]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[189]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[18]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[190]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[191]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[192]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[193]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[194]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[195]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[196]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[197]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[198]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[199]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[19]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[1]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[200]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[201]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[202]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[203]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[204]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[205]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[206]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[207]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[208]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[209]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[20]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[210]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[211]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[212]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[213]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[214]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[215]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[216]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[217]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[218]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[219]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[21]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[220]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[221]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[222]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[223]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[224]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[225]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[226]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[227]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[228]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[229]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[22]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[230]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[231]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[232]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[233]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[234]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[235]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[236]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[237]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[238]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[239]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[23]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[240]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[241]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[242]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[243]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[244]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[245]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[246]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[247]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[248]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[249]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[24]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[250]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[251]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[252]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[253]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[254]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[255]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[256]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[257]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[258]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[259]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[25]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[260]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[261]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[262]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[263]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[264]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[265]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[266]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[267]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[268]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[269]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[26]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[270]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[271]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[272]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[273]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[274]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[275]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[276]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[277]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[278]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[279]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[27]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[280]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[281]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[282]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[283]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[284]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[285]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[286]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[287]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[288]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[289]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[28]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[290]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[291]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[292]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[293]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[294]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[295]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[296]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[297]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[298]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[299]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[29]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[2]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[300]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[301]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[302]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[303]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[304]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[305]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[306]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[307]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[308]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[309]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[30]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[310]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[311]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[312]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[313]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[314]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[315]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[316]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[317]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[318]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[319]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[31]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[320]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[321]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[322]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[323]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[324]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[325]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[326]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[327]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[328]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[329]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[32]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[330]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[331]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[332]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[333]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[334]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[335]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[336]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[337]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[338]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[339]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[33]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[340]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[341]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[342]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[343]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[344]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[345]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[346]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[347]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[348]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[349]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[34]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[350]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[351]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[352]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[353]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[354]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[355]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[356]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[357]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[358]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[359]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[35]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[360]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[361]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[362]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[363]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[364]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[365]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[366]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[367]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[368]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[369]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[36]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[370]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[371]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[372]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[373]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[374]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[375]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[376]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[377]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[378]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[379]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[37]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[380]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[381]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[382]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[383]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[384]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[385]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[386]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[387]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[388]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[389]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[38]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[390]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[391]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[392]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[393]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[394]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[395]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[396]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[397]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[398]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[399]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[39]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[3]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[400]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[401]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[402]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[403]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[404]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[405]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[406]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[407]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[408]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[409]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[40]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[410]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[411]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[412]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[413]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[414]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[415]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[416]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[417]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[418]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[419]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[41]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[420]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[421]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[422]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[423]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[424]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[425]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[426]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[427]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[428]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[429]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[42]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[430]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[431]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[432]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[433]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[434]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[435]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[436]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[437]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[438]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[439]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[43]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[440]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[441]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[442]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[443]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[444]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[445]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[446]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[447]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[448]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[449]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[44]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[450]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[451]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[452]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[453]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[454]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[455]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[456]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[457]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[458]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[459]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[45]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[460]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[461]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[462]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[463]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[464]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[465]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[466]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[467]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[468]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[469]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[46]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[470]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[471]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[472]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[473]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[474]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[475]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[476]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[477]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[478]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[479]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[47]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[480]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[481]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[482]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[483]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[484]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[485]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[486]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[487]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[488]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[489]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[48]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[490]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[491]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[492]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[493]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[494]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[495]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[496]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[497]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[498]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[499]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[49]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[4]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[500]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[501]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[502]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[503]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[504]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[505]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[506]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[507]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[508]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[509]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[50]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[510]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[511]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[512]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[513]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[514]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[515]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[516]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[517]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[518]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[519]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[51]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[520]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[521]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[522]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[523]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[524]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[525]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[526]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[527]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[528]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[529]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[52]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[530]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[531]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[532]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[533]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[534]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[535]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[536]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[537]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[538]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[539]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[53]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[540]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[541]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[542]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[543]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[544]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[545]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[546]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[547]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[548]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[549]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[54]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[550]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[551]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[552]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[553]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[554]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[555]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[556]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[557]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[558]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[559]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[55]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[560]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[561]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[562]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[563]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[564]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[565]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[566]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[567]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[568]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[569]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[56]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[570]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[571]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[572]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[573]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[574]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[575]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[576]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[577]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[578]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[579]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[57]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[580]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[581]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[582]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[583]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[584]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[585]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[586]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[587]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[588]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[589]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[58]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[590]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[591]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[592]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[593]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[594]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[595]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[596]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[597]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[598]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[599]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[59]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[5]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[600]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[601]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[602]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[603]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[604]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[605]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[606]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[607]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[608]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[609]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[60]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[610]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[611]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[612]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[613]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[614]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[615]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[616]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[617]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[618]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[619]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[61]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[620]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[621]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[622]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[623]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[624]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[625]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[626]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[627]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[628]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[629]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[62]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[630]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[631]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[632]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[633]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[634]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[635]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[636]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[637]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[638]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[639]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[63]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[640]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[641]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[642]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[643]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[64]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[65]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[66]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[67]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[68]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[69]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[6]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[70]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[71]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[72]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[73]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[74]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[75]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[76]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[77]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[78]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[79]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[7]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[80]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[81]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[82]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[83]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[84]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[85]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[86]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[87]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[88]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[89]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[8]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[90]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[91]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[92]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[93]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[94]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[95]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[96]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[97]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[98]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[99]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WDATA[9]) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B0) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B1) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B2) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_RETRANS_RAM_WE_B3) = (100:100:100, 100:100:100); + (LBUS_CLK => STAT_TX_UNDERFLOW_ERR) = (100:100:100, 100:100:100); + (LBUS_CLK => TX_OVFOUT) = (100:100:100, 100:100:100); + (LBUS_CLK => TX_RDYOUT) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA00[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA01[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA02[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA03[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA04[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA05[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA06[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA07[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA08[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA09[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA10[9]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[0]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[10]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[11]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[12]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[13]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[14]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[15]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[16]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[17]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[18]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[19]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[1]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[20]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[21]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[22]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[23]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[24]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[25]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[26]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[27]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[28]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[29]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[2]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[30]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[31]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[32]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[33]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[34]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[35]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[36]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[37]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[38]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[39]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[3]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[40]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[41]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[42]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[43]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[44]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[45]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[46]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[47]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[48]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[49]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[4]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[50]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[51]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[52]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[53]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[54]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[55]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[56]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[57]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[58]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[59]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[5]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[60]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[61]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[62]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[63]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[6]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[7]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[8]) = (100:100:100, 100:100:100); + (TX_SERDES_REFCLK => TX_SERDES_DATA11[9]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CORE_CLK, 0:0:0, notifier); + $period (negedge DRP_CLK, 0:0:0, notifier); + $period (negedge LBUS_CLK, 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[10], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[11], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (negedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (negedge TX_SERDES_REFCLK, 0:0:0, notifier); + $period (posedge CORE_CLK, 0:0:0, notifier); + $period (posedge DRP_CLK, 0:0:0, notifier); + $period (posedge LBUS_CLK, 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[0], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[10], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[11], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[1], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[2], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[3], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[4], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[5], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[6], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[7], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[8], 0:0:0, notifier); + $period (posedge RX_SERDES_CLK[9], 0:0:0, notifier); + $period (posedge TX_SERDES_REFCLK, 0:0:0, notifier); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[10]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[11]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (negedge RX_RESET, posedge CORE_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, CORE_CLK_delay); + $recrem (negedge RX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, LBUS_CLK_delay); + $recrem (negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (negedge RX_SERDES_RESET[10], posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[10], RX_SERDES_CLK_delay[10]); + $recrem (negedge RX_SERDES_RESET[11], posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[11], RX_SERDES_CLK_delay[11]); + $recrem (negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (negedge TX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, LBUS_CLK_delay); + $recrem (negedge TX_SERDES_REFCLK_RESET, posedge TX_SERDES_REFCLK, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_RESET_delay, TX_SERDES_REFCLK_delay); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[10]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[11]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]); + $recrem (posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]); + $recrem (posedge RX_RESET, posedge CORE_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, CORE_CLK_delay); + $recrem (posedge RX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , RX_RESET_delay, LBUS_CLK_delay); + $recrem (posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]); + $recrem (posedge RX_SERDES_RESET[10], posedge RX_SERDES_CLK[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[10], RX_SERDES_CLK_delay[10]); + $recrem (posedge RX_SERDES_RESET[11], posedge RX_SERDES_CLK[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[11], RX_SERDES_CLK_delay[11]); + $recrem (posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]); + $recrem (posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]); + $recrem (posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]); + $recrem (posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]); + $recrem (posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]); + $recrem (posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]); + $recrem (posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]); + $recrem (posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]); + $recrem (posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]); + $recrem (posedge TX_RESET, posedge LBUS_CLK, 0:0:0, 0:0:0, notifier, , , TX_RESET_delay, LBUS_CLK_delay); + $recrem (posedge TX_SERDES_REFCLK_RESET, posedge TX_SERDES_REFCLK, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_RESET_delay, TX_SERDES_REFCLK_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_ERRIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ERRIN_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_RESET, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_delay); + $setuphold (posedge CORE_CLK, negedge CTL_RX_RETRANS_RESET_MODE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_MODE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[0]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[1]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[2]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_ERRINJ_BITERR_LANE[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[3]); + $setuphold (posedge CORE_CLK, negedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge CTL_TX_RLIM_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RLIM_ENABLE_delay); + $setuphold (posedge CORE_CLK, negedge RX_BYPASS_FORCE_REALIGNIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_FORCE_REALIGNIN_delay); + $setuphold (posedge CORE_CLK, negedge RX_BYPASS_RDIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_RDIN_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_ERRIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_ERRIN_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_RESET, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_delay); + $setuphold (posedge CORE_CLK, posedge CTL_RX_RETRANS_RESET_MODE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_RX_RETRANS_RESET_MODE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[0], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[0]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[1], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[1]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[2], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[2]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_ERRINJ_BITERR_LANE[3], 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_ERRINJ_BITERR_LANE_delay[3]); + $setuphold (posedge CORE_CLK, posedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge CTL_TX_RLIM_ENABLE, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, CTL_TX_RLIM_ENABLE_delay); + $setuphold (posedge CORE_CLK, posedge RX_BYPASS_FORCE_REALIGNIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_FORCE_REALIGNIN_delay); + $setuphold (posedge CORE_CLK, posedge RX_BYPASS_RDIN, 0:0:0, 0:0:0, notifier, , , CORE_CLK_delay, RX_BYPASS_RDIN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, negedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, negedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, negedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_ADDR_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[0], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[0]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[10], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[10]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[11], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[11]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[12], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[12]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[13], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[13]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[14], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[14]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[15], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[15]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[1], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[1]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[2], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[2]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[3], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[3]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[4], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[4]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[5], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[5]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[6], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[6]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[7], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[7]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[8], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[8]); + $setuphold (posedge DRP_CLK, posedge DRP_DI[9], 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_DI_delay[9]); + $setuphold (posedge DRP_CLK, posedge DRP_EN, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_EN_delay); + $setuphold (posedge DRP_CLK, posedge DRP_WE, 0:0:0, 0:0:0, notifier, , , DRP_CLK_delay, DRP_WE_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_ERRINJ_BITERR_GO, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_ERRINJ_BITERR_GO_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[100]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[101]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[102]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[103]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[104]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[105]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[106]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[107]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[108]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[109]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[110]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[111]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[112]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[113]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[114]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[115]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[116]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[117]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[118]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[119]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[120]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[121]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[122]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[123]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[124]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[125]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[126]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[127]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[128]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[129]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[12]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[130]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[131]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[132]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[133]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[134]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[135]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[136]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[137]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[138]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[139]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[13]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[140]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[141]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[142]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[143]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[144]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[145]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[146]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[147]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[148]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[149]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[14]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[150]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[151]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[152]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[153]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[154]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[155]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[156]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[157]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[158]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[159]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[15]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[160]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[161]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[162]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[163]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[164]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[165]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[166]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[167]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[168]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[169]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[16]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[170]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[171]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[172]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[173]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[174]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[175]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[176]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[177]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[178]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[179]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[17]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[180]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[181]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[182]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[183]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[184]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[185]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[186]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[187]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[188]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[189]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[18]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[190]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[191]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[192]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[193]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[194]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[195]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[196]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[197]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[198]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[199]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[19]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[200]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[201]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[202]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[203]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[204]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[205]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[206]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[207]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[208]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[209]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[20]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[210]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[211]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[212]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[213]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[214]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[215]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[216]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[217]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[218]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[219]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[21]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[220]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[221]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[222]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[223]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[224]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[225]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[226]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[227]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[228]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[229]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[22]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[230]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[231]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[232]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[233]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[234]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[235]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[236]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[237]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[238]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[239]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[23]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[240]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[241]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[242]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[243]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[244]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[245]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[246]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[247]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[248]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[249]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[24]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[250]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[251]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[252]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[253]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[254]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[255]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[25]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[26]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[27]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[28]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[29]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[30]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[31]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[32]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[33]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[34]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[35]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[36]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[37]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[38]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[39]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[40]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[41]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[42]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[43]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[44]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[45]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[46]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[47]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[48]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[49]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[50]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[51]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[52]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[53]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[54]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[55]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[56]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[57]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[58]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[59]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[60]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[61]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[62]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[63]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[64]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[65]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[66]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[67]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[68]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[69]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[70]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[71]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[72]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[73]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[74]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[75]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[76]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[77]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[78]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[79]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[80]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[81]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[82]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[83]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[84]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[85]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[86]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[87]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[88]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[89]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[90]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[91]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[92]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[93]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[94]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[95]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[96]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[97]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[98]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[99]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_FC_STAT[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[9]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_MUBITS[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_PERRIN, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_PERRIN_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[100]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[101]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[102]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[103]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[104]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[105]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[106]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[107]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[108]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[109]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[110]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[111]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[112]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[113]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[114]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[115]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[116]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[117]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[118]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[119]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[120]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[121]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[122]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[123]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[124]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[125]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[126]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[127]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[128]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[129]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[12]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[130]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[131]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[132]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[133]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[134]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[135]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[136]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[137]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[138]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[139]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[13]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[140]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[141]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[142]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[143]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[144]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[145]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[146]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[147]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[148]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[149]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[14]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[150]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[151]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[152]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[153]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[154]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[155]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[156]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[157]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[158]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[159]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[15]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[160]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[161]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[162]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[163]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[164]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[165]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[166]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[167]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[168]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[169]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[16]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[170]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[171]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[172]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[173]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[174]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[175]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[176]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[177]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[178]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[179]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[17]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[180]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[181]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[182]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[183]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[184]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[185]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[186]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[187]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[188]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[189]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[18]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[190]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[191]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[192]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[193]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[194]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[195]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[196]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[197]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[198]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[199]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[19]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[200]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[201]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[202]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[203]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[204]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[205]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[206]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[207]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[208]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[209]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[20]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[210]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[211]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[212]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[213]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[214]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[215]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[216]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[217]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[218]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[219]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[21]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[220]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[221]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[222]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[223]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[224]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[225]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[226]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[227]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[228]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[229]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[22]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[230]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[231]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[232]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[233]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[234]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[235]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[236]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[237]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[238]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[239]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[23]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[240]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[241]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[242]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[243]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[244]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[245]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[246]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[247]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[248]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[249]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[24]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[250]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[251]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[252]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[253]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[254]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[255]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[256], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[256]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[257], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[257]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[258], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[258]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[259], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[259]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[25]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[260], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[260]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[261], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[261]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[262], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[262]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[263], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[263]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[264], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[264]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[265], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[265]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[266], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[266]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[267], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[267]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[268], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[268]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[269], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[269]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[26]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[270], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[270]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[271], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[271]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[272], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[272]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[273], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[273]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[274], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[274]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[275], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[275]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[276], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[276]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[277], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[277]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[278], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[278]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[279], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[279]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[27]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[280], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[280]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[281], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[281]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[282], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[282]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[283], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[283]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[284], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[284]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[285], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[285]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[286], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[286]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[287], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[287]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[288], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[288]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[289], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[289]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[28]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[290], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[290]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[291], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[291]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[292], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[292]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[293], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[293]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[294], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[294]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[295], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[295]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[296], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[296]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[297], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[297]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[298], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[298]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[299], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[299]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[29]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[300], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[300]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[301], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[301]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[302], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[302]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[303], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[303]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[304], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[304]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[305], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[305]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[306], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[306]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[307], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[307]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[308], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[308]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[309], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[309]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[30]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[310], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[310]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[311], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[311]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[312], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[312]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[313], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[313]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[314], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[314]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[315], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[315]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[316], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[316]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[317], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[317]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[318], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[318]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[319], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[319]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[31]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[320], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[320]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[321], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[321]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[322], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[322]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[323], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[323]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[324], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[324]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[325], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[325]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[326], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[326]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[327], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[327]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[328], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[328]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[329], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[329]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[32]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[330], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[330]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[331], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[331]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[332], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[332]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[333], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[333]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[334], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[334]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[335], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[335]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[336], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[336]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[337], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[337]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[338], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[338]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[339], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[339]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[33]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[340], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[340]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[341], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[341]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[342], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[342]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[343], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[343]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[344], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[344]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[345], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[345]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[346], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[346]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[347], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[347]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[348], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[348]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[349], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[349]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[34]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[350], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[350]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[351], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[351]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[352], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[352]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[353], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[353]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[354], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[354]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[355], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[355]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[356], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[356]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[357], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[357]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[358], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[358]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[359], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[359]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[35]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[360], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[360]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[361], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[361]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[362], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[362]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[363], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[363]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[364], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[364]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[365], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[365]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[366], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[366]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[367], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[367]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[368], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[368]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[369], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[369]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[36]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[370], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[370]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[371], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[371]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[372], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[372]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[373], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[373]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[374], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[374]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[375], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[375]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[376], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[376]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[377], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[377]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[378], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[378]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[379], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[379]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[37]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[380], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[380]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[381], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[381]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[382], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[382]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[383], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[383]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[384], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[384]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[385], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[385]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[386], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[386]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[387], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[387]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[388], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[388]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[389], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[389]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[38]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[390], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[390]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[391], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[391]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[392], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[392]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[393], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[393]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[394], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[394]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[395], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[395]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[396], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[396]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[397], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[397]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[398], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[398]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[399], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[399]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[39]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[400], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[400]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[401], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[401]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[402], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[402]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[403], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[403]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[404], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[404]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[405], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[405]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[406], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[406]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[407], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[407]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[408], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[408]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[409], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[409]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[40]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[410], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[410]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[411], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[411]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[412], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[412]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[413], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[413]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[414], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[414]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[415], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[415]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[416], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[416]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[417], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[417]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[418], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[418]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[419], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[419]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[41]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[420], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[420]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[421], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[421]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[422], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[422]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[423], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[423]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[424], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[424]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[425], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[425]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[426], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[426]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[427], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[427]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[428], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[428]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[429], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[429]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[42]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[430], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[430]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[431], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[431]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[432], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[432]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[433], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[433]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[434], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[434]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[435], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[435]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[436], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[436]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[437], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[437]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[438], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[438]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[439], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[439]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[43]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[440], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[440]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[441], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[441]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[442], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[442]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[443], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[443]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[444], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[444]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[445], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[445]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[446], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[446]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[447], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[447]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[448], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[448]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[449], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[449]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[44]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[450], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[450]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[451], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[451]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[452], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[452]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[453], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[453]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[454], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[454]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[455], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[455]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[456], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[456]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[457], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[457]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[458], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[458]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[459], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[459]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[45]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[460], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[460]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[461], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[461]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[462], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[462]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[463], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[463]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[464], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[464]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[465], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[465]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[466], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[466]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[467], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[467]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[468], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[468]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[469], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[469]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[46]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[470], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[470]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[471], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[471]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[472], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[472]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[473], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[473]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[474], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[474]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[475], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[475]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[476], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[476]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[477], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[477]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[478], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[478]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[479], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[479]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[47]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[480], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[480]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[481], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[481]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[482], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[482]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[483], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[483]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[484], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[484]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[485], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[485]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[486], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[486]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[487], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[487]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[488], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[488]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[489], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[489]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[48]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[490], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[490]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[491], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[491]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[492], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[492]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[493], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[493]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[494], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[494]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[495], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[495]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[496], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[496]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[497], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[497]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[498], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[498]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[499], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[499]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[49]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[500], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[500]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[501], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[501]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[502], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[502]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[503], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[503]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[504], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[504]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[505], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[505]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[506], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[506]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[507], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[507]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[508], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[508]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[509], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[509]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[50]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[510], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[510]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[511], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[511]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[512], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[512]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[513], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[513]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[514], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[514]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[515], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[515]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[516], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[516]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[517], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[517]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[518], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[518]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[519], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[519]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[51]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[520], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[520]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[521], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[521]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[522], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[522]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[523], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[523]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[524], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[524]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[525], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[525]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[526], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[526]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[527], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[527]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[528], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[528]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[529], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[529]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[52]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[530], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[530]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[531], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[531]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[532], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[532]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[533], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[533]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[534], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[534]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[535], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[535]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[536], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[536]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[537], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[537]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[538], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[538]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[539], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[539]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[53]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[540], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[540]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[541], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[541]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[542], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[542]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[543], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[543]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[544], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[544]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[545], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[545]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[546], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[546]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[547], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[547]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[548], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[548]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[549], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[549]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[54]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[550], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[550]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[551], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[551]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[552], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[552]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[553], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[553]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[554], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[554]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[555], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[555]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[556], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[556]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[557], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[557]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[558], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[558]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[559], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[559]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[55]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[560], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[560]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[561], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[561]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[562], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[562]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[563], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[563]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[564], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[564]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[565], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[565]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[566], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[566]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[567], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[567]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[568], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[568]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[569], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[569]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[56]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[570], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[570]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[571], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[571]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[572], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[572]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[573], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[573]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[574], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[574]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[575], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[575]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[576], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[576]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[577], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[577]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[578], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[578]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[579], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[579]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[57]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[580], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[580]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[581], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[581]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[582], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[582]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[583], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[583]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[584], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[584]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[585], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[585]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[586], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[586]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[587], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[587]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[588], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[588]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[589], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[589]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[58]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[590], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[590]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[591], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[591]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[592], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[592]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[593], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[593]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[594], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[594]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[595], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[595]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[596], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[596]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[597], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[597]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[598], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[598]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[599], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[599]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[59]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[600], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[600]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[601], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[601]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[602], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[602]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[603], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[603]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[604], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[604]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[605], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[605]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[606], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[606]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[607], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[607]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[608], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[608]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[609], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[609]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[60]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[610], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[610]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[611], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[611]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[612], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[612]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[613], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[613]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[614], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[614]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[615], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[615]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[616], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[616]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[617], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[617]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[618], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[618]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[619], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[619]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[61]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[620], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[620]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[621], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[621]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[622], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[622]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[623], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[623]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[624], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[624]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[625], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[625]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[626], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[626]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[627], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[627]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[628], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[628]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[629], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[629]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[62]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[630], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[630]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[631], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[631]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[632], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[632]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[633], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[633]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[634], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[634]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[635], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[635]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[636], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[636]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[637], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[637]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[638], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[638]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[639], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[639]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[63]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[640], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[640]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[641], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[641]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[642], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[642]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[643], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[643]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[64]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[65]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[66]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[67]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[68]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[69]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[70]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[71]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[72]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[73]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[74]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[75]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[76]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[77]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[78]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[79]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[80]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[81]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[82]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[83]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[84]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[85]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[86]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[87]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[88]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[89]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[90]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[91]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[92]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[93]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[94]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[95]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[96]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[97]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[98]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[99]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_RAM_RDATA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[9]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RETRANS_REQ_VALID, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_VALID_delay); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_DELTA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[9]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_INTV[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[0]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[10]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[11]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[1]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[2]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[3]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[4]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[5]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[6]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[7]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[8]); + $setuphold (posedge LBUS_CLK, negedge CTL_TX_RLIM_MAX[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_BCTLIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_CHANIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge LBUS_CLK, negedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge LBUS_CLK, negedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge LBUS_CLK, negedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_RX_RETRANS_ACK, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_ACK_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_RX_RETRANS_FORCE_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_RX_RETRANS_FORCE_REQ_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_ERRINJ_BITERR_GO, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_ERRINJ_BITERR_GO_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[100]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[101]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[102]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[103]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[104]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[105]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[106]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[107]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[108]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[109]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[110]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[111]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[112]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[113]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[114]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[115]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[116]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[117]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[118]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[119]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[120]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[121]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[122]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[123]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[124]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[125]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[126]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[127]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[128]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[129]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[12]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[130]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[131]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[132]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[133]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[134]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[135]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[136]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[137]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[138]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[139]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[13]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[140]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[141]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[142]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[143]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[144]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[145]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[146]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[147]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[148]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[149]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[14]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[150]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[151]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[152]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[153]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[154]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[155]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[156]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[157]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[158]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[159]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[15]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[160]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[161]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[162]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[163]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[164]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[165]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[166]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[167]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[168]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[169]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[16]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[170]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[171]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[172]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[173]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[174]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[175]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[176]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[177]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[178]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[179]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[17]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[180]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[181]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[182]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[183]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[184]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[185]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[186]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[187]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[188]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[189]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[18]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[190]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[191]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[192]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[193]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[194]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[195]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[196]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[197]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[198]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[199]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[19]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[200]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[201]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[202]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[203]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[204]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[205]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[206]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[207]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[208]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[209]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[20]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[210]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[211]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[212]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[213]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[214]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[215]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[216]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[217]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[218]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[219]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[21]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[220]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[221]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[222]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[223]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[224]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[225]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[226]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[227]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[228]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[229]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[22]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[230]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[231]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[232]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[233]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[234]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[235]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[236]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[237]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[238]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[239]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[23]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[240]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[241]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[242]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[243]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[244]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[245]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[246]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[247]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[248]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[249]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[24]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[250]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[251]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[252]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[253]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[254]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[255]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[25]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[26]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[27]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[28]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[29]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[30]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[31]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[32]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[33]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[34]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[35]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[36]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[37]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[38]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[39]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[40]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[41]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[42]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[43]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[44]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[45]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[46]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[47]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[48]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[49]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[50]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[51]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[52]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[53]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[54]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[55]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[56]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[57]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[58]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[59]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[60]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[61]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[62]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[63]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[64]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[65]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[66]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[67]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[68]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[69]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[70]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[71]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[72]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[73]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[74]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[75]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[76]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[77]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[78]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[79]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[80]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[81]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[82]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[83]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[84]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[85]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[86]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[87]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[88]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[89]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[90]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[91]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[92]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[93]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[94]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[95]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[96]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[97]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[98]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[99]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_FC_STAT[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_FC_STAT_delay[9]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_MUBITS[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_MUBITS_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_ENABLE, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_ENABLE_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_PERRIN, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_PERRIN_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[100]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[101]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[102]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[103]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[104]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[105]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[106]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[107]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[108]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[109]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[110]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[111]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[112]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[113]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[114]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[115]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[116]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[117]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[118]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[119]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[120]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[121]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[122]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[123]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[124]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[125]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[126]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[127]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[128], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[128]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[129], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[129]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[12]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[130], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[130]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[131], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[131]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[132], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[132]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[133], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[133]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[134], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[134]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[135], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[135]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[136], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[136]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[137], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[137]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[138], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[138]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[139], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[139]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[13]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[140], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[140]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[141], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[141]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[142], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[142]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[143], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[143]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[144], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[144]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[145], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[145]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[146], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[146]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[147], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[147]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[148], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[148]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[149], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[149]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[14]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[150], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[150]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[151], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[151]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[152], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[152]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[153], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[153]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[154], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[154]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[155], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[155]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[156], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[156]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[157], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[157]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[158], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[158]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[159], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[159]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[15]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[160], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[160]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[161], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[161]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[162], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[162]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[163], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[163]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[164], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[164]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[165], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[165]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[166], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[166]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[167], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[167]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[168], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[168]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[169], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[169]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[16]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[170], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[170]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[171], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[171]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[172], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[172]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[173], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[173]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[174], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[174]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[175], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[175]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[176], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[176]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[177], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[177]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[178], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[178]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[179], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[179]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[17]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[180], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[180]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[181], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[181]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[182], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[182]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[183], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[183]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[184], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[184]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[185], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[185]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[186], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[186]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[187], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[187]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[188], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[188]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[189], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[189]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[18]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[190], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[190]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[191], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[191]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[192], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[192]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[193], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[193]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[194], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[194]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[195], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[195]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[196], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[196]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[197], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[197]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[198], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[198]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[199], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[199]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[19]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[200], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[200]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[201], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[201]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[202], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[202]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[203], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[203]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[204], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[204]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[205], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[205]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[206], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[206]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[207], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[207]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[208], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[208]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[209], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[209]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[20]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[210], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[210]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[211], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[211]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[212], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[212]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[213], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[213]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[214], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[214]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[215], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[215]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[216], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[216]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[217], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[217]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[218], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[218]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[219], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[219]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[21]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[220], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[220]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[221], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[221]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[222], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[222]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[223], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[223]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[224], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[224]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[225], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[225]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[226], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[226]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[227], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[227]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[228], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[228]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[229], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[229]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[22]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[230], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[230]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[231], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[231]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[232], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[232]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[233], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[233]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[234], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[234]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[235], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[235]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[236], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[236]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[237], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[237]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[238], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[238]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[239], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[239]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[23]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[240], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[240]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[241], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[241]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[242], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[242]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[243], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[243]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[244], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[244]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[245], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[245]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[246], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[246]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[247], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[247]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[248], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[248]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[249], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[249]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[24]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[250], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[250]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[251], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[251]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[252], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[252]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[253], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[253]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[254], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[254]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[255], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[255]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[256], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[256]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[257], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[257]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[258], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[258]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[259], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[259]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[25]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[260], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[260]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[261], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[261]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[262], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[262]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[263], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[263]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[264], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[264]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[265], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[265]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[266], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[266]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[267], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[267]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[268], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[268]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[269], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[269]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[26]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[270], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[270]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[271], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[271]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[272], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[272]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[273], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[273]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[274], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[274]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[275], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[275]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[276], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[276]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[277], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[277]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[278], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[278]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[279], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[279]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[27]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[280], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[280]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[281], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[281]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[282], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[282]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[283], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[283]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[284], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[284]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[285], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[285]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[286], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[286]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[287], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[287]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[288], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[288]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[289], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[289]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[28]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[290], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[290]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[291], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[291]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[292], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[292]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[293], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[293]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[294], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[294]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[295], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[295]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[296], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[296]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[297], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[297]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[298], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[298]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[299], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[299]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[29]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[300], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[300]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[301], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[301]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[302], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[302]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[303], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[303]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[304], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[304]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[305], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[305]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[306], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[306]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[307], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[307]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[308], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[308]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[309], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[309]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[30]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[310], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[310]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[311], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[311]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[312], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[312]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[313], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[313]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[314], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[314]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[315], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[315]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[316], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[316]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[317], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[317]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[318], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[318]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[319], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[319]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[31]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[320], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[320]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[321], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[321]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[322], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[322]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[323], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[323]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[324], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[324]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[325], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[325]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[326], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[326]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[327], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[327]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[328], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[328]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[329], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[329]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[32]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[330], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[330]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[331], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[331]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[332], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[332]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[333], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[333]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[334], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[334]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[335], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[335]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[336], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[336]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[337], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[337]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[338], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[338]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[339], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[339]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[33]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[340], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[340]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[341], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[341]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[342], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[342]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[343], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[343]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[344], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[344]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[345], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[345]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[346], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[346]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[347], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[347]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[348], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[348]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[349], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[349]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[34]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[350], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[350]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[351], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[351]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[352], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[352]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[353], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[353]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[354], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[354]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[355], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[355]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[356], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[356]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[357], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[357]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[358], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[358]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[359], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[359]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[35]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[360], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[360]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[361], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[361]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[362], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[362]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[363], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[363]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[364], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[364]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[365], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[365]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[366], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[366]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[367], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[367]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[368], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[368]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[369], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[369]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[36]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[370], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[370]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[371], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[371]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[372], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[372]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[373], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[373]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[374], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[374]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[375], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[375]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[376], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[376]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[377], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[377]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[378], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[378]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[379], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[379]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[37]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[380], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[380]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[381], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[381]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[382], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[382]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[383], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[383]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[384], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[384]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[385], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[385]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[386], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[386]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[387], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[387]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[388], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[388]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[389], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[389]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[38]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[390], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[390]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[391], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[391]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[392], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[392]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[393], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[393]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[394], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[394]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[395], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[395]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[396], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[396]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[397], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[397]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[398], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[398]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[399], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[399]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[39]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[400], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[400]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[401], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[401]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[402], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[402]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[403], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[403]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[404], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[404]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[405], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[405]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[406], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[406]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[407], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[407]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[408], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[408]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[409], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[409]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[40]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[410], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[410]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[411], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[411]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[412], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[412]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[413], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[413]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[414], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[414]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[415], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[415]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[416], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[416]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[417], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[417]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[418], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[418]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[419], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[419]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[41]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[420], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[420]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[421], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[421]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[422], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[422]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[423], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[423]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[424], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[424]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[425], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[425]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[426], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[426]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[427], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[427]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[428], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[428]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[429], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[429]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[42]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[430], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[430]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[431], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[431]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[432], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[432]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[433], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[433]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[434], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[434]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[435], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[435]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[436], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[436]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[437], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[437]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[438], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[438]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[439], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[439]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[43]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[440], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[440]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[441], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[441]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[442], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[442]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[443], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[443]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[444], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[444]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[445], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[445]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[446], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[446]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[447], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[447]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[448], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[448]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[449], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[449]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[44]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[450], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[450]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[451], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[451]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[452], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[452]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[453], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[453]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[454], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[454]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[455], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[455]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[456], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[456]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[457], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[457]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[458], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[458]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[459], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[459]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[45]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[460], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[460]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[461], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[461]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[462], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[462]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[463], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[463]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[464], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[464]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[465], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[465]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[466], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[466]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[467], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[467]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[468], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[468]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[469], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[469]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[46]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[470], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[470]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[471], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[471]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[472], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[472]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[473], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[473]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[474], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[474]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[475], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[475]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[476], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[476]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[477], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[477]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[478], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[478]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[479], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[479]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[47]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[480], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[480]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[481], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[481]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[482], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[482]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[483], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[483]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[484], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[484]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[485], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[485]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[486], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[486]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[487], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[487]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[488], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[488]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[489], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[489]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[48]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[490], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[490]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[491], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[491]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[492], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[492]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[493], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[493]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[494], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[494]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[495], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[495]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[496], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[496]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[497], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[497]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[498], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[498]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[499], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[499]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[49]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[500], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[500]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[501], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[501]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[502], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[502]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[503], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[503]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[504], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[504]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[505], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[505]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[506], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[506]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[507], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[507]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[508], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[508]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[509], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[509]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[50]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[510], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[510]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[511], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[511]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[512], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[512]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[513], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[513]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[514], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[514]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[515], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[515]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[516], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[516]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[517], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[517]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[518], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[518]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[519], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[519]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[51]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[520], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[520]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[521], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[521]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[522], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[522]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[523], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[523]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[524], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[524]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[525], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[525]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[526], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[526]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[527], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[527]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[528], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[528]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[529], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[529]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[52]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[530], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[530]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[531], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[531]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[532], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[532]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[533], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[533]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[534], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[534]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[535], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[535]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[536], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[536]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[537], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[537]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[538], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[538]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[539], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[539]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[53]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[540], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[540]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[541], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[541]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[542], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[542]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[543], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[543]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[544], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[544]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[545], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[545]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[546], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[546]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[547], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[547]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[548], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[548]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[549], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[549]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[54]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[550], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[550]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[551], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[551]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[552], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[552]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[553], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[553]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[554], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[554]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[555], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[555]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[556], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[556]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[557], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[557]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[558], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[558]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[559], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[559]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[55]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[560], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[560]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[561], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[561]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[562], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[562]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[563], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[563]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[564], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[564]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[565], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[565]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[566], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[566]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[567], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[567]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[568], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[568]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[569], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[569]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[56]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[570], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[570]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[571], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[571]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[572], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[572]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[573], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[573]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[574], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[574]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[575], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[575]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[576], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[576]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[577], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[577]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[578], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[578]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[579], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[579]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[57]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[580], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[580]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[581], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[581]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[582], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[582]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[583], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[583]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[584], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[584]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[585], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[585]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[586], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[586]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[587], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[587]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[588], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[588]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[589], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[589]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[58]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[590], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[590]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[591], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[591]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[592], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[592]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[593], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[593]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[594], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[594]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[595], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[595]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[596], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[596]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[597], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[597]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[598], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[598]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[599], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[599]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[59]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[600], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[600]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[601], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[601]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[602], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[602]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[603], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[603]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[604], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[604]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[605], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[605]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[606], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[606]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[607], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[607]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[608], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[608]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[609], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[609]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[60]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[610], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[610]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[611], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[611]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[612], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[612]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[613], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[613]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[614], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[614]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[615], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[615]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[616], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[616]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[617], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[617]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[618], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[618]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[619], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[619]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[61]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[620], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[620]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[621], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[621]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[622], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[622]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[623], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[623]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[624], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[624]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[625], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[625]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[626], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[626]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[627], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[627]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[628], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[628]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[629], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[629]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[62]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[630], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[630]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[631], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[631]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[632], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[632]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[633], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[633]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[634], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[634]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[635], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[635]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[636], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[636]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[637], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[637]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[638], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[638]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[639], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[639]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[63]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[640], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[640]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[641], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[641]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[642], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[642]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[643], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[643]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[64]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[65]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[66]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[67]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[68]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[69]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[70]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[71]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[72]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[73]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[74]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[75]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[76]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[77]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[78]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[79]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[80]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[81]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[82]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[83]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[84]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[85]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[86]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[87]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[88]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[89]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[90]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[91]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[92]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[93]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[94]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[95]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[96]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[97]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[98]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[99]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_RAM_RDATA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_RAM_RDATA_delay[9]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_REQ, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RETRANS_REQ_VALID, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RETRANS_REQ_VALID_delay); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_DELTA[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_DELTA_delay[9]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_INTV[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_INTV_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[0]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[10]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[11]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[1]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[2]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[3]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[4]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[5]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[6]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[7]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[8]); + $setuphold (posedge LBUS_CLK, posedge CTL_TX_RLIM_MAX[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, CTL_TX_RLIM_MAX_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_BCTLIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_BCTLIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN0_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN1_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN2_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_CHANIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_CHANIN3_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN0_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN1_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN2_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[100]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[101]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[102]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[103]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[104]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[105]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[106]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[107]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[108]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[109]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[10]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[110]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[111]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[112]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[113]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[114]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[115]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[116]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[117]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[118]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[119]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[11]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[120]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[121]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[122]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[123]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[124]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[125]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[126]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[127]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[12]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[13]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[14]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[15]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[16]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[17]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[18]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[19]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[20]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[21]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[22]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[23]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[24]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[25]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[26]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[27]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[28]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[29]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[30]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[31]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[32]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[33]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[34]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[35]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[36]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[37]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[38]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[39]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[40]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[41]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[42]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[43]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[44]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[45]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[46]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[47]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[48]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[49]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[4]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[50]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[51]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[52]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[53]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[54]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[55]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[56]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[57]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[58]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[59]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[5]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[60]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[61]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[62]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[63]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[64]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[65]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[66]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[67]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[68]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[69]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[6]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[70]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[71]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[72]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[73]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[74]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[75]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[76]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[77]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[78]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[79]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[7]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[80]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[81]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[82]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[83]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[84]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[85]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[86]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[87]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[88]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[89]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[8]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[90]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[91]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[92]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[93]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[94]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[95]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[96]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[97]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[98]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[99]); + $setuphold (posedge LBUS_CLK, posedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_DATAIN3_delay[9]); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ENAIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ENAIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_EOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_EOPIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_ERRIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_ERRIN3_delay); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN0_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN1_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN2_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[0]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[1]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[2]); + $setuphold (posedge LBUS_CLK, posedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_MTYIN3_delay[3]); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN0, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN0_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN1, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN1_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN2, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN2_delay); + $setuphold (posedge LBUS_CLK, posedge TX_SOPIN3, 0:0:0, 0:0:0, notifier, , , LBUS_CLK_delay, TX_SOPIN3_delay); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA00[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[9]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[0]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[10]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[11]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[12]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[13]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[14]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[15]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[16]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[17]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[18]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[19]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[1]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[20]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[21]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[22]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[23]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[24]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[25]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[26]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[27]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[28]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[29]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[2]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[30]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[31]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[32]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[33]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[34]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[35]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[36]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[37]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[38]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[39]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[3]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[40]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[41]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[42]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[43]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[44]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[45]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[46]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[47]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[48]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[49]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[4]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[50]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[51]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[52]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[53]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[54]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[55]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[56]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[57]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[58]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[59]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[5]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[60]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[61]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[62]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[63]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[6]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[7]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[8]); + $setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA00[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[0], RX_SERDES_DATA00_delay[9]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[0]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[10]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[11]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[12]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[13]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[14]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[15]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[16]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[17]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[18]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[19]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[1]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[20]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[21]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[22]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[23]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[24]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[25]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[26]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[27]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[28]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[29]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[2]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[30]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[31]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[32]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[33]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[34]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[35]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[36]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[37]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[38]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[39]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[3]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[40]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[41]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[42]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[43]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[44]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[45]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[46]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[47]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[48]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[49]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[4]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[50]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[51]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[52]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[53]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[54]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[55]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[56]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[57]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[58]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[59]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[5]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[60]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[61]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[62]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[63]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[6]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[7]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[8]); + $setuphold (posedge RX_SERDES_CLK[10], negedge RX_SERDES_DATA10[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[9]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[0]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[10]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[11]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[12]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[13]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[14]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[15]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[16]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[17]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[18]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[19]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[1]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[20]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[21]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[22]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[23]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[24]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[25]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[26]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[27]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[28]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[29]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[2]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[30]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[31]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[32]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[33]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[34]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[35]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[36]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[37]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[38]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[39]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[3]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[40]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[41]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[42]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[43]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[44]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[45]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[46]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[47]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[48]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[49]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[4]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[50]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[51]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[52]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[53]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[54]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[55]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[56]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[57]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[58]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[59]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[5]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[60]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[61]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[62]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[63]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[6]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[7]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[8]); + $setuphold (posedge RX_SERDES_CLK[10], posedge RX_SERDES_DATA10[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[10], RX_SERDES_DATA10_delay[9]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[0]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[10]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[11]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[12]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[13]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[14]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[15]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[16]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[17]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[18]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[19]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[1]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[20]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[21]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[22]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[23]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[24]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[25]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[26]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[27]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[28]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[29]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[2]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[30]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[31]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[32]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[33]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[34]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[35]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[36]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[37]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[38]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[39]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[3]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[40]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[41]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[42]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[43]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[44]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[45]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[46]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[47]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[48]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[49]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[4]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[50]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[51]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[52]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[53]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[54]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[55]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[56]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[57]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[58]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[59]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[5]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[60]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[61]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[62]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[63]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[6]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[7]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[8]); + $setuphold (posedge RX_SERDES_CLK[11], negedge RX_SERDES_DATA11[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[9]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[0]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[10]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[11]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[12]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[13]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[14]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[15]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[16]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[17]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[18]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[19]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[1]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[20]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[21]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[22]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[23]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[24]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[25]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[26]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[27]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[28]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[29]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[2]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[30]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[31]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[32]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[33]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[34]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[35]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[36]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[37]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[38]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[39]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[3]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[40]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[41]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[42]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[43]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[44]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[45]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[46]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[47]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[48]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[49]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[4]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[50]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[51]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[52]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[53]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[54]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[55]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[56]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[57]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[58]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[59]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[5]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[60]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[61]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[62]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[63]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[6]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[7]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[8]); + $setuphold (posedge RX_SERDES_CLK[11], posedge RX_SERDES_DATA11[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[11], RX_SERDES_DATA11_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA01[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[9]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[0]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[10]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[11]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[12]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[13]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[14]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[15]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[16]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[17]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[18]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[19]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[1]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[20]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[21]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[22]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[23]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[24]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[25]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[26]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[27]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[28]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[29]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[2]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[30]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[31]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[32]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[33]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[34]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[35]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[36]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[37]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[38]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[39]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[3]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[40]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[41]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[42]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[43]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[44]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[45]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[46]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[47]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[48]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[49]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[4]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[50]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[51]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[52]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[53]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[54]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[55]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[56]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[57]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[58]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[59]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[5]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[60]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[61]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[62]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[63]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[6]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[7]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[8]); + $setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA01[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[1], RX_SERDES_DATA01_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA02[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[9]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[0]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[10]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[11]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[12]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[13]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[14]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[15]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[16]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[17]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[18]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[19]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[1]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[20]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[21]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[22]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[23]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[24]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[25]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[26]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[27]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[28]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[29]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[2]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[30]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[31]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[32]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[33]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[34]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[35]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[36]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[37]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[38]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[39]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[3]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[40]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[41]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[42]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[43]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[44]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[45]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[46]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[47]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[48]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[49]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[4]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[50]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[51]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[52]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[53]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[54]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[55]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[56]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[57]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[58]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[59]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[5]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[60]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[61]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[62]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[63]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[6]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[7]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[8]); + $setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA02[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[2], RX_SERDES_DATA02_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA03[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[9]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[0]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[10]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[11]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[12]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[13]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[14]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[15]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[16]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[17]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[18]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[19]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[1]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[20]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[21]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[22]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[23]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[24]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[25]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[26]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[27]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[28]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[29]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[2]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[30]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[31]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[32]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[33]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[34]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[35]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[36]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[37]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[38]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[39]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[3]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[40]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[41]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[42]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[43]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[44]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[45]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[46]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[47]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[48]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[49]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[4]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[50]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[51]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[52]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[53]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[54]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[55]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[56]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[57]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[58]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[59]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[5]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[60]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[61]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[62]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[63]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[6]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[7]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[8]); + $setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA03[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[3], RX_SERDES_DATA03_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[32]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[33]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[34]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[35]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[36]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[37]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[38]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[39]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[40]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[41]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[42]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[43]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[44]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[45]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[46]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[47]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[48]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[49]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[50]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[51]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[52]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[53]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[54]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[55]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[56]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[57]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[58]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[59]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[60]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[61]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[62]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[63]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA04[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[9]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[0]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[10]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[11]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[12]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[13]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[14]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[15]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[16]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[17]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[18]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[19]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[1]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[20]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[21]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[22]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[23]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[24]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[25]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[26]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[27]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[28]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[29]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[2]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[30]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[31]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[32]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[33]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[34]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[35]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[36]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[37]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[38]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[39]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[3]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[40]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[41]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[42]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[43]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[44]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[45]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[46]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[47]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[48]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[49]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[4]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[50]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[51]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[52]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[53]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[54]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[55]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[56]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[57]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[58]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[59]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[5]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[60]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[61]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[62]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[63]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[6]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[7]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[8]); + $setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA04[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[4], RX_SERDES_DATA04_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[32]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[33]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[34]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[35]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[36]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[37]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[38]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[39]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[40]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[41]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[42]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[43]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[44]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[45]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[46]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[47]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[48]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[49]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[50]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[51]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[52]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[53]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[54]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[55]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[56]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[57]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[58]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[59]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[60]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[61]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[62]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[63]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA05[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[9]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[0]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[10]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[11]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[12]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[13]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[14]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[15]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[16]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[17]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[18]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[19]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[1]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[20]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[21]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[22]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[23]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[24]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[25]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[26]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[27]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[28]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[29]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[2]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[30]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[31]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[32]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[33]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[34]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[35]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[36]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[37]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[38]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[39]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[3]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[40]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[41]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[42]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[43]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[44]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[45]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[46]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[47]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[48]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[49]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[4]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[50]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[51]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[52]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[53]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[54]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[55]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[56]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[57]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[58]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[59]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[5]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[60]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[61]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[62]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[63]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[6]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[7]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[8]); + $setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA05[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[5], RX_SERDES_DATA05_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[32]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[33]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[34]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[35]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[36]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[37]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[38]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[39]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[40]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[41]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[42]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[43]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[44]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[45]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[46]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[47]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[48]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[49]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[50]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[51]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[52]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[53]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[54]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[55]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[56]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[57]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[58]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[59]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[60]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[61]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[62]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[63]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA06[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[9]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[0]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[10]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[11]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[12]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[13]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[14]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[15]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[16]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[17]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[18]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[19]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[1]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[20]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[21]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[22]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[23]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[24]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[25]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[26]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[27]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[28]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[29]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[2]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[30]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[31]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[32]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[33]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[34]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[35]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[36]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[37]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[38]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[39]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[3]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[40]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[41]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[42]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[43]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[44]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[45]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[46]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[47]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[48]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[49]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[4]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[50]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[51]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[52]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[53]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[54]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[55]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[56]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[57]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[58]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[59]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[5]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[60]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[61]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[62]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[63]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[6]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[7]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[8]); + $setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA06[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[6], RX_SERDES_DATA06_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[32]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[33]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[34]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[35]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[36]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[37]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[38]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[39]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[40]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[41]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[42]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[43]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[44]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[45]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[46]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[47]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[48]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[49]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[50]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[51]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[52]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[53]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[54]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[55]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[56]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[57]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[58]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[59]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[60]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[61]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[62]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[63]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA07[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[9]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[0]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[10]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[11]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[12]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[13]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[14]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[15]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[16]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[17]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[18]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[19]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[1]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[20]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[21]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[22]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[23]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[24]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[25]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[26]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[27]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[28]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[29]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[2]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[30]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[31]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[32]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[33]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[34]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[35]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[36]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[37]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[38]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[39]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[3]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[40]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[41]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[42]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[43]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[44]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[45]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[46]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[47]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[48]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[49]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[4]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[50]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[51]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[52]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[53]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[54]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[55]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[56]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[57]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[58]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[59]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[5]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[60]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[61]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[62]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[63]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[6]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[7]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[8]); + $setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA07[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[7], RX_SERDES_DATA07_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[32]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[33]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[34]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[35]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[36]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[37]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[38]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[39]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[40]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[41]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[42]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[43]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[44]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[45]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[46]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[47]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[48]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[49]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[50]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[51]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[52]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[53]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[54]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[55]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[56]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[57]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[58]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[59]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[60]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[61]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[62]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[63]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA08[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[9]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[0]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[10]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[11]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[12]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[13]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[14]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[15]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[16]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[17]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[18]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[19]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[1]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[20]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[21]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[22]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[23]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[24]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[25]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[26]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[27]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[28]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[29]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[2]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[30]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[31]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[32]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[33]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[34]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[35]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[36]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[37]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[38]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[39]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[3]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[40]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[41]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[42]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[43]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[44]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[45]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[46]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[47]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[48]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[49]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[4]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[50]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[51]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[52]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[53]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[54]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[55]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[56]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[57]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[58]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[59]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[5]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[60]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[61]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[62]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[63]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[6]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[7]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[8]); + $setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA08[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[8], RX_SERDES_DATA08_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[32]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[33]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[34]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[35]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[36]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[37]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[38]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[39]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[40]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[41]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[42]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[43]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[44]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[45]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[46]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[47]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[48]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[49]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[50]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[51]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[52]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[53]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[54]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[55]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[56]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[57]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[58]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[59]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[60]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[61]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[62]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[63]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA09[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[9]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[0], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[0]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[10], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[10]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[11], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[11]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[12], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[12]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[13], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[13]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[14], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[14]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[15], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[15]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[16], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[16]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[17], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[17]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[18], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[18]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[19], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[19]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[1], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[1]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[20], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[20]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[21], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[21]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[22], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[22]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[23], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[23]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[24], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[24]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[25], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[25]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[26], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[26]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[27], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[27]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[28], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[28]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[29], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[29]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[2], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[2]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[30], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[30]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[31], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[31]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[32], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[32]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[33], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[33]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[34], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[34]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[35], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[35]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[36], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[36]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[37], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[37]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[38], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[38]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[39], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[39]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[3], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[3]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[40], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[40]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[41], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[41]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[42], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[42]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[43], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[43]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[44], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[44]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[45], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[45]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[46], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[46]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[47], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[47]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[48], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[48]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[49], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[49]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[4], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[4]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[50], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[50]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[51], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[51]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[52], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[52]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[53], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[53]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[54], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[54]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[55], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[55]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[56], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[56]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[57], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[57]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[58], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[58]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[59], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[59]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[5], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[5]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[60], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[60]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[61], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[61]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[62], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[62]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[63], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[63]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[6], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[6]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[7], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[7]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[8], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[8]); + $setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA09[9], 0:0:0, 0:0:0, notifier, , , RX_SERDES_CLK_delay[9], RX_SERDES_DATA09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_INTFSTAT, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_INTFSTAT_delay); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge CTL_TX_DIAGWORD_LANESTAT[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_CTRLIN[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN00[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN01[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN02[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN03[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN04[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN05[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN06[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN07[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN08[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN09[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN10[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_DATAIN11[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_ENAIN, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_ENAIN_delay); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_GEARBOX_SEQIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, negedge TX_BYPASS_MFRAMER_STATEIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_INTFSTAT, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_INTFSTAT_delay); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge CTL_TX_DIAGWORD_LANESTAT[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, CTL_TX_DIAGWORD_LANESTAT_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_CTRLIN[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_CTRLIN_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN00[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN00_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN01[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN01_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN02[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN02_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN03[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN03_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN04[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN04_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN05[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN05_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN06[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN06_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN07[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN07_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN08[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN08_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN09[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN09_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN10[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN10_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[10], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[10]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[11], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[11]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[12], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[12]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[13], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[13]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[14], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[14]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[15], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[15]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[16], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[16]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[17], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[17]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[18], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[18]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[19], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[19]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[20], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[20]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[21], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[21]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[22], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[22]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[23], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[23]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[24], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[24]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[25], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[25]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[26], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[26]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[27], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[27]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[28], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[28]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[29], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[29]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[30], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[30]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[31], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[31]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[32], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[32]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[33], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[33]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[34], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[34]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[35], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[35]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[36], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[36]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[37], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[37]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[38], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[38]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[39], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[39]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[40], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[40]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[41], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[41]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[42], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[42]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[43], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[43]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[44], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[44]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[45], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[45]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[46], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[46]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[47], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[47]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[48], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[48]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[49], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[49]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[50], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[50]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[51], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[51]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[52], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[52]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[53], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[53]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[54], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[54]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[55], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[55]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[56], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[56]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[57], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[57]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[58], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[58]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[59], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[59]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[60], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[60]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[61], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[61]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[62], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[62]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[63], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[63]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[8], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[8]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_DATAIN11[9], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_DATAIN11_delay[9]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_ENAIN, 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_ENAIN_delay); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[3]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[4], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[4]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[5], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[5]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[6], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[6]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_GEARBOX_SEQIN[7], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_GEARBOX_SEQIN_delay[7]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[0], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[0]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[1], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[1]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[2], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[2]); + $setuphold (posedge TX_SERDES_REFCLK, posedge TX_BYPASS_MFRAMER_STATEIN[3], 0:0:0, 0:0:0, notifier, , , TX_SERDES_REFCLK_delay, TX_BYPASS_MFRAMER_STATEIN_delay[3]); + $width (negedge CORE_CLK, 0:0:0, 0, notifier); + $width (negedge DRP_CLK, 0:0:0, 0, notifier); + $width (negedge LBUS_CLK, 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[10], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[11], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (negedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (negedge TX_SERDES_REFCLK, 0:0:0, 0, notifier); + $width (posedge CORE_CLK, 0:0:0, 0, notifier); + $width (posedge DRP_CLK, 0:0:0, 0, notifier); + $width (posedge LBUS_CLK, 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[0], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[10], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[11], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[1], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[2], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[3], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[4], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[5], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[6], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[7], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[8], 0:0:0, 0, notifier); + $width (posedge RX_SERDES_CLK[9], 0:0:0, 0, notifier); + $width (posedge TX_SERDES_REFCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/INBUF.v b/verilog/src/unisims/INBUF.v new file mode 100644 index 0000000..d684bd4 --- /dev/null +++ b/verilog/src/unisims/INBUF.v @@ -0,0 +1,175 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : INBUF.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 808642 Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module INBUF #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter IBUF_LOW_PWR = "TRUE", + parameter ISTANDARD = "UNUSED", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0 +)( + output O, + + input [3:0] OSC, + input OSC_EN, + input PAD, + input VREF +); + +// define constants + localparam MODULE_NAME = "INBUF"; + +// Parameter encodings and registers + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + + reg trig_attr = 1'b0; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + + wire IBUF_LOW_PWR_BIN; + wire [6:0] SIM_INPUT_BUFFER_OFFSET_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire OSC_EN_in; + wire [3:0] OSC_in; + +`ifdef XIL_TIMING + wire OSC_EN_delay; + wire [3:0] OSC_delay; +`endif + + reg O_OSC_in; + integer OSC_int = 0; + + assign O = (OSC_EN_in === 1'b1) ? O_OSC_in : PAD; + +`ifdef XIL_TIMING + assign OSC_EN_in = OSC_EN_delay; + assign OSC_in = OSC_delay; +`else + assign OSC_EN_in = OSC_EN; + assign OSC_in = OSC; +`endif + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-106] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-111] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + always @ (OSC_in or OSC_EN_in) begin + OSC_int = OSC_in[2:0] * 5; + if (OSC_in[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in === 1'b1) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin + O_OSC_in <= 1'b0; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin + O_OSC_in <= 1'b1; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin + O_OSC_in <= ~O_OSC_in; + end + end + end + + initial begin +// if (OSC_EN_in === 1'b1) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin + O_OSC_in <= 1'b0; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin + O_OSC_in <= 1'b1; + end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin + O_OSC_in <= 1'bx; + end + end + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (OSC *> O) = (0:0:0, 0:0:0); + (OSC_EN => O) = (0:0:0, 0:0:0); + (PAD => O) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $setuphold (negedge OSC_EN, negedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay); + $setuphold (negedge OSC_EN, posedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/INV.v b/verilog/src/unisims/INV.v new file mode 100644 index 0000000..0a87cb8 --- /dev/null +++ b/verilog/src/unisims/INV.v @@ -0,0 +1,63 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Inverter +// /___/ /\ Filename : INV.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps/1 ps + +`celldefine + +module INV (O, I); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + output O; + input I; + + not n1 (O, I); + +`ifdef XIL_TIMING + + specify + + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IN_FIFO.v b/verilog/src/unisims/IN_FIFO.v new file mode 100644 index 0000000..d9582b5 --- /dev/null +++ b/verilog/src/unisims/IN_FIFO.v @@ -0,0 +1,362 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 7SERIES IN FIFO +// /__/ /\ Filename : IN_FIFO.v +// \ \ / \ +// \__\/\__ \ +// +// Date: Comment: +// 08MAR2010 Initial UNI/UNP/SIM version from yml +// 03JUN2010 yml update +// 29JUN2010 enable encrypted rtl +// 10AUG2010 yml, rtl update +// 29SEP2010 minor cleanup +// add width checks, full path support +// 28OCT2010 rtl update +// 05NOV2010 update defaults +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 15AUG2011 621681 remove SIM_SPEEDUP, make default +// 21SEP2011 625537 period checks on RDCLK, WRCLK +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IN_FIFO ( + ALMOSTEMPTY, + ALMOSTFULL, + EMPTY, + FULL, + Q0, + Q1, + Q2, + Q3, + Q4, + Q5, + Q6, + Q7, + Q8, + Q9, + + D0, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + D9, + RDCLK, + RDEN, + RESET, + WRCLK, + WREN +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; + parameter SYNCHRONOUS_MODE = "FALSE"; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam out_delay = 0; +`else + localparam in_delay = 1; + localparam out_delay = 10; +`endif + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + localparam MODULE_NAME = "IN_FIFO"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [7:0] Q0; + output [7:0] Q1; + output [7:0] Q2; + output [7:0] Q3; + output [7:0] Q4; + output [7:0] Q5; + output [7:0] Q6; + output [7:0] Q7; + output [7:0] Q8; + output [7:0] Q9; + + input RDCLK; + input RDEN; + input RESET; + input WRCLK; + input WREN; + input [3:0] D0; + input [3:0] D1; + input [3:0] D2; + input [3:0] D3; + input [3:0] D4; + input [3:0] D7; + input [3:0] D8; + input [3:0] D9; + input [7:0] D5; + input [7:0] D6; + + reg [0:0] ARRAY_MODE_BINARY; + reg [0:0] SLOW_RD_CLK_BINARY; + reg [0:0] SLOW_WR_CLK_BINARY; + reg [0:0] SYNCHRONOUS_MODE_BINARY; + reg [3:0] SPARE_BINARY; + reg [7:0] ALMOST_EMPTY_VALUE_BINARY; + reg [7:0] ALMOST_FULL_VALUE_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (ALMOST_EMPTY_VALUE) + 1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001; + 2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011; + default : begin + $display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE); + #1 $finish; + end + endcase + + case (ALMOST_FULL_VALUE) + 1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001; + 2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011; + default : begin + $display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE); + #1 $finish; + end + endcase + + case (ARRAY_MODE) + "ARRAY_MODE_4_X_8" : ARRAY_MODE_BINARY <= 1'b1; + "ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_4_X_8 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE); + #1 $finish; + end + endcase + + SLOW_RD_CLK_BINARY <= 1'b0; + SLOW_WR_CLK_BINARY <= 1'b0; + SPARE_BINARY <= 4'b0; + + case (SYNCHRONOUS_MODE) + "FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE); + #1 $finish; + end + endcase + + end + + wire [7:0] delay_Q0; + wire [7:0] delay_Q1; + wire [7:0] delay_Q2; + wire [7:0] delay_Q3; + wire [7:0] delay_Q4; + wire [7:0] delay_Q5; + wire [7:0] delay_Q6; + wire [7:0] delay_Q7; + wire [7:0] delay_Q8; + wire [7:0] delay_Q9; + wire delay_ALMOSTEMPTY; + wire delay_ALMOSTFULL; + wire delay_EMPTY; + wire delay_FULL; + wire [3:0] delay_SCANOUT; + + wire [3:0] delay_D0; + wire [3:0] delay_D1; + wire [3:0] delay_D2; + wire [3:0] delay_D3; + wire [3:0] delay_D4; + wire [3:0] delay_D7; + wire [3:0] delay_D8; + wire [3:0] delay_D9; + wire [7:0] delay_D5; + wire [7:0] delay_D6; + wire delay_RDCLK; + wire delay_RDEN; + wire delay_RESET; + wire delay_SCANENB = 1'b1; + wire delay_TESTMODEB = 1'b1; + wire delay_TESTREADDISB = 1'b1; + wire delay_TESTWRITEDISB = 1'b1; + wire [3:0] delay_SCANIN = 4'hf; + wire delay_WRCLK; + wire delay_WREN; + wire delay_GSR; + + assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY; + assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL; + assign #(out_delay) EMPTY = delay_EMPTY; + assign #(out_delay) FULL = delay_FULL; + assign #(out_delay) Q0 = delay_Q0; + assign #(out_delay) Q1 = delay_Q1; + assign #(out_delay) Q2 = delay_Q2; + assign #(out_delay) Q3 = delay_Q3; + assign #(out_delay) Q4 = delay_Q4; + assign #(out_delay) Q5 = delay_Q5; + assign #(out_delay) Q6 = delay_Q6; + assign #(out_delay) Q7 = delay_Q7; + assign #(out_delay) Q8 = delay_Q8; + assign #(out_delay) Q9 = delay_Q9; + +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_RDCLK = RDCLK; + assign #(INCLK_DELAY) delay_WRCLK = WRCLK; + + assign #(in_delay) delay_D0 = D0; + assign #(in_delay) delay_D1 = D1; + assign #(in_delay) delay_D2 = D2; + assign #(in_delay) delay_D3 = D3; + assign #(in_delay) delay_D4 = D4; + assign #(in_delay) delay_D5 = D5; + assign #(in_delay) delay_D6 = D6; + assign #(in_delay) delay_D7 = D7; + assign #(in_delay) delay_D8 = D8; + assign #(in_delay) delay_D9 = D9; + assign #(in_delay) delay_RDEN = RDEN; +`endif + assign #(in_delay) delay_RESET = RESET; +`ifndef XIL_TIMING + assign #(in_delay) delay_WREN = WREN; +`endif + assign delay_GSR = GSR; + + SIP_IN_FIFO IN_FIFO_INST + ( + .ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY), + .ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY), + .ARRAY_MODE (ARRAY_MODE_BINARY), + .SLOW_RD_CLK (SLOW_RD_CLK_BINARY), + .SLOW_WR_CLK (SLOW_WR_CLK_BINARY), + .SPARE (SPARE_BINARY), + .SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY), + + .ALMOSTEMPTY (delay_ALMOSTEMPTY), + .ALMOSTFULL (delay_ALMOSTFULL), + .EMPTY (delay_EMPTY), + .FULL (delay_FULL), + .Q0 (delay_Q0), + .Q1 (delay_Q1), + .Q2 (delay_Q2), + .Q3 (delay_Q3), + .Q4 (delay_Q4), + .Q5 (delay_Q5), + .Q6 (delay_Q6), + .Q7 (delay_Q7), + .Q8 (delay_Q8), + .Q9 (delay_Q9), + .SCANOUT (delay_SCANOUT), + .D0 (delay_D0), + .D1 (delay_D1), + .D2 (delay_D2), + .D3 (delay_D3), + .D4 (delay_D4), + .D5 (delay_D5), + .D6 (delay_D6), + .D7 (delay_D7), + .D8 (delay_D8), + .D9 (delay_D9), + .RDCLK (delay_RDCLK), + .RDEN (delay_RDEN), + .RESET (delay_RESET), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .TESTMODEB (delay_TESTMODEB), + .TESTREADDISB (delay_TESTREADDISB), + .TESTWRITEDISB (delay_TESTWRITEDISB), + .WRCLK (delay_WRCLK), + .WREN (delay_WREN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN); + $setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0); + $setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1); + $setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2); + $setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3); + $setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4); + $setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5); + $setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6); + $setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7); + $setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8); + $setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN); + $setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0); + $setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1); + $setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2); + $setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3); + $setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4); + $setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5); + $setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6); + $setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7); + $setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8); + $setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (negedge RESET, 0:0:0, 0, notifier); + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (posedge RESET, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); + ( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10); + ( RDCLK *> EMPTY) = (10:10:10, 10:10:10); + ( RDCLK *> Q0) = (10:10:10, 10:10:10); + ( RDCLK *> Q1) = (10:10:10, 10:10:10); + ( RDCLK *> Q2) = (10:10:10, 10:10:10); + ( RDCLK *> Q3) = (10:10:10, 10:10:10); + ( RDCLK *> Q4) = (10:10:10, 10:10:10); + ( RDCLK *> Q5) = (10:10:10, 10:10:10); + ( RDCLK *> Q6) = (10:10:10, 10:10:10); + ( RDCLK *> Q7) = (10:10:10, 10:10:10); + ( RDCLK *> Q8) = (10:10:10, 10:10:10); + ( RDCLK *> Q9) = (10:10:10, 10:10:10); + ( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10); + ( WRCLK *> FULL) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // IN_FIFO + +`endcelldefine diff --git a/verilog/src/unisims/IOBUF.v b/verilog/src/unisims/IOBUF.v new file mode 100644 index 0000000..25df0d0 --- /dev/null +++ b/verilog/src/unisims/IOBUF.v @@ -0,0 +1,96 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUF (O, IO, I, T); + + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + initial begin + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + end + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (I => IO)= (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/IOBUFDS.v b/verilog/src/unisims/IOBUFDS.v new file mode 100644 index 0000000..f0cbca0 --- /dev/null +++ b/verilog/src/unisims/IOBUFDS.v @@ -0,0 +1,161 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 07/26/07 - Add else to handle x case for o_out (CR 424214). +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 03/19/09 - CR 511590 - Added Z condition handling +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// 10/14/09 - CR 535630 - Added DIFF_TERM attribute. +// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures. +// 12/01/10 - CR 584500 - added attribute SLEW +// 08/08/11 - CR 616816 - ncsim compile error during XIL_TIMING +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/13/12 - 669215 - add parameter DQS_BIAS +// 08/28/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUFDS (O, IO, IOB, I, T); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + localparam MODULE_NAME = "IOBUFDS"; + + + output O; + inout IO, IOB; + input I, T; + + wire i_in, io_in, iob_in, t_in; + reg o_out, io_out, iob_out; + reg O_int; + + reg DQS_BIAS_BINARY = 1'b0; + + wire t_or_gts; + tri0 GTS = glbl.GTS; + + assign i_in = I; + assign t_in = T; + assign io_in = IO; + assign iob_in = IOB; + + assign t_or_gts = GTS || t_in; + assign IO = t_or_gts ? 1'bz : i_in; + assign IOB = t_or_gts ? 1'bz : ~i_in; + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin + $display("DRC Warning : The IOSTANDARD attribute on %s instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", MODULE_NAME, IOSTANDARD); + end + + end + + always @(io_in or iob_in or DQS_BIAS_BINARY) begin + if (io_in == 1'b1 && iob_in == 1'b0) + o_out <= 1'b1; + else if (io_in == 1'b0 && iob_in == 1'b1) + o_out <= 1'b0; + else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if ((io_in === 1'bx) || (iob_in == 1'bx)) + o_out <= 1'bx; + end + +// assign O = (t_in === 1'b0) ? 1'b1 : ((t_in === 1'b1) ? o_out : 1'bx)); + assign O = o_out; + + + +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + (T => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDSE3.v b/verilog/src/unisims/IOBUFDSE3.v new file mode 100644 index 0000000..0560a2f --- /dev/null +++ b/verilog/src/unisims/IOBUFDSE3.v @@ -0,0 +1,369 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Differential Bidirectional I/O Buffer with Offset Calibration +// /___/ /\ Filename : IOBUFDSE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUFDSE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DIFF_TERM = "FALSE", + parameter DQS_BIAS = "FALSE", + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SIM_DEVICE = "ULTRASCALE", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0, + parameter USE_IBUFDISABLE = "FALSE" +)( + output O, + + inout IO, + inout IOB, + + input DCITERMDISABLE, + input I, + input IBUFDISABLE, + input [3:0] OSC, + input [1:0] OSC_EN, + input T +); + +// define constants + localparam MODULE_NAME = "IOBUFDSE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam DIFF_TERM_FALSE = 0; + localparam DIFF_TERM_TRUE = 1; + localparam DQS_BIAS_FALSE = 0; + localparam DQS_BIAS_TRUE = 1; + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_RF = 8; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10; + localparam SIM_DEVICE_VERSAL_HBM = 11; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 12; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 13; + localparam SIM_DEVICE_VERSAL_PREMIUM = 14; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PRIME = 17; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 19; + localparam USE_IBUFDISABLE_FALSE = 0; + localparam USE_IBUFDISABLE_TRUE = 1; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; + localparam [40:1] DIFF_TERM_REG = DIFF_TERM; + localparam [40:1] DQS_BIAS_REG = DQS_BIAS; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE; + localparam [144:1] SIM_DEVICE_REG = SIM_DEVICE; + + wire DIFF_TERM_BIN; + wire DQS_BIAS_BIN; + wire IBUF_LOW_PWR_BIN; + wire USE_IBUFDISABLE_BIN; + wire [4:0] SIM_DEVICE_BIN; + + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg O_out; + wire IO_out; + wire IOB_out; + reg O_OSC_in; + + wire O_delay; + + wire DCITERMDISABLE_in; + wire IBUFDISABLE_in; + wire I_in; + wire IO_in; + wire IOB_in; + wire T_in; + wire [1:0] OSC_EN_in; + wire [3:0] OSC_in; + + wire DCITERMDISABLE_delay; + wire IBUFDISABLE_delay; + wire I_delay; + wire IOB_delay_I; + wire IO_delay_I; + wire IO_delay_O; + wire IOB_delay_O; + wire T_delay; + wire [1:0] OSC_EN_delay; + wire [3:0] OSC_delay; + + wire ts; + integer OSC_int = 0; + wire not_t_or_ibufdisable; + assign not_t_or_ibufdisable = ~T_in || IBUFDISABLE_in; + + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T_in); + bufif0 B1 (IO_out, I_in, ts); + notif0 N1 (IOB_out, I_in, ts); + assign #(out_delay) O = O_delay; + assign #(out_delay) IO = IO_delay_O; + assign #(out_delay) IOB = IOB_delay_O; + +// inputs with no timing checks + assign #(in_delay) IOB_delay_I = IOB; + assign #(in_delay) DCITERMDISABLE_delay = DCITERMDISABLE; + assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE; + assign #(in_delay) I_delay = I; + assign #(in_delay) IO_delay_I = IO; + assign #(in_delay) OSC_EN_delay = OSC_EN; + assign #(in_delay) OSC_delay = OSC; + assign #(in_delay) T_delay = T; + +// assign O_delay = O_out; + assign IO_delay_O = IO_out; + assign IOB_delay_O = IOB_out; + + assign DCITERMDISABLE_in = DCITERMDISABLE_delay; + assign IBUFDISABLE_in = IBUFDISABLE_delay; + assign I_in = I_delay; + assign IO_in = IO_delay_I; + assign IOB_in = IOB_delay_I; + assign OSC_EN_in = OSC_EN_delay; + assign OSC_in = OSC_delay; + assign T_in = T_delay; + + + assign DIFF_TERM_BIN = + (DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE : + (DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE : + DIFF_TERM_FALSE; + + assign DQS_BIAS_BIN = + (DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE : + (DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE : + DQS_BIAS_FALSE; + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + + assign USE_IBUFDISABLE_BIN = + (USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE : + (USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE : + USE_IBUFDISABLE_FALSE; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-105] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin + $display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG); + attr_err = 1'b1; +end + + if ((attr_test == 1'b1) || + ((DQS_BIAS_REG != "FALSE") && + (DQS_BIAS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-103] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + + if ((attr_test == 1'b1) || + ((USE_IBUFDISABLE_REG != "FALSE") && + (USE_IBUFDISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +// begin behavioral model + + wire versal_or_later; + wire [1:0] OSC_EN_in_muxed; + wire [3:0] OSC_in_muxed; + + assign versal_or_later = ( SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE || + SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE_PLUS ) ? 1'b0 : 1'b1; + + assign OSC_in_muxed = versal_or_later ? 4'd0 : OSC_in; + assign OSC_EN_in_muxed = versal_or_later ? 2'd0 : OSC_EN_in; + + + assign O_delay = (OSC_EN_in_muxed === 2'b11) ? O_OSC_in : + (OSC_EN_in_muxed === 2'b10 || OSC_EN_in_muxed === 2'b01) ? 1'bx : + O_out; + + always @ (OSC_in_muxed or OSC_EN_in_muxed) begin + OSC_int = OSC_in_muxed[2:0] * 5; + if (OSC_in_muxed[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in_muxed == 1'b1) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= ~O_OSC_in; + end + end + + initial begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= 1'bx; + + end + + always @(IO_in or IOB_in or DQS_BIAS_BIN or not_t_or_ibufdisable or USE_IBUFDISABLE_BIN) begin + if (USE_IBUFDISABLE_BIN == 1'b1 && not_t_or_ibufdisable == 1'b1) + O_out <= 1'b0; + else if ((USE_IBUFDISABLE_BIN == 1'b1 && not_t_or_ibufdisable == 1'b0) || (USE_IBUFDISABLE_BIN == 1'b0)) begin + if (IO_in == 1'b1 && IOB_in == 1'b0) + O_out <= 1'b1; + else if (IO_in == 1'b0 && IOB_in == 1'b1) + O_out <= 1'b0; + else if ((IO_in === 1'bz || IO_in == 1'b0) && (IOB_in === 1'bz || IOB_in == 1'b1)) + if (DQS_BIAS_BIN == 1'b1) + O_out <= 1'b0; + else + O_out <= 1'bx; + else if ((IO_in === 1'bx) || (IOB_in === 1'bx)) + O_out <= 1'bx; + end + else begin + O_out <= 1'bx; + end + end + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDS_DCIEN.v b/verilog/src/unisims/IOBUFDS_DCIEN.v new file mode 100644 index 0000000..54fc8d6 --- /dev/null +++ b/verilog/src/unisims/IOBUFDS_DCIEN.v @@ -0,0 +1,220 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_DCIEN.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 12/08/10 - Initial version. +// 03/28/11 - CR 603466 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/10/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUFDS_DCIEN (O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IOBUFDS_DCIEN"; + + + output O; + inout IO; + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; + + wire i_in, io_in, iob_in, ibufdisable_in, dcitermdisable_in, t_in, out_val; + reg o_out, io_out, iob_out; + reg O_int; + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + wire t_or_gts; + wire not_t_or_ibufdisable; + + tri0 GTS = glbl.GTS; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((not_t_or_ibufdisable === 1'b1) ? out_val : ((not_t_or_ibufdisable === 1'b0) ? o_out : 1'bx)); + + assign dcitermdisable_in = DCITERMDISABLE; + assign i_in = I; + assign ibufdisable_in = IBUFDISABLE; + assign t_in = T; + assign io_in = IO; + assign iob_in = IOB; + + assign t_or_gts = GTS || t_in; + assign IO = t_or_gts ? 1'bz : i_in; + assign IOB = t_or_gts ? 1'bz : ~i_in; + + assign not_t_or_ibufdisable = ~t_in || ibufdisable_in; + + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin + $display("DRC Warning : The IOSTANDARD attribute on IOBUFDS_DCIEN instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD); + end + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + always @(io_in or iob_in or DQS_BIAS_BINARY) begin + if (io_in == 1'b1 && iob_in == 1'b0) + o_out <= 1'b1; + else if (io_in == 1'b0 && iob_in == 1'b1) + o_out <= 1'b0; + else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if (io_in === 1'bx || iob_in === 1'bx) + o_out <= 1'bx; + end + + +`ifdef XIL_TIMING + specify + (DCITERMDISABLE => O) = (0:0:0, 0:0:0); + (DCITERMDISABLE => IO) = (0:0:0, 0:0:0); + (DCITERMDISABLE => IOB) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => IOB) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + (T => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDS_DIFF_OUT.v b/verilog/src/unisims/IOBUFDS_DIFF_OUT.v new file mode 100644 index 0000000..df64761 --- /dev/null +++ b/verilog/src/unisims/IOBUFDS_DIFF_OUT.v @@ -0,0 +1,170 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_DIFF_OUT.v +// \ \ / \ Timestamp : Tue May 26 17:09:31 PDT 2009 +// \___\/\___\ +// +// Revision: +// 05/26/09 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUFDS_DIFF_OUT (O, OB, IO, IOB, I, TM, TS); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + output OB; + inout IO; + inout IOB; + input I; + input TM; + input TS; + + wire t1, t2; + reg DQS_BIAS_BINARY = 1'b0; + + tri0 GTS = glbl.GTS; + + reg O_out, OB_out; + + or O1 (t1, GTS, TM); + bufif0 B1 (IO, I, t1); + + or O2 (t2, GTS, TS); + notif0 N2 (IOB, I, t2); + + assign O = O_out; + assign OB = OB_out; + + initial begin + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase // case(IBUF_LOW_PWR) + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + + endcase + + + + end + + + always @(IO or IOB or DQS_BIAS_BINARY) begin + if (IO == 1'b1 && IOB == 1'b0) begin + O_out <= IO; + OB_out <= ~IO; + end + else if (IO == 1'b0 && IOB == 1'b1) begin + O_out <= IO; + OB_out <= ~IO; + end + else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin + if (DQS_BIAS_BINARY == 1'b1) begin + O_out <= 1'b0; + OB_out <= 1'b1; + end else begin + O_out <= 1'bx; + OB_out <= 1'bx; + end + end + else begin + O_out <= 1'bx; + OB_out <= 1'bx; + end + end + + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (TM => O) = (0:0:0, 0:0:0); + (TM => OB) = (0:0:0, 0:0:0); + (TM => IO) = (0:0:0, 0:0:0); + (TM => IOB) = (0:0:0, 0:0:0); + (TS => O) = (0:0:0, 0:0:0); + (TS => OB) = (0:0:0, 0:0:0); + (TS => IO) = (0:0:0, 0:0:0); + (TS => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => OB) = (0:0:0, 0:0:0); + (IO => IO) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => OB) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (IOB => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDS_DIFF_OUT_DCIEN.v b/verilog/src/unisims/IOBUFDS_DIFF_OUT_DCIEN.v new file mode 100644 index 0000000..98e7a46 --- /dev/null +++ b/verilog/src/unisims/IOBUFDS_DIFF_OUT_DCIEN.v @@ -0,0 +1,228 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_DIFF_OUT_DCIEN.v +// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010 +// \___\/\___\ +// +// Revision: +// 04/29/10 - Initial version. +// 03/28/11 - CR 603466 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUFDS_DIFF_OUT_DCIEN (O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + output OB; + inout IO; + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input TM; + input TS; + +// define constants + localparam MODULE_NAME = "IOBUFDS_DIFF_OUT_DCIEN"; + + wire t1, t2, out_val, out_b_val; + wire T_OR_IBUFDISABLE_1; + wire T_OR_IBUFDISABLE_2; + + tri0 GTS = glbl.GTS; + + or O1 (t1, GTS, TM); + bufif0 B1 (IO, I, t1); + + or O2 (t2, GTS, TS); + notif0 N2 (IOB, I, t2); + + reg O_int, OB_int; + reg DQS_BIAS_BINARY = 1'b0; + + + initial begin + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + end + + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + assign out_b_val = 1'b1; + end + "ULTRASCALE" : begin + assign out_val = 1'b0; + assign out_b_val = 1'bx; + end + default : begin + assign out_val = 1'b0; + assign out_b_val = 1'b0; + end + endcase + endgenerate + + always @(IO or IOB or DQS_BIAS_BINARY) begin + if (IO == 1'b1 && IOB == 1'b0) begin + O_int <= IO; + OB_int <= ~IO; + end + else if (IO == 1'b0 && IOB == 1'b1) begin + O_int <= IO; + OB_int <= ~IO; + end + else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin + if (DQS_BIAS_BINARY == 1'b1) begin + O_int <= 1'b0; + OB_int <= 1'b1; + end else begin + O_int <= 1'bx; + OB_int <= 1'bx; + end + end + else begin + O_int <= 1'bx; + OB_int <= 1'bx; + end + end + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE; + assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE; + assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? out_val : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx; + assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? out_b_val : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx; + end + "FALSE" : begin + assign O = O_int; + assign OB = OB_int; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + (DCITERMDISABLE => O) = (0:0:0, 0:0:0); + (DCITERMDISABLE => OB) = (0:0:0, 0:0:0); + (DCITERMDISABLE => IO) = (0:0:0, 0:0:0); + (DCITERMDISABLE => IOB) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => OB) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => OB) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => OB) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => IOB) = (0:0:0, 0:0:0); + (TM => O) = (0:0:0, 0:0:0); + (TM => OB) = (0:0:0, 0:0:0); + (TM => IO) = (0:0:0, 0:0:0); + (TM => IOB) = (0:0:0, 0:0:0); + (TS => O) = (0:0:0, 0:0:0); + (TS => OB) = (0:0:0, 0:0:0); + (TS => IO) = (0:0:0, 0:0:0); + (TS => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDS_DIFF_OUT_INTERMDISABLE.v b/verilog/src/unisims/IOBUFDS_DIFF_OUT_INTERMDISABLE.v new file mode 100644 index 0000000..7169194 --- /dev/null +++ b/verilog/src/unisims/IOBUFDS_DIFF_OUT_INTERMDISABLE.v @@ -0,0 +1,224 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_DIFF_OUT_INTERMDISABLE.v +// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011 +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS); + + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + output OB; + inout IO; + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input TM; + input TS; + +// define constants + localparam MODULE_NAME = "IOBUFDS_DIFF_OUT_INTERMDISABLE"; + + wire t1, t2,out_val,out_b_val; + wire T_OR_IBUFDISABLE_1; + wire T_OR_IBUFDISABLE_2; + reg DQS_BIAS_BINARY = 1'b0; + + tri0 GTS = glbl.GTS; + + or O1 (t1, GTS, TM); + bufif0 B1 (IO, I, t1); + + or O2 (t2, GTS, TS); + notif0 N2 (IOB, I, t2); + + reg O_int, OB_int; + + initial begin + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + assign out_b_val = 1'b1; + end + "ULTRASCALE" : begin + assign out_val = 1'b0; + assign out_b_val = 1'bx; + end + default : begin + assign out_val = 1'b0; + assign out_b_val = 1'b0; + end + endcase + endgenerate + + always @(IO or IOB or DQS_BIAS_BINARY) begin + if (IO == 1'b1 && IOB == 1'b0) begin + O_int <= IO; + OB_int <= ~IO; + end + else if (IO == 1'b0 && IOB == 1'b1) begin + O_int <= IO; + OB_int <= ~IO; + end + else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin + if (DQS_BIAS_BINARY == 1'b1) begin + O_int <= 1'b0; + OB_int <= 1'b1; + end else begin + O_int <= 1'bx; + OB_int <= 1'bx; + end + end + else begin + O_int <= 1'bx; + OB_int <= 1'bx; + end + end + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE; + assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE; + assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? out_val : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx; + assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? out_b_val : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx; + end + "FALSE" : begin + assign O = O_int; + assign OB = OB_int; + end + endcase + endgenerate +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => OB) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => OB) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => OB) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => IOB) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => OB) = (0:0:0, 0:0:0); + (INTERMDISABLE => IO) = (0:0:0, 0:0:0); + (INTERMDISABLE => IOB) = (0:0:0, 0:0:0); + (TM => O) = (0:0:0, 0:0:0); + (TM => OB) = (0:0:0, 0:0:0); + (TM => IO) = (0:0:0, 0:0:0); + (TM => IOB) = (0:0:0, 0:0:0); + (TS => O) = (0:0:0, 0:0:0); + (TS => OB) = (0:0:0, 0:0:0); + (TS => IO) = (0:0:0, 0:0:0); + (TS => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFDS_INTERMDISABLE.v b/verilog/src/unisims/IOBUFDS_INTERMDISABLE.v new file mode 100644 index 0000000..9afb76b --- /dev/null +++ b/verilog/src/unisims/IOBUFDS_INTERMDISABLE.v @@ -0,0 +1,222 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_INTERMDISABLE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/13/12 - 669215 - add parameter DQS_BIAS +// 08/29/12 - 675511 - add DQS_BIAS functionality +// 09/11/12 - 677753 - remove X glitch on O +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUFDS_INTERMDISABLE (O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + + localparam MODULE_NAME = "IOBUFDS_INTERMDISABLE"; + + + output O; + inout IO; + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; + + wire i_in, io_in, iob_in, ibufdisable_in, intermdisable_in, t_in; + reg o_out, io_out, iob_out; + reg O_int; + wire out_val; + + reg DQS_BIAS_BINARY = 1'b0; + reg USE_IBUFDISABLE_BINARY = 1'b0; + + wire t_or_gts; + wire not_t_or_ibufdisable; +// wire disable_out; + + tri0 GTS = glbl.GTS; + + assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out : + ((not_t_or_ibufdisable === 1'b1) ? out_val : ((not_t_or_ibufdisable === 1'b0) ? o_out : 1'bx)); + + assign intermdisable_in = INTERMDISABLE; + assign i_in = I; + assign ibufdisable_in = IBUFDISABLE; + assign t_in = T; + assign io_in = IO; + assign iob_in = IOB; + + assign t_or_gts = GTS || t_in; + assign IO = t_or_gts ? 1'bz : i_in; + assign IOB = t_or_gts ? 1'bz : ~i_in; + +// assign disable_out = intermdisable_in && ibufdisable_in; + assign not_t_or_ibufdisable = ~t_in || ibufdisable_in; + + + initial begin + + case (DQS_BIAS) + + "TRUE" : DQS_BIAS_BINARY <= #1 1'b1; + "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS); + #1 $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM); + #1 $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR); + #1 $finish; + end + + endcase + + if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin + $display("DRC Warning : The IOSTANDARD attribute on IOBUFDS_DCIEN instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD); + end + + case (USE_IBUFDISABLE) + + "TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1; + "FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE); + #1 $finish; + end + + endcase + + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + end + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + always @(io_in or iob_in or DQS_BIAS_BINARY) begin + if (io_in == 1'b1 && iob_in == 1'b0) + o_out <= 1'b1; + else if (io_in == 1'b0 && iob_in == 1'b1) + o_out <= 1'b0; + else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1)) + if (DQS_BIAS_BINARY == 1'b1) + o_out <= 1'b0; + else + o_out <= 1'bx; + else if (io_in === 1'bx || iob_in === 1'bx) + o_out <= 1'bx; + end + + +`ifdef XIL_TIMING + specify + (I => IO) = (0:0:0, 0:0:0); + (I => IOB) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IO => IOB) = (0:0:0, 0:0:0); + (IOB => O) = (0:0:0, 0:0:0); + (IOB => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (IBUFDISABLE => IOB) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => IO) = (0:0:0, 0:0:0); + (INTERMDISABLE => IOB) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + (T => IOB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUFE3.v b/verilog/src/unisims/IOBUFE3.v new file mode 100644 index 0000000..e197b6f --- /dev/null +++ b/verilog/src/unisims/IOBUFE3.v @@ -0,0 +1,326 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Bidirectional I/O Buffer with Offset Calibration and VREF Tuning +// /___/ /\ Filename : IOBUFE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUFE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DRIVE = 12, + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SIM_DEVICE = "ULTRASCALE", + parameter integer SIM_INPUT_BUFFER_OFFSET = 0, + parameter USE_IBUFDISABLE = "FALSE" +)( + output O, + + inout IO, + + input DCITERMDISABLE, + input I, + input IBUFDISABLE, + input [3:0] OSC, + input OSC_EN, + input T, + input VREF +); + +// define constants + localparam MODULE_NAME = "IOBUFE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_VERSAL_AI_CORE = 2; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 5; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_RF = 8; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10; + localparam SIM_DEVICE_VERSAL_HBM = 11; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 12; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 13; + localparam SIM_DEVICE_VERSAL_PREMIUM = 14; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 15; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 16; + localparam SIM_DEVICE_VERSAL_PRIME = 17; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 18; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 19; + localparam USE_IBUFDISABLE_FALSE = 0; + localparam USE_IBUFDISABLE_TRUE = 1; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; + localparam [4:0] DRIVE_REG = DRIVE; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET; + localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE; + localparam [144:1] SIM_DEVICE_REG = SIM_DEVICE; + + wire [4:0] DRIVE_BIN; + wire IBUF_LOW_PWR_BIN; + wire [4:0] SIM_DEVICE_BIN; + wire USE_IBUFDISABLE_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire O_out; + reg O_OSC_in; + + wire O_delay; + + wire DCITERMDISABLE_in; + wire IBUFDISABLE_in; + wire I_in; + wire IO_in; + wire IO_out; + wire OSC_EN_in; + wire T_in; + wire VREF_in; + wire [3:0] OSC_in; + + wire DCITERMDISABLE_delay; + wire IBUFDISABLE_delay; + wire I_delay; + wire OSC_EN_delay; + wire T_delay; + wire IO_delay_O; + wire IO_delay_I; + wire VREF_delay; + wire [3:0] OSC_delay; + + assign #(out_delay) O = O_delay; + + +// inputs with no timing checks + assign #(in_delay) DCITERMDISABLE_delay = DCITERMDISABLE; + assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE; + assign #(in_delay) I_delay = I; + assign #(in_delay) IO_delay_I = IO; + assign #(in_delay) IO = IO_delay_O; + assign #(in_delay) OSC_EN_delay = OSC_EN; + assign #(in_delay) OSC_delay = OSC; + assign #(in_delay) T_delay = T; + assign #(in_delay) VREF_delay = VREF; + + assign O_delay = O_out; + assign IO_delay_O = IO_out; + + assign DCITERMDISABLE_in = DCITERMDISABLE_delay; + assign IBUFDISABLE_in = IBUFDISABLE_delay; + assign I_in = I_delay; + assign IO_in = IO_delay_I; + assign OSC_EN_in = OSC_EN_delay; + assign OSC_in = OSC_delay; + assign T_in = T_delay; + assign VREF_in = VREF_delay; + + wire ts; + integer OSC_int = 0; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T_in); + bufif0 T1 (IO_out, I_in, ts); + + + assign DRIVE_BIN = DRIVE_REG; + + assign IBUF_LOW_PWR_BIN = + (IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE : + (IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE : + IBUF_LOW_PWR_TRUE; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign USE_IBUFDISABLE_BIN = + (USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE : + (USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE : + USE_IBUFDISABLE_FALSE; + + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DRIVE_REG < 2) || (DRIVE_REG > 24))) begin + $display("Error: [Unisim %s-101] DRIVE attribute is set to %d. Legal values for this attribute are 2 to 24. Instance: %m", MODULE_NAME, DRIVE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin + $display("Error: [Unisim %s-104] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-102] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ( (SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_IBUFDISABLE_REG != "FALSE") && + (USE_IBUFDISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +// begin behavioral model + wire not_t_or_ibufdisable; + wire versal_or_later; + wire OSC_EN_in_muxed; + wire [3:0] OSC_in_muxed; + + assign versal_or_later = ( SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE || + SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE_PLUS ) ? 1'b0 : 1'b1; + + assign OSC_in_muxed = versal_or_later ? 4'd0 : OSC_in; + assign OSC_EN_in_muxed = versal_or_later ? 1'b0 : OSC_EN_in; + + + initial begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= 1'bx; + end + + assign not_t_or_ibufdisable = ~T_in || IBUFDISABLE_in; + + generate + case (USE_IBUFDISABLE_REG) + "TRUE" : begin + assign O_out = (not_t_or_ibufdisable == 0)? (OSC_EN_in_muxed) ? O_OSC_in : IO_in : (not_t_or_ibufdisable == 1 && OSC_EN_in_muxed != 1)? 1'b0 : 1'bx; + end + "FALSE" : begin + assign O_out = (OSC_EN_in_muxed) ? O_OSC_in : IO_in; + end + endcase + endgenerate + + always @ (OSC_in_muxed or OSC_EN_in_muxed) begin + OSC_int = OSC_in_muxed[2:0] * 5; + if (OSC_in_muxed[3] == 1'b0 ) + OSC_int = -1*OSC_int; + + if(OSC_EN_in_muxed == 1'b1) begin + if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) + O_OSC_in <= 1'b0; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) + O_OSC_in <= 1'b1; + else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) + O_OSC_in <= ~O_OSC_in; + end + end + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUF_ANALOG.v b/verilog/src/unisims/IOBUF_ANALOG.v new file mode 100644 index 0000000..fe15d41 --- /dev/null +++ b/verilog/src/unisims/IOBUF_ANALOG.v @@ -0,0 +1,130 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Analog Auxiliary SYSMON Input Output Buffer +// /___/ /\ Filename : IOBUF_ANALOG.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module IOBUF_ANALOG #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DRIVE = 12, + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SLEW = "SLOW" +)( + output O, + + inout IO, + + input I, + input T +); + +// define constants + localparam MODULE_NAME = "IOBUF_ANALOG"; + +// Parameter encodings and registers + localparam IBUF_LOW_PWR_FALSE = 1; + localparam IBUF_LOW_PWR_TRUE = 0; + localparam IOSTANDARD_DEFAULT = 0; + localparam SLEW_FAST = 1; + localparam SLEW_SLOW = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "IOBUF_ANALOG_dr.v" +`else + localparam [4:0] DRIVE_REG = DRIVE; + localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR; + localparam [56:1] IOSTANDARD_REG = IOSTANDARD; + localparam [32:1] SLEW_REG = SLEW; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire I_in; + wire T_in; + + assign I_in = (I === 1'bz) || I; // rv 1 + assign T_in = (T === 1'bz) || T; // rv 1 + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DRIVE_REG < 2) || (DRIVE_REG > 24))) begin + $display("Error: [Unisim %s-101] DRIVE attribute is set to %d. Legal values for this attribute are 2 to 24. Instance: %m", MODULE_NAME, DRIVE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IBUF_LOW_PWR_REG != "TRUE") && + (IBUF_LOW_PWR_REG != "FALSE"))) begin + $display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SLEW_REG != "SLOW") && + (SLEW_REG != "FAST"))) begin + $display("Error: [Unisim %s-109] SLEW attribute is set to %s. Legal values for this attribute are SLOW or FAST. Instance: %m", MODULE_NAME, SLEW_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign O = IO; + assign IO = ~T_in ? I_in : 1'bz; + +specify + (I => IO) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUF_DCIEN.v b/verilog/src/unisims/IOBUF_DCIEN.v new file mode 100644 index 0000000..7f15cce --- /dev/null +++ b/verilog/src/unisims/IOBUF_DCIEN.v @@ -0,0 +1,156 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF_DCIEN.v +// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010 +// \___\/\___\ +// +// Revision: +// 12/08/10 - Initial version. +// 03/28/11 - CR 603466 fix +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUF_DCIEN (O, IO, DCITERMDISABLE, I, IBUFDISABLE, T); + + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + inout IO; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; + +// define constants + localparam MODULE_NAME = "IOBUF_DCIEN"; + + wire ts; + wire T_OR_IBUFDISABLE; + wire out_val; + wire disable_out; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + and a1 (disable_out, DCITERMDISABLE, IBUFDISABLE); + +// buf B1 (O, IO); + + initial begin + + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-105] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + end // initial begin + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE; + assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx; + end + "FALSE" : begin + assign O = IO; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + + (DCITERMDISABLE => O) = (0:0:0, 0:0:0); + (DCITERMDISABLE => IO) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/IOBUF_INTERMDISABLE.v b/verilog/src/unisims/IOBUF_INTERMDISABLE.v new file mode 100644 index 0000000..c96e5bf --- /dev/null +++ b/verilog/src/unisims/IOBUF_INTERMDISABLE.v @@ -0,0 +1,152 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF_INTERMDISABLE.v +// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011 +// \___\/\___\ +// +// Revision: +// 04/20/11 - Initial version. +// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active +// 08/31/11 - CR 623170 -- Tristate powergating support +// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE +// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module IOBUF_INTERMDISABLE (O, IO, I, IBUFDISABLE, INTERMDISABLE, T); + + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + output O; + inout IO; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; + +// define constants + localparam MODULE_NAME = "IOBUF_INTERMDISABLE"; + + wire ts,out_val; + wire T_OR_IBUFDISABLE; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + +// buf B1 (O, IO); + + initial begin + + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + #1 $finish; + end + + endcase + if ((SIM_DEVICE != "7SERIES") && + (SIM_DEVICE != "ULTRASCALE") && + (SIM_DEVICE != "VERSAL_AI_CORE") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE != "VERSAL_AI_EDGE") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE != "VERSAL_AI_RF") && + (SIM_DEVICE != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE != "VERSAL_HBM") && + (SIM_DEVICE != "VERSAL_HBM_ES1") && + (SIM_DEVICE != "VERSAL_HBM_ES2") && + (SIM_DEVICE != "VERSAL_PREMIUM") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE != "VERSAL_PRIME") && + (SIM_DEVICE != "VERSAL_PRIME_ES1") && + (SIM_DEVICE != "VERSAL_PRIME_ES2")) begin + $display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + #1 $finish; + end + + + end // initial begin + generate + case (SIM_DEVICE) + "7SERIES" : begin + assign out_val = 1'b1; + end + default : begin + assign out_val = 1'b0; + end + endcase + endgenerate + + generate + case (USE_IBUFDISABLE) + "TRUE" : begin + assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE; + assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx; + end + "FALSE" : begin + assign O = IO; + end + endcase + endgenerate + +`ifdef XIL_TIMING + specify + + (I => O) = (0:0:0, 0:0:0); + (I => IO) = (0:0:0, 0:0:0); + (IO => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => O) = (0:0:0, 0:0:0); + (IBUFDISABLE => IO) = (0:0:0, 0:0:0); + (INTERMDISABLE => O) = (0:0:0, 0:0:0); + (INTERMDISABLE => IO) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => IO) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ISERDES.v b/verilog/src/unisims/ISERDES.v new file mode 100644 index 0000000..dfcadae --- /dev/null +++ b/verilog/src/unisims/ISERDES.v @@ -0,0 +1,1495 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Input Deserializer +// /___/ /\ Filename : ISERDES.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus. +// 03/18/05 - Changed SIM_TAPDELAY_VALUE to 75 from 78. +// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV +// 07/19/06 - CR 234556 fix. Added SIM_DELAY_D, SIM_SETUP_D_CLK and SIM_HOLD_D_CLK +// 10/13/06 - CR 424503 fix. False setup/hold warnings during post ngd simulation +// 10/13/06 - Fixed CR 426606 +// 06/06/07 - Added wire declaration for internal signals +// 07/02/07 - CR 441960 -- made some params into localparams +// 04/15/08 - CR 468871 Negative SetupHold fix +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR); + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKDIV; + input D; + input DLYCE; + input DLYINC; + input DLYRST; + input OCLK; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + parameter integer SIM_DELAY_D = 0; + parameter integer SIM_SETUP_D_CLK = 0; + parameter integer SIM_HOLD_D_CLK = 0; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + localparam DELAY_D = (IOBDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0; + + integer delay_count, delay_count_int; + integer clk_change_time, data_change_time; + integer return_code = 0; + +//----------------------------------------------------------------- +//-------------- Function xsetuphold_chk ------------------------- +//----------------------------------------------------------------- + function xsetuphold_chk; + input integer clk_time; + input integer data_time; + begin + xsetuphold_chk = 0; + if(data_time > clk_time) + begin +// CR 424503 +// if((data_time - clk_time) <= SIM_HOLD_D_CLK) + if((data_time - clk_time) < SIM_HOLD_D_CLK) + begin +// write_hold_message; + $display ("** Error %m \$hold(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_HOLD_D_CLK); + xsetuphold_chk = 2; + end + + end + else + begin +// CR 424503 +// if((clk_time - data_time) <= SIM_SETUP_D_CLK) + if((clk_time - data_time) < SIM_SETUP_D_CLK) + begin +// write_setup_message; + $display ("** Error %m \$setup(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_SETUP_D_CLK); + xsetuphold_chk = 1; + end + end + end + endfunction + + tri0 GSR = glbl.GSR; + + reg [1:0] sel; + reg [3:0] data_width_int; + reg bts_q1, bts_q2, bts_q3; + reg c23, c45, c67; + reg ce1r, ce2r; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + reg ice, memmux, q2pmux; + reg mux, mux1, muxc; + reg notifier; + reg clkdiv_int, clkdivmux; + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg num_ce_int; + reg qr1, qr2, qhc1, qhc2, qlc1, qlc2; + reg shiftn2_in, shiftn1_in; + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg serdes_mode_int, data_rate_int, bitslip_enable_int; + reg d_delay, o_delay; + + wire shiftout1_out, shiftout2_out; + wire [1:0] sel1; + wire [2:0] bsmux; + wire [3:0] selrnk3; + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63; + + wire bitslip_in; + wire ce1_in; + wire ce2_in; + wire clk_in; + wire clkdiv_in; + wire d_in; + wire dlyce_in; + wire dlyinc_in; + wire dlyrst_in; + wire gsr_in; + wire oclk_in; + wire rev_in; + wire sr_in; + wire shiftin1_in; + wire shiftin2_in; + + buf b_o (O, o_out); + buf b_q1 (Q1, q1_out); + buf b_q2 (Q2, q2_out); + buf b_q3 (Q3, q3_out); + buf b_q4 (Q4, q4_out); + buf b_q5 (Q5, q5_out); + buf b_q6 (Q6, q6_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + + buf b_bitslip (bitslip_in, BITSLIP); + buf b_ce1 (ce1_in, CE1); + buf b_ce2 (ce2_in, CE2); + buf b_clk (clk_in, CLK); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d (d_in, D); + buf b_dlyce (dlyce_in, DLYCE); + buf b_dlyinc (dlyinc_in, DLYINC); + buf b_dlyrst (dlyrst_in, DLYRST); + buf b_gsr (gsr_in, GSR); + buf b_oclk (oclk_in, OCLK); + buf b_rev (rev_in, REV); + buf b_sr (sr_in, SR); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + +// WARNING !!!: This model may not work properly if the +// following parameters are changed. + +// xilinx_internal_parameter on + + parameter integer SIM_TAPDELAY_VALUE = 75; + +// Parameter declarations for delays + localparam ffinp = 300; + localparam mxinp1 = 60; + localparam mxinp2 = 120; + +// Delay parameters + + localparam ffice = 300; + localparam mxice = 60; + +// Delay parameter assignment + + localparam ffbsc = 300; + localparam mxbsc = 60; + + localparam mxinp1_my = 0; + +// xilinx_internal_parameter off + + initial begin + +// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin + $display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."); + #1 $finish; + end + else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin + $display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."); + #1 $finish; + end + +// ------------------------------------------------------------------------------------ + + if (IOBDELAY_VALUE < 0 || IOBDELAY_VALUE > 63) begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_VALUE on ISERDES instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IOBDELAY_VALUE); + #1 $finish; + + end + + + if (IOBDELAY_TYPE != "DEFAULT" && IOBDELAY_TYPE != "FIXED" && IOBDELAY_TYPE != "VARIABLE") begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IOBDELAY_TYPE); + #1 $finish; + + end + + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + endcase // case(SERDES_MODE) + + + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + #1 $finish; + end + endcase // case(DATA_RATE) + + + case (BITSLIP_ENABLE) + + "FALSE" : bitslip_enable_int <= 1'b0; + "TRUE" : bitslip_enable_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE); + #1 $finish; + end + + endcase // case(BITSLIP_ENABLE) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + + + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDES instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + #1 $finish; + end + + endcase // case(NUM_CE) + + end // initial begin + + + assign sel1 = {serdes_mode_int, data_rate_int}; + + assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00}; + + assign bsmux = {bitslip_enable_int, data_rate_int, muxc}; + + + +// GSR + always @(gsr_in) begin + + if (gsr_in == 1'b1) begin + + if (IOBDELAY_TYPE == "DEFAULT") + + assign delay_count = 0; + + else + + assign delay_count = IOBDELAY_VALUE; + + assign bts_q3 = 1'b0; + assign bts_q2 = 1'b0; + assign bts_q1 = 1'b0; + assign clkdiv_int = 1'b0; + + assign ce1r = 1'b0; + assign ce2r = 1'b0; + + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + + end + else if (gsr_in == 1'b0) begin + + deassign delay_count; + + deassign bts_q3; + deassign bts_q2; + deassign bts_q1; + deassign clkdiv_int; + + deassign ce1r; + deassign ce2r; + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + + end // if (gsr_in == 1'b0) + end // always @ (gsr_in) + + + +// IDELAY + always @(posedge clkdiv_in) begin + + if (IOBDELAY_TYPE == "VARIABLE") begin + + if (dlyrst_in == 1'b1) begin + + delay_count = IOBDELAY_VALUE; + + end + else if (dlyrst_in == 1'b0 && dlyce_in == 1'b1) begin + + if (dlyinc_in == 1'b1) begin + + if (delay_count < 63) + + delay_count = delay_count + 1; + + else if (delay_count == 63) + + delay_count = 0; + + end + else if (dlyinc_in == 1'b0) begin + + if (delay_count > 0) + + delay_count = delay_count - 1; + + else if (delay_count == 0) + + delay_count = 63; + end + + end + + end // if (IOBDELAY_TYPE == "VARIABLE") + + end // always @ (posedge clkdiv_in) + + +// delay chain + assign #DELAY_D delay_chain_0 = d_in; + assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0; + assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1; + assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2; + assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3; + assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4; + assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5; + assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6; + assign #SIM_TAPDELAY_VALUE delay_chain_8 = delay_chain_7; + assign #SIM_TAPDELAY_VALUE delay_chain_9 = delay_chain_8; + assign #SIM_TAPDELAY_VALUE delay_chain_10 = delay_chain_9; + assign #SIM_TAPDELAY_VALUE delay_chain_11 = delay_chain_10; + assign #SIM_TAPDELAY_VALUE delay_chain_12 = delay_chain_11; + assign #SIM_TAPDELAY_VALUE delay_chain_13 = delay_chain_12; + assign #SIM_TAPDELAY_VALUE delay_chain_14 = delay_chain_13; + assign #SIM_TAPDELAY_VALUE delay_chain_15 = delay_chain_14; + assign #SIM_TAPDELAY_VALUE delay_chain_16 = delay_chain_15; + assign #SIM_TAPDELAY_VALUE delay_chain_17 = delay_chain_16; + assign #SIM_TAPDELAY_VALUE delay_chain_18 = delay_chain_17; + assign #SIM_TAPDELAY_VALUE delay_chain_19 = delay_chain_18; + assign #SIM_TAPDELAY_VALUE delay_chain_20 = delay_chain_19; + assign #SIM_TAPDELAY_VALUE delay_chain_21 = delay_chain_20; + assign #SIM_TAPDELAY_VALUE delay_chain_22 = delay_chain_21; + assign #SIM_TAPDELAY_VALUE delay_chain_23 = delay_chain_22; + assign #SIM_TAPDELAY_VALUE delay_chain_24 = delay_chain_23; + assign #SIM_TAPDELAY_VALUE delay_chain_25 = delay_chain_24; + assign #SIM_TAPDELAY_VALUE delay_chain_26 = delay_chain_25; + assign #SIM_TAPDELAY_VALUE delay_chain_27 = delay_chain_26; + assign #SIM_TAPDELAY_VALUE delay_chain_28 = delay_chain_27; + assign #SIM_TAPDELAY_VALUE delay_chain_29 = delay_chain_28; + assign #SIM_TAPDELAY_VALUE delay_chain_30 = delay_chain_29; + assign #SIM_TAPDELAY_VALUE delay_chain_31 = delay_chain_30; + assign #SIM_TAPDELAY_VALUE delay_chain_32 = delay_chain_31; + assign #SIM_TAPDELAY_VALUE delay_chain_33 = delay_chain_32; + assign #SIM_TAPDELAY_VALUE delay_chain_34 = delay_chain_33; + assign #SIM_TAPDELAY_VALUE delay_chain_35 = delay_chain_34; + assign #SIM_TAPDELAY_VALUE delay_chain_36 = delay_chain_35; + assign #SIM_TAPDELAY_VALUE delay_chain_37 = delay_chain_36; + assign #SIM_TAPDELAY_VALUE delay_chain_38 = delay_chain_37; + assign #SIM_TAPDELAY_VALUE delay_chain_39 = delay_chain_38; + assign #SIM_TAPDELAY_VALUE delay_chain_40 = delay_chain_39; + assign #SIM_TAPDELAY_VALUE delay_chain_41 = delay_chain_40; + assign #SIM_TAPDELAY_VALUE delay_chain_42 = delay_chain_41; + assign #SIM_TAPDELAY_VALUE delay_chain_43 = delay_chain_42; + assign #SIM_TAPDELAY_VALUE delay_chain_44 = delay_chain_43; + assign #SIM_TAPDELAY_VALUE delay_chain_45 = delay_chain_44; + assign #SIM_TAPDELAY_VALUE delay_chain_46 = delay_chain_45; + assign #SIM_TAPDELAY_VALUE delay_chain_47 = delay_chain_46; + assign #SIM_TAPDELAY_VALUE delay_chain_48 = delay_chain_47; + assign #SIM_TAPDELAY_VALUE delay_chain_49 = delay_chain_48; + assign #SIM_TAPDELAY_VALUE delay_chain_50 = delay_chain_49; + assign #SIM_TAPDELAY_VALUE delay_chain_51 = delay_chain_50; + assign #SIM_TAPDELAY_VALUE delay_chain_52 = delay_chain_51; + assign #SIM_TAPDELAY_VALUE delay_chain_53 = delay_chain_52; + assign #SIM_TAPDELAY_VALUE delay_chain_54 = delay_chain_53; + assign #SIM_TAPDELAY_VALUE delay_chain_55 = delay_chain_54; + assign #SIM_TAPDELAY_VALUE delay_chain_56 = delay_chain_55; + assign #SIM_TAPDELAY_VALUE delay_chain_57 = delay_chain_56; + assign #SIM_TAPDELAY_VALUE delay_chain_58 = delay_chain_57; + assign #SIM_TAPDELAY_VALUE delay_chain_59 = delay_chain_58; + assign #SIM_TAPDELAY_VALUE delay_chain_60 = delay_chain_59; + assign #SIM_TAPDELAY_VALUE delay_chain_61 = delay_chain_60; + assign #SIM_TAPDELAY_VALUE delay_chain_62 = delay_chain_61; + assign #SIM_TAPDELAY_VALUE delay_chain_63 = delay_chain_62; + + +// assign delay + always @(delay_count_int) begin + + case (delay_count_int) + 0: assign d_delay = delay_chain_0; + 1: assign d_delay = delay_chain_1; + 2: assign d_delay = delay_chain_2; + 3: assign d_delay = delay_chain_3; + 4: assign d_delay = delay_chain_4; + 5: assign d_delay = delay_chain_5; + 6: assign d_delay = delay_chain_6; + 7: assign d_delay = delay_chain_7; + 8: assign d_delay = delay_chain_8; + 9: assign d_delay = delay_chain_9; + 10: assign d_delay = delay_chain_10; + 11: assign d_delay = delay_chain_11; + 12: assign d_delay = delay_chain_12; + 13: assign d_delay = delay_chain_13; + 14: assign d_delay = delay_chain_14; + 15: assign d_delay = delay_chain_15; + 16: assign d_delay = delay_chain_16; + 17: assign d_delay = delay_chain_17; + 18: assign d_delay = delay_chain_18; + 19: assign d_delay = delay_chain_19; + 20: assign d_delay = delay_chain_20; + 21: assign d_delay = delay_chain_21; + 22: assign d_delay = delay_chain_22; + 23: assign d_delay = delay_chain_23; + 24: assign d_delay = delay_chain_24; + 25: assign d_delay = delay_chain_25; + 26: assign d_delay = delay_chain_26; + 27: assign d_delay = delay_chain_27; + 28: assign d_delay = delay_chain_28; + 29: assign d_delay = delay_chain_29; + 30: assign d_delay = delay_chain_30; + 31: assign d_delay = delay_chain_31; + 32: assign d_delay = delay_chain_32; + 33: assign d_delay = delay_chain_33; + 34: assign d_delay = delay_chain_34; + 35: assign d_delay = delay_chain_35; + 36: assign d_delay = delay_chain_36; + 37: assign d_delay = delay_chain_37; + 38: assign d_delay = delay_chain_38; + 39: assign d_delay = delay_chain_39; + 40: assign d_delay = delay_chain_40; + 41: assign d_delay = delay_chain_41; + 42: assign d_delay = delay_chain_42; + 43: assign d_delay = delay_chain_43; + 44: assign d_delay = delay_chain_44; + 45: assign d_delay = delay_chain_45; + 46: assign d_delay = delay_chain_46; + 47: assign d_delay = delay_chain_47; + 48: assign d_delay = delay_chain_48; + 49: assign d_delay = delay_chain_49; + 50: assign d_delay = delay_chain_50; + 51: assign d_delay = delay_chain_51; + 52: assign d_delay = delay_chain_52; + 53: assign d_delay = delay_chain_53; + 54: assign d_delay = delay_chain_54; + 55: assign d_delay = delay_chain_55; + 56: assign d_delay = delay_chain_56; + 57: assign d_delay = delay_chain_57; + 58: assign d_delay = delay_chain_58; + 59: assign d_delay = delay_chain_59; + 60: assign d_delay = delay_chain_60; + 61: assign d_delay = delay_chain_61; + 62: assign d_delay = delay_chain_62; + 63: assign d_delay = delay_chain_63; + default: + assign d_delay = delay_chain_0; + + endcase + end // always @ (delay_count_int) + + +// to workaround the glitches generated by mux of assign delay above + always @(delay_count) + delay_count_int <= #0 delay_count; + + +// Mux to O and o_delay + always @(d_in or d_delay) begin + + case (IOBDELAY) + + "NONE" : begin + o_delay <= d_in; + o_out <= d_in; + end + "IBUF" : begin + o_delay <= d_in; + o_out <= d_delay; + end + "IFD" : begin + o_delay <= d_delay; + o_out <= d_in; + end + "BOTH" : begin + o_delay <= d_delay; + o_out <= d_delay; + end + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDES instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + $finish; + end + + endcase // case(IOBDELAY) + + end // always @ (d_in or d_delay) + + +// 1st rank of registers + +// Asynchronous Operation + always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin +// 1st flop in rank 1 that is full featured + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1)) + + q1rnk1 <= # ffinp SRVAL_Q1; + + else if (rev_in == 1'b1) + + q1rnk1 <= # ffinp !SRVAL_Q1; + + else if (ice == 1'b1) + + q1rnk1 <= # ffinp o_delay; + + end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + + always @(posedge clk_in or posedge sr_in) begin +// rest of flops which are not full featured and don't have clock options + + if (sr_in == 1'b1) begin + + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + + end + else begin + + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + + end + + end // always @ (posedge clk_in or sr_in) + + +// 2nd flop in rank 1 + +// Asynchronous Operation + always @(negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1)) + + q2nrnk1 <= # ffinp SRVAL_Q2; + + else if (rev_in == 1'b1) + + q2nrnk1 <= # ffinp !SRVAL_Q2; + + else if (ice == 1'b1) + + q2nrnk1 <= # ffinp o_delay; + + end // always @ (negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 4th flop in rank 1 operating on the posedge for networking +// Asynchronous Operation + always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1)) + + q2prnk1 <= # ffinp SRVAL_Q4; + + else if (rev_in == 1'b1) + + q2prnk1 <= # ffinp !SRVAL_Q4; + + else if (ice == 1'b1) + + q2prnk1 <= # ffinp q2nrnk1; + + end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 3rd flop in 2nd rank which is full featured and has +// a choice of being clocked by oclk or clk + +// Asynchronous Operation + always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1)) + + q1prnk1 <= # ffinp SRVAL_Q3; + + else if (rev_in == 1'b1) + + q1prnk1 <= # ffinp !SRVAL_Q3; + + else if (ice == 1'b1) + + q1prnk1 <= # ffinp q1rnk1; + + end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + always @(posedge memmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + + end + else begin + + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + + end + + end // always @ (posedge memmux or posedge sr_in) + + +////////////////////////////////////////// +// Mux elements for the 1st rank +//////////////////////////////////////// + +// Optional inverter for q2p (4th flop in rank1) + always @ (memmux) begin + + case (INTERFACE_TYPE) + + "MEMORY" : q2pmux <= # mxinp1 !memmux; + "NETWORKING" : q2pmux <= # mxinp1 memmux; + default: q2pmux <= # mxinp1 !memmux; + + endcase + + end // always @ (memmux) + + +// 4 clock muxs in first rank + always @(clk_in or oclk_in) begin + + case (INTERFACE_TYPE) + + "MEMORY" : memmux <= # mxinp1 oclk_in; + "NETWORKING" : memmux <= # mxinp1 clk_in; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE); + $finish; + end + + endcase // case(INTERFACE_TYPE) + + end // always @(clk_in or oclk_in) + + + + +// data input mux for q3, q4, q5 and q6 + always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + + case (sel1) + + 2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in; + default : dataq3rnk1 <= # mxinp1 q1prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2) + + + always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + + case (sel1) + + 2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1; + default : dataq4rnk1 <= # mxinp1 q2prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1) + + + always @(data_rate_int or q3rnk1 or q4rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1; + default : dataq5rnk1 <= # mxinp1 q4rnk1; + + endcase // case(DATA_RATE) + + end + + + always @(data_rate_int or q4rnk1 or q5rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1; + default : dataq6rnk1 <= # mxinp1 q5rnk1; + + endcase // case(DATA_RATE) + + end + + +// 2nd rank of registers + +// clkdivmux to pass clkdiv_int or CLKDIV to rank 2 + always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin + + case (bitslip_enable_int) + + 1'b0 : clkdivmux <= # mxinp1 clkdiv_in; + 1'b1 : clkdivmux <= # mxinp1 clkdiv_int; + default : clkdivmux <= # mxinp1 clkdiv_in; + + endcase // case(BITSLIP_ENABLE) + + end // always @(clkdiv_int or clkdiv_in) + + + +// Asynchronous Operation + always @(posedge clkdivmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk2 <= # ffinp 1'b0; + q2rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + + end + else begin + + q1rnk2 <= # ffinp dataq1rnk2; + q2rnk2 <= # ffinp dataq2rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + + end + + end // always @ (posedge clkdivmux or sr_in) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + + casex (bsmux) + + 3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1; + 3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1; + default : dataq1rnk2 <= # mxinp2 q2prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + + always @(bsmux or q1prnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1; + 3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1; + default : dataq2rnk2 <= # mxinp2 q1prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1prnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1; + 3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1; + default : dataq3rnk2 <= # mxinp2 q4rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1; + 3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1; + default : dataq4rnk2 <= # mxinp2 q3rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1; + 3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1; + default : dataq5rnk2 <= # mxinp2 q6rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + + casex (bsmux) + + 3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1; + 3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1; + default : dataq6rnk2 <= # mxinp2 q5rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +// 3rd rank of registers + +// Asynchronous Operation + always @(posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + + end + else begin + + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Outputs + + assign shiftout2_out = q5rnk1; + + assign shiftout1_out = q6rnk1; + + + always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q1_out <= # mxinp1_my q1prnk1; + 4'b0X01 : q1_out <= # mxinp1_my q1rnk1; + 4'b0X10 : q1_out <= # mxinp1_my q1rnk1; + 4'b10XX : q1_out <= # mxinp1_my q1rnk2; + 4'b11XX : q1_out <= # mxinp1_my q1rnk3; + default : q1_out <= # mxinp1_my q1rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) + + + always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X01 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X10 : q2_out <= # mxinp1_my q2nrnk1; + 4'b10XX : q2_out <= # mxinp1_my q2rnk2; + 4'b11XX : q2_out <= # mxinp1_my q2rnk3; + default : q2_out <= # mxinp1_my q2rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) + + + always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin + + case (bitslip_enable_int) + + 1'b0 : q3_out <= # mxinp1_my q3rnk2; + 1'b1 : q3_out <= # mxinp1_my q3rnk3; + + endcase // case(BITSLIP_ENABLE) + + end // always @ (q3rnk2 or q3rnk3) + + + + + always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q4_out <= # mxinp1_my q4rnk2; + 1'b1 : q4_out <= # mxinp1_my q4rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q4rnk2 or q4rnk3) + + + always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q5_out <= # mxinp1_my q5rnk2; + 1'b1 : q5_out <= # mxinp1_my q5rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q5rnk2 or q5rnk3) + + + always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q6_out <= # mxinp1_my q6rnk2; + 1'b1 : q6_out <= # mxinp1_my q6rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q6rnk2 or q6rnk3) + + + + + +// Set value of counter in bitslip controller + always @(data_rate_int or data_width_int) begin + + casex ({data_rate_int, data_width_int}) + + 5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default : begin + $display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + $finish; + end + + endcase + + end // always @ (data_rate_int or data_width_int) + + + + + +/////////////////////////////////////////// +// Bit slip controler +/////////////////////////////////////////// + + +// Divide by 2 - 8 counter + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b0) begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Synchronous Operation + always @ (negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b1) begin + + clkdiv_int <= # ffbsc clkdiv_int; + bts_q1 <= # ffbsc bts_q1; + bts_q2 <= # ffbsc bts_q2; + bts_q3 <= # ffbsc bts_q3; + + end + else begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (negedge clk_in) + + +// 4:1 selector mux and divider selections + always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin + + case (sel) + + 2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + 2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2)); + 2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3)); + 2'b11 : mux <= # mxbsc !bts_q3; + default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + + endcase + + end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) + + + +// Bitslip control logic +// Low speed control flop + +// Asynchronous Operation + always @ (posedge qr1 or posedge clkdiv_in) begin + + if (qr1 == 1'b1) begin + + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + + end + else if (bitslip_in == 1'b0) begin + + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + + end + else begin + + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip_in & mux1); + + end + + end // always @ (posedge qr1 or posedge clkdiv_in) + + +// Mux to select between sdr "1" and ddr "0" + + always @ (data_rate_int or qlc1) begin + + case (data_rate_int) + + 1'b0 : mux1 <= # mxbsc qlc1; + 1'b1 : mux1 <= # mxbsc 1'b1; + + endcase + + end + + + +// High speed control flop + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + + end + else begin + + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Mux that drives control line of mux in front +// of 2nd rank of flops + + always @ (data_rate_int or mux1) begin + + case (data_rate_int) + + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + + endcase + + end + + +// Asynchronous set flops + +// Low speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qr1 <= # ffbsc 1'b1; + + else + + qr1 <= # ffbsc 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or negedge clk_in) begin + + if (sr_in == 1'b1) + + qr2 <= # ffbsc 1'b1; + + else + + qr2 <= # ffbsc qr1; + + end // always @ (posedge sr_in or negedge clk_in) + + +///////////////////////////////////////////// +// ICE +/////////////////////////////////////////// + + +// Asynchronous Operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + + end + else begin + + ce1r <= # ffice ce1_in; + ce2r <= # ffice ce2_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + + // Output mux ice + always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin + case ({num_ce_int, clkdiv_in}) + 2'b00 : ice <= # mxice ce1_in; + 2'b01 : ice <= # mxice ce1_in; +// 426606 + 2'b10 : ice <= # mxice ce2r; + 2'b11 : ice <= # mxice ce1r; + default : ice <= # mxice ce1_in; + endcase + end + +//*** Timing Checks Start here +//------------------------------------------------------------------- +// +//------------------------------------------------------------------- + always @(posedge CLK) begin + clk_change_time = $time; + return_code = xsetuphold_chk(clk_change_time, data_change_time); + end + + always @(d_delay) begin + data_change_time = $time; + return_code = xsetuphold_chk(clk_change_time, data_change_time); + end + + +`ifndef XIL_TIMING + + assign bitslip_in = BITSLIP; + assign clk_in = CLK; + assign ce1_in = CE1; + assign ce2_in = CE2; + assign clkdiv_in = CLKDIV; + assign d_in = D; + assign dlyinc_in = DLYINC; + assign dlyce_in = DLYCE; + assign dlyrst_in = DLYRST; + +`endif + + + specify + + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + (D => O) = (0:0:0, 0:0:0); + (SR => Q1) = (0:0:0, 0:0:0); + (SR => Q2) = (0:0:0, 0:0:0); + (SR => Q3) = (0:0:0, 0:0:0); + (SR => Q4) = (0:0:0, 0:0:0); + (SR => Q5) = (0:0:0, 0:0:0); + (SR => Q6) = (0:0:0, 0:0:0); + + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + $setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + $setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + $setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + + $setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in); + $setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in); + $setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in); + $setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in); + $setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in); + $setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in); + $setuphold (posedge CLKDIV, posedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in); + $setuphold (posedge CLKDIV, negedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in); + $setuphold (posedge CLKDIV, posedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in); + $setuphold (posedge CLKDIV, negedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in); + $setuphold (posedge CLKDIV, posedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in); + $setuphold (posedge CLKDIV, negedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in); + + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $period (posedge OCLK, 0:0:0, notifier); + + $recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier); + $recrem (negedge SR, posedge OCLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge REV, posedge OCLK, 0:0:0, 0:0:0, notifier); +// CR 232324 + $setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier); + $setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier); + $setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier); + + $setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier); + $setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier); + $setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier); + $setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier); + + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLKDIV, 0:0:0, 0, notifier); + $width (posedge OCLK, 0:0:0, 0, notifier); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLKDIV, 0:0:0, 0, notifier); + $width (negedge OCLK, 0:0:0, 0, notifier); + +`endif + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ISERDES + +`endcelldefine diff --git a/verilog/src/unisims/ISERDESE1.v b/verilog/src/unisims/ISERDESE1.v new file mode 100644 index 0000000..ff9e8f1 --- /dev/null +++ b/verilog/src/unisims/ISERDESE1.v @@ -0,0 +1,1743 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / Source Synchronous Input Deserializer for Virtex6 +// /___/ /\ Filename : ISERDESE1.v +// \ \ / \ Timestamp : Tue May 26 15:42:08 PDT 2009 +// \___\/\___\ +// +// Revision: +// 05/26/09 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module ISERDESE1 (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB, RST, SHIFTIN1, SHIFTIN2); + + + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter IOBDELAY = "NONE"; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + + + `ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + `endif + +//------------------------------------------------------------- +// Outputs: +//------------------------------------------------------------- +// O: o output +// Q1: q1 output +// Q2: q2 output +// Q3: q3 output +// Q4: q4 output +// Q5: q5 output +// Q6: q6 output +// SHIFTOUT1: carry out data +// SHIFTOUT2: carry out data +// +//------------------------------------------------------------- +// Inputs: +//------------------------------------------------------------- +// D: Input from pad +// CE1: main clock enable input +// CE2: 2nd clock enable input for serdes +// BITSLIP: Manage bitslip controller +// SHIFTIN1: Carry in data +// SHIFTIN2: Carry in data +// CLK: High speed clock or strobe +// CLKB: High speed inverted clock or strobe +// Primary use is QDR +// CLKDIV: Divided clock from H clock row or OCLKDIV for memory applications +// OCLK: High speed output clock +// OCLKB: High speed inverted output clock +// Primary use is oversampling +// RST: Set/Reset control. +// CLKDIV: Low speed clock to drive counter for delay element +// +// DYNCLKSEL: Dynamically change polarity of CLK +// DYNCLKDIVSEL: Dynamically change polarity of CLKDIV +// DYNOCLKSEL: Dynamically change polarity of OCLK +// OFB: Feedback input from the OQ portion of the output +// + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKB; + input CLKDIV; + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + input OCLK; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; + + +// + wire [1:0] SRTYPE, DDR_CLK_EDGE; + wire SERDES; + wire TFB; +// CR 541284 wire OVERSAMPLE, RANK12_DLY, RANK23_DLY; + wire RANK12_DLY, RANK23_DLY; + wire D_EMU; + assign SRTYPE = 2'b00; + assign SERDES = 1'b1; + assign DDR_CLK_EDGE = 2'b11; + assign TFB = 1'b0; +// CR 541284 assign OVERSAMPLE = 1'b0; + reg OVERSAMPLE = 1'b0; + assign RANK12_DLY = 1'b0; + assign RANK23_DLY = 1'b0; + assign D_EMU = 1'b0; + +// Output signals + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + wire shiftout1_out, shiftout2_out; + + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + + reg memmux, q2pmux; + + reg clkmux1, clkmux2, clkmux3, clkmux4; + + reg clkoimux, oclkoimux, clkdivoimux; + reg clkboimux, oclkboimux = 0, clkdivboimux; + + + reg clkdivmux1, clkdivmux2; + + reg ddr3clkmux; + + reg rank3clkmux; + + reg c23, c45, c67; + + reg [1:0] sel; + + wire [3:0] selrnk3; + + wire [4:0] cntr; + + wire [1:0] sel1; + + wire [3:0] bsmux; + + wire ice; + + wire muxc; + + wire clkdiv_int; + + wire [1:0] clkdivsel; + + wire bitslip_en; + + wire int_typ; + + wire [1:0] os_en; + + wire [2:0] rank2_cksel; + + reg data_in; + reg o_out_pre_fb = 0, o_delay_pre_fb = 0; + + + reg data_rate_int; + reg [3:0] data_width_int; + reg dyn_clkdiv_inv_int, dyn_clk_inv_int, dyn_oclk_inv_int; + reg ofb_used_int, num_ce_int, serdes_mode_int; + reg [1:0] interface_type_int; + + reg notifier; + +// Other signals + tri0 GSR = glbl.GSR; + + + + buf b_o (O, o_out); + buf b_q1 (Q1, q1_out); + buf b_q2 (Q2, q2_out); + buf b_q3 (Q3, q3_out); + buf b_q4 (Q4, q4_out); + buf b_q5 (Q5, q5_out); + buf b_q6 (Q6, q6_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + + wire bitslip_in, ce1_in, ce2_in, clk_in, clkb_in, clkdiv_in, + d_in, ddly_in, dynclkdivsel_in, dynclksel_in, dynoclksel_in, oclk_in, + oclkb_in, ofb_in, rst_in, shiftin1_in, shiftin2_in; +`ifndef XIL_TIMING + assign bitslip_in = BITSLIP; + assign ce1_in = CE1; + assign ce2_in = CE2; + assign clk_in = CLK; + assign clkb_in = CLKB; + assign clkdiv_in = CLKDIV; + assign d_in = D; + assign ddly_in = DDLY; + assign dynclkdivsel_in = DYNCLKDIVSEL; + assign dynclksel_in = DYNCLKSEL; +// CR 518368 +// assign dynoclksel_in = DYNOCLKSEL; + assign oclk_in = OCLK; +// CR 507371 +// assign oclkb_in = OCLKB; + assign ofb_in = OFB; + assign rst_in = RST; + assign shiftin1_in = SHIFTIN1; + assign shiftin2_in = SHIFTIN2; +`endif // `ifndef XIL_TIMING + + + task INTERFACE_TYPE_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("NETWORKING DDR 4, 6, 8, 10\n"); + $display("MEMORY SDR None\n"); + $display("MEMORY DDR 4\n"); + end + endtask // INTERFACE_TYPE_msg + +// CR 541284 + task OVERSAMPLE_DDR_SDR_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("OVERSAMPLE SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("OVERSAMPLE DDR 4, 6, 8, 10\n"); + end + endtask // OVERSAMPLE_DDR_SDR_msg + + initial begin +//------------------------------------------------- +//----- DATA_RATE check +//------------------------------------------------- + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + #1 $finish; + end + endcase // case(DATA_RATE) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + + +//------------------------------------------------- +//----- DYN_CLKDIV_INV_EN check +//------------------------------------------------- + case (DYN_CLKDIV_INV_EN) + + "FALSE" : dyn_clkdiv_inv_int <= 1'b0; + "TRUE" : dyn_clkdiv_inv_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN); + #1 $finish; + end + + endcase // case(DYN_CLKDIV_INV_EN) + +//------------------------------------------------- +//----- DYN_CLK_INV_EN check +//------------------------------------------------- + case (DYN_CLK_INV_EN) + + "FALSE" : dyn_clk_inv_int <= 1'b0; + "TRUE" : dyn_clk_inv_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN); + #1 $finish; + end + + endcase // case(DYN_CLK_INV_EN) + +//------------------------------------------------- +//----- OFB_USED check +//------------------------------------------------- + case (OFB_USED) + + "FALSE" : ofb_used_int <= 1'b0; + "TRUE" : ofb_used_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED); + #1 $finish; + end + + endcase // case(OFB_USED) +//------------------------------------------------- +//----- NUM_CE check +//------------------------------------------------- + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + #1 $finish; + end + + endcase // case(NUM_CE) + + +//------------------------------------------------- +//----- INTERFACE_TYPE check +//------------------------------------------------- + case (INTERFACE_TYPE) + "MEMORY" : begin + interface_type_int <= 2'b00; + case(DATA_RATE) + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : INTERFACE_TYPE_msg; + endcase // DATA_RATE + end + "NETWORKING" : begin + interface_type_int <= 2'b01; + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + "MEMORY_QDR" : + interface_type_int <= 2'b10; + "MEMORY_DDR3" : + interface_type_int <= 2'b11; +// CR 541284 + "OVERSAMPLE" : begin + OVERSAMPLE <= 1'b1; + interface_type_int <= 2'b01; + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : OVERSAMPLE_DDR_SDR_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10 : ; + default : OVERSAMPLE_DDR_SDR_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE); + #1 $finish; + end + endcase // INTERFACE_TYPE + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + endcase // case(SERDES_MODE) + +//------------------------------------------------- + end // initial begin + +//------------------------------------------------- +assign int_typ = interface_type_int[1] | interface_type_int[0]; + +assign bitslip_en = interface_type_int[0]; + +// CR 541284 +assign os_en = {int_typ, OVERSAMPLE}; // {int_typ, OVERSAMPLE}; + +assign sel1 = {serdes_mode_int, data_rate_int}; // {SERDES_MODE,DATA_RATE}; + +// CR 541284 +assign rank2_cksel = {interface_type_int, OVERSAMPLE}; // {interface_type_int, OVERSAMPLE}; + +assign selrnk3 = {1'b1, bitslip_en, 2'b11}; // {SERDES,bitslip_en, DDR_CLK_EDGE}; + +// CR 541284 +assign bsmux = {bitslip_en, data_rate_int, muxc, OVERSAMPLE}; // {bitslip_en,DATA_RATE,muxc, OVERSAMPLE}; + +assign cntr = {data_rate_int, data_width_int}; // {DATA_RATE,DATA_WIDTH}; + +// Parameter declarations for delays + + localparam ffinp = 300; + localparam mxinp1 = 60; + localparam mxinp2 = 120; + +// Delay parameters + localparam ht0 = 800; + localparam fftco = 300; + localparam mxdly = 60; + localparam cnstdly = 80; + + +// GSR + + always @(GSR) begin + if (GSR == 1'b1) begin + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + assign ddr3clkmux = 1'b1; + end + else if (GSR == 1'b0) begin + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + deassign ddr3clkmux; + + end // if (GSR == 1'b0) + end // always @ (GSR) + +//------------------------------------------------- +// Input to ISERDES +//------------------------------------------------- + + always @(d_in or ddly_in) begin + + case (IOBDELAY) + + "NONE" : begin + o_out_pre_fb <= d_in; + o_delay_pre_fb <= d_in; + + end + "IBUF" : begin + o_out_pre_fb <= ddly_in; + o_delay_pre_fb <= d_in; + end + "IFD" : begin + o_out_pre_fb <= d_in; + o_delay_pre_fb <= ddly_in; + end + "BOTH" : begin + o_out_pre_fb <= ddly_in; + o_delay_pre_fb <= ddly_in; + end + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE1 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + $finish; + end + + endcase // case(IOBDELAY) + + end // always @ (d_in or ddly_in) + + generate + case (OFB_USED) + "TRUE" : always @(ofb_in) + begin + o_out <= ofb_in; + data_in <= ofb_in; + end + "FALSE" : begin + always @(o_out_pre_fb) o_out <= o_out_pre_fb; + always @(o_delay_pre_fb) data_in <= o_delay_pre_fb; + end + endcase + endgenerate + +//------------------------------------------------------ +// High Speed Clock Generation and Polarity Control +//------------------------------------------------------ + +// Optional inverter for clk + generate + case (DYN_CLK_INV_EN) + "FALSE" : always @(clk_in) clkoimux <= clk_in; + "TRUE" : +// CR 523086 + always @ (dynclksel_in or clk_in or clkb_in) begin + case (dynclksel_in) + 1'b0: clkoimux <= clkb_in; + 1'b1: clkoimux <= clk_in; + endcase + end + endcase + endgenerate + +// Optional inverter for clkb + generate + case (DYN_CLK_INV_EN) + "FALSE" : always @(clkb_in) clkboimux <= clkb_in; + "TRUE" : +// CR 523086 + always @ (dynclksel_in or clkb_in or clk_in) begin + case (dynclksel_in) + 1'b0: clkboimux <= clk_in; + 1'b1: clkboimux <= clkb_in; + endcase + end + endcase + endgenerate + +// CR 518368 +// Optional inverter for oclk +/* + generate + case (DYN_OCLK_INV_EN) + "FALSE" : always @(oclk_in) oclkoimux <= oclk_in; + "TRUE" : + always @ (dynoclksel_in or oclk_in) begin + case (dynoclksel_in) + 1'b0: oclkoimux <= oclk_in; + 1'b1: oclkoimux <= ~oclk_in; + endcase + end + endcase + endgenerate +*/ + + always @(oclk_in) oclkoimux <= oclk_in; + +//CR 507371 +// Optional inverter for oclkb +/* + generate + case (DYN_OCLK_INV_EN) + "FALSE" : always @(oclkb_in) oclkboimux <= oclkb_in; + "TRUE" : + always @ (dynoclksel_in or oclkb_in) begin + case (dynoclksel_in) + 1'b0: oclkboimux <= oclkb_in; + 1'b1: oclkboimux <= ~oclkb_in; + endcase + end + endcase + endgenerate +*/ + +// Optional inverter for clkdiv + generate + case (DYN_CLKDIV_INV_EN) + "FALSE" : always @(clkdiv_in) clkdivoimux <= clkdiv_in; + "TRUE" : + always @ (dynclkdivsel_in or clkdiv_in) begin + case (dynclkdivsel_in) + 1'b0: clkdivoimux <= clkdiv_in; + 1'b1: clkdivoimux <= ~clkdiv_in; + endcase + end + endcase + endgenerate + +// clkmux for 2nd flop in rank1 + generate + case (INTERFACE_TYPE) + "MEMORY" : always @(clkboimux) clkmux2 <= clkboimux; + "NETWORKING" : always @(clkboimux) clkmux2 <= clkboimux; + "MEMORY_QDR" : always @(clkboimux) clkmux2 <= clkboimux; + "MEMORY_DDR3" : always @(clkboimux) clkmux2 <= clkboimux; + endcase + endgenerate + +// clkmux for 3rd flop in rank1 + always @ (os_en or oclkoimux or clkoimux) begin + case (os_en) + 2'b00: clkmux3 <= oclkoimux; + 2'b01: clkmux3 <= oclkoimux; + 2'b10: clkmux3 <= clkoimux; + 2'b11: clkmux3 <= oclkoimux; + endcase + end + +//clkmux for 4th flop in rank1 + always @ (os_en or oclkoimux or clkoimux or oclkboimux) begin + case(os_en) + 2'b00: clkmux4 <= ~oclkoimux; + 2'b01: clkmux4 <= ~oclkoimux; + 2'b10: clkmux4 <= clkoimux; + 2'b11: clkmux4 <= oclkboimux; + default: clkmux4 <= ~oclkoimux; + endcase + end + +// Rest of clock muxs in first rank + always @ (int_typ or oclkoimux or clkoimux) begin + case (int_typ) + 1'b0: memmux <= # mxinp1 oclkoimux; + 1'b1: memmux <= # mxinp1 clkoimux; + default: memmux <= # mxinp1 oclkoimux; + endcase + end + +//------------------------------------------------- +// 1st rank of registers -- Synchronous Operation +//------------------------------------------------- +// Uses the positive edge of CLK +// This includes the 1st, 6th, 7th and 8th flops in rank 1 +// These flops are designated as q1rnk1, q5rnk1, q6rnk1 +// and q6prnk1. q1rnk1 is full featured. +// q5rnk1, q6rnk1 and q6prnk1 are not. + + always @ (posedge clkoimux) begin + if(rst_in == 1'b1) begin + q1rnk1 <= # ffinp SRVAL_Q1; + end + else if (ice == 1'b1) begin + q1rnk1 <= # ffinp data_in; + end + + if(rst_in == 1'b1) begin + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + end + else begin + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + end + end // always @ (posedge clkoimux) + +// 2nd flop in rank 1, designated q2nrnk1, that is full featured +// and operates only on the negative edge of CLK or positive +// edge of CLKB + + always @ (posedge clkmux2) begin + if(rst_in == 1'b1) + q2nrnk1 <= # ffinp SRVAL_Q2; + else if (ice == 1'b1) + q2nrnk1 <= # ffinp data_in; + end // always @ (posedge clkmux2) + +// 3rd, 4th, 5th and 6th flops in rank1 +// The 3rd and 4th flops are full featured while +// The 5th and 6th flops only have reset. The flops are +// designated as q1prnk1, q2prnk1, q3rnk1 and q4rnk1. +// These 4 flops can be driven from CLK or OCLK. This +// function is implemented by the clk mux called +// "memmux". Flops q1prnk1, q3rnk1 and q4rnk1 are +// driven of the positive edge of memmux. Flop q2prnk1 +// is further driven by the optional inverter mux named +// "q2pmux" that allows it to be driven off either the +// positive or negative edge of memmux. +// + + always @ (posedge clkmux3) begin + if(rst_in == 1'b1) + q1prnk1 <= # ffinp SRVAL_Q3; + else if (ice == 1'b1) + q1prnk1 <= # ffinp q1rnk1; + end // always @ (posedge clkmux3) + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + + always @ (posedge memmux) begin + if(rst_in == 1'b1) begin + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + end + else begin + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + end + end // always @ (posedge clkmux2) + +// 4th flop in rank 1 (q2prnk1). This is a full featured flop +// that for memory is clocked on the negative edge of OCLK +// and for networking is clocked on the positive edge of CLK + + + always @ (posedge clkmux4) begin + if(rst_in == 1'b1) + q2prnk1 <= # ffinp SRVAL_Q4; + else if (ice == 1'b1) + q2prnk1 <= # ffinp q2nrnk1; + end // always @ (posedge clkmux4) + +//------------------------------------------------- +// Mux elements for the 1st rank +//------------------------------------------------- + +// data input mux for q3, q4, q5 and q6 + + always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + case (sel1) + 2'b00: dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01: dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10: dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11: dataq3rnk1 <= # mxinp1 shiftin1_in; + default: dataq3rnk1 <= # mxinp1 q1prnk1; + endcase // case(sel1) + end // always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in) + + always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + case (sel1) + 2'b00: dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01: dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10: dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11: dataq4rnk1 <= # mxinp1 q3rnk1; + default: dataq4rnk1 <= # mxinp1 q2prnk1; + endcase // case(sel1) + end // always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in) + + always @ (data_rate_int or q3rnk1 or q4rnk1) begin + case (data_rate_int) + 1'b0: dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1: dataq5rnk1 <= # mxinp1 q4rnk1; + default: dataq5rnk1 <= # mxinp1 q4rnk1; + endcase // case(data_rate_int) + end // always @ (data_rate_int or q3rnk1 or q4rnk1) + + always @ (data_rate_int or q4rnk1 or q5rnk1) begin + case (data_rate_int) + 1'b0: dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1: dataq6rnk1 <= # mxinp1 q5rnk1; + default: dataq6rnk1 <= # mxinp1 q5rnk1; + endcase // case(data_rate_int) + end // always @ (data_rate_int or q4rnk1 or q5rnk1) + +//------------------------------------------------- +// 2nd rank of registers -- Synchronous Operation +//------------------------------------------------- + + +// DDR3 Divide By 2 CKT + + always @ (negedge clkoimux) begin + if(rst_in) + ddr3clkmux <= 1'b0; + else if (INTERFACE_TYPE == "MEMORY_DDR3") + ddr3clkmux <= ~ddr3clkmux; + else + ddr3clkmux <= ddr3clkmux; + end // always @ (negedge clkoimux) + +// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2 + always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr) begin + case (rank2_cksel) + 3'b000: clkdivmux1 <= # mxinp1 clkdivoimux; + 3'b010: begin + case (cntr) + 5'b00100: clkdivmux1 <= # mxinp1 ~clkdiv_int; + 5'b10010: clkdivmux1 <= # mxinp1 ~clkdiv_int; + default: clkdivmux1 <= # mxinp1 clkdiv_int; + endcase + end + 3'b100: clkdivmux1 <= # mxinp1 clkdivoimux; + 3'b110: #1 clkdivmux1 <= # mxinp1 ddr3clkmux; + 3'b011: clkdivmux1 <= # mxinp1 clkoimux; +// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time); + endcase // case (rank2_cksel) + end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr) + + +// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2 + always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or oclkoimux or cntr) begin + case (rank2_cksel) + 3'b000: clkdivmux2 <= # mxinp1 clkdivoimux; + 3'b010: begin + case (cntr) + 5'b00100: clkdivmux2 <= # mxinp1 ~clkdiv_int; + 5'b10010: clkdivmux2 <= # mxinp1 ~clkdiv_int; + default: clkdivmux2 <= # mxinp1 clkdiv_int; + endcase + end + 3'b100: clkdivmux2 <= # mxinp1 clkdivoimux; + 3'b110: #1 clkdivmux2 <= #mxinp1 ddr3clkmux; + 3'b011: clkdivmux2 <= # mxinp1 oclkoimux; +// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time); + endcase // case (rank2_cksel) + end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux) + +// Synchronous Operation + always @ (posedge clkdivmux1) begin + if(rst_in == 1'b1) begin + q1rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + end + else begin + q1rnk2 <= # ffinp dataq1rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + end + end // always @ (posedge clkdivmux1) + + + always @ (posedge clkdivmux2) begin + if(rst_in == 1'b1) begin + q2rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + end + else begin + q2rnk2 <= # ffinp dataq2rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + end + end // always @ (posedge clkdivmux2) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + + always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + casex (bsmux) + 4'b00X0: dataq1rnk2 <= # mxinp2 q2prnk1; + 4'b1000: dataq1rnk2 <= # mxinp2 q2prnk1; + 4'b1010: dataq1rnk2 <= # mxinp2 q1prnk1; + 4'bX1X0: dataq1rnk2 <= # mxinp2 q1rnk1; + 4'bXXX1: dataq1rnk2 <= # mxinp2 q1rnk1; + default: dataq1rnk2 <= # mxinp2 q2prnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1) begin + casex (bsmux) + 4'b00X0: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'b1000: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'b1010: dataq2rnk2 <= # mxinp2 q4rnk1; + 4'bX1X0: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'bXXX0: dataq2rnk2 <= # mxinp2 q2nrnk1; + default: dataq2rnk2 <= # mxinp2 q1prnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1) + + always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1) begin + casex (bsmux) + 4'b00X0: dataq3rnk2 <= # mxinp2 q4rnk1; + 4'b1000: dataq3rnk2 <= # mxinp2 q4rnk1; + 4'b1010: dataq3rnk2 <= # mxinp2 q3rnk1; + 4'bX1X0: dataq3rnk2 <= # mxinp2 q3rnk1; + 4'bXXX1: dataq3rnk2 <= # mxinp2 q1prnk1; + default: dataq3rnk2 <= # mxinp2 q4rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1) + + always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1) begin + casex (bsmux) + 4'b00X0: dataq4rnk2 <= # mxinp2 q3rnk1; + 4'b1000: dataq4rnk2 <= # mxinp2 q3rnk1; + 4'b1010: dataq4rnk2 <= # mxinp2 q6rnk1; + 4'bX1X0: dataq4rnk2 <= # mxinp2 q4rnk1; + 4'bXXX1: dataq4rnk2 <= # mxinp2 q2prnk1; + default: dataq4rnk2 <= # mxinp2 q3rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1) + + always @ (bsmux or q5rnk1 or q6rnk1) begin + casex (bsmux) + 4'b00X0: dataq5rnk2 <= # mxinp2 q6rnk1; + 4'b1000: dataq5rnk2 <= # mxinp2 q6rnk1; + 4'b1010: dataq5rnk2 <= # mxinp2 q5rnk1; + 4'bX1X0: dataq5rnk2 <= # mxinp2 q5rnk1; + default: dataq5rnk2 <= # mxinp2 q6rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q5rnk1 or q6rnk1) + + always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + casex (bsmux) + 4'b00X0: dataq6rnk2 <= # mxinp2 q5rnk1; + 4'b1000: dataq6rnk2 <= # mxinp2 q5rnk1; + 4'b1010: dataq6rnk2 <= # mxinp2 q6prnk1; + 4'bX1X0: dataq6rnk2 <= # mxinp2 q6rnk1; + default: dataq6rnk2 <= # mxinp2 q5rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +//------------------------------------------------- +// 3rd rank of registers -- Synchronous Operation +//------------------------------------------------- + + +// clkdivmuxs to pass CLK or CLKDIV to rank 3 + always @ (OVERSAMPLE or clkdivoimux or clkoimux) begin + case (OVERSAMPLE) + 1'b0: rank3clkmux <= # mxinp1 clkdivoimux; + 1'b1: rank3clkmux <= # mxinp1 clkoimux; + default: rank3clkmux <= # mxinp1 clkdivoimux; + endcase // case (OVERSAMPLE) + end // always @ (OVERSAMPLE or clkdivoimux or clkoimux) + +// Synchronous Operation + + always @ (posedge rank3clkmux) begin + if(rst_in == 1'b1) begin + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + end + else begin + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + end + end // always @ (posedge rank3clkmux) + +//------------------------------------------------- +// Outputs +//------------------------------------------------- + + assign shiftout1_out = q6rnk1; + assign shiftout2_out = q5rnk1; + + always @ (selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + casex (selrnk3) + 4'b0X00: q1_out <= # mxinp1 q1prnk1; + 4'b0X01: q1_out <= # mxinp1 q1rnk1; + 4'b0X10: q1_out <= # mxinp1 q1rnk1; + 4'b10XX: q1_out <= # mxinp1 q1rnk2; + 4'b11XX: q1_out <= # mxinp1 q1rnk3; + default: q1_out <= # mxinp1 q1rnk2; + endcase + end + + always @ (selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + casex (selrnk3) + 4'b0X00: q2_out <= # mxinp1 q2prnk1; + 4'b0X01: q2_out <= # mxinp1 q2prnk1; + 4'b0X10: q2_out <= # mxinp1 q2nrnk1; + 4'b10XX: q2_out <= # mxinp1 q2rnk2; + 4'b11XX: q2_out <= # mxinp1 q2rnk3; + default: q2_out <= # mxinp1 q2rnk2; + endcase + end + + always @ (bitslip_en or q3rnk2 or q3rnk3) begin + case (bitslip_en) + 1'b0: q3_out <= # mxinp1 q3rnk2; + 1'b1: q3_out <= # mxinp1 q3rnk3; + default: q3_out <= # mxinp1 q3rnk2; + endcase + end + + always @ (bitslip_en or q4rnk2 or q4rnk3) begin + casex (bitslip_en) + 1'b0: q4_out <= # mxinp1 q4rnk2; + 1'b1: q4_out <= # mxinp1 q4rnk3; + default: q4_out <= # mxinp1 q4rnk2; + endcase + end + + always @ (bitslip_en or q5rnk2 or q5rnk3) begin + casex (bitslip_en) + 1'b0: q5_out <= # mxinp1 q5rnk2; + 1'b1: q5_out <= # mxinp1 q5rnk3; + default: q5_out <= # mxinp1 q5rnk2; + endcase + end + + always @ (bitslip_en or q6rnk2 or q6rnk3) begin + casex (bitslip_en) + 1'b0: q6_out <= # mxinp1 q6rnk2; + 1'b1: q6_out <= # mxinp1 q6rnk3; + default: q6_out <= # mxinp1 q6rnk2; + endcase + end + +// Instantiate Bitslip controller +bscntrl_iserdese1_vlog bsc (.c23(c23), .c45(c45), .c67(c67), .sel(sel), + .DATA_RATE(data_rate_int), .bitslip(bitslip_in), + .clk(!clkoimux), .clkdiv(clkdivoimux), .r(rst_in), + .clkdiv_int(clkdiv_int), .muxc(muxc) + ); + +// Set value of counter in bitslip controller +always @ (cntr or c23 or c45 or c67 or sel) +begin + casex (cntr) + 5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default: $display("DATA_WIDTH %b and DATA_RATE %b at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + endcase + +end + + +// Instantiate clock enable circuit +ice_iserdese1_vlog cec (.ce1(ce1_in), .ce2(ce2_in), .NUM_CE(num_ce_int), + .clkdiv(rank3clkmux), .r(rst_in), .ice(ice) + ); + + +`ifndef XIL_TIMING + specify + + (CLK => Q1) = (100:100:100, 100:100:100); + (CLK => Q2) = (100:100:100, 100:100:100); + (CLK => Q3) = (100:100:100, 100:100:100); + (CLK => Q4) = (100:100:100, 100:100:100); + (CLK => Q5) = (100:100:100, 100:100:100); + (CLK => Q6) = (100:100:100, 100:100:100); + + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + (D => O) = (0, 0); + (DDLY => O) = (0, 0); + (OFB => O) = (0, 0); + + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING +//*** Timing Checks Start here + + specify + + (D => O) = (0:0:0, 0:0:0); + (DDLY => O) = (0:0:0, 0:0:0); + (OFB => O) = (0:0:0, 0:0:0); + (CLK => Q1) = (100:100:100, 100:100:100); + (CLK => Q2) = (100:100:100, 100:100:100); + (CLK => Q3) = (100:100:100, 100:100:100); + (CLK => Q4) = (100:100:100, 100:100:100); + (CLK => Q5) = (100:100:100, 100:100:100); + (CLK => Q6) = (100:100:100, 100:100:100); + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + (RST => Q1) = (0:0:0, 0:0:0); + (RST => Q2) = (0:0:0, 0:0:0); + (RST => Q3) = (0:0:0, 0:0:0); + (RST => Q4) = (0:0:0, 0:0:0); + (RST => Q5) = (0:0:0, 0:0:0); + (RST => Q6) = (0:0:0, 0:0:0); + + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in); + $setuphold (posedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, , , clk_in, ddly_in); + $setuphold (posedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, , , clk_in, ddly_in); + $setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + $setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in); + $setuphold (posedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, , , clk_in, ofb_in); + $setuphold (posedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, , , clk_in, ofb_in); + + $setuphold (posedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, , , clkb_in, d_in); + $setuphold (posedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, , , clkb_in, d_in); + $setuphold (posedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, , , clkb_in, ddly_in); + $setuphold (posedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, , , clkb_in, ddly_in); + $setuphold (posedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkb_in, ce1_in); + $setuphold (posedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkb_in, ce1_in); + $setuphold (posedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, , , clkb_in, ofb_in); + $setuphold (posedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, , , clkb_in, ofb_in); + + $setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in); + $setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in); + $setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in); + $setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in); + $setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in); + $setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in); + +//-- SYNC + $setuphold (posedge CLK, posedge RST, 0:0:0, 0:0:0, notifier, , , clk_in, rst_in); + $setuphold (posedge CLK, negedge RST, 0:0:0, 0:0:0, notifier, , , clk_in, rst_in); + $setuphold (posedge CLKB, posedge RST, 0:0:0, 0:0:0, notifier, , , clkb_in, rst_in); + $setuphold (posedge CLKB, negedge RST, 0:0:0, 0:0:0, notifier, , , clkb_in, rst_in); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rst_in); + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rst_in); + $setuphold (posedge OCLK, posedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in); + $setuphold (posedge OCLK, negedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in); + $setuphold (negedge OCLK, posedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in); + $setuphold (negedge OCLK, negedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in); + + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKB, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $period (posedge OCLK, 0:0:0, notifier); + + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLKB, 0:0:0, 0, notifier); + $width (posedge CLKDIV, 0:0:0, 0, notifier); + $width (posedge OCLK, 0:0:0, 0, notifier); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLKB, 0:0:0, 0, notifier); + $width (negedge CLKDIV, 0:0:0, 0, notifier); + $width (negedge OCLK, 0:0:0, 0, notifier); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifdef XIL_TIMING + + +endmodule // ISERDESE1 + +`timescale 1ps/1ps +/////////////////////////////////////////////////////// +// +// Bit slip controller +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// bitslip: Activates bitslip controller +// clk: High speed forwarded clock +// clkdiv: Low speed from clock divider in H clock row +// r: Generates resest for flops +// +// +// Outputs: +// clkdiv_int: Generates clock same frequency as clkdiv +// muxc: Controls mux in 2nd rank for DDR bitslip +// +// +// Programmable options +// +// DATA_RATE: Selects between sdr "1" and ddr "0" operation +// c23: Selector between divide by 2 and divide by 3 +// c45: Selector between divide by 4 and divide by 5 +// c67: Selector between divide by 6 and divide by 7 +// sel: Mux selector with following table: +// 00: Divide by 2 or 3 +// 01: Divide by 4 or 5 +// 10: Divide by 6 or 7 +// 11: Divide by 8 +// +//////////////////////////////////////////////////////////////////////////////// +// + +module bscntrl_iserdese1_vlog (c23, c45, c67, sel, DATA_RATE, + bitslip, + clk, clkdiv, r, + clkdiv_int,muxc + ); + +// programmable points +input c23, c45, c67, DATA_RATE; + +input [1:0] sel; + +// regular inputs + +input clk, r, clkdiv; + +input bitslip; + +// Programmable Test Attributes +wire SRTYPE; +assign SRTYPE = 1'b0; + +// outputs +output clkdiv_int, muxc; + + +reg clkdiv_int; + +reg q1, q2, q3; + +reg mux; + +reg qhc1, qhc2, qlc1, qlc2; + +reg qr1, qr2; + +reg mux1, muxc; + + +////////////////////////////////////////////////// +// +// Delay parameter assignment +// +///////////////////////////////////////////////// + +localparam ffbsc = 300; +localparam mxbsc = 60; + + +//////////////////////////////////////////////////// +// +// Initialization of flops through GSR +// +/////////////////////////////////////////////////// + +`ifdef SW_NO_ISERDES_TEST +`else +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign q3 = 1'b0; + assign q2 = 1'b0; + assign q1 = 1'b0; + assign clkdiv_int = 1'b0; + end + else + begin + deassign q3; + deassign q2; + deassign q1; + deassign clkdiv_int; + end +end +`endif +////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + + +/////////////////////////////// +// +// Divide by 2 - 8 counter +// +//////////////////////////////// + +// Asynchronous Operation +always @ (posedge qr2 or posedge clk) +begin + if (qr2 & SRTYPE) + begin + clkdiv_int <= # ffbsc 1'b0; + q1 <= # ffbsc 1'b0; + q2 <= # ffbsc 1'b0; + q3 <= # ffbsc 1'b0; + end + else if (qhc1 & SRTYPE) + begin + clkdiv_int <= # ffbsc clkdiv_int; + q1 <= # ffbsc q1; + q2 <= # ffbsc q2; + q3 <= # ffbsc q3; + end + else if (SRTYPE) + begin + q3 <= # ffbsc q2; + q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1); + q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + end +end +// Synchronous Operation +always @ (posedge clk) +begin + if (qr2 & !SRTYPE) + begin + clkdiv_int <= # ffbsc 1'b0; + q1 <= # ffbsc 1'b0; + q2 <= # ffbsc 1'b0; + q3 <= # ffbsc 1'b0; + end + else if (qhc1 & !SRTYPE) + begin + clkdiv_int <= # ffbsc clkdiv_int; + q1 <= # ffbsc q1; + q2 <= # ffbsc q2; + q3 <= # ffbsc q3; + end + else if (!SRTYPE) + begin + q3 <= # ffbsc q2; + q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1); + q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + end +end + + + +////////////////////////////////////////// +// 4:1 selector mux and divider selections +////////////////////////////////////////// +always @ (sel or c23 or c45 or c67 or clkdiv_int or q1 or q2 or q3) + begin + case (sel) + 2'b00: mux <= # mxbsc !(clkdiv_int | (c23 & q1)); + 2'b01: mux <= # mxbsc !(q1 | (c45 & q2)); + 2'b10: mux <= # mxbsc !(q2 | (c67 & q3)); + 2'b11: mux <= # mxbsc !q3; + default: mux <= # mxbsc !(clkdiv_int | (c23 & q1)); + endcase + end + +/////////////////////////////////// +// +// Bitslip control logic +// +/////////////////////////////////// + + +///////////////////// +// Low speed control flop +/////////////////////// + +// Asynchronous Operation +always @ (posedge qr1 or posedge clkdiv) +begin + begin + if (qr1 & SRTYPE) + begin + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + end + else if (!bitslip & SRTYPE) + begin + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + end + else if (SRTYPE) + begin + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip & mux1); + end + end +end +// Synchronous Operation +always @ (posedge clkdiv) +begin + begin + if (qr1 & !SRTYPE) + begin + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + end + else if (!bitslip & !SRTYPE) + begin + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + end + else if (!SRTYPE) + begin + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip & mux1); + end + end +end + + +///////////////////////////////////////////// +// Mux to select between sdr "1" and ddr "0" +///////////////////////////////////////////// +always @ (qlc1 or DATA_RATE) + begin + case (DATA_RATE) + 1'b0: mux1 <= # mxbsc qlc1; + 1'b1: mux1 <= # mxbsc 1'b1; + + endcase + end + +///////////////////////// +// High speed control flop +///////////////////////// + +// Asynchronous Operation +always @ (posedge qr2 or posedge clk) +begin + begin + if (qr2 & SRTYPE) + begin + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + end + else if (SRTYPE) + begin + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + end + end +end +// Synchronous Operation +always @ (posedge clk) +begin + begin + if (qr2 & !SRTYPE) + begin + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + end + else if (!SRTYPE) + begin + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + end + end +end + + + +///////////////////////////////////////////// +// Mux that drives control line of mux in front +// of 2nd rank of flops +////////////////////////////////////////// +always @ (mux1 or DATA_RATE) +begin + case (DATA_RATE) + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + endcase +end + +///////////////////////////// +// Asynchronous set flops +///////////////////////////// + +///////////////////// +// Low speed reset flop +/////////////////////// + +// Asynchronous Operation +always @ (posedge r or posedge clkdiv) + begin + if (r & SRTYPE) + begin + qr1 <= # ffbsc 1'b1; + end + else if (SRTYPE) + begin + qr1 <= # ffbsc 1'b0; + end + end +// Synchronous Operation +always @ (posedge clkdiv) + begin + if (r & !SRTYPE) + begin + qr1 <= # ffbsc 1'b1; + end + else if (!SRTYPE) + begin + qr1 <= # ffbsc 1'b0; + end + end + +///////////////////// +// High speed reset flop +/////////////////////// +// Asynchronous Operation +always @ (posedge r or posedge clk) + begin + if (r & SRTYPE) + begin + qr2 <= # ffbsc 1'b1; + end + else if (SRTYPE) + begin + qr2 <= # ffbsc qr1; + end + end +// Synchronous Operation +always @ (posedge clk) + begin + if (r & !SRTYPE) + begin + qr2 <= # ffbsc 1'b1; + end + else if (!SRTYPE) + begin + qr2 <= # ffbsc qr1; + end + end + + +/////////////////////// + +endmodule + + + +`timescale 1ps/1ps +// +/////////////////////////////////////////////////////// +// +// Input Clock Enable Circuit +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: ce1: 1st and default clock enable +// ce2: 2nd clock enable used for serdes memory cases +// r: Synchronous reset +// clkdiv: Low speed output clock generated off the DCM +// +// +// +// Outputs: intce: Clock enable +// +// +// Programmable options +// +// NUM_CE: 0: ce1 only, 1: ce1 and ce2 +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module ice_iserdese1_vlog (ce1, ce2, NUM_CE, + clkdiv, r, + ice + ); + + +// regular inputs + +input ce1, ce2; + +input clkdiv, r; + +// programmable points +input NUM_CE; + + +// programmable test points +// Synchronus RST +wire SRTYPE; +assign SRTYPE = 1'b0; + +// output +output ice; + + +reg ce1r, ce2r, ice; + +wire [1:0] cesel; + +assign cesel = {NUM_CE,clkdiv}; + + + +////////////////////////////////////////////////// +// +// Delay parameters +// +///////////////////// + +localparam ffice = 300; +localparam mxice = 60; + + +//////////////////////////////////////////////////// +// +// Initialization of flops through GSR +// +/////////////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign ce1r = 1'b0; + assign ce2r = 1'b0; + end + else + begin + deassign ce1r; + deassign ce2r; + end +end +////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + + + + +// Asynchronous Operation +always @ (posedge clkdiv or posedge r) + begin + if (r & SRTYPE) + begin + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + end + else if (SRTYPE) + begin + ce1r <= # ffice ce1; + ce2r <= # ffice ce2; + end + end +// Synchronous Operation +always @ (posedge clkdiv) + begin + if (r & !SRTYPE) + begin + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + end + else if (!SRTYPE) + begin + ce1r <= # ffice ce1; + ce2r <= # ffice ce2; + end + end + +// Output mux +always @ (cesel or ce1 or ce1r or ce2r) + begin + case (cesel) + 2'b00: ice <= # mxice ce1; + 2'b01: ice <= # mxice ce1; + 2'b10: ice <= # mxice ce2r; + 2'b11: ice <= # mxice ce1r; + default: ice <= # mxice ce1; + endcase + end + +/////////////////////// + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ISERDESE2.v b/verilog/src/unisims/ISERDESE2.v new file mode 100644 index 0000000..9e1ad77 --- /dev/null +++ b/verilog/src/unisims/ISERDESE2.v @@ -0,0 +1,765 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Input Deserializer for Virtex7 +// /___/ /\ Filename : ISERDESE2.v +// \ \ / \ Timestamp : Tue Jan 19 16:29:39 PST 2010 +// \___\/\___\ +// +// Revision: +// 01/19/10 - Initial version. +// 03/24/11 - Sync-up +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ISERDESE2 ( + O, + Q1, + Q2, + Q3, + Q4, + Q5, + Q6, + Q7, + Q8, + SHIFTOUT1, + SHIFTOUT2, + + BITSLIP, + CE1, + CE2, + CLK, + CLKB, + CLKDIV, + CLKDIVP, + D, + DDLY, + DYNCLKDIVSEL, + DYNCLKSEL, + OCLK, + OCLKB, + OFB, + RST, + SHIFTIN1, + SHIFTIN2 +); + + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter [0:0] IS_CLKB_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_OCLKB_INVERTED = 1'b0; + parameter [0:0] IS_OCLK_INVERTED = 1'b0; + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter integer NUM_CE = 2; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output Q7; + output Q8; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKB; + input CLKDIV; + input CLKDIVP; + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + input OCLK; + input OCLKB; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; + + tri0 GSR = glbl.GSR; + + reg INTERFACE_TYPE_BINARY; + reg IOBDELAY_BINARY; + reg [0:0] DATA_RATE_BINARY; + reg [0:0] DYN_CLKDIV_INV_EN_BINARY; + reg [0:0] DYN_CLK_INV_EN_BINARY; + reg [0:0] INIT_Q1_BINARY; + reg [0:0] INIT_Q2_BINARY; + reg [0:0] INIT_Q3_BINARY; + reg [0:0] INIT_Q4_BINARY; + reg [0:0] NUM_CE_BINARY; + reg [0:0] SERDES_MODE_BINARY; + reg [1:0] OFB_USED_BINARY; + reg [3:0] DATA_WIDTH_BINARY; + + reg data_in = 0; + reg o_out_pre_fb = 0, o_delay_pre_fb = 0; + reg o_out = 0; + + reg notifier; + + wire O_OUT; + wire Q1_OUT; + wire Q2_OUT; + wire Q3_OUT; + wire Q4_OUT; + wire Q5_OUT; + wire Q6_OUT; + wire Q7_OUT; + wire Q8_OUT; + wire SHIFTOUT1_OUT; + wire SHIFTOUT2_OUT; + + wire BITSLIP_IN; + wire CE1_IN; + wire CE2_IN; + wire CLKB_IN; + wire CLKDIVP_IN; + wire CLKDIV_IN; + wire CLK_IN; + wire DDLY_IN; + wire DYNCLKDIVSEL_IN; + wire DYNCLKSEL_IN; + wire D_IN; + wire OCLKB_IN; + wire OCLK_IN; + wire OFB_IN; + wire RST_IN; + wire SHIFTIN1_IN; + wire SHIFTIN2_IN; + + wire BITSLIP_INDELAY; + wire CE1_INDELAY; + wire CE2_INDELAY; + wire CLKB_INDELAY; + wire CLKDIVP_INDELAY; + wire CLKDIV_INDELAY; + wire CLK_INDELAY; + wire DDLY_INDELAY; + wire DYNCLKDIVSEL_INDELAY; + wire DYNCLKSEL_INDELAY; + wire D_INDELAY; + wire OCLKB_INDELAY; + wire OCLK_INDELAY; + wire OFB_INDELAY; + wire RST_INDELAY; + wire SHIFTIN1_INDELAY; + wire SHIFTIN2_INDELAY; + +//--------------------------------------- + buf B_O (O, O_OUT); + buf B_Q1 (Q1, Q1_OUT); + buf B_Q2 (Q2, Q2_OUT); + buf B_Q3 (Q3, Q3_OUT); + buf B_Q4 (Q4, Q4_OUT); + buf B_Q5 (Q5, Q5_OUT); + buf B_Q6 (Q6, Q6_OUT); + buf B_Q7 (Q7, Q7_OUT); + buf B_Q8 (Q8, Q8_OUT); + buf B_SHIFTOUT1 (SHIFTOUT1, SHIFTOUT1_OUT); + buf B_SHIFTOUT2 (SHIFTOUT2, SHIFTOUT2_OUT); + + buf B_BITSLIP (BITSLIP_IN, BITSLIP); + buf B_CE1 (CE1_IN, CE1); + buf B_CE2 (CE2_IN, CE2); + buf B_CLK (CLK_IN, CLK); + buf B_CLKB (CLKB_IN, CLKB); + buf B_CLKDIV (CLKDIV_IN, CLKDIV); + buf B_CLKDIVP (CLKDIVP_IN, CLKDIVP); + buf B_D (D_IN, D); + buf B_DDLY (DDLY_IN, DDLY); + buf B_DYNCLKDIVSEL (DYNCLKDIVSEL_IN, DYNCLKDIVSEL); + buf B_DYNCLKSEL (DYNCLKSEL_IN, DYNCLKSEL); + buf B_OCLK (OCLK_IN, OCLK); + buf B_OCLKB (OCLKB_IN, OCLKB); + buf B_OFB (OFB_IN, OFB); + buf B_RST (RST_IN, RST); + buf B_SHIFTIN1 (SHIFTIN1_IN, SHIFTIN1); + buf B_SHIFTIN2 (SHIFTIN2_IN, SHIFTIN2); + + wire delay_O; + wire delay_Q1; + wire delay_Q2; + wire delay_Q3; + wire delay_Q4; + wire delay_Q5; + wire delay_Q6; + wire delay_Q7; + wire delay_Q8; + wire delay_SHIFTOUT1; + wire delay_SHIFTOUT2; + + wire delay_BITSLIP,BITSLIP_in; + wire delay_CE1,CE1_in; + wire delay_CE2,CE2_in; + wire delay_CLK,CLK_inv,CLK_in; + wire delay_CLKB,CLKB_inv,CLKB_in; + wire delay_CLKDIV,CLKDIV_inv,CLKDIV_in; + wire delay_CLKDIVP,CLKDIVP_inv,CLKDIVP_in; + wire delay_D,D_inv,D_in; + wire delay_DDLY,DDLY_in; + wire delay_DYNCLKDIVSEL,DYNCLKDIVSEL_in; + wire delay_DYNCLKSEL,DYNCLKSEL_in; + wire delay_OCLK,OCLK_inv,OCLK_in; + wire delay_OCLKB,OCLKB_inv,OCLKB_in; + wire delay_OFB,OFB_in; + wire delay_RST,RST_in; + wire delay_SHIFTIN1,SHIFTIN1_in; + wire delay_SHIFTIN2,SHIFTIN2_in; + + assign #(out_delay) O_OUT = o_out; + assign #(out_delay) Q1_OUT = delay_Q1; + assign #(out_delay) Q2_OUT = delay_Q2; + assign #(out_delay) Q3_OUT = delay_Q3; + assign #(out_delay) Q4_OUT = delay_Q4; + assign #(out_delay) Q5_OUT = delay_Q5; + assign #(out_delay) Q6_OUT = delay_Q6; + assign #(out_delay) Q7_OUT = delay_Q7; + assign #(out_delay) Q8_OUT = delay_Q8; + assign #(out_delay) SHIFTOUT1_OUT = delay_SHIFTOUT1; + assign #(out_delay) SHIFTOUT2_OUT = delay_SHIFTOUT2; + +`ifndef XIL_TIMING // unisim + assign #(in_delay) delay_BITSLIP = BITSLIP; + assign #(in_delay) delay_CE1 = CE1; + assign #(in_delay) delay_CE2 = CE2; + assign #(INCLK_DELAY) delay_CLK = CLK; + assign #(INCLK_DELAY) delay_CLKB = CLKB; + assign #(INCLK_DELAY) delay_CLKDIV = CLKDIV; + assign #(INCLK_DELAY) delay_CLKDIVP = CLKDIVP; + assign #(in_delay) delay_D = D; + assign #(in_delay) delay_DDLY = DDLY; + assign #(in_delay) delay_DYNCLKDIVSEL = DYNCLKDIVSEL; + assign #(in_delay) delay_DYNCLKSEL = DYNCLKSEL; + assign #(INCLK_DELAY) delay_OCLK = OCLK; + assign #(INCLK_DELAY) delay_OCLKB = OCLKB; + assign #(in_delay) delay_OFB = OFB; + assign #(in_delay) delay_RST = RST; + assign #(in_delay) delay_SHIFTIN1 = SHIFTIN1; + assign #(in_delay) delay_SHIFTIN2 = SHIFTIN2; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL; + assign delay_DYNCLKSEL = DYNCLKSEL; + assign delay_OCLK = OCLK; + assign delay_OCLKB = OCLKB; + assign delay_SHIFTIN1 = SHIFTIN1; + assign delay_SHIFTIN2 = SHIFTIN2; +`endif + +//`ifdef XIL_TIMING //Simprim + assign BITSLIP_in = delay_BITSLIP; + assign CE1_in = delay_CE1; + assign CE2_in = delay_CE2; + assign DDLY_in = delay_DDLY; + assign DYNCLKDIVSEL_in = delay_DYNCLKDIVSEL; + assign DYNCLKSEL_in = delay_DYNCLKSEL; + assign OFB_in = delay_OFB; + assign RST_in = delay_RST; + assign SHIFTIN1_in = delay_SHIFTIN1; + assign SHIFTIN2_in = delay_SHIFTIN2; +//`endif + assign CLK_in = IS_CLK_INVERTED ^ delay_CLK; + assign CLKB_in = IS_CLKB_INVERTED ^ delay_CLKB; + assign CLKDIV_in = IS_CLKDIV_INVERTED ^ delay_CLKDIV; + assign CLKDIVP_in = IS_CLKDIVP_INVERTED ^ delay_CLKDIVP; + assign D_in = IS_D_INVERTED ^ delay_D; + assign OCLK_in = IS_OCLK_INVERTED ^ delay_OCLK; + assign OCLKB_in = IS_OCLKB_INVERTED ^ delay_OCLKB; + + assign #(INCLK_DELAY) CLKB_INDELAY = CLKB_IN; + assign #(INCLK_DELAY) CLKDIVP_INDELAY = CLKDIVP_IN; + assign #(INCLK_DELAY) CLKDIV_INDELAY = CLKDIV_IN; + assign #(INCLK_DELAY) CLK_INDELAY = CLK_IN; + assign #(INCLK_DELAY) OCLKB_INDELAY = OCLKB_IN; + assign #(INCLK_DELAY) OCLK_INDELAY = OCLK_IN; + + assign #(in_delay) BITSLIP_INDELAY = BITSLIP_IN; + assign #(in_delay) CE1_INDELAY = CE1_IN; + assign #(in_delay) CE2_INDELAY = CE2_IN; + assign #(in_delay) DDLY_INDELAY = DDLY_IN; + assign #(in_delay) DYNCLKDIVSEL_INDELAY = DYNCLKDIVSEL_IN; + assign #(in_delay) DYNCLKSEL_INDELAY = DYNCLKSEL_IN; + assign #(in_delay) D_INDELAY = D_IN; + assign #(in_delay) OFB_INDELAY = OFB_IN; + assign #(in_delay) RST_INDELAY = RST_IN; + assign #(in_delay) SHIFTIN1_INDELAY = SHIFTIN1_IN; + assign #(in_delay) SHIFTIN2_INDELAY = SHIFTIN2_IN; + assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL_INDELAY; + assign delay_DYNCLKSEL = DYNCLKSEL_INDELAY; +// assign delay_OCLK = OCLK_INDELAY; +// assign delay_OCLKB = OCLKB_INDELAY; +// assign delay_RST = RST_INDELAY; +// assign delay_SHIFTIN1 = SHIFTIN1_INDELAY; +// assign delay_SHIFTIN2 = SHIFTIN2_INDELAY; + +//---------------------------------------------------------- +//------------------------- TASKS -------------------------- +//---------------------------------------------------------- + task INTERFACE_TYPE_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("NETWORKING DDR 4, 6, 8, 10, 14\n"); + $display("MEMORY DDR 4\n"); + end + endtask // INTERFACE_TYPE_msg + + task OVERSAMPLE_DDR_SDR_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("OVERSAMPLE SDR 4\n"); + $display("OVERSAMPLE DDR 4\n"); + end + endtask // OVERSAMPLE_DDR_SDR_msg + +//---------------------------------------------------------- +//------------------ Parameter Checks ---------------------- +//---------------------------------------------------------- + initial begin +//------------------------------------------------- +//----- DATA_RATE check +//------------------------------------------------- + case (DATA_RATE) + "SDR", "DDR" :; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + #1 $finish; + end + endcase // case(DATA_RATE) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10, 14 :; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, 10 or 14", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + + +//------------------------------------------------- +//----- DYN_CLKDIV_INV_EN check +//------------------------------------------------- + case (DYN_CLKDIV_INV_EN) + + "TRUE", "FALSE" :; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN); + #1 $finish; + end + + endcase // case(DYN_CLKDIV_INV_EN) + +//------------------------------------------------- +//----- DYN_CLK_INV_EN check +//------------------------------------------------- + case (DYN_CLK_INV_EN) + + "TRUE", "FALSE" :; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN); + #1 $finish; + end + + endcase // case(DYN_CLK_INV_EN) + +//------------------------------------------------- +//----- IOBDELAY check +//------------------------------------------------- + case (IOBDELAY) + "NONE", "IBUF", "IFD", "BOTH" :; + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + #1 $finish; + end + endcase // case(IOBDELAY) + +//------------------------------------------------- +//----- OFB_USED check +//------------------------------------------------- + case (OFB_USED) + + "TRUE", "FALSE" :; + default : begin + $display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED); + #1 $finish; + end + + endcase // case(OFB_USED) +//------------------------------------------------- +//----- NUM_CE check +//------------------------------------------------- + case (NUM_CE) + + 1, 2 :; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + #1 $finish; + end + + endcase // case(NUM_CE) + + +//------------------------------------------------- +//----- INTERFACE_TYPE check +//------------------------------------------------- + case (INTERFACE_TYPE) + "MEMORY" : begin + case(DATA_RATE) + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : INTERFACE_TYPE_msg; + endcase // DATA_RATE + end + "NETWORKING" : begin + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10, 14 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + "MEMORY_DDR3" :; + "MEMORY_QDR" :; + "OVERSAMPLE" : begin + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 4 : ; + default : OVERSAMPLE_DDR_SDR_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : OVERSAMPLE_DDR_SDR_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE); + #1 $finish; + end + endcase // INTERFACE_TYPE + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) + "MASTER", "SLAVE" :; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + endcase // case(SERDES_MODE) + + end // initial begin + + + +// CR 574021 +//------------------------------------------------- +// Input to ISERDES +//------------------------------------------------- + + always @(D_in or DDLY_in) begin + + case (IOBDELAY) + + "NONE" : begin + o_out_pre_fb <= D_in; + o_delay_pre_fb <= D_in; + + end + "IBUF" : begin + o_out_pre_fb <= DDLY_in; + o_delay_pre_fb <= D_in; + end + "IFD" : begin + o_out_pre_fb <= D_in; + o_delay_pre_fb <= DDLY_in; + end + "BOTH" : begin + o_out_pre_fb <= DDLY_in; + o_delay_pre_fb <= DDLY_in; + end + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + $finish; + end + + endcase // case(IOBDELAY) + + end // always @ (D_in or DDLY_in) + + generate + case (OFB_USED) + "TRUE" : always @(OFB_in) + begin + o_out <= OFB_in; + data_in <= OFB_in; + end + "FALSE" : begin + always @(o_out_pre_fb) o_out <= o_out_pre_fb; + always @(o_delay_pre_fb) data_in <= o_delay_pre_fb; + end + endcase + endgenerate + +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- + B_ISERDESE2 #( + .DATA_RATE (DATA_RATE), + .DATA_WIDTH (DATA_WIDTH), + .DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN), + .DYN_CLK_INV_EN (DYN_CLK_INV_EN), + .INIT_Q1 (INIT_Q1), + .INIT_Q2 (INIT_Q2), + .INIT_Q3 (INIT_Q3), + .INIT_Q4 (INIT_Q4), + .INTERFACE_TYPE (INTERFACE_TYPE), + .IOBDELAY (IOBDELAY), + .NUM_CE (NUM_CE), + .OFB_USED (OFB_USED), + .SERDES_MODE (SERDES_MODE), + .SRVAL_Q1 (SRVAL_Q1), + .SRVAL_Q2 (SRVAL_Q2), + .SRVAL_Q3 (SRVAL_Q3), + .SRVAL_Q4 (SRVAL_Q4)) + + B_ISERDESE2_INST ( + .O (delay_O), + .Q1 (delay_Q1), + .Q2 (delay_Q2), + .Q3 (delay_Q3), + .Q4 (delay_Q4), + .Q5 (delay_Q5), + .Q6 (delay_Q6), + .Q7 (delay_Q7), + .Q8 (delay_Q8), + .SHIFTOUT1 (delay_SHIFTOUT1), + .SHIFTOUT2 (delay_SHIFTOUT2), + .BITSLIP (BITSLIP_in), + .CE1 (CE1_in), + .CE2 (CE2_in), + .CLK (CLK_in), + .CLKB (CLKB_in), + .CLKDIV (CLKDIV_in), + .CLKDIVP (CLKDIVP_in), + .D (data_in), + .DDLY (DDLY_in), + .DYNCLKDIVSEL (DYNCLKDIVSEL_in), + .DYNCLKSEL (DYNCLKSEL_in), + .OCLK (OCLK_in), + .OCLKB (OCLKB_in), + .OFB (OFB_in), + .RST (RST_in), + .SHIFTIN1 (SHIFTIN1_in), + .SHIFTIN2 (SHIFTIN2_in), + .GSR(GSR) + ); + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + wire clkb_en_n; + wire clkb_en_p; + wire clkdiv_en_p; + wire clkdiv_en_n; + wire clkdivp_en_n; + wire clkdivp_en_p; + assign clk_en_n = IS_CLK_INVERTED; + assign clk_en_p = ~IS_CLK_INVERTED; + assign clkb_en_n = IS_CLKB_INVERTED; + assign clkb_en_p = ~IS_CLKB_INVERTED; + assign clkdiv_en_n = IS_CLKDIV_INVERTED; + assign clkdiv_en_p = ~IS_CLKDIV_INVERTED; + assign clkdivp_en_n = IS_CLKDIVP_INVERTED; + assign clkdivp_en_p = ~IS_CLKDIVP_INVERTED; + +`endif + specify +`ifdef XIL_TIMING // Simprim + $period (negedge CLK, 0:0:0, notifier); + $period (negedge CLKB, 0:0:0, notifier); + $period (negedge CLKDIV, 0:0:0, notifier); + $period (negedge CLKDIVP, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKB, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $period (posedge CLKDIVP, 0:0:0, notifier); + + $setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_CE1); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_D); + $setuphold (posedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_DDLY); + $setuphold (posedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OFB); + $setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_CE1); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_D); + $setuphold (posedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_DDLY); + $setuphold (posedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OFB); + $setuphold (posedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_CE1); + $setuphold (posedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_D); + $setuphold (posedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_DDLY); + $setuphold (posedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_OFB); + $setuphold (posedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_CE1); + $setuphold (posedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_D); + $setuphold (posedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_DDLY); + $setuphold (posedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_p, clkb_en_p, delay_CLKB, delay_OFB); + $setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_BITSLIP); + $setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE1); + $setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE2); + $setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_BITSLIP); + $setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE1); + $setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_CE2); + $setuphold (posedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE1); + $setuphold (posedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE2); + $setuphold (posedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE1); + $setuphold (posedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_CE2); + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST); + $setuphold (posedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_RST); + $setuphold (posedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_p, clkdivp_en_p, delay_CLKDIVP, delay_RST); + + $setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_CE1); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_D); + $setuphold (negedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_DDLY); + $setuphold (negedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OFB); + $setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_CE1); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_D); + $setuphold (negedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_DDLY); + $setuphold (negedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OFB); + $setuphold (negedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_CE1); + $setuphold (negedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_D); + $setuphold (negedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_DDLY); + $setuphold (negedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_OFB); + $setuphold (negedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_CE1); + $setuphold (negedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_D); + $setuphold (negedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_DDLY); + $setuphold (negedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, clkb_en_n, clkb_en_n, delay_CLKB, delay_OFB); + $setuphold (negedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_BITSLIP); + $setuphold (negedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE1); + $setuphold (negedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE2); + $setuphold (negedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_BITSLIP); + $setuphold (negedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE1); + $setuphold (negedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_CE2); + $setuphold (negedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE1); + $setuphold (negedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE2); + $setuphold (negedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE1); + $setuphold (negedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_CE2); + $setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST); + $setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST); + $setuphold (negedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_RST); + $setuphold (negedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier, clkdivp_en_n, clkdivp_en_n, delay_CLKDIVP, delay_RST); + + + +`endif + ( CLK => Q1) = (100:100:100, 100:100:100); + ( CLK => Q2) = (100:100:100, 100:100:100); + ( CLK => Q3) = (100:100:100, 100:100:100); + ( CLK => Q4) = (100:100:100, 100:100:100); + ( CLK => Q5) = (100:100:100, 100:100:100); + ( CLK => Q6) = (100:100:100, 100:100:100); + ( CLK => Q7) = (100:100:100, 100:100:100); + ( CLK => Q8) = (100:100:100, 100:100:100); + ( CLKDIV => Q1) = (100:100:100, 100:100:100); + ( CLKDIV => Q2) = (100:100:100, 100:100:100); + ( CLKDIV => Q3) = (100:100:100, 100:100:100); + ( CLKDIV => Q4) = (100:100:100, 100:100:100); + ( CLKDIV => Q5) = (100:100:100, 100:100:100); + ( CLKDIV => Q6) = (100:100:100, 100:100:100); + ( CLKDIV => Q7) = (100:100:100, 100:100:100); + ( CLKDIV => Q8) = (100:100:100, 100:100:100); + ( CLKDIVP => Q1) = (100:100:100, 100:100:100); + ( CLKDIVP => Q2) = (100:100:100, 100:100:100); + ( CLKDIVP => Q3) = (100:100:100, 100:100:100); + ( CLKDIVP => Q4) = (100:100:100, 100:100:100); + ( CLKDIVP => Q5) = (100:100:100, 100:100:100); + ( CLKDIVP => Q6) = (100:100:100, 100:100:100); + ( CLKDIVP => Q7) = (100:100:100, 100:100:100); + ( CLKDIVP => Q8) = (100:100:100, 100:100:100); + ( D => O) = (100:100:100, 100:100:100); + ( DDLY => O) = (100:100:100, 100:100:100); + ( OFB => O) = (100:100:100, 100:100:100); + + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ISERDESE3.v b/verilog/src/unisims/ISERDESE3.v new file mode 100644 index 0000000..dfd37d3 --- /dev/null +++ b/verilog/src/unisims/ISERDESE3.v @@ -0,0 +1,349 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / ISERDESE3 +// /___/ /\ Filename : ISERDESE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ISERDESE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DATA_WIDTH = 8, + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", + parameter FIFO_ENABLE = "FALSE", + parameter FIFO_SYNC_MODE = "FALSE", + parameter IDDR_MODE = "FALSE", + parameter [0:0] IS_CLK_B_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0 +)( + output FIFO_EMPTY, + output INTERNAL_DIVCLK, + output [7:0] Q, + + input CLK, + input CLKDIV, + input CLK_B, + input D, + input FIFO_RD_CLK, + input FIFO_RD_EN, + input RST +); + +// define constants + localparam MODULE_NAME = "ISERDESE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "ISERDESE3_dr.v" +`else + localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH; + localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE; + localparam [40:1] FIFO_ENABLE_REG = FIFO_ENABLE; + localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE; + localparam [40:1] IDDR_MODE_REG = IDDR_MODE; + localparam [0:0] IS_CLK_B_INVERTED_REG = IS_CLK_B_INVERTED; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; +`endif + + localparam [40:1] DDR_DIS_DQS_REG = "FALSE"; + localparam [1:0] SPARE_REG = 2'b00; + + wire IS_CLK_B_INVERTED_BIN; + wire IS_CLK_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire FIFO_EMPTY_out; + wire INTERNAL_DIVCLK_out; + wire [7:0] Q_out; + + wire FIFO_EMPTY_delay; + wire INTERNAL_DIVCLK_delay; + wire [7:0] Q_delay; + + wire CLKDIV_in; + wire CLK_B_in; + wire CLK_in; + wire D_in; + wire FIFO_RD_CLK_in; + wire FIFO_RD_EN_in; + wire IFD_CE_in; + wire RST_in; + + wire CLKDIV_delay; + wire CLK_B_delay; + wire CLK_delay; + wire D_delay; + wire FIFO_RD_CLK_delay; + wire FIFO_RD_EN_delay; + wire RST_delay; + + + assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay; + assign #(out_delay) INTERNAL_DIVCLK = INTERNAL_DIVCLK_delay; + assign #(out_delay) Q = Q_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLKDIV_delay = CLKDIV; + assign #(inclk_delay) CLK_B_delay = CLK_B; + assign #(inclk_delay) CLK_delay = CLK; + assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK; + + assign #(in_delay) D_delay = D; + assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN; + assign #(in_delay) RST_delay = RST; +`endif // `ifndef XIL_TIMING + + + assign FIFO_EMPTY_delay = FIFO_EMPTY_out; + assign INTERNAL_DIVCLK_delay = INTERNAL_DIVCLK_out; + assign Q_delay = Q_out; + + assign CLKDIV_in = CLKDIV_delay; + assign CLK_B_in = CLK_B_delay ^ IS_CLK_B_INVERTED_BIN; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign D_in = D_delay; + assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay; + assign FIFO_RD_EN_in = FIFO_RD_EN_delay; + assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN; + + assign IS_CLK_B_INVERTED_BIN = IS_CLK_B_INVERTED_REG; + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DATA_WIDTH_REG != 8) && + (DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") && + (DDR_CLK_EDGE_REG != "SAME_EDGE") && + (DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED"))) begin + $display("Error: [Unisim %s-102] DDR_CLK_EDGE attribute is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED. Instance: %m", MODULE_NAME, DDR_CLK_EDGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIFO_ENABLE_REG != "FALSE") && + (FIFO_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] FIFO_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIFO_SYNC_MODE_REG != "FALSE") && + (FIFO_SYNC_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IDDR_MODE_REG != "FALSE") && + (IDDR_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] IDDR_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IDDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-110] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-111] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign IFD_CE_in = 1'b0; // tie off + +generate +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_ISERDESE3_D1 SIP_ISERDESE3_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DDR_CLK_EDGE (DDR_CLK_EDGE_REG), + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .FIFO_ENABLE (FIFO_ENABLE_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .IDDR_MODE (IDDR_MODE_REG), + .SPARE (SPARE_REG), + .FIFO_EMPTY (FIFO_EMPTY_out), + .INTERNAL_DIVCLK (INTERNAL_DIVCLK_out), + .Q (Q_out), + .CLK (CLK_in), + .CLKDIV (CLKDIV_in), + .CLK_B (CLK_B_in), + .D (D_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .RST (RST_in), + .GSR (glblGSR) + ); +end else begin : generate_block1 + + SIP_ISERDESE3 SIP_ISERDESE3_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DDR_CLK_EDGE (DDR_CLK_EDGE_REG), + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .FIFO_ENABLE (FIFO_ENABLE_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .IDDR_MODE (IDDR_MODE_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .FIFO_EMPTY (FIFO_EMPTY_out), + .INTERNAL_DIVCLK (INTERNAL_DIVCLK_out), + .Q (Q_out), + .CLK (CLK_in), + .CLKDIV (CLKDIV_in), + .CLK_B (CLK_B_in), + .D (D_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .RST (RST_in), + .GSR (glblGSR) + ); + end +endgenerate +`ifdef XIL_TIMING + reg notifier; + + wire clk_b_en_n; + wire clk_b_en_p; + wire clk_en_n; + wire clk_en_p; + + assign clk_b_en_n = IS_CLK_B_INVERTED_BIN; + assign clk_b_en_p = ~IS_CLK_B_INVERTED_BIN; + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; +`endif + + specify + (CLK *> Q) = (100:100:100, 100:100:100); + (CLK => FIFO_EMPTY) = (100:100:100, 100:100:100); + (CLK => INTERNAL_DIVCLK) = (100:100:100, 100:100:100); + (CLK_B *> Q) = (100:100:100, 100:100:100); + (FIFO_RD_CLK *> Q) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100); + (negedge RST *> (Q +: 0)) = (100:100:100, 100:100:100); + (posedge RST *> (Q +: 0)) = (100:100:100, 100:100:100); + // (INTERNAL_DIVCLK *> Q) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (negedge CLKDIV, 0:0:0, notifier); + $period (negedge CLK_B, 0:0:0, notifier); + $period (negedge FIFO_RD_CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $period (posedge CLK_B, 0:0:0, notifier); + $period (posedge FIFO_RD_CLK, 0:0:0, notifier); + $recrem (negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_delay, CLK_delay); + $recrem (negedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, RST_delay, CLK_B_delay); + $recrem (negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_delay, CLK_delay); + $recrem (negedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, RST_delay, CLK_B_delay); + $recrem (posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_delay, CLK_delay); + $recrem (posedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, RST_delay, CLK_B_delay); + $recrem (posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_delay, CLK_delay); + $recrem (posedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, RST_delay, CLK_B_delay); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay); + $setuphold (negedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, CLK_B_delay, D_delay); + $setuphold (negedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, CLK_B_delay, D_delay); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay); + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, , , CLKDIV_delay, RST_delay); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, , , CLKDIV_delay, RST_delay); + $setuphold (posedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, CLK_B_delay, D_delay); + $setuphold (posedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, CLK_B_delay, D_delay); + $setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLKDIV, 0:0:0, 0, notifier); + $width (negedge CLK_B, 0:0:0, 0, notifier); + $width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLKDIV, 0:0:0, 0, notifier); + $width (posedge CLK_B, 0:0:0, 0, notifier); + $width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ISERDES_NODELAY.v b/verilog/src/unisims/ISERDES_NODELAY.v new file mode 100644 index 0000000..17a5826 --- /dev/null +++ b/verilog/src/unisims/ISERDES_NODELAY.v @@ -0,0 +1,1136 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Input Deserializer without delay element +// /___/ /\ Filename : ISERDES_NODELAY.v +// \ \ / \ Timestamp : Fri Oct 21 10:31:45 PDT 2005 +// \___\/\___\ +// +// Revision: +// 10/21/05 - Initial version. +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real) +// 06/16/06 - Added new port CLKB +// 10/13/06 - Fixed CR 426606 +// 07/07/07 - Added wire declaration for internal signals +// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations +// 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations +// 01/12/11 - CR 589496 changed some internal parameters to localparams +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2); + + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKB; + input CLKDIV; + input D; + input OCLK; + input RST; + input SHIFTIN1; + input SHIFTIN2; + + localparam SRVAL_Q1 = 1'b0; + localparam SRVAL_Q2 = 1'b0; + localparam SRVAL_Q3 = 1'b0; + localparam SRVAL_Q4 = 1'b0; + + tri0 GSR = glbl.GSR; + + reg [1:0] sel; + reg [3:0] data_width_int; + reg bts_q1, bts_q2, bts_q3; + reg c23, c45, c67; + reg ce1r, ce2r; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + reg ice, memmux, q2pmux; + reg mux, mux1, muxc; + reg notifier; + reg clkdiv_int, clkdivmux; + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg num_ce_int; + reg qr1, qr2, qhc1, qhc2, qlc1, qlc2; + reg shiftn2_in, shiftn1_in; + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg serdes_mode_int, data_rate_int, bitslip_enable_int; + + wire o_delay; + + reg rev_in = 0; + + wire shiftout1_out, shiftout2_out; + wire [1:0] sel1; + wire [2:0] bsmux; + wire [3:0] selrnk3; + + wire bitslip_in; + wire ce1_in; + wire ce2_in; + wire clk_in; + wire clkb_in; + wire clkdiv_in; + wire d_in; + wire dlyce_in; + wire dlyinc_in; + wire dlyrst_in; + wire gsr_in; + wire oclk_in; + wire sr_in; + wire shiftin1_in; + wire shiftin2_in; + + buf b_q1 (Q1, q1_out); + buf b_q2 (Q2, q2_out); + buf b_q3 (Q3, q3_out); + buf b_q4 (Q4, q4_out); + buf b_q5 (Q5, q5_out); + buf b_q6 (Q6, q6_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + + buf b_bitslip (bitslip_in, BITSLIP); + buf b_ce1 (ce1_in, CE1); + buf b_ce2 (ce2_in, CE2); + buf b_clk (clk_in, CLK); + buf b_clkb (clkb_in, CLKB); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d (d_in, D); + buf b_gsr (gsr_in, GSR); + buf b_oclk (oclk_in, OCLK); + buf b_sr (sr_in, RST); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + +// WARNING !!!: This model may not work properly if the +// following parameters are changed. + +// xilinx_internal_parameter on + + +// Parameter declarations for delays + localparam ffinp = 300; + localparam mxinp1 = 60; + localparam mxinp2 = 120; + +// Delay parameters + + localparam ffice = 300; + localparam mxice = 60; + +// Delay parameter assignment + + localparam ffbsc = 300; + localparam mxbsc = 60; + + localparam mxinp1_my = 0; + +// xilinx_internal_parameter off + +// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------ + task CR454107_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("NETWORKING DDR 4, 6, 8, 10\n"); + $display("MEMORY SDR None\n"); + $display("MEMORY DDR 4\n"); + end + endtask // CR454107_msg + + initial begin + +// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------ + case (INTERFACE_TYPE) + "NETWORKING" : + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + "MEMORY" : + case(DATA_RATE) + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + default : CR454107_msg; + endcase // DATA_RATE + default : ; + endcase // INTERFACE_TYPE + +// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin + $display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."); + #1 $finish; + end + else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin + $display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."); + #1 $finish; + end + +//------------------------------------------------------------------------------------ + + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + endcase // case(SERDES_MODE) + + + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + #1 $finish; + end + endcase // case(DATA_RATE) + + + case (BITSLIP_ENABLE) + + "FALSE" : bitslip_enable_int <= 1'b0; + "TRUE" : bitslip_enable_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE); + #1 $finish; + end + + endcase // case(BITSLIP_ENABLE) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + + + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + #1 $finish; + end + + endcase // case(NUM_CE) + + end // initial begin + + + assign sel1 = {serdes_mode_int, data_rate_int}; + + assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00}; + + assign bsmux = {bitslip_enable_int, data_rate_int, muxc}; + + + +// GSR + always @(gsr_in) begin + + if (gsr_in == 1'b1) begin + + assign bts_q3 = 1'b0; + assign bts_q2 = 1'b0; + assign bts_q1 = 1'b0; + assign clkdiv_int = 1'b0; + + assign ce1r = 1'b0; + assign ce2r = 1'b0; + + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + + end + else if (gsr_in == 1'b0) begin + + + deassign bts_q3; + deassign bts_q2; + deassign bts_q1; + deassign clkdiv_int; + + deassign ce1r; + deassign ce2r; + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + + end // if (gsr_in == 1'b0) + end // always @ (gsr_in) + + + +// to workaround the glitches generated by mux of assign delay above +// always @(delay_count) +// delay_count_int <= #0 delay_count; + + assign o_delay = d_in; + +// 1st rank of registers + +// Asynchronous Operation + always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin +// 1st flop in rank 1 that is full featured + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1)) + + q1rnk1 <= # ffinp SRVAL_Q1; + + else if (rev_in == 1'b1) + + q1rnk1 <= # ffinp !SRVAL_Q1; + + else if (ice == 1'b1) + + q1rnk1 <= # ffinp o_delay; + + end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + + always @(posedge clk_in or posedge sr_in) begin +// rest of flops which are not full featured and don't have clock options + + if (sr_in == 1'b1) begin + + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + + end + else begin + + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + + end + + end // always @ (posedge clk_in or sr_in) + + +// 2nd flop in rank 1 + +// Asynchronous Operation + always @(posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1)) + + q2nrnk1 <= # ffinp SRVAL_Q2; + + else if (rev_in == 1'b1) + + q2nrnk1 <= # ffinp !SRVAL_Q2; + + else if (ice == 1'b1) + + q2nrnk1 <= # ffinp o_delay; + + end // always @ (posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 4th flop in rank 1 operating on the posedge for networking +// Asynchronous Operation + always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1)) + + q2prnk1 <= # ffinp SRVAL_Q4; + + else if (rev_in == 1'b1) + + q2prnk1 <= # ffinp !SRVAL_Q4; + + else if (ice == 1'b1) + + q2prnk1 <= # ffinp q2nrnk1; + + end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 3rd flop in 2nd rank which is full featured and has +// a choice of being clocked by oclk or clk + +// Asynchronous Operation + always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1)) + + q1prnk1 <= # ffinp SRVAL_Q3; + + else if (rev_in == 1'b1) + + q1prnk1 <= # ffinp !SRVAL_Q3; + + else if (ice == 1'b1) + + q1prnk1 <= # ffinp q1rnk1; + + end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + always @(posedge memmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + + end + else begin + + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + + end + + end // always @ (posedge memmux or posedge sr_in) + + +////////////////////////////////////////// +// Mux elements for the 1st rank +//////////////////////////////////////// + +// Optional inverter for q2p (4th flop in rank1) + always @ (memmux) begin + + case (INTERFACE_TYPE) + + "MEMORY" : q2pmux <= # mxinp1 !memmux; + "NETWORKING" : q2pmux <= # mxinp1 memmux; + default: q2pmux <= # mxinp1 !memmux; + + endcase + + end // always @ (memmux) + + +// 4 clock muxs in first rank + always @(clk_in or oclk_in) begin + + case (INTERFACE_TYPE) + + "MEMORY" : memmux <= # mxinp1 oclk_in; + "NETWORKING" : memmux <= # mxinp1 clk_in; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE); + $finish; + end + + endcase // case(INTERFACE_TYPE) + + end // always @(clk_in or oclk_in) + + + + +// data input mux for q3, q4, q5 and q6 + always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + + case (sel1) + + 2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in; + default : dataq3rnk1 <= # mxinp1 q1prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2) + + + always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + + case (sel1) + + 2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1; + default : dataq4rnk1 <= # mxinp1 q2prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1) + + + always @(data_rate_int or q3rnk1 or q4rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1; + default : dataq5rnk1 <= # mxinp1 q4rnk1; + + endcase // case(DATA_RATE) + + end + + + always @(data_rate_int or q4rnk1 or q5rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1; + default : dataq6rnk1 <= # mxinp1 q5rnk1; + + endcase // case(DATA_RATE) + + end + + +// 2nd rank of registers + +// clkdivmux to pass clkdiv_int or CLKDIV to rank 2 + always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin + + case (bitslip_enable_int) + + 1'b0 : clkdivmux <= # mxinp1 clkdiv_in; + 1'b1 : clkdivmux <= # mxinp1 clkdiv_int; + default : clkdivmux <= # mxinp1 clkdiv_in; + + endcase // case(BITSLIP_ENABLE) + + end // always @(clkdiv_int or clkdiv_in) + + + +// Asynchronous Operation + always @(posedge clkdivmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk2 <= # ffinp 1'b0; + q2rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + + end + else begin + + q1rnk2 <= # ffinp dataq1rnk2; + q2rnk2 <= # ffinp dataq2rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + + end + + end // always @ (posedge clkdivmux or sr_in) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + + casex (bsmux) + + 3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1; + 3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1; + default : dataq1rnk2 <= # mxinp2 q2prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + + always @(bsmux or q1prnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1; + 3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1; + default : dataq2rnk2 <= # mxinp2 q1prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1prnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1; + 3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1; + default : dataq3rnk2 <= # mxinp2 q4rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1; + 3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1; + default : dataq4rnk2 <= # mxinp2 q3rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1; + 3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1; + default : dataq5rnk2 <= # mxinp2 q6rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + + casex (bsmux) + + 3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1; + 3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1; + default : dataq6rnk2 <= # mxinp2 q5rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +// 3rd rank of registers + +// Asynchronous Operation + always @(posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + + end + else begin + + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Outputs + + assign shiftout2_out = q5rnk1; + + assign shiftout1_out = q6rnk1; + + + always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q1_out <= # mxinp1_my q1prnk1; + 4'b0X01 : q1_out <= # mxinp1_my q1rnk1; + 4'b0X10 : q1_out <= # mxinp1_my q1rnk1; + 4'b10XX : q1_out <= # mxinp1_my q1rnk2; + 4'b11XX : q1_out <= # mxinp1_my q1rnk3; + default : q1_out <= # mxinp1_my q1rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) + + + always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X01 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X10 : q2_out <= # mxinp1_my q2nrnk1; + 4'b10XX : q2_out <= # mxinp1_my q2rnk2; + 4'b11XX : q2_out <= # mxinp1_my q2rnk3; + default : q2_out <= # mxinp1_my q2rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) + + + always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin + + case (bitslip_enable_int) + + 1'b0 : q3_out <= # mxinp1_my q3rnk2; + 1'b1 : q3_out <= # mxinp1_my q3rnk3; + + endcase // case(BITSLIP_ENABLE) + + end // always @ (q3rnk2 or q3rnk3) + + + + + always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q4_out <= # mxinp1_my q4rnk2; + 1'b1 : q4_out <= # mxinp1_my q4rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q4rnk2 or q4rnk3) + + + always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q5_out <= # mxinp1_my q5rnk2; + 1'b1 : q5_out <= # mxinp1_my q5rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q5rnk2 or q5rnk3) + + + always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q6_out <= # mxinp1_my q6rnk2; + 1'b1 : q6_out <= # mxinp1_my q6rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q6rnk2 or q6rnk3) + + + + + +// Set value of counter in bitslip controller + always @(data_rate_int or data_width_int) begin + + casex ({data_rate_int, data_width_int}) + + 5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default : begin + $display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + $finish; + end + + endcase + + end // always @ (data_rate_int or data_width_int) + + + + + +/////////////////////////////////////////// +// Bit slip controler +/////////////////////////////////////////// + + +// Divide by 2 - 8 counter + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b0) begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Synchronous Operation + always @ (negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b1) begin + + clkdiv_int <= # ffbsc clkdiv_int; + bts_q1 <= # ffbsc bts_q1; + bts_q2 <= # ffbsc bts_q2; + bts_q3 <= # ffbsc bts_q3; + + end + else begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (negedge clk_in) + + +// 4:1 selector mux and divider selections + always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin + + case (sel) + + 2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + 2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2)); + 2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3)); + 2'b11 : mux <= # mxbsc !bts_q3; + default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + + endcase + + end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) + + + +// Bitslip control logic +// Low speed control flop + +// Asynchronous Operation + always @ (posedge qr1 or posedge clkdiv_in) begin + + if (qr1 == 1'b1) begin + + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + + end + else if (bitslip_in == 1'b0) begin + + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + + end + else begin + + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip_in & mux1); + + end + + end // always @ (posedge qr1 or posedge clkdiv_in) + + +// Mux to select between sdr "1" and ddr "0" + + always @ (data_rate_int or qlc1) begin + + case (data_rate_int) + + 1'b0 : mux1 <= # mxbsc qlc1; + 1'b1 : mux1 <= # mxbsc 1'b1; + + endcase + + end + + + +// High speed control flop + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + + end + else begin + + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Mux that drives control line of mux in front +// of 2nd rank of flops + + always @ (data_rate_int or mux1) begin + + case (data_rate_int) + + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + + endcase + + end + + +// Asynchronous set flops + +// Low speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qr1 <= # ffbsc 1'b1; + + else + + qr1 <= # ffbsc 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or negedge clk_in) begin + + if (sr_in == 1'b1) + + qr2 <= # ffbsc 1'b1; + + else + + qr2 <= # ffbsc qr1; + + end // always @ (posedge sr_in or negedge clk_in) + + +///////////////////////////////////////////// +// ICE +/////////////////////////////////////////// + + +// Asynchronous Operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + + end + else begin + + ce1r <= # ffice ce1_in; + ce2r <= # ffice ce2_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + + // Output mux ice + always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin + case ({num_ce_int, clkdiv_in}) + 2'b00 : ice <= # mxice ce1_in; + 2'b01 : ice <= # mxice ce1_in; +// 426606 + 2'b10 : ice <= # mxice ce2r; + 2'b11 : ice <= # mxice ce1r; + default : ice <= # mxice ce1_in; + endcase + end + +//*** Timing Checks Start here + + specify + + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ISERDES_NODELAY + +`endcelldefine diff --git a/verilog/src/unisims/JTAG_SIME2.v b/verilog/src/unisims/JTAG_SIME2.v new file mode 100644 index 0000000..e484410 --- /dev/null +++ b/verilog/src/unisims/JTAG_SIME2.v @@ -0,0 +1,879 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Jtag TAP Controler for VIRTEX7 +// /___/ /\ Filename : JTAG_SIME2.v +// \ \ / \ Timestamp : Mon May 17 17:10:29 PDT 2010 +// \___\/\___\ +// +// Revision: +// 05/17/10 - Initial version. +// 11/30/11 - 632642 - Updated supported devices and corresponding IDCODES. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 07/05/12 - Updated the simulation model (CR 667100). +// 07/23/12 - Fixed IRLengthMax (CR 669116). +// 04/07/15 - Added negedge to RESET, RUNTEST, UPDATE and TDO (CR 857726). +// End Revision + +`timescale 1 ps/1 ps + +`celldefine + +module JTAG_SIME2( TDO, TCK, TDI, TMS); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + + parameter PART_NAME = "7K325T"; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- +// localparam IRLengthMax = 10; + localparam IRLengthMax = 24; + localparam IDLength = 32; + + reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 24'b010001010001010001010001, + BYPASS_INSTR = 24'b111111111111111111111111, + IDCODE_INSTR = 24'b001001001001001001001001, + USER1_INSTR = 24'b000010100100100100100100, + USER2_INSTR = 24'b000011100100100100100100, + USER3_INSTR = 24'b100010100100100100100100, + USER4_INSTR = 24'b100011100100100100100100; + +// localparam IRLength = 10; + localparam IRLength = ( + (PART_NAME == "XCKU3P") || (PART_NAME == "xcku3p") || + (PART_NAME == "XCKU9P") || (PART_NAME == "xcku9p") || + (PART_NAME == "XCKU11P") || (PART_NAME == "xcku11p") || + (PART_NAME == "XCKU13EG") || (PART_NAME == "xcku13eg") || + (PART_NAME == "XCKU15P") || (PART_NAME == "xcku15p") || + (PART_NAME == "XCKU5P") || (PART_NAME == "xcku5p") || + (PART_NAME == "XCVU3P") || (PART_NAME == "xcvu3p") || + (PART_NAME == "KU025") || (PART_NAME == "ku025") || + (PART_NAME == "KU035") || (PART_NAME == "ku035") || + (PART_NAME == "KU040") || (PART_NAME == "ku040") || + (PART_NAME == "KU060") || (PART_NAME == "ku060") || + (PART_NAME == "KU095") || (PART_NAME == "ku095") || + (PART_NAME == "VU065") || (PART_NAME == "vu065") || + (PART_NAME == "VU080") || (PART_NAME == "vu080") || + (PART_NAME == "VU095") || (PART_NAME == "vu095") || + (PART_NAME == "7A15T") || (PART_NAME == "7a15t") || + (PART_NAME == "7A25T") || (PART_NAME == "7a25t") || + (PART_NAME == "7S15") || (PART_NAME == "7s15") || + (PART_NAME == "7S100") || (PART_NAME == "7s100") || + (PART_NAME == "7A35T") || (PART_NAME == "7a35t") || + (PART_NAME == "7A50T") || (PART_NAME == "7a50t") || + (PART_NAME == "7A75T") || (PART_NAME == "7a75t") || + (PART_NAME == "7A100T") || (PART_NAME == "7a100t") || + (PART_NAME == "7A200T") || (PART_NAME == "7a200t") || + (PART_NAME == "7K70T") || (PART_NAME == "7k70t") || + (PART_NAME == "7K160T") || (PART_NAME == "7k160t") || + (PART_NAME == "7K325T") || (PART_NAME == "7k325t") || + (PART_NAME == "7K355T") || (PART_NAME == "7k355t") || + (PART_NAME == "7K410T") || (PART_NAME == "7k410t") || + (PART_NAME == "7K420T") || (PART_NAME == "7k420t") || + (PART_NAME == "7K480T") || (PART_NAME == "7k480t") || + (PART_NAME == "7V585T") || (PART_NAME == "7v585t")) ? 6 : ( + (PART_NAME == "XCZU9EG") || (PART_NAME == "xczu9eg") || + (PART_NAME == "XCVU5P") || (PART_NAME == "xcvu5p") || + (PART_NAME == "XCVU7P") || (PART_NAME == "xcvu7p") || + (PART_NAME == "KU085") || (PART_NAME == "ku085") || + (PART_NAME == "KU115") || (PART_NAME == "ku115") || + (PART_NAME == "VU125") || (PART_NAME == "vu125")) ? 12 : ( + (PART_NAME == "XCZU3EG") || (PART_NAME == "xczu3eg") || + (PART_NAME == "XCZU4EG") || (PART_NAME == "xczu4eg") || + (PART_NAME == "XCZU5EG") || (PART_NAME == "xczu5eg") || + (PART_NAME == "XCZU7EG") || (PART_NAME == "xczu7eg") || + (PART_NAME == "XCZU2CG") || (PART_NAME == "xczu2cg") || + (PART_NAME == "XCZU3CG") || (PART_NAME == "xczu3cg") || + (PART_NAME == "XCZU4CG") || (PART_NAME == "xczu4cg") || + (PART_NAME == "XCZU5CG") || (PART_NAME == "xczu5cg") || + (PART_NAME == "XCZU6CG") || (PART_NAME == "xczu6cg") || + (PART_NAME == "XCZU7CG") || (PART_NAME == "xczu7cg") || + (PART_NAME == "XCZU9CG") || (PART_NAME == "xczu9cg") || + (PART_NAME == "XCZU5EV") || (PART_NAME == "xczu5ev") || + (PART_NAME == "XCZU11EG") || (PART_NAME == "xczu11eg") || + (PART_NAME == "XCZU15EG") || (PART_NAME == "xczu15eg") || + (PART_NAME == "XCZU19EG") || (PART_NAME == "xczu19eg") || + (PART_NAME == "XCZU7EV") || (PART_NAME == "xczu7ev") || + (PART_NAME == "XCZU2EG") || (PART_NAME == "xczu2eg") || + (PART_NAME == "XCZU4EV") || (PART_NAME == "xczu4ev") || + (PART_NAME == "XCZU6EG") || (PART_NAME == "xczu6eg") || + (PART_NAME == "XCZU17EG") || (PART_NAME == "xczu17eg")) ? 16 : ( + (PART_NAME == "XCVU13P") || (PART_NAME == "xcvu13p") || + (PART_NAME == "7V2000T") || (PART_NAME == "7v2000t")) ? 24 : ( + (PART_NAME == "7VH580T") || (PART_NAME == "7vh580t")) ? 22 : ( + (PART_NAME == "7VH870T") || (PART_NAME == "7vh870t")) ? 38 : ( + (PART_NAME == "7VX330T") || (PART_NAME == "7vx330t") || + (PART_NAME == "7VX415T") || (PART_NAME == "7vx415t") || + (PART_NAME == "7VX485T") || (PART_NAME == "7vx485t") || + (PART_NAME == "7VX550T") || (PART_NAME == "7vx550t") || + (PART_NAME == "7VX690T") || (PART_NAME == "7vx690t") || + (PART_NAME == "7VX980T") || (PART_NAME == "7vx980t")) ? 6 : ( + (PART_NAME == "7VX1140T") || (PART_NAME == "7vx1140t")) ? 24 : ( + (PART_NAME == "7Z010") || (PART_NAME == "7z010") || + (PART_NAME == "7Z015") || (PART_NAME == "7z015") || + (PART_NAME == "7Z020") || (PART_NAME == "7z020") || + (PART_NAME == "7Z030") || (PART_NAME == "7z030") || + (PART_NAME == "7Z035") || (PART_NAME == "7z035") || + (PART_NAME == "7Z045") || (PART_NAME == "7z045") || + (PART_NAME == "7Z007S") || (PART_NAME == "7z007s") || + (PART_NAME == "7Z012S") || (PART_NAME == "7z012s") || + (PART_NAME == "7Z014S") || (PART_NAME == "7z014s") || + (PART_NAME == "7Z100") || (PART_NAME == "7z100")) ? 6 : ( + (PART_NAME == "XCVU9P") || (PART_NAME == "xcvu9p") || + (PART_NAME == "XCVU11P") || (PART_NAME == "xcvu11p") || + (PART_NAME == "VU160") || (PART_NAME == "vu160") || + (PART_NAME == "VU190") || (PART_NAME == "vu190") || + (PART_NAME == "VU440") || (PART_NAME == "vu440")) ? 18 : 24 ; +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + reg Rti_sig = 0; + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "7A15T", "7a15t" : IDCODEval_sig <= 32'h0362E093; + "7A25T", "7a25t" : IDCODEval_sig <= 32'h037C2093; + "7A35T", "7a35t" : IDCODEval_sig <= 32'h0362D093; + "7A50T", "7a50t" : IDCODEval_sig <= 32'h0362C093; + "7A75T", "7a75t" : IDCODEval_sig <= 32'h03632093; + "7A100T", "7a100t" : IDCODEval_sig <= 32'h03631093; + "7A200T", "7a200t" : IDCODEval_sig <= 32'h03636093; + "7K70T", "7k70t" : IDCODEval_sig <= 32'h03647093; + "7K160T", "7k160t" : IDCODEval_sig <= 32'h0364C093; + "7K325T", "7k325t" : IDCODEval_sig <= 32'h03651093; + "7K355T", "7k355t" : IDCODEval_sig <= 32'h03747093; + "7K410T", "7k410t" : IDCODEval_sig <= 32'h03656093; + "7K420T", "7k420t" : IDCODEval_sig <= 32'h03752093; + "7K480T", "7k480t" : IDCODEval_sig <= 32'h03751093; + "7S15", "7s15" : IDCODEval_sig <= 32'h03620093; + "7S100", "7s100" : IDCODEval_sig <= 32'h037C7093; + "7V585T", "7v585t" : IDCODEval_sig <= 32'h03671093; + "7V2000T", "7v2000t" : IDCODEval_sig <= 32'h036B3093; + "7VH580T", "7vh580t" : IDCODEval_sig <= 32'h036D9093; + "7VH870T", "7vh870t" : IDCODEval_sig <= 32'h036DB093; + "7VX330T", "7vx330t" : IDCODEval_sig <= 32'h03667093; + "7VX415T", "7vx415t" : IDCODEval_sig <= 32'h03682093; + "7VX485T", "7vx485t" : IDCODEval_sig <= 32'h03687093; + "7VX550T", "7vx550t" : IDCODEval_sig <= 32'h03692093; + "7VX690T", "7vx690t" : IDCODEval_sig <= 32'h03691093; + "7VX980T", "7vx980t" : IDCODEval_sig <= 32'h03696093; + "7VX1140T", "7vx1140t" : IDCODEval_sig <= 32'h036D5093; + "7Z010", "7z010" : IDCODEval_sig <= 32'h03722093; + "7Z015", "7z015" : IDCODEval_sig <= 32'h0373B093; + "7Z020", "7z020" : IDCODEval_sig <= 32'h03727093; + "7Z030", "7z030" : IDCODEval_sig <= 32'h0372C093; + "7Z035", "7z035" : IDCODEval_sig <= 32'h03732093; + "7Z045", "7z045" : IDCODEval_sig <= 32'h03731093; + "7Z100", "7z100" : IDCODEval_sig <= 32'h03736093; + "7Z007S", "7z007s" : IDCODEval_sig <= 32'h03723093; + "7Z012S", "7z012s" : IDCODEval_sig <= 32'h0373C093; + "7Z014S", "7z014s" : IDCODEval_sig <= 32'h03728093; + "KU025", "ku025" : IDCODEval_sig <= 32'h03824093; + "KU035", "ku035" : IDCODEval_sig <= 32'h03823093; + "KU040", "ku040" : IDCODEval_sig <= 32'h03822093; + "KU060", "ku060" : IDCODEval_sig <= 32'h03919093; + "KU085", "ku085" : IDCODEval_sig <= 32'h0390F093; + "KU095", "ku095" : IDCODEval_sig <= 32'h03844093; + "KU115", "ku115" : IDCODEval_sig <= 32'h0390D093; + "VU065", "vu065" : IDCODEval_sig <= 32'h03939093; + "VU080", "vu080" : IDCODEval_sig <= 32'h03843093; + "VU095", "vu095" : IDCODEval_sig <= 32'h03842093; + "VU125", "vu125" : IDCODEval_sig <= 32'h0392D093; + "VU160", "vu160" : IDCODEval_sig <= 32'h03933093; + "VU190", "vu190" : IDCODEval_sig <= 32'h03931093; + "VU440", "vu440" : IDCODEval_sig <= 32'h0396D093; + "XCKU3P", "xcku3p" : IDCODEval_sig <= 32'h04A46093; + "XCKU9P", "xcku9p" : IDCODEval_sig <= 32'h0484A093; + "XCKU11P", "xcku11p" : IDCODEval_sig <= 32'h04A4E093; + "XCKU13EG", "xcku13eg" : IDCODEval_sig <= 32'h04A52093; + "XCKU15P", "xcku15p" : IDCODEval_sig <= 32'h04A56093; + "XCKU5P", "xcku5p" : IDCODEval_sig <= 32'h04A62093; + "XCVU3P", "xcvu3p" : IDCODEval_sig <= 32'h04B39093; + "XCZU9EG", "xczu9eg" : IDCODEval_sig <= 32'h04738093; + "XCVU5P", "xcvu5p" : IDCODEval_sig <= 32'h04B2B093; + "XCVU7P", "xcvu7p" : IDCODEval_sig <= 32'h04B29093; + "XCZU3EG", "xczu3eg" : IDCODEval_sig <= 32'h04710093; + "XCZU4EG", "xczu4eg" : IDCODEval_sig <= 32'h04A47093; + "XCZU5EG", "xczu5eg" : IDCODEval_sig <= 32'h04A46093; + "XCZU7EG", "xczu7eg" : IDCODEval_sig <= 32'h04A5A093; + "XCZU2CG", "xczu2cg" : IDCODEval_sig <= 32'h04A43093; + "XCZU3CG", "xczu3cg" : IDCODEval_sig <= 32'h04A42093; + "XCZU4CG", "xczu4cg" : IDCODEval_sig <= 32'h04A47093; + "XCZU5CG", "xczu5cg" : IDCODEval_sig <= 32'h04A46093; + "XCZU6CG", "xczu6cg" : IDCODEval_sig <= 32'h0484B093; + "XCZU7CG", "xczu7cg" : IDCODEval_sig <= 32'h04A5A093; + "XCZU9CG", "xczu9cg" : IDCODEval_sig <= 32'h0484A093; + "XCZU5EV", "xczu5ev" : IDCODEval_sig <= 32'h04720093; + "XCZU11EG", "xczu11eg" : IDCODEval_sig <= 32'h04740093; + "XCZU15EG", "xczu15eg" : IDCODEval_sig <= 32'h04750093; + "XCZU19EG", "xczu19eg" : IDCODEval_sig <= 32'h04758093; + "XCZU7EV", "xczu7ev" : IDCODEval_sig <= 32'h04730093; + "XCZU2EG", "xczu2eg" : IDCODEval_sig <= 32'h04A43093; + "XCZU4EV", "xczu4ev" : IDCODEval_sig <= 32'h04A47093; + "XCZU6EG", "xczu6eg" : IDCODEval_sig <= 32'h04A4B093; + "XCZU17EG", "xczu17eg" : IDCODEval_sig <= 32'h04A57093; + "XCVU9P", "xcvu9p" : IDCODEval_sig <= 32'h04B31093; + "XCVU11P", "xcvu11p" : IDCODEval_sig <= 32'h04B42093; + "XCVU13P", "xcvu13p" : IDCODEval_sig <= 32'h04B51093; + + + default : begin + + $display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIME2 instance %m is set to %s. The legal values for this attributes are 7A15T, 7A35T, 7A50T, 7A75T, 7A100T, 7A200T, 7K70T, 7K160T, 7K325T, 7K355T, 7K410T, 7K420T, 7K480T, 7V585T, 7S15, 7S100, 7A25T, 7V2000T, 7VH580T, 7VH870T, 7VX330T, 7VX415T, 7VX485T, 7VX550T, 7VX690T, 7VX980T, 7VX1140T, 7Z010, 7Z015, 7Z020, 7Z030, 7Z035, 7Z045, 7Z100, 7Z007S, 7Z012S, 7Z014S, KU025, KU035, KU040, KU060, KU095, KU115, VU065, VU080, VU095, VU125, VU160, VU190, VU440, XCKU3P, XCKU9P, XCKU11P, XCKU13EG, XCKU15P, XCKU5P, XCVU3P, XCZU9EG, XCVU5P, XCVU7P, XCZU3EG, XCZU4EG, XCZU5EG, XCZU7EG, XCZU2CG, XCZU3CG, XCZU4CG, XCZU5CG, XCZU6CG, XCZU7CG, XCZU9CG, XCZU5EV, XCZU11EG, XCZU15EG, XCZU19EG, XCZU7EV, XCZU2EG, XCZU4EV, XCZU6EG, XCZU17EG, XCVU9P, XCVU11P or XCVU13P.", PART_NAME); + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState <= TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState <= RunTestIdle; + jtag_state_name <= "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState <= SelectDRScan; + jtag_state_name <= "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState <= CaptureDR; + jtag_state_name <= "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState <= SelectIRScan; + jtag_state_name <= "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState <= ShiftDR; + jtag_state_name <= "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState <= Exit1DR; + jtag_state_name <= "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + BypassReg <= TDI; + + if(TMS == 1) begin + CurrentState <= Exit1DR; + jtag_state_name <= "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState <= PauseDR; + jtag_state_name <= "PauseDR"; + end + else if(TMS == 1) begin + CurrentState <= UpdateDR; + jtag_state_name <= "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState <= Exit2DR; + jtag_state_name <= "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState <= ShiftDR; + jtag_state_name <= "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState <= UpdateDR; + jtag_state_name <= "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState <= RunTestIdle; + jtag_state_name <= "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState <= SelectDRScan; + jtag_state_name <= "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState <= CaptureIR; + jtag_state_name <= "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState <= TestLogicReset; + jtag_state_name <= "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState <= ShiftIR; + jtag_state_name <= "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState <= Exit1IR; + jtag_state_name <= "Exit1IR"; + end + end + + ShiftIR: + begin +// ClkIR_sig <= 1; + + if(TMS == 1) begin + CurrentState <= Exit1IR; + jtag_state_name <= "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState <= PauseIR; + jtag_state_name <= "PauseIR"; + end + else if(TMS == 1) begin + CurrentState <= UpdateIR; + jtag_state_name <= "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState <= Exit2IR; + jtag_state_name <= "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState <= ShiftIR; + jtag_state_name <= "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState <= UpdateIR; + jtag_state_name <= "UpdateIR"; + end + end + + UpdateIR: + begin + //-- FP +// ClkIR_sig <= 1; + + if(TMS == 0) begin + CurrentState <= RunTestIdle; + jtag_state_name <= "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState <= SelectDRScan; + jtag_state_name <= "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig <= 1; + + if(TRST == 1 ) begin + Tlrst_sig <= #DELAY_SIG 1; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig <= #DELAY_SIG 1; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + RunTestIdle: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 1; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 1; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 1; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 1; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + ClkIR_sig <= TCK; + end + ShiftIR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 1; + UpdateIR_sig <= #DELAY_SIG 0; + ClkIR_sig <= TCK; + end + UpdateIR: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 1; + end + default: begin + Tlrst_sig <= #DELAY_SIG 0; + Rti_sig <= #DELAY_SIG 0; + CaptureDR_sig <= #DELAY_SIG 0; + ShiftDR_sig <= #DELAY_SIG 0; + UpdateDR_sig <= #DELAY_SIG 0; + ShiftIR_sig <= #DELAY_SIG 0; + UpdateIR_sig <= #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin +// ClkIR_sig = ShiftIR_sig & TCK; + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + glbl.JTAG_RUNTEST_GLBL <= Rti_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + TlrstN_sig <= Tlrst_sig; + end + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]; + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + +// IR_CAPTURE_VAL : begin +// ; +// jtag_instruction_name = "IR_CAPTURE"; +// end + + BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + default : begin + jtag_instruction_name = "UNKNOWN"; + // if UNKNOWN instruction, set all signals to 0 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin +// reg [(IDLength -1) : 0] IDreg; + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)]) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// 213980 NCsim compile error fix + TDO <= TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + +`ifdef XIL_TIMING + + specify +// 213980 NCsim compile error fix +// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + + endspecify + +`endif // `ifdef XIL_TIMING + +endmodule // JTAG_SIME2 + +`endcelldefine + diff --git a/verilog/src/unisims/KEEPER.v b/verilog/src/unisims/KEEPER.v new file mode 100644 index 0000000..ab54581 --- /dev/null +++ b/verilog/src/unisims/KEEPER.v @@ -0,0 +1,58 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Weak Keeper +// /___/ /\ Filename : KEEPER.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +`celldefine + +module KEEPER (O); + + inout O; + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + reg in; + + always @(O) + if (O) + in <= 1; + else + in <= 0; + + buf (pull1, pull0) B1 (O, in); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/LDCE.v b/verilog/src/unisims/LDCE.v new file mode 100644 index 0000000..7c6249c --- /dev/null +++ b/verilog/src/unisims/LDCE.v @@ -0,0 +1,223 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Gate Enable +// /___/ /\ Filename : LDCE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/25/10 - Initial version. +// 11/01/11 - Disable timing check when set reset active (CR633224) +// 12/08/11 - add MSGON and XON attribures (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine +module LDCE #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b0, + parameter [0:0] IS_CLR_INVERTED = 1'b0, + parameter [0:0] IS_G_INVERTED = 1'b0 +)( + output Q, + + input CLR, + input D, + input G, + input GE +); + + wire [0:0] IS_CLR_INVERTED_BIN; + wire [0:0] IS_G_INVERTED_BIN; + + reg Q_out = INIT; + + wire CLR_in; + wire D_in; + wire GE_in; + wire G_in; + + assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED; + assign IS_G_INVERTED_BIN = IS_G_INVERTED; + +`ifdef XIL_TIMING + wire CLR_dly; + wire D_dly; + wire GE_dly; + wire G_dly; + + assign CLR_in = (CLR !== 1'bz) && (CLR_dly ^ IS_CLR_INVERTED_BIN); // rv 0 + assign D_in = D_dly; + assign G_in = G_dly ^ IS_G_INVERTED_BIN; + assign GE_in = (GE === 1'bz) || GE_dly; // rv 1 +`else + assign CLR_in = (CLR !== 1'bz) && (CLR ^ IS_CLR_INVERTED_BIN); // rv 0 + assign D_in = D; + assign G_in = G ^ IS_G_INVERTED_BIN; + assign GE_in = (GE === 1'bz) || GE; // rv 1 +`endif + + assign Q = Q_out; + + reg notifier; + wire notifier1; + reg rst_int, set_int; + wire o_out; + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nrst; + wire in_clk_enable, in_clk_enable_n, in_clk_enable_p; + wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p; + wire rst_clk_enable, rst_clk_enable1; + wire tl_enable, tl_enable_n, tl_enable_p; + wire clk_en_n, clk_en_p; +`endif + + tri0 GSR = glbl.GSR; + +`ifdef XIL_TIMING + not (nrst, CLR_in); + not (ngsr, GSR); + xor (in_out, D_dly, Q); + + and (in_clk_enable, ngsr, nrst, GE_in); + and (ce_clk_enable, ngsr, nrst, in_out); + and (rst_clk_enable, ngsr, GE_in); + and (tl_enable, ngsr, nrst); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN; + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN; + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN; + assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable; + assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN; + assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN; + assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN; + assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN; +`else + assign notifier1 = 1'bx; +`endif + + always @(GSR or CLR_in) begin + if (GSR) begin + if (INIT) begin + rst_int = 1'b0; + set_int = 1'b1; + end + else begin + rst_int = 1'b1; + set_int = 1'b0; + end + end + else begin + rst_int = CLR_in; + set_int = 1'b0; + end + end + + latchsre_ldce (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1); + + always @(o_out) + Q_out = o_out; + + + specify + (D => Q) = (100:100:100, 100:100:100); + (G => Q) = (100:100:100, 100:100:100); + (GE => Q) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + (CLR => Q) = (0:0:0, 0:0:0); + (negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); + (posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); + $period (negedge G, 0:0:0, notifier); + $period (posedge G, 0:0:0, notifier); + $recrem (negedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly); + $recrem (negedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly); + $recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly); + $recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly); + $recrem (posedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly); + $recrem (posedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly); + $setuphold (negedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly); + $setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly); + $setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly); + $setuphold (negedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly); + $setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly); + $setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly); + $setuphold (posedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly); + $setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly); + $setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly); + $setuphold (posedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly); + $setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly); + $setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly); + $width (negedge CLR, 0:0:0, 0, notifier); + $width (negedge G, 0:0:0, 0, notifier); + $width (posedge CLR, 0:0:0, 0, notifier); + $width (posedge G, 0:0:0, 0, notifier); + $width (posedge GE, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + + +endmodule + +`endcelldefine + + +primitive latchsre_ldce (q, clk, d, set, rst, ge, notifier); + + output q; reg q; + input clk, d, set, rst, ge, notifier; + + table + + // clk d set rst ge notifier q q+; + + 1 0 0 0 1 ? : ? : 0; + 1 1 0 0 1 ? : ? : 1; + + 0 ? 0 0 ? ? : ? : -; + ? ? 0 0 0 ? : ? : -; + ? 0 0 ? ? ? : 0 : -; + ? 1 ? 0 ? ? : 1 : -; + + ? ? 1 0 ? ? : ? : 1; + ? ? ? 1 ? ? : ? : 0; + 0 ? 0 x ? ? : 0 : 0; + ? ? 0 x 0 ? : 0 : 0; + 1 0 0 x 1 ? : ? : 0; + 0 ? x 0 ? ? : 1 : 1; + ? ? x 0 0 ? : 1 : 1; + 1 1 x 0 1 ? : ? : 1; + ? ? ? ? ? * : ? : x; + + endtable + +endprimitive diff --git a/verilog/src/unisims/LDPE.v b/verilog/src/unisims/LDPE.v new file mode 100644 index 0000000..210be58 --- /dev/null +++ b/verilog/src/unisims/LDPE.v @@ -0,0 +1,219 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Transparent Data Latch with Asynchronous Preset and Gate Enable +// /___/ /\ Filename : LDPE.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 08/25/10 - Initial version. +// 11/01/11 - Disable timing check when set reset active (CR633224) +// 12/08/11 - add MSGON and XON attribures (CR636891) +// 01/16/12 - 640813 - add MSGON and XON functionality +// 04/16/13 - PR683925 - add invertible pin support. +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine +module LDPE #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + parameter MSGON = "TRUE", + parameter XON = "TRUE", + `endif + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_G_INVERTED = 1'b0, + parameter [0:0] IS_PRE_INVERTED = 1'b0 +)( + output Q, + + input D, + input G, + input GE, + input PRE +); + + wire [0:0] IS_G_INVERTED_BIN; + wire [0:0] IS_PRE_INVERTED_BIN; + + reg Q_out = INIT; + + wire D_in; + wire GE_in; + wire G_in; + wire PRE_in; + + assign IS_G_INVERTED_BIN = IS_G_INVERTED; + assign IS_PRE_INVERTED_BIN = IS_PRE_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire GE_dly; + wire G_dly; + wire PRE_dly; + + assign D_in = D_dly; + assign G_in = G_dly ^ IS_G_INVERTED_BIN; + assign GE_in = (GE === 1'bz) || GE_dly; // rv 1 + assign PRE_in = (PRE !== 1'bz) && (PRE_dly ^ IS_PRE_INVERTED_BIN); // rv 0 +`else + assign D_in = D; + assign G_in = G ^ IS_G_INVERTED_BIN; + assign GE_in = (GE === 1'bz) || GE; // rv 1 + assign PRE_in = (PRE !== 1'bz) && (PRE ^ IS_PRE_INVERTED_BIN); // rv 0 +`endif + + assign Q = Q_out; + + reg notifier; + wire notifier1; + reg rst_int, set_int; + wire o_out; + +`ifdef XIL_TIMING + wire ngsr, in_out; + wire nset; + wire in_clk_enable, in_clk_enable_n, in_clk_enable_p; + wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p; + wire rst_clk_enable, rst_clk_enable1; + wire tl_enable, tl_enable_n, tl_enable_p; + wire clk_en_n, clk_en_p; +`endif + + tri0 GSR = glbl.GSR; + +`ifdef XIL_TIMING + not (nset, PRE_in); + not (ngsr, GSR); + xor (in_out, D_dly, Q); + + and (in_clk_enable, ngsr, nset, GE_in); + and (ce_clk_enable, ngsr, nset, in_out); + and (rst_clk_enable, ngsr, GE_in); + and (tl_enable, ngsr, nset); + + assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; + assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN; + assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN; + assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN; + assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN; + assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable; + assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN; + assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN; + assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN; + assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN; +`else + assign notifier1 = 1'bx; +`endif + + always @(GSR or PRE_in) begin + if (GSR) begin + if (INIT) begin + rst_int = 1'b0; + set_int = 1'b1; + end + else begin + rst_int = 1'b1; + set_int = 1'b0; + end + end + else begin + rst_int = 1'b0; + set_int = PRE_in; + end + end + + latchsre_ldpe (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1); + + always @(o_out) + Q_out = o_out; + + + specify + (D => Q) = (100:100:100, 100:100:100); + (G => Q) = (100:100:100, 100:100:100); + (GE => Q) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + (PRE => Q) = (0:0:0, 0:0:0); + (negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); + (posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); + $period (negedge G, 0:0:0, notifier); + $period (posedge G, 0:0:0, notifier); + $recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly); + $recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly); + $recrem (negedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly); + $recrem (negedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly); + $recrem (posedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly); + $recrem (posedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly); + $setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly); + $setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly); + $setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly); + $setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly); + $setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly); + $setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly); + $setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly); + $setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly); + $width (negedge G, 0:0:0, 0, notifier); + $width (negedge PRE, 0:0:0, 0, notifier); + $width (posedge G, 0:0:0, 0, notifier); + $width (posedge GE, 0:0:0, 0, notifier); + $width (posedge PRE, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + + +endmodule + +`endcelldefine + + +primitive latchsre_ldpe (q, clk, d, set, rst, ge, notifier); + + output q; reg q; + input clk, d, set, rst, ge, notifier; + + table + + // clk d set rst ge notifier q q+; + + 1 0 0 0 1 ? : ? : 0; + 1 1 0 0 1 ? : ? : 1; + + 0 ? 0 0 ? ? : ? : -; + ? ? 0 0 0 ? : ? : -; + ? 0 0 ? ? ? : 0 : -; + ? 1 ? 0 ? ? : 1 : -; + + ? ? 1 0 ? ? : ? : 1; + ? ? ? 1 ? ? : ? : 0; + 0 ? 0 x ? ? : 0 : 0; + ? ? 0 x 0 ? : 0 : 0; + 1 0 0 x 1 ? : ? : 0; + 0 ? x 0 ? ? : 1 : 1; + ? ? x 0 0 ? : 1 : 1; + 1 1 x 0 1 ? : ? : 1; + ? ? ? ? ? * : ? : x; + + endtable + +endprimitive diff --git a/verilog/src/unisims/LUT1.v b/verilog/src/unisims/LUT1.v new file mode 100644 index 0000000..146d362 --- /dev/null +++ b/verilog/src/unisims/LUT1.v @@ -0,0 +1,93 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 1-Bit Look-Up Table +// /___/ /\ Filename : LUT1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/12/11 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT1 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [1:0] INIT = 2'h0 +)( + output O, + + input I0 +); + +// define constants + localparam MODULE_NAME = "LUT1"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT1_dr.v" +`else + reg [1:0] INIT_REG = INIT; +`endif + + x_lut1_mux2 (O, INIT_REG[1], INIT_REG[0], I0); + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine + +primitive x_lut1_mux2 (o, d1, d0, s0); + + output o; + input d1, d0; + input s0; + + table + + // d1 d0 s0 : o; + + ? 1 0 : 1; + ? 0 0 : 0; + 1 ? 1 : 1; + 0 ? 1 : 0; + + 0 0 x : 0; + 1 1 x : 1; + + endtable + +endprimitive diff --git a/verilog/src/unisims/LUT2.v b/verilog/src/unisims/LUT2.v new file mode 100644 index 0000000..35cd904 --- /dev/null +++ b/verilog/src/unisims/LUT2.v @@ -0,0 +1,110 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 2-Bit Look-Up Table +// /___/ /\ Filename : LUT2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC Parameter +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [3:0] INIT = 4'h0 +)( + output O, + + input I0, + input I1 +); + +// define constants + localparam MODULE_NAME = "LUT2"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT2_dr.v" +`else + reg [3:0] INIT_REG = INIT; +`endif + + x_lut2_mux4 (O, INIT_REG[3], INIT_REG[2], INIT_REG[1], INIT_REG[0], I1, I0); + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine + +primitive x_lut2_mux4 (o, d3, d2, d1, d0, s1, s0); + + output o; + input d3, d2, d1, d0; + input s1, s0; + + table + + // d3 d2 d1 d0 s1 s0 : o; + + ? ? ? 1 0 0 : 1; + ? ? ? 0 0 0 : 0; + ? ? 1 ? 0 1 : 1; + ? ? 0 ? 0 1 : 0; + ? 1 ? ? 1 0 : 1; + ? 0 ? ? 1 0 : 0; + 1 ? ? ? 1 1 : 1; + 0 ? ? ? 1 1 : 0; + + ? ? 0 0 0 x : 0; + ? ? 1 1 0 x : 1; + 0 0 ? ? 1 x : 0; + 1 1 ? ? 1 x : 1; + + ? 0 ? 0 x 0 : 0; + ? 1 ? 1 x 0 : 1; + 0 ? 0 ? x 1 : 0; + 1 ? 1 ? x 1 : 1; + + 0 0 0 0 x x : 0; + 1 1 1 1 x x : 1; + + endtable + +endprimitive diff --git a/verilog/src/unisims/LUT3.v b/verilog/src/unisims/LUT3.v new file mode 100644 index 0000000..1a957ec --- /dev/null +++ b/verilog/src/unisims/LUT3.v @@ -0,0 +1,152 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 3-Bit Look-Up Table +// /___/ /\ Filename : LUT3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC Parameter +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [7:0] INIT = 8'h00 +)( + output O, + + input I0, + input I1, + input I2 +); + +// define constants + localparam MODULE_NAME = "LUT3"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT3_dr.v" +`else + reg [7:0] INIT_REG = INIT; +`endif + + x_lut3_mux8 (O, INIT_REG[7], INIT_REG[6], INIT_REG[5], INIT_REG[4], INIT_REG[3], INIT_REG[2], INIT_REG[1], INIT_REG[0], I2, I1, I0); + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine + +primitive x_lut3_mux8 (o, d7, d6, d5, d4, d3, d2, d1, d0, s2, s1, s0); + + output o; + input d7, d6, d5, d4, d3, d2, d1, d0; + input s2, s1, s0; + + table + + // d7 d6 d5 d4 d3 d2 d1 d0 s2 s1 s0 : o; + + ? ? ? ? ? ? ? 1 0 0 0 : 1; + ? ? ? ? ? ? ? 0 0 0 0 : 0; + ? ? ? ? ? ? 1 ? 0 0 1 : 1; + ? ? ? ? ? ? 0 ? 0 0 1 : 0; + ? ? ? ? ? 1 ? ? 0 1 0 : 1; + ? ? ? ? ? 0 ? ? 0 1 0 : 0; + ? ? ? ? 1 ? ? ? 0 1 1 : 1; + ? ? ? ? 0 ? ? ? 0 1 1 : 0; + ? ? ? 1 ? ? ? ? 1 0 0 : 1; + ? ? ? 0 ? ? ? ? 1 0 0 : 0; + ? ? 1 ? ? ? ? ? 1 0 1 : 1; + ? ? 0 ? ? ? ? ? 1 0 1 : 0; + ? 1 ? ? ? ? ? ? 1 1 0 : 1; + ? 0 ? ? ? ? ? ? 1 1 0 : 0; + 1 ? ? ? ? ? ? ? 1 1 1 : 1; + 0 ? ? ? ? ? ? ? 1 1 1 : 0; + + ? ? ? ? ? ? 0 0 0 0 x : 0; + ? ? ? ? ? ? 1 1 0 0 x : 1; + ? ? ? ? 0 0 ? ? 0 1 x : 0; + ? ? ? ? 1 1 ? ? 0 1 x : 1; + ? ? 0 0 ? ? ? ? 1 0 x : 0; + ? ? 1 1 ? ? ? ? 1 0 x : 1; + 0 0 ? ? ? ? ? ? 1 1 x : 0; + 1 1 ? ? ? ? ? ? 1 1 x : 1; + + ? ? ? ? ? 0 ? 0 0 x 0 : 0; + ? ? ? ? ? 1 ? 1 0 x 0 : 1; + ? ? ? ? 0 ? 0 ? 0 x 1 : 0; + ? ? ? ? 1 ? 1 ? 0 x 1 : 1; + ? 0 ? 0 ? ? ? ? 1 x 0 : 0; + ? 1 ? 1 ? ? ? ? 1 x 0 : 1; + 0 ? 0 ? ? ? ? ? 1 x 1 : 0; + 1 ? 1 ? ? ? ? ? 1 x 1 : 1; + + ? ? ? 0 ? ? ? 0 x 0 0 : 0; + ? ? ? 1 ? ? ? 1 x 0 0 : 1; + ? ? 0 ? ? ? 0 ? x 0 1 : 0; + ? ? 1 ? ? ? 1 ? x 0 1 : 1; + ? 0 ? ? ? 0 ? ? x 1 0 : 0; + ? 1 ? ? ? 1 ? ? x 1 0 : 1; + 0 ? ? ? 0 ? ? ? x 1 1 : 0; + 1 ? ? ? 1 ? ? ? x 1 1 : 1; + + ? ? ? ? 0 0 0 0 0 x x : 0; + ? ? ? ? 1 1 1 1 0 x x : 1; + 0 0 0 0 ? ? ? ? 1 x x : 0; + 1 1 1 1 ? ? ? ? 1 x x : 1; + + ? ? 0 0 ? ? 0 0 x 0 x : 0; + ? ? 1 1 ? ? 1 1 x 0 x : 1; + 0 0 ? ? 0 0 ? ? x 1 x : 0; + 1 1 ? ? 1 1 ? ? x 1 x : 1; + + ? 0 ? 0 ? 0 ? 0 x x 0 : 0; + ? 1 ? 1 ? 1 ? 1 x x 0 : 1; + 0 ? 0 ? 0 ? 0 ? x x 1 : 0; + 1 ? 1 ? 1 ? 1 ? x x 1 : 1; + + 0 0 0 0 0 0 0 0 x x x : 0; + 1 1 1 1 1 1 1 1 x x x : 1; + + endtable + +endprimitive diff --git a/verilog/src/unisims/LUT4.v b/verilog/src/unisims/LUT4.v new file mode 100644 index 0000000..9a07766 --- /dev/null +++ b/verilog/src/unisims/LUT4.v @@ -0,0 +1,115 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 4-Bit Look-Up Table +// /___/ /\ Filename : LUT4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace primitive with function; Remove buf. +// 03/11/05 - Add LOC Parameter +// 06/04/07 - Add wire declaration to internal signal. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] INIT = 16'h0000 +)( + output O, + + input I0, + input I1, + input I2, + input I3 +); + +// define constants + localparam MODULE_NAME = "LUT4"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT4_dr.v" +`else + reg [15:0] INIT_REG = INIT; +`endif + +// begin behavioral model + + reg O_out; + + assign O = O_out; + + function lut_mux4_f; + input [3:0] d; + input [1:0] s; + begin + if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) + lut_mux4_f = d[s]; + else if ( ~(|d) || &d) + lut_mux4_f = d[0]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}])) + lut_mux4_f = d[{1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}])) + lut_mux4_f = d[{s[1],1'b0}]; + else + lut_mux4_f = 1'bx; + end + endfunction + + always @(I0 or I1 or I2 or I3) begin + if ( (I0 ^ I1 ^ I2 ^ I3) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3) === 1'b1) + O_out = INIT_REG[{I3, I2, I1, I0}]; + else if ( ~(|INIT_REG) || &INIT_REG ) + O_out = INIT_REG[0]; + else + O_out = lut_mux4_f ({lut_mux4_f (INIT_REG[15:12], {I1, I0}), + lut_mux4_f ( INIT_REG[11:8], {I1, I0}), + lut_mux4_f ( INIT_REG[7:4], {I1, I0}), + lut_mux4_f ( INIT_REG[3:0], {I1, I0})}, {I3, I2}); + end + +// end behavioral model + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + (I3 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/LUT5.v b/verilog/src/unisims/LUT5.v new file mode 100644 index 0000000..4620a45 --- /dev/null +++ b/verilog/src/unisims/LUT5.v @@ -0,0 +1,154 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 5-Bit Look-Up Table +// /___/ /\ Filename : LUT5.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace primitive with function; Remove buf. +// 01/07/06 - 222733 - Add LOC Parameter +// 06/04/07 - Add wire declaration to internal signal. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT5 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [31:0] INIT = 32'h00000000 +)( + output O, + + input I0, + input I1, + input I2, + input I3, + input I4 +); + +// define constants + localparam MODULE_NAME = "LUT5"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT5_dr.v" +`else + reg [31:0] INIT_REG = INIT; +`endif + +// begin behavioral model + + reg O_out; + + assign O = O_out; + + function lut_mux4_f; + input [3:0] d; + input [1:0] s; + begin + if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) + lut_mux4_f = d[s]; + else if ( ~(|d) || &d) + lut_mux4_f = d[0]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}])) + lut_mux4_f = d[{1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}])) + lut_mux4_f = d[{s[1],1'b0}]; + else + lut_mux4_f = 1'bx; + end + endfunction + + function lut_mux8_f; + input [7:0] d; + input [2:0] s; + begin + if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0)) + lut_mux8_f = d[s]; + else if ( ~(|d) || &d) + lut_mux8_f = d[0]; + else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) && + (d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}])) + lut_mux8_f = d[{1'b0,s[1:0]}]; + else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) && + (d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}])) + lut_mux8_f = d[{s[2],1'b0,s[0]}]; + else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) && + (d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}])) + lut_mux8_f = d[{s[2:1],1'b0}]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}])) + lut_mux8_f = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && + (d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}])) + lut_mux8_f = d[{1'b0,s[1],1'b0}]; + else if (((s[2] === 1'b1) || (s[2] === 1'b0)) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}])) + lut_mux8_f = d[{s[2],1'b0,1'b0}]; + else + lut_mux8_f = 1'bx; + end + endfunction + + always @(I0 or I1 or I2 or I3 or I4) begin + if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b1) + O_out = INIT_REG[{I4, I3, I2, I1, I0}]; + else if ( ~(|INIT_REG) || &INIT_REG ) + O_out = INIT_REG[0]; + else + O_out = lut_mux4_f ({lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), + lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I4, I3}); + end + +// end behavioral model + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + (I3 => O) = (0:0:0, 0:0:0); + (I4 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/LUT6.v b/verilog/src/unisims/LUT6.v new file mode 100644 index 0000000..2be3fa2 --- /dev/null +++ b/verilog/src/unisims/LUT6.v @@ -0,0 +1,143 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 6-Bit Look-Up Table +// /___/ /\ Filename : LUT6.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace primitive with function; Remove buf. +// 01/07/06 - 222733 - Add LOC Parameter +// 06/04/07 - Add wire declaration to internal signal. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT6 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000 +)( + output O, + + input I0, + input I1, + input I2, + input I3, + input I4, + input I5 +); + +// define constants + localparam MODULE_NAME = "LUT6"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT6_dr.v" +`else + reg [63:0] INIT_REG = INIT; +`endif + +// begin behavioral model + + reg O_out; + + assign O = O_out; + + function lut_mux8_f; + input [7:0] d; + input [2:0] s; + begin + if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0)) + lut_mux8_f = d[s]; + else if ( ~(|d) || &d) + lut_mux8_f = d[0]; + else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) && + (d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}])) + lut_mux8_f = d[{1'b0,s[1:0]}]; + else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) && + (d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}])) + lut_mux8_f = d[{s[2],1'b0,s[0]}]; + else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) && + (d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}])) + lut_mux8_f = d[{s[2:1],1'b0}]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}])) + lut_mux8_f = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && + (d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}])) + lut_mux8_f = d[{1'b0,s[1],1'b0}]; + else if (((s[2] === 1'b1) || (s[2] === 1'b0)) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}])) + lut_mux8_f = d[{s[2],1'b0,1'b0}]; + else + lut_mux8_f = 1'bx; + end + endfunction + + always @(I0 or I1 or I2 or I3 or I4 or I5) begin + if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1) + O_out = INIT_REG[{I5, I4, I3, I2, I1, I0}]; + else if ( ~(|INIT_REG) || &INIT_REG ) + O_out = INIT_REG[0]; + else + O_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}), + lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}), + lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}), + lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}), + lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), + lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3}); + end + +// end behavioral model + +`ifdef XIL_TIMING + specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + (I3 => O) = (0:0:0, 0:0:0); + (I4 => O) = (0:0:0, 0:0:0); + (I5 => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/LUT6_2.v b/verilog/src/unisims/LUT6_2.v new file mode 100644 index 0000000..77349a4 --- /dev/null +++ b/verilog/src/unisims/LUT6_2.v @@ -0,0 +1,180 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 6-Bit Look-Up Table with Two Outputs +// /___/ /\ Filename : LUT6_2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 08/08/06 - Initial version. +// 06/04/07 - Change timescale form 100ps/10ps to 1ps/1ps. +// Add wire definition. +// 06/19/07 - 441956 - Add LOC Parameter +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 09/12/16 - ANSI ports, speed improvements +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module LUT6_2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000 +)( + output O5, + output O6, + + input I0, + input I1, + input I2, + input I3, + input I4, + input I5 +); + +// define constants + localparam MODULE_NAME = "LUT6_2"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "LUT6_2_dr.v" +`else + reg [63:0] INIT_REG = INIT; +`endif + +// begin behavioral model + + reg O5_out; + reg O6_out; + + assign O5 = O5_out; + assign O6 = O6_out; + + function lut_mux4_f; + input [3:0] d; + input [1:0] s; + begin + if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) + lut_mux4_f = d[s]; + else if ( ~(|d) || &d) + lut_mux4_f = d[0]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}])) + lut_mux4_f = d[{1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}])) + lut_mux4_f = d[{s[1],1'b0}]; + else + lut_mux4_f = 1'bx; + end + endfunction + + function lut_mux8_f; + input [7:0] d; + input [2:0] s; + begin + if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0)) + lut_mux8_f = d[s]; + else if ( ~(|d) || &d) + lut_mux8_f = d[0]; + else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) && + (d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}])) + lut_mux8_f = d[{1'b0,s[1:0]}]; + else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) && + (d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}])) + lut_mux8_f = d[{s[2],1'b0,s[0]}]; + else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) && + (d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}])) + lut_mux8_f = d[{s[2:1],1'b0}]; + else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) && + (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}])) + lut_mux8_f = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && + (d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) && + (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}])) + lut_mux8_f = d[{1'b0,s[1],1'b0}]; + else if (((s[2] === 1'b1) || (s[2] === 1'b0)) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) && + (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}])) + lut_mux8_f = d[{s[2],1'b0,1'b0}]; + else + lut_mux8_f = 1'bx; + end + endfunction + + always @(I0 or I1 or I2 or I3 or I4) begin + if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b1) + O5_out = INIT_REG[{I4, I3, I2, I1, I0}]; + else if ( ~(|INIT_REG[31:0]) || &INIT_REG[31:0] ) + O5_out = INIT_REG[0]; + else + O5_out = lut_mux4_f ({lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), + lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I4, I3}); + end + + always @(I0 or I1 or I2 or I3 or I4 or I5) begin + if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1) + O6_out = INIT_REG[{I5, I4, I3, I2, I1, I0}]; + else if ( ~(|INIT_REG) || &INIT_REG ) + O6_out = INIT_REG[0]; + else + O6_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}), + lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}), + lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}), + lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}), + lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), + lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), + lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3}); + end + +// end behavioral model + +`ifdef XIL_TIMING + specify + (I0 => O5) = (0:0:0, 0:0:0); + (I1 => O5) = (0:0:0, 0:0:0); + (I2 => O5) = (0:0:0, 0:0:0); + (I3 => O5) = (0:0:0, 0:0:0); + (I4 => O5) = (0:0:0, 0:0:0); + (I0 => O6) = (0:0:0, 0:0:0); + (I1 => O6) = (0:0:0, 0:0:0); + (I2 => O6) = (0:0:0, 0:0:0); + (I3 => O6) = (0:0:0, 0:0:0); + (I4 => O6) = (0:0:0, 0:0:0); + (I5 => O6) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MASTER_JTAG.v b/verilog/src/unisims/MASTER_JTAG.v new file mode 100644 index 0000000..0a4475d --- /dev/null +++ b/verilog/src/unisims/MASTER_JTAG.v @@ -0,0 +1,52 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2013.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : MASTER_JTAG.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 06/17/13 - Initial version. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine +module MASTER_JTAG + `ifdef XIL_TIMING //Simprim adding LOC only +#( + parameter LOC = "UNPLACED" +) + `endif +( + output TDO, + + input TCK, + input TDI, + input TMS +); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME2_ADV.v b/verilog/src/unisims/MMCME2_ADV.v new file mode 100644 index 0000000..7b08f56 --- /dev/null +++ b/verilog/src/unisims/MMCME2_ADV.v @@ -0,0 +1,4517 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME2_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/07/08 - Initial version. +// 09/19/08 - Change CLKFBOUT_MULT to CLKFBOUT_MULT_F +// CLKOUT0_DIVIDE to CLKOUT0_DIVIDE_F +// 10/03/08 - Initial all signals. +// 10/30/08 - Clock source switching without reset (CR492263). +// 11/18/08 - Add timing check for DADDR[6:5]. +// 12/02/08 - Fix bug of Duty cycle calculation (CR498696) +// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137) +// 12/09/08 - Enable output at CLKFBOUT_MULT_F*8 for fraction mode (CR499322) +// 01/08/09 - Add phase and duty cycle checks for fraction divide (CR501181) +// 01/09/09 - make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137) +// 01/14/09 - Fine phase shift wrap around to 0 after 56 times; +// - PSEN to PSDONE change to 12 PSCLK; RST minpusle to 5ns; +// - add pulldown to PWRDWN pin. (CR503425) +// 01/14/09 - increase clkout_en_time for fraction mode (CR499322) +// 01/21/09 - align CLKFBOUT to CLKIN for fraction mode (CR504602) +// 01/27/09 - update DRP register address (CR505271) +// 01/28/09 - assign clkout_en0 and clkout_en1 to 0 when RST=1 (CR505767) +// 02/03/09 - Fix bug in clkfb fine phase shift. +// - Add delay to clkout_en0_tmp (CR506530). +// 02/05/09 - Add ps_in_ps calculation to clkvco_delay when clkfb_fps_en=1. +// - round clk_ht clk_lt for duty_cycle (CR506531) +// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1601 and 399 to cover the rounded +// error (CR507969) +// 02/25/09 - round clk_ht clk_lt for duty_cycle (509386) +// 02/26/09 - Fix for clkin and clkfbin stop case (CR503425) +// 03/04/09 - Fix for CLOCK_HOLD (CR510820). +// 03/27/09 - set default 1 to CLKINSEL pin (CR516951) +// 04/13/09 - Check vco range when CLKINSEL not connected (CR516951) +// 04/22/09 - Add reset to clkinstopped related signals (CR519102) +// 04/27/09 - Make duty cycle of fraction mode 50/50 (CR519505) +// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120) +// 07/23/09 - fix bug in clk0_dt (CR527643) +// 07/27/09 - Do divide when period_avg > 0 (CR528090) +// - Change DIVCLK_DIVIDE to 80 (CR525904) +// - Add initial lock setting (CR524523) +// - Update RES CP setting (CR524522) +// 07/31/09 - Add if else to handle the fracion and nonfraction for clkout_en. +// 08/10/09 - Calculate clkin_lost_val after lock_period=1 (CR528520). +// 08/15/09 - Update LFHF (CR524522) +// 08/19/09 - Set clkfb_lost_val initial value (CR531354) +// 08/28/09 - add clkin_period_tmp_t to handle period_avg calculation +// when clkin has jitter (CR528520) +// 09/11/09 - Change CLKIN_FREQ_MIN to 10 Mhz (CR532774) +// 10/01/09 - Change CLKIN_FREQ_MAX to 800Mhz (CR535076) +// Add reset check for clock switchover (CR534900) +// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ +// MAX & MIN to parameter (CR535828) +// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662) +// 10/22/09 - Add period_vco_mf for clkvco_delay calculation (CR536951) +// Add cmpvco to compensate period_vco rounded error (CR537073) +// 12/02/09 - not stop clkvco_lk when jitter (CR538717) +// 01/08/10 - Change minimum RST pulse width from 5 ns to 1.5 ns +// Add 1 ns delay to locked_out_tmp when RST=1 (CR543857) +// 01/19/10 - make change to clkvoc_lk_tmp to handle M=1 case (CR544970) +// 02/09/10 - Add global PLL_LOCKG (CR547918) +// 02/23/10 - Not use edge for locked_out_tmp (CR549667) +// 03/04/10 - Change CLKFBOUT_MULT_F range to 5-64 (CR551618) +// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618) +// 03/24/10 - Add SIM_DEVICE attribute +// 04/07/10 - Generate clkvco_ps_tmp2_en correctly when ps_lock_dly rising +// and clkout_ps=1 case; increase lock_period time to 10 (CR556468) +// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966) +// 07/28/10 - Update ref parameter values (CR569260) +// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324) +// 09/03/10 - use %f for M_MIN and M_MAX (CR574247) +// 09/09/10 - Change to bus timing. +// 09/26/10 - Add RST to LOCKED timing path (CR567807) +// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003) +// 03/08/11 - Support fraction mode phase shifting with phase parameter +// setting (CR596402) +// 04/26/11 - Support fraction mode phase shifting with DRP(CR607989) +// 05/24/11 - Set frac_wf_f to 1 when divide=2.125 (CR611840) +// 06/06/11 - set period_vco_half_rm2 to 0 when period_vco=0 (CR613021) +// 06/08/11 - Disable clk0 fraction mode when CLKOUT0_DIVIDE_F in range +// greater than 1 and less than 2. Add DRC check for it (608893) +// 08/03/11 - use clk0_frac instead of clk0_sfrac (CR 618600) +// 10/26/11 - Add DRC check for samples CLKIN period with parameter setting (CR631150) +// Add spectrum attributes. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 02/22/12 - Modify DRC (638094). +// 03/01/12 - fraction enable for m/d (CR 648429) +// 03/07/12 - added vcoflag (CR 638088, CR 636493) +// 04/19/12 - 654951 - rounding issue with clk_out_para_cal +// 05/03/12 - ncsim issue with clkfb_frac_en (CR 655792) +// 05/03/12 - jittery clock (CR 652401) +// 05/03/12 - incorrect period (CR 654951) +// 05/10/12 - fractional divide calculation issue (CR 658151) +// 05/18/12 - fractional divide calculation issue (CR 660657) +// 06/11/12 - update cp and res settings (CR 664278) +// 06/20/12 - modify reset drc (CR 643540) +// 09/06/12 - 655711 - modify displayed MAX on CLK_DUTY_CYCLE +// 12/12/12 - fix clk_osc process for ncsim (CR 676829) +// 04/04/13 - fix clkvco_frac_en for DRP (CR 709093) +// 04/09/13 - Added DRP monitor (CR 695630). +// 05/03/13 - 670208 Fractional clock alignment issue +// 05/31/13 - 720783 - revert clock alignment fix +// 10/22/2014 808642 - Added #1 to $finish +// 11/26/2014 829050 - remove CLKIN -> CLKOUT* timing paths +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME2_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 10.000, + parameter real CLKPFD_FREQ_MAX = 550.000, + parameter real CLKPFD_FREQ_MIN = 10.000, + parameter real VCOCLK_FREQ_MAX = 1600.000, + parameter real VCOCLK_FREQ_MIN = 600.000, +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter CLKFBOUT_USE_FINE_PS = "FALSE", + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKIN2_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter CLKOUT0_USE_FINE_PS = "FALSE", + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUT1_USE_FINE_PS = "FALSE", + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter CLKOUT2_USE_FINE_PS = "FALSE", + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT3_USE_FINE_PS = "FALSE", + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter CLKOUT4_USE_FINE_PS = "FALSE", + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter CLKOUT5_USE_FINE_PS = "FALSE", + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter CLKOUT6_USE_FINE_PS = "FALSE", + parameter COMPENSATION = "ZHOLD", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, + parameter [0:0] IS_PSEN_INVERTED = 1'b0, + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter real REF_JITTER2 = 0.010, + parameter SS_EN = "FALSE", + parameter SS_MODE = "CENTER_HIGH", + parameter integer SS_MOD_PERIOD = 10000, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKFBOUTB, + output CLKFBSTOPPED, + output CLKINSTOPPED, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output [15:0] DO, + output DRDY, + output LOCKED, + output PSDONE, + + input CLKFBIN, + input CLKIN1, + input CLKIN2, + input CLKINSEL, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PSCLK, + input PSEN, + input PSINCDEC, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 10.000; + localparam real CLKPFD_FREQ_MAX = 550.000; + localparam real CLKPFD_FREQ_MIN = 10.000; + localparam real VCOCLK_FREQ_MAX = 1600.000; + localparam real VCOCLK_FREQ_MIN = 600.000; +`endif + +// define constants + localparam MODULE_NAME = "MMCME2_ADV"; + +// Parameter encodings and registers + localparam BANDWIDTH_HIGH = 1; + localparam BANDWIDTH_LOW = 2; + localparam BANDWIDTH_OPTIMIZED = 0; + localparam CLKFBOUT_USE_FINE_PS_FALSE = 1; + localparam CLKFBOUT_USE_FINE_PS_TRUE = 0; + localparam CLKOUT0_USE_FINE_PS_FALSE = 1; + localparam CLKOUT0_USE_FINE_PS_TRUE = 0; + localparam CLKOUT1_USE_FINE_PS_FALSE = 1; + localparam CLKOUT1_USE_FINE_PS_TRUE = 0; + localparam CLKOUT2_USE_FINE_PS_FALSE = 1; + localparam CLKOUT2_USE_FINE_PS_TRUE = 0; + localparam CLKOUT3_USE_FINE_PS_FALSE = 1; + localparam CLKOUT3_USE_FINE_PS_TRUE = 0; + localparam CLKOUT4_CASCADE_FALSE = 0; + localparam CLKOUT4_CASCADE_TRUE = 1; + localparam CLKOUT4_USE_FINE_PS_FALSE = 1; + localparam CLKOUT4_USE_FINE_PS_TRUE = 0; + localparam CLKOUT5_USE_FINE_PS_FALSE = 1; + localparam CLKOUT5_USE_FINE_PS_TRUE = 0; + localparam CLKOUT6_USE_FINE_PS_FALSE = 1; + localparam CLKOUT6_USE_FINE_PS_TRUE = 0; + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_EXTERNAL = 2; + localparam COMPENSATION_INTERNAL = 3; + localparam COMPENSATION_ZHOLD = 0; + localparam SS_EN_FALSE = 0; + localparam SS_EN_TRUE = 1; + localparam SS_MODE_CENTER_HIGH = 0; + localparam SS_MODE_CENTER_LOW = 1; + localparam SS_MODE_DOWN_HIGH = 2; + localparam SS_MODE_DOWN_LOW = 3; + localparam STARTUP_WAIT_FALSE = 1; + localparam STARTUP_WAIT_TRUE = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "MMCME2_ADV_dr.v" +`else + localparam [72:1] BANDWIDTH_REG = BANDWIDTH; + localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F; + localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; + localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS; + localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD; + localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD; + localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; + localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; + localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F; + localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; + localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; + localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS; + localparam [31:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; + localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; + localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; + localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS; + localparam [31:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE; + localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE; + localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE; + localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS; + localparam [31:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE; + localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE; + localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE; + localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS; + localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE; + localparam [31:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE; + localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE; + localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE; + localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS; + localparam [31:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE; + localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE; + localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE; + localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS; + localparam [31:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE; + localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE; + localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE; + localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS; + localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; + localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; + localparam [64:1] COMPENSATION_REG = COMPENSATION; + localparam [31:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; + localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED; + localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED; + localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REF_JITTER1_REG = REF_JITTER1; + localparam real REF_JITTER2_REG = REF_JITTER2; + localparam [40:1] SS_EN_REG = SS_EN; + localparam [88:1] SS_MODE_REG = SS_MODE; + localparam [31:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD; + localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; + localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; + localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; +`endif + +`ifdef XIL_XECLIB + wire [1:0] BANDWIDTH_BIN; + wire [63:0] CLKFBOUT_MULT_F_BIN; + wire [63:0] CLKFBOUT_PHASE_BIN; + wire CLKFBOUT_USE_FINE_PS_BIN; + wire [63:0] CLKIN1_PERIOD_BIN; + wire [63:0] CLKIN2_PERIOD_BIN; + wire [63:0] CLKIN_FREQ_MAX_BIN; + wire [63:0] CLKIN_FREQ_MIN_BIN; + wire [63:0] CLKOUT0_DIVIDE_F_BIN; + wire [63:0] CLKOUT0_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT0_PHASE_BIN; + wire CLKOUT0_USE_FINE_PS_BIN; + wire [7:0] CLKOUT1_DIVIDE_BIN; + wire [63:0] CLKOUT1_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT1_PHASE_BIN; + wire CLKOUT1_USE_FINE_PS_BIN; + wire [7:0] CLKOUT2_DIVIDE_BIN; + wire [63:0] CLKOUT2_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT2_PHASE_BIN; + wire CLKOUT2_USE_FINE_PS_BIN; + wire [7:0] CLKOUT3_DIVIDE_BIN; + wire [63:0] CLKOUT3_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT3_PHASE_BIN; + wire CLKOUT3_USE_FINE_PS_BIN; + wire CLKOUT4_CASCADE_BIN; + wire [7:0] CLKOUT4_DIVIDE_BIN; + wire [63:0] CLKOUT4_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT4_PHASE_BIN; + wire CLKOUT4_USE_FINE_PS_BIN; + wire [7:0] CLKOUT5_DIVIDE_BIN; + wire [63:0] CLKOUT5_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT5_PHASE_BIN; + wire CLKOUT5_USE_FINE_PS_BIN; + wire [7:0] CLKOUT6_DIVIDE_BIN; + wire [63:0] CLKOUT6_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT6_PHASE_BIN; + wire CLKOUT6_USE_FINE_PS_BIN; + wire [63:0] CLKPFD_FREQ_MAX_BIN; + wire [63:0] CLKPFD_FREQ_MIN_BIN; + wire [1:0] COMPENSATION_BIN; + wire [6:0] DIVCLK_DIVIDE_BIN; + wire [63:0] REF_JITTER1_BIN; + wire [63:0] REF_JITTER2_BIN; + wire SS_EN_BIN; + wire [1:0] SS_MODE_BIN; + wire [15:0] SS_MOD_PERIOD_BIN; + wire STARTUP_WAIT_BIN; + wire [63:0] VCOCLK_FREQ_MAX_BIN; + wire [63:0] VCOCLK_FREQ_MIN_BIN; +`else + reg [1:0] BANDWIDTH_BIN; + reg [63:0] CLKFBOUT_MULT_F_BIN; + reg [63:0] CLKFBOUT_PHASE_BIN; + reg CLKFBOUT_USE_FINE_PS_BIN; + reg [63:0] CLKIN1_PERIOD_BIN; + reg [63:0] CLKIN2_PERIOD_BIN; + reg [63:0] CLKIN_FREQ_MAX_BIN; + reg [63:0] CLKIN_FREQ_MIN_BIN; + reg [63:0] CLKOUT0_DIVIDE_F_BIN; + reg [63:0] CLKOUT0_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT0_PHASE_BIN; + reg CLKOUT0_USE_FINE_PS_BIN; + reg [7:0] CLKOUT1_DIVIDE_BIN; + reg [63:0] CLKOUT1_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT1_PHASE_BIN; + reg CLKOUT1_USE_FINE_PS_BIN; + reg [7:0] CLKOUT2_DIVIDE_BIN; + reg [63:0] CLKOUT2_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT2_PHASE_BIN; + reg CLKOUT2_USE_FINE_PS_BIN; + reg [7:0] CLKOUT3_DIVIDE_BIN; + reg [63:0] CLKOUT3_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT3_PHASE_BIN; + reg CLKOUT3_USE_FINE_PS_BIN; + reg CLKOUT4_CASCADE_BIN; + reg [7:0] CLKOUT4_DIVIDE_BIN; + reg [63:0] CLKOUT4_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT4_PHASE_BIN; + reg CLKOUT4_USE_FINE_PS_BIN; + reg [7:0] CLKOUT5_DIVIDE_BIN; + reg [63:0] CLKOUT5_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT5_PHASE_BIN; + reg CLKOUT5_USE_FINE_PS_BIN; + reg [7:0] CLKOUT6_DIVIDE_BIN; + reg [63:0] CLKOUT6_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT6_PHASE_BIN; + reg CLKOUT6_USE_FINE_PS_BIN; + reg [63:0] CLKPFD_FREQ_MAX_BIN; + reg [63:0] CLKPFD_FREQ_MIN_BIN; + reg [1:0] COMPENSATION_BIN; + reg [6:0] DIVCLK_DIVIDE_BIN; + reg [63:0] REF_JITTER1_BIN; + reg [63:0] REF_JITTER2_BIN; + reg SS_EN_BIN; + reg [1:0] SS_MODE_BIN; + reg [15:0] SS_MOD_PERIOD_BIN; + reg STARTUP_WAIT_BIN; + reg [63:0] VCOCLK_FREQ_MAX_BIN; + reg [63:0] VCOCLK_FREQ_MIN_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg CLKFBOUTB_out; + reg CLKFBOUT_out; + reg CLKFBSTOPPED_out; + reg CLKINSTOPPED_out; + reg CLKOUT0B_out; + reg CLKOUT0_out; + reg CLKOUT1B_out; + reg CLKOUT1_out; + reg CLKOUT2B_out; + reg CLKOUT2_out; + reg CLKOUT3B_out; + reg CLKOUT3_out; + reg CLKOUT4_out; + reg CLKOUT5_out; + reg CLKOUT6_out; + reg DRDY_out; + reg LOCKED_out; + reg PSDONE_out; + reg [15:0] DO_out; + + wire CLKFBIN_in; + wire CLKIN1_in; + wire CLKIN2_in; + wire CLKINSEL_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire PSCLK_in; + wire PSEN_in; + wire PSINCDEC_in; + wire PWRDWN_in; + wire RST_in; + wire [15:0] DI_in; + wire [6:0] DADDR_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire PSCLK_delay; + wire PSEN_delay; + wire PSINCDEC_delay; + wire [15:0] DI_delay; + wire [6:0] DADDR_delay; +`endif + + assign CLKFBOUT = CLKFBOUT_out; + assign CLKFBOUTB = CLKFBOUTB_out; + assign CLKFBSTOPPED = CLKFBSTOPPED_out; + assign CLKINSTOPPED = CLKINSTOPPED_out; + assign CLKOUT0 = CLKOUT0_out; + assign CLKOUT0B = CLKOUT0B_out; + assign CLKOUT1 = CLKOUT1_out; + assign CLKOUT1B = CLKOUT1B_out; + assign CLKOUT2 = CLKOUT2_out; + assign CLKOUT2B = CLKOUT2B_out; + assign CLKOUT3 = CLKOUT3_out; + assign CLKOUT3B = CLKOUT3B_out; + assign CLKOUT4 = CLKOUT4_out; + assign CLKOUT5 = CLKOUT5_out; + assign CLKOUT6 = CLKOUT6_out; + assign DO = DO_out; + assign DRDY = DRDY_out; + assign LOCKED = LOCKED_out; + assign PSDONE = PSDONE_out; + +`ifdef XIL_TIMING + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`else + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`endif + + assign CLKFBIN_in = (CLKFBIN !== 1'bz) && CLKFBIN; // rv 0 + assign CLKIN1_in = (CLKIN1 !== 1'bz) && CLKIN1; // rv 0 + assign CLKIN2_in = (CLKIN2 !== 1'bz) && CLKIN2; // rv 0 + assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_REG); // rv 1 + assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0 + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + assign CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + assign CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + assign CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_TRUE; + + assign CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + assign CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + assign CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + assign CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + assign CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + assign CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + assign CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + assign CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_TRUE; + + assign CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + assign CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + assign CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + assign CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_TRUE; + + assign CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + assign CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + assign CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + assign CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_TRUE; + + assign CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + assign CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + assign CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + assign CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_TRUE; + + assign CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + assign CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + assign CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + assign CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + assign CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_TRUE; + + assign CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + assign CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + assign CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + assign CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_TRUE; + + assign CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + assign CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + assign CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + assign CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_TRUE; + + assign CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + assign CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + COMPENSATION_ZHOLD; + + assign DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + assign REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + assign REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + assign SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + assign SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + assign SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + assign STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_TRUE; + + assign VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + assign VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_TRUE; + + CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_TRUE; + + CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_TRUE; + + CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_TRUE; + + CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_TRUE; + + CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_TRUE; + + CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_TRUE; + + CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_TRUE; + + CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + COMPENSATION_BIN = + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + COMPENSATION_ZHOLD; + + DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_TRUE; + + VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BANDWIDTH_REG != "OPTIMIZED") && + (BANDWIDTH_REG != "HIGH") && + (BANDWIDTH_REG != "LOW"))) begin + $display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > 64.000)) begin + $display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to 64.000. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKFBOUT_USE_FINE_PS_REG != "TRUE") && + (CLKFBOUT_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin + $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin + $display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT0_USE_FINE_PS_REG != "TRUE") && + (CLKOUT0_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_USE_FINE_PS_REG != "TRUE") && + (CLKOUT1_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_USE_FINE_PS_REG != "TRUE") && + (CLKOUT2_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_USE_FINE_PS_REG != "TRUE") && + (CLKOUT3_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_CASCADE_REG != "FALSE") && + (CLKOUT4_CASCADE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_USE_FINE_PS_REG != "TRUE") && + (CLKOUT4_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_USE_FINE_PS_REG != "TRUE") && + (CLKOUT5_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_USE_FINE_PS_REG != "TRUE") && + (CLKOUT6_USE_FINE_PS_REG != "FALSE"))) begin + $display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin + $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((COMPENSATION_REG != "ZHOLD") && + (COMPENSATION_REG != "BUF_IN") && + (COMPENSATION_REG != "EXTERNAL") && + (COMPENSATION_REG != "INTERNAL"))) begin + $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL or INTERNAL. Instance: %m", MODULE_NAME, COMPENSATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin + $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin + $display("Error: [Unisim %s-147] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin + $display("Error: [Unisim %s-148] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_EN_REG != "FALSE") && + (SS_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-149] SS_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SS_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MODE_REG != "CENTER_HIGH") && + (SS_MODE_REG != "CENTER_LOW") && + (SS_MODE_REG != "DOWN_HIGH") && + (SS_MODE_REG != "DOWN_LOW"))) begin + $display("Error: [Unisim %s-150] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin + $display("Error: [Unisim %s-151] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_WAIT_REG != "TRUE") && + (STARTUP_WAIT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-152] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin + $display("Error: [Unisim %s-153] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MIN_REG < 600.000 || VCOCLK_FREQ_MIN_REG > 600.000)) begin + $display("Error: [Unisim %s-154] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute are 600.000 to 600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + localparam VCOCLK_FREQ_TARGET = 1000; + localparam M_MIN = 2.000; + localparam M_MAX = 64.000; + localparam real VF_MIN = 600.000; + localparam D_MIN = 1; + localparam D_MAX = 106; + localparam O_MIN = 1; + localparam O_MAX = 128; + localparam O_MAX_HT_LT = 64; + localparam REF_CLK_JITTER_MAX = 1000; + localparam REF_CLK_JITTER_SCALE = 0.1; + localparam MAX_FEEDBACK_DELAY = 10.0; + localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; + localparam ps_max = 55; + + reg [160:1] clkout_name; + real CLKOUT0_DIVIDE_F_RND; + real CLKFBOUT_MULT_F_RND; + + tri1 p_up; + wire glock; + + integer pchk_tmp1, pchk_tmp2; + integer clkvco_div_fint; + real clkvco_div_frac; + reg clk0_out; + reg clkfbout_out; + integer clkvco_frac_en; + integer ps_in_init; + reg clk0_fps_en=0, clk1_fps_en=0, clk2_fps_en=0, clk3_fps_en=0; + reg clk4_fps_en=0, clk5_fps_en=0, clk6_fps_en=0, clkfbout_fps_en=0; + reg fps_en=1'b0, fps_clk_en=1'b0; + reg clkinstopped_out1; + reg clkin_hold_f = 0; + reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0; + integer period_avg_stpi = 0, period_avg_stp = 0; + real tmp_stp1, tmp_stp2; + reg pd_stp_p = 0; + reg vco_stp_f = 0; + reg psen_w = 0; + reg clkinstopped_out_dly = 0; + reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp; + reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; + reg rst_clkinstopped_rc = 0; + reg rst_clkinstopped_lk, rst_clkfbstopped_lk; + integer clkin_lost_cnt; + integer clkfbin_lost_cnt; + reg clkinstopped_hold = 0; + integer ps_in_ps, ps_cnt; + integer ps_in_ps_neg, ps_cnt_neg; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drp_lock; + integer drp_lock_lat = 4; + integer drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [160:0] tmp_string; + reg rst_int = 1'b0; + reg pwron_int; + wire rst_in_o; + reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out; + reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; + integer clkout_en_val, clkout_en_t; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + reg clkvco = 1'b0; + reg clkvco_lk_dly_tmp; + reg clkvco_lk_en; + reg clkvco_lk; + reg fbclk_tmp; + reg clkin_osc, clkin_p; + reg clkfbin_osc, clkfbin_p; + reg clkinstopped_vco_f; + time rst_edge, rst_ht; + reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0; + reg clkfbout_tst=1'b0; + real fb_delay_max; + time fb_delay=0, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay; + time dly_tmp1, tmp_ps_val2; + integer dly_tmp_int, tmp_ps_val1; + time clkin_edge, delay_edge; + real period_clkin, clkin_period_tmp; + integer clkin_period_tmp_t; + integer clkin_period [4:0]; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + real period_vco_rl, period_vco_rl_half; + integer period_vco_half_rm1, period_vco_half_rm2; + real cmpvco = 0.0; + real clkvco_pdrm; + integer period_vco_mf; + integer period_vco_tmp; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco_max, period_vco_min; + integer period_vco1, period_vco2, period_vco3, period_vco4; + integer period_vco5, period_vco6, period_vco7; + integer period_vco_target, period_vco_target_half; + integer period_fb=100000, period_avg=100000; + integer clk0_frac_lt, clk0_frac_ht; + real clk0_frac_lt_rl, clk0_frac_ht_rl; + integer clk0_frac_rm; + real clk0_frac_rm_rl; + integer clkfbout_frac_lt, clkfbout_frac_ht; + real clkfbout_frac_lt_rl, clkfbout_frac_ht_rl; + integer clkfbout_frac_rm; + real clkfbout_frac_rm_rl; + integer period_ps, period_ps_old; + reg ps_lock, ps_lock_dly; + real clkvco_freq_init_chk, clkfbout_pm_rl; + real tmp_real; + integer ik0, ik1, ik2, ik3, ik4, ib, i, j; + integer md_product, m_product, m_product2; + integer mf_product, clk0f_product; +// integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk; + integer clkin_lost_val; + integer clkfbin_lost_val; + time pll_locked_delay, clkin_dly_t, clkfbin_dly_t; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock; + integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + wire init_trig, clkpll_r; + reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0; + reg clk4in=1'b0,clk5in=1'b0,clk6in=1'b0; + reg clkpll_tmp1, clkpll; + reg clkfboutin=1'b0; + wire clkfbps_en; + reg chk_ok; + wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en; + wire clk4ps_en, clk5ps_en, clk6ps_en; + reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel; + reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel; + reg [6:0] d_fht, clkfbout_fht, clk0_fht; + reg [6:0] d_flt, clkfbout_flt, clk0_flt; + reg [5:0] clk0_dly_cnt; + reg [5:0] clk1_dly_cnt; + reg [5:0] clk2_dly_cnt; + reg [5:0] clk3_dly_cnt; + reg [5:0] clk4_dly_cnt; + reg [5:0] clk5_dly_cnt; + reg [5:0] clk6_dly_cnt; + real clk0_phase, clk0_duty; + real clk1_phase, clk1_duty; + real clk2_phase, clk2_duty; + real clk3_phase, clk3_duty; + real clk4_phase, clk4_duty; + real clk5_phase, clk5_duty; + real clk6_phase, clk6_duty; + real divclk_phase=0.000, divclk_duty=0.500; + real clkfbout_phase, clkfbout_duty=0.500; +// mem cells + reg [2:0] d_frac, clkfbout_frac, clk0_frac; + reg d_frac_en, clkfbout_frac_en, clk0_frac_en; + reg d_wf_f; + reg clkfbout_wf_f, clk0_wf_f; + reg d_wf_r; + reg clkfbout_wf_r, clk0_wf_r; + reg [2:0] d_mx, clkfbout_mx; + reg [2:0] clk0_mx, clk1_mx, clk2_mx, clk3_mx; + reg [2:0] clk4_mx, clk5_mx, clk6_mx; + reg divclk_e, clkfbin_e; + reg clkfbout_e; + reg clk0_e, clk1_e, clk2_e, clk3_e; + reg clk4_e, clk5_e, clk6_e; + reg divclk_nc, clkfbin_nc; + reg clkfbout_nc; + reg clk0_nc, clk1_nc, clk2_nc, clk3_nc; + reg clk4_nc, clk5_nc, clk6_nc; + reg [5:0] d_dt=0, clkfbout_dt=0; + reg [5:0] clk0_dt=0, clk1_dt=0, clk2_dt=0, clk3_dt=0; + reg [5:0] clk4_dt=0, clk5_dt=0, clk6_dt=0; + reg [2:0] d_pm_f; + reg [2:0] clkfbout_pm_f, clk0_pm_f; + reg [2:0] clkfbout_pm_r, clk0_pm_r; + reg [2:0] d_pm; + reg [2:0] clk1_pm, clk2_pm, clk3_pm; + reg [2:0] clk4_pm, clk5_pm, clk6_pm; + reg divclk_en=1, clkfbout_en=1; + reg clk0_en=1, clk1_en=1, clk2_en=1, clk3_en=1; + reg clk4_en=1, clk5_en=1, clk6_en=1; + reg [5:0] clkfbin_ht; + reg [5:0] clkfbout_ht; + reg [7:0] divclk_ht; + reg [5:0] clk0_ht, clk1_ht, clk2_ht, clk3_ht; + reg [5:0] clk4_ht, clk5_ht, clk6_ht; + reg [5:0] clkfbin_lt; + reg [7:0] divclk_lt; + reg [6:0] clkfbout_lt; + reg [6:0] clk0_lt, clk1_lt, clk2_lt, clk3_lt; + reg [6:0] clk4_lt, clk5_lt, clk6_lt; +// + real clkfbout_f_div=1.0; + real clk0_f_div; + integer d_div, clkfbout_div, clk0_div; + reg [5:0] clkfbout_dly_cnt; + reg [7:0] clkfbout_cnt; + reg [7:0] clk0_cnt; + reg [7:0] clk1_cnt, clk1_div; + reg [7:0] clk2_cnt, clk2_div; + reg [7:0] clk3_cnt, clk3_div; + reg [7:0] clk4_cnt, clk4_div; + reg [7:0] clk5_cnt, clk5_div; + reg [7:0] clk6_cnt, clk6_div; + integer divclk_cnt_max, clkfbout_cnt_max; + integer clk0_cnt_max, clk1_cnt_max, clk2_cnt_max, clk3_cnt_max; + integer clk4_cnt_max, clk5_cnt_max, clk6_cnt_max; + integer divclk_cnt_ht, clkfbout_cnt_ht; + integer clk0_cnt_ht, clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht; + integer clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht; + reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0; + reg divclk_out, divclk_out_tmp; + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + wire clkinsel_tmp; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + reg init_chk; + reg rst_clkinsel_flag = 0; + wire pwrdwn_in1; + reg pwrdwn_in1_h = 0; + reg rst_input_r_h = 0; + reg pchk_clr = 0; + reg psincdec_chg = 0; + reg psincdec_chg_tmp = 0; + wire rst_input; + reg vcoflag = 0; + reg drp_updt = 1'b0; + + real halfperiod_sum = 0.0; + integer halfperiod = 0; + reg clkvco_free = 1'b0; + integer ik10=0, ik11=0; + + //drp monitor + reg den_r1 = 1'b0; + reg den_r2 = 1'b0; + reg dwe_r1 = 1'b0; + reg dwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge DCLK_in) + begin + // pipeline the DEN and DWE + den_r1 <= DEN_in; + dwe_r1 <= DWE_in; + den_r2 <= den_r1; + dwe_r2 <= dwe_r1; + // Check - if DEN or DWE is more than 1 DCLK + if ((den_r1 == 1'b1) && (den_r2 == 1'b1)) + begin + $display("DRC Error : DEN is high for more than 1 DCLK. Instance %m"); + $finish; + end + if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1)) + begin + $display("DRC Error : DWE is high for more than 1 DCLK. Instance %m"); + $finish; + end + //After the 1st DEN pulse, check the DEN and DRDY. + case (sfsm) + FSM_IDLE: + begin + if(DEN_in == 1'b1) + sfsm <= FSM_WAIT; + end + FSM_WAIT: + begin + // After the 1st DEN, 4 cases can happen + // DEN DRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle. + //Add the check for another DPREN pulse + if(DEN_in === 1'b1 && DRDY === 1'b0) + begin + $display("DRC Error : DEN is enabled before DRDY returns. Instance %m"); + $finish; + end + //Add the check for another DWE pulse + if ((DWE_in === 1'b1) && (DEN_in === 1'b0)) + begin + $display("DRC Error : DWE is enabled before DRDY returns. Instance %m"); + $finish; + end + if ((DRDY === 1'b1) && (DEN_in === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + if ((DRDY === 1'b1) && (DEN_in === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + default: + begin + $display("DRC Error : Default state in DRP FSM. Instance %m"); + $finish; + end + endcase + end // always @ (posedge DCLK) + //end drp monitor + +`ifndef XIL_XECLIB + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin + $display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + #1 $finish; + end + + CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0; + CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0; + + if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin + $display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin + $display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + + if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + + clkfbout_f_div = CLKFBOUT_MULT_F_RND; + attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + + clk0_f_div = CLKOUT0_DIVIDE_F_RND; + attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + + clk1_div = CLKOUT1_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + clk2_div = CLKOUT2_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + clk3_div = CLKOUT3_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + clk4_div = CLKOUT4_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + clk5_div = CLKOUT5_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + clk6_div = CLKOUT6_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + divclk_div = DIVCLK_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + + ps_in_init = 0; + ps_in_ps = ps_in_init; + ps_cnt = 0; + + clk0_fps_en = (CLKOUT0_USE_FINE_PS_REG == "TRUE"); + clk1_fps_en = (CLKOUT1_USE_FINE_PS_REG == "TRUE"); + clk2_fps_en = (CLKOUT2_USE_FINE_PS_REG == "TRUE"); + clk3_fps_en = (CLKOUT3_USE_FINE_PS_REG == "TRUE"); + clk4_fps_en = (CLKOUT4_USE_FINE_PS_REG == "TRUE"); + clk5_fps_en = (CLKOUT5_USE_FINE_PS_REG == "TRUE"); + clk6_fps_en = (CLKOUT6_USE_FINE_PS_REG == "TRUE"); + clkfbout_fps_en = (CLKFBOUT_USE_FINE_PS_REG == "TRUE"); + + fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en + || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en; + + if (clk0_frac_en == 1'b1) begin + if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin + $display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + #1 $finish; + end + end + + pll_lfhf = 2'b00; + + if (BANDWIDTH_REG === "LOW") + case (clkfbout_div) + 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 4 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 5 : begin pll_cp = 4'b0010 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b0010 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b0010 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b0010 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b0010 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 13 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 14 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 15 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 16 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 17 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 18 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 19 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 20 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 21 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 22 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 23 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 24 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 25 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 26 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 27 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 28 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 29 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 30 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 31 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 32 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 33 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 34 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 35 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 36 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 37 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 38 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 39 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 40 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 41 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 47 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 48 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 49 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 50 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 51 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 52 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 53 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 54 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 55 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 56 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 57 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 62 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 63 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 64 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + endcase + else if (BANDWIDTH_REG === "HIGH") + case (clkfbout_div) + 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end + 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end + 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end + 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + endcase + else if (BANDWIDTH_REG === "OPTIMIZED") + case (clkfbout_div) + 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end + 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end + 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end + 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + endcase + + case (clkfbout_div) + 1 : begin drp_lock_ref_dly = 5'd6; + drp_lock_fb_dly = 5'd6; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 2 : begin drp_lock_ref_dly = 5'd6; + drp_lock_fb_dly = 5'd6; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 3 : begin drp_lock_ref_dly = 5'd8; + drp_lock_fb_dly = 5'd8; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 4 : begin drp_lock_ref_dly = 5'd11; + drp_lock_fb_dly = 5'd11; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 5 : begin drp_lock_ref_dly = 5'd14; + drp_lock_fb_dly = 5'd14; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 6 : begin drp_lock_ref_dly = 5'd17; + drp_lock_fb_dly = 5'd17; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 7 : begin drp_lock_ref_dly = 5'd19; + drp_lock_fb_dly = 5'd19; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 8 : begin drp_lock_ref_dly = 5'd22; + drp_lock_fb_dly = 5'd22; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 9 : begin drp_lock_ref_dly = 5'd25; + drp_lock_fb_dly = 5'd25; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 10 : begin drp_lock_ref_dly = 5'd28; + drp_lock_fb_dly = 5'd28; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 11 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd900; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 12 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd825; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 13 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd750; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 14 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd700; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 15 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd650; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 16 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd625; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 17 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd575; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 18 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd550; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 19 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd525; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 20 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd500; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 21 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd475; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 22 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd450; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 23 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd425; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 24 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd400; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 25 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd400; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 26 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd375; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 27 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd350; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 28 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd350; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 29 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd325; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 30 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd325; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 31 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 32 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 33 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 34 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 35 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 36 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 37 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 38 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 39 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 40 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 41 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 42 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 43 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 44 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 45 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 46 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 47 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 48 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 49 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 50 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 51 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 52 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 53 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 54 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 55 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 56 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 57 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 58 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 59 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 60 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 61 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 62 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 63 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 64 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + endcase + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX); + tmp_string = "CLKFBOUT_MULT_F"; + chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string); + if(clk0_frac_en == 1'b0) begin + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string); + end + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string); + period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + clk0f_product = CLKOUT0_DIVIDE_F_RND * 8; + pll_lock_time = 12; + lock_period_time = 10; + if (clkfbout_frac_en == 1'b1) begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + clkout_en_val = mf_product - 1; + m_product2 = clkfbout_div / 2; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + m_product2 = clkfbout_div / 2; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + divclk_div = DIVCLK_DIVIDE_REG; + + dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[7] = {2'bx, clk0_pm_f[2:0], clk0_wf_f, + 2'b0, clk5_e, clk5_nc, clk5_dt[5:0]}; + dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {1'bx, clk0_frac[2:0], clk0_frac_en, clk0_wf_r, + 2'b0, clk0_e, clk0_nc, clk0_dt[5:0]}; + dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {6'bx, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]}; + dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[13] = {6'bx, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]}; + dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[15] = {6'bx, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]}; + dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[17] = {6'bx, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]}; + dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]}; + dr_sram[19] = {2'bx, clkfbout_pm_f[2:0], clkfbout_wf_f, + 2'b0, clk6_e, clk6_nc, clk6_dt[5:0]}; + dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]}; + dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en, + clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]}; + dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]}; + dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + dr_sram[116] = {5'bx, 6'b0, 5'b00001}; + end +`endif + + initial begin + clkpll_jitter_unlock = 0; + clkinstopped_vco_f = 0; + rst_clkfbstopped = 0; + rst_clkinstopped = 0; + rst_clkfbstopped_lk = 0; + rst_clkinstopped_lk = 0; + clkfbin_stop_tmp = 0; + clkin_stop_tmp = 0; + clkvco_lk_en = 0; + clkvco_lk_dly_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + divclk_div = DIVCLK_DIVIDE_REG; + ps_lock = 0; + ps_lock_dly = 0; + PSDONE_out = 1'b0; + rst_int = 0; + CLKINSTOPPED_out = 1'b0; + clkinstopped_out1 = 0; + CLKFBSTOPPED_out = 1'b0; + clkfbstopped_out1 = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_period_tmp_t = 0; + period_avg = 100000; + period_fb = 100000; + clkin_lost_val = 2; + clkfbin_lost_val = 2; + fb_delay = 0; + clkvco_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fb_comp_delay = 0; + clkfbout_pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + period_ps = 0; + period_ps_old = 0; + clkfbout_frac_ht = 0; + clkfbout_frac_lt = 0; + clk0_frac_ht = 0; + clk0_frac_lt = 0; + clk0_frac_ht_rl = 0.0; + clk0_frac_lt_rl = 0.0; + clkvco_rm_cnt = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + fbclk_tmp = 0; + clkfbout_tst = 1'b0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + DRDY_out = 1'b0; + LOCKED_out = 1'b0; + DO_out = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clk6_dly_cnt = 6'b0; + clkfbout_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clk6_cnt = 8'b0; + clkfbout_cnt = 8'b0; + divclk_cnt = 8'b0; + CLKOUT0_out = 1'b0; + CLKOUT0B_out = 1'b1; + CLKOUT1_out = 1'b0; + CLKOUT1B_out = 1'b1; + CLKOUT2_out = 1'b0; + CLKOUT2B_out = 1'b1; + CLKOUT3_out = 1'b0; + CLKOUT3B_out = 1'b1; + CLKOUT4_out = 1'b0; + CLKOUT5_out = 1'b0; + CLKOUT6_out = 1'b0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clk6_out = 0; + CLKFBOUT_out = 1'b0; + CLKFBOUTB_out = 1'b1; + divclk_out = 0; + divclk_out_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign #2 clkinsel_tmp = CLKINSEL_in; + + assign glock = (STARTUP_WAIT_BIN == STARTUP_WAIT_FALSE) || LOCKED; + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + + initial begin + init_chk = 0; + #2; + init_chk = 1; + #2; + init_chk = 0; + end + + always @(CLKINSEL_in or posedge init_chk ) begin + #1; + if (init_chk == 0 && $time > 3 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time); + #1 $finish; + end + + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin + if (CLKIN1_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN1_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + + #1 $finish; + end + end + else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin + if (CLKIN2_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN2_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + #1 $finish; + end + end + + period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG; + if (period_clkin == 0) period_clkin = 10; + + if (period_clkin < MAX_FEEDBACK_DELAY) + fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE; + else + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG); + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + end + end + + assign init_trig = 1; + assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in; + + assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0; + assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkpll_r or posedge rst_input) + if (rst_input) + rst_int <= 1; + else + rst_int <= rst_input ; + + assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped || clkpll_jitter_unlock); + +//simprim_rst_h + always @(posedge pwrdwn_in1 or posedge pchk_clr) + if (pwrdwn_in1) + pwrdwn_in1_h <= 1; + else if (pchk_clr) + pwrdwn_in1_h <= 0; + + always @(posedge RST_in or posedge pchk_clr) + if (RST_in) + rst_input_r_h <= 1; + else if (pchk_clr) + rst_input_r_h <= 0; + + + always @(rst_input ) + if (rst_input==1) begin + rst_edge = $time; + pchk_clr = 0; + end + else if (rst_input==0 && rst_edge > 1) begin + rst_ht = $time - rst_edge; + if (rst_ht < 1500) begin + if (rst_input_r_h == 1 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns) . Instance %m ", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0) + $display("Warning: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + end + pchk_clr = 1; + end +//endsimprim_rst_h + + // + // DRP port read and write + // + + always @ (*) begin + DO_out = dr_sram[daddr_lat]; + end + + always @(posedge DCLK_in or posedge glblGSR) + if (glblGSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 0; + drp_updt <= 1'b0; + end + else begin + if (~RST_in && drp_updt) drp_updt <= 1'b0; + if (DEN_in == 1) begin + valid_daddr = addr_is_valid(DADDR_in); + if (drp_lock == 1) begin + $display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); + end + else begin + drp_lock <= 1; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + daddr_lat <= DADDR_in; + end + if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time); + if (DWE_in == 1) begin // write process + if (rst_input == 1) begin + if (valid_daddr) dr_sram[DADDR_in] <= DI_in; + if (valid_daddr || drp_updt) drp_updt <= 1'b1; + if (DADDR_in == 7'd6) + lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in); + else if (DADDR_in == 7'd7) + upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in); + else if (DADDR_in == 7'd8) + lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in); + else if (DADDR_in == 7'd9) begin + upper_frac_drp(clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in); + end else if (DADDR_in == 7'd10) + lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in); + else if (DADDR_in == 7'd11) + upper_drp(clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in); + else if (DADDR_in == 7'd12) + lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in); + else if (DADDR_in == 7'd13) + upper_drp(clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in); + else if (DADDR_in == 7'd14) + lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in); + else if (DADDR_in == 7'd15) + upper_drp(clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in); + else if (DADDR_in == 7'd16) + lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in); + else if (DADDR_in == 7'd17) + upper_drp(clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in); + else if (DADDR_in == 7'd18) + lower_drp(clk6_pm, clk6_en, clk6_ht, clk6_lt, DI_in); + else if (DADDR_in == 7'd19) + upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in); + else if (DADDR_in == 7'd20) + lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in); + else if (DADDR_in == 7'd21) + upper_frac_drp(clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in); + else if (DADDR_in == 7'd22) begin + divclk_e = DI_in[13]; + divclk_nc = DI_in[12]; + divclk_ht = DI_in[11:6]; + divclk_lt = DI_in[5:0]; + end + end + else begin + $display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + end + else begin + drp_lock <= 0; + DRDY_out <= 1; + drp_lock_lat_cnt <= 0; + end + end + if (DRDY == 1) DRDY_out <= 0; + end + + function addr_is_valid; + input [6:0] daddr_in; + begin + addr_is_valid = 1'b1; + for (i=0; i<=6; i=i+1) + if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0; + if ((addr_is_valid) && + ((daddr_in >= 7'd06 && daddr_in <= 7'd22) || + (daddr_in >= 7'd24 && daddr_in <= 7'd26) || + (daddr_in == 7'd40) || + (daddr_in == 7'd78) || + (daddr_in == 7'd79) || + (daddr_in == 7'd116))) addr_is_valid = 1'b1; + else addr_is_valid = 1'b0; + end + endfunction + + // end process drp; + + // + // determine clock period + // + + always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag) + if (rst_int || rst_clkinsel_flag) + begin + clkin_period[0] <= 1000 * period_clkin; + clkin_period[1] <= 1000 * period_clkin; + clkin_period[2] <= 1000 * period_clkin; + clkin_period[3] <= 1000 * period_clkin; + clkin_period[4] <= 1000 * period_clkin; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end else begin + clkin_edge <= $time; + if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && (pll_unlock1 == 0 || unlock_recover == 1)) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + pll_locked_tm <= 0; + pll_locked_tmp1 <= 0; + end + if (( clkin_lock_cnt >= pll_lock_time && pll_unlock == 0) || + (unlock_recover == 1 && clkin_lock_cnt > lock_cnt_max - 2)) + pll_locked_tm <= #1 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(posedge pll_locked_tmp1) + if (CLKINSEL_in === 0) begin + pchk_tmp1 = CLKIN2_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN2_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + else begin + pchk_tmp1 = CLKIN1_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN1_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + + always @(*) + if (rst_int == 0) begin + if (clkfbout_frac_en == 1'b0) begin + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + clkout_en_val = mf_product - 1; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + end + + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + if (clkout_en0_tmp==0 ) + clkout_en0 = 0; + else begin + if (clkfbout_frac_en == 1'b1) begin + if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + else begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in_o ) + if (rst_in_o) + clkout_en = 0; + else + clkout_en = clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_int or glblGSR) + if (rst_int || glblGSR) begin + assign pll_locked_tmp2 = 0; + end + else begin + deassign pll_locked_tmp2; + end + + always @(rst_int) + if (rst_int) begin + assign clkout_en0 = 0; + assign clkout_en1 = 0; + end + else begin + deassign clkout_en0; + deassign clkout_en1; + end + + always @(rst_int or pll_locked_tm or pll_locked_tmp2 or pll_unlock or unlock_recover) begin + if ((rst_int == 1) && (LOCKED !== 1'b0)) + LOCKED_out <= #1000 0; + else if ((pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && ~unlock_recover) === 1'b1) + LOCKED_out <= 1'b1; + else + LOCKED_out <= 1'b0; + end + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4]) begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; + + if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + end + + always @(clkinstopped_out1 or clkin_hold_f or rst_int) + if (rst_int) + clkinstopped_hold = 0; + else begin + if (clkinstopped_out1) + clkinstopped_hold <= 1; + else begin + if (clkin_hold_f) + clkinstopped_hold = 0; + end + end + + always @(posedge clkinstopped_out1) begin + period_avg_stpi <= period_avg; + pd_stp_p <= #1 1; + @(negedge clkvco) + pd_stp_p <= #1 0; + end + + always @(negedge clkvco or posedge rst_int or posedge pd_stp_p) + if (rst_int) begin + period_avg_stp <= 1000; + vco_stp_f <= 0; + end + else if (pd_stp_p) + period_avg_stp <= period_avg_stpi; + else begin + if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin + if (period_vco > 1739) + vco_stp_f <= 1; + else begin + period_avg_stp <= period_avg_stp + 1; + end + end + end + + + always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold + or period_avg_stp or posedge rst_clkinstopped_rc) + if (period_avg > 0 ) begin + md_product = divclk_div * clkfbout_f_div; + m_product = clkfbout_f_div; + m_product2 = clkfbout_f_div / 2; + clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div); + clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint; + if (clkvco_div_frac > 0.000) + clkvco_frac_en = 1; + else + clkvco_frac_en = 0; + period_fb = period_avg * divclk_div; + period_vco_tmp = period_fb / clkfbout_f_div; + period_vco_rl = 1.0 * period_fb / clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp; + period_vco_mf = period_avg * 8; + if (clkinstopped_hold == 1) begin + if (clkin_hold_f) begin + period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl_half = period_vco_rl / 2.0; + end + else begin + period_vco = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + end + end + else + period_vco = period_vco_tmp; + + period_vco_rm = period_fb % clkfbout_div; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + if (period_vco_half_rm < 1) + period_vco_half_rm2 = 0; + else + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbout_f_div; + clkin_dly_t = period_avg * (divclk_div + 1.25); + clkfbin_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + end + + always @ (negedge RST_in) begin + if (drp_updt) begin + clkout_name = "CLKFBOUT"; + mc_to_attr(clkout_name, clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty); + if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc) + $display("Error : [Unisim %s-38] CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time); + clkout_name = "CLKOUT0"; + mc_to_attr(clkout_name, clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty); + if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc) + $display("Error : [Unisim %s-37] CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time); + clkout_name = "CLKOUT1"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty); + clkout_name = "CLKOUT2"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty); + clkout_name = "CLKOUT3"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty); + clkout_name = "CLKOUT4"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty); + clkout_name = "CLKOUT5"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty); + clkout_name = "CLKOUT6"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty); + clkout_name = "DIVCLK"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty); + if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc) + $display("Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + end + end + + always @(clkfbout_f_div) begin + mf_product = clkfbout_f_div * 8; + end + + always @(*) begin + if (clkfbout_frac_en) begin + clkfbout_frac_ht_rl = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_rsel) / 8.0; + clkfbout_frac_lt_rl = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_fsel) / 8.0; + clkfbout_frac_ht = $rtoi(clkfbout_frac_ht_rl); + clkfbout_frac_lt = $rtoi(clkfbout_frac_lt_rl); + end + end + + always @(*) begin + if (clk0_frac_en) begin + clk0_frac_ht_rl = period_vco_rl * clk0_fht + (period_vco_rl * clk0_rsel) / 8.0; + clk0_frac_lt_rl = period_vco_rl * clk0_flt + (period_vco_rl * clk0_fsel) / 8.0; + clk0_frac_ht = $rtoi(clk0_frac_ht_rl); + clk0_frac_lt = $rtoi(clk0_frac_lt_rl); + end + end + + reg ps_wr_to_max = 1'b0; + always @(period_vco or ps_in_ps) + if (fps_en == 1) begin + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && PSINCDEC_in == 0) + period_ps = 0; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + + always @( clkpll_r ) + clkpll_tmp1 <= #(period_avg) clkpll_r; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(posedge clkinstopped_out1 or posedge rst_int) + if ( rst_int) + clkinstopped_vco_f <= 0; + else begin + clkinstopped_vco_f <= 1; + @(negedge clkinstopped_out1 or posedge rst_int ) + if (rst_int) + clkinstopped_vco_f <= 0; + else begin + @(posedge clkpll); + @(posedge clkpll) + clkinstopped_vco_f <= 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + CLKINSTOPPED_out <= 0; + else begin + CLKINSTOPPED_out <= 1; + if (clkin_hold_f == 1) begin + @(posedge LOCKED or posedge rst_int) + CLKINSTOPPED_out <= 0; + end + else begin + if (CLKINSEL_in == 1) + $display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + else + $display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + end + end + + always @(posedge clkfbstopped_out1 or posedge rst_int) + if (rst_int) + CLKFBSTOPPED_out <= 1'b0; + else begin + CLKFBSTOPPED_out <= 1'b1; + @(posedge LOCKED) + CLKFBSTOPPED_out <= 1'b0; + end + + always @(clkout_en_t) + if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) + rst_clkinstopped_tm = 1; + else + rst_clkinstopped_tm = 0; + + always @(negedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + rst_clkinstopped <= 0; + else + if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin + @(posedge rst_clkinstopped_tm) + rst_clkinstopped <= #period_vco4 1; + @(negedge rst_clkinstopped_tm ) begin + rst_clkinstopped <= #period_vco5 0; + rst_clkinstopped_rc <= #period_vco6 1; + rst_clkinstopped_rc <= #period_vco7 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly <= 0; + else begin + clkinstopped_out_dly <= 1; + if (clkin_hold_f == 1) begin + @(negedge rst_clkinstopped_rc or posedge rst_int) + clkinstopped_out_dly <= 0; + end + end + + always @(clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly2 <= 0; + else + clkinstopped_out_dly2 <= clkinstopped_out1; + + always @(negedge rst_clkinstopped or posedge rst_int) + if (rst_int) + rst_clkinstopped_lk <= 0; + else begin + rst_clkinstopped_lk <= 1; + @(posedge LOCKED) + rst_clkinstopped_lk <= 0; + end + + always @(clkinstopped_vco_f or CLKINSTOPPED or clkvco_lk or clkvco_free or rst_int) + if (rst_int) + clkvco_lk = 0; + else begin + if (CLKINSTOPPED == 1 && clkin_stop_f == 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else if (clkinstopped_vco_f == 1 && period_vco_half > 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else + clkvco_lk = clkvco_free; + end + +// free run vco comp + + always @(posedge clkpll) + if (pll_locked_tm == 1 ) begin + clkvco_free = 1'b1; + halfperiod_sum = 0.0; + halfperiod = 0; + if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin + if (mf_product > 1) begin + for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin + clkout_en_t <= ik10; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik10; + end else begin + clkout_en_t <= 1; + end + end else begin + if (m_product > 1) begin + for (ik11=1; ik11 < m_product; ik11=ik11+1) begin + clkout_en_t <= ik11; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik11; + end else begin + clkout_en_t <= 1; + end + end + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + if (clkfbout_f_div < divclk_div) begin + #(period_vco_rl_half - period_avg/2.0); + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl + or lock_period or ps_in_ps ) + if (lock_period == 1) begin + if (clkfbout_frac_en == 1'b1) begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + else begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + dly_tmp1 = fb_delay + fb_comp_delay; + dly_tmp_int = 1; + if (CLKFBOUT_USE_FINE_PS_BIN == CLKFBOUT_USE_FINE_PS_TRUE) begin + if (ps_in_ps < 0) begin + tmp_ps_val1 = -1 * ps_in_ps; + tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; + if (tmp_ps_val2 > dly_tmp1 ) begin + dly_tmp_int = -1; + dly_tmp = tmp_ps_val2 - dly_tmp1; + end + else if (tmp_ps_val2 == dly_tmp1 ) begin + dly_tmp_int = 0; + dly_tmp = 0; + end + else begin + dly_tmp_int = 1; + dly_tmp = dly_tmp1 - tmp_ps_val2; + end + end + else + dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; + end + else + dly_tmp = dly_tmp1; + + if (dly_tmp_int < 0) + clkvco_delay = dly_tmp; + else begin + if (clkfbout_frac_en == 1'b1 && dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + end + + always @(clkfbout_pm_r) + case (clkfbout_pm_r) + 3'b000 : clkfbout_pm_rl = 0.0; + 3'b001 : clkfbout_pm_rl = 0.125; + 3'b010 : clkfbout_pm_rl = 0.25; + 3'b011 : clkfbout_pm_rl = 0.375; + 3'b100 : clkfbout_pm_rl = 0.50; + 3'b101 : clkfbout_pm_rl = 0.625; + 3'b110 : clkfbout_pm_rl = 0.75; + 3'b111 : clkfbout_pm_rl = 0.875; + endcase + + always @(clkvco_lk) + clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; + + always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) + if ( pll_locked_tm && vco_stp_f == 0) begin + if (dly_tmp == 0) + clkvco = clkvco_lk; + else + clkvco = clkvco_lk_dly_tmp; + end + else + clkvco = 0; + + always @(posedge PSCLK_in or posedge rst_int) + if (rst_int) begin + ps_in_ps <= ps_in_init; + ps_cnt <= 0; + psen_w <= 0; + fps_clk_en <= 0; + ps_lock <= 0; + end else if (fps_en == 1) begin + fps_clk_en <= 1; + if (PSEN_in) begin + if (psen_w == 1) + $display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time); + + psen_w <= 1; + if (ps_lock == 1) + $display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time); + else if (PSINCDEC_in == 1) begin + if (ps_cnt < ps_max) + ps_cnt <= ps_cnt + 1; + else + ps_cnt <= 0; + + if (ps_in_ps < ps_max) + ps_in_ps <= ps_in_ps + 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + else if (PSINCDEC_in == 0) begin + ps_cnt_neg = (-1) * ps_cnt; + ps_in_ps_neg = (-1) * ps_in_ps; + if (ps_cnt_neg < ps_max) + ps_cnt <= ps_cnt - 1; + else + ps_cnt <= 0; + + if (ps_in_ps_neg < ps_max) + ps_in_ps <= ps_in_ps - 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + end + else + psen_w <= 0; + + if ( PSDONE == 1'b1) + ps_lock <= 0; + end + + always @(posedge ps_lock) + if (fps_en == 1) begin + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + begin + PSDONE_out = 1'b1; + @(posedge PSCLK_in); + PSDONE_out = 1'b0; + end + end + + always @(rst_clkinstopped) + if (rst_clkinstopped) begin + assign clkfbout_frac_ht = 50; + assign clkfbout_frac_lt = 50; + assign clkfbout_frac_ht_rl = 50.0; + assign clkfbout_frac_lt_rl = 50.0; + end + else begin + deassign clkfbout_frac_ht; + deassign clkfbout_frac_lt; + deassign clkfbout_frac_ht_rl; + deassign clkfbout_frac_lt_rl; + end + + integer clk0_delay, clk1_delay, clk2_delay, clk3_delay, clk4_delay, clk5_delay, clk6_delay, clkfbout_delay; + integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next; + always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps); + always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps); + always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps); + always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps); + always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps); + always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps); + always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps); + always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps); + + always @ (posedge clkvco) begin + if (ps_lock) begin + if ((period_ps - period_ps_old) > period_vco/2) + ps_wr_to_max <= 1'b1; + else + ps_wr_to_max <= 1'b0; + end + period_ps_old = period_ps; + clk0_delay <= clk0_delay_next; + clk1_delay <= clk1_delay_next; + clk2_delay <= clk2_delay_next; + clk3_delay <= clk3_delay_next; + clk4_delay <= clk4_delay_next; + clk5_delay <= clk5_delay_next; + clk6_delay <= clk6_delay_next; + clkfbout_delay <= clkfbout_delay_next; + end + + always @ (clkvco) begin + if (clkout_en && clk0_en) + if (clk0_delay == 0) clk0in = clkvco; + else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin + clk0in <= #(clk0_delay - period_ps) 1'b0; + clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1; + clk0in <= #(clk0_delay) 1'b0; + end else begin + clk0in <= #clk0_delay clkvco; + end + else clk0in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk1_en) + if (clk1_delay == 0) clk1in = clkvco; + else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin + clk1in <= #(clk1_delay - period_ps) 1'b0; + clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1; + clk1in <= #(clk1_delay) 1'b0; + end else begin + clk1in <= #clk1_delay clkvco; + end + else clk1in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk2_en) + if (clk2_delay == 0) clk2in = clkvco; + else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin + clk2in <= #(clk2_delay - period_ps) 1'b0; + clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1; + clk2in <= #(clk2_delay) 1'b0; + end else begin + clk2in <= #clk2_delay clkvco; + end + else clk2in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk3_en) + if (clk3_delay == 0) clk3in = clkvco; + else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin + clk3in <= #(clk3_delay - period_ps) 1'b0; + clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1; + clk3in <= #(clk3_delay) 1'b0; + end else begin + clk3in <= #clk3_delay clkvco; + end + else clk3in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk4_en) + if (CLKOUT4_CASCADE_BIN == CLKOUT4_CASCADE_TRUE) clk4in = clk6_out; + else if (clk4_delay == 0) clk4in = clkvco; + else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin + clk4in <= #(clk4_delay - period_ps) 1'b0; + clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1; + clk4in <= #(clk4_delay) 1'b0; + end else begin + clk4in <= #clk4_delay clkvco; + end + else clk4in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk5_en) + if (clk5_delay == 0) clk5in = clkvco; + else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin + clk5in <= #(clk5_delay - period_ps) 1'b0; + clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1; + clk5in <= #(clk5_delay) 1'b0; + end else begin + clk5in <= #clk5_delay clkvco; + end + else clk5in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk6_en) + if (clk6_delay == 0) clk6in = clkvco; + else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin + clk6in <= #(clk6_delay - period_ps) 1'b0; + clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1; + clk6in <= #(clk6_delay) 1'b0; + end else begin + clk6in <= #clk6_delay clkvco; + end + else clk6in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clkfbout_en) + if (clkfbout_delay == 0) clkfboutin = clkvco; + else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin + clkfboutin <= #(clkfbout_delay - period_ps) 1'b0; + clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1; + clkfboutin <= #(clkfbout_delay) 1'b0; + end else begin + clkfboutin <= #clkfbout_delay clkvco; + end + else clkfboutin = 1'b0; + end + + + assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en; + assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en; + assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en; + assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en; + assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en; + assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en; + assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en; + assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en; + + always @(negedge clk0in or posedge rst_in_o) + if (rst_in_o) + clk0_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk0_dly_cnt < clk0_dt) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in_o) + if (rst_in_o) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clk1_dt && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in_o) + if (rst_in_o) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clk2_dt && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in_o) + if (rst_in_o) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clk3_dt && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in_o) + if (rst_in_o) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clk4_dt && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in_o) + if (rst_in_o) + clk5_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk5_dly_cnt < clk5_dt) + clk5_dly_cnt <= clk5_dly_cnt + 1; + end + + always @(negedge clk6in or posedge rst_in_o) + if (rst_in_o) + clk6_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk6_dly_cnt < clk6_dt) + clk6_dly_cnt <= clk6_dly_cnt + 1; + end + + always @(negedge clkfboutin or posedge rst_in_o) + if (rst_in_o) + clkfbout_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clkfbout_dly_cnt < clkfbout_dt) + clkfbout_dly_cnt <= clkfbout_dly_cnt + 1; + end + + always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o) + if (rst_in_o || ~clkfbps_en) begin + clkfbout_cnt <= 8'b0; + clkfbout_out = 0; + end + else if (clkfbout_nc) clkfbout_out = ~clkfbout_out; + else if (~clkfbout_frac_en) begin + if (clkfbout_cnt < clkfbout_cnt_max) + clkfbout_cnt <= clkfbout_cnt + 1; + else + clkfbout_cnt <= 8'b0; + if (clkfbout_cnt < clkfbout_cnt_ht) + clkfbout_out = 1; + else + clkfbout_out = 0; + end + else if (clkfbout_frac_en && clkfboutin) begin + clkfbout_out = 1; + clkfbout_frac_rm_rl = 0.0; + clkfbout_frac_rm = 0; + for (ib=1; ib < 8; ib=ib+1) begin + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_ht_rl - clkfbout_frac_ht - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_ht + clkfbout_frac_rm) clkfbout_out = 0; + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_lt_rl - clkfbout_frac_lt - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_lt + clkfbout_frac_rm) clkfbout_out = 1; + end + #(clkfbout_frac_ht) clkfbout_out = 0; + #(clkfbout_frac_lt - period_vco1); + end + + always @(posedge clk0in or negedge clk0in or posedge rst_in_o) + if (rst_in_o || ~clk0ps_en) begin + clk0_cnt <= 8'b0; + clk0_out = 0; + end + else if (clk0_nc) clk0_out = ~clk0_out; + else if (~clk0_frac_en) begin + if (clk0_cnt < clk0_cnt_max) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + if (clk0_cnt < clk0_cnt_ht) + clk0_out = 1; + else + clk0_out = 0; + end + else if (clk0_frac_en && clk0in) begin + clk0_out = 1; + clk0_frac_rm_rl = 0.0; + clk0_frac_rm = 0; + for (ik0=1; ik0 < 8; ik0=ik0+1) begin + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_ht_rl - clk0_frac_ht - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_ht + clk0_frac_rm) clk0_out = 0; + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_lt_rl - clk0_frac_lt - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_lt + clk0_frac_rm) clk0_out = 1; + end + #(clk0_frac_ht) clk0_out = 0; + #(clk0_frac_lt - period_vco1); + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in_o) + if (rst_in_o || ~clk1ps_en) begin + clk1_cnt <= 8'b0; + clk1_out = 0; + end + else if (clk1_nc) clk1_out = ~clk1_out; + else begin + if (clk1_cnt < clk1_cnt_max) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + if (clk1_cnt < clk1_cnt_ht) + clk1_out = 1; + else + clk1_out = 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in_o) + if (rst_in_o || ~clk2ps_en) begin + clk2_cnt <= 8'b0; + clk2_out = 0; + end + else if (clk2_nc) clk2_out = ~clk2_out; + else begin + if (clk2_cnt < clk2_cnt_max) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + if (clk2_cnt < clk2_cnt_ht) + clk2_out = 1; + else + clk2_out = 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in_o) + if (rst_in_o || ~clk3ps_en) begin + clk3_cnt <= 8'b0; + clk3_out = 0; + end + else if (clk3_nc) clk3_out = ~clk3_out; + else begin + if (clk3_cnt < clk3_cnt_max) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + if (clk3_cnt < clk3_cnt_ht) + clk3_out = 1; + else + clk3_out = 0; + end + + always @(posedge clk4in or negedge clk4in or posedge rst_in_o) + if (rst_in_o || ~clk4ps_en) begin + clk4_cnt <= 8'b0; + clk4_out = 0; + end + else if (clk4_nc) clk4_out = ~clk4_out; + else begin + if (clk4_cnt < clk4_cnt_max) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + if (clk4_cnt < clk4_cnt_ht) + clk4_out = 1; + else + clk4_out = 0; + end + + always @(posedge clk5in or negedge clk5in or posedge rst_in_o) + if (rst_in_o || ~clk5ps_en) begin + clk5_cnt <= 8'b0; + clk5_out = 0; + end + else if (clk5_nc) clk5_out = ~clk5_out; + else begin + if (clk5_cnt < clk5_cnt_max) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + if (clk5_cnt < clk5_cnt_ht) + clk5_out = 1; + else + clk5_out = 0; + end + + always @(posedge clk6in or negedge clk6in or posedge rst_in_o) + if (rst_in_o || ~clk6ps_en) begin + clk6_cnt <= 8'b0; + clk6_out = 0; + end + else if (clk6_nc) clk6_out = ~clk6_out; + else begin + if (clk6_cnt < clk6_cnt_max) + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 8'b0; + if (clk6_cnt < clk6_cnt_ht) + clk6_out = 1; + else + clk6_out = 0; + end + + + always @(clk0_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT0_out = clk0_out; + CLKOUT0B_out = ~clk0_out; + end else begin + CLKOUT0_out = clkfbout_tst; + CLKOUT0B_out = ~clkfbout_tst; + end + + always @(clk1_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT1_out = clk1_out; + CLKOUT1B_out = ~clk1_out; + end else begin + CLKOUT1_out = clkfbout_tst; + CLKOUT1B_out = ~clkfbout_tst; + end + + always @(clk2_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT2_out = clk2_out; + CLKOUT2B_out = ~clk2_out; + end else begin + CLKOUT2_out = clkfbout_tst; + CLKOUT2B_out = ~clkfbout_tst; + end + + always @(clk3_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT3_out = clk3_out; + CLKOUT3B_out = ~clk3_out; + end else begin + CLKOUT3_out = clkfbout_tst; + CLKOUT3B_out = ~clkfbout_tst; + end + + always @(clk4_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT4_out = clk4_out; + end else begin + CLKOUT4_out = clkfbout_tst; + end + + always @(clk5_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT5_out = clk5_out; + end else begin + CLKOUT5_out = clkfbout_tst; + end + + always @(clk6_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT6_out = clk6_out; + end else begin + CLKOUT6_out = clkfbout_tst; + end + + always @(clkfbout_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) + begin + CLKFBOUT_out = clkfbout_out; + CLKFBOUTB_out = ~clkfbout_out; + end + else + begin + CLKFBOUT_out = clkfbout_tst; + CLKFBOUTB_out = ~clkfbout_tst; + end + + // + // determine feedback delay + // + + + always @(posedge clkpll_r ) + if (fb_delay_found) clkfbout_tst = 1'b0; + else clkfbout_tst = ~clkfbout_tst; + + always @( posedge clkfbout_tst ) + delay_edge = $time; + + always @( posedge rst_int ) + begin + fb_delay <= 0; + fb_delay_found_tmp <= 0; + end + + always @(posedge CLKFBIN_in ) + if (fb_delay_found_tmp == 0 ) begin + if ( delay_edge != 0) begin + fb_delay <= ($time - delay_edge); + fb_delay_found_tmp <= 1; + end else begin + fb_delay <= 0; + fb_delay_found_tmp <= 0; + end + end + + always @(negedge clkfbout_tst or negedge fb_delay_found_tmp) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay or fb_delay_found) + if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); + end + + // + // generate unlock signal + // + + always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc; + always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc; + + always @(posedge clkpll_r or negedge clkpll_r) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge CLKFBIN_in or negedge CLKFBIN_in) begin + clkfbin_p <= 1; + clkfbin_p <= #100 0; + end + + always @(posedge clkin_osc or posedge rst_int or posedge clkin_p) + if (rst_int == 1) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out1 == 1) begin + @(posedge clkpll_r) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out1 <= 0; + end + else + clkinstopped_out1 <= 1; + end + + always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p or posedge pll_unlock) + if (rst_int == 1 || clkfbin_p == 1 || pll_unlock == 1) begin + clkfbstopped_out1 <= 0; + clkfbin_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfbin_lost_cnt < clkfbin_lost_val) begin + clkfbin_lost_cnt <= clkfbin_lost_cnt + 1; + clkfbstopped_out1 <= 0; + end + else + clkfbstopped_out1 <= 1; + end + + + always @(clkin_jit or rst_int ) + if (rst_int) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit != period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit != -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // tasks +task mc_to_attr; + input [160:1] clkout_name; + input [2:0] pm_f; + input wf_f; + input [2:0] frac; + input frac_en; + input wf_r; + input [1:0] mx; + input e; + input nc; + input [5:0] dt; + input [2:0] pm_r; + input en; + input [5:0] ht; + input [5:0] lt; + output real div; + output real phase; + output real duty; + + integer odd_frac; + reg odd; + real frac_r; + integer div_2; + integer pm_f_c; + real duty_step; + real phase_step; + +begin + +if (nc == 1'b1) begin + div = 1.0; + duty = 0.5; +end +else if (frac_en == 1'b1) begin + duty =0.50; + + if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f; + else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r; + else pm_f_c = 8 + pm_f - pm_r; + + if (pm_f_c < 4) begin + odd = 1'b0; + odd_frac = frac; + end + else begin + odd = 1'b1; + odd_frac = frac + 8; + end + + frac_r = frac * 0.125; + + if (odd_frac > 9) div_2 = lt; + else div_2 = lt + 1; + + div = 2.0 * div_2 + 1.0 * odd + frac_r; + +end +else begin + + if (ht == 6'b0 && lt == 6'b0) div = 128.0; + else if (ht == 6'b0) div = 64.0 + lt * 1.0; + else if (lt == 6'b0) div = ht * 1.0 + 64.0; + else div = ht * 1.0 + lt * 1.0; + + duty_step = 0.5 / div; + + duty = (2.0 * ht + e) * duty_step; + +end + + phase_step = 360.0 / (div * 8.0); + phase = phase_step * (dt*8.0 + pm_r*1.0); + +end +endtask + +task upper_mix_drp; + output reg [2:0] pm_f; + output reg wf_f; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + pm_f = DI[13:11]; + wf_f = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_frac_drp; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + frac = DI[14:12]; + frac_en = DI[11]; + wf_r = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_drp; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task lower_drp; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input [15:0] DI; +begin + pm_r = DI[15:13]; + en = DI[12]; + ht = DI[11:6]; + lt = DI[5:0]; +end +endtask + +//ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div) +task ht_calc; + input [2:0] frac; + input frac_en; + input e; + input [5:0] ht; + input [6:0] lt; + input real f_div; + output [3:0] clk_rsel; + output [3:0] clk_fsel; + output [6:0] clk_fht; + output [6:0] clk_flt; + output integer clk_cnt_max; + output integer clk_cnt_ht; + output integer clk_div_fint; + + integer clk_div_fint_odd; +begin + clk_div_fint = $rtoi(f_div); + if (frac_en) begin + clk_fht = clk_div_fint / 2; + clk_flt = clk_div_fint / 2; + clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt; + if (clk_div_fint_odd > 0) begin + clk_rsel = (8 + frac) / 2; + clk_fsel = 8 + frac - clk_rsel; + end + else begin + clk_rsel = frac / 2; + clk_fsel = frac - clk_rsel; + end + end + else begin + if (ht == 6'b0) clk_fht = 64; else clk_fht = ht; + if (lt == 7'b0) clk_flt = 64; else clk_flt = lt; + clk_cnt_max = 2 * (clk_fht + clk_flt) - 1; + clk_cnt_ht = 2 * clk_fht + e; + end + +end +endtask + +task attr_to_mc; + output reg [2:0] pm_f; + output reg wf_f; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input real div; + input real phase; + input real duty; + + integer div_int; + real div_frac; + real div_rnd; + + reg [37:0] vector; +begin + +// determine frac_en + div_int = $rtoi(div); + div_frac = div - $itor(div_int); + if (div_frac > 0.000) frac_en = 1'b1; + else frac_en = 1'b0; + +// rnd frac to nearest 0.125 - may become .000 + div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0; + +// determine int and frac part + div_int = $rtoi(div_rnd); + div_frac = div_rnd - $itor(div_int); + + if (frac_en == 1'b1) + vector = mmcm_frac_calc(div_int,phase*1000,duty*100000,div_frac*1000); + else + vector = mmcm_calc(div_int,phase*1000,duty*100000); + + if (frac_en == 1'b1) begin + pm_f = vector[35:33]; + wf_f = vector[32]; + frac = vector[30:28]; + frac_en = vector[27]; + wf_r = vector[26]; + end + else begin + pm_f = 3'b0; + wf_f = 1'b0; + frac = 3'b0; + frac_en = 1'b0; + wf_r = 1'b0; + end + mx = vector[25:24]; + e = vector[23]; + nc = vector[22]; + dt = vector[21:16]; + pm_r = vector[15:13]; + en = 1'b1; + ht = vector[11:6]; + lt = vector[5:0]; +end +endtask + +`define MMCME2_ADV_FRAC_PRECISION 10 +`define MMCME2_ADV_FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`MMCME2_ADV_FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`MMCME2_ADV_FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`MMCME2_ADV_FIXED_WIDTH:1] precision + ); + + begin + + // If the fractional precision bit is high then round up + if( decimal[(`MMCME2_ADV_FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`MMCME2_ADV_FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`MMCME2_ADV_FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`MMCME2_ADV_FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `MMCME2_ADV_FRAC_PRECISION) / 100_000; + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + // comes from above round_frac + high_time = temp[`MMCME2_ADV_FRAC_PRECISION+7:`MMCME2_ADV_FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`MMCME2_ADV_FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_in_cycles; + reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`MMCME2_ADV_FIXED_WIDTH:1] temp; + + begin + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `MMCME2_ADV_FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `MMCME2_ADV_FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`MMCME2_ADV_FRAC_PRECISION:`MMCME2_ADV_FRAC_PRECISION-2]; + delay_time = temp[`MMCME2_ADV_FRAC_PRECISION+6:`MMCME2_ADV_FRAC_PRECISION+1]; + + // Setup the return value + mmcm_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + mmcm_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); +// $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_divider(divide, duty_cycle); //Not used since edge and no count are 0 when fractional + phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + end +endfunction + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_CHK = 1.0; + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + $display(" Instance %m "); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + integer para_in; + integer range_low; + integer range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; + end + endfunction + + function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + real para_in; + real range_low; + real range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_real_range_chk = 1'b0; + end + endfunction + + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (CLKIN1 => LOCKED) = (100:100:100, 100:100:100); + (CLKIN2 => LOCKED) = (100:100:100, 100:100:100); + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (PSCLK => PSDONE) = (100:100:100, 100:100:100); + (negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKFBOUTB, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKIN2, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT2B, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT3B, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge CLKOUT6, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge PSCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKFBOUTB, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKIN2, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT2B, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT3B, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge CLKOUT6, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge PSCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge CLKIN2, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PSCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge CLKIN2, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PSCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME2_BASE.v b/verilog/src/unisims/MMCME2_BASE.v new file mode 100644 index 0000000..f4ddb41 --- /dev/null +++ b/verilog/src/unisims/MMCME2_BASE.v @@ -0,0 +1,190 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Base Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME2_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 05/27/10 - Initial version +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME2_BASE ( + CLKFBOUT, + CLKFBOUTB, + CLKOUT0, + CLKOUT0B, + CLKOUT1, + CLKOUT1B, + CLKOUT2, + CLKOUT2B, + CLKOUT3, + CLKOUT3B, + CLKOUT4, + CLKOUT5, + CLKOUT6, + LOCKED, + CLKFBIN, + CLKIN1, + PWRDWN, + RST +); + + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif + + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; + +// define constants + localparam MODULE_NAME = "MMCME2_BASE"; + + wire OPEN_DRDY; + wire OPEN_PSDONE; + wire OPEN_FBS; + wire OPEN_INS; + wire [15:0] OPEN_DO; + + MMCME2_ADV #( + .BANDWIDTH(BANDWIDTH), + .CLKFBOUT_MULT_F(CLKFBOUT_MULT_F), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN1_PERIOD), + .CLKIN2_PERIOD(10), + .CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_CASCADE(CLKOUT4_CASCADE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .CLKOUT6_DIVIDE(CLKOUT6_DIVIDE), + .CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE), + .CLKOUT6_PHASE(CLKOUT6_PHASE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .REF_JITTER1(REF_JITTER1), + .STARTUP_WAIT(STARTUP_WAIT) + ) mmcm_adv_1 ( + .CLKFBOUT (CLKFBOUT), + .CLKFBOUTB (CLKFBOUTB), + .CLKFBSTOPPED(OPEN_FBS), + .CLKINSTOPPED(OPEN_INS), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUT2 (CLKOUT2), + .CLKOUT2B (CLKOUT2B), + .CLKOUT3 (CLKOUT3), + .CLKOUT3B (CLKOUT3B), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .CLKOUT6 (CLKOUT6), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .LOCKED (LOCKED), + .PSDONE(OPEN_PSDONE), + .CLKFBIN (CLKFBIN), + .CLKIN1 (CLKIN1), + .CLKIN2 (1'b0), + .CLKINSEL(1'b1), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(PWRDWN), + .RST (RST) + ); +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME3_ADV.v b/verilog/src/unisims/MMCME3_ADV.v new file mode 100644 index 0000000..453f544 --- /dev/null +++ b/verilog/src/unisims/MMCME3_ADV.v @@ -0,0 +1,4415 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME3_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/21/2013 - YML changes +// 03/22/2013 - 708090 - Change error to Warning +// 03/27/2013 - Update with writer notation +// 04/04/2013 - 709484 - Add PFD check +// 04/04/2013 - 709093 - Fix periods after DRP +// 04/12/2013 - invertible pin changes +// 04/22/2013 - 713991 - Fix cddcdone assertion +// 04/24/2013 - 709726 - fix vcoflag +// 05/07/2013 - 714319 - fix phase warning +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME3_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 10.000, + parameter real CLKPFD_FREQ_MAX = 550.000, + parameter real CLKPFD_FREQ_MIN = 10.000, + parameter real VCOCLK_FREQ_MAX = 1600.000, + parameter real VCOCLK_FREQ_MIN = 600.000, +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter CLKFBOUT_USE_FINE_PS = "FALSE", + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKIN2_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter CLKOUT0_USE_FINE_PS = "FALSE", + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUT1_USE_FINE_PS = "FALSE", + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter CLKOUT2_USE_FINE_PS = "FALSE", + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT3_USE_FINE_PS = "FALSE", + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter CLKOUT4_USE_FINE_PS = "FALSE", + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter CLKOUT5_USE_FINE_PS = "FALSE", + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter CLKOUT6_USE_FINE_PS = "FALSE", + parameter COMPENSATION = "AUTO", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0, + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, + parameter [0:0] IS_PSEN_INVERTED = 1'b0, + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter real REF_JITTER2 = 0.010, + parameter SS_EN = "FALSE", + parameter SS_MODE = "CENTER_HIGH", + parameter integer SS_MOD_PERIOD = 10000, + parameter STARTUP_WAIT = "FALSE" +)( + output CDDCDONE, + output CLKFBOUT, + output CLKFBOUTB, + output CLKFBSTOPPED, + output CLKINSTOPPED, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output [15:0] DO, + output DRDY, + output LOCKED, + output PSDONE, + + input CDDCREQ, + input CLKFBIN, + input CLKIN1, + input CLKIN2, + input CLKINSEL, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PSCLK, + input PSEN, + input PSINCDEC, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 10.000; + localparam real CLKPFD_FREQ_MAX = 550.000; + localparam real CLKPFD_FREQ_MIN = 10.000; + localparam real VCOCLK_FREQ_MAX = 1600.000; + localparam real VCOCLK_FREQ_MIN = 600.000; +`endif + +// define constants + localparam MODULE_NAME = "MMCME3_ADV"; + +// Parameter encodings and registers + localparam BANDWIDTH_HIGH = 1; + localparam BANDWIDTH_LOW = 2; + localparam BANDWIDTH_OPTIMIZED = 0; + localparam CLKFBOUT_USE_FINE_PS_FALSE = 0; + localparam CLKFBOUT_USE_FINE_PS_TRUE = 1; + localparam CLKOUT0_USE_FINE_PS_FALSE = 0; + localparam CLKOUT0_USE_FINE_PS_TRUE = 1; + localparam CLKOUT1_USE_FINE_PS_FALSE = 0; + localparam CLKOUT1_USE_FINE_PS_TRUE = 1; + localparam CLKOUT2_USE_FINE_PS_FALSE = 0; + localparam CLKOUT2_USE_FINE_PS_TRUE = 1; + localparam CLKOUT3_USE_FINE_PS_FALSE = 0; + localparam CLKOUT3_USE_FINE_PS_TRUE = 1; + localparam CLKOUT4_CASCADE_FALSE = 0; + localparam CLKOUT4_CASCADE_TRUE = 1; + localparam CLKOUT4_USE_FINE_PS_FALSE = 0; + localparam CLKOUT4_USE_FINE_PS_TRUE = 1; + localparam CLKOUT5_USE_FINE_PS_FALSE = 0; + localparam CLKOUT5_USE_FINE_PS_TRUE = 1; + localparam CLKOUT6_USE_FINE_PS_FALSE = 0; + localparam CLKOUT6_USE_FINE_PS_TRUE = 1; + localparam COMPENSATION_AUTO = 0; + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_EXTERNAL = 2; + localparam COMPENSATION_INTERNAL = 3; + localparam COMPENSATION_ZHOLD = 4; + localparam SS_EN_FALSE = 0; + localparam SS_EN_TRUE = 1; + localparam SS_MODE_CENTER_HIGH = 0; + localparam SS_MODE_CENTER_LOW = 1; + localparam SS_MODE_DOWN_HIGH = 2; + localparam SS_MODE_DOWN_LOW = 3; + localparam STARTUP_WAIT_FALSE = 0; + localparam STARTUP_WAIT_TRUE = 1; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "MMCME3_ADV_dr.v" +`else + localparam [72:1] BANDWIDTH_REG = BANDWIDTH; + localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F; + localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; + localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS; + localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD; + localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD; + localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; + localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; + localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F; + localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; + localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; + localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS; + localparam [31:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; + localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; + localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; + localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS; + localparam [31:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE; + localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE; + localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE; + localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS; + localparam [31:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE; + localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE; + localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE; + localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS; + localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE; + localparam [31:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE; + localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE; + localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE; + localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS; + localparam [31:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE; + localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE; + localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE; + localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS; + localparam [31:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE; + localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE; + localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE; + localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS; + localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; + localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; + localparam [64:1] COMPENSATION_REG = COMPENSATION; + localparam [31:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED; + localparam [0:0] IS_CLKIN2_INVERTED_REG = IS_CLKIN2_INVERTED; + localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED; + localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED; + localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REF_JITTER1_REG = REF_JITTER1; + localparam real REF_JITTER2_REG = REF_JITTER2; + localparam [40:1] SS_EN_REG = SS_EN; + localparam [88:1] SS_MODE_REG = SS_MODE; + localparam [31:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD; + localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; + localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; + localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; +`endif + +`ifdef XIL_XECLIB + wire [1:0] BANDWIDTH_BIN; + wire [63:0] CLKFBOUT_MULT_F_BIN; + wire [63:0] CLKFBOUT_PHASE_BIN; + wire CLKFBOUT_USE_FINE_PS_BIN; + wire [63:0] CLKIN1_PERIOD_BIN; + wire [63:0] CLKIN2_PERIOD_BIN; + wire [63:0] CLKIN_FREQ_MAX_BIN; + wire [63:0] CLKIN_FREQ_MIN_BIN; + wire [63:0] CLKOUT0_DIVIDE_F_BIN; + wire [63:0] CLKOUT0_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT0_PHASE_BIN; + wire CLKOUT0_USE_FINE_PS_BIN; + wire [7:0] CLKOUT1_DIVIDE_BIN; + wire [63:0] CLKOUT1_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT1_PHASE_BIN; + wire CLKOUT1_USE_FINE_PS_BIN; + wire [7:0] CLKOUT2_DIVIDE_BIN; + wire [63:0] CLKOUT2_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT2_PHASE_BIN; + wire CLKOUT2_USE_FINE_PS_BIN; + wire [7:0] CLKOUT3_DIVIDE_BIN; + wire [63:0] CLKOUT3_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT3_PHASE_BIN; + wire CLKOUT3_USE_FINE_PS_BIN; + wire CLKOUT4_CASCADE_BIN; + wire [7:0] CLKOUT4_DIVIDE_BIN; + wire [63:0] CLKOUT4_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT4_PHASE_BIN; + wire CLKOUT4_USE_FINE_PS_BIN; + wire [7:0] CLKOUT5_DIVIDE_BIN; + wire [63:0] CLKOUT5_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT5_PHASE_BIN; + wire CLKOUT5_USE_FINE_PS_BIN; + wire [7:0] CLKOUT6_DIVIDE_BIN; + wire [63:0] CLKOUT6_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT6_PHASE_BIN; + wire CLKOUT6_USE_FINE_PS_BIN; + wire [63:0] CLKPFD_FREQ_MAX_BIN; + wire [63:0] CLKPFD_FREQ_MIN_BIN; + wire [2:0] COMPENSATION_BIN; + wire [6:0] DIVCLK_DIVIDE_BIN; + wire [63:0] REF_JITTER1_BIN; + wire [63:0] REF_JITTER2_BIN; + wire SS_EN_BIN; + wire [1:0] SS_MODE_BIN; + wire [15:0] SS_MOD_PERIOD_BIN; + wire STARTUP_WAIT_BIN; + wire [63:0] VCOCLK_FREQ_MAX_BIN; + wire [63:0] VCOCLK_FREQ_MIN_BIN; +`else + reg [1:0] BANDWIDTH_BIN; + reg [63:0] CLKFBOUT_MULT_F_BIN; + reg [63:0] CLKFBOUT_PHASE_BIN; + reg CLKFBOUT_USE_FINE_PS_BIN; + reg [63:0] CLKIN1_PERIOD_BIN; + reg [63:0] CLKIN2_PERIOD_BIN; + reg [63:0] CLKIN_FREQ_MAX_BIN; + reg [63:0] CLKIN_FREQ_MIN_BIN; + reg [63:0] CLKOUT0_DIVIDE_F_BIN; + reg [63:0] CLKOUT0_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT0_PHASE_BIN; + reg CLKOUT0_USE_FINE_PS_BIN; + reg [7:0] CLKOUT1_DIVIDE_BIN; + reg [63:0] CLKOUT1_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT1_PHASE_BIN; + reg CLKOUT1_USE_FINE_PS_BIN; + reg [7:0] CLKOUT2_DIVIDE_BIN; + reg [63:0] CLKOUT2_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT2_PHASE_BIN; + reg CLKOUT2_USE_FINE_PS_BIN; + reg [7:0] CLKOUT3_DIVIDE_BIN; + reg [63:0] CLKOUT3_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT3_PHASE_BIN; + reg CLKOUT3_USE_FINE_PS_BIN; + reg CLKOUT4_CASCADE_BIN; + reg [7:0] CLKOUT4_DIVIDE_BIN; + reg [63:0] CLKOUT4_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT4_PHASE_BIN; + reg CLKOUT4_USE_FINE_PS_BIN; + reg [7:0] CLKOUT5_DIVIDE_BIN; + reg [63:0] CLKOUT5_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT5_PHASE_BIN; + reg CLKOUT5_USE_FINE_PS_BIN; + reg [7:0] CLKOUT6_DIVIDE_BIN; + reg [63:0] CLKOUT6_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT6_PHASE_BIN; + reg CLKOUT6_USE_FINE_PS_BIN; + reg [63:0] CLKPFD_FREQ_MAX_BIN; + reg [63:0] CLKPFD_FREQ_MIN_BIN; + reg [2:0] COMPENSATION_BIN; + reg [6:0] DIVCLK_DIVIDE_BIN; + reg [63:0] REF_JITTER1_BIN; + reg [63:0] REF_JITTER2_BIN; + reg SS_EN_BIN; + reg [1:0] SS_MODE_BIN; + reg [15:0] SS_MOD_PERIOD_BIN; + reg STARTUP_WAIT_BIN; + reg [63:0] VCOCLK_FREQ_MAX_BIN; + reg [63:0] VCOCLK_FREQ_MIN_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg CDDCDONE_out; + reg CLKFBOUTB_out; + reg CLKFBOUT_out; + reg CLKFBSTOPPED_out; + reg CLKINSTOPPED_out; + reg CLKOUT0B_out; + reg CLKOUT0_out; + reg CLKOUT1B_out; + reg CLKOUT1_out; + reg CLKOUT2B_out; + reg CLKOUT2_out; + reg CLKOUT3B_out; + reg CLKOUT3_out; + reg CLKOUT4_out; + reg CLKOUT5_out; + reg CLKOUT6_out; + reg DRDY_out; + reg LOCKED_out; + reg PSDONE_out; + reg [15:0] DO_out; + + wire CDDCREQ_in; + wire CLKFBIN_in; + wire CLKIN1_in; + wire CLKIN2_in; + wire CLKINSEL_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire PSCLK_in; + wire PSEN_in; + wire PSINCDEC_in; + wire PWRDWN_in; + wire RST_in; + wire [15:0] DI_in; + wire [6:0] DADDR_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire PSCLK_delay; + wire PSEN_delay; + wire PSINCDEC_delay; + wire [15:0] DI_delay; + wire [6:0] DADDR_delay; +`endif + + assign CDDCDONE = CDDCDONE_out; + assign CLKFBOUT = CLKFBOUT_out; + assign CLKFBOUTB = CLKFBOUTB_out; + assign CLKFBSTOPPED = CLKFBSTOPPED_out; + assign CLKINSTOPPED = CLKINSTOPPED_out; + assign CLKOUT0 = CLKOUT0_out; + assign CLKOUT0B = CLKOUT0B_out; + assign CLKOUT1 = CLKOUT1_out; + assign CLKOUT1B = CLKOUT1B_out; + assign CLKOUT2 = CLKOUT2_out; + assign CLKOUT2B = CLKOUT2B_out; + assign CLKOUT3 = CLKOUT3_out; + assign CLKOUT3B = CLKOUT3B_out; + assign CLKOUT4 = CLKOUT4_out; + assign CLKOUT5 = CLKOUT5_out; + assign CLKOUT6 = CLKOUT6_out; + assign DO = DO_out; + assign DRDY = DRDY_out; + assign LOCKED = LOCKED_out; + assign PSDONE = PSDONE_out; + +`ifdef XIL_TIMING + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`else + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`endif + + assign CDDCREQ_in = (CDDCREQ !== 1'bz) && CDDCREQ; // rv 0 + assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0 + assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0 + assign CLKIN2_in = (CLKIN2 !== 1'bz) && (CLKIN2 ^ IS_CLKIN2_INVERTED_REG); // rv 0 + assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_REG); // rv 1 + assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0 + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + assign CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + assign CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + assign CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_FALSE; + + assign CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + assign CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + assign CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + assign CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + assign CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + assign CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + assign CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + assign CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_FALSE; + + assign CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + assign CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + assign CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + assign CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_FALSE; + + assign CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + assign CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + assign CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + assign CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_FALSE; + + assign CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + assign CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + assign CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + assign CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_FALSE; + + assign CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + assign CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + assign CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + assign CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + assign CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_FALSE; + + assign CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + assign CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + assign CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + assign CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_FALSE; + + assign CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + assign CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + assign CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + assign CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_FALSE; + + assign CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + assign CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + COMPENSATION_AUTO; + + assign DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + assign REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + assign REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + assign SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + assign SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + assign SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + assign STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + assign VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + assign VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_FALSE; + + CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_FALSE; + + CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_FALSE; + + CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_FALSE; + + CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_FALSE; + + CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_FALSE; + + CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_FALSE; + + CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_FALSE; + + CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + COMPENSATION_AUTO; + + DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BANDWIDTH_REG != "OPTIMIZED") && + (BANDWIDTH_REG != "HIGH") && + (BANDWIDTH_REG != "LOW"))) begin + $display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > 64.000)) begin + $display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to 64.000. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKFBOUT_USE_FINE_PS_REG != "FALSE") && + (CLKFBOUT_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin + $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin + $display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT0_USE_FINE_PS_REG != "FALSE") && + (CLKOUT0_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_USE_FINE_PS_REG != "FALSE") && + (CLKOUT1_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_USE_FINE_PS_REG != "FALSE") && + (CLKOUT2_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_USE_FINE_PS_REG != "FALSE") && + (CLKOUT3_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_CASCADE_REG != "FALSE") && + (CLKOUT4_CASCADE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_USE_FINE_PS_REG != "FALSE") && + (CLKOUT4_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_USE_FINE_PS_REG != "FALSE") && + (CLKOUT5_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_USE_FINE_PS_REG != "FALSE") && + (CLKOUT6_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin + $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((COMPENSATION_REG != "AUTO") && + (COMPENSATION_REG != "BUF_IN") && + (COMPENSATION_REG != "EXTERNAL") && + (COMPENSATION_REG != "INTERNAL") && + (COMPENSATION_REG != "ZHOLD"))) begin + $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are AUTO, BUF_IN, EXTERNAL, INTERNAL or ZHOLD. Instance: %m", MODULE_NAME, COMPENSATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin + $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin + $display("Error: [Unisim %s-150] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin + $display("Error: [Unisim %s-151] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_EN_REG != "FALSE") && + (SS_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-152] SS_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SS_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MODE_REG != "CENTER_HIGH") && + (SS_MODE_REG != "CENTER_LOW") && + (SS_MODE_REG != "DOWN_HIGH") && + (SS_MODE_REG != "DOWN_LOW"))) begin + $display("Error: [Unisim %s-153] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin + $display("Error: [Unisim %s-154] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_WAIT_REG != "FALSE") && + (STARTUP_WAIT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin + $display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MIN_REG < 600.000 || VCOCLK_FREQ_MIN_REG > 600.000)) begin + $display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute are 600.000 to 600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG); + attr_err = 1'b1; + end + + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + localparam VCOCLK_FREQ_TARGET = 1000; + localparam M_MIN = 2.000; + localparam M_MAX = 64.000; + localparam real VF_MIN = 600.000; + localparam D_MIN = 1; + localparam D_MAX = 106; + localparam O_MIN = 1; + localparam O_MAX = 128; + localparam O_MAX_HT_LT = 64; + localparam REF_CLK_JITTER_MAX = 1000; + localparam REF_CLK_JITTER_SCALE = 0.1; + localparam MAX_FEEDBACK_DELAY = 5.0; + localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; + localparam ps_max = 55; + + reg [160:1] clkout_name; + real CLKOUT0_DIVIDE_F_RND; + real CLKFBOUT_MULT_F_RND; + + tri1 p_up; + wire glock; + + integer pchk_tmp1, pchk_tmp2; + integer clkvco_div_fint; + real clkvco_div_frac; + reg clk0_out; + reg clkfbout_out; + integer clkvco_frac_en; + integer ps_in_init; + reg clk0_fps_en=0, clk1_fps_en=0, clk2_fps_en=0, clk3_fps_en=0; + reg clk4_fps_en=0, clk5_fps_en=0, clk6_fps_en=0, clkfbout_fps_en=0; + reg fps_en=1'b0, fps_clk_en=1'b0; + reg clkinstopped_out1; + reg clkin_hold_f = 0; + reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0; + integer period_avg_stpi = 0, period_avg_stp = 0; + real tmp_stp1, tmp_stp2; + reg pd_stp_p = 0; + reg vco_stp_f = 0; + reg psen_w = 0; + reg clkinstopped_out_dly = 0; + reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp; + reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; + reg rst_clkinstopped_rc = 0; + reg rst_clkinstopped_lk, rst_clkfbstopped_lk; + integer clkin_lost_cnt; + integer clkfbin_lost_cnt; + reg clkinstopped_hold = 0; + integer ps_in_ps, ps_cnt; + integer ps_in_ps_neg, ps_cnt_neg; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drp_lock; + integer drp_lock_lat = 4; + integer drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [160:0] tmp_string; + reg rst_int = 1'b0; + reg pwron_int; + wire rst_in_o; + reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out; + reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; + integer clkout_en_val, clkout_en_t; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + reg clkvco = 1'b0; + reg clkvco_lk_dly_tmp; + reg clkvco_lk_en; + reg clkvco_lk; + reg fbclk_tmp; + reg clkin_osc, clkin_p; + reg clkfbin_osc, clkfbin_p; + reg clkinstopped_vco_f; + time rst_edge, rst_ht; + reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0; + reg clkfbout_tst=1'b0; + real fb_delay_max; + time fb_delay=0, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay; + time dly_tmp1, tmp_ps_val2; + integer dly_tmp_int, tmp_ps_val1; + time clkin_edge, delay_edge; + real period_clkin, clkin_period_tmp; + integer clkin_period_tmp_t; + integer clkin_period [4:0]; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + real period_vco_rl, period_vco_rl_half; + integer period_vco_half_rm1, period_vco_half_rm2; + real cmpvco = 0.0; + real clkvco_pdrm; + integer period_vco_mf; + integer period_vco_tmp; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco_max, period_vco_min; + integer period_vco1, period_vco2, period_vco3, period_vco4; + integer period_vco5, period_vco6, period_vco7; + integer period_vco_target, period_vco_target_half; + integer period_fb=100000, period_avg=100000; + integer clk0_frac_lt, clk0_frac_ht; + real clk0_frac_lt_rl, clk0_frac_ht_rl; + integer clk0_frac_rm; + real clk0_frac_rm_rl; + integer clkfbout_frac_lt, clkfbout_frac_ht; + real clkfbout_frac_lt_rl, clkfbout_frac_ht_rl; + integer clkfbout_frac_rm; + real clkfbout_frac_rm_rl; + integer period_ps, period_ps_old; + reg ps_lock, ps_lock_dly; + real clkvco_freq_init_chk, clkfbout_pm_rl; + real tmp_real; + integer ik0, ik1, ik2, ik3, ik4, ib, i, j; + integer md_product, m_product, m_product2; + integer mf_product, clk0f_product; +// integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk; + integer clkin_lost_val; + integer clkfbin_lost_val; + time pll_locked_delay, clkin_dly_t, clkfbin_dly_t; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock; + integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + wire init_trig, clkpll_r; + reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0; + reg clk4in=1'b0,clk5in=1'b0,clk6in=1'b0; + reg clkpll_tmp1, clkpll; + reg clkfboutin=1'b0; + wire clkfbps_en; + reg chk_ok; + wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en; + wire clk4ps_en, clk5ps_en, clk6ps_en; + reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel; + reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel; + reg [6:0] d_fht, clkfbout_fht, clk0_fht; + reg [6:0] d_flt, clkfbout_flt, clk0_flt; + reg [5:0] clk0_dly_cnt; + reg [5:0] clk1_dly_cnt; + reg [5:0] clk2_dly_cnt; + reg [5:0] clk3_dly_cnt; + reg [5:0] clk4_dly_cnt; + reg [5:0] clk5_dly_cnt; + reg [5:0] clk6_dly_cnt; + real clk0_phase, clk0_duty; + real clk1_phase, clk1_duty; + real clk2_phase, clk2_duty; + real clk3_phase, clk3_duty; + real clk4_phase, clk4_duty; + real clk5_phase, clk5_duty; + real clk6_phase, clk6_duty; + real divclk_phase=0.000, divclk_duty=0.500; + real clkfbout_phase, clkfbout_duty=0.500; +// mem cells + reg [2:0] d_frac, clkfbout_frac, clk0_frac; + reg d_frac_en, clkfbout_frac_en, clk0_frac_en; + reg clk0_cddc_en=1'b0, clk1_cddc_en=1'b0, clk2_cddc_en=1'b0, clk3_cddc_en=1'b0, clk4_cddc_en=1'b0, clk5_cddc_en=1'b0, clk6_cddc_en=1'b0, clkfbout_cddc_res=1'b0; + reg d_wf_f; + reg clkfbout_wf_f, clk0_wf_f; + reg d_wf_r; + reg clkfbout_wf_r, clk0_wf_r; + reg [2:0] d_mx, clkfbout_mx; + reg [2:0] clk0_mx, clk1_mx, clk2_mx, clk3_mx; + reg [2:0] clk4_mx, clk5_mx, clk6_mx; + reg divclk_e, clkfbin_e; + reg clkfbout_e; + reg clk0_e, clk1_e, clk2_e, clk3_e; + reg clk4_e, clk5_e, clk6_e; + reg divclk_nc, clkfbin_nc; + reg clkfbout_nc; + reg clk0_nc, clk1_nc, clk2_nc, clk3_nc; + reg clk4_nc, clk5_nc, clk6_nc; + reg [5:0] d_dt=0, clkfbout_dt=0; + reg [5:0] clk0_dt=0, clk1_dt=0, clk2_dt=0, clk3_dt=0; + reg [5:0] clk4_dt=0, clk5_dt=0, clk6_dt=0; + reg [2:0] d_pm_f; + reg [2:0] clkfbout_pm_f, clk0_pm_f; + reg [2:0] clkfbout_pm_r, clk0_pm_r; + reg [2:0] d_pm; + reg [2:0] clk1_pm, clk2_pm, clk3_pm; + reg [2:0] clk4_pm, clk5_pm, clk6_pm; + reg divclk_en=1, clkfbout_en=1; + reg clk0_en=1, clk1_en=1, clk2_en=1, clk3_en=1; + reg clk4_en=1, clk5_en=1, clk6_en=1; + reg [5:0] clkfbin_ht; + reg [5:0] clkfbout_ht; + reg [7:0] divclk_ht; + reg [5:0] clk0_ht, clk1_ht, clk2_ht, clk3_ht; + reg [5:0] clk4_ht, clk5_ht, clk6_ht; + reg [5:0] clkfbin_lt; + reg [7:0] divclk_lt; + reg [6:0] clkfbout_lt; + reg [6:0] clk0_lt, clk1_lt, clk2_lt, clk3_lt; + reg [6:0] clk4_lt, clk5_lt, clk6_lt; +// + real clkfbout_f_div=1.0; + real clk0_f_div; + integer d_div, clkfbout_div, clk0_div; + reg [5:0] clkfbout_dly_cnt; + reg [7:0] clkfbout_cnt; + reg [7:0] clk0_cnt; + reg [7:0] clk1_cnt, clk1_div; + reg [7:0] clk2_cnt, clk2_div; + reg [7:0] clk3_cnt, clk3_div; + reg [7:0] clk4_cnt, clk4_div; + reg [7:0] clk5_cnt, clk5_div; + reg [7:0] clk6_cnt, clk6_div; + integer divclk_cnt_max, clkfbout_cnt_max; + integer clk0_cnt_max, clk1_cnt_max, clk2_cnt_max, clk3_cnt_max; + integer clk4_cnt_max, clk5_cnt_max, clk6_cnt_max; + integer divclk_cnt_ht, clkfbout_cnt_ht; + integer clk0_cnt_ht, clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht; + integer clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht; + reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0; + reg divclk_out, divclk_out_tmp; + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + wire clkinsel_tmp; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + real clkpfd_freq_init_chk; + reg init_chk; + reg rst_clkinsel_flag = 0; + wire CLKFBIN_int; + wire pwrdwn_in1; + reg pwrdwn_in1_h = 0; + reg rst_input_r_h = 0; + reg pchk_clr = 0; + reg psincdec_chg = 0; + reg psincdec_chg_tmp = 0; + wire rst_input; + wire clkfbin_sel; + reg vcoflag = 0; + reg drp_updt = 1'b0; + + real halfperiod_sum = 0.0; + integer halfperiod = 0; + reg clkvco_free = 1'b0; + integer ik10=0, ik11=0; + +`ifndef XIL_XECLIB + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin + $display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + #1 $finish; + end + + CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0; + CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0; + + if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin + $display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin + $display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + + if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + + clkfbout_f_div = CLKFBOUT_MULT_F_RND; + attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + + clk0_f_div = CLKOUT0_DIVIDE_F_RND; + attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + + clk1_div = CLKOUT1_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + clk2_div = CLKOUT2_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + clk3_div = CLKOUT3_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + clk4_div = CLKOUT4_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + clk5_div = CLKOUT5_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + clk6_div = CLKOUT6_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + divclk_div = DIVCLK_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + + ps_in_init = 0; + ps_in_ps = ps_in_init; + ps_cnt = 0; + + clk0_fps_en = (CLKOUT0_USE_FINE_PS_REG == "TRUE"); + clk1_fps_en = (CLKOUT1_USE_FINE_PS_REG == "TRUE"); + clk2_fps_en = (CLKOUT2_USE_FINE_PS_REG == "TRUE"); + clk3_fps_en = (CLKOUT3_USE_FINE_PS_REG == "TRUE"); + clk4_fps_en = (CLKOUT4_USE_FINE_PS_REG == "TRUE"); + clk5_fps_en = (CLKOUT5_USE_FINE_PS_REG == "TRUE"); + clk6_fps_en = (CLKOUT6_USE_FINE_PS_REG == "TRUE"); + clkfbout_fps_en = (CLKFBOUT_USE_FINE_PS_REG == "TRUE"); + + fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en + || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en; + + if (clk0_frac_en == 1'b1) begin + if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin + $display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + #1 $finish; + end + end + + pll_lfhf = 2'b00; + + if (BANDWIDTH_REG === "LOW") + case (clkfbout_div) + 2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 4 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 5 : begin pll_cp = 4'b0010 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b0010 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b0010 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b0010 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b0010 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 13 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 14 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 15 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end + 16 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 17 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 18 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end + 19 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 20 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 21 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 22 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 23 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 24 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 25 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end + 26 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 27 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 28 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 29 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 30 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end + 31 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 32 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 33 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 34 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 35 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 36 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 37 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 38 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 39 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 40 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 41 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 47 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end + 48 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 49 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 50 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 51 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 52 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 53 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 54 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 55 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 56 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 57 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 62 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 63 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + 64 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end + endcase + else if (BANDWIDTH_REG === "HIGH") + case (clkfbout_div) + 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end + 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end + 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end + 13 : begin pll_cp = 4'b1110 ; pll_res = 4'b0001 ; end + 14 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 15 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 16 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 17 : begin pll_cp = 4'b1110 ; pll_res = 4'b0110 ; end + 18 : begin pll_cp = 4'b1111 ; pll_res = 4'b0110 ; end + 19 : begin pll_cp = 4'b1110 ; pll_res = 4'b1010 ; end + 20 : begin pll_cp = 4'b1110 ; pll_res = 4'b1010 ; end + 21 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 22 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 23 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 24 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 25 : begin pll_cp = 4'b0111 ; pll_res = 4'b0010 ; end + 26 : begin pll_cp = 4'b0111 ; pll_res = 4'b0010 ; end + 27 : begin pll_cp = 4'b1110 ; pll_res = 32'd10; end + 28 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 29 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 30 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 31 : begin pll_cp = 4'b0100 ; pll_res = 4'b0100 ; end + 32 : begin pll_cp = 4'b1101 ; pll_res = 4'b0110 ; end + 33 : begin pll_cp = 4'b1101 ; pll_res = 4'b0110 ; end + 34 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 35 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 36 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end + 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + endcase + else if (BANDWIDTH_REG === "OPTIMIZED") + case (clkfbout_div) + 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end + 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end + 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end + 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end + 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end + 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end + 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end + 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end + 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end + 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end + 13 : begin pll_cp = 4'b1110 ; pll_res = 4'b0001 ; end + 14 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 15 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 16 : begin pll_cp = 4'b1111 ; pll_res = 4'b0001 ; end + 17 : begin pll_cp = 4'b1110 ; pll_res = 4'b0110 ; end + 18 : begin pll_cp = 4'b1111 ; pll_res = 4'b0110 ; end + 19 : begin pll_cp = 4'b1110 ; pll_res = 4'b1010 ; end + 20 : begin pll_cp = 4'b1110 ; pll_res = 4'b1010 ; end + 21 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 22 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 23 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 24 : begin pll_cp = 4'b1111 ; pll_res = 4'b1010 ; end + 25 : begin pll_cp = 4'b0111 ; pll_res = 4'b0010 ; end + 26 : begin pll_cp = 4'b0111 ; pll_res = 4'b0010 ; end + 27 : begin pll_cp = 4'b1110 ; pll_res = 4'b1010 ; end + 28 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 29 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 30 : begin pll_cp = 4'b0110 ; pll_res = 4'b0010 ; end + 31 : begin pll_cp = 4'b0100 ; pll_res = 4'b0100 ; end + 32 : begin pll_cp = 4'b1101 ; pll_res = 4'b0110 ; end + 33 : begin pll_cp = 4'b1101 ; pll_res = 4'b0110 ; end + 34 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 35 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 36 : begin pll_cp = 4'b0101 ; pll_res = 4'b0010 ; end + 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end + 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end + 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end + 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end + 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end + 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end + 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end + 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end + 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end + endcase + + case (clkfbout_div) + 1 : begin drp_lock_ref_dly = 5'd6; + drp_lock_fb_dly = 5'd6; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 2 : begin drp_lock_ref_dly = 5'd6; + drp_lock_fb_dly = 5'd6; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 3 : begin drp_lock_ref_dly = 5'd8; + drp_lock_fb_dly = 5'd8; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 4 : begin drp_lock_ref_dly = 5'd11; + drp_lock_fb_dly = 5'd11; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 5 : begin drp_lock_ref_dly = 5'd14; + drp_lock_fb_dly = 5'd14; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 6 : begin drp_lock_ref_dly = 5'd17; + drp_lock_fb_dly = 5'd17; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 7 : begin drp_lock_ref_dly = 5'd19; + drp_lock_fb_dly = 5'd19; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 8 : begin drp_lock_ref_dly = 5'd22; + drp_lock_fb_dly = 5'd22; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 9 : begin drp_lock_ref_dly = 5'd25; + drp_lock_fb_dly = 5'd25; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 10 : begin drp_lock_ref_dly = 5'd28; + drp_lock_fb_dly = 5'd28; + drp_lock_cnt = 10'd1000; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 11 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd900; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 12 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd825; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 13 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd750; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 14 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd700; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 15 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd650; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 16 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd625; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 17 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd575; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 18 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd550; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 19 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd525; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 20 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd500; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 21 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd475; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 22 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd450; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 23 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd425; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 24 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd400; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 25 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd400; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 26 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd375; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 27 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd350; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 28 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd350; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 29 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd325; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 30 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd325; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 31 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 32 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 33 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd300; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 34 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 35 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 36 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd275; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 37 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 38 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 39 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 40 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 41 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 42 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 43 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 44 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 45 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 46 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 47 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 48 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 49 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 50 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 51 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 52 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 53 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 54 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 55 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 56 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 57 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 58 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 59 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 60 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 61 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 62 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 63 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + 64 : begin drp_lock_ref_dly = 5'd31; + drp_lock_fb_dly = 5'd31; + drp_lock_cnt = 10'd250; + drp_lock_sat_high = 10'd1001; + drp_unlock_cnt = 10'd1; end + endcase + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX); + tmp_string = "CLKFBOUT_MULT_F"; + chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string); + if(clk0_frac_en == 1'b0) begin + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string); + end + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string); + period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + clk0f_product = CLKOUT0_DIVIDE_F_RND * 8; + pll_lock_time = 12; + lock_period_time = 10; + if (clkfbout_frac_en == 1'b1) begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + clkout_en_val = mf_product - 1; + m_product2 = clkfbout_div / 2; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + m_product2 = clkfbout_div / 2; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + divclk_div = DIVCLK_DIVIDE_REG; + + dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[7] = {clk0_pm_f[2:0], clk0_wf_f, 1'bx, clk5_cddc_en, + 2'b0, clk5_e, clk5_nc, clk5_dt[5:0]}; + dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {clk0_cddc_en, clk0_frac[2:0], clk0_frac_en, clk0_wf_r, + 2'b0, clk0_e, clk0_nc, clk0_dt[5:0]}; + dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {5'bx, clk1_cddc_en, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]}; + dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[13] = {5'bx, clk2_cddc_en, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]}; + dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[15] = {5'bx, clk3_cddc_en, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]}; + dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[17] = {5'bx, clk4_cddc_en, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]}; + dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]}; + dr_sram[19] = {clkfbout_pm_f[2:0], clkfbout_wf_f, 1'bx, clk6_cddc_en, + 2'b0, clk6_e, clk6_nc, clk6_dt[5:0]}; + dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]}; + dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en, + clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]}; + dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]}; + dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[28] = {11'bx, 5'b0}; + dr_sram[39] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + end +`endif + + initial begin + clkpll_jitter_unlock = 0; + clkinstopped_vco_f = 0; + rst_clkfbstopped = 0; + rst_clkinstopped = 0; + rst_clkfbstopped_lk = 0; + rst_clkinstopped_lk = 0; + clkfbin_stop_tmp = 0; + clkin_stop_tmp = 0; + clkvco_lk_en = 0; + clkvco_lk_dly_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + divclk_div = DIVCLK_DIVIDE_REG; + ps_lock = 0; + ps_lock_dly = 0; + PSDONE_out = 1'b0; + rst_int = 0; + CLKINSTOPPED_out = 1'b0; + clkinstopped_out1 = 0; + CLKFBSTOPPED_out = 1'b0; + clkfbstopped_out1 = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_period_tmp_t = 0; + period_avg = 100000; + period_fb = 100000; + clkin_lost_val = 2; + clkfbin_lost_val = 2; + fb_delay = 0; + clkvco_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fb_comp_delay = 0; + clkfbout_pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + period_ps = 0; + period_ps_old = 0; + clkfbout_frac_ht = 0; + clkfbout_frac_lt = 0; + clk0_frac_ht = 0; + clk0_frac_lt = 0; + clk0_frac_ht_rl = 0.0; + clk0_frac_lt_rl = 0.0; + clkvco_rm_cnt = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + fbclk_tmp = 0; + clkfbout_tst = 1'b0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + DRDY_out = 1'b0; + CDDCDONE_out = 1'b0; + LOCKED_out = 1'b0; + DO_out = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clk6_dly_cnt = 6'b0; + clkfbout_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clk6_cnt = 8'b0; + clkfbout_cnt = 8'b0; + divclk_cnt = 8'b0; + CLKOUT0_out = 1'b0; + CLKOUT0B_out = 1'b1; + CLKOUT1_out = 1'b0; + CLKOUT1B_out = 1'b1; + CLKOUT2_out = 1'b0; + CLKOUT2B_out = 1'b1; + CLKOUT3_out = 1'b0; + CLKOUT3B_out = 1'b1; + CLKOUT4_out = 1'b0; + CLKOUT5_out = 1'b0; + CLKOUT6_out = 1'b0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clk6_out = 0; + CLKFBOUT_out = 1'b0; + CLKFBOUTB_out = 1'b1; + divclk_out = 0; + divclk_out_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign #2 clkinsel_tmp = CLKINSEL_in; + + assign glock = (STARTUP_WAIT_BIN == STARTUP_WAIT_FALSE) || LOCKED; + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + + initial begin + init_chk = 0; + #2; + init_chk = 1; + #2; + init_chk = 0; + end + + always @(CLKINSEL_in or posedge init_chk ) begin + #1; + if (init_chk == 0 && $time > 3 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time); + #1 $finish; + end + + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin + if (CLKIN1_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN1_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + + #1 $finish; + end + end + else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin + if (CLKIN2_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN2_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + #1 $finish; + end + end + + period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG; + if (period_clkin == 0) period_clkin = 10; + + if (period_clkin < MAX_FEEDBACK_DELAY) + fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE; + else + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG); + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + end + clkpfd_freq_init_chk = (1000.0) / (period_clkin * DIVCLK_DIVIDE_REG); + if (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-9] The calculated PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz set by CLKPFD_FREQ_MIN/MAX. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-10] The calculated PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz set by CLKPFD_FREQ_MIN/MAX. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + end + end + + assign init_trig = 1; + assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in; + + assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0; + assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkpll_r or posedge rst_input) + if (rst_input) + rst_int <= 1; + else + rst_int <= rst_input ; + + assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped); + +//simprim_rst_h + always @(posedge pwrdwn_in1 or posedge pchk_clr) + if (pwrdwn_in1) + pwrdwn_in1_h <= 1; + else if (pchk_clr) + pwrdwn_in1_h <= 0; + + always @(posedge RST_in or posedge pchk_clr) + if (RST_in) + rst_input_r_h <= 1; + else if (pchk_clr) + rst_input_r_h <= 0; + + + always @(rst_input ) + if (rst_input==1) begin + rst_edge = $time; + pchk_clr = 0; + end + else if (rst_input==0 && rst_edge > 1) begin + rst_ht = $time - rst_edge; + if (rst_ht < 1500) begin + if (rst_input_r_h == 1 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns) . Instance %m ", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0) + $display("Warning: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + end + pchk_clr = 1; + end +//endsimprim_rst_h + + // + // DRP port read and write + // + + always @ (*) begin + DO_out = dr_sram[daddr_lat]; + end + + always @(posedge DCLK_in or posedge glblGSR) + if (glblGSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 0; + drp_updt <= 1'b0; + end + else begin + if (~(RST_in || CDDCREQ_in) && drp_updt) drp_updt <= 1'b0; + if (DEN_in == 1) begin + valid_daddr = addr_is_valid(DADDR_in); + if (drp_lock == 1) begin + $display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); + end + else begin + drp_lock <= 1; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + daddr_lat <= DADDR_in; + end + if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time); + if (DWE_in == 1) begin // write process + if (rst_input == 1 || CDDCREQ_in == 1) begin + if (valid_daddr) dr_sram[DADDR_in] <= DI_in; + if (valid_daddr || drp_updt) drp_updt <= 1'b1; + if (DADDR_in == 7'd6) + lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in); + else if (DADDR_in == 7'd7) + upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_cddc_en, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in); + else if (DADDR_in == 7'd8) + lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in); + else if (DADDR_in == 7'd9) begin + upper_frac_drp(clk0_cddc_en, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in); + end else if (DADDR_in == 7'd10) + lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in); + else if (DADDR_in == 7'd11) + upper_drp(clk1_cddc_en, clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in); + else if (DADDR_in == 7'd12) + lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in); + else if (DADDR_in == 7'd13) + upper_drp(clk2_cddc_en, clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in); + else if (DADDR_in == 7'd14) + lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in); + else if (DADDR_in == 7'd15) + upper_drp(clk3_cddc_en, clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in); + else if (DADDR_in == 7'd16) + lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in); + else if (DADDR_in == 7'd17) + upper_drp(clk4_cddc_en, clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in); + else if (DADDR_in == 7'd18) + lower_drp(clk6_pm, clk6_en, clk6_ht, clk6_lt, DI_in); + else if (DADDR_in == 7'd19) + upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_cddc_en, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in); + else if (DADDR_in == 7'd20) + lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in); + else if (DADDR_in == 7'd21) + upper_frac_drp(clkfbout_cddc_res, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in); + else if (DADDR_in == 7'd22) begin + divclk_e = DI_in[13]; + divclk_nc = DI_in[12]; + divclk_ht = DI_in[11:6]; + divclk_lt = DI_in[5:0]; + end + end + else begin + $display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + end + else begin + drp_lock <= 0; + DRDY_out <= 1; + drp_lock_lat_cnt <= 0; + end + end + if (DRDY == 1) DRDY_out <= 0; + end + + always @(posedge CDDCREQ_in or negedge CDDCREQ_in) + begin + if (CDDCREQ_in == 1'b1) + CDDCDONE_out <= 1'b0; + else + begin + @(posedge clkvco) + @(posedge clkvco) + @(posedge clkvco) + CDDCDONE_out <= ~CDDCREQ_in; + end + end + + function addr_is_valid; + input [6:0] daddr_in; + begin + addr_is_valid = 1'b1; + for (i=0; i<=6; i=i+1) + if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0; + if ((addr_is_valid) && + ((daddr_in >= 7'd06 && daddr_in <= 7'd22) || + (daddr_in >= 7'd24 && daddr_in <= 7'd26) || + (daddr_in == 7'd28) || + (daddr_in == 7'd39) || + (daddr_in == 7'd78) || + (daddr_in == 7'd79))) addr_is_valid = 1'b1; + else addr_is_valid = 1'b0; + end + endfunction + + // end process drp; + + // + // determine clock period + // + + always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag) + if (rst_int || rst_clkinsel_flag) + begin + clkin_period[0] <= 1000 * period_clkin; + clkin_period[1] <= 1000 * period_clkin; + clkin_period[2] <= 1000 * period_clkin; + clkin_period[3] <= 1000 * period_clkin; + clkin_period[4] <= 1000 * period_clkin; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end else begin + clkin_edge <= $time; + if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= #1 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(posedge pll_locked_tmp1) + if (CLKINSEL_in === 0) begin + pchk_tmp1 = CLKIN2_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN2_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + else begin + pchk_tmp1 = CLKIN1_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN1_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + + always @(*) + if (rst_int == 0) begin + if (clkfbout_frac_en == 1'b0) begin + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + clkout_en_val = mf_product - 1; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + end + + always @(clkout_en0_tmp) begin + #1; + if(clkout_en0_tmp==1'b1 && clkout_en_t==clkout_en_val && clkout_en_val>1) begin + @(posedge clkpll or negedge clkpll); + #1; + end + clkout_en0_tmp1 = clkout_en0_tmp; + end + + //clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + if (clkout_en0_tmp==0 ) + clkout_en0 = 0; + else begin + if (clkfbout_frac_en == 1'b1) begin + if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + else begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in_o ) + if (rst_in_o) + clkout_en = 0; + else + clkout_en = clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_int or glblGSR) + if (rst_int || glblGSR) begin + assign pll_locked_tmp2 = 0; + end + else begin + deassign pll_locked_tmp2; + end + + always @(rst_int) + if (rst_int) begin + assign clkout_en0 = 0; + assign clkout_en1 = 0; + end + else begin + deassign clkout_en0; + deassign clkout_en1; + end + + always @(rst_int or pll_locked_tm or pll_locked_tmp2 or pll_unlock or unlock_recover) begin + if ((rst_int == 1) && (LOCKED !== 1'b0)) + LOCKED_out <= #1000 0; + else if ((pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && ~unlock_recover) === 1'b1) + LOCKED_out <= 1'b1; + else + LOCKED_out <= 1'b0; + end + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4]) begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; + + if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + end + + always @(clkinstopped_out1 or clkin_hold_f or rst_int) + if (rst_int) + clkinstopped_hold = 0; + else begin + if (clkinstopped_out1) + clkinstopped_hold <= 1; + else begin + if (clkin_hold_f) + clkinstopped_hold = 0; + end + end + + always @(posedge clkinstopped_out1) begin + period_avg_stpi <= period_avg; + pd_stp_p <= #1 1; + @(negedge clkvco) + pd_stp_p <= #1 0; + end + + always @(negedge clkvco or posedge rst_int or posedge pd_stp_p) + if (rst_int) begin + period_avg_stp <= 1000; + vco_stp_f <= 0; + end + else if (pd_stp_p) + period_avg_stp <= period_avg_stpi; + else begin + if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin + if (period_vco > 1739) + vco_stp_f <= 1; + else begin + period_avg_stp <= period_avg_stp + 1; + end + end + end + + + always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold + or period_avg_stp or posedge rst_clkinstopped_rc) + if (period_avg > 0 ) begin + md_product = divclk_div * clkfbout_f_div; + m_product = clkfbout_f_div; + m_product2 = clkfbout_f_div / 2; + clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div); + clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint; + if (clkvco_div_frac > 0.000) + clkvco_frac_en = 1; + else + clkvco_frac_en = 0; + period_fb = period_avg * divclk_div; + period_vco_tmp = period_fb / clkfbout_f_div; + period_vco_rl = 1.0 * period_fb / clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp; + period_vco_mf = period_avg * 8; + if (clkinstopped_hold == 1) begin + if (clkin_hold_f) begin + period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl_half = period_vco_rl / 2.0; + end + else begin + period_vco = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + end + end + else + period_vco = period_vco_tmp; + + period_vco_rm = period_fb % clkfbout_div; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + if (period_vco_half_rm < 1) + period_vco_half_rm2 = 0; + else + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbout_f_div; + clkin_dly_t = period_avg * (divclk_div + 1.25); + clkfbin_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + end + + always @ (negedge RST_in or negedge CDDCREQ_in) begin + if (drp_updt) begin + clkout_name = "CLKFBOUT"; + mc_to_attr(clkout_name, clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty); + if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc) + $display("Error : [Unisim %s-38] CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time); + clkout_name = "CLKOUT0"; + mc_to_attr(clkout_name, clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty); + if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc) + $display("Error : [Unisim %s-37] CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time); + clkout_name = "CLKOUT1"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty); + clkout_name = "CLKOUT2"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty); + clkout_name = "CLKOUT3"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty); + clkout_name = "CLKOUT4"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty); + clkout_name = "CLKOUT5"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty); + clkout_name = "CLKOUT6"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty); + clkout_name = "DIVCLK"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty); + if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc) + $display("Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + end + end + + always @(clkfbout_f_div) begin + mf_product = clkfbout_f_div * 8; + end + + always @(*) begin + if (clkfbout_frac_en) begin + clkfbout_frac_ht_rl = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_rsel) / 8.0; + clkfbout_frac_lt_rl = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_fsel) / 8.0; + clkfbout_frac_ht = $rtoi(clkfbout_frac_ht_rl); + clkfbout_frac_lt = $rtoi(clkfbout_frac_lt_rl); + end + end + + always @(*) begin + if (clk0_frac_en) begin + clk0_frac_ht_rl = period_vco_rl * clk0_fht + (period_vco_rl * clk0_rsel) / 8.0; + clk0_frac_lt_rl = period_vco_rl * clk0_flt + (period_vco_rl * clk0_fsel) / 8.0; + clk0_frac_ht = $rtoi(clk0_frac_ht_rl); + clk0_frac_lt = $rtoi(clk0_frac_lt_rl); + end + end + + reg ps_wr_to_max = 1'b0; + always @(period_vco or ps_in_ps) + if (fps_en == 1) begin + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && PSINCDEC_in == 0) + period_ps = 0; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + + always @( clkpll_r ) + clkpll_tmp1 <= #(period_avg) clkpll_r; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(posedge clkinstopped_out1 or posedge rst_int) + if ( rst_int) + clkinstopped_vco_f <= 0; + else begin + clkinstopped_vco_f <= 1; + @(negedge clkinstopped_out1 or posedge rst_int ) + if (rst_int) + clkinstopped_vco_f <= 0; + else begin + @(posedge clkpll); + @(posedge clkpll) + clkinstopped_vco_f <= 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + CLKINSTOPPED_out <= 0; + else begin + CLKINSTOPPED_out <= 1; + if (clkin_hold_f == 1) begin + @(posedge LOCKED or posedge rst_int) + CLKINSTOPPED_out <= 0; + end + else begin + if (CLKINSEL_in == 1) + $display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + else + $display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + end + end + + always @(posedge clkfbstopped_out1 or posedge rst_int) + if (rst_int) + CLKFBSTOPPED_out <= 1'b0; + else begin + CLKFBSTOPPED_out <= 1'b1; + @(posedge LOCKED) + CLKFBSTOPPED_out <= 1'b0; + end + + always @(clkout_en_t) + if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) + rst_clkinstopped_tm = 1; + else + rst_clkinstopped_tm = 0; + + always @(negedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + rst_clkinstopped <= 0; + else + if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin + @(posedge rst_clkinstopped_tm) + rst_clkinstopped <= #period_vco4 1; + @(negedge rst_clkinstopped_tm ) begin + rst_clkinstopped <= #period_vco5 0; + rst_clkinstopped_rc <= #period_vco6 1; + rst_clkinstopped_rc <= #period_vco7 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly <= 0; + else begin + clkinstopped_out_dly <= 1; + if (clkin_hold_f == 1) begin + @(negedge rst_clkinstopped_rc or posedge rst_int) + clkinstopped_out_dly <= 0; + end + end + + always @(clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly2 <= 0; + else + clkinstopped_out_dly2 <= clkinstopped_out1; + + always @(negedge rst_clkinstopped or posedge rst_int) + if (rst_int) + rst_clkinstopped_lk <= 0; + else begin + rst_clkinstopped_lk <= 1; + @(posedge LOCKED) + rst_clkinstopped_lk <= 0; + end + + always @(clkinstopped_vco_f or CLKINSTOPPED or clkvco_lk or clkvco_free or rst_int) + if (rst_int) + clkvco_lk = 0; + else begin + if (CLKINSTOPPED == 1 && clkin_stop_f == 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else if (clkinstopped_vco_f == 1 && period_vco_half > 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else + clkvco_lk = clkvco_free; + end + +// free run vco comp + + always @(posedge clkpll) + if (pll_locked_tm == 1 ) begin + clkvco_free = 1'b1; + halfperiod_sum = 0.0; + halfperiod = 0; + if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin + if (mf_product > 1) begin + for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin + clkout_en_t <= ik10; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik10; + end else begin + clkout_en_t <= 1; + end + end else begin + if (m_product > 1) begin + for (ik11=1; ik11 < m_product; ik11=ik11+1) begin + clkout_en_t <= ik11; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik11; + end else begin + clkout_en_t <= 1; + end + end + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + if (clkfbout_f_div < divclk_div) begin + #(period_vco_rl_half - period_avg/2.0); + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl + or lock_period or ps_in_ps ) + if (lock_period == 1) begin + if (clkfbout_frac_en == 1'b1) begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + else begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + dly_tmp1 = fb_delay + fb_comp_delay; + dly_tmp_int = 1; + if (CLKFBOUT_USE_FINE_PS_BIN == CLKFBOUT_USE_FINE_PS_TRUE) begin + if (ps_in_ps < 0) begin + tmp_ps_val1 = -1 * ps_in_ps; + tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; + if (tmp_ps_val2 > dly_tmp1 ) begin + dly_tmp_int = -1; + dly_tmp = tmp_ps_val2 - dly_tmp1; + end + else if (tmp_ps_val2 == dly_tmp1 ) begin + dly_tmp_int = 0; + dly_tmp = 0; + end + else begin + dly_tmp_int = 1; + dly_tmp = dly_tmp1 - tmp_ps_val2; + end + end + else + dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; + end + else + dly_tmp = dly_tmp1; + + if (dly_tmp_int < 0) + clkvco_delay = dly_tmp; + else begin + if (clkfbout_frac_en == 1'b1 && dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + end + + always @(clkfbout_pm_r) + case (clkfbout_pm_r) + 3'b000 : clkfbout_pm_rl = 0.0; + 3'b001 : clkfbout_pm_rl = 0.125; + 3'b010 : clkfbout_pm_rl = 0.25; + 3'b011 : clkfbout_pm_rl = 0.375; + 3'b100 : clkfbout_pm_rl = 0.50; + 3'b101 : clkfbout_pm_rl = 0.625; + 3'b110 : clkfbout_pm_rl = 0.75; + 3'b111 : clkfbout_pm_rl = 0.875; + endcase + + always @(clkvco_lk) + clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; + + always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) + if ( pll_locked_tm && vco_stp_f == 0) begin + if (dly_tmp == 0) + clkvco = clkvco_lk; + else + clkvco = clkvco_lk_dly_tmp; + end + else + clkvco = 0; + + always @(posedge PSCLK_in or posedge rst_int) + if (rst_int) begin + ps_in_ps <= ps_in_init; + ps_cnt <= 0; + psen_w <= 0; + fps_clk_en <= 0; + ps_lock <= 0; + end else if (fps_en == 1) begin + fps_clk_en <= 1; + if (PSEN_in) begin + if (psen_w == 1) + $display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time); + + psen_w <= 1; + if (ps_lock == 1) + $display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time); + else if (PSINCDEC_in == 1) begin + if (ps_cnt < ps_max) + ps_cnt <= ps_cnt + 1; + else + ps_cnt <= 0; + + if (ps_in_ps < ps_max) + ps_in_ps <= ps_in_ps + 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + else if (PSINCDEC_in == 0) begin + ps_cnt_neg = (-1) * ps_cnt; + ps_in_ps_neg = (-1) * ps_in_ps; + if (ps_cnt_neg < ps_max) + ps_cnt <= ps_cnt - 1; + else + ps_cnt <= 0; + + if (ps_in_ps_neg < ps_max) + ps_in_ps <= ps_in_ps - 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + end + else + psen_w <= 0; + + if ( PSDONE == 1'b1) + ps_lock <= 0; + end + + always @(posedge ps_lock) + if (fps_en == 1) begin + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + begin + PSDONE_out = 1'b1; + @(posedge PSCLK_in); + PSDONE_out = 1'b0; + end + end + + always @(rst_clkinstopped) + if (rst_clkinstopped) begin + assign clkfbout_frac_ht = 50; + assign clkfbout_frac_lt = 50; + assign clkfbout_frac_ht_rl = 50.0; + assign clkfbout_frac_lt_rl = 50.0; + end + else begin + deassign clkfbout_frac_ht; + deassign clkfbout_frac_lt; + deassign clkfbout_frac_ht_rl; + deassign clkfbout_frac_lt_rl; + end + + integer clk0_delay, clk1_delay, clk2_delay, clk3_delay, clk4_delay, clk5_delay, clk6_delay, clkfbout_delay; + integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next; + always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps); + always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps); + always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps); + always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps); + always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps); + always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps); + always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps); + always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps); + + always @ (posedge clkvco) begin + if (ps_lock) begin + if ((period_ps - period_ps_old) > period_vco/2) + ps_wr_to_max <= 1'b1; + else + ps_wr_to_max <= 1'b0; + end + period_ps_old = period_ps; + clk0_delay <= clk0_delay_next; + clk1_delay <= clk1_delay_next; + clk2_delay <= clk2_delay_next; + clk3_delay <= clk3_delay_next; + clk4_delay <= clk4_delay_next; + clk5_delay <= clk5_delay_next; + clk6_delay <= clk6_delay_next; + clkfbout_delay <= clkfbout_delay_next; + end + + always @ (clkvco) begin + if (clkout_en && clk0_en) + if (clk0_delay == 0) clk0in = clkvco; + else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin + clk0in <= #(clk0_delay - period_ps) 1'b0; + clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1; + clk0in <= #(clk0_delay) 1'b0; + end else begin + clk0in <= #clk0_delay clkvco; + end + else clk0in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk1_en) + if (clk1_delay == 0) clk1in = clkvco; + else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin + clk1in <= #(clk1_delay - period_ps) 1'b0; + clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1; + clk1in <= #(clk1_delay) 1'b0; + end else begin + clk1in <= #clk1_delay clkvco; + end + else clk1in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk2_en) + if (clk2_delay == 0) clk2in = clkvco; + else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin + clk2in <= #(clk2_delay - period_ps) 1'b0; + clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1; + clk2in <= #(clk2_delay) 1'b0; + end else begin + clk2in <= #clk2_delay clkvco; + end + else clk2in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk3_en) + if (clk3_delay == 0) clk3in = clkvco; + else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin + clk3in <= #(clk3_delay - period_ps) 1'b0; + clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1; + clk3in <= #(clk3_delay) 1'b0; + end else begin + clk3in <= #clk3_delay clkvco; + end + else clk3in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk4_en) + if (CLKOUT4_CASCADE_BIN == CLKOUT4_CASCADE_TRUE) clk4in = clk6_out; + else if (clk4_delay == 0) clk4in = clkvco; + else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin + clk4in <= #(clk4_delay - period_ps) 1'b0; + clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1; + clk4in <= #(clk4_delay) 1'b0; + end else begin + clk4in <= #clk4_delay clkvco; + end + else clk4in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk5_en) + if (clk5_delay == 0) clk5in = clkvco; + else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin + clk5in <= #(clk5_delay - period_ps) 1'b0; + clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1; + clk5in <= #(clk5_delay) 1'b0; + end else begin + clk5in <= #clk5_delay clkvco; + end + else clk5in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk6_en) + if (clk6_delay == 0) clk6in = clkvco; + else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin + clk6in <= #(clk6_delay - period_ps) 1'b0; + clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1; + clk6in <= #(clk6_delay) 1'b0; + end else begin + clk6in <= #clk6_delay clkvco; + end + else clk6in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clkfbout_en) + if (clkfbout_delay == 0) clkfboutin = clkvco; + else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin + clkfboutin <= #(clkfbout_delay - period_ps) 1'b0; + clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1; + clkfboutin <= #(clkfbout_delay) 1'b0; + end else begin + clkfboutin <= #clkfbout_delay clkvco; + end + else clkfboutin = 1'b0; + end + + + assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en; + assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en; + assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en; + assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en; + assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en; + assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en; + assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en; + assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en; + + always @(negedge clk0in or posedge rst_in_o) + if (rst_in_o) + clk0_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk0_dly_cnt < clk0_dt) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in_o) + if (rst_in_o) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clk1_dt && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in_o) + if (rst_in_o) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clk2_dt && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in_o) + if (rst_in_o) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clk3_dt && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in_o) + if (rst_in_o) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clk4_dt && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in_o) + if (rst_in_o) + clk5_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk5_dly_cnt < clk5_dt) + clk5_dly_cnt <= clk5_dly_cnt + 1; + end + + always @(negedge clk6in or posedge rst_in_o) + if (rst_in_o) + clk6_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk6_dly_cnt < clk6_dt) + clk6_dly_cnt <= clk6_dly_cnt + 1; + end + + always @(negedge clkfboutin or posedge rst_in_o) + if (rst_in_o) + clkfbout_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clkfbout_dly_cnt < clkfbout_dt) + clkfbout_dly_cnt <= clkfbout_dly_cnt + 1; + end + + always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o) + if (rst_in_o || ~clkfbps_en) begin + clkfbout_cnt <= 8'b0; + clkfbout_out = 0; + end + else if (clkfbout_nc) clkfbout_out = ~clkfbout_out; + else if (~clkfbout_frac_en) begin + if (clkfbout_cnt < clkfbout_cnt_max) + clkfbout_cnt <= clkfbout_cnt + 1; + else + clkfbout_cnt <= 8'b0; + if (clkfbout_cnt < clkfbout_cnt_ht) + clkfbout_out = 1; + else + clkfbout_out = 0; + end + else if (clkfbout_frac_en && clkfboutin) begin + clkfbout_out = 1; + clkfbout_frac_rm_rl = 0.0; + clkfbout_frac_rm = 0; + for (ib=1; ib < 8; ib=ib+1) begin + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_ht_rl - clkfbout_frac_ht - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_ht + clkfbout_frac_rm) clkfbout_out = 0; + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_lt_rl - clkfbout_frac_lt - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_lt + clkfbout_frac_rm) clkfbout_out = 1; + end + #(clkfbout_frac_ht) clkfbout_out = 0; + #(clkfbout_frac_lt - period_vco1); + end + + always @(posedge clk0in or negedge clk0in or posedge rst_in_o) + if (rst_in_o || ~clk0ps_en) begin + clk0_cnt <= 8'b0; + clk0_out = 0; + end + else if (clk0_nc) clk0_out = ~clk0_out; + else if (~clk0_frac_en) begin + if (clk0_cnt < clk0_cnt_max) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + if (clk0_cnt < clk0_cnt_ht) + clk0_out = 1; + else + clk0_out = 0; + end + else if (clk0_frac_en && clk0in) begin + clk0_out = 1; + clk0_frac_rm_rl = 0.0; + clk0_frac_rm = 0; + for (ik0=1; ik0 < 8; ik0=ik0+1) begin + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_ht_rl - clk0_frac_ht - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_ht + clk0_frac_rm) clk0_out = 0; + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_lt_rl - clk0_frac_lt - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_lt + clk0_frac_rm) clk0_out = 1; + end + #(clk0_frac_ht) clk0_out = 0; + #(clk0_frac_lt - period_vco1); + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in_o) + if (rst_in_o || ~clk1ps_en) begin + clk1_cnt <= 8'b0; + clk1_out = 0; + end + else if (clk1_nc) clk1_out = ~clk1_out; + else begin + if (clk1_cnt < clk1_cnt_max) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + if (clk1_cnt < clk1_cnt_ht) + clk1_out = 1; + else + clk1_out = 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in_o) + if (rst_in_o || ~clk2ps_en) begin + clk2_cnt <= 8'b0; + clk2_out = 0; + end + else if (clk2_nc) clk2_out = ~clk2_out; + else begin + if (clk2_cnt < clk2_cnt_max) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + if (clk2_cnt < clk2_cnt_ht) + clk2_out = 1; + else + clk2_out = 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in_o) + if (rst_in_o || ~clk3ps_en) begin + clk3_cnt <= 8'b0; + clk3_out = 0; + end + else if (clk3_nc) clk3_out = ~clk3_out; + else begin + if (clk3_cnt < clk3_cnt_max) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + if (clk3_cnt < clk3_cnt_ht) + clk3_out = 1; + else + clk3_out = 0; + end + + always @(posedge clk4in or negedge clk4in or posedge rst_in_o) + if (rst_in_o || ~clk4ps_en) begin + clk4_cnt <= 8'b0; + clk4_out = 0; + end + else if (clk4_nc) clk4_out = ~clk4_out; + else begin + if (clk4_cnt < clk4_cnt_max) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + if (clk4_cnt < clk4_cnt_ht) + clk4_out = 1; + else + clk4_out = 0; + end + + always @(posedge clk5in or negedge clk5in or posedge rst_in_o) + if (rst_in_o || ~clk5ps_en) begin + clk5_cnt <= 8'b0; + clk5_out = 0; + end + else if (clk5_nc) clk5_out = ~clk5_out; + else begin + if (clk5_cnt < clk5_cnt_max) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + if (clk5_cnt < clk5_cnt_ht) + clk5_out = 1; + else + clk5_out = 0; + end + + always @(posedge clk6in or negedge clk6in or posedge rst_in_o) + if (rst_in_o || ~clk6ps_en) begin + clk6_cnt <= 8'b0; + clk6_out = 0; + end + else if (clk6_nc) clk6_out = ~clk6_out; + else begin + if (clk6_cnt < clk6_cnt_max) + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 8'b0; + if (clk6_cnt < clk6_cnt_ht) + clk6_out = 1; + else + clk6_out = 0; + end + + + always @(clk0_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT0_out = clk0_out; + CLKOUT0B_out = ~clk0_out; + end else begin + CLKOUT0_out = clkfbout_tst; + CLKOUT0B_out = ~clkfbout_tst; + end + + always @(clk1_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT1_out = clk1_out; + CLKOUT1B_out = ~clk1_out; + end else begin + CLKOUT1_out = clkfbout_tst; + CLKOUT1B_out = ~clkfbout_tst; + end + + always @(clk2_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT2_out = clk2_out; + CLKOUT2B_out = ~clk2_out; + end else begin + CLKOUT2_out = clkfbout_tst; + CLKOUT2B_out = ~clkfbout_tst; + end + + always @(clk3_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT3_out = clk3_out; + CLKOUT3B_out = ~clk3_out; + end else begin + CLKOUT3_out = clkfbout_tst; + CLKOUT3B_out = ~clkfbout_tst; + end + + always @(clk4_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT4_out = clk4_out; + end else begin + CLKOUT4_out = clkfbout_tst; + end + + always @(clk5_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT5_out = clk5_out; + end else begin + CLKOUT5_out = clkfbout_tst; + end + + always @(clk6_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT6_out = clk6_out; + end else begin + CLKOUT6_out = clkfbout_tst; + end + + always @(clkfbout_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) + begin + CLKFBOUT_out = clkfbout_out; + CLKFBOUTB_out = ~clkfbout_out; + end + else + begin + CLKFBOUT_out = clkfbout_tst; + CLKFBOUTB_out = ~clkfbout_tst; + end + + // + // determine feedback delay + // + + + always @(posedge clkpll_r ) + if (fb_delay_found) clkfbout_tst = 1'b0; + else clkfbout_tst = ~clkfbout_tst; + + always @( posedge clkfbout_tst ) + delay_edge = $time; + + assign clkfbin_sel = ((COMPENSATION_BIN == COMPENSATION_INTERNAL) || + ((COMPENSATION_BIN == COMPENSATION_AUTO) && (CLKFBIN === 1'bz))); + + assign CLKFBIN_int = clkfbin_sel && CLKFBOUT_out || ~clkfbin_sel && CLKFBIN_in; + + always @(posedge CLKFBIN_int ) + if (fb_delay_found_tmp == 0 ) begin + if ( delay_edge != 0) begin + fb_delay <= ($time - delay_edge); + fb_delay_found_tmp <= 1; + end else begin + fb_delay <= 0; + fb_delay_found_tmp <= 0; + end + end + + always @(negedge clkfbout_tst or negedge fb_delay_found_tmp) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay or fb_delay_found) + if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); + end + + // + // generate unlock signal + // + + always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc; + always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc; + + always @(posedge clkpll_r or negedge clkpll_r) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int) begin + clkfbin_p <= 1; + clkfbin_p <= #100 0; + end + + always @(posedge clkin_osc or posedge rst_int or posedge clkin_p) + if ((rst_int == 1) || (LOCKED == 1'b0)) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out1 == 1) begin + @(posedge clkpll_r) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out1 <= 0; + end + else + clkinstopped_out1 <= 1; + end + + always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p) + if (rst_int == 1 || clkfbin_p == 1) begin + clkfbstopped_out1 <= 0; + clkfbin_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfbin_lost_cnt < clkfbin_lost_val) begin + clkfbin_lost_cnt <= clkfbin_lost_cnt + 1; + clkfbstopped_out1 <= 0; + end + else + clkfbstopped_out1 <= 1; + end + + + always @(clkin_jit or rst_int ) + if (rst_int) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // tasks +task mc_to_attr; + input [160:1] clkout_name; + input [2:0] pm_f; + input wf_f; + input [2:0] frac; + input frac_en; + input wf_r; + input [1:0] mx; + input e; + input nc; + input [5:0] dt; + input [2:0] pm_r; + input en; + input [5:0] ht; + input [5:0] lt; + output real div; + output real phase; + output real duty; + + integer odd_frac; + reg odd; + real frac_r; + integer div_2; + integer pm_f_c; + real duty_step; + real phase_step; + +begin + +if (nc == 1'b1) begin + div = 1.0; + duty = 0.5; +end +else if (frac_en == 1'b1) begin + duty =0.50; + + if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f; + else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r; + else pm_f_c = 8 + pm_f - pm_r; + + if (pm_f_c < 4) begin + odd = 1'b0; + odd_frac = frac; + end + else begin + odd = 1'b1; + odd_frac = frac + 8; + end + + frac_r = frac * 0.125; + + if (odd_frac > 9) div_2 = lt; + else div_2 = lt + 1; + + div = 2.0 * div_2 + 1.0 * odd + frac_r; + +end +else begin + + if (ht == 6'b0 && lt == 6'b0) div = 128.0; + else if (ht == 6'b0) div = 64.0 + lt * 1.0; + else if (lt == 6'b0) div = ht * 1.0 + 64.0; + else div = ht * 1.0 + lt * 1.0; + + duty_step = 0.5 / div; + + duty = (2.0 * ht + e) * duty_step; + +end + + phase_step = 360.0 / (div * 8.0); + phase = phase_step * (dt*8.0 + pm_r*1.0); + +end +endtask + +task upper_mix_drp; + output reg [2:0] pm_f; + output reg wf_f; + output reg cddc_en; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + pm_f = DI[15:13]; + wf_f = DI[12]; + cddc_en = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_frac_drp; + output reg cddc_en; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + cddc_en = DI[15]; + frac = DI[14:12]; + frac_en = DI[11]; + wf_r = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_drp; + output reg cddc_en; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + cddc_en = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task lower_drp; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input [15:0] DI; +begin + pm_r = DI[15:13]; + en = DI[12]; + ht = DI[11:6]; + lt = DI[5:0]; +end +endtask + +//ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div) +task ht_calc; + input [2:0] frac; + input frac_en; + input e; + input [5:0] ht; + input [6:0] lt; + input real f_div; + output [3:0] clk_rsel; + output [3:0] clk_fsel; + output [6:0] clk_fht; + output [6:0] clk_flt; + output integer clk_cnt_max; + output integer clk_cnt_ht; + output integer clk_div_fint; + + integer clk_div_fint_odd; +begin + clk_div_fint = $rtoi(f_div); + if (frac_en) begin + clk_fht = clk_div_fint / 2; + clk_flt = clk_div_fint / 2; + clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt; + if (clk_div_fint_odd > 0) begin + clk_rsel = (8 + frac) / 2; + clk_fsel = 8 + frac - clk_rsel; + end + else begin + clk_rsel = frac / 2; + clk_fsel = frac - clk_rsel; + end + end + else begin + if (ht == 6'b0) clk_fht = 64; else clk_fht = ht; + if (lt == 7'b0) clk_flt = 64; else clk_flt = lt; + clk_cnt_max = 2 * (clk_fht + clk_flt) - 1; + clk_cnt_ht = 2 * clk_fht + e; + end + +end +endtask + +task attr_to_mc; + output reg [2:0] pm_f; + output reg wf_f; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input real div; + input real phase; + input real duty; + + integer div_int; + real div_frac; + real div_rnd; + + reg [37:0] vector; +begin + +// determine frac_en + div_int = $rtoi(div); + div_frac = div - $itor(div_int); + if (div_frac > 0.000) frac_en = 1'b1; + else frac_en = 1'b0; + +// rnd frac to nearest 0.125 - may become .000 + div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0; + +// determine int and frac part + div_int = $rtoi(div_rnd); + div_frac = div_rnd - $itor(div_int); + + if (frac_en == 1'b1) + vector = mmcm_frac_calc(div_int,phase*1000,duty*100000,div_frac*1000); + else + vector = mmcm_calc(div_int,phase*1000,duty*100000); + + if (frac_en == 1'b1) begin + pm_f = vector[35:33]; + wf_f = vector[32]; + frac = vector[30:28]; + frac_en = vector[27]; + wf_r = vector[26]; + end + else begin + pm_f = 3'b0; + wf_f = 1'b0; + frac = 3'b0; + frac_en = 1'b0; + wf_r = 1'b0; + end + mx = vector[25:24]; + e = vector[23]; + en = 1'b1; + if (div_int == 1) begin + nc = 1'b1; + ht = 6'b1; + lt = 6'b1; + end else begin + nc = vector[22]; + ht = vector[11:6]; + lt = vector[5:0]; + end + dt = vector[21:16]; + pm_r = vector[15:13]; +end +endtask + +`define MMCME3_ADV_FRAC_PRECISION 10 +`define MMCME3_ADV_FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`MMCME3_ADV_FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`MMCME3_ADV_FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`MMCME3_ADV_FIXED_WIDTH:1] precision + ); + + begin + + // If the fractional precision bit is high then round up + if( decimal[(`MMCME3_ADV_FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`MMCME3_ADV_FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`MMCME3_ADV_FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`MMCME3_ADV_FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `MMCME3_ADV_FRAC_PRECISION) / 100_000; + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + // comes from above round_frac + high_time = temp[`MMCME3_ADV_FRAC_PRECISION+7:`MMCME3_ADV_FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`MMCME3_ADV_FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`MMCME3_ADV_FIXED_WIDTH:1] phase_in_cycles; + reg [`MMCME3_ADV_FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`MMCME3_ADV_FIXED_WIDTH:1] temp; + + begin + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `MMCME3_ADV_FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `MMCME3_ADV_FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`MMCME3_ADV_FRAC_PRECISION:`MMCME3_ADV_FRAC_PRECISION-2]; + delay_time = temp[`MMCME3_ADV_FRAC_PRECISION+6:`MMCME3_ADV_FRAC_PRECISION+1]; + + // Setup the return value + mmcm_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + mmcm_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); +// $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_divider(divide, duty_cycle); //Not used since edge and no count are 0 when fractional + phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + end +endfunction + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_CHK = 1.0; + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + $display(" Instance %m "); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + integer para_in; + integer range_low; + integer range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; + end + endfunction + + function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + real para_in; + real range_low; + real range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_real_range_chk = 1'b0; + end + endfunction + + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (CLKIN1 => LOCKED) = (100:100:100, 100:100:100); + (CLKIN2 => LOCKED) = (100:100:100, 100:100:100); + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (PSCLK => PSDONE) = (100:100:100, 100:100:100); + (PWRDWN => CLKFBSTOPPED) = (0:0:0, 0:0:0); + (PWRDWN => CLKINSTOPPED) = (0:0:0, 0:0:0); + (PWRDWN => LOCKED) = (100:100:100, 100:100:100); + (negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKFBOUTB, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKIN2, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT2B, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT3B, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge CLKOUT6, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge PSCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKFBOUTB, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKIN2, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT2B, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT3B, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge CLKOUT6, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge PSCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge CLKIN2, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PSCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge CLKIN2, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PSCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME3_BASE.v b/verilog/src/unisims/MMCME3_BASE.v new file mode 100644 index 0000000..9a38a98 --- /dev/null +++ b/verilog/src/unisims/MMCME3_BASE.v @@ -0,0 +1,297 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Base Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME3_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME3_BASE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKFBOUTB, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output LOCKED, + + input CLKFBIN, + input CLKIN1, + input PWRDWN, + input RST +); + +// define constants + localparam MODULE_NAME = "MMCME3_BASE"; + + reg trig_attr = 1'b0; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + + wire CLKFBIN_in; + wire CLKIN1_in; + wire PWRDWN_in; + wire RST_in; + + assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0 + assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0 + assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0 + + initial begin + #1; + trig_attr = ~trig_attr; + end + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + +end +`endif + +`ifndef XIL_XECLIB + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end +`endif + + wire CDDCDONE; + wire DRDY; + wire PSDONE; + wire CLKFBSTOPPED; + wire CLKINSTOPPED; + wire [15:0] DO; + MMCME3_ADV #( + .BANDWIDTH(BANDWIDTH), + .CLKFBOUT_MULT_F(CLKFBOUT_MULT_F), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN1_PERIOD), + .CLKIN2_PERIOD(10), + .CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_CASCADE(CLKOUT4_CASCADE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .CLKOUT6_DIVIDE(CLKOUT6_DIVIDE), + .CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE), + .CLKOUT6_PHASE(CLKOUT6_PHASE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .REF_JITTER1(REF_JITTER1), + .STARTUP_WAIT(STARTUP_WAIT) + ) mmcm_adv_1 ( + .CDDCDONE (CDDCDONE), + .CLKFBOUT (CLKFBOUT), + .CLKFBOUTB (CLKFBOUTB), + .CLKFBSTOPPED(CLKFBSTOPPED), + .CLKINSTOPPED(CLKINSTOPPED), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUT2 (CLKOUT2), + .CLKOUT2B (CLKOUT2B), + .CLKOUT3 (CLKOUT3), + .CLKOUT3B (CLKOUT3B), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .CLKOUT6 (CLKOUT6), + .DO (DO), + .DRDY (DRDY), + .LOCKED (LOCKED), + .PSDONE(PSDONE), + .CDDCREQ (1'b0), + .CLKFBIN (CLKFBIN_in), + .CLKIN1 (CLKIN1_in), + .CLKIN2 (1'b0), + .CLKINSEL(1'b1), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(PWRDWN_in), + .RST (RST_in) + ); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKFBOUTB, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT2B, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT3B, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge CLKOUT6, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKFBOUTB, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT2B, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT3B, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge CLKOUT6, 0:0:0, notifier); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME4_ADV.v b/verilog/src/unisims/MMCME4_ADV.v new file mode 100644 index 0000000..c1fa346 --- /dev/null +++ b/verilog/src/unisims/MMCME4_ADV.v @@ -0,0 +1,4322 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME4_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/21/2013 - YML changes +// 03/22/2013 - 708090 - Change error to Warning +// 03/27/2013 - Update with writer notation +// 04/04/2013 - 709484 - Add PFD check +// 04/04/2013 - 709093 - Fix periods after DRP +// 04/12/2013 - invertible pin changes +// 04/22/2013 - 713991 - Fix cddcdone assertion +// 04/24/2013 - 709726 - fix vcoflag +// 05/07/2013 - 714319 - fix phase warning +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME4_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 10.000, + parameter real CLKPFD_FREQ_MAX = 550.000, + parameter real CLKPFD_FREQ_MIN = 10.000, + parameter real VCOCLK_FREQ_MAX = 1600.000, + parameter real VCOCLK_FREQ_MIN = 800.000, +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter CLKFBOUT_USE_FINE_PS = "FALSE", + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKIN2_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter CLKOUT0_USE_FINE_PS = "FALSE", + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUT1_USE_FINE_PS = "FALSE", + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter CLKOUT2_USE_FINE_PS = "FALSE", + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT3_USE_FINE_PS = "FALSE", + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter CLKOUT4_USE_FINE_PS = "FALSE", + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter CLKOUT5_USE_FINE_PS = "FALSE", + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter CLKOUT6_USE_FINE_PS = "FALSE", + parameter COMPENSATION = "AUTO", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0, + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, + parameter [0:0] IS_PSEN_INVERTED = 1'b0, + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter real REF_JITTER2 = 0.010, + parameter SS_EN = "FALSE", + parameter SS_MODE = "CENTER_HIGH", + parameter integer SS_MOD_PERIOD = 10000, + parameter STARTUP_WAIT = "FALSE" +)( + output CDDCDONE, + output CLKFBOUT, + output CLKFBOUTB, + output CLKFBSTOPPED, + output CLKINSTOPPED, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output [15:0] DO, + output DRDY, + output LOCKED, + output PSDONE, + + input CDDCREQ, + input CLKFBIN, + input CLKIN1, + input CLKIN2, + input CLKINSEL, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PSCLK, + input PSEN, + input PSINCDEC, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 10.000; + localparam real CLKPFD_FREQ_MAX = 550.000; + localparam real CLKPFD_FREQ_MIN = 10.000; + localparam real VCOCLK_FREQ_MAX = 1600.000; + localparam real VCOCLK_FREQ_MIN = 800.000; +`endif + +// define constants + localparam MODULE_NAME = "MMCME4_ADV"; + +// Parameter encodings and registers + localparam BANDWIDTH_HIGH = 1; + localparam BANDWIDTH_LOW = 2; + localparam BANDWIDTH_OPTIMIZED = 0; + localparam CLKFBOUT_USE_FINE_PS_FALSE = 0; + localparam CLKFBOUT_USE_FINE_PS_TRUE = 1; + localparam CLKOUT0_USE_FINE_PS_FALSE = 0; + localparam CLKOUT0_USE_FINE_PS_TRUE = 1; + localparam CLKOUT1_USE_FINE_PS_FALSE = 0; + localparam CLKOUT1_USE_FINE_PS_TRUE = 1; + localparam CLKOUT2_USE_FINE_PS_FALSE = 0; + localparam CLKOUT2_USE_FINE_PS_TRUE = 1; + localparam CLKOUT3_USE_FINE_PS_FALSE = 0; + localparam CLKOUT3_USE_FINE_PS_TRUE = 1; + localparam CLKOUT4_CASCADE_FALSE = 0; + localparam CLKOUT4_CASCADE_TRUE = 1; + localparam CLKOUT4_USE_FINE_PS_FALSE = 0; + localparam CLKOUT4_USE_FINE_PS_TRUE = 1; + localparam CLKOUT5_USE_FINE_PS_FALSE = 0; + localparam CLKOUT5_USE_FINE_PS_TRUE = 1; + localparam CLKOUT6_USE_FINE_PS_FALSE = 0; + localparam CLKOUT6_USE_FINE_PS_TRUE = 1; + localparam COMPENSATION_AUTO = 0; + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_EXTERNAL = 2; + localparam COMPENSATION_INTERNAL = 3; + localparam COMPENSATION_ZHOLD = 4; + localparam SS_EN_FALSE = 0; + localparam SS_EN_TRUE = 1; + localparam SS_MODE_CENTER_HIGH = 0; + localparam SS_MODE_CENTER_LOW = 1; + localparam SS_MODE_DOWN_HIGH = 2; + localparam SS_MODE_DOWN_LOW = 3; + localparam STARTUP_WAIT_FALSE = 0; + localparam STARTUP_WAIT_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "MMCME4_ADV_dr.v" +`else + localparam [72:1] BANDWIDTH_REG = BANDWIDTH; + localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F; + localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; + localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS; + localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD; + localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD; + localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; + localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; + localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F; + localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; + localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; + localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS; + localparam [31:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; + localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; + localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; + localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS; + localparam [31:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE; + localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE; + localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE; + localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS; + localparam [31:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE; + localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE; + localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE; + localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS; + localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE; + localparam [31:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE; + localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE; + localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE; + localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS; + localparam [31:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE; + localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE; + localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE; + localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS; + localparam [31:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE; + localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE; + localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE; + localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS; + localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; + localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; + localparam [64:1] COMPENSATION_REG = COMPENSATION; + localparam [31:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED; + localparam [0:0] IS_CLKIN2_INVERTED_REG = IS_CLKIN2_INVERTED; + localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED; + localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED; + localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REF_JITTER1_REG = REF_JITTER1; + localparam real REF_JITTER2_REG = REF_JITTER2; + localparam [40:1] SS_EN_REG = SS_EN; + localparam [88:1] SS_MODE_REG = SS_MODE; + localparam [31:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD; + localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; + localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; + localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; +`endif + +`ifdef XIL_XECLIB + wire [1:0] BANDWIDTH_BIN; + wire [63:0] CLKFBOUT_MULT_F_BIN; + wire [63:0] CLKFBOUT_PHASE_BIN; + wire CLKFBOUT_USE_FINE_PS_BIN; + wire [63:0] CLKIN1_PERIOD_BIN; + wire [63:0] CLKIN2_PERIOD_BIN; + wire [63:0] CLKIN_FREQ_MAX_BIN; + wire [63:0] CLKIN_FREQ_MIN_BIN; + wire [63:0] CLKOUT0_DIVIDE_F_BIN; + wire [63:0] CLKOUT0_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT0_PHASE_BIN; + wire CLKOUT0_USE_FINE_PS_BIN; + wire [7:0] CLKOUT1_DIVIDE_BIN; + wire [63:0] CLKOUT1_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT1_PHASE_BIN; + wire CLKOUT1_USE_FINE_PS_BIN; + wire [7:0] CLKOUT2_DIVIDE_BIN; + wire [63:0] CLKOUT2_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT2_PHASE_BIN; + wire CLKOUT2_USE_FINE_PS_BIN; + wire [7:0] CLKOUT3_DIVIDE_BIN; + wire [63:0] CLKOUT3_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT3_PHASE_BIN; + wire CLKOUT3_USE_FINE_PS_BIN; + wire CLKOUT4_CASCADE_BIN; + wire [7:0] CLKOUT4_DIVIDE_BIN; + wire [63:0] CLKOUT4_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT4_PHASE_BIN; + wire CLKOUT4_USE_FINE_PS_BIN; + wire [7:0] CLKOUT5_DIVIDE_BIN; + wire [63:0] CLKOUT5_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT5_PHASE_BIN; + wire CLKOUT5_USE_FINE_PS_BIN; + wire [7:0] CLKOUT6_DIVIDE_BIN; + wire [63:0] CLKOUT6_DUTY_CYCLE_BIN; + wire [63:0] CLKOUT6_PHASE_BIN; + wire CLKOUT6_USE_FINE_PS_BIN; + wire [63:0] CLKPFD_FREQ_MAX_BIN; + wire [63:0] CLKPFD_FREQ_MIN_BIN; + wire [2:0] COMPENSATION_BIN; + wire [6:0] DIVCLK_DIVIDE_BIN; + wire [63:0] REF_JITTER1_BIN; + wire [63:0] REF_JITTER2_BIN; + wire SS_EN_BIN; + wire [1:0] SS_MODE_BIN; + wire [15:0] SS_MOD_PERIOD_BIN; + wire STARTUP_WAIT_BIN; + wire [63:0] VCOCLK_FREQ_MAX_BIN; + wire [63:0] VCOCLK_FREQ_MIN_BIN; +`else + reg [1:0] BANDWIDTH_BIN; + reg [63:0] CLKFBOUT_MULT_F_BIN; + reg [63:0] CLKFBOUT_PHASE_BIN; + reg CLKFBOUT_USE_FINE_PS_BIN; + reg [63:0] CLKIN1_PERIOD_BIN; + reg [63:0] CLKIN2_PERIOD_BIN; + reg [63:0] CLKIN_FREQ_MAX_BIN; + reg [63:0] CLKIN_FREQ_MIN_BIN; + reg [63:0] CLKOUT0_DIVIDE_F_BIN; + reg [63:0] CLKOUT0_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT0_PHASE_BIN; + reg CLKOUT0_USE_FINE_PS_BIN; + reg [7:0] CLKOUT1_DIVIDE_BIN; + reg [63:0] CLKOUT1_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT1_PHASE_BIN; + reg CLKOUT1_USE_FINE_PS_BIN; + reg [7:0] CLKOUT2_DIVIDE_BIN; + reg [63:0] CLKOUT2_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT2_PHASE_BIN; + reg CLKOUT2_USE_FINE_PS_BIN; + reg [7:0] CLKOUT3_DIVIDE_BIN; + reg [63:0] CLKOUT3_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT3_PHASE_BIN; + reg CLKOUT3_USE_FINE_PS_BIN; + reg CLKOUT4_CASCADE_BIN; + reg [7:0] CLKOUT4_DIVIDE_BIN; + reg [63:0] CLKOUT4_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT4_PHASE_BIN; + reg CLKOUT4_USE_FINE_PS_BIN; + reg [7:0] CLKOUT5_DIVIDE_BIN; + reg [63:0] CLKOUT5_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT5_PHASE_BIN; + reg CLKOUT5_USE_FINE_PS_BIN; + reg [7:0] CLKOUT6_DIVIDE_BIN; + reg [63:0] CLKOUT6_DUTY_CYCLE_BIN; + reg [63:0] CLKOUT6_PHASE_BIN; + reg CLKOUT6_USE_FINE_PS_BIN; + reg [63:0] CLKPFD_FREQ_MAX_BIN; + reg [63:0] CLKPFD_FREQ_MIN_BIN; + reg [2:0] COMPENSATION_BIN; + reg [6:0] DIVCLK_DIVIDE_BIN; + reg [63:0] REF_JITTER1_BIN; + reg [63:0] REF_JITTER2_BIN; + reg SS_EN_BIN; + reg [1:0] SS_MODE_BIN; + reg [15:0] SS_MOD_PERIOD_BIN; + reg STARTUP_WAIT_BIN; + reg [63:0] VCOCLK_FREQ_MAX_BIN; + reg [63:0] VCOCLK_FREQ_MIN_BIN; +`endif + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire CDDCREQ_in; + wire CLKFBIN_in; + wire CLKIN1_in; + wire CLKIN2_in; + wire CLKINSEL_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire PSCLK_in; + wire PSEN_in; + wire PSINCDEC_in; + wire PWRDWN_in; + wire RST_in; + wire [15:0] DI_in; + wire [6:0] DADDR_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire PSCLK_delay; + wire PSEN_delay; + wire PSINCDEC_delay; + wire [15:0] DI_delay; + wire [6:0] DADDR_delay; +`endif + +`ifdef XIL_TIMING + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`else + assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0 + assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0 + assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0 + assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0 + assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0 + assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0 + assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0 + assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0 + assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0 + assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0 + assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0 + assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0 + assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0 + assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0 + assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0 + assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0 + assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0 + assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0 + assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0 + assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0 + assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0 + assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0 + assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0 + assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0 + assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0 + assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0 + assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0 + assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_REG); // rv 0 + assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_REG); // rv 0 +`endif + + assign CDDCREQ_in = (CDDCREQ !== 1'bz) && CDDCREQ; // rv 0 + assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0 + assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0 + assign CLKIN2_in = (CLKIN2 !== 1'bz) && (CLKIN2 ^ IS_CLKIN2_INVERTED_REG); // rv 0 + assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_REG); // rv 1 + assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0 + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + assign CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + assign CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + assign CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_FALSE; + + assign CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + assign CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + assign CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + assign CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + assign CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + assign CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + assign CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + assign CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_FALSE; + + assign CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + assign CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + assign CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + assign CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_FALSE; + + assign CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + assign CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + assign CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + assign CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_FALSE; + + assign CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + assign CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + assign CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + assign CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_FALSE; + + assign CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + assign CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + assign CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + assign CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + assign CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_FALSE; + + assign CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + assign CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + assign CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + assign CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_FALSE; + + assign CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + assign CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + assign CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + assign CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_FALSE; + + assign CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + assign CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + COMPENSATION_AUTO; + + assign DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + assign REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + assign REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + assign SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + assign SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + assign SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + assign STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + assign VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + assign VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + +`else + always @ (trig_attr) begin + #1; + BANDWIDTH_BIN = + (BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED : + (BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH : + (BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW : + BANDWIDTH_OPTIMIZED; + + CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000; + + CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000; + + CLKFBOUT_USE_FINE_PS_BIN = + (CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE : + (CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE : + CLKFBOUT_USE_FINE_PS_FALSE; + + CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000; + + CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000; + + CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000; + + CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000; + + CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000; + + CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000; + + CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000; + + CLKOUT0_USE_FINE_PS_BIN = + (CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE : + (CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE : + CLKOUT0_USE_FINE_PS_FALSE; + + CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0]; + + CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000; + + CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000; + + CLKOUT1_USE_FINE_PS_BIN = + (CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE : + (CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE : + CLKOUT1_USE_FINE_PS_FALSE; + + CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0]; + + CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000; + + CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000; + + CLKOUT2_USE_FINE_PS_BIN = + (CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE : + (CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE : + CLKOUT2_USE_FINE_PS_FALSE; + + CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0]; + + CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000; + + CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000; + + CLKOUT3_USE_FINE_PS_BIN = + (CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE : + (CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE : + CLKOUT3_USE_FINE_PS_FALSE; + + CLKOUT4_CASCADE_BIN = + (CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE : + (CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE : + CLKOUT4_CASCADE_FALSE; + + CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0]; + + CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000; + + CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000; + + CLKOUT4_USE_FINE_PS_BIN = + (CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE : + (CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE : + CLKOUT4_USE_FINE_PS_FALSE; + + CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0]; + + CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000; + + CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000; + + CLKOUT5_USE_FINE_PS_BIN = + (CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE : + (CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE : + CLKOUT5_USE_FINE_PS_FALSE; + + CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0]; + + CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000; + + CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000; + + CLKOUT6_USE_FINE_PS_BIN = + (CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE : + (CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE : + CLKOUT6_USE_FINE_PS_FALSE; + + CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000; + + CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000; + + COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + COMPENSATION_AUTO; + + DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0]; + + REF_JITTER1_BIN = REF_JITTER1_REG * 1000; + + REF_JITTER2_BIN = REF_JITTER2_REG * 1000; + + SS_EN_BIN = + (SS_EN_REG == "FALSE") ? SS_EN_FALSE : + (SS_EN_REG == "TRUE") ? SS_EN_TRUE : + SS_EN_FALSE; + + SS_MODE_BIN = + (SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH : + (SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW : + (SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH : + (SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW : + SS_MODE_CENTER_HIGH; + + SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0]; + + STARTUP_WAIT_BIN = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000; + + VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((BANDWIDTH_REG != "OPTIMIZED") && + (BANDWIDTH_REG != "HIGH") && + (BANDWIDTH_REG != "LOW"))) begin + $display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > 128.000)) begin + $display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to 128.000. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKFBOUT_USE_FINE_PS_REG != "FALSE") && + (CLKFBOUT_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin + $display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin + $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin + $display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT0_USE_FINE_PS_REG != "FALSE") && + (CLKOUT0_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_USE_FINE_PS_REG != "FALSE") && + (CLKOUT1_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT2_USE_FINE_PS_REG != "FALSE") && + (CLKOUT2_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT3_USE_FINE_PS_REG != "FALSE") && + (CLKOUT3_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_CASCADE_REG != "FALSE") && + (CLKOUT4_CASCADE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT4_USE_FINE_PS_REG != "FALSE") && + (CLKOUT4_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT5_USE_FINE_PS_REG != "FALSE") && + (CLKOUT5_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT6_USE_FINE_PS_REG != "FALSE") && + (CLKOUT6_USE_FINE_PS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin + $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin + $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((COMPENSATION_REG != "AUTO") && + (COMPENSATION_REG != "BUF_IN") && + (COMPENSATION_REG != "EXTERNAL") && + (COMPENSATION_REG != "INTERNAL") && + (COMPENSATION_REG != "ZHOLD"))) begin + $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are AUTO, BUF_IN, EXTERNAL, INTERNAL or ZHOLD. Instance: %m", MODULE_NAME, COMPENSATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin + $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin + $display("Error: [Unisim %s-150] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin + $display("Error: [Unisim %s-151] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_EN_REG != "FALSE") && + (SS_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-152] SS_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SS_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MODE_REG != "CENTER_HIGH") && + (SS_MODE_REG != "CENTER_LOW") && + (SS_MODE_REG != "DOWN_HIGH") && + (SS_MODE_REG != "DOWN_LOW"))) begin + $display("Error: [Unisim %s-153] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin + $display("Error: [Unisim %s-154] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_WAIT_REG != "FALSE") && + (STARTUP_WAIT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MAX_REG < 1600.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin + $display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1600.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MIN_REG < 800.000 || VCOCLK_FREQ_MIN_REG > 800.000)) begin + $display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute are 800.000 to 800.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg CDDCDONE_out; + reg CLKFBOUTB_out; + reg CLKFBOUT_out; + reg CLKFBSTOPPED_out; + reg CLKINSTOPPED_out; + reg CLKOUT0B_out; + reg CLKOUT0_out; + reg CLKOUT1B_out; + reg CLKOUT1_out; + reg CLKOUT2B_out; + reg CLKOUT2_out; + reg CLKOUT3B_out; + reg CLKOUT3_out; + reg CLKOUT4_out; + reg CLKOUT5_out; + reg CLKOUT6_out; + reg DRDY_out; + reg LOCKED_out; + reg PSDONE_out; + reg [15:0] DO_out; + + assign CDDCDONE = CDDCDONE_out; + assign CLKFBOUT = CLKFBOUT_out; + assign CLKFBOUTB = CLKFBOUTB_out; + assign CLKFBSTOPPED = CLKFBSTOPPED_out; + assign CLKINSTOPPED = CLKINSTOPPED_out; + assign CLKOUT0 = CLKOUT0_out; + assign CLKOUT0B = CLKOUT0B_out; + assign CLKOUT1 = CLKOUT1_out; + assign CLKOUT1B = CLKOUT1B_out; + assign CLKOUT2 = CLKOUT2_out; + assign CLKOUT2B = CLKOUT2B_out; + assign CLKOUT3 = CLKOUT3_out; + assign CLKOUT3B = CLKOUT3B_out; + assign CLKOUT4 = CLKOUT4_out; + assign CLKOUT5 = CLKOUT5_out; + assign CLKOUT6 = CLKOUT6_out; + assign DO = DO_out; + assign DRDY = DRDY_out; + assign LOCKED = LOCKED_out; + assign PSDONE = PSDONE_out; + + localparam VCOCLK_FREQ_TARGET = 1000; + localparam M_MIN = 2.000; + localparam M_MAX = 128.000; + localparam VF_MIN = 800.000; + localparam D_MIN = 1; + localparam D_MAX = 106; + localparam O_MIN = 1; + localparam O_MAX = 128; + localparam O_MAX_HT_LT = 64; + localparam REF_CLK_JITTER_MAX = 1000; + localparam REF_CLK_JITTER_SCALE = 0.1; + localparam MAX_FEEDBACK_DELAY = 5.0; + localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; + localparam ps_max = 55; + + integer nBandwidth_HIGH=0; + integer nBandwidth_LOW=1; + integer nBandwidth_OPTIMIZED=2; + + reg [160:1] clkout_name; + real CLKOUT0_DIVIDE_F_RND; + real CLKFBOUT_MULT_F_RND; + + tri1 p_up; + wire glock; + + integer pchk_tmp1, pchk_tmp2; + integer clkvco_div_fint; + real clkvco_div_frac; + reg clk0_out; + reg clkfbout_out; + integer clkvco_frac_en; + integer ps_in_init; + reg clk0_fps_en=0, clk1_fps_en=0, clk2_fps_en=0, clk3_fps_en=0; + reg clk4_fps_en=0, clk5_fps_en=0, clk6_fps_en=0, clkfbout_fps_en=0; + reg fps_en=1'b0, fps_clk_en=1'b0; + reg clkinstopped_out1; + reg clkin_hold_f = 0; + reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0; + integer period_avg_stpi = 0, period_avg_stp = 0; + real tmp_stp1, tmp_stp2; + reg pd_stp_p = 0; + reg vco_stp_f = 0; + reg psen_w = 0; + reg clkinstopped_out_dly = 0; + reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp; + reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; + reg rst_clkinstopped_rc = 0; + reg rst_clkinstopped_lk, rst_clkfbstopped_lk; + integer clkin_lost_cnt; + integer clkfbin_lost_cnt; + reg clkinstopped_hold = 0; + integer ps_in_ps, ps_cnt; + integer ps_in_ps_neg, ps_cnt_neg; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drp_lock; + integer drp_lock_lat = 4; + integer drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [160:0] tmp_string; + reg rst_int = 1'b0; + reg pwron_int; + wire rst_in_o; + reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out; + reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; + integer clkout_en_val, clkout_en_t; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + reg clkvco = 1'b0; + reg clkvco_lk_dly_tmp; + reg clkvco_lk_en; + reg clkvco_lk; + reg fbclk_tmp; + reg clkin_osc, clkin_p; + reg clkfbin_osc, clkfbin_p; + reg clkinstopped_vco_f; + time rst_edge, rst_ht; + reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0; + reg clkfbout_tst=1'b0; + real fb_delay_max; + time fb_delay=0, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay; + time dly_tmp1, tmp_ps_val2; + integer dly_tmp_int, tmp_ps_val1; + time clkin_edge, delay_edge; + real period_clkin, clkin_period_tmp; + integer clkin_period_tmp_t; + integer clkin_period [4:0]; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + real period_vco_rl, period_vco_rl_half; + integer period_vco_half_rm1, period_vco_half_rm2; + real cmpvco = 0.0; + real clkvco_pdrm; + integer period_vco_mf; + integer period_vco_tmp; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco_max, period_vco_min; + integer period_vco1, period_vco2, period_vco3, period_vco4; + integer period_vco5, period_vco6, period_vco7; + integer period_vco_target, period_vco_target_half; + integer period_fb=100000, period_avg=100000; + integer clk0_frac_lt, clk0_frac_ht; + real clk0_frac_lt_rl, clk0_frac_ht_rl; + integer clk0_frac_rm; + real clk0_frac_rm_rl; + integer clkfbout_frac_lt, clkfbout_frac_ht; + real clkfbout_frac_lt_rl, clkfbout_frac_ht_rl; + integer clkfbout_frac_rm; + real clkfbout_frac_rm_rl; + integer period_ps, period_ps_old; + reg ps_lock, ps_lock_dly; + real clkvco_freq_init_chk, clkfbout_pm_rl; + real tmp_real; + integer ik0, ik1, ik2, ik3, ik4, ib, i, j; + integer md_product, m_product, m_product2; + integer mf_product, clk0f_product; +// integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk; + integer clkin_lost_val; + integer clkfbin_lost_val; + time pll_locked_delay, clkin_dly_t, clkfbin_dly_t; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock; + integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + wire init_trig, clkpll_r; + reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0; + reg clk4in=1'b0,clk5in=1'b0,clk6in=1'b0; + reg clkpll_tmp1, clkpll; + reg clkfboutin=1'b0; + wire clkfbps_en; + reg chk_ok; + wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en; + wire clk4ps_en, clk5ps_en, clk6ps_en; + reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel; + reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel; + reg [6:0] d_fht, clkfbout_fht, clk0_fht; + reg [6:0] d_flt, clkfbout_flt, clk0_flt; + reg [5:0] clk0_dly_cnt; + reg [5:0] clk1_dly_cnt; + reg [5:0] clk2_dly_cnt; + reg [5:0] clk3_dly_cnt; + reg [5:0] clk4_dly_cnt; + reg [5:0] clk5_dly_cnt; + reg [5:0] clk6_dly_cnt; + real clk0_phase, clk0_duty; + real clk1_phase, clk1_duty; + real clk2_phase, clk2_duty; + real clk3_phase, clk3_duty; + real clk4_phase, clk4_duty; + real clk5_phase, clk5_duty; + real clk6_phase, clk6_duty; + real divclk_phase=0.000, divclk_duty=0.500; + real clkfbout_phase, clkfbout_duty=0.500; +// mem cells + reg [2:0] d_frac, clkfbout_frac, clk0_frac; + reg d_frac_en, clkfbout_frac_en, clk0_frac_en; + reg clk0_cddc_en=1'b0, clk1_cddc_en=1'b0, clk2_cddc_en=1'b0, clk3_cddc_en=1'b0, clk4_cddc_en=1'b0, clk5_cddc_en=1'b0, clk6_cddc_en=1'b0, clkfbout_cddc_res=1'b0; + reg d_wf_f; + reg clkfbout_wf_f, clk0_wf_f; + reg d_wf_r; + reg clkfbout_wf_r, clk0_wf_r; + reg [2:0] d_mx, clkfbout_mx; + reg [2:0] clk0_mx, clk1_mx, clk2_mx, clk3_mx; + reg [2:0] clk4_mx, clk5_mx, clk6_mx; + reg divclk_e, clkfbin_e; + reg clkfbout_e; + reg clk0_e, clk1_e, clk2_e, clk3_e; + reg clk4_e, clk5_e, clk6_e; + reg divclk_nc, clkfbin_nc; + reg clkfbout_nc; + reg clk0_nc, clk1_nc, clk2_nc, clk3_nc; + reg clk4_nc, clk5_nc, clk6_nc; + reg [5:0] d_dt=0, clkfbout_dt=0; + reg [5:0] clk0_dt=0, clk1_dt=0, clk2_dt=0, clk3_dt=0; + reg [5:0] clk4_dt=0, clk5_dt=0, clk6_dt=0; + reg [2:0] d_pm_f; + reg [2:0] clkfbout_pm_f, clk0_pm_f; + reg [2:0] clkfbout_pm_r, clk0_pm_r; + reg [2:0] d_pm; + reg [2:0] clk1_pm, clk2_pm, clk3_pm; + reg [2:0] clk4_pm, clk5_pm, clk6_pm; + reg divclk_en=1, clkfbout_en=1; + reg clk0_en=1, clk1_en=1, clk2_en=1, clk3_en=1; + reg clk4_en=1, clk5_en=1, clk6_en=1; + reg [5:0] clkfbin_ht; + reg [5:0] clkfbout_ht; + reg [7:0] divclk_ht; + reg [5:0] clk0_ht, clk1_ht, clk2_ht, clk3_ht; + reg [5:0] clk4_ht, clk5_ht, clk6_ht; + reg [5:0] clkfbin_lt; + reg [7:0] divclk_lt; + reg [6:0] clkfbout_lt; + reg [6:0] clk0_lt, clk1_lt, clk2_lt, clk3_lt; + reg [6:0] clk4_lt, clk5_lt, clk6_lt; +// + real clkfbout_f_div=1.0; + real clk0_f_div; + integer d_div, clkfbout_div, clk0_div; + reg [5:0] clkfbout_dly_cnt; + reg [7:0] clkfbout_cnt; + reg [7:0] clk0_cnt; + reg [7:0] clk1_cnt, clk1_div; + reg [7:0] clk2_cnt, clk2_div; + reg [7:0] clk3_cnt, clk3_div; + reg [7:0] clk4_cnt, clk4_div; + reg [7:0] clk5_cnt, clk5_div; + reg [7:0] clk6_cnt, clk6_div; + integer divclk_cnt_max, clkfbout_cnt_max; + integer clk0_cnt_max, clk1_cnt_max, clk2_cnt_max, clk3_cnt_max; + integer clk4_cnt_max, clk5_cnt_max, clk6_cnt_max; + integer divclk_cnt_ht, clkfbout_cnt_ht; + integer clk0_cnt_ht, clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht; + integer clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht; + reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0; + reg divclk_out, divclk_out_tmp; + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + wire clkinsel_tmp; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + real clkpfd_freq_init_chk; + reg init_chk; + reg rst_clkinsel_flag = 0; + wire CLKFBIN_int; + wire pwrdwn_in1; + reg pwrdwn_in1_h = 0; + reg rst_input_r_h = 0; + reg pchk_clr = 0; + reg psincdec_chg = 0; + reg psincdec_chg_tmp = 0; + wire rst_input; + wire clkfbin_sel; + reg vcoflag = 0; + reg drp_updt = 1'b0; + + real halfperiod_sum = 0.0; + integer halfperiod = 0; + reg clkvco_free = 1'b0; + integer ik10=0, ik11=0; + + reg input_jitter_warn_issued; + +`ifndef XIL_XECLIB + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin + $display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); + #1 $finish; + end + + CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0; + CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0; + + if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin + $display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin + $display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); + end + + if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin + $display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); + end + + clkfbout_f_div = CLKFBOUT_MULT_F_RND; + attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + clk0_f_div = CLKOUT0_DIVIDE_F_RND; + attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + + clk1_div = CLKOUT1_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + clk2_div = CLKOUT2_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + clk3_div = CLKOUT3_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + clk4_div = CLKOUT4_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + clk5_div = CLKOUT5_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + clk6_div = CLKOUT6_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + divclk_div = DIVCLK_DIVIDE_REG; + attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + + ps_in_init = 0; + ps_in_ps = ps_in_init; + ps_cnt = 0; + + clk0_fps_en = (CLKOUT0_USE_FINE_PS_REG == "TRUE"); + clk1_fps_en = (CLKOUT1_USE_FINE_PS_REG == "TRUE"); + clk2_fps_en = (CLKOUT2_USE_FINE_PS_REG == "TRUE"); + clk3_fps_en = (CLKOUT3_USE_FINE_PS_REG == "TRUE"); + clk4_fps_en = (CLKOUT4_USE_FINE_PS_REG == "TRUE"); + clk5_fps_en = (CLKOUT5_USE_FINE_PS_REG == "TRUE"); + clk6_fps_en = (CLKOUT6_USE_FINE_PS_REG == "TRUE"); + clkfbout_fps_en = (CLKFBOUT_USE_FINE_PS_REG == "TRUE"); + + fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en + || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en; + + if (clk0_frac_en == 1'b1) begin + if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin + $display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + #1 $finish; + end + end + + pll_lfhf = 2'b00; + + if (BANDWIDTH_REG === "LOW") + GetMultVal(clkfbout_div,nBandwidth_LOW,pll_cp,pll_res); + else if (BANDWIDTH_REG === "HIGH") + GetMultVal(clkfbout_div,nBandwidth_HIGH,pll_cp,pll_res); + else if (BANDWIDTH_REG === "OPTIMIZED") + GetMultVal(clkfbout_div,nBandwidth_OPTIMIZED,pll_cp,pll_res); + + GetLockDetSettings(clkfbout_div,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_lock_sat_high,drp_unlock_cnt); + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX); + tmp_string = "CLKFBOUT_MULT_F"; + chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string); + if(clk0_frac_en == 1'b0) begin + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string); + end + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string); + period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + clk0f_product = CLKOUT0_DIVIDE_F_RND * 8; + pll_lock_time = 12; + lock_period_time = 10; + if (clkfbout_frac_en == 1'b1) begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + clkout_en_val = mf_product - 1; + m_product2 = clkfbout_div / 2; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + md_product = clkfbout_div * DIVCLK_DIVIDE_REG; + m_product = clkfbout_div; + mf_product = CLKFBOUT_MULT_F_RND * 8; + m_product2 = clkfbout_div / 2; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + divclk_div = DIVCLK_DIVIDE_REG; + + dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[7] = {clk0_pm_f[2:0], clk0_wf_f, 1'bx, clk5_cddc_en, + 2'b0, clk5_e, clk5_nc, clk5_dt[5:0]}; + dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {clk0_cddc_en, clk0_frac[2:0], clk0_frac_en, clk0_wf_r, + 2'b0, clk0_e, clk0_nc, clk0_dt[5:0]}; + dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {5'bx, clk1_cddc_en, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]}; + dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[13] = {5'bx, clk2_cddc_en, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]}; + dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[15] = {5'bx, clk3_cddc_en, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]}; + dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[17] = {5'bx, clk4_cddc_en, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]}; + dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]}; + dr_sram[19] = {clkfbout_pm_f[2:0], clkfbout_wf_f, 1'bx, clk6_cddc_en, + 2'b0, clk6_e, clk6_nc, clk6_dt[5:0]}; + dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]}; + dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en, + clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]}; + dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]}; + dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[28] = {11'bx, 5'b0}; + dr_sram[39] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + end +`endif + + initial begin + clkpll_jitter_unlock = 0; + clkinstopped_vco_f = 0; + rst_clkfbstopped = 0; + rst_clkinstopped = 0; + rst_clkfbstopped_lk = 0; + rst_clkinstopped_lk = 0; + clkfbin_stop_tmp = 0; + clkin_stop_tmp = 0; + clkvco_lk_en = 0; + clkvco_lk_dly_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + divclk_div = DIVCLK_DIVIDE_REG; + ps_lock = 0; + ps_lock_dly = 0; + PSDONE_out = 1'b0; + rst_int = 0; + CLKINSTOPPED_out = 1'b0; + clkinstopped_out1 = 0; + CLKFBSTOPPED_out = 1'b0; + clkfbstopped_out1 = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_period_tmp_t = 0; + period_avg = 100000; + period_fb = 100000; + clkin_lost_val = 2; + clkfbin_lost_val = 2; + fb_delay = 0; + clkvco_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fb_comp_delay = 0; + clkfbout_pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + period_ps = 0; + period_ps_old = 0; + clkfbout_frac_ht = 0; + clkfbout_frac_lt = 0; + clk0_frac_ht = 0; + clk0_frac_lt = 0; + clk0_frac_ht_rl = 0.0; + clk0_frac_lt_rl = 0.0; + clkvco_rm_cnt = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + fbclk_tmp = 0; + clkfbout_tst = 1'b0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + DRDY_out = 1'b0; + CDDCDONE_out = 1'b0; + LOCKED_out = 1'b0; + DO_out = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clk6_dly_cnt = 6'b0; + clkfbout_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clk6_cnt = 8'b0; + clkfbout_cnt = 8'b0; + divclk_cnt = 8'b0; + CLKOUT0_out = 1'b0; + CLKOUT0B_out = 1'b1; + CLKOUT1_out = 1'b0; + CLKOUT1B_out = 1'b1; + CLKOUT2_out = 1'b0; + CLKOUT2B_out = 1'b1; + CLKOUT3_out = 1'b0; + CLKOUT3B_out = 1'b1; + CLKOUT4_out = 1'b0; + CLKOUT5_out = 1'b0; + CLKOUT6_out = 1'b0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clk6_out = 0; + CLKFBOUT_out = 1'b0; + CLKFBOUTB_out = 1'b1; + divclk_out = 0; + divclk_out_tmp = 0; + clkin_osc = 0; + clkfbin_osc = 0; + clkin_p = 0; + clkfbin_p = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign #2 clkinsel_tmp = CLKINSEL_in; + + assign glock = (STARTUP_WAIT_BIN == STARTUP_WAIT_FALSE) || LOCKED; + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + + initial begin + init_chk = 0; + #2; + init_chk = 1; + #2; + init_chk = 0; + end + + always @(CLKINSEL_in or posedge init_chk ) begin + #1; + if (init_chk == 0 && $time > 3 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time); + #1 $finish; + end + + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin + if (CLKIN1_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN1_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + + #1 $finish; + end + end + else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin + if (CLKIN2_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN2_PERIOD_REG * 1000 < clkin_chk_t2_i) begin + $display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + #1 $finish; + end + end + + period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG; + if (period_clkin == 0) period_clkin = 10; + + if (period_clkin < MAX_FEEDBACK_DELAY) + fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE; + else + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG); + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + end + clkpfd_freq_init_chk = (1000.0) / (period_clkin * DIVCLK_DIVIDE_REG); + if (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-9] The calculated PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz set by CLKPFD_FREQ_MIN/MAX. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display ("Error: [Unisim %s-10] The calculated PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz set by CLKPFD_FREQ_MIN/MAX. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + end + end + + assign init_trig = 1; + assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in; + assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0; + assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkpll_r or posedge rst_input) + if (rst_input) + rst_int <= 1; + else + rst_int <= rst_input ; + + assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped); + +//simprim_rst_h + always @(posedge pwrdwn_in1 or posedge pchk_clr) + if (pwrdwn_in1) + pwrdwn_in1_h <= 1; + else if (pchk_clr) + pwrdwn_in1_h <= 0; + + always @(posedge RST_in or posedge pchk_clr) + if (RST_in) + rst_input_r_h <= 1; + else if (pchk_clr) + rst_input_r_h <= 0; + + + always @(rst_input ) + if (rst_input==1) begin + rst_edge = $time; + pchk_clr = 0; + end + else if (rst_input==0 && rst_edge > 1) begin + rst_ht = $time - rst_edge; + if (rst_ht < 1500) begin + if (rst_input_r_h == 1 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns) . Instance %m ", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0) + $display("Warning: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1) + $display("Warning: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0); + end + pchk_clr = 1; + end +//endsimprim_rst_h + + // + // DRP port read and write + // + + always @ (*) begin + DO_out = dr_sram[daddr_lat]; + end + + always @(posedge DCLK_in or posedge glblGSR) + if (glblGSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 0; + drp_updt <= 1'b0; + end else begin + if (~(RST_in || CDDCREQ_in) && drp_updt) drp_updt <= 1'b0; + if (DEN_in == 1) begin + valid_daddr = addr_is_valid(DADDR_in); + if (drp_lock == 1) begin + $display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); + end else begin + drp_lock <= 1; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + daddr_lat <= DADDR_in; + end + if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time); + if (DWE_in == 1) begin // write process + if (rst_input == 1 || CDDCREQ_in == 1) begin + if (valid_daddr) dr_sram[DADDR_in] <= DI_in; + if (valid_daddr || drp_updt) drp_updt <= 1'b1; + if (DADDR_in == 7'd6) + lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in); + else if (DADDR_in == 7'd7) + upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_cddc_en, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in); + else if (DADDR_in == 7'd8) + lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in); + else if (DADDR_in == 7'd9) begin + upper_frac_drp(clk0_cddc_en, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in); + end else if (DADDR_in == 7'd10) + lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in); + else if (DADDR_in == 7'd11) + upper_drp(clk1_cddc_en, clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in); + else if (DADDR_in == 7'd12) + lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in); + else if (DADDR_in == 7'd13) + upper_drp(clk2_cddc_en, clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in); + else if (DADDR_in == 7'd14) + lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in); + else if (DADDR_in == 7'd15) + upper_drp(clk3_cddc_en, clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in); + else if (DADDR_in == 7'd16) + lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in); + else if (DADDR_in == 7'd17) + upper_drp(clk4_cddc_en, clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in); + else if (DADDR_in == 7'd18) + lower_drp(clk6_pm, clk6_en, clk6_ht, clk6_lt, DI_in); + else if (DADDR_in == 7'd19) + upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_cddc_en, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in); + else if (DADDR_in == 7'd20) + lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in); + else if (DADDR_in == 7'd21) + upper_frac_drp(clkfbout_cddc_res, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in); + else if (DADDR_in == 7'd22) begin + divclk_e = DI_in[13]; + divclk_nc = DI_in[12]; + divclk_ht = DI_in[11:6]; + divclk_lt = DI_in[5:0]; + end + else if (DADDR_in == 7'd24) + drp_lock_cnt = DI_in[9:0]; + else if (DADDR_in == 7'd25) begin + drp_lock_fb_dly = DI_in[14:10]; + drp_unlock_cnt = DI_in[9:0]; + end + else if (DADDR_in == 7'd26) begin + drp_lock_ref_dly = DI_in[14:10]; + drp_lock_sat_high = DI_in[9:0]; + end + else if (DADDR_in == 7'd78) + pll_cp = {DI_in[15],DI_in[12],DI_in[11],DI_in[8]}; + else if (DADDR_in == 7'd79) + pll_res = {DI_in[15],DI_in[12],DI_in[11],DI_in[8]}; + end else begin + $display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + end else begin + drp_lock <= 0; + DRDY_out <= 1; + drp_lock_lat_cnt <= 0; + end + end + if (DRDY == 1) DRDY_out <= 0; + end + + always @(posedge CDDCREQ_in or negedge CDDCREQ_in) + begin + if (CDDCREQ_in == 1'b1) + CDDCDONE_out <= 1'b0; + else + begin + @(posedge clkvco) + @(posedge clkvco) + @(posedge clkvco) + CDDCDONE_out <= ~CDDCREQ_in; + end + end + + function addr_is_valid; + input [6:0] daddr_in; + begin + addr_is_valid = 1'b1; + for (i=0; i<=6; i=i+1) + if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0; + if ((addr_is_valid) && + ((daddr_in >= 7'd06 && daddr_in <= 7'd22) || + (daddr_in >= 7'd24 && daddr_in <= 7'd26) || + (daddr_in == 7'd28) || + (daddr_in == 7'd39) || + (daddr_in == 7'd78) || + (daddr_in == 7'd79))) addr_is_valid = 1'b1; + else addr_is_valid = 1'b0; + end + endfunction + + // end process drp; + + // + // determine clock period + // + + always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag) + if (rst_int || rst_clkinsel_flag) + begin + clkin_period[0] <= 1000 * period_clkin; + clkin_period[1] <= 1000 * period_clkin; + clkin_period[2] <= 1000 * period_clkin; + clkin_period[3] <= 1000 * period_clkin; + clkin_period[4] <= 1000 * period_clkin; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end else begin + clkin_edge <= $time; + if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= #1 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(posedge pll_locked_tmp1) + if (CLKINSEL_in === 0) begin + pchk_tmp1 = CLKIN2_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN2_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + else begin + pchk_tmp1 = CLKIN1_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN1_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME); + end + end + + always @(*) + if (rst_int == 0) begin + if (clkfbout_frac_en == 1'b0) begin + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + clkout_en_val = mf_product - 1; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + end + + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + if (clkout_en0_tmp==0 ) + clkout_en0 = 0; + else begin + if (clkfbout_frac_en == 1'b1) begin + if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + else begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in_o ) + if (rst_in_o) + clkout_en = 0; + else + clkout_en = clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_int or glblGSR) + if (rst_int || glblGSR) begin + assign pll_locked_tmp2 = 0; + end + else begin + deassign pll_locked_tmp2; + end + + always @(rst_int) + if (rst_int) begin + assign clkout_en0 = 0; + assign clkout_en1 = 0; + end + else begin + deassign clkout_en0; + deassign clkout_en1; + end + + always @(rst_int or pll_locked_tm or pll_locked_tmp2 or pll_unlock or unlock_recover) begin + if ((rst_int == 1) && (LOCKED !== 1'b0)) + LOCKED_out <= #1000 0; + else if ((pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && ~unlock_recover) === 1'b1) + LOCKED_out <= 1'b1; + else + LOCKED_out <= 1'b0; + end + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4]) begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; + + if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + end + + //CR-1062375 + always @(rst_int or LOCKED_out or clkin_period[4]) begin + if(rst_int) + input_jitter_warn_issued <= 1'b0; + else if(LOCKED && !input_jitter_warn_issued) + if(clkin_period[4]!=clkin_period[3]) begin + $display("Warning: [Unisim %s-39] Input clock has jitter. This may cause misalignment in output clocks. Instance %m ", MODULE_NAME, $time); + input_jitter_warn_issued <= 1'b1; + end + end + + always @(clkinstopped_out1 or clkin_hold_f or rst_int) + if (rst_int) + clkinstopped_hold = 0; + else begin + if (clkinstopped_out1) + clkinstopped_hold <= 1; + else begin + if (clkin_hold_f) + clkinstopped_hold = 0; + end + end + + always @(posedge clkinstopped_out1) begin + period_avg_stpi <= period_avg; + pd_stp_p <= #1 1; + @(negedge clkvco) + pd_stp_p <= #1 0; + end + + always @(negedge clkvco or posedge rst_int or posedge pd_stp_p) + if (rst_int) begin + period_avg_stp <= 1000; + vco_stp_f <= 0; + end + else if (pd_stp_p) + period_avg_stp <= period_avg_stpi; + else begin + if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin + if (period_vco > 1739) + vco_stp_f <= 1; + else begin + period_avg_stp <= period_avg_stp + 1; + end + end + end + + + always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold + or period_avg_stp or posedge rst_clkinstopped_rc) + if (period_avg > 0 ) begin + md_product = divclk_div * clkfbout_f_div; + m_product = clkfbout_f_div; + m_product2 = clkfbout_f_div / 2; + clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div); + clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint; + if (clkvco_div_frac > 0.000) + clkvco_frac_en = 1; + else + clkvco_frac_en = 0; + period_fb = period_avg * divclk_div; + period_vco_tmp = period_fb / clkfbout_f_div; + period_vco_rl = 1.0 * period_fb / clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp; + period_vco_mf = period_avg * 8; + if (clkinstopped_hold == 1) begin + if (clkin_hold_f) begin + period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + period_vco_rl_half = period_vco_rl / 2.0; + end + else begin + period_vco = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div; + period_vco_rl_half = period_vco_rl / 2.0; + end + end + else + period_vco = period_vco_tmp; + + period_vco_rm = period_fb % clkfbout_div; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + if (period_vco_half_rm < 1) + period_vco_half_rm2 = 0; + else + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbout_f_div; + clkin_dly_t = period_avg * (divclk_div + 1.25); + clkfbin_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + end + + always @ (negedge RST_in or negedge CDDCREQ_in) begin + if (drp_updt) begin + clkout_name = "CLKFBOUT"; + mc_to_attr(clkout_name, clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty); + if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc) + $display("Error : [Unisim %s-38] CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time); + check_m_settings(clkfbout_f_div,pll_cp,pll_res,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_unlock_cnt,drp_lock_sat_high); + #1; + clkout_name = "CLKOUT0"; + mc_to_attr(clkout_name, clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty); + if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc) + $display("Error : [Unisim %s-37] CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time); + #1; + clkout_name = "CLKOUT1"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty); + clkout_name = "CLKOUT2"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty); + clkout_name = "CLKOUT3"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty); + clkout_name = "CLKOUT4"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty); + clkout_name = "CLKOUT5"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty); + clkout_name = "CLKOUT6"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty); + clkout_name = "DIVCLK"; + mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty); + if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc) + $display("Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time); + ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); + ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); + ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); + ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); + end + end + + always @(clkfbout_f_div) begin + mf_product = clkfbout_f_div * 8; + end + + always @(*) begin + if (clkfbout_frac_en) begin + clkfbout_frac_ht_rl = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_rsel) / 8.0; + clkfbout_frac_lt_rl = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_fsel) / 8.0; + clkfbout_frac_ht = $rtoi(clkfbout_frac_ht_rl); + clkfbout_frac_lt = $rtoi(clkfbout_frac_lt_rl); + end + end + + always @(*) begin + if (clk0_frac_en) begin + clk0_frac_ht_rl = period_vco_rl * clk0_fht + (period_vco_rl * clk0_rsel) / 8.0; + clk0_frac_lt_rl = period_vco_rl * clk0_flt + (period_vco_rl * clk0_fsel) / 8.0; + clk0_frac_ht = $rtoi(clk0_frac_ht_rl); + clk0_frac_lt = $rtoi(clk0_frac_lt_rl); + end + end + + reg ps_wr_to_max = 1'b0; + always @(period_vco or ps_in_ps) + if (fps_en == 1) begin + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && PSINCDEC_in == 0) + period_ps = 0; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + + always @( clkpll_r ) + clkpll_tmp1 <= #(period_avg) clkpll_r; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(posedge clkinstopped_out1 or posedge rst_int) + if ( rst_int) + clkinstopped_vco_f <= 0; + else begin + clkinstopped_vco_f <= 1; + @(negedge clkinstopped_out1 or posedge rst_int ) + if (rst_int) + clkinstopped_vco_f <= 0; + else begin + @(posedge clkpll); + @(posedge clkpll) + clkinstopped_vco_f <= 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + CLKINSTOPPED_out <= 0; + else begin + CLKINSTOPPED_out <= 1; + if (clkin_hold_f == 1) begin + @(posedge LOCKED or posedge rst_int) + CLKINSTOPPED_out <= 0; + end + else begin + if (CLKINSEL_in == 1) + $display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + else + $display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + end + end + + always @(posedge clkfbstopped_out1 or posedge rst_int) + if (rst_int) + CLKFBSTOPPED_out <= 1'b0; + else begin + CLKFBSTOPPED_out <= 1'b1; + @(posedge LOCKED) + CLKFBSTOPPED_out <= 1'b0; + end + + always @(clkout_en_t) + if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) + rst_clkinstopped_tm = 1; + else + rst_clkinstopped_tm = 0; + + always @(negedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + rst_clkinstopped <= 0; + else + if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin + @(posedge rst_clkinstopped_tm) + rst_clkinstopped <= #period_vco4 1; + @(negedge rst_clkinstopped_tm ) begin + rst_clkinstopped <= #period_vco5 0; + rst_clkinstopped_rc <= #period_vco6 1; + rst_clkinstopped_rc <= #period_vco7 0; + end + end + + always @(posedge clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly <= 0; + else begin + clkinstopped_out_dly <= 1; + if (clkin_hold_f == 1) begin + @(negedge rst_clkinstopped_rc or posedge rst_int) + clkinstopped_out_dly <= 0; + end + end + + always @(clkinstopped_out1 or posedge rst_int) + if (rst_int) + clkinstopped_out_dly2 <= 0; + else + clkinstopped_out_dly2 <= clkinstopped_out1; + + always @(negedge rst_clkinstopped or posedge rst_int) + if (rst_int) + rst_clkinstopped_lk <= 0; + else begin + rst_clkinstopped_lk <= 1; + @(posedge LOCKED) + rst_clkinstopped_lk <= 0; + end + + always @(clkinstopped_vco_f or CLKINSTOPPED or clkvco_lk or clkvco_free or rst_int) + if (rst_int) + clkvco_lk = 0; + else begin + if (CLKINSTOPPED == 1 && clkin_stop_f == 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else if (clkinstopped_vco_f == 1 && period_vco_half > 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else + clkvco_lk = clkvco_free; + end + +// free run vco comp + + always @(posedge clkpll) + if (pll_locked_tm == 1 ) begin + clkvco_free = 1'b1; + halfperiod_sum = 0.0; + halfperiod = 0; + if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin + if (mf_product > 1) begin + for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin + clkout_en_t <= ik10; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik10; + end else begin + clkout_en_t <= 1; + end + end else begin + if (m_product > 1) begin + for (ik11=1; ik11 < m_product; ik11=ik11+1) begin + clkout_en_t <= ik11; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b1; + end + clkout_en_t <= ik11; + end else begin + clkout_en_t <= 1; + end + end + halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; + halfperiod = $rtoi(halfperiod_sum); + #halfperiod clkvco_free = 1'b0; + if (clkfbout_f_div < divclk_div) begin + #(period_vco_rl_half - period_avg/2.0); + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl + or lock_period or ps_in_ps ) + if (lock_period == 1) begin + if (clkfbout_frac_en == 1'b1) begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + else begin + val_tmp = period_avg * DIVCLK_DIVIDE_REG; + fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); + end + dly_tmp1 = fb_delay + fb_comp_delay; + dly_tmp_int = 1; + if (CLKFBOUT_USE_FINE_PS_BIN == CLKFBOUT_USE_FINE_PS_TRUE) begin + if (ps_in_ps < 0) begin + tmp_ps_val1 = -1 * ps_in_ps; + tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; + if (tmp_ps_val2 > dly_tmp1 ) begin + dly_tmp_int = -1; + dly_tmp = tmp_ps_val2 - dly_tmp1; + end + else if (tmp_ps_val2 == dly_tmp1 ) begin + dly_tmp_int = 0; + dly_tmp = 0; + end + else begin + dly_tmp_int = 1; + dly_tmp = dly_tmp1 - tmp_ps_val2; + end + end + else + dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; + end + else + dly_tmp = dly_tmp1; + + if (dly_tmp_int < 0) + clkvco_delay = dly_tmp; + else begin + if (clkfbout_frac_en == 1'b1 && dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + end + + always @(clkfbout_pm_r) + case (clkfbout_pm_r) + 3'b000 : clkfbout_pm_rl = 0.0; + 3'b001 : clkfbout_pm_rl = 0.125; + 3'b010 : clkfbout_pm_rl = 0.25; + 3'b011 : clkfbout_pm_rl = 0.375; + 3'b100 : clkfbout_pm_rl = 0.50; + 3'b101 : clkfbout_pm_rl = 0.625; + 3'b110 : clkfbout_pm_rl = 0.75; + 3'b111 : clkfbout_pm_rl = 0.875; + endcase + + always @(clkvco_lk) + clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; + + always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) + if ( pll_locked_tm && vco_stp_f == 0) begin + if (dly_tmp == 0) + clkvco = clkvco_lk; + else + clkvco = clkvco_lk_dly_tmp; + end + else + clkvco = 0; + + always @(posedge PSCLK_in or posedge rst_int) + if (rst_int) begin + ps_in_ps <= ps_in_init; + ps_cnt <= 0; + psen_w <= 0; + fps_clk_en <= 0; + ps_lock <= 0; + end else if (fps_en == 1) begin + fps_clk_en <= 1; + if (PSEN_in) begin + if (psen_w == 1) + $display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time); + + psen_w <= 1; + if (ps_lock == 1) + $display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time); + else if (PSINCDEC_in == 1) begin + if (ps_cnt < ps_max) + ps_cnt <= ps_cnt + 1; + else + ps_cnt <= 0; + + if (ps_in_ps < ps_max) + ps_in_ps <= ps_in_ps + 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + else if (PSINCDEC_in == 0) begin + ps_cnt_neg = (-1) * ps_cnt; + ps_in_ps_neg = (-1) * ps_in_ps; + if (ps_cnt_neg < ps_max) + ps_cnt <= ps_cnt - 1; + else + ps_cnt <= 0; + + if (ps_in_ps_neg < ps_max) + ps_in_ps <= ps_in_ps - 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + end + else + psen_w <= 0; + + if ( PSDONE == 1'b1) + ps_lock <= 0; + end + + always @(posedge ps_lock) + if (fps_en == 1) begin + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + @(posedge PSCLK_in) + begin + PSDONE_out = 1'b1; + @(posedge PSCLK_in); + PSDONE_out = 1'b0; + end + end + + always @(rst_clkinstopped) + if (rst_clkinstopped) begin + assign clkfbout_frac_ht = 50; + assign clkfbout_frac_lt = 50; + assign clkfbout_frac_ht_rl = 50.0; + assign clkfbout_frac_lt_rl = 50.0; + end + else begin + deassign clkfbout_frac_ht; + deassign clkfbout_frac_lt; + deassign clkfbout_frac_ht_rl; + deassign clkfbout_frac_lt_rl; + end + + integer clk0_delay, clk1_delay, clk2_delay, clk3_delay, clk4_delay, clk5_delay, clk6_delay, clkfbout_delay; + integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next; + always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps); + always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps); + always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps); + always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps); + always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps); + always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps); + always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps); + always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps); + + always @ (posedge clkvco) begin + if (ps_lock) begin + if ((period_ps - period_ps_old) > period_vco/2) + ps_wr_to_max <= 1'b1; + else + ps_wr_to_max <= 1'b0; + end + period_ps_old = period_ps; + clk0_delay <= clk0_delay_next; + clk1_delay <= clk1_delay_next; + clk2_delay <= clk2_delay_next; + clk3_delay <= clk3_delay_next; + clk4_delay <= clk4_delay_next; + clk5_delay <= clk5_delay_next; + clk6_delay <= clk6_delay_next; + clkfbout_delay <= clkfbout_delay_next; + end + + always @ (clkvco) begin + if (clkout_en && clk0_en) + if (clk0_delay == 0) clk0in = clkvco; + else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin + clk0in <= #(clk0_delay - period_ps) 1'b0; + clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1; + clk0in <= #(clk0_delay) 1'b0; + end else begin + clk0in <= #clk0_delay clkvco; + end + else clk0in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk1_en) + if (clk1_delay == 0) clk1in = clkvco; + else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin + clk1in <= #(clk1_delay - period_ps) 1'b0; + clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1; + clk1in <= #(clk1_delay) 1'b0; + end else begin + clk1in <= #clk1_delay clkvco; + end + else clk1in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk2_en) + if (clk2_delay == 0) clk2in = clkvco; + else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin + clk2in <= #(clk2_delay - period_ps) 1'b0; + clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1; + clk2in <= #(clk2_delay) 1'b0; + end else begin + clk2in <= #clk2_delay clkvco; + end + else clk2in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk3_en) + if (clk3_delay == 0) clk3in = clkvco; + else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin + clk3in <= #(clk3_delay - period_ps) 1'b0; + clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1; + clk3in <= #(clk3_delay) 1'b0; + end else begin + clk3in <= #clk3_delay clkvco; + end + else clk3in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk4_en) + if (CLKOUT4_CASCADE_BIN == CLKOUT4_CASCADE_TRUE) clk4in = clk6_out; + else if (clk4_delay == 0) clk4in = clkvco; + else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin + clk4in <= #(clk4_delay - period_ps) 1'b0; + clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1; + clk4in <= #(clk4_delay) 1'b0; + end else begin + clk4in <= #clk4_delay clkvco; + end + else clk4in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk5_en) + if (clk5_delay == 0) clk5in = clkvco; + else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin + clk5in <= #(clk5_delay - period_ps) 1'b0; + clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1; + clk5in <= #(clk5_delay) 1'b0; + end else begin + clk5in <= #clk5_delay clkvco; + end + else clk5in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clk6_en) + if (clk6_delay == 0) clk6in = clkvco; + else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin + clk6in <= #(clk6_delay - period_ps) 1'b0; + clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1; + clk6in <= #(clk6_delay) 1'b0; + end else begin + clk6in <= #clk6_delay clkvco; + end + else clk6in = 1'b0; + end + + always @ (clkvco) begin + if (clkout_en && clkfbout_en) + if (clkfbout_delay == 0) clkfboutin = clkvco; + else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin + clkfboutin <= #(clkfbout_delay - period_ps) 1'b0; + clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1; + clkfboutin <= #(clkfbout_delay) 1'b0; + end else begin + clkfboutin <= #clkfbout_delay clkvco; + end + else clkfboutin = 1'b0; + end + + + assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en; + assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en; + assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en; + assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en; + assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en; + assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en; + assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en; + assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en; + + always @(negedge clk0in or posedge rst_in_o) + if (rst_in_o) + clk0_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk0_dly_cnt < clk0_dt) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in_o) + if (rst_in_o) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clk1_dt && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in_o) + if (rst_in_o) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clk2_dt && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in_o) + if (rst_in_o) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clk3_dt && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in_o) + if (rst_in_o) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clk4_dt && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in_o) + if (rst_in_o) + clk5_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk5_dly_cnt < clk5_dt) + clk5_dly_cnt <= clk5_dly_cnt + 1; + end + + always @(negedge clk6in or posedge rst_in_o) + if (rst_in_o) + clk6_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clk6_dly_cnt < clk6_dt) + clk6_dly_cnt <= clk6_dly_cnt + 1; + end + + always @(negedge clkfboutin or posedge rst_in_o) + if (rst_in_o) + clkfbout_dly_cnt <= 6'b0; + else if (clkout_en == 1 ) begin + if (clkfbout_dly_cnt < clkfbout_dt) + clkfbout_dly_cnt <= clkfbout_dly_cnt + 1; + end + + always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o) + if (rst_in_o || ~clkfbps_en) begin + clkfbout_cnt <= 8'b0; + clkfbout_out = 0; + end + else if (clkfbout_nc) clkfbout_out = ~clkfbout_out; + else if (~clkfbout_frac_en) begin + if (clkfbout_cnt < clkfbout_cnt_max) + clkfbout_cnt <= clkfbout_cnt + 1; + else + clkfbout_cnt <= 8'b0; + if (clkfbout_cnt < clkfbout_cnt_ht) + clkfbout_out = 1; + else + clkfbout_out = 0; + end + else if (clkfbout_frac_en && clkfboutin) begin + clkfbout_out = 1; + clkfbout_frac_rm_rl = 0.0; + clkfbout_frac_rm = 0; + for (ib=1; ib < 8; ib=ib+1) begin + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_ht_rl - clkfbout_frac_ht - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_ht + clkfbout_frac_rm) clkfbout_out = 0; + clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_lt_rl - clkfbout_frac_lt - clkfbout_frac_rm; + clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl); + #(clkfbout_frac_lt + clkfbout_frac_rm) clkfbout_out = 1; + end + #(clkfbout_frac_ht) clkfbout_out = 0; + #(clkfbout_frac_lt - period_vco1); + end + + always @(posedge clk0in or negedge clk0in or posedge rst_in_o) + if (rst_in_o || ~clk0ps_en) begin + clk0_cnt <= 8'b0; + clk0_out = 0; + end + else if (clk0_nc) clk0_out = ~clk0_out; + else if (~clk0_frac_en) begin + if (clk0_cnt < clk0_cnt_max) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + if (clk0_cnt < clk0_cnt_ht) + clk0_out = 1; + else + clk0_out = 0; + end + else if (clk0_frac_en && clk0in) begin + clk0_out = 1; + clk0_frac_rm_rl = 0.0; + clk0_frac_rm = 0; + for (ik0=1; ik0 < 8; ik0=ik0+1) begin + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_ht_rl - clk0_frac_ht - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_ht + clk0_frac_rm) clk0_out = 0; + clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_lt_rl - clk0_frac_lt - clk0_frac_rm; + clk0_frac_rm = $rtoi(clk0_frac_rm_rl); + #(clk0_frac_lt + clk0_frac_rm) clk0_out = 1; + end + #(clk0_frac_ht) clk0_out = 0; + #(clk0_frac_lt - period_vco1); + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in_o) + if (rst_in_o || ~clk1ps_en) begin + clk1_cnt <= 8'b0; + clk1_out = 0; + end + else if (clk1_nc) clk1_out = ~clk1_out; + else begin + if (clk1_cnt < clk1_cnt_max) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + if (clk1_cnt < clk1_cnt_ht) + clk1_out = 1; + else + clk1_out = 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in_o) + if (rst_in_o || ~clk2ps_en) begin + clk2_cnt <= 8'b0; + clk2_out = 0; + end + else if (clk2_nc) clk2_out = ~clk2_out; + else begin + if (clk2_cnt < clk2_cnt_max) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + if (clk2_cnt < clk2_cnt_ht) + clk2_out = 1; + else + clk2_out = 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in_o) + if (rst_in_o || ~clk3ps_en) begin + clk3_cnt <= 8'b0; + clk3_out = 0; + end + else if (clk3_nc) clk3_out = ~clk3_out; + else begin + if (clk3_cnt < clk3_cnt_max) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + if (clk3_cnt < clk3_cnt_ht) + clk3_out = 1; + else + clk3_out = 0; + end + + always @(posedge clk4in or negedge clk4in or posedge rst_in_o) + if (rst_in_o || ~clk4ps_en) begin + clk4_cnt <= 8'b0; + clk4_out = 0; + end + else if (clk4_nc) clk4_out = ~clk4_out; + else begin + if (clk4_cnt < clk4_cnt_max) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + if (clk4_cnt < clk4_cnt_ht) + clk4_out = 1; + else + clk4_out = 0; + end + + always @(posedge clk5in or negedge clk5in or posedge rst_in_o) + if (rst_in_o || ~clk5ps_en) begin + clk5_cnt <= 8'b0; + clk5_out = 0; + end + else if (clk5_nc) clk5_out = ~clk5_out; + else begin + if (clk5_cnt < clk5_cnt_max) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + if (clk5_cnt < clk5_cnt_ht) + clk5_out = 1; + else + clk5_out = 0; + end + + always @(posedge clk6in or negedge clk6in or posedge rst_in_o) + if (rst_in_o || ~clk6ps_en) begin + clk6_cnt <= 8'b0; + clk6_out = 0; + end + else if (clk6_nc) clk6_out = ~clk6_out; + else begin + if (clk6_cnt < clk6_cnt_max) + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 8'b0; + if (clk6_cnt < clk6_cnt_ht) + clk6_out = 1; + else + clk6_out = 0; + end + + + always @(clk0_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT0_out = clk0_out; + CLKOUT0B_out = ~clk0_out; + end else begin + CLKOUT0_out = clkfbout_tst; + CLKOUT0B_out = ~clkfbout_tst; + end + + always @(clk1_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT1_out = clk1_out; + CLKOUT1B_out = ~clk1_out; + end else begin + CLKOUT1_out = clkfbout_tst; + CLKOUT1B_out = ~clkfbout_tst; + end + + always @(clk2_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT2_out = clk2_out; + CLKOUT2B_out = ~clk2_out; + end else begin + CLKOUT2_out = clkfbout_tst; + CLKOUT2B_out = ~clkfbout_tst; + end + + always @(clk3_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT3_out = clk3_out; + CLKOUT3B_out = ~clk3_out; + end else begin + CLKOUT3_out = clkfbout_tst; + CLKOUT3B_out = ~clkfbout_tst; + end + + always @(clk4_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT4_out = clk4_out; + end else begin + CLKOUT4_out = clkfbout_tst; + end + + always @(clk5_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT5_out = clk5_out; + end else begin + CLKOUT5_out = clkfbout_tst; + end + + always @(clk6_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) begin + CLKOUT6_out = clk6_out; + end else begin + CLKOUT6_out = clkfbout_tst; + end + + always @(clkfbout_out or clkfbout_tst or fb_delay_found) + if (fb_delay_found == 1'b1) + begin + CLKFBOUT_out = clkfbout_out; + CLKFBOUTB_out = ~clkfbout_out; + end + else + begin + CLKFBOUT_out = clkfbout_tst; + CLKFBOUTB_out = ~clkfbout_tst; + end + + // + // determine feedback delay + // + + + always @(posedge clkpll_r ) + if (fb_delay_found) clkfbout_tst = 1'b0; + else clkfbout_tst = ~clkfbout_tst; + + always @( posedge clkfbout_tst ) + delay_edge = $time; + + assign clkfbin_sel = ((COMPENSATION_BIN == COMPENSATION_INTERNAL) || + ((COMPENSATION_BIN == COMPENSATION_AUTO) && (CLKFBIN === 1'bz))); + + assign CLKFBIN_int = clkfbin_sel && CLKFBOUT_out || ~clkfbin_sel && CLKFBIN_in; + + always @(posedge CLKFBIN_int ) + if (clkfbin_sel == 1 ) begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b1; + end else if (fb_delay_found_tmp == 1'b0 ) begin + if ( delay_edge != 0) begin + fb_delay <= ($time - delay_edge); + fb_delay_found_tmp <= 1'b1; + end else begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end + end + + always @(negedge clkfbout_tst or negedge fb_delay_found_tmp) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay or fb_delay_found) + if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); + end + + // + // generate unlock signal + // + + always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc; + always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc; + + always @(posedge clkpll_r or negedge clkpll_r) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int) begin + clkfbin_p <= 1; + clkfbin_p <= #100 0; + end + + always @(posedge clkin_osc or posedge rst_int or posedge clkin_p) + if ((rst_int == 1) || (LOCKED == 1'b0)) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out1 == 1) begin + @(posedge clkpll_r) begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out1 <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out1 <= 0; + end + else + clkinstopped_out1 <= 1; + end + + always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p) + if (rst_int == 1 || clkfbin_p == 1) begin + clkfbstopped_out1 <= 0; + clkfbin_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfbin_lost_cnt < clkfbin_lost_val) begin + clkfbin_lost_cnt <= clkfbin_lost_cnt + 1; + clkfbstopped_out1 <= 0; + end + else + clkfbstopped_out1 <= 1; + end + + + always @(clkin_jit or rst_int ) + if (rst_int) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // tasks +task mc_to_attr; + input [160:1] clkout_name; + input [2:0] pm_f; + input wf_f; + input [2:0] frac; + input frac_en; + input wf_r; + input [1:0] mx; + input e; + input nc; + input [5:0] dt; + input [2:0] pm_r; + input en; + input [5:0] ht; + input [5:0] lt; + output real div; + output real phase; + output real duty; + + integer odd_frac; + reg odd; + real frac_r; + integer div_2; + integer pm_f_c; + real duty_step; + real phase_step; + + reg [2:0] pm_f_calc; + reg wf_f_calc; + reg [2:0] frac_calc; + reg frac_en_calc; + reg wf_r_calc; + reg [1:0] mx_calc; + reg e_calc; + reg nc_calc; + reg [5:0] dt_calc; + reg [2:0] pm_r_calc; + reg en_calc; + reg [5:0] ht_calc; + reg [5:0] lt_calc; + reg [34:0] calc; + reg [34:0] actual; + +begin + +if (nc == 1'b1) begin + div = 1.0; + duty = 0.5; +end +else if (frac_en == 1'b1) begin + duty =0.50; + + if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f; + else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r; + else pm_f_c = 8 + pm_f - pm_r; + + if (pm_f_c < 4) begin + odd = 1'b0; + odd_frac = frac; + end + else begin + odd = 1'b1; + odd_frac = frac + 8; + end + + frac_r = frac * 0.125; + + if (odd_frac > 9) div_2 = lt; + else div_2 = lt + 1; + + div = 2.0 * div_2 + 1.0 * odd + frac_r; + +end +else begin + + if (ht == 6'b0 && lt == 6'b0) div = 128.0; + else if (ht == 6'b0) div = 64.0 + lt * 1.0; + else if (lt == 6'b0) div = ht * 1.0 + 64.0; + else div = ht * 1.0 + lt * 1.0; + + duty_step = 0.5 / div; + + if (ht == 6'b0) duty = (2.0 * 64 + e) * duty_step; + else duty = (2.0 * ht + e) * duty_step; + +end + + phase_step = 360.0 / (div * 8.0); + phase = phase_step * (dt*8.0 + pm_r*1.0); + + attr_to_mc(pm_f_calc, wf_f_calc, frac_calc, frac_en_calc, wf_r_calc, mx_calc, e_calc, nc_calc, dt_calc, pm_r_calc, en_calc, ht_calc, lt_calc, div, phase, duty); + if (nc == 1'b1) begin + calc = {pm_f, wf_f, frac, frac_en, wf_r, mx, e, nc_calc, dt, pm_r, en, ht, lt}; + end else begin + calc = {pm_f_calc, wf_f_calc, frac_calc, frac_en_calc, wf_r_calc, mx_calc, e_calc, nc_calc, dt_calc, pm_r_calc, en_calc, ht_calc, lt_calc}; + end + actual = {pm_f, wf_f, frac, frac_en, wf_r, mx, e, nc, dt, pm_r, en, ht, lt}; + if (actual != calc) begin + $display("Error: [Unisim %s-36] Illegal counter DRP programming for %s at time %t. Instance %m ", MODULE_NAME, clkout_name, $time); + if (pm_f_calc != pm_f) $display ("Error: [Unisim %s-37] pm_f calc ('b%b) different from pm_f programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, pm_f_calc, pm_f, $time); + if (wf_f_calc != wf_f) $display ("Error: [Unisim %s-37] wf_f calc ('b%b) different from wf_f programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, wf_f_calc, wf_f, $time); + if (frac_calc != frac) $display ("Error: [Unisim %s-37] frac calc ('b%b) different from frac programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, frac_calc, frac, $time); + if (frac_en_calc != frac_en) $display ("Error: [Unisim %s-37] frac_en calc ('b%b) different from frac_en programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, frac_en_calc, frac_en, $time); + if (wf_r_calc != wf_r) $display ("Error: [Unisim %s-37] wf_r calc ('b%b) different from wf_r programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, wf_r_calc, wf_r, $time); + if (mx_calc != mx) $display ("Error: [Unisim %s-37] mx calc ('b%b) different from mx programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, mx_calc, mx, $time); + if (e_calc != e) $display ("Error: [Unisim %s-37] e calc ('b%b) different from e programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, e_calc, e, $time); + if (nc_calc != nc) $display ("Error: [Unisim %s-37] nc calc ('b%b) different from nc programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, nc_calc, nc, $time); + if (dt_calc != dt) $display ("Error: [Unisim %s-37] dt calc ('b%b) different from dt programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, dt_calc, dt, $time); + if (pm_r_calc != pm_r) $display ("Error: [Unisim %s-37] pm_r calc ('b%b) different from pm_r programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, pm_r_calc, pm_r, $time); + if (en_calc != en) $display ("Error: [Unisim %s-37] en calc ('b%b) different from en programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, en_calc, en, $time); + if (ht_calc != ht) $display ("Error: [Unisim %s-37] ht calc ('b%b) different from ht programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, ht_calc, ht, $time); + if (lt_calc != lt) $display ("Error: [Unisim %s-37] lt calc ('b%b) different from lt programmed ('b%b) at time %t. Instance %m ", MODULE_NAME, lt_calc, lt, $time); + end +end +endtask + +task upper_mix_drp; + output reg [2:0] pm_f; + output reg wf_f; + output reg cddc_en; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + pm_f = DI[15:13]; + wf_f = DI[12]; + cddc_en = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_frac_drp; + output reg cddc_en; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + cddc_en = DI[15]; + frac = DI[14:12]; + frac_en = DI[11]; + wf_r = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task upper_drp; + output reg cddc_en; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + input [15:0] DI; +begin + cddc_en = DI[10]; + mx = DI[9:8]; + e = DI[7]; + nc = DI[6]; + dt = DI[5:0]; +end +endtask + +task lower_drp; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input [15:0] DI; +begin + pm_r = DI[15:13]; + en = DI[12]; + ht = DI[11:6]; + lt = DI[5:0]; +end +endtask + +//ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div) +task ht_calc; + input [2:0] frac; + input frac_en; + input e; + input [5:0] ht; + input [6:0] lt; + input real f_div; + output [3:0] clk_rsel; + output [3:0] clk_fsel; + output [6:0] clk_fht; + output [6:0] clk_flt; + output integer clk_cnt_max; + output integer clk_cnt_ht; + output integer clk_div_fint; + + integer clk_div_fint_odd; +begin + clk_div_fint = $rtoi(f_div); + if (frac_en) begin + clk_fht = clk_div_fint / 2; + clk_flt = clk_div_fint / 2; + clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt; + if (clk_div_fint_odd > 0) begin + clk_rsel = (8 + frac) / 2; + clk_fsel = 8 + frac - clk_rsel; + end + else begin + clk_rsel = frac / 2; + clk_fsel = frac - clk_rsel; + end + end + else begin + if (ht == 6'b0) clk_fht = 64; else clk_fht = ht; + if (lt == 7'b0) clk_flt = 64; else clk_flt = lt; + clk_cnt_max = 2 * (clk_fht + clk_flt) - 1; + clk_cnt_ht = 2 * clk_fht + e; + end + +end +endtask + +task attr_to_mc; + output reg [2:0] pm_f; + output reg wf_f; + output reg [2:0] frac; + output reg frac_en; + output reg wf_r; + output reg [1:0] mx; + output reg e; + output reg nc; + output reg [5:0] dt; + output reg [2:0] pm_r; + output reg en; + output reg [5:0] ht; + output reg [5:0] lt; + input real div; + input real phase; + input real duty; + + integer div_int; + real div_frac; + real div_rnd; + + reg [37:0] vector; +begin + +// determine frac_en + div_int = $rtoi(div); + div_frac = div - $itor(div_int); + if (div_frac > 0.000) frac_en = 1'b1; + else frac_en = 1'b0; + +// rnd frac to nearest 0.125 - may become .000 + div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0; + +// determine int and frac part + div_int = $rtoi(div_rnd); + div_frac = div_rnd - $itor(div_int); + + if (frac_en == 1'b1) + vector = mmcm_frac_calc(div_int,phase*1000,duty*100000,div_frac*1000); + else + vector = mmcm_calc(div_int,phase*1000,duty*100000); + + if (frac_en == 1'b1) begin + pm_f = vector[35:33]; + wf_f = vector[32]; + frac = vector[30:28]; + frac_en = vector[27]; + wf_r = vector[26]; + end + else begin + pm_f = 3'b0; + wf_f = 1'b0; + frac = 3'b0; + frac_en = 1'b0; + wf_r = 1'b0; + end + mx = vector[25:24]; + e = vector[23]; + en = 1'b1; + if (div_int == 1) begin + nc = 1'b1; + ht = 6'b1; + lt = 6'b1; + end else begin + nc = vector[22]; + ht = vector[11:6]; + lt = vector[5:0]; + end + dt = vector[21:16]; + pm_r = vector[15:13]; +end +endtask + +`define MMCME4_ADV_FRAC_PRECISION 10 +`define MMCME4_ADV_FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`MMCME4_ADV_FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`MMCME4_ADV_FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`MMCME4_ADV_FIXED_WIDTH:1] precision + ); + + begin + + // If the fractional precision bit is high then round up + if( decimal[(`MMCME4_ADV_FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`MMCME4_ADV_FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`MMCME4_ADV_FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`MMCME4_ADV_FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `MMCME4_ADV_FRAC_PRECISION) / 100_000; + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + // comes from above round_frac + high_time = temp[`MMCME4_ADV_FRAC_PRECISION+7:`MMCME4_ADV_FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`MMCME4_ADV_FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`MMCME4_ADV_FIXED_WIDTH:1] phase_in_cycles; + reg [`MMCME4_ADV_FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`MMCME4_ADV_FIXED_WIDTH:1] temp; + + begin + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `MMCME4_ADV_FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `MMCME4_ADV_FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`MMCME4_ADV_FRAC_PRECISION:`MMCME4_ADV_FRAC_PRECISION-2]; + delay_time = temp[`MMCME4_ADV_FRAC_PRECISION+6:`MMCME4_ADV_FRAC_PRECISION+1]; + + // Setup the return value + mmcm_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + mmcm_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); +// $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_divider(divide, duty_cycle); //Not used since edge and no count are 0 when fractional + phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + end +endfunction + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_CHK = 1.0; + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + $display(" Instance %m "); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + integer para_in; + integer range_low; + integer range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; + end + endfunction + + function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + real para_in; + real range_low; + real range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); + $finish; + end + para_real_range_chk = 1'b0; + end + endfunction + +task check_m_settings; + input real clkfbout_f_div; + input [3:0] pll_cp; + input [3:0] pll_res; + input [4:0] drp_lock_ref_dly; + input [4:0] drp_lock_fb_dly; + input [9:0] drp_lock_cnt; + input [9:0] drp_unlock_cnt; + input [9:0] drp_lock_sat_high; + + integer clkfbout_div; + reg [3:0] pll_cp_low, pll_cp_high, pll_cp_optimized; + reg [3:0] pll_res_low, pll_res_high, pll_res_optimized; + reg [4:0] drp_lock_ref_dly_calc; + reg [4:0] drp_lock_fb_dly_calc; + reg [9:0] drp_lock_cnt_calc; + reg [9:0] drp_unlock_cnt_calc; + reg [9:0] drp_lock_sat_high_calc; + reg [47:0] actual; + reg [47:0] calc_low, calc_high, calc_optimized; + +begin + + actual = {pll_cp,pll_res,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_lock_sat_high,drp_unlock_cnt}; + clkfbout_div = $rtoi(clkfbout_f_div); + GetMultVal(clkfbout_div,nBandwidth_LOW,pll_cp_low,pll_res_low); + GetMultVal(clkfbout_div,nBandwidth_HIGH,pll_cp_high,pll_res_high); + GetMultVal(clkfbout_div,nBandwidth_OPTIMIZED,pll_cp_optimized,pll_res_optimized); + GetLockDetSettings(clkfbout_div,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc); + calc_low = {pll_cp_low,pll_res_low,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + calc_high = {pll_cp_high,pll_res_high,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + calc_optimized = {pll_cp_optimized,pll_res_optimized,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + + if (actual != calc_low && actual != calc_high && actual != calc_optimized) + $display("Error: [Unisim %s-35] Illegal cp, res, and/or lock DRP programming at time %t. Programmed vales do not match Bandwidth setting. Instance %m ", MODULE_NAME, $time); + +end +endtask + +task GetLockDetSettings (input integer fClkFbOutMultF, output [4:0] lock_ref_dly, output [4:0] lock_fb_dly, output [9:0] lock_cnt, output [9:0] lock_sat_high, output [9:0] unlock_cnt); + begin + lock_sat_high = 10'd1001; + unlock_cnt = 10'd1; + case (fClkFbOutMultF) + 1,2: begin + lock_ref_dly = 5'd6; + lock_fb_dly = 5'd6; + lock_cnt = 10'd1000; + end + 3: begin + lock_ref_dly = 5'd8; + lock_fb_dly = 5'd8; + lock_cnt = 10'd1000; + end + 4: begin + lock_ref_dly = 5'd11; + lock_fb_dly = 5'd11; + lock_cnt = 10'd1000; + end + 5: begin + lock_ref_dly = 5'd14; + lock_fb_dly = 5'd14; + lock_cnt = 10'd1000; + end + 6: begin + lock_ref_dly = 5'd17; + lock_fb_dly = 5'd17; + lock_cnt = 10'd1000; + end + 7: begin + lock_ref_dly = 5'd19; + lock_fb_dly = 5'd19; + lock_cnt = 10'd1000; + end + 8: begin + lock_ref_dly = 5'd22; + lock_fb_dly = 5'd22; + lock_cnt = 10'd1000; + end + 9: begin + lock_ref_dly = 5'd25; + lock_fb_dly = 5'd25; + lock_cnt = 10'd1000; + end + 10: begin + lock_ref_dly = 5'd28; + lock_fb_dly = 5'd28; + lock_cnt = 10'd1000; + end + 11: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd900; + end + 12: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd825; + end + 13: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd750; + end + 14: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd700; + end + 15: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd650; + end + 16: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd625; + end + 17: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd575; + end + 18: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd550; + end + 19: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd525; + end + 20: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd500; + end + 21: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd475; + end + 22: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd450; + end + 23: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd425; + end + 24,25: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd400; + end + 26: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd375; + end + 27,28: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd350; + end + 29,30: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd325; + end + 31,32,33: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd300; + end + 34,35,36: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd275; + end + default: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd250; + end + endcase + end +endtask + +task GetMultVal (input integer fClkFbOutMultF, input integer nBandwidth, output [3:0] cp, output [3:0] res); + begin + if ((nBandwidth == nBandwidth_HIGH) || (nBandwidth == nBandwidth_OPTIMIZED)) + case (fClkFbOutMultF) + 2: begin + cp = 4'd7; res = 4'd15; + end + 3: begin + cp = 4'd14; res = 4'd15; + end + 4: begin + cp = 4'd15; res = 4'd15; + end + 5: begin + cp = 4'd15; res = 4'd11; + end + 6: begin + cp = 4'd15; res = 4'd13; + end + 7: begin + cp = 4'd15; res = 4'd3; + end + 8: begin + cp = 4'd14; res = 4'd5; + end + 9,10: begin + cp = 4'd15; res = 4'd9; + end + 11: begin + cp = 4'd14; res = 4'd14; + end + 12: begin + cp = 4'd15; res = 4'd14; + end + 13,14,15: begin + cp = 4'd15; res = 4'd1; + end + 16,17: begin + cp = 4'd14; res = 4'd6; + end + 18: begin + cp = 4'd15; res = 4'd6; + end + 19,20: begin + cp = 4'd14; res = 4'd10; + end + 21,22,23,24,25: begin + cp = 4'd15; res = 4'd10; + end + 26,27,28: begin + cp = 4'd13; res = 4'd12; + end + 29,30,31: begin + cp = 4'd14; res = 4'd12; + end + 32,33,34,35,36,37: begin + cp = 4'd15; res = 4'd12; + end + 38,39,40,41: begin + cp = 4'd14; res = 4'd2; + end + 42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62: begin + cp = 4'd15; res = 4'd2; + end + 63,64,65,66,67,68,69,70: begin + cp = 4'd12; res = 4'd4; + end + 71,72,73,74,75,76,77: begin + cp = 4'd13; res = 4'd4; + end + 78,79,80,81,82,83,84,85: begin + cp = 4'd14; res = 4'd4; + end + 86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119: begin + cp = 4'd15; res = 4'd4; + end + 120,121,122,123,124,125,126,127,128: begin + cp = 4'd13; res = 4'd8; + end + endcase + else if (nBandwidth == nBandwidth_LOW) begin + case (fClkFbOutMultF) + 2: begin + cp = 4'd3; res = 4'd15; + end + 3: begin + cp = 4'd3; res = 4'd13; + end + 4: begin + cp = 4'd3; res = 4'd5; + end + 5: begin + cp = 4'd3; res = 4'd9; + end + 6,7: begin + cp = 4'd3; res = 4'd14; + end + 8: begin + cp = 4'd3; res = 4'd1; + end + 9,10,11: begin + cp = 4'd3; res = 4'd6; + end + 12,13,14: begin + cp = 4'd3; res = 4'd10; + end + 15: begin + cp = 4'd4; res = 4'd6; + end + 16: begin + cp = 4'd3; res = 4'd12; + end + 17: begin + cp = 4'd14; res = 4'd6; + end + 18: begin + cp = 4'd15; res = 4'd6; + end + 19,20: begin + cp = 4'd14; res = 4'd10; + end + 21,22,23,24,25: begin + cp = 4'd15; res = 4'd10; + end + 26,27,28: begin + cp = 4'd13; res = 4'd12; + end + 29,30,31: begin + cp = 4'd14; res = 4'd12; + end + 32,33,34,35,36,37: begin + cp = 4'd15; res = 4'd12; + end + 38,39,40,41: begin + cp = 4'd14; res = 4'd2; + end + 42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62: begin + cp = 4'd15; res = 4'd2; + end + 63,64,65,66,67,68,69,70: begin + cp = 4'd12; res = 4'd4; + end + 71,72,73,74,75,76,77: begin + cp = 4'd13; res = 4'd4; + end + 78,79,80,81,82,83,84,85: begin + cp = 4'd14; res = 4'd4; + end + 86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119: begin + cp = 4'd15; res = 4'd4; + end + 120,121,122,123,124,125,126,127,128: begin + cp = 4'd13; res = 4'd8; + end + endcase + end + end +endtask + +// end behavioral model + +`ifndef XIL_XECLIB + specify + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (PSCLK => PSDONE) = (100:100:100, 100:100:100); + (negedge PWRDWN => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge PWRDWN => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge PWRDWN => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge PWRDWN => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge PWRDWN => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge PWRDWN => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKFBOUTB, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKIN2, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT2B, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT3B, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge CLKOUT6, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge PSCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKFBOUTB, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKIN2, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT2B, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT3B, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge CLKOUT6, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge PSCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); + $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge CLKIN2, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PSCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge CLKIN2, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PSCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MMCME4_BASE.v b/verilog/src/unisims/MMCME4_BASE.v new file mode 100644 index 0000000..3d43a74 --- /dev/null +++ b/verilog/src/unisims/MMCME4_BASE.v @@ -0,0 +1,297 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Base Mixed Mode Clock Manager (MMCM) +// /___/ /\ Filename : MMCME4_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MMCME4_BASE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKFBOUTB, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output LOCKED, + + input CLKFBIN, + input CLKIN1, + input PWRDWN, + input RST +); + +// define constants + localparam MODULE_NAME = "MMCME4_BASE"; + + reg trig_attr = 1'b0; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + + wire CLKFBIN_in; + wire CLKIN1_in; + wire PWRDWN_in; + wire RST_in; + + assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0 + assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0 + assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0 + assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0 + + initial begin + #1; + trig_attr = ~trig_attr; + end + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + +end +`endif + +`ifndef XIL_XECLIB + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end +`endif + + wire CDDCDONE; + wire DRDY; + wire PSDONE; + wire CLKFBSTOPPED; + wire CLKINSTOPPED; + wire [15:0] DO; + MMCME4_ADV #( + .BANDWIDTH(BANDWIDTH), + .CLKFBOUT_MULT_F(CLKFBOUT_MULT_F), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN1_PERIOD), + .CLKIN2_PERIOD(10), + .CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_CASCADE(CLKOUT4_CASCADE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .CLKOUT6_DIVIDE(CLKOUT6_DIVIDE), + .CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE), + .CLKOUT6_PHASE(CLKOUT6_PHASE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .REF_JITTER1(REF_JITTER1), + .STARTUP_WAIT(STARTUP_WAIT) + ) mmcm_adv_1 ( + .CDDCDONE (CDDCDONE), + .CLKFBOUT (CLKFBOUT), + .CLKFBOUTB (CLKFBOUTB), + .CLKFBSTOPPED(CLKFBSTOPPED), + .CLKINSTOPPED(CLKINSTOPPED), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUT2 (CLKOUT2), + .CLKOUT2B (CLKOUT2B), + .CLKOUT3 (CLKOUT3), + .CLKOUT3B (CLKOUT3B), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .CLKOUT6 (CLKOUT6), + .DO (DO), + .DRDY (DRDY), + .LOCKED (LOCKED), + .PSDONE(PSDONE), + .CDDCREQ (1'b0), + .CLKFBIN (CLKFBIN_in), + .CLKIN1 (CLKIN1_in), + .CLKIN2 (1'b0), + .CLKINSEL(1'b1), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(PWRDWN_in), + .RST (RST_in) + ); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKFBOUTB, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT2B, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT3B, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge CLKOUT6, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKFBOUTB, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT2B, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT3B, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge CLKOUT6, 0:0:0, notifier); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/MUXCY.v b/verilog/src/unisims/MUXCY.v new file mode 100644 index 0000000..44ee115 --- /dev/null +++ b/verilog/src/unisims/MUXCY.v @@ -0,0 +1,78 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Multiplexer for Carry Logic with General Output +// /___/ /\ Filename : MUXCY.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module MUXCY (O, CI, DI, S); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + input CI, DI, S; + + reg O_out; + + always @(CI or DI or S) + if (S) + O_out = CI; + else + O_out = DI; + + assign O = O_out; + +`ifdef XIL_TIMING + + specify + + (CI => O) = (0:0:0, 0:0:0); + (DI => O) = (0:0:0, 0:0:0); + (S => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/MUXF7.v b/verilog/src/unisims/MUXF7.v new file mode 100644 index 0000000..5a9b5d3 --- /dev/null +++ b/verilog/src/unisims/MUXF7.v @@ -0,0 +1,77 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF7.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module MUXF7 (O, I0, I1, S); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + input I0, I1, S; + + reg O_out; + + always @(I0 or I1 or S) + if (S) + O_out = I1; + else + O_out = I0; + + assign O = O_out; + +`ifdef XIL_TIMING + + specify + + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (S => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/MUXF8.v b/verilog/src/unisims/MUXF8.v new file mode 100644 index 0000000..735f924 --- /dev/null +++ b/verilog/src/unisims/MUXF8.v @@ -0,0 +1,78 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module MUXF8 (O, I0, I1, S); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + input I0, I1, S; + + reg O_out; + + always @(I0 or I1 or S) + if (S) + O_out = I1; + else + O_out = I0; + + assign O = O_out; + +`ifdef XIL_TIMING + + specify + + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (S => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/MUXF9.v b/verilog/src/unisims/MUXF9.v new file mode 100644 index 0000000..1e3c33c --- /dev/null +++ b/verilog/src/unisims/MUXF9.v @@ -0,0 +1,77 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : +// / / +// /__/ /\ Filename : MUXF9.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/unified/chen/g2ltw/g2ltw.pl +// Revision: 1.0 +// 09/26/12 - 680234 - ncsim compile error +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module MUXF9 + `ifdef XIL_TIMING //Simprim +#( + parameter LOC = "UNPLACED" +) + `endif +( + output O, + + input I0, + input I1, + input S +); + + reg O_out; + + always @(I0 or I1 or S) + if (S) + O_out = I1; + else + O_out = I0; + + assign O = O_out; + +`ifdef XIL_TIMING + + specify + + + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (S => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + + endspecify + +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUF.v b/verilog/src/unisims/OBUF.v new file mode 100644 index 0000000..3ab659b --- /dev/null +++ b/verilog/src/unisims/OBUF.v @@ -0,0 +1,89 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer +// /___/ /\ Filename : OBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +`celldefine + +module OBUF (O, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + parameter SLEW = "SLOW"; + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + #1 $finish; + end + + endcase + + end + + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + + +endmodule + +`endcelldefine + + + + diff --git a/verilog/src/unisims/OBUFDS.v b/verilog/src/unisims/OBUFDS.v new file mode 100644 index 0000000..186a18a --- /dev/null +++ b/verilog/src/unisims/OBUFDS.v @@ -0,0 +1,87 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Differential Signaling Output Buffer +// /___/ /\ Filename : OBUFDS.v +// \ \ / \ Timestamp : Tue Mar 1 14:57:54 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/01/05 - Added global GTS. +// 03/01/05 - Added LOC parameter. +// 05/23/05 - Declared tri0 GTS. +// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps/1 ps + +`celldefine + +module OBUFDS (O, OB, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + + output O, OB; + + input I; + tri0 GTS = glbl.GTS; + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + #1 $finish; + end + + endcase + + end + + bufif0 (O, I, GTS); + notif0 (OB, I, GTS); + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_DPHY.v b/verilog/src/unisims/OBUFDS_DPHY.v new file mode 100644 index 0000000..0bfa8cc --- /dev/null +++ b/verilog/src/unisims/OBUFDS_DPHY.v @@ -0,0 +1,149 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / _no_description_ +// /___/ /\ Filename : OBUFDS_DPHY.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFDS_DPHY #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter IOSTANDARD = "DEFAULT" +)( + output O, + output OB, + + input HSTX_I, + input HSTX_T, + input LPTX_I_N, + input LPTX_I_P, + input LPTX_T +); + +// define constants + localparam MODULE_NAME = "OBUFDS_DPHY"; + +// Parameter encodings and registers + localparam IOSTANDARD_DEFAULT = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OBUFDS_DPHY_dr.v" +`else + localparam [56:1] IOSTANDARD_REG = IOSTANDARD; +`endif + + wire IOSTANDARD_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg OB_out; + reg O_out; + + wire HSTX_I_in; + wire HSTX_T_in; + wire LPTX_I_N_in; + wire LPTX_I_P_in; + wire LPTX_T_in; + + reg hs_mode = 1'b1; + + assign (strong1,strong0) O = (hs_mode === 1'b0) ? O_out : 1'bz; + assign (strong1, strong0) OB = (hs_mode === 1'b0) ? OB_out : 1'bz; + assign (supply1,supply0) O = (hs_mode === 1'b1) ? O_out : 1'bz; + assign (supply1,supply0) OB = (hs_mode === 1'b1) ? OB_out : 1'bz; + + assign HSTX_I_in = HSTX_I; + assign HSTX_T_in = HSTX_T; + assign LPTX_I_N_in = LPTX_I_N; + assign LPTX_I_P_in = LPTX_I_P; + assign LPTX_T_in = LPTX_T; + + assign IOSTANDARD_BIN = + (IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT : + IOSTANDARD_DEFAULT; + +//Commenting out the DRC check for IOSTANDARD attribute as it is not required as per IOTST. +/* initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((IOSTANDARD_REG != "DEFAULT"))) begin + $display("Error: [Unisim %s-101] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +*/ + always @ (LPTX_T_in or HSTX_T_in or LPTX_I_P_in or LPTX_I_N_in or HSTX_I_in) begin + if (LPTX_T_in === 1'b0) begin + O_out <= LPTX_I_P_in; + OB_out <= LPTX_I_N_in; + hs_mode <= 1'b0; + end else if (LPTX_T_in === 1'b1 && HSTX_T_in === 1'b0) begin + O_out <= HSTX_I_in; + OB_out <= ~HSTX_I_in; + hs_mode <= 1'b1; + end else begin + O_out <= 1'bz; + OB_out <= 1'bz; + hs_mode <= 1'bx; + end + end + +specify + (HSTX_I => O) = (0:0:0, 0:0:0); + (HSTX_I => OB) = (0:0:0, 0:0:0); + (HSTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); + (HSTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); + (LPTX_I_N => OB) = (0:0:0, 0:0:0); + (LPTX_I_P => O) = (0:0:0, 0:0:0); + (LPTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); + (LPTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; +endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTE3.v b/verilog/src/unisims/OBUFDS_GTE3.v new file mode 100644 index 0000000..5ba1aa7 --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTE3.v @@ -0,0 +1,102 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : OBUFDS_GTE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 12/11/2012 - Initial version +// 03/22/2013 - Model added +// 03/25/2013 - Sync 5 YML & model update +// 04/12/2013 - Add attribute section +// 08/28/2013 - Remove REFCLKOUT_CLKOUT_SEL, Add specify section +// 06/02/2014 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + + +`timescale 1 ps / 1 ps + +`celldefine +module OBUFDS_GTE3 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000 +)( + output O, + output OB, + + input CEB, + input I +); + +// define constants + + localparam MODULE_NAME = "OBUFDS_GTE3"; + // Parameter encodings and registers + + `ifndef XIL_DR + localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; + `endif + wire REFCLK_EN_TX_PATH_BIN; + wire [4:0] REFCLK_ICNTL_TX_BIN; + + tri0 GTS = glbl.GTS; + tri0 glblGSR = glbl.GSR; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + +// include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "OBUFDS_GTE3_dr.v" + `endif + + assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG; + + assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG; + + wire t1; + wire t2; + + or O1 (t1, GTS, CEB); + or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1); + bufif0 B1 (O, I, t2); + notif0 N1 (OB, I, t2); + + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTE3_ADV.v b/verilog/src/unisims/OBUFDS_GTE3_ADV.v new file mode 100644 index 0000000..5dbe5f8 --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTE3_ADV.v @@ -0,0 +1,126 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : OBUFDS_GTE3_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 08/28/2013 - Initial model +// 06/02/14 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine +module OBUFDS_GTE3_ADV #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000 +)( + output O, + output OB, + + input CEB, + input [3:0] I, + input [1:0] RXRECCLK_SEL +); + +// define constants + localparam MODULE_NAME = "OBUFDS_GTE3_ADV"; + + reg I_delay; + +// Parameter encodings and registers + + `ifndef XIL_DR + localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; + `endif + + wire REFCLK_EN_TX_PATH_BIN; + wire [4:0] REFCLK_ICNTL_TX_BIN; + + + tri0 GTS = glbl.GTS; + tri0 glblGSR = glbl.GSR; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + +// include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "OBUFDS_GTE3_ADV_dr.v" + `endif + + assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG; + + assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG; + + wire t1; + wire t2; + + or O1 (t1, GTS, CEB); + or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1); + + + // ===================== + // Generate I_delay + // ===================== + always @(*) begin + case (RXRECCLK_SEL) + 2'b00: I_delay <= I[0]; + 2'b01: I_delay <= I[1]; + 2'b10: I_delay <= I[2]; + 2'b11: I_delay <= I[3]; + default : I_delay <= I[0]; + endcase + end + + bufif0 B1 (O, I_delay, t2); + notif0 N1 (OB, I_delay, t2); + + + specify + (I[0] => O) = (0:0:0, 0:0:0); + (I[0] => OB) = (0:0:0, 0:0:0); + (I[1] => O) = (0:0:0, 0:0:0); + (I[1] => OB) = (0:0:0, 0:0:0); + (I[2] => O) = (0:0:0, 0:0:0); + (I[2] => OB) = (0:0:0, 0:0:0); + (I[3] => O) = (0:0:0, 0:0:0); + (I[3] => OB) = (0:0:0, 0:0:0); + (CEB => O) = (0:0:0, 0:0:0); + (CEB => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + + + endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTE4.v b/verilog/src/unisims/OBUFDS_GTE4.v new file mode 100644 index 0000000..1a1685d --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTE4.v @@ -0,0 +1,95 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver Buffer +// /___/ /\ Filename : OBUFDS_GTE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/27/2015 - Initial version from E3 +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFDS_GTE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000 +)( + output O, + output OB, + + input CEB, + input I +); + +// define constants + localparam MODULE_NAME = "OBUFDS_GTE4"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OBUFDS_GTE4_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +reg glblGTS = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +tri0 glblGTS = glbl.GTS; +`endif + + +// wire CEB_in; +// wire I_in; + +// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0 +// assign I_in = I; + +// ===================== +// Generate O +// ===================== + + assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I; + assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I; + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTE4_ADV.v b/verilog/src/unisims/OBUFDS_GTE4_ADV.v new file mode 100644 index 0000000..481e1b0 --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTE4_ADV.v @@ -0,0 +1,121 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Gigabit Transceiver Buffer +// /___/ /\ Filename : OBUFDS_GTE4_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/27/2015 - Initial version from E3 +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFDS_GTE4_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000 +)( + output O, + output OB, + + input CEB, + input [3:0] I, + input [1:0] RXRECCLK_SEL +); + +// define constants + localparam MODULE_NAME = "OBUFDS_GTE4_ADV"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OBUFDS_GTE4_ADV_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; + reg glblGTS = glbl.GTS; +`else + tri0 glblGSR = glbl.GSR; + tri0 glblGTS = glbl.GTS; +`endif + + reg attr_err = 1'b0; + +// wire CEB_in; +// wire [1:0] RXRECCLK_SEL_in; +// wire [3:0] I_in; + +// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0 +// assign I_in = I; +// assign RXRECCLK_SEL_in = RXRECCLK_SEL; + + reg I_sel = 1'b0; +// ===================== +// Generate I_sel +// ===================== + always @(*) begin + case (RXRECCLK_SEL) + 2'b00: I_sel <= I[0]; + 2'b01: I_sel <= I[1]; + 2'b10: I_sel <= I[2]; + 2'b11: I_sel <= I[3]; + default : I_sel <= I[0]; + endcase + end + +// ===================== +// Generate O +// ===================== + + assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I_sel; + assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I_sel; + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (CEB => O) = (0:0:0, 0:0:0); + (CEB => OB) = (0:0:0, 0:0:0); + (I[0] => O) = (0:0:0, 0:0:0); + (I[0] => OB) = (0:0:0, 0:0:0); + (I[1] => O) = (0:0:0, 0:0:0); + (I[1] => OB) = (0:0:0, 0:0:0); + (I[2] => O) = (0:0:0, 0:0:0); + (I[2] => OB) = (0:0:0, 0:0:0); + (I[3] => O) = (0:0:0, 0:0:0); + (I[3] => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTM.v b/verilog/src/unisims/OBUFDS_GTM.v new file mode 100644 index 0000000..3dfeb23 --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTM.v @@ -0,0 +1,144 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / OBUFDS_GTM +// /___/ /\ Filename : OBUFDS_GTM.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFDS_GTM #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter integer REFCLK_ICNTL_TX = 0 +)( + output O, + output OB, + + input CEB, + input I +); + +// define constants + localparam MODULE_NAME = "OBUFDS_GTM"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OBUFDS_GTM_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; +`endif + +`ifdef XIL_XECLIB + wire [3:0] REFCLK_ICNTL_TX_BIN; +`else + reg [3:0] REFCLK_ICNTL_TX_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +reg glblGTS = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +tri0 glblGTS = glbl.GTS; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0]; + +`else + always @ (trig_attr) begin + #1; + REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0]; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((REFCLK_ICNTL_TX_REG != 0) && + (REFCLK_ICNTL_TX_REG != 1) && + (REFCLK_ICNTL_TX_REG != 3) && + (REFCLK_ICNTL_TX_REG != 7) && + (REFCLK_ICNTL_TX_REG != 15))) begin + $display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +// begin behavioral model + +// ===================== +// Generate O +// ===================== + + assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I; + assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I; + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFDS_GTM_ADV.v b/verilog/src/unisims/OBUFDS_GTM_ADV.v new file mode 100644 index 0000000..038aec4 --- /dev/null +++ b/verilog/src/unisims/OBUFDS_GTM_ADV.v @@ -0,0 +1,170 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / OBUFDS_GTM_ADV +// /___/ /\ Filename : OBUFDS_GTM_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFDS_GTM_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0, + parameter integer REFCLK_ICNTL_TX = 0, + parameter [1:0] RXRECCLK_SEL = 2'b00 +)( + output O, + output OB, + + input CEB, + input [3:0] I +); + +// define constants + localparam MODULE_NAME = "OBUFDS_GTM_ADV"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OBUFDS_GTM_ADV_dr.v" +`else + reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH; + reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX; + reg [1:0] RXRECCLK_SEL_REG = RXRECCLK_SEL; +`endif + +`ifdef XIL_XECLIB + wire [3:0] REFCLK_ICNTL_TX_BIN; +`else + reg [3:0] REFCLK_ICNTL_TX_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +reg glblGTS = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +tri0 glblGTS = glbl.GTS; +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0]; + +`else + always @ (trig_attr) begin + #1; + REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0]; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((REFCLK_ICNTL_TX_REG != 0) && + (REFCLK_ICNTL_TX_REG != 1) && + (REFCLK_ICNTL_TX_REG != 3) && + (REFCLK_ICNTL_TX_REG != 7) && + (REFCLK_ICNTL_TX_REG != 15))) begin + $display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +// begin behavioral model + + reg I_sel = 1'b0; +// ===================== +// Generate I_sel +// ===================== + always @(*) begin + case (RXRECCLK_SEL_REG) + 2'b00: I_sel <= I[0]; + 2'b01: I_sel <= I[1]; + 2'b10: I_sel <= I[2]; + 2'b11: I_sel <= I[3]; + default : I_sel <= I[0]; + endcase + end + +// ===================== +// Generate O +// ===================== + + assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I_sel; + assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I_sel; + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + specify + (CEB => O) = (0:0:0, 0:0:0); + (CEB => OB) = (0:0:0, 0:0:0); + (I[0] => O) = (0:0:0, 0:0:0); + (I[0] => OB) = (0:0:0, 0:0:0); + (I[1] => O) = (0:0:0, 0:0:0); + (I[1] => OB) = (0:0:0, 0:0:0); + (I[2] => O) = (0:0:0, 0:0:0); + (I[2] => OB) = (0:0:0, 0:0:0); + (I[3] => O) = (0:0:0, 0:0:0); + (I[3] => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif +`endif + + + +// end behavioral model + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFT.v b/verilog/src/unisims/OBUFT.v new file mode 100644 index 0000000..8ebae6b --- /dev/null +++ b/verilog/src/unisims/OBUFT.v @@ -0,0 +1,92 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer +// /___/ /\ Filename : OBUFT.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +`celldefine + +module OBUFT (O, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + parameter SLEW = "SLOW"; + + output O; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + #1 $finish; + end + + endcase + + end + + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0, + 0:0:0, 0:0:0, + 0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/OBUFTDS.v b/verilog/src/unisims/OBUFTDS.v new file mode 100644 index 0000000..a76e465 --- /dev/null +++ b/verilog/src/unisims/OBUFTDS.v @@ -0,0 +1,96 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer +// /___/ /\ Filename : OBUFTDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFTDS (O, OB, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + +`ifdef XIL_TIMING + + parameter LOC = " UNPLACED"; + +`endif + + parameter SLEW = "SLOW"; + + + output O, OB; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFTDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + #1 $finish; + end + + endcase + + end + + +`ifdef XIL_TIMING + + specify + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0, + 0:0:0, 0:0:0, + 0:0:0, 0:0:0); + (T => OB) = (0:0:0, 0:0:0, + 0:0:0, 0:0:0, + 0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +`endif + + +endmodule + +`endcelldefine + + diff --git a/verilog/src/unisims/OBUFTDS_DCIEN.v b/verilog/src/unisims/OBUFTDS_DCIEN.v new file mode 100644 index 0000000..fa32e05 --- /dev/null +++ b/verilog/src/unisims/OBUFTDS_DCIEN.v @@ -0,0 +1,76 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 3-State Differential Signaling Output Buffer +// /___/ /\ Filename : OBUFTDS_DCIEN.v +// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010 +// \___\/\___\ +// +// Revision: +// 04/29/10 - Initial version. +// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim +// 06/10/11 - CR 584500 - added attribute SLEW +// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T); + + parameter IOSTANDARD = "DEFAULT"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter SLEW = "SLOW"; + + output O; + output OB; + + input DCITERMDISABLE; + input I; + input T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +`ifdef XIL_TIMING + specify + (DCITERMDISABLE => O) = (0:0:0, 0:0:0); + (DCITERMDISABLE => OB) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (I => OB) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + (T => OB) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OBUFT_DCIEN.v b/verilog/src/unisims/OBUFT_DCIEN.v new file mode 100644 index 0000000..c3f570a --- /dev/null +++ b/verilog/src/unisims/OBUFT_DCIEN.v @@ -0,0 +1,73 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 3-State Output Buffer +// /___/ /\ Filename : OBUFT_DCIEN.v +// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010 +// \___\/\___\ +// +// Revision: +// 04/29/10 - Initial version. +// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim +// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module OBUFT_DCIEN (O, DCITERMDISABLE, I, T); + + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif // `ifdef XIL_TIMING + parameter SLEW = "SLOW"; + + output O; + + input DCITERMDISABLE; + input I; + input T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +`ifdef XIL_TIMING + specify + (DCITERMDISABLE => O) = (0:0:0, 0:0:0); + (I => O) = (0:0:0, 0:0:0); + (T => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // `ifdef XIL_TIMING + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/ODDR.v b/verilog/src/unisims/ODDR.v new file mode 100644 index 0000000..d2db266 --- /dev/null +++ b/verilog/src/unisims/ODDR.v @@ -0,0 +1,296 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop +// /___/ /\ Filename : ODDR.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outputs. +// 05/29/07 - Added wire declaration for internal signals +// 04/17/08 - CR 468871 Negative SetupHold fix +// 05/12/08 - CR 455447 add XON MSGON property to support async reg +// 12/03/08 - CR 498674 added pulldown on R/S. +// 07/28/09 - CR 527698 According to holistic, CE has to be high for both rise/fall CLK +// - If CE is low on the rising edge, it has an effect of no change in the falling CLK. +// 06/23/10 - CR 566394 Removed extra recrem checks +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/13/12 - CR 591320 fixed SU/H checks in OPPOSITE edge mode. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ODDR (Q, C, CE, D1, D2, R, S); + + output Q; + + input C; + input CE; + input D1; + input D2; + input R; + input S; + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + + parameter SRTYPE = "SYNC"; +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; +`endif + + localparam MODULE_NAME = "ODDR"; + + pulldown P1 (R); + pulldown P2 (S); + + reg q_out = INIT, qd2_posedge_int; +`ifdef XIL_TIMING + reg notifier; + wire notifierx; +`endif + tri0 GSR = glbl.GSR; + + wire c_in,delay_c; + wire ce_in,delay_ce; + wire d1_in,delay_d1; + wire d2_in,delay_d2; + wire gsr_in; + wire r_in,delay_r; + wire s_in,delay_s; + + assign gsr_in = GSR; + assign Q = q_out; + +`ifdef XIL_TIMING + + wire nr, ns, ngsr; + wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable; + wire ce_c_enable1, d1_c_enable1, d2_c_enable1, d2_c_enable2, r_c_enable1, s_c_enable1; + + not (nr, R); + not (ns, S); + not (ngsr, GSR); + + and (ce_c_enable, ngsr, nr, ns); + and (d_c_enable, ngsr, nr, ns, CE); + and (s_c_enable, ngsr, nr); + + assign notifierx = (XON == "FALSE") ? 1'bx : notifier; + + assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable; + assign d1_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable; + assign d2_c_enable1 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "OPPOSITE_EDGE")) ? 1'b0 : d_c_enable; // SAME_EDGE case, D2 to posedge C + assign d2_c_enable2 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "SAME_EDGE")) ? 1'b0 : d_c_enable; // OPPOSITE_EDGE case, D2 to negedge C + assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr; + assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable; + +`endif + + initial begin + + if ((INIT != 0) && (INIT != 1)) begin + $display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT); + #1 $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE); + #1 $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE); + #1 $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q_out = INIT; + assign qd2_posedge_int = INIT; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b0; + assign qd2_posedge_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b1; + assign qd2_posedge_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q_out; + deassign qd2_posedge_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q_out; + deassign qd2_posedge_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q_out <= 1'b0; + qd2_posedge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q_out <= 1'b1; + qd2_posedge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q_out <= d1_in; + qd2_posedge_int <= d2_in; + end +// CR 527698 + else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin + qd2_posedge_int <= q_out; + end + end // always @ (posedge c_in) + + + always @(negedge c_in) begin + if (r_in == 1'b1) + q_out <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q_out <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + if (DDR_CLK_EDGE == "SAME_EDGE") + q_out <= qd2_posedge_int; + else if (DDR_CLK_EDGE == "OPPOSITE_EDGE") + q_out <= d2_in; + end + end // always @ (negedge c_in) + +`ifndef XIL_TIMING + + assign delay_c = C; + assign delay_ce = CE; + assign delay_d1 = D1; + assign delay_d2 = D2; + assign delay_r = R; + assign delay_s = S; + +`endif + assign c_in = IS_C_INVERTED ^ delay_c; + assign ce_in = delay_ce; + assign d1_in = IS_D1_INVERTED ^ delay_d1; + assign d2_in = IS_D2_INVERTED ^ delay_d2; + assign r_in = delay_r; + assign s_in = delay_s; + + +//*** Timing Checks Start here + +`ifdef XIL_TIMING + + wire c_en_n; + wire c_en_p; + wire ce_c_enable1_n,d1_c_enable1_n,d2_c_enable2_n,r_c_enable1_n,s_c_enable1_n; + wire ce_c_enable1_p,d1_c_enable1_p,d2_c_enable2_p,r_c_enable1_p,s_c_enable1_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + assign ce_c_enable1_n = ce_c_enable1 && c_en_n; + assign ce_c_enable1_p = ce_c_enable1 && c_en_p; + assign d1_c_enable1_n = d1_c_enable1 && c_en_n; + assign d1_c_enable1_p = d1_c_enable1 && c_en_p; + assign d2_c_enable2_n = d2_c_enable2 && c_en_n; + assign d2_c_enable2_p = d2_c_enable2 && c_en_p; + assign r_c_enable1_n = r_c_enable1 && c_en_n; + assign r_c_enable1_p = r_c_enable1 && c_en_p; + assign s_c_enable1_p = s_c_enable1 && c_en_p; + assign s_c_enable1_n = s_c_enable1 && c_en_n; + + always @(notifierx) begin + q_out <= 1'bx; + end + +`endif + + specify + + (C => Q) = (100:100:100, 100:100:100); + (posedge R => (Q +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q +: 0)) = (0:0:0, 0:0:0); + +`ifdef XIL_TIMING + (R => Q) = (0:0:0, 0:0:0); + (S => Q) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + $recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n); + $recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p); + $recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n); + $recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p); + $recrem ( posedge R, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n); + $recrem ( posedge R, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p); + $recrem ( posedge S, negedge C, 0:0:0, 0:0:0, notifier,c_en_n,c_en_n); + $recrem ( posedge S, posedge C, 0:0:0, 0:0:0, notifier,c_en_p,c_en_p); + $setuphold (negedge C, negedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce); + $setuphold (negedge C, negedge D1 &&& (d1_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1); + $setuphold (negedge C, negedge D2 &&& (d2_c_enable2_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2); + $setuphold (negedge C, negedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r); + $setuphold (negedge C, negedge S &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s); + $setuphold (negedge C, posedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce); + $setuphold (negedge C, posedge D1 &&& (d1_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1); + $setuphold (negedge C, posedge D2 &&& (d2_c_enable2_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2); + $setuphold (negedge C, posedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r); + $setuphold (negedge C, posedge S &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s); + $setuphold (posedge C, negedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce); + $setuphold (posedge C, negedge D1 &&& (d1_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1); + $setuphold (posedge C, negedge D2 &&& (d2_c_enable2_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2); + $setuphold (posedge C, negedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r); + $setuphold (posedge C, negedge S &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s); + $setuphold (posedge C, posedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce); + $setuphold (posedge C, posedge D1 &&& (d1_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1); + $setuphold (posedge C, posedge D2 &&& (d2_c_enable2_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2); + $setuphold (posedge C, posedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r); + $setuphold (posedge C, posedge S &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s); + $width (negedge C, 0:0:0, 0, notifier); + $width (negedge R, 0:0:0, 0, notifier); + $width (negedge S, 0:0:0, 0, notifier); + $width (posedge C, 0:0:0, 0, notifier); + $width (posedge R, 0:0:0, 0, notifier); + $width (posedge S, 0:0:0, 0, notifier); + +`endif + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ODDR + +`endcelldefine + diff --git a/verilog/src/unisims/ODDRE1.v b/verilog/src/unisims/ODDRE1.v new file mode 100644 index 0000000..7fa701d --- /dev/null +++ b/verilog/src/unisims/ODDRE1.v @@ -0,0 +1,339 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / ODDRE1 +// /___/ /\ Filename : ODDRE1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ODDRE1 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D1_INVERTED = 1'b0, + parameter [0:0] IS_D2_INVERTED = 1'b0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter [0:0] SRVAL = 1'b0 +)( + output Q, + + input C, + input D1, + input D2, + input SR +); + +// define constants + localparam MODULE_NAME = "ODDRE1"; + +// Parameter encodings and registers + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 2; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES2 = 3; + localparam SIM_DEVICE_VERSAL_AI_CORE = 5; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 6; + localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 7; + localparam SIM_DEVICE_VERSAL_AI_EDGE = 8; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 9; + localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 10; + localparam SIM_DEVICE_VERSAL_AI_RF = 11; + localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 12; + localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 13; + localparam SIM_DEVICE_VERSAL_HBM = 16; + localparam SIM_DEVICE_VERSAL_HBM_ES1 = 17; + localparam SIM_DEVICE_VERSAL_HBM_ES2 = 18; + localparam SIM_DEVICE_VERSAL_PREMIUM = 19; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 20; + localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 21; + localparam SIM_DEVICE_VERSAL_PRIME = 22; + localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 23; + localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 24; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "ODDRE1_dr.v" +`else + reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; + reg [0:0] IS_D1_INVERTED_REG = IS_D1_INVERTED; + reg [0:0] IS_D2_INVERTED_REG = IS_D2_INVERTED; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [0:0] SRVAL_REG = SRVAL; +`endif + +`ifdef XIL_XECLIB + wire [4:0] SIM_DEVICE_BIN; +`else + reg [4:0] SIM_DEVICE_BIN; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire C_in; + wire D1_in; + wire D2_in; + wire SR_in; + +`ifdef XIL_TIMING + wire C_delay; + wire D1_delay; + wire D2_delay; + wire SR_delay; +`endif + +`ifdef XIL_TIMING + assign C_in = C_delay ^ IS_C_INVERTED_REG; + assign D1_in = D1_delay ^ IS_D1_INVERTED_REG; + assign D2_in = D2_delay ^ IS_D2_INVERTED_REG; + assign SR_in = (SR !== 1'bz) && SR_delay; // rv 0 +`else + assign C_in = C ^ IS_C_INVERTED_REG; + assign D1_in = D1 ^ IS_D1_INVERTED_REG; + assign D2_in = D2 ^ IS_D2_INVERTED_REG; + assign SR_in = (SR !== 1'bz) && SR; // rv 0 +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + +`else + always @ (trig_attr) begin + #1; + SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 : + (SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 : + (SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 : + (SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM : + (SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 : + (SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 : + (SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 : + (SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 : + (SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 : + SIM_DEVICE_ULTRASCALE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") && + (SIM_DEVICE_REG != "VERSAL_AI_RF") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") && + (SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") && + (SIM_DEVICE_REG != "VERSAL_HBM") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES1") && + (SIM_DEVICE_REG != "VERSAL_HBM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") && + (SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") && + (SIM_DEVICE_REG != "VERSAL_PRIME") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES1") && + (SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin + $display("Error: [Unisim %s-105] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg Q_out; + reg QD2_posedge_int; + reg R_sync1 = 1'b0; + reg R_sync2 = 1'b0; + reg R_sync3 = 1'b0; + wire R_sync; + wire R_async; + + assign Q = Q_out; + assign R_async = ((SIM_DEVICE_BIN != SIM_DEVICE_ULTRASCALE) && (SIM_DEVICE_BIN != SIM_DEVICE_ULTRASCALE_PLUS) && (SIM_DEVICE_BIN != SIM_DEVICE_ULTRASCALE_PLUS_ES1) && (SIM_DEVICE_BIN != SIM_DEVICE_ULTRASCALE_PLUS_ES2)); + assign R_sync = R_async ? SR_in : (R_sync1 || R_sync2 || R_sync3); + + always @(posedge C_in) begin + if (~R_async) begin + R_sync1 <= SR_in; + R_sync2 <= R_sync1; + R_sync3 <= R_sync2; + end + end + + always @ (glblGSR or SR_in or R_sync) begin + if (glblGSR == 1'b1) begin + assign Q_out = SRVAL_REG; + assign QD2_posedge_int = SRVAL_REG; + end else if (glblGSR == 1'b0) begin + if (SR_in == 1'b1 || R_sync == 1'b1) begin + assign Q_out = SRVAL_REG; + assign QD2_posedge_int = SRVAL_REG; + end else if (R_sync == 1'b0) begin + deassign Q_out; + deassign QD2_posedge_int; + end + end + end + + always @(posedge C_in) begin + if (SR_in == 1'b1 || R_sync ==1'b1) begin + Q_out <= SRVAL_REG; + QD2_posedge_int <= SRVAL_REG; + end else if (R_sync == 1'b0) begin + Q_out <= D1_in; + QD2_posedge_int <= D2_in; + end + end + + always @(negedge C_in) begin + if (SR_in == 1'b1 || R_sync == 1'b1) begin + Q_out <= SRVAL_REG; + end else if (R_sync == 1'b0) begin + Q_out <= QD2_posedge_int; + end + end + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire c_en_n; + wire c_en_p; + + assign c_en_n = IS_C_INVERTED_REG; + assign c_en_p = ~IS_C_INVERTED_REG; + +`endif + + specify + (C => Q) = (100:100:100, 100:100:100); + (D1 => Q) = (0:0:0, 0:0:0); + (posedge SR => (Q +: 0)) = (100:100:100, 100:100:100); + (posedge SR => (Q +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + $recrem (negedge SR, negedge C, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, SR_delay, C_delay); + $recrem (negedge SR, posedge C, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, SR_delay, C_delay); + $recrem (posedge SR, negedge C, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, SR_delay, C_delay); + $recrem (posedge SR, posedge C, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, SR_delay, C_delay); + $setuphold (negedge C, negedge D1, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D1_delay); + $setuphold (negedge C, negedge D2, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D2_delay); + $setuphold (negedge C, posedge D1, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D1_delay); + $setuphold (negedge C, posedge D2, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, C_delay, D2_delay); + $setuphold (posedge C, negedge D1, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D1_delay); + $setuphold (posedge C, negedge D2, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D2_delay); + $setuphold (posedge C, posedge D1, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D1_delay); + $setuphold (posedge C, posedge D2, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, C_delay, D2_delay); + $width (negedge C, 0:0:0, 0, notifier); + $width (negedge SR, 0:0:0, 0, notifier); + $width (posedge C, 0:0:0, 0, notifier); + $width (posedge SR, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/ODELAYE2.v b/verilog/src/unisims/ODELAYE2.v new file mode 100644 index 0000000..01f156e --- /dev/null +++ b/verilog/src/unisims/ODELAYE2.v @@ -0,0 +1,587 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / Onput Fixed or Variable Delay Element. +// /___/ /\ Filename : ODELAYE2.v +// \ \ / \ Timestamp : Mon Sep 21 08:48:13 PDT 2009 +// \___\/\___\ +// +// Revision: +// 09/21/09 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ODELAYE2 (CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN, REGRST); + + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "ODATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + parameter integer SIM_DELAY_D = 0; + localparam DELAY_D = (ODELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0; +`endif // ifdef XIL_TIMING + +`ifndef XIL_TIMING + integer DELAY_D=0; +`endif // ifndef XIL_TIMING + + output [4:0] CNTVALUEOUT; + output DATAOUT; + + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input INC; + input LD; + input LDPIPEEN; + input ODATAIN; + input REGRST; + + + tri0 GSR = glbl.GSR; + real CALC_TAPDELAY ; + real INIT_DELAY; + +//------------------- constants ------------------------------------ + + localparam MAX_DELAY_COUNT = 31; + localparam MIN_DELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCYL = 210.0; + localparam MIN_REFCLK_FREQUENCYL = 190.0; + + localparam MAX_REFCLK_FREQUENCYH = 410.0; + localparam MIN_REFCLK_FREQUENCYH = 290.0; + + +//------------------- variable declaration ------------------------- + + integer odelay_count; + integer CNTVALUEIN_INTEGER; + reg [4:0] cntvalueout_pre; + + reg notifier; + + reg data_mux = 0; + reg tap_out = 0; + reg DATAOUT_reg = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31; + + reg c_in; + wire c_in_pre,delay_C; + wire ce_in,delay_CE; + wire cinvctrl_in,delay_CINVCTRL; + wire clkin_in,delay_CLKIN; + wire [4:0] cntvaluein_in,delay_CNTVALUEIN; + wire odatain_in,delay_ODATAIN; + wire gsr_in; + wire inc_in,delay_INC; + wire ld_in,delay_LD; + wire ldpipeen_in,delay_LDPIPEEN; + wire regrst_in,delay_REGRST; + + reg [4:0] qcntvalueout_reg = 5'b0; + reg [4:0] qcntvalueout_mux = 5'b0; + + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- +// CR 587496 +// assign #INIT_DELAY DATAOUT = tap_out; + always @(tap_out) + DATAOUT_reg <= #INIT_DELAY tap_out; + + assign DATAOUT = DATAOUT_reg; + assign CNTVALUEOUT = cntvalueout_pre; + +`ifndef XIL_TIMING +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign delay_C = C; + assign delay_CE = CE; + assign delay_CNTVALUEIN = CNTVALUEIN; + assign delay_INC = INC; + assign delay_LD = LD; + assign delay_LDPIPEEN = LDPIPEEN; + assign delay_REGRST = REGRST; +`endif // ifndef XIL_TIMING + assign delay_CINVCTRL = CINVCTRL; + assign delay_CLKIN = CLKIN; + assign delay_ODATAIN = ODATAIN; + assign gsr_in = GSR; + + assign c_in_pre = IS_C_INVERTED ^ delay_C; + assign ce_in = delay_CE; + assign cntvaluein_in = delay_CNTVALUEIN; + assign inc_in = delay_INC; + assign ld_in = delay_LD; + assign ldpipeen_in = delay_LDPIPEEN; + assign regrst_in = delay_REGRST; + assign cinvctrl_in = delay_CINVCTRL; + assign clkin_in = delay_CLKIN; + assign odatain_in = IS_ODATAIN_INVERTED ^ delay_ODATAIN; + + + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin +// For simprims, the fixed Delay values are taken from the sdf. + // if (ODELAY_TYPE == "FIXED") + // assign odelay_count = 0; + // else + // assign odelay_count = ODELAY_VALUE; + case (ODELAY_TYPE) + "VAR_LOAD", "VAR_LOAD_PIPE": assign odelay_count = 0; + "FIXED", "VARIABLE" : assign odelay_count = ODELAY_VALUE; + endcase + end + else if (gsr_in == 1'b0) begin + deassign odelay_count; + end + end + + +//------------------------------------------------------------ +//--------------------- Initialization -------------------- +//------------------------------------------------------------ + + initial begin + + //-------- CINVCTRL_SEL check + + case (CINVCTRL_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CINVCTRL_SEL on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL); + #1 $finish; + end + endcase + + //-------- DELAY_SRC check + + if (DELAY_SRC != "ODATAIN" && DELAY_SRC != "CLKIN") begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2 instance %m is set to %s. Legal values for this attribute are ODATAIN or CLKIN", DELAY_SRC); + #1 $finish; + end + + + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + #1 $finish; + end + endcase + + + //-------- ODELAY_TYPE check + + if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOAD" && ODELAY_TYPE != "VAR_LOAD_PIPE") begin + + $display("Attribute Syntax Error : The attribute ODELAY_TYPE on ODELAYE2 instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", ODELAY_TYPE); + #1 $finish; + + end + + + //-------- ODELAY_VALUE check + + if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute ODELAY_VALUE on ODELAYE2 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE); + #1 $finish; + + end + + //-------- PIPE_SEL check + + case (PIPE_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute PIPE_SEL on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL); + #1 $finish; + end + endcase + + + + //-------- REFCLK_FREQUENCY check + + //if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin + if ((REFCLK_FREQUENCY >= 190.0 && REFCLK_FREQUENCY <= 210.0) || + (REFCLK_FREQUENCY >= 290.0 && REFCLK_FREQUENCY <= 310.0) || + (REFCLK_FREQUENCY >=390.0 && REFCLK_FREQUENCY <= 410.0)) + /* */; + else begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on ODELAYE2 instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0 or between 390.0 and 410.0", REFCLK_FREQUENCY); + #1 $finish; + end + + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on ODELAYE2 instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + #1 $finish; + end + endcase + + //-------- CALC_TAPDELAY check + + INIT_DELAY = 600; + + end // initial begin + + // CALC_TAPDELAY value + initial begin + if ((REFCLK_FREQUENCY <= 410.0) && (REFCLK_FREQUENCY >= 390.0)) + begin + CALC_TAPDELAY = 39; + end + else if ((REFCLK_FREQUENCY <= 310.0) && (REFCLK_FREQUENCY >= 290.0)) + begin + CALC_TAPDELAY = 52; + end + else + begin + CALC_TAPDELAY = 78; + end + end + +//---------------------------------------------------------------------- +//------------------------ Dynamic clock inversion --------------------- +//---------------------------------------------------------------------- + +// always @(c_in_pre or cinvctrl_in) begin +// case (CINVCTRL_SEL) +// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); +// "FALSE" : c_in = c_in_pre; +// endcase +// end + + generate + case (CINVCTRL_SEL) + "TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); + "FALSE" : always @(c_in_pre) c_in = c_in_pre; + endcase + endgenerate +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- + always @(odelay_count) begin +// Fixed CNTVALUEOUT for when in FIXED mode because of simprim. + if(ODELAY_TYPE != "FIXED") + assign cntvalueout_pre = odelay_count; + else + assign cntvalueout_pre = ODELAY_VALUE; + end + +//---------------------------------------------------------------------- +//-------------------------- CNTVALUEIN LOAD -------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + if (regrst_in == 1'b1) + qcntvalueout_reg = 5'b0; + else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin + qcntvalueout_reg = CNTVALUEIN_INTEGER; + end + end // always @(posedge c_in) + + generate + case (PIPE_SEL) + "TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg; + "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; + endcase + endgenerate + +//---------------------------------------------------------------------- +//-------------------------- ODELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + + if (ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOAD" | ODELAY_TYPE == "VAR_LOAD_PIPE") begin + if (ld_in == 1'b1) begin + case (ODELAY_TYPE) + "VARIABLE" : odelay_count = ODELAY_VALUE; + "VAR_LOAD", "VAR_LOAD_PIPE" : odelay_count = qcntvalueout_mux; + endcase + end + else if (ld_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + case (ODELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (odelay_count < MAX_DELAY_COUNT) + odelay_count = odelay_count + 1; + else if (odelay_count == MAX_DELAY_COUNT) + odelay_count = MIN_DELAY_COUNT; + end + endcase + end + else if (inc_in == 1'b0) begin + case (ODELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (odelay_count > MIN_DELAY_COUNT) + odelay_count = odelay_count - 1; + else if (odelay_count == MIN_DELAY_COUNT) + odelay_count = MAX_DELAY_COUNT; + end + endcase + end + end + end // + end // always @ (posedge c_in) + + always @(cntvaluein_in or gsr_in) begin + case (cntvaluein_in) + 5'b00000 : assign CNTVALUEIN_INTEGER = 0; + 5'b00001 : assign CNTVALUEIN_INTEGER = 1; + 5'b00010 : assign CNTVALUEIN_INTEGER = 2; + 5'b00011 : assign CNTVALUEIN_INTEGER = 3; + 5'b00100 : assign CNTVALUEIN_INTEGER = 4; + 5'b00101 : assign CNTVALUEIN_INTEGER = 5; + 5'b00110 : assign CNTVALUEIN_INTEGER = 6; + 5'b00111 : assign CNTVALUEIN_INTEGER = 7; + 5'b01000 : assign CNTVALUEIN_INTEGER = 8; + 5'b01001 : assign CNTVALUEIN_INTEGER = 9; + 5'b01010 : assign CNTVALUEIN_INTEGER = 10; + 5'b01011 : assign CNTVALUEIN_INTEGER = 11; + 5'b01100 : assign CNTVALUEIN_INTEGER = 12; + 5'b01101 : assign CNTVALUEIN_INTEGER = 13; + 5'b01110 : assign CNTVALUEIN_INTEGER = 14; + 5'b01111 : assign CNTVALUEIN_INTEGER = 15; + 5'b10000 : assign CNTVALUEIN_INTEGER = 16; + 5'b10001 : assign CNTVALUEIN_INTEGER = 17; + 5'b10010 : assign CNTVALUEIN_INTEGER = 18; + 5'b10011 : assign CNTVALUEIN_INTEGER = 19; + 5'b10100 : assign CNTVALUEIN_INTEGER = 20; + 5'b10101 : assign CNTVALUEIN_INTEGER = 21; + 5'b10110 : assign CNTVALUEIN_INTEGER = 22; + 5'b10111 : assign CNTVALUEIN_INTEGER = 23; + 5'b11000 : assign CNTVALUEIN_INTEGER = 24; + 5'b11001 : assign CNTVALUEIN_INTEGER = 25; + 5'b11010 : assign CNTVALUEIN_INTEGER = 26; + 5'b11011 : assign CNTVALUEIN_INTEGER = 27; + 5'b11100 : assign CNTVALUEIN_INTEGER = 28; + 5'b11101 : assign CNTVALUEIN_INTEGER = 29; + 5'b11110 : assign CNTVALUEIN_INTEGER = 30; + 5'b11111 : assign CNTVALUEIN_INTEGER = 31; + endcase + end + + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(clkin_in or odatain_in) begin + + case (DELAY_SRC) + + "ODATAIN" : begin + data_mux <= odatain_in; + end + "CLKIN" : begin + data_mux <= clkin_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2 instance %m is set to %s. Legal values for this attribute are CLKIN or ODATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @(datain_in or idatain_in) + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* + assign #(DELAY_D) delay_chain_0 = data_mux; + assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(odelay_count) begin + case (odelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + end // always @ (odelay_count) + +`ifdef XIL_TIMING + wire c_en_n; + wire c_en_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + + wire c_d_en; + wire o_d_en; + + assign c_d_en = (odelay_count == 0) && (DELAY_SRC == "CLKIN"); + assign o_d_en = (odelay_count == 0) && (DELAY_SRC == "ODATAIN"); + +//*** Timing Checks Start here + + always @(notifier) begin + tap_out <= 1'bx; + end +`endif // ifdef XIL_TIMING + +`ifdef XIL_TIMING + specify + + ( C *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( C => DATAOUT) = (0:0:0, 0:0:0); + ( CINVCTRL *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( CINVCTRL => DATAOUT) = (0:0:0, 0:0:0); + if (c_d_en) ( CLKIN => DATAOUT) = (0:0:0, 0:0:0); + if (o_d_en) ( ODATAIN => DATAOUT) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CE); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CE); + $setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_INC); + $setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_INC); + $setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LD); + $setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LD); + $setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CNTVALUEIN); + $setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_CNTVALUEIN); + $setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LDPIPEEN); + $setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_LDPIPEEN); + $setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_REGRST); + $setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_C, delay_REGRST); + + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CE); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CE); + $setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_INC); + $setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_INC); + $setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LD); + $setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LD); + $setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CNTVALUEIN); + $setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_CNTVALUEIN); + $setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LDPIPEEN); + $setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_LDPIPEEN); + $setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_REGRST); + $setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_C, delay_REGRST); + + + specparam PATHPULSE$ = 0; + + endspecify +`endif // ifdef XIL_TIMING + +endmodule // ODELAYE2 + +`endcelldefine diff --git a/verilog/src/unisims/ODELAYE2_FINEDELAY.v b/verilog/src/unisims/ODELAYE2_FINEDELAY.v new file mode 100644 index 0000000..b764c38 --- /dev/null +++ b/verilog/src/unisims/ODELAYE2_FINEDELAY.v @@ -0,0 +1,641 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2011 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.0 +// \ \ Description : Xilinx Functional and Timing Simulation Library Component +// / / Onput Fixed or Variable Delay Element with Fine Adjustment. +// /___/ /\ Filename : ODELAYE2_FINEDELAY.v +// \ \ / \ Timestamp : Tue Feb 15 15:52:17 PST 2011 +// \___\/\___\ +// +// Revision: +// 02/15/11 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ODELAYE2_FINEDELAY ( + CNTVALUEOUT, + DATAOUT, + + C, + CE, + CINVCTRL, + CLKIN, + CNTVALUEIN, + INC, + LD, + LDPIPEEN, + ODATAIN, + OFDLY, + REGRST +); + + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "ODATAIN"; + parameter FINEDELAY = "BYPASS"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + parameter integer SIM_DELAY_D = 0; + localparam DELAY_D = (ODELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0; +`endif // ifdef XIL_TIMING + +`ifndef XIL_TIMING + integer DELAY_D=0; +`endif // ifndef XIL_TIMING + + output [4:0] CNTVALUEOUT; + output DATAOUT; + + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input INC; + input LD; + input LDPIPEEN; + input ODATAIN; + input [2:0] OFDLY; + input REGRST; + + + tri0 GSR = glbl.GSR; + + real CALC_TAPDELAY_RD ; // regular tap delay + real CALC_TAPDELAY_FD ; // fine tap delay + real INIT_DELAY_RD; + real INIT_DELAY_FD; + +//------------------- constants ------------------------------------ + + localparam MAX_DELAY_COUNT = 31; + localparam MIN_DELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCYL = 210.0; + localparam MIN_REFCLK_FREQUENCYL = 190.0; + + localparam MAX_REFCLK_FREQUENCYH = 410.0; + localparam MIN_REFCLK_FREQUENCYH = 290.0; + + +//------------------- variable declaration ------------------------- + + integer odelay_count; + integer CNTVALUEIN_INTEGER; + reg [4:0] cntvalueout_pre; + + reg notifier; + + reg data_mux = 0; + reg tap_out_rd = 0; + reg tap_out_fd = 0; + reg tap_out_final = 0; + reg DATAOUT_reg = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31; + + wire fine_delay_0, fine_delay_1, fine_delay_2, fine_delay_3, fine_delay_4, fine_delay_5; + + reg c_in; + wire c_in_pre,delay_c; + wire ce_in,delay_ce; + wire cinvctrl_in,delay_cinvctrl; + wire clkin_in,delay_clkin; + wire [4:0] cntvaluein_in,delay_cntvaluein; + wire odatain_in,delay_odatain; + wire ofdly_in,delay_ofdly; + wire gsr_in; + wire inc_in,delay_inc; + wire ld_in,delay_ld; + wire ldpipeen_in,delay_ldpipeen; + wire regrst_in,delay_regrst; + + reg [4:0] qcntvalueout_reg = 5'b0; + reg [4:0] qcntvalueout_mux = 5'b0; + + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- + generate + case (FINEDELAY) + "BYPASS" : always @(tap_out_rd) tap_out_final = tap_out_rd; + "ADD_DLY" : always @(tap_out_fd) tap_out_final = tap_out_fd; + endcase + endgenerate + +// CR 587496 +// assign #INIT_DELAY DATAOUT = tap_out_final; + always @(tap_out_final) + DATAOUT_reg <= #INIT_DELAY_RD tap_out_final; + + assign DATAOUT = DATAOUT_reg; + assign CNTVALUEOUT = cntvalueout_pre; + +`ifndef XIL_TIMING +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign delay_c = C; + assign delay_ce = CE; + assign delay_cntvaluein = CNTVALUEIN; + assign delay_inc = INC; + assign delay_ld = LD; + assign delay_ldpipeen = LDPIPEEN; + assign delay_regrst = REGRST; +`endif // ifndef XIL_TIMING + assign delay_cinvctrl = CINVCTRL; + assign delay_clkin = CLKIN; + assign delay_odatain = ODATAIN; + assign delay_ofdly = OFDLY; + assign gsr_in = GSR; + + assign c_in_pre = IS_C_INVERTED ^ delay_c; + assign ce_in = delay_ce; + assign cntvaluein_in = delay_cntvaluein; + assign inc_in = delay_inc; + assign ld_in = delay_ld; + assign ldpipeen_in = delay_ldpipeen; + assign regrst_in = delay_regrst; + + assign cinvctrl_in = delay_cinvctrl; + assign clkin_in = delay_clkin; + assign odatain_in = IS_ODATAIN_INVERTED ^ delay_odatain; + assign ofdly_in = delay_ofdly; + + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin +// For simprims, the fixed Delay values are taken from the sdf. + if (ODELAY_TYPE == "FIXED") + assign odelay_count = 0; + else + assign odelay_count = ODELAY_VALUE; + end + else if (gsr_in == 1'b0) begin + deassign odelay_count; + end + end + + +//------------------------------------------------------------ +//--------------------- Initialization -------------------- +//------------------------------------------------------------ + + initial begin + + //-------- CINVCTRL_SEL check + + case (CINVCTRL_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CINVCTRL_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL); + #1 $finish; + end + endcase + + //-------- DELAY_SRC check + + if (DELAY_SRC != "ODATAIN" && DELAY_SRC != "CLKIN") begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are ODATAIN or CLKIN", DELAY_SRC); + #1 $finish; + end + + //-------- FINEDELAY check + + if (FINEDELAY != "BYPASS" && FINEDELAY != "ADD_DLY") begin + $display("Attribute Syntax Error : The attribute FINEDELAY on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are BYPASS or ADD_DLY", FINEDELAY); + #1 $finish; + end + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + #1 $finish; + end + endcase + + + //-------- ODELAY_TYPE check + + if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOAD" && ODELAY_TYPE != "VAR_LOAD_PIPE") begin + + $display("Attribute Syntax Error : The attribute ODELAY_TYPE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", ODELAY_TYPE); + #1 $finish; + + end + + + //-------- ODELAY_VALUE check + + if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute ODELAY_VALUE on ODELAYE2_FINEDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE); + #1 $finish; + + end + + //-------- PIPE_SEL check + + case (PIPE_SEL) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute PIPE_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL); + #1 $finish; + end + endcase + + + + //-------- REFCLK_FREQUENCY check + + if ((REFCLK_FREQUENCY >= 190.0 && REFCLK_FREQUENCY <= 210.0) || + (REFCLK_FREQUENCY >= 290.0 && REFCLK_FREQUENCY <= 310.0) || + (REFCLK_FREQUENCY >=390.0 && REFCLK_FREQUENCY <= 410.0)) + /* */; + else begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on ODELAYE2_FINEDELAY instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0 or between 390.0 and 410.0", REFCLK_FREQUENCY); + #1 $finish; + end + + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + #1 $finish; + end + endcase + + //-------- CALC_TAPDELAY_RD check + + INIT_DELAY_RD = 600; //regular delay + INIT_DELAY_FD = 40; //fine delay + + end // initial begin + + // CALC_TAPDELAY_RD value + initial begin + if ((REFCLK_FREQUENCY <= 410.0) && (REFCLK_FREQUENCY >= 390.0)) + begin + CALC_TAPDELAY_RD = 39; + end + else if ((REFCLK_FREQUENCY <= 310.0) && (REFCLK_FREQUENCY >= 290.0)) + begin + CALC_TAPDELAY_RD = 52; + end + else + begin + CALC_TAPDELAY_RD = 78; + end + + CALC_TAPDELAY_FD = 10; //fine delay + end + +//---------------------------------------------------------------------- +//------------------------ Dynamic clock inversion --------------------- +//---------------------------------------------------------------------- + generate + case (CINVCTRL_SEL) + "TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); + "FALSE" : always @(c_in_pre) c_in = c_in_pre; + endcase + endgenerate +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- + always @(odelay_count) begin +// Fixed CNTVALUEOUT for when in FIXED mode because of simprim. + if(ODELAY_TYPE != "FIXED") + assign cntvalueout_pre = odelay_count; + else + assign cntvalueout_pre = ODELAY_VALUE; + end + +//---------------------------------------------------------------------- +//-------------------------- CNTVALUEIN LOAD -------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + if (regrst_in == 1'b1) + qcntvalueout_reg = 5'b0; + else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin + qcntvalueout_reg = CNTVALUEIN_INTEGER; + end + end // always @(posedge c_in) + + generate + case (PIPE_SEL) + "TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg; + "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; + endcase + endgenerate + +//---------------------------------------------------------------------- +//-------------------------- ODELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(posedge c_in) begin + + if (ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOAD" | ODELAY_TYPE == "VAR_LOAD_PIPE") begin + if (ld_in == 1'b1) begin + case (ODELAY_TYPE) + "VARIABLE" : odelay_count = ODELAY_VALUE; + "VAR_LOAD", "VAR_LOAD_PIPE" : odelay_count = qcntvalueout_mux; + endcase + end + else if (ld_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + case (ODELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (odelay_count < MAX_DELAY_COUNT) + odelay_count = odelay_count + 1; + else if (odelay_count == MAX_DELAY_COUNT) + odelay_count = MIN_DELAY_COUNT; + end + endcase + end + else if (inc_in == 1'b0) begin + case (ODELAY_TYPE) + "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin + if (odelay_count > MIN_DELAY_COUNT) + odelay_count = odelay_count - 1; + else if (odelay_count == MIN_DELAY_COUNT) + odelay_count = MAX_DELAY_COUNT; + end + endcase + end + end + end // + end // always @ (posedge c_in) + + always @(cntvaluein_in or gsr_in) begin + case (cntvaluein_in) + 5'b00000 : assign CNTVALUEIN_INTEGER = 0; + 5'b00001 : assign CNTVALUEIN_INTEGER = 1; + 5'b00010 : assign CNTVALUEIN_INTEGER = 2; + 5'b00011 : assign CNTVALUEIN_INTEGER = 3; + 5'b00100 : assign CNTVALUEIN_INTEGER = 4; + 5'b00101 : assign CNTVALUEIN_INTEGER = 5; + 5'b00110 : assign CNTVALUEIN_INTEGER = 6; + 5'b00111 : assign CNTVALUEIN_INTEGER = 7; + 5'b01000 : assign CNTVALUEIN_INTEGER = 8; + 5'b01001 : assign CNTVALUEIN_INTEGER = 9; + 5'b01010 : assign CNTVALUEIN_INTEGER = 10; + 5'b01011 : assign CNTVALUEIN_INTEGER = 11; + 5'b01100 : assign CNTVALUEIN_INTEGER = 12; + 5'b01101 : assign CNTVALUEIN_INTEGER = 13; + 5'b01110 : assign CNTVALUEIN_INTEGER = 14; + 5'b01111 : assign CNTVALUEIN_INTEGER = 15; + 5'b10000 : assign CNTVALUEIN_INTEGER = 16; + 5'b10001 : assign CNTVALUEIN_INTEGER = 17; + 5'b10010 : assign CNTVALUEIN_INTEGER = 18; + 5'b10011 : assign CNTVALUEIN_INTEGER = 19; + 5'b10100 : assign CNTVALUEIN_INTEGER = 20; + 5'b10101 : assign CNTVALUEIN_INTEGER = 21; + 5'b10110 : assign CNTVALUEIN_INTEGER = 22; + 5'b10111 : assign CNTVALUEIN_INTEGER = 23; + 5'b11000 : assign CNTVALUEIN_INTEGER = 24; + 5'b11001 : assign CNTVALUEIN_INTEGER = 25; + 5'b11010 : assign CNTVALUEIN_INTEGER = 26; + 5'b11011 : assign CNTVALUEIN_INTEGER = 27; + 5'b11100 : assign CNTVALUEIN_INTEGER = 28; + 5'b11101 : assign CNTVALUEIN_INTEGER = 29; + 5'b11110 : assign CNTVALUEIN_INTEGER = 30; + 5'b11111 : assign CNTVALUEIN_INTEGER = 31; + endcase + end + + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(clkin_in or odatain_in) begin + + case (DELAY_SRC) + + "ODATAIN" : begin + data_mux <= odatain_in; + end + "CLKIN" : begin + data_mux <= clkin_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are CLKIN or ODATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @(datain_in or idatain_in) + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* + assign #(DELAY_D) delay_chain_0 = data_mux; + assign #CALC_TAPDELAY_RD delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY_RD delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY_RD delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY_RD delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY_RD delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY_RD delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY_RD delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY_RD delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY_RD delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY_RD delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY_RD delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY_RD delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY_RD delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY_RD delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY_RD delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY_RD delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY_RD delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY_RD delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY_RD delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY_RD delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY_RD delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY_RD delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY_RD delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY_RD delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY_RD delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY_RD delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY_RD delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY_RD delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY_RD delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY_RD delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY_RD delay_chain_31 = delay_chain_30; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(odelay_count) begin + case (odelay_count) + 0: assign tap_out_rd = delay_chain_0; + 1: assign tap_out_rd = delay_chain_1; + 2: assign tap_out_rd = delay_chain_2; + 3: assign tap_out_rd = delay_chain_3; + 4: assign tap_out_rd = delay_chain_4; + 5: assign tap_out_rd = delay_chain_5; + 6: assign tap_out_rd = delay_chain_6; + 7: assign tap_out_rd = delay_chain_7; + 8: assign tap_out_rd = delay_chain_8; + 9: assign tap_out_rd = delay_chain_9; + 10: assign tap_out_rd = delay_chain_10; + 11: assign tap_out_rd = delay_chain_11; + 12: assign tap_out_rd = delay_chain_12; + 13: assign tap_out_rd = delay_chain_13; + 14: assign tap_out_rd = delay_chain_14; + 15: assign tap_out_rd = delay_chain_15; + 16: assign tap_out_rd = delay_chain_16; + 17: assign tap_out_rd = delay_chain_17; + 18: assign tap_out_rd = delay_chain_18; + 19: assign tap_out_rd = delay_chain_19; + 20: assign tap_out_rd = delay_chain_20; + 21: assign tap_out_rd = delay_chain_21; + 22: assign tap_out_rd = delay_chain_22; + 23: assign tap_out_rd = delay_chain_23; + 24: assign tap_out_rd = delay_chain_24; + 25: assign tap_out_rd = delay_chain_25; + 26: assign tap_out_rd = delay_chain_26; + 27: assign tap_out_rd = delay_chain_27; + 28: assign tap_out_rd = delay_chain_28; + 29: assign tap_out_rd = delay_chain_29; + 30: assign tap_out_rd = delay_chain_30; + 31: assign tap_out_rd = delay_chain_31; + default: + assign tap_out_rd = delay_chain_0; + endcase + end // always @ (odelay_count) + +//********************************************************* +//*** FINE DELAY signal +//********************************************************* + assign #(INIT_DELAY_FD) fine_delay_0 = tap_out_rd; + assign #CALC_TAPDELAY_FD fine_delay_1 = fine_delay_0; + assign #CALC_TAPDELAY_FD fine_delay_2 = fine_delay_1; + assign #CALC_TAPDELAY_FD fine_delay_3 = fine_delay_2; + assign #CALC_TAPDELAY_FD fine_delay_4 = fine_delay_3; + assign #CALC_TAPDELAY_FD fine_delay_5 = fine_delay_4; + + always @(ofdly_in) begin + case (ofdly_in) + 3'b000: assign tap_out_fd = fine_delay_0; + 3'b001: assign tap_out_fd = fine_delay_1; + 3'b010: assign tap_out_fd = fine_delay_2; + 3'b011: assign tap_out_fd = fine_delay_3; + 3'b100: assign tap_out_fd = fine_delay_4; + default: + assign tap_out_fd = 1'bx; + endcase + end // always @ (ofdly_in) + + +`ifdef XIL_TIMING + wire c_en_n; + wire c_en_p; + assign c_en_n = IS_C_INVERTED; + assign c_en_p = ~IS_C_INVERTED; + + wire c_d_en; + wire o_d_en; + + assign c_d_en = (odelay_count == 0) && (ofdly_in == 0) && (DELAY_SRC == "CLKIN"); + assign o_d_en = (odelay_count == 0) && (ofdly_in == 0) && (DELAY_SRC == "ODATAIN"); + + +//*** Timing Checks Start here + + always @(notifier) begin + tap_out_rd <= 1'bx; + end +`endif // ifdef XIL_TIMING + +`ifdef XIL_TIMING + specify + + ( C *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( C => DATAOUT) = (0:0:0, 0:0:0); + ( CINVCTRL *> CNTVALUEOUT) = (0:0:0, 0:0:0); + ( CINVCTRL => DATAOUT) = (0:0:0, 0:0:0); + if (c_d_en) ( CLKIN => DATAOUT) = (0:0:0, 0:0:0); + if (o_d_en) ( ODATAIN => DATAOUT) = (0:0:0, 0:0:0); + + $period (negedge C, 0:0:0, notifier); + $period (posedge C, 0:0:0, notifier); + + $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ce); + $setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc); + $setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_inc); + $setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld); + $setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ld); + $setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein); + $setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_cntvaluein); + $setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen); + $setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_ldpipeen); + $setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst); + $setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_p, c_en_p, delay_c, delay_regrst); + + $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ce); + $setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc); + $setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_inc); + $setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld); + $setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ld); + $setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein); + $setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_cntvaluein); + $setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen); + $setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_ldpipeen); + $setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst); + $setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, c_en_n, c_en_n, delay_c, delay_regrst); + + + specparam PATHPULSE$ = 0; + + endspecify +`endif // ifdef XIL_TIMING + +endmodule // ODELAYE2_FINEDELAY + +`endcelldefine diff --git a/verilog/src/unisims/ODELAYE3.v b/verilog/src/unisims/ODELAYE3.v new file mode 100644 index 0000000..95487b1 --- /dev/null +++ b/verilog/src/unisims/ODELAYE3.v @@ -0,0 +1,710 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Output Fixed or Variable Delay Element +// /___/ /\ Filename : ODELAYE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module ODELAYE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE = "NONE", + parameter DELAY_FORMAT = "TIME", + parameter DELAY_TYPE = "FIXED", + parameter integer DELAY_VALUE = 0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REFCLK_FREQUENCY = 300.0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter UPDATE_MODE = "ASYNC" +)( + output CASC_OUT, + output [8:0] CNTVALUEOUT, + output DATAOUT, + + input CASC_IN, + input CASC_RETURN, + input CE, + input CLK, + input [8:0] CNTVALUEIN, + input EN_VTC, + input INC, + input LOAD, + input ODATAIN, + input RST +); + +// define constants + localparam MODULE_NAME = "ODELAYE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + localparam CASCADE_MASTER = 1; + localparam CASCADE_NONE = 0; + localparam CASCADE_SLAVE_END = 2; + localparam CASCADE_SLAVE_MIDDLE = 3; + localparam DELAY_FORMAT_COUNT = 1; + localparam DELAY_FORMAT_TIME = 0; + localparam DELAY_TYPE_FIXED = 0; + localparam DELAY_TYPE_VARIABLE = 1; + localparam DELAY_TYPE_VAR_LOAD = 2; + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 2; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES2 = 3; + localparam UPDATE_MODE_ASYNC = 0; + localparam UPDATE_MODE_MANUAL = 1; + localparam UPDATE_MODE_SYNC = 2; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "ODELAYE3_dr.v" +`else + localparam [96:1] CASCADE_REG = CASCADE; + localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT; + localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE; + localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE; +`endif + + wire [1:0] CASCADE_BIN; + wire DELAY_FORMAT_BIN; + wire [1:0] DELAY_TYPE_BIN; + wire [10:0] DELAY_VALUE_BIN; + wire [63:0] REFCLK_FREQUENCY_BIN; + wire [1:0] SIM_DEVICE_BIN; + wire [63:0] SIM_VERSION_BIN; + wire [1:0] UPDATE_MODE_BIN; + + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + + wire CASC_IN_in; + wire CASC_RETURN_in; + wire CE_in; + wire CLK_in; + wire EN_VTC_in; + wire INC_in; + wire LOAD_in; + wire ODATAIN_in; + wire RST_in; + wire [8:0] CNTVALUEIN_in; + + wire CASC_IN_delay; + wire CASC_RETURN_delay; + wire CE_delay; + wire CLK_delay; + wire EN_VTC_delay; + wire INC_delay; + wire LOAD_delay; + wire ODATAIN_delay; + wire RST_delay; + wire [8:0] CNTVALUEIN_delay; + + reg CASC_OUT_out; + reg DATAOUT_out; + reg [8:0] CNTVALUEOUT_out; + + wire CASC_OUT_delay; + wire DATAOUT_delay; + wire [8:0] CNTVALUEOUT_delay; + + assign #(out_delay) CASC_OUT = CASC_OUT_delay; + assign #(out_delay) CNTVALUEOUT = (EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : CNTVALUEOUT_delay; + assign #(out_delay) DATAOUT = DATAOUT_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLK_delay = CLK; + + assign #(in_delay) CE_delay = CE; + assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN; + assign #(in_delay) INC_delay = INC; + assign #(in_delay) LOAD_delay = LOAD; +`endif // `ifndef XIL_TIMING +// inputs with no timing checks + + assign #(in_delay) RST_delay = RST; + assign #(in_delay) CASC_IN_delay = CASC_IN; + assign #(in_delay) CASC_RETURN_delay = CASC_RETURN; + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) ODATAIN_delay = ODATAIN; + + assign CASC_OUT_delay = CASC_OUT_out; + assign CNTVALUEOUT_delay = CNTVALUEOUT_out; + assign DATAOUT_delay = DATAOUT_out; + + assign CASC_IN_in = CASC_IN_delay; + assign CASC_RETURN_in = CASC_RETURN_delay; + assign CE_in = CE_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG; + assign CNTVALUEIN_in[0] = (CNTVALUEIN[0] === 1'bz) || CNTVALUEIN_delay[0]; // rv 1 + assign CNTVALUEIN_in[1] = (CNTVALUEIN[1] === 1'bz) || CNTVALUEIN_delay[1]; // rv 1 + assign CNTVALUEIN_in[2] = (CNTVALUEIN[2] === 1'bz) || CNTVALUEIN_delay[2]; // rv 1 + assign CNTVALUEIN_in[3] = (CNTVALUEIN[3] === 1'bz) || CNTVALUEIN_delay[3]; // rv 1 + assign CNTVALUEIN_in[4] = (CNTVALUEIN[4] === 1'bz) || CNTVALUEIN_delay[4]; // rv 1 + assign CNTVALUEIN_in[5] = (CNTVALUEIN[5] === 1'bz) || CNTVALUEIN_delay[5]; // rv 1 + assign CNTVALUEIN_in[6] = (CNTVALUEIN[6] === 1'bz) || CNTVALUEIN_delay[6]; // rv 1 + assign CNTVALUEIN_in[7] = (CNTVALUEIN[7] === 1'bz) || CNTVALUEIN_delay[7]; // rv 1 + assign CNTVALUEIN_in[8] = (CNTVALUEIN[8] === 1'bz) || CNTVALUEIN_delay[8]; // rv 1 + assign EN_VTC_in = EN_VTC_delay; + assign INC_in = INC_delay; + assign LOAD_in = LOAD_delay; + assign ODATAIN_in = ODATAIN_delay; + assign RST_in = RST_delay ^ IS_RST_INVERTED_REG; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + + assign CASCADE_BIN = + (CASCADE_REG == "NONE") ? CASCADE_NONE : + (CASCADE_REG == "MASTER") ? CASCADE_MASTER : + (CASCADE_REG == "SLAVE_END") ? CASCADE_SLAVE_END : + (CASCADE_REG == "SLAVE_MIDDLE") ? CASCADE_SLAVE_MIDDLE : + CASCADE_NONE; + + assign DELAY_FORMAT_BIN = + (DELAY_FORMAT_REG == "TIME") ? DELAY_FORMAT_TIME : + (DELAY_FORMAT_REG == "COUNT") ? DELAY_FORMAT_COUNT : + DELAY_FORMAT_TIME; + + assign DELAY_TYPE_BIN = + (DELAY_TYPE_REG == "FIXED") ? DELAY_TYPE_FIXED : + (DELAY_TYPE_REG == "VARIABLE") ? DELAY_TYPE_VARIABLE : + (DELAY_TYPE_REG == "VAR_LOAD") ? DELAY_TYPE_VAR_LOAD : + DELAY_TYPE_FIXED; + + assign DELAY_VALUE_BIN = DELAY_VALUE_REG[10:0]; + + assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + assign UPDATE_MODE_BIN = + (UPDATE_MODE_REG == "ASYNC") ? UPDATE_MODE_ASYNC : + (UPDATE_MODE_REG == "MANUAL") ? UPDATE_MODE_MANUAL : + (UPDATE_MODE_REG == "SYNC") ? UPDATE_MODE_SYNC : + UPDATE_MODE_ASYNC; + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CASCADE_REG != "NONE") && + (CASCADE_REG != "MASTER") && + (CASCADE_REG != "SLAVE_END") && + (CASCADE_REG != "SLAVE_MIDDLE"))) begin + $display("Error: [Unisim %s-101] CASCADE attribute is set to %s. Legal values for this attribute are NONE, MASTER, SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_FORMAT_REG != "TIME") && + (DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-102] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_TYPE_REG != "FIXED") && + (DELAY_TYPE_REG != "VAR_LOAD") && + (DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-104] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-108] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-108] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-109] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-110] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_REG != "ASYNC") && + (UPDATE_MODE_REG != "MANUAL") && + (UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-111] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + localparam MAX_DELAY_COUNT = 511; + localparam MIN_DELAY_COUNT = 0; + + integer PER_BIT_FINE_DELAY; + integer PER_BIT_MEDIUM_DELAY; + integer INTRINSIC_FINE_DELAY; + integer INTRINSIC_MEDIUM_DELAY; + integer ODATAIN_INTRINSIC_DELAY; + integer CASC_IN_INTRINSIC_DELAY; + integer CASC_RET_INTRINSIC_DELAY; + integer DATA_OUT_INTRINSIC_DELAY; + integer CASC_OUT_INTRINSIC_DELAY; + + reg [17:0] gen_mc_fixed_dly_ratio; + reg tap_out; + reg clk_smux; + reg data_mux; + reg data_mux_sync; + reg data_mux_sync1; + reg data_mux_sync2; + reg data_mux_sync3; + reg data_mux_sync4; + reg cdataout_pre; + reg RST_sync1; + reg RST_sync2; + reg RST_sync3; + reg [8:0] idelay_count_async; + reg [8:0] idelay_count_sync; + reg [8:0] cntvalue_updated; + reg [8:0] cntvalue_updated_sync; + reg [8:0] cntvalue_updated_async; + reg [8:0] idelay_count_pre; + reg [8:0] CNTVALUEIN_INTEGER; + time delay_value; + + initial begin + case (SIM_DEVICE) + "ULTRASCALE" : begin + PER_BIT_FINE_DELAY = 5; + PER_BIT_MEDIUM_DELAY = 40; + INTRINSIC_FINE_DELAY = 75; + INTRINSIC_MEDIUM_DELAY = 40; + ODATAIN_INTRINSIC_DELAY = 60; + CASC_IN_INTRINSIC_DELAY = 60; + CASC_RET_INTRINSIC_DELAY = 60; + DATA_OUT_INTRINSIC_DELAY = 25; + CASC_OUT_INTRINSIC_DELAY = 80; + end + "ULTRASCALE_PLUS","ULTRASCALE_PLUS_ES1","ULTRASCALE_PLUS_ES2" : begin + PER_BIT_FINE_DELAY = 4; + PER_BIT_MEDIUM_DELAY = 32; + INTRINSIC_FINE_DELAY = 60; + INTRINSIC_MEDIUM_DELAY = 32; + ODATAIN_INTRINSIC_DELAY = 32; + CASC_IN_INTRINSIC_DELAY = 32; + CASC_RET_INTRINSIC_DELAY = 32; + DATA_OUT_INTRINSIC_DELAY = 20; + CASC_OUT_INTRINSIC_DELAY = 45; + end + default : begin + PER_BIT_FINE_DELAY = 5; + PER_BIT_MEDIUM_DELAY = 40; + INTRINSIC_FINE_DELAY = 75; + INTRINSIC_MEDIUM_DELAY = 40; + ODATAIN_INTRINSIC_DELAY = 60; + CASC_IN_INTRINSIC_DELAY = 60; + CASC_RET_INTRINSIC_DELAY = 60; + DATA_OUT_INTRINSIC_DELAY = 25; + CASC_OUT_INTRINSIC_DELAY = 80; + end + endcase + CNTVALUEOUT_out = 9'b0; + DATAOUT_out = 1'b0; + CASC_OUT_out = 1'b0; + cdataout_pre = 1'b0; + end + + always @(RST_in) begin + if (RST_in === 1'b1 && DELAY_FORMAT_REG == "TIME") + $display("Warning: [Unisim %s-1] Ultrascale IDELAYCTRL and I/ODELAYE3, RST simulation behaviour may not match hardware behaviour when DELAY_FORMAT = TIME, if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide Instance: %m", MODULE_NAME); + end + + always @ (trig_attr) begin + #1; + if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME) begin + if ((DELAY_VALUE_REG == 0) || (REFCLK_FREQUENCY_REG == 0)) begin + idelay_count_pre = 0; + cntvalue_updated = idelay_count_pre; + end else begin + idelay_count_pre = DELAY_VALUE_REG/5; + cntvalue_updated = idelay_count_pre; + end + end else if (DELAY_FORMAT_BIN == DELAY_FORMAT_COUNT) begin + idelay_count_pre = DELAY_VALUE_REG; + cntvalue_updated = idelay_count_pre; + end + end + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- + always @(tap_out) begin + DATAOUT_out <= #(DATA_OUT_INTRINSIC_DELAY) tap_out; + end + + always @(cdataout_pre) begin + CASC_OUT_out <= #(CASC_OUT_INTRINSIC_DELAY) cdataout_pre; + end + +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + +//*** GLOBAL hidden GSR pin + always @(glblGSR or RST_in) begin + if (glblGSR == 1'b1 || RST_in == 1'b1) begin +// assign idelay_count_sync = idelay_count_pre; + assign idelay_count_async = idelay_count_pre; + assign cntvalue_updated_sync = idelay_count_pre; + assign cntvalue_updated_async = idelay_count_pre; + end else if (glblGSR == 1'b0 || RST_in == 1'b0) begin +// deassign idelay_count_sync; + deassign idelay_count_async; + deassign cntvalue_updated_sync; + deassign cntvalue_updated_async; + end + end + +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- +// always @(idelay_count_sync or idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin + always @(idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin + case (UPDATE_MODE_REG) + "SYNC" : begin + CNTVALUEOUT_out = idelay_count_async; + cntvalue_updated = cntvalue_updated_sync; + end + "ASYNC" , "MANUAL" : begin + CNTVALUEOUT_out = idelay_count_async; + cntvalue_updated = cntvalue_updated_async; + end + default: $display("Error: [Unisim %s-1] UPDATE_MODE_REG=%s is not valid value. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + endcase + end + +//---------------------------------------------------------------------- +//-------------------------- DELAY_COUNT ---------------------------- +//---------------------------------------------------------------------- + always @(CLK_in or RST_in or RST_sync3 or RST_sync2 or RST_sync1) begin + if (RST_in == 1'b1 || RST_sync3 == 1'b1 || RST_sync2 == 1'b1 || RST_sync1 == 1'b1) + clk_smux = 1'b0; + else if (RST_sync3 == 1'b0) + clk_smux = CLK_in; + end + + always @(posedge CLK_in) begin + RST_sync1 <= RST_in; + RST_sync2 <= RST_sync1; + RST_sync3 <= RST_sync2; + end + + always @(posedge clk_smux) begin + if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin + case(DELAY_TYPE_REG) + "FIXED": ; //Do nothing. + "VAR_LOAD": + if (EN_VTC_in == 1'b0) begin + casex({LOAD_in, CE_in, INC_in}) + 3'b000: ; //Do nothing. + 3'b001: ; //Do nothing. + 3'b010: + begin //{ + if (idelay_count_async > MIN_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async-1; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= idelay_count_async-1; + end + else if (idelay_count_async == MIN_DELAY_COUNT) begin + idelay_count_async <= MAX_DELAY_COUNT; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= MAX_DELAY_COUNT; + end + end //} + 3'b011: + begin //{ + if (idelay_count_async < MAX_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async + 1; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= idelay_count_async + 1; + end + else if (idelay_count_async == MAX_DELAY_COUNT) begin + idelay_count_async <= MIN_DELAY_COUNT; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= MIN_DELAY_COUNT; + end + end //} + 3'b100, 3'b101: + begin //{ + idelay_count_async <= CNTVALUEIN_INTEGER; + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + cntvalue_updated_async <= CNTVALUEIN_INTEGER; + end //} + 3'b110: + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + $display("Error: [Unisim %s-2] Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s. Instance: %m", MODULE_NAME, UPDATE_MODE_REG, DELAY_TYPE_REG); + else cntvalue_updated_async <= idelay_count_async; + 3'b111: + if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) + $display("Error: [Unisim %s-3] Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s. Instance: %m", MODULE_NAME, UPDATE_MODE_REG, DELAY_TYPE_REG); + else idelay_count_async <= idelay_count_async + CNTVALUEIN_INTEGER; + default: $display("Error: [Unisim %s-4] Invalid scenario. LOAD = %b, CE = %b INC = %b. Instance: %m", MODULE_NAME, LOAD_in, CE_in, INC_in); + endcase + end + "VARIABLE": + if (EN_VTC_in == 1'b0) begin + casex({LOAD_in, CE_in, INC_in}) + 3'b000: ; //Do nothing. + 3'b001: ; //Do nothing. + 3'b010: + begin //{ + if (idelay_count_async > MIN_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async-1; + cntvalue_updated_async <= idelay_count_async-1; + end + else if (idelay_count_async == MIN_DELAY_COUNT) begin + idelay_count_async <= MAX_DELAY_COUNT; + cntvalue_updated_async <= MAX_DELAY_COUNT; + end + end //} + 3'b011: + begin //{ + if (idelay_count_async < MAX_DELAY_COUNT) begin + idelay_count_async <= idelay_count_async + 1; + cntvalue_updated_async <= idelay_count_async + 1; + end + else if (idelay_count_async == MAX_DELAY_COUNT) begin + idelay_count_async <= MIN_DELAY_COUNT; + cntvalue_updated_async <= MIN_DELAY_COUNT; + end + end //} + default: $display("Error: [Unisim %s-5] Invalid scenario. LOAD = %b, CE = %b, INC = %b, DELAY_TYPE=%s. Instance: %m", MODULE_NAME, LOAD_in, CE_in, INC_in, DELAY_TYPE_REG); + endcase + end + default: $display("Error: [Unisim %s-6] DELAY_TYPE=%s is not a valid value. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + endcase + end + end // always @ (posedge CLK_in) + + always @(data_mux) begin + data_mux_sync = data_mux_sync4; + data_mux_sync4 = data_mux_sync3; + data_mux_sync3 = data_mux_sync2; + data_mux_sync2 = data_mux_sync1; + data_mux_sync1 = data_mux; + end + + always @(data_mux_sync) begin + cntvalue_updated_sync = cntvalue_updated_async; + end + + always @(CNTVALUEIN_in or glblGSR) begin + CNTVALUEIN_INTEGER = CNTVALUEIN_in; + end + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(ODATAIN_in or CASC_IN_in or CASC_RETURN_in or CASCADE_REG) begin + case (CASCADE_REG) + "NONE": begin + data_mux = ODATAIN_in; + cdataout_pre = ODATAIN_in; + end + "MASTER": begin + data_mux = CASC_RETURN_in; + cdataout_pre = ODATAIN_in; + end + "SLAVE_END" : begin + data_mux = CASC_IN_in; + cdataout_pre = 1'b0; + end + "SLAVE_MIDDLE" : begin + data_mux = CASC_RETURN_in; + cdataout_pre = CASC_IN_in; + end + default : begin + $display("Error: [Unisim %s-7] The attribute CASCADE is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + $finish; + end + endcase // case(CASCADE_REG) + end // always @(ODATAIN_in or CASC_IN_in) + + always @ (cntvalue_updated or data_mux or CASC_RETURN_in or DELAY_FORMAT_REG) begin + delay_value = (cntvalue_updated[2:0]*PER_BIT_FINE_DELAY) + (cntvalue_updated[8:3]*PER_BIT_MEDIUM_DELAY) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ; + case (CASCADE_REG) + "NONE" : begin + delay_value = delay_value + ODATAIN_INTRINSIC_DELAY; + end + "MASTER","SLAVE_MIDDLE" : begin + delay_value = delay_value + CASC_RET_INTRINSIC_DELAY; + end + "SLAVE_END" : begin + delay_value = delay_value + CASC_IN_INTRINSIC_DELAY; + end + default : begin + $display("Error: [Unisim %s-8] The attribute CASCADE is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE. Instance: %m", MODULE_NAME, CASCADE_REG); + $finish; + end + endcase // case(CASCADE_REG) + end + + always @ (*) begin + tap_out <= #delay_value data_mux; + end + +// end behavioral model + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; +`endif + + wire ci_co_en; + wire ci_do_en; + wire cr_do_en; + wire o_co_en; + wire o_do_en; + + assign ci_do_en = (delay_value == 0) && (CASCADE_REG == "SLAVE_END"); + assign ci_co_en = (delay_value == 0) && (CASCADE_REG == "SLAVE_MIDDLE"); + assign cr_do_en = (delay_value == 0) && ((CASCADE_REG == "SLAVE_MIDDLE") || (CASCADE_REG == "MASTER")); + assign o_do_en = (delay_value == 0) && (CASCADE_REG == "NONE"); + assign o_co_en = (delay_value == 0) && ((CASCADE_REG == "NONE") || (CASCADE_REG == "MASTER")); + + specify + if (ci_co_en) (CASC_IN => CASC_OUT) = (0:0:0, 0:0:0); + if (ci_do_en) (CASC_IN => DATAOUT) = (0:0:0, 0:0:0); + if (cr_do_en) (CASC_RETURN => DATAOUT) = (0:0:0, 0:0:0); + (CLK *> CNTVALUEOUT) = (100:100:100, 100:100:100); + if (o_co_en) (ODATAIN => CASC_OUT) = (0:0:0, 0:0:0); + if (o_do_en) (ODATAIN => DATAOUT) = (0:0:0, 0:0:0); + (negedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + (posedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] == 'b0) (negedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] != 'b0) (negedge RST *> (CNTVALUEOUT +: 1)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] == 'b0) (posedge RST *> (CNTVALUEOUT +: 0)) = (100:100:100, 100:100:100); + //if (gen_mc_fixed_dly_ratio[8:0] != 'b0) (posedge RST *> (CNTVALUEOUT +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OR2L.v b/verilog/src/unisims/OR2L.v new file mode 100644 index 0000000..c9c2c8d --- /dev/null +++ b/verilog/src/unisims/OR2L.v @@ -0,0 +1,73 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Latch used as 2-input OR Gate +// /___/ /\ Filename : OR2L.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/26/08 - Initial version. +// 04/01/08 - Add GSR +// 02/19/09 - 509139 - Order port name +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 04/16/13 - 683925 - add invertible pin support. +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OR2L #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [0:0] IS_SRI_INVERTED = 1'b0 +)( + output O, + + input DI, + input SRI +); + + tri0 GSR = glbl.GSR; + + wire SRI_in; + + assign SRI_in = IS_SRI_INVERTED ^ SRI; + + assign O = ~GSR && (DI || SRI_in); + +`ifdef XIL_TIMING + reg notifier; + + specify + (DI => O) = (0:0:0, 0:0:0); + (SRI => O) = (0:0:0, 0:0:0); + $width (negedge SRI, 0:0:0, 0, notifier); + $width (posedge SRI, 0:0:0, 0, notifier); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule +`endcelldefine diff --git a/verilog/src/unisims/OSERDES.v b/verilog/src/unisims/OSERDES.v new file mode 100644 index 0000000..6637f8d --- /dev/null +++ b/verilog/src/unisims/OSERDES.v @@ -0,0 +1,1087 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1i +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Output Serializer +// /___/ /\ Filename : OSERDES.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus. +// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV +// 08/21/06 - CR 210819 -- Added timing checks for DDR mode +// 06/06/07 - Fixed timescale values +// 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. +// 04/16/08 - CR 468871 Negative SetupHold fix +// 04/23/09 - CR 516748 simprim only fix +// 06/01/09 - CR 523601 simprim only (timing) fix for Tristate Output +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ, + CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE); + + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TQ; + + input CLK; + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + tri0 GSR = glbl.GSR; + input OCE; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + input T1; + input T2; + input T3; + input T4; + input TCE; + + reg c23, c45, c67; + reg t1r, t2r, t3r, t4r; + reg io_sdata_edge, io_odata_edge, io_ddr_data; + reg iot_sdata_edge, iot_odata_edge, iot_ddr_data; + reg data1, data2, data3, data4, data5, data6; + reg serdes_mode_int, serdes_int; + reg data_rate_oq_int, ddr_clk_edge_int; + reg [1:0] data_rate_tq_int, tristate_width_int; + reg [1:0] sel; + reg d1r, d2r, d3r, d4r, d5r, d6r; + reg q0, q1, q2, q3; + reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2; + reg qt1, qt2, qt2n; + reg load, qhr, qlr, mux; + reg data1t, data2t; + reg oq_out = INIT_OQ, tq_out = INIT_TQ; + reg [3:0] data_width_int; + reg notifier; + + wire oqsr, oqrev; + wire tqsr, tqrev; + wire c2p, c3; + wire [2:0] sel1_4; + wire [3:0] sel5_6; + wire [4:0] sel_tri; + wire [6:0] seltq; + wire [3:0] seloq; + + wire clk_in; + wire clkdiv_in; + wire d1_in; + wire d2_in; + wire d3_in; + wire d4_in; + wire d5_in; + wire d6_in; + wire gsr_in; + wire oce_in; + wire sr_in; + wire rev_in; + wire shiftin1_in; + wire shiftin2_in; + wire t1_in; + wire t2_in; + wire t3_in; + wire t4_in; + wire tce_in; + + wire shiftout1_out; + wire shiftout2_out; + + buf b_oq (OQ, oq_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + buf b_tq (TQ, tq_out); + + buf b_clk (clk_in, CLK); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d1 (d1_in, D1); + buf b_d2 (d2_in, D2); + buf b_d3 (d3_in, D3); + buf b_d4 (d4_in, D4); + buf b_d5 (d5_in, D5); + buf b_d6 (d6_in, D6); + buf b_gsr (gsr_in, GSR); + buf b_oce (oce_in, OCE); + buf b_r (sr_in, SR); + buf b_s (rev_in, REV); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + buf b_t1 (t1_in, T1); + buf b_t2 (t2_in, T2); + buf b_t3 (t3_in, T3); + buf b_t4 (t4_in, T4); + buf b_tce (tce_in, TCE); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + +///////////////////////////////////////////////////////// +// +// Delay assignments +// +///////////////////////////////////////////////////////// + +// Data output delays + + localparam io_ffd = 1; // clock to out delay for flip flops driven by clk + localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv + localparam io_mxd = 1; // 60 ps mux delay + localparam io_mxr1 = 1; // mux before 2nd rank of flops + + // Programmable load generator + localparam ffdcnt = 1; + localparam mxdcnt = 1; +// CR 516748 +// localparam ffrst = 145; // clock to out delay for flop in PLSG + localparam ffrst = 45; // clock to out delay for flop in PLSG + + // Tristate output delays + localparam iot_ffd = 1; +// CR 523601 +// localparam iot_mxd = 1; + localparam iot_mxd = 20; +///////////////////////////////////////////////////////////// + + + always @(gsr_in) + + if (gsr_in) begin + + assign oq_out = INIT_OQ; + assign d1rnk2 = INIT_OQ; + assign d2rnk2 = INIT_OQ; + assign d2nrnk2 = INIT_OQ; + assign d6rnk2 = 1'b0; + assign d5rnk2 = 1'b0; + assign d4rnk2 = 1'b0; + assign d3rnk2 = 1'b0; + + assign d6r = 1'b0; + assign d5r = 1'b0; + assign d4r = 1'b0; + assign d3r = 1'b0; + assign d2r = 1'b0; + assign d1r = 1'b0; + +// PLG + assign q3 = 1'b0; + assign q2 = 1'b0; + assign q1 = 1'b0; + assign q0 = 1'b0; + +// Tristate output + assign tq_out = INIT_TQ; + assign qt1 = INIT_TQ; + assign qt2 = INIT_TQ; + assign qt2n = INIT_TQ; + assign t4r = 1'b0; + assign t3r = 1'b0; + assign t2r = 1'b0; + assign t1r = 1'b0; + + end + else begin + + deassign oq_out; + deassign d1rnk2; + deassign d2rnk2; + deassign d2nrnk2; + deassign d6rnk2; + deassign d5rnk2; + deassign d4rnk2; + deassign d3rnk2; + deassign d6r; + deassign d5r; + deassign d4r; + deassign d3r; + deassign d2r; + deassign d1r; + +// PLG + deassign q3; + deassign q2; + deassign q1; + deassign q0; + +// Tristate output + deassign tq_out; + deassign qt1; + deassign qt2; + deassign qt2n; + deassign t4r; + deassign t3r; + deassign t2r; + deassign t1r; + + end + + + initial begin + + case (SERDES_MODE) + + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + + endcase // case(SERDES_MODE) + + + serdes_int <= 1'b1; // SERDES = TRUE + + ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE + + + case (DATA_RATE_OQ) + + "SDR" : data_rate_oq_int <= 1'b1; + "DDR" : data_rate_oq_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + #1 $finish; + end + + endcase // case(DATA_RATE_OQ) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + #1 $finish; + end + + endcase // case(DATA_WIDTH) + + + case (DATA_RATE_TQ) + + "BUF" : data_rate_tq_int <= 2'b00; + "SDR" : data_rate_tq_int <= 2'b01; + "DDR" : data_rate_tq_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ); + #1 $finish; + end + + endcase // case(DATA_RATE_TQ) + + + case (TRISTATE_WIDTH) + + 1 : tristate_width_int <= 2'b00; + 2 : tristate_width_int <= 2'b01; + 4 : tristate_width_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH); + #1 $finish; + end + + endcase // case(TRISTATE_WIDTH) + + + end // initial begin + + + assign shiftout1_out = d3rnk2 & serdes_mode_int; + + assign shiftout2_out = d4rnk2 & serdes_mode_int; + + assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int); + + assign c3 = !c2p; + + assign sel1_4 = {serdes_int, load, data_rate_oq_int}; + + assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int}; + +// Tristate output + assign sel_tri = {load, data_rate_tq_int, tristate_width_int}; + + assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev}; + + assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev}; + + assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ); + + assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ); + + assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ); + + assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ); + +// 3 flops to create DDR operations of 4 latches +// asynchronous operation + always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d1rnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d1rnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d1rnk2 <= # io_ffd data1; + + else if (oce_in == 1'b0) // to match with HW + + d1rnk2 <= # io_ffd oq_out; + + end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 2nd latch +// asynchronous operation + always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d2rnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d2rnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d2rnk2 <= # io_ffd data2; + + else if (oce_in == 1'b0) // to match with HW + + d2rnk2 <= # io_ffd oq_out; + + end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation + always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d2nrnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d2nrnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d2nrnk2 <= # io_ffd d2rnk2; + + else if (oce_in == 1'b0) // to match with HW + + d2nrnk2 <= # io_ffd oq_out; + + end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// last 4 flops which only have reset and init +// asynchronous operation + always @ (posedge clk_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + d3rnk2 <= # io_ffd 1'b0; + d4rnk2 <= # io_ffd 1'b0; + d5rnk2 <= # io_ffd 1'b0; + d6rnk2 <= # io_ffd 1'b0; + + end + else begin + + d3rnk2 <= # io_ffd data3; + d4rnk2 <= # io_ffd data4; + d5rnk2 <= # io_ffd data5; + d6rnk2 <= # io_ffd data6; + + end + + end // always @ (posedge clk_in or posedge sr_in) + + +// First rank of flops for input data +// asynchronous operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + d1r <= # io_ffcd 1'b0; + d2r <= # io_ffcd 1'b0; + d3r <= # io_ffcd 1'b0; + d4r <= # io_ffcd 1'b0; + d5r <= # io_ffcd 1'b0; + d6r <= # io_ffcd 1'b0; + + end + else begin + + d1r <= # io_ffcd d1_in; + d2r <= # io_ffcd d2_in; + d3r <= # io_ffcd d3_in; + d4r <= # io_ffcd d4_in; + d5r <= # io_ffcd d5_in; + d6r <= # io_ffcd d6_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Muxs for 2nd rank of flops + always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin + + casex (sel1_4) + + 3'b100: data1 <= # io_mxr1 d3rnk2; + 3'b110: data1 <= # io_mxr1 d1r; + 3'b101: data1 <= # io_mxr1 d2rnk2; + 3'b111: data1 <= # io_mxr1 d1r; + default: data1 <= # io_mxr1 d3rnk2; + + endcase + + end + + + always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin + + casex (sel1_4) + + 3'b100: data2 <= # io_mxr1 d4rnk2; + 3'b110: data2 <= # io_mxr1 d2r; + 3'b101: data2 <= # io_mxr1 d3rnk2; + 3'b111: data2 <= # io_mxr1 d2r; + default: data2 <= # io_mxr1 d4rnk2; + + endcase + + end + + +//Note: To stop data rate of 00 from being illegal, register data is fed to mux + always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin + + casex (sel1_4) + + 3'b100: data3 <= # io_mxr1 d5rnk2; + 3'b110: data3 <= # io_mxr1 d3r; + 3'b101: data3 <= # io_mxr1 d4rnk2; + 3'b111: data3 <= # io_mxr1 d3r; + default: data3 <= # io_mxr1 d5rnk2; + + endcase + + end + + + always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin + + casex (sel1_4) + + 3'b100: data4 <= # io_mxr1 d6rnk2; + 3'b110: data4 <= # io_mxr1 d4r; + 3'b101: data4 <= # io_mxr1 d5rnk2; + 3'b111: data4 <= # io_mxr1 d4r; + default: data4 <= # io_mxr1 d6rnk2; + + endcase + + end + + + always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin + + casex (sel5_6) + + 4'b1000: data5 <= # io_mxr1 shiftin1_in; + 4'b1010: data5 <= # io_mxr1 d5r; + 4'b1001: data5 <= # io_mxr1 d6rnk2; + 4'b1011: data5 <= # io_mxr1 d5r; + 4'b1100: data5 <= # io_mxr1 1'b0; + 4'b1110: data5 <= # io_mxr1 d5r; + 4'b1101: data5 <= # io_mxr1 d6rnk2; + 4'b1111: data5 <= # io_mxr1 d5r; + default: data5 <= # io_mxr1 shiftin1_in; + + endcase + + end + + + always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin + + casex (sel5_6) + + 4'b1000: data6 <= # io_mxr1 shiftin2_in; + 4'b1010: data6 <= # io_mxr1 d6r; + 4'b1001: data6 <= # io_mxr1 shiftin1_in; + 4'b1011: data6 <= # io_mxr1 d6r; + 4'b1100: data6 <= # io_mxr1 1'b0; + 4'b1110: data6 <= # io_mxr1 d6r; + 4'b1101: data6 <= # io_mxr1 1'b0; + 4'b1111: data6 <= # io_mxr1 d6r; + default: data6 <= # io_mxr1 shiftin2_in; + + endcase + + end + + +// Logic to generate same edge data from d1rnk2 and d2nrnk2; + always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin + + io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3); + + end + +// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2 + always @(clk_in or d1rnk2 or d2rnk2) begin + + case (clk_in) + + 1'b0: io_odata_edge <= # io_mxd d2rnk2; + 1'b1: io_odata_edge <= # io_mxd d1rnk2; + default: io_odata_edge <= # io_mxd d1rnk2; + + endcase + + end + + +// Logic to same edge and opposite data into just ddr data + always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin + + io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int); + + end + + +// Output mux to generate OQ + always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin + + casex (seloq) + + 4'bXX01: oq_out <= # io_mxd 1'b1; + 4'bXX10: oq_out <= # io_mxd 1'b0; + 4'bXX11: oq_out <= # io_mxd 1'b0; + 4'b0000: oq_out <= # io_mxd oq_out; + 4'b0100: oq_out <= # io_mxd oq_out; + 4'b1000: oq_out <= # io_mxd io_ddr_data; + 4'b1100: oq_out <= # io_mxd d1rnk2; + default: oq_out <= # io_mxd io_ddr_data; + + endcase + + end + + +// Set value of counter in bitslip controller + always @ (data_rate_oq_int or data_width_int) begin + + casex ({data_rate_oq_int, data_width_int}) + + 5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end + 5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end + 5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end + 5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end + 5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end + 5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end + 5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end + + default: begin + $display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0); + $finish; + end + + endcase + + end // always @ (data_rate_oq_int or data_width_int) + + + + +/////////////////////////////////////////////////////////////// +// Programmable Load Generator (PLG) +// Divide by 2-8 counter with load enable output +////////////////////////////////////////////////////////////////// + +// flops for counter +// asynchronous reset + always @ (posedge qhr or posedge clk_in) begin + + if (qhr) begin + + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + + end + else begin + + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + + end + + end // always @ (posedge qhr or posedge clk_in) + + +// mux settings for counter + always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin + + case (sel) + + 2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1)); + 2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2)); + 2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3)); + 2'b11: mux <= # mxdcnt !q3; + default: mux <= # mxdcnt 1'b0; + + endcase + + end + + +// mux decoding for load signal + always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin + + case (sel) + + 2'b00: load <= # mxdcnt q0; + 2'b01: load <= # mxdcnt q0 & q1; + 2'b10: load <= # mxdcnt q0 & q2; + 2'b11: load <= # mxdcnt q0 & q3; + default: load <= # mxdcnt 1'b0; + + endcase + + end + + +// flops to reset counter +// Low speed flop +// asynchronous reset + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qlr <= # ffrst 1'b1; + + else + + qlr <= # ffrst 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed flop +// asynchronous reset + always @ (posedge sr_in or posedge clk_in) begin + + if (sr_in == 1'b1) + + qhr <= # ffdcnt 1'b1; + + else + + qhr <= # ffdcnt qlr; + + end // always @ (posedge sr_in or posedge clk_in) + + + +/////////////////////////////////////////////////////// +// +// Tristate Output cell +// +//////////////////////////////////////////////////////// + +// 3 flops to create DDR operations of 4 latches +// Representation of top latch +// asynchronous operation + always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt1 <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt1 <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt1 <= # iot_ffd data1t; + + else if (tce_in == 1'b0) + + qt1 <= # iot_ffd tq_out; + + end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 2nd latch +// asynchronous operation + always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt2 <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt2 <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt2 <= # iot_ffd data2t; + + else if (tce_in == 1'b0) + + qt2 <= # iot_ffd tq_out; + + end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation + always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt2n <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt2n <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt2n <= # iot_ffd qt2; + + else if (tce_in == 1'b0) + + qt2n <= # iot_ffd tq_out; + + end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// First rank of flops +// asynchronous reset operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + t1r <= # iot_ffd 1'b0; + t2r <= # iot_ffd 1'b0; + t3r <= # iot_ffd 1'b0; + t4r <= # iot_ffd 1'b0; + + end + else begin + + t1r <= # iot_ffd t1_in; + t2r <= # iot_ffd t2_in; + t3r <= # iot_ffd t3_in; + t4r <= # iot_ffd t4_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Data Muxs for tristate otuput signals + always @ (sel_tri or t1_in or t1r or t3r) begin + + casex (sel_tri) + + 5'b00000: data1t <= # iot_mxd t1_in; + 5'b10000: data1t <= # iot_mxd t1_in; + 5'bX0000: data1t <= # iot_mxd t1_in; + 5'b00100: data1t <= # iot_mxd t1_in; + 5'b10100: data1t <= # iot_mxd t1_in; + 5'bX0100: data1t <= # iot_mxd t1_in; + 5'b01001: data1t <= # iot_mxd t1_in; + 5'b11001: data1t <= # iot_mxd t1_in; + 5'b01010: data1t <= # iot_mxd t3r; + 5'b11010: data1t <= # iot_mxd t1r; +// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + default: begin + $display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0); + $finish; + end + + endcase + + end + +// For data 2, width of 1 is inserted as acceptable for buf and sdr +// The capability exists in the device if the feature is added + always @ (sel_tri or t2_in or t2r or t4r) begin + + casex (sel_tri) + + 5'b00000: data2t <= # iot_mxd t2_in; + 5'b00100: data2t <= # iot_mxd t2_in; + 5'b10000: data2t <= # iot_mxd t2_in; + 5'b10100: data2t <= # iot_mxd t2_in; + 5'bX0000: data2t <= # iot_mxd t2_in; + 5'bX0100: data2t <= # iot_mxd t2_in; + 5'b00X00: data2t <= # iot_mxd t2_in; + 5'b10X00: data2t <= # iot_mxd t2_in; + 5'bX0X00: data2t <= # iot_mxd t2_in; + 5'b01001: data2t <= # iot_mxd t2_in; + 5'b11001: data2t <= # iot_mxd t2_in; + 5'bX1001: data2t <= # iot_mxd t2_in; + 5'b01010: data2t <= # iot_mxd t4r; + 5'b11010: data2t <= # iot_mxd t2r; +// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + default: begin + $display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0); + $finish; + end + + endcase + + end + + +// Logic to generate same edge data from qt1, qt3; + always @ (clk_in or c3 or qt1 or qt2n) begin + + iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3); + + end + + +// Mux to create opposite edge DDR function + always @ (clk_in or qt1 or qt2) begin + + case (clk_in) + + 1'b0: iot_odata_edge <= # iot_mxd qt2; + 1'b1: iot_odata_edge <= # iot_mxd qt1; + default: iot_odata_edge <= 1'b0; + + endcase + + end + + +// Logic to same edge and opposite data into just ddr data + always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin + + iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int); + + end + +// Output mux to generate TQ +// Note that the TQ mux can also support T2 combinatorial or +// registered outputs. Those modes are not support in this model. + always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin + + casex (seltq) + + 7'bX01XX01: tq_out <= # iot_mxd 1'b1; + 7'bX10XX01: tq_out <= # iot_mxd 1'b1; + 7'bX01XX10: tq_out <= # iot_mxd 1'b0; + 7'bX10XX10: tq_out <= # iot_mxd 1'b0; + 7'bX01XX11: tq_out <= # iot_mxd 1'b0; + 7'bX10XX11: tq_out <= # iot_mxd 1'b0; + 7'bX0000XX: tq_out <= # iot_mxd data1t; + 7'b0010000: tq_out <= # iot_mxd tq_out; + 7'b0100100: tq_out <= # iot_mxd tq_out; + 7'b0101000: tq_out <= # iot_mxd tq_out; + 7'b1010000: tq_out <= # iot_mxd qt1; + 7'b1100100: tq_out <= # iot_mxd iot_ddr_data; + 7'b1101000: tq_out <= # iot_mxd iot_ddr_data; + default: tq_out <= # iot_mxd iot_ddr_data; + + endcase + + end + +//*** Timing Checks Start here + +`ifndef XIL_TIMING + + assign clk_in = CLK; + assign oce_in = OCE; + assign tce_in = TCE; + assign clkdiv_in = CLKDIV; + assign d1_in = D1; + assign d2_in = D2; + assign d3_in = D3; + assign d4_in = D4; + assign d5_in = D5; + assign d6_in = D6; + assign rev_in = REV; + assign sr_in = SR; + assign t1_in = T1; + assign t2_in = T2; + assign t3_in = T3; + assign t4_in = T4; + +`endif + + + specify + + (CLK => OQ) = (100:100:100, 100:100:100); + (CLK => TQ) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + (SR => OQ) = (0:0:0, 0:0:0); + (REV => OQ) = (0:0:0, 0:0:0); + (T1 => TQ) = (0:0:0, 0:0:0); + (SR => TQ) = (0:0:0, 0:0:0); + (REV => TQ) = (0:0:0, 0:0:0); + + $setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in); + $setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in); + $setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in); + $setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in); + $setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in); + $setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in); + $setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in); + $setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in); + $setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in); + $setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in); + $setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in); + $setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in); + + $setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in); + $setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in); + $setuphold (posedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in); + $setuphold (posedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in); + + $setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in); + $setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in); + $setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in); + $setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in); + $setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in); + $setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in); + $setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in); + $setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in); + + $setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in); + $setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in); + $setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in); + $setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in); + + $setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in); + $setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in); + $setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in); + $setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in); + + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + + $recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier); +// CR 232324 + $setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in); + $setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in); + $setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in); + $setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in); + $setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in); + $setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in); + $setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in); + $setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in); + +// CR 210819 + $setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in); + $setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in); + $setuphold (negedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in); + $setuphold (negedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in); + + $recrem (negedge REV, negedge CLK, 0:0:0, 0:0:0, notifier); + $recrem (negedge SR, negedge CLK, 0:0:0, 0:0:0, notifier); + + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLKDIV, 0:0:0, 0, notifier); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLKDIV, 0:0:0, 0, notifier); + +`endif + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // OSERDES + +`endcelldefine diff --git a/verilog/src/unisims/OSERDESE1.v b/verilog/src/unisims/OSERDESE1.v new file mode 100644 index 0000000..75ddcea --- /dev/null +++ b/verilog/src/unisims/OSERDESE1.v @@ -0,0 +1,3290 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Output Serializer +// /___/ /\ Filename : OSERDESE1.v +// \ \ / \ Timestamp : Tue Sep 16 15:30:44 PDT 2008 +// \___\/\___\ +// +// Revision: +// 09/16/08 - Initial version. +// 12/05/08 - IR 495397. +// 01/13/09 - IR 503429. +// 01/15/09 - IR 503783 CLKPERF is not inverted for OFB/ofb_out. +// 02/06/09 - CR 507373 Removed IOCLKGLITCH and CLKB +// 02/26/09 - CR 510489 fixed SHIFTIN2_in +// 03/16/09 - CR 512140 and 512139 -- sdf load errors +// 01/27/10 - CR 546419 Updated specify block +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 09/04/12 - 676501 CLK -> OFB specify path missing +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module OSERDESE1 (OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ, + CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TCE, WC); + + + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter integer DDR3_DATA = 1; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter INTERFACE_TYPE = "DEFAULT"; + parameter integer ODELAY_USED = 0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + + + `ifdef XIL_TIMING + parameter LOC = "UNPLACED"; + `endif + +//------------------------------------------------------------- +// Outputs: +//------------------------------------------------------------- +// OQ: Data output +// TQ: Output of tristate mux +// SHIFTOUT1: Carry out data 1 for slave +// SHIFTOUT2: Carry out data 2 for slave +// OFB: O Feedback output + +// +//------------------------------------------------------------- +// Inputs: +//------------------------------------------------------------- +// +// Inputs: +// CLK: High speed clock from DCM +// CLKB: Inverted High speed clock from DCM +// CLKDIV: Low speed divided clock from DCM +// CLKPERF: Performance Path clock +// CLKPERFDELAY: delayed Performance Path clock +// D1, D2, D3, D4, D5, D6 : Data inputs +// OCE: Clock enable for output data flops +// ODV: ODELAY value > 140 degrees +// RST: Reset control +// T1, T2, T3, T4: tristate inputs +// SHIFTIN1: Carry in data 1 for master from slave +// SHIFTIN2: Carry in data 2 for master from slave +// TCE: Tristate clock enable +// WC: Write command given by memory controller + + output OCBEXTEND; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TFB; + output TQ; + + input CLK; + input CLKDIV; + input CLKPERF; + input CLKPERFDELAY; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input ODV; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input T1; + input T2; + input T3; + input T4; + input TCE; + input WC; + + +// + wire SERDES, DDR_CLK_EDGE; + wire [5:0] SRTYPE; + wire WC_DELAY; + wire [4:0] SELFHEAL; + + + wire load; + wire qmux1, qmux2, tmux1, tmux2; + wire data1, data2, triin1, triin2; + wire d2rnk2; + wire CLKD; + wire CLKDIVD; + wire iodelay_state; + +// attribute + reg data_rate_int; + reg [3:0] data_width_int; + reg [1:0] tristate_width_int; + reg data_rate_oq_int; + reg [1:0] data_rate_tq_int; + reg ddr3_data_int; + reg interface_type_int; + reg odelay_used_int; + reg serdes_mode_int; + +// Output signals + wire ioclkglitch_out, ocbextend_out, ofb_out, oq_out, tq_out, shiftout1_out, shiftout2_out; + wire tfb_out; + +// Other signals + tri0 GSR = glbl.GSR; + + reg notifier; + + wire CLK_in; + wire CLKDIV_in; + wire CLKPERF_in; + wire CLKPERFDELAY_in; + wire D1_in; + wire D2_in; + wire D3_in; + wire D4_in; + wire D5_in; + wire D6_in; + wire OCE_in; + wire ODV_in; + wire RST_in; + wire SHIFTIN1_in; + wire SHIFTIN2_in; + wire T1_in; + wire T2_in; + wire T3_in; + wire T4_in; + wire TCE_in; + wire WC_in; + +`ifndef XIL_TIMING + + assign CLK_in = CLK; + assign CLKDIV_in = CLKDIV; + assign D1_in = D1; + assign D2_in = D2; + assign D3_in = D3; + assign D4_in = D4; + assign D5_in = D5; + assign D6_in = D6; + assign OCE_in = OCE; + assign T1_in = T1; + assign T2_in = T2; + assign T3_in = T3; + assign T4_in = T4; + assign TCE_in = TCE; + assign WC_in = WC; + +`endif // `ifndef XIL_TIMING + + + assign CLKPERF_in = CLKPERF; +// assign CLKPERFDELAY_in = CLKPERFDELAY; +// IR 495397 & IR 499954 +// assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY; + generate + case (ODELAY_USED) + 0: assign CLKPERFDELAY_in = CLKPERF; + 1: assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY; + endcase + endgenerate + + assign SHIFTIN1_in = SHIFTIN1; + assign SHIFTIN2_in = SHIFTIN2; + assign ODV_in = ODV; + assign RST_in = RST; + + buf b_ocbextend (OCBEXTEND, ocbextend_out); + buf b_ofb (OFB, ofb_out); + buf b_oq (OQ, oq_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + buf b_tfb (TFB, tfb_out); + buf b_tq (TQ, tq_out); + + + initial begin + +//------------------------------------------------- +//----- DATA_RATE_OQ check +//------------------------------------------------- + case (DATA_RATE_OQ) + "SDR" : data_rate_oq_int <= 1'b1; + "DDR" : data_rate_oq_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + #1 $finish; + end + endcase // case(DATA_RATE_OQ) + +//------------------------------------------------- +//----- DATA_RATE_TQ check +//------------------------------------------------- + case (DATA_RATE_TQ) + + "BUF" : data_rate_tq_int <= 2'b00; + "SDR" : data_rate_tq_int <= 2'b01; + "DDR" : data_rate_tq_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ); + #1 $finish; + end + + endcase // case(DATA_RATE_TQ) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + +//------------------------------------------------- +//----- DDR3_DATA check +//------------------------------------------------- + case (DDR3_DATA) + 0 : ddr3_data_int <= 1'b0; + 1 : ddr3_data_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DDR3_DATA on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 0 or 1", DDR3_DATA); + #1 $finish; + end + endcase // case(DDR3_DATA) + +//------------------------------------------------- +//----- INTERFACE_TYPE check +//------------------------------------------------- + case (INTERFACE_TYPE) + "DEFAULT" : interface_type_int <= 1'b0; + "MEMORY_DDR3" : interface_type_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, or MEMORY_DDR3", INTERFACE_TYPE); + #1 $finish; + end + endcase // INTERFACE_TYPE + + +//------------------------------------------------- +//----- ODELAY_USED check +//------------------------------------------------- + case (ODELAY_USED) + +// "FALSE" : odelay_used_int <= 1'b0; +// "TRUE" : odelay_used_int <= 1'b1; + 0 : odelay_used_int <= 1'b0; + 1 : odelay_used_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute ODELAY_USED on OSERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", ODELAY_USED); + #1 $finish; + end + + endcase // case(ODELAY_USED) + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) + + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + + endcase // case(SERDES_MODE) + +//------------------------------------------------- +//----- TRISTATE_WIDTH check +//------------------------------------------------- + case (TRISTATE_WIDTH) + + 1 : tristate_width_int <= 2'b00; + 2 : tristate_width_int <= 2'b01; + 4 : tristate_width_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH); + #1 $finish; + end + + endcase // case(TRISTATE_WIDTH) + +//------------------------------------------------- + end // initial begin + +//------------------------------------------------- + + assign SERDES = 1'b1; + assign SRTYPE = 6'b111111; + assign DDR_CLK_EDGE = 1'b1; + assign WC_DELAY = 1'b0; + assign SELFHEAL = 5'b00000; + + assign #0 CLKD = CLK; + assign #0 CLKDIVD = CLKDIV; + + + assign #10 ofb_out = (ODELAY_USED == 1)? CLKPERF : oq_out; + assign #10 tfb_out = iodelay_state; + + +///////////////////////////////////////////////////////// +// +// Delay assignments +// +///////////////////////////////////////////////////////// + +// Data output delays +defparam dfront.FFD = 1; // clock to out delay for flip flops +// driven by clk +defparam datao.FFD = 1; // clock to out delay for flip flops +// driven by clk +defparam dfront.FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +defparam dfront.MXD = 1; // mux delay + +defparam dfront.MXR1 = 1; // mux before 2nd rank of flops + +// Programmable load generator +defparam dfront.ldgen.ffdcnt = 1; +defparam dfront.ldgen.mxdcnt = 1; +defparam dfront.ldgen.FFRST = 145; // clock to out delay for flop in PLSG + +// Tristate output delays +defparam tfront.ffd = 1; // clock to out delay for flip flops +defparam tfront.mxd = 1; // mux delay + +defparam trio.ffd = 1; // clock to out delay for flip flops +defparam trio.mxd = 1; // mux delay + +//------------------------------------------------------------------ +// Instantiate output data section +//------------------------------------------------------------------ + +rank12d_oserdese1_vlog dfront (.D1(D1_in), .D2(D2_in), .D3(D3_in), .D4(D4_in), .D5(D5_in), .D6(D6_in), + .d2rnk2(d2rnk2), + .SHIFTIN1(SHIFTIN1_in), .SHIFTIN2(SHIFTIN2_in), + .C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .OCE(OCE_in), + .data1(data1), .data2(data2), .SHIFTOUT1(shiftout1_out), .SHIFTOUT2(shiftout2_out), + .DATA_RATE_OQ(data_rate_oq_int), .DATA_WIDTH(data_width_int), + .SERDES_MODE(serdes_mode_int), .load(load), + .IOCLK_GLITCH(ioclkglitch_out), + .INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ)); + + +trif_oserdese1_vlog tfront (.T1(T1_in), .T2(T2_in), .T3(T3_in), .T4(T4_in), .load(load), + .C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .TCE(TCE_in), + .DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int), + .INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ), + .data1(triin1), .data2(triin2)); + + +txbuffer_oserdese1_vlog DDR3FIFO (.iodelay_state(iodelay_state), .qmux1(qmux1), .qmux2(qmux2), .tmux1(tmux1), .tmux2(tmux2), + .d1(data1), .d2(data2), .t1(triin1), .t2(triin2), .trif(tq_out), + .WC(WC_in), .ODV(ODV_in), .extra(ocbextend_out), + .clk(CLK_in), .clkdiv(CLKDIV_in), .bufo(CLKPERFDELAY_in), .bufop(CLKPERF_in), .rst(RST_in), + .ODELAY_USED(odelay_used_int), .DDR3_DATA(ddr3_data_int), + .DDR3_MODE(interface_type_int)); + +dout_oserdese1_vlog datao (.data1(qmux1), .data2(qmux2), + .CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .OCE(OCE_in), + .OQ(oq_out), .d2rnk2(d2rnk2), + .DATA_RATE_OQ(data_rate_oq_int), + .INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ), + .DDR3_MODE(interface_type_int)); + +tout_oserdese1_vlog trio (.data1(tmux1), .data2(tmux2), + .CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .TCE(TCE_in), + .DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int), + .INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ), + .TQ(tq_out), .DDR3_MODE(interface_type_int)); + + +`ifndef XIL_TIMING + specify + ( CLK => OFB) = (100, 100); + ( CLK => OQ) = (100, 100); + ( CLK => TQ) = (100, 100); + ( CLKPERF => OQ) = (100, 100); + ( CLKPERF => TQ) = (100, 100); + ( CLKPERFDELAY => OQ) = (100, 100); + ( CLKPERFDELAY => TQ) = (100, 100); + ( T1 => TQ) = (0, 0); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING +//*** Timing Checks Start here + + specify + ( CLK => OFB) = (100:100:100, 100:100:100); + ( CLK => OQ) = (100:100:100, 100:100:100); + ( CLK => TQ) = (100:100:100, 100:100:100); + ( CLKPERF => OQ) = (100:100:100, 100:100:100); + ( CLKPERF => TQ) = (100:100:100, 100:100:100); + ( CLKPERFDELAY => OQ) = (100:100:100, 100:100:100); + ( CLKPERFDELAY => TQ) = (100:100:100, 100:100:100); + ( T1 => TQ) = (0:0:0, 0:0:0); + + $setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in); + $setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in); + $setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in); + $setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in); + $setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in); + $setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in); + $setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in); + $setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in); + $setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in); + $setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in); + $setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in); + $setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in); + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in); + $setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in); + $setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in); + $setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in); + $setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in); + $setuphold (posedge CLKDIV, negedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in); + $setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in); + $setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in); + $setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in); + $setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in); + $setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in); + $setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in); + $setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in); + $setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in); + $setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in); + $setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in); + $setuphold (posedge CLKDIV, posedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in); + + specparam PATHPULSE$ = 0; + + endspecify +`endif // `ifdef XIL_TIMING + + +endmodule // OSERDESE1 + +`timescale 1ps/1ps +///////////////////////////////////////////////////////// +// +// module selfheal_oserdese1_vlog +// +/////////////////////////////////////////////////////// +// +// Self healing circuit for Mt Blanc +// This model ONLY works for SERDES operation!! +// +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// dq3 - dq0: Data from load counter +// CLKDIV: Divided clock from PLL +// srint: RESET from load generator +// rst: Set/Reset control +// +// +// +// Outputs: +// SHO: Data output +// +// +// +// Programmable Points +// SELFHEAL: String of 5 bits. 1 as enable and 4 as compare +// Test attributes in model +// +// +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module selfheal_oserdese1_vlog (dq3, dq2, dq1, dq0, + CLKDIV, srint, rst, + SHO); + +input dq3, dq2, dq1, dq0; + +input CLKDIV, srint, rst; + +output SHO; + + +reg shr; + +reg SHO; + + +wire clkint; + +wire error; + +wire rst_in, rst_self_heal; + + +// Programmable Points + +wire [4:0] SELFHEAL; +assign SELFHEAL = 5'b00000; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 10; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 10; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 10; // 60 ps mux delay + +parameter MXR1 = 10; + + + +///////////////////////////////////////// + + +assign clkint = CLKDIV & SELFHEAL[4]; + +assign error = (((~SELFHEAL[4] ^ SELFHEAL[3]) ^ dq3) | ((~SELFHEAL[4] ^ SELFHEAL[2]) ^ dq2) | ((~SELFHEAL[4] ^ SELFHEAL[1]) ^ dq1) | ((~SELFHEAL[4] ^ SELFHEAL[0]) ^ dq0)); + +assign rst_in = (~SELFHEAL[4] | ~srint); + +assign rst_self_heal = (rst | ~shr); + +///////////////////////////////////////// +// Reset Flop +//////////////////////////////////////// + +always @ (posedge clkint or posedge rst) +begin + begin + if (rst) + begin + shr <= # FFD 1'b0; + end + else begin + shr <= #FFD rst_in; + end + end +end + +// Self heal flop +always @ (posedge clkint or posedge rst_self_heal) +begin + begin + + if (rst_self_heal) + begin + SHO <= 1'b0; + end + else + begin + SHO <= # FFD error; + end + end +end + + + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module plg_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// Programmable Load Generator (PLG) +// Divide by 2-8 counter with load enable output +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// c23: Selects between divide by 2 or 3 +// c45: Selects between divide by 4 or 5 +// c67: Selects between divide by 6 or 7 +// sel: Selects which divide function is chosen +// 00:2 or 3, 01:4 or 5, 10:6 or 7, 11:8 +// clk: High speed clock from DCM +// clkdiv: Low speed clock from DCM +// rst: Reset +// +// +// +// Outputs: +// +// load: Loads serdes register at terminal count +// +// +// Test attributes: +// INIT_LOADCNT: 4-bits to init counter +// SRTYPE: 1-bit to control synchronous or asynchronous operation +// SELFHEAL: 5-bits to control self healing feature +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module plg_oserdese1_vlog (c23, c45, c67, sel, + clk, clkdiv, rst, + load, IOCLK_GLITCH); + +input c23, c45, c67; + +input [1:0] sel; + +input clk, clkdiv, rst; + +output load; + +output IOCLK_GLITCH; + +wire SRTYPE; +wire [3:0] INIT_LOADCNT; +wire [4:0] SELFHEAL; +assign SRTYPE = 1'b1; +assign INIT_LOADCNT = 4'b0000; +assign SELFHEAL = 5'b00000; + +reg q0, q1, q2, q3; + +reg qhr, qlr; + +reg load, mux; + +wire cntrrst; + + +assign cntrrst = IOCLK_GLITCH | rst; + + + +// Parameters for gate delays +parameter ffdcnt = 1; +parameter mxdcnt = 1; +parameter FFRST = 145; // clock to out delay for flop in PLSG + + + +////////////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign q3 = INIT_LOADCNT[3]; + assign q2 = INIT_LOADCNT[2]; + assign q1 = INIT_LOADCNT[1]; + assign q0 = INIT_LOADCNT[0]; + end + else + begin + deassign q3; + deassign q2; + deassign q1; + deassign q0; + end +end + + + + + + + +// flops for counter +// asynchronous reset +always @ (posedge qhr or posedge clk) +begin + if (qhr & !SRTYPE) + begin + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + end + else if (!SRTYPE) + begin + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + end +end +// synchronous reset +always @ (posedge clk) +begin + if (qhr & SRTYPE) + begin + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + end + else if (SRTYPE) + begin + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + end +end + + +// mux settings for counter +always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) + begin + case (sel) + 2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1)); + 2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2)); + 2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3)); + 2'b11: mux <= # mxdcnt !q3; + default: mux <= # mxdcnt 1'b0; + endcase + end + + +// mux decoding for load signal +always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) + begin + case (sel) + 2'b00: load <= # mxdcnt q0; + 2'b01: load <= # mxdcnt q0 & q1; + 2'b10: load <= # mxdcnt q0 & q2; + 2'b11: load <= # mxdcnt q0 & q3; + default: load <= # mxdcnt 1'b0; + endcase + end + +// flops to reset counter + +// Low speed flop +// asynchronous reset +always @ (posedge cntrrst or posedge clkdiv) + begin + if (cntrrst & !SRTYPE) + begin + qlr <= # FFRST 1'b1; + end + else if (!SRTYPE) + begin + qlr <= # FFRST 1'b0; + end + end +// synchronous reset +always @ (posedge clkdiv) + begin + if (cntrrst & SRTYPE) + begin + qlr <= # FFRST 1'b1; + end + else if (SRTYPE) + begin + qlr <= # FFRST 1'b0; + end + end + + + +// High speed flop +// asynchronous reset +always @ (posedge cntrrst or posedge clk) + begin + if (cntrrst & !SRTYPE) + begin + qhr <= # ffdcnt 1'b1; + end + else if (!SRTYPE) + begin + qhr <= # ffdcnt qlr; + end + end +// synchronous reset +always @ (posedge clk) + begin + if (cntrrst & SRTYPE) + begin + qhr <= # ffdcnt 1'b1; + end + else if (SRTYPE) + begin + qhr <= # ffdcnt qlr; + end + end + +selfheal_oserdese1_vlog fixcntr (.dq3(q3), .dq2(q2), .dq1(q1), .dq0(q0), + .CLKDIV(clkdiv), .srint(qlr), .rst(rst), + .SHO(IOCLK_GLITCH)); +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module rank12d_oserdese1_vlog +// +// +// This model ONLY works for SERDES operation!! +// Does not include tristate circuit +// +// +//////////////////////////////////////////////////////// +// +// Inputs: +// D1: Data input 1 +// D2: Data input 2 +// D3: Data input 3 +// D4: Data input 4 +// D5: Data input 5 +// D6: Data input 6 +// C: High speed clock from DCM +// OCE: Clock enable for output data flops +// SR: Set/Reset control. For the last 3 flops in OQ +// (d1rnk2, d2rnk2 and d2nrnk2) this function is +// controlled bythe attributes SRVAL_OQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// CLKDIV: Low speed divided clock from DCM +// SHIFTIN1: Carry in data 1 for master from slave +// SHIFTIN2: Carry in data 2 for master from slave +// +// +// +// Outputs: +// data1: Data output mux for top flop +// data2: Data output mux for bottom flop +// SHIFTOUT1: Carry out data 1 for slave +// SHIFTOUT2: Carry out data 2 for slave +// load: Used for the tristate when combined into a single model +// +// +// +// Programmable Points +// DATA_RATE_OQ: Rate control for data output, 1-bit +// sdr (1), ddr (0) +// DATA_WIDTH: Input data width, +// 4-bits, values can be from 2 to 10 +// SERDES_MODE: Denotes master (0) or slave (1) +// SIM_X_INPUT: This attribute is NOT SUPPORTED in this model!!! +// +// +// +// Programmable points for Test model +// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset +// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2, +// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter +// INIT_ORANK1: Init value for 6 registers in 1st rank (6-bits) +// INIT_ORANK2_PARTIAL: Init value for bottom 4 registers in the 2nd rank (4-bits) +// INIT_LOADCNT: Init value for the load counter (4-bits) +// The other 2 registers in the load counter have init bits, but are +// not supported in this model +// SERDES: Indicates that SERDES mode is chosen +// SLEFHEAL: 5-bit to set self heal circuit +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module rank12d_oserdese1_vlog (D1, D2, D3, D4, D5, D6, d2rnk2, + SHIFTIN1, SHIFTIN2, + C, CLKDIV, SR, OCE, + data1, data2, SHIFTOUT1, SHIFTOUT2, + DATA_RATE_OQ, DATA_WIDTH, + SERDES_MODE, load, + IOCLK_GLITCH, + INIT_OQ, SRVAL_OQ); + +input D1, D2, D3, D4, D5, D6; + +input d2rnk2; + +input SHIFTIN1, SHIFTIN2; + +input C, CLKDIV, SR, OCE; + +input INIT_OQ, SRVAL_OQ; + +output data1, data2; + +output SHIFTOUT1, SHIFTOUT2; + +output load; + +output IOCLK_GLITCH; + +// Programmable Points + +input DATA_RATE_OQ; + +input [3:0] DATA_WIDTH; + +input SERDES_MODE; + +wire DDR_CLK_EDGE, SERDES; +wire [3:0] SRTYPE; +wire [4:0] SELFHEAL; + +wire [3:0] INIT_ORANK2_PARTIAL; +wire [5:0] INIT_ORANK1; + +assign DDR_CLK_EDGE = 1'b1; +assign SERDES = 1'b1; +assign SRTYPE = 4'b1111; +assign SELFHEAL = 5'b00000; + +assign INIT_ORANK2_PARTIAL = 4'b0000; +assign INIT_ORANK1 = 6'b000000; + +reg d1r, d2r, d3r, d4r, d5r, d6r; + +reg d3rnk2, d4rnk2, d5rnk2, d6rnk2; + +reg data1, data2, data3, data4, data5, data6; + +reg ddr_data, odata_edge, sdata_edge; + +reg c23, c45, c67; + +reg [1:0] sel; + +wire C2p, C3; + +wire loadint; + +wire [3:0] seloq; + +wire oqsr, oqrev; + +wire [2:0] sel1_4; + +wire [3:0] sel5_6; + +wire [4:0] plgcnt; + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign plgcnt = {DATA_RATE_OQ,DATA_WIDTH}; + +assign sel1_4 = {SERDES,loadint,DATA_RATE_OQ}; + +assign sel5_6 = {SERDES,SERDES_MODE,loadint,DATA_RATE_OQ}; + +assign load = loadint; + +assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev}; + +assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ; + +assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 1; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 1; // 60 ps mux delay + +parameter MXR1 = 1; + +//////////////////////////////////////////// +// Initialization of flops with GSR for test model +/////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign d6rnk2 = INIT_ORANK2_PARTIAL[3]; + assign d5rnk2 = INIT_ORANK2_PARTIAL[2]; + assign d4rnk2 = INIT_ORANK2_PARTIAL[1]; + assign d3rnk2 = INIT_ORANK2_PARTIAL[0]; + + assign d6r = INIT_ORANK1[5]; + assign d5r = INIT_ORANK1[4]; + assign d4r = INIT_ORANK1[3]; + assign d3r = INIT_ORANK1[2]; + assign d2r = INIT_ORANK1[1]; + assign d1r = INIT_ORANK1[0]; + end + else + begin + deassign d6rnk2; + deassign d5rnk2; + deassign d4rnk2; + deassign d3rnk2; + deassign d6r; + deassign d5r; + deassign d4r; + deassign d3r; + deassign d2r; + deassign d1r; + end +end + +///////////////////////////////////////// + + + +// Assign shiftout1 and shiftout2 + +assign SHIFTOUT1 = d3rnk2 & SERDES_MODE; + +assign SHIFTOUT2 = d4rnk2 & SERDES_MODE; + + + + + + +// last 4 flops which only have reset and init +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRTYPE[2]) + begin + d3rnk2 <= # FFD 1'b0; + d4rnk2 <= # FFD 1'b0; + d5rnk2 <= # FFD 1'b0; + d6rnk2 <= # FFD 1'b0; + end + else if (!SRTYPE[2]) + begin + d3rnk2 <= # FFD data3; + d4rnk2 <= # FFD data4; + d5rnk2 <= # FFD data5; + d6rnk2 <= # FFD data6; + + end + end +end +// synchronous operation +always @ (posedge C) +begin + begin + if (SR & SRTYPE[2]) + begin + d3rnk2 <= # FFD 1'b0; + d4rnk2 <= # FFD 1'b0; + d5rnk2 <= # FFD 1'b0; + d6rnk2 <= # FFD 1'b0; + end + else if (SRTYPE[2]) + begin + d3rnk2 <= # FFD data3; + d4rnk2 <= # FFD data4; + d5rnk2 <= # FFD data5; + d6rnk2 <= # FFD data6; + + end + end +end + + + + + + + +/////////////////////////////////////////////////// +// First rank of flops for input data +////////////////////////////////////////////////// + +// asynchronous operation +always @ (posedge CLKDIV or posedge SR) +begin + begin + if (SR & !SRTYPE[3]) + begin + d1r <= # FFCD 1'b0; + d2r <= # FFCD 1'b0; + d3r <= # FFCD 1'b0; + d4r <= # FFCD 1'b0; + d5r <= # FFCD 1'b0; + d6r <= # FFCD 1'b0; + end + else if (!SRTYPE[3]) + begin + d1r <= # FFCD D1; + d2r <= # FFCD D2; + d3r <= # FFCD D3; + d4r <= # FFCD D4; + d5r <= # FFCD D5; + d6r <= # FFCD D6; + + end + end +end +// synchronous operation +always @ (posedge CLKDIV) +begin + begin + if (SR & SRTYPE[3]) + begin + d1r <= # FFCD 1'b0; + d2r <= # FFCD 1'b0; + d3r <= # FFCD 1'b0; + d4r <= # FFCD 1'b0; + d5r <= # FFCD 1'b0; + d6r <= # FFCD 1'b0; + end + else if (SRTYPE[3]) + begin + d1r <= # FFCD D1; + d2r <= # FFCD D2; + d3r <= # FFCD D3; + d4r <= # FFCD D4; + d5r <= # FFCD D5; + d6r <= # FFCD D6; + + end + end +end + +// Muxs for 2nd rank of flops +always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) + begin + + casex (sel1_4) + 3'b100: data1 <= # MXR1 d3rnk2; + 3'b110: data1 <= # MXR1 d1r; + 3'b101: data1 <= # MXR1 d2rnk2; + 3'b111: data1 <= # MXR1 d1r; + default: data1 <= # MXR1 d3rnk2; + endcase + end + +always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) + begin + casex (sel1_4) + 3'b100: data2 <= # MXR1 d4rnk2; + 3'b110: data2 <= # MXR1 d2r; + 3'b101: data2 <= # MXR1 d3rnk2; + 3'b111: data2 <= # MXR1 d2r; + default: data2 <= # MXR1 d4rnk2; + endcase + end + +//Note: To stop data rate of 00 from being illegal, register data is fed to mux +always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) + begin + casex (sel1_4) + 3'b100: data3 <= # MXR1 d5rnk2; + 3'b110: data3 <= # MXR1 d3r; + 3'b101: data3 <= # MXR1 d4rnk2; + 3'b111: data3 <= # MXR1 d3r; + default: data3 <= # MXR1 d5rnk2; + endcase + end + +always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) + begin + casex (sel1_4) + 3'b100: data4 <= # MXR1 d6rnk2; + 3'b110: data4 <= # MXR1 d4r; + 3'b101: data4 <= # MXR1 d5rnk2; + 3'b111: data4 <= # MXR1 d4r; + default: data4 <= # MXR1 d6rnk2; + endcase + end + +always @ (sel5_6 or d5r or d6rnk2 or SHIFTIN1) + begin + casex (sel5_6) + 4'b1000: data5 <= # MXR1 SHIFTIN1; + 4'b1010: data5 <= # MXR1 d5r; + 4'b1001: data5 <= # MXR1 d6rnk2; + 4'b1011: data5 <= # MXR1 d5r; + 4'b1100: data5 <= # MXR1 1'b0; + 4'b1110: data5 <= # MXR1 d5r; + 4'b1101: data5 <= # MXR1 d6rnk2; + 4'b1111: data5 <= # MXR1 d5r; + default: data5 <= # MXR1 SHIFTIN1; + endcase + end + +always @ (sel5_6 or D6 or d6r or SHIFTIN1 or SHIFTIN2) + begin + casex (sel5_6) + 4'b1000: data6 <= # MXR1 SHIFTIN2; + 4'b1010: data6 <= # MXR1 d6r; + 4'b1001: data6 <= # MXR1 SHIFTIN1; + 4'b1011: data6 <= # MXR1 d6r; + 4'b1100: data6 <= # MXR1 1'b0; + 4'b1110: data6 <= # MXR1 d6r; + 4'b1101: data6 <= # MXR1 1'b0; + 4'b1111: data6 <= # MXR1 d6r; + default: data6 <= # MXR1 SHIFTIN2; + endcase + end + + + + +// instantiate programmable load generator +plg_oserdese1_vlog ldgen (.c23(c23), .c45(c45), .c67(c67), .sel(sel), + .clk(C), .clkdiv(CLKDIV), .rst(SR), + .load(loadint), .IOCLK_GLITCH(IOCLK_GLITCH)); + +// Set value of counter in programmable load generator +always @ (plgcnt or c23 or c45 or c67 or sel) +begin + casex (plgcnt) + 5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default: $display("DATA_WIDTH %b and DATA_RATE_OQ %b at %t is an illegal value", DATA_WIDTH, DATA_RATE_OQ, $time); + endcase +end + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module trif_oserdese1_vlog +// +///////////////////////////////////////////////////////// +// +// Inputs: +// +// T1, T2, T3, T4: tristate inputs +// load: Programmable load generator output +// TCE: Tristate clock enable +// SR: Set/Reset control. For the last 3 flops in TQ +// (qt1, qt2 and qt2n) this function is +// controlled bythe attributes SRVAL_TQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// C, C2: High speed clocks +// C2 drives 2nd latch and C3 (inverse of C2) drives +// 3rd latch in output section +// CLKDIV: Low speed clock +// +// +// +// +// Outputs: +// +// TQ: Output of tristate mux +// +// +// Programmable Options: +// +// DATA_RATE_TQ: 2-bit field for types of operaiton +// 0 (buf from T1), 1 (registered output from T1), 2 (ddr) +// TRISTATE_WIDTH: 2-bit field for input width +// 0 (width 1), 1 (width 2), 2 (width 4) +// INIT_TQ: Init TQ output (0,1) +// SRVAL_TQ: This bit to controls value of SR input. +// Only the last 3 flops (qt1, qt2 and qt2n) are +// affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only +// respond to this pin as a reset. Their function +// cannot be changed. SR is 'O' for SET and '1' for RESET. +// +// +// Programmable Test Options: +// SRTYPE: Control S and R as asynchronous (0) or synchronous (1) +// 2-bit value. 1st bit (msb) controls the 4 input flops +// and the 2nd bit (lsb) controls the "3 legacy flops" +// DDR_CLK_EDGE: Same or opposite edge operation +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module trif_oserdese1_vlog (T1, T2, T3, T4, load, + C, CLKDIV, SR, TCE, + DATA_RATE_TQ, TRISTATE_WIDTH, + INIT_TQ, SRVAL_TQ, + data1, data2); + +input T1, T2, T3, T4, load; + +input C, CLKDIV, SR, TCE; + +input [1:0] TRISTATE_WIDTH; + +input [1:0] DATA_RATE_TQ; + +input INIT_TQ, SRVAL_TQ; + +output data1, data2; + +wire DDR_CLK_EDGE; +wire [3:0] INIT_TRANK1; +wire [1:0] SRTYPE; +assign SRTYPE = 2'b11; +assign DDR_CLK_EDGE = 1'b1; +assign INIT_TRANK1 = 4'b0000; + +reg t1r, t2r, t3r, t4r; + +reg qt1, qt2, qt2n; + +reg data1, data2; + +reg sdata_edge, odata_edge, ddr_data; + +wire C2p, C3; + +wire load; + +wire [6:0] tqsel; + +wire [4:0] sel; + +assign sel = {load,DATA_RATE_TQ,TRISTATE_WIDTH}; + + + + + +////////////////////////////////////////////////// + + +// Parameters for gate delays +parameter ffd = 1; +parameter mxd = 1; + + +///////////////////////////// +// Initialization of Flops +//////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign t1r = INIT_TRANK1[0]; + assign t2r = INIT_TRANK1[1]; + assign t3r = INIT_TRANK1[2]; + assign t4r = INIT_TRANK1[3]; + + end + else + begin + deassign t1r; + deassign t2r; + deassign t3r; + deassign t4r; + end +end + + + + +// First rank of flops +// asynchronous reset operation +always @ (posedge CLKDIV or posedge SR) +begin + begin + if (SR & !SRTYPE[1]) + begin + t1r <= # ffd 1'b0; + t2r <= # ffd 1'b0; + t3r <= # ffd 1'b0; + t4r <= # ffd 1'b0; + end + else if (!SRTYPE[1]) + begin + t1r <= # ffd T1; + t2r <= # ffd T2; + t3r <= # ffd T3; + t4r <= # ffd T4; + end + end +end + +// synchronous reset operation +always @ (posedge CLKDIV) +begin + begin + if (SR & SRTYPE[1]) + begin + t1r <= # ffd 1'b0; + t2r <= # ffd 1'b0; + t3r <= # ffd 1'b0; + t4r <= # ffd 1'b0; + end + else if (SRTYPE[1]) + begin + t1r <= # ffd T1; + t2r <= # ffd T2; + t3r <= # ffd T3; + t4r <= # ffd T4; + end + end +end + + + + + +// Data Muxs for tristate otuput signals +always @ (sel or T1 or t1r or t3r) + begin + + casex (sel) + 5'b00000: data1 <= # mxd T1; + 5'b10000: data1 <= # mxd T1; + 5'bX0000: data1 <= # mxd T1; + 5'b00100: data1 <= # mxd T1; + 5'b10100: data1 <= # mxd T1; + 5'bX0100: data1 <= # mxd T1; + 5'b01001: data1 <= # mxd T1; + 5'b11001: data1 <= # mxd T1; + 5'b01010: data1 <= # mxd t3r; + 5'b11010: data1 <= # mxd t1r; +// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + + default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time); + endcase + end +// For data 2, width of 1 is inserted as acceptable for buf and sdr +// The capability exists in the device if the feature is added +always @ (sel or T2 or t2r or t4r) + begin + casex (sel) + 5'b00000: data2 <= # mxd T2; + 5'b00100: data2 <= # mxd T2; + 5'b10000: data2 <= # mxd T2; + 5'b10100: data2 <= # mxd T2; + 5'bX0000: data2 <= # mxd T2; + 5'bX0100: data2 <= # mxd T2; + 5'b00X00: data2 <= # mxd T2; + 5'b10X00: data2 <= # mxd T2; + 5'bX0X00: data2 <= # mxd T2; + 5'b01001: data2 <= # mxd T2; + 5'b11001: data2 <= # mxd T2; + 5'bX1001: data2 <= # mxd T2; + 5'b01010: data2 <= # mxd t4r; + 5'b11010: data2 <= # mxd t2r; +// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + + default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time); + endcase + end + + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module txbuffer_oserdese1_vlog +// +///////////////////////////////////////////////////////// +// +// FIFO and Control circuit for OSERDES + +module txbuffer_oserdese1_vlog (iodelay_state, qmux1, qmux2, tmux1, tmux2, + d1, d2, t1, t2, trif, + WC, ODV, extra, + clk, clkdiv, bufo, bufop, rst, + ODELAY_USED, DDR3_DATA, + DDR3_MODE); + +input d1, d2, t1, t2; + +input trif; + +input WC, ODV; + +input rst; + +input clk, clkdiv, bufo, bufop; + +input ODELAY_USED, DDR3_DATA; + +input DDR3_MODE; + +output iodelay_state, extra; + +output qmux1, qmux2, tmux1, tmux2; + +wire WC_DELAY; +assign WC_DELAY = 1'b0; + +wire rd_gap1; + +wire rst_bufo_p, rst_bufg_p; + + +wire rst_bufo_rc, rst_bufg_wc, rst_cntr, rst_bufop_rc; + +wire [1:0] qwc, qrd; + +wire bufo_out; +wire inv_qmux1, inv_qmux2, inv_tmux1, inv_tmux2; + + +fifo_tdpipe_oserdese1_vlog data1 (.muxout(inv_qmux1), .din(~d1), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog data2 (.muxout(inv_qmux2), .din(~d2), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog tris1 (.muxout(inv_tmux1), .din(~t1), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog tris2 (.muxout(inv_tmux2), .din(~t2), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +wire qmux1 = ~inv_qmux1; +wire qmux2 = ~inv_qmux2; +wire tmux1 = ~inv_tmux1; +wire tmux2 = ~inv_tmux2; + +fifo_reset_oserdese1_vlog rstckt (.rst_bufo_p(rst_bufo_p), .rst_bufo_rc(rst_bufo_rc), + .rst_bufg_p(rst_bufg_p), .rst_bufg_wc(rst_bufg_wc), + .rst_cntr(rst_cntr), + .bufg_clk(clk), .bufo_clk(bufo), .clkdiv(clkdiv), .rst(rst), + .divide_2(WC_DELAY), .bufop_clk(bufop), .rst_bufop_rc(rst_bufop_rc) + + ); + + + + +fifo_addr_oserdese1_vlog addcntr (.qwc(qwc), .qrd(qrd), .rd_gap1(rd_gap1), .rst_bufg_wc(rst_bufg_wc), .rst_bufo_rc(rst_bufo_rc), .bufg_clk(clk), .bufo_clk(bufo), + .data(DDR3_DATA), .extra(extra), .rst_bufop_rc(rst_bufop_rc), .bufop_clk(bufop) + + ); + + + +iodlyctrl_npre_oserdese1_vlog idlyctrl (.iodelay_state(iodelay_state), .bufo_out(bufo_out), .rst_cntr(rst_cntr), + .wc(WC), .trif(trif), + .rst(rst_bufg_p), .bufg_clk(clk), .bufo_clk(bufo), .bufg_clkdiv(clkdiv), + .ddr3_dimm(ODELAY_USED), .wl6(WC_DELAY) + ); + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_tdpipe_oserdese1_vlog +// +//////////////////////////////////////////////////////// + +// FIFO for write path + +module fifo_tdpipe_oserdese1_vlog (muxout, din, qwc, qrd, + rd_gap1, + bufg_clk, bufo_clk, rst_bufo_p, rst_bufg_p, + DDR3_DATA, extra, ODV, DDR3_MODE + + ); + + +input din; + +input [1:0] qwc, qrd; + +input rd_gap1; + +input rst_bufo_p, rst_bufg_p; + +input bufg_clk, bufo_clk; + +input DDR3_DATA, ODV; + +input extra; + +input DDR3_MODE; + +output muxout; + + +reg muxout; + +reg qout1, qout2; + +reg qout_int, qout_int2; + +reg [4:1] fifo; + +reg cin1; + +reg omux; + +wire [2:0] sel; + +reg pipe1, pipe2; + +wire selqoi, selqoi2; + +wire [2:0] selmuxout; + + + + + + +// 4 flops that make up the basic FIFO. They are all clocked +// off of fast BUFG. The first flop is the top flop in the chain. +// The CE input is used to mux the inputs. If the flop is selected, +// CE is high and it takes data from the output of the mux. If the +// flop is not selected, it retains its data. + +always @ (posedge bufg_clk or posedge rst_bufg_p) + begin + if (rst_bufg_p) + begin + fifo <= #10 4'b0000; + end + else if (!qwc[1] & !qwc[0]) + begin + fifo <= #10 {fifo[4:2],din}; + end + else if (!qwc[1] & qwc[0]) + begin + fifo <= #10 {fifo[4:3],din,fifo[1]}; + end + else if (qwc[1] & qwc[0]) + begin + fifo <= #10 {fifo[4],din,fifo[2:1]}; + end + else if (qwc[1] & !qwc[0]) + begin + fifo <= #10 {din,fifo[3:1]}; + end + end + + + +// Capture stage top +// This is the top flop of the "3 flops" for ODDR. This flop, along with the read +// counter will be clocked off of bufo. A 4:1 mux wil decode the outputs of the +// read counter and load the write data. A subsequent 2:1 mux will decode between +// the fifo and the legacy operation + + +// OMUX + +always @ (qrd or fifo) + begin + case (qrd) + 2'b00: omux <= #10 fifo[1]; + 2'b01: omux <= #10 fifo[2]; + 2'b10: omux <= #10 fifo[4]; + 2'b11: omux <= #10 fifo[3]; + default: omux <= #10 fifo[1]; + endcase + end + + +always @ (posedge bufo_clk or posedge rst_bufo_p) + begin + if (rst_bufo_p) + begin + qout_int <= #10 1'b0; + qout_int2 <= #10 1'b0; + end + else + begin + qout_int <= #10 omux; + qout_int2 <= #10 qout_int; + end + end + +assign #10 selqoi = ODV | rd_gap1; + + +always @ (selqoi or qout_int or omux) + begin + case(selqoi) + 1'b0: qout1 <= #10 omux; + 1'b1: qout1 <= #10 qout_int; + default: qout1 <= #10 omux; + endcase + end + +assign #10 selqoi2 = ODV & rd_gap1; + +always @ (selqoi2 or qout_int2 or qout_int) + begin + case(selqoi2) + 1'b0: qout2 <= #10 qout_int; + 1'b1: qout2 <= #10 qout_int2; + default qout2 <= #10 qout_int; + endcase + end + + +assign #14 selmuxout = {DDR3_MODE,DDR3_DATA,extra}; + + +always @ (selmuxout or din or omux or qout1 or qout2) + begin + case (selmuxout) + 3'b000: muxout = #1 din; + 3'b001: muxout = #1 din; + 3'b010: muxout = #1 din; + 3'b011: muxout = #1 din; + 3'b100: muxout = #1 omux; + 3'b101: muxout = #1 omux; + 3'b110: muxout = #1 qout1; + 3'b111: muxout = #1 qout2; + default: muxout = #10 din; + endcase + end + + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_reset_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// TX FIFO reset +// +// This design performs 2 functions. One function is to reset all the +// flops in the TX FIFO. The other function is to respond to the signal +// rst_cntr. This signal comes from iodlyctrl and will be used to initiate an +// orderly transition to switch the DQ/DQS I/O from and read to a write. +// This process is required only for DDR3 DIMM support because the IODELAY +// is used for both the inputs and the outputs. The signal from the +// squelch circuit is a present fabric output. An additional input +// indicating that a write command was issued will be +// required for all I/O to support this signal. +// +// This design uses an asynchronous reset to reset all flops. After the +// reset is disabled, a 0 is propagated through the pipe stages to terminate +// the reset. The first 2 flops run off of the clkdiv domain. Their output +// feeds a latch to cross between the clkdiv and bufg_clk domain. The pipe +// stage for the bufg_clk domain is 3 deep, where the last flop is the +// reset signal for the bufg_clk domain. The 2nd flop of the bufg_clk pipe +// is fed to 2 flops that are in the bufo_clk domain. The 2 flops are +// to resolve metastability between the 2 clock domains. +// +// The circuit to enable an orderly transition from read to write uses the +// PREAMBLE_SYNCHED output of a portion of the squelch circuit. This pulse +// will initiate the reset sequence and also generate an enable which will +// switch the IODELAY from an IDELAY to an ODELAY. Timing is as specified in +// the "State of the Union" presentation. +// +// + + +module fifo_reset_oserdese1_vlog (rst_bufo_p, rst_bufo_rc, + rst_bufg_p, rst_bufg_wc, + rst_cntr, + bufg_clk, bufo_clk, clkdiv, rst, + divide_2, bufop_clk, rst_bufop_rc + + ); + + +input rst_cntr; + +input rst; + +input bufg_clk, bufo_clk, clkdiv; + +input bufop_clk; + + +// Memory cell input to support divide by 1 operation +input divide_2; + + +output rst_bufo_p, rst_bufo_rc; +output rst_bufg_p, rst_bufg_wc; + +output rst_bufop_rc; + + +reg [1:0] clkdiv_pipe; + +reg bufg_pipe; + +reg rst_cntr_reg; + +reg [2:0] bufo_rst_p, bufo_rst_rc; + +reg [1:0] bufop_rst_rc; + +reg [1:0] bufg_rst_p, bufg_rst_wc; + +wire bufg_clkdiv_latch, ltint1, ltint2, ltint3; + +wire latch_in; + + + + + + + +// 2 stage pipe for clkdiv domain to allow user to properly +// time everything + + +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + rst_cntr_reg <= #10 1'b0; + end + else + begin + rst_cntr_reg <= #10 rst_cntr; + end + end + + +always @ (posedge clkdiv or posedge rst) + begin + if (rst) + begin + clkdiv_pipe <= #10 2'b11; + end + else + begin + clkdiv_pipe <= #10 {clkdiv_pipe[0],1'b0}; + end + end + +// Latch to compensate for clkdiv and bufg_clk clock skew +// Built of actual gates + +assign #1 latch_in = clkdiv_pipe[1]; + +assign #1 bufg_clkdiv_latch = !(ltint1 && ltint3); +assign #1 ltint1 = !(latch_in && bufg_clk); +assign #1 ltint2 = !(ltint1 && bufg_clk); +assign #1 ltint3 = !(bufg_clkdiv_latch && ltint2); + + + + + +// BUFG flop to register latch signal +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + bufg_pipe <= #10 1'b1; + end + else + begin + bufg_pipe <= #10 bufg_clkdiv_latch; + end + end + + + + +// BUFG clock domain resests + +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + bufg_rst_p <= #10 2'b11; + end + else + begin + bufg_rst_p <= #10 {bufg_rst_p[0],bufg_pipe}; + end + end + + +always @ (posedge bufg_clk or posedge rst_cntr or posedge rst) + begin + if (rst || rst_cntr) + begin + bufg_rst_wc <= #10 2'b11; + end + else + begin + bufg_rst_wc <= #10 {bufg_rst_wc[0],bufg_pipe}; + end + end + + + +// BUFO clock domain Resets +always @ (posedge bufo_clk or posedge rst) + begin + if (rst) + begin + bufo_rst_p <= #10 3'b111; + end + else + begin + bufo_rst_p <= #10 {bufo_rst_p[1:0],bufg_pipe}; + end + end + +always @ (posedge bufo_clk or posedge rst or posedge rst_cntr) + begin + if (rst || rst_cntr) + begin + bufo_rst_rc <= #10 3'b111; + end + else + begin + bufo_rst_rc <= #10 {bufo_rst_rc[1:0],bufg_pipe}; + end + end + + + +always @ (posedge bufop_clk or posedge rst or posedge rst_cntr) + begin + if (rst || rst_cntr) + begin + bufop_rst_rc <= #10 2'b11; + end + else + begin + bufop_rst_rc <= #10 {bufop_rst_rc[0],bufg_pipe}; + end + end + + +// final reset assignments +assign rst_bufo_rc = bufo_rst_rc[1]; + +assign rst_bufo_p = bufo_rst_p[1]; + +assign rst_bufop_rc = bufop_rst_rc[1]; + +assign rst_bufg_wc = bufg_rst_wc[1]; + +assign rst_bufg_p = bufg_rst_p[1]; + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_addr_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// Read and Write address generators for TX FIFO +// +// This circuit contains 2 greycode read and write address generators +// that will be used with the TX FIFO. Both counters generate a +// count sequence of 00 -> 01 -> 11 -> 10 -> 00. + + + +module fifo_addr_oserdese1_vlog (qwc, qrd, rd_gap1, rst_bufg_wc, rst_bufo_rc, bufg_clk, bufo_clk, + data, extra, rst_bufop_rc, bufop_clk + + ); + + +input bufg_clk, bufo_clk; + +input rst_bufo_rc, rst_bufg_wc; + +input rst_bufop_rc; + +input data; // mc to tell if I/O is DDR3 DQ or DQS + +input bufop_clk; + +output qwc, qrd; + +output rd_gap1, extra; + + + + +reg [1:0] qwc; + +reg [1:0] qrd; + + +reg stop_rd, rd_gap1, extra; + +reg rd_cor, rd_cor_cnt, rd_cor_cnt1; + + +wire qwc0_latch, qwc1_latch; + +wire li01, li02, li03; + +wire li11, li12, li13; + + +wire qwc0_latchn, qwc1_latchn; + +wire li01n, li02n, li03n; + +wire li11n, li12n, li13n; + + +reg stop_rdn, rd_cor_cntn, rd_cor_cnt1n, stop_rc; + + + + +reg [1:0] qwcd; + +reg [1:0] qrdd; + + +reg stop_rdd, rd_gap1d, extrad; + +reg rd_cord, rd_cor_cntd, rd_cor_cnt1d; + + +wire qwcd0_latch, qwcd1_latch; + +wire li01d, li02d, li03d; + +wire li11d, li12d, li13d; + + + +// Write counter +// The write counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The write counter is initialized +// to 11 and the read counter will be initialized to 00. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The write counter is clocked off of the bufg clock + +always @ (posedge bufg_clk or posedge rst_bufg_wc) + begin + if (rst_bufg_wc) + begin + qwc <= # 10 2'b11; + end + else if (qwc[1] ^ qwc[0]) + begin + qwc[1] <= # 10 ~qwc[1]; + qwc[0] <= # 10 qwc[0]; + end + else + begin + qwc[1] <= # 10 qwc[1]; + qwc[0] <= # 10 ~qwc[0]; + end + end + + + + + + +// Read counter +// The read counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized +// to 00 and the write counter will be initialized to 11. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The read counter is clocked off of the bufo clock + +always @ (posedge bufo_clk or posedge rst_bufo_rc) + + begin + if (rst_bufo_rc) + begin + qrd <= # 10 2'b00; + end + else if (stop_rd && !data) + begin + qrd <= #10 qrd; + end + else if (qrd[1] ^ qrd[0]) + begin + qrd[1] <= # 10 ~qrd[1]; + qrd[0] <= # 10 qrd[0]; + end + else + begin + qrd[1] <= # 10 qrd[1]; + qrd[0] <= # 10 ~qrd[0]; + end + end + +always @ (posedge bufo_clk or posedge rst_bufo_rc) + + begin + if (rst_bufo_rc) + begin + rd_gap1 <= # 10 1'b0; + end +// else if ((qwc1_latch && qwc0_latch) && (qrd[0] ^ qrd[1])) + else if ((qwc1_latch && qwc0_latch) && (qrd[0])) + begin + rd_gap1 <= # 10 1'b1; + end + else + begin + rd_gap1 <= # 10 rd_gap1; + end + end + + + + + +// Looking for 11 + +assign #1 qwc0_latch = !(li01 & li03); +assign #1 li01 = !(qwc[0] & bufo_clk); +assign #1 li02 = !(li01 & bufo_clk); +assign #1 li03 = !(qwc0_latch & li02); + + +assign #1 qwc1_latch = !(li11 & li13); +assign #1 li11 = !(qwc[1] & bufo_clk); +assign #1 li12 = !(li11 & bufo_clk); +assign #1 li13 = !(qwc1_latch & li12); + + +// The following counter is to match the control counter to see if the +// read counter did a hold after reset. This knowledge will enable the +// computation of the 'extra' output. This in turn can add the +// proper number of pipe stages to the output. The circuit must use +// the output of BUFO and not be modified by ODELAY. This is because +// the control pins PP clock was not modified by BUFO. If the +// control pins PP clock was modified by BUFO, the reset must be done +// with this in mind. + +// Read counter +// The read counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized +// to 00 and the write counter will be initialized to 11. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The read counter is clocked off of the bufo clock + +always @ (posedge bufop_clk or posedge rst_bufop_rc) + + begin + if (rst_bufop_rc) + begin + qrdd <= # 10 2'b00; + end + else if (qrdd[1] ^ qrdd[0]) + begin + qrdd[1] <= # 10 ~qrdd[1]; + qrdd[0] <= # 10 qrdd[0]; + end + else + begin + qrdd[1] <= # 10 qrdd[1]; + qrdd[0] <= # 10 ~qrdd[0]; + end + end + + + +// Looking for 11 + +assign #1 qwcd0_latch = !(li01d & li03d); +assign #1 li01d = !(qwc[0] & bufop_clk); +assign #1 li02d = !(li01d & bufop_clk); +assign #1 li03d = !(qwcd0_latch & li02d); + + +assign #1 qwcd1_latch = !(li11d & li13d); +assign #1 li11d = !(qwc[1] & bufop_clk); +assign #1 li12d = !(li11d & bufop_clk); +assign #1 li13d = !(qwcd1_latch & li12d); + + + +// Circuit to fix read address counters in non data pins +always @ (posedge bufop_clk or posedge rst_bufo_rc) + + begin + if (rst_bufop_rc) + begin + stop_rd <= # 10 1'b0; + rd_cor_cnt <= #10 1'b0; + rd_cor_cnt1 <= #10 1'b0; + end + else if (((qwcd1_latch && qwcd0_latch) && (qrdd[0] ^ qrdd[1]) && !rd_cor_cnt1)) + begin + stop_rd <= #10 1'b1; + rd_cor_cnt <= #10 1'b1; + rd_cor_cnt1 <= #10 rd_cor_cnt; + end + else + begin + stop_rd <= #10 1'b0; + rd_cor_cnt <= #10 1'b1; + rd_cor_cnt1 <= #10 rd_cor_cnt; + end + end + +// Circuit to inform data if control counters habe been fixed + +always @ (posedge bufop_clk or posedge rst_bufop_rc) + begin + if (rst_bufop_rc) + begin + extra <= #10 1'b0; + end + else if (stop_rd) + begin + extra <= #10 1'b1; + end + end + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module iodlyctrl_npre_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// Circuit to automatically switch IODELAY from IDELAY to ODELAY using knowledge +// of write command. This circuit forces the user to wait 3 extra CLK/CLK# cycles +// when performing a read to write turnaround. The JEDEC DDR3 spec states that +// the turnaround can be done in 2 clock cycles. This circuit requires 5 clock +// cycles. +// This circuit is only used for a DDR3 appplication that uses DIMMs + + + +module iodlyctrl_npre_oserdese1_vlog (iodelay_state, bufo_out, rst_cntr, + wc, trif, + rst, bufg_clk, bufo_clk, bufg_clkdiv, + ddr3_dimm, wl6 + ); + + +input wc; + +input trif; + +input rst; + +input bufo_clk, bufg_clk, bufg_clkdiv; + +input ddr3_dimm, wl6; + +output iodelay_state, rst_cntr; + +output bufo_out; + + +reg qw0cd, qw1cd; + +reg turn, turn_p1; + +reg rst_cntr; + +reg w_to_w; + +reg [2:0] wtw_cntr; + +reg cmd0, cmd0_n6, cmd0_6, cmd1; + + + + +wire wr_cmd0; + +wire lt0int1, lt0int2, lt0int3; + +wire lt1int1, lt1int2, lt1int3; + +wire latch_in; + +reg qwcd; + + + + + +assign bufo_out = bufo_clk; + + +// create turn signal for IODELAY +assign iodelay_state = (trif && ~w_to_w) & ((~turn && ~turn_p1) || ~ddr3_dimm); + + + +// Registers to detect write command + +// Registers using bufg clkdiv +always @ (posedge bufg_clkdiv) +begin + if (rst) + begin + qwcd <= #10 0; + end + else + begin + qwcd <= #10 wc; + end +end + + + +// Latch to allow skew between CLK and CLKDIV from BUFGs +assign #1 wr_cmd0 = !(lt0int1 && lt0int3); +assign #1 lt0int1 = !(qwcd && bufg_clk); +assign #1 lt0int2 = !(lt0int1 && bufg_clk); +assign #1 lt0int3 = !(wr_cmd0 && lt0int2); + +always @ (posedge bufg_clk) + begin + if (rst) + begin + cmd0_n6 <= #10 1'b0; + cmd0_6 <= #10 1'b0; + end + else + begin + cmd0_n6 <= #10 wr_cmd0; + cmd0_6 <= #10 cmd0_n6; + end + end + + + +// mux to add extra pipe stage for WL = 6 +always @ (cmd0_n6 or wl6 or cmd0_6) + begin + case (wl6) + 1'b0: cmd0 <= #10 cmd0_n6; + 1'b1: cmd0 <= #10 cmd0_6; + default: cmd0 <= #10 cmd0_n6; + endcase + end + + +// Turn IODELAY and reset FIFO read/write counters +//always @ (posedge bufg_clk) +// begin +// if (rst) +// +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// else if (w_to_w) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b0; +// end +// else if (cmd0 && !turn) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b1; +// end +// else if (~trif) +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// else if (turn) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b0; +// end +// else +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// end + + + +always @ (posedge bufg_clk) +begin + begin + if (rst) + begin + turn <= #10 1'b0; + end + else + begin + turn <= #10 (w_to_w || (cmd0 && ~turn) || + (~wtw_cntr[2] && turn)); + end + + end + + begin + if (rst) + begin + rst_cntr <= #10 1'b0; + end + else + begin + rst_cntr <= #10 (~w_to_w && (cmd0 && ~turn)); + end + end +end + + + + +always @ (posedge bufg_clk) + begin + if (rst) + begin + turn_p1 <= #10 1'b0; + end + else + begin + turn_p1 <= #10 turn; + end + end + + + + +// Detect multiple write commands and don"t turn IODELAY +//always @ (posedge bufg_clk) +// begin +// if (rst) +// begin +// w_to_w <= #10 1'b0; +// wtw_cntr <= #10 3'b000; +// end +// else if (cmd0 && turn_p1) +// begin +// w_to_w <= #10 1'b1; +// wtw_cntr <= #10 3'b000; +// end +// else if (wtw_cntr == 3'b101) +// begin +// w_to_w <= #10 1'b0; +// wtw_cntr <= #10 3'b000; +// end +// else if (w_to_w) +// begin +// w_to_w <= #10 1'b1; +// wtw_cntr <= #10 wtw_cntr + 1; +// end +// end + + +always @ (posedge bufg_clk) +begin + begin + if (rst) + begin + w_to_w <= #10 1'b0; + end + else + begin + w_to_w <= #10 ((cmd0 && turn_p1) || + (w_to_w && (~wtw_cntr[2] || ~wtw_cntr[1]))); + end + end +end + + +always @ (posedge bufg_clk) + + begin + if (!(w_to_w || turn) || (cmd0 && turn_p1)) + begin + wtw_cntr <= #10 3'b000; + end + else if (w_to_w || turn_p1) + begin + wtw_cntr <= #10 wtw_cntr + 1; + end + end + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// MODULE dout_oserdese1_vlog +// +// This model ONLY works for SERDES operation!! +// Does not include tristate circuit +// +///////////////////////////////////////////////////////// +// +// Inputs: +// data1: Data from FIFO +// data2: Data input FIFO +// CLK: High speed clock from DCM +// BUFO: Clock from performance path +// OCE: Clock enable for output data flops +// SR: Set/Reset control. For the last 3 flops in OQ +// (d1rnk2, d2rnk2 and d2nrnk2) this function is +// controlled bythe attributes SRVAL_OQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// +// +// +// Outputs: +// OQ: Data output +// +// +// +// Programmable Points +// DATA_RATE_OQ: Rate control for data output, 1-bit +// sdr (1), ddr (0) +// INIT_OQ: Init OQ output "flop" +// SRVAL_OQ: This bit to controls value of SR input. +// Only the last 3 flops (d1rnk2, d2rnk2 and d2nrnk2) +// are affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only respond to +// this pin as a reset. Their function cannot be +// changed. SR is '1' for SET and '0' for RESET. +// +// +// +// Programmable points for Test model +// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset +// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2, +// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter +// DDR_CLK_EDGE: Controls use of 2 or 3 flops for single case. Default to 1 for +// SERDES operation +// +// +/////////////////////////////////////////////////////////////////////////////// +// + +module dout_oserdese1_vlog (data1, data2, + CLK, BUFO, SR, OCE, + OQ, d2rnk2, + DATA_RATE_OQ, + INIT_OQ, SRVAL_OQ, + DDR3_MODE); + +input data1, data2; + +input CLK, SR, OCE; + +input BUFO; + +input INIT_OQ, SRVAL_OQ; + +input DDR3_MODE; + +output OQ; + +output d2rnk2; + + +// Programmable Points + +input DATA_RATE_OQ; + +wire DDR_CLK_EDGE; +wire [3:0] SRTYPE; +assign DDR_CLK_EDGE = 1'b1; +assign SRTYPE = 4'b1111; +reg d1rnk2, d2rnk2, d2nrnk2; + +reg OQ; + +reg ddr_data, odata_edge, sdata_edge; + +reg c23, c45, c67; + +wire C; + +wire C2p, C3; + +wire [3:0] seloq; + +wire oqsr, oqrev; + +assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE); + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev}; + +assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ; + +assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 1; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 1; // 60 ps mux delay + +parameter MXR1 = 1; + +//////////////////////////////////////////// +// Initialization of flops with GSR for test model +/////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign OQ = INIT_OQ; + assign d1rnk2 = INIT_OQ; + assign d2rnk2 = INIT_OQ; + assign d2nrnk2 = INIT_OQ; + end + else + begin + deassign OQ; + deassign d1rnk2; + deassign d2rnk2; + deassign d2nrnk2; + end +end + +///////////////////////////////////////// + + + + + + +///////////////////////////////////////// +// 3 flops to create DDR operations of 4 latches +//////////////////////////////////////// + +// Representation of top latch +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d1rnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d1rnk2 <= # FFD data1; + end + end +end + +// synchronous operation +always @ (posedge C) +begin + begin + + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d1rnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d1rnk2 <= # FFD data1; + end + end +end + + + + +// Representation of 2nd latch +// asynchronous operation +always @ (posedge C2p or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d2rnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d2rnk2 <= # FFD data2; + end + end +end + +// synchronous operation +always @ (posedge C2p) +begin + begin + + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d2rnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d2rnk2 <= # FFD data2; + end + end +end + + + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation +always @ (posedge C3 or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d2nrnk2 <= # FFD d2rnk2; + end + end +end + +// synchronous operation +always @ (posedge C3) +begin + + begin + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d2nrnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d2nrnk2 <= # FFD d2rnk2; + end + end +end + + +// Logic to generate same edge data from d1rnk2 and d2nrnk2; +always @ (C or C3 or d1rnk2 or d2nrnk2) + begin + sdata_edge <= # MXD (d1rnk2 & C) | (d2nrnk2 & C3); + end + +// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2 +always @ (C or d1rnk2 or d2rnk2) + begin + case (C) + 1'b0: odata_edge <= # MXD d2rnk2; + 1'b1: odata_edge <= # MXD d1rnk2; + default: odata_edge <= # MXD d1rnk2; + endcase + end + +// Logic to same edge and opposite data into just ddr data +always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE) + begin + ddr_data <= # MXD (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE); + end + + +// Output mux to generate OQ +always @ (seloq or d1rnk2 or ddr_data or OQ) + begin + casex (seloq) + 4'bXX01: OQ <= # MXD 1'b1; + 4'bXX10: OQ <= # MXD 1'b0; + 4'bXX11: OQ <= # MXD 1'b0; + 4'bX000: OQ <= # MXD ddr_data; + 4'bX100: OQ <= # MXD d1rnk2; + default: OQ <= # MXD ddr_data; + endcase + end + + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module tout_oserdese1_vlog +// +// Tristate Output cell for Mt Blanc +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// +// data1, data2: tristate inputs +// TCE: Tristate clock enable +// SR: Set/Reset control. For the last 3 flops in TQ +// (qt1, qt2 and qt2n) this function is +// controlled bythe attributes SRVAL_TQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// CLK: High speed clocks +// C2 drives 2nd latch and C3 (inverse of C2) drives +// 3rd latch in output section +// BUFO: Performance path clock +// +// +// +// +// Outputs: +// +// TQ: Output of tristate mux +// +// +// Programmable Options: +// +// DATA_RATE_TQ: 2-bit field for types of operaiton +// 0 (buf from T1), 1 (registered output from T1), 2 (ddr) +// TRISTATE_WIDTH: 2-bit field for input width +// 0 (width 1), 1 (width 2), 2 (width 4) +// INIT_TQ: Init TQ output (0,1) +// SRVAL_TQ: This bit to controls value of SR input. +// Only the last 3 flops (qt1, qt2 and qt2n) are +// affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only +// respond to this pin as a reset. Their function +// cannot be changed. SR is 'O' for SET and '1' for RESET. +// +// +// Programmable Test Options: +// SRTYPE: Control S and R as asynchronous (0) or synchronous (1) +// 2-bit value. 1st bit (msb) controls the 4 input flops +// and the 2nd bit (lsb) controls the "3 legacy flops" +// DDR_CLK_EDGE: Same or opposite edge operation +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module tout_oserdese1_vlog (data1, data2, + CLK, BUFO, SR, TCE, + DATA_RATE_TQ, TRISTATE_WIDTH, + INIT_TQ, SRVAL_TQ, + TQ, DDR3_MODE); + +input data1, data2; + +input CLK, BUFO, SR, TCE; + +input [1:0] DATA_RATE_TQ, TRISTATE_WIDTH; + +input INIT_TQ, SRVAL_TQ; + +input DDR3_MODE; + +output TQ; + +wire DDR_CLK_EDGE; +wire [1:0] SRTYPE; +assign SRTYPE = 2'b11; +assign DDR_CLK_EDGE = 1'b1; + +reg TQ; + +reg t1r, t2r, t3r, t4r; + +reg qt1, qt2, qt2n; + +reg sdata_edge, odata_edge, ddr_data; + +wire C; + +wire C2p, C3; + +wire load; + +wire [5:0] tqsel; + +wire tqsr, tqrev; + +wire [4:0] sel; + +assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE); + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign tqsr = (!SRTYPE[0] & SR & !SRVAL_TQ) | (!SRTYPE[0] & SRVAL_TQ); + +assign tqrev = (!SRTYPE[0] & SR & SRVAL_TQ) | (!SRTYPE[0] & !SRVAL_TQ); + +assign tqsel = {TCE,DATA_RATE_TQ,TRISTATE_WIDTH,tqsr}; + + + + + +////////////////////////////////////////////////// + + +// Parameters for gate delays +parameter ffd = 1; +parameter mxd = 1; + + +///////////////////////////// +// Initialization of Flops +//////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign TQ = INIT_TQ; + assign qt1 = INIT_TQ; + assign qt2 = INIT_TQ; + assign qt2n = INIT_TQ; + end + else + begin + deassign TQ; + deassign qt1; + deassign qt2; + deassign qt2n; + end +end + + + +///////////////////////////////////////// +// 3 flops to create DDR operations of 4 latches +//////////////////////////////////////// + +// Representation of top latch +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt1 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt1 <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt1 <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt1 <= # ffd data1; + end + end +end + +// synchronous operation +always @ (posedge C) +begin + begin + + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt1 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt1 <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt1 <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt1 <= # ffd data1; + end + end +end + + + + +// Representation of 2nd latch +// asynchronous operation +always @ (posedge C2p or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt2 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt2 <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt2 <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt2 <= # ffd data2; + end + end +end + +// synchronous operation +always @ (posedge C2p) +begin + begin + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt2 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt2 <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt2 <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt2 <= # ffd data2; + end + end +end + + + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation +always @ (posedge C3 or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt2n <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt2n <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt2n <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt2n <= # ffd qt2; + end + end +end + +// synchronous operation +always @ (posedge C3) +begin + + begin + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt2n <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt2n <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt2n <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt2n <= # ffd qt2; + end + end +end + + +// Logic to generate same edge data from qt1, qt3; +always @ (C or C3 or qt1 or qt2n) + begin + sdata_edge <= # mxd (qt1 & C) | (qt2n & C3); + end + +// Mux to create opposite edge DDR function +always @ (C or qt1 or qt2) + begin + case (C) + 1'b0: odata_edge <= # mxd qt2; + 1'b1: odata_edge <= # mxd qt1; + default: odata_edge <= 1'b0; + endcase + end + +// Logic to same edge and opposite data into just ddr data +always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE) + begin + ddr_data <= # mxd (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE); + end + +// Output mux to generate TQ +// Note that the TQ mux can also support T2 combinatorial or +// registered outputs. +always @ (tqsel or data1 or ddr_data or qt1 or TQ) + begin + casex (tqsel) + 6'bX01XX1: TQ <= # mxd 1'b0; + 6'bX10XX1: TQ <= # mxd 1'b0; + 6'bX01XX1: TQ <= # mxd 1'b0; + 6'bX10XX1: TQ <= # mxd 1'b0; + 6'bX0000X: TQ <= # mxd data1; + // 6'b001000: TQ <= # mxd TQ; + // 6'b010010: TQ <= # mxd TQ; + // 6'b010100: TQ <= # mxd TQ; + 6'bX01000: TQ <= # mxd qt1; + 6'bX10010: TQ <= # mxd ddr_data; + 6'bX10100: TQ <= # mxd ddr_data; + default: TQ <= # mxd ddr_data; + endcase + end + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OSERDESE2.v b/verilog/src/unisims/OSERDESE2.v new file mode 100644 index 0000000..94441e6 --- /dev/null +++ b/verilog/src/unisims/OSERDESE2.v @@ -0,0 +1,524 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Output Serializer Virtex7 +// /___/ /\ Filename : OSERDESE2.v +// \ \ / \ Timestamp : Fri Jan 29 14:59:32 PST 2010 +// \___\/\___\ +// +// Revision: +// 01/29/10 - Initial version. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module OSERDESE2 ( + OFB, + OQ, + SHIFTOUT1, + SHIFTOUT2, + TBYTEOUT, + TFB, + TQ, + + CLK, + CLKDIV, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + OCE, + RST, + SHIFTIN1, + SHIFTIN2, + T1, + T2, + T3, + T4, + TBYTEIN, + TCE +); + + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter [0:0] IS_D3_INVERTED = 1'b0; + parameter [0:0] IS_D4_INVERTED = 1'b0; + parameter [0:0] IS_D5_INVERTED = 1'b0; + parameter [0:0] IS_D6_INVERTED = 1'b0; + parameter [0:0] IS_D7_INVERTED = 1'b0; + parameter [0:0] IS_D8_INVERTED = 1'b0; + parameter [0:0] IS_T1_INVERTED = 1'b0; + parameter [0:0] IS_T2_INVERTED = 1'b0; + parameter [0:0] IS_T3_INVERTED = 1'b0; + parameter [0:0] IS_T4_INVERTED = 1'b0; + + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter TBYTE_CTL = "FALSE"; + parameter TBYTE_SRC = "FALSE"; + parameter integer TRISTATE_WIDTH = 4; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TBYTEOUT; + output TFB; + output TQ; + + input CLK; + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input T1; + input T2; + input T3; + input T4; + input TBYTEIN; + input TCE; + + reg DATA_RATE_OQ_BINARY; + reg DATA_WIDTH_BINARY; + reg LOC_BINARY; + reg [0:0] INIT_OQ_BINARY; + reg [0:0] INIT_TQ_BINARY; + reg [0:0] SERDES_MODE_BINARY; + reg [0:0] SRVAL_OQ_BINARY; + reg [0:0] SRVAL_TQ_BINARY; + reg [0:0] TBYTE_CTL_BINARY; + reg [0:0] TBYTE_SRC_BINARY; + reg [0:0] TRISTATE_WIDTH_BINARY; + reg [5:0] DATA_RATE_TQ_BINARY; + + tri0 GSR = glbl.GSR; + reg notifier; + + wire OFB_OUT; + wire OQ_OUT; + wire SHIFTOUT1_OUT; + wire SHIFTOUT2_OUT; + wire TBYTEOUT_OUT; + wire TFB_OUT; + wire TQ_OUT; + + wire CLKDIV_IN; + wire CLK_IN; + wire D1_IN; + wire D2_IN; + wire D3_IN; + wire D4_IN; + wire D5_IN; + wire D6_IN; + wire D7_IN; + wire D8_IN; + wire OCE_IN; + wire RST_IN; + wire SHIFTIN1_IN; + wire SHIFTIN2_IN; + wire T1_IN; + wire T2_IN; + wire T3_IN; + wire T4_IN; + wire TBYTEIN_IN; + wire TCE_IN; + + wire CLKDIV_INDELAY; + wire CLK_INDELAY; + wire D1_INDELAY; + wire D2_INDELAY; + wire D3_INDELAY; + wire D4_INDELAY; + wire D5_INDELAY; + wire D6_INDELAY; + wire D7_INDELAY; + wire D8_INDELAY; + wire OCE_INDELAY; + wire RST_INDELAY; + wire SHIFTIN1_INDELAY; + wire SHIFTIN2_INDELAY; + wire T1_INDELAY; + wire T2_INDELAY; + wire T3_INDELAY; + wire T4_INDELAY; + wire TBYTEIN_INDELAY; + wire TCE_INDELAY; + + wire delay_OFB,OFB_out; + wire delay_OQ,OQ_out; + wire delay_SHIFTOUT1,SHIFTOUT1_out; + wire delay_SHIFTOUT2,SHIFTOUT2_out; + wire delay_TBYTEOUT,TBYTEOUT_out; + wire delay_TFB,TFB_out; + wire delay_TQ,TQ_out; + + wire delay_CLK,CLK_in; + wire delay_CLKDIV,CLKDIV_in; + wire delay_D1,D1_in; + wire delay_D2,D2_in; + wire delay_D3,D3_in; + wire delay_D4,D4_in; + wire delay_D5,D5_in; + wire delay_D6,D6_in; + wire delay_D7,D7_in; + wire delay_D8,D8_in; + wire delay_OCE,OCE_in; + wire delay_RST,RST_in; + wire delay_SHIFTIN1,SHIFTIN1_in; + wire delay_SHIFTIN2,SHIFTIN2_in; + wire delay_T1,T1_in; + wire delay_T2,T2_in; + wire delay_T3,T3_in; + wire delay_T4,T4_in; + wire delay_TBYTEIN,TBYTEIN_in; + wire delay_TCE,TCE_in; + + + assign #(out_delay) OFB = delay_OFB; + assign #(out_delay) OQ = delay_OQ; + assign #(out_delay) SHIFTOUT1 = delay_SHIFTOUT1; + assign #(out_delay) SHIFTOUT2 = delay_SHIFTOUT2; + assign #(out_delay) TBYTEOUT = delay_TBYTEOUT; + assign #(out_delay) TFB = delay_TFB; + assign #(out_delay) TQ = delay_TQ; + + assign delay_OFB = OFB_out; + assign delay_OQ = OQ_out; + assign delay_SHIFTOUT1 = SHIFTOUT1_out; + assign delay_SHIFTOUT2 = SHIFTOUT2_out; + assign delay_TBYTEOUT = TBYTEOUT_out; + assign delay_TFB = TFB_out; + assign delay_TQ = TQ_out; + + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_CLKDIV = CLKDIV; + assign #(INCLK_DELAY) delay_CLK = CLK; + + assign #(in_delay) delay_D1 = D1; + assign #(in_delay) delay_D2 = D2; + assign #(in_delay) delay_D3 = D3; + assign #(in_delay) delay_D4 = D4; + assign #(in_delay) delay_D5 = D5; + assign #(in_delay) delay_D6 = D6; + assign #(in_delay) delay_D7 = D7; + assign #(in_delay) delay_D8 = D8; + assign #(in_delay) delay_OCE = OCE; + assign #(in_delay) delay_RST = RST; + assign #(in_delay) delay_SHIFTIN1 = SHIFTIN1; + assign #(in_delay) delay_SHIFTIN2 = SHIFTIN2; + assign #(in_delay) delay_T1 = T1; + assign #(in_delay) delay_T2 = T2; + assign #(in_delay) delay_T3 = T3; + assign #(in_delay) delay_T4 = T4; + assign #(in_delay) delay_TBYTEIN = TBYTEIN; + assign #(in_delay) delay_TCE = TCE; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim +// assign delay_RST = RST; + assign delay_SHIFTIN1 = SHIFTIN1; + assign delay_SHIFTIN2 = SHIFTIN2; + assign delay_TBYTEIN = TBYTEIN; +`endif + assign CLKDIV_in = IS_CLKDIV_INVERTED ^ delay_CLKDIV; + assign CLK_in = IS_CLK_INVERTED ^ delay_CLK; + + assign D1_in = IS_D1_INVERTED ^ delay_D1; + assign D2_in = IS_D2_INVERTED ^ delay_D2; + assign D3_in = IS_D3_INVERTED ^ delay_D3; + assign D4_in = IS_D4_INVERTED ^ delay_D4; + assign D5_in = IS_D5_INVERTED ^ delay_D5; + assign D6_in = IS_D6_INVERTED ^ delay_D6; + assign D7_in = IS_D7_INVERTED ^ delay_D7; + assign D8_in = IS_D8_INVERTED ^ delay_D8; + assign OCE_in = delay_OCE; + assign RST_in = delay_RST; + assign SHIFTIN1_in = delay_SHIFTIN1; + assign SHIFTIN2_in = delay_SHIFTIN2; + assign T1_in = IS_T1_INVERTED ^ delay_T1; + assign T2_in = IS_T2_INVERTED ^ delay_T2; + assign T3_in = IS_T3_INVERTED ^ delay_T3; + assign T4_in = IS_T4_INVERTED ^ delay_T4; + assign TBYTEIN_in = delay_TBYTEIN; + assign TCE_in = delay_TCE; + + assign SHIFTIN1_in = delay_SHIFTIN1; + assign SHIFTIN2_in = delay_SHIFTIN2; + assign TBYTEIN_in = delay_TBYTEIN; + + + + initial begin +//------------------------------------------------- +//----- DATA_RATE_OQ check +//------------------------------------------------- + case (DATA_RATE_OQ) + "SDR", "DDR" :; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + #1 $finish; + end + endcase // case(DATA_RATE_OQ) + +//------------------------------------------------- +//----- DATA_RATE_TQ check +//------------------------------------------------- + case (DATA_RATE_TQ) + "BUF", "DDR", "SDR" :; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are BUF, SDR, or DDR", DATA_RATE_TQ); + #1 $finish; + end + endcase // case(DATA_RATE_TQ) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10, 14 : ; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE2 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, 10 or 14", DATA_WIDTH); + #1 $finish; + end + endcase // case(DATA_WIDTH) + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) // {mem_slave} + + "MASTER", "SLAVE" :; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE2 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + #1 $finish; + end + + endcase // case(SERDES_MODE) + +//------------------------------------------------- +//----- TRISTATE_WIDTH check +//------------------------------------------------- + case (TRISTATE_WIDTH) // {mem_twidth4} + + 1,2,4 : ; + default : begin + $display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE2 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH); + #1 $finish; + end + + endcase // case(TRISTATE_WIDTH) + +//------------------------------------------------- +//----- DATA_RATE_OQ/DATA_WIDTH Combination +//------------------------------------------------- + case (DATA_RATE_OQ) + "SDR" , "DDR" : ; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + #1 $finish; + end + endcase // case(DATA_RATE_OQ/DATA_WIDTH) + +//------------------------------------------------- + end // initial begin + + + + B_OSERDESE2 #( + .DATA_RATE_OQ (DATA_RATE_OQ), + .DATA_RATE_TQ (DATA_RATE_TQ), + .DATA_WIDTH (DATA_WIDTH), + .INIT_OQ (INIT_OQ), + .INIT_TQ (INIT_TQ), + .SERDES_MODE (SERDES_MODE), + .SRVAL_OQ (SRVAL_OQ), + .SRVAL_TQ (SRVAL_TQ), + .TBYTE_CTL (TBYTE_CTL), + .TBYTE_SRC (TBYTE_SRC), + .TRISTATE_WIDTH (TRISTATE_WIDTH)) + + B_OSERDESE2_INST ( + .OFB (OFB_out), + .OQ (OQ_out), + .SHIFTOUT1 (SHIFTOUT1_out), + .SHIFTOUT2 (SHIFTOUT2_out), + .TBYTEOUT (TBYTEOUT_out), + .TFB (TFB_out), + .TQ (TQ_out), + .CLK (CLK_in), + .CLKDIV (CLKDIV_in), + .D1 (D1_in), + .D2 (D2_in), + .D3 (D3_in), + .D4 (D4_in), + .D5 (D5_in), + .D6 (D6_in), + .D7 (D7_in), + .D8 (D8_in), + .OCE (OCE_in), + .RST (RST_in), + .SHIFTIN1 (SHIFTIN1_in), + .SHIFTIN2 (SHIFTIN2_in), + .T1 (T1_in), + .T2 (T2_in), + .T3 (T3_in), + .T4 (T4_in), + .TBYTEIN (TBYTEIN_in), + .TCE (TCE_in), + .GSR (GSR) + ); + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + wire clkdiv_en_p; + wire clkdiv_en_n; + assign clk_en_n = IS_CLK_INVERTED; + assign clk_en_p = ~IS_CLK_INVERTED; + assign clkdiv_en_n = IS_CLKDIV_INVERTED; + assign clkdiv_en_p = ~IS_CLKDIV_INVERTED; + +`endif + + specify +`ifdef XIL_TIMING // Simprim + $period (negedge CLK, 0:0:0, notifier); + $period (negedge CLKDIV, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OCE); + $setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_T1); + $setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_TCE); + $setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_OCE); + $setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_T1); + $setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, delay_CLK, delay_TCE); + $setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D1); + $setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D2); + $setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D3); + $setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D4); + $setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D5); + $setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D6); + $setuphold (posedge CLKDIV, negedge D7, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D7); + $setuphold (posedge CLKDIV, negedge D8, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D8); + $setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T1); + $setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T2); + $setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T3); + $setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T4); + $setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D1); + $setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D2); + $setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D3); + $setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D4); + $setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D5); + $setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D6); + $setuphold (posedge CLKDIV, posedge D7, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D7); + $setuphold (posedge CLKDIV, posedge D8, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_D8); + $setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T1); + $setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T2); + $setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T3); + $setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_T4); + + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, delay_CLKDIV, delay_RST); + + $setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OCE); + $setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_T1); + $setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_TCE); + $setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_OCE); + $setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_T1); + $setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, delay_CLK, delay_TCE); + $setuphold (negedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D1); + $setuphold (negedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D2); + $setuphold (negedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D3); + $setuphold (negedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D4); + $setuphold (negedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D5); + $setuphold (negedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D6); + $setuphold (negedge CLKDIV, negedge D7, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D7); + $setuphold (negedge CLKDIV, negedge D8, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D8); + $setuphold (negedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T1); + $setuphold (negedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T2); + $setuphold (negedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T3); + $setuphold (negedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T4); + $setuphold (negedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D1); + $setuphold (negedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D2); + $setuphold (negedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D3); + $setuphold (negedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D4); + $setuphold (negedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D5); + $setuphold (negedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D6); + $setuphold (negedge CLKDIV, posedge D7, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D7); + $setuphold (negedge CLKDIV, posedge D8, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_D8); + $setuphold (negedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T1); + $setuphold (negedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T2); + $setuphold (negedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T3); + $setuphold (negedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_T4); + + $setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST); + $setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, delay_CLKDIV, delay_RST); + + +`endif + ( CLK => OFB) = (100:100:100, 100:100:100); + ( CLK => OQ) = (100:100:100, 100:100:100); + ( CLK => TFB) = (100:100:100, 100:100:100); + ( CLK => TQ) = (100:100:100, 100:100:100); + ( T1 => TBYTEOUT) = (100:100:100, 100:100:100); + ( T1 => TQ) = (100:100:100, 100:100:100); + ( TBYTEIN => TQ) = (100:100:100, 100:100:100); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OSERDESE3.v b/verilog/src/unisims/OSERDESE3.v new file mode 100644 index 0000000..fd9dfeb --- /dev/null +++ b/verilog/src/unisims/OSERDESE3.v @@ -0,0 +1,318 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / OSERDESE3 +// /___/ /\ Filename : OSERDESE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OSERDESE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DATA_WIDTH = 8, + parameter [0:0] INIT = 1'b0, + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter ODDR_MODE = "FALSE", + parameter OSERDES_D_BYPASS = "FALSE", + parameter OSERDES_T_BYPASS = "FALSE", + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0 +)( + output OQ, + output T_OUT, + + input CLK, + input CLKDIV, + input [7:0] D, + input RST, + input T +); + +// define constants + localparam MODULE_NAME = "OSERDESE3"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "OSERDESE3_dr.v" +`else + localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH; + localparam [0:0] INIT_REG = INIT; + localparam [0:0] IS_CLKDIV_INVERTED_REG = IS_CLKDIV_INVERTED; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [40:1] ODDR_MODE_REG = ODDR_MODE; + localparam [40:1] OSERDES_D_BYPASS_REG = OSERDES_D_BYPASS; + localparam [40:1] OSERDES_T_BYPASS_REG = OSERDES_T_BYPASS; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; +`endif + + localparam [40:1] OSERDES_ENABLE_REG = "TRUE"; + localparam [1:0] SPARE_REG = 2'b00; + localparam [64:1] TBYTE_CTL_REG = "T"; + + wire IS_CLKDIV_INVERTED_BIN; + wire IS_CLK_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire OQ_out; + wire T_OUT_out; + + wire OQ_delay; + wire T_OUT_delay; + + wire CLKDIV_in; + wire CLK_in; + wire OFD_CE_in; + wire RST_in; + wire T_in; + wire [7:0] D_in; + + wire CLKDIV_delay; + wire CLK_delay; + wire RST_delay; + wire T_delay; + wire [7:0] D_delay; + wire init_param; + + assign #(out_delay) OQ = OQ_delay; + assign #(out_delay) T_OUT = T_OUT_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLKDIV_delay = CLKDIV; + assign #(inclk_delay) CLK_delay = CLK; + assign #(in_delay) D_delay = D; + assign #(in_delay) RST_delay = RST; +`endif + +// inputs with no timing checks + + assign #(in_delay) T_delay = T; + + assign OQ_delay = OQ_out; + assign T_OUT_delay = T_OUT_out; + + assign CLKDIV_in = CLKDIV_delay ^ IS_CLKDIV_INVERTED_BIN; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign D_in = D_delay; + assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN; + assign T_in = (T !== 1'bz) && T_delay; // rv 0 + + assign IS_CLKDIV_INVERTED_BIN = IS_CLKDIV_INVERTED_REG; + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + assign init_param = (INIT == 1'b0) ? 1'b0 : 1'b1; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DATA_WIDTH_REG != 8) && + (DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ODDR_MODE_REG != "FALSE") && + (ODDR_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] ODDR_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ODDR_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OSERDES_D_BYPASS_REG != "FALSE") && + (OSERDES_D_BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] OSERDES_D_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OSERDES_D_BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OSERDES_T_BYPASS_REG != "FALSE") && + (OSERDES_T_BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] OSERDES_T_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OSERDES_T_BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-110] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-111] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign OFD_CE_in = 1'b0; // tie off + +generate +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + + SIP_OSERDESE3_D1 SIP_OSERDESE3_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .INIT (INIT_REG), + .ODDR_MODE (ODDR_MODE_REG), + .OSERDES_D_BYPASS (OSERDES_D_BYPASS_REG), + .OSERDES_ENABLE (OSERDES_ENABLE_REG), + .OSERDES_T_BYPASS (OSERDES_T_BYPASS_REG), + .SPARE (SPARE_REG), + .TBYTE_CTL (TBYTE_CTL_REG), + .OQ (OQ_out), + .T_OUT (T_OUT_out), + .CLK (CLK_in), + .CLKDIV (CLKDIV_in), + .D (D_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .T (T_in), + .GSR (glblGSR) + ); +end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + SIP_OSERDESE3_K2 SIP_OSERDESE3_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .INIT (INIT_REG), + .ODDR_MODE (ODDR_MODE_REG), + .OSERDES_D_BYPASS (OSERDES_D_BYPASS_REG), + .OSERDES_T_BYPASS (OSERDES_T_BYPASS_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .TBYTE_CTL (TBYTE_CTL_REG), + .OQ (OQ_out), + .T_OUT (T_OUT_out), + .CLK (CLK_in), + .CLKDIV (CLKDIV_in), + .D (D_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .T (T_in), + .GSR (glblGSR) + ); +end +endgenerate +`ifdef XIL_TIMING + reg notifier; + + wire clk_en_n; + wire clk_en_p; + wire clkdiv_en_n; + wire clkdiv_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; + assign clkdiv_en_n = IS_CLKDIV_INVERTED_BIN; + assign clkdiv_en_p = ~IS_CLKDIV_INVERTED_BIN; +`endif + + specify + (CLK => OQ) = (100:100:100, 100:100:100); + (CLK => T_OUT) = (100:100:100, 100:100:100); + (CLKDIV => OQ) = (100:100:100, 100:100:100); + (CLKDIV => T_OUT) = (100:100:100, 100:100:100); + (D *> OQ) = (0:0:0, 0:0:0); + (D *> T_OUT) = (0:0:0, 0:0:0); + (T => T_OUT) = (0:0:0, 0:0:0); + (negedge RST => (OQ +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (T_OUT +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (OQ +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (T_OUT +: 0)) = (100:100:100, 100:100:100); + // if (init_param == 1'b1) (negedge RST => (OQ +: 1)) = (100:100:100, 100:100:100); + // if (init_param == 1'b1) (negedge RST => (T_OUT +: 1)) = (100:100:100, 100:100:100); + // if (init_param == 1'b1) (posedge RST => (OQ +: 1)) = (100:100:100, 100:100:100); + // if (init_param == 1'b1) (posedge RST => (T_OUT +: 1)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (negedge CLKDIV, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLKDIV, 0:0:0, notifier); + $recrem (negedge RST, negedge CLKDIV, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, RST_delay, CLKDIV_delay); + $recrem (negedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, RST_delay, CLKDIV_delay); + $recrem (posedge RST, negedge CLKDIV, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, RST_delay, CLKDIV_delay); + $recrem (posedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, RST_delay, CLKDIV_delay); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay); + $setuphold (negedge CLKDIV, negedge D, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, CLKDIV_delay, D_delay); + $setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, CLKDIV_delay, RST_delay); + $setuphold (negedge CLKDIV, posedge D, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, CLKDIV_delay, D_delay); + $setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_n, clkdiv_en_n, CLKDIV_delay, RST_delay); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay); + $setuphold (posedge CLKDIV, negedge D, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, CLKDIV_delay, D_delay); + $setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, CLKDIV_delay, RST_delay); + $setuphold (posedge CLKDIV, posedge D, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, CLKDIV_delay, D_delay); + $setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, clkdiv_en_p, clkdiv_en_p, CLKDIV_delay, RST_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLKDIV, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLKDIV, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/OUT_FIFO.v b/verilog/src/unisims/OUT_FIFO.v new file mode 100644 index 0000000..fa48142 --- /dev/null +++ b/verilog/src/unisims/OUT_FIFO.v @@ -0,0 +1,385 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Simulation Library Component +// / / 7SERIES OUT FIFO +// /__/ /\ Filename : OUT_FIFO.v +// \ \ / \ +// \__\/\__ \ +// +// Date: Comment: +// 15MAR2010 Initial UNI/UNP/SIM version from yml +// 03JUN2010 yml update +// 10JUN2010 yml update +// 29JUN2010 enable encrypted rtl +// 10AUG2010 yml, rtl update +// 28SEP2010 minor clean up +// add width checks +// 28OCT2010 rtl update +// 05NOV2010 update defaults +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 15AUG2011 621681 remove SIM_SPEEDUP, make default +// 21SEP2011 625537 period checks on RDCLK, WRCLK +// 16FEB2012 645871 add conditions to RDEN -> Q delays +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module OUT_FIFO ( + ALMOSTEMPTY, + ALMOSTFULL, + EMPTY, + FULL, + Q0, + Q1, + Q2, + Q3, + Q4, + Q5, + Q6, + Q7, + Q8, + Q9, + + D0, + D1, + D2, + D3, + D4, + D5, + D6, + D7, + D8, + D9, + RDCLK, + RDEN, + RESET, + WRCLK, + WREN +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; + parameter OUTPUT_DISABLE = "FALSE"; + parameter SYNCHRONOUS_MODE = "FALSE"; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam out_delay = 0; +`else + localparam in_delay = 1; + localparam out_delay = 10; +`endif + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + localparam MODULE_NAME = "OUT_FIFO"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [3:0] Q0; + output [3:0] Q1; + output [3:0] Q2; + output [3:0] Q3; + output [3:0] Q4; + output [3:0] Q7; + output [3:0] Q8; + output [3:0] Q9; + output [7:0] Q5; + output [7:0] Q6; + + input RDCLK; + input RDEN; + input RESET; + input WRCLK; + input WREN; + input [7:0] D0; + input [7:0] D1; + input [7:0] D2; + input [7:0] D3; + input [7:0] D4; + input [7:0] D5; + input [7:0] D6; + input [7:0] D7; + input [7:0] D8; + input [7:0] D9; + + reg [0:0] ARRAY_MODE_BINARY; + reg [0:0] OUTPUT_DISABLE_BINARY; + reg [0:0] SLOW_RD_CLK_BINARY; + reg [0:0] SLOW_WR_CLK_BINARY; + reg [0:0] SYNCHRONOUS_MODE_BINARY; + reg [3:0] SPARE_BINARY; + reg [7:0] ALMOST_EMPTY_VALUE_BINARY; + reg [7:0] ALMOST_FULL_VALUE_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (ALMOST_EMPTY_VALUE) + 1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001; + 2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011; + default : begin + $display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE); + #1 $finish; + end + endcase + + case (ALMOST_FULL_VALUE) + 1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001; + 2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011; + default : begin + $display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE); + #1 $finish; + end + endcase + + case (ARRAY_MODE) + "ARRAY_MODE_8_X_4" : ARRAY_MODE_BINARY <= 1'b1; + "ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_8_X_4 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE); + #1 $finish; + end + endcase + + case (OUTPUT_DISABLE) + "FALSE" : OUTPUT_DISABLE_BINARY <= 1'b0; + "TRUE" : OUTPUT_DISABLE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute OUTPUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_DISABLE); + #1 $finish; + end + endcase + + SLOW_RD_CLK_BINARY <= 1'b0; + SLOW_WR_CLK_BINARY <= 1'b0; + SPARE_BINARY <= 4'b0; + + case (SYNCHRONOUS_MODE) + "FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE); + #1 $finish; + end + endcase + + end + + wire [3:0] delay_Q0; + wire [3:0] delay_Q1; + wire [3:0] delay_Q2; + wire [3:0] delay_Q3; + wire [3:0] delay_Q4; + wire [3:0] delay_Q7; + wire [3:0] delay_Q8; + wire [3:0] delay_Q9; + wire [7:0] delay_Q5; + wire [7:0] delay_Q6; + wire delay_ALMOSTEMPTY; + wire delay_ALMOSTFULL; + wire delay_EMPTY; + wire delay_FULL; + wire [3:0] delay_SCANOUT; + + wire [7:0] delay_D0; + wire [7:0] delay_D1; + wire [7:0] delay_D2; + wire [7:0] delay_D3; + wire [7:0] delay_D4; + wire [7:0] delay_D5; + wire [7:0] delay_D6; + wire [7:0] delay_D7; + wire [7:0] delay_D8; + wire [7:0] delay_D9; + wire delay_RDCLK; + wire delay_RDEN; + wire delay_RESET; + wire delay_SCANENB = 1'b1; + wire delay_TESTMODEB = 1'b1; + wire delay_TESTREADDISB = 1'b1; + wire delay_TESTWRITEDISB = 1'b1; + wire [3:0] delay_SCANIN = 4'hf; + wire delay_WRCLK; + wire delay_WREN; + wire delay_GSR; + + assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY; + assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL; + assign #(out_delay) EMPTY = delay_EMPTY; + assign #(out_delay) FULL = delay_FULL; + assign #(out_delay) Q0 = delay_Q0; + assign #(out_delay) Q1 = delay_Q1; + assign #(out_delay) Q2 = delay_Q2; + assign #(out_delay) Q3 = delay_Q3; + assign #(out_delay) Q4 = delay_Q4; + assign #(out_delay) Q5 = delay_Q5; + assign #(out_delay) Q6 = delay_Q6; + assign #(out_delay) Q7 = delay_Q7; + assign #(out_delay) Q8 = delay_Q8; + assign #(out_delay) Q9 = delay_Q9; + +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_RDCLK = RDCLK; + assign #(INCLK_DELAY) delay_WRCLK = WRCLK; + + assign #(in_delay) delay_D0 = D0; + assign #(in_delay) delay_D1 = D1; + assign #(in_delay) delay_D2 = D2; + assign #(in_delay) delay_D3 = D3; + assign #(in_delay) delay_D4 = D4; + assign #(in_delay) delay_D5 = D5; + assign #(in_delay) delay_D6 = D6; + assign #(in_delay) delay_D7 = D7; + assign #(in_delay) delay_D8 = D8; + assign #(in_delay) delay_D9 = D9; + assign #(in_delay) delay_RDEN = RDEN; +`endif + assign #(in_delay) delay_RESET = RESET; +`ifndef XIL_TIMING + assign #(in_delay) delay_WREN = WREN; +`endif + assign delay_GSR = GSR; + + SIP_OUT_FIFO OUT_FIFO_INST ( + .ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY), + .ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY), + .ARRAY_MODE (ARRAY_MODE_BINARY), + .OUTPUT_DISABLE (OUTPUT_DISABLE_BINARY), + .SLOW_RD_CLK (SLOW_RD_CLK_BINARY), + .SLOW_WR_CLK (SLOW_WR_CLK_BINARY), + .SPARE (SPARE_BINARY), + .SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY), + + .ALMOSTEMPTY (delay_ALMOSTEMPTY), + .ALMOSTFULL (delay_ALMOSTFULL), + .EMPTY (delay_EMPTY), + .FULL (delay_FULL), + .Q0 (delay_Q0), + .Q1 (delay_Q1), + .Q2 (delay_Q2), + .Q3 (delay_Q3), + .Q4 (delay_Q4), + .Q5 (delay_Q5), + .Q6 (delay_Q6), + .Q7 (delay_Q7), + .Q8 (delay_Q8), + .Q9 (delay_Q9), + .SCANOUT (delay_SCANOUT), + .D0 (delay_D0), + .D1 (delay_D1), + .D2 (delay_D2), + .D3 (delay_D3), + .D4 (delay_D4), + .D5 (delay_D5), + .D6 (delay_D6), + .D7 (delay_D7), + .D8 (delay_D8), + .D9 (delay_D9), + .RDCLK (delay_RDCLK), + .RDEN (delay_RDEN), + .RESET (delay_RESET), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .TESTMODEB (delay_TESTMODEB), + .TESTREADDISB (delay_TESTREADDISB), + .TESTWRITEDISB (delay_TESTWRITEDISB), + .WRCLK (delay_WRCLK), + .WREN (delay_WREN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (negedge RDCLK, 0:0:0, notifier); + $period (negedge WRCLK, 0:0:0, notifier); + $period (posedge RDCLK, 0:0:0, notifier); + $period (posedge WRCLK, 0:0:0, notifier); + $setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN); + $setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN); + $setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0); + $setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1); + $setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2); + $setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3); + $setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4); + $setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5); + $setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6); + $setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7); + $setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8); + $setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9); + $setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN); + $setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0); + $setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1); + $setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2); + $setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3); + $setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4); + $setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5); + $setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6); + $setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7); + $setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8); + $setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9); + $setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN); + $width (negedge RDCLK, 0:0:0, 0, notifier); + $width (negedge RESET, 0:0:0, 0, notifier); + $width (negedge WRCLK, 0:0:0, 0, notifier); + $width (posedge RDCLK, 0:0:0, 0, notifier); + $width (posedge RESET, 0:0:0, 0, notifier); + $width (posedge WRCLK, 0:0:0, 0, notifier); + ( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10); + ( RDCLK *> EMPTY) = (10:10:10, 10:10:10); + ( RDCLK *> Q0) = (10:10:10, 10:10:10); + ( RDCLK *> Q1) = (10:10:10, 10:10:10); + ( RDCLK *> Q2) = (10:10:10, 10:10:10); + ( RDCLK *> Q3) = (10:10:10, 10:10:10); + ( RDCLK *> Q4) = (10:10:10, 10:10:10); + ( RDCLK *> Q5) = (10:10:10, 10:10:10); + ( RDCLK *> Q6) = (10:10:10, 10:10:10); + ( RDCLK *> Q7) = (10:10:10, 10:10:10); + ( RDCLK *> Q8) = (10:10:10, 10:10:10); + ( RDCLK *> Q9) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q0) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q1) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q2) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q3) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q4) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q5) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q6) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q7) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q8) = (10:10:10, 10:10:10); + if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q9) = (10:10:10, 10:10:10); + ( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10); + ( WRCLK *> FULL) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // OUT_FIFO + +`endcelldefine diff --git a/verilog/src/unisims/PCIE40E4.v b/verilog/src/unisims/PCIE40E4.v new file mode 100644 index 0000000..61d6d37 --- /dev/null +++ b/verilog/src/unisims/PCIE40E4.v @@ -0,0 +1,24733 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / PCIE40E4 +// /___/ /\ Filename : PCIE40E4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PCIE40E4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter ARI_CAP_ENABLE = "FALSE", + parameter AUTO_FLR_RESPONSE = "FALSE", + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0, + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20, + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080, + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE", + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE", + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE", + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE", + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE", + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000, + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE", + parameter AXISTEN_IF_EXT_512 = "FALSE", + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE", + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE", + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE", + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE", + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE", + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_RC_STRADDLE = "FALSE", + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE", + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE", + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE", + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2, + parameter CFG_BYPASS_MODE_ENABLE = "FALSE", + parameter CRM_CORE_CLK_FREQ_500 = "TRUE", + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2, + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000, + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00, + parameter [3:0] DEBUG_CAR_SPARE = 4'h0, + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000, + parameter [15:0] DEBUG_LL_SPARE = 16'h0000, + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE", + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE", + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE", + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE", + parameter [15:0] DEBUG_PL_SPARE = 16'h0000, + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE", + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE", + parameter [15:0] DEBUG_TL_SPARE = 16'h0000, + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + parameter DSN_CAP_ENABLE = "FALSE", + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter HEADER_TYPE_OVERRIDE = "FALSE", + parameter IS_SWITCH_PORT = "FALSE", + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter [8:0] LL_ACK_TIMEOUT = 9'h000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE", + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE", + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0, + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE", + parameter LL_RX_TLP_PARITY_GEN = "TRUE", + parameter LL_TX_TLP_PARITY_CHK = "TRUE", + parameter [15:0] LL_USER_SPARE = 16'h0000, + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250, + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE", + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE", + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000, + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE", + parameter MCAP_ENABLE = "FALSE", + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE", + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000, + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE", + parameter [15:0] MCAP_VSEC_ID = 16'h0000, + parameter [11:0] MCAP_VSEC_LEN = 12'h02C, + parameter [3:0] MCAP_VSEC_REV = 4'h0, + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE", + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [3:0] PF0_ARI_CAP_VER = 4'h1, + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR0_CONTROL = 3'h4, + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF0_BAR1_CONTROL = 3'h0, + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR3_CONTROL = 3'h0, + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR5_CONTROL = 3'h0, + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF0_CLASS_CODE = 24'h000000, + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE", + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE", + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE", + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0, + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE", + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0, + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE", + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1, + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7, + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0, + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000, + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000, + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_LTR_CAP_VER = 4'h1, + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04, + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00, + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF0_PM_CAP_ID = 8'h01, + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00, + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE", + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE", + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3, + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE", + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000, + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF0_TPHR_CAP_ENABLE = "FALSE", + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1, + parameter PF0_VC_CAP_ENABLE = "FALSE", + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_VC_CAP_VER = 4'h1, + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR0_CONTROL = 3'h4, + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF1_BAR1_CONTROL = 3'h0, + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR3_CONTROL = 3'h0, + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR5_CONTROL = 3'h0, + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF1_CLASS_CODE = 24'h000000, + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00, + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00, + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR0_CONTROL = 3'h4, + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF2_BAR1_CONTROL = 3'h0, + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR3_CONTROL = 3'h0, + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR5_CONTROL = 3'h0, + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF2_CLASS_CODE = 24'h000000, + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00, + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00, + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR0_CONTROL = 3'h4, + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF3_BAR1_CONTROL = 3'h0, + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR3_CONTROL = 3'h0, + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR5_CONTROL = 3'h0, + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF3_CLASS_CODE = 24'h000000, + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00, + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00, + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE", + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE", + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE", + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE", + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE", + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE", + parameter PL_DISABLE_DC_BALANCE = "FALSE", + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE", + parameter PL_DISABLE_LANE_REVERSAL = "FALSE", + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0, + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE", + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE", + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000, + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE", + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0, + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0, + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02, + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1, + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0, + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33, + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44, + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE", + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0, + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0, + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE", + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE", + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE", + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE", + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE", + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE", + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00, + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4, + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08, + parameter integer PL_N_FTS = 255, + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE", + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE", + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00, + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0, + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0, + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0, + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0, + parameter PL_SRIS_ENABLE = "FALSE", + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00, + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00, + parameter PL_UPSTREAM_FACING = "TRUE", + parameter [15:0] PL_USER_SPARE = 16'h0000, + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500, + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8, + parameter PM_ENABLE_L23_ENTRY = "FALSE", + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE", + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100, + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000, + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000, + parameter SIM_VERSION = "1.0", + parameter SPARE_BIT0 = "FALSE", + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter SPARE_BIT3 = "FALSE", + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0, + parameter TL2CFG_IF_PARITY_CHK = "TRUE", + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0, + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1, + parameter [11:0] TL_CREDITS_CD = 12'h000, + parameter [7:0] TL_CREDITS_CH = 8'h00, + parameter [11:0] TL_CREDITS_NPD = 12'h004, + parameter [7:0] TL_CREDITS_NPH = 8'h20, + parameter [11:0] TL_CREDITS_PD = 12'h0E0, + parameter [7:0] TL_CREDITS_PH = 8'h20, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08, + parameter [1:0] TL_PF_ENABLE_REG = 2'h0, + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0, + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE", + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE", + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE", + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE", + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE", + parameter [15:0] TL_USER_SPARE = 16'h0000, + parameter TPH_FROM_RAM_PIPELINE = "FALSE", + parameter TPH_TO_RAM_PIPELINE = "FALSE", + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80, + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0 +)( + output [7:0] AXIUSEROUT, + output [7:0] CFGBUSNUMBER, + output [1:0] CFGCURRENTSPEED, + output CFGERRCOROUT, + output CFGERRFATALOUT, + output CFGERRNONFATALOUT, + output [7:0] CFGEXTFUNCTIONNUMBER, + output CFGEXTREADRECEIVED, + output [9:0] CFGEXTREGISTERNUMBER, + output [3:0] CFGEXTWRITEBYTEENABLE, + output [31:0] CFGEXTWRITEDATA, + output CFGEXTWRITERECEIVED, + output [11:0] CFGFCCPLD, + output [7:0] CFGFCCPLH, + output [11:0] CFGFCNPD, + output [7:0] CFGFCNPH, + output [11:0] CFGFCPD, + output [7:0] CFGFCPH, + output [3:0] CFGFLRINPROCESS, + output [11:0] CFGFUNCTIONPOWERSTATE, + output [15:0] CFGFUNCTIONSTATUS, + output CFGHOTRESETOUT, + output [31:0] CFGINTERRUPTMSIDATA, + output [3:0] CFGINTERRUPTMSIENABLE, + output CFGINTERRUPTMSIFAIL, + output CFGINTERRUPTMSIMASKUPDATE, + output [11:0] CFGINTERRUPTMSIMMENABLE, + output CFGINTERRUPTMSISENT, + output [3:0] CFGINTERRUPTMSIXENABLE, + output [3:0] CFGINTERRUPTMSIXMASK, + output CFGINTERRUPTMSIXVECPENDINGSTATUS, + output CFGINTERRUPTSENT, + output [1:0] CFGLINKPOWERSTATE, + output [4:0] CFGLOCALERROROUT, + output CFGLOCALERRORVALID, + output CFGLTRENABLE, + output [5:0] CFGLTSSMSTATE, + output [1:0] CFGMAXPAYLOAD, + output [2:0] CFGMAXREADREQ, + output [31:0] CFGMGMTREADDATA, + output CFGMGMTREADWRITEDONE, + output CFGMSGRECEIVED, + output [7:0] CFGMSGRECEIVEDDATA, + output [4:0] CFGMSGRECEIVEDTYPE, + output CFGMSGTRANSMITDONE, + output [12:0] CFGMSIXRAMADDRESS, + output CFGMSIXRAMREADENABLE, + output [3:0] CFGMSIXRAMWRITEBYTEENABLE, + output [35:0] CFGMSIXRAMWRITEDATA, + output [2:0] CFGNEGOTIATEDWIDTH, + output [1:0] CFGOBFFENABLE, + output CFGPHYLINKDOWN, + output [1:0] CFGPHYLINKSTATUS, + output CFGPLSTATUSCHANGE, + output CFGPOWERSTATECHANGEINTERRUPT, + output [3:0] CFGRCBSTATUS, + output [1:0] CFGRXPMSTATE, + output [11:0] CFGTPHRAMADDRESS, + output CFGTPHRAMREADENABLE, + output [3:0] CFGTPHRAMWRITEBYTEENABLE, + output [35:0] CFGTPHRAMWRITEDATA, + output [3:0] CFGTPHREQUESTERENABLE, + output [11:0] CFGTPHSTMODE, + output [1:0] CFGTXPMSTATE, + output CONFMCAPDESIGNSWITCH, + output CONFMCAPEOS, + output CONFMCAPINUSEBYPCIE, + output CONFREQREADY, + output [31:0] CONFRESPRDATA, + output CONFRESPVALID, + output [31:0] DBGCTRL0OUT, + output [31:0] DBGCTRL1OUT, + output [255:0] DBGDATA0OUT, + output [255:0] DBGDATA1OUT, + output [15:0] DRPDO, + output DRPRDY, + output [255:0] MAXISCQTDATA, + output [7:0] MAXISCQTKEEP, + output MAXISCQTLAST, + output [87:0] MAXISCQTUSER, + output MAXISCQTVALID, + output [255:0] MAXISRCTDATA, + output [7:0] MAXISRCTKEEP, + output MAXISRCTLAST, + output [74:0] MAXISRCTUSER, + output MAXISRCTVALID, + output [8:0] MIREPLAYRAMADDRESS0, + output [8:0] MIREPLAYRAMADDRESS1, + output MIREPLAYRAMREADENABLE0, + output MIREPLAYRAMREADENABLE1, + output [127:0] MIREPLAYRAMWRITEDATA0, + output [127:0] MIREPLAYRAMWRITEDATA1, + output MIREPLAYRAMWRITEENABLE0, + output MIREPLAYRAMWRITEENABLE1, + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0, + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1, + output [1:0] MIRXCOMPLETIONRAMREADENABLE0, + output [1:0] MIRXCOMPLETIONRAMREADENABLE1, + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0, + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1, + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0, + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1, + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0, + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1, + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0, + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1, + output MIRXPOSTEDREQUESTRAMREADENABLE0, + output MIRXPOSTEDREQUESTRAMREADENABLE1, + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0, + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1, + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0, + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1, + output MIRXPOSTEDREQUESTRAMWRITEENABLE0, + output MIRXPOSTEDREQUESTRAMWRITEENABLE1, + output [5:0] PCIECQNPREQCOUNT, + output PCIEPERST0B, + output PCIEPERST1B, + output [5:0] PCIERQSEQNUM0, + output [5:0] PCIERQSEQNUM1, + output PCIERQSEQNUMVLD0, + output PCIERQSEQNUMVLD1, + output [7:0] PCIERQTAG0, + output [7:0] PCIERQTAG1, + output [3:0] PCIERQTAGAV, + output PCIERQTAGVLD0, + output PCIERQTAGVLD1, + output [3:0] PCIETFCNPDAV, + output [3:0] PCIETFCNPHAV, + output [1:0] PIPERX00EQCONTROL, + output PIPERX00POLARITY, + output [1:0] PIPERX01EQCONTROL, + output PIPERX01POLARITY, + output [1:0] PIPERX02EQCONTROL, + output PIPERX02POLARITY, + output [1:0] PIPERX03EQCONTROL, + output PIPERX03POLARITY, + output [1:0] PIPERX04EQCONTROL, + output PIPERX04POLARITY, + output [1:0] PIPERX05EQCONTROL, + output PIPERX05POLARITY, + output [1:0] PIPERX06EQCONTROL, + output PIPERX06POLARITY, + output [1:0] PIPERX07EQCONTROL, + output PIPERX07POLARITY, + output [1:0] PIPERX08EQCONTROL, + output PIPERX08POLARITY, + output [1:0] PIPERX09EQCONTROL, + output PIPERX09POLARITY, + output [1:0] PIPERX10EQCONTROL, + output PIPERX10POLARITY, + output [1:0] PIPERX11EQCONTROL, + output PIPERX11POLARITY, + output [1:0] PIPERX12EQCONTROL, + output PIPERX12POLARITY, + output [1:0] PIPERX13EQCONTROL, + output PIPERX13POLARITY, + output [1:0] PIPERX14EQCONTROL, + output PIPERX14POLARITY, + output [1:0] PIPERX15EQCONTROL, + output PIPERX15POLARITY, + output [5:0] PIPERXEQLPLFFS, + output [3:0] PIPERXEQLPTXPRESET, + output [1:0] PIPETX00CHARISK, + output PIPETX00COMPLIANCE, + output [31:0] PIPETX00DATA, + output PIPETX00DATAVALID, + output PIPETX00ELECIDLE, + output [1:0] PIPETX00EQCONTROL, + output [5:0] PIPETX00EQDEEMPH, + output [1:0] PIPETX00POWERDOWN, + output PIPETX00STARTBLOCK, + output [1:0] PIPETX00SYNCHEADER, + output [1:0] PIPETX01CHARISK, + output PIPETX01COMPLIANCE, + output [31:0] PIPETX01DATA, + output PIPETX01DATAVALID, + output PIPETX01ELECIDLE, + output [1:0] PIPETX01EQCONTROL, + output [5:0] PIPETX01EQDEEMPH, + output [1:0] PIPETX01POWERDOWN, + output PIPETX01STARTBLOCK, + output [1:0] PIPETX01SYNCHEADER, + output [1:0] PIPETX02CHARISK, + output PIPETX02COMPLIANCE, + output [31:0] PIPETX02DATA, + output PIPETX02DATAVALID, + output PIPETX02ELECIDLE, + output [1:0] PIPETX02EQCONTROL, + output [5:0] PIPETX02EQDEEMPH, + output [1:0] PIPETX02POWERDOWN, + output PIPETX02STARTBLOCK, + output [1:0] PIPETX02SYNCHEADER, + output [1:0] PIPETX03CHARISK, + output PIPETX03COMPLIANCE, + output [31:0] PIPETX03DATA, + output PIPETX03DATAVALID, + output PIPETX03ELECIDLE, + output [1:0] PIPETX03EQCONTROL, + output [5:0] PIPETX03EQDEEMPH, + output [1:0] PIPETX03POWERDOWN, + output PIPETX03STARTBLOCK, + output [1:0] PIPETX03SYNCHEADER, + output [1:0] PIPETX04CHARISK, + output PIPETX04COMPLIANCE, + output [31:0] PIPETX04DATA, + output PIPETX04DATAVALID, + output PIPETX04ELECIDLE, + output [1:0] PIPETX04EQCONTROL, + output [5:0] PIPETX04EQDEEMPH, + output [1:0] PIPETX04POWERDOWN, + output PIPETX04STARTBLOCK, + output [1:0] PIPETX04SYNCHEADER, + output [1:0] PIPETX05CHARISK, + output PIPETX05COMPLIANCE, + output [31:0] PIPETX05DATA, + output PIPETX05DATAVALID, + output PIPETX05ELECIDLE, + output [1:0] PIPETX05EQCONTROL, + output [5:0] PIPETX05EQDEEMPH, + output [1:0] PIPETX05POWERDOWN, + output PIPETX05STARTBLOCK, + output [1:0] PIPETX05SYNCHEADER, + output [1:0] PIPETX06CHARISK, + output PIPETX06COMPLIANCE, + output [31:0] PIPETX06DATA, + output PIPETX06DATAVALID, + output PIPETX06ELECIDLE, + output [1:0] PIPETX06EQCONTROL, + output [5:0] PIPETX06EQDEEMPH, + output [1:0] PIPETX06POWERDOWN, + output PIPETX06STARTBLOCK, + output [1:0] PIPETX06SYNCHEADER, + output [1:0] PIPETX07CHARISK, + output PIPETX07COMPLIANCE, + output [31:0] PIPETX07DATA, + output PIPETX07DATAVALID, + output PIPETX07ELECIDLE, + output [1:0] PIPETX07EQCONTROL, + output [5:0] PIPETX07EQDEEMPH, + output [1:0] PIPETX07POWERDOWN, + output PIPETX07STARTBLOCK, + output [1:0] PIPETX07SYNCHEADER, + output [1:0] PIPETX08CHARISK, + output PIPETX08COMPLIANCE, + output [31:0] PIPETX08DATA, + output PIPETX08DATAVALID, + output PIPETX08ELECIDLE, + output [1:0] PIPETX08EQCONTROL, + output [5:0] PIPETX08EQDEEMPH, + output [1:0] PIPETX08POWERDOWN, + output PIPETX08STARTBLOCK, + output [1:0] PIPETX08SYNCHEADER, + output [1:0] PIPETX09CHARISK, + output PIPETX09COMPLIANCE, + output [31:0] PIPETX09DATA, + output PIPETX09DATAVALID, + output PIPETX09ELECIDLE, + output [1:0] PIPETX09EQCONTROL, + output [5:0] PIPETX09EQDEEMPH, + output [1:0] PIPETX09POWERDOWN, + output PIPETX09STARTBLOCK, + output [1:0] PIPETX09SYNCHEADER, + output [1:0] PIPETX10CHARISK, + output PIPETX10COMPLIANCE, + output [31:0] PIPETX10DATA, + output PIPETX10DATAVALID, + output PIPETX10ELECIDLE, + output [1:0] PIPETX10EQCONTROL, + output [5:0] PIPETX10EQDEEMPH, + output [1:0] PIPETX10POWERDOWN, + output PIPETX10STARTBLOCK, + output [1:0] PIPETX10SYNCHEADER, + output [1:0] PIPETX11CHARISK, + output PIPETX11COMPLIANCE, + output [31:0] PIPETX11DATA, + output PIPETX11DATAVALID, + output PIPETX11ELECIDLE, + output [1:0] PIPETX11EQCONTROL, + output [5:0] PIPETX11EQDEEMPH, + output [1:0] PIPETX11POWERDOWN, + output PIPETX11STARTBLOCK, + output [1:0] PIPETX11SYNCHEADER, + output [1:0] PIPETX12CHARISK, + output PIPETX12COMPLIANCE, + output [31:0] PIPETX12DATA, + output PIPETX12DATAVALID, + output PIPETX12ELECIDLE, + output [1:0] PIPETX12EQCONTROL, + output [5:0] PIPETX12EQDEEMPH, + output [1:0] PIPETX12POWERDOWN, + output PIPETX12STARTBLOCK, + output [1:0] PIPETX12SYNCHEADER, + output [1:0] PIPETX13CHARISK, + output PIPETX13COMPLIANCE, + output [31:0] PIPETX13DATA, + output PIPETX13DATAVALID, + output PIPETX13ELECIDLE, + output [1:0] PIPETX13EQCONTROL, + output [5:0] PIPETX13EQDEEMPH, + output [1:0] PIPETX13POWERDOWN, + output PIPETX13STARTBLOCK, + output [1:0] PIPETX13SYNCHEADER, + output [1:0] PIPETX14CHARISK, + output PIPETX14COMPLIANCE, + output [31:0] PIPETX14DATA, + output PIPETX14DATAVALID, + output PIPETX14ELECIDLE, + output [1:0] PIPETX14EQCONTROL, + output [5:0] PIPETX14EQDEEMPH, + output [1:0] PIPETX14POWERDOWN, + output PIPETX14STARTBLOCK, + output [1:0] PIPETX14SYNCHEADER, + output [1:0] PIPETX15CHARISK, + output PIPETX15COMPLIANCE, + output [31:0] PIPETX15DATA, + output PIPETX15DATAVALID, + output PIPETX15ELECIDLE, + output [1:0] PIPETX15EQCONTROL, + output [5:0] PIPETX15EQDEEMPH, + output [1:0] PIPETX15POWERDOWN, + output PIPETX15STARTBLOCK, + output [1:0] PIPETX15SYNCHEADER, + output PIPETXDEEMPH, + output [2:0] PIPETXMARGIN, + output [1:0] PIPETXRATE, + output PIPETXRCVRDET, + output PIPETXRESET, + output PIPETXSWING, + output PLEQINPROGRESS, + output [1:0] PLEQPHASE, + output PLGEN34EQMISMATCH, + output [3:0] SAXISCCTREADY, + output [3:0] SAXISRQTREADY, + output [31:0] USERSPAREOUT, + + input [7:0] AXIUSERIN, + input CFGCONFIGSPACEENABLE, + input [15:0] CFGDEVIDPF0, + input [15:0] CFGDEVIDPF1, + input [15:0] CFGDEVIDPF2, + input [15:0] CFGDEVIDPF3, + input [7:0] CFGDSBUSNUMBER, + input [4:0] CFGDSDEVICENUMBER, + input [2:0] CFGDSFUNCTIONNUMBER, + input [63:0] CFGDSN, + input [7:0] CFGDSPORTNUMBER, + input CFGERRCORIN, + input CFGERRUNCORIN, + input [31:0] CFGEXTREADDATA, + input CFGEXTREADDATAVALID, + input [2:0] CFGFCSEL, + input [3:0] CFGFLRDONE, + input CFGHOTRESETIN, + input [3:0] CFGINTERRUPTINT, + input [2:0] CFGINTERRUPTMSIATTR, + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER, + input [31:0] CFGINTERRUPTMSIINT, + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS, + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, + input [1:0] CFGINTERRUPTMSISELECT, + input CFGINTERRUPTMSITPHPRESENT, + input [7:0] CFGINTERRUPTMSITPHSTTAG, + input [1:0] CFGINTERRUPTMSITPHTYPE, + input [63:0] CFGINTERRUPTMSIXADDRESS, + input [31:0] CFGINTERRUPTMSIXDATA, + input CFGINTERRUPTMSIXINT, + input [1:0] CFGINTERRUPTMSIXVECPENDING, + input [3:0] CFGINTERRUPTPENDING, + input CFGLINKTRAININGENABLE, + input [9:0] CFGMGMTADDR, + input [3:0] CFGMGMTBYTEENABLE, + input CFGMGMTDEBUGACCESS, + input [7:0] CFGMGMTFUNCTIONNUMBER, + input CFGMGMTREAD, + input CFGMGMTWRITE, + input [31:0] CFGMGMTWRITEDATA, + input CFGMSGTRANSMIT, + input [31:0] CFGMSGTRANSMITDATA, + input [2:0] CFGMSGTRANSMITTYPE, + input [35:0] CFGMSIXRAMREADDATA, + input CFGPMASPML1ENTRYREJECT, + input CFGPMASPMTXL0SENTRYDISABLE, + input CFGPOWERSTATECHANGEACK, + input CFGREQPMTRANSITIONL23READY, + input [7:0] CFGREVIDPF0, + input [7:0] CFGREVIDPF1, + input [7:0] CFGREVIDPF2, + input [7:0] CFGREVIDPF3, + input [15:0] CFGSUBSYSIDPF0, + input [15:0] CFGSUBSYSIDPF1, + input [15:0] CFGSUBSYSIDPF2, + input [15:0] CFGSUBSYSIDPF3, + input [15:0] CFGSUBSYSVENDID, + input [35:0] CFGTPHRAMREADDATA, + input [15:0] CFGVENDID, + input CFGVFFLRDONE, + input [7:0] CFGVFFLRFUNCNUM, + input CONFMCAPREQUESTBYCONF, + input [31:0] CONFREQDATA, + input [3:0] CONFREQREGNUM, + input [1:0] CONFREQTYPE, + input CONFREQVALID, + input CORECLK, + input CORECLKMIREPLAYRAM0, + input CORECLKMIREPLAYRAM1, + input CORECLKMIRXCOMPLETIONRAM0, + input CORECLKMIRXCOMPLETIONRAM1, + input CORECLKMIRXPOSTEDREQUESTRAM0, + input CORECLKMIRXPOSTEDREQUESTRAM1, + input [5:0] DBGSEL0, + input [5:0] DBGSEL1, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input [21:0] MAXISCQTREADY, + input [21:0] MAXISRCTREADY, + input MCAPCLK, + input MCAPPERST0B, + input MCAPPERST1B, + input MGMTRESETN, + input MGMTSTICKYRESETN, + input [5:0] MIREPLAYRAMERRCOR, + input [5:0] MIREPLAYRAMERRUNCOR, + input [127:0] MIREPLAYRAMREADDATA0, + input [127:0] MIREPLAYRAMREADDATA1, + input [11:0] MIRXCOMPLETIONRAMERRCOR, + input [11:0] MIRXCOMPLETIONRAMERRUNCOR, + input [143:0] MIRXCOMPLETIONRAMREADDATA0, + input [143:0] MIRXCOMPLETIONRAMREADDATA1, + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR, + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR, + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0, + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1, + input [1:0] PCIECOMPLDELIVERED, + input [7:0] PCIECOMPLDELIVEREDTAG0, + input [7:0] PCIECOMPLDELIVEREDTAG1, + input [1:0] PCIECQNPREQ, + input PCIECQNPUSERCREDITRCVD, + input PCIECQPIPELINEEMPTY, + input PCIEPOSTEDREQDELIVERED, + input PIPECLK, + input PIPECLKEN, + input [5:0] PIPEEQFS, + input [5:0] PIPEEQLF, + input PIPERESETN, + input [1:0] PIPERX00CHARISK, + input [31:0] PIPERX00DATA, + input PIPERX00DATAVALID, + input PIPERX00ELECIDLE, + input PIPERX00EQDONE, + input PIPERX00EQLPADAPTDONE, + input PIPERX00EQLPLFFSSEL, + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET, + input PIPERX00PHYSTATUS, + input [1:0] PIPERX00STARTBLOCK, + input [2:0] PIPERX00STATUS, + input [1:0] PIPERX00SYNCHEADER, + input PIPERX00VALID, + input [1:0] PIPERX01CHARISK, + input [31:0] PIPERX01DATA, + input PIPERX01DATAVALID, + input PIPERX01ELECIDLE, + input PIPERX01EQDONE, + input PIPERX01EQLPADAPTDONE, + input PIPERX01EQLPLFFSSEL, + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET, + input PIPERX01PHYSTATUS, + input [1:0] PIPERX01STARTBLOCK, + input [2:0] PIPERX01STATUS, + input [1:0] PIPERX01SYNCHEADER, + input PIPERX01VALID, + input [1:0] PIPERX02CHARISK, + input [31:0] PIPERX02DATA, + input PIPERX02DATAVALID, + input PIPERX02ELECIDLE, + input PIPERX02EQDONE, + input PIPERX02EQLPADAPTDONE, + input PIPERX02EQLPLFFSSEL, + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET, + input PIPERX02PHYSTATUS, + input [1:0] PIPERX02STARTBLOCK, + input [2:0] PIPERX02STATUS, + input [1:0] PIPERX02SYNCHEADER, + input PIPERX02VALID, + input [1:0] PIPERX03CHARISK, + input [31:0] PIPERX03DATA, + input PIPERX03DATAVALID, + input PIPERX03ELECIDLE, + input PIPERX03EQDONE, + input PIPERX03EQLPADAPTDONE, + input PIPERX03EQLPLFFSSEL, + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET, + input PIPERX03PHYSTATUS, + input [1:0] PIPERX03STARTBLOCK, + input [2:0] PIPERX03STATUS, + input [1:0] PIPERX03SYNCHEADER, + input PIPERX03VALID, + input [1:0] PIPERX04CHARISK, + input [31:0] PIPERX04DATA, + input PIPERX04DATAVALID, + input PIPERX04ELECIDLE, + input PIPERX04EQDONE, + input PIPERX04EQLPADAPTDONE, + input PIPERX04EQLPLFFSSEL, + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET, + input PIPERX04PHYSTATUS, + input [1:0] PIPERX04STARTBLOCK, + input [2:0] PIPERX04STATUS, + input [1:0] PIPERX04SYNCHEADER, + input PIPERX04VALID, + input [1:0] PIPERX05CHARISK, + input [31:0] PIPERX05DATA, + input PIPERX05DATAVALID, + input PIPERX05ELECIDLE, + input PIPERX05EQDONE, + input PIPERX05EQLPADAPTDONE, + input PIPERX05EQLPLFFSSEL, + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET, + input PIPERX05PHYSTATUS, + input [1:0] PIPERX05STARTBLOCK, + input [2:0] PIPERX05STATUS, + input [1:0] PIPERX05SYNCHEADER, + input PIPERX05VALID, + input [1:0] PIPERX06CHARISK, + input [31:0] PIPERX06DATA, + input PIPERX06DATAVALID, + input PIPERX06ELECIDLE, + input PIPERX06EQDONE, + input PIPERX06EQLPADAPTDONE, + input PIPERX06EQLPLFFSSEL, + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET, + input PIPERX06PHYSTATUS, + input [1:0] PIPERX06STARTBLOCK, + input [2:0] PIPERX06STATUS, + input [1:0] PIPERX06SYNCHEADER, + input PIPERX06VALID, + input [1:0] PIPERX07CHARISK, + input [31:0] PIPERX07DATA, + input PIPERX07DATAVALID, + input PIPERX07ELECIDLE, + input PIPERX07EQDONE, + input PIPERX07EQLPADAPTDONE, + input PIPERX07EQLPLFFSSEL, + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET, + input PIPERX07PHYSTATUS, + input [1:0] PIPERX07STARTBLOCK, + input [2:0] PIPERX07STATUS, + input [1:0] PIPERX07SYNCHEADER, + input PIPERX07VALID, + input [1:0] PIPERX08CHARISK, + input [31:0] PIPERX08DATA, + input PIPERX08DATAVALID, + input PIPERX08ELECIDLE, + input PIPERX08EQDONE, + input PIPERX08EQLPADAPTDONE, + input PIPERX08EQLPLFFSSEL, + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET, + input PIPERX08PHYSTATUS, + input [1:0] PIPERX08STARTBLOCK, + input [2:0] PIPERX08STATUS, + input [1:0] PIPERX08SYNCHEADER, + input PIPERX08VALID, + input [1:0] PIPERX09CHARISK, + input [31:0] PIPERX09DATA, + input PIPERX09DATAVALID, + input PIPERX09ELECIDLE, + input PIPERX09EQDONE, + input PIPERX09EQLPADAPTDONE, + input PIPERX09EQLPLFFSSEL, + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET, + input PIPERX09PHYSTATUS, + input [1:0] PIPERX09STARTBLOCK, + input [2:0] PIPERX09STATUS, + input [1:0] PIPERX09SYNCHEADER, + input PIPERX09VALID, + input [1:0] PIPERX10CHARISK, + input [31:0] PIPERX10DATA, + input PIPERX10DATAVALID, + input PIPERX10ELECIDLE, + input PIPERX10EQDONE, + input PIPERX10EQLPADAPTDONE, + input PIPERX10EQLPLFFSSEL, + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET, + input PIPERX10PHYSTATUS, + input [1:0] PIPERX10STARTBLOCK, + input [2:0] PIPERX10STATUS, + input [1:0] PIPERX10SYNCHEADER, + input PIPERX10VALID, + input [1:0] PIPERX11CHARISK, + input [31:0] PIPERX11DATA, + input PIPERX11DATAVALID, + input PIPERX11ELECIDLE, + input PIPERX11EQDONE, + input PIPERX11EQLPADAPTDONE, + input PIPERX11EQLPLFFSSEL, + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET, + input PIPERX11PHYSTATUS, + input [1:0] PIPERX11STARTBLOCK, + input [2:0] PIPERX11STATUS, + input [1:0] PIPERX11SYNCHEADER, + input PIPERX11VALID, + input [1:0] PIPERX12CHARISK, + input [31:0] PIPERX12DATA, + input PIPERX12DATAVALID, + input PIPERX12ELECIDLE, + input PIPERX12EQDONE, + input PIPERX12EQLPADAPTDONE, + input PIPERX12EQLPLFFSSEL, + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET, + input PIPERX12PHYSTATUS, + input [1:0] PIPERX12STARTBLOCK, + input [2:0] PIPERX12STATUS, + input [1:0] PIPERX12SYNCHEADER, + input PIPERX12VALID, + input [1:0] PIPERX13CHARISK, + input [31:0] PIPERX13DATA, + input PIPERX13DATAVALID, + input PIPERX13ELECIDLE, + input PIPERX13EQDONE, + input PIPERX13EQLPADAPTDONE, + input PIPERX13EQLPLFFSSEL, + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET, + input PIPERX13PHYSTATUS, + input [1:0] PIPERX13STARTBLOCK, + input [2:0] PIPERX13STATUS, + input [1:0] PIPERX13SYNCHEADER, + input PIPERX13VALID, + input [1:0] PIPERX14CHARISK, + input [31:0] PIPERX14DATA, + input PIPERX14DATAVALID, + input PIPERX14ELECIDLE, + input PIPERX14EQDONE, + input PIPERX14EQLPADAPTDONE, + input PIPERX14EQLPLFFSSEL, + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET, + input PIPERX14PHYSTATUS, + input [1:0] PIPERX14STARTBLOCK, + input [2:0] PIPERX14STATUS, + input [1:0] PIPERX14SYNCHEADER, + input PIPERX14VALID, + input [1:0] PIPERX15CHARISK, + input [31:0] PIPERX15DATA, + input PIPERX15DATAVALID, + input PIPERX15ELECIDLE, + input PIPERX15EQDONE, + input PIPERX15EQLPADAPTDONE, + input PIPERX15EQLPLFFSSEL, + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET, + input PIPERX15PHYSTATUS, + input [1:0] PIPERX15STARTBLOCK, + input [2:0] PIPERX15STATUS, + input [1:0] PIPERX15SYNCHEADER, + input PIPERX15VALID, + input [17:0] PIPETX00EQCOEFF, + input PIPETX00EQDONE, + input [17:0] PIPETX01EQCOEFF, + input PIPETX01EQDONE, + input [17:0] PIPETX02EQCOEFF, + input PIPETX02EQDONE, + input [17:0] PIPETX03EQCOEFF, + input PIPETX03EQDONE, + input [17:0] PIPETX04EQCOEFF, + input PIPETX04EQDONE, + input [17:0] PIPETX05EQCOEFF, + input PIPETX05EQDONE, + input [17:0] PIPETX06EQCOEFF, + input PIPETX06EQDONE, + input [17:0] PIPETX07EQCOEFF, + input PIPETX07EQDONE, + input [17:0] PIPETX08EQCOEFF, + input PIPETX08EQDONE, + input [17:0] PIPETX09EQCOEFF, + input PIPETX09EQDONE, + input [17:0] PIPETX10EQCOEFF, + input PIPETX10EQDONE, + input [17:0] PIPETX11EQCOEFF, + input PIPETX11EQDONE, + input [17:0] PIPETX12EQCOEFF, + input PIPETX12EQDONE, + input [17:0] PIPETX13EQCOEFF, + input PIPETX13EQDONE, + input [17:0] PIPETX14EQCOEFF, + input PIPETX14EQDONE, + input [17:0] PIPETX15EQCOEFF, + input PIPETX15EQDONE, + input PLEQRESETEIEOSCOUNT, + input PLGEN2UPSTREAMPREFERDEEMPH, + input PLGEN34REDOEQSPEED, + input PLGEN34REDOEQUALIZATION, + input RESETN, + input [255:0] SAXISCCTDATA, + input [7:0] SAXISCCTKEEP, + input SAXISCCTLAST, + input [32:0] SAXISCCTUSER, + input SAXISCCTVALID, + input [255:0] SAXISRQTDATA, + input [7:0] SAXISRQTKEEP, + input SAXISRQTLAST, + input [61:0] SAXISRQTUSER, + input SAXISRQTVALID, + input USERCLK, + input USERCLK2, + input USERCLKEN, + input [31:0] USERSPAREIN +); + +// define constants + localparam MODULE_NAME = "PCIE40E4"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "PCIE40E4_dr.v" +`else + localparam [40:1] ARI_CAP_ENABLE_REG = ARI_CAP_ENABLE; + localparam [40:1] AUTO_FLR_RESPONSE_REG = AUTO_FLR_RESPONSE; + localparam [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE_REG = AXISTEN_IF_CC_ALIGNMENT_MODE; + localparam [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0_REG = AXISTEN_IF_COMPL_TIMEOUT_REG0; + localparam [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1_REG = AXISTEN_IF_COMPL_TIMEOUT_REG1; + localparam [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE_REG = AXISTEN_IF_CQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG = AXISTEN_IF_CQ_EN_POISONED_MEM_WR; + localparam [40:1] AXISTEN_IF_ENABLE_256_TAGS_REG = AXISTEN_IF_ENABLE_256_TAGS; + localparam [40:1] AXISTEN_IF_ENABLE_CLIENT_TAG_REG = AXISTEN_IF_ENABLE_CLIENT_TAG; + localparam [40:1] AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG = AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE; + localparam [40:1] AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG = AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK; + localparam [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE_REG = AXISTEN_IF_ENABLE_MSG_ROUTE; + localparam [40:1] AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG = AXISTEN_IF_ENABLE_RX_MSG_INTFC; + localparam [40:1] AXISTEN_IF_EXT_512_REG = AXISTEN_IF_EXT_512; + localparam [40:1] AXISTEN_IF_EXT_512_CC_STRADDLE_REG = AXISTEN_IF_EXT_512_CC_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_CQ_STRADDLE_REG = AXISTEN_IF_EXT_512_CQ_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_RC_STRADDLE_REG = AXISTEN_IF_EXT_512_RC_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_RQ_STRADDLE_REG = AXISTEN_IF_EXT_512_RQ_STRADDLE; + localparam [40:1] AXISTEN_IF_LEGACY_MODE_ENABLE_REG = AXISTEN_IF_LEGACY_MODE_ENABLE; + localparam [40:1] AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG = AXISTEN_IF_MSIX_FROM_RAM_PIPELINE; + localparam [40:1] AXISTEN_IF_MSIX_RX_PARITY_EN_REG = AXISTEN_IF_MSIX_RX_PARITY_EN; + localparam [40:1] AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG = AXISTEN_IF_MSIX_TO_RAM_PIPELINE; + localparam [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE_REG = AXISTEN_IF_RC_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RC_STRADDLE_REG = AXISTEN_IF_RC_STRADDLE; + localparam [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE_REG = AXISTEN_IF_RQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RX_PARITY_EN_REG = AXISTEN_IF_RX_PARITY_EN; + localparam [40:1] AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG = AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT; + localparam [40:1] AXISTEN_IF_TX_PARITY_EN_REG = AXISTEN_IF_TX_PARITY_EN; + localparam [1:0] AXISTEN_IF_WIDTH_REG = AXISTEN_IF_WIDTH; + localparam [40:1] CFG_BYPASS_MODE_ENABLE_REG = CFG_BYPASS_MODE_ENABLE; + localparam [40:1] CRM_CORE_CLK_FREQ_500_REG = CRM_CORE_CLK_FREQ_500; + localparam [1:0] CRM_USER_CLK_FREQ_REG = CRM_USER_CLK_FREQ; + localparam [15:0] DEBUG_AXI4ST_SPARE_REG = DEBUG_AXI4ST_SPARE; + localparam [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT_REG = DEBUG_AXIST_DISABLE_FEATURE_BIT; + localparam [3:0] DEBUG_CAR_SPARE_REG = DEBUG_CAR_SPARE; + localparam [15:0] DEBUG_CFG_SPARE_REG = DEBUG_CFG_SPARE; + localparam [15:0] DEBUG_LL_SPARE_REG = DEBUG_LL_SPARE; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG = DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL; + localparam [40:1] DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG = DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW; + localparam [40:1] DEBUG_PL_DISABLE_SCRAMBLING_REG = DEBUG_PL_DISABLE_SCRAMBLING; + localparam [40:1] DEBUG_PL_SIM_RESET_LFSR_REG = DEBUG_PL_SIM_RESET_LFSR; + localparam [15:0] DEBUG_PL_SPARE_REG = DEBUG_PL_SPARE; + localparam [40:1] DEBUG_TL_DISABLE_FC_TIMEOUT_REG = DEBUG_TL_DISABLE_FC_TIMEOUT; + localparam [40:1] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG = DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS; + localparam [15:0] DEBUG_TL_SPARE_REG = DEBUG_TL_SPARE; + localparam [7:0] DNSTREAM_LINK_NUM_REG = DNSTREAM_LINK_NUM; + localparam [40:1] DSN_CAP_ENABLE_REG = DSN_CAP_ENABLE; + localparam [40:1] EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG = EXTENDED_CFG_EXTEND_INTERFACE_ENABLE; + localparam [40:1] HEADER_TYPE_OVERRIDE_REG = HEADER_TYPE_OVERRIDE; + localparam [40:1] IS_SWITCH_PORT_REG = IS_SWITCH_PORT; + localparam [40:1] LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG = LEGACY_CFG_EXTEND_INTERFACE_ENABLE; + localparam [8:0] LL_ACK_TIMEOUT_REG = LL_ACK_TIMEOUT; + localparam [40:1] LL_ACK_TIMEOUT_EN_REG = LL_ACK_TIMEOUT_EN; + localparam [1:0] LL_ACK_TIMEOUT_FUNC_REG = LL_ACK_TIMEOUT_FUNC; + localparam [40:1] LL_DISABLE_SCHED_TX_NAK_REG = LL_DISABLE_SCHED_TX_NAK; + localparam [40:1] LL_REPLAY_FROM_RAM_PIPELINE_REG = LL_REPLAY_FROM_RAM_PIPELINE; + localparam [8:0] LL_REPLAY_TIMEOUT_REG = LL_REPLAY_TIMEOUT; + localparam [40:1] LL_REPLAY_TIMEOUT_EN_REG = LL_REPLAY_TIMEOUT_EN; + localparam [1:0] LL_REPLAY_TIMEOUT_FUNC_REG = LL_REPLAY_TIMEOUT_FUNC; + localparam [40:1] LL_REPLAY_TO_RAM_PIPELINE_REG = LL_REPLAY_TO_RAM_PIPELINE; + localparam [40:1] LL_RX_TLP_PARITY_GEN_REG = LL_RX_TLP_PARITY_GEN; + localparam [40:1] LL_TX_TLP_PARITY_CHK_REG = LL_TX_TLP_PARITY_CHK; + localparam [15:0] LL_USER_SPARE_REG = LL_USER_SPARE; + localparam [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG = LTR_TX_MESSAGE_MINIMUM_INTERVAL; + localparam [40:1] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG = LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE; + localparam [40:1] LTR_TX_MESSAGE_ON_LTR_ENABLE_REG = LTR_TX_MESSAGE_ON_LTR_ENABLE; + localparam [11:0] MCAP_CAP_NEXTPTR_REG = MCAP_CAP_NEXTPTR; + localparam [40:1] MCAP_CONFIGURE_OVERRIDE_REG = MCAP_CONFIGURE_OVERRIDE; + localparam [40:1] MCAP_ENABLE_REG = MCAP_ENABLE; + localparam [40:1] MCAP_EOS_DESIGN_SWITCH_REG = MCAP_EOS_DESIGN_SWITCH; + localparam [31:0] MCAP_FPGA_BITSTREAM_VERSION_REG = MCAP_FPGA_BITSTREAM_VERSION; + localparam [40:1] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_IO_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_INPUT_GATE_DESIGN_SWITCH_REG = MCAP_INPUT_GATE_DESIGN_SWITCH; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_EOS_REG = MCAP_INTERRUPT_ON_MCAP_EOS; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_ERROR_REG = MCAP_INTERRUPT_ON_MCAP_ERROR; + localparam [15:0] MCAP_VSEC_ID_REG = MCAP_VSEC_ID; + localparam [11:0] MCAP_VSEC_LEN_REG = MCAP_VSEC_LEN; + localparam [3:0] MCAP_VSEC_REV_REG = MCAP_VSEC_REV; + localparam [40:1] PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG = PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE; + localparam [11:0] PF0_AER_CAP_NEXTPTR_REG = PF0_AER_CAP_NEXTPTR; + localparam [11:0] PF0_ARI_CAP_NEXTPTR_REG = PF0_ARI_CAP_NEXTPTR; + localparam [7:0] PF0_ARI_CAP_NEXT_FUNC_REG = PF0_ARI_CAP_NEXT_FUNC; + localparam [3:0] PF0_ARI_CAP_VER_REG = PF0_ARI_CAP_VER; + localparam [5:0] PF0_BAR0_APERTURE_SIZE_REG = PF0_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_BAR0_CONTROL_REG = PF0_BAR0_CONTROL; + localparam [4:0] PF0_BAR1_APERTURE_SIZE_REG = PF0_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_BAR1_CONTROL_REG = PF0_BAR1_CONTROL; + localparam [5:0] PF0_BAR2_APERTURE_SIZE_REG = PF0_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_BAR2_CONTROL_REG = PF0_BAR2_CONTROL; + localparam [4:0] PF0_BAR3_APERTURE_SIZE_REG = PF0_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_BAR3_CONTROL_REG = PF0_BAR3_CONTROL; + localparam [5:0] PF0_BAR4_APERTURE_SIZE_REG = PF0_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_BAR4_CONTROL_REG = PF0_BAR4_CONTROL; + localparam [4:0] PF0_BAR5_APERTURE_SIZE_REG = PF0_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_BAR5_CONTROL_REG = PF0_BAR5_CONTROL; + localparam [7:0] PF0_CAPABILITY_POINTER_REG = PF0_CAPABILITY_POINTER; + localparam [23:0] PF0_CLASS_CODE_REG = PF0_CLASS_CODE; + localparam [40:1] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG = PF0_DEV_CAP2_ARI_FORWARD_ENABLE; + localparam [40:1] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG = PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE; + localparam [40:1] PF0_DEV_CAP2_LTR_SUPPORT_REG = PF0_DEV_CAP2_LTR_SUPPORT; + localparam [1:0] PF0_DEV_CAP2_OBFF_SUPPORT_REG = PF0_DEV_CAP2_OBFF_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L1_LATENCY; + localparam [40:1] PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG = PF0_DEV_CAP_EXT_TAG_SUPPORTED; + localparam [40:1] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG = PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE; + localparam [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF0_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF0_DSN_CAP_NEXTPTR_REG = PF0_DSN_CAP_NEXTPTR; + localparam [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE_REG = PF0_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF0_EXPANSION_ROM_ENABLE_REG = PF0_EXPANSION_ROM_ENABLE; + localparam [2:0] PF0_INTERRUPT_PIN_REG = PF0_INTERRUPT_PIN; + localparam [1:0] PF0_LINK_CAP_ASPM_SUPPORT_REG = PF0_LINK_CAP_ASPM_SUPPORT; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4; + localparam [0:0] PF0_LINK_CONTROL_RCB_REG = PF0_LINK_CONTROL_RCB; + localparam [40:1] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG = PF0_LINK_STATUS_SLOT_CLOCK_CONFIG; + localparam [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG = PF0_LTR_CAP_MAX_NOSNOOP_LAT; + localparam [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT_REG = PF0_LTR_CAP_MAX_SNOOP_LAT; + localparam [11:0] PF0_LTR_CAP_NEXTPTR_REG = PF0_LTR_CAP_NEXTPTR; + localparam [3:0] PF0_LTR_CAP_VER_REG = PF0_LTR_CAP_VER; + localparam [7:0] PF0_MSIX_CAP_NEXTPTR_REG = PF0_MSIX_CAP_NEXTPTR; + localparam [2:0] PF0_MSIX_CAP_PBA_BIR_REG = PF0_MSIX_CAP_PBA_BIR; + localparam [28:0] PF0_MSIX_CAP_PBA_OFFSET_REG = PF0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF0_MSIX_CAP_TABLE_BIR_REG = PF0_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF0_MSIX_CAP_TABLE_OFFSET_REG = PF0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF0_MSIX_CAP_TABLE_SIZE_REG = PF0_MSIX_CAP_TABLE_SIZE; + localparam [5:0] PF0_MSIX_VECTOR_COUNT_REG = PF0_MSIX_VECTOR_COUNT; + localparam [2:0] PF0_MSI_CAP_MULTIMSGCAP_REG = PF0_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF0_MSI_CAP_NEXTPTR_REG = PF0_MSI_CAP_NEXTPTR; + localparam [40:1] PF0_MSI_CAP_PERVECMASKCAP_REG = PF0_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF0_PCIE_CAP_NEXTPTR_REG = PF0_PCIE_CAP_NEXTPTR; + localparam [7:0] PF0_PM_CAP_ID_REG = PF0_PM_CAP_ID; + localparam [7:0] PF0_PM_CAP_NEXTPTR_REG = PF0_PM_CAP_NEXTPTR; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D0_REG = PF0_PM_CAP_PMESUPPORT_D0; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D1_REG = PF0_PM_CAP_PMESUPPORT_D1; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D3HOT_REG = PF0_PM_CAP_PMESUPPORT_D3HOT; + localparam [40:1] PF0_PM_CAP_SUPP_D1_STATE_REG = PF0_PM_CAP_SUPP_D1_STATE; + localparam [2:0] PF0_PM_CAP_VER_ID_REG = PF0_PM_CAP_VER_ID; + localparam [40:1] PF0_PM_CSR_NOSOFTRESET_REG = PF0_PM_CSR_NOSOFTRESET; + localparam [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG = PF0_SECONDARY_PCIE_CAP_NEXTPTR; + localparam [40:1] PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE_REG = PF0_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR0_CONTROL_REG = PF0_SRIOV_BAR0_CONTROL; + localparam [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE_REG = PF0_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR1_CONTROL_REG = PF0_SRIOV_BAR1_CONTROL; + localparam [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE_REG = PF0_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR2_CONTROL_REG = PF0_SRIOV_BAR2_CONTROL; + localparam [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE_REG = PF0_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR3_CONTROL_REG = PF0_SRIOV_BAR3_CONTROL; + localparam [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE_REG = PF0_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR4_CONTROL_REG = PF0_SRIOV_BAR4_CONTROL; + localparam [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE_REG = PF0_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR5_CONTROL_REG = PF0_SRIOV_BAR5_CONTROL; + localparam [15:0] PF0_SRIOV_CAP_INITIAL_VF_REG = PF0_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF0_SRIOV_CAP_NEXTPTR_REG = PF0_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF0_SRIOV_CAP_TOTAL_VF_REG = PF0_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF0_SRIOV_CAP_VER_REG = PF0_SRIOV_CAP_VER; + localparam [15:0] PF0_SRIOV_FIRST_VF_OFFSET_REG = PF0_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF0_SRIOV_FUNC_DEP_LINK_REG = PF0_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF0_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF0_SRIOV_VF_DEVICE_ID_REG = PF0_SRIOV_VF_DEVICE_ID; + localparam [40:1] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF0_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF0_TPHR_CAP_ENABLE_REG = PF0_TPHR_CAP_ENABLE; + localparam [40:1] PF0_TPHR_CAP_INT_VEC_MODE_REG = PF0_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF0_TPHR_CAP_NEXTPTR_REG = PF0_TPHR_CAP_NEXTPTR; + localparam [2:0] PF0_TPHR_CAP_ST_MODE_SEL_REG = PF0_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF0_TPHR_CAP_ST_TABLE_LOC_REG = PF0_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE_REG = PF0_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF0_TPHR_CAP_VER_REG = PF0_TPHR_CAP_VER; + localparam [40:1] PF0_VC_CAP_ENABLE_REG = PF0_VC_CAP_ENABLE; + localparam [11:0] PF0_VC_CAP_NEXTPTR_REG = PF0_VC_CAP_NEXTPTR; + localparam [3:0] PF0_VC_CAP_VER_REG = PF0_VC_CAP_VER; + localparam [11:0] PF1_AER_CAP_NEXTPTR_REG = PF1_AER_CAP_NEXTPTR; + localparam [11:0] PF1_ARI_CAP_NEXTPTR_REG = PF1_ARI_CAP_NEXTPTR; + localparam [7:0] PF1_ARI_CAP_NEXT_FUNC_REG = PF1_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF1_BAR0_APERTURE_SIZE_REG = PF1_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_BAR0_CONTROL_REG = PF1_BAR0_CONTROL; + localparam [4:0] PF1_BAR1_APERTURE_SIZE_REG = PF1_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_BAR1_CONTROL_REG = PF1_BAR1_CONTROL; + localparam [5:0] PF1_BAR2_APERTURE_SIZE_REG = PF1_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_BAR2_CONTROL_REG = PF1_BAR2_CONTROL; + localparam [4:0] PF1_BAR3_APERTURE_SIZE_REG = PF1_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_BAR3_CONTROL_REG = PF1_BAR3_CONTROL; + localparam [5:0] PF1_BAR4_APERTURE_SIZE_REG = PF1_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_BAR4_CONTROL_REG = PF1_BAR4_CONTROL; + localparam [4:0] PF1_BAR5_APERTURE_SIZE_REG = PF1_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_BAR5_CONTROL_REG = PF1_BAR5_CONTROL; + localparam [7:0] PF1_CAPABILITY_POINTER_REG = PF1_CAPABILITY_POINTER; + localparam [23:0] PF1_CLASS_CODE_REG = PF1_CLASS_CODE; + localparam [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF1_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF1_DSN_CAP_NEXTPTR_REG = PF1_DSN_CAP_NEXTPTR; + localparam [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE_REG = PF1_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF1_EXPANSION_ROM_ENABLE_REG = PF1_EXPANSION_ROM_ENABLE; + localparam [2:0] PF1_INTERRUPT_PIN_REG = PF1_INTERRUPT_PIN; + localparam [7:0] PF1_MSIX_CAP_NEXTPTR_REG = PF1_MSIX_CAP_NEXTPTR; + localparam [2:0] PF1_MSIX_CAP_PBA_BIR_REG = PF1_MSIX_CAP_PBA_BIR; + localparam [28:0] PF1_MSIX_CAP_PBA_OFFSET_REG = PF1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF1_MSIX_CAP_TABLE_BIR_REG = PF1_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF1_MSIX_CAP_TABLE_OFFSET_REG = PF1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF1_MSIX_CAP_TABLE_SIZE_REG = PF1_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF1_MSI_CAP_MULTIMSGCAP_REG = PF1_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF1_MSI_CAP_NEXTPTR_REG = PF1_MSI_CAP_NEXTPTR; + localparam [40:1] PF1_MSI_CAP_PERVECMASKCAP_REG = PF1_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF1_PCIE_CAP_NEXTPTR_REG = PF1_PCIE_CAP_NEXTPTR; + localparam [7:0] PF1_PM_CAP_NEXTPTR_REG = PF1_PM_CAP_NEXTPTR; + localparam [40:1] PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE_REG = PF1_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR0_CONTROL_REG = PF1_SRIOV_BAR0_CONTROL; + localparam [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE_REG = PF1_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR1_CONTROL_REG = PF1_SRIOV_BAR1_CONTROL; + localparam [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE_REG = PF1_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR2_CONTROL_REG = PF1_SRIOV_BAR2_CONTROL; + localparam [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE_REG = PF1_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR3_CONTROL_REG = PF1_SRIOV_BAR3_CONTROL; + localparam [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE_REG = PF1_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR4_CONTROL_REG = PF1_SRIOV_BAR4_CONTROL; + localparam [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE_REG = PF1_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR5_CONTROL_REG = PF1_SRIOV_BAR5_CONTROL; + localparam [15:0] PF1_SRIOV_CAP_INITIAL_VF_REG = PF1_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF1_SRIOV_CAP_NEXTPTR_REG = PF1_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF1_SRIOV_CAP_TOTAL_VF_REG = PF1_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF1_SRIOV_CAP_VER_REG = PF1_SRIOV_CAP_VER; + localparam [15:0] PF1_SRIOV_FIRST_VF_OFFSET_REG = PF1_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF1_SRIOV_FUNC_DEP_LINK_REG = PF1_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF1_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF1_SRIOV_VF_DEVICE_ID_REG = PF1_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF1_TPHR_CAP_NEXTPTR_REG = PF1_TPHR_CAP_NEXTPTR; + localparam [2:0] PF1_TPHR_CAP_ST_MODE_SEL_REG = PF1_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] PF2_AER_CAP_NEXTPTR_REG = PF2_AER_CAP_NEXTPTR; + localparam [11:0] PF2_ARI_CAP_NEXTPTR_REG = PF2_ARI_CAP_NEXTPTR; + localparam [7:0] PF2_ARI_CAP_NEXT_FUNC_REG = PF2_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF2_BAR0_APERTURE_SIZE_REG = PF2_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_BAR0_CONTROL_REG = PF2_BAR0_CONTROL; + localparam [4:0] PF2_BAR1_APERTURE_SIZE_REG = PF2_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_BAR1_CONTROL_REG = PF2_BAR1_CONTROL; + localparam [5:0] PF2_BAR2_APERTURE_SIZE_REG = PF2_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_BAR2_CONTROL_REG = PF2_BAR2_CONTROL; + localparam [4:0] PF2_BAR3_APERTURE_SIZE_REG = PF2_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_BAR3_CONTROL_REG = PF2_BAR3_CONTROL; + localparam [5:0] PF2_BAR4_APERTURE_SIZE_REG = PF2_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_BAR4_CONTROL_REG = PF2_BAR4_CONTROL; + localparam [4:0] PF2_BAR5_APERTURE_SIZE_REG = PF2_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_BAR5_CONTROL_REG = PF2_BAR5_CONTROL; + localparam [7:0] PF2_CAPABILITY_POINTER_REG = PF2_CAPABILITY_POINTER; + localparam [23:0] PF2_CLASS_CODE_REG = PF2_CLASS_CODE; + localparam [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF2_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF2_DSN_CAP_NEXTPTR_REG = PF2_DSN_CAP_NEXTPTR; + localparam [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE_REG = PF2_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF2_EXPANSION_ROM_ENABLE_REG = PF2_EXPANSION_ROM_ENABLE; + localparam [2:0] PF2_INTERRUPT_PIN_REG = PF2_INTERRUPT_PIN; + localparam [7:0] PF2_MSIX_CAP_NEXTPTR_REG = PF2_MSIX_CAP_NEXTPTR; + localparam [2:0] PF2_MSIX_CAP_PBA_BIR_REG = PF2_MSIX_CAP_PBA_BIR; + localparam [28:0] PF2_MSIX_CAP_PBA_OFFSET_REG = PF2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF2_MSIX_CAP_TABLE_BIR_REG = PF2_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF2_MSIX_CAP_TABLE_OFFSET_REG = PF2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF2_MSIX_CAP_TABLE_SIZE_REG = PF2_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF2_MSI_CAP_MULTIMSGCAP_REG = PF2_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF2_MSI_CAP_NEXTPTR_REG = PF2_MSI_CAP_NEXTPTR; + localparam [40:1] PF2_MSI_CAP_PERVECMASKCAP_REG = PF2_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF2_PCIE_CAP_NEXTPTR_REG = PF2_PCIE_CAP_NEXTPTR; + localparam [7:0] PF2_PM_CAP_NEXTPTR_REG = PF2_PM_CAP_NEXTPTR; + localparam [40:1] PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE_REG = PF2_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR0_CONTROL_REG = PF2_SRIOV_BAR0_CONTROL; + localparam [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE_REG = PF2_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR1_CONTROL_REG = PF2_SRIOV_BAR1_CONTROL; + localparam [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE_REG = PF2_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR2_CONTROL_REG = PF2_SRIOV_BAR2_CONTROL; + localparam [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE_REG = PF2_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR3_CONTROL_REG = PF2_SRIOV_BAR3_CONTROL; + localparam [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE_REG = PF2_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR4_CONTROL_REG = PF2_SRIOV_BAR4_CONTROL; + localparam [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE_REG = PF2_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR5_CONTROL_REG = PF2_SRIOV_BAR5_CONTROL; + localparam [15:0] PF2_SRIOV_CAP_INITIAL_VF_REG = PF2_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF2_SRIOV_CAP_NEXTPTR_REG = PF2_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF2_SRIOV_CAP_TOTAL_VF_REG = PF2_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF2_SRIOV_CAP_VER_REG = PF2_SRIOV_CAP_VER; + localparam [15:0] PF2_SRIOV_FIRST_VF_OFFSET_REG = PF2_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF2_SRIOV_FUNC_DEP_LINK_REG = PF2_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF2_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF2_SRIOV_VF_DEVICE_ID_REG = PF2_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF2_TPHR_CAP_NEXTPTR_REG = PF2_TPHR_CAP_NEXTPTR; + localparam [2:0] PF2_TPHR_CAP_ST_MODE_SEL_REG = PF2_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] PF3_AER_CAP_NEXTPTR_REG = PF3_AER_CAP_NEXTPTR; + localparam [11:0] PF3_ARI_CAP_NEXTPTR_REG = PF3_ARI_CAP_NEXTPTR; + localparam [7:0] PF3_ARI_CAP_NEXT_FUNC_REG = PF3_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF3_BAR0_APERTURE_SIZE_REG = PF3_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_BAR0_CONTROL_REG = PF3_BAR0_CONTROL; + localparam [4:0] PF3_BAR1_APERTURE_SIZE_REG = PF3_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_BAR1_CONTROL_REG = PF3_BAR1_CONTROL; + localparam [5:0] PF3_BAR2_APERTURE_SIZE_REG = PF3_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_BAR2_CONTROL_REG = PF3_BAR2_CONTROL; + localparam [4:0] PF3_BAR3_APERTURE_SIZE_REG = PF3_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_BAR3_CONTROL_REG = PF3_BAR3_CONTROL; + localparam [5:0] PF3_BAR4_APERTURE_SIZE_REG = PF3_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_BAR4_CONTROL_REG = PF3_BAR4_CONTROL; + localparam [4:0] PF3_BAR5_APERTURE_SIZE_REG = PF3_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_BAR5_CONTROL_REG = PF3_BAR5_CONTROL; + localparam [7:0] PF3_CAPABILITY_POINTER_REG = PF3_CAPABILITY_POINTER; + localparam [23:0] PF3_CLASS_CODE_REG = PF3_CLASS_CODE; + localparam [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF3_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF3_DSN_CAP_NEXTPTR_REG = PF3_DSN_CAP_NEXTPTR; + localparam [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE_REG = PF3_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF3_EXPANSION_ROM_ENABLE_REG = PF3_EXPANSION_ROM_ENABLE; + localparam [2:0] PF3_INTERRUPT_PIN_REG = PF3_INTERRUPT_PIN; + localparam [7:0] PF3_MSIX_CAP_NEXTPTR_REG = PF3_MSIX_CAP_NEXTPTR; + localparam [2:0] PF3_MSIX_CAP_PBA_BIR_REG = PF3_MSIX_CAP_PBA_BIR; + localparam [28:0] PF3_MSIX_CAP_PBA_OFFSET_REG = PF3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF3_MSIX_CAP_TABLE_BIR_REG = PF3_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF3_MSIX_CAP_TABLE_OFFSET_REG = PF3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF3_MSIX_CAP_TABLE_SIZE_REG = PF3_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF3_MSI_CAP_MULTIMSGCAP_REG = PF3_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF3_MSI_CAP_NEXTPTR_REG = PF3_MSI_CAP_NEXTPTR; + localparam [40:1] PF3_MSI_CAP_PERVECMASKCAP_REG = PF3_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF3_PCIE_CAP_NEXTPTR_REG = PF3_PCIE_CAP_NEXTPTR; + localparam [7:0] PF3_PM_CAP_NEXTPTR_REG = PF3_PM_CAP_NEXTPTR; + localparam [40:1] PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE_REG = PF3_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR0_CONTROL_REG = PF3_SRIOV_BAR0_CONTROL; + localparam [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE_REG = PF3_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR1_CONTROL_REG = PF3_SRIOV_BAR1_CONTROL; + localparam [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE_REG = PF3_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR2_CONTROL_REG = PF3_SRIOV_BAR2_CONTROL; + localparam [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE_REG = PF3_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR3_CONTROL_REG = PF3_SRIOV_BAR3_CONTROL; + localparam [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE_REG = PF3_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR4_CONTROL_REG = PF3_SRIOV_BAR4_CONTROL; + localparam [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE_REG = PF3_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR5_CONTROL_REG = PF3_SRIOV_BAR5_CONTROL; + localparam [15:0] PF3_SRIOV_CAP_INITIAL_VF_REG = PF3_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF3_SRIOV_CAP_NEXTPTR_REG = PF3_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF3_SRIOV_CAP_TOTAL_VF_REG = PF3_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF3_SRIOV_CAP_VER_REG = PF3_SRIOV_CAP_VER; + localparam [15:0] PF3_SRIOV_FIRST_VF_OFFSET_REG = PF3_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF3_SRIOV_FUNC_DEP_LINK_REG = PF3_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF3_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF3_SRIOV_VF_DEVICE_ID_REG = PF3_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF3_TPHR_CAP_NEXTPTR_REG = PF3_TPHR_CAP_NEXTPTR; + localparam [2:0] PF3_TPHR_CAP_ST_MODE_SEL_REG = PF3_TPHR_CAP_ST_MODE_SEL; + localparam [40:1] PL_CFG_STATE_ROBUSTNESS_ENABLE_REG = PL_CFG_STATE_ROBUSTNESS_ENABLE; + localparam [40:1] PL_DEEMPH_SOURCE_SELECT_REG = PL_DEEMPH_SOURCE_SELECT; + localparam [40:1] PL_DESKEW_ON_SKIP_IN_GEN12_REG = PL_DESKEW_ON_SKIP_IN_GEN12; + localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3; + localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4; + localparam [40:1] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG = PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2; + localparam [40:1] PL_DISABLE_DC_BALANCE_REG = PL_DISABLE_DC_BALANCE; + localparam [40:1] PL_DISABLE_EI_INFER_IN_L0_REG = PL_DISABLE_EI_INFER_IN_L0; + localparam [40:1] PL_DISABLE_LANE_REVERSAL_REG = PL_DISABLE_LANE_REVERSAL; + localparam [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP_REG = PL_DISABLE_LFSR_UPDATE_ON_SKP; + localparam [40:1] PL_DISABLE_RETRAIN_ON_EB_ERROR_REG = PL_DISABLE_RETRAIN_ON_EB_ERROR; + localparam [40:1] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_FRAMING_ERROR; + localparam [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR; + localparam [40:1] PL_DISABLE_UPCONFIG_CAPABLE_REG = PL_DISABLE_UPCONFIG_CAPABLE; + localparam [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG = PL_EQ_ADAPT_DISABLE_COEFF_CHECK; + localparam [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG = PL_EQ_ADAPT_DISABLE_PRESET_CHECK; + localparam [4:0] PL_EQ_ADAPT_ITER_COUNT_REG = PL_EQ_ADAPT_ITER_COUNT; + localparam [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG = PL_EQ_ADAPT_REJECT_RETRY_COUNT; + localparam [1:0] PL_EQ_BYPASS_PHASE23_REG = PL_EQ_BYPASS_PHASE23; + localparam [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT_REG = PL_EQ_DEFAULT_RX_PRESET_HINT; + localparam [7:0] PL_EQ_DEFAULT_TX_PRESET_REG = PL_EQ_DEFAULT_TX_PRESET; + localparam [40:1] PL_EQ_DISABLE_MISMATCH_CHECK_REG = PL_EQ_DISABLE_MISMATCH_CHECK; + localparam [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0_REG = PL_EQ_RX_ADAPT_EQ_PHASE0; + localparam [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1_REG = PL_EQ_RX_ADAPT_EQ_PHASE1; + localparam [40:1] PL_EQ_SHORT_ADAPT_PHASE_REG = PL_EQ_SHORT_ADAPT_PHASE; + localparam [40:1] PL_EQ_TX_8G_EQ_TS2_ENABLE_REG = PL_EQ_TX_8G_EQ_TS2_ENABLE; + localparam [40:1] PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG = PL_EXIT_LOOPBACK_ON_EI_ENTRY; + localparam [40:1] PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG = PL_INFER_EI_DISABLE_LPBK_ACTIVE; + localparam [40:1] PL_INFER_EI_DISABLE_REC_RC_REG = PL_INFER_EI_DISABLE_REC_RC; + localparam [40:1] PL_INFER_EI_DISABLE_REC_SPD_REG = PL_INFER_EI_DISABLE_REC_SPD; + localparam [31:0] PL_LANE0_EQ_CONTROL_REG = PL_LANE0_EQ_CONTROL; + localparam [31:0] PL_LANE10_EQ_CONTROL_REG = PL_LANE10_EQ_CONTROL; + localparam [31:0] PL_LANE11_EQ_CONTROL_REG = PL_LANE11_EQ_CONTROL; + localparam [31:0] PL_LANE12_EQ_CONTROL_REG = PL_LANE12_EQ_CONTROL; + localparam [31:0] PL_LANE13_EQ_CONTROL_REG = PL_LANE13_EQ_CONTROL; + localparam [31:0] PL_LANE14_EQ_CONTROL_REG = PL_LANE14_EQ_CONTROL; + localparam [31:0] PL_LANE15_EQ_CONTROL_REG = PL_LANE15_EQ_CONTROL; + localparam [31:0] PL_LANE1_EQ_CONTROL_REG = PL_LANE1_EQ_CONTROL; + localparam [31:0] PL_LANE2_EQ_CONTROL_REG = PL_LANE2_EQ_CONTROL; + localparam [31:0] PL_LANE3_EQ_CONTROL_REG = PL_LANE3_EQ_CONTROL; + localparam [31:0] PL_LANE4_EQ_CONTROL_REG = PL_LANE4_EQ_CONTROL; + localparam [31:0] PL_LANE5_EQ_CONTROL_REG = PL_LANE5_EQ_CONTROL; + localparam [31:0] PL_LANE6_EQ_CONTROL_REG = PL_LANE6_EQ_CONTROL; + localparam [31:0] PL_LANE7_EQ_CONTROL_REG = PL_LANE7_EQ_CONTROL; + localparam [31:0] PL_LANE8_EQ_CONTROL_REG = PL_LANE8_EQ_CONTROL; + localparam [31:0] PL_LANE9_EQ_CONTROL_REG = PL_LANE9_EQ_CONTROL; + localparam [3:0] PL_LINK_CAP_MAX_LINK_SPEED_REG = PL_LINK_CAP_MAX_LINK_SPEED; + localparam [4:0] PL_LINK_CAP_MAX_LINK_WIDTH_REG = PL_LINK_CAP_MAX_LINK_WIDTH; + localparam [7:0] PL_N_FTS_REG = PL_N_FTS; + localparam [40:1] PL_QUIESCE_GUARANTEE_DISABLE_REG = PL_QUIESCE_GUARANTEE_DISABLE; + localparam [40:1] PL_REDO_EQ_SOURCE_SELECT_REG = PL_REDO_EQ_SOURCE_SELECT; + localparam [7:0] PL_REPORT_ALL_PHY_ERRORS_REG = PL_REPORT_ALL_PHY_ERRORS; + localparam [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS_REG = PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS; + localparam [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3_REG = PL_RX_ADAPT_TIMER_CLWS_GEN3; + localparam [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4_REG = PL_RX_ADAPT_TIMER_CLWS_GEN4; + localparam [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS_REG = PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS; + localparam [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3_REG = PL_RX_ADAPT_TIMER_RRL_GEN3; + localparam [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4_REG = PL_RX_ADAPT_TIMER_RRL_GEN4; + localparam [1:0] PL_RX_L0S_EXIT_TO_RECOVERY_REG = PL_RX_L0S_EXIT_TO_RECOVERY; + localparam [1:0] PL_SIM_FAST_LINK_TRAINING_REG = PL_SIM_FAST_LINK_TRAINING; + localparam [40:1] PL_SRIS_ENABLE_REG = PL_SRIS_ENABLE; + localparam [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC_REG = PL_SRIS_SKPOS_GEN_SPD_VEC; + localparam [6:0] PL_SRIS_SKPOS_REC_SPD_VEC_REG = PL_SRIS_SKPOS_REC_SPD_VEC; + localparam [40:1] PL_UPSTREAM_FACING_REG = PL_UPSTREAM_FACING; + localparam [15:0] PL_USER_SPARE_REG = PL_USER_SPARE; + localparam [15:0] PM_ASPML0S_TIMEOUT_REG = PM_ASPML0S_TIMEOUT; + localparam [19:0] PM_ASPML1_ENTRY_DELAY_REG = PM_ASPML1_ENTRY_DELAY; + localparam [40:1] PM_ENABLE_L23_ENTRY_REG = PM_ENABLE_L23_ENTRY; + localparam [40:1] PM_ENABLE_SLOT_POWER_CAPTURE_REG = PM_ENABLE_SLOT_POWER_CAPTURE; + localparam [31:0] PM_L1_REENTRY_DELAY_REG = PM_L1_REENTRY_DELAY; + localparam [19:0] PM_PME_SERVICE_TIMEOUT_DELAY_REG = PM_PME_SERVICE_TIMEOUT_DELAY; + localparam [15:0] PM_PME_TURNOFF_ACK_DELAY_REG = PM_PME_TURNOFF_ACK_DELAY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [31:0] SIM_JTAG_IDCODE_REG = SIM_JTAG_IDCODE; + localparam [24:1] SIM_VERSION_REG = SIM_VERSION; + localparam [40:1] SPARE_BIT0_REG = SPARE_BIT0; + localparam [0:0] SPARE_BIT1_REG = SPARE_BIT1; + localparam [0:0] SPARE_BIT2_REG = SPARE_BIT2; + localparam [40:1] SPARE_BIT3_REG = SPARE_BIT3; + localparam [0:0] SPARE_BIT4_REG = SPARE_BIT4; + localparam [0:0] SPARE_BIT5_REG = SPARE_BIT5; + localparam [0:0] SPARE_BIT6_REG = SPARE_BIT6; + localparam [0:0] SPARE_BIT7_REG = SPARE_BIT7; + localparam [0:0] SPARE_BIT8_REG = SPARE_BIT8; + localparam [7:0] SPARE_BYTE0_REG = SPARE_BYTE0; + localparam [7:0] SPARE_BYTE1_REG = SPARE_BYTE1; + localparam [7:0] SPARE_BYTE2_REG = SPARE_BYTE2; + localparam [7:0] SPARE_BYTE3_REG = SPARE_BYTE3; + localparam [31:0] SPARE_WORD0_REG = SPARE_WORD0; + localparam [31:0] SPARE_WORD1_REG = SPARE_WORD1; + localparam [31:0] SPARE_WORD2_REG = SPARE_WORD2; + localparam [31:0] SPARE_WORD3_REG = SPARE_WORD3; + localparam [3:0] SRIOV_CAP_ENABLE_REG = SRIOV_CAP_ENABLE; + localparam [40:1] TL2CFG_IF_PARITY_CHK_REG = TL2CFG_IF_PARITY_CHK; + localparam [1:0] TL_COMPLETION_RAM_NUM_TLPS_REG = TL_COMPLETION_RAM_NUM_TLPS; + localparam [1:0] TL_COMPLETION_RAM_SIZE_REG = TL_COMPLETION_RAM_SIZE; + localparam [11:0] TL_CREDITS_CD_REG = TL_CREDITS_CD; + localparam [7:0] TL_CREDITS_CH_REG = TL_CREDITS_CH; + localparam [11:0] TL_CREDITS_NPD_REG = TL_CREDITS_NPD; + localparam [7:0] TL_CREDITS_NPH_REG = TL_CREDITS_NPH; + localparam [11:0] TL_CREDITS_PD_REG = TL_CREDITS_PD; + localparam [7:0] TL_CREDITS_PH_REG = TL_CREDITS_PH; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_REG = TL_FC_UPDATE_MIN_INTERVAL_TIME; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_REG = TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT; + localparam [1:0] TL_PF_ENABLE_REG_REG = TL_PF_ENABLE_REG; + localparam [0:0] TL_POSTED_RAM_SIZE_REG = TL_POSTED_RAM_SIZE; + localparam [40:1] TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG = TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG = TL_RX_COMPLETION_TO_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG = TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE; + localparam [40:1] TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG = TL_RX_POSTED_FROM_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG = TL_RX_POSTED_TO_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG = TL_RX_POSTED_TO_RAM_WRITE_PIPELINE; + localparam [40:1] TL_TX_MUX_STRICT_PRIORITY_REG = TL_TX_MUX_STRICT_PRIORITY; + localparam [40:1] TL_TX_TLP_STRADDLE_ENABLE_REG = TL_TX_TLP_STRADDLE_ENABLE; + localparam [40:1] TL_TX_TLP_TERMINATE_PARITY_REG = TL_TX_TLP_TERMINATE_PARITY; + localparam [15:0] TL_USER_SPARE_REG = TL_USER_SPARE; + localparam [40:1] TPH_FROM_RAM_PIPELINE_REG = TPH_FROM_RAM_PIPELINE; + localparam [40:1] TPH_TO_RAM_PIPELINE_REG = TPH_TO_RAM_PIPELINE; + localparam [7:0] VF0_CAPABILITY_POINTER_REG = VF0_CAPABILITY_POINTER; + localparam [11:0] VFG0_ARI_CAP_NEXTPTR_REG = VFG0_ARI_CAP_NEXTPTR; + localparam [7:0] VFG0_MSIX_CAP_NEXTPTR_REG = VFG0_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG0_MSIX_CAP_PBA_BIR_REG = VFG0_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG0_MSIX_CAP_PBA_OFFSET_REG = VFG0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG0_MSIX_CAP_TABLE_BIR_REG = VFG0_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG0_MSIX_CAP_TABLE_OFFSET_REG = VFG0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG0_MSIX_CAP_TABLE_SIZE_REG = VFG0_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG0_PCIE_CAP_NEXTPTR_REG = VFG0_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG0_TPHR_CAP_NEXTPTR_REG = VFG0_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG0_TPHR_CAP_ST_MODE_SEL_REG = VFG0_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG1_ARI_CAP_NEXTPTR_REG = VFG1_ARI_CAP_NEXTPTR; + localparam [7:0] VFG1_MSIX_CAP_NEXTPTR_REG = VFG1_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG1_MSIX_CAP_PBA_BIR_REG = VFG1_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG1_MSIX_CAP_PBA_OFFSET_REG = VFG1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG1_MSIX_CAP_TABLE_BIR_REG = VFG1_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG1_MSIX_CAP_TABLE_OFFSET_REG = VFG1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG1_MSIX_CAP_TABLE_SIZE_REG = VFG1_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG1_PCIE_CAP_NEXTPTR_REG = VFG1_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG1_TPHR_CAP_NEXTPTR_REG = VFG1_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG1_TPHR_CAP_ST_MODE_SEL_REG = VFG1_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG2_ARI_CAP_NEXTPTR_REG = VFG2_ARI_CAP_NEXTPTR; + localparam [7:0] VFG2_MSIX_CAP_NEXTPTR_REG = VFG2_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG2_MSIX_CAP_PBA_BIR_REG = VFG2_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG2_MSIX_CAP_PBA_OFFSET_REG = VFG2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG2_MSIX_CAP_TABLE_BIR_REG = VFG2_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG2_MSIX_CAP_TABLE_OFFSET_REG = VFG2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG2_MSIX_CAP_TABLE_SIZE_REG = VFG2_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG2_PCIE_CAP_NEXTPTR_REG = VFG2_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG2_TPHR_CAP_NEXTPTR_REG = VFG2_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG2_TPHR_CAP_ST_MODE_SEL_REG = VFG2_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG3_ARI_CAP_NEXTPTR_REG = VFG3_ARI_CAP_NEXTPTR; + localparam [7:0] VFG3_MSIX_CAP_NEXTPTR_REG = VFG3_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG3_MSIX_CAP_PBA_BIR_REG = VFG3_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG3_MSIX_CAP_PBA_OFFSET_REG = VFG3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG3_MSIX_CAP_TABLE_BIR_REG = VFG3_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG3_MSIX_CAP_TABLE_OFFSET_REG = VFG3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG3_MSIX_CAP_TABLE_SIZE_REG = VFG3_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG3_PCIE_CAP_NEXTPTR_REG = VFG3_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG3_TPHR_CAP_NEXTPTR_REG = VFG3_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG3_TPHR_CAP_ST_MODE_SEL_REG = VFG3_TPHR_CAP_ST_MODE_SEL; +`endif + + localparam [40:1] TEST_MODE_PIN_CHAR_REG = "FALSE"; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CFGERRCOROUT_out; + wire CFGERRFATALOUT_out; + wire CFGERRNONFATALOUT_out; + wire CFGEXTREADRECEIVED_out; + wire CFGEXTWRITERECEIVED_out; + wire CFGHOTRESETOUT_out; + wire CFGINTERRUPTMSIFAIL_out; + wire CFGINTERRUPTMSIMASKUPDATE_out; + wire CFGINTERRUPTMSISENT_out; + wire CFGINTERRUPTMSIXVECPENDINGSTATUS_out; + wire CFGINTERRUPTSENT_out; + wire CFGLOCALERRORVALID_out; + wire CFGLTRENABLE_out; + wire CFGMGMTREADWRITEDONE_out; + wire CFGMSGRECEIVED_out; + wire CFGMSGTRANSMITDONE_out; + wire CFGMSIXRAMREADENABLE_out; + wire CFGPHYLINKDOWN_out; + wire CFGPLSTATUSCHANGE_out; + wire CFGPOWERSTATECHANGEINTERRUPT_out; + wire CFGTPHRAMREADENABLE_out; + wire CONFMCAPDESIGNSWITCH_out; + wire CONFMCAPEOS_out; + wire CONFMCAPINUSEBYPCIE_out; + wire CONFREQREADY_out; + wire CONFRESPVALID_out; + wire DRPRDY_out; + wire MAXISCQTLAST_out; + wire MAXISCQTVALID_out; + wire MAXISRCTLAST_out; + wire MAXISRCTVALID_out; + wire MIREPLAYRAMREADENABLE0_out; + wire MIREPLAYRAMREADENABLE1_out; + wire MIREPLAYRAMWRITEENABLE0_out; + wire MIREPLAYRAMWRITEENABLE1_out; + wire MIRXPOSTEDREQUESTRAMREADENABLE0_out; + wire MIRXPOSTEDREQUESTRAMREADENABLE1_out; + wire MIRXPOSTEDREQUESTRAMWRITEENABLE0_out; + wire MIRXPOSTEDREQUESTRAMWRITEENABLE1_out; + wire PCIEPERST0B_out; + wire PCIEPERST1B_out; + wire PCIERQSEQNUMVLD0_out; + wire PCIERQSEQNUMVLD1_out; + wire PCIERQTAGVLD0_out; + wire PCIERQTAGVLD1_out; + wire PIPERX00POLARITY_out; + wire PIPERX01POLARITY_out; + wire PIPERX02POLARITY_out; + wire PIPERX03POLARITY_out; + wire PIPERX04POLARITY_out; + wire PIPERX05POLARITY_out; + wire PIPERX06POLARITY_out; + wire PIPERX07POLARITY_out; + wire PIPERX08POLARITY_out; + wire PIPERX09POLARITY_out; + wire PIPERX10POLARITY_out; + wire PIPERX11POLARITY_out; + wire PIPERX12POLARITY_out; + wire PIPERX13POLARITY_out; + wire PIPERX14POLARITY_out; + wire PIPERX15POLARITY_out; + wire PIPETX00COMPLIANCE_out; + wire PIPETX00DATAVALID_out; + wire PIPETX00ELECIDLE_out; + wire PIPETX00STARTBLOCK_out; + wire PIPETX01COMPLIANCE_out; + wire PIPETX01DATAVALID_out; + wire PIPETX01ELECIDLE_out; + wire PIPETX01STARTBLOCK_out; + wire PIPETX02COMPLIANCE_out; + wire PIPETX02DATAVALID_out; + wire PIPETX02ELECIDLE_out; + wire PIPETX02STARTBLOCK_out; + wire PIPETX03COMPLIANCE_out; + wire PIPETX03DATAVALID_out; + wire PIPETX03ELECIDLE_out; + wire PIPETX03STARTBLOCK_out; + wire PIPETX04COMPLIANCE_out; + wire PIPETX04DATAVALID_out; + wire PIPETX04ELECIDLE_out; + wire PIPETX04STARTBLOCK_out; + wire PIPETX05COMPLIANCE_out; + wire PIPETX05DATAVALID_out; + wire PIPETX05ELECIDLE_out; + wire PIPETX05STARTBLOCK_out; + wire PIPETX06COMPLIANCE_out; + wire PIPETX06DATAVALID_out; + wire PIPETX06ELECIDLE_out; + wire PIPETX06STARTBLOCK_out; + wire PIPETX07COMPLIANCE_out; + wire PIPETX07DATAVALID_out; + wire PIPETX07ELECIDLE_out; + wire PIPETX07STARTBLOCK_out; + wire PIPETX08COMPLIANCE_out; + wire PIPETX08DATAVALID_out; + wire PIPETX08ELECIDLE_out; + wire PIPETX08STARTBLOCK_out; + wire PIPETX09COMPLIANCE_out; + wire PIPETX09DATAVALID_out; + wire PIPETX09ELECIDLE_out; + wire PIPETX09STARTBLOCK_out; + wire PIPETX10COMPLIANCE_out; + wire PIPETX10DATAVALID_out; + wire PIPETX10ELECIDLE_out; + wire PIPETX10STARTBLOCK_out; + wire PIPETX11COMPLIANCE_out; + wire PIPETX11DATAVALID_out; + wire PIPETX11ELECIDLE_out; + wire PIPETX11STARTBLOCK_out; + wire PIPETX12COMPLIANCE_out; + wire PIPETX12DATAVALID_out; + wire PIPETX12ELECIDLE_out; + wire PIPETX12STARTBLOCK_out; + wire PIPETX13COMPLIANCE_out; + wire PIPETX13DATAVALID_out; + wire PIPETX13ELECIDLE_out; + wire PIPETX13STARTBLOCK_out; + wire PIPETX14COMPLIANCE_out; + wire PIPETX14DATAVALID_out; + wire PIPETX14ELECIDLE_out; + wire PIPETX14STARTBLOCK_out; + wire PIPETX15COMPLIANCE_out; + wire PIPETX15DATAVALID_out; + wire PIPETX15ELECIDLE_out; + wire PIPETX15STARTBLOCK_out; + wire PIPETXDEEMPH_out; + wire PIPETXRCVRDET_out; + wire PIPETXRESET_out; + wire PIPETXSWING_out; + wire PLEQINPROGRESS_out; + wire PLGEN34EQMISMATCH_out; + wire PMVOUT_out; + wire [11:0] CFGFCCPLD_out; + wire [11:0] CFGFCNPD_out; + wire [11:0] CFGFCPD_out; + wire [11:0] CFGFUNCTIONPOWERSTATE_out; + wire [11:0] CFGINTERRUPTMSIMMENABLE_out; + wire [11:0] CFGTPHRAMADDRESS_out; + wire [11:0] CFGTPHSTMODE_out; + wire [127:0] MIREPLAYRAMWRITEDATA0_out; + wire [127:0] MIREPLAYRAMWRITEDATA1_out; + wire [12:0] CFGMSIXRAMADDRESS_out; + wire [143:0] MIRXCOMPLETIONRAMWRITEDATA0_out; + wire [143:0] MIRXCOMPLETIONRAMWRITEDATA1_out; + wire [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0_out; + wire [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1_out; + wire [15:0] CFGFUNCTIONSTATUS_out; + wire [15:0] DRPDO_out; + wire [172:0] SCANOUT_out; + wire [1:0] CFGCURRENTSPEED_out; + wire [1:0] CFGLINKPOWERSTATE_out; + wire [1:0] CFGMAXPAYLOAD_out; + wire [1:0] CFGOBFFENABLE_out; + wire [1:0] CFGPHYLINKSTATUS_out; + wire [1:0] CFGRXPMSTATE_out; + wire [1:0] CFGTXPMSTATE_out; + wire [1:0] MIRXCOMPLETIONRAMREADENABLE0_out; + wire [1:0] MIRXCOMPLETIONRAMREADENABLE1_out; + wire [1:0] MIRXCOMPLETIONRAMWRITEENABLE0_out; + wire [1:0] MIRXCOMPLETIONRAMWRITEENABLE1_out; + wire [1:0] PIPERX00EQCONTROL_out; + wire [1:0] PIPERX01EQCONTROL_out; + wire [1:0] PIPERX02EQCONTROL_out; + wire [1:0] PIPERX03EQCONTROL_out; + wire [1:0] PIPERX04EQCONTROL_out; + wire [1:0] PIPERX05EQCONTROL_out; + wire [1:0] PIPERX06EQCONTROL_out; + wire [1:0] PIPERX07EQCONTROL_out; + wire [1:0] PIPERX08EQCONTROL_out; + wire [1:0] PIPERX09EQCONTROL_out; + wire [1:0] PIPERX10EQCONTROL_out; + wire [1:0] PIPERX11EQCONTROL_out; + wire [1:0] PIPERX12EQCONTROL_out; + wire [1:0] PIPERX13EQCONTROL_out; + wire [1:0] PIPERX14EQCONTROL_out; + wire [1:0] PIPERX15EQCONTROL_out; + wire [1:0] PIPETX00CHARISK_out; + wire [1:0] PIPETX00EQCONTROL_out; + wire [1:0] PIPETX00POWERDOWN_out; + wire [1:0] PIPETX00SYNCHEADER_out; + wire [1:0] PIPETX01CHARISK_out; + wire [1:0] PIPETX01EQCONTROL_out; + wire [1:0] PIPETX01POWERDOWN_out; + wire [1:0] PIPETX01SYNCHEADER_out; + wire [1:0] PIPETX02CHARISK_out; + wire [1:0] PIPETX02EQCONTROL_out; + wire [1:0] PIPETX02POWERDOWN_out; + wire [1:0] PIPETX02SYNCHEADER_out; + wire [1:0] PIPETX03CHARISK_out; + wire [1:0] PIPETX03EQCONTROL_out; + wire [1:0] PIPETX03POWERDOWN_out; + wire [1:0] PIPETX03SYNCHEADER_out; + wire [1:0] PIPETX04CHARISK_out; + wire [1:0] PIPETX04EQCONTROL_out; + wire [1:0] PIPETX04POWERDOWN_out; + wire [1:0] PIPETX04SYNCHEADER_out; + wire [1:0] PIPETX05CHARISK_out; + wire [1:0] PIPETX05EQCONTROL_out; + wire [1:0] PIPETX05POWERDOWN_out; + wire [1:0] PIPETX05SYNCHEADER_out; + wire [1:0] PIPETX06CHARISK_out; + wire [1:0] PIPETX06EQCONTROL_out; + wire [1:0] PIPETX06POWERDOWN_out; + wire [1:0] PIPETX06SYNCHEADER_out; + wire [1:0] PIPETX07CHARISK_out; + wire [1:0] PIPETX07EQCONTROL_out; + wire [1:0] PIPETX07POWERDOWN_out; + wire [1:0] PIPETX07SYNCHEADER_out; + wire [1:0] PIPETX08CHARISK_out; + wire [1:0] PIPETX08EQCONTROL_out; + wire [1:0] PIPETX08POWERDOWN_out; + wire [1:0] PIPETX08SYNCHEADER_out; + wire [1:0] PIPETX09CHARISK_out; + wire [1:0] PIPETX09EQCONTROL_out; + wire [1:0] PIPETX09POWERDOWN_out; + wire [1:0] PIPETX09SYNCHEADER_out; + wire [1:0] PIPETX10CHARISK_out; + wire [1:0] PIPETX10EQCONTROL_out; + wire [1:0] PIPETX10POWERDOWN_out; + wire [1:0] PIPETX10SYNCHEADER_out; + wire [1:0] PIPETX11CHARISK_out; + wire [1:0] PIPETX11EQCONTROL_out; + wire [1:0] PIPETX11POWERDOWN_out; + wire [1:0] PIPETX11SYNCHEADER_out; + wire [1:0] PIPETX12CHARISK_out; + wire [1:0] PIPETX12EQCONTROL_out; + wire [1:0] PIPETX12POWERDOWN_out; + wire [1:0] PIPETX12SYNCHEADER_out; + wire [1:0] PIPETX13CHARISK_out; + wire [1:0] PIPETX13EQCONTROL_out; + wire [1:0] PIPETX13POWERDOWN_out; + wire [1:0] PIPETX13SYNCHEADER_out; + wire [1:0] PIPETX14CHARISK_out; + wire [1:0] PIPETX14EQCONTROL_out; + wire [1:0] PIPETX14POWERDOWN_out; + wire [1:0] PIPETX14SYNCHEADER_out; + wire [1:0] PIPETX15CHARISK_out; + wire [1:0] PIPETX15EQCONTROL_out; + wire [1:0] PIPETX15POWERDOWN_out; + wire [1:0] PIPETX15SYNCHEADER_out; + wire [1:0] PIPETXRATE_out; + wire [1:0] PLEQPHASE_out; + wire [255:0] DBGDATA0OUT_out; + wire [255:0] DBGDATA1OUT_out; + wire [255:0] MAXISCQTDATA_out; + wire [255:0] MAXISRCTDATA_out; + wire [2:0] CFGMAXREADREQ_out; + wire [2:0] CFGNEGOTIATEDWIDTH_out; + wire [2:0] PIPETXMARGIN_out; + wire [31:0] CFGEXTWRITEDATA_out; + wire [31:0] CFGINTERRUPTMSIDATA_out; + wire [31:0] CFGMGMTREADDATA_out; + wire [31:0] CONFRESPRDATA_out; + wire [31:0] DBGCTRL0OUT_out; + wire [31:0] DBGCTRL1OUT_out; + wire [31:0] PIPETX00DATA_out; + wire [31:0] PIPETX01DATA_out; + wire [31:0] PIPETX02DATA_out; + wire [31:0] PIPETX03DATA_out; + wire [31:0] PIPETX04DATA_out; + wire [31:0] PIPETX05DATA_out; + wire [31:0] PIPETX06DATA_out; + wire [31:0] PIPETX07DATA_out; + wire [31:0] PIPETX08DATA_out; + wire [31:0] PIPETX09DATA_out; + wire [31:0] PIPETX10DATA_out; + wire [31:0] PIPETX11DATA_out; + wire [31:0] PIPETX12DATA_out; + wire [31:0] PIPETX13DATA_out; + wire [31:0] PIPETX14DATA_out; + wire [31:0] PIPETX15DATA_out; + wire [31:0] USERSPAREOUT_out; + wire [35:0] CFGMSIXRAMWRITEDATA_out; + wire [35:0] CFGTPHRAMWRITEDATA_out; + wire [3:0] CFGEXTWRITEBYTEENABLE_out; + wire [3:0] CFGFLRINPROCESS_out; + wire [3:0] CFGINTERRUPTMSIENABLE_out; + wire [3:0] CFGINTERRUPTMSIXENABLE_out; + wire [3:0] CFGINTERRUPTMSIXMASK_out; + wire [3:0] CFGMSIXRAMWRITEBYTEENABLE_out; + wire [3:0] CFGRCBSTATUS_out; + wire [3:0] CFGTPHRAMWRITEBYTEENABLE_out; + wire [3:0] CFGTPHREQUESTERENABLE_out; + wire [3:0] PCIERQTAGAV_out; + wire [3:0] PCIETFCNPDAV_out; + wire [3:0] PCIETFCNPHAV_out; + wire [3:0] PIPERXEQLPTXPRESET_out; + wire [3:0] SAXISCCTREADY_out; + wire [3:0] SAXISRQTREADY_out; + wire [4:0] CFGLOCALERROROUT_out; + wire [4:0] CFGMSGRECEIVEDTYPE_out; + wire [5:0] CFGLTSSMSTATE_out; + wire [5:0] PCIECQNPREQCOUNT_out; + wire [5:0] PCIERQSEQNUM0_out; + wire [5:0] PCIERQSEQNUM1_out; + wire [5:0] PIPERXEQLPLFFS_out; + wire [5:0] PIPETX00EQDEEMPH_out; + wire [5:0] PIPETX01EQDEEMPH_out; + wire [5:0] PIPETX02EQDEEMPH_out; + wire [5:0] PIPETX03EQDEEMPH_out; + wire [5:0] PIPETX04EQDEEMPH_out; + wire [5:0] PIPETX05EQDEEMPH_out; + wire [5:0] PIPETX06EQDEEMPH_out; + wire [5:0] PIPETX07EQDEEMPH_out; + wire [5:0] PIPETX08EQDEEMPH_out; + wire [5:0] PIPETX09EQDEEMPH_out; + wire [5:0] PIPETX10EQDEEMPH_out; + wire [5:0] PIPETX11EQDEEMPH_out; + wire [5:0] PIPETX12EQDEEMPH_out; + wire [5:0] PIPETX13EQDEEMPH_out; + wire [5:0] PIPETX14EQDEEMPH_out; + wire [5:0] PIPETX15EQDEEMPH_out; + wire [74:0] MAXISRCTUSER_out; + wire [7:0] AXIUSEROUT_out; + wire [7:0] CFGBUSNUMBER_out; + wire [7:0] CFGEXTFUNCTIONNUMBER_out; + wire [7:0] CFGFCCPLH_out; + wire [7:0] CFGFCNPH_out; + wire [7:0] CFGFCPH_out; + wire [7:0] CFGMSGRECEIVEDDATA_out; + wire [7:0] MAXISCQTKEEP_out; + wire [7:0] MAXISRCTKEEP_out; + wire [7:0] PCIERQTAG0_out; + wire [7:0] PCIERQTAG1_out; + wire [87:0] MAXISCQTUSER_out; + wire [8:0] MIREPLAYRAMADDRESS0_out; + wire [8:0] MIREPLAYRAMADDRESS1_out; + wire [8:0] MIRXCOMPLETIONRAMREADADDRESS0_out; + wire [8:0] MIRXCOMPLETIONRAMREADADDRESS1_out; + wire [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0_out; + wire [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1_out; + wire [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0_out; + wire [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1_out; + wire [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out; + wire [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out; + wire [9:0] CFGEXTREGISTERNUMBER_out; + + wire CFGCONFIGSPACEENABLE_in; + wire CFGERRCORIN_in; + wire CFGERRUNCORIN_in; + wire CFGEXTREADDATAVALID_in; + wire CFGHOTRESETIN_in; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in; + wire CFGINTERRUPTMSITPHPRESENT_in; + wire CFGINTERRUPTMSIXINT_in; + wire CFGLINKTRAININGENABLE_in; + wire CFGMGMTDEBUGACCESS_in; + wire CFGMGMTREAD_in; + wire CFGMGMTWRITE_in; + wire CFGMSGTRANSMIT_in; + wire CFGPMASPML1ENTRYREJECT_in; + wire CFGPMASPMTXL0SENTRYDISABLE_in; + wire CFGPOWERSTATECHANGEACK_in; + wire CFGREQPMTRANSITIONL23READY_in; + wire CFGVFFLRDONE_in; + wire CONFMCAPREQUESTBYCONF_in; + wire CONFREQVALID_in; + wire CORECLKMIREPLAYRAM0_in; + wire CORECLKMIREPLAYRAM1_in; + wire CORECLKMIRXCOMPLETIONRAM0_in; + wire CORECLKMIRXCOMPLETIONRAM1_in; + wire CORECLKMIRXPOSTEDREQUESTRAM0_in; + wire CORECLKMIRXPOSTEDREQUESTRAM1_in; + wire CORECLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire MCAPCLK_in; + wire MCAPPERST0B_in; + wire MCAPPERST1B_in; + wire MGMTRESETN_in; + wire MGMTSTICKYRESETN_in; + wire PCIECQNPUSERCREDITRCVD_in; + wire PCIECQPIPELINEEMPTY_in; + wire PCIEPOSTEDREQDELIVERED_in; + wire PIPECLKEN_in; + wire PIPECLK_in; + wire PIPERESETN_in; + wire PIPERX00DATAVALID_in; + wire PIPERX00ELECIDLE_in; + wire PIPERX00EQDONE_in; + wire PIPERX00EQLPADAPTDONE_in; + wire PIPERX00EQLPLFFSSEL_in; + wire PIPERX00PHYSTATUS_in; + wire PIPERX00VALID_in; + wire PIPERX01DATAVALID_in; + wire PIPERX01ELECIDLE_in; + wire PIPERX01EQDONE_in; + wire PIPERX01EQLPADAPTDONE_in; + wire PIPERX01EQLPLFFSSEL_in; + wire PIPERX01PHYSTATUS_in; + wire PIPERX01VALID_in; + wire PIPERX02DATAVALID_in; + wire PIPERX02ELECIDLE_in; + wire PIPERX02EQDONE_in; + wire PIPERX02EQLPADAPTDONE_in; + wire PIPERX02EQLPLFFSSEL_in; + wire PIPERX02PHYSTATUS_in; + wire PIPERX02VALID_in; + wire PIPERX03DATAVALID_in; + wire PIPERX03ELECIDLE_in; + wire PIPERX03EQDONE_in; + wire PIPERX03EQLPADAPTDONE_in; + wire PIPERX03EQLPLFFSSEL_in; + wire PIPERX03PHYSTATUS_in; + wire PIPERX03VALID_in; + wire PIPERX04DATAVALID_in; + wire PIPERX04ELECIDLE_in; + wire PIPERX04EQDONE_in; + wire PIPERX04EQLPADAPTDONE_in; + wire PIPERX04EQLPLFFSSEL_in; + wire PIPERX04PHYSTATUS_in; + wire PIPERX04VALID_in; + wire PIPERX05DATAVALID_in; + wire PIPERX05ELECIDLE_in; + wire PIPERX05EQDONE_in; + wire PIPERX05EQLPADAPTDONE_in; + wire PIPERX05EQLPLFFSSEL_in; + wire PIPERX05PHYSTATUS_in; + wire PIPERX05VALID_in; + wire PIPERX06DATAVALID_in; + wire PIPERX06ELECIDLE_in; + wire PIPERX06EQDONE_in; + wire PIPERX06EQLPADAPTDONE_in; + wire PIPERX06EQLPLFFSSEL_in; + wire PIPERX06PHYSTATUS_in; + wire PIPERX06VALID_in; + wire PIPERX07DATAVALID_in; + wire PIPERX07ELECIDLE_in; + wire PIPERX07EQDONE_in; + wire PIPERX07EQLPADAPTDONE_in; + wire PIPERX07EQLPLFFSSEL_in; + wire PIPERX07PHYSTATUS_in; + wire PIPERX07VALID_in; + wire PIPERX08DATAVALID_in; + wire PIPERX08ELECIDLE_in; + wire PIPERX08EQDONE_in; + wire PIPERX08EQLPADAPTDONE_in; + wire PIPERX08EQLPLFFSSEL_in; + wire PIPERX08PHYSTATUS_in; + wire PIPERX08VALID_in; + wire PIPERX09DATAVALID_in; + wire PIPERX09ELECIDLE_in; + wire PIPERX09EQDONE_in; + wire PIPERX09EQLPADAPTDONE_in; + wire PIPERX09EQLPLFFSSEL_in; + wire PIPERX09PHYSTATUS_in; + wire PIPERX09VALID_in; + wire PIPERX10DATAVALID_in; + wire PIPERX10ELECIDLE_in; + wire PIPERX10EQDONE_in; + wire PIPERX10EQLPADAPTDONE_in; + wire PIPERX10EQLPLFFSSEL_in; + wire PIPERX10PHYSTATUS_in; + wire PIPERX10VALID_in; + wire PIPERX11DATAVALID_in; + wire PIPERX11ELECIDLE_in; + wire PIPERX11EQDONE_in; + wire PIPERX11EQLPADAPTDONE_in; + wire PIPERX11EQLPLFFSSEL_in; + wire PIPERX11PHYSTATUS_in; + wire PIPERX11VALID_in; + wire PIPERX12DATAVALID_in; + wire PIPERX12ELECIDLE_in; + wire PIPERX12EQDONE_in; + wire PIPERX12EQLPADAPTDONE_in; + wire PIPERX12EQLPLFFSSEL_in; + wire PIPERX12PHYSTATUS_in; + wire PIPERX12VALID_in; + wire PIPERX13DATAVALID_in; + wire PIPERX13ELECIDLE_in; + wire PIPERX13EQDONE_in; + wire PIPERX13EQLPADAPTDONE_in; + wire PIPERX13EQLPLFFSSEL_in; + wire PIPERX13PHYSTATUS_in; + wire PIPERX13VALID_in; + wire PIPERX14DATAVALID_in; + wire PIPERX14ELECIDLE_in; + wire PIPERX14EQDONE_in; + wire PIPERX14EQLPADAPTDONE_in; + wire PIPERX14EQLPLFFSSEL_in; + wire PIPERX14PHYSTATUS_in; + wire PIPERX14VALID_in; + wire PIPERX15DATAVALID_in; + wire PIPERX15ELECIDLE_in; + wire PIPERX15EQDONE_in; + wire PIPERX15EQLPADAPTDONE_in; + wire PIPERX15EQLPLFFSSEL_in; + wire PIPERX15PHYSTATUS_in; + wire PIPERX15VALID_in; + wire PIPETX00EQDONE_in; + wire PIPETX01EQDONE_in; + wire PIPETX02EQDONE_in; + wire PIPETX03EQDONE_in; + wire PIPETX04EQDONE_in; + wire PIPETX05EQDONE_in; + wire PIPETX06EQDONE_in; + wire PIPETX07EQDONE_in; + wire PIPETX08EQDONE_in; + wire PIPETX09EQDONE_in; + wire PIPETX10EQDONE_in; + wire PIPETX11EQDONE_in; + wire PIPETX12EQDONE_in; + wire PIPETX13EQDONE_in; + wire PIPETX14EQDONE_in; + wire PIPETX15EQDONE_in; + wire PLEQRESETEIEOSCOUNT_in; + wire PLGEN2UPSTREAMPREFERDEEMPH_in; + wire PLGEN34REDOEQSPEED_in; + wire PLGEN34REDOEQUALIZATION_in; + wire PMVENABLEN_in; + wire RESETN_in; + wire SAXISCCTLAST_in; + wire SAXISCCTVALID_in; + wire SAXISRQTLAST_in; + wire SAXISRQTVALID_in; + wire SCANENABLEN_in; + wire SCANMODEN_in; + wire USERCLK2_in; + wire USERCLKEN_in; + wire USERCLK_in; + wire [11:0] MIRXCOMPLETIONRAMERRCOR_in; + wire [11:0] MIRXCOMPLETIONRAMERRUNCOR_in; + wire [127:0] MIREPLAYRAMREADDATA0_in; + wire [127:0] MIREPLAYRAMREADDATA1_in; + wire [143:0] MIRXCOMPLETIONRAMREADDATA0_in; + wire [143:0] MIRXCOMPLETIONRAMREADDATA1_in; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA0_in; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA1_in; + wire [15:0] CFGDEVIDPF0_in; + wire [15:0] CFGDEVIDPF1_in; + wire [15:0] CFGDEVIDPF2_in; + wire [15:0] CFGDEVIDPF3_in; + wire [15:0] CFGSUBSYSIDPF0_in; + wire [15:0] CFGSUBSYSIDPF1_in; + wire [15:0] CFGSUBSYSIDPF2_in; + wire [15:0] CFGSUBSYSIDPF3_in; + wire [15:0] CFGSUBSYSVENDID_in; + wire [15:0] CFGVENDID_in; + wire [15:0] DRPDI_in; + wire [172:0] SCANIN_in; + wire [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPETX00EQCOEFF_in; + wire [17:0] PIPETX01EQCOEFF_in; + wire [17:0] PIPETX02EQCOEFF_in; + wire [17:0] PIPETX03EQCOEFF_in; + wire [17:0] PIPETX04EQCOEFF_in; + wire [17:0] PIPETX05EQCOEFF_in; + wire [17:0] PIPETX06EQCOEFF_in; + wire [17:0] PIPETX07EQCOEFF_in; + wire [17:0] PIPETX08EQCOEFF_in; + wire [17:0] PIPETX09EQCOEFF_in; + wire [17:0] PIPETX10EQCOEFF_in; + wire [17:0] PIPETX11EQCOEFF_in; + wire [17:0] PIPETX12EQCOEFF_in; + wire [17:0] PIPETX13EQCOEFF_in; + wire [17:0] PIPETX14EQCOEFF_in; + wire [17:0] PIPETX15EQCOEFF_in; + wire [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in; + wire [1:0] CFGINTERRUPTMSISELECT_in; + wire [1:0] CFGINTERRUPTMSITPHTYPE_in; + wire [1:0] CFGINTERRUPTMSIXVECPENDING_in; + wire [1:0] CONFREQTYPE_in; + wire [1:0] PCIECOMPLDELIVERED_in; + wire [1:0] PCIECQNPREQ_in; + wire [1:0] PIPERX00CHARISK_in; + wire [1:0] PIPERX00STARTBLOCK_in; + wire [1:0] PIPERX00SYNCHEADER_in; + wire [1:0] PIPERX01CHARISK_in; + wire [1:0] PIPERX01STARTBLOCK_in; + wire [1:0] PIPERX01SYNCHEADER_in; + wire [1:0] PIPERX02CHARISK_in; + wire [1:0] PIPERX02STARTBLOCK_in; + wire [1:0] PIPERX02SYNCHEADER_in; + wire [1:0] PIPERX03CHARISK_in; + wire [1:0] PIPERX03STARTBLOCK_in; + wire [1:0] PIPERX03SYNCHEADER_in; + wire [1:0] PIPERX04CHARISK_in; + wire [1:0] PIPERX04STARTBLOCK_in; + wire [1:0] PIPERX04SYNCHEADER_in; + wire [1:0] PIPERX05CHARISK_in; + wire [1:0] PIPERX05STARTBLOCK_in; + wire [1:0] PIPERX05SYNCHEADER_in; + wire [1:0] PIPERX06CHARISK_in; + wire [1:0] PIPERX06STARTBLOCK_in; + wire [1:0] PIPERX06SYNCHEADER_in; + wire [1:0] PIPERX07CHARISK_in; + wire [1:0] PIPERX07STARTBLOCK_in; + wire [1:0] PIPERX07SYNCHEADER_in; + wire [1:0] PIPERX08CHARISK_in; + wire [1:0] PIPERX08STARTBLOCK_in; + wire [1:0] PIPERX08SYNCHEADER_in; + wire [1:0] PIPERX09CHARISK_in; + wire [1:0] PIPERX09STARTBLOCK_in; + wire [1:0] PIPERX09SYNCHEADER_in; + wire [1:0] PIPERX10CHARISK_in; + wire [1:0] PIPERX10STARTBLOCK_in; + wire [1:0] PIPERX10SYNCHEADER_in; + wire [1:0] PIPERX11CHARISK_in; + wire [1:0] PIPERX11STARTBLOCK_in; + wire [1:0] PIPERX11SYNCHEADER_in; + wire [1:0] PIPERX12CHARISK_in; + wire [1:0] PIPERX12STARTBLOCK_in; + wire [1:0] PIPERX12SYNCHEADER_in; + wire [1:0] PIPERX13CHARISK_in; + wire [1:0] PIPERX13STARTBLOCK_in; + wire [1:0] PIPERX13SYNCHEADER_in; + wire [1:0] PIPERX14CHARISK_in; + wire [1:0] PIPERX14STARTBLOCK_in; + wire [1:0] PIPERX14SYNCHEADER_in; + wire [1:0] PIPERX15CHARISK_in; + wire [1:0] PIPERX15STARTBLOCK_in; + wire [1:0] PIPERX15SYNCHEADER_in; + wire [1:0] PMVDIVIDE_in; + wire [21:0] MAXISCQTREADY_in; + wire [21:0] MAXISRCTREADY_in; + wire [255:0] SAXISCCTDATA_in; + wire [255:0] SAXISRQTDATA_in; + wire [2:0] CFGDSFUNCTIONNUMBER_in; + wire [2:0] CFGFCSEL_in; + wire [2:0] CFGINTERRUPTMSIATTR_in; + wire [2:0] CFGMSGTRANSMITTYPE_in; + wire [2:0] PIPERX00STATUS_in; + wire [2:0] PIPERX01STATUS_in; + wire [2:0] PIPERX02STATUS_in; + wire [2:0] PIPERX03STATUS_in; + wire [2:0] PIPERX04STATUS_in; + wire [2:0] PIPERX05STATUS_in; + wire [2:0] PIPERX06STATUS_in; + wire [2:0] PIPERX07STATUS_in; + wire [2:0] PIPERX08STATUS_in; + wire [2:0] PIPERX09STATUS_in; + wire [2:0] PIPERX10STATUS_in; + wire [2:0] PIPERX11STATUS_in; + wire [2:0] PIPERX12STATUS_in; + wire [2:0] PIPERX13STATUS_in; + wire [2:0] PIPERX14STATUS_in; + wire [2:0] PIPERX15STATUS_in; + wire [2:0] PMVSELECT_in; + wire [31:0] CFGEXTREADDATA_in; + wire [31:0] CFGINTERRUPTMSIINT_in; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_in; + wire [31:0] CFGINTERRUPTMSIXDATA_in; + wire [31:0] CFGMGMTWRITEDATA_in; + wire [31:0] CFGMSGTRANSMITDATA_in; + wire [31:0] CONFREQDATA_in; + wire [31:0] PIPERX00DATA_in; + wire [31:0] PIPERX01DATA_in; + wire [31:0] PIPERX02DATA_in; + wire [31:0] PIPERX03DATA_in; + wire [31:0] PIPERX04DATA_in; + wire [31:0] PIPERX05DATA_in; + wire [31:0] PIPERX06DATA_in; + wire [31:0] PIPERX07DATA_in; + wire [31:0] PIPERX08DATA_in; + wire [31:0] PIPERX09DATA_in; + wire [31:0] PIPERX10DATA_in; + wire [31:0] PIPERX11DATA_in; + wire [31:0] PIPERX12DATA_in; + wire [31:0] PIPERX13DATA_in; + wire [31:0] PIPERX14DATA_in; + wire [31:0] PIPERX15DATA_in; + wire [31:0] USERSPAREIN_in; + wire [32:0] SAXISCCTUSER_in; + wire [35:0] CFGMSIXRAMREADDATA_in; + wire [35:0] CFGTPHRAMREADDATA_in; + wire [3:0] CFGFLRDONE_in; + wire [3:0] CFGINTERRUPTINT_in; + wire [3:0] CFGINTERRUPTPENDING_in; + wire [3:0] CFGMGMTBYTEENABLE_in; + wire [3:0] CONFREQREGNUM_in; + wire [4:0] CFGDSDEVICENUMBER_in; + wire [5:0] DBGSEL0_in; + wire [5:0] DBGSEL1_in; + wire [5:0] MIREPLAYRAMERRCOR_in; + wire [5:0] MIREPLAYRAMERRUNCOR_in; + wire [5:0] MIRXPOSTEDREQUESTRAMERRCOR_in; + wire [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR_in; + wire [5:0] PIPEEQFS_in; + wire [5:0] PIPEEQLF_in; + wire [61:0] SAXISRQTUSER_in; + wire [63:0] CFGDSN_in; + wire [63:0] CFGINTERRUPTMSIXADDRESS_in; + wire [7:0] AXIUSERIN_in; + wire [7:0] CFGDSBUSNUMBER_in; + wire [7:0] CFGDSPORTNUMBER_in; + wire [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER_in; + wire [7:0] CFGINTERRUPTMSITPHSTTAG_in; + wire [7:0] CFGMGMTFUNCTIONNUMBER_in; + wire [7:0] CFGREVIDPF0_in; + wire [7:0] CFGREVIDPF1_in; + wire [7:0] CFGREVIDPF2_in; + wire [7:0] CFGREVIDPF3_in; + wire [7:0] CFGVFFLRFUNCNUM_in; + wire [7:0] PCIECOMPLDELIVEREDTAG0_in; + wire [7:0] PCIECOMPLDELIVEREDTAG1_in; + wire [7:0] SAXISCCTKEEP_in; + wire [7:0] SAXISRQTKEEP_in; + wire [9:0] CFGMGMTADDR_in; + wire [9:0] DRPADDR_in; + +`ifdef XIL_TIMING + wire CFGCONFIGSPACEENABLE_delay; + wire CFGERRCORIN_delay; + wire CFGERRUNCORIN_delay; + wire CFGEXTREADDATAVALID_delay; + wire CFGHOTRESETIN_delay; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; + wire CFGINTERRUPTMSITPHPRESENT_delay; + wire CFGINTERRUPTMSIXINT_delay; + wire CFGLINKTRAININGENABLE_delay; + wire CFGMGMTDEBUGACCESS_delay; + wire CFGMGMTREAD_delay; + wire CFGMGMTWRITE_delay; + wire CFGMSGTRANSMIT_delay; + wire CFGPMASPML1ENTRYREJECT_delay; + wire CFGPMASPMTXL0SENTRYDISABLE_delay; + wire CFGPOWERSTATECHANGEACK_delay; + wire CFGREQPMTRANSITIONL23READY_delay; + wire CFGVFFLRDONE_delay; + wire CONFMCAPREQUESTBYCONF_delay; + wire CONFREQVALID_delay; + wire CORECLK_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire PCIECQNPUSERCREDITRCVD_delay; + wire PCIECQPIPELINEEMPTY_delay; + wire PCIEPOSTEDREQDELIVERED_delay; + wire PIPECLK_delay; + wire PIPERX00DATAVALID_delay; + wire PIPERX00ELECIDLE_delay; + wire PIPERX00EQDONE_delay; + wire PIPERX00EQLPADAPTDONE_delay; + wire PIPERX00EQLPLFFSSEL_delay; + wire PIPERX00PHYSTATUS_delay; + wire PIPERX00VALID_delay; + wire PIPERX01DATAVALID_delay; + wire PIPERX01ELECIDLE_delay; + wire PIPERX01EQDONE_delay; + wire PIPERX01EQLPADAPTDONE_delay; + wire PIPERX01EQLPLFFSSEL_delay; + wire PIPERX01PHYSTATUS_delay; + wire PIPERX01VALID_delay; + wire PIPERX02DATAVALID_delay; + wire PIPERX02ELECIDLE_delay; + wire PIPERX02EQDONE_delay; + wire PIPERX02EQLPADAPTDONE_delay; + wire PIPERX02EQLPLFFSSEL_delay; + wire PIPERX02PHYSTATUS_delay; + wire PIPERX02VALID_delay; + wire PIPERX03DATAVALID_delay; + wire PIPERX03ELECIDLE_delay; + wire PIPERX03EQDONE_delay; + wire PIPERX03EQLPADAPTDONE_delay; + wire PIPERX03EQLPLFFSSEL_delay; + wire PIPERX03PHYSTATUS_delay; + wire PIPERX03VALID_delay; + wire PIPERX04DATAVALID_delay; + wire PIPERX04ELECIDLE_delay; + wire PIPERX04EQDONE_delay; + wire PIPERX04EQLPADAPTDONE_delay; + wire PIPERX04EQLPLFFSSEL_delay; + wire PIPERX04PHYSTATUS_delay; + wire PIPERX04VALID_delay; + wire PIPERX05DATAVALID_delay; + wire PIPERX05ELECIDLE_delay; + wire PIPERX05EQDONE_delay; + wire PIPERX05EQLPADAPTDONE_delay; + wire PIPERX05EQLPLFFSSEL_delay; + wire PIPERX05PHYSTATUS_delay; + wire PIPERX05VALID_delay; + wire PIPERX06DATAVALID_delay; + wire PIPERX06ELECIDLE_delay; + wire PIPERX06EQDONE_delay; + wire PIPERX06EQLPADAPTDONE_delay; + wire PIPERX06EQLPLFFSSEL_delay; + wire PIPERX06PHYSTATUS_delay; + wire PIPERX06VALID_delay; + wire PIPERX07DATAVALID_delay; + wire PIPERX07ELECIDLE_delay; + wire PIPERX07EQDONE_delay; + wire PIPERX07EQLPADAPTDONE_delay; + wire PIPERX07EQLPLFFSSEL_delay; + wire PIPERX07PHYSTATUS_delay; + wire PIPERX07VALID_delay; + wire PIPERX08DATAVALID_delay; + wire PIPERX08ELECIDLE_delay; + wire PIPERX08EQDONE_delay; + wire PIPERX08EQLPADAPTDONE_delay; + wire PIPERX08EQLPLFFSSEL_delay; + wire PIPERX08PHYSTATUS_delay; + wire PIPERX08VALID_delay; + wire PIPERX09DATAVALID_delay; + wire PIPERX09ELECIDLE_delay; + wire PIPERX09EQDONE_delay; + wire PIPERX09EQLPADAPTDONE_delay; + wire PIPERX09EQLPLFFSSEL_delay; + wire PIPERX09PHYSTATUS_delay; + wire PIPERX09VALID_delay; + wire PIPERX10DATAVALID_delay; + wire PIPERX10ELECIDLE_delay; + wire PIPERX10EQDONE_delay; + wire PIPERX10EQLPADAPTDONE_delay; + wire PIPERX10EQLPLFFSSEL_delay; + wire PIPERX10PHYSTATUS_delay; + wire PIPERX10VALID_delay; + wire PIPERX11DATAVALID_delay; + wire PIPERX11ELECIDLE_delay; + wire PIPERX11EQDONE_delay; + wire PIPERX11EQLPADAPTDONE_delay; + wire PIPERX11EQLPLFFSSEL_delay; + wire PIPERX11PHYSTATUS_delay; + wire PIPERX11VALID_delay; + wire PIPERX12DATAVALID_delay; + wire PIPERX12ELECIDLE_delay; + wire PIPERX12EQDONE_delay; + wire PIPERX12EQLPADAPTDONE_delay; + wire PIPERX12EQLPLFFSSEL_delay; + wire PIPERX12PHYSTATUS_delay; + wire PIPERX12VALID_delay; + wire PIPERX13DATAVALID_delay; + wire PIPERX13ELECIDLE_delay; + wire PIPERX13EQDONE_delay; + wire PIPERX13EQLPADAPTDONE_delay; + wire PIPERX13EQLPLFFSSEL_delay; + wire PIPERX13PHYSTATUS_delay; + wire PIPERX13VALID_delay; + wire PIPERX14DATAVALID_delay; + wire PIPERX14ELECIDLE_delay; + wire PIPERX14EQDONE_delay; + wire PIPERX14EQLPADAPTDONE_delay; + wire PIPERX14EQLPLFFSSEL_delay; + wire PIPERX14PHYSTATUS_delay; + wire PIPERX14VALID_delay; + wire PIPERX15DATAVALID_delay; + wire PIPERX15ELECIDLE_delay; + wire PIPERX15EQDONE_delay; + wire PIPERX15EQLPADAPTDONE_delay; + wire PIPERX15EQLPLFFSSEL_delay; + wire PIPERX15PHYSTATUS_delay; + wire PIPERX15VALID_delay; + wire PIPETX00EQDONE_delay; + wire PIPETX01EQDONE_delay; + wire PIPETX02EQDONE_delay; + wire PIPETX03EQDONE_delay; + wire PIPETX04EQDONE_delay; + wire PIPETX05EQDONE_delay; + wire PIPETX06EQDONE_delay; + wire PIPETX07EQDONE_delay; + wire PIPETX08EQDONE_delay; + wire PIPETX09EQDONE_delay; + wire PIPETX10EQDONE_delay; + wire PIPETX11EQDONE_delay; + wire PIPETX12EQDONE_delay; + wire PIPETX13EQDONE_delay; + wire PIPETX14EQDONE_delay; + wire PIPETX15EQDONE_delay; + wire PLGEN2UPSTREAMPREFERDEEMPH_delay; + wire PLGEN34REDOEQSPEED_delay; + wire PLGEN34REDOEQUALIZATION_delay; + wire SAXISCCTLAST_delay; + wire SAXISCCTVALID_delay; + wire SAXISRQTLAST_delay; + wire SAXISRQTVALID_delay; + wire USERCLKEN_delay; + wire [11:0] MIRXCOMPLETIONRAMERRCOR_delay; + wire [11:0] MIRXCOMPLETIONRAMERRUNCOR_delay; + wire [127:0] MIREPLAYRAMREADDATA0_delay; + wire [127:0] MIREPLAYRAMREADDATA1_delay; + wire [143:0] MIRXCOMPLETIONRAMREADDATA0_delay; + wire [143:0] MIRXCOMPLETIONRAMREADDATA1_delay; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA0_delay; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA1_delay; + wire [15:0] CFGDEVIDPF0_delay; + wire [15:0] CFGDEVIDPF1_delay; + wire [15:0] CFGDEVIDPF2_delay; + wire [15:0] CFGDEVIDPF3_delay; + wire [15:0] CFGSUBSYSIDPF0_delay; + wire [15:0] CFGSUBSYSIDPF1_delay; + wire [15:0] CFGSUBSYSIDPF2_delay; + wire [15:0] CFGSUBSYSIDPF3_delay; + wire [15:0] CFGSUBSYSVENDID_delay; + wire [15:0] CFGVENDID_delay; + wire [15:0] DRPDI_delay; + wire [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPETX00EQCOEFF_delay; + wire [17:0] PIPETX01EQCOEFF_delay; + wire [17:0] PIPETX02EQCOEFF_delay; + wire [17:0] PIPETX03EQCOEFF_delay; + wire [17:0] PIPETX04EQCOEFF_delay; + wire [17:0] PIPETX05EQCOEFF_delay; + wire [17:0] PIPETX06EQCOEFF_delay; + wire [17:0] PIPETX07EQCOEFF_delay; + wire [17:0] PIPETX08EQCOEFF_delay; + wire [17:0] PIPETX09EQCOEFF_delay; + wire [17:0] PIPETX10EQCOEFF_delay; + wire [17:0] PIPETX11EQCOEFF_delay; + wire [17:0] PIPETX12EQCOEFF_delay; + wire [17:0] PIPETX13EQCOEFF_delay; + wire [17:0] PIPETX14EQCOEFF_delay; + wire [17:0] PIPETX15EQCOEFF_delay; + wire [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay; + wire [1:0] CFGINTERRUPTMSISELECT_delay; + wire [1:0] CFGINTERRUPTMSITPHTYPE_delay; + wire [1:0] CFGINTERRUPTMSIXVECPENDING_delay; + wire [1:0] CONFREQTYPE_delay; + wire [1:0] PCIECOMPLDELIVERED_delay; + wire [1:0] PCIECQNPREQ_delay; + wire [1:0] PIPERX00CHARISK_delay; + wire [1:0] PIPERX00STARTBLOCK_delay; + wire [1:0] PIPERX00SYNCHEADER_delay; + wire [1:0] PIPERX01CHARISK_delay; + wire [1:0] PIPERX01STARTBLOCK_delay; + wire [1:0] PIPERX01SYNCHEADER_delay; + wire [1:0] PIPERX02CHARISK_delay; + wire [1:0] PIPERX02STARTBLOCK_delay; + wire [1:0] PIPERX02SYNCHEADER_delay; + wire [1:0] PIPERX03CHARISK_delay; + wire [1:0] PIPERX03STARTBLOCK_delay; + wire [1:0] PIPERX03SYNCHEADER_delay; + wire [1:0] PIPERX04CHARISK_delay; + wire [1:0] PIPERX04STARTBLOCK_delay; + wire [1:0] PIPERX04SYNCHEADER_delay; + wire [1:0] PIPERX05CHARISK_delay; + wire [1:0] PIPERX05STARTBLOCK_delay; + wire [1:0] PIPERX05SYNCHEADER_delay; + wire [1:0] PIPERX06CHARISK_delay; + wire [1:0] PIPERX06STARTBLOCK_delay; + wire [1:0] PIPERX06SYNCHEADER_delay; + wire [1:0] PIPERX07CHARISK_delay; + wire [1:0] PIPERX07STARTBLOCK_delay; + wire [1:0] PIPERX07SYNCHEADER_delay; + wire [1:0] PIPERX08CHARISK_delay; + wire [1:0] PIPERX08STARTBLOCK_delay; + wire [1:0] PIPERX08SYNCHEADER_delay; + wire [1:0] PIPERX09CHARISK_delay; + wire [1:0] PIPERX09STARTBLOCK_delay; + wire [1:0] PIPERX09SYNCHEADER_delay; + wire [1:0] PIPERX10CHARISK_delay; + wire [1:0] PIPERX10STARTBLOCK_delay; + wire [1:0] PIPERX10SYNCHEADER_delay; + wire [1:0] PIPERX11CHARISK_delay; + wire [1:0] PIPERX11STARTBLOCK_delay; + wire [1:0] PIPERX11SYNCHEADER_delay; + wire [1:0] PIPERX12CHARISK_delay; + wire [1:0] PIPERX12STARTBLOCK_delay; + wire [1:0] PIPERX12SYNCHEADER_delay; + wire [1:0] PIPERX13CHARISK_delay; + wire [1:0] PIPERX13STARTBLOCK_delay; + wire [1:0] PIPERX13SYNCHEADER_delay; + wire [1:0] PIPERX14CHARISK_delay; + wire [1:0] PIPERX14STARTBLOCK_delay; + wire [1:0] PIPERX14SYNCHEADER_delay; + wire [1:0] PIPERX15CHARISK_delay; + wire [1:0] PIPERX15STARTBLOCK_delay; + wire [1:0] PIPERX15SYNCHEADER_delay; + wire [21:0] MAXISCQTREADY_delay; + wire [21:0] MAXISRCTREADY_delay; + wire [255:0] SAXISCCTDATA_delay; + wire [255:0] SAXISRQTDATA_delay; + wire [2:0] CFGDSFUNCTIONNUMBER_delay; + wire [2:0] CFGFCSEL_delay; + wire [2:0] CFGINTERRUPTMSIATTR_delay; + wire [2:0] CFGMSGTRANSMITTYPE_delay; + wire [2:0] PIPERX00STATUS_delay; + wire [2:0] PIPERX01STATUS_delay; + wire [2:0] PIPERX02STATUS_delay; + wire [2:0] PIPERX03STATUS_delay; + wire [2:0] PIPERX04STATUS_delay; + wire [2:0] PIPERX05STATUS_delay; + wire [2:0] PIPERX06STATUS_delay; + wire [2:0] PIPERX07STATUS_delay; + wire [2:0] PIPERX08STATUS_delay; + wire [2:0] PIPERX09STATUS_delay; + wire [2:0] PIPERX10STATUS_delay; + wire [2:0] PIPERX11STATUS_delay; + wire [2:0] PIPERX12STATUS_delay; + wire [2:0] PIPERX13STATUS_delay; + wire [2:0] PIPERX14STATUS_delay; + wire [2:0] PIPERX15STATUS_delay; + wire [31:0] CFGEXTREADDATA_delay; + wire [31:0] CFGINTERRUPTMSIINT_delay; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_delay; + wire [31:0] CFGINTERRUPTMSIXDATA_delay; + wire [31:0] CFGMGMTWRITEDATA_delay; + wire [31:0] CFGMSGTRANSMITDATA_delay; + wire [31:0] CONFREQDATA_delay; + wire [31:0] PIPERX00DATA_delay; + wire [31:0] PIPERX01DATA_delay; + wire [31:0] PIPERX02DATA_delay; + wire [31:0] PIPERX03DATA_delay; + wire [31:0] PIPERX04DATA_delay; + wire [31:0] PIPERX05DATA_delay; + wire [31:0] PIPERX06DATA_delay; + wire [31:0] PIPERX07DATA_delay; + wire [31:0] PIPERX08DATA_delay; + wire [31:0] PIPERX09DATA_delay; + wire [31:0] PIPERX10DATA_delay; + wire [31:0] PIPERX11DATA_delay; + wire [31:0] PIPERX12DATA_delay; + wire [31:0] PIPERX13DATA_delay; + wire [31:0] PIPERX14DATA_delay; + wire [31:0] PIPERX15DATA_delay; + wire [31:0] USERSPAREIN_delay; + wire [32:0] SAXISCCTUSER_delay; + wire [35:0] CFGMSIXRAMREADDATA_delay; + wire [35:0] CFGTPHRAMREADDATA_delay; + wire [3:0] CFGFLRDONE_delay; + wire [3:0] CFGINTERRUPTINT_delay; + wire [3:0] CFGINTERRUPTPENDING_delay; + wire [3:0] CFGMGMTBYTEENABLE_delay; + wire [3:0] CONFREQREGNUM_delay; + wire [4:0] CFGDSDEVICENUMBER_delay; + wire [5:0] DBGSEL0_delay; + wire [5:0] DBGSEL1_delay; + wire [5:0] MIREPLAYRAMERRCOR_delay; + wire [5:0] MIREPLAYRAMERRUNCOR_delay; + wire [5:0] MIRXPOSTEDREQUESTRAMERRCOR_delay; + wire [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR_delay; + wire [5:0] PIPEEQFS_delay; + wire [5:0] PIPEEQLF_delay; + wire [61:0] SAXISRQTUSER_delay; + wire [63:0] CFGDSN_delay; + wire [63:0] CFGINTERRUPTMSIXADDRESS_delay; + wire [7:0] AXIUSERIN_delay; + wire [7:0] CFGDSBUSNUMBER_delay; + wire [7:0] CFGDSPORTNUMBER_delay; + wire [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER_delay; + wire [7:0] CFGINTERRUPTMSITPHSTTAG_delay; + wire [7:0] CFGMGMTFUNCTIONNUMBER_delay; + wire [7:0] CFGREVIDPF0_delay; + wire [7:0] CFGREVIDPF1_delay; + wire [7:0] CFGREVIDPF2_delay; + wire [7:0] CFGREVIDPF3_delay; + wire [7:0] CFGVFFLRFUNCNUM_delay; + wire [7:0] PCIECOMPLDELIVEREDTAG0_delay; + wire [7:0] PCIECOMPLDELIVEREDTAG1_delay; + wire [7:0] SAXISCCTKEEP_delay; + wire [7:0] SAXISRQTKEEP_delay; + wire [9:0] CFGMGMTADDR_delay; + wire [9:0] DRPADDR_delay; +`endif + + assign AXIUSEROUT = AXIUSEROUT_out; + assign CFGBUSNUMBER = CFGBUSNUMBER_out; + assign CFGCURRENTSPEED = CFGCURRENTSPEED_out; + assign CFGERRCOROUT = CFGERRCOROUT_out; + assign CFGERRFATALOUT = CFGERRFATALOUT_out; + assign CFGERRNONFATALOUT = CFGERRNONFATALOUT_out; + assign CFGEXTFUNCTIONNUMBER = CFGEXTFUNCTIONNUMBER_out; + assign CFGEXTREADRECEIVED = CFGEXTREADRECEIVED_out; + assign CFGEXTREGISTERNUMBER = CFGEXTREGISTERNUMBER_out; + assign CFGEXTWRITEBYTEENABLE = CFGEXTWRITEBYTEENABLE_out; + assign CFGEXTWRITEDATA = CFGEXTWRITEDATA_out; + assign CFGEXTWRITERECEIVED = CFGEXTWRITERECEIVED_out; + assign CFGFCCPLD = CFGFCCPLD_out; + assign CFGFCCPLH = CFGFCCPLH_out; + assign CFGFCNPD = CFGFCNPD_out; + assign CFGFCNPH = CFGFCNPH_out; + assign CFGFCPD = CFGFCPD_out; + assign CFGFCPH = CFGFCPH_out; + assign CFGFLRINPROCESS = CFGFLRINPROCESS_out; + assign CFGFUNCTIONPOWERSTATE = CFGFUNCTIONPOWERSTATE_out; + assign CFGFUNCTIONSTATUS = CFGFUNCTIONSTATUS_out; + assign CFGHOTRESETOUT = CFGHOTRESETOUT_out; + assign CFGINTERRUPTMSIDATA = CFGINTERRUPTMSIDATA_out; + assign CFGINTERRUPTMSIENABLE = CFGINTERRUPTMSIENABLE_out; + assign CFGINTERRUPTMSIFAIL = CFGINTERRUPTMSIFAIL_out; + assign CFGINTERRUPTMSIMASKUPDATE = CFGINTERRUPTMSIMASKUPDATE_out; + assign CFGINTERRUPTMSIMMENABLE = CFGINTERRUPTMSIMMENABLE_out; + assign CFGINTERRUPTMSISENT = CFGINTERRUPTMSISENT_out; + assign CFGINTERRUPTMSIXENABLE = CFGINTERRUPTMSIXENABLE_out; + assign CFGINTERRUPTMSIXMASK = CFGINTERRUPTMSIXMASK_out; + assign CFGINTERRUPTMSIXVECPENDINGSTATUS = CFGINTERRUPTMSIXVECPENDINGSTATUS_out; + assign CFGINTERRUPTSENT = CFGINTERRUPTSENT_out; + assign CFGLINKPOWERSTATE = CFGLINKPOWERSTATE_out; + assign CFGLOCALERROROUT = CFGLOCALERROROUT_out; + assign CFGLOCALERRORVALID = CFGLOCALERRORVALID_out; + assign CFGLTRENABLE = CFGLTRENABLE_out; + assign CFGLTSSMSTATE = CFGLTSSMSTATE_out; + assign CFGMAXPAYLOAD = CFGMAXPAYLOAD_out; + assign CFGMAXREADREQ = CFGMAXREADREQ_out; + assign CFGMGMTREADDATA = CFGMGMTREADDATA_out; + assign CFGMGMTREADWRITEDONE = CFGMGMTREADWRITEDONE_out; + assign CFGMSGRECEIVED = CFGMSGRECEIVED_out; + assign CFGMSGRECEIVEDDATA = CFGMSGRECEIVEDDATA_out; + assign CFGMSGRECEIVEDTYPE = CFGMSGRECEIVEDTYPE_out; + assign CFGMSGTRANSMITDONE = CFGMSGTRANSMITDONE_out; + assign CFGMSIXRAMADDRESS = CFGMSIXRAMADDRESS_out; + assign CFGMSIXRAMREADENABLE = CFGMSIXRAMREADENABLE_out; + assign CFGMSIXRAMWRITEBYTEENABLE = CFGMSIXRAMWRITEBYTEENABLE_out; + assign CFGMSIXRAMWRITEDATA = CFGMSIXRAMWRITEDATA_out; + assign CFGNEGOTIATEDWIDTH = CFGNEGOTIATEDWIDTH_out; + assign CFGOBFFENABLE = CFGOBFFENABLE_out; + assign CFGPHYLINKDOWN = CFGPHYLINKDOWN_out; + assign CFGPHYLINKSTATUS = CFGPHYLINKSTATUS_out; + assign CFGPLSTATUSCHANGE = CFGPLSTATUSCHANGE_out; + assign CFGPOWERSTATECHANGEINTERRUPT = CFGPOWERSTATECHANGEINTERRUPT_out; + assign CFGRCBSTATUS = CFGRCBSTATUS_out; + assign CFGRXPMSTATE = CFGRXPMSTATE_out; + assign CFGTPHRAMADDRESS = CFGTPHRAMADDRESS_out; + assign CFGTPHRAMREADENABLE = CFGTPHRAMREADENABLE_out; + assign CFGTPHRAMWRITEBYTEENABLE = CFGTPHRAMWRITEBYTEENABLE_out; + assign CFGTPHRAMWRITEDATA = CFGTPHRAMWRITEDATA_out; + assign CFGTPHREQUESTERENABLE = CFGTPHREQUESTERENABLE_out; + assign CFGTPHSTMODE = CFGTPHSTMODE_out; + assign CFGTXPMSTATE = CFGTXPMSTATE_out; + assign CONFMCAPDESIGNSWITCH = CONFMCAPDESIGNSWITCH_out; + assign CONFMCAPEOS = CONFMCAPEOS_out; + assign CONFMCAPINUSEBYPCIE = CONFMCAPINUSEBYPCIE_out; + assign CONFREQREADY = CONFREQREADY_out; + assign CONFRESPRDATA = CONFRESPRDATA_out; + assign CONFRESPVALID = CONFRESPVALID_out; + assign DBGCTRL0OUT = DBGCTRL0OUT_out; + assign DBGCTRL1OUT = DBGCTRL1OUT_out; + assign DBGDATA0OUT = DBGDATA0OUT_out; + assign DBGDATA1OUT = DBGDATA1OUT_out; + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign MAXISCQTDATA = MAXISCQTDATA_out; + assign MAXISCQTKEEP = MAXISCQTKEEP_out; + assign MAXISCQTLAST = MAXISCQTLAST_out; + assign MAXISCQTUSER = MAXISCQTUSER_out; + assign MAXISCQTVALID = MAXISCQTVALID_out; + assign MAXISRCTDATA = MAXISRCTDATA_out; + assign MAXISRCTKEEP = MAXISRCTKEEP_out; + assign MAXISRCTLAST = MAXISRCTLAST_out; + assign MAXISRCTUSER = MAXISRCTUSER_out; + assign MAXISRCTVALID = MAXISRCTVALID_out; + assign MIREPLAYRAMADDRESS0 = MIREPLAYRAMADDRESS0_out; + assign MIREPLAYRAMADDRESS1 = MIREPLAYRAMADDRESS1_out; + assign MIREPLAYRAMREADENABLE0 = MIREPLAYRAMREADENABLE0_out; + assign MIREPLAYRAMREADENABLE1 = MIREPLAYRAMREADENABLE1_out; + assign MIREPLAYRAMWRITEDATA0 = MIREPLAYRAMWRITEDATA0_out; + assign MIREPLAYRAMWRITEDATA1 = MIREPLAYRAMWRITEDATA1_out; + assign MIREPLAYRAMWRITEENABLE0 = MIREPLAYRAMWRITEENABLE0_out; + assign MIREPLAYRAMWRITEENABLE1 = MIREPLAYRAMWRITEENABLE1_out; + assign MIRXCOMPLETIONRAMREADADDRESS0 = MIRXCOMPLETIONRAMREADADDRESS0_out; + assign MIRXCOMPLETIONRAMREADADDRESS1 = MIRXCOMPLETIONRAMREADADDRESS1_out; + assign MIRXCOMPLETIONRAMREADENABLE0 = MIRXCOMPLETIONRAMREADENABLE0_out; + assign MIRXCOMPLETIONRAMREADENABLE1 = MIRXCOMPLETIONRAMREADENABLE1_out; + assign MIRXCOMPLETIONRAMWRITEADDRESS0 = MIRXCOMPLETIONRAMWRITEADDRESS0_out; + assign MIRXCOMPLETIONRAMWRITEADDRESS1 = MIRXCOMPLETIONRAMWRITEADDRESS1_out; + assign MIRXCOMPLETIONRAMWRITEDATA0 = MIRXCOMPLETIONRAMWRITEDATA0_out; + assign MIRXCOMPLETIONRAMWRITEDATA1 = MIRXCOMPLETIONRAMWRITEDATA1_out; + assign MIRXCOMPLETIONRAMWRITEENABLE0 = MIRXCOMPLETIONRAMWRITEENABLE0_out; + assign MIRXCOMPLETIONRAMWRITEENABLE1 = MIRXCOMPLETIONRAMWRITEENABLE1_out; + assign MIRXPOSTEDREQUESTRAMREADADDRESS0 = MIRXPOSTEDREQUESTRAMREADADDRESS0_out; + assign MIRXPOSTEDREQUESTRAMREADADDRESS1 = MIRXPOSTEDREQUESTRAMREADADDRESS1_out; + assign MIRXPOSTEDREQUESTRAMREADENABLE0 = MIRXPOSTEDREQUESTRAMREADENABLE0_out; + assign MIRXPOSTEDREQUESTRAMREADENABLE1 = MIRXPOSTEDREQUESTRAMREADENABLE1_out; + assign MIRXPOSTEDREQUESTRAMWRITEADDRESS0 = MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out; + assign MIRXPOSTEDREQUESTRAMWRITEADDRESS1 = MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out; + assign MIRXPOSTEDREQUESTRAMWRITEDATA0 = MIRXPOSTEDREQUESTRAMWRITEDATA0_out; + assign MIRXPOSTEDREQUESTRAMWRITEDATA1 = MIRXPOSTEDREQUESTRAMWRITEDATA1_out; + assign MIRXPOSTEDREQUESTRAMWRITEENABLE0 = MIRXPOSTEDREQUESTRAMWRITEENABLE0_out; + assign MIRXPOSTEDREQUESTRAMWRITEENABLE1 = MIRXPOSTEDREQUESTRAMWRITEENABLE1_out; + assign PCIECQNPREQCOUNT = PCIECQNPREQCOUNT_out; + assign PCIEPERST0B = PCIEPERST0B_out; + assign PCIEPERST1B = PCIEPERST1B_out; + assign PCIERQSEQNUM0 = PCIERQSEQNUM0_out; + assign PCIERQSEQNUM1 = PCIERQSEQNUM1_out; + assign PCIERQSEQNUMVLD0 = PCIERQSEQNUMVLD0_out; + assign PCIERQSEQNUMVLD1 = PCIERQSEQNUMVLD1_out; + assign PCIERQTAG0 = PCIERQTAG0_out; + assign PCIERQTAG1 = PCIERQTAG1_out; + assign PCIERQTAGAV = PCIERQTAGAV_out; + assign PCIERQTAGVLD0 = PCIERQTAGVLD0_out; + assign PCIERQTAGVLD1 = PCIERQTAGVLD1_out; + assign PCIETFCNPDAV = PCIETFCNPDAV_out; + assign PCIETFCNPHAV = PCIETFCNPHAV_out; + assign PIPERX00EQCONTROL = PIPERX00EQCONTROL_out; + assign PIPERX00POLARITY = PIPERX00POLARITY_out; + assign PIPERX01EQCONTROL = PIPERX01EQCONTROL_out; + assign PIPERX01POLARITY = PIPERX01POLARITY_out; + assign PIPERX02EQCONTROL = PIPERX02EQCONTROL_out; + assign PIPERX02POLARITY = PIPERX02POLARITY_out; + assign PIPERX03EQCONTROL = PIPERX03EQCONTROL_out; + assign PIPERX03POLARITY = PIPERX03POLARITY_out; + assign PIPERX04EQCONTROL = PIPERX04EQCONTROL_out; + assign PIPERX04POLARITY = PIPERX04POLARITY_out; + assign PIPERX05EQCONTROL = PIPERX05EQCONTROL_out; + assign PIPERX05POLARITY = PIPERX05POLARITY_out; + assign PIPERX06EQCONTROL = PIPERX06EQCONTROL_out; + assign PIPERX06POLARITY = PIPERX06POLARITY_out; + assign PIPERX07EQCONTROL = PIPERX07EQCONTROL_out; + assign PIPERX07POLARITY = PIPERX07POLARITY_out; + assign PIPERX08EQCONTROL = PIPERX08EQCONTROL_out; + assign PIPERX08POLARITY = PIPERX08POLARITY_out; + assign PIPERX09EQCONTROL = PIPERX09EQCONTROL_out; + assign PIPERX09POLARITY = PIPERX09POLARITY_out; + assign PIPERX10EQCONTROL = PIPERX10EQCONTROL_out; + assign PIPERX10POLARITY = PIPERX10POLARITY_out; + assign PIPERX11EQCONTROL = PIPERX11EQCONTROL_out; + assign PIPERX11POLARITY = PIPERX11POLARITY_out; + assign PIPERX12EQCONTROL = PIPERX12EQCONTROL_out; + assign PIPERX12POLARITY = PIPERX12POLARITY_out; + assign PIPERX13EQCONTROL = PIPERX13EQCONTROL_out; + assign PIPERX13POLARITY = PIPERX13POLARITY_out; + assign PIPERX14EQCONTROL = PIPERX14EQCONTROL_out; + assign PIPERX14POLARITY = PIPERX14POLARITY_out; + assign PIPERX15EQCONTROL = PIPERX15EQCONTROL_out; + assign PIPERX15POLARITY = PIPERX15POLARITY_out; + assign PIPERXEQLPLFFS = PIPERXEQLPLFFS_out; + assign PIPERXEQLPTXPRESET = PIPERXEQLPTXPRESET_out; + assign PIPETX00CHARISK = PIPETX00CHARISK_out; + assign PIPETX00COMPLIANCE = PIPETX00COMPLIANCE_out; + assign PIPETX00DATA = PIPETX00DATA_out; + assign PIPETX00DATAVALID = PIPETX00DATAVALID_out; + assign PIPETX00ELECIDLE = PIPETX00ELECIDLE_out; + assign PIPETX00EQCONTROL = PIPETX00EQCONTROL_out; + assign PIPETX00EQDEEMPH = PIPETX00EQDEEMPH_out; + assign PIPETX00POWERDOWN = PIPETX00POWERDOWN_out; + assign PIPETX00STARTBLOCK = PIPETX00STARTBLOCK_out; + assign PIPETX00SYNCHEADER = PIPETX00SYNCHEADER_out; + assign PIPETX01CHARISK = PIPETX01CHARISK_out; + assign PIPETX01COMPLIANCE = PIPETX01COMPLIANCE_out; + assign PIPETX01DATA = PIPETX01DATA_out; + assign PIPETX01DATAVALID = PIPETX01DATAVALID_out; + assign PIPETX01ELECIDLE = PIPETX01ELECIDLE_out; + assign PIPETX01EQCONTROL = PIPETX01EQCONTROL_out; + assign PIPETX01EQDEEMPH = PIPETX01EQDEEMPH_out; + assign PIPETX01POWERDOWN = PIPETX01POWERDOWN_out; + assign PIPETX01STARTBLOCK = PIPETX01STARTBLOCK_out; + assign PIPETX01SYNCHEADER = PIPETX01SYNCHEADER_out; + assign PIPETX02CHARISK = PIPETX02CHARISK_out; + assign PIPETX02COMPLIANCE = PIPETX02COMPLIANCE_out; + assign PIPETX02DATA = PIPETX02DATA_out; + assign PIPETX02DATAVALID = PIPETX02DATAVALID_out; + assign PIPETX02ELECIDLE = PIPETX02ELECIDLE_out; + assign PIPETX02EQCONTROL = PIPETX02EQCONTROL_out; + assign PIPETX02EQDEEMPH = PIPETX02EQDEEMPH_out; + assign PIPETX02POWERDOWN = PIPETX02POWERDOWN_out; + assign PIPETX02STARTBLOCK = PIPETX02STARTBLOCK_out; + assign PIPETX02SYNCHEADER = PIPETX02SYNCHEADER_out; + assign PIPETX03CHARISK = PIPETX03CHARISK_out; + assign PIPETX03COMPLIANCE = PIPETX03COMPLIANCE_out; + assign PIPETX03DATA = PIPETX03DATA_out; + assign PIPETX03DATAVALID = PIPETX03DATAVALID_out; + assign PIPETX03ELECIDLE = PIPETX03ELECIDLE_out; + assign PIPETX03EQCONTROL = PIPETX03EQCONTROL_out; + assign PIPETX03EQDEEMPH = PIPETX03EQDEEMPH_out; + assign PIPETX03POWERDOWN = PIPETX03POWERDOWN_out; + assign PIPETX03STARTBLOCK = PIPETX03STARTBLOCK_out; + assign PIPETX03SYNCHEADER = PIPETX03SYNCHEADER_out; + assign PIPETX04CHARISK = PIPETX04CHARISK_out; + assign PIPETX04COMPLIANCE = PIPETX04COMPLIANCE_out; + assign PIPETX04DATA = PIPETX04DATA_out; + assign PIPETX04DATAVALID = PIPETX04DATAVALID_out; + assign PIPETX04ELECIDLE = PIPETX04ELECIDLE_out; + assign PIPETX04EQCONTROL = PIPETX04EQCONTROL_out; + assign PIPETX04EQDEEMPH = PIPETX04EQDEEMPH_out; + assign PIPETX04POWERDOWN = PIPETX04POWERDOWN_out; + assign PIPETX04STARTBLOCK = PIPETX04STARTBLOCK_out; + assign PIPETX04SYNCHEADER = PIPETX04SYNCHEADER_out; + assign PIPETX05CHARISK = PIPETX05CHARISK_out; + assign PIPETX05COMPLIANCE = PIPETX05COMPLIANCE_out; + assign PIPETX05DATA = PIPETX05DATA_out; + assign PIPETX05DATAVALID = PIPETX05DATAVALID_out; + assign PIPETX05ELECIDLE = PIPETX05ELECIDLE_out; + assign PIPETX05EQCONTROL = PIPETX05EQCONTROL_out; + assign PIPETX05EQDEEMPH = PIPETX05EQDEEMPH_out; + assign PIPETX05POWERDOWN = PIPETX05POWERDOWN_out; + assign PIPETX05STARTBLOCK = PIPETX05STARTBLOCK_out; + assign PIPETX05SYNCHEADER = PIPETX05SYNCHEADER_out; + assign PIPETX06CHARISK = PIPETX06CHARISK_out; + assign PIPETX06COMPLIANCE = PIPETX06COMPLIANCE_out; + assign PIPETX06DATA = PIPETX06DATA_out; + assign PIPETX06DATAVALID = PIPETX06DATAVALID_out; + assign PIPETX06ELECIDLE = PIPETX06ELECIDLE_out; + assign PIPETX06EQCONTROL = PIPETX06EQCONTROL_out; + assign PIPETX06EQDEEMPH = PIPETX06EQDEEMPH_out; + assign PIPETX06POWERDOWN = PIPETX06POWERDOWN_out; + assign PIPETX06STARTBLOCK = PIPETX06STARTBLOCK_out; + assign PIPETX06SYNCHEADER = PIPETX06SYNCHEADER_out; + assign PIPETX07CHARISK = PIPETX07CHARISK_out; + assign PIPETX07COMPLIANCE = PIPETX07COMPLIANCE_out; + assign PIPETX07DATA = PIPETX07DATA_out; + assign PIPETX07DATAVALID = PIPETX07DATAVALID_out; + assign PIPETX07ELECIDLE = PIPETX07ELECIDLE_out; + assign PIPETX07EQCONTROL = PIPETX07EQCONTROL_out; + assign PIPETX07EQDEEMPH = PIPETX07EQDEEMPH_out; + assign PIPETX07POWERDOWN = PIPETX07POWERDOWN_out; + assign PIPETX07STARTBLOCK = PIPETX07STARTBLOCK_out; + assign PIPETX07SYNCHEADER = PIPETX07SYNCHEADER_out; + assign PIPETX08CHARISK = PIPETX08CHARISK_out; + assign PIPETX08COMPLIANCE = PIPETX08COMPLIANCE_out; + assign PIPETX08DATA = PIPETX08DATA_out; + assign PIPETX08DATAVALID = PIPETX08DATAVALID_out; + assign PIPETX08ELECIDLE = PIPETX08ELECIDLE_out; + assign PIPETX08EQCONTROL = PIPETX08EQCONTROL_out; + assign PIPETX08EQDEEMPH = PIPETX08EQDEEMPH_out; + assign PIPETX08POWERDOWN = PIPETX08POWERDOWN_out; + assign PIPETX08STARTBLOCK = PIPETX08STARTBLOCK_out; + assign PIPETX08SYNCHEADER = PIPETX08SYNCHEADER_out; + assign PIPETX09CHARISK = PIPETX09CHARISK_out; + assign PIPETX09COMPLIANCE = PIPETX09COMPLIANCE_out; + assign PIPETX09DATA = PIPETX09DATA_out; + assign PIPETX09DATAVALID = PIPETX09DATAVALID_out; + assign PIPETX09ELECIDLE = PIPETX09ELECIDLE_out; + assign PIPETX09EQCONTROL = PIPETX09EQCONTROL_out; + assign PIPETX09EQDEEMPH = PIPETX09EQDEEMPH_out; + assign PIPETX09POWERDOWN = PIPETX09POWERDOWN_out; + assign PIPETX09STARTBLOCK = PIPETX09STARTBLOCK_out; + assign PIPETX09SYNCHEADER = PIPETX09SYNCHEADER_out; + assign PIPETX10CHARISK = PIPETX10CHARISK_out; + assign PIPETX10COMPLIANCE = PIPETX10COMPLIANCE_out; + assign PIPETX10DATA = PIPETX10DATA_out; + assign PIPETX10DATAVALID = PIPETX10DATAVALID_out; + assign PIPETX10ELECIDLE = PIPETX10ELECIDLE_out; + assign PIPETX10EQCONTROL = PIPETX10EQCONTROL_out; + assign PIPETX10EQDEEMPH = PIPETX10EQDEEMPH_out; + assign PIPETX10POWERDOWN = PIPETX10POWERDOWN_out; + assign PIPETX10STARTBLOCK = PIPETX10STARTBLOCK_out; + assign PIPETX10SYNCHEADER = PIPETX10SYNCHEADER_out; + assign PIPETX11CHARISK = PIPETX11CHARISK_out; + assign PIPETX11COMPLIANCE = PIPETX11COMPLIANCE_out; + assign PIPETX11DATA = PIPETX11DATA_out; + assign PIPETX11DATAVALID = PIPETX11DATAVALID_out; + assign PIPETX11ELECIDLE = PIPETX11ELECIDLE_out; + assign PIPETX11EQCONTROL = PIPETX11EQCONTROL_out; + assign PIPETX11EQDEEMPH = PIPETX11EQDEEMPH_out; + assign PIPETX11POWERDOWN = PIPETX11POWERDOWN_out; + assign PIPETX11STARTBLOCK = PIPETX11STARTBLOCK_out; + assign PIPETX11SYNCHEADER = PIPETX11SYNCHEADER_out; + assign PIPETX12CHARISK = PIPETX12CHARISK_out; + assign PIPETX12COMPLIANCE = PIPETX12COMPLIANCE_out; + assign PIPETX12DATA = PIPETX12DATA_out; + assign PIPETX12DATAVALID = PIPETX12DATAVALID_out; + assign PIPETX12ELECIDLE = PIPETX12ELECIDLE_out; + assign PIPETX12EQCONTROL = PIPETX12EQCONTROL_out; + assign PIPETX12EQDEEMPH = PIPETX12EQDEEMPH_out; + assign PIPETX12POWERDOWN = PIPETX12POWERDOWN_out; + assign PIPETX12STARTBLOCK = PIPETX12STARTBLOCK_out; + assign PIPETX12SYNCHEADER = PIPETX12SYNCHEADER_out; + assign PIPETX13CHARISK = PIPETX13CHARISK_out; + assign PIPETX13COMPLIANCE = PIPETX13COMPLIANCE_out; + assign PIPETX13DATA = PIPETX13DATA_out; + assign PIPETX13DATAVALID = PIPETX13DATAVALID_out; + assign PIPETX13ELECIDLE = PIPETX13ELECIDLE_out; + assign PIPETX13EQCONTROL = PIPETX13EQCONTROL_out; + assign PIPETX13EQDEEMPH = PIPETX13EQDEEMPH_out; + assign PIPETX13POWERDOWN = PIPETX13POWERDOWN_out; + assign PIPETX13STARTBLOCK = PIPETX13STARTBLOCK_out; + assign PIPETX13SYNCHEADER = PIPETX13SYNCHEADER_out; + assign PIPETX14CHARISK = PIPETX14CHARISK_out; + assign PIPETX14COMPLIANCE = PIPETX14COMPLIANCE_out; + assign PIPETX14DATA = PIPETX14DATA_out; + assign PIPETX14DATAVALID = PIPETX14DATAVALID_out; + assign PIPETX14ELECIDLE = PIPETX14ELECIDLE_out; + assign PIPETX14EQCONTROL = PIPETX14EQCONTROL_out; + assign PIPETX14EQDEEMPH = PIPETX14EQDEEMPH_out; + assign PIPETX14POWERDOWN = PIPETX14POWERDOWN_out; + assign PIPETX14STARTBLOCK = PIPETX14STARTBLOCK_out; + assign PIPETX14SYNCHEADER = PIPETX14SYNCHEADER_out; + assign PIPETX15CHARISK = PIPETX15CHARISK_out; + assign PIPETX15COMPLIANCE = PIPETX15COMPLIANCE_out; + assign PIPETX15DATA = PIPETX15DATA_out; + assign PIPETX15DATAVALID = PIPETX15DATAVALID_out; + assign PIPETX15ELECIDLE = PIPETX15ELECIDLE_out; + assign PIPETX15EQCONTROL = PIPETX15EQCONTROL_out; + assign PIPETX15EQDEEMPH = PIPETX15EQDEEMPH_out; + assign PIPETX15POWERDOWN = PIPETX15POWERDOWN_out; + assign PIPETX15STARTBLOCK = PIPETX15STARTBLOCK_out; + assign PIPETX15SYNCHEADER = PIPETX15SYNCHEADER_out; + assign PIPETXDEEMPH = PIPETXDEEMPH_out; + assign PIPETXMARGIN = PIPETXMARGIN_out; + assign PIPETXRATE = PIPETXRATE_out; + assign PIPETXRCVRDET = PIPETXRCVRDET_out; + assign PIPETXRESET = PIPETXRESET_out; + assign PIPETXSWING = PIPETXSWING_out; + assign PLEQINPROGRESS = PLEQINPROGRESS_out; + assign PLEQPHASE = PLEQPHASE_out; + assign PLGEN34EQMISMATCH = PLGEN34EQMISMATCH_out; + assign SAXISCCTREADY = SAXISCCTREADY_out; + assign SAXISRQTREADY = SAXISRQTREADY_out; + assign USERSPAREOUT = USERSPAREOUT_out; + +`ifdef XIL_TIMING + assign AXIUSERIN_in[0] = (AXIUSERIN[0] !== 1'bz) && AXIUSERIN_delay[0]; // rv 0 + assign AXIUSERIN_in[1] = (AXIUSERIN[1] !== 1'bz) && AXIUSERIN_delay[1]; // rv 0 + assign AXIUSERIN_in[2] = (AXIUSERIN[2] !== 1'bz) && AXIUSERIN_delay[2]; // rv 0 + assign AXIUSERIN_in[3] = (AXIUSERIN[3] !== 1'bz) && AXIUSERIN_delay[3]; // rv 0 + assign AXIUSERIN_in[4] = (AXIUSERIN[4] !== 1'bz) && AXIUSERIN_delay[4]; // rv 0 + assign AXIUSERIN_in[5] = (AXIUSERIN[5] !== 1'bz) && AXIUSERIN_delay[5]; // rv 0 + assign AXIUSERIN_in[6] = (AXIUSERIN[6] !== 1'bz) && AXIUSERIN_delay[6]; // rv 0 + assign AXIUSERIN_in[7] = (AXIUSERIN[7] !== 1'bz) && AXIUSERIN_delay[7]; // rv 0 + assign CFGCONFIGSPACEENABLE_in = (CFGCONFIGSPACEENABLE === 1'bz) || CFGCONFIGSPACEENABLE_delay; // rv 1 + assign CFGDEVIDPF0_in[0] = (CFGDEVIDPF0[0] !== 1'bz) && CFGDEVIDPF0_delay[0]; // rv 0 + assign CFGDEVIDPF0_in[10] = (CFGDEVIDPF0[10] !== 1'bz) && CFGDEVIDPF0_delay[10]; // rv 0 + assign CFGDEVIDPF0_in[11] = (CFGDEVIDPF0[11] !== 1'bz) && CFGDEVIDPF0_delay[11]; // rv 0 + assign CFGDEVIDPF0_in[12] = (CFGDEVIDPF0[12] !== 1'bz) && CFGDEVIDPF0_delay[12]; // rv 0 + assign CFGDEVIDPF0_in[13] = (CFGDEVIDPF0[13] !== 1'bz) && CFGDEVIDPF0_delay[13]; // rv 0 + assign CFGDEVIDPF0_in[14] = (CFGDEVIDPF0[14] !== 1'bz) && CFGDEVIDPF0_delay[14]; // rv 0 + assign CFGDEVIDPF0_in[15] = (CFGDEVIDPF0[15] !== 1'bz) && CFGDEVIDPF0_delay[15]; // rv 0 + assign CFGDEVIDPF0_in[1] = (CFGDEVIDPF0[1] !== 1'bz) && CFGDEVIDPF0_delay[1]; // rv 0 + assign CFGDEVIDPF0_in[2] = (CFGDEVIDPF0[2] !== 1'bz) && CFGDEVIDPF0_delay[2]; // rv 0 + assign CFGDEVIDPF0_in[3] = (CFGDEVIDPF0[3] !== 1'bz) && CFGDEVIDPF0_delay[3]; // rv 0 + assign CFGDEVIDPF0_in[4] = (CFGDEVIDPF0[4] !== 1'bz) && CFGDEVIDPF0_delay[4]; // rv 0 + assign CFGDEVIDPF0_in[5] = (CFGDEVIDPF0[5] !== 1'bz) && CFGDEVIDPF0_delay[5]; // rv 0 + assign CFGDEVIDPF0_in[6] = (CFGDEVIDPF0[6] !== 1'bz) && CFGDEVIDPF0_delay[6]; // rv 0 + assign CFGDEVIDPF0_in[7] = (CFGDEVIDPF0[7] !== 1'bz) && CFGDEVIDPF0_delay[7]; // rv 0 + assign CFGDEVIDPF0_in[8] = (CFGDEVIDPF0[8] !== 1'bz) && CFGDEVIDPF0_delay[8]; // rv 0 + assign CFGDEVIDPF0_in[9] = (CFGDEVIDPF0[9] !== 1'bz) && CFGDEVIDPF0_delay[9]; // rv 0 + assign CFGDEVIDPF1_in[0] = (CFGDEVIDPF1[0] !== 1'bz) && CFGDEVIDPF1_delay[0]; // rv 0 + assign CFGDEVIDPF1_in[10] = (CFGDEVIDPF1[10] !== 1'bz) && CFGDEVIDPF1_delay[10]; // rv 0 + assign CFGDEVIDPF1_in[11] = (CFGDEVIDPF1[11] !== 1'bz) && CFGDEVIDPF1_delay[11]; // rv 0 + assign CFGDEVIDPF1_in[12] = (CFGDEVIDPF1[12] !== 1'bz) && CFGDEVIDPF1_delay[12]; // rv 0 + assign CFGDEVIDPF1_in[13] = (CFGDEVIDPF1[13] !== 1'bz) && CFGDEVIDPF1_delay[13]; // rv 0 + assign CFGDEVIDPF1_in[14] = (CFGDEVIDPF1[14] !== 1'bz) && CFGDEVIDPF1_delay[14]; // rv 0 + assign CFGDEVIDPF1_in[15] = (CFGDEVIDPF1[15] !== 1'bz) && CFGDEVIDPF1_delay[15]; // rv 0 + assign CFGDEVIDPF1_in[1] = (CFGDEVIDPF1[1] !== 1'bz) && CFGDEVIDPF1_delay[1]; // rv 0 + assign CFGDEVIDPF1_in[2] = (CFGDEVIDPF1[2] !== 1'bz) && CFGDEVIDPF1_delay[2]; // rv 0 + assign CFGDEVIDPF1_in[3] = (CFGDEVIDPF1[3] !== 1'bz) && CFGDEVIDPF1_delay[3]; // rv 0 + assign CFGDEVIDPF1_in[4] = (CFGDEVIDPF1[4] !== 1'bz) && CFGDEVIDPF1_delay[4]; // rv 0 + assign CFGDEVIDPF1_in[5] = (CFGDEVIDPF1[5] !== 1'bz) && CFGDEVIDPF1_delay[5]; // rv 0 + assign CFGDEVIDPF1_in[6] = (CFGDEVIDPF1[6] !== 1'bz) && CFGDEVIDPF1_delay[6]; // rv 0 + assign CFGDEVIDPF1_in[7] = (CFGDEVIDPF1[7] !== 1'bz) && CFGDEVIDPF1_delay[7]; // rv 0 + assign CFGDEVIDPF1_in[8] = (CFGDEVIDPF1[8] !== 1'bz) && CFGDEVIDPF1_delay[8]; // rv 0 + assign CFGDEVIDPF1_in[9] = (CFGDEVIDPF1[9] !== 1'bz) && CFGDEVIDPF1_delay[9]; // rv 0 + assign CFGDEVIDPF2_in[0] = (CFGDEVIDPF2[0] !== 1'bz) && CFGDEVIDPF2_delay[0]; // rv 0 + assign CFGDEVIDPF2_in[10] = (CFGDEVIDPF2[10] !== 1'bz) && CFGDEVIDPF2_delay[10]; // rv 0 + assign CFGDEVIDPF2_in[11] = (CFGDEVIDPF2[11] !== 1'bz) && CFGDEVIDPF2_delay[11]; // rv 0 + assign CFGDEVIDPF2_in[12] = (CFGDEVIDPF2[12] !== 1'bz) && CFGDEVIDPF2_delay[12]; // rv 0 + assign CFGDEVIDPF2_in[13] = (CFGDEVIDPF2[13] !== 1'bz) && CFGDEVIDPF2_delay[13]; // rv 0 + assign CFGDEVIDPF2_in[14] = (CFGDEVIDPF2[14] !== 1'bz) && CFGDEVIDPF2_delay[14]; // rv 0 + assign CFGDEVIDPF2_in[15] = (CFGDEVIDPF2[15] !== 1'bz) && CFGDEVIDPF2_delay[15]; // rv 0 + assign CFGDEVIDPF2_in[1] = (CFGDEVIDPF2[1] !== 1'bz) && CFGDEVIDPF2_delay[1]; // rv 0 + assign CFGDEVIDPF2_in[2] = (CFGDEVIDPF2[2] !== 1'bz) && CFGDEVIDPF2_delay[2]; // rv 0 + assign CFGDEVIDPF2_in[3] = (CFGDEVIDPF2[3] !== 1'bz) && CFGDEVIDPF2_delay[3]; // rv 0 + assign CFGDEVIDPF2_in[4] = (CFGDEVIDPF2[4] !== 1'bz) && CFGDEVIDPF2_delay[4]; // rv 0 + assign CFGDEVIDPF2_in[5] = (CFGDEVIDPF2[5] !== 1'bz) && CFGDEVIDPF2_delay[5]; // rv 0 + assign CFGDEVIDPF2_in[6] = (CFGDEVIDPF2[6] !== 1'bz) && CFGDEVIDPF2_delay[6]; // rv 0 + assign CFGDEVIDPF2_in[7] = (CFGDEVIDPF2[7] !== 1'bz) && CFGDEVIDPF2_delay[7]; // rv 0 + assign CFGDEVIDPF2_in[8] = (CFGDEVIDPF2[8] !== 1'bz) && CFGDEVIDPF2_delay[8]; // rv 0 + assign CFGDEVIDPF2_in[9] = (CFGDEVIDPF2[9] !== 1'bz) && CFGDEVIDPF2_delay[9]; // rv 0 + assign CFGDEVIDPF3_in[0] = (CFGDEVIDPF3[0] !== 1'bz) && CFGDEVIDPF3_delay[0]; // rv 0 + assign CFGDEVIDPF3_in[10] = (CFGDEVIDPF3[10] !== 1'bz) && CFGDEVIDPF3_delay[10]; // rv 0 + assign CFGDEVIDPF3_in[11] = (CFGDEVIDPF3[11] !== 1'bz) && CFGDEVIDPF3_delay[11]; // rv 0 + assign CFGDEVIDPF3_in[12] = (CFGDEVIDPF3[12] !== 1'bz) && CFGDEVIDPF3_delay[12]; // rv 0 + assign CFGDEVIDPF3_in[13] = (CFGDEVIDPF3[13] !== 1'bz) && CFGDEVIDPF3_delay[13]; // rv 0 + assign CFGDEVIDPF3_in[14] = (CFGDEVIDPF3[14] !== 1'bz) && CFGDEVIDPF3_delay[14]; // rv 0 + assign CFGDEVIDPF3_in[15] = (CFGDEVIDPF3[15] !== 1'bz) && CFGDEVIDPF3_delay[15]; // rv 0 + assign CFGDEVIDPF3_in[1] = (CFGDEVIDPF3[1] !== 1'bz) && CFGDEVIDPF3_delay[1]; // rv 0 + assign CFGDEVIDPF3_in[2] = (CFGDEVIDPF3[2] !== 1'bz) && CFGDEVIDPF3_delay[2]; // rv 0 + assign CFGDEVIDPF3_in[3] = (CFGDEVIDPF3[3] !== 1'bz) && CFGDEVIDPF3_delay[3]; // rv 0 + assign CFGDEVIDPF3_in[4] = (CFGDEVIDPF3[4] !== 1'bz) && CFGDEVIDPF3_delay[4]; // rv 0 + assign CFGDEVIDPF3_in[5] = (CFGDEVIDPF3[5] !== 1'bz) && CFGDEVIDPF3_delay[5]; // rv 0 + assign CFGDEVIDPF3_in[6] = (CFGDEVIDPF3[6] !== 1'bz) && CFGDEVIDPF3_delay[6]; // rv 0 + assign CFGDEVIDPF3_in[7] = (CFGDEVIDPF3[7] !== 1'bz) && CFGDEVIDPF3_delay[7]; // rv 0 + assign CFGDEVIDPF3_in[8] = (CFGDEVIDPF3[8] !== 1'bz) && CFGDEVIDPF3_delay[8]; // rv 0 + assign CFGDEVIDPF3_in[9] = (CFGDEVIDPF3[9] !== 1'bz) && CFGDEVIDPF3_delay[9]; // rv 0 + assign CFGDSBUSNUMBER_in[0] = (CFGDSBUSNUMBER[0] !== 1'bz) && CFGDSBUSNUMBER_delay[0]; // rv 0 + assign CFGDSBUSNUMBER_in[1] = (CFGDSBUSNUMBER[1] !== 1'bz) && CFGDSBUSNUMBER_delay[1]; // rv 0 + assign CFGDSBUSNUMBER_in[2] = (CFGDSBUSNUMBER[2] !== 1'bz) && CFGDSBUSNUMBER_delay[2]; // rv 0 + assign CFGDSBUSNUMBER_in[3] = (CFGDSBUSNUMBER[3] !== 1'bz) && CFGDSBUSNUMBER_delay[3]; // rv 0 + assign CFGDSBUSNUMBER_in[4] = (CFGDSBUSNUMBER[4] !== 1'bz) && CFGDSBUSNUMBER_delay[4]; // rv 0 + assign CFGDSBUSNUMBER_in[5] = (CFGDSBUSNUMBER[5] !== 1'bz) && CFGDSBUSNUMBER_delay[5]; // rv 0 + assign CFGDSBUSNUMBER_in[6] = (CFGDSBUSNUMBER[6] !== 1'bz) && CFGDSBUSNUMBER_delay[6]; // rv 0 + assign CFGDSBUSNUMBER_in[7] = (CFGDSBUSNUMBER[7] !== 1'bz) && CFGDSBUSNUMBER_delay[7]; // rv 0 + assign CFGDSDEVICENUMBER_in[0] = (CFGDSDEVICENUMBER[0] !== 1'bz) && CFGDSDEVICENUMBER_delay[0]; // rv 0 + assign CFGDSDEVICENUMBER_in[1] = (CFGDSDEVICENUMBER[1] !== 1'bz) && CFGDSDEVICENUMBER_delay[1]; // rv 0 + assign CFGDSDEVICENUMBER_in[2] = (CFGDSDEVICENUMBER[2] !== 1'bz) && CFGDSDEVICENUMBER_delay[2]; // rv 0 + assign CFGDSDEVICENUMBER_in[3] = (CFGDSDEVICENUMBER[3] !== 1'bz) && CFGDSDEVICENUMBER_delay[3]; // rv 0 + assign CFGDSDEVICENUMBER_in[4] = (CFGDSDEVICENUMBER[4] !== 1'bz) && CFGDSDEVICENUMBER_delay[4]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[0] = (CFGDSFUNCTIONNUMBER[0] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[1] = (CFGDSFUNCTIONNUMBER[1] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[2] = (CFGDSFUNCTIONNUMBER[2] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGDSN_in[0] = (CFGDSN[0] !== 1'bz) && CFGDSN_delay[0]; // rv 0 + assign CFGDSN_in[10] = (CFGDSN[10] !== 1'bz) && CFGDSN_delay[10]; // rv 0 + assign CFGDSN_in[11] = (CFGDSN[11] !== 1'bz) && CFGDSN_delay[11]; // rv 0 + assign CFGDSN_in[12] = (CFGDSN[12] !== 1'bz) && CFGDSN_delay[12]; // rv 0 + assign CFGDSN_in[13] = (CFGDSN[13] !== 1'bz) && CFGDSN_delay[13]; // rv 0 + assign CFGDSN_in[14] = (CFGDSN[14] !== 1'bz) && CFGDSN_delay[14]; // rv 0 + assign CFGDSN_in[15] = (CFGDSN[15] !== 1'bz) && CFGDSN_delay[15]; // rv 0 + assign CFGDSN_in[16] = (CFGDSN[16] !== 1'bz) && CFGDSN_delay[16]; // rv 0 + assign CFGDSN_in[17] = (CFGDSN[17] !== 1'bz) && CFGDSN_delay[17]; // rv 0 + assign CFGDSN_in[18] = (CFGDSN[18] !== 1'bz) && CFGDSN_delay[18]; // rv 0 + assign CFGDSN_in[19] = (CFGDSN[19] !== 1'bz) && CFGDSN_delay[19]; // rv 0 + assign CFGDSN_in[1] = (CFGDSN[1] !== 1'bz) && CFGDSN_delay[1]; // rv 0 + assign CFGDSN_in[20] = (CFGDSN[20] !== 1'bz) && CFGDSN_delay[20]; // rv 0 + assign CFGDSN_in[21] = (CFGDSN[21] !== 1'bz) && CFGDSN_delay[21]; // rv 0 + assign CFGDSN_in[22] = (CFGDSN[22] !== 1'bz) && CFGDSN_delay[22]; // rv 0 + assign CFGDSN_in[23] = (CFGDSN[23] !== 1'bz) && CFGDSN_delay[23]; // rv 0 + assign CFGDSN_in[24] = (CFGDSN[24] !== 1'bz) && CFGDSN_delay[24]; // rv 0 + assign CFGDSN_in[25] = (CFGDSN[25] !== 1'bz) && CFGDSN_delay[25]; // rv 0 + assign CFGDSN_in[26] = (CFGDSN[26] !== 1'bz) && CFGDSN_delay[26]; // rv 0 + assign CFGDSN_in[27] = (CFGDSN[27] !== 1'bz) && CFGDSN_delay[27]; // rv 0 + assign CFGDSN_in[28] = (CFGDSN[28] !== 1'bz) && CFGDSN_delay[28]; // rv 0 + assign CFGDSN_in[29] = (CFGDSN[29] !== 1'bz) && CFGDSN_delay[29]; // rv 0 + assign CFGDSN_in[2] = (CFGDSN[2] !== 1'bz) && CFGDSN_delay[2]; // rv 0 + assign CFGDSN_in[30] = (CFGDSN[30] !== 1'bz) && CFGDSN_delay[30]; // rv 0 + assign CFGDSN_in[31] = (CFGDSN[31] !== 1'bz) && CFGDSN_delay[31]; // rv 0 + assign CFGDSN_in[32] = (CFGDSN[32] !== 1'bz) && CFGDSN_delay[32]; // rv 0 + assign CFGDSN_in[33] = (CFGDSN[33] !== 1'bz) && CFGDSN_delay[33]; // rv 0 + assign CFGDSN_in[34] = (CFGDSN[34] !== 1'bz) && CFGDSN_delay[34]; // rv 0 + assign CFGDSN_in[35] = (CFGDSN[35] !== 1'bz) && CFGDSN_delay[35]; // rv 0 + assign CFGDSN_in[36] = (CFGDSN[36] !== 1'bz) && CFGDSN_delay[36]; // rv 0 + assign CFGDSN_in[37] = (CFGDSN[37] !== 1'bz) && CFGDSN_delay[37]; // rv 0 + assign CFGDSN_in[38] = (CFGDSN[38] !== 1'bz) && CFGDSN_delay[38]; // rv 0 + assign CFGDSN_in[39] = (CFGDSN[39] !== 1'bz) && CFGDSN_delay[39]; // rv 0 + assign CFGDSN_in[3] = (CFGDSN[3] !== 1'bz) && CFGDSN_delay[3]; // rv 0 + assign CFGDSN_in[40] = (CFGDSN[40] !== 1'bz) && CFGDSN_delay[40]; // rv 0 + assign CFGDSN_in[41] = (CFGDSN[41] !== 1'bz) && CFGDSN_delay[41]; // rv 0 + assign CFGDSN_in[42] = (CFGDSN[42] !== 1'bz) && CFGDSN_delay[42]; // rv 0 + assign CFGDSN_in[43] = (CFGDSN[43] !== 1'bz) && CFGDSN_delay[43]; // rv 0 + assign CFGDSN_in[44] = (CFGDSN[44] !== 1'bz) && CFGDSN_delay[44]; // rv 0 + assign CFGDSN_in[45] = (CFGDSN[45] !== 1'bz) && CFGDSN_delay[45]; // rv 0 + assign CFGDSN_in[46] = (CFGDSN[46] !== 1'bz) && CFGDSN_delay[46]; // rv 0 + assign CFGDSN_in[47] = (CFGDSN[47] !== 1'bz) && CFGDSN_delay[47]; // rv 0 + assign CFGDSN_in[48] = (CFGDSN[48] !== 1'bz) && CFGDSN_delay[48]; // rv 0 + assign CFGDSN_in[49] = (CFGDSN[49] !== 1'bz) && CFGDSN_delay[49]; // rv 0 + assign CFGDSN_in[4] = (CFGDSN[4] !== 1'bz) && CFGDSN_delay[4]; // rv 0 + assign CFGDSN_in[50] = (CFGDSN[50] !== 1'bz) && CFGDSN_delay[50]; // rv 0 + assign CFGDSN_in[51] = (CFGDSN[51] !== 1'bz) && CFGDSN_delay[51]; // rv 0 + assign CFGDSN_in[52] = (CFGDSN[52] !== 1'bz) && CFGDSN_delay[52]; // rv 0 + assign CFGDSN_in[53] = (CFGDSN[53] !== 1'bz) && CFGDSN_delay[53]; // rv 0 + assign CFGDSN_in[54] = (CFGDSN[54] !== 1'bz) && CFGDSN_delay[54]; // rv 0 + assign CFGDSN_in[55] = (CFGDSN[55] !== 1'bz) && CFGDSN_delay[55]; // rv 0 + assign CFGDSN_in[56] = (CFGDSN[56] !== 1'bz) && CFGDSN_delay[56]; // rv 0 + assign CFGDSN_in[57] = (CFGDSN[57] !== 1'bz) && CFGDSN_delay[57]; // rv 0 + assign CFGDSN_in[58] = (CFGDSN[58] !== 1'bz) && CFGDSN_delay[58]; // rv 0 + assign CFGDSN_in[59] = (CFGDSN[59] !== 1'bz) && CFGDSN_delay[59]; // rv 0 + assign CFGDSN_in[5] = (CFGDSN[5] !== 1'bz) && CFGDSN_delay[5]; // rv 0 + assign CFGDSN_in[60] = (CFGDSN[60] !== 1'bz) && CFGDSN_delay[60]; // rv 0 + assign CFGDSN_in[61] = (CFGDSN[61] !== 1'bz) && CFGDSN_delay[61]; // rv 0 + assign CFGDSN_in[62] = (CFGDSN[62] !== 1'bz) && CFGDSN_delay[62]; // rv 0 + assign CFGDSN_in[63] = (CFGDSN[63] !== 1'bz) && CFGDSN_delay[63]; // rv 0 + assign CFGDSN_in[6] = (CFGDSN[6] !== 1'bz) && CFGDSN_delay[6]; // rv 0 + assign CFGDSN_in[7] = (CFGDSN[7] !== 1'bz) && CFGDSN_delay[7]; // rv 0 + assign CFGDSN_in[8] = (CFGDSN[8] !== 1'bz) && CFGDSN_delay[8]; // rv 0 + assign CFGDSN_in[9] = (CFGDSN[9] !== 1'bz) && CFGDSN_delay[9]; // rv 0 + assign CFGDSPORTNUMBER_in[0] = (CFGDSPORTNUMBER[0] !== 1'bz) && CFGDSPORTNUMBER_delay[0]; // rv 0 + assign CFGDSPORTNUMBER_in[1] = (CFGDSPORTNUMBER[1] !== 1'bz) && CFGDSPORTNUMBER_delay[1]; // rv 0 + assign CFGDSPORTNUMBER_in[2] = (CFGDSPORTNUMBER[2] !== 1'bz) && CFGDSPORTNUMBER_delay[2]; // rv 0 + assign CFGDSPORTNUMBER_in[3] = (CFGDSPORTNUMBER[3] !== 1'bz) && CFGDSPORTNUMBER_delay[3]; // rv 0 + assign CFGDSPORTNUMBER_in[4] = (CFGDSPORTNUMBER[4] !== 1'bz) && CFGDSPORTNUMBER_delay[4]; // rv 0 + assign CFGDSPORTNUMBER_in[5] = (CFGDSPORTNUMBER[5] !== 1'bz) && CFGDSPORTNUMBER_delay[5]; // rv 0 + assign CFGDSPORTNUMBER_in[6] = (CFGDSPORTNUMBER[6] !== 1'bz) && CFGDSPORTNUMBER_delay[6]; // rv 0 + assign CFGDSPORTNUMBER_in[7] = (CFGDSPORTNUMBER[7] !== 1'bz) && CFGDSPORTNUMBER_delay[7]; // rv 0 + assign CFGERRCORIN_in = (CFGERRCORIN !== 1'bz) && CFGERRCORIN_delay; // rv 0 + assign CFGERRUNCORIN_in = (CFGERRUNCORIN !== 1'bz) && CFGERRUNCORIN_delay; // rv 0 + assign CFGEXTREADDATAVALID_in = (CFGEXTREADDATAVALID !== 1'bz) && CFGEXTREADDATAVALID_delay; // rv 0 + assign CFGEXTREADDATA_in[0] = (CFGEXTREADDATA[0] !== 1'bz) && CFGEXTREADDATA_delay[0]; // rv 0 + assign CFGEXTREADDATA_in[10] = (CFGEXTREADDATA[10] !== 1'bz) && CFGEXTREADDATA_delay[10]; // rv 0 + assign CFGEXTREADDATA_in[11] = (CFGEXTREADDATA[11] !== 1'bz) && CFGEXTREADDATA_delay[11]; // rv 0 + assign CFGEXTREADDATA_in[12] = (CFGEXTREADDATA[12] !== 1'bz) && CFGEXTREADDATA_delay[12]; // rv 0 + assign CFGEXTREADDATA_in[13] = (CFGEXTREADDATA[13] !== 1'bz) && CFGEXTREADDATA_delay[13]; // rv 0 + assign CFGEXTREADDATA_in[14] = (CFGEXTREADDATA[14] !== 1'bz) && CFGEXTREADDATA_delay[14]; // rv 0 + assign CFGEXTREADDATA_in[15] = (CFGEXTREADDATA[15] !== 1'bz) && CFGEXTREADDATA_delay[15]; // rv 0 + assign CFGEXTREADDATA_in[16] = (CFGEXTREADDATA[16] !== 1'bz) && CFGEXTREADDATA_delay[16]; // rv 0 + assign CFGEXTREADDATA_in[17] = (CFGEXTREADDATA[17] !== 1'bz) && CFGEXTREADDATA_delay[17]; // rv 0 + assign CFGEXTREADDATA_in[18] = (CFGEXTREADDATA[18] !== 1'bz) && CFGEXTREADDATA_delay[18]; // rv 0 + assign CFGEXTREADDATA_in[19] = (CFGEXTREADDATA[19] !== 1'bz) && CFGEXTREADDATA_delay[19]; // rv 0 + assign CFGEXTREADDATA_in[1] = (CFGEXTREADDATA[1] !== 1'bz) && CFGEXTREADDATA_delay[1]; // rv 0 + assign CFGEXTREADDATA_in[20] = (CFGEXTREADDATA[20] !== 1'bz) && CFGEXTREADDATA_delay[20]; // rv 0 + assign CFGEXTREADDATA_in[21] = (CFGEXTREADDATA[21] !== 1'bz) && CFGEXTREADDATA_delay[21]; // rv 0 + assign CFGEXTREADDATA_in[22] = (CFGEXTREADDATA[22] !== 1'bz) && CFGEXTREADDATA_delay[22]; // rv 0 + assign CFGEXTREADDATA_in[23] = (CFGEXTREADDATA[23] !== 1'bz) && CFGEXTREADDATA_delay[23]; // rv 0 + assign CFGEXTREADDATA_in[24] = (CFGEXTREADDATA[24] !== 1'bz) && CFGEXTREADDATA_delay[24]; // rv 0 + assign CFGEXTREADDATA_in[25] = (CFGEXTREADDATA[25] !== 1'bz) && CFGEXTREADDATA_delay[25]; // rv 0 + assign CFGEXTREADDATA_in[26] = (CFGEXTREADDATA[26] !== 1'bz) && CFGEXTREADDATA_delay[26]; // rv 0 + assign CFGEXTREADDATA_in[27] = (CFGEXTREADDATA[27] !== 1'bz) && CFGEXTREADDATA_delay[27]; // rv 0 + assign CFGEXTREADDATA_in[28] = (CFGEXTREADDATA[28] !== 1'bz) && CFGEXTREADDATA_delay[28]; // rv 0 + assign CFGEXTREADDATA_in[29] = (CFGEXTREADDATA[29] !== 1'bz) && CFGEXTREADDATA_delay[29]; // rv 0 + assign CFGEXTREADDATA_in[2] = (CFGEXTREADDATA[2] !== 1'bz) && CFGEXTREADDATA_delay[2]; // rv 0 + assign CFGEXTREADDATA_in[30] = (CFGEXTREADDATA[30] !== 1'bz) && CFGEXTREADDATA_delay[30]; // rv 0 + assign CFGEXTREADDATA_in[31] = (CFGEXTREADDATA[31] !== 1'bz) && CFGEXTREADDATA_delay[31]; // rv 0 + assign CFGEXTREADDATA_in[3] = (CFGEXTREADDATA[3] !== 1'bz) && CFGEXTREADDATA_delay[3]; // rv 0 + assign CFGEXTREADDATA_in[4] = (CFGEXTREADDATA[4] !== 1'bz) && CFGEXTREADDATA_delay[4]; // rv 0 + assign CFGEXTREADDATA_in[5] = (CFGEXTREADDATA[5] !== 1'bz) && CFGEXTREADDATA_delay[5]; // rv 0 + assign CFGEXTREADDATA_in[6] = (CFGEXTREADDATA[6] !== 1'bz) && CFGEXTREADDATA_delay[6]; // rv 0 + assign CFGEXTREADDATA_in[7] = (CFGEXTREADDATA[7] !== 1'bz) && CFGEXTREADDATA_delay[7]; // rv 0 + assign CFGEXTREADDATA_in[8] = (CFGEXTREADDATA[8] !== 1'bz) && CFGEXTREADDATA_delay[8]; // rv 0 + assign CFGEXTREADDATA_in[9] = (CFGEXTREADDATA[9] !== 1'bz) && CFGEXTREADDATA_delay[9]; // rv 0 + assign CFGFCSEL_in[0] = (CFGFCSEL[0] !== 1'bz) && CFGFCSEL_delay[0]; // rv 0 + assign CFGFCSEL_in[1] = (CFGFCSEL[1] !== 1'bz) && CFGFCSEL_delay[1]; // rv 0 + assign CFGFCSEL_in[2] = (CFGFCSEL[2] !== 1'bz) && CFGFCSEL_delay[2]; // rv 0 + assign CFGFLRDONE_in[0] = (CFGFLRDONE[0] !== 1'bz) && CFGFLRDONE_delay[0]; // rv 0 + assign CFGFLRDONE_in[1] = (CFGFLRDONE[1] !== 1'bz) && CFGFLRDONE_delay[1]; // rv 0 + assign CFGFLRDONE_in[2] = (CFGFLRDONE[2] !== 1'bz) && CFGFLRDONE_delay[2]; // rv 0 + assign CFGFLRDONE_in[3] = (CFGFLRDONE[3] !== 1'bz) && CFGFLRDONE_delay[3]; // rv 0 + assign CFGHOTRESETIN_in = (CFGHOTRESETIN !== 1'bz) && CFGHOTRESETIN_delay; // rv 0 + assign CFGINTERRUPTINT_in[0] = (CFGINTERRUPTINT[0] !== 1'bz) && CFGINTERRUPTINT_delay[0]; // rv 0 + assign CFGINTERRUPTINT_in[1] = (CFGINTERRUPTINT[1] !== 1'bz) && CFGINTERRUPTINT_delay[1]; // rv 0 + assign CFGINTERRUPTINT_in[2] = (CFGINTERRUPTINT[2] !== 1'bz) && CFGINTERRUPTINT_delay[2]; // rv 0 + assign CFGINTERRUPTINT_in[3] = (CFGINTERRUPTINT[3] !== 1'bz) && CFGINTERRUPTINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[0] = (CFGINTERRUPTMSIATTR[0] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[0]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[1] = (CFGINTERRUPTMSIATTR[1] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[1]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[2] = (CFGINTERRUPTMSIATTR[2] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[0] = (CFGINTERRUPTMSIFUNCTIONNUMBER[0] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[1] = (CFGINTERRUPTMSIFUNCTIONNUMBER[1] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[2] = (CFGINTERRUPTMSIFUNCTIONNUMBER[2] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[3] = (CFGINTERRUPTMSIFUNCTIONNUMBER[3] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[4] = (CFGINTERRUPTMSIFUNCTIONNUMBER[4] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[5] = (CFGINTERRUPTMSIFUNCTIONNUMBER[5] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[6] = (CFGINTERRUPTMSIFUNCTIONNUMBER[6] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[7] = (CFGINTERRUPTMSIFUNCTIONNUMBER[7] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[0] = (CFGINTERRUPTMSIINT[0] !== 1'bz) && CFGINTERRUPTMSIINT_delay[0]; // rv 0 + assign CFGINTERRUPTMSIINT_in[10] = (CFGINTERRUPTMSIINT[10] !== 1'bz) && CFGINTERRUPTMSIINT_delay[10]; // rv 0 + assign CFGINTERRUPTMSIINT_in[11] = (CFGINTERRUPTMSIINT[11] !== 1'bz) && CFGINTERRUPTMSIINT_delay[11]; // rv 0 + assign CFGINTERRUPTMSIINT_in[12] = (CFGINTERRUPTMSIINT[12] !== 1'bz) && CFGINTERRUPTMSIINT_delay[12]; // rv 0 + assign CFGINTERRUPTMSIINT_in[13] = (CFGINTERRUPTMSIINT[13] !== 1'bz) && CFGINTERRUPTMSIINT_delay[13]; // rv 0 + assign CFGINTERRUPTMSIINT_in[14] = (CFGINTERRUPTMSIINT[14] !== 1'bz) && CFGINTERRUPTMSIINT_delay[14]; // rv 0 + assign CFGINTERRUPTMSIINT_in[15] = (CFGINTERRUPTMSIINT[15] !== 1'bz) && CFGINTERRUPTMSIINT_delay[15]; // rv 0 + assign CFGINTERRUPTMSIINT_in[16] = (CFGINTERRUPTMSIINT[16] !== 1'bz) && CFGINTERRUPTMSIINT_delay[16]; // rv 0 + assign CFGINTERRUPTMSIINT_in[17] = (CFGINTERRUPTMSIINT[17] !== 1'bz) && CFGINTERRUPTMSIINT_delay[17]; // rv 0 + assign CFGINTERRUPTMSIINT_in[18] = (CFGINTERRUPTMSIINT[18] !== 1'bz) && CFGINTERRUPTMSIINT_delay[18]; // rv 0 + assign CFGINTERRUPTMSIINT_in[19] = (CFGINTERRUPTMSIINT[19] !== 1'bz) && CFGINTERRUPTMSIINT_delay[19]; // rv 0 + assign CFGINTERRUPTMSIINT_in[1] = (CFGINTERRUPTMSIINT[1] !== 1'bz) && CFGINTERRUPTMSIINT_delay[1]; // rv 0 + assign CFGINTERRUPTMSIINT_in[20] = (CFGINTERRUPTMSIINT[20] !== 1'bz) && CFGINTERRUPTMSIINT_delay[20]; // rv 0 + assign CFGINTERRUPTMSIINT_in[21] = (CFGINTERRUPTMSIINT[21] !== 1'bz) && CFGINTERRUPTMSIINT_delay[21]; // rv 0 + assign CFGINTERRUPTMSIINT_in[22] = (CFGINTERRUPTMSIINT[22] !== 1'bz) && CFGINTERRUPTMSIINT_delay[22]; // rv 0 + assign CFGINTERRUPTMSIINT_in[23] = (CFGINTERRUPTMSIINT[23] !== 1'bz) && CFGINTERRUPTMSIINT_delay[23]; // rv 0 + assign CFGINTERRUPTMSIINT_in[24] = (CFGINTERRUPTMSIINT[24] !== 1'bz) && CFGINTERRUPTMSIINT_delay[24]; // rv 0 + assign CFGINTERRUPTMSIINT_in[25] = (CFGINTERRUPTMSIINT[25] !== 1'bz) && CFGINTERRUPTMSIINT_delay[25]; // rv 0 + assign CFGINTERRUPTMSIINT_in[26] = (CFGINTERRUPTMSIINT[26] !== 1'bz) && CFGINTERRUPTMSIINT_delay[26]; // rv 0 + assign CFGINTERRUPTMSIINT_in[27] = (CFGINTERRUPTMSIINT[27] !== 1'bz) && CFGINTERRUPTMSIINT_delay[27]; // rv 0 + assign CFGINTERRUPTMSIINT_in[28] = (CFGINTERRUPTMSIINT[28] !== 1'bz) && CFGINTERRUPTMSIINT_delay[28]; // rv 0 + assign CFGINTERRUPTMSIINT_in[29] = (CFGINTERRUPTMSIINT[29] !== 1'bz) && CFGINTERRUPTMSIINT_delay[29]; // rv 0 + assign CFGINTERRUPTMSIINT_in[2] = (CFGINTERRUPTMSIINT[2] !== 1'bz) && CFGINTERRUPTMSIINT_delay[2]; // rv 0 + assign CFGINTERRUPTMSIINT_in[30] = (CFGINTERRUPTMSIINT[30] !== 1'bz) && CFGINTERRUPTMSIINT_delay[30]; // rv 0 + assign CFGINTERRUPTMSIINT_in[31] = (CFGINTERRUPTMSIINT[31] !== 1'bz) && CFGINTERRUPTMSIINT_delay[31]; // rv 0 + assign CFGINTERRUPTMSIINT_in[3] = (CFGINTERRUPTMSIINT[3] !== 1'bz) && CFGINTERRUPTMSIINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[4] = (CFGINTERRUPTMSIINT[4] !== 1'bz) && CFGINTERRUPTMSIINT_delay[4]; // rv 0 + assign CFGINTERRUPTMSIINT_in[5] = (CFGINTERRUPTMSIINT[5] !== 1'bz) && CFGINTERRUPTMSIINT_delay[5]; // rv 0 + assign CFGINTERRUPTMSIINT_in[6] = (CFGINTERRUPTMSIINT[6] !== 1'bz) && CFGINTERRUPTMSIINT_delay[6]; // rv 0 + assign CFGINTERRUPTMSIINT_in[7] = (CFGINTERRUPTMSIINT[7] !== 1'bz) && CFGINTERRUPTMSIINT_delay[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[8] = (CFGINTERRUPTMSIINT[8] !== 1'bz) && CFGINTERRUPTMSIINT_delay[8]; // rv 0 + assign CFGINTERRUPTMSIINT_in[9] = (CFGINTERRUPTMSIINT[9] !== 1'bz) && CFGINTERRUPTMSIINT_delay[9]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[0] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[1] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[0] = (CFGINTERRUPTMSIPENDINGSTATUS[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[10] = (CFGINTERRUPTMSIPENDINGSTATUS[10] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[11] = (CFGINTERRUPTMSIPENDINGSTATUS[11] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[12] = (CFGINTERRUPTMSIPENDINGSTATUS[12] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[13] = (CFGINTERRUPTMSIPENDINGSTATUS[13] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[14] = (CFGINTERRUPTMSIPENDINGSTATUS[14] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[15] = (CFGINTERRUPTMSIPENDINGSTATUS[15] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[16] = (CFGINTERRUPTMSIPENDINGSTATUS[16] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[17] = (CFGINTERRUPTMSIPENDINGSTATUS[17] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[18] = (CFGINTERRUPTMSIPENDINGSTATUS[18] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[19] = (CFGINTERRUPTMSIPENDINGSTATUS[19] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[1] = (CFGINTERRUPTMSIPENDINGSTATUS[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[20] = (CFGINTERRUPTMSIPENDINGSTATUS[20] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[21] = (CFGINTERRUPTMSIPENDINGSTATUS[21] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[22] = (CFGINTERRUPTMSIPENDINGSTATUS[22] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[23] = (CFGINTERRUPTMSIPENDINGSTATUS[23] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[24] = (CFGINTERRUPTMSIPENDINGSTATUS[24] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[25] = (CFGINTERRUPTMSIPENDINGSTATUS[25] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[26] = (CFGINTERRUPTMSIPENDINGSTATUS[26] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[27] = (CFGINTERRUPTMSIPENDINGSTATUS[27] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[28] = (CFGINTERRUPTMSIPENDINGSTATUS[28] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[29] = (CFGINTERRUPTMSIPENDINGSTATUS[29] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[2] = (CFGINTERRUPTMSIPENDINGSTATUS[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[30] = (CFGINTERRUPTMSIPENDINGSTATUS[30] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[31] = (CFGINTERRUPTMSIPENDINGSTATUS[31] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[3] = (CFGINTERRUPTMSIPENDINGSTATUS[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[4] = (CFGINTERRUPTMSIPENDINGSTATUS[4] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[5] = (CFGINTERRUPTMSIPENDINGSTATUS[5] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[6] = (CFGINTERRUPTMSIPENDINGSTATUS[6] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[7] = (CFGINTERRUPTMSIPENDINGSTATUS[7] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[8] = (CFGINTERRUPTMSIPENDINGSTATUS[8] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[9] = (CFGINTERRUPTMSIPENDINGSTATUS[9] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[9]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[0] = (CFGINTERRUPTMSISELECT[0] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[0]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[1] = (CFGINTERRUPTMSISELECT[1] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[1]; // rv 0 + assign CFGINTERRUPTMSITPHPRESENT_in = (CFGINTERRUPTMSITPHPRESENT !== 1'bz) && CFGINTERRUPTMSITPHPRESENT_delay; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[0] = (CFGINTERRUPTMSITPHSTTAG[0] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[1] = (CFGINTERRUPTMSITPHSTTAG[1] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[1]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[2] = (CFGINTERRUPTMSITPHSTTAG[2] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[2]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[3] = (CFGINTERRUPTMSITPHSTTAG[3] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[3]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[4] = (CFGINTERRUPTMSITPHSTTAG[4] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[4]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[5] = (CFGINTERRUPTMSITPHSTTAG[5] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[5]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[6] = (CFGINTERRUPTMSITPHSTTAG[6] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[6]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[7] = (CFGINTERRUPTMSITPHSTTAG[7] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[7]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[0] = (CFGINTERRUPTMSITPHTYPE[0] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[1] = (CFGINTERRUPTMSITPHTYPE[1] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[0] = (CFGINTERRUPTMSIXADDRESS[0] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[10] = (CFGINTERRUPTMSIXADDRESS[10] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[11] = (CFGINTERRUPTMSIXADDRESS[11] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[12] = (CFGINTERRUPTMSIXADDRESS[12] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[13] = (CFGINTERRUPTMSIXADDRESS[13] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[14] = (CFGINTERRUPTMSIXADDRESS[14] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[15] = (CFGINTERRUPTMSIXADDRESS[15] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[16] = (CFGINTERRUPTMSIXADDRESS[16] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[17] = (CFGINTERRUPTMSIXADDRESS[17] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[18] = (CFGINTERRUPTMSIXADDRESS[18] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[19] = (CFGINTERRUPTMSIXADDRESS[19] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[1] = (CFGINTERRUPTMSIXADDRESS[1] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[20] = (CFGINTERRUPTMSIXADDRESS[20] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[21] = (CFGINTERRUPTMSIXADDRESS[21] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[22] = (CFGINTERRUPTMSIXADDRESS[22] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[23] = (CFGINTERRUPTMSIXADDRESS[23] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[24] = (CFGINTERRUPTMSIXADDRESS[24] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[25] = (CFGINTERRUPTMSIXADDRESS[25] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[26] = (CFGINTERRUPTMSIXADDRESS[26] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[27] = (CFGINTERRUPTMSIXADDRESS[27] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[28] = (CFGINTERRUPTMSIXADDRESS[28] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[29] = (CFGINTERRUPTMSIXADDRESS[29] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[2] = (CFGINTERRUPTMSIXADDRESS[2] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[30] = (CFGINTERRUPTMSIXADDRESS[30] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[31] = (CFGINTERRUPTMSIXADDRESS[31] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[32] = (CFGINTERRUPTMSIXADDRESS[32] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[32]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[33] = (CFGINTERRUPTMSIXADDRESS[33] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[33]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[34] = (CFGINTERRUPTMSIXADDRESS[34] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[34]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[35] = (CFGINTERRUPTMSIXADDRESS[35] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[35]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[36] = (CFGINTERRUPTMSIXADDRESS[36] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[36]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[37] = (CFGINTERRUPTMSIXADDRESS[37] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[37]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[38] = (CFGINTERRUPTMSIXADDRESS[38] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[38]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[39] = (CFGINTERRUPTMSIXADDRESS[39] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[39]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[3] = (CFGINTERRUPTMSIXADDRESS[3] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[40] = (CFGINTERRUPTMSIXADDRESS[40] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[40]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[41] = (CFGINTERRUPTMSIXADDRESS[41] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[41]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[42] = (CFGINTERRUPTMSIXADDRESS[42] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[42]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[43] = (CFGINTERRUPTMSIXADDRESS[43] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[43]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[44] = (CFGINTERRUPTMSIXADDRESS[44] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[44]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[45] = (CFGINTERRUPTMSIXADDRESS[45] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[45]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[46] = (CFGINTERRUPTMSIXADDRESS[46] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[46]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[47] = (CFGINTERRUPTMSIXADDRESS[47] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[47]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[48] = (CFGINTERRUPTMSIXADDRESS[48] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[48]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[49] = (CFGINTERRUPTMSIXADDRESS[49] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[49]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[4] = (CFGINTERRUPTMSIXADDRESS[4] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[50] = (CFGINTERRUPTMSIXADDRESS[50] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[50]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[51] = (CFGINTERRUPTMSIXADDRESS[51] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[51]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[52] = (CFGINTERRUPTMSIXADDRESS[52] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[52]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[53] = (CFGINTERRUPTMSIXADDRESS[53] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[53]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[54] = (CFGINTERRUPTMSIXADDRESS[54] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[54]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[55] = (CFGINTERRUPTMSIXADDRESS[55] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[55]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[56] = (CFGINTERRUPTMSIXADDRESS[56] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[56]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[57] = (CFGINTERRUPTMSIXADDRESS[57] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[57]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[58] = (CFGINTERRUPTMSIXADDRESS[58] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[58]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[59] = (CFGINTERRUPTMSIXADDRESS[59] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[59]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[5] = (CFGINTERRUPTMSIXADDRESS[5] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[60] = (CFGINTERRUPTMSIXADDRESS[60] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[60]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[61] = (CFGINTERRUPTMSIXADDRESS[61] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[61]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[62] = (CFGINTERRUPTMSIXADDRESS[62] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[62]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[63] = (CFGINTERRUPTMSIXADDRESS[63] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[63]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[6] = (CFGINTERRUPTMSIXADDRESS[6] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[7] = (CFGINTERRUPTMSIXADDRESS[7] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[8] = (CFGINTERRUPTMSIXADDRESS[8] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[9] = (CFGINTERRUPTMSIXADDRESS[9] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[0] = (CFGINTERRUPTMSIXDATA[0] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[10] = (CFGINTERRUPTMSIXDATA[10] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[11] = (CFGINTERRUPTMSIXDATA[11] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[12] = (CFGINTERRUPTMSIXDATA[12] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[13] = (CFGINTERRUPTMSIXDATA[13] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[14] = (CFGINTERRUPTMSIXDATA[14] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[15] = (CFGINTERRUPTMSIXDATA[15] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[16] = (CFGINTERRUPTMSIXDATA[16] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[17] = (CFGINTERRUPTMSIXDATA[17] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[18] = (CFGINTERRUPTMSIXDATA[18] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[19] = (CFGINTERRUPTMSIXDATA[19] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[1] = (CFGINTERRUPTMSIXDATA[1] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[20] = (CFGINTERRUPTMSIXDATA[20] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[21] = (CFGINTERRUPTMSIXDATA[21] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[22] = (CFGINTERRUPTMSIXDATA[22] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[23] = (CFGINTERRUPTMSIXDATA[23] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[24] = (CFGINTERRUPTMSIXDATA[24] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[25] = (CFGINTERRUPTMSIXDATA[25] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[26] = (CFGINTERRUPTMSIXDATA[26] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[27] = (CFGINTERRUPTMSIXDATA[27] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[28] = (CFGINTERRUPTMSIXDATA[28] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[29] = (CFGINTERRUPTMSIXDATA[29] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[2] = (CFGINTERRUPTMSIXDATA[2] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[30] = (CFGINTERRUPTMSIXDATA[30] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[31] = (CFGINTERRUPTMSIXDATA[31] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[3] = (CFGINTERRUPTMSIXDATA[3] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[4] = (CFGINTERRUPTMSIXDATA[4] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[5] = (CFGINTERRUPTMSIXDATA[5] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[6] = (CFGINTERRUPTMSIXDATA[6] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[7] = (CFGINTERRUPTMSIXDATA[7] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[8] = (CFGINTERRUPTMSIXDATA[8] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[9] = (CFGINTERRUPTMSIXDATA[9] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXINT_in = (CFGINTERRUPTMSIXINT !== 1'bz) && CFGINTERRUPTMSIXINT_delay; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[0] = (CFGINTERRUPTMSIXVECPENDING[0] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[1] = (CFGINTERRUPTMSIXVECPENDING[1] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING_delay[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[0] = (CFGINTERRUPTPENDING[0] !== 1'bz) && CFGINTERRUPTPENDING_delay[0]; // rv 0 + assign CFGINTERRUPTPENDING_in[1] = (CFGINTERRUPTPENDING[1] !== 1'bz) && CFGINTERRUPTPENDING_delay[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[2] = (CFGINTERRUPTPENDING[2] !== 1'bz) && CFGINTERRUPTPENDING_delay[2]; // rv 0 + assign CFGINTERRUPTPENDING_in[3] = (CFGINTERRUPTPENDING[3] !== 1'bz) && CFGINTERRUPTPENDING_delay[3]; // rv 0 + assign CFGLINKTRAININGENABLE_in = (CFGLINKTRAININGENABLE === 1'bz) || CFGLINKTRAININGENABLE_delay; // rv 1 + assign CFGMGMTADDR_in[0] = (CFGMGMTADDR[0] !== 1'bz) && CFGMGMTADDR_delay[0]; // rv 0 + assign CFGMGMTADDR_in[1] = (CFGMGMTADDR[1] !== 1'bz) && CFGMGMTADDR_delay[1]; // rv 0 + assign CFGMGMTADDR_in[2] = (CFGMGMTADDR[2] !== 1'bz) && CFGMGMTADDR_delay[2]; // rv 0 + assign CFGMGMTADDR_in[3] = (CFGMGMTADDR[3] !== 1'bz) && CFGMGMTADDR_delay[3]; // rv 0 + assign CFGMGMTADDR_in[4] = (CFGMGMTADDR[4] !== 1'bz) && CFGMGMTADDR_delay[4]; // rv 0 + assign CFGMGMTADDR_in[5] = (CFGMGMTADDR[5] !== 1'bz) && CFGMGMTADDR_delay[5]; // rv 0 + assign CFGMGMTADDR_in[6] = (CFGMGMTADDR[6] !== 1'bz) && CFGMGMTADDR_delay[6]; // rv 0 + assign CFGMGMTADDR_in[7] = (CFGMGMTADDR[7] !== 1'bz) && CFGMGMTADDR_delay[7]; // rv 0 + assign CFGMGMTADDR_in[8] = (CFGMGMTADDR[8] !== 1'bz) && CFGMGMTADDR_delay[8]; // rv 0 + assign CFGMGMTADDR_in[9] = (CFGMGMTADDR[9] !== 1'bz) && CFGMGMTADDR_delay[9]; // rv 0 + assign CFGMGMTBYTEENABLE_in[0] = (CFGMGMTBYTEENABLE[0] !== 1'bz) && CFGMGMTBYTEENABLE_delay[0]; // rv 0 + assign CFGMGMTBYTEENABLE_in[1] = (CFGMGMTBYTEENABLE[1] !== 1'bz) && CFGMGMTBYTEENABLE_delay[1]; // rv 0 + assign CFGMGMTBYTEENABLE_in[2] = (CFGMGMTBYTEENABLE[2] !== 1'bz) && CFGMGMTBYTEENABLE_delay[2]; // rv 0 + assign CFGMGMTBYTEENABLE_in[3] = (CFGMGMTBYTEENABLE[3] !== 1'bz) && CFGMGMTBYTEENABLE_delay[3]; // rv 0 + assign CFGMGMTDEBUGACCESS_in = (CFGMGMTDEBUGACCESS !== 1'bz) && CFGMGMTDEBUGACCESS_delay; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[0] = (CFGMGMTFUNCTIONNUMBER[0] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[1] = (CFGMGMTFUNCTIONNUMBER[1] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[2] = (CFGMGMTFUNCTIONNUMBER[2] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[3] = (CFGMGMTFUNCTIONNUMBER[3] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[4] = (CFGMGMTFUNCTIONNUMBER[4] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[4]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[5] = (CFGMGMTFUNCTIONNUMBER[5] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[5]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[6] = (CFGMGMTFUNCTIONNUMBER[6] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[6]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[7] = (CFGMGMTFUNCTIONNUMBER[7] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[7]; // rv 0 + assign CFGMGMTREAD_in = (CFGMGMTREAD !== 1'bz) && CFGMGMTREAD_delay; // rv 0 + assign CFGMGMTWRITEDATA_in[0] = (CFGMGMTWRITEDATA[0] !== 1'bz) && CFGMGMTWRITEDATA_delay[0]; // rv 0 + assign CFGMGMTWRITEDATA_in[10] = (CFGMGMTWRITEDATA[10] !== 1'bz) && CFGMGMTWRITEDATA_delay[10]; // rv 0 + assign CFGMGMTWRITEDATA_in[11] = (CFGMGMTWRITEDATA[11] !== 1'bz) && CFGMGMTWRITEDATA_delay[11]; // rv 0 + assign CFGMGMTWRITEDATA_in[12] = (CFGMGMTWRITEDATA[12] !== 1'bz) && CFGMGMTWRITEDATA_delay[12]; // rv 0 + assign CFGMGMTWRITEDATA_in[13] = (CFGMGMTWRITEDATA[13] !== 1'bz) && CFGMGMTWRITEDATA_delay[13]; // rv 0 + assign CFGMGMTWRITEDATA_in[14] = (CFGMGMTWRITEDATA[14] !== 1'bz) && CFGMGMTWRITEDATA_delay[14]; // rv 0 + assign CFGMGMTWRITEDATA_in[15] = (CFGMGMTWRITEDATA[15] !== 1'bz) && CFGMGMTWRITEDATA_delay[15]; // rv 0 + assign CFGMGMTWRITEDATA_in[16] = (CFGMGMTWRITEDATA[16] !== 1'bz) && CFGMGMTWRITEDATA_delay[16]; // rv 0 + assign CFGMGMTWRITEDATA_in[17] = (CFGMGMTWRITEDATA[17] !== 1'bz) && CFGMGMTWRITEDATA_delay[17]; // rv 0 + assign CFGMGMTWRITEDATA_in[18] = (CFGMGMTWRITEDATA[18] !== 1'bz) && CFGMGMTWRITEDATA_delay[18]; // rv 0 + assign CFGMGMTWRITEDATA_in[19] = (CFGMGMTWRITEDATA[19] !== 1'bz) && CFGMGMTWRITEDATA_delay[19]; // rv 0 + assign CFGMGMTWRITEDATA_in[1] = (CFGMGMTWRITEDATA[1] !== 1'bz) && CFGMGMTWRITEDATA_delay[1]; // rv 0 + assign CFGMGMTWRITEDATA_in[20] = (CFGMGMTWRITEDATA[20] !== 1'bz) && CFGMGMTWRITEDATA_delay[20]; // rv 0 + assign CFGMGMTWRITEDATA_in[21] = (CFGMGMTWRITEDATA[21] !== 1'bz) && CFGMGMTWRITEDATA_delay[21]; // rv 0 + assign CFGMGMTWRITEDATA_in[22] = (CFGMGMTWRITEDATA[22] !== 1'bz) && CFGMGMTWRITEDATA_delay[22]; // rv 0 + assign CFGMGMTWRITEDATA_in[23] = (CFGMGMTWRITEDATA[23] !== 1'bz) && CFGMGMTWRITEDATA_delay[23]; // rv 0 + assign CFGMGMTWRITEDATA_in[24] = (CFGMGMTWRITEDATA[24] !== 1'bz) && CFGMGMTWRITEDATA_delay[24]; // rv 0 + assign CFGMGMTWRITEDATA_in[25] = (CFGMGMTWRITEDATA[25] !== 1'bz) && CFGMGMTWRITEDATA_delay[25]; // rv 0 + assign CFGMGMTWRITEDATA_in[26] = (CFGMGMTWRITEDATA[26] !== 1'bz) && CFGMGMTWRITEDATA_delay[26]; // rv 0 + assign CFGMGMTWRITEDATA_in[27] = (CFGMGMTWRITEDATA[27] !== 1'bz) && CFGMGMTWRITEDATA_delay[27]; // rv 0 + assign CFGMGMTWRITEDATA_in[28] = (CFGMGMTWRITEDATA[28] !== 1'bz) && CFGMGMTWRITEDATA_delay[28]; // rv 0 + assign CFGMGMTWRITEDATA_in[29] = (CFGMGMTWRITEDATA[29] !== 1'bz) && CFGMGMTWRITEDATA_delay[29]; // rv 0 + assign CFGMGMTWRITEDATA_in[2] = (CFGMGMTWRITEDATA[2] !== 1'bz) && CFGMGMTWRITEDATA_delay[2]; // rv 0 + assign CFGMGMTWRITEDATA_in[30] = (CFGMGMTWRITEDATA[30] !== 1'bz) && CFGMGMTWRITEDATA_delay[30]; // rv 0 + assign CFGMGMTWRITEDATA_in[31] = (CFGMGMTWRITEDATA[31] !== 1'bz) && CFGMGMTWRITEDATA_delay[31]; // rv 0 + assign CFGMGMTWRITEDATA_in[3] = (CFGMGMTWRITEDATA[3] !== 1'bz) && CFGMGMTWRITEDATA_delay[3]; // rv 0 + assign CFGMGMTWRITEDATA_in[4] = (CFGMGMTWRITEDATA[4] !== 1'bz) && CFGMGMTWRITEDATA_delay[4]; // rv 0 + assign CFGMGMTWRITEDATA_in[5] = (CFGMGMTWRITEDATA[5] !== 1'bz) && CFGMGMTWRITEDATA_delay[5]; // rv 0 + assign CFGMGMTWRITEDATA_in[6] = (CFGMGMTWRITEDATA[6] !== 1'bz) && CFGMGMTWRITEDATA_delay[6]; // rv 0 + assign CFGMGMTWRITEDATA_in[7] = (CFGMGMTWRITEDATA[7] !== 1'bz) && CFGMGMTWRITEDATA_delay[7]; // rv 0 + assign CFGMGMTWRITEDATA_in[8] = (CFGMGMTWRITEDATA[8] !== 1'bz) && CFGMGMTWRITEDATA_delay[8]; // rv 0 + assign CFGMGMTWRITEDATA_in[9] = (CFGMGMTWRITEDATA[9] !== 1'bz) && CFGMGMTWRITEDATA_delay[9]; // rv 0 + assign CFGMGMTWRITE_in = (CFGMGMTWRITE !== 1'bz) && CFGMGMTWRITE_delay; // rv 0 + assign CFGMSGTRANSMITDATA_in[0] = (CFGMSGTRANSMITDATA[0] !== 1'bz) && CFGMSGTRANSMITDATA_delay[0]; // rv 0 + assign CFGMSGTRANSMITDATA_in[10] = (CFGMSGTRANSMITDATA[10] !== 1'bz) && CFGMSGTRANSMITDATA_delay[10]; // rv 0 + assign CFGMSGTRANSMITDATA_in[11] = (CFGMSGTRANSMITDATA[11] !== 1'bz) && CFGMSGTRANSMITDATA_delay[11]; // rv 0 + assign CFGMSGTRANSMITDATA_in[12] = (CFGMSGTRANSMITDATA[12] !== 1'bz) && CFGMSGTRANSMITDATA_delay[12]; // rv 0 + assign CFGMSGTRANSMITDATA_in[13] = (CFGMSGTRANSMITDATA[13] !== 1'bz) && CFGMSGTRANSMITDATA_delay[13]; // rv 0 + assign CFGMSGTRANSMITDATA_in[14] = (CFGMSGTRANSMITDATA[14] !== 1'bz) && CFGMSGTRANSMITDATA_delay[14]; // rv 0 + assign CFGMSGTRANSMITDATA_in[15] = (CFGMSGTRANSMITDATA[15] !== 1'bz) && CFGMSGTRANSMITDATA_delay[15]; // rv 0 + assign CFGMSGTRANSMITDATA_in[16] = (CFGMSGTRANSMITDATA[16] !== 1'bz) && CFGMSGTRANSMITDATA_delay[16]; // rv 0 + assign CFGMSGTRANSMITDATA_in[17] = (CFGMSGTRANSMITDATA[17] !== 1'bz) && CFGMSGTRANSMITDATA_delay[17]; // rv 0 + assign CFGMSGTRANSMITDATA_in[18] = (CFGMSGTRANSMITDATA[18] !== 1'bz) && CFGMSGTRANSMITDATA_delay[18]; // rv 0 + assign CFGMSGTRANSMITDATA_in[19] = (CFGMSGTRANSMITDATA[19] !== 1'bz) && CFGMSGTRANSMITDATA_delay[19]; // rv 0 + assign CFGMSGTRANSMITDATA_in[1] = (CFGMSGTRANSMITDATA[1] !== 1'bz) && CFGMSGTRANSMITDATA_delay[1]; // rv 0 + assign CFGMSGTRANSMITDATA_in[20] = (CFGMSGTRANSMITDATA[20] !== 1'bz) && CFGMSGTRANSMITDATA_delay[20]; // rv 0 + assign CFGMSGTRANSMITDATA_in[21] = (CFGMSGTRANSMITDATA[21] !== 1'bz) && CFGMSGTRANSMITDATA_delay[21]; // rv 0 + assign CFGMSGTRANSMITDATA_in[22] = (CFGMSGTRANSMITDATA[22] !== 1'bz) && CFGMSGTRANSMITDATA_delay[22]; // rv 0 + assign CFGMSGTRANSMITDATA_in[23] = (CFGMSGTRANSMITDATA[23] !== 1'bz) && CFGMSGTRANSMITDATA_delay[23]; // rv 0 + assign CFGMSGTRANSMITDATA_in[24] = (CFGMSGTRANSMITDATA[24] !== 1'bz) && CFGMSGTRANSMITDATA_delay[24]; // rv 0 + assign CFGMSGTRANSMITDATA_in[25] = (CFGMSGTRANSMITDATA[25] !== 1'bz) && CFGMSGTRANSMITDATA_delay[25]; // rv 0 + assign CFGMSGTRANSMITDATA_in[26] = (CFGMSGTRANSMITDATA[26] !== 1'bz) && CFGMSGTRANSMITDATA_delay[26]; // rv 0 + assign CFGMSGTRANSMITDATA_in[27] = (CFGMSGTRANSMITDATA[27] !== 1'bz) && CFGMSGTRANSMITDATA_delay[27]; // rv 0 + assign CFGMSGTRANSMITDATA_in[28] = (CFGMSGTRANSMITDATA[28] !== 1'bz) && CFGMSGTRANSMITDATA_delay[28]; // rv 0 + assign CFGMSGTRANSMITDATA_in[29] = (CFGMSGTRANSMITDATA[29] !== 1'bz) && CFGMSGTRANSMITDATA_delay[29]; // rv 0 + assign CFGMSGTRANSMITDATA_in[2] = (CFGMSGTRANSMITDATA[2] !== 1'bz) && CFGMSGTRANSMITDATA_delay[2]; // rv 0 + assign CFGMSGTRANSMITDATA_in[30] = (CFGMSGTRANSMITDATA[30] !== 1'bz) && CFGMSGTRANSMITDATA_delay[30]; // rv 0 + assign CFGMSGTRANSMITDATA_in[31] = (CFGMSGTRANSMITDATA[31] !== 1'bz) && CFGMSGTRANSMITDATA_delay[31]; // rv 0 + assign CFGMSGTRANSMITDATA_in[3] = (CFGMSGTRANSMITDATA[3] !== 1'bz) && CFGMSGTRANSMITDATA_delay[3]; // rv 0 + assign CFGMSGTRANSMITDATA_in[4] = (CFGMSGTRANSMITDATA[4] !== 1'bz) && CFGMSGTRANSMITDATA_delay[4]; // rv 0 + assign CFGMSGTRANSMITDATA_in[5] = (CFGMSGTRANSMITDATA[5] !== 1'bz) && CFGMSGTRANSMITDATA_delay[5]; // rv 0 + assign CFGMSGTRANSMITDATA_in[6] = (CFGMSGTRANSMITDATA[6] !== 1'bz) && CFGMSGTRANSMITDATA_delay[6]; // rv 0 + assign CFGMSGTRANSMITDATA_in[7] = (CFGMSGTRANSMITDATA[7] !== 1'bz) && CFGMSGTRANSMITDATA_delay[7]; // rv 0 + assign CFGMSGTRANSMITDATA_in[8] = (CFGMSGTRANSMITDATA[8] !== 1'bz) && CFGMSGTRANSMITDATA_delay[8]; // rv 0 + assign CFGMSGTRANSMITDATA_in[9] = (CFGMSGTRANSMITDATA[9] !== 1'bz) && CFGMSGTRANSMITDATA_delay[9]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[0] = (CFGMSGTRANSMITTYPE[0] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[0]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[1] = (CFGMSGTRANSMITTYPE[1] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[1]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[2] = (CFGMSGTRANSMITTYPE[2] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[2]; // rv 0 + assign CFGMSGTRANSMIT_in = (CFGMSGTRANSMIT !== 1'bz) && CFGMSGTRANSMIT_delay; // rv 0 + assign CFGMSIXRAMREADDATA_in[0] = (CFGMSIXRAMREADDATA[0] !== 1'bz) && CFGMSIXRAMREADDATA_delay[0]; // rv 0 + assign CFGMSIXRAMREADDATA_in[10] = (CFGMSIXRAMREADDATA[10] !== 1'bz) && CFGMSIXRAMREADDATA_delay[10]; // rv 0 + assign CFGMSIXRAMREADDATA_in[11] = (CFGMSIXRAMREADDATA[11] !== 1'bz) && CFGMSIXRAMREADDATA_delay[11]; // rv 0 + assign CFGMSIXRAMREADDATA_in[12] = (CFGMSIXRAMREADDATA[12] !== 1'bz) && CFGMSIXRAMREADDATA_delay[12]; // rv 0 + assign CFGMSIXRAMREADDATA_in[13] = (CFGMSIXRAMREADDATA[13] !== 1'bz) && CFGMSIXRAMREADDATA_delay[13]; // rv 0 + assign CFGMSIXRAMREADDATA_in[14] = (CFGMSIXRAMREADDATA[14] !== 1'bz) && CFGMSIXRAMREADDATA_delay[14]; // rv 0 + assign CFGMSIXRAMREADDATA_in[15] = (CFGMSIXRAMREADDATA[15] !== 1'bz) && CFGMSIXRAMREADDATA_delay[15]; // rv 0 + assign CFGMSIXRAMREADDATA_in[16] = (CFGMSIXRAMREADDATA[16] !== 1'bz) && CFGMSIXRAMREADDATA_delay[16]; // rv 0 + assign CFGMSIXRAMREADDATA_in[17] = (CFGMSIXRAMREADDATA[17] !== 1'bz) && CFGMSIXRAMREADDATA_delay[17]; // rv 0 + assign CFGMSIXRAMREADDATA_in[18] = (CFGMSIXRAMREADDATA[18] !== 1'bz) && CFGMSIXRAMREADDATA_delay[18]; // rv 0 + assign CFGMSIXRAMREADDATA_in[19] = (CFGMSIXRAMREADDATA[19] !== 1'bz) && CFGMSIXRAMREADDATA_delay[19]; // rv 0 + assign CFGMSIXRAMREADDATA_in[1] = (CFGMSIXRAMREADDATA[1] !== 1'bz) && CFGMSIXRAMREADDATA_delay[1]; // rv 0 + assign CFGMSIXRAMREADDATA_in[20] = (CFGMSIXRAMREADDATA[20] !== 1'bz) && CFGMSIXRAMREADDATA_delay[20]; // rv 0 + assign CFGMSIXRAMREADDATA_in[21] = (CFGMSIXRAMREADDATA[21] !== 1'bz) && CFGMSIXRAMREADDATA_delay[21]; // rv 0 + assign CFGMSIXRAMREADDATA_in[22] = (CFGMSIXRAMREADDATA[22] !== 1'bz) && CFGMSIXRAMREADDATA_delay[22]; // rv 0 + assign CFGMSIXRAMREADDATA_in[23] = (CFGMSIXRAMREADDATA[23] !== 1'bz) && CFGMSIXRAMREADDATA_delay[23]; // rv 0 + assign CFGMSIXRAMREADDATA_in[24] = (CFGMSIXRAMREADDATA[24] !== 1'bz) && CFGMSIXRAMREADDATA_delay[24]; // rv 0 + assign CFGMSIXRAMREADDATA_in[25] = (CFGMSIXRAMREADDATA[25] !== 1'bz) && CFGMSIXRAMREADDATA_delay[25]; // rv 0 + assign CFGMSIXRAMREADDATA_in[26] = (CFGMSIXRAMREADDATA[26] !== 1'bz) && CFGMSIXRAMREADDATA_delay[26]; // rv 0 + assign CFGMSIXRAMREADDATA_in[27] = (CFGMSIXRAMREADDATA[27] !== 1'bz) && CFGMSIXRAMREADDATA_delay[27]; // rv 0 + assign CFGMSIXRAMREADDATA_in[28] = (CFGMSIXRAMREADDATA[28] !== 1'bz) && CFGMSIXRAMREADDATA_delay[28]; // rv 0 + assign CFGMSIXRAMREADDATA_in[29] = (CFGMSIXRAMREADDATA[29] !== 1'bz) && CFGMSIXRAMREADDATA_delay[29]; // rv 0 + assign CFGMSIXRAMREADDATA_in[2] = (CFGMSIXRAMREADDATA[2] !== 1'bz) && CFGMSIXRAMREADDATA_delay[2]; // rv 0 + assign CFGMSIXRAMREADDATA_in[30] = (CFGMSIXRAMREADDATA[30] !== 1'bz) && CFGMSIXRAMREADDATA_delay[30]; // rv 0 + assign CFGMSIXRAMREADDATA_in[31] = (CFGMSIXRAMREADDATA[31] !== 1'bz) && CFGMSIXRAMREADDATA_delay[31]; // rv 0 + assign CFGMSIXRAMREADDATA_in[32] = (CFGMSIXRAMREADDATA[32] !== 1'bz) && CFGMSIXRAMREADDATA_delay[32]; // rv 0 + assign CFGMSIXRAMREADDATA_in[33] = (CFGMSIXRAMREADDATA[33] !== 1'bz) && CFGMSIXRAMREADDATA_delay[33]; // rv 0 + assign CFGMSIXRAMREADDATA_in[34] = (CFGMSIXRAMREADDATA[34] !== 1'bz) && CFGMSIXRAMREADDATA_delay[34]; // rv 0 + assign CFGMSIXRAMREADDATA_in[35] = (CFGMSIXRAMREADDATA[35] !== 1'bz) && CFGMSIXRAMREADDATA_delay[35]; // rv 0 + assign CFGMSIXRAMREADDATA_in[3] = (CFGMSIXRAMREADDATA[3] !== 1'bz) && CFGMSIXRAMREADDATA_delay[3]; // rv 0 + assign CFGMSIXRAMREADDATA_in[4] = (CFGMSIXRAMREADDATA[4] !== 1'bz) && CFGMSIXRAMREADDATA_delay[4]; // rv 0 + assign CFGMSIXRAMREADDATA_in[5] = (CFGMSIXRAMREADDATA[5] !== 1'bz) && CFGMSIXRAMREADDATA_delay[5]; // rv 0 + assign CFGMSIXRAMREADDATA_in[6] = (CFGMSIXRAMREADDATA[6] !== 1'bz) && CFGMSIXRAMREADDATA_delay[6]; // rv 0 + assign CFGMSIXRAMREADDATA_in[7] = (CFGMSIXRAMREADDATA[7] !== 1'bz) && CFGMSIXRAMREADDATA_delay[7]; // rv 0 + assign CFGMSIXRAMREADDATA_in[8] = (CFGMSIXRAMREADDATA[8] !== 1'bz) && CFGMSIXRAMREADDATA_delay[8]; // rv 0 + assign CFGMSIXRAMREADDATA_in[9] = (CFGMSIXRAMREADDATA[9] !== 1'bz) && CFGMSIXRAMREADDATA_delay[9]; // rv 0 + assign CFGPMASPML1ENTRYREJECT_in = (CFGPMASPML1ENTRYREJECT !== 1'bz) && CFGPMASPML1ENTRYREJECT_delay; // rv 0 + assign CFGPMASPMTXL0SENTRYDISABLE_in = (CFGPMASPMTXL0SENTRYDISABLE !== 1'bz) && CFGPMASPMTXL0SENTRYDISABLE_delay; // rv 0 + assign CFGPOWERSTATECHANGEACK_in = (CFGPOWERSTATECHANGEACK === 1'bz) || CFGPOWERSTATECHANGEACK_delay; // rv 1 + assign CFGREQPMTRANSITIONL23READY_in = (CFGREQPMTRANSITIONL23READY !== 1'bz) && CFGREQPMTRANSITIONL23READY_delay; // rv 0 + assign CFGREVIDPF0_in[0] = (CFGREVIDPF0[0] !== 1'bz) && CFGREVIDPF0_delay[0]; // rv 0 + assign CFGREVIDPF0_in[1] = (CFGREVIDPF0[1] !== 1'bz) && CFGREVIDPF0_delay[1]; // rv 0 + assign CFGREVIDPF0_in[2] = (CFGREVIDPF0[2] !== 1'bz) && CFGREVIDPF0_delay[2]; // rv 0 + assign CFGREVIDPF0_in[3] = (CFGREVIDPF0[3] !== 1'bz) && CFGREVIDPF0_delay[3]; // rv 0 + assign CFGREVIDPF0_in[4] = (CFGREVIDPF0[4] !== 1'bz) && CFGREVIDPF0_delay[4]; // rv 0 + assign CFGREVIDPF0_in[5] = (CFGREVIDPF0[5] !== 1'bz) && CFGREVIDPF0_delay[5]; // rv 0 + assign CFGREVIDPF0_in[6] = (CFGREVIDPF0[6] !== 1'bz) && CFGREVIDPF0_delay[6]; // rv 0 + assign CFGREVIDPF0_in[7] = (CFGREVIDPF0[7] !== 1'bz) && CFGREVIDPF0_delay[7]; // rv 0 + assign CFGREVIDPF1_in[0] = (CFGREVIDPF1[0] !== 1'bz) && CFGREVIDPF1_delay[0]; // rv 0 + assign CFGREVIDPF1_in[1] = (CFGREVIDPF1[1] !== 1'bz) && CFGREVIDPF1_delay[1]; // rv 0 + assign CFGREVIDPF1_in[2] = (CFGREVIDPF1[2] !== 1'bz) && CFGREVIDPF1_delay[2]; // rv 0 + assign CFGREVIDPF1_in[3] = (CFGREVIDPF1[3] !== 1'bz) && CFGREVIDPF1_delay[3]; // rv 0 + assign CFGREVIDPF1_in[4] = (CFGREVIDPF1[4] !== 1'bz) && CFGREVIDPF1_delay[4]; // rv 0 + assign CFGREVIDPF1_in[5] = (CFGREVIDPF1[5] !== 1'bz) && CFGREVIDPF1_delay[5]; // rv 0 + assign CFGREVIDPF1_in[6] = (CFGREVIDPF1[6] !== 1'bz) && CFGREVIDPF1_delay[6]; // rv 0 + assign CFGREVIDPF1_in[7] = (CFGREVIDPF1[7] !== 1'bz) && CFGREVIDPF1_delay[7]; // rv 0 + assign CFGREVIDPF2_in[0] = (CFGREVIDPF2[0] !== 1'bz) && CFGREVIDPF2_delay[0]; // rv 0 + assign CFGREVIDPF2_in[1] = (CFGREVIDPF2[1] !== 1'bz) && CFGREVIDPF2_delay[1]; // rv 0 + assign CFGREVIDPF2_in[2] = (CFGREVIDPF2[2] !== 1'bz) && CFGREVIDPF2_delay[2]; // rv 0 + assign CFGREVIDPF2_in[3] = (CFGREVIDPF2[3] !== 1'bz) && CFGREVIDPF2_delay[3]; // rv 0 + assign CFGREVIDPF2_in[4] = (CFGREVIDPF2[4] !== 1'bz) && CFGREVIDPF2_delay[4]; // rv 0 + assign CFGREVIDPF2_in[5] = (CFGREVIDPF2[5] !== 1'bz) && CFGREVIDPF2_delay[5]; // rv 0 + assign CFGREVIDPF2_in[6] = (CFGREVIDPF2[6] !== 1'bz) && CFGREVIDPF2_delay[6]; // rv 0 + assign CFGREVIDPF2_in[7] = (CFGREVIDPF2[7] !== 1'bz) && CFGREVIDPF2_delay[7]; // rv 0 + assign CFGREVIDPF3_in[0] = (CFGREVIDPF3[0] !== 1'bz) && CFGREVIDPF3_delay[0]; // rv 0 + assign CFGREVIDPF3_in[1] = (CFGREVIDPF3[1] !== 1'bz) && CFGREVIDPF3_delay[1]; // rv 0 + assign CFGREVIDPF3_in[2] = (CFGREVIDPF3[2] !== 1'bz) && CFGREVIDPF3_delay[2]; // rv 0 + assign CFGREVIDPF3_in[3] = (CFGREVIDPF3[3] !== 1'bz) && CFGREVIDPF3_delay[3]; // rv 0 + assign CFGREVIDPF3_in[4] = (CFGREVIDPF3[4] !== 1'bz) && CFGREVIDPF3_delay[4]; // rv 0 + assign CFGREVIDPF3_in[5] = (CFGREVIDPF3[5] !== 1'bz) && CFGREVIDPF3_delay[5]; // rv 0 + assign CFGREVIDPF3_in[6] = (CFGREVIDPF3[6] !== 1'bz) && CFGREVIDPF3_delay[6]; // rv 0 + assign CFGREVIDPF3_in[7] = (CFGREVIDPF3[7] !== 1'bz) && CFGREVIDPF3_delay[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[0] = (CFGSUBSYSIDPF0[0] !== 1'bz) && CFGSUBSYSIDPF0_delay[0]; // rv 0 + assign CFGSUBSYSIDPF0_in[10] = (CFGSUBSYSIDPF0[10] !== 1'bz) && CFGSUBSYSIDPF0_delay[10]; // rv 0 + assign CFGSUBSYSIDPF0_in[11] = (CFGSUBSYSIDPF0[11] !== 1'bz) && CFGSUBSYSIDPF0_delay[11]; // rv 0 + assign CFGSUBSYSIDPF0_in[12] = (CFGSUBSYSIDPF0[12] !== 1'bz) && CFGSUBSYSIDPF0_delay[12]; // rv 0 + assign CFGSUBSYSIDPF0_in[13] = (CFGSUBSYSIDPF0[13] !== 1'bz) && CFGSUBSYSIDPF0_delay[13]; // rv 0 + assign CFGSUBSYSIDPF0_in[14] = (CFGSUBSYSIDPF0[14] !== 1'bz) && CFGSUBSYSIDPF0_delay[14]; // rv 0 + assign CFGSUBSYSIDPF0_in[15] = (CFGSUBSYSIDPF0[15] !== 1'bz) && CFGSUBSYSIDPF0_delay[15]; // rv 0 + assign CFGSUBSYSIDPF0_in[1] = (CFGSUBSYSIDPF0[1] !== 1'bz) && CFGSUBSYSIDPF0_delay[1]; // rv 0 + assign CFGSUBSYSIDPF0_in[2] = (CFGSUBSYSIDPF0[2] !== 1'bz) && CFGSUBSYSIDPF0_delay[2]; // rv 0 + assign CFGSUBSYSIDPF0_in[3] = (CFGSUBSYSIDPF0[3] !== 1'bz) && CFGSUBSYSIDPF0_delay[3]; // rv 0 + assign CFGSUBSYSIDPF0_in[4] = (CFGSUBSYSIDPF0[4] !== 1'bz) && CFGSUBSYSIDPF0_delay[4]; // rv 0 + assign CFGSUBSYSIDPF0_in[5] = (CFGSUBSYSIDPF0[5] !== 1'bz) && CFGSUBSYSIDPF0_delay[5]; // rv 0 + assign CFGSUBSYSIDPF0_in[6] = (CFGSUBSYSIDPF0[6] !== 1'bz) && CFGSUBSYSIDPF0_delay[6]; // rv 0 + assign CFGSUBSYSIDPF0_in[7] = (CFGSUBSYSIDPF0[7] !== 1'bz) && CFGSUBSYSIDPF0_delay[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[8] = (CFGSUBSYSIDPF0[8] !== 1'bz) && CFGSUBSYSIDPF0_delay[8]; // rv 0 + assign CFGSUBSYSIDPF0_in[9] = (CFGSUBSYSIDPF0[9] !== 1'bz) && CFGSUBSYSIDPF0_delay[9]; // rv 0 + assign CFGSUBSYSIDPF1_in[0] = (CFGSUBSYSIDPF1[0] !== 1'bz) && CFGSUBSYSIDPF1_delay[0]; // rv 0 + assign CFGSUBSYSIDPF1_in[10] = (CFGSUBSYSIDPF1[10] !== 1'bz) && CFGSUBSYSIDPF1_delay[10]; // rv 0 + assign CFGSUBSYSIDPF1_in[11] = (CFGSUBSYSIDPF1[11] !== 1'bz) && CFGSUBSYSIDPF1_delay[11]; // rv 0 + assign CFGSUBSYSIDPF1_in[12] = (CFGSUBSYSIDPF1[12] !== 1'bz) && CFGSUBSYSIDPF1_delay[12]; // rv 0 + assign CFGSUBSYSIDPF1_in[13] = (CFGSUBSYSIDPF1[13] !== 1'bz) && CFGSUBSYSIDPF1_delay[13]; // rv 0 + assign CFGSUBSYSIDPF1_in[14] = (CFGSUBSYSIDPF1[14] !== 1'bz) && CFGSUBSYSIDPF1_delay[14]; // rv 0 + assign CFGSUBSYSIDPF1_in[15] = (CFGSUBSYSIDPF1[15] !== 1'bz) && CFGSUBSYSIDPF1_delay[15]; // rv 0 + assign CFGSUBSYSIDPF1_in[1] = (CFGSUBSYSIDPF1[1] !== 1'bz) && CFGSUBSYSIDPF1_delay[1]; // rv 0 + assign CFGSUBSYSIDPF1_in[2] = (CFGSUBSYSIDPF1[2] !== 1'bz) && CFGSUBSYSIDPF1_delay[2]; // rv 0 + assign CFGSUBSYSIDPF1_in[3] = (CFGSUBSYSIDPF1[3] !== 1'bz) && CFGSUBSYSIDPF1_delay[3]; // rv 0 + assign CFGSUBSYSIDPF1_in[4] = (CFGSUBSYSIDPF1[4] !== 1'bz) && CFGSUBSYSIDPF1_delay[4]; // rv 0 + assign CFGSUBSYSIDPF1_in[5] = (CFGSUBSYSIDPF1[5] !== 1'bz) && CFGSUBSYSIDPF1_delay[5]; // rv 0 + assign CFGSUBSYSIDPF1_in[6] = (CFGSUBSYSIDPF1[6] !== 1'bz) && CFGSUBSYSIDPF1_delay[6]; // rv 0 + assign CFGSUBSYSIDPF1_in[7] = (CFGSUBSYSIDPF1[7] !== 1'bz) && CFGSUBSYSIDPF1_delay[7]; // rv 0 + assign CFGSUBSYSIDPF1_in[8] = (CFGSUBSYSIDPF1[8] !== 1'bz) && CFGSUBSYSIDPF1_delay[8]; // rv 0 + assign CFGSUBSYSIDPF1_in[9] = (CFGSUBSYSIDPF1[9] !== 1'bz) && CFGSUBSYSIDPF1_delay[9]; // rv 0 + assign CFGSUBSYSIDPF2_in[0] = (CFGSUBSYSIDPF2[0] !== 1'bz) && CFGSUBSYSIDPF2_delay[0]; // rv 0 + assign CFGSUBSYSIDPF2_in[10] = (CFGSUBSYSIDPF2[10] !== 1'bz) && CFGSUBSYSIDPF2_delay[10]; // rv 0 + assign CFGSUBSYSIDPF2_in[11] = (CFGSUBSYSIDPF2[11] !== 1'bz) && CFGSUBSYSIDPF2_delay[11]; // rv 0 + assign CFGSUBSYSIDPF2_in[12] = (CFGSUBSYSIDPF2[12] !== 1'bz) && CFGSUBSYSIDPF2_delay[12]; // rv 0 + assign CFGSUBSYSIDPF2_in[13] = (CFGSUBSYSIDPF2[13] !== 1'bz) && CFGSUBSYSIDPF2_delay[13]; // rv 0 + assign CFGSUBSYSIDPF2_in[14] = (CFGSUBSYSIDPF2[14] !== 1'bz) && CFGSUBSYSIDPF2_delay[14]; // rv 0 + assign CFGSUBSYSIDPF2_in[15] = (CFGSUBSYSIDPF2[15] !== 1'bz) && CFGSUBSYSIDPF2_delay[15]; // rv 0 + assign CFGSUBSYSIDPF2_in[1] = (CFGSUBSYSIDPF2[1] !== 1'bz) && CFGSUBSYSIDPF2_delay[1]; // rv 0 + assign CFGSUBSYSIDPF2_in[2] = (CFGSUBSYSIDPF2[2] !== 1'bz) && CFGSUBSYSIDPF2_delay[2]; // rv 0 + assign CFGSUBSYSIDPF2_in[3] = (CFGSUBSYSIDPF2[3] !== 1'bz) && CFGSUBSYSIDPF2_delay[3]; // rv 0 + assign CFGSUBSYSIDPF2_in[4] = (CFGSUBSYSIDPF2[4] !== 1'bz) && CFGSUBSYSIDPF2_delay[4]; // rv 0 + assign CFGSUBSYSIDPF2_in[5] = (CFGSUBSYSIDPF2[5] !== 1'bz) && CFGSUBSYSIDPF2_delay[5]; // rv 0 + assign CFGSUBSYSIDPF2_in[6] = (CFGSUBSYSIDPF2[6] !== 1'bz) && CFGSUBSYSIDPF2_delay[6]; // rv 0 + assign CFGSUBSYSIDPF2_in[7] = (CFGSUBSYSIDPF2[7] !== 1'bz) && CFGSUBSYSIDPF2_delay[7]; // rv 0 + assign CFGSUBSYSIDPF2_in[8] = (CFGSUBSYSIDPF2[8] !== 1'bz) && CFGSUBSYSIDPF2_delay[8]; // rv 0 + assign CFGSUBSYSIDPF2_in[9] = (CFGSUBSYSIDPF2[9] !== 1'bz) && CFGSUBSYSIDPF2_delay[9]; // rv 0 + assign CFGSUBSYSIDPF3_in[0] = (CFGSUBSYSIDPF3[0] !== 1'bz) && CFGSUBSYSIDPF3_delay[0]; // rv 0 + assign CFGSUBSYSIDPF3_in[10] = (CFGSUBSYSIDPF3[10] !== 1'bz) && CFGSUBSYSIDPF3_delay[10]; // rv 0 + assign CFGSUBSYSIDPF3_in[11] = (CFGSUBSYSIDPF3[11] !== 1'bz) && CFGSUBSYSIDPF3_delay[11]; // rv 0 + assign CFGSUBSYSIDPF3_in[12] = (CFGSUBSYSIDPF3[12] !== 1'bz) && CFGSUBSYSIDPF3_delay[12]; // rv 0 + assign CFGSUBSYSIDPF3_in[13] = (CFGSUBSYSIDPF3[13] !== 1'bz) && CFGSUBSYSIDPF3_delay[13]; // rv 0 + assign CFGSUBSYSIDPF3_in[14] = (CFGSUBSYSIDPF3[14] !== 1'bz) && CFGSUBSYSIDPF3_delay[14]; // rv 0 + assign CFGSUBSYSIDPF3_in[15] = (CFGSUBSYSIDPF3[15] !== 1'bz) && CFGSUBSYSIDPF3_delay[15]; // rv 0 + assign CFGSUBSYSIDPF3_in[1] = (CFGSUBSYSIDPF3[1] !== 1'bz) && CFGSUBSYSIDPF3_delay[1]; // rv 0 + assign CFGSUBSYSIDPF3_in[2] = (CFGSUBSYSIDPF3[2] !== 1'bz) && CFGSUBSYSIDPF3_delay[2]; // rv 0 + assign CFGSUBSYSIDPF3_in[3] = (CFGSUBSYSIDPF3[3] !== 1'bz) && CFGSUBSYSIDPF3_delay[3]; // rv 0 + assign CFGSUBSYSIDPF3_in[4] = (CFGSUBSYSIDPF3[4] !== 1'bz) && CFGSUBSYSIDPF3_delay[4]; // rv 0 + assign CFGSUBSYSIDPF3_in[5] = (CFGSUBSYSIDPF3[5] !== 1'bz) && CFGSUBSYSIDPF3_delay[5]; // rv 0 + assign CFGSUBSYSIDPF3_in[6] = (CFGSUBSYSIDPF3[6] !== 1'bz) && CFGSUBSYSIDPF3_delay[6]; // rv 0 + assign CFGSUBSYSIDPF3_in[7] = (CFGSUBSYSIDPF3[7] !== 1'bz) && CFGSUBSYSIDPF3_delay[7]; // rv 0 + assign CFGSUBSYSIDPF3_in[8] = (CFGSUBSYSIDPF3[8] !== 1'bz) && CFGSUBSYSIDPF3_delay[8]; // rv 0 + assign CFGSUBSYSIDPF3_in[9] = (CFGSUBSYSIDPF3[9] !== 1'bz) && CFGSUBSYSIDPF3_delay[9]; // rv 0 + assign CFGSUBSYSVENDID_in[0] = (CFGSUBSYSVENDID[0] !== 1'bz) && CFGSUBSYSVENDID_delay[0]; // rv 0 + assign CFGSUBSYSVENDID_in[10] = (CFGSUBSYSVENDID[10] !== 1'bz) && CFGSUBSYSVENDID_delay[10]; // rv 0 + assign CFGSUBSYSVENDID_in[11] = (CFGSUBSYSVENDID[11] !== 1'bz) && CFGSUBSYSVENDID_delay[11]; // rv 0 + assign CFGSUBSYSVENDID_in[12] = (CFGSUBSYSVENDID[12] !== 1'bz) && CFGSUBSYSVENDID_delay[12]; // rv 0 + assign CFGSUBSYSVENDID_in[13] = (CFGSUBSYSVENDID[13] !== 1'bz) && CFGSUBSYSVENDID_delay[13]; // rv 0 + assign CFGSUBSYSVENDID_in[14] = (CFGSUBSYSVENDID[14] !== 1'bz) && CFGSUBSYSVENDID_delay[14]; // rv 0 + assign CFGSUBSYSVENDID_in[15] = (CFGSUBSYSVENDID[15] !== 1'bz) && CFGSUBSYSVENDID_delay[15]; // rv 0 + assign CFGSUBSYSVENDID_in[1] = (CFGSUBSYSVENDID[1] !== 1'bz) && CFGSUBSYSVENDID_delay[1]; // rv 0 + assign CFGSUBSYSVENDID_in[2] = (CFGSUBSYSVENDID[2] !== 1'bz) && CFGSUBSYSVENDID_delay[2]; // rv 0 + assign CFGSUBSYSVENDID_in[3] = (CFGSUBSYSVENDID[3] !== 1'bz) && CFGSUBSYSVENDID_delay[3]; // rv 0 + assign CFGSUBSYSVENDID_in[4] = (CFGSUBSYSVENDID[4] !== 1'bz) && CFGSUBSYSVENDID_delay[4]; // rv 0 + assign CFGSUBSYSVENDID_in[5] = (CFGSUBSYSVENDID[5] !== 1'bz) && CFGSUBSYSVENDID_delay[5]; // rv 0 + assign CFGSUBSYSVENDID_in[6] = (CFGSUBSYSVENDID[6] !== 1'bz) && CFGSUBSYSVENDID_delay[6]; // rv 0 + assign CFGSUBSYSVENDID_in[7] = (CFGSUBSYSVENDID[7] !== 1'bz) && CFGSUBSYSVENDID_delay[7]; // rv 0 + assign CFGSUBSYSVENDID_in[8] = (CFGSUBSYSVENDID[8] !== 1'bz) && CFGSUBSYSVENDID_delay[8]; // rv 0 + assign CFGSUBSYSVENDID_in[9] = (CFGSUBSYSVENDID[9] !== 1'bz) && CFGSUBSYSVENDID_delay[9]; // rv 0 + assign CFGTPHRAMREADDATA_in[0] = (CFGTPHRAMREADDATA[0] !== 1'bz) && CFGTPHRAMREADDATA_delay[0]; // rv 0 + assign CFGTPHRAMREADDATA_in[10] = (CFGTPHRAMREADDATA[10] !== 1'bz) && CFGTPHRAMREADDATA_delay[10]; // rv 0 + assign CFGTPHRAMREADDATA_in[11] = (CFGTPHRAMREADDATA[11] !== 1'bz) && CFGTPHRAMREADDATA_delay[11]; // rv 0 + assign CFGTPHRAMREADDATA_in[12] = (CFGTPHRAMREADDATA[12] !== 1'bz) && CFGTPHRAMREADDATA_delay[12]; // rv 0 + assign CFGTPHRAMREADDATA_in[13] = (CFGTPHRAMREADDATA[13] !== 1'bz) && CFGTPHRAMREADDATA_delay[13]; // rv 0 + assign CFGTPHRAMREADDATA_in[14] = (CFGTPHRAMREADDATA[14] !== 1'bz) && CFGTPHRAMREADDATA_delay[14]; // rv 0 + assign CFGTPHRAMREADDATA_in[15] = (CFGTPHRAMREADDATA[15] !== 1'bz) && CFGTPHRAMREADDATA_delay[15]; // rv 0 + assign CFGTPHRAMREADDATA_in[16] = (CFGTPHRAMREADDATA[16] !== 1'bz) && CFGTPHRAMREADDATA_delay[16]; // rv 0 + assign CFGTPHRAMREADDATA_in[17] = (CFGTPHRAMREADDATA[17] !== 1'bz) && CFGTPHRAMREADDATA_delay[17]; // rv 0 + assign CFGTPHRAMREADDATA_in[18] = (CFGTPHRAMREADDATA[18] !== 1'bz) && CFGTPHRAMREADDATA_delay[18]; // rv 0 + assign CFGTPHRAMREADDATA_in[19] = (CFGTPHRAMREADDATA[19] !== 1'bz) && CFGTPHRAMREADDATA_delay[19]; // rv 0 + assign CFGTPHRAMREADDATA_in[1] = (CFGTPHRAMREADDATA[1] !== 1'bz) && CFGTPHRAMREADDATA_delay[1]; // rv 0 + assign CFGTPHRAMREADDATA_in[20] = (CFGTPHRAMREADDATA[20] !== 1'bz) && CFGTPHRAMREADDATA_delay[20]; // rv 0 + assign CFGTPHRAMREADDATA_in[21] = (CFGTPHRAMREADDATA[21] !== 1'bz) && CFGTPHRAMREADDATA_delay[21]; // rv 0 + assign CFGTPHRAMREADDATA_in[22] = (CFGTPHRAMREADDATA[22] !== 1'bz) && CFGTPHRAMREADDATA_delay[22]; // rv 0 + assign CFGTPHRAMREADDATA_in[23] = (CFGTPHRAMREADDATA[23] !== 1'bz) && CFGTPHRAMREADDATA_delay[23]; // rv 0 + assign CFGTPHRAMREADDATA_in[24] = (CFGTPHRAMREADDATA[24] !== 1'bz) && CFGTPHRAMREADDATA_delay[24]; // rv 0 + assign CFGTPHRAMREADDATA_in[25] = (CFGTPHRAMREADDATA[25] !== 1'bz) && CFGTPHRAMREADDATA_delay[25]; // rv 0 + assign CFGTPHRAMREADDATA_in[26] = (CFGTPHRAMREADDATA[26] !== 1'bz) && CFGTPHRAMREADDATA_delay[26]; // rv 0 + assign CFGTPHRAMREADDATA_in[27] = (CFGTPHRAMREADDATA[27] !== 1'bz) && CFGTPHRAMREADDATA_delay[27]; // rv 0 + assign CFGTPHRAMREADDATA_in[28] = (CFGTPHRAMREADDATA[28] !== 1'bz) && CFGTPHRAMREADDATA_delay[28]; // rv 0 + assign CFGTPHRAMREADDATA_in[29] = (CFGTPHRAMREADDATA[29] !== 1'bz) && CFGTPHRAMREADDATA_delay[29]; // rv 0 + assign CFGTPHRAMREADDATA_in[2] = (CFGTPHRAMREADDATA[2] !== 1'bz) && CFGTPHRAMREADDATA_delay[2]; // rv 0 + assign CFGTPHRAMREADDATA_in[30] = (CFGTPHRAMREADDATA[30] !== 1'bz) && CFGTPHRAMREADDATA_delay[30]; // rv 0 + assign CFGTPHRAMREADDATA_in[31] = (CFGTPHRAMREADDATA[31] !== 1'bz) && CFGTPHRAMREADDATA_delay[31]; // rv 0 + assign CFGTPHRAMREADDATA_in[32] = (CFGTPHRAMREADDATA[32] !== 1'bz) && CFGTPHRAMREADDATA_delay[32]; // rv 0 + assign CFGTPHRAMREADDATA_in[33] = (CFGTPHRAMREADDATA[33] !== 1'bz) && CFGTPHRAMREADDATA_delay[33]; // rv 0 + assign CFGTPHRAMREADDATA_in[34] = (CFGTPHRAMREADDATA[34] !== 1'bz) && CFGTPHRAMREADDATA_delay[34]; // rv 0 + assign CFGTPHRAMREADDATA_in[35] = (CFGTPHRAMREADDATA[35] !== 1'bz) && CFGTPHRAMREADDATA_delay[35]; // rv 0 + assign CFGTPHRAMREADDATA_in[3] = (CFGTPHRAMREADDATA[3] !== 1'bz) && CFGTPHRAMREADDATA_delay[3]; // rv 0 + assign CFGTPHRAMREADDATA_in[4] = (CFGTPHRAMREADDATA[4] !== 1'bz) && CFGTPHRAMREADDATA_delay[4]; // rv 0 + assign CFGTPHRAMREADDATA_in[5] = (CFGTPHRAMREADDATA[5] !== 1'bz) && CFGTPHRAMREADDATA_delay[5]; // rv 0 + assign CFGTPHRAMREADDATA_in[6] = (CFGTPHRAMREADDATA[6] !== 1'bz) && CFGTPHRAMREADDATA_delay[6]; // rv 0 + assign CFGTPHRAMREADDATA_in[7] = (CFGTPHRAMREADDATA[7] !== 1'bz) && CFGTPHRAMREADDATA_delay[7]; // rv 0 + assign CFGTPHRAMREADDATA_in[8] = (CFGTPHRAMREADDATA[8] !== 1'bz) && CFGTPHRAMREADDATA_delay[8]; // rv 0 + assign CFGTPHRAMREADDATA_in[9] = (CFGTPHRAMREADDATA[9] !== 1'bz) && CFGTPHRAMREADDATA_delay[9]; // rv 0 + assign CFGVENDID_in[0] = (CFGVENDID[0] !== 1'bz) && CFGVENDID_delay[0]; // rv 0 + assign CFGVENDID_in[10] = (CFGVENDID[10] !== 1'bz) && CFGVENDID_delay[10]; // rv 0 + assign CFGVENDID_in[11] = (CFGVENDID[11] !== 1'bz) && CFGVENDID_delay[11]; // rv 0 + assign CFGVENDID_in[12] = (CFGVENDID[12] !== 1'bz) && CFGVENDID_delay[12]; // rv 0 + assign CFGVENDID_in[13] = (CFGVENDID[13] !== 1'bz) && CFGVENDID_delay[13]; // rv 0 + assign CFGVENDID_in[14] = (CFGVENDID[14] !== 1'bz) && CFGVENDID_delay[14]; // rv 0 + assign CFGVENDID_in[15] = (CFGVENDID[15] !== 1'bz) && CFGVENDID_delay[15]; // rv 0 + assign CFGVENDID_in[1] = (CFGVENDID[1] !== 1'bz) && CFGVENDID_delay[1]; // rv 0 + assign CFGVENDID_in[2] = (CFGVENDID[2] !== 1'bz) && CFGVENDID_delay[2]; // rv 0 + assign CFGVENDID_in[3] = (CFGVENDID[3] !== 1'bz) && CFGVENDID_delay[3]; // rv 0 + assign CFGVENDID_in[4] = (CFGVENDID[4] !== 1'bz) && CFGVENDID_delay[4]; // rv 0 + assign CFGVENDID_in[5] = (CFGVENDID[5] !== 1'bz) && CFGVENDID_delay[5]; // rv 0 + assign CFGVENDID_in[6] = (CFGVENDID[6] !== 1'bz) && CFGVENDID_delay[6]; // rv 0 + assign CFGVENDID_in[7] = (CFGVENDID[7] !== 1'bz) && CFGVENDID_delay[7]; // rv 0 + assign CFGVENDID_in[8] = (CFGVENDID[8] !== 1'bz) && CFGVENDID_delay[8]; // rv 0 + assign CFGVENDID_in[9] = (CFGVENDID[9] !== 1'bz) && CFGVENDID_delay[9]; // rv 0 + assign CFGVFFLRDONE_in = (CFGVFFLRDONE !== 1'bz) && CFGVFFLRDONE_delay; // rv 0 + assign CFGVFFLRFUNCNUM_in[0] = (CFGVFFLRFUNCNUM[0] !== 1'bz) && CFGVFFLRFUNCNUM_delay[0]; // rv 0 + assign CFGVFFLRFUNCNUM_in[1] = (CFGVFFLRFUNCNUM[1] !== 1'bz) && CFGVFFLRFUNCNUM_delay[1]; // rv 0 + assign CFGVFFLRFUNCNUM_in[2] = (CFGVFFLRFUNCNUM[2] !== 1'bz) && CFGVFFLRFUNCNUM_delay[2]; // rv 0 + assign CFGVFFLRFUNCNUM_in[3] = (CFGVFFLRFUNCNUM[3] !== 1'bz) && CFGVFFLRFUNCNUM_delay[3]; // rv 0 + assign CFGVFFLRFUNCNUM_in[4] = (CFGVFFLRFUNCNUM[4] !== 1'bz) && CFGVFFLRFUNCNUM_delay[4]; // rv 0 + assign CFGVFFLRFUNCNUM_in[5] = (CFGVFFLRFUNCNUM[5] !== 1'bz) && CFGVFFLRFUNCNUM_delay[5]; // rv 0 + assign CFGVFFLRFUNCNUM_in[6] = (CFGVFFLRFUNCNUM[6] !== 1'bz) && CFGVFFLRFUNCNUM_delay[6]; // rv 0 + assign CFGVFFLRFUNCNUM_in[7] = (CFGVFFLRFUNCNUM[7] !== 1'bz) && CFGVFFLRFUNCNUM_delay[7]; // rv 0 + assign CONFMCAPREQUESTBYCONF_in = (CONFMCAPREQUESTBYCONF !== 1'bz) && CONFMCAPREQUESTBYCONF_delay; // rv 0 + assign CONFREQDATA_in[0] = (CONFREQDATA[0] !== 1'bz) && CONFREQDATA_delay[0]; // rv 0 + assign CONFREQDATA_in[10] = (CONFREQDATA[10] !== 1'bz) && CONFREQDATA_delay[10]; // rv 0 + assign CONFREQDATA_in[11] = (CONFREQDATA[11] !== 1'bz) && CONFREQDATA_delay[11]; // rv 0 + assign CONFREQDATA_in[12] = (CONFREQDATA[12] !== 1'bz) && CONFREQDATA_delay[12]; // rv 0 + assign CONFREQDATA_in[13] = (CONFREQDATA[13] !== 1'bz) && CONFREQDATA_delay[13]; // rv 0 + assign CONFREQDATA_in[14] = (CONFREQDATA[14] !== 1'bz) && CONFREQDATA_delay[14]; // rv 0 + assign CONFREQDATA_in[15] = (CONFREQDATA[15] !== 1'bz) && CONFREQDATA_delay[15]; // rv 0 + assign CONFREQDATA_in[16] = (CONFREQDATA[16] !== 1'bz) && CONFREQDATA_delay[16]; // rv 0 + assign CONFREQDATA_in[17] = (CONFREQDATA[17] !== 1'bz) && CONFREQDATA_delay[17]; // rv 0 + assign CONFREQDATA_in[18] = (CONFREQDATA[18] !== 1'bz) && CONFREQDATA_delay[18]; // rv 0 + assign CONFREQDATA_in[19] = (CONFREQDATA[19] !== 1'bz) && CONFREQDATA_delay[19]; // rv 0 + assign CONFREQDATA_in[1] = (CONFREQDATA[1] !== 1'bz) && CONFREQDATA_delay[1]; // rv 0 + assign CONFREQDATA_in[20] = (CONFREQDATA[20] !== 1'bz) && CONFREQDATA_delay[20]; // rv 0 + assign CONFREQDATA_in[21] = (CONFREQDATA[21] !== 1'bz) && CONFREQDATA_delay[21]; // rv 0 + assign CONFREQDATA_in[22] = (CONFREQDATA[22] !== 1'bz) && CONFREQDATA_delay[22]; // rv 0 + assign CONFREQDATA_in[23] = (CONFREQDATA[23] !== 1'bz) && CONFREQDATA_delay[23]; // rv 0 + assign CONFREQDATA_in[24] = (CONFREQDATA[24] !== 1'bz) && CONFREQDATA_delay[24]; // rv 0 + assign CONFREQDATA_in[25] = (CONFREQDATA[25] !== 1'bz) && CONFREQDATA_delay[25]; // rv 0 + assign CONFREQDATA_in[26] = (CONFREQDATA[26] !== 1'bz) && CONFREQDATA_delay[26]; // rv 0 + assign CONFREQDATA_in[27] = (CONFREQDATA[27] !== 1'bz) && CONFREQDATA_delay[27]; // rv 0 + assign CONFREQDATA_in[28] = (CONFREQDATA[28] !== 1'bz) && CONFREQDATA_delay[28]; // rv 0 + assign CONFREQDATA_in[29] = (CONFREQDATA[29] !== 1'bz) && CONFREQDATA_delay[29]; // rv 0 + assign CONFREQDATA_in[2] = (CONFREQDATA[2] !== 1'bz) && CONFREQDATA_delay[2]; // rv 0 + assign CONFREQDATA_in[30] = (CONFREQDATA[30] !== 1'bz) && CONFREQDATA_delay[30]; // rv 0 + assign CONFREQDATA_in[31] = (CONFREQDATA[31] !== 1'bz) && CONFREQDATA_delay[31]; // rv 0 + assign CONFREQDATA_in[3] = (CONFREQDATA[3] !== 1'bz) && CONFREQDATA_delay[3]; // rv 0 + assign CONFREQDATA_in[4] = (CONFREQDATA[4] !== 1'bz) && CONFREQDATA_delay[4]; // rv 0 + assign CONFREQDATA_in[5] = (CONFREQDATA[5] !== 1'bz) && CONFREQDATA_delay[5]; // rv 0 + assign CONFREQDATA_in[6] = (CONFREQDATA[6] !== 1'bz) && CONFREQDATA_delay[6]; // rv 0 + assign CONFREQDATA_in[7] = (CONFREQDATA[7] !== 1'bz) && CONFREQDATA_delay[7]; // rv 0 + assign CONFREQDATA_in[8] = (CONFREQDATA[8] !== 1'bz) && CONFREQDATA_delay[8]; // rv 0 + assign CONFREQDATA_in[9] = (CONFREQDATA[9] !== 1'bz) && CONFREQDATA_delay[9]; // rv 0 + assign CONFREQREGNUM_in[0] = (CONFREQREGNUM[0] !== 1'bz) && CONFREQREGNUM_delay[0]; // rv 0 + assign CONFREQREGNUM_in[1] = (CONFREQREGNUM[1] !== 1'bz) && CONFREQREGNUM_delay[1]; // rv 0 + assign CONFREQREGNUM_in[2] = (CONFREQREGNUM[2] !== 1'bz) && CONFREQREGNUM_delay[2]; // rv 0 + assign CONFREQREGNUM_in[3] = (CONFREQREGNUM[3] !== 1'bz) && CONFREQREGNUM_delay[3]; // rv 0 + assign CONFREQTYPE_in[0] = (CONFREQTYPE[0] !== 1'bz) && CONFREQTYPE_delay[0]; // rv 0 + assign CONFREQTYPE_in[1] = (CONFREQTYPE[1] !== 1'bz) && CONFREQTYPE_delay[1]; // rv 0 + assign CONFREQVALID_in = (CONFREQVALID !== 1'bz) && CONFREQVALID_delay; // rv 0 + assign CORECLK_in = (CORECLK !== 1'bz) && CORECLK_delay; // rv 0 + assign DBGSEL0_in[0] = (DBGSEL0[0] !== 1'bz) && DBGSEL0_delay[0]; // rv 0 + assign DBGSEL0_in[1] = (DBGSEL0[1] !== 1'bz) && DBGSEL0_delay[1]; // rv 0 + assign DBGSEL0_in[2] = (DBGSEL0[2] !== 1'bz) && DBGSEL0_delay[2]; // rv 0 + assign DBGSEL0_in[3] = (DBGSEL0[3] !== 1'bz) && DBGSEL0_delay[3]; // rv 0 + assign DBGSEL0_in[4] = (DBGSEL0[4] !== 1'bz) && DBGSEL0_delay[4]; // rv 0 + assign DBGSEL0_in[5] = (DBGSEL0[5] !== 1'bz) && DBGSEL0_delay[5]; // rv 0 + assign DBGSEL1_in[0] = (DBGSEL1[0] !== 1'bz) && DBGSEL1_delay[0]; // rv 0 + assign DBGSEL1_in[1] = (DBGSEL1[1] !== 1'bz) && DBGSEL1_delay[1]; // rv 0 + assign DBGSEL1_in[2] = (DBGSEL1[2] !== 1'bz) && DBGSEL1_delay[2]; // rv 0 + assign DBGSEL1_in[3] = (DBGSEL1[3] !== 1'bz) && DBGSEL1_delay[3]; // rv 0 + assign DBGSEL1_in[4] = (DBGSEL1[4] !== 1'bz) && DBGSEL1_delay[4]; // rv 0 + assign DBGSEL1_in[5] = (DBGSEL1[5] !== 1'bz) && DBGSEL1_delay[5]; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign MAXISCQTREADY_in[0] = (MAXISCQTREADY[0] !== 1'bz) && MAXISCQTREADY_delay[0]; // rv 0 + assign MAXISCQTREADY_in[10] = (MAXISCQTREADY[10] !== 1'bz) && MAXISCQTREADY_delay[10]; // rv 0 + assign MAXISCQTREADY_in[11] = (MAXISCQTREADY[11] !== 1'bz) && MAXISCQTREADY_delay[11]; // rv 0 + assign MAXISCQTREADY_in[12] = (MAXISCQTREADY[12] !== 1'bz) && MAXISCQTREADY_delay[12]; // rv 0 + assign MAXISCQTREADY_in[13] = (MAXISCQTREADY[13] !== 1'bz) && MAXISCQTREADY_delay[13]; // rv 0 + assign MAXISCQTREADY_in[14] = (MAXISCQTREADY[14] !== 1'bz) && MAXISCQTREADY_delay[14]; // rv 0 + assign MAXISCQTREADY_in[15] = (MAXISCQTREADY[15] !== 1'bz) && MAXISCQTREADY_delay[15]; // rv 0 + assign MAXISCQTREADY_in[16] = (MAXISCQTREADY[16] !== 1'bz) && MAXISCQTREADY_delay[16]; // rv 0 + assign MAXISCQTREADY_in[17] = (MAXISCQTREADY[17] !== 1'bz) && MAXISCQTREADY_delay[17]; // rv 0 + assign MAXISCQTREADY_in[18] = (MAXISCQTREADY[18] !== 1'bz) && MAXISCQTREADY_delay[18]; // rv 0 + assign MAXISCQTREADY_in[19] = (MAXISCQTREADY[19] !== 1'bz) && MAXISCQTREADY_delay[19]; // rv 0 + assign MAXISCQTREADY_in[1] = (MAXISCQTREADY[1] !== 1'bz) && MAXISCQTREADY_delay[1]; // rv 0 + assign MAXISCQTREADY_in[20] = (MAXISCQTREADY[20] !== 1'bz) && MAXISCQTREADY_delay[20]; // rv 0 + assign MAXISCQTREADY_in[21] = (MAXISCQTREADY[21] !== 1'bz) && MAXISCQTREADY_delay[21]; // rv 0 + assign MAXISCQTREADY_in[2] = (MAXISCQTREADY[2] !== 1'bz) && MAXISCQTREADY_delay[2]; // rv 0 + assign MAXISCQTREADY_in[3] = (MAXISCQTREADY[3] !== 1'bz) && MAXISCQTREADY_delay[3]; // rv 0 + assign MAXISCQTREADY_in[4] = (MAXISCQTREADY[4] !== 1'bz) && MAXISCQTREADY_delay[4]; // rv 0 + assign MAXISCQTREADY_in[5] = (MAXISCQTREADY[5] !== 1'bz) && MAXISCQTREADY_delay[5]; // rv 0 + assign MAXISCQTREADY_in[6] = (MAXISCQTREADY[6] !== 1'bz) && MAXISCQTREADY_delay[6]; // rv 0 + assign MAXISCQTREADY_in[7] = (MAXISCQTREADY[7] !== 1'bz) && MAXISCQTREADY_delay[7]; // rv 0 + assign MAXISCQTREADY_in[8] = (MAXISCQTREADY[8] !== 1'bz) && MAXISCQTREADY_delay[8]; // rv 0 + assign MAXISCQTREADY_in[9] = (MAXISCQTREADY[9] !== 1'bz) && MAXISCQTREADY_delay[9]; // rv 0 + assign MAXISRCTREADY_in[0] = (MAXISRCTREADY[0] !== 1'bz) && MAXISRCTREADY_delay[0]; // rv 0 + assign MAXISRCTREADY_in[10] = (MAXISRCTREADY[10] !== 1'bz) && MAXISRCTREADY_delay[10]; // rv 0 + assign MAXISRCTREADY_in[11] = (MAXISRCTREADY[11] !== 1'bz) && MAXISRCTREADY_delay[11]; // rv 0 + assign MAXISRCTREADY_in[12] = (MAXISRCTREADY[12] !== 1'bz) && MAXISRCTREADY_delay[12]; // rv 0 + assign MAXISRCTREADY_in[13] = (MAXISRCTREADY[13] !== 1'bz) && MAXISRCTREADY_delay[13]; // rv 0 + assign MAXISRCTREADY_in[14] = (MAXISRCTREADY[14] !== 1'bz) && MAXISRCTREADY_delay[14]; // rv 0 + assign MAXISRCTREADY_in[15] = (MAXISRCTREADY[15] !== 1'bz) && MAXISRCTREADY_delay[15]; // rv 0 + assign MAXISRCTREADY_in[16] = (MAXISRCTREADY[16] !== 1'bz) && MAXISRCTREADY_delay[16]; // rv 0 + assign MAXISRCTREADY_in[17] = (MAXISRCTREADY[17] !== 1'bz) && MAXISRCTREADY_delay[17]; // rv 0 + assign MAXISRCTREADY_in[18] = (MAXISRCTREADY[18] !== 1'bz) && MAXISRCTREADY_delay[18]; // rv 0 + assign MAXISRCTREADY_in[19] = (MAXISRCTREADY[19] !== 1'bz) && MAXISRCTREADY_delay[19]; // rv 0 + assign MAXISRCTREADY_in[1] = (MAXISRCTREADY[1] !== 1'bz) && MAXISRCTREADY_delay[1]; // rv 0 + assign MAXISRCTREADY_in[20] = (MAXISRCTREADY[20] !== 1'bz) && MAXISRCTREADY_delay[20]; // rv 0 + assign MAXISRCTREADY_in[21] = (MAXISRCTREADY[21] !== 1'bz) && MAXISRCTREADY_delay[21]; // rv 0 + assign MAXISRCTREADY_in[2] = (MAXISRCTREADY[2] !== 1'bz) && MAXISRCTREADY_delay[2]; // rv 0 + assign MAXISRCTREADY_in[3] = (MAXISRCTREADY[3] !== 1'bz) && MAXISRCTREADY_delay[3]; // rv 0 + assign MAXISRCTREADY_in[4] = (MAXISRCTREADY[4] !== 1'bz) && MAXISRCTREADY_delay[4]; // rv 0 + assign MAXISRCTREADY_in[5] = (MAXISRCTREADY[5] !== 1'bz) && MAXISRCTREADY_delay[5]; // rv 0 + assign MAXISRCTREADY_in[6] = (MAXISRCTREADY[6] !== 1'bz) && MAXISRCTREADY_delay[6]; // rv 0 + assign MAXISRCTREADY_in[7] = (MAXISRCTREADY[7] !== 1'bz) && MAXISRCTREADY_delay[7]; // rv 0 + assign MAXISRCTREADY_in[8] = (MAXISRCTREADY[8] !== 1'bz) && MAXISRCTREADY_delay[8]; // rv 0 + assign MAXISRCTREADY_in[9] = (MAXISRCTREADY[9] !== 1'bz) && MAXISRCTREADY_delay[9]; // rv 0 + assign MIREPLAYRAMERRCOR_in[0] = (MIREPLAYRAMERRCOR[0] !== 1'bz) && MIREPLAYRAMERRCOR_delay[0]; // rv 0 + assign MIREPLAYRAMERRCOR_in[1] = (MIREPLAYRAMERRCOR[1] !== 1'bz) && MIREPLAYRAMERRCOR_delay[1]; // rv 0 + assign MIREPLAYRAMERRCOR_in[2] = (MIREPLAYRAMERRCOR[2] !== 1'bz) && MIREPLAYRAMERRCOR_delay[2]; // rv 0 + assign MIREPLAYRAMERRCOR_in[3] = (MIREPLAYRAMERRCOR[3] !== 1'bz) && MIREPLAYRAMERRCOR_delay[3]; // rv 0 + assign MIREPLAYRAMERRCOR_in[4] = (MIREPLAYRAMERRCOR[4] !== 1'bz) && MIREPLAYRAMERRCOR_delay[4]; // rv 0 + assign MIREPLAYRAMERRCOR_in[5] = (MIREPLAYRAMERRCOR[5] !== 1'bz) && MIREPLAYRAMERRCOR_delay[5]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[0] = (MIREPLAYRAMERRUNCOR[0] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[0]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[1] = (MIREPLAYRAMERRUNCOR[1] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[1]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[2] = (MIREPLAYRAMERRUNCOR[2] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[2]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[3] = (MIREPLAYRAMERRUNCOR[3] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[3]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[4] = (MIREPLAYRAMERRUNCOR[4] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[4]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[5] = (MIREPLAYRAMERRUNCOR[5] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[0] = (MIREPLAYRAMREADDATA0[0] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[0]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[100] = (MIREPLAYRAMREADDATA0[100] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[100]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[101] = (MIREPLAYRAMREADDATA0[101] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[101]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[102] = (MIREPLAYRAMREADDATA0[102] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[102]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[103] = (MIREPLAYRAMREADDATA0[103] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[103]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[104] = (MIREPLAYRAMREADDATA0[104] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[104]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[105] = (MIREPLAYRAMREADDATA0[105] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[105]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[106] = (MIREPLAYRAMREADDATA0[106] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[106]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[107] = (MIREPLAYRAMREADDATA0[107] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[107]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[108] = (MIREPLAYRAMREADDATA0[108] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[108]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[109] = (MIREPLAYRAMREADDATA0[109] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[109]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[10] = (MIREPLAYRAMREADDATA0[10] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[10]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[110] = (MIREPLAYRAMREADDATA0[110] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[110]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[111] = (MIREPLAYRAMREADDATA0[111] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[111]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[112] = (MIREPLAYRAMREADDATA0[112] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[112]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[113] = (MIREPLAYRAMREADDATA0[113] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[113]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[114] = (MIREPLAYRAMREADDATA0[114] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[114]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[115] = (MIREPLAYRAMREADDATA0[115] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[115]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[116] = (MIREPLAYRAMREADDATA0[116] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[116]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[117] = (MIREPLAYRAMREADDATA0[117] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[117]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[118] = (MIREPLAYRAMREADDATA0[118] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[118]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[119] = (MIREPLAYRAMREADDATA0[119] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[119]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[11] = (MIREPLAYRAMREADDATA0[11] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[11]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[120] = (MIREPLAYRAMREADDATA0[120] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[120]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[121] = (MIREPLAYRAMREADDATA0[121] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[121]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[122] = (MIREPLAYRAMREADDATA0[122] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[122]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[123] = (MIREPLAYRAMREADDATA0[123] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[123]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[124] = (MIREPLAYRAMREADDATA0[124] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[124]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[125] = (MIREPLAYRAMREADDATA0[125] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[125]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[126] = (MIREPLAYRAMREADDATA0[126] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[126]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[127] = (MIREPLAYRAMREADDATA0[127] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[127]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[12] = (MIREPLAYRAMREADDATA0[12] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[12]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[13] = (MIREPLAYRAMREADDATA0[13] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[13]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[14] = (MIREPLAYRAMREADDATA0[14] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[14]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[15] = (MIREPLAYRAMREADDATA0[15] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[15]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[16] = (MIREPLAYRAMREADDATA0[16] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[16]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[17] = (MIREPLAYRAMREADDATA0[17] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[17]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[18] = (MIREPLAYRAMREADDATA0[18] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[18]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[19] = (MIREPLAYRAMREADDATA0[19] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[19]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[1] = (MIREPLAYRAMREADDATA0[1] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[1]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[20] = (MIREPLAYRAMREADDATA0[20] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[20]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[21] = (MIREPLAYRAMREADDATA0[21] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[21]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[22] = (MIREPLAYRAMREADDATA0[22] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[22]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[23] = (MIREPLAYRAMREADDATA0[23] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[23]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[24] = (MIREPLAYRAMREADDATA0[24] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[24]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[25] = (MIREPLAYRAMREADDATA0[25] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[25]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[26] = (MIREPLAYRAMREADDATA0[26] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[26]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[27] = (MIREPLAYRAMREADDATA0[27] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[27]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[28] = (MIREPLAYRAMREADDATA0[28] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[28]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[29] = (MIREPLAYRAMREADDATA0[29] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[29]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[2] = (MIREPLAYRAMREADDATA0[2] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[2]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[30] = (MIREPLAYRAMREADDATA0[30] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[30]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[31] = (MIREPLAYRAMREADDATA0[31] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[31]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[32] = (MIREPLAYRAMREADDATA0[32] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[32]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[33] = (MIREPLAYRAMREADDATA0[33] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[33]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[34] = (MIREPLAYRAMREADDATA0[34] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[34]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[35] = (MIREPLAYRAMREADDATA0[35] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[35]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[36] = (MIREPLAYRAMREADDATA0[36] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[36]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[37] = (MIREPLAYRAMREADDATA0[37] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[37]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[38] = (MIREPLAYRAMREADDATA0[38] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[38]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[39] = (MIREPLAYRAMREADDATA0[39] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[39]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[3] = (MIREPLAYRAMREADDATA0[3] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[3]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[40] = (MIREPLAYRAMREADDATA0[40] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[40]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[41] = (MIREPLAYRAMREADDATA0[41] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[41]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[42] = (MIREPLAYRAMREADDATA0[42] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[42]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[43] = (MIREPLAYRAMREADDATA0[43] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[43]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[44] = (MIREPLAYRAMREADDATA0[44] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[44]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[45] = (MIREPLAYRAMREADDATA0[45] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[45]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[46] = (MIREPLAYRAMREADDATA0[46] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[46]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[47] = (MIREPLAYRAMREADDATA0[47] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[47]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[48] = (MIREPLAYRAMREADDATA0[48] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[48]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[49] = (MIREPLAYRAMREADDATA0[49] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[49]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[4] = (MIREPLAYRAMREADDATA0[4] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[4]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[50] = (MIREPLAYRAMREADDATA0[50] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[50]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[51] = (MIREPLAYRAMREADDATA0[51] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[51]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[52] = (MIREPLAYRAMREADDATA0[52] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[52]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[53] = (MIREPLAYRAMREADDATA0[53] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[53]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[54] = (MIREPLAYRAMREADDATA0[54] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[54]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[55] = (MIREPLAYRAMREADDATA0[55] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[55]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[56] = (MIREPLAYRAMREADDATA0[56] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[56]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[57] = (MIREPLAYRAMREADDATA0[57] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[57]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[58] = (MIREPLAYRAMREADDATA0[58] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[58]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[59] = (MIREPLAYRAMREADDATA0[59] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[59]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[5] = (MIREPLAYRAMREADDATA0[5] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[60] = (MIREPLAYRAMREADDATA0[60] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[60]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[61] = (MIREPLAYRAMREADDATA0[61] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[61]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[62] = (MIREPLAYRAMREADDATA0[62] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[62]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[63] = (MIREPLAYRAMREADDATA0[63] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[63]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[64] = (MIREPLAYRAMREADDATA0[64] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[64]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[65] = (MIREPLAYRAMREADDATA0[65] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[65]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[66] = (MIREPLAYRAMREADDATA0[66] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[66]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[67] = (MIREPLAYRAMREADDATA0[67] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[67]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[68] = (MIREPLAYRAMREADDATA0[68] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[68]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[69] = (MIREPLAYRAMREADDATA0[69] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[69]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[6] = (MIREPLAYRAMREADDATA0[6] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[6]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[70] = (MIREPLAYRAMREADDATA0[70] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[70]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[71] = (MIREPLAYRAMREADDATA0[71] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[71]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[72] = (MIREPLAYRAMREADDATA0[72] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[72]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[73] = (MIREPLAYRAMREADDATA0[73] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[73]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[74] = (MIREPLAYRAMREADDATA0[74] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[74]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[75] = (MIREPLAYRAMREADDATA0[75] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[75]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[76] = (MIREPLAYRAMREADDATA0[76] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[76]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[77] = (MIREPLAYRAMREADDATA0[77] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[77]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[78] = (MIREPLAYRAMREADDATA0[78] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[78]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[79] = (MIREPLAYRAMREADDATA0[79] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[79]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[7] = (MIREPLAYRAMREADDATA0[7] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[7]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[80] = (MIREPLAYRAMREADDATA0[80] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[80]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[81] = (MIREPLAYRAMREADDATA0[81] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[81]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[82] = (MIREPLAYRAMREADDATA0[82] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[82]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[83] = (MIREPLAYRAMREADDATA0[83] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[83]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[84] = (MIREPLAYRAMREADDATA0[84] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[84]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[85] = (MIREPLAYRAMREADDATA0[85] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[85]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[86] = (MIREPLAYRAMREADDATA0[86] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[86]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[87] = (MIREPLAYRAMREADDATA0[87] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[87]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[88] = (MIREPLAYRAMREADDATA0[88] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[88]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[89] = (MIREPLAYRAMREADDATA0[89] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[89]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[8] = (MIREPLAYRAMREADDATA0[8] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[8]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[90] = (MIREPLAYRAMREADDATA0[90] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[90]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[91] = (MIREPLAYRAMREADDATA0[91] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[91]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[92] = (MIREPLAYRAMREADDATA0[92] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[92]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[93] = (MIREPLAYRAMREADDATA0[93] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[93]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[94] = (MIREPLAYRAMREADDATA0[94] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[94]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[95] = (MIREPLAYRAMREADDATA0[95] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[95]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[96] = (MIREPLAYRAMREADDATA0[96] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[96]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[97] = (MIREPLAYRAMREADDATA0[97] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[97]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[98] = (MIREPLAYRAMREADDATA0[98] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[98]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[99] = (MIREPLAYRAMREADDATA0[99] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[99]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[9] = (MIREPLAYRAMREADDATA0[9] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[9]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[0] = (MIREPLAYRAMREADDATA1[0] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[0]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[100] = (MIREPLAYRAMREADDATA1[100] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[100]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[101] = (MIREPLAYRAMREADDATA1[101] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[101]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[102] = (MIREPLAYRAMREADDATA1[102] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[102]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[103] = (MIREPLAYRAMREADDATA1[103] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[103]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[104] = (MIREPLAYRAMREADDATA1[104] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[104]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[105] = (MIREPLAYRAMREADDATA1[105] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[105]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[106] = (MIREPLAYRAMREADDATA1[106] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[106]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[107] = (MIREPLAYRAMREADDATA1[107] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[107]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[108] = (MIREPLAYRAMREADDATA1[108] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[108]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[109] = (MIREPLAYRAMREADDATA1[109] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[109]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[10] = (MIREPLAYRAMREADDATA1[10] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[10]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[110] = (MIREPLAYRAMREADDATA1[110] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[110]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[111] = (MIREPLAYRAMREADDATA1[111] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[111]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[112] = (MIREPLAYRAMREADDATA1[112] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[112]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[113] = (MIREPLAYRAMREADDATA1[113] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[113]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[114] = (MIREPLAYRAMREADDATA1[114] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[114]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[115] = (MIREPLAYRAMREADDATA1[115] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[115]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[116] = (MIREPLAYRAMREADDATA1[116] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[116]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[117] = (MIREPLAYRAMREADDATA1[117] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[117]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[118] = (MIREPLAYRAMREADDATA1[118] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[118]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[119] = (MIREPLAYRAMREADDATA1[119] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[119]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[11] = (MIREPLAYRAMREADDATA1[11] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[11]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[120] = (MIREPLAYRAMREADDATA1[120] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[120]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[121] = (MIREPLAYRAMREADDATA1[121] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[121]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[122] = (MIREPLAYRAMREADDATA1[122] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[122]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[123] = (MIREPLAYRAMREADDATA1[123] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[123]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[124] = (MIREPLAYRAMREADDATA1[124] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[124]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[125] = (MIREPLAYRAMREADDATA1[125] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[125]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[126] = (MIREPLAYRAMREADDATA1[126] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[126]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[127] = (MIREPLAYRAMREADDATA1[127] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[127]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[12] = (MIREPLAYRAMREADDATA1[12] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[12]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[13] = (MIREPLAYRAMREADDATA1[13] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[13]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[14] = (MIREPLAYRAMREADDATA1[14] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[14]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[15] = (MIREPLAYRAMREADDATA1[15] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[15]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[16] = (MIREPLAYRAMREADDATA1[16] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[16]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[17] = (MIREPLAYRAMREADDATA1[17] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[17]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[18] = (MIREPLAYRAMREADDATA1[18] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[18]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[19] = (MIREPLAYRAMREADDATA1[19] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[19]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[1] = (MIREPLAYRAMREADDATA1[1] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[1]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[20] = (MIREPLAYRAMREADDATA1[20] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[20]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[21] = (MIREPLAYRAMREADDATA1[21] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[21]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[22] = (MIREPLAYRAMREADDATA1[22] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[22]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[23] = (MIREPLAYRAMREADDATA1[23] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[23]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[24] = (MIREPLAYRAMREADDATA1[24] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[24]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[25] = (MIREPLAYRAMREADDATA1[25] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[25]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[26] = (MIREPLAYRAMREADDATA1[26] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[26]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[27] = (MIREPLAYRAMREADDATA1[27] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[27]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[28] = (MIREPLAYRAMREADDATA1[28] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[28]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[29] = (MIREPLAYRAMREADDATA1[29] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[29]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[2] = (MIREPLAYRAMREADDATA1[2] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[2]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[30] = (MIREPLAYRAMREADDATA1[30] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[30]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[31] = (MIREPLAYRAMREADDATA1[31] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[31]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[32] = (MIREPLAYRAMREADDATA1[32] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[32]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[33] = (MIREPLAYRAMREADDATA1[33] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[33]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[34] = (MIREPLAYRAMREADDATA1[34] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[34]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[35] = (MIREPLAYRAMREADDATA1[35] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[35]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[36] = (MIREPLAYRAMREADDATA1[36] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[36]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[37] = (MIREPLAYRAMREADDATA1[37] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[37]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[38] = (MIREPLAYRAMREADDATA1[38] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[38]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[39] = (MIREPLAYRAMREADDATA1[39] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[39]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[3] = (MIREPLAYRAMREADDATA1[3] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[3]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[40] = (MIREPLAYRAMREADDATA1[40] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[40]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[41] = (MIREPLAYRAMREADDATA1[41] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[41]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[42] = (MIREPLAYRAMREADDATA1[42] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[42]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[43] = (MIREPLAYRAMREADDATA1[43] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[43]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[44] = (MIREPLAYRAMREADDATA1[44] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[44]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[45] = (MIREPLAYRAMREADDATA1[45] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[45]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[46] = (MIREPLAYRAMREADDATA1[46] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[46]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[47] = (MIREPLAYRAMREADDATA1[47] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[47]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[48] = (MIREPLAYRAMREADDATA1[48] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[48]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[49] = (MIREPLAYRAMREADDATA1[49] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[49]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[4] = (MIREPLAYRAMREADDATA1[4] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[4]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[50] = (MIREPLAYRAMREADDATA1[50] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[50]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[51] = (MIREPLAYRAMREADDATA1[51] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[51]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[52] = (MIREPLAYRAMREADDATA1[52] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[52]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[53] = (MIREPLAYRAMREADDATA1[53] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[53]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[54] = (MIREPLAYRAMREADDATA1[54] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[54]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[55] = (MIREPLAYRAMREADDATA1[55] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[55]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[56] = (MIREPLAYRAMREADDATA1[56] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[56]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[57] = (MIREPLAYRAMREADDATA1[57] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[57]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[58] = (MIREPLAYRAMREADDATA1[58] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[58]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[59] = (MIREPLAYRAMREADDATA1[59] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[59]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[5] = (MIREPLAYRAMREADDATA1[5] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[60] = (MIREPLAYRAMREADDATA1[60] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[60]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[61] = (MIREPLAYRAMREADDATA1[61] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[61]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[62] = (MIREPLAYRAMREADDATA1[62] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[62]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[63] = (MIREPLAYRAMREADDATA1[63] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[63]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[64] = (MIREPLAYRAMREADDATA1[64] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[64]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[65] = (MIREPLAYRAMREADDATA1[65] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[65]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[66] = (MIREPLAYRAMREADDATA1[66] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[66]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[67] = (MIREPLAYRAMREADDATA1[67] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[67]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[68] = (MIREPLAYRAMREADDATA1[68] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[68]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[69] = (MIREPLAYRAMREADDATA1[69] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[69]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[6] = (MIREPLAYRAMREADDATA1[6] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[6]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[70] = (MIREPLAYRAMREADDATA1[70] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[70]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[71] = (MIREPLAYRAMREADDATA1[71] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[71]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[72] = (MIREPLAYRAMREADDATA1[72] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[72]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[73] = (MIREPLAYRAMREADDATA1[73] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[73]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[74] = (MIREPLAYRAMREADDATA1[74] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[74]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[75] = (MIREPLAYRAMREADDATA1[75] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[75]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[76] = (MIREPLAYRAMREADDATA1[76] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[76]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[77] = (MIREPLAYRAMREADDATA1[77] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[77]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[78] = (MIREPLAYRAMREADDATA1[78] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[78]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[79] = (MIREPLAYRAMREADDATA1[79] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[79]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[7] = (MIREPLAYRAMREADDATA1[7] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[7]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[80] = (MIREPLAYRAMREADDATA1[80] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[80]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[81] = (MIREPLAYRAMREADDATA1[81] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[81]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[82] = (MIREPLAYRAMREADDATA1[82] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[82]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[83] = (MIREPLAYRAMREADDATA1[83] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[83]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[84] = (MIREPLAYRAMREADDATA1[84] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[84]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[85] = (MIREPLAYRAMREADDATA1[85] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[85]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[86] = (MIREPLAYRAMREADDATA1[86] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[86]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[87] = (MIREPLAYRAMREADDATA1[87] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[87]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[88] = (MIREPLAYRAMREADDATA1[88] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[88]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[89] = (MIREPLAYRAMREADDATA1[89] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[89]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[8] = (MIREPLAYRAMREADDATA1[8] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[8]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[90] = (MIREPLAYRAMREADDATA1[90] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[90]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[91] = (MIREPLAYRAMREADDATA1[91] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[91]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[92] = (MIREPLAYRAMREADDATA1[92] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[92]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[93] = (MIREPLAYRAMREADDATA1[93] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[93]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[94] = (MIREPLAYRAMREADDATA1[94] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[94]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[95] = (MIREPLAYRAMREADDATA1[95] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[95]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[96] = (MIREPLAYRAMREADDATA1[96] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[96]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[97] = (MIREPLAYRAMREADDATA1[97] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[97]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[98] = (MIREPLAYRAMREADDATA1[98] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[98]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[99] = (MIREPLAYRAMREADDATA1[99] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[99]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[9] = (MIREPLAYRAMREADDATA1[9] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[0] = (MIRXCOMPLETIONRAMERRCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[10] = (MIRXCOMPLETIONRAMERRCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[11] = (MIRXCOMPLETIONRAMERRCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[1] = (MIRXCOMPLETIONRAMERRCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[2] = (MIRXCOMPLETIONRAMERRCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[3] = (MIRXCOMPLETIONRAMERRCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[4] = (MIRXCOMPLETIONRAMERRCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[5] = (MIRXCOMPLETIONRAMERRCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[6] = (MIRXCOMPLETIONRAMERRCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[7] = (MIRXCOMPLETIONRAMERRCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[8] = (MIRXCOMPLETIONRAMERRCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[9] = (MIRXCOMPLETIONRAMERRCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[0] = (MIRXCOMPLETIONRAMERRUNCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[10] = (MIRXCOMPLETIONRAMERRUNCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[11] = (MIRXCOMPLETIONRAMERRUNCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[1] = (MIRXCOMPLETIONRAMERRUNCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[2] = (MIRXCOMPLETIONRAMERRUNCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[3] = (MIRXCOMPLETIONRAMERRUNCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[4] = (MIRXCOMPLETIONRAMERRUNCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[5] = (MIRXCOMPLETIONRAMERRUNCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[6] = (MIRXCOMPLETIONRAMERRUNCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[7] = (MIRXCOMPLETIONRAMERRUNCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[8] = (MIRXCOMPLETIONRAMERRUNCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[9] = (MIRXCOMPLETIONRAMERRUNCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[0] = (MIRXCOMPLETIONRAMREADDATA0[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[100] = (MIRXCOMPLETIONRAMREADDATA0[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[101] = (MIRXCOMPLETIONRAMREADDATA0[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[102] = (MIRXCOMPLETIONRAMREADDATA0[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[103] = (MIRXCOMPLETIONRAMREADDATA0[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[104] = (MIRXCOMPLETIONRAMREADDATA0[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[105] = (MIRXCOMPLETIONRAMREADDATA0[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[106] = (MIRXCOMPLETIONRAMREADDATA0[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[107] = (MIRXCOMPLETIONRAMREADDATA0[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[108] = (MIRXCOMPLETIONRAMREADDATA0[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[109] = (MIRXCOMPLETIONRAMREADDATA0[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[10] = (MIRXCOMPLETIONRAMREADDATA0[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[110] = (MIRXCOMPLETIONRAMREADDATA0[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[111] = (MIRXCOMPLETIONRAMREADDATA0[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[112] = (MIRXCOMPLETIONRAMREADDATA0[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[113] = (MIRXCOMPLETIONRAMREADDATA0[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[114] = (MIRXCOMPLETIONRAMREADDATA0[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[115] = (MIRXCOMPLETIONRAMREADDATA0[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[116] = (MIRXCOMPLETIONRAMREADDATA0[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[117] = (MIRXCOMPLETIONRAMREADDATA0[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[118] = (MIRXCOMPLETIONRAMREADDATA0[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[119] = (MIRXCOMPLETIONRAMREADDATA0[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[11] = (MIRXCOMPLETIONRAMREADDATA0[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[120] = (MIRXCOMPLETIONRAMREADDATA0[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[121] = (MIRXCOMPLETIONRAMREADDATA0[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[122] = (MIRXCOMPLETIONRAMREADDATA0[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[123] = (MIRXCOMPLETIONRAMREADDATA0[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[124] = (MIRXCOMPLETIONRAMREADDATA0[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[125] = (MIRXCOMPLETIONRAMREADDATA0[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[126] = (MIRXCOMPLETIONRAMREADDATA0[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[127] = (MIRXCOMPLETIONRAMREADDATA0[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[128] = (MIRXCOMPLETIONRAMREADDATA0[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[129] = (MIRXCOMPLETIONRAMREADDATA0[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[12] = (MIRXCOMPLETIONRAMREADDATA0[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[130] = (MIRXCOMPLETIONRAMREADDATA0[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[131] = (MIRXCOMPLETIONRAMREADDATA0[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[132] = (MIRXCOMPLETIONRAMREADDATA0[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[133] = (MIRXCOMPLETIONRAMREADDATA0[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[134] = (MIRXCOMPLETIONRAMREADDATA0[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[135] = (MIRXCOMPLETIONRAMREADDATA0[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[136] = (MIRXCOMPLETIONRAMREADDATA0[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[137] = (MIRXCOMPLETIONRAMREADDATA0[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[138] = (MIRXCOMPLETIONRAMREADDATA0[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[139] = (MIRXCOMPLETIONRAMREADDATA0[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[13] = (MIRXCOMPLETIONRAMREADDATA0[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[140] = (MIRXCOMPLETIONRAMREADDATA0[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[141] = (MIRXCOMPLETIONRAMREADDATA0[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[142] = (MIRXCOMPLETIONRAMREADDATA0[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[143] = (MIRXCOMPLETIONRAMREADDATA0[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[14] = (MIRXCOMPLETIONRAMREADDATA0[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[15] = (MIRXCOMPLETIONRAMREADDATA0[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[16] = (MIRXCOMPLETIONRAMREADDATA0[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[17] = (MIRXCOMPLETIONRAMREADDATA0[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[18] = (MIRXCOMPLETIONRAMREADDATA0[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[19] = (MIRXCOMPLETIONRAMREADDATA0[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[1] = (MIRXCOMPLETIONRAMREADDATA0[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[20] = (MIRXCOMPLETIONRAMREADDATA0[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[21] = (MIRXCOMPLETIONRAMREADDATA0[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[22] = (MIRXCOMPLETIONRAMREADDATA0[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[23] = (MIRXCOMPLETIONRAMREADDATA0[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[24] = (MIRXCOMPLETIONRAMREADDATA0[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[25] = (MIRXCOMPLETIONRAMREADDATA0[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[26] = (MIRXCOMPLETIONRAMREADDATA0[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[27] = (MIRXCOMPLETIONRAMREADDATA0[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[28] = (MIRXCOMPLETIONRAMREADDATA0[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[29] = (MIRXCOMPLETIONRAMREADDATA0[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[2] = (MIRXCOMPLETIONRAMREADDATA0[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[30] = (MIRXCOMPLETIONRAMREADDATA0[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[31] = (MIRXCOMPLETIONRAMREADDATA0[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[32] = (MIRXCOMPLETIONRAMREADDATA0[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[33] = (MIRXCOMPLETIONRAMREADDATA0[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[34] = (MIRXCOMPLETIONRAMREADDATA0[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[35] = (MIRXCOMPLETIONRAMREADDATA0[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[36] = (MIRXCOMPLETIONRAMREADDATA0[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[37] = (MIRXCOMPLETIONRAMREADDATA0[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[38] = (MIRXCOMPLETIONRAMREADDATA0[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[39] = (MIRXCOMPLETIONRAMREADDATA0[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[3] = (MIRXCOMPLETIONRAMREADDATA0[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[40] = (MIRXCOMPLETIONRAMREADDATA0[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[41] = (MIRXCOMPLETIONRAMREADDATA0[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[42] = (MIRXCOMPLETIONRAMREADDATA0[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[43] = (MIRXCOMPLETIONRAMREADDATA0[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[44] = (MIRXCOMPLETIONRAMREADDATA0[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[45] = (MIRXCOMPLETIONRAMREADDATA0[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[46] = (MIRXCOMPLETIONRAMREADDATA0[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[47] = (MIRXCOMPLETIONRAMREADDATA0[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[48] = (MIRXCOMPLETIONRAMREADDATA0[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[49] = (MIRXCOMPLETIONRAMREADDATA0[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[4] = (MIRXCOMPLETIONRAMREADDATA0[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[50] = (MIRXCOMPLETIONRAMREADDATA0[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[51] = (MIRXCOMPLETIONRAMREADDATA0[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[52] = (MIRXCOMPLETIONRAMREADDATA0[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[53] = (MIRXCOMPLETIONRAMREADDATA0[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[54] = (MIRXCOMPLETIONRAMREADDATA0[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[55] = (MIRXCOMPLETIONRAMREADDATA0[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[56] = (MIRXCOMPLETIONRAMREADDATA0[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[57] = (MIRXCOMPLETIONRAMREADDATA0[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[58] = (MIRXCOMPLETIONRAMREADDATA0[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[59] = (MIRXCOMPLETIONRAMREADDATA0[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[5] = (MIRXCOMPLETIONRAMREADDATA0[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[60] = (MIRXCOMPLETIONRAMREADDATA0[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[61] = (MIRXCOMPLETIONRAMREADDATA0[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[62] = (MIRXCOMPLETIONRAMREADDATA0[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[63] = (MIRXCOMPLETIONRAMREADDATA0[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[64] = (MIRXCOMPLETIONRAMREADDATA0[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[65] = (MIRXCOMPLETIONRAMREADDATA0[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[66] = (MIRXCOMPLETIONRAMREADDATA0[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[67] = (MIRXCOMPLETIONRAMREADDATA0[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[68] = (MIRXCOMPLETIONRAMREADDATA0[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[69] = (MIRXCOMPLETIONRAMREADDATA0[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[6] = (MIRXCOMPLETIONRAMREADDATA0[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[70] = (MIRXCOMPLETIONRAMREADDATA0[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[71] = (MIRXCOMPLETIONRAMREADDATA0[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[72] = (MIRXCOMPLETIONRAMREADDATA0[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[73] = (MIRXCOMPLETIONRAMREADDATA0[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[74] = (MIRXCOMPLETIONRAMREADDATA0[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[75] = (MIRXCOMPLETIONRAMREADDATA0[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[76] = (MIRXCOMPLETIONRAMREADDATA0[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[77] = (MIRXCOMPLETIONRAMREADDATA0[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[78] = (MIRXCOMPLETIONRAMREADDATA0[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[79] = (MIRXCOMPLETIONRAMREADDATA0[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[7] = (MIRXCOMPLETIONRAMREADDATA0[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[80] = (MIRXCOMPLETIONRAMREADDATA0[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[81] = (MIRXCOMPLETIONRAMREADDATA0[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[82] = (MIRXCOMPLETIONRAMREADDATA0[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[83] = (MIRXCOMPLETIONRAMREADDATA0[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[84] = (MIRXCOMPLETIONRAMREADDATA0[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[85] = (MIRXCOMPLETIONRAMREADDATA0[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[86] = (MIRXCOMPLETIONRAMREADDATA0[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[87] = (MIRXCOMPLETIONRAMREADDATA0[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[88] = (MIRXCOMPLETIONRAMREADDATA0[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[89] = (MIRXCOMPLETIONRAMREADDATA0[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[8] = (MIRXCOMPLETIONRAMREADDATA0[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[90] = (MIRXCOMPLETIONRAMREADDATA0[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[91] = (MIRXCOMPLETIONRAMREADDATA0[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[92] = (MIRXCOMPLETIONRAMREADDATA0[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[93] = (MIRXCOMPLETIONRAMREADDATA0[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[94] = (MIRXCOMPLETIONRAMREADDATA0[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[95] = (MIRXCOMPLETIONRAMREADDATA0[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[96] = (MIRXCOMPLETIONRAMREADDATA0[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[97] = (MIRXCOMPLETIONRAMREADDATA0[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[98] = (MIRXCOMPLETIONRAMREADDATA0[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[99] = (MIRXCOMPLETIONRAMREADDATA0[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[9] = (MIRXCOMPLETIONRAMREADDATA0[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[0] = (MIRXCOMPLETIONRAMREADDATA1[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[100] = (MIRXCOMPLETIONRAMREADDATA1[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[101] = (MIRXCOMPLETIONRAMREADDATA1[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[102] = (MIRXCOMPLETIONRAMREADDATA1[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[103] = (MIRXCOMPLETIONRAMREADDATA1[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[104] = (MIRXCOMPLETIONRAMREADDATA1[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[105] = (MIRXCOMPLETIONRAMREADDATA1[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[106] = (MIRXCOMPLETIONRAMREADDATA1[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[107] = (MIRXCOMPLETIONRAMREADDATA1[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[108] = (MIRXCOMPLETIONRAMREADDATA1[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[109] = (MIRXCOMPLETIONRAMREADDATA1[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[10] = (MIRXCOMPLETIONRAMREADDATA1[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[110] = (MIRXCOMPLETIONRAMREADDATA1[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[111] = (MIRXCOMPLETIONRAMREADDATA1[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[112] = (MIRXCOMPLETIONRAMREADDATA1[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[113] = (MIRXCOMPLETIONRAMREADDATA1[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[114] = (MIRXCOMPLETIONRAMREADDATA1[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[115] = (MIRXCOMPLETIONRAMREADDATA1[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[116] = (MIRXCOMPLETIONRAMREADDATA1[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[117] = (MIRXCOMPLETIONRAMREADDATA1[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[118] = (MIRXCOMPLETIONRAMREADDATA1[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[119] = (MIRXCOMPLETIONRAMREADDATA1[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[11] = (MIRXCOMPLETIONRAMREADDATA1[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[120] = (MIRXCOMPLETIONRAMREADDATA1[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[121] = (MIRXCOMPLETIONRAMREADDATA1[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[122] = (MIRXCOMPLETIONRAMREADDATA1[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[123] = (MIRXCOMPLETIONRAMREADDATA1[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[124] = (MIRXCOMPLETIONRAMREADDATA1[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[125] = (MIRXCOMPLETIONRAMREADDATA1[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[126] = (MIRXCOMPLETIONRAMREADDATA1[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[127] = (MIRXCOMPLETIONRAMREADDATA1[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[128] = (MIRXCOMPLETIONRAMREADDATA1[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[129] = (MIRXCOMPLETIONRAMREADDATA1[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[12] = (MIRXCOMPLETIONRAMREADDATA1[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[130] = (MIRXCOMPLETIONRAMREADDATA1[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[131] = (MIRXCOMPLETIONRAMREADDATA1[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[132] = (MIRXCOMPLETIONRAMREADDATA1[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[133] = (MIRXCOMPLETIONRAMREADDATA1[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[134] = (MIRXCOMPLETIONRAMREADDATA1[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[135] = (MIRXCOMPLETIONRAMREADDATA1[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[136] = (MIRXCOMPLETIONRAMREADDATA1[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[137] = (MIRXCOMPLETIONRAMREADDATA1[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[138] = (MIRXCOMPLETIONRAMREADDATA1[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[139] = (MIRXCOMPLETIONRAMREADDATA1[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[13] = (MIRXCOMPLETIONRAMREADDATA1[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[140] = (MIRXCOMPLETIONRAMREADDATA1[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[141] = (MIRXCOMPLETIONRAMREADDATA1[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[142] = (MIRXCOMPLETIONRAMREADDATA1[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[143] = (MIRXCOMPLETIONRAMREADDATA1[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[14] = (MIRXCOMPLETIONRAMREADDATA1[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[15] = (MIRXCOMPLETIONRAMREADDATA1[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[16] = (MIRXCOMPLETIONRAMREADDATA1[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[17] = (MIRXCOMPLETIONRAMREADDATA1[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[18] = (MIRXCOMPLETIONRAMREADDATA1[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[19] = (MIRXCOMPLETIONRAMREADDATA1[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[1] = (MIRXCOMPLETIONRAMREADDATA1[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[20] = (MIRXCOMPLETIONRAMREADDATA1[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[21] = (MIRXCOMPLETIONRAMREADDATA1[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[22] = (MIRXCOMPLETIONRAMREADDATA1[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[23] = (MIRXCOMPLETIONRAMREADDATA1[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[24] = (MIRXCOMPLETIONRAMREADDATA1[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[25] = (MIRXCOMPLETIONRAMREADDATA1[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[26] = (MIRXCOMPLETIONRAMREADDATA1[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[27] = (MIRXCOMPLETIONRAMREADDATA1[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[28] = (MIRXCOMPLETIONRAMREADDATA1[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[29] = (MIRXCOMPLETIONRAMREADDATA1[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[2] = (MIRXCOMPLETIONRAMREADDATA1[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[30] = (MIRXCOMPLETIONRAMREADDATA1[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[31] = (MIRXCOMPLETIONRAMREADDATA1[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[32] = (MIRXCOMPLETIONRAMREADDATA1[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[33] = (MIRXCOMPLETIONRAMREADDATA1[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[34] = (MIRXCOMPLETIONRAMREADDATA1[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[35] = (MIRXCOMPLETIONRAMREADDATA1[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[36] = (MIRXCOMPLETIONRAMREADDATA1[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[37] = (MIRXCOMPLETIONRAMREADDATA1[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[38] = (MIRXCOMPLETIONRAMREADDATA1[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[39] = (MIRXCOMPLETIONRAMREADDATA1[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[3] = (MIRXCOMPLETIONRAMREADDATA1[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[40] = (MIRXCOMPLETIONRAMREADDATA1[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[41] = (MIRXCOMPLETIONRAMREADDATA1[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[42] = (MIRXCOMPLETIONRAMREADDATA1[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[43] = (MIRXCOMPLETIONRAMREADDATA1[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[44] = (MIRXCOMPLETIONRAMREADDATA1[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[45] = (MIRXCOMPLETIONRAMREADDATA1[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[46] = (MIRXCOMPLETIONRAMREADDATA1[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[47] = (MIRXCOMPLETIONRAMREADDATA1[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[48] = (MIRXCOMPLETIONRAMREADDATA1[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[49] = (MIRXCOMPLETIONRAMREADDATA1[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[4] = (MIRXCOMPLETIONRAMREADDATA1[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[50] = (MIRXCOMPLETIONRAMREADDATA1[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[51] = (MIRXCOMPLETIONRAMREADDATA1[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[52] = (MIRXCOMPLETIONRAMREADDATA1[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[53] = (MIRXCOMPLETIONRAMREADDATA1[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[54] = (MIRXCOMPLETIONRAMREADDATA1[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[55] = (MIRXCOMPLETIONRAMREADDATA1[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[56] = (MIRXCOMPLETIONRAMREADDATA1[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[57] = (MIRXCOMPLETIONRAMREADDATA1[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[58] = (MIRXCOMPLETIONRAMREADDATA1[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[59] = (MIRXCOMPLETIONRAMREADDATA1[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[5] = (MIRXCOMPLETIONRAMREADDATA1[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[60] = (MIRXCOMPLETIONRAMREADDATA1[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[61] = (MIRXCOMPLETIONRAMREADDATA1[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[62] = (MIRXCOMPLETIONRAMREADDATA1[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[63] = (MIRXCOMPLETIONRAMREADDATA1[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[64] = (MIRXCOMPLETIONRAMREADDATA1[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[65] = (MIRXCOMPLETIONRAMREADDATA1[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[66] = (MIRXCOMPLETIONRAMREADDATA1[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[67] = (MIRXCOMPLETIONRAMREADDATA1[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[68] = (MIRXCOMPLETIONRAMREADDATA1[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[69] = (MIRXCOMPLETIONRAMREADDATA1[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[6] = (MIRXCOMPLETIONRAMREADDATA1[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[70] = (MIRXCOMPLETIONRAMREADDATA1[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[71] = (MIRXCOMPLETIONRAMREADDATA1[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[72] = (MIRXCOMPLETIONRAMREADDATA1[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[73] = (MIRXCOMPLETIONRAMREADDATA1[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[74] = (MIRXCOMPLETIONRAMREADDATA1[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[75] = (MIRXCOMPLETIONRAMREADDATA1[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[76] = (MIRXCOMPLETIONRAMREADDATA1[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[77] = (MIRXCOMPLETIONRAMREADDATA1[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[78] = (MIRXCOMPLETIONRAMREADDATA1[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[79] = (MIRXCOMPLETIONRAMREADDATA1[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[7] = (MIRXCOMPLETIONRAMREADDATA1[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[80] = (MIRXCOMPLETIONRAMREADDATA1[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[81] = (MIRXCOMPLETIONRAMREADDATA1[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[82] = (MIRXCOMPLETIONRAMREADDATA1[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[83] = (MIRXCOMPLETIONRAMREADDATA1[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[84] = (MIRXCOMPLETIONRAMREADDATA1[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[85] = (MIRXCOMPLETIONRAMREADDATA1[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[86] = (MIRXCOMPLETIONRAMREADDATA1[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[87] = (MIRXCOMPLETIONRAMREADDATA1[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[88] = (MIRXCOMPLETIONRAMREADDATA1[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[89] = (MIRXCOMPLETIONRAMREADDATA1[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[8] = (MIRXCOMPLETIONRAMREADDATA1[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[90] = (MIRXCOMPLETIONRAMREADDATA1[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[91] = (MIRXCOMPLETIONRAMREADDATA1[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[92] = (MIRXCOMPLETIONRAMREADDATA1[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[93] = (MIRXCOMPLETIONRAMREADDATA1[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[94] = (MIRXCOMPLETIONRAMREADDATA1[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[95] = (MIRXCOMPLETIONRAMREADDATA1[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[96] = (MIRXCOMPLETIONRAMREADDATA1[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[97] = (MIRXCOMPLETIONRAMREADDATA1[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[98] = (MIRXCOMPLETIONRAMREADDATA1[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[99] = (MIRXCOMPLETIONRAMREADDATA1[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[9] = (MIRXCOMPLETIONRAMREADDATA1[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRUNCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRUNCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRUNCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRUNCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRUNCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRUNCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA0[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA0[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA0[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA0[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA0[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA0[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA0[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA0[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA0[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA0[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA0[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA0[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA0[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA0[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA0[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA0[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA0[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA0[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA0[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA0[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA0[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA0[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA0[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA0[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA0[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA0[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA0[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA0[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA0[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA0[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA0[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA0[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA0[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA0[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA0[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA0[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA0[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA0[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA0[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA0[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA0[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA0[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA0[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA0[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA0[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA0[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA0[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA0[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA0[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA0[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA0[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA0[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA0[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA0[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA0[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA0[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA0[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA0[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA0[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA0[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA0[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA0[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA0[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA0[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA0[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA0[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA0[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA0[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA0[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA0[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA0[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA0[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA0[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA0[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA0[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA0[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA0[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA0[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA0[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA0[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA0[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA0[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA0[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA0[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA0[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA0[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA0[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA0[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA0[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA0[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA0[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA0[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA0[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA0[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA0[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA0[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA0[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA0[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA0[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA0[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA0[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA0[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA0[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA0[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA0[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA0[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA0[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA0[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA0[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA0[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA0[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA0[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA0[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA0[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA0[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA0[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA0[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA0[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA0[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA0[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA0[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA0[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA0[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA0[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA0[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA0[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA0[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA0[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA0[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA0[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA0[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA0[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA0[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA0[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA0[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA0[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA0[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA0[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA0[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA0[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA0[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA0[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA0[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA0[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA1[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA1[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA1[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA1[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA1[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA1[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA1[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA1[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA1[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA1[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA1[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA1[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA1[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA1[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA1[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA1[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA1[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA1[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA1[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA1[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA1[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA1[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA1[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA1[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA1[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA1[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA1[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA1[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA1[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA1[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA1[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA1[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA1[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA1[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA1[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA1[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA1[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA1[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA1[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA1[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA1[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA1[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA1[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA1[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA1[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA1[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA1[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA1[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA1[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA1[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA1[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA1[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA1[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA1[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA1[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA1[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA1[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA1[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA1[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA1[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA1[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA1[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA1[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA1[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA1[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA1[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA1[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA1[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA1[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA1[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA1[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA1[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA1[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA1[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA1[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA1[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA1[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA1[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA1[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA1[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA1[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA1[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA1[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA1[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA1[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA1[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA1[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA1[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA1[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA1[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA1[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA1[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA1[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA1[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA1[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA1[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA1[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA1[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA1[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA1[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA1[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA1[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA1[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA1[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA1[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA1[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA1[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA1[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA1[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA1[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA1[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA1[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA1[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA1[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA1[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA1[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA1[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA1[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA1[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA1[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA1[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA1[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA1[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA1[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA1[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA1[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA1[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA1[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA1[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA1[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA1[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA1[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA1[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA1[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA1[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA1[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA1[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA1[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA1[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA1[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA1[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA1[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA1[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA1[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[0] = (PCIECOMPLDELIVEREDTAG0[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[1] = (PCIECOMPLDELIVEREDTAG0[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[2] = (PCIECOMPLDELIVEREDTAG0[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[3] = (PCIECOMPLDELIVEREDTAG0[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[4] = (PCIECOMPLDELIVEREDTAG0[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[5] = (PCIECOMPLDELIVEREDTAG0[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[6] = (PCIECOMPLDELIVEREDTAG0[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[7] = (PCIECOMPLDELIVEREDTAG0[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[7]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[0] = (PCIECOMPLDELIVEREDTAG1[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[1] = (PCIECOMPLDELIVEREDTAG1[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[2] = (PCIECOMPLDELIVEREDTAG1[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[3] = (PCIECOMPLDELIVEREDTAG1[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[4] = (PCIECOMPLDELIVEREDTAG1[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[5] = (PCIECOMPLDELIVEREDTAG1[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[6] = (PCIECOMPLDELIVEREDTAG1[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[7] = (PCIECOMPLDELIVEREDTAG1[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[7]; // rv 0 + assign PCIECOMPLDELIVERED_in[0] = (PCIECOMPLDELIVERED[0] !== 1'bz) && PCIECOMPLDELIVERED_delay[0]; // rv 0 + assign PCIECOMPLDELIVERED_in[1] = (PCIECOMPLDELIVERED[1] !== 1'bz) && PCIECOMPLDELIVERED_delay[1]; // rv 0 + assign PCIECQNPREQ_in[0] = (PCIECQNPREQ[0] === 1'bz) || PCIECQNPREQ_delay[0]; // rv 1 + assign PCIECQNPREQ_in[1] = (PCIECQNPREQ[1] === 1'bz) || PCIECQNPREQ_delay[1]; // rv 1 + assign PCIECQNPUSERCREDITRCVD_in = (PCIECQNPUSERCREDITRCVD !== 1'bz) && PCIECQNPUSERCREDITRCVD_delay; // rv 0 + assign PCIECQPIPELINEEMPTY_in = (PCIECQPIPELINEEMPTY !== 1'bz) && PCIECQPIPELINEEMPTY_delay; // rv 0 + assign PCIEPOSTEDREQDELIVERED_in = (PCIEPOSTEDREQDELIVERED !== 1'bz) && PCIEPOSTEDREQDELIVERED_delay; // rv 0 + assign PIPECLK_in = (PIPECLK !== 1'bz) && PIPECLK_delay; // rv 0 + assign PIPEEQFS_in[0] = (PIPEEQFS[0] !== 1'bz) && PIPEEQFS_delay[0]; // rv 0 + assign PIPEEQFS_in[1] = (PIPEEQFS[1] !== 1'bz) && PIPEEQFS_delay[1]; // rv 0 + assign PIPEEQFS_in[2] = (PIPEEQFS[2] !== 1'bz) && PIPEEQFS_delay[2]; // rv 0 + assign PIPEEQFS_in[3] = (PIPEEQFS[3] !== 1'bz) && PIPEEQFS_delay[3]; // rv 0 + assign PIPEEQFS_in[4] = (PIPEEQFS[4] !== 1'bz) && PIPEEQFS_delay[4]; // rv 0 + assign PIPEEQFS_in[5] = (PIPEEQFS[5] !== 1'bz) && PIPEEQFS_delay[5]; // rv 0 + assign PIPEEQLF_in[0] = (PIPEEQLF[0] !== 1'bz) && PIPEEQLF_delay[0]; // rv 0 + assign PIPEEQLF_in[1] = (PIPEEQLF[1] !== 1'bz) && PIPEEQLF_delay[1]; // rv 0 + assign PIPEEQLF_in[2] = (PIPEEQLF[2] !== 1'bz) && PIPEEQLF_delay[2]; // rv 0 + assign PIPEEQLF_in[3] = (PIPEEQLF[3] !== 1'bz) && PIPEEQLF_delay[3]; // rv 0 + assign PIPEEQLF_in[4] = (PIPEEQLF[4] !== 1'bz) && PIPEEQLF_delay[4]; // rv 0 + assign PIPEEQLF_in[5] = (PIPEEQLF[5] !== 1'bz) && PIPEEQLF_delay[5]; // rv 0 + assign PIPERX00CHARISK_in[0] = (PIPERX00CHARISK[0] === 1'bz) || PIPERX00CHARISK_delay[0]; // rv 1 + assign PIPERX00CHARISK_in[1] = (PIPERX00CHARISK[1] === 1'bz) || PIPERX00CHARISK_delay[1]; // rv 1 + assign PIPERX00DATAVALID_in = (PIPERX00DATAVALID !== 1'bz) && PIPERX00DATAVALID_delay; // rv 0 + assign PIPERX00DATA_in[0] = (PIPERX00DATA[0] !== 1'bz) && PIPERX00DATA_delay[0]; // rv 0 + assign PIPERX00DATA_in[10] = (PIPERX00DATA[10] !== 1'bz) && PIPERX00DATA_delay[10]; // rv 0 + assign PIPERX00DATA_in[11] = (PIPERX00DATA[11] !== 1'bz) && PIPERX00DATA_delay[11]; // rv 0 + assign PIPERX00DATA_in[12] = (PIPERX00DATA[12] !== 1'bz) && PIPERX00DATA_delay[12]; // rv 0 + assign PIPERX00DATA_in[13] = (PIPERX00DATA[13] !== 1'bz) && PIPERX00DATA_delay[13]; // rv 0 + assign PIPERX00DATA_in[14] = (PIPERX00DATA[14] !== 1'bz) && PIPERX00DATA_delay[14]; // rv 0 + assign PIPERX00DATA_in[15] = (PIPERX00DATA[15] !== 1'bz) && PIPERX00DATA_delay[15]; // rv 0 + assign PIPERX00DATA_in[16] = (PIPERX00DATA[16] !== 1'bz) && PIPERX00DATA_delay[16]; // rv 0 + assign PIPERX00DATA_in[17] = (PIPERX00DATA[17] !== 1'bz) && PIPERX00DATA_delay[17]; // rv 0 + assign PIPERX00DATA_in[18] = (PIPERX00DATA[18] !== 1'bz) && PIPERX00DATA_delay[18]; // rv 0 + assign PIPERX00DATA_in[19] = (PIPERX00DATA[19] !== 1'bz) && PIPERX00DATA_delay[19]; // rv 0 + assign PIPERX00DATA_in[1] = (PIPERX00DATA[1] !== 1'bz) && PIPERX00DATA_delay[1]; // rv 0 + assign PIPERX00DATA_in[20] = (PIPERX00DATA[20] !== 1'bz) && PIPERX00DATA_delay[20]; // rv 0 + assign PIPERX00DATA_in[21] = (PIPERX00DATA[21] !== 1'bz) && PIPERX00DATA_delay[21]; // rv 0 + assign PIPERX00DATA_in[22] = (PIPERX00DATA[22] !== 1'bz) && PIPERX00DATA_delay[22]; // rv 0 + assign PIPERX00DATA_in[23] = (PIPERX00DATA[23] !== 1'bz) && PIPERX00DATA_delay[23]; // rv 0 + assign PIPERX00DATA_in[24] = (PIPERX00DATA[24] !== 1'bz) && PIPERX00DATA_delay[24]; // rv 0 + assign PIPERX00DATA_in[25] = (PIPERX00DATA[25] !== 1'bz) && PIPERX00DATA_delay[25]; // rv 0 + assign PIPERX00DATA_in[26] = (PIPERX00DATA[26] !== 1'bz) && PIPERX00DATA_delay[26]; // rv 0 + assign PIPERX00DATA_in[27] = (PIPERX00DATA[27] !== 1'bz) && PIPERX00DATA_delay[27]; // rv 0 + assign PIPERX00DATA_in[28] = (PIPERX00DATA[28] !== 1'bz) && PIPERX00DATA_delay[28]; // rv 0 + assign PIPERX00DATA_in[29] = (PIPERX00DATA[29] !== 1'bz) && PIPERX00DATA_delay[29]; // rv 0 + assign PIPERX00DATA_in[2] = (PIPERX00DATA[2] !== 1'bz) && PIPERX00DATA_delay[2]; // rv 0 + assign PIPERX00DATA_in[30] = (PIPERX00DATA[30] !== 1'bz) && PIPERX00DATA_delay[30]; // rv 0 + assign PIPERX00DATA_in[31] = (PIPERX00DATA[31] !== 1'bz) && PIPERX00DATA_delay[31]; // rv 0 + assign PIPERX00DATA_in[3] = (PIPERX00DATA[3] !== 1'bz) && PIPERX00DATA_delay[3]; // rv 0 + assign PIPERX00DATA_in[4] = (PIPERX00DATA[4] !== 1'bz) && PIPERX00DATA_delay[4]; // rv 0 + assign PIPERX00DATA_in[5] = (PIPERX00DATA[5] !== 1'bz) && PIPERX00DATA_delay[5]; // rv 0 + assign PIPERX00DATA_in[6] = (PIPERX00DATA[6] !== 1'bz) && PIPERX00DATA_delay[6]; // rv 0 + assign PIPERX00DATA_in[7] = (PIPERX00DATA[7] !== 1'bz) && PIPERX00DATA_delay[7]; // rv 0 + assign PIPERX00DATA_in[8] = (PIPERX00DATA[8] !== 1'bz) && PIPERX00DATA_delay[8]; // rv 0 + assign PIPERX00DATA_in[9] = (PIPERX00DATA[9] !== 1'bz) && PIPERX00DATA_delay[9]; // rv 0 + assign PIPERX00ELECIDLE_in = (PIPERX00ELECIDLE === 1'bz) || PIPERX00ELECIDLE_delay; // rv 1 + assign PIPERX00EQDONE_in = (PIPERX00EQDONE !== 1'bz) && PIPERX00EQDONE_delay; // rv 0 + assign PIPERX00EQLPADAPTDONE_in = (PIPERX00EQLPADAPTDONE !== 1'bz) && PIPERX00EQLPADAPTDONE_delay; // rv 0 + assign PIPERX00EQLPLFFSSEL_in = (PIPERX00EQLPLFFSSEL !== 1'bz) && PIPERX00EQLPLFFSSEL_delay; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX00EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX00EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX00EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX00EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX00EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX00EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX00EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX00EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX00EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX00EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX00EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX00EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX00EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX00EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX00EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX00EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX00EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX00EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX00PHYSTATUS_in = (PIPERX00PHYSTATUS === 1'bz) || PIPERX00PHYSTATUS_delay; // rv 1 + assign PIPERX00STARTBLOCK_in[0] = (PIPERX00STARTBLOCK[0] !== 1'bz) && PIPERX00STARTBLOCK_delay[0]; // rv 0 + assign PIPERX00STARTBLOCK_in[1] = (PIPERX00STARTBLOCK[1] !== 1'bz) && PIPERX00STARTBLOCK_delay[1]; // rv 0 + assign PIPERX00STATUS_in[0] = (PIPERX00STATUS[0] !== 1'bz) && PIPERX00STATUS_delay[0]; // rv 0 + assign PIPERX00STATUS_in[1] = (PIPERX00STATUS[1] !== 1'bz) && PIPERX00STATUS_delay[1]; // rv 0 + assign PIPERX00STATUS_in[2] = (PIPERX00STATUS[2] !== 1'bz) && PIPERX00STATUS_delay[2]; // rv 0 + assign PIPERX00SYNCHEADER_in[0] = (PIPERX00SYNCHEADER[0] !== 1'bz) && PIPERX00SYNCHEADER_delay[0]; // rv 0 + assign PIPERX00SYNCHEADER_in[1] = (PIPERX00SYNCHEADER[1] !== 1'bz) && PIPERX00SYNCHEADER_delay[1]; // rv 0 + assign PIPERX00VALID_in = (PIPERX00VALID !== 1'bz) && PIPERX00VALID_delay; // rv 0 + assign PIPERX01CHARISK_in[0] = (PIPERX01CHARISK[0] === 1'bz) || PIPERX01CHARISK_delay[0]; // rv 1 + assign PIPERX01CHARISK_in[1] = (PIPERX01CHARISK[1] === 1'bz) || PIPERX01CHARISK_delay[1]; // rv 1 + assign PIPERX01DATAVALID_in = (PIPERX01DATAVALID !== 1'bz) && PIPERX01DATAVALID_delay; // rv 0 + assign PIPERX01DATA_in[0] = (PIPERX01DATA[0] !== 1'bz) && PIPERX01DATA_delay[0]; // rv 0 + assign PIPERX01DATA_in[10] = (PIPERX01DATA[10] !== 1'bz) && PIPERX01DATA_delay[10]; // rv 0 + assign PIPERX01DATA_in[11] = (PIPERX01DATA[11] !== 1'bz) && PIPERX01DATA_delay[11]; // rv 0 + assign PIPERX01DATA_in[12] = (PIPERX01DATA[12] !== 1'bz) && PIPERX01DATA_delay[12]; // rv 0 + assign PIPERX01DATA_in[13] = (PIPERX01DATA[13] !== 1'bz) && PIPERX01DATA_delay[13]; // rv 0 + assign PIPERX01DATA_in[14] = (PIPERX01DATA[14] !== 1'bz) && PIPERX01DATA_delay[14]; // rv 0 + assign PIPERX01DATA_in[15] = (PIPERX01DATA[15] !== 1'bz) && PIPERX01DATA_delay[15]; // rv 0 + assign PIPERX01DATA_in[16] = (PIPERX01DATA[16] !== 1'bz) && PIPERX01DATA_delay[16]; // rv 0 + assign PIPERX01DATA_in[17] = (PIPERX01DATA[17] !== 1'bz) && PIPERX01DATA_delay[17]; // rv 0 + assign PIPERX01DATA_in[18] = (PIPERX01DATA[18] !== 1'bz) && PIPERX01DATA_delay[18]; // rv 0 + assign PIPERX01DATA_in[19] = (PIPERX01DATA[19] !== 1'bz) && PIPERX01DATA_delay[19]; // rv 0 + assign PIPERX01DATA_in[1] = (PIPERX01DATA[1] !== 1'bz) && PIPERX01DATA_delay[1]; // rv 0 + assign PIPERX01DATA_in[20] = (PIPERX01DATA[20] !== 1'bz) && PIPERX01DATA_delay[20]; // rv 0 + assign PIPERX01DATA_in[21] = (PIPERX01DATA[21] !== 1'bz) && PIPERX01DATA_delay[21]; // rv 0 + assign PIPERX01DATA_in[22] = (PIPERX01DATA[22] !== 1'bz) && PIPERX01DATA_delay[22]; // rv 0 + assign PIPERX01DATA_in[23] = (PIPERX01DATA[23] !== 1'bz) && PIPERX01DATA_delay[23]; // rv 0 + assign PIPERX01DATA_in[24] = (PIPERX01DATA[24] !== 1'bz) && PIPERX01DATA_delay[24]; // rv 0 + assign PIPERX01DATA_in[25] = (PIPERX01DATA[25] !== 1'bz) && PIPERX01DATA_delay[25]; // rv 0 + assign PIPERX01DATA_in[26] = (PIPERX01DATA[26] !== 1'bz) && PIPERX01DATA_delay[26]; // rv 0 + assign PIPERX01DATA_in[27] = (PIPERX01DATA[27] !== 1'bz) && PIPERX01DATA_delay[27]; // rv 0 + assign PIPERX01DATA_in[28] = (PIPERX01DATA[28] !== 1'bz) && PIPERX01DATA_delay[28]; // rv 0 + assign PIPERX01DATA_in[29] = (PIPERX01DATA[29] !== 1'bz) && PIPERX01DATA_delay[29]; // rv 0 + assign PIPERX01DATA_in[2] = (PIPERX01DATA[2] !== 1'bz) && PIPERX01DATA_delay[2]; // rv 0 + assign PIPERX01DATA_in[30] = (PIPERX01DATA[30] !== 1'bz) && PIPERX01DATA_delay[30]; // rv 0 + assign PIPERX01DATA_in[31] = (PIPERX01DATA[31] !== 1'bz) && PIPERX01DATA_delay[31]; // rv 0 + assign PIPERX01DATA_in[3] = (PIPERX01DATA[3] !== 1'bz) && PIPERX01DATA_delay[3]; // rv 0 + assign PIPERX01DATA_in[4] = (PIPERX01DATA[4] !== 1'bz) && PIPERX01DATA_delay[4]; // rv 0 + assign PIPERX01DATA_in[5] = (PIPERX01DATA[5] !== 1'bz) && PIPERX01DATA_delay[5]; // rv 0 + assign PIPERX01DATA_in[6] = (PIPERX01DATA[6] !== 1'bz) && PIPERX01DATA_delay[6]; // rv 0 + assign PIPERX01DATA_in[7] = (PIPERX01DATA[7] !== 1'bz) && PIPERX01DATA_delay[7]; // rv 0 + assign PIPERX01DATA_in[8] = (PIPERX01DATA[8] !== 1'bz) && PIPERX01DATA_delay[8]; // rv 0 + assign PIPERX01DATA_in[9] = (PIPERX01DATA[9] !== 1'bz) && PIPERX01DATA_delay[9]; // rv 0 + assign PIPERX01ELECIDLE_in = (PIPERX01ELECIDLE === 1'bz) || PIPERX01ELECIDLE_delay; // rv 1 + assign PIPERX01EQDONE_in = (PIPERX01EQDONE !== 1'bz) && PIPERX01EQDONE_delay; // rv 0 + assign PIPERX01EQLPADAPTDONE_in = (PIPERX01EQLPADAPTDONE !== 1'bz) && PIPERX01EQLPADAPTDONE_delay; // rv 0 + assign PIPERX01EQLPLFFSSEL_in = (PIPERX01EQLPLFFSSEL !== 1'bz) && PIPERX01EQLPLFFSSEL_delay; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX01EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX01EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX01EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX01EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX01EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX01EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX01EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX01EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX01EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX01EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX01EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX01EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX01EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX01EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX01EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX01EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX01EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX01EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX01PHYSTATUS_in = (PIPERX01PHYSTATUS === 1'bz) || PIPERX01PHYSTATUS_delay; // rv 1 + assign PIPERX01STARTBLOCK_in[0] = (PIPERX01STARTBLOCK[0] !== 1'bz) && PIPERX01STARTBLOCK_delay[0]; // rv 0 + assign PIPERX01STARTBLOCK_in[1] = (PIPERX01STARTBLOCK[1] !== 1'bz) && PIPERX01STARTBLOCK_delay[1]; // rv 0 + assign PIPERX01STATUS_in[0] = (PIPERX01STATUS[0] !== 1'bz) && PIPERX01STATUS_delay[0]; // rv 0 + assign PIPERX01STATUS_in[1] = (PIPERX01STATUS[1] !== 1'bz) && PIPERX01STATUS_delay[1]; // rv 0 + assign PIPERX01STATUS_in[2] = (PIPERX01STATUS[2] !== 1'bz) && PIPERX01STATUS_delay[2]; // rv 0 + assign PIPERX01SYNCHEADER_in[0] = (PIPERX01SYNCHEADER[0] !== 1'bz) && PIPERX01SYNCHEADER_delay[0]; // rv 0 + assign PIPERX01SYNCHEADER_in[1] = (PIPERX01SYNCHEADER[1] !== 1'bz) && PIPERX01SYNCHEADER_delay[1]; // rv 0 + assign PIPERX01VALID_in = (PIPERX01VALID !== 1'bz) && PIPERX01VALID_delay; // rv 0 + assign PIPERX02CHARISK_in[0] = (PIPERX02CHARISK[0] === 1'bz) || PIPERX02CHARISK_delay[0]; // rv 1 + assign PIPERX02CHARISK_in[1] = (PIPERX02CHARISK[1] === 1'bz) || PIPERX02CHARISK_delay[1]; // rv 1 + assign PIPERX02DATAVALID_in = (PIPERX02DATAVALID !== 1'bz) && PIPERX02DATAVALID_delay; // rv 0 + assign PIPERX02DATA_in[0] = (PIPERX02DATA[0] !== 1'bz) && PIPERX02DATA_delay[0]; // rv 0 + assign PIPERX02DATA_in[10] = (PIPERX02DATA[10] !== 1'bz) && PIPERX02DATA_delay[10]; // rv 0 + assign PIPERX02DATA_in[11] = (PIPERX02DATA[11] !== 1'bz) && PIPERX02DATA_delay[11]; // rv 0 + assign PIPERX02DATA_in[12] = (PIPERX02DATA[12] !== 1'bz) && PIPERX02DATA_delay[12]; // rv 0 + assign PIPERX02DATA_in[13] = (PIPERX02DATA[13] !== 1'bz) && PIPERX02DATA_delay[13]; // rv 0 + assign PIPERX02DATA_in[14] = (PIPERX02DATA[14] !== 1'bz) && PIPERX02DATA_delay[14]; // rv 0 + assign PIPERX02DATA_in[15] = (PIPERX02DATA[15] !== 1'bz) && PIPERX02DATA_delay[15]; // rv 0 + assign PIPERX02DATA_in[16] = (PIPERX02DATA[16] !== 1'bz) && PIPERX02DATA_delay[16]; // rv 0 + assign PIPERX02DATA_in[17] = (PIPERX02DATA[17] !== 1'bz) && PIPERX02DATA_delay[17]; // rv 0 + assign PIPERX02DATA_in[18] = (PIPERX02DATA[18] !== 1'bz) && PIPERX02DATA_delay[18]; // rv 0 + assign PIPERX02DATA_in[19] = (PIPERX02DATA[19] !== 1'bz) && PIPERX02DATA_delay[19]; // rv 0 + assign PIPERX02DATA_in[1] = (PIPERX02DATA[1] !== 1'bz) && PIPERX02DATA_delay[1]; // rv 0 + assign PIPERX02DATA_in[20] = (PIPERX02DATA[20] !== 1'bz) && PIPERX02DATA_delay[20]; // rv 0 + assign PIPERX02DATA_in[21] = (PIPERX02DATA[21] !== 1'bz) && PIPERX02DATA_delay[21]; // rv 0 + assign PIPERX02DATA_in[22] = (PIPERX02DATA[22] !== 1'bz) && PIPERX02DATA_delay[22]; // rv 0 + assign PIPERX02DATA_in[23] = (PIPERX02DATA[23] !== 1'bz) && PIPERX02DATA_delay[23]; // rv 0 + assign PIPERX02DATA_in[24] = (PIPERX02DATA[24] !== 1'bz) && PIPERX02DATA_delay[24]; // rv 0 + assign PIPERX02DATA_in[25] = (PIPERX02DATA[25] !== 1'bz) && PIPERX02DATA_delay[25]; // rv 0 + assign PIPERX02DATA_in[26] = (PIPERX02DATA[26] !== 1'bz) && PIPERX02DATA_delay[26]; // rv 0 + assign PIPERX02DATA_in[27] = (PIPERX02DATA[27] !== 1'bz) && PIPERX02DATA_delay[27]; // rv 0 + assign PIPERX02DATA_in[28] = (PIPERX02DATA[28] !== 1'bz) && PIPERX02DATA_delay[28]; // rv 0 + assign PIPERX02DATA_in[29] = (PIPERX02DATA[29] !== 1'bz) && PIPERX02DATA_delay[29]; // rv 0 + assign PIPERX02DATA_in[2] = (PIPERX02DATA[2] !== 1'bz) && PIPERX02DATA_delay[2]; // rv 0 + assign PIPERX02DATA_in[30] = (PIPERX02DATA[30] !== 1'bz) && PIPERX02DATA_delay[30]; // rv 0 + assign PIPERX02DATA_in[31] = (PIPERX02DATA[31] !== 1'bz) && PIPERX02DATA_delay[31]; // rv 0 + assign PIPERX02DATA_in[3] = (PIPERX02DATA[3] !== 1'bz) && PIPERX02DATA_delay[3]; // rv 0 + assign PIPERX02DATA_in[4] = (PIPERX02DATA[4] !== 1'bz) && PIPERX02DATA_delay[4]; // rv 0 + assign PIPERX02DATA_in[5] = (PIPERX02DATA[5] !== 1'bz) && PIPERX02DATA_delay[5]; // rv 0 + assign PIPERX02DATA_in[6] = (PIPERX02DATA[6] !== 1'bz) && PIPERX02DATA_delay[6]; // rv 0 + assign PIPERX02DATA_in[7] = (PIPERX02DATA[7] !== 1'bz) && PIPERX02DATA_delay[7]; // rv 0 + assign PIPERX02DATA_in[8] = (PIPERX02DATA[8] !== 1'bz) && PIPERX02DATA_delay[8]; // rv 0 + assign PIPERX02DATA_in[9] = (PIPERX02DATA[9] !== 1'bz) && PIPERX02DATA_delay[9]; // rv 0 + assign PIPERX02ELECIDLE_in = (PIPERX02ELECIDLE === 1'bz) || PIPERX02ELECIDLE_delay; // rv 1 + assign PIPERX02EQDONE_in = (PIPERX02EQDONE !== 1'bz) && PIPERX02EQDONE_delay; // rv 0 + assign PIPERX02EQLPADAPTDONE_in = (PIPERX02EQLPADAPTDONE !== 1'bz) && PIPERX02EQLPADAPTDONE_delay; // rv 0 + assign PIPERX02EQLPLFFSSEL_in = (PIPERX02EQLPLFFSSEL !== 1'bz) && PIPERX02EQLPLFFSSEL_delay; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX02EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX02EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX02EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX02EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX02EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX02EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX02EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX02EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX02EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX02EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX02EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX02EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX02EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX02EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX02EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX02EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX02EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX02EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX02PHYSTATUS_in = (PIPERX02PHYSTATUS === 1'bz) || PIPERX02PHYSTATUS_delay; // rv 1 + assign PIPERX02STARTBLOCK_in[0] = (PIPERX02STARTBLOCK[0] !== 1'bz) && PIPERX02STARTBLOCK_delay[0]; // rv 0 + assign PIPERX02STARTBLOCK_in[1] = (PIPERX02STARTBLOCK[1] !== 1'bz) && PIPERX02STARTBLOCK_delay[1]; // rv 0 + assign PIPERX02STATUS_in[0] = (PIPERX02STATUS[0] !== 1'bz) && PIPERX02STATUS_delay[0]; // rv 0 + assign PIPERX02STATUS_in[1] = (PIPERX02STATUS[1] !== 1'bz) && PIPERX02STATUS_delay[1]; // rv 0 + assign PIPERX02STATUS_in[2] = (PIPERX02STATUS[2] !== 1'bz) && PIPERX02STATUS_delay[2]; // rv 0 + assign PIPERX02SYNCHEADER_in[0] = (PIPERX02SYNCHEADER[0] !== 1'bz) && PIPERX02SYNCHEADER_delay[0]; // rv 0 + assign PIPERX02SYNCHEADER_in[1] = (PIPERX02SYNCHEADER[1] !== 1'bz) && PIPERX02SYNCHEADER_delay[1]; // rv 0 + assign PIPERX02VALID_in = (PIPERX02VALID !== 1'bz) && PIPERX02VALID_delay; // rv 0 + assign PIPERX03CHARISK_in[0] = (PIPERX03CHARISK[0] === 1'bz) || PIPERX03CHARISK_delay[0]; // rv 1 + assign PIPERX03CHARISK_in[1] = (PIPERX03CHARISK[1] === 1'bz) || PIPERX03CHARISK_delay[1]; // rv 1 + assign PIPERX03DATAVALID_in = (PIPERX03DATAVALID !== 1'bz) && PIPERX03DATAVALID_delay; // rv 0 + assign PIPERX03DATA_in[0] = (PIPERX03DATA[0] !== 1'bz) && PIPERX03DATA_delay[0]; // rv 0 + assign PIPERX03DATA_in[10] = (PIPERX03DATA[10] !== 1'bz) && PIPERX03DATA_delay[10]; // rv 0 + assign PIPERX03DATA_in[11] = (PIPERX03DATA[11] !== 1'bz) && PIPERX03DATA_delay[11]; // rv 0 + assign PIPERX03DATA_in[12] = (PIPERX03DATA[12] !== 1'bz) && PIPERX03DATA_delay[12]; // rv 0 + assign PIPERX03DATA_in[13] = (PIPERX03DATA[13] !== 1'bz) && PIPERX03DATA_delay[13]; // rv 0 + assign PIPERX03DATA_in[14] = (PIPERX03DATA[14] !== 1'bz) && PIPERX03DATA_delay[14]; // rv 0 + assign PIPERX03DATA_in[15] = (PIPERX03DATA[15] !== 1'bz) && PIPERX03DATA_delay[15]; // rv 0 + assign PIPERX03DATA_in[16] = (PIPERX03DATA[16] !== 1'bz) && PIPERX03DATA_delay[16]; // rv 0 + assign PIPERX03DATA_in[17] = (PIPERX03DATA[17] !== 1'bz) && PIPERX03DATA_delay[17]; // rv 0 + assign PIPERX03DATA_in[18] = (PIPERX03DATA[18] !== 1'bz) && PIPERX03DATA_delay[18]; // rv 0 + assign PIPERX03DATA_in[19] = (PIPERX03DATA[19] !== 1'bz) && PIPERX03DATA_delay[19]; // rv 0 + assign PIPERX03DATA_in[1] = (PIPERX03DATA[1] !== 1'bz) && PIPERX03DATA_delay[1]; // rv 0 + assign PIPERX03DATA_in[20] = (PIPERX03DATA[20] !== 1'bz) && PIPERX03DATA_delay[20]; // rv 0 + assign PIPERX03DATA_in[21] = (PIPERX03DATA[21] !== 1'bz) && PIPERX03DATA_delay[21]; // rv 0 + assign PIPERX03DATA_in[22] = (PIPERX03DATA[22] !== 1'bz) && PIPERX03DATA_delay[22]; // rv 0 + assign PIPERX03DATA_in[23] = (PIPERX03DATA[23] !== 1'bz) && PIPERX03DATA_delay[23]; // rv 0 + assign PIPERX03DATA_in[24] = (PIPERX03DATA[24] !== 1'bz) && PIPERX03DATA_delay[24]; // rv 0 + assign PIPERX03DATA_in[25] = (PIPERX03DATA[25] !== 1'bz) && PIPERX03DATA_delay[25]; // rv 0 + assign PIPERX03DATA_in[26] = (PIPERX03DATA[26] !== 1'bz) && PIPERX03DATA_delay[26]; // rv 0 + assign PIPERX03DATA_in[27] = (PIPERX03DATA[27] !== 1'bz) && PIPERX03DATA_delay[27]; // rv 0 + assign PIPERX03DATA_in[28] = (PIPERX03DATA[28] !== 1'bz) && PIPERX03DATA_delay[28]; // rv 0 + assign PIPERX03DATA_in[29] = (PIPERX03DATA[29] !== 1'bz) && PIPERX03DATA_delay[29]; // rv 0 + assign PIPERX03DATA_in[2] = (PIPERX03DATA[2] !== 1'bz) && PIPERX03DATA_delay[2]; // rv 0 + assign PIPERX03DATA_in[30] = (PIPERX03DATA[30] !== 1'bz) && PIPERX03DATA_delay[30]; // rv 0 + assign PIPERX03DATA_in[31] = (PIPERX03DATA[31] !== 1'bz) && PIPERX03DATA_delay[31]; // rv 0 + assign PIPERX03DATA_in[3] = (PIPERX03DATA[3] !== 1'bz) && PIPERX03DATA_delay[3]; // rv 0 + assign PIPERX03DATA_in[4] = (PIPERX03DATA[4] !== 1'bz) && PIPERX03DATA_delay[4]; // rv 0 + assign PIPERX03DATA_in[5] = (PIPERX03DATA[5] !== 1'bz) && PIPERX03DATA_delay[5]; // rv 0 + assign PIPERX03DATA_in[6] = (PIPERX03DATA[6] !== 1'bz) && PIPERX03DATA_delay[6]; // rv 0 + assign PIPERX03DATA_in[7] = (PIPERX03DATA[7] !== 1'bz) && PIPERX03DATA_delay[7]; // rv 0 + assign PIPERX03DATA_in[8] = (PIPERX03DATA[8] !== 1'bz) && PIPERX03DATA_delay[8]; // rv 0 + assign PIPERX03DATA_in[9] = (PIPERX03DATA[9] !== 1'bz) && PIPERX03DATA_delay[9]; // rv 0 + assign PIPERX03ELECIDLE_in = (PIPERX03ELECIDLE === 1'bz) || PIPERX03ELECIDLE_delay; // rv 1 + assign PIPERX03EQDONE_in = (PIPERX03EQDONE !== 1'bz) && PIPERX03EQDONE_delay; // rv 0 + assign PIPERX03EQLPADAPTDONE_in = (PIPERX03EQLPADAPTDONE !== 1'bz) && PIPERX03EQLPADAPTDONE_delay; // rv 0 + assign PIPERX03EQLPLFFSSEL_in = (PIPERX03EQLPLFFSSEL !== 1'bz) && PIPERX03EQLPLFFSSEL_delay; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX03EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX03EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX03EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX03EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX03EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX03EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX03EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX03EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX03EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX03EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX03EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX03EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX03EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX03EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX03EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX03EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX03EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX03EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX03PHYSTATUS_in = (PIPERX03PHYSTATUS === 1'bz) || PIPERX03PHYSTATUS_delay; // rv 1 + assign PIPERX03STARTBLOCK_in[0] = (PIPERX03STARTBLOCK[0] !== 1'bz) && PIPERX03STARTBLOCK_delay[0]; // rv 0 + assign PIPERX03STARTBLOCK_in[1] = (PIPERX03STARTBLOCK[1] !== 1'bz) && PIPERX03STARTBLOCK_delay[1]; // rv 0 + assign PIPERX03STATUS_in[0] = (PIPERX03STATUS[0] !== 1'bz) && PIPERX03STATUS_delay[0]; // rv 0 + assign PIPERX03STATUS_in[1] = (PIPERX03STATUS[1] !== 1'bz) && PIPERX03STATUS_delay[1]; // rv 0 + assign PIPERX03STATUS_in[2] = (PIPERX03STATUS[2] !== 1'bz) && PIPERX03STATUS_delay[2]; // rv 0 + assign PIPERX03SYNCHEADER_in[0] = (PIPERX03SYNCHEADER[0] !== 1'bz) && PIPERX03SYNCHEADER_delay[0]; // rv 0 + assign PIPERX03SYNCHEADER_in[1] = (PIPERX03SYNCHEADER[1] !== 1'bz) && PIPERX03SYNCHEADER_delay[1]; // rv 0 + assign PIPERX03VALID_in = (PIPERX03VALID !== 1'bz) && PIPERX03VALID_delay; // rv 0 + assign PIPERX04CHARISK_in[0] = (PIPERX04CHARISK[0] === 1'bz) || PIPERX04CHARISK_delay[0]; // rv 1 + assign PIPERX04CHARISK_in[1] = (PIPERX04CHARISK[1] === 1'bz) || PIPERX04CHARISK_delay[1]; // rv 1 + assign PIPERX04DATAVALID_in = (PIPERX04DATAVALID !== 1'bz) && PIPERX04DATAVALID_delay; // rv 0 + assign PIPERX04DATA_in[0] = (PIPERX04DATA[0] !== 1'bz) && PIPERX04DATA_delay[0]; // rv 0 + assign PIPERX04DATA_in[10] = (PIPERX04DATA[10] !== 1'bz) && PIPERX04DATA_delay[10]; // rv 0 + assign PIPERX04DATA_in[11] = (PIPERX04DATA[11] !== 1'bz) && PIPERX04DATA_delay[11]; // rv 0 + assign PIPERX04DATA_in[12] = (PIPERX04DATA[12] !== 1'bz) && PIPERX04DATA_delay[12]; // rv 0 + assign PIPERX04DATA_in[13] = (PIPERX04DATA[13] !== 1'bz) && PIPERX04DATA_delay[13]; // rv 0 + assign PIPERX04DATA_in[14] = (PIPERX04DATA[14] !== 1'bz) && PIPERX04DATA_delay[14]; // rv 0 + assign PIPERX04DATA_in[15] = (PIPERX04DATA[15] !== 1'bz) && PIPERX04DATA_delay[15]; // rv 0 + assign PIPERX04DATA_in[16] = (PIPERX04DATA[16] !== 1'bz) && PIPERX04DATA_delay[16]; // rv 0 + assign PIPERX04DATA_in[17] = (PIPERX04DATA[17] !== 1'bz) && PIPERX04DATA_delay[17]; // rv 0 + assign PIPERX04DATA_in[18] = (PIPERX04DATA[18] !== 1'bz) && PIPERX04DATA_delay[18]; // rv 0 + assign PIPERX04DATA_in[19] = (PIPERX04DATA[19] !== 1'bz) && PIPERX04DATA_delay[19]; // rv 0 + assign PIPERX04DATA_in[1] = (PIPERX04DATA[1] !== 1'bz) && PIPERX04DATA_delay[1]; // rv 0 + assign PIPERX04DATA_in[20] = (PIPERX04DATA[20] !== 1'bz) && PIPERX04DATA_delay[20]; // rv 0 + assign PIPERX04DATA_in[21] = (PIPERX04DATA[21] !== 1'bz) && PIPERX04DATA_delay[21]; // rv 0 + assign PIPERX04DATA_in[22] = (PIPERX04DATA[22] !== 1'bz) && PIPERX04DATA_delay[22]; // rv 0 + assign PIPERX04DATA_in[23] = (PIPERX04DATA[23] !== 1'bz) && PIPERX04DATA_delay[23]; // rv 0 + assign PIPERX04DATA_in[24] = (PIPERX04DATA[24] !== 1'bz) && PIPERX04DATA_delay[24]; // rv 0 + assign PIPERX04DATA_in[25] = (PIPERX04DATA[25] !== 1'bz) && PIPERX04DATA_delay[25]; // rv 0 + assign PIPERX04DATA_in[26] = (PIPERX04DATA[26] !== 1'bz) && PIPERX04DATA_delay[26]; // rv 0 + assign PIPERX04DATA_in[27] = (PIPERX04DATA[27] !== 1'bz) && PIPERX04DATA_delay[27]; // rv 0 + assign PIPERX04DATA_in[28] = (PIPERX04DATA[28] !== 1'bz) && PIPERX04DATA_delay[28]; // rv 0 + assign PIPERX04DATA_in[29] = (PIPERX04DATA[29] !== 1'bz) && PIPERX04DATA_delay[29]; // rv 0 + assign PIPERX04DATA_in[2] = (PIPERX04DATA[2] !== 1'bz) && PIPERX04DATA_delay[2]; // rv 0 + assign PIPERX04DATA_in[30] = (PIPERX04DATA[30] !== 1'bz) && PIPERX04DATA_delay[30]; // rv 0 + assign PIPERX04DATA_in[31] = (PIPERX04DATA[31] !== 1'bz) && PIPERX04DATA_delay[31]; // rv 0 + assign PIPERX04DATA_in[3] = (PIPERX04DATA[3] !== 1'bz) && PIPERX04DATA_delay[3]; // rv 0 + assign PIPERX04DATA_in[4] = (PIPERX04DATA[4] !== 1'bz) && PIPERX04DATA_delay[4]; // rv 0 + assign PIPERX04DATA_in[5] = (PIPERX04DATA[5] !== 1'bz) && PIPERX04DATA_delay[5]; // rv 0 + assign PIPERX04DATA_in[6] = (PIPERX04DATA[6] !== 1'bz) && PIPERX04DATA_delay[6]; // rv 0 + assign PIPERX04DATA_in[7] = (PIPERX04DATA[7] !== 1'bz) && PIPERX04DATA_delay[7]; // rv 0 + assign PIPERX04DATA_in[8] = (PIPERX04DATA[8] !== 1'bz) && PIPERX04DATA_delay[8]; // rv 0 + assign PIPERX04DATA_in[9] = (PIPERX04DATA[9] !== 1'bz) && PIPERX04DATA_delay[9]; // rv 0 + assign PIPERX04ELECIDLE_in = (PIPERX04ELECIDLE === 1'bz) || PIPERX04ELECIDLE_delay; // rv 1 + assign PIPERX04EQDONE_in = (PIPERX04EQDONE !== 1'bz) && PIPERX04EQDONE_delay; // rv 0 + assign PIPERX04EQLPADAPTDONE_in = (PIPERX04EQLPADAPTDONE !== 1'bz) && PIPERX04EQLPADAPTDONE_delay; // rv 0 + assign PIPERX04EQLPLFFSSEL_in = (PIPERX04EQLPLFFSSEL !== 1'bz) && PIPERX04EQLPLFFSSEL_delay; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX04EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX04EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX04EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX04EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX04EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX04EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX04EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX04EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX04EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX04EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX04EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX04EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX04EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX04EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX04EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX04EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX04EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX04EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX04PHYSTATUS_in = (PIPERX04PHYSTATUS === 1'bz) || PIPERX04PHYSTATUS_delay; // rv 1 + assign PIPERX04STARTBLOCK_in[0] = (PIPERX04STARTBLOCK[0] !== 1'bz) && PIPERX04STARTBLOCK_delay[0]; // rv 0 + assign PIPERX04STARTBLOCK_in[1] = (PIPERX04STARTBLOCK[1] !== 1'bz) && PIPERX04STARTBLOCK_delay[1]; // rv 0 + assign PIPERX04STATUS_in[0] = (PIPERX04STATUS[0] !== 1'bz) && PIPERX04STATUS_delay[0]; // rv 0 + assign PIPERX04STATUS_in[1] = (PIPERX04STATUS[1] !== 1'bz) && PIPERX04STATUS_delay[1]; // rv 0 + assign PIPERX04STATUS_in[2] = (PIPERX04STATUS[2] !== 1'bz) && PIPERX04STATUS_delay[2]; // rv 0 + assign PIPERX04SYNCHEADER_in[0] = (PIPERX04SYNCHEADER[0] !== 1'bz) && PIPERX04SYNCHEADER_delay[0]; // rv 0 + assign PIPERX04SYNCHEADER_in[1] = (PIPERX04SYNCHEADER[1] !== 1'bz) && PIPERX04SYNCHEADER_delay[1]; // rv 0 + assign PIPERX04VALID_in = (PIPERX04VALID !== 1'bz) && PIPERX04VALID_delay; // rv 0 + assign PIPERX05CHARISK_in[0] = (PIPERX05CHARISK[0] === 1'bz) || PIPERX05CHARISK_delay[0]; // rv 1 + assign PIPERX05CHARISK_in[1] = (PIPERX05CHARISK[1] === 1'bz) || PIPERX05CHARISK_delay[1]; // rv 1 + assign PIPERX05DATAVALID_in = (PIPERX05DATAVALID !== 1'bz) && PIPERX05DATAVALID_delay; // rv 0 + assign PIPERX05DATA_in[0] = (PIPERX05DATA[0] !== 1'bz) && PIPERX05DATA_delay[0]; // rv 0 + assign PIPERX05DATA_in[10] = (PIPERX05DATA[10] !== 1'bz) && PIPERX05DATA_delay[10]; // rv 0 + assign PIPERX05DATA_in[11] = (PIPERX05DATA[11] !== 1'bz) && PIPERX05DATA_delay[11]; // rv 0 + assign PIPERX05DATA_in[12] = (PIPERX05DATA[12] !== 1'bz) && PIPERX05DATA_delay[12]; // rv 0 + assign PIPERX05DATA_in[13] = (PIPERX05DATA[13] !== 1'bz) && PIPERX05DATA_delay[13]; // rv 0 + assign PIPERX05DATA_in[14] = (PIPERX05DATA[14] !== 1'bz) && PIPERX05DATA_delay[14]; // rv 0 + assign PIPERX05DATA_in[15] = (PIPERX05DATA[15] !== 1'bz) && PIPERX05DATA_delay[15]; // rv 0 + assign PIPERX05DATA_in[16] = (PIPERX05DATA[16] !== 1'bz) && PIPERX05DATA_delay[16]; // rv 0 + assign PIPERX05DATA_in[17] = (PIPERX05DATA[17] !== 1'bz) && PIPERX05DATA_delay[17]; // rv 0 + assign PIPERX05DATA_in[18] = (PIPERX05DATA[18] !== 1'bz) && PIPERX05DATA_delay[18]; // rv 0 + assign PIPERX05DATA_in[19] = (PIPERX05DATA[19] !== 1'bz) && PIPERX05DATA_delay[19]; // rv 0 + assign PIPERX05DATA_in[1] = (PIPERX05DATA[1] !== 1'bz) && PIPERX05DATA_delay[1]; // rv 0 + assign PIPERX05DATA_in[20] = (PIPERX05DATA[20] !== 1'bz) && PIPERX05DATA_delay[20]; // rv 0 + assign PIPERX05DATA_in[21] = (PIPERX05DATA[21] !== 1'bz) && PIPERX05DATA_delay[21]; // rv 0 + assign PIPERX05DATA_in[22] = (PIPERX05DATA[22] !== 1'bz) && PIPERX05DATA_delay[22]; // rv 0 + assign PIPERX05DATA_in[23] = (PIPERX05DATA[23] !== 1'bz) && PIPERX05DATA_delay[23]; // rv 0 + assign PIPERX05DATA_in[24] = (PIPERX05DATA[24] !== 1'bz) && PIPERX05DATA_delay[24]; // rv 0 + assign PIPERX05DATA_in[25] = (PIPERX05DATA[25] !== 1'bz) && PIPERX05DATA_delay[25]; // rv 0 + assign PIPERX05DATA_in[26] = (PIPERX05DATA[26] !== 1'bz) && PIPERX05DATA_delay[26]; // rv 0 + assign PIPERX05DATA_in[27] = (PIPERX05DATA[27] !== 1'bz) && PIPERX05DATA_delay[27]; // rv 0 + assign PIPERX05DATA_in[28] = (PIPERX05DATA[28] !== 1'bz) && PIPERX05DATA_delay[28]; // rv 0 + assign PIPERX05DATA_in[29] = (PIPERX05DATA[29] !== 1'bz) && PIPERX05DATA_delay[29]; // rv 0 + assign PIPERX05DATA_in[2] = (PIPERX05DATA[2] !== 1'bz) && PIPERX05DATA_delay[2]; // rv 0 + assign PIPERX05DATA_in[30] = (PIPERX05DATA[30] !== 1'bz) && PIPERX05DATA_delay[30]; // rv 0 + assign PIPERX05DATA_in[31] = (PIPERX05DATA[31] !== 1'bz) && PIPERX05DATA_delay[31]; // rv 0 + assign PIPERX05DATA_in[3] = (PIPERX05DATA[3] !== 1'bz) && PIPERX05DATA_delay[3]; // rv 0 + assign PIPERX05DATA_in[4] = (PIPERX05DATA[4] !== 1'bz) && PIPERX05DATA_delay[4]; // rv 0 + assign PIPERX05DATA_in[5] = (PIPERX05DATA[5] !== 1'bz) && PIPERX05DATA_delay[5]; // rv 0 + assign PIPERX05DATA_in[6] = (PIPERX05DATA[6] !== 1'bz) && PIPERX05DATA_delay[6]; // rv 0 + assign PIPERX05DATA_in[7] = (PIPERX05DATA[7] !== 1'bz) && PIPERX05DATA_delay[7]; // rv 0 + assign PIPERX05DATA_in[8] = (PIPERX05DATA[8] !== 1'bz) && PIPERX05DATA_delay[8]; // rv 0 + assign PIPERX05DATA_in[9] = (PIPERX05DATA[9] !== 1'bz) && PIPERX05DATA_delay[9]; // rv 0 + assign PIPERX05ELECIDLE_in = (PIPERX05ELECIDLE === 1'bz) || PIPERX05ELECIDLE_delay; // rv 1 + assign PIPERX05EQDONE_in = (PIPERX05EQDONE !== 1'bz) && PIPERX05EQDONE_delay; // rv 0 + assign PIPERX05EQLPADAPTDONE_in = (PIPERX05EQLPADAPTDONE !== 1'bz) && PIPERX05EQLPADAPTDONE_delay; // rv 0 + assign PIPERX05EQLPLFFSSEL_in = (PIPERX05EQLPLFFSSEL !== 1'bz) && PIPERX05EQLPLFFSSEL_delay; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX05EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX05EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX05EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX05EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX05EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX05EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX05EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX05EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX05EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX05EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX05EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX05EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX05EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX05EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX05EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX05EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX05EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX05EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX05PHYSTATUS_in = (PIPERX05PHYSTATUS === 1'bz) || PIPERX05PHYSTATUS_delay; // rv 1 + assign PIPERX05STARTBLOCK_in[0] = (PIPERX05STARTBLOCK[0] !== 1'bz) && PIPERX05STARTBLOCK_delay[0]; // rv 0 + assign PIPERX05STARTBLOCK_in[1] = (PIPERX05STARTBLOCK[1] !== 1'bz) && PIPERX05STARTBLOCK_delay[1]; // rv 0 + assign PIPERX05STATUS_in[0] = (PIPERX05STATUS[0] !== 1'bz) && PIPERX05STATUS_delay[0]; // rv 0 + assign PIPERX05STATUS_in[1] = (PIPERX05STATUS[1] !== 1'bz) && PIPERX05STATUS_delay[1]; // rv 0 + assign PIPERX05STATUS_in[2] = (PIPERX05STATUS[2] !== 1'bz) && PIPERX05STATUS_delay[2]; // rv 0 + assign PIPERX05SYNCHEADER_in[0] = (PIPERX05SYNCHEADER[0] !== 1'bz) && PIPERX05SYNCHEADER_delay[0]; // rv 0 + assign PIPERX05SYNCHEADER_in[1] = (PIPERX05SYNCHEADER[1] !== 1'bz) && PIPERX05SYNCHEADER_delay[1]; // rv 0 + assign PIPERX05VALID_in = (PIPERX05VALID !== 1'bz) && PIPERX05VALID_delay; // rv 0 + assign PIPERX06CHARISK_in[0] = (PIPERX06CHARISK[0] === 1'bz) || PIPERX06CHARISK_delay[0]; // rv 1 + assign PIPERX06CHARISK_in[1] = (PIPERX06CHARISK[1] === 1'bz) || PIPERX06CHARISK_delay[1]; // rv 1 + assign PIPERX06DATAVALID_in = (PIPERX06DATAVALID !== 1'bz) && PIPERX06DATAVALID_delay; // rv 0 + assign PIPERX06DATA_in[0] = (PIPERX06DATA[0] !== 1'bz) && PIPERX06DATA_delay[0]; // rv 0 + assign PIPERX06DATA_in[10] = (PIPERX06DATA[10] !== 1'bz) && PIPERX06DATA_delay[10]; // rv 0 + assign PIPERX06DATA_in[11] = (PIPERX06DATA[11] !== 1'bz) && PIPERX06DATA_delay[11]; // rv 0 + assign PIPERX06DATA_in[12] = (PIPERX06DATA[12] !== 1'bz) && PIPERX06DATA_delay[12]; // rv 0 + assign PIPERX06DATA_in[13] = (PIPERX06DATA[13] !== 1'bz) && PIPERX06DATA_delay[13]; // rv 0 + assign PIPERX06DATA_in[14] = (PIPERX06DATA[14] !== 1'bz) && PIPERX06DATA_delay[14]; // rv 0 + assign PIPERX06DATA_in[15] = (PIPERX06DATA[15] !== 1'bz) && PIPERX06DATA_delay[15]; // rv 0 + assign PIPERX06DATA_in[16] = (PIPERX06DATA[16] !== 1'bz) && PIPERX06DATA_delay[16]; // rv 0 + assign PIPERX06DATA_in[17] = (PIPERX06DATA[17] !== 1'bz) && PIPERX06DATA_delay[17]; // rv 0 + assign PIPERX06DATA_in[18] = (PIPERX06DATA[18] !== 1'bz) && PIPERX06DATA_delay[18]; // rv 0 + assign PIPERX06DATA_in[19] = (PIPERX06DATA[19] !== 1'bz) && PIPERX06DATA_delay[19]; // rv 0 + assign PIPERX06DATA_in[1] = (PIPERX06DATA[1] !== 1'bz) && PIPERX06DATA_delay[1]; // rv 0 + assign PIPERX06DATA_in[20] = (PIPERX06DATA[20] !== 1'bz) && PIPERX06DATA_delay[20]; // rv 0 + assign PIPERX06DATA_in[21] = (PIPERX06DATA[21] !== 1'bz) && PIPERX06DATA_delay[21]; // rv 0 + assign PIPERX06DATA_in[22] = (PIPERX06DATA[22] !== 1'bz) && PIPERX06DATA_delay[22]; // rv 0 + assign PIPERX06DATA_in[23] = (PIPERX06DATA[23] !== 1'bz) && PIPERX06DATA_delay[23]; // rv 0 + assign PIPERX06DATA_in[24] = (PIPERX06DATA[24] !== 1'bz) && PIPERX06DATA_delay[24]; // rv 0 + assign PIPERX06DATA_in[25] = (PIPERX06DATA[25] !== 1'bz) && PIPERX06DATA_delay[25]; // rv 0 + assign PIPERX06DATA_in[26] = (PIPERX06DATA[26] !== 1'bz) && PIPERX06DATA_delay[26]; // rv 0 + assign PIPERX06DATA_in[27] = (PIPERX06DATA[27] !== 1'bz) && PIPERX06DATA_delay[27]; // rv 0 + assign PIPERX06DATA_in[28] = (PIPERX06DATA[28] !== 1'bz) && PIPERX06DATA_delay[28]; // rv 0 + assign PIPERX06DATA_in[29] = (PIPERX06DATA[29] !== 1'bz) && PIPERX06DATA_delay[29]; // rv 0 + assign PIPERX06DATA_in[2] = (PIPERX06DATA[2] !== 1'bz) && PIPERX06DATA_delay[2]; // rv 0 + assign PIPERX06DATA_in[30] = (PIPERX06DATA[30] !== 1'bz) && PIPERX06DATA_delay[30]; // rv 0 + assign PIPERX06DATA_in[31] = (PIPERX06DATA[31] !== 1'bz) && PIPERX06DATA_delay[31]; // rv 0 + assign PIPERX06DATA_in[3] = (PIPERX06DATA[3] !== 1'bz) && PIPERX06DATA_delay[3]; // rv 0 + assign PIPERX06DATA_in[4] = (PIPERX06DATA[4] !== 1'bz) && PIPERX06DATA_delay[4]; // rv 0 + assign PIPERX06DATA_in[5] = (PIPERX06DATA[5] !== 1'bz) && PIPERX06DATA_delay[5]; // rv 0 + assign PIPERX06DATA_in[6] = (PIPERX06DATA[6] !== 1'bz) && PIPERX06DATA_delay[6]; // rv 0 + assign PIPERX06DATA_in[7] = (PIPERX06DATA[7] !== 1'bz) && PIPERX06DATA_delay[7]; // rv 0 + assign PIPERX06DATA_in[8] = (PIPERX06DATA[8] !== 1'bz) && PIPERX06DATA_delay[8]; // rv 0 + assign PIPERX06DATA_in[9] = (PIPERX06DATA[9] !== 1'bz) && PIPERX06DATA_delay[9]; // rv 0 + assign PIPERX06ELECIDLE_in = (PIPERX06ELECIDLE === 1'bz) || PIPERX06ELECIDLE_delay; // rv 1 + assign PIPERX06EQDONE_in = (PIPERX06EQDONE !== 1'bz) && PIPERX06EQDONE_delay; // rv 0 + assign PIPERX06EQLPADAPTDONE_in = (PIPERX06EQLPADAPTDONE !== 1'bz) && PIPERX06EQLPADAPTDONE_delay; // rv 0 + assign PIPERX06EQLPLFFSSEL_in = (PIPERX06EQLPLFFSSEL !== 1'bz) && PIPERX06EQLPLFFSSEL_delay; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX06EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX06EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX06EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX06EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX06EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX06EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX06EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX06EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX06EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX06EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX06EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX06EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX06EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX06EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX06EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX06EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX06EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX06EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX06PHYSTATUS_in = (PIPERX06PHYSTATUS === 1'bz) || PIPERX06PHYSTATUS_delay; // rv 1 + assign PIPERX06STARTBLOCK_in[0] = (PIPERX06STARTBLOCK[0] !== 1'bz) && PIPERX06STARTBLOCK_delay[0]; // rv 0 + assign PIPERX06STARTBLOCK_in[1] = (PIPERX06STARTBLOCK[1] !== 1'bz) && PIPERX06STARTBLOCK_delay[1]; // rv 0 + assign PIPERX06STATUS_in[0] = (PIPERX06STATUS[0] !== 1'bz) && PIPERX06STATUS_delay[0]; // rv 0 + assign PIPERX06STATUS_in[1] = (PIPERX06STATUS[1] !== 1'bz) && PIPERX06STATUS_delay[1]; // rv 0 + assign PIPERX06STATUS_in[2] = (PIPERX06STATUS[2] !== 1'bz) && PIPERX06STATUS_delay[2]; // rv 0 + assign PIPERX06SYNCHEADER_in[0] = (PIPERX06SYNCHEADER[0] !== 1'bz) && PIPERX06SYNCHEADER_delay[0]; // rv 0 + assign PIPERX06SYNCHEADER_in[1] = (PIPERX06SYNCHEADER[1] !== 1'bz) && PIPERX06SYNCHEADER_delay[1]; // rv 0 + assign PIPERX06VALID_in = (PIPERX06VALID !== 1'bz) && PIPERX06VALID_delay; // rv 0 + assign PIPERX07CHARISK_in[0] = (PIPERX07CHARISK[0] === 1'bz) || PIPERX07CHARISK_delay[0]; // rv 1 + assign PIPERX07CHARISK_in[1] = (PIPERX07CHARISK[1] === 1'bz) || PIPERX07CHARISK_delay[1]; // rv 1 + assign PIPERX07DATAVALID_in = (PIPERX07DATAVALID !== 1'bz) && PIPERX07DATAVALID_delay; // rv 0 + assign PIPERX07DATA_in[0] = (PIPERX07DATA[0] !== 1'bz) && PIPERX07DATA_delay[0]; // rv 0 + assign PIPERX07DATA_in[10] = (PIPERX07DATA[10] !== 1'bz) && PIPERX07DATA_delay[10]; // rv 0 + assign PIPERX07DATA_in[11] = (PIPERX07DATA[11] !== 1'bz) && PIPERX07DATA_delay[11]; // rv 0 + assign PIPERX07DATA_in[12] = (PIPERX07DATA[12] !== 1'bz) && PIPERX07DATA_delay[12]; // rv 0 + assign PIPERX07DATA_in[13] = (PIPERX07DATA[13] !== 1'bz) && PIPERX07DATA_delay[13]; // rv 0 + assign PIPERX07DATA_in[14] = (PIPERX07DATA[14] !== 1'bz) && PIPERX07DATA_delay[14]; // rv 0 + assign PIPERX07DATA_in[15] = (PIPERX07DATA[15] !== 1'bz) && PIPERX07DATA_delay[15]; // rv 0 + assign PIPERX07DATA_in[16] = (PIPERX07DATA[16] !== 1'bz) && PIPERX07DATA_delay[16]; // rv 0 + assign PIPERX07DATA_in[17] = (PIPERX07DATA[17] !== 1'bz) && PIPERX07DATA_delay[17]; // rv 0 + assign PIPERX07DATA_in[18] = (PIPERX07DATA[18] !== 1'bz) && PIPERX07DATA_delay[18]; // rv 0 + assign PIPERX07DATA_in[19] = (PIPERX07DATA[19] !== 1'bz) && PIPERX07DATA_delay[19]; // rv 0 + assign PIPERX07DATA_in[1] = (PIPERX07DATA[1] !== 1'bz) && PIPERX07DATA_delay[1]; // rv 0 + assign PIPERX07DATA_in[20] = (PIPERX07DATA[20] !== 1'bz) && PIPERX07DATA_delay[20]; // rv 0 + assign PIPERX07DATA_in[21] = (PIPERX07DATA[21] !== 1'bz) && PIPERX07DATA_delay[21]; // rv 0 + assign PIPERX07DATA_in[22] = (PIPERX07DATA[22] !== 1'bz) && PIPERX07DATA_delay[22]; // rv 0 + assign PIPERX07DATA_in[23] = (PIPERX07DATA[23] !== 1'bz) && PIPERX07DATA_delay[23]; // rv 0 + assign PIPERX07DATA_in[24] = (PIPERX07DATA[24] !== 1'bz) && PIPERX07DATA_delay[24]; // rv 0 + assign PIPERX07DATA_in[25] = (PIPERX07DATA[25] !== 1'bz) && PIPERX07DATA_delay[25]; // rv 0 + assign PIPERX07DATA_in[26] = (PIPERX07DATA[26] !== 1'bz) && PIPERX07DATA_delay[26]; // rv 0 + assign PIPERX07DATA_in[27] = (PIPERX07DATA[27] !== 1'bz) && PIPERX07DATA_delay[27]; // rv 0 + assign PIPERX07DATA_in[28] = (PIPERX07DATA[28] !== 1'bz) && PIPERX07DATA_delay[28]; // rv 0 + assign PIPERX07DATA_in[29] = (PIPERX07DATA[29] !== 1'bz) && PIPERX07DATA_delay[29]; // rv 0 + assign PIPERX07DATA_in[2] = (PIPERX07DATA[2] !== 1'bz) && PIPERX07DATA_delay[2]; // rv 0 + assign PIPERX07DATA_in[30] = (PIPERX07DATA[30] !== 1'bz) && PIPERX07DATA_delay[30]; // rv 0 + assign PIPERX07DATA_in[31] = (PIPERX07DATA[31] !== 1'bz) && PIPERX07DATA_delay[31]; // rv 0 + assign PIPERX07DATA_in[3] = (PIPERX07DATA[3] !== 1'bz) && PIPERX07DATA_delay[3]; // rv 0 + assign PIPERX07DATA_in[4] = (PIPERX07DATA[4] !== 1'bz) && PIPERX07DATA_delay[4]; // rv 0 + assign PIPERX07DATA_in[5] = (PIPERX07DATA[5] !== 1'bz) && PIPERX07DATA_delay[5]; // rv 0 + assign PIPERX07DATA_in[6] = (PIPERX07DATA[6] !== 1'bz) && PIPERX07DATA_delay[6]; // rv 0 + assign PIPERX07DATA_in[7] = (PIPERX07DATA[7] !== 1'bz) && PIPERX07DATA_delay[7]; // rv 0 + assign PIPERX07DATA_in[8] = (PIPERX07DATA[8] !== 1'bz) && PIPERX07DATA_delay[8]; // rv 0 + assign PIPERX07DATA_in[9] = (PIPERX07DATA[9] !== 1'bz) && PIPERX07DATA_delay[9]; // rv 0 + assign PIPERX07ELECIDLE_in = (PIPERX07ELECIDLE === 1'bz) || PIPERX07ELECIDLE_delay; // rv 1 + assign PIPERX07EQDONE_in = (PIPERX07EQDONE !== 1'bz) && PIPERX07EQDONE_delay; // rv 0 + assign PIPERX07EQLPADAPTDONE_in = (PIPERX07EQLPADAPTDONE !== 1'bz) && PIPERX07EQLPADAPTDONE_delay; // rv 0 + assign PIPERX07EQLPLFFSSEL_in = (PIPERX07EQLPLFFSSEL !== 1'bz) && PIPERX07EQLPLFFSSEL_delay; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX07EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX07EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX07EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX07EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX07EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX07EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX07EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX07EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX07EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX07EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX07EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX07EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX07EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX07EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX07EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX07EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX07EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX07EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX07PHYSTATUS_in = (PIPERX07PHYSTATUS === 1'bz) || PIPERX07PHYSTATUS_delay; // rv 1 + assign PIPERX07STARTBLOCK_in[0] = (PIPERX07STARTBLOCK[0] !== 1'bz) && PIPERX07STARTBLOCK_delay[0]; // rv 0 + assign PIPERX07STARTBLOCK_in[1] = (PIPERX07STARTBLOCK[1] !== 1'bz) && PIPERX07STARTBLOCK_delay[1]; // rv 0 + assign PIPERX07STATUS_in[0] = (PIPERX07STATUS[0] !== 1'bz) && PIPERX07STATUS_delay[0]; // rv 0 + assign PIPERX07STATUS_in[1] = (PIPERX07STATUS[1] !== 1'bz) && PIPERX07STATUS_delay[1]; // rv 0 + assign PIPERX07STATUS_in[2] = (PIPERX07STATUS[2] !== 1'bz) && PIPERX07STATUS_delay[2]; // rv 0 + assign PIPERX07SYNCHEADER_in[0] = (PIPERX07SYNCHEADER[0] !== 1'bz) && PIPERX07SYNCHEADER_delay[0]; // rv 0 + assign PIPERX07SYNCHEADER_in[1] = (PIPERX07SYNCHEADER[1] !== 1'bz) && PIPERX07SYNCHEADER_delay[1]; // rv 0 + assign PIPERX07VALID_in = (PIPERX07VALID !== 1'bz) && PIPERX07VALID_delay; // rv 0 + assign PIPERX08CHARISK_in[0] = (PIPERX08CHARISK[0] === 1'bz) || PIPERX08CHARISK_delay[0]; // rv 1 + assign PIPERX08CHARISK_in[1] = (PIPERX08CHARISK[1] === 1'bz) || PIPERX08CHARISK_delay[1]; // rv 1 + assign PIPERX08DATAVALID_in = (PIPERX08DATAVALID !== 1'bz) && PIPERX08DATAVALID_delay; // rv 0 + assign PIPERX08DATA_in[0] = (PIPERX08DATA[0] !== 1'bz) && PIPERX08DATA_delay[0]; // rv 0 + assign PIPERX08DATA_in[10] = (PIPERX08DATA[10] !== 1'bz) && PIPERX08DATA_delay[10]; // rv 0 + assign PIPERX08DATA_in[11] = (PIPERX08DATA[11] !== 1'bz) && PIPERX08DATA_delay[11]; // rv 0 + assign PIPERX08DATA_in[12] = (PIPERX08DATA[12] !== 1'bz) && PIPERX08DATA_delay[12]; // rv 0 + assign PIPERX08DATA_in[13] = (PIPERX08DATA[13] !== 1'bz) && PIPERX08DATA_delay[13]; // rv 0 + assign PIPERX08DATA_in[14] = (PIPERX08DATA[14] !== 1'bz) && PIPERX08DATA_delay[14]; // rv 0 + assign PIPERX08DATA_in[15] = (PIPERX08DATA[15] !== 1'bz) && PIPERX08DATA_delay[15]; // rv 0 + assign PIPERX08DATA_in[16] = (PIPERX08DATA[16] !== 1'bz) && PIPERX08DATA_delay[16]; // rv 0 + assign PIPERX08DATA_in[17] = (PIPERX08DATA[17] !== 1'bz) && PIPERX08DATA_delay[17]; // rv 0 + assign PIPERX08DATA_in[18] = (PIPERX08DATA[18] !== 1'bz) && PIPERX08DATA_delay[18]; // rv 0 + assign PIPERX08DATA_in[19] = (PIPERX08DATA[19] !== 1'bz) && PIPERX08DATA_delay[19]; // rv 0 + assign PIPERX08DATA_in[1] = (PIPERX08DATA[1] !== 1'bz) && PIPERX08DATA_delay[1]; // rv 0 + assign PIPERX08DATA_in[20] = (PIPERX08DATA[20] !== 1'bz) && PIPERX08DATA_delay[20]; // rv 0 + assign PIPERX08DATA_in[21] = (PIPERX08DATA[21] !== 1'bz) && PIPERX08DATA_delay[21]; // rv 0 + assign PIPERX08DATA_in[22] = (PIPERX08DATA[22] !== 1'bz) && PIPERX08DATA_delay[22]; // rv 0 + assign PIPERX08DATA_in[23] = (PIPERX08DATA[23] !== 1'bz) && PIPERX08DATA_delay[23]; // rv 0 + assign PIPERX08DATA_in[24] = (PIPERX08DATA[24] !== 1'bz) && PIPERX08DATA_delay[24]; // rv 0 + assign PIPERX08DATA_in[25] = (PIPERX08DATA[25] !== 1'bz) && PIPERX08DATA_delay[25]; // rv 0 + assign PIPERX08DATA_in[26] = (PIPERX08DATA[26] !== 1'bz) && PIPERX08DATA_delay[26]; // rv 0 + assign PIPERX08DATA_in[27] = (PIPERX08DATA[27] !== 1'bz) && PIPERX08DATA_delay[27]; // rv 0 + assign PIPERX08DATA_in[28] = (PIPERX08DATA[28] !== 1'bz) && PIPERX08DATA_delay[28]; // rv 0 + assign PIPERX08DATA_in[29] = (PIPERX08DATA[29] !== 1'bz) && PIPERX08DATA_delay[29]; // rv 0 + assign PIPERX08DATA_in[2] = (PIPERX08DATA[2] !== 1'bz) && PIPERX08DATA_delay[2]; // rv 0 + assign PIPERX08DATA_in[30] = (PIPERX08DATA[30] !== 1'bz) && PIPERX08DATA_delay[30]; // rv 0 + assign PIPERX08DATA_in[31] = (PIPERX08DATA[31] !== 1'bz) && PIPERX08DATA_delay[31]; // rv 0 + assign PIPERX08DATA_in[3] = (PIPERX08DATA[3] !== 1'bz) && PIPERX08DATA_delay[3]; // rv 0 + assign PIPERX08DATA_in[4] = (PIPERX08DATA[4] !== 1'bz) && PIPERX08DATA_delay[4]; // rv 0 + assign PIPERX08DATA_in[5] = (PIPERX08DATA[5] !== 1'bz) && PIPERX08DATA_delay[5]; // rv 0 + assign PIPERX08DATA_in[6] = (PIPERX08DATA[6] !== 1'bz) && PIPERX08DATA_delay[6]; // rv 0 + assign PIPERX08DATA_in[7] = (PIPERX08DATA[7] !== 1'bz) && PIPERX08DATA_delay[7]; // rv 0 + assign PIPERX08DATA_in[8] = (PIPERX08DATA[8] !== 1'bz) && PIPERX08DATA_delay[8]; // rv 0 + assign PIPERX08DATA_in[9] = (PIPERX08DATA[9] !== 1'bz) && PIPERX08DATA_delay[9]; // rv 0 + assign PIPERX08ELECIDLE_in = (PIPERX08ELECIDLE === 1'bz) || PIPERX08ELECIDLE_delay; // rv 1 + assign PIPERX08EQDONE_in = (PIPERX08EQDONE !== 1'bz) && PIPERX08EQDONE_delay; // rv 0 + assign PIPERX08EQLPADAPTDONE_in = (PIPERX08EQLPADAPTDONE !== 1'bz) && PIPERX08EQLPADAPTDONE_delay; // rv 0 + assign PIPERX08EQLPLFFSSEL_in = (PIPERX08EQLPLFFSSEL !== 1'bz) && PIPERX08EQLPLFFSSEL_delay; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX08EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX08EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX08EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX08EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX08EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX08EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX08EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX08EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX08EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX08EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX08EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX08EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX08EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX08EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX08EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX08EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX08EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX08EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX08PHYSTATUS_in = (PIPERX08PHYSTATUS === 1'bz) || PIPERX08PHYSTATUS_delay; // rv 1 + assign PIPERX08STARTBLOCK_in[0] = (PIPERX08STARTBLOCK[0] !== 1'bz) && PIPERX08STARTBLOCK_delay[0]; // rv 0 + assign PIPERX08STARTBLOCK_in[1] = (PIPERX08STARTBLOCK[1] !== 1'bz) && PIPERX08STARTBLOCK_delay[1]; // rv 0 + assign PIPERX08STATUS_in[0] = (PIPERX08STATUS[0] !== 1'bz) && PIPERX08STATUS_delay[0]; // rv 0 + assign PIPERX08STATUS_in[1] = (PIPERX08STATUS[1] !== 1'bz) && PIPERX08STATUS_delay[1]; // rv 0 + assign PIPERX08STATUS_in[2] = (PIPERX08STATUS[2] !== 1'bz) && PIPERX08STATUS_delay[2]; // rv 0 + assign PIPERX08SYNCHEADER_in[0] = (PIPERX08SYNCHEADER[0] !== 1'bz) && PIPERX08SYNCHEADER_delay[0]; // rv 0 + assign PIPERX08SYNCHEADER_in[1] = (PIPERX08SYNCHEADER[1] !== 1'bz) && PIPERX08SYNCHEADER_delay[1]; // rv 0 + assign PIPERX08VALID_in = (PIPERX08VALID !== 1'bz) && PIPERX08VALID_delay; // rv 0 + assign PIPERX09CHARISK_in[0] = (PIPERX09CHARISK[0] === 1'bz) || PIPERX09CHARISK_delay[0]; // rv 1 + assign PIPERX09CHARISK_in[1] = (PIPERX09CHARISK[1] === 1'bz) || PIPERX09CHARISK_delay[1]; // rv 1 + assign PIPERX09DATAVALID_in = (PIPERX09DATAVALID !== 1'bz) && PIPERX09DATAVALID_delay; // rv 0 + assign PIPERX09DATA_in[0] = (PIPERX09DATA[0] !== 1'bz) && PIPERX09DATA_delay[0]; // rv 0 + assign PIPERX09DATA_in[10] = (PIPERX09DATA[10] !== 1'bz) && PIPERX09DATA_delay[10]; // rv 0 + assign PIPERX09DATA_in[11] = (PIPERX09DATA[11] !== 1'bz) && PIPERX09DATA_delay[11]; // rv 0 + assign PIPERX09DATA_in[12] = (PIPERX09DATA[12] !== 1'bz) && PIPERX09DATA_delay[12]; // rv 0 + assign PIPERX09DATA_in[13] = (PIPERX09DATA[13] !== 1'bz) && PIPERX09DATA_delay[13]; // rv 0 + assign PIPERX09DATA_in[14] = (PIPERX09DATA[14] !== 1'bz) && PIPERX09DATA_delay[14]; // rv 0 + assign PIPERX09DATA_in[15] = (PIPERX09DATA[15] !== 1'bz) && PIPERX09DATA_delay[15]; // rv 0 + assign PIPERX09DATA_in[16] = (PIPERX09DATA[16] !== 1'bz) && PIPERX09DATA_delay[16]; // rv 0 + assign PIPERX09DATA_in[17] = (PIPERX09DATA[17] !== 1'bz) && PIPERX09DATA_delay[17]; // rv 0 + assign PIPERX09DATA_in[18] = (PIPERX09DATA[18] !== 1'bz) && PIPERX09DATA_delay[18]; // rv 0 + assign PIPERX09DATA_in[19] = (PIPERX09DATA[19] !== 1'bz) && PIPERX09DATA_delay[19]; // rv 0 + assign PIPERX09DATA_in[1] = (PIPERX09DATA[1] !== 1'bz) && PIPERX09DATA_delay[1]; // rv 0 + assign PIPERX09DATA_in[20] = (PIPERX09DATA[20] !== 1'bz) && PIPERX09DATA_delay[20]; // rv 0 + assign PIPERX09DATA_in[21] = (PIPERX09DATA[21] !== 1'bz) && PIPERX09DATA_delay[21]; // rv 0 + assign PIPERX09DATA_in[22] = (PIPERX09DATA[22] !== 1'bz) && PIPERX09DATA_delay[22]; // rv 0 + assign PIPERX09DATA_in[23] = (PIPERX09DATA[23] !== 1'bz) && PIPERX09DATA_delay[23]; // rv 0 + assign PIPERX09DATA_in[24] = (PIPERX09DATA[24] !== 1'bz) && PIPERX09DATA_delay[24]; // rv 0 + assign PIPERX09DATA_in[25] = (PIPERX09DATA[25] !== 1'bz) && PIPERX09DATA_delay[25]; // rv 0 + assign PIPERX09DATA_in[26] = (PIPERX09DATA[26] !== 1'bz) && PIPERX09DATA_delay[26]; // rv 0 + assign PIPERX09DATA_in[27] = (PIPERX09DATA[27] !== 1'bz) && PIPERX09DATA_delay[27]; // rv 0 + assign PIPERX09DATA_in[28] = (PIPERX09DATA[28] !== 1'bz) && PIPERX09DATA_delay[28]; // rv 0 + assign PIPERX09DATA_in[29] = (PIPERX09DATA[29] !== 1'bz) && PIPERX09DATA_delay[29]; // rv 0 + assign PIPERX09DATA_in[2] = (PIPERX09DATA[2] !== 1'bz) && PIPERX09DATA_delay[2]; // rv 0 + assign PIPERX09DATA_in[30] = (PIPERX09DATA[30] !== 1'bz) && PIPERX09DATA_delay[30]; // rv 0 + assign PIPERX09DATA_in[31] = (PIPERX09DATA[31] !== 1'bz) && PIPERX09DATA_delay[31]; // rv 0 + assign PIPERX09DATA_in[3] = (PIPERX09DATA[3] !== 1'bz) && PIPERX09DATA_delay[3]; // rv 0 + assign PIPERX09DATA_in[4] = (PIPERX09DATA[4] !== 1'bz) && PIPERX09DATA_delay[4]; // rv 0 + assign PIPERX09DATA_in[5] = (PIPERX09DATA[5] !== 1'bz) && PIPERX09DATA_delay[5]; // rv 0 + assign PIPERX09DATA_in[6] = (PIPERX09DATA[6] !== 1'bz) && PIPERX09DATA_delay[6]; // rv 0 + assign PIPERX09DATA_in[7] = (PIPERX09DATA[7] !== 1'bz) && PIPERX09DATA_delay[7]; // rv 0 + assign PIPERX09DATA_in[8] = (PIPERX09DATA[8] !== 1'bz) && PIPERX09DATA_delay[8]; // rv 0 + assign PIPERX09DATA_in[9] = (PIPERX09DATA[9] !== 1'bz) && PIPERX09DATA_delay[9]; // rv 0 + assign PIPERX09ELECIDLE_in = (PIPERX09ELECIDLE === 1'bz) || PIPERX09ELECIDLE_delay; // rv 1 + assign PIPERX09EQDONE_in = (PIPERX09EQDONE !== 1'bz) && PIPERX09EQDONE_delay; // rv 0 + assign PIPERX09EQLPADAPTDONE_in = (PIPERX09EQLPADAPTDONE !== 1'bz) && PIPERX09EQLPADAPTDONE_delay; // rv 0 + assign PIPERX09EQLPLFFSSEL_in = (PIPERX09EQLPLFFSSEL !== 1'bz) && PIPERX09EQLPLFFSSEL_delay; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX09EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX09EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX09EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX09EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX09EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX09EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX09EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX09EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX09EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX09EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX09EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX09EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX09EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX09EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX09EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX09EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX09EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX09EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX09PHYSTATUS_in = (PIPERX09PHYSTATUS === 1'bz) || PIPERX09PHYSTATUS_delay; // rv 1 + assign PIPERX09STARTBLOCK_in[0] = (PIPERX09STARTBLOCK[0] !== 1'bz) && PIPERX09STARTBLOCK_delay[0]; // rv 0 + assign PIPERX09STARTBLOCK_in[1] = (PIPERX09STARTBLOCK[1] !== 1'bz) && PIPERX09STARTBLOCK_delay[1]; // rv 0 + assign PIPERX09STATUS_in[0] = (PIPERX09STATUS[0] !== 1'bz) && PIPERX09STATUS_delay[0]; // rv 0 + assign PIPERX09STATUS_in[1] = (PIPERX09STATUS[1] !== 1'bz) && PIPERX09STATUS_delay[1]; // rv 0 + assign PIPERX09STATUS_in[2] = (PIPERX09STATUS[2] !== 1'bz) && PIPERX09STATUS_delay[2]; // rv 0 + assign PIPERX09SYNCHEADER_in[0] = (PIPERX09SYNCHEADER[0] !== 1'bz) && PIPERX09SYNCHEADER_delay[0]; // rv 0 + assign PIPERX09SYNCHEADER_in[1] = (PIPERX09SYNCHEADER[1] !== 1'bz) && PIPERX09SYNCHEADER_delay[1]; // rv 0 + assign PIPERX09VALID_in = (PIPERX09VALID !== 1'bz) && PIPERX09VALID_delay; // rv 0 + assign PIPERX10CHARISK_in[0] = (PIPERX10CHARISK[0] === 1'bz) || PIPERX10CHARISK_delay[0]; // rv 1 + assign PIPERX10CHARISK_in[1] = (PIPERX10CHARISK[1] === 1'bz) || PIPERX10CHARISK_delay[1]; // rv 1 + assign PIPERX10DATAVALID_in = (PIPERX10DATAVALID !== 1'bz) && PIPERX10DATAVALID_delay; // rv 0 + assign PIPERX10DATA_in[0] = (PIPERX10DATA[0] !== 1'bz) && PIPERX10DATA_delay[0]; // rv 0 + assign PIPERX10DATA_in[10] = (PIPERX10DATA[10] !== 1'bz) && PIPERX10DATA_delay[10]; // rv 0 + assign PIPERX10DATA_in[11] = (PIPERX10DATA[11] !== 1'bz) && PIPERX10DATA_delay[11]; // rv 0 + assign PIPERX10DATA_in[12] = (PIPERX10DATA[12] !== 1'bz) && PIPERX10DATA_delay[12]; // rv 0 + assign PIPERX10DATA_in[13] = (PIPERX10DATA[13] !== 1'bz) && PIPERX10DATA_delay[13]; // rv 0 + assign PIPERX10DATA_in[14] = (PIPERX10DATA[14] !== 1'bz) && PIPERX10DATA_delay[14]; // rv 0 + assign PIPERX10DATA_in[15] = (PIPERX10DATA[15] !== 1'bz) && PIPERX10DATA_delay[15]; // rv 0 + assign PIPERX10DATA_in[16] = (PIPERX10DATA[16] !== 1'bz) && PIPERX10DATA_delay[16]; // rv 0 + assign PIPERX10DATA_in[17] = (PIPERX10DATA[17] !== 1'bz) && PIPERX10DATA_delay[17]; // rv 0 + assign PIPERX10DATA_in[18] = (PIPERX10DATA[18] !== 1'bz) && PIPERX10DATA_delay[18]; // rv 0 + assign PIPERX10DATA_in[19] = (PIPERX10DATA[19] !== 1'bz) && PIPERX10DATA_delay[19]; // rv 0 + assign PIPERX10DATA_in[1] = (PIPERX10DATA[1] !== 1'bz) && PIPERX10DATA_delay[1]; // rv 0 + assign PIPERX10DATA_in[20] = (PIPERX10DATA[20] !== 1'bz) && PIPERX10DATA_delay[20]; // rv 0 + assign PIPERX10DATA_in[21] = (PIPERX10DATA[21] !== 1'bz) && PIPERX10DATA_delay[21]; // rv 0 + assign PIPERX10DATA_in[22] = (PIPERX10DATA[22] !== 1'bz) && PIPERX10DATA_delay[22]; // rv 0 + assign PIPERX10DATA_in[23] = (PIPERX10DATA[23] !== 1'bz) && PIPERX10DATA_delay[23]; // rv 0 + assign PIPERX10DATA_in[24] = (PIPERX10DATA[24] !== 1'bz) && PIPERX10DATA_delay[24]; // rv 0 + assign PIPERX10DATA_in[25] = (PIPERX10DATA[25] !== 1'bz) && PIPERX10DATA_delay[25]; // rv 0 + assign PIPERX10DATA_in[26] = (PIPERX10DATA[26] !== 1'bz) && PIPERX10DATA_delay[26]; // rv 0 + assign PIPERX10DATA_in[27] = (PIPERX10DATA[27] !== 1'bz) && PIPERX10DATA_delay[27]; // rv 0 + assign PIPERX10DATA_in[28] = (PIPERX10DATA[28] !== 1'bz) && PIPERX10DATA_delay[28]; // rv 0 + assign PIPERX10DATA_in[29] = (PIPERX10DATA[29] !== 1'bz) && PIPERX10DATA_delay[29]; // rv 0 + assign PIPERX10DATA_in[2] = (PIPERX10DATA[2] !== 1'bz) && PIPERX10DATA_delay[2]; // rv 0 + assign PIPERX10DATA_in[30] = (PIPERX10DATA[30] !== 1'bz) && PIPERX10DATA_delay[30]; // rv 0 + assign PIPERX10DATA_in[31] = (PIPERX10DATA[31] !== 1'bz) && PIPERX10DATA_delay[31]; // rv 0 + assign PIPERX10DATA_in[3] = (PIPERX10DATA[3] !== 1'bz) && PIPERX10DATA_delay[3]; // rv 0 + assign PIPERX10DATA_in[4] = (PIPERX10DATA[4] !== 1'bz) && PIPERX10DATA_delay[4]; // rv 0 + assign PIPERX10DATA_in[5] = (PIPERX10DATA[5] !== 1'bz) && PIPERX10DATA_delay[5]; // rv 0 + assign PIPERX10DATA_in[6] = (PIPERX10DATA[6] !== 1'bz) && PIPERX10DATA_delay[6]; // rv 0 + assign PIPERX10DATA_in[7] = (PIPERX10DATA[7] !== 1'bz) && PIPERX10DATA_delay[7]; // rv 0 + assign PIPERX10DATA_in[8] = (PIPERX10DATA[8] !== 1'bz) && PIPERX10DATA_delay[8]; // rv 0 + assign PIPERX10DATA_in[9] = (PIPERX10DATA[9] !== 1'bz) && PIPERX10DATA_delay[9]; // rv 0 + assign PIPERX10ELECIDLE_in = (PIPERX10ELECIDLE === 1'bz) || PIPERX10ELECIDLE_delay; // rv 1 + assign PIPERX10EQDONE_in = (PIPERX10EQDONE !== 1'bz) && PIPERX10EQDONE_delay; // rv 0 + assign PIPERX10EQLPADAPTDONE_in = (PIPERX10EQLPADAPTDONE !== 1'bz) && PIPERX10EQLPADAPTDONE_delay; // rv 0 + assign PIPERX10EQLPLFFSSEL_in = (PIPERX10EQLPLFFSSEL !== 1'bz) && PIPERX10EQLPLFFSSEL_delay; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX10EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX10EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX10EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX10EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX10EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX10EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX10EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX10EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX10EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX10EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX10EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX10EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX10EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX10EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX10EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX10EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX10EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX10EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX10PHYSTATUS_in = (PIPERX10PHYSTATUS === 1'bz) || PIPERX10PHYSTATUS_delay; // rv 1 + assign PIPERX10STARTBLOCK_in[0] = (PIPERX10STARTBLOCK[0] !== 1'bz) && PIPERX10STARTBLOCK_delay[0]; // rv 0 + assign PIPERX10STARTBLOCK_in[1] = (PIPERX10STARTBLOCK[1] !== 1'bz) && PIPERX10STARTBLOCK_delay[1]; // rv 0 + assign PIPERX10STATUS_in[0] = (PIPERX10STATUS[0] !== 1'bz) && PIPERX10STATUS_delay[0]; // rv 0 + assign PIPERX10STATUS_in[1] = (PIPERX10STATUS[1] !== 1'bz) && PIPERX10STATUS_delay[1]; // rv 0 + assign PIPERX10STATUS_in[2] = (PIPERX10STATUS[2] !== 1'bz) && PIPERX10STATUS_delay[2]; // rv 0 + assign PIPERX10SYNCHEADER_in[0] = (PIPERX10SYNCHEADER[0] !== 1'bz) && PIPERX10SYNCHEADER_delay[0]; // rv 0 + assign PIPERX10SYNCHEADER_in[1] = (PIPERX10SYNCHEADER[1] !== 1'bz) && PIPERX10SYNCHEADER_delay[1]; // rv 0 + assign PIPERX10VALID_in = (PIPERX10VALID !== 1'bz) && PIPERX10VALID_delay; // rv 0 + assign PIPERX11CHARISK_in[0] = (PIPERX11CHARISK[0] === 1'bz) || PIPERX11CHARISK_delay[0]; // rv 1 + assign PIPERX11CHARISK_in[1] = (PIPERX11CHARISK[1] === 1'bz) || PIPERX11CHARISK_delay[1]; // rv 1 + assign PIPERX11DATAVALID_in = (PIPERX11DATAVALID !== 1'bz) && PIPERX11DATAVALID_delay; // rv 0 + assign PIPERX11DATA_in[0] = (PIPERX11DATA[0] !== 1'bz) && PIPERX11DATA_delay[0]; // rv 0 + assign PIPERX11DATA_in[10] = (PIPERX11DATA[10] !== 1'bz) && PIPERX11DATA_delay[10]; // rv 0 + assign PIPERX11DATA_in[11] = (PIPERX11DATA[11] !== 1'bz) && PIPERX11DATA_delay[11]; // rv 0 + assign PIPERX11DATA_in[12] = (PIPERX11DATA[12] !== 1'bz) && PIPERX11DATA_delay[12]; // rv 0 + assign PIPERX11DATA_in[13] = (PIPERX11DATA[13] !== 1'bz) && PIPERX11DATA_delay[13]; // rv 0 + assign PIPERX11DATA_in[14] = (PIPERX11DATA[14] !== 1'bz) && PIPERX11DATA_delay[14]; // rv 0 + assign PIPERX11DATA_in[15] = (PIPERX11DATA[15] !== 1'bz) && PIPERX11DATA_delay[15]; // rv 0 + assign PIPERX11DATA_in[16] = (PIPERX11DATA[16] !== 1'bz) && PIPERX11DATA_delay[16]; // rv 0 + assign PIPERX11DATA_in[17] = (PIPERX11DATA[17] !== 1'bz) && PIPERX11DATA_delay[17]; // rv 0 + assign PIPERX11DATA_in[18] = (PIPERX11DATA[18] !== 1'bz) && PIPERX11DATA_delay[18]; // rv 0 + assign PIPERX11DATA_in[19] = (PIPERX11DATA[19] !== 1'bz) && PIPERX11DATA_delay[19]; // rv 0 + assign PIPERX11DATA_in[1] = (PIPERX11DATA[1] !== 1'bz) && PIPERX11DATA_delay[1]; // rv 0 + assign PIPERX11DATA_in[20] = (PIPERX11DATA[20] !== 1'bz) && PIPERX11DATA_delay[20]; // rv 0 + assign PIPERX11DATA_in[21] = (PIPERX11DATA[21] !== 1'bz) && PIPERX11DATA_delay[21]; // rv 0 + assign PIPERX11DATA_in[22] = (PIPERX11DATA[22] !== 1'bz) && PIPERX11DATA_delay[22]; // rv 0 + assign PIPERX11DATA_in[23] = (PIPERX11DATA[23] !== 1'bz) && PIPERX11DATA_delay[23]; // rv 0 + assign PIPERX11DATA_in[24] = (PIPERX11DATA[24] !== 1'bz) && PIPERX11DATA_delay[24]; // rv 0 + assign PIPERX11DATA_in[25] = (PIPERX11DATA[25] !== 1'bz) && PIPERX11DATA_delay[25]; // rv 0 + assign PIPERX11DATA_in[26] = (PIPERX11DATA[26] !== 1'bz) && PIPERX11DATA_delay[26]; // rv 0 + assign PIPERX11DATA_in[27] = (PIPERX11DATA[27] !== 1'bz) && PIPERX11DATA_delay[27]; // rv 0 + assign PIPERX11DATA_in[28] = (PIPERX11DATA[28] !== 1'bz) && PIPERX11DATA_delay[28]; // rv 0 + assign PIPERX11DATA_in[29] = (PIPERX11DATA[29] !== 1'bz) && PIPERX11DATA_delay[29]; // rv 0 + assign PIPERX11DATA_in[2] = (PIPERX11DATA[2] !== 1'bz) && PIPERX11DATA_delay[2]; // rv 0 + assign PIPERX11DATA_in[30] = (PIPERX11DATA[30] !== 1'bz) && PIPERX11DATA_delay[30]; // rv 0 + assign PIPERX11DATA_in[31] = (PIPERX11DATA[31] !== 1'bz) && PIPERX11DATA_delay[31]; // rv 0 + assign PIPERX11DATA_in[3] = (PIPERX11DATA[3] !== 1'bz) && PIPERX11DATA_delay[3]; // rv 0 + assign PIPERX11DATA_in[4] = (PIPERX11DATA[4] !== 1'bz) && PIPERX11DATA_delay[4]; // rv 0 + assign PIPERX11DATA_in[5] = (PIPERX11DATA[5] !== 1'bz) && PIPERX11DATA_delay[5]; // rv 0 + assign PIPERX11DATA_in[6] = (PIPERX11DATA[6] !== 1'bz) && PIPERX11DATA_delay[6]; // rv 0 + assign PIPERX11DATA_in[7] = (PIPERX11DATA[7] !== 1'bz) && PIPERX11DATA_delay[7]; // rv 0 + assign PIPERX11DATA_in[8] = (PIPERX11DATA[8] !== 1'bz) && PIPERX11DATA_delay[8]; // rv 0 + assign PIPERX11DATA_in[9] = (PIPERX11DATA[9] !== 1'bz) && PIPERX11DATA_delay[9]; // rv 0 + assign PIPERX11ELECIDLE_in = (PIPERX11ELECIDLE === 1'bz) || PIPERX11ELECIDLE_delay; // rv 1 + assign PIPERX11EQDONE_in = (PIPERX11EQDONE !== 1'bz) && PIPERX11EQDONE_delay; // rv 0 + assign PIPERX11EQLPADAPTDONE_in = (PIPERX11EQLPADAPTDONE !== 1'bz) && PIPERX11EQLPADAPTDONE_delay; // rv 0 + assign PIPERX11EQLPLFFSSEL_in = (PIPERX11EQLPLFFSSEL !== 1'bz) && PIPERX11EQLPLFFSSEL_delay; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX11EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX11EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX11EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX11EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX11EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX11EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX11EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX11EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX11EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX11EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX11EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX11EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX11EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX11EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX11EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX11EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX11EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX11EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX11PHYSTATUS_in = (PIPERX11PHYSTATUS === 1'bz) || PIPERX11PHYSTATUS_delay; // rv 1 + assign PIPERX11STARTBLOCK_in[0] = (PIPERX11STARTBLOCK[0] !== 1'bz) && PIPERX11STARTBLOCK_delay[0]; // rv 0 + assign PIPERX11STARTBLOCK_in[1] = (PIPERX11STARTBLOCK[1] !== 1'bz) && PIPERX11STARTBLOCK_delay[1]; // rv 0 + assign PIPERX11STATUS_in[0] = (PIPERX11STATUS[0] !== 1'bz) && PIPERX11STATUS_delay[0]; // rv 0 + assign PIPERX11STATUS_in[1] = (PIPERX11STATUS[1] !== 1'bz) && PIPERX11STATUS_delay[1]; // rv 0 + assign PIPERX11STATUS_in[2] = (PIPERX11STATUS[2] !== 1'bz) && PIPERX11STATUS_delay[2]; // rv 0 + assign PIPERX11SYNCHEADER_in[0] = (PIPERX11SYNCHEADER[0] !== 1'bz) && PIPERX11SYNCHEADER_delay[0]; // rv 0 + assign PIPERX11SYNCHEADER_in[1] = (PIPERX11SYNCHEADER[1] !== 1'bz) && PIPERX11SYNCHEADER_delay[1]; // rv 0 + assign PIPERX11VALID_in = (PIPERX11VALID !== 1'bz) && PIPERX11VALID_delay; // rv 0 + assign PIPERX12CHARISK_in[0] = (PIPERX12CHARISK[0] === 1'bz) || PIPERX12CHARISK_delay[0]; // rv 1 + assign PIPERX12CHARISK_in[1] = (PIPERX12CHARISK[1] === 1'bz) || PIPERX12CHARISK_delay[1]; // rv 1 + assign PIPERX12DATAVALID_in = (PIPERX12DATAVALID !== 1'bz) && PIPERX12DATAVALID_delay; // rv 0 + assign PIPERX12DATA_in[0] = (PIPERX12DATA[0] !== 1'bz) && PIPERX12DATA_delay[0]; // rv 0 + assign PIPERX12DATA_in[10] = (PIPERX12DATA[10] !== 1'bz) && PIPERX12DATA_delay[10]; // rv 0 + assign PIPERX12DATA_in[11] = (PIPERX12DATA[11] !== 1'bz) && PIPERX12DATA_delay[11]; // rv 0 + assign PIPERX12DATA_in[12] = (PIPERX12DATA[12] !== 1'bz) && PIPERX12DATA_delay[12]; // rv 0 + assign PIPERX12DATA_in[13] = (PIPERX12DATA[13] !== 1'bz) && PIPERX12DATA_delay[13]; // rv 0 + assign PIPERX12DATA_in[14] = (PIPERX12DATA[14] !== 1'bz) && PIPERX12DATA_delay[14]; // rv 0 + assign PIPERX12DATA_in[15] = (PIPERX12DATA[15] !== 1'bz) && PIPERX12DATA_delay[15]; // rv 0 + assign PIPERX12DATA_in[16] = (PIPERX12DATA[16] !== 1'bz) && PIPERX12DATA_delay[16]; // rv 0 + assign PIPERX12DATA_in[17] = (PIPERX12DATA[17] !== 1'bz) && PIPERX12DATA_delay[17]; // rv 0 + assign PIPERX12DATA_in[18] = (PIPERX12DATA[18] !== 1'bz) && PIPERX12DATA_delay[18]; // rv 0 + assign PIPERX12DATA_in[19] = (PIPERX12DATA[19] !== 1'bz) && PIPERX12DATA_delay[19]; // rv 0 + assign PIPERX12DATA_in[1] = (PIPERX12DATA[1] !== 1'bz) && PIPERX12DATA_delay[1]; // rv 0 + assign PIPERX12DATA_in[20] = (PIPERX12DATA[20] !== 1'bz) && PIPERX12DATA_delay[20]; // rv 0 + assign PIPERX12DATA_in[21] = (PIPERX12DATA[21] !== 1'bz) && PIPERX12DATA_delay[21]; // rv 0 + assign PIPERX12DATA_in[22] = (PIPERX12DATA[22] !== 1'bz) && PIPERX12DATA_delay[22]; // rv 0 + assign PIPERX12DATA_in[23] = (PIPERX12DATA[23] !== 1'bz) && PIPERX12DATA_delay[23]; // rv 0 + assign PIPERX12DATA_in[24] = (PIPERX12DATA[24] !== 1'bz) && PIPERX12DATA_delay[24]; // rv 0 + assign PIPERX12DATA_in[25] = (PIPERX12DATA[25] !== 1'bz) && PIPERX12DATA_delay[25]; // rv 0 + assign PIPERX12DATA_in[26] = (PIPERX12DATA[26] !== 1'bz) && PIPERX12DATA_delay[26]; // rv 0 + assign PIPERX12DATA_in[27] = (PIPERX12DATA[27] !== 1'bz) && PIPERX12DATA_delay[27]; // rv 0 + assign PIPERX12DATA_in[28] = (PIPERX12DATA[28] !== 1'bz) && PIPERX12DATA_delay[28]; // rv 0 + assign PIPERX12DATA_in[29] = (PIPERX12DATA[29] !== 1'bz) && PIPERX12DATA_delay[29]; // rv 0 + assign PIPERX12DATA_in[2] = (PIPERX12DATA[2] !== 1'bz) && PIPERX12DATA_delay[2]; // rv 0 + assign PIPERX12DATA_in[30] = (PIPERX12DATA[30] !== 1'bz) && PIPERX12DATA_delay[30]; // rv 0 + assign PIPERX12DATA_in[31] = (PIPERX12DATA[31] !== 1'bz) && PIPERX12DATA_delay[31]; // rv 0 + assign PIPERX12DATA_in[3] = (PIPERX12DATA[3] !== 1'bz) && PIPERX12DATA_delay[3]; // rv 0 + assign PIPERX12DATA_in[4] = (PIPERX12DATA[4] !== 1'bz) && PIPERX12DATA_delay[4]; // rv 0 + assign PIPERX12DATA_in[5] = (PIPERX12DATA[5] !== 1'bz) && PIPERX12DATA_delay[5]; // rv 0 + assign PIPERX12DATA_in[6] = (PIPERX12DATA[6] !== 1'bz) && PIPERX12DATA_delay[6]; // rv 0 + assign PIPERX12DATA_in[7] = (PIPERX12DATA[7] !== 1'bz) && PIPERX12DATA_delay[7]; // rv 0 + assign PIPERX12DATA_in[8] = (PIPERX12DATA[8] !== 1'bz) && PIPERX12DATA_delay[8]; // rv 0 + assign PIPERX12DATA_in[9] = (PIPERX12DATA[9] !== 1'bz) && PIPERX12DATA_delay[9]; // rv 0 + assign PIPERX12ELECIDLE_in = (PIPERX12ELECIDLE === 1'bz) || PIPERX12ELECIDLE_delay; // rv 1 + assign PIPERX12EQDONE_in = (PIPERX12EQDONE !== 1'bz) && PIPERX12EQDONE_delay; // rv 0 + assign PIPERX12EQLPADAPTDONE_in = (PIPERX12EQLPADAPTDONE !== 1'bz) && PIPERX12EQLPADAPTDONE_delay; // rv 0 + assign PIPERX12EQLPLFFSSEL_in = (PIPERX12EQLPLFFSSEL !== 1'bz) && PIPERX12EQLPLFFSSEL_delay; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX12EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX12EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX12EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX12EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX12EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX12EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX12EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX12EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX12EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX12EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX12EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX12EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX12EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX12EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX12EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX12EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX12EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX12EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX12PHYSTATUS_in = (PIPERX12PHYSTATUS === 1'bz) || PIPERX12PHYSTATUS_delay; // rv 1 + assign PIPERX12STARTBLOCK_in[0] = (PIPERX12STARTBLOCK[0] !== 1'bz) && PIPERX12STARTBLOCK_delay[0]; // rv 0 + assign PIPERX12STARTBLOCK_in[1] = (PIPERX12STARTBLOCK[1] !== 1'bz) && PIPERX12STARTBLOCK_delay[1]; // rv 0 + assign PIPERX12STATUS_in[0] = (PIPERX12STATUS[0] !== 1'bz) && PIPERX12STATUS_delay[0]; // rv 0 + assign PIPERX12STATUS_in[1] = (PIPERX12STATUS[1] !== 1'bz) && PIPERX12STATUS_delay[1]; // rv 0 + assign PIPERX12STATUS_in[2] = (PIPERX12STATUS[2] !== 1'bz) && PIPERX12STATUS_delay[2]; // rv 0 + assign PIPERX12SYNCHEADER_in[0] = (PIPERX12SYNCHEADER[0] !== 1'bz) && PIPERX12SYNCHEADER_delay[0]; // rv 0 + assign PIPERX12SYNCHEADER_in[1] = (PIPERX12SYNCHEADER[1] !== 1'bz) && PIPERX12SYNCHEADER_delay[1]; // rv 0 + assign PIPERX12VALID_in = (PIPERX12VALID !== 1'bz) && PIPERX12VALID_delay; // rv 0 + assign PIPERX13CHARISK_in[0] = (PIPERX13CHARISK[0] === 1'bz) || PIPERX13CHARISK_delay[0]; // rv 1 + assign PIPERX13CHARISK_in[1] = (PIPERX13CHARISK[1] === 1'bz) || PIPERX13CHARISK_delay[1]; // rv 1 + assign PIPERX13DATAVALID_in = (PIPERX13DATAVALID !== 1'bz) && PIPERX13DATAVALID_delay; // rv 0 + assign PIPERX13DATA_in[0] = (PIPERX13DATA[0] !== 1'bz) && PIPERX13DATA_delay[0]; // rv 0 + assign PIPERX13DATA_in[10] = (PIPERX13DATA[10] !== 1'bz) && PIPERX13DATA_delay[10]; // rv 0 + assign PIPERX13DATA_in[11] = (PIPERX13DATA[11] !== 1'bz) && PIPERX13DATA_delay[11]; // rv 0 + assign PIPERX13DATA_in[12] = (PIPERX13DATA[12] !== 1'bz) && PIPERX13DATA_delay[12]; // rv 0 + assign PIPERX13DATA_in[13] = (PIPERX13DATA[13] !== 1'bz) && PIPERX13DATA_delay[13]; // rv 0 + assign PIPERX13DATA_in[14] = (PIPERX13DATA[14] !== 1'bz) && PIPERX13DATA_delay[14]; // rv 0 + assign PIPERX13DATA_in[15] = (PIPERX13DATA[15] !== 1'bz) && PIPERX13DATA_delay[15]; // rv 0 + assign PIPERX13DATA_in[16] = (PIPERX13DATA[16] !== 1'bz) && PIPERX13DATA_delay[16]; // rv 0 + assign PIPERX13DATA_in[17] = (PIPERX13DATA[17] !== 1'bz) && PIPERX13DATA_delay[17]; // rv 0 + assign PIPERX13DATA_in[18] = (PIPERX13DATA[18] !== 1'bz) && PIPERX13DATA_delay[18]; // rv 0 + assign PIPERX13DATA_in[19] = (PIPERX13DATA[19] !== 1'bz) && PIPERX13DATA_delay[19]; // rv 0 + assign PIPERX13DATA_in[1] = (PIPERX13DATA[1] !== 1'bz) && PIPERX13DATA_delay[1]; // rv 0 + assign PIPERX13DATA_in[20] = (PIPERX13DATA[20] !== 1'bz) && PIPERX13DATA_delay[20]; // rv 0 + assign PIPERX13DATA_in[21] = (PIPERX13DATA[21] !== 1'bz) && PIPERX13DATA_delay[21]; // rv 0 + assign PIPERX13DATA_in[22] = (PIPERX13DATA[22] !== 1'bz) && PIPERX13DATA_delay[22]; // rv 0 + assign PIPERX13DATA_in[23] = (PIPERX13DATA[23] !== 1'bz) && PIPERX13DATA_delay[23]; // rv 0 + assign PIPERX13DATA_in[24] = (PIPERX13DATA[24] !== 1'bz) && PIPERX13DATA_delay[24]; // rv 0 + assign PIPERX13DATA_in[25] = (PIPERX13DATA[25] !== 1'bz) && PIPERX13DATA_delay[25]; // rv 0 + assign PIPERX13DATA_in[26] = (PIPERX13DATA[26] !== 1'bz) && PIPERX13DATA_delay[26]; // rv 0 + assign PIPERX13DATA_in[27] = (PIPERX13DATA[27] !== 1'bz) && PIPERX13DATA_delay[27]; // rv 0 + assign PIPERX13DATA_in[28] = (PIPERX13DATA[28] !== 1'bz) && PIPERX13DATA_delay[28]; // rv 0 + assign PIPERX13DATA_in[29] = (PIPERX13DATA[29] !== 1'bz) && PIPERX13DATA_delay[29]; // rv 0 + assign PIPERX13DATA_in[2] = (PIPERX13DATA[2] !== 1'bz) && PIPERX13DATA_delay[2]; // rv 0 + assign PIPERX13DATA_in[30] = (PIPERX13DATA[30] !== 1'bz) && PIPERX13DATA_delay[30]; // rv 0 + assign PIPERX13DATA_in[31] = (PIPERX13DATA[31] !== 1'bz) && PIPERX13DATA_delay[31]; // rv 0 + assign PIPERX13DATA_in[3] = (PIPERX13DATA[3] !== 1'bz) && PIPERX13DATA_delay[3]; // rv 0 + assign PIPERX13DATA_in[4] = (PIPERX13DATA[4] !== 1'bz) && PIPERX13DATA_delay[4]; // rv 0 + assign PIPERX13DATA_in[5] = (PIPERX13DATA[5] !== 1'bz) && PIPERX13DATA_delay[5]; // rv 0 + assign PIPERX13DATA_in[6] = (PIPERX13DATA[6] !== 1'bz) && PIPERX13DATA_delay[6]; // rv 0 + assign PIPERX13DATA_in[7] = (PIPERX13DATA[7] !== 1'bz) && PIPERX13DATA_delay[7]; // rv 0 + assign PIPERX13DATA_in[8] = (PIPERX13DATA[8] !== 1'bz) && PIPERX13DATA_delay[8]; // rv 0 + assign PIPERX13DATA_in[9] = (PIPERX13DATA[9] !== 1'bz) && PIPERX13DATA_delay[9]; // rv 0 + assign PIPERX13ELECIDLE_in = (PIPERX13ELECIDLE === 1'bz) || PIPERX13ELECIDLE_delay; // rv 1 + assign PIPERX13EQDONE_in = (PIPERX13EQDONE !== 1'bz) && PIPERX13EQDONE_delay; // rv 0 + assign PIPERX13EQLPADAPTDONE_in = (PIPERX13EQLPADAPTDONE !== 1'bz) && PIPERX13EQLPADAPTDONE_delay; // rv 0 + assign PIPERX13EQLPLFFSSEL_in = (PIPERX13EQLPLFFSSEL !== 1'bz) && PIPERX13EQLPLFFSSEL_delay; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX13EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX13EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX13EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX13EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX13EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX13EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX13EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX13EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX13EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX13EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX13EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX13EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX13EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX13EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX13EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX13EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX13EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX13EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX13PHYSTATUS_in = (PIPERX13PHYSTATUS === 1'bz) || PIPERX13PHYSTATUS_delay; // rv 1 + assign PIPERX13STARTBLOCK_in[0] = (PIPERX13STARTBLOCK[0] !== 1'bz) && PIPERX13STARTBLOCK_delay[0]; // rv 0 + assign PIPERX13STARTBLOCK_in[1] = (PIPERX13STARTBLOCK[1] !== 1'bz) && PIPERX13STARTBLOCK_delay[1]; // rv 0 + assign PIPERX13STATUS_in[0] = (PIPERX13STATUS[0] !== 1'bz) && PIPERX13STATUS_delay[0]; // rv 0 + assign PIPERX13STATUS_in[1] = (PIPERX13STATUS[1] !== 1'bz) && PIPERX13STATUS_delay[1]; // rv 0 + assign PIPERX13STATUS_in[2] = (PIPERX13STATUS[2] !== 1'bz) && PIPERX13STATUS_delay[2]; // rv 0 + assign PIPERX13SYNCHEADER_in[0] = (PIPERX13SYNCHEADER[0] !== 1'bz) && PIPERX13SYNCHEADER_delay[0]; // rv 0 + assign PIPERX13SYNCHEADER_in[1] = (PIPERX13SYNCHEADER[1] !== 1'bz) && PIPERX13SYNCHEADER_delay[1]; // rv 0 + assign PIPERX13VALID_in = (PIPERX13VALID !== 1'bz) && PIPERX13VALID_delay; // rv 0 + assign PIPERX14CHARISK_in[0] = (PIPERX14CHARISK[0] === 1'bz) || PIPERX14CHARISK_delay[0]; // rv 1 + assign PIPERX14CHARISK_in[1] = (PIPERX14CHARISK[1] === 1'bz) || PIPERX14CHARISK_delay[1]; // rv 1 + assign PIPERX14DATAVALID_in = (PIPERX14DATAVALID !== 1'bz) && PIPERX14DATAVALID_delay; // rv 0 + assign PIPERX14DATA_in[0] = (PIPERX14DATA[0] !== 1'bz) && PIPERX14DATA_delay[0]; // rv 0 + assign PIPERX14DATA_in[10] = (PIPERX14DATA[10] !== 1'bz) && PIPERX14DATA_delay[10]; // rv 0 + assign PIPERX14DATA_in[11] = (PIPERX14DATA[11] !== 1'bz) && PIPERX14DATA_delay[11]; // rv 0 + assign PIPERX14DATA_in[12] = (PIPERX14DATA[12] !== 1'bz) && PIPERX14DATA_delay[12]; // rv 0 + assign PIPERX14DATA_in[13] = (PIPERX14DATA[13] !== 1'bz) && PIPERX14DATA_delay[13]; // rv 0 + assign PIPERX14DATA_in[14] = (PIPERX14DATA[14] !== 1'bz) && PIPERX14DATA_delay[14]; // rv 0 + assign PIPERX14DATA_in[15] = (PIPERX14DATA[15] !== 1'bz) && PIPERX14DATA_delay[15]; // rv 0 + assign PIPERX14DATA_in[16] = (PIPERX14DATA[16] !== 1'bz) && PIPERX14DATA_delay[16]; // rv 0 + assign PIPERX14DATA_in[17] = (PIPERX14DATA[17] !== 1'bz) && PIPERX14DATA_delay[17]; // rv 0 + assign PIPERX14DATA_in[18] = (PIPERX14DATA[18] !== 1'bz) && PIPERX14DATA_delay[18]; // rv 0 + assign PIPERX14DATA_in[19] = (PIPERX14DATA[19] !== 1'bz) && PIPERX14DATA_delay[19]; // rv 0 + assign PIPERX14DATA_in[1] = (PIPERX14DATA[1] !== 1'bz) && PIPERX14DATA_delay[1]; // rv 0 + assign PIPERX14DATA_in[20] = (PIPERX14DATA[20] !== 1'bz) && PIPERX14DATA_delay[20]; // rv 0 + assign PIPERX14DATA_in[21] = (PIPERX14DATA[21] !== 1'bz) && PIPERX14DATA_delay[21]; // rv 0 + assign PIPERX14DATA_in[22] = (PIPERX14DATA[22] !== 1'bz) && PIPERX14DATA_delay[22]; // rv 0 + assign PIPERX14DATA_in[23] = (PIPERX14DATA[23] !== 1'bz) && PIPERX14DATA_delay[23]; // rv 0 + assign PIPERX14DATA_in[24] = (PIPERX14DATA[24] !== 1'bz) && PIPERX14DATA_delay[24]; // rv 0 + assign PIPERX14DATA_in[25] = (PIPERX14DATA[25] !== 1'bz) && PIPERX14DATA_delay[25]; // rv 0 + assign PIPERX14DATA_in[26] = (PIPERX14DATA[26] !== 1'bz) && PIPERX14DATA_delay[26]; // rv 0 + assign PIPERX14DATA_in[27] = (PIPERX14DATA[27] !== 1'bz) && PIPERX14DATA_delay[27]; // rv 0 + assign PIPERX14DATA_in[28] = (PIPERX14DATA[28] !== 1'bz) && PIPERX14DATA_delay[28]; // rv 0 + assign PIPERX14DATA_in[29] = (PIPERX14DATA[29] !== 1'bz) && PIPERX14DATA_delay[29]; // rv 0 + assign PIPERX14DATA_in[2] = (PIPERX14DATA[2] !== 1'bz) && PIPERX14DATA_delay[2]; // rv 0 + assign PIPERX14DATA_in[30] = (PIPERX14DATA[30] !== 1'bz) && PIPERX14DATA_delay[30]; // rv 0 + assign PIPERX14DATA_in[31] = (PIPERX14DATA[31] !== 1'bz) && PIPERX14DATA_delay[31]; // rv 0 + assign PIPERX14DATA_in[3] = (PIPERX14DATA[3] !== 1'bz) && PIPERX14DATA_delay[3]; // rv 0 + assign PIPERX14DATA_in[4] = (PIPERX14DATA[4] !== 1'bz) && PIPERX14DATA_delay[4]; // rv 0 + assign PIPERX14DATA_in[5] = (PIPERX14DATA[5] !== 1'bz) && PIPERX14DATA_delay[5]; // rv 0 + assign PIPERX14DATA_in[6] = (PIPERX14DATA[6] !== 1'bz) && PIPERX14DATA_delay[6]; // rv 0 + assign PIPERX14DATA_in[7] = (PIPERX14DATA[7] !== 1'bz) && PIPERX14DATA_delay[7]; // rv 0 + assign PIPERX14DATA_in[8] = (PIPERX14DATA[8] !== 1'bz) && PIPERX14DATA_delay[8]; // rv 0 + assign PIPERX14DATA_in[9] = (PIPERX14DATA[9] !== 1'bz) && PIPERX14DATA_delay[9]; // rv 0 + assign PIPERX14ELECIDLE_in = (PIPERX14ELECIDLE === 1'bz) || PIPERX14ELECIDLE_delay; // rv 1 + assign PIPERX14EQDONE_in = (PIPERX14EQDONE !== 1'bz) && PIPERX14EQDONE_delay; // rv 0 + assign PIPERX14EQLPADAPTDONE_in = (PIPERX14EQLPADAPTDONE !== 1'bz) && PIPERX14EQLPADAPTDONE_delay; // rv 0 + assign PIPERX14EQLPLFFSSEL_in = (PIPERX14EQLPLFFSSEL !== 1'bz) && PIPERX14EQLPLFFSSEL_delay; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX14EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX14EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX14EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX14EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX14EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX14EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX14EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX14EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX14EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX14EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX14EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX14EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX14EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX14EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX14EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX14EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX14EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX14EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX14PHYSTATUS_in = (PIPERX14PHYSTATUS === 1'bz) || PIPERX14PHYSTATUS_delay; // rv 1 + assign PIPERX14STARTBLOCK_in[0] = (PIPERX14STARTBLOCK[0] !== 1'bz) && PIPERX14STARTBLOCK_delay[0]; // rv 0 + assign PIPERX14STARTBLOCK_in[1] = (PIPERX14STARTBLOCK[1] !== 1'bz) && PIPERX14STARTBLOCK_delay[1]; // rv 0 + assign PIPERX14STATUS_in[0] = (PIPERX14STATUS[0] !== 1'bz) && PIPERX14STATUS_delay[0]; // rv 0 + assign PIPERX14STATUS_in[1] = (PIPERX14STATUS[1] !== 1'bz) && PIPERX14STATUS_delay[1]; // rv 0 + assign PIPERX14STATUS_in[2] = (PIPERX14STATUS[2] !== 1'bz) && PIPERX14STATUS_delay[2]; // rv 0 + assign PIPERX14SYNCHEADER_in[0] = (PIPERX14SYNCHEADER[0] !== 1'bz) && PIPERX14SYNCHEADER_delay[0]; // rv 0 + assign PIPERX14SYNCHEADER_in[1] = (PIPERX14SYNCHEADER[1] !== 1'bz) && PIPERX14SYNCHEADER_delay[1]; // rv 0 + assign PIPERX14VALID_in = (PIPERX14VALID !== 1'bz) && PIPERX14VALID_delay; // rv 0 + assign PIPERX15CHARISK_in[0] = (PIPERX15CHARISK[0] === 1'bz) || PIPERX15CHARISK_delay[0]; // rv 1 + assign PIPERX15CHARISK_in[1] = (PIPERX15CHARISK[1] === 1'bz) || PIPERX15CHARISK_delay[1]; // rv 1 + assign PIPERX15DATAVALID_in = (PIPERX15DATAVALID !== 1'bz) && PIPERX15DATAVALID_delay; // rv 0 + assign PIPERX15DATA_in[0] = (PIPERX15DATA[0] !== 1'bz) && PIPERX15DATA_delay[0]; // rv 0 + assign PIPERX15DATA_in[10] = (PIPERX15DATA[10] !== 1'bz) && PIPERX15DATA_delay[10]; // rv 0 + assign PIPERX15DATA_in[11] = (PIPERX15DATA[11] !== 1'bz) && PIPERX15DATA_delay[11]; // rv 0 + assign PIPERX15DATA_in[12] = (PIPERX15DATA[12] !== 1'bz) && PIPERX15DATA_delay[12]; // rv 0 + assign PIPERX15DATA_in[13] = (PIPERX15DATA[13] !== 1'bz) && PIPERX15DATA_delay[13]; // rv 0 + assign PIPERX15DATA_in[14] = (PIPERX15DATA[14] !== 1'bz) && PIPERX15DATA_delay[14]; // rv 0 + assign PIPERX15DATA_in[15] = (PIPERX15DATA[15] !== 1'bz) && PIPERX15DATA_delay[15]; // rv 0 + assign PIPERX15DATA_in[16] = (PIPERX15DATA[16] !== 1'bz) && PIPERX15DATA_delay[16]; // rv 0 + assign PIPERX15DATA_in[17] = (PIPERX15DATA[17] !== 1'bz) && PIPERX15DATA_delay[17]; // rv 0 + assign PIPERX15DATA_in[18] = (PIPERX15DATA[18] !== 1'bz) && PIPERX15DATA_delay[18]; // rv 0 + assign PIPERX15DATA_in[19] = (PIPERX15DATA[19] !== 1'bz) && PIPERX15DATA_delay[19]; // rv 0 + assign PIPERX15DATA_in[1] = (PIPERX15DATA[1] !== 1'bz) && PIPERX15DATA_delay[1]; // rv 0 + assign PIPERX15DATA_in[20] = (PIPERX15DATA[20] !== 1'bz) && PIPERX15DATA_delay[20]; // rv 0 + assign PIPERX15DATA_in[21] = (PIPERX15DATA[21] !== 1'bz) && PIPERX15DATA_delay[21]; // rv 0 + assign PIPERX15DATA_in[22] = (PIPERX15DATA[22] !== 1'bz) && PIPERX15DATA_delay[22]; // rv 0 + assign PIPERX15DATA_in[23] = (PIPERX15DATA[23] !== 1'bz) && PIPERX15DATA_delay[23]; // rv 0 + assign PIPERX15DATA_in[24] = (PIPERX15DATA[24] !== 1'bz) && PIPERX15DATA_delay[24]; // rv 0 + assign PIPERX15DATA_in[25] = (PIPERX15DATA[25] !== 1'bz) && PIPERX15DATA_delay[25]; // rv 0 + assign PIPERX15DATA_in[26] = (PIPERX15DATA[26] !== 1'bz) && PIPERX15DATA_delay[26]; // rv 0 + assign PIPERX15DATA_in[27] = (PIPERX15DATA[27] !== 1'bz) && PIPERX15DATA_delay[27]; // rv 0 + assign PIPERX15DATA_in[28] = (PIPERX15DATA[28] !== 1'bz) && PIPERX15DATA_delay[28]; // rv 0 + assign PIPERX15DATA_in[29] = (PIPERX15DATA[29] !== 1'bz) && PIPERX15DATA_delay[29]; // rv 0 + assign PIPERX15DATA_in[2] = (PIPERX15DATA[2] !== 1'bz) && PIPERX15DATA_delay[2]; // rv 0 + assign PIPERX15DATA_in[30] = (PIPERX15DATA[30] !== 1'bz) && PIPERX15DATA_delay[30]; // rv 0 + assign PIPERX15DATA_in[31] = (PIPERX15DATA[31] !== 1'bz) && PIPERX15DATA_delay[31]; // rv 0 + assign PIPERX15DATA_in[3] = (PIPERX15DATA[3] !== 1'bz) && PIPERX15DATA_delay[3]; // rv 0 + assign PIPERX15DATA_in[4] = (PIPERX15DATA[4] !== 1'bz) && PIPERX15DATA_delay[4]; // rv 0 + assign PIPERX15DATA_in[5] = (PIPERX15DATA[5] !== 1'bz) && PIPERX15DATA_delay[5]; // rv 0 + assign PIPERX15DATA_in[6] = (PIPERX15DATA[6] !== 1'bz) && PIPERX15DATA_delay[6]; // rv 0 + assign PIPERX15DATA_in[7] = (PIPERX15DATA[7] !== 1'bz) && PIPERX15DATA_delay[7]; // rv 0 + assign PIPERX15DATA_in[8] = (PIPERX15DATA[8] !== 1'bz) && PIPERX15DATA_delay[8]; // rv 0 + assign PIPERX15DATA_in[9] = (PIPERX15DATA[9] !== 1'bz) && PIPERX15DATA_delay[9]; // rv 0 + assign PIPERX15ELECIDLE_in = (PIPERX15ELECIDLE === 1'bz) || PIPERX15ELECIDLE_delay; // rv 1 + assign PIPERX15EQDONE_in = (PIPERX15EQDONE !== 1'bz) && PIPERX15EQDONE_delay; // rv 0 + assign PIPERX15EQLPADAPTDONE_in = (PIPERX15EQLPADAPTDONE !== 1'bz) && PIPERX15EQLPADAPTDONE_delay; // rv 0 + assign PIPERX15EQLPLFFSSEL_in = (PIPERX15EQLPLFFSSEL !== 1'bz) && PIPERX15EQLPLFFSSEL_delay; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX15EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX15EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX15EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX15EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX15EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX15EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX15EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX15EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX15EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX15EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX15EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX15EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX15EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX15EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX15EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX15EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX15EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX15EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX15PHYSTATUS_in = (PIPERX15PHYSTATUS === 1'bz) || PIPERX15PHYSTATUS_delay; // rv 1 + assign PIPERX15STARTBLOCK_in[0] = (PIPERX15STARTBLOCK[0] !== 1'bz) && PIPERX15STARTBLOCK_delay[0]; // rv 0 + assign PIPERX15STARTBLOCK_in[1] = (PIPERX15STARTBLOCK[1] !== 1'bz) && PIPERX15STARTBLOCK_delay[1]; // rv 0 + assign PIPERX15STATUS_in[0] = (PIPERX15STATUS[0] !== 1'bz) && PIPERX15STATUS_delay[0]; // rv 0 + assign PIPERX15STATUS_in[1] = (PIPERX15STATUS[1] !== 1'bz) && PIPERX15STATUS_delay[1]; // rv 0 + assign PIPERX15STATUS_in[2] = (PIPERX15STATUS[2] !== 1'bz) && PIPERX15STATUS_delay[2]; // rv 0 + assign PIPERX15SYNCHEADER_in[0] = (PIPERX15SYNCHEADER[0] !== 1'bz) && PIPERX15SYNCHEADER_delay[0]; // rv 0 + assign PIPERX15SYNCHEADER_in[1] = (PIPERX15SYNCHEADER[1] !== 1'bz) && PIPERX15SYNCHEADER_delay[1]; // rv 0 + assign PIPERX15VALID_in = (PIPERX15VALID !== 1'bz) && PIPERX15VALID_delay; // rv 0 + assign PIPETX00EQCOEFF_in[0] = (PIPETX00EQCOEFF[0] !== 1'bz) && PIPETX00EQCOEFF_delay[0]; // rv 0 + assign PIPETX00EQCOEFF_in[10] = (PIPETX00EQCOEFF[10] !== 1'bz) && PIPETX00EQCOEFF_delay[10]; // rv 0 + assign PIPETX00EQCOEFF_in[11] = (PIPETX00EQCOEFF[11] !== 1'bz) && PIPETX00EQCOEFF_delay[11]; // rv 0 + assign PIPETX00EQCOEFF_in[12] = (PIPETX00EQCOEFF[12] !== 1'bz) && PIPETX00EQCOEFF_delay[12]; // rv 0 + assign PIPETX00EQCOEFF_in[13] = (PIPETX00EQCOEFF[13] !== 1'bz) && PIPETX00EQCOEFF_delay[13]; // rv 0 + assign PIPETX00EQCOEFF_in[14] = (PIPETX00EQCOEFF[14] !== 1'bz) && PIPETX00EQCOEFF_delay[14]; // rv 0 + assign PIPETX00EQCOEFF_in[15] = (PIPETX00EQCOEFF[15] !== 1'bz) && PIPETX00EQCOEFF_delay[15]; // rv 0 + assign PIPETX00EQCOEFF_in[16] = (PIPETX00EQCOEFF[16] !== 1'bz) && PIPETX00EQCOEFF_delay[16]; // rv 0 + assign PIPETX00EQCOEFF_in[17] = (PIPETX00EQCOEFF[17] !== 1'bz) && PIPETX00EQCOEFF_delay[17]; // rv 0 + assign PIPETX00EQCOEFF_in[1] = (PIPETX00EQCOEFF[1] !== 1'bz) && PIPETX00EQCOEFF_delay[1]; // rv 0 + assign PIPETX00EQCOEFF_in[2] = (PIPETX00EQCOEFF[2] !== 1'bz) && PIPETX00EQCOEFF_delay[2]; // rv 0 + assign PIPETX00EQCOEFF_in[3] = (PIPETX00EQCOEFF[3] !== 1'bz) && PIPETX00EQCOEFF_delay[3]; // rv 0 + assign PIPETX00EQCOEFF_in[4] = (PIPETX00EQCOEFF[4] !== 1'bz) && PIPETX00EQCOEFF_delay[4]; // rv 0 + assign PIPETX00EQCOEFF_in[5] = (PIPETX00EQCOEFF[5] !== 1'bz) && PIPETX00EQCOEFF_delay[5]; // rv 0 + assign PIPETX00EQCOEFF_in[6] = (PIPETX00EQCOEFF[6] !== 1'bz) && PIPETX00EQCOEFF_delay[6]; // rv 0 + assign PIPETX00EQCOEFF_in[7] = (PIPETX00EQCOEFF[7] !== 1'bz) && PIPETX00EQCOEFF_delay[7]; // rv 0 + assign PIPETX00EQCOEFF_in[8] = (PIPETX00EQCOEFF[8] !== 1'bz) && PIPETX00EQCOEFF_delay[8]; // rv 0 + assign PIPETX00EQCOEFF_in[9] = (PIPETX00EQCOEFF[9] !== 1'bz) && PIPETX00EQCOEFF_delay[9]; // rv 0 + assign PIPETX00EQDONE_in = (PIPETX00EQDONE !== 1'bz) && PIPETX00EQDONE_delay; // rv 0 + assign PIPETX01EQCOEFF_in[0] = (PIPETX01EQCOEFF[0] !== 1'bz) && PIPETX01EQCOEFF_delay[0]; // rv 0 + assign PIPETX01EQCOEFF_in[10] = (PIPETX01EQCOEFF[10] !== 1'bz) && PIPETX01EQCOEFF_delay[10]; // rv 0 + assign PIPETX01EQCOEFF_in[11] = (PIPETX01EQCOEFF[11] !== 1'bz) && PIPETX01EQCOEFF_delay[11]; // rv 0 + assign PIPETX01EQCOEFF_in[12] = (PIPETX01EQCOEFF[12] !== 1'bz) && PIPETX01EQCOEFF_delay[12]; // rv 0 + assign PIPETX01EQCOEFF_in[13] = (PIPETX01EQCOEFF[13] !== 1'bz) && PIPETX01EQCOEFF_delay[13]; // rv 0 + assign PIPETX01EQCOEFF_in[14] = (PIPETX01EQCOEFF[14] !== 1'bz) && PIPETX01EQCOEFF_delay[14]; // rv 0 + assign PIPETX01EQCOEFF_in[15] = (PIPETX01EQCOEFF[15] !== 1'bz) && PIPETX01EQCOEFF_delay[15]; // rv 0 + assign PIPETX01EQCOEFF_in[16] = (PIPETX01EQCOEFF[16] !== 1'bz) && PIPETX01EQCOEFF_delay[16]; // rv 0 + assign PIPETX01EQCOEFF_in[17] = (PIPETX01EQCOEFF[17] !== 1'bz) && PIPETX01EQCOEFF_delay[17]; // rv 0 + assign PIPETX01EQCOEFF_in[1] = (PIPETX01EQCOEFF[1] !== 1'bz) && PIPETX01EQCOEFF_delay[1]; // rv 0 + assign PIPETX01EQCOEFF_in[2] = (PIPETX01EQCOEFF[2] !== 1'bz) && PIPETX01EQCOEFF_delay[2]; // rv 0 + assign PIPETX01EQCOEFF_in[3] = (PIPETX01EQCOEFF[3] !== 1'bz) && PIPETX01EQCOEFF_delay[3]; // rv 0 + assign PIPETX01EQCOEFF_in[4] = (PIPETX01EQCOEFF[4] !== 1'bz) && PIPETX01EQCOEFF_delay[4]; // rv 0 + assign PIPETX01EQCOEFF_in[5] = (PIPETX01EQCOEFF[5] !== 1'bz) && PIPETX01EQCOEFF_delay[5]; // rv 0 + assign PIPETX01EQCOEFF_in[6] = (PIPETX01EQCOEFF[6] !== 1'bz) && PIPETX01EQCOEFF_delay[6]; // rv 0 + assign PIPETX01EQCOEFF_in[7] = (PIPETX01EQCOEFF[7] !== 1'bz) && PIPETX01EQCOEFF_delay[7]; // rv 0 + assign PIPETX01EQCOEFF_in[8] = (PIPETX01EQCOEFF[8] !== 1'bz) && PIPETX01EQCOEFF_delay[8]; // rv 0 + assign PIPETX01EQCOEFF_in[9] = (PIPETX01EQCOEFF[9] !== 1'bz) && PIPETX01EQCOEFF_delay[9]; // rv 0 + assign PIPETX01EQDONE_in = (PIPETX01EQDONE !== 1'bz) && PIPETX01EQDONE_delay; // rv 0 + assign PIPETX02EQCOEFF_in[0] = (PIPETX02EQCOEFF[0] !== 1'bz) && PIPETX02EQCOEFF_delay[0]; // rv 0 + assign PIPETX02EQCOEFF_in[10] = (PIPETX02EQCOEFF[10] !== 1'bz) && PIPETX02EQCOEFF_delay[10]; // rv 0 + assign PIPETX02EQCOEFF_in[11] = (PIPETX02EQCOEFF[11] !== 1'bz) && PIPETX02EQCOEFF_delay[11]; // rv 0 + assign PIPETX02EQCOEFF_in[12] = (PIPETX02EQCOEFF[12] !== 1'bz) && PIPETX02EQCOEFF_delay[12]; // rv 0 + assign PIPETX02EQCOEFF_in[13] = (PIPETX02EQCOEFF[13] !== 1'bz) && PIPETX02EQCOEFF_delay[13]; // rv 0 + assign PIPETX02EQCOEFF_in[14] = (PIPETX02EQCOEFF[14] !== 1'bz) && PIPETX02EQCOEFF_delay[14]; // rv 0 + assign PIPETX02EQCOEFF_in[15] = (PIPETX02EQCOEFF[15] !== 1'bz) && PIPETX02EQCOEFF_delay[15]; // rv 0 + assign PIPETX02EQCOEFF_in[16] = (PIPETX02EQCOEFF[16] !== 1'bz) && PIPETX02EQCOEFF_delay[16]; // rv 0 + assign PIPETX02EQCOEFF_in[17] = (PIPETX02EQCOEFF[17] !== 1'bz) && PIPETX02EQCOEFF_delay[17]; // rv 0 + assign PIPETX02EQCOEFF_in[1] = (PIPETX02EQCOEFF[1] !== 1'bz) && PIPETX02EQCOEFF_delay[1]; // rv 0 + assign PIPETX02EQCOEFF_in[2] = (PIPETX02EQCOEFF[2] !== 1'bz) && PIPETX02EQCOEFF_delay[2]; // rv 0 + assign PIPETX02EQCOEFF_in[3] = (PIPETX02EQCOEFF[3] !== 1'bz) && PIPETX02EQCOEFF_delay[3]; // rv 0 + assign PIPETX02EQCOEFF_in[4] = (PIPETX02EQCOEFF[4] !== 1'bz) && PIPETX02EQCOEFF_delay[4]; // rv 0 + assign PIPETX02EQCOEFF_in[5] = (PIPETX02EQCOEFF[5] !== 1'bz) && PIPETX02EQCOEFF_delay[5]; // rv 0 + assign PIPETX02EQCOEFF_in[6] = (PIPETX02EQCOEFF[6] !== 1'bz) && PIPETX02EQCOEFF_delay[6]; // rv 0 + assign PIPETX02EQCOEFF_in[7] = (PIPETX02EQCOEFF[7] !== 1'bz) && PIPETX02EQCOEFF_delay[7]; // rv 0 + assign PIPETX02EQCOEFF_in[8] = (PIPETX02EQCOEFF[8] !== 1'bz) && PIPETX02EQCOEFF_delay[8]; // rv 0 + assign PIPETX02EQCOEFF_in[9] = (PIPETX02EQCOEFF[9] !== 1'bz) && PIPETX02EQCOEFF_delay[9]; // rv 0 + assign PIPETX02EQDONE_in = (PIPETX02EQDONE !== 1'bz) && PIPETX02EQDONE_delay; // rv 0 + assign PIPETX03EQCOEFF_in[0] = (PIPETX03EQCOEFF[0] !== 1'bz) && PIPETX03EQCOEFF_delay[0]; // rv 0 + assign PIPETX03EQCOEFF_in[10] = (PIPETX03EQCOEFF[10] !== 1'bz) && PIPETX03EQCOEFF_delay[10]; // rv 0 + assign PIPETX03EQCOEFF_in[11] = (PIPETX03EQCOEFF[11] !== 1'bz) && PIPETX03EQCOEFF_delay[11]; // rv 0 + assign PIPETX03EQCOEFF_in[12] = (PIPETX03EQCOEFF[12] !== 1'bz) && PIPETX03EQCOEFF_delay[12]; // rv 0 + assign PIPETX03EQCOEFF_in[13] = (PIPETX03EQCOEFF[13] !== 1'bz) && PIPETX03EQCOEFF_delay[13]; // rv 0 + assign PIPETX03EQCOEFF_in[14] = (PIPETX03EQCOEFF[14] !== 1'bz) && PIPETX03EQCOEFF_delay[14]; // rv 0 + assign PIPETX03EQCOEFF_in[15] = (PIPETX03EQCOEFF[15] !== 1'bz) && PIPETX03EQCOEFF_delay[15]; // rv 0 + assign PIPETX03EQCOEFF_in[16] = (PIPETX03EQCOEFF[16] !== 1'bz) && PIPETX03EQCOEFF_delay[16]; // rv 0 + assign PIPETX03EQCOEFF_in[17] = (PIPETX03EQCOEFF[17] !== 1'bz) && PIPETX03EQCOEFF_delay[17]; // rv 0 + assign PIPETX03EQCOEFF_in[1] = (PIPETX03EQCOEFF[1] !== 1'bz) && PIPETX03EQCOEFF_delay[1]; // rv 0 + assign PIPETX03EQCOEFF_in[2] = (PIPETX03EQCOEFF[2] !== 1'bz) && PIPETX03EQCOEFF_delay[2]; // rv 0 + assign PIPETX03EQCOEFF_in[3] = (PIPETX03EQCOEFF[3] !== 1'bz) && PIPETX03EQCOEFF_delay[3]; // rv 0 + assign PIPETX03EQCOEFF_in[4] = (PIPETX03EQCOEFF[4] !== 1'bz) && PIPETX03EQCOEFF_delay[4]; // rv 0 + assign PIPETX03EQCOEFF_in[5] = (PIPETX03EQCOEFF[5] !== 1'bz) && PIPETX03EQCOEFF_delay[5]; // rv 0 + assign PIPETX03EQCOEFF_in[6] = (PIPETX03EQCOEFF[6] !== 1'bz) && PIPETX03EQCOEFF_delay[6]; // rv 0 + assign PIPETX03EQCOEFF_in[7] = (PIPETX03EQCOEFF[7] !== 1'bz) && PIPETX03EQCOEFF_delay[7]; // rv 0 + assign PIPETX03EQCOEFF_in[8] = (PIPETX03EQCOEFF[8] !== 1'bz) && PIPETX03EQCOEFF_delay[8]; // rv 0 + assign PIPETX03EQCOEFF_in[9] = (PIPETX03EQCOEFF[9] !== 1'bz) && PIPETX03EQCOEFF_delay[9]; // rv 0 + assign PIPETX03EQDONE_in = (PIPETX03EQDONE !== 1'bz) && PIPETX03EQDONE_delay; // rv 0 + assign PIPETX04EQCOEFF_in[0] = (PIPETX04EQCOEFF[0] !== 1'bz) && PIPETX04EQCOEFF_delay[0]; // rv 0 + assign PIPETX04EQCOEFF_in[10] = (PIPETX04EQCOEFF[10] !== 1'bz) && PIPETX04EQCOEFF_delay[10]; // rv 0 + assign PIPETX04EQCOEFF_in[11] = (PIPETX04EQCOEFF[11] !== 1'bz) && PIPETX04EQCOEFF_delay[11]; // rv 0 + assign PIPETX04EQCOEFF_in[12] = (PIPETX04EQCOEFF[12] !== 1'bz) && PIPETX04EQCOEFF_delay[12]; // rv 0 + assign PIPETX04EQCOEFF_in[13] = (PIPETX04EQCOEFF[13] !== 1'bz) && PIPETX04EQCOEFF_delay[13]; // rv 0 + assign PIPETX04EQCOEFF_in[14] = (PIPETX04EQCOEFF[14] !== 1'bz) && PIPETX04EQCOEFF_delay[14]; // rv 0 + assign PIPETX04EQCOEFF_in[15] = (PIPETX04EQCOEFF[15] !== 1'bz) && PIPETX04EQCOEFF_delay[15]; // rv 0 + assign PIPETX04EQCOEFF_in[16] = (PIPETX04EQCOEFF[16] !== 1'bz) && PIPETX04EQCOEFF_delay[16]; // rv 0 + assign PIPETX04EQCOEFF_in[17] = (PIPETX04EQCOEFF[17] !== 1'bz) && PIPETX04EQCOEFF_delay[17]; // rv 0 + assign PIPETX04EQCOEFF_in[1] = (PIPETX04EQCOEFF[1] !== 1'bz) && PIPETX04EQCOEFF_delay[1]; // rv 0 + assign PIPETX04EQCOEFF_in[2] = (PIPETX04EQCOEFF[2] !== 1'bz) && PIPETX04EQCOEFF_delay[2]; // rv 0 + assign PIPETX04EQCOEFF_in[3] = (PIPETX04EQCOEFF[3] !== 1'bz) && PIPETX04EQCOEFF_delay[3]; // rv 0 + assign PIPETX04EQCOEFF_in[4] = (PIPETX04EQCOEFF[4] !== 1'bz) && PIPETX04EQCOEFF_delay[4]; // rv 0 + assign PIPETX04EQCOEFF_in[5] = (PIPETX04EQCOEFF[5] !== 1'bz) && PIPETX04EQCOEFF_delay[5]; // rv 0 + assign PIPETX04EQCOEFF_in[6] = (PIPETX04EQCOEFF[6] !== 1'bz) && PIPETX04EQCOEFF_delay[6]; // rv 0 + assign PIPETX04EQCOEFF_in[7] = (PIPETX04EQCOEFF[7] !== 1'bz) && PIPETX04EQCOEFF_delay[7]; // rv 0 + assign PIPETX04EQCOEFF_in[8] = (PIPETX04EQCOEFF[8] !== 1'bz) && PIPETX04EQCOEFF_delay[8]; // rv 0 + assign PIPETX04EQCOEFF_in[9] = (PIPETX04EQCOEFF[9] !== 1'bz) && PIPETX04EQCOEFF_delay[9]; // rv 0 + assign PIPETX04EQDONE_in = (PIPETX04EQDONE !== 1'bz) && PIPETX04EQDONE_delay; // rv 0 + assign PIPETX05EQCOEFF_in[0] = (PIPETX05EQCOEFF[0] !== 1'bz) && PIPETX05EQCOEFF_delay[0]; // rv 0 + assign PIPETX05EQCOEFF_in[10] = (PIPETX05EQCOEFF[10] !== 1'bz) && PIPETX05EQCOEFF_delay[10]; // rv 0 + assign PIPETX05EQCOEFF_in[11] = (PIPETX05EQCOEFF[11] !== 1'bz) && PIPETX05EQCOEFF_delay[11]; // rv 0 + assign PIPETX05EQCOEFF_in[12] = (PIPETX05EQCOEFF[12] !== 1'bz) && PIPETX05EQCOEFF_delay[12]; // rv 0 + assign PIPETX05EQCOEFF_in[13] = (PIPETX05EQCOEFF[13] !== 1'bz) && PIPETX05EQCOEFF_delay[13]; // rv 0 + assign PIPETX05EQCOEFF_in[14] = (PIPETX05EQCOEFF[14] !== 1'bz) && PIPETX05EQCOEFF_delay[14]; // rv 0 + assign PIPETX05EQCOEFF_in[15] = (PIPETX05EQCOEFF[15] !== 1'bz) && PIPETX05EQCOEFF_delay[15]; // rv 0 + assign PIPETX05EQCOEFF_in[16] = (PIPETX05EQCOEFF[16] !== 1'bz) && PIPETX05EQCOEFF_delay[16]; // rv 0 + assign PIPETX05EQCOEFF_in[17] = (PIPETX05EQCOEFF[17] !== 1'bz) && PIPETX05EQCOEFF_delay[17]; // rv 0 + assign PIPETX05EQCOEFF_in[1] = (PIPETX05EQCOEFF[1] !== 1'bz) && PIPETX05EQCOEFF_delay[1]; // rv 0 + assign PIPETX05EQCOEFF_in[2] = (PIPETX05EQCOEFF[2] !== 1'bz) && PIPETX05EQCOEFF_delay[2]; // rv 0 + assign PIPETX05EQCOEFF_in[3] = (PIPETX05EQCOEFF[3] !== 1'bz) && PIPETX05EQCOEFF_delay[3]; // rv 0 + assign PIPETX05EQCOEFF_in[4] = (PIPETX05EQCOEFF[4] !== 1'bz) && PIPETX05EQCOEFF_delay[4]; // rv 0 + assign PIPETX05EQCOEFF_in[5] = (PIPETX05EQCOEFF[5] !== 1'bz) && PIPETX05EQCOEFF_delay[5]; // rv 0 + assign PIPETX05EQCOEFF_in[6] = (PIPETX05EQCOEFF[6] !== 1'bz) && PIPETX05EQCOEFF_delay[6]; // rv 0 + assign PIPETX05EQCOEFF_in[7] = (PIPETX05EQCOEFF[7] !== 1'bz) && PIPETX05EQCOEFF_delay[7]; // rv 0 + assign PIPETX05EQCOEFF_in[8] = (PIPETX05EQCOEFF[8] !== 1'bz) && PIPETX05EQCOEFF_delay[8]; // rv 0 + assign PIPETX05EQCOEFF_in[9] = (PIPETX05EQCOEFF[9] !== 1'bz) && PIPETX05EQCOEFF_delay[9]; // rv 0 + assign PIPETX05EQDONE_in = (PIPETX05EQDONE !== 1'bz) && PIPETX05EQDONE_delay; // rv 0 + assign PIPETX06EQCOEFF_in[0] = (PIPETX06EQCOEFF[0] !== 1'bz) && PIPETX06EQCOEFF_delay[0]; // rv 0 + assign PIPETX06EQCOEFF_in[10] = (PIPETX06EQCOEFF[10] !== 1'bz) && PIPETX06EQCOEFF_delay[10]; // rv 0 + assign PIPETX06EQCOEFF_in[11] = (PIPETX06EQCOEFF[11] !== 1'bz) && PIPETX06EQCOEFF_delay[11]; // rv 0 + assign PIPETX06EQCOEFF_in[12] = (PIPETX06EQCOEFF[12] !== 1'bz) && PIPETX06EQCOEFF_delay[12]; // rv 0 + assign PIPETX06EQCOEFF_in[13] = (PIPETX06EQCOEFF[13] !== 1'bz) && PIPETX06EQCOEFF_delay[13]; // rv 0 + assign PIPETX06EQCOEFF_in[14] = (PIPETX06EQCOEFF[14] !== 1'bz) && PIPETX06EQCOEFF_delay[14]; // rv 0 + assign PIPETX06EQCOEFF_in[15] = (PIPETX06EQCOEFF[15] !== 1'bz) && PIPETX06EQCOEFF_delay[15]; // rv 0 + assign PIPETX06EQCOEFF_in[16] = (PIPETX06EQCOEFF[16] !== 1'bz) && PIPETX06EQCOEFF_delay[16]; // rv 0 + assign PIPETX06EQCOEFF_in[17] = (PIPETX06EQCOEFF[17] !== 1'bz) && PIPETX06EQCOEFF_delay[17]; // rv 0 + assign PIPETX06EQCOEFF_in[1] = (PIPETX06EQCOEFF[1] !== 1'bz) && PIPETX06EQCOEFF_delay[1]; // rv 0 + assign PIPETX06EQCOEFF_in[2] = (PIPETX06EQCOEFF[2] !== 1'bz) && PIPETX06EQCOEFF_delay[2]; // rv 0 + assign PIPETX06EQCOEFF_in[3] = (PIPETX06EQCOEFF[3] !== 1'bz) && PIPETX06EQCOEFF_delay[3]; // rv 0 + assign PIPETX06EQCOEFF_in[4] = (PIPETX06EQCOEFF[4] !== 1'bz) && PIPETX06EQCOEFF_delay[4]; // rv 0 + assign PIPETX06EQCOEFF_in[5] = (PIPETX06EQCOEFF[5] !== 1'bz) && PIPETX06EQCOEFF_delay[5]; // rv 0 + assign PIPETX06EQCOEFF_in[6] = (PIPETX06EQCOEFF[6] !== 1'bz) && PIPETX06EQCOEFF_delay[6]; // rv 0 + assign PIPETX06EQCOEFF_in[7] = (PIPETX06EQCOEFF[7] !== 1'bz) && PIPETX06EQCOEFF_delay[7]; // rv 0 + assign PIPETX06EQCOEFF_in[8] = (PIPETX06EQCOEFF[8] !== 1'bz) && PIPETX06EQCOEFF_delay[8]; // rv 0 + assign PIPETX06EQCOEFF_in[9] = (PIPETX06EQCOEFF[9] !== 1'bz) && PIPETX06EQCOEFF_delay[9]; // rv 0 + assign PIPETX06EQDONE_in = (PIPETX06EQDONE !== 1'bz) && PIPETX06EQDONE_delay; // rv 0 + assign PIPETX07EQCOEFF_in[0] = (PIPETX07EQCOEFF[0] !== 1'bz) && PIPETX07EQCOEFF_delay[0]; // rv 0 + assign PIPETX07EQCOEFF_in[10] = (PIPETX07EQCOEFF[10] !== 1'bz) && PIPETX07EQCOEFF_delay[10]; // rv 0 + assign PIPETX07EQCOEFF_in[11] = (PIPETX07EQCOEFF[11] !== 1'bz) && PIPETX07EQCOEFF_delay[11]; // rv 0 + assign PIPETX07EQCOEFF_in[12] = (PIPETX07EQCOEFF[12] !== 1'bz) && PIPETX07EQCOEFF_delay[12]; // rv 0 + assign PIPETX07EQCOEFF_in[13] = (PIPETX07EQCOEFF[13] !== 1'bz) && PIPETX07EQCOEFF_delay[13]; // rv 0 + assign PIPETX07EQCOEFF_in[14] = (PIPETX07EQCOEFF[14] !== 1'bz) && PIPETX07EQCOEFF_delay[14]; // rv 0 + assign PIPETX07EQCOEFF_in[15] = (PIPETX07EQCOEFF[15] !== 1'bz) && PIPETX07EQCOEFF_delay[15]; // rv 0 + assign PIPETX07EQCOEFF_in[16] = (PIPETX07EQCOEFF[16] !== 1'bz) && PIPETX07EQCOEFF_delay[16]; // rv 0 + assign PIPETX07EQCOEFF_in[17] = (PIPETX07EQCOEFF[17] !== 1'bz) && PIPETX07EQCOEFF_delay[17]; // rv 0 + assign PIPETX07EQCOEFF_in[1] = (PIPETX07EQCOEFF[1] !== 1'bz) && PIPETX07EQCOEFF_delay[1]; // rv 0 + assign PIPETX07EQCOEFF_in[2] = (PIPETX07EQCOEFF[2] !== 1'bz) && PIPETX07EQCOEFF_delay[2]; // rv 0 + assign PIPETX07EQCOEFF_in[3] = (PIPETX07EQCOEFF[3] !== 1'bz) && PIPETX07EQCOEFF_delay[3]; // rv 0 + assign PIPETX07EQCOEFF_in[4] = (PIPETX07EQCOEFF[4] !== 1'bz) && PIPETX07EQCOEFF_delay[4]; // rv 0 + assign PIPETX07EQCOEFF_in[5] = (PIPETX07EQCOEFF[5] !== 1'bz) && PIPETX07EQCOEFF_delay[5]; // rv 0 + assign PIPETX07EQCOEFF_in[6] = (PIPETX07EQCOEFF[6] !== 1'bz) && PIPETX07EQCOEFF_delay[6]; // rv 0 + assign PIPETX07EQCOEFF_in[7] = (PIPETX07EQCOEFF[7] !== 1'bz) && PIPETX07EQCOEFF_delay[7]; // rv 0 + assign PIPETX07EQCOEFF_in[8] = (PIPETX07EQCOEFF[8] !== 1'bz) && PIPETX07EQCOEFF_delay[8]; // rv 0 + assign PIPETX07EQCOEFF_in[9] = (PIPETX07EQCOEFF[9] !== 1'bz) && PIPETX07EQCOEFF_delay[9]; // rv 0 + assign PIPETX07EQDONE_in = (PIPETX07EQDONE !== 1'bz) && PIPETX07EQDONE_delay; // rv 0 + assign PIPETX08EQCOEFF_in[0] = (PIPETX08EQCOEFF[0] !== 1'bz) && PIPETX08EQCOEFF_delay[0]; // rv 0 + assign PIPETX08EQCOEFF_in[10] = (PIPETX08EQCOEFF[10] !== 1'bz) && PIPETX08EQCOEFF_delay[10]; // rv 0 + assign PIPETX08EQCOEFF_in[11] = (PIPETX08EQCOEFF[11] !== 1'bz) && PIPETX08EQCOEFF_delay[11]; // rv 0 + assign PIPETX08EQCOEFF_in[12] = (PIPETX08EQCOEFF[12] !== 1'bz) && PIPETX08EQCOEFF_delay[12]; // rv 0 + assign PIPETX08EQCOEFF_in[13] = (PIPETX08EQCOEFF[13] !== 1'bz) && PIPETX08EQCOEFF_delay[13]; // rv 0 + assign PIPETX08EQCOEFF_in[14] = (PIPETX08EQCOEFF[14] !== 1'bz) && PIPETX08EQCOEFF_delay[14]; // rv 0 + assign PIPETX08EQCOEFF_in[15] = (PIPETX08EQCOEFF[15] !== 1'bz) && PIPETX08EQCOEFF_delay[15]; // rv 0 + assign PIPETX08EQCOEFF_in[16] = (PIPETX08EQCOEFF[16] !== 1'bz) && PIPETX08EQCOEFF_delay[16]; // rv 0 + assign PIPETX08EQCOEFF_in[17] = (PIPETX08EQCOEFF[17] !== 1'bz) && PIPETX08EQCOEFF_delay[17]; // rv 0 + assign PIPETX08EQCOEFF_in[1] = (PIPETX08EQCOEFF[1] !== 1'bz) && PIPETX08EQCOEFF_delay[1]; // rv 0 + assign PIPETX08EQCOEFF_in[2] = (PIPETX08EQCOEFF[2] !== 1'bz) && PIPETX08EQCOEFF_delay[2]; // rv 0 + assign PIPETX08EQCOEFF_in[3] = (PIPETX08EQCOEFF[3] !== 1'bz) && PIPETX08EQCOEFF_delay[3]; // rv 0 + assign PIPETX08EQCOEFF_in[4] = (PIPETX08EQCOEFF[4] !== 1'bz) && PIPETX08EQCOEFF_delay[4]; // rv 0 + assign PIPETX08EQCOEFF_in[5] = (PIPETX08EQCOEFF[5] !== 1'bz) && PIPETX08EQCOEFF_delay[5]; // rv 0 + assign PIPETX08EQCOEFF_in[6] = (PIPETX08EQCOEFF[6] !== 1'bz) && PIPETX08EQCOEFF_delay[6]; // rv 0 + assign PIPETX08EQCOEFF_in[7] = (PIPETX08EQCOEFF[7] !== 1'bz) && PIPETX08EQCOEFF_delay[7]; // rv 0 + assign PIPETX08EQCOEFF_in[8] = (PIPETX08EQCOEFF[8] !== 1'bz) && PIPETX08EQCOEFF_delay[8]; // rv 0 + assign PIPETX08EQCOEFF_in[9] = (PIPETX08EQCOEFF[9] !== 1'bz) && PIPETX08EQCOEFF_delay[9]; // rv 0 + assign PIPETX08EQDONE_in = (PIPETX08EQDONE !== 1'bz) && PIPETX08EQDONE_delay; // rv 0 + assign PIPETX09EQCOEFF_in[0] = (PIPETX09EQCOEFF[0] !== 1'bz) && PIPETX09EQCOEFF_delay[0]; // rv 0 + assign PIPETX09EQCOEFF_in[10] = (PIPETX09EQCOEFF[10] !== 1'bz) && PIPETX09EQCOEFF_delay[10]; // rv 0 + assign PIPETX09EQCOEFF_in[11] = (PIPETX09EQCOEFF[11] !== 1'bz) && PIPETX09EQCOEFF_delay[11]; // rv 0 + assign PIPETX09EQCOEFF_in[12] = (PIPETX09EQCOEFF[12] !== 1'bz) && PIPETX09EQCOEFF_delay[12]; // rv 0 + assign PIPETX09EQCOEFF_in[13] = (PIPETX09EQCOEFF[13] !== 1'bz) && PIPETX09EQCOEFF_delay[13]; // rv 0 + assign PIPETX09EQCOEFF_in[14] = (PIPETX09EQCOEFF[14] !== 1'bz) && PIPETX09EQCOEFF_delay[14]; // rv 0 + assign PIPETX09EQCOEFF_in[15] = (PIPETX09EQCOEFF[15] !== 1'bz) && PIPETX09EQCOEFF_delay[15]; // rv 0 + assign PIPETX09EQCOEFF_in[16] = (PIPETX09EQCOEFF[16] !== 1'bz) && PIPETX09EQCOEFF_delay[16]; // rv 0 + assign PIPETX09EQCOEFF_in[17] = (PIPETX09EQCOEFF[17] !== 1'bz) && PIPETX09EQCOEFF_delay[17]; // rv 0 + assign PIPETX09EQCOEFF_in[1] = (PIPETX09EQCOEFF[1] !== 1'bz) && PIPETX09EQCOEFF_delay[1]; // rv 0 + assign PIPETX09EQCOEFF_in[2] = (PIPETX09EQCOEFF[2] !== 1'bz) && PIPETX09EQCOEFF_delay[2]; // rv 0 + assign PIPETX09EQCOEFF_in[3] = (PIPETX09EQCOEFF[3] !== 1'bz) && PIPETX09EQCOEFF_delay[3]; // rv 0 + assign PIPETX09EQCOEFF_in[4] = (PIPETX09EQCOEFF[4] !== 1'bz) && PIPETX09EQCOEFF_delay[4]; // rv 0 + assign PIPETX09EQCOEFF_in[5] = (PIPETX09EQCOEFF[5] !== 1'bz) && PIPETX09EQCOEFF_delay[5]; // rv 0 + assign PIPETX09EQCOEFF_in[6] = (PIPETX09EQCOEFF[6] !== 1'bz) && PIPETX09EQCOEFF_delay[6]; // rv 0 + assign PIPETX09EQCOEFF_in[7] = (PIPETX09EQCOEFF[7] !== 1'bz) && PIPETX09EQCOEFF_delay[7]; // rv 0 + assign PIPETX09EQCOEFF_in[8] = (PIPETX09EQCOEFF[8] !== 1'bz) && PIPETX09EQCOEFF_delay[8]; // rv 0 + assign PIPETX09EQCOEFF_in[9] = (PIPETX09EQCOEFF[9] !== 1'bz) && PIPETX09EQCOEFF_delay[9]; // rv 0 + assign PIPETX09EQDONE_in = (PIPETX09EQDONE !== 1'bz) && PIPETX09EQDONE_delay; // rv 0 + assign PIPETX10EQCOEFF_in[0] = (PIPETX10EQCOEFF[0] !== 1'bz) && PIPETX10EQCOEFF_delay[0]; // rv 0 + assign PIPETX10EQCOEFF_in[10] = (PIPETX10EQCOEFF[10] !== 1'bz) && PIPETX10EQCOEFF_delay[10]; // rv 0 + assign PIPETX10EQCOEFF_in[11] = (PIPETX10EQCOEFF[11] !== 1'bz) && PIPETX10EQCOEFF_delay[11]; // rv 0 + assign PIPETX10EQCOEFF_in[12] = (PIPETX10EQCOEFF[12] !== 1'bz) && PIPETX10EQCOEFF_delay[12]; // rv 0 + assign PIPETX10EQCOEFF_in[13] = (PIPETX10EQCOEFF[13] !== 1'bz) && PIPETX10EQCOEFF_delay[13]; // rv 0 + assign PIPETX10EQCOEFF_in[14] = (PIPETX10EQCOEFF[14] !== 1'bz) && PIPETX10EQCOEFF_delay[14]; // rv 0 + assign PIPETX10EQCOEFF_in[15] = (PIPETX10EQCOEFF[15] !== 1'bz) && PIPETX10EQCOEFF_delay[15]; // rv 0 + assign PIPETX10EQCOEFF_in[16] = (PIPETX10EQCOEFF[16] !== 1'bz) && PIPETX10EQCOEFF_delay[16]; // rv 0 + assign PIPETX10EQCOEFF_in[17] = (PIPETX10EQCOEFF[17] !== 1'bz) && PIPETX10EQCOEFF_delay[17]; // rv 0 + assign PIPETX10EQCOEFF_in[1] = (PIPETX10EQCOEFF[1] !== 1'bz) && PIPETX10EQCOEFF_delay[1]; // rv 0 + assign PIPETX10EQCOEFF_in[2] = (PIPETX10EQCOEFF[2] !== 1'bz) && PIPETX10EQCOEFF_delay[2]; // rv 0 + assign PIPETX10EQCOEFF_in[3] = (PIPETX10EQCOEFF[3] !== 1'bz) && PIPETX10EQCOEFF_delay[3]; // rv 0 + assign PIPETX10EQCOEFF_in[4] = (PIPETX10EQCOEFF[4] !== 1'bz) && PIPETX10EQCOEFF_delay[4]; // rv 0 + assign PIPETX10EQCOEFF_in[5] = (PIPETX10EQCOEFF[5] !== 1'bz) && PIPETX10EQCOEFF_delay[5]; // rv 0 + assign PIPETX10EQCOEFF_in[6] = (PIPETX10EQCOEFF[6] !== 1'bz) && PIPETX10EQCOEFF_delay[6]; // rv 0 + assign PIPETX10EQCOEFF_in[7] = (PIPETX10EQCOEFF[7] !== 1'bz) && PIPETX10EQCOEFF_delay[7]; // rv 0 + assign PIPETX10EQCOEFF_in[8] = (PIPETX10EQCOEFF[8] !== 1'bz) && PIPETX10EQCOEFF_delay[8]; // rv 0 + assign PIPETX10EQCOEFF_in[9] = (PIPETX10EQCOEFF[9] !== 1'bz) && PIPETX10EQCOEFF_delay[9]; // rv 0 + assign PIPETX10EQDONE_in = (PIPETX10EQDONE !== 1'bz) && PIPETX10EQDONE_delay; // rv 0 + assign PIPETX11EQCOEFF_in[0] = (PIPETX11EQCOEFF[0] !== 1'bz) && PIPETX11EQCOEFF_delay[0]; // rv 0 + assign PIPETX11EQCOEFF_in[10] = (PIPETX11EQCOEFF[10] !== 1'bz) && PIPETX11EQCOEFF_delay[10]; // rv 0 + assign PIPETX11EQCOEFF_in[11] = (PIPETX11EQCOEFF[11] !== 1'bz) && PIPETX11EQCOEFF_delay[11]; // rv 0 + assign PIPETX11EQCOEFF_in[12] = (PIPETX11EQCOEFF[12] !== 1'bz) && PIPETX11EQCOEFF_delay[12]; // rv 0 + assign PIPETX11EQCOEFF_in[13] = (PIPETX11EQCOEFF[13] !== 1'bz) && PIPETX11EQCOEFF_delay[13]; // rv 0 + assign PIPETX11EQCOEFF_in[14] = (PIPETX11EQCOEFF[14] !== 1'bz) && PIPETX11EQCOEFF_delay[14]; // rv 0 + assign PIPETX11EQCOEFF_in[15] = (PIPETX11EQCOEFF[15] !== 1'bz) && PIPETX11EQCOEFF_delay[15]; // rv 0 + assign PIPETX11EQCOEFF_in[16] = (PIPETX11EQCOEFF[16] !== 1'bz) && PIPETX11EQCOEFF_delay[16]; // rv 0 + assign PIPETX11EQCOEFF_in[17] = (PIPETX11EQCOEFF[17] !== 1'bz) && PIPETX11EQCOEFF_delay[17]; // rv 0 + assign PIPETX11EQCOEFF_in[1] = (PIPETX11EQCOEFF[1] !== 1'bz) && PIPETX11EQCOEFF_delay[1]; // rv 0 + assign PIPETX11EQCOEFF_in[2] = (PIPETX11EQCOEFF[2] !== 1'bz) && PIPETX11EQCOEFF_delay[2]; // rv 0 + assign PIPETX11EQCOEFF_in[3] = (PIPETX11EQCOEFF[3] !== 1'bz) && PIPETX11EQCOEFF_delay[3]; // rv 0 + assign PIPETX11EQCOEFF_in[4] = (PIPETX11EQCOEFF[4] !== 1'bz) && PIPETX11EQCOEFF_delay[4]; // rv 0 + assign PIPETX11EQCOEFF_in[5] = (PIPETX11EQCOEFF[5] !== 1'bz) && PIPETX11EQCOEFF_delay[5]; // rv 0 + assign PIPETX11EQCOEFF_in[6] = (PIPETX11EQCOEFF[6] !== 1'bz) && PIPETX11EQCOEFF_delay[6]; // rv 0 + assign PIPETX11EQCOEFF_in[7] = (PIPETX11EQCOEFF[7] !== 1'bz) && PIPETX11EQCOEFF_delay[7]; // rv 0 + assign PIPETX11EQCOEFF_in[8] = (PIPETX11EQCOEFF[8] !== 1'bz) && PIPETX11EQCOEFF_delay[8]; // rv 0 + assign PIPETX11EQCOEFF_in[9] = (PIPETX11EQCOEFF[9] !== 1'bz) && PIPETX11EQCOEFF_delay[9]; // rv 0 + assign PIPETX11EQDONE_in = (PIPETX11EQDONE !== 1'bz) && PIPETX11EQDONE_delay; // rv 0 + assign PIPETX12EQCOEFF_in[0] = (PIPETX12EQCOEFF[0] !== 1'bz) && PIPETX12EQCOEFF_delay[0]; // rv 0 + assign PIPETX12EQCOEFF_in[10] = (PIPETX12EQCOEFF[10] !== 1'bz) && PIPETX12EQCOEFF_delay[10]; // rv 0 + assign PIPETX12EQCOEFF_in[11] = (PIPETX12EQCOEFF[11] !== 1'bz) && PIPETX12EQCOEFF_delay[11]; // rv 0 + assign PIPETX12EQCOEFF_in[12] = (PIPETX12EQCOEFF[12] !== 1'bz) && PIPETX12EQCOEFF_delay[12]; // rv 0 + assign PIPETX12EQCOEFF_in[13] = (PIPETX12EQCOEFF[13] !== 1'bz) && PIPETX12EQCOEFF_delay[13]; // rv 0 + assign PIPETX12EQCOEFF_in[14] = (PIPETX12EQCOEFF[14] !== 1'bz) && PIPETX12EQCOEFF_delay[14]; // rv 0 + assign PIPETX12EQCOEFF_in[15] = (PIPETX12EQCOEFF[15] !== 1'bz) && PIPETX12EQCOEFF_delay[15]; // rv 0 + assign PIPETX12EQCOEFF_in[16] = (PIPETX12EQCOEFF[16] !== 1'bz) && PIPETX12EQCOEFF_delay[16]; // rv 0 + assign PIPETX12EQCOEFF_in[17] = (PIPETX12EQCOEFF[17] !== 1'bz) && PIPETX12EQCOEFF_delay[17]; // rv 0 + assign PIPETX12EQCOEFF_in[1] = (PIPETX12EQCOEFF[1] !== 1'bz) && PIPETX12EQCOEFF_delay[1]; // rv 0 + assign PIPETX12EQCOEFF_in[2] = (PIPETX12EQCOEFF[2] !== 1'bz) && PIPETX12EQCOEFF_delay[2]; // rv 0 + assign PIPETX12EQCOEFF_in[3] = (PIPETX12EQCOEFF[3] !== 1'bz) && PIPETX12EQCOEFF_delay[3]; // rv 0 + assign PIPETX12EQCOEFF_in[4] = (PIPETX12EQCOEFF[4] !== 1'bz) && PIPETX12EQCOEFF_delay[4]; // rv 0 + assign PIPETX12EQCOEFF_in[5] = (PIPETX12EQCOEFF[5] !== 1'bz) && PIPETX12EQCOEFF_delay[5]; // rv 0 + assign PIPETX12EQCOEFF_in[6] = (PIPETX12EQCOEFF[6] !== 1'bz) && PIPETX12EQCOEFF_delay[6]; // rv 0 + assign PIPETX12EQCOEFF_in[7] = (PIPETX12EQCOEFF[7] !== 1'bz) && PIPETX12EQCOEFF_delay[7]; // rv 0 + assign PIPETX12EQCOEFF_in[8] = (PIPETX12EQCOEFF[8] !== 1'bz) && PIPETX12EQCOEFF_delay[8]; // rv 0 + assign PIPETX12EQCOEFF_in[9] = (PIPETX12EQCOEFF[9] !== 1'bz) && PIPETX12EQCOEFF_delay[9]; // rv 0 + assign PIPETX12EQDONE_in = (PIPETX12EQDONE !== 1'bz) && PIPETX12EQDONE_delay; // rv 0 + assign PIPETX13EQCOEFF_in[0] = (PIPETX13EQCOEFF[0] !== 1'bz) && PIPETX13EQCOEFF_delay[0]; // rv 0 + assign PIPETX13EQCOEFF_in[10] = (PIPETX13EQCOEFF[10] !== 1'bz) && PIPETX13EQCOEFF_delay[10]; // rv 0 + assign PIPETX13EQCOEFF_in[11] = (PIPETX13EQCOEFF[11] !== 1'bz) && PIPETX13EQCOEFF_delay[11]; // rv 0 + assign PIPETX13EQCOEFF_in[12] = (PIPETX13EQCOEFF[12] !== 1'bz) && PIPETX13EQCOEFF_delay[12]; // rv 0 + assign PIPETX13EQCOEFF_in[13] = (PIPETX13EQCOEFF[13] !== 1'bz) && PIPETX13EQCOEFF_delay[13]; // rv 0 + assign PIPETX13EQCOEFF_in[14] = (PIPETX13EQCOEFF[14] !== 1'bz) && PIPETX13EQCOEFF_delay[14]; // rv 0 + assign PIPETX13EQCOEFF_in[15] = (PIPETX13EQCOEFF[15] !== 1'bz) && PIPETX13EQCOEFF_delay[15]; // rv 0 + assign PIPETX13EQCOEFF_in[16] = (PIPETX13EQCOEFF[16] !== 1'bz) && PIPETX13EQCOEFF_delay[16]; // rv 0 + assign PIPETX13EQCOEFF_in[17] = (PIPETX13EQCOEFF[17] !== 1'bz) && PIPETX13EQCOEFF_delay[17]; // rv 0 + assign PIPETX13EQCOEFF_in[1] = (PIPETX13EQCOEFF[1] !== 1'bz) && PIPETX13EQCOEFF_delay[1]; // rv 0 + assign PIPETX13EQCOEFF_in[2] = (PIPETX13EQCOEFF[2] !== 1'bz) && PIPETX13EQCOEFF_delay[2]; // rv 0 + assign PIPETX13EQCOEFF_in[3] = (PIPETX13EQCOEFF[3] !== 1'bz) && PIPETX13EQCOEFF_delay[3]; // rv 0 + assign PIPETX13EQCOEFF_in[4] = (PIPETX13EQCOEFF[4] !== 1'bz) && PIPETX13EQCOEFF_delay[4]; // rv 0 + assign PIPETX13EQCOEFF_in[5] = (PIPETX13EQCOEFF[5] !== 1'bz) && PIPETX13EQCOEFF_delay[5]; // rv 0 + assign PIPETX13EQCOEFF_in[6] = (PIPETX13EQCOEFF[6] !== 1'bz) && PIPETX13EQCOEFF_delay[6]; // rv 0 + assign PIPETX13EQCOEFF_in[7] = (PIPETX13EQCOEFF[7] !== 1'bz) && PIPETX13EQCOEFF_delay[7]; // rv 0 + assign PIPETX13EQCOEFF_in[8] = (PIPETX13EQCOEFF[8] !== 1'bz) && PIPETX13EQCOEFF_delay[8]; // rv 0 + assign PIPETX13EQCOEFF_in[9] = (PIPETX13EQCOEFF[9] !== 1'bz) && PIPETX13EQCOEFF_delay[9]; // rv 0 + assign PIPETX13EQDONE_in = (PIPETX13EQDONE !== 1'bz) && PIPETX13EQDONE_delay; // rv 0 + assign PIPETX14EQCOEFF_in[0] = (PIPETX14EQCOEFF[0] !== 1'bz) && PIPETX14EQCOEFF_delay[0]; // rv 0 + assign PIPETX14EQCOEFF_in[10] = (PIPETX14EQCOEFF[10] !== 1'bz) && PIPETX14EQCOEFF_delay[10]; // rv 0 + assign PIPETX14EQCOEFF_in[11] = (PIPETX14EQCOEFF[11] !== 1'bz) && PIPETX14EQCOEFF_delay[11]; // rv 0 + assign PIPETX14EQCOEFF_in[12] = (PIPETX14EQCOEFF[12] !== 1'bz) && PIPETX14EQCOEFF_delay[12]; // rv 0 + assign PIPETX14EQCOEFF_in[13] = (PIPETX14EQCOEFF[13] !== 1'bz) && PIPETX14EQCOEFF_delay[13]; // rv 0 + assign PIPETX14EQCOEFF_in[14] = (PIPETX14EQCOEFF[14] !== 1'bz) && PIPETX14EQCOEFF_delay[14]; // rv 0 + assign PIPETX14EQCOEFF_in[15] = (PIPETX14EQCOEFF[15] !== 1'bz) && PIPETX14EQCOEFF_delay[15]; // rv 0 + assign PIPETX14EQCOEFF_in[16] = (PIPETX14EQCOEFF[16] !== 1'bz) && PIPETX14EQCOEFF_delay[16]; // rv 0 + assign PIPETX14EQCOEFF_in[17] = (PIPETX14EQCOEFF[17] !== 1'bz) && PIPETX14EQCOEFF_delay[17]; // rv 0 + assign PIPETX14EQCOEFF_in[1] = (PIPETX14EQCOEFF[1] !== 1'bz) && PIPETX14EQCOEFF_delay[1]; // rv 0 + assign PIPETX14EQCOEFF_in[2] = (PIPETX14EQCOEFF[2] !== 1'bz) && PIPETX14EQCOEFF_delay[2]; // rv 0 + assign PIPETX14EQCOEFF_in[3] = (PIPETX14EQCOEFF[3] !== 1'bz) && PIPETX14EQCOEFF_delay[3]; // rv 0 + assign PIPETX14EQCOEFF_in[4] = (PIPETX14EQCOEFF[4] !== 1'bz) && PIPETX14EQCOEFF_delay[4]; // rv 0 + assign PIPETX14EQCOEFF_in[5] = (PIPETX14EQCOEFF[5] !== 1'bz) && PIPETX14EQCOEFF_delay[5]; // rv 0 + assign PIPETX14EQCOEFF_in[6] = (PIPETX14EQCOEFF[6] !== 1'bz) && PIPETX14EQCOEFF_delay[6]; // rv 0 + assign PIPETX14EQCOEFF_in[7] = (PIPETX14EQCOEFF[7] !== 1'bz) && PIPETX14EQCOEFF_delay[7]; // rv 0 + assign PIPETX14EQCOEFF_in[8] = (PIPETX14EQCOEFF[8] !== 1'bz) && PIPETX14EQCOEFF_delay[8]; // rv 0 + assign PIPETX14EQCOEFF_in[9] = (PIPETX14EQCOEFF[9] !== 1'bz) && PIPETX14EQCOEFF_delay[9]; // rv 0 + assign PIPETX14EQDONE_in = (PIPETX14EQDONE !== 1'bz) && PIPETX14EQDONE_delay; // rv 0 + assign PIPETX15EQCOEFF_in[0] = (PIPETX15EQCOEFF[0] !== 1'bz) && PIPETX15EQCOEFF_delay[0]; // rv 0 + assign PIPETX15EQCOEFF_in[10] = (PIPETX15EQCOEFF[10] !== 1'bz) && PIPETX15EQCOEFF_delay[10]; // rv 0 + assign PIPETX15EQCOEFF_in[11] = (PIPETX15EQCOEFF[11] !== 1'bz) && PIPETX15EQCOEFF_delay[11]; // rv 0 + assign PIPETX15EQCOEFF_in[12] = (PIPETX15EQCOEFF[12] !== 1'bz) && PIPETX15EQCOEFF_delay[12]; // rv 0 + assign PIPETX15EQCOEFF_in[13] = (PIPETX15EQCOEFF[13] !== 1'bz) && PIPETX15EQCOEFF_delay[13]; // rv 0 + assign PIPETX15EQCOEFF_in[14] = (PIPETX15EQCOEFF[14] !== 1'bz) && PIPETX15EQCOEFF_delay[14]; // rv 0 + assign PIPETX15EQCOEFF_in[15] = (PIPETX15EQCOEFF[15] !== 1'bz) && PIPETX15EQCOEFF_delay[15]; // rv 0 + assign PIPETX15EQCOEFF_in[16] = (PIPETX15EQCOEFF[16] !== 1'bz) && PIPETX15EQCOEFF_delay[16]; // rv 0 + assign PIPETX15EQCOEFF_in[17] = (PIPETX15EQCOEFF[17] !== 1'bz) && PIPETX15EQCOEFF_delay[17]; // rv 0 + assign PIPETX15EQCOEFF_in[1] = (PIPETX15EQCOEFF[1] !== 1'bz) && PIPETX15EQCOEFF_delay[1]; // rv 0 + assign PIPETX15EQCOEFF_in[2] = (PIPETX15EQCOEFF[2] !== 1'bz) && PIPETX15EQCOEFF_delay[2]; // rv 0 + assign PIPETX15EQCOEFF_in[3] = (PIPETX15EQCOEFF[3] !== 1'bz) && PIPETX15EQCOEFF_delay[3]; // rv 0 + assign PIPETX15EQCOEFF_in[4] = (PIPETX15EQCOEFF[4] !== 1'bz) && PIPETX15EQCOEFF_delay[4]; // rv 0 + assign PIPETX15EQCOEFF_in[5] = (PIPETX15EQCOEFF[5] !== 1'bz) && PIPETX15EQCOEFF_delay[5]; // rv 0 + assign PIPETX15EQCOEFF_in[6] = (PIPETX15EQCOEFF[6] !== 1'bz) && PIPETX15EQCOEFF_delay[6]; // rv 0 + assign PIPETX15EQCOEFF_in[7] = (PIPETX15EQCOEFF[7] !== 1'bz) && PIPETX15EQCOEFF_delay[7]; // rv 0 + assign PIPETX15EQCOEFF_in[8] = (PIPETX15EQCOEFF[8] !== 1'bz) && PIPETX15EQCOEFF_delay[8]; // rv 0 + assign PIPETX15EQCOEFF_in[9] = (PIPETX15EQCOEFF[9] !== 1'bz) && PIPETX15EQCOEFF_delay[9]; // rv 0 + assign PIPETX15EQDONE_in = (PIPETX15EQDONE !== 1'bz) && PIPETX15EQDONE_delay; // rv 0 + assign PLGEN2UPSTREAMPREFERDEEMPH_in = (PLGEN2UPSTREAMPREFERDEEMPH !== 1'bz) && PLGEN2UPSTREAMPREFERDEEMPH_delay; // rv 0 + assign PLGEN34REDOEQSPEED_in = (PLGEN34REDOEQSPEED !== 1'bz) && PLGEN34REDOEQSPEED_delay; // rv 0 + assign PLGEN34REDOEQUALIZATION_in = (PLGEN34REDOEQUALIZATION !== 1'bz) && PLGEN34REDOEQUALIZATION_delay; // rv 0 + assign SAXISCCTDATA_in[0] = (SAXISCCTDATA[0] === 1'bz) || SAXISCCTDATA_delay[0]; // rv 1 + assign SAXISCCTDATA_in[100] = (SAXISCCTDATA[100] === 1'bz) || SAXISCCTDATA_delay[100]; // rv 1 + assign SAXISCCTDATA_in[101] = (SAXISCCTDATA[101] === 1'bz) || SAXISCCTDATA_delay[101]; // rv 1 + assign SAXISCCTDATA_in[102] = (SAXISCCTDATA[102] === 1'bz) || SAXISCCTDATA_delay[102]; // rv 1 + assign SAXISCCTDATA_in[103] = (SAXISCCTDATA[103] === 1'bz) || SAXISCCTDATA_delay[103]; // rv 1 + assign SAXISCCTDATA_in[104] = (SAXISCCTDATA[104] === 1'bz) || SAXISCCTDATA_delay[104]; // rv 1 + assign SAXISCCTDATA_in[105] = (SAXISCCTDATA[105] === 1'bz) || SAXISCCTDATA_delay[105]; // rv 1 + assign SAXISCCTDATA_in[106] = (SAXISCCTDATA[106] === 1'bz) || SAXISCCTDATA_delay[106]; // rv 1 + assign SAXISCCTDATA_in[107] = (SAXISCCTDATA[107] === 1'bz) || SAXISCCTDATA_delay[107]; // rv 1 + assign SAXISCCTDATA_in[108] = (SAXISCCTDATA[108] === 1'bz) || SAXISCCTDATA_delay[108]; // rv 1 + assign SAXISCCTDATA_in[109] = (SAXISCCTDATA[109] === 1'bz) || SAXISCCTDATA_delay[109]; // rv 1 + assign SAXISCCTDATA_in[10] = (SAXISCCTDATA[10] === 1'bz) || SAXISCCTDATA_delay[10]; // rv 1 + assign SAXISCCTDATA_in[110] = (SAXISCCTDATA[110] === 1'bz) || SAXISCCTDATA_delay[110]; // rv 1 + assign SAXISCCTDATA_in[111] = (SAXISCCTDATA[111] === 1'bz) || SAXISCCTDATA_delay[111]; // rv 1 + assign SAXISCCTDATA_in[112] = (SAXISCCTDATA[112] === 1'bz) || SAXISCCTDATA_delay[112]; // rv 1 + assign SAXISCCTDATA_in[113] = (SAXISCCTDATA[113] === 1'bz) || SAXISCCTDATA_delay[113]; // rv 1 + assign SAXISCCTDATA_in[114] = (SAXISCCTDATA[114] === 1'bz) || SAXISCCTDATA_delay[114]; // rv 1 + assign SAXISCCTDATA_in[115] = (SAXISCCTDATA[115] === 1'bz) || SAXISCCTDATA_delay[115]; // rv 1 + assign SAXISCCTDATA_in[116] = (SAXISCCTDATA[116] === 1'bz) || SAXISCCTDATA_delay[116]; // rv 1 + assign SAXISCCTDATA_in[117] = (SAXISCCTDATA[117] === 1'bz) || SAXISCCTDATA_delay[117]; // rv 1 + assign SAXISCCTDATA_in[118] = (SAXISCCTDATA[118] === 1'bz) || SAXISCCTDATA_delay[118]; // rv 1 + assign SAXISCCTDATA_in[119] = (SAXISCCTDATA[119] === 1'bz) || SAXISCCTDATA_delay[119]; // rv 1 + assign SAXISCCTDATA_in[11] = (SAXISCCTDATA[11] === 1'bz) || SAXISCCTDATA_delay[11]; // rv 1 + assign SAXISCCTDATA_in[120] = (SAXISCCTDATA[120] === 1'bz) || SAXISCCTDATA_delay[120]; // rv 1 + assign SAXISCCTDATA_in[121] = (SAXISCCTDATA[121] === 1'bz) || SAXISCCTDATA_delay[121]; // rv 1 + assign SAXISCCTDATA_in[122] = (SAXISCCTDATA[122] === 1'bz) || SAXISCCTDATA_delay[122]; // rv 1 + assign SAXISCCTDATA_in[123] = (SAXISCCTDATA[123] === 1'bz) || SAXISCCTDATA_delay[123]; // rv 1 + assign SAXISCCTDATA_in[124] = (SAXISCCTDATA[124] === 1'bz) || SAXISCCTDATA_delay[124]; // rv 1 + assign SAXISCCTDATA_in[125] = (SAXISCCTDATA[125] === 1'bz) || SAXISCCTDATA_delay[125]; // rv 1 + assign SAXISCCTDATA_in[126] = (SAXISCCTDATA[126] === 1'bz) || SAXISCCTDATA_delay[126]; // rv 1 + assign SAXISCCTDATA_in[127] = (SAXISCCTDATA[127] === 1'bz) || SAXISCCTDATA_delay[127]; // rv 1 + assign SAXISCCTDATA_in[128] = (SAXISCCTDATA[128] === 1'bz) || SAXISCCTDATA_delay[128]; // rv 1 + assign SAXISCCTDATA_in[129] = (SAXISCCTDATA[129] === 1'bz) || SAXISCCTDATA_delay[129]; // rv 1 + assign SAXISCCTDATA_in[12] = (SAXISCCTDATA[12] === 1'bz) || SAXISCCTDATA_delay[12]; // rv 1 + assign SAXISCCTDATA_in[130] = (SAXISCCTDATA[130] === 1'bz) || SAXISCCTDATA_delay[130]; // rv 1 + assign SAXISCCTDATA_in[131] = (SAXISCCTDATA[131] === 1'bz) || SAXISCCTDATA_delay[131]; // rv 1 + assign SAXISCCTDATA_in[132] = (SAXISCCTDATA[132] === 1'bz) || SAXISCCTDATA_delay[132]; // rv 1 + assign SAXISCCTDATA_in[133] = (SAXISCCTDATA[133] === 1'bz) || SAXISCCTDATA_delay[133]; // rv 1 + assign SAXISCCTDATA_in[134] = (SAXISCCTDATA[134] === 1'bz) || SAXISCCTDATA_delay[134]; // rv 1 + assign SAXISCCTDATA_in[135] = (SAXISCCTDATA[135] === 1'bz) || SAXISCCTDATA_delay[135]; // rv 1 + assign SAXISCCTDATA_in[136] = (SAXISCCTDATA[136] === 1'bz) || SAXISCCTDATA_delay[136]; // rv 1 + assign SAXISCCTDATA_in[137] = (SAXISCCTDATA[137] === 1'bz) || SAXISCCTDATA_delay[137]; // rv 1 + assign SAXISCCTDATA_in[138] = (SAXISCCTDATA[138] === 1'bz) || SAXISCCTDATA_delay[138]; // rv 1 + assign SAXISCCTDATA_in[139] = (SAXISCCTDATA[139] === 1'bz) || SAXISCCTDATA_delay[139]; // rv 1 + assign SAXISCCTDATA_in[13] = (SAXISCCTDATA[13] === 1'bz) || SAXISCCTDATA_delay[13]; // rv 1 + assign SAXISCCTDATA_in[140] = (SAXISCCTDATA[140] === 1'bz) || SAXISCCTDATA_delay[140]; // rv 1 + assign SAXISCCTDATA_in[141] = (SAXISCCTDATA[141] === 1'bz) || SAXISCCTDATA_delay[141]; // rv 1 + assign SAXISCCTDATA_in[142] = (SAXISCCTDATA[142] === 1'bz) || SAXISCCTDATA_delay[142]; // rv 1 + assign SAXISCCTDATA_in[143] = (SAXISCCTDATA[143] === 1'bz) || SAXISCCTDATA_delay[143]; // rv 1 + assign SAXISCCTDATA_in[144] = (SAXISCCTDATA[144] === 1'bz) || SAXISCCTDATA_delay[144]; // rv 1 + assign SAXISCCTDATA_in[145] = (SAXISCCTDATA[145] === 1'bz) || SAXISCCTDATA_delay[145]; // rv 1 + assign SAXISCCTDATA_in[146] = (SAXISCCTDATA[146] === 1'bz) || SAXISCCTDATA_delay[146]; // rv 1 + assign SAXISCCTDATA_in[147] = (SAXISCCTDATA[147] === 1'bz) || SAXISCCTDATA_delay[147]; // rv 1 + assign SAXISCCTDATA_in[148] = (SAXISCCTDATA[148] === 1'bz) || SAXISCCTDATA_delay[148]; // rv 1 + assign SAXISCCTDATA_in[149] = (SAXISCCTDATA[149] === 1'bz) || SAXISCCTDATA_delay[149]; // rv 1 + assign SAXISCCTDATA_in[14] = (SAXISCCTDATA[14] === 1'bz) || SAXISCCTDATA_delay[14]; // rv 1 + assign SAXISCCTDATA_in[150] = (SAXISCCTDATA[150] === 1'bz) || SAXISCCTDATA_delay[150]; // rv 1 + assign SAXISCCTDATA_in[151] = (SAXISCCTDATA[151] === 1'bz) || SAXISCCTDATA_delay[151]; // rv 1 + assign SAXISCCTDATA_in[152] = (SAXISCCTDATA[152] === 1'bz) || SAXISCCTDATA_delay[152]; // rv 1 + assign SAXISCCTDATA_in[153] = (SAXISCCTDATA[153] === 1'bz) || SAXISCCTDATA_delay[153]; // rv 1 + assign SAXISCCTDATA_in[154] = (SAXISCCTDATA[154] === 1'bz) || SAXISCCTDATA_delay[154]; // rv 1 + assign SAXISCCTDATA_in[155] = (SAXISCCTDATA[155] === 1'bz) || SAXISCCTDATA_delay[155]; // rv 1 + assign SAXISCCTDATA_in[156] = (SAXISCCTDATA[156] === 1'bz) || SAXISCCTDATA_delay[156]; // rv 1 + assign SAXISCCTDATA_in[157] = (SAXISCCTDATA[157] === 1'bz) || SAXISCCTDATA_delay[157]; // rv 1 + assign SAXISCCTDATA_in[158] = (SAXISCCTDATA[158] === 1'bz) || SAXISCCTDATA_delay[158]; // rv 1 + assign SAXISCCTDATA_in[159] = (SAXISCCTDATA[159] === 1'bz) || SAXISCCTDATA_delay[159]; // rv 1 + assign SAXISCCTDATA_in[15] = (SAXISCCTDATA[15] === 1'bz) || SAXISCCTDATA_delay[15]; // rv 1 + assign SAXISCCTDATA_in[160] = (SAXISCCTDATA[160] === 1'bz) || SAXISCCTDATA_delay[160]; // rv 1 + assign SAXISCCTDATA_in[161] = (SAXISCCTDATA[161] === 1'bz) || SAXISCCTDATA_delay[161]; // rv 1 + assign SAXISCCTDATA_in[162] = (SAXISCCTDATA[162] === 1'bz) || SAXISCCTDATA_delay[162]; // rv 1 + assign SAXISCCTDATA_in[163] = (SAXISCCTDATA[163] === 1'bz) || SAXISCCTDATA_delay[163]; // rv 1 + assign SAXISCCTDATA_in[164] = (SAXISCCTDATA[164] === 1'bz) || SAXISCCTDATA_delay[164]; // rv 1 + assign SAXISCCTDATA_in[165] = (SAXISCCTDATA[165] === 1'bz) || SAXISCCTDATA_delay[165]; // rv 1 + assign SAXISCCTDATA_in[166] = (SAXISCCTDATA[166] === 1'bz) || SAXISCCTDATA_delay[166]; // rv 1 + assign SAXISCCTDATA_in[167] = (SAXISCCTDATA[167] === 1'bz) || SAXISCCTDATA_delay[167]; // rv 1 + assign SAXISCCTDATA_in[168] = (SAXISCCTDATA[168] === 1'bz) || SAXISCCTDATA_delay[168]; // rv 1 + assign SAXISCCTDATA_in[169] = (SAXISCCTDATA[169] === 1'bz) || SAXISCCTDATA_delay[169]; // rv 1 + assign SAXISCCTDATA_in[16] = (SAXISCCTDATA[16] === 1'bz) || SAXISCCTDATA_delay[16]; // rv 1 + assign SAXISCCTDATA_in[170] = (SAXISCCTDATA[170] === 1'bz) || SAXISCCTDATA_delay[170]; // rv 1 + assign SAXISCCTDATA_in[171] = (SAXISCCTDATA[171] === 1'bz) || SAXISCCTDATA_delay[171]; // rv 1 + assign SAXISCCTDATA_in[172] = (SAXISCCTDATA[172] === 1'bz) || SAXISCCTDATA_delay[172]; // rv 1 + assign SAXISCCTDATA_in[173] = (SAXISCCTDATA[173] === 1'bz) || SAXISCCTDATA_delay[173]; // rv 1 + assign SAXISCCTDATA_in[174] = (SAXISCCTDATA[174] === 1'bz) || SAXISCCTDATA_delay[174]; // rv 1 + assign SAXISCCTDATA_in[175] = (SAXISCCTDATA[175] === 1'bz) || SAXISCCTDATA_delay[175]; // rv 1 + assign SAXISCCTDATA_in[176] = (SAXISCCTDATA[176] === 1'bz) || SAXISCCTDATA_delay[176]; // rv 1 + assign SAXISCCTDATA_in[177] = (SAXISCCTDATA[177] === 1'bz) || SAXISCCTDATA_delay[177]; // rv 1 + assign SAXISCCTDATA_in[178] = (SAXISCCTDATA[178] === 1'bz) || SAXISCCTDATA_delay[178]; // rv 1 + assign SAXISCCTDATA_in[179] = (SAXISCCTDATA[179] === 1'bz) || SAXISCCTDATA_delay[179]; // rv 1 + assign SAXISCCTDATA_in[17] = (SAXISCCTDATA[17] === 1'bz) || SAXISCCTDATA_delay[17]; // rv 1 + assign SAXISCCTDATA_in[180] = (SAXISCCTDATA[180] === 1'bz) || SAXISCCTDATA_delay[180]; // rv 1 + assign SAXISCCTDATA_in[181] = (SAXISCCTDATA[181] === 1'bz) || SAXISCCTDATA_delay[181]; // rv 1 + assign SAXISCCTDATA_in[182] = (SAXISCCTDATA[182] === 1'bz) || SAXISCCTDATA_delay[182]; // rv 1 + assign SAXISCCTDATA_in[183] = (SAXISCCTDATA[183] === 1'bz) || SAXISCCTDATA_delay[183]; // rv 1 + assign SAXISCCTDATA_in[184] = (SAXISCCTDATA[184] === 1'bz) || SAXISCCTDATA_delay[184]; // rv 1 + assign SAXISCCTDATA_in[185] = (SAXISCCTDATA[185] === 1'bz) || SAXISCCTDATA_delay[185]; // rv 1 + assign SAXISCCTDATA_in[186] = (SAXISCCTDATA[186] === 1'bz) || SAXISCCTDATA_delay[186]; // rv 1 + assign SAXISCCTDATA_in[187] = (SAXISCCTDATA[187] === 1'bz) || SAXISCCTDATA_delay[187]; // rv 1 + assign SAXISCCTDATA_in[188] = (SAXISCCTDATA[188] === 1'bz) || SAXISCCTDATA_delay[188]; // rv 1 + assign SAXISCCTDATA_in[189] = (SAXISCCTDATA[189] === 1'bz) || SAXISCCTDATA_delay[189]; // rv 1 + assign SAXISCCTDATA_in[18] = (SAXISCCTDATA[18] === 1'bz) || SAXISCCTDATA_delay[18]; // rv 1 + assign SAXISCCTDATA_in[190] = (SAXISCCTDATA[190] === 1'bz) || SAXISCCTDATA_delay[190]; // rv 1 + assign SAXISCCTDATA_in[191] = (SAXISCCTDATA[191] === 1'bz) || SAXISCCTDATA_delay[191]; // rv 1 + assign SAXISCCTDATA_in[192] = (SAXISCCTDATA[192] === 1'bz) || SAXISCCTDATA_delay[192]; // rv 1 + assign SAXISCCTDATA_in[193] = (SAXISCCTDATA[193] === 1'bz) || SAXISCCTDATA_delay[193]; // rv 1 + assign SAXISCCTDATA_in[194] = (SAXISCCTDATA[194] === 1'bz) || SAXISCCTDATA_delay[194]; // rv 1 + assign SAXISCCTDATA_in[195] = (SAXISCCTDATA[195] === 1'bz) || SAXISCCTDATA_delay[195]; // rv 1 + assign SAXISCCTDATA_in[196] = (SAXISCCTDATA[196] === 1'bz) || SAXISCCTDATA_delay[196]; // rv 1 + assign SAXISCCTDATA_in[197] = (SAXISCCTDATA[197] === 1'bz) || SAXISCCTDATA_delay[197]; // rv 1 + assign SAXISCCTDATA_in[198] = (SAXISCCTDATA[198] === 1'bz) || SAXISCCTDATA_delay[198]; // rv 1 + assign SAXISCCTDATA_in[199] = (SAXISCCTDATA[199] === 1'bz) || SAXISCCTDATA_delay[199]; // rv 1 + assign SAXISCCTDATA_in[19] = (SAXISCCTDATA[19] === 1'bz) || SAXISCCTDATA_delay[19]; // rv 1 + assign SAXISCCTDATA_in[1] = (SAXISCCTDATA[1] === 1'bz) || SAXISCCTDATA_delay[1]; // rv 1 + assign SAXISCCTDATA_in[200] = (SAXISCCTDATA[200] === 1'bz) || SAXISCCTDATA_delay[200]; // rv 1 + assign SAXISCCTDATA_in[201] = (SAXISCCTDATA[201] === 1'bz) || SAXISCCTDATA_delay[201]; // rv 1 + assign SAXISCCTDATA_in[202] = (SAXISCCTDATA[202] === 1'bz) || SAXISCCTDATA_delay[202]; // rv 1 + assign SAXISCCTDATA_in[203] = (SAXISCCTDATA[203] === 1'bz) || SAXISCCTDATA_delay[203]; // rv 1 + assign SAXISCCTDATA_in[204] = (SAXISCCTDATA[204] === 1'bz) || SAXISCCTDATA_delay[204]; // rv 1 + assign SAXISCCTDATA_in[205] = (SAXISCCTDATA[205] === 1'bz) || SAXISCCTDATA_delay[205]; // rv 1 + assign SAXISCCTDATA_in[206] = (SAXISCCTDATA[206] === 1'bz) || SAXISCCTDATA_delay[206]; // rv 1 + assign SAXISCCTDATA_in[207] = (SAXISCCTDATA[207] === 1'bz) || SAXISCCTDATA_delay[207]; // rv 1 + assign SAXISCCTDATA_in[208] = (SAXISCCTDATA[208] === 1'bz) || SAXISCCTDATA_delay[208]; // rv 1 + assign SAXISCCTDATA_in[209] = (SAXISCCTDATA[209] === 1'bz) || SAXISCCTDATA_delay[209]; // rv 1 + assign SAXISCCTDATA_in[20] = (SAXISCCTDATA[20] === 1'bz) || SAXISCCTDATA_delay[20]; // rv 1 + assign SAXISCCTDATA_in[210] = (SAXISCCTDATA[210] === 1'bz) || SAXISCCTDATA_delay[210]; // rv 1 + assign SAXISCCTDATA_in[211] = (SAXISCCTDATA[211] === 1'bz) || SAXISCCTDATA_delay[211]; // rv 1 + assign SAXISCCTDATA_in[212] = (SAXISCCTDATA[212] === 1'bz) || SAXISCCTDATA_delay[212]; // rv 1 + assign SAXISCCTDATA_in[213] = (SAXISCCTDATA[213] === 1'bz) || SAXISCCTDATA_delay[213]; // rv 1 + assign SAXISCCTDATA_in[214] = (SAXISCCTDATA[214] === 1'bz) || SAXISCCTDATA_delay[214]; // rv 1 + assign SAXISCCTDATA_in[215] = (SAXISCCTDATA[215] === 1'bz) || SAXISCCTDATA_delay[215]; // rv 1 + assign SAXISCCTDATA_in[216] = (SAXISCCTDATA[216] === 1'bz) || SAXISCCTDATA_delay[216]; // rv 1 + assign SAXISCCTDATA_in[217] = (SAXISCCTDATA[217] === 1'bz) || SAXISCCTDATA_delay[217]; // rv 1 + assign SAXISCCTDATA_in[218] = (SAXISCCTDATA[218] === 1'bz) || SAXISCCTDATA_delay[218]; // rv 1 + assign SAXISCCTDATA_in[219] = (SAXISCCTDATA[219] === 1'bz) || SAXISCCTDATA_delay[219]; // rv 1 + assign SAXISCCTDATA_in[21] = (SAXISCCTDATA[21] === 1'bz) || SAXISCCTDATA_delay[21]; // rv 1 + assign SAXISCCTDATA_in[220] = (SAXISCCTDATA[220] === 1'bz) || SAXISCCTDATA_delay[220]; // rv 1 + assign SAXISCCTDATA_in[221] = (SAXISCCTDATA[221] === 1'bz) || SAXISCCTDATA_delay[221]; // rv 1 + assign SAXISCCTDATA_in[222] = (SAXISCCTDATA[222] === 1'bz) || SAXISCCTDATA_delay[222]; // rv 1 + assign SAXISCCTDATA_in[223] = (SAXISCCTDATA[223] === 1'bz) || SAXISCCTDATA_delay[223]; // rv 1 + assign SAXISCCTDATA_in[224] = (SAXISCCTDATA[224] === 1'bz) || SAXISCCTDATA_delay[224]; // rv 1 + assign SAXISCCTDATA_in[225] = (SAXISCCTDATA[225] === 1'bz) || SAXISCCTDATA_delay[225]; // rv 1 + assign SAXISCCTDATA_in[226] = (SAXISCCTDATA[226] === 1'bz) || SAXISCCTDATA_delay[226]; // rv 1 + assign SAXISCCTDATA_in[227] = (SAXISCCTDATA[227] === 1'bz) || SAXISCCTDATA_delay[227]; // rv 1 + assign SAXISCCTDATA_in[228] = (SAXISCCTDATA[228] === 1'bz) || SAXISCCTDATA_delay[228]; // rv 1 + assign SAXISCCTDATA_in[229] = (SAXISCCTDATA[229] === 1'bz) || SAXISCCTDATA_delay[229]; // rv 1 + assign SAXISCCTDATA_in[22] = (SAXISCCTDATA[22] === 1'bz) || SAXISCCTDATA_delay[22]; // rv 1 + assign SAXISCCTDATA_in[230] = (SAXISCCTDATA[230] === 1'bz) || SAXISCCTDATA_delay[230]; // rv 1 + assign SAXISCCTDATA_in[231] = (SAXISCCTDATA[231] === 1'bz) || SAXISCCTDATA_delay[231]; // rv 1 + assign SAXISCCTDATA_in[232] = (SAXISCCTDATA[232] === 1'bz) || SAXISCCTDATA_delay[232]; // rv 1 + assign SAXISCCTDATA_in[233] = (SAXISCCTDATA[233] === 1'bz) || SAXISCCTDATA_delay[233]; // rv 1 + assign SAXISCCTDATA_in[234] = (SAXISCCTDATA[234] === 1'bz) || SAXISCCTDATA_delay[234]; // rv 1 + assign SAXISCCTDATA_in[235] = (SAXISCCTDATA[235] === 1'bz) || SAXISCCTDATA_delay[235]; // rv 1 + assign SAXISCCTDATA_in[236] = (SAXISCCTDATA[236] === 1'bz) || SAXISCCTDATA_delay[236]; // rv 1 + assign SAXISCCTDATA_in[237] = (SAXISCCTDATA[237] === 1'bz) || SAXISCCTDATA_delay[237]; // rv 1 + assign SAXISCCTDATA_in[238] = (SAXISCCTDATA[238] === 1'bz) || SAXISCCTDATA_delay[238]; // rv 1 + assign SAXISCCTDATA_in[239] = (SAXISCCTDATA[239] === 1'bz) || SAXISCCTDATA_delay[239]; // rv 1 + assign SAXISCCTDATA_in[23] = (SAXISCCTDATA[23] === 1'bz) || SAXISCCTDATA_delay[23]; // rv 1 + assign SAXISCCTDATA_in[240] = (SAXISCCTDATA[240] === 1'bz) || SAXISCCTDATA_delay[240]; // rv 1 + assign SAXISCCTDATA_in[241] = (SAXISCCTDATA[241] === 1'bz) || SAXISCCTDATA_delay[241]; // rv 1 + assign SAXISCCTDATA_in[242] = (SAXISCCTDATA[242] === 1'bz) || SAXISCCTDATA_delay[242]; // rv 1 + assign SAXISCCTDATA_in[243] = (SAXISCCTDATA[243] === 1'bz) || SAXISCCTDATA_delay[243]; // rv 1 + assign SAXISCCTDATA_in[244] = (SAXISCCTDATA[244] === 1'bz) || SAXISCCTDATA_delay[244]; // rv 1 + assign SAXISCCTDATA_in[245] = (SAXISCCTDATA[245] === 1'bz) || SAXISCCTDATA_delay[245]; // rv 1 + assign SAXISCCTDATA_in[246] = (SAXISCCTDATA[246] === 1'bz) || SAXISCCTDATA_delay[246]; // rv 1 + assign SAXISCCTDATA_in[247] = (SAXISCCTDATA[247] === 1'bz) || SAXISCCTDATA_delay[247]; // rv 1 + assign SAXISCCTDATA_in[248] = (SAXISCCTDATA[248] === 1'bz) || SAXISCCTDATA_delay[248]; // rv 1 + assign SAXISCCTDATA_in[249] = (SAXISCCTDATA[249] === 1'bz) || SAXISCCTDATA_delay[249]; // rv 1 + assign SAXISCCTDATA_in[24] = (SAXISCCTDATA[24] === 1'bz) || SAXISCCTDATA_delay[24]; // rv 1 + assign SAXISCCTDATA_in[250] = (SAXISCCTDATA[250] === 1'bz) || SAXISCCTDATA_delay[250]; // rv 1 + assign SAXISCCTDATA_in[251] = (SAXISCCTDATA[251] === 1'bz) || SAXISCCTDATA_delay[251]; // rv 1 + assign SAXISCCTDATA_in[252] = (SAXISCCTDATA[252] === 1'bz) || SAXISCCTDATA_delay[252]; // rv 1 + assign SAXISCCTDATA_in[253] = (SAXISCCTDATA[253] === 1'bz) || SAXISCCTDATA_delay[253]; // rv 1 + assign SAXISCCTDATA_in[254] = (SAXISCCTDATA[254] === 1'bz) || SAXISCCTDATA_delay[254]; // rv 1 + assign SAXISCCTDATA_in[255] = (SAXISCCTDATA[255] === 1'bz) || SAXISCCTDATA_delay[255]; // rv 1 + assign SAXISCCTDATA_in[25] = (SAXISCCTDATA[25] === 1'bz) || SAXISCCTDATA_delay[25]; // rv 1 + assign SAXISCCTDATA_in[26] = (SAXISCCTDATA[26] === 1'bz) || SAXISCCTDATA_delay[26]; // rv 1 + assign SAXISCCTDATA_in[27] = (SAXISCCTDATA[27] === 1'bz) || SAXISCCTDATA_delay[27]; // rv 1 + assign SAXISCCTDATA_in[28] = (SAXISCCTDATA[28] === 1'bz) || SAXISCCTDATA_delay[28]; // rv 1 + assign SAXISCCTDATA_in[29] = (SAXISCCTDATA[29] === 1'bz) || SAXISCCTDATA_delay[29]; // rv 1 + assign SAXISCCTDATA_in[2] = (SAXISCCTDATA[2] === 1'bz) || SAXISCCTDATA_delay[2]; // rv 1 + assign SAXISCCTDATA_in[30] = (SAXISCCTDATA[30] === 1'bz) || SAXISCCTDATA_delay[30]; // rv 1 + assign SAXISCCTDATA_in[31] = (SAXISCCTDATA[31] === 1'bz) || SAXISCCTDATA_delay[31]; // rv 1 + assign SAXISCCTDATA_in[32] = (SAXISCCTDATA[32] === 1'bz) || SAXISCCTDATA_delay[32]; // rv 1 + assign SAXISCCTDATA_in[33] = (SAXISCCTDATA[33] === 1'bz) || SAXISCCTDATA_delay[33]; // rv 1 + assign SAXISCCTDATA_in[34] = (SAXISCCTDATA[34] === 1'bz) || SAXISCCTDATA_delay[34]; // rv 1 + assign SAXISCCTDATA_in[35] = (SAXISCCTDATA[35] === 1'bz) || SAXISCCTDATA_delay[35]; // rv 1 + assign SAXISCCTDATA_in[36] = (SAXISCCTDATA[36] === 1'bz) || SAXISCCTDATA_delay[36]; // rv 1 + assign SAXISCCTDATA_in[37] = (SAXISCCTDATA[37] === 1'bz) || SAXISCCTDATA_delay[37]; // rv 1 + assign SAXISCCTDATA_in[38] = (SAXISCCTDATA[38] === 1'bz) || SAXISCCTDATA_delay[38]; // rv 1 + assign SAXISCCTDATA_in[39] = (SAXISCCTDATA[39] === 1'bz) || SAXISCCTDATA_delay[39]; // rv 1 + assign SAXISCCTDATA_in[3] = (SAXISCCTDATA[3] === 1'bz) || SAXISCCTDATA_delay[3]; // rv 1 + assign SAXISCCTDATA_in[40] = (SAXISCCTDATA[40] === 1'bz) || SAXISCCTDATA_delay[40]; // rv 1 + assign SAXISCCTDATA_in[41] = (SAXISCCTDATA[41] === 1'bz) || SAXISCCTDATA_delay[41]; // rv 1 + assign SAXISCCTDATA_in[42] = (SAXISCCTDATA[42] === 1'bz) || SAXISCCTDATA_delay[42]; // rv 1 + assign SAXISCCTDATA_in[43] = (SAXISCCTDATA[43] === 1'bz) || SAXISCCTDATA_delay[43]; // rv 1 + assign SAXISCCTDATA_in[44] = (SAXISCCTDATA[44] === 1'bz) || SAXISCCTDATA_delay[44]; // rv 1 + assign SAXISCCTDATA_in[45] = (SAXISCCTDATA[45] === 1'bz) || SAXISCCTDATA_delay[45]; // rv 1 + assign SAXISCCTDATA_in[46] = (SAXISCCTDATA[46] === 1'bz) || SAXISCCTDATA_delay[46]; // rv 1 + assign SAXISCCTDATA_in[47] = (SAXISCCTDATA[47] === 1'bz) || SAXISCCTDATA_delay[47]; // rv 1 + assign SAXISCCTDATA_in[48] = (SAXISCCTDATA[48] === 1'bz) || SAXISCCTDATA_delay[48]; // rv 1 + assign SAXISCCTDATA_in[49] = (SAXISCCTDATA[49] === 1'bz) || SAXISCCTDATA_delay[49]; // rv 1 + assign SAXISCCTDATA_in[4] = (SAXISCCTDATA[4] === 1'bz) || SAXISCCTDATA_delay[4]; // rv 1 + assign SAXISCCTDATA_in[50] = (SAXISCCTDATA[50] === 1'bz) || SAXISCCTDATA_delay[50]; // rv 1 + assign SAXISCCTDATA_in[51] = (SAXISCCTDATA[51] === 1'bz) || SAXISCCTDATA_delay[51]; // rv 1 + assign SAXISCCTDATA_in[52] = (SAXISCCTDATA[52] === 1'bz) || SAXISCCTDATA_delay[52]; // rv 1 + assign SAXISCCTDATA_in[53] = (SAXISCCTDATA[53] === 1'bz) || SAXISCCTDATA_delay[53]; // rv 1 + assign SAXISCCTDATA_in[54] = (SAXISCCTDATA[54] === 1'bz) || SAXISCCTDATA_delay[54]; // rv 1 + assign SAXISCCTDATA_in[55] = (SAXISCCTDATA[55] === 1'bz) || SAXISCCTDATA_delay[55]; // rv 1 + assign SAXISCCTDATA_in[56] = (SAXISCCTDATA[56] === 1'bz) || SAXISCCTDATA_delay[56]; // rv 1 + assign SAXISCCTDATA_in[57] = (SAXISCCTDATA[57] === 1'bz) || SAXISCCTDATA_delay[57]; // rv 1 + assign SAXISCCTDATA_in[58] = (SAXISCCTDATA[58] === 1'bz) || SAXISCCTDATA_delay[58]; // rv 1 + assign SAXISCCTDATA_in[59] = (SAXISCCTDATA[59] === 1'bz) || SAXISCCTDATA_delay[59]; // rv 1 + assign SAXISCCTDATA_in[5] = (SAXISCCTDATA[5] === 1'bz) || SAXISCCTDATA_delay[5]; // rv 1 + assign SAXISCCTDATA_in[60] = (SAXISCCTDATA[60] === 1'bz) || SAXISCCTDATA_delay[60]; // rv 1 + assign SAXISCCTDATA_in[61] = (SAXISCCTDATA[61] === 1'bz) || SAXISCCTDATA_delay[61]; // rv 1 + assign SAXISCCTDATA_in[62] = (SAXISCCTDATA[62] === 1'bz) || SAXISCCTDATA_delay[62]; // rv 1 + assign SAXISCCTDATA_in[63] = (SAXISCCTDATA[63] === 1'bz) || SAXISCCTDATA_delay[63]; // rv 1 + assign SAXISCCTDATA_in[64] = (SAXISCCTDATA[64] === 1'bz) || SAXISCCTDATA_delay[64]; // rv 1 + assign SAXISCCTDATA_in[65] = (SAXISCCTDATA[65] === 1'bz) || SAXISCCTDATA_delay[65]; // rv 1 + assign SAXISCCTDATA_in[66] = (SAXISCCTDATA[66] === 1'bz) || SAXISCCTDATA_delay[66]; // rv 1 + assign SAXISCCTDATA_in[67] = (SAXISCCTDATA[67] === 1'bz) || SAXISCCTDATA_delay[67]; // rv 1 + assign SAXISCCTDATA_in[68] = (SAXISCCTDATA[68] === 1'bz) || SAXISCCTDATA_delay[68]; // rv 1 + assign SAXISCCTDATA_in[69] = (SAXISCCTDATA[69] === 1'bz) || SAXISCCTDATA_delay[69]; // rv 1 + assign SAXISCCTDATA_in[6] = (SAXISCCTDATA[6] === 1'bz) || SAXISCCTDATA_delay[6]; // rv 1 + assign SAXISCCTDATA_in[70] = (SAXISCCTDATA[70] === 1'bz) || SAXISCCTDATA_delay[70]; // rv 1 + assign SAXISCCTDATA_in[71] = (SAXISCCTDATA[71] === 1'bz) || SAXISCCTDATA_delay[71]; // rv 1 + assign SAXISCCTDATA_in[72] = (SAXISCCTDATA[72] === 1'bz) || SAXISCCTDATA_delay[72]; // rv 1 + assign SAXISCCTDATA_in[73] = (SAXISCCTDATA[73] === 1'bz) || SAXISCCTDATA_delay[73]; // rv 1 + assign SAXISCCTDATA_in[74] = (SAXISCCTDATA[74] === 1'bz) || SAXISCCTDATA_delay[74]; // rv 1 + assign SAXISCCTDATA_in[75] = (SAXISCCTDATA[75] === 1'bz) || SAXISCCTDATA_delay[75]; // rv 1 + assign SAXISCCTDATA_in[76] = (SAXISCCTDATA[76] === 1'bz) || SAXISCCTDATA_delay[76]; // rv 1 + assign SAXISCCTDATA_in[77] = (SAXISCCTDATA[77] === 1'bz) || SAXISCCTDATA_delay[77]; // rv 1 + assign SAXISCCTDATA_in[78] = (SAXISCCTDATA[78] === 1'bz) || SAXISCCTDATA_delay[78]; // rv 1 + assign SAXISCCTDATA_in[79] = (SAXISCCTDATA[79] === 1'bz) || SAXISCCTDATA_delay[79]; // rv 1 + assign SAXISCCTDATA_in[7] = (SAXISCCTDATA[7] === 1'bz) || SAXISCCTDATA_delay[7]; // rv 1 + assign SAXISCCTDATA_in[80] = (SAXISCCTDATA[80] === 1'bz) || SAXISCCTDATA_delay[80]; // rv 1 + assign SAXISCCTDATA_in[81] = (SAXISCCTDATA[81] === 1'bz) || SAXISCCTDATA_delay[81]; // rv 1 + assign SAXISCCTDATA_in[82] = (SAXISCCTDATA[82] === 1'bz) || SAXISCCTDATA_delay[82]; // rv 1 + assign SAXISCCTDATA_in[83] = (SAXISCCTDATA[83] === 1'bz) || SAXISCCTDATA_delay[83]; // rv 1 + assign SAXISCCTDATA_in[84] = (SAXISCCTDATA[84] === 1'bz) || SAXISCCTDATA_delay[84]; // rv 1 + assign SAXISCCTDATA_in[85] = (SAXISCCTDATA[85] === 1'bz) || SAXISCCTDATA_delay[85]; // rv 1 + assign SAXISCCTDATA_in[86] = (SAXISCCTDATA[86] === 1'bz) || SAXISCCTDATA_delay[86]; // rv 1 + assign SAXISCCTDATA_in[87] = (SAXISCCTDATA[87] === 1'bz) || SAXISCCTDATA_delay[87]; // rv 1 + assign SAXISCCTDATA_in[88] = (SAXISCCTDATA[88] === 1'bz) || SAXISCCTDATA_delay[88]; // rv 1 + assign SAXISCCTDATA_in[89] = (SAXISCCTDATA[89] === 1'bz) || SAXISCCTDATA_delay[89]; // rv 1 + assign SAXISCCTDATA_in[8] = (SAXISCCTDATA[8] === 1'bz) || SAXISCCTDATA_delay[8]; // rv 1 + assign SAXISCCTDATA_in[90] = (SAXISCCTDATA[90] === 1'bz) || SAXISCCTDATA_delay[90]; // rv 1 + assign SAXISCCTDATA_in[91] = (SAXISCCTDATA[91] === 1'bz) || SAXISCCTDATA_delay[91]; // rv 1 + assign SAXISCCTDATA_in[92] = (SAXISCCTDATA[92] === 1'bz) || SAXISCCTDATA_delay[92]; // rv 1 + assign SAXISCCTDATA_in[93] = (SAXISCCTDATA[93] === 1'bz) || SAXISCCTDATA_delay[93]; // rv 1 + assign SAXISCCTDATA_in[94] = (SAXISCCTDATA[94] === 1'bz) || SAXISCCTDATA_delay[94]; // rv 1 + assign SAXISCCTDATA_in[95] = (SAXISCCTDATA[95] === 1'bz) || SAXISCCTDATA_delay[95]; // rv 1 + assign SAXISCCTDATA_in[96] = (SAXISCCTDATA[96] === 1'bz) || SAXISCCTDATA_delay[96]; // rv 1 + assign SAXISCCTDATA_in[97] = (SAXISCCTDATA[97] === 1'bz) || SAXISCCTDATA_delay[97]; // rv 1 + assign SAXISCCTDATA_in[98] = (SAXISCCTDATA[98] === 1'bz) || SAXISCCTDATA_delay[98]; // rv 1 + assign SAXISCCTDATA_in[99] = (SAXISCCTDATA[99] === 1'bz) || SAXISCCTDATA_delay[99]; // rv 1 + assign SAXISCCTDATA_in[9] = (SAXISCCTDATA[9] === 1'bz) || SAXISCCTDATA_delay[9]; // rv 1 + assign SAXISCCTKEEP_in[0] = (SAXISCCTKEEP[0] !== 1'bz) && SAXISCCTKEEP_delay[0]; // rv 0 + assign SAXISCCTKEEP_in[1] = (SAXISCCTKEEP[1] !== 1'bz) && SAXISCCTKEEP_delay[1]; // rv 0 + assign SAXISCCTKEEP_in[2] = (SAXISCCTKEEP[2] !== 1'bz) && SAXISCCTKEEP_delay[2]; // rv 0 + assign SAXISCCTKEEP_in[3] = (SAXISCCTKEEP[3] !== 1'bz) && SAXISCCTKEEP_delay[3]; // rv 0 + assign SAXISCCTKEEP_in[4] = (SAXISCCTKEEP[4] !== 1'bz) && SAXISCCTKEEP_delay[4]; // rv 0 + assign SAXISCCTKEEP_in[5] = (SAXISCCTKEEP[5] !== 1'bz) && SAXISCCTKEEP_delay[5]; // rv 0 + assign SAXISCCTKEEP_in[6] = (SAXISCCTKEEP[6] !== 1'bz) && SAXISCCTKEEP_delay[6]; // rv 0 + assign SAXISCCTKEEP_in[7] = (SAXISCCTKEEP[7] !== 1'bz) && SAXISCCTKEEP_delay[7]; // rv 0 + assign SAXISCCTLAST_in = (SAXISCCTLAST === 1'bz) || SAXISCCTLAST_delay; // rv 1 + assign SAXISCCTUSER_in[0] = (SAXISCCTUSER[0] === 1'bz) || SAXISCCTUSER_delay[0]; // rv 1 + assign SAXISCCTUSER_in[10] = (SAXISCCTUSER[10] === 1'bz) || SAXISCCTUSER_delay[10]; // rv 1 + assign SAXISCCTUSER_in[11] = (SAXISCCTUSER[11] === 1'bz) || SAXISCCTUSER_delay[11]; // rv 1 + assign SAXISCCTUSER_in[12] = (SAXISCCTUSER[12] === 1'bz) || SAXISCCTUSER_delay[12]; // rv 1 + assign SAXISCCTUSER_in[13] = (SAXISCCTUSER[13] === 1'bz) || SAXISCCTUSER_delay[13]; // rv 1 + assign SAXISCCTUSER_in[14] = (SAXISCCTUSER[14] === 1'bz) || SAXISCCTUSER_delay[14]; // rv 1 + assign SAXISCCTUSER_in[15] = (SAXISCCTUSER[15] === 1'bz) || SAXISCCTUSER_delay[15]; // rv 1 + assign SAXISCCTUSER_in[16] = (SAXISCCTUSER[16] === 1'bz) || SAXISCCTUSER_delay[16]; // rv 1 + assign SAXISCCTUSER_in[17] = (SAXISCCTUSER[17] === 1'bz) || SAXISCCTUSER_delay[17]; // rv 1 + assign SAXISCCTUSER_in[18] = (SAXISCCTUSER[18] === 1'bz) || SAXISCCTUSER_delay[18]; // rv 1 + assign SAXISCCTUSER_in[19] = (SAXISCCTUSER[19] === 1'bz) || SAXISCCTUSER_delay[19]; // rv 1 + assign SAXISCCTUSER_in[1] = (SAXISCCTUSER[1] === 1'bz) || SAXISCCTUSER_delay[1]; // rv 1 + assign SAXISCCTUSER_in[20] = (SAXISCCTUSER[20] === 1'bz) || SAXISCCTUSER_delay[20]; // rv 1 + assign SAXISCCTUSER_in[21] = (SAXISCCTUSER[21] === 1'bz) || SAXISCCTUSER_delay[21]; // rv 1 + assign SAXISCCTUSER_in[22] = (SAXISCCTUSER[22] === 1'bz) || SAXISCCTUSER_delay[22]; // rv 1 + assign SAXISCCTUSER_in[23] = (SAXISCCTUSER[23] === 1'bz) || SAXISCCTUSER_delay[23]; // rv 1 + assign SAXISCCTUSER_in[24] = (SAXISCCTUSER[24] === 1'bz) || SAXISCCTUSER_delay[24]; // rv 1 + assign SAXISCCTUSER_in[25] = (SAXISCCTUSER[25] === 1'bz) || SAXISCCTUSER_delay[25]; // rv 1 + assign SAXISCCTUSER_in[26] = (SAXISCCTUSER[26] === 1'bz) || SAXISCCTUSER_delay[26]; // rv 1 + assign SAXISCCTUSER_in[27] = (SAXISCCTUSER[27] === 1'bz) || SAXISCCTUSER_delay[27]; // rv 1 + assign SAXISCCTUSER_in[28] = (SAXISCCTUSER[28] === 1'bz) || SAXISCCTUSER_delay[28]; // rv 1 + assign SAXISCCTUSER_in[29] = (SAXISCCTUSER[29] === 1'bz) || SAXISCCTUSER_delay[29]; // rv 1 + assign SAXISCCTUSER_in[2] = (SAXISCCTUSER[2] === 1'bz) || SAXISCCTUSER_delay[2]; // rv 1 + assign SAXISCCTUSER_in[30] = (SAXISCCTUSER[30] === 1'bz) || SAXISCCTUSER_delay[30]; // rv 1 + assign SAXISCCTUSER_in[31] = (SAXISCCTUSER[31] === 1'bz) || SAXISCCTUSER_delay[31]; // rv 1 + assign SAXISCCTUSER_in[32] = (SAXISCCTUSER[32] === 1'bz) || SAXISCCTUSER_delay[32]; // rv 1 + assign SAXISCCTUSER_in[3] = (SAXISCCTUSER[3] === 1'bz) || SAXISCCTUSER_delay[3]; // rv 1 + assign SAXISCCTUSER_in[4] = (SAXISCCTUSER[4] === 1'bz) || SAXISCCTUSER_delay[4]; // rv 1 + assign SAXISCCTUSER_in[5] = (SAXISCCTUSER[5] === 1'bz) || SAXISCCTUSER_delay[5]; // rv 1 + assign SAXISCCTUSER_in[6] = (SAXISCCTUSER[6] === 1'bz) || SAXISCCTUSER_delay[6]; // rv 1 + assign SAXISCCTUSER_in[7] = (SAXISCCTUSER[7] === 1'bz) || SAXISCCTUSER_delay[7]; // rv 1 + assign SAXISCCTUSER_in[8] = (SAXISCCTUSER[8] === 1'bz) || SAXISCCTUSER_delay[8]; // rv 1 + assign SAXISCCTUSER_in[9] = (SAXISCCTUSER[9] === 1'bz) || SAXISCCTUSER_delay[9]; // rv 1 + assign SAXISCCTVALID_in = (SAXISCCTVALID !== 1'bz) && SAXISCCTVALID_delay; // rv 0 + assign SAXISRQTDATA_in[0] = (SAXISRQTDATA[0] === 1'bz) || SAXISRQTDATA_delay[0]; // rv 1 + assign SAXISRQTDATA_in[100] = (SAXISRQTDATA[100] === 1'bz) || SAXISRQTDATA_delay[100]; // rv 1 + assign SAXISRQTDATA_in[101] = (SAXISRQTDATA[101] === 1'bz) || SAXISRQTDATA_delay[101]; // rv 1 + assign SAXISRQTDATA_in[102] = (SAXISRQTDATA[102] === 1'bz) || SAXISRQTDATA_delay[102]; // rv 1 + assign SAXISRQTDATA_in[103] = (SAXISRQTDATA[103] === 1'bz) || SAXISRQTDATA_delay[103]; // rv 1 + assign SAXISRQTDATA_in[104] = (SAXISRQTDATA[104] === 1'bz) || SAXISRQTDATA_delay[104]; // rv 1 + assign SAXISRQTDATA_in[105] = (SAXISRQTDATA[105] === 1'bz) || SAXISRQTDATA_delay[105]; // rv 1 + assign SAXISRQTDATA_in[106] = (SAXISRQTDATA[106] === 1'bz) || SAXISRQTDATA_delay[106]; // rv 1 + assign SAXISRQTDATA_in[107] = (SAXISRQTDATA[107] === 1'bz) || SAXISRQTDATA_delay[107]; // rv 1 + assign SAXISRQTDATA_in[108] = (SAXISRQTDATA[108] === 1'bz) || SAXISRQTDATA_delay[108]; // rv 1 + assign SAXISRQTDATA_in[109] = (SAXISRQTDATA[109] === 1'bz) || SAXISRQTDATA_delay[109]; // rv 1 + assign SAXISRQTDATA_in[10] = (SAXISRQTDATA[10] === 1'bz) || SAXISRQTDATA_delay[10]; // rv 1 + assign SAXISRQTDATA_in[110] = (SAXISRQTDATA[110] === 1'bz) || SAXISRQTDATA_delay[110]; // rv 1 + assign SAXISRQTDATA_in[111] = (SAXISRQTDATA[111] === 1'bz) || SAXISRQTDATA_delay[111]; // rv 1 + assign SAXISRQTDATA_in[112] = (SAXISRQTDATA[112] === 1'bz) || SAXISRQTDATA_delay[112]; // rv 1 + assign SAXISRQTDATA_in[113] = (SAXISRQTDATA[113] === 1'bz) || SAXISRQTDATA_delay[113]; // rv 1 + assign SAXISRQTDATA_in[114] = (SAXISRQTDATA[114] === 1'bz) || SAXISRQTDATA_delay[114]; // rv 1 + assign SAXISRQTDATA_in[115] = (SAXISRQTDATA[115] === 1'bz) || SAXISRQTDATA_delay[115]; // rv 1 + assign SAXISRQTDATA_in[116] = (SAXISRQTDATA[116] === 1'bz) || SAXISRQTDATA_delay[116]; // rv 1 + assign SAXISRQTDATA_in[117] = (SAXISRQTDATA[117] === 1'bz) || SAXISRQTDATA_delay[117]; // rv 1 + assign SAXISRQTDATA_in[118] = (SAXISRQTDATA[118] === 1'bz) || SAXISRQTDATA_delay[118]; // rv 1 + assign SAXISRQTDATA_in[119] = (SAXISRQTDATA[119] === 1'bz) || SAXISRQTDATA_delay[119]; // rv 1 + assign SAXISRQTDATA_in[11] = (SAXISRQTDATA[11] === 1'bz) || SAXISRQTDATA_delay[11]; // rv 1 + assign SAXISRQTDATA_in[120] = (SAXISRQTDATA[120] === 1'bz) || SAXISRQTDATA_delay[120]; // rv 1 + assign SAXISRQTDATA_in[121] = (SAXISRQTDATA[121] === 1'bz) || SAXISRQTDATA_delay[121]; // rv 1 + assign SAXISRQTDATA_in[122] = (SAXISRQTDATA[122] === 1'bz) || SAXISRQTDATA_delay[122]; // rv 1 + assign SAXISRQTDATA_in[123] = (SAXISRQTDATA[123] === 1'bz) || SAXISRQTDATA_delay[123]; // rv 1 + assign SAXISRQTDATA_in[124] = (SAXISRQTDATA[124] === 1'bz) || SAXISRQTDATA_delay[124]; // rv 1 + assign SAXISRQTDATA_in[125] = (SAXISRQTDATA[125] === 1'bz) || SAXISRQTDATA_delay[125]; // rv 1 + assign SAXISRQTDATA_in[126] = (SAXISRQTDATA[126] === 1'bz) || SAXISRQTDATA_delay[126]; // rv 1 + assign SAXISRQTDATA_in[127] = (SAXISRQTDATA[127] === 1'bz) || SAXISRQTDATA_delay[127]; // rv 1 + assign SAXISRQTDATA_in[128] = (SAXISRQTDATA[128] === 1'bz) || SAXISRQTDATA_delay[128]; // rv 1 + assign SAXISRQTDATA_in[129] = (SAXISRQTDATA[129] === 1'bz) || SAXISRQTDATA_delay[129]; // rv 1 + assign SAXISRQTDATA_in[12] = (SAXISRQTDATA[12] === 1'bz) || SAXISRQTDATA_delay[12]; // rv 1 + assign SAXISRQTDATA_in[130] = (SAXISRQTDATA[130] === 1'bz) || SAXISRQTDATA_delay[130]; // rv 1 + assign SAXISRQTDATA_in[131] = (SAXISRQTDATA[131] === 1'bz) || SAXISRQTDATA_delay[131]; // rv 1 + assign SAXISRQTDATA_in[132] = (SAXISRQTDATA[132] === 1'bz) || SAXISRQTDATA_delay[132]; // rv 1 + assign SAXISRQTDATA_in[133] = (SAXISRQTDATA[133] === 1'bz) || SAXISRQTDATA_delay[133]; // rv 1 + assign SAXISRQTDATA_in[134] = (SAXISRQTDATA[134] === 1'bz) || SAXISRQTDATA_delay[134]; // rv 1 + assign SAXISRQTDATA_in[135] = (SAXISRQTDATA[135] === 1'bz) || SAXISRQTDATA_delay[135]; // rv 1 + assign SAXISRQTDATA_in[136] = (SAXISRQTDATA[136] === 1'bz) || SAXISRQTDATA_delay[136]; // rv 1 + assign SAXISRQTDATA_in[137] = (SAXISRQTDATA[137] === 1'bz) || SAXISRQTDATA_delay[137]; // rv 1 + assign SAXISRQTDATA_in[138] = (SAXISRQTDATA[138] === 1'bz) || SAXISRQTDATA_delay[138]; // rv 1 + assign SAXISRQTDATA_in[139] = (SAXISRQTDATA[139] === 1'bz) || SAXISRQTDATA_delay[139]; // rv 1 + assign SAXISRQTDATA_in[13] = (SAXISRQTDATA[13] === 1'bz) || SAXISRQTDATA_delay[13]; // rv 1 + assign SAXISRQTDATA_in[140] = (SAXISRQTDATA[140] === 1'bz) || SAXISRQTDATA_delay[140]; // rv 1 + assign SAXISRQTDATA_in[141] = (SAXISRQTDATA[141] === 1'bz) || SAXISRQTDATA_delay[141]; // rv 1 + assign SAXISRQTDATA_in[142] = (SAXISRQTDATA[142] === 1'bz) || SAXISRQTDATA_delay[142]; // rv 1 + assign SAXISRQTDATA_in[143] = (SAXISRQTDATA[143] === 1'bz) || SAXISRQTDATA_delay[143]; // rv 1 + assign SAXISRQTDATA_in[144] = (SAXISRQTDATA[144] === 1'bz) || SAXISRQTDATA_delay[144]; // rv 1 + assign SAXISRQTDATA_in[145] = (SAXISRQTDATA[145] === 1'bz) || SAXISRQTDATA_delay[145]; // rv 1 + assign SAXISRQTDATA_in[146] = (SAXISRQTDATA[146] === 1'bz) || SAXISRQTDATA_delay[146]; // rv 1 + assign SAXISRQTDATA_in[147] = (SAXISRQTDATA[147] === 1'bz) || SAXISRQTDATA_delay[147]; // rv 1 + assign SAXISRQTDATA_in[148] = (SAXISRQTDATA[148] === 1'bz) || SAXISRQTDATA_delay[148]; // rv 1 + assign SAXISRQTDATA_in[149] = (SAXISRQTDATA[149] === 1'bz) || SAXISRQTDATA_delay[149]; // rv 1 + assign SAXISRQTDATA_in[14] = (SAXISRQTDATA[14] === 1'bz) || SAXISRQTDATA_delay[14]; // rv 1 + assign SAXISRQTDATA_in[150] = (SAXISRQTDATA[150] === 1'bz) || SAXISRQTDATA_delay[150]; // rv 1 + assign SAXISRQTDATA_in[151] = (SAXISRQTDATA[151] === 1'bz) || SAXISRQTDATA_delay[151]; // rv 1 + assign SAXISRQTDATA_in[152] = (SAXISRQTDATA[152] === 1'bz) || SAXISRQTDATA_delay[152]; // rv 1 + assign SAXISRQTDATA_in[153] = (SAXISRQTDATA[153] === 1'bz) || SAXISRQTDATA_delay[153]; // rv 1 + assign SAXISRQTDATA_in[154] = (SAXISRQTDATA[154] === 1'bz) || SAXISRQTDATA_delay[154]; // rv 1 + assign SAXISRQTDATA_in[155] = (SAXISRQTDATA[155] === 1'bz) || SAXISRQTDATA_delay[155]; // rv 1 + assign SAXISRQTDATA_in[156] = (SAXISRQTDATA[156] === 1'bz) || SAXISRQTDATA_delay[156]; // rv 1 + assign SAXISRQTDATA_in[157] = (SAXISRQTDATA[157] === 1'bz) || SAXISRQTDATA_delay[157]; // rv 1 + assign SAXISRQTDATA_in[158] = (SAXISRQTDATA[158] === 1'bz) || SAXISRQTDATA_delay[158]; // rv 1 + assign SAXISRQTDATA_in[159] = (SAXISRQTDATA[159] === 1'bz) || SAXISRQTDATA_delay[159]; // rv 1 + assign SAXISRQTDATA_in[15] = (SAXISRQTDATA[15] === 1'bz) || SAXISRQTDATA_delay[15]; // rv 1 + assign SAXISRQTDATA_in[160] = (SAXISRQTDATA[160] === 1'bz) || SAXISRQTDATA_delay[160]; // rv 1 + assign SAXISRQTDATA_in[161] = (SAXISRQTDATA[161] === 1'bz) || SAXISRQTDATA_delay[161]; // rv 1 + assign SAXISRQTDATA_in[162] = (SAXISRQTDATA[162] === 1'bz) || SAXISRQTDATA_delay[162]; // rv 1 + assign SAXISRQTDATA_in[163] = (SAXISRQTDATA[163] === 1'bz) || SAXISRQTDATA_delay[163]; // rv 1 + assign SAXISRQTDATA_in[164] = (SAXISRQTDATA[164] === 1'bz) || SAXISRQTDATA_delay[164]; // rv 1 + assign SAXISRQTDATA_in[165] = (SAXISRQTDATA[165] === 1'bz) || SAXISRQTDATA_delay[165]; // rv 1 + assign SAXISRQTDATA_in[166] = (SAXISRQTDATA[166] === 1'bz) || SAXISRQTDATA_delay[166]; // rv 1 + assign SAXISRQTDATA_in[167] = (SAXISRQTDATA[167] === 1'bz) || SAXISRQTDATA_delay[167]; // rv 1 + assign SAXISRQTDATA_in[168] = (SAXISRQTDATA[168] === 1'bz) || SAXISRQTDATA_delay[168]; // rv 1 + assign SAXISRQTDATA_in[169] = (SAXISRQTDATA[169] === 1'bz) || SAXISRQTDATA_delay[169]; // rv 1 + assign SAXISRQTDATA_in[16] = (SAXISRQTDATA[16] === 1'bz) || SAXISRQTDATA_delay[16]; // rv 1 + assign SAXISRQTDATA_in[170] = (SAXISRQTDATA[170] === 1'bz) || SAXISRQTDATA_delay[170]; // rv 1 + assign SAXISRQTDATA_in[171] = (SAXISRQTDATA[171] === 1'bz) || SAXISRQTDATA_delay[171]; // rv 1 + assign SAXISRQTDATA_in[172] = (SAXISRQTDATA[172] === 1'bz) || SAXISRQTDATA_delay[172]; // rv 1 + assign SAXISRQTDATA_in[173] = (SAXISRQTDATA[173] === 1'bz) || SAXISRQTDATA_delay[173]; // rv 1 + assign SAXISRQTDATA_in[174] = (SAXISRQTDATA[174] === 1'bz) || SAXISRQTDATA_delay[174]; // rv 1 + assign SAXISRQTDATA_in[175] = (SAXISRQTDATA[175] === 1'bz) || SAXISRQTDATA_delay[175]; // rv 1 + assign SAXISRQTDATA_in[176] = (SAXISRQTDATA[176] === 1'bz) || SAXISRQTDATA_delay[176]; // rv 1 + assign SAXISRQTDATA_in[177] = (SAXISRQTDATA[177] === 1'bz) || SAXISRQTDATA_delay[177]; // rv 1 + assign SAXISRQTDATA_in[178] = (SAXISRQTDATA[178] === 1'bz) || SAXISRQTDATA_delay[178]; // rv 1 + assign SAXISRQTDATA_in[179] = (SAXISRQTDATA[179] === 1'bz) || SAXISRQTDATA_delay[179]; // rv 1 + assign SAXISRQTDATA_in[17] = (SAXISRQTDATA[17] === 1'bz) || SAXISRQTDATA_delay[17]; // rv 1 + assign SAXISRQTDATA_in[180] = (SAXISRQTDATA[180] === 1'bz) || SAXISRQTDATA_delay[180]; // rv 1 + assign SAXISRQTDATA_in[181] = (SAXISRQTDATA[181] === 1'bz) || SAXISRQTDATA_delay[181]; // rv 1 + assign SAXISRQTDATA_in[182] = (SAXISRQTDATA[182] === 1'bz) || SAXISRQTDATA_delay[182]; // rv 1 + assign SAXISRQTDATA_in[183] = (SAXISRQTDATA[183] === 1'bz) || SAXISRQTDATA_delay[183]; // rv 1 + assign SAXISRQTDATA_in[184] = (SAXISRQTDATA[184] === 1'bz) || SAXISRQTDATA_delay[184]; // rv 1 + assign SAXISRQTDATA_in[185] = (SAXISRQTDATA[185] === 1'bz) || SAXISRQTDATA_delay[185]; // rv 1 + assign SAXISRQTDATA_in[186] = (SAXISRQTDATA[186] === 1'bz) || SAXISRQTDATA_delay[186]; // rv 1 + assign SAXISRQTDATA_in[187] = (SAXISRQTDATA[187] === 1'bz) || SAXISRQTDATA_delay[187]; // rv 1 + assign SAXISRQTDATA_in[188] = (SAXISRQTDATA[188] === 1'bz) || SAXISRQTDATA_delay[188]; // rv 1 + assign SAXISRQTDATA_in[189] = (SAXISRQTDATA[189] === 1'bz) || SAXISRQTDATA_delay[189]; // rv 1 + assign SAXISRQTDATA_in[18] = (SAXISRQTDATA[18] === 1'bz) || SAXISRQTDATA_delay[18]; // rv 1 + assign SAXISRQTDATA_in[190] = (SAXISRQTDATA[190] === 1'bz) || SAXISRQTDATA_delay[190]; // rv 1 + assign SAXISRQTDATA_in[191] = (SAXISRQTDATA[191] === 1'bz) || SAXISRQTDATA_delay[191]; // rv 1 + assign SAXISRQTDATA_in[192] = (SAXISRQTDATA[192] === 1'bz) || SAXISRQTDATA_delay[192]; // rv 1 + assign SAXISRQTDATA_in[193] = (SAXISRQTDATA[193] === 1'bz) || SAXISRQTDATA_delay[193]; // rv 1 + assign SAXISRQTDATA_in[194] = (SAXISRQTDATA[194] === 1'bz) || SAXISRQTDATA_delay[194]; // rv 1 + assign SAXISRQTDATA_in[195] = (SAXISRQTDATA[195] === 1'bz) || SAXISRQTDATA_delay[195]; // rv 1 + assign SAXISRQTDATA_in[196] = (SAXISRQTDATA[196] === 1'bz) || SAXISRQTDATA_delay[196]; // rv 1 + assign SAXISRQTDATA_in[197] = (SAXISRQTDATA[197] === 1'bz) || SAXISRQTDATA_delay[197]; // rv 1 + assign SAXISRQTDATA_in[198] = (SAXISRQTDATA[198] === 1'bz) || SAXISRQTDATA_delay[198]; // rv 1 + assign SAXISRQTDATA_in[199] = (SAXISRQTDATA[199] === 1'bz) || SAXISRQTDATA_delay[199]; // rv 1 + assign SAXISRQTDATA_in[19] = (SAXISRQTDATA[19] === 1'bz) || SAXISRQTDATA_delay[19]; // rv 1 + assign SAXISRQTDATA_in[1] = (SAXISRQTDATA[1] === 1'bz) || SAXISRQTDATA_delay[1]; // rv 1 + assign SAXISRQTDATA_in[200] = (SAXISRQTDATA[200] === 1'bz) || SAXISRQTDATA_delay[200]; // rv 1 + assign SAXISRQTDATA_in[201] = (SAXISRQTDATA[201] === 1'bz) || SAXISRQTDATA_delay[201]; // rv 1 + assign SAXISRQTDATA_in[202] = (SAXISRQTDATA[202] === 1'bz) || SAXISRQTDATA_delay[202]; // rv 1 + assign SAXISRQTDATA_in[203] = (SAXISRQTDATA[203] === 1'bz) || SAXISRQTDATA_delay[203]; // rv 1 + assign SAXISRQTDATA_in[204] = (SAXISRQTDATA[204] === 1'bz) || SAXISRQTDATA_delay[204]; // rv 1 + assign SAXISRQTDATA_in[205] = (SAXISRQTDATA[205] === 1'bz) || SAXISRQTDATA_delay[205]; // rv 1 + assign SAXISRQTDATA_in[206] = (SAXISRQTDATA[206] === 1'bz) || SAXISRQTDATA_delay[206]; // rv 1 + assign SAXISRQTDATA_in[207] = (SAXISRQTDATA[207] === 1'bz) || SAXISRQTDATA_delay[207]; // rv 1 + assign SAXISRQTDATA_in[208] = (SAXISRQTDATA[208] === 1'bz) || SAXISRQTDATA_delay[208]; // rv 1 + assign SAXISRQTDATA_in[209] = (SAXISRQTDATA[209] === 1'bz) || SAXISRQTDATA_delay[209]; // rv 1 + assign SAXISRQTDATA_in[20] = (SAXISRQTDATA[20] === 1'bz) || SAXISRQTDATA_delay[20]; // rv 1 + assign SAXISRQTDATA_in[210] = (SAXISRQTDATA[210] === 1'bz) || SAXISRQTDATA_delay[210]; // rv 1 + assign SAXISRQTDATA_in[211] = (SAXISRQTDATA[211] === 1'bz) || SAXISRQTDATA_delay[211]; // rv 1 + assign SAXISRQTDATA_in[212] = (SAXISRQTDATA[212] === 1'bz) || SAXISRQTDATA_delay[212]; // rv 1 + assign SAXISRQTDATA_in[213] = (SAXISRQTDATA[213] === 1'bz) || SAXISRQTDATA_delay[213]; // rv 1 + assign SAXISRQTDATA_in[214] = (SAXISRQTDATA[214] === 1'bz) || SAXISRQTDATA_delay[214]; // rv 1 + assign SAXISRQTDATA_in[215] = (SAXISRQTDATA[215] === 1'bz) || SAXISRQTDATA_delay[215]; // rv 1 + assign SAXISRQTDATA_in[216] = (SAXISRQTDATA[216] === 1'bz) || SAXISRQTDATA_delay[216]; // rv 1 + assign SAXISRQTDATA_in[217] = (SAXISRQTDATA[217] === 1'bz) || SAXISRQTDATA_delay[217]; // rv 1 + assign SAXISRQTDATA_in[218] = (SAXISRQTDATA[218] === 1'bz) || SAXISRQTDATA_delay[218]; // rv 1 + assign SAXISRQTDATA_in[219] = (SAXISRQTDATA[219] === 1'bz) || SAXISRQTDATA_delay[219]; // rv 1 + assign SAXISRQTDATA_in[21] = (SAXISRQTDATA[21] === 1'bz) || SAXISRQTDATA_delay[21]; // rv 1 + assign SAXISRQTDATA_in[220] = (SAXISRQTDATA[220] === 1'bz) || SAXISRQTDATA_delay[220]; // rv 1 + assign SAXISRQTDATA_in[221] = (SAXISRQTDATA[221] === 1'bz) || SAXISRQTDATA_delay[221]; // rv 1 + assign SAXISRQTDATA_in[222] = (SAXISRQTDATA[222] === 1'bz) || SAXISRQTDATA_delay[222]; // rv 1 + assign SAXISRQTDATA_in[223] = (SAXISRQTDATA[223] === 1'bz) || SAXISRQTDATA_delay[223]; // rv 1 + assign SAXISRQTDATA_in[224] = (SAXISRQTDATA[224] === 1'bz) || SAXISRQTDATA_delay[224]; // rv 1 + assign SAXISRQTDATA_in[225] = (SAXISRQTDATA[225] === 1'bz) || SAXISRQTDATA_delay[225]; // rv 1 + assign SAXISRQTDATA_in[226] = (SAXISRQTDATA[226] === 1'bz) || SAXISRQTDATA_delay[226]; // rv 1 + assign SAXISRQTDATA_in[227] = (SAXISRQTDATA[227] === 1'bz) || SAXISRQTDATA_delay[227]; // rv 1 + assign SAXISRQTDATA_in[228] = (SAXISRQTDATA[228] === 1'bz) || SAXISRQTDATA_delay[228]; // rv 1 + assign SAXISRQTDATA_in[229] = (SAXISRQTDATA[229] === 1'bz) || SAXISRQTDATA_delay[229]; // rv 1 + assign SAXISRQTDATA_in[22] = (SAXISRQTDATA[22] === 1'bz) || SAXISRQTDATA_delay[22]; // rv 1 + assign SAXISRQTDATA_in[230] = (SAXISRQTDATA[230] === 1'bz) || SAXISRQTDATA_delay[230]; // rv 1 + assign SAXISRQTDATA_in[231] = (SAXISRQTDATA[231] === 1'bz) || SAXISRQTDATA_delay[231]; // rv 1 + assign SAXISRQTDATA_in[232] = (SAXISRQTDATA[232] === 1'bz) || SAXISRQTDATA_delay[232]; // rv 1 + assign SAXISRQTDATA_in[233] = (SAXISRQTDATA[233] === 1'bz) || SAXISRQTDATA_delay[233]; // rv 1 + assign SAXISRQTDATA_in[234] = (SAXISRQTDATA[234] === 1'bz) || SAXISRQTDATA_delay[234]; // rv 1 + assign SAXISRQTDATA_in[235] = (SAXISRQTDATA[235] === 1'bz) || SAXISRQTDATA_delay[235]; // rv 1 + assign SAXISRQTDATA_in[236] = (SAXISRQTDATA[236] === 1'bz) || SAXISRQTDATA_delay[236]; // rv 1 + assign SAXISRQTDATA_in[237] = (SAXISRQTDATA[237] === 1'bz) || SAXISRQTDATA_delay[237]; // rv 1 + assign SAXISRQTDATA_in[238] = (SAXISRQTDATA[238] === 1'bz) || SAXISRQTDATA_delay[238]; // rv 1 + assign SAXISRQTDATA_in[239] = (SAXISRQTDATA[239] === 1'bz) || SAXISRQTDATA_delay[239]; // rv 1 + assign SAXISRQTDATA_in[23] = (SAXISRQTDATA[23] === 1'bz) || SAXISRQTDATA_delay[23]; // rv 1 + assign SAXISRQTDATA_in[240] = (SAXISRQTDATA[240] === 1'bz) || SAXISRQTDATA_delay[240]; // rv 1 + assign SAXISRQTDATA_in[241] = (SAXISRQTDATA[241] === 1'bz) || SAXISRQTDATA_delay[241]; // rv 1 + assign SAXISRQTDATA_in[242] = (SAXISRQTDATA[242] === 1'bz) || SAXISRQTDATA_delay[242]; // rv 1 + assign SAXISRQTDATA_in[243] = (SAXISRQTDATA[243] === 1'bz) || SAXISRQTDATA_delay[243]; // rv 1 + assign SAXISRQTDATA_in[244] = (SAXISRQTDATA[244] === 1'bz) || SAXISRQTDATA_delay[244]; // rv 1 + assign SAXISRQTDATA_in[245] = (SAXISRQTDATA[245] === 1'bz) || SAXISRQTDATA_delay[245]; // rv 1 + assign SAXISRQTDATA_in[246] = (SAXISRQTDATA[246] === 1'bz) || SAXISRQTDATA_delay[246]; // rv 1 + assign SAXISRQTDATA_in[247] = (SAXISRQTDATA[247] === 1'bz) || SAXISRQTDATA_delay[247]; // rv 1 + assign SAXISRQTDATA_in[248] = (SAXISRQTDATA[248] === 1'bz) || SAXISRQTDATA_delay[248]; // rv 1 + assign SAXISRQTDATA_in[249] = (SAXISRQTDATA[249] === 1'bz) || SAXISRQTDATA_delay[249]; // rv 1 + assign SAXISRQTDATA_in[24] = (SAXISRQTDATA[24] === 1'bz) || SAXISRQTDATA_delay[24]; // rv 1 + assign SAXISRQTDATA_in[250] = (SAXISRQTDATA[250] === 1'bz) || SAXISRQTDATA_delay[250]; // rv 1 + assign SAXISRQTDATA_in[251] = (SAXISRQTDATA[251] === 1'bz) || SAXISRQTDATA_delay[251]; // rv 1 + assign SAXISRQTDATA_in[252] = (SAXISRQTDATA[252] === 1'bz) || SAXISRQTDATA_delay[252]; // rv 1 + assign SAXISRQTDATA_in[253] = (SAXISRQTDATA[253] === 1'bz) || SAXISRQTDATA_delay[253]; // rv 1 + assign SAXISRQTDATA_in[254] = (SAXISRQTDATA[254] === 1'bz) || SAXISRQTDATA_delay[254]; // rv 1 + assign SAXISRQTDATA_in[255] = (SAXISRQTDATA[255] === 1'bz) || SAXISRQTDATA_delay[255]; // rv 1 + assign SAXISRQTDATA_in[25] = (SAXISRQTDATA[25] === 1'bz) || SAXISRQTDATA_delay[25]; // rv 1 + assign SAXISRQTDATA_in[26] = (SAXISRQTDATA[26] === 1'bz) || SAXISRQTDATA_delay[26]; // rv 1 + assign SAXISRQTDATA_in[27] = (SAXISRQTDATA[27] === 1'bz) || SAXISRQTDATA_delay[27]; // rv 1 + assign SAXISRQTDATA_in[28] = (SAXISRQTDATA[28] === 1'bz) || SAXISRQTDATA_delay[28]; // rv 1 + assign SAXISRQTDATA_in[29] = (SAXISRQTDATA[29] === 1'bz) || SAXISRQTDATA_delay[29]; // rv 1 + assign SAXISRQTDATA_in[2] = (SAXISRQTDATA[2] === 1'bz) || SAXISRQTDATA_delay[2]; // rv 1 + assign SAXISRQTDATA_in[30] = (SAXISRQTDATA[30] === 1'bz) || SAXISRQTDATA_delay[30]; // rv 1 + assign SAXISRQTDATA_in[31] = (SAXISRQTDATA[31] === 1'bz) || SAXISRQTDATA_delay[31]; // rv 1 + assign SAXISRQTDATA_in[32] = (SAXISRQTDATA[32] === 1'bz) || SAXISRQTDATA_delay[32]; // rv 1 + assign SAXISRQTDATA_in[33] = (SAXISRQTDATA[33] === 1'bz) || SAXISRQTDATA_delay[33]; // rv 1 + assign SAXISRQTDATA_in[34] = (SAXISRQTDATA[34] === 1'bz) || SAXISRQTDATA_delay[34]; // rv 1 + assign SAXISRQTDATA_in[35] = (SAXISRQTDATA[35] === 1'bz) || SAXISRQTDATA_delay[35]; // rv 1 + assign SAXISRQTDATA_in[36] = (SAXISRQTDATA[36] === 1'bz) || SAXISRQTDATA_delay[36]; // rv 1 + assign SAXISRQTDATA_in[37] = (SAXISRQTDATA[37] === 1'bz) || SAXISRQTDATA_delay[37]; // rv 1 + assign SAXISRQTDATA_in[38] = (SAXISRQTDATA[38] === 1'bz) || SAXISRQTDATA_delay[38]; // rv 1 + assign SAXISRQTDATA_in[39] = (SAXISRQTDATA[39] === 1'bz) || SAXISRQTDATA_delay[39]; // rv 1 + assign SAXISRQTDATA_in[3] = (SAXISRQTDATA[3] === 1'bz) || SAXISRQTDATA_delay[3]; // rv 1 + assign SAXISRQTDATA_in[40] = (SAXISRQTDATA[40] === 1'bz) || SAXISRQTDATA_delay[40]; // rv 1 + assign SAXISRQTDATA_in[41] = (SAXISRQTDATA[41] === 1'bz) || SAXISRQTDATA_delay[41]; // rv 1 + assign SAXISRQTDATA_in[42] = (SAXISRQTDATA[42] === 1'bz) || SAXISRQTDATA_delay[42]; // rv 1 + assign SAXISRQTDATA_in[43] = (SAXISRQTDATA[43] === 1'bz) || SAXISRQTDATA_delay[43]; // rv 1 + assign SAXISRQTDATA_in[44] = (SAXISRQTDATA[44] === 1'bz) || SAXISRQTDATA_delay[44]; // rv 1 + assign SAXISRQTDATA_in[45] = (SAXISRQTDATA[45] === 1'bz) || SAXISRQTDATA_delay[45]; // rv 1 + assign SAXISRQTDATA_in[46] = (SAXISRQTDATA[46] === 1'bz) || SAXISRQTDATA_delay[46]; // rv 1 + assign SAXISRQTDATA_in[47] = (SAXISRQTDATA[47] === 1'bz) || SAXISRQTDATA_delay[47]; // rv 1 + assign SAXISRQTDATA_in[48] = (SAXISRQTDATA[48] === 1'bz) || SAXISRQTDATA_delay[48]; // rv 1 + assign SAXISRQTDATA_in[49] = (SAXISRQTDATA[49] === 1'bz) || SAXISRQTDATA_delay[49]; // rv 1 + assign SAXISRQTDATA_in[4] = (SAXISRQTDATA[4] === 1'bz) || SAXISRQTDATA_delay[4]; // rv 1 + assign SAXISRQTDATA_in[50] = (SAXISRQTDATA[50] === 1'bz) || SAXISRQTDATA_delay[50]; // rv 1 + assign SAXISRQTDATA_in[51] = (SAXISRQTDATA[51] === 1'bz) || SAXISRQTDATA_delay[51]; // rv 1 + assign SAXISRQTDATA_in[52] = (SAXISRQTDATA[52] === 1'bz) || SAXISRQTDATA_delay[52]; // rv 1 + assign SAXISRQTDATA_in[53] = (SAXISRQTDATA[53] === 1'bz) || SAXISRQTDATA_delay[53]; // rv 1 + assign SAXISRQTDATA_in[54] = (SAXISRQTDATA[54] === 1'bz) || SAXISRQTDATA_delay[54]; // rv 1 + assign SAXISRQTDATA_in[55] = (SAXISRQTDATA[55] === 1'bz) || SAXISRQTDATA_delay[55]; // rv 1 + assign SAXISRQTDATA_in[56] = (SAXISRQTDATA[56] === 1'bz) || SAXISRQTDATA_delay[56]; // rv 1 + assign SAXISRQTDATA_in[57] = (SAXISRQTDATA[57] === 1'bz) || SAXISRQTDATA_delay[57]; // rv 1 + assign SAXISRQTDATA_in[58] = (SAXISRQTDATA[58] === 1'bz) || SAXISRQTDATA_delay[58]; // rv 1 + assign SAXISRQTDATA_in[59] = (SAXISRQTDATA[59] === 1'bz) || SAXISRQTDATA_delay[59]; // rv 1 + assign SAXISRQTDATA_in[5] = (SAXISRQTDATA[5] === 1'bz) || SAXISRQTDATA_delay[5]; // rv 1 + assign SAXISRQTDATA_in[60] = (SAXISRQTDATA[60] === 1'bz) || SAXISRQTDATA_delay[60]; // rv 1 + assign SAXISRQTDATA_in[61] = (SAXISRQTDATA[61] === 1'bz) || SAXISRQTDATA_delay[61]; // rv 1 + assign SAXISRQTDATA_in[62] = (SAXISRQTDATA[62] === 1'bz) || SAXISRQTDATA_delay[62]; // rv 1 + assign SAXISRQTDATA_in[63] = (SAXISRQTDATA[63] === 1'bz) || SAXISRQTDATA_delay[63]; // rv 1 + assign SAXISRQTDATA_in[64] = (SAXISRQTDATA[64] === 1'bz) || SAXISRQTDATA_delay[64]; // rv 1 + assign SAXISRQTDATA_in[65] = (SAXISRQTDATA[65] === 1'bz) || SAXISRQTDATA_delay[65]; // rv 1 + assign SAXISRQTDATA_in[66] = (SAXISRQTDATA[66] === 1'bz) || SAXISRQTDATA_delay[66]; // rv 1 + assign SAXISRQTDATA_in[67] = (SAXISRQTDATA[67] === 1'bz) || SAXISRQTDATA_delay[67]; // rv 1 + assign SAXISRQTDATA_in[68] = (SAXISRQTDATA[68] === 1'bz) || SAXISRQTDATA_delay[68]; // rv 1 + assign SAXISRQTDATA_in[69] = (SAXISRQTDATA[69] === 1'bz) || SAXISRQTDATA_delay[69]; // rv 1 + assign SAXISRQTDATA_in[6] = (SAXISRQTDATA[6] === 1'bz) || SAXISRQTDATA_delay[6]; // rv 1 + assign SAXISRQTDATA_in[70] = (SAXISRQTDATA[70] === 1'bz) || SAXISRQTDATA_delay[70]; // rv 1 + assign SAXISRQTDATA_in[71] = (SAXISRQTDATA[71] === 1'bz) || SAXISRQTDATA_delay[71]; // rv 1 + assign SAXISRQTDATA_in[72] = (SAXISRQTDATA[72] === 1'bz) || SAXISRQTDATA_delay[72]; // rv 1 + assign SAXISRQTDATA_in[73] = (SAXISRQTDATA[73] === 1'bz) || SAXISRQTDATA_delay[73]; // rv 1 + assign SAXISRQTDATA_in[74] = (SAXISRQTDATA[74] === 1'bz) || SAXISRQTDATA_delay[74]; // rv 1 + assign SAXISRQTDATA_in[75] = (SAXISRQTDATA[75] === 1'bz) || SAXISRQTDATA_delay[75]; // rv 1 + assign SAXISRQTDATA_in[76] = (SAXISRQTDATA[76] === 1'bz) || SAXISRQTDATA_delay[76]; // rv 1 + assign SAXISRQTDATA_in[77] = (SAXISRQTDATA[77] === 1'bz) || SAXISRQTDATA_delay[77]; // rv 1 + assign SAXISRQTDATA_in[78] = (SAXISRQTDATA[78] === 1'bz) || SAXISRQTDATA_delay[78]; // rv 1 + assign SAXISRQTDATA_in[79] = (SAXISRQTDATA[79] === 1'bz) || SAXISRQTDATA_delay[79]; // rv 1 + assign SAXISRQTDATA_in[7] = (SAXISRQTDATA[7] === 1'bz) || SAXISRQTDATA_delay[7]; // rv 1 + assign SAXISRQTDATA_in[80] = (SAXISRQTDATA[80] === 1'bz) || SAXISRQTDATA_delay[80]; // rv 1 + assign SAXISRQTDATA_in[81] = (SAXISRQTDATA[81] === 1'bz) || SAXISRQTDATA_delay[81]; // rv 1 + assign SAXISRQTDATA_in[82] = (SAXISRQTDATA[82] === 1'bz) || SAXISRQTDATA_delay[82]; // rv 1 + assign SAXISRQTDATA_in[83] = (SAXISRQTDATA[83] === 1'bz) || SAXISRQTDATA_delay[83]; // rv 1 + assign SAXISRQTDATA_in[84] = (SAXISRQTDATA[84] === 1'bz) || SAXISRQTDATA_delay[84]; // rv 1 + assign SAXISRQTDATA_in[85] = (SAXISRQTDATA[85] === 1'bz) || SAXISRQTDATA_delay[85]; // rv 1 + assign SAXISRQTDATA_in[86] = (SAXISRQTDATA[86] === 1'bz) || SAXISRQTDATA_delay[86]; // rv 1 + assign SAXISRQTDATA_in[87] = (SAXISRQTDATA[87] === 1'bz) || SAXISRQTDATA_delay[87]; // rv 1 + assign SAXISRQTDATA_in[88] = (SAXISRQTDATA[88] === 1'bz) || SAXISRQTDATA_delay[88]; // rv 1 + assign SAXISRQTDATA_in[89] = (SAXISRQTDATA[89] === 1'bz) || SAXISRQTDATA_delay[89]; // rv 1 + assign SAXISRQTDATA_in[8] = (SAXISRQTDATA[8] === 1'bz) || SAXISRQTDATA_delay[8]; // rv 1 + assign SAXISRQTDATA_in[90] = (SAXISRQTDATA[90] === 1'bz) || SAXISRQTDATA_delay[90]; // rv 1 + assign SAXISRQTDATA_in[91] = (SAXISRQTDATA[91] === 1'bz) || SAXISRQTDATA_delay[91]; // rv 1 + assign SAXISRQTDATA_in[92] = (SAXISRQTDATA[92] === 1'bz) || SAXISRQTDATA_delay[92]; // rv 1 + assign SAXISRQTDATA_in[93] = (SAXISRQTDATA[93] === 1'bz) || SAXISRQTDATA_delay[93]; // rv 1 + assign SAXISRQTDATA_in[94] = (SAXISRQTDATA[94] === 1'bz) || SAXISRQTDATA_delay[94]; // rv 1 + assign SAXISRQTDATA_in[95] = (SAXISRQTDATA[95] === 1'bz) || SAXISRQTDATA_delay[95]; // rv 1 + assign SAXISRQTDATA_in[96] = (SAXISRQTDATA[96] === 1'bz) || SAXISRQTDATA_delay[96]; // rv 1 + assign SAXISRQTDATA_in[97] = (SAXISRQTDATA[97] === 1'bz) || SAXISRQTDATA_delay[97]; // rv 1 + assign SAXISRQTDATA_in[98] = (SAXISRQTDATA[98] === 1'bz) || SAXISRQTDATA_delay[98]; // rv 1 + assign SAXISRQTDATA_in[99] = (SAXISRQTDATA[99] === 1'bz) || SAXISRQTDATA_delay[99]; // rv 1 + assign SAXISRQTDATA_in[9] = (SAXISRQTDATA[9] === 1'bz) || SAXISRQTDATA_delay[9]; // rv 1 + assign SAXISRQTKEEP_in[0] = (SAXISRQTKEEP[0] !== 1'bz) && SAXISRQTKEEP_delay[0]; // rv 0 + assign SAXISRQTKEEP_in[1] = (SAXISRQTKEEP[1] !== 1'bz) && SAXISRQTKEEP_delay[1]; // rv 0 + assign SAXISRQTKEEP_in[2] = (SAXISRQTKEEP[2] !== 1'bz) && SAXISRQTKEEP_delay[2]; // rv 0 + assign SAXISRQTKEEP_in[3] = (SAXISRQTKEEP[3] !== 1'bz) && SAXISRQTKEEP_delay[3]; // rv 0 + assign SAXISRQTKEEP_in[4] = (SAXISRQTKEEP[4] !== 1'bz) && SAXISRQTKEEP_delay[4]; // rv 0 + assign SAXISRQTKEEP_in[5] = (SAXISRQTKEEP[5] !== 1'bz) && SAXISRQTKEEP_delay[5]; // rv 0 + assign SAXISRQTKEEP_in[6] = (SAXISRQTKEEP[6] !== 1'bz) && SAXISRQTKEEP_delay[6]; // rv 0 + assign SAXISRQTKEEP_in[7] = (SAXISRQTKEEP[7] !== 1'bz) && SAXISRQTKEEP_delay[7]; // rv 0 + assign SAXISRQTLAST_in = (SAXISRQTLAST === 1'bz) || SAXISRQTLAST_delay; // rv 1 + assign SAXISRQTUSER_in[0] = (SAXISRQTUSER[0] === 1'bz) || SAXISRQTUSER_delay[0]; // rv 1 + assign SAXISRQTUSER_in[10] = (SAXISRQTUSER[10] === 1'bz) || SAXISRQTUSER_delay[10]; // rv 1 + assign SAXISRQTUSER_in[11] = (SAXISRQTUSER[11] === 1'bz) || SAXISRQTUSER_delay[11]; // rv 1 + assign SAXISRQTUSER_in[12] = (SAXISRQTUSER[12] === 1'bz) || SAXISRQTUSER_delay[12]; // rv 1 + assign SAXISRQTUSER_in[13] = (SAXISRQTUSER[13] === 1'bz) || SAXISRQTUSER_delay[13]; // rv 1 + assign SAXISRQTUSER_in[14] = (SAXISRQTUSER[14] === 1'bz) || SAXISRQTUSER_delay[14]; // rv 1 + assign SAXISRQTUSER_in[15] = (SAXISRQTUSER[15] === 1'bz) || SAXISRQTUSER_delay[15]; // rv 1 + assign SAXISRQTUSER_in[16] = (SAXISRQTUSER[16] === 1'bz) || SAXISRQTUSER_delay[16]; // rv 1 + assign SAXISRQTUSER_in[17] = (SAXISRQTUSER[17] === 1'bz) || SAXISRQTUSER_delay[17]; // rv 1 + assign SAXISRQTUSER_in[18] = (SAXISRQTUSER[18] === 1'bz) || SAXISRQTUSER_delay[18]; // rv 1 + assign SAXISRQTUSER_in[19] = (SAXISRQTUSER[19] === 1'bz) || SAXISRQTUSER_delay[19]; // rv 1 + assign SAXISRQTUSER_in[1] = (SAXISRQTUSER[1] === 1'bz) || SAXISRQTUSER_delay[1]; // rv 1 + assign SAXISRQTUSER_in[20] = (SAXISRQTUSER[20] === 1'bz) || SAXISRQTUSER_delay[20]; // rv 1 + assign SAXISRQTUSER_in[21] = (SAXISRQTUSER[21] === 1'bz) || SAXISRQTUSER_delay[21]; // rv 1 + assign SAXISRQTUSER_in[22] = (SAXISRQTUSER[22] === 1'bz) || SAXISRQTUSER_delay[22]; // rv 1 + assign SAXISRQTUSER_in[23] = (SAXISRQTUSER[23] === 1'bz) || SAXISRQTUSER_delay[23]; // rv 1 + assign SAXISRQTUSER_in[24] = (SAXISRQTUSER[24] === 1'bz) || SAXISRQTUSER_delay[24]; // rv 1 + assign SAXISRQTUSER_in[25] = (SAXISRQTUSER[25] === 1'bz) || SAXISRQTUSER_delay[25]; // rv 1 + assign SAXISRQTUSER_in[26] = (SAXISRQTUSER[26] === 1'bz) || SAXISRQTUSER_delay[26]; // rv 1 + assign SAXISRQTUSER_in[27] = (SAXISRQTUSER[27] === 1'bz) || SAXISRQTUSER_delay[27]; // rv 1 + assign SAXISRQTUSER_in[28] = (SAXISRQTUSER[28] === 1'bz) || SAXISRQTUSER_delay[28]; // rv 1 + assign SAXISRQTUSER_in[29] = (SAXISRQTUSER[29] === 1'bz) || SAXISRQTUSER_delay[29]; // rv 1 + assign SAXISRQTUSER_in[2] = (SAXISRQTUSER[2] === 1'bz) || SAXISRQTUSER_delay[2]; // rv 1 + assign SAXISRQTUSER_in[30] = (SAXISRQTUSER[30] === 1'bz) || SAXISRQTUSER_delay[30]; // rv 1 + assign SAXISRQTUSER_in[31] = (SAXISRQTUSER[31] === 1'bz) || SAXISRQTUSER_delay[31]; // rv 1 + assign SAXISRQTUSER_in[32] = (SAXISRQTUSER[32] === 1'bz) || SAXISRQTUSER_delay[32]; // rv 1 + assign SAXISRQTUSER_in[33] = (SAXISRQTUSER[33] === 1'bz) || SAXISRQTUSER_delay[33]; // rv 1 + assign SAXISRQTUSER_in[34] = (SAXISRQTUSER[34] === 1'bz) || SAXISRQTUSER_delay[34]; // rv 1 + assign SAXISRQTUSER_in[35] = (SAXISRQTUSER[35] === 1'bz) || SAXISRQTUSER_delay[35]; // rv 1 + assign SAXISRQTUSER_in[36] = (SAXISRQTUSER[36] === 1'bz) || SAXISRQTUSER_delay[36]; // rv 1 + assign SAXISRQTUSER_in[37] = (SAXISRQTUSER[37] === 1'bz) || SAXISRQTUSER_delay[37]; // rv 1 + assign SAXISRQTUSER_in[38] = (SAXISRQTUSER[38] === 1'bz) || SAXISRQTUSER_delay[38]; // rv 1 + assign SAXISRQTUSER_in[39] = (SAXISRQTUSER[39] === 1'bz) || SAXISRQTUSER_delay[39]; // rv 1 + assign SAXISRQTUSER_in[3] = (SAXISRQTUSER[3] === 1'bz) || SAXISRQTUSER_delay[3]; // rv 1 + assign SAXISRQTUSER_in[40] = (SAXISRQTUSER[40] === 1'bz) || SAXISRQTUSER_delay[40]; // rv 1 + assign SAXISRQTUSER_in[41] = (SAXISRQTUSER[41] === 1'bz) || SAXISRQTUSER_delay[41]; // rv 1 + assign SAXISRQTUSER_in[42] = (SAXISRQTUSER[42] === 1'bz) || SAXISRQTUSER_delay[42]; // rv 1 + assign SAXISRQTUSER_in[43] = (SAXISRQTUSER[43] === 1'bz) || SAXISRQTUSER_delay[43]; // rv 1 + assign SAXISRQTUSER_in[44] = (SAXISRQTUSER[44] === 1'bz) || SAXISRQTUSER_delay[44]; // rv 1 + assign SAXISRQTUSER_in[45] = (SAXISRQTUSER[45] === 1'bz) || SAXISRQTUSER_delay[45]; // rv 1 + assign SAXISRQTUSER_in[46] = (SAXISRQTUSER[46] === 1'bz) || SAXISRQTUSER_delay[46]; // rv 1 + assign SAXISRQTUSER_in[47] = (SAXISRQTUSER[47] === 1'bz) || SAXISRQTUSER_delay[47]; // rv 1 + assign SAXISRQTUSER_in[48] = (SAXISRQTUSER[48] === 1'bz) || SAXISRQTUSER_delay[48]; // rv 1 + assign SAXISRQTUSER_in[49] = (SAXISRQTUSER[49] === 1'bz) || SAXISRQTUSER_delay[49]; // rv 1 + assign SAXISRQTUSER_in[4] = (SAXISRQTUSER[4] === 1'bz) || SAXISRQTUSER_delay[4]; // rv 1 + assign SAXISRQTUSER_in[50] = (SAXISRQTUSER[50] === 1'bz) || SAXISRQTUSER_delay[50]; // rv 1 + assign SAXISRQTUSER_in[51] = (SAXISRQTUSER[51] === 1'bz) || SAXISRQTUSER_delay[51]; // rv 1 + assign SAXISRQTUSER_in[52] = (SAXISRQTUSER[52] === 1'bz) || SAXISRQTUSER_delay[52]; // rv 1 + assign SAXISRQTUSER_in[53] = (SAXISRQTUSER[53] === 1'bz) || SAXISRQTUSER_delay[53]; // rv 1 + assign SAXISRQTUSER_in[54] = (SAXISRQTUSER[54] === 1'bz) || SAXISRQTUSER_delay[54]; // rv 1 + assign SAXISRQTUSER_in[55] = (SAXISRQTUSER[55] === 1'bz) || SAXISRQTUSER_delay[55]; // rv 1 + assign SAXISRQTUSER_in[56] = (SAXISRQTUSER[56] === 1'bz) || SAXISRQTUSER_delay[56]; // rv 1 + assign SAXISRQTUSER_in[57] = (SAXISRQTUSER[57] === 1'bz) || SAXISRQTUSER_delay[57]; // rv 1 + assign SAXISRQTUSER_in[58] = (SAXISRQTUSER[58] === 1'bz) || SAXISRQTUSER_delay[58]; // rv 1 + assign SAXISRQTUSER_in[59] = (SAXISRQTUSER[59] === 1'bz) || SAXISRQTUSER_delay[59]; // rv 1 + assign SAXISRQTUSER_in[5] = (SAXISRQTUSER[5] === 1'bz) || SAXISRQTUSER_delay[5]; // rv 1 + assign SAXISRQTUSER_in[60] = (SAXISRQTUSER[60] === 1'bz) || SAXISRQTUSER_delay[60]; // rv 1 + assign SAXISRQTUSER_in[61] = (SAXISRQTUSER[61] === 1'bz) || SAXISRQTUSER_delay[61]; // rv 1 + assign SAXISRQTUSER_in[6] = (SAXISRQTUSER[6] === 1'bz) || SAXISRQTUSER_delay[6]; // rv 1 + assign SAXISRQTUSER_in[7] = (SAXISRQTUSER[7] === 1'bz) || SAXISRQTUSER_delay[7]; // rv 1 + assign SAXISRQTUSER_in[8] = (SAXISRQTUSER[8] === 1'bz) || SAXISRQTUSER_delay[8]; // rv 1 + assign SAXISRQTUSER_in[9] = (SAXISRQTUSER[9] === 1'bz) || SAXISRQTUSER_delay[9]; // rv 1 + assign SAXISRQTVALID_in = (SAXISRQTVALID !== 1'bz) && SAXISRQTVALID_delay; // rv 0 + assign USERCLKEN_in = (USERCLKEN !== 1'bz) && USERCLKEN_delay; // rv 0 + assign USERSPAREIN_in[0] = (USERSPAREIN[0] === 1'bz) || USERSPAREIN_delay[0]; // rv 1 + assign USERSPAREIN_in[10] = (USERSPAREIN[10] === 1'bz) || USERSPAREIN_delay[10]; // rv 1 + assign USERSPAREIN_in[11] = (USERSPAREIN[11] === 1'bz) || USERSPAREIN_delay[11]; // rv 1 + assign USERSPAREIN_in[12] = (USERSPAREIN[12] === 1'bz) || USERSPAREIN_delay[12]; // rv 1 + assign USERSPAREIN_in[13] = (USERSPAREIN[13] === 1'bz) || USERSPAREIN_delay[13]; // rv 1 + assign USERSPAREIN_in[14] = (USERSPAREIN[14] === 1'bz) || USERSPAREIN_delay[14]; // rv 1 + assign USERSPAREIN_in[15] = (USERSPAREIN[15] === 1'bz) || USERSPAREIN_delay[15]; // rv 1 + assign USERSPAREIN_in[16] = (USERSPAREIN[16] === 1'bz) || USERSPAREIN_delay[16]; // rv 1 + assign USERSPAREIN_in[17] = (USERSPAREIN[17] === 1'bz) || USERSPAREIN_delay[17]; // rv 1 + assign USERSPAREIN_in[18] = (USERSPAREIN[18] === 1'bz) || USERSPAREIN_delay[18]; // rv 1 + assign USERSPAREIN_in[19] = (USERSPAREIN[19] === 1'bz) || USERSPAREIN_delay[19]; // rv 1 + assign USERSPAREIN_in[1] = (USERSPAREIN[1] === 1'bz) || USERSPAREIN_delay[1]; // rv 1 + assign USERSPAREIN_in[20] = (USERSPAREIN[20] === 1'bz) || USERSPAREIN_delay[20]; // rv 1 + assign USERSPAREIN_in[21] = (USERSPAREIN[21] === 1'bz) || USERSPAREIN_delay[21]; // rv 1 + assign USERSPAREIN_in[22] = (USERSPAREIN[22] === 1'bz) || USERSPAREIN_delay[22]; // rv 1 + assign USERSPAREIN_in[23] = (USERSPAREIN[23] === 1'bz) || USERSPAREIN_delay[23]; // rv 1 + assign USERSPAREIN_in[24] = (USERSPAREIN[24] === 1'bz) || USERSPAREIN_delay[24]; // rv 1 + assign USERSPAREIN_in[25] = (USERSPAREIN[25] === 1'bz) || USERSPAREIN_delay[25]; // rv 1 + assign USERSPAREIN_in[26] = (USERSPAREIN[26] === 1'bz) || USERSPAREIN_delay[26]; // rv 1 + assign USERSPAREIN_in[27] = (USERSPAREIN[27] === 1'bz) || USERSPAREIN_delay[27]; // rv 1 + assign USERSPAREIN_in[28] = (USERSPAREIN[28] === 1'bz) || USERSPAREIN_delay[28]; // rv 1 + assign USERSPAREIN_in[29] = (USERSPAREIN[29] === 1'bz) || USERSPAREIN_delay[29]; // rv 1 + assign USERSPAREIN_in[2] = (USERSPAREIN[2] === 1'bz) || USERSPAREIN_delay[2]; // rv 1 + assign USERSPAREIN_in[30] = (USERSPAREIN[30] === 1'bz) || USERSPAREIN_delay[30]; // rv 1 + assign USERSPAREIN_in[31] = (USERSPAREIN[31] === 1'bz) || USERSPAREIN_delay[31]; // rv 1 + assign USERSPAREIN_in[3] = (USERSPAREIN[3] === 1'bz) || USERSPAREIN_delay[3]; // rv 1 + assign USERSPAREIN_in[4] = (USERSPAREIN[4] === 1'bz) || USERSPAREIN_delay[4]; // rv 1 + assign USERSPAREIN_in[5] = (USERSPAREIN[5] === 1'bz) || USERSPAREIN_delay[5]; // rv 1 + assign USERSPAREIN_in[6] = (USERSPAREIN[6] === 1'bz) || USERSPAREIN_delay[6]; // rv 1 + assign USERSPAREIN_in[7] = (USERSPAREIN[7] === 1'bz) || USERSPAREIN_delay[7]; // rv 1 + assign USERSPAREIN_in[8] = (USERSPAREIN[8] === 1'bz) || USERSPAREIN_delay[8]; // rv 1 + assign USERSPAREIN_in[9] = (USERSPAREIN[9] === 1'bz) || USERSPAREIN_delay[9]; // rv 1 +`else + assign AXIUSERIN_in[0] = (AXIUSERIN[0] !== 1'bz) && AXIUSERIN[0]; // rv 0 + assign AXIUSERIN_in[1] = (AXIUSERIN[1] !== 1'bz) && AXIUSERIN[1]; // rv 0 + assign AXIUSERIN_in[2] = (AXIUSERIN[2] !== 1'bz) && AXIUSERIN[2]; // rv 0 + assign AXIUSERIN_in[3] = (AXIUSERIN[3] !== 1'bz) && AXIUSERIN[3]; // rv 0 + assign AXIUSERIN_in[4] = (AXIUSERIN[4] !== 1'bz) && AXIUSERIN[4]; // rv 0 + assign AXIUSERIN_in[5] = (AXIUSERIN[5] !== 1'bz) && AXIUSERIN[5]; // rv 0 + assign AXIUSERIN_in[6] = (AXIUSERIN[6] !== 1'bz) && AXIUSERIN[6]; // rv 0 + assign AXIUSERIN_in[7] = (AXIUSERIN[7] !== 1'bz) && AXIUSERIN[7]; // rv 0 + assign CFGCONFIGSPACEENABLE_in = (CFGCONFIGSPACEENABLE === 1'bz) || CFGCONFIGSPACEENABLE; // rv 1 + assign CFGDEVIDPF0_in[0] = (CFGDEVIDPF0[0] !== 1'bz) && CFGDEVIDPF0[0]; // rv 0 + assign CFGDEVIDPF0_in[10] = (CFGDEVIDPF0[10] !== 1'bz) && CFGDEVIDPF0[10]; // rv 0 + assign CFGDEVIDPF0_in[11] = (CFGDEVIDPF0[11] !== 1'bz) && CFGDEVIDPF0[11]; // rv 0 + assign CFGDEVIDPF0_in[12] = (CFGDEVIDPF0[12] !== 1'bz) && CFGDEVIDPF0[12]; // rv 0 + assign CFGDEVIDPF0_in[13] = (CFGDEVIDPF0[13] !== 1'bz) && CFGDEVIDPF0[13]; // rv 0 + assign CFGDEVIDPF0_in[14] = (CFGDEVIDPF0[14] !== 1'bz) && CFGDEVIDPF0[14]; // rv 0 + assign CFGDEVIDPF0_in[15] = (CFGDEVIDPF0[15] !== 1'bz) && CFGDEVIDPF0[15]; // rv 0 + assign CFGDEVIDPF0_in[1] = (CFGDEVIDPF0[1] !== 1'bz) && CFGDEVIDPF0[1]; // rv 0 + assign CFGDEVIDPF0_in[2] = (CFGDEVIDPF0[2] !== 1'bz) && CFGDEVIDPF0[2]; // rv 0 + assign CFGDEVIDPF0_in[3] = (CFGDEVIDPF0[3] !== 1'bz) && CFGDEVIDPF0[3]; // rv 0 + assign CFGDEVIDPF0_in[4] = (CFGDEVIDPF0[4] !== 1'bz) && CFGDEVIDPF0[4]; // rv 0 + assign CFGDEVIDPF0_in[5] = (CFGDEVIDPF0[5] !== 1'bz) && CFGDEVIDPF0[5]; // rv 0 + assign CFGDEVIDPF0_in[6] = (CFGDEVIDPF0[6] !== 1'bz) && CFGDEVIDPF0[6]; // rv 0 + assign CFGDEVIDPF0_in[7] = (CFGDEVIDPF0[7] !== 1'bz) && CFGDEVIDPF0[7]; // rv 0 + assign CFGDEVIDPF0_in[8] = (CFGDEVIDPF0[8] !== 1'bz) && CFGDEVIDPF0[8]; // rv 0 + assign CFGDEVIDPF0_in[9] = (CFGDEVIDPF0[9] !== 1'bz) && CFGDEVIDPF0[9]; // rv 0 + assign CFGDEVIDPF1_in[0] = (CFGDEVIDPF1[0] !== 1'bz) && CFGDEVIDPF1[0]; // rv 0 + assign CFGDEVIDPF1_in[10] = (CFGDEVIDPF1[10] !== 1'bz) && CFGDEVIDPF1[10]; // rv 0 + assign CFGDEVIDPF1_in[11] = (CFGDEVIDPF1[11] !== 1'bz) && CFGDEVIDPF1[11]; // rv 0 + assign CFGDEVIDPF1_in[12] = (CFGDEVIDPF1[12] !== 1'bz) && CFGDEVIDPF1[12]; // rv 0 + assign CFGDEVIDPF1_in[13] = (CFGDEVIDPF1[13] !== 1'bz) && CFGDEVIDPF1[13]; // rv 0 + assign CFGDEVIDPF1_in[14] = (CFGDEVIDPF1[14] !== 1'bz) && CFGDEVIDPF1[14]; // rv 0 + assign CFGDEVIDPF1_in[15] = (CFGDEVIDPF1[15] !== 1'bz) && CFGDEVIDPF1[15]; // rv 0 + assign CFGDEVIDPF1_in[1] = (CFGDEVIDPF1[1] !== 1'bz) && CFGDEVIDPF1[1]; // rv 0 + assign CFGDEVIDPF1_in[2] = (CFGDEVIDPF1[2] !== 1'bz) && CFGDEVIDPF1[2]; // rv 0 + assign CFGDEVIDPF1_in[3] = (CFGDEVIDPF1[3] !== 1'bz) && CFGDEVIDPF1[3]; // rv 0 + assign CFGDEVIDPF1_in[4] = (CFGDEVIDPF1[4] !== 1'bz) && CFGDEVIDPF1[4]; // rv 0 + assign CFGDEVIDPF1_in[5] = (CFGDEVIDPF1[5] !== 1'bz) && CFGDEVIDPF1[5]; // rv 0 + assign CFGDEVIDPF1_in[6] = (CFGDEVIDPF1[6] !== 1'bz) && CFGDEVIDPF1[6]; // rv 0 + assign CFGDEVIDPF1_in[7] = (CFGDEVIDPF1[7] !== 1'bz) && CFGDEVIDPF1[7]; // rv 0 + assign CFGDEVIDPF1_in[8] = (CFGDEVIDPF1[8] !== 1'bz) && CFGDEVIDPF1[8]; // rv 0 + assign CFGDEVIDPF1_in[9] = (CFGDEVIDPF1[9] !== 1'bz) && CFGDEVIDPF1[9]; // rv 0 + assign CFGDEVIDPF2_in[0] = (CFGDEVIDPF2[0] !== 1'bz) && CFGDEVIDPF2[0]; // rv 0 + assign CFGDEVIDPF2_in[10] = (CFGDEVIDPF2[10] !== 1'bz) && CFGDEVIDPF2[10]; // rv 0 + assign CFGDEVIDPF2_in[11] = (CFGDEVIDPF2[11] !== 1'bz) && CFGDEVIDPF2[11]; // rv 0 + assign CFGDEVIDPF2_in[12] = (CFGDEVIDPF2[12] !== 1'bz) && CFGDEVIDPF2[12]; // rv 0 + assign CFGDEVIDPF2_in[13] = (CFGDEVIDPF2[13] !== 1'bz) && CFGDEVIDPF2[13]; // rv 0 + assign CFGDEVIDPF2_in[14] = (CFGDEVIDPF2[14] !== 1'bz) && CFGDEVIDPF2[14]; // rv 0 + assign CFGDEVIDPF2_in[15] = (CFGDEVIDPF2[15] !== 1'bz) && CFGDEVIDPF2[15]; // rv 0 + assign CFGDEVIDPF2_in[1] = (CFGDEVIDPF2[1] !== 1'bz) && CFGDEVIDPF2[1]; // rv 0 + assign CFGDEVIDPF2_in[2] = (CFGDEVIDPF2[2] !== 1'bz) && CFGDEVIDPF2[2]; // rv 0 + assign CFGDEVIDPF2_in[3] = (CFGDEVIDPF2[3] !== 1'bz) && CFGDEVIDPF2[3]; // rv 0 + assign CFGDEVIDPF2_in[4] = (CFGDEVIDPF2[4] !== 1'bz) && CFGDEVIDPF2[4]; // rv 0 + assign CFGDEVIDPF2_in[5] = (CFGDEVIDPF2[5] !== 1'bz) && CFGDEVIDPF2[5]; // rv 0 + assign CFGDEVIDPF2_in[6] = (CFGDEVIDPF2[6] !== 1'bz) && CFGDEVIDPF2[6]; // rv 0 + assign CFGDEVIDPF2_in[7] = (CFGDEVIDPF2[7] !== 1'bz) && CFGDEVIDPF2[7]; // rv 0 + assign CFGDEVIDPF2_in[8] = (CFGDEVIDPF2[8] !== 1'bz) && CFGDEVIDPF2[8]; // rv 0 + assign CFGDEVIDPF2_in[9] = (CFGDEVIDPF2[9] !== 1'bz) && CFGDEVIDPF2[9]; // rv 0 + assign CFGDEVIDPF3_in[0] = (CFGDEVIDPF3[0] !== 1'bz) && CFGDEVIDPF3[0]; // rv 0 + assign CFGDEVIDPF3_in[10] = (CFGDEVIDPF3[10] !== 1'bz) && CFGDEVIDPF3[10]; // rv 0 + assign CFGDEVIDPF3_in[11] = (CFGDEVIDPF3[11] !== 1'bz) && CFGDEVIDPF3[11]; // rv 0 + assign CFGDEVIDPF3_in[12] = (CFGDEVIDPF3[12] !== 1'bz) && CFGDEVIDPF3[12]; // rv 0 + assign CFGDEVIDPF3_in[13] = (CFGDEVIDPF3[13] !== 1'bz) && CFGDEVIDPF3[13]; // rv 0 + assign CFGDEVIDPF3_in[14] = (CFGDEVIDPF3[14] !== 1'bz) && CFGDEVIDPF3[14]; // rv 0 + assign CFGDEVIDPF3_in[15] = (CFGDEVIDPF3[15] !== 1'bz) && CFGDEVIDPF3[15]; // rv 0 + assign CFGDEVIDPF3_in[1] = (CFGDEVIDPF3[1] !== 1'bz) && CFGDEVIDPF3[1]; // rv 0 + assign CFGDEVIDPF3_in[2] = (CFGDEVIDPF3[2] !== 1'bz) && CFGDEVIDPF3[2]; // rv 0 + assign CFGDEVIDPF3_in[3] = (CFGDEVIDPF3[3] !== 1'bz) && CFGDEVIDPF3[3]; // rv 0 + assign CFGDEVIDPF3_in[4] = (CFGDEVIDPF3[4] !== 1'bz) && CFGDEVIDPF3[4]; // rv 0 + assign CFGDEVIDPF3_in[5] = (CFGDEVIDPF3[5] !== 1'bz) && CFGDEVIDPF3[5]; // rv 0 + assign CFGDEVIDPF3_in[6] = (CFGDEVIDPF3[6] !== 1'bz) && CFGDEVIDPF3[6]; // rv 0 + assign CFGDEVIDPF3_in[7] = (CFGDEVIDPF3[7] !== 1'bz) && CFGDEVIDPF3[7]; // rv 0 + assign CFGDEVIDPF3_in[8] = (CFGDEVIDPF3[8] !== 1'bz) && CFGDEVIDPF3[8]; // rv 0 + assign CFGDEVIDPF3_in[9] = (CFGDEVIDPF3[9] !== 1'bz) && CFGDEVIDPF3[9]; // rv 0 + assign CFGDSBUSNUMBER_in[0] = (CFGDSBUSNUMBER[0] !== 1'bz) && CFGDSBUSNUMBER[0]; // rv 0 + assign CFGDSBUSNUMBER_in[1] = (CFGDSBUSNUMBER[1] !== 1'bz) && CFGDSBUSNUMBER[1]; // rv 0 + assign CFGDSBUSNUMBER_in[2] = (CFGDSBUSNUMBER[2] !== 1'bz) && CFGDSBUSNUMBER[2]; // rv 0 + assign CFGDSBUSNUMBER_in[3] = (CFGDSBUSNUMBER[3] !== 1'bz) && CFGDSBUSNUMBER[3]; // rv 0 + assign CFGDSBUSNUMBER_in[4] = (CFGDSBUSNUMBER[4] !== 1'bz) && CFGDSBUSNUMBER[4]; // rv 0 + assign CFGDSBUSNUMBER_in[5] = (CFGDSBUSNUMBER[5] !== 1'bz) && CFGDSBUSNUMBER[5]; // rv 0 + assign CFGDSBUSNUMBER_in[6] = (CFGDSBUSNUMBER[6] !== 1'bz) && CFGDSBUSNUMBER[6]; // rv 0 + assign CFGDSBUSNUMBER_in[7] = (CFGDSBUSNUMBER[7] !== 1'bz) && CFGDSBUSNUMBER[7]; // rv 0 + assign CFGDSDEVICENUMBER_in[0] = (CFGDSDEVICENUMBER[0] !== 1'bz) && CFGDSDEVICENUMBER[0]; // rv 0 + assign CFGDSDEVICENUMBER_in[1] = (CFGDSDEVICENUMBER[1] !== 1'bz) && CFGDSDEVICENUMBER[1]; // rv 0 + assign CFGDSDEVICENUMBER_in[2] = (CFGDSDEVICENUMBER[2] !== 1'bz) && CFGDSDEVICENUMBER[2]; // rv 0 + assign CFGDSDEVICENUMBER_in[3] = (CFGDSDEVICENUMBER[3] !== 1'bz) && CFGDSDEVICENUMBER[3]; // rv 0 + assign CFGDSDEVICENUMBER_in[4] = (CFGDSDEVICENUMBER[4] !== 1'bz) && CFGDSDEVICENUMBER[4]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[0] = (CFGDSFUNCTIONNUMBER[0] !== 1'bz) && CFGDSFUNCTIONNUMBER[0]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[1] = (CFGDSFUNCTIONNUMBER[1] !== 1'bz) && CFGDSFUNCTIONNUMBER[1]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[2] = (CFGDSFUNCTIONNUMBER[2] !== 1'bz) && CFGDSFUNCTIONNUMBER[2]; // rv 0 + assign CFGDSN_in[0] = (CFGDSN[0] !== 1'bz) && CFGDSN[0]; // rv 0 + assign CFGDSN_in[10] = (CFGDSN[10] !== 1'bz) && CFGDSN[10]; // rv 0 + assign CFGDSN_in[11] = (CFGDSN[11] !== 1'bz) && CFGDSN[11]; // rv 0 + assign CFGDSN_in[12] = (CFGDSN[12] !== 1'bz) && CFGDSN[12]; // rv 0 + assign CFGDSN_in[13] = (CFGDSN[13] !== 1'bz) && CFGDSN[13]; // rv 0 + assign CFGDSN_in[14] = (CFGDSN[14] !== 1'bz) && CFGDSN[14]; // rv 0 + assign CFGDSN_in[15] = (CFGDSN[15] !== 1'bz) && CFGDSN[15]; // rv 0 + assign CFGDSN_in[16] = (CFGDSN[16] !== 1'bz) && CFGDSN[16]; // rv 0 + assign CFGDSN_in[17] = (CFGDSN[17] !== 1'bz) && CFGDSN[17]; // rv 0 + assign CFGDSN_in[18] = (CFGDSN[18] !== 1'bz) && CFGDSN[18]; // rv 0 + assign CFGDSN_in[19] = (CFGDSN[19] !== 1'bz) && CFGDSN[19]; // rv 0 + assign CFGDSN_in[1] = (CFGDSN[1] !== 1'bz) && CFGDSN[1]; // rv 0 + assign CFGDSN_in[20] = (CFGDSN[20] !== 1'bz) && CFGDSN[20]; // rv 0 + assign CFGDSN_in[21] = (CFGDSN[21] !== 1'bz) && CFGDSN[21]; // rv 0 + assign CFGDSN_in[22] = (CFGDSN[22] !== 1'bz) && CFGDSN[22]; // rv 0 + assign CFGDSN_in[23] = (CFGDSN[23] !== 1'bz) && CFGDSN[23]; // rv 0 + assign CFGDSN_in[24] = (CFGDSN[24] !== 1'bz) && CFGDSN[24]; // rv 0 + assign CFGDSN_in[25] = (CFGDSN[25] !== 1'bz) && CFGDSN[25]; // rv 0 + assign CFGDSN_in[26] = (CFGDSN[26] !== 1'bz) && CFGDSN[26]; // rv 0 + assign CFGDSN_in[27] = (CFGDSN[27] !== 1'bz) && CFGDSN[27]; // rv 0 + assign CFGDSN_in[28] = (CFGDSN[28] !== 1'bz) && CFGDSN[28]; // rv 0 + assign CFGDSN_in[29] = (CFGDSN[29] !== 1'bz) && CFGDSN[29]; // rv 0 + assign CFGDSN_in[2] = (CFGDSN[2] !== 1'bz) && CFGDSN[2]; // rv 0 + assign CFGDSN_in[30] = (CFGDSN[30] !== 1'bz) && CFGDSN[30]; // rv 0 + assign CFGDSN_in[31] = (CFGDSN[31] !== 1'bz) && CFGDSN[31]; // rv 0 + assign CFGDSN_in[32] = (CFGDSN[32] !== 1'bz) && CFGDSN[32]; // rv 0 + assign CFGDSN_in[33] = (CFGDSN[33] !== 1'bz) && CFGDSN[33]; // rv 0 + assign CFGDSN_in[34] = (CFGDSN[34] !== 1'bz) && CFGDSN[34]; // rv 0 + assign CFGDSN_in[35] = (CFGDSN[35] !== 1'bz) && CFGDSN[35]; // rv 0 + assign CFGDSN_in[36] = (CFGDSN[36] !== 1'bz) && CFGDSN[36]; // rv 0 + assign CFGDSN_in[37] = (CFGDSN[37] !== 1'bz) && CFGDSN[37]; // rv 0 + assign CFGDSN_in[38] = (CFGDSN[38] !== 1'bz) && CFGDSN[38]; // rv 0 + assign CFGDSN_in[39] = (CFGDSN[39] !== 1'bz) && CFGDSN[39]; // rv 0 + assign CFGDSN_in[3] = (CFGDSN[3] !== 1'bz) && CFGDSN[3]; // rv 0 + assign CFGDSN_in[40] = (CFGDSN[40] !== 1'bz) && CFGDSN[40]; // rv 0 + assign CFGDSN_in[41] = (CFGDSN[41] !== 1'bz) && CFGDSN[41]; // rv 0 + assign CFGDSN_in[42] = (CFGDSN[42] !== 1'bz) && CFGDSN[42]; // rv 0 + assign CFGDSN_in[43] = (CFGDSN[43] !== 1'bz) && CFGDSN[43]; // rv 0 + assign CFGDSN_in[44] = (CFGDSN[44] !== 1'bz) && CFGDSN[44]; // rv 0 + assign CFGDSN_in[45] = (CFGDSN[45] !== 1'bz) && CFGDSN[45]; // rv 0 + assign CFGDSN_in[46] = (CFGDSN[46] !== 1'bz) && CFGDSN[46]; // rv 0 + assign CFGDSN_in[47] = (CFGDSN[47] !== 1'bz) && CFGDSN[47]; // rv 0 + assign CFGDSN_in[48] = (CFGDSN[48] !== 1'bz) && CFGDSN[48]; // rv 0 + assign CFGDSN_in[49] = (CFGDSN[49] !== 1'bz) && CFGDSN[49]; // rv 0 + assign CFGDSN_in[4] = (CFGDSN[4] !== 1'bz) && CFGDSN[4]; // rv 0 + assign CFGDSN_in[50] = (CFGDSN[50] !== 1'bz) && CFGDSN[50]; // rv 0 + assign CFGDSN_in[51] = (CFGDSN[51] !== 1'bz) && CFGDSN[51]; // rv 0 + assign CFGDSN_in[52] = (CFGDSN[52] !== 1'bz) && CFGDSN[52]; // rv 0 + assign CFGDSN_in[53] = (CFGDSN[53] !== 1'bz) && CFGDSN[53]; // rv 0 + assign CFGDSN_in[54] = (CFGDSN[54] !== 1'bz) && CFGDSN[54]; // rv 0 + assign CFGDSN_in[55] = (CFGDSN[55] !== 1'bz) && CFGDSN[55]; // rv 0 + assign CFGDSN_in[56] = (CFGDSN[56] !== 1'bz) && CFGDSN[56]; // rv 0 + assign CFGDSN_in[57] = (CFGDSN[57] !== 1'bz) && CFGDSN[57]; // rv 0 + assign CFGDSN_in[58] = (CFGDSN[58] !== 1'bz) && CFGDSN[58]; // rv 0 + assign CFGDSN_in[59] = (CFGDSN[59] !== 1'bz) && CFGDSN[59]; // rv 0 + assign CFGDSN_in[5] = (CFGDSN[5] !== 1'bz) && CFGDSN[5]; // rv 0 + assign CFGDSN_in[60] = (CFGDSN[60] !== 1'bz) && CFGDSN[60]; // rv 0 + assign CFGDSN_in[61] = (CFGDSN[61] !== 1'bz) && CFGDSN[61]; // rv 0 + assign CFGDSN_in[62] = (CFGDSN[62] !== 1'bz) && CFGDSN[62]; // rv 0 + assign CFGDSN_in[63] = (CFGDSN[63] !== 1'bz) && CFGDSN[63]; // rv 0 + assign CFGDSN_in[6] = (CFGDSN[6] !== 1'bz) && CFGDSN[6]; // rv 0 + assign CFGDSN_in[7] = (CFGDSN[7] !== 1'bz) && CFGDSN[7]; // rv 0 + assign CFGDSN_in[8] = (CFGDSN[8] !== 1'bz) && CFGDSN[8]; // rv 0 + assign CFGDSN_in[9] = (CFGDSN[9] !== 1'bz) && CFGDSN[9]; // rv 0 + assign CFGDSPORTNUMBER_in[0] = (CFGDSPORTNUMBER[0] !== 1'bz) && CFGDSPORTNUMBER[0]; // rv 0 + assign CFGDSPORTNUMBER_in[1] = (CFGDSPORTNUMBER[1] !== 1'bz) && CFGDSPORTNUMBER[1]; // rv 0 + assign CFGDSPORTNUMBER_in[2] = (CFGDSPORTNUMBER[2] !== 1'bz) && CFGDSPORTNUMBER[2]; // rv 0 + assign CFGDSPORTNUMBER_in[3] = (CFGDSPORTNUMBER[3] !== 1'bz) && CFGDSPORTNUMBER[3]; // rv 0 + assign CFGDSPORTNUMBER_in[4] = (CFGDSPORTNUMBER[4] !== 1'bz) && CFGDSPORTNUMBER[4]; // rv 0 + assign CFGDSPORTNUMBER_in[5] = (CFGDSPORTNUMBER[5] !== 1'bz) && CFGDSPORTNUMBER[5]; // rv 0 + assign CFGDSPORTNUMBER_in[6] = (CFGDSPORTNUMBER[6] !== 1'bz) && CFGDSPORTNUMBER[6]; // rv 0 + assign CFGDSPORTNUMBER_in[7] = (CFGDSPORTNUMBER[7] !== 1'bz) && CFGDSPORTNUMBER[7]; // rv 0 + assign CFGERRCORIN_in = (CFGERRCORIN !== 1'bz) && CFGERRCORIN; // rv 0 + assign CFGERRUNCORIN_in = (CFGERRUNCORIN !== 1'bz) && CFGERRUNCORIN; // rv 0 + assign CFGEXTREADDATAVALID_in = (CFGEXTREADDATAVALID !== 1'bz) && CFGEXTREADDATAVALID; // rv 0 + assign CFGEXTREADDATA_in[0] = (CFGEXTREADDATA[0] !== 1'bz) && CFGEXTREADDATA[0]; // rv 0 + assign CFGEXTREADDATA_in[10] = (CFGEXTREADDATA[10] !== 1'bz) && CFGEXTREADDATA[10]; // rv 0 + assign CFGEXTREADDATA_in[11] = (CFGEXTREADDATA[11] !== 1'bz) && CFGEXTREADDATA[11]; // rv 0 + assign CFGEXTREADDATA_in[12] = (CFGEXTREADDATA[12] !== 1'bz) && CFGEXTREADDATA[12]; // rv 0 + assign CFGEXTREADDATA_in[13] = (CFGEXTREADDATA[13] !== 1'bz) && CFGEXTREADDATA[13]; // rv 0 + assign CFGEXTREADDATA_in[14] = (CFGEXTREADDATA[14] !== 1'bz) && CFGEXTREADDATA[14]; // rv 0 + assign CFGEXTREADDATA_in[15] = (CFGEXTREADDATA[15] !== 1'bz) && CFGEXTREADDATA[15]; // rv 0 + assign CFGEXTREADDATA_in[16] = (CFGEXTREADDATA[16] !== 1'bz) && CFGEXTREADDATA[16]; // rv 0 + assign CFGEXTREADDATA_in[17] = (CFGEXTREADDATA[17] !== 1'bz) && CFGEXTREADDATA[17]; // rv 0 + assign CFGEXTREADDATA_in[18] = (CFGEXTREADDATA[18] !== 1'bz) && CFGEXTREADDATA[18]; // rv 0 + assign CFGEXTREADDATA_in[19] = (CFGEXTREADDATA[19] !== 1'bz) && CFGEXTREADDATA[19]; // rv 0 + assign CFGEXTREADDATA_in[1] = (CFGEXTREADDATA[1] !== 1'bz) && CFGEXTREADDATA[1]; // rv 0 + assign CFGEXTREADDATA_in[20] = (CFGEXTREADDATA[20] !== 1'bz) && CFGEXTREADDATA[20]; // rv 0 + assign CFGEXTREADDATA_in[21] = (CFGEXTREADDATA[21] !== 1'bz) && CFGEXTREADDATA[21]; // rv 0 + assign CFGEXTREADDATA_in[22] = (CFGEXTREADDATA[22] !== 1'bz) && CFGEXTREADDATA[22]; // rv 0 + assign CFGEXTREADDATA_in[23] = (CFGEXTREADDATA[23] !== 1'bz) && CFGEXTREADDATA[23]; // rv 0 + assign CFGEXTREADDATA_in[24] = (CFGEXTREADDATA[24] !== 1'bz) && CFGEXTREADDATA[24]; // rv 0 + assign CFGEXTREADDATA_in[25] = (CFGEXTREADDATA[25] !== 1'bz) && CFGEXTREADDATA[25]; // rv 0 + assign CFGEXTREADDATA_in[26] = (CFGEXTREADDATA[26] !== 1'bz) && CFGEXTREADDATA[26]; // rv 0 + assign CFGEXTREADDATA_in[27] = (CFGEXTREADDATA[27] !== 1'bz) && CFGEXTREADDATA[27]; // rv 0 + assign CFGEXTREADDATA_in[28] = (CFGEXTREADDATA[28] !== 1'bz) && CFGEXTREADDATA[28]; // rv 0 + assign CFGEXTREADDATA_in[29] = (CFGEXTREADDATA[29] !== 1'bz) && CFGEXTREADDATA[29]; // rv 0 + assign CFGEXTREADDATA_in[2] = (CFGEXTREADDATA[2] !== 1'bz) && CFGEXTREADDATA[2]; // rv 0 + assign CFGEXTREADDATA_in[30] = (CFGEXTREADDATA[30] !== 1'bz) && CFGEXTREADDATA[30]; // rv 0 + assign CFGEXTREADDATA_in[31] = (CFGEXTREADDATA[31] !== 1'bz) && CFGEXTREADDATA[31]; // rv 0 + assign CFGEXTREADDATA_in[3] = (CFGEXTREADDATA[3] !== 1'bz) && CFGEXTREADDATA[3]; // rv 0 + assign CFGEXTREADDATA_in[4] = (CFGEXTREADDATA[4] !== 1'bz) && CFGEXTREADDATA[4]; // rv 0 + assign CFGEXTREADDATA_in[5] = (CFGEXTREADDATA[5] !== 1'bz) && CFGEXTREADDATA[5]; // rv 0 + assign CFGEXTREADDATA_in[6] = (CFGEXTREADDATA[6] !== 1'bz) && CFGEXTREADDATA[6]; // rv 0 + assign CFGEXTREADDATA_in[7] = (CFGEXTREADDATA[7] !== 1'bz) && CFGEXTREADDATA[7]; // rv 0 + assign CFGEXTREADDATA_in[8] = (CFGEXTREADDATA[8] !== 1'bz) && CFGEXTREADDATA[8]; // rv 0 + assign CFGEXTREADDATA_in[9] = (CFGEXTREADDATA[9] !== 1'bz) && CFGEXTREADDATA[9]; // rv 0 + assign CFGFCSEL_in[0] = (CFGFCSEL[0] !== 1'bz) && CFGFCSEL[0]; // rv 0 + assign CFGFCSEL_in[1] = (CFGFCSEL[1] !== 1'bz) && CFGFCSEL[1]; // rv 0 + assign CFGFCSEL_in[2] = (CFGFCSEL[2] !== 1'bz) && CFGFCSEL[2]; // rv 0 + assign CFGFLRDONE_in[0] = (CFGFLRDONE[0] !== 1'bz) && CFGFLRDONE[0]; // rv 0 + assign CFGFLRDONE_in[1] = (CFGFLRDONE[1] !== 1'bz) && CFGFLRDONE[1]; // rv 0 + assign CFGFLRDONE_in[2] = (CFGFLRDONE[2] !== 1'bz) && CFGFLRDONE[2]; // rv 0 + assign CFGFLRDONE_in[3] = (CFGFLRDONE[3] !== 1'bz) && CFGFLRDONE[3]; // rv 0 + assign CFGHOTRESETIN_in = (CFGHOTRESETIN !== 1'bz) && CFGHOTRESETIN; // rv 0 + assign CFGINTERRUPTINT_in[0] = (CFGINTERRUPTINT[0] !== 1'bz) && CFGINTERRUPTINT[0]; // rv 0 + assign CFGINTERRUPTINT_in[1] = (CFGINTERRUPTINT[1] !== 1'bz) && CFGINTERRUPTINT[1]; // rv 0 + assign CFGINTERRUPTINT_in[2] = (CFGINTERRUPTINT[2] !== 1'bz) && CFGINTERRUPTINT[2]; // rv 0 + assign CFGINTERRUPTINT_in[3] = (CFGINTERRUPTINT[3] !== 1'bz) && CFGINTERRUPTINT[3]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[0] = (CFGINTERRUPTMSIATTR[0] !== 1'bz) && CFGINTERRUPTMSIATTR[0]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[1] = (CFGINTERRUPTMSIATTR[1] !== 1'bz) && CFGINTERRUPTMSIATTR[1]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[2] = (CFGINTERRUPTMSIATTR[2] !== 1'bz) && CFGINTERRUPTMSIATTR[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[0] = (CFGINTERRUPTMSIFUNCTIONNUMBER[0] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[0]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[1] = (CFGINTERRUPTMSIFUNCTIONNUMBER[1] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[1]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[2] = (CFGINTERRUPTMSIFUNCTIONNUMBER[2] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[3] = (CFGINTERRUPTMSIFUNCTIONNUMBER[3] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[3]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[4] = (CFGINTERRUPTMSIFUNCTIONNUMBER[4] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[4]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[5] = (CFGINTERRUPTMSIFUNCTIONNUMBER[5] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[5]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[6] = (CFGINTERRUPTMSIFUNCTIONNUMBER[6] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[6]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[7] = (CFGINTERRUPTMSIFUNCTIONNUMBER[7] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[0] = (CFGINTERRUPTMSIINT[0] !== 1'bz) && CFGINTERRUPTMSIINT[0]; // rv 0 + assign CFGINTERRUPTMSIINT_in[10] = (CFGINTERRUPTMSIINT[10] !== 1'bz) && CFGINTERRUPTMSIINT[10]; // rv 0 + assign CFGINTERRUPTMSIINT_in[11] = (CFGINTERRUPTMSIINT[11] !== 1'bz) && CFGINTERRUPTMSIINT[11]; // rv 0 + assign CFGINTERRUPTMSIINT_in[12] = (CFGINTERRUPTMSIINT[12] !== 1'bz) && CFGINTERRUPTMSIINT[12]; // rv 0 + assign CFGINTERRUPTMSIINT_in[13] = (CFGINTERRUPTMSIINT[13] !== 1'bz) && CFGINTERRUPTMSIINT[13]; // rv 0 + assign CFGINTERRUPTMSIINT_in[14] = (CFGINTERRUPTMSIINT[14] !== 1'bz) && CFGINTERRUPTMSIINT[14]; // rv 0 + assign CFGINTERRUPTMSIINT_in[15] = (CFGINTERRUPTMSIINT[15] !== 1'bz) && CFGINTERRUPTMSIINT[15]; // rv 0 + assign CFGINTERRUPTMSIINT_in[16] = (CFGINTERRUPTMSIINT[16] !== 1'bz) && CFGINTERRUPTMSIINT[16]; // rv 0 + assign CFGINTERRUPTMSIINT_in[17] = (CFGINTERRUPTMSIINT[17] !== 1'bz) && CFGINTERRUPTMSIINT[17]; // rv 0 + assign CFGINTERRUPTMSIINT_in[18] = (CFGINTERRUPTMSIINT[18] !== 1'bz) && CFGINTERRUPTMSIINT[18]; // rv 0 + assign CFGINTERRUPTMSIINT_in[19] = (CFGINTERRUPTMSIINT[19] !== 1'bz) && CFGINTERRUPTMSIINT[19]; // rv 0 + assign CFGINTERRUPTMSIINT_in[1] = (CFGINTERRUPTMSIINT[1] !== 1'bz) && CFGINTERRUPTMSIINT[1]; // rv 0 + assign CFGINTERRUPTMSIINT_in[20] = (CFGINTERRUPTMSIINT[20] !== 1'bz) && CFGINTERRUPTMSIINT[20]; // rv 0 + assign CFGINTERRUPTMSIINT_in[21] = (CFGINTERRUPTMSIINT[21] !== 1'bz) && CFGINTERRUPTMSIINT[21]; // rv 0 + assign CFGINTERRUPTMSIINT_in[22] = (CFGINTERRUPTMSIINT[22] !== 1'bz) && CFGINTERRUPTMSIINT[22]; // rv 0 + assign CFGINTERRUPTMSIINT_in[23] = (CFGINTERRUPTMSIINT[23] !== 1'bz) && CFGINTERRUPTMSIINT[23]; // rv 0 + assign CFGINTERRUPTMSIINT_in[24] = (CFGINTERRUPTMSIINT[24] !== 1'bz) && CFGINTERRUPTMSIINT[24]; // rv 0 + assign CFGINTERRUPTMSIINT_in[25] = (CFGINTERRUPTMSIINT[25] !== 1'bz) && CFGINTERRUPTMSIINT[25]; // rv 0 + assign CFGINTERRUPTMSIINT_in[26] = (CFGINTERRUPTMSIINT[26] !== 1'bz) && CFGINTERRUPTMSIINT[26]; // rv 0 + assign CFGINTERRUPTMSIINT_in[27] = (CFGINTERRUPTMSIINT[27] !== 1'bz) && CFGINTERRUPTMSIINT[27]; // rv 0 + assign CFGINTERRUPTMSIINT_in[28] = (CFGINTERRUPTMSIINT[28] !== 1'bz) && CFGINTERRUPTMSIINT[28]; // rv 0 + assign CFGINTERRUPTMSIINT_in[29] = (CFGINTERRUPTMSIINT[29] !== 1'bz) && CFGINTERRUPTMSIINT[29]; // rv 0 + assign CFGINTERRUPTMSIINT_in[2] = (CFGINTERRUPTMSIINT[2] !== 1'bz) && CFGINTERRUPTMSIINT[2]; // rv 0 + assign CFGINTERRUPTMSIINT_in[30] = (CFGINTERRUPTMSIINT[30] !== 1'bz) && CFGINTERRUPTMSIINT[30]; // rv 0 + assign CFGINTERRUPTMSIINT_in[31] = (CFGINTERRUPTMSIINT[31] !== 1'bz) && CFGINTERRUPTMSIINT[31]; // rv 0 + assign CFGINTERRUPTMSIINT_in[3] = (CFGINTERRUPTMSIINT[3] !== 1'bz) && CFGINTERRUPTMSIINT[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[4] = (CFGINTERRUPTMSIINT[4] !== 1'bz) && CFGINTERRUPTMSIINT[4]; // rv 0 + assign CFGINTERRUPTMSIINT_in[5] = (CFGINTERRUPTMSIINT[5] !== 1'bz) && CFGINTERRUPTMSIINT[5]; // rv 0 + assign CFGINTERRUPTMSIINT_in[6] = (CFGINTERRUPTMSIINT[6] !== 1'bz) && CFGINTERRUPTMSIINT[6]; // rv 0 + assign CFGINTERRUPTMSIINT_in[7] = (CFGINTERRUPTMSIINT[7] !== 1'bz) && CFGINTERRUPTMSIINT[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[8] = (CFGINTERRUPTMSIINT[8] !== 1'bz) && CFGINTERRUPTMSIINT[8]; // rv 0 + assign CFGINTERRUPTMSIINT_in[9] = (CFGINTERRUPTMSIINT[9] !== 1'bz) && CFGINTERRUPTMSIINT[9]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[0] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[1] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[0] = (CFGINTERRUPTMSIPENDINGSTATUS[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[10] = (CFGINTERRUPTMSIPENDINGSTATUS[10] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[10]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[11] = (CFGINTERRUPTMSIPENDINGSTATUS[11] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[11]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[12] = (CFGINTERRUPTMSIPENDINGSTATUS[12] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[12]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[13] = (CFGINTERRUPTMSIPENDINGSTATUS[13] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[13]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[14] = (CFGINTERRUPTMSIPENDINGSTATUS[14] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[14]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[15] = (CFGINTERRUPTMSIPENDINGSTATUS[15] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[15]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[16] = (CFGINTERRUPTMSIPENDINGSTATUS[16] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[16]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[17] = (CFGINTERRUPTMSIPENDINGSTATUS[17] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[17]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[18] = (CFGINTERRUPTMSIPENDINGSTATUS[18] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[18]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[19] = (CFGINTERRUPTMSIPENDINGSTATUS[19] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[19]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[1] = (CFGINTERRUPTMSIPENDINGSTATUS[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[20] = (CFGINTERRUPTMSIPENDINGSTATUS[20] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[20]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[21] = (CFGINTERRUPTMSIPENDINGSTATUS[21] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[21]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[22] = (CFGINTERRUPTMSIPENDINGSTATUS[22] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[22]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[23] = (CFGINTERRUPTMSIPENDINGSTATUS[23] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[23]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[24] = (CFGINTERRUPTMSIPENDINGSTATUS[24] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[24]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[25] = (CFGINTERRUPTMSIPENDINGSTATUS[25] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[25]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[26] = (CFGINTERRUPTMSIPENDINGSTATUS[26] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[26]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[27] = (CFGINTERRUPTMSIPENDINGSTATUS[27] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[27]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[28] = (CFGINTERRUPTMSIPENDINGSTATUS[28] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[28]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[29] = (CFGINTERRUPTMSIPENDINGSTATUS[29] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[29]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[2] = (CFGINTERRUPTMSIPENDINGSTATUS[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[30] = (CFGINTERRUPTMSIPENDINGSTATUS[30] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[30]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[31] = (CFGINTERRUPTMSIPENDINGSTATUS[31] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[31]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[3] = (CFGINTERRUPTMSIPENDINGSTATUS[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[4] = (CFGINTERRUPTMSIPENDINGSTATUS[4] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[4]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[5] = (CFGINTERRUPTMSIPENDINGSTATUS[5] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[5]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[6] = (CFGINTERRUPTMSIPENDINGSTATUS[6] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[6]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[7] = (CFGINTERRUPTMSIPENDINGSTATUS[7] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[7]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[8] = (CFGINTERRUPTMSIPENDINGSTATUS[8] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[8]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[9] = (CFGINTERRUPTMSIPENDINGSTATUS[9] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[9]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[0] = (CFGINTERRUPTMSISELECT[0] !== 1'bz) && CFGINTERRUPTMSISELECT[0]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[1] = (CFGINTERRUPTMSISELECT[1] !== 1'bz) && CFGINTERRUPTMSISELECT[1]; // rv 0 + assign CFGINTERRUPTMSITPHPRESENT_in = (CFGINTERRUPTMSITPHPRESENT !== 1'bz) && CFGINTERRUPTMSITPHPRESENT; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[0] = (CFGINTERRUPTMSITPHSTTAG[0] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[0]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[1] = (CFGINTERRUPTMSITPHSTTAG[1] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[1]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[2] = (CFGINTERRUPTMSITPHSTTAG[2] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[2]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[3] = (CFGINTERRUPTMSITPHSTTAG[3] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[3]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[4] = (CFGINTERRUPTMSITPHSTTAG[4] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[4]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[5] = (CFGINTERRUPTMSITPHSTTAG[5] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[5]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[6] = (CFGINTERRUPTMSITPHSTTAG[6] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[6]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[7] = (CFGINTERRUPTMSITPHSTTAG[7] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[7]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[0] = (CFGINTERRUPTMSITPHTYPE[0] !== 1'bz) && CFGINTERRUPTMSITPHTYPE[0]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[1] = (CFGINTERRUPTMSITPHTYPE[1] !== 1'bz) && CFGINTERRUPTMSITPHTYPE[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[0] = (CFGINTERRUPTMSIXADDRESS[0] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[0]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[10] = (CFGINTERRUPTMSIXADDRESS[10] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[10]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[11] = (CFGINTERRUPTMSIXADDRESS[11] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[11]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[12] = (CFGINTERRUPTMSIXADDRESS[12] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[12]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[13] = (CFGINTERRUPTMSIXADDRESS[13] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[13]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[14] = (CFGINTERRUPTMSIXADDRESS[14] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[14]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[15] = (CFGINTERRUPTMSIXADDRESS[15] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[15]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[16] = (CFGINTERRUPTMSIXADDRESS[16] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[16]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[17] = (CFGINTERRUPTMSIXADDRESS[17] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[17]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[18] = (CFGINTERRUPTMSIXADDRESS[18] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[18]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[19] = (CFGINTERRUPTMSIXADDRESS[19] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[19]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[1] = (CFGINTERRUPTMSIXADDRESS[1] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[20] = (CFGINTERRUPTMSIXADDRESS[20] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[20]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[21] = (CFGINTERRUPTMSIXADDRESS[21] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[21]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[22] = (CFGINTERRUPTMSIXADDRESS[22] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[22]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[23] = (CFGINTERRUPTMSIXADDRESS[23] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[23]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[24] = (CFGINTERRUPTMSIXADDRESS[24] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[24]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[25] = (CFGINTERRUPTMSIXADDRESS[25] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[25]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[26] = (CFGINTERRUPTMSIXADDRESS[26] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[26]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[27] = (CFGINTERRUPTMSIXADDRESS[27] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[27]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[28] = (CFGINTERRUPTMSIXADDRESS[28] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[28]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[29] = (CFGINTERRUPTMSIXADDRESS[29] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[29]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[2] = (CFGINTERRUPTMSIXADDRESS[2] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[2]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[30] = (CFGINTERRUPTMSIXADDRESS[30] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[30]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[31] = (CFGINTERRUPTMSIXADDRESS[31] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[31]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[32] = (CFGINTERRUPTMSIXADDRESS[32] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[32]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[33] = (CFGINTERRUPTMSIXADDRESS[33] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[33]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[34] = (CFGINTERRUPTMSIXADDRESS[34] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[34]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[35] = (CFGINTERRUPTMSIXADDRESS[35] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[35]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[36] = (CFGINTERRUPTMSIXADDRESS[36] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[36]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[37] = (CFGINTERRUPTMSIXADDRESS[37] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[37]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[38] = (CFGINTERRUPTMSIXADDRESS[38] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[38]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[39] = (CFGINTERRUPTMSIXADDRESS[39] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[39]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[3] = (CFGINTERRUPTMSIXADDRESS[3] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[3]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[40] = (CFGINTERRUPTMSIXADDRESS[40] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[40]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[41] = (CFGINTERRUPTMSIXADDRESS[41] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[41]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[42] = (CFGINTERRUPTMSIXADDRESS[42] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[42]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[43] = (CFGINTERRUPTMSIXADDRESS[43] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[43]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[44] = (CFGINTERRUPTMSIXADDRESS[44] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[44]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[45] = (CFGINTERRUPTMSIXADDRESS[45] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[45]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[46] = (CFGINTERRUPTMSIXADDRESS[46] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[46]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[47] = (CFGINTERRUPTMSIXADDRESS[47] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[47]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[48] = (CFGINTERRUPTMSIXADDRESS[48] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[48]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[49] = (CFGINTERRUPTMSIXADDRESS[49] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[49]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[4] = (CFGINTERRUPTMSIXADDRESS[4] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[4]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[50] = (CFGINTERRUPTMSIXADDRESS[50] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[50]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[51] = (CFGINTERRUPTMSIXADDRESS[51] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[51]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[52] = (CFGINTERRUPTMSIXADDRESS[52] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[52]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[53] = (CFGINTERRUPTMSIXADDRESS[53] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[53]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[54] = (CFGINTERRUPTMSIXADDRESS[54] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[54]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[55] = (CFGINTERRUPTMSIXADDRESS[55] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[55]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[56] = (CFGINTERRUPTMSIXADDRESS[56] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[56]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[57] = (CFGINTERRUPTMSIXADDRESS[57] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[57]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[58] = (CFGINTERRUPTMSIXADDRESS[58] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[58]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[59] = (CFGINTERRUPTMSIXADDRESS[59] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[59]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[5] = (CFGINTERRUPTMSIXADDRESS[5] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[5]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[60] = (CFGINTERRUPTMSIXADDRESS[60] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[60]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[61] = (CFGINTERRUPTMSIXADDRESS[61] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[61]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[62] = (CFGINTERRUPTMSIXADDRESS[62] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[62]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[63] = (CFGINTERRUPTMSIXADDRESS[63] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[63]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[6] = (CFGINTERRUPTMSIXADDRESS[6] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[6]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[7] = (CFGINTERRUPTMSIXADDRESS[7] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[7]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[8] = (CFGINTERRUPTMSIXADDRESS[8] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[8]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[9] = (CFGINTERRUPTMSIXADDRESS[9] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[9]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[0] = (CFGINTERRUPTMSIXDATA[0] !== 1'bz) && CFGINTERRUPTMSIXDATA[0]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[10] = (CFGINTERRUPTMSIXDATA[10] !== 1'bz) && CFGINTERRUPTMSIXDATA[10]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[11] = (CFGINTERRUPTMSIXDATA[11] !== 1'bz) && CFGINTERRUPTMSIXDATA[11]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[12] = (CFGINTERRUPTMSIXDATA[12] !== 1'bz) && CFGINTERRUPTMSIXDATA[12]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[13] = (CFGINTERRUPTMSIXDATA[13] !== 1'bz) && CFGINTERRUPTMSIXDATA[13]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[14] = (CFGINTERRUPTMSIXDATA[14] !== 1'bz) && CFGINTERRUPTMSIXDATA[14]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[15] = (CFGINTERRUPTMSIXDATA[15] !== 1'bz) && CFGINTERRUPTMSIXDATA[15]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[16] = (CFGINTERRUPTMSIXDATA[16] !== 1'bz) && CFGINTERRUPTMSIXDATA[16]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[17] = (CFGINTERRUPTMSIXDATA[17] !== 1'bz) && CFGINTERRUPTMSIXDATA[17]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[18] = (CFGINTERRUPTMSIXDATA[18] !== 1'bz) && CFGINTERRUPTMSIXDATA[18]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[19] = (CFGINTERRUPTMSIXDATA[19] !== 1'bz) && CFGINTERRUPTMSIXDATA[19]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[1] = (CFGINTERRUPTMSIXDATA[1] !== 1'bz) && CFGINTERRUPTMSIXDATA[1]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[20] = (CFGINTERRUPTMSIXDATA[20] !== 1'bz) && CFGINTERRUPTMSIXDATA[20]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[21] = (CFGINTERRUPTMSIXDATA[21] !== 1'bz) && CFGINTERRUPTMSIXDATA[21]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[22] = (CFGINTERRUPTMSIXDATA[22] !== 1'bz) && CFGINTERRUPTMSIXDATA[22]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[23] = (CFGINTERRUPTMSIXDATA[23] !== 1'bz) && CFGINTERRUPTMSIXDATA[23]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[24] = (CFGINTERRUPTMSIXDATA[24] !== 1'bz) && CFGINTERRUPTMSIXDATA[24]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[25] = (CFGINTERRUPTMSIXDATA[25] !== 1'bz) && CFGINTERRUPTMSIXDATA[25]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[26] = (CFGINTERRUPTMSIXDATA[26] !== 1'bz) && CFGINTERRUPTMSIXDATA[26]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[27] = (CFGINTERRUPTMSIXDATA[27] !== 1'bz) && CFGINTERRUPTMSIXDATA[27]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[28] = (CFGINTERRUPTMSIXDATA[28] !== 1'bz) && CFGINTERRUPTMSIXDATA[28]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[29] = (CFGINTERRUPTMSIXDATA[29] !== 1'bz) && CFGINTERRUPTMSIXDATA[29]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[2] = (CFGINTERRUPTMSIXDATA[2] !== 1'bz) && CFGINTERRUPTMSIXDATA[2]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[30] = (CFGINTERRUPTMSIXDATA[30] !== 1'bz) && CFGINTERRUPTMSIXDATA[30]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[31] = (CFGINTERRUPTMSIXDATA[31] !== 1'bz) && CFGINTERRUPTMSIXDATA[31]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[3] = (CFGINTERRUPTMSIXDATA[3] !== 1'bz) && CFGINTERRUPTMSIXDATA[3]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[4] = (CFGINTERRUPTMSIXDATA[4] !== 1'bz) && CFGINTERRUPTMSIXDATA[4]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[5] = (CFGINTERRUPTMSIXDATA[5] !== 1'bz) && CFGINTERRUPTMSIXDATA[5]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[6] = (CFGINTERRUPTMSIXDATA[6] !== 1'bz) && CFGINTERRUPTMSIXDATA[6]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[7] = (CFGINTERRUPTMSIXDATA[7] !== 1'bz) && CFGINTERRUPTMSIXDATA[7]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[8] = (CFGINTERRUPTMSIXDATA[8] !== 1'bz) && CFGINTERRUPTMSIXDATA[8]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[9] = (CFGINTERRUPTMSIXDATA[9] !== 1'bz) && CFGINTERRUPTMSIXDATA[9]; // rv 0 + assign CFGINTERRUPTMSIXINT_in = (CFGINTERRUPTMSIXINT !== 1'bz) && CFGINTERRUPTMSIXINT; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[0] = (CFGINTERRUPTMSIXVECPENDING[0] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING[0]; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[1] = (CFGINTERRUPTMSIXVECPENDING[1] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[0] = (CFGINTERRUPTPENDING[0] !== 1'bz) && CFGINTERRUPTPENDING[0]; // rv 0 + assign CFGINTERRUPTPENDING_in[1] = (CFGINTERRUPTPENDING[1] !== 1'bz) && CFGINTERRUPTPENDING[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[2] = (CFGINTERRUPTPENDING[2] !== 1'bz) && CFGINTERRUPTPENDING[2]; // rv 0 + assign CFGINTERRUPTPENDING_in[3] = (CFGINTERRUPTPENDING[3] !== 1'bz) && CFGINTERRUPTPENDING[3]; // rv 0 + assign CFGLINKTRAININGENABLE_in = (CFGLINKTRAININGENABLE === 1'bz) || CFGLINKTRAININGENABLE; // rv 1 + assign CFGMGMTADDR_in[0] = (CFGMGMTADDR[0] !== 1'bz) && CFGMGMTADDR[0]; // rv 0 + assign CFGMGMTADDR_in[1] = (CFGMGMTADDR[1] !== 1'bz) && CFGMGMTADDR[1]; // rv 0 + assign CFGMGMTADDR_in[2] = (CFGMGMTADDR[2] !== 1'bz) && CFGMGMTADDR[2]; // rv 0 + assign CFGMGMTADDR_in[3] = (CFGMGMTADDR[3] !== 1'bz) && CFGMGMTADDR[3]; // rv 0 + assign CFGMGMTADDR_in[4] = (CFGMGMTADDR[4] !== 1'bz) && CFGMGMTADDR[4]; // rv 0 + assign CFGMGMTADDR_in[5] = (CFGMGMTADDR[5] !== 1'bz) && CFGMGMTADDR[5]; // rv 0 + assign CFGMGMTADDR_in[6] = (CFGMGMTADDR[6] !== 1'bz) && CFGMGMTADDR[6]; // rv 0 + assign CFGMGMTADDR_in[7] = (CFGMGMTADDR[7] !== 1'bz) && CFGMGMTADDR[7]; // rv 0 + assign CFGMGMTADDR_in[8] = (CFGMGMTADDR[8] !== 1'bz) && CFGMGMTADDR[8]; // rv 0 + assign CFGMGMTADDR_in[9] = (CFGMGMTADDR[9] !== 1'bz) && CFGMGMTADDR[9]; // rv 0 + assign CFGMGMTBYTEENABLE_in[0] = (CFGMGMTBYTEENABLE[0] !== 1'bz) && CFGMGMTBYTEENABLE[0]; // rv 0 + assign CFGMGMTBYTEENABLE_in[1] = (CFGMGMTBYTEENABLE[1] !== 1'bz) && CFGMGMTBYTEENABLE[1]; // rv 0 + assign CFGMGMTBYTEENABLE_in[2] = (CFGMGMTBYTEENABLE[2] !== 1'bz) && CFGMGMTBYTEENABLE[2]; // rv 0 + assign CFGMGMTBYTEENABLE_in[3] = (CFGMGMTBYTEENABLE[3] !== 1'bz) && CFGMGMTBYTEENABLE[3]; // rv 0 + assign CFGMGMTDEBUGACCESS_in = (CFGMGMTDEBUGACCESS !== 1'bz) && CFGMGMTDEBUGACCESS; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[0] = (CFGMGMTFUNCTIONNUMBER[0] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[0]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[1] = (CFGMGMTFUNCTIONNUMBER[1] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[1]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[2] = (CFGMGMTFUNCTIONNUMBER[2] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[2]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[3] = (CFGMGMTFUNCTIONNUMBER[3] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[3]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[4] = (CFGMGMTFUNCTIONNUMBER[4] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[4]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[5] = (CFGMGMTFUNCTIONNUMBER[5] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[5]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[6] = (CFGMGMTFUNCTIONNUMBER[6] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[6]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[7] = (CFGMGMTFUNCTIONNUMBER[7] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[7]; // rv 0 + assign CFGMGMTREAD_in = (CFGMGMTREAD !== 1'bz) && CFGMGMTREAD; // rv 0 + assign CFGMGMTWRITEDATA_in[0] = (CFGMGMTWRITEDATA[0] !== 1'bz) && CFGMGMTWRITEDATA[0]; // rv 0 + assign CFGMGMTWRITEDATA_in[10] = (CFGMGMTWRITEDATA[10] !== 1'bz) && CFGMGMTWRITEDATA[10]; // rv 0 + assign CFGMGMTWRITEDATA_in[11] = (CFGMGMTWRITEDATA[11] !== 1'bz) && CFGMGMTWRITEDATA[11]; // rv 0 + assign CFGMGMTWRITEDATA_in[12] = (CFGMGMTWRITEDATA[12] !== 1'bz) && CFGMGMTWRITEDATA[12]; // rv 0 + assign CFGMGMTWRITEDATA_in[13] = (CFGMGMTWRITEDATA[13] !== 1'bz) && CFGMGMTWRITEDATA[13]; // rv 0 + assign CFGMGMTWRITEDATA_in[14] = (CFGMGMTWRITEDATA[14] !== 1'bz) && CFGMGMTWRITEDATA[14]; // rv 0 + assign CFGMGMTWRITEDATA_in[15] = (CFGMGMTWRITEDATA[15] !== 1'bz) && CFGMGMTWRITEDATA[15]; // rv 0 + assign CFGMGMTWRITEDATA_in[16] = (CFGMGMTWRITEDATA[16] !== 1'bz) && CFGMGMTWRITEDATA[16]; // rv 0 + assign CFGMGMTWRITEDATA_in[17] = (CFGMGMTWRITEDATA[17] !== 1'bz) && CFGMGMTWRITEDATA[17]; // rv 0 + assign CFGMGMTWRITEDATA_in[18] = (CFGMGMTWRITEDATA[18] !== 1'bz) && CFGMGMTWRITEDATA[18]; // rv 0 + assign CFGMGMTWRITEDATA_in[19] = (CFGMGMTWRITEDATA[19] !== 1'bz) && CFGMGMTWRITEDATA[19]; // rv 0 + assign CFGMGMTWRITEDATA_in[1] = (CFGMGMTWRITEDATA[1] !== 1'bz) && CFGMGMTWRITEDATA[1]; // rv 0 + assign CFGMGMTWRITEDATA_in[20] = (CFGMGMTWRITEDATA[20] !== 1'bz) && CFGMGMTWRITEDATA[20]; // rv 0 + assign CFGMGMTWRITEDATA_in[21] = (CFGMGMTWRITEDATA[21] !== 1'bz) && CFGMGMTWRITEDATA[21]; // rv 0 + assign CFGMGMTWRITEDATA_in[22] = (CFGMGMTWRITEDATA[22] !== 1'bz) && CFGMGMTWRITEDATA[22]; // rv 0 + assign CFGMGMTWRITEDATA_in[23] = (CFGMGMTWRITEDATA[23] !== 1'bz) && CFGMGMTWRITEDATA[23]; // rv 0 + assign CFGMGMTWRITEDATA_in[24] = (CFGMGMTWRITEDATA[24] !== 1'bz) && CFGMGMTWRITEDATA[24]; // rv 0 + assign CFGMGMTWRITEDATA_in[25] = (CFGMGMTWRITEDATA[25] !== 1'bz) && CFGMGMTWRITEDATA[25]; // rv 0 + assign CFGMGMTWRITEDATA_in[26] = (CFGMGMTWRITEDATA[26] !== 1'bz) && CFGMGMTWRITEDATA[26]; // rv 0 + assign CFGMGMTWRITEDATA_in[27] = (CFGMGMTWRITEDATA[27] !== 1'bz) && CFGMGMTWRITEDATA[27]; // rv 0 + assign CFGMGMTWRITEDATA_in[28] = (CFGMGMTWRITEDATA[28] !== 1'bz) && CFGMGMTWRITEDATA[28]; // rv 0 + assign CFGMGMTWRITEDATA_in[29] = (CFGMGMTWRITEDATA[29] !== 1'bz) && CFGMGMTWRITEDATA[29]; // rv 0 + assign CFGMGMTWRITEDATA_in[2] = (CFGMGMTWRITEDATA[2] !== 1'bz) && CFGMGMTWRITEDATA[2]; // rv 0 + assign CFGMGMTWRITEDATA_in[30] = (CFGMGMTWRITEDATA[30] !== 1'bz) && CFGMGMTWRITEDATA[30]; // rv 0 + assign CFGMGMTWRITEDATA_in[31] = (CFGMGMTWRITEDATA[31] !== 1'bz) && CFGMGMTWRITEDATA[31]; // rv 0 + assign CFGMGMTWRITEDATA_in[3] = (CFGMGMTWRITEDATA[3] !== 1'bz) && CFGMGMTWRITEDATA[3]; // rv 0 + assign CFGMGMTWRITEDATA_in[4] = (CFGMGMTWRITEDATA[4] !== 1'bz) && CFGMGMTWRITEDATA[4]; // rv 0 + assign CFGMGMTWRITEDATA_in[5] = (CFGMGMTWRITEDATA[5] !== 1'bz) && CFGMGMTWRITEDATA[5]; // rv 0 + assign CFGMGMTWRITEDATA_in[6] = (CFGMGMTWRITEDATA[6] !== 1'bz) && CFGMGMTWRITEDATA[6]; // rv 0 + assign CFGMGMTWRITEDATA_in[7] = (CFGMGMTWRITEDATA[7] !== 1'bz) && CFGMGMTWRITEDATA[7]; // rv 0 + assign CFGMGMTWRITEDATA_in[8] = (CFGMGMTWRITEDATA[8] !== 1'bz) && CFGMGMTWRITEDATA[8]; // rv 0 + assign CFGMGMTWRITEDATA_in[9] = (CFGMGMTWRITEDATA[9] !== 1'bz) && CFGMGMTWRITEDATA[9]; // rv 0 + assign CFGMGMTWRITE_in = (CFGMGMTWRITE !== 1'bz) && CFGMGMTWRITE; // rv 0 + assign CFGMSGTRANSMITDATA_in[0] = (CFGMSGTRANSMITDATA[0] !== 1'bz) && CFGMSGTRANSMITDATA[0]; // rv 0 + assign CFGMSGTRANSMITDATA_in[10] = (CFGMSGTRANSMITDATA[10] !== 1'bz) && CFGMSGTRANSMITDATA[10]; // rv 0 + assign CFGMSGTRANSMITDATA_in[11] = (CFGMSGTRANSMITDATA[11] !== 1'bz) && CFGMSGTRANSMITDATA[11]; // rv 0 + assign CFGMSGTRANSMITDATA_in[12] = (CFGMSGTRANSMITDATA[12] !== 1'bz) && CFGMSGTRANSMITDATA[12]; // rv 0 + assign CFGMSGTRANSMITDATA_in[13] = (CFGMSGTRANSMITDATA[13] !== 1'bz) && CFGMSGTRANSMITDATA[13]; // rv 0 + assign CFGMSGTRANSMITDATA_in[14] = (CFGMSGTRANSMITDATA[14] !== 1'bz) && CFGMSGTRANSMITDATA[14]; // rv 0 + assign CFGMSGTRANSMITDATA_in[15] = (CFGMSGTRANSMITDATA[15] !== 1'bz) && CFGMSGTRANSMITDATA[15]; // rv 0 + assign CFGMSGTRANSMITDATA_in[16] = (CFGMSGTRANSMITDATA[16] !== 1'bz) && CFGMSGTRANSMITDATA[16]; // rv 0 + assign CFGMSGTRANSMITDATA_in[17] = (CFGMSGTRANSMITDATA[17] !== 1'bz) && CFGMSGTRANSMITDATA[17]; // rv 0 + assign CFGMSGTRANSMITDATA_in[18] = (CFGMSGTRANSMITDATA[18] !== 1'bz) && CFGMSGTRANSMITDATA[18]; // rv 0 + assign CFGMSGTRANSMITDATA_in[19] = (CFGMSGTRANSMITDATA[19] !== 1'bz) && CFGMSGTRANSMITDATA[19]; // rv 0 + assign CFGMSGTRANSMITDATA_in[1] = (CFGMSGTRANSMITDATA[1] !== 1'bz) && CFGMSGTRANSMITDATA[1]; // rv 0 + assign CFGMSGTRANSMITDATA_in[20] = (CFGMSGTRANSMITDATA[20] !== 1'bz) && CFGMSGTRANSMITDATA[20]; // rv 0 + assign CFGMSGTRANSMITDATA_in[21] = (CFGMSGTRANSMITDATA[21] !== 1'bz) && CFGMSGTRANSMITDATA[21]; // rv 0 + assign CFGMSGTRANSMITDATA_in[22] = (CFGMSGTRANSMITDATA[22] !== 1'bz) && CFGMSGTRANSMITDATA[22]; // rv 0 + assign CFGMSGTRANSMITDATA_in[23] = (CFGMSGTRANSMITDATA[23] !== 1'bz) && CFGMSGTRANSMITDATA[23]; // rv 0 + assign CFGMSGTRANSMITDATA_in[24] = (CFGMSGTRANSMITDATA[24] !== 1'bz) && CFGMSGTRANSMITDATA[24]; // rv 0 + assign CFGMSGTRANSMITDATA_in[25] = (CFGMSGTRANSMITDATA[25] !== 1'bz) && CFGMSGTRANSMITDATA[25]; // rv 0 + assign CFGMSGTRANSMITDATA_in[26] = (CFGMSGTRANSMITDATA[26] !== 1'bz) && CFGMSGTRANSMITDATA[26]; // rv 0 + assign CFGMSGTRANSMITDATA_in[27] = (CFGMSGTRANSMITDATA[27] !== 1'bz) && CFGMSGTRANSMITDATA[27]; // rv 0 + assign CFGMSGTRANSMITDATA_in[28] = (CFGMSGTRANSMITDATA[28] !== 1'bz) && CFGMSGTRANSMITDATA[28]; // rv 0 + assign CFGMSGTRANSMITDATA_in[29] = (CFGMSGTRANSMITDATA[29] !== 1'bz) && CFGMSGTRANSMITDATA[29]; // rv 0 + assign CFGMSGTRANSMITDATA_in[2] = (CFGMSGTRANSMITDATA[2] !== 1'bz) && CFGMSGTRANSMITDATA[2]; // rv 0 + assign CFGMSGTRANSMITDATA_in[30] = (CFGMSGTRANSMITDATA[30] !== 1'bz) && CFGMSGTRANSMITDATA[30]; // rv 0 + assign CFGMSGTRANSMITDATA_in[31] = (CFGMSGTRANSMITDATA[31] !== 1'bz) && CFGMSGTRANSMITDATA[31]; // rv 0 + assign CFGMSGTRANSMITDATA_in[3] = (CFGMSGTRANSMITDATA[3] !== 1'bz) && CFGMSGTRANSMITDATA[3]; // rv 0 + assign CFGMSGTRANSMITDATA_in[4] = (CFGMSGTRANSMITDATA[4] !== 1'bz) && CFGMSGTRANSMITDATA[4]; // rv 0 + assign CFGMSGTRANSMITDATA_in[5] = (CFGMSGTRANSMITDATA[5] !== 1'bz) && CFGMSGTRANSMITDATA[5]; // rv 0 + assign CFGMSGTRANSMITDATA_in[6] = (CFGMSGTRANSMITDATA[6] !== 1'bz) && CFGMSGTRANSMITDATA[6]; // rv 0 + assign CFGMSGTRANSMITDATA_in[7] = (CFGMSGTRANSMITDATA[7] !== 1'bz) && CFGMSGTRANSMITDATA[7]; // rv 0 + assign CFGMSGTRANSMITDATA_in[8] = (CFGMSGTRANSMITDATA[8] !== 1'bz) && CFGMSGTRANSMITDATA[8]; // rv 0 + assign CFGMSGTRANSMITDATA_in[9] = (CFGMSGTRANSMITDATA[9] !== 1'bz) && CFGMSGTRANSMITDATA[9]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[0] = (CFGMSGTRANSMITTYPE[0] !== 1'bz) && CFGMSGTRANSMITTYPE[0]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[1] = (CFGMSGTRANSMITTYPE[1] !== 1'bz) && CFGMSGTRANSMITTYPE[1]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[2] = (CFGMSGTRANSMITTYPE[2] !== 1'bz) && CFGMSGTRANSMITTYPE[2]; // rv 0 + assign CFGMSGTRANSMIT_in = (CFGMSGTRANSMIT !== 1'bz) && CFGMSGTRANSMIT; // rv 0 + assign CFGMSIXRAMREADDATA_in[0] = (CFGMSIXRAMREADDATA[0] !== 1'bz) && CFGMSIXRAMREADDATA[0]; // rv 0 + assign CFGMSIXRAMREADDATA_in[10] = (CFGMSIXRAMREADDATA[10] !== 1'bz) && CFGMSIXRAMREADDATA[10]; // rv 0 + assign CFGMSIXRAMREADDATA_in[11] = (CFGMSIXRAMREADDATA[11] !== 1'bz) && CFGMSIXRAMREADDATA[11]; // rv 0 + assign CFGMSIXRAMREADDATA_in[12] = (CFGMSIXRAMREADDATA[12] !== 1'bz) && CFGMSIXRAMREADDATA[12]; // rv 0 + assign CFGMSIXRAMREADDATA_in[13] = (CFGMSIXRAMREADDATA[13] !== 1'bz) && CFGMSIXRAMREADDATA[13]; // rv 0 + assign CFGMSIXRAMREADDATA_in[14] = (CFGMSIXRAMREADDATA[14] !== 1'bz) && CFGMSIXRAMREADDATA[14]; // rv 0 + assign CFGMSIXRAMREADDATA_in[15] = (CFGMSIXRAMREADDATA[15] !== 1'bz) && CFGMSIXRAMREADDATA[15]; // rv 0 + assign CFGMSIXRAMREADDATA_in[16] = (CFGMSIXRAMREADDATA[16] !== 1'bz) && CFGMSIXRAMREADDATA[16]; // rv 0 + assign CFGMSIXRAMREADDATA_in[17] = (CFGMSIXRAMREADDATA[17] !== 1'bz) && CFGMSIXRAMREADDATA[17]; // rv 0 + assign CFGMSIXRAMREADDATA_in[18] = (CFGMSIXRAMREADDATA[18] !== 1'bz) && CFGMSIXRAMREADDATA[18]; // rv 0 + assign CFGMSIXRAMREADDATA_in[19] = (CFGMSIXRAMREADDATA[19] !== 1'bz) && CFGMSIXRAMREADDATA[19]; // rv 0 + assign CFGMSIXRAMREADDATA_in[1] = (CFGMSIXRAMREADDATA[1] !== 1'bz) && CFGMSIXRAMREADDATA[1]; // rv 0 + assign CFGMSIXRAMREADDATA_in[20] = (CFGMSIXRAMREADDATA[20] !== 1'bz) && CFGMSIXRAMREADDATA[20]; // rv 0 + assign CFGMSIXRAMREADDATA_in[21] = (CFGMSIXRAMREADDATA[21] !== 1'bz) && CFGMSIXRAMREADDATA[21]; // rv 0 + assign CFGMSIXRAMREADDATA_in[22] = (CFGMSIXRAMREADDATA[22] !== 1'bz) && CFGMSIXRAMREADDATA[22]; // rv 0 + assign CFGMSIXRAMREADDATA_in[23] = (CFGMSIXRAMREADDATA[23] !== 1'bz) && CFGMSIXRAMREADDATA[23]; // rv 0 + assign CFGMSIXRAMREADDATA_in[24] = (CFGMSIXRAMREADDATA[24] !== 1'bz) && CFGMSIXRAMREADDATA[24]; // rv 0 + assign CFGMSIXRAMREADDATA_in[25] = (CFGMSIXRAMREADDATA[25] !== 1'bz) && CFGMSIXRAMREADDATA[25]; // rv 0 + assign CFGMSIXRAMREADDATA_in[26] = (CFGMSIXRAMREADDATA[26] !== 1'bz) && CFGMSIXRAMREADDATA[26]; // rv 0 + assign CFGMSIXRAMREADDATA_in[27] = (CFGMSIXRAMREADDATA[27] !== 1'bz) && CFGMSIXRAMREADDATA[27]; // rv 0 + assign CFGMSIXRAMREADDATA_in[28] = (CFGMSIXRAMREADDATA[28] !== 1'bz) && CFGMSIXRAMREADDATA[28]; // rv 0 + assign CFGMSIXRAMREADDATA_in[29] = (CFGMSIXRAMREADDATA[29] !== 1'bz) && CFGMSIXRAMREADDATA[29]; // rv 0 + assign CFGMSIXRAMREADDATA_in[2] = (CFGMSIXRAMREADDATA[2] !== 1'bz) && CFGMSIXRAMREADDATA[2]; // rv 0 + assign CFGMSIXRAMREADDATA_in[30] = (CFGMSIXRAMREADDATA[30] !== 1'bz) && CFGMSIXRAMREADDATA[30]; // rv 0 + assign CFGMSIXRAMREADDATA_in[31] = (CFGMSIXRAMREADDATA[31] !== 1'bz) && CFGMSIXRAMREADDATA[31]; // rv 0 + assign CFGMSIXRAMREADDATA_in[32] = (CFGMSIXRAMREADDATA[32] !== 1'bz) && CFGMSIXRAMREADDATA[32]; // rv 0 + assign CFGMSIXRAMREADDATA_in[33] = (CFGMSIXRAMREADDATA[33] !== 1'bz) && CFGMSIXRAMREADDATA[33]; // rv 0 + assign CFGMSIXRAMREADDATA_in[34] = (CFGMSIXRAMREADDATA[34] !== 1'bz) && CFGMSIXRAMREADDATA[34]; // rv 0 + assign CFGMSIXRAMREADDATA_in[35] = (CFGMSIXRAMREADDATA[35] !== 1'bz) && CFGMSIXRAMREADDATA[35]; // rv 0 + assign CFGMSIXRAMREADDATA_in[3] = (CFGMSIXRAMREADDATA[3] !== 1'bz) && CFGMSIXRAMREADDATA[3]; // rv 0 + assign CFGMSIXRAMREADDATA_in[4] = (CFGMSIXRAMREADDATA[4] !== 1'bz) && CFGMSIXRAMREADDATA[4]; // rv 0 + assign CFGMSIXRAMREADDATA_in[5] = (CFGMSIXRAMREADDATA[5] !== 1'bz) && CFGMSIXRAMREADDATA[5]; // rv 0 + assign CFGMSIXRAMREADDATA_in[6] = (CFGMSIXRAMREADDATA[6] !== 1'bz) && CFGMSIXRAMREADDATA[6]; // rv 0 + assign CFGMSIXRAMREADDATA_in[7] = (CFGMSIXRAMREADDATA[7] !== 1'bz) && CFGMSIXRAMREADDATA[7]; // rv 0 + assign CFGMSIXRAMREADDATA_in[8] = (CFGMSIXRAMREADDATA[8] !== 1'bz) && CFGMSIXRAMREADDATA[8]; // rv 0 + assign CFGMSIXRAMREADDATA_in[9] = (CFGMSIXRAMREADDATA[9] !== 1'bz) && CFGMSIXRAMREADDATA[9]; // rv 0 + assign CFGPMASPML1ENTRYREJECT_in = (CFGPMASPML1ENTRYREJECT !== 1'bz) && CFGPMASPML1ENTRYREJECT; // rv 0 + assign CFGPMASPMTXL0SENTRYDISABLE_in = (CFGPMASPMTXL0SENTRYDISABLE !== 1'bz) && CFGPMASPMTXL0SENTRYDISABLE; // rv 0 + assign CFGPOWERSTATECHANGEACK_in = (CFGPOWERSTATECHANGEACK === 1'bz) || CFGPOWERSTATECHANGEACK; // rv 1 + assign CFGREQPMTRANSITIONL23READY_in = (CFGREQPMTRANSITIONL23READY !== 1'bz) && CFGREQPMTRANSITIONL23READY; // rv 0 + assign CFGREVIDPF0_in[0] = (CFGREVIDPF0[0] !== 1'bz) && CFGREVIDPF0[0]; // rv 0 + assign CFGREVIDPF0_in[1] = (CFGREVIDPF0[1] !== 1'bz) && CFGREVIDPF0[1]; // rv 0 + assign CFGREVIDPF0_in[2] = (CFGREVIDPF0[2] !== 1'bz) && CFGREVIDPF0[2]; // rv 0 + assign CFGREVIDPF0_in[3] = (CFGREVIDPF0[3] !== 1'bz) && CFGREVIDPF0[3]; // rv 0 + assign CFGREVIDPF0_in[4] = (CFGREVIDPF0[4] !== 1'bz) && CFGREVIDPF0[4]; // rv 0 + assign CFGREVIDPF0_in[5] = (CFGREVIDPF0[5] !== 1'bz) && CFGREVIDPF0[5]; // rv 0 + assign CFGREVIDPF0_in[6] = (CFGREVIDPF0[6] !== 1'bz) && CFGREVIDPF0[6]; // rv 0 + assign CFGREVIDPF0_in[7] = (CFGREVIDPF0[7] !== 1'bz) && CFGREVIDPF0[7]; // rv 0 + assign CFGREVIDPF1_in[0] = (CFGREVIDPF1[0] !== 1'bz) && CFGREVIDPF1[0]; // rv 0 + assign CFGREVIDPF1_in[1] = (CFGREVIDPF1[1] !== 1'bz) && CFGREVIDPF1[1]; // rv 0 + assign CFGREVIDPF1_in[2] = (CFGREVIDPF1[2] !== 1'bz) && CFGREVIDPF1[2]; // rv 0 + assign CFGREVIDPF1_in[3] = (CFGREVIDPF1[3] !== 1'bz) && CFGREVIDPF1[3]; // rv 0 + assign CFGREVIDPF1_in[4] = (CFGREVIDPF1[4] !== 1'bz) && CFGREVIDPF1[4]; // rv 0 + assign CFGREVIDPF1_in[5] = (CFGREVIDPF1[5] !== 1'bz) && CFGREVIDPF1[5]; // rv 0 + assign CFGREVIDPF1_in[6] = (CFGREVIDPF1[6] !== 1'bz) && CFGREVIDPF1[6]; // rv 0 + assign CFGREVIDPF1_in[7] = (CFGREVIDPF1[7] !== 1'bz) && CFGREVIDPF1[7]; // rv 0 + assign CFGREVIDPF2_in[0] = (CFGREVIDPF2[0] !== 1'bz) && CFGREVIDPF2[0]; // rv 0 + assign CFGREVIDPF2_in[1] = (CFGREVIDPF2[1] !== 1'bz) && CFGREVIDPF2[1]; // rv 0 + assign CFGREVIDPF2_in[2] = (CFGREVIDPF2[2] !== 1'bz) && CFGREVIDPF2[2]; // rv 0 + assign CFGREVIDPF2_in[3] = (CFGREVIDPF2[3] !== 1'bz) && CFGREVIDPF2[3]; // rv 0 + assign CFGREVIDPF2_in[4] = (CFGREVIDPF2[4] !== 1'bz) && CFGREVIDPF2[4]; // rv 0 + assign CFGREVIDPF2_in[5] = (CFGREVIDPF2[5] !== 1'bz) && CFGREVIDPF2[5]; // rv 0 + assign CFGREVIDPF2_in[6] = (CFGREVIDPF2[6] !== 1'bz) && CFGREVIDPF2[6]; // rv 0 + assign CFGREVIDPF2_in[7] = (CFGREVIDPF2[7] !== 1'bz) && CFGREVIDPF2[7]; // rv 0 + assign CFGREVIDPF3_in[0] = (CFGREVIDPF3[0] !== 1'bz) && CFGREVIDPF3[0]; // rv 0 + assign CFGREVIDPF3_in[1] = (CFGREVIDPF3[1] !== 1'bz) && CFGREVIDPF3[1]; // rv 0 + assign CFGREVIDPF3_in[2] = (CFGREVIDPF3[2] !== 1'bz) && CFGREVIDPF3[2]; // rv 0 + assign CFGREVIDPF3_in[3] = (CFGREVIDPF3[3] !== 1'bz) && CFGREVIDPF3[3]; // rv 0 + assign CFGREVIDPF3_in[4] = (CFGREVIDPF3[4] !== 1'bz) && CFGREVIDPF3[4]; // rv 0 + assign CFGREVIDPF3_in[5] = (CFGREVIDPF3[5] !== 1'bz) && CFGREVIDPF3[5]; // rv 0 + assign CFGREVIDPF3_in[6] = (CFGREVIDPF3[6] !== 1'bz) && CFGREVIDPF3[6]; // rv 0 + assign CFGREVIDPF3_in[7] = (CFGREVIDPF3[7] !== 1'bz) && CFGREVIDPF3[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[0] = (CFGSUBSYSIDPF0[0] !== 1'bz) && CFGSUBSYSIDPF0[0]; // rv 0 + assign CFGSUBSYSIDPF0_in[10] = (CFGSUBSYSIDPF0[10] !== 1'bz) && CFGSUBSYSIDPF0[10]; // rv 0 + assign CFGSUBSYSIDPF0_in[11] = (CFGSUBSYSIDPF0[11] !== 1'bz) && CFGSUBSYSIDPF0[11]; // rv 0 + assign CFGSUBSYSIDPF0_in[12] = (CFGSUBSYSIDPF0[12] !== 1'bz) && CFGSUBSYSIDPF0[12]; // rv 0 + assign CFGSUBSYSIDPF0_in[13] = (CFGSUBSYSIDPF0[13] !== 1'bz) && CFGSUBSYSIDPF0[13]; // rv 0 + assign CFGSUBSYSIDPF0_in[14] = (CFGSUBSYSIDPF0[14] !== 1'bz) && CFGSUBSYSIDPF0[14]; // rv 0 + assign CFGSUBSYSIDPF0_in[15] = (CFGSUBSYSIDPF0[15] !== 1'bz) && CFGSUBSYSIDPF0[15]; // rv 0 + assign CFGSUBSYSIDPF0_in[1] = (CFGSUBSYSIDPF0[1] !== 1'bz) && CFGSUBSYSIDPF0[1]; // rv 0 + assign CFGSUBSYSIDPF0_in[2] = (CFGSUBSYSIDPF0[2] !== 1'bz) && CFGSUBSYSIDPF0[2]; // rv 0 + assign CFGSUBSYSIDPF0_in[3] = (CFGSUBSYSIDPF0[3] !== 1'bz) && CFGSUBSYSIDPF0[3]; // rv 0 + assign CFGSUBSYSIDPF0_in[4] = (CFGSUBSYSIDPF0[4] !== 1'bz) && CFGSUBSYSIDPF0[4]; // rv 0 + assign CFGSUBSYSIDPF0_in[5] = (CFGSUBSYSIDPF0[5] !== 1'bz) && CFGSUBSYSIDPF0[5]; // rv 0 + assign CFGSUBSYSIDPF0_in[6] = (CFGSUBSYSIDPF0[6] !== 1'bz) && CFGSUBSYSIDPF0[6]; // rv 0 + assign CFGSUBSYSIDPF0_in[7] = (CFGSUBSYSIDPF0[7] !== 1'bz) && CFGSUBSYSIDPF0[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[8] = (CFGSUBSYSIDPF0[8] !== 1'bz) && CFGSUBSYSIDPF0[8]; // rv 0 + assign CFGSUBSYSIDPF0_in[9] = (CFGSUBSYSIDPF0[9] !== 1'bz) && CFGSUBSYSIDPF0[9]; // rv 0 + assign CFGSUBSYSIDPF1_in[0] = (CFGSUBSYSIDPF1[0] !== 1'bz) && CFGSUBSYSIDPF1[0]; // rv 0 + assign CFGSUBSYSIDPF1_in[10] = (CFGSUBSYSIDPF1[10] !== 1'bz) && CFGSUBSYSIDPF1[10]; // rv 0 + assign CFGSUBSYSIDPF1_in[11] = (CFGSUBSYSIDPF1[11] !== 1'bz) && CFGSUBSYSIDPF1[11]; // rv 0 + assign CFGSUBSYSIDPF1_in[12] = (CFGSUBSYSIDPF1[12] !== 1'bz) && CFGSUBSYSIDPF1[12]; // rv 0 + assign CFGSUBSYSIDPF1_in[13] = (CFGSUBSYSIDPF1[13] !== 1'bz) && CFGSUBSYSIDPF1[13]; // rv 0 + assign CFGSUBSYSIDPF1_in[14] = (CFGSUBSYSIDPF1[14] !== 1'bz) && CFGSUBSYSIDPF1[14]; // rv 0 + assign CFGSUBSYSIDPF1_in[15] = (CFGSUBSYSIDPF1[15] !== 1'bz) && CFGSUBSYSIDPF1[15]; // rv 0 + assign CFGSUBSYSIDPF1_in[1] = (CFGSUBSYSIDPF1[1] !== 1'bz) && CFGSUBSYSIDPF1[1]; // rv 0 + assign CFGSUBSYSIDPF1_in[2] = (CFGSUBSYSIDPF1[2] !== 1'bz) && CFGSUBSYSIDPF1[2]; // rv 0 + assign CFGSUBSYSIDPF1_in[3] = (CFGSUBSYSIDPF1[3] !== 1'bz) && CFGSUBSYSIDPF1[3]; // rv 0 + assign CFGSUBSYSIDPF1_in[4] = (CFGSUBSYSIDPF1[4] !== 1'bz) && CFGSUBSYSIDPF1[4]; // rv 0 + assign CFGSUBSYSIDPF1_in[5] = (CFGSUBSYSIDPF1[5] !== 1'bz) && CFGSUBSYSIDPF1[5]; // rv 0 + assign CFGSUBSYSIDPF1_in[6] = (CFGSUBSYSIDPF1[6] !== 1'bz) && CFGSUBSYSIDPF1[6]; // rv 0 + assign CFGSUBSYSIDPF1_in[7] = (CFGSUBSYSIDPF1[7] !== 1'bz) && CFGSUBSYSIDPF1[7]; // rv 0 + assign CFGSUBSYSIDPF1_in[8] = (CFGSUBSYSIDPF1[8] !== 1'bz) && CFGSUBSYSIDPF1[8]; // rv 0 + assign CFGSUBSYSIDPF1_in[9] = (CFGSUBSYSIDPF1[9] !== 1'bz) && CFGSUBSYSIDPF1[9]; // rv 0 + assign CFGSUBSYSIDPF2_in[0] = (CFGSUBSYSIDPF2[0] !== 1'bz) && CFGSUBSYSIDPF2[0]; // rv 0 + assign CFGSUBSYSIDPF2_in[10] = (CFGSUBSYSIDPF2[10] !== 1'bz) && CFGSUBSYSIDPF2[10]; // rv 0 + assign CFGSUBSYSIDPF2_in[11] = (CFGSUBSYSIDPF2[11] !== 1'bz) && CFGSUBSYSIDPF2[11]; // rv 0 + assign CFGSUBSYSIDPF2_in[12] = (CFGSUBSYSIDPF2[12] !== 1'bz) && CFGSUBSYSIDPF2[12]; // rv 0 + assign CFGSUBSYSIDPF2_in[13] = (CFGSUBSYSIDPF2[13] !== 1'bz) && CFGSUBSYSIDPF2[13]; // rv 0 + assign CFGSUBSYSIDPF2_in[14] = (CFGSUBSYSIDPF2[14] !== 1'bz) && CFGSUBSYSIDPF2[14]; // rv 0 + assign CFGSUBSYSIDPF2_in[15] = (CFGSUBSYSIDPF2[15] !== 1'bz) && CFGSUBSYSIDPF2[15]; // rv 0 + assign CFGSUBSYSIDPF2_in[1] = (CFGSUBSYSIDPF2[1] !== 1'bz) && CFGSUBSYSIDPF2[1]; // rv 0 + assign CFGSUBSYSIDPF2_in[2] = (CFGSUBSYSIDPF2[2] !== 1'bz) && CFGSUBSYSIDPF2[2]; // rv 0 + assign CFGSUBSYSIDPF2_in[3] = (CFGSUBSYSIDPF2[3] !== 1'bz) && CFGSUBSYSIDPF2[3]; // rv 0 + assign CFGSUBSYSIDPF2_in[4] = (CFGSUBSYSIDPF2[4] !== 1'bz) && CFGSUBSYSIDPF2[4]; // rv 0 + assign CFGSUBSYSIDPF2_in[5] = (CFGSUBSYSIDPF2[5] !== 1'bz) && CFGSUBSYSIDPF2[5]; // rv 0 + assign CFGSUBSYSIDPF2_in[6] = (CFGSUBSYSIDPF2[6] !== 1'bz) && CFGSUBSYSIDPF2[6]; // rv 0 + assign CFGSUBSYSIDPF2_in[7] = (CFGSUBSYSIDPF2[7] !== 1'bz) && CFGSUBSYSIDPF2[7]; // rv 0 + assign CFGSUBSYSIDPF2_in[8] = (CFGSUBSYSIDPF2[8] !== 1'bz) && CFGSUBSYSIDPF2[8]; // rv 0 + assign CFGSUBSYSIDPF2_in[9] = (CFGSUBSYSIDPF2[9] !== 1'bz) && CFGSUBSYSIDPF2[9]; // rv 0 + assign CFGSUBSYSIDPF3_in[0] = (CFGSUBSYSIDPF3[0] !== 1'bz) && CFGSUBSYSIDPF3[0]; // rv 0 + assign CFGSUBSYSIDPF3_in[10] = (CFGSUBSYSIDPF3[10] !== 1'bz) && CFGSUBSYSIDPF3[10]; // rv 0 + assign CFGSUBSYSIDPF3_in[11] = (CFGSUBSYSIDPF3[11] !== 1'bz) && CFGSUBSYSIDPF3[11]; // rv 0 + assign CFGSUBSYSIDPF3_in[12] = (CFGSUBSYSIDPF3[12] !== 1'bz) && CFGSUBSYSIDPF3[12]; // rv 0 + assign CFGSUBSYSIDPF3_in[13] = (CFGSUBSYSIDPF3[13] !== 1'bz) && CFGSUBSYSIDPF3[13]; // rv 0 + assign CFGSUBSYSIDPF3_in[14] = (CFGSUBSYSIDPF3[14] !== 1'bz) && CFGSUBSYSIDPF3[14]; // rv 0 + assign CFGSUBSYSIDPF3_in[15] = (CFGSUBSYSIDPF3[15] !== 1'bz) && CFGSUBSYSIDPF3[15]; // rv 0 + assign CFGSUBSYSIDPF3_in[1] = (CFGSUBSYSIDPF3[1] !== 1'bz) && CFGSUBSYSIDPF3[1]; // rv 0 + assign CFGSUBSYSIDPF3_in[2] = (CFGSUBSYSIDPF3[2] !== 1'bz) && CFGSUBSYSIDPF3[2]; // rv 0 + assign CFGSUBSYSIDPF3_in[3] = (CFGSUBSYSIDPF3[3] !== 1'bz) && CFGSUBSYSIDPF3[3]; // rv 0 + assign CFGSUBSYSIDPF3_in[4] = (CFGSUBSYSIDPF3[4] !== 1'bz) && CFGSUBSYSIDPF3[4]; // rv 0 + assign CFGSUBSYSIDPF3_in[5] = (CFGSUBSYSIDPF3[5] !== 1'bz) && CFGSUBSYSIDPF3[5]; // rv 0 + assign CFGSUBSYSIDPF3_in[6] = (CFGSUBSYSIDPF3[6] !== 1'bz) && CFGSUBSYSIDPF3[6]; // rv 0 + assign CFGSUBSYSIDPF3_in[7] = (CFGSUBSYSIDPF3[7] !== 1'bz) && CFGSUBSYSIDPF3[7]; // rv 0 + assign CFGSUBSYSIDPF3_in[8] = (CFGSUBSYSIDPF3[8] !== 1'bz) && CFGSUBSYSIDPF3[8]; // rv 0 + assign CFGSUBSYSIDPF3_in[9] = (CFGSUBSYSIDPF3[9] !== 1'bz) && CFGSUBSYSIDPF3[9]; // rv 0 + assign CFGSUBSYSVENDID_in[0] = (CFGSUBSYSVENDID[0] !== 1'bz) && CFGSUBSYSVENDID[0]; // rv 0 + assign CFGSUBSYSVENDID_in[10] = (CFGSUBSYSVENDID[10] !== 1'bz) && CFGSUBSYSVENDID[10]; // rv 0 + assign CFGSUBSYSVENDID_in[11] = (CFGSUBSYSVENDID[11] !== 1'bz) && CFGSUBSYSVENDID[11]; // rv 0 + assign CFGSUBSYSVENDID_in[12] = (CFGSUBSYSVENDID[12] !== 1'bz) && CFGSUBSYSVENDID[12]; // rv 0 + assign CFGSUBSYSVENDID_in[13] = (CFGSUBSYSVENDID[13] !== 1'bz) && CFGSUBSYSVENDID[13]; // rv 0 + assign CFGSUBSYSVENDID_in[14] = (CFGSUBSYSVENDID[14] !== 1'bz) && CFGSUBSYSVENDID[14]; // rv 0 + assign CFGSUBSYSVENDID_in[15] = (CFGSUBSYSVENDID[15] !== 1'bz) && CFGSUBSYSVENDID[15]; // rv 0 + assign CFGSUBSYSVENDID_in[1] = (CFGSUBSYSVENDID[1] !== 1'bz) && CFGSUBSYSVENDID[1]; // rv 0 + assign CFGSUBSYSVENDID_in[2] = (CFGSUBSYSVENDID[2] !== 1'bz) && CFGSUBSYSVENDID[2]; // rv 0 + assign CFGSUBSYSVENDID_in[3] = (CFGSUBSYSVENDID[3] !== 1'bz) && CFGSUBSYSVENDID[3]; // rv 0 + assign CFGSUBSYSVENDID_in[4] = (CFGSUBSYSVENDID[4] !== 1'bz) && CFGSUBSYSVENDID[4]; // rv 0 + assign CFGSUBSYSVENDID_in[5] = (CFGSUBSYSVENDID[5] !== 1'bz) && CFGSUBSYSVENDID[5]; // rv 0 + assign CFGSUBSYSVENDID_in[6] = (CFGSUBSYSVENDID[6] !== 1'bz) && CFGSUBSYSVENDID[6]; // rv 0 + assign CFGSUBSYSVENDID_in[7] = (CFGSUBSYSVENDID[7] !== 1'bz) && CFGSUBSYSVENDID[7]; // rv 0 + assign CFGSUBSYSVENDID_in[8] = (CFGSUBSYSVENDID[8] !== 1'bz) && CFGSUBSYSVENDID[8]; // rv 0 + assign CFGSUBSYSVENDID_in[9] = (CFGSUBSYSVENDID[9] !== 1'bz) && CFGSUBSYSVENDID[9]; // rv 0 + assign CFGTPHRAMREADDATA_in[0] = (CFGTPHRAMREADDATA[0] !== 1'bz) && CFGTPHRAMREADDATA[0]; // rv 0 + assign CFGTPHRAMREADDATA_in[10] = (CFGTPHRAMREADDATA[10] !== 1'bz) && CFGTPHRAMREADDATA[10]; // rv 0 + assign CFGTPHRAMREADDATA_in[11] = (CFGTPHRAMREADDATA[11] !== 1'bz) && CFGTPHRAMREADDATA[11]; // rv 0 + assign CFGTPHRAMREADDATA_in[12] = (CFGTPHRAMREADDATA[12] !== 1'bz) && CFGTPHRAMREADDATA[12]; // rv 0 + assign CFGTPHRAMREADDATA_in[13] = (CFGTPHRAMREADDATA[13] !== 1'bz) && CFGTPHRAMREADDATA[13]; // rv 0 + assign CFGTPHRAMREADDATA_in[14] = (CFGTPHRAMREADDATA[14] !== 1'bz) && CFGTPHRAMREADDATA[14]; // rv 0 + assign CFGTPHRAMREADDATA_in[15] = (CFGTPHRAMREADDATA[15] !== 1'bz) && CFGTPHRAMREADDATA[15]; // rv 0 + assign CFGTPHRAMREADDATA_in[16] = (CFGTPHRAMREADDATA[16] !== 1'bz) && CFGTPHRAMREADDATA[16]; // rv 0 + assign CFGTPHRAMREADDATA_in[17] = (CFGTPHRAMREADDATA[17] !== 1'bz) && CFGTPHRAMREADDATA[17]; // rv 0 + assign CFGTPHRAMREADDATA_in[18] = (CFGTPHRAMREADDATA[18] !== 1'bz) && CFGTPHRAMREADDATA[18]; // rv 0 + assign CFGTPHRAMREADDATA_in[19] = (CFGTPHRAMREADDATA[19] !== 1'bz) && CFGTPHRAMREADDATA[19]; // rv 0 + assign CFGTPHRAMREADDATA_in[1] = (CFGTPHRAMREADDATA[1] !== 1'bz) && CFGTPHRAMREADDATA[1]; // rv 0 + assign CFGTPHRAMREADDATA_in[20] = (CFGTPHRAMREADDATA[20] !== 1'bz) && CFGTPHRAMREADDATA[20]; // rv 0 + assign CFGTPHRAMREADDATA_in[21] = (CFGTPHRAMREADDATA[21] !== 1'bz) && CFGTPHRAMREADDATA[21]; // rv 0 + assign CFGTPHRAMREADDATA_in[22] = (CFGTPHRAMREADDATA[22] !== 1'bz) && CFGTPHRAMREADDATA[22]; // rv 0 + assign CFGTPHRAMREADDATA_in[23] = (CFGTPHRAMREADDATA[23] !== 1'bz) && CFGTPHRAMREADDATA[23]; // rv 0 + assign CFGTPHRAMREADDATA_in[24] = (CFGTPHRAMREADDATA[24] !== 1'bz) && CFGTPHRAMREADDATA[24]; // rv 0 + assign CFGTPHRAMREADDATA_in[25] = (CFGTPHRAMREADDATA[25] !== 1'bz) && CFGTPHRAMREADDATA[25]; // rv 0 + assign CFGTPHRAMREADDATA_in[26] = (CFGTPHRAMREADDATA[26] !== 1'bz) && CFGTPHRAMREADDATA[26]; // rv 0 + assign CFGTPHRAMREADDATA_in[27] = (CFGTPHRAMREADDATA[27] !== 1'bz) && CFGTPHRAMREADDATA[27]; // rv 0 + assign CFGTPHRAMREADDATA_in[28] = (CFGTPHRAMREADDATA[28] !== 1'bz) && CFGTPHRAMREADDATA[28]; // rv 0 + assign CFGTPHRAMREADDATA_in[29] = (CFGTPHRAMREADDATA[29] !== 1'bz) && CFGTPHRAMREADDATA[29]; // rv 0 + assign CFGTPHRAMREADDATA_in[2] = (CFGTPHRAMREADDATA[2] !== 1'bz) && CFGTPHRAMREADDATA[2]; // rv 0 + assign CFGTPHRAMREADDATA_in[30] = (CFGTPHRAMREADDATA[30] !== 1'bz) && CFGTPHRAMREADDATA[30]; // rv 0 + assign CFGTPHRAMREADDATA_in[31] = (CFGTPHRAMREADDATA[31] !== 1'bz) && CFGTPHRAMREADDATA[31]; // rv 0 + assign CFGTPHRAMREADDATA_in[32] = (CFGTPHRAMREADDATA[32] !== 1'bz) && CFGTPHRAMREADDATA[32]; // rv 0 + assign CFGTPHRAMREADDATA_in[33] = (CFGTPHRAMREADDATA[33] !== 1'bz) && CFGTPHRAMREADDATA[33]; // rv 0 + assign CFGTPHRAMREADDATA_in[34] = (CFGTPHRAMREADDATA[34] !== 1'bz) && CFGTPHRAMREADDATA[34]; // rv 0 + assign CFGTPHRAMREADDATA_in[35] = (CFGTPHRAMREADDATA[35] !== 1'bz) && CFGTPHRAMREADDATA[35]; // rv 0 + assign CFGTPHRAMREADDATA_in[3] = (CFGTPHRAMREADDATA[3] !== 1'bz) && CFGTPHRAMREADDATA[3]; // rv 0 + assign CFGTPHRAMREADDATA_in[4] = (CFGTPHRAMREADDATA[4] !== 1'bz) && CFGTPHRAMREADDATA[4]; // rv 0 + assign CFGTPHRAMREADDATA_in[5] = (CFGTPHRAMREADDATA[5] !== 1'bz) && CFGTPHRAMREADDATA[5]; // rv 0 + assign CFGTPHRAMREADDATA_in[6] = (CFGTPHRAMREADDATA[6] !== 1'bz) && CFGTPHRAMREADDATA[6]; // rv 0 + assign CFGTPHRAMREADDATA_in[7] = (CFGTPHRAMREADDATA[7] !== 1'bz) && CFGTPHRAMREADDATA[7]; // rv 0 + assign CFGTPHRAMREADDATA_in[8] = (CFGTPHRAMREADDATA[8] !== 1'bz) && CFGTPHRAMREADDATA[8]; // rv 0 + assign CFGTPHRAMREADDATA_in[9] = (CFGTPHRAMREADDATA[9] !== 1'bz) && CFGTPHRAMREADDATA[9]; // rv 0 + assign CFGVENDID_in[0] = (CFGVENDID[0] !== 1'bz) && CFGVENDID[0]; // rv 0 + assign CFGVENDID_in[10] = (CFGVENDID[10] !== 1'bz) && CFGVENDID[10]; // rv 0 + assign CFGVENDID_in[11] = (CFGVENDID[11] !== 1'bz) && CFGVENDID[11]; // rv 0 + assign CFGVENDID_in[12] = (CFGVENDID[12] !== 1'bz) && CFGVENDID[12]; // rv 0 + assign CFGVENDID_in[13] = (CFGVENDID[13] !== 1'bz) && CFGVENDID[13]; // rv 0 + assign CFGVENDID_in[14] = (CFGVENDID[14] !== 1'bz) && CFGVENDID[14]; // rv 0 + assign CFGVENDID_in[15] = (CFGVENDID[15] !== 1'bz) && CFGVENDID[15]; // rv 0 + assign CFGVENDID_in[1] = (CFGVENDID[1] !== 1'bz) && CFGVENDID[1]; // rv 0 + assign CFGVENDID_in[2] = (CFGVENDID[2] !== 1'bz) && CFGVENDID[2]; // rv 0 + assign CFGVENDID_in[3] = (CFGVENDID[3] !== 1'bz) && CFGVENDID[3]; // rv 0 + assign CFGVENDID_in[4] = (CFGVENDID[4] !== 1'bz) && CFGVENDID[4]; // rv 0 + assign CFGVENDID_in[5] = (CFGVENDID[5] !== 1'bz) && CFGVENDID[5]; // rv 0 + assign CFGVENDID_in[6] = (CFGVENDID[6] !== 1'bz) && CFGVENDID[6]; // rv 0 + assign CFGVENDID_in[7] = (CFGVENDID[7] !== 1'bz) && CFGVENDID[7]; // rv 0 + assign CFGVENDID_in[8] = (CFGVENDID[8] !== 1'bz) && CFGVENDID[8]; // rv 0 + assign CFGVENDID_in[9] = (CFGVENDID[9] !== 1'bz) && CFGVENDID[9]; // rv 0 + assign CFGVFFLRDONE_in = (CFGVFFLRDONE !== 1'bz) && CFGVFFLRDONE; // rv 0 + assign CFGVFFLRFUNCNUM_in[0] = (CFGVFFLRFUNCNUM[0] !== 1'bz) && CFGVFFLRFUNCNUM[0]; // rv 0 + assign CFGVFFLRFUNCNUM_in[1] = (CFGVFFLRFUNCNUM[1] !== 1'bz) && CFGVFFLRFUNCNUM[1]; // rv 0 + assign CFGVFFLRFUNCNUM_in[2] = (CFGVFFLRFUNCNUM[2] !== 1'bz) && CFGVFFLRFUNCNUM[2]; // rv 0 + assign CFGVFFLRFUNCNUM_in[3] = (CFGVFFLRFUNCNUM[3] !== 1'bz) && CFGVFFLRFUNCNUM[3]; // rv 0 + assign CFGVFFLRFUNCNUM_in[4] = (CFGVFFLRFUNCNUM[4] !== 1'bz) && CFGVFFLRFUNCNUM[4]; // rv 0 + assign CFGVFFLRFUNCNUM_in[5] = (CFGVFFLRFUNCNUM[5] !== 1'bz) && CFGVFFLRFUNCNUM[5]; // rv 0 + assign CFGVFFLRFUNCNUM_in[6] = (CFGVFFLRFUNCNUM[6] !== 1'bz) && CFGVFFLRFUNCNUM[6]; // rv 0 + assign CFGVFFLRFUNCNUM_in[7] = (CFGVFFLRFUNCNUM[7] !== 1'bz) && CFGVFFLRFUNCNUM[7]; // rv 0 + assign CONFMCAPREQUESTBYCONF_in = (CONFMCAPREQUESTBYCONF !== 1'bz) && CONFMCAPREQUESTBYCONF; // rv 0 + assign CONFREQDATA_in[0] = (CONFREQDATA[0] !== 1'bz) && CONFREQDATA[0]; // rv 0 + assign CONFREQDATA_in[10] = (CONFREQDATA[10] !== 1'bz) && CONFREQDATA[10]; // rv 0 + assign CONFREQDATA_in[11] = (CONFREQDATA[11] !== 1'bz) && CONFREQDATA[11]; // rv 0 + assign CONFREQDATA_in[12] = (CONFREQDATA[12] !== 1'bz) && CONFREQDATA[12]; // rv 0 + assign CONFREQDATA_in[13] = (CONFREQDATA[13] !== 1'bz) && CONFREQDATA[13]; // rv 0 + assign CONFREQDATA_in[14] = (CONFREQDATA[14] !== 1'bz) && CONFREQDATA[14]; // rv 0 + assign CONFREQDATA_in[15] = (CONFREQDATA[15] !== 1'bz) && CONFREQDATA[15]; // rv 0 + assign CONFREQDATA_in[16] = (CONFREQDATA[16] !== 1'bz) && CONFREQDATA[16]; // rv 0 + assign CONFREQDATA_in[17] = (CONFREQDATA[17] !== 1'bz) && CONFREQDATA[17]; // rv 0 + assign CONFREQDATA_in[18] = (CONFREQDATA[18] !== 1'bz) && CONFREQDATA[18]; // rv 0 + assign CONFREQDATA_in[19] = (CONFREQDATA[19] !== 1'bz) && CONFREQDATA[19]; // rv 0 + assign CONFREQDATA_in[1] = (CONFREQDATA[1] !== 1'bz) && CONFREQDATA[1]; // rv 0 + assign CONFREQDATA_in[20] = (CONFREQDATA[20] !== 1'bz) && CONFREQDATA[20]; // rv 0 + assign CONFREQDATA_in[21] = (CONFREQDATA[21] !== 1'bz) && CONFREQDATA[21]; // rv 0 + assign CONFREQDATA_in[22] = (CONFREQDATA[22] !== 1'bz) && CONFREQDATA[22]; // rv 0 + assign CONFREQDATA_in[23] = (CONFREQDATA[23] !== 1'bz) && CONFREQDATA[23]; // rv 0 + assign CONFREQDATA_in[24] = (CONFREQDATA[24] !== 1'bz) && CONFREQDATA[24]; // rv 0 + assign CONFREQDATA_in[25] = (CONFREQDATA[25] !== 1'bz) && CONFREQDATA[25]; // rv 0 + assign CONFREQDATA_in[26] = (CONFREQDATA[26] !== 1'bz) && CONFREQDATA[26]; // rv 0 + assign CONFREQDATA_in[27] = (CONFREQDATA[27] !== 1'bz) && CONFREQDATA[27]; // rv 0 + assign CONFREQDATA_in[28] = (CONFREQDATA[28] !== 1'bz) && CONFREQDATA[28]; // rv 0 + assign CONFREQDATA_in[29] = (CONFREQDATA[29] !== 1'bz) && CONFREQDATA[29]; // rv 0 + assign CONFREQDATA_in[2] = (CONFREQDATA[2] !== 1'bz) && CONFREQDATA[2]; // rv 0 + assign CONFREQDATA_in[30] = (CONFREQDATA[30] !== 1'bz) && CONFREQDATA[30]; // rv 0 + assign CONFREQDATA_in[31] = (CONFREQDATA[31] !== 1'bz) && CONFREQDATA[31]; // rv 0 + assign CONFREQDATA_in[3] = (CONFREQDATA[3] !== 1'bz) && CONFREQDATA[3]; // rv 0 + assign CONFREQDATA_in[4] = (CONFREQDATA[4] !== 1'bz) && CONFREQDATA[4]; // rv 0 + assign CONFREQDATA_in[5] = (CONFREQDATA[5] !== 1'bz) && CONFREQDATA[5]; // rv 0 + assign CONFREQDATA_in[6] = (CONFREQDATA[6] !== 1'bz) && CONFREQDATA[6]; // rv 0 + assign CONFREQDATA_in[7] = (CONFREQDATA[7] !== 1'bz) && CONFREQDATA[7]; // rv 0 + assign CONFREQDATA_in[8] = (CONFREQDATA[8] !== 1'bz) && CONFREQDATA[8]; // rv 0 + assign CONFREQDATA_in[9] = (CONFREQDATA[9] !== 1'bz) && CONFREQDATA[9]; // rv 0 + assign CONFREQREGNUM_in[0] = (CONFREQREGNUM[0] !== 1'bz) && CONFREQREGNUM[0]; // rv 0 + assign CONFREQREGNUM_in[1] = (CONFREQREGNUM[1] !== 1'bz) && CONFREQREGNUM[1]; // rv 0 + assign CONFREQREGNUM_in[2] = (CONFREQREGNUM[2] !== 1'bz) && CONFREQREGNUM[2]; // rv 0 + assign CONFREQREGNUM_in[3] = (CONFREQREGNUM[3] !== 1'bz) && CONFREQREGNUM[3]; // rv 0 + assign CONFREQTYPE_in[0] = (CONFREQTYPE[0] !== 1'bz) && CONFREQTYPE[0]; // rv 0 + assign CONFREQTYPE_in[1] = (CONFREQTYPE[1] !== 1'bz) && CONFREQTYPE[1]; // rv 0 + assign CONFREQVALID_in = (CONFREQVALID !== 1'bz) && CONFREQVALID; // rv 0 + assign CORECLK_in = (CORECLK !== 1'bz) && CORECLK; // rv 0 + assign DBGSEL0_in[0] = (DBGSEL0[0] !== 1'bz) && DBGSEL0[0]; // rv 0 + assign DBGSEL0_in[1] = (DBGSEL0[1] !== 1'bz) && DBGSEL0[1]; // rv 0 + assign DBGSEL0_in[2] = (DBGSEL0[2] !== 1'bz) && DBGSEL0[2]; // rv 0 + assign DBGSEL0_in[3] = (DBGSEL0[3] !== 1'bz) && DBGSEL0[3]; // rv 0 + assign DBGSEL0_in[4] = (DBGSEL0[4] !== 1'bz) && DBGSEL0[4]; // rv 0 + assign DBGSEL0_in[5] = (DBGSEL0[5] !== 1'bz) && DBGSEL0[5]; // rv 0 + assign DBGSEL1_in[0] = (DBGSEL1[0] !== 1'bz) && DBGSEL1[0]; // rv 0 + assign DBGSEL1_in[1] = (DBGSEL1[1] !== 1'bz) && DBGSEL1[1]; // rv 0 + assign DBGSEL1_in[2] = (DBGSEL1[2] !== 1'bz) && DBGSEL1[2]; // rv 0 + assign DBGSEL1_in[3] = (DBGSEL1[3] !== 1'bz) && DBGSEL1[3]; // rv 0 + assign DBGSEL1_in[4] = (DBGSEL1[4] !== 1'bz) && DBGSEL1[4]; // rv 0 + assign DBGSEL1_in[5] = (DBGSEL1[5] !== 1'bz) && DBGSEL1[5]; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign MAXISCQTREADY_in[0] = (MAXISCQTREADY[0] !== 1'bz) && MAXISCQTREADY[0]; // rv 0 + assign MAXISCQTREADY_in[10] = (MAXISCQTREADY[10] !== 1'bz) && MAXISCQTREADY[10]; // rv 0 + assign MAXISCQTREADY_in[11] = (MAXISCQTREADY[11] !== 1'bz) && MAXISCQTREADY[11]; // rv 0 + assign MAXISCQTREADY_in[12] = (MAXISCQTREADY[12] !== 1'bz) && MAXISCQTREADY[12]; // rv 0 + assign MAXISCQTREADY_in[13] = (MAXISCQTREADY[13] !== 1'bz) && MAXISCQTREADY[13]; // rv 0 + assign MAXISCQTREADY_in[14] = (MAXISCQTREADY[14] !== 1'bz) && MAXISCQTREADY[14]; // rv 0 + assign MAXISCQTREADY_in[15] = (MAXISCQTREADY[15] !== 1'bz) && MAXISCQTREADY[15]; // rv 0 + assign MAXISCQTREADY_in[16] = (MAXISCQTREADY[16] !== 1'bz) && MAXISCQTREADY[16]; // rv 0 + assign MAXISCQTREADY_in[17] = (MAXISCQTREADY[17] !== 1'bz) && MAXISCQTREADY[17]; // rv 0 + assign MAXISCQTREADY_in[18] = (MAXISCQTREADY[18] !== 1'bz) && MAXISCQTREADY[18]; // rv 0 + assign MAXISCQTREADY_in[19] = (MAXISCQTREADY[19] !== 1'bz) && MAXISCQTREADY[19]; // rv 0 + assign MAXISCQTREADY_in[1] = (MAXISCQTREADY[1] !== 1'bz) && MAXISCQTREADY[1]; // rv 0 + assign MAXISCQTREADY_in[20] = (MAXISCQTREADY[20] !== 1'bz) && MAXISCQTREADY[20]; // rv 0 + assign MAXISCQTREADY_in[21] = (MAXISCQTREADY[21] !== 1'bz) && MAXISCQTREADY[21]; // rv 0 + assign MAXISCQTREADY_in[2] = (MAXISCQTREADY[2] !== 1'bz) && MAXISCQTREADY[2]; // rv 0 + assign MAXISCQTREADY_in[3] = (MAXISCQTREADY[3] !== 1'bz) && MAXISCQTREADY[3]; // rv 0 + assign MAXISCQTREADY_in[4] = (MAXISCQTREADY[4] !== 1'bz) && MAXISCQTREADY[4]; // rv 0 + assign MAXISCQTREADY_in[5] = (MAXISCQTREADY[5] !== 1'bz) && MAXISCQTREADY[5]; // rv 0 + assign MAXISCQTREADY_in[6] = (MAXISCQTREADY[6] !== 1'bz) && MAXISCQTREADY[6]; // rv 0 + assign MAXISCQTREADY_in[7] = (MAXISCQTREADY[7] !== 1'bz) && MAXISCQTREADY[7]; // rv 0 + assign MAXISCQTREADY_in[8] = (MAXISCQTREADY[8] !== 1'bz) && MAXISCQTREADY[8]; // rv 0 + assign MAXISCQTREADY_in[9] = (MAXISCQTREADY[9] !== 1'bz) && MAXISCQTREADY[9]; // rv 0 + assign MAXISRCTREADY_in[0] = (MAXISRCTREADY[0] !== 1'bz) && MAXISRCTREADY[0]; // rv 0 + assign MAXISRCTREADY_in[10] = (MAXISRCTREADY[10] !== 1'bz) && MAXISRCTREADY[10]; // rv 0 + assign MAXISRCTREADY_in[11] = (MAXISRCTREADY[11] !== 1'bz) && MAXISRCTREADY[11]; // rv 0 + assign MAXISRCTREADY_in[12] = (MAXISRCTREADY[12] !== 1'bz) && MAXISRCTREADY[12]; // rv 0 + assign MAXISRCTREADY_in[13] = (MAXISRCTREADY[13] !== 1'bz) && MAXISRCTREADY[13]; // rv 0 + assign MAXISRCTREADY_in[14] = (MAXISRCTREADY[14] !== 1'bz) && MAXISRCTREADY[14]; // rv 0 + assign MAXISRCTREADY_in[15] = (MAXISRCTREADY[15] !== 1'bz) && MAXISRCTREADY[15]; // rv 0 + assign MAXISRCTREADY_in[16] = (MAXISRCTREADY[16] !== 1'bz) && MAXISRCTREADY[16]; // rv 0 + assign MAXISRCTREADY_in[17] = (MAXISRCTREADY[17] !== 1'bz) && MAXISRCTREADY[17]; // rv 0 + assign MAXISRCTREADY_in[18] = (MAXISRCTREADY[18] !== 1'bz) && MAXISRCTREADY[18]; // rv 0 + assign MAXISRCTREADY_in[19] = (MAXISRCTREADY[19] !== 1'bz) && MAXISRCTREADY[19]; // rv 0 + assign MAXISRCTREADY_in[1] = (MAXISRCTREADY[1] !== 1'bz) && MAXISRCTREADY[1]; // rv 0 + assign MAXISRCTREADY_in[20] = (MAXISRCTREADY[20] !== 1'bz) && MAXISRCTREADY[20]; // rv 0 + assign MAXISRCTREADY_in[21] = (MAXISRCTREADY[21] !== 1'bz) && MAXISRCTREADY[21]; // rv 0 + assign MAXISRCTREADY_in[2] = (MAXISRCTREADY[2] !== 1'bz) && MAXISRCTREADY[2]; // rv 0 + assign MAXISRCTREADY_in[3] = (MAXISRCTREADY[3] !== 1'bz) && MAXISRCTREADY[3]; // rv 0 + assign MAXISRCTREADY_in[4] = (MAXISRCTREADY[4] !== 1'bz) && MAXISRCTREADY[4]; // rv 0 + assign MAXISRCTREADY_in[5] = (MAXISRCTREADY[5] !== 1'bz) && MAXISRCTREADY[5]; // rv 0 + assign MAXISRCTREADY_in[6] = (MAXISRCTREADY[6] !== 1'bz) && MAXISRCTREADY[6]; // rv 0 + assign MAXISRCTREADY_in[7] = (MAXISRCTREADY[7] !== 1'bz) && MAXISRCTREADY[7]; // rv 0 + assign MAXISRCTREADY_in[8] = (MAXISRCTREADY[8] !== 1'bz) && MAXISRCTREADY[8]; // rv 0 + assign MAXISRCTREADY_in[9] = (MAXISRCTREADY[9] !== 1'bz) && MAXISRCTREADY[9]; // rv 0 + assign MIREPLAYRAMERRCOR_in[0] = (MIREPLAYRAMERRCOR[0] !== 1'bz) && MIREPLAYRAMERRCOR[0]; // rv 0 + assign MIREPLAYRAMERRCOR_in[1] = (MIREPLAYRAMERRCOR[1] !== 1'bz) && MIREPLAYRAMERRCOR[1]; // rv 0 + assign MIREPLAYRAMERRCOR_in[2] = (MIREPLAYRAMERRCOR[2] !== 1'bz) && MIREPLAYRAMERRCOR[2]; // rv 0 + assign MIREPLAYRAMERRCOR_in[3] = (MIREPLAYRAMERRCOR[3] !== 1'bz) && MIREPLAYRAMERRCOR[3]; // rv 0 + assign MIREPLAYRAMERRCOR_in[4] = (MIREPLAYRAMERRCOR[4] !== 1'bz) && MIREPLAYRAMERRCOR[4]; // rv 0 + assign MIREPLAYRAMERRCOR_in[5] = (MIREPLAYRAMERRCOR[5] !== 1'bz) && MIREPLAYRAMERRCOR[5]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[0] = (MIREPLAYRAMERRUNCOR[0] !== 1'bz) && MIREPLAYRAMERRUNCOR[0]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[1] = (MIREPLAYRAMERRUNCOR[1] !== 1'bz) && MIREPLAYRAMERRUNCOR[1]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[2] = (MIREPLAYRAMERRUNCOR[2] !== 1'bz) && MIREPLAYRAMERRUNCOR[2]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[3] = (MIREPLAYRAMERRUNCOR[3] !== 1'bz) && MIREPLAYRAMERRUNCOR[3]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[4] = (MIREPLAYRAMERRUNCOR[4] !== 1'bz) && MIREPLAYRAMERRUNCOR[4]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[5] = (MIREPLAYRAMERRUNCOR[5] !== 1'bz) && MIREPLAYRAMERRUNCOR[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[0] = (MIREPLAYRAMREADDATA0[0] !== 1'bz) && MIREPLAYRAMREADDATA0[0]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[100] = (MIREPLAYRAMREADDATA0[100] !== 1'bz) && MIREPLAYRAMREADDATA0[100]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[101] = (MIREPLAYRAMREADDATA0[101] !== 1'bz) && MIREPLAYRAMREADDATA0[101]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[102] = (MIREPLAYRAMREADDATA0[102] !== 1'bz) && MIREPLAYRAMREADDATA0[102]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[103] = (MIREPLAYRAMREADDATA0[103] !== 1'bz) && MIREPLAYRAMREADDATA0[103]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[104] = (MIREPLAYRAMREADDATA0[104] !== 1'bz) && MIREPLAYRAMREADDATA0[104]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[105] = (MIREPLAYRAMREADDATA0[105] !== 1'bz) && MIREPLAYRAMREADDATA0[105]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[106] = (MIREPLAYRAMREADDATA0[106] !== 1'bz) && MIREPLAYRAMREADDATA0[106]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[107] = (MIREPLAYRAMREADDATA0[107] !== 1'bz) && MIREPLAYRAMREADDATA0[107]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[108] = (MIREPLAYRAMREADDATA0[108] !== 1'bz) && MIREPLAYRAMREADDATA0[108]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[109] = (MIREPLAYRAMREADDATA0[109] !== 1'bz) && MIREPLAYRAMREADDATA0[109]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[10] = (MIREPLAYRAMREADDATA0[10] !== 1'bz) && MIREPLAYRAMREADDATA0[10]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[110] = (MIREPLAYRAMREADDATA0[110] !== 1'bz) && MIREPLAYRAMREADDATA0[110]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[111] = (MIREPLAYRAMREADDATA0[111] !== 1'bz) && MIREPLAYRAMREADDATA0[111]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[112] = (MIREPLAYRAMREADDATA0[112] !== 1'bz) && MIREPLAYRAMREADDATA0[112]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[113] = (MIREPLAYRAMREADDATA0[113] !== 1'bz) && MIREPLAYRAMREADDATA0[113]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[114] = (MIREPLAYRAMREADDATA0[114] !== 1'bz) && MIREPLAYRAMREADDATA0[114]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[115] = (MIREPLAYRAMREADDATA0[115] !== 1'bz) && MIREPLAYRAMREADDATA0[115]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[116] = (MIREPLAYRAMREADDATA0[116] !== 1'bz) && MIREPLAYRAMREADDATA0[116]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[117] = (MIREPLAYRAMREADDATA0[117] !== 1'bz) && MIREPLAYRAMREADDATA0[117]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[118] = (MIREPLAYRAMREADDATA0[118] !== 1'bz) && MIREPLAYRAMREADDATA0[118]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[119] = (MIREPLAYRAMREADDATA0[119] !== 1'bz) && MIREPLAYRAMREADDATA0[119]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[11] = (MIREPLAYRAMREADDATA0[11] !== 1'bz) && MIREPLAYRAMREADDATA0[11]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[120] = (MIREPLAYRAMREADDATA0[120] !== 1'bz) && MIREPLAYRAMREADDATA0[120]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[121] = (MIREPLAYRAMREADDATA0[121] !== 1'bz) && MIREPLAYRAMREADDATA0[121]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[122] = (MIREPLAYRAMREADDATA0[122] !== 1'bz) && MIREPLAYRAMREADDATA0[122]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[123] = (MIREPLAYRAMREADDATA0[123] !== 1'bz) && MIREPLAYRAMREADDATA0[123]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[124] = (MIREPLAYRAMREADDATA0[124] !== 1'bz) && MIREPLAYRAMREADDATA0[124]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[125] = (MIREPLAYRAMREADDATA0[125] !== 1'bz) && MIREPLAYRAMREADDATA0[125]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[126] = (MIREPLAYRAMREADDATA0[126] !== 1'bz) && MIREPLAYRAMREADDATA0[126]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[127] = (MIREPLAYRAMREADDATA0[127] !== 1'bz) && MIREPLAYRAMREADDATA0[127]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[12] = (MIREPLAYRAMREADDATA0[12] !== 1'bz) && MIREPLAYRAMREADDATA0[12]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[13] = (MIREPLAYRAMREADDATA0[13] !== 1'bz) && MIREPLAYRAMREADDATA0[13]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[14] = (MIREPLAYRAMREADDATA0[14] !== 1'bz) && MIREPLAYRAMREADDATA0[14]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[15] = (MIREPLAYRAMREADDATA0[15] !== 1'bz) && MIREPLAYRAMREADDATA0[15]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[16] = (MIREPLAYRAMREADDATA0[16] !== 1'bz) && MIREPLAYRAMREADDATA0[16]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[17] = (MIREPLAYRAMREADDATA0[17] !== 1'bz) && MIREPLAYRAMREADDATA0[17]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[18] = (MIREPLAYRAMREADDATA0[18] !== 1'bz) && MIREPLAYRAMREADDATA0[18]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[19] = (MIREPLAYRAMREADDATA0[19] !== 1'bz) && MIREPLAYRAMREADDATA0[19]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[1] = (MIREPLAYRAMREADDATA0[1] !== 1'bz) && MIREPLAYRAMREADDATA0[1]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[20] = (MIREPLAYRAMREADDATA0[20] !== 1'bz) && MIREPLAYRAMREADDATA0[20]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[21] = (MIREPLAYRAMREADDATA0[21] !== 1'bz) && MIREPLAYRAMREADDATA0[21]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[22] = (MIREPLAYRAMREADDATA0[22] !== 1'bz) && MIREPLAYRAMREADDATA0[22]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[23] = (MIREPLAYRAMREADDATA0[23] !== 1'bz) && MIREPLAYRAMREADDATA0[23]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[24] = (MIREPLAYRAMREADDATA0[24] !== 1'bz) && MIREPLAYRAMREADDATA0[24]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[25] = (MIREPLAYRAMREADDATA0[25] !== 1'bz) && MIREPLAYRAMREADDATA0[25]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[26] = (MIREPLAYRAMREADDATA0[26] !== 1'bz) && MIREPLAYRAMREADDATA0[26]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[27] = (MIREPLAYRAMREADDATA0[27] !== 1'bz) && MIREPLAYRAMREADDATA0[27]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[28] = (MIREPLAYRAMREADDATA0[28] !== 1'bz) && MIREPLAYRAMREADDATA0[28]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[29] = (MIREPLAYRAMREADDATA0[29] !== 1'bz) && MIREPLAYRAMREADDATA0[29]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[2] = (MIREPLAYRAMREADDATA0[2] !== 1'bz) && MIREPLAYRAMREADDATA0[2]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[30] = (MIREPLAYRAMREADDATA0[30] !== 1'bz) && MIREPLAYRAMREADDATA0[30]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[31] = (MIREPLAYRAMREADDATA0[31] !== 1'bz) && MIREPLAYRAMREADDATA0[31]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[32] = (MIREPLAYRAMREADDATA0[32] !== 1'bz) && MIREPLAYRAMREADDATA0[32]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[33] = (MIREPLAYRAMREADDATA0[33] !== 1'bz) && MIREPLAYRAMREADDATA0[33]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[34] = (MIREPLAYRAMREADDATA0[34] !== 1'bz) && MIREPLAYRAMREADDATA0[34]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[35] = (MIREPLAYRAMREADDATA0[35] !== 1'bz) && MIREPLAYRAMREADDATA0[35]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[36] = (MIREPLAYRAMREADDATA0[36] !== 1'bz) && MIREPLAYRAMREADDATA0[36]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[37] = (MIREPLAYRAMREADDATA0[37] !== 1'bz) && MIREPLAYRAMREADDATA0[37]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[38] = (MIREPLAYRAMREADDATA0[38] !== 1'bz) && MIREPLAYRAMREADDATA0[38]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[39] = (MIREPLAYRAMREADDATA0[39] !== 1'bz) && MIREPLAYRAMREADDATA0[39]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[3] = (MIREPLAYRAMREADDATA0[3] !== 1'bz) && MIREPLAYRAMREADDATA0[3]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[40] = (MIREPLAYRAMREADDATA0[40] !== 1'bz) && MIREPLAYRAMREADDATA0[40]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[41] = (MIREPLAYRAMREADDATA0[41] !== 1'bz) && MIREPLAYRAMREADDATA0[41]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[42] = (MIREPLAYRAMREADDATA0[42] !== 1'bz) && MIREPLAYRAMREADDATA0[42]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[43] = (MIREPLAYRAMREADDATA0[43] !== 1'bz) && MIREPLAYRAMREADDATA0[43]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[44] = (MIREPLAYRAMREADDATA0[44] !== 1'bz) && MIREPLAYRAMREADDATA0[44]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[45] = (MIREPLAYRAMREADDATA0[45] !== 1'bz) && MIREPLAYRAMREADDATA0[45]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[46] = (MIREPLAYRAMREADDATA0[46] !== 1'bz) && MIREPLAYRAMREADDATA0[46]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[47] = (MIREPLAYRAMREADDATA0[47] !== 1'bz) && MIREPLAYRAMREADDATA0[47]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[48] = (MIREPLAYRAMREADDATA0[48] !== 1'bz) && MIREPLAYRAMREADDATA0[48]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[49] = (MIREPLAYRAMREADDATA0[49] !== 1'bz) && MIREPLAYRAMREADDATA0[49]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[4] = (MIREPLAYRAMREADDATA0[4] !== 1'bz) && MIREPLAYRAMREADDATA0[4]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[50] = (MIREPLAYRAMREADDATA0[50] !== 1'bz) && MIREPLAYRAMREADDATA0[50]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[51] = (MIREPLAYRAMREADDATA0[51] !== 1'bz) && MIREPLAYRAMREADDATA0[51]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[52] = (MIREPLAYRAMREADDATA0[52] !== 1'bz) && MIREPLAYRAMREADDATA0[52]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[53] = (MIREPLAYRAMREADDATA0[53] !== 1'bz) && MIREPLAYRAMREADDATA0[53]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[54] = (MIREPLAYRAMREADDATA0[54] !== 1'bz) && MIREPLAYRAMREADDATA0[54]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[55] = (MIREPLAYRAMREADDATA0[55] !== 1'bz) && MIREPLAYRAMREADDATA0[55]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[56] = (MIREPLAYRAMREADDATA0[56] !== 1'bz) && MIREPLAYRAMREADDATA0[56]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[57] = (MIREPLAYRAMREADDATA0[57] !== 1'bz) && MIREPLAYRAMREADDATA0[57]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[58] = (MIREPLAYRAMREADDATA0[58] !== 1'bz) && MIREPLAYRAMREADDATA0[58]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[59] = (MIREPLAYRAMREADDATA0[59] !== 1'bz) && MIREPLAYRAMREADDATA0[59]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[5] = (MIREPLAYRAMREADDATA0[5] !== 1'bz) && MIREPLAYRAMREADDATA0[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[60] = (MIREPLAYRAMREADDATA0[60] !== 1'bz) && MIREPLAYRAMREADDATA0[60]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[61] = (MIREPLAYRAMREADDATA0[61] !== 1'bz) && MIREPLAYRAMREADDATA0[61]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[62] = (MIREPLAYRAMREADDATA0[62] !== 1'bz) && MIREPLAYRAMREADDATA0[62]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[63] = (MIREPLAYRAMREADDATA0[63] !== 1'bz) && MIREPLAYRAMREADDATA0[63]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[64] = (MIREPLAYRAMREADDATA0[64] !== 1'bz) && MIREPLAYRAMREADDATA0[64]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[65] = (MIREPLAYRAMREADDATA0[65] !== 1'bz) && MIREPLAYRAMREADDATA0[65]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[66] = (MIREPLAYRAMREADDATA0[66] !== 1'bz) && MIREPLAYRAMREADDATA0[66]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[67] = (MIREPLAYRAMREADDATA0[67] !== 1'bz) && MIREPLAYRAMREADDATA0[67]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[68] = (MIREPLAYRAMREADDATA0[68] !== 1'bz) && MIREPLAYRAMREADDATA0[68]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[69] = (MIREPLAYRAMREADDATA0[69] !== 1'bz) && MIREPLAYRAMREADDATA0[69]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[6] = (MIREPLAYRAMREADDATA0[6] !== 1'bz) && MIREPLAYRAMREADDATA0[6]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[70] = (MIREPLAYRAMREADDATA0[70] !== 1'bz) && MIREPLAYRAMREADDATA0[70]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[71] = (MIREPLAYRAMREADDATA0[71] !== 1'bz) && MIREPLAYRAMREADDATA0[71]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[72] = (MIREPLAYRAMREADDATA0[72] !== 1'bz) && MIREPLAYRAMREADDATA0[72]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[73] = (MIREPLAYRAMREADDATA0[73] !== 1'bz) && MIREPLAYRAMREADDATA0[73]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[74] = (MIREPLAYRAMREADDATA0[74] !== 1'bz) && MIREPLAYRAMREADDATA0[74]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[75] = (MIREPLAYRAMREADDATA0[75] !== 1'bz) && MIREPLAYRAMREADDATA0[75]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[76] = (MIREPLAYRAMREADDATA0[76] !== 1'bz) && MIREPLAYRAMREADDATA0[76]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[77] = (MIREPLAYRAMREADDATA0[77] !== 1'bz) && MIREPLAYRAMREADDATA0[77]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[78] = (MIREPLAYRAMREADDATA0[78] !== 1'bz) && MIREPLAYRAMREADDATA0[78]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[79] = (MIREPLAYRAMREADDATA0[79] !== 1'bz) && MIREPLAYRAMREADDATA0[79]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[7] = (MIREPLAYRAMREADDATA0[7] !== 1'bz) && MIREPLAYRAMREADDATA0[7]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[80] = (MIREPLAYRAMREADDATA0[80] !== 1'bz) && MIREPLAYRAMREADDATA0[80]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[81] = (MIREPLAYRAMREADDATA0[81] !== 1'bz) && MIREPLAYRAMREADDATA0[81]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[82] = (MIREPLAYRAMREADDATA0[82] !== 1'bz) && MIREPLAYRAMREADDATA0[82]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[83] = (MIREPLAYRAMREADDATA0[83] !== 1'bz) && MIREPLAYRAMREADDATA0[83]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[84] = (MIREPLAYRAMREADDATA0[84] !== 1'bz) && MIREPLAYRAMREADDATA0[84]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[85] = (MIREPLAYRAMREADDATA0[85] !== 1'bz) && MIREPLAYRAMREADDATA0[85]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[86] = (MIREPLAYRAMREADDATA0[86] !== 1'bz) && MIREPLAYRAMREADDATA0[86]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[87] = (MIREPLAYRAMREADDATA0[87] !== 1'bz) && MIREPLAYRAMREADDATA0[87]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[88] = (MIREPLAYRAMREADDATA0[88] !== 1'bz) && MIREPLAYRAMREADDATA0[88]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[89] = (MIREPLAYRAMREADDATA0[89] !== 1'bz) && MIREPLAYRAMREADDATA0[89]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[8] = (MIREPLAYRAMREADDATA0[8] !== 1'bz) && MIREPLAYRAMREADDATA0[8]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[90] = (MIREPLAYRAMREADDATA0[90] !== 1'bz) && MIREPLAYRAMREADDATA0[90]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[91] = (MIREPLAYRAMREADDATA0[91] !== 1'bz) && MIREPLAYRAMREADDATA0[91]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[92] = (MIREPLAYRAMREADDATA0[92] !== 1'bz) && MIREPLAYRAMREADDATA0[92]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[93] = (MIREPLAYRAMREADDATA0[93] !== 1'bz) && MIREPLAYRAMREADDATA0[93]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[94] = (MIREPLAYRAMREADDATA0[94] !== 1'bz) && MIREPLAYRAMREADDATA0[94]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[95] = (MIREPLAYRAMREADDATA0[95] !== 1'bz) && MIREPLAYRAMREADDATA0[95]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[96] = (MIREPLAYRAMREADDATA0[96] !== 1'bz) && MIREPLAYRAMREADDATA0[96]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[97] = (MIREPLAYRAMREADDATA0[97] !== 1'bz) && MIREPLAYRAMREADDATA0[97]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[98] = (MIREPLAYRAMREADDATA0[98] !== 1'bz) && MIREPLAYRAMREADDATA0[98]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[99] = (MIREPLAYRAMREADDATA0[99] !== 1'bz) && MIREPLAYRAMREADDATA0[99]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[9] = (MIREPLAYRAMREADDATA0[9] !== 1'bz) && MIREPLAYRAMREADDATA0[9]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[0] = (MIREPLAYRAMREADDATA1[0] !== 1'bz) && MIREPLAYRAMREADDATA1[0]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[100] = (MIREPLAYRAMREADDATA1[100] !== 1'bz) && MIREPLAYRAMREADDATA1[100]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[101] = (MIREPLAYRAMREADDATA1[101] !== 1'bz) && MIREPLAYRAMREADDATA1[101]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[102] = (MIREPLAYRAMREADDATA1[102] !== 1'bz) && MIREPLAYRAMREADDATA1[102]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[103] = (MIREPLAYRAMREADDATA1[103] !== 1'bz) && MIREPLAYRAMREADDATA1[103]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[104] = (MIREPLAYRAMREADDATA1[104] !== 1'bz) && MIREPLAYRAMREADDATA1[104]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[105] = (MIREPLAYRAMREADDATA1[105] !== 1'bz) && MIREPLAYRAMREADDATA1[105]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[106] = (MIREPLAYRAMREADDATA1[106] !== 1'bz) && MIREPLAYRAMREADDATA1[106]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[107] = (MIREPLAYRAMREADDATA1[107] !== 1'bz) && MIREPLAYRAMREADDATA1[107]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[108] = (MIREPLAYRAMREADDATA1[108] !== 1'bz) && MIREPLAYRAMREADDATA1[108]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[109] = (MIREPLAYRAMREADDATA1[109] !== 1'bz) && MIREPLAYRAMREADDATA1[109]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[10] = (MIREPLAYRAMREADDATA1[10] !== 1'bz) && MIREPLAYRAMREADDATA1[10]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[110] = (MIREPLAYRAMREADDATA1[110] !== 1'bz) && MIREPLAYRAMREADDATA1[110]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[111] = (MIREPLAYRAMREADDATA1[111] !== 1'bz) && MIREPLAYRAMREADDATA1[111]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[112] = (MIREPLAYRAMREADDATA1[112] !== 1'bz) && MIREPLAYRAMREADDATA1[112]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[113] = (MIREPLAYRAMREADDATA1[113] !== 1'bz) && MIREPLAYRAMREADDATA1[113]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[114] = (MIREPLAYRAMREADDATA1[114] !== 1'bz) && MIREPLAYRAMREADDATA1[114]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[115] = (MIREPLAYRAMREADDATA1[115] !== 1'bz) && MIREPLAYRAMREADDATA1[115]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[116] = (MIREPLAYRAMREADDATA1[116] !== 1'bz) && MIREPLAYRAMREADDATA1[116]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[117] = (MIREPLAYRAMREADDATA1[117] !== 1'bz) && MIREPLAYRAMREADDATA1[117]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[118] = (MIREPLAYRAMREADDATA1[118] !== 1'bz) && MIREPLAYRAMREADDATA1[118]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[119] = (MIREPLAYRAMREADDATA1[119] !== 1'bz) && MIREPLAYRAMREADDATA1[119]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[11] = (MIREPLAYRAMREADDATA1[11] !== 1'bz) && MIREPLAYRAMREADDATA1[11]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[120] = (MIREPLAYRAMREADDATA1[120] !== 1'bz) && MIREPLAYRAMREADDATA1[120]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[121] = (MIREPLAYRAMREADDATA1[121] !== 1'bz) && MIREPLAYRAMREADDATA1[121]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[122] = (MIREPLAYRAMREADDATA1[122] !== 1'bz) && MIREPLAYRAMREADDATA1[122]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[123] = (MIREPLAYRAMREADDATA1[123] !== 1'bz) && MIREPLAYRAMREADDATA1[123]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[124] = (MIREPLAYRAMREADDATA1[124] !== 1'bz) && MIREPLAYRAMREADDATA1[124]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[125] = (MIREPLAYRAMREADDATA1[125] !== 1'bz) && MIREPLAYRAMREADDATA1[125]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[126] = (MIREPLAYRAMREADDATA1[126] !== 1'bz) && MIREPLAYRAMREADDATA1[126]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[127] = (MIREPLAYRAMREADDATA1[127] !== 1'bz) && MIREPLAYRAMREADDATA1[127]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[12] = (MIREPLAYRAMREADDATA1[12] !== 1'bz) && MIREPLAYRAMREADDATA1[12]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[13] = (MIREPLAYRAMREADDATA1[13] !== 1'bz) && MIREPLAYRAMREADDATA1[13]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[14] = (MIREPLAYRAMREADDATA1[14] !== 1'bz) && MIREPLAYRAMREADDATA1[14]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[15] = (MIREPLAYRAMREADDATA1[15] !== 1'bz) && MIREPLAYRAMREADDATA1[15]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[16] = (MIREPLAYRAMREADDATA1[16] !== 1'bz) && MIREPLAYRAMREADDATA1[16]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[17] = (MIREPLAYRAMREADDATA1[17] !== 1'bz) && MIREPLAYRAMREADDATA1[17]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[18] = (MIREPLAYRAMREADDATA1[18] !== 1'bz) && MIREPLAYRAMREADDATA1[18]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[19] = (MIREPLAYRAMREADDATA1[19] !== 1'bz) && MIREPLAYRAMREADDATA1[19]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[1] = (MIREPLAYRAMREADDATA1[1] !== 1'bz) && MIREPLAYRAMREADDATA1[1]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[20] = (MIREPLAYRAMREADDATA1[20] !== 1'bz) && MIREPLAYRAMREADDATA1[20]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[21] = (MIREPLAYRAMREADDATA1[21] !== 1'bz) && MIREPLAYRAMREADDATA1[21]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[22] = (MIREPLAYRAMREADDATA1[22] !== 1'bz) && MIREPLAYRAMREADDATA1[22]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[23] = (MIREPLAYRAMREADDATA1[23] !== 1'bz) && MIREPLAYRAMREADDATA1[23]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[24] = (MIREPLAYRAMREADDATA1[24] !== 1'bz) && MIREPLAYRAMREADDATA1[24]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[25] = (MIREPLAYRAMREADDATA1[25] !== 1'bz) && MIREPLAYRAMREADDATA1[25]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[26] = (MIREPLAYRAMREADDATA1[26] !== 1'bz) && MIREPLAYRAMREADDATA1[26]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[27] = (MIREPLAYRAMREADDATA1[27] !== 1'bz) && MIREPLAYRAMREADDATA1[27]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[28] = (MIREPLAYRAMREADDATA1[28] !== 1'bz) && MIREPLAYRAMREADDATA1[28]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[29] = (MIREPLAYRAMREADDATA1[29] !== 1'bz) && MIREPLAYRAMREADDATA1[29]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[2] = (MIREPLAYRAMREADDATA1[2] !== 1'bz) && MIREPLAYRAMREADDATA1[2]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[30] = (MIREPLAYRAMREADDATA1[30] !== 1'bz) && MIREPLAYRAMREADDATA1[30]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[31] = (MIREPLAYRAMREADDATA1[31] !== 1'bz) && MIREPLAYRAMREADDATA1[31]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[32] = (MIREPLAYRAMREADDATA1[32] !== 1'bz) && MIREPLAYRAMREADDATA1[32]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[33] = (MIREPLAYRAMREADDATA1[33] !== 1'bz) && MIREPLAYRAMREADDATA1[33]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[34] = (MIREPLAYRAMREADDATA1[34] !== 1'bz) && MIREPLAYRAMREADDATA1[34]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[35] = (MIREPLAYRAMREADDATA1[35] !== 1'bz) && MIREPLAYRAMREADDATA1[35]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[36] = (MIREPLAYRAMREADDATA1[36] !== 1'bz) && MIREPLAYRAMREADDATA1[36]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[37] = (MIREPLAYRAMREADDATA1[37] !== 1'bz) && MIREPLAYRAMREADDATA1[37]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[38] = (MIREPLAYRAMREADDATA1[38] !== 1'bz) && MIREPLAYRAMREADDATA1[38]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[39] = (MIREPLAYRAMREADDATA1[39] !== 1'bz) && MIREPLAYRAMREADDATA1[39]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[3] = (MIREPLAYRAMREADDATA1[3] !== 1'bz) && MIREPLAYRAMREADDATA1[3]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[40] = (MIREPLAYRAMREADDATA1[40] !== 1'bz) && MIREPLAYRAMREADDATA1[40]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[41] = (MIREPLAYRAMREADDATA1[41] !== 1'bz) && MIREPLAYRAMREADDATA1[41]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[42] = (MIREPLAYRAMREADDATA1[42] !== 1'bz) && MIREPLAYRAMREADDATA1[42]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[43] = (MIREPLAYRAMREADDATA1[43] !== 1'bz) && MIREPLAYRAMREADDATA1[43]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[44] = (MIREPLAYRAMREADDATA1[44] !== 1'bz) && MIREPLAYRAMREADDATA1[44]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[45] = (MIREPLAYRAMREADDATA1[45] !== 1'bz) && MIREPLAYRAMREADDATA1[45]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[46] = (MIREPLAYRAMREADDATA1[46] !== 1'bz) && MIREPLAYRAMREADDATA1[46]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[47] = (MIREPLAYRAMREADDATA1[47] !== 1'bz) && MIREPLAYRAMREADDATA1[47]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[48] = (MIREPLAYRAMREADDATA1[48] !== 1'bz) && MIREPLAYRAMREADDATA1[48]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[49] = (MIREPLAYRAMREADDATA1[49] !== 1'bz) && MIREPLAYRAMREADDATA1[49]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[4] = (MIREPLAYRAMREADDATA1[4] !== 1'bz) && MIREPLAYRAMREADDATA1[4]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[50] = (MIREPLAYRAMREADDATA1[50] !== 1'bz) && MIREPLAYRAMREADDATA1[50]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[51] = (MIREPLAYRAMREADDATA1[51] !== 1'bz) && MIREPLAYRAMREADDATA1[51]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[52] = (MIREPLAYRAMREADDATA1[52] !== 1'bz) && MIREPLAYRAMREADDATA1[52]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[53] = (MIREPLAYRAMREADDATA1[53] !== 1'bz) && MIREPLAYRAMREADDATA1[53]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[54] = (MIREPLAYRAMREADDATA1[54] !== 1'bz) && MIREPLAYRAMREADDATA1[54]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[55] = (MIREPLAYRAMREADDATA1[55] !== 1'bz) && MIREPLAYRAMREADDATA1[55]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[56] = (MIREPLAYRAMREADDATA1[56] !== 1'bz) && MIREPLAYRAMREADDATA1[56]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[57] = (MIREPLAYRAMREADDATA1[57] !== 1'bz) && MIREPLAYRAMREADDATA1[57]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[58] = (MIREPLAYRAMREADDATA1[58] !== 1'bz) && MIREPLAYRAMREADDATA1[58]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[59] = (MIREPLAYRAMREADDATA1[59] !== 1'bz) && MIREPLAYRAMREADDATA1[59]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[5] = (MIREPLAYRAMREADDATA1[5] !== 1'bz) && MIREPLAYRAMREADDATA1[5]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[60] = (MIREPLAYRAMREADDATA1[60] !== 1'bz) && MIREPLAYRAMREADDATA1[60]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[61] = (MIREPLAYRAMREADDATA1[61] !== 1'bz) && MIREPLAYRAMREADDATA1[61]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[62] = (MIREPLAYRAMREADDATA1[62] !== 1'bz) && MIREPLAYRAMREADDATA1[62]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[63] = (MIREPLAYRAMREADDATA1[63] !== 1'bz) && MIREPLAYRAMREADDATA1[63]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[64] = (MIREPLAYRAMREADDATA1[64] !== 1'bz) && MIREPLAYRAMREADDATA1[64]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[65] = (MIREPLAYRAMREADDATA1[65] !== 1'bz) && MIREPLAYRAMREADDATA1[65]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[66] = (MIREPLAYRAMREADDATA1[66] !== 1'bz) && MIREPLAYRAMREADDATA1[66]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[67] = (MIREPLAYRAMREADDATA1[67] !== 1'bz) && MIREPLAYRAMREADDATA1[67]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[68] = (MIREPLAYRAMREADDATA1[68] !== 1'bz) && MIREPLAYRAMREADDATA1[68]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[69] = (MIREPLAYRAMREADDATA1[69] !== 1'bz) && MIREPLAYRAMREADDATA1[69]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[6] = (MIREPLAYRAMREADDATA1[6] !== 1'bz) && MIREPLAYRAMREADDATA1[6]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[70] = (MIREPLAYRAMREADDATA1[70] !== 1'bz) && MIREPLAYRAMREADDATA1[70]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[71] = (MIREPLAYRAMREADDATA1[71] !== 1'bz) && MIREPLAYRAMREADDATA1[71]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[72] = (MIREPLAYRAMREADDATA1[72] !== 1'bz) && MIREPLAYRAMREADDATA1[72]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[73] = (MIREPLAYRAMREADDATA1[73] !== 1'bz) && MIREPLAYRAMREADDATA1[73]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[74] = (MIREPLAYRAMREADDATA1[74] !== 1'bz) && MIREPLAYRAMREADDATA1[74]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[75] = (MIREPLAYRAMREADDATA1[75] !== 1'bz) && MIREPLAYRAMREADDATA1[75]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[76] = (MIREPLAYRAMREADDATA1[76] !== 1'bz) && MIREPLAYRAMREADDATA1[76]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[77] = (MIREPLAYRAMREADDATA1[77] !== 1'bz) && MIREPLAYRAMREADDATA1[77]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[78] = (MIREPLAYRAMREADDATA1[78] !== 1'bz) && MIREPLAYRAMREADDATA1[78]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[79] = (MIREPLAYRAMREADDATA1[79] !== 1'bz) && MIREPLAYRAMREADDATA1[79]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[7] = (MIREPLAYRAMREADDATA1[7] !== 1'bz) && MIREPLAYRAMREADDATA1[7]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[80] = (MIREPLAYRAMREADDATA1[80] !== 1'bz) && MIREPLAYRAMREADDATA1[80]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[81] = (MIREPLAYRAMREADDATA1[81] !== 1'bz) && MIREPLAYRAMREADDATA1[81]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[82] = (MIREPLAYRAMREADDATA1[82] !== 1'bz) && MIREPLAYRAMREADDATA1[82]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[83] = (MIREPLAYRAMREADDATA1[83] !== 1'bz) && MIREPLAYRAMREADDATA1[83]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[84] = (MIREPLAYRAMREADDATA1[84] !== 1'bz) && MIREPLAYRAMREADDATA1[84]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[85] = (MIREPLAYRAMREADDATA1[85] !== 1'bz) && MIREPLAYRAMREADDATA1[85]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[86] = (MIREPLAYRAMREADDATA1[86] !== 1'bz) && MIREPLAYRAMREADDATA1[86]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[87] = (MIREPLAYRAMREADDATA1[87] !== 1'bz) && MIREPLAYRAMREADDATA1[87]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[88] = (MIREPLAYRAMREADDATA1[88] !== 1'bz) && MIREPLAYRAMREADDATA1[88]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[89] = (MIREPLAYRAMREADDATA1[89] !== 1'bz) && MIREPLAYRAMREADDATA1[89]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[8] = (MIREPLAYRAMREADDATA1[8] !== 1'bz) && MIREPLAYRAMREADDATA1[8]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[90] = (MIREPLAYRAMREADDATA1[90] !== 1'bz) && MIREPLAYRAMREADDATA1[90]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[91] = (MIREPLAYRAMREADDATA1[91] !== 1'bz) && MIREPLAYRAMREADDATA1[91]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[92] = (MIREPLAYRAMREADDATA1[92] !== 1'bz) && MIREPLAYRAMREADDATA1[92]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[93] = (MIREPLAYRAMREADDATA1[93] !== 1'bz) && MIREPLAYRAMREADDATA1[93]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[94] = (MIREPLAYRAMREADDATA1[94] !== 1'bz) && MIREPLAYRAMREADDATA1[94]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[95] = (MIREPLAYRAMREADDATA1[95] !== 1'bz) && MIREPLAYRAMREADDATA1[95]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[96] = (MIREPLAYRAMREADDATA1[96] !== 1'bz) && MIREPLAYRAMREADDATA1[96]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[97] = (MIREPLAYRAMREADDATA1[97] !== 1'bz) && MIREPLAYRAMREADDATA1[97]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[98] = (MIREPLAYRAMREADDATA1[98] !== 1'bz) && MIREPLAYRAMREADDATA1[98]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[99] = (MIREPLAYRAMREADDATA1[99] !== 1'bz) && MIREPLAYRAMREADDATA1[99]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[9] = (MIREPLAYRAMREADDATA1[9] !== 1'bz) && MIREPLAYRAMREADDATA1[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[0] = (MIRXCOMPLETIONRAMERRCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[10] = (MIRXCOMPLETIONRAMERRCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[11] = (MIRXCOMPLETIONRAMERRCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[1] = (MIRXCOMPLETIONRAMERRCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[2] = (MIRXCOMPLETIONRAMERRCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[3] = (MIRXCOMPLETIONRAMERRCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[4] = (MIRXCOMPLETIONRAMERRCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[5] = (MIRXCOMPLETIONRAMERRCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[6] = (MIRXCOMPLETIONRAMERRCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[7] = (MIRXCOMPLETIONRAMERRCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[8] = (MIRXCOMPLETIONRAMERRCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[9] = (MIRXCOMPLETIONRAMERRCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[0] = (MIRXCOMPLETIONRAMERRUNCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[10] = (MIRXCOMPLETIONRAMERRUNCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[11] = (MIRXCOMPLETIONRAMERRUNCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[1] = (MIRXCOMPLETIONRAMERRUNCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[2] = (MIRXCOMPLETIONRAMERRUNCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[3] = (MIRXCOMPLETIONRAMERRUNCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[4] = (MIRXCOMPLETIONRAMERRUNCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[5] = (MIRXCOMPLETIONRAMERRUNCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[6] = (MIRXCOMPLETIONRAMERRUNCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[7] = (MIRXCOMPLETIONRAMERRUNCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[8] = (MIRXCOMPLETIONRAMERRUNCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[9] = (MIRXCOMPLETIONRAMERRUNCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[0] = (MIRXCOMPLETIONRAMREADDATA0[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[100] = (MIRXCOMPLETIONRAMREADDATA0[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[101] = (MIRXCOMPLETIONRAMREADDATA0[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[102] = (MIRXCOMPLETIONRAMREADDATA0[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[103] = (MIRXCOMPLETIONRAMREADDATA0[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[104] = (MIRXCOMPLETIONRAMREADDATA0[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[105] = (MIRXCOMPLETIONRAMREADDATA0[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[106] = (MIRXCOMPLETIONRAMREADDATA0[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[107] = (MIRXCOMPLETIONRAMREADDATA0[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[108] = (MIRXCOMPLETIONRAMREADDATA0[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[109] = (MIRXCOMPLETIONRAMREADDATA0[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[10] = (MIRXCOMPLETIONRAMREADDATA0[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[110] = (MIRXCOMPLETIONRAMREADDATA0[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[111] = (MIRXCOMPLETIONRAMREADDATA0[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[112] = (MIRXCOMPLETIONRAMREADDATA0[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[113] = (MIRXCOMPLETIONRAMREADDATA0[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[114] = (MIRXCOMPLETIONRAMREADDATA0[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[115] = (MIRXCOMPLETIONRAMREADDATA0[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[116] = (MIRXCOMPLETIONRAMREADDATA0[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[117] = (MIRXCOMPLETIONRAMREADDATA0[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[118] = (MIRXCOMPLETIONRAMREADDATA0[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[119] = (MIRXCOMPLETIONRAMREADDATA0[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[11] = (MIRXCOMPLETIONRAMREADDATA0[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[120] = (MIRXCOMPLETIONRAMREADDATA0[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[121] = (MIRXCOMPLETIONRAMREADDATA0[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[122] = (MIRXCOMPLETIONRAMREADDATA0[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[123] = (MIRXCOMPLETIONRAMREADDATA0[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[124] = (MIRXCOMPLETIONRAMREADDATA0[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[125] = (MIRXCOMPLETIONRAMREADDATA0[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[126] = (MIRXCOMPLETIONRAMREADDATA0[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[127] = (MIRXCOMPLETIONRAMREADDATA0[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[128] = (MIRXCOMPLETIONRAMREADDATA0[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[129] = (MIRXCOMPLETIONRAMREADDATA0[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[12] = (MIRXCOMPLETIONRAMREADDATA0[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[130] = (MIRXCOMPLETIONRAMREADDATA0[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[131] = (MIRXCOMPLETIONRAMREADDATA0[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[132] = (MIRXCOMPLETIONRAMREADDATA0[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[133] = (MIRXCOMPLETIONRAMREADDATA0[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[134] = (MIRXCOMPLETIONRAMREADDATA0[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[135] = (MIRXCOMPLETIONRAMREADDATA0[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[136] = (MIRXCOMPLETIONRAMREADDATA0[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[137] = (MIRXCOMPLETIONRAMREADDATA0[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[138] = (MIRXCOMPLETIONRAMREADDATA0[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[139] = (MIRXCOMPLETIONRAMREADDATA0[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[13] = (MIRXCOMPLETIONRAMREADDATA0[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[140] = (MIRXCOMPLETIONRAMREADDATA0[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[141] = (MIRXCOMPLETIONRAMREADDATA0[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[142] = (MIRXCOMPLETIONRAMREADDATA0[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[143] = (MIRXCOMPLETIONRAMREADDATA0[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[14] = (MIRXCOMPLETIONRAMREADDATA0[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[15] = (MIRXCOMPLETIONRAMREADDATA0[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[16] = (MIRXCOMPLETIONRAMREADDATA0[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[17] = (MIRXCOMPLETIONRAMREADDATA0[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[18] = (MIRXCOMPLETIONRAMREADDATA0[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[19] = (MIRXCOMPLETIONRAMREADDATA0[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[1] = (MIRXCOMPLETIONRAMREADDATA0[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[20] = (MIRXCOMPLETIONRAMREADDATA0[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[21] = (MIRXCOMPLETIONRAMREADDATA0[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[22] = (MIRXCOMPLETIONRAMREADDATA0[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[23] = (MIRXCOMPLETIONRAMREADDATA0[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[24] = (MIRXCOMPLETIONRAMREADDATA0[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[25] = (MIRXCOMPLETIONRAMREADDATA0[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[26] = (MIRXCOMPLETIONRAMREADDATA0[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[27] = (MIRXCOMPLETIONRAMREADDATA0[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[28] = (MIRXCOMPLETIONRAMREADDATA0[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[29] = (MIRXCOMPLETIONRAMREADDATA0[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[2] = (MIRXCOMPLETIONRAMREADDATA0[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[30] = (MIRXCOMPLETIONRAMREADDATA0[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[31] = (MIRXCOMPLETIONRAMREADDATA0[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[32] = (MIRXCOMPLETIONRAMREADDATA0[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[33] = (MIRXCOMPLETIONRAMREADDATA0[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[34] = (MIRXCOMPLETIONRAMREADDATA0[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[35] = (MIRXCOMPLETIONRAMREADDATA0[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[36] = (MIRXCOMPLETIONRAMREADDATA0[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[37] = (MIRXCOMPLETIONRAMREADDATA0[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[38] = (MIRXCOMPLETIONRAMREADDATA0[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[39] = (MIRXCOMPLETIONRAMREADDATA0[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[3] = (MIRXCOMPLETIONRAMREADDATA0[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[40] = (MIRXCOMPLETIONRAMREADDATA0[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[41] = (MIRXCOMPLETIONRAMREADDATA0[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[42] = (MIRXCOMPLETIONRAMREADDATA0[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[43] = (MIRXCOMPLETIONRAMREADDATA0[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[44] = (MIRXCOMPLETIONRAMREADDATA0[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[45] = (MIRXCOMPLETIONRAMREADDATA0[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[46] = (MIRXCOMPLETIONRAMREADDATA0[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[47] = (MIRXCOMPLETIONRAMREADDATA0[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[48] = (MIRXCOMPLETIONRAMREADDATA0[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[49] = (MIRXCOMPLETIONRAMREADDATA0[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[4] = (MIRXCOMPLETIONRAMREADDATA0[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[50] = (MIRXCOMPLETIONRAMREADDATA0[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[51] = (MIRXCOMPLETIONRAMREADDATA0[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[52] = (MIRXCOMPLETIONRAMREADDATA0[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[53] = (MIRXCOMPLETIONRAMREADDATA0[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[54] = (MIRXCOMPLETIONRAMREADDATA0[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[55] = (MIRXCOMPLETIONRAMREADDATA0[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[56] = (MIRXCOMPLETIONRAMREADDATA0[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[57] = (MIRXCOMPLETIONRAMREADDATA0[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[58] = (MIRXCOMPLETIONRAMREADDATA0[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[59] = (MIRXCOMPLETIONRAMREADDATA0[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[5] = (MIRXCOMPLETIONRAMREADDATA0[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[60] = (MIRXCOMPLETIONRAMREADDATA0[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[61] = (MIRXCOMPLETIONRAMREADDATA0[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[62] = (MIRXCOMPLETIONRAMREADDATA0[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[63] = (MIRXCOMPLETIONRAMREADDATA0[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[64] = (MIRXCOMPLETIONRAMREADDATA0[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[65] = (MIRXCOMPLETIONRAMREADDATA0[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[66] = (MIRXCOMPLETIONRAMREADDATA0[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[67] = (MIRXCOMPLETIONRAMREADDATA0[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[68] = (MIRXCOMPLETIONRAMREADDATA0[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[69] = (MIRXCOMPLETIONRAMREADDATA0[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[6] = (MIRXCOMPLETIONRAMREADDATA0[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[70] = (MIRXCOMPLETIONRAMREADDATA0[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[71] = (MIRXCOMPLETIONRAMREADDATA0[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[72] = (MIRXCOMPLETIONRAMREADDATA0[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[73] = (MIRXCOMPLETIONRAMREADDATA0[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[74] = (MIRXCOMPLETIONRAMREADDATA0[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[75] = (MIRXCOMPLETIONRAMREADDATA0[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[76] = (MIRXCOMPLETIONRAMREADDATA0[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[77] = (MIRXCOMPLETIONRAMREADDATA0[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[78] = (MIRXCOMPLETIONRAMREADDATA0[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[79] = (MIRXCOMPLETIONRAMREADDATA0[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[7] = (MIRXCOMPLETIONRAMREADDATA0[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[80] = (MIRXCOMPLETIONRAMREADDATA0[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[81] = (MIRXCOMPLETIONRAMREADDATA0[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[82] = (MIRXCOMPLETIONRAMREADDATA0[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[83] = (MIRXCOMPLETIONRAMREADDATA0[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[84] = (MIRXCOMPLETIONRAMREADDATA0[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[85] = (MIRXCOMPLETIONRAMREADDATA0[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[86] = (MIRXCOMPLETIONRAMREADDATA0[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[87] = (MIRXCOMPLETIONRAMREADDATA0[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[88] = (MIRXCOMPLETIONRAMREADDATA0[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[89] = (MIRXCOMPLETIONRAMREADDATA0[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[8] = (MIRXCOMPLETIONRAMREADDATA0[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[90] = (MIRXCOMPLETIONRAMREADDATA0[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[91] = (MIRXCOMPLETIONRAMREADDATA0[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[92] = (MIRXCOMPLETIONRAMREADDATA0[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[93] = (MIRXCOMPLETIONRAMREADDATA0[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[94] = (MIRXCOMPLETIONRAMREADDATA0[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[95] = (MIRXCOMPLETIONRAMREADDATA0[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[96] = (MIRXCOMPLETIONRAMREADDATA0[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[97] = (MIRXCOMPLETIONRAMREADDATA0[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[98] = (MIRXCOMPLETIONRAMREADDATA0[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[99] = (MIRXCOMPLETIONRAMREADDATA0[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[9] = (MIRXCOMPLETIONRAMREADDATA0[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[0] = (MIRXCOMPLETIONRAMREADDATA1[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[100] = (MIRXCOMPLETIONRAMREADDATA1[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[101] = (MIRXCOMPLETIONRAMREADDATA1[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[102] = (MIRXCOMPLETIONRAMREADDATA1[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[103] = (MIRXCOMPLETIONRAMREADDATA1[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[104] = (MIRXCOMPLETIONRAMREADDATA1[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[105] = (MIRXCOMPLETIONRAMREADDATA1[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[106] = (MIRXCOMPLETIONRAMREADDATA1[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[107] = (MIRXCOMPLETIONRAMREADDATA1[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[108] = (MIRXCOMPLETIONRAMREADDATA1[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[109] = (MIRXCOMPLETIONRAMREADDATA1[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[10] = (MIRXCOMPLETIONRAMREADDATA1[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[110] = (MIRXCOMPLETIONRAMREADDATA1[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[111] = (MIRXCOMPLETIONRAMREADDATA1[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[112] = (MIRXCOMPLETIONRAMREADDATA1[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[113] = (MIRXCOMPLETIONRAMREADDATA1[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[114] = (MIRXCOMPLETIONRAMREADDATA1[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[115] = (MIRXCOMPLETIONRAMREADDATA1[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[116] = (MIRXCOMPLETIONRAMREADDATA1[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[117] = (MIRXCOMPLETIONRAMREADDATA1[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[118] = (MIRXCOMPLETIONRAMREADDATA1[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[119] = (MIRXCOMPLETIONRAMREADDATA1[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[11] = (MIRXCOMPLETIONRAMREADDATA1[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[120] = (MIRXCOMPLETIONRAMREADDATA1[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[121] = (MIRXCOMPLETIONRAMREADDATA1[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[122] = (MIRXCOMPLETIONRAMREADDATA1[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[123] = (MIRXCOMPLETIONRAMREADDATA1[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[124] = (MIRXCOMPLETIONRAMREADDATA1[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[125] = (MIRXCOMPLETIONRAMREADDATA1[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[126] = (MIRXCOMPLETIONRAMREADDATA1[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[127] = (MIRXCOMPLETIONRAMREADDATA1[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[128] = (MIRXCOMPLETIONRAMREADDATA1[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[129] = (MIRXCOMPLETIONRAMREADDATA1[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[12] = (MIRXCOMPLETIONRAMREADDATA1[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[130] = (MIRXCOMPLETIONRAMREADDATA1[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[131] = (MIRXCOMPLETIONRAMREADDATA1[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[132] = (MIRXCOMPLETIONRAMREADDATA1[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[133] = (MIRXCOMPLETIONRAMREADDATA1[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[134] = (MIRXCOMPLETIONRAMREADDATA1[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[135] = (MIRXCOMPLETIONRAMREADDATA1[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[136] = (MIRXCOMPLETIONRAMREADDATA1[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[137] = (MIRXCOMPLETIONRAMREADDATA1[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[138] = (MIRXCOMPLETIONRAMREADDATA1[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[139] = (MIRXCOMPLETIONRAMREADDATA1[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[13] = (MIRXCOMPLETIONRAMREADDATA1[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[140] = (MIRXCOMPLETIONRAMREADDATA1[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[141] = (MIRXCOMPLETIONRAMREADDATA1[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[142] = (MIRXCOMPLETIONRAMREADDATA1[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[143] = (MIRXCOMPLETIONRAMREADDATA1[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[14] = (MIRXCOMPLETIONRAMREADDATA1[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[15] = (MIRXCOMPLETIONRAMREADDATA1[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[16] = (MIRXCOMPLETIONRAMREADDATA1[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[17] = (MIRXCOMPLETIONRAMREADDATA1[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[18] = (MIRXCOMPLETIONRAMREADDATA1[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[19] = (MIRXCOMPLETIONRAMREADDATA1[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[1] = (MIRXCOMPLETIONRAMREADDATA1[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[20] = (MIRXCOMPLETIONRAMREADDATA1[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[21] = (MIRXCOMPLETIONRAMREADDATA1[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[22] = (MIRXCOMPLETIONRAMREADDATA1[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[23] = (MIRXCOMPLETIONRAMREADDATA1[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[24] = (MIRXCOMPLETIONRAMREADDATA1[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[25] = (MIRXCOMPLETIONRAMREADDATA1[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[26] = (MIRXCOMPLETIONRAMREADDATA1[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[27] = (MIRXCOMPLETIONRAMREADDATA1[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[28] = (MIRXCOMPLETIONRAMREADDATA1[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[29] = (MIRXCOMPLETIONRAMREADDATA1[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[2] = (MIRXCOMPLETIONRAMREADDATA1[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[30] = (MIRXCOMPLETIONRAMREADDATA1[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[31] = (MIRXCOMPLETIONRAMREADDATA1[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[32] = (MIRXCOMPLETIONRAMREADDATA1[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[33] = (MIRXCOMPLETIONRAMREADDATA1[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[34] = (MIRXCOMPLETIONRAMREADDATA1[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[35] = (MIRXCOMPLETIONRAMREADDATA1[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[36] = (MIRXCOMPLETIONRAMREADDATA1[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[37] = (MIRXCOMPLETIONRAMREADDATA1[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[38] = (MIRXCOMPLETIONRAMREADDATA1[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[39] = (MIRXCOMPLETIONRAMREADDATA1[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[3] = (MIRXCOMPLETIONRAMREADDATA1[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[40] = (MIRXCOMPLETIONRAMREADDATA1[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[41] = (MIRXCOMPLETIONRAMREADDATA1[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[42] = (MIRXCOMPLETIONRAMREADDATA1[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[43] = (MIRXCOMPLETIONRAMREADDATA1[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[44] = (MIRXCOMPLETIONRAMREADDATA1[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[45] = (MIRXCOMPLETIONRAMREADDATA1[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[46] = (MIRXCOMPLETIONRAMREADDATA1[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[47] = (MIRXCOMPLETIONRAMREADDATA1[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[48] = (MIRXCOMPLETIONRAMREADDATA1[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[49] = (MIRXCOMPLETIONRAMREADDATA1[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[4] = (MIRXCOMPLETIONRAMREADDATA1[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[50] = (MIRXCOMPLETIONRAMREADDATA1[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[51] = (MIRXCOMPLETIONRAMREADDATA1[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[52] = (MIRXCOMPLETIONRAMREADDATA1[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[53] = (MIRXCOMPLETIONRAMREADDATA1[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[54] = (MIRXCOMPLETIONRAMREADDATA1[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[55] = (MIRXCOMPLETIONRAMREADDATA1[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[56] = (MIRXCOMPLETIONRAMREADDATA1[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[57] = (MIRXCOMPLETIONRAMREADDATA1[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[58] = (MIRXCOMPLETIONRAMREADDATA1[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[59] = (MIRXCOMPLETIONRAMREADDATA1[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[5] = (MIRXCOMPLETIONRAMREADDATA1[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[60] = (MIRXCOMPLETIONRAMREADDATA1[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[61] = (MIRXCOMPLETIONRAMREADDATA1[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[62] = (MIRXCOMPLETIONRAMREADDATA1[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[63] = (MIRXCOMPLETIONRAMREADDATA1[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[64] = (MIRXCOMPLETIONRAMREADDATA1[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[65] = (MIRXCOMPLETIONRAMREADDATA1[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[66] = (MIRXCOMPLETIONRAMREADDATA1[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[67] = (MIRXCOMPLETIONRAMREADDATA1[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[68] = (MIRXCOMPLETIONRAMREADDATA1[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[69] = (MIRXCOMPLETIONRAMREADDATA1[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[6] = (MIRXCOMPLETIONRAMREADDATA1[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[70] = (MIRXCOMPLETIONRAMREADDATA1[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[71] = (MIRXCOMPLETIONRAMREADDATA1[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[72] = (MIRXCOMPLETIONRAMREADDATA1[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[73] = (MIRXCOMPLETIONRAMREADDATA1[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[74] = (MIRXCOMPLETIONRAMREADDATA1[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[75] = (MIRXCOMPLETIONRAMREADDATA1[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[76] = (MIRXCOMPLETIONRAMREADDATA1[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[77] = (MIRXCOMPLETIONRAMREADDATA1[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[78] = (MIRXCOMPLETIONRAMREADDATA1[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[79] = (MIRXCOMPLETIONRAMREADDATA1[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[7] = (MIRXCOMPLETIONRAMREADDATA1[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[80] = (MIRXCOMPLETIONRAMREADDATA1[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[81] = (MIRXCOMPLETIONRAMREADDATA1[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[82] = (MIRXCOMPLETIONRAMREADDATA1[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[83] = (MIRXCOMPLETIONRAMREADDATA1[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[84] = (MIRXCOMPLETIONRAMREADDATA1[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[85] = (MIRXCOMPLETIONRAMREADDATA1[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[86] = (MIRXCOMPLETIONRAMREADDATA1[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[87] = (MIRXCOMPLETIONRAMREADDATA1[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[88] = (MIRXCOMPLETIONRAMREADDATA1[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[89] = (MIRXCOMPLETIONRAMREADDATA1[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[8] = (MIRXCOMPLETIONRAMREADDATA1[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[90] = (MIRXCOMPLETIONRAMREADDATA1[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[91] = (MIRXCOMPLETIONRAMREADDATA1[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[92] = (MIRXCOMPLETIONRAMREADDATA1[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[93] = (MIRXCOMPLETIONRAMREADDATA1[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[94] = (MIRXCOMPLETIONRAMREADDATA1[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[95] = (MIRXCOMPLETIONRAMREADDATA1[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[96] = (MIRXCOMPLETIONRAMREADDATA1[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[97] = (MIRXCOMPLETIONRAMREADDATA1[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[98] = (MIRXCOMPLETIONRAMREADDATA1[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[99] = (MIRXCOMPLETIONRAMREADDATA1[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[9] = (MIRXCOMPLETIONRAMREADDATA1[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRUNCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRUNCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRUNCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRUNCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRUNCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRUNCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA0[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA0[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA0[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA0[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA0[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA0[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA0[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA0[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA0[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA0[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA0[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA0[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA0[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA0[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA0[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA0[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA0[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA0[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA0[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA0[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA0[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA0[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA0[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA0[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA0[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA0[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA0[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA0[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA0[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA0[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA0[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA0[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA0[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA0[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA0[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA0[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA0[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA0[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA0[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA0[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA0[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA0[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA0[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA0[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA0[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA0[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA0[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA0[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA0[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA0[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA0[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA0[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA0[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA0[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA0[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA0[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA0[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA0[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA0[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA0[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA0[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA0[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA0[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA0[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA0[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA0[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA0[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA0[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA0[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA0[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA0[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA0[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA0[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA0[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA0[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA0[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA0[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA0[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA0[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA0[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA0[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA0[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA0[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA0[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA0[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA0[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA0[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA0[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA0[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA0[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA0[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA0[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA0[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA0[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA0[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA0[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA0[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA0[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA0[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA0[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA0[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA0[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA0[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA0[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA0[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA0[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA0[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA0[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA0[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA0[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA0[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA0[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA0[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA0[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA0[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA0[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA0[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA0[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA0[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA0[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA0[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA0[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA0[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA0[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA0[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA0[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA0[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA0[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA0[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA0[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA0[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA0[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA0[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA0[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA0[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA0[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA0[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA0[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA0[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA0[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA0[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA0[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA0[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA0[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA1[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA1[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA1[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA1[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA1[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA1[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA1[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA1[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA1[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA1[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA1[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA1[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA1[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA1[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA1[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA1[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA1[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA1[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA1[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA1[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA1[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA1[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA1[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA1[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA1[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA1[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA1[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA1[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA1[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA1[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA1[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA1[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA1[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA1[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA1[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA1[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA1[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA1[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA1[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA1[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA1[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA1[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA1[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA1[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA1[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA1[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA1[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA1[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA1[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA1[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA1[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA1[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA1[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA1[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA1[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA1[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA1[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA1[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA1[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA1[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA1[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA1[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA1[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA1[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA1[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA1[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA1[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA1[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA1[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA1[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA1[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA1[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA1[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA1[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA1[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA1[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA1[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA1[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA1[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA1[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA1[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA1[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA1[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA1[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA1[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA1[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA1[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA1[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA1[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA1[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA1[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA1[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA1[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA1[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA1[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA1[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA1[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA1[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA1[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA1[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA1[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA1[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA1[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA1[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA1[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA1[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA1[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA1[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA1[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA1[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA1[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA1[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA1[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA1[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA1[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA1[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA1[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA1[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA1[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA1[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA1[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA1[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA1[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA1[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA1[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA1[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA1[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA1[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA1[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA1[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA1[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA1[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA1[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA1[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA1[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA1[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA1[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA1[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA1[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA1[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA1[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA1[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA1[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA1[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[9]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[0] = (PCIECOMPLDELIVEREDTAG0[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[1] = (PCIECOMPLDELIVEREDTAG0[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[2] = (PCIECOMPLDELIVEREDTAG0[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[3] = (PCIECOMPLDELIVEREDTAG0[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[4] = (PCIECOMPLDELIVEREDTAG0[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[5] = (PCIECOMPLDELIVEREDTAG0[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[6] = (PCIECOMPLDELIVEREDTAG0[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[7] = (PCIECOMPLDELIVEREDTAG0[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[7]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[0] = (PCIECOMPLDELIVEREDTAG1[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[1] = (PCIECOMPLDELIVEREDTAG1[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[2] = (PCIECOMPLDELIVEREDTAG1[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[3] = (PCIECOMPLDELIVEREDTAG1[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[4] = (PCIECOMPLDELIVEREDTAG1[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[5] = (PCIECOMPLDELIVEREDTAG1[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[6] = (PCIECOMPLDELIVEREDTAG1[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[7] = (PCIECOMPLDELIVEREDTAG1[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[7]; // rv 0 + assign PCIECOMPLDELIVERED_in[0] = (PCIECOMPLDELIVERED[0] !== 1'bz) && PCIECOMPLDELIVERED[0]; // rv 0 + assign PCIECOMPLDELIVERED_in[1] = (PCIECOMPLDELIVERED[1] !== 1'bz) && PCIECOMPLDELIVERED[1]; // rv 0 + assign PCIECQNPREQ_in[0] = (PCIECQNPREQ[0] === 1'bz) || PCIECQNPREQ[0]; // rv 1 + assign PCIECQNPREQ_in[1] = (PCIECQNPREQ[1] === 1'bz) || PCIECQNPREQ[1]; // rv 1 + assign PCIECQNPUSERCREDITRCVD_in = (PCIECQNPUSERCREDITRCVD !== 1'bz) && PCIECQNPUSERCREDITRCVD; // rv 0 + assign PCIECQPIPELINEEMPTY_in = (PCIECQPIPELINEEMPTY !== 1'bz) && PCIECQPIPELINEEMPTY; // rv 0 + assign PCIEPOSTEDREQDELIVERED_in = (PCIEPOSTEDREQDELIVERED !== 1'bz) && PCIEPOSTEDREQDELIVERED; // rv 0 + assign PIPECLK_in = (PIPECLK !== 1'bz) && PIPECLK; // rv 0 + assign PIPEEQFS_in[0] = (PIPEEQFS[0] !== 1'bz) && PIPEEQFS[0]; // rv 0 + assign PIPEEQFS_in[1] = (PIPEEQFS[1] !== 1'bz) && PIPEEQFS[1]; // rv 0 + assign PIPEEQFS_in[2] = (PIPEEQFS[2] !== 1'bz) && PIPEEQFS[2]; // rv 0 + assign PIPEEQFS_in[3] = (PIPEEQFS[3] !== 1'bz) && PIPEEQFS[3]; // rv 0 + assign PIPEEQFS_in[4] = (PIPEEQFS[4] !== 1'bz) && PIPEEQFS[4]; // rv 0 + assign PIPEEQFS_in[5] = (PIPEEQFS[5] !== 1'bz) && PIPEEQFS[5]; // rv 0 + assign PIPEEQLF_in[0] = (PIPEEQLF[0] !== 1'bz) && PIPEEQLF[0]; // rv 0 + assign PIPEEQLF_in[1] = (PIPEEQLF[1] !== 1'bz) && PIPEEQLF[1]; // rv 0 + assign PIPEEQLF_in[2] = (PIPEEQLF[2] !== 1'bz) && PIPEEQLF[2]; // rv 0 + assign PIPEEQLF_in[3] = (PIPEEQLF[3] !== 1'bz) && PIPEEQLF[3]; // rv 0 + assign PIPEEQLF_in[4] = (PIPEEQLF[4] !== 1'bz) && PIPEEQLF[4]; // rv 0 + assign PIPEEQLF_in[5] = (PIPEEQLF[5] !== 1'bz) && PIPEEQLF[5]; // rv 0 + assign PIPERX00CHARISK_in[0] = (PIPERX00CHARISK[0] === 1'bz) || PIPERX00CHARISK[0]; // rv 1 + assign PIPERX00CHARISK_in[1] = (PIPERX00CHARISK[1] === 1'bz) || PIPERX00CHARISK[1]; // rv 1 + assign PIPERX00DATAVALID_in = (PIPERX00DATAVALID !== 1'bz) && PIPERX00DATAVALID; // rv 0 + assign PIPERX00DATA_in[0] = (PIPERX00DATA[0] !== 1'bz) && PIPERX00DATA[0]; // rv 0 + assign PIPERX00DATA_in[10] = (PIPERX00DATA[10] !== 1'bz) && PIPERX00DATA[10]; // rv 0 + assign PIPERX00DATA_in[11] = (PIPERX00DATA[11] !== 1'bz) && PIPERX00DATA[11]; // rv 0 + assign PIPERX00DATA_in[12] = (PIPERX00DATA[12] !== 1'bz) && PIPERX00DATA[12]; // rv 0 + assign PIPERX00DATA_in[13] = (PIPERX00DATA[13] !== 1'bz) && PIPERX00DATA[13]; // rv 0 + assign PIPERX00DATA_in[14] = (PIPERX00DATA[14] !== 1'bz) && PIPERX00DATA[14]; // rv 0 + assign PIPERX00DATA_in[15] = (PIPERX00DATA[15] !== 1'bz) && PIPERX00DATA[15]; // rv 0 + assign PIPERX00DATA_in[16] = (PIPERX00DATA[16] !== 1'bz) && PIPERX00DATA[16]; // rv 0 + assign PIPERX00DATA_in[17] = (PIPERX00DATA[17] !== 1'bz) && PIPERX00DATA[17]; // rv 0 + assign PIPERX00DATA_in[18] = (PIPERX00DATA[18] !== 1'bz) && PIPERX00DATA[18]; // rv 0 + assign PIPERX00DATA_in[19] = (PIPERX00DATA[19] !== 1'bz) && PIPERX00DATA[19]; // rv 0 + assign PIPERX00DATA_in[1] = (PIPERX00DATA[1] !== 1'bz) && PIPERX00DATA[1]; // rv 0 + assign PIPERX00DATA_in[20] = (PIPERX00DATA[20] !== 1'bz) && PIPERX00DATA[20]; // rv 0 + assign PIPERX00DATA_in[21] = (PIPERX00DATA[21] !== 1'bz) && PIPERX00DATA[21]; // rv 0 + assign PIPERX00DATA_in[22] = (PIPERX00DATA[22] !== 1'bz) && PIPERX00DATA[22]; // rv 0 + assign PIPERX00DATA_in[23] = (PIPERX00DATA[23] !== 1'bz) && PIPERX00DATA[23]; // rv 0 + assign PIPERX00DATA_in[24] = (PIPERX00DATA[24] !== 1'bz) && PIPERX00DATA[24]; // rv 0 + assign PIPERX00DATA_in[25] = (PIPERX00DATA[25] !== 1'bz) && PIPERX00DATA[25]; // rv 0 + assign PIPERX00DATA_in[26] = (PIPERX00DATA[26] !== 1'bz) && PIPERX00DATA[26]; // rv 0 + assign PIPERX00DATA_in[27] = (PIPERX00DATA[27] !== 1'bz) && PIPERX00DATA[27]; // rv 0 + assign PIPERX00DATA_in[28] = (PIPERX00DATA[28] !== 1'bz) && PIPERX00DATA[28]; // rv 0 + assign PIPERX00DATA_in[29] = (PIPERX00DATA[29] !== 1'bz) && PIPERX00DATA[29]; // rv 0 + assign PIPERX00DATA_in[2] = (PIPERX00DATA[2] !== 1'bz) && PIPERX00DATA[2]; // rv 0 + assign PIPERX00DATA_in[30] = (PIPERX00DATA[30] !== 1'bz) && PIPERX00DATA[30]; // rv 0 + assign PIPERX00DATA_in[31] = (PIPERX00DATA[31] !== 1'bz) && PIPERX00DATA[31]; // rv 0 + assign PIPERX00DATA_in[3] = (PIPERX00DATA[3] !== 1'bz) && PIPERX00DATA[3]; // rv 0 + assign PIPERX00DATA_in[4] = (PIPERX00DATA[4] !== 1'bz) && PIPERX00DATA[4]; // rv 0 + assign PIPERX00DATA_in[5] = (PIPERX00DATA[5] !== 1'bz) && PIPERX00DATA[5]; // rv 0 + assign PIPERX00DATA_in[6] = (PIPERX00DATA[6] !== 1'bz) && PIPERX00DATA[6]; // rv 0 + assign PIPERX00DATA_in[7] = (PIPERX00DATA[7] !== 1'bz) && PIPERX00DATA[7]; // rv 0 + assign PIPERX00DATA_in[8] = (PIPERX00DATA[8] !== 1'bz) && PIPERX00DATA[8]; // rv 0 + assign PIPERX00DATA_in[9] = (PIPERX00DATA[9] !== 1'bz) && PIPERX00DATA[9]; // rv 0 + assign PIPERX00ELECIDLE_in = (PIPERX00ELECIDLE === 1'bz) || PIPERX00ELECIDLE; // rv 1 + assign PIPERX00EQDONE_in = (PIPERX00EQDONE !== 1'bz) && PIPERX00EQDONE; // rv 0 + assign PIPERX00EQLPADAPTDONE_in = (PIPERX00EQLPADAPTDONE !== 1'bz) && PIPERX00EQLPADAPTDONE; // rv 0 + assign PIPERX00EQLPLFFSSEL_in = (PIPERX00EQLPLFFSSEL !== 1'bz) && PIPERX00EQLPLFFSSEL; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX00EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX00EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX00EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX00EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX00EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX00EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX00EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX00EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX00EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX00EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX00EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX00EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX00EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX00EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX00EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX00EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX00EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX00EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX00PHYSTATUS_in = (PIPERX00PHYSTATUS === 1'bz) || PIPERX00PHYSTATUS; // rv 1 + assign PIPERX00STARTBLOCK_in[0] = (PIPERX00STARTBLOCK[0] !== 1'bz) && PIPERX00STARTBLOCK[0]; // rv 0 + assign PIPERX00STARTBLOCK_in[1] = (PIPERX00STARTBLOCK[1] !== 1'bz) && PIPERX00STARTBLOCK[1]; // rv 0 + assign PIPERX00STATUS_in[0] = (PIPERX00STATUS[0] !== 1'bz) && PIPERX00STATUS[0]; // rv 0 + assign PIPERX00STATUS_in[1] = (PIPERX00STATUS[1] !== 1'bz) && PIPERX00STATUS[1]; // rv 0 + assign PIPERX00STATUS_in[2] = (PIPERX00STATUS[2] !== 1'bz) && PIPERX00STATUS[2]; // rv 0 + assign PIPERX00SYNCHEADER_in[0] = (PIPERX00SYNCHEADER[0] !== 1'bz) && PIPERX00SYNCHEADER[0]; // rv 0 + assign PIPERX00SYNCHEADER_in[1] = (PIPERX00SYNCHEADER[1] !== 1'bz) && PIPERX00SYNCHEADER[1]; // rv 0 + assign PIPERX00VALID_in = (PIPERX00VALID !== 1'bz) && PIPERX00VALID; // rv 0 + assign PIPERX01CHARISK_in[0] = (PIPERX01CHARISK[0] === 1'bz) || PIPERX01CHARISK[0]; // rv 1 + assign PIPERX01CHARISK_in[1] = (PIPERX01CHARISK[1] === 1'bz) || PIPERX01CHARISK[1]; // rv 1 + assign PIPERX01DATAVALID_in = (PIPERX01DATAVALID !== 1'bz) && PIPERX01DATAVALID; // rv 0 + assign PIPERX01DATA_in[0] = (PIPERX01DATA[0] !== 1'bz) && PIPERX01DATA[0]; // rv 0 + assign PIPERX01DATA_in[10] = (PIPERX01DATA[10] !== 1'bz) && PIPERX01DATA[10]; // rv 0 + assign PIPERX01DATA_in[11] = (PIPERX01DATA[11] !== 1'bz) && PIPERX01DATA[11]; // rv 0 + assign PIPERX01DATA_in[12] = (PIPERX01DATA[12] !== 1'bz) && PIPERX01DATA[12]; // rv 0 + assign PIPERX01DATA_in[13] = (PIPERX01DATA[13] !== 1'bz) && PIPERX01DATA[13]; // rv 0 + assign PIPERX01DATA_in[14] = (PIPERX01DATA[14] !== 1'bz) && PIPERX01DATA[14]; // rv 0 + assign PIPERX01DATA_in[15] = (PIPERX01DATA[15] !== 1'bz) && PIPERX01DATA[15]; // rv 0 + assign PIPERX01DATA_in[16] = (PIPERX01DATA[16] !== 1'bz) && PIPERX01DATA[16]; // rv 0 + assign PIPERX01DATA_in[17] = (PIPERX01DATA[17] !== 1'bz) && PIPERX01DATA[17]; // rv 0 + assign PIPERX01DATA_in[18] = (PIPERX01DATA[18] !== 1'bz) && PIPERX01DATA[18]; // rv 0 + assign PIPERX01DATA_in[19] = (PIPERX01DATA[19] !== 1'bz) && PIPERX01DATA[19]; // rv 0 + assign PIPERX01DATA_in[1] = (PIPERX01DATA[1] !== 1'bz) && PIPERX01DATA[1]; // rv 0 + assign PIPERX01DATA_in[20] = (PIPERX01DATA[20] !== 1'bz) && PIPERX01DATA[20]; // rv 0 + assign PIPERX01DATA_in[21] = (PIPERX01DATA[21] !== 1'bz) && PIPERX01DATA[21]; // rv 0 + assign PIPERX01DATA_in[22] = (PIPERX01DATA[22] !== 1'bz) && PIPERX01DATA[22]; // rv 0 + assign PIPERX01DATA_in[23] = (PIPERX01DATA[23] !== 1'bz) && PIPERX01DATA[23]; // rv 0 + assign PIPERX01DATA_in[24] = (PIPERX01DATA[24] !== 1'bz) && PIPERX01DATA[24]; // rv 0 + assign PIPERX01DATA_in[25] = (PIPERX01DATA[25] !== 1'bz) && PIPERX01DATA[25]; // rv 0 + assign PIPERX01DATA_in[26] = (PIPERX01DATA[26] !== 1'bz) && PIPERX01DATA[26]; // rv 0 + assign PIPERX01DATA_in[27] = (PIPERX01DATA[27] !== 1'bz) && PIPERX01DATA[27]; // rv 0 + assign PIPERX01DATA_in[28] = (PIPERX01DATA[28] !== 1'bz) && PIPERX01DATA[28]; // rv 0 + assign PIPERX01DATA_in[29] = (PIPERX01DATA[29] !== 1'bz) && PIPERX01DATA[29]; // rv 0 + assign PIPERX01DATA_in[2] = (PIPERX01DATA[2] !== 1'bz) && PIPERX01DATA[2]; // rv 0 + assign PIPERX01DATA_in[30] = (PIPERX01DATA[30] !== 1'bz) && PIPERX01DATA[30]; // rv 0 + assign PIPERX01DATA_in[31] = (PIPERX01DATA[31] !== 1'bz) && PIPERX01DATA[31]; // rv 0 + assign PIPERX01DATA_in[3] = (PIPERX01DATA[3] !== 1'bz) && PIPERX01DATA[3]; // rv 0 + assign PIPERX01DATA_in[4] = (PIPERX01DATA[4] !== 1'bz) && PIPERX01DATA[4]; // rv 0 + assign PIPERX01DATA_in[5] = (PIPERX01DATA[5] !== 1'bz) && PIPERX01DATA[5]; // rv 0 + assign PIPERX01DATA_in[6] = (PIPERX01DATA[6] !== 1'bz) && PIPERX01DATA[6]; // rv 0 + assign PIPERX01DATA_in[7] = (PIPERX01DATA[7] !== 1'bz) && PIPERX01DATA[7]; // rv 0 + assign PIPERX01DATA_in[8] = (PIPERX01DATA[8] !== 1'bz) && PIPERX01DATA[8]; // rv 0 + assign PIPERX01DATA_in[9] = (PIPERX01DATA[9] !== 1'bz) && PIPERX01DATA[9]; // rv 0 + assign PIPERX01ELECIDLE_in = (PIPERX01ELECIDLE === 1'bz) || PIPERX01ELECIDLE; // rv 1 + assign PIPERX01EQDONE_in = (PIPERX01EQDONE !== 1'bz) && PIPERX01EQDONE; // rv 0 + assign PIPERX01EQLPADAPTDONE_in = (PIPERX01EQLPADAPTDONE !== 1'bz) && PIPERX01EQLPADAPTDONE; // rv 0 + assign PIPERX01EQLPLFFSSEL_in = (PIPERX01EQLPLFFSSEL !== 1'bz) && PIPERX01EQLPLFFSSEL; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX01EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX01EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX01EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX01EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX01EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX01EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX01EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX01EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX01EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX01EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX01EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX01EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX01EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX01EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX01EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX01EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX01EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX01EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX01PHYSTATUS_in = (PIPERX01PHYSTATUS === 1'bz) || PIPERX01PHYSTATUS; // rv 1 + assign PIPERX01STARTBLOCK_in[0] = (PIPERX01STARTBLOCK[0] !== 1'bz) && PIPERX01STARTBLOCK[0]; // rv 0 + assign PIPERX01STARTBLOCK_in[1] = (PIPERX01STARTBLOCK[1] !== 1'bz) && PIPERX01STARTBLOCK[1]; // rv 0 + assign PIPERX01STATUS_in[0] = (PIPERX01STATUS[0] !== 1'bz) && PIPERX01STATUS[0]; // rv 0 + assign PIPERX01STATUS_in[1] = (PIPERX01STATUS[1] !== 1'bz) && PIPERX01STATUS[1]; // rv 0 + assign PIPERX01STATUS_in[2] = (PIPERX01STATUS[2] !== 1'bz) && PIPERX01STATUS[2]; // rv 0 + assign PIPERX01SYNCHEADER_in[0] = (PIPERX01SYNCHEADER[0] !== 1'bz) && PIPERX01SYNCHEADER[0]; // rv 0 + assign PIPERX01SYNCHEADER_in[1] = (PIPERX01SYNCHEADER[1] !== 1'bz) && PIPERX01SYNCHEADER[1]; // rv 0 + assign PIPERX01VALID_in = (PIPERX01VALID !== 1'bz) && PIPERX01VALID; // rv 0 + assign PIPERX02CHARISK_in[0] = (PIPERX02CHARISK[0] === 1'bz) || PIPERX02CHARISK[0]; // rv 1 + assign PIPERX02CHARISK_in[1] = (PIPERX02CHARISK[1] === 1'bz) || PIPERX02CHARISK[1]; // rv 1 + assign PIPERX02DATAVALID_in = (PIPERX02DATAVALID !== 1'bz) && PIPERX02DATAVALID; // rv 0 + assign PIPERX02DATA_in[0] = (PIPERX02DATA[0] !== 1'bz) && PIPERX02DATA[0]; // rv 0 + assign PIPERX02DATA_in[10] = (PIPERX02DATA[10] !== 1'bz) && PIPERX02DATA[10]; // rv 0 + assign PIPERX02DATA_in[11] = (PIPERX02DATA[11] !== 1'bz) && PIPERX02DATA[11]; // rv 0 + assign PIPERX02DATA_in[12] = (PIPERX02DATA[12] !== 1'bz) && PIPERX02DATA[12]; // rv 0 + assign PIPERX02DATA_in[13] = (PIPERX02DATA[13] !== 1'bz) && PIPERX02DATA[13]; // rv 0 + assign PIPERX02DATA_in[14] = (PIPERX02DATA[14] !== 1'bz) && PIPERX02DATA[14]; // rv 0 + assign PIPERX02DATA_in[15] = (PIPERX02DATA[15] !== 1'bz) && PIPERX02DATA[15]; // rv 0 + assign PIPERX02DATA_in[16] = (PIPERX02DATA[16] !== 1'bz) && PIPERX02DATA[16]; // rv 0 + assign PIPERX02DATA_in[17] = (PIPERX02DATA[17] !== 1'bz) && PIPERX02DATA[17]; // rv 0 + assign PIPERX02DATA_in[18] = (PIPERX02DATA[18] !== 1'bz) && PIPERX02DATA[18]; // rv 0 + assign PIPERX02DATA_in[19] = (PIPERX02DATA[19] !== 1'bz) && PIPERX02DATA[19]; // rv 0 + assign PIPERX02DATA_in[1] = (PIPERX02DATA[1] !== 1'bz) && PIPERX02DATA[1]; // rv 0 + assign PIPERX02DATA_in[20] = (PIPERX02DATA[20] !== 1'bz) && PIPERX02DATA[20]; // rv 0 + assign PIPERX02DATA_in[21] = (PIPERX02DATA[21] !== 1'bz) && PIPERX02DATA[21]; // rv 0 + assign PIPERX02DATA_in[22] = (PIPERX02DATA[22] !== 1'bz) && PIPERX02DATA[22]; // rv 0 + assign PIPERX02DATA_in[23] = (PIPERX02DATA[23] !== 1'bz) && PIPERX02DATA[23]; // rv 0 + assign PIPERX02DATA_in[24] = (PIPERX02DATA[24] !== 1'bz) && PIPERX02DATA[24]; // rv 0 + assign PIPERX02DATA_in[25] = (PIPERX02DATA[25] !== 1'bz) && PIPERX02DATA[25]; // rv 0 + assign PIPERX02DATA_in[26] = (PIPERX02DATA[26] !== 1'bz) && PIPERX02DATA[26]; // rv 0 + assign PIPERX02DATA_in[27] = (PIPERX02DATA[27] !== 1'bz) && PIPERX02DATA[27]; // rv 0 + assign PIPERX02DATA_in[28] = (PIPERX02DATA[28] !== 1'bz) && PIPERX02DATA[28]; // rv 0 + assign PIPERX02DATA_in[29] = (PIPERX02DATA[29] !== 1'bz) && PIPERX02DATA[29]; // rv 0 + assign PIPERX02DATA_in[2] = (PIPERX02DATA[2] !== 1'bz) && PIPERX02DATA[2]; // rv 0 + assign PIPERX02DATA_in[30] = (PIPERX02DATA[30] !== 1'bz) && PIPERX02DATA[30]; // rv 0 + assign PIPERX02DATA_in[31] = (PIPERX02DATA[31] !== 1'bz) && PIPERX02DATA[31]; // rv 0 + assign PIPERX02DATA_in[3] = (PIPERX02DATA[3] !== 1'bz) && PIPERX02DATA[3]; // rv 0 + assign PIPERX02DATA_in[4] = (PIPERX02DATA[4] !== 1'bz) && PIPERX02DATA[4]; // rv 0 + assign PIPERX02DATA_in[5] = (PIPERX02DATA[5] !== 1'bz) && PIPERX02DATA[5]; // rv 0 + assign PIPERX02DATA_in[6] = (PIPERX02DATA[6] !== 1'bz) && PIPERX02DATA[6]; // rv 0 + assign PIPERX02DATA_in[7] = (PIPERX02DATA[7] !== 1'bz) && PIPERX02DATA[7]; // rv 0 + assign PIPERX02DATA_in[8] = (PIPERX02DATA[8] !== 1'bz) && PIPERX02DATA[8]; // rv 0 + assign PIPERX02DATA_in[9] = (PIPERX02DATA[9] !== 1'bz) && PIPERX02DATA[9]; // rv 0 + assign PIPERX02ELECIDLE_in = (PIPERX02ELECIDLE === 1'bz) || PIPERX02ELECIDLE; // rv 1 + assign PIPERX02EQDONE_in = (PIPERX02EQDONE !== 1'bz) && PIPERX02EQDONE; // rv 0 + assign PIPERX02EQLPADAPTDONE_in = (PIPERX02EQLPADAPTDONE !== 1'bz) && PIPERX02EQLPADAPTDONE; // rv 0 + assign PIPERX02EQLPLFFSSEL_in = (PIPERX02EQLPLFFSSEL !== 1'bz) && PIPERX02EQLPLFFSSEL; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX02EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX02EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX02EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX02EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX02EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX02EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX02EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX02EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX02EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX02EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX02EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX02EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX02EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX02EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX02EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX02EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX02EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX02EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX02PHYSTATUS_in = (PIPERX02PHYSTATUS === 1'bz) || PIPERX02PHYSTATUS; // rv 1 + assign PIPERX02STARTBLOCK_in[0] = (PIPERX02STARTBLOCK[0] !== 1'bz) && PIPERX02STARTBLOCK[0]; // rv 0 + assign PIPERX02STARTBLOCK_in[1] = (PIPERX02STARTBLOCK[1] !== 1'bz) && PIPERX02STARTBLOCK[1]; // rv 0 + assign PIPERX02STATUS_in[0] = (PIPERX02STATUS[0] !== 1'bz) && PIPERX02STATUS[0]; // rv 0 + assign PIPERX02STATUS_in[1] = (PIPERX02STATUS[1] !== 1'bz) && PIPERX02STATUS[1]; // rv 0 + assign PIPERX02STATUS_in[2] = (PIPERX02STATUS[2] !== 1'bz) && PIPERX02STATUS[2]; // rv 0 + assign PIPERX02SYNCHEADER_in[0] = (PIPERX02SYNCHEADER[0] !== 1'bz) && PIPERX02SYNCHEADER[0]; // rv 0 + assign PIPERX02SYNCHEADER_in[1] = (PIPERX02SYNCHEADER[1] !== 1'bz) && PIPERX02SYNCHEADER[1]; // rv 0 + assign PIPERX02VALID_in = (PIPERX02VALID !== 1'bz) && PIPERX02VALID; // rv 0 + assign PIPERX03CHARISK_in[0] = (PIPERX03CHARISK[0] === 1'bz) || PIPERX03CHARISK[0]; // rv 1 + assign PIPERX03CHARISK_in[1] = (PIPERX03CHARISK[1] === 1'bz) || PIPERX03CHARISK[1]; // rv 1 + assign PIPERX03DATAVALID_in = (PIPERX03DATAVALID !== 1'bz) && PIPERX03DATAVALID; // rv 0 + assign PIPERX03DATA_in[0] = (PIPERX03DATA[0] !== 1'bz) && PIPERX03DATA[0]; // rv 0 + assign PIPERX03DATA_in[10] = (PIPERX03DATA[10] !== 1'bz) && PIPERX03DATA[10]; // rv 0 + assign PIPERX03DATA_in[11] = (PIPERX03DATA[11] !== 1'bz) && PIPERX03DATA[11]; // rv 0 + assign PIPERX03DATA_in[12] = (PIPERX03DATA[12] !== 1'bz) && PIPERX03DATA[12]; // rv 0 + assign PIPERX03DATA_in[13] = (PIPERX03DATA[13] !== 1'bz) && PIPERX03DATA[13]; // rv 0 + assign PIPERX03DATA_in[14] = (PIPERX03DATA[14] !== 1'bz) && PIPERX03DATA[14]; // rv 0 + assign PIPERX03DATA_in[15] = (PIPERX03DATA[15] !== 1'bz) && PIPERX03DATA[15]; // rv 0 + assign PIPERX03DATA_in[16] = (PIPERX03DATA[16] !== 1'bz) && PIPERX03DATA[16]; // rv 0 + assign PIPERX03DATA_in[17] = (PIPERX03DATA[17] !== 1'bz) && PIPERX03DATA[17]; // rv 0 + assign PIPERX03DATA_in[18] = (PIPERX03DATA[18] !== 1'bz) && PIPERX03DATA[18]; // rv 0 + assign PIPERX03DATA_in[19] = (PIPERX03DATA[19] !== 1'bz) && PIPERX03DATA[19]; // rv 0 + assign PIPERX03DATA_in[1] = (PIPERX03DATA[1] !== 1'bz) && PIPERX03DATA[1]; // rv 0 + assign PIPERX03DATA_in[20] = (PIPERX03DATA[20] !== 1'bz) && PIPERX03DATA[20]; // rv 0 + assign PIPERX03DATA_in[21] = (PIPERX03DATA[21] !== 1'bz) && PIPERX03DATA[21]; // rv 0 + assign PIPERX03DATA_in[22] = (PIPERX03DATA[22] !== 1'bz) && PIPERX03DATA[22]; // rv 0 + assign PIPERX03DATA_in[23] = (PIPERX03DATA[23] !== 1'bz) && PIPERX03DATA[23]; // rv 0 + assign PIPERX03DATA_in[24] = (PIPERX03DATA[24] !== 1'bz) && PIPERX03DATA[24]; // rv 0 + assign PIPERX03DATA_in[25] = (PIPERX03DATA[25] !== 1'bz) && PIPERX03DATA[25]; // rv 0 + assign PIPERX03DATA_in[26] = (PIPERX03DATA[26] !== 1'bz) && PIPERX03DATA[26]; // rv 0 + assign PIPERX03DATA_in[27] = (PIPERX03DATA[27] !== 1'bz) && PIPERX03DATA[27]; // rv 0 + assign PIPERX03DATA_in[28] = (PIPERX03DATA[28] !== 1'bz) && PIPERX03DATA[28]; // rv 0 + assign PIPERX03DATA_in[29] = (PIPERX03DATA[29] !== 1'bz) && PIPERX03DATA[29]; // rv 0 + assign PIPERX03DATA_in[2] = (PIPERX03DATA[2] !== 1'bz) && PIPERX03DATA[2]; // rv 0 + assign PIPERX03DATA_in[30] = (PIPERX03DATA[30] !== 1'bz) && PIPERX03DATA[30]; // rv 0 + assign PIPERX03DATA_in[31] = (PIPERX03DATA[31] !== 1'bz) && PIPERX03DATA[31]; // rv 0 + assign PIPERX03DATA_in[3] = (PIPERX03DATA[3] !== 1'bz) && PIPERX03DATA[3]; // rv 0 + assign PIPERX03DATA_in[4] = (PIPERX03DATA[4] !== 1'bz) && PIPERX03DATA[4]; // rv 0 + assign PIPERX03DATA_in[5] = (PIPERX03DATA[5] !== 1'bz) && PIPERX03DATA[5]; // rv 0 + assign PIPERX03DATA_in[6] = (PIPERX03DATA[6] !== 1'bz) && PIPERX03DATA[6]; // rv 0 + assign PIPERX03DATA_in[7] = (PIPERX03DATA[7] !== 1'bz) && PIPERX03DATA[7]; // rv 0 + assign PIPERX03DATA_in[8] = (PIPERX03DATA[8] !== 1'bz) && PIPERX03DATA[8]; // rv 0 + assign PIPERX03DATA_in[9] = (PIPERX03DATA[9] !== 1'bz) && PIPERX03DATA[9]; // rv 0 + assign PIPERX03ELECIDLE_in = (PIPERX03ELECIDLE === 1'bz) || PIPERX03ELECIDLE; // rv 1 + assign PIPERX03EQDONE_in = (PIPERX03EQDONE !== 1'bz) && PIPERX03EQDONE; // rv 0 + assign PIPERX03EQLPADAPTDONE_in = (PIPERX03EQLPADAPTDONE !== 1'bz) && PIPERX03EQLPADAPTDONE; // rv 0 + assign PIPERX03EQLPLFFSSEL_in = (PIPERX03EQLPLFFSSEL !== 1'bz) && PIPERX03EQLPLFFSSEL; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX03EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX03EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX03EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX03EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX03EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX03EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX03EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX03EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX03EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX03EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX03EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX03EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX03EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX03EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX03EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX03EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX03EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX03EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX03PHYSTATUS_in = (PIPERX03PHYSTATUS === 1'bz) || PIPERX03PHYSTATUS; // rv 1 + assign PIPERX03STARTBLOCK_in[0] = (PIPERX03STARTBLOCK[0] !== 1'bz) && PIPERX03STARTBLOCK[0]; // rv 0 + assign PIPERX03STARTBLOCK_in[1] = (PIPERX03STARTBLOCK[1] !== 1'bz) && PIPERX03STARTBLOCK[1]; // rv 0 + assign PIPERX03STATUS_in[0] = (PIPERX03STATUS[0] !== 1'bz) && PIPERX03STATUS[0]; // rv 0 + assign PIPERX03STATUS_in[1] = (PIPERX03STATUS[1] !== 1'bz) && PIPERX03STATUS[1]; // rv 0 + assign PIPERX03STATUS_in[2] = (PIPERX03STATUS[2] !== 1'bz) && PIPERX03STATUS[2]; // rv 0 + assign PIPERX03SYNCHEADER_in[0] = (PIPERX03SYNCHEADER[0] !== 1'bz) && PIPERX03SYNCHEADER[0]; // rv 0 + assign PIPERX03SYNCHEADER_in[1] = (PIPERX03SYNCHEADER[1] !== 1'bz) && PIPERX03SYNCHEADER[1]; // rv 0 + assign PIPERX03VALID_in = (PIPERX03VALID !== 1'bz) && PIPERX03VALID; // rv 0 + assign PIPERX04CHARISK_in[0] = (PIPERX04CHARISK[0] === 1'bz) || PIPERX04CHARISK[0]; // rv 1 + assign PIPERX04CHARISK_in[1] = (PIPERX04CHARISK[1] === 1'bz) || PIPERX04CHARISK[1]; // rv 1 + assign PIPERX04DATAVALID_in = (PIPERX04DATAVALID !== 1'bz) && PIPERX04DATAVALID; // rv 0 + assign PIPERX04DATA_in[0] = (PIPERX04DATA[0] !== 1'bz) && PIPERX04DATA[0]; // rv 0 + assign PIPERX04DATA_in[10] = (PIPERX04DATA[10] !== 1'bz) && PIPERX04DATA[10]; // rv 0 + assign PIPERX04DATA_in[11] = (PIPERX04DATA[11] !== 1'bz) && PIPERX04DATA[11]; // rv 0 + assign PIPERX04DATA_in[12] = (PIPERX04DATA[12] !== 1'bz) && PIPERX04DATA[12]; // rv 0 + assign PIPERX04DATA_in[13] = (PIPERX04DATA[13] !== 1'bz) && PIPERX04DATA[13]; // rv 0 + assign PIPERX04DATA_in[14] = (PIPERX04DATA[14] !== 1'bz) && PIPERX04DATA[14]; // rv 0 + assign PIPERX04DATA_in[15] = (PIPERX04DATA[15] !== 1'bz) && PIPERX04DATA[15]; // rv 0 + assign PIPERX04DATA_in[16] = (PIPERX04DATA[16] !== 1'bz) && PIPERX04DATA[16]; // rv 0 + assign PIPERX04DATA_in[17] = (PIPERX04DATA[17] !== 1'bz) && PIPERX04DATA[17]; // rv 0 + assign PIPERX04DATA_in[18] = (PIPERX04DATA[18] !== 1'bz) && PIPERX04DATA[18]; // rv 0 + assign PIPERX04DATA_in[19] = (PIPERX04DATA[19] !== 1'bz) && PIPERX04DATA[19]; // rv 0 + assign PIPERX04DATA_in[1] = (PIPERX04DATA[1] !== 1'bz) && PIPERX04DATA[1]; // rv 0 + assign PIPERX04DATA_in[20] = (PIPERX04DATA[20] !== 1'bz) && PIPERX04DATA[20]; // rv 0 + assign PIPERX04DATA_in[21] = (PIPERX04DATA[21] !== 1'bz) && PIPERX04DATA[21]; // rv 0 + assign PIPERX04DATA_in[22] = (PIPERX04DATA[22] !== 1'bz) && PIPERX04DATA[22]; // rv 0 + assign PIPERX04DATA_in[23] = (PIPERX04DATA[23] !== 1'bz) && PIPERX04DATA[23]; // rv 0 + assign PIPERX04DATA_in[24] = (PIPERX04DATA[24] !== 1'bz) && PIPERX04DATA[24]; // rv 0 + assign PIPERX04DATA_in[25] = (PIPERX04DATA[25] !== 1'bz) && PIPERX04DATA[25]; // rv 0 + assign PIPERX04DATA_in[26] = (PIPERX04DATA[26] !== 1'bz) && PIPERX04DATA[26]; // rv 0 + assign PIPERX04DATA_in[27] = (PIPERX04DATA[27] !== 1'bz) && PIPERX04DATA[27]; // rv 0 + assign PIPERX04DATA_in[28] = (PIPERX04DATA[28] !== 1'bz) && PIPERX04DATA[28]; // rv 0 + assign PIPERX04DATA_in[29] = (PIPERX04DATA[29] !== 1'bz) && PIPERX04DATA[29]; // rv 0 + assign PIPERX04DATA_in[2] = (PIPERX04DATA[2] !== 1'bz) && PIPERX04DATA[2]; // rv 0 + assign PIPERX04DATA_in[30] = (PIPERX04DATA[30] !== 1'bz) && PIPERX04DATA[30]; // rv 0 + assign PIPERX04DATA_in[31] = (PIPERX04DATA[31] !== 1'bz) && PIPERX04DATA[31]; // rv 0 + assign PIPERX04DATA_in[3] = (PIPERX04DATA[3] !== 1'bz) && PIPERX04DATA[3]; // rv 0 + assign PIPERX04DATA_in[4] = (PIPERX04DATA[4] !== 1'bz) && PIPERX04DATA[4]; // rv 0 + assign PIPERX04DATA_in[5] = (PIPERX04DATA[5] !== 1'bz) && PIPERX04DATA[5]; // rv 0 + assign PIPERX04DATA_in[6] = (PIPERX04DATA[6] !== 1'bz) && PIPERX04DATA[6]; // rv 0 + assign PIPERX04DATA_in[7] = (PIPERX04DATA[7] !== 1'bz) && PIPERX04DATA[7]; // rv 0 + assign PIPERX04DATA_in[8] = (PIPERX04DATA[8] !== 1'bz) && PIPERX04DATA[8]; // rv 0 + assign PIPERX04DATA_in[9] = (PIPERX04DATA[9] !== 1'bz) && PIPERX04DATA[9]; // rv 0 + assign PIPERX04ELECIDLE_in = (PIPERX04ELECIDLE === 1'bz) || PIPERX04ELECIDLE; // rv 1 + assign PIPERX04EQDONE_in = (PIPERX04EQDONE !== 1'bz) && PIPERX04EQDONE; // rv 0 + assign PIPERX04EQLPADAPTDONE_in = (PIPERX04EQLPADAPTDONE !== 1'bz) && PIPERX04EQLPADAPTDONE; // rv 0 + assign PIPERX04EQLPLFFSSEL_in = (PIPERX04EQLPLFFSSEL !== 1'bz) && PIPERX04EQLPLFFSSEL; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX04EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX04EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX04EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX04EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX04EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX04EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX04EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX04EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX04EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX04EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX04EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX04EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX04EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX04EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX04EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX04EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX04EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX04EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX04PHYSTATUS_in = (PIPERX04PHYSTATUS === 1'bz) || PIPERX04PHYSTATUS; // rv 1 + assign PIPERX04STARTBLOCK_in[0] = (PIPERX04STARTBLOCK[0] !== 1'bz) && PIPERX04STARTBLOCK[0]; // rv 0 + assign PIPERX04STARTBLOCK_in[1] = (PIPERX04STARTBLOCK[1] !== 1'bz) && PIPERX04STARTBLOCK[1]; // rv 0 + assign PIPERX04STATUS_in[0] = (PIPERX04STATUS[0] !== 1'bz) && PIPERX04STATUS[0]; // rv 0 + assign PIPERX04STATUS_in[1] = (PIPERX04STATUS[1] !== 1'bz) && PIPERX04STATUS[1]; // rv 0 + assign PIPERX04STATUS_in[2] = (PIPERX04STATUS[2] !== 1'bz) && PIPERX04STATUS[2]; // rv 0 + assign PIPERX04SYNCHEADER_in[0] = (PIPERX04SYNCHEADER[0] !== 1'bz) && PIPERX04SYNCHEADER[0]; // rv 0 + assign PIPERX04SYNCHEADER_in[1] = (PIPERX04SYNCHEADER[1] !== 1'bz) && PIPERX04SYNCHEADER[1]; // rv 0 + assign PIPERX04VALID_in = (PIPERX04VALID !== 1'bz) && PIPERX04VALID; // rv 0 + assign PIPERX05CHARISK_in[0] = (PIPERX05CHARISK[0] === 1'bz) || PIPERX05CHARISK[0]; // rv 1 + assign PIPERX05CHARISK_in[1] = (PIPERX05CHARISK[1] === 1'bz) || PIPERX05CHARISK[1]; // rv 1 + assign PIPERX05DATAVALID_in = (PIPERX05DATAVALID !== 1'bz) && PIPERX05DATAVALID; // rv 0 + assign PIPERX05DATA_in[0] = (PIPERX05DATA[0] !== 1'bz) && PIPERX05DATA[0]; // rv 0 + assign PIPERX05DATA_in[10] = (PIPERX05DATA[10] !== 1'bz) && PIPERX05DATA[10]; // rv 0 + assign PIPERX05DATA_in[11] = (PIPERX05DATA[11] !== 1'bz) && PIPERX05DATA[11]; // rv 0 + assign PIPERX05DATA_in[12] = (PIPERX05DATA[12] !== 1'bz) && PIPERX05DATA[12]; // rv 0 + assign PIPERX05DATA_in[13] = (PIPERX05DATA[13] !== 1'bz) && PIPERX05DATA[13]; // rv 0 + assign PIPERX05DATA_in[14] = (PIPERX05DATA[14] !== 1'bz) && PIPERX05DATA[14]; // rv 0 + assign PIPERX05DATA_in[15] = (PIPERX05DATA[15] !== 1'bz) && PIPERX05DATA[15]; // rv 0 + assign PIPERX05DATA_in[16] = (PIPERX05DATA[16] !== 1'bz) && PIPERX05DATA[16]; // rv 0 + assign PIPERX05DATA_in[17] = (PIPERX05DATA[17] !== 1'bz) && PIPERX05DATA[17]; // rv 0 + assign PIPERX05DATA_in[18] = (PIPERX05DATA[18] !== 1'bz) && PIPERX05DATA[18]; // rv 0 + assign PIPERX05DATA_in[19] = (PIPERX05DATA[19] !== 1'bz) && PIPERX05DATA[19]; // rv 0 + assign PIPERX05DATA_in[1] = (PIPERX05DATA[1] !== 1'bz) && PIPERX05DATA[1]; // rv 0 + assign PIPERX05DATA_in[20] = (PIPERX05DATA[20] !== 1'bz) && PIPERX05DATA[20]; // rv 0 + assign PIPERX05DATA_in[21] = (PIPERX05DATA[21] !== 1'bz) && PIPERX05DATA[21]; // rv 0 + assign PIPERX05DATA_in[22] = (PIPERX05DATA[22] !== 1'bz) && PIPERX05DATA[22]; // rv 0 + assign PIPERX05DATA_in[23] = (PIPERX05DATA[23] !== 1'bz) && PIPERX05DATA[23]; // rv 0 + assign PIPERX05DATA_in[24] = (PIPERX05DATA[24] !== 1'bz) && PIPERX05DATA[24]; // rv 0 + assign PIPERX05DATA_in[25] = (PIPERX05DATA[25] !== 1'bz) && PIPERX05DATA[25]; // rv 0 + assign PIPERX05DATA_in[26] = (PIPERX05DATA[26] !== 1'bz) && PIPERX05DATA[26]; // rv 0 + assign PIPERX05DATA_in[27] = (PIPERX05DATA[27] !== 1'bz) && PIPERX05DATA[27]; // rv 0 + assign PIPERX05DATA_in[28] = (PIPERX05DATA[28] !== 1'bz) && PIPERX05DATA[28]; // rv 0 + assign PIPERX05DATA_in[29] = (PIPERX05DATA[29] !== 1'bz) && PIPERX05DATA[29]; // rv 0 + assign PIPERX05DATA_in[2] = (PIPERX05DATA[2] !== 1'bz) && PIPERX05DATA[2]; // rv 0 + assign PIPERX05DATA_in[30] = (PIPERX05DATA[30] !== 1'bz) && PIPERX05DATA[30]; // rv 0 + assign PIPERX05DATA_in[31] = (PIPERX05DATA[31] !== 1'bz) && PIPERX05DATA[31]; // rv 0 + assign PIPERX05DATA_in[3] = (PIPERX05DATA[3] !== 1'bz) && PIPERX05DATA[3]; // rv 0 + assign PIPERX05DATA_in[4] = (PIPERX05DATA[4] !== 1'bz) && PIPERX05DATA[4]; // rv 0 + assign PIPERX05DATA_in[5] = (PIPERX05DATA[5] !== 1'bz) && PIPERX05DATA[5]; // rv 0 + assign PIPERX05DATA_in[6] = (PIPERX05DATA[6] !== 1'bz) && PIPERX05DATA[6]; // rv 0 + assign PIPERX05DATA_in[7] = (PIPERX05DATA[7] !== 1'bz) && PIPERX05DATA[7]; // rv 0 + assign PIPERX05DATA_in[8] = (PIPERX05DATA[8] !== 1'bz) && PIPERX05DATA[8]; // rv 0 + assign PIPERX05DATA_in[9] = (PIPERX05DATA[9] !== 1'bz) && PIPERX05DATA[9]; // rv 0 + assign PIPERX05ELECIDLE_in = (PIPERX05ELECIDLE === 1'bz) || PIPERX05ELECIDLE; // rv 1 + assign PIPERX05EQDONE_in = (PIPERX05EQDONE !== 1'bz) && PIPERX05EQDONE; // rv 0 + assign PIPERX05EQLPADAPTDONE_in = (PIPERX05EQLPADAPTDONE !== 1'bz) && PIPERX05EQLPADAPTDONE; // rv 0 + assign PIPERX05EQLPLFFSSEL_in = (PIPERX05EQLPLFFSSEL !== 1'bz) && PIPERX05EQLPLFFSSEL; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX05EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX05EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX05EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX05EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX05EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX05EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX05EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX05EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX05EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX05EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX05EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX05EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX05EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX05EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX05EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX05EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX05EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX05EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX05PHYSTATUS_in = (PIPERX05PHYSTATUS === 1'bz) || PIPERX05PHYSTATUS; // rv 1 + assign PIPERX05STARTBLOCK_in[0] = (PIPERX05STARTBLOCK[0] !== 1'bz) && PIPERX05STARTBLOCK[0]; // rv 0 + assign PIPERX05STARTBLOCK_in[1] = (PIPERX05STARTBLOCK[1] !== 1'bz) && PIPERX05STARTBLOCK[1]; // rv 0 + assign PIPERX05STATUS_in[0] = (PIPERX05STATUS[0] !== 1'bz) && PIPERX05STATUS[0]; // rv 0 + assign PIPERX05STATUS_in[1] = (PIPERX05STATUS[1] !== 1'bz) && PIPERX05STATUS[1]; // rv 0 + assign PIPERX05STATUS_in[2] = (PIPERX05STATUS[2] !== 1'bz) && PIPERX05STATUS[2]; // rv 0 + assign PIPERX05SYNCHEADER_in[0] = (PIPERX05SYNCHEADER[0] !== 1'bz) && PIPERX05SYNCHEADER[0]; // rv 0 + assign PIPERX05SYNCHEADER_in[1] = (PIPERX05SYNCHEADER[1] !== 1'bz) && PIPERX05SYNCHEADER[1]; // rv 0 + assign PIPERX05VALID_in = (PIPERX05VALID !== 1'bz) && PIPERX05VALID; // rv 0 + assign PIPERX06CHARISK_in[0] = (PIPERX06CHARISK[0] === 1'bz) || PIPERX06CHARISK[0]; // rv 1 + assign PIPERX06CHARISK_in[1] = (PIPERX06CHARISK[1] === 1'bz) || PIPERX06CHARISK[1]; // rv 1 + assign PIPERX06DATAVALID_in = (PIPERX06DATAVALID !== 1'bz) && PIPERX06DATAVALID; // rv 0 + assign PIPERX06DATA_in[0] = (PIPERX06DATA[0] !== 1'bz) && PIPERX06DATA[0]; // rv 0 + assign PIPERX06DATA_in[10] = (PIPERX06DATA[10] !== 1'bz) && PIPERX06DATA[10]; // rv 0 + assign PIPERX06DATA_in[11] = (PIPERX06DATA[11] !== 1'bz) && PIPERX06DATA[11]; // rv 0 + assign PIPERX06DATA_in[12] = (PIPERX06DATA[12] !== 1'bz) && PIPERX06DATA[12]; // rv 0 + assign PIPERX06DATA_in[13] = (PIPERX06DATA[13] !== 1'bz) && PIPERX06DATA[13]; // rv 0 + assign PIPERX06DATA_in[14] = (PIPERX06DATA[14] !== 1'bz) && PIPERX06DATA[14]; // rv 0 + assign PIPERX06DATA_in[15] = (PIPERX06DATA[15] !== 1'bz) && PIPERX06DATA[15]; // rv 0 + assign PIPERX06DATA_in[16] = (PIPERX06DATA[16] !== 1'bz) && PIPERX06DATA[16]; // rv 0 + assign PIPERX06DATA_in[17] = (PIPERX06DATA[17] !== 1'bz) && PIPERX06DATA[17]; // rv 0 + assign PIPERX06DATA_in[18] = (PIPERX06DATA[18] !== 1'bz) && PIPERX06DATA[18]; // rv 0 + assign PIPERX06DATA_in[19] = (PIPERX06DATA[19] !== 1'bz) && PIPERX06DATA[19]; // rv 0 + assign PIPERX06DATA_in[1] = (PIPERX06DATA[1] !== 1'bz) && PIPERX06DATA[1]; // rv 0 + assign PIPERX06DATA_in[20] = (PIPERX06DATA[20] !== 1'bz) && PIPERX06DATA[20]; // rv 0 + assign PIPERX06DATA_in[21] = (PIPERX06DATA[21] !== 1'bz) && PIPERX06DATA[21]; // rv 0 + assign PIPERX06DATA_in[22] = (PIPERX06DATA[22] !== 1'bz) && PIPERX06DATA[22]; // rv 0 + assign PIPERX06DATA_in[23] = (PIPERX06DATA[23] !== 1'bz) && PIPERX06DATA[23]; // rv 0 + assign PIPERX06DATA_in[24] = (PIPERX06DATA[24] !== 1'bz) && PIPERX06DATA[24]; // rv 0 + assign PIPERX06DATA_in[25] = (PIPERX06DATA[25] !== 1'bz) && PIPERX06DATA[25]; // rv 0 + assign PIPERX06DATA_in[26] = (PIPERX06DATA[26] !== 1'bz) && PIPERX06DATA[26]; // rv 0 + assign PIPERX06DATA_in[27] = (PIPERX06DATA[27] !== 1'bz) && PIPERX06DATA[27]; // rv 0 + assign PIPERX06DATA_in[28] = (PIPERX06DATA[28] !== 1'bz) && PIPERX06DATA[28]; // rv 0 + assign PIPERX06DATA_in[29] = (PIPERX06DATA[29] !== 1'bz) && PIPERX06DATA[29]; // rv 0 + assign PIPERX06DATA_in[2] = (PIPERX06DATA[2] !== 1'bz) && PIPERX06DATA[2]; // rv 0 + assign PIPERX06DATA_in[30] = (PIPERX06DATA[30] !== 1'bz) && PIPERX06DATA[30]; // rv 0 + assign PIPERX06DATA_in[31] = (PIPERX06DATA[31] !== 1'bz) && PIPERX06DATA[31]; // rv 0 + assign PIPERX06DATA_in[3] = (PIPERX06DATA[3] !== 1'bz) && PIPERX06DATA[3]; // rv 0 + assign PIPERX06DATA_in[4] = (PIPERX06DATA[4] !== 1'bz) && PIPERX06DATA[4]; // rv 0 + assign PIPERX06DATA_in[5] = (PIPERX06DATA[5] !== 1'bz) && PIPERX06DATA[5]; // rv 0 + assign PIPERX06DATA_in[6] = (PIPERX06DATA[6] !== 1'bz) && PIPERX06DATA[6]; // rv 0 + assign PIPERX06DATA_in[7] = (PIPERX06DATA[7] !== 1'bz) && PIPERX06DATA[7]; // rv 0 + assign PIPERX06DATA_in[8] = (PIPERX06DATA[8] !== 1'bz) && PIPERX06DATA[8]; // rv 0 + assign PIPERX06DATA_in[9] = (PIPERX06DATA[9] !== 1'bz) && PIPERX06DATA[9]; // rv 0 + assign PIPERX06ELECIDLE_in = (PIPERX06ELECIDLE === 1'bz) || PIPERX06ELECIDLE; // rv 1 + assign PIPERX06EQDONE_in = (PIPERX06EQDONE !== 1'bz) && PIPERX06EQDONE; // rv 0 + assign PIPERX06EQLPADAPTDONE_in = (PIPERX06EQLPADAPTDONE !== 1'bz) && PIPERX06EQLPADAPTDONE; // rv 0 + assign PIPERX06EQLPLFFSSEL_in = (PIPERX06EQLPLFFSSEL !== 1'bz) && PIPERX06EQLPLFFSSEL; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX06EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX06EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX06EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX06EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX06EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX06EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX06EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX06EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX06EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX06EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX06EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX06EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX06EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX06EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX06EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX06EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX06EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX06EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX06PHYSTATUS_in = (PIPERX06PHYSTATUS === 1'bz) || PIPERX06PHYSTATUS; // rv 1 + assign PIPERX06STARTBLOCK_in[0] = (PIPERX06STARTBLOCK[0] !== 1'bz) && PIPERX06STARTBLOCK[0]; // rv 0 + assign PIPERX06STARTBLOCK_in[1] = (PIPERX06STARTBLOCK[1] !== 1'bz) && PIPERX06STARTBLOCK[1]; // rv 0 + assign PIPERX06STATUS_in[0] = (PIPERX06STATUS[0] !== 1'bz) && PIPERX06STATUS[0]; // rv 0 + assign PIPERX06STATUS_in[1] = (PIPERX06STATUS[1] !== 1'bz) && PIPERX06STATUS[1]; // rv 0 + assign PIPERX06STATUS_in[2] = (PIPERX06STATUS[2] !== 1'bz) && PIPERX06STATUS[2]; // rv 0 + assign PIPERX06SYNCHEADER_in[0] = (PIPERX06SYNCHEADER[0] !== 1'bz) && PIPERX06SYNCHEADER[0]; // rv 0 + assign PIPERX06SYNCHEADER_in[1] = (PIPERX06SYNCHEADER[1] !== 1'bz) && PIPERX06SYNCHEADER[1]; // rv 0 + assign PIPERX06VALID_in = (PIPERX06VALID !== 1'bz) && PIPERX06VALID; // rv 0 + assign PIPERX07CHARISK_in[0] = (PIPERX07CHARISK[0] === 1'bz) || PIPERX07CHARISK[0]; // rv 1 + assign PIPERX07CHARISK_in[1] = (PIPERX07CHARISK[1] === 1'bz) || PIPERX07CHARISK[1]; // rv 1 + assign PIPERX07DATAVALID_in = (PIPERX07DATAVALID !== 1'bz) && PIPERX07DATAVALID; // rv 0 + assign PIPERX07DATA_in[0] = (PIPERX07DATA[0] !== 1'bz) && PIPERX07DATA[0]; // rv 0 + assign PIPERX07DATA_in[10] = (PIPERX07DATA[10] !== 1'bz) && PIPERX07DATA[10]; // rv 0 + assign PIPERX07DATA_in[11] = (PIPERX07DATA[11] !== 1'bz) && PIPERX07DATA[11]; // rv 0 + assign PIPERX07DATA_in[12] = (PIPERX07DATA[12] !== 1'bz) && PIPERX07DATA[12]; // rv 0 + assign PIPERX07DATA_in[13] = (PIPERX07DATA[13] !== 1'bz) && PIPERX07DATA[13]; // rv 0 + assign PIPERX07DATA_in[14] = (PIPERX07DATA[14] !== 1'bz) && PIPERX07DATA[14]; // rv 0 + assign PIPERX07DATA_in[15] = (PIPERX07DATA[15] !== 1'bz) && PIPERX07DATA[15]; // rv 0 + assign PIPERX07DATA_in[16] = (PIPERX07DATA[16] !== 1'bz) && PIPERX07DATA[16]; // rv 0 + assign PIPERX07DATA_in[17] = (PIPERX07DATA[17] !== 1'bz) && PIPERX07DATA[17]; // rv 0 + assign PIPERX07DATA_in[18] = (PIPERX07DATA[18] !== 1'bz) && PIPERX07DATA[18]; // rv 0 + assign PIPERX07DATA_in[19] = (PIPERX07DATA[19] !== 1'bz) && PIPERX07DATA[19]; // rv 0 + assign PIPERX07DATA_in[1] = (PIPERX07DATA[1] !== 1'bz) && PIPERX07DATA[1]; // rv 0 + assign PIPERX07DATA_in[20] = (PIPERX07DATA[20] !== 1'bz) && PIPERX07DATA[20]; // rv 0 + assign PIPERX07DATA_in[21] = (PIPERX07DATA[21] !== 1'bz) && PIPERX07DATA[21]; // rv 0 + assign PIPERX07DATA_in[22] = (PIPERX07DATA[22] !== 1'bz) && PIPERX07DATA[22]; // rv 0 + assign PIPERX07DATA_in[23] = (PIPERX07DATA[23] !== 1'bz) && PIPERX07DATA[23]; // rv 0 + assign PIPERX07DATA_in[24] = (PIPERX07DATA[24] !== 1'bz) && PIPERX07DATA[24]; // rv 0 + assign PIPERX07DATA_in[25] = (PIPERX07DATA[25] !== 1'bz) && PIPERX07DATA[25]; // rv 0 + assign PIPERX07DATA_in[26] = (PIPERX07DATA[26] !== 1'bz) && PIPERX07DATA[26]; // rv 0 + assign PIPERX07DATA_in[27] = (PIPERX07DATA[27] !== 1'bz) && PIPERX07DATA[27]; // rv 0 + assign PIPERX07DATA_in[28] = (PIPERX07DATA[28] !== 1'bz) && PIPERX07DATA[28]; // rv 0 + assign PIPERX07DATA_in[29] = (PIPERX07DATA[29] !== 1'bz) && PIPERX07DATA[29]; // rv 0 + assign PIPERX07DATA_in[2] = (PIPERX07DATA[2] !== 1'bz) && PIPERX07DATA[2]; // rv 0 + assign PIPERX07DATA_in[30] = (PIPERX07DATA[30] !== 1'bz) && PIPERX07DATA[30]; // rv 0 + assign PIPERX07DATA_in[31] = (PIPERX07DATA[31] !== 1'bz) && PIPERX07DATA[31]; // rv 0 + assign PIPERX07DATA_in[3] = (PIPERX07DATA[3] !== 1'bz) && PIPERX07DATA[3]; // rv 0 + assign PIPERX07DATA_in[4] = (PIPERX07DATA[4] !== 1'bz) && PIPERX07DATA[4]; // rv 0 + assign PIPERX07DATA_in[5] = (PIPERX07DATA[5] !== 1'bz) && PIPERX07DATA[5]; // rv 0 + assign PIPERX07DATA_in[6] = (PIPERX07DATA[6] !== 1'bz) && PIPERX07DATA[6]; // rv 0 + assign PIPERX07DATA_in[7] = (PIPERX07DATA[7] !== 1'bz) && PIPERX07DATA[7]; // rv 0 + assign PIPERX07DATA_in[8] = (PIPERX07DATA[8] !== 1'bz) && PIPERX07DATA[8]; // rv 0 + assign PIPERX07DATA_in[9] = (PIPERX07DATA[9] !== 1'bz) && PIPERX07DATA[9]; // rv 0 + assign PIPERX07ELECIDLE_in = (PIPERX07ELECIDLE === 1'bz) || PIPERX07ELECIDLE; // rv 1 + assign PIPERX07EQDONE_in = (PIPERX07EQDONE !== 1'bz) && PIPERX07EQDONE; // rv 0 + assign PIPERX07EQLPADAPTDONE_in = (PIPERX07EQLPADAPTDONE !== 1'bz) && PIPERX07EQLPADAPTDONE; // rv 0 + assign PIPERX07EQLPLFFSSEL_in = (PIPERX07EQLPLFFSSEL !== 1'bz) && PIPERX07EQLPLFFSSEL; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX07EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX07EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX07EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX07EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX07EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX07EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX07EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX07EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX07EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX07EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX07EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX07EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX07EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX07EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX07EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX07EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX07EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX07EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX07PHYSTATUS_in = (PIPERX07PHYSTATUS === 1'bz) || PIPERX07PHYSTATUS; // rv 1 + assign PIPERX07STARTBLOCK_in[0] = (PIPERX07STARTBLOCK[0] !== 1'bz) && PIPERX07STARTBLOCK[0]; // rv 0 + assign PIPERX07STARTBLOCK_in[1] = (PIPERX07STARTBLOCK[1] !== 1'bz) && PIPERX07STARTBLOCK[1]; // rv 0 + assign PIPERX07STATUS_in[0] = (PIPERX07STATUS[0] !== 1'bz) && PIPERX07STATUS[0]; // rv 0 + assign PIPERX07STATUS_in[1] = (PIPERX07STATUS[1] !== 1'bz) && PIPERX07STATUS[1]; // rv 0 + assign PIPERX07STATUS_in[2] = (PIPERX07STATUS[2] !== 1'bz) && PIPERX07STATUS[2]; // rv 0 + assign PIPERX07SYNCHEADER_in[0] = (PIPERX07SYNCHEADER[0] !== 1'bz) && PIPERX07SYNCHEADER[0]; // rv 0 + assign PIPERX07SYNCHEADER_in[1] = (PIPERX07SYNCHEADER[1] !== 1'bz) && PIPERX07SYNCHEADER[1]; // rv 0 + assign PIPERX07VALID_in = (PIPERX07VALID !== 1'bz) && PIPERX07VALID; // rv 0 + assign PIPERX08CHARISK_in[0] = (PIPERX08CHARISK[0] === 1'bz) || PIPERX08CHARISK[0]; // rv 1 + assign PIPERX08CHARISK_in[1] = (PIPERX08CHARISK[1] === 1'bz) || PIPERX08CHARISK[1]; // rv 1 + assign PIPERX08DATAVALID_in = (PIPERX08DATAVALID !== 1'bz) && PIPERX08DATAVALID; // rv 0 + assign PIPERX08DATA_in[0] = (PIPERX08DATA[0] !== 1'bz) && PIPERX08DATA[0]; // rv 0 + assign PIPERX08DATA_in[10] = (PIPERX08DATA[10] !== 1'bz) && PIPERX08DATA[10]; // rv 0 + assign PIPERX08DATA_in[11] = (PIPERX08DATA[11] !== 1'bz) && PIPERX08DATA[11]; // rv 0 + assign PIPERX08DATA_in[12] = (PIPERX08DATA[12] !== 1'bz) && PIPERX08DATA[12]; // rv 0 + assign PIPERX08DATA_in[13] = (PIPERX08DATA[13] !== 1'bz) && PIPERX08DATA[13]; // rv 0 + assign PIPERX08DATA_in[14] = (PIPERX08DATA[14] !== 1'bz) && PIPERX08DATA[14]; // rv 0 + assign PIPERX08DATA_in[15] = (PIPERX08DATA[15] !== 1'bz) && PIPERX08DATA[15]; // rv 0 + assign PIPERX08DATA_in[16] = (PIPERX08DATA[16] !== 1'bz) && PIPERX08DATA[16]; // rv 0 + assign PIPERX08DATA_in[17] = (PIPERX08DATA[17] !== 1'bz) && PIPERX08DATA[17]; // rv 0 + assign PIPERX08DATA_in[18] = (PIPERX08DATA[18] !== 1'bz) && PIPERX08DATA[18]; // rv 0 + assign PIPERX08DATA_in[19] = (PIPERX08DATA[19] !== 1'bz) && PIPERX08DATA[19]; // rv 0 + assign PIPERX08DATA_in[1] = (PIPERX08DATA[1] !== 1'bz) && PIPERX08DATA[1]; // rv 0 + assign PIPERX08DATA_in[20] = (PIPERX08DATA[20] !== 1'bz) && PIPERX08DATA[20]; // rv 0 + assign PIPERX08DATA_in[21] = (PIPERX08DATA[21] !== 1'bz) && PIPERX08DATA[21]; // rv 0 + assign PIPERX08DATA_in[22] = (PIPERX08DATA[22] !== 1'bz) && PIPERX08DATA[22]; // rv 0 + assign PIPERX08DATA_in[23] = (PIPERX08DATA[23] !== 1'bz) && PIPERX08DATA[23]; // rv 0 + assign PIPERX08DATA_in[24] = (PIPERX08DATA[24] !== 1'bz) && PIPERX08DATA[24]; // rv 0 + assign PIPERX08DATA_in[25] = (PIPERX08DATA[25] !== 1'bz) && PIPERX08DATA[25]; // rv 0 + assign PIPERX08DATA_in[26] = (PIPERX08DATA[26] !== 1'bz) && PIPERX08DATA[26]; // rv 0 + assign PIPERX08DATA_in[27] = (PIPERX08DATA[27] !== 1'bz) && PIPERX08DATA[27]; // rv 0 + assign PIPERX08DATA_in[28] = (PIPERX08DATA[28] !== 1'bz) && PIPERX08DATA[28]; // rv 0 + assign PIPERX08DATA_in[29] = (PIPERX08DATA[29] !== 1'bz) && PIPERX08DATA[29]; // rv 0 + assign PIPERX08DATA_in[2] = (PIPERX08DATA[2] !== 1'bz) && PIPERX08DATA[2]; // rv 0 + assign PIPERX08DATA_in[30] = (PIPERX08DATA[30] !== 1'bz) && PIPERX08DATA[30]; // rv 0 + assign PIPERX08DATA_in[31] = (PIPERX08DATA[31] !== 1'bz) && PIPERX08DATA[31]; // rv 0 + assign PIPERX08DATA_in[3] = (PIPERX08DATA[3] !== 1'bz) && PIPERX08DATA[3]; // rv 0 + assign PIPERX08DATA_in[4] = (PIPERX08DATA[4] !== 1'bz) && PIPERX08DATA[4]; // rv 0 + assign PIPERX08DATA_in[5] = (PIPERX08DATA[5] !== 1'bz) && PIPERX08DATA[5]; // rv 0 + assign PIPERX08DATA_in[6] = (PIPERX08DATA[6] !== 1'bz) && PIPERX08DATA[6]; // rv 0 + assign PIPERX08DATA_in[7] = (PIPERX08DATA[7] !== 1'bz) && PIPERX08DATA[7]; // rv 0 + assign PIPERX08DATA_in[8] = (PIPERX08DATA[8] !== 1'bz) && PIPERX08DATA[8]; // rv 0 + assign PIPERX08DATA_in[9] = (PIPERX08DATA[9] !== 1'bz) && PIPERX08DATA[9]; // rv 0 + assign PIPERX08ELECIDLE_in = (PIPERX08ELECIDLE === 1'bz) || PIPERX08ELECIDLE; // rv 1 + assign PIPERX08EQDONE_in = (PIPERX08EQDONE !== 1'bz) && PIPERX08EQDONE; // rv 0 + assign PIPERX08EQLPADAPTDONE_in = (PIPERX08EQLPADAPTDONE !== 1'bz) && PIPERX08EQLPADAPTDONE; // rv 0 + assign PIPERX08EQLPLFFSSEL_in = (PIPERX08EQLPLFFSSEL !== 1'bz) && PIPERX08EQLPLFFSSEL; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX08EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX08EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX08EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX08EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX08EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX08EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX08EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX08EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX08EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX08EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX08EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX08EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX08EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX08EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX08EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX08EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX08EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX08EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX08PHYSTATUS_in = (PIPERX08PHYSTATUS === 1'bz) || PIPERX08PHYSTATUS; // rv 1 + assign PIPERX08STARTBLOCK_in[0] = (PIPERX08STARTBLOCK[0] !== 1'bz) && PIPERX08STARTBLOCK[0]; // rv 0 + assign PIPERX08STARTBLOCK_in[1] = (PIPERX08STARTBLOCK[1] !== 1'bz) && PIPERX08STARTBLOCK[1]; // rv 0 + assign PIPERX08STATUS_in[0] = (PIPERX08STATUS[0] !== 1'bz) && PIPERX08STATUS[0]; // rv 0 + assign PIPERX08STATUS_in[1] = (PIPERX08STATUS[1] !== 1'bz) && PIPERX08STATUS[1]; // rv 0 + assign PIPERX08STATUS_in[2] = (PIPERX08STATUS[2] !== 1'bz) && PIPERX08STATUS[2]; // rv 0 + assign PIPERX08SYNCHEADER_in[0] = (PIPERX08SYNCHEADER[0] !== 1'bz) && PIPERX08SYNCHEADER[0]; // rv 0 + assign PIPERX08SYNCHEADER_in[1] = (PIPERX08SYNCHEADER[1] !== 1'bz) && PIPERX08SYNCHEADER[1]; // rv 0 + assign PIPERX08VALID_in = (PIPERX08VALID !== 1'bz) && PIPERX08VALID; // rv 0 + assign PIPERX09CHARISK_in[0] = (PIPERX09CHARISK[0] === 1'bz) || PIPERX09CHARISK[0]; // rv 1 + assign PIPERX09CHARISK_in[1] = (PIPERX09CHARISK[1] === 1'bz) || PIPERX09CHARISK[1]; // rv 1 + assign PIPERX09DATAVALID_in = (PIPERX09DATAVALID !== 1'bz) && PIPERX09DATAVALID; // rv 0 + assign PIPERX09DATA_in[0] = (PIPERX09DATA[0] !== 1'bz) && PIPERX09DATA[0]; // rv 0 + assign PIPERX09DATA_in[10] = (PIPERX09DATA[10] !== 1'bz) && PIPERX09DATA[10]; // rv 0 + assign PIPERX09DATA_in[11] = (PIPERX09DATA[11] !== 1'bz) && PIPERX09DATA[11]; // rv 0 + assign PIPERX09DATA_in[12] = (PIPERX09DATA[12] !== 1'bz) && PIPERX09DATA[12]; // rv 0 + assign PIPERX09DATA_in[13] = (PIPERX09DATA[13] !== 1'bz) && PIPERX09DATA[13]; // rv 0 + assign PIPERX09DATA_in[14] = (PIPERX09DATA[14] !== 1'bz) && PIPERX09DATA[14]; // rv 0 + assign PIPERX09DATA_in[15] = (PIPERX09DATA[15] !== 1'bz) && PIPERX09DATA[15]; // rv 0 + assign PIPERX09DATA_in[16] = (PIPERX09DATA[16] !== 1'bz) && PIPERX09DATA[16]; // rv 0 + assign PIPERX09DATA_in[17] = (PIPERX09DATA[17] !== 1'bz) && PIPERX09DATA[17]; // rv 0 + assign PIPERX09DATA_in[18] = (PIPERX09DATA[18] !== 1'bz) && PIPERX09DATA[18]; // rv 0 + assign PIPERX09DATA_in[19] = (PIPERX09DATA[19] !== 1'bz) && PIPERX09DATA[19]; // rv 0 + assign PIPERX09DATA_in[1] = (PIPERX09DATA[1] !== 1'bz) && PIPERX09DATA[1]; // rv 0 + assign PIPERX09DATA_in[20] = (PIPERX09DATA[20] !== 1'bz) && PIPERX09DATA[20]; // rv 0 + assign PIPERX09DATA_in[21] = (PIPERX09DATA[21] !== 1'bz) && PIPERX09DATA[21]; // rv 0 + assign PIPERX09DATA_in[22] = (PIPERX09DATA[22] !== 1'bz) && PIPERX09DATA[22]; // rv 0 + assign PIPERX09DATA_in[23] = (PIPERX09DATA[23] !== 1'bz) && PIPERX09DATA[23]; // rv 0 + assign PIPERX09DATA_in[24] = (PIPERX09DATA[24] !== 1'bz) && PIPERX09DATA[24]; // rv 0 + assign PIPERX09DATA_in[25] = (PIPERX09DATA[25] !== 1'bz) && PIPERX09DATA[25]; // rv 0 + assign PIPERX09DATA_in[26] = (PIPERX09DATA[26] !== 1'bz) && PIPERX09DATA[26]; // rv 0 + assign PIPERX09DATA_in[27] = (PIPERX09DATA[27] !== 1'bz) && PIPERX09DATA[27]; // rv 0 + assign PIPERX09DATA_in[28] = (PIPERX09DATA[28] !== 1'bz) && PIPERX09DATA[28]; // rv 0 + assign PIPERX09DATA_in[29] = (PIPERX09DATA[29] !== 1'bz) && PIPERX09DATA[29]; // rv 0 + assign PIPERX09DATA_in[2] = (PIPERX09DATA[2] !== 1'bz) && PIPERX09DATA[2]; // rv 0 + assign PIPERX09DATA_in[30] = (PIPERX09DATA[30] !== 1'bz) && PIPERX09DATA[30]; // rv 0 + assign PIPERX09DATA_in[31] = (PIPERX09DATA[31] !== 1'bz) && PIPERX09DATA[31]; // rv 0 + assign PIPERX09DATA_in[3] = (PIPERX09DATA[3] !== 1'bz) && PIPERX09DATA[3]; // rv 0 + assign PIPERX09DATA_in[4] = (PIPERX09DATA[4] !== 1'bz) && PIPERX09DATA[4]; // rv 0 + assign PIPERX09DATA_in[5] = (PIPERX09DATA[5] !== 1'bz) && PIPERX09DATA[5]; // rv 0 + assign PIPERX09DATA_in[6] = (PIPERX09DATA[6] !== 1'bz) && PIPERX09DATA[6]; // rv 0 + assign PIPERX09DATA_in[7] = (PIPERX09DATA[7] !== 1'bz) && PIPERX09DATA[7]; // rv 0 + assign PIPERX09DATA_in[8] = (PIPERX09DATA[8] !== 1'bz) && PIPERX09DATA[8]; // rv 0 + assign PIPERX09DATA_in[9] = (PIPERX09DATA[9] !== 1'bz) && PIPERX09DATA[9]; // rv 0 + assign PIPERX09ELECIDLE_in = (PIPERX09ELECIDLE === 1'bz) || PIPERX09ELECIDLE; // rv 1 + assign PIPERX09EQDONE_in = (PIPERX09EQDONE !== 1'bz) && PIPERX09EQDONE; // rv 0 + assign PIPERX09EQLPADAPTDONE_in = (PIPERX09EQLPADAPTDONE !== 1'bz) && PIPERX09EQLPADAPTDONE; // rv 0 + assign PIPERX09EQLPLFFSSEL_in = (PIPERX09EQLPLFFSSEL !== 1'bz) && PIPERX09EQLPLFFSSEL; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX09EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX09EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX09EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX09EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX09EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX09EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX09EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX09EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX09EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX09EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX09EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX09EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX09EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX09EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX09EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX09EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX09EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX09EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX09PHYSTATUS_in = (PIPERX09PHYSTATUS === 1'bz) || PIPERX09PHYSTATUS; // rv 1 + assign PIPERX09STARTBLOCK_in[0] = (PIPERX09STARTBLOCK[0] !== 1'bz) && PIPERX09STARTBLOCK[0]; // rv 0 + assign PIPERX09STARTBLOCK_in[1] = (PIPERX09STARTBLOCK[1] !== 1'bz) && PIPERX09STARTBLOCK[1]; // rv 0 + assign PIPERX09STATUS_in[0] = (PIPERX09STATUS[0] !== 1'bz) && PIPERX09STATUS[0]; // rv 0 + assign PIPERX09STATUS_in[1] = (PIPERX09STATUS[1] !== 1'bz) && PIPERX09STATUS[1]; // rv 0 + assign PIPERX09STATUS_in[2] = (PIPERX09STATUS[2] !== 1'bz) && PIPERX09STATUS[2]; // rv 0 + assign PIPERX09SYNCHEADER_in[0] = (PIPERX09SYNCHEADER[0] !== 1'bz) && PIPERX09SYNCHEADER[0]; // rv 0 + assign PIPERX09SYNCHEADER_in[1] = (PIPERX09SYNCHEADER[1] !== 1'bz) && PIPERX09SYNCHEADER[1]; // rv 0 + assign PIPERX09VALID_in = (PIPERX09VALID !== 1'bz) && PIPERX09VALID; // rv 0 + assign PIPERX10CHARISK_in[0] = (PIPERX10CHARISK[0] === 1'bz) || PIPERX10CHARISK[0]; // rv 1 + assign PIPERX10CHARISK_in[1] = (PIPERX10CHARISK[1] === 1'bz) || PIPERX10CHARISK[1]; // rv 1 + assign PIPERX10DATAVALID_in = (PIPERX10DATAVALID !== 1'bz) && PIPERX10DATAVALID; // rv 0 + assign PIPERX10DATA_in[0] = (PIPERX10DATA[0] !== 1'bz) && PIPERX10DATA[0]; // rv 0 + assign PIPERX10DATA_in[10] = (PIPERX10DATA[10] !== 1'bz) && PIPERX10DATA[10]; // rv 0 + assign PIPERX10DATA_in[11] = (PIPERX10DATA[11] !== 1'bz) && PIPERX10DATA[11]; // rv 0 + assign PIPERX10DATA_in[12] = (PIPERX10DATA[12] !== 1'bz) && PIPERX10DATA[12]; // rv 0 + assign PIPERX10DATA_in[13] = (PIPERX10DATA[13] !== 1'bz) && PIPERX10DATA[13]; // rv 0 + assign PIPERX10DATA_in[14] = (PIPERX10DATA[14] !== 1'bz) && PIPERX10DATA[14]; // rv 0 + assign PIPERX10DATA_in[15] = (PIPERX10DATA[15] !== 1'bz) && PIPERX10DATA[15]; // rv 0 + assign PIPERX10DATA_in[16] = (PIPERX10DATA[16] !== 1'bz) && PIPERX10DATA[16]; // rv 0 + assign PIPERX10DATA_in[17] = (PIPERX10DATA[17] !== 1'bz) && PIPERX10DATA[17]; // rv 0 + assign PIPERX10DATA_in[18] = (PIPERX10DATA[18] !== 1'bz) && PIPERX10DATA[18]; // rv 0 + assign PIPERX10DATA_in[19] = (PIPERX10DATA[19] !== 1'bz) && PIPERX10DATA[19]; // rv 0 + assign PIPERX10DATA_in[1] = (PIPERX10DATA[1] !== 1'bz) && PIPERX10DATA[1]; // rv 0 + assign PIPERX10DATA_in[20] = (PIPERX10DATA[20] !== 1'bz) && PIPERX10DATA[20]; // rv 0 + assign PIPERX10DATA_in[21] = (PIPERX10DATA[21] !== 1'bz) && PIPERX10DATA[21]; // rv 0 + assign PIPERX10DATA_in[22] = (PIPERX10DATA[22] !== 1'bz) && PIPERX10DATA[22]; // rv 0 + assign PIPERX10DATA_in[23] = (PIPERX10DATA[23] !== 1'bz) && PIPERX10DATA[23]; // rv 0 + assign PIPERX10DATA_in[24] = (PIPERX10DATA[24] !== 1'bz) && PIPERX10DATA[24]; // rv 0 + assign PIPERX10DATA_in[25] = (PIPERX10DATA[25] !== 1'bz) && PIPERX10DATA[25]; // rv 0 + assign PIPERX10DATA_in[26] = (PIPERX10DATA[26] !== 1'bz) && PIPERX10DATA[26]; // rv 0 + assign PIPERX10DATA_in[27] = (PIPERX10DATA[27] !== 1'bz) && PIPERX10DATA[27]; // rv 0 + assign PIPERX10DATA_in[28] = (PIPERX10DATA[28] !== 1'bz) && PIPERX10DATA[28]; // rv 0 + assign PIPERX10DATA_in[29] = (PIPERX10DATA[29] !== 1'bz) && PIPERX10DATA[29]; // rv 0 + assign PIPERX10DATA_in[2] = (PIPERX10DATA[2] !== 1'bz) && PIPERX10DATA[2]; // rv 0 + assign PIPERX10DATA_in[30] = (PIPERX10DATA[30] !== 1'bz) && PIPERX10DATA[30]; // rv 0 + assign PIPERX10DATA_in[31] = (PIPERX10DATA[31] !== 1'bz) && PIPERX10DATA[31]; // rv 0 + assign PIPERX10DATA_in[3] = (PIPERX10DATA[3] !== 1'bz) && PIPERX10DATA[3]; // rv 0 + assign PIPERX10DATA_in[4] = (PIPERX10DATA[4] !== 1'bz) && PIPERX10DATA[4]; // rv 0 + assign PIPERX10DATA_in[5] = (PIPERX10DATA[5] !== 1'bz) && PIPERX10DATA[5]; // rv 0 + assign PIPERX10DATA_in[6] = (PIPERX10DATA[6] !== 1'bz) && PIPERX10DATA[6]; // rv 0 + assign PIPERX10DATA_in[7] = (PIPERX10DATA[7] !== 1'bz) && PIPERX10DATA[7]; // rv 0 + assign PIPERX10DATA_in[8] = (PIPERX10DATA[8] !== 1'bz) && PIPERX10DATA[8]; // rv 0 + assign PIPERX10DATA_in[9] = (PIPERX10DATA[9] !== 1'bz) && PIPERX10DATA[9]; // rv 0 + assign PIPERX10ELECIDLE_in = (PIPERX10ELECIDLE === 1'bz) || PIPERX10ELECIDLE; // rv 1 + assign PIPERX10EQDONE_in = (PIPERX10EQDONE !== 1'bz) && PIPERX10EQDONE; // rv 0 + assign PIPERX10EQLPADAPTDONE_in = (PIPERX10EQLPADAPTDONE !== 1'bz) && PIPERX10EQLPADAPTDONE; // rv 0 + assign PIPERX10EQLPLFFSSEL_in = (PIPERX10EQLPLFFSSEL !== 1'bz) && PIPERX10EQLPLFFSSEL; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX10EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX10EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX10EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX10EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX10EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX10EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX10EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX10EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX10EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX10EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX10EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX10EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX10EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX10EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX10EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX10EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX10EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX10EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX10PHYSTATUS_in = (PIPERX10PHYSTATUS === 1'bz) || PIPERX10PHYSTATUS; // rv 1 + assign PIPERX10STARTBLOCK_in[0] = (PIPERX10STARTBLOCK[0] !== 1'bz) && PIPERX10STARTBLOCK[0]; // rv 0 + assign PIPERX10STARTBLOCK_in[1] = (PIPERX10STARTBLOCK[1] !== 1'bz) && PIPERX10STARTBLOCK[1]; // rv 0 + assign PIPERX10STATUS_in[0] = (PIPERX10STATUS[0] !== 1'bz) && PIPERX10STATUS[0]; // rv 0 + assign PIPERX10STATUS_in[1] = (PIPERX10STATUS[1] !== 1'bz) && PIPERX10STATUS[1]; // rv 0 + assign PIPERX10STATUS_in[2] = (PIPERX10STATUS[2] !== 1'bz) && PIPERX10STATUS[2]; // rv 0 + assign PIPERX10SYNCHEADER_in[0] = (PIPERX10SYNCHEADER[0] !== 1'bz) && PIPERX10SYNCHEADER[0]; // rv 0 + assign PIPERX10SYNCHEADER_in[1] = (PIPERX10SYNCHEADER[1] !== 1'bz) && PIPERX10SYNCHEADER[1]; // rv 0 + assign PIPERX10VALID_in = (PIPERX10VALID !== 1'bz) && PIPERX10VALID; // rv 0 + assign PIPERX11CHARISK_in[0] = (PIPERX11CHARISK[0] === 1'bz) || PIPERX11CHARISK[0]; // rv 1 + assign PIPERX11CHARISK_in[1] = (PIPERX11CHARISK[1] === 1'bz) || PIPERX11CHARISK[1]; // rv 1 + assign PIPERX11DATAVALID_in = (PIPERX11DATAVALID !== 1'bz) && PIPERX11DATAVALID; // rv 0 + assign PIPERX11DATA_in[0] = (PIPERX11DATA[0] !== 1'bz) && PIPERX11DATA[0]; // rv 0 + assign PIPERX11DATA_in[10] = (PIPERX11DATA[10] !== 1'bz) && PIPERX11DATA[10]; // rv 0 + assign PIPERX11DATA_in[11] = (PIPERX11DATA[11] !== 1'bz) && PIPERX11DATA[11]; // rv 0 + assign PIPERX11DATA_in[12] = (PIPERX11DATA[12] !== 1'bz) && PIPERX11DATA[12]; // rv 0 + assign PIPERX11DATA_in[13] = (PIPERX11DATA[13] !== 1'bz) && PIPERX11DATA[13]; // rv 0 + assign PIPERX11DATA_in[14] = (PIPERX11DATA[14] !== 1'bz) && PIPERX11DATA[14]; // rv 0 + assign PIPERX11DATA_in[15] = (PIPERX11DATA[15] !== 1'bz) && PIPERX11DATA[15]; // rv 0 + assign PIPERX11DATA_in[16] = (PIPERX11DATA[16] !== 1'bz) && PIPERX11DATA[16]; // rv 0 + assign PIPERX11DATA_in[17] = (PIPERX11DATA[17] !== 1'bz) && PIPERX11DATA[17]; // rv 0 + assign PIPERX11DATA_in[18] = (PIPERX11DATA[18] !== 1'bz) && PIPERX11DATA[18]; // rv 0 + assign PIPERX11DATA_in[19] = (PIPERX11DATA[19] !== 1'bz) && PIPERX11DATA[19]; // rv 0 + assign PIPERX11DATA_in[1] = (PIPERX11DATA[1] !== 1'bz) && PIPERX11DATA[1]; // rv 0 + assign PIPERX11DATA_in[20] = (PIPERX11DATA[20] !== 1'bz) && PIPERX11DATA[20]; // rv 0 + assign PIPERX11DATA_in[21] = (PIPERX11DATA[21] !== 1'bz) && PIPERX11DATA[21]; // rv 0 + assign PIPERX11DATA_in[22] = (PIPERX11DATA[22] !== 1'bz) && PIPERX11DATA[22]; // rv 0 + assign PIPERX11DATA_in[23] = (PIPERX11DATA[23] !== 1'bz) && PIPERX11DATA[23]; // rv 0 + assign PIPERX11DATA_in[24] = (PIPERX11DATA[24] !== 1'bz) && PIPERX11DATA[24]; // rv 0 + assign PIPERX11DATA_in[25] = (PIPERX11DATA[25] !== 1'bz) && PIPERX11DATA[25]; // rv 0 + assign PIPERX11DATA_in[26] = (PIPERX11DATA[26] !== 1'bz) && PIPERX11DATA[26]; // rv 0 + assign PIPERX11DATA_in[27] = (PIPERX11DATA[27] !== 1'bz) && PIPERX11DATA[27]; // rv 0 + assign PIPERX11DATA_in[28] = (PIPERX11DATA[28] !== 1'bz) && PIPERX11DATA[28]; // rv 0 + assign PIPERX11DATA_in[29] = (PIPERX11DATA[29] !== 1'bz) && PIPERX11DATA[29]; // rv 0 + assign PIPERX11DATA_in[2] = (PIPERX11DATA[2] !== 1'bz) && PIPERX11DATA[2]; // rv 0 + assign PIPERX11DATA_in[30] = (PIPERX11DATA[30] !== 1'bz) && PIPERX11DATA[30]; // rv 0 + assign PIPERX11DATA_in[31] = (PIPERX11DATA[31] !== 1'bz) && PIPERX11DATA[31]; // rv 0 + assign PIPERX11DATA_in[3] = (PIPERX11DATA[3] !== 1'bz) && PIPERX11DATA[3]; // rv 0 + assign PIPERX11DATA_in[4] = (PIPERX11DATA[4] !== 1'bz) && PIPERX11DATA[4]; // rv 0 + assign PIPERX11DATA_in[5] = (PIPERX11DATA[5] !== 1'bz) && PIPERX11DATA[5]; // rv 0 + assign PIPERX11DATA_in[6] = (PIPERX11DATA[6] !== 1'bz) && PIPERX11DATA[6]; // rv 0 + assign PIPERX11DATA_in[7] = (PIPERX11DATA[7] !== 1'bz) && PIPERX11DATA[7]; // rv 0 + assign PIPERX11DATA_in[8] = (PIPERX11DATA[8] !== 1'bz) && PIPERX11DATA[8]; // rv 0 + assign PIPERX11DATA_in[9] = (PIPERX11DATA[9] !== 1'bz) && PIPERX11DATA[9]; // rv 0 + assign PIPERX11ELECIDLE_in = (PIPERX11ELECIDLE === 1'bz) || PIPERX11ELECIDLE; // rv 1 + assign PIPERX11EQDONE_in = (PIPERX11EQDONE !== 1'bz) && PIPERX11EQDONE; // rv 0 + assign PIPERX11EQLPADAPTDONE_in = (PIPERX11EQLPADAPTDONE !== 1'bz) && PIPERX11EQLPADAPTDONE; // rv 0 + assign PIPERX11EQLPLFFSSEL_in = (PIPERX11EQLPLFFSSEL !== 1'bz) && PIPERX11EQLPLFFSSEL; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX11EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX11EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX11EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX11EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX11EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX11EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX11EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX11EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX11EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX11EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX11EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX11EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX11EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX11EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX11EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX11EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX11EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX11EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX11PHYSTATUS_in = (PIPERX11PHYSTATUS === 1'bz) || PIPERX11PHYSTATUS; // rv 1 + assign PIPERX11STARTBLOCK_in[0] = (PIPERX11STARTBLOCK[0] !== 1'bz) && PIPERX11STARTBLOCK[0]; // rv 0 + assign PIPERX11STARTBLOCK_in[1] = (PIPERX11STARTBLOCK[1] !== 1'bz) && PIPERX11STARTBLOCK[1]; // rv 0 + assign PIPERX11STATUS_in[0] = (PIPERX11STATUS[0] !== 1'bz) && PIPERX11STATUS[0]; // rv 0 + assign PIPERX11STATUS_in[1] = (PIPERX11STATUS[1] !== 1'bz) && PIPERX11STATUS[1]; // rv 0 + assign PIPERX11STATUS_in[2] = (PIPERX11STATUS[2] !== 1'bz) && PIPERX11STATUS[2]; // rv 0 + assign PIPERX11SYNCHEADER_in[0] = (PIPERX11SYNCHEADER[0] !== 1'bz) && PIPERX11SYNCHEADER[0]; // rv 0 + assign PIPERX11SYNCHEADER_in[1] = (PIPERX11SYNCHEADER[1] !== 1'bz) && PIPERX11SYNCHEADER[1]; // rv 0 + assign PIPERX11VALID_in = (PIPERX11VALID !== 1'bz) && PIPERX11VALID; // rv 0 + assign PIPERX12CHARISK_in[0] = (PIPERX12CHARISK[0] === 1'bz) || PIPERX12CHARISK[0]; // rv 1 + assign PIPERX12CHARISK_in[1] = (PIPERX12CHARISK[1] === 1'bz) || PIPERX12CHARISK[1]; // rv 1 + assign PIPERX12DATAVALID_in = (PIPERX12DATAVALID !== 1'bz) && PIPERX12DATAVALID; // rv 0 + assign PIPERX12DATA_in[0] = (PIPERX12DATA[0] !== 1'bz) && PIPERX12DATA[0]; // rv 0 + assign PIPERX12DATA_in[10] = (PIPERX12DATA[10] !== 1'bz) && PIPERX12DATA[10]; // rv 0 + assign PIPERX12DATA_in[11] = (PIPERX12DATA[11] !== 1'bz) && PIPERX12DATA[11]; // rv 0 + assign PIPERX12DATA_in[12] = (PIPERX12DATA[12] !== 1'bz) && PIPERX12DATA[12]; // rv 0 + assign PIPERX12DATA_in[13] = (PIPERX12DATA[13] !== 1'bz) && PIPERX12DATA[13]; // rv 0 + assign PIPERX12DATA_in[14] = (PIPERX12DATA[14] !== 1'bz) && PIPERX12DATA[14]; // rv 0 + assign PIPERX12DATA_in[15] = (PIPERX12DATA[15] !== 1'bz) && PIPERX12DATA[15]; // rv 0 + assign PIPERX12DATA_in[16] = (PIPERX12DATA[16] !== 1'bz) && PIPERX12DATA[16]; // rv 0 + assign PIPERX12DATA_in[17] = (PIPERX12DATA[17] !== 1'bz) && PIPERX12DATA[17]; // rv 0 + assign PIPERX12DATA_in[18] = (PIPERX12DATA[18] !== 1'bz) && PIPERX12DATA[18]; // rv 0 + assign PIPERX12DATA_in[19] = (PIPERX12DATA[19] !== 1'bz) && PIPERX12DATA[19]; // rv 0 + assign PIPERX12DATA_in[1] = (PIPERX12DATA[1] !== 1'bz) && PIPERX12DATA[1]; // rv 0 + assign PIPERX12DATA_in[20] = (PIPERX12DATA[20] !== 1'bz) && PIPERX12DATA[20]; // rv 0 + assign PIPERX12DATA_in[21] = (PIPERX12DATA[21] !== 1'bz) && PIPERX12DATA[21]; // rv 0 + assign PIPERX12DATA_in[22] = (PIPERX12DATA[22] !== 1'bz) && PIPERX12DATA[22]; // rv 0 + assign PIPERX12DATA_in[23] = (PIPERX12DATA[23] !== 1'bz) && PIPERX12DATA[23]; // rv 0 + assign PIPERX12DATA_in[24] = (PIPERX12DATA[24] !== 1'bz) && PIPERX12DATA[24]; // rv 0 + assign PIPERX12DATA_in[25] = (PIPERX12DATA[25] !== 1'bz) && PIPERX12DATA[25]; // rv 0 + assign PIPERX12DATA_in[26] = (PIPERX12DATA[26] !== 1'bz) && PIPERX12DATA[26]; // rv 0 + assign PIPERX12DATA_in[27] = (PIPERX12DATA[27] !== 1'bz) && PIPERX12DATA[27]; // rv 0 + assign PIPERX12DATA_in[28] = (PIPERX12DATA[28] !== 1'bz) && PIPERX12DATA[28]; // rv 0 + assign PIPERX12DATA_in[29] = (PIPERX12DATA[29] !== 1'bz) && PIPERX12DATA[29]; // rv 0 + assign PIPERX12DATA_in[2] = (PIPERX12DATA[2] !== 1'bz) && PIPERX12DATA[2]; // rv 0 + assign PIPERX12DATA_in[30] = (PIPERX12DATA[30] !== 1'bz) && PIPERX12DATA[30]; // rv 0 + assign PIPERX12DATA_in[31] = (PIPERX12DATA[31] !== 1'bz) && PIPERX12DATA[31]; // rv 0 + assign PIPERX12DATA_in[3] = (PIPERX12DATA[3] !== 1'bz) && PIPERX12DATA[3]; // rv 0 + assign PIPERX12DATA_in[4] = (PIPERX12DATA[4] !== 1'bz) && PIPERX12DATA[4]; // rv 0 + assign PIPERX12DATA_in[5] = (PIPERX12DATA[5] !== 1'bz) && PIPERX12DATA[5]; // rv 0 + assign PIPERX12DATA_in[6] = (PIPERX12DATA[6] !== 1'bz) && PIPERX12DATA[6]; // rv 0 + assign PIPERX12DATA_in[7] = (PIPERX12DATA[7] !== 1'bz) && PIPERX12DATA[7]; // rv 0 + assign PIPERX12DATA_in[8] = (PIPERX12DATA[8] !== 1'bz) && PIPERX12DATA[8]; // rv 0 + assign PIPERX12DATA_in[9] = (PIPERX12DATA[9] !== 1'bz) && PIPERX12DATA[9]; // rv 0 + assign PIPERX12ELECIDLE_in = (PIPERX12ELECIDLE === 1'bz) || PIPERX12ELECIDLE; // rv 1 + assign PIPERX12EQDONE_in = (PIPERX12EQDONE !== 1'bz) && PIPERX12EQDONE; // rv 0 + assign PIPERX12EQLPADAPTDONE_in = (PIPERX12EQLPADAPTDONE !== 1'bz) && PIPERX12EQLPADAPTDONE; // rv 0 + assign PIPERX12EQLPLFFSSEL_in = (PIPERX12EQLPLFFSSEL !== 1'bz) && PIPERX12EQLPLFFSSEL; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX12EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX12EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX12EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX12EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX12EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX12EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX12EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX12EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX12EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX12EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX12EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX12EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX12EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX12EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX12EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX12EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX12EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX12EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX12PHYSTATUS_in = (PIPERX12PHYSTATUS === 1'bz) || PIPERX12PHYSTATUS; // rv 1 + assign PIPERX12STARTBLOCK_in[0] = (PIPERX12STARTBLOCK[0] !== 1'bz) && PIPERX12STARTBLOCK[0]; // rv 0 + assign PIPERX12STARTBLOCK_in[1] = (PIPERX12STARTBLOCK[1] !== 1'bz) && PIPERX12STARTBLOCK[1]; // rv 0 + assign PIPERX12STATUS_in[0] = (PIPERX12STATUS[0] !== 1'bz) && PIPERX12STATUS[0]; // rv 0 + assign PIPERX12STATUS_in[1] = (PIPERX12STATUS[1] !== 1'bz) && PIPERX12STATUS[1]; // rv 0 + assign PIPERX12STATUS_in[2] = (PIPERX12STATUS[2] !== 1'bz) && PIPERX12STATUS[2]; // rv 0 + assign PIPERX12SYNCHEADER_in[0] = (PIPERX12SYNCHEADER[0] !== 1'bz) && PIPERX12SYNCHEADER[0]; // rv 0 + assign PIPERX12SYNCHEADER_in[1] = (PIPERX12SYNCHEADER[1] !== 1'bz) && PIPERX12SYNCHEADER[1]; // rv 0 + assign PIPERX12VALID_in = (PIPERX12VALID !== 1'bz) && PIPERX12VALID; // rv 0 + assign PIPERX13CHARISK_in[0] = (PIPERX13CHARISK[0] === 1'bz) || PIPERX13CHARISK[0]; // rv 1 + assign PIPERX13CHARISK_in[1] = (PIPERX13CHARISK[1] === 1'bz) || PIPERX13CHARISK[1]; // rv 1 + assign PIPERX13DATAVALID_in = (PIPERX13DATAVALID !== 1'bz) && PIPERX13DATAVALID; // rv 0 + assign PIPERX13DATA_in[0] = (PIPERX13DATA[0] !== 1'bz) && PIPERX13DATA[0]; // rv 0 + assign PIPERX13DATA_in[10] = (PIPERX13DATA[10] !== 1'bz) && PIPERX13DATA[10]; // rv 0 + assign PIPERX13DATA_in[11] = (PIPERX13DATA[11] !== 1'bz) && PIPERX13DATA[11]; // rv 0 + assign PIPERX13DATA_in[12] = (PIPERX13DATA[12] !== 1'bz) && PIPERX13DATA[12]; // rv 0 + assign PIPERX13DATA_in[13] = (PIPERX13DATA[13] !== 1'bz) && PIPERX13DATA[13]; // rv 0 + assign PIPERX13DATA_in[14] = (PIPERX13DATA[14] !== 1'bz) && PIPERX13DATA[14]; // rv 0 + assign PIPERX13DATA_in[15] = (PIPERX13DATA[15] !== 1'bz) && PIPERX13DATA[15]; // rv 0 + assign PIPERX13DATA_in[16] = (PIPERX13DATA[16] !== 1'bz) && PIPERX13DATA[16]; // rv 0 + assign PIPERX13DATA_in[17] = (PIPERX13DATA[17] !== 1'bz) && PIPERX13DATA[17]; // rv 0 + assign PIPERX13DATA_in[18] = (PIPERX13DATA[18] !== 1'bz) && PIPERX13DATA[18]; // rv 0 + assign PIPERX13DATA_in[19] = (PIPERX13DATA[19] !== 1'bz) && PIPERX13DATA[19]; // rv 0 + assign PIPERX13DATA_in[1] = (PIPERX13DATA[1] !== 1'bz) && PIPERX13DATA[1]; // rv 0 + assign PIPERX13DATA_in[20] = (PIPERX13DATA[20] !== 1'bz) && PIPERX13DATA[20]; // rv 0 + assign PIPERX13DATA_in[21] = (PIPERX13DATA[21] !== 1'bz) && PIPERX13DATA[21]; // rv 0 + assign PIPERX13DATA_in[22] = (PIPERX13DATA[22] !== 1'bz) && PIPERX13DATA[22]; // rv 0 + assign PIPERX13DATA_in[23] = (PIPERX13DATA[23] !== 1'bz) && PIPERX13DATA[23]; // rv 0 + assign PIPERX13DATA_in[24] = (PIPERX13DATA[24] !== 1'bz) && PIPERX13DATA[24]; // rv 0 + assign PIPERX13DATA_in[25] = (PIPERX13DATA[25] !== 1'bz) && PIPERX13DATA[25]; // rv 0 + assign PIPERX13DATA_in[26] = (PIPERX13DATA[26] !== 1'bz) && PIPERX13DATA[26]; // rv 0 + assign PIPERX13DATA_in[27] = (PIPERX13DATA[27] !== 1'bz) && PIPERX13DATA[27]; // rv 0 + assign PIPERX13DATA_in[28] = (PIPERX13DATA[28] !== 1'bz) && PIPERX13DATA[28]; // rv 0 + assign PIPERX13DATA_in[29] = (PIPERX13DATA[29] !== 1'bz) && PIPERX13DATA[29]; // rv 0 + assign PIPERX13DATA_in[2] = (PIPERX13DATA[2] !== 1'bz) && PIPERX13DATA[2]; // rv 0 + assign PIPERX13DATA_in[30] = (PIPERX13DATA[30] !== 1'bz) && PIPERX13DATA[30]; // rv 0 + assign PIPERX13DATA_in[31] = (PIPERX13DATA[31] !== 1'bz) && PIPERX13DATA[31]; // rv 0 + assign PIPERX13DATA_in[3] = (PIPERX13DATA[3] !== 1'bz) && PIPERX13DATA[3]; // rv 0 + assign PIPERX13DATA_in[4] = (PIPERX13DATA[4] !== 1'bz) && PIPERX13DATA[4]; // rv 0 + assign PIPERX13DATA_in[5] = (PIPERX13DATA[5] !== 1'bz) && PIPERX13DATA[5]; // rv 0 + assign PIPERX13DATA_in[6] = (PIPERX13DATA[6] !== 1'bz) && PIPERX13DATA[6]; // rv 0 + assign PIPERX13DATA_in[7] = (PIPERX13DATA[7] !== 1'bz) && PIPERX13DATA[7]; // rv 0 + assign PIPERX13DATA_in[8] = (PIPERX13DATA[8] !== 1'bz) && PIPERX13DATA[8]; // rv 0 + assign PIPERX13DATA_in[9] = (PIPERX13DATA[9] !== 1'bz) && PIPERX13DATA[9]; // rv 0 + assign PIPERX13ELECIDLE_in = (PIPERX13ELECIDLE === 1'bz) || PIPERX13ELECIDLE; // rv 1 + assign PIPERX13EQDONE_in = (PIPERX13EQDONE !== 1'bz) && PIPERX13EQDONE; // rv 0 + assign PIPERX13EQLPADAPTDONE_in = (PIPERX13EQLPADAPTDONE !== 1'bz) && PIPERX13EQLPADAPTDONE; // rv 0 + assign PIPERX13EQLPLFFSSEL_in = (PIPERX13EQLPLFFSSEL !== 1'bz) && PIPERX13EQLPLFFSSEL; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX13EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX13EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX13EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX13EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX13EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX13EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX13EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX13EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX13EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX13EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX13EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX13EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX13EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX13EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX13EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX13EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX13EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX13EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX13PHYSTATUS_in = (PIPERX13PHYSTATUS === 1'bz) || PIPERX13PHYSTATUS; // rv 1 + assign PIPERX13STARTBLOCK_in[0] = (PIPERX13STARTBLOCK[0] !== 1'bz) && PIPERX13STARTBLOCK[0]; // rv 0 + assign PIPERX13STARTBLOCK_in[1] = (PIPERX13STARTBLOCK[1] !== 1'bz) && PIPERX13STARTBLOCK[1]; // rv 0 + assign PIPERX13STATUS_in[0] = (PIPERX13STATUS[0] !== 1'bz) && PIPERX13STATUS[0]; // rv 0 + assign PIPERX13STATUS_in[1] = (PIPERX13STATUS[1] !== 1'bz) && PIPERX13STATUS[1]; // rv 0 + assign PIPERX13STATUS_in[2] = (PIPERX13STATUS[2] !== 1'bz) && PIPERX13STATUS[2]; // rv 0 + assign PIPERX13SYNCHEADER_in[0] = (PIPERX13SYNCHEADER[0] !== 1'bz) && PIPERX13SYNCHEADER[0]; // rv 0 + assign PIPERX13SYNCHEADER_in[1] = (PIPERX13SYNCHEADER[1] !== 1'bz) && PIPERX13SYNCHEADER[1]; // rv 0 + assign PIPERX13VALID_in = (PIPERX13VALID !== 1'bz) && PIPERX13VALID; // rv 0 + assign PIPERX14CHARISK_in[0] = (PIPERX14CHARISK[0] === 1'bz) || PIPERX14CHARISK[0]; // rv 1 + assign PIPERX14CHARISK_in[1] = (PIPERX14CHARISK[1] === 1'bz) || PIPERX14CHARISK[1]; // rv 1 + assign PIPERX14DATAVALID_in = (PIPERX14DATAVALID !== 1'bz) && PIPERX14DATAVALID; // rv 0 + assign PIPERX14DATA_in[0] = (PIPERX14DATA[0] !== 1'bz) && PIPERX14DATA[0]; // rv 0 + assign PIPERX14DATA_in[10] = (PIPERX14DATA[10] !== 1'bz) && PIPERX14DATA[10]; // rv 0 + assign PIPERX14DATA_in[11] = (PIPERX14DATA[11] !== 1'bz) && PIPERX14DATA[11]; // rv 0 + assign PIPERX14DATA_in[12] = (PIPERX14DATA[12] !== 1'bz) && PIPERX14DATA[12]; // rv 0 + assign PIPERX14DATA_in[13] = (PIPERX14DATA[13] !== 1'bz) && PIPERX14DATA[13]; // rv 0 + assign PIPERX14DATA_in[14] = (PIPERX14DATA[14] !== 1'bz) && PIPERX14DATA[14]; // rv 0 + assign PIPERX14DATA_in[15] = (PIPERX14DATA[15] !== 1'bz) && PIPERX14DATA[15]; // rv 0 + assign PIPERX14DATA_in[16] = (PIPERX14DATA[16] !== 1'bz) && PIPERX14DATA[16]; // rv 0 + assign PIPERX14DATA_in[17] = (PIPERX14DATA[17] !== 1'bz) && PIPERX14DATA[17]; // rv 0 + assign PIPERX14DATA_in[18] = (PIPERX14DATA[18] !== 1'bz) && PIPERX14DATA[18]; // rv 0 + assign PIPERX14DATA_in[19] = (PIPERX14DATA[19] !== 1'bz) && PIPERX14DATA[19]; // rv 0 + assign PIPERX14DATA_in[1] = (PIPERX14DATA[1] !== 1'bz) && PIPERX14DATA[1]; // rv 0 + assign PIPERX14DATA_in[20] = (PIPERX14DATA[20] !== 1'bz) && PIPERX14DATA[20]; // rv 0 + assign PIPERX14DATA_in[21] = (PIPERX14DATA[21] !== 1'bz) && PIPERX14DATA[21]; // rv 0 + assign PIPERX14DATA_in[22] = (PIPERX14DATA[22] !== 1'bz) && PIPERX14DATA[22]; // rv 0 + assign PIPERX14DATA_in[23] = (PIPERX14DATA[23] !== 1'bz) && PIPERX14DATA[23]; // rv 0 + assign PIPERX14DATA_in[24] = (PIPERX14DATA[24] !== 1'bz) && PIPERX14DATA[24]; // rv 0 + assign PIPERX14DATA_in[25] = (PIPERX14DATA[25] !== 1'bz) && PIPERX14DATA[25]; // rv 0 + assign PIPERX14DATA_in[26] = (PIPERX14DATA[26] !== 1'bz) && PIPERX14DATA[26]; // rv 0 + assign PIPERX14DATA_in[27] = (PIPERX14DATA[27] !== 1'bz) && PIPERX14DATA[27]; // rv 0 + assign PIPERX14DATA_in[28] = (PIPERX14DATA[28] !== 1'bz) && PIPERX14DATA[28]; // rv 0 + assign PIPERX14DATA_in[29] = (PIPERX14DATA[29] !== 1'bz) && PIPERX14DATA[29]; // rv 0 + assign PIPERX14DATA_in[2] = (PIPERX14DATA[2] !== 1'bz) && PIPERX14DATA[2]; // rv 0 + assign PIPERX14DATA_in[30] = (PIPERX14DATA[30] !== 1'bz) && PIPERX14DATA[30]; // rv 0 + assign PIPERX14DATA_in[31] = (PIPERX14DATA[31] !== 1'bz) && PIPERX14DATA[31]; // rv 0 + assign PIPERX14DATA_in[3] = (PIPERX14DATA[3] !== 1'bz) && PIPERX14DATA[3]; // rv 0 + assign PIPERX14DATA_in[4] = (PIPERX14DATA[4] !== 1'bz) && PIPERX14DATA[4]; // rv 0 + assign PIPERX14DATA_in[5] = (PIPERX14DATA[5] !== 1'bz) && PIPERX14DATA[5]; // rv 0 + assign PIPERX14DATA_in[6] = (PIPERX14DATA[6] !== 1'bz) && PIPERX14DATA[6]; // rv 0 + assign PIPERX14DATA_in[7] = (PIPERX14DATA[7] !== 1'bz) && PIPERX14DATA[7]; // rv 0 + assign PIPERX14DATA_in[8] = (PIPERX14DATA[8] !== 1'bz) && PIPERX14DATA[8]; // rv 0 + assign PIPERX14DATA_in[9] = (PIPERX14DATA[9] !== 1'bz) && PIPERX14DATA[9]; // rv 0 + assign PIPERX14ELECIDLE_in = (PIPERX14ELECIDLE === 1'bz) || PIPERX14ELECIDLE; // rv 1 + assign PIPERX14EQDONE_in = (PIPERX14EQDONE !== 1'bz) && PIPERX14EQDONE; // rv 0 + assign PIPERX14EQLPADAPTDONE_in = (PIPERX14EQLPADAPTDONE !== 1'bz) && PIPERX14EQLPADAPTDONE; // rv 0 + assign PIPERX14EQLPLFFSSEL_in = (PIPERX14EQLPLFFSSEL !== 1'bz) && PIPERX14EQLPLFFSSEL; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX14EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX14EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX14EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX14EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX14EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX14EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX14EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX14EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX14EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX14EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX14EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX14EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX14EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX14EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX14EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX14EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX14EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX14EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX14PHYSTATUS_in = (PIPERX14PHYSTATUS === 1'bz) || PIPERX14PHYSTATUS; // rv 1 + assign PIPERX14STARTBLOCK_in[0] = (PIPERX14STARTBLOCK[0] !== 1'bz) && PIPERX14STARTBLOCK[0]; // rv 0 + assign PIPERX14STARTBLOCK_in[1] = (PIPERX14STARTBLOCK[1] !== 1'bz) && PIPERX14STARTBLOCK[1]; // rv 0 + assign PIPERX14STATUS_in[0] = (PIPERX14STATUS[0] !== 1'bz) && PIPERX14STATUS[0]; // rv 0 + assign PIPERX14STATUS_in[1] = (PIPERX14STATUS[1] !== 1'bz) && PIPERX14STATUS[1]; // rv 0 + assign PIPERX14STATUS_in[2] = (PIPERX14STATUS[2] !== 1'bz) && PIPERX14STATUS[2]; // rv 0 + assign PIPERX14SYNCHEADER_in[0] = (PIPERX14SYNCHEADER[0] !== 1'bz) && PIPERX14SYNCHEADER[0]; // rv 0 + assign PIPERX14SYNCHEADER_in[1] = (PIPERX14SYNCHEADER[1] !== 1'bz) && PIPERX14SYNCHEADER[1]; // rv 0 + assign PIPERX14VALID_in = (PIPERX14VALID !== 1'bz) && PIPERX14VALID; // rv 0 + assign PIPERX15CHARISK_in[0] = (PIPERX15CHARISK[0] === 1'bz) || PIPERX15CHARISK[0]; // rv 1 + assign PIPERX15CHARISK_in[1] = (PIPERX15CHARISK[1] === 1'bz) || PIPERX15CHARISK[1]; // rv 1 + assign PIPERX15DATAVALID_in = (PIPERX15DATAVALID !== 1'bz) && PIPERX15DATAVALID; // rv 0 + assign PIPERX15DATA_in[0] = (PIPERX15DATA[0] !== 1'bz) && PIPERX15DATA[0]; // rv 0 + assign PIPERX15DATA_in[10] = (PIPERX15DATA[10] !== 1'bz) && PIPERX15DATA[10]; // rv 0 + assign PIPERX15DATA_in[11] = (PIPERX15DATA[11] !== 1'bz) && PIPERX15DATA[11]; // rv 0 + assign PIPERX15DATA_in[12] = (PIPERX15DATA[12] !== 1'bz) && PIPERX15DATA[12]; // rv 0 + assign PIPERX15DATA_in[13] = (PIPERX15DATA[13] !== 1'bz) && PIPERX15DATA[13]; // rv 0 + assign PIPERX15DATA_in[14] = (PIPERX15DATA[14] !== 1'bz) && PIPERX15DATA[14]; // rv 0 + assign PIPERX15DATA_in[15] = (PIPERX15DATA[15] !== 1'bz) && PIPERX15DATA[15]; // rv 0 + assign PIPERX15DATA_in[16] = (PIPERX15DATA[16] !== 1'bz) && PIPERX15DATA[16]; // rv 0 + assign PIPERX15DATA_in[17] = (PIPERX15DATA[17] !== 1'bz) && PIPERX15DATA[17]; // rv 0 + assign PIPERX15DATA_in[18] = (PIPERX15DATA[18] !== 1'bz) && PIPERX15DATA[18]; // rv 0 + assign PIPERX15DATA_in[19] = (PIPERX15DATA[19] !== 1'bz) && PIPERX15DATA[19]; // rv 0 + assign PIPERX15DATA_in[1] = (PIPERX15DATA[1] !== 1'bz) && PIPERX15DATA[1]; // rv 0 + assign PIPERX15DATA_in[20] = (PIPERX15DATA[20] !== 1'bz) && PIPERX15DATA[20]; // rv 0 + assign PIPERX15DATA_in[21] = (PIPERX15DATA[21] !== 1'bz) && PIPERX15DATA[21]; // rv 0 + assign PIPERX15DATA_in[22] = (PIPERX15DATA[22] !== 1'bz) && PIPERX15DATA[22]; // rv 0 + assign PIPERX15DATA_in[23] = (PIPERX15DATA[23] !== 1'bz) && PIPERX15DATA[23]; // rv 0 + assign PIPERX15DATA_in[24] = (PIPERX15DATA[24] !== 1'bz) && PIPERX15DATA[24]; // rv 0 + assign PIPERX15DATA_in[25] = (PIPERX15DATA[25] !== 1'bz) && PIPERX15DATA[25]; // rv 0 + assign PIPERX15DATA_in[26] = (PIPERX15DATA[26] !== 1'bz) && PIPERX15DATA[26]; // rv 0 + assign PIPERX15DATA_in[27] = (PIPERX15DATA[27] !== 1'bz) && PIPERX15DATA[27]; // rv 0 + assign PIPERX15DATA_in[28] = (PIPERX15DATA[28] !== 1'bz) && PIPERX15DATA[28]; // rv 0 + assign PIPERX15DATA_in[29] = (PIPERX15DATA[29] !== 1'bz) && PIPERX15DATA[29]; // rv 0 + assign PIPERX15DATA_in[2] = (PIPERX15DATA[2] !== 1'bz) && PIPERX15DATA[2]; // rv 0 + assign PIPERX15DATA_in[30] = (PIPERX15DATA[30] !== 1'bz) && PIPERX15DATA[30]; // rv 0 + assign PIPERX15DATA_in[31] = (PIPERX15DATA[31] !== 1'bz) && PIPERX15DATA[31]; // rv 0 + assign PIPERX15DATA_in[3] = (PIPERX15DATA[3] !== 1'bz) && PIPERX15DATA[3]; // rv 0 + assign PIPERX15DATA_in[4] = (PIPERX15DATA[4] !== 1'bz) && PIPERX15DATA[4]; // rv 0 + assign PIPERX15DATA_in[5] = (PIPERX15DATA[5] !== 1'bz) && PIPERX15DATA[5]; // rv 0 + assign PIPERX15DATA_in[6] = (PIPERX15DATA[6] !== 1'bz) && PIPERX15DATA[6]; // rv 0 + assign PIPERX15DATA_in[7] = (PIPERX15DATA[7] !== 1'bz) && PIPERX15DATA[7]; // rv 0 + assign PIPERX15DATA_in[8] = (PIPERX15DATA[8] !== 1'bz) && PIPERX15DATA[8]; // rv 0 + assign PIPERX15DATA_in[9] = (PIPERX15DATA[9] !== 1'bz) && PIPERX15DATA[9]; // rv 0 + assign PIPERX15ELECIDLE_in = (PIPERX15ELECIDLE === 1'bz) || PIPERX15ELECIDLE; // rv 1 + assign PIPERX15EQDONE_in = (PIPERX15EQDONE !== 1'bz) && PIPERX15EQDONE; // rv 0 + assign PIPERX15EQLPADAPTDONE_in = (PIPERX15EQLPADAPTDONE !== 1'bz) && PIPERX15EQLPADAPTDONE; // rv 0 + assign PIPERX15EQLPLFFSSEL_in = (PIPERX15EQLPLFFSSEL !== 1'bz) && PIPERX15EQLPLFFSSEL; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX15EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX15EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX15EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX15EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX15EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX15EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX15EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX15EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX15EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX15EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX15EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX15EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX15EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX15EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX15EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX15EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX15EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX15EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX15PHYSTATUS_in = (PIPERX15PHYSTATUS === 1'bz) || PIPERX15PHYSTATUS; // rv 1 + assign PIPERX15STARTBLOCK_in[0] = (PIPERX15STARTBLOCK[0] !== 1'bz) && PIPERX15STARTBLOCK[0]; // rv 0 + assign PIPERX15STARTBLOCK_in[1] = (PIPERX15STARTBLOCK[1] !== 1'bz) && PIPERX15STARTBLOCK[1]; // rv 0 + assign PIPERX15STATUS_in[0] = (PIPERX15STATUS[0] !== 1'bz) && PIPERX15STATUS[0]; // rv 0 + assign PIPERX15STATUS_in[1] = (PIPERX15STATUS[1] !== 1'bz) && PIPERX15STATUS[1]; // rv 0 + assign PIPERX15STATUS_in[2] = (PIPERX15STATUS[2] !== 1'bz) && PIPERX15STATUS[2]; // rv 0 + assign PIPERX15SYNCHEADER_in[0] = (PIPERX15SYNCHEADER[0] !== 1'bz) && PIPERX15SYNCHEADER[0]; // rv 0 + assign PIPERX15SYNCHEADER_in[1] = (PIPERX15SYNCHEADER[1] !== 1'bz) && PIPERX15SYNCHEADER[1]; // rv 0 + assign PIPERX15VALID_in = (PIPERX15VALID !== 1'bz) && PIPERX15VALID; // rv 0 + assign PIPETX00EQCOEFF_in[0] = (PIPETX00EQCOEFF[0] !== 1'bz) && PIPETX00EQCOEFF[0]; // rv 0 + assign PIPETX00EQCOEFF_in[10] = (PIPETX00EQCOEFF[10] !== 1'bz) && PIPETX00EQCOEFF[10]; // rv 0 + assign PIPETX00EQCOEFF_in[11] = (PIPETX00EQCOEFF[11] !== 1'bz) && PIPETX00EQCOEFF[11]; // rv 0 + assign PIPETX00EQCOEFF_in[12] = (PIPETX00EQCOEFF[12] !== 1'bz) && PIPETX00EQCOEFF[12]; // rv 0 + assign PIPETX00EQCOEFF_in[13] = (PIPETX00EQCOEFF[13] !== 1'bz) && PIPETX00EQCOEFF[13]; // rv 0 + assign PIPETX00EQCOEFF_in[14] = (PIPETX00EQCOEFF[14] !== 1'bz) && PIPETX00EQCOEFF[14]; // rv 0 + assign PIPETX00EQCOEFF_in[15] = (PIPETX00EQCOEFF[15] !== 1'bz) && PIPETX00EQCOEFF[15]; // rv 0 + assign PIPETX00EQCOEFF_in[16] = (PIPETX00EQCOEFF[16] !== 1'bz) && PIPETX00EQCOEFF[16]; // rv 0 + assign PIPETX00EQCOEFF_in[17] = (PIPETX00EQCOEFF[17] !== 1'bz) && PIPETX00EQCOEFF[17]; // rv 0 + assign PIPETX00EQCOEFF_in[1] = (PIPETX00EQCOEFF[1] !== 1'bz) && PIPETX00EQCOEFF[1]; // rv 0 + assign PIPETX00EQCOEFF_in[2] = (PIPETX00EQCOEFF[2] !== 1'bz) && PIPETX00EQCOEFF[2]; // rv 0 + assign PIPETX00EQCOEFF_in[3] = (PIPETX00EQCOEFF[3] !== 1'bz) && PIPETX00EQCOEFF[3]; // rv 0 + assign PIPETX00EQCOEFF_in[4] = (PIPETX00EQCOEFF[4] !== 1'bz) && PIPETX00EQCOEFF[4]; // rv 0 + assign PIPETX00EQCOEFF_in[5] = (PIPETX00EQCOEFF[5] !== 1'bz) && PIPETX00EQCOEFF[5]; // rv 0 + assign PIPETX00EQCOEFF_in[6] = (PIPETX00EQCOEFF[6] !== 1'bz) && PIPETX00EQCOEFF[6]; // rv 0 + assign PIPETX00EQCOEFF_in[7] = (PIPETX00EQCOEFF[7] !== 1'bz) && PIPETX00EQCOEFF[7]; // rv 0 + assign PIPETX00EQCOEFF_in[8] = (PIPETX00EQCOEFF[8] !== 1'bz) && PIPETX00EQCOEFF[8]; // rv 0 + assign PIPETX00EQCOEFF_in[9] = (PIPETX00EQCOEFF[9] !== 1'bz) && PIPETX00EQCOEFF[9]; // rv 0 + assign PIPETX00EQDONE_in = (PIPETX00EQDONE !== 1'bz) && PIPETX00EQDONE; // rv 0 + assign PIPETX01EQCOEFF_in[0] = (PIPETX01EQCOEFF[0] !== 1'bz) && PIPETX01EQCOEFF[0]; // rv 0 + assign PIPETX01EQCOEFF_in[10] = (PIPETX01EQCOEFF[10] !== 1'bz) && PIPETX01EQCOEFF[10]; // rv 0 + assign PIPETX01EQCOEFF_in[11] = (PIPETX01EQCOEFF[11] !== 1'bz) && PIPETX01EQCOEFF[11]; // rv 0 + assign PIPETX01EQCOEFF_in[12] = (PIPETX01EQCOEFF[12] !== 1'bz) && PIPETX01EQCOEFF[12]; // rv 0 + assign PIPETX01EQCOEFF_in[13] = (PIPETX01EQCOEFF[13] !== 1'bz) && PIPETX01EQCOEFF[13]; // rv 0 + assign PIPETX01EQCOEFF_in[14] = (PIPETX01EQCOEFF[14] !== 1'bz) && PIPETX01EQCOEFF[14]; // rv 0 + assign PIPETX01EQCOEFF_in[15] = (PIPETX01EQCOEFF[15] !== 1'bz) && PIPETX01EQCOEFF[15]; // rv 0 + assign PIPETX01EQCOEFF_in[16] = (PIPETX01EQCOEFF[16] !== 1'bz) && PIPETX01EQCOEFF[16]; // rv 0 + assign PIPETX01EQCOEFF_in[17] = (PIPETX01EQCOEFF[17] !== 1'bz) && PIPETX01EQCOEFF[17]; // rv 0 + assign PIPETX01EQCOEFF_in[1] = (PIPETX01EQCOEFF[1] !== 1'bz) && PIPETX01EQCOEFF[1]; // rv 0 + assign PIPETX01EQCOEFF_in[2] = (PIPETX01EQCOEFF[2] !== 1'bz) && PIPETX01EQCOEFF[2]; // rv 0 + assign PIPETX01EQCOEFF_in[3] = (PIPETX01EQCOEFF[3] !== 1'bz) && PIPETX01EQCOEFF[3]; // rv 0 + assign PIPETX01EQCOEFF_in[4] = (PIPETX01EQCOEFF[4] !== 1'bz) && PIPETX01EQCOEFF[4]; // rv 0 + assign PIPETX01EQCOEFF_in[5] = (PIPETX01EQCOEFF[5] !== 1'bz) && PIPETX01EQCOEFF[5]; // rv 0 + assign PIPETX01EQCOEFF_in[6] = (PIPETX01EQCOEFF[6] !== 1'bz) && PIPETX01EQCOEFF[6]; // rv 0 + assign PIPETX01EQCOEFF_in[7] = (PIPETX01EQCOEFF[7] !== 1'bz) && PIPETX01EQCOEFF[7]; // rv 0 + assign PIPETX01EQCOEFF_in[8] = (PIPETX01EQCOEFF[8] !== 1'bz) && PIPETX01EQCOEFF[8]; // rv 0 + assign PIPETX01EQCOEFF_in[9] = (PIPETX01EQCOEFF[9] !== 1'bz) && PIPETX01EQCOEFF[9]; // rv 0 + assign PIPETX01EQDONE_in = (PIPETX01EQDONE !== 1'bz) && PIPETX01EQDONE; // rv 0 + assign PIPETX02EQCOEFF_in[0] = (PIPETX02EQCOEFF[0] !== 1'bz) && PIPETX02EQCOEFF[0]; // rv 0 + assign PIPETX02EQCOEFF_in[10] = (PIPETX02EQCOEFF[10] !== 1'bz) && PIPETX02EQCOEFF[10]; // rv 0 + assign PIPETX02EQCOEFF_in[11] = (PIPETX02EQCOEFF[11] !== 1'bz) && PIPETX02EQCOEFF[11]; // rv 0 + assign PIPETX02EQCOEFF_in[12] = (PIPETX02EQCOEFF[12] !== 1'bz) && PIPETX02EQCOEFF[12]; // rv 0 + assign PIPETX02EQCOEFF_in[13] = (PIPETX02EQCOEFF[13] !== 1'bz) && PIPETX02EQCOEFF[13]; // rv 0 + assign PIPETX02EQCOEFF_in[14] = (PIPETX02EQCOEFF[14] !== 1'bz) && PIPETX02EQCOEFF[14]; // rv 0 + assign PIPETX02EQCOEFF_in[15] = (PIPETX02EQCOEFF[15] !== 1'bz) && PIPETX02EQCOEFF[15]; // rv 0 + assign PIPETX02EQCOEFF_in[16] = (PIPETX02EQCOEFF[16] !== 1'bz) && PIPETX02EQCOEFF[16]; // rv 0 + assign PIPETX02EQCOEFF_in[17] = (PIPETX02EQCOEFF[17] !== 1'bz) && PIPETX02EQCOEFF[17]; // rv 0 + assign PIPETX02EQCOEFF_in[1] = (PIPETX02EQCOEFF[1] !== 1'bz) && PIPETX02EQCOEFF[1]; // rv 0 + assign PIPETX02EQCOEFF_in[2] = (PIPETX02EQCOEFF[2] !== 1'bz) && PIPETX02EQCOEFF[2]; // rv 0 + assign PIPETX02EQCOEFF_in[3] = (PIPETX02EQCOEFF[3] !== 1'bz) && PIPETX02EQCOEFF[3]; // rv 0 + assign PIPETX02EQCOEFF_in[4] = (PIPETX02EQCOEFF[4] !== 1'bz) && PIPETX02EQCOEFF[4]; // rv 0 + assign PIPETX02EQCOEFF_in[5] = (PIPETX02EQCOEFF[5] !== 1'bz) && PIPETX02EQCOEFF[5]; // rv 0 + assign PIPETX02EQCOEFF_in[6] = (PIPETX02EQCOEFF[6] !== 1'bz) && PIPETX02EQCOEFF[6]; // rv 0 + assign PIPETX02EQCOEFF_in[7] = (PIPETX02EQCOEFF[7] !== 1'bz) && PIPETX02EQCOEFF[7]; // rv 0 + assign PIPETX02EQCOEFF_in[8] = (PIPETX02EQCOEFF[8] !== 1'bz) && PIPETX02EQCOEFF[8]; // rv 0 + assign PIPETX02EQCOEFF_in[9] = (PIPETX02EQCOEFF[9] !== 1'bz) && PIPETX02EQCOEFF[9]; // rv 0 + assign PIPETX02EQDONE_in = (PIPETX02EQDONE !== 1'bz) && PIPETX02EQDONE; // rv 0 + assign PIPETX03EQCOEFF_in[0] = (PIPETX03EQCOEFF[0] !== 1'bz) && PIPETX03EQCOEFF[0]; // rv 0 + assign PIPETX03EQCOEFF_in[10] = (PIPETX03EQCOEFF[10] !== 1'bz) && PIPETX03EQCOEFF[10]; // rv 0 + assign PIPETX03EQCOEFF_in[11] = (PIPETX03EQCOEFF[11] !== 1'bz) && PIPETX03EQCOEFF[11]; // rv 0 + assign PIPETX03EQCOEFF_in[12] = (PIPETX03EQCOEFF[12] !== 1'bz) && PIPETX03EQCOEFF[12]; // rv 0 + assign PIPETX03EQCOEFF_in[13] = (PIPETX03EQCOEFF[13] !== 1'bz) && PIPETX03EQCOEFF[13]; // rv 0 + assign PIPETX03EQCOEFF_in[14] = (PIPETX03EQCOEFF[14] !== 1'bz) && PIPETX03EQCOEFF[14]; // rv 0 + assign PIPETX03EQCOEFF_in[15] = (PIPETX03EQCOEFF[15] !== 1'bz) && PIPETX03EQCOEFF[15]; // rv 0 + assign PIPETX03EQCOEFF_in[16] = (PIPETX03EQCOEFF[16] !== 1'bz) && PIPETX03EQCOEFF[16]; // rv 0 + assign PIPETX03EQCOEFF_in[17] = (PIPETX03EQCOEFF[17] !== 1'bz) && PIPETX03EQCOEFF[17]; // rv 0 + assign PIPETX03EQCOEFF_in[1] = (PIPETX03EQCOEFF[1] !== 1'bz) && PIPETX03EQCOEFF[1]; // rv 0 + assign PIPETX03EQCOEFF_in[2] = (PIPETX03EQCOEFF[2] !== 1'bz) && PIPETX03EQCOEFF[2]; // rv 0 + assign PIPETX03EQCOEFF_in[3] = (PIPETX03EQCOEFF[3] !== 1'bz) && PIPETX03EQCOEFF[3]; // rv 0 + assign PIPETX03EQCOEFF_in[4] = (PIPETX03EQCOEFF[4] !== 1'bz) && PIPETX03EQCOEFF[4]; // rv 0 + assign PIPETX03EQCOEFF_in[5] = (PIPETX03EQCOEFF[5] !== 1'bz) && PIPETX03EQCOEFF[5]; // rv 0 + assign PIPETX03EQCOEFF_in[6] = (PIPETX03EQCOEFF[6] !== 1'bz) && PIPETX03EQCOEFF[6]; // rv 0 + assign PIPETX03EQCOEFF_in[7] = (PIPETX03EQCOEFF[7] !== 1'bz) && PIPETX03EQCOEFF[7]; // rv 0 + assign PIPETX03EQCOEFF_in[8] = (PIPETX03EQCOEFF[8] !== 1'bz) && PIPETX03EQCOEFF[8]; // rv 0 + assign PIPETX03EQCOEFF_in[9] = (PIPETX03EQCOEFF[9] !== 1'bz) && PIPETX03EQCOEFF[9]; // rv 0 + assign PIPETX03EQDONE_in = (PIPETX03EQDONE !== 1'bz) && PIPETX03EQDONE; // rv 0 + assign PIPETX04EQCOEFF_in[0] = (PIPETX04EQCOEFF[0] !== 1'bz) && PIPETX04EQCOEFF[0]; // rv 0 + assign PIPETX04EQCOEFF_in[10] = (PIPETX04EQCOEFF[10] !== 1'bz) && PIPETX04EQCOEFF[10]; // rv 0 + assign PIPETX04EQCOEFF_in[11] = (PIPETX04EQCOEFF[11] !== 1'bz) && PIPETX04EQCOEFF[11]; // rv 0 + assign PIPETX04EQCOEFF_in[12] = (PIPETX04EQCOEFF[12] !== 1'bz) && PIPETX04EQCOEFF[12]; // rv 0 + assign PIPETX04EQCOEFF_in[13] = (PIPETX04EQCOEFF[13] !== 1'bz) && PIPETX04EQCOEFF[13]; // rv 0 + assign PIPETX04EQCOEFF_in[14] = (PIPETX04EQCOEFF[14] !== 1'bz) && PIPETX04EQCOEFF[14]; // rv 0 + assign PIPETX04EQCOEFF_in[15] = (PIPETX04EQCOEFF[15] !== 1'bz) && PIPETX04EQCOEFF[15]; // rv 0 + assign PIPETX04EQCOEFF_in[16] = (PIPETX04EQCOEFF[16] !== 1'bz) && PIPETX04EQCOEFF[16]; // rv 0 + assign PIPETX04EQCOEFF_in[17] = (PIPETX04EQCOEFF[17] !== 1'bz) && PIPETX04EQCOEFF[17]; // rv 0 + assign PIPETX04EQCOEFF_in[1] = (PIPETX04EQCOEFF[1] !== 1'bz) && PIPETX04EQCOEFF[1]; // rv 0 + assign PIPETX04EQCOEFF_in[2] = (PIPETX04EQCOEFF[2] !== 1'bz) && PIPETX04EQCOEFF[2]; // rv 0 + assign PIPETX04EQCOEFF_in[3] = (PIPETX04EQCOEFF[3] !== 1'bz) && PIPETX04EQCOEFF[3]; // rv 0 + assign PIPETX04EQCOEFF_in[4] = (PIPETX04EQCOEFF[4] !== 1'bz) && PIPETX04EQCOEFF[4]; // rv 0 + assign PIPETX04EQCOEFF_in[5] = (PIPETX04EQCOEFF[5] !== 1'bz) && PIPETX04EQCOEFF[5]; // rv 0 + assign PIPETX04EQCOEFF_in[6] = (PIPETX04EQCOEFF[6] !== 1'bz) && PIPETX04EQCOEFF[6]; // rv 0 + assign PIPETX04EQCOEFF_in[7] = (PIPETX04EQCOEFF[7] !== 1'bz) && PIPETX04EQCOEFF[7]; // rv 0 + assign PIPETX04EQCOEFF_in[8] = (PIPETX04EQCOEFF[8] !== 1'bz) && PIPETX04EQCOEFF[8]; // rv 0 + assign PIPETX04EQCOEFF_in[9] = (PIPETX04EQCOEFF[9] !== 1'bz) && PIPETX04EQCOEFF[9]; // rv 0 + assign PIPETX04EQDONE_in = (PIPETX04EQDONE !== 1'bz) && PIPETX04EQDONE; // rv 0 + assign PIPETX05EQCOEFF_in[0] = (PIPETX05EQCOEFF[0] !== 1'bz) && PIPETX05EQCOEFF[0]; // rv 0 + assign PIPETX05EQCOEFF_in[10] = (PIPETX05EQCOEFF[10] !== 1'bz) && PIPETX05EQCOEFF[10]; // rv 0 + assign PIPETX05EQCOEFF_in[11] = (PIPETX05EQCOEFF[11] !== 1'bz) && PIPETX05EQCOEFF[11]; // rv 0 + assign PIPETX05EQCOEFF_in[12] = (PIPETX05EQCOEFF[12] !== 1'bz) && PIPETX05EQCOEFF[12]; // rv 0 + assign PIPETX05EQCOEFF_in[13] = (PIPETX05EQCOEFF[13] !== 1'bz) && PIPETX05EQCOEFF[13]; // rv 0 + assign PIPETX05EQCOEFF_in[14] = (PIPETX05EQCOEFF[14] !== 1'bz) && PIPETX05EQCOEFF[14]; // rv 0 + assign PIPETX05EQCOEFF_in[15] = (PIPETX05EQCOEFF[15] !== 1'bz) && PIPETX05EQCOEFF[15]; // rv 0 + assign PIPETX05EQCOEFF_in[16] = (PIPETX05EQCOEFF[16] !== 1'bz) && PIPETX05EQCOEFF[16]; // rv 0 + assign PIPETX05EQCOEFF_in[17] = (PIPETX05EQCOEFF[17] !== 1'bz) && PIPETX05EQCOEFF[17]; // rv 0 + assign PIPETX05EQCOEFF_in[1] = (PIPETX05EQCOEFF[1] !== 1'bz) && PIPETX05EQCOEFF[1]; // rv 0 + assign PIPETX05EQCOEFF_in[2] = (PIPETX05EQCOEFF[2] !== 1'bz) && PIPETX05EQCOEFF[2]; // rv 0 + assign PIPETX05EQCOEFF_in[3] = (PIPETX05EQCOEFF[3] !== 1'bz) && PIPETX05EQCOEFF[3]; // rv 0 + assign PIPETX05EQCOEFF_in[4] = (PIPETX05EQCOEFF[4] !== 1'bz) && PIPETX05EQCOEFF[4]; // rv 0 + assign PIPETX05EQCOEFF_in[5] = (PIPETX05EQCOEFF[5] !== 1'bz) && PIPETX05EQCOEFF[5]; // rv 0 + assign PIPETX05EQCOEFF_in[6] = (PIPETX05EQCOEFF[6] !== 1'bz) && PIPETX05EQCOEFF[6]; // rv 0 + assign PIPETX05EQCOEFF_in[7] = (PIPETX05EQCOEFF[7] !== 1'bz) && PIPETX05EQCOEFF[7]; // rv 0 + assign PIPETX05EQCOEFF_in[8] = (PIPETX05EQCOEFF[8] !== 1'bz) && PIPETX05EQCOEFF[8]; // rv 0 + assign PIPETX05EQCOEFF_in[9] = (PIPETX05EQCOEFF[9] !== 1'bz) && PIPETX05EQCOEFF[9]; // rv 0 + assign PIPETX05EQDONE_in = (PIPETX05EQDONE !== 1'bz) && PIPETX05EQDONE; // rv 0 + assign PIPETX06EQCOEFF_in[0] = (PIPETX06EQCOEFF[0] !== 1'bz) && PIPETX06EQCOEFF[0]; // rv 0 + assign PIPETX06EQCOEFF_in[10] = (PIPETX06EQCOEFF[10] !== 1'bz) && PIPETX06EQCOEFF[10]; // rv 0 + assign PIPETX06EQCOEFF_in[11] = (PIPETX06EQCOEFF[11] !== 1'bz) && PIPETX06EQCOEFF[11]; // rv 0 + assign PIPETX06EQCOEFF_in[12] = (PIPETX06EQCOEFF[12] !== 1'bz) && PIPETX06EQCOEFF[12]; // rv 0 + assign PIPETX06EQCOEFF_in[13] = (PIPETX06EQCOEFF[13] !== 1'bz) && PIPETX06EQCOEFF[13]; // rv 0 + assign PIPETX06EQCOEFF_in[14] = (PIPETX06EQCOEFF[14] !== 1'bz) && PIPETX06EQCOEFF[14]; // rv 0 + assign PIPETX06EQCOEFF_in[15] = (PIPETX06EQCOEFF[15] !== 1'bz) && PIPETX06EQCOEFF[15]; // rv 0 + assign PIPETX06EQCOEFF_in[16] = (PIPETX06EQCOEFF[16] !== 1'bz) && PIPETX06EQCOEFF[16]; // rv 0 + assign PIPETX06EQCOEFF_in[17] = (PIPETX06EQCOEFF[17] !== 1'bz) && PIPETX06EQCOEFF[17]; // rv 0 + assign PIPETX06EQCOEFF_in[1] = (PIPETX06EQCOEFF[1] !== 1'bz) && PIPETX06EQCOEFF[1]; // rv 0 + assign PIPETX06EQCOEFF_in[2] = (PIPETX06EQCOEFF[2] !== 1'bz) && PIPETX06EQCOEFF[2]; // rv 0 + assign PIPETX06EQCOEFF_in[3] = (PIPETX06EQCOEFF[3] !== 1'bz) && PIPETX06EQCOEFF[3]; // rv 0 + assign PIPETX06EQCOEFF_in[4] = (PIPETX06EQCOEFF[4] !== 1'bz) && PIPETX06EQCOEFF[4]; // rv 0 + assign PIPETX06EQCOEFF_in[5] = (PIPETX06EQCOEFF[5] !== 1'bz) && PIPETX06EQCOEFF[5]; // rv 0 + assign PIPETX06EQCOEFF_in[6] = (PIPETX06EQCOEFF[6] !== 1'bz) && PIPETX06EQCOEFF[6]; // rv 0 + assign PIPETX06EQCOEFF_in[7] = (PIPETX06EQCOEFF[7] !== 1'bz) && PIPETX06EQCOEFF[7]; // rv 0 + assign PIPETX06EQCOEFF_in[8] = (PIPETX06EQCOEFF[8] !== 1'bz) && PIPETX06EQCOEFF[8]; // rv 0 + assign PIPETX06EQCOEFF_in[9] = (PIPETX06EQCOEFF[9] !== 1'bz) && PIPETX06EQCOEFF[9]; // rv 0 + assign PIPETX06EQDONE_in = (PIPETX06EQDONE !== 1'bz) && PIPETX06EQDONE; // rv 0 + assign PIPETX07EQCOEFF_in[0] = (PIPETX07EQCOEFF[0] !== 1'bz) && PIPETX07EQCOEFF[0]; // rv 0 + assign PIPETX07EQCOEFF_in[10] = (PIPETX07EQCOEFF[10] !== 1'bz) && PIPETX07EQCOEFF[10]; // rv 0 + assign PIPETX07EQCOEFF_in[11] = (PIPETX07EQCOEFF[11] !== 1'bz) && PIPETX07EQCOEFF[11]; // rv 0 + assign PIPETX07EQCOEFF_in[12] = (PIPETX07EQCOEFF[12] !== 1'bz) && PIPETX07EQCOEFF[12]; // rv 0 + assign PIPETX07EQCOEFF_in[13] = (PIPETX07EQCOEFF[13] !== 1'bz) && PIPETX07EQCOEFF[13]; // rv 0 + assign PIPETX07EQCOEFF_in[14] = (PIPETX07EQCOEFF[14] !== 1'bz) && PIPETX07EQCOEFF[14]; // rv 0 + assign PIPETX07EQCOEFF_in[15] = (PIPETX07EQCOEFF[15] !== 1'bz) && PIPETX07EQCOEFF[15]; // rv 0 + assign PIPETX07EQCOEFF_in[16] = (PIPETX07EQCOEFF[16] !== 1'bz) && PIPETX07EQCOEFF[16]; // rv 0 + assign PIPETX07EQCOEFF_in[17] = (PIPETX07EQCOEFF[17] !== 1'bz) && PIPETX07EQCOEFF[17]; // rv 0 + assign PIPETX07EQCOEFF_in[1] = (PIPETX07EQCOEFF[1] !== 1'bz) && PIPETX07EQCOEFF[1]; // rv 0 + assign PIPETX07EQCOEFF_in[2] = (PIPETX07EQCOEFF[2] !== 1'bz) && PIPETX07EQCOEFF[2]; // rv 0 + assign PIPETX07EQCOEFF_in[3] = (PIPETX07EQCOEFF[3] !== 1'bz) && PIPETX07EQCOEFF[3]; // rv 0 + assign PIPETX07EQCOEFF_in[4] = (PIPETX07EQCOEFF[4] !== 1'bz) && PIPETX07EQCOEFF[4]; // rv 0 + assign PIPETX07EQCOEFF_in[5] = (PIPETX07EQCOEFF[5] !== 1'bz) && PIPETX07EQCOEFF[5]; // rv 0 + assign PIPETX07EQCOEFF_in[6] = (PIPETX07EQCOEFF[6] !== 1'bz) && PIPETX07EQCOEFF[6]; // rv 0 + assign PIPETX07EQCOEFF_in[7] = (PIPETX07EQCOEFF[7] !== 1'bz) && PIPETX07EQCOEFF[7]; // rv 0 + assign PIPETX07EQCOEFF_in[8] = (PIPETX07EQCOEFF[8] !== 1'bz) && PIPETX07EQCOEFF[8]; // rv 0 + assign PIPETX07EQCOEFF_in[9] = (PIPETX07EQCOEFF[9] !== 1'bz) && PIPETX07EQCOEFF[9]; // rv 0 + assign PIPETX07EQDONE_in = (PIPETX07EQDONE !== 1'bz) && PIPETX07EQDONE; // rv 0 + assign PIPETX08EQCOEFF_in[0] = (PIPETX08EQCOEFF[0] !== 1'bz) && PIPETX08EQCOEFF[0]; // rv 0 + assign PIPETX08EQCOEFF_in[10] = (PIPETX08EQCOEFF[10] !== 1'bz) && PIPETX08EQCOEFF[10]; // rv 0 + assign PIPETX08EQCOEFF_in[11] = (PIPETX08EQCOEFF[11] !== 1'bz) && PIPETX08EQCOEFF[11]; // rv 0 + assign PIPETX08EQCOEFF_in[12] = (PIPETX08EQCOEFF[12] !== 1'bz) && PIPETX08EQCOEFF[12]; // rv 0 + assign PIPETX08EQCOEFF_in[13] = (PIPETX08EQCOEFF[13] !== 1'bz) && PIPETX08EQCOEFF[13]; // rv 0 + assign PIPETX08EQCOEFF_in[14] = (PIPETX08EQCOEFF[14] !== 1'bz) && PIPETX08EQCOEFF[14]; // rv 0 + assign PIPETX08EQCOEFF_in[15] = (PIPETX08EQCOEFF[15] !== 1'bz) && PIPETX08EQCOEFF[15]; // rv 0 + assign PIPETX08EQCOEFF_in[16] = (PIPETX08EQCOEFF[16] !== 1'bz) && PIPETX08EQCOEFF[16]; // rv 0 + assign PIPETX08EQCOEFF_in[17] = (PIPETX08EQCOEFF[17] !== 1'bz) && PIPETX08EQCOEFF[17]; // rv 0 + assign PIPETX08EQCOEFF_in[1] = (PIPETX08EQCOEFF[1] !== 1'bz) && PIPETX08EQCOEFF[1]; // rv 0 + assign PIPETX08EQCOEFF_in[2] = (PIPETX08EQCOEFF[2] !== 1'bz) && PIPETX08EQCOEFF[2]; // rv 0 + assign PIPETX08EQCOEFF_in[3] = (PIPETX08EQCOEFF[3] !== 1'bz) && PIPETX08EQCOEFF[3]; // rv 0 + assign PIPETX08EQCOEFF_in[4] = (PIPETX08EQCOEFF[4] !== 1'bz) && PIPETX08EQCOEFF[4]; // rv 0 + assign PIPETX08EQCOEFF_in[5] = (PIPETX08EQCOEFF[5] !== 1'bz) && PIPETX08EQCOEFF[5]; // rv 0 + assign PIPETX08EQCOEFF_in[6] = (PIPETX08EQCOEFF[6] !== 1'bz) && PIPETX08EQCOEFF[6]; // rv 0 + assign PIPETX08EQCOEFF_in[7] = (PIPETX08EQCOEFF[7] !== 1'bz) && PIPETX08EQCOEFF[7]; // rv 0 + assign PIPETX08EQCOEFF_in[8] = (PIPETX08EQCOEFF[8] !== 1'bz) && PIPETX08EQCOEFF[8]; // rv 0 + assign PIPETX08EQCOEFF_in[9] = (PIPETX08EQCOEFF[9] !== 1'bz) && PIPETX08EQCOEFF[9]; // rv 0 + assign PIPETX08EQDONE_in = (PIPETX08EQDONE !== 1'bz) && PIPETX08EQDONE; // rv 0 + assign PIPETX09EQCOEFF_in[0] = (PIPETX09EQCOEFF[0] !== 1'bz) && PIPETX09EQCOEFF[0]; // rv 0 + assign PIPETX09EQCOEFF_in[10] = (PIPETX09EQCOEFF[10] !== 1'bz) && PIPETX09EQCOEFF[10]; // rv 0 + assign PIPETX09EQCOEFF_in[11] = (PIPETX09EQCOEFF[11] !== 1'bz) && PIPETX09EQCOEFF[11]; // rv 0 + assign PIPETX09EQCOEFF_in[12] = (PIPETX09EQCOEFF[12] !== 1'bz) && PIPETX09EQCOEFF[12]; // rv 0 + assign PIPETX09EQCOEFF_in[13] = (PIPETX09EQCOEFF[13] !== 1'bz) && PIPETX09EQCOEFF[13]; // rv 0 + assign PIPETX09EQCOEFF_in[14] = (PIPETX09EQCOEFF[14] !== 1'bz) && PIPETX09EQCOEFF[14]; // rv 0 + assign PIPETX09EQCOEFF_in[15] = (PIPETX09EQCOEFF[15] !== 1'bz) && PIPETX09EQCOEFF[15]; // rv 0 + assign PIPETX09EQCOEFF_in[16] = (PIPETX09EQCOEFF[16] !== 1'bz) && PIPETX09EQCOEFF[16]; // rv 0 + assign PIPETX09EQCOEFF_in[17] = (PIPETX09EQCOEFF[17] !== 1'bz) && PIPETX09EQCOEFF[17]; // rv 0 + assign PIPETX09EQCOEFF_in[1] = (PIPETX09EQCOEFF[1] !== 1'bz) && PIPETX09EQCOEFF[1]; // rv 0 + assign PIPETX09EQCOEFF_in[2] = (PIPETX09EQCOEFF[2] !== 1'bz) && PIPETX09EQCOEFF[2]; // rv 0 + assign PIPETX09EQCOEFF_in[3] = (PIPETX09EQCOEFF[3] !== 1'bz) && PIPETX09EQCOEFF[3]; // rv 0 + assign PIPETX09EQCOEFF_in[4] = (PIPETX09EQCOEFF[4] !== 1'bz) && PIPETX09EQCOEFF[4]; // rv 0 + assign PIPETX09EQCOEFF_in[5] = (PIPETX09EQCOEFF[5] !== 1'bz) && PIPETX09EQCOEFF[5]; // rv 0 + assign PIPETX09EQCOEFF_in[6] = (PIPETX09EQCOEFF[6] !== 1'bz) && PIPETX09EQCOEFF[6]; // rv 0 + assign PIPETX09EQCOEFF_in[7] = (PIPETX09EQCOEFF[7] !== 1'bz) && PIPETX09EQCOEFF[7]; // rv 0 + assign PIPETX09EQCOEFF_in[8] = (PIPETX09EQCOEFF[8] !== 1'bz) && PIPETX09EQCOEFF[8]; // rv 0 + assign PIPETX09EQCOEFF_in[9] = (PIPETX09EQCOEFF[9] !== 1'bz) && PIPETX09EQCOEFF[9]; // rv 0 + assign PIPETX09EQDONE_in = (PIPETX09EQDONE !== 1'bz) && PIPETX09EQDONE; // rv 0 + assign PIPETX10EQCOEFF_in[0] = (PIPETX10EQCOEFF[0] !== 1'bz) && PIPETX10EQCOEFF[0]; // rv 0 + assign PIPETX10EQCOEFF_in[10] = (PIPETX10EQCOEFF[10] !== 1'bz) && PIPETX10EQCOEFF[10]; // rv 0 + assign PIPETX10EQCOEFF_in[11] = (PIPETX10EQCOEFF[11] !== 1'bz) && PIPETX10EQCOEFF[11]; // rv 0 + assign PIPETX10EQCOEFF_in[12] = (PIPETX10EQCOEFF[12] !== 1'bz) && PIPETX10EQCOEFF[12]; // rv 0 + assign PIPETX10EQCOEFF_in[13] = (PIPETX10EQCOEFF[13] !== 1'bz) && PIPETX10EQCOEFF[13]; // rv 0 + assign PIPETX10EQCOEFF_in[14] = (PIPETX10EQCOEFF[14] !== 1'bz) && PIPETX10EQCOEFF[14]; // rv 0 + assign PIPETX10EQCOEFF_in[15] = (PIPETX10EQCOEFF[15] !== 1'bz) && PIPETX10EQCOEFF[15]; // rv 0 + assign PIPETX10EQCOEFF_in[16] = (PIPETX10EQCOEFF[16] !== 1'bz) && PIPETX10EQCOEFF[16]; // rv 0 + assign PIPETX10EQCOEFF_in[17] = (PIPETX10EQCOEFF[17] !== 1'bz) && PIPETX10EQCOEFF[17]; // rv 0 + assign PIPETX10EQCOEFF_in[1] = (PIPETX10EQCOEFF[1] !== 1'bz) && PIPETX10EQCOEFF[1]; // rv 0 + assign PIPETX10EQCOEFF_in[2] = (PIPETX10EQCOEFF[2] !== 1'bz) && PIPETX10EQCOEFF[2]; // rv 0 + assign PIPETX10EQCOEFF_in[3] = (PIPETX10EQCOEFF[3] !== 1'bz) && PIPETX10EQCOEFF[3]; // rv 0 + assign PIPETX10EQCOEFF_in[4] = (PIPETX10EQCOEFF[4] !== 1'bz) && PIPETX10EQCOEFF[4]; // rv 0 + assign PIPETX10EQCOEFF_in[5] = (PIPETX10EQCOEFF[5] !== 1'bz) && PIPETX10EQCOEFF[5]; // rv 0 + assign PIPETX10EQCOEFF_in[6] = (PIPETX10EQCOEFF[6] !== 1'bz) && PIPETX10EQCOEFF[6]; // rv 0 + assign PIPETX10EQCOEFF_in[7] = (PIPETX10EQCOEFF[7] !== 1'bz) && PIPETX10EQCOEFF[7]; // rv 0 + assign PIPETX10EQCOEFF_in[8] = (PIPETX10EQCOEFF[8] !== 1'bz) && PIPETX10EQCOEFF[8]; // rv 0 + assign PIPETX10EQCOEFF_in[9] = (PIPETX10EQCOEFF[9] !== 1'bz) && PIPETX10EQCOEFF[9]; // rv 0 + assign PIPETX10EQDONE_in = (PIPETX10EQDONE !== 1'bz) && PIPETX10EQDONE; // rv 0 + assign PIPETX11EQCOEFF_in[0] = (PIPETX11EQCOEFF[0] !== 1'bz) && PIPETX11EQCOEFF[0]; // rv 0 + assign PIPETX11EQCOEFF_in[10] = (PIPETX11EQCOEFF[10] !== 1'bz) && PIPETX11EQCOEFF[10]; // rv 0 + assign PIPETX11EQCOEFF_in[11] = (PIPETX11EQCOEFF[11] !== 1'bz) && PIPETX11EQCOEFF[11]; // rv 0 + assign PIPETX11EQCOEFF_in[12] = (PIPETX11EQCOEFF[12] !== 1'bz) && PIPETX11EQCOEFF[12]; // rv 0 + assign PIPETX11EQCOEFF_in[13] = (PIPETX11EQCOEFF[13] !== 1'bz) && PIPETX11EQCOEFF[13]; // rv 0 + assign PIPETX11EQCOEFF_in[14] = (PIPETX11EQCOEFF[14] !== 1'bz) && PIPETX11EQCOEFF[14]; // rv 0 + assign PIPETX11EQCOEFF_in[15] = (PIPETX11EQCOEFF[15] !== 1'bz) && PIPETX11EQCOEFF[15]; // rv 0 + assign PIPETX11EQCOEFF_in[16] = (PIPETX11EQCOEFF[16] !== 1'bz) && PIPETX11EQCOEFF[16]; // rv 0 + assign PIPETX11EQCOEFF_in[17] = (PIPETX11EQCOEFF[17] !== 1'bz) && PIPETX11EQCOEFF[17]; // rv 0 + assign PIPETX11EQCOEFF_in[1] = (PIPETX11EQCOEFF[1] !== 1'bz) && PIPETX11EQCOEFF[1]; // rv 0 + assign PIPETX11EQCOEFF_in[2] = (PIPETX11EQCOEFF[2] !== 1'bz) && PIPETX11EQCOEFF[2]; // rv 0 + assign PIPETX11EQCOEFF_in[3] = (PIPETX11EQCOEFF[3] !== 1'bz) && PIPETX11EQCOEFF[3]; // rv 0 + assign PIPETX11EQCOEFF_in[4] = (PIPETX11EQCOEFF[4] !== 1'bz) && PIPETX11EQCOEFF[4]; // rv 0 + assign PIPETX11EQCOEFF_in[5] = (PIPETX11EQCOEFF[5] !== 1'bz) && PIPETX11EQCOEFF[5]; // rv 0 + assign PIPETX11EQCOEFF_in[6] = (PIPETX11EQCOEFF[6] !== 1'bz) && PIPETX11EQCOEFF[6]; // rv 0 + assign PIPETX11EQCOEFF_in[7] = (PIPETX11EQCOEFF[7] !== 1'bz) && PIPETX11EQCOEFF[7]; // rv 0 + assign PIPETX11EQCOEFF_in[8] = (PIPETX11EQCOEFF[8] !== 1'bz) && PIPETX11EQCOEFF[8]; // rv 0 + assign PIPETX11EQCOEFF_in[9] = (PIPETX11EQCOEFF[9] !== 1'bz) && PIPETX11EQCOEFF[9]; // rv 0 + assign PIPETX11EQDONE_in = (PIPETX11EQDONE !== 1'bz) && PIPETX11EQDONE; // rv 0 + assign PIPETX12EQCOEFF_in[0] = (PIPETX12EQCOEFF[0] !== 1'bz) && PIPETX12EQCOEFF[0]; // rv 0 + assign PIPETX12EQCOEFF_in[10] = (PIPETX12EQCOEFF[10] !== 1'bz) && PIPETX12EQCOEFF[10]; // rv 0 + assign PIPETX12EQCOEFF_in[11] = (PIPETX12EQCOEFF[11] !== 1'bz) && PIPETX12EQCOEFF[11]; // rv 0 + assign PIPETX12EQCOEFF_in[12] = (PIPETX12EQCOEFF[12] !== 1'bz) && PIPETX12EQCOEFF[12]; // rv 0 + assign PIPETX12EQCOEFF_in[13] = (PIPETX12EQCOEFF[13] !== 1'bz) && PIPETX12EQCOEFF[13]; // rv 0 + assign PIPETX12EQCOEFF_in[14] = (PIPETX12EQCOEFF[14] !== 1'bz) && PIPETX12EQCOEFF[14]; // rv 0 + assign PIPETX12EQCOEFF_in[15] = (PIPETX12EQCOEFF[15] !== 1'bz) && PIPETX12EQCOEFF[15]; // rv 0 + assign PIPETX12EQCOEFF_in[16] = (PIPETX12EQCOEFF[16] !== 1'bz) && PIPETX12EQCOEFF[16]; // rv 0 + assign PIPETX12EQCOEFF_in[17] = (PIPETX12EQCOEFF[17] !== 1'bz) && PIPETX12EQCOEFF[17]; // rv 0 + assign PIPETX12EQCOEFF_in[1] = (PIPETX12EQCOEFF[1] !== 1'bz) && PIPETX12EQCOEFF[1]; // rv 0 + assign PIPETX12EQCOEFF_in[2] = (PIPETX12EQCOEFF[2] !== 1'bz) && PIPETX12EQCOEFF[2]; // rv 0 + assign PIPETX12EQCOEFF_in[3] = (PIPETX12EQCOEFF[3] !== 1'bz) && PIPETX12EQCOEFF[3]; // rv 0 + assign PIPETX12EQCOEFF_in[4] = (PIPETX12EQCOEFF[4] !== 1'bz) && PIPETX12EQCOEFF[4]; // rv 0 + assign PIPETX12EQCOEFF_in[5] = (PIPETX12EQCOEFF[5] !== 1'bz) && PIPETX12EQCOEFF[5]; // rv 0 + assign PIPETX12EQCOEFF_in[6] = (PIPETX12EQCOEFF[6] !== 1'bz) && PIPETX12EQCOEFF[6]; // rv 0 + assign PIPETX12EQCOEFF_in[7] = (PIPETX12EQCOEFF[7] !== 1'bz) && PIPETX12EQCOEFF[7]; // rv 0 + assign PIPETX12EQCOEFF_in[8] = (PIPETX12EQCOEFF[8] !== 1'bz) && PIPETX12EQCOEFF[8]; // rv 0 + assign PIPETX12EQCOEFF_in[9] = (PIPETX12EQCOEFF[9] !== 1'bz) && PIPETX12EQCOEFF[9]; // rv 0 + assign PIPETX12EQDONE_in = (PIPETX12EQDONE !== 1'bz) && PIPETX12EQDONE; // rv 0 + assign PIPETX13EQCOEFF_in[0] = (PIPETX13EQCOEFF[0] !== 1'bz) && PIPETX13EQCOEFF[0]; // rv 0 + assign PIPETX13EQCOEFF_in[10] = (PIPETX13EQCOEFF[10] !== 1'bz) && PIPETX13EQCOEFF[10]; // rv 0 + assign PIPETX13EQCOEFF_in[11] = (PIPETX13EQCOEFF[11] !== 1'bz) && PIPETX13EQCOEFF[11]; // rv 0 + assign PIPETX13EQCOEFF_in[12] = (PIPETX13EQCOEFF[12] !== 1'bz) && PIPETX13EQCOEFF[12]; // rv 0 + assign PIPETX13EQCOEFF_in[13] = (PIPETX13EQCOEFF[13] !== 1'bz) && PIPETX13EQCOEFF[13]; // rv 0 + assign PIPETX13EQCOEFF_in[14] = (PIPETX13EQCOEFF[14] !== 1'bz) && PIPETX13EQCOEFF[14]; // rv 0 + assign PIPETX13EQCOEFF_in[15] = (PIPETX13EQCOEFF[15] !== 1'bz) && PIPETX13EQCOEFF[15]; // rv 0 + assign PIPETX13EQCOEFF_in[16] = (PIPETX13EQCOEFF[16] !== 1'bz) && PIPETX13EQCOEFF[16]; // rv 0 + assign PIPETX13EQCOEFF_in[17] = (PIPETX13EQCOEFF[17] !== 1'bz) && PIPETX13EQCOEFF[17]; // rv 0 + assign PIPETX13EQCOEFF_in[1] = (PIPETX13EQCOEFF[1] !== 1'bz) && PIPETX13EQCOEFF[1]; // rv 0 + assign PIPETX13EQCOEFF_in[2] = (PIPETX13EQCOEFF[2] !== 1'bz) && PIPETX13EQCOEFF[2]; // rv 0 + assign PIPETX13EQCOEFF_in[3] = (PIPETX13EQCOEFF[3] !== 1'bz) && PIPETX13EQCOEFF[3]; // rv 0 + assign PIPETX13EQCOEFF_in[4] = (PIPETX13EQCOEFF[4] !== 1'bz) && PIPETX13EQCOEFF[4]; // rv 0 + assign PIPETX13EQCOEFF_in[5] = (PIPETX13EQCOEFF[5] !== 1'bz) && PIPETX13EQCOEFF[5]; // rv 0 + assign PIPETX13EQCOEFF_in[6] = (PIPETX13EQCOEFF[6] !== 1'bz) && PIPETX13EQCOEFF[6]; // rv 0 + assign PIPETX13EQCOEFF_in[7] = (PIPETX13EQCOEFF[7] !== 1'bz) && PIPETX13EQCOEFF[7]; // rv 0 + assign PIPETX13EQCOEFF_in[8] = (PIPETX13EQCOEFF[8] !== 1'bz) && PIPETX13EQCOEFF[8]; // rv 0 + assign PIPETX13EQCOEFF_in[9] = (PIPETX13EQCOEFF[9] !== 1'bz) && PIPETX13EQCOEFF[9]; // rv 0 + assign PIPETX13EQDONE_in = (PIPETX13EQDONE !== 1'bz) && PIPETX13EQDONE; // rv 0 + assign PIPETX14EQCOEFF_in[0] = (PIPETX14EQCOEFF[0] !== 1'bz) && PIPETX14EQCOEFF[0]; // rv 0 + assign PIPETX14EQCOEFF_in[10] = (PIPETX14EQCOEFF[10] !== 1'bz) && PIPETX14EQCOEFF[10]; // rv 0 + assign PIPETX14EQCOEFF_in[11] = (PIPETX14EQCOEFF[11] !== 1'bz) && PIPETX14EQCOEFF[11]; // rv 0 + assign PIPETX14EQCOEFF_in[12] = (PIPETX14EQCOEFF[12] !== 1'bz) && PIPETX14EQCOEFF[12]; // rv 0 + assign PIPETX14EQCOEFF_in[13] = (PIPETX14EQCOEFF[13] !== 1'bz) && PIPETX14EQCOEFF[13]; // rv 0 + assign PIPETX14EQCOEFF_in[14] = (PIPETX14EQCOEFF[14] !== 1'bz) && PIPETX14EQCOEFF[14]; // rv 0 + assign PIPETX14EQCOEFF_in[15] = (PIPETX14EQCOEFF[15] !== 1'bz) && PIPETX14EQCOEFF[15]; // rv 0 + assign PIPETX14EQCOEFF_in[16] = (PIPETX14EQCOEFF[16] !== 1'bz) && PIPETX14EQCOEFF[16]; // rv 0 + assign PIPETX14EQCOEFF_in[17] = (PIPETX14EQCOEFF[17] !== 1'bz) && PIPETX14EQCOEFF[17]; // rv 0 + assign PIPETX14EQCOEFF_in[1] = (PIPETX14EQCOEFF[1] !== 1'bz) && PIPETX14EQCOEFF[1]; // rv 0 + assign PIPETX14EQCOEFF_in[2] = (PIPETX14EQCOEFF[2] !== 1'bz) && PIPETX14EQCOEFF[2]; // rv 0 + assign PIPETX14EQCOEFF_in[3] = (PIPETX14EQCOEFF[3] !== 1'bz) && PIPETX14EQCOEFF[3]; // rv 0 + assign PIPETX14EQCOEFF_in[4] = (PIPETX14EQCOEFF[4] !== 1'bz) && PIPETX14EQCOEFF[4]; // rv 0 + assign PIPETX14EQCOEFF_in[5] = (PIPETX14EQCOEFF[5] !== 1'bz) && PIPETX14EQCOEFF[5]; // rv 0 + assign PIPETX14EQCOEFF_in[6] = (PIPETX14EQCOEFF[6] !== 1'bz) && PIPETX14EQCOEFF[6]; // rv 0 + assign PIPETX14EQCOEFF_in[7] = (PIPETX14EQCOEFF[7] !== 1'bz) && PIPETX14EQCOEFF[7]; // rv 0 + assign PIPETX14EQCOEFF_in[8] = (PIPETX14EQCOEFF[8] !== 1'bz) && PIPETX14EQCOEFF[8]; // rv 0 + assign PIPETX14EQCOEFF_in[9] = (PIPETX14EQCOEFF[9] !== 1'bz) && PIPETX14EQCOEFF[9]; // rv 0 + assign PIPETX14EQDONE_in = (PIPETX14EQDONE !== 1'bz) && PIPETX14EQDONE; // rv 0 + assign PIPETX15EQCOEFF_in[0] = (PIPETX15EQCOEFF[0] !== 1'bz) && PIPETX15EQCOEFF[0]; // rv 0 + assign PIPETX15EQCOEFF_in[10] = (PIPETX15EQCOEFF[10] !== 1'bz) && PIPETX15EQCOEFF[10]; // rv 0 + assign PIPETX15EQCOEFF_in[11] = (PIPETX15EQCOEFF[11] !== 1'bz) && PIPETX15EQCOEFF[11]; // rv 0 + assign PIPETX15EQCOEFF_in[12] = (PIPETX15EQCOEFF[12] !== 1'bz) && PIPETX15EQCOEFF[12]; // rv 0 + assign PIPETX15EQCOEFF_in[13] = (PIPETX15EQCOEFF[13] !== 1'bz) && PIPETX15EQCOEFF[13]; // rv 0 + assign PIPETX15EQCOEFF_in[14] = (PIPETX15EQCOEFF[14] !== 1'bz) && PIPETX15EQCOEFF[14]; // rv 0 + assign PIPETX15EQCOEFF_in[15] = (PIPETX15EQCOEFF[15] !== 1'bz) && PIPETX15EQCOEFF[15]; // rv 0 + assign PIPETX15EQCOEFF_in[16] = (PIPETX15EQCOEFF[16] !== 1'bz) && PIPETX15EQCOEFF[16]; // rv 0 + assign PIPETX15EQCOEFF_in[17] = (PIPETX15EQCOEFF[17] !== 1'bz) && PIPETX15EQCOEFF[17]; // rv 0 + assign PIPETX15EQCOEFF_in[1] = (PIPETX15EQCOEFF[1] !== 1'bz) && PIPETX15EQCOEFF[1]; // rv 0 + assign PIPETX15EQCOEFF_in[2] = (PIPETX15EQCOEFF[2] !== 1'bz) && PIPETX15EQCOEFF[2]; // rv 0 + assign PIPETX15EQCOEFF_in[3] = (PIPETX15EQCOEFF[3] !== 1'bz) && PIPETX15EQCOEFF[3]; // rv 0 + assign PIPETX15EQCOEFF_in[4] = (PIPETX15EQCOEFF[4] !== 1'bz) && PIPETX15EQCOEFF[4]; // rv 0 + assign PIPETX15EQCOEFF_in[5] = (PIPETX15EQCOEFF[5] !== 1'bz) && PIPETX15EQCOEFF[5]; // rv 0 + assign PIPETX15EQCOEFF_in[6] = (PIPETX15EQCOEFF[6] !== 1'bz) && PIPETX15EQCOEFF[6]; // rv 0 + assign PIPETX15EQCOEFF_in[7] = (PIPETX15EQCOEFF[7] !== 1'bz) && PIPETX15EQCOEFF[7]; // rv 0 + assign PIPETX15EQCOEFF_in[8] = (PIPETX15EQCOEFF[8] !== 1'bz) && PIPETX15EQCOEFF[8]; // rv 0 + assign PIPETX15EQCOEFF_in[9] = (PIPETX15EQCOEFF[9] !== 1'bz) && PIPETX15EQCOEFF[9]; // rv 0 + assign PIPETX15EQDONE_in = (PIPETX15EQDONE !== 1'bz) && PIPETX15EQDONE; // rv 0 + assign PLGEN2UPSTREAMPREFERDEEMPH_in = (PLGEN2UPSTREAMPREFERDEEMPH !== 1'bz) && PLGEN2UPSTREAMPREFERDEEMPH; // rv 0 + assign PLGEN34REDOEQSPEED_in = (PLGEN34REDOEQSPEED !== 1'bz) && PLGEN34REDOEQSPEED; // rv 0 + assign PLGEN34REDOEQUALIZATION_in = (PLGEN34REDOEQUALIZATION !== 1'bz) && PLGEN34REDOEQUALIZATION; // rv 0 + assign SAXISCCTDATA_in[0] = (SAXISCCTDATA[0] === 1'bz) || SAXISCCTDATA[0]; // rv 1 + assign SAXISCCTDATA_in[100] = (SAXISCCTDATA[100] === 1'bz) || SAXISCCTDATA[100]; // rv 1 + assign SAXISCCTDATA_in[101] = (SAXISCCTDATA[101] === 1'bz) || SAXISCCTDATA[101]; // rv 1 + assign SAXISCCTDATA_in[102] = (SAXISCCTDATA[102] === 1'bz) || SAXISCCTDATA[102]; // rv 1 + assign SAXISCCTDATA_in[103] = (SAXISCCTDATA[103] === 1'bz) || SAXISCCTDATA[103]; // rv 1 + assign SAXISCCTDATA_in[104] = (SAXISCCTDATA[104] === 1'bz) || SAXISCCTDATA[104]; // rv 1 + assign SAXISCCTDATA_in[105] = (SAXISCCTDATA[105] === 1'bz) || SAXISCCTDATA[105]; // rv 1 + assign SAXISCCTDATA_in[106] = (SAXISCCTDATA[106] === 1'bz) || SAXISCCTDATA[106]; // rv 1 + assign SAXISCCTDATA_in[107] = (SAXISCCTDATA[107] === 1'bz) || SAXISCCTDATA[107]; // rv 1 + assign SAXISCCTDATA_in[108] = (SAXISCCTDATA[108] === 1'bz) || SAXISCCTDATA[108]; // rv 1 + assign SAXISCCTDATA_in[109] = (SAXISCCTDATA[109] === 1'bz) || SAXISCCTDATA[109]; // rv 1 + assign SAXISCCTDATA_in[10] = (SAXISCCTDATA[10] === 1'bz) || SAXISCCTDATA[10]; // rv 1 + assign SAXISCCTDATA_in[110] = (SAXISCCTDATA[110] === 1'bz) || SAXISCCTDATA[110]; // rv 1 + assign SAXISCCTDATA_in[111] = (SAXISCCTDATA[111] === 1'bz) || SAXISCCTDATA[111]; // rv 1 + assign SAXISCCTDATA_in[112] = (SAXISCCTDATA[112] === 1'bz) || SAXISCCTDATA[112]; // rv 1 + assign SAXISCCTDATA_in[113] = (SAXISCCTDATA[113] === 1'bz) || SAXISCCTDATA[113]; // rv 1 + assign SAXISCCTDATA_in[114] = (SAXISCCTDATA[114] === 1'bz) || SAXISCCTDATA[114]; // rv 1 + assign SAXISCCTDATA_in[115] = (SAXISCCTDATA[115] === 1'bz) || SAXISCCTDATA[115]; // rv 1 + assign SAXISCCTDATA_in[116] = (SAXISCCTDATA[116] === 1'bz) || SAXISCCTDATA[116]; // rv 1 + assign SAXISCCTDATA_in[117] = (SAXISCCTDATA[117] === 1'bz) || SAXISCCTDATA[117]; // rv 1 + assign SAXISCCTDATA_in[118] = (SAXISCCTDATA[118] === 1'bz) || SAXISCCTDATA[118]; // rv 1 + assign SAXISCCTDATA_in[119] = (SAXISCCTDATA[119] === 1'bz) || SAXISCCTDATA[119]; // rv 1 + assign SAXISCCTDATA_in[11] = (SAXISCCTDATA[11] === 1'bz) || SAXISCCTDATA[11]; // rv 1 + assign SAXISCCTDATA_in[120] = (SAXISCCTDATA[120] === 1'bz) || SAXISCCTDATA[120]; // rv 1 + assign SAXISCCTDATA_in[121] = (SAXISCCTDATA[121] === 1'bz) || SAXISCCTDATA[121]; // rv 1 + assign SAXISCCTDATA_in[122] = (SAXISCCTDATA[122] === 1'bz) || SAXISCCTDATA[122]; // rv 1 + assign SAXISCCTDATA_in[123] = (SAXISCCTDATA[123] === 1'bz) || SAXISCCTDATA[123]; // rv 1 + assign SAXISCCTDATA_in[124] = (SAXISCCTDATA[124] === 1'bz) || SAXISCCTDATA[124]; // rv 1 + assign SAXISCCTDATA_in[125] = (SAXISCCTDATA[125] === 1'bz) || SAXISCCTDATA[125]; // rv 1 + assign SAXISCCTDATA_in[126] = (SAXISCCTDATA[126] === 1'bz) || SAXISCCTDATA[126]; // rv 1 + assign SAXISCCTDATA_in[127] = (SAXISCCTDATA[127] === 1'bz) || SAXISCCTDATA[127]; // rv 1 + assign SAXISCCTDATA_in[128] = (SAXISCCTDATA[128] === 1'bz) || SAXISCCTDATA[128]; // rv 1 + assign SAXISCCTDATA_in[129] = (SAXISCCTDATA[129] === 1'bz) || SAXISCCTDATA[129]; // rv 1 + assign SAXISCCTDATA_in[12] = (SAXISCCTDATA[12] === 1'bz) || SAXISCCTDATA[12]; // rv 1 + assign SAXISCCTDATA_in[130] = (SAXISCCTDATA[130] === 1'bz) || SAXISCCTDATA[130]; // rv 1 + assign SAXISCCTDATA_in[131] = (SAXISCCTDATA[131] === 1'bz) || SAXISCCTDATA[131]; // rv 1 + assign SAXISCCTDATA_in[132] = (SAXISCCTDATA[132] === 1'bz) || SAXISCCTDATA[132]; // rv 1 + assign SAXISCCTDATA_in[133] = (SAXISCCTDATA[133] === 1'bz) || SAXISCCTDATA[133]; // rv 1 + assign SAXISCCTDATA_in[134] = (SAXISCCTDATA[134] === 1'bz) || SAXISCCTDATA[134]; // rv 1 + assign SAXISCCTDATA_in[135] = (SAXISCCTDATA[135] === 1'bz) || SAXISCCTDATA[135]; // rv 1 + assign SAXISCCTDATA_in[136] = (SAXISCCTDATA[136] === 1'bz) || SAXISCCTDATA[136]; // rv 1 + assign SAXISCCTDATA_in[137] = (SAXISCCTDATA[137] === 1'bz) || SAXISCCTDATA[137]; // rv 1 + assign SAXISCCTDATA_in[138] = (SAXISCCTDATA[138] === 1'bz) || SAXISCCTDATA[138]; // rv 1 + assign SAXISCCTDATA_in[139] = (SAXISCCTDATA[139] === 1'bz) || SAXISCCTDATA[139]; // rv 1 + assign SAXISCCTDATA_in[13] = (SAXISCCTDATA[13] === 1'bz) || SAXISCCTDATA[13]; // rv 1 + assign SAXISCCTDATA_in[140] = (SAXISCCTDATA[140] === 1'bz) || SAXISCCTDATA[140]; // rv 1 + assign SAXISCCTDATA_in[141] = (SAXISCCTDATA[141] === 1'bz) || SAXISCCTDATA[141]; // rv 1 + assign SAXISCCTDATA_in[142] = (SAXISCCTDATA[142] === 1'bz) || SAXISCCTDATA[142]; // rv 1 + assign SAXISCCTDATA_in[143] = (SAXISCCTDATA[143] === 1'bz) || SAXISCCTDATA[143]; // rv 1 + assign SAXISCCTDATA_in[144] = (SAXISCCTDATA[144] === 1'bz) || SAXISCCTDATA[144]; // rv 1 + assign SAXISCCTDATA_in[145] = (SAXISCCTDATA[145] === 1'bz) || SAXISCCTDATA[145]; // rv 1 + assign SAXISCCTDATA_in[146] = (SAXISCCTDATA[146] === 1'bz) || SAXISCCTDATA[146]; // rv 1 + assign SAXISCCTDATA_in[147] = (SAXISCCTDATA[147] === 1'bz) || SAXISCCTDATA[147]; // rv 1 + assign SAXISCCTDATA_in[148] = (SAXISCCTDATA[148] === 1'bz) || SAXISCCTDATA[148]; // rv 1 + assign SAXISCCTDATA_in[149] = (SAXISCCTDATA[149] === 1'bz) || SAXISCCTDATA[149]; // rv 1 + assign SAXISCCTDATA_in[14] = (SAXISCCTDATA[14] === 1'bz) || SAXISCCTDATA[14]; // rv 1 + assign SAXISCCTDATA_in[150] = (SAXISCCTDATA[150] === 1'bz) || SAXISCCTDATA[150]; // rv 1 + assign SAXISCCTDATA_in[151] = (SAXISCCTDATA[151] === 1'bz) || SAXISCCTDATA[151]; // rv 1 + assign SAXISCCTDATA_in[152] = (SAXISCCTDATA[152] === 1'bz) || SAXISCCTDATA[152]; // rv 1 + assign SAXISCCTDATA_in[153] = (SAXISCCTDATA[153] === 1'bz) || SAXISCCTDATA[153]; // rv 1 + assign SAXISCCTDATA_in[154] = (SAXISCCTDATA[154] === 1'bz) || SAXISCCTDATA[154]; // rv 1 + assign SAXISCCTDATA_in[155] = (SAXISCCTDATA[155] === 1'bz) || SAXISCCTDATA[155]; // rv 1 + assign SAXISCCTDATA_in[156] = (SAXISCCTDATA[156] === 1'bz) || SAXISCCTDATA[156]; // rv 1 + assign SAXISCCTDATA_in[157] = (SAXISCCTDATA[157] === 1'bz) || SAXISCCTDATA[157]; // rv 1 + assign SAXISCCTDATA_in[158] = (SAXISCCTDATA[158] === 1'bz) || SAXISCCTDATA[158]; // rv 1 + assign SAXISCCTDATA_in[159] = (SAXISCCTDATA[159] === 1'bz) || SAXISCCTDATA[159]; // rv 1 + assign SAXISCCTDATA_in[15] = (SAXISCCTDATA[15] === 1'bz) || SAXISCCTDATA[15]; // rv 1 + assign SAXISCCTDATA_in[160] = (SAXISCCTDATA[160] === 1'bz) || SAXISCCTDATA[160]; // rv 1 + assign SAXISCCTDATA_in[161] = (SAXISCCTDATA[161] === 1'bz) || SAXISCCTDATA[161]; // rv 1 + assign SAXISCCTDATA_in[162] = (SAXISCCTDATA[162] === 1'bz) || SAXISCCTDATA[162]; // rv 1 + assign SAXISCCTDATA_in[163] = (SAXISCCTDATA[163] === 1'bz) || SAXISCCTDATA[163]; // rv 1 + assign SAXISCCTDATA_in[164] = (SAXISCCTDATA[164] === 1'bz) || SAXISCCTDATA[164]; // rv 1 + assign SAXISCCTDATA_in[165] = (SAXISCCTDATA[165] === 1'bz) || SAXISCCTDATA[165]; // rv 1 + assign SAXISCCTDATA_in[166] = (SAXISCCTDATA[166] === 1'bz) || SAXISCCTDATA[166]; // rv 1 + assign SAXISCCTDATA_in[167] = (SAXISCCTDATA[167] === 1'bz) || SAXISCCTDATA[167]; // rv 1 + assign SAXISCCTDATA_in[168] = (SAXISCCTDATA[168] === 1'bz) || SAXISCCTDATA[168]; // rv 1 + assign SAXISCCTDATA_in[169] = (SAXISCCTDATA[169] === 1'bz) || SAXISCCTDATA[169]; // rv 1 + assign SAXISCCTDATA_in[16] = (SAXISCCTDATA[16] === 1'bz) || SAXISCCTDATA[16]; // rv 1 + assign SAXISCCTDATA_in[170] = (SAXISCCTDATA[170] === 1'bz) || SAXISCCTDATA[170]; // rv 1 + assign SAXISCCTDATA_in[171] = (SAXISCCTDATA[171] === 1'bz) || SAXISCCTDATA[171]; // rv 1 + assign SAXISCCTDATA_in[172] = (SAXISCCTDATA[172] === 1'bz) || SAXISCCTDATA[172]; // rv 1 + assign SAXISCCTDATA_in[173] = (SAXISCCTDATA[173] === 1'bz) || SAXISCCTDATA[173]; // rv 1 + assign SAXISCCTDATA_in[174] = (SAXISCCTDATA[174] === 1'bz) || SAXISCCTDATA[174]; // rv 1 + assign SAXISCCTDATA_in[175] = (SAXISCCTDATA[175] === 1'bz) || SAXISCCTDATA[175]; // rv 1 + assign SAXISCCTDATA_in[176] = (SAXISCCTDATA[176] === 1'bz) || SAXISCCTDATA[176]; // rv 1 + assign SAXISCCTDATA_in[177] = (SAXISCCTDATA[177] === 1'bz) || SAXISCCTDATA[177]; // rv 1 + assign SAXISCCTDATA_in[178] = (SAXISCCTDATA[178] === 1'bz) || SAXISCCTDATA[178]; // rv 1 + assign SAXISCCTDATA_in[179] = (SAXISCCTDATA[179] === 1'bz) || SAXISCCTDATA[179]; // rv 1 + assign SAXISCCTDATA_in[17] = (SAXISCCTDATA[17] === 1'bz) || SAXISCCTDATA[17]; // rv 1 + assign SAXISCCTDATA_in[180] = (SAXISCCTDATA[180] === 1'bz) || SAXISCCTDATA[180]; // rv 1 + assign SAXISCCTDATA_in[181] = (SAXISCCTDATA[181] === 1'bz) || SAXISCCTDATA[181]; // rv 1 + assign SAXISCCTDATA_in[182] = (SAXISCCTDATA[182] === 1'bz) || SAXISCCTDATA[182]; // rv 1 + assign SAXISCCTDATA_in[183] = (SAXISCCTDATA[183] === 1'bz) || SAXISCCTDATA[183]; // rv 1 + assign SAXISCCTDATA_in[184] = (SAXISCCTDATA[184] === 1'bz) || SAXISCCTDATA[184]; // rv 1 + assign SAXISCCTDATA_in[185] = (SAXISCCTDATA[185] === 1'bz) || SAXISCCTDATA[185]; // rv 1 + assign SAXISCCTDATA_in[186] = (SAXISCCTDATA[186] === 1'bz) || SAXISCCTDATA[186]; // rv 1 + assign SAXISCCTDATA_in[187] = (SAXISCCTDATA[187] === 1'bz) || SAXISCCTDATA[187]; // rv 1 + assign SAXISCCTDATA_in[188] = (SAXISCCTDATA[188] === 1'bz) || SAXISCCTDATA[188]; // rv 1 + assign SAXISCCTDATA_in[189] = (SAXISCCTDATA[189] === 1'bz) || SAXISCCTDATA[189]; // rv 1 + assign SAXISCCTDATA_in[18] = (SAXISCCTDATA[18] === 1'bz) || SAXISCCTDATA[18]; // rv 1 + assign SAXISCCTDATA_in[190] = (SAXISCCTDATA[190] === 1'bz) || SAXISCCTDATA[190]; // rv 1 + assign SAXISCCTDATA_in[191] = (SAXISCCTDATA[191] === 1'bz) || SAXISCCTDATA[191]; // rv 1 + assign SAXISCCTDATA_in[192] = (SAXISCCTDATA[192] === 1'bz) || SAXISCCTDATA[192]; // rv 1 + assign SAXISCCTDATA_in[193] = (SAXISCCTDATA[193] === 1'bz) || SAXISCCTDATA[193]; // rv 1 + assign SAXISCCTDATA_in[194] = (SAXISCCTDATA[194] === 1'bz) || SAXISCCTDATA[194]; // rv 1 + assign SAXISCCTDATA_in[195] = (SAXISCCTDATA[195] === 1'bz) || SAXISCCTDATA[195]; // rv 1 + assign SAXISCCTDATA_in[196] = (SAXISCCTDATA[196] === 1'bz) || SAXISCCTDATA[196]; // rv 1 + assign SAXISCCTDATA_in[197] = (SAXISCCTDATA[197] === 1'bz) || SAXISCCTDATA[197]; // rv 1 + assign SAXISCCTDATA_in[198] = (SAXISCCTDATA[198] === 1'bz) || SAXISCCTDATA[198]; // rv 1 + assign SAXISCCTDATA_in[199] = (SAXISCCTDATA[199] === 1'bz) || SAXISCCTDATA[199]; // rv 1 + assign SAXISCCTDATA_in[19] = (SAXISCCTDATA[19] === 1'bz) || SAXISCCTDATA[19]; // rv 1 + assign SAXISCCTDATA_in[1] = (SAXISCCTDATA[1] === 1'bz) || SAXISCCTDATA[1]; // rv 1 + assign SAXISCCTDATA_in[200] = (SAXISCCTDATA[200] === 1'bz) || SAXISCCTDATA[200]; // rv 1 + assign SAXISCCTDATA_in[201] = (SAXISCCTDATA[201] === 1'bz) || SAXISCCTDATA[201]; // rv 1 + assign SAXISCCTDATA_in[202] = (SAXISCCTDATA[202] === 1'bz) || SAXISCCTDATA[202]; // rv 1 + assign SAXISCCTDATA_in[203] = (SAXISCCTDATA[203] === 1'bz) || SAXISCCTDATA[203]; // rv 1 + assign SAXISCCTDATA_in[204] = (SAXISCCTDATA[204] === 1'bz) || SAXISCCTDATA[204]; // rv 1 + assign SAXISCCTDATA_in[205] = (SAXISCCTDATA[205] === 1'bz) || SAXISCCTDATA[205]; // rv 1 + assign SAXISCCTDATA_in[206] = (SAXISCCTDATA[206] === 1'bz) || SAXISCCTDATA[206]; // rv 1 + assign SAXISCCTDATA_in[207] = (SAXISCCTDATA[207] === 1'bz) || SAXISCCTDATA[207]; // rv 1 + assign SAXISCCTDATA_in[208] = (SAXISCCTDATA[208] === 1'bz) || SAXISCCTDATA[208]; // rv 1 + assign SAXISCCTDATA_in[209] = (SAXISCCTDATA[209] === 1'bz) || SAXISCCTDATA[209]; // rv 1 + assign SAXISCCTDATA_in[20] = (SAXISCCTDATA[20] === 1'bz) || SAXISCCTDATA[20]; // rv 1 + assign SAXISCCTDATA_in[210] = (SAXISCCTDATA[210] === 1'bz) || SAXISCCTDATA[210]; // rv 1 + assign SAXISCCTDATA_in[211] = (SAXISCCTDATA[211] === 1'bz) || SAXISCCTDATA[211]; // rv 1 + assign SAXISCCTDATA_in[212] = (SAXISCCTDATA[212] === 1'bz) || SAXISCCTDATA[212]; // rv 1 + assign SAXISCCTDATA_in[213] = (SAXISCCTDATA[213] === 1'bz) || SAXISCCTDATA[213]; // rv 1 + assign SAXISCCTDATA_in[214] = (SAXISCCTDATA[214] === 1'bz) || SAXISCCTDATA[214]; // rv 1 + assign SAXISCCTDATA_in[215] = (SAXISCCTDATA[215] === 1'bz) || SAXISCCTDATA[215]; // rv 1 + assign SAXISCCTDATA_in[216] = (SAXISCCTDATA[216] === 1'bz) || SAXISCCTDATA[216]; // rv 1 + assign SAXISCCTDATA_in[217] = (SAXISCCTDATA[217] === 1'bz) || SAXISCCTDATA[217]; // rv 1 + assign SAXISCCTDATA_in[218] = (SAXISCCTDATA[218] === 1'bz) || SAXISCCTDATA[218]; // rv 1 + assign SAXISCCTDATA_in[219] = (SAXISCCTDATA[219] === 1'bz) || SAXISCCTDATA[219]; // rv 1 + assign SAXISCCTDATA_in[21] = (SAXISCCTDATA[21] === 1'bz) || SAXISCCTDATA[21]; // rv 1 + assign SAXISCCTDATA_in[220] = (SAXISCCTDATA[220] === 1'bz) || SAXISCCTDATA[220]; // rv 1 + assign SAXISCCTDATA_in[221] = (SAXISCCTDATA[221] === 1'bz) || SAXISCCTDATA[221]; // rv 1 + assign SAXISCCTDATA_in[222] = (SAXISCCTDATA[222] === 1'bz) || SAXISCCTDATA[222]; // rv 1 + assign SAXISCCTDATA_in[223] = (SAXISCCTDATA[223] === 1'bz) || SAXISCCTDATA[223]; // rv 1 + assign SAXISCCTDATA_in[224] = (SAXISCCTDATA[224] === 1'bz) || SAXISCCTDATA[224]; // rv 1 + assign SAXISCCTDATA_in[225] = (SAXISCCTDATA[225] === 1'bz) || SAXISCCTDATA[225]; // rv 1 + assign SAXISCCTDATA_in[226] = (SAXISCCTDATA[226] === 1'bz) || SAXISCCTDATA[226]; // rv 1 + assign SAXISCCTDATA_in[227] = (SAXISCCTDATA[227] === 1'bz) || SAXISCCTDATA[227]; // rv 1 + assign SAXISCCTDATA_in[228] = (SAXISCCTDATA[228] === 1'bz) || SAXISCCTDATA[228]; // rv 1 + assign SAXISCCTDATA_in[229] = (SAXISCCTDATA[229] === 1'bz) || SAXISCCTDATA[229]; // rv 1 + assign SAXISCCTDATA_in[22] = (SAXISCCTDATA[22] === 1'bz) || SAXISCCTDATA[22]; // rv 1 + assign SAXISCCTDATA_in[230] = (SAXISCCTDATA[230] === 1'bz) || SAXISCCTDATA[230]; // rv 1 + assign SAXISCCTDATA_in[231] = (SAXISCCTDATA[231] === 1'bz) || SAXISCCTDATA[231]; // rv 1 + assign SAXISCCTDATA_in[232] = (SAXISCCTDATA[232] === 1'bz) || SAXISCCTDATA[232]; // rv 1 + assign SAXISCCTDATA_in[233] = (SAXISCCTDATA[233] === 1'bz) || SAXISCCTDATA[233]; // rv 1 + assign SAXISCCTDATA_in[234] = (SAXISCCTDATA[234] === 1'bz) || SAXISCCTDATA[234]; // rv 1 + assign SAXISCCTDATA_in[235] = (SAXISCCTDATA[235] === 1'bz) || SAXISCCTDATA[235]; // rv 1 + assign SAXISCCTDATA_in[236] = (SAXISCCTDATA[236] === 1'bz) || SAXISCCTDATA[236]; // rv 1 + assign SAXISCCTDATA_in[237] = (SAXISCCTDATA[237] === 1'bz) || SAXISCCTDATA[237]; // rv 1 + assign SAXISCCTDATA_in[238] = (SAXISCCTDATA[238] === 1'bz) || SAXISCCTDATA[238]; // rv 1 + assign SAXISCCTDATA_in[239] = (SAXISCCTDATA[239] === 1'bz) || SAXISCCTDATA[239]; // rv 1 + assign SAXISCCTDATA_in[23] = (SAXISCCTDATA[23] === 1'bz) || SAXISCCTDATA[23]; // rv 1 + assign SAXISCCTDATA_in[240] = (SAXISCCTDATA[240] === 1'bz) || SAXISCCTDATA[240]; // rv 1 + assign SAXISCCTDATA_in[241] = (SAXISCCTDATA[241] === 1'bz) || SAXISCCTDATA[241]; // rv 1 + assign SAXISCCTDATA_in[242] = (SAXISCCTDATA[242] === 1'bz) || SAXISCCTDATA[242]; // rv 1 + assign SAXISCCTDATA_in[243] = (SAXISCCTDATA[243] === 1'bz) || SAXISCCTDATA[243]; // rv 1 + assign SAXISCCTDATA_in[244] = (SAXISCCTDATA[244] === 1'bz) || SAXISCCTDATA[244]; // rv 1 + assign SAXISCCTDATA_in[245] = (SAXISCCTDATA[245] === 1'bz) || SAXISCCTDATA[245]; // rv 1 + assign SAXISCCTDATA_in[246] = (SAXISCCTDATA[246] === 1'bz) || SAXISCCTDATA[246]; // rv 1 + assign SAXISCCTDATA_in[247] = (SAXISCCTDATA[247] === 1'bz) || SAXISCCTDATA[247]; // rv 1 + assign SAXISCCTDATA_in[248] = (SAXISCCTDATA[248] === 1'bz) || SAXISCCTDATA[248]; // rv 1 + assign SAXISCCTDATA_in[249] = (SAXISCCTDATA[249] === 1'bz) || SAXISCCTDATA[249]; // rv 1 + assign SAXISCCTDATA_in[24] = (SAXISCCTDATA[24] === 1'bz) || SAXISCCTDATA[24]; // rv 1 + assign SAXISCCTDATA_in[250] = (SAXISCCTDATA[250] === 1'bz) || SAXISCCTDATA[250]; // rv 1 + assign SAXISCCTDATA_in[251] = (SAXISCCTDATA[251] === 1'bz) || SAXISCCTDATA[251]; // rv 1 + assign SAXISCCTDATA_in[252] = (SAXISCCTDATA[252] === 1'bz) || SAXISCCTDATA[252]; // rv 1 + assign SAXISCCTDATA_in[253] = (SAXISCCTDATA[253] === 1'bz) || SAXISCCTDATA[253]; // rv 1 + assign SAXISCCTDATA_in[254] = (SAXISCCTDATA[254] === 1'bz) || SAXISCCTDATA[254]; // rv 1 + assign SAXISCCTDATA_in[255] = (SAXISCCTDATA[255] === 1'bz) || SAXISCCTDATA[255]; // rv 1 + assign SAXISCCTDATA_in[25] = (SAXISCCTDATA[25] === 1'bz) || SAXISCCTDATA[25]; // rv 1 + assign SAXISCCTDATA_in[26] = (SAXISCCTDATA[26] === 1'bz) || SAXISCCTDATA[26]; // rv 1 + assign SAXISCCTDATA_in[27] = (SAXISCCTDATA[27] === 1'bz) || SAXISCCTDATA[27]; // rv 1 + assign SAXISCCTDATA_in[28] = (SAXISCCTDATA[28] === 1'bz) || SAXISCCTDATA[28]; // rv 1 + assign SAXISCCTDATA_in[29] = (SAXISCCTDATA[29] === 1'bz) || SAXISCCTDATA[29]; // rv 1 + assign SAXISCCTDATA_in[2] = (SAXISCCTDATA[2] === 1'bz) || SAXISCCTDATA[2]; // rv 1 + assign SAXISCCTDATA_in[30] = (SAXISCCTDATA[30] === 1'bz) || SAXISCCTDATA[30]; // rv 1 + assign SAXISCCTDATA_in[31] = (SAXISCCTDATA[31] === 1'bz) || SAXISCCTDATA[31]; // rv 1 + assign SAXISCCTDATA_in[32] = (SAXISCCTDATA[32] === 1'bz) || SAXISCCTDATA[32]; // rv 1 + assign SAXISCCTDATA_in[33] = (SAXISCCTDATA[33] === 1'bz) || SAXISCCTDATA[33]; // rv 1 + assign SAXISCCTDATA_in[34] = (SAXISCCTDATA[34] === 1'bz) || SAXISCCTDATA[34]; // rv 1 + assign SAXISCCTDATA_in[35] = (SAXISCCTDATA[35] === 1'bz) || SAXISCCTDATA[35]; // rv 1 + assign SAXISCCTDATA_in[36] = (SAXISCCTDATA[36] === 1'bz) || SAXISCCTDATA[36]; // rv 1 + assign SAXISCCTDATA_in[37] = (SAXISCCTDATA[37] === 1'bz) || SAXISCCTDATA[37]; // rv 1 + assign SAXISCCTDATA_in[38] = (SAXISCCTDATA[38] === 1'bz) || SAXISCCTDATA[38]; // rv 1 + assign SAXISCCTDATA_in[39] = (SAXISCCTDATA[39] === 1'bz) || SAXISCCTDATA[39]; // rv 1 + assign SAXISCCTDATA_in[3] = (SAXISCCTDATA[3] === 1'bz) || SAXISCCTDATA[3]; // rv 1 + assign SAXISCCTDATA_in[40] = (SAXISCCTDATA[40] === 1'bz) || SAXISCCTDATA[40]; // rv 1 + assign SAXISCCTDATA_in[41] = (SAXISCCTDATA[41] === 1'bz) || SAXISCCTDATA[41]; // rv 1 + assign SAXISCCTDATA_in[42] = (SAXISCCTDATA[42] === 1'bz) || SAXISCCTDATA[42]; // rv 1 + assign SAXISCCTDATA_in[43] = (SAXISCCTDATA[43] === 1'bz) || SAXISCCTDATA[43]; // rv 1 + assign SAXISCCTDATA_in[44] = (SAXISCCTDATA[44] === 1'bz) || SAXISCCTDATA[44]; // rv 1 + assign SAXISCCTDATA_in[45] = (SAXISCCTDATA[45] === 1'bz) || SAXISCCTDATA[45]; // rv 1 + assign SAXISCCTDATA_in[46] = (SAXISCCTDATA[46] === 1'bz) || SAXISCCTDATA[46]; // rv 1 + assign SAXISCCTDATA_in[47] = (SAXISCCTDATA[47] === 1'bz) || SAXISCCTDATA[47]; // rv 1 + assign SAXISCCTDATA_in[48] = (SAXISCCTDATA[48] === 1'bz) || SAXISCCTDATA[48]; // rv 1 + assign SAXISCCTDATA_in[49] = (SAXISCCTDATA[49] === 1'bz) || SAXISCCTDATA[49]; // rv 1 + assign SAXISCCTDATA_in[4] = (SAXISCCTDATA[4] === 1'bz) || SAXISCCTDATA[4]; // rv 1 + assign SAXISCCTDATA_in[50] = (SAXISCCTDATA[50] === 1'bz) || SAXISCCTDATA[50]; // rv 1 + assign SAXISCCTDATA_in[51] = (SAXISCCTDATA[51] === 1'bz) || SAXISCCTDATA[51]; // rv 1 + assign SAXISCCTDATA_in[52] = (SAXISCCTDATA[52] === 1'bz) || SAXISCCTDATA[52]; // rv 1 + assign SAXISCCTDATA_in[53] = (SAXISCCTDATA[53] === 1'bz) || SAXISCCTDATA[53]; // rv 1 + assign SAXISCCTDATA_in[54] = (SAXISCCTDATA[54] === 1'bz) || SAXISCCTDATA[54]; // rv 1 + assign SAXISCCTDATA_in[55] = (SAXISCCTDATA[55] === 1'bz) || SAXISCCTDATA[55]; // rv 1 + assign SAXISCCTDATA_in[56] = (SAXISCCTDATA[56] === 1'bz) || SAXISCCTDATA[56]; // rv 1 + assign SAXISCCTDATA_in[57] = (SAXISCCTDATA[57] === 1'bz) || SAXISCCTDATA[57]; // rv 1 + assign SAXISCCTDATA_in[58] = (SAXISCCTDATA[58] === 1'bz) || SAXISCCTDATA[58]; // rv 1 + assign SAXISCCTDATA_in[59] = (SAXISCCTDATA[59] === 1'bz) || SAXISCCTDATA[59]; // rv 1 + assign SAXISCCTDATA_in[5] = (SAXISCCTDATA[5] === 1'bz) || SAXISCCTDATA[5]; // rv 1 + assign SAXISCCTDATA_in[60] = (SAXISCCTDATA[60] === 1'bz) || SAXISCCTDATA[60]; // rv 1 + assign SAXISCCTDATA_in[61] = (SAXISCCTDATA[61] === 1'bz) || SAXISCCTDATA[61]; // rv 1 + assign SAXISCCTDATA_in[62] = (SAXISCCTDATA[62] === 1'bz) || SAXISCCTDATA[62]; // rv 1 + assign SAXISCCTDATA_in[63] = (SAXISCCTDATA[63] === 1'bz) || SAXISCCTDATA[63]; // rv 1 + assign SAXISCCTDATA_in[64] = (SAXISCCTDATA[64] === 1'bz) || SAXISCCTDATA[64]; // rv 1 + assign SAXISCCTDATA_in[65] = (SAXISCCTDATA[65] === 1'bz) || SAXISCCTDATA[65]; // rv 1 + assign SAXISCCTDATA_in[66] = (SAXISCCTDATA[66] === 1'bz) || SAXISCCTDATA[66]; // rv 1 + assign SAXISCCTDATA_in[67] = (SAXISCCTDATA[67] === 1'bz) || SAXISCCTDATA[67]; // rv 1 + assign SAXISCCTDATA_in[68] = (SAXISCCTDATA[68] === 1'bz) || SAXISCCTDATA[68]; // rv 1 + assign SAXISCCTDATA_in[69] = (SAXISCCTDATA[69] === 1'bz) || SAXISCCTDATA[69]; // rv 1 + assign SAXISCCTDATA_in[6] = (SAXISCCTDATA[6] === 1'bz) || SAXISCCTDATA[6]; // rv 1 + assign SAXISCCTDATA_in[70] = (SAXISCCTDATA[70] === 1'bz) || SAXISCCTDATA[70]; // rv 1 + assign SAXISCCTDATA_in[71] = (SAXISCCTDATA[71] === 1'bz) || SAXISCCTDATA[71]; // rv 1 + assign SAXISCCTDATA_in[72] = (SAXISCCTDATA[72] === 1'bz) || SAXISCCTDATA[72]; // rv 1 + assign SAXISCCTDATA_in[73] = (SAXISCCTDATA[73] === 1'bz) || SAXISCCTDATA[73]; // rv 1 + assign SAXISCCTDATA_in[74] = (SAXISCCTDATA[74] === 1'bz) || SAXISCCTDATA[74]; // rv 1 + assign SAXISCCTDATA_in[75] = (SAXISCCTDATA[75] === 1'bz) || SAXISCCTDATA[75]; // rv 1 + assign SAXISCCTDATA_in[76] = (SAXISCCTDATA[76] === 1'bz) || SAXISCCTDATA[76]; // rv 1 + assign SAXISCCTDATA_in[77] = (SAXISCCTDATA[77] === 1'bz) || SAXISCCTDATA[77]; // rv 1 + assign SAXISCCTDATA_in[78] = (SAXISCCTDATA[78] === 1'bz) || SAXISCCTDATA[78]; // rv 1 + assign SAXISCCTDATA_in[79] = (SAXISCCTDATA[79] === 1'bz) || SAXISCCTDATA[79]; // rv 1 + assign SAXISCCTDATA_in[7] = (SAXISCCTDATA[7] === 1'bz) || SAXISCCTDATA[7]; // rv 1 + assign SAXISCCTDATA_in[80] = (SAXISCCTDATA[80] === 1'bz) || SAXISCCTDATA[80]; // rv 1 + assign SAXISCCTDATA_in[81] = (SAXISCCTDATA[81] === 1'bz) || SAXISCCTDATA[81]; // rv 1 + assign SAXISCCTDATA_in[82] = (SAXISCCTDATA[82] === 1'bz) || SAXISCCTDATA[82]; // rv 1 + assign SAXISCCTDATA_in[83] = (SAXISCCTDATA[83] === 1'bz) || SAXISCCTDATA[83]; // rv 1 + assign SAXISCCTDATA_in[84] = (SAXISCCTDATA[84] === 1'bz) || SAXISCCTDATA[84]; // rv 1 + assign SAXISCCTDATA_in[85] = (SAXISCCTDATA[85] === 1'bz) || SAXISCCTDATA[85]; // rv 1 + assign SAXISCCTDATA_in[86] = (SAXISCCTDATA[86] === 1'bz) || SAXISCCTDATA[86]; // rv 1 + assign SAXISCCTDATA_in[87] = (SAXISCCTDATA[87] === 1'bz) || SAXISCCTDATA[87]; // rv 1 + assign SAXISCCTDATA_in[88] = (SAXISCCTDATA[88] === 1'bz) || SAXISCCTDATA[88]; // rv 1 + assign SAXISCCTDATA_in[89] = (SAXISCCTDATA[89] === 1'bz) || SAXISCCTDATA[89]; // rv 1 + assign SAXISCCTDATA_in[8] = (SAXISCCTDATA[8] === 1'bz) || SAXISCCTDATA[8]; // rv 1 + assign SAXISCCTDATA_in[90] = (SAXISCCTDATA[90] === 1'bz) || SAXISCCTDATA[90]; // rv 1 + assign SAXISCCTDATA_in[91] = (SAXISCCTDATA[91] === 1'bz) || SAXISCCTDATA[91]; // rv 1 + assign SAXISCCTDATA_in[92] = (SAXISCCTDATA[92] === 1'bz) || SAXISCCTDATA[92]; // rv 1 + assign SAXISCCTDATA_in[93] = (SAXISCCTDATA[93] === 1'bz) || SAXISCCTDATA[93]; // rv 1 + assign SAXISCCTDATA_in[94] = (SAXISCCTDATA[94] === 1'bz) || SAXISCCTDATA[94]; // rv 1 + assign SAXISCCTDATA_in[95] = (SAXISCCTDATA[95] === 1'bz) || SAXISCCTDATA[95]; // rv 1 + assign SAXISCCTDATA_in[96] = (SAXISCCTDATA[96] === 1'bz) || SAXISCCTDATA[96]; // rv 1 + assign SAXISCCTDATA_in[97] = (SAXISCCTDATA[97] === 1'bz) || SAXISCCTDATA[97]; // rv 1 + assign SAXISCCTDATA_in[98] = (SAXISCCTDATA[98] === 1'bz) || SAXISCCTDATA[98]; // rv 1 + assign SAXISCCTDATA_in[99] = (SAXISCCTDATA[99] === 1'bz) || SAXISCCTDATA[99]; // rv 1 + assign SAXISCCTDATA_in[9] = (SAXISCCTDATA[9] === 1'bz) || SAXISCCTDATA[9]; // rv 1 + assign SAXISCCTKEEP_in[0] = (SAXISCCTKEEP[0] !== 1'bz) && SAXISCCTKEEP[0]; // rv 0 + assign SAXISCCTKEEP_in[1] = (SAXISCCTKEEP[1] !== 1'bz) && SAXISCCTKEEP[1]; // rv 0 + assign SAXISCCTKEEP_in[2] = (SAXISCCTKEEP[2] !== 1'bz) && SAXISCCTKEEP[2]; // rv 0 + assign SAXISCCTKEEP_in[3] = (SAXISCCTKEEP[3] !== 1'bz) && SAXISCCTKEEP[3]; // rv 0 + assign SAXISCCTKEEP_in[4] = (SAXISCCTKEEP[4] !== 1'bz) && SAXISCCTKEEP[4]; // rv 0 + assign SAXISCCTKEEP_in[5] = (SAXISCCTKEEP[5] !== 1'bz) && SAXISCCTKEEP[5]; // rv 0 + assign SAXISCCTKEEP_in[6] = (SAXISCCTKEEP[6] !== 1'bz) && SAXISCCTKEEP[6]; // rv 0 + assign SAXISCCTKEEP_in[7] = (SAXISCCTKEEP[7] !== 1'bz) && SAXISCCTKEEP[7]; // rv 0 + assign SAXISCCTLAST_in = (SAXISCCTLAST === 1'bz) || SAXISCCTLAST; // rv 1 + assign SAXISCCTUSER_in[0] = (SAXISCCTUSER[0] === 1'bz) || SAXISCCTUSER[0]; // rv 1 + assign SAXISCCTUSER_in[10] = (SAXISCCTUSER[10] === 1'bz) || SAXISCCTUSER[10]; // rv 1 + assign SAXISCCTUSER_in[11] = (SAXISCCTUSER[11] === 1'bz) || SAXISCCTUSER[11]; // rv 1 + assign SAXISCCTUSER_in[12] = (SAXISCCTUSER[12] === 1'bz) || SAXISCCTUSER[12]; // rv 1 + assign SAXISCCTUSER_in[13] = (SAXISCCTUSER[13] === 1'bz) || SAXISCCTUSER[13]; // rv 1 + assign SAXISCCTUSER_in[14] = (SAXISCCTUSER[14] === 1'bz) || SAXISCCTUSER[14]; // rv 1 + assign SAXISCCTUSER_in[15] = (SAXISCCTUSER[15] === 1'bz) || SAXISCCTUSER[15]; // rv 1 + assign SAXISCCTUSER_in[16] = (SAXISCCTUSER[16] === 1'bz) || SAXISCCTUSER[16]; // rv 1 + assign SAXISCCTUSER_in[17] = (SAXISCCTUSER[17] === 1'bz) || SAXISCCTUSER[17]; // rv 1 + assign SAXISCCTUSER_in[18] = (SAXISCCTUSER[18] === 1'bz) || SAXISCCTUSER[18]; // rv 1 + assign SAXISCCTUSER_in[19] = (SAXISCCTUSER[19] === 1'bz) || SAXISCCTUSER[19]; // rv 1 + assign SAXISCCTUSER_in[1] = (SAXISCCTUSER[1] === 1'bz) || SAXISCCTUSER[1]; // rv 1 + assign SAXISCCTUSER_in[20] = (SAXISCCTUSER[20] === 1'bz) || SAXISCCTUSER[20]; // rv 1 + assign SAXISCCTUSER_in[21] = (SAXISCCTUSER[21] === 1'bz) || SAXISCCTUSER[21]; // rv 1 + assign SAXISCCTUSER_in[22] = (SAXISCCTUSER[22] === 1'bz) || SAXISCCTUSER[22]; // rv 1 + assign SAXISCCTUSER_in[23] = (SAXISCCTUSER[23] === 1'bz) || SAXISCCTUSER[23]; // rv 1 + assign SAXISCCTUSER_in[24] = (SAXISCCTUSER[24] === 1'bz) || SAXISCCTUSER[24]; // rv 1 + assign SAXISCCTUSER_in[25] = (SAXISCCTUSER[25] === 1'bz) || SAXISCCTUSER[25]; // rv 1 + assign SAXISCCTUSER_in[26] = (SAXISCCTUSER[26] === 1'bz) || SAXISCCTUSER[26]; // rv 1 + assign SAXISCCTUSER_in[27] = (SAXISCCTUSER[27] === 1'bz) || SAXISCCTUSER[27]; // rv 1 + assign SAXISCCTUSER_in[28] = (SAXISCCTUSER[28] === 1'bz) || SAXISCCTUSER[28]; // rv 1 + assign SAXISCCTUSER_in[29] = (SAXISCCTUSER[29] === 1'bz) || SAXISCCTUSER[29]; // rv 1 + assign SAXISCCTUSER_in[2] = (SAXISCCTUSER[2] === 1'bz) || SAXISCCTUSER[2]; // rv 1 + assign SAXISCCTUSER_in[30] = (SAXISCCTUSER[30] === 1'bz) || SAXISCCTUSER[30]; // rv 1 + assign SAXISCCTUSER_in[31] = (SAXISCCTUSER[31] === 1'bz) || SAXISCCTUSER[31]; // rv 1 + assign SAXISCCTUSER_in[32] = (SAXISCCTUSER[32] === 1'bz) || SAXISCCTUSER[32]; // rv 1 + assign SAXISCCTUSER_in[3] = (SAXISCCTUSER[3] === 1'bz) || SAXISCCTUSER[3]; // rv 1 + assign SAXISCCTUSER_in[4] = (SAXISCCTUSER[4] === 1'bz) || SAXISCCTUSER[4]; // rv 1 + assign SAXISCCTUSER_in[5] = (SAXISCCTUSER[5] === 1'bz) || SAXISCCTUSER[5]; // rv 1 + assign SAXISCCTUSER_in[6] = (SAXISCCTUSER[6] === 1'bz) || SAXISCCTUSER[6]; // rv 1 + assign SAXISCCTUSER_in[7] = (SAXISCCTUSER[7] === 1'bz) || SAXISCCTUSER[7]; // rv 1 + assign SAXISCCTUSER_in[8] = (SAXISCCTUSER[8] === 1'bz) || SAXISCCTUSER[8]; // rv 1 + assign SAXISCCTUSER_in[9] = (SAXISCCTUSER[9] === 1'bz) || SAXISCCTUSER[9]; // rv 1 + assign SAXISCCTVALID_in = (SAXISCCTVALID !== 1'bz) && SAXISCCTVALID; // rv 0 + assign SAXISRQTDATA_in[0] = (SAXISRQTDATA[0] === 1'bz) || SAXISRQTDATA[0]; // rv 1 + assign SAXISRQTDATA_in[100] = (SAXISRQTDATA[100] === 1'bz) || SAXISRQTDATA[100]; // rv 1 + assign SAXISRQTDATA_in[101] = (SAXISRQTDATA[101] === 1'bz) || SAXISRQTDATA[101]; // rv 1 + assign SAXISRQTDATA_in[102] = (SAXISRQTDATA[102] === 1'bz) || SAXISRQTDATA[102]; // rv 1 + assign SAXISRQTDATA_in[103] = (SAXISRQTDATA[103] === 1'bz) || SAXISRQTDATA[103]; // rv 1 + assign SAXISRQTDATA_in[104] = (SAXISRQTDATA[104] === 1'bz) || SAXISRQTDATA[104]; // rv 1 + assign SAXISRQTDATA_in[105] = (SAXISRQTDATA[105] === 1'bz) || SAXISRQTDATA[105]; // rv 1 + assign SAXISRQTDATA_in[106] = (SAXISRQTDATA[106] === 1'bz) || SAXISRQTDATA[106]; // rv 1 + assign SAXISRQTDATA_in[107] = (SAXISRQTDATA[107] === 1'bz) || SAXISRQTDATA[107]; // rv 1 + assign SAXISRQTDATA_in[108] = (SAXISRQTDATA[108] === 1'bz) || SAXISRQTDATA[108]; // rv 1 + assign SAXISRQTDATA_in[109] = (SAXISRQTDATA[109] === 1'bz) || SAXISRQTDATA[109]; // rv 1 + assign SAXISRQTDATA_in[10] = (SAXISRQTDATA[10] === 1'bz) || SAXISRQTDATA[10]; // rv 1 + assign SAXISRQTDATA_in[110] = (SAXISRQTDATA[110] === 1'bz) || SAXISRQTDATA[110]; // rv 1 + assign SAXISRQTDATA_in[111] = (SAXISRQTDATA[111] === 1'bz) || SAXISRQTDATA[111]; // rv 1 + assign SAXISRQTDATA_in[112] = (SAXISRQTDATA[112] === 1'bz) || SAXISRQTDATA[112]; // rv 1 + assign SAXISRQTDATA_in[113] = (SAXISRQTDATA[113] === 1'bz) || SAXISRQTDATA[113]; // rv 1 + assign SAXISRQTDATA_in[114] = (SAXISRQTDATA[114] === 1'bz) || SAXISRQTDATA[114]; // rv 1 + assign SAXISRQTDATA_in[115] = (SAXISRQTDATA[115] === 1'bz) || SAXISRQTDATA[115]; // rv 1 + assign SAXISRQTDATA_in[116] = (SAXISRQTDATA[116] === 1'bz) || SAXISRQTDATA[116]; // rv 1 + assign SAXISRQTDATA_in[117] = (SAXISRQTDATA[117] === 1'bz) || SAXISRQTDATA[117]; // rv 1 + assign SAXISRQTDATA_in[118] = (SAXISRQTDATA[118] === 1'bz) || SAXISRQTDATA[118]; // rv 1 + assign SAXISRQTDATA_in[119] = (SAXISRQTDATA[119] === 1'bz) || SAXISRQTDATA[119]; // rv 1 + assign SAXISRQTDATA_in[11] = (SAXISRQTDATA[11] === 1'bz) || SAXISRQTDATA[11]; // rv 1 + assign SAXISRQTDATA_in[120] = (SAXISRQTDATA[120] === 1'bz) || SAXISRQTDATA[120]; // rv 1 + assign SAXISRQTDATA_in[121] = (SAXISRQTDATA[121] === 1'bz) || SAXISRQTDATA[121]; // rv 1 + assign SAXISRQTDATA_in[122] = (SAXISRQTDATA[122] === 1'bz) || SAXISRQTDATA[122]; // rv 1 + assign SAXISRQTDATA_in[123] = (SAXISRQTDATA[123] === 1'bz) || SAXISRQTDATA[123]; // rv 1 + assign SAXISRQTDATA_in[124] = (SAXISRQTDATA[124] === 1'bz) || SAXISRQTDATA[124]; // rv 1 + assign SAXISRQTDATA_in[125] = (SAXISRQTDATA[125] === 1'bz) || SAXISRQTDATA[125]; // rv 1 + assign SAXISRQTDATA_in[126] = (SAXISRQTDATA[126] === 1'bz) || SAXISRQTDATA[126]; // rv 1 + assign SAXISRQTDATA_in[127] = (SAXISRQTDATA[127] === 1'bz) || SAXISRQTDATA[127]; // rv 1 + assign SAXISRQTDATA_in[128] = (SAXISRQTDATA[128] === 1'bz) || SAXISRQTDATA[128]; // rv 1 + assign SAXISRQTDATA_in[129] = (SAXISRQTDATA[129] === 1'bz) || SAXISRQTDATA[129]; // rv 1 + assign SAXISRQTDATA_in[12] = (SAXISRQTDATA[12] === 1'bz) || SAXISRQTDATA[12]; // rv 1 + assign SAXISRQTDATA_in[130] = (SAXISRQTDATA[130] === 1'bz) || SAXISRQTDATA[130]; // rv 1 + assign SAXISRQTDATA_in[131] = (SAXISRQTDATA[131] === 1'bz) || SAXISRQTDATA[131]; // rv 1 + assign SAXISRQTDATA_in[132] = (SAXISRQTDATA[132] === 1'bz) || SAXISRQTDATA[132]; // rv 1 + assign SAXISRQTDATA_in[133] = (SAXISRQTDATA[133] === 1'bz) || SAXISRQTDATA[133]; // rv 1 + assign SAXISRQTDATA_in[134] = (SAXISRQTDATA[134] === 1'bz) || SAXISRQTDATA[134]; // rv 1 + assign SAXISRQTDATA_in[135] = (SAXISRQTDATA[135] === 1'bz) || SAXISRQTDATA[135]; // rv 1 + assign SAXISRQTDATA_in[136] = (SAXISRQTDATA[136] === 1'bz) || SAXISRQTDATA[136]; // rv 1 + assign SAXISRQTDATA_in[137] = (SAXISRQTDATA[137] === 1'bz) || SAXISRQTDATA[137]; // rv 1 + assign SAXISRQTDATA_in[138] = (SAXISRQTDATA[138] === 1'bz) || SAXISRQTDATA[138]; // rv 1 + assign SAXISRQTDATA_in[139] = (SAXISRQTDATA[139] === 1'bz) || SAXISRQTDATA[139]; // rv 1 + assign SAXISRQTDATA_in[13] = (SAXISRQTDATA[13] === 1'bz) || SAXISRQTDATA[13]; // rv 1 + assign SAXISRQTDATA_in[140] = (SAXISRQTDATA[140] === 1'bz) || SAXISRQTDATA[140]; // rv 1 + assign SAXISRQTDATA_in[141] = (SAXISRQTDATA[141] === 1'bz) || SAXISRQTDATA[141]; // rv 1 + assign SAXISRQTDATA_in[142] = (SAXISRQTDATA[142] === 1'bz) || SAXISRQTDATA[142]; // rv 1 + assign SAXISRQTDATA_in[143] = (SAXISRQTDATA[143] === 1'bz) || SAXISRQTDATA[143]; // rv 1 + assign SAXISRQTDATA_in[144] = (SAXISRQTDATA[144] === 1'bz) || SAXISRQTDATA[144]; // rv 1 + assign SAXISRQTDATA_in[145] = (SAXISRQTDATA[145] === 1'bz) || SAXISRQTDATA[145]; // rv 1 + assign SAXISRQTDATA_in[146] = (SAXISRQTDATA[146] === 1'bz) || SAXISRQTDATA[146]; // rv 1 + assign SAXISRQTDATA_in[147] = (SAXISRQTDATA[147] === 1'bz) || SAXISRQTDATA[147]; // rv 1 + assign SAXISRQTDATA_in[148] = (SAXISRQTDATA[148] === 1'bz) || SAXISRQTDATA[148]; // rv 1 + assign SAXISRQTDATA_in[149] = (SAXISRQTDATA[149] === 1'bz) || SAXISRQTDATA[149]; // rv 1 + assign SAXISRQTDATA_in[14] = (SAXISRQTDATA[14] === 1'bz) || SAXISRQTDATA[14]; // rv 1 + assign SAXISRQTDATA_in[150] = (SAXISRQTDATA[150] === 1'bz) || SAXISRQTDATA[150]; // rv 1 + assign SAXISRQTDATA_in[151] = (SAXISRQTDATA[151] === 1'bz) || SAXISRQTDATA[151]; // rv 1 + assign SAXISRQTDATA_in[152] = (SAXISRQTDATA[152] === 1'bz) || SAXISRQTDATA[152]; // rv 1 + assign SAXISRQTDATA_in[153] = (SAXISRQTDATA[153] === 1'bz) || SAXISRQTDATA[153]; // rv 1 + assign SAXISRQTDATA_in[154] = (SAXISRQTDATA[154] === 1'bz) || SAXISRQTDATA[154]; // rv 1 + assign SAXISRQTDATA_in[155] = (SAXISRQTDATA[155] === 1'bz) || SAXISRQTDATA[155]; // rv 1 + assign SAXISRQTDATA_in[156] = (SAXISRQTDATA[156] === 1'bz) || SAXISRQTDATA[156]; // rv 1 + assign SAXISRQTDATA_in[157] = (SAXISRQTDATA[157] === 1'bz) || SAXISRQTDATA[157]; // rv 1 + assign SAXISRQTDATA_in[158] = (SAXISRQTDATA[158] === 1'bz) || SAXISRQTDATA[158]; // rv 1 + assign SAXISRQTDATA_in[159] = (SAXISRQTDATA[159] === 1'bz) || SAXISRQTDATA[159]; // rv 1 + assign SAXISRQTDATA_in[15] = (SAXISRQTDATA[15] === 1'bz) || SAXISRQTDATA[15]; // rv 1 + assign SAXISRQTDATA_in[160] = (SAXISRQTDATA[160] === 1'bz) || SAXISRQTDATA[160]; // rv 1 + assign SAXISRQTDATA_in[161] = (SAXISRQTDATA[161] === 1'bz) || SAXISRQTDATA[161]; // rv 1 + assign SAXISRQTDATA_in[162] = (SAXISRQTDATA[162] === 1'bz) || SAXISRQTDATA[162]; // rv 1 + assign SAXISRQTDATA_in[163] = (SAXISRQTDATA[163] === 1'bz) || SAXISRQTDATA[163]; // rv 1 + assign SAXISRQTDATA_in[164] = (SAXISRQTDATA[164] === 1'bz) || SAXISRQTDATA[164]; // rv 1 + assign SAXISRQTDATA_in[165] = (SAXISRQTDATA[165] === 1'bz) || SAXISRQTDATA[165]; // rv 1 + assign SAXISRQTDATA_in[166] = (SAXISRQTDATA[166] === 1'bz) || SAXISRQTDATA[166]; // rv 1 + assign SAXISRQTDATA_in[167] = (SAXISRQTDATA[167] === 1'bz) || SAXISRQTDATA[167]; // rv 1 + assign SAXISRQTDATA_in[168] = (SAXISRQTDATA[168] === 1'bz) || SAXISRQTDATA[168]; // rv 1 + assign SAXISRQTDATA_in[169] = (SAXISRQTDATA[169] === 1'bz) || SAXISRQTDATA[169]; // rv 1 + assign SAXISRQTDATA_in[16] = (SAXISRQTDATA[16] === 1'bz) || SAXISRQTDATA[16]; // rv 1 + assign SAXISRQTDATA_in[170] = (SAXISRQTDATA[170] === 1'bz) || SAXISRQTDATA[170]; // rv 1 + assign SAXISRQTDATA_in[171] = (SAXISRQTDATA[171] === 1'bz) || SAXISRQTDATA[171]; // rv 1 + assign SAXISRQTDATA_in[172] = (SAXISRQTDATA[172] === 1'bz) || SAXISRQTDATA[172]; // rv 1 + assign SAXISRQTDATA_in[173] = (SAXISRQTDATA[173] === 1'bz) || SAXISRQTDATA[173]; // rv 1 + assign SAXISRQTDATA_in[174] = (SAXISRQTDATA[174] === 1'bz) || SAXISRQTDATA[174]; // rv 1 + assign SAXISRQTDATA_in[175] = (SAXISRQTDATA[175] === 1'bz) || SAXISRQTDATA[175]; // rv 1 + assign SAXISRQTDATA_in[176] = (SAXISRQTDATA[176] === 1'bz) || SAXISRQTDATA[176]; // rv 1 + assign SAXISRQTDATA_in[177] = (SAXISRQTDATA[177] === 1'bz) || SAXISRQTDATA[177]; // rv 1 + assign SAXISRQTDATA_in[178] = (SAXISRQTDATA[178] === 1'bz) || SAXISRQTDATA[178]; // rv 1 + assign SAXISRQTDATA_in[179] = (SAXISRQTDATA[179] === 1'bz) || SAXISRQTDATA[179]; // rv 1 + assign SAXISRQTDATA_in[17] = (SAXISRQTDATA[17] === 1'bz) || SAXISRQTDATA[17]; // rv 1 + assign SAXISRQTDATA_in[180] = (SAXISRQTDATA[180] === 1'bz) || SAXISRQTDATA[180]; // rv 1 + assign SAXISRQTDATA_in[181] = (SAXISRQTDATA[181] === 1'bz) || SAXISRQTDATA[181]; // rv 1 + assign SAXISRQTDATA_in[182] = (SAXISRQTDATA[182] === 1'bz) || SAXISRQTDATA[182]; // rv 1 + assign SAXISRQTDATA_in[183] = (SAXISRQTDATA[183] === 1'bz) || SAXISRQTDATA[183]; // rv 1 + assign SAXISRQTDATA_in[184] = (SAXISRQTDATA[184] === 1'bz) || SAXISRQTDATA[184]; // rv 1 + assign SAXISRQTDATA_in[185] = (SAXISRQTDATA[185] === 1'bz) || SAXISRQTDATA[185]; // rv 1 + assign SAXISRQTDATA_in[186] = (SAXISRQTDATA[186] === 1'bz) || SAXISRQTDATA[186]; // rv 1 + assign SAXISRQTDATA_in[187] = (SAXISRQTDATA[187] === 1'bz) || SAXISRQTDATA[187]; // rv 1 + assign SAXISRQTDATA_in[188] = (SAXISRQTDATA[188] === 1'bz) || SAXISRQTDATA[188]; // rv 1 + assign SAXISRQTDATA_in[189] = (SAXISRQTDATA[189] === 1'bz) || SAXISRQTDATA[189]; // rv 1 + assign SAXISRQTDATA_in[18] = (SAXISRQTDATA[18] === 1'bz) || SAXISRQTDATA[18]; // rv 1 + assign SAXISRQTDATA_in[190] = (SAXISRQTDATA[190] === 1'bz) || SAXISRQTDATA[190]; // rv 1 + assign SAXISRQTDATA_in[191] = (SAXISRQTDATA[191] === 1'bz) || SAXISRQTDATA[191]; // rv 1 + assign SAXISRQTDATA_in[192] = (SAXISRQTDATA[192] === 1'bz) || SAXISRQTDATA[192]; // rv 1 + assign SAXISRQTDATA_in[193] = (SAXISRQTDATA[193] === 1'bz) || SAXISRQTDATA[193]; // rv 1 + assign SAXISRQTDATA_in[194] = (SAXISRQTDATA[194] === 1'bz) || SAXISRQTDATA[194]; // rv 1 + assign SAXISRQTDATA_in[195] = (SAXISRQTDATA[195] === 1'bz) || SAXISRQTDATA[195]; // rv 1 + assign SAXISRQTDATA_in[196] = (SAXISRQTDATA[196] === 1'bz) || SAXISRQTDATA[196]; // rv 1 + assign SAXISRQTDATA_in[197] = (SAXISRQTDATA[197] === 1'bz) || SAXISRQTDATA[197]; // rv 1 + assign SAXISRQTDATA_in[198] = (SAXISRQTDATA[198] === 1'bz) || SAXISRQTDATA[198]; // rv 1 + assign SAXISRQTDATA_in[199] = (SAXISRQTDATA[199] === 1'bz) || SAXISRQTDATA[199]; // rv 1 + assign SAXISRQTDATA_in[19] = (SAXISRQTDATA[19] === 1'bz) || SAXISRQTDATA[19]; // rv 1 + assign SAXISRQTDATA_in[1] = (SAXISRQTDATA[1] === 1'bz) || SAXISRQTDATA[1]; // rv 1 + assign SAXISRQTDATA_in[200] = (SAXISRQTDATA[200] === 1'bz) || SAXISRQTDATA[200]; // rv 1 + assign SAXISRQTDATA_in[201] = (SAXISRQTDATA[201] === 1'bz) || SAXISRQTDATA[201]; // rv 1 + assign SAXISRQTDATA_in[202] = (SAXISRQTDATA[202] === 1'bz) || SAXISRQTDATA[202]; // rv 1 + assign SAXISRQTDATA_in[203] = (SAXISRQTDATA[203] === 1'bz) || SAXISRQTDATA[203]; // rv 1 + assign SAXISRQTDATA_in[204] = (SAXISRQTDATA[204] === 1'bz) || SAXISRQTDATA[204]; // rv 1 + assign SAXISRQTDATA_in[205] = (SAXISRQTDATA[205] === 1'bz) || SAXISRQTDATA[205]; // rv 1 + assign SAXISRQTDATA_in[206] = (SAXISRQTDATA[206] === 1'bz) || SAXISRQTDATA[206]; // rv 1 + assign SAXISRQTDATA_in[207] = (SAXISRQTDATA[207] === 1'bz) || SAXISRQTDATA[207]; // rv 1 + assign SAXISRQTDATA_in[208] = (SAXISRQTDATA[208] === 1'bz) || SAXISRQTDATA[208]; // rv 1 + assign SAXISRQTDATA_in[209] = (SAXISRQTDATA[209] === 1'bz) || SAXISRQTDATA[209]; // rv 1 + assign SAXISRQTDATA_in[20] = (SAXISRQTDATA[20] === 1'bz) || SAXISRQTDATA[20]; // rv 1 + assign SAXISRQTDATA_in[210] = (SAXISRQTDATA[210] === 1'bz) || SAXISRQTDATA[210]; // rv 1 + assign SAXISRQTDATA_in[211] = (SAXISRQTDATA[211] === 1'bz) || SAXISRQTDATA[211]; // rv 1 + assign SAXISRQTDATA_in[212] = (SAXISRQTDATA[212] === 1'bz) || SAXISRQTDATA[212]; // rv 1 + assign SAXISRQTDATA_in[213] = (SAXISRQTDATA[213] === 1'bz) || SAXISRQTDATA[213]; // rv 1 + assign SAXISRQTDATA_in[214] = (SAXISRQTDATA[214] === 1'bz) || SAXISRQTDATA[214]; // rv 1 + assign SAXISRQTDATA_in[215] = (SAXISRQTDATA[215] === 1'bz) || SAXISRQTDATA[215]; // rv 1 + assign SAXISRQTDATA_in[216] = (SAXISRQTDATA[216] === 1'bz) || SAXISRQTDATA[216]; // rv 1 + assign SAXISRQTDATA_in[217] = (SAXISRQTDATA[217] === 1'bz) || SAXISRQTDATA[217]; // rv 1 + assign SAXISRQTDATA_in[218] = (SAXISRQTDATA[218] === 1'bz) || SAXISRQTDATA[218]; // rv 1 + assign SAXISRQTDATA_in[219] = (SAXISRQTDATA[219] === 1'bz) || SAXISRQTDATA[219]; // rv 1 + assign SAXISRQTDATA_in[21] = (SAXISRQTDATA[21] === 1'bz) || SAXISRQTDATA[21]; // rv 1 + assign SAXISRQTDATA_in[220] = (SAXISRQTDATA[220] === 1'bz) || SAXISRQTDATA[220]; // rv 1 + assign SAXISRQTDATA_in[221] = (SAXISRQTDATA[221] === 1'bz) || SAXISRQTDATA[221]; // rv 1 + assign SAXISRQTDATA_in[222] = (SAXISRQTDATA[222] === 1'bz) || SAXISRQTDATA[222]; // rv 1 + assign SAXISRQTDATA_in[223] = (SAXISRQTDATA[223] === 1'bz) || SAXISRQTDATA[223]; // rv 1 + assign SAXISRQTDATA_in[224] = (SAXISRQTDATA[224] === 1'bz) || SAXISRQTDATA[224]; // rv 1 + assign SAXISRQTDATA_in[225] = (SAXISRQTDATA[225] === 1'bz) || SAXISRQTDATA[225]; // rv 1 + assign SAXISRQTDATA_in[226] = (SAXISRQTDATA[226] === 1'bz) || SAXISRQTDATA[226]; // rv 1 + assign SAXISRQTDATA_in[227] = (SAXISRQTDATA[227] === 1'bz) || SAXISRQTDATA[227]; // rv 1 + assign SAXISRQTDATA_in[228] = (SAXISRQTDATA[228] === 1'bz) || SAXISRQTDATA[228]; // rv 1 + assign SAXISRQTDATA_in[229] = (SAXISRQTDATA[229] === 1'bz) || SAXISRQTDATA[229]; // rv 1 + assign SAXISRQTDATA_in[22] = (SAXISRQTDATA[22] === 1'bz) || SAXISRQTDATA[22]; // rv 1 + assign SAXISRQTDATA_in[230] = (SAXISRQTDATA[230] === 1'bz) || SAXISRQTDATA[230]; // rv 1 + assign SAXISRQTDATA_in[231] = (SAXISRQTDATA[231] === 1'bz) || SAXISRQTDATA[231]; // rv 1 + assign SAXISRQTDATA_in[232] = (SAXISRQTDATA[232] === 1'bz) || SAXISRQTDATA[232]; // rv 1 + assign SAXISRQTDATA_in[233] = (SAXISRQTDATA[233] === 1'bz) || SAXISRQTDATA[233]; // rv 1 + assign SAXISRQTDATA_in[234] = (SAXISRQTDATA[234] === 1'bz) || SAXISRQTDATA[234]; // rv 1 + assign SAXISRQTDATA_in[235] = (SAXISRQTDATA[235] === 1'bz) || SAXISRQTDATA[235]; // rv 1 + assign SAXISRQTDATA_in[236] = (SAXISRQTDATA[236] === 1'bz) || SAXISRQTDATA[236]; // rv 1 + assign SAXISRQTDATA_in[237] = (SAXISRQTDATA[237] === 1'bz) || SAXISRQTDATA[237]; // rv 1 + assign SAXISRQTDATA_in[238] = (SAXISRQTDATA[238] === 1'bz) || SAXISRQTDATA[238]; // rv 1 + assign SAXISRQTDATA_in[239] = (SAXISRQTDATA[239] === 1'bz) || SAXISRQTDATA[239]; // rv 1 + assign SAXISRQTDATA_in[23] = (SAXISRQTDATA[23] === 1'bz) || SAXISRQTDATA[23]; // rv 1 + assign SAXISRQTDATA_in[240] = (SAXISRQTDATA[240] === 1'bz) || SAXISRQTDATA[240]; // rv 1 + assign SAXISRQTDATA_in[241] = (SAXISRQTDATA[241] === 1'bz) || SAXISRQTDATA[241]; // rv 1 + assign SAXISRQTDATA_in[242] = (SAXISRQTDATA[242] === 1'bz) || SAXISRQTDATA[242]; // rv 1 + assign SAXISRQTDATA_in[243] = (SAXISRQTDATA[243] === 1'bz) || SAXISRQTDATA[243]; // rv 1 + assign SAXISRQTDATA_in[244] = (SAXISRQTDATA[244] === 1'bz) || SAXISRQTDATA[244]; // rv 1 + assign SAXISRQTDATA_in[245] = (SAXISRQTDATA[245] === 1'bz) || SAXISRQTDATA[245]; // rv 1 + assign SAXISRQTDATA_in[246] = (SAXISRQTDATA[246] === 1'bz) || SAXISRQTDATA[246]; // rv 1 + assign SAXISRQTDATA_in[247] = (SAXISRQTDATA[247] === 1'bz) || SAXISRQTDATA[247]; // rv 1 + assign SAXISRQTDATA_in[248] = (SAXISRQTDATA[248] === 1'bz) || SAXISRQTDATA[248]; // rv 1 + assign SAXISRQTDATA_in[249] = (SAXISRQTDATA[249] === 1'bz) || SAXISRQTDATA[249]; // rv 1 + assign SAXISRQTDATA_in[24] = (SAXISRQTDATA[24] === 1'bz) || SAXISRQTDATA[24]; // rv 1 + assign SAXISRQTDATA_in[250] = (SAXISRQTDATA[250] === 1'bz) || SAXISRQTDATA[250]; // rv 1 + assign SAXISRQTDATA_in[251] = (SAXISRQTDATA[251] === 1'bz) || SAXISRQTDATA[251]; // rv 1 + assign SAXISRQTDATA_in[252] = (SAXISRQTDATA[252] === 1'bz) || SAXISRQTDATA[252]; // rv 1 + assign SAXISRQTDATA_in[253] = (SAXISRQTDATA[253] === 1'bz) || SAXISRQTDATA[253]; // rv 1 + assign SAXISRQTDATA_in[254] = (SAXISRQTDATA[254] === 1'bz) || SAXISRQTDATA[254]; // rv 1 + assign SAXISRQTDATA_in[255] = (SAXISRQTDATA[255] === 1'bz) || SAXISRQTDATA[255]; // rv 1 + assign SAXISRQTDATA_in[25] = (SAXISRQTDATA[25] === 1'bz) || SAXISRQTDATA[25]; // rv 1 + assign SAXISRQTDATA_in[26] = (SAXISRQTDATA[26] === 1'bz) || SAXISRQTDATA[26]; // rv 1 + assign SAXISRQTDATA_in[27] = (SAXISRQTDATA[27] === 1'bz) || SAXISRQTDATA[27]; // rv 1 + assign SAXISRQTDATA_in[28] = (SAXISRQTDATA[28] === 1'bz) || SAXISRQTDATA[28]; // rv 1 + assign SAXISRQTDATA_in[29] = (SAXISRQTDATA[29] === 1'bz) || SAXISRQTDATA[29]; // rv 1 + assign SAXISRQTDATA_in[2] = (SAXISRQTDATA[2] === 1'bz) || SAXISRQTDATA[2]; // rv 1 + assign SAXISRQTDATA_in[30] = (SAXISRQTDATA[30] === 1'bz) || SAXISRQTDATA[30]; // rv 1 + assign SAXISRQTDATA_in[31] = (SAXISRQTDATA[31] === 1'bz) || SAXISRQTDATA[31]; // rv 1 + assign SAXISRQTDATA_in[32] = (SAXISRQTDATA[32] === 1'bz) || SAXISRQTDATA[32]; // rv 1 + assign SAXISRQTDATA_in[33] = (SAXISRQTDATA[33] === 1'bz) || SAXISRQTDATA[33]; // rv 1 + assign SAXISRQTDATA_in[34] = (SAXISRQTDATA[34] === 1'bz) || SAXISRQTDATA[34]; // rv 1 + assign SAXISRQTDATA_in[35] = (SAXISRQTDATA[35] === 1'bz) || SAXISRQTDATA[35]; // rv 1 + assign SAXISRQTDATA_in[36] = (SAXISRQTDATA[36] === 1'bz) || SAXISRQTDATA[36]; // rv 1 + assign SAXISRQTDATA_in[37] = (SAXISRQTDATA[37] === 1'bz) || SAXISRQTDATA[37]; // rv 1 + assign SAXISRQTDATA_in[38] = (SAXISRQTDATA[38] === 1'bz) || SAXISRQTDATA[38]; // rv 1 + assign SAXISRQTDATA_in[39] = (SAXISRQTDATA[39] === 1'bz) || SAXISRQTDATA[39]; // rv 1 + assign SAXISRQTDATA_in[3] = (SAXISRQTDATA[3] === 1'bz) || SAXISRQTDATA[3]; // rv 1 + assign SAXISRQTDATA_in[40] = (SAXISRQTDATA[40] === 1'bz) || SAXISRQTDATA[40]; // rv 1 + assign SAXISRQTDATA_in[41] = (SAXISRQTDATA[41] === 1'bz) || SAXISRQTDATA[41]; // rv 1 + assign SAXISRQTDATA_in[42] = (SAXISRQTDATA[42] === 1'bz) || SAXISRQTDATA[42]; // rv 1 + assign SAXISRQTDATA_in[43] = (SAXISRQTDATA[43] === 1'bz) || SAXISRQTDATA[43]; // rv 1 + assign SAXISRQTDATA_in[44] = (SAXISRQTDATA[44] === 1'bz) || SAXISRQTDATA[44]; // rv 1 + assign SAXISRQTDATA_in[45] = (SAXISRQTDATA[45] === 1'bz) || SAXISRQTDATA[45]; // rv 1 + assign SAXISRQTDATA_in[46] = (SAXISRQTDATA[46] === 1'bz) || SAXISRQTDATA[46]; // rv 1 + assign SAXISRQTDATA_in[47] = (SAXISRQTDATA[47] === 1'bz) || SAXISRQTDATA[47]; // rv 1 + assign SAXISRQTDATA_in[48] = (SAXISRQTDATA[48] === 1'bz) || SAXISRQTDATA[48]; // rv 1 + assign SAXISRQTDATA_in[49] = (SAXISRQTDATA[49] === 1'bz) || SAXISRQTDATA[49]; // rv 1 + assign SAXISRQTDATA_in[4] = (SAXISRQTDATA[4] === 1'bz) || SAXISRQTDATA[4]; // rv 1 + assign SAXISRQTDATA_in[50] = (SAXISRQTDATA[50] === 1'bz) || SAXISRQTDATA[50]; // rv 1 + assign SAXISRQTDATA_in[51] = (SAXISRQTDATA[51] === 1'bz) || SAXISRQTDATA[51]; // rv 1 + assign SAXISRQTDATA_in[52] = (SAXISRQTDATA[52] === 1'bz) || SAXISRQTDATA[52]; // rv 1 + assign SAXISRQTDATA_in[53] = (SAXISRQTDATA[53] === 1'bz) || SAXISRQTDATA[53]; // rv 1 + assign SAXISRQTDATA_in[54] = (SAXISRQTDATA[54] === 1'bz) || SAXISRQTDATA[54]; // rv 1 + assign SAXISRQTDATA_in[55] = (SAXISRQTDATA[55] === 1'bz) || SAXISRQTDATA[55]; // rv 1 + assign SAXISRQTDATA_in[56] = (SAXISRQTDATA[56] === 1'bz) || SAXISRQTDATA[56]; // rv 1 + assign SAXISRQTDATA_in[57] = (SAXISRQTDATA[57] === 1'bz) || SAXISRQTDATA[57]; // rv 1 + assign SAXISRQTDATA_in[58] = (SAXISRQTDATA[58] === 1'bz) || SAXISRQTDATA[58]; // rv 1 + assign SAXISRQTDATA_in[59] = (SAXISRQTDATA[59] === 1'bz) || SAXISRQTDATA[59]; // rv 1 + assign SAXISRQTDATA_in[5] = (SAXISRQTDATA[5] === 1'bz) || SAXISRQTDATA[5]; // rv 1 + assign SAXISRQTDATA_in[60] = (SAXISRQTDATA[60] === 1'bz) || SAXISRQTDATA[60]; // rv 1 + assign SAXISRQTDATA_in[61] = (SAXISRQTDATA[61] === 1'bz) || SAXISRQTDATA[61]; // rv 1 + assign SAXISRQTDATA_in[62] = (SAXISRQTDATA[62] === 1'bz) || SAXISRQTDATA[62]; // rv 1 + assign SAXISRQTDATA_in[63] = (SAXISRQTDATA[63] === 1'bz) || SAXISRQTDATA[63]; // rv 1 + assign SAXISRQTDATA_in[64] = (SAXISRQTDATA[64] === 1'bz) || SAXISRQTDATA[64]; // rv 1 + assign SAXISRQTDATA_in[65] = (SAXISRQTDATA[65] === 1'bz) || SAXISRQTDATA[65]; // rv 1 + assign SAXISRQTDATA_in[66] = (SAXISRQTDATA[66] === 1'bz) || SAXISRQTDATA[66]; // rv 1 + assign SAXISRQTDATA_in[67] = (SAXISRQTDATA[67] === 1'bz) || SAXISRQTDATA[67]; // rv 1 + assign SAXISRQTDATA_in[68] = (SAXISRQTDATA[68] === 1'bz) || SAXISRQTDATA[68]; // rv 1 + assign SAXISRQTDATA_in[69] = (SAXISRQTDATA[69] === 1'bz) || SAXISRQTDATA[69]; // rv 1 + assign SAXISRQTDATA_in[6] = (SAXISRQTDATA[6] === 1'bz) || SAXISRQTDATA[6]; // rv 1 + assign SAXISRQTDATA_in[70] = (SAXISRQTDATA[70] === 1'bz) || SAXISRQTDATA[70]; // rv 1 + assign SAXISRQTDATA_in[71] = (SAXISRQTDATA[71] === 1'bz) || SAXISRQTDATA[71]; // rv 1 + assign SAXISRQTDATA_in[72] = (SAXISRQTDATA[72] === 1'bz) || SAXISRQTDATA[72]; // rv 1 + assign SAXISRQTDATA_in[73] = (SAXISRQTDATA[73] === 1'bz) || SAXISRQTDATA[73]; // rv 1 + assign SAXISRQTDATA_in[74] = (SAXISRQTDATA[74] === 1'bz) || SAXISRQTDATA[74]; // rv 1 + assign SAXISRQTDATA_in[75] = (SAXISRQTDATA[75] === 1'bz) || SAXISRQTDATA[75]; // rv 1 + assign SAXISRQTDATA_in[76] = (SAXISRQTDATA[76] === 1'bz) || SAXISRQTDATA[76]; // rv 1 + assign SAXISRQTDATA_in[77] = (SAXISRQTDATA[77] === 1'bz) || SAXISRQTDATA[77]; // rv 1 + assign SAXISRQTDATA_in[78] = (SAXISRQTDATA[78] === 1'bz) || SAXISRQTDATA[78]; // rv 1 + assign SAXISRQTDATA_in[79] = (SAXISRQTDATA[79] === 1'bz) || SAXISRQTDATA[79]; // rv 1 + assign SAXISRQTDATA_in[7] = (SAXISRQTDATA[7] === 1'bz) || SAXISRQTDATA[7]; // rv 1 + assign SAXISRQTDATA_in[80] = (SAXISRQTDATA[80] === 1'bz) || SAXISRQTDATA[80]; // rv 1 + assign SAXISRQTDATA_in[81] = (SAXISRQTDATA[81] === 1'bz) || SAXISRQTDATA[81]; // rv 1 + assign SAXISRQTDATA_in[82] = (SAXISRQTDATA[82] === 1'bz) || SAXISRQTDATA[82]; // rv 1 + assign SAXISRQTDATA_in[83] = (SAXISRQTDATA[83] === 1'bz) || SAXISRQTDATA[83]; // rv 1 + assign SAXISRQTDATA_in[84] = (SAXISRQTDATA[84] === 1'bz) || SAXISRQTDATA[84]; // rv 1 + assign SAXISRQTDATA_in[85] = (SAXISRQTDATA[85] === 1'bz) || SAXISRQTDATA[85]; // rv 1 + assign SAXISRQTDATA_in[86] = (SAXISRQTDATA[86] === 1'bz) || SAXISRQTDATA[86]; // rv 1 + assign SAXISRQTDATA_in[87] = (SAXISRQTDATA[87] === 1'bz) || SAXISRQTDATA[87]; // rv 1 + assign SAXISRQTDATA_in[88] = (SAXISRQTDATA[88] === 1'bz) || SAXISRQTDATA[88]; // rv 1 + assign SAXISRQTDATA_in[89] = (SAXISRQTDATA[89] === 1'bz) || SAXISRQTDATA[89]; // rv 1 + assign SAXISRQTDATA_in[8] = (SAXISRQTDATA[8] === 1'bz) || SAXISRQTDATA[8]; // rv 1 + assign SAXISRQTDATA_in[90] = (SAXISRQTDATA[90] === 1'bz) || SAXISRQTDATA[90]; // rv 1 + assign SAXISRQTDATA_in[91] = (SAXISRQTDATA[91] === 1'bz) || SAXISRQTDATA[91]; // rv 1 + assign SAXISRQTDATA_in[92] = (SAXISRQTDATA[92] === 1'bz) || SAXISRQTDATA[92]; // rv 1 + assign SAXISRQTDATA_in[93] = (SAXISRQTDATA[93] === 1'bz) || SAXISRQTDATA[93]; // rv 1 + assign SAXISRQTDATA_in[94] = (SAXISRQTDATA[94] === 1'bz) || SAXISRQTDATA[94]; // rv 1 + assign SAXISRQTDATA_in[95] = (SAXISRQTDATA[95] === 1'bz) || SAXISRQTDATA[95]; // rv 1 + assign SAXISRQTDATA_in[96] = (SAXISRQTDATA[96] === 1'bz) || SAXISRQTDATA[96]; // rv 1 + assign SAXISRQTDATA_in[97] = (SAXISRQTDATA[97] === 1'bz) || SAXISRQTDATA[97]; // rv 1 + assign SAXISRQTDATA_in[98] = (SAXISRQTDATA[98] === 1'bz) || SAXISRQTDATA[98]; // rv 1 + assign SAXISRQTDATA_in[99] = (SAXISRQTDATA[99] === 1'bz) || SAXISRQTDATA[99]; // rv 1 + assign SAXISRQTDATA_in[9] = (SAXISRQTDATA[9] === 1'bz) || SAXISRQTDATA[9]; // rv 1 + assign SAXISRQTKEEP_in[0] = (SAXISRQTKEEP[0] !== 1'bz) && SAXISRQTKEEP[0]; // rv 0 + assign SAXISRQTKEEP_in[1] = (SAXISRQTKEEP[1] !== 1'bz) && SAXISRQTKEEP[1]; // rv 0 + assign SAXISRQTKEEP_in[2] = (SAXISRQTKEEP[2] !== 1'bz) && SAXISRQTKEEP[2]; // rv 0 + assign SAXISRQTKEEP_in[3] = (SAXISRQTKEEP[3] !== 1'bz) && SAXISRQTKEEP[3]; // rv 0 + assign SAXISRQTKEEP_in[4] = (SAXISRQTKEEP[4] !== 1'bz) && SAXISRQTKEEP[4]; // rv 0 + assign SAXISRQTKEEP_in[5] = (SAXISRQTKEEP[5] !== 1'bz) && SAXISRQTKEEP[5]; // rv 0 + assign SAXISRQTKEEP_in[6] = (SAXISRQTKEEP[6] !== 1'bz) && SAXISRQTKEEP[6]; // rv 0 + assign SAXISRQTKEEP_in[7] = (SAXISRQTKEEP[7] !== 1'bz) && SAXISRQTKEEP[7]; // rv 0 + assign SAXISRQTLAST_in = (SAXISRQTLAST === 1'bz) || SAXISRQTLAST; // rv 1 + assign SAXISRQTUSER_in[0] = (SAXISRQTUSER[0] === 1'bz) || SAXISRQTUSER[0]; // rv 1 + assign SAXISRQTUSER_in[10] = (SAXISRQTUSER[10] === 1'bz) || SAXISRQTUSER[10]; // rv 1 + assign SAXISRQTUSER_in[11] = (SAXISRQTUSER[11] === 1'bz) || SAXISRQTUSER[11]; // rv 1 + assign SAXISRQTUSER_in[12] = (SAXISRQTUSER[12] === 1'bz) || SAXISRQTUSER[12]; // rv 1 + assign SAXISRQTUSER_in[13] = (SAXISRQTUSER[13] === 1'bz) || SAXISRQTUSER[13]; // rv 1 + assign SAXISRQTUSER_in[14] = (SAXISRQTUSER[14] === 1'bz) || SAXISRQTUSER[14]; // rv 1 + assign SAXISRQTUSER_in[15] = (SAXISRQTUSER[15] === 1'bz) || SAXISRQTUSER[15]; // rv 1 + assign SAXISRQTUSER_in[16] = (SAXISRQTUSER[16] === 1'bz) || SAXISRQTUSER[16]; // rv 1 + assign SAXISRQTUSER_in[17] = (SAXISRQTUSER[17] === 1'bz) || SAXISRQTUSER[17]; // rv 1 + assign SAXISRQTUSER_in[18] = (SAXISRQTUSER[18] === 1'bz) || SAXISRQTUSER[18]; // rv 1 + assign SAXISRQTUSER_in[19] = (SAXISRQTUSER[19] === 1'bz) || SAXISRQTUSER[19]; // rv 1 + assign SAXISRQTUSER_in[1] = (SAXISRQTUSER[1] === 1'bz) || SAXISRQTUSER[1]; // rv 1 + assign SAXISRQTUSER_in[20] = (SAXISRQTUSER[20] === 1'bz) || SAXISRQTUSER[20]; // rv 1 + assign SAXISRQTUSER_in[21] = (SAXISRQTUSER[21] === 1'bz) || SAXISRQTUSER[21]; // rv 1 + assign SAXISRQTUSER_in[22] = (SAXISRQTUSER[22] === 1'bz) || SAXISRQTUSER[22]; // rv 1 + assign SAXISRQTUSER_in[23] = (SAXISRQTUSER[23] === 1'bz) || SAXISRQTUSER[23]; // rv 1 + assign SAXISRQTUSER_in[24] = (SAXISRQTUSER[24] === 1'bz) || SAXISRQTUSER[24]; // rv 1 + assign SAXISRQTUSER_in[25] = (SAXISRQTUSER[25] === 1'bz) || SAXISRQTUSER[25]; // rv 1 + assign SAXISRQTUSER_in[26] = (SAXISRQTUSER[26] === 1'bz) || SAXISRQTUSER[26]; // rv 1 + assign SAXISRQTUSER_in[27] = (SAXISRQTUSER[27] === 1'bz) || SAXISRQTUSER[27]; // rv 1 + assign SAXISRQTUSER_in[28] = (SAXISRQTUSER[28] === 1'bz) || SAXISRQTUSER[28]; // rv 1 + assign SAXISRQTUSER_in[29] = (SAXISRQTUSER[29] === 1'bz) || SAXISRQTUSER[29]; // rv 1 + assign SAXISRQTUSER_in[2] = (SAXISRQTUSER[2] === 1'bz) || SAXISRQTUSER[2]; // rv 1 + assign SAXISRQTUSER_in[30] = (SAXISRQTUSER[30] === 1'bz) || SAXISRQTUSER[30]; // rv 1 + assign SAXISRQTUSER_in[31] = (SAXISRQTUSER[31] === 1'bz) || SAXISRQTUSER[31]; // rv 1 + assign SAXISRQTUSER_in[32] = (SAXISRQTUSER[32] === 1'bz) || SAXISRQTUSER[32]; // rv 1 + assign SAXISRQTUSER_in[33] = (SAXISRQTUSER[33] === 1'bz) || SAXISRQTUSER[33]; // rv 1 + assign SAXISRQTUSER_in[34] = (SAXISRQTUSER[34] === 1'bz) || SAXISRQTUSER[34]; // rv 1 + assign SAXISRQTUSER_in[35] = (SAXISRQTUSER[35] === 1'bz) || SAXISRQTUSER[35]; // rv 1 + assign SAXISRQTUSER_in[36] = (SAXISRQTUSER[36] === 1'bz) || SAXISRQTUSER[36]; // rv 1 + assign SAXISRQTUSER_in[37] = (SAXISRQTUSER[37] === 1'bz) || SAXISRQTUSER[37]; // rv 1 + assign SAXISRQTUSER_in[38] = (SAXISRQTUSER[38] === 1'bz) || SAXISRQTUSER[38]; // rv 1 + assign SAXISRQTUSER_in[39] = (SAXISRQTUSER[39] === 1'bz) || SAXISRQTUSER[39]; // rv 1 + assign SAXISRQTUSER_in[3] = (SAXISRQTUSER[3] === 1'bz) || SAXISRQTUSER[3]; // rv 1 + assign SAXISRQTUSER_in[40] = (SAXISRQTUSER[40] === 1'bz) || SAXISRQTUSER[40]; // rv 1 + assign SAXISRQTUSER_in[41] = (SAXISRQTUSER[41] === 1'bz) || SAXISRQTUSER[41]; // rv 1 + assign SAXISRQTUSER_in[42] = (SAXISRQTUSER[42] === 1'bz) || SAXISRQTUSER[42]; // rv 1 + assign SAXISRQTUSER_in[43] = (SAXISRQTUSER[43] === 1'bz) || SAXISRQTUSER[43]; // rv 1 + assign SAXISRQTUSER_in[44] = (SAXISRQTUSER[44] === 1'bz) || SAXISRQTUSER[44]; // rv 1 + assign SAXISRQTUSER_in[45] = (SAXISRQTUSER[45] === 1'bz) || SAXISRQTUSER[45]; // rv 1 + assign SAXISRQTUSER_in[46] = (SAXISRQTUSER[46] === 1'bz) || SAXISRQTUSER[46]; // rv 1 + assign SAXISRQTUSER_in[47] = (SAXISRQTUSER[47] === 1'bz) || SAXISRQTUSER[47]; // rv 1 + assign SAXISRQTUSER_in[48] = (SAXISRQTUSER[48] === 1'bz) || SAXISRQTUSER[48]; // rv 1 + assign SAXISRQTUSER_in[49] = (SAXISRQTUSER[49] === 1'bz) || SAXISRQTUSER[49]; // rv 1 + assign SAXISRQTUSER_in[4] = (SAXISRQTUSER[4] === 1'bz) || SAXISRQTUSER[4]; // rv 1 + assign SAXISRQTUSER_in[50] = (SAXISRQTUSER[50] === 1'bz) || SAXISRQTUSER[50]; // rv 1 + assign SAXISRQTUSER_in[51] = (SAXISRQTUSER[51] === 1'bz) || SAXISRQTUSER[51]; // rv 1 + assign SAXISRQTUSER_in[52] = (SAXISRQTUSER[52] === 1'bz) || SAXISRQTUSER[52]; // rv 1 + assign SAXISRQTUSER_in[53] = (SAXISRQTUSER[53] === 1'bz) || SAXISRQTUSER[53]; // rv 1 + assign SAXISRQTUSER_in[54] = (SAXISRQTUSER[54] === 1'bz) || SAXISRQTUSER[54]; // rv 1 + assign SAXISRQTUSER_in[55] = (SAXISRQTUSER[55] === 1'bz) || SAXISRQTUSER[55]; // rv 1 + assign SAXISRQTUSER_in[56] = (SAXISRQTUSER[56] === 1'bz) || SAXISRQTUSER[56]; // rv 1 + assign SAXISRQTUSER_in[57] = (SAXISRQTUSER[57] === 1'bz) || SAXISRQTUSER[57]; // rv 1 + assign SAXISRQTUSER_in[58] = (SAXISRQTUSER[58] === 1'bz) || SAXISRQTUSER[58]; // rv 1 + assign SAXISRQTUSER_in[59] = (SAXISRQTUSER[59] === 1'bz) || SAXISRQTUSER[59]; // rv 1 + assign SAXISRQTUSER_in[5] = (SAXISRQTUSER[5] === 1'bz) || SAXISRQTUSER[5]; // rv 1 + assign SAXISRQTUSER_in[60] = (SAXISRQTUSER[60] === 1'bz) || SAXISRQTUSER[60]; // rv 1 + assign SAXISRQTUSER_in[61] = (SAXISRQTUSER[61] === 1'bz) || SAXISRQTUSER[61]; // rv 1 + assign SAXISRQTUSER_in[6] = (SAXISRQTUSER[6] === 1'bz) || SAXISRQTUSER[6]; // rv 1 + assign SAXISRQTUSER_in[7] = (SAXISRQTUSER[7] === 1'bz) || SAXISRQTUSER[7]; // rv 1 + assign SAXISRQTUSER_in[8] = (SAXISRQTUSER[8] === 1'bz) || SAXISRQTUSER[8]; // rv 1 + assign SAXISRQTUSER_in[9] = (SAXISRQTUSER[9] === 1'bz) || SAXISRQTUSER[9]; // rv 1 + assign SAXISRQTVALID_in = (SAXISRQTVALID !== 1'bz) && SAXISRQTVALID; // rv 0 + assign USERCLKEN_in = (USERCLKEN !== 1'bz) && USERCLKEN; // rv 0 + assign USERSPAREIN_in[0] = (USERSPAREIN[0] === 1'bz) || USERSPAREIN[0]; // rv 1 + assign USERSPAREIN_in[10] = (USERSPAREIN[10] === 1'bz) || USERSPAREIN[10]; // rv 1 + assign USERSPAREIN_in[11] = (USERSPAREIN[11] === 1'bz) || USERSPAREIN[11]; // rv 1 + assign USERSPAREIN_in[12] = (USERSPAREIN[12] === 1'bz) || USERSPAREIN[12]; // rv 1 + assign USERSPAREIN_in[13] = (USERSPAREIN[13] === 1'bz) || USERSPAREIN[13]; // rv 1 + assign USERSPAREIN_in[14] = (USERSPAREIN[14] === 1'bz) || USERSPAREIN[14]; // rv 1 + assign USERSPAREIN_in[15] = (USERSPAREIN[15] === 1'bz) || USERSPAREIN[15]; // rv 1 + assign USERSPAREIN_in[16] = (USERSPAREIN[16] === 1'bz) || USERSPAREIN[16]; // rv 1 + assign USERSPAREIN_in[17] = (USERSPAREIN[17] === 1'bz) || USERSPAREIN[17]; // rv 1 + assign USERSPAREIN_in[18] = (USERSPAREIN[18] === 1'bz) || USERSPAREIN[18]; // rv 1 + assign USERSPAREIN_in[19] = (USERSPAREIN[19] === 1'bz) || USERSPAREIN[19]; // rv 1 + assign USERSPAREIN_in[1] = (USERSPAREIN[1] === 1'bz) || USERSPAREIN[1]; // rv 1 + assign USERSPAREIN_in[20] = (USERSPAREIN[20] === 1'bz) || USERSPAREIN[20]; // rv 1 + assign USERSPAREIN_in[21] = (USERSPAREIN[21] === 1'bz) || USERSPAREIN[21]; // rv 1 + assign USERSPAREIN_in[22] = (USERSPAREIN[22] === 1'bz) || USERSPAREIN[22]; // rv 1 + assign USERSPAREIN_in[23] = (USERSPAREIN[23] === 1'bz) || USERSPAREIN[23]; // rv 1 + assign USERSPAREIN_in[24] = (USERSPAREIN[24] === 1'bz) || USERSPAREIN[24]; // rv 1 + assign USERSPAREIN_in[25] = (USERSPAREIN[25] === 1'bz) || USERSPAREIN[25]; // rv 1 + assign USERSPAREIN_in[26] = (USERSPAREIN[26] === 1'bz) || USERSPAREIN[26]; // rv 1 + assign USERSPAREIN_in[27] = (USERSPAREIN[27] === 1'bz) || USERSPAREIN[27]; // rv 1 + assign USERSPAREIN_in[28] = (USERSPAREIN[28] === 1'bz) || USERSPAREIN[28]; // rv 1 + assign USERSPAREIN_in[29] = (USERSPAREIN[29] === 1'bz) || USERSPAREIN[29]; // rv 1 + assign USERSPAREIN_in[2] = (USERSPAREIN[2] === 1'bz) || USERSPAREIN[2]; // rv 1 + assign USERSPAREIN_in[30] = (USERSPAREIN[30] === 1'bz) || USERSPAREIN[30]; // rv 1 + assign USERSPAREIN_in[31] = (USERSPAREIN[31] === 1'bz) || USERSPAREIN[31]; // rv 1 + assign USERSPAREIN_in[3] = (USERSPAREIN[3] === 1'bz) || USERSPAREIN[3]; // rv 1 + assign USERSPAREIN_in[4] = (USERSPAREIN[4] === 1'bz) || USERSPAREIN[4]; // rv 1 + assign USERSPAREIN_in[5] = (USERSPAREIN[5] === 1'bz) || USERSPAREIN[5]; // rv 1 + assign USERSPAREIN_in[6] = (USERSPAREIN[6] === 1'bz) || USERSPAREIN[6]; // rv 1 + assign USERSPAREIN_in[7] = (USERSPAREIN[7] === 1'bz) || USERSPAREIN[7]; // rv 1 + assign USERSPAREIN_in[8] = (USERSPAREIN[8] === 1'bz) || USERSPAREIN[8]; // rv 1 + assign USERSPAREIN_in[9] = (USERSPAREIN[9] === 1'bz) || USERSPAREIN[9]; // rv 1 +`endif + assign CORECLKMIREPLAYRAM0_in = (CORECLKMIREPLAYRAM0 !== 1'bz) && CORECLKMIREPLAYRAM0; // rv 0 + assign CORECLKMIREPLAYRAM1_in = (CORECLKMIREPLAYRAM1 !== 1'bz) && CORECLKMIREPLAYRAM1; // rv 0 + assign CORECLKMIRXCOMPLETIONRAM0_in = (CORECLKMIRXCOMPLETIONRAM0 !== 1'bz) && CORECLKMIRXCOMPLETIONRAM0; // rv 0 + assign CORECLKMIRXCOMPLETIONRAM1_in = (CORECLKMIRXCOMPLETIONRAM1 !== 1'bz) && CORECLKMIRXCOMPLETIONRAM1; // rv 0 + assign CORECLKMIRXPOSTEDREQUESTRAM0_in = (CORECLKMIRXPOSTEDREQUESTRAM0 !== 1'bz) && CORECLKMIRXPOSTEDREQUESTRAM0; // rv 0 + assign CORECLKMIRXPOSTEDREQUESTRAM1_in = (CORECLKMIRXPOSTEDREQUESTRAM1 !== 1'bz) && CORECLKMIRXPOSTEDREQUESTRAM1; // rv 0 + assign MCAPCLK_in = (MCAPCLK !== 1'bz) && MCAPCLK; // rv 0 + assign MCAPPERST0B_in = (MCAPPERST0B === 1'bz) || MCAPPERST0B; // rv 1 + assign MCAPPERST1B_in = (MCAPPERST1B === 1'bz) || MCAPPERST1B; // rv 1 + assign MGMTRESETN_in = (MGMTRESETN !== 1'bz) && MGMTRESETN; // rv 0 + assign MGMTSTICKYRESETN_in = (MGMTSTICKYRESETN !== 1'bz) && MGMTSTICKYRESETN; // rv 0 + assign PIPECLKEN_in = (PIPECLKEN !== 1'bz) && PIPECLKEN; // rv 0 + assign PIPERESETN_in = (PIPERESETN !== 1'bz) && PIPERESETN; // rv 0 + assign PLEQRESETEIEOSCOUNT_in = (PLEQRESETEIEOSCOUNT !== 1'bz) && PLEQRESETEIEOSCOUNT; // rv 0 + assign RESETN_in = (RESETN !== 1'bz) && RESETN; // rv 0 + assign USERCLK2_in = (USERCLK2 !== 1'bz) && USERCLK2; // rv 0 + assign USERCLK_in = (USERCLK !== 1'bz) && USERCLK; // rv 0 + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ARI_CAP_ENABLE_REG != "FALSE") && + (ARI_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] ARI_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ARI_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AUTO_FLR_RESPONSE_REG != "FALSE") && + (AUTO_FLR_RESPONSE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] AUTO_FLR_RESPONSE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AUTO_FLR_RESPONSE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG != "FALSE") && + (AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] AXISTEN_IF_CQ_EN_POISONED_MEM_WR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_256_TAGS_REG != "FALSE") && + (AXISTEN_IF_ENABLE_256_TAGS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] AXISTEN_IF_ENABLE_256_TAGS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_256_TAGS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "FALSE") && + (AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] AXISTEN_IF_ENABLE_CLIENT_TAG attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_CLIENT_TAG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG != "FALSE") && + (AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG != "TRUE") && + (AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-111] AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "FALSE") && + (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] AXISTEN_IF_ENABLE_RX_MSG_INTFC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_REG != "FALSE") && + (AXISTEN_IF_EXT_512_REG != "TRUE"))) begin + $display("Error: [Unisim %s-114] AXISTEN_IF_EXT_512 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_CC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_CC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-115] AXISTEN_IF_EXT_512_CC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_CC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_CQ_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_CQ_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] AXISTEN_IF_EXT_512_CQ_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_CQ_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_RC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_RC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-117] AXISTEN_IF_EXT_512_RC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_RC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_RQ_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_RQ_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] AXISTEN_IF_EXT_512_RQ_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_RQ_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_LEGACY_MODE_ENABLE_REG != "FALSE") && + (AXISTEN_IF_LEGACY_MODE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-119] AXISTEN_IF_LEGACY_MODE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_LEGACY_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG != "FALSE") && + (AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] AXISTEN_IF_MSIX_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_RX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_MSIX_RX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-121] AXISTEN_IF_MSIX_RX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_RX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG != "FALSE") && + (AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-122] AXISTEN_IF_MSIX_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_RC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_RC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-124] AXISTEN_IF_RC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_RC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_RX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_RX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-126] AXISTEN_IF_RX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_RX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG != "FALSE") && + (AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-127] AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_TX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_TX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-128] AXISTEN_IF_TX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_TX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CFG_BYPASS_MODE_ENABLE_REG != "FALSE") && + (CFG_BYPASS_MODE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] CFG_BYPASS_MODE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CFG_BYPASS_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CRM_CORE_CLK_FREQ_500_REG != "TRUE") && + (CRM_CORE_CLK_FREQ_500_REG != "FALSE"))) begin + $display("Error: [Unisim %s-131] CRM_CORE_CLK_FREQ_500 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CRM_CORE_CLK_FREQ_500_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-138] DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-139] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-140] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG != "FALSE") && + (DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-141] DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG != "FALSE") && + (DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG != "TRUE"))) begin + $display("Error: [Unisim %s-142] DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_SCRAMBLING_REG != "FALSE") && + (DEBUG_PL_DISABLE_SCRAMBLING_REG != "TRUE"))) begin + $display("Error: [Unisim %s-143] DEBUG_PL_DISABLE_SCRAMBLING attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_SCRAMBLING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_SIM_RESET_LFSR_REG != "FALSE") && + (DEBUG_PL_SIM_RESET_LFSR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-144] DEBUG_PL_SIM_RESET_LFSR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_SIM_RESET_LFSR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_TL_DISABLE_FC_TIMEOUT_REG != "FALSE") && + (DEBUG_TL_DISABLE_FC_TIMEOUT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-146] DEBUG_TL_DISABLE_FC_TIMEOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_TL_DISABLE_FC_TIMEOUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "FALSE") && + (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-147] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DSN_CAP_ENABLE_REG != "FALSE") && + (DSN_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-150] DSN_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DSN_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-151] EXTENDED_CFG_EXTEND_INTERFACE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((HEADER_TYPE_OVERRIDE_REG != "FALSE") && + (HEADER_TYPE_OVERRIDE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-152] HEADER_TYPE_OVERRIDE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, HEADER_TYPE_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_SWITCH_PORT_REG != "FALSE") && + (IS_SWITCH_PORT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-153] IS_SWITCH_PORT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IS_SWITCH_PORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-154] LEGACY_CFG_EXTEND_INTERFACE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_ACK_TIMEOUT_EN_REG != "FALSE") && + (LL_ACK_TIMEOUT_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-156] LL_ACK_TIMEOUT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_ACK_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_ACK_TIMEOUT_FUNC_REG != 0) && + (LL_ACK_TIMEOUT_FUNC_REG != 1) && + (LL_ACK_TIMEOUT_FUNC_REG != 2) && + (LL_ACK_TIMEOUT_FUNC_REG != 3))) begin + $display("Error: [Unisim %s-157] LL_ACK_TIMEOUT_FUNC attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, LL_ACK_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_DISABLE_SCHED_TX_NAK_REG != "FALSE") && + (LL_DISABLE_SCHED_TX_NAK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-158] LL_DISABLE_SCHED_TX_NAK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_DISABLE_SCHED_TX_NAK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_FROM_RAM_PIPELINE_REG != "FALSE") && + (LL_REPLAY_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-159] LL_REPLAY_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TIMEOUT_EN_REG != "FALSE") && + (LL_REPLAY_TIMEOUT_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-161] LL_REPLAY_TIMEOUT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TIMEOUT_FUNC_REG != 0) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 1) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 2) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 3))) begin + $display("Error: [Unisim %s-162] LL_REPLAY_TIMEOUT_FUNC attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, LL_REPLAY_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TO_RAM_PIPELINE_REG != "FALSE") && + (LL_REPLAY_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-163] LL_REPLAY_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_RX_TLP_PARITY_GEN_REG != "TRUE") && + (LL_RX_TLP_PARITY_GEN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-164] LL_RX_TLP_PARITY_GEN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LL_RX_TLP_PARITY_GEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_TX_TLP_PARITY_CHK_REG != "TRUE") && + (LL_TX_TLP_PARITY_CHK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-165] LL_TX_TLP_PARITY_CHK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LL_TX_TLP_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-168] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-169] LTR_TX_MESSAGE_ON_LTR_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LTR_TX_MESSAGE_ON_LTR_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_CONFIGURE_OVERRIDE_REG != "FALSE") && + (MCAP_CONFIGURE_OVERRIDE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-171] MCAP_CONFIGURE_OVERRIDE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_CONFIGURE_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_ENABLE_REG != "FALSE") && + (MCAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-172] MCAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_EOS_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_EOS_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-173] MCAP_EOS_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_EOS_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-175] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-176] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-177] MCAP_INPUT_GATE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INPUT_GATE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INTERRUPT_ON_MCAP_EOS_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_EOS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-178] MCAP_INTERRUPT_ON_MCAP_EOS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_EOS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-179] MCAP_INTERRUPT_ON_MCAP_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG != "FALSE") && + (PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-183] PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-202] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-203] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-204] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "FALSE") && + (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-205] PF0_DEV_CAP2_ARI_FORWARD_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "TRUE") && + (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-206] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_LTR_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_LTR_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-207] PF0_DEV_CAP2_LTR_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_LTR_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "FALSE") && + (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-209] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 7))) begin + $display("Error: [Unisim %s-210] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 7))) begin + $display("Error: [Unisim %s-211] PF0_DEV_CAP_ENDPOINT_L1_LATENCY attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "TRUE") && + (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "FALSE"))) begin + $display("Error: [Unisim %s-212] PF0_DEV_CAP_EXT_TAG_SUPPORTED attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "TRUE") && + (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-213] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF0_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-217] PF0_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_ASPM_SUPPORT_REG != 0) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 1) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 2) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 3))) begin + $display("Error: [Unisim %s-219] PF0_LINK_CAP_ASPM_SUPPORT attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PF0_LINK_CAP_ASPM_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-220] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-221] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-222] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-223] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-224] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-225] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-226] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-227] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-228] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-229] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-230] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-231] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-232] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-233] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-234] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-235] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "TRUE") && + (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "FALSE"))) begin + $display("Error: [Unisim %s-237] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSIX_CAP_PBA_BIR_REG != 0) && + (PF0_MSIX_CAP_PBA_BIR_REG != 1) && + (PF0_MSIX_CAP_PBA_BIR_REG != 2) && + (PF0_MSIX_CAP_PBA_BIR_REG != 3) && + (PF0_MSIX_CAP_PBA_BIR_REG != 4) && + (PF0_MSIX_CAP_PBA_BIR_REG != 5) && + (PF0_MSIX_CAP_PBA_BIR_REG != 6) && + (PF0_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-243] PF0_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-245] PF0_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-249] PF0_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF0_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-251] PF0_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D0_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D0_REG != "FALSE"))) begin + $display("Error: [Unisim %s-255] PF0_PM_CAP_PMESUPPORT_D0 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D1_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D1_REG != "FALSE"))) begin + $display("Error: [Unisim %s-256] PF0_PM_CAP_PMESUPPORT_D1 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-257] PF0_PM_CAP_PMESUPPORT_D3HOT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D3HOT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_SUPP_D1_STATE_REG != "TRUE") && + (PF0_PM_CAP_SUPP_D1_STATE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-258] PF0_PM_CAP_SUPP_D1_STATE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_SUPP_D1_STATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CSR_NOSOFTRESET_REG != "TRUE") && + (PF0_PM_CSR_NOSOFTRESET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-260] PF0_PM_CSR_NOSOFTRESET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CSR_NOSOFTRESET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-262] PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-283] PF0_TPHR_CAP_DEV_SPECIFIC_MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF0_TPHR_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-284] PF0_TPHR_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-285] PF0_TPHR_CAP_INT_VEC_MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_VC_CAP_ENABLE_REG != "FALSE") && + (PF0_VC_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-291] PF0_VC_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_VC_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF1_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-314] PF1_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSIX_CAP_PBA_BIR_REG != 0) && + (PF1_MSIX_CAP_PBA_BIR_REG != 1) && + (PF1_MSIX_CAP_PBA_BIR_REG != 2) && + (PF1_MSIX_CAP_PBA_BIR_REG != 3) && + (PF1_MSIX_CAP_PBA_BIR_REG != 4) && + (PF1_MSIX_CAP_PBA_BIR_REG != 5) && + (PF1_MSIX_CAP_PBA_BIR_REG != 6) && + (PF1_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-317] PF1_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-319] PF1_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-322] PF1_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF1_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-324] PF1_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-327] PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF2_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-370] PF2_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSIX_CAP_PBA_BIR_REG != 0) && + (PF2_MSIX_CAP_PBA_BIR_REG != 1) && + (PF2_MSIX_CAP_PBA_BIR_REG != 2) && + (PF2_MSIX_CAP_PBA_BIR_REG != 3) && + (PF2_MSIX_CAP_PBA_BIR_REG != 4) && + (PF2_MSIX_CAP_PBA_BIR_REG != 5) && + (PF2_MSIX_CAP_PBA_BIR_REG != 6) && + (PF2_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-373] PF2_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-375] PF2_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-378] PF2_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF2_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-380] PF2_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-383] PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF3_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-426] PF3_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSIX_CAP_PBA_BIR_REG != 0) && + (PF3_MSIX_CAP_PBA_BIR_REG != 1) && + (PF3_MSIX_CAP_PBA_BIR_REG != 2) && + (PF3_MSIX_CAP_PBA_BIR_REG != 3) && + (PF3_MSIX_CAP_PBA_BIR_REG != 4) && + (PF3_MSIX_CAP_PBA_BIR_REG != 5) && + (PF3_MSIX_CAP_PBA_BIR_REG != 6) && + (PF3_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-429] PF3_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-431] PF3_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-434] PF3_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF3_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-436] PF3_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-439] PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_CFG_STATE_ROBUSTNESS_ENABLE_REG != "TRUE") && + (PL_CFG_STATE_ROBUSTNESS_ENABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-462] PL_CFG_STATE_ROBUSTNESS_ENABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_CFG_STATE_ROBUSTNESS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DEEMPH_SOURCE_SELECT_REG != "TRUE") && + (PL_DEEMPH_SOURCE_SELECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-463] PL_DEEMPH_SOURCE_SELECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_DEEMPH_SOURCE_SELECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DESKEW_ON_SKIP_IN_GEN12_REG != "FALSE") && + (PL_DESKEW_ON_SKIP_IN_GEN12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-464] PL_DESKEW_ON_SKIP_IN_GEN12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DESKEW_ON_SKIP_IN_GEN12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "FALSE") && + (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "TRUE"))) begin + $display("Error: [Unisim %s-465] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG != "FALSE") && + (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG != "TRUE"))) begin + $display("Error: [Unisim %s-466] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "FALSE") && + (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "TRUE"))) begin + $display("Error: [Unisim %s-467] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_DC_BALANCE_REG != "FALSE") && + (PL_DISABLE_DC_BALANCE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-468] PL_DISABLE_DC_BALANCE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_DC_BALANCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") && + (PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-469] PL_DISABLE_EI_INFER_IN_L0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_EI_INFER_IN_L0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_LANE_REVERSAL_REG != "FALSE") && + (PL_DISABLE_LANE_REVERSAL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-470] PL_DISABLE_LANE_REVERSAL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_LANE_REVERSAL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_RETRAIN_ON_EB_ERROR_REG != "FALSE") && + (PL_DISABLE_RETRAIN_ON_EB_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-472] PL_DISABLE_RETRAIN_ON_EB_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_RETRAIN_ON_EB_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "FALSE") && + (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-473] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_UPCONFIG_CAPABLE_REG != "FALSE") && + (PL_DISABLE_UPCONFIG_CAPABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-475] PL_DISABLE_UPCONFIG_CAPABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_UPCONFIG_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_DISABLE_MISMATCH_CHECK_REG != "TRUE") && + (PL_EQ_DISABLE_MISMATCH_CHECK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-483] PL_EQ_DISABLE_MISMATCH_CHECK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_EQ_DISABLE_MISMATCH_CHECK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_SHORT_ADAPT_PHASE_REG != "FALSE") && + (PL_EQ_SHORT_ADAPT_PHASE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-486] PL_EQ_SHORT_ADAPT_PHASE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_EQ_SHORT_ADAPT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_TX_8G_EQ_TS2_ENABLE_REG != "FALSE") && + (PL_EQ_TX_8G_EQ_TS2_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-487] PL_EQ_TX_8G_EQ_TS2_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_EQ_TX_8G_EQ_TS2_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG != "TRUE") && + (PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-488] PL_EXIT_LOOPBACK_ON_EI_ENTRY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG != "TRUE") && + (PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-489] PL_INFER_EI_DISABLE_LPBK_ACTIVE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_REC_RC_REG != "FALSE") && + (PL_INFER_EI_DISABLE_REC_RC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-490] PL_INFER_EI_DISABLE_REC_RC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_REC_RC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_REC_SPD_REG != "FALSE") && + (PL_INFER_EI_DISABLE_REC_SPD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-491] PL_INFER_EI_DISABLE_REC_SPD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_REC_SPD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_N_FTS_REG < 0) || (PL_N_FTS_REG > 255))) begin + $display("Error: [Unisim %s-510] PL_N_FTS attribute is set to %d. Legal values for this attribute are 0 to 255. Instance: %m", MODULE_NAME, PL_N_FTS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_QUIESCE_GUARANTEE_DISABLE_REG != "FALSE") && + (PL_QUIESCE_GUARANTEE_DISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-511] PL_QUIESCE_GUARANTEE_DISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_QUIESCE_GUARANTEE_DISABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_REDO_EQ_SOURCE_SELECT_REG != "TRUE") && + (PL_REDO_EQ_SOURCE_SELECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-512] PL_REDO_EQ_SOURCE_SELECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_REDO_EQ_SOURCE_SELECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_SRIS_ENABLE_REG != "FALSE") && + (PL_SRIS_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-522] PL_SRIS_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_SRIS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_UPSTREAM_FACING_REG != "TRUE") && + (PL_UPSTREAM_FACING_REG != "FALSE"))) begin + $display("Error: [Unisim %s-525] PL_UPSTREAM_FACING attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_UPSTREAM_FACING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PM_ENABLE_L23_ENTRY_REG != "FALSE") && + (PM_ENABLE_L23_ENTRY_REG != "TRUE"))) begin + $display("Error: [Unisim %s-529] PM_ENABLE_L23_ENTRY attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PM_ENABLE_L23_ENTRY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PM_ENABLE_SLOT_POWER_CAPTURE_REG != "TRUE") && + (PM_ENABLE_SLOT_POWER_CAPTURE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-530] PM_ENABLE_SLOT_POWER_CAPTURE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PM_ENABLE_SLOT_POWER_CAPTURE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-534] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != "1.0") && + (SIM_VERSION_REG != "1.1") && + (SIM_VERSION_REG != "1.2") && + (SIM_VERSION_REG != "1.3") && + (SIM_VERSION_REG != "2.0") && + (SIM_VERSION_REG != "3.0") && + (SIM_VERSION_REG != "4.0"))) begin + $display("Error: [Unisim %s-536] SIM_VERSION attribute is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0 or 4.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT0_REG != "FALSE") && + (SPARE_BIT0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-537] SPARE_BIT0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SPARE_BIT0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT1_REG != 0) && + (SPARE_BIT1_REG != 1))) begin + $display("Error: [Unisim %s-538] SPARE_BIT1 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT2_REG != 0) && + (SPARE_BIT2_REG != 1))) begin + $display("Error: [Unisim %s-539] SPARE_BIT2 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT3_REG != "FALSE") && + (SPARE_BIT3_REG != "TRUE"))) begin + $display("Error: [Unisim %s-540] SPARE_BIT3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SPARE_BIT3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT4_REG != 0) && + (SPARE_BIT4_REG != 1))) begin + $display("Error: [Unisim %s-541] SPARE_BIT4 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT5_REG != 0) && + (SPARE_BIT5_REG != 1))) begin + $display("Error: [Unisim %s-542] SPARE_BIT5 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT5_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT6_REG != 0) && + (SPARE_BIT6_REG != 1))) begin + $display("Error: [Unisim %s-543] SPARE_BIT6 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT6_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT7_REG != 0) && + (SPARE_BIT7_REG != 1))) begin + $display("Error: [Unisim %s-544] SPARE_BIT7 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT7_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT8_REG != 0) && + (SPARE_BIT8_REG != 1))) begin + $display("Error: [Unisim %s-545] SPARE_BIT8 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT8_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL2CFG_IF_PARITY_CHK_REG != "TRUE") && + (TL2CFG_IF_PARITY_CHK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-556] TL2CFG_IF_PARITY_CHK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TL2CFG_IF_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-569] TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-570] TL_RX_COMPLETION_TO_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-571] TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-572] TL_RX_POSTED_FROM_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-573] TL_RX_POSTED_TO_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-574] TL_RX_POSTED_TO_RAM_WRITE_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_MUX_STRICT_PRIORITY_REG != "TRUE") && + (TL_TX_MUX_STRICT_PRIORITY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-575] TL_TX_MUX_STRICT_PRIORITY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TL_TX_MUX_STRICT_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_TLP_STRADDLE_ENABLE_REG != "FALSE") && + (TL_TX_TLP_STRADDLE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-576] TL_TX_TLP_STRADDLE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_TX_TLP_STRADDLE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_TLP_TERMINATE_PARITY_REG != "FALSE") && + (TL_TX_TLP_TERMINATE_PARITY_REG != "TRUE"))) begin + $display("Error: [Unisim %s-577] TL_TX_TLP_TERMINATE_PARITY attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_TX_TLP_TERMINATE_PARITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TPH_FROM_RAM_PIPELINE_REG != "FALSE") && + (TPH_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-579] TPH_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TPH_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TPH_TO_RAM_PIPELINE_REG != "FALSE") && + (TPH_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-580] TPH_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TPH_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG0_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-584] VFG0_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG0_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-586] VFG0_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG1_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-594] VFG1_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG1_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-596] VFG1_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG2_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-604] VFG2_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG2_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-606] VFG2_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG3_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-614] VFG3_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG3_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-616] VFG3_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign PMVDIVIDE_in = 2'b11; // tie off + assign PMVENABLEN_in = 1'b1; // tie off + assign PMVSELECT_in = 3'b111; // tie off + assign SCANENABLEN_in = 1'b1; // tie off + assign SCANIN_in = 173'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign SCANMODEN_in = 1'b1; // tie off + + SIP_PCIE40E4 #( + .MCAP_ENABLE_PAR (MCAP_ENABLE), + .SIM_JTAG_IDCODE (SIM_JTAG_IDCODE) +) SIP_PCIE40E4_INST ( + .ARI_CAP_ENABLE (ARI_CAP_ENABLE_REG), + .AUTO_FLR_RESPONSE (AUTO_FLR_RESPONSE_REG), + .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_COMPL_TIMEOUT_REG0 (AXISTEN_IF_COMPL_TIMEOUT_REG0_REG), + .AXISTEN_IF_COMPL_TIMEOUT_REG1 (AXISTEN_IF_COMPL_TIMEOUT_REG1_REG), + .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_CQ_EN_POISONED_MEM_WR (AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG), + .AXISTEN_IF_ENABLE_256_TAGS (AXISTEN_IF_ENABLE_256_TAGS_REG), + .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG_REG), + .AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE (AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG), + .AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK (AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG), + .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE_REG), + .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG), + .AXISTEN_IF_EXT_512 (AXISTEN_IF_EXT_512_REG), + .AXISTEN_IF_EXT_512_CC_STRADDLE (AXISTEN_IF_EXT_512_CC_STRADDLE_REG), + .AXISTEN_IF_EXT_512_CQ_STRADDLE (AXISTEN_IF_EXT_512_CQ_STRADDLE_REG), + .AXISTEN_IF_EXT_512_RC_STRADDLE (AXISTEN_IF_EXT_512_RC_STRADDLE_REG), + .AXISTEN_IF_EXT_512_RQ_STRADDLE (AXISTEN_IF_EXT_512_RQ_STRADDLE_REG), + .AXISTEN_IF_LEGACY_MODE_ENABLE (AXISTEN_IF_LEGACY_MODE_ENABLE_REG), + .AXISTEN_IF_MSIX_FROM_RAM_PIPELINE (AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG), + .AXISTEN_IF_MSIX_RX_PARITY_EN (AXISTEN_IF_MSIX_RX_PARITY_EN_REG), + .AXISTEN_IF_MSIX_TO_RAM_PIPELINE (AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG), + .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE_REG), + .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RX_PARITY_EN (AXISTEN_IF_RX_PARITY_EN_REG), + .AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT (AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG), + .AXISTEN_IF_TX_PARITY_EN (AXISTEN_IF_TX_PARITY_EN_REG), + .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH_REG), + .CFG_BYPASS_MODE_ENABLE (CFG_BYPASS_MODE_ENABLE_REG), + .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500_REG), + .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ_REG), + .DEBUG_AXI4ST_SPARE (DEBUG_AXI4ST_SPARE_REG), + .DEBUG_AXIST_DISABLE_FEATURE_BIT (DEBUG_AXIST_DISABLE_FEATURE_BIT_REG), + .DEBUG_CAR_SPARE (DEBUG_CAR_SPARE_REG), + .DEBUG_CFG_SPARE (DEBUG_CFG_SPARE_REG), + .DEBUG_LL_SPARE (DEBUG_LL_SPARE_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG), + .DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL (DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG), + .DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW (DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG), + .DEBUG_PL_DISABLE_SCRAMBLING (DEBUG_PL_DISABLE_SCRAMBLING_REG), + .DEBUG_PL_SIM_RESET_LFSR (DEBUG_PL_SIM_RESET_LFSR_REG), + .DEBUG_PL_SPARE (DEBUG_PL_SPARE_REG), + .DEBUG_TL_DISABLE_FC_TIMEOUT (DEBUG_TL_DISABLE_FC_TIMEOUT_REG), + .DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG), + .DEBUG_TL_SPARE (DEBUG_TL_SPARE_REG), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM_REG), + .DSN_CAP_ENABLE (DSN_CAP_ENABLE_REG), + .EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG), + .HEADER_TYPE_OVERRIDE (HEADER_TYPE_OVERRIDE_REG), + .IS_SWITCH_PORT (IS_SWITCH_PORT_REG), + .LEGACY_CFG_EXTEND_INTERFACE_ENABLE (LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT_REG), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN_REG), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC_REG), + .LL_DISABLE_SCHED_TX_NAK (LL_DISABLE_SCHED_TX_NAK_REG), + .LL_REPLAY_FROM_RAM_PIPELINE (LL_REPLAY_FROM_RAM_PIPELINE_REG), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT_REG), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN_REG), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC_REG), + .LL_REPLAY_TO_RAM_PIPELINE (LL_REPLAY_TO_RAM_PIPELINE_REG), + .LL_RX_TLP_PARITY_GEN (LL_RX_TLP_PARITY_GEN_REG), + .LL_TX_TLP_PARITY_CHK (LL_TX_TLP_PARITY_CHK_REG), + .LL_USER_SPARE (LL_USER_SPARE_REG), + .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG), + .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG), + .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG), + .MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR_REG), + .MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE_REG), + .MCAP_ENABLE (MCAP_ENABLE_REG), + .MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH_REG), + .MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION_REG), + .MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG), + .MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG), + .MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH_REG), + .MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS_REG), + .MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR_REG), + .MCAP_VSEC_ID (MCAP_VSEC_ID_REG), + .MCAP_VSEC_LEN (MCAP_VSEC_LEN_REG), + .MCAP_VSEC_REV (MCAP_VSEC_REV_REG), + .PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE (PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG), + .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC_REG), + .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER_REG), + .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE_REG), + .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL_REG), + .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE_REG), + .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL_REG), + .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE_REG), + .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL_REG), + .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE_REG), + .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL_REG), + .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE_REG), + .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL_REG), + .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE_REG), + .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL_REG), + .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER_REG), + .PF0_CLASS_CODE (PF0_CLASS_CODE_REG), + .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG), + .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG), + .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT_REG), + .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT_REG), + .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG), + .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG), + .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG), + .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG), + .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR_REG), + .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE_REG), + .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN_REG), + .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG), + .PF0_LINK_CONTROL_RCB (PF0_LINK_CONTROL_RCB_REG), + .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG), + .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG), + .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT_REG), + .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR_REG), + .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER_REG), + .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR_REG), + .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR_REG), + .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR_REG), + .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE_REG), + .PF0_MSIX_VECTOR_COUNT (PF0_MSIX_VECTOR_COUNT_REG), + .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP_REG), + .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR_REG), + .PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP_REG), + .PF0_PCIE_CAP_NEXTPTR (PF0_PCIE_CAP_NEXTPTR_REG), + .PF0_PM_CAP_ID (PF0_PM_CAP_ID_REG), + .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR_REG), + .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0_REG), + .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1_REG), + .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT_REG), + .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE_REG), + .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID_REG), + .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET_REG), + .PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG), + .PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL_REG), + .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL_REG), + .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL_REG), + .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL_REG), + .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL_REG), + .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL_REG), + .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF_REG), + .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR_REG), + .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF_REG), + .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER_REG), + .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET_REG), + .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK_REG), + .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID_REG), + .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE_REG), + .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE_REG), + .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR_REG), + .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL_REG), + .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC_REG), + .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER_REG), + .PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE_REG), + .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR_REG), + .PF0_VC_CAP_VER (PF0_VC_CAP_VER_REG), + .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC_REG), + .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE_REG), + .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL_REG), + .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE_REG), + .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL_REG), + .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE_REG), + .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL_REG), + .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE_REG), + .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL_REG), + .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE_REG), + .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL_REG), + .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE_REG), + .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL_REG), + .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER_REG), + .PF1_CLASS_CODE (PF1_CLASS_CODE_REG), + .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR_REG), + .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE_REG), + .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN_REG), + .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR_REG), + .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR_REG), + .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR_REG), + .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE_REG), + .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP_REG), + .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR_REG), + .PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP_REG), + .PF1_PCIE_CAP_NEXTPTR (PF1_PCIE_CAP_NEXTPTR_REG), + .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR_REG), + .PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL_REG), + .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL_REG), + .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL_REG), + .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL_REG), + .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL_REG), + .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL_REG), + .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF_REG), + .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR_REG), + .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF_REG), + .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER_REG), + .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET_REG), + .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK_REG), + .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID_REG), + .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR_REG), + .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL_REG), + .PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC_REG), + .PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE_REG), + .PF2_BAR0_CONTROL (PF2_BAR0_CONTROL_REG), + .PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE_REG), + .PF2_BAR1_CONTROL (PF2_BAR1_CONTROL_REG), + .PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE_REG), + .PF2_BAR2_CONTROL (PF2_BAR2_CONTROL_REG), + .PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE_REG), + .PF2_BAR3_CONTROL (PF2_BAR3_CONTROL_REG), + .PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE_REG), + .PF2_BAR4_CONTROL (PF2_BAR4_CONTROL_REG), + .PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE_REG), + .PF2_BAR5_CONTROL (PF2_BAR5_CONTROL_REG), + .PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER_REG), + .PF2_CLASS_CODE (PF2_CLASS_CODE_REG), + .PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR_REG), + .PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE_REG), + .PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN_REG), + .PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR_REG), + .PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR_REG), + .PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR_REG), + .PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE_REG), + .PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP_REG), + .PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR_REG), + .PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP_REG), + .PF2_PCIE_CAP_NEXTPTR (PF2_PCIE_CAP_NEXTPTR_REG), + .PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR_REG), + .PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL_REG), + .PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL_REG), + .PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL_REG), + .PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL_REG), + .PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL_REG), + .PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL_REG), + .PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF_REG), + .PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR_REG), + .PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF_REG), + .PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER_REG), + .PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET_REG), + .PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK_REG), + .PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID_REG), + .PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR_REG), + .PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL_REG), + .PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC_REG), + .PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE_REG), + .PF3_BAR0_CONTROL (PF3_BAR0_CONTROL_REG), + .PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE_REG), + .PF3_BAR1_CONTROL (PF3_BAR1_CONTROL_REG), + .PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE_REG), + .PF3_BAR2_CONTROL (PF3_BAR2_CONTROL_REG), + .PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE_REG), + .PF3_BAR3_CONTROL (PF3_BAR3_CONTROL_REG), + .PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE_REG), + .PF3_BAR4_CONTROL (PF3_BAR4_CONTROL_REG), + .PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE_REG), + .PF3_BAR5_CONTROL (PF3_BAR5_CONTROL_REG), + .PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER_REG), + .PF3_CLASS_CODE (PF3_CLASS_CODE_REG), + .PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR_REG), + .PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE_REG), + .PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN_REG), + .PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR_REG), + .PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR_REG), + .PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR_REG), + .PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE_REG), + .PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP_REG), + .PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR_REG), + .PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP_REG), + .PF3_PCIE_CAP_NEXTPTR (PF3_PCIE_CAP_NEXTPTR_REG), + .PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR_REG), + .PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL_REG), + .PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL_REG), + .PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL_REG), + .PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL_REG), + .PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL_REG), + .PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL_REG), + .PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF_REG), + .PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR_REG), + .PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF_REG), + .PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER_REG), + .PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET_REG), + .PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK_REG), + .PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID_REG), + .PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR_REG), + .PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL_REG), + .PL_CFG_STATE_ROBUSTNESS_ENABLE (PL_CFG_STATE_ROBUSTNESS_ENABLE_REG), + .PL_DEEMPH_SOURCE_SELECT (PL_DEEMPH_SOURCE_SELECT_REG), + .PL_DESKEW_ON_SKIP_IN_GEN12 (PL_DESKEW_ON_SKIP_IN_GEN12_REG), + .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG), + .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG), + .PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG), + .PL_DISABLE_DC_BALANCE (PL_DISABLE_DC_BALANCE_REG), + .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0_REG), + .PL_DISABLE_LANE_REVERSAL (PL_DISABLE_LANE_REVERSAL_REG), + .PL_DISABLE_LFSR_UPDATE_ON_SKP (PL_DISABLE_LFSR_UPDATE_ON_SKP_REG), + .PL_DISABLE_RETRAIN_ON_EB_ERROR (PL_DISABLE_RETRAIN_ON_EB_ERROR_REG), + .PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG), + .PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR_REG), + .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE_REG), + .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG), + .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG), + .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT_REG), + .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG), + .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23_REG), + .PL_EQ_DEFAULT_RX_PRESET_HINT (PL_EQ_DEFAULT_RX_PRESET_HINT_REG), + .PL_EQ_DEFAULT_TX_PRESET (PL_EQ_DEFAULT_TX_PRESET_REG), + .PL_EQ_DISABLE_MISMATCH_CHECK (PL_EQ_DISABLE_MISMATCH_CHECK_REG), + .PL_EQ_RX_ADAPT_EQ_PHASE0 (PL_EQ_RX_ADAPT_EQ_PHASE0_REG), + .PL_EQ_RX_ADAPT_EQ_PHASE1 (PL_EQ_RX_ADAPT_EQ_PHASE1_REG), + .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE_REG), + .PL_EQ_TX_8G_EQ_TS2_ENABLE (PL_EQ_TX_8G_EQ_TS2_ENABLE_REG), + .PL_EXIT_LOOPBACK_ON_EI_ENTRY (PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG), + .PL_INFER_EI_DISABLE_LPBK_ACTIVE (PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG), + .PL_INFER_EI_DISABLE_REC_RC (PL_INFER_EI_DISABLE_REC_RC_REG), + .PL_INFER_EI_DISABLE_REC_SPD (PL_INFER_EI_DISABLE_REC_SPD_REG), + .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL_REG), + .PL_LANE10_EQ_CONTROL (PL_LANE10_EQ_CONTROL_REG), + .PL_LANE11_EQ_CONTROL (PL_LANE11_EQ_CONTROL_REG), + .PL_LANE12_EQ_CONTROL (PL_LANE12_EQ_CONTROL_REG), + .PL_LANE13_EQ_CONTROL (PL_LANE13_EQ_CONTROL_REG), + .PL_LANE14_EQ_CONTROL (PL_LANE14_EQ_CONTROL_REG), + .PL_LANE15_EQ_CONTROL (PL_LANE15_EQ_CONTROL_REG), + .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL_REG), + .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL_REG), + .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL_REG), + .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL_REG), + .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL_REG), + .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL_REG), + .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL_REG), + .PL_LANE8_EQ_CONTROL (PL_LANE8_EQ_CONTROL_REG), + .PL_LANE9_EQ_CONTROL (PL_LANE9_EQ_CONTROL_REG), + .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED_REG), + .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH_REG), + .PL_N_FTS (PL_N_FTS_REG), + .PL_QUIESCE_GUARANTEE_DISABLE (PL_QUIESCE_GUARANTEE_DISABLE_REG), + .PL_REDO_EQ_SOURCE_SELECT (PL_REDO_EQ_SOURCE_SELECT_REG), + .PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS_REG), + .PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS (PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS_REG), + .PL_RX_ADAPT_TIMER_CLWS_GEN3 (PL_RX_ADAPT_TIMER_CLWS_GEN3_REG), + .PL_RX_ADAPT_TIMER_CLWS_GEN4 (PL_RX_ADAPT_TIMER_CLWS_GEN4_REG), + .PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS (PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS_REG), + .PL_RX_ADAPT_TIMER_RRL_GEN3 (PL_RX_ADAPT_TIMER_RRL_GEN3_REG), + .PL_RX_ADAPT_TIMER_RRL_GEN4 (PL_RX_ADAPT_TIMER_RRL_GEN4_REG), + .PL_RX_L0S_EXIT_TO_RECOVERY (PL_RX_L0S_EXIT_TO_RECOVERY_REG), + .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING_REG), + .PL_SRIS_ENABLE (PL_SRIS_ENABLE_REG), + .PL_SRIS_SKPOS_GEN_SPD_VEC (PL_SRIS_SKPOS_GEN_SPD_VEC_REG), + .PL_SRIS_SKPOS_REC_SPD_VEC (PL_SRIS_SKPOS_REC_SPD_VEC_REG), + .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING_REG), + .PL_USER_SPARE (PL_USER_SPARE_REG), + .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT_REG), + .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY_REG), + .PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY_REG), + .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE_REG), + .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY_REG), + .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY_REG), + .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY_REG), + .SPARE_BIT0 (SPARE_BIT0_REG), + .SPARE_BIT1 (SPARE_BIT1_REG), + .SPARE_BIT2 (SPARE_BIT2_REG), + .SPARE_BIT3 (SPARE_BIT3_REG), + .SPARE_BIT4 (SPARE_BIT4_REG), + .SPARE_BIT5 (SPARE_BIT5_REG), + .SPARE_BIT6 (SPARE_BIT6_REG), + .SPARE_BIT7 (SPARE_BIT7_REG), + .SPARE_BIT8 (SPARE_BIT8_REG), + .SPARE_BYTE0 (SPARE_BYTE0_REG), + .SPARE_BYTE1 (SPARE_BYTE1_REG), + .SPARE_BYTE2 (SPARE_BYTE2_REG), + .SPARE_BYTE3 (SPARE_BYTE3_REG), + .SPARE_WORD0 (SPARE_WORD0_REG), + .SPARE_WORD1 (SPARE_WORD1_REG), + .SPARE_WORD2 (SPARE_WORD2_REG), + .SPARE_WORD3 (SPARE_WORD3_REG), + .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .TL2CFG_IF_PARITY_CHK (TL2CFG_IF_PARITY_CHK_REG), + .TL_COMPLETION_RAM_NUM_TLPS (TL_COMPLETION_RAM_NUM_TLPS_REG), + .TL_COMPLETION_RAM_SIZE (TL_COMPLETION_RAM_SIZE_REG), + .TL_CREDITS_CD (TL_CREDITS_CD_REG), + .TL_CREDITS_CH (TL_CREDITS_CH_REG), + .TL_CREDITS_NPD (TL_CREDITS_NPD_REG), + .TL_CREDITS_NPH (TL_CREDITS_NPH_REG), + .TL_CREDITS_PD (TL_CREDITS_PD_REG), + .TL_CREDITS_PH (TL_CREDITS_PH_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TIME (TL_FC_UPDATE_MIN_INTERVAL_TIME_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT (TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_REG), + .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG_REG), + .TL_POSTED_RAM_SIZE (TL_POSTED_RAM_SIZE_REG), + .TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE (TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG), + .TL_RX_COMPLETION_TO_RAM_READ_PIPELINE (TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG), + .TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE (TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG), + .TL_RX_POSTED_FROM_RAM_READ_PIPELINE (TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG), + .TL_RX_POSTED_TO_RAM_READ_PIPELINE (TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG), + .TL_RX_POSTED_TO_RAM_WRITE_PIPELINE (TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG), + .TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY_REG), + .TL_TX_TLP_STRADDLE_ENABLE (TL_TX_TLP_STRADDLE_ENABLE_REG), + .TL_TX_TLP_TERMINATE_PARITY (TL_TX_TLP_TERMINATE_PARITY_REG), + .TL_USER_SPARE (TL_USER_SPARE_REG), + .TPH_FROM_RAM_PIPELINE (TPH_FROM_RAM_PIPELINE_REG), + .TPH_TO_RAM_PIPELINE (TPH_TO_RAM_PIPELINE_REG), + .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER_REG), + .VFG0_ARI_CAP_NEXTPTR (VFG0_ARI_CAP_NEXTPTR_REG), + .VFG0_MSIX_CAP_NEXTPTR (VFG0_MSIX_CAP_NEXTPTR_REG), + .VFG0_MSIX_CAP_PBA_BIR (VFG0_MSIX_CAP_PBA_BIR_REG), + .VFG0_MSIX_CAP_PBA_OFFSET (VFG0_MSIX_CAP_PBA_OFFSET_REG), + .VFG0_MSIX_CAP_TABLE_BIR (VFG0_MSIX_CAP_TABLE_BIR_REG), + .VFG0_MSIX_CAP_TABLE_OFFSET (VFG0_MSIX_CAP_TABLE_OFFSET_REG), + .VFG0_MSIX_CAP_TABLE_SIZE (VFG0_MSIX_CAP_TABLE_SIZE_REG), + .VFG0_PCIE_CAP_NEXTPTR (VFG0_PCIE_CAP_NEXTPTR_REG), + .VFG0_TPHR_CAP_NEXTPTR (VFG0_TPHR_CAP_NEXTPTR_REG), + .VFG0_TPHR_CAP_ST_MODE_SEL (VFG0_TPHR_CAP_ST_MODE_SEL_REG), + .VFG1_ARI_CAP_NEXTPTR (VFG1_ARI_CAP_NEXTPTR_REG), + .VFG1_MSIX_CAP_NEXTPTR (VFG1_MSIX_CAP_NEXTPTR_REG), + .VFG1_MSIX_CAP_PBA_BIR (VFG1_MSIX_CAP_PBA_BIR_REG), + .VFG1_MSIX_CAP_PBA_OFFSET (VFG1_MSIX_CAP_PBA_OFFSET_REG), + .VFG1_MSIX_CAP_TABLE_BIR (VFG1_MSIX_CAP_TABLE_BIR_REG), + .VFG1_MSIX_CAP_TABLE_OFFSET (VFG1_MSIX_CAP_TABLE_OFFSET_REG), + .VFG1_MSIX_CAP_TABLE_SIZE (VFG1_MSIX_CAP_TABLE_SIZE_REG), + .VFG1_PCIE_CAP_NEXTPTR (VFG1_PCIE_CAP_NEXTPTR_REG), + .VFG1_TPHR_CAP_NEXTPTR (VFG1_TPHR_CAP_NEXTPTR_REG), + .VFG1_TPHR_CAP_ST_MODE_SEL (VFG1_TPHR_CAP_ST_MODE_SEL_REG), + .VFG2_ARI_CAP_NEXTPTR (VFG2_ARI_CAP_NEXTPTR_REG), + .VFG2_MSIX_CAP_NEXTPTR (VFG2_MSIX_CAP_NEXTPTR_REG), + .VFG2_MSIX_CAP_PBA_BIR (VFG2_MSIX_CAP_PBA_BIR_REG), + .VFG2_MSIX_CAP_PBA_OFFSET (VFG2_MSIX_CAP_PBA_OFFSET_REG), + .VFG2_MSIX_CAP_TABLE_BIR (VFG2_MSIX_CAP_TABLE_BIR_REG), + .VFG2_MSIX_CAP_TABLE_OFFSET (VFG2_MSIX_CAP_TABLE_OFFSET_REG), + .VFG2_MSIX_CAP_TABLE_SIZE (VFG2_MSIX_CAP_TABLE_SIZE_REG), + .VFG2_PCIE_CAP_NEXTPTR (VFG2_PCIE_CAP_NEXTPTR_REG), + .VFG2_TPHR_CAP_NEXTPTR (VFG2_TPHR_CAP_NEXTPTR_REG), + .VFG2_TPHR_CAP_ST_MODE_SEL (VFG2_TPHR_CAP_ST_MODE_SEL_REG), + .VFG3_ARI_CAP_NEXTPTR (VFG3_ARI_CAP_NEXTPTR_REG), + .VFG3_MSIX_CAP_NEXTPTR (VFG3_MSIX_CAP_NEXTPTR_REG), + .VFG3_MSIX_CAP_PBA_BIR (VFG3_MSIX_CAP_PBA_BIR_REG), + .VFG3_MSIX_CAP_PBA_OFFSET (VFG3_MSIX_CAP_PBA_OFFSET_REG), + .VFG3_MSIX_CAP_TABLE_BIR (VFG3_MSIX_CAP_TABLE_BIR_REG), + .VFG3_MSIX_CAP_TABLE_OFFSET (VFG3_MSIX_CAP_TABLE_OFFSET_REG), + .VFG3_MSIX_CAP_TABLE_SIZE (VFG3_MSIX_CAP_TABLE_SIZE_REG), + .VFG3_PCIE_CAP_NEXTPTR (VFG3_PCIE_CAP_NEXTPTR_REG), + .VFG3_TPHR_CAP_NEXTPTR (VFG3_TPHR_CAP_NEXTPTR_REG), + .VFG3_TPHR_CAP_ST_MODE_SEL (VFG3_TPHR_CAP_ST_MODE_SEL_REG), + .AXIUSEROUT (AXIUSEROUT_out), + .CFGBUSNUMBER (CFGBUSNUMBER_out), + .CFGCURRENTSPEED (CFGCURRENTSPEED_out), + .CFGERRCOROUT (CFGERRCOROUT_out), + .CFGERRFATALOUT (CFGERRFATALOUT_out), + .CFGERRNONFATALOUT (CFGERRNONFATALOUT_out), + .CFGEXTFUNCTIONNUMBER (CFGEXTFUNCTIONNUMBER_out), + .CFGEXTREADRECEIVED (CFGEXTREADRECEIVED_out), + .CFGEXTREGISTERNUMBER (CFGEXTREGISTERNUMBER_out), + .CFGEXTWRITEBYTEENABLE (CFGEXTWRITEBYTEENABLE_out), + .CFGEXTWRITEDATA (CFGEXTWRITEDATA_out), + .CFGEXTWRITERECEIVED (CFGEXTWRITERECEIVED_out), + .CFGFCCPLD (CFGFCCPLD_out), + .CFGFCCPLH (CFGFCCPLH_out), + .CFGFCNPD (CFGFCNPD_out), + .CFGFCNPH (CFGFCNPH_out), + .CFGFCPD (CFGFCPD_out), + .CFGFCPH (CFGFCPH_out), + .CFGFLRINPROCESS (CFGFLRINPROCESS_out), + .CFGFUNCTIONPOWERSTATE (CFGFUNCTIONPOWERSTATE_out), + .CFGFUNCTIONSTATUS (CFGFUNCTIONSTATUS_out), + .CFGHOTRESETOUT (CFGHOTRESETOUT_out), + .CFGINTERRUPTMSIDATA (CFGINTERRUPTMSIDATA_out), + .CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE_out), + .CFGINTERRUPTMSIFAIL (CFGINTERRUPTMSIFAIL_out), + .CFGINTERRUPTMSIMASKUPDATE (CFGINTERRUPTMSIMASKUPDATE_out), + .CFGINTERRUPTMSIMMENABLE (CFGINTERRUPTMSIMMENABLE_out), + .CFGINTERRUPTMSISENT (CFGINTERRUPTMSISENT_out), + .CFGINTERRUPTMSIXENABLE (CFGINTERRUPTMSIXENABLE_out), + .CFGINTERRUPTMSIXMASK (CFGINTERRUPTMSIXMASK_out), + .CFGINTERRUPTMSIXVECPENDINGSTATUS (CFGINTERRUPTMSIXVECPENDINGSTATUS_out), + .CFGINTERRUPTSENT (CFGINTERRUPTSENT_out), + .CFGLINKPOWERSTATE (CFGLINKPOWERSTATE_out), + .CFGLOCALERROROUT (CFGLOCALERROROUT_out), + .CFGLOCALERRORVALID (CFGLOCALERRORVALID_out), + .CFGLTRENABLE (CFGLTRENABLE_out), + .CFGLTSSMSTATE (CFGLTSSMSTATE_out), + .CFGMAXPAYLOAD (CFGMAXPAYLOAD_out), + .CFGMAXREADREQ (CFGMAXREADREQ_out), + .CFGMGMTREADDATA (CFGMGMTREADDATA_out), + .CFGMGMTREADWRITEDONE (CFGMGMTREADWRITEDONE_out), + .CFGMSGRECEIVED (CFGMSGRECEIVED_out), + .CFGMSGRECEIVEDDATA (CFGMSGRECEIVEDDATA_out), + .CFGMSGRECEIVEDTYPE (CFGMSGRECEIVEDTYPE_out), + .CFGMSGTRANSMITDONE (CFGMSGTRANSMITDONE_out), + .CFGMSIXRAMADDRESS (CFGMSIXRAMADDRESS_out), + .CFGMSIXRAMREADENABLE (CFGMSIXRAMREADENABLE_out), + .CFGMSIXRAMWRITEBYTEENABLE (CFGMSIXRAMWRITEBYTEENABLE_out), + .CFGMSIXRAMWRITEDATA (CFGMSIXRAMWRITEDATA_out), + .CFGNEGOTIATEDWIDTH (CFGNEGOTIATEDWIDTH_out), + .CFGOBFFENABLE (CFGOBFFENABLE_out), + .CFGPHYLINKDOWN (CFGPHYLINKDOWN_out), + .CFGPHYLINKSTATUS (CFGPHYLINKSTATUS_out), + .CFGPLSTATUSCHANGE (CFGPLSTATUSCHANGE_out), + .CFGPOWERSTATECHANGEINTERRUPT (CFGPOWERSTATECHANGEINTERRUPT_out), + .CFGRCBSTATUS (CFGRCBSTATUS_out), + .CFGRXPMSTATE (CFGRXPMSTATE_out), + .CFGTPHRAMADDRESS (CFGTPHRAMADDRESS_out), + .CFGTPHRAMREADENABLE (CFGTPHRAMREADENABLE_out), + .CFGTPHRAMWRITEBYTEENABLE (CFGTPHRAMWRITEBYTEENABLE_out), + .CFGTPHRAMWRITEDATA (CFGTPHRAMWRITEDATA_out), + .CFGTPHREQUESTERENABLE (CFGTPHREQUESTERENABLE_out), + .CFGTPHSTMODE (CFGTPHSTMODE_out), + .CFGTXPMSTATE (CFGTXPMSTATE_out), + .CONFMCAPDESIGNSWITCH (CONFMCAPDESIGNSWITCH_out), + .CONFMCAPEOS (CONFMCAPEOS_out), + .CONFMCAPINUSEBYPCIE (CONFMCAPINUSEBYPCIE_out), + .CONFREQREADY (CONFREQREADY_out), + .CONFRESPRDATA (CONFRESPRDATA_out), + .CONFRESPVALID (CONFRESPVALID_out), + .DBGCTRL0OUT (DBGCTRL0OUT_out), + .DBGCTRL1OUT (DBGCTRL1OUT_out), + .DBGDATA0OUT (DBGDATA0OUT_out), + .DBGDATA1OUT (DBGDATA1OUT_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .MAXISCQTDATA (MAXISCQTDATA_out), + .MAXISCQTKEEP (MAXISCQTKEEP_out), + .MAXISCQTLAST (MAXISCQTLAST_out), + .MAXISCQTUSER (MAXISCQTUSER_out), + .MAXISCQTVALID (MAXISCQTVALID_out), + .MAXISRCTDATA (MAXISRCTDATA_out), + .MAXISRCTKEEP (MAXISRCTKEEP_out), + .MAXISRCTLAST (MAXISRCTLAST_out), + .MAXISRCTUSER (MAXISRCTUSER_out), + .MAXISRCTVALID (MAXISRCTVALID_out), + .MIREPLAYRAMADDRESS0 (MIREPLAYRAMADDRESS0_out), + .MIREPLAYRAMADDRESS1 (MIREPLAYRAMADDRESS1_out), + .MIREPLAYRAMREADENABLE0 (MIREPLAYRAMREADENABLE0_out), + .MIREPLAYRAMREADENABLE1 (MIREPLAYRAMREADENABLE1_out), + .MIREPLAYRAMWRITEDATA0 (MIREPLAYRAMWRITEDATA0_out), + .MIREPLAYRAMWRITEDATA1 (MIREPLAYRAMWRITEDATA1_out), + .MIREPLAYRAMWRITEENABLE0 (MIREPLAYRAMWRITEENABLE0_out), + .MIREPLAYRAMWRITEENABLE1 (MIREPLAYRAMWRITEENABLE1_out), + .MIRXCOMPLETIONRAMREADADDRESS0 (MIRXCOMPLETIONRAMREADADDRESS0_out), + .MIRXCOMPLETIONRAMREADADDRESS1 (MIRXCOMPLETIONRAMREADADDRESS1_out), + .MIRXCOMPLETIONRAMREADENABLE0 (MIRXCOMPLETIONRAMREADENABLE0_out), + .MIRXCOMPLETIONRAMREADENABLE1 (MIRXCOMPLETIONRAMREADENABLE1_out), + .MIRXCOMPLETIONRAMWRITEADDRESS0 (MIRXCOMPLETIONRAMWRITEADDRESS0_out), + .MIRXCOMPLETIONRAMWRITEADDRESS1 (MIRXCOMPLETIONRAMWRITEADDRESS1_out), + .MIRXCOMPLETIONRAMWRITEDATA0 (MIRXCOMPLETIONRAMWRITEDATA0_out), + .MIRXCOMPLETIONRAMWRITEDATA1 (MIRXCOMPLETIONRAMWRITEDATA1_out), + .MIRXCOMPLETIONRAMWRITEENABLE0 (MIRXCOMPLETIONRAMWRITEENABLE0_out), + .MIRXCOMPLETIONRAMWRITEENABLE1 (MIRXCOMPLETIONRAMWRITEENABLE1_out), + .MIRXPOSTEDREQUESTRAMREADADDRESS0 (MIRXPOSTEDREQUESTRAMREADADDRESS0_out), + .MIRXPOSTEDREQUESTRAMREADADDRESS1 (MIRXPOSTEDREQUESTRAMREADADDRESS1_out), + .MIRXPOSTEDREQUESTRAMREADENABLE0 (MIRXPOSTEDREQUESTRAMREADENABLE0_out), + .MIRXPOSTEDREQUESTRAMREADENABLE1 (MIRXPOSTEDREQUESTRAMREADENABLE1_out), + .MIRXPOSTEDREQUESTRAMWRITEADDRESS0 (MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out), + .MIRXPOSTEDREQUESTRAMWRITEADDRESS1 (MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out), + .MIRXPOSTEDREQUESTRAMWRITEDATA0 (MIRXPOSTEDREQUESTRAMWRITEDATA0_out), + .MIRXPOSTEDREQUESTRAMWRITEDATA1 (MIRXPOSTEDREQUESTRAMWRITEDATA1_out), + .MIRXPOSTEDREQUESTRAMWRITEENABLE0 (MIRXPOSTEDREQUESTRAMWRITEENABLE0_out), + .MIRXPOSTEDREQUESTRAMWRITEENABLE1 (MIRXPOSTEDREQUESTRAMWRITEENABLE1_out), + .PCIECQNPREQCOUNT (PCIECQNPREQCOUNT_out), + .PCIEPERST0B (PCIEPERST0B_out), + .PCIEPERST1B (PCIEPERST1B_out), + .PCIERQSEQNUM0 (PCIERQSEQNUM0_out), + .PCIERQSEQNUM1 (PCIERQSEQNUM1_out), + .PCIERQSEQNUMVLD0 (PCIERQSEQNUMVLD0_out), + .PCIERQSEQNUMVLD1 (PCIERQSEQNUMVLD1_out), + .PCIERQTAG0 (PCIERQTAG0_out), + .PCIERQTAG1 (PCIERQTAG1_out), + .PCIERQTAGAV (PCIERQTAGAV_out), + .PCIERQTAGVLD0 (PCIERQTAGVLD0_out), + .PCIERQTAGVLD1 (PCIERQTAGVLD1_out), + .PCIETFCNPDAV (PCIETFCNPDAV_out), + .PCIETFCNPHAV (PCIETFCNPHAV_out), + .PIPERX00EQCONTROL (PIPERX00EQCONTROL_out), + .PIPERX00POLARITY (PIPERX00POLARITY_out), + .PIPERX01EQCONTROL (PIPERX01EQCONTROL_out), + .PIPERX01POLARITY (PIPERX01POLARITY_out), + .PIPERX02EQCONTROL (PIPERX02EQCONTROL_out), + .PIPERX02POLARITY (PIPERX02POLARITY_out), + .PIPERX03EQCONTROL (PIPERX03EQCONTROL_out), + .PIPERX03POLARITY (PIPERX03POLARITY_out), + .PIPERX04EQCONTROL (PIPERX04EQCONTROL_out), + .PIPERX04POLARITY (PIPERX04POLARITY_out), + .PIPERX05EQCONTROL (PIPERX05EQCONTROL_out), + .PIPERX05POLARITY (PIPERX05POLARITY_out), + .PIPERX06EQCONTROL (PIPERX06EQCONTROL_out), + .PIPERX06POLARITY (PIPERX06POLARITY_out), + .PIPERX07EQCONTROL (PIPERX07EQCONTROL_out), + .PIPERX07POLARITY (PIPERX07POLARITY_out), + .PIPERX08EQCONTROL (PIPERX08EQCONTROL_out), + .PIPERX08POLARITY (PIPERX08POLARITY_out), + .PIPERX09EQCONTROL (PIPERX09EQCONTROL_out), + .PIPERX09POLARITY (PIPERX09POLARITY_out), + .PIPERX10EQCONTROL (PIPERX10EQCONTROL_out), + .PIPERX10POLARITY (PIPERX10POLARITY_out), + .PIPERX11EQCONTROL (PIPERX11EQCONTROL_out), + .PIPERX11POLARITY (PIPERX11POLARITY_out), + .PIPERX12EQCONTROL (PIPERX12EQCONTROL_out), + .PIPERX12POLARITY (PIPERX12POLARITY_out), + .PIPERX13EQCONTROL (PIPERX13EQCONTROL_out), + .PIPERX13POLARITY (PIPERX13POLARITY_out), + .PIPERX14EQCONTROL (PIPERX14EQCONTROL_out), + .PIPERX14POLARITY (PIPERX14POLARITY_out), + .PIPERX15EQCONTROL (PIPERX15EQCONTROL_out), + .PIPERX15POLARITY (PIPERX15POLARITY_out), + .PIPERXEQLPLFFS (PIPERXEQLPLFFS_out), + .PIPERXEQLPTXPRESET (PIPERXEQLPTXPRESET_out), + .PIPETX00CHARISK (PIPETX00CHARISK_out), + .PIPETX00COMPLIANCE (PIPETX00COMPLIANCE_out), + .PIPETX00DATA (PIPETX00DATA_out), + .PIPETX00DATAVALID (PIPETX00DATAVALID_out), + .PIPETX00ELECIDLE (PIPETX00ELECIDLE_out), + .PIPETX00EQCONTROL (PIPETX00EQCONTROL_out), + .PIPETX00EQDEEMPH (PIPETX00EQDEEMPH_out), + .PIPETX00POWERDOWN (PIPETX00POWERDOWN_out), + .PIPETX00STARTBLOCK (PIPETX00STARTBLOCK_out), + .PIPETX00SYNCHEADER (PIPETX00SYNCHEADER_out), + .PIPETX01CHARISK (PIPETX01CHARISK_out), + .PIPETX01COMPLIANCE (PIPETX01COMPLIANCE_out), + .PIPETX01DATA (PIPETX01DATA_out), + .PIPETX01DATAVALID (PIPETX01DATAVALID_out), + .PIPETX01ELECIDLE (PIPETX01ELECIDLE_out), + .PIPETX01EQCONTROL (PIPETX01EQCONTROL_out), + .PIPETX01EQDEEMPH (PIPETX01EQDEEMPH_out), + .PIPETX01POWERDOWN (PIPETX01POWERDOWN_out), + .PIPETX01STARTBLOCK (PIPETX01STARTBLOCK_out), + .PIPETX01SYNCHEADER (PIPETX01SYNCHEADER_out), + .PIPETX02CHARISK (PIPETX02CHARISK_out), + .PIPETX02COMPLIANCE (PIPETX02COMPLIANCE_out), + .PIPETX02DATA (PIPETX02DATA_out), + .PIPETX02DATAVALID (PIPETX02DATAVALID_out), + .PIPETX02ELECIDLE (PIPETX02ELECIDLE_out), + .PIPETX02EQCONTROL (PIPETX02EQCONTROL_out), + .PIPETX02EQDEEMPH (PIPETX02EQDEEMPH_out), + .PIPETX02POWERDOWN (PIPETX02POWERDOWN_out), + .PIPETX02STARTBLOCK (PIPETX02STARTBLOCK_out), + .PIPETX02SYNCHEADER (PIPETX02SYNCHEADER_out), + .PIPETX03CHARISK (PIPETX03CHARISK_out), + .PIPETX03COMPLIANCE (PIPETX03COMPLIANCE_out), + .PIPETX03DATA (PIPETX03DATA_out), + .PIPETX03DATAVALID (PIPETX03DATAVALID_out), + .PIPETX03ELECIDLE (PIPETX03ELECIDLE_out), + .PIPETX03EQCONTROL (PIPETX03EQCONTROL_out), + .PIPETX03EQDEEMPH (PIPETX03EQDEEMPH_out), + .PIPETX03POWERDOWN (PIPETX03POWERDOWN_out), + .PIPETX03STARTBLOCK (PIPETX03STARTBLOCK_out), + .PIPETX03SYNCHEADER (PIPETX03SYNCHEADER_out), + .PIPETX04CHARISK (PIPETX04CHARISK_out), + .PIPETX04COMPLIANCE (PIPETX04COMPLIANCE_out), + .PIPETX04DATA (PIPETX04DATA_out), + .PIPETX04DATAVALID (PIPETX04DATAVALID_out), + .PIPETX04ELECIDLE (PIPETX04ELECIDLE_out), + .PIPETX04EQCONTROL (PIPETX04EQCONTROL_out), + .PIPETX04EQDEEMPH (PIPETX04EQDEEMPH_out), + .PIPETX04POWERDOWN (PIPETX04POWERDOWN_out), + .PIPETX04STARTBLOCK (PIPETX04STARTBLOCK_out), + .PIPETX04SYNCHEADER (PIPETX04SYNCHEADER_out), + .PIPETX05CHARISK (PIPETX05CHARISK_out), + .PIPETX05COMPLIANCE (PIPETX05COMPLIANCE_out), + .PIPETX05DATA (PIPETX05DATA_out), + .PIPETX05DATAVALID (PIPETX05DATAVALID_out), + .PIPETX05ELECIDLE (PIPETX05ELECIDLE_out), + .PIPETX05EQCONTROL (PIPETX05EQCONTROL_out), + .PIPETX05EQDEEMPH (PIPETX05EQDEEMPH_out), + .PIPETX05POWERDOWN (PIPETX05POWERDOWN_out), + .PIPETX05STARTBLOCK (PIPETX05STARTBLOCK_out), + .PIPETX05SYNCHEADER (PIPETX05SYNCHEADER_out), + .PIPETX06CHARISK (PIPETX06CHARISK_out), + .PIPETX06COMPLIANCE (PIPETX06COMPLIANCE_out), + .PIPETX06DATA (PIPETX06DATA_out), + .PIPETX06DATAVALID (PIPETX06DATAVALID_out), + .PIPETX06ELECIDLE (PIPETX06ELECIDLE_out), + .PIPETX06EQCONTROL (PIPETX06EQCONTROL_out), + .PIPETX06EQDEEMPH (PIPETX06EQDEEMPH_out), + .PIPETX06POWERDOWN (PIPETX06POWERDOWN_out), + .PIPETX06STARTBLOCK (PIPETX06STARTBLOCK_out), + .PIPETX06SYNCHEADER (PIPETX06SYNCHEADER_out), + .PIPETX07CHARISK (PIPETX07CHARISK_out), + .PIPETX07COMPLIANCE (PIPETX07COMPLIANCE_out), + .PIPETX07DATA (PIPETX07DATA_out), + .PIPETX07DATAVALID (PIPETX07DATAVALID_out), + .PIPETX07ELECIDLE (PIPETX07ELECIDLE_out), + .PIPETX07EQCONTROL (PIPETX07EQCONTROL_out), + .PIPETX07EQDEEMPH (PIPETX07EQDEEMPH_out), + .PIPETX07POWERDOWN (PIPETX07POWERDOWN_out), + .PIPETX07STARTBLOCK (PIPETX07STARTBLOCK_out), + .PIPETX07SYNCHEADER (PIPETX07SYNCHEADER_out), + .PIPETX08CHARISK (PIPETX08CHARISK_out), + .PIPETX08COMPLIANCE (PIPETX08COMPLIANCE_out), + .PIPETX08DATA (PIPETX08DATA_out), + .PIPETX08DATAVALID (PIPETX08DATAVALID_out), + .PIPETX08ELECIDLE (PIPETX08ELECIDLE_out), + .PIPETX08EQCONTROL (PIPETX08EQCONTROL_out), + .PIPETX08EQDEEMPH (PIPETX08EQDEEMPH_out), + .PIPETX08POWERDOWN (PIPETX08POWERDOWN_out), + .PIPETX08STARTBLOCK (PIPETX08STARTBLOCK_out), + .PIPETX08SYNCHEADER (PIPETX08SYNCHEADER_out), + .PIPETX09CHARISK (PIPETX09CHARISK_out), + .PIPETX09COMPLIANCE (PIPETX09COMPLIANCE_out), + .PIPETX09DATA (PIPETX09DATA_out), + .PIPETX09DATAVALID (PIPETX09DATAVALID_out), + .PIPETX09ELECIDLE (PIPETX09ELECIDLE_out), + .PIPETX09EQCONTROL (PIPETX09EQCONTROL_out), + .PIPETX09EQDEEMPH (PIPETX09EQDEEMPH_out), + .PIPETX09POWERDOWN (PIPETX09POWERDOWN_out), + .PIPETX09STARTBLOCK (PIPETX09STARTBLOCK_out), + .PIPETX09SYNCHEADER (PIPETX09SYNCHEADER_out), + .PIPETX10CHARISK (PIPETX10CHARISK_out), + .PIPETX10COMPLIANCE (PIPETX10COMPLIANCE_out), + .PIPETX10DATA (PIPETX10DATA_out), + .PIPETX10DATAVALID (PIPETX10DATAVALID_out), + .PIPETX10ELECIDLE (PIPETX10ELECIDLE_out), + .PIPETX10EQCONTROL (PIPETX10EQCONTROL_out), + .PIPETX10EQDEEMPH (PIPETX10EQDEEMPH_out), + .PIPETX10POWERDOWN (PIPETX10POWERDOWN_out), + .PIPETX10STARTBLOCK (PIPETX10STARTBLOCK_out), + .PIPETX10SYNCHEADER (PIPETX10SYNCHEADER_out), + .PIPETX11CHARISK (PIPETX11CHARISK_out), + .PIPETX11COMPLIANCE (PIPETX11COMPLIANCE_out), + .PIPETX11DATA (PIPETX11DATA_out), + .PIPETX11DATAVALID (PIPETX11DATAVALID_out), + .PIPETX11ELECIDLE (PIPETX11ELECIDLE_out), + .PIPETX11EQCONTROL (PIPETX11EQCONTROL_out), + .PIPETX11EQDEEMPH (PIPETX11EQDEEMPH_out), + .PIPETX11POWERDOWN (PIPETX11POWERDOWN_out), + .PIPETX11STARTBLOCK (PIPETX11STARTBLOCK_out), + .PIPETX11SYNCHEADER (PIPETX11SYNCHEADER_out), + .PIPETX12CHARISK (PIPETX12CHARISK_out), + .PIPETX12COMPLIANCE (PIPETX12COMPLIANCE_out), + .PIPETX12DATA (PIPETX12DATA_out), + .PIPETX12DATAVALID (PIPETX12DATAVALID_out), + .PIPETX12ELECIDLE (PIPETX12ELECIDLE_out), + .PIPETX12EQCONTROL (PIPETX12EQCONTROL_out), + .PIPETX12EQDEEMPH (PIPETX12EQDEEMPH_out), + .PIPETX12POWERDOWN (PIPETX12POWERDOWN_out), + .PIPETX12STARTBLOCK (PIPETX12STARTBLOCK_out), + .PIPETX12SYNCHEADER (PIPETX12SYNCHEADER_out), + .PIPETX13CHARISK (PIPETX13CHARISK_out), + .PIPETX13COMPLIANCE (PIPETX13COMPLIANCE_out), + .PIPETX13DATA (PIPETX13DATA_out), + .PIPETX13DATAVALID (PIPETX13DATAVALID_out), + .PIPETX13ELECIDLE (PIPETX13ELECIDLE_out), + .PIPETX13EQCONTROL (PIPETX13EQCONTROL_out), + .PIPETX13EQDEEMPH (PIPETX13EQDEEMPH_out), + .PIPETX13POWERDOWN (PIPETX13POWERDOWN_out), + .PIPETX13STARTBLOCK (PIPETX13STARTBLOCK_out), + .PIPETX13SYNCHEADER (PIPETX13SYNCHEADER_out), + .PIPETX14CHARISK (PIPETX14CHARISK_out), + .PIPETX14COMPLIANCE (PIPETX14COMPLIANCE_out), + .PIPETX14DATA (PIPETX14DATA_out), + .PIPETX14DATAVALID (PIPETX14DATAVALID_out), + .PIPETX14ELECIDLE (PIPETX14ELECIDLE_out), + .PIPETX14EQCONTROL (PIPETX14EQCONTROL_out), + .PIPETX14EQDEEMPH (PIPETX14EQDEEMPH_out), + .PIPETX14POWERDOWN (PIPETX14POWERDOWN_out), + .PIPETX14STARTBLOCK (PIPETX14STARTBLOCK_out), + .PIPETX14SYNCHEADER (PIPETX14SYNCHEADER_out), + .PIPETX15CHARISK (PIPETX15CHARISK_out), + .PIPETX15COMPLIANCE (PIPETX15COMPLIANCE_out), + .PIPETX15DATA (PIPETX15DATA_out), + .PIPETX15DATAVALID (PIPETX15DATAVALID_out), + .PIPETX15ELECIDLE (PIPETX15ELECIDLE_out), + .PIPETX15EQCONTROL (PIPETX15EQCONTROL_out), + .PIPETX15EQDEEMPH (PIPETX15EQDEEMPH_out), + .PIPETX15POWERDOWN (PIPETX15POWERDOWN_out), + .PIPETX15STARTBLOCK (PIPETX15STARTBLOCK_out), + .PIPETX15SYNCHEADER (PIPETX15SYNCHEADER_out), + .PIPETXDEEMPH (PIPETXDEEMPH_out), + .PIPETXMARGIN (PIPETXMARGIN_out), + .PIPETXRATE (PIPETXRATE_out), + .PIPETXRCVRDET (PIPETXRCVRDET_out), + .PIPETXRESET (PIPETXRESET_out), + .PIPETXSWING (PIPETXSWING_out), + .PLEQINPROGRESS (PLEQINPROGRESS_out), + .PLEQPHASE (PLEQPHASE_out), + .PLGEN34EQMISMATCH (PLGEN34EQMISMATCH_out), + .PMVOUT (PMVOUT_out), + .SAXISCCTREADY (SAXISCCTREADY_out), + .SAXISRQTREADY (SAXISRQTREADY_out), + .SCANOUT (SCANOUT_out), + .USERSPAREOUT (USERSPAREOUT_out), + .AXIUSERIN (AXIUSERIN_in), + .CFGCONFIGSPACEENABLE (CFGCONFIGSPACEENABLE_in), + .CFGDEVIDPF0 (CFGDEVIDPF0_in), + .CFGDEVIDPF1 (CFGDEVIDPF1_in), + .CFGDEVIDPF2 (CFGDEVIDPF2_in), + .CFGDEVIDPF3 (CFGDEVIDPF3_in), + .CFGDSBUSNUMBER (CFGDSBUSNUMBER_in), + .CFGDSDEVICENUMBER (CFGDSDEVICENUMBER_in), + .CFGDSFUNCTIONNUMBER (CFGDSFUNCTIONNUMBER_in), + .CFGDSN (CFGDSN_in), + .CFGDSPORTNUMBER (CFGDSPORTNUMBER_in), + .CFGERRCORIN (CFGERRCORIN_in), + .CFGERRUNCORIN (CFGERRUNCORIN_in), + .CFGEXTREADDATA (CFGEXTREADDATA_in), + .CFGEXTREADDATAVALID (CFGEXTREADDATAVALID_in), + .CFGFCSEL (CFGFCSEL_in), + .CFGFLRDONE (CFGFLRDONE_in), + .CFGHOTRESETIN (CFGHOTRESETIN_in), + .CFGINTERRUPTINT (CFGINTERRUPTINT_in), + .CFGINTERRUPTMSIATTR (CFGINTERRUPTMSIATTR_in), + .CFGINTERRUPTMSIFUNCTIONNUMBER (CFGINTERRUPTMSIFUNCTIONNUMBER_in), + .CFGINTERRUPTMSIINT (CFGINTERRUPTMSIINT_in), + .CFGINTERRUPTMSIPENDINGSTATUS (CFGINTERRUPTMSIPENDINGSTATUS_in), + .CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in), + .CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in), + .CFGINTERRUPTMSISELECT (CFGINTERRUPTMSISELECT_in), + .CFGINTERRUPTMSITPHPRESENT (CFGINTERRUPTMSITPHPRESENT_in), + .CFGINTERRUPTMSITPHSTTAG (CFGINTERRUPTMSITPHSTTAG_in), + .CFGINTERRUPTMSITPHTYPE (CFGINTERRUPTMSITPHTYPE_in), + .CFGINTERRUPTMSIXADDRESS (CFGINTERRUPTMSIXADDRESS_in), + .CFGINTERRUPTMSIXDATA (CFGINTERRUPTMSIXDATA_in), + .CFGINTERRUPTMSIXINT (CFGINTERRUPTMSIXINT_in), + .CFGINTERRUPTMSIXVECPENDING (CFGINTERRUPTMSIXVECPENDING_in), + .CFGINTERRUPTPENDING (CFGINTERRUPTPENDING_in), + .CFGLINKTRAININGENABLE (CFGLINKTRAININGENABLE_in), + .CFGMGMTADDR (CFGMGMTADDR_in), + .CFGMGMTBYTEENABLE (CFGMGMTBYTEENABLE_in), + .CFGMGMTDEBUGACCESS (CFGMGMTDEBUGACCESS_in), + .CFGMGMTFUNCTIONNUMBER (CFGMGMTFUNCTIONNUMBER_in), + .CFGMGMTREAD (CFGMGMTREAD_in), + .CFGMGMTWRITE (CFGMGMTWRITE_in), + .CFGMGMTWRITEDATA (CFGMGMTWRITEDATA_in), + .CFGMSGTRANSMIT (CFGMSGTRANSMIT_in), + .CFGMSGTRANSMITDATA (CFGMSGTRANSMITDATA_in), + .CFGMSGTRANSMITTYPE (CFGMSGTRANSMITTYPE_in), + .CFGMSIXRAMREADDATA (CFGMSIXRAMREADDATA_in), + .CFGPMASPML1ENTRYREJECT (CFGPMASPML1ENTRYREJECT_in), + .CFGPMASPMTXL0SENTRYDISABLE (CFGPMASPMTXL0SENTRYDISABLE_in), + .CFGPOWERSTATECHANGEACK (CFGPOWERSTATECHANGEACK_in), + .CFGREQPMTRANSITIONL23READY (CFGREQPMTRANSITIONL23READY_in), + .CFGREVIDPF0 (CFGREVIDPF0_in), + .CFGREVIDPF1 (CFGREVIDPF1_in), + .CFGREVIDPF2 (CFGREVIDPF2_in), + .CFGREVIDPF3 (CFGREVIDPF3_in), + .CFGSUBSYSIDPF0 (CFGSUBSYSIDPF0_in), + .CFGSUBSYSIDPF1 (CFGSUBSYSIDPF1_in), + .CFGSUBSYSIDPF2 (CFGSUBSYSIDPF2_in), + .CFGSUBSYSIDPF3 (CFGSUBSYSIDPF3_in), + .CFGSUBSYSVENDID (CFGSUBSYSVENDID_in), + .CFGTPHRAMREADDATA (CFGTPHRAMREADDATA_in), + .CFGVENDID (CFGVENDID_in), + .CFGVFFLRDONE (CFGVFFLRDONE_in), + .CFGVFFLRFUNCNUM (CFGVFFLRFUNCNUM_in), + .CONFMCAPREQUESTBYCONF (CONFMCAPREQUESTBYCONF_in), + .CONFREQDATA (CONFREQDATA_in), + .CONFREQREGNUM (CONFREQREGNUM_in), + .CONFREQTYPE (CONFREQTYPE_in), + .CONFREQVALID (CONFREQVALID_in), + .CORECLK (CORECLK_in), + .CORECLKMIREPLAYRAM0 (CORECLKMIREPLAYRAM0_in), + .CORECLKMIREPLAYRAM1 (CORECLKMIREPLAYRAM1_in), + .CORECLKMIRXCOMPLETIONRAM0 (CORECLKMIRXCOMPLETIONRAM0_in), + .CORECLKMIRXCOMPLETIONRAM1 (CORECLKMIRXCOMPLETIONRAM1_in), + .CORECLKMIRXPOSTEDREQUESTRAM0 (CORECLKMIRXPOSTEDREQUESTRAM0_in), + .CORECLKMIRXPOSTEDREQUESTRAM1 (CORECLKMIRXPOSTEDREQUESTRAM1_in), + .DBGSEL0 (DBGSEL0_in), + .DBGSEL1 (DBGSEL1_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .MAXISCQTREADY (MAXISCQTREADY_in), + .MAXISRCTREADY (MAXISRCTREADY_in), + .MCAPCLK (MCAPCLK_in), + .MCAPPERST0B (MCAPPERST0B_in), + .MCAPPERST1B (MCAPPERST1B_in), + .MGMTRESETN (MGMTRESETN_in), + .MGMTSTICKYRESETN (MGMTSTICKYRESETN_in), + .MIREPLAYRAMERRCOR (MIREPLAYRAMERRCOR_in), + .MIREPLAYRAMERRUNCOR (MIREPLAYRAMERRUNCOR_in), + .MIREPLAYRAMREADDATA0 (MIREPLAYRAMREADDATA0_in), + .MIREPLAYRAMREADDATA1 (MIREPLAYRAMREADDATA1_in), + .MIRXCOMPLETIONRAMERRCOR (MIRXCOMPLETIONRAMERRCOR_in), + .MIRXCOMPLETIONRAMERRUNCOR (MIRXCOMPLETIONRAMERRUNCOR_in), + .MIRXCOMPLETIONRAMREADDATA0 (MIRXCOMPLETIONRAMREADDATA0_in), + .MIRXCOMPLETIONRAMREADDATA1 (MIRXCOMPLETIONRAMREADDATA1_in), + .MIRXPOSTEDREQUESTRAMERRCOR (MIRXPOSTEDREQUESTRAMERRCOR_in), + .MIRXPOSTEDREQUESTRAMERRUNCOR (MIRXPOSTEDREQUESTRAMERRUNCOR_in), + .MIRXPOSTEDREQUESTRAMREADDATA0 (MIRXPOSTEDREQUESTRAMREADDATA0_in), + .MIRXPOSTEDREQUESTRAMREADDATA1 (MIRXPOSTEDREQUESTRAMREADDATA1_in), + .PCIECOMPLDELIVERED (PCIECOMPLDELIVERED_in), + .PCIECOMPLDELIVEREDTAG0 (PCIECOMPLDELIVEREDTAG0_in), + .PCIECOMPLDELIVEREDTAG1 (PCIECOMPLDELIVEREDTAG1_in), + .PCIECQNPREQ (PCIECQNPREQ_in), + .PCIECQNPUSERCREDITRCVD (PCIECQNPUSERCREDITRCVD_in), + .PCIECQPIPELINEEMPTY (PCIECQPIPELINEEMPTY_in), + .PCIEPOSTEDREQDELIVERED (PCIEPOSTEDREQDELIVERED_in), + .PIPECLK (PIPECLK_in), + .PIPECLKEN (PIPECLKEN_in), + .PIPEEQFS (PIPEEQFS_in), + .PIPEEQLF (PIPEEQLF_in), + .PIPERESETN (PIPERESETN_in), + .PIPERX00CHARISK (PIPERX00CHARISK_in), + .PIPERX00DATA (PIPERX00DATA_in), + .PIPERX00DATAVALID (PIPERX00DATAVALID_in), + .PIPERX00ELECIDLE (PIPERX00ELECIDLE_in), + .PIPERX00EQDONE (PIPERX00EQDONE_in), + .PIPERX00EQLPADAPTDONE (PIPERX00EQLPADAPTDONE_in), + .PIPERX00EQLPLFFSSEL (PIPERX00EQLPLFFSSEL_in), + .PIPERX00EQLPNEWTXCOEFFORPRESET (PIPERX00EQLPNEWTXCOEFFORPRESET_in), + .PIPERX00PHYSTATUS (PIPERX00PHYSTATUS_in), + .PIPERX00STARTBLOCK (PIPERX00STARTBLOCK_in), + .PIPERX00STATUS (PIPERX00STATUS_in), + .PIPERX00SYNCHEADER (PIPERX00SYNCHEADER_in), + .PIPERX00VALID (PIPERX00VALID_in), + .PIPERX01CHARISK (PIPERX01CHARISK_in), + .PIPERX01DATA (PIPERX01DATA_in), + .PIPERX01DATAVALID (PIPERX01DATAVALID_in), + .PIPERX01ELECIDLE (PIPERX01ELECIDLE_in), + .PIPERX01EQDONE (PIPERX01EQDONE_in), + .PIPERX01EQLPADAPTDONE (PIPERX01EQLPADAPTDONE_in), + .PIPERX01EQLPLFFSSEL (PIPERX01EQLPLFFSSEL_in), + .PIPERX01EQLPNEWTXCOEFFORPRESET (PIPERX01EQLPNEWTXCOEFFORPRESET_in), + .PIPERX01PHYSTATUS (PIPERX01PHYSTATUS_in), + .PIPERX01STARTBLOCK (PIPERX01STARTBLOCK_in), + .PIPERX01STATUS (PIPERX01STATUS_in), + .PIPERX01SYNCHEADER (PIPERX01SYNCHEADER_in), + .PIPERX01VALID (PIPERX01VALID_in), + .PIPERX02CHARISK (PIPERX02CHARISK_in), + .PIPERX02DATA (PIPERX02DATA_in), + .PIPERX02DATAVALID (PIPERX02DATAVALID_in), + .PIPERX02ELECIDLE (PIPERX02ELECIDLE_in), + .PIPERX02EQDONE (PIPERX02EQDONE_in), + .PIPERX02EQLPADAPTDONE (PIPERX02EQLPADAPTDONE_in), + .PIPERX02EQLPLFFSSEL (PIPERX02EQLPLFFSSEL_in), + .PIPERX02EQLPNEWTXCOEFFORPRESET (PIPERX02EQLPNEWTXCOEFFORPRESET_in), + .PIPERX02PHYSTATUS (PIPERX02PHYSTATUS_in), + .PIPERX02STARTBLOCK (PIPERX02STARTBLOCK_in), + .PIPERX02STATUS (PIPERX02STATUS_in), + .PIPERX02SYNCHEADER (PIPERX02SYNCHEADER_in), + .PIPERX02VALID (PIPERX02VALID_in), + .PIPERX03CHARISK (PIPERX03CHARISK_in), + .PIPERX03DATA (PIPERX03DATA_in), + .PIPERX03DATAVALID (PIPERX03DATAVALID_in), + .PIPERX03ELECIDLE (PIPERX03ELECIDLE_in), + .PIPERX03EQDONE (PIPERX03EQDONE_in), + .PIPERX03EQLPADAPTDONE (PIPERX03EQLPADAPTDONE_in), + .PIPERX03EQLPLFFSSEL (PIPERX03EQLPLFFSSEL_in), + .PIPERX03EQLPNEWTXCOEFFORPRESET (PIPERX03EQLPNEWTXCOEFFORPRESET_in), + .PIPERX03PHYSTATUS (PIPERX03PHYSTATUS_in), + .PIPERX03STARTBLOCK (PIPERX03STARTBLOCK_in), + .PIPERX03STATUS (PIPERX03STATUS_in), + .PIPERX03SYNCHEADER (PIPERX03SYNCHEADER_in), + .PIPERX03VALID (PIPERX03VALID_in), + .PIPERX04CHARISK (PIPERX04CHARISK_in), + .PIPERX04DATA (PIPERX04DATA_in), + .PIPERX04DATAVALID (PIPERX04DATAVALID_in), + .PIPERX04ELECIDLE (PIPERX04ELECIDLE_in), + .PIPERX04EQDONE (PIPERX04EQDONE_in), + .PIPERX04EQLPADAPTDONE (PIPERX04EQLPADAPTDONE_in), + .PIPERX04EQLPLFFSSEL (PIPERX04EQLPLFFSSEL_in), + .PIPERX04EQLPNEWTXCOEFFORPRESET (PIPERX04EQLPNEWTXCOEFFORPRESET_in), + .PIPERX04PHYSTATUS (PIPERX04PHYSTATUS_in), + .PIPERX04STARTBLOCK (PIPERX04STARTBLOCK_in), + .PIPERX04STATUS (PIPERX04STATUS_in), + .PIPERX04SYNCHEADER (PIPERX04SYNCHEADER_in), + .PIPERX04VALID (PIPERX04VALID_in), + .PIPERX05CHARISK (PIPERX05CHARISK_in), + .PIPERX05DATA (PIPERX05DATA_in), + .PIPERX05DATAVALID (PIPERX05DATAVALID_in), + .PIPERX05ELECIDLE (PIPERX05ELECIDLE_in), + .PIPERX05EQDONE (PIPERX05EQDONE_in), + .PIPERX05EQLPADAPTDONE (PIPERX05EQLPADAPTDONE_in), + .PIPERX05EQLPLFFSSEL (PIPERX05EQLPLFFSSEL_in), + .PIPERX05EQLPNEWTXCOEFFORPRESET (PIPERX05EQLPNEWTXCOEFFORPRESET_in), + .PIPERX05PHYSTATUS (PIPERX05PHYSTATUS_in), + .PIPERX05STARTBLOCK (PIPERX05STARTBLOCK_in), + .PIPERX05STATUS (PIPERX05STATUS_in), + .PIPERX05SYNCHEADER (PIPERX05SYNCHEADER_in), + .PIPERX05VALID (PIPERX05VALID_in), + .PIPERX06CHARISK (PIPERX06CHARISK_in), + .PIPERX06DATA (PIPERX06DATA_in), + .PIPERX06DATAVALID (PIPERX06DATAVALID_in), + .PIPERX06ELECIDLE (PIPERX06ELECIDLE_in), + .PIPERX06EQDONE (PIPERX06EQDONE_in), + .PIPERX06EQLPADAPTDONE (PIPERX06EQLPADAPTDONE_in), + .PIPERX06EQLPLFFSSEL (PIPERX06EQLPLFFSSEL_in), + .PIPERX06EQLPNEWTXCOEFFORPRESET (PIPERX06EQLPNEWTXCOEFFORPRESET_in), + .PIPERX06PHYSTATUS (PIPERX06PHYSTATUS_in), + .PIPERX06STARTBLOCK (PIPERX06STARTBLOCK_in), + .PIPERX06STATUS (PIPERX06STATUS_in), + .PIPERX06SYNCHEADER (PIPERX06SYNCHEADER_in), + .PIPERX06VALID (PIPERX06VALID_in), + .PIPERX07CHARISK (PIPERX07CHARISK_in), + .PIPERX07DATA (PIPERX07DATA_in), + .PIPERX07DATAVALID (PIPERX07DATAVALID_in), + .PIPERX07ELECIDLE (PIPERX07ELECIDLE_in), + .PIPERX07EQDONE (PIPERX07EQDONE_in), + .PIPERX07EQLPADAPTDONE (PIPERX07EQLPADAPTDONE_in), + .PIPERX07EQLPLFFSSEL (PIPERX07EQLPLFFSSEL_in), + .PIPERX07EQLPNEWTXCOEFFORPRESET (PIPERX07EQLPNEWTXCOEFFORPRESET_in), + .PIPERX07PHYSTATUS (PIPERX07PHYSTATUS_in), + .PIPERX07STARTBLOCK (PIPERX07STARTBLOCK_in), + .PIPERX07STATUS (PIPERX07STATUS_in), + .PIPERX07SYNCHEADER (PIPERX07SYNCHEADER_in), + .PIPERX07VALID (PIPERX07VALID_in), + .PIPERX08CHARISK (PIPERX08CHARISK_in), + .PIPERX08DATA (PIPERX08DATA_in), + .PIPERX08DATAVALID (PIPERX08DATAVALID_in), + .PIPERX08ELECIDLE (PIPERX08ELECIDLE_in), + .PIPERX08EQDONE (PIPERX08EQDONE_in), + .PIPERX08EQLPADAPTDONE (PIPERX08EQLPADAPTDONE_in), + .PIPERX08EQLPLFFSSEL (PIPERX08EQLPLFFSSEL_in), + .PIPERX08EQLPNEWTXCOEFFORPRESET (PIPERX08EQLPNEWTXCOEFFORPRESET_in), + .PIPERX08PHYSTATUS (PIPERX08PHYSTATUS_in), + .PIPERX08STARTBLOCK (PIPERX08STARTBLOCK_in), + .PIPERX08STATUS (PIPERX08STATUS_in), + .PIPERX08SYNCHEADER (PIPERX08SYNCHEADER_in), + .PIPERX08VALID (PIPERX08VALID_in), + .PIPERX09CHARISK (PIPERX09CHARISK_in), + .PIPERX09DATA (PIPERX09DATA_in), + .PIPERX09DATAVALID (PIPERX09DATAVALID_in), + .PIPERX09ELECIDLE (PIPERX09ELECIDLE_in), + .PIPERX09EQDONE (PIPERX09EQDONE_in), + .PIPERX09EQLPADAPTDONE (PIPERX09EQLPADAPTDONE_in), + .PIPERX09EQLPLFFSSEL (PIPERX09EQLPLFFSSEL_in), + .PIPERX09EQLPNEWTXCOEFFORPRESET (PIPERX09EQLPNEWTXCOEFFORPRESET_in), + .PIPERX09PHYSTATUS (PIPERX09PHYSTATUS_in), + .PIPERX09STARTBLOCK (PIPERX09STARTBLOCK_in), + .PIPERX09STATUS (PIPERX09STATUS_in), + .PIPERX09SYNCHEADER (PIPERX09SYNCHEADER_in), + .PIPERX09VALID (PIPERX09VALID_in), + .PIPERX10CHARISK (PIPERX10CHARISK_in), + .PIPERX10DATA (PIPERX10DATA_in), + .PIPERX10DATAVALID (PIPERX10DATAVALID_in), + .PIPERX10ELECIDLE (PIPERX10ELECIDLE_in), + .PIPERX10EQDONE (PIPERX10EQDONE_in), + .PIPERX10EQLPADAPTDONE (PIPERX10EQLPADAPTDONE_in), + .PIPERX10EQLPLFFSSEL (PIPERX10EQLPLFFSSEL_in), + .PIPERX10EQLPNEWTXCOEFFORPRESET (PIPERX10EQLPNEWTXCOEFFORPRESET_in), + .PIPERX10PHYSTATUS (PIPERX10PHYSTATUS_in), + .PIPERX10STARTBLOCK (PIPERX10STARTBLOCK_in), + .PIPERX10STATUS (PIPERX10STATUS_in), + .PIPERX10SYNCHEADER (PIPERX10SYNCHEADER_in), + .PIPERX10VALID (PIPERX10VALID_in), + .PIPERX11CHARISK (PIPERX11CHARISK_in), + .PIPERX11DATA (PIPERX11DATA_in), + .PIPERX11DATAVALID (PIPERX11DATAVALID_in), + .PIPERX11ELECIDLE (PIPERX11ELECIDLE_in), + .PIPERX11EQDONE (PIPERX11EQDONE_in), + .PIPERX11EQLPADAPTDONE (PIPERX11EQLPADAPTDONE_in), + .PIPERX11EQLPLFFSSEL (PIPERX11EQLPLFFSSEL_in), + .PIPERX11EQLPNEWTXCOEFFORPRESET (PIPERX11EQLPNEWTXCOEFFORPRESET_in), + .PIPERX11PHYSTATUS (PIPERX11PHYSTATUS_in), + .PIPERX11STARTBLOCK (PIPERX11STARTBLOCK_in), + .PIPERX11STATUS (PIPERX11STATUS_in), + .PIPERX11SYNCHEADER (PIPERX11SYNCHEADER_in), + .PIPERX11VALID (PIPERX11VALID_in), + .PIPERX12CHARISK (PIPERX12CHARISK_in), + .PIPERX12DATA (PIPERX12DATA_in), + .PIPERX12DATAVALID (PIPERX12DATAVALID_in), + .PIPERX12ELECIDLE (PIPERX12ELECIDLE_in), + .PIPERX12EQDONE (PIPERX12EQDONE_in), + .PIPERX12EQLPADAPTDONE (PIPERX12EQLPADAPTDONE_in), + .PIPERX12EQLPLFFSSEL (PIPERX12EQLPLFFSSEL_in), + .PIPERX12EQLPNEWTXCOEFFORPRESET (PIPERX12EQLPNEWTXCOEFFORPRESET_in), + .PIPERX12PHYSTATUS (PIPERX12PHYSTATUS_in), + .PIPERX12STARTBLOCK (PIPERX12STARTBLOCK_in), + .PIPERX12STATUS (PIPERX12STATUS_in), + .PIPERX12SYNCHEADER (PIPERX12SYNCHEADER_in), + .PIPERX12VALID (PIPERX12VALID_in), + .PIPERX13CHARISK (PIPERX13CHARISK_in), + .PIPERX13DATA (PIPERX13DATA_in), + .PIPERX13DATAVALID (PIPERX13DATAVALID_in), + .PIPERX13ELECIDLE (PIPERX13ELECIDLE_in), + .PIPERX13EQDONE (PIPERX13EQDONE_in), + .PIPERX13EQLPADAPTDONE (PIPERX13EQLPADAPTDONE_in), + .PIPERX13EQLPLFFSSEL (PIPERX13EQLPLFFSSEL_in), + .PIPERX13EQLPNEWTXCOEFFORPRESET (PIPERX13EQLPNEWTXCOEFFORPRESET_in), + .PIPERX13PHYSTATUS (PIPERX13PHYSTATUS_in), + .PIPERX13STARTBLOCK (PIPERX13STARTBLOCK_in), + .PIPERX13STATUS (PIPERX13STATUS_in), + .PIPERX13SYNCHEADER (PIPERX13SYNCHEADER_in), + .PIPERX13VALID (PIPERX13VALID_in), + .PIPERX14CHARISK (PIPERX14CHARISK_in), + .PIPERX14DATA (PIPERX14DATA_in), + .PIPERX14DATAVALID (PIPERX14DATAVALID_in), + .PIPERX14ELECIDLE (PIPERX14ELECIDLE_in), + .PIPERX14EQDONE (PIPERX14EQDONE_in), + .PIPERX14EQLPADAPTDONE (PIPERX14EQLPADAPTDONE_in), + .PIPERX14EQLPLFFSSEL (PIPERX14EQLPLFFSSEL_in), + .PIPERX14EQLPNEWTXCOEFFORPRESET (PIPERX14EQLPNEWTXCOEFFORPRESET_in), + .PIPERX14PHYSTATUS (PIPERX14PHYSTATUS_in), + .PIPERX14STARTBLOCK (PIPERX14STARTBLOCK_in), + .PIPERX14STATUS (PIPERX14STATUS_in), + .PIPERX14SYNCHEADER (PIPERX14SYNCHEADER_in), + .PIPERX14VALID (PIPERX14VALID_in), + .PIPERX15CHARISK (PIPERX15CHARISK_in), + .PIPERX15DATA (PIPERX15DATA_in), + .PIPERX15DATAVALID (PIPERX15DATAVALID_in), + .PIPERX15ELECIDLE (PIPERX15ELECIDLE_in), + .PIPERX15EQDONE (PIPERX15EQDONE_in), + .PIPERX15EQLPADAPTDONE (PIPERX15EQLPADAPTDONE_in), + .PIPERX15EQLPLFFSSEL (PIPERX15EQLPLFFSSEL_in), + .PIPERX15EQLPNEWTXCOEFFORPRESET (PIPERX15EQLPNEWTXCOEFFORPRESET_in), + .PIPERX15PHYSTATUS (PIPERX15PHYSTATUS_in), + .PIPERX15STARTBLOCK (PIPERX15STARTBLOCK_in), + .PIPERX15STATUS (PIPERX15STATUS_in), + .PIPERX15SYNCHEADER (PIPERX15SYNCHEADER_in), + .PIPERX15VALID (PIPERX15VALID_in), + .PIPETX00EQCOEFF (PIPETX00EQCOEFF_in), + .PIPETX00EQDONE (PIPETX00EQDONE_in), + .PIPETX01EQCOEFF (PIPETX01EQCOEFF_in), + .PIPETX01EQDONE (PIPETX01EQDONE_in), + .PIPETX02EQCOEFF (PIPETX02EQCOEFF_in), + .PIPETX02EQDONE (PIPETX02EQDONE_in), + .PIPETX03EQCOEFF (PIPETX03EQCOEFF_in), + .PIPETX03EQDONE (PIPETX03EQDONE_in), + .PIPETX04EQCOEFF (PIPETX04EQCOEFF_in), + .PIPETX04EQDONE (PIPETX04EQDONE_in), + .PIPETX05EQCOEFF (PIPETX05EQCOEFF_in), + .PIPETX05EQDONE (PIPETX05EQDONE_in), + .PIPETX06EQCOEFF (PIPETX06EQCOEFF_in), + .PIPETX06EQDONE (PIPETX06EQDONE_in), + .PIPETX07EQCOEFF (PIPETX07EQCOEFF_in), + .PIPETX07EQDONE (PIPETX07EQDONE_in), + .PIPETX08EQCOEFF (PIPETX08EQCOEFF_in), + .PIPETX08EQDONE (PIPETX08EQDONE_in), + .PIPETX09EQCOEFF (PIPETX09EQCOEFF_in), + .PIPETX09EQDONE (PIPETX09EQDONE_in), + .PIPETX10EQCOEFF (PIPETX10EQCOEFF_in), + .PIPETX10EQDONE (PIPETX10EQDONE_in), + .PIPETX11EQCOEFF (PIPETX11EQCOEFF_in), + .PIPETX11EQDONE (PIPETX11EQDONE_in), + .PIPETX12EQCOEFF (PIPETX12EQCOEFF_in), + .PIPETX12EQDONE (PIPETX12EQDONE_in), + .PIPETX13EQCOEFF (PIPETX13EQCOEFF_in), + .PIPETX13EQDONE (PIPETX13EQDONE_in), + .PIPETX14EQCOEFF (PIPETX14EQCOEFF_in), + .PIPETX14EQDONE (PIPETX14EQDONE_in), + .PIPETX15EQCOEFF (PIPETX15EQCOEFF_in), + .PIPETX15EQDONE (PIPETX15EQDONE_in), + .PLEQRESETEIEOSCOUNT (PLEQRESETEIEOSCOUNT_in), + .PLGEN2UPSTREAMPREFERDEEMPH (PLGEN2UPSTREAMPREFERDEEMPH_in), + .PLGEN34REDOEQSPEED (PLGEN34REDOEQSPEED_in), + .PLGEN34REDOEQUALIZATION (PLGEN34REDOEQUALIZATION_in), + .PMVDIVIDE (PMVDIVIDE_in), + .PMVENABLEN (PMVENABLEN_in), + .PMVSELECT (PMVSELECT_in), + .RESETN (RESETN_in), + .SAXISCCTDATA (SAXISCCTDATA_in), + .SAXISCCTKEEP (SAXISCCTKEEP_in), + .SAXISCCTLAST (SAXISCCTLAST_in), + .SAXISCCTUSER (SAXISCCTUSER_in), + .SAXISCCTVALID (SAXISCCTVALID_in), + .SAXISRQTDATA (SAXISRQTDATA_in), + .SAXISRQTKEEP (SAXISRQTKEEP_in), + .SAXISRQTLAST (SAXISRQTLAST_in), + .SAXISRQTUSER (SAXISRQTUSER_in), + .SAXISRQTVALID (SAXISRQTVALID_in), + .SCANENABLEN (SCANENABLEN_in), + .SCANIN (SCANIN_in), + .SCANMODEN (SCANMODEN_in), + .USERCLK (USERCLK_in), + .USERCLK2 (USERCLK2_in), + .USERCLKEN (USERCLKEN_in), + .USERSPAREIN (USERSPAREIN_in), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (CORECLK => AXIUSEROUT[0]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[1]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[2]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[3]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[4]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[5]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[6]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGCURRENTSPEED[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGCURRENTSPEED[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGERRCOROUT) = (100:100:100, 100:100:100); + (CORECLK => CFGERRFATALOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGERRNONFATALOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREADRECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITERECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGHOTRESETOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIFAIL) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMASKUPDATE) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSISENT) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXVECPENDINGSTATUS) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTSENT) = (100:100:100, 100:100:100); + (CORECLK => CFGLINKPOWERSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLINKPOWERSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERRORVALID) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXPAYLOAD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXPAYLOAD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADWRITEDONE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGTRANSMITDONE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMREADENABLE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKDOWN) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGPLSTATUSCHANGE) = (100:100:100, 100:100:100); + (CORECLK => CFGPOWERSTATECHANGEINTERRUPT) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGRXPMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGRXPMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMREADENABLE) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTXPMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTXPMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPDESIGNSWITCH) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPEOS) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPINUSEBYPCIE) = (100:100:100, 100:100:100); + (CORECLK => CONFREQREADY) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPVALID) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[100]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[101]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[102]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[103]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[104]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[105]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[106]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[107]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[108]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[109]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[110]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[111]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[112]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[113]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[114]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[115]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[116]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[117]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[118]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[119]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[120]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[121]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[122]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[123]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[124]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[125]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[126]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[127]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[128]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[129]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[130]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[131]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[132]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[133]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[134]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[135]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[136]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[137]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[138]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[139]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[140]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[141]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[142]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[143]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[144]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[145]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[146]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[147]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[148]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[149]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[150]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[151]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[152]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[153]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[154]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[155]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[156]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[157]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[158]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[159]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[160]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[161]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[162]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[163]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[164]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[165]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[166]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[167]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[168]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[169]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[170]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[171]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[172]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[173]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[174]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[175]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[176]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[177]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[178]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[179]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[180]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[181]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[182]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[183]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[184]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[185]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[186]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[187]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[188]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[189]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[190]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[191]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[192]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[193]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[194]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[195]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[196]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[197]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[198]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[199]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[200]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[201]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[202]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[203]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[204]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[205]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[206]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[207]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[208]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[209]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[210]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[211]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[212]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[213]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[214]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[215]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[216]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[217]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[218]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[219]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[220]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[221]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[222]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[223]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[224]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[225]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[226]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[227]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[228]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[229]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[230]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[231]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[232]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[233]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[234]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[235]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[236]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[237]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[238]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[239]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[240]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[241]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[242]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[243]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[244]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[245]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[246]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[247]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[248]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[249]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[250]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[251]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[252]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[253]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[254]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[255]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[32]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[33]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[34]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[35]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[36]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[37]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[38]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[39]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[40]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[41]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[42]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[43]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[44]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[45]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[46]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[47]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[48]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[49]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[50]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[51]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[52]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[53]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[54]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[55]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[56]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[57]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[58]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[59]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[60]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[61]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[62]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[63]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[64]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[65]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[66]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[67]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[68]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[69]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[70]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[71]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[72]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[73]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[74]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[75]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[76]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[77]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[78]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[79]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[80]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[81]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[82]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[83]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[84]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[85]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[86]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[87]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[88]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[89]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[90]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[91]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[92]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[93]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[94]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[95]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[96]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[97]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[98]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[99]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[100]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[101]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[102]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[103]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[104]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[105]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[106]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[107]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[108]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[109]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[110]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[111]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[112]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[113]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[114]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[115]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[116]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[117]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[118]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[119]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[120]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[121]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[122]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[123]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[124]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[125]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[126]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[127]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[128]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[129]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[130]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[131]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[132]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[133]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[134]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[135]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[136]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[137]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[138]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[139]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[140]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[141]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[142]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[143]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[144]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[145]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[146]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[147]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[148]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[149]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[150]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[151]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[152]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[153]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[154]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[155]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[156]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[157]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[158]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[159]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[160]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[161]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[162]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[163]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[164]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[165]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[166]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[167]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[168]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[169]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[170]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[171]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[172]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[173]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[174]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[175]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[176]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[177]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[178]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[179]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[180]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[181]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[182]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[183]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[184]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[185]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[186]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[187]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[188]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[189]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[190]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[191]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[192]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[193]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[194]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[195]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[196]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[197]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[198]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[199]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[200]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[201]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[202]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[203]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[204]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[205]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[206]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[207]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[208]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[209]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[210]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[211]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[212]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[213]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[214]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[215]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[216]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[217]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[218]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[219]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[220]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[221]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[222]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[223]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[224]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[225]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[226]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[227]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[228]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[229]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[230]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[231]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[232]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[233]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[234]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[235]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[236]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[237]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[238]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[239]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[240]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[241]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[242]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[243]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[244]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[245]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[246]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[247]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[248]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[249]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[250]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[251]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[252]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[253]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[254]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[255]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[32]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[33]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[34]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[35]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[36]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[37]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[38]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[39]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[40]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[41]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[42]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[43]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[44]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[45]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[46]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[47]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[48]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[49]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[50]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[51]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[52]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[53]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[54]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[55]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[56]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[57]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[58]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[59]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[60]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[61]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[62]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[63]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[64]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[65]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[66]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[67]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[68]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[69]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[70]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[71]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[72]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[73]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[74]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[75]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[76]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[77]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[78]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[79]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[80]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[81]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[82]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[83]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[84]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[85]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[86]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[87]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[88]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[89]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[90]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[91]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[92]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[93]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[94]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[95]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[96]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[97]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[98]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[99]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[100]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[101]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[102]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[103]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[104]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[105]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[106]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[107]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[108]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[109]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[110]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[111]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[112]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[113]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[114]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[115]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[116]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[117]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[118]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[119]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[120]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[121]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[122]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[123]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[124]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[125]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[126]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[127]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[128]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[129]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[130]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[131]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[132]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[133]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[134]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[135]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[136]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[137]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[138]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[139]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[140]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[141]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[142]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[143]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[144]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[145]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[146]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[147]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[148]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[149]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[150]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[151]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[152]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[153]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[154]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[155]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[156]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[157]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[158]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[159]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[160]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[161]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[162]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[163]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[164]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[165]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[166]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[167]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[168]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[169]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[170]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[171]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[172]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[173]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[174]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[175]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[176]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[177]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[178]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[179]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[180]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[181]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[182]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[183]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[184]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[185]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[186]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[187]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[188]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[189]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[190]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[191]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[192]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[193]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[194]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[195]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[196]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[197]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[198]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[199]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[200]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[201]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[202]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[203]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[204]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[205]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[206]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[207]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[208]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[209]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[210]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[211]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[212]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[213]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[214]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[215]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[216]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[217]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[218]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[219]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[220]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[221]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[222]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[223]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[224]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[225]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[226]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[227]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[228]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[229]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[230]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[231]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[232]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[233]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[234]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[235]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[236]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[237]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[238]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[239]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[240]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[241]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[242]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[243]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[244]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[245]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[246]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[247]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[248]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[249]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[250]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[251]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[252]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[253]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[254]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[255]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[88]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[89]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[90]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[91]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[92]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[93]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[94]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[95]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[96]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[97]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[98]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[99]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTLAST) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTVALID) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[100]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[101]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[102]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[103]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[104]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[105]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[106]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[107]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[108]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[109]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[110]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[111]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[112]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[113]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[114]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[115]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[116]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[117]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[118]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[119]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[120]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[121]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[122]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[123]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[124]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[125]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[126]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[127]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[128]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[129]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[130]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[131]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[132]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[133]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[134]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[135]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[136]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[137]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[138]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[139]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[140]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[141]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[142]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[143]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[144]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[145]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[146]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[147]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[148]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[149]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[150]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[151]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[152]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[153]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[154]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[155]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[156]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[157]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[158]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[159]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[160]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[161]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[162]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[163]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[164]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[165]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[166]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[167]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[168]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[169]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[170]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[171]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[172]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[173]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[174]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[175]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[176]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[177]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[178]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[179]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[180]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[181]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[182]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[183]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[184]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[185]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[186]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[187]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[188]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[189]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[190]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[191]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[192]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[193]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[194]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[195]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[196]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[197]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[198]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[199]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[200]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[201]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[202]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[203]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[204]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[205]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[206]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[207]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[208]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[209]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[210]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[211]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[212]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[213]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[214]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[215]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[216]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[217]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[218]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[219]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[220]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[221]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[222]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[223]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[224]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[225]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[226]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[227]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[228]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[229]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[230]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[231]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[232]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[233]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[234]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[235]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[236]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[237]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[238]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[239]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[240]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[241]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[242]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[243]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[244]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[245]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[246]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[247]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[248]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[249]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[250]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[251]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[252]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[253]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[254]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[255]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[88]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[89]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[90]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[91]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[92]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[93]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[94]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[95]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[96]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[97]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[98]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[99]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTLAST) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTVALID) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUMVLD0) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUMVLD1) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[6]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[7]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[6]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[7]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGVLD0) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGVLD1) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[3]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[0]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[1]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[2]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[3]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[0]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[1]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[2]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[3]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[0]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[10]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[11]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[12]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[13]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[14]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[15]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[16]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[17]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[18]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[19]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[1]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[20]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[21]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[22]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[23]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[24]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[25]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[26]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[27]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[28]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[29]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[2]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[30]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[31]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[3]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[4]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[5]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[6]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[7]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[8]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[9]) = (100:100:100, 100:100:100); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMREADENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMREADENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADENABLE0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADENABLE0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEENABLE0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEENABLE0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADENABLE1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADENABLE1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEENABLE1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEENABLE1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEENABLE1) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXDEEMPH) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRATE[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRATE[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRCVRDET) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRESET) = (100:100:100, 100:100:100); + (PIPECLK => PLEQINPROGRESS) = (100:100:100, 100:100:100); + (PIPECLK => PLEQPHASE[0]) = (100:100:100, 100:100:100); + (PIPECLK => PLEQPHASE[1]) = (100:100:100, 100:100:100); + (PIPECLK => PLGEN34EQMISMATCH) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CORECLK, 0:0:0, notifier); + $period (negedge CORECLKMIREPLAYRAM0, 0:0:0, notifier); + $period (negedge CORECLKMIREPLAYRAM1, 0:0:0, notifier); + $period (negedge CORECLKMIRXCOMPLETIONRAM0, 0:0:0, notifier); + $period (negedge CORECLKMIRXCOMPLETIONRAM1, 0:0:0, notifier); + $period (negedge CORECLKMIRXPOSTEDREQUESTRAM0, 0:0:0, notifier); + $period (negedge CORECLKMIRXPOSTEDREQUESTRAM1, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge MCAPCLK, 0:0:0, notifier); + $period (negedge PIPECLK, 0:0:0, notifier); + $period (posedge CORECLK, 0:0:0, notifier); + $period (posedge CORECLKMIREPLAYRAM0, 0:0:0, notifier); + $period (posedge CORECLKMIREPLAYRAM1, 0:0:0, notifier); + $period (posedge CORECLKMIRXCOMPLETIONRAM0, 0:0:0, notifier); + $period (posedge CORECLKMIRXCOMPLETIONRAM1, 0:0:0, notifier); + $period (posedge CORECLKMIRXPOSTEDREQUESTRAM0, 0:0:0, notifier); + $period (posedge CORECLKMIRXPOSTEDREQUESTRAM1, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge MCAPCLK, 0:0:0, notifier); + $period (posedge PIPECLK, 0:0:0, notifier); + $setuphold (posedge CORECLK, negedge AXIUSERIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[0]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[1]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[2]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[3]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[4]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[5]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[6]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[7]); + $setuphold (posedge CORECLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[16]); + $setuphold (posedge CORECLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[17]); + $setuphold (posedge CORECLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[18]); + $setuphold (posedge CORECLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[19]); + $setuphold (posedge CORECLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[20]); + $setuphold (posedge CORECLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[21]); + $setuphold (posedge CORECLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[22]); + $setuphold (posedge CORECLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[23]); + $setuphold (posedge CORECLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[24]); + $setuphold (posedge CORECLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[25]); + $setuphold (posedge CORECLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[26]); + $setuphold (posedge CORECLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[27]); + $setuphold (posedge CORECLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[28]); + $setuphold (posedge CORECLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[29]); + $setuphold (posedge CORECLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[30]); + $setuphold (posedge CORECLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[31]); + $setuphold (posedge CORECLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[32]); + $setuphold (posedge CORECLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[33]); + $setuphold (posedge CORECLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[34]); + $setuphold (posedge CORECLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[35]); + $setuphold (posedge CORECLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[36]); + $setuphold (posedge CORECLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[37]); + $setuphold (posedge CORECLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[38]); + $setuphold (posedge CORECLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[39]); + $setuphold (posedge CORECLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[40]); + $setuphold (posedge CORECLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[41]); + $setuphold (posedge CORECLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[42]); + $setuphold (posedge CORECLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[43]); + $setuphold (posedge CORECLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[44]); + $setuphold (posedge CORECLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[45]); + $setuphold (posedge CORECLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[46]); + $setuphold (posedge CORECLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[47]); + $setuphold (posedge CORECLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[48]); + $setuphold (posedge CORECLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[49]); + $setuphold (posedge CORECLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[50]); + $setuphold (posedge CORECLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[51]); + $setuphold (posedge CORECLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[52]); + $setuphold (posedge CORECLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[53]); + $setuphold (posedge CORECLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[54]); + $setuphold (posedge CORECLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[55]); + $setuphold (posedge CORECLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[56]); + $setuphold (posedge CORECLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[57]); + $setuphold (posedge CORECLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[58]); + $setuphold (posedge CORECLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[59]); + $setuphold (posedge CORECLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[60]); + $setuphold (posedge CORECLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[61]); + $setuphold (posedge CORECLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[62]); + $setuphold (posedge CORECLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[63]); + $setuphold (posedge CORECLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRCORIN_delay); + $setuphold (posedge CORECLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[3]); + $setuphold (posedge CORECLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXVECPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXVECPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[3]); + $setuphold (posedge CORECLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTDEBUGACCESS, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTDEBUGACCESS_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGPMASPML1ENTRYREJECT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPML1ENTRYREJECT_delay); + $setuphold (posedge CORECLK, negedge CFGPMASPMTXL0SENTRYDISABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPMTXL0SENTRYDISABLE_delay); + $setuphold (posedge CORECLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge CORECLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge CORECLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge CORECLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge CORECLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge CORECLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge CORECLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge CORECLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge CORECLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge CORECLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge CORECLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge CORECLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge CORECLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge CORECLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge CORECLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge CORECLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge CORECLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge CORECLK, negedge CFGVFFLRDONE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRDONE_delay); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[2]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[3]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[4]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[5]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[6]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[7]); + $setuphold (posedge CORECLK, negedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge CORECLK, negedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge CORECLK, negedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQVALID_delay); + $setuphold (posedge CORECLK, negedge DBGSEL0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[0]); + $setuphold (posedge CORECLK, negedge DBGSEL0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[1]); + $setuphold (posedge CORECLK, negedge DBGSEL0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[2]); + $setuphold (posedge CORECLK, negedge DBGSEL0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[3]); + $setuphold (posedge CORECLK, negedge DBGSEL0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[4]); + $setuphold (posedge CORECLK, negedge DBGSEL0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[5]); + $setuphold (posedge CORECLK, negedge DBGSEL1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[0]); + $setuphold (posedge CORECLK, negedge DBGSEL1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[1]); + $setuphold (posedge CORECLK, negedge DBGSEL1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[2]); + $setuphold (posedge CORECLK, negedge DBGSEL1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[3]); + $setuphold (posedge CORECLK, negedge DBGSEL1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[4]); + $setuphold (posedge CORECLK, negedge DBGSEL1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[2]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[3]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[4]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[5]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[6]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[7]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[2]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[3]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[4]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[5]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[6]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[7]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVERED[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVERED[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECQNPREQ[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPREQ_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECQNPUSERCREDITRCVD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPUSERCREDITRCVD_delay); + $setuphold (posedge CORECLK, negedge PCIECQPIPELINEEMPTY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQPIPELINEEMPTY_delay); + $setuphold (posedge CORECLK, negedge PCIEPOSTEDREQDELIVERED, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIEPOSTEDREQDELIVERED_delay); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTVALID_delay); + $setuphold (posedge CORECLK, negedge USERCLKEN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERCLKEN_delay); + $setuphold (posedge CORECLK, negedge USERSPAREIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[0]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[10]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[11]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[12]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[13]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[14]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[15]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[16]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[17]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[18]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[19]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[1]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[20]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[21]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[22]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[23]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[24]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[25]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[26]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[27]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[28]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[29]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[2]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[30]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[31]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[3]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[4]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[5]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[6]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[7]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[8]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[9]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[0]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[1]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[2]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[3]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[4]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[5]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[6]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[7]); + $setuphold (posedge CORECLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[16]); + $setuphold (posedge CORECLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[17]); + $setuphold (posedge CORECLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[18]); + $setuphold (posedge CORECLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[19]); + $setuphold (posedge CORECLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[20]); + $setuphold (posedge CORECLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[21]); + $setuphold (posedge CORECLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[22]); + $setuphold (posedge CORECLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[23]); + $setuphold (posedge CORECLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[24]); + $setuphold (posedge CORECLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[25]); + $setuphold (posedge CORECLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[26]); + $setuphold (posedge CORECLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[27]); + $setuphold (posedge CORECLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[28]); + $setuphold (posedge CORECLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[29]); + $setuphold (posedge CORECLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[30]); + $setuphold (posedge CORECLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[31]); + $setuphold (posedge CORECLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[32]); + $setuphold (posedge CORECLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[33]); + $setuphold (posedge CORECLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[34]); + $setuphold (posedge CORECLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[35]); + $setuphold (posedge CORECLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[36]); + $setuphold (posedge CORECLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[37]); + $setuphold (posedge CORECLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[38]); + $setuphold (posedge CORECLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[39]); + $setuphold (posedge CORECLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[40]); + $setuphold (posedge CORECLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[41]); + $setuphold (posedge CORECLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[42]); + $setuphold (posedge CORECLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[43]); + $setuphold (posedge CORECLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[44]); + $setuphold (posedge CORECLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[45]); + $setuphold (posedge CORECLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[46]); + $setuphold (posedge CORECLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[47]); + $setuphold (posedge CORECLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[48]); + $setuphold (posedge CORECLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[49]); + $setuphold (posedge CORECLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[50]); + $setuphold (posedge CORECLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[51]); + $setuphold (posedge CORECLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[52]); + $setuphold (posedge CORECLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[53]); + $setuphold (posedge CORECLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[54]); + $setuphold (posedge CORECLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[55]); + $setuphold (posedge CORECLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[56]); + $setuphold (posedge CORECLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[57]); + $setuphold (posedge CORECLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[58]); + $setuphold (posedge CORECLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[59]); + $setuphold (posedge CORECLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[60]); + $setuphold (posedge CORECLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[61]); + $setuphold (posedge CORECLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[62]); + $setuphold (posedge CORECLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[63]); + $setuphold (posedge CORECLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRCORIN_delay); + $setuphold (posedge CORECLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[3]); + $setuphold (posedge CORECLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXVECPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXVECPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[3]); + $setuphold (posedge CORECLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTDEBUGACCESS, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTDEBUGACCESS_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGPMASPML1ENTRYREJECT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPML1ENTRYREJECT_delay); + $setuphold (posedge CORECLK, posedge CFGPMASPMTXL0SENTRYDISABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPMTXL0SENTRYDISABLE_delay); + $setuphold (posedge CORECLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge CORECLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge CORECLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge CORECLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge CORECLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge CORECLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge CORECLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge CORECLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge CORECLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge CORECLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge CORECLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge CORECLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge CORECLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge CORECLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge CORECLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge CORECLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge CORECLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge CORECLK, posedge CFGVFFLRDONE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRDONE_delay); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[2]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[3]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[4]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[5]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[6]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[7]); + $setuphold (posedge CORECLK, posedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge CORECLK, posedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge CORECLK, posedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQVALID_delay); + $setuphold (posedge CORECLK, posedge DBGSEL0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[0]); + $setuphold (posedge CORECLK, posedge DBGSEL0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[1]); + $setuphold (posedge CORECLK, posedge DBGSEL0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[2]); + $setuphold (posedge CORECLK, posedge DBGSEL0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[3]); + $setuphold (posedge CORECLK, posedge DBGSEL0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[4]); + $setuphold (posedge CORECLK, posedge DBGSEL0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[5]); + $setuphold (posedge CORECLK, posedge DBGSEL1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[0]); + $setuphold (posedge CORECLK, posedge DBGSEL1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[1]); + $setuphold (posedge CORECLK, posedge DBGSEL1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[2]); + $setuphold (posedge CORECLK, posedge DBGSEL1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[3]); + $setuphold (posedge CORECLK, posedge DBGSEL1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[4]); + $setuphold (posedge CORECLK, posedge DBGSEL1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[2]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[3]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[4]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[5]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[6]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[7]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[2]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[3]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[4]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[5]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[6]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[7]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVERED[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVERED[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECQNPREQ[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPREQ_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECQNPUSERCREDITRCVD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPUSERCREDITRCVD_delay); + $setuphold (posedge CORECLK, posedge PCIECQPIPELINEEMPTY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQPIPELINEEMPTY_delay); + $setuphold (posedge CORECLK, posedge PCIEPOSTEDREQDELIVERED, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIEPOSTEDREQDELIVERED_delay); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTVALID_delay); + $setuphold (posedge CORECLK, posedge USERCLKEN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERCLKEN_delay); + $setuphold (posedge CORECLK, posedge USERSPAREIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[0]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[10]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[11]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[12]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[13]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[14]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[15]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[16]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[17]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[18]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[19]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[1]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[20]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[21]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[22]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[23]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[24]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[25]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[26]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[27]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[28]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[29]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[2]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[30]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[31]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[3]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[4]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[5]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[6]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[7]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[8]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX00ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX00PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX01ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX01PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX02ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX02PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX03ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX03PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX04ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX04PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX05ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX05PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX06ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX06PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX07ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX07PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX08ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX08PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX09ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX09PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX10ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX10PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX11ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX11PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX12ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX12PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX13ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX13PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX14ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX14PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX15ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX15PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge PIPECLK, negedge PLGEN34REDOEQSPEED, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQSPEED_delay); + $setuphold (posedge PIPECLK, negedge PLGEN34REDOEQUALIZATION, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQUALIZATION_delay); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX00ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX00PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX01ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX01PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX02ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX02PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX03ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX03PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX04ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX04PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX05ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX05PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX06ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX06PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX07ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX07PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX08ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX08PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX09ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX09PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX10ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX10PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX11ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX11PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX12ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX12PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX13ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX13PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX14ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX14PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX15ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX15PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge PIPECLK, posedge PLGEN34REDOEQSPEED, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQSPEED_delay); + $setuphold (posedge PIPECLK, posedge PLGEN34REDOEQUALIZATION, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQUALIZATION_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PCIE4CE4.v b/verilog/src/unisims/PCIE4CE4.v new file mode 100644 index 0000000..e82d693 --- /dev/null +++ b/verilog/src/unisims/PCIE4CE4.v @@ -0,0 +1,26442 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / PCIE4CE4 +// /___/ /\ Filename : PCIE4CE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PCIE4CE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter ARI_CAP_ENABLE = "FALSE", + parameter AUTO_FLR_RESPONSE = "FALSE", + parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08, + parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08, + parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE", + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0, + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20, + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080, + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE", + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE", + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE", + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE", + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE", + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000, + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE", + parameter AXISTEN_IF_EXT_512 = "FALSE", + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE", + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE", + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE", + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE", + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE", + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE", + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_RC_STRADDLE = "FALSE", + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0, + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE", + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE", + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE", + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2, + parameter CCIX_DIRECT_ATTACH_MODE = "FALSE", + parameter CCIX_ENABLE = "FALSE", + parameter [15:0] CCIX_VENDOR_ID = 16'h0000, + parameter CFG_BYPASS_MODE_ENABLE = "FALSE", + parameter CRM_CORE_CLK_FREQ_500 = "TRUE", + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2, + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000, + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00, + parameter [3:0] DEBUG_CAR_SPARE = 4'h0, + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000, + parameter [15:0] DEBUG_LL_SPARE = 16'h0000, + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE", + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE", + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE", + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE", + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE", + parameter [15:0] DEBUG_PL_SPARE = 16'h0000, + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE", + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE", + parameter [15:0] DEBUG_TL_SPARE = 16'h0000, + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + parameter DSN_CAP_ENABLE = "FALSE", + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter HEADER_TYPE_OVERRIDE = "FALSE", + parameter IS_SWITCH_PORT = "FALSE", + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter [8:0] LL_ACK_TIMEOUT = 9'h000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE", + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE", + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0, + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE", + parameter LL_RX_TLP_PARITY_GEN = "TRUE", + parameter LL_TX_TLP_PARITY_CHK = "TRUE", + parameter [15:0] LL_USER_SPARE = 16'h0000, + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250, + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE", + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE", + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000, + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE", + parameter MCAP_ENABLE = "FALSE", + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE", + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000, + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE", + parameter [15:0] MCAP_VSEC_ID = 16'h0000, + parameter [11:0] MCAP_VSEC_LEN = 12'h02C, + parameter [3:0] MCAP_VSEC_REV = 4'h0, + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE", + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [3:0] PF0_ARI_CAP_VER = 4'h1, + parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000, + parameter PF0_ATS_CAP_ON = "FALSE", + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR0_CONTROL = 3'h4, + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF0_BAR1_CONTROL = 3'h0, + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR3_CONTROL = 3'h0, + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR5_CONTROL = 3'h0, + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF0_CLASS_CODE = 24'h000000, + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE", + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE", + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE", + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0, + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE", + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0, + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE", + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1, + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7, + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0, + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000, + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000, + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_LTR_CAP_VER = 4'h1, + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04, + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00, + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF0_PM_CAP_ID = 8'h01, + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00, + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE", + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE", + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3, + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE", + parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000, + parameter PF0_PRI_CAP_ON = "FALSE", + parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000, + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000, + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF0_TPHR_CAP_ENABLE = "FALSE", + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1, + parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0, + parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00, + parameter PF0_VC_CAP_ENABLE = "FALSE", + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_VC_CAP_VER = 4'h1, + parameter PF0_VC_EXTENDED_COUNT = "FALSE", + parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE", + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000, + parameter PF1_ATS_CAP_ON = "FALSE", + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR0_CONTROL = 3'h4, + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF1_BAR1_CONTROL = 3'h0, + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR3_CONTROL = 3'h0, + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR5_CONTROL = 3'h0, + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF1_CLASS_CODE = 24'h000000, + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00, + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00, + parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000, + parameter PF1_PRI_CAP_ON = "FALSE", + parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000, + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000, + parameter PF2_ATS_CAP_ON = "FALSE", + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR0_CONTROL = 3'h4, + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF2_BAR1_CONTROL = 3'h0, + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR3_CONTROL = 3'h0, + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR5_CONTROL = 3'h0, + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF2_CLASS_CODE = 24'h000000, + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00, + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00, + parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000, + parameter PF2_PRI_CAP_ON = "FALSE", + parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000, + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000, + parameter PF3_ATS_CAP_ON = "FALSE", + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR0_CONTROL = 3'h4, + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF3_BAR1_CONTROL = 3'h0, + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR3_CONTROL = 3'h0, + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR5_CONTROL = 3'h0, + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80, + parameter [23:0] PF3_CLASS_CODE = 24'h000000, + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE", + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00, + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00, + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00, + parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000, + parameter PF3_PRI_CAP_ON = "FALSE", + parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000, + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE", + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0, + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0, + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE", + parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE", + parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE", + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE", + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE", + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE", + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE", + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE", + parameter PL_DISABLE_DC_BALANCE = "FALSE", + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE", + parameter PL_DISABLE_LANE_REVERSAL = "FALSE", + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0, + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE", + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE", + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000, + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE", + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0, + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0, + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02, + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1, + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0, + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33, + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44, + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE", + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0, + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0, + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE", + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE", + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE", + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE", + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE", + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE", + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00, + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00, + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4, + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08, + parameter integer PL_N_FTS = 255, + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE", + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE", + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00, + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0, + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0, + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0, + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0, + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0, + parameter PL_SRIS_ENABLE = "FALSE", + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00, + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00, + parameter PL_UPSTREAM_FACING = "TRUE", + parameter [15:0] PL_USER_SPARE = 16'h0000, + parameter [15:0] PL_USER_SPARE2 = 16'h0000, + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500, + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8, + parameter PM_ENABLE_L23_ENTRY = "FALSE", + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE", + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100, + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000, + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000, + parameter SIM_VERSION = "1.0", + parameter SPARE_BIT0 = "FALSE", + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter SPARE_BIT3 = "FALSE", + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0, + parameter TL2CFG_IF_PARITY_CHK = "TRUE", + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0, + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1, + parameter [11:0] TL_CREDITS_CD = 12'h000, + parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000, + parameter [7:0] TL_CREDITS_CH = 8'h00, + parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00, + parameter [11:0] TL_CREDITS_NPD = 12'h004, + parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000, + parameter [7:0] TL_CREDITS_NPH = 8'h20, + parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01, + parameter [11:0] TL_CREDITS_PD = 12'h0E0, + parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0, + parameter [7:0] TL_CREDITS_PH = 8'h20, + parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08, + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08, + parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE", + parameter [1:0] TL_PF_ENABLE_REG = 2'h0, + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0, + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE", + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE", + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE", + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE", + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE", + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE", + parameter [15:0] TL_USER_SPARE = 16'h0000, + parameter TPH_FROM_RAM_PIPELINE = "FALSE", + parameter TPH_TO_RAM_PIPELINE = "FALSE", + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80, + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000, + parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000, + parameter VFG0_ATS_CAP_ON = "FALSE", + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000, + parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000, + parameter VFG1_ATS_CAP_ON = "FALSE", + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000, + parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000, + parameter VFG2_ATS_CAP_ON = "FALSE", + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000, + parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00, + parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000, + parameter VFG3_ATS_CAP_ON = "FALSE", + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00, + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0 +)( + output [7:0] AXIUSEROUT, + output CCIXTXCREDIT, + output [7:0] CFGBUSNUMBER, + output [1:0] CFGCURRENTSPEED, + output CFGERRCOROUT, + output CFGERRFATALOUT, + output CFGERRNONFATALOUT, + output [7:0] CFGEXTFUNCTIONNUMBER, + output CFGEXTREADRECEIVED, + output [9:0] CFGEXTREGISTERNUMBER, + output [3:0] CFGEXTWRITEBYTEENABLE, + output [31:0] CFGEXTWRITEDATA, + output CFGEXTWRITERECEIVED, + output [11:0] CFGFCCPLD, + output [7:0] CFGFCCPLH, + output [11:0] CFGFCNPD, + output [7:0] CFGFCNPH, + output [11:0] CFGFCPD, + output [7:0] CFGFCPH, + output [3:0] CFGFLRINPROCESS, + output [11:0] CFGFUNCTIONPOWERSTATE, + output [15:0] CFGFUNCTIONSTATUS, + output CFGHOTRESETOUT, + output [31:0] CFGINTERRUPTMSIDATA, + output [3:0] CFGINTERRUPTMSIENABLE, + output CFGINTERRUPTMSIFAIL, + output CFGINTERRUPTMSIMASKUPDATE, + output [11:0] CFGINTERRUPTMSIMMENABLE, + output CFGINTERRUPTMSISENT, + output [3:0] CFGINTERRUPTMSIXENABLE, + output [3:0] CFGINTERRUPTMSIXMASK, + output CFGINTERRUPTMSIXVECPENDINGSTATUS, + output CFGINTERRUPTSENT, + output [1:0] CFGLINKPOWERSTATE, + output [4:0] CFGLOCALERROROUT, + output CFGLOCALERRORVALID, + output CFGLTRENABLE, + output [5:0] CFGLTSSMSTATE, + output [1:0] CFGMAXPAYLOAD, + output [2:0] CFGMAXREADREQ, + output [31:0] CFGMGMTREADDATA, + output CFGMGMTREADWRITEDONE, + output CFGMSGRECEIVED, + output [7:0] CFGMSGRECEIVEDDATA, + output [4:0] CFGMSGRECEIVEDTYPE, + output CFGMSGTRANSMITDONE, + output [12:0] CFGMSIXRAMADDRESS, + output CFGMSIXRAMREADENABLE, + output [3:0] CFGMSIXRAMWRITEBYTEENABLE, + output [35:0] CFGMSIXRAMWRITEDATA, + output [2:0] CFGNEGOTIATEDWIDTH, + output [1:0] CFGOBFFENABLE, + output CFGPHYLINKDOWN, + output [1:0] CFGPHYLINKSTATUS, + output CFGPLSTATUSCHANGE, + output CFGPOWERSTATECHANGEINTERRUPT, + output [3:0] CFGRCBSTATUS, + output [1:0] CFGRXPMSTATE, + output [11:0] CFGTPHRAMADDRESS, + output CFGTPHRAMREADENABLE, + output [3:0] CFGTPHRAMWRITEBYTEENABLE, + output [35:0] CFGTPHRAMWRITEDATA, + output [3:0] CFGTPHREQUESTERENABLE, + output [11:0] CFGTPHSTMODE, + output [1:0] CFGTXPMSTATE, + output CFGVC1ENABLE, + output CFGVC1NEGOTIATIONPENDING, + output CONFMCAPDESIGNSWITCH, + output CONFMCAPEOS, + output CONFMCAPINUSEBYPCIE, + output CONFREQREADY, + output [31:0] CONFRESPRDATA, + output CONFRESPVALID, + output [129:0] DBGCCIXOUT, + output [31:0] DBGCTRL0OUT, + output [31:0] DBGCTRL1OUT, + output [255:0] DBGDATA0OUT, + output [255:0] DBGDATA1OUT, + output [15:0] DRPDO, + output DRPRDY, + output [45:0] MAXISCCIXRXTUSER, + output MAXISCCIXRXTVALID, + output [255:0] MAXISCQTDATA, + output [7:0] MAXISCQTKEEP, + output MAXISCQTLAST, + output [87:0] MAXISCQTUSER, + output MAXISCQTVALID, + output [255:0] MAXISRCTDATA, + output [7:0] MAXISRCTKEEP, + output MAXISRCTLAST, + output [74:0] MAXISRCTUSER, + output MAXISRCTVALID, + output [8:0] MIREPLAYRAMADDRESS0, + output [8:0] MIREPLAYRAMADDRESS1, + output MIREPLAYRAMREADENABLE0, + output MIREPLAYRAMREADENABLE1, + output [127:0] MIREPLAYRAMWRITEDATA0, + output [127:0] MIREPLAYRAMWRITEDATA1, + output MIREPLAYRAMWRITEENABLE0, + output MIREPLAYRAMWRITEENABLE1, + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0, + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1, + output [1:0] MIRXCOMPLETIONRAMREADENABLE0, + output [1:0] MIRXCOMPLETIONRAMREADENABLE1, + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0, + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1, + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0, + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1, + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0, + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1, + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0, + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1, + output MIRXPOSTEDREQUESTRAMREADENABLE0, + output MIRXPOSTEDREQUESTRAMREADENABLE1, + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0, + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1, + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0, + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1, + output MIRXPOSTEDREQUESTRAMWRITEENABLE0, + output MIRXPOSTEDREQUESTRAMWRITEENABLE1, + output [5:0] PCIECQNPREQCOUNT, + output PCIEPERST0B, + output PCIEPERST1B, + output [5:0] PCIERQSEQNUM0, + output [5:0] PCIERQSEQNUM1, + output PCIERQSEQNUMVLD0, + output PCIERQSEQNUMVLD1, + output [7:0] PCIERQTAG0, + output [7:0] PCIERQTAG1, + output [3:0] PCIERQTAGAV, + output PCIERQTAGVLD0, + output PCIERQTAGVLD1, + output [3:0] PCIETFCNPDAV, + output [3:0] PCIETFCNPHAV, + output [1:0] PIPERX00EQCONTROL, + output PIPERX00POLARITY, + output [1:0] PIPERX01EQCONTROL, + output PIPERX01POLARITY, + output [1:0] PIPERX02EQCONTROL, + output PIPERX02POLARITY, + output [1:0] PIPERX03EQCONTROL, + output PIPERX03POLARITY, + output [1:0] PIPERX04EQCONTROL, + output PIPERX04POLARITY, + output [1:0] PIPERX05EQCONTROL, + output PIPERX05POLARITY, + output [1:0] PIPERX06EQCONTROL, + output PIPERX06POLARITY, + output [1:0] PIPERX07EQCONTROL, + output PIPERX07POLARITY, + output [1:0] PIPERX08EQCONTROL, + output PIPERX08POLARITY, + output [1:0] PIPERX09EQCONTROL, + output PIPERX09POLARITY, + output [1:0] PIPERX10EQCONTROL, + output PIPERX10POLARITY, + output [1:0] PIPERX11EQCONTROL, + output PIPERX11POLARITY, + output [1:0] PIPERX12EQCONTROL, + output PIPERX12POLARITY, + output [1:0] PIPERX13EQCONTROL, + output PIPERX13POLARITY, + output [1:0] PIPERX14EQCONTROL, + output PIPERX14POLARITY, + output [1:0] PIPERX15EQCONTROL, + output PIPERX15POLARITY, + output [5:0] PIPERXEQLPLFFS, + output [3:0] PIPERXEQLPTXPRESET, + output [1:0] PIPETX00CHARISK, + output PIPETX00COMPLIANCE, + output [31:0] PIPETX00DATA, + output PIPETX00DATAVALID, + output PIPETX00ELECIDLE, + output [1:0] PIPETX00EQCONTROL, + output [5:0] PIPETX00EQDEEMPH, + output [1:0] PIPETX00POWERDOWN, + output PIPETX00STARTBLOCK, + output [1:0] PIPETX00SYNCHEADER, + output [1:0] PIPETX01CHARISK, + output PIPETX01COMPLIANCE, + output [31:0] PIPETX01DATA, + output PIPETX01DATAVALID, + output PIPETX01ELECIDLE, + output [1:0] PIPETX01EQCONTROL, + output [5:0] PIPETX01EQDEEMPH, + output [1:0] PIPETX01POWERDOWN, + output PIPETX01STARTBLOCK, + output [1:0] PIPETX01SYNCHEADER, + output [1:0] PIPETX02CHARISK, + output PIPETX02COMPLIANCE, + output [31:0] PIPETX02DATA, + output PIPETX02DATAVALID, + output PIPETX02ELECIDLE, + output [1:0] PIPETX02EQCONTROL, + output [5:0] PIPETX02EQDEEMPH, + output [1:0] PIPETX02POWERDOWN, + output PIPETX02STARTBLOCK, + output [1:0] PIPETX02SYNCHEADER, + output [1:0] PIPETX03CHARISK, + output PIPETX03COMPLIANCE, + output [31:0] PIPETX03DATA, + output PIPETX03DATAVALID, + output PIPETX03ELECIDLE, + output [1:0] PIPETX03EQCONTROL, + output [5:0] PIPETX03EQDEEMPH, + output [1:0] PIPETX03POWERDOWN, + output PIPETX03STARTBLOCK, + output [1:0] PIPETX03SYNCHEADER, + output [1:0] PIPETX04CHARISK, + output PIPETX04COMPLIANCE, + output [31:0] PIPETX04DATA, + output PIPETX04DATAVALID, + output PIPETX04ELECIDLE, + output [1:0] PIPETX04EQCONTROL, + output [5:0] PIPETX04EQDEEMPH, + output [1:0] PIPETX04POWERDOWN, + output PIPETX04STARTBLOCK, + output [1:0] PIPETX04SYNCHEADER, + output [1:0] PIPETX05CHARISK, + output PIPETX05COMPLIANCE, + output [31:0] PIPETX05DATA, + output PIPETX05DATAVALID, + output PIPETX05ELECIDLE, + output [1:0] PIPETX05EQCONTROL, + output [5:0] PIPETX05EQDEEMPH, + output [1:0] PIPETX05POWERDOWN, + output PIPETX05STARTBLOCK, + output [1:0] PIPETX05SYNCHEADER, + output [1:0] PIPETX06CHARISK, + output PIPETX06COMPLIANCE, + output [31:0] PIPETX06DATA, + output PIPETX06DATAVALID, + output PIPETX06ELECIDLE, + output [1:0] PIPETX06EQCONTROL, + output [5:0] PIPETX06EQDEEMPH, + output [1:0] PIPETX06POWERDOWN, + output PIPETX06STARTBLOCK, + output [1:0] PIPETX06SYNCHEADER, + output [1:0] PIPETX07CHARISK, + output PIPETX07COMPLIANCE, + output [31:0] PIPETX07DATA, + output PIPETX07DATAVALID, + output PIPETX07ELECIDLE, + output [1:0] PIPETX07EQCONTROL, + output [5:0] PIPETX07EQDEEMPH, + output [1:0] PIPETX07POWERDOWN, + output PIPETX07STARTBLOCK, + output [1:0] PIPETX07SYNCHEADER, + output [1:0] PIPETX08CHARISK, + output PIPETX08COMPLIANCE, + output [31:0] PIPETX08DATA, + output PIPETX08DATAVALID, + output PIPETX08ELECIDLE, + output [1:0] PIPETX08EQCONTROL, + output [5:0] PIPETX08EQDEEMPH, + output [1:0] PIPETX08POWERDOWN, + output PIPETX08STARTBLOCK, + output [1:0] PIPETX08SYNCHEADER, + output [1:0] PIPETX09CHARISK, + output PIPETX09COMPLIANCE, + output [31:0] PIPETX09DATA, + output PIPETX09DATAVALID, + output PIPETX09ELECIDLE, + output [1:0] PIPETX09EQCONTROL, + output [5:0] PIPETX09EQDEEMPH, + output [1:0] PIPETX09POWERDOWN, + output PIPETX09STARTBLOCK, + output [1:0] PIPETX09SYNCHEADER, + output [1:0] PIPETX10CHARISK, + output PIPETX10COMPLIANCE, + output [31:0] PIPETX10DATA, + output PIPETX10DATAVALID, + output PIPETX10ELECIDLE, + output [1:0] PIPETX10EQCONTROL, + output [5:0] PIPETX10EQDEEMPH, + output [1:0] PIPETX10POWERDOWN, + output PIPETX10STARTBLOCK, + output [1:0] PIPETX10SYNCHEADER, + output [1:0] PIPETX11CHARISK, + output PIPETX11COMPLIANCE, + output [31:0] PIPETX11DATA, + output PIPETX11DATAVALID, + output PIPETX11ELECIDLE, + output [1:0] PIPETX11EQCONTROL, + output [5:0] PIPETX11EQDEEMPH, + output [1:0] PIPETX11POWERDOWN, + output PIPETX11STARTBLOCK, + output [1:0] PIPETX11SYNCHEADER, + output [1:0] PIPETX12CHARISK, + output PIPETX12COMPLIANCE, + output [31:0] PIPETX12DATA, + output PIPETX12DATAVALID, + output PIPETX12ELECIDLE, + output [1:0] PIPETX12EQCONTROL, + output [5:0] PIPETX12EQDEEMPH, + output [1:0] PIPETX12POWERDOWN, + output PIPETX12STARTBLOCK, + output [1:0] PIPETX12SYNCHEADER, + output [1:0] PIPETX13CHARISK, + output PIPETX13COMPLIANCE, + output [31:0] PIPETX13DATA, + output PIPETX13DATAVALID, + output PIPETX13ELECIDLE, + output [1:0] PIPETX13EQCONTROL, + output [5:0] PIPETX13EQDEEMPH, + output [1:0] PIPETX13POWERDOWN, + output PIPETX13STARTBLOCK, + output [1:0] PIPETX13SYNCHEADER, + output [1:0] PIPETX14CHARISK, + output PIPETX14COMPLIANCE, + output [31:0] PIPETX14DATA, + output PIPETX14DATAVALID, + output PIPETX14ELECIDLE, + output [1:0] PIPETX14EQCONTROL, + output [5:0] PIPETX14EQDEEMPH, + output [1:0] PIPETX14POWERDOWN, + output PIPETX14STARTBLOCK, + output [1:0] PIPETX14SYNCHEADER, + output [1:0] PIPETX15CHARISK, + output PIPETX15COMPLIANCE, + output [31:0] PIPETX15DATA, + output PIPETX15DATAVALID, + output PIPETX15ELECIDLE, + output [1:0] PIPETX15EQCONTROL, + output [5:0] PIPETX15EQDEEMPH, + output [1:0] PIPETX15POWERDOWN, + output PIPETX15STARTBLOCK, + output [1:0] PIPETX15SYNCHEADER, + output PIPETXDEEMPH, + output [2:0] PIPETXMARGIN, + output [1:0] PIPETXRATE, + output PIPETXRCVRDET, + output PIPETXRESET, + output PIPETXSWING, + output PLEQINPROGRESS, + output [1:0] PLEQPHASE, + output PLGEN34EQMISMATCH, + output [3:0] SAXISCCTREADY, + output [3:0] SAXISRQTREADY, + output [23:0] USERSPAREOUT, + + input [7:0] AXIUSERIN, + input CCIXOPTIMIZEDTLPTXANDRXENABLE, + input CCIXRXCORRECTABLEERRORDETECTED, + input CCIXRXFIFOOVERFLOW, + input CCIXRXTLPFORWARDED0, + input CCIXRXTLPFORWARDED1, + input [5:0] CCIXRXTLPFORWARDEDLENGTH0, + input [5:0] CCIXRXTLPFORWARDEDLENGTH1, + input CCIXRXUNCORRECTABLEERRORDETECTED, + input CFGCONFIGSPACEENABLE, + input [15:0] CFGDEVIDPF0, + input [15:0] CFGDEVIDPF1, + input [15:0] CFGDEVIDPF2, + input [15:0] CFGDEVIDPF3, + input [7:0] CFGDSBUSNUMBER, + input [4:0] CFGDSDEVICENUMBER, + input [2:0] CFGDSFUNCTIONNUMBER, + input [63:0] CFGDSN, + input [7:0] CFGDSPORTNUMBER, + input CFGERRCORIN, + input CFGERRUNCORIN, + input [31:0] CFGEXTREADDATA, + input CFGEXTREADDATAVALID, + input [2:0] CFGFCSEL, + input CFGFCVCSEL, + input [3:0] CFGFLRDONE, + input CFGHOTRESETIN, + input [3:0] CFGINTERRUPTINT, + input [2:0] CFGINTERRUPTMSIATTR, + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER, + input [31:0] CFGINTERRUPTMSIINT, + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS, + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, + input [1:0] CFGINTERRUPTMSISELECT, + input CFGINTERRUPTMSITPHPRESENT, + input [7:0] CFGINTERRUPTMSITPHSTTAG, + input [1:0] CFGINTERRUPTMSITPHTYPE, + input [63:0] CFGINTERRUPTMSIXADDRESS, + input [31:0] CFGINTERRUPTMSIXDATA, + input CFGINTERRUPTMSIXINT, + input [1:0] CFGINTERRUPTMSIXVECPENDING, + input [3:0] CFGINTERRUPTPENDING, + input CFGLINKTRAININGENABLE, + input [9:0] CFGMGMTADDR, + input [3:0] CFGMGMTBYTEENABLE, + input CFGMGMTDEBUGACCESS, + input [7:0] CFGMGMTFUNCTIONNUMBER, + input CFGMGMTREAD, + input CFGMGMTWRITE, + input [31:0] CFGMGMTWRITEDATA, + input CFGMSGTRANSMIT, + input [31:0] CFGMSGTRANSMITDATA, + input [2:0] CFGMSGTRANSMITTYPE, + input [35:0] CFGMSIXRAMREADDATA, + input CFGPMASPML1ENTRYREJECT, + input CFGPMASPMTXL0SENTRYDISABLE, + input CFGPOWERSTATECHANGEACK, + input CFGREQPMTRANSITIONL23READY, + input [7:0] CFGREVIDPF0, + input [7:0] CFGREVIDPF1, + input [7:0] CFGREVIDPF2, + input [7:0] CFGREVIDPF3, + input [15:0] CFGSUBSYSIDPF0, + input [15:0] CFGSUBSYSIDPF1, + input [15:0] CFGSUBSYSIDPF2, + input [15:0] CFGSUBSYSIDPF3, + input [15:0] CFGSUBSYSVENDID, + input [35:0] CFGTPHRAMREADDATA, + input [15:0] CFGVENDID, + input CFGVFFLRDONE, + input [7:0] CFGVFFLRFUNCNUM, + input CONFMCAPREQUESTBYCONF, + input [31:0] CONFREQDATA, + input [3:0] CONFREQREGNUM, + input [1:0] CONFREQTYPE, + input CONFREQVALID, + input CORECLK, + input CORECLKCCIX, + input CORECLKMIREPLAYRAM0, + input CORECLKMIREPLAYRAM1, + input CORECLKMIRXCOMPLETIONRAM0, + input CORECLKMIRXCOMPLETIONRAM1, + input CORECLKMIRXPOSTEDREQUESTRAM0, + input CORECLKMIRXPOSTEDREQUESTRAM1, + input [5:0] DBGSEL0, + input [5:0] DBGSEL1, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input [21:0] MAXISCQTREADY, + input [21:0] MAXISRCTREADY, + input MCAPCLK, + input MCAPPERST0B, + input MCAPPERST1B, + input MGMTRESETN, + input MGMTSTICKYRESETN, + input [5:0] MIREPLAYRAMERRCOR, + input [5:0] MIREPLAYRAMERRUNCOR, + input [127:0] MIREPLAYRAMREADDATA0, + input [127:0] MIREPLAYRAMREADDATA1, + input [11:0] MIRXCOMPLETIONRAMERRCOR, + input [11:0] MIRXCOMPLETIONRAMERRUNCOR, + input [143:0] MIRXCOMPLETIONRAMREADDATA0, + input [143:0] MIRXCOMPLETIONRAMREADDATA1, + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR, + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR, + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0, + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1, + input [1:0] PCIECOMPLDELIVERED, + input [7:0] PCIECOMPLDELIVEREDTAG0, + input [7:0] PCIECOMPLDELIVEREDTAG1, + input [1:0] PCIECQNPREQ, + input PCIECQNPUSERCREDITRCVD, + input PCIECQPIPELINEEMPTY, + input PCIEPOSTEDREQDELIVERED, + input PIPECLK, + input PIPECLKEN, + input [5:0] PIPEEQFS, + input [5:0] PIPEEQLF, + input PIPERESETN, + input [1:0] PIPERX00CHARISK, + input [31:0] PIPERX00DATA, + input PIPERX00DATAVALID, + input PIPERX00ELECIDLE, + input PIPERX00EQDONE, + input PIPERX00EQLPADAPTDONE, + input PIPERX00EQLPLFFSSEL, + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET, + input PIPERX00PHYSTATUS, + input [1:0] PIPERX00STARTBLOCK, + input [2:0] PIPERX00STATUS, + input [1:0] PIPERX00SYNCHEADER, + input PIPERX00VALID, + input [1:0] PIPERX01CHARISK, + input [31:0] PIPERX01DATA, + input PIPERX01DATAVALID, + input PIPERX01ELECIDLE, + input PIPERX01EQDONE, + input PIPERX01EQLPADAPTDONE, + input PIPERX01EQLPLFFSSEL, + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET, + input PIPERX01PHYSTATUS, + input [1:0] PIPERX01STARTBLOCK, + input [2:0] PIPERX01STATUS, + input [1:0] PIPERX01SYNCHEADER, + input PIPERX01VALID, + input [1:0] PIPERX02CHARISK, + input [31:0] PIPERX02DATA, + input PIPERX02DATAVALID, + input PIPERX02ELECIDLE, + input PIPERX02EQDONE, + input PIPERX02EQLPADAPTDONE, + input PIPERX02EQLPLFFSSEL, + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET, + input PIPERX02PHYSTATUS, + input [1:0] PIPERX02STARTBLOCK, + input [2:0] PIPERX02STATUS, + input [1:0] PIPERX02SYNCHEADER, + input PIPERX02VALID, + input [1:0] PIPERX03CHARISK, + input [31:0] PIPERX03DATA, + input PIPERX03DATAVALID, + input PIPERX03ELECIDLE, + input PIPERX03EQDONE, + input PIPERX03EQLPADAPTDONE, + input PIPERX03EQLPLFFSSEL, + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET, + input PIPERX03PHYSTATUS, + input [1:0] PIPERX03STARTBLOCK, + input [2:0] PIPERX03STATUS, + input [1:0] PIPERX03SYNCHEADER, + input PIPERX03VALID, + input [1:0] PIPERX04CHARISK, + input [31:0] PIPERX04DATA, + input PIPERX04DATAVALID, + input PIPERX04ELECIDLE, + input PIPERX04EQDONE, + input PIPERX04EQLPADAPTDONE, + input PIPERX04EQLPLFFSSEL, + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET, + input PIPERX04PHYSTATUS, + input [1:0] PIPERX04STARTBLOCK, + input [2:0] PIPERX04STATUS, + input [1:0] PIPERX04SYNCHEADER, + input PIPERX04VALID, + input [1:0] PIPERX05CHARISK, + input [31:0] PIPERX05DATA, + input PIPERX05DATAVALID, + input PIPERX05ELECIDLE, + input PIPERX05EQDONE, + input PIPERX05EQLPADAPTDONE, + input PIPERX05EQLPLFFSSEL, + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET, + input PIPERX05PHYSTATUS, + input [1:0] PIPERX05STARTBLOCK, + input [2:0] PIPERX05STATUS, + input [1:0] PIPERX05SYNCHEADER, + input PIPERX05VALID, + input [1:0] PIPERX06CHARISK, + input [31:0] PIPERX06DATA, + input PIPERX06DATAVALID, + input PIPERX06ELECIDLE, + input PIPERX06EQDONE, + input PIPERX06EQLPADAPTDONE, + input PIPERX06EQLPLFFSSEL, + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET, + input PIPERX06PHYSTATUS, + input [1:0] PIPERX06STARTBLOCK, + input [2:0] PIPERX06STATUS, + input [1:0] PIPERX06SYNCHEADER, + input PIPERX06VALID, + input [1:0] PIPERX07CHARISK, + input [31:0] PIPERX07DATA, + input PIPERX07DATAVALID, + input PIPERX07ELECIDLE, + input PIPERX07EQDONE, + input PIPERX07EQLPADAPTDONE, + input PIPERX07EQLPLFFSSEL, + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET, + input PIPERX07PHYSTATUS, + input [1:0] PIPERX07STARTBLOCK, + input [2:0] PIPERX07STATUS, + input [1:0] PIPERX07SYNCHEADER, + input PIPERX07VALID, + input [1:0] PIPERX08CHARISK, + input [31:0] PIPERX08DATA, + input PIPERX08DATAVALID, + input PIPERX08ELECIDLE, + input PIPERX08EQDONE, + input PIPERX08EQLPADAPTDONE, + input PIPERX08EQLPLFFSSEL, + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET, + input PIPERX08PHYSTATUS, + input [1:0] PIPERX08STARTBLOCK, + input [2:0] PIPERX08STATUS, + input [1:0] PIPERX08SYNCHEADER, + input PIPERX08VALID, + input [1:0] PIPERX09CHARISK, + input [31:0] PIPERX09DATA, + input PIPERX09DATAVALID, + input PIPERX09ELECIDLE, + input PIPERX09EQDONE, + input PIPERX09EQLPADAPTDONE, + input PIPERX09EQLPLFFSSEL, + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET, + input PIPERX09PHYSTATUS, + input [1:0] PIPERX09STARTBLOCK, + input [2:0] PIPERX09STATUS, + input [1:0] PIPERX09SYNCHEADER, + input PIPERX09VALID, + input [1:0] PIPERX10CHARISK, + input [31:0] PIPERX10DATA, + input PIPERX10DATAVALID, + input PIPERX10ELECIDLE, + input PIPERX10EQDONE, + input PIPERX10EQLPADAPTDONE, + input PIPERX10EQLPLFFSSEL, + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET, + input PIPERX10PHYSTATUS, + input [1:0] PIPERX10STARTBLOCK, + input [2:0] PIPERX10STATUS, + input [1:0] PIPERX10SYNCHEADER, + input PIPERX10VALID, + input [1:0] PIPERX11CHARISK, + input [31:0] PIPERX11DATA, + input PIPERX11DATAVALID, + input PIPERX11ELECIDLE, + input PIPERX11EQDONE, + input PIPERX11EQLPADAPTDONE, + input PIPERX11EQLPLFFSSEL, + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET, + input PIPERX11PHYSTATUS, + input [1:0] PIPERX11STARTBLOCK, + input [2:0] PIPERX11STATUS, + input [1:0] PIPERX11SYNCHEADER, + input PIPERX11VALID, + input [1:0] PIPERX12CHARISK, + input [31:0] PIPERX12DATA, + input PIPERX12DATAVALID, + input PIPERX12ELECIDLE, + input PIPERX12EQDONE, + input PIPERX12EQLPADAPTDONE, + input PIPERX12EQLPLFFSSEL, + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET, + input PIPERX12PHYSTATUS, + input [1:0] PIPERX12STARTBLOCK, + input [2:0] PIPERX12STATUS, + input [1:0] PIPERX12SYNCHEADER, + input PIPERX12VALID, + input [1:0] PIPERX13CHARISK, + input [31:0] PIPERX13DATA, + input PIPERX13DATAVALID, + input PIPERX13ELECIDLE, + input PIPERX13EQDONE, + input PIPERX13EQLPADAPTDONE, + input PIPERX13EQLPLFFSSEL, + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET, + input PIPERX13PHYSTATUS, + input [1:0] PIPERX13STARTBLOCK, + input [2:0] PIPERX13STATUS, + input [1:0] PIPERX13SYNCHEADER, + input PIPERX13VALID, + input [1:0] PIPERX14CHARISK, + input [31:0] PIPERX14DATA, + input PIPERX14DATAVALID, + input PIPERX14ELECIDLE, + input PIPERX14EQDONE, + input PIPERX14EQLPADAPTDONE, + input PIPERX14EQLPLFFSSEL, + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET, + input PIPERX14PHYSTATUS, + input [1:0] PIPERX14STARTBLOCK, + input [2:0] PIPERX14STATUS, + input [1:0] PIPERX14SYNCHEADER, + input PIPERX14VALID, + input [1:0] PIPERX15CHARISK, + input [31:0] PIPERX15DATA, + input PIPERX15DATAVALID, + input PIPERX15ELECIDLE, + input PIPERX15EQDONE, + input PIPERX15EQLPADAPTDONE, + input PIPERX15EQLPLFFSSEL, + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET, + input PIPERX15PHYSTATUS, + input [1:0] PIPERX15STARTBLOCK, + input [2:0] PIPERX15STATUS, + input [1:0] PIPERX15SYNCHEADER, + input PIPERX15VALID, + input [17:0] PIPETX00EQCOEFF, + input PIPETX00EQDONE, + input [17:0] PIPETX01EQCOEFF, + input PIPETX01EQDONE, + input [17:0] PIPETX02EQCOEFF, + input PIPETX02EQDONE, + input [17:0] PIPETX03EQCOEFF, + input PIPETX03EQDONE, + input [17:0] PIPETX04EQCOEFF, + input PIPETX04EQDONE, + input [17:0] PIPETX05EQCOEFF, + input PIPETX05EQDONE, + input [17:0] PIPETX06EQCOEFF, + input PIPETX06EQDONE, + input [17:0] PIPETX07EQCOEFF, + input PIPETX07EQDONE, + input [17:0] PIPETX08EQCOEFF, + input PIPETX08EQDONE, + input [17:0] PIPETX09EQCOEFF, + input PIPETX09EQDONE, + input [17:0] PIPETX10EQCOEFF, + input PIPETX10EQDONE, + input [17:0] PIPETX11EQCOEFF, + input PIPETX11EQDONE, + input [17:0] PIPETX12EQCOEFF, + input PIPETX12EQDONE, + input [17:0] PIPETX13EQCOEFF, + input PIPETX13EQDONE, + input [17:0] PIPETX14EQCOEFF, + input PIPETX14EQDONE, + input [17:0] PIPETX15EQCOEFF, + input PIPETX15EQDONE, + input PLEQRESETEIEOSCOUNT, + input PLGEN2UPSTREAMPREFERDEEMPH, + input PLGEN34REDOEQSPEED, + input PLGEN34REDOEQUALIZATION, + input RESETN, + input [255:0] SAXISCCIXTXTDATA, + input [45:0] SAXISCCIXTXTUSER, + input SAXISCCIXTXTVALID, + input [255:0] SAXISCCTDATA, + input [7:0] SAXISCCTKEEP, + input SAXISCCTLAST, + input [32:0] SAXISCCTUSER, + input SAXISCCTVALID, + input [255:0] SAXISRQTDATA, + input [7:0] SAXISRQTKEEP, + input SAXISRQTLAST, + input [61:0] SAXISRQTUSER, + input SAXISRQTVALID, + input USERCLK, + input USERCLK2, + input USERCLKEN, + input [31:0] USERSPAREIN +); + +// define constants + localparam MODULE_NAME = "PCIE4CE4"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "PCIE4CE4_dr.v" +`else + localparam [40:1] ARI_CAP_ENABLE_REG = ARI_CAP_ENABLE; + localparam [40:1] AUTO_FLR_RESPONSE_REG = AUTO_FLR_RESPONSE; + localparam [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT_REG = AXISTEN_IF_CCIX_RX_CREDIT_LIMIT; + localparam [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT_REG = AXISTEN_IF_CCIX_TX_CREDIT_LIMIT; + localparam [40:1] AXISTEN_IF_CCIX_TX_REGISTERED_TREADY_REG = AXISTEN_IF_CCIX_TX_REGISTERED_TREADY; + localparam [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE_REG = AXISTEN_IF_CC_ALIGNMENT_MODE; + localparam [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0_REG = AXISTEN_IF_COMPL_TIMEOUT_REG0; + localparam [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1_REG = AXISTEN_IF_COMPL_TIMEOUT_REG1; + localparam [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE_REG = AXISTEN_IF_CQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG = AXISTEN_IF_CQ_EN_POISONED_MEM_WR; + localparam [40:1] AXISTEN_IF_ENABLE_256_TAGS_REG = AXISTEN_IF_ENABLE_256_TAGS; + localparam [40:1] AXISTEN_IF_ENABLE_CLIENT_TAG_REG = AXISTEN_IF_ENABLE_CLIENT_TAG; + localparam [40:1] AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG = AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE; + localparam [40:1] AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG = AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK; + localparam [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE_REG = AXISTEN_IF_ENABLE_MSG_ROUTE; + localparam [40:1] AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG = AXISTEN_IF_ENABLE_RX_MSG_INTFC; + localparam [40:1] AXISTEN_IF_EXT_512_REG = AXISTEN_IF_EXT_512; + localparam [40:1] AXISTEN_IF_EXT_512_CC_STRADDLE_REG = AXISTEN_IF_EXT_512_CC_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_CQ_STRADDLE_REG = AXISTEN_IF_EXT_512_CQ_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_RC_STRADDLE_REG = AXISTEN_IF_EXT_512_RC_STRADDLE; + localparam [40:1] AXISTEN_IF_EXT_512_RQ_STRADDLE_REG = AXISTEN_IF_EXT_512_RQ_STRADDLE; + localparam [40:1] AXISTEN_IF_LEGACY_MODE_ENABLE_REG = AXISTEN_IF_LEGACY_MODE_ENABLE; + localparam [40:1] AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG = AXISTEN_IF_MSIX_FROM_RAM_PIPELINE; + localparam [40:1] AXISTEN_IF_MSIX_RX_PARITY_EN_REG = AXISTEN_IF_MSIX_RX_PARITY_EN; + localparam [40:1] AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG = AXISTEN_IF_MSIX_TO_RAM_PIPELINE; + localparam [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE_REG = AXISTEN_IF_RC_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RC_STRADDLE_REG = AXISTEN_IF_RC_STRADDLE; + localparam [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE_REG = AXISTEN_IF_RQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RX_PARITY_EN_REG = AXISTEN_IF_RX_PARITY_EN; + localparam [40:1] AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG = AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT; + localparam [40:1] AXISTEN_IF_TX_PARITY_EN_REG = AXISTEN_IF_TX_PARITY_EN; + localparam [1:0] AXISTEN_IF_WIDTH_REG = AXISTEN_IF_WIDTH; + localparam [40:1] CCIX_DIRECT_ATTACH_MODE_REG = CCIX_DIRECT_ATTACH_MODE; + localparam [40:1] CCIX_ENABLE_REG = CCIX_ENABLE; + localparam [15:0] CCIX_VENDOR_ID_REG = CCIX_VENDOR_ID; + localparam [40:1] CFG_BYPASS_MODE_ENABLE_REG = CFG_BYPASS_MODE_ENABLE; + localparam [40:1] CRM_CORE_CLK_FREQ_500_REG = CRM_CORE_CLK_FREQ_500; + localparam [1:0] CRM_USER_CLK_FREQ_REG = CRM_USER_CLK_FREQ; + localparam [15:0] DEBUG_AXI4ST_SPARE_REG = DEBUG_AXI4ST_SPARE; + localparam [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT_REG = DEBUG_AXIST_DISABLE_FEATURE_BIT; + localparam [3:0] DEBUG_CAR_SPARE_REG = DEBUG_CAR_SPARE; + localparam [15:0] DEBUG_CFG_SPARE_REG = DEBUG_CFG_SPARE; + localparam [15:0] DEBUG_LL_SPARE_REG = DEBUG_LL_SPARE; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG = DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR; + localparam [40:1] DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG = DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL; + localparam [40:1] DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG = DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW; + localparam [40:1] DEBUG_PL_DISABLE_SCRAMBLING_REG = DEBUG_PL_DISABLE_SCRAMBLING; + localparam [40:1] DEBUG_PL_SIM_RESET_LFSR_REG = DEBUG_PL_SIM_RESET_LFSR; + localparam [15:0] DEBUG_PL_SPARE_REG = DEBUG_PL_SPARE; + localparam [40:1] DEBUG_TL_DISABLE_FC_TIMEOUT_REG = DEBUG_TL_DISABLE_FC_TIMEOUT; + localparam [40:1] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG = DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS; + localparam [15:0] DEBUG_TL_SPARE_REG = DEBUG_TL_SPARE; + localparam [7:0] DNSTREAM_LINK_NUM_REG = DNSTREAM_LINK_NUM; + localparam [40:1] DSN_CAP_ENABLE_REG = DSN_CAP_ENABLE; + localparam [40:1] EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG = EXTENDED_CFG_EXTEND_INTERFACE_ENABLE; + localparam [40:1] HEADER_TYPE_OVERRIDE_REG = HEADER_TYPE_OVERRIDE; + localparam [40:1] IS_SWITCH_PORT_REG = IS_SWITCH_PORT; + localparam [40:1] LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG = LEGACY_CFG_EXTEND_INTERFACE_ENABLE; + localparam [8:0] LL_ACK_TIMEOUT_REG = LL_ACK_TIMEOUT; + localparam [40:1] LL_ACK_TIMEOUT_EN_REG = LL_ACK_TIMEOUT_EN; + localparam [1:0] LL_ACK_TIMEOUT_FUNC_REG = LL_ACK_TIMEOUT_FUNC; + localparam [40:1] LL_DISABLE_SCHED_TX_NAK_REG = LL_DISABLE_SCHED_TX_NAK; + localparam [40:1] LL_REPLAY_FROM_RAM_PIPELINE_REG = LL_REPLAY_FROM_RAM_PIPELINE; + localparam [8:0] LL_REPLAY_TIMEOUT_REG = LL_REPLAY_TIMEOUT; + localparam [40:1] LL_REPLAY_TIMEOUT_EN_REG = LL_REPLAY_TIMEOUT_EN; + localparam [1:0] LL_REPLAY_TIMEOUT_FUNC_REG = LL_REPLAY_TIMEOUT_FUNC; + localparam [40:1] LL_REPLAY_TO_RAM_PIPELINE_REG = LL_REPLAY_TO_RAM_PIPELINE; + localparam [40:1] LL_RX_TLP_PARITY_GEN_REG = LL_RX_TLP_PARITY_GEN; + localparam [40:1] LL_TX_TLP_PARITY_CHK_REG = LL_TX_TLP_PARITY_CHK; + localparam [15:0] LL_USER_SPARE_REG = LL_USER_SPARE; + localparam [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG = LTR_TX_MESSAGE_MINIMUM_INTERVAL; + localparam [40:1] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG = LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE; + localparam [40:1] LTR_TX_MESSAGE_ON_LTR_ENABLE_REG = LTR_TX_MESSAGE_ON_LTR_ENABLE; + localparam [11:0] MCAP_CAP_NEXTPTR_REG = MCAP_CAP_NEXTPTR; + localparam [40:1] MCAP_CONFIGURE_OVERRIDE_REG = MCAP_CONFIGURE_OVERRIDE; + localparam [40:1] MCAP_ENABLE_REG = MCAP_ENABLE; + localparam [40:1] MCAP_EOS_DESIGN_SWITCH_REG = MCAP_EOS_DESIGN_SWITCH; + localparam [31:0] MCAP_FPGA_BITSTREAM_VERSION_REG = MCAP_FPGA_BITSTREAM_VERSION; + localparam [40:1] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_IO_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_INPUT_GATE_DESIGN_SWITCH_REG = MCAP_INPUT_GATE_DESIGN_SWITCH; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_EOS_REG = MCAP_INTERRUPT_ON_MCAP_EOS; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_ERROR_REG = MCAP_INTERRUPT_ON_MCAP_ERROR; + localparam [15:0] MCAP_VSEC_ID_REG = MCAP_VSEC_ID; + localparam [11:0] MCAP_VSEC_LEN_REG = MCAP_VSEC_LEN; + localparam [3:0] MCAP_VSEC_REV_REG = MCAP_VSEC_REV; + localparam [40:1] PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG = PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE; + localparam [11:0] PF0_AER_CAP_NEXTPTR_REG = PF0_AER_CAP_NEXTPTR; + localparam [11:0] PF0_ARI_CAP_NEXTPTR_REG = PF0_ARI_CAP_NEXTPTR; + localparam [7:0] PF0_ARI_CAP_NEXT_FUNC_REG = PF0_ARI_CAP_NEXT_FUNC; + localparam [3:0] PF0_ARI_CAP_VER_REG = PF0_ARI_CAP_VER; + localparam [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH_REG = PF0_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] PF0_ATS_CAP_NEXTPTR_REG = PF0_ATS_CAP_NEXTPTR; + localparam [40:1] PF0_ATS_CAP_ON_REG = PF0_ATS_CAP_ON; + localparam [5:0] PF0_BAR0_APERTURE_SIZE_REG = PF0_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_BAR0_CONTROL_REG = PF0_BAR0_CONTROL; + localparam [4:0] PF0_BAR1_APERTURE_SIZE_REG = PF0_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_BAR1_CONTROL_REG = PF0_BAR1_CONTROL; + localparam [5:0] PF0_BAR2_APERTURE_SIZE_REG = PF0_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_BAR2_CONTROL_REG = PF0_BAR2_CONTROL; + localparam [4:0] PF0_BAR3_APERTURE_SIZE_REG = PF0_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_BAR3_CONTROL_REG = PF0_BAR3_CONTROL; + localparam [5:0] PF0_BAR4_APERTURE_SIZE_REG = PF0_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_BAR4_CONTROL_REG = PF0_BAR4_CONTROL; + localparam [4:0] PF0_BAR5_APERTURE_SIZE_REG = PF0_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_BAR5_CONTROL_REG = PF0_BAR5_CONTROL; + localparam [7:0] PF0_CAPABILITY_POINTER_REG = PF0_CAPABILITY_POINTER; + localparam [23:0] PF0_CLASS_CODE_REG = PF0_CLASS_CODE; + localparam [40:1] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG = PF0_DEV_CAP2_ARI_FORWARD_ENABLE; + localparam [40:1] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG = PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE; + localparam [40:1] PF0_DEV_CAP2_LTR_SUPPORT_REG = PF0_DEV_CAP2_LTR_SUPPORT; + localparam [1:0] PF0_DEV_CAP2_OBFF_SUPPORT_REG = PF0_DEV_CAP2_OBFF_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L1_LATENCY; + localparam [40:1] PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG = PF0_DEV_CAP_EXT_TAG_SUPPORTED; + localparam [40:1] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG = PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE; + localparam [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF0_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF0_DSN_CAP_NEXTPTR_REG = PF0_DSN_CAP_NEXTPTR; + localparam [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE_REG = PF0_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF0_EXPANSION_ROM_ENABLE_REG = PF0_EXPANSION_ROM_ENABLE; + localparam [2:0] PF0_INTERRUPT_PIN_REG = PF0_INTERRUPT_PIN; + localparam [1:0] PF0_LINK_CAP_ASPM_SUPPORT_REG = PF0_LINK_CAP_ASPM_SUPPORT; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4; + localparam [0:0] PF0_LINK_CONTROL_RCB_REG = PF0_LINK_CONTROL_RCB; + localparam [40:1] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG = PF0_LINK_STATUS_SLOT_CLOCK_CONFIG; + localparam [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG = PF0_LTR_CAP_MAX_NOSNOOP_LAT; + localparam [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT_REG = PF0_LTR_CAP_MAX_SNOOP_LAT; + localparam [11:0] PF0_LTR_CAP_NEXTPTR_REG = PF0_LTR_CAP_NEXTPTR; + localparam [3:0] PF0_LTR_CAP_VER_REG = PF0_LTR_CAP_VER; + localparam [7:0] PF0_MSIX_CAP_NEXTPTR_REG = PF0_MSIX_CAP_NEXTPTR; + localparam [2:0] PF0_MSIX_CAP_PBA_BIR_REG = PF0_MSIX_CAP_PBA_BIR; + localparam [28:0] PF0_MSIX_CAP_PBA_OFFSET_REG = PF0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF0_MSIX_CAP_TABLE_BIR_REG = PF0_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF0_MSIX_CAP_TABLE_OFFSET_REG = PF0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF0_MSIX_CAP_TABLE_SIZE_REG = PF0_MSIX_CAP_TABLE_SIZE; + localparam [5:0] PF0_MSIX_VECTOR_COUNT_REG = PF0_MSIX_VECTOR_COUNT; + localparam [2:0] PF0_MSI_CAP_MULTIMSGCAP_REG = PF0_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF0_MSI_CAP_NEXTPTR_REG = PF0_MSI_CAP_NEXTPTR; + localparam [40:1] PF0_MSI_CAP_PERVECMASKCAP_REG = PF0_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF0_PCIE_CAP_NEXTPTR_REG = PF0_PCIE_CAP_NEXTPTR; + localparam [7:0] PF0_PM_CAP_ID_REG = PF0_PM_CAP_ID; + localparam [7:0] PF0_PM_CAP_NEXTPTR_REG = PF0_PM_CAP_NEXTPTR; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D0_REG = PF0_PM_CAP_PMESUPPORT_D0; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D1_REG = PF0_PM_CAP_PMESUPPORT_D1; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D3HOT_REG = PF0_PM_CAP_PMESUPPORT_D3HOT; + localparam [40:1] PF0_PM_CAP_SUPP_D1_STATE_REG = PF0_PM_CAP_SUPP_D1_STATE; + localparam [2:0] PF0_PM_CAP_VER_ID_REG = PF0_PM_CAP_VER_ID; + localparam [40:1] PF0_PM_CSR_NOSOFTRESET_REG = PF0_PM_CSR_NOSOFTRESET; + localparam [11:0] PF0_PRI_CAP_NEXTPTR_REG = PF0_PRI_CAP_NEXTPTR; + localparam [40:1] PF0_PRI_CAP_ON_REG = PF0_PRI_CAP_ON; + localparam [31:0] PF0_PRI_OST_PR_CAPACITY_REG = PF0_PRI_OST_PR_CAPACITY; + localparam [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG = PF0_SECONDARY_PCIE_CAP_NEXTPTR; + localparam [40:1] PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE_REG = PF0_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR0_CONTROL_REG = PF0_SRIOV_BAR0_CONTROL; + localparam [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE_REG = PF0_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR1_CONTROL_REG = PF0_SRIOV_BAR1_CONTROL; + localparam [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE_REG = PF0_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR2_CONTROL_REG = PF0_SRIOV_BAR2_CONTROL; + localparam [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE_REG = PF0_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR3_CONTROL_REG = PF0_SRIOV_BAR3_CONTROL; + localparam [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE_REG = PF0_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR4_CONTROL_REG = PF0_SRIOV_BAR4_CONTROL; + localparam [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE_REG = PF0_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR5_CONTROL_REG = PF0_SRIOV_BAR5_CONTROL; + localparam [15:0] PF0_SRIOV_CAP_INITIAL_VF_REG = PF0_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF0_SRIOV_CAP_NEXTPTR_REG = PF0_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF0_SRIOV_CAP_TOTAL_VF_REG = PF0_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF0_SRIOV_CAP_VER_REG = PF0_SRIOV_CAP_VER; + localparam [15:0] PF0_SRIOV_FIRST_VF_OFFSET_REG = PF0_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF0_SRIOV_FUNC_DEP_LINK_REG = PF0_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF0_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF0_SRIOV_VF_DEVICE_ID_REG = PF0_SRIOV_VF_DEVICE_ID; + localparam [40:1] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF0_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF0_TPHR_CAP_ENABLE_REG = PF0_TPHR_CAP_ENABLE; + localparam [40:1] PF0_TPHR_CAP_INT_VEC_MODE_REG = PF0_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF0_TPHR_CAP_NEXTPTR_REG = PF0_TPHR_CAP_NEXTPTR; + localparam [2:0] PF0_TPHR_CAP_ST_MODE_SEL_REG = PF0_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF0_TPHR_CAP_ST_TABLE_LOC_REG = PF0_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE_REG = PF0_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF0_TPHR_CAP_VER_REG = PF0_TPHR_CAP_VER; + localparam [3:0] PF0_VC_ARB_CAPABILITY_REG = PF0_VC_ARB_CAPABILITY; + localparam [7:0] PF0_VC_ARB_TBL_OFFSET_REG = PF0_VC_ARB_TBL_OFFSET; + localparam [40:1] PF0_VC_CAP_ENABLE_REG = PF0_VC_CAP_ENABLE; + localparam [11:0] PF0_VC_CAP_NEXTPTR_REG = PF0_VC_CAP_NEXTPTR; + localparam [3:0] PF0_VC_CAP_VER_REG = PF0_VC_CAP_VER; + localparam [40:1] PF0_VC_EXTENDED_COUNT_REG = PF0_VC_EXTENDED_COUNT; + localparam [40:1] PF0_VC_LOW_PRIORITY_EXTENDED_COUNT_REG = PF0_VC_LOW_PRIORITY_EXTENDED_COUNT; + localparam [11:0] PF1_AER_CAP_NEXTPTR_REG = PF1_AER_CAP_NEXTPTR; + localparam [11:0] PF1_ARI_CAP_NEXTPTR_REG = PF1_ARI_CAP_NEXTPTR; + localparam [7:0] PF1_ARI_CAP_NEXT_FUNC_REG = PF1_ARI_CAP_NEXT_FUNC; + localparam [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH_REG = PF1_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] PF1_ATS_CAP_NEXTPTR_REG = PF1_ATS_CAP_NEXTPTR; + localparam [40:1] PF1_ATS_CAP_ON_REG = PF1_ATS_CAP_ON; + localparam [5:0] PF1_BAR0_APERTURE_SIZE_REG = PF1_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_BAR0_CONTROL_REG = PF1_BAR0_CONTROL; + localparam [4:0] PF1_BAR1_APERTURE_SIZE_REG = PF1_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_BAR1_CONTROL_REG = PF1_BAR1_CONTROL; + localparam [5:0] PF1_BAR2_APERTURE_SIZE_REG = PF1_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_BAR2_CONTROL_REG = PF1_BAR2_CONTROL; + localparam [4:0] PF1_BAR3_APERTURE_SIZE_REG = PF1_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_BAR3_CONTROL_REG = PF1_BAR3_CONTROL; + localparam [5:0] PF1_BAR4_APERTURE_SIZE_REG = PF1_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_BAR4_CONTROL_REG = PF1_BAR4_CONTROL; + localparam [4:0] PF1_BAR5_APERTURE_SIZE_REG = PF1_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_BAR5_CONTROL_REG = PF1_BAR5_CONTROL; + localparam [7:0] PF1_CAPABILITY_POINTER_REG = PF1_CAPABILITY_POINTER; + localparam [23:0] PF1_CLASS_CODE_REG = PF1_CLASS_CODE; + localparam [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF1_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF1_DSN_CAP_NEXTPTR_REG = PF1_DSN_CAP_NEXTPTR; + localparam [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE_REG = PF1_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF1_EXPANSION_ROM_ENABLE_REG = PF1_EXPANSION_ROM_ENABLE; + localparam [2:0] PF1_INTERRUPT_PIN_REG = PF1_INTERRUPT_PIN; + localparam [7:0] PF1_MSIX_CAP_NEXTPTR_REG = PF1_MSIX_CAP_NEXTPTR; + localparam [2:0] PF1_MSIX_CAP_PBA_BIR_REG = PF1_MSIX_CAP_PBA_BIR; + localparam [28:0] PF1_MSIX_CAP_PBA_OFFSET_REG = PF1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF1_MSIX_CAP_TABLE_BIR_REG = PF1_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF1_MSIX_CAP_TABLE_OFFSET_REG = PF1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF1_MSIX_CAP_TABLE_SIZE_REG = PF1_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF1_MSI_CAP_MULTIMSGCAP_REG = PF1_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF1_MSI_CAP_NEXTPTR_REG = PF1_MSI_CAP_NEXTPTR; + localparam [40:1] PF1_MSI_CAP_PERVECMASKCAP_REG = PF1_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF1_PCIE_CAP_NEXTPTR_REG = PF1_PCIE_CAP_NEXTPTR; + localparam [7:0] PF1_PM_CAP_NEXTPTR_REG = PF1_PM_CAP_NEXTPTR; + localparam [11:0] PF1_PRI_CAP_NEXTPTR_REG = PF1_PRI_CAP_NEXTPTR; + localparam [40:1] PF1_PRI_CAP_ON_REG = PF1_PRI_CAP_ON; + localparam [31:0] PF1_PRI_OST_PR_CAPACITY_REG = PF1_PRI_OST_PR_CAPACITY; + localparam [40:1] PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE_REG = PF1_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR0_CONTROL_REG = PF1_SRIOV_BAR0_CONTROL; + localparam [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE_REG = PF1_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR1_CONTROL_REG = PF1_SRIOV_BAR1_CONTROL; + localparam [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE_REG = PF1_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR2_CONTROL_REG = PF1_SRIOV_BAR2_CONTROL; + localparam [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE_REG = PF1_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR3_CONTROL_REG = PF1_SRIOV_BAR3_CONTROL; + localparam [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE_REG = PF1_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR4_CONTROL_REG = PF1_SRIOV_BAR4_CONTROL; + localparam [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE_REG = PF1_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR5_CONTROL_REG = PF1_SRIOV_BAR5_CONTROL; + localparam [15:0] PF1_SRIOV_CAP_INITIAL_VF_REG = PF1_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF1_SRIOV_CAP_NEXTPTR_REG = PF1_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF1_SRIOV_CAP_TOTAL_VF_REG = PF1_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF1_SRIOV_CAP_VER_REG = PF1_SRIOV_CAP_VER; + localparam [15:0] PF1_SRIOV_FIRST_VF_OFFSET_REG = PF1_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF1_SRIOV_FUNC_DEP_LINK_REG = PF1_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF1_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF1_SRIOV_VF_DEVICE_ID_REG = PF1_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF1_TPHR_CAP_NEXTPTR_REG = PF1_TPHR_CAP_NEXTPTR; + localparam [2:0] PF1_TPHR_CAP_ST_MODE_SEL_REG = PF1_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] PF2_AER_CAP_NEXTPTR_REG = PF2_AER_CAP_NEXTPTR; + localparam [11:0] PF2_ARI_CAP_NEXTPTR_REG = PF2_ARI_CAP_NEXTPTR; + localparam [7:0] PF2_ARI_CAP_NEXT_FUNC_REG = PF2_ARI_CAP_NEXT_FUNC; + localparam [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH_REG = PF2_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] PF2_ATS_CAP_NEXTPTR_REG = PF2_ATS_CAP_NEXTPTR; + localparam [40:1] PF2_ATS_CAP_ON_REG = PF2_ATS_CAP_ON; + localparam [5:0] PF2_BAR0_APERTURE_SIZE_REG = PF2_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_BAR0_CONTROL_REG = PF2_BAR0_CONTROL; + localparam [4:0] PF2_BAR1_APERTURE_SIZE_REG = PF2_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_BAR1_CONTROL_REG = PF2_BAR1_CONTROL; + localparam [5:0] PF2_BAR2_APERTURE_SIZE_REG = PF2_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_BAR2_CONTROL_REG = PF2_BAR2_CONTROL; + localparam [4:0] PF2_BAR3_APERTURE_SIZE_REG = PF2_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_BAR3_CONTROL_REG = PF2_BAR3_CONTROL; + localparam [5:0] PF2_BAR4_APERTURE_SIZE_REG = PF2_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_BAR4_CONTROL_REG = PF2_BAR4_CONTROL; + localparam [4:0] PF2_BAR5_APERTURE_SIZE_REG = PF2_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_BAR5_CONTROL_REG = PF2_BAR5_CONTROL; + localparam [7:0] PF2_CAPABILITY_POINTER_REG = PF2_CAPABILITY_POINTER; + localparam [23:0] PF2_CLASS_CODE_REG = PF2_CLASS_CODE; + localparam [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF2_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF2_DSN_CAP_NEXTPTR_REG = PF2_DSN_CAP_NEXTPTR; + localparam [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE_REG = PF2_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF2_EXPANSION_ROM_ENABLE_REG = PF2_EXPANSION_ROM_ENABLE; + localparam [2:0] PF2_INTERRUPT_PIN_REG = PF2_INTERRUPT_PIN; + localparam [7:0] PF2_MSIX_CAP_NEXTPTR_REG = PF2_MSIX_CAP_NEXTPTR; + localparam [2:0] PF2_MSIX_CAP_PBA_BIR_REG = PF2_MSIX_CAP_PBA_BIR; + localparam [28:0] PF2_MSIX_CAP_PBA_OFFSET_REG = PF2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF2_MSIX_CAP_TABLE_BIR_REG = PF2_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF2_MSIX_CAP_TABLE_OFFSET_REG = PF2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF2_MSIX_CAP_TABLE_SIZE_REG = PF2_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF2_MSI_CAP_MULTIMSGCAP_REG = PF2_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF2_MSI_CAP_NEXTPTR_REG = PF2_MSI_CAP_NEXTPTR; + localparam [40:1] PF2_MSI_CAP_PERVECMASKCAP_REG = PF2_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF2_PCIE_CAP_NEXTPTR_REG = PF2_PCIE_CAP_NEXTPTR; + localparam [7:0] PF2_PM_CAP_NEXTPTR_REG = PF2_PM_CAP_NEXTPTR; + localparam [11:0] PF2_PRI_CAP_NEXTPTR_REG = PF2_PRI_CAP_NEXTPTR; + localparam [40:1] PF2_PRI_CAP_ON_REG = PF2_PRI_CAP_ON; + localparam [31:0] PF2_PRI_OST_PR_CAPACITY_REG = PF2_PRI_OST_PR_CAPACITY; + localparam [40:1] PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE_REG = PF2_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR0_CONTROL_REG = PF2_SRIOV_BAR0_CONTROL; + localparam [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE_REG = PF2_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR1_CONTROL_REG = PF2_SRIOV_BAR1_CONTROL; + localparam [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE_REG = PF2_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR2_CONTROL_REG = PF2_SRIOV_BAR2_CONTROL; + localparam [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE_REG = PF2_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR3_CONTROL_REG = PF2_SRIOV_BAR3_CONTROL; + localparam [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE_REG = PF2_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR4_CONTROL_REG = PF2_SRIOV_BAR4_CONTROL; + localparam [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE_REG = PF2_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR5_CONTROL_REG = PF2_SRIOV_BAR5_CONTROL; + localparam [15:0] PF2_SRIOV_CAP_INITIAL_VF_REG = PF2_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF2_SRIOV_CAP_NEXTPTR_REG = PF2_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF2_SRIOV_CAP_TOTAL_VF_REG = PF2_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF2_SRIOV_CAP_VER_REG = PF2_SRIOV_CAP_VER; + localparam [15:0] PF2_SRIOV_FIRST_VF_OFFSET_REG = PF2_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF2_SRIOV_FUNC_DEP_LINK_REG = PF2_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF2_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF2_SRIOV_VF_DEVICE_ID_REG = PF2_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF2_TPHR_CAP_NEXTPTR_REG = PF2_TPHR_CAP_NEXTPTR; + localparam [2:0] PF2_TPHR_CAP_ST_MODE_SEL_REG = PF2_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] PF3_AER_CAP_NEXTPTR_REG = PF3_AER_CAP_NEXTPTR; + localparam [11:0] PF3_ARI_CAP_NEXTPTR_REG = PF3_ARI_CAP_NEXTPTR; + localparam [7:0] PF3_ARI_CAP_NEXT_FUNC_REG = PF3_ARI_CAP_NEXT_FUNC; + localparam [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH_REG = PF3_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] PF3_ATS_CAP_NEXTPTR_REG = PF3_ATS_CAP_NEXTPTR; + localparam [40:1] PF3_ATS_CAP_ON_REG = PF3_ATS_CAP_ON; + localparam [5:0] PF3_BAR0_APERTURE_SIZE_REG = PF3_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_BAR0_CONTROL_REG = PF3_BAR0_CONTROL; + localparam [4:0] PF3_BAR1_APERTURE_SIZE_REG = PF3_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_BAR1_CONTROL_REG = PF3_BAR1_CONTROL; + localparam [5:0] PF3_BAR2_APERTURE_SIZE_REG = PF3_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_BAR2_CONTROL_REG = PF3_BAR2_CONTROL; + localparam [4:0] PF3_BAR3_APERTURE_SIZE_REG = PF3_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_BAR3_CONTROL_REG = PF3_BAR3_CONTROL; + localparam [5:0] PF3_BAR4_APERTURE_SIZE_REG = PF3_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_BAR4_CONTROL_REG = PF3_BAR4_CONTROL; + localparam [4:0] PF3_BAR5_APERTURE_SIZE_REG = PF3_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_BAR5_CONTROL_REG = PF3_BAR5_CONTROL; + localparam [7:0] PF3_CAPABILITY_POINTER_REG = PF3_CAPABILITY_POINTER; + localparam [23:0] PF3_CLASS_CODE_REG = PF3_CLASS_CODE; + localparam [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF3_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF3_DSN_CAP_NEXTPTR_REG = PF3_DSN_CAP_NEXTPTR; + localparam [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE_REG = PF3_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF3_EXPANSION_ROM_ENABLE_REG = PF3_EXPANSION_ROM_ENABLE; + localparam [2:0] PF3_INTERRUPT_PIN_REG = PF3_INTERRUPT_PIN; + localparam [7:0] PF3_MSIX_CAP_NEXTPTR_REG = PF3_MSIX_CAP_NEXTPTR; + localparam [2:0] PF3_MSIX_CAP_PBA_BIR_REG = PF3_MSIX_CAP_PBA_BIR; + localparam [28:0] PF3_MSIX_CAP_PBA_OFFSET_REG = PF3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF3_MSIX_CAP_TABLE_BIR_REG = PF3_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF3_MSIX_CAP_TABLE_OFFSET_REG = PF3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF3_MSIX_CAP_TABLE_SIZE_REG = PF3_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF3_MSI_CAP_MULTIMSGCAP_REG = PF3_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF3_MSI_CAP_NEXTPTR_REG = PF3_MSI_CAP_NEXTPTR; + localparam [40:1] PF3_MSI_CAP_PERVECMASKCAP_REG = PF3_MSI_CAP_PERVECMASKCAP; + localparam [7:0] PF3_PCIE_CAP_NEXTPTR_REG = PF3_PCIE_CAP_NEXTPTR; + localparam [7:0] PF3_PM_CAP_NEXTPTR_REG = PF3_PM_CAP_NEXTPTR; + localparam [11:0] PF3_PRI_CAP_NEXTPTR_REG = PF3_PRI_CAP_NEXTPTR; + localparam [40:1] PF3_PRI_CAP_ON_REG = PF3_PRI_CAP_ON; + localparam [31:0] PF3_PRI_OST_PR_CAPACITY_REG = PF3_PRI_OST_PR_CAPACITY; + localparam [40:1] PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG = PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED; + localparam [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE_REG = PF3_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR0_CONTROL_REG = PF3_SRIOV_BAR0_CONTROL; + localparam [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE_REG = PF3_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR1_CONTROL_REG = PF3_SRIOV_BAR1_CONTROL; + localparam [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE_REG = PF3_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR2_CONTROL_REG = PF3_SRIOV_BAR2_CONTROL; + localparam [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE_REG = PF3_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR3_CONTROL_REG = PF3_SRIOV_BAR3_CONTROL; + localparam [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE_REG = PF3_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR4_CONTROL_REG = PF3_SRIOV_BAR4_CONTROL; + localparam [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE_REG = PF3_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR5_CONTROL_REG = PF3_SRIOV_BAR5_CONTROL; + localparam [15:0] PF3_SRIOV_CAP_INITIAL_VF_REG = PF3_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF3_SRIOV_CAP_NEXTPTR_REG = PF3_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF3_SRIOV_CAP_TOTAL_VF_REG = PF3_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF3_SRIOV_CAP_VER_REG = PF3_SRIOV_CAP_VER; + localparam [15:0] PF3_SRIOV_FIRST_VF_OFFSET_REG = PF3_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF3_SRIOV_FUNC_DEP_LINK_REG = PF3_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF3_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF3_SRIOV_VF_DEVICE_ID_REG = PF3_SRIOV_VF_DEVICE_ID; + localparam [11:0] PF3_TPHR_CAP_NEXTPTR_REG = PF3_TPHR_CAP_NEXTPTR; + localparam [2:0] PF3_TPHR_CAP_ST_MODE_SEL_REG = PF3_TPHR_CAP_ST_MODE_SEL; + localparam [40:1] PL_CFG_STATE_ROBUSTNESS_ENABLE_REG = PL_CFG_STATE_ROBUSTNESS_ENABLE; + localparam [40:1] PL_CTRL_SKP_GEN_ENABLE_REG = PL_CTRL_SKP_GEN_ENABLE; + localparam [40:1] PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE_REG = PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE; + localparam [40:1] PL_DEEMPH_SOURCE_SELECT_REG = PL_DEEMPH_SOURCE_SELECT; + localparam [40:1] PL_DESKEW_ON_SKIP_IN_GEN12_REG = PL_DESKEW_ON_SKIP_IN_GEN12; + localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3; + localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4; + localparam [40:1] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG = PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2; + localparam [40:1] PL_DISABLE_DC_BALANCE_REG = PL_DISABLE_DC_BALANCE; + localparam [40:1] PL_DISABLE_EI_INFER_IN_L0_REG = PL_DISABLE_EI_INFER_IN_L0; + localparam [40:1] PL_DISABLE_LANE_REVERSAL_REG = PL_DISABLE_LANE_REVERSAL; + localparam [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP_REG = PL_DISABLE_LFSR_UPDATE_ON_SKP; + localparam [40:1] PL_DISABLE_RETRAIN_ON_EB_ERROR_REG = PL_DISABLE_RETRAIN_ON_EB_ERROR; + localparam [40:1] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_FRAMING_ERROR; + localparam [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR; + localparam [40:1] PL_DISABLE_UPCONFIG_CAPABLE_REG = PL_DISABLE_UPCONFIG_CAPABLE; + localparam [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG = PL_EQ_ADAPT_DISABLE_COEFF_CHECK; + localparam [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG = PL_EQ_ADAPT_DISABLE_PRESET_CHECK; + localparam [4:0] PL_EQ_ADAPT_ITER_COUNT_REG = PL_EQ_ADAPT_ITER_COUNT; + localparam [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG = PL_EQ_ADAPT_REJECT_RETRY_COUNT; + localparam [1:0] PL_EQ_BYPASS_PHASE23_REG = PL_EQ_BYPASS_PHASE23; + localparam [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT_REG = PL_EQ_DEFAULT_RX_PRESET_HINT; + localparam [7:0] PL_EQ_DEFAULT_TX_PRESET_REG = PL_EQ_DEFAULT_TX_PRESET; + localparam [40:1] PL_EQ_DISABLE_MISMATCH_CHECK_REG = PL_EQ_DISABLE_MISMATCH_CHECK; + localparam [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0_REG = PL_EQ_RX_ADAPT_EQ_PHASE0; + localparam [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1_REG = PL_EQ_RX_ADAPT_EQ_PHASE1; + localparam [40:1] PL_EQ_SHORT_ADAPT_PHASE_REG = PL_EQ_SHORT_ADAPT_PHASE; + localparam [40:1] PL_EQ_TX_8G_EQ_TS2_ENABLE_REG = PL_EQ_TX_8G_EQ_TS2_ENABLE; + localparam [40:1] PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG = PL_EXIT_LOOPBACK_ON_EI_ENTRY; + localparam [40:1] PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG = PL_INFER_EI_DISABLE_LPBK_ACTIVE; + localparam [40:1] PL_INFER_EI_DISABLE_REC_RC_REG = PL_INFER_EI_DISABLE_REC_RC; + localparam [40:1] PL_INFER_EI_DISABLE_REC_SPD_REG = PL_INFER_EI_DISABLE_REC_SPD; + localparam [31:0] PL_LANE0_EQ_CONTROL_REG = PL_LANE0_EQ_CONTROL; + localparam [31:0] PL_LANE10_EQ_CONTROL_REG = PL_LANE10_EQ_CONTROL; + localparam [31:0] PL_LANE11_EQ_CONTROL_REG = PL_LANE11_EQ_CONTROL; + localparam [31:0] PL_LANE12_EQ_CONTROL_REG = PL_LANE12_EQ_CONTROL; + localparam [31:0] PL_LANE13_EQ_CONTROL_REG = PL_LANE13_EQ_CONTROL; + localparam [31:0] PL_LANE14_EQ_CONTROL_REG = PL_LANE14_EQ_CONTROL; + localparam [31:0] PL_LANE15_EQ_CONTROL_REG = PL_LANE15_EQ_CONTROL; + localparam [31:0] PL_LANE1_EQ_CONTROL_REG = PL_LANE1_EQ_CONTROL; + localparam [31:0] PL_LANE2_EQ_CONTROL_REG = PL_LANE2_EQ_CONTROL; + localparam [31:0] PL_LANE3_EQ_CONTROL_REG = PL_LANE3_EQ_CONTROL; + localparam [31:0] PL_LANE4_EQ_CONTROL_REG = PL_LANE4_EQ_CONTROL; + localparam [31:0] PL_LANE5_EQ_CONTROL_REG = PL_LANE5_EQ_CONTROL; + localparam [31:0] PL_LANE6_EQ_CONTROL_REG = PL_LANE6_EQ_CONTROL; + localparam [31:0] PL_LANE7_EQ_CONTROL_REG = PL_LANE7_EQ_CONTROL; + localparam [31:0] PL_LANE8_EQ_CONTROL_REG = PL_LANE8_EQ_CONTROL; + localparam [31:0] PL_LANE9_EQ_CONTROL_REG = PL_LANE9_EQ_CONTROL; + localparam [3:0] PL_LINK_CAP_MAX_LINK_SPEED_REG = PL_LINK_CAP_MAX_LINK_SPEED; + localparam [4:0] PL_LINK_CAP_MAX_LINK_WIDTH_REG = PL_LINK_CAP_MAX_LINK_WIDTH; + localparam [7:0] PL_N_FTS_REG = PL_N_FTS; + localparam [40:1] PL_QUIESCE_GUARANTEE_DISABLE_REG = PL_QUIESCE_GUARANTEE_DISABLE; + localparam [40:1] PL_REDO_EQ_SOURCE_SELECT_REG = PL_REDO_EQ_SOURCE_SELECT; + localparam [7:0] PL_REPORT_ALL_PHY_ERRORS_REG = PL_REPORT_ALL_PHY_ERRORS; + localparam [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS_REG = PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS; + localparam [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3_REG = PL_RX_ADAPT_TIMER_CLWS_GEN3; + localparam [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4_REG = PL_RX_ADAPT_TIMER_CLWS_GEN4; + localparam [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS_REG = PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS; + localparam [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3_REG = PL_RX_ADAPT_TIMER_RRL_GEN3; + localparam [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4_REG = PL_RX_ADAPT_TIMER_RRL_GEN4; + localparam [1:0] PL_RX_L0S_EXIT_TO_RECOVERY_REG = PL_RX_L0S_EXIT_TO_RECOVERY; + localparam [1:0] PL_SIM_FAST_LINK_TRAINING_REG = PL_SIM_FAST_LINK_TRAINING; + localparam [40:1] PL_SRIS_ENABLE_REG = PL_SRIS_ENABLE; + localparam [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC_REG = PL_SRIS_SKPOS_GEN_SPD_VEC; + localparam [6:0] PL_SRIS_SKPOS_REC_SPD_VEC_REG = PL_SRIS_SKPOS_REC_SPD_VEC; + localparam [40:1] PL_UPSTREAM_FACING_REG = PL_UPSTREAM_FACING; + localparam [15:0] PL_USER_SPARE_REG = PL_USER_SPARE; + localparam [15:0] PL_USER_SPARE2_REG = PL_USER_SPARE2; + localparam [15:0] PM_ASPML0S_TIMEOUT_REG = PM_ASPML0S_TIMEOUT; + localparam [19:0] PM_ASPML1_ENTRY_DELAY_REG = PM_ASPML1_ENTRY_DELAY; + localparam [40:1] PM_ENABLE_L23_ENTRY_REG = PM_ENABLE_L23_ENTRY; + localparam [40:1] PM_ENABLE_SLOT_POWER_CAPTURE_REG = PM_ENABLE_SLOT_POWER_CAPTURE; + localparam [31:0] PM_L1_REENTRY_DELAY_REG = PM_L1_REENTRY_DELAY; + localparam [19:0] PM_PME_SERVICE_TIMEOUT_DELAY_REG = PM_PME_SERVICE_TIMEOUT_DELAY; + localparam [15:0] PM_PME_TURNOFF_ACK_DELAY_REG = PM_PME_TURNOFF_ACK_DELAY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [31:0] SIM_JTAG_IDCODE_REG = SIM_JTAG_IDCODE; + localparam [24:1] SIM_VERSION_REG = SIM_VERSION; + localparam [40:1] SPARE_BIT0_REG = SPARE_BIT0; + localparam [0:0] SPARE_BIT1_REG = SPARE_BIT1; + localparam [0:0] SPARE_BIT2_REG = SPARE_BIT2; + localparam [40:1] SPARE_BIT3_REG = SPARE_BIT3; + localparam [0:0] SPARE_BIT4_REG = SPARE_BIT4; + localparam [0:0] SPARE_BIT5_REG = SPARE_BIT5; + localparam [0:0] SPARE_BIT6_REG = SPARE_BIT6; + localparam [0:0] SPARE_BIT7_REG = SPARE_BIT7; + localparam [0:0] SPARE_BIT8_REG = SPARE_BIT8; + localparam [7:0] SPARE_BYTE0_REG = SPARE_BYTE0; + localparam [7:0] SPARE_BYTE1_REG = SPARE_BYTE1; + localparam [7:0] SPARE_BYTE2_REG = SPARE_BYTE2; + localparam [7:0] SPARE_BYTE3_REG = SPARE_BYTE3; + localparam [31:0] SPARE_WORD0_REG = SPARE_WORD0; + localparam [31:0] SPARE_WORD1_REG = SPARE_WORD1; + localparam [31:0] SPARE_WORD2_REG = SPARE_WORD2; + localparam [31:0] SPARE_WORD3_REG = SPARE_WORD3; + localparam [3:0] SRIOV_CAP_ENABLE_REG = SRIOV_CAP_ENABLE; + localparam [40:1] TL2CFG_IF_PARITY_CHK_REG = TL2CFG_IF_PARITY_CHK; + localparam [1:0] TL_COMPLETION_RAM_NUM_TLPS_REG = TL_COMPLETION_RAM_NUM_TLPS; + localparam [1:0] TL_COMPLETION_RAM_SIZE_REG = TL_COMPLETION_RAM_SIZE; + localparam [11:0] TL_CREDITS_CD_REG = TL_CREDITS_CD; + localparam [11:0] TL_CREDITS_CD_VC1_REG = TL_CREDITS_CD_VC1; + localparam [7:0] TL_CREDITS_CH_REG = TL_CREDITS_CH; + localparam [7:0] TL_CREDITS_CH_VC1_REG = TL_CREDITS_CH_VC1; + localparam [11:0] TL_CREDITS_NPD_REG = TL_CREDITS_NPD; + localparam [11:0] TL_CREDITS_NPD_VC1_REG = TL_CREDITS_NPD_VC1; + localparam [7:0] TL_CREDITS_NPH_REG = TL_CREDITS_NPH; + localparam [7:0] TL_CREDITS_NPH_VC1_REG = TL_CREDITS_NPH_VC1; + localparam [11:0] TL_CREDITS_PD_REG = TL_CREDITS_PD; + localparam [11:0] TL_CREDITS_PD_VC1_REG = TL_CREDITS_PD_VC1; + localparam [7:0] TL_CREDITS_PH_REG = TL_CREDITS_PH; + localparam [7:0] TL_CREDITS_PH_VC1_REG = TL_CREDITS_PH_VC1; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_REG = TL_FC_UPDATE_MIN_INTERVAL_TIME; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1_REG = TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_REG = TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT; + localparam [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1_REG = TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1; + localparam [40:1] TL_FEATURE_ENABLE_FC_SCALING_REG = TL_FEATURE_ENABLE_FC_SCALING; + localparam [1:0] TL_PF_ENABLE_REG_REG = TL_PF_ENABLE_REG; + localparam [0:0] TL_POSTED_RAM_SIZE_REG = TL_POSTED_RAM_SIZE; + localparam [40:1] TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG = TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG = TL_RX_COMPLETION_TO_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG = TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE; + localparam [40:1] TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG = TL_RX_POSTED_FROM_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG = TL_RX_POSTED_TO_RAM_READ_PIPELINE; + localparam [40:1] TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG = TL_RX_POSTED_TO_RAM_WRITE_PIPELINE; + localparam [40:1] TL_TX_MUX_STRICT_PRIORITY_REG = TL_TX_MUX_STRICT_PRIORITY; + localparam [40:1] TL_TX_TLP_STRADDLE_ENABLE_REG = TL_TX_TLP_STRADDLE_ENABLE; + localparam [40:1] TL_TX_TLP_TERMINATE_PARITY_REG = TL_TX_TLP_TERMINATE_PARITY; + localparam [15:0] TL_USER_SPARE_REG = TL_USER_SPARE; + localparam [40:1] TPH_FROM_RAM_PIPELINE_REG = TPH_FROM_RAM_PIPELINE; + localparam [40:1] TPH_TO_RAM_PIPELINE_REG = TPH_TO_RAM_PIPELINE; + localparam [7:0] VF0_CAPABILITY_POINTER_REG = VF0_CAPABILITY_POINTER; + localparam [11:0] VFG0_ARI_CAP_NEXTPTR_REG = VFG0_ARI_CAP_NEXTPTR; + localparam [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH_REG = VFG0_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] VFG0_ATS_CAP_NEXTPTR_REG = VFG0_ATS_CAP_NEXTPTR; + localparam [40:1] VFG0_ATS_CAP_ON_REG = VFG0_ATS_CAP_ON; + localparam [7:0] VFG0_MSIX_CAP_NEXTPTR_REG = VFG0_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG0_MSIX_CAP_PBA_BIR_REG = VFG0_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG0_MSIX_CAP_PBA_OFFSET_REG = VFG0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG0_MSIX_CAP_TABLE_BIR_REG = VFG0_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG0_MSIX_CAP_TABLE_OFFSET_REG = VFG0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG0_MSIX_CAP_TABLE_SIZE_REG = VFG0_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG0_PCIE_CAP_NEXTPTR_REG = VFG0_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG0_TPHR_CAP_NEXTPTR_REG = VFG0_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG0_TPHR_CAP_ST_MODE_SEL_REG = VFG0_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG1_ARI_CAP_NEXTPTR_REG = VFG1_ARI_CAP_NEXTPTR; + localparam [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH_REG = VFG1_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] VFG1_ATS_CAP_NEXTPTR_REG = VFG1_ATS_CAP_NEXTPTR; + localparam [40:1] VFG1_ATS_CAP_ON_REG = VFG1_ATS_CAP_ON; + localparam [7:0] VFG1_MSIX_CAP_NEXTPTR_REG = VFG1_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG1_MSIX_CAP_PBA_BIR_REG = VFG1_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG1_MSIX_CAP_PBA_OFFSET_REG = VFG1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG1_MSIX_CAP_TABLE_BIR_REG = VFG1_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG1_MSIX_CAP_TABLE_OFFSET_REG = VFG1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG1_MSIX_CAP_TABLE_SIZE_REG = VFG1_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG1_PCIE_CAP_NEXTPTR_REG = VFG1_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG1_TPHR_CAP_NEXTPTR_REG = VFG1_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG1_TPHR_CAP_ST_MODE_SEL_REG = VFG1_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG2_ARI_CAP_NEXTPTR_REG = VFG2_ARI_CAP_NEXTPTR; + localparam [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH_REG = VFG2_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] VFG2_ATS_CAP_NEXTPTR_REG = VFG2_ATS_CAP_NEXTPTR; + localparam [40:1] VFG2_ATS_CAP_ON_REG = VFG2_ATS_CAP_ON; + localparam [7:0] VFG2_MSIX_CAP_NEXTPTR_REG = VFG2_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG2_MSIX_CAP_PBA_BIR_REG = VFG2_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG2_MSIX_CAP_PBA_OFFSET_REG = VFG2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG2_MSIX_CAP_TABLE_BIR_REG = VFG2_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG2_MSIX_CAP_TABLE_OFFSET_REG = VFG2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG2_MSIX_CAP_TABLE_SIZE_REG = VFG2_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG2_PCIE_CAP_NEXTPTR_REG = VFG2_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG2_TPHR_CAP_NEXTPTR_REG = VFG2_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG2_TPHR_CAP_ST_MODE_SEL_REG = VFG2_TPHR_CAP_ST_MODE_SEL; + localparam [11:0] VFG3_ARI_CAP_NEXTPTR_REG = VFG3_ARI_CAP_NEXTPTR; + localparam [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH_REG = VFG3_ATS_CAP_INV_QUEUE_DEPTH; + localparam [11:0] VFG3_ATS_CAP_NEXTPTR_REG = VFG3_ATS_CAP_NEXTPTR; + localparam [40:1] VFG3_ATS_CAP_ON_REG = VFG3_ATS_CAP_ON; + localparam [7:0] VFG3_MSIX_CAP_NEXTPTR_REG = VFG3_MSIX_CAP_NEXTPTR; + localparam [2:0] VFG3_MSIX_CAP_PBA_BIR_REG = VFG3_MSIX_CAP_PBA_BIR; + localparam [28:0] VFG3_MSIX_CAP_PBA_OFFSET_REG = VFG3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VFG3_MSIX_CAP_TABLE_BIR_REG = VFG3_MSIX_CAP_TABLE_BIR; + localparam [28:0] VFG3_MSIX_CAP_TABLE_OFFSET_REG = VFG3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VFG3_MSIX_CAP_TABLE_SIZE_REG = VFG3_MSIX_CAP_TABLE_SIZE; + localparam [7:0] VFG3_PCIE_CAP_NEXTPTR_REG = VFG3_PCIE_CAP_NEXTPTR; + localparam [11:0] VFG3_TPHR_CAP_NEXTPTR_REG = VFG3_TPHR_CAP_NEXTPTR; + localparam [2:0] VFG3_TPHR_CAP_ST_MODE_SEL_REG = VFG3_TPHR_CAP_ST_MODE_SEL; +`endif + + localparam [40:1] TEST_MODE_PIN_CHAR_REG = "FALSE"; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CCIXTXCREDIT_out; + wire CFGERRCOROUT_out; + wire CFGERRFATALOUT_out; + wire CFGERRNONFATALOUT_out; + wire CFGEXTREADRECEIVED_out; + wire CFGEXTWRITERECEIVED_out; + wire CFGHOTRESETOUT_out; + wire CFGINTERRUPTMSIFAIL_out; + wire CFGINTERRUPTMSIMASKUPDATE_out; + wire CFGINTERRUPTMSISENT_out; + wire CFGINTERRUPTMSIXVECPENDINGSTATUS_out; + wire CFGINTERRUPTSENT_out; + wire CFGLOCALERRORVALID_out; + wire CFGLTRENABLE_out; + wire CFGMGMTREADWRITEDONE_out; + wire CFGMSGRECEIVED_out; + wire CFGMSGTRANSMITDONE_out; + wire CFGMSIXRAMREADENABLE_out; + wire CFGPHYLINKDOWN_out; + wire CFGPLSTATUSCHANGE_out; + wire CFGPOWERSTATECHANGEINTERRUPT_out; + wire CFGTPHRAMREADENABLE_out; + wire CFGVC1ENABLE_out; + wire CFGVC1NEGOTIATIONPENDING_out; + wire CONFMCAPDESIGNSWITCH_out; + wire CONFMCAPEOS_out; + wire CONFMCAPINUSEBYPCIE_out; + wire CONFREQREADY_out; + wire CONFRESPVALID_out; + wire DRPRDY_out; + wire MAXISCCIXRXTVALID_out; + wire MAXISCQTLAST_out; + wire MAXISCQTVALID_out; + wire MAXISRCTLAST_out; + wire MAXISRCTVALID_out; + wire MIREPLAYRAMREADENABLE0_out; + wire MIREPLAYRAMREADENABLE1_out; + wire MIREPLAYRAMWRITEENABLE0_out; + wire MIREPLAYRAMWRITEENABLE1_out; + wire MIRXPOSTEDREQUESTRAMREADENABLE0_out; + wire MIRXPOSTEDREQUESTRAMREADENABLE1_out; + wire MIRXPOSTEDREQUESTRAMWRITEENABLE0_out; + wire MIRXPOSTEDREQUESTRAMWRITEENABLE1_out; + wire PCIEPERST0B_out; + wire PCIEPERST1B_out; + wire PCIERQSEQNUMVLD0_out; + wire PCIERQSEQNUMVLD1_out; + wire PCIERQTAGVLD0_out; + wire PCIERQTAGVLD1_out; + wire PIPERX00POLARITY_out; + wire PIPERX01POLARITY_out; + wire PIPERX02POLARITY_out; + wire PIPERX03POLARITY_out; + wire PIPERX04POLARITY_out; + wire PIPERX05POLARITY_out; + wire PIPERX06POLARITY_out; + wire PIPERX07POLARITY_out; + wire PIPERX08POLARITY_out; + wire PIPERX09POLARITY_out; + wire PIPERX10POLARITY_out; + wire PIPERX11POLARITY_out; + wire PIPERX12POLARITY_out; + wire PIPERX13POLARITY_out; + wire PIPERX14POLARITY_out; + wire PIPERX15POLARITY_out; + wire PIPETX00COMPLIANCE_out; + wire PIPETX00DATAVALID_out; + wire PIPETX00ELECIDLE_out; + wire PIPETX00STARTBLOCK_out; + wire PIPETX01COMPLIANCE_out; + wire PIPETX01DATAVALID_out; + wire PIPETX01ELECIDLE_out; + wire PIPETX01STARTBLOCK_out; + wire PIPETX02COMPLIANCE_out; + wire PIPETX02DATAVALID_out; + wire PIPETX02ELECIDLE_out; + wire PIPETX02STARTBLOCK_out; + wire PIPETX03COMPLIANCE_out; + wire PIPETX03DATAVALID_out; + wire PIPETX03ELECIDLE_out; + wire PIPETX03STARTBLOCK_out; + wire PIPETX04COMPLIANCE_out; + wire PIPETX04DATAVALID_out; + wire PIPETX04ELECIDLE_out; + wire PIPETX04STARTBLOCK_out; + wire PIPETX05COMPLIANCE_out; + wire PIPETX05DATAVALID_out; + wire PIPETX05ELECIDLE_out; + wire PIPETX05STARTBLOCK_out; + wire PIPETX06COMPLIANCE_out; + wire PIPETX06DATAVALID_out; + wire PIPETX06ELECIDLE_out; + wire PIPETX06STARTBLOCK_out; + wire PIPETX07COMPLIANCE_out; + wire PIPETX07DATAVALID_out; + wire PIPETX07ELECIDLE_out; + wire PIPETX07STARTBLOCK_out; + wire PIPETX08COMPLIANCE_out; + wire PIPETX08DATAVALID_out; + wire PIPETX08ELECIDLE_out; + wire PIPETX08STARTBLOCK_out; + wire PIPETX09COMPLIANCE_out; + wire PIPETX09DATAVALID_out; + wire PIPETX09ELECIDLE_out; + wire PIPETX09STARTBLOCK_out; + wire PIPETX10COMPLIANCE_out; + wire PIPETX10DATAVALID_out; + wire PIPETX10ELECIDLE_out; + wire PIPETX10STARTBLOCK_out; + wire PIPETX11COMPLIANCE_out; + wire PIPETX11DATAVALID_out; + wire PIPETX11ELECIDLE_out; + wire PIPETX11STARTBLOCK_out; + wire PIPETX12COMPLIANCE_out; + wire PIPETX12DATAVALID_out; + wire PIPETX12ELECIDLE_out; + wire PIPETX12STARTBLOCK_out; + wire PIPETX13COMPLIANCE_out; + wire PIPETX13DATAVALID_out; + wire PIPETX13ELECIDLE_out; + wire PIPETX13STARTBLOCK_out; + wire PIPETX14COMPLIANCE_out; + wire PIPETX14DATAVALID_out; + wire PIPETX14ELECIDLE_out; + wire PIPETX14STARTBLOCK_out; + wire PIPETX15COMPLIANCE_out; + wire PIPETX15DATAVALID_out; + wire PIPETX15ELECIDLE_out; + wire PIPETX15STARTBLOCK_out; + wire PIPETXDEEMPH_out; + wire PIPETXRCVRDET_out; + wire PIPETXRESET_out; + wire PIPETXSWING_out; + wire PLEQINPROGRESS_out; + wire PLGEN34EQMISMATCH_out; + wire PMVOUT_out; + wire [11:0] CFGFCCPLD_out; + wire [11:0] CFGFCNPD_out; + wire [11:0] CFGFCPD_out; + wire [11:0] CFGFUNCTIONPOWERSTATE_out; + wire [11:0] CFGINTERRUPTMSIMMENABLE_out; + wire [11:0] CFGTPHRAMADDRESS_out; + wire [11:0] CFGTPHSTMODE_out; + wire [127:0] MIREPLAYRAMWRITEDATA0_out; + wire [127:0] MIREPLAYRAMWRITEDATA1_out; + wire [129:0] DBGCCIXOUT_out; + wire [12:0] CFGMSIXRAMADDRESS_out; + wire [143:0] MIRXCOMPLETIONRAMWRITEDATA0_out; + wire [143:0] MIRXCOMPLETIONRAMWRITEDATA1_out; + wire [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0_out; + wire [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1_out; + wire [15:0] CFGFUNCTIONSTATUS_out; + wire [15:0] DRPDO_out; + wire [1:0] CFGCURRENTSPEED_out; + wire [1:0] CFGLINKPOWERSTATE_out; + wire [1:0] CFGMAXPAYLOAD_out; + wire [1:0] CFGOBFFENABLE_out; + wire [1:0] CFGPHYLINKSTATUS_out; + wire [1:0] CFGRXPMSTATE_out; + wire [1:0] CFGTXPMSTATE_out; + wire [1:0] MIRXCOMPLETIONRAMREADENABLE0_out; + wire [1:0] MIRXCOMPLETIONRAMREADENABLE1_out; + wire [1:0] MIRXCOMPLETIONRAMWRITEENABLE0_out; + wire [1:0] MIRXCOMPLETIONRAMWRITEENABLE1_out; + wire [1:0] PIPERX00EQCONTROL_out; + wire [1:0] PIPERX01EQCONTROL_out; + wire [1:0] PIPERX02EQCONTROL_out; + wire [1:0] PIPERX03EQCONTROL_out; + wire [1:0] PIPERX04EQCONTROL_out; + wire [1:0] PIPERX05EQCONTROL_out; + wire [1:0] PIPERX06EQCONTROL_out; + wire [1:0] PIPERX07EQCONTROL_out; + wire [1:0] PIPERX08EQCONTROL_out; + wire [1:0] PIPERX09EQCONTROL_out; + wire [1:0] PIPERX10EQCONTROL_out; + wire [1:0] PIPERX11EQCONTROL_out; + wire [1:0] PIPERX12EQCONTROL_out; + wire [1:0] PIPERX13EQCONTROL_out; + wire [1:0] PIPERX14EQCONTROL_out; + wire [1:0] PIPERX15EQCONTROL_out; + wire [1:0] PIPETX00CHARISK_out; + wire [1:0] PIPETX00EQCONTROL_out; + wire [1:0] PIPETX00POWERDOWN_out; + wire [1:0] PIPETX00SYNCHEADER_out; + wire [1:0] PIPETX01CHARISK_out; + wire [1:0] PIPETX01EQCONTROL_out; + wire [1:0] PIPETX01POWERDOWN_out; + wire [1:0] PIPETX01SYNCHEADER_out; + wire [1:0] PIPETX02CHARISK_out; + wire [1:0] PIPETX02EQCONTROL_out; + wire [1:0] PIPETX02POWERDOWN_out; + wire [1:0] PIPETX02SYNCHEADER_out; + wire [1:0] PIPETX03CHARISK_out; + wire [1:0] PIPETX03EQCONTROL_out; + wire [1:0] PIPETX03POWERDOWN_out; + wire [1:0] PIPETX03SYNCHEADER_out; + wire [1:0] PIPETX04CHARISK_out; + wire [1:0] PIPETX04EQCONTROL_out; + wire [1:0] PIPETX04POWERDOWN_out; + wire [1:0] PIPETX04SYNCHEADER_out; + wire [1:0] PIPETX05CHARISK_out; + wire [1:0] PIPETX05EQCONTROL_out; + wire [1:0] PIPETX05POWERDOWN_out; + wire [1:0] PIPETX05SYNCHEADER_out; + wire [1:0] PIPETX06CHARISK_out; + wire [1:0] PIPETX06EQCONTROL_out; + wire [1:0] PIPETX06POWERDOWN_out; + wire [1:0] PIPETX06SYNCHEADER_out; + wire [1:0] PIPETX07CHARISK_out; + wire [1:0] PIPETX07EQCONTROL_out; + wire [1:0] PIPETX07POWERDOWN_out; + wire [1:0] PIPETX07SYNCHEADER_out; + wire [1:0] PIPETX08CHARISK_out; + wire [1:0] PIPETX08EQCONTROL_out; + wire [1:0] PIPETX08POWERDOWN_out; + wire [1:0] PIPETX08SYNCHEADER_out; + wire [1:0] PIPETX09CHARISK_out; + wire [1:0] PIPETX09EQCONTROL_out; + wire [1:0] PIPETX09POWERDOWN_out; + wire [1:0] PIPETX09SYNCHEADER_out; + wire [1:0] PIPETX10CHARISK_out; + wire [1:0] PIPETX10EQCONTROL_out; + wire [1:0] PIPETX10POWERDOWN_out; + wire [1:0] PIPETX10SYNCHEADER_out; + wire [1:0] PIPETX11CHARISK_out; + wire [1:0] PIPETX11EQCONTROL_out; + wire [1:0] PIPETX11POWERDOWN_out; + wire [1:0] PIPETX11SYNCHEADER_out; + wire [1:0] PIPETX12CHARISK_out; + wire [1:0] PIPETX12EQCONTROL_out; + wire [1:0] PIPETX12POWERDOWN_out; + wire [1:0] PIPETX12SYNCHEADER_out; + wire [1:0] PIPETX13CHARISK_out; + wire [1:0] PIPETX13EQCONTROL_out; + wire [1:0] PIPETX13POWERDOWN_out; + wire [1:0] PIPETX13SYNCHEADER_out; + wire [1:0] PIPETX14CHARISK_out; + wire [1:0] PIPETX14EQCONTROL_out; + wire [1:0] PIPETX14POWERDOWN_out; + wire [1:0] PIPETX14SYNCHEADER_out; + wire [1:0] PIPETX15CHARISK_out; + wire [1:0] PIPETX15EQCONTROL_out; + wire [1:0] PIPETX15POWERDOWN_out; + wire [1:0] PIPETX15SYNCHEADER_out; + wire [1:0] PIPETXRATE_out; + wire [1:0] PLEQPHASE_out; + wire [23:0] USERSPAREOUT_out; + wire [255:0] DBGDATA0OUT_out; + wire [255:0] DBGDATA1OUT_out; + wire [255:0] MAXISCQTDATA_out; + wire [255:0] MAXISRCTDATA_out; + wire [2:0] CFGMAXREADREQ_out; + wire [2:0] CFGNEGOTIATEDWIDTH_out; + wire [2:0] PIPETXMARGIN_out; + wire [31:0] CFGEXTWRITEDATA_out; + wire [31:0] CFGINTERRUPTMSIDATA_out; + wire [31:0] CFGMGMTREADDATA_out; + wire [31:0] CONFRESPRDATA_out; + wire [31:0] DBGCTRL0OUT_out; + wire [31:0] DBGCTRL1OUT_out; + wire [31:0] PIPETX00DATA_out; + wire [31:0] PIPETX01DATA_out; + wire [31:0] PIPETX02DATA_out; + wire [31:0] PIPETX03DATA_out; + wire [31:0] PIPETX04DATA_out; + wire [31:0] PIPETX05DATA_out; + wire [31:0] PIPETX06DATA_out; + wire [31:0] PIPETX07DATA_out; + wire [31:0] PIPETX08DATA_out; + wire [31:0] PIPETX09DATA_out; + wire [31:0] PIPETX10DATA_out; + wire [31:0] PIPETX11DATA_out; + wire [31:0] PIPETX12DATA_out; + wire [31:0] PIPETX13DATA_out; + wire [31:0] PIPETX14DATA_out; + wire [31:0] PIPETX15DATA_out; + wire [35:0] CFGMSIXRAMWRITEDATA_out; + wire [35:0] CFGTPHRAMWRITEDATA_out; + wire [3:0] CFGEXTWRITEBYTEENABLE_out; + wire [3:0] CFGFLRINPROCESS_out; + wire [3:0] CFGINTERRUPTMSIENABLE_out; + wire [3:0] CFGINTERRUPTMSIXENABLE_out; + wire [3:0] CFGINTERRUPTMSIXMASK_out; + wire [3:0] CFGMSIXRAMWRITEBYTEENABLE_out; + wire [3:0] CFGRCBSTATUS_out; + wire [3:0] CFGTPHRAMWRITEBYTEENABLE_out; + wire [3:0] CFGTPHREQUESTERENABLE_out; + wire [3:0] PCIERQTAGAV_out; + wire [3:0] PCIETFCNPDAV_out; + wire [3:0] PCIETFCNPHAV_out; + wire [3:0] PIPERXEQLPTXPRESET_out; + wire [3:0] SAXISCCTREADY_out; + wire [3:0] SAXISRQTREADY_out; + wire [45:0] MAXISCCIXRXTUSER_out; + wire [4:0] CFGLOCALERROROUT_out; + wire [4:0] CFGMSGRECEIVEDTYPE_out; + wire [5:0] CFGLTSSMSTATE_out; + wire [5:0] PCIECQNPREQCOUNT_out; + wire [5:0] PCIERQSEQNUM0_out; + wire [5:0] PCIERQSEQNUM1_out; + wire [5:0] PIPERXEQLPLFFS_out; + wire [5:0] PIPETX00EQDEEMPH_out; + wire [5:0] PIPETX01EQDEEMPH_out; + wire [5:0] PIPETX02EQDEEMPH_out; + wire [5:0] PIPETX03EQDEEMPH_out; + wire [5:0] PIPETX04EQDEEMPH_out; + wire [5:0] PIPETX05EQDEEMPH_out; + wire [5:0] PIPETX06EQDEEMPH_out; + wire [5:0] PIPETX07EQDEEMPH_out; + wire [5:0] PIPETX08EQDEEMPH_out; + wire [5:0] PIPETX09EQDEEMPH_out; + wire [5:0] PIPETX10EQDEEMPH_out; + wire [5:0] PIPETX11EQDEEMPH_out; + wire [5:0] PIPETX12EQDEEMPH_out; + wire [5:0] PIPETX13EQDEEMPH_out; + wire [5:0] PIPETX14EQDEEMPH_out; + wire [5:0] PIPETX15EQDEEMPH_out; + wire [74:0] MAXISRCTUSER_out; + wire [7:0] AXIUSEROUT_out; + wire [7:0] CFGBUSNUMBER_out; + wire [7:0] CFGEXTFUNCTIONNUMBER_out; + wire [7:0] CFGFCCPLH_out; + wire [7:0] CFGFCNPH_out; + wire [7:0] CFGFCPH_out; + wire [7:0] CFGMSGRECEIVEDDATA_out; + wire [7:0] MAXISCQTKEEP_out; + wire [7:0] MAXISRCTKEEP_out; + wire [7:0] PCIERQTAG0_out; + wire [7:0] PCIERQTAG1_out; + wire [87:0] MAXISCQTUSER_out; + wire [8:0] MIREPLAYRAMADDRESS0_out; + wire [8:0] MIREPLAYRAMADDRESS1_out; + wire [8:0] MIRXCOMPLETIONRAMREADADDRESS0_out; + wire [8:0] MIRXCOMPLETIONRAMREADADDRESS1_out; + wire [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0_out; + wire [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1_out; + wire [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0_out; + wire [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1_out; + wire [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out; + wire [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out; + wire [9:0] CFGEXTREGISTERNUMBER_out; + + wire CCIXOPTIMIZEDTLPTXANDRXENABLE_in; + wire CCIXRXCORRECTABLEERRORDETECTED_in; + wire CCIXRXFIFOOVERFLOW_in; + wire CCIXRXTLPFORWARDED0_in; + wire CCIXRXTLPFORWARDED1_in; + wire CCIXRXUNCORRECTABLEERRORDETECTED_in; + wire CFGCONFIGSPACEENABLE_in; + wire CFGERRCORIN_in; + wire CFGERRUNCORIN_in; + wire CFGEXTREADDATAVALID_in; + wire CFGFCVCSEL_in; + wire CFGHOTRESETIN_in; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in; + wire CFGINTERRUPTMSITPHPRESENT_in; + wire CFGINTERRUPTMSIXINT_in; + wire CFGLINKTRAININGENABLE_in; + wire CFGMGMTDEBUGACCESS_in; + wire CFGMGMTREAD_in; + wire CFGMGMTWRITE_in; + wire CFGMSGTRANSMIT_in; + wire CFGPMASPML1ENTRYREJECT_in; + wire CFGPMASPMTXL0SENTRYDISABLE_in; + wire CFGPOWERSTATECHANGEACK_in; + wire CFGREQPMTRANSITIONL23READY_in; + wire CFGVFFLRDONE_in; + wire CONFMCAPREQUESTBYCONF_in; + wire CONFREQVALID_in; + wire CORECLKCCIX_in; + wire CORECLKMIREPLAYRAM0_in; + wire CORECLKMIREPLAYRAM1_in; + wire CORECLKMIRXCOMPLETIONRAM0_in; + wire CORECLKMIRXCOMPLETIONRAM1_in; + wire CORECLKMIRXPOSTEDREQUESTRAM0_in; + wire CORECLKMIRXPOSTEDREQUESTRAM1_in; + wire CORECLK_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire MCAPCLK_in; + wire MCAPPERST0B_in; + wire MCAPPERST1B_in; + wire MGMTRESETN_in; + wire MGMTSTICKYRESETN_in; + wire PCIECQNPUSERCREDITRCVD_in; + wire PCIECQPIPELINEEMPTY_in; + wire PCIEPOSTEDREQDELIVERED_in; + wire PIPECLKEN_in; + wire PIPECLK_in; + wire PIPERESETN_in; + wire PIPERX00DATAVALID_in; + wire PIPERX00ELECIDLE_in; + wire PIPERX00EQDONE_in; + wire PIPERX00EQLPADAPTDONE_in; + wire PIPERX00EQLPLFFSSEL_in; + wire PIPERX00PHYSTATUS_in; + wire PIPERX00VALID_in; + wire PIPERX01DATAVALID_in; + wire PIPERX01ELECIDLE_in; + wire PIPERX01EQDONE_in; + wire PIPERX01EQLPADAPTDONE_in; + wire PIPERX01EQLPLFFSSEL_in; + wire PIPERX01PHYSTATUS_in; + wire PIPERX01VALID_in; + wire PIPERX02DATAVALID_in; + wire PIPERX02ELECIDLE_in; + wire PIPERX02EQDONE_in; + wire PIPERX02EQLPADAPTDONE_in; + wire PIPERX02EQLPLFFSSEL_in; + wire PIPERX02PHYSTATUS_in; + wire PIPERX02VALID_in; + wire PIPERX03DATAVALID_in; + wire PIPERX03ELECIDLE_in; + wire PIPERX03EQDONE_in; + wire PIPERX03EQLPADAPTDONE_in; + wire PIPERX03EQLPLFFSSEL_in; + wire PIPERX03PHYSTATUS_in; + wire PIPERX03VALID_in; + wire PIPERX04DATAVALID_in; + wire PIPERX04ELECIDLE_in; + wire PIPERX04EQDONE_in; + wire PIPERX04EQLPADAPTDONE_in; + wire PIPERX04EQLPLFFSSEL_in; + wire PIPERX04PHYSTATUS_in; + wire PIPERX04VALID_in; + wire PIPERX05DATAVALID_in; + wire PIPERX05ELECIDLE_in; + wire PIPERX05EQDONE_in; + wire PIPERX05EQLPADAPTDONE_in; + wire PIPERX05EQLPLFFSSEL_in; + wire PIPERX05PHYSTATUS_in; + wire PIPERX05VALID_in; + wire PIPERX06DATAVALID_in; + wire PIPERX06ELECIDLE_in; + wire PIPERX06EQDONE_in; + wire PIPERX06EQLPADAPTDONE_in; + wire PIPERX06EQLPLFFSSEL_in; + wire PIPERX06PHYSTATUS_in; + wire PIPERX06VALID_in; + wire PIPERX07DATAVALID_in; + wire PIPERX07ELECIDLE_in; + wire PIPERX07EQDONE_in; + wire PIPERX07EQLPADAPTDONE_in; + wire PIPERX07EQLPLFFSSEL_in; + wire PIPERX07PHYSTATUS_in; + wire PIPERX07VALID_in; + wire PIPERX08DATAVALID_in; + wire PIPERX08ELECIDLE_in; + wire PIPERX08EQDONE_in; + wire PIPERX08EQLPADAPTDONE_in; + wire PIPERX08EQLPLFFSSEL_in; + wire PIPERX08PHYSTATUS_in; + wire PIPERX08VALID_in; + wire PIPERX09DATAVALID_in; + wire PIPERX09ELECIDLE_in; + wire PIPERX09EQDONE_in; + wire PIPERX09EQLPADAPTDONE_in; + wire PIPERX09EQLPLFFSSEL_in; + wire PIPERX09PHYSTATUS_in; + wire PIPERX09VALID_in; + wire PIPERX10DATAVALID_in; + wire PIPERX10ELECIDLE_in; + wire PIPERX10EQDONE_in; + wire PIPERX10EQLPADAPTDONE_in; + wire PIPERX10EQLPLFFSSEL_in; + wire PIPERX10PHYSTATUS_in; + wire PIPERX10VALID_in; + wire PIPERX11DATAVALID_in; + wire PIPERX11ELECIDLE_in; + wire PIPERX11EQDONE_in; + wire PIPERX11EQLPADAPTDONE_in; + wire PIPERX11EQLPLFFSSEL_in; + wire PIPERX11PHYSTATUS_in; + wire PIPERX11VALID_in; + wire PIPERX12DATAVALID_in; + wire PIPERX12ELECIDLE_in; + wire PIPERX12EQDONE_in; + wire PIPERX12EQLPADAPTDONE_in; + wire PIPERX12EQLPLFFSSEL_in; + wire PIPERX12PHYSTATUS_in; + wire PIPERX12VALID_in; + wire PIPERX13DATAVALID_in; + wire PIPERX13ELECIDLE_in; + wire PIPERX13EQDONE_in; + wire PIPERX13EQLPADAPTDONE_in; + wire PIPERX13EQLPLFFSSEL_in; + wire PIPERX13PHYSTATUS_in; + wire PIPERX13VALID_in; + wire PIPERX14DATAVALID_in; + wire PIPERX14ELECIDLE_in; + wire PIPERX14EQDONE_in; + wire PIPERX14EQLPADAPTDONE_in; + wire PIPERX14EQLPLFFSSEL_in; + wire PIPERX14PHYSTATUS_in; + wire PIPERX14VALID_in; + wire PIPERX15DATAVALID_in; + wire PIPERX15ELECIDLE_in; + wire PIPERX15EQDONE_in; + wire PIPERX15EQLPADAPTDONE_in; + wire PIPERX15EQLPLFFSSEL_in; + wire PIPERX15PHYSTATUS_in; + wire PIPERX15VALID_in; + wire PIPETX00EQDONE_in; + wire PIPETX01EQDONE_in; + wire PIPETX02EQDONE_in; + wire PIPETX03EQDONE_in; + wire PIPETX04EQDONE_in; + wire PIPETX05EQDONE_in; + wire PIPETX06EQDONE_in; + wire PIPETX07EQDONE_in; + wire PIPETX08EQDONE_in; + wire PIPETX09EQDONE_in; + wire PIPETX10EQDONE_in; + wire PIPETX11EQDONE_in; + wire PIPETX12EQDONE_in; + wire PIPETX13EQDONE_in; + wire PIPETX14EQDONE_in; + wire PIPETX15EQDONE_in; + wire PLEQRESETEIEOSCOUNT_in; + wire PLGEN2UPSTREAMPREFERDEEMPH_in; + wire PLGEN34REDOEQSPEED_in; + wire PLGEN34REDOEQUALIZATION_in; + wire PMVENABLEN_in; + wire RESETN_in; + wire SAXISCCIXTXTVALID_in; + wire SAXISCCTLAST_in; + wire SAXISCCTVALID_in; + wire SAXISRQTLAST_in; + wire SAXISRQTVALID_in; + wire SCANENABLEN_in; + wire SCANMODEN_in; + wire USERCLK2_in; + wire USERCLKEN_in; + wire USERCLK_in; + wire [11:0] MIRXCOMPLETIONRAMERRCOR_in; + wire [11:0] MIRXCOMPLETIONRAMERRUNCOR_in; + wire [127:0] MIREPLAYRAMREADDATA0_in; + wire [127:0] MIREPLAYRAMREADDATA1_in; + wire [129:0] SCANIN_in; + wire [143:0] MIRXCOMPLETIONRAMREADDATA0_in; + wire [143:0] MIRXCOMPLETIONRAMREADDATA1_in; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA0_in; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA1_in; + wire [15:0] CFGDEVIDPF0_in; + wire [15:0] CFGDEVIDPF1_in; + wire [15:0] CFGDEVIDPF2_in; + wire [15:0] CFGDEVIDPF3_in; + wire [15:0] CFGSUBSYSIDPF0_in; + wire [15:0] CFGSUBSYSIDPF1_in; + wire [15:0] CFGSUBSYSIDPF2_in; + wire [15:0] CFGSUBSYSIDPF3_in; + wire [15:0] CFGSUBSYSVENDID_in; + wire [15:0] CFGVENDID_in; + wire [15:0] DRPDI_in; + wire [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPETX00EQCOEFF_in; + wire [17:0] PIPETX01EQCOEFF_in; + wire [17:0] PIPETX02EQCOEFF_in; + wire [17:0] PIPETX03EQCOEFF_in; + wire [17:0] PIPETX04EQCOEFF_in; + wire [17:0] PIPETX05EQCOEFF_in; + wire [17:0] PIPETX06EQCOEFF_in; + wire [17:0] PIPETX07EQCOEFF_in; + wire [17:0] PIPETX08EQCOEFF_in; + wire [17:0] PIPETX09EQCOEFF_in; + wire [17:0] PIPETX10EQCOEFF_in; + wire [17:0] PIPETX11EQCOEFF_in; + wire [17:0] PIPETX12EQCOEFF_in; + wire [17:0] PIPETX13EQCOEFF_in; + wire [17:0] PIPETX14EQCOEFF_in; + wire [17:0] PIPETX15EQCOEFF_in; + wire [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in; + wire [1:0] CFGINTERRUPTMSISELECT_in; + wire [1:0] CFGINTERRUPTMSITPHTYPE_in; + wire [1:0] CFGINTERRUPTMSIXVECPENDING_in; + wire [1:0] CONFREQTYPE_in; + wire [1:0] PCIECOMPLDELIVERED_in; + wire [1:0] PCIECQNPREQ_in; + wire [1:0] PIPERX00CHARISK_in; + wire [1:0] PIPERX00STARTBLOCK_in; + wire [1:0] PIPERX00SYNCHEADER_in; + wire [1:0] PIPERX01CHARISK_in; + wire [1:0] PIPERX01STARTBLOCK_in; + wire [1:0] PIPERX01SYNCHEADER_in; + wire [1:0] PIPERX02CHARISK_in; + wire [1:0] PIPERX02STARTBLOCK_in; + wire [1:0] PIPERX02SYNCHEADER_in; + wire [1:0] PIPERX03CHARISK_in; + wire [1:0] PIPERX03STARTBLOCK_in; + wire [1:0] PIPERX03SYNCHEADER_in; + wire [1:0] PIPERX04CHARISK_in; + wire [1:0] PIPERX04STARTBLOCK_in; + wire [1:0] PIPERX04SYNCHEADER_in; + wire [1:0] PIPERX05CHARISK_in; + wire [1:0] PIPERX05STARTBLOCK_in; + wire [1:0] PIPERX05SYNCHEADER_in; + wire [1:0] PIPERX06CHARISK_in; + wire [1:0] PIPERX06STARTBLOCK_in; + wire [1:0] PIPERX06SYNCHEADER_in; + wire [1:0] PIPERX07CHARISK_in; + wire [1:0] PIPERX07STARTBLOCK_in; + wire [1:0] PIPERX07SYNCHEADER_in; + wire [1:0] PIPERX08CHARISK_in; + wire [1:0] PIPERX08STARTBLOCK_in; + wire [1:0] PIPERX08SYNCHEADER_in; + wire [1:0] PIPERX09CHARISK_in; + wire [1:0] PIPERX09STARTBLOCK_in; + wire [1:0] PIPERX09SYNCHEADER_in; + wire [1:0] PIPERX10CHARISK_in; + wire [1:0] PIPERX10STARTBLOCK_in; + wire [1:0] PIPERX10SYNCHEADER_in; + wire [1:0] PIPERX11CHARISK_in; + wire [1:0] PIPERX11STARTBLOCK_in; + wire [1:0] PIPERX11SYNCHEADER_in; + wire [1:0] PIPERX12CHARISK_in; + wire [1:0] PIPERX12STARTBLOCK_in; + wire [1:0] PIPERX12SYNCHEADER_in; + wire [1:0] PIPERX13CHARISK_in; + wire [1:0] PIPERX13STARTBLOCK_in; + wire [1:0] PIPERX13SYNCHEADER_in; + wire [1:0] PIPERX14CHARISK_in; + wire [1:0] PIPERX14STARTBLOCK_in; + wire [1:0] PIPERX14SYNCHEADER_in; + wire [1:0] PIPERX15CHARISK_in; + wire [1:0] PIPERX15STARTBLOCK_in; + wire [1:0] PIPERX15SYNCHEADER_in; + wire [1:0] PMVDIVIDE_in; + wire [21:0] MAXISCQTREADY_in; + wire [21:0] MAXISRCTREADY_in; + wire [255:0] SAXISCCIXTXTDATA_in; + wire [255:0] SAXISCCTDATA_in; + wire [255:0] SAXISRQTDATA_in; + wire [2:0] CFGDSFUNCTIONNUMBER_in; + wire [2:0] CFGFCSEL_in; + wire [2:0] CFGINTERRUPTMSIATTR_in; + wire [2:0] CFGMSGTRANSMITTYPE_in; + wire [2:0] PIPERX00STATUS_in; + wire [2:0] PIPERX01STATUS_in; + wire [2:0] PIPERX02STATUS_in; + wire [2:0] PIPERX03STATUS_in; + wire [2:0] PIPERX04STATUS_in; + wire [2:0] PIPERX05STATUS_in; + wire [2:0] PIPERX06STATUS_in; + wire [2:0] PIPERX07STATUS_in; + wire [2:0] PIPERX08STATUS_in; + wire [2:0] PIPERX09STATUS_in; + wire [2:0] PIPERX10STATUS_in; + wire [2:0] PIPERX11STATUS_in; + wire [2:0] PIPERX12STATUS_in; + wire [2:0] PIPERX13STATUS_in; + wire [2:0] PIPERX14STATUS_in; + wire [2:0] PIPERX15STATUS_in; + wire [2:0] PMVSELECT_in; + wire [31:0] CFGEXTREADDATA_in; + wire [31:0] CFGINTERRUPTMSIINT_in; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_in; + wire [31:0] CFGINTERRUPTMSIXDATA_in; + wire [31:0] CFGMGMTWRITEDATA_in; + wire [31:0] CFGMSGTRANSMITDATA_in; + wire [31:0] CONFREQDATA_in; + wire [31:0] PIPERX00DATA_in; + wire [31:0] PIPERX01DATA_in; + wire [31:0] PIPERX02DATA_in; + wire [31:0] PIPERX03DATA_in; + wire [31:0] PIPERX04DATA_in; + wire [31:0] PIPERX05DATA_in; + wire [31:0] PIPERX06DATA_in; + wire [31:0] PIPERX07DATA_in; + wire [31:0] PIPERX08DATA_in; + wire [31:0] PIPERX09DATA_in; + wire [31:0] PIPERX10DATA_in; + wire [31:0] PIPERX11DATA_in; + wire [31:0] PIPERX12DATA_in; + wire [31:0] PIPERX13DATA_in; + wire [31:0] PIPERX14DATA_in; + wire [31:0] PIPERX15DATA_in; + wire [31:0] USERSPAREIN_in; + wire [32:0] SAXISCCTUSER_in; + wire [35:0] CFGMSIXRAMREADDATA_in; + wire [35:0] CFGTPHRAMREADDATA_in; + wire [3:0] CFGFLRDONE_in; + wire [3:0] CFGINTERRUPTINT_in; + wire [3:0] CFGINTERRUPTPENDING_in; + wire [3:0] CFGMGMTBYTEENABLE_in; + wire [3:0] CONFREQREGNUM_in; + wire [45:0] SAXISCCIXTXTUSER_in; + wire [4:0] CFGDSDEVICENUMBER_in; + wire [5:0] CCIXRXTLPFORWARDEDLENGTH0_in; + wire [5:0] CCIXRXTLPFORWARDEDLENGTH1_in; + wire [5:0] DBGSEL0_in; + wire [5:0] DBGSEL1_in; + wire [5:0] MIREPLAYRAMERRCOR_in; + wire [5:0] MIREPLAYRAMERRUNCOR_in; + wire [5:0] MIRXPOSTEDREQUESTRAMERRCOR_in; + wire [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR_in; + wire [5:0] PIPEEQFS_in; + wire [5:0] PIPEEQLF_in; + wire [61:0] SAXISRQTUSER_in; + wire [63:0] CFGDSN_in; + wire [63:0] CFGINTERRUPTMSIXADDRESS_in; + wire [7:0] AXIUSERIN_in; + wire [7:0] CFGDSBUSNUMBER_in; + wire [7:0] CFGDSPORTNUMBER_in; + wire [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER_in; + wire [7:0] CFGINTERRUPTMSITPHSTTAG_in; + wire [7:0] CFGMGMTFUNCTIONNUMBER_in; + wire [7:0] CFGREVIDPF0_in; + wire [7:0] CFGREVIDPF1_in; + wire [7:0] CFGREVIDPF2_in; + wire [7:0] CFGREVIDPF3_in; + wire [7:0] CFGVFFLRFUNCNUM_in; + wire [7:0] PCIECOMPLDELIVEREDTAG0_in; + wire [7:0] PCIECOMPLDELIVEREDTAG1_in; + wire [7:0] SAXISCCTKEEP_in; + wire [7:0] SAXISRQTKEEP_in; + wire [9:0] CFGMGMTADDR_in; + wire [9:0] DRPADDR_in; + +`ifdef XIL_TIMING + wire CCIXOPTIMIZEDTLPTXANDRXENABLE_delay; + wire CCIXRXTLPFORWARDED0_delay; + wire CCIXRXTLPFORWARDED1_delay; + wire CFGCONFIGSPACEENABLE_delay; + wire CFGERRCORIN_delay; + wire CFGERRUNCORIN_delay; + wire CFGEXTREADDATAVALID_delay; + wire CFGFCVCSEL_delay; + wire CFGHOTRESETIN_delay; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; + wire CFGINTERRUPTMSITPHPRESENT_delay; + wire CFGINTERRUPTMSIXINT_delay; + wire CFGLINKTRAININGENABLE_delay; + wire CFGMGMTDEBUGACCESS_delay; + wire CFGMGMTREAD_delay; + wire CFGMGMTWRITE_delay; + wire CFGMSGTRANSMIT_delay; + wire CFGPMASPML1ENTRYREJECT_delay; + wire CFGPMASPMTXL0SENTRYDISABLE_delay; + wire CFGPOWERSTATECHANGEACK_delay; + wire CFGREQPMTRANSITIONL23READY_delay; + wire CFGVFFLRDONE_delay; + wire CONFMCAPREQUESTBYCONF_delay; + wire CONFREQVALID_delay; + wire CORECLK_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire PCIECQNPUSERCREDITRCVD_delay; + wire PCIECQPIPELINEEMPTY_delay; + wire PCIEPOSTEDREQDELIVERED_delay; + wire PIPECLK_delay; + wire PIPERX00DATAVALID_delay; + wire PIPERX00ELECIDLE_delay; + wire PIPERX00EQDONE_delay; + wire PIPERX00EQLPADAPTDONE_delay; + wire PIPERX00EQLPLFFSSEL_delay; + wire PIPERX00PHYSTATUS_delay; + wire PIPERX00VALID_delay; + wire PIPERX01DATAVALID_delay; + wire PIPERX01ELECIDLE_delay; + wire PIPERX01EQDONE_delay; + wire PIPERX01EQLPADAPTDONE_delay; + wire PIPERX01EQLPLFFSSEL_delay; + wire PIPERX01PHYSTATUS_delay; + wire PIPERX01VALID_delay; + wire PIPERX02DATAVALID_delay; + wire PIPERX02ELECIDLE_delay; + wire PIPERX02EQDONE_delay; + wire PIPERX02EQLPADAPTDONE_delay; + wire PIPERX02EQLPLFFSSEL_delay; + wire PIPERX02PHYSTATUS_delay; + wire PIPERX02VALID_delay; + wire PIPERX03DATAVALID_delay; + wire PIPERX03ELECIDLE_delay; + wire PIPERX03EQDONE_delay; + wire PIPERX03EQLPADAPTDONE_delay; + wire PIPERX03EQLPLFFSSEL_delay; + wire PIPERX03PHYSTATUS_delay; + wire PIPERX03VALID_delay; + wire PIPERX04DATAVALID_delay; + wire PIPERX04ELECIDLE_delay; + wire PIPERX04EQDONE_delay; + wire PIPERX04EQLPADAPTDONE_delay; + wire PIPERX04EQLPLFFSSEL_delay; + wire PIPERX04PHYSTATUS_delay; + wire PIPERX04VALID_delay; + wire PIPERX05DATAVALID_delay; + wire PIPERX05ELECIDLE_delay; + wire PIPERX05EQDONE_delay; + wire PIPERX05EQLPADAPTDONE_delay; + wire PIPERX05EQLPLFFSSEL_delay; + wire PIPERX05PHYSTATUS_delay; + wire PIPERX05VALID_delay; + wire PIPERX06DATAVALID_delay; + wire PIPERX06ELECIDLE_delay; + wire PIPERX06EQDONE_delay; + wire PIPERX06EQLPADAPTDONE_delay; + wire PIPERX06EQLPLFFSSEL_delay; + wire PIPERX06PHYSTATUS_delay; + wire PIPERX06VALID_delay; + wire PIPERX07DATAVALID_delay; + wire PIPERX07ELECIDLE_delay; + wire PIPERX07EQDONE_delay; + wire PIPERX07EQLPADAPTDONE_delay; + wire PIPERX07EQLPLFFSSEL_delay; + wire PIPERX07PHYSTATUS_delay; + wire PIPERX07VALID_delay; + wire PIPERX08DATAVALID_delay; + wire PIPERX08ELECIDLE_delay; + wire PIPERX08EQDONE_delay; + wire PIPERX08EQLPADAPTDONE_delay; + wire PIPERX08EQLPLFFSSEL_delay; + wire PIPERX08PHYSTATUS_delay; + wire PIPERX08VALID_delay; + wire PIPERX09DATAVALID_delay; + wire PIPERX09ELECIDLE_delay; + wire PIPERX09EQDONE_delay; + wire PIPERX09EQLPADAPTDONE_delay; + wire PIPERX09EQLPLFFSSEL_delay; + wire PIPERX09PHYSTATUS_delay; + wire PIPERX09VALID_delay; + wire PIPERX10DATAVALID_delay; + wire PIPERX10ELECIDLE_delay; + wire PIPERX10EQDONE_delay; + wire PIPERX10EQLPADAPTDONE_delay; + wire PIPERX10EQLPLFFSSEL_delay; + wire PIPERX10PHYSTATUS_delay; + wire PIPERX10VALID_delay; + wire PIPERX11DATAVALID_delay; + wire PIPERX11ELECIDLE_delay; + wire PIPERX11EQDONE_delay; + wire PIPERX11EQLPADAPTDONE_delay; + wire PIPERX11EQLPLFFSSEL_delay; + wire PIPERX11PHYSTATUS_delay; + wire PIPERX11VALID_delay; + wire PIPERX12DATAVALID_delay; + wire PIPERX12ELECIDLE_delay; + wire PIPERX12EQDONE_delay; + wire PIPERX12EQLPADAPTDONE_delay; + wire PIPERX12EQLPLFFSSEL_delay; + wire PIPERX12PHYSTATUS_delay; + wire PIPERX12VALID_delay; + wire PIPERX13DATAVALID_delay; + wire PIPERX13ELECIDLE_delay; + wire PIPERX13EQDONE_delay; + wire PIPERX13EQLPADAPTDONE_delay; + wire PIPERX13EQLPLFFSSEL_delay; + wire PIPERX13PHYSTATUS_delay; + wire PIPERX13VALID_delay; + wire PIPERX14DATAVALID_delay; + wire PIPERX14ELECIDLE_delay; + wire PIPERX14EQDONE_delay; + wire PIPERX14EQLPADAPTDONE_delay; + wire PIPERX14EQLPLFFSSEL_delay; + wire PIPERX14PHYSTATUS_delay; + wire PIPERX14VALID_delay; + wire PIPERX15DATAVALID_delay; + wire PIPERX15ELECIDLE_delay; + wire PIPERX15EQDONE_delay; + wire PIPERX15EQLPADAPTDONE_delay; + wire PIPERX15EQLPLFFSSEL_delay; + wire PIPERX15PHYSTATUS_delay; + wire PIPERX15VALID_delay; + wire PIPETX00EQDONE_delay; + wire PIPETX01EQDONE_delay; + wire PIPETX02EQDONE_delay; + wire PIPETX03EQDONE_delay; + wire PIPETX04EQDONE_delay; + wire PIPETX05EQDONE_delay; + wire PIPETX06EQDONE_delay; + wire PIPETX07EQDONE_delay; + wire PIPETX08EQDONE_delay; + wire PIPETX09EQDONE_delay; + wire PIPETX10EQDONE_delay; + wire PIPETX11EQDONE_delay; + wire PIPETX12EQDONE_delay; + wire PIPETX13EQDONE_delay; + wire PIPETX14EQDONE_delay; + wire PIPETX15EQDONE_delay; + wire PLGEN2UPSTREAMPREFERDEEMPH_delay; + wire PLGEN34REDOEQSPEED_delay; + wire PLGEN34REDOEQUALIZATION_delay; + wire SAXISCCIXTXTVALID_delay; + wire SAXISCCTLAST_delay; + wire SAXISCCTVALID_delay; + wire SAXISRQTLAST_delay; + wire SAXISRQTVALID_delay; + wire USERCLKEN_delay; + wire [11:0] MIRXCOMPLETIONRAMERRCOR_delay; + wire [11:0] MIRXCOMPLETIONRAMERRUNCOR_delay; + wire [127:0] MIREPLAYRAMREADDATA0_delay; + wire [127:0] MIREPLAYRAMREADDATA1_delay; + wire [143:0] MIRXCOMPLETIONRAMREADDATA0_delay; + wire [143:0] MIRXCOMPLETIONRAMREADDATA1_delay; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA0_delay; + wire [143:0] MIRXPOSTEDREQUESTRAMREADDATA1_delay; + wire [15:0] CFGDEVIDPF0_delay; + wire [15:0] CFGDEVIDPF1_delay; + wire [15:0] CFGDEVIDPF2_delay; + wire [15:0] CFGDEVIDPF3_delay; + wire [15:0] CFGSUBSYSIDPF0_delay; + wire [15:0] CFGSUBSYSIDPF1_delay; + wire [15:0] CFGSUBSYSIDPF2_delay; + wire [15:0] CFGSUBSYSIDPF3_delay; + wire [15:0] CFGSUBSYSVENDID_delay; + wire [15:0] CFGVENDID_delay; + wire [15:0] DRPDI_delay; + wire [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPETX00EQCOEFF_delay; + wire [17:0] PIPETX01EQCOEFF_delay; + wire [17:0] PIPETX02EQCOEFF_delay; + wire [17:0] PIPETX03EQCOEFF_delay; + wire [17:0] PIPETX04EQCOEFF_delay; + wire [17:0] PIPETX05EQCOEFF_delay; + wire [17:0] PIPETX06EQCOEFF_delay; + wire [17:0] PIPETX07EQCOEFF_delay; + wire [17:0] PIPETX08EQCOEFF_delay; + wire [17:0] PIPETX09EQCOEFF_delay; + wire [17:0] PIPETX10EQCOEFF_delay; + wire [17:0] PIPETX11EQCOEFF_delay; + wire [17:0] PIPETX12EQCOEFF_delay; + wire [17:0] PIPETX13EQCOEFF_delay; + wire [17:0] PIPETX14EQCOEFF_delay; + wire [17:0] PIPETX15EQCOEFF_delay; + wire [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay; + wire [1:0] CFGINTERRUPTMSISELECT_delay; + wire [1:0] CFGINTERRUPTMSITPHTYPE_delay; + wire [1:0] CFGINTERRUPTMSIXVECPENDING_delay; + wire [1:0] CONFREQTYPE_delay; + wire [1:0] PCIECOMPLDELIVERED_delay; + wire [1:0] PCIECQNPREQ_delay; + wire [1:0] PIPERX00CHARISK_delay; + wire [1:0] PIPERX00STARTBLOCK_delay; + wire [1:0] PIPERX00SYNCHEADER_delay; + wire [1:0] PIPERX01CHARISK_delay; + wire [1:0] PIPERX01STARTBLOCK_delay; + wire [1:0] PIPERX01SYNCHEADER_delay; + wire [1:0] PIPERX02CHARISK_delay; + wire [1:0] PIPERX02STARTBLOCK_delay; + wire [1:0] PIPERX02SYNCHEADER_delay; + wire [1:0] PIPERX03CHARISK_delay; + wire [1:0] PIPERX03STARTBLOCK_delay; + wire [1:0] PIPERX03SYNCHEADER_delay; + wire [1:0] PIPERX04CHARISK_delay; + wire [1:0] PIPERX04STARTBLOCK_delay; + wire [1:0] PIPERX04SYNCHEADER_delay; + wire [1:0] PIPERX05CHARISK_delay; + wire [1:0] PIPERX05STARTBLOCK_delay; + wire [1:0] PIPERX05SYNCHEADER_delay; + wire [1:0] PIPERX06CHARISK_delay; + wire [1:0] PIPERX06STARTBLOCK_delay; + wire [1:0] PIPERX06SYNCHEADER_delay; + wire [1:0] PIPERX07CHARISK_delay; + wire [1:0] PIPERX07STARTBLOCK_delay; + wire [1:0] PIPERX07SYNCHEADER_delay; + wire [1:0] PIPERX08CHARISK_delay; + wire [1:0] PIPERX08STARTBLOCK_delay; + wire [1:0] PIPERX08SYNCHEADER_delay; + wire [1:0] PIPERX09CHARISK_delay; + wire [1:0] PIPERX09STARTBLOCK_delay; + wire [1:0] PIPERX09SYNCHEADER_delay; + wire [1:0] PIPERX10CHARISK_delay; + wire [1:0] PIPERX10STARTBLOCK_delay; + wire [1:0] PIPERX10SYNCHEADER_delay; + wire [1:0] PIPERX11CHARISK_delay; + wire [1:0] PIPERX11STARTBLOCK_delay; + wire [1:0] PIPERX11SYNCHEADER_delay; + wire [1:0] PIPERX12CHARISK_delay; + wire [1:0] PIPERX12STARTBLOCK_delay; + wire [1:0] PIPERX12SYNCHEADER_delay; + wire [1:0] PIPERX13CHARISK_delay; + wire [1:0] PIPERX13STARTBLOCK_delay; + wire [1:0] PIPERX13SYNCHEADER_delay; + wire [1:0] PIPERX14CHARISK_delay; + wire [1:0] PIPERX14STARTBLOCK_delay; + wire [1:0] PIPERX14SYNCHEADER_delay; + wire [1:0] PIPERX15CHARISK_delay; + wire [1:0] PIPERX15STARTBLOCK_delay; + wire [1:0] PIPERX15SYNCHEADER_delay; + wire [21:0] MAXISCQTREADY_delay; + wire [21:0] MAXISRCTREADY_delay; + wire [255:0] SAXISCCIXTXTDATA_delay; + wire [255:0] SAXISCCTDATA_delay; + wire [255:0] SAXISRQTDATA_delay; + wire [2:0] CFGDSFUNCTIONNUMBER_delay; + wire [2:0] CFGFCSEL_delay; + wire [2:0] CFGINTERRUPTMSIATTR_delay; + wire [2:0] CFGMSGTRANSMITTYPE_delay; + wire [2:0] PIPERX00STATUS_delay; + wire [2:0] PIPERX01STATUS_delay; + wire [2:0] PIPERX02STATUS_delay; + wire [2:0] PIPERX03STATUS_delay; + wire [2:0] PIPERX04STATUS_delay; + wire [2:0] PIPERX05STATUS_delay; + wire [2:0] PIPERX06STATUS_delay; + wire [2:0] PIPERX07STATUS_delay; + wire [2:0] PIPERX08STATUS_delay; + wire [2:0] PIPERX09STATUS_delay; + wire [2:0] PIPERX10STATUS_delay; + wire [2:0] PIPERX11STATUS_delay; + wire [2:0] PIPERX12STATUS_delay; + wire [2:0] PIPERX13STATUS_delay; + wire [2:0] PIPERX14STATUS_delay; + wire [2:0] PIPERX15STATUS_delay; + wire [31:0] CFGEXTREADDATA_delay; + wire [31:0] CFGINTERRUPTMSIINT_delay; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_delay; + wire [31:0] CFGINTERRUPTMSIXDATA_delay; + wire [31:0] CFGMGMTWRITEDATA_delay; + wire [31:0] CFGMSGTRANSMITDATA_delay; + wire [31:0] CONFREQDATA_delay; + wire [31:0] PIPERX00DATA_delay; + wire [31:0] PIPERX01DATA_delay; + wire [31:0] PIPERX02DATA_delay; + wire [31:0] PIPERX03DATA_delay; + wire [31:0] PIPERX04DATA_delay; + wire [31:0] PIPERX05DATA_delay; + wire [31:0] PIPERX06DATA_delay; + wire [31:0] PIPERX07DATA_delay; + wire [31:0] PIPERX08DATA_delay; + wire [31:0] PIPERX09DATA_delay; + wire [31:0] PIPERX10DATA_delay; + wire [31:0] PIPERX11DATA_delay; + wire [31:0] PIPERX12DATA_delay; + wire [31:0] PIPERX13DATA_delay; + wire [31:0] PIPERX14DATA_delay; + wire [31:0] PIPERX15DATA_delay; + wire [31:0] USERSPAREIN_delay; + wire [32:0] SAXISCCTUSER_delay; + wire [35:0] CFGMSIXRAMREADDATA_delay; + wire [35:0] CFGTPHRAMREADDATA_delay; + wire [3:0] CFGFLRDONE_delay; + wire [3:0] CFGINTERRUPTINT_delay; + wire [3:0] CFGINTERRUPTPENDING_delay; + wire [3:0] CFGMGMTBYTEENABLE_delay; + wire [3:0] CONFREQREGNUM_delay; + wire [45:0] SAXISCCIXTXTUSER_delay; + wire [4:0] CFGDSDEVICENUMBER_delay; + wire [5:0] CCIXRXTLPFORWARDEDLENGTH0_delay; + wire [5:0] CCIXRXTLPFORWARDEDLENGTH1_delay; + wire [5:0] DBGSEL0_delay; + wire [5:0] DBGSEL1_delay; + wire [5:0] MIREPLAYRAMERRCOR_delay; + wire [5:0] MIREPLAYRAMERRUNCOR_delay; + wire [5:0] MIRXPOSTEDREQUESTRAMERRCOR_delay; + wire [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR_delay; + wire [5:0] PIPEEQFS_delay; + wire [5:0] PIPEEQLF_delay; + wire [61:0] SAXISRQTUSER_delay; + wire [63:0] CFGDSN_delay; + wire [63:0] CFGINTERRUPTMSIXADDRESS_delay; + wire [7:0] AXIUSERIN_delay; + wire [7:0] CFGDSBUSNUMBER_delay; + wire [7:0] CFGDSPORTNUMBER_delay; + wire [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER_delay; + wire [7:0] CFGINTERRUPTMSITPHSTTAG_delay; + wire [7:0] CFGMGMTFUNCTIONNUMBER_delay; + wire [7:0] CFGREVIDPF0_delay; + wire [7:0] CFGREVIDPF1_delay; + wire [7:0] CFGREVIDPF2_delay; + wire [7:0] CFGREVIDPF3_delay; + wire [7:0] CFGVFFLRFUNCNUM_delay; + wire [7:0] PCIECOMPLDELIVEREDTAG0_delay; + wire [7:0] PCIECOMPLDELIVEREDTAG1_delay; + wire [7:0] SAXISCCTKEEP_delay; + wire [7:0] SAXISRQTKEEP_delay; + wire [9:0] CFGMGMTADDR_delay; + wire [9:0] DRPADDR_delay; +`endif + + assign AXIUSEROUT = AXIUSEROUT_out; + assign CCIXTXCREDIT = CCIXTXCREDIT_out; + assign CFGBUSNUMBER = CFGBUSNUMBER_out; + assign CFGCURRENTSPEED = CFGCURRENTSPEED_out; + assign CFGERRCOROUT = CFGERRCOROUT_out; + assign CFGERRFATALOUT = CFGERRFATALOUT_out; + assign CFGERRNONFATALOUT = CFGERRNONFATALOUT_out; + assign CFGEXTFUNCTIONNUMBER = CFGEXTFUNCTIONNUMBER_out; + assign CFGEXTREADRECEIVED = CFGEXTREADRECEIVED_out; + assign CFGEXTREGISTERNUMBER = CFGEXTREGISTERNUMBER_out; + assign CFGEXTWRITEBYTEENABLE = CFGEXTWRITEBYTEENABLE_out; + assign CFGEXTWRITEDATA = CFGEXTWRITEDATA_out; + assign CFGEXTWRITERECEIVED = CFGEXTWRITERECEIVED_out; + assign CFGFCCPLD = CFGFCCPLD_out; + assign CFGFCCPLH = CFGFCCPLH_out; + assign CFGFCNPD = CFGFCNPD_out; + assign CFGFCNPH = CFGFCNPH_out; + assign CFGFCPD = CFGFCPD_out; + assign CFGFCPH = CFGFCPH_out; + assign CFGFLRINPROCESS = CFGFLRINPROCESS_out; + assign CFGFUNCTIONPOWERSTATE = CFGFUNCTIONPOWERSTATE_out; + assign CFGFUNCTIONSTATUS = CFGFUNCTIONSTATUS_out; + assign CFGHOTRESETOUT = CFGHOTRESETOUT_out; + assign CFGINTERRUPTMSIDATA = CFGINTERRUPTMSIDATA_out; + assign CFGINTERRUPTMSIENABLE = CFGINTERRUPTMSIENABLE_out; + assign CFGINTERRUPTMSIFAIL = CFGINTERRUPTMSIFAIL_out; + assign CFGINTERRUPTMSIMASKUPDATE = CFGINTERRUPTMSIMASKUPDATE_out; + assign CFGINTERRUPTMSIMMENABLE = CFGINTERRUPTMSIMMENABLE_out; + assign CFGINTERRUPTMSISENT = CFGINTERRUPTMSISENT_out; + assign CFGINTERRUPTMSIXENABLE = CFGINTERRUPTMSIXENABLE_out; + assign CFGINTERRUPTMSIXMASK = CFGINTERRUPTMSIXMASK_out; + assign CFGINTERRUPTMSIXVECPENDINGSTATUS = CFGINTERRUPTMSIXVECPENDINGSTATUS_out; + assign CFGINTERRUPTSENT = CFGINTERRUPTSENT_out; + assign CFGLINKPOWERSTATE = CFGLINKPOWERSTATE_out; + assign CFGLOCALERROROUT = CFGLOCALERROROUT_out; + assign CFGLOCALERRORVALID = CFGLOCALERRORVALID_out; + assign CFGLTRENABLE = CFGLTRENABLE_out; + assign CFGLTSSMSTATE = CFGLTSSMSTATE_out; + assign CFGMAXPAYLOAD = CFGMAXPAYLOAD_out; + assign CFGMAXREADREQ = CFGMAXREADREQ_out; + assign CFGMGMTREADDATA = CFGMGMTREADDATA_out; + assign CFGMGMTREADWRITEDONE = CFGMGMTREADWRITEDONE_out; + assign CFGMSGRECEIVED = CFGMSGRECEIVED_out; + assign CFGMSGRECEIVEDDATA = CFGMSGRECEIVEDDATA_out; + assign CFGMSGRECEIVEDTYPE = CFGMSGRECEIVEDTYPE_out; + assign CFGMSGTRANSMITDONE = CFGMSGTRANSMITDONE_out; + assign CFGMSIXRAMADDRESS = CFGMSIXRAMADDRESS_out; + assign CFGMSIXRAMREADENABLE = CFGMSIXRAMREADENABLE_out; + assign CFGMSIXRAMWRITEBYTEENABLE = CFGMSIXRAMWRITEBYTEENABLE_out; + assign CFGMSIXRAMWRITEDATA = CFGMSIXRAMWRITEDATA_out; + assign CFGNEGOTIATEDWIDTH = CFGNEGOTIATEDWIDTH_out; + assign CFGOBFFENABLE = CFGOBFFENABLE_out; + assign CFGPHYLINKDOWN = CFGPHYLINKDOWN_out; + assign CFGPHYLINKSTATUS = CFGPHYLINKSTATUS_out; + assign CFGPLSTATUSCHANGE = CFGPLSTATUSCHANGE_out; + assign CFGPOWERSTATECHANGEINTERRUPT = CFGPOWERSTATECHANGEINTERRUPT_out; + assign CFGRCBSTATUS = CFGRCBSTATUS_out; + assign CFGRXPMSTATE = CFGRXPMSTATE_out; + assign CFGTPHRAMADDRESS = CFGTPHRAMADDRESS_out; + assign CFGTPHRAMREADENABLE = CFGTPHRAMREADENABLE_out; + assign CFGTPHRAMWRITEBYTEENABLE = CFGTPHRAMWRITEBYTEENABLE_out; + assign CFGTPHRAMWRITEDATA = CFGTPHRAMWRITEDATA_out; + assign CFGTPHREQUESTERENABLE = CFGTPHREQUESTERENABLE_out; + assign CFGTPHSTMODE = CFGTPHSTMODE_out; + assign CFGTXPMSTATE = CFGTXPMSTATE_out; + assign CFGVC1ENABLE = CFGVC1ENABLE_out; + assign CFGVC1NEGOTIATIONPENDING = CFGVC1NEGOTIATIONPENDING_out; + assign CONFMCAPDESIGNSWITCH = CONFMCAPDESIGNSWITCH_out; + assign CONFMCAPEOS = CONFMCAPEOS_out; + assign CONFMCAPINUSEBYPCIE = CONFMCAPINUSEBYPCIE_out; + assign CONFREQREADY = CONFREQREADY_out; + assign CONFRESPRDATA = CONFRESPRDATA_out; + assign CONFRESPVALID = CONFRESPVALID_out; + assign DBGCCIXOUT = DBGCCIXOUT_out; + assign DBGCTRL0OUT = DBGCTRL0OUT_out; + assign DBGCTRL1OUT = DBGCTRL1OUT_out; + assign DBGDATA0OUT = DBGDATA0OUT_out; + assign DBGDATA1OUT = DBGDATA1OUT_out; + assign DRPDO = DRPDO_out; + assign DRPRDY = DRPRDY_out; + assign MAXISCCIXRXTUSER = MAXISCCIXRXTUSER_out; + assign MAXISCCIXRXTVALID = MAXISCCIXRXTVALID_out; + assign MAXISCQTDATA = MAXISCQTDATA_out; + assign MAXISCQTKEEP = MAXISCQTKEEP_out; + assign MAXISCQTLAST = MAXISCQTLAST_out; + assign MAXISCQTUSER = MAXISCQTUSER_out; + assign MAXISCQTVALID = MAXISCQTVALID_out; + assign MAXISRCTDATA = MAXISRCTDATA_out; + assign MAXISRCTKEEP = MAXISRCTKEEP_out; + assign MAXISRCTLAST = MAXISRCTLAST_out; + assign MAXISRCTUSER = MAXISRCTUSER_out; + assign MAXISRCTVALID = MAXISRCTVALID_out; + assign MIREPLAYRAMADDRESS0 = MIREPLAYRAMADDRESS0_out; + assign MIREPLAYRAMADDRESS1 = MIREPLAYRAMADDRESS1_out; + assign MIREPLAYRAMREADENABLE0 = MIREPLAYRAMREADENABLE0_out; + assign MIREPLAYRAMREADENABLE1 = MIREPLAYRAMREADENABLE1_out; + assign MIREPLAYRAMWRITEDATA0 = MIREPLAYRAMWRITEDATA0_out; + assign MIREPLAYRAMWRITEDATA1 = MIREPLAYRAMWRITEDATA1_out; + assign MIREPLAYRAMWRITEENABLE0 = MIREPLAYRAMWRITEENABLE0_out; + assign MIREPLAYRAMWRITEENABLE1 = MIREPLAYRAMWRITEENABLE1_out; + assign MIRXCOMPLETIONRAMREADADDRESS0 = MIRXCOMPLETIONRAMREADADDRESS0_out; + assign MIRXCOMPLETIONRAMREADADDRESS1 = MIRXCOMPLETIONRAMREADADDRESS1_out; + assign MIRXCOMPLETIONRAMREADENABLE0 = MIRXCOMPLETIONRAMREADENABLE0_out; + assign MIRXCOMPLETIONRAMREADENABLE1 = MIRXCOMPLETIONRAMREADENABLE1_out; + assign MIRXCOMPLETIONRAMWRITEADDRESS0 = MIRXCOMPLETIONRAMWRITEADDRESS0_out; + assign MIRXCOMPLETIONRAMWRITEADDRESS1 = MIRXCOMPLETIONRAMWRITEADDRESS1_out; + assign MIRXCOMPLETIONRAMWRITEDATA0 = MIRXCOMPLETIONRAMWRITEDATA0_out; + assign MIRXCOMPLETIONRAMWRITEDATA1 = MIRXCOMPLETIONRAMWRITEDATA1_out; + assign MIRXCOMPLETIONRAMWRITEENABLE0 = MIRXCOMPLETIONRAMWRITEENABLE0_out; + assign MIRXCOMPLETIONRAMWRITEENABLE1 = MIRXCOMPLETIONRAMWRITEENABLE1_out; + assign MIRXPOSTEDREQUESTRAMREADADDRESS0 = MIRXPOSTEDREQUESTRAMREADADDRESS0_out; + assign MIRXPOSTEDREQUESTRAMREADADDRESS1 = MIRXPOSTEDREQUESTRAMREADADDRESS1_out; + assign MIRXPOSTEDREQUESTRAMREADENABLE0 = MIRXPOSTEDREQUESTRAMREADENABLE0_out; + assign MIRXPOSTEDREQUESTRAMREADENABLE1 = MIRXPOSTEDREQUESTRAMREADENABLE1_out; + assign MIRXPOSTEDREQUESTRAMWRITEADDRESS0 = MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out; + assign MIRXPOSTEDREQUESTRAMWRITEADDRESS1 = MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out; + assign MIRXPOSTEDREQUESTRAMWRITEDATA0 = MIRXPOSTEDREQUESTRAMWRITEDATA0_out; + assign MIRXPOSTEDREQUESTRAMWRITEDATA1 = MIRXPOSTEDREQUESTRAMWRITEDATA1_out; + assign MIRXPOSTEDREQUESTRAMWRITEENABLE0 = MIRXPOSTEDREQUESTRAMWRITEENABLE0_out; + assign MIRXPOSTEDREQUESTRAMWRITEENABLE1 = MIRXPOSTEDREQUESTRAMWRITEENABLE1_out; + assign PCIECQNPREQCOUNT = PCIECQNPREQCOUNT_out; + assign PCIEPERST0B = PCIEPERST0B_out; + assign PCIEPERST1B = PCIEPERST1B_out; + assign PCIERQSEQNUM0 = PCIERQSEQNUM0_out; + assign PCIERQSEQNUM1 = PCIERQSEQNUM1_out; + assign PCIERQSEQNUMVLD0 = PCIERQSEQNUMVLD0_out; + assign PCIERQSEQNUMVLD1 = PCIERQSEQNUMVLD1_out; + assign PCIERQTAG0 = PCIERQTAG0_out; + assign PCIERQTAG1 = PCIERQTAG1_out; + assign PCIERQTAGAV = PCIERQTAGAV_out; + assign PCIERQTAGVLD0 = PCIERQTAGVLD0_out; + assign PCIERQTAGVLD1 = PCIERQTAGVLD1_out; + assign PCIETFCNPDAV = PCIETFCNPDAV_out; + assign PCIETFCNPHAV = PCIETFCNPHAV_out; + assign PIPERX00EQCONTROL = PIPERX00EQCONTROL_out; + assign PIPERX00POLARITY = PIPERX00POLARITY_out; + assign PIPERX01EQCONTROL = PIPERX01EQCONTROL_out; + assign PIPERX01POLARITY = PIPERX01POLARITY_out; + assign PIPERX02EQCONTROL = PIPERX02EQCONTROL_out; + assign PIPERX02POLARITY = PIPERX02POLARITY_out; + assign PIPERX03EQCONTROL = PIPERX03EQCONTROL_out; + assign PIPERX03POLARITY = PIPERX03POLARITY_out; + assign PIPERX04EQCONTROL = PIPERX04EQCONTROL_out; + assign PIPERX04POLARITY = PIPERX04POLARITY_out; + assign PIPERX05EQCONTROL = PIPERX05EQCONTROL_out; + assign PIPERX05POLARITY = PIPERX05POLARITY_out; + assign PIPERX06EQCONTROL = PIPERX06EQCONTROL_out; + assign PIPERX06POLARITY = PIPERX06POLARITY_out; + assign PIPERX07EQCONTROL = PIPERX07EQCONTROL_out; + assign PIPERX07POLARITY = PIPERX07POLARITY_out; + assign PIPERX08EQCONTROL = PIPERX08EQCONTROL_out; + assign PIPERX08POLARITY = PIPERX08POLARITY_out; + assign PIPERX09EQCONTROL = PIPERX09EQCONTROL_out; + assign PIPERX09POLARITY = PIPERX09POLARITY_out; + assign PIPERX10EQCONTROL = PIPERX10EQCONTROL_out; + assign PIPERX10POLARITY = PIPERX10POLARITY_out; + assign PIPERX11EQCONTROL = PIPERX11EQCONTROL_out; + assign PIPERX11POLARITY = PIPERX11POLARITY_out; + assign PIPERX12EQCONTROL = PIPERX12EQCONTROL_out; + assign PIPERX12POLARITY = PIPERX12POLARITY_out; + assign PIPERX13EQCONTROL = PIPERX13EQCONTROL_out; + assign PIPERX13POLARITY = PIPERX13POLARITY_out; + assign PIPERX14EQCONTROL = PIPERX14EQCONTROL_out; + assign PIPERX14POLARITY = PIPERX14POLARITY_out; + assign PIPERX15EQCONTROL = PIPERX15EQCONTROL_out; + assign PIPERX15POLARITY = PIPERX15POLARITY_out; + assign PIPERXEQLPLFFS = PIPERXEQLPLFFS_out; + assign PIPERXEQLPTXPRESET = PIPERXEQLPTXPRESET_out; + assign PIPETX00CHARISK = PIPETX00CHARISK_out; + assign PIPETX00COMPLIANCE = PIPETX00COMPLIANCE_out; + assign PIPETX00DATA = PIPETX00DATA_out; + assign PIPETX00DATAVALID = PIPETX00DATAVALID_out; + assign PIPETX00ELECIDLE = PIPETX00ELECIDLE_out; + assign PIPETX00EQCONTROL = PIPETX00EQCONTROL_out; + assign PIPETX00EQDEEMPH = PIPETX00EQDEEMPH_out; + assign PIPETX00POWERDOWN = PIPETX00POWERDOWN_out; + assign PIPETX00STARTBLOCK = PIPETX00STARTBLOCK_out; + assign PIPETX00SYNCHEADER = PIPETX00SYNCHEADER_out; + assign PIPETX01CHARISK = PIPETX01CHARISK_out; + assign PIPETX01COMPLIANCE = PIPETX01COMPLIANCE_out; + assign PIPETX01DATA = PIPETX01DATA_out; + assign PIPETX01DATAVALID = PIPETX01DATAVALID_out; + assign PIPETX01ELECIDLE = PIPETX01ELECIDLE_out; + assign PIPETX01EQCONTROL = PIPETX01EQCONTROL_out; + assign PIPETX01EQDEEMPH = PIPETX01EQDEEMPH_out; + assign PIPETX01POWERDOWN = PIPETX01POWERDOWN_out; + assign PIPETX01STARTBLOCK = PIPETX01STARTBLOCK_out; + assign PIPETX01SYNCHEADER = PIPETX01SYNCHEADER_out; + assign PIPETX02CHARISK = PIPETX02CHARISK_out; + assign PIPETX02COMPLIANCE = PIPETX02COMPLIANCE_out; + assign PIPETX02DATA = PIPETX02DATA_out; + assign PIPETX02DATAVALID = PIPETX02DATAVALID_out; + assign PIPETX02ELECIDLE = PIPETX02ELECIDLE_out; + assign PIPETX02EQCONTROL = PIPETX02EQCONTROL_out; + assign PIPETX02EQDEEMPH = PIPETX02EQDEEMPH_out; + assign PIPETX02POWERDOWN = PIPETX02POWERDOWN_out; + assign PIPETX02STARTBLOCK = PIPETX02STARTBLOCK_out; + assign PIPETX02SYNCHEADER = PIPETX02SYNCHEADER_out; + assign PIPETX03CHARISK = PIPETX03CHARISK_out; + assign PIPETX03COMPLIANCE = PIPETX03COMPLIANCE_out; + assign PIPETX03DATA = PIPETX03DATA_out; + assign PIPETX03DATAVALID = PIPETX03DATAVALID_out; + assign PIPETX03ELECIDLE = PIPETX03ELECIDLE_out; + assign PIPETX03EQCONTROL = PIPETX03EQCONTROL_out; + assign PIPETX03EQDEEMPH = PIPETX03EQDEEMPH_out; + assign PIPETX03POWERDOWN = PIPETX03POWERDOWN_out; + assign PIPETX03STARTBLOCK = PIPETX03STARTBLOCK_out; + assign PIPETX03SYNCHEADER = PIPETX03SYNCHEADER_out; + assign PIPETX04CHARISK = PIPETX04CHARISK_out; + assign PIPETX04COMPLIANCE = PIPETX04COMPLIANCE_out; + assign PIPETX04DATA = PIPETX04DATA_out; + assign PIPETX04DATAVALID = PIPETX04DATAVALID_out; + assign PIPETX04ELECIDLE = PIPETX04ELECIDLE_out; + assign PIPETX04EQCONTROL = PIPETX04EQCONTROL_out; + assign PIPETX04EQDEEMPH = PIPETX04EQDEEMPH_out; + assign PIPETX04POWERDOWN = PIPETX04POWERDOWN_out; + assign PIPETX04STARTBLOCK = PIPETX04STARTBLOCK_out; + assign PIPETX04SYNCHEADER = PIPETX04SYNCHEADER_out; + assign PIPETX05CHARISK = PIPETX05CHARISK_out; + assign PIPETX05COMPLIANCE = PIPETX05COMPLIANCE_out; + assign PIPETX05DATA = PIPETX05DATA_out; + assign PIPETX05DATAVALID = PIPETX05DATAVALID_out; + assign PIPETX05ELECIDLE = PIPETX05ELECIDLE_out; + assign PIPETX05EQCONTROL = PIPETX05EQCONTROL_out; + assign PIPETX05EQDEEMPH = PIPETX05EQDEEMPH_out; + assign PIPETX05POWERDOWN = PIPETX05POWERDOWN_out; + assign PIPETX05STARTBLOCK = PIPETX05STARTBLOCK_out; + assign PIPETX05SYNCHEADER = PIPETX05SYNCHEADER_out; + assign PIPETX06CHARISK = PIPETX06CHARISK_out; + assign PIPETX06COMPLIANCE = PIPETX06COMPLIANCE_out; + assign PIPETX06DATA = PIPETX06DATA_out; + assign PIPETX06DATAVALID = PIPETX06DATAVALID_out; + assign PIPETX06ELECIDLE = PIPETX06ELECIDLE_out; + assign PIPETX06EQCONTROL = PIPETX06EQCONTROL_out; + assign PIPETX06EQDEEMPH = PIPETX06EQDEEMPH_out; + assign PIPETX06POWERDOWN = PIPETX06POWERDOWN_out; + assign PIPETX06STARTBLOCK = PIPETX06STARTBLOCK_out; + assign PIPETX06SYNCHEADER = PIPETX06SYNCHEADER_out; + assign PIPETX07CHARISK = PIPETX07CHARISK_out; + assign PIPETX07COMPLIANCE = PIPETX07COMPLIANCE_out; + assign PIPETX07DATA = PIPETX07DATA_out; + assign PIPETX07DATAVALID = PIPETX07DATAVALID_out; + assign PIPETX07ELECIDLE = PIPETX07ELECIDLE_out; + assign PIPETX07EQCONTROL = PIPETX07EQCONTROL_out; + assign PIPETX07EQDEEMPH = PIPETX07EQDEEMPH_out; + assign PIPETX07POWERDOWN = PIPETX07POWERDOWN_out; + assign PIPETX07STARTBLOCK = PIPETX07STARTBLOCK_out; + assign PIPETX07SYNCHEADER = PIPETX07SYNCHEADER_out; + assign PIPETX08CHARISK = PIPETX08CHARISK_out; + assign PIPETX08COMPLIANCE = PIPETX08COMPLIANCE_out; + assign PIPETX08DATA = PIPETX08DATA_out; + assign PIPETX08DATAVALID = PIPETX08DATAVALID_out; + assign PIPETX08ELECIDLE = PIPETX08ELECIDLE_out; + assign PIPETX08EQCONTROL = PIPETX08EQCONTROL_out; + assign PIPETX08EQDEEMPH = PIPETX08EQDEEMPH_out; + assign PIPETX08POWERDOWN = PIPETX08POWERDOWN_out; + assign PIPETX08STARTBLOCK = PIPETX08STARTBLOCK_out; + assign PIPETX08SYNCHEADER = PIPETX08SYNCHEADER_out; + assign PIPETX09CHARISK = PIPETX09CHARISK_out; + assign PIPETX09COMPLIANCE = PIPETX09COMPLIANCE_out; + assign PIPETX09DATA = PIPETX09DATA_out; + assign PIPETX09DATAVALID = PIPETX09DATAVALID_out; + assign PIPETX09ELECIDLE = PIPETX09ELECIDLE_out; + assign PIPETX09EQCONTROL = PIPETX09EQCONTROL_out; + assign PIPETX09EQDEEMPH = PIPETX09EQDEEMPH_out; + assign PIPETX09POWERDOWN = PIPETX09POWERDOWN_out; + assign PIPETX09STARTBLOCK = PIPETX09STARTBLOCK_out; + assign PIPETX09SYNCHEADER = PIPETX09SYNCHEADER_out; + assign PIPETX10CHARISK = PIPETX10CHARISK_out; + assign PIPETX10COMPLIANCE = PIPETX10COMPLIANCE_out; + assign PIPETX10DATA = PIPETX10DATA_out; + assign PIPETX10DATAVALID = PIPETX10DATAVALID_out; + assign PIPETX10ELECIDLE = PIPETX10ELECIDLE_out; + assign PIPETX10EQCONTROL = PIPETX10EQCONTROL_out; + assign PIPETX10EQDEEMPH = PIPETX10EQDEEMPH_out; + assign PIPETX10POWERDOWN = PIPETX10POWERDOWN_out; + assign PIPETX10STARTBLOCK = PIPETX10STARTBLOCK_out; + assign PIPETX10SYNCHEADER = PIPETX10SYNCHEADER_out; + assign PIPETX11CHARISK = PIPETX11CHARISK_out; + assign PIPETX11COMPLIANCE = PIPETX11COMPLIANCE_out; + assign PIPETX11DATA = PIPETX11DATA_out; + assign PIPETX11DATAVALID = PIPETX11DATAVALID_out; + assign PIPETX11ELECIDLE = PIPETX11ELECIDLE_out; + assign PIPETX11EQCONTROL = PIPETX11EQCONTROL_out; + assign PIPETX11EQDEEMPH = PIPETX11EQDEEMPH_out; + assign PIPETX11POWERDOWN = PIPETX11POWERDOWN_out; + assign PIPETX11STARTBLOCK = PIPETX11STARTBLOCK_out; + assign PIPETX11SYNCHEADER = PIPETX11SYNCHEADER_out; + assign PIPETX12CHARISK = PIPETX12CHARISK_out; + assign PIPETX12COMPLIANCE = PIPETX12COMPLIANCE_out; + assign PIPETX12DATA = PIPETX12DATA_out; + assign PIPETX12DATAVALID = PIPETX12DATAVALID_out; + assign PIPETX12ELECIDLE = PIPETX12ELECIDLE_out; + assign PIPETX12EQCONTROL = PIPETX12EQCONTROL_out; + assign PIPETX12EQDEEMPH = PIPETX12EQDEEMPH_out; + assign PIPETX12POWERDOWN = PIPETX12POWERDOWN_out; + assign PIPETX12STARTBLOCK = PIPETX12STARTBLOCK_out; + assign PIPETX12SYNCHEADER = PIPETX12SYNCHEADER_out; + assign PIPETX13CHARISK = PIPETX13CHARISK_out; + assign PIPETX13COMPLIANCE = PIPETX13COMPLIANCE_out; + assign PIPETX13DATA = PIPETX13DATA_out; + assign PIPETX13DATAVALID = PIPETX13DATAVALID_out; + assign PIPETX13ELECIDLE = PIPETX13ELECIDLE_out; + assign PIPETX13EQCONTROL = PIPETX13EQCONTROL_out; + assign PIPETX13EQDEEMPH = PIPETX13EQDEEMPH_out; + assign PIPETX13POWERDOWN = PIPETX13POWERDOWN_out; + assign PIPETX13STARTBLOCK = PIPETX13STARTBLOCK_out; + assign PIPETX13SYNCHEADER = PIPETX13SYNCHEADER_out; + assign PIPETX14CHARISK = PIPETX14CHARISK_out; + assign PIPETX14COMPLIANCE = PIPETX14COMPLIANCE_out; + assign PIPETX14DATA = PIPETX14DATA_out; + assign PIPETX14DATAVALID = PIPETX14DATAVALID_out; + assign PIPETX14ELECIDLE = PIPETX14ELECIDLE_out; + assign PIPETX14EQCONTROL = PIPETX14EQCONTROL_out; + assign PIPETX14EQDEEMPH = PIPETX14EQDEEMPH_out; + assign PIPETX14POWERDOWN = PIPETX14POWERDOWN_out; + assign PIPETX14STARTBLOCK = PIPETX14STARTBLOCK_out; + assign PIPETX14SYNCHEADER = PIPETX14SYNCHEADER_out; + assign PIPETX15CHARISK = PIPETX15CHARISK_out; + assign PIPETX15COMPLIANCE = PIPETX15COMPLIANCE_out; + assign PIPETX15DATA = PIPETX15DATA_out; + assign PIPETX15DATAVALID = PIPETX15DATAVALID_out; + assign PIPETX15ELECIDLE = PIPETX15ELECIDLE_out; + assign PIPETX15EQCONTROL = PIPETX15EQCONTROL_out; + assign PIPETX15EQDEEMPH = PIPETX15EQDEEMPH_out; + assign PIPETX15POWERDOWN = PIPETX15POWERDOWN_out; + assign PIPETX15STARTBLOCK = PIPETX15STARTBLOCK_out; + assign PIPETX15SYNCHEADER = PIPETX15SYNCHEADER_out; + assign PIPETXDEEMPH = PIPETXDEEMPH_out; + assign PIPETXMARGIN = PIPETXMARGIN_out; + assign PIPETXRATE = PIPETXRATE_out; + assign PIPETXRCVRDET = PIPETXRCVRDET_out; + assign PIPETXRESET = PIPETXRESET_out; + assign PIPETXSWING = PIPETXSWING_out; + assign PLEQINPROGRESS = PLEQINPROGRESS_out; + assign PLEQPHASE = PLEQPHASE_out; + assign PLGEN34EQMISMATCH = PLGEN34EQMISMATCH_out; + assign SAXISCCTREADY = SAXISCCTREADY_out; + assign SAXISRQTREADY = SAXISRQTREADY_out; + assign USERSPAREOUT = USERSPAREOUT_out; + +`ifdef XIL_TIMING + assign AXIUSERIN_in[0] = (AXIUSERIN[0] !== 1'bz) && AXIUSERIN_delay[0]; // rv 0 + assign AXIUSERIN_in[1] = (AXIUSERIN[1] !== 1'bz) && AXIUSERIN_delay[1]; // rv 0 + assign AXIUSERIN_in[2] = (AXIUSERIN[2] !== 1'bz) && AXIUSERIN_delay[2]; // rv 0 + assign AXIUSERIN_in[3] = (AXIUSERIN[3] !== 1'bz) && AXIUSERIN_delay[3]; // rv 0 + assign AXIUSERIN_in[4] = (AXIUSERIN[4] !== 1'bz) && AXIUSERIN_delay[4]; // rv 0 + assign AXIUSERIN_in[5] = (AXIUSERIN[5] !== 1'bz) && AXIUSERIN_delay[5]; // rv 0 + assign AXIUSERIN_in[6] = (AXIUSERIN[6] !== 1'bz) && AXIUSERIN_delay[6]; // rv 0 + assign AXIUSERIN_in[7] = (AXIUSERIN[7] !== 1'bz) && AXIUSERIN_delay[7]; // rv 0 + assign CCIXOPTIMIZEDTLPTXANDRXENABLE_in = (CCIXOPTIMIZEDTLPTXANDRXENABLE !== 1'bz) && CCIXOPTIMIZEDTLPTXANDRXENABLE_delay; // rv 0 + assign CCIXRXTLPFORWARDED0_in = (CCIXRXTLPFORWARDED0 !== 1'bz) && CCIXRXTLPFORWARDED0_delay; // rv 0 + assign CCIXRXTLPFORWARDED1_in = (CCIXRXTLPFORWARDED1 !== 1'bz) && CCIXRXTLPFORWARDED1_delay; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[0] = (CCIXRXTLPFORWARDEDLENGTH0[0] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[0]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[1] = (CCIXRXTLPFORWARDEDLENGTH0[1] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[1]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[2] = (CCIXRXTLPFORWARDEDLENGTH0[2] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[2]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[3] = (CCIXRXTLPFORWARDEDLENGTH0[3] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[3]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[4] = (CCIXRXTLPFORWARDEDLENGTH0[4] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[4]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[5] = (CCIXRXTLPFORWARDEDLENGTH0[5] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0_delay[5]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[0] = (CCIXRXTLPFORWARDEDLENGTH1[0] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[0]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[1] = (CCIXRXTLPFORWARDEDLENGTH1[1] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[1]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[2] = (CCIXRXTLPFORWARDEDLENGTH1[2] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[2]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[3] = (CCIXRXTLPFORWARDEDLENGTH1[3] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[3]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[4] = (CCIXRXTLPFORWARDEDLENGTH1[4] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[4]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[5] = (CCIXRXTLPFORWARDEDLENGTH1[5] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1_delay[5]; // rv 0 + assign CFGCONFIGSPACEENABLE_in = (CFGCONFIGSPACEENABLE === 1'bz) || CFGCONFIGSPACEENABLE_delay; // rv 1 + assign CFGDEVIDPF0_in[0] = (CFGDEVIDPF0[0] !== 1'bz) && CFGDEVIDPF0_delay[0]; // rv 0 + assign CFGDEVIDPF0_in[10] = (CFGDEVIDPF0[10] !== 1'bz) && CFGDEVIDPF0_delay[10]; // rv 0 + assign CFGDEVIDPF0_in[11] = (CFGDEVIDPF0[11] !== 1'bz) && CFGDEVIDPF0_delay[11]; // rv 0 + assign CFGDEVIDPF0_in[12] = (CFGDEVIDPF0[12] !== 1'bz) && CFGDEVIDPF0_delay[12]; // rv 0 + assign CFGDEVIDPF0_in[13] = (CFGDEVIDPF0[13] !== 1'bz) && CFGDEVIDPF0_delay[13]; // rv 0 + assign CFGDEVIDPF0_in[14] = (CFGDEVIDPF0[14] !== 1'bz) && CFGDEVIDPF0_delay[14]; // rv 0 + assign CFGDEVIDPF0_in[15] = (CFGDEVIDPF0[15] !== 1'bz) && CFGDEVIDPF0_delay[15]; // rv 0 + assign CFGDEVIDPF0_in[1] = (CFGDEVIDPF0[1] !== 1'bz) && CFGDEVIDPF0_delay[1]; // rv 0 + assign CFGDEVIDPF0_in[2] = (CFGDEVIDPF0[2] !== 1'bz) && CFGDEVIDPF0_delay[2]; // rv 0 + assign CFGDEVIDPF0_in[3] = (CFGDEVIDPF0[3] !== 1'bz) && CFGDEVIDPF0_delay[3]; // rv 0 + assign CFGDEVIDPF0_in[4] = (CFGDEVIDPF0[4] !== 1'bz) && CFGDEVIDPF0_delay[4]; // rv 0 + assign CFGDEVIDPF0_in[5] = (CFGDEVIDPF0[5] !== 1'bz) && CFGDEVIDPF0_delay[5]; // rv 0 + assign CFGDEVIDPF0_in[6] = (CFGDEVIDPF0[6] !== 1'bz) && CFGDEVIDPF0_delay[6]; // rv 0 + assign CFGDEVIDPF0_in[7] = (CFGDEVIDPF0[7] !== 1'bz) && CFGDEVIDPF0_delay[7]; // rv 0 + assign CFGDEVIDPF0_in[8] = (CFGDEVIDPF0[8] !== 1'bz) && CFGDEVIDPF0_delay[8]; // rv 0 + assign CFGDEVIDPF0_in[9] = (CFGDEVIDPF0[9] !== 1'bz) && CFGDEVIDPF0_delay[9]; // rv 0 + assign CFGDEVIDPF1_in[0] = (CFGDEVIDPF1[0] !== 1'bz) && CFGDEVIDPF1_delay[0]; // rv 0 + assign CFGDEVIDPF1_in[10] = (CFGDEVIDPF1[10] !== 1'bz) && CFGDEVIDPF1_delay[10]; // rv 0 + assign CFGDEVIDPF1_in[11] = (CFGDEVIDPF1[11] !== 1'bz) && CFGDEVIDPF1_delay[11]; // rv 0 + assign CFGDEVIDPF1_in[12] = (CFGDEVIDPF1[12] !== 1'bz) && CFGDEVIDPF1_delay[12]; // rv 0 + assign CFGDEVIDPF1_in[13] = (CFGDEVIDPF1[13] !== 1'bz) && CFGDEVIDPF1_delay[13]; // rv 0 + assign CFGDEVIDPF1_in[14] = (CFGDEVIDPF1[14] !== 1'bz) && CFGDEVIDPF1_delay[14]; // rv 0 + assign CFGDEVIDPF1_in[15] = (CFGDEVIDPF1[15] !== 1'bz) && CFGDEVIDPF1_delay[15]; // rv 0 + assign CFGDEVIDPF1_in[1] = (CFGDEVIDPF1[1] !== 1'bz) && CFGDEVIDPF1_delay[1]; // rv 0 + assign CFGDEVIDPF1_in[2] = (CFGDEVIDPF1[2] !== 1'bz) && CFGDEVIDPF1_delay[2]; // rv 0 + assign CFGDEVIDPF1_in[3] = (CFGDEVIDPF1[3] !== 1'bz) && CFGDEVIDPF1_delay[3]; // rv 0 + assign CFGDEVIDPF1_in[4] = (CFGDEVIDPF1[4] !== 1'bz) && CFGDEVIDPF1_delay[4]; // rv 0 + assign CFGDEVIDPF1_in[5] = (CFGDEVIDPF1[5] !== 1'bz) && CFGDEVIDPF1_delay[5]; // rv 0 + assign CFGDEVIDPF1_in[6] = (CFGDEVIDPF1[6] !== 1'bz) && CFGDEVIDPF1_delay[6]; // rv 0 + assign CFGDEVIDPF1_in[7] = (CFGDEVIDPF1[7] !== 1'bz) && CFGDEVIDPF1_delay[7]; // rv 0 + assign CFGDEVIDPF1_in[8] = (CFGDEVIDPF1[8] !== 1'bz) && CFGDEVIDPF1_delay[8]; // rv 0 + assign CFGDEVIDPF1_in[9] = (CFGDEVIDPF1[9] !== 1'bz) && CFGDEVIDPF1_delay[9]; // rv 0 + assign CFGDEVIDPF2_in[0] = (CFGDEVIDPF2[0] !== 1'bz) && CFGDEVIDPF2_delay[0]; // rv 0 + assign CFGDEVIDPF2_in[10] = (CFGDEVIDPF2[10] !== 1'bz) && CFGDEVIDPF2_delay[10]; // rv 0 + assign CFGDEVIDPF2_in[11] = (CFGDEVIDPF2[11] !== 1'bz) && CFGDEVIDPF2_delay[11]; // rv 0 + assign CFGDEVIDPF2_in[12] = (CFGDEVIDPF2[12] !== 1'bz) && CFGDEVIDPF2_delay[12]; // rv 0 + assign CFGDEVIDPF2_in[13] = (CFGDEVIDPF2[13] !== 1'bz) && CFGDEVIDPF2_delay[13]; // rv 0 + assign CFGDEVIDPF2_in[14] = (CFGDEVIDPF2[14] !== 1'bz) && CFGDEVIDPF2_delay[14]; // rv 0 + assign CFGDEVIDPF2_in[15] = (CFGDEVIDPF2[15] !== 1'bz) && CFGDEVIDPF2_delay[15]; // rv 0 + assign CFGDEVIDPF2_in[1] = (CFGDEVIDPF2[1] !== 1'bz) && CFGDEVIDPF2_delay[1]; // rv 0 + assign CFGDEVIDPF2_in[2] = (CFGDEVIDPF2[2] !== 1'bz) && CFGDEVIDPF2_delay[2]; // rv 0 + assign CFGDEVIDPF2_in[3] = (CFGDEVIDPF2[3] !== 1'bz) && CFGDEVIDPF2_delay[3]; // rv 0 + assign CFGDEVIDPF2_in[4] = (CFGDEVIDPF2[4] !== 1'bz) && CFGDEVIDPF2_delay[4]; // rv 0 + assign CFGDEVIDPF2_in[5] = (CFGDEVIDPF2[5] !== 1'bz) && CFGDEVIDPF2_delay[5]; // rv 0 + assign CFGDEVIDPF2_in[6] = (CFGDEVIDPF2[6] !== 1'bz) && CFGDEVIDPF2_delay[6]; // rv 0 + assign CFGDEVIDPF2_in[7] = (CFGDEVIDPF2[7] !== 1'bz) && CFGDEVIDPF2_delay[7]; // rv 0 + assign CFGDEVIDPF2_in[8] = (CFGDEVIDPF2[8] !== 1'bz) && CFGDEVIDPF2_delay[8]; // rv 0 + assign CFGDEVIDPF2_in[9] = (CFGDEVIDPF2[9] !== 1'bz) && CFGDEVIDPF2_delay[9]; // rv 0 + assign CFGDEVIDPF3_in[0] = (CFGDEVIDPF3[0] !== 1'bz) && CFGDEVIDPF3_delay[0]; // rv 0 + assign CFGDEVIDPF3_in[10] = (CFGDEVIDPF3[10] !== 1'bz) && CFGDEVIDPF3_delay[10]; // rv 0 + assign CFGDEVIDPF3_in[11] = (CFGDEVIDPF3[11] !== 1'bz) && CFGDEVIDPF3_delay[11]; // rv 0 + assign CFGDEVIDPF3_in[12] = (CFGDEVIDPF3[12] !== 1'bz) && CFGDEVIDPF3_delay[12]; // rv 0 + assign CFGDEVIDPF3_in[13] = (CFGDEVIDPF3[13] !== 1'bz) && CFGDEVIDPF3_delay[13]; // rv 0 + assign CFGDEVIDPF3_in[14] = (CFGDEVIDPF3[14] !== 1'bz) && CFGDEVIDPF3_delay[14]; // rv 0 + assign CFGDEVIDPF3_in[15] = (CFGDEVIDPF3[15] !== 1'bz) && CFGDEVIDPF3_delay[15]; // rv 0 + assign CFGDEVIDPF3_in[1] = (CFGDEVIDPF3[1] !== 1'bz) && CFGDEVIDPF3_delay[1]; // rv 0 + assign CFGDEVIDPF3_in[2] = (CFGDEVIDPF3[2] !== 1'bz) && CFGDEVIDPF3_delay[2]; // rv 0 + assign CFGDEVIDPF3_in[3] = (CFGDEVIDPF3[3] !== 1'bz) && CFGDEVIDPF3_delay[3]; // rv 0 + assign CFGDEVIDPF3_in[4] = (CFGDEVIDPF3[4] !== 1'bz) && CFGDEVIDPF3_delay[4]; // rv 0 + assign CFGDEVIDPF3_in[5] = (CFGDEVIDPF3[5] !== 1'bz) && CFGDEVIDPF3_delay[5]; // rv 0 + assign CFGDEVIDPF3_in[6] = (CFGDEVIDPF3[6] !== 1'bz) && CFGDEVIDPF3_delay[6]; // rv 0 + assign CFGDEVIDPF3_in[7] = (CFGDEVIDPF3[7] !== 1'bz) && CFGDEVIDPF3_delay[7]; // rv 0 + assign CFGDEVIDPF3_in[8] = (CFGDEVIDPF3[8] !== 1'bz) && CFGDEVIDPF3_delay[8]; // rv 0 + assign CFGDEVIDPF3_in[9] = (CFGDEVIDPF3[9] !== 1'bz) && CFGDEVIDPF3_delay[9]; // rv 0 + assign CFGDSBUSNUMBER_in[0] = (CFGDSBUSNUMBER[0] !== 1'bz) && CFGDSBUSNUMBER_delay[0]; // rv 0 + assign CFGDSBUSNUMBER_in[1] = (CFGDSBUSNUMBER[1] !== 1'bz) && CFGDSBUSNUMBER_delay[1]; // rv 0 + assign CFGDSBUSNUMBER_in[2] = (CFGDSBUSNUMBER[2] !== 1'bz) && CFGDSBUSNUMBER_delay[2]; // rv 0 + assign CFGDSBUSNUMBER_in[3] = (CFGDSBUSNUMBER[3] !== 1'bz) && CFGDSBUSNUMBER_delay[3]; // rv 0 + assign CFGDSBUSNUMBER_in[4] = (CFGDSBUSNUMBER[4] !== 1'bz) && CFGDSBUSNUMBER_delay[4]; // rv 0 + assign CFGDSBUSNUMBER_in[5] = (CFGDSBUSNUMBER[5] !== 1'bz) && CFGDSBUSNUMBER_delay[5]; // rv 0 + assign CFGDSBUSNUMBER_in[6] = (CFGDSBUSNUMBER[6] !== 1'bz) && CFGDSBUSNUMBER_delay[6]; // rv 0 + assign CFGDSBUSNUMBER_in[7] = (CFGDSBUSNUMBER[7] !== 1'bz) && CFGDSBUSNUMBER_delay[7]; // rv 0 + assign CFGDSDEVICENUMBER_in[0] = (CFGDSDEVICENUMBER[0] !== 1'bz) && CFGDSDEVICENUMBER_delay[0]; // rv 0 + assign CFGDSDEVICENUMBER_in[1] = (CFGDSDEVICENUMBER[1] !== 1'bz) && CFGDSDEVICENUMBER_delay[1]; // rv 0 + assign CFGDSDEVICENUMBER_in[2] = (CFGDSDEVICENUMBER[2] !== 1'bz) && CFGDSDEVICENUMBER_delay[2]; // rv 0 + assign CFGDSDEVICENUMBER_in[3] = (CFGDSDEVICENUMBER[3] !== 1'bz) && CFGDSDEVICENUMBER_delay[3]; // rv 0 + assign CFGDSDEVICENUMBER_in[4] = (CFGDSDEVICENUMBER[4] !== 1'bz) && CFGDSDEVICENUMBER_delay[4]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[0] = (CFGDSFUNCTIONNUMBER[0] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[1] = (CFGDSFUNCTIONNUMBER[1] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[2] = (CFGDSFUNCTIONNUMBER[2] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGDSN_in[0] = (CFGDSN[0] !== 1'bz) && CFGDSN_delay[0]; // rv 0 + assign CFGDSN_in[10] = (CFGDSN[10] !== 1'bz) && CFGDSN_delay[10]; // rv 0 + assign CFGDSN_in[11] = (CFGDSN[11] !== 1'bz) && CFGDSN_delay[11]; // rv 0 + assign CFGDSN_in[12] = (CFGDSN[12] !== 1'bz) && CFGDSN_delay[12]; // rv 0 + assign CFGDSN_in[13] = (CFGDSN[13] !== 1'bz) && CFGDSN_delay[13]; // rv 0 + assign CFGDSN_in[14] = (CFGDSN[14] !== 1'bz) && CFGDSN_delay[14]; // rv 0 + assign CFGDSN_in[15] = (CFGDSN[15] !== 1'bz) && CFGDSN_delay[15]; // rv 0 + assign CFGDSN_in[16] = (CFGDSN[16] !== 1'bz) && CFGDSN_delay[16]; // rv 0 + assign CFGDSN_in[17] = (CFGDSN[17] !== 1'bz) && CFGDSN_delay[17]; // rv 0 + assign CFGDSN_in[18] = (CFGDSN[18] !== 1'bz) && CFGDSN_delay[18]; // rv 0 + assign CFGDSN_in[19] = (CFGDSN[19] !== 1'bz) && CFGDSN_delay[19]; // rv 0 + assign CFGDSN_in[1] = (CFGDSN[1] !== 1'bz) && CFGDSN_delay[1]; // rv 0 + assign CFGDSN_in[20] = (CFGDSN[20] !== 1'bz) && CFGDSN_delay[20]; // rv 0 + assign CFGDSN_in[21] = (CFGDSN[21] !== 1'bz) && CFGDSN_delay[21]; // rv 0 + assign CFGDSN_in[22] = (CFGDSN[22] !== 1'bz) && CFGDSN_delay[22]; // rv 0 + assign CFGDSN_in[23] = (CFGDSN[23] !== 1'bz) && CFGDSN_delay[23]; // rv 0 + assign CFGDSN_in[24] = (CFGDSN[24] !== 1'bz) && CFGDSN_delay[24]; // rv 0 + assign CFGDSN_in[25] = (CFGDSN[25] !== 1'bz) && CFGDSN_delay[25]; // rv 0 + assign CFGDSN_in[26] = (CFGDSN[26] !== 1'bz) && CFGDSN_delay[26]; // rv 0 + assign CFGDSN_in[27] = (CFGDSN[27] !== 1'bz) && CFGDSN_delay[27]; // rv 0 + assign CFGDSN_in[28] = (CFGDSN[28] !== 1'bz) && CFGDSN_delay[28]; // rv 0 + assign CFGDSN_in[29] = (CFGDSN[29] !== 1'bz) && CFGDSN_delay[29]; // rv 0 + assign CFGDSN_in[2] = (CFGDSN[2] !== 1'bz) && CFGDSN_delay[2]; // rv 0 + assign CFGDSN_in[30] = (CFGDSN[30] !== 1'bz) && CFGDSN_delay[30]; // rv 0 + assign CFGDSN_in[31] = (CFGDSN[31] !== 1'bz) && CFGDSN_delay[31]; // rv 0 + assign CFGDSN_in[32] = (CFGDSN[32] !== 1'bz) && CFGDSN_delay[32]; // rv 0 + assign CFGDSN_in[33] = (CFGDSN[33] !== 1'bz) && CFGDSN_delay[33]; // rv 0 + assign CFGDSN_in[34] = (CFGDSN[34] !== 1'bz) && CFGDSN_delay[34]; // rv 0 + assign CFGDSN_in[35] = (CFGDSN[35] !== 1'bz) && CFGDSN_delay[35]; // rv 0 + assign CFGDSN_in[36] = (CFGDSN[36] !== 1'bz) && CFGDSN_delay[36]; // rv 0 + assign CFGDSN_in[37] = (CFGDSN[37] !== 1'bz) && CFGDSN_delay[37]; // rv 0 + assign CFGDSN_in[38] = (CFGDSN[38] !== 1'bz) && CFGDSN_delay[38]; // rv 0 + assign CFGDSN_in[39] = (CFGDSN[39] !== 1'bz) && CFGDSN_delay[39]; // rv 0 + assign CFGDSN_in[3] = (CFGDSN[3] !== 1'bz) && CFGDSN_delay[3]; // rv 0 + assign CFGDSN_in[40] = (CFGDSN[40] !== 1'bz) && CFGDSN_delay[40]; // rv 0 + assign CFGDSN_in[41] = (CFGDSN[41] !== 1'bz) && CFGDSN_delay[41]; // rv 0 + assign CFGDSN_in[42] = (CFGDSN[42] !== 1'bz) && CFGDSN_delay[42]; // rv 0 + assign CFGDSN_in[43] = (CFGDSN[43] !== 1'bz) && CFGDSN_delay[43]; // rv 0 + assign CFGDSN_in[44] = (CFGDSN[44] !== 1'bz) && CFGDSN_delay[44]; // rv 0 + assign CFGDSN_in[45] = (CFGDSN[45] !== 1'bz) && CFGDSN_delay[45]; // rv 0 + assign CFGDSN_in[46] = (CFGDSN[46] !== 1'bz) && CFGDSN_delay[46]; // rv 0 + assign CFGDSN_in[47] = (CFGDSN[47] !== 1'bz) && CFGDSN_delay[47]; // rv 0 + assign CFGDSN_in[48] = (CFGDSN[48] !== 1'bz) && CFGDSN_delay[48]; // rv 0 + assign CFGDSN_in[49] = (CFGDSN[49] !== 1'bz) && CFGDSN_delay[49]; // rv 0 + assign CFGDSN_in[4] = (CFGDSN[4] !== 1'bz) && CFGDSN_delay[4]; // rv 0 + assign CFGDSN_in[50] = (CFGDSN[50] !== 1'bz) && CFGDSN_delay[50]; // rv 0 + assign CFGDSN_in[51] = (CFGDSN[51] !== 1'bz) && CFGDSN_delay[51]; // rv 0 + assign CFGDSN_in[52] = (CFGDSN[52] !== 1'bz) && CFGDSN_delay[52]; // rv 0 + assign CFGDSN_in[53] = (CFGDSN[53] !== 1'bz) && CFGDSN_delay[53]; // rv 0 + assign CFGDSN_in[54] = (CFGDSN[54] !== 1'bz) && CFGDSN_delay[54]; // rv 0 + assign CFGDSN_in[55] = (CFGDSN[55] !== 1'bz) && CFGDSN_delay[55]; // rv 0 + assign CFGDSN_in[56] = (CFGDSN[56] !== 1'bz) && CFGDSN_delay[56]; // rv 0 + assign CFGDSN_in[57] = (CFGDSN[57] !== 1'bz) && CFGDSN_delay[57]; // rv 0 + assign CFGDSN_in[58] = (CFGDSN[58] !== 1'bz) && CFGDSN_delay[58]; // rv 0 + assign CFGDSN_in[59] = (CFGDSN[59] !== 1'bz) && CFGDSN_delay[59]; // rv 0 + assign CFGDSN_in[5] = (CFGDSN[5] !== 1'bz) && CFGDSN_delay[5]; // rv 0 + assign CFGDSN_in[60] = (CFGDSN[60] !== 1'bz) && CFGDSN_delay[60]; // rv 0 + assign CFGDSN_in[61] = (CFGDSN[61] !== 1'bz) && CFGDSN_delay[61]; // rv 0 + assign CFGDSN_in[62] = (CFGDSN[62] !== 1'bz) && CFGDSN_delay[62]; // rv 0 + assign CFGDSN_in[63] = (CFGDSN[63] !== 1'bz) && CFGDSN_delay[63]; // rv 0 + assign CFGDSN_in[6] = (CFGDSN[6] !== 1'bz) && CFGDSN_delay[6]; // rv 0 + assign CFGDSN_in[7] = (CFGDSN[7] !== 1'bz) && CFGDSN_delay[7]; // rv 0 + assign CFGDSN_in[8] = (CFGDSN[8] !== 1'bz) && CFGDSN_delay[8]; // rv 0 + assign CFGDSN_in[9] = (CFGDSN[9] !== 1'bz) && CFGDSN_delay[9]; // rv 0 + assign CFGDSPORTNUMBER_in[0] = (CFGDSPORTNUMBER[0] !== 1'bz) && CFGDSPORTNUMBER_delay[0]; // rv 0 + assign CFGDSPORTNUMBER_in[1] = (CFGDSPORTNUMBER[1] !== 1'bz) && CFGDSPORTNUMBER_delay[1]; // rv 0 + assign CFGDSPORTNUMBER_in[2] = (CFGDSPORTNUMBER[2] !== 1'bz) && CFGDSPORTNUMBER_delay[2]; // rv 0 + assign CFGDSPORTNUMBER_in[3] = (CFGDSPORTNUMBER[3] !== 1'bz) && CFGDSPORTNUMBER_delay[3]; // rv 0 + assign CFGDSPORTNUMBER_in[4] = (CFGDSPORTNUMBER[4] !== 1'bz) && CFGDSPORTNUMBER_delay[4]; // rv 0 + assign CFGDSPORTNUMBER_in[5] = (CFGDSPORTNUMBER[5] !== 1'bz) && CFGDSPORTNUMBER_delay[5]; // rv 0 + assign CFGDSPORTNUMBER_in[6] = (CFGDSPORTNUMBER[6] !== 1'bz) && CFGDSPORTNUMBER_delay[6]; // rv 0 + assign CFGDSPORTNUMBER_in[7] = (CFGDSPORTNUMBER[7] !== 1'bz) && CFGDSPORTNUMBER_delay[7]; // rv 0 + assign CFGERRCORIN_in = (CFGERRCORIN !== 1'bz) && CFGERRCORIN_delay; // rv 0 + assign CFGERRUNCORIN_in = (CFGERRUNCORIN !== 1'bz) && CFGERRUNCORIN_delay; // rv 0 + assign CFGEXTREADDATAVALID_in = (CFGEXTREADDATAVALID !== 1'bz) && CFGEXTREADDATAVALID_delay; // rv 0 + assign CFGEXTREADDATA_in[0] = (CFGEXTREADDATA[0] !== 1'bz) && CFGEXTREADDATA_delay[0]; // rv 0 + assign CFGEXTREADDATA_in[10] = (CFGEXTREADDATA[10] !== 1'bz) && CFGEXTREADDATA_delay[10]; // rv 0 + assign CFGEXTREADDATA_in[11] = (CFGEXTREADDATA[11] !== 1'bz) && CFGEXTREADDATA_delay[11]; // rv 0 + assign CFGEXTREADDATA_in[12] = (CFGEXTREADDATA[12] !== 1'bz) && CFGEXTREADDATA_delay[12]; // rv 0 + assign CFGEXTREADDATA_in[13] = (CFGEXTREADDATA[13] !== 1'bz) && CFGEXTREADDATA_delay[13]; // rv 0 + assign CFGEXTREADDATA_in[14] = (CFGEXTREADDATA[14] !== 1'bz) && CFGEXTREADDATA_delay[14]; // rv 0 + assign CFGEXTREADDATA_in[15] = (CFGEXTREADDATA[15] !== 1'bz) && CFGEXTREADDATA_delay[15]; // rv 0 + assign CFGEXTREADDATA_in[16] = (CFGEXTREADDATA[16] !== 1'bz) && CFGEXTREADDATA_delay[16]; // rv 0 + assign CFGEXTREADDATA_in[17] = (CFGEXTREADDATA[17] !== 1'bz) && CFGEXTREADDATA_delay[17]; // rv 0 + assign CFGEXTREADDATA_in[18] = (CFGEXTREADDATA[18] !== 1'bz) && CFGEXTREADDATA_delay[18]; // rv 0 + assign CFGEXTREADDATA_in[19] = (CFGEXTREADDATA[19] !== 1'bz) && CFGEXTREADDATA_delay[19]; // rv 0 + assign CFGEXTREADDATA_in[1] = (CFGEXTREADDATA[1] !== 1'bz) && CFGEXTREADDATA_delay[1]; // rv 0 + assign CFGEXTREADDATA_in[20] = (CFGEXTREADDATA[20] !== 1'bz) && CFGEXTREADDATA_delay[20]; // rv 0 + assign CFGEXTREADDATA_in[21] = (CFGEXTREADDATA[21] !== 1'bz) && CFGEXTREADDATA_delay[21]; // rv 0 + assign CFGEXTREADDATA_in[22] = (CFGEXTREADDATA[22] !== 1'bz) && CFGEXTREADDATA_delay[22]; // rv 0 + assign CFGEXTREADDATA_in[23] = (CFGEXTREADDATA[23] !== 1'bz) && CFGEXTREADDATA_delay[23]; // rv 0 + assign CFGEXTREADDATA_in[24] = (CFGEXTREADDATA[24] !== 1'bz) && CFGEXTREADDATA_delay[24]; // rv 0 + assign CFGEXTREADDATA_in[25] = (CFGEXTREADDATA[25] !== 1'bz) && CFGEXTREADDATA_delay[25]; // rv 0 + assign CFGEXTREADDATA_in[26] = (CFGEXTREADDATA[26] !== 1'bz) && CFGEXTREADDATA_delay[26]; // rv 0 + assign CFGEXTREADDATA_in[27] = (CFGEXTREADDATA[27] !== 1'bz) && CFGEXTREADDATA_delay[27]; // rv 0 + assign CFGEXTREADDATA_in[28] = (CFGEXTREADDATA[28] !== 1'bz) && CFGEXTREADDATA_delay[28]; // rv 0 + assign CFGEXTREADDATA_in[29] = (CFGEXTREADDATA[29] !== 1'bz) && CFGEXTREADDATA_delay[29]; // rv 0 + assign CFGEXTREADDATA_in[2] = (CFGEXTREADDATA[2] !== 1'bz) && CFGEXTREADDATA_delay[2]; // rv 0 + assign CFGEXTREADDATA_in[30] = (CFGEXTREADDATA[30] !== 1'bz) && CFGEXTREADDATA_delay[30]; // rv 0 + assign CFGEXTREADDATA_in[31] = (CFGEXTREADDATA[31] !== 1'bz) && CFGEXTREADDATA_delay[31]; // rv 0 + assign CFGEXTREADDATA_in[3] = (CFGEXTREADDATA[3] !== 1'bz) && CFGEXTREADDATA_delay[3]; // rv 0 + assign CFGEXTREADDATA_in[4] = (CFGEXTREADDATA[4] !== 1'bz) && CFGEXTREADDATA_delay[4]; // rv 0 + assign CFGEXTREADDATA_in[5] = (CFGEXTREADDATA[5] !== 1'bz) && CFGEXTREADDATA_delay[5]; // rv 0 + assign CFGEXTREADDATA_in[6] = (CFGEXTREADDATA[6] !== 1'bz) && CFGEXTREADDATA_delay[6]; // rv 0 + assign CFGEXTREADDATA_in[7] = (CFGEXTREADDATA[7] !== 1'bz) && CFGEXTREADDATA_delay[7]; // rv 0 + assign CFGEXTREADDATA_in[8] = (CFGEXTREADDATA[8] !== 1'bz) && CFGEXTREADDATA_delay[8]; // rv 0 + assign CFGEXTREADDATA_in[9] = (CFGEXTREADDATA[9] !== 1'bz) && CFGEXTREADDATA_delay[9]; // rv 0 + assign CFGFCSEL_in[0] = (CFGFCSEL[0] !== 1'bz) && CFGFCSEL_delay[0]; // rv 0 + assign CFGFCSEL_in[1] = (CFGFCSEL[1] !== 1'bz) && CFGFCSEL_delay[1]; // rv 0 + assign CFGFCSEL_in[2] = (CFGFCSEL[2] !== 1'bz) && CFGFCSEL_delay[2]; // rv 0 + assign CFGFCVCSEL_in = (CFGFCVCSEL !== 1'bz) && CFGFCVCSEL_delay; // rv 0 + assign CFGFLRDONE_in[0] = (CFGFLRDONE[0] !== 1'bz) && CFGFLRDONE_delay[0]; // rv 0 + assign CFGFLRDONE_in[1] = (CFGFLRDONE[1] !== 1'bz) && CFGFLRDONE_delay[1]; // rv 0 + assign CFGFLRDONE_in[2] = (CFGFLRDONE[2] !== 1'bz) && CFGFLRDONE_delay[2]; // rv 0 + assign CFGFLRDONE_in[3] = (CFGFLRDONE[3] !== 1'bz) && CFGFLRDONE_delay[3]; // rv 0 + assign CFGHOTRESETIN_in = (CFGHOTRESETIN !== 1'bz) && CFGHOTRESETIN_delay; // rv 0 + assign CFGINTERRUPTINT_in[0] = (CFGINTERRUPTINT[0] !== 1'bz) && CFGINTERRUPTINT_delay[0]; // rv 0 + assign CFGINTERRUPTINT_in[1] = (CFGINTERRUPTINT[1] !== 1'bz) && CFGINTERRUPTINT_delay[1]; // rv 0 + assign CFGINTERRUPTINT_in[2] = (CFGINTERRUPTINT[2] !== 1'bz) && CFGINTERRUPTINT_delay[2]; // rv 0 + assign CFGINTERRUPTINT_in[3] = (CFGINTERRUPTINT[3] !== 1'bz) && CFGINTERRUPTINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[0] = (CFGINTERRUPTMSIATTR[0] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[0]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[1] = (CFGINTERRUPTMSIATTR[1] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[1]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[2] = (CFGINTERRUPTMSIATTR[2] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[0] = (CFGINTERRUPTMSIFUNCTIONNUMBER[0] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[1] = (CFGINTERRUPTMSIFUNCTIONNUMBER[1] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[2] = (CFGINTERRUPTMSIFUNCTIONNUMBER[2] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[3] = (CFGINTERRUPTMSIFUNCTIONNUMBER[3] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[4] = (CFGINTERRUPTMSIFUNCTIONNUMBER[4] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[5] = (CFGINTERRUPTMSIFUNCTIONNUMBER[5] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[6] = (CFGINTERRUPTMSIFUNCTIONNUMBER[6] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[7] = (CFGINTERRUPTMSIFUNCTIONNUMBER[7] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[0] = (CFGINTERRUPTMSIINT[0] !== 1'bz) && CFGINTERRUPTMSIINT_delay[0]; // rv 0 + assign CFGINTERRUPTMSIINT_in[10] = (CFGINTERRUPTMSIINT[10] !== 1'bz) && CFGINTERRUPTMSIINT_delay[10]; // rv 0 + assign CFGINTERRUPTMSIINT_in[11] = (CFGINTERRUPTMSIINT[11] !== 1'bz) && CFGINTERRUPTMSIINT_delay[11]; // rv 0 + assign CFGINTERRUPTMSIINT_in[12] = (CFGINTERRUPTMSIINT[12] !== 1'bz) && CFGINTERRUPTMSIINT_delay[12]; // rv 0 + assign CFGINTERRUPTMSIINT_in[13] = (CFGINTERRUPTMSIINT[13] !== 1'bz) && CFGINTERRUPTMSIINT_delay[13]; // rv 0 + assign CFGINTERRUPTMSIINT_in[14] = (CFGINTERRUPTMSIINT[14] !== 1'bz) && CFGINTERRUPTMSIINT_delay[14]; // rv 0 + assign CFGINTERRUPTMSIINT_in[15] = (CFGINTERRUPTMSIINT[15] !== 1'bz) && CFGINTERRUPTMSIINT_delay[15]; // rv 0 + assign CFGINTERRUPTMSIINT_in[16] = (CFGINTERRUPTMSIINT[16] !== 1'bz) && CFGINTERRUPTMSIINT_delay[16]; // rv 0 + assign CFGINTERRUPTMSIINT_in[17] = (CFGINTERRUPTMSIINT[17] !== 1'bz) && CFGINTERRUPTMSIINT_delay[17]; // rv 0 + assign CFGINTERRUPTMSIINT_in[18] = (CFGINTERRUPTMSIINT[18] !== 1'bz) && CFGINTERRUPTMSIINT_delay[18]; // rv 0 + assign CFGINTERRUPTMSIINT_in[19] = (CFGINTERRUPTMSIINT[19] !== 1'bz) && CFGINTERRUPTMSIINT_delay[19]; // rv 0 + assign CFGINTERRUPTMSIINT_in[1] = (CFGINTERRUPTMSIINT[1] !== 1'bz) && CFGINTERRUPTMSIINT_delay[1]; // rv 0 + assign CFGINTERRUPTMSIINT_in[20] = (CFGINTERRUPTMSIINT[20] !== 1'bz) && CFGINTERRUPTMSIINT_delay[20]; // rv 0 + assign CFGINTERRUPTMSIINT_in[21] = (CFGINTERRUPTMSIINT[21] !== 1'bz) && CFGINTERRUPTMSIINT_delay[21]; // rv 0 + assign CFGINTERRUPTMSIINT_in[22] = (CFGINTERRUPTMSIINT[22] !== 1'bz) && CFGINTERRUPTMSIINT_delay[22]; // rv 0 + assign CFGINTERRUPTMSIINT_in[23] = (CFGINTERRUPTMSIINT[23] !== 1'bz) && CFGINTERRUPTMSIINT_delay[23]; // rv 0 + assign CFGINTERRUPTMSIINT_in[24] = (CFGINTERRUPTMSIINT[24] !== 1'bz) && CFGINTERRUPTMSIINT_delay[24]; // rv 0 + assign CFGINTERRUPTMSIINT_in[25] = (CFGINTERRUPTMSIINT[25] !== 1'bz) && CFGINTERRUPTMSIINT_delay[25]; // rv 0 + assign CFGINTERRUPTMSIINT_in[26] = (CFGINTERRUPTMSIINT[26] !== 1'bz) && CFGINTERRUPTMSIINT_delay[26]; // rv 0 + assign CFGINTERRUPTMSIINT_in[27] = (CFGINTERRUPTMSIINT[27] !== 1'bz) && CFGINTERRUPTMSIINT_delay[27]; // rv 0 + assign CFGINTERRUPTMSIINT_in[28] = (CFGINTERRUPTMSIINT[28] !== 1'bz) && CFGINTERRUPTMSIINT_delay[28]; // rv 0 + assign CFGINTERRUPTMSIINT_in[29] = (CFGINTERRUPTMSIINT[29] !== 1'bz) && CFGINTERRUPTMSIINT_delay[29]; // rv 0 + assign CFGINTERRUPTMSIINT_in[2] = (CFGINTERRUPTMSIINT[2] !== 1'bz) && CFGINTERRUPTMSIINT_delay[2]; // rv 0 + assign CFGINTERRUPTMSIINT_in[30] = (CFGINTERRUPTMSIINT[30] !== 1'bz) && CFGINTERRUPTMSIINT_delay[30]; // rv 0 + assign CFGINTERRUPTMSIINT_in[31] = (CFGINTERRUPTMSIINT[31] !== 1'bz) && CFGINTERRUPTMSIINT_delay[31]; // rv 0 + assign CFGINTERRUPTMSIINT_in[3] = (CFGINTERRUPTMSIINT[3] !== 1'bz) && CFGINTERRUPTMSIINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[4] = (CFGINTERRUPTMSIINT[4] !== 1'bz) && CFGINTERRUPTMSIINT_delay[4]; // rv 0 + assign CFGINTERRUPTMSIINT_in[5] = (CFGINTERRUPTMSIINT[5] !== 1'bz) && CFGINTERRUPTMSIINT_delay[5]; // rv 0 + assign CFGINTERRUPTMSIINT_in[6] = (CFGINTERRUPTMSIINT[6] !== 1'bz) && CFGINTERRUPTMSIINT_delay[6]; // rv 0 + assign CFGINTERRUPTMSIINT_in[7] = (CFGINTERRUPTMSIINT[7] !== 1'bz) && CFGINTERRUPTMSIINT_delay[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[8] = (CFGINTERRUPTMSIINT[8] !== 1'bz) && CFGINTERRUPTMSIINT_delay[8]; // rv 0 + assign CFGINTERRUPTMSIINT_in[9] = (CFGINTERRUPTMSIINT[9] !== 1'bz) && CFGINTERRUPTMSIINT_delay[9]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[0] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[1] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[0] = (CFGINTERRUPTMSIPENDINGSTATUS[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[10] = (CFGINTERRUPTMSIPENDINGSTATUS[10] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[11] = (CFGINTERRUPTMSIPENDINGSTATUS[11] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[12] = (CFGINTERRUPTMSIPENDINGSTATUS[12] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[13] = (CFGINTERRUPTMSIPENDINGSTATUS[13] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[14] = (CFGINTERRUPTMSIPENDINGSTATUS[14] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[15] = (CFGINTERRUPTMSIPENDINGSTATUS[15] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[16] = (CFGINTERRUPTMSIPENDINGSTATUS[16] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[17] = (CFGINTERRUPTMSIPENDINGSTATUS[17] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[18] = (CFGINTERRUPTMSIPENDINGSTATUS[18] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[19] = (CFGINTERRUPTMSIPENDINGSTATUS[19] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[1] = (CFGINTERRUPTMSIPENDINGSTATUS[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[20] = (CFGINTERRUPTMSIPENDINGSTATUS[20] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[21] = (CFGINTERRUPTMSIPENDINGSTATUS[21] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[22] = (CFGINTERRUPTMSIPENDINGSTATUS[22] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[23] = (CFGINTERRUPTMSIPENDINGSTATUS[23] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[24] = (CFGINTERRUPTMSIPENDINGSTATUS[24] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[25] = (CFGINTERRUPTMSIPENDINGSTATUS[25] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[26] = (CFGINTERRUPTMSIPENDINGSTATUS[26] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[27] = (CFGINTERRUPTMSIPENDINGSTATUS[27] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[28] = (CFGINTERRUPTMSIPENDINGSTATUS[28] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[29] = (CFGINTERRUPTMSIPENDINGSTATUS[29] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[2] = (CFGINTERRUPTMSIPENDINGSTATUS[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[30] = (CFGINTERRUPTMSIPENDINGSTATUS[30] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[31] = (CFGINTERRUPTMSIPENDINGSTATUS[31] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[3] = (CFGINTERRUPTMSIPENDINGSTATUS[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[4] = (CFGINTERRUPTMSIPENDINGSTATUS[4] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[5] = (CFGINTERRUPTMSIPENDINGSTATUS[5] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[6] = (CFGINTERRUPTMSIPENDINGSTATUS[6] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[7] = (CFGINTERRUPTMSIPENDINGSTATUS[7] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[8] = (CFGINTERRUPTMSIPENDINGSTATUS[8] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[9] = (CFGINTERRUPTMSIPENDINGSTATUS[9] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[9]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[0] = (CFGINTERRUPTMSISELECT[0] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[0]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[1] = (CFGINTERRUPTMSISELECT[1] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[1]; // rv 0 + assign CFGINTERRUPTMSITPHPRESENT_in = (CFGINTERRUPTMSITPHPRESENT !== 1'bz) && CFGINTERRUPTMSITPHPRESENT_delay; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[0] = (CFGINTERRUPTMSITPHSTTAG[0] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[1] = (CFGINTERRUPTMSITPHSTTAG[1] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[1]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[2] = (CFGINTERRUPTMSITPHSTTAG[2] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[2]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[3] = (CFGINTERRUPTMSITPHSTTAG[3] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[3]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[4] = (CFGINTERRUPTMSITPHSTTAG[4] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[4]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[5] = (CFGINTERRUPTMSITPHSTTAG[5] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[5]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[6] = (CFGINTERRUPTMSITPHSTTAG[6] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[6]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[7] = (CFGINTERRUPTMSITPHSTTAG[7] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[7]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[0] = (CFGINTERRUPTMSITPHTYPE[0] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[1] = (CFGINTERRUPTMSITPHTYPE[1] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[0] = (CFGINTERRUPTMSIXADDRESS[0] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[10] = (CFGINTERRUPTMSIXADDRESS[10] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[11] = (CFGINTERRUPTMSIXADDRESS[11] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[12] = (CFGINTERRUPTMSIXADDRESS[12] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[13] = (CFGINTERRUPTMSIXADDRESS[13] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[14] = (CFGINTERRUPTMSIXADDRESS[14] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[15] = (CFGINTERRUPTMSIXADDRESS[15] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[16] = (CFGINTERRUPTMSIXADDRESS[16] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[17] = (CFGINTERRUPTMSIXADDRESS[17] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[18] = (CFGINTERRUPTMSIXADDRESS[18] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[19] = (CFGINTERRUPTMSIXADDRESS[19] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[1] = (CFGINTERRUPTMSIXADDRESS[1] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[20] = (CFGINTERRUPTMSIXADDRESS[20] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[21] = (CFGINTERRUPTMSIXADDRESS[21] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[22] = (CFGINTERRUPTMSIXADDRESS[22] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[23] = (CFGINTERRUPTMSIXADDRESS[23] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[24] = (CFGINTERRUPTMSIXADDRESS[24] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[25] = (CFGINTERRUPTMSIXADDRESS[25] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[26] = (CFGINTERRUPTMSIXADDRESS[26] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[27] = (CFGINTERRUPTMSIXADDRESS[27] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[28] = (CFGINTERRUPTMSIXADDRESS[28] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[29] = (CFGINTERRUPTMSIXADDRESS[29] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[2] = (CFGINTERRUPTMSIXADDRESS[2] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[30] = (CFGINTERRUPTMSIXADDRESS[30] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[31] = (CFGINTERRUPTMSIXADDRESS[31] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[32] = (CFGINTERRUPTMSIXADDRESS[32] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[32]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[33] = (CFGINTERRUPTMSIXADDRESS[33] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[33]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[34] = (CFGINTERRUPTMSIXADDRESS[34] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[34]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[35] = (CFGINTERRUPTMSIXADDRESS[35] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[35]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[36] = (CFGINTERRUPTMSIXADDRESS[36] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[36]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[37] = (CFGINTERRUPTMSIXADDRESS[37] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[37]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[38] = (CFGINTERRUPTMSIXADDRESS[38] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[38]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[39] = (CFGINTERRUPTMSIXADDRESS[39] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[39]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[3] = (CFGINTERRUPTMSIXADDRESS[3] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[40] = (CFGINTERRUPTMSIXADDRESS[40] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[40]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[41] = (CFGINTERRUPTMSIXADDRESS[41] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[41]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[42] = (CFGINTERRUPTMSIXADDRESS[42] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[42]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[43] = (CFGINTERRUPTMSIXADDRESS[43] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[43]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[44] = (CFGINTERRUPTMSIXADDRESS[44] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[44]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[45] = (CFGINTERRUPTMSIXADDRESS[45] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[45]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[46] = (CFGINTERRUPTMSIXADDRESS[46] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[46]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[47] = (CFGINTERRUPTMSIXADDRESS[47] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[47]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[48] = (CFGINTERRUPTMSIXADDRESS[48] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[48]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[49] = (CFGINTERRUPTMSIXADDRESS[49] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[49]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[4] = (CFGINTERRUPTMSIXADDRESS[4] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[50] = (CFGINTERRUPTMSIXADDRESS[50] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[50]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[51] = (CFGINTERRUPTMSIXADDRESS[51] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[51]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[52] = (CFGINTERRUPTMSIXADDRESS[52] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[52]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[53] = (CFGINTERRUPTMSIXADDRESS[53] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[53]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[54] = (CFGINTERRUPTMSIXADDRESS[54] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[54]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[55] = (CFGINTERRUPTMSIXADDRESS[55] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[55]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[56] = (CFGINTERRUPTMSIXADDRESS[56] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[56]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[57] = (CFGINTERRUPTMSIXADDRESS[57] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[57]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[58] = (CFGINTERRUPTMSIXADDRESS[58] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[58]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[59] = (CFGINTERRUPTMSIXADDRESS[59] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[59]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[5] = (CFGINTERRUPTMSIXADDRESS[5] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[60] = (CFGINTERRUPTMSIXADDRESS[60] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[60]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[61] = (CFGINTERRUPTMSIXADDRESS[61] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[61]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[62] = (CFGINTERRUPTMSIXADDRESS[62] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[62]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[63] = (CFGINTERRUPTMSIXADDRESS[63] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[63]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[6] = (CFGINTERRUPTMSIXADDRESS[6] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[7] = (CFGINTERRUPTMSIXADDRESS[7] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[8] = (CFGINTERRUPTMSIXADDRESS[8] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[9] = (CFGINTERRUPTMSIXADDRESS[9] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[0] = (CFGINTERRUPTMSIXDATA[0] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[10] = (CFGINTERRUPTMSIXDATA[10] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[11] = (CFGINTERRUPTMSIXDATA[11] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[12] = (CFGINTERRUPTMSIXDATA[12] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[13] = (CFGINTERRUPTMSIXDATA[13] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[14] = (CFGINTERRUPTMSIXDATA[14] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[15] = (CFGINTERRUPTMSIXDATA[15] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[16] = (CFGINTERRUPTMSIXDATA[16] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[17] = (CFGINTERRUPTMSIXDATA[17] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[18] = (CFGINTERRUPTMSIXDATA[18] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[19] = (CFGINTERRUPTMSIXDATA[19] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[1] = (CFGINTERRUPTMSIXDATA[1] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[20] = (CFGINTERRUPTMSIXDATA[20] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[21] = (CFGINTERRUPTMSIXDATA[21] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[22] = (CFGINTERRUPTMSIXDATA[22] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[23] = (CFGINTERRUPTMSIXDATA[23] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[24] = (CFGINTERRUPTMSIXDATA[24] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[25] = (CFGINTERRUPTMSIXDATA[25] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[26] = (CFGINTERRUPTMSIXDATA[26] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[27] = (CFGINTERRUPTMSIXDATA[27] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[28] = (CFGINTERRUPTMSIXDATA[28] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[29] = (CFGINTERRUPTMSIXDATA[29] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[2] = (CFGINTERRUPTMSIXDATA[2] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[30] = (CFGINTERRUPTMSIXDATA[30] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[31] = (CFGINTERRUPTMSIXDATA[31] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[3] = (CFGINTERRUPTMSIXDATA[3] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[4] = (CFGINTERRUPTMSIXDATA[4] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[5] = (CFGINTERRUPTMSIXDATA[5] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[6] = (CFGINTERRUPTMSIXDATA[6] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[7] = (CFGINTERRUPTMSIXDATA[7] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[8] = (CFGINTERRUPTMSIXDATA[8] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[9] = (CFGINTERRUPTMSIXDATA[9] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXINT_in = (CFGINTERRUPTMSIXINT !== 1'bz) && CFGINTERRUPTMSIXINT_delay; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[0] = (CFGINTERRUPTMSIXVECPENDING[0] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[1] = (CFGINTERRUPTMSIXVECPENDING[1] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING_delay[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[0] = (CFGINTERRUPTPENDING[0] !== 1'bz) && CFGINTERRUPTPENDING_delay[0]; // rv 0 + assign CFGINTERRUPTPENDING_in[1] = (CFGINTERRUPTPENDING[1] !== 1'bz) && CFGINTERRUPTPENDING_delay[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[2] = (CFGINTERRUPTPENDING[2] !== 1'bz) && CFGINTERRUPTPENDING_delay[2]; // rv 0 + assign CFGINTERRUPTPENDING_in[3] = (CFGINTERRUPTPENDING[3] !== 1'bz) && CFGINTERRUPTPENDING_delay[3]; // rv 0 + assign CFGLINKTRAININGENABLE_in = (CFGLINKTRAININGENABLE === 1'bz) || CFGLINKTRAININGENABLE_delay; // rv 1 + assign CFGMGMTADDR_in[0] = (CFGMGMTADDR[0] !== 1'bz) && CFGMGMTADDR_delay[0]; // rv 0 + assign CFGMGMTADDR_in[1] = (CFGMGMTADDR[1] !== 1'bz) && CFGMGMTADDR_delay[1]; // rv 0 + assign CFGMGMTADDR_in[2] = (CFGMGMTADDR[2] !== 1'bz) && CFGMGMTADDR_delay[2]; // rv 0 + assign CFGMGMTADDR_in[3] = (CFGMGMTADDR[3] !== 1'bz) && CFGMGMTADDR_delay[3]; // rv 0 + assign CFGMGMTADDR_in[4] = (CFGMGMTADDR[4] !== 1'bz) && CFGMGMTADDR_delay[4]; // rv 0 + assign CFGMGMTADDR_in[5] = (CFGMGMTADDR[5] !== 1'bz) && CFGMGMTADDR_delay[5]; // rv 0 + assign CFGMGMTADDR_in[6] = (CFGMGMTADDR[6] !== 1'bz) && CFGMGMTADDR_delay[6]; // rv 0 + assign CFGMGMTADDR_in[7] = (CFGMGMTADDR[7] !== 1'bz) && CFGMGMTADDR_delay[7]; // rv 0 + assign CFGMGMTADDR_in[8] = (CFGMGMTADDR[8] !== 1'bz) && CFGMGMTADDR_delay[8]; // rv 0 + assign CFGMGMTADDR_in[9] = (CFGMGMTADDR[9] !== 1'bz) && CFGMGMTADDR_delay[9]; // rv 0 + assign CFGMGMTBYTEENABLE_in[0] = (CFGMGMTBYTEENABLE[0] !== 1'bz) && CFGMGMTBYTEENABLE_delay[0]; // rv 0 + assign CFGMGMTBYTEENABLE_in[1] = (CFGMGMTBYTEENABLE[1] !== 1'bz) && CFGMGMTBYTEENABLE_delay[1]; // rv 0 + assign CFGMGMTBYTEENABLE_in[2] = (CFGMGMTBYTEENABLE[2] !== 1'bz) && CFGMGMTBYTEENABLE_delay[2]; // rv 0 + assign CFGMGMTBYTEENABLE_in[3] = (CFGMGMTBYTEENABLE[3] !== 1'bz) && CFGMGMTBYTEENABLE_delay[3]; // rv 0 + assign CFGMGMTDEBUGACCESS_in = (CFGMGMTDEBUGACCESS !== 1'bz) && CFGMGMTDEBUGACCESS_delay; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[0] = (CFGMGMTFUNCTIONNUMBER[0] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[1] = (CFGMGMTFUNCTIONNUMBER[1] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[2] = (CFGMGMTFUNCTIONNUMBER[2] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[3] = (CFGMGMTFUNCTIONNUMBER[3] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[4] = (CFGMGMTFUNCTIONNUMBER[4] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[4]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[5] = (CFGMGMTFUNCTIONNUMBER[5] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[5]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[6] = (CFGMGMTFUNCTIONNUMBER[6] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[6]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[7] = (CFGMGMTFUNCTIONNUMBER[7] !== 1'bz) && CFGMGMTFUNCTIONNUMBER_delay[7]; // rv 0 + assign CFGMGMTREAD_in = (CFGMGMTREAD !== 1'bz) && CFGMGMTREAD_delay; // rv 0 + assign CFGMGMTWRITEDATA_in[0] = (CFGMGMTWRITEDATA[0] !== 1'bz) && CFGMGMTWRITEDATA_delay[0]; // rv 0 + assign CFGMGMTWRITEDATA_in[10] = (CFGMGMTWRITEDATA[10] !== 1'bz) && CFGMGMTWRITEDATA_delay[10]; // rv 0 + assign CFGMGMTWRITEDATA_in[11] = (CFGMGMTWRITEDATA[11] !== 1'bz) && CFGMGMTWRITEDATA_delay[11]; // rv 0 + assign CFGMGMTWRITEDATA_in[12] = (CFGMGMTWRITEDATA[12] !== 1'bz) && CFGMGMTWRITEDATA_delay[12]; // rv 0 + assign CFGMGMTWRITEDATA_in[13] = (CFGMGMTWRITEDATA[13] !== 1'bz) && CFGMGMTWRITEDATA_delay[13]; // rv 0 + assign CFGMGMTWRITEDATA_in[14] = (CFGMGMTWRITEDATA[14] !== 1'bz) && CFGMGMTWRITEDATA_delay[14]; // rv 0 + assign CFGMGMTWRITEDATA_in[15] = (CFGMGMTWRITEDATA[15] !== 1'bz) && CFGMGMTWRITEDATA_delay[15]; // rv 0 + assign CFGMGMTWRITEDATA_in[16] = (CFGMGMTWRITEDATA[16] !== 1'bz) && CFGMGMTWRITEDATA_delay[16]; // rv 0 + assign CFGMGMTWRITEDATA_in[17] = (CFGMGMTWRITEDATA[17] !== 1'bz) && CFGMGMTWRITEDATA_delay[17]; // rv 0 + assign CFGMGMTWRITEDATA_in[18] = (CFGMGMTWRITEDATA[18] !== 1'bz) && CFGMGMTWRITEDATA_delay[18]; // rv 0 + assign CFGMGMTWRITEDATA_in[19] = (CFGMGMTWRITEDATA[19] !== 1'bz) && CFGMGMTWRITEDATA_delay[19]; // rv 0 + assign CFGMGMTWRITEDATA_in[1] = (CFGMGMTWRITEDATA[1] !== 1'bz) && CFGMGMTWRITEDATA_delay[1]; // rv 0 + assign CFGMGMTWRITEDATA_in[20] = (CFGMGMTWRITEDATA[20] !== 1'bz) && CFGMGMTWRITEDATA_delay[20]; // rv 0 + assign CFGMGMTWRITEDATA_in[21] = (CFGMGMTWRITEDATA[21] !== 1'bz) && CFGMGMTWRITEDATA_delay[21]; // rv 0 + assign CFGMGMTWRITEDATA_in[22] = (CFGMGMTWRITEDATA[22] !== 1'bz) && CFGMGMTWRITEDATA_delay[22]; // rv 0 + assign CFGMGMTWRITEDATA_in[23] = (CFGMGMTWRITEDATA[23] !== 1'bz) && CFGMGMTWRITEDATA_delay[23]; // rv 0 + assign CFGMGMTWRITEDATA_in[24] = (CFGMGMTWRITEDATA[24] !== 1'bz) && CFGMGMTWRITEDATA_delay[24]; // rv 0 + assign CFGMGMTWRITEDATA_in[25] = (CFGMGMTWRITEDATA[25] !== 1'bz) && CFGMGMTWRITEDATA_delay[25]; // rv 0 + assign CFGMGMTWRITEDATA_in[26] = (CFGMGMTWRITEDATA[26] !== 1'bz) && CFGMGMTWRITEDATA_delay[26]; // rv 0 + assign CFGMGMTWRITEDATA_in[27] = (CFGMGMTWRITEDATA[27] !== 1'bz) && CFGMGMTWRITEDATA_delay[27]; // rv 0 + assign CFGMGMTWRITEDATA_in[28] = (CFGMGMTWRITEDATA[28] !== 1'bz) && CFGMGMTWRITEDATA_delay[28]; // rv 0 + assign CFGMGMTWRITEDATA_in[29] = (CFGMGMTWRITEDATA[29] !== 1'bz) && CFGMGMTWRITEDATA_delay[29]; // rv 0 + assign CFGMGMTWRITEDATA_in[2] = (CFGMGMTWRITEDATA[2] !== 1'bz) && CFGMGMTWRITEDATA_delay[2]; // rv 0 + assign CFGMGMTWRITEDATA_in[30] = (CFGMGMTWRITEDATA[30] !== 1'bz) && CFGMGMTWRITEDATA_delay[30]; // rv 0 + assign CFGMGMTWRITEDATA_in[31] = (CFGMGMTWRITEDATA[31] !== 1'bz) && CFGMGMTWRITEDATA_delay[31]; // rv 0 + assign CFGMGMTWRITEDATA_in[3] = (CFGMGMTWRITEDATA[3] !== 1'bz) && CFGMGMTWRITEDATA_delay[3]; // rv 0 + assign CFGMGMTWRITEDATA_in[4] = (CFGMGMTWRITEDATA[4] !== 1'bz) && CFGMGMTWRITEDATA_delay[4]; // rv 0 + assign CFGMGMTWRITEDATA_in[5] = (CFGMGMTWRITEDATA[5] !== 1'bz) && CFGMGMTWRITEDATA_delay[5]; // rv 0 + assign CFGMGMTWRITEDATA_in[6] = (CFGMGMTWRITEDATA[6] !== 1'bz) && CFGMGMTWRITEDATA_delay[6]; // rv 0 + assign CFGMGMTWRITEDATA_in[7] = (CFGMGMTWRITEDATA[7] !== 1'bz) && CFGMGMTWRITEDATA_delay[7]; // rv 0 + assign CFGMGMTWRITEDATA_in[8] = (CFGMGMTWRITEDATA[8] !== 1'bz) && CFGMGMTWRITEDATA_delay[8]; // rv 0 + assign CFGMGMTWRITEDATA_in[9] = (CFGMGMTWRITEDATA[9] !== 1'bz) && CFGMGMTWRITEDATA_delay[9]; // rv 0 + assign CFGMGMTWRITE_in = (CFGMGMTWRITE !== 1'bz) && CFGMGMTWRITE_delay; // rv 0 + assign CFGMSGTRANSMITDATA_in[0] = (CFGMSGTRANSMITDATA[0] !== 1'bz) && CFGMSGTRANSMITDATA_delay[0]; // rv 0 + assign CFGMSGTRANSMITDATA_in[10] = (CFGMSGTRANSMITDATA[10] !== 1'bz) && CFGMSGTRANSMITDATA_delay[10]; // rv 0 + assign CFGMSGTRANSMITDATA_in[11] = (CFGMSGTRANSMITDATA[11] !== 1'bz) && CFGMSGTRANSMITDATA_delay[11]; // rv 0 + assign CFGMSGTRANSMITDATA_in[12] = (CFGMSGTRANSMITDATA[12] !== 1'bz) && CFGMSGTRANSMITDATA_delay[12]; // rv 0 + assign CFGMSGTRANSMITDATA_in[13] = (CFGMSGTRANSMITDATA[13] !== 1'bz) && CFGMSGTRANSMITDATA_delay[13]; // rv 0 + assign CFGMSGTRANSMITDATA_in[14] = (CFGMSGTRANSMITDATA[14] !== 1'bz) && CFGMSGTRANSMITDATA_delay[14]; // rv 0 + assign CFGMSGTRANSMITDATA_in[15] = (CFGMSGTRANSMITDATA[15] !== 1'bz) && CFGMSGTRANSMITDATA_delay[15]; // rv 0 + assign CFGMSGTRANSMITDATA_in[16] = (CFGMSGTRANSMITDATA[16] !== 1'bz) && CFGMSGTRANSMITDATA_delay[16]; // rv 0 + assign CFGMSGTRANSMITDATA_in[17] = (CFGMSGTRANSMITDATA[17] !== 1'bz) && CFGMSGTRANSMITDATA_delay[17]; // rv 0 + assign CFGMSGTRANSMITDATA_in[18] = (CFGMSGTRANSMITDATA[18] !== 1'bz) && CFGMSGTRANSMITDATA_delay[18]; // rv 0 + assign CFGMSGTRANSMITDATA_in[19] = (CFGMSGTRANSMITDATA[19] !== 1'bz) && CFGMSGTRANSMITDATA_delay[19]; // rv 0 + assign CFGMSGTRANSMITDATA_in[1] = (CFGMSGTRANSMITDATA[1] !== 1'bz) && CFGMSGTRANSMITDATA_delay[1]; // rv 0 + assign CFGMSGTRANSMITDATA_in[20] = (CFGMSGTRANSMITDATA[20] !== 1'bz) && CFGMSGTRANSMITDATA_delay[20]; // rv 0 + assign CFGMSGTRANSMITDATA_in[21] = (CFGMSGTRANSMITDATA[21] !== 1'bz) && CFGMSGTRANSMITDATA_delay[21]; // rv 0 + assign CFGMSGTRANSMITDATA_in[22] = (CFGMSGTRANSMITDATA[22] !== 1'bz) && CFGMSGTRANSMITDATA_delay[22]; // rv 0 + assign CFGMSGTRANSMITDATA_in[23] = (CFGMSGTRANSMITDATA[23] !== 1'bz) && CFGMSGTRANSMITDATA_delay[23]; // rv 0 + assign CFGMSGTRANSMITDATA_in[24] = (CFGMSGTRANSMITDATA[24] !== 1'bz) && CFGMSGTRANSMITDATA_delay[24]; // rv 0 + assign CFGMSGTRANSMITDATA_in[25] = (CFGMSGTRANSMITDATA[25] !== 1'bz) && CFGMSGTRANSMITDATA_delay[25]; // rv 0 + assign CFGMSGTRANSMITDATA_in[26] = (CFGMSGTRANSMITDATA[26] !== 1'bz) && CFGMSGTRANSMITDATA_delay[26]; // rv 0 + assign CFGMSGTRANSMITDATA_in[27] = (CFGMSGTRANSMITDATA[27] !== 1'bz) && CFGMSGTRANSMITDATA_delay[27]; // rv 0 + assign CFGMSGTRANSMITDATA_in[28] = (CFGMSGTRANSMITDATA[28] !== 1'bz) && CFGMSGTRANSMITDATA_delay[28]; // rv 0 + assign CFGMSGTRANSMITDATA_in[29] = (CFGMSGTRANSMITDATA[29] !== 1'bz) && CFGMSGTRANSMITDATA_delay[29]; // rv 0 + assign CFGMSGTRANSMITDATA_in[2] = (CFGMSGTRANSMITDATA[2] !== 1'bz) && CFGMSGTRANSMITDATA_delay[2]; // rv 0 + assign CFGMSGTRANSMITDATA_in[30] = (CFGMSGTRANSMITDATA[30] !== 1'bz) && CFGMSGTRANSMITDATA_delay[30]; // rv 0 + assign CFGMSGTRANSMITDATA_in[31] = (CFGMSGTRANSMITDATA[31] !== 1'bz) && CFGMSGTRANSMITDATA_delay[31]; // rv 0 + assign CFGMSGTRANSMITDATA_in[3] = (CFGMSGTRANSMITDATA[3] !== 1'bz) && CFGMSGTRANSMITDATA_delay[3]; // rv 0 + assign CFGMSGTRANSMITDATA_in[4] = (CFGMSGTRANSMITDATA[4] !== 1'bz) && CFGMSGTRANSMITDATA_delay[4]; // rv 0 + assign CFGMSGTRANSMITDATA_in[5] = (CFGMSGTRANSMITDATA[5] !== 1'bz) && CFGMSGTRANSMITDATA_delay[5]; // rv 0 + assign CFGMSGTRANSMITDATA_in[6] = (CFGMSGTRANSMITDATA[6] !== 1'bz) && CFGMSGTRANSMITDATA_delay[6]; // rv 0 + assign CFGMSGTRANSMITDATA_in[7] = (CFGMSGTRANSMITDATA[7] !== 1'bz) && CFGMSGTRANSMITDATA_delay[7]; // rv 0 + assign CFGMSGTRANSMITDATA_in[8] = (CFGMSGTRANSMITDATA[8] !== 1'bz) && CFGMSGTRANSMITDATA_delay[8]; // rv 0 + assign CFGMSGTRANSMITDATA_in[9] = (CFGMSGTRANSMITDATA[9] !== 1'bz) && CFGMSGTRANSMITDATA_delay[9]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[0] = (CFGMSGTRANSMITTYPE[0] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[0]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[1] = (CFGMSGTRANSMITTYPE[1] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[1]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[2] = (CFGMSGTRANSMITTYPE[2] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[2]; // rv 0 + assign CFGMSGTRANSMIT_in = (CFGMSGTRANSMIT !== 1'bz) && CFGMSGTRANSMIT_delay; // rv 0 + assign CFGMSIXRAMREADDATA_in[0] = (CFGMSIXRAMREADDATA[0] !== 1'bz) && CFGMSIXRAMREADDATA_delay[0]; // rv 0 + assign CFGMSIXRAMREADDATA_in[10] = (CFGMSIXRAMREADDATA[10] !== 1'bz) && CFGMSIXRAMREADDATA_delay[10]; // rv 0 + assign CFGMSIXRAMREADDATA_in[11] = (CFGMSIXRAMREADDATA[11] !== 1'bz) && CFGMSIXRAMREADDATA_delay[11]; // rv 0 + assign CFGMSIXRAMREADDATA_in[12] = (CFGMSIXRAMREADDATA[12] !== 1'bz) && CFGMSIXRAMREADDATA_delay[12]; // rv 0 + assign CFGMSIXRAMREADDATA_in[13] = (CFGMSIXRAMREADDATA[13] !== 1'bz) && CFGMSIXRAMREADDATA_delay[13]; // rv 0 + assign CFGMSIXRAMREADDATA_in[14] = (CFGMSIXRAMREADDATA[14] !== 1'bz) && CFGMSIXRAMREADDATA_delay[14]; // rv 0 + assign CFGMSIXRAMREADDATA_in[15] = (CFGMSIXRAMREADDATA[15] !== 1'bz) && CFGMSIXRAMREADDATA_delay[15]; // rv 0 + assign CFGMSIXRAMREADDATA_in[16] = (CFGMSIXRAMREADDATA[16] !== 1'bz) && CFGMSIXRAMREADDATA_delay[16]; // rv 0 + assign CFGMSIXRAMREADDATA_in[17] = (CFGMSIXRAMREADDATA[17] !== 1'bz) && CFGMSIXRAMREADDATA_delay[17]; // rv 0 + assign CFGMSIXRAMREADDATA_in[18] = (CFGMSIXRAMREADDATA[18] !== 1'bz) && CFGMSIXRAMREADDATA_delay[18]; // rv 0 + assign CFGMSIXRAMREADDATA_in[19] = (CFGMSIXRAMREADDATA[19] !== 1'bz) && CFGMSIXRAMREADDATA_delay[19]; // rv 0 + assign CFGMSIXRAMREADDATA_in[1] = (CFGMSIXRAMREADDATA[1] !== 1'bz) && CFGMSIXRAMREADDATA_delay[1]; // rv 0 + assign CFGMSIXRAMREADDATA_in[20] = (CFGMSIXRAMREADDATA[20] !== 1'bz) && CFGMSIXRAMREADDATA_delay[20]; // rv 0 + assign CFGMSIXRAMREADDATA_in[21] = (CFGMSIXRAMREADDATA[21] !== 1'bz) && CFGMSIXRAMREADDATA_delay[21]; // rv 0 + assign CFGMSIXRAMREADDATA_in[22] = (CFGMSIXRAMREADDATA[22] !== 1'bz) && CFGMSIXRAMREADDATA_delay[22]; // rv 0 + assign CFGMSIXRAMREADDATA_in[23] = (CFGMSIXRAMREADDATA[23] !== 1'bz) && CFGMSIXRAMREADDATA_delay[23]; // rv 0 + assign CFGMSIXRAMREADDATA_in[24] = (CFGMSIXRAMREADDATA[24] !== 1'bz) && CFGMSIXRAMREADDATA_delay[24]; // rv 0 + assign CFGMSIXRAMREADDATA_in[25] = (CFGMSIXRAMREADDATA[25] !== 1'bz) && CFGMSIXRAMREADDATA_delay[25]; // rv 0 + assign CFGMSIXRAMREADDATA_in[26] = (CFGMSIXRAMREADDATA[26] !== 1'bz) && CFGMSIXRAMREADDATA_delay[26]; // rv 0 + assign CFGMSIXRAMREADDATA_in[27] = (CFGMSIXRAMREADDATA[27] !== 1'bz) && CFGMSIXRAMREADDATA_delay[27]; // rv 0 + assign CFGMSIXRAMREADDATA_in[28] = (CFGMSIXRAMREADDATA[28] !== 1'bz) && CFGMSIXRAMREADDATA_delay[28]; // rv 0 + assign CFGMSIXRAMREADDATA_in[29] = (CFGMSIXRAMREADDATA[29] !== 1'bz) && CFGMSIXRAMREADDATA_delay[29]; // rv 0 + assign CFGMSIXRAMREADDATA_in[2] = (CFGMSIXRAMREADDATA[2] !== 1'bz) && CFGMSIXRAMREADDATA_delay[2]; // rv 0 + assign CFGMSIXRAMREADDATA_in[30] = (CFGMSIXRAMREADDATA[30] !== 1'bz) && CFGMSIXRAMREADDATA_delay[30]; // rv 0 + assign CFGMSIXRAMREADDATA_in[31] = (CFGMSIXRAMREADDATA[31] !== 1'bz) && CFGMSIXRAMREADDATA_delay[31]; // rv 0 + assign CFGMSIXRAMREADDATA_in[32] = (CFGMSIXRAMREADDATA[32] !== 1'bz) && CFGMSIXRAMREADDATA_delay[32]; // rv 0 + assign CFGMSIXRAMREADDATA_in[33] = (CFGMSIXRAMREADDATA[33] !== 1'bz) && CFGMSIXRAMREADDATA_delay[33]; // rv 0 + assign CFGMSIXRAMREADDATA_in[34] = (CFGMSIXRAMREADDATA[34] !== 1'bz) && CFGMSIXRAMREADDATA_delay[34]; // rv 0 + assign CFGMSIXRAMREADDATA_in[35] = (CFGMSIXRAMREADDATA[35] !== 1'bz) && CFGMSIXRAMREADDATA_delay[35]; // rv 0 + assign CFGMSIXRAMREADDATA_in[3] = (CFGMSIXRAMREADDATA[3] !== 1'bz) && CFGMSIXRAMREADDATA_delay[3]; // rv 0 + assign CFGMSIXRAMREADDATA_in[4] = (CFGMSIXRAMREADDATA[4] !== 1'bz) && CFGMSIXRAMREADDATA_delay[4]; // rv 0 + assign CFGMSIXRAMREADDATA_in[5] = (CFGMSIXRAMREADDATA[5] !== 1'bz) && CFGMSIXRAMREADDATA_delay[5]; // rv 0 + assign CFGMSIXRAMREADDATA_in[6] = (CFGMSIXRAMREADDATA[6] !== 1'bz) && CFGMSIXRAMREADDATA_delay[6]; // rv 0 + assign CFGMSIXRAMREADDATA_in[7] = (CFGMSIXRAMREADDATA[7] !== 1'bz) && CFGMSIXRAMREADDATA_delay[7]; // rv 0 + assign CFGMSIXRAMREADDATA_in[8] = (CFGMSIXRAMREADDATA[8] !== 1'bz) && CFGMSIXRAMREADDATA_delay[8]; // rv 0 + assign CFGMSIXRAMREADDATA_in[9] = (CFGMSIXRAMREADDATA[9] !== 1'bz) && CFGMSIXRAMREADDATA_delay[9]; // rv 0 + assign CFGPMASPML1ENTRYREJECT_in = (CFGPMASPML1ENTRYREJECT !== 1'bz) && CFGPMASPML1ENTRYREJECT_delay; // rv 0 + assign CFGPMASPMTXL0SENTRYDISABLE_in = (CFGPMASPMTXL0SENTRYDISABLE !== 1'bz) && CFGPMASPMTXL0SENTRYDISABLE_delay; // rv 0 + assign CFGPOWERSTATECHANGEACK_in = (CFGPOWERSTATECHANGEACK === 1'bz) || CFGPOWERSTATECHANGEACK_delay; // rv 1 + assign CFGREQPMTRANSITIONL23READY_in = (CFGREQPMTRANSITIONL23READY !== 1'bz) && CFGREQPMTRANSITIONL23READY_delay; // rv 0 + assign CFGREVIDPF0_in[0] = (CFGREVIDPF0[0] !== 1'bz) && CFGREVIDPF0_delay[0]; // rv 0 + assign CFGREVIDPF0_in[1] = (CFGREVIDPF0[1] !== 1'bz) && CFGREVIDPF0_delay[1]; // rv 0 + assign CFGREVIDPF0_in[2] = (CFGREVIDPF0[2] !== 1'bz) && CFGREVIDPF0_delay[2]; // rv 0 + assign CFGREVIDPF0_in[3] = (CFGREVIDPF0[3] !== 1'bz) && CFGREVIDPF0_delay[3]; // rv 0 + assign CFGREVIDPF0_in[4] = (CFGREVIDPF0[4] !== 1'bz) && CFGREVIDPF0_delay[4]; // rv 0 + assign CFGREVIDPF0_in[5] = (CFGREVIDPF0[5] !== 1'bz) && CFGREVIDPF0_delay[5]; // rv 0 + assign CFGREVIDPF0_in[6] = (CFGREVIDPF0[6] !== 1'bz) && CFGREVIDPF0_delay[6]; // rv 0 + assign CFGREVIDPF0_in[7] = (CFGREVIDPF0[7] !== 1'bz) && CFGREVIDPF0_delay[7]; // rv 0 + assign CFGREVIDPF1_in[0] = (CFGREVIDPF1[0] !== 1'bz) && CFGREVIDPF1_delay[0]; // rv 0 + assign CFGREVIDPF1_in[1] = (CFGREVIDPF1[1] !== 1'bz) && CFGREVIDPF1_delay[1]; // rv 0 + assign CFGREVIDPF1_in[2] = (CFGREVIDPF1[2] !== 1'bz) && CFGREVIDPF1_delay[2]; // rv 0 + assign CFGREVIDPF1_in[3] = (CFGREVIDPF1[3] !== 1'bz) && CFGREVIDPF1_delay[3]; // rv 0 + assign CFGREVIDPF1_in[4] = (CFGREVIDPF1[4] !== 1'bz) && CFGREVIDPF1_delay[4]; // rv 0 + assign CFGREVIDPF1_in[5] = (CFGREVIDPF1[5] !== 1'bz) && CFGREVIDPF1_delay[5]; // rv 0 + assign CFGREVIDPF1_in[6] = (CFGREVIDPF1[6] !== 1'bz) && CFGREVIDPF1_delay[6]; // rv 0 + assign CFGREVIDPF1_in[7] = (CFGREVIDPF1[7] !== 1'bz) && CFGREVIDPF1_delay[7]; // rv 0 + assign CFGREVIDPF2_in[0] = (CFGREVIDPF2[0] !== 1'bz) && CFGREVIDPF2_delay[0]; // rv 0 + assign CFGREVIDPF2_in[1] = (CFGREVIDPF2[1] !== 1'bz) && CFGREVIDPF2_delay[1]; // rv 0 + assign CFGREVIDPF2_in[2] = (CFGREVIDPF2[2] !== 1'bz) && CFGREVIDPF2_delay[2]; // rv 0 + assign CFGREVIDPF2_in[3] = (CFGREVIDPF2[3] !== 1'bz) && CFGREVIDPF2_delay[3]; // rv 0 + assign CFGREVIDPF2_in[4] = (CFGREVIDPF2[4] !== 1'bz) && CFGREVIDPF2_delay[4]; // rv 0 + assign CFGREVIDPF2_in[5] = (CFGREVIDPF2[5] !== 1'bz) && CFGREVIDPF2_delay[5]; // rv 0 + assign CFGREVIDPF2_in[6] = (CFGREVIDPF2[6] !== 1'bz) && CFGREVIDPF2_delay[6]; // rv 0 + assign CFGREVIDPF2_in[7] = (CFGREVIDPF2[7] !== 1'bz) && CFGREVIDPF2_delay[7]; // rv 0 + assign CFGREVIDPF3_in[0] = (CFGREVIDPF3[0] !== 1'bz) && CFGREVIDPF3_delay[0]; // rv 0 + assign CFGREVIDPF3_in[1] = (CFGREVIDPF3[1] !== 1'bz) && CFGREVIDPF3_delay[1]; // rv 0 + assign CFGREVIDPF3_in[2] = (CFGREVIDPF3[2] !== 1'bz) && CFGREVIDPF3_delay[2]; // rv 0 + assign CFGREVIDPF3_in[3] = (CFGREVIDPF3[3] !== 1'bz) && CFGREVIDPF3_delay[3]; // rv 0 + assign CFGREVIDPF3_in[4] = (CFGREVIDPF3[4] !== 1'bz) && CFGREVIDPF3_delay[4]; // rv 0 + assign CFGREVIDPF3_in[5] = (CFGREVIDPF3[5] !== 1'bz) && CFGREVIDPF3_delay[5]; // rv 0 + assign CFGREVIDPF3_in[6] = (CFGREVIDPF3[6] !== 1'bz) && CFGREVIDPF3_delay[6]; // rv 0 + assign CFGREVIDPF3_in[7] = (CFGREVIDPF3[7] !== 1'bz) && CFGREVIDPF3_delay[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[0] = (CFGSUBSYSIDPF0[0] !== 1'bz) && CFGSUBSYSIDPF0_delay[0]; // rv 0 + assign CFGSUBSYSIDPF0_in[10] = (CFGSUBSYSIDPF0[10] !== 1'bz) && CFGSUBSYSIDPF0_delay[10]; // rv 0 + assign CFGSUBSYSIDPF0_in[11] = (CFGSUBSYSIDPF0[11] !== 1'bz) && CFGSUBSYSIDPF0_delay[11]; // rv 0 + assign CFGSUBSYSIDPF0_in[12] = (CFGSUBSYSIDPF0[12] !== 1'bz) && CFGSUBSYSIDPF0_delay[12]; // rv 0 + assign CFGSUBSYSIDPF0_in[13] = (CFGSUBSYSIDPF0[13] !== 1'bz) && CFGSUBSYSIDPF0_delay[13]; // rv 0 + assign CFGSUBSYSIDPF0_in[14] = (CFGSUBSYSIDPF0[14] !== 1'bz) && CFGSUBSYSIDPF0_delay[14]; // rv 0 + assign CFGSUBSYSIDPF0_in[15] = (CFGSUBSYSIDPF0[15] !== 1'bz) && CFGSUBSYSIDPF0_delay[15]; // rv 0 + assign CFGSUBSYSIDPF0_in[1] = (CFGSUBSYSIDPF0[1] !== 1'bz) && CFGSUBSYSIDPF0_delay[1]; // rv 0 + assign CFGSUBSYSIDPF0_in[2] = (CFGSUBSYSIDPF0[2] !== 1'bz) && CFGSUBSYSIDPF0_delay[2]; // rv 0 + assign CFGSUBSYSIDPF0_in[3] = (CFGSUBSYSIDPF0[3] !== 1'bz) && CFGSUBSYSIDPF0_delay[3]; // rv 0 + assign CFGSUBSYSIDPF0_in[4] = (CFGSUBSYSIDPF0[4] !== 1'bz) && CFGSUBSYSIDPF0_delay[4]; // rv 0 + assign CFGSUBSYSIDPF0_in[5] = (CFGSUBSYSIDPF0[5] !== 1'bz) && CFGSUBSYSIDPF0_delay[5]; // rv 0 + assign CFGSUBSYSIDPF0_in[6] = (CFGSUBSYSIDPF0[6] !== 1'bz) && CFGSUBSYSIDPF0_delay[6]; // rv 0 + assign CFGSUBSYSIDPF0_in[7] = (CFGSUBSYSIDPF0[7] !== 1'bz) && CFGSUBSYSIDPF0_delay[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[8] = (CFGSUBSYSIDPF0[8] !== 1'bz) && CFGSUBSYSIDPF0_delay[8]; // rv 0 + assign CFGSUBSYSIDPF0_in[9] = (CFGSUBSYSIDPF0[9] !== 1'bz) && CFGSUBSYSIDPF0_delay[9]; // rv 0 + assign CFGSUBSYSIDPF1_in[0] = (CFGSUBSYSIDPF1[0] !== 1'bz) && CFGSUBSYSIDPF1_delay[0]; // rv 0 + assign CFGSUBSYSIDPF1_in[10] = (CFGSUBSYSIDPF1[10] !== 1'bz) && CFGSUBSYSIDPF1_delay[10]; // rv 0 + assign CFGSUBSYSIDPF1_in[11] = (CFGSUBSYSIDPF1[11] !== 1'bz) && CFGSUBSYSIDPF1_delay[11]; // rv 0 + assign CFGSUBSYSIDPF1_in[12] = (CFGSUBSYSIDPF1[12] !== 1'bz) && CFGSUBSYSIDPF1_delay[12]; // rv 0 + assign CFGSUBSYSIDPF1_in[13] = (CFGSUBSYSIDPF1[13] !== 1'bz) && CFGSUBSYSIDPF1_delay[13]; // rv 0 + assign CFGSUBSYSIDPF1_in[14] = (CFGSUBSYSIDPF1[14] !== 1'bz) && CFGSUBSYSIDPF1_delay[14]; // rv 0 + assign CFGSUBSYSIDPF1_in[15] = (CFGSUBSYSIDPF1[15] !== 1'bz) && CFGSUBSYSIDPF1_delay[15]; // rv 0 + assign CFGSUBSYSIDPF1_in[1] = (CFGSUBSYSIDPF1[1] !== 1'bz) && CFGSUBSYSIDPF1_delay[1]; // rv 0 + assign CFGSUBSYSIDPF1_in[2] = (CFGSUBSYSIDPF1[2] !== 1'bz) && CFGSUBSYSIDPF1_delay[2]; // rv 0 + assign CFGSUBSYSIDPF1_in[3] = (CFGSUBSYSIDPF1[3] !== 1'bz) && CFGSUBSYSIDPF1_delay[3]; // rv 0 + assign CFGSUBSYSIDPF1_in[4] = (CFGSUBSYSIDPF1[4] !== 1'bz) && CFGSUBSYSIDPF1_delay[4]; // rv 0 + assign CFGSUBSYSIDPF1_in[5] = (CFGSUBSYSIDPF1[5] !== 1'bz) && CFGSUBSYSIDPF1_delay[5]; // rv 0 + assign CFGSUBSYSIDPF1_in[6] = (CFGSUBSYSIDPF1[6] !== 1'bz) && CFGSUBSYSIDPF1_delay[6]; // rv 0 + assign CFGSUBSYSIDPF1_in[7] = (CFGSUBSYSIDPF1[7] !== 1'bz) && CFGSUBSYSIDPF1_delay[7]; // rv 0 + assign CFGSUBSYSIDPF1_in[8] = (CFGSUBSYSIDPF1[8] !== 1'bz) && CFGSUBSYSIDPF1_delay[8]; // rv 0 + assign CFGSUBSYSIDPF1_in[9] = (CFGSUBSYSIDPF1[9] !== 1'bz) && CFGSUBSYSIDPF1_delay[9]; // rv 0 + assign CFGSUBSYSIDPF2_in[0] = (CFGSUBSYSIDPF2[0] !== 1'bz) && CFGSUBSYSIDPF2_delay[0]; // rv 0 + assign CFGSUBSYSIDPF2_in[10] = (CFGSUBSYSIDPF2[10] !== 1'bz) && CFGSUBSYSIDPF2_delay[10]; // rv 0 + assign CFGSUBSYSIDPF2_in[11] = (CFGSUBSYSIDPF2[11] !== 1'bz) && CFGSUBSYSIDPF2_delay[11]; // rv 0 + assign CFGSUBSYSIDPF2_in[12] = (CFGSUBSYSIDPF2[12] !== 1'bz) && CFGSUBSYSIDPF2_delay[12]; // rv 0 + assign CFGSUBSYSIDPF2_in[13] = (CFGSUBSYSIDPF2[13] !== 1'bz) && CFGSUBSYSIDPF2_delay[13]; // rv 0 + assign CFGSUBSYSIDPF2_in[14] = (CFGSUBSYSIDPF2[14] !== 1'bz) && CFGSUBSYSIDPF2_delay[14]; // rv 0 + assign CFGSUBSYSIDPF2_in[15] = (CFGSUBSYSIDPF2[15] !== 1'bz) && CFGSUBSYSIDPF2_delay[15]; // rv 0 + assign CFGSUBSYSIDPF2_in[1] = (CFGSUBSYSIDPF2[1] !== 1'bz) && CFGSUBSYSIDPF2_delay[1]; // rv 0 + assign CFGSUBSYSIDPF2_in[2] = (CFGSUBSYSIDPF2[2] !== 1'bz) && CFGSUBSYSIDPF2_delay[2]; // rv 0 + assign CFGSUBSYSIDPF2_in[3] = (CFGSUBSYSIDPF2[3] !== 1'bz) && CFGSUBSYSIDPF2_delay[3]; // rv 0 + assign CFGSUBSYSIDPF2_in[4] = (CFGSUBSYSIDPF2[4] !== 1'bz) && CFGSUBSYSIDPF2_delay[4]; // rv 0 + assign CFGSUBSYSIDPF2_in[5] = (CFGSUBSYSIDPF2[5] !== 1'bz) && CFGSUBSYSIDPF2_delay[5]; // rv 0 + assign CFGSUBSYSIDPF2_in[6] = (CFGSUBSYSIDPF2[6] !== 1'bz) && CFGSUBSYSIDPF2_delay[6]; // rv 0 + assign CFGSUBSYSIDPF2_in[7] = (CFGSUBSYSIDPF2[7] !== 1'bz) && CFGSUBSYSIDPF2_delay[7]; // rv 0 + assign CFGSUBSYSIDPF2_in[8] = (CFGSUBSYSIDPF2[8] !== 1'bz) && CFGSUBSYSIDPF2_delay[8]; // rv 0 + assign CFGSUBSYSIDPF2_in[9] = (CFGSUBSYSIDPF2[9] !== 1'bz) && CFGSUBSYSIDPF2_delay[9]; // rv 0 + assign CFGSUBSYSIDPF3_in[0] = (CFGSUBSYSIDPF3[0] !== 1'bz) && CFGSUBSYSIDPF3_delay[0]; // rv 0 + assign CFGSUBSYSIDPF3_in[10] = (CFGSUBSYSIDPF3[10] !== 1'bz) && CFGSUBSYSIDPF3_delay[10]; // rv 0 + assign CFGSUBSYSIDPF3_in[11] = (CFGSUBSYSIDPF3[11] !== 1'bz) && CFGSUBSYSIDPF3_delay[11]; // rv 0 + assign CFGSUBSYSIDPF3_in[12] = (CFGSUBSYSIDPF3[12] !== 1'bz) && CFGSUBSYSIDPF3_delay[12]; // rv 0 + assign CFGSUBSYSIDPF3_in[13] = (CFGSUBSYSIDPF3[13] !== 1'bz) && CFGSUBSYSIDPF3_delay[13]; // rv 0 + assign CFGSUBSYSIDPF3_in[14] = (CFGSUBSYSIDPF3[14] !== 1'bz) && CFGSUBSYSIDPF3_delay[14]; // rv 0 + assign CFGSUBSYSIDPF3_in[15] = (CFGSUBSYSIDPF3[15] !== 1'bz) && CFGSUBSYSIDPF3_delay[15]; // rv 0 + assign CFGSUBSYSIDPF3_in[1] = (CFGSUBSYSIDPF3[1] !== 1'bz) && CFGSUBSYSIDPF3_delay[1]; // rv 0 + assign CFGSUBSYSIDPF3_in[2] = (CFGSUBSYSIDPF3[2] !== 1'bz) && CFGSUBSYSIDPF3_delay[2]; // rv 0 + assign CFGSUBSYSIDPF3_in[3] = (CFGSUBSYSIDPF3[3] !== 1'bz) && CFGSUBSYSIDPF3_delay[3]; // rv 0 + assign CFGSUBSYSIDPF3_in[4] = (CFGSUBSYSIDPF3[4] !== 1'bz) && CFGSUBSYSIDPF3_delay[4]; // rv 0 + assign CFGSUBSYSIDPF3_in[5] = (CFGSUBSYSIDPF3[5] !== 1'bz) && CFGSUBSYSIDPF3_delay[5]; // rv 0 + assign CFGSUBSYSIDPF3_in[6] = (CFGSUBSYSIDPF3[6] !== 1'bz) && CFGSUBSYSIDPF3_delay[6]; // rv 0 + assign CFGSUBSYSIDPF3_in[7] = (CFGSUBSYSIDPF3[7] !== 1'bz) && CFGSUBSYSIDPF3_delay[7]; // rv 0 + assign CFGSUBSYSIDPF3_in[8] = (CFGSUBSYSIDPF3[8] !== 1'bz) && CFGSUBSYSIDPF3_delay[8]; // rv 0 + assign CFGSUBSYSIDPF3_in[9] = (CFGSUBSYSIDPF3[9] !== 1'bz) && CFGSUBSYSIDPF3_delay[9]; // rv 0 + assign CFGSUBSYSVENDID_in[0] = (CFGSUBSYSVENDID[0] !== 1'bz) && CFGSUBSYSVENDID_delay[0]; // rv 0 + assign CFGSUBSYSVENDID_in[10] = (CFGSUBSYSVENDID[10] !== 1'bz) && CFGSUBSYSVENDID_delay[10]; // rv 0 + assign CFGSUBSYSVENDID_in[11] = (CFGSUBSYSVENDID[11] !== 1'bz) && CFGSUBSYSVENDID_delay[11]; // rv 0 + assign CFGSUBSYSVENDID_in[12] = (CFGSUBSYSVENDID[12] !== 1'bz) && CFGSUBSYSVENDID_delay[12]; // rv 0 + assign CFGSUBSYSVENDID_in[13] = (CFGSUBSYSVENDID[13] !== 1'bz) && CFGSUBSYSVENDID_delay[13]; // rv 0 + assign CFGSUBSYSVENDID_in[14] = (CFGSUBSYSVENDID[14] !== 1'bz) && CFGSUBSYSVENDID_delay[14]; // rv 0 + assign CFGSUBSYSVENDID_in[15] = (CFGSUBSYSVENDID[15] !== 1'bz) && CFGSUBSYSVENDID_delay[15]; // rv 0 + assign CFGSUBSYSVENDID_in[1] = (CFGSUBSYSVENDID[1] !== 1'bz) && CFGSUBSYSVENDID_delay[1]; // rv 0 + assign CFGSUBSYSVENDID_in[2] = (CFGSUBSYSVENDID[2] !== 1'bz) && CFGSUBSYSVENDID_delay[2]; // rv 0 + assign CFGSUBSYSVENDID_in[3] = (CFGSUBSYSVENDID[3] !== 1'bz) && CFGSUBSYSVENDID_delay[3]; // rv 0 + assign CFGSUBSYSVENDID_in[4] = (CFGSUBSYSVENDID[4] !== 1'bz) && CFGSUBSYSVENDID_delay[4]; // rv 0 + assign CFGSUBSYSVENDID_in[5] = (CFGSUBSYSVENDID[5] !== 1'bz) && CFGSUBSYSVENDID_delay[5]; // rv 0 + assign CFGSUBSYSVENDID_in[6] = (CFGSUBSYSVENDID[6] !== 1'bz) && CFGSUBSYSVENDID_delay[6]; // rv 0 + assign CFGSUBSYSVENDID_in[7] = (CFGSUBSYSVENDID[7] !== 1'bz) && CFGSUBSYSVENDID_delay[7]; // rv 0 + assign CFGSUBSYSVENDID_in[8] = (CFGSUBSYSVENDID[8] !== 1'bz) && CFGSUBSYSVENDID_delay[8]; // rv 0 + assign CFGSUBSYSVENDID_in[9] = (CFGSUBSYSVENDID[9] !== 1'bz) && CFGSUBSYSVENDID_delay[9]; // rv 0 + assign CFGTPHRAMREADDATA_in[0] = (CFGTPHRAMREADDATA[0] !== 1'bz) && CFGTPHRAMREADDATA_delay[0]; // rv 0 + assign CFGTPHRAMREADDATA_in[10] = (CFGTPHRAMREADDATA[10] !== 1'bz) && CFGTPHRAMREADDATA_delay[10]; // rv 0 + assign CFGTPHRAMREADDATA_in[11] = (CFGTPHRAMREADDATA[11] !== 1'bz) && CFGTPHRAMREADDATA_delay[11]; // rv 0 + assign CFGTPHRAMREADDATA_in[12] = (CFGTPHRAMREADDATA[12] !== 1'bz) && CFGTPHRAMREADDATA_delay[12]; // rv 0 + assign CFGTPHRAMREADDATA_in[13] = (CFGTPHRAMREADDATA[13] !== 1'bz) && CFGTPHRAMREADDATA_delay[13]; // rv 0 + assign CFGTPHRAMREADDATA_in[14] = (CFGTPHRAMREADDATA[14] !== 1'bz) && CFGTPHRAMREADDATA_delay[14]; // rv 0 + assign CFGTPHRAMREADDATA_in[15] = (CFGTPHRAMREADDATA[15] !== 1'bz) && CFGTPHRAMREADDATA_delay[15]; // rv 0 + assign CFGTPHRAMREADDATA_in[16] = (CFGTPHRAMREADDATA[16] !== 1'bz) && CFGTPHRAMREADDATA_delay[16]; // rv 0 + assign CFGTPHRAMREADDATA_in[17] = (CFGTPHRAMREADDATA[17] !== 1'bz) && CFGTPHRAMREADDATA_delay[17]; // rv 0 + assign CFGTPHRAMREADDATA_in[18] = (CFGTPHRAMREADDATA[18] !== 1'bz) && CFGTPHRAMREADDATA_delay[18]; // rv 0 + assign CFGTPHRAMREADDATA_in[19] = (CFGTPHRAMREADDATA[19] !== 1'bz) && CFGTPHRAMREADDATA_delay[19]; // rv 0 + assign CFGTPHRAMREADDATA_in[1] = (CFGTPHRAMREADDATA[1] !== 1'bz) && CFGTPHRAMREADDATA_delay[1]; // rv 0 + assign CFGTPHRAMREADDATA_in[20] = (CFGTPHRAMREADDATA[20] !== 1'bz) && CFGTPHRAMREADDATA_delay[20]; // rv 0 + assign CFGTPHRAMREADDATA_in[21] = (CFGTPHRAMREADDATA[21] !== 1'bz) && CFGTPHRAMREADDATA_delay[21]; // rv 0 + assign CFGTPHRAMREADDATA_in[22] = (CFGTPHRAMREADDATA[22] !== 1'bz) && CFGTPHRAMREADDATA_delay[22]; // rv 0 + assign CFGTPHRAMREADDATA_in[23] = (CFGTPHRAMREADDATA[23] !== 1'bz) && CFGTPHRAMREADDATA_delay[23]; // rv 0 + assign CFGTPHRAMREADDATA_in[24] = (CFGTPHRAMREADDATA[24] !== 1'bz) && CFGTPHRAMREADDATA_delay[24]; // rv 0 + assign CFGTPHRAMREADDATA_in[25] = (CFGTPHRAMREADDATA[25] !== 1'bz) && CFGTPHRAMREADDATA_delay[25]; // rv 0 + assign CFGTPHRAMREADDATA_in[26] = (CFGTPHRAMREADDATA[26] !== 1'bz) && CFGTPHRAMREADDATA_delay[26]; // rv 0 + assign CFGTPHRAMREADDATA_in[27] = (CFGTPHRAMREADDATA[27] !== 1'bz) && CFGTPHRAMREADDATA_delay[27]; // rv 0 + assign CFGTPHRAMREADDATA_in[28] = (CFGTPHRAMREADDATA[28] !== 1'bz) && CFGTPHRAMREADDATA_delay[28]; // rv 0 + assign CFGTPHRAMREADDATA_in[29] = (CFGTPHRAMREADDATA[29] !== 1'bz) && CFGTPHRAMREADDATA_delay[29]; // rv 0 + assign CFGTPHRAMREADDATA_in[2] = (CFGTPHRAMREADDATA[2] !== 1'bz) && CFGTPHRAMREADDATA_delay[2]; // rv 0 + assign CFGTPHRAMREADDATA_in[30] = (CFGTPHRAMREADDATA[30] !== 1'bz) && CFGTPHRAMREADDATA_delay[30]; // rv 0 + assign CFGTPHRAMREADDATA_in[31] = (CFGTPHRAMREADDATA[31] !== 1'bz) && CFGTPHRAMREADDATA_delay[31]; // rv 0 + assign CFGTPHRAMREADDATA_in[32] = (CFGTPHRAMREADDATA[32] !== 1'bz) && CFGTPHRAMREADDATA_delay[32]; // rv 0 + assign CFGTPHRAMREADDATA_in[33] = (CFGTPHRAMREADDATA[33] !== 1'bz) && CFGTPHRAMREADDATA_delay[33]; // rv 0 + assign CFGTPHRAMREADDATA_in[34] = (CFGTPHRAMREADDATA[34] !== 1'bz) && CFGTPHRAMREADDATA_delay[34]; // rv 0 + assign CFGTPHRAMREADDATA_in[35] = (CFGTPHRAMREADDATA[35] !== 1'bz) && CFGTPHRAMREADDATA_delay[35]; // rv 0 + assign CFGTPHRAMREADDATA_in[3] = (CFGTPHRAMREADDATA[3] !== 1'bz) && CFGTPHRAMREADDATA_delay[3]; // rv 0 + assign CFGTPHRAMREADDATA_in[4] = (CFGTPHRAMREADDATA[4] !== 1'bz) && CFGTPHRAMREADDATA_delay[4]; // rv 0 + assign CFGTPHRAMREADDATA_in[5] = (CFGTPHRAMREADDATA[5] !== 1'bz) && CFGTPHRAMREADDATA_delay[5]; // rv 0 + assign CFGTPHRAMREADDATA_in[6] = (CFGTPHRAMREADDATA[6] !== 1'bz) && CFGTPHRAMREADDATA_delay[6]; // rv 0 + assign CFGTPHRAMREADDATA_in[7] = (CFGTPHRAMREADDATA[7] !== 1'bz) && CFGTPHRAMREADDATA_delay[7]; // rv 0 + assign CFGTPHRAMREADDATA_in[8] = (CFGTPHRAMREADDATA[8] !== 1'bz) && CFGTPHRAMREADDATA_delay[8]; // rv 0 + assign CFGTPHRAMREADDATA_in[9] = (CFGTPHRAMREADDATA[9] !== 1'bz) && CFGTPHRAMREADDATA_delay[9]; // rv 0 + assign CFGVENDID_in[0] = (CFGVENDID[0] !== 1'bz) && CFGVENDID_delay[0]; // rv 0 + assign CFGVENDID_in[10] = (CFGVENDID[10] !== 1'bz) && CFGVENDID_delay[10]; // rv 0 + assign CFGVENDID_in[11] = (CFGVENDID[11] !== 1'bz) && CFGVENDID_delay[11]; // rv 0 + assign CFGVENDID_in[12] = (CFGVENDID[12] !== 1'bz) && CFGVENDID_delay[12]; // rv 0 + assign CFGVENDID_in[13] = (CFGVENDID[13] !== 1'bz) && CFGVENDID_delay[13]; // rv 0 + assign CFGVENDID_in[14] = (CFGVENDID[14] !== 1'bz) && CFGVENDID_delay[14]; // rv 0 + assign CFGVENDID_in[15] = (CFGVENDID[15] !== 1'bz) && CFGVENDID_delay[15]; // rv 0 + assign CFGVENDID_in[1] = (CFGVENDID[1] !== 1'bz) && CFGVENDID_delay[1]; // rv 0 + assign CFGVENDID_in[2] = (CFGVENDID[2] !== 1'bz) && CFGVENDID_delay[2]; // rv 0 + assign CFGVENDID_in[3] = (CFGVENDID[3] !== 1'bz) && CFGVENDID_delay[3]; // rv 0 + assign CFGVENDID_in[4] = (CFGVENDID[4] !== 1'bz) && CFGVENDID_delay[4]; // rv 0 + assign CFGVENDID_in[5] = (CFGVENDID[5] !== 1'bz) && CFGVENDID_delay[5]; // rv 0 + assign CFGVENDID_in[6] = (CFGVENDID[6] !== 1'bz) && CFGVENDID_delay[6]; // rv 0 + assign CFGVENDID_in[7] = (CFGVENDID[7] !== 1'bz) && CFGVENDID_delay[7]; // rv 0 + assign CFGVENDID_in[8] = (CFGVENDID[8] !== 1'bz) && CFGVENDID_delay[8]; // rv 0 + assign CFGVENDID_in[9] = (CFGVENDID[9] !== 1'bz) && CFGVENDID_delay[9]; // rv 0 + assign CFGVFFLRDONE_in = (CFGVFFLRDONE !== 1'bz) && CFGVFFLRDONE_delay; // rv 0 + assign CFGVFFLRFUNCNUM_in[0] = (CFGVFFLRFUNCNUM[0] !== 1'bz) && CFGVFFLRFUNCNUM_delay[0]; // rv 0 + assign CFGVFFLRFUNCNUM_in[1] = (CFGVFFLRFUNCNUM[1] !== 1'bz) && CFGVFFLRFUNCNUM_delay[1]; // rv 0 + assign CFGVFFLRFUNCNUM_in[2] = (CFGVFFLRFUNCNUM[2] !== 1'bz) && CFGVFFLRFUNCNUM_delay[2]; // rv 0 + assign CFGVFFLRFUNCNUM_in[3] = (CFGVFFLRFUNCNUM[3] !== 1'bz) && CFGVFFLRFUNCNUM_delay[3]; // rv 0 + assign CFGVFFLRFUNCNUM_in[4] = (CFGVFFLRFUNCNUM[4] !== 1'bz) && CFGVFFLRFUNCNUM_delay[4]; // rv 0 + assign CFGVFFLRFUNCNUM_in[5] = (CFGVFFLRFUNCNUM[5] !== 1'bz) && CFGVFFLRFUNCNUM_delay[5]; // rv 0 + assign CFGVFFLRFUNCNUM_in[6] = (CFGVFFLRFUNCNUM[6] !== 1'bz) && CFGVFFLRFUNCNUM_delay[6]; // rv 0 + assign CFGVFFLRFUNCNUM_in[7] = (CFGVFFLRFUNCNUM[7] !== 1'bz) && CFGVFFLRFUNCNUM_delay[7]; // rv 0 + assign CONFMCAPREQUESTBYCONF_in = (CONFMCAPREQUESTBYCONF !== 1'bz) && CONFMCAPREQUESTBYCONF_delay; // rv 0 + assign CONFREQDATA_in[0] = (CONFREQDATA[0] !== 1'bz) && CONFREQDATA_delay[0]; // rv 0 + assign CONFREQDATA_in[10] = (CONFREQDATA[10] !== 1'bz) && CONFREQDATA_delay[10]; // rv 0 + assign CONFREQDATA_in[11] = (CONFREQDATA[11] !== 1'bz) && CONFREQDATA_delay[11]; // rv 0 + assign CONFREQDATA_in[12] = (CONFREQDATA[12] !== 1'bz) && CONFREQDATA_delay[12]; // rv 0 + assign CONFREQDATA_in[13] = (CONFREQDATA[13] !== 1'bz) && CONFREQDATA_delay[13]; // rv 0 + assign CONFREQDATA_in[14] = (CONFREQDATA[14] !== 1'bz) && CONFREQDATA_delay[14]; // rv 0 + assign CONFREQDATA_in[15] = (CONFREQDATA[15] !== 1'bz) && CONFREQDATA_delay[15]; // rv 0 + assign CONFREQDATA_in[16] = (CONFREQDATA[16] !== 1'bz) && CONFREQDATA_delay[16]; // rv 0 + assign CONFREQDATA_in[17] = (CONFREQDATA[17] !== 1'bz) && CONFREQDATA_delay[17]; // rv 0 + assign CONFREQDATA_in[18] = (CONFREQDATA[18] !== 1'bz) && CONFREQDATA_delay[18]; // rv 0 + assign CONFREQDATA_in[19] = (CONFREQDATA[19] !== 1'bz) && CONFREQDATA_delay[19]; // rv 0 + assign CONFREQDATA_in[1] = (CONFREQDATA[1] !== 1'bz) && CONFREQDATA_delay[1]; // rv 0 + assign CONFREQDATA_in[20] = (CONFREQDATA[20] !== 1'bz) && CONFREQDATA_delay[20]; // rv 0 + assign CONFREQDATA_in[21] = (CONFREQDATA[21] !== 1'bz) && CONFREQDATA_delay[21]; // rv 0 + assign CONFREQDATA_in[22] = (CONFREQDATA[22] !== 1'bz) && CONFREQDATA_delay[22]; // rv 0 + assign CONFREQDATA_in[23] = (CONFREQDATA[23] !== 1'bz) && CONFREQDATA_delay[23]; // rv 0 + assign CONFREQDATA_in[24] = (CONFREQDATA[24] !== 1'bz) && CONFREQDATA_delay[24]; // rv 0 + assign CONFREQDATA_in[25] = (CONFREQDATA[25] !== 1'bz) && CONFREQDATA_delay[25]; // rv 0 + assign CONFREQDATA_in[26] = (CONFREQDATA[26] !== 1'bz) && CONFREQDATA_delay[26]; // rv 0 + assign CONFREQDATA_in[27] = (CONFREQDATA[27] !== 1'bz) && CONFREQDATA_delay[27]; // rv 0 + assign CONFREQDATA_in[28] = (CONFREQDATA[28] !== 1'bz) && CONFREQDATA_delay[28]; // rv 0 + assign CONFREQDATA_in[29] = (CONFREQDATA[29] !== 1'bz) && CONFREQDATA_delay[29]; // rv 0 + assign CONFREQDATA_in[2] = (CONFREQDATA[2] !== 1'bz) && CONFREQDATA_delay[2]; // rv 0 + assign CONFREQDATA_in[30] = (CONFREQDATA[30] !== 1'bz) && CONFREQDATA_delay[30]; // rv 0 + assign CONFREQDATA_in[31] = (CONFREQDATA[31] !== 1'bz) && CONFREQDATA_delay[31]; // rv 0 + assign CONFREQDATA_in[3] = (CONFREQDATA[3] !== 1'bz) && CONFREQDATA_delay[3]; // rv 0 + assign CONFREQDATA_in[4] = (CONFREQDATA[4] !== 1'bz) && CONFREQDATA_delay[4]; // rv 0 + assign CONFREQDATA_in[5] = (CONFREQDATA[5] !== 1'bz) && CONFREQDATA_delay[5]; // rv 0 + assign CONFREQDATA_in[6] = (CONFREQDATA[6] !== 1'bz) && CONFREQDATA_delay[6]; // rv 0 + assign CONFREQDATA_in[7] = (CONFREQDATA[7] !== 1'bz) && CONFREQDATA_delay[7]; // rv 0 + assign CONFREQDATA_in[8] = (CONFREQDATA[8] !== 1'bz) && CONFREQDATA_delay[8]; // rv 0 + assign CONFREQDATA_in[9] = (CONFREQDATA[9] !== 1'bz) && CONFREQDATA_delay[9]; // rv 0 + assign CONFREQREGNUM_in[0] = (CONFREQREGNUM[0] !== 1'bz) && CONFREQREGNUM_delay[0]; // rv 0 + assign CONFREQREGNUM_in[1] = (CONFREQREGNUM[1] !== 1'bz) && CONFREQREGNUM_delay[1]; // rv 0 + assign CONFREQREGNUM_in[2] = (CONFREQREGNUM[2] !== 1'bz) && CONFREQREGNUM_delay[2]; // rv 0 + assign CONFREQREGNUM_in[3] = (CONFREQREGNUM[3] !== 1'bz) && CONFREQREGNUM_delay[3]; // rv 0 + assign CONFREQTYPE_in[0] = (CONFREQTYPE[0] !== 1'bz) && CONFREQTYPE_delay[0]; // rv 0 + assign CONFREQTYPE_in[1] = (CONFREQTYPE[1] !== 1'bz) && CONFREQTYPE_delay[1]; // rv 0 + assign CONFREQVALID_in = (CONFREQVALID !== 1'bz) && CONFREQVALID_delay; // rv 0 + assign CORECLK_in = (CORECLK !== 1'bz) && CORECLK_delay; // rv 0 + assign DBGSEL0_in[0] = (DBGSEL0[0] !== 1'bz) && DBGSEL0_delay[0]; // rv 0 + assign DBGSEL0_in[1] = (DBGSEL0[1] !== 1'bz) && DBGSEL0_delay[1]; // rv 0 + assign DBGSEL0_in[2] = (DBGSEL0[2] !== 1'bz) && DBGSEL0_delay[2]; // rv 0 + assign DBGSEL0_in[3] = (DBGSEL0[3] !== 1'bz) && DBGSEL0_delay[3]; // rv 0 + assign DBGSEL0_in[4] = (DBGSEL0[4] !== 1'bz) && DBGSEL0_delay[4]; // rv 0 + assign DBGSEL0_in[5] = (DBGSEL0[5] !== 1'bz) && DBGSEL0_delay[5]; // rv 0 + assign DBGSEL1_in[0] = (DBGSEL1[0] !== 1'bz) && DBGSEL1_delay[0]; // rv 0 + assign DBGSEL1_in[1] = (DBGSEL1[1] !== 1'bz) && DBGSEL1_delay[1]; // rv 0 + assign DBGSEL1_in[2] = (DBGSEL1[2] !== 1'bz) && DBGSEL1_delay[2]; // rv 0 + assign DBGSEL1_in[3] = (DBGSEL1[3] !== 1'bz) && DBGSEL1_delay[3]; // rv 0 + assign DBGSEL1_in[4] = (DBGSEL1[4] !== 1'bz) && DBGSEL1_delay[4]; // rv 0 + assign DBGSEL1_in[5] = (DBGSEL1[5] !== 1'bz) && DBGSEL1_delay[5]; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign MAXISCQTREADY_in[0] = (MAXISCQTREADY[0] !== 1'bz) && MAXISCQTREADY_delay[0]; // rv 0 + assign MAXISCQTREADY_in[10] = (MAXISCQTREADY[10] !== 1'bz) && MAXISCQTREADY_delay[10]; // rv 0 + assign MAXISCQTREADY_in[11] = (MAXISCQTREADY[11] !== 1'bz) && MAXISCQTREADY_delay[11]; // rv 0 + assign MAXISCQTREADY_in[12] = (MAXISCQTREADY[12] !== 1'bz) && MAXISCQTREADY_delay[12]; // rv 0 + assign MAXISCQTREADY_in[13] = (MAXISCQTREADY[13] !== 1'bz) && MAXISCQTREADY_delay[13]; // rv 0 + assign MAXISCQTREADY_in[14] = (MAXISCQTREADY[14] !== 1'bz) && MAXISCQTREADY_delay[14]; // rv 0 + assign MAXISCQTREADY_in[15] = (MAXISCQTREADY[15] !== 1'bz) && MAXISCQTREADY_delay[15]; // rv 0 + assign MAXISCQTREADY_in[16] = (MAXISCQTREADY[16] !== 1'bz) && MAXISCQTREADY_delay[16]; // rv 0 + assign MAXISCQTREADY_in[17] = (MAXISCQTREADY[17] !== 1'bz) && MAXISCQTREADY_delay[17]; // rv 0 + assign MAXISCQTREADY_in[18] = (MAXISCQTREADY[18] !== 1'bz) && MAXISCQTREADY_delay[18]; // rv 0 + assign MAXISCQTREADY_in[19] = (MAXISCQTREADY[19] !== 1'bz) && MAXISCQTREADY_delay[19]; // rv 0 + assign MAXISCQTREADY_in[1] = (MAXISCQTREADY[1] !== 1'bz) && MAXISCQTREADY_delay[1]; // rv 0 + assign MAXISCQTREADY_in[20] = (MAXISCQTREADY[20] !== 1'bz) && MAXISCQTREADY_delay[20]; // rv 0 + assign MAXISCQTREADY_in[21] = (MAXISCQTREADY[21] !== 1'bz) && MAXISCQTREADY_delay[21]; // rv 0 + assign MAXISCQTREADY_in[2] = (MAXISCQTREADY[2] !== 1'bz) && MAXISCQTREADY_delay[2]; // rv 0 + assign MAXISCQTREADY_in[3] = (MAXISCQTREADY[3] !== 1'bz) && MAXISCQTREADY_delay[3]; // rv 0 + assign MAXISCQTREADY_in[4] = (MAXISCQTREADY[4] !== 1'bz) && MAXISCQTREADY_delay[4]; // rv 0 + assign MAXISCQTREADY_in[5] = (MAXISCQTREADY[5] !== 1'bz) && MAXISCQTREADY_delay[5]; // rv 0 + assign MAXISCQTREADY_in[6] = (MAXISCQTREADY[6] !== 1'bz) && MAXISCQTREADY_delay[6]; // rv 0 + assign MAXISCQTREADY_in[7] = (MAXISCQTREADY[7] !== 1'bz) && MAXISCQTREADY_delay[7]; // rv 0 + assign MAXISCQTREADY_in[8] = (MAXISCQTREADY[8] !== 1'bz) && MAXISCQTREADY_delay[8]; // rv 0 + assign MAXISCQTREADY_in[9] = (MAXISCQTREADY[9] !== 1'bz) && MAXISCQTREADY_delay[9]; // rv 0 + assign MAXISRCTREADY_in[0] = (MAXISRCTREADY[0] !== 1'bz) && MAXISRCTREADY_delay[0]; // rv 0 + assign MAXISRCTREADY_in[10] = (MAXISRCTREADY[10] !== 1'bz) && MAXISRCTREADY_delay[10]; // rv 0 + assign MAXISRCTREADY_in[11] = (MAXISRCTREADY[11] !== 1'bz) && MAXISRCTREADY_delay[11]; // rv 0 + assign MAXISRCTREADY_in[12] = (MAXISRCTREADY[12] !== 1'bz) && MAXISRCTREADY_delay[12]; // rv 0 + assign MAXISRCTREADY_in[13] = (MAXISRCTREADY[13] !== 1'bz) && MAXISRCTREADY_delay[13]; // rv 0 + assign MAXISRCTREADY_in[14] = (MAXISRCTREADY[14] !== 1'bz) && MAXISRCTREADY_delay[14]; // rv 0 + assign MAXISRCTREADY_in[15] = (MAXISRCTREADY[15] !== 1'bz) && MAXISRCTREADY_delay[15]; // rv 0 + assign MAXISRCTREADY_in[16] = (MAXISRCTREADY[16] !== 1'bz) && MAXISRCTREADY_delay[16]; // rv 0 + assign MAXISRCTREADY_in[17] = (MAXISRCTREADY[17] !== 1'bz) && MAXISRCTREADY_delay[17]; // rv 0 + assign MAXISRCTREADY_in[18] = (MAXISRCTREADY[18] !== 1'bz) && MAXISRCTREADY_delay[18]; // rv 0 + assign MAXISRCTREADY_in[19] = (MAXISRCTREADY[19] !== 1'bz) && MAXISRCTREADY_delay[19]; // rv 0 + assign MAXISRCTREADY_in[1] = (MAXISRCTREADY[1] !== 1'bz) && MAXISRCTREADY_delay[1]; // rv 0 + assign MAXISRCTREADY_in[20] = (MAXISRCTREADY[20] !== 1'bz) && MAXISRCTREADY_delay[20]; // rv 0 + assign MAXISRCTREADY_in[21] = (MAXISRCTREADY[21] !== 1'bz) && MAXISRCTREADY_delay[21]; // rv 0 + assign MAXISRCTREADY_in[2] = (MAXISRCTREADY[2] !== 1'bz) && MAXISRCTREADY_delay[2]; // rv 0 + assign MAXISRCTREADY_in[3] = (MAXISRCTREADY[3] !== 1'bz) && MAXISRCTREADY_delay[3]; // rv 0 + assign MAXISRCTREADY_in[4] = (MAXISRCTREADY[4] !== 1'bz) && MAXISRCTREADY_delay[4]; // rv 0 + assign MAXISRCTREADY_in[5] = (MAXISRCTREADY[5] !== 1'bz) && MAXISRCTREADY_delay[5]; // rv 0 + assign MAXISRCTREADY_in[6] = (MAXISRCTREADY[6] !== 1'bz) && MAXISRCTREADY_delay[6]; // rv 0 + assign MAXISRCTREADY_in[7] = (MAXISRCTREADY[7] !== 1'bz) && MAXISRCTREADY_delay[7]; // rv 0 + assign MAXISRCTREADY_in[8] = (MAXISRCTREADY[8] !== 1'bz) && MAXISRCTREADY_delay[8]; // rv 0 + assign MAXISRCTREADY_in[9] = (MAXISRCTREADY[9] !== 1'bz) && MAXISRCTREADY_delay[9]; // rv 0 + assign MIREPLAYRAMERRCOR_in[0] = (MIREPLAYRAMERRCOR[0] !== 1'bz) && MIREPLAYRAMERRCOR_delay[0]; // rv 0 + assign MIREPLAYRAMERRCOR_in[1] = (MIREPLAYRAMERRCOR[1] !== 1'bz) && MIREPLAYRAMERRCOR_delay[1]; // rv 0 + assign MIREPLAYRAMERRCOR_in[2] = (MIREPLAYRAMERRCOR[2] !== 1'bz) && MIREPLAYRAMERRCOR_delay[2]; // rv 0 + assign MIREPLAYRAMERRCOR_in[3] = (MIREPLAYRAMERRCOR[3] !== 1'bz) && MIREPLAYRAMERRCOR_delay[3]; // rv 0 + assign MIREPLAYRAMERRCOR_in[4] = (MIREPLAYRAMERRCOR[4] !== 1'bz) && MIREPLAYRAMERRCOR_delay[4]; // rv 0 + assign MIREPLAYRAMERRCOR_in[5] = (MIREPLAYRAMERRCOR[5] !== 1'bz) && MIREPLAYRAMERRCOR_delay[5]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[0] = (MIREPLAYRAMERRUNCOR[0] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[0]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[1] = (MIREPLAYRAMERRUNCOR[1] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[1]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[2] = (MIREPLAYRAMERRUNCOR[2] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[2]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[3] = (MIREPLAYRAMERRUNCOR[3] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[3]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[4] = (MIREPLAYRAMERRUNCOR[4] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[4]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[5] = (MIREPLAYRAMERRUNCOR[5] !== 1'bz) && MIREPLAYRAMERRUNCOR_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[0] = (MIREPLAYRAMREADDATA0[0] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[0]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[100] = (MIREPLAYRAMREADDATA0[100] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[100]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[101] = (MIREPLAYRAMREADDATA0[101] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[101]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[102] = (MIREPLAYRAMREADDATA0[102] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[102]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[103] = (MIREPLAYRAMREADDATA0[103] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[103]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[104] = (MIREPLAYRAMREADDATA0[104] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[104]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[105] = (MIREPLAYRAMREADDATA0[105] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[105]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[106] = (MIREPLAYRAMREADDATA0[106] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[106]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[107] = (MIREPLAYRAMREADDATA0[107] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[107]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[108] = (MIREPLAYRAMREADDATA0[108] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[108]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[109] = (MIREPLAYRAMREADDATA0[109] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[109]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[10] = (MIREPLAYRAMREADDATA0[10] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[10]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[110] = (MIREPLAYRAMREADDATA0[110] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[110]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[111] = (MIREPLAYRAMREADDATA0[111] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[111]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[112] = (MIREPLAYRAMREADDATA0[112] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[112]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[113] = (MIREPLAYRAMREADDATA0[113] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[113]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[114] = (MIREPLAYRAMREADDATA0[114] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[114]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[115] = (MIREPLAYRAMREADDATA0[115] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[115]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[116] = (MIREPLAYRAMREADDATA0[116] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[116]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[117] = (MIREPLAYRAMREADDATA0[117] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[117]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[118] = (MIREPLAYRAMREADDATA0[118] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[118]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[119] = (MIREPLAYRAMREADDATA0[119] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[119]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[11] = (MIREPLAYRAMREADDATA0[11] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[11]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[120] = (MIREPLAYRAMREADDATA0[120] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[120]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[121] = (MIREPLAYRAMREADDATA0[121] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[121]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[122] = (MIREPLAYRAMREADDATA0[122] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[122]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[123] = (MIREPLAYRAMREADDATA0[123] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[123]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[124] = (MIREPLAYRAMREADDATA0[124] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[124]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[125] = (MIREPLAYRAMREADDATA0[125] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[125]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[126] = (MIREPLAYRAMREADDATA0[126] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[126]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[127] = (MIREPLAYRAMREADDATA0[127] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[127]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[12] = (MIREPLAYRAMREADDATA0[12] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[12]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[13] = (MIREPLAYRAMREADDATA0[13] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[13]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[14] = (MIREPLAYRAMREADDATA0[14] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[14]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[15] = (MIREPLAYRAMREADDATA0[15] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[15]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[16] = (MIREPLAYRAMREADDATA0[16] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[16]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[17] = (MIREPLAYRAMREADDATA0[17] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[17]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[18] = (MIREPLAYRAMREADDATA0[18] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[18]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[19] = (MIREPLAYRAMREADDATA0[19] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[19]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[1] = (MIREPLAYRAMREADDATA0[1] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[1]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[20] = (MIREPLAYRAMREADDATA0[20] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[20]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[21] = (MIREPLAYRAMREADDATA0[21] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[21]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[22] = (MIREPLAYRAMREADDATA0[22] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[22]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[23] = (MIREPLAYRAMREADDATA0[23] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[23]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[24] = (MIREPLAYRAMREADDATA0[24] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[24]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[25] = (MIREPLAYRAMREADDATA0[25] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[25]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[26] = (MIREPLAYRAMREADDATA0[26] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[26]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[27] = (MIREPLAYRAMREADDATA0[27] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[27]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[28] = (MIREPLAYRAMREADDATA0[28] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[28]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[29] = (MIREPLAYRAMREADDATA0[29] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[29]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[2] = (MIREPLAYRAMREADDATA0[2] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[2]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[30] = (MIREPLAYRAMREADDATA0[30] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[30]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[31] = (MIREPLAYRAMREADDATA0[31] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[31]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[32] = (MIREPLAYRAMREADDATA0[32] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[32]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[33] = (MIREPLAYRAMREADDATA0[33] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[33]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[34] = (MIREPLAYRAMREADDATA0[34] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[34]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[35] = (MIREPLAYRAMREADDATA0[35] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[35]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[36] = (MIREPLAYRAMREADDATA0[36] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[36]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[37] = (MIREPLAYRAMREADDATA0[37] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[37]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[38] = (MIREPLAYRAMREADDATA0[38] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[38]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[39] = (MIREPLAYRAMREADDATA0[39] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[39]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[3] = (MIREPLAYRAMREADDATA0[3] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[3]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[40] = (MIREPLAYRAMREADDATA0[40] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[40]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[41] = (MIREPLAYRAMREADDATA0[41] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[41]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[42] = (MIREPLAYRAMREADDATA0[42] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[42]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[43] = (MIREPLAYRAMREADDATA0[43] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[43]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[44] = (MIREPLAYRAMREADDATA0[44] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[44]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[45] = (MIREPLAYRAMREADDATA0[45] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[45]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[46] = (MIREPLAYRAMREADDATA0[46] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[46]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[47] = (MIREPLAYRAMREADDATA0[47] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[47]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[48] = (MIREPLAYRAMREADDATA0[48] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[48]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[49] = (MIREPLAYRAMREADDATA0[49] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[49]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[4] = (MIREPLAYRAMREADDATA0[4] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[4]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[50] = (MIREPLAYRAMREADDATA0[50] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[50]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[51] = (MIREPLAYRAMREADDATA0[51] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[51]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[52] = (MIREPLAYRAMREADDATA0[52] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[52]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[53] = (MIREPLAYRAMREADDATA0[53] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[53]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[54] = (MIREPLAYRAMREADDATA0[54] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[54]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[55] = (MIREPLAYRAMREADDATA0[55] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[55]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[56] = (MIREPLAYRAMREADDATA0[56] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[56]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[57] = (MIREPLAYRAMREADDATA0[57] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[57]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[58] = (MIREPLAYRAMREADDATA0[58] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[58]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[59] = (MIREPLAYRAMREADDATA0[59] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[59]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[5] = (MIREPLAYRAMREADDATA0[5] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[60] = (MIREPLAYRAMREADDATA0[60] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[60]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[61] = (MIREPLAYRAMREADDATA0[61] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[61]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[62] = (MIREPLAYRAMREADDATA0[62] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[62]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[63] = (MIREPLAYRAMREADDATA0[63] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[63]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[64] = (MIREPLAYRAMREADDATA0[64] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[64]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[65] = (MIREPLAYRAMREADDATA0[65] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[65]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[66] = (MIREPLAYRAMREADDATA0[66] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[66]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[67] = (MIREPLAYRAMREADDATA0[67] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[67]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[68] = (MIREPLAYRAMREADDATA0[68] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[68]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[69] = (MIREPLAYRAMREADDATA0[69] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[69]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[6] = (MIREPLAYRAMREADDATA0[6] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[6]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[70] = (MIREPLAYRAMREADDATA0[70] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[70]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[71] = (MIREPLAYRAMREADDATA0[71] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[71]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[72] = (MIREPLAYRAMREADDATA0[72] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[72]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[73] = (MIREPLAYRAMREADDATA0[73] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[73]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[74] = (MIREPLAYRAMREADDATA0[74] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[74]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[75] = (MIREPLAYRAMREADDATA0[75] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[75]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[76] = (MIREPLAYRAMREADDATA0[76] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[76]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[77] = (MIREPLAYRAMREADDATA0[77] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[77]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[78] = (MIREPLAYRAMREADDATA0[78] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[78]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[79] = (MIREPLAYRAMREADDATA0[79] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[79]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[7] = (MIREPLAYRAMREADDATA0[7] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[7]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[80] = (MIREPLAYRAMREADDATA0[80] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[80]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[81] = (MIREPLAYRAMREADDATA0[81] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[81]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[82] = (MIREPLAYRAMREADDATA0[82] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[82]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[83] = (MIREPLAYRAMREADDATA0[83] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[83]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[84] = (MIREPLAYRAMREADDATA0[84] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[84]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[85] = (MIREPLAYRAMREADDATA0[85] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[85]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[86] = (MIREPLAYRAMREADDATA0[86] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[86]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[87] = (MIREPLAYRAMREADDATA0[87] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[87]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[88] = (MIREPLAYRAMREADDATA0[88] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[88]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[89] = (MIREPLAYRAMREADDATA0[89] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[89]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[8] = (MIREPLAYRAMREADDATA0[8] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[8]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[90] = (MIREPLAYRAMREADDATA0[90] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[90]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[91] = (MIREPLAYRAMREADDATA0[91] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[91]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[92] = (MIREPLAYRAMREADDATA0[92] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[92]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[93] = (MIREPLAYRAMREADDATA0[93] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[93]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[94] = (MIREPLAYRAMREADDATA0[94] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[94]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[95] = (MIREPLAYRAMREADDATA0[95] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[95]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[96] = (MIREPLAYRAMREADDATA0[96] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[96]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[97] = (MIREPLAYRAMREADDATA0[97] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[97]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[98] = (MIREPLAYRAMREADDATA0[98] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[98]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[99] = (MIREPLAYRAMREADDATA0[99] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[99]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[9] = (MIREPLAYRAMREADDATA0[9] !== 1'bz) && MIREPLAYRAMREADDATA0_delay[9]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[0] = (MIREPLAYRAMREADDATA1[0] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[0]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[100] = (MIREPLAYRAMREADDATA1[100] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[100]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[101] = (MIREPLAYRAMREADDATA1[101] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[101]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[102] = (MIREPLAYRAMREADDATA1[102] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[102]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[103] = (MIREPLAYRAMREADDATA1[103] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[103]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[104] = (MIREPLAYRAMREADDATA1[104] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[104]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[105] = (MIREPLAYRAMREADDATA1[105] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[105]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[106] = (MIREPLAYRAMREADDATA1[106] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[106]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[107] = (MIREPLAYRAMREADDATA1[107] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[107]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[108] = (MIREPLAYRAMREADDATA1[108] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[108]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[109] = (MIREPLAYRAMREADDATA1[109] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[109]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[10] = (MIREPLAYRAMREADDATA1[10] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[10]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[110] = (MIREPLAYRAMREADDATA1[110] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[110]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[111] = (MIREPLAYRAMREADDATA1[111] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[111]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[112] = (MIREPLAYRAMREADDATA1[112] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[112]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[113] = (MIREPLAYRAMREADDATA1[113] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[113]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[114] = (MIREPLAYRAMREADDATA1[114] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[114]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[115] = (MIREPLAYRAMREADDATA1[115] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[115]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[116] = (MIREPLAYRAMREADDATA1[116] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[116]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[117] = (MIREPLAYRAMREADDATA1[117] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[117]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[118] = (MIREPLAYRAMREADDATA1[118] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[118]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[119] = (MIREPLAYRAMREADDATA1[119] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[119]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[11] = (MIREPLAYRAMREADDATA1[11] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[11]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[120] = (MIREPLAYRAMREADDATA1[120] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[120]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[121] = (MIREPLAYRAMREADDATA1[121] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[121]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[122] = (MIREPLAYRAMREADDATA1[122] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[122]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[123] = (MIREPLAYRAMREADDATA1[123] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[123]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[124] = (MIREPLAYRAMREADDATA1[124] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[124]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[125] = (MIREPLAYRAMREADDATA1[125] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[125]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[126] = (MIREPLAYRAMREADDATA1[126] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[126]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[127] = (MIREPLAYRAMREADDATA1[127] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[127]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[12] = (MIREPLAYRAMREADDATA1[12] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[12]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[13] = (MIREPLAYRAMREADDATA1[13] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[13]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[14] = (MIREPLAYRAMREADDATA1[14] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[14]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[15] = (MIREPLAYRAMREADDATA1[15] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[15]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[16] = (MIREPLAYRAMREADDATA1[16] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[16]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[17] = (MIREPLAYRAMREADDATA1[17] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[17]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[18] = (MIREPLAYRAMREADDATA1[18] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[18]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[19] = (MIREPLAYRAMREADDATA1[19] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[19]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[1] = (MIREPLAYRAMREADDATA1[1] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[1]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[20] = (MIREPLAYRAMREADDATA1[20] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[20]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[21] = (MIREPLAYRAMREADDATA1[21] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[21]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[22] = (MIREPLAYRAMREADDATA1[22] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[22]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[23] = (MIREPLAYRAMREADDATA1[23] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[23]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[24] = (MIREPLAYRAMREADDATA1[24] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[24]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[25] = (MIREPLAYRAMREADDATA1[25] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[25]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[26] = (MIREPLAYRAMREADDATA1[26] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[26]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[27] = (MIREPLAYRAMREADDATA1[27] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[27]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[28] = (MIREPLAYRAMREADDATA1[28] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[28]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[29] = (MIREPLAYRAMREADDATA1[29] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[29]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[2] = (MIREPLAYRAMREADDATA1[2] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[2]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[30] = (MIREPLAYRAMREADDATA1[30] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[30]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[31] = (MIREPLAYRAMREADDATA1[31] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[31]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[32] = (MIREPLAYRAMREADDATA1[32] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[32]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[33] = (MIREPLAYRAMREADDATA1[33] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[33]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[34] = (MIREPLAYRAMREADDATA1[34] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[34]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[35] = (MIREPLAYRAMREADDATA1[35] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[35]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[36] = (MIREPLAYRAMREADDATA1[36] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[36]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[37] = (MIREPLAYRAMREADDATA1[37] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[37]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[38] = (MIREPLAYRAMREADDATA1[38] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[38]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[39] = (MIREPLAYRAMREADDATA1[39] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[39]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[3] = (MIREPLAYRAMREADDATA1[3] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[3]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[40] = (MIREPLAYRAMREADDATA1[40] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[40]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[41] = (MIREPLAYRAMREADDATA1[41] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[41]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[42] = (MIREPLAYRAMREADDATA1[42] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[42]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[43] = (MIREPLAYRAMREADDATA1[43] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[43]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[44] = (MIREPLAYRAMREADDATA1[44] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[44]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[45] = (MIREPLAYRAMREADDATA1[45] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[45]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[46] = (MIREPLAYRAMREADDATA1[46] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[46]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[47] = (MIREPLAYRAMREADDATA1[47] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[47]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[48] = (MIREPLAYRAMREADDATA1[48] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[48]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[49] = (MIREPLAYRAMREADDATA1[49] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[49]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[4] = (MIREPLAYRAMREADDATA1[4] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[4]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[50] = (MIREPLAYRAMREADDATA1[50] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[50]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[51] = (MIREPLAYRAMREADDATA1[51] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[51]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[52] = (MIREPLAYRAMREADDATA1[52] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[52]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[53] = (MIREPLAYRAMREADDATA1[53] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[53]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[54] = (MIREPLAYRAMREADDATA1[54] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[54]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[55] = (MIREPLAYRAMREADDATA1[55] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[55]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[56] = (MIREPLAYRAMREADDATA1[56] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[56]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[57] = (MIREPLAYRAMREADDATA1[57] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[57]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[58] = (MIREPLAYRAMREADDATA1[58] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[58]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[59] = (MIREPLAYRAMREADDATA1[59] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[59]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[5] = (MIREPLAYRAMREADDATA1[5] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[60] = (MIREPLAYRAMREADDATA1[60] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[60]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[61] = (MIREPLAYRAMREADDATA1[61] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[61]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[62] = (MIREPLAYRAMREADDATA1[62] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[62]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[63] = (MIREPLAYRAMREADDATA1[63] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[63]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[64] = (MIREPLAYRAMREADDATA1[64] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[64]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[65] = (MIREPLAYRAMREADDATA1[65] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[65]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[66] = (MIREPLAYRAMREADDATA1[66] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[66]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[67] = (MIREPLAYRAMREADDATA1[67] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[67]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[68] = (MIREPLAYRAMREADDATA1[68] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[68]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[69] = (MIREPLAYRAMREADDATA1[69] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[69]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[6] = (MIREPLAYRAMREADDATA1[6] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[6]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[70] = (MIREPLAYRAMREADDATA1[70] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[70]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[71] = (MIREPLAYRAMREADDATA1[71] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[71]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[72] = (MIREPLAYRAMREADDATA1[72] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[72]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[73] = (MIREPLAYRAMREADDATA1[73] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[73]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[74] = (MIREPLAYRAMREADDATA1[74] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[74]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[75] = (MIREPLAYRAMREADDATA1[75] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[75]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[76] = (MIREPLAYRAMREADDATA1[76] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[76]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[77] = (MIREPLAYRAMREADDATA1[77] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[77]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[78] = (MIREPLAYRAMREADDATA1[78] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[78]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[79] = (MIREPLAYRAMREADDATA1[79] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[79]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[7] = (MIREPLAYRAMREADDATA1[7] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[7]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[80] = (MIREPLAYRAMREADDATA1[80] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[80]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[81] = (MIREPLAYRAMREADDATA1[81] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[81]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[82] = (MIREPLAYRAMREADDATA1[82] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[82]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[83] = (MIREPLAYRAMREADDATA1[83] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[83]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[84] = (MIREPLAYRAMREADDATA1[84] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[84]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[85] = (MIREPLAYRAMREADDATA1[85] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[85]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[86] = (MIREPLAYRAMREADDATA1[86] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[86]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[87] = (MIREPLAYRAMREADDATA1[87] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[87]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[88] = (MIREPLAYRAMREADDATA1[88] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[88]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[89] = (MIREPLAYRAMREADDATA1[89] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[89]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[8] = (MIREPLAYRAMREADDATA1[8] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[8]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[90] = (MIREPLAYRAMREADDATA1[90] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[90]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[91] = (MIREPLAYRAMREADDATA1[91] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[91]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[92] = (MIREPLAYRAMREADDATA1[92] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[92]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[93] = (MIREPLAYRAMREADDATA1[93] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[93]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[94] = (MIREPLAYRAMREADDATA1[94] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[94]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[95] = (MIREPLAYRAMREADDATA1[95] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[95]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[96] = (MIREPLAYRAMREADDATA1[96] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[96]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[97] = (MIREPLAYRAMREADDATA1[97] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[97]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[98] = (MIREPLAYRAMREADDATA1[98] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[98]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[99] = (MIREPLAYRAMREADDATA1[99] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[99]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[9] = (MIREPLAYRAMREADDATA1[9] !== 1'bz) && MIREPLAYRAMREADDATA1_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[0] = (MIRXCOMPLETIONRAMERRCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[10] = (MIRXCOMPLETIONRAMERRCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[11] = (MIRXCOMPLETIONRAMERRCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[1] = (MIRXCOMPLETIONRAMERRCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[2] = (MIRXCOMPLETIONRAMERRCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[3] = (MIRXCOMPLETIONRAMERRCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[4] = (MIRXCOMPLETIONRAMERRCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[5] = (MIRXCOMPLETIONRAMERRCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[6] = (MIRXCOMPLETIONRAMERRCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[7] = (MIRXCOMPLETIONRAMERRCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[8] = (MIRXCOMPLETIONRAMERRCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[9] = (MIRXCOMPLETIONRAMERRCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[0] = (MIRXCOMPLETIONRAMERRUNCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[10] = (MIRXCOMPLETIONRAMERRUNCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[11] = (MIRXCOMPLETIONRAMERRUNCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[1] = (MIRXCOMPLETIONRAMERRUNCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[2] = (MIRXCOMPLETIONRAMERRUNCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[3] = (MIRXCOMPLETIONRAMERRUNCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[4] = (MIRXCOMPLETIONRAMERRUNCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[5] = (MIRXCOMPLETIONRAMERRUNCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[6] = (MIRXCOMPLETIONRAMERRUNCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[7] = (MIRXCOMPLETIONRAMERRUNCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[8] = (MIRXCOMPLETIONRAMERRUNCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[9] = (MIRXCOMPLETIONRAMERRUNCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[0] = (MIRXCOMPLETIONRAMREADDATA0[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[100] = (MIRXCOMPLETIONRAMREADDATA0[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[101] = (MIRXCOMPLETIONRAMREADDATA0[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[102] = (MIRXCOMPLETIONRAMREADDATA0[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[103] = (MIRXCOMPLETIONRAMREADDATA0[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[104] = (MIRXCOMPLETIONRAMREADDATA0[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[105] = (MIRXCOMPLETIONRAMREADDATA0[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[106] = (MIRXCOMPLETIONRAMREADDATA0[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[107] = (MIRXCOMPLETIONRAMREADDATA0[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[108] = (MIRXCOMPLETIONRAMREADDATA0[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[109] = (MIRXCOMPLETIONRAMREADDATA0[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[10] = (MIRXCOMPLETIONRAMREADDATA0[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[110] = (MIRXCOMPLETIONRAMREADDATA0[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[111] = (MIRXCOMPLETIONRAMREADDATA0[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[112] = (MIRXCOMPLETIONRAMREADDATA0[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[113] = (MIRXCOMPLETIONRAMREADDATA0[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[114] = (MIRXCOMPLETIONRAMREADDATA0[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[115] = (MIRXCOMPLETIONRAMREADDATA0[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[116] = (MIRXCOMPLETIONRAMREADDATA0[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[117] = (MIRXCOMPLETIONRAMREADDATA0[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[118] = (MIRXCOMPLETIONRAMREADDATA0[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[119] = (MIRXCOMPLETIONRAMREADDATA0[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[11] = (MIRXCOMPLETIONRAMREADDATA0[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[120] = (MIRXCOMPLETIONRAMREADDATA0[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[121] = (MIRXCOMPLETIONRAMREADDATA0[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[122] = (MIRXCOMPLETIONRAMREADDATA0[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[123] = (MIRXCOMPLETIONRAMREADDATA0[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[124] = (MIRXCOMPLETIONRAMREADDATA0[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[125] = (MIRXCOMPLETIONRAMREADDATA0[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[126] = (MIRXCOMPLETIONRAMREADDATA0[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[127] = (MIRXCOMPLETIONRAMREADDATA0[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[128] = (MIRXCOMPLETIONRAMREADDATA0[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[129] = (MIRXCOMPLETIONRAMREADDATA0[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[12] = (MIRXCOMPLETIONRAMREADDATA0[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[130] = (MIRXCOMPLETIONRAMREADDATA0[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[131] = (MIRXCOMPLETIONRAMREADDATA0[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[132] = (MIRXCOMPLETIONRAMREADDATA0[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[133] = (MIRXCOMPLETIONRAMREADDATA0[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[134] = (MIRXCOMPLETIONRAMREADDATA0[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[135] = (MIRXCOMPLETIONRAMREADDATA0[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[136] = (MIRXCOMPLETIONRAMREADDATA0[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[137] = (MIRXCOMPLETIONRAMREADDATA0[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[138] = (MIRXCOMPLETIONRAMREADDATA0[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[139] = (MIRXCOMPLETIONRAMREADDATA0[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[13] = (MIRXCOMPLETIONRAMREADDATA0[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[140] = (MIRXCOMPLETIONRAMREADDATA0[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[141] = (MIRXCOMPLETIONRAMREADDATA0[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[142] = (MIRXCOMPLETIONRAMREADDATA0[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[143] = (MIRXCOMPLETIONRAMREADDATA0[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[14] = (MIRXCOMPLETIONRAMREADDATA0[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[15] = (MIRXCOMPLETIONRAMREADDATA0[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[16] = (MIRXCOMPLETIONRAMREADDATA0[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[17] = (MIRXCOMPLETIONRAMREADDATA0[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[18] = (MIRXCOMPLETIONRAMREADDATA0[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[19] = (MIRXCOMPLETIONRAMREADDATA0[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[1] = (MIRXCOMPLETIONRAMREADDATA0[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[20] = (MIRXCOMPLETIONRAMREADDATA0[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[21] = (MIRXCOMPLETIONRAMREADDATA0[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[22] = (MIRXCOMPLETIONRAMREADDATA0[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[23] = (MIRXCOMPLETIONRAMREADDATA0[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[24] = (MIRXCOMPLETIONRAMREADDATA0[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[25] = (MIRXCOMPLETIONRAMREADDATA0[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[26] = (MIRXCOMPLETIONRAMREADDATA0[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[27] = (MIRXCOMPLETIONRAMREADDATA0[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[28] = (MIRXCOMPLETIONRAMREADDATA0[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[29] = (MIRXCOMPLETIONRAMREADDATA0[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[2] = (MIRXCOMPLETIONRAMREADDATA0[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[30] = (MIRXCOMPLETIONRAMREADDATA0[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[31] = (MIRXCOMPLETIONRAMREADDATA0[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[32] = (MIRXCOMPLETIONRAMREADDATA0[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[33] = (MIRXCOMPLETIONRAMREADDATA0[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[34] = (MIRXCOMPLETIONRAMREADDATA0[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[35] = (MIRXCOMPLETIONRAMREADDATA0[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[36] = (MIRXCOMPLETIONRAMREADDATA0[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[37] = (MIRXCOMPLETIONRAMREADDATA0[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[38] = (MIRXCOMPLETIONRAMREADDATA0[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[39] = (MIRXCOMPLETIONRAMREADDATA0[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[3] = (MIRXCOMPLETIONRAMREADDATA0[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[40] = (MIRXCOMPLETIONRAMREADDATA0[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[41] = (MIRXCOMPLETIONRAMREADDATA0[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[42] = (MIRXCOMPLETIONRAMREADDATA0[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[43] = (MIRXCOMPLETIONRAMREADDATA0[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[44] = (MIRXCOMPLETIONRAMREADDATA0[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[45] = (MIRXCOMPLETIONRAMREADDATA0[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[46] = (MIRXCOMPLETIONRAMREADDATA0[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[47] = (MIRXCOMPLETIONRAMREADDATA0[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[48] = (MIRXCOMPLETIONRAMREADDATA0[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[49] = (MIRXCOMPLETIONRAMREADDATA0[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[4] = (MIRXCOMPLETIONRAMREADDATA0[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[50] = (MIRXCOMPLETIONRAMREADDATA0[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[51] = (MIRXCOMPLETIONRAMREADDATA0[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[52] = (MIRXCOMPLETIONRAMREADDATA0[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[53] = (MIRXCOMPLETIONRAMREADDATA0[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[54] = (MIRXCOMPLETIONRAMREADDATA0[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[55] = (MIRXCOMPLETIONRAMREADDATA0[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[56] = (MIRXCOMPLETIONRAMREADDATA0[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[57] = (MIRXCOMPLETIONRAMREADDATA0[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[58] = (MIRXCOMPLETIONRAMREADDATA0[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[59] = (MIRXCOMPLETIONRAMREADDATA0[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[5] = (MIRXCOMPLETIONRAMREADDATA0[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[60] = (MIRXCOMPLETIONRAMREADDATA0[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[61] = (MIRXCOMPLETIONRAMREADDATA0[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[62] = (MIRXCOMPLETIONRAMREADDATA0[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[63] = (MIRXCOMPLETIONRAMREADDATA0[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[64] = (MIRXCOMPLETIONRAMREADDATA0[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[65] = (MIRXCOMPLETIONRAMREADDATA0[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[66] = (MIRXCOMPLETIONRAMREADDATA0[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[67] = (MIRXCOMPLETIONRAMREADDATA0[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[68] = (MIRXCOMPLETIONRAMREADDATA0[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[69] = (MIRXCOMPLETIONRAMREADDATA0[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[6] = (MIRXCOMPLETIONRAMREADDATA0[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[70] = (MIRXCOMPLETIONRAMREADDATA0[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[71] = (MIRXCOMPLETIONRAMREADDATA0[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[72] = (MIRXCOMPLETIONRAMREADDATA0[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[73] = (MIRXCOMPLETIONRAMREADDATA0[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[74] = (MIRXCOMPLETIONRAMREADDATA0[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[75] = (MIRXCOMPLETIONRAMREADDATA0[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[76] = (MIRXCOMPLETIONRAMREADDATA0[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[77] = (MIRXCOMPLETIONRAMREADDATA0[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[78] = (MIRXCOMPLETIONRAMREADDATA0[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[79] = (MIRXCOMPLETIONRAMREADDATA0[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[7] = (MIRXCOMPLETIONRAMREADDATA0[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[80] = (MIRXCOMPLETIONRAMREADDATA0[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[81] = (MIRXCOMPLETIONRAMREADDATA0[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[82] = (MIRXCOMPLETIONRAMREADDATA0[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[83] = (MIRXCOMPLETIONRAMREADDATA0[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[84] = (MIRXCOMPLETIONRAMREADDATA0[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[85] = (MIRXCOMPLETIONRAMREADDATA0[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[86] = (MIRXCOMPLETIONRAMREADDATA0[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[87] = (MIRXCOMPLETIONRAMREADDATA0[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[88] = (MIRXCOMPLETIONRAMREADDATA0[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[89] = (MIRXCOMPLETIONRAMREADDATA0[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[8] = (MIRXCOMPLETIONRAMREADDATA0[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[90] = (MIRXCOMPLETIONRAMREADDATA0[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[91] = (MIRXCOMPLETIONRAMREADDATA0[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[92] = (MIRXCOMPLETIONRAMREADDATA0[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[93] = (MIRXCOMPLETIONRAMREADDATA0[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[94] = (MIRXCOMPLETIONRAMREADDATA0[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[95] = (MIRXCOMPLETIONRAMREADDATA0[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[96] = (MIRXCOMPLETIONRAMREADDATA0[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[97] = (MIRXCOMPLETIONRAMREADDATA0[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[98] = (MIRXCOMPLETIONRAMREADDATA0[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[99] = (MIRXCOMPLETIONRAMREADDATA0[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[9] = (MIRXCOMPLETIONRAMREADDATA0[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0_delay[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[0] = (MIRXCOMPLETIONRAMREADDATA1[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[100] = (MIRXCOMPLETIONRAMREADDATA1[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[101] = (MIRXCOMPLETIONRAMREADDATA1[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[102] = (MIRXCOMPLETIONRAMREADDATA1[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[103] = (MIRXCOMPLETIONRAMREADDATA1[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[104] = (MIRXCOMPLETIONRAMREADDATA1[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[105] = (MIRXCOMPLETIONRAMREADDATA1[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[106] = (MIRXCOMPLETIONRAMREADDATA1[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[107] = (MIRXCOMPLETIONRAMREADDATA1[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[108] = (MIRXCOMPLETIONRAMREADDATA1[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[109] = (MIRXCOMPLETIONRAMREADDATA1[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[10] = (MIRXCOMPLETIONRAMREADDATA1[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[110] = (MIRXCOMPLETIONRAMREADDATA1[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[111] = (MIRXCOMPLETIONRAMREADDATA1[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[112] = (MIRXCOMPLETIONRAMREADDATA1[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[113] = (MIRXCOMPLETIONRAMREADDATA1[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[114] = (MIRXCOMPLETIONRAMREADDATA1[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[115] = (MIRXCOMPLETIONRAMREADDATA1[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[116] = (MIRXCOMPLETIONRAMREADDATA1[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[117] = (MIRXCOMPLETIONRAMREADDATA1[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[118] = (MIRXCOMPLETIONRAMREADDATA1[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[119] = (MIRXCOMPLETIONRAMREADDATA1[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[11] = (MIRXCOMPLETIONRAMREADDATA1[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[120] = (MIRXCOMPLETIONRAMREADDATA1[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[121] = (MIRXCOMPLETIONRAMREADDATA1[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[122] = (MIRXCOMPLETIONRAMREADDATA1[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[123] = (MIRXCOMPLETIONRAMREADDATA1[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[124] = (MIRXCOMPLETIONRAMREADDATA1[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[125] = (MIRXCOMPLETIONRAMREADDATA1[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[126] = (MIRXCOMPLETIONRAMREADDATA1[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[127] = (MIRXCOMPLETIONRAMREADDATA1[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[128] = (MIRXCOMPLETIONRAMREADDATA1[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[129] = (MIRXCOMPLETIONRAMREADDATA1[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[12] = (MIRXCOMPLETIONRAMREADDATA1[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[130] = (MIRXCOMPLETIONRAMREADDATA1[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[131] = (MIRXCOMPLETIONRAMREADDATA1[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[132] = (MIRXCOMPLETIONRAMREADDATA1[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[133] = (MIRXCOMPLETIONRAMREADDATA1[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[134] = (MIRXCOMPLETIONRAMREADDATA1[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[135] = (MIRXCOMPLETIONRAMREADDATA1[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[136] = (MIRXCOMPLETIONRAMREADDATA1[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[137] = (MIRXCOMPLETIONRAMREADDATA1[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[138] = (MIRXCOMPLETIONRAMREADDATA1[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[139] = (MIRXCOMPLETIONRAMREADDATA1[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[13] = (MIRXCOMPLETIONRAMREADDATA1[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[140] = (MIRXCOMPLETIONRAMREADDATA1[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[141] = (MIRXCOMPLETIONRAMREADDATA1[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[142] = (MIRXCOMPLETIONRAMREADDATA1[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[143] = (MIRXCOMPLETIONRAMREADDATA1[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[14] = (MIRXCOMPLETIONRAMREADDATA1[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[15] = (MIRXCOMPLETIONRAMREADDATA1[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[16] = (MIRXCOMPLETIONRAMREADDATA1[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[17] = (MIRXCOMPLETIONRAMREADDATA1[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[18] = (MIRXCOMPLETIONRAMREADDATA1[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[19] = (MIRXCOMPLETIONRAMREADDATA1[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[1] = (MIRXCOMPLETIONRAMREADDATA1[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[20] = (MIRXCOMPLETIONRAMREADDATA1[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[21] = (MIRXCOMPLETIONRAMREADDATA1[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[22] = (MIRXCOMPLETIONRAMREADDATA1[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[23] = (MIRXCOMPLETIONRAMREADDATA1[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[24] = (MIRXCOMPLETIONRAMREADDATA1[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[25] = (MIRXCOMPLETIONRAMREADDATA1[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[26] = (MIRXCOMPLETIONRAMREADDATA1[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[27] = (MIRXCOMPLETIONRAMREADDATA1[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[28] = (MIRXCOMPLETIONRAMREADDATA1[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[29] = (MIRXCOMPLETIONRAMREADDATA1[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[2] = (MIRXCOMPLETIONRAMREADDATA1[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[30] = (MIRXCOMPLETIONRAMREADDATA1[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[31] = (MIRXCOMPLETIONRAMREADDATA1[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[32] = (MIRXCOMPLETIONRAMREADDATA1[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[33] = (MIRXCOMPLETIONRAMREADDATA1[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[34] = (MIRXCOMPLETIONRAMREADDATA1[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[35] = (MIRXCOMPLETIONRAMREADDATA1[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[36] = (MIRXCOMPLETIONRAMREADDATA1[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[37] = (MIRXCOMPLETIONRAMREADDATA1[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[38] = (MIRXCOMPLETIONRAMREADDATA1[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[39] = (MIRXCOMPLETIONRAMREADDATA1[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[3] = (MIRXCOMPLETIONRAMREADDATA1[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[40] = (MIRXCOMPLETIONRAMREADDATA1[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[41] = (MIRXCOMPLETIONRAMREADDATA1[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[42] = (MIRXCOMPLETIONRAMREADDATA1[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[43] = (MIRXCOMPLETIONRAMREADDATA1[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[44] = (MIRXCOMPLETIONRAMREADDATA1[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[45] = (MIRXCOMPLETIONRAMREADDATA1[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[46] = (MIRXCOMPLETIONRAMREADDATA1[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[47] = (MIRXCOMPLETIONRAMREADDATA1[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[48] = (MIRXCOMPLETIONRAMREADDATA1[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[49] = (MIRXCOMPLETIONRAMREADDATA1[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[4] = (MIRXCOMPLETIONRAMREADDATA1[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[50] = (MIRXCOMPLETIONRAMREADDATA1[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[51] = (MIRXCOMPLETIONRAMREADDATA1[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[52] = (MIRXCOMPLETIONRAMREADDATA1[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[53] = (MIRXCOMPLETIONRAMREADDATA1[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[54] = (MIRXCOMPLETIONRAMREADDATA1[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[55] = (MIRXCOMPLETIONRAMREADDATA1[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[56] = (MIRXCOMPLETIONRAMREADDATA1[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[57] = (MIRXCOMPLETIONRAMREADDATA1[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[58] = (MIRXCOMPLETIONRAMREADDATA1[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[59] = (MIRXCOMPLETIONRAMREADDATA1[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[5] = (MIRXCOMPLETIONRAMREADDATA1[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[60] = (MIRXCOMPLETIONRAMREADDATA1[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[61] = (MIRXCOMPLETIONRAMREADDATA1[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[62] = (MIRXCOMPLETIONRAMREADDATA1[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[63] = (MIRXCOMPLETIONRAMREADDATA1[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[64] = (MIRXCOMPLETIONRAMREADDATA1[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[65] = (MIRXCOMPLETIONRAMREADDATA1[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[66] = (MIRXCOMPLETIONRAMREADDATA1[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[67] = (MIRXCOMPLETIONRAMREADDATA1[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[68] = (MIRXCOMPLETIONRAMREADDATA1[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[69] = (MIRXCOMPLETIONRAMREADDATA1[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[6] = (MIRXCOMPLETIONRAMREADDATA1[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[70] = (MIRXCOMPLETIONRAMREADDATA1[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[71] = (MIRXCOMPLETIONRAMREADDATA1[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[72] = (MIRXCOMPLETIONRAMREADDATA1[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[73] = (MIRXCOMPLETIONRAMREADDATA1[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[74] = (MIRXCOMPLETIONRAMREADDATA1[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[75] = (MIRXCOMPLETIONRAMREADDATA1[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[76] = (MIRXCOMPLETIONRAMREADDATA1[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[77] = (MIRXCOMPLETIONRAMREADDATA1[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[78] = (MIRXCOMPLETIONRAMREADDATA1[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[79] = (MIRXCOMPLETIONRAMREADDATA1[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[7] = (MIRXCOMPLETIONRAMREADDATA1[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[80] = (MIRXCOMPLETIONRAMREADDATA1[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[81] = (MIRXCOMPLETIONRAMREADDATA1[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[82] = (MIRXCOMPLETIONRAMREADDATA1[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[83] = (MIRXCOMPLETIONRAMREADDATA1[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[84] = (MIRXCOMPLETIONRAMREADDATA1[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[85] = (MIRXCOMPLETIONRAMREADDATA1[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[86] = (MIRXCOMPLETIONRAMREADDATA1[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[87] = (MIRXCOMPLETIONRAMREADDATA1[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[88] = (MIRXCOMPLETIONRAMREADDATA1[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[89] = (MIRXCOMPLETIONRAMREADDATA1[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[8] = (MIRXCOMPLETIONRAMREADDATA1[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[90] = (MIRXCOMPLETIONRAMREADDATA1[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[91] = (MIRXCOMPLETIONRAMREADDATA1[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[92] = (MIRXCOMPLETIONRAMREADDATA1[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[93] = (MIRXCOMPLETIONRAMREADDATA1[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[94] = (MIRXCOMPLETIONRAMREADDATA1[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[95] = (MIRXCOMPLETIONRAMREADDATA1[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[96] = (MIRXCOMPLETIONRAMREADDATA1[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[97] = (MIRXCOMPLETIONRAMREADDATA1[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[98] = (MIRXCOMPLETIONRAMREADDATA1[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[99] = (MIRXCOMPLETIONRAMREADDATA1[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[9] = (MIRXCOMPLETIONRAMREADDATA1[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1_delay[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRUNCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRUNCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRUNCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRUNCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRUNCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRUNCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA0[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA0[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA0[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA0[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA0[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA0[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA0[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA0[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA0[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA0[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA0[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA0[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA0[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA0[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA0[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA0[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA0[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA0[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA0[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA0[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA0[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA0[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA0[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA0[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA0[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA0[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA0[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA0[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA0[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA0[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA0[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA0[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA0[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA0[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA0[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA0[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA0[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA0[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA0[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA0[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA0[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA0[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA0[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA0[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA0[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA0[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA0[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA0[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA0[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA0[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA0[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA0[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA0[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA0[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA0[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA0[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA0[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA0[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA0[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA0[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA0[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA0[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA0[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA0[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA0[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA0[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA0[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA0[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA0[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA0[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA0[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA0[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA0[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA0[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA0[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA0[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA0[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA0[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA0[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA0[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA0[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA0[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA0[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA0[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA0[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA0[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA0[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA0[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA0[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA0[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA0[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA0[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA0[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA0[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA0[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA0[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA0[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA0[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA0[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA0[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA0[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA0[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA0[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA0[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA0[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA0[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA0[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA0[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA0[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA0[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA0[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA0[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA0[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA0[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA0[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA0[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA0[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA0[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA0[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA0[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA0[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA0[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA0[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA0[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA0[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA0[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA0[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA0[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA0[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA0[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA0[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA0[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA0[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA0[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA0[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA0[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA0[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA0[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA0[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA0[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA0[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA0[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA0[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA0[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA1[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA1[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA1[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA1[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA1[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA1[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA1[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA1[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA1[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA1[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA1[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA1[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA1[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA1[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA1[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA1[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA1[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA1[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA1[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA1[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA1[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA1[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA1[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA1[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA1[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA1[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA1[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA1[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA1[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA1[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA1[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA1[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA1[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA1[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA1[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA1[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA1[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA1[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA1[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA1[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA1[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA1[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA1[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA1[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA1[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA1[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA1[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA1[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA1[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA1[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA1[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA1[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA1[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA1[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA1[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA1[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA1[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA1[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA1[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA1[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA1[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA1[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA1[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA1[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA1[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA1[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA1[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA1[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA1[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA1[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA1[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA1[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA1[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA1[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA1[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA1[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA1[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA1[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA1[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA1[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA1[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA1[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA1[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA1[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA1[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA1[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA1[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA1[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA1[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA1[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA1[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA1[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA1[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA1[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA1[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA1[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA1[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA1[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA1[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA1[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA1[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA1[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA1[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA1[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA1[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA1[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA1[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA1[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA1[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA1[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA1[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA1[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA1[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA1[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA1[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA1[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA1[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA1[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA1[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA1[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA1[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA1[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA1[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA1[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA1[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA1[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA1[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA1[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA1[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA1[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA1[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA1[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA1[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA1[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA1[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA1[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA1[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA1[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA1[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA1[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA1[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA1[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA1[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA1[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[0] = (PCIECOMPLDELIVEREDTAG0[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[1] = (PCIECOMPLDELIVEREDTAG0[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[2] = (PCIECOMPLDELIVEREDTAG0[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[3] = (PCIECOMPLDELIVEREDTAG0[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[4] = (PCIECOMPLDELIVEREDTAG0[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[5] = (PCIECOMPLDELIVEREDTAG0[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[6] = (PCIECOMPLDELIVEREDTAG0[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[7] = (PCIECOMPLDELIVEREDTAG0[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG0_delay[7]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[0] = (PCIECOMPLDELIVEREDTAG1[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[1] = (PCIECOMPLDELIVEREDTAG1[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[2] = (PCIECOMPLDELIVEREDTAG1[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[3] = (PCIECOMPLDELIVEREDTAG1[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[4] = (PCIECOMPLDELIVEREDTAG1[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[5] = (PCIECOMPLDELIVEREDTAG1[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[6] = (PCIECOMPLDELIVEREDTAG1[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[7] = (PCIECOMPLDELIVEREDTAG1[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG1_delay[7]; // rv 0 + assign PCIECOMPLDELIVERED_in[0] = (PCIECOMPLDELIVERED[0] !== 1'bz) && PCIECOMPLDELIVERED_delay[0]; // rv 0 + assign PCIECOMPLDELIVERED_in[1] = (PCIECOMPLDELIVERED[1] !== 1'bz) && PCIECOMPLDELIVERED_delay[1]; // rv 0 + assign PCIECQNPREQ_in[0] = (PCIECQNPREQ[0] === 1'bz) || PCIECQNPREQ_delay[0]; // rv 1 + assign PCIECQNPREQ_in[1] = (PCIECQNPREQ[1] === 1'bz) || PCIECQNPREQ_delay[1]; // rv 1 + assign PCIECQNPUSERCREDITRCVD_in = (PCIECQNPUSERCREDITRCVD !== 1'bz) && PCIECQNPUSERCREDITRCVD_delay; // rv 0 + assign PCIECQPIPELINEEMPTY_in = (PCIECQPIPELINEEMPTY !== 1'bz) && PCIECQPIPELINEEMPTY_delay; // rv 0 + assign PCIEPOSTEDREQDELIVERED_in = (PCIEPOSTEDREQDELIVERED !== 1'bz) && PCIEPOSTEDREQDELIVERED_delay; // rv 0 + assign PIPECLK_in = (PIPECLK !== 1'bz) && PIPECLK_delay; // rv 0 + assign PIPEEQFS_in[0] = (PIPEEQFS[0] !== 1'bz) && PIPEEQFS_delay[0]; // rv 0 + assign PIPEEQFS_in[1] = (PIPEEQFS[1] !== 1'bz) && PIPEEQFS_delay[1]; // rv 0 + assign PIPEEQFS_in[2] = (PIPEEQFS[2] !== 1'bz) && PIPEEQFS_delay[2]; // rv 0 + assign PIPEEQFS_in[3] = (PIPEEQFS[3] !== 1'bz) && PIPEEQFS_delay[3]; // rv 0 + assign PIPEEQFS_in[4] = (PIPEEQFS[4] !== 1'bz) && PIPEEQFS_delay[4]; // rv 0 + assign PIPEEQFS_in[5] = (PIPEEQFS[5] !== 1'bz) && PIPEEQFS_delay[5]; // rv 0 + assign PIPEEQLF_in[0] = (PIPEEQLF[0] !== 1'bz) && PIPEEQLF_delay[0]; // rv 0 + assign PIPEEQLF_in[1] = (PIPEEQLF[1] !== 1'bz) && PIPEEQLF_delay[1]; // rv 0 + assign PIPEEQLF_in[2] = (PIPEEQLF[2] !== 1'bz) && PIPEEQLF_delay[2]; // rv 0 + assign PIPEEQLF_in[3] = (PIPEEQLF[3] !== 1'bz) && PIPEEQLF_delay[3]; // rv 0 + assign PIPEEQLF_in[4] = (PIPEEQLF[4] !== 1'bz) && PIPEEQLF_delay[4]; // rv 0 + assign PIPEEQLF_in[5] = (PIPEEQLF[5] !== 1'bz) && PIPEEQLF_delay[5]; // rv 0 + assign PIPERX00CHARISK_in[0] = (PIPERX00CHARISK[0] === 1'bz) || PIPERX00CHARISK_delay[0]; // rv 1 + assign PIPERX00CHARISK_in[1] = (PIPERX00CHARISK[1] === 1'bz) || PIPERX00CHARISK_delay[1]; // rv 1 + assign PIPERX00DATAVALID_in = (PIPERX00DATAVALID !== 1'bz) && PIPERX00DATAVALID_delay; // rv 0 + assign PIPERX00DATA_in[0] = (PIPERX00DATA[0] !== 1'bz) && PIPERX00DATA_delay[0]; // rv 0 + assign PIPERX00DATA_in[10] = (PIPERX00DATA[10] !== 1'bz) && PIPERX00DATA_delay[10]; // rv 0 + assign PIPERX00DATA_in[11] = (PIPERX00DATA[11] !== 1'bz) && PIPERX00DATA_delay[11]; // rv 0 + assign PIPERX00DATA_in[12] = (PIPERX00DATA[12] !== 1'bz) && PIPERX00DATA_delay[12]; // rv 0 + assign PIPERX00DATA_in[13] = (PIPERX00DATA[13] !== 1'bz) && PIPERX00DATA_delay[13]; // rv 0 + assign PIPERX00DATA_in[14] = (PIPERX00DATA[14] !== 1'bz) && PIPERX00DATA_delay[14]; // rv 0 + assign PIPERX00DATA_in[15] = (PIPERX00DATA[15] !== 1'bz) && PIPERX00DATA_delay[15]; // rv 0 + assign PIPERX00DATA_in[16] = (PIPERX00DATA[16] !== 1'bz) && PIPERX00DATA_delay[16]; // rv 0 + assign PIPERX00DATA_in[17] = (PIPERX00DATA[17] !== 1'bz) && PIPERX00DATA_delay[17]; // rv 0 + assign PIPERX00DATA_in[18] = (PIPERX00DATA[18] !== 1'bz) && PIPERX00DATA_delay[18]; // rv 0 + assign PIPERX00DATA_in[19] = (PIPERX00DATA[19] !== 1'bz) && PIPERX00DATA_delay[19]; // rv 0 + assign PIPERX00DATA_in[1] = (PIPERX00DATA[1] !== 1'bz) && PIPERX00DATA_delay[1]; // rv 0 + assign PIPERX00DATA_in[20] = (PIPERX00DATA[20] !== 1'bz) && PIPERX00DATA_delay[20]; // rv 0 + assign PIPERX00DATA_in[21] = (PIPERX00DATA[21] !== 1'bz) && PIPERX00DATA_delay[21]; // rv 0 + assign PIPERX00DATA_in[22] = (PIPERX00DATA[22] !== 1'bz) && PIPERX00DATA_delay[22]; // rv 0 + assign PIPERX00DATA_in[23] = (PIPERX00DATA[23] !== 1'bz) && PIPERX00DATA_delay[23]; // rv 0 + assign PIPERX00DATA_in[24] = (PIPERX00DATA[24] !== 1'bz) && PIPERX00DATA_delay[24]; // rv 0 + assign PIPERX00DATA_in[25] = (PIPERX00DATA[25] !== 1'bz) && PIPERX00DATA_delay[25]; // rv 0 + assign PIPERX00DATA_in[26] = (PIPERX00DATA[26] !== 1'bz) && PIPERX00DATA_delay[26]; // rv 0 + assign PIPERX00DATA_in[27] = (PIPERX00DATA[27] !== 1'bz) && PIPERX00DATA_delay[27]; // rv 0 + assign PIPERX00DATA_in[28] = (PIPERX00DATA[28] !== 1'bz) && PIPERX00DATA_delay[28]; // rv 0 + assign PIPERX00DATA_in[29] = (PIPERX00DATA[29] !== 1'bz) && PIPERX00DATA_delay[29]; // rv 0 + assign PIPERX00DATA_in[2] = (PIPERX00DATA[2] !== 1'bz) && PIPERX00DATA_delay[2]; // rv 0 + assign PIPERX00DATA_in[30] = (PIPERX00DATA[30] !== 1'bz) && PIPERX00DATA_delay[30]; // rv 0 + assign PIPERX00DATA_in[31] = (PIPERX00DATA[31] !== 1'bz) && PIPERX00DATA_delay[31]; // rv 0 + assign PIPERX00DATA_in[3] = (PIPERX00DATA[3] !== 1'bz) && PIPERX00DATA_delay[3]; // rv 0 + assign PIPERX00DATA_in[4] = (PIPERX00DATA[4] !== 1'bz) && PIPERX00DATA_delay[4]; // rv 0 + assign PIPERX00DATA_in[5] = (PIPERX00DATA[5] !== 1'bz) && PIPERX00DATA_delay[5]; // rv 0 + assign PIPERX00DATA_in[6] = (PIPERX00DATA[6] !== 1'bz) && PIPERX00DATA_delay[6]; // rv 0 + assign PIPERX00DATA_in[7] = (PIPERX00DATA[7] !== 1'bz) && PIPERX00DATA_delay[7]; // rv 0 + assign PIPERX00DATA_in[8] = (PIPERX00DATA[8] !== 1'bz) && PIPERX00DATA_delay[8]; // rv 0 + assign PIPERX00DATA_in[9] = (PIPERX00DATA[9] !== 1'bz) && PIPERX00DATA_delay[9]; // rv 0 + assign PIPERX00ELECIDLE_in = (PIPERX00ELECIDLE === 1'bz) || PIPERX00ELECIDLE_delay; // rv 1 + assign PIPERX00EQDONE_in = (PIPERX00EQDONE !== 1'bz) && PIPERX00EQDONE_delay; // rv 0 + assign PIPERX00EQLPADAPTDONE_in = (PIPERX00EQLPADAPTDONE !== 1'bz) && PIPERX00EQLPADAPTDONE_delay; // rv 0 + assign PIPERX00EQLPLFFSSEL_in = (PIPERX00EQLPLFFSSEL !== 1'bz) && PIPERX00EQLPLFFSSEL_delay; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX00EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX00EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX00EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX00EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX00EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX00EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX00EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX00EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX00EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX00EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX00EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX00EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX00EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX00EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX00EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX00EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX00EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX00EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX00PHYSTATUS_in = (PIPERX00PHYSTATUS === 1'bz) || PIPERX00PHYSTATUS_delay; // rv 1 + assign PIPERX00STARTBLOCK_in[0] = (PIPERX00STARTBLOCK[0] !== 1'bz) && PIPERX00STARTBLOCK_delay[0]; // rv 0 + assign PIPERX00STARTBLOCK_in[1] = (PIPERX00STARTBLOCK[1] !== 1'bz) && PIPERX00STARTBLOCK_delay[1]; // rv 0 + assign PIPERX00STATUS_in[0] = (PIPERX00STATUS[0] !== 1'bz) && PIPERX00STATUS_delay[0]; // rv 0 + assign PIPERX00STATUS_in[1] = (PIPERX00STATUS[1] !== 1'bz) && PIPERX00STATUS_delay[1]; // rv 0 + assign PIPERX00STATUS_in[2] = (PIPERX00STATUS[2] !== 1'bz) && PIPERX00STATUS_delay[2]; // rv 0 + assign PIPERX00SYNCHEADER_in[0] = (PIPERX00SYNCHEADER[0] !== 1'bz) && PIPERX00SYNCHEADER_delay[0]; // rv 0 + assign PIPERX00SYNCHEADER_in[1] = (PIPERX00SYNCHEADER[1] !== 1'bz) && PIPERX00SYNCHEADER_delay[1]; // rv 0 + assign PIPERX00VALID_in = (PIPERX00VALID !== 1'bz) && PIPERX00VALID_delay; // rv 0 + assign PIPERX01CHARISK_in[0] = (PIPERX01CHARISK[0] === 1'bz) || PIPERX01CHARISK_delay[0]; // rv 1 + assign PIPERX01CHARISK_in[1] = (PIPERX01CHARISK[1] === 1'bz) || PIPERX01CHARISK_delay[1]; // rv 1 + assign PIPERX01DATAVALID_in = (PIPERX01DATAVALID !== 1'bz) && PIPERX01DATAVALID_delay; // rv 0 + assign PIPERX01DATA_in[0] = (PIPERX01DATA[0] !== 1'bz) && PIPERX01DATA_delay[0]; // rv 0 + assign PIPERX01DATA_in[10] = (PIPERX01DATA[10] !== 1'bz) && PIPERX01DATA_delay[10]; // rv 0 + assign PIPERX01DATA_in[11] = (PIPERX01DATA[11] !== 1'bz) && PIPERX01DATA_delay[11]; // rv 0 + assign PIPERX01DATA_in[12] = (PIPERX01DATA[12] !== 1'bz) && PIPERX01DATA_delay[12]; // rv 0 + assign PIPERX01DATA_in[13] = (PIPERX01DATA[13] !== 1'bz) && PIPERX01DATA_delay[13]; // rv 0 + assign PIPERX01DATA_in[14] = (PIPERX01DATA[14] !== 1'bz) && PIPERX01DATA_delay[14]; // rv 0 + assign PIPERX01DATA_in[15] = (PIPERX01DATA[15] !== 1'bz) && PIPERX01DATA_delay[15]; // rv 0 + assign PIPERX01DATA_in[16] = (PIPERX01DATA[16] !== 1'bz) && PIPERX01DATA_delay[16]; // rv 0 + assign PIPERX01DATA_in[17] = (PIPERX01DATA[17] !== 1'bz) && PIPERX01DATA_delay[17]; // rv 0 + assign PIPERX01DATA_in[18] = (PIPERX01DATA[18] !== 1'bz) && PIPERX01DATA_delay[18]; // rv 0 + assign PIPERX01DATA_in[19] = (PIPERX01DATA[19] !== 1'bz) && PIPERX01DATA_delay[19]; // rv 0 + assign PIPERX01DATA_in[1] = (PIPERX01DATA[1] !== 1'bz) && PIPERX01DATA_delay[1]; // rv 0 + assign PIPERX01DATA_in[20] = (PIPERX01DATA[20] !== 1'bz) && PIPERX01DATA_delay[20]; // rv 0 + assign PIPERX01DATA_in[21] = (PIPERX01DATA[21] !== 1'bz) && PIPERX01DATA_delay[21]; // rv 0 + assign PIPERX01DATA_in[22] = (PIPERX01DATA[22] !== 1'bz) && PIPERX01DATA_delay[22]; // rv 0 + assign PIPERX01DATA_in[23] = (PIPERX01DATA[23] !== 1'bz) && PIPERX01DATA_delay[23]; // rv 0 + assign PIPERX01DATA_in[24] = (PIPERX01DATA[24] !== 1'bz) && PIPERX01DATA_delay[24]; // rv 0 + assign PIPERX01DATA_in[25] = (PIPERX01DATA[25] !== 1'bz) && PIPERX01DATA_delay[25]; // rv 0 + assign PIPERX01DATA_in[26] = (PIPERX01DATA[26] !== 1'bz) && PIPERX01DATA_delay[26]; // rv 0 + assign PIPERX01DATA_in[27] = (PIPERX01DATA[27] !== 1'bz) && PIPERX01DATA_delay[27]; // rv 0 + assign PIPERX01DATA_in[28] = (PIPERX01DATA[28] !== 1'bz) && PIPERX01DATA_delay[28]; // rv 0 + assign PIPERX01DATA_in[29] = (PIPERX01DATA[29] !== 1'bz) && PIPERX01DATA_delay[29]; // rv 0 + assign PIPERX01DATA_in[2] = (PIPERX01DATA[2] !== 1'bz) && PIPERX01DATA_delay[2]; // rv 0 + assign PIPERX01DATA_in[30] = (PIPERX01DATA[30] !== 1'bz) && PIPERX01DATA_delay[30]; // rv 0 + assign PIPERX01DATA_in[31] = (PIPERX01DATA[31] !== 1'bz) && PIPERX01DATA_delay[31]; // rv 0 + assign PIPERX01DATA_in[3] = (PIPERX01DATA[3] !== 1'bz) && PIPERX01DATA_delay[3]; // rv 0 + assign PIPERX01DATA_in[4] = (PIPERX01DATA[4] !== 1'bz) && PIPERX01DATA_delay[4]; // rv 0 + assign PIPERX01DATA_in[5] = (PIPERX01DATA[5] !== 1'bz) && PIPERX01DATA_delay[5]; // rv 0 + assign PIPERX01DATA_in[6] = (PIPERX01DATA[6] !== 1'bz) && PIPERX01DATA_delay[6]; // rv 0 + assign PIPERX01DATA_in[7] = (PIPERX01DATA[7] !== 1'bz) && PIPERX01DATA_delay[7]; // rv 0 + assign PIPERX01DATA_in[8] = (PIPERX01DATA[8] !== 1'bz) && PIPERX01DATA_delay[8]; // rv 0 + assign PIPERX01DATA_in[9] = (PIPERX01DATA[9] !== 1'bz) && PIPERX01DATA_delay[9]; // rv 0 + assign PIPERX01ELECIDLE_in = (PIPERX01ELECIDLE === 1'bz) || PIPERX01ELECIDLE_delay; // rv 1 + assign PIPERX01EQDONE_in = (PIPERX01EQDONE !== 1'bz) && PIPERX01EQDONE_delay; // rv 0 + assign PIPERX01EQLPADAPTDONE_in = (PIPERX01EQLPADAPTDONE !== 1'bz) && PIPERX01EQLPADAPTDONE_delay; // rv 0 + assign PIPERX01EQLPLFFSSEL_in = (PIPERX01EQLPLFFSSEL !== 1'bz) && PIPERX01EQLPLFFSSEL_delay; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX01EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX01EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX01EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX01EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX01EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX01EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX01EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX01EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX01EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX01EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX01EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX01EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX01EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX01EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX01EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX01EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX01EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX01EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX01PHYSTATUS_in = (PIPERX01PHYSTATUS === 1'bz) || PIPERX01PHYSTATUS_delay; // rv 1 + assign PIPERX01STARTBLOCK_in[0] = (PIPERX01STARTBLOCK[0] !== 1'bz) && PIPERX01STARTBLOCK_delay[0]; // rv 0 + assign PIPERX01STARTBLOCK_in[1] = (PIPERX01STARTBLOCK[1] !== 1'bz) && PIPERX01STARTBLOCK_delay[1]; // rv 0 + assign PIPERX01STATUS_in[0] = (PIPERX01STATUS[0] !== 1'bz) && PIPERX01STATUS_delay[0]; // rv 0 + assign PIPERX01STATUS_in[1] = (PIPERX01STATUS[1] !== 1'bz) && PIPERX01STATUS_delay[1]; // rv 0 + assign PIPERX01STATUS_in[2] = (PIPERX01STATUS[2] !== 1'bz) && PIPERX01STATUS_delay[2]; // rv 0 + assign PIPERX01SYNCHEADER_in[0] = (PIPERX01SYNCHEADER[0] !== 1'bz) && PIPERX01SYNCHEADER_delay[0]; // rv 0 + assign PIPERX01SYNCHEADER_in[1] = (PIPERX01SYNCHEADER[1] !== 1'bz) && PIPERX01SYNCHEADER_delay[1]; // rv 0 + assign PIPERX01VALID_in = (PIPERX01VALID !== 1'bz) && PIPERX01VALID_delay; // rv 0 + assign PIPERX02CHARISK_in[0] = (PIPERX02CHARISK[0] === 1'bz) || PIPERX02CHARISK_delay[0]; // rv 1 + assign PIPERX02CHARISK_in[1] = (PIPERX02CHARISK[1] === 1'bz) || PIPERX02CHARISK_delay[1]; // rv 1 + assign PIPERX02DATAVALID_in = (PIPERX02DATAVALID !== 1'bz) && PIPERX02DATAVALID_delay; // rv 0 + assign PIPERX02DATA_in[0] = (PIPERX02DATA[0] !== 1'bz) && PIPERX02DATA_delay[0]; // rv 0 + assign PIPERX02DATA_in[10] = (PIPERX02DATA[10] !== 1'bz) && PIPERX02DATA_delay[10]; // rv 0 + assign PIPERX02DATA_in[11] = (PIPERX02DATA[11] !== 1'bz) && PIPERX02DATA_delay[11]; // rv 0 + assign PIPERX02DATA_in[12] = (PIPERX02DATA[12] !== 1'bz) && PIPERX02DATA_delay[12]; // rv 0 + assign PIPERX02DATA_in[13] = (PIPERX02DATA[13] !== 1'bz) && PIPERX02DATA_delay[13]; // rv 0 + assign PIPERX02DATA_in[14] = (PIPERX02DATA[14] !== 1'bz) && PIPERX02DATA_delay[14]; // rv 0 + assign PIPERX02DATA_in[15] = (PIPERX02DATA[15] !== 1'bz) && PIPERX02DATA_delay[15]; // rv 0 + assign PIPERX02DATA_in[16] = (PIPERX02DATA[16] !== 1'bz) && PIPERX02DATA_delay[16]; // rv 0 + assign PIPERX02DATA_in[17] = (PIPERX02DATA[17] !== 1'bz) && PIPERX02DATA_delay[17]; // rv 0 + assign PIPERX02DATA_in[18] = (PIPERX02DATA[18] !== 1'bz) && PIPERX02DATA_delay[18]; // rv 0 + assign PIPERX02DATA_in[19] = (PIPERX02DATA[19] !== 1'bz) && PIPERX02DATA_delay[19]; // rv 0 + assign PIPERX02DATA_in[1] = (PIPERX02DATA[1] !== 1'bz) && PIPERX02DATA_delay[1]; // rv 0 + assign PIPERX02DATA_in[20] = (PIPERX02DATA[20] !== 1'bz) && PIPERX02DATA_delay[20]; // rv 0 + assign PIPERX02DATA_in[21] = (PIPERX02DATA[21] !== 1'bz) && PIPERX02DATA_delay[21]; // rv 0 + assign PIPERX02DATA_in[22] = (PIPERX02DATA[22] !== 1'bz) && PIPERX02DATA_delay[22]; // rv 0 + assign PIPERX02DATA_in[23] = (PIPERX02DATA[23] !== 1'bz) && PIPERX02DATA_delay[23]; // rv 0 + assign PIPERX02DATA_in[24] = (PIPERX02DATA[24] !== 1'bz) && PIPERX02DATA_delay[24]; // rv 0 + assign PIPERX02DATA_in[25] = (PIPERX02DATA[25] !== 1'bz) && PIPERX02DATA_delay[25]; // rv 0 + assign PIPERX02DATA_in[26] = (PIPERX02DATA[26] !== 1'bz) && PIPERX02DATA_delay[26]; // rv 0 + assign PIPERX02DATA_in[27] = (PIPERX02DATA[27] !== 1'bz) && PIPERX02DATA_delay[27]; // rv 0 + assign PIPERX02DATA_in[28] = (PIPERX02DATA[28] !== 1'bz) && PIPERX02DATA_delay[28]; // rv 0 + assign PIPERX02DATA_in[29] = (PIPERX02DATA[29] !== 1'bz) && PIPERX02DATA_delay[29]; // rv 0 + assign PIPERX02DATA_in[2] = (PIPERX02DATA[2] !== 1'bz) && PIPERX02DATA_delay[2]; // rv 0 + assign PIPERX02DATA_in[30] = (PIPERX02DATA[30] !== 1'bz) && PIPERX02DATA_delay[30]; // rv 0 + assign PIPERX02DATA_in[31] = (PIPERX02DATA[31] !== 1'bz) && PIPERX02DATA_delay[31]; // rv 0 + assign PIPERX02DATA_in[3] = (PIPERX02DATA[3] !== 1'bz) && PIPERX02DATA_delay[3]; // rv 0 + assign PIPERX02DATA_in[4] = (PIPERX02DATA[4] !== 1'bz) && PIPERX02DATA_delay[4]; // rv 0 + assign PIPERX02DATA_in[5] = (PIPERX02DATA[5] !== 1'bz) && PIPERX02DATA_delay[5]; // rv 0 + assign PIPERX02DATA_in[6] = (PIPERX02DATA[6] !== 1'bz) && PIPERX02DATA_delay[6]; // rv 0 + assign PIPERX02DATA_in[7] = (PIPERX02DATA[7] !== 1'bz) && PIPERX02DATA_delay[7]; // rv 0 + assign PIPERX02DATA_in[8] = (PIPERX02DATA[8] !== 1'bz) && PIPERX02DATA_delay[8]; // rv 0 + assign PIPERX02DATA_in[9] = (PIPERX02DATA[9] !== 1'bz) && PIPERX02DATA_delay[9]; // rv 0 + assign PIPERX02ELECIDLE_in = (PIPERX02ELECIDLE === 1'bz) || PIPERX02ELECIDLE_delay; // rv 1 + assign PIPERX02EQDONE_in = (PIPERX02EQDONE !== 1'bz) && PIPERX02EQDONE_delay; // rv 0 + assign PIPERX02EQLPADAPTDONE_in = (PIPERX02EQLPADAPTDONE !== 1'bz) && PIPERX02EQLPADAPTDONE_delay; // rv 0 + assign PIPERX02EQLPLFFSSEL_in = (PIPERX02EQLPLFFSSEL !== 1'bz) && PIPERX02EQLPLFFSSEL_delay; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX02EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX02EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX02EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX02EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX02EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX02EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX02EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX02EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX02EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX02EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX02EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX02EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX02EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX02EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX02EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX02EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX02EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX02EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX02PHYSTATUS_in = (PIPERX02PHYSTATUS === 1'bz) || PIPERX02PHYSTATUS_delay; // rv 1 + assign PIPERX02STARTBLOCK_in[0] = (PIPERX02STARTBLOCK[0] !== 1'bz) && PIPERX02STARTBLOCK_delay[0]; // rv 0 + assign PIPERX02STARTBLOCK_in[1] = (PIPERX02STARTBLOCK[1] !== 1'bz) && PIPERX02STARTBLOCK_delay[1]; // rv 0 + assign PIPERX02STATUS_in[0] = (PIPERX02STATUS[0] !== 1'bz) && PIPERX02STATUS_delay[0]; // rv 0 + assign PIPERX02STATUS_in[1] = (PIPERX02STATUS[1] !== 1'bz) && PIPERX02STATUS_delay[1]; // rv 0 + assign PIPERX02STATUS_in[2] = (PIPERX02STATUS[2] !== 1'bz) && PIPERX02STATUS_delay[2]; // rv 0 + assign PIPERX02SYNCHEADER_in[0] = (PIPERX02SYNCHEADER[0] !== 1'bz) && PIPERX02SYNCHEADER_delay[0]; // rv 0 + assign PIPERX02SYNCHEADER_in[1] = (PIPERX02SYNCHEADER[1] !== 1'bz) && PIPERX02SYNCHEADER_delay[1]; // rv 0 + assign PIPERX02VALID_in = (PIPERX02VALID !== 1'bz) && PIPERX02VALID_delay; // rv 0 + assign PIPERX03CHARISK_in[0] = (PIPERX03CHARISK[0] === 1'bz) || PIPERX03CHARISK_delay[0]; // rv 1 + assign PIPERX03CHARISK_in[1] = (PIPERX03CHARISK[1] === 1'bz) || PIPERX03CHARISK_delay[1]; // rv 1 + assign PIPERX03DATAVALID_in = (PIPERX03DATAVALID !== 1'bz) && PIPERX03DATAVALID_delay; // rv 0 + assign PIPERX03DATA_in[0] = (PIPERX03DATA[0] !== 1'bz) && PIPERX03DATA_delay[0]; // rv 0 + assign PIPERX03DATA_in[10] = (PIPERX03DATA[10] !== 1'bz) && PIPERX03DATA_delay[10]; // rv 0 + assign PIPERX03DATA_in[11] = (PIPERX03DATA[11] !== 1'bz) && PIPERX03DATA_delay[11]; // rv 0 + assign PIPERX03DATA_in[12] = (PIPERX03DATA[12] !== 1'bz) && PIPERX03DATA_delay[12]; // rv 0 + assign PIPERX03DATA_in[13] = (PIPERX03DATA[13] !== 1'bz) && PIPERX03DATA_delay[13]; // rv 0 + assign PIPERX03DATA_in[14] = (PIPERX03DATA[14] !== 1'bz) && PIPERX03DATA_delay[14]; // rv 0 + assign PIPERX03DATA_in[15] = (PIPERX03DATA[15] !== 1'bz) && PIPERX03DATA_delay[15]; // rv 0 + assign PIPERX03DATA_in[16] = (PIPERX03DATA[16] !== 1'bz) && PIPERX03DATA_delay[16]; // rv 0 + assign PIPERX03DATA_in[17] = (PIPERX03DATA[17] !== 1'bz) && PIPERX03DATA_delay[17]; // rv 0 + assign PIPERX03DATA_in[18] = (PIPERX03DATA[18] !== 1'bz) && PIPERX03DATA_delay[18]; // rv 0 + assign PIPERX03DATA_in[19] = (PIPERX03DATA[19] !== 1'bz) && PIPERX03DATA_delay[19]; // rv 0 + assign PIPERX03DATA_in[1] = (PIPERX03DATA[1] !== 1'bz) && PIPERX03DATA_delay[1]; // rv 0 + assign PIPERX03DATA_in[20] = (PIPERX03DATA[20] !== 1'bz) && PIPERX03DATA_delay[20]; // rv 0 + assign PIPERX03DATA_in[21] = (PIPERX03DATA[21] !== 1'bz) && PIPERX03DATA_delay[21]; // rv 0 + assign PIPERX03DATA_in[22] = (PIPERX03DATA[22] !== 1'bz) && PIPERX03DATA_delay[22]; // rv 0 + assign PIPERX03DATA_in[23] = (PIPERX03DATA[23] !== 1'bz) && PIPERX03DATA_delay[23]; // rv 0 + assign PIPERX03DATA_in[24] = (PIPERX03DATA[24] !== 1'bz) && PIPERX03DATA_delay[24]; // rv 0 + assign PIPERX03DATA_in[25] = (PIPERX03DATA[25] !== 1'bz) && PIPERX03DATA_delay[25]; // rv 0 + assign PIPERX03DATA_in[26] = (PIPERX03DATA[26] !== 1'bz) && PIPERX03DATA_delay[26]; // rv 0 + assign PIPERX03DATA_in[27] = (PIPERX03DATA[27] !== 1'bz) && PIPERX03DATA_delay[27]; // rv 0 + assign PIPERX03DATA_in[28] = (PIPERX03DATA[28] !== 1'bz) && PIPERX03DATA_delay[28]; // rv 0 + assign PIPERX03DATA_in[29] = (PIPERX03DATA[29] !== 1'bz) && PIPERX03DATA_delay[29]; // rv 0 + assign PIPERX03DATA_in[2] = (PIPERX03DATA[2] !== 1'bz) && PIPERX03DATA_delay[2]; // rv 0 + assign PIPERX03DATA_in[30] = (PIPERX03DATA[30] !== 1'bz) && PIPERX03DATA_delay[30]; // rv 0 + assign PIPERX03DATA_in[31] = (PIPERX03DATA[31] !== 1'bz) && PIPERX03DATA_delay[31]; // rv 0 + assign PIPERX03DATA_in[3] = (PIPERX03DATA[3] !== 1'bz) && PIPERX03DATA_delay[3]; // rv 0 + assign PIPERX03DATA_in[4] = (PIPERX03DATA[4] !== 1'bz) && PIPERX03DATA_delay[4]; // rv 0 + assign PIPERX03DATA_in[5] = (PIPERX03DATA[5] !== 1'bz) && PIPERX03DATA_delay[5]; // rv 0 + assign PIPERX03DATA_in[6] = (PIPERX03DATA[6] !== 1'bz) && PIPERX03DATA_delay[6]; // rv 0 + assign PIPERX03DATA_in[7] = (PIPERX03DATA[7] !== 1'bz) && PIPERX03DATA_delay[7]; // rv 0 + assign PIPERX03DATA_in[8] = (PIPERX03DATA[8] !== 1'bz) && PIPERX03DATA_delay[8]; // rv 0 + assign PIPERX03DATA_in[9] = (PIPERX03DATA[9] !== 1'bz) && PIPERX03DATA_delay[9]; // rv 0 + assign PIPERX03ELECIDLE_in = (PIPERX03ELECIDLE === 1'bz) || PIPERX03ELECIDLE_delay; // rv 1 + assign PIPERX03EQDONE_in = (PIPERX03EQDONE !== 1'bz) && PIPERX03EQDONE_delay; // rv 0 + assign PIPERX03EQLPADAPTDONE_in = (PIPERX03EQLPADAPTDONE !== 1'bz) && PIPERX03EQLPADAPTDONE_delay; // rv 0 + assign PIPERX03EQLPLFFSSEL_in = (PIPERX03EQLPLFFSSEL !== 1'bz) && PIPERX03EQLPLFFSSEL_delay; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX03EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX03EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX03EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX03EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX03EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX03EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX03EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX03EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX03EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX03EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX03EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX03EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX03EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX03EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX03EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX03EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX03EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX03EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX03PHYSTATUS_in = (PIPERX03PHYSTATUS === 1'bz) || PIPERX03PHYSTATUS_delay; // rv 1 + assign PIPERX03STARTBLOCK_in[0] = (PIPERX03STARTBLOCK[0] !== 1'bz) && PIPERX03STARTBLOCK_delay[0]; // rv 0 + assign PIPERX03STARTBLOCK_in[1] = (PIPERX03STARTBLOCK[1] !== 1'bz) && PIPERX03STARTBLOCK_delay[1]; // rv 0 + assign PIPERX03STATUS_in[0] = (PIPERX03STATUS[0] !== 1'bz) && PIPERX03STATUS_delay[0]; // rv 0 + assign PIPERX03STATUS_in[1] = (PIPERX03STATUS[1] !== 1'bz) && PIPERX03STATUS_delay[1]; // rv 0 + assign PIPERX03STATUS_in[2] = (PIPERX03STATUS[2] !== 1'bz) && PIPERX03STATUS_delay[2]; // rv 0 + assign PIPERX03SYNCHEADER_in[0] = (PIPERX03SYNCHEADER[0] !== 1'bz) && PIPERX03SYNCHEADER_delay[0]; // rv 0 + assign PIPERX03SYNCHEADER_in[1] = (PIPERX03SYNCHEADER[1] !== 1'bz) && PIPERX03SYNCHEADER_delay[1]; // rv 0 + assign PIPERX03VALID_in = (PIPERX03VALID !== 1'bz) && PIPERX03VALID_delay; // rv 0 + assign PIPERX04CHARISK_in[0] = (PIPERX04CHARISK[0] === 1'bz) || PIPERX04CHARISK_delay[0]; // rv 1 + assign PIPERX04CHARISK_in[1] = (PIPERX04CHARISK[1] === 1'bz) || PIPERX04CHARISK_delay[1]; // rv 1 + assign PIPERX04DATAVALID_in = (PIPERX04DATAVALID !== 1'bz) && PIPERX04DATAVALID_delay; // rv 0 + assign PIPERX04DATA_in[0] = (PIPERX04DATA[0] !== 1'bz) && PIPERX04DATA_delay[0]; // rv 0 + assign PIPERX04DATA_in[10] = (PIPERX04DATA[10] !== 1'bz) && PIPERX04DATA_delay[10]; // rv 0 + assign PIPERX04DATA_in[11] = (PIPERX04DATA[11] !== 1'bz) && PIPERX04DATA_delay[11]; // rv 0 + assign PIPERX04DATA_in[12] = (PIPERX04DATA[12] !== 1'bz) && PIPERX04DATA_delay[12]; // rv 0 + assign PIPERX04DATA_in[13] = (PIPERX04DATA[13] !== 1'bz) && PIPERX04DATA_delay[13]; // rv 0 + assign PIPERX04DATA_in[14] = (PIPERX04DATA[14] !== 1'bz) && PIPERX04DATA_delay[14]; // rv 0 + assign PIPERX04DATA_in[15] = (PIPERX04DATA[15] !== 1'bz) && PIPERX04DATA_delay[15]; // rv 0 + assign PIPERX04DATA_in[16] = (PIPERX04DATA[16] !== 1'bz) && PIPERX04DATA_delay[16]; // rv 0 + assign PIPERX04DATA_in[17] = (PIPERX04DATA[17] !== 1'bz) && PIPERX04DATA_delay[17]; // rv 0 + assign PIPERX04DATA_in[18] = (PIPERX04DATA[18] !== 1'bz) && PIPERX04DATA_delay[18]; // rv 0 + assign PIPERX04DATA_in[19] = (PIPERX04DATA[19] !== 1'bz) && PIPERX04DATA_delay[19]; // rv 0 + assign PIPERX04DATA_in[1] = (PIPERX04DATA[1] !== 1'bz) && PIPERX04DATA_delay[1]; // rv 0 + assign PIPERX04DATA_in[20] = (PIPERX04DATA[20] !== 1'bz) && PIPERX04DATA_delay[20]; // rv 0 + assign PIPERX04DATA_in[21] = (PIPERX04DATA[21] !== 1'bz) && PIPERX04DATA_delay[21]; // rv 0 + assign PIPERX04DATA_in[22] = (PIPERX04DATA[22] !== 1'bz) && PIPERX04DATA_delay[22]; // rv 0 + assign PIPERX04DATA_in[23] = (PIPERX04DATA[23] !== 1'bz) && PIPERX04DATA_delay[23]; // rv 0 + assign PIPERX04DATA_in[24] = (PIPERX04DATA[24] !== 1'bz) && PIPERX04DATA_delay[24]; // rv 0 + assign PIPERX04DATA_in[25] = (PIPERX04DATA[25] !== 1'bz) && PIPERX04DATA_delay[25]; // rv 0 + assign PIPERX04DATA_in[26] = (PIPERX04DATA[26] !== 1'bz) && PIPERX04DATA_delay[26]; // rv 0 + assign PIPERX04DATA_in[27] = (PIPERX04DATA[27] !== 1'bz) && PIPERX04DATA_delay[27]; // rv 0 + assign PIPERX04DATA_in[28] = (PIPERX04DATA[28] !== 1'bz) && PIPERX04DATA_delay[28]; // rv 0 + assign PIPERX04DATA_in[29] = (PIPERX04DATA[29] !== 1'bz) && PIPERX04DATA_delay[29]; // rv 0 + assign PIPERX04DATA_in[2] = (PIPERX04DATA[2] !== 1'bz) && PIPERX04DATA_delay[2]; // rv 0 + assign PIPERX04DATA_in[30] = (PIPERX04DATA[30] !== 1'bz) && PIPERX04DATA_delay[30]; // rv 0 + assign PIPERX04DATA_in[31] = (PIPERX04DATA[31] !== 1'bz) && PIPERX04DATA_delay[31]; // rv 0 + assign PIPERX04DATA_in[3] = (PIPERX04DATA[3] !== 1'bz) && PIPERX04DATA_delay[3]; // rv 0 + assign PIPERX04DATA_in[4] = (PIPERX04DATA[4] !== 1'bz) && PIPERX04DATA_delay[4]; // rv 0 + assign PIPERX04DATA_in[5] = (PIPERX04DATA[5] !== 1'bz) && PIPERX04DATA_delay[5]; // rv 0 + assign PIPERX04DATA_in[6] = (PIPERX04DATA[6] !== 1'bz) && PIPERX04DATA_delay[6]; // rv 0 + assign PIPERX04DATA_in[7] = (PIPERX04DATA[7] !== 1'bz) && PIPERX04DATA_delay[7]; // rv 0 + assign PIPERX04DATA_in[8] = (PIPERX04DATA[8] !== 1'bz) && PIPERX04DATA_delay[8]; // rv 0 + assign PIPERX04DATA_in[9] = (PIPERX04DATA[9] !== 1'bz) && PIPERX04DATA_delay[9]; // rv 0 + assign PIPERX04ELECIDLE_in = (PIPERX04ELECIDLE === 1'bz) || PIPERX04ELECIDLE_delay; // rv 1 + assign PIPERX04EQDONE_in = (PIPERX04EQDONE !== 1'bz) && PIPERX04EQDONE_delay; // rv 0 + assign PIPERX04EQLPADAPTDONE_in = (PIPERX04EQLPADAPTDONE !== 1'bz) && PIPERX04EQLPADAPTDONE_delay; // rv 0 + assign PIPERX04EQLPLFFSSEL_in = (PIPERX04EQLPLFFSSEL !== 1'bz) && PIPERX04EQLPLFFSSEL_delay; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX04EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX04EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX04EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX04EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX04EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX04EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX04EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX04EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX04EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX04EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX04EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX04EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX04EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX04EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX04EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX04EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX04EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX04EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX04PHYSTATUS_in = (PIPERX04PHYSTATUS === 1'bz) || PIPERX04PHYSTATUS_delay; // rv 1 + assign PIPERX04STARTBLOCK_in[0] = (PIPERX04STARTBLOCK[0] !== 1'bz) && PIPERX04STARTBLOCK_delay[0]; // rv 0 + assign PIPERX04STARTBLOCK_in[1] = (PIPERX04STARTBLOCK[1] !== 1'bz) && PIPERX04STARTBLOCK_delay[1]; // rv 0 + assign PIPERX04STATUS_in[0] = (PIPERX04STATUS[0] !== 1'bz) && PIPERX04STATUS_delay[0]; // rv 0 + assign PIPERX04STATUS_in[1] = (PIPERX04STATUS[1] !== 1'bz) && PIPERX04STATUS_delay[1]; // rv 0 + assign PIPERX04STATUS_in[2] = (PIPERX04STATUS[2] !== 1'bz) && PIPERX04STATUS_delay[2]; // rv 0 + assign PIPERX04SYNCHEADER_in[0] = (PIPERX04SYNCHEADER[0] !== 1'bz) && PIPERX04SYNCHEADER_delay[0]; // rv 0 + assign PIPERX04SYNCHEADER_in[1] = (PIPERX04SYNCHEADER[1] !== 1'bz) && PIPERX04SYNCHEADER_delay[1]; // rv 0 + assign PIPERX04VALID_in = (PIPERX04VALID !== 1'bz) && PIPERX04VALID_delay; // rv 0 + assign PIPERX05CHARISK_in[0] = (PIPERX05CHARISK[0] === 1'bz) || PIPERX05CHARISK_delay[0]; // rv 1 + assign PIPERX05CHARISK_in[1] = (PIPERX05CHARISK[1] === 1'bz) || PIPERX05CHARISK_delay[1]; // rv 1 + assign PIPERX05DATAVALID_in = (PIPERX05DATAVALID !== 1'bz) && PIPERX05DATAVALID_delay; // rv 0 + assign PIPERX05DATA_in[0] = (PIPERX05DATA[0] !== 1'bz) && PIPERX05DATA_delay[0]; // rv 0 + assign PIPERX05DATA_in[10] = (PIPERX05DATA[10] !== 1'bz) && PIPERX05DATA_delay[10]; // rv 0 + assign PIPERX05DATA_in[11] = (PIPERX05DATA[11] !== 1'bz) && PIPERX05DATA_delay[11]; // rv 0 + assign PIPERX05DATA_in[12] = (PIPERX05DATA[12] !== 1'bz) && PIPERX05DATA_delay[12]; // rv 0 + assign PIPERX05DATA_in[13] = (PIPERX05DATA[13] !== 1'bz) && PIPERX05DATA_delay[13]; // rv 0 + assign PIPERX05DATA_in[14] = (PIPERX05DATA[14] !== 1'bz) && PIPERX05DATA_delay[14]; // rv 0 + assign PIPERX05DATA_in[15] = (PIPERX05DATA[15] !== 1'bz) && PIPERX05DATA_delay[15]; // rv 0 + assign PIPERX05DATA_in[16] = (PIPERX05DATA[16] !== 1'bz) && PIPERX05DATA_delay[16]; // rv 0 + assign PIPERX05DATA_in[17] = (PIPERX05DATA[17] !== 1'bz) && PIPERX05DATA_delay[17]; // rv 0 + assign PIPERX05DATA_in[18] = (PIPERX05DATA[18] !== 1'bz) && PIPERX05DATA_delay[18]; // rv 0 + assign PIPERX05DATA_in[19] = (PIPERX05DATA[19] !== 1'bz) && PIPERX05DATA_delay[19]; // rv 0 + assign PIPERX05DATA_in[1] = (PIPERX05DATA[1] !== 1'bz) && PIPERX05DATA_delay[1]; // rv 0 + assign PIPERX05DATA_in[20] = (PIPERX05DATA[20] !== 1'bz) && PIPERX05DATA_delay[20]; // rv 0 + assign PIPERX05DATA_in[21] = (PIPERX05DATA[21] !== 1'bz) && PIPERX05DATA_delay[21]; // rv 0 + assign PIPERX05DATA_in[22] = (PIPERX05DATA[22] !== 1'bz) && PIPERX05DATA_delay[22]; // rv 0 + assign PIPERX05DATA_in[23] = (PIPERX05DATA[23] !== 1'bz) && PIPERX05DATA_delay[23]; // rv 0 + assign PIPERX05DATA_in[24] = (PIPERX05DATA[24] !== 1'bz) && PIPERX05DATA_delay[24]; // rv 0 + assign PIPERX05DATA_in[25] = (PIPERX05DATA[25] !== 1'bz) && PIPERX05DATA_delay[25]; // rv 0 + assign PIPERX05DATA_in[26] = (PIPERX05DATA[26] !== 1'bz) && PIPERX05DATA_delay[26]; // rv 0 + assign PIPERX05DATA_in[27] = (PIPERX05DATA[27] !== 1'bz) && PIPERX05DATA_delay[27]; // rv 0 + assign PIPERX05DATA_in[28] = (PIPERX05DATA[28] !== 1'bz) && PIPERX05DATA_delay[28]; // rv 0 + assign PIPERX05DATA_in[29] = (PIPERX05DATA[29] !== 1'bz) && PIPERX05DATA_delay[29]; // rv 0 + assign PIPERX05DATA_in[2] = (PIPERX05DATA[2] !== 1'bz) && PIPERX05DATA_delay[2]; // rv 0 + assign PIPERX05DATA_in[30] = (PIPERX05DATA[30] !== 1'bz) && PIPERX05DATA_delay[30]; // rv 0 + assign PIPERX05DATA_in[31] = (PIPERX05DATA[31] !== 1'bz) && PIPERX05DATA_delay[31]; // rv 0 + assign PIPERX05DATA_in[3] = (PIPERX05DATA[3] !== 1'bz) && PIPERX05DATA_delay[3]; // rv 0 + assign PIPERX05DATA_in[4] = (PIPERX05DATA[4] !== 1'bz) && PIPERX05DATA_delay[4]; // rv 0 + assign PIPERX05DATA_in[5] = (PIPERX05DATA[5] !== 1'bz) && PIPERX05DATA_delay[5]; // rv 0 + assign PIPERX05DATA_in[6] = (PIPERX05DATA[6] !== 1'bz) && PIPERX05DATA_delay[6]; // rv 0 + assign PIPERX05DATA_in[7] = (PIPERX05DATA[7] !== 1'bz) && PIPERX05DATA_delay[7]; // rv 0 + assign PIPERX05DATA_in[8] = (PIPERX05DATA[8] !== 1'bz) && PIPERX05DATA_delay[8]; // rv 0 + assign PIPERX05DATA_in[9] = (PIPERX05DATA[9] !== 1'bz) && PIPERX05DATA_delay[9]; // rv 0 + assign PIPERX05ELECIDLE_in = (PIPERX05ELECIDLE === 1'bz) || PIPERX05ELECIDLE_delay; // rv 1 + assign PIPERX05EQDONE_in = (PIPERX05EQDONE !== 1'bz) && PIPERX05EQDONE_delay; // rv 0 + assign PIPERX05EQLPADAPTDONE_in = (PIPERX05EQLPADAPTDONE !== 1'bz) && PIPERX05EQLPADAPTDONE_delay; // rv 0 + assign PIPERX05EQLPLFFSSEL_in = (PIPERX05EQLPLFFSSEL !== 1'bz) && PIPERX05EQLPLFFSSEL_delay; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX05EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX05EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX05EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX05EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX05EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX05EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX05EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX05EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX05EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX05EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX05EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX05EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX05EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX05EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX05EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX05EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX05EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX05EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX05PHYSTATUS_in = (PIPERX05PHYSTATUS === 1'bz) || PIPERX05PHYSTATUS_delay; // rv 1 + assign PIPERX05STARTBLOCK_in[0] = (PIPERX05STARTBLOCK[0] !== 1'bz) && PIPERX05STARTBLOCK_delay[0]; // rv 0 + assign PIPERX05STARTBLOCK_in[1] = (PIPERX05STARTBLOCK[1] !== 1'bz) && PIPERX05STARTBLOCK_delay[1]; // rv 0 + assign PIPERX05STATUS_in[0] = (PIPERX05STATUS[0] !== 1'bz) && PIPERX05STATUS_delay[0]; // rv 0 + assign PIPERX05STATUS_in[1] = (PIPERX05STATUS[1] !== 1'bz) && PIPERX05STATUS_delay[1]; // rv 0 + assign PIPERX05STATUS_in[2] = (PIPERX05STATUS[2] !== 1'bz) && PIPERX05STATUS_delay[2]; // rv 0 + assign PIPERX05SYNCHEADER_in[0] = (PIPERX05SYNCHEADER[0] !== 1'bz) && PIPERX05SYNCHEADER_delay[0]; // rv 0 + assign PIPERX05SYNCHEADER_in[1] = (PIPERX05SYNCHEADER[1] !== 1'bz) && PIPERX05SYNCHEADER_delay[1]; // rv 0 + assign PIPERX05VALID_in = (PIPERX05VALID !== 1'bz) && PIPERX05VALID_delay; // rv 0 + assign PIPERX06CHARISK_in[0] = (PIPERX06CHARISK[0] === 1'bz) || PIPERX06CHARISK_delay[0]; // rv 1 + assign PIPERX06CHARISK_in[1] = (PIPERX06CHARISK[1] === 1'bz) || PIPERX06CHARISK_delay[1]; // rv 1 + assign PIPERX06DATAVALID_in = (PIPERX06DATAVALID !== 1'bz) && PIPERX06DATAVALID_delay; // rv 0 + assign PIPERX06DATA_in[0] = (PIPERX06DATA[0] !== 1'bz) && PIPERX06DATA_delay[0]; // rv 0 + assign PIPERX06DATA_in[10] = (PIPERX06DATA[10] !== 1'bz) && PIPERX06DATA_delay[10]; // rv 0 + assign PIPERX06DATA_in[11] = (PIPERX06DATA[11] !== 1'bz) && PIPERX06DATA_delay[11]; // rv 0 + assign PIPERX06DATA_in[12] = (PIPERX06DATA[12] !== 1'bz) && PIPERX06DATA_delay[12]; // rv 0 + assign PIPERX06DATA_in[13] = (PIPERX06DATA[13] !== 1'bz) && PIPERX06DATA_delay[13]; // rv 0 + assign PIPERX06DATA_in[14] = (PIPERX06DATA[14] !== 1'bz) && PIPERX06DATA_delay[14]; // rv 0 + assign PIPERX06DATA_in[15] = (PIPERX06DATA[15] !== 1'bz) && PIPERX06DATA_delay[15]; // rv 0 + assign PIPERX06DATA_in[16] = (PIPERX06DATA[16] !== 1'bz) && PIPERX06DATA_delay[16]; // rv 0 + assign PIPERX06DATA_in[17] = (PIPERX06DATA[17] !== 1'bz) && PIPERX06DATA_delay[17]; // rv 0 + assign PIPERX06DATA_in[18] = (PIPERX06DATA[18] !== 1'bz) && PIPERX06DATA_delay[18]; // rv 0 + assign PIPERX06DATA_in[19] = (PIPERX06DATA[19] !== 1'bz) && PIPERX06DATA_delay[19]; // rv 0 + assign PIPERX06DATA_in[1] = (PIPERX06DATA[1] !== 1'bz) && PIPERX06DATA_delay[1]; // rv 0 + assign PIPERX06DATA_in[20] = (PIPERX06DATA[20] !== 1'bz) && PIPERX06DATA_delay[20]; // rv 0 + assign PIPERX06DATA_in[21] = (PIPERX06DATA[21] !== 1'bz) && PIPERX06DATA_delay[21]; // rv 0 + assign PIPERX06DATA_in[22] = (PIPERX06DATA[22] !== 1'bz) && PIPERX06DATA_delay[22]; // rv 0 + assign PIPERX06DATA_in[23] = (PIPERX06DATA[23] !== 1'bz) && PIPERX06DATA_delay[23]; // rv 0 + assign PIPERX06DATA_in[24] = (PIPERX06DATA[24] !== 1'bz) && PIPERX06DATA_delay[24]; // rv 0 + assign PIPERX06DATA_in[25] = (PIPERX06DATA[25] !== 1'bz) && PIPERX06DATA_delay[25]; // rv 0 + assign PIPERX06DATA_in[26] = (PIPERX06DATA[26] !== 1'bz) && PIPERX06DATA_delay[26]; // rv 0 + assign PIPERX06DATA_in[27] = (PIPERX06DATA[27] !== 1'bz) && PIPERX06DATA_delay[27]; // rv 0 + assign PIPERX06DATA_in[28] = (PIPERX06DATA[28] !== 1'bz) && PIPERX06DATA_delay[28]; // rv 0 + assign PIPERX06DATA_in[29] = (PIPERX06DATA[29] !== 1'bz) && PIPERX06DATA_delay[29]; // rv 0 + assign PIPERX06DATA_in[2] = (PIPERX06DATA[2] !== 1'bz) && PIPERX06DATA_delay[2]; // rv 0 + assign PIPERX06DATA_in[30] = (PIPERX06DATA[30] !== 1'bz) && PIPERX06DATA_delay[30]; // rv 0 + assign PIPERX06DATA_in[31] = (PIPERX06DATA[31] !== 1'bz) && PIPERX06DATA_delay[31]; // rv 0 + assign PIPERX06DATA_in[3] = (PIPERX06DATA[3] !== 1'bz) && PIPERX06DATA_delay[3]; // rv 0 + assign PIPERX06DATA_in[4] = (PIPERX06DATA[4] !== 1'bz) && PIPERX06DATA_delay[4]; // rv 0 + assign PIPERX06DATA_in[5] = (PIPERX06DATA[5] !== 1'bz) && PIPERX06DATA_delay[5]; // rv 0 + assign PIPERX06DATA_in[6] = (PIPERX06DATA[6] !== 1'bz) && PIPERX06DATA_delay[6]; // rv 0 + assign PIPERX06DATA_in[7] = (PIPERX06DATA[7] !== 1'bz) && PIPERX06DATA_delay[7]; // rv 0 + assign PIPERX06DATA_in[8] = (PIPERX06DATA[8] !== 1'bz) && PIPERX06DATA_delay[8]; // rv 0 + assign PIPERX06DATA_in[9] = (PIPERX06DATA[9] !== 1'bz) && PIPERX06DATA_delay[9]; // rv 0 + assign PIPERX06ELECIDLE_in = (PIPERX06ELECIDLE === 1'bz) || PIPERX06ELECIDLE_delay; // rv 1 + assign PIPERX06EQDONE_in = (PIPERX06EQDONE !== 1'bz) && PIPERX06EQDONE_delay; // rv 0 + assign PIPERX06EQLPADAPTDONE_in = (PIPERX06EQLPADAPTDONE !== 1'bz) && PIPERX06EQLPADAPTDONE_delay; // rv 0 + assign PIPERX06EQLPLFFSSEL_in = (PIPERX06EQLPLFFSSEL !== 1'bz) && PIPERX06EQLPLFFSSEL_delay; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX06EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX06EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX06EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX06EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX06EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX06EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX06EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX06EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX06EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX06EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX06EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX06EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX06EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX06EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX06EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX06EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX06EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX06EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX06PHYSTATUS_in = (PIPERX06PHYSTATUS === 1'bz) || PIPERX06PHYSTATUS_delay; // rv 1 + assign PIPERX06STARTBLOCK_in[0] = (PIPERX06STARTBLOCK[0] !== 1'bz) && PIPERX06STARTBLOCK_delay[0]; // rv 0 + assign PIPERX06STARTBLOCK_in[1] = (PIPERX06STARTBLOCK[1] !== 1'bz) && PIPERX06STARTBLOCK_delay[1]; // rv 0 + assign PIPERX06STATUS_in[0] = (PIPERX06STATUS[0] !== 1'bz) && PIPERX06STATUS_delay[0]; // rv 0 + assign PIPERX06STATUS_in[1] = (PIPERX06STATUS[1] !== 1'bz) && PIPERX06STATUS_delay[1]; // rv 0 + assign PIPERX06STATUS_in[2] = (PIPERX06STATUS[2] !== 1'bz) && PIPERX06STATUS_delay[2]; // rv 0 + assign PIPERX06SYNCHEADER_in[0] = (PIPERX06SYNCHEADER[0] !== 1'bz) && PIPERX06SYNCHEADER_delay[0]; // rv 0 + assign PIPERX06SYNCHEADER_in[1] = (PIPERX06SYNCHEADER[1] !== 1'bz) && PIPERX06SYNCHEADER_delay[1]; // rv 0 + assign PIPERX06VALID_in = (PIPERX06VALID !== 1'bz) && PIPERX06VALID_delay; // rv 0 + assign PIPERX07CHARISK_in[0] = (PIPERX07CHARISK[0] === 1'bz) || PIPERX07CHARISK_delay[0]; // rv 1 + assign PIPERX07CHARISK_in[1] = (PIPERX07CHARISK[1] === 1'bz) || PIPERX07CHARISK_delay[1]; // rv 1 + assign PIPERX07DATAVALID_in = (PIPERX07DATAVALID !== 1'bz) && PIPERX07DATAVALID_delay; // rv 0 + assign PIPERX07DATA_in[0] = (PIPERX07DATA[0] !== 1'bz) && PIPERX07DATA_delay[0]; // rv 0 + assign PIPERX07DATA_in[10] = (PIPERX07DATA[10] !== 1'bz) && PIPERX07DATA_delay[10]; // rv 0 + assign PIPERX07DATA_in[11] = (PIPERX07DATA[11] !== 1'bz) && PIPERX07DATA_delay[11]; // rv 0 + assign PIPERX07DATA_in[12] = (PIPERX07DATA[12] !== 1'bz) && PIPERX07DATA_delay[12]; // rv 0 + assign PIPERX07DATA_in[13] = (PIPERX07DATA[13] !== 1'bz) && PIPERX07DATA_delay[13]; // rv 0 + assign PIPERX07DATA_in[14] = (PIPERX07DATA[14] !== 1'bz) && PIPERX07DATA_delay[14]; // rv 0 + assign PIPERX07DATA_in[15] = (PIPERX07DATA[15] !== 1'bz) && PIPERX07DATA_delay[15]; // rv 0 + assign PIPERX07DATA_in[16] = (PIPERX07DATA[16] !== 1'bz) && PIPERX07DATA_delay[16]; // rv 0 + assign PIPERX07DATA_in[17] = (PIPERX07DATA[17] !== 1'bz) && PIPERX07DATA_delay[17]; // rv 0 + assign PIPERX07DATA_in[18] = (PIPERX07DATA[18] !== 1'bz) && PIPERX07DATA_delay[18]; // rv 0 + assign PIPERX07DATA_in[19] = (PIPERX07DATA[19] !== 1'bz) && PIPERX07DATA_delay[19]; // rv 0 + assign PIPERX07DATA_in[1] = (PIPERX07DATA[1] !== 1'bz) && PIPERX07DATA_delay[1]; // rv 0 + assign PIPERX07DATA_in[20] = (PIPERX07DATA[20] !== 1'bz) && PIPERX07DATA_delay[20]; // rv 0 + assign PIPERX07DATA_in[21] = (PIPERX07DATA[21] !== 1'bz) && PIPERX07DATA_delay[21]; // rv 0 + assign PIPERX07DATA_in[22] = (PIPERX07DATA[22] !== 1'bz) && PIPERX07DATA_delay[22]; // rv 0 + assign PIPERX07DATA_in[23] = (PIPERX07DATA[23] !== 1'bz) && PIPERX07DATA_delay[23]; // rv 0 + assign PIPERX07DATA_in[24] = (PIPERX07DATA[24] !== 1'bz) && PIPERX07DATA_delay[24]; // rv 0 + assign PIPERX07DATA_in[25] = (PIPERX07DATA[25] !== 1'bz) && PIPERX07DATA_delay[25]; // rv 0 + assign PIPERX07DATA_in[26] = (PIPERX07DATA[26] !== 1'bz) && PIPERX07DATA_delay[26]; // rv 0 + assign PIPERX07DATA_in[27] = (PIPERX07DATA[27] !== 1'bz) && PIPERX07DATA_delay[27]; // rv 0 + assign PIPERX07DATA_in[28] = (PIPERX07DATA[28] !== 1'bz) && PIPERX07DATA_delay[28]; // rv 0 + assign PIPERX07DATA_in[29] = (PIPERX07DATA[29] !== 1'bz) && PIPERX07DATA_delay[29]; // rv 0 + assign PIPERX07DATA_in[2] = (PIPERX07DATA[2] !== 1'bz) && PIPERX07DATA_delay[2]; // rv 0 + assign PIPERX07DATA_in[30] = (PIPERX07DATA[30] !== 1'bz) && PIPERX07DATA_delay[30]; // rv 0 + assign PIPERX07DATA_in[31] = (PIPERX07DATA[31] !== 1'bz) && PIPERX07DATA_delay[31]; // rv 0 + assign PIPERX07DATA_in[3] = (PIPERX07DATA[3] !== 1'bz) && PIPERX07DATA_delay[3]; // rv 0 + assign PIPERX07DATA_in[4] = (PIPERX07DATA[4] !== 1'bz) && PIPERX07DATA_delay[4]; // rv 0 + assign PIPERX07DATA_in[5] = (PIPERX07DATA[5] !== 1'bz) && PIPERX07DATA_delay[5]; // rv 0 + assign PIPERX07DATA_in[6] = (PIPERX07DATA[6] !== 1'bz) && PIPERX07DATA_delay[6]; // rv 0 + assign PIPERX07DATA_in[7] = (PIPERX07DATA[7] !== 1'bz) && PIPERX07DATA_delay[7]; // rv 0 + assign PIPERX07DATA_in[8] = (PIPERX07DATA[8] !== 1'bz) && PIPERX07DATA_delay[8]; // rv 0 + assign PIPERX07DATA_in[9] = (PIPERX07DATA[9] !== 1'bz) && PIPERX07DATA_delay[9]; // rv 0 + assign PIPERX07ELECIDLE_in = (PIPERX07ELECIDLE === 1'bz) || PIPERX07ELECIDLE_delay; // rv 1 + assign PIPERX07EQDONE_in = (PIPERX07EQDONE !== 1'bz) && PIPERX07EQDONE_delay; // rv 0 + assign PIPERX07EQLPADAPTDONE_in = (PIPERX07EQLPADAPTDONE !== 1'bz) && PIPERX07EQLPADAPTDONE_delay; // rv 0 + assign PIPERX07EQLPLFFSSEL_in = (PIPERX07EQLPLFFSSEL !== 1'bz) && PIPERX07EQLPLFFSSEL_delay; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX07EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX07EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX07EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX07EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX07EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX07EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX07EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX07EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX07EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX07EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX07EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX07EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX07EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX07EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX07EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX07EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX07EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX07EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX07PHYSTATUS_in = (PIPERX07PHYSTATUS === 1'bz) || PIPERX07PHYSTATUS_delay; // rv 1 + assign PIPERX07STARTBLOCK_in[0] = (PIPERX07STARTBLOCK[0] !== 1'bz) && PIPERX07STARTBLOCK_delay[0]; // rv 0 + assign PIPERX07STARTBLOCK_in[1] = (PIPERX07STARTBLOCK[1] !== 1'bz) && PIPERX07STARTBLOCK_delay[1]; // rv 0 + assign PIPERX07STATUS_in[0] = (PIPERX07STATUS[0] !== 1'bz) && PIPERX07STATUS_delay[0]; // rv 0 + assign PIPERX07STATUS_in[1] = (PIPERX07STATUS[1] !== 1'bz) && PIPERX07STATUS_delay[1]; // rv 0 + assign PIPERX07STATUS_in[2] = (PIPERX07STATUS[2] !== 1'bz) && PIPERX07STATUS_delay[2]; // rv 0 + assign PIPERX07SYNCHEADER_in[0] = (PIPERX07SYNCHEADER[0] !== 1'bz) && PIPERX07SYNCHEADER_delay[0]; // rv 0 + assign PIPERX07SYNCHEADER_in[1] = (PIPERX07SYNCHEADER[1] !== 1'bz) && PIPERX07SYNCHEADER_delay[1]; // rv 0 + assign PIPERX07VALID_in = (PIPERX07VALID !== 1'bz) && PIPERX07VALID_delay; // rv 0 + assign PIPERX08CHARISK_in[0] = (PIPERX08CHARISK[0] === 1'bz) || PIPERX08CHARISK_delay[0]; // rv 1 + assign PIPERX08CHARISK_in[1] = (PIPERX08CHARISK[1] === 1'bz) || PIPERX08CHARISK_delay[1]; // rv 1 + assign PIPERX08DATAVALID_in = (PIPERX08DATAVALID !== 1'bz) && PIPERX08DATAVALID_delay; // rv 0 + assign PIPERX08DATA_in[0] = (PIPERX08DATA[0] !== 1'bz) && PIPERX08DATA_delay[0]; // rv 0 + assign PIPERX08DATA_in[10] = (PIPERX08DATA[10] !== 1'bz) && PIPERX08DATA_delay[10]; // rv 0 + assign PIPERX08DATA_in[11] = (PIPERX08DATA[11] !== 1'bz) && PIPERX08DATA_delay[11]; // rv 0 + assign PIPERX08DATA_in[12] = (PIPERX08DATA[12] !== 1'bz) && PIPERX08DATA_delay[12]; // rv 0 + assign PIPERX08DATA_in[13] = (PIPERX08DATA[13] !== 1'bz) && PIPERX08DATA_delay[13]; // rv 0 + assign PIPERX08DATA_in[14] = (PIPERX08DATA[14] !== 1'bz) && PIPERX08DATA_delay[14]; // rv 0 + assign PIPERX08DATA_in[15] = (PIPERX08DATA[15] !== 1'bz) && PIPERX08DATA_delay[15]; // rv 0 + assign PIPERX08DATA_in[16] = (PIPERX08DATA[16] !== 1'bz) && PIPERX08DATA_delay[16]; // rv 0 + assign PIPERX08DATA_in[17] = (PIPERX08DATA[17] !== 1'bz) && PIPERX08DATA_delay[17]; // rv 0 + assign PIPERX08DATA_in[18] = (PIPERX08DATA[18] !== 1'bz) && PIPERX08DATA_delay[18]; // rv 0 + assign PIPERX08DATA_in[19] = (PIPERX08DATA[19] !== 1'bz) && PIPERX08DATA_delay[19]; // rv 0 + assign PIPERX08DATA_in[1] = (PIPERX08DATA[1] !== 1'bz) && PIPERX08DATA_delay[1]; // rv 0 + assign PIPERX08DATA_in[20] = (PIPERX08DATA[20] !== 1'bz) && PIPERX08DATA_delay[20]; // rv 0 + assign PIPERX08DATA_in[21] = (PIPERX08DATA[21] !== 1'bz) && PIPERX08DATA_delay[21]; // rv 0 + assign PIPERX08DATA_in[22] = (PIPERX08DATA[22] !== 1'bz) && PIPERX08DATA_delay[22]; // rv 0 + assign PIPERX08DATA_in[23] = (PIPERX08DATA[23] !== 1'bz) && PIPERX08DATA_delay[23]; // rv 0 + assign PIPERX08DATA_in[24] = (PIPERX08DATA[24] !== 1'bz) && PIPERX08DATA_delay[24]; // rv 0 + assign PIPERX08DATA_in[25] = (PIPERX08DATA[25] !== 1'bz) && PIPERX08DATA_delay[25]; // rv 0 + assign PIPERX08DATA_in[26] = (PIPERX08DATA[26] !== 1'bz) && PIPERX08DATA_delay[26]; // rv 0 + assign PIPERX08DATA_in[27] = (PIPERX08DATA[27] !== 1'bz) && PIPERX08DATA_delay[27]; // rv 0 + assign PIPERX08DATA_in[28] = (PIPERX08DATA[28] !== 1'bz) && PIPERX08DATA_delay[28]; // rv 0 + assign PIPERX08DATA_in[29] = (PIPERX08DATA[29] !== 1'bz) && PIPERX08DATA_delay[29]; // rv 0 + assign PIPERX08DATA_in[2] = (PIPERX08DATA[2] !== 1'bz) && PIPERX08DATA_delay[2]; // rv 0 + assign PIPERX08DATA_in[30] = (PIPERX08DATA[30] !== 1'bz) && PIPERX08DATA_delay[30]; // rv 0 + assign PIPERX08DATA_in[31] = (PIPERX08DATA[31] !== 1'bz) && PIPERX08DATA_delay[31]; // rv 0 + assign PIPERX08DATA_in[3] = (PIPERX08DATA[3] !== 1'bz) && PIPERX08DATA_delay[3]; // rv 0 + assign PIPERX08DATA_in[4] = (PIPERX08DATA[4] !== 1'bz) && PIPERX08DATA_delay[4]; // rv 0 + assign PIPERX08DATA_in[5] = (PIPERX08DATA[5] !== 1'bz) && PIPERX08DATA_delay[5]; // rv 0 + assign PIPERX08DATA_in[6] = (PIPERX08DATA[6] !== 1'bz) && PIPERX08DATA_delay[6]; // rv 0 + assign PIPERX08DATA_in[7] = (PIPERX08DATA[7] !== 1'bz) && PIPERX08DATA_delay[7]; // rv 0 + assign PIPERX08DATA_in[8] = (PIPERX08DATA[8] !== 1'bz) && PIPERX08DATA_delay[8]; // rv 0 + assign PIPERX08DATA_in[9] = (PIPERX08DATA[9] !== 1'bz) && PIPERX08DATA_delay[9]; // rv 0 + assign PIPERX08ELECIDLE_in = (PIPERX08ELECIDLE === 1'bz) || PIPERX08ELECIDLE_delay; // rv 1 + assign PIPERX08EQDONE_in = (PIPERX08EQDONE !== 1'bz) && PIPERX08EQDONE_delay; // rv 0 + assign PIPERX08EQLPADAPTDONE_in = (PIPERX08EQLPADAPTDONE !== 1'bz) && PIPERX08EQLPADAPTDONE_delay; // rv 0 + assign PIPERX08EQLPLFFSSEL_in = (PIPERX08EQLPLFFSSEL !== 1'bz) && PIPERX08EQLPLFFSSEL_delay; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX08EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX08EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX08EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX08EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX08EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX08EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX08EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX08EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX08EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX08EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX08EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX08EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX08EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX08EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX08EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX08EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX08EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX08EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX08PHYSTATUS_in = (PIPERX08PHYSTATUS === 1'bz) || PIPERX08PHYSTATUS_delay; // rv 1 + assign PIPERX08STARTBLOCK_in[0] = (PIPERX08STARTBLOCK[0] !== 1'bz) && PIPERX08STARTBLOCK_delay[0]; // rv 0 + assign PIPERX08STARTBLOCK_in[1] = (PIPERX08STARTBLOCK[1] !== 1'bz) && PIPERX08STARTBLOCK_delay[1]; // rv 0 + assign PIPERX08STATUS_in[0] = (PIPERX08STATUS[0] !== 1'bz) && PIPERX08STATUS_delay[0]; // rv 0 + assign PIPERX08STATUS_in[1] = (PIPERX08STATUS[1] !== 1'bz) && PIPERX08STATUS_delay[1]; // rv 0 + assign PIPERX08STATUS_in[2] = (PIPERX08STATUS[2] !== 1'bz) && PIPERX08STATUS_delay[2]; // rv 0 + assign PIPERX08SYNCHEADER_in[0] = (PIPERX08SYNCHEADER[0] !== 1'bz) && PIPERX08SYNCHEADER_delay[0]; // rv 0 + assign PIPERX08SYNCHEADER_in[1] = (PIPERX08SYNCHEADER[1] !== 1'bz) && PIPERX08SYNCHEADER_delay[1]; // rv 0 + assign PIPERX08VALID_in = (PIPERX08VALID !== 1'bz) && PIPERX08VALID_delay; // rv 0 + assign PIPERX09CHARISK_in[0] = (PIPERX09CHARISK[0] === 1'bz) || PIPERX09CHARISK_delay[0]; // rv 1 + assign PIPERX09CHARISK_in[1] = (PIPERX09CHARISK[1] === 1'bz) || PIPERX09CHARISK_delay[1]; // rv 1 + assign PIPERX09DATAVALID_in = (PIPERX09DATAVALID !== 1'bz) && PIPERX09DATAVALID_delay; // rv 0 + assign PIPERX09DATA_in[0] = (PIPERX09DATA[0] !== 1'bz) && PIPERX09DATA_delay[0]; // rv 0 + assign PIPERX09DATA_in[10] = (PIPERX09DATA[10] !== 1'bz) && PIPERX09DATA_delay[10]; // rv 0 + assign PIPERX09DATA_in[11] = (PIPERX09DATA[11] !== 1'bz) && PIPERX09DATA_delay[11]; // rv 0 + assign PIPERX09DATA_in[12] = (PIPERX09DATA[12] !== 1'bz) && PIPERX09DATA_delay[12]; // rv 0 + assign PIPERX09DATA_in[13] = (PIPERX09DATA[13] !== 1'bz) && PIPERX09DATA_delay[13]; // rv 0 + assign PIPERX09DATA_in[14] = (PIPERX09DATA[14] !== 1'bz) && PIPERX09DATA_delay[14]; // rv 0 + assign PIPERX09DATA_in[15] = (PIPERX09DATA[15] !== 1'bz) && PIPERX09DATA_delay[15]; // rv 0 + assign PIPERX09DATA_in[16] = (PIPERX09DATA[16] !== 1'bz) && PIPERX09DATA_delay[16]; // rv 0 + assign PIPERX09DATA_in[17] = (PIPERX09DATA[17] !== 1'bz) && PIPERX09DATA_delay[17]; // rv 0 + assign PIPERX09DATA_in[18] = (PIPERX09DATA[18] !== 1'bz) && PIPERX09DATA_delay[18]; // rv 0 + assign PIPERX09DATA_in[19] = (PIPERX09DATA[19] !== 1'bz) && PIPERX09DATA_delay[19]; // rv 0 + assign PIPERX09DATA_in[1] = (PIPERX09DATA[1] !== 1'bz) && PIPERX09DATA_delay[1]; // rv 0 + assign PIPERX09DATA_in[20] = (PIPERX09DATA[20] !== 1'bz) && PIPERX09DATA_delay[20]; // rv 0 + assign PIPERX09DATA_in[21] = (PIPERX09DATA[21] !== 1'bz) && PIPERX09DATA_delay[21]; // rv 0 + assign PIPERX09DATA_in[22] = (PIPERX09DATA[22] !== 1'bz) && PIPERX09DATA_delay[22]; // rv 0 + assign PIPERX09DATA_in[23] = (PIPERX09DATA[23] !== 1'bz) && PIPERX09DATA_delay[23]; // rv 0 + assign PIPERX09DATA_in[24] = (PIPERX09DATA[24] !== 1'bz) && PIPERX09DATA_delay[24]; // rv 0 + assign PIPERX09DATA_in[25] = (PIPERX09DATA[25] !== 1'bz) && PIPERX09DATA_delay[25]; // rv 0 + assign PIPERX09DATA_in[26] = (PIPERX09DATA[26] !== 1'bz) && PIPERX09DATA_delay[26]; // rv 0 + assign PIPERX09DATA_in[27] = (PIPERX09DATA[27] !== 1'bz) && PIPERX09DATA_delay[27]; // rv 0 + assign PIPERX09DATA_in[28] = (PIPERX09DATA[28] !== 1'bz) && PIPERX09DATA_delay[28]; // rv 0 + assign PIPERX09DATA_in[29] = (PIPERX09DATA[29] !== 1'bz) && PIPERX09DATA_delay[29]; // rv 0 + assign PIPERX09DATA_in[2] = (PIPERX09DATA[2] !== 1'bz) && PIPERX09DATA_delay[2]; // rv 0 + assign PIPERX09DATA_in[30] = (PIPERX09DATA[30] !== 1'bz) && PIPERX09DATA_delay[30]; // rv 0 + assign PIPERX09DATA_in[31] = (PIPERX09DATA[31] !== 1'bz) && PIPERX09DATA_delay[31]; // rv 0 + assign PIPERX09DATA_in[3] = (PIPERX09DATA[3] !== 1'bz) && PIPERX09DATA_delay[3]; // rv 0 + assign PIPERX09DATA_in[4] = (PIPERX09DATA[4] !== 1'bz) && PIPERX09DATA_delay[4]; // rv 0 + assign PIPERX09DATA_in[5] = (PIPERX09DATA[5] !== 1'bz) && PIPERX09DATA_delay[5]; // rv 0 + assign PIPERX09DATA_in[6] = (PIPERX09DATA[6] !== 1'bz) && PIPERX09DATA_delay[6]; // rv 0 + assign PIPERX09DATA_in[7] = (PIPERX09DATA[7] !== 1'bz) && PIPERX09DATA_delay[7]; // rv 0 + assign PIPERX09DATA_in[8] = (PIPERX09DATA[8] !== 1'bz) && PIPERX09DATA_delay[8]; // rv 0 + assign PIPERX09DATA_in[9] = (PIPERX09DATA[9] !== 1'bz) && PIPERX09DATA_delay[9]; // rv 0 + assign PIPERX09ELECIDLE_in = (PIPERX09ELECIDLE === 1'bz) || PIPERX09ELECIDLE_delay; // rv 1 + assign PIPERX09EQDONE_in = (PIPERX09EQDONE !== 1'bz) && PIPERX09EQDONE_delay; // rv 0 + assign PIPERX09EQLPADAPTDONE_in = (PIPERX09EQLPADAPTDONE !== 1'bz) && PIPERX09EQLPADAPTDONE_delay; // rv 0 + assign PIPERX09EQLPLFFSSEL_in = (PIPERX09EQLPLFFSSEL !== 1'bz) && PIPERX09EQLPLFFSSEL_delay; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX09EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX09EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX09EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX09EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX09EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX09EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX09EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX09EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX09EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX09EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX09EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX09EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX09EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX09EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX09EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX09EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX09EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX09EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX09PHYSTATUS_in = (PIPERX09PHYSTATUS === 1'bz) || PIPERX09PHYSTATUS_delay; // rv 1 + assign PIPERX09STARTBLOCK_in[0] = (PIPERX09STARTBLOCK[0] !== 1'bz) && PIPERX09STARTBLOCK_delay[0]; // rv 0 + assign PIPERX09STARTBLOCK_in[1] = (PIPERX09STARTBLOCK[1] !== 1'bz) && PIPERX09STARTBLOCK_delay[1]; // rv 0 + assign PIPERX09STATUS_in[0] = (PIPERX09STATUS[0] !== 1'bz) && PIPERX09STATUS_delay[0]; // rv 0 + assign PIPERX09STATUS_in[1] = (PIPERX09STATUS[1] !== 1'bz) && PIPERX09STATUS_delay[1]; // rv 0 + assign PIPERX09STATUS_in[2] = (PIPERX09STATUS[2] !== 1'bz) && PIPERX09STATUS_delay[2]; // rv 0 + assign PIPERX09SYNCHEADER_in[0] = (PIPERX09SYNCHEADER[0] !== 1'bz) && PIPERX09SYNCHEADER_delay[0]; // rv 0 + assign PIPERX09SYNCHEADER_in[1] = (PIPERX09SYNCHEADER[1] !== 1'bz) && PIPERX09SYNCHEADER_delay[1]; // rv 0 + assign PIPERX09VALID_in = (PIPERX09VALID !== 1'bz) && PIPERX09VALID_delay; // rv 0 + assign PIPERX10CHARISK_in[0] = (PIPERX10CHARISK[0] === 1'bz) || PIPERX10CHARISK_delay[0]; // rv 1 + assign PIPERX10CHARISK_in[1] = (PIPERX10CHARISK[1] === 1'bz) || PIPERX10CHARISK_delay[1]; // rv 1 + assign PIPERX10DATAVALID_in = (PIPERX10DATAVALID !== 1'bz) && PIPERX10DATAVALID_delay; // rv 0 + assign PIPERX10DATA_in[0] = (PIPERX10DATA[0] !== 1'bz) && PIPERX10DATA_delay[0]; // rv 0 + assign PIPERX10DATA_in[10] = (PIPERX10DATA[10] !== 1'bz) && PIPERX10DATA_delay[10]; // rv 0 + assign PIPERX10DATA_in[11] = (PIPERX10DATA[11] !== 1'bz) && PIPERX10DATA_delay[11]; // rv 0 + assign PIPERX10DATA_in[12] = (PIPERX10DATA[12] !== 1'bz) && PIPERX10DATA_delay[12]; // rv 0 + assign PIPERX10DATA_in[13] = (PIPERX10DATA[13] !== 1'bz) && PIPERX10DATA_delay[13]; // rv 0 + assign PIPERX10DATA_in[14] = (PIPERX10DATA[14] !== 1'bz) && PIPERX10DATA_delay[14]; // rv 0 + assign PIPERX10DATA_in[15] = (PIPERX10DATA[15] !== 1'bz) && PIPERX10DATA_delay[15]; // rv 0 + assign PIPERX10DATA_in[16] = (PIPERX10DATA[16] !== 1'bz) && PIPERX10DATA_delay[16]; // rv 0 + assign PIPERX10DATA_in[17] = (PIPERX10DATA[17] !== 1'bz) && PIPERX10DATA_delay[17]; // rv 0 + assign PIPERX10DATA_in[18] = (PIPERX10DATA[18] !== 1'bz) && PIPERX10DATA_delay[18]; // rv 0 + assign PIPERX10DATA_in[19] = (PIPERX10DATA[19] !== 1'bz) && PIPERX10DATA_delay[19]; // rv 0 + assign PIPERX10DATA_in[1] = (PIPERX10DATA[1] !== 1'bz) && PIPERX10DATA_delay[1]; // rv 0 + assign PIPERX10DATA_in[20] = (PIPERX10DATA[20] !== 1'bz) && PIPERX10DATA_delay[20]; // rv 0 + assign PIPERX10DATA_in[21] = (PIPERX10DATA[21] !== 1'bz) && PIPERX10DATA_delay[21]; // rv 0 + assign PIPERX10DATA_in[22] = (PIPERX10DATA[22] !== 1'bz) && PIPERX10DATA_delay[22]; // rv 0 + assign PIPERX10DATA_in[23] = (PIPERX10DATA[23] !== 1'bz) && PIPERX10DATA_delay[23]; // rv 0 + assign PIPERX10DATA_in[24] = (PIPERX10DATA[24] !== 1'bz) && PIPERX10DATA_delay[24]; // rv 0 + assign PIPERX10DATA_in[25] = (PIPERX10DATA[25] !== 1'bz) && PIPERX10DATA_delay[25]; // rv 0 + assign PIPERX10DATA_in[26] = (PIPERX10DATA[26] !== 1'bz) && PIPERX10DATA_delay[26]; // rv 0 + assign PIPERX10DATA_in[27] = (PIPERX10DATA[27] !== 1'bz) && PIPERX10DATA_delay[27]; // rv 0 + assign PIPERX10DATA_in[28] = (PIPERX10DATA[28] !== 1'bz) && PIPERX10DATA_delay[28]; // rv 0 + assign PIPERX10DATA_in[29] = (PIPERX10DATA[29] !== 1'bz) && PIPERX10DATA_delay[29]; // rv 0 + assign PIPERX10DATA_in[2] = (PIPERX10DATA[2] !== 1'bz) && PIPERX10DATA_delay[2]; // rv 0 + assign PIPERX10DATA_in[30] = (PIPERX10DATA[30] !== 1'bz) && PIPERX10DATA_delay[30]; // rv 0 + assign PIPERX10DATA_in[31] = (PIPERX10DATA[31] !== 1'bz) && PIPERX10DATA_delay[31]; // rv 0 + assign PIPERX10DATA_in[3] = (PIPERX10DATA[3] !== 1'bz) && PIPERX10DATA_delay[3]; // rv 0 + assign PIPERX10DATA_in[4] = (PIPERX10DATA[4] !== 1'bz) && PIPERX10DATA_delay[4]; // rv 0 + assign PIPERX10DATA_in[5] = (PIPERX10DATA[5] !== 1'bz) && PIPERX10DATA_delay[5]; // rv 0 + assign PIPERX10DATA_in[6] = (PIPERX10DATA[6] !== 1'bz) && PIPERX10DATA_delay[6]; // rv 0 + assign PIPERX10DATA_in[7] = (PIPERX10DATA[7] !== 1'bz) && PIPERX10DATA_delay[7]; // rv 0 + assign PIPERX10DATA_in[8] = (PIPERX10DATA[8] !== 1'bz) && PIPERX10DATA_delay[8]; // rv 0 + assign PIPERX10DATA_in[9] = (PIPERX10DATA[9] !== 1'bz) && PIPERX10DATA_delay[9]; // rv 0 + assign PIPERX10ELECIDLE_in = (PIPERX10ELECIDLE === 1'bz) || PIPERX10ELECIDLE_delay; // rv 1 + assign PIPERX10EQDONE_in = (PIPERX10EQDONE !== 1'bz) && PIPERX10EQDONE_delay; // rv 0 + assign PIPERX10EQLPADAPTDONE_in = (PIPERX10EQLPADAPTDONE !== 1'bz) && PIPERX10EQLPADAPTDONE_delay; // rv 0 + assign PIPERX10EQLPLFFSSEL_in = (PIPERX10EQLPLFFSSEL !== 1'bz) && PIPERX10EQLPLFFSSEL_delay; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX10EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX10EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX10EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX10EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX10EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX10EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX10EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX10EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX10EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX10EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX10EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX10EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX10EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX10EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX10EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX10EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX10EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX10EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX10PHYSTATUS_in = (PIPERX10PHYSTATUS === 1'bz) || PIPERX10PHYSTATUS_delay; // rv 1 + assign PIPERX10STARTBLOCK_in[0] = (PIPERX10STARTBLOCK[0] !== 1'bz) && PIPERX10STARTBLOCK_delay[0]; // rv 0 + assign PIPERX10STARTBLOCK_in[1] = (PIPERX10STARTBLOCK[1] !== 1'bz) && PIPERX10STARTBLOCK_delay[1]; // rv 0 + assign PIPERX10STATUS_in[0] = (PIPERX10STATUS[0] !== 1'bz) && PIPERX10STATUS_delay[0]; // rv 0 + assign PIPERX10STATUS_in[1] = (PIPERX10STATUS[1] !== 1'bz) && PIPERX10STATUS_delay[1]; // rv 0 + assign PIPERX10STATUS_in[2] = (PIPERX10STATUS[2] !== 1'bz) && PIPERX10STATUS_delay[2]; // rv 0 + assign PIPERX10SYNCHEADER_in[0] = (PIPERX10SYNCHEADER[0] !== 1'bz) && PIPERX10SYNCHEADER_delay[0]; // rv 0 + assign PIPERX10SYNCHEADER_in[1] = (PIPERX10SYNCHEADER[1] !== 1'bz) && PIPERX10SYNCHEADER_delay[1]; // rv 0 + assign PIPERX10VALID_in = (PIPERX10VALID !== 1'bz) && PIPERX10VALID_delay; // rv 0 + assign PIPERX11CHARISK_in[0] = (PIPERX11CHARISK[0] === 1'bz) || PIPERX11CHARISK_delay[0]; // rv 1 + assign PIPERX11CHARISK_in[1] = (PIPERX11CHARISK[1] === 1'bz) || PIPERX11CHARISK_delay[1]; // rv 1 + assign PIPERX11DATAVALID_in = (PIPERX11DATAVALID !== 1'bz) && PIPERX11DATAVALID_delay; // rv 0 + assign PIPERX11DATA_in[0] = (PIPERX11DATA[0] !== 1'bz) && PIPERX11DATA_delay[0]; // rv 0 + assign PIPERX11DATA_in[10] = (PIPERX11DATA[10] !== 1'bz) && PIPERX11DATA_delay[10]; // rv 0 + assign PIPERX11DATA_in[11] = (PIPERX11DATA[11] !== 1'bz) && PIPERX11DATA_delay[11]; // rv 0 + assign PIPERX11DATA_in[12] = (PIPERX11DATA[12] !== 1'bz) && PIPERX11DATA_delay[12]; // rv 0 + assign PIPERX11DATA_in[13] = (PIPERX11DATA[13] !== 1'bz) && PIPERX11DATA_delay[13]; // rv 0 + assign PIPERX11DATA_in[14] = (PIPERX11DATA[14] !== 1'bz) && PIPERX11DATA_delay[14]; // rv 0 + assign PIPERX11DATA_in[15] = (PIPERX11DATA[15] !== 1'bz) && PIPERX11DATA_delay[15]; // rv 0 + assign PIPERX11DATA_in[16] = (PIPERX11DATA[16] !== 1'bz) && PIPERX11DATA_delay[16]; // rv 0 + assign PIPERX11DATA_in[17] = (PIPERX11DATA[17] !== 1'bz) && PIPERX11DATA_delay[17]; // rv 0 + assign PIPERX11DATA_in[18] = (PIPERX11DATA[18] !== 1'bz) && PIPERX11DATA_delay[18]; // rv 0 + assign PIPERX11DATA_in[19] = (PIPERX11DATA[19] !== 1'bz) && PIPERX11DATA_delay[19]; // rv 0 + assign PIPERX11DATA_in[1] = (PIPERX11DATA[1] !== 1'bz) && PIPERX11DATA_delay[1]; // rv 0 + assign PIPERX11DATA_in[20] = (PIPERX11DATA[20] !== 1'bz) && PIPERX11DATA_delay[20]; // rv 0 + assign PIPERX11DATA_in[21] = (PIPERX11DATA[21] !== 1'bz) && PIPERX11DATA_delay[21]; // rv 0 + assign PIPERX11DATA_in[22] = (PIPERX11DATA[22] !== 1'bz) && PIPERX11DATA_delay[22]; // rv 0 + assign PIPERX11DATA_in[23] = (PIPERX11DATA[23] !== 1'bz) && PIPERX11DATA_delay[23]; // rv 0 + assign PIPERX11DATA_in[24] = (PIPERX11DATA[24] !== 1'bz) && PIPERX11DATA_delay[24]; // rv 0 + assign PIPERX11DATA_in[25] = (PIPERX11DATA[25] !== 1'bz) && PIPERX11DATA_delay[25]; // rv 0 + assign PIPERX11DATA_in[26] = (PIPERX11DATA[26] !== 1'bz) && PIPERX11DATA_delay[26]; // rv 0 + assign PIPERX11DATA_in[27] = (PIPERX11DATA[27] !== 1'bz) && PIPERX11DATA_delay[27]; // rv 0 + assign PIPERX11DATA_in[28] = (PIPERX11DATA[28] !== 1'bz) && PIPERX11DATA_delay[28]; // rv 0 + assign PIPERX11DATA_in[29] = (PIPERX11DATA[29] !== 1'bz) && PIPERX11DATA_delay[29]; // rv 0 + assign PIPERX11DATA_in[2] = (PIPERX11DATA[2] !== 1'bz) && PIPERX11DATA_delay[2]; // rv 0 + assign PIPERX11DATA_in[30] = (PIPERX11DATA[30] !== 1'bz) && PIPERX11DATA_delay[30]; // rv 0 + assign PIPERX11DATA_in[31] = (PIPERX11DATA[31] !== 1'bz) && PIPERX11DATA_delay[31]; // rv 0 + assign PIPERX11DATA_in[3] = (PIPERX11DATA[3] !== 1'bz) && PIPERX11DATA_delay[3]; // rv 0 + assign PIPERX11DATA_in[4] = (PIPERX11DATA[4] !== 1'bz) && PIPERX11DATA_delay[4]; // rv 0 + assign PIPERX11DATA_in[5] = (PIPERX11DATA[5] !== 1'bz) && PIPERX11DATA_delay[5]; // rv 0 + assign PIPERX11DATA_in[6] = (PIPERX11DATA[6] !== 1'bz) && PIPERX11DATA_delay[6]; // rv 0 + assign PIPERX11DATA_in[7] = (PIPERX11DATA[7] !== 1'bz) && PIPERX11DATA_delay[7]; // rv 0 + assign PIPERX11DATA_in[8] = (PIPERX11DATA[8] !== 1'bz) && PIPERX11DATA_delay[8]; // rv 0 + assign PIPERX11DATA_in[9] = (PIPERX11DATA[9] !== 1'bz) && PIPERX11DATA_delay[9]; // rv 0 + assign PIPERX11ELECIDLE_in = (PIPERX11ELECIDLE === 1'bz) || PIPERX11ELECIDLE_delay; // rv 1 + assign PIPERX11EQDONE_in = (PIPERX11EQDONE !== 1'bz) && PIPERX11EQDONE_delay; // rv 0 + assign PIPERX11EQLPADAPTDONE_in = (PIPERX11EQLPADAPTDONE !== 1'bz) && PIPERX11EQLPADAPTDONE_delay; // rv 0 + assign PIPERX11EQLPLFFSSEL_in = (PIPERX11EQLPLFFSSEL !== 1'bz) && PIPERX11EQLPLFFSSEL_delay; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX11EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX11EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX11EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX11EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX11EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX11EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX11EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX11EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX11EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX11EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX11EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX11EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX11EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX11EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX11EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX11EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX11EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX11EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX11PHYSTATUS_in = (PIPERX11PHYSTATUS === 1'bz) || PIPERX11PHYSTATUS_delay; // rv 1 + assign PIPERX11STARTBLOCK_in[0] = (PIPERX11STARTBLOCK[0] !== 1'bz) && PIPERX11STARTBLOCK_delay[0]; // rv 0 + assign PIPERX11STARTBLOCK_in[1] = (PIPERX11STARTBLOCK[1] !== 1'bz) && PIPERX11STARTBLOCK_delay[1]; // rv 0 + assign PIPERX11STATUS_in[0] = (PIPERX11STATUS[0] !== 1'bz) && PIPERX11STATUS_delay[0]; // rv 0 + assign PIPERX11STATUS_in[1] = (PIPERX11STATUS[1] !== 1'bz) && PIPERX11STATUS_delay[1]; // rv 0 + assign PIPERX11STATUS_in[2] = (PIPERX11STATUS[2] !== 1'bz) && PIPERX11STATUS_delay[2]; // rv 0 + assign PIPERX11SYNCHEADER_in[0] = (PIPERX11SYNCHEADER[0] !== 1'bz) && PIPERX11SYNCHEADER_delay[0]; // rv 0 + assign PIPERX11SYNCHEADER_in[1] = (PIPERX11SYNCHEADER[1] !== 1'bz) && PIPERX11SYNCHEADER_delay[1]; // rv 0 + assign PIPERX11VALID_in = (PIPERX11VALID !== 1'bz) && PIPERX11VALID_delay; // rv 0 + assign PIPERX12CHARISK_in[0] = (PIPERX12CHARISK[0] === 1'bz) || PIPERX12CHARISK_delay[0]; // rv 1 + assign PIPERX12CHARISK_in[1] = (PIPERX12CHARISK[1] === 1'bz) || PIPERX12CHARISK_delay[1]; // rv 1 + assign PIPERX12DATAVALID_in = (PIPERX12DATAVALID !== 1'bz) && PIPERX12DATAVALID_delay; // rv 0 + assign PIPERX12DATA_in[0] = (PIPERX12DATA[0] !== 1'bz) && PIPERX12DATA_delay[0]; // rv 0 + assign PIPERX12DATA_in[10] = (PIPERX12DATA[10] !== 1'bz) && PIPERX12DATA_delay[10]; // rv 0 + assign PIPERX12DATA_in[11] = (PIPERX12DATA[11] !== 1'bz) && PIPERX12DATA_delay[11]; // rv 0 + assign PIPERX12DATA_in[12] = (PIPERX12DATA[12] !== 1'bz) && PIPERX12DATA_delay[12]; // rv 0 + assign PIPERX12DATA_in[13] = (PIPERX12DATA[13] !== 1'bz) && PIPERX12DATA_delay[13]; // rv 0 + assign PIPERX12DATA_in[14] = (PIPERX12DATA[14] !== 1'bz) && PIPERX12DATA_delay[14]; // rv 0 + assign PIPERX12DATA_in[15] = (PIPERX12DATA[15] !== 1'bz) && PIPERX12DATA_delay[15]; // rv 0 + assign PIPERX12DATA_in[16] = (PIPERX12DATA[16] !== 1'bz) && PIPERX12DATA_delay[16]; // rv 0 + assign PIPERX12DATA_in[17] = (PIPERX12DATA[17] !== 1'bz) && PIPERX12DATA_delay[17]; // rv 0 + assign PIPERX12DATA_in[18] = (PIPERX12DATA[18] !== 1'bz) && PIPERX12DATA_delay[18]; // rv 0 + assign PIPERX12DATA_in[19] = (PIPERX12DATA[19] !== 1'bz) && PIPERX12DATA_delay[19]; // rv 0 + assign PIPERX12DATA_in[1] = (PIPERX12DATA[1] !== 1'bz) && PIPERX12DATA_delay[1]; // rv 0 + assign PIPERX12DATA_in[20] = (PIPERX12DATA[20] !== 1'bz) && PIPERX12DATA_delay[20]; // rv 0 + assign PIPERX12DATA_in[21] = (PIPERX12DATA[21] !== 1'bz) && PIPERX12DATA_delay[21]; // rv 0 + assign PIPERX12DATA_in[22] = (PIPERX12DATA[22] !== 1'bz) && PIPERX12DATA_delay[22]; // rv 0 + assign PIPERX12DATA_in[23] = (PIPERX12DATA[23] !== 1'bz) && PIPERX12DATA_delay[23]; // rv 0 + assign PIPERX12DATA_in[24] = (PIPERX12DATA[24] !== 1'bz) && PIPERX12DATA_delay[24]; // rv 0 + assign PIPERX12DATA_in[25] = (PIPERX12DATA[25] !== 1'bz) && PIPERX12DATA_delay[25]; // rv 0 + assign PIPERX12DATA_in[26] = (PIPERX12DATA[26] !== 1'bz) && PIPERX12DATA_delay[26]; // rv 0 + assign PIPERX12DATA_in[27] = (PIPERX12DATA[27] !== 1'bz) && PIPERX12DATA_delay[27]; // rv 0 + assign PIPERX12DATA_in[28] = (PIPERX12DATA[28] !== 1'bz) && PIPERX12DATA_delay[28]; // rv 0 + assign PIPERX12DATA_in[29] = (PIPERX12DATA[29] !== 1'bz) && PIPERX12DATA_delay[29]; // rv 0 + assign PIPERX12DATA_in[2] = (PIPERX12DATA[2] !== 1'bz) && PIPERX12DATA_delay[2]; // rv 0 + assign PIPERX12DATA_in[30] = (PIPERX12DATA[30] !== 1'bz) && PIPERX12DATA_delay[30]; // rv 0 + assign PIPERX12DATA_in[31] = (PIPERX12DATA[31] !== 1'bz) && PIPERX12DATA_delay[31]; // rv 0 + assign PIPERX12DATA_in[3] = (PIPERX12DATA[3] !== 1'bz) && PIPERX12DATA_delay[3]; // rv 0 + assign PIPERX12DATA_in[4] = (PIPERX12DATA[4] !== 1'bz) && PIPERX12DATA_delay[4]; // rv 0 + assign PIPERX12DATA_in[5] = (PIPERX12DATA[5] !== 1'bz) && PIPERX12DATA_delay[5]; // rv 0 + assign PIPERX12DATA_in[6] = (PIPERX12DATA[6] !== 1'bz) && PIPERX12DATA_delay[6]; // rv 0 + assign PIPERX12DATA_in[7] = (PIPERX12DATA[7] !== 1'bz) && PIPERX12DATA_delay[7]; // rv 0 + assign PIPERX12DATA_in[8] = (PIPERX12DATA[8] !== 1'bz) && PIPERX12DATA_delay[8]; // rv 0 + assign PIPERX12DATA_in[9] = (PIPERX12DATA[9] !== 1'bz) && PIPERX12DATA_delay[9]; // rv 0 + assign PIPERX12ELECIDLE_in = (PIPERX12ELECIDLE === 1'bz) || PIPERX12ELECIDLE_delay; // rv 1 + assign PIPERX12EQDONE_in = (PIPERX12EQDONE !== 1'bz) && PIPERX12EQDONE_delay; // rv 0 + assign PIPERX12EQLPADAPTDONE_in = (PIPERX12EQLPADAPTDONE !== 1'bz) && PIPERX12EQLPADAPTDONE_delay; // rv 0 + assign PIPERX12EQLPLFFSSEL_in = (PIPERX12EQLPLFFSSEL !== 1'bz) && PIPERX12EQLPLFFSSEL_delay; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX12EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX12EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX12EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX12EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX12EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX12EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX12EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX12EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX12EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX12EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX12EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX12EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX12EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX12EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX12EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX12EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX12EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX12EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX12PHYSTATUS_in = (PIPERX12PHYSTATUS === 1'bz) || PIPERX12PHYSTATUS_delay; // rv 1 + assign PIPERX12STARTBLOCK_in[0] = (PIPERX12STARTBLOCK[0] !== 1'bz) && PIPERX12STARTBLOCK_delay[0]; // rv 0 + assign PIPERX12STARTBLOCK_in[1] = (PIPERX12STARTBLOCK[1] !== 1'bz) && PIPERX12STARTBLOCK_delay[1]; // rv 0 + assign PIPERX12STATUS_in[0] = (PIPERX12STATUS[0] !== 1'bz) && PIPERX12STATUS_delay[0]; // rv 0 + assign PIPERX12STATUS_in[1] = (PIPERX12STATUS[1] !== 1'bz) && PIPERX12STATUS_delay[1]; // rv 0 + assign PIPERX12STATUS_in[2] = (PIPERX12STATUS[2] !== 1'bz) && PIPERX12STATUS_delay[2]; // rv 0 + assign PIPERX12SYNCHEADER_in[0] = (PIPERX12SYNCHEADER[0] !== 1'bz) && PIPERX12SYNCHEADER_delay[0]; // rv 0 + assign PIPERX12SYNCHEADER_in[1] = (PIPERX12SYNCHEADER[1] !== 1'bz) && PIPERX12SYNCHEADER_delay[1]; // rv 0 + assign PIPERX12VALID_in = (PIPERX12VALID !== 1'bz) && PIPERX12VALID_delay; // rv 0 + assign PIPERX13CHARISK_in[0] = (PIPERX13CHARISK[0] === 1'bz) || PIPERX13CHARISK_delay[0]; // rv 1 + assign PIPERX13CHARISK_in[1] = (PIPERX13CHARISK[1] === 1'bz) || PIPERX13CHARISK_delay[1]; // rv 1 + assign PIPERX13DATAVALID_in = (PIPERX13DATAVALID !== 1'bz) && PIPERX13DATAVALID_delay; // rv 0 + assign PIPERX13DATA_in[0] = (PIPERX13DATA[0] !== 1'bz) && PIPERX13DATA_delay[0]; // rv 0 + assign PIPERX13DATA_in[10] = (PIPERX13DATA[10] !== 1'bz) && PIPERX13DATA_delay[10]; // rv 0 + assign PIPERX13DATA_in[11] = (PIPERX13DATA[11] !== 1'bz) && PIPERX13DATA_delay[11]; // rv 0 + assign PIPERX13DATA_in[12] = (PIPERX13DATA[12] !== 1'bz) && PIPERX13DATA_delay[12]; // rv 0 + assign PIPERX13DATA_in[13] = (PIPERX13DATA[13] !== 1'bz) && PIPERX13DATA_delay[13]; // rv 0 + assign PIPERX13DATA_in[14] = (PIPERX13DATA[14] !== 1'bz) && PIPERX13DATA_delay[14]; // rv 0 + assign PIPERX13DATA_in[15] = (PIPERX13DATA[15] !== 1'bz) && PIPERX13DATA_delay[15]; // rv 0 + assign PIPERX13DATA_in[16] = (PIPERX13DATA[16] !== 1'bz) && PIPERX13DATA_delay[16]; // rv 0 + assign PIPERX13DATA_in[17] = (PIPERX13DATA[17] !== 1'bz) && PIPERX13DATA_delay[17]; // rv 0 + assign PIPERX13DATA_in[18] = (PIPERX13DATA[18] !== 1'bz) && PIPERX13DATA_delay[18]; // rv 0 + assign PIPERX13DATA_in[19] = (PIPERX13DATA[19] !== 1'bz) && PIPERX13DATA_delay[19]; // rv 0 + assign PIPERX13DATA_in[1] = (PIPERX13DATA[1] !== 1'bz) && PIPERX13DATA_delay[1]; // rv 0 + assign PIPERX13DATA_in[20] = (PIPERX13DATA[20] !== 1'bz) && PIPERX13DATA_delay[20]; // rv 0 + assign PIPERX13DATA_in[21] = (PIPERX13DATA[21] !== 1'bz) && PIPERX13DATA_delay[21]; // rv 0 + assign PIPERX13DATA_in[22] = (PIPERX13DATA[22] !== 1'bz) && PIPERX13DATA_delay[22]; // rv 0 + assign PIPERX13DATA_in[23] = (PIPERX13DATA[23] !== 1'bz) && PIPERX13DATA_delay[23]; // rv 0 + assign PIPERX13DATA_in[24] = (PIPERX13DATA[24] !== 1'bz) && PIPERX13DATA_delay[24]; // rv 0 + assign PIPERX13DATA_in[25] = (PIPERX13DATA[25] !== 1'bz) && PIPERX13DATA_delay[25]; // rv 0 + assign PIPERX13DATA_in[26] = (PIPERX13DATA[26] !== 1'bz) && PIPERX13DATA_delay[26]; // rv 0 + assign PIPERX13DATA_in[27] = (PIPERX13DATA[27] !== 1'bz) && PIPERX13DATA_delay[27]; // rv 0 + assign PIPERX13DATA_in[28] = (PIPERX13DATA[28] !== 1'bz) && PIPERX13DATA_delay[28]; // rv 0 + assign PIPERX13DATA_in[29] = (PIPERX13DATA[29] !== 1'bz) && PIPERX13DATA_delay[29]; // rv 0 + assign PIPERX13DATA_in[2] = (PIPERX13DATA[2] !== 1'bz) && PIPERX13DATA_delay[2]; // rv 0 + assign PIPERX13DATA_in[30] = (PIPERX13DATA[30] !== 1'bz) && PIPERX13DATA_delay[30]; // rv 0 + assign PIPERX13DATA_in[31] = (PIPERX13DATA[31] !== 1'bz) && PIPERX13DATA_delay[31]; // rv 0 + assign PIPERX13DATA_in[3] = (PIPERX13DATA[3] !== 1'bz) && PIPERX13DATA_delay[3]; // rv 0 + assign PIPERX13DATA_in[4] = (PIPERX13DATA[4] !== 1'bz) && PIPERX13DATA_delay[4]; // rv 0 + assign PIPERX13DATA_in[5] = (PIPERX13DATA[5] !== 1'bz) && PIPERX13DATA_delay[5]; // rv 0 + assign PIPERX13DATA_in[6] = (PIPERX13DATA[6] !== 1'bz) && PIPERX13DATA_delay[6]; // rv 0 + assign PIPERX13DATA_in[7] = (PIPERX13DATA[7] !== 1'bz) && PIPERX13DATA_delay[7]; // rv 0 + assign PIPERX13DATA_in[8] = (PIPERX13DATA[8] !== 1'bz) && PIPERX13DATA_delay[8]; // rv 0 + assign PIPERX13DATA_in[9] = (PIPERX13DATA[9] !== 1'bz) && PIPERX13DATA_delay[9]; // rv 0 + assign PIPERX13ELECIDLE_in = (PIPERX13ELECIDLE === 1'bz) || PIPERX13ELECIDLE_delay; // rv 1 + assign PIPERX13EQDONE_in = (PIPERX13EQDONE !== 1'bz) && PIPERX13EQDONE_delay; // rv 0 + assign PIPERX13EQLPADAPTDONE_in = (PIPERX13EQLPADAPTDONE !== 1'bz) && PIPERX13EQLPADAPTDONE_delay; // rv 0 + assign PIPERX13EQLPLFFSSEL_in = (PIPERX13EQLPLFFSSEL !== 1'bz) && PIPERX13EQLPLFFSSEL_delay; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX13EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX13EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX13EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX13EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX13EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX13EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX13EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX13EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX13EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX13EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX13EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX13EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX13EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX13EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX13EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX13EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX13EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX13EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX13PHYSTATUS_in = (PIPERX13PHYSTATUS === 1'bz) || PIPERX13PHYSTATUS_delay; // rv 1 + assign PIPERX13STARTBLOCK_in[0] = (PIPERX13STARTBLOCK[0] !== 1'bz) && PIPERX13STARTBLOCK_delay[0]; // rv 0 + assign PIPERX13STARTBLOCK_in[1] = (PIPERX13STARTBLOCK[1] !== 1'bz) && PIPERX13STARTBLOCK_delay[1]; // rv 0 + assign PIPERX13STATUS_in[0] = (PIPERX13STATUS[0] !== 1'bz) && PIPERX13STATUS_delay[0]; // rv 0 + assign PIPERX13STATUS_in[1] = (PIPERX13STATUS[1] !== 1'bz) && PIPERX13STATUS_delay[1]; // rv 0 + assign PIPERX13STATUS_in[2] = (PIPERX13STATUS[2] !== 1'bz) && PIPERX13STATUS_delay[2]; // rv 0 + assign PIPERX13SYNCHEADER_in[0] = (PIPERX13SYNCHEADER[0] !== 1'bz) && PIPERX13SYNCHEADER_delay[0]; // rv 0 + assign PIPERX13SYNCHEADER_in[1] = (PIPERX13SYNCHEADER[1] !== 1'bz) && PIPERX13SYNCHEADER_delay[1]; // rv 0 + assign PIPERX13VALID_in = (PIPERX13VALID !== 1'bz) && PIPERX13VALID_delay; // rv 0 + assign PIPERX14CHARISK_in[0] = (PIPERX14CHARISK[0] === 1'bz) || PIPERX14CHARISK_delay[0]; // rv 1 + assign PIPERX14CHARISK_in[1] = (PIPERX14CHARISK[1] === 1'bz) || PIPERX14CHARISK_delay[1]; // rv 1 + assign PIPERX14DATAVALID_in = (PIPERX14DATAVALID !== 1'bz) && PIPERX14DATAVALID_delay; // rv 0 + assign PIPERX14DATA_in[0] = (PIPERX14DATA[0] !== 1'bz) && PIPERX14DATA_delay[0]; // rv 0 + assign PIPERX14DATA_in[10] = (PIPERX14DATA[10] !== 1'bz) && PIPERX14DATA_delay[10]; // rv 0 + assign PIPERX14DATA_in[11] = (PIPERX14DATA[11] !== 1'bz) && PIPERX14DATA_delay[11]; // rv 0 + assign PIPERX14DATA_in[12] = (PIPERX14DATA[12] !== 1'bz) && PIPERX14DATA_delay[12]; // rv 0 + assign PIPERX14DATA_in[13] = (PIPERX14DATA[13] !== 1'bz) && PIPERX14DATA_delay[13]; // rv 0 + assign PIPERX14DATA_in[14] = (PIPERX14DATA[14] !== 1'bz) && PIPERX14DATA_delay[14]; // rv 0 + assign PIPERX14DATA_in[15] = (PIPERX14DATA[15] !== 1'bz) && PIPERX14DATA_delay[15]; // rv 0 + assign PIPERX14DATA_in[16] = (PIPERX14DATA[16] !== 1'bz) && PIPERX14DATA_delay[16]; // rv 0 + assign PIPERX14DATA_in[17] = (PIPERX14DATA[17] !== 1'bz) && PIPERX14DATA_delay[17]; // rv 0 + assign PIPERX14DATA_in[18] = (PIPERX14DATA[18] !== 1'bz) && PIPERX14DATA_delay[18]; // rv 0 + assign PIPERX14DATA_in[19] = (PIPERX14DATA[19] !== 1'bz) && PIPERX14DATA_delay[19]; // rv 0 + assign PIPERX14DATA_in[1] = (PIPERX14DATA[1] !== 1'bz) && PIPERX14DATA_delay[1]; // rv 0 + assign PIPERX14DATA_in[20] = (PIPERX14DATA[20] !== 1'bz) && PIPERX14DATA_delay[20]; // rv 0 + assign PIPERX14DATA_in[21] = (PIPERX14DATA[21] !== 1'bz) && PIPERX14DATA_delay[21]; // rv 0 + assign PIPERX14DATA_in[22] = (PIPERX14DATA[22] !== 1'bz) && PIPERX14DATA_delay[22]; // rv 0 + assign PIPERX14DATA_in[23] = (PIPERX14DATA[23] !== 1'bz) && PIPERX14DATA_delay[23]; // rv 0 + assign PIPERX14DATA_in[24] = (PIPERX14DATA[24] !== 1'bz) && PIPERX14DATA_delay[24]; // rv 0 + assign PIPERX14DATA_in[25] = (PIPERX14DATA[25] !== 1'bz) && PIPERX14DATA_delay[25]; // rv 0 + assign PIPERX14DATA_in[26] = (PIPERX14DATA[26] !== 1'bz) && PIPERX14DATA_delay[26]; // rv 0 + assign PIPERX14DATA_in[27] = (PIPERX14DATA[27] !== 1'bz) && PIPERX14DATA_delay[27]; // rv 0 + assign PIPERX14DATA_in[28] = (PIPERX14DATA[28] !== 1'bz) && PIPERX14DATA_delay[28]; // rv 0 + assign PIPERX14DATA_in[29] = (PIPERX14DATA[29] !== 1'bz) && PIPERX14DATA_delay[29]; // rv 0 + assign PIPERX14DATA_in[2] = (PIPERX14DATA[2] !== 1'bz) && PIPERX14DATA_delay[2]; // rv 0 + assign PIPERX14DATA_in[30] = (PIPERX14DATA[30] !== 1'bz) && PIPERX14DATA_delay[30]; // rv 0 + assign PIPERX14DATA_in[31] = (PIPERX14DATA[31] !== 1'bz) && PIPERX14DATA_delay[31]; // rv 0 + assign PIPERX14DATA_in[3] = (PIPERX14DATA[3] !== 1'bz) && PIPERX14DATA_delay[3]; // rv 0 + assign PIPERX14DATA_in[4] = (PIPERX14DATA[4] !== 1'bz) && PIPERX14DATA_delay[4]; // rv 0 + assign PIPERX14DATA_in[5] = (PIPERX14DATA[5] !== 1'bz) && PIPERX14DATA_delay[5]; // rv 0 + assign PIPERX14DATA_in[6] = (PIPERX14DATA[6] !== 1'bz) && PIPERX14DATA_delay[6]; // rv 0 + assign PIPERX14DATA_in[7] = (PIPERX14DATA[7] !== 1'bz) && PIPERX14DATA_delay[7]; // rv 0 + assign PIPERX14DATA_in[8] = (PIPERX14DATA[8] !== 1'bz) && PIPERX14DATA_delay[8]; // rv 0 + assign PIPERX14DATA_in[9] = (PIPERX14DATA[9] !== 1'bz) && PIPERX14DATA_delay[9]; // rv 0 + assign PIPERX14ELECIDLE_in = (PIPERX14ELECIDLE === 1'bz) || PIPERX14ELECIDLE_delay; // rv 1 + assign PIPERX14EQDONE_in = (PIPERX14EQDONE !== 1'bz) && PIPERX14EQDONE_delay; // rv 0 + assign PIPERX14EQLPADAPTDONE_in = (PIPERX14EQLPADAPTDONE !== 1'bz) && PIPERX14EQLPADAPTDONE_delay; // rv 0 + assign PIPERX14EQLPLFFSSEL_in = (PIPERX14EQLPLFFSSEL !== 1'bz) && PIPERX14EQLPLFFSSEL_delay; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX14EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX14EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX14EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX14EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX14EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX14EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX14EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX14EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX14EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX14EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX14EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX14EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX14EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX14EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX14EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX14EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX14EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX14EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX14PHYSTATUS_in = (PIPERX14PHYSTATUS === 1'bz) || PIPERX14PHYSTATUS_delay; // rv 1 + assign PIPERX14STARTBLOCK_in[0] = (PIPERX14STARTBLOCK[0] !== 1'bz) && PIPERX14STARTBLOCK_delay[0]; // rv 0 + assign PIPERX14STARTBLOCK_in[1] = (PIPERX14STARTBLOCK[1] !== 1'bz) && PIPERX14STARTBLOCK_delay[1]; // rv 0 + assign PIPERX14STATUS_in[0] = (PIPERX14STATUS[0] !== 1'bz) && PIPERX14STATUS_delay[0]; // rv 0 + assign PIPERX14STATUS_in[1] = (PIPERX14STATUS[1] !== 1'bz) && PIPERX14STATUS_delay[1]; // rv 0 + assign PIPERX14STATUS_in[2] = (PIPERX14STATUS[2] !== 1'bz) && PIPERX14STATUS_delay[2]; // rv 0 + assign PIPERX14SYNCHEADER_in[0] = (PIPERX14SYNCHEADER[0] !== 1'bz) && PIPERX14SYNCHEADER_delay[0]; // rv 0 + assign PIPERX14SYNCHEADER_in[1] = (PIPERX14SYNCHEADER[1] !== 1'bz) && PIPERX14SYNCHEADER_delay[1]; // rv 0 + assign PIPERX14VALID_in = (PIPERX14VALID !== 1'bz) && PIPERX14VALID_delay; // rv 0 + assign PIPERX15CHARISK_in[0] = (PIPERX15CHARISK[0] === 1'bz) || PIPERX15CHARISK_delay[0]; // rv 1 + assign PIPERX15CHARISK_in[1] = (PIPERX15CHARISK[1] === 1'bz) || PIPERX15CHARISK_delay[1]; // rv 1 + assign PIPERX15DATAVALID_in = (PIPERX15DATAVALID !== 1'bz) && PIPERX15DATAVALID_delay; // rv 0 + assign PIPERX15DATA_in[0] = (PIPERX15DATA[0] !== 1'bz) && PIPERX15DATA_delay[0]; // rv 0 + assign PIPERX15DATA_in[10] = (PIPERX15DATA[10] !== 1'bz) && PIPERX15DATA_delay[10]; // rv 0 + assign PIPERX15DATA_in[11] = (PIPERX15DATA[11] !== 1'bz) && PIPERX15DATA_delay[11]; // rv 0 + assign PIPERX15DATA_in[12] = (PIPERX15DATA[12] !== 1'bz) && PIPERX15DATA_delay[12]; // rv 0 + assign PIPERX15DATA_in[13] = (PIPERX15DATA[13] !== 1'bz) && PIPERX15DATA_delay[13]; // rv 0 + assign PIPERX15DATA_in[14] = (PIPERX15DATA[14] !== 1'bz) && PIPERX15DATA_delay[14]; // rv 0 + assign PIPERX15DATA_in[15] = (PIPERX15DATA[15] !== 1'bz) && PIPERX15DATA_delay[15]; // rv 0 + assign PIPERX15DATA_in[16] = (PIPERX15DATA[16] !== 1'bz) && PIPERX15DATA_delay[16]; // rv 0 + assign PIPERX15DATA_in[17] = (PIPERX15DATA[17] !== 1'bz) && PIPERX15DATA_delay[17]; // rv 0 + assign PIPERX15DATA_in[18] = (PIPERX15DATA[18] !== 1'bz) && PIPERX15DATA_delay[18]; // rv 0 + assign PIPERX15DATA_in[19] = (PIPERX15DATA[19] !== 1'bz) && PIPERX15DATA_delay[19]; // rv 0 + assign PIPERX15DATA_in[1] = (PIPERX15DATA[1] !== 1'bz) && PIPERX15DATA_delay[1]; // rv 0 + assign PIPERX15DATA_in[20] = (PIPERX15DATA[20] !== 1'bz) && PIPERX15DATA_delay[20]; // rv 0 + assign PIPERX15DATA_in[21] = (PIPERX15DATA[21] !== 1'bz) && PIPERX15DATA_delay[21]; // rv 0 + assign PIPERX15DATA_in[22] = (PIPERX15DATA[22] !== 1'bz) && PIPERX15DATA_delay[22]; // rv 0 + assign PIPERX15DATA_in[23] = (PIPERX15DATA[23] !== 1'bz) && PIPERX15DATA_delay[23]; // rv 0 + assign PIPERX15DATA_in[24] = (PIPERX15DATA[24] !== 1'bz) && PIPERX15DATA_delay[24]; // rv 0 + assign PIPERX15DATA_in[25] = (PIPERX15DATA[25] !== 1'bz) && PIPERX15DATA_delay[25]; // rv 0 + assign PIPERX15DATA_in[26] = (PIPERX15DATA[26] !== 1'bz) && PIPERX15DATA_delay[26]; // rv 0 + assign PIPERX15DATA_in[27] = (PIPERX15DATA[27] !== 1'bz) && PIPERX15DATA_delay[27]; // rv 0 + assign PIPERX15DATA_in[28] = (PIPERX15DATA[28] !== 1'bz) && PIPERX15DATA_delay[28]; // rv 0 + assign PIPERX15DATA_in[29] = (PIPERX15DATA[29] !== 1'bz) && PIPERX15DATA_delay[29]; // rv 0 + assign PIPERX15DATA_in[2] = (PIPERX15DATA[2] !== 1'bz) && PIPERX15DATA_delay[2]; // rv 0 + assign PIPERX15DATA_in[30] = (PIPERX15DATA[30] !== 1'bz) && PIPERX15DATA_delay[30]; // rv 0 + assign PIPERX15DATA_in[31] = (PIPERX15DATA[31] !== 1'bz) && PIPERX15DATA_delay[31]; // rv 0 + assign PIPERX15DATA_in[3] = (PIPERX15DATA[3] !== 1'bz) && PIPERX15DATA_delay[3]; // rv 0 + assign PIPERX15DATA_in[4] = (PIPERX15DATA[4] !== 1'bz) && PIPERX15DATA_delay[4]; // rv 0 + assign PIPERX15DATA_in[5] = (PIPERX15DATA[5] !== 1'bz) && PIPERX15DATA_delay[5]; // rv 0 + assign PIPERX15DATA_in[6] = (PIPERX15DATA[6] !== 1'bz) && PIPERX15DATA_delay[6]; // rv 0 + assign PIPERX15DATA_in[7] = (PIPERX15DATA[7] !== 1'bz) && PIPERX15DATA_delay[7]; // rv 0 + assign PIPERX15DATA_in[8] = (PIPERX15DATA[8] !== 1'bz) && PIPERX15DATA_delay[8]; // rv 0 + assign PIPERX15DATA_in[9] = (PIPERX15DATA[9] !== 1'bz) && PIPERX15DATA_delay[9]; // rv 0 + assign PIPERX15ELECIDLE_in = (PIPERX15ELECIDLE === 1'bz) || PIPERX15ELECIDLE_delay; // rv 1 + assign PIPERX15EQDONE_in = (PIPERX15EQDONE !== 1'bz) && PIPERX15EQDONE_delay; // rv 0 + assign PIPERX15EQLPADAPTDONE_in = (PIPERX15EQLPADAPTDONE !== 1'bz) && PIPERX15EQLPADAPTDONE_delay; // rv 0 + assign PIPERX15EQLPLFFSSEL_in = (PIPERX15EQLPLFFSSEL !== 1'bz) && PIPERX15EQLPLFFSSEL_delay; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX15EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX15EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX15EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX15EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX15EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX15EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX15EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX15EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX15EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX15EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX15EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX15EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX15EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX15EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX15EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX15EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX15EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX15EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX15PHYSTATUS_in = (PIPERX15PHYSTATUS === 1'bz) || PIPERX15PHYSTATUS_delay; // rv 1 + assign PIPERX15STARTBLOCK_in[0] = (PIPERX15STARTBLOCK[0] !== 1'bz) && PIPERX15STARTBLOCK_delay[0]; // rv 0 + assign PIPERX15STARTBLOCK_in[1] = (PIPERX15STARTBLOCK[1] !== 1'bz) && PIPERX15STARTBLOCK_delay[1]; // rv 0 + assign PIPERX15STATUS_in[0] = (PIPERX15STATUS[0] !== 1'bz) && PIPERX15STATUS_delay[0]; // rv 0 + assign PIPERX15STATUS_in[1] = (PIPERX15STATUS[1] !== 1'bz) && PIPERX15STATUS_delay[1]; // rv 0 + assign PIPERX15STATUS_in[2] = (PIPERX15STATUS[2] !== 1'bz) && PIPERX15STATUS_delay[2]; // rv 0 + assign PIPERX15SYNCHEADER_in[0] = (PIPERX15SYNCHEADER[0] !== 1'bz) && PIPERX15SYNCHEADER_delay[0]; // rv 0 + assign PIPERX15SYNCHEADER_in[1] = (PIPERX15SYNCHEADER[1] !== 1'bz) && PIPERX15SYNCHEADER_delay[1]; // rv 0 + assign PIPERX15VALID_in = (PIPERX15VALID !== 1'bz) && PIPERX15VALID_delay; // rv 0 + assign PIPETX00EQCOEFF_in[0] = (PIPETX00EQCOEFF[0] !== 1'bz) && PIPETX00EQCOEFF_delay[0]; // rv 0 + assign PIPETX00EQCOEFF_in[10] = (PIPETX00EQCOEFF[10] !== 1'bz) && PIPETX00EQCOEFF_delay[10]; // rv 0 + assign PIPETX00EQCOEFF_in[11] = (PIPETX00EQCOEFF[11] !== 1'bz) && PIPETX00EQCOEFF_delay[11]; // rv 0 + assign PIPETX00EQCOEFF_in[12] = (PIPETX00EQCOEFF[12] !== 1'bz) && PIPETX00EQCOEFF_delay[12]; // rv 0 + assign PIPETX00EQCOEFF_in[13] = (PIPETX00EQCOEFF[13] !== 1'bz) && PIPETX00EQCOEFF_delay[13]; // rv 0 + assign PIPETX00EQCOEFF_in[14] = (PIPETX00EQCOEFF[14] !== 1'bz) && PIPETX00EQCOEFF_delay[14]; // rv 0 + assign PIPETX00EQCOEFF_in[15] = (PIPETX00EQCOEFF[15] !== 1'bz) && PIPETX00EQCOEFF_delay[15]; // rv 0 + assign PIPETX00EQCOEFF_in[16] = (PIPETX00EQCOEFF[16] !== 1'bz) && PIPETX00EQCOEFF_delay[16]; // rv 0 + assign PIPETX00EQCOEFF_in[17] = (PIPETX00EQCOEFF[17] !== 1'bz) && PIPETX00EQCOEFF_delay[17]; // rv 0 + assign PIPETX00EQCOEFF_in[1] = (PIPETX00EQCOEFF[1] !== 1'bz) && PIPETX00EQCOEFF_delay[1]; // rv 0 + assign PIPETX00EQCOEFF_in[2] = (PIPETX00EQCOEFF[2] !== 1'bz) && PIPETX00EQCOEFF_delay[2]; // rv 0 + assign PIPETX00EQCOEFF_in[3] = (PIPETX00EQCOEFF[3] !== 1'bz) && PIPETX00EQCOEFF_delay[3]; // rv 0 + assign PIPETX00EQCOEFF_in[4] = (PIPETX00EQCOEFF[4] !== 1'bz) && PIPETX00EQCOEFF_delay[4]; // rv 0 + assign PIPETX00EQCOEFF_in[5] = (PIPETX00EQCOEFF[5] !== 1'bz) && PIPETX00EQCOEFF_delay[5]; // rv 0 + assign PIPETX00EQCOEFF_in[6] = (PIPETX00EQCOEFF[6] !== 1'bz) && PIPETX00EQCOEFF_delay[6]; // rv 0 + assign PIPETX00EQCOEFF_in[7] = (PIPETX00EQCOEFF[7] !== 1'bz) && PIPETX00EQCOEFF_delay[7]; // rv 0 + assign PIPETX00EQCOEFF_in[8] = (PIPETX00EQCOEFF[8] !== 1'bz) && PIPETX00EQCOEFF_delay[8]; // rv 0 + assign PIPETX00EQCOEFF_in[9] = (PIPETX00EQCOEFF[9] !== 1'bz) && PIPETX00EQCOEFF_delay[9]; // rv 0 + assign PIPETX00EQDONE_in = (PIPETX00EQDONE !== 1'bz) && PIPETX00EQDONE_delay; // rv 0 + assign PIPETX01EQCOEFF_in[0] = (PIPETX01EQCOEFF[0] !== 1'bz) && PIPETX01EQCOEFF_delay[0]; // rv 0 + assign PIPETX01EQCOEFF_in[10] = (PIPETX01EQCOEFF[10] !== 1'bz) && PIPETX01EQCOEFF_delay[10]; // rv 0 + assign PIPETX01EQCOEFF_in[11] = (PIPETX01EQCOEFF[11] !== 1'bz) && PIPETX01EQCOEFF_delay[11]; // rv 0 + assign PIPETX01EQCOEFF_in[12] = (PIPETX01EQCOEFF[12] !== 1'bz) && PIPETX01EQCOEFF_delay[12]; // rv 0 + assign PIPETX01EQCOEFF_in[13] = (PIPETX01EQCOEFF[13] !== 1'bz) && PIPETX01EQCOEFF_delay[13]; // rv 0 + assign PIPETX01EQCOEFF_in[14] = (PIPETX01EQCOEFF[14] !== 1'bz) && PIPETX01EQCOEFF_delay[14]; // rv 0 + assign PIPETX01EQCOEFF_in[15] = (PIPETX01EQCOEFF[15] !== 1'bz) && PIPETX01EQCOEFF_delay[15]; // rv 0 + assign PIPETX01EQCOEFF_in[16] = (PIPETX01EQCOEFF[16] !== 1'bz) && PIPETX01EQCOEFF_delay[16]; // rv 0 + assign PIPETX01EQCOEFF_in[17] = (PIPETX01EQCOEFF[17] !== 1'bz) && PIPETX01EQCOEFF_delay[17]; // rv 0 + assign PIPETX01EQCOEFF_in[1] = (PIPETX01EQCOEFF[1] !== 1'bz) && PIPETX01EQCOEFF_delay[1]; // rv 0 + assign PIPETX01EQCOEFF_in[2] = (PIPETX01EQCOEFF[2] !== 1'bz) && PIPETX01EQCOEFF_delay[2]; // rv 0 + assign PIPETX01EQCOEFF_in[3] = (PIPETX01EQCOEFF[3] !== 1'bz) && PIPETX01EQCOEFF_delay[3]; // rv 0 + assign PIPETX01EQCOEFF_in[4] = (PIPETX01EQCOEFF[4] !== 1'bz) && PIPETX01EQCOEFF_delay[4]; // rv 0 + assign PIPETX01EQCOEFF_in[5] = (PIPETX01EQCOEFF[5] !== 1'bz) && PIPETX01EQCOEFF_delay[5]; // rv 0 + assign PIPETX01EQCOEFF_in[6] = (PIPETX01EQCOEFF[6] !== 1'bz) && PIPETX01EQCOEFF_delay[6]; // rv 0 + assign PIPETX01EQCOEFF_in[7] = (PIPETX01EQCOEFF[7] !== 1'bz) && PIPETX01EQCOEFF_delay[7]; // rv 0 + assign PIPETX01EQCOEFF_in[8] = (PIPETX01EQCOEFF[8] !== 1'bz) && PIPETX01EQCOEFF_delay[8]; // rv 0 + assign PIPETX01EQCOEFF_in[9] = (PIPETX01EQCOEFF[9] !== 1'bz) && PIPETX01EQCOEFF_delay[9]; // rv 0 + assign PIPETX01EQDONE_in = (PIPETX01EQDONE !== 1'bz) && PIPETX01EQDONE_delay; // rv 0 + assign PIPETX02EQCOEFF_in[0] = (PIPETX02EQCOEFF[0] !== 1'bz) && PIPETX02EQCOEFF_delay[0]; // rv 0 + assign PIPETX02EQCOEFF_in[10] = (PIPETX02EQCOEFF[10] !== 1'bz) && PIPETX02EQCOEFF_delay[10]; // rv 0 + assign PIPETX02EQCOEFF_in[11] = (PIPETX02EQCOEFF[11] !== 1'bz) && PIPETX02EQCOEFF_delay[11]; // rv 0 + assign PIPETX02EQCOEFF_in[12] = (PIPETX02EQCOEFF[12] !== 1'bz) && PIPETX02EQCOEFF_delay[12]; // rv 0 + assign PIPETX02EQCOEFF_in[13] = (PIPETX02EQCOEFF[13] !== 1'bz) && PIPETX02EQCOEFF_delay[13]; // rv 0 + assign PIPETX02EQCOEFF_in[14] = (PIPETX02EQCOEFF[14] !== 1'bz) && PIPETX02EQCOEFF_delay[14]; // rv 0 + assign PIPETX02EQCOEFF_in[15] = (PIPETX02EQCOEFF[15] !== 1'bz) && PIPETX02EQCOEFF_delay[15]; // rv 0 + assign PIPETX02EQCOEFF_in[16] = (PIPETX02EQCOEFF[16] !== 1'bz) && PIPETX02EQCOEFF_delay[16]; // rv 0 + assign PIPETX02EQCOEFF_in[17] = (PIPETX02EQCOEFF[17] !== 1'bz) && PIPETX02EQCOEFF_delay[17]; // rv 0 + assign PIPETX02EQCOEFF_in[1] = (PIPETX02EQCOEFF[1] !== 1'bz) && PIPETX02EQCOEFF_delay[1]; // rv 0 + assign PIPETX02EQCOEFF_in[2] = (PIPETX02EQCOEFF[2] !== 1'bz) && PIPETX02EQCOEFF_delay[2]; // rv 0 + assign PIPETX02EQCOEFF_in[3] = (PIPETX02EQCOEFF[3] !== 1'bz) && PIPETX02EQCOEFF_delay[3]; // rv 0 + assign PIPETX02EQCOEFF_in[4] = (PIPETX02EQCOEFF[4] !== 1'bz) && PIPETX02EQCOEFF_delay[4]; // rv 0 + assign PIPETX02EQCOEFF_in[5] = (PIPETX02EQCOEFF[5] !== 1'bz) && PIPETX02EQCOEFF_delay[5]; // rv 0 + assign PIPETX02EQCOEFF_in[6] = (PIPETX02EQCOEFF[6] !== 1'bz) && PIPETX02EQCOEFF_delay[6]; // rv 0 + assign PIPETX02EQCOEFF_in[7] = (PIPETX02EQCOEFF[7] !== 1'bz) && PIPETX02EQCOEFF_delay[7]; // rv 0 + assign PIPETX02EQCOEFF_in[8] = (PIPETX02EQCOEFF[8] !== 1'bz) && PIPETX02EQCOEFF_delay[8]; // rv 0 + assign PIPETX02EQCOEFF_in[9] = (PIPETX02EQCOEFF[9] !== 1'bz) && PIPETX02EQCOEFF_delay[9]; // rv 0 + assign PIPETX02EQDONE_in = (PIPETX02EQDONE !== 1'bz) && PIPETX02EQDONE_delay; // rv 0 + assign PIPETX03EQCOEFF_in[0] = (PIPETX03EQCOEFF[0] !== 1'bz) && PIPETX03EQCOEFF_delay[0]; // rv 0 + assign PIPETX03EQCOEFF_in[10] = (PIPETX03EQCOEFF[10] !== 1'bz) && PIPETX03EQCOEFF_delay[10]; // rv 0 + assign PIPETX03EQCOEFF_in[11] = (PIPETX03EQCOEFF[11] !== 1'bz) && PIPETX03EQCOEFF_delay[11]; // rv 0 + assign PIPETX03EQCOEFF_in[12] = (PIPETX03EQCOEFF[12] !== 1'bz) && PIPETX03EQCOEFF_delay[12]; // rv 0 + assign PIPETX03EQCOEFF_in[13] = (PIPETX03EQCOEFF[13] !== 1'bz) && PIPETX03EQCOEFF_delay[13]; // rv 0 + assign PIPETX03EQCOEFF_in[14] = (PIPETX03EQCOEFF[14] !== 1'bz) && PIPETX03EQCOEFF_delay[14]; // rv 0 + assign PIPETX03EQCOEFF_in[15] = (PIPETX03EQCOEFF[15] !== 1'bz) && PIPETX03EQCOEFF_delay[15]; // rv 0 + assign PIPETX03EQCOEFF_in[16] = (PIPETX03EQCOEFF[16] !== 1'bz) && PIPETX03EQCOEFF_delay[16]; // rv 0 + assign PIPETX03EQCOEFF_in[17] = (PIPETX03EQCOEFF[17] !== 1'bz) && PIPETX03EQCOEFF_delay[17]; // rv 0 + assign PIPETX03EQCOEFF_in[1] = (PIPETX03EQCOEFF[1] !== 1'bz) && PIPETX03EQCOEFF_delay[1]; // rv 0 + assign PIPETX03EQCOEFF_in[2] = (PIPETX03EQCOEFF[2] !== 1'bz) && PIPETX03EQCOEFF_delay[2]; // rv 0 + assign PIPETX03EQCOEFF_in[3] = (PIPETX03EQCOEFF[3] !== 1'bz) && PIPETX03EQCOEFF_delay[3]; // rv 0 + assign PIPETX03EQCOEFF_in[4] = (PIPETX03EQCOEFF[4] !== 1'bz) && PIPETX03EQCOEFF_delay[4]; // rv 0 + assign PIPETX03EQCOEFF_in[5] = (PIPETX03EQCOEFF[5] !== 1'bz) && PIPETX03EQCOEFF_delay[5]; // rv 0 + assign PIPETX03EQCOEFF_in[6] = (PIPETX03EQCOEFF[6] !== 1'bz) && PIPETX03EQCOEFF_delay[6]; // rv 0 + assign PIPETX03EQCOEFF_in[7] = (PIPETX03EQCOEFF[7] !== 1'bz) && PIPETX03EQCOEFF_delay[7]; // rv 0 + assign PIPETX03EQCOEFF_in[8] = (PIPETX03EQCOEFF[8] !== 1'bz) && PIPETX03EQCOEFF_delay[8]; // rv 0 + assign PIPETX03EQCOEFF_in[9] = (PIPETX03EQCOEFF[9] !== 1'bz) && PIPETX03EQCOEFF_delay[9]; // rv 0 + assign PIPETX03EQDONE_in = (PIPETX03EQDONE !== 1'bz) && PIPETX03EQDONE_delay; // rv 0 + assign PIPETX04EQCOEFF_in[0] = (PIPETX04EQCOEFF[0] !== 1'bz) && PIPETX04EQCOEFF_delay[0]; // rv 0 + assign PIPETX04EQCOEFF_in[10] = (PIPETX04EQCOEFF[10] !== 1'bz) && PIPETX04EQCOEFF_delay[10]; // rv 0 + assign PIPETX04EQCOEFF_in[11] = (PIPETX04EQCOEFF[11] !== 1'bz) && PIPETX04EQCOEFF_delay[11]; // rv 0 + assign PIPETX04EQCOEFF_in[12] = (PIPETX04EQCOEFF[12] !== 1'bz) && PIPETX04EQCOEFF_delay[12]; // rv 0 + assign PIPETX04EQCOEFF_in[13] = (PIPETX04EQCOEFF[13] !== 1'bz) && PIPETX04EQCOEFF_delay[13]; // rv 0 + assign PIPETX04EQCOEFF_in[14] = (PIPETX04EQCOEFF[14] !== 1'bz) && PIPETX04EQCOEFF_delay[14]; // rv 0 + assign PIPETX04EQCOEFF_in[15] = (PIPETX04EQCOEFF[15] !== 1'bz) && PIPETX04EQCOEFF_delay[15]; // rv 0 + assign PIPETX04EQCOEFF_in[16] = (PIPETX04EQCOEFF[16] !== 1'bz) && PIPETX04EQCOEFF_delay[16]; // rv 0 + assign PIPETX04EQCOEFF_in[17] = (PIPETX04EQCOEFF[17] !== 1'bz) && PIPETX04EQCOEFF_delay[17]; // rv 0 + assign PIPETX04EQCOEFF_in[1] = (PIPETX04EQCOEFF[1] !== 1'bz) && PIPETX04EQCOEFF_delay[1]; // rv 0 + assign PIPETX04EQCOEFF_in[2] = (PIPETX04EQCOEFF[2] !== 1'bz) && PIPETX04EQCOEFF_delay[2]; // rv 0 + assign PIPETX04EQCOEFF_in[3] = (PIPETX04EQCOEFF[3] !== 1'bz) && PIPETX04EQCOEFF_delay[3]; // rv 0 + assign PIPETX04EQCOEFF_in[4] = (PIPETX04EQCOEFF[4] !== 1'bz) && PIPETX04EQCOEFF_delay[4]; // rv 0 + assign PIPETX04EQCOEFF_in[5] = (PIPETX04EQCOEFF[5] !== 1'bz) && PIPETX04EQCOEFF_delay[5]; // rv 0 + assign PIPETX04EQCOEFF_in[6] = (PIPETX04EQCOEFF[6] !== 1'bz) && PIPETX04EQCOEFF_delay[6]; // rv 0 + assign PIPETX04EQCOEFF_in[7] = (PIPETX04EQCOEFF[7] !== 1'bz) && PIPETX04EQCOEFF_delay[7]; // rv 0 + assign PIPETX04EQCOEFF_in[8] = (PIPETX04EQCOEFF[8] !== 1'bz) && PIPETX04EQCOEFF_delay[8]; // rv 0 + assign PIPETX04EQCOEFF_in[9] = (PIPETX04EQCOEFF[9] !== 1'bz) && PIPETX04EQCOEFF_delay[9]; // rv 0 + assign PIPETX04EQDONE_in = (PIPETX04EQDONE !== 1'bz) && PIPETX04EQDONE_delay; // rv 0 + assign PIPETX05EQCOEFF_in[0] = (PIPETX05EQCOEFF[0] !== 1'bz) && PIPETX05EQCOEFF_delay[0]; // rv 0 + assign PIPETX05EQCOEFF_in[10] = (PIPETX05EQCOEFF[10] !== 1'bz) && PIPETX05EQCOEFF_delay[10]; // rv 0 + assign PIPETX05EQCOEFF_in[11] = (PIPETX05EQCOEFF[11] !== 1'bz) && PIPETX05EQCOEFF_delay[11]; // rv 0 + assign PIPETX05EQCOEFF_in[12] = (PIPETX05EQCOEFF[12] !== 1'bz) && PIPETX05EQCOEFF_delay[12]; // rv 0 + assign PIPETX05EQCOEFF_in[13] = (PIPETX05EQCOEFF[13] !== 1'bz) && PIPETX05EQCOEFF_delay[13]; // rv 0 + assign PIPETX05EQCOEFF_in[14] = (PIPETX05EQCOEFF[14] !== 1'bz) && PIPETX05EQCOEFF_delay[14]; // rv 0 + assign PIPETX05EQCOEFF_in[15] = (PIPETX05EQCOEFF[15] !== 1'bz) && PIPETX05EQCOEFF_delay[15]; // rv 0 + assign PIPETX05EQCOEFF_in[16] = (PIPETX05EQCOEFF[16] !== 1'bz) && PIPETX05EQCOEFF_delay[16]; // rv 0 + assign PIPETX05EQCOEFF_in[17] = (PIPETX05EQCOEFF[17] !== 1'bz) && PIPETX05EQCOEFF_delay[17]; // rv 0 + assign PIPETX05EQCOEFF_in[1] = (PIPETX05EQCOEFF[1] !== 1'bz) && PIPETX05EQCOEFF_delay[1]; // rv 0 + assign PIPETX05EQCOEFF_in[2] = (PIPETX05EQCOEFF[2] !== 1'bz) && PIPETX05EQCOEFF_delay[2]; // rv 0 + assign PIPETX05EQCOEFF_in[3] = (PIPETX05EQCOEFF[3] !== 1'bz) && PIPETX05EQCOEFF_delay[3]; // rv 0 + assign PIPETX05EQCOEFF_in[4] = (PIPETX05EQCOEFF[4] !== 1'bz) && PIPETX05EQCOEFF_delay[4]; // rv 0 + assign PIPETX05EQCOEFF_in[5] = (PIPETX05EQCOEFF[5] !== 1'bz) && PIPETX05EQCOEFF_delay[5]; // rv 0 + assign PIPETX05EQCOEFF_in[6] = (PIPETX05EQCOEFF[6] !== 1'bz) && PIPETX05EQCOEFF_delay[6]; // rv 0 + assign PIPETX05EQCOEFF_in[7] = (PIPETX05EQCOEFF[7] !== 1'bz) && PIPETX05EQCOEFF_delay[7]; // rv 0 + assign PIPETX05EQCOEFF_in[8] = (PIPETX05EQCOEFF[8] !== 1'bz) && PIPETX05EQCOEFF_delay[8]; // rv 0 + assign PIPETX05EQCOEFF_in[9] = (PIPETX05EQCOEFF[9] !== 1'bz) && PIPETX05EQCOEFF_delay[9]; // rv 0 + assign PIPETX05EQDONE_in = (PIPETX05EQDONE !== 1'bz) && PIPETX05EQDONE_delay; // rv 0 + assign PIPETX06EQCOEFF_in[0] = (PIPETX06EQCOEFF[0] !== 1'bz) && PIPETX06EQCOEFF_delay[0]; // rv 0 + assign PIPETX06EQCOEFF_in[10] = (PIPETX06EQCOEFF[10] !== 1'bz) && PIPETX06EQCOEFF_delay[10]; // rv 0 + assign PIPETX06EQCOEFF_in[11] = (PIPETX06EQCOEFF[11] !== 1'bz) && PIPETX06EQCOEFF_delay[11]; // rv 0 + assign PIPETX06EQCOEFF_in[12] = (PIPETX06EQCOEFF[12] !== 1'bz) && PIPETX06EQCOEFF_delay[12]; // rv 0 + assign PIPETX06EQCOEFF_in[13] = (PIPETX06EQCOEFF[13] !== 1'bz) && PIPETX06EQCOEFF_delay[13]; // rv 0 + assign PIPETX06EQCOEFF_in[14] = (PIPETX06EQCOEFF[14] !== 1'bz) && PIPETX06EQCOEFF_delay[14]; // rv 0 + assign PIPETX06EQCOEFF_in[15] = (PIPETX06EQCOEFF[15] !== 1'bz) && PIPETX06EQCOEFF_delay[15]; // rv 0 + assign PIPETX06EQCOEFF_in[16] = (PIPETX06EQCOEFF[16] !== 1'bz) && PIPETX06EQCOEFF_delay[16]; // rv 0 + assign PIPETX06EQCOEFF_in[17] = (PIPETX06EQCOEFF[17] !== 1'bz) && PIPETX06EQCOEFF_delay[17]; // rv 0 + assign PIPETX06EQCOEFF_in[1] = (PIPETX06EQCOEFF[1] !== 1'bz) && PIPETX06EQCOEFF_delay[1]; // rv 0 + assign PIPETX06EQCOEFF_in[2] = (PIPETX06EQCOEFF[2] !== 1'bz) && PIPETX06EQCOEFF_delay[2]; // rv 0 + assign PIPETX06EQCOEFF_in[3] = (PIPETX06EQCOEFF[3] !== 1'bz) && PIPETX06EQCOEFF_delay[3]; // rv 0 + assign PIPETX06EQCOEFF_in[4] = (PIPETX06EQCOEFF[4] !== 1'bz) && PIPETX06EQCOEFF_delay[4]; // rv 0 + assign PIPETX06EQCOEFF_in[5] = (PIPETX06EQCOEFF[5] !== 1'bz) && PIPETX06EQCOEFF_delay[5]; // rv 0 + assign PIPETX06EQCOEFF_in[6] = (PIPETX06EQCOEFF[6] !== 1'bz) && PIPETX06EQCOEFF_delay[6]; // rv 0 + assign PIPETX06EQCOEFF_in[7] = (PIPETX06EQCOEFF[7] !== 1'bz) && PIPETX06EQCOEFF_delay[7]; // rv 0 + assign PIPETX06EQCOEFF_in[8] = (PIPETX06EQCOEFF[8] !== 1'bz) && PIPETX06EQCOEFF_delay[8]; // rv 0 + assign PIPETX06EQCOEFF_in[9] = (PIPETX06EQCOEFF[9] !== 1'bz) && PIPETX06EQCOEFF_delay[9]; // rv 0 + assign PIPETX06EQDONE_in = (PIPETX06EQDONE !== 1'bz) && PIPETX06EQDONE_delay; // rv 0 + assign PIPETX07EQCOEFF_in[0] = (PIPETX07EQCOEFF[0] !== 1'bz) && PIPETX07EQCOEFF_delay[0]; // rv 0 + assign PIPETX07EQCOEFF_in[10] = (PIPETX07EQCOEFF[10] !== 1'bz) && PIPETX07EQCOEFF_delay[10]; // rv 0 + assign PIPETX07EQCOEFF_in[11] = (PIPETX07EQCOEFF[11] !== 1'bz) && PIPETX07EQCOEFF_delay[11]; // rv 0 + assign PIPETX07EQCOEFF_in[12] = (PIPETX07EQCOEFF[12] !== 1'bz) && PIPETX07EQCOEFF_delay[12]; // rv 0 + assign PIPETX07EQCOEFF_in[13] = (PIPETX07EQCOEFF[13] !== 1'bz) && PIPETX07EQCOEFF_delay[13]; // rv 0 + assign PIPETX07EQCOEFF_in[14] = (PIPETX07EQCOEFF[14] !== 1'bz) && PIPETX07EQCOEFF_delay[14]; // rv 0 + assign PIPETX07EQCOEFF_in[15] = (PIPETX07EQCOEFF[15] !== 1'bz) && PIPETX07EQCOEFF_delay[15]; // rv 0 + assign PIPETX07EQCOEFF_in[16] = (PIPETX07EQCOEFF[16] !== 1'bz) && PIPETX07EQCOEFF_delay[16]; // rv 0 + assign PIPETX07EQCOEFF_in[17] = (PIPETX07EQCOEFF[17] !== 1'bz) && PIPETX07EQCOEFF_delay[17]; // rv 0 + assign PIPETX07EQCOEFF_in[1] = (PIPETX07EQCOEFF[1] !== 1'bz) && PIPETX07EQCOEFF_delay[1]; // rv 0 + assign PIPETX07EQCOEFF_in[2] = (PIPETX07EQCOEFF[2] !== 1'bz) && PIPETX07EQCOEFF_delay[2]; // rv 0 + assign PIPETX07EQCOEFF_in[3] = (PIPETX07EQCOEFF[3] !== 1'bz) && PIPETX07EQCOEFF_delay[3]; // rv 0 + assign PIPETX07EQCOEFF_in[4] = (PIPETX07EQCOEFF[4] !== 1'bz) && PIPETX07EQCOEFF_delay[4]; // rv 0 + assign PIPETX07EQCOEFF_in[5] = (PIPETX07EQCOEFF[5] !== 1'bz) && PIPETX07EQCOEFF_delay[5]; // rv 0 + assign PIPETX07EQCOEFF_in[6] = (PIPETX07EQCOEFF[6] !== 1'bz) && PIPETX07EQCOEFF_delay[6]; // rv 0 + assign PIPETX07EQCOEFF_in[7] = (PIPETX07EQCOEFF[7] !== 1'bz) && PIPETX07EQCOEFF_delay[7]; // rv 0 + assign PIPETX07EQCOEFF_in[8] = (PIPETX07EQCOEFF[8] !== 1'bz) && PIPETX07EQCOEFF_delay[8]; // rv 0 + assign PIPETX07EQCOEFF_in[9] = (PIPETX07EQCOEFF[9] !== 1'bz) && PIPETX07EQCOEFF_delay[9]; // rv 0 + assign PIPETX07EQDONE_in = (PIPETX07EQDONE !== 1'bz) && PIPETX07EQDONE_delay; // rv 0 + assign PIPETX08EQCOEFF_in[0] = (PIPETX08EQCOEFF[0] !== 1'bz) && PIPETX08EQCOEFF_delay[0]; // rv 0 + assign PIPETX08EQCOEFF_in[10] = (PIPETX08EQCOEFF[10] !== 1'bz) && PIPETX08EQCOEFF_delay[10]; // rv 0 + assign PIPETX08EQCOEFF_in[11] = (PIPETX08EQCOEFF[11] !== 1'bz) && PIPETX08EQCOEFF_delay[11]; // rv 0 + assign PIPETX08EQCOEFF_in[12] = (PIPETX08EQCOEFF[12] !== 1'bz) && PIPETX08EQCOEFF_delay[12]; // rv 0 + assign PIPETX08EQCOEFF_in[13] = (PIPETX08EQCOEFF[13] !== 1'bz) && PIPETX08EQCOEFF_delay[13]; // rv 0 + assign PIPETX08EQCOEFF_in[14] = (PIPETX08EQCOEFF[14] !== 1'bz) && PIPETX08EQCOEFF_delay[14]; // rv 0 + assign PIPETX08EQCOEFF_in[15] = (PIPETX08EQCOEFF[15] !== 1'bz) && PIPETX08EQCOEFF_delay[15]; // rv 0 + assign PIPETX08EQCOEFF_in[16] = (PIPETX08EQCOEFF[16] !== 1'bz) && PIPETX08EQCOEFF_delay[16]; // rv 0 + assign PIPETX08EQCOEFF_in[17] = (PIPETX08EQCOEFF[17] !== 1'bz) && PIPETX08EQCOEFF_delay[17]; // rv 0 + assign PIPETX08EQCOEFF_in[1] = (PIPETX08EQCOEFF[1] !== 1'bz) && PIPETX08EQCOEFF_delay[1]; // rv 0 + assign PIPETX08EQCOEFF_in[2] = (PIPETX08EQCOEFF[2] !== 1'bz) && PIPETX08EQCOEFF_delay[2]; // rv 0 + assign PIPETX08EQCOEFF_in[3] = (PIPETX08EQCOEFF[3] !== 1'bz) && PIPETX08EQCOEFF_delay[3]; // rv 0 + assign PIPETX08EQCOEFF_in[4] = (PIPETX08EQCOEFF[4] !== 1'bz) && PIPETX08EQCOEFF_delay[4]; // rv 0 + assign PIPETX08EQCOEFF_in[5] = (PIPETX08EQCOEFF[5] !== 1'bz) && PIPETX08EQCOEFF_delay[5]; // rv 0 + assign PIPETX08EQCOEFF_in[6] = (PIPETX08EQCOEFF[6] !== 1'bz) && PIPETX08EQCOEFF_delay[6]; // rv 0 + assign PIPETX08EQCOEFF_in[7] = (PIPETX08EQCOEFF[7] !== 1'bz) && PIPETX08EQCOEFF_delay[7]; // rv 0 + assign PIPETX08EQCOEFF_in[8] = (PIPETX08EQCOEFF[8] !== 1'bz) && PIPETX08EQCOEFF_delay[8]; // rv 0 + assign PIPETX08EQCOEFF_in[9] = (PIPETX08EQCOEFF[9] !== 1'bz) && PIPETX08EQCOEFF_delay[9]; // rv 0 + assign PIPETX08EQDONE_in = (PIPETX08EQDONE !== 1'bz) && PIPETX08EQDONE_delay; // rv 0 + assign PIPETX09EQCOEFF_in[0] = (PIPETX09EQCOEFF[0] !== 1'bz) && PIPETX09EQCOEFF_delay[0]; // rv 0 + assign PIPETX09EQCOEFF_in[10] = (PIPETX09EQCOEFF[10] !== 1'bz) && PIPETX09EQCOEFF_delay[10]; // rv 0 + assign PIPETX09EQCOEFF_in[11] = (PIPETX09EQCOEFF[11] !== 1'bz) && PIPETX09EQCOEFF_delay[11]; // rv 0 + assign PIPETX09EQCOEFF_in[12] = (PIPETX09EQCOEFF[12] !== 1'bz) && PIPETX09EQCOEFF_delay[12]; // rv 0 + assign PIPETX09EQCOEFF_in[13] = (PIPETX09EQCOEFF[13] !== 1'bz) && PIPETX09EQCOEFF_delay[13]; // rv 0 + assign PIPETX09EQCOEFF_in[14] = (PIPETX09EQCOEFF[14] !== 1'bz) && PIPETX09EQCOEFF_delay[14]; // rv 0 + assign PIPETX09EQCOEFF_in[15] = (PIPETX09EQCOEFF[15] !== 1'bz) && PIPETX09EQCOEFF_delay[15]; // rv 0 + assign PIPETX09EQCOEFF_in[16] = (PIPETX09EQCOEFF[16] !== 1'bz) && PIPETX09EQCOEFF_delay[16]; // rv 0 + assign PIPETX09EQCOEFF_in[17] = (PIPETX09EQCOEFF[17] !== 1'bz) && PIPETX09EQCOEFF_delay[17]; // rv 0 + assign PIPETX09EQCOEFF_in[1] = (PIPETX09EQCOEFF[1] !== 1'bz) && PIPETX09EQCOEFF_delay[1]; // rv 0 + assign PIPETX09EQCOEFF_in[2] = (PIPETX09EQCOEFF[2] !== 1'bz) && PIPETX09EQCOEFF_delay[2]; // rv 0 + assign PIPETX09EQCOEFF_in[3] = (PIPETX09EQCOEFF[3] !== 1'bz) && PIPETX09EQCOEFF_delay[3]; // rv 0 + assign PIPETX09EQCOEFF_in[4] = (PIPETX09EQCOEFF[4] !== 1'bz) && PIPETX09EQCOEFF_delay[4]; // rv 0 + assign PIPETX09EQCOEFF_in[5] = (PIPETX09EQCOEFF[5] !== 1'bz) && PIPETX09EQCOEFF_delay[5]; // rv 0 + assign PIPETX09EQCOEFF_in[6] = (PIPETX09EQCOEFF[6] !== 1'bz) && PIPETX09EQCOEFF_delay[6]; // rv 0 + assign PIPETX09EQCOEFF_in[7] = (PIPETX09EQCOEFF[7] !== 1'bz) && PIPETX09EQCOEFF_delay[7]; // rv 0 + assign PIPETX09EQCOEFF_in[8] = (PIPETX09EQCOEFF[8] !== 1'bz) && PIPETX09EQCOEFF_delay[8]; // rv 0 + assign PIPETX09EQCOEFF_in[9] = (PIPETX09EQCOEFF[9] !== 1'bz) && PIPETX09EQCOEFF_delay[9]; // rv 0 + assign PIPETX09EQDONE_in = (PIPETX09EQDONE !== 1'bz) && PIPETX09EQDONE_delay; // rv 0 + assign PIPETX10EQCOEFF_in[0] = (PIPETX10EQCOEFF[0] !== 1'bz) && PIPETX10EQCOEFF_delay[0]; // rv 0 + assign PIPETX10EQCOEFF_in[10] = (PIPETX10EQCOEFF[10] !== 1'bz) && PIPETX10EQCOEFF_delay[10]; // rv 0 + assign PIPETX10EQCOEFF_in[11] = (PIPETX10EQCOEFF[11] !== 1'bz) && PIPETX10EQCOEFF_delay[11]; // rv 0 + assign PIPETX10EQCOEFF_in[12] = (PIPETX10EQCOEFF[12] !== 1'bz) && PIPETX10EQCOEFF_delay[12]; // rv 0 + assign PIPETX10EQCOEFF_in[13] = (PIPETX10EQCOEFF[13] !== 1'bz) && PIPETX10EQCOEFF_delay[13]; // rv 0 + assign PIPETX10EQCOEFF_in[14] = (PIPETX10EQCOEFF[14] !== 1'bz) && PIPETX10EQCOEFF_delay[14]; // rv 0 + assign PIPETX10EQCOEFF_in[15] = (PIPETX10EQCOEFF[15] !== 1'bz) && PIPETX10EQCOEFF_delay[15]; // rv 0 + assign PIPETX10EQCOEFF_in[16] = (PIPETX10EQCOEFF[16] !== 1'bz) && PIPETX10EQCOEFF_delay[16]; // rv 0 + assign PIPETX10EQCOEFF_in[17] = (PIPETX10EQCOEFF[17] !== 1'bz) && PIPETX10EQCOEFF_delay[17]; // rv 0 + assign PIPETX10EQCOEFF_in[1] = (PIPETX10EQCOEFF[1] !== 1'bz) && PIPETX10EQCOEFF_delay[1]; // rv 0 + assign PIPETX10EQCOEFF_in[2] = (PIPETX10EQCOEFF[2] !== 1'bz) && PIPETX10EQCOEFF_delay[2]; // rv 0 + assign PIPETX10EQCOEFF_in[3] = (PIPETX10EQCOEFF[3] !== 1'bz) && PIPETX10EQCOEFF_delay[3]; // rv 0 + assign PIPETX10EQCOEFF_in[4] = (PIPETX10EQCOEFF[4] !== 1'bz) && PIPETX10EQCOEFF_delay[4]; // rv 0 + assign PIPETX10EQCOEFF_in[5] = (PIPETX10EQCOEFF[5] !== 1'bz) && PIPETX10EQCOEFF_delay[5]; // rv 0 + assign PIPETX10EQCOEFF_in[6] = (PIPETX10EQCOEFF[6] !== 1'bz) && PIPETX10EQCOEFF_delay[6]; // rv 0 + assign PIPETX10EQCOEFF_in[7] = (PIPETX10EQCOEFF[7] !== 1'bz) && PIPETX10EQCOEFF_delay[7]; // rv 0 + assign PIPETX10EQCOEFF_in[8] = (PIPETX10EQCOEFF[8] !== 1'bz) && PIPETX10EQCOEFF_delay[8]; // rv 0 + assign PIPETX10EQCOEFF_in[9] = (PIPETX10EQCOEFF[9] !== 1'bz) && PIPETX10EQCOEFF_delay[9]; // rv 0 + assign PIPETX10EQDONE_in = (PIPETX10EQDONE !== 1'bz) && PIPETX10EQDONE_delay; // rv 0 + assign PIPETX11EQCOEFF_in[0] = (PIPETX11EQCOEFF[0] !== 1'bz) && PIPETX11EQCOEFF_delay[0]; // rv 0 + assign PIPETX11EQCOEFF_in[10] = (PIPETX11EQCOEFF[10] !== 1'bz) && PIPETX11EQCOEFF_delay[10]; // rv 0 + assign PIPETX11EQCOEFF_in[11] = (PIPETX11EQCOEFF[11] !== 1'bz) && PIPETX11EQCOEFF_delay[11]; // rv 0 + assign PIPETX11EQCOEFF_in[12] = (PIPETX11EQCOEFF[12] !== 1'bz) && PIPETX11EQCOEFF_delay[12]; // rv 0 + assign PIPETX11EQCOEFF_in[13] = (PIPETX11EQCOEFF[13] !== 1'bz) && PIPETX11EQCOEFF_delay[13]; // rv 0 + assign PIPETX11EQCOEFF_in[14] = (PIPETX11EQCOEFF[14] !== 1'bz) && PIPETX11EQCOEFF_delay[14]; // rv 0 + assign PIPETX11EQCOEFF_in[15] = (PIPETX11EQCOEFF[15] !== 1'bz) && PIPETX11EQCOEFF_delay[15]; // rv 0 + assign PIPETX11EQCOEFF_in[16] = (PIPETX11EQCOEFF[16] !== 1'bz) && PIPETX11EQCOEFF_delay[16]; // rv 0 + assign PIPETX11EQCOEFF_in[17] = (PIPETX11EQCOEFF[17] !== 1'bz) && PIPETX11EQCOEFF_delay[17]; // rv 0 + assign PIPETX11EQCOEFF_in[1] = (PIPETX11EQCOEFF[1] !== 1'bz) && PIPETX11EQCOEFF_delay[1]; // rv 0 + assign PIPETX11EQCOEFF_in[2] = (PIPETX11EQCOEFF[2] !== 1'bz) && PIPETX11EQCOEFF_delay[2]; // rv 0 + assign PIPETX11EQCOEFF_in[3] = (PIPETX11EQCOEFF[3] !== 1'bz) && PIPETX11EQCOEFF_delay[3]; // rv 0 + assign PIPETX11EQCOEFF_in[4] = (PIPETX11EQCOEFF[4] !== 1'bz) && PIPETX11EQCOEFF_delay[4]; // rv 0 + assign PIPETX11EQCOEFF_in[5] = (PIPETX11EQCOEFF[5] !== 1'bz) && PIPETX11EQCOEFF_delay[5]; // rv 0 + assign PIPETX11EQCOEFF_in[6] = (PIPETX11EQCOEFF[6] !== 1'bz) && PIPETX11EQCOEFF_delay[6]; // rv 0 + assign PIPETX11EQCOEFF_in[7] = (PIPETX11EQCOEFF[7] !== 1'bz) && PIPETX11EQCOEFF_delay[7]; // rv 0 + assign PIPETX11EQCOEFF_in[8] = (PIPETX11EQCOEFF[8] !== 1'bz) && PIPETX11EQCOEFF_delay[8]; // rv 0 + assign PIPETX11EQCOEFF_in[9] = (PIPETX11EQCOEFF[9] !== 1'bz) && PIPETX11EQCOEFF_delay[9]; // rv 0 + assign PIPETX11EQDONE_in = (PIPETX11EQDONE !== 1'bz) && PIPETX11EQDONE_delay; // rv 0 + assign PIPETX12EQCOEFF_in[0] = (PIPETX12EQCOEFF[0] !== 1'bz) && PIPETX12EQCOEFF_delay[0]; // rv 0 + assign PIPETX12EQCOEFF_in[10] = (PIPETX12EQCOEFF[10] !== 1'bz) && PIPETX12EQCOEFF_delay[10]; // rv 0 + assign PIPETX12EQCOEFF_in[11] = (PIPETX12EQCOEFF[11] !== 1'bz) && PIPETX12EQCOEFF_delay[11]; // rv 0 + assign PIPETX12EQCOEFF_in[12] = (PIPETX12EQCOEFF[12] !== 1'bz) && PIPETX12EQCOEFF_delay[12]; // rv 0 + assign PIPETX12EQCOEFF_in[13] = (PIPETX12EQCOEFF[13] !== 1'bz) && PIPETX12EQCOEFF_delay[13]; // rv 0 + assign PIPETX12EQCOEFF_in[14] = (PIPETX12EQCOEFF[14] !== 1'bz) && PIPETX12EQCOEFF_delay[14]; // rv 0 + assign PIPETX12EQCOEFF_in[15] = (PIPETX12EQCOEFF[15] !== 1'bz) && PIPETX12EQCOEFF_delay[15]; // rv 0 + assign PIPETX12EQCOEFF_in[16] = (PIPETX12EQCOEFF[16] !== 1'bz) && PIPETX12EQCOEFF_delay[16]; // rv 0 + assign PIPETX12EQCOEFF_in[17] = (PIPETX12EQCOEFF[17] !== 1'bz) && PIPETX12EQCOEFF_delay[17]; // rv 0 + assign PIPETX12EQCOEFF_in[1] = (PIPETX12EQCOEFF[1] !== 1'bz) && PIPETX12EQCOEFF_delay[1]; // rv 0 + assign PIPETX12EQCOEFF_in[2] = (PIPETX12EQCOEFF[2] !== 1'bz) && PIPETX12EQCOEFF_delay[2]; // rv 0 + assign PIPETX12EQCOEFF_in[3] = (PIPETX12EQCOEFF[3] !== 1'bz) && PIPETX12EQCOEFF_delay[3]; // rv 0 + assign PIPETX12EQCOEFF_in[4] = (PIPETX12EQCOEFF[4] !== 1'bz) && PIPETX12EQCOEFF_delay[4]; // rv 0 + assign PIPETX12EQCOEFF_in[5] = (PIPETX12EQCOEFF[5] !== 1'bz) && PIPETX12EQCOEFF_delay[5]; // rv 0 + assign PIPETX12EQCOEFF_in[6] = (PIPETX12EQCOEFF[6] !== 1'bz) && PIPETX12EQCOEFF_delay[6]; // rv 0 + assign PIPETX12EQCOEFF_in[7] = (PIPETX12EQCOEFF[7] !== 1'bz) && PIPETX12EQCOEFF_delay[7]; // rv 0 + assign PIPETX12EQCOEFF_in[8] = (PIPETX12EQCOEFF[8] !== 1'bz) && PIPETX12EQCOEFF_delay[8]; // rv 0 + assign PIPETX12EQCOEFF_in[9] = (PIPETX12EQCOEFF[9] !== 1'bz) && PIPETX12EQCOEFF_delay[9]; // rv 0 + assign PIPETX12EQDONE_in = (PIPETX12EQDONE !== 1'bz) && PIPETX12EQDONE_delay; // rv 0 + assign PIPETX13EQCOEFF_in[0] = (PIPETX13EQCOEFF[0] !== 1'bz) && PIPETX13EQCOEFF_delay[0]; // rv 0 + assign PIPETX13EQCOEFF_in[10] = (PIPETX13EQCOEFF[10] !== 1'bz) && PIPETX13EQCOEFF_delay[10]; // rv 0 + assign PIPETX13EQCOEFF_in[11] = (PIPETX13EQCOEFF[11] !== 1'bz) && PIPETX13EQCOEFF_delay[11]; // rv 0 + assign PIPETX13EQCOEFF_in[12] = (PIPETX13EQCOEFF[12] !== 1'bz) && PIPETX13EQCOEFF_delay[12]; // rv 0 + assign PIPETX13EQCOEFF_in[13] = (PIPETX13EQCOEFF[13] !== 1'bz) && PIPETX13EQCOEFF_delay[13]; // rv 0 + assign PIPETX13EQCOEFF_in[14] = (PIPETX13EQCOEFF[14] !== 1'bz) && PIPETX13EQCOEFF_delay[14]; // rv 0 + assign PIPETX13EQCOEFF_in[15] = (PIPETX13EQCOEFF[15] !== 1'bz) && PIPETX13EQCOEFF_delay[15]; // rv 0 + assign PIPETX13EQCOEFF_in[16] = (PIPETX13EQCOEFF[16] !== 1'bz) && PIPETX13EQCOEFF_delay[16]; // rv 0 + assign PIPETX13EQCOEFF_in[17] = (PIPETX13EQCOEFF[17] !== 1'bz) && PIPETX13EQCOEFF_delay[17]; // rv 0 + assign PIPETX13EQCOEFF_in[1] = (PIPETX13EQCOEFF[1] !== 1'bz) && PIPETX13EQCOEFF_delay[1]; // rv 0 + assign PIPETX13EQCOEFF_in[2] = (PIPETX13EQCOEFF[2] !== 1'bz) && PIPETX13EQCOEFF_delay[2]; // rv 0 + assign PIPETX13EQCOEFF_in[3] = (PIPETX13EQCOEFF[3] !== 1'bz) && PIPETX13EQCOEFF_delay[3]; // rv 0 + assign PIPETX13EQCOEFF_in[4] = (PIPETX13EQCOEFF[4] !== 1'bz) && PIPETX13EQCOEFF_delay[4]; // rv 0 + assign PIPETX13EQCOEFF_in[5] = (PIPETX13EQCOEFF[5] !== 1'bz) && PIPETX13EQCOEFF_delay[5]; // rv 0 + assign PIPETX13EQCOEFF_in[6] = (PIPETX13EQCOEFF[6] !== 1'bz) && PIPETX13EQCOEFF_delay[6]; // rv 0 + assign PIPETX13EQCOEFF_in[7] = (PIPETX13EQCOEFF[7] !== 1'bz) && PIPETX13EQCOEFF_delay[7]; // rv 0 + assign PIPETX13EQCOEFF_in[8] = (PIPETX13EQCOEFF[8] !== 1'bz) && PIPETX13EQCOEFF_delay[8]; // rv 0 + assign PIPETX13EQCOEFF_in[9] = (PIPETX13EQCOEFF[9] !== 1'bz) && PIPETX13EQCOEFF_delay[9]; // rv 0 + assign PIPETX13EQDONE_in = (PIPETX13EQDONE !== 1'bz) && PIPETX13EQDONE_delay; // rv 0 + assign PIPETX14EQCOEFF_in[0] = (PIPETX14EQCOEFF[0] !== 1'bz) && PIPETX14EQCOEFF_delay[0]; // rv 0 + assign PIPETX14EQCOEFF_in[10] = (PIPETX14EQCOEFF[10] !== 1'bz) && PIPETX14EQCOEFF_delay[10]; // rv 0 + assign PIPETX14EQCOEFF_in[11] = (PIPETX14EQCOEFF[11] !== 1'bz) && PIPETX14EQCOEFF_delay[11]; // rv 0 + assign PIPETX14EQCOEFF_in[12] = (PIPETX14EQCOEFF[12] !== 1'bz) && PIPETX14EQCOEFF_delay[12]; // rv 0 + assign PIPETX14EQCOEFF_in[13] = (PIPETX14EQCOEFF[13] !== 1'bz) && PIPETX14EQCOEFF_delay[13]; // rv 0 + assign PIPETX14EQCOEFF_in[14] = (PIPETX14EQCOEFF[14] !== 1'bz) && PIPETX14EQCOEFF_delay[14]; // rv 0 + assign PIPETX14EQCOEFF_in[15] = (PIPETX14EQCOEFF[15] !== 1'bz) && PIPETX14EQCOEFF_delay[15]; // rv 0 + assign PIPETX14EQCOEFF_in[16] = (PIPETX14EQCOEFF[16] !== 1'bz) && PIPETX14EQCOEFF_delay[16]; // rv 0 + assign PIPETX14EQCOEFF_in[17] = (PIPETX14EQCOEFF[17] !== 1'bz) && PIPETX14EQCOEFF_delay[17]; // rv 0 + assign PIPETX14EQCOEFF_in[1] = (PIPETX14EQCOEFF[1] !== 1'bz) && PIPETX14EQCOEFF_delay[1]; // rv 0 + assign PIPETX14EQCOEFF_in[2] = (PIPETX14EQCOEFF[2] !== 1'bz) && PIPETX14EQCOEFF_delay[2]; // rv 0 + assign PIPETX14EQCOEFF_in[3] = (PIPETX14EQCOEFF[3] !== 1'bz) && PIPETX14EQCOEFF_delay[3]; // rv 0 + assign PIPETX14EQCOEFF_in[4] = (PIPETX14EQCOEFF[4] !== 1'bz) && PIPETX14EQCOEFF_delay[4]; // rv 0 + assign PIPETX14EQCOEFF_in[5] = (PIPETX14EQCOEFF[5] !== 1'bz) && PIPETX14EQCOEFF_delay[5]; // rv 0 + assign PIPETX14EQCOEFF_in[6] = (PIPETX14EQCOEFF[6] !== 1'bz) && PIPETX14EQCOEFF_delay[6]; // rv 0 + assign PIPETX14EQCOEFF_in[7] = (PIPETX14EQCOEFF[7] !== 1'bz) && PIPETX14EQCOEFF_delay[7]; // rv 0 + assign PIPETX14EQCOEFF_in[8] = (PIPETX14EQCOEFF[8] !== 1'bz) && PIPETX14EQCOEFF_delay[8]; // rv 0 + assign PIPETX14EQCOEFF_in[9] = (PIPETX14EQCOEFF[9] !== 1'bz) && PIPETX14EQCOEFF_delay[9]; // rv 0 + assign PIPETX14EQDONE_in = (PIPETX14EQDONE !== 1'bz) && PIPETX14EQDONE_delay; // rv 0 + assign PIPETX15EQCOEFF_in[0] = (PIPETX15EQCOEFF[0] !== 1'bz) && PIPETX15EQCOEFF_delay[0]; // rv 0 + assign PIPETX15EQCOEFF_in[10] = (PIPETX15EQCOEFF[10] !== 1'bz) && PIPETX15EQCOEFF_delay[10]; // rv 0 + assign PIPETX15EQCOEFF_in[11] = (PIPETX15EQCOEFF[11] !== 1'bz) && PIPETX15EQCOEFF_delay[11]; // rv 0 + assign PIPETX15EQCOEFF_in[12] = (PIPETX15EQCOEFF[12] !== 1'bz) && PIPETX15EQCOEFF_delay[12]; // rv 0 + assign PIPETX15EQCOEFF_in[13] = (PIPETX15EQCOEFF[13] !== 1'bz) && PIPETX15EQCOEFF_delay[13]; // rv 0 + assign PIPETX15EQCOEFF_in[14] = (PIPETX15EQCOEFF[14] !== 1'bz) && PIPETX15EQCOEFF_delay[14]; // rv 0 + assign PIPETX15EQCOEFF_in[15] = (PIPETX15EQCOEFF[15] !== 1'bz) && PIPETX15EQCOEFF_delay[15]; // rv 0 + assign PIPETX15EQCOEFF_in[16] = (PIPETX15EQCOEFF[16] !== 1'bz) && PIPETX15EQCOEFF_delay[16]; // rv 0 + assign PIPETX15EQCOEFF_in[17] = (PIPETX15EQCOEFF[17] !== 1'bz) && PIPETX15EQCOEFF_delay[17]; // rv 0 + assign PIPETX15EQCOEFF_in[1] = (PIPETX15EQCOEFF[1] !== 1'bz) && PIPETX15EQCOEFF_delay[1]; // rv 0 + assign PIPETX15EQCOEFF_in[2] = (PIPETX15EQCOEFF[2] !== 1'bz) && PIPETX15EQCOEFF_delay[2]; // rv 0 + assign PIPETX15EQCOEFF_in[3] = (PIPETX15EQCOEFF[3] !== 1'bz) && PIPETX15EQCOEFF_delay[3]; // rv 0 + assign PIPETX15EQCOEFF_in[4] = (PIPETX15EQCOEFF[4] !== 1'bz) && PIPETX15EQCOEFF_delay[4]; // rv 0 + assign PIPETX15EQCOEFF_in[5] = (PIPETX15EQCOEFF[5] !== 1'bz) && PIPETX15EQCOEFF_delay[5]; // rv 0 + assign PIPETX15EQCOEFF_in[6] = (PIPETX15EQCOEFF[6] !== 1'bz) && PIPETX15EQCOEFF_delay[6]; // rv 0 + assign PIPETX15EQCOEFF_in[7] = (PIPETX15EQCOEFF[7] !== 1'bz) && PIPETX15EQCOEFF_delay[7]; // rv 0 + assign PIPETX15EQCOEFF_in[8] = (PIPETX15EQCOEFF[8] !== 1'bz) && PIPETX15EQCOEFF_delay[8]; // rv 0 + assign PIPETX15EQCOEFF_in[9] = (PIPETX15EQCOEFF[9] !== 1'bz) && PIPETX15EQCOEFF_delay[9]; // rv 0 + assign PIPETX15EQDONE_in = (PIPETX15EQDONE !== 1'bz) && PIPETX15EQDONE_delay; // rv 0 + assign PLGEN2UPSTREAMPREFERDEEMPH_in = (PLGEN2UPSTREAMPREFERDEEMPH !== 1'bz) && PLGEN2UPSTREAMPREFERDEEMPH_delay; // rv 0 + assign PLGEN34REDOEQSPEED_in = (PLGEN34REDOEQSPEED !== 1'bz) && PLGEN34REDOEQSPEED_delay; // rv 0 + assign PLGEN34REDOEQUALIZATION_in = (PLGEN34REDOEQUALIZATION !== 1'bz) && PLGEN34REDOEQUALIZATION_delay; // rv 0 + assign SAXISCCIXTXTDATA_in[0] = (SAXISCCIXTXTDATA[0] !== 1'bz) && SAXISCCIXTXTDATA_delay[0]; // rv 0 + assign SAXISCCIXTXTDATA_in[100] = (SAXISCCIXTXTDATA[100] !== 1'bz) && SAXISCCIXTXTDATA_delay[100]; // rv 0 + assign SAXISCCIXTXTDATA_in[101] = (SAXISCCIXTXTDATA[101] !== 1'bz) && SAXISCCIXTXTDATA_delay[101]; // rv 0 + assign SAXISCCIXTXTDATA_in[102] = (SAXISCCIXTXTDATA[102] !== 1'bz) && SAXISCCIXTXTDATA_delay[102]; // rv 0 + assign SAXISCCIXTXTDATA_in[103] = (SAXISCCIXTXTDATA[103] !== 1'bz) && SAXISCCIXTXTDATA_delay[103]; // rv 0 + assign SAXISCCIXTXTDATA_in[104] = (SAXISCCIXTXTDATA[104] !== 1'bz) && SAXISCCIXTXTDATA_delay[104]; // rv 0 + assign SAXISCCIXTXTDATA_in[105] = (SAXISCCIXTXTDATA[105] !== 1'bz) && SAXISCCIXTXTDATA_delay[105]; // rv 0 + assign SAXISCCIXTXTDATA_in[106] = (SAXISCCIXTXTDATA[106] !== 1'bz) && SAXISCCIXTXTDATA_delay[106]; // rv 0 + assign SAXISCCIXTXTDATA_in[107] = (SAXISCCIXTXTDATA[107] !== 1'bz) && SAXISCCIXTXTDATA_delay[107]; // rv 0 + assign SAXISCCIXTXTDATA_in[108] = (SAXISCCIXTXTDATA[108] !== 1'bz) && SAXISCCIXTXTDATA_delay[108]; // rv 0 + assign SAXISCCIXTXTDATA_in[109] = (SAXISCCIXTXTDATA[109] !== 1'bz) && SAXISCCIXTXTDATA_delay[109]; // rv 0 + assign SAXISCCIXTXTDATA_in[10] = (SAXISCCIXTXTDATA[10] !== 1'bz) && SAXISCCIXTXTDATA_delay[10]; // rv 0 + assign SAXISCCIXTXTDATA_in[110] = (SAXISCCIXTXTDATA[110] !== 1'bz) && SAXISCCIXTXTDATA_delay[110]; // rv 0 + assign SAXISCCIXTXTDATA_in[111] = (SAXISCCIXTXTDATA[111] !== 1'bz) && SAXISCCIXTXTDATA_delay[111]; // rv 0 + assign SAXISCCIXTXTDATA_in[112] = (SAXISCCIXTXTDATA[112] !== 1'bz) && SAXISCCIXTXTDATA_delay[112]; // rv 0 + assign SAXISCCIXTXTDATA_in[113] = (SAXISCCIXTXTDATA[113] !== 1'bz) && SAXISCCIXTXTDATA_delay[113]; // rv 0 + assign SAXISCCIXTXTDATA_in[114] = (SAXISCCIXTXTDATA[114] !== 1'bz) && SAXISCCIXTXTDATA_delay[114]; // rv 0 + assign SAXISCCIXTXTDATA_in[115] = (SAXISCCIXTXTDATA[115] !== 1'bz) && SAXISCCIXTXTDATA_delay[115]; // rv 0 + assign SAXISCCIXTXTDATA_in[116] = (SAXISCCIXTXTDATA[116] !== 1'bz) && SAXISCCIXTXTDATA_delay[116]; // rv 0 + assign SAXISCCIXTXTDATA_in[117] = (SAXISCCIXTXTDATA[117] !== 1'bz) && SAXISCCIXTXTDATA_delay[117]; // rv 0 + assign SAXISCCIXTXTDATA_in[118] = (SAXISCCIXTXTDATA[118] !== 1'bz) && SAXISCCIXTXTDATA_delay[118]; // rv 0 + assign SAXISCCIXTXTDATA_in[119] = (SAXISCCIXTXTDATA[119] !== 1'bz) && SAXISCCIXTXTDATA_delay[119]; // rv 0 + assign SAXISCCIXTXTDATA_in[11] = (SAXISCCIXTXTDATA[11] !== 1'bz) && SAXISCCIXTXTDATA_delay[11]; // rv 0 + assign SAXISCCIXTXTDATA_in[120] = (SAXISCCIXTXTDATA[120] !== 1'bz) && SAXISCCIXTXTDATA_delay[120]; // rv 0 + assign SAXISCCIXTXTDATA_in[121] = (SAXISCCIXTXTDATA[121] !== 1'bz) && SAXISCCIXTXTDATA_delay[121]; // rv 0 + assign SAXISCCIXTXTDATA_in[122] = (SAXISCCIXTXTDATA[122] !== 1'bz) && SAXISCCIXTXTDATA_delay[122]; // rv 0 + assign SAXISCCIXTXTDATA_in[123] = (SAXISCCIXTXTDATA[123] !== 1'bz) && SAXISCCIXTXTDATA_delay[123]; // rv 0 + assign SAXISCCIXTXTDATA_in[124] = (SAXISCCIXTXTDATA[124] !== 1'bz) && SAXISCCIXTXTDATA_delay[124]; // rv 0 + assign SAXISCCIXTXTDATA_in[125] = (SAXISCCIXTXTDATA[125] !== 1'bz) && SAXISCCIXTXTDATA_delay[125]; // rv 0 + assign SAXISCCIXTXTDATA_in[126] = (SAXISCCIXTXTDATA[126] !== 1'bz) && SAXISCCIXTXTDATA_delay[126]; // rv 0 + assign SAXISCCIXTXTDATA_in[127] = (SAXISCCIXTXTDATA[127] !== 1'bz) && SAXISCCIXTXTDATA_delay[127]; // rv 0 + assign SAXISCCIXTXTDATA_in[128] = (SAXISCCIXTXTDATA[128] !== 1'bz) && SAXISCCIXTXTDATA_delay[128]; // rv 0 + assign SAXISCCIXTXTDATA_in[129] = (SAXISCCIXTXTDATA[129] !== 1'bz) && SAXISCCIXTXTDATA_delay[129]; // rv 0 + assign SAXISCCIXTXTDATA_in[12] = (SAXISCCIXTXTDATA[12] !== 1'bz) && SAXISCCIXTXTDATA_delay[12]; // rv 0 + assign SAXISCCIXTXTDATA_in[130] = (SAXISCCIXTXTDATA[130] !== 1'bz) && SAXISCCIXTXTDATA_delay[130]; // rv 0 + assign SAXISCCIXTXTDATA_in[131] = (SAXISCCIXTXTDATA[131] !== 1'bz) && SAXISCCIXTXTDATA_delay[131]; // rv 0 + assign SAXISCCIXTXTDATA_in[132] = (SAXISCCIXTXTDATA[132] !== 1'bz) && SAXISCCIXTXTDATA_delay[132]; // rv 0 + assign SAXISCCIXTXTDATA_in[133] = (SAXISCCIXTXTDATA[133] !== 1'bz) && SAXISCCIXTXTDATA_delay[133]; // rv 0 + assign SAXISCCIXTXTDATA_in[134] = (SAXISCCIXTXTDATA[134] !== 1'bz) && SAXISCCIXTXTDATA_delay[134]; // rv 0 + assign SAXISCCIXTXTDATA_in[135] = (SAXISCCIXTXTDATA[135] !== 1'bz) && SAXISCCIXTXTDATA_delay[135]; // rv 0 + assign SAXISCCIXTXTDATA_in[136] = (SAXISCCIXTXTDATA[136] !== 1'bz) && SAXISCCIXTXTDATA_delay[136]; // rv 0 + assign SAXISCCIXTXTDATA_in[137] = (SAXISCCIXTXTDATA[137] !== 1'bz) && SAXISCCIXTXTDATA_delay[137]; // rv 0 + assign SAXISCCIXTXTDATA_in[138] = (SAXISCCIXTXTDATA[138] !== 1'bz) && SAXISCCIXTXTDATA_delay[138]; // rv 0 + assign SAXISCCIXTXTDATA_in[139] = (SAXISCCIXTXTDATA[139] !== 1'bz) && SAXISCCIXTXTDATA_delay[139]; // rv 0 + assign SAXISCCIXTXTDATA_in[13] = (SAXISCCIXTXTDATA[13] !== 1'bz) && SAXISCCIXTXTDATA_delay[13]; // rv 0 + assign SAXISCCIXTXTDATA_in[140] = (SAXISCCIXTXTDATA[140] !== 1'bz) && SAXISCCIXTXTDATA_delay[140]; // rv 0 + assign SAXISCCIXTXTDATA_in[141] = (SAXISCCIXTXTDATA[141] !== 1'bz) && SAXISCCIXTXTDATA_delay[141]; // rv 0 + assign SAXISCCIXTXTDATA_in[142] = (SAXISCCIXTXTDATA[142] !== 1'bz) && SAXISCCIXTXTDATA_delay[142]; // rv 0 + assign SAXISCCIXTXTDATA_in[143] = (SAXISCCIXTXTDATA[143] !== 1'bz) && SAXISCCIXTXTDATA_delay[143]; // rv 0 + assign SAXISCCIXTXTDATA_in[144] = (SAXISCCIXTXTDATA[144] !== 1'bz) && SAXISCCIXTXTDATA_delay[144]; // rv 0 + assign SAXISCCIXTXTDATA_in[145] = (SAXISCCIXTXTDATA[145] !== 1'bz) && SAXISCCIXTXTDATA_delay[145]; // rv 0 + assign SAXISCCIXTXTDATA_in[146] = (SAXISCCIXTXTDATA[146] !== 1'bz) && SAXISCCIXTXTDATA_delay[146]; // rv 0 + assign SAXISCCIXTXTDATA_in[147] = (SAXISCCIXTXTDATA[147] !== 1'bz) && SAXISCCIXTXTDATA_delay[147]; // rv 0 + assign SAXISCCIXTXTDATA_in[148] = (SAXISCCIXTXTDATA[148] !== 1'bz) && SAXISCCIXTXTDATA_delay[148]; // rv 0 + assign SAXISCCIXTXTDATA_in[149] = (SAXISCCIXTXTDATA[149] !== 1'bz) && SAXISCCIXTXTDATA_delay[149]; // rv 0 + assign SAXISCCIXTXTDATA_in[14] = (SAXISCCIXTXTDATA[14] !== 1'bz) && SAXISCCIXTXTDATA_delay[14]; // rv 0 + assign SAXISCCIXTXTDATA_in[150] = (SAXISCCIXTXTDATA[150] !== 1'bz) && SAXISCCIXTXTDATA_delay[150]; // rv 0 + assign SAXISCCIXTXTDATA_in[151] = (SAXISCCIXTXTDATA[151] !== 1'bz) && SAXISCCIXTXTDATA_delay[151]; // rv 0 + assign SAXISCCIXTXTDATA_in[152] = (SAXISCCIXTXTDATA[152] !== 1'bz) && SAXISCCIXTXTDATA_delay[152]; // rv 0 + assign SAXISCCIXTXTDATA_in[153] = (SAXISCCIXTXTDATA[153] !== 1'bz) && SAXISCCIXTXTDATA_delay[153]; // rv 0 + assign SAXISCCIXTXTDATA_in[154] = (SAXISCCIXTXTDATA[154] !== 1'bz) && SAXISCCIXTXTDATA_delay[154]; // rv 0 + assign SAXISCCIXTXTDATA_in[155] = (SAXISCCIXTXTDATA[155] !== 1'bz) && SAXISCCIXTXTDATA_delay[155]; // rv 0 + assign SAXISCCIXTXTDATA_in[156] = (SAXISCCIXTXTDATA[156] !== 1'bz) && SAXISCCIXTXTDATA_delay[156]; // rv 0 + assign SAXISCCIXTXTDATA_in[157] = (SAXISCCIXTXTDATA[157] !== 1'bz) && SAXISCCIXTXTDATA_delay[157]; // rv 0 + assign SAXISCCIXTXTDATA_in[158] = (SAXISCCIXTXTDATA[158] !== 1'bz) && SAXISCCIXTXTDATA_delay[158]; // rv 0 + assign SAXISCCIXTXTDATA_in[159] = (SAXISCCIXTXTDATA[159] !== 1'bz) && SAXISCCIXTXTDATA_delay[159]; // rv 0 + assign SAXISCCIXTXTDATA_in[15] = (SAXISCCIXTXTDATA[15] !== 1'bz) && SAXISCCIXTXTDATA_delay[15]; // rv 0 + assign SAXISCCIXTXTDATA_in[160] = (SAXISCCIXTXTDATA[160] !== 1'bz) && SAXISCCIXTXTDATA_delay[160]; // rv 0 + assign SAXISCCIXTXTDATA_in[161] = (SAXISCCIXTXTDATA[161] !== 1'bz) && SAXISCCIXTXTDATA_delay[161]; // rv 0 + assign SAXISCCIXTXTDATA_in[162] = (SAXISCCIXTXTDATA[162] !== 1'bz) && SAXISCCIXTXTDATA_delay[162]; // rv 0 + assign SAXISCCIXTXTDATA_in[163] = (SAXISCCIXTXTDATA[163] !== 1'bz) && SAXISCCIXTXTDATA_delay[163]; // rv 0 + assign SAXISCCIXTXTDATA_in[164] = (SAXISCCIXTXTDATA[164] !== 1'bz) && SAXISCCIXTXTDATA_delay[164]; // rv 0 + assign SAXISCCIXTXTDATA_in[165] = (SAXISCCIXTXTDATA[165] !== 1'bz) && SAXISCCIXTXTDATA_delay[165]; // rv 0 + assign SAXISCCIXTXTDATA_in[166] = (SAXISCCIXTXTDATA[166] !== 1'bz) && SAXISCCIXTXTDATA_delay[166]; // rv 0 + assign SAXISCCIXTXTDATA_in[167] = (SAXISCCIXTXTDATA[167] !== 1'bz) && SAXISCCIXTXTDATA_delay[167]; // rv 0 + assign SAXISCCIXTXTDATA_in[168] = (SAXISCCIXTXTDATA[168] !== 1'bz) && SAXISCCIXTXTDATA_delay[168]; // rv 0 + assign SAXISCCIXTXTDATA_in[169] = (SAXISCCIXTXTDATA[169] !== 1'bz) && SAXISCCIXTXTDATA_delay[169]; // rv 0 + assign SAXISCCIXTXTDATA_in[16] = (SAXISCCIXTXTDATA[16] !== 1'bz) && SAXISCCIXTXTDATA_delay[16]; // rv 0 + assign SAXISCCIXTXTDATA_in[170] = (SAXISCCIXTXTDATA[170] !== 1'bz) && SAXISCCIXTXTDATA_delay[170]; // rv 0 + assign SAXISCCIXTXTDATA_in[171] = (SAXISCCIXTXTDATA[171] !== 1'bz) && SAXISCCIXTXTDATA_delay[171]; // rv 0 + assign SAXISCCIXTXTDATA_in[172] = (SAXISCCIXTXTDATA[172] !== 1'bz) && SAXISCCIXTXTDATA_delay[172]; // rv 0 + assign SAXISCCIXTXTDATA_in[173] = (SAXISCCIXTXTDATA[173] !== 1'bz) && SAXISCCIXTXTDATA_delay[173]; // rv 0 + assign SAXISCCIXTXTDATA_in[174] = (SAXISCCIXTXTDATA[174] !== 1'bz) && SAXISCCIXTXTDATA_delay[174]; // rv 0 + assign SAXISCCIXTXTDATA_in[175] = (SAXISCCIXTXTDATA[175] !== 1'bz) && SAXISCCIXTXTDATA_delay[175]; // rv 0 + assign SAXISCCIXTXTDATA_in[176] = (SAXISCCIXTXTDATA[176] !== 1'bz) && SAXISCCIXTXTDATA_delay[176]; // rv 0 + assign SAXISCCIXTXTDATA_in[177] = (SAXISCCIXTXTDATA[177] !== 1'bz) && SAXISCCIXTXTDATA_delay[177]; // rv 0 + assign SAXISCCIXTXTDATA_in[178] = (SAXISCCIXTXTDATA[178] !== 1'bz) && SAXISCCIXTXTDATA_delay[178]; // rv 0 + assign SAXISCCIXTXTDATA_in[179] = (SAXISCCIXTXTDATA[179] !== 1'bz) && SAXISCCIXTXTDATA_delay[179]; // rv 0 + assign SAXISCCIXTXTDATA_in[17] = (SAXISCCIXTXTDATA[17] !== 1'bz) && SAXISCCIXTXTDATA_delay[17]; // rv 0 + assign SAXISCCIXTXTDATA_in[180] = (SAXISCCIXTXTDATA[180] !== 1'bz) && SAXISCCIXTXTDATA_delay[180]; // rv 0 + assign SAXISCCIXTXTDATA_in[181] = (SAXISCCIXTXTDATA[181] !== 1'bz) && SAXISCCIXTXTDATA_delay[181]; // rv 0 + assign SAXISCCIXTXTDATA_in[182] = (SAXISCCIXTXTDATA[182] !== 1'bz) && SAXISCCIXTXTDATA_delay[182]; // rv 0 + assign SAXISCCIXTXTDATA_in[183] = (SAXISCCIXTXTDATA[183] !== 1'bz) && SAXISCCIXTXTDATA_delay[183]; // rv 0 + assign SAXISCCIXTXTDATA_in[184] = (SAXISCCIXTXTDATA[184] !== 1'bz) && SAXISCCIXTXTDATA_delay[184]; // rv 0 + assign SAXISCCIXTXTDATA_in[185] = (SAXISCCIXTXTDATA[185] !== 1'bz) && SAXISCCIXTXTDATA_delay[185]; // rv 0 + assign SAXISCCIXTXTDATA_in[186] = (SAXISCCIXTXTDATA[186] !== 1'bz) && SAXISCCIXTXTDATA_delay[186]; // rv 0 + assign SAXISCCIXTXTDATA_in[187] = (SAXISCCIXTXTDATA[187] !== 1'bz) && SAXISCCIXTXTDATA_delay[187]; // rv 0 + assign SAXISCCIXTXTDATA_in[188] = (SAXISCCIXTXTDATA[188] !== 1'bz) && SAXISCCIXTXTDATA_delay[188]; // rv 0 + assign SAXISCCIXTXTDATA_in[189] = (SAXISCCIXTXTDATA[189] !== 1'bz) && SAXISCCIXTXTDATA_delay[189]; // rv 0 + assign SAXISCCIXTXTDATA_in[18] = (SAXISCCIXTXTDATA[18] !== 1'bz) && SAXISCCIXTXTDATA_delay[18]; // rv 0 + assign SAXISCCIXTXTDATA_in[190] = (SAXISCCIXTXTDATA[190] !== 1'bz) && SAXISCCIXTXTDATA_delay[190]; // rv 0 + assign SAXISCCIXTXTDATA_in[191] = (SAXISCCIXTXTDATA[191] !== 1'bz) && SAXISCCIXTXTDATA_delay[191]; // rv 0 + assign SAXISCCIXTXTDATA_in[192] = (SAXISCCIXTXTDATA[192] !== 1'bz) && SAXISCCIXTXTDATA_delay[192]; // rv 0 + assign SAXISCCIXTXTDATA_in[193] = (SAXISCCIXTXTDATA[193] !== 1'bz) && SAXISCCIXTXTDATA_delay[193]; // rv 0 + assign SAXISCCIXTXTDATA_in[194] = (SAXISCCIXTXTDATA[194] !== 1'bz) && SAXISCCIXTXTDATA_delay[194]; // rv 0 + assign SAXISCCIXTXTDATA_in[195] = (SAXISCCIXTXTDATA[195] !== 1'bz) && SAXISCCIXTXTDATA_delay[195]; // rv 0 + assign SAXISCCIXTXTDATA_in[196] = (SAXISCCIXTXTDATA[196] !== 1'bz) && SAXISCCIXTXTDATA_delay[196]; // rv 0 + assign SAXISCCIXTXTDATA_in[197] = (SAXISCCIXTXTDATA[197] !== 1'bz) && SAXISCCIXTXTDATA_delay[197]; // rv 0 + assign SAXISCCIXTXTDATA_in[198] = (SAXISCCIXTXTDATA[198] !== 1'bz) && SAXISCCIXTXTDATA_delay[198]; // rv 0 + assign SAXISCCIXTXTDATA_in[199] = (SAXISCCIXTXTDATA[199] !== 1'bz) && SAXISCCIXTXTDATA_delay[199]; // rv 0 + assign SAXISCCIXTXTDATA_in[19] = (SAXISCCIXTXTDATA[19] !== 1'bz) && SAXISCCIXTXTDATA_delay[19]; // rv 0 + assign SAXISCCIXTXTDATA_in[1] = (SAXISCCIXTXTDATA[1] !== 1'bz) && SAXISCCIXTXTDATA_delay[1]; // rv 0 + assign SAXISCCIXTXTDATA_in[200] = (SAXISCCIXTXTDATA[200] !== 1'bz) && SAXISCCIXTXTDATA_delay[200]; // rv 0 + assign SAXISCCIXTXTDATA_in[201] = (SAXISCCIXTXTDATA[201] !== 1'bz) && SAXISCCIXTXTDATA_delay[201]; // rv 0 + assign SAXISCCIXTXTDATA_in[202] = (SAXISCCIXTXTDATA[202] !== 1'bz) && SAXISCCIXTXTDATA_delay[202]; // rv 0 + assign SAXISCCIXTXTDATA_in[203] = (SAXISCCIXTXTDATA[203] !== 1'bz) && SAXISCCIXTXTDATA_delay[203]; // rv 0 + assign SAXISCCIXTXTDATA_in[204] = (SAXISCCIXTXTDATA[204] !== 1'bz) && SAXISCCIXTXTDATA_delay[204]; // rv 0 + assign SAXISCCIXTXTDATA_in[205] = (SAXISCCIXTXTDATA[205] !== 1'bz) && SAXISCCIXTXTDATA_delay[205]; // rv 0 + assign SAXISCCIXTXTDATA_in[206] = (SAXISCCIXTXTDATA[206] !== 1'bz) && SAXISCCIXTXTDATA_delay[206]; // rv 0 + assign SAXISCCIXTXTDATA_in[207] = (SAXISCCIXTXTDATA[207] !== 1'bz) && SAXISCCIXTXTDATA_delay[207]; // rv 0 + assign SAXISCCIXTXTDATA_in[208] = (SAXISCCIXTXTDATA[208] !== 1'bz) && SAXISCCIXTXTDATA_delay[208]; // rv 0 + assign SAXISCCIXTXTDATA_in[209] = (SAXISCCIXTXTDATA[209] !== 1'bz) && SAXISCCIXTXTDATA_delay[209]; // rv 0 + assign SAXISCCIXTXTDATA_in[20] = (SAXISCCIXTXTDATA[20] !== 1'bz) && SAXISCCIXTXTDATA_delay[20]; // rv 0 + assign SAXISCCIXTXTDATA_in[210] = (SAXISCCIXTXTDATA[210] !== 1'bz) && SAXISCCIXTXTDATA_delay[210]; // rv 0 + assign SAXISCCIXTXTDATA_in[211] = (SAXISCCIXTXTDATA[211] !== 1'bz) && SAXISCCIXTXTDATA_delay[211]; // rv 0 + assign SAXISCCIXTXTDATA_in[212] = (SAXISCCIXTXTDATA[212] !== 1'bz) && SAXISCCIXTXTDATA_delay[212]; // rv 0 + assign SAXISCCIXTXTDATA_in[213] = (SAXISCCIXTXTDATA[213] !== 1'bz) && SAXISCCIXTXTDATA_delay[213]; // rv 0 + assign SAXISCCIXTXTDATA_in[214] = (SAXISCCIXTXTDATA[214] !== 1'bz) && SAXISCCIXTXTDATA_delay[214]; // rv 0 + assign SAXISCCIXTXTDATA_in[215] = (SAXISCCIXTXTDATA[215] !== 1'bz) && SAXISCCIXTXTDATA_delay[215]; // rv 0 + assign SAXISCCIXTXTDATA_in[216] = (SAXISCCIXTXTDATA[216] !== 1'bz) && SAXISCCIXTXTDATA_delay[216]; // rv 0 + assign SAXISCCIXTXTDATA_in[217] = (SAXISCCIXTXTDATA[217] !== 1'bz) && SAXISCCIXTXTDATA_delay[217]; // rv 0 + assign SAXISCCIXTXTDATA_in[218] = (SAXISCCIXTXTDATA[218] !== 1'bz) && SAXISCCIXTXTDATA_delay[218]; // rv 0 + assign SAXISCCIXTXTDATA_in[219] = (SAXISCCIXTXTDATA[219] !== 1'bz) && SAXISCCIXTXTDATA_delay[219]; // rv 0 + assign SAXISCCIXTXTDATA_in[21] = (SAXISCCIXTXTDATA[21] !== 1'bz) && SAXISCCIXTXTDATA_delay[21]; // rv 0 + assign SAXISCCIXTXTDATA_in[220] = (SAXISCCIXTXTDATA[220] !== 1'bz) && SAXISCCIXTXTDATA_delay[220]; // rv 0 + assign SAXISCCIXTXTDATA_in[221] = (SAXISCCIXTXTDATA[221] !== 1'bz) && SAXISCCIXTXTDATA_delay[221]; // rv 0 + assign SAXISCCIXTXTDATA_in[222] = (SAXISCCIXTXTDATA[222] !== 1'bz) && SAXISCCIXTXTDATA_delay[222]; // rv 0 + assign SAXISCCIXTXTDATA_in[223] = (SAXISCCIXTXTDATA[223] !== 1'bz) && SAXISCCIXTXTDATA_delay[223]; // rv 0 + assign SAXISCCIXTXTDATA_in[224] = (SAXISCCIXTXTDATA[224] !== 1'bz) && SAXISCCIXTXTDATA_delay[224]; // rv 0 + assign SAXISCCIXTXTDATA_in[225] = (SAXISCCIXTXTDATA[225] !== 1'bz) && SAXISCCIXTXTDATA_delay[225]; // rv 0 + assign SAXISCCIXTXTDATA_in[226] = (SAXISCCIXTXTDATA[226] !== 1'bz) && SAXISCCIXTXTDATA_delay[226]; // rv 0 + assign SAXISCCIXTXTDATA_in[227] = (SAXISCCIXTXTDATA[227] !== 1'bz) && SAXISCCIXTXTDATA_delay[227]; // rv 0 + assign SAXISCCIXTXTDATA_in[228] = (SAXISCCIXTXTDATA[228] !== 1'bz) && SAXISCCIXTXTDATA_delay[228]; // rv 0 + assign SAXISCCIXTXTDATA_in[229] = (SAXISCCIXTXTDATA[229] !== 1'bz) && SAXISCCIXTXTDATA_delay[229]; // rv 0 + assign SAXISCCIXTXTDATA_in[22] = (SAXISCCIXTXTDATA[22] !== 1'bz) && SAXISCCIXTXTDATA_delay[22]; // rv 0 + assign SAXISCCIXTXTDATA_in[230] = (SAXISCCIXTXTDATA[230] !== 1'bz) && SAXISCCIXTXTDATA_delay[230]; // rv 0 + assign SAXISCCIXTXTDATA_in[231] = (SAXISCCIXTXTDATA[231] !== 1'bz) && SAXISCCIXTXTDATA_delay[231]; // rv 0 + assign SAXISCCIXTXTDATA_in[232] = (SAXISCCIXTXTDATA[232] !== 1'bz) && SAXISCCIXTXTDATA_delay[232]; // rv 0 + assign SAXISCCIXTXTDATA_in[233] = (SAXISCCIXTXTDATA[233] !== 1'bz) && SAXISCCIXTXTDATA_delay[233]; // rv 0 + assign SAXISCCIXTXTDATA_in[234] = (SAXISCCIXTXTDATA[234] !== 1'bz) && SAXISCCIXTXTDATA_delay[234]; // rv 0 + assign SAXISCCIXTXTDATA_in[235] = (SAXISCCIXTXTDATA[235] !== 1'bz) && SAXISCCIXTXTDATA_delay[235]; // rv 0 + assign SAXISCCIXTXTDATA_in[236] = (SAXISCCIXTXTDATA[236] !== 1'bz) && SAXISCCIXTXTDATA_delay[236]; // rv 0 + assign SAXISCCIXTXTDATA_in[237] = (SAXISCCIXTXTDATA[237] !== 1'bz) && SAXISCCIXTXTDATA_delay[237]; // rv 0 + assign SAXISCCIXTXTDATA_in[238] = (SAXISCCIXTXTDATA[238] !== 1'bz) && SAXISCCIXTXTDATA_delay[238]; // rv 0 + assign SAXISCCIXTXTDATA_in[239] = (SAXISCCIXTXTDATA[239] !== 1'bz) && SAXISCCIXTXTDATA_delay[239]; // rv 0 + assign SAXISCCIXTXTDATA_in[23] = (SAXISCCIXTXTDATA[23] !== 1'bz) && SAXISCCIXTXTDATA_delay[23]; // rv 0 + assign SAXISCCIXTXTDATA_in[240] = (SAXISCCIXTXTDATA[240] !== 1'bz) && SAXISCCIXTXTDATA_delay[240]; // rv 0 + assign SAXISCCIXTXTDATA_in[241] = (SAXISCCIXTXTDATA[241] !== 1'bz) && SAXISCCIXTXTDATA_delay[241]; // rv 0 + assign SAXISCCIXTXTDATA_in[242] = (SAXISCCIXTXTDATA[242] !== 1'bz) && SAXISCCIXTXTDATA_delay[242]; // rv 0 + assign SAXISCCIXTXTDATA_in[243] = (SAXISCCIXTXTDATA[243] !== 1'bz) && SAXISCCIXTXTDATA_delay[243]; // rv 0 + assign SAXISCCIXTXTDATA_in[244] = (SAXISCCIXTXTDATA[244] !== 1'bz) && SAXISCCIXTXTDATA_delay[244]; // rv 0 + assign SAXISCCIXTXTDATA_in[245] = (SAXISCCIXTXTDATA[245] !== 1'bz) && SAXISCCIXTXTDATA_delay[245]; // rv 0 + assign SAXISCCIXTXTDATA_in[246] = (SAXISCCIXTXTDATA[246] !== 1'bz) && SAXISCCIXTXTDATA_delay[246]; // rv 0 + assign SAXISCCIXTXTDATA_in[247] = (SAXISCCIXTXTDATA[247] !== 1'bz) && SAXISCCIXTXTDATA_delay[247]; // rv 0 + assign SAXISCCIXTXTDATA_in[248] = (SAXISCCIXTXTDATA[248] !== 1'bz) && SAXISCCIXTXTDATA_delay[248]; // rv 0 + assign SAXISCCIXTXTDATA_in[249] = (SAXISCCIXTXTDATA[249] !== 1'bz) && SAXISCCIXTXTDATA_delay[249]; // rv 0 + assign SAXISCCIXTXTDATA_in[24] = (SAXISCCIXTXTDATA[24] !== 1'bz) && SAXISCCIXTXTDATA_delay[24]; // rv 0 + assign SAXISCCIXTXTDATA_in[250] = (SAXISCCIXTXTDATA[250] !== 1'bz) && SAXISCCIXTXTDATA_delay[250]; // rv 0 + assign SAXISCCIXTXTDATA_in[251] = (SAXISCCIXTXTDATA[251] !== 1'bz) && SAXISCCIXTXTDATA_delay[251]; // rv 0 + assign SAXISCCIXTXTDATA_in[252] = (SAXISCCIXTXTDATA[252] !== 1'bz) && SAXISCCIXTXTDATA_delay[252]; // rv 0 + assign SAXISCCIXTXTDATA_in[253] = (SAXISCCIXTXTDATA[253] !== 1'bz) && SAXISCCIXTXTDATA_delay[253]; // rv 0 + assign SAXISCCIXTXTDATA_in[254] = (SAXISCCIXTXTDATA[254] !== 1'bz) && SAXISCCIXTXTDATA_delay[254]; // rv 0 + assign SAXISCCIXTXTDATA_in[255] = (SAXISCCIXTXTDATA[255] !== 1'bz) && SAXISCCIXTXTDATA_delay[255]; // rv 0 + assign SAXISCCIXTXTDATA_in[25] = (SAXISCCIXTXTDATA[25] !== 1'bz) && SAXISCCIXTXTDATA_delay[25]; // rv 0 + assign SAXISCCIXTXTDATA_in[26] = (SAXISCCIXTXTDATA[26] !== 1'bz) && SAXISCCIXTXTDATA_delay[26]; // rv 0 + assign SAXISCCIXTXTDATA_in[27] = (SAXISCCIXTXTDATA[27] !== 1'bz) && SAXISCCIXTXTDATA_delay[27]; // rv 0 + assign SAXISCCIXTXTDATA_in[28] = (SAXISCCIXTXTDATA[28] !== 1'bz) && SAXISCCIXTXTDATA_delay[28]; // rv 0 + assign SAXISCCIXTXTDATA_in[29] = (SAXISCCIXTXTDATA[29] !== 1'bz) && SAXISCCIXTXTDATA_delay[29]; // rv 0 + assign SAXISCCIXTXTDATA_in[2] = (SAXISCCIXTXTDATA[2] !== 1'bz) && SAXISCCIXTXTDATA_delay[2]; // rv 0 + assign SAXISCCIXTXTDATA_in[30] = (SAXISCCIXTXTDATA[30] !== 1'bz) && SAXISCCIXTXTDATA_delay[30]; // rv 0 + assign SAXISCCIXTXTDATA_in[31] = (SAXISCCIXTXTDATA[31] !== 1'bz) && SAXISCCIXTXTDATA_delay[31]; // rv 0 + assign SAXISCCIXTXTDATA_in[32] = (SAXISCCIXTXTDATA[32] !== 1'bz) && SAXISCCIXTXTDATA_delay[32]; // rv 0 + assign SAXISCCIXTXTDATA_in[33] = (SAXISCCIXTXTDATA[33] !== 1'bz) && SAXISCCIXTXTDATA_delay[33]; // rv 0 + assign SAXISCCIXTXTDATA_in[34] = (SAXISCCIXTXTDATA[34] !== 1'bz) && SAXISCCIXTXTDATA_delay[34]; // rv 0 + assign SAXISCCIXTXTDATA_in[35] = (SAXISCCIXTXTDATA[35] !== 1'bz) && SAXISCCIXTXTDATA_delay[35]; // rv 0 + assign SAXISCCIXTXTDATA_in[36] = (SAXISCCIXTXTDATA[36] !== 1'bz) && SAXISCCIXTXTDATA_delay[36]; // rv 0 + assign SAXISCCIXTXTDATA_in[37] = (SAXISCCIXTXTDATA[37] !== 1'bz) && SAXISCCIXTXTDATA_delay[37]; // rv 0 + assign SAXISCCIXTXTDATA_in[38] = (SAXISCCIXTXTDATA[38] !== 1'bz) && SAXISCCIXTXTDATA_delay[38]; // rv 0 + assign SAXISCCIXTXTDATA_in[39] = (SAXISCCIXTXTDATA[39] !== 1'bz) && SAXISCCIXTXTDATA_delay[39]; // rv 0 + assign SAXISCCIXTXTDATA_in[3] = (SAXISCCIXTXTDATA[3] !== 1'bz) && SAXISCCIXTXTDATA_delay[3]; // rv 0 + assign SAXISCCIXTXTDATA_in[40] = (SAXISCCIXTXTDATA[40] !== 1'bz) && SAXISCCIXTXTDATA_delay[40]; // rv 0 + assign SAXISCCIXTXTDATA_in[41] = (SAXISCCIXTXTDATA[41] !== 1'bz) && SAXISCCIXTXTDATA_delay[41]; // rv 0 + assign SAXISCCIXTXTDATA_in[42] = (SAXISCCIXTXTDATA[42] !== 1'bz) && SAXISCCIXTXTDATA_delay[42]; // rv 0 + assign SAXISCCIXTXTDATA_in[43] = (SAXISCCIXTXTDATA[43] !== 1'bz) && SAXISCCIXTXTDATA_delay[43]; // rv 0 + assign SAXISCCIXTXTDATA_in[44] = (SAXISCCIXTXTDATA[44] !== 1'bz) && SAXISCCIXTXTDATA_delay[44]; // rv 0 + assign SAXISCCIXTXTDATA_in[45] = (SAXISCCIXTXTDATA[45] !== 1'bz) && SAXISCCIXTXTDATA_delay[45]; // rv 0 + assign SAXISCCIXTXTDATA_in[46] = (SAXISCCIXTXTDATA[46] !== 1'bz) && SAXISCCIXTXTDATA_delay[46]; // rv 0 + assign SAXISCCIXTXTDATA_in[47] = (SAXISCCIXTXTDATA[47] !== 1'bz) && SAXISCCIXTXTDATA_delay[47]; // rv 0 + assign SAXISCCIXTXTDATA_in[48] = (SAXISCCIXTXTDATA[48] !== 1'bz) && SAXISCCIXTXTDATA_delay[48]; // rv 0 + assign SAXISCCIXTXTDATA_in[49] = (SAXISCCIXTXTDATA[49] !== 1'bz) && SAXISCCIXTXTDATA_delay[49]; // rv 0 + assign SAXISCCIXTXTDATA_in[4] = (SAXISCCIXTXTDATA[4] !== 1'bz) && SAXISCCIXTXTDATA_delay[4]; // rv 0 + assign SAXISCCIXTXTDATA_in[50] = (SAXISCCIXTXTDATA[50] !== 1'bz) && SAXISCCIXTXTDATA_delay[50]; // rv 0 + assign SAXISCCIXTXTDATA_in[51] = (SAXISCCIXTXTDATA[51] !== 1'bz) && SAXISCCIXTXTDATA_delay[51]; // rv 0 + assign SAXISCCIXTXTDATA_in[52] = (SAXISCCIXTXTDATA[52] !== 1'bz) && SAXISCCIXTXTDATA_delay[52]; // rv 0 + assign SAXISCCIXTXTDATA_in[53] = (SAXISCCIXTXTDATA[53] !== 1'bz) && SAXISCCIXTXTDATA_delay[53]; // rv 0 + assign SAXISCCIXTXTDATA_in[54] = (SAXISCCIXTXTDATA[54] !== 1'bz) && SAXISCCIXTXTDATA_delay[54]; // rv 0 + assign SAXISCCIXTXTDATA_in[55] = (SAXISCCIXTXTDATA[55] !== 1'bz) && SAXISCCIXTXTDATA_delay[55]; // rv 0 + assign SAXISCCIXTXTDATA_in[56] = (SAXISCCIXTXTDATA[56] !== 1'bz) && SAXISCCIXTXTDATA_delay[56]; // rv 0 + assign SAXISCCIXTXTDATA_in[57] = (SAXISCCIXTXTDATA[57] !== 1'bz) && SAXISCCIXTXTDATA_delay[57]; // rv 0 + assign SAXISCCIXTXTDATA_in[58] = (SAXISCCIXTXTDATA[58] !== 1'bz) && SAXISCCIXTXTDATA_delay[58]; // rv 0 + assign SAXISCCIXTXTDATA_in[59] = (SAXISCCIXTXTDATA[59] !== 1'bz) && SAXISCCIXTXTDATA_delay[59]; // rv 0 + assign SAXISCCIXTXTDATA_in[5] = (SAXISCCIXTXTDATA[5] !== 1'bz) && SAXISCCIXTXTDATA_delay[5]; // rv 0 + assign SAXISCCIXTXTDATA_in[60] = (SAXISCCIXTXTDATA[60] !== 1'bz) && SAXISCCIXTXTDATA_delay[60]; // rv 0 + assign SAXISCCIXTXTDATA_in[61] = (SAXISCCIXTXTDATA[61] !== 1'bz) && SAXISCCIXTXTDATA_delay[61]; // rv 0 + assign SAXISCCIXTXTDATA_in[62] = (SAXISCCIXTXTDATA[62] !== 1'bz) && SAXISCCIXTXTDATA_delay[62]; // rv 0 + assign SAXISCCIXTXTDATA_in[63] = (SAXISCCIXTXTDATA[63] !== 1'bz) && SAXISCCIXTXTDATA_delay[63]; // rv 0 + assign SAXISCCIXTXTDATA_in[64] = (SAXISCCIXTXTDATA[64] !== 1'bz) && SAXISCCIXTXTDATA_delay[64]; // rv 0 + assign SAXISCCIXTXTDATA_in[65] = (SAXISCCIXTXTDATA[65] !== 1'bz) && SAXISCCIXTXTDATA_delay[65]; // rv 0 + assign SAXISCCIXTXTDATA_in[66] = (SAXISCCIXTXTDATA[66] !== 1'bz) && SAXISCCIXTXTDATA_delay[66]; // rv 0 + assign SAXISCCIXTXTDATA_in[67] = (SAXISCCIXTXTDATA[67] !== 1'bz) && SAXISCCIXTXTDATA_delay[67]; // rv 0 + assign SAXISCCIXTXTDATA_in[68] = (SAXISCCIXTXTDATA[68] !== 1'bz) && SAXISCCIXTXTDATA_delay[68]; // rv 0 + assign SAXISCCIXTXTDATA_in[69] = (SAXISCCIXTXTDATA[69] !== 1'bz) && SAXISCCIXTXTDATA_delay[69]; // rv 0 + assign SAXISCCIXTXTDATA_in[6] = (SAXISCCIXTXTDATA[6] !== 1'bz) && SAXISCCIXTXTDATA_delay[6]; // rv 0 + assign SAXISCCIXTXTDATA_in[70] = (SAXISCCIXTXTDATA[70] !== 1'bz) && SAXISCCIXTXTDATA_delay[70]; // rv 0 + assign SAXISCCIXTXTDATA_in[71] = (SAXISCCIXTXTDATA[71] !== 1'bz) && SAXISCCIXTXTDATA_delay[71]; // rv 0 + assign SAXISCCIXTXTDATA_in[72] = (SAXISCCIXTXTDATA[72] !== 1'bz) && SAXISCCIXTXTDATA_delay[72]; // rv 0 + assign SAXISCCIXTXTDATA_in[73] = (SAXISCCIXTXTDATA[73] !== 1'bz) && SAXISCCIXTXTDATA_delay[73]; // rv 0 + assign SAXISCCIXTXTDATA_in[74] = (SAXISCCIXTXTDATA[74] !== 1'bz) && SAXISCCIXTXTDATA_delay[74]; // rv 0 + assign SAXISCCIXTXTDATA_in[75] = (SAXISCCIXTXTDATA[75] !== 1'bz) && SAXISCCIXTXTDATA_delay[75]; // rv 0 + assign SAXISCCIXTXTDATA_in[76] = (SAXISCCIXTXTDATA[76] !== 1'bz) && SAXISCCIXTXTDATA_delay[76]; // rv 0 + assign SAXISCCIXTXTDATA_in[77] = (SAXISCCIXTXTDATA[77] !== 1'bz) && SAXISCCIXTXTDATA_delay[77]; // rv 0 + assign SAXISCCIXTXTDATA_in[78] = (SAXISCCIXTXTDATA[78] !== 1'bz) && SAXISCCIXTXTDATA_delay[78]; // rv 0 + assign SAXISCCIXTXTDATA_in[79] = (SAXISCCIXTXTDATA[79] !== 1'bz) && SAXISCCIXTXTDATA_delay[79]; // rv 0 + assign SAXISCCIXTXTDATA_in[7] = (SAXISCCIXTXTDATA[7] !== 1'bz) && SAXISCCIXTXTDATA_delay[7]; // rv 0 + assign SAXISCCIXTXTDATA_in[80] = (SAXISCCIXTXTDATA[80] !== 1'bz) && SAXISCCIXTXTDATA_delay[80]; // rv 0 + assign SAXISCCIXTXTDATA_in[81] = (SAXISCCIXTXTDATA[81] !== 1'bz) && SAXISCCIXTXTDATA_delay[81]; // rv 0 + assign SAXISCCIXTXTDATA_in[82] = (SAXISCCIXTXTDATA[82] !== 1'bz) && SAXISCCIXTXTDATA_delay[82]; // rv 0 + assign SAXISCCIXTXTDATA_in[83] = (SAXISCCIXTXTDATA[83] !== 1'bz) && SAXISCCIXTXTDATA_delay[83]; // rv 0 + assign SAXISCCIXTXTDATA_in[84] = (SAXISCCIXTXTDATA[84] !== 1'bz) && SAXISCCIXTXTDATA_delay[84]; // rv 0 + assign SAXISCCIXTXTDATA_in[85] = (SAXISCCIXTXTDATA[85] !== 1'bz) && SAXISCCIXTXTDATA_delay[85]; // rv 0 + assign SAXISCCIXTXTDATA_in[86] = (SAXISCCIXTXTDATA[86] !== 1'bz) && SAXISCCIXTXTDATA_delay[86]; // rv 0 + assign SAXISCCIXTXTDATA_in[87] = (SAXISCCIXTXTDATA[87] !== 1'bz) && SAXISCCIXTXTDATA_delay[87]; // rv 0 + assign SAXISCCIXTXTDATA_in[88] = (SAXISCCIXTXTDATA[88] !== 1'bz) && SAXISCCIXTXTDATA_delay[88]; // rv 0 + assign SAXISCCIXTXTDATA_in[89] = (SAXISCCIXTXTDATA[89] !== 1'bz) && SAXISCCIXTXTDATA_delay[89]; // rv 0 + assign SAXISCCIXTXTDATA_in[8] = (SAXISCCIXTXTDATA[8] !== 1'bz) && SAXISCCIXTXTDATA_delay[8]; // rv 0 + assign SAXISCCIXTXTDATA_in[90] = (SAXISCCIXTXTDATA[90] !== 1'bz) && SAXISCCIXTXTDATA_delay[90]; // rv 0 + assign SAXISCCIXTXTDATA_in[91] = (SAXISCCIXTXTDATA[91] !== 1'bz) && SAXISCCIXTXTDATA_delay[91]; // rv 0 + assign SAXISCCIXTXTDATA_in[92] = (SAXISCCIXTXTDATA[92] !== 1'bz) && SAXISCCIXTXTDATA_delay[92]; // rv 0 + assign SAXISCCIXTXTDATA_in[93] = (SAXISCCIXTXTDATA[93] !== 1'bz) && SAXISCCIXTXTDATA_delay[93]; // rv 0 + assign SAXISCCIXTXTDATA_in[94] = (SAXISCCIXTXTDATA[94] !== 1'bz) && SAXISCCIXTXTDATA_delay[94]; // rv 0 + assign SAXISCCIXTXTDATA_in[95] = (SAXISCCIXTXTDATA[95] !== 1'bz) && SAXISCCIXTXTDATA_delay[95]; // rv 0 + assign SAXISCCIXTXTDATA_in[96] = (SAXISCCIXTXTDATA[96] !== 1'bz) && SAXISCCIXTXTDATA_delay[96]; // rv 0 + assign SAXISCCIXTXTDATA_in[97] = (SAXISCCIXTXTDATA[97] !== 1'bz) && SAXISCCIXTXTDATA_delay[97]; // rv 0 + assign SAXISCCIXTXTDATA_in[98] = (SAXISCCIXTXTDATA[98] !== 1'bz) && SAXISCCIXTXTDATA_delay[98]; // rv 0 + assign SAXISCCIXTXTDATA_in[99] = (SAXISCCIXTXTDATA[99] !== 1'bz) && SAXISCCIXTXTDATA_delay[99]; // rv 0 + assign SAXISCCIXTXTDATA_in[9] = (SAXISCCIXTXTDATA[9] !== 1'bz) && SAXISCCIXTXTDATA_delay[9]; // rv 0 + assign SAXISCCIXTXTUSER_in[0] = (SAXISCCIXTXTUSER[0] !== 1'bz) && SAXISCCIXTXTUSER_delay[0]; // rv 0 + assign SAXISCCIXTXTUSER_in[10] = (SAXISCCIXTXTUSER[10] !== 1'bz) && SAXISCCIXTXTUSER_delay[10]; // rv 0 + assign SAXISCCIXTXTUSER_in[11] = (SAXISCCIXTXTUSER[11] !== 1'bz) && SAXISCCIXTXTUSER_delay[11]; // rv 0 + assign SAXISCCIXTXTUSER_in[12] = (SAXISCCIXTXTUSER[12] !== 1'bz) && SAXISCCIXTXTUSER_delay[12]; // rv 0 + assign SAXISCCIXTXTUSER_in[13] = (SAXISCCIXTXTUSER[13] !== 1'bz) && SAXISCCIXTXTUSER_delay[13]; // rv 0 + assign SAXISCCIXTXTUSER_in[14] = (SAXISCCIXTXTUSER[14] !== 1'bz) && SAXISCCIXTXTUSER_delay[14]; // rv 0 + assign SAXISCCIXTXTUSER_in[15] = (SAXISCCIXTXTUSER[15] !== 1'bz) && SAXISCCIXTXTUSER_delay[15]; // rv 0 + assign SAXISCCIXTXTUSER_in[16] = (SAXISCCIXTXTUSER[16] !== 1'bz) && SAXISCCIXTXTUSER_delay[16]; // rv 0 + assign SAXISCCIXTXTUSER_in[17] = (SAXISCCIXTXTUSER[17] !== 1'bz) && SAXISCCIXTXTUSER_delay[17]; // rv 0 + assign SAXISCCIXTXTUSER_in[18] = (SAXISCCIXTXTUSER[18] !== 1'bz) && SAXISCCIXTXTUSER_delay[18]; // rv 0 + assign SAXISCCIXTXTUSER_in[19] = (SAXISCCIXTXTUSER[19] !== 1'bz) && SAXISCCIXTXTUSER_delay[19]; // rv 0 + assign SAXISCCIXTXTUSER_in[1] = (SAXISCCIXTXTUSER[1] !== 1'bz) && SAXISCCIXTXTUSER_delay[1]; // rv 0 + assign SAXISCCIXTXTUSER_in[20] = (SAXISCCIXTXTUSER[20] !== 1'bz) && SAXISCCIXTXTUSER_delay[20]; // rv 0 + assign SAXISCCIXTXTUSER_in[21] = (SAXISCCIXTXTUSER[21] !== 1'bz) && SAXISCCIXTXTUSER_delay[21]; // rv 0 + assign SAXISCCIXTXTUSER_in[22] = (SAXISCCIXTXTUSER[22] !== 1'bz) && SAXISCCIXTXTUSER_delay[22]; // rv 0 + assign SAXISCCIXTXTUSER_in[23] = (SAXISCCIXTXTUSER[23] !== 1'bz) && SAXISCCIXTXTUSER_delay[23]; // rv 0 + assign SAXISCCIXTXTUSER_in[24] = (SAXISCCIXTXTUSER[24] !== 1'bz) && SAXISCCIXTXTUSER_delay[24]; // rv 0 + assign SAXISCCIXTXTUSER_in[25] = (SAXISCCIXTXTUSER[25] !== 1'bz) && SAXISCCIXTXTUSER_delay[25]; // rv 0 + assign SAXISCCIXTXTUSER_in[26] = (SAXISCCIXTXTUSER[26] !== 1'bz) && SAXISCCIXTXTUSER_delay[26]; // rv 0 + assign SAXISCCIXTXTUSER_in[27] = (SAXISCCIXTXTUSER[27] !== 1'bz) && SAXISCCIXTXTUSER_delay[27]; // rv 0 + assign SAXISCCIXTXTUSER_in[28] = (SAXISCCIXTXTUSER[28] !== 1'bz) && SAXISCCIXTXTUSER_delay[28]; // rv 0 + assign SAXISCCIXTXTUSER_in[29] = (SAXISCCIXTXTUSER[29] !== 1'bz) && SAXISCCIXTXTUSER_delay[29]; // rv 0 + assign SAXISCCIXTXTUSER_in[2] = (SAXISCCIXTXTUSER[2] !== 1'bz) && SAXISCCIXTXTUSER_delay[2]; // rv 0 + assign SAXISCCIXTXTUSER_in[30] = (SAXISCCIXTXTUSER[30] !== 1'bz) && SAXISCCIXTXTUSER_delay[30]; // rv 0 + assign SAXISCCIXTXTUSER_in[31] = (SAXISCCIXTXTUSER[31] !== 1'bz) && SAXISCCIXTXTUSER_delay[31]; // rv 0 + assign SAXISCCIXTXTUSER_in[32] = (SAXISCCIXTXTUSER[32] !== 1'bz) && SAXISCCIXTXTUSER_delay[32]; // rv 0 + assign SAXISCCIXTXTUSER_in[33] = (SAXISCCIXTXTUSER[33] !== 1'bz) && SAXISCCIXTXTUSER_delay[33]; // rv 0 + assign SAXISCCIXTXTUSER_in[34] = (SAXISCCIXTXTUSER[34] !== 1'bz) && SAXISCCIXTXTUSER_delay[34]; // rv 0 + assign SAXISCCIXTXTUSER_in[35] = (SAXISCCIXTXTUSER[35] !== 1'bz) && SAXISCCIXTXTUSER_delay[35]; // rv 0 + assign SAXISCCIXTXTUSER_in[36] = (SAXISCCIXTXTUSER[36] !== 1'bz) && SAXISCCIXTXTUSER_delay[36]; // rv 0 + assign SAXISCCIXTXTUSER_in[37] = (SAXISCCIXTXTUSER[37] !== 1'bz) && SAXISCCIXTXTUSER_delay[37]; // rv 0 + assign SAXISCCIXTXTUSER_in[38] = (SAXISCCIXTXTUSER[38] !== 1'bz) && SAXISCCIXTXTUSER_delay[38]; // rv 0 + assign SAXISCCIXTXTUSER_in[39] = (SAXISCCIXTXTUSER[39] !== 1'bz) && SAXISCCIXTXTUSER_delay[39]; // rv 0 + assign SAXISCCIXTXTUSER_in[3] = (SAXISCCIXTXTUSER[3] !== 1'bz) && SAXISCCIXTXTUSER_delay[3]; // rv 0 + assign SAXISCCIXTXTUSER_in[40] = (SAXISCCIXTXTUSER[40] !== 1'bz) && SAXISCCIXTXTUSER_delay[40]; // rv 0 + assign SAXISCCIXTXTUSER_in[41] = (SAXISCCIXTXTUSER[41] !== 1'bz) && SAXISCCIXTXTUSER_delay[41]; // rv 0 + assign SAXISCCIXTXTUSER_in[42] = (SAXISCCIXTXTUSER[42] !== 1'bz) && SAXISCCIXTXTUSER_delay[42]; // rv 0 + assign SAXISCCIXTXTUSER_in[43] = (SAXISCCIXTXTUSER[43] !== 1'bz) && SAXISCCIXTXTUSER_delay[43]; // rv 0 + assign SAXISCCIXTXTUSER_in[44] = (SAXISCCIXTXTUSER[44] !== 1'bz) && SAXISCCIXTXTUSER_delay[44]; // rv 0 + assign SAXISCCIXTXTUSER_in[45] = (SAXISCCIXTXTUSER[45] !== 1'bz) && SAXISCCIXTXTUSER_delay[45]; // rv 0 + assign SAXISCCIXTXTUSER_in[4] = (SAXISCCIXTXTUSER[4] !== 1'bz) && SAXISCCIXTXTUSER_delay[4]; // rv 0 + assign SAXISCCIXTXTUSER_in[5] = (SAXISCCIXTXTUSER[5] !== 1'bz) && SAXISCCIXTXTUSER_delay[5]; // rv 0 + assign SAXISCCIXTXTUSER_in[6] = (SAXISCCIXTXTUSER[6] !== 1'bz) && SAXISCCIXTXTUSER_delay[6]; // rv 0 + assign SAXISCCIXTXTUSER_in[7] = (SAXISCCIXTXTUSER[7] !== 1'bz) && SAXISCCIXTXTUSER_delay[7]; // rv 0 + assign SAXISCCIXTXTUSER_in[8] = (SAXISCCIXTXTUSER[8] !== 1'bz) && SAXISCCIXTXTUSER_delay[8]; // rv 0 + assign SAXISCCIXTXTUSER_in[9] = (SAXISCCIXTXTUSER[9] !== 1'bz) && SAXISCCIXTXTUSER_delay[9]; // rv 0 + assign SAXISCCIXTXTVALID_in = (SAXISCCIXTXTVALID !== 1'bz) && SAXISCCIXTXTVALID_delay; // rv 0 + assign SAXISCCTDATA_in[0] = (SAXISCCTDATA[0] === 1'bz) || SAXISCCTDATA_delay[0]; // rv 1 + assign SAXISCCTDATA_in[100] = (SAXISCCTDATA[100] === 1'bz) || SAXISCCTDATA_delay[100]; // rv 1 + assign SAXISCCTDATA_in[101] = (SAXISCCTDATA[101] === 1'bz) || SAXISCCTDATA_delay[101]; // rv 1 + assign SAXISCCTDATA_in[102] = (SAXISCCTDATA[102] === 1'bz) || SAXISCCTDATA_delay[102]; // rv 1 + assign SAXISCCTDATA_in[103] = (SAXISCCTDATA[103] === 1'bz) || SAXISCCTDATA_delay[103]; // rv 1 + assign SAXISCCTDATA_in[104] = (SAXISCCTDATA[104] === 1'bz) || SAXISCCTDATA_delay[104]; // rv 1 + assign SAXISCCTDATA_in[105] = (SAXISCCTDATA[105] === 1'bz) || SAXISCCTDATA_delay[105]; // rv 1 + assign SAXISCCTDATA_in[106] = (SAXISCCTDATA[106] === 1'bz) || SAXISCCTDATA_delay[106]; // rv 1 + assign SAXISCCTDATA_in[107] = (SAXISCCTDATA[107] === 1'bz) || SAXISCCTDATA_delay[107]; // rv 1 + assign SAXISCCTDATA_in[108] = (SAXISCCTDATA[108] === 1'bz) || SAXISCCTDATA_delay[108]; // rv 1 + assign SAXISCCTDATA_in[109] = (SAXISCCTDATA[109] === 1'bz) || SAXISCCTDATA_delay[109]; // rv 1 + assign SAXISCCTDATA_in[10] = (SAXISCCTDATA[10] === 1'bz) || SAXISCCTDATA_delay[10]; // rv 1 + assign SAXISCCTDATA_in[110] = (SAXISCCTDATA[110] === 1'bz) || SAXISCCTDATA_delay[110]; // rv 1 + assign SAXISCCTDATA_in[111] = (SAXISCCTDATA[111] === 1'bz) || SAXISCCTDATA_delay[111]; // rv 1 + assign SAXISCCTDATA_in[112] = (SAXISCCTDATA[112] === 1'bz) || SAXISCCTDATA_delay[112]; // rv 1 + assign SAXISCCTDATA_in[113] = (SAXISCCTDATA[113] === 1'bz) || SAXISCCTDATA_delay[113]; // rv 1 + assign SAXISCCTDATA_in[114] = (SAXISCCTDATA[114] === 1'bz) || SAXISCCTDATA_delay[114]; // rv 1 + assign SAXISCCTDATA_in[115] = (SAXISCCTDATA[115] === 1'bz) || SAXISCCTDATA_delay[115]; // rv 1 + assign SAXISCCTDATA_in[116] = (SAXISCCTDATA[116] === 1'bz) || SAXISCCTDATA_delay[116]; // rv 1 + assign SAXISCCTDATA_in[117] = (SAXISCCTDATA[117] === 1'bz) || SAXISCCTDATA_delay[117]; // rv 1 + assign SAXISCCTDATA_in[118] = (SAXISCCTDATA[118] === 1'bz) || SAXISCCTDATA_delay[118]; // rv 1 + assign SAXISCCTDATA_in[119] = (SAXISCCTDATA[119] === 1'bz) || SAXISCCTDATA_delay[119]; // rv 1 + assign SAXISCCTDATA_in[11] = (SAXISCCTDATA[11] === 1'bz) || SAXISCCTDATA_delay[11]; // rv 1 + assign SAXISCCTDATA_in[120] = (SAXISCCTDATA[120] === 1'bz) || SAXISCCTDATA_delay[120]; // rv 1 + assign SAXISCCTDATA_in[121] = (SAXISCCTDATA[121] === 1'bz) || SAXISCCTDATA_delay[121]; // rv 1 + assign SAXISCCTDATA_in[122] = (SAXISCCTDATA[122] === 1'bz) || SAXISCCTDATA_delay[122]; // rv 1 + assign SAXISCCTDATA_in[123] = (SAXISCCTDATA[123] === 1'bz) || SAXISCCTDATA_delay[123]; // rv 1 + assign SAXISCCTDATA_in[124] = (SAXISCCTDATA[124] === 1'bz) || SAXISCCTDATA_delay[124]; // rv 1 + assign SAXISCCTDATA_in[125] = (SAXISCCTDATA[125] === 1'bz) || SAXISCCTDATA_delay[125]; // rv 1 + assign SAXISCCTDATA_in[126] = (SAXISCCTDATA[126] === 1'bz) || SAXISCCTDATA_delay[126]; // rv 1 + assign SAXISCCTDATA_in[127] = (SAXISCCTDATA[127] === 1'bz) || SAXISCCTDATA_delay[127]; // rv 1 + assign SAXISCCTDATA_in[128] = (SAXISCCTDATA[128] === 1'bz) || SAXISCCTDATA_delay[128]; // rv 1 + assign SAXISCCTDATA_in[129] = (SAXISCCTDATA[129] === 1'bz) || SAXISCCTDATA_delay[129]; // rv 1 + assign SAXISCCTDATA_in[12] = (SAXISCCTDATA[12] === 1'bz) || SAXISCCTDATA_delay[12]; // rv 1 + assign SAXISCCTDATA_in[130] = (SAXISCCTDATA[130] === 1'bz) || SAXISCCTDATA_delay[130]; // rv 1 + assign SAXISCCTDATA_in[131] = (SAXISCCTDATA[131] === 1'bz) || SAXISCCTDATA_delay[131]; // rv 1 + assign SAXISCCTDATA_in[132] = (SAXISCCTDATA[132] === 1'bz) || SAXISCCTDATA_delay[132]; // rv 1 + assign SAXISCCTDATA_in[133] = (SAXISCCTDATA[133] === 1'bz) || SAXISCCTDATA_delay[133]; // rv 1 + assign SAXISCCTDATA_in[134] = (SAXISCCTDATA[134] === 1'bz) || SAXISCCTDATA_delay[134]; // rv 1 + assign SAXISCCTDATA_in[135] = (SAXISCCTDATA[135] === 1'bz) || SAXISCCTDATA_delay[135]; // rv 1 + assign SAXISCCTDATA_in[136] = (SAXISCCTDATA[136] === 1'bz) || SAXISCCTDATA_delay[136]; // rv 1 + assign SAXISCCTDATA_in[137] = (SAXISCCTDATA[137] === 1'bz) || SAXISCCTDATA_delay[137]; // rv 1 + assign SAXISCCTDATA_in[138] = (SAXISCCTDATA[138] === 1'bz) || SAXISCCTDATA_delay[138]; // rv 1 + assign SAXISCCTDATA_in[139] = (SAXISCCTDATA[139] === 1'bz) || SAXISCCTDATA_delay[139]; // rv 1 + assign SAXISCCTDATA_in[13] = (SAXISCCTDATA[13] === 1'bz) || SAXISCCTDATA_delay[13]; // rv 1 + assign SAXISCCTDATA_in[140] = (SAXISCCTDATA[140] === 1'bz) || SAXISCCTDATA_delay[140]; // rv 1 + assign SAXISCCTDATA_in[141] = (SAXISCCTDATA[141] === 1'bz) || SAXISCCTDATA_delay[141]; // rv 1 + assign SAXISCCTDATA_in[142] = (SAXISCCTDATA[142] === 1'bz) || SAXISCCTDATA_delay[142]; // rv 1 + assign SAXISCCTDATA_in[143] = (SAXISCCTDATA[143] === 1'bz) || SAXISCCTDATA_delay[143]; // rv 1 + assign SAXISCCTDATA_in[144] = (SAXISCCTDATA[144] === 1'bz) || SAXISCCTDATA_delay[144]; // rv 1 + assign SAXISCCTDATA_in[145] = (SAXISCCTDATA[145] === 1'bz) || SAXISCCTDATA_delay[145]; // rv 1 + assign SAXISCCTDATA_in[146] = (SAXISCCTDATA[146] === 1'bz) || SAXISCCTDATA_delay[146]; // rv 1 + assign SAXISCCTDATA_in[147] = (SAXISCCTDATA[147] === 1'bz) || SAXISCCTDATA_delay[147]; // rv 1 + assign SAXISCCTDATA_in[148] = (SAXISCCTDATA[148] === 1'bz) || SAXISCCTDATA_delay[148]; // rv 1 + assign SAXISCCTDATA_in[149] = (SAXISCCTDATA[149] === 1'bz) || SAXISCCTDATA_delay[149]; // rv 1 + assign SAXISCCTDATA_in[14] = (SAXISCCTDATA[14] === 1'bz) || SAXISCCTDATA_delay[14]; // rv 1 + assign SAXISCCTDATA_in[150] = (SAXISCCTDATA[150] === 1'bz) || SAXISCCTDATA_delay[150]; // rv 1 + assign SAXISCCTDATA_in[151] = (SAXISCCTDATA[151] === 1'bz) || SAXISCCTDATA_delay[151]; // rv 1 + assign SAXISCCTDATA_in[152] = (SAXISCCTDATA[152] === 1'bz) || SAXISCCTDATA_delay[152]; // rv 1 + assign SAXISCCTDATA_in[153] = (SAXISCCTDATA[153] === 1'bz) || SAXISCCTDATA_delay[153]; // rv 1 + assign SAXISCCTDATA_in[154] = (SAXISCCTDATA[154] === 1'bz) || SAXISCCTDATA_delay[154]; // rv 1 + assign SAXISCCTDATA_in[155] = (SAXISCCTDATA[155] === 1'bz) || SAXISCCTDATA_delay[155]; // rv 1 + assign SAXISCCTDATA_in[156] = (SAXISCCTDATA[156] === 1'bz) || SAXISCCTDATA_delay[156]; // rv 1 + assign SAXISCCTDATA_in[157] = (SAXISCCTDATA[157] === 1'bz) || SAXISCCTDATA_delay[157]; // rv 1 + assign SAXISCCTDATA_in[158] = (SAXISCCTDATA[158] === 1'bz) || SAXISCCTDATA_delay[158]; // rv 1 + assign SAXISCCTDATA_in[159] = (SAXISCCTDATA[159] === 1'bz) || SAXISCCTDATA_delay[159]; // rv 1 + assign SAXISCCTDATA_in[15] = (SAXISCCTDATA[15] === 1'bz) || SAXISCCTDATA_delay[15]; // rv 1 + assign SAXISCCTDATA_in[160] = (SAXISCCTDATA[160] === 1'bz) || SAXISCCTDATA_delay[160]; // rv 1 + assign SAXISCCTDATA_in[161] = (SAXISCCTDATA[161] === 1'bz) || SAXISCCTDATA_delay[161]; // rv 1 + assign SAXISCCTDATA_in[162] = (SAXISCCTDATA[162] === 1'bz) || SAXISCCTDATA_delay[162]; // rv 1 + assign SAXISCCTDATA_in[163] = (SAXISCCTDATA[163] === 1'bz) || SAXISCCTDATA_delay[163]; // rv 1 + assign SAXISCCTDATA_in[164] = (SAXISCCTDATA[164] === 1'bz) || SAXISCCTDATA_delay[164]; // rv 1 + assign SAXISCCTDATA_in[165] = (SAXISCCTDATA[165] === 1'bz) || SAXISCCTDATA_delay[165]; // rv 1 + assign SAXISCCTDATA_in[166] = (SAXISCCTDATA[166] === 1'bz) || SAXISCCTDATA_delay[166]; // rv 1 + assign SAXISCCTDATA_in[167] = (SAXISCCTDATA[167] === 1'bz) || SAXISCCTDATA_delay[167]; // rv 1 + assign SAXISCCTDATA_in[168] = (SAXISCCTDATA[168] === 1'bz) || SAXISCCTDATA_delay[168]; // rv 1 + assign SAXISCCTDATA_in[169] = (SAXISCCTDATA[169] === 1'bz) || SAXISCCTDATA_delay[169]; // rv 1 + assign SAXISCCTDATA_in[16] = (SAXISCCTDATA[16] === 1'bz) || SAXISCCTDATA_delay[16]; // rv 1 + assign SAXISCCTDATA_in[170] = (SAXISCCTDATA[170] === 1'bz) || SAXISCCTDATA_delay[170]; // rv 1 + assign SAXISCCTDATA_in[171] = (SAXISCCTDATA[171] === 1'bz) || SAXISCCTDATA_delay[171]; // rv 1 + assign SAXISCCTDATA_in[172] = (SAXISCCTDATA[172] === 1'bz) || SAXISCCTDATA_delay[172]; // rv 1 + assign SAXISCCTDATA_in[173] = (SAXISCCTDATA[173] === 1'bz) || SAXISCCTDATA_delay[173]; // rv 1 + assign SAXISCCTDATA_in[174] = (SAXISCCTDATA[174] === 1'bz) || SAXISCCTDATA_delay[174]; // rv 1 + assign SAXISCCTDATA_in[175] = (SAXISCCTDATA[175] === 1'bz) || SAXISCCTDATA_delay[175]; // rv 1 + assign SAXISCCTDATA_in[176] = (SAXISCCTDATA[176] === 1'bz) || SAXISCCTDATA_delay[176]; // rv 1 + assign SAXISCCTDATA_in[177] = (SAXISCCTDATA[177] === 1'bz) || SAXISCCTDATA_delay[177]; // rv 1 + assign SAXISCCTDATA_in[178] = (SAXISCCTDATA[178] === 1'bz) || SAXISCCTDATA_delay[178]; // rv 1 + assign SAXISCCTDATA_in[179] = (SAXISCCTDATA[179] === 1'bz) || SAXISCCTDATA_delay[179]; // rv 1 + assign SAXISCCTDATA_in[17] = (SAXISCCTDATA[17] === 1'bz) || SAXISCCTDATA_delay[17]; // rv 1 + assign SAXISCCTDATA_in[180] = (SAXISCCTDATA[180] === 1'bz) || SAXISCCTDATA_delay[180]; // rv 1 + assign SAXISCCTDATA_in[181] = (SAXISCCTDATA[181] === 1'bz) || SAXISCCTDATA_delay[181]; // rv 1 + assign SAXISCCTDATA_in[182] = (SAXISCCTDATA[182] === 1'bz) || SAXISCCTDATA_delay[182]; // rv 1 + assign SAXISCCTDATA_in[183] = (SAXISCCTDATA[183] === 1'bz) || SAXISCCTDATA_delay[183]; // rv 1 + assign SAXISCCTDATA_in[184] = (SAXISCCTDATA[184] === 1'bz) || SAXISCCTDATA_delay[184]; // rv 1 + assign SAXISCCTDATA_in[185] = (SAXISCCTDATA[185] === 1'bz) || SAXISCCTDATA_delay[185]; // rv 1 + assign SAXISCCTDATA_in[186] = (SAXISCCTDATA[186] === 1'bz) || SAXISCCTDATA_delay[186]; // rv 1 + assign SAXISCCTDATA_in[187] = (SAXISCCTDATA[187] === 1'bz) || SAXISCCTDATA_delay[187]; // rv 1 + assign SAXISCCTDATA_in[188] = (SAXISCCTDATA[188] === 1'bz) || SAXISCCTDATA_delay[188]; // rv 1 + assign SAXISCCTDATA_in[189] = (SAXISCCTDATA[189] === 1'bz) || SAXISCCTDATA_delay[189]; // rv 1 + assign SAXISCCTDATA_in[18] = (SAXISCCTDATA[18] === 1'bz) || SAXISCCTDATA_delay[18]; // rv 1 + assign SAXISCCTDATA_in[190] = (SAXISCCTDATA[190] === 1'bz) || SAXISCCTDATA_delay[190]; // rv 1 + assign SAXISCCTDATA_in[191] = (SAXISCCTDATA[191] === 1'bz) || SAXISCCTDATA_delay[191]; // rv 1 + assign SAXISCCTDATA_in[192] = (SAXISCCTDATA[192] === 1'bz) || SAXISCCTDATA_delay[192]; // rv 1 + assign SAXISCCTDATA_in[193] = (SAXISCCTDATA[193] === 1'bz) || SAXISCCTDATA_delay[193]; // rv 1 + assign SAXISCCTDATA_in[194] = (SAXISCCTDATA[194] === 1'bz) || SAXISCCTDATA_delay[194]; // rv 1 + assign SAXISCCTDATA_in[195] = (SAXISCCTDATA[195] === 1'bz) || SAXISCCTDATA_delay[195]; // rv 1 + assign SAXISCCTDATA_in[196] = (SAXISCCTDATA[196] === 1'bz) || SAXISCCTDATA_delay[196]; // rv 1 + assign SAXISCCTDATA_in[197] = (SAXISCCTDATA[197] === 1'bz) || SAXISCCTDATA_delay[197]; // rv 1 + assign SAXISCCTDATA_in[198] = (SAXISCCTDATA[198] === 1'bz) || SAXISCCTDATA_delay[198]; // rv 1 + assign SAXISCCTDATA_in[199] = (SAXISCCTDATA[199] === 1'bz) || SAXISCCTDATA_delay[199]; // rv 1 + assign SAXISCCTDATA_in[19] = (SAXISCCTDATA[19] === 1'bz) || SAXISCCTDATA_delay[19]; // rv 1 + assign SAXISCCTDATA_in[1] = (SAXISCCTDATA[1] === 1'bz) || SAXISCCTDATA_delay[1]; // rv 1 + assign SAXISCCTDATA_in[200] = (SAXISCCTDATA[200] === 1'bz) || SAXISCCTDATA_delay[200]; // rv 1 + assign SAXISCCTDATA_in[201] = (SAXISCCTDATA[201] === 1'bz) || SAXISCCTDATA_delay[201]; // rv 1 + assign SAXISCCTDATA_in[202] = (SAXISCCTDATA[202] === 1'bz) || SAXISCCTDATA_delay[202]; // rv 1 + assign SAXISCCTDATA_in[203] = (SAXISCCTDATA[203] === 1'bz) || SAXISCCTDATA_delay[203]; // rv 1 + assign SAXISCCTDATA_in[204] = (SAXISCCTDATA[204] === 1'bz) || SAXISCCTDATA_delay[204]; // rv 1 + assign SAXISCCTDATA_in[205] = (SAXISCCTDATA[205] === 1'bz) || SAXISCCTDATA_delay[205]; // rv 1 + assign SAXISCCTDATA_in[206] = (SAXISCCTDATA[206] === 1'bz) || SAXISCCTDATA_delay[206]; // rv 1 + assign SAXISCCTDATA_in[207] = (SAXISCCTDATA[207] === 1'bz) || SAXISCCTDATA_delay[207]; // rv 1 + assign SAXISCCTDATA_in[208] = (SAXISCCTDATA[208] === 1'bz) || SAXISCCTDATA_delay[208]; // rv 1 + assign SAXISCCTDATA_in[209] = (SAXISCCTDATA[209] === 1'bz) || SAXISCCTDATA_delay[209]; // rv 1 + assign SAXISCCTDATA_in[20] = (SAXISCCTDATA[20] === 1'bz) || SAXISCCTDATA_delay[20]; // rv 1 + assign SAXISCCTDATA_in[210] = (SAXISCCTDATA[210] === 1'bz) || SAXISCCTDATA_delay[210]; // rv 1 + assign SAXISCCTDATA_in[211] = (SAXISCCTDATA[211] === 1'bz) || SAXISCCTDATA_delay[211]; // rv 1 + assign SAXISCCTDATA_in[212] = (SAXISCCTDATA[212] === 1'bz) || SAXISCCTDATA_delay[212]; // rv 1 + assign SAXISCCTDATA_in[213] = (SAXISCCTDATA[213] === 1'bz) || SAXISCCTDATA_delay[213]; // rv 1 + assign SAXISCCTDATA_in[214] = (SAXISCCTDATA[214] === 1'bz) || SAXISCCTDATA_delay[214]; // rv 1 + assign SAXISCCTDATA_in[215] = (SAXISCCTDATA[215] === 1'bz) || SAXISCCTDATA_delay[215]; // rv 1 + assign SAXISCCTDATA_in[216] = (SAXISCCTDATA[216] === 1'bz) || SAXISCCTDATA_delay[216]; // rv 1 + assign SAXISCCTDATA_in[217] = (SAXISCCTDATA[217] === 1'bz) || SAXISCCTDATA_delay[217]; // rv 1 + assign SAXISCCTDATA_in[218] = (SAXISCCTDATA[218] === 1'bz) || SAXISCCTDATA_delay[218]; // rv 1 + assign SAXISCCTDATA_in[219] = (SAXISCCTDATA[219] === 1'bz) || SAXISCCTDATA_delay[219]; // rv 1 + assign SAXISCCTDATA_in[21] = (SAXISCCTDATA[21] === 1'bz) || SAXISCCTDATA_delay[21]; // rv 1 + assign SAXISCCTDATA_in[220] = (SAXISCCTDATA[220] === 1'bz) || SAXISCCTDATA_delay[220]; // rv 1 + assign SAXISCCTDATA_in[221] = (SAXISCCTDATA[221] === 1'bz) || SAXISCCTDATA_delay[221]; // rv 1 + assign SAXISCCTDATA_in[222] = (SAXISCCTDATA[222] === 1'bz) || SAXISCCTDATA_delay[222]; // rv 1 + assign SAXISCCTDATA_in[223] = (SAXISCCTDATA[223] === 1'bz) || SAXISCCTDATA_delay[223]; // rv 1 + assign SAXISCCTDATA_in[224] = (SAXISCCTDATA[224] === 1'bz) || SAXISCCTDATA_delay[224]; // rv 1 + assign SAXISCCTDATA_in[225] = (SAXISCCTDATA[225] === 1'bz) || SAXISCCTDATA_delay[225]; // rv 1 + assign SAXISCCTDATA_in[226] = (SAXISCCTDATA[226] === 1'bz) || SAXISCCTDATA_delay[226]; // rv 1 + assign SAXISCCTDATA_in[227] = (SAXISCCTDATA[227] === 1'bz) || SAXISCCTDATA_delay[227]; // rv 1 + assign SAXISCCTDATA_in[228] = (SAXISCCTDATA[228] === 1'bz) || SAXISCCTDATA_delay[228]; // rv 1 + assign SAXISCCTDATA_in[229] = (SAXISCCTDATA[229] === 1'bz) || SAXISCCTDATA_delay[229]; // rv 1 + assign SAXISCCTDATA_in[22] = (SAXISCCTDATA[22] === 1'bz) || SAXISCCTDATA_delay[22]; // rv 1 + assign SAXISCCTDATA_in[230] = (SAXISCCTDATA[230] === 1'bz) || SAXISCCTDATA_delay[230]; // rv 1 + assign SAXISCCTDATA_in[231] = (SAXISCCTDATA[231] === 1'bz) || SAXISCCTDATA_delay[231]; // rv 1 + assign SAXISCCTDATA_in[232] = (SAXISCCTDATA[232] === 1'bz) || SAXISCCTDATA_delay[232]; // rv 1 + assign SAXISCCTDATA_in[233] = (SAXISCCTDATA[233] === 1'bz) || SAXISCCTDATA_delay[233]; // rv 1 + assign SAXISCCTDATA_in[234] = (SAXISCCTDATA[234] === 1'bz) || SAXISCCTDATA_delay[234]; // rv 1 + assign SAXISCCTDATA_in[235] = (SAXISCCTDATA[235] === 1'bz) || SAXISCCTDATA_delay[235]; // rv 1 + assign SAXISCCTDATA_in[236] = (SAXISCCTDATA[236] === 1'bz) || SAXISCCTDATA_delay[236]; // rv 1 + assign SAXISCCTDATA_in[237] = (SAXISCCTDATA[237] === 1'bz) || SAXISCCTDATA_delay[237]; // rv 1 + assign SAXISCCTDATA_in[238] = (SAXISCCTDATA[238] === 1'bz) || SAXISCCTDATA_delay[238]; // rv 1 + assign SAXISCCTDATA_in[239] = (SAXISCCTDATA[239] === 1'bz) || SAXISCCTDATA_delay[239]; // rv 1 + assign SAXISCCTDATA_in[23] = (SAXISCCTDATA[23] === 1'bz) || SAXISCCTDATA_delay[23]; // rv 1 + assign SAXISCCTDATA_in[240] = (SAXISCCTDATA[240] === 1'bz) || SAXISCCTDATA_delay[240]; // rv 1 + assign SAXISCCTDATA_in[241] = (SAXISCCTDATA[241] === 1'bz) || SAXISCCTDATA_delay[241]; // rv 1 + assign SAXISCCTDATA_in[242] = (SAXISCCTDATA[242] === 1'bz) || SAXISCCTDATA_delay[242]; // rv 1 + assign SAXISCCTDATA_in[243] = (SAXISCCTDATA[243] === 1'bz) || SAXISCCTDATA_delay[243]; // rv 1 + assign SAXISCCTDATA_in[244] = (SAXISCCTDATA[244] === 1'bz) || SAXISCCTDATA_delay[244]; // rv 1 + assign SAXISCCTDATA_in[245] = (SAXISCCTDATA[245] === 1'bz) || SAXISCCTDATA_delay[245]; // rv 1 + assign SAXISCCTDATA_in[246] = (SAXISCCTDATA[246] === 1'bz) || SAXISCCTDATA_delay[246]; // rv 1 + assign SAXISCCTDATA_in[247] = (SAXISCCTDATA[247] === 1'bz) || SAXISCCTDATA_delay[247]; // rv 1 + assign SAXISCCTDATA_in[248] = (SAXISCCTDATA[248] === 1'bz) || SAXISCCTDATA_delay[248]; // rv 1 + assign SAXISCCTDATA_in[249] = (SAXISCCTDATA[249] === 1'bz) || SAXISCCTDATA_delay[249]; // rv 1 + assign SAXISCCTDATA_in[24] = (SAXISCCTDATA[24] === 1'bz) || SAXISCCTDATA_delay[24]; // rv 1 + assign SAXISCCTDATA_in[250] = (SAXISCCTDATA[250] === 1'bz) || SAXISCCTDATA_delay[250]; // rv 1 + assign SAXISCCTDATA_in[251] = (SAXISCCTDATA[251] === 1'bz) || SAXISCCTDATA_delay[251]; // rv 1 + assign SAXISCCTDATA_in[252] = (SAXISCCTDATA[252] === 1'bz) || SAXISCCTDATA_delay[252]; // rv 1 + assign SAXISCCTDATA_in[253] = (SAXISCCTDATA[253] === 1'bz) || SAXISCCTDATA_delay[253]; // rv 1 + assign SAXISCCTDATA_in[254] = (SAXISCCTDATA[254] === 1'bz) || SAXISCCTDATA_delay[254]; // rv 1 + assign SAXISCCTDATA_in[255] = (SAXISCCTDATA[255] === 1'bz) || SAXISCCTDATA_delay[255]; // rv 1 + assign SAXISCCTDATA_in[25] = (SAXISCCTDATA[25] === 1'bz) || SAXISCCTDATA_delay[25]; // rv 1 + assign SAXISCCTDATA_in[26] = (SAXISCCTDATA[26] === 1'bz) || SAXISCCTDATA_delay[26]; // rv 1 + assign SAXISCCTDATA_in[27] = (SAXISCCTDATA[27] === 1'bz) || SAXISCCTDATA_delay[27]; // rv 1 + assign SAXISCCTDATA_in[28] = (SAXISCCTDATA[28] === 1'bz) || SAXISCCTDATA_delay[28]; // rv 1 + assign SAXISCCTDATA_in[29] = (SAXISCCTDATA[29] === 1'bz) || SAXISCCTDATA_delay[29]; // rv 1 + assign SAXISCCTDATA_in[2] = (SAXISCCTDATA[2] === 1'bz) || SAXISCCTDATA_delay[2]; // rv 1 + assign SAXISCCTDATA_in[30] = (SAXISCCTDATA[30] === 1'bz) || SAXISCCTDATA_delay[30]; // rv 1 + assign SAXISCCTDATA_in[31] = (SAXISCCTDATA[31] === 1'bz) || SAXISCCTDATA_delay[31]; // rv 1 + assign SAXISCCTDATA_in[32] = (SAXISCCTDATA[32] === 1'bz) || SAXISCCTDATA_delay[32]; // rv 1 + assign SAXISCCTDATA_in[33] = (SAXISCCTDATA[33] === 1'bz) || SAXISCCTDATA_delay[33]; // rv 1 + assign SAXISCCTDATA_in[34] = (SAXISCCTDATA[34] === 1'bz) || SAXISCCTDATA_delay[34]; // rv 1 + assign SAXISCCTDATA_in[35] = (SAXISCCTDATA[35] === 1'bz) || SAXISCCTDATA_delay[35]; // rv 1 + assign SAXISCCTDATA_in[36] = (SAXISCCTDATA[36] === 1'bz) || SAXISCCTDATA_delay[36]; // rv 1 + assign SAXISCCTDATA_in[37] = (SAXISCCTDATA[37] === 1'bz) || SAXISCCTDATA_delay[37]; // rv 1 + assign SAXISCCTDATA_in[38] = (SAXISCCTDATA[38] === 1'bz) || SAXISCCTDATA_delay[38]; // rv 1 + assign SAXISCCTDATA_in[39] = (SAXISCCTDATA[39] === 1'bz) || SAXISCCTDATA_delay[39]; // rv 1 + assign SAXISCCTDATA_in[3] = (SAXISCCTDATA[3] === 1'bz) || SAXISCCTDATA_delay[3]; // rv 1 + assign SAXISCCTDATA_in[40] = (SAXISCCTDATA[40] === 1'bz) || SAXISCCTDATA_delay[40]; // rv 1 + assign SAXISCCTDATA_in[41] = (SAXISCCTDATA[41] === 1'bz) || SAXISCCTDATA_delay[41]; // rv 1 + assign SAXISCCTDATA_in[42] = (SAXISCCTDATA[42] === 1'bz) || SAXISCCTDATA_delay[42]; // rv 1 + assign SAXISCCTDATA_in[43] = (SAXISCCTDATA[43] === 1'bz) || SAXISCCTDATA_delay[43]; // rv 1 + assign SAXISCCTDATA_in[44] = (SAXISCCTDATA[44] === 1'bz) || SAXISCCTDATA_delay[44]; // rv 1 + assign SAXISCCTDATA_in[45] = (SAXISCCTDATA[45] === 1'bz) || SAXISCCTDATA_delay[45]; // rv 1 + assign SAXISCCTDATA_in[46] = (SAXISCCTDATA[46] === 1'bz) || SAXISCCTDATA_delay[46]; // rv 1 + assign SAXISCCTDATA_in[47] = (SAXISCCTDATA[47] === 1'bz) || SAXISCCTDATA_delay[47]; // rv 1 + assign SAXISCCTDATA_in[48] = (SAXISCCTDATA[48] === 1'bz) || SAXISCCTDATA_delay[48]; // rv 1 + assign SAXISCCTDATA_in[49] = (SAXISCCTDATA[49] === 1'bz) || SAXISCCTDATA_delay[49]; // rv 1 + assign SAXISCCTDATA_in[4] = (SAXISCCTDATA[4] === 1'bz) || SAXISCCTDATA_delay[4]; // rv 1 + assign SAXISCCTDATA_in[50] = (SAXISCCTDATA[50] === 1'bz) || SAXISCCTDATA_delay[50]; // rv 1 + assign SAXISCCTDATA_in[51] = (SAXISCCTDATA[51] === 1'bz) || SAXISCCTDATA_delay[51]; // rv 1 + assign SAXISCCTDATA_in[52] = (SAXISCCTDATA[52] === 1'bz) || SAXISCCTDATA_delay[52]; // rv 1 + assign SAXISCCTDATA_in[53] = (SAXISCCTDATA[53] === 1'bz) || SAXISCCTDATA_delay[53]; // rv 1 + assign SAXISCCTDATA_in[54] = (SAXISCCTDATA[54] === 1'bz) || SAXISCCTDATA_delay[54]; // rv 1 + assign SAXISCCTDATA_in[55] = (SAXISCCTDATA[55] === 1'bz) || SAXISCCTDATA_delay[55]; // rv 1 + assign SAXISCCTDATA_in[56] = (SAXISCCTDATA[56] === 1'bz) || SAXISCCTDATA_delay[56]; // rv 1 + assign SAXISCCTDATA_in[57] = (SAXISCCTDATA[57] === 1'bz) || SAXISCCTDATA_delay[57]; // rv 1 + assign SAXISCCTDATA_in[58] = (SAXISCCTDATA[58] === 1'bz) || SAXISCCTDATA_delay[58]; // rv 1 + assign SAXISCCTDATA_in[59] = (SAXISCCTDATA[59] === 1'bz) || SAXISCCTDATA_delay[59]; // rv 1 + assign SAXISCCTDATA_in[5] = (SAXISCCTDATA[5] === 1'bz) || SAXISCCTDATA_delay[5]; // rv 1 + assign SAXISCCTDATA_in[60] = (SAXISCCTDATA[60] === 1'bz) || SAXISCCTDATA_delay[60]; // rv 1 + assign SAXISCCTDATA_in[61] = (SAXISCCTDATA[61] === 1'bz) || SAXISCCTDATA_delay[61]; // rv 1 + assign SAXISCCTDATA_in[62] = (SAXISCCTDATA[62] === 1'bz) || SAXISCCTDATA_delay[62]; // rv 1 + assign SAXISCCTDATA_in[63] = (SAXISCCTDATA[63] === 1'bz) || SAXISCCTDATA_delay[63]; // rv 1 + assign SAXISCCTDATA_in[64] = (SAXISCCTDATA[64] === 1'bz) || SAXISCCTDATA_delay[64]; // rv 1 + assign SAXISCCTDATA_in[65] = (SAXISCCTDATA[65] === 1'bz) || SAXISCCTDATA_delay[65]; // rv 1 + assign SAXISCCTDATA_in[66] = (SAXISCCTDATA[66] === 1'bz) || SAXISCCTDATA_delay[66]; // rv 1 + assign SAXISCCTDATA_in[67] = (SAXISCCTDATA[67] === 1'bz) || SAXISCCTDATA_delay[67]; // rv 1 + assign SAXISCCTDATA_in[68] = (SAXISCCTDATA[68] === 1'bz) || SAXISCCTDATA_delay[68]; // rv 1 + assign SAXISCCTDATA_in[69] = (SAXISCCTDATA[69] === 1'bz) || SAXISCCTDATA_delay[69]; // rv 1 + assign SAXISCCTDATA_in[6] = (SAXISCCTDATA[6] === 1'bz) || SAXISCCTDATA_delay[6]; // rv 1 + assign SAXISCCTDATA_in[70] = (SAXISCCTDATA[70] === 1'bz) || SAXISCCTDATA_delay[70]; // rv 1 + assign SAXISCCTDATA_in[71] = (SAXISCCTDATA[71] === 1'bz) || SAXISCCTDATA_delay[71]; // rv 1 + assign SAXISCCTDATA_in[72] = (SAXISCCTDATA[72] === 1'bz) || SAXISCCTDATA_delay[72]; // rv 1 + assign SAXISCCTDATA_in[73] = (SAXISCCTDATA[73] === 1'bz) || SAXISCCTDATA_delay[73]; // rv 1 + assign SAXISCCTDATA_in[74] = (SAXISCCTDATA[74] === 1'bz) || SAXISCCTDATA_delay[74]; // rv 1 + assign SAXISCCTDATA_in[75] = (SAXISCCTDATA[75] === 1'bz) || SAXISCCTDATA_delay[75]; // rv 1 + assign SAXISCCTDATA_in[76] = (SAXISCCTDATA[76] === 1'bz) || SAXISCCTDATA_delay[76]; // rv 1 + assign SAXISCCTDATA_in[77] = (SAXISCCTDATA[77] === 1'bz) || SAXISCCTDATA_delay[77]; // rv 1 + assign SAXISCCTDATA_in[78] = (SAXISCCTDATA[78] === 1'bz) || SAXISCCTDATA_delay[78]; // rv 1 + assign SAXISCCTDATA_in[79] = (SAXISCCTDATA[79] === 1'bz) || SAXISCCTDATA_delay[79]; // rv 1 + assign SAXISCCTDATA_in[7] = (SAXISCCTDATA[7] === 1'bz) || SAXISCCTDATA_delay[7]; // rv 1 + assign SAXISCCTDATA_in[80] = (SAXISCCTDATA[80] === 1'bz) || SAXISCCTDATA_delay[80]; // rv 1 + assign SAXISCCTDATA_in[81] = (SAXISCCTDATA[81] === 1'bz) || SAXISCCTDATA_delay[81]; // rv 1 + assign SAXISCCTDATA_in[82] = (SAXISCCTDATA[82] === 1'bz) || SAXISCCTDATA_delay[82]; // rv 1 + assign SAXISCCTDATA_in[83] = (SAXISCCTDATA[83] === 1'bz) || SAXISCCTDATA_delay[83]; // rv 1 + assign SAXISCCTDATA_in[84] = (SAXISCCTDATA[84] === 1'bz) || SAXISCCTDATA_delay[84]; // rv 1 + assign SAXISCCTDATA_in[85] = (SAXISCCTDATA[85] === 1'bz) || SAXISCCTDATA_delay[85]; // rv 1 + assign SAXISCCTDATA_in[86] = (SAXISCCTDATA[86] === 1'bz) || SAXISCCTDATA_delay[86]; // rv 1 + assign SAXISCCTDATA_in[87] = (SAXISCCTDATA[87] === 1'bz) || SAXISCCTDATA_delay[87]; // rv 1 + assign SAXISCCTDATA_in[88] = (SAXISCCTDATA[88] === 1'bz) || SAXISCCTDATA_delay[88]; // rv 1 + assign SAXISCCTDATA_in[89] = (SAXISCCTDATA[89] === 1'bz) || SAXISCCTDATA_delay[89]; // rv 1 + assign SAXISCCTDATA_in[8] = (SAXISCCTDATA[8] === 1'bz) || SAXISCCTDATA_delay[8]; // rv 1 + assign SAXISCCTDATA_in[90] = (SAXISCCTDATA[90] === 1'bz) || SAXISCCTDATA_delay[90]; // rv 1 + assign SAXISCCTDATA_in[91] = (SAXISCCTDATA[91] === 1'bz) || SAXISCCTDATA_delay[91]; // rv 1 + assign SAXISCCTDATA_in[92] = (SAXISCCTDATA[92] === 1'bz) || SAXISCCTDATA_delay[92]; // rv 1 + assign SAXISCCTDATA_in[93] = (SAXISCCTDATA[93] === 1'bz) || SAXISCCTDATA_delay[93]; // rv 1 + assign SAXISCCTDATA_in[94] = (SAXISCCTDATA[94] === 1'bz) || SAXISCCTDATA_delay[94]; // rv 1 + assign SAXISCCTDATA_in[95] = (SAXISCCTDATA[95] === 1'bz) || SAXISCCTDATA_delay[95]; // rv 1 + assign SAXISCCTDATA_in[96] = (SAXISCCTDATA[96] === 1'bz) || SAXISCCTDATA_delay[96]; // rv 1 + assign SAXISCCTDATA_in[97] = (SAXISCCTDATA[97] === 1'bz) || SAXISCCTDATA_delay[97]; // rv 1 + assign SAXISCCTDATA_in[98] = (SAXISCCTDATA[98] === 1'bz) || SAXISCCTDATA_delay[98]; // rv 1 + assign SAXISCCTDATA_in[99] = (SAXISCCTDATA[99] === 1'bz) || SAXISCCTDATA_delay[99]; // rv 1 + assign SAXISCCTDATA_in[9] = (SAXISCCTDATA[9] === 1'bz) || SAXISCCTDATA_delay[9]; // rv 1 + assign SAXISCCTKEEP_in[0] = (SAXISCCTKEEP[0] !== 1'bz) && SAXISCCTKEEP_delay[0]; // rv 0 + assign SAXISCCTKEEP_in[1] = (SAXISCCTKEEP[1] !== 1'bz) && SAXISCCTKEEP_delay[1]; // rv 0 + assign SAXISCCTKEEP_in[2] = (SAXISCCTKEEP[2] !== 1'bz) && SAXISCCTKEEP_delay[2]; // rv 0 + assign SAXISCCTKEEP_in[3] = (SAXISCCTKEEP[3] !== 1'bz) && SAXISCCTKEEP_delay[3]; // rv 0 + assign SAXISCCTKEEP_in[4] = (SAXISCCTKEEP[4] !== 1'bz) && SAXISCCTKEEP_delay[4]; // rv 0 + assign SAXISCCTKEEP_in[5] = (SAXISCCTKEEP[5] !== 1'bz) && SAXISCCTKEEP_delay[5]; // rv 0 + assign SAXISCCTKEEP_in[6] = (SAXISCCTKEEP[6] !== 1'bz) && SAXISCCTKEEP_delay[6]; // rv 0 + assign SAXISCCTKEEP_in[7] = (SAXISCCTKEEP[7] !== 1'bz) && SAXISCCTKEEP_delay[7]; // rv 0 + assign SAXISCCTLAST_in = (SAXISCCTLAST === 1'bz) || SAXISCCTLAST_delay; // rv 1 + assign SAXISCCTUSER_in[0] = (SAXISCCTUSER[0] === 1'bz) || SAXISCCTUSER_delay[0]; // rv 1 + assign SAXISCCTUSER_in[10] = (SAXISCCTUSER[10] === 1'bz) || SAXISCCTUSER_delay[10]; // rv 1 + assign SAXISCCTUSER_in[11] = (SAXISCCTUSER[11] === 1'bz) || SAXISCCTUSER_delay[11]; // rv 1 + assign SAXISCCTUSER_in[12] = (SAXISCCTUSER[12] === 1'bz) || SAXISCCTUSER_delay[12]; // rv 1 + assign SAXISCCTUSER_in[13] = (SAXISCCTUSER[13] === 1'bz) || SAXISCCTUSER_delay[13]; // rv 1 + assign SAXISCCTUSER_in[14] = (SAXISCCTUSER[14] === 1'bz) || SAXISCCTUSER_delay[14]; // rv 1 + assign SAXISCCTUSER_in[15] = (SAXISCCTUSER[15] === 1'bz) || SAXISCCTUSER_delay[15]; // rv 1 + assign SAXISCCTUSER_in[16] = (SAXISCCTUSER[16] === 1'bz) || SAXISCCTUSER_delay[16]; // rv 1 + assign SAXISCCTUSER_in[17] = (SAXISCCTUSER[17] === 1'bz) || SAXISCCTUSER_delay[17]; // rv 1 + assign SAXISCCTUSER_in[18] = (SAXISCCTUSER[18] === 1'bz) || SAXISCCTUSER_delay[18]; // rv 1 + assign SAXISCCTUSER_in[19] = (SAXISCCTUSER[19] === 1'bz) || SAXISCCTUSER_delay[19]; // rv 1 + assign SAXISCCTUSER_in[1] = (SAXISCCTUSER[1] === 1'bz) || SAXISCCTUSER_delay[1]; // rv 1 + assign SAXISCCTUSER_in[20] = (SAXISCCTUSER[20] === 1'bz) || SAXISCCTUSER_delay[20]; // rv 1 + assign SAXISCCTUSER_in[21] = (SAXISCCTUSER[21] === 1'bz) || SAXISCCTUSER_delay[21]; // rv 1 + assign SAXISCCTUSER_in[22] = (SAXISCCTUSER[22] === 1'bz) || SAXISCCTUSER_delay[22]; // rv 1 + assign SAXISCCTUSER_in[23] = (SAXISCCTUSER[23] === 1'bz) || SAXISCCTUSER_delay[23]; // rv 1 + assign SAXISCCTUSER_in[24] = (SAXISCCTUSER[24] === 1'bz) || SAXISCCTUSER_delay[24]; // rv 1 + assign SAXISCCTUSER_in[25] = (SAXISCCTUSER[25] === 1'bz) || SAXISCCTUSER_delay[25]; // rv 1 + assign SAXISCCTUSER_in[26] = (SAXISCCTUSER[26] === 1'bz) || SAXISCCTUSER_delay[26]; // rv 1 + assign SAXISCCTUSER_in[27] = (SAXISCCTUSER[27] === 1'bz) || SAXISCCTUSER_delay[27]; // rv 1 + assign SAXISCCTUSER_in[28] = (SAXISCCTUSER[28] === 1'bz) || SAXISCCTUSER_delay[28]; // rv 1 + assign SAXISCCTUSER_in[29] = (SAXISCCTUSER[29] === 1'bz) || SAXISCCTUSER_delay[29]; // rv 1 + assign SAXISCCTUSER_in[2] = (SAXISCCTUSER[2] === 1'bz) || SAXISCCTUSER_delay[2]; // rv 1 + assign SAXISCCTUSER_in[30] = (SAXISCCTUSER[30] === 1'bz) || SAXISCCTUSER_delay[30]; // rv 1 + assign SAXISCCTUSER_in[31] = (SAXISCCTUSER[31] === 1'bz) || SAXISCCTUSER_delay[31]; // rv 1 + assign SAXISCCTUSER_in[32] = (SAXISCCTUSER[32] === 1'bz) || SAXISCCTUSER_delay[32]; // rv 1 + assign SAXISCCTUSER_in[3] = (SAXISCCTUSER[3] === 1'bz) || SAXISCCTUSER_delay[3]; // rv 1 + assign SAXISCCTUSER_in[4] = (SAXISCCTUSER[4] === 1'bz) || SAXISCCTUSER_delay[4]; // rv 1 + assign SAXISCCTUSER_in[5] = (SAXISCCTUSER[5] === 1'bz) || SAXISCCTUSER_delay[5]; // rv 1 + assign SAXISCCTUSER_in[6] = (SAXISCCTUSER[6] === 1'bz) || SAXISCCTUSER_delay[6]; // rv 1 + assign SAXISCCTUSER_in[7] = (SAXISCCTUSER[7] === 1'bz) || SAXISCCTUSER_delay[7]; // rv 1 + assign SAXISCCTUSER_in[8] = (SAXISCCTUSER[8] === 1'bz) || SAXISCCTUSER_delay[8]; // rv 1 + assign SAXISCCTUSER_in[9] = (SAXISCCTUSER[9] === 1'bz) || SAXISCCTUSER_delay[9]; // rv 1 + assign SAXISCCTVALID_in = (SAXISCCTVALID !== 1'bz) && SAXISCCTVALID_delay; // rv 0 + assign SAXISRQTDATA_in[0] = (SAXISRQTDATA[0] === 1'bz) || SAXISRQTDATA_delay[0]; // rv 1 + assign SAXISRQTDATA_in[100] = (SAXISRQTDATA[100] === 1'bz) || SAXISRQTDATA_delay[100]; // rv 1 + assign SAXISRQTDATA_in[101] = (SAXISRQTDATA[101] === 1'bz) || SAXISRQTDATA_delay[101]; // rv 1 + assign SAXISRQTDATA_in[102] = (SAXISRQTDATA[102] === 1'bz) || SAXISRQTDATA_delay[102]; // rv 1 + assign SAXISRQTDATA_in[103] = (SAXISRQTDATA[103] === 1'bz) || SAXISRQTDATA_delay[103]; // rv 1 + assign SAXISRQTDATA_in[104] = (SAXISRQTDATA[104] === 1'bz) || SAXISRQTDATA_delay[104]; // rv 1 + assign SAXISRQTDATA_in[105] = (SAXISRQTDATA[105] === 1'bz) || SAXISRQTDATA_delay[105]; // rv 1 + assign SAXISRQTDATA_in[106] = (SAXISRQTDATA[106] === 1'bz) || SAXISRQTDATA_delay[106]; // rv 1 + assign SAXISRQTDATA_in[107] = (SAXISRQTDATA[107] === 1'bz) || SAXISRQTDATA_delay[107]; // rv 1 + assign SAXISRQTDATA_in[108] = (SAXISRQTDATA[108] === 1'bz) || SAXISRQTDATA_delay[108]; // rv 1 + assign SAXISRQTDATA_in[109] = (SAXISRQTDATA[109] === 1'bz) || SAXISRQTDATA_delay[109]; // rv 1 + assign SAXISRQTDATA_in[10] = (SAXISRQTDATA[10] === 1'bz) || SAXISRQTDATA_delay[10]; // rv 1 + assign SAXISRQTDATA_in[110] = (SAXISRQTDATA[110] === 1'bz) || SAXISRQTDATA_delay[110]; // rv 1 + assign SAXISRQTDATA_in[111] = (SAXISRQTDATA[111] === 1'bz) || SAXISRQTDATA_delay[111]; // rv 1 + assign SAXISRQTDATA_in[112] = (SAXISRQTDATA[112] === 1'bz) || SAXISRQTDATA_delay[112]; // rv 1 + assign SAXISRQTDATA_in[113] = (SAXISRQTDATA[113] === 1'bz) || SAXISRQTDATA_delay[113]; // rv 1 + assign SAXISRQTDATA_in[114] = (SAXISRQTDATA[114] === 1'bz) || SAXISRQTDATA_delay[114]; // rv 1 + assign SAXISRQTDATA_in[115] = (SAXISRQTDATA[115] === 1'bz) || SAXISRQTDATA_delay[115]; // rv 1 + assign SAXISRQTDATA_in[116] = (SAXISRQTDATA[116] === 1'bz) || SAXISRQTDATA_delay[116]; // rv 1 + assign SAXISRQTDATA_in[117] = (SAXISRQTDATA[117] === 1'bz) || SAXISRQTDATA_delay[117]; // rv 1 + assign SAXISRQTDATA_in[118] = (SAXISRQTDATA[118] === 1'bz) || SAXISRQTDATA_delay[118]; // rv 1 + assign SAXISRQTDATA_in[119] = (SAXISRQTDATA[119] === 1'bz) || SAXISRQTDATA_delay[119]; // rv 1 + assign SAXISRQTDATA_in[11] = (SAXISRQTDATA[11] === 1'bz) || SAXISRQTDATA_delay[11]; // rv 1 + assign SAXISRQTDATA_in[120] = (SAXISRQTDATA[120] === 1'bz) || SAXISRQTDATA_delay[120]; // rv 1 + assign SAXISRQTDATA_in[121] = (SAXISRQTDATA[121] === 1'bz) || SAXISRQTDATA_delay[121]; // rv 1 + assign SAXISRQTDATA_in[122] = (SAXISRQTDATA[122] === 1'bz) || SAXISRQTDATA_delay[122]; // rv 1 + assign SAXISRQTDATA_in[123] = (SAXISRQTDATA[123] === 1'bz) || SAXISRQTDATA_delay[123]; // rv 1 + assign SAXISRQTDATA_in[124] = (SAXISRQTDATA[124] === 1'bz) || SAXISRQTDATA_delay[124]; // rv 1 + assign SAXISRQTDATA_in[125] = (SAXISRQTDATA[125] === 1'bz) || SAXISRQTDATA_delay[125]; // rv 1 + assign SAXISRQTDATA_in[126] = (SAXISRQTDATA[126] === 1'bz) || SAXISRQTDATA_delay[126]; // rv 1 + assign SAXISRQTDATA_in[127] = (SAXISRQTDATA[127] === 1'bz) || SAXISRQTDATA_delay[127]; // rv 1 + assign SAXISRQTDATA_in[128] = (SAXISRQTDATA[128] === 1'bz) || SAXISRQTDATA_delay[128]; // rv 1 + assign SAXISRQTDATA_in[129] = (SAXISRQTDATA[129] === 1'bz) || SAXISRQTDATA_delay[129]; // rv 1 + assign SAXISRQTDATA_in[12] = (SAXISRQTDATA[12] === 1'bz) || SAXISRQTDATA_delay[12]; // rv 1 + assign SAXISRQTDATA_in[130] = (SAXISRQTDATA[130] === 1'bz) || SAXISRQTDATA_delay[130]; // rv 1 + assign SAXISRQTDATA_in[131] = (SAXISRQTDATA[131] === 1'bz) || SAXISRQTDATA_delay[131]; // rv 1 + assign SAXISRQTDATA_in[132] = (SAXISRQTDATA[132] === 1'bz) || SAXISRQTDATA_delay[132]; // rv 1 + assign SAXISRQTDATA_in[133] = (SAXISRQTDATA[133] === 1'bz) || SAXISRQTDATA_delay[133]; // rv 1 + assign SAXISRQTDATA_in[134] = (SAXISRQTDATA[134] === 1'bz) || SAXISRQTDATA_delay[134]; // rv 1 + assign SAXISRQTDATA_in[135] = (SAXISRQTDATA[135] === 1'bz) || SAXISRQTDATA_delay[135]; // rv 1 + assign SAXISRQTDATA_in[136] = (SAXISRQTDATA[136] === 1'bz) || SAXISRQTDATA_delay[136]; // rv 1 + assign SAXISRQTDATA_in[137] = (SAXISRQTDATA[137] === 1'bz) || SAXISRQTDATA_delay[137]; // rv 1 + assign SAXISRQTDATA_in[138] = (SAXISRQTDATA[138] === 1'bz) || SAXISRQTDATA_delay[138]; // rv 1 + assign SAXISRQTDATA_in[139] = (SAXISRQTDATA[139] === 1'bz) || SAXISRQTDATA_delay[139]; // rv 1 + assign SAXISRQTDATA_in[13] = (SAXISRQTDATA[13] === 1'bz) || SAXISRQTDATA_delay[13]; // rv 1 + assign SAXISRQTDATA_in[140] = (SAXISRQTDATA[140] === 1'bz) || SAXISRQTDATA_delay[140]; // rv 1 + assign SAXISRQTDATA_in[141] = (SAXISRQTDATA[141] === 1'bz) || SAXISRQTDATA_delay[141]; // rv 1 + assign SAXISRQTDATA_in[142] = (SAXISRQTDATA[142] === 1'bz) || SAXISRQTDATA_delay[142]; // rv 1 + assign SAXISRQTDATA_in[143] = (SAXISRQTDATA[143] === 1'bz) || SAXISRQTDATA_delay[143]; // rv 1 + assign SAXISRQTDATA_in[144] = (SAXISRQTDATA[144] === 1'bz) || SAXISRQTDATA_delay[144]; // rv 1 + assign SAXISRQTDATA_in[145] = (SAXISRQTDATA[145] === 1'bz) || SAXISRQTDATA_delay[145]; // rv 1 + assign SAXISRQTDATA_in[146] = (SAXISRQTDATA[146] === 1'bz) || SAXISRQTDATA_delay[146]; // rv 1 + assign SAXISRQTDATA_in[147] = (SAXISRQTDATA[147] === 1'bz) || SAXISRQTDATA_delay[147]; // rv 1 + assign SAXISRQTDATA_in[148] = (SAXISRQTDATA[148] === 1'bz) || SAXISRQTDATA_delay[148]; // rv 1 + assign SAXISRQTDATA_in[149] = (SAXISRQTDATA[149] === 1'bz) || SAXISRQTDATA_delay[149]; // rv 1 + assign SAXISRQTDATA_in[14] = (SAXISRQTDATA[14] === 1'bz) || SAXISRQTDATA_delay[14]; // rv 1 + assign SAXISRQTDATA_in[150] = (SAXISRQTDATA[150] === 1'bz) || SAXISRQTDATA_delay[150]; // rv 1 + assign SAXISRQTDATA_in[151] = (SAXISRQTDATA[151] === 1'bz) || SAXISRQTDATA_delay[151]; // rv 1 + assign SAXISRQTDATA_in[152] = (SAXISRQTDATA[152] === 1'bz) || SAXISRQTDATA_delay[152]; // rv 1 + assign SAXISRQTDATA_in[153] = (SAXISRQTDATA[153] === 1'bz) || SAXISRQTDATA_delay[153]; // rv 1 + assign SAXISRQTDATA_in[154] = (SAXISRQTDATA[154] === 1'bz) || SAXISRQTDATA_delay[154]; // rv 1 + assign SAXISRQTDATA_in[155] = (SAXISRQTDATA[155] === 1'bz) || SAXISRQTDATA_delay[155]; // rv 1 + assign SAXISRQTDATA_in[156] = (SAXISRQTDATA[156] === 1'bz) || SAXISRQTDATA_delay[156]; // rv 1 + assign SAXISRQTDATA_in[157] = (SAXISRQTDATA[157] === 1'bz) || SAXISRQTDATA_delay[157]; // rv 1 + assign SAXISRQTDATA_in[158] = (SAXISRQTDATA[158] === 1'bz) || SAXISRQTDATA_delay[158]; // rv 1 + assign SAXISRQTDATA_in[159] = (SAXISRQTDATA[159] === 1'bz) || SAXISRQTDATA_delay[159]; // rv 1 + assign SAXISRQTDATA_in[15] = (SAXISRQTDATA[15] === 1'bz) || SAXISRQTDATA_delay[15]; // rv 1 + assign SAXISRQTDATA_in[160] = (SAXISRQTDATA[160] === 1'bz) || SAXISRQTDATA_delay[160]; // rv 1 + assign SAXISRQTDATA_in[161] = (SAXISRQTDATA[161] === 1'bz) || SAXISRQTDATA_delay[161]; // rv 1 + assign SAXISRQTDATA_in[162] = (SAXISRQTDATA[162] === 1'bz) || SAXISRQTDATA_delay[162]; // rv 1 + assign SAXISRQTDATA_in[163] = (SAXISRQTDATA[163] === 1'bz) || SAXISRQTDATA_delay[163]; // rv 1 + assign SAXISRQTDATA_in[164] = (SAXISRQTDATA[164] === 1'bz) || SAXISRQTDATA_delay[164]; // rv 1 + assign SAXISRQTDATA_in[165] = (SAXISRQTDATA[165] === 1'bz) || SAXISRQTDATA_delay[165]; // rv 1 + assign SAXISRQTDATA_in[166] = (SAXISRQTDATA[166] === 1'bz) || SAXISRQTDATA_delay[166]; // rv 1 + assign SAXISRQTDATA_in[167] = (SAXISRQTDATA[167] === 1'bz) || SAXISRQTDATA_delay[167]; // rv 1 + assign SAXISRQTDATA_in[168] = (SAXISRQTDATA[168] === 1'bz) || SAXISRQTDATA_delay[168]; // rv 1 + assign SAXISRQTDATA_in[169] = (SAXISRQTDATA[169] === 1'bz) || SAXISRQTDATA_delay[169]; // rv 1 + assign SAXISRQTDATA_in[16] = (SAXISRQTDATA[16] === 1'bz) || SAXISRQTDATA_delay[16]; // rv 1 + assign SAXISRQTDATA_in[170] = (SAXISRQTDATA[170] === 1'bz) || SAXISRQTDATA_delay[170]; // rv 1 + assign SAXISRQTDATA_in[171] = (SAXISRQTDATA[171] === 1'bz) || SAXISRQTDATA_delay[171]; // rv 1 + assign SAXISRQTDATA_in[172] = (SAXISRQTDATA[172] === 1'bz) || SAXISRQTDATA_delay[172]; // rv 1 + assign SAXISRQTDATA_in[173] = (SAXISRQTDATA[173] === 1'bz) || SAXISRQTDATA_delay[173]; // rv 1 + assign SAXISRQTDATA_in[174] = (SAXISRQTDATA[174] === 1'bz) || SAXISRQTDATA_delay[174]; // rv 1 + assign SAXISRQTDATA_in[175] = (SAXISRQTDATA[175] === 1'bz) || SAXISRQTDATA_delay[175]; // rv 1 + assign SAXISRQTDATA_in[176] = (SAXISRQTDATA[176] === 1'bz) || SAXISRQTDATA_delay[176]; // rv 1 + assign SAXISRQTDATA_in[177] = (SAXISRQTDATA[177] === 1'bz) || SAXISRQTDATA_delay[177]; // rv 1 + assign SAXISRQTDATA_in[178] = (SAXISRQTDATA[178] === 1'bz) || SAXISRQTDATA_delay[178]; // rv 1 + assign SAXISRQTDATA_in[179] = (SAXISRQTDATA[179] === 1'bz) || SAXISRQTDATA_delay[179]; // rv 1 + assign SAXISRQTDATA_in[17] = (SAXISRQTDATA[17] === 1'bz) || SAXISRQTDATA_delay[17]; // rv 1 + assign SAXISRQTDATA_in[180] = (SAXISRQTDATA[180] === 1'bz) || SAXISRQTDATA_delay[180]; // rv 1 + assign SAXISRQTDATA_in[181] = (SAXISRQTDATA[181] === 1'bz) || SAXISRQTDATA_delay[181]; // rv 1 + assign SAXISRQTDATA_in[182] = (SAXISRQTDATA[182] === 1'bz) || SAXISRQTDATA_delay[182]; // rv 1 + assign SAXISRQTDATA_in[183] = (SAXISRQTDATA[183] === 1'bz) || SAXISRQTDATA_delay[183]; // rv 1 + assign SAXISRQTDATA_in[184] = (SAXISRQTDATA[184] === 1'bz) || SAXISRQTDATA_delay[184]; // rv 1 + assign SAXISRQTDATA_in[185] = (SAXISRQTDATA[185] === 1'bz) || SAXISRQTDATA_delay[185]; // rv 1 + assign SAXISRQTDATA_in[186] = (SAXISRQTDATA[186] === 1'bz) || SAXISRQTDATA_delay[186]; // rv 1 + assign SAXISRQTDATA_in[187] = (SAXISRQTDATA[187] === 1'bz) || SAXISRQTDATA_delay[187]; // rv 1 + assign SAXISRQTDATA_in[188] = (SAXISRQTDATA[188] === 1'bz) || SAXISRQTDATA_delay[188]; // rv 1 + assign SAXISRQTDATA_in[189] = (SAXISRQTDATA[189] === 1'bz) || SAXISRQTDATA_delay[189]; // rv 1 + assign SAXISRQTDATA_in[18] = (SAXISRQTDATA[18] === 1'bz) || SAXISRQTDATA_delay[18]; // rv 1 + assign SAXISRQTDATA_in[190] = (SAXISRQTDATA[190] === 1'bz) || SAXISRQTDATA_delay[190]; // rv 1 + assign SAXISRQTDATA_in[191] = (SAXISRQTDATA[191] === 1'bz) || SAXISRQTDATA_delay[191]; // rv 1 + assign SAXISRQTDATA_in[192] = (SAXISRQTDATA[192] === 1'bz) || SAXISRQTDATA_delay[192]; // rv 1 + assign SAXISRQTDATA_in[193] = (SAXISRQTDATA[193] === 1'bz) || SAXISRQTDATA_delay[193]; // rv 1 + assign SAXISRQTDATA_in[194] = (SAXISRQTDATA[194] === 1'bz) || SAXISRQTDATA_delay[194]; // rv 1 + assign SAXISRQTDATA_in[195] = (SAXISRQTDATA[195] === 1'bz) || SAXISRQTDATA_delay[195]; // rv 1 + assign SAXISRQTDATA_in[196] = (SAXISRQTDATA[196] === 1'bz) || SAXISRQTDATA_delay[196]; // rv 1 + assign SAXISRQTDATA_in[197] = (SAXISRQTDATA[197] === 1'bz) || SAXISRQTDATA_delay[197]; // rv 1 + assign SAXISRQTDATA_in[198] = (SAXISRQTDATA[198] === 1'bz) || SAXISRQTDATA_delay[198]; // rv 1 + assign SAXISRQTDATA_in[199] = (SAXISRQTDATA[199] === 1'bz) || SAXISRQTDATA_delay[199]; // rv 1 + assign SAXISRQTDATA_in[19] = (SAXISRQTDATA[19] === 1'bz) || SAXISRQTDATA_delay[19]; // rv 1 + assign SAXISRQTDATA_in[1] = (SAXISRQTDATA[1] === 1'bz) || SAXISRQTDATA_delay[1]; // rv 1 + assign SAXISRQTDATA_in[200] = (SAXISRQTDATA[200] === 1'bz) || SAXISRQTDATA_delay[200]; // rv 1 + assign SAXISRQTDATA_in[201] = (SAXISRQTDATA[201] === 1'bz) || SAXISRQTDATA_delay[201]; // rv 1 + assign SAXISRQTDATA_in[202] = (SAXISRQTDATA[202] === 1'bz) || SAXISRQTDATA_delay[202]; // rv 1 + assign SAXISRQTDATA_in[203] = (SAXISRQTDATA[203] === 1'bz) || SAXISRQTDATA_delay[203]; // rv 1 + assign SAXISRQTDATA_in[204] = (SAXISRQTDATA[204] === 1'bz) || SAXISRQTDATA_delay[204]; // rv 1 + assign SAXISRQTDATA_in[205] = (SAXISRQTDATA[205] === 1'bz) || SAXISRQTDATA_delay[205]; // rv 1 + assign SAXISRQTDATA_in[206] = (SAXISRQTDATA[206] === 1'bz) || SAXISRQTDATA_delay[206]; // rv 1 + assign SAXISRQTDATA_in[207] = (SAXISRQTDATA[207] === 1'bz) || SAXISRQTDATA_delay[207]; // rv 1 + assign SAXISRQTDATA_in[208] = (SAXISRQTDATA[208] === 1'bz) || SAXISRQTDATA_delay[208]; // rv 1 + assign SAXISRQTDATA_in[209] = (SAXISRQTDATA[209] === 1'bz) || SAXISRQTDATA_delay[209]; // rv 1 + assign SAXISRQTDATA_in[20] = (SAXISRQTDATA[20] === 1'bz) || SAXISRQTDATA_delay[20]; // rv 1 + assign SAXISRQTDATA_in[210] = (SAXISRQTDATA[210] === 1'bz) || SAXISRQTDATA_delay[210]; // rv 1 + assign SAXISRQTDATA_in[211] = (SAXISRQTDATA[211] === 1'bz) || SAXISRQTDATA_delay[211]; // rv 1 + assign SAXISRQTDATA_in[212] = (SAXISRQTDATA[212] === 1'bz) || SAXISRQTDATA_delay[212]; // rv 1 + assign SAXISRQTDATA_in[213] = (SAXISRQTDATA[213] === 1'bz) || SAXISRQTDATA_delay[213]; // rv 1 + assign SAXISRQTDATA_in[214] = (SAXISRQTDATA[214] === 1'bz) || SAXISRQTDATA_delay[214]; // rv 1 + assign SAXISRQTDATA_in[215] = (SAXISRQTDATA[215] === 1'bz) || SAXISRQTDATA_delay[215]; // rv 1 + assign SAXISRQTDATA_in[216] = (SAXISRQTDATA[216] === 1'bz) || SAXISRQTDATA_delay[216]; // rv 1 + assign SAXISRQTDATA_in[217] = (SAXISRQTDATA[217] === 1'bz) || SAXISRQTDATA_delay[217]; // rv 1 + assign SAXISRQTDATA_in[218] = (SAXISRQTDATA[218] === 1'bz) || SAXISRQTDATA_delay[218]; // rv 1 + assign SAXISRQTDATA_in[219] = (SAXISRQTDATA[219] === 1'bz) || SAXISRQTDATA_delay[219]; // rv 1 + assign SAXISRQTDATA_in[21] = (SAXISRQTDATA[21] === 1'bz) || SAXISRQTDATA_delay[21]; // rv 1 + assign SAXISRQTDATA_in[220] = (SAXISRQTDATA[220] === 1'bz) || SAXISRQTDATA_delay[220]; // rv 1 + assign SAXISRQTDATA_in[221] = (SAXISRQTDATA[221] === 1'bz) || SAXISRQTDATA_delay[221]; // rv 1 + assign SAXISRQTDATA_in[222] = (SAXISRQTDATA[222] === 1'bz) || SAXISRQTDATA_delay[222]; // rv 1 + assign SAXISRQTDATA_in[223] = (SAXISRQTDATA[223] === 1'bz) || SAXISRQTDATA_delay[223]; // rv 1 + assign SAXISRQTDATA_in[224] = (SAXISRQTDATA[224] === 1'bz) || SAXISRQTDATA_delay[224]; // rv 1 + assign SAXISRQTDATA_in[225] = (SAXISRQTDATA[225] === 1'bz) || SAXISRQTDATA_delay[225]; // rv 1 + assign SAXISRQTDATA_in[226] = (SAXISRQTDATA[226] === 1'bz) || SAXISRQTDATA_delay[226]; // rv 1 + assign SAXISRQTDATA_in[227] = (SAXISRQTDATA[227] === 1'bz) || SAXISRQTDATA_delay[227]; // rv 1 + assign SAXISRQTDATA_in[228] = (SAXISRQTDATA[228] === 1'bz) || SAXISRQTDATA_delay[228]; // rv 1 + assign SAXISRQTDATA_in[229] = (SAXISRQTDATA[229] === 1'bz) || SAXISRQTDATA_delay[229]; // rv 1 + assign SAXISRQTDATA_in[22] = (SAXISRQTDATA[22] === 1'bz) || SAXISRQTDATA_delay[22]; // rv 1 + assign SAXISRQTDATA_in[230] = (SAXISRQTDATA[230] === 1'bz) || SAXISRQTDATA_delay[230]; // rv 1 + assign SAXISRQTDATA_in[231] = (SAXISRQTDATA[231] === 1'bz) || SAXISRQTDATA_delay[231]; // rv 1 + assign SAXISRQTDATA_in[232] = (SAXISRQTDATA[232] === 1'bz) || SAXISRQTDATA_delay[232]; // rv 1 + assign SAXISRQTDATA_in[233] = (SAXISRQTDATA[233] === 1'bz) || SAXISRQTDATA_delay[233]; // rv 1 + assign SAXISRQTDATA_in[234] = (SAXISRQTDATA[234] === 1'bz) || SAXISRQTDATA_delay[234]; // rv 1 + assign SAXISRQTDATA_in[235] = (SAXISRQTDATA[235] === 1'bz) || SAXISRQTDATA_delay[235]; // rv 1 + assign SAXISRQTDATA_in[236] = (SAXISRQTDATA[236] === 1'bz) || SAXISRQTDATA_delay[236]; // rv 1 + assign SAXISRQTDATA_in[237] = (SAXISRQTDATA[237] === 1'bz) || SAXISRQTDATA_delay[237]; // rv 1 + assign SAXISRQTDATA_in[238] = (SAXISRQTDATA[238] === 1'bz) || SAXISRQTDATA_delay[238]; // rv 1 + assign SAXISRQTDATA_in[239] = (SAXISRQTDATA[239] === 1'bz) || SAXISRQTDATA_delay[239]; // rv 1 + assign SAXISRQTDATA_in[23] = (SAXISRQTDATA[23] === 1'bz) || SAXISRQTDATA_delay[23]; // rv 1 + assign SAXISRQTDATA_in[240] = (SAXISRQTDATA[240] === 1'bz) || SAXISRQTDATA_delay[240]; // rv 1 + assign SAXISRQTDATA_in[241] = (SAXISRQTDATA[241] === 1'bz) || SAXISRQTDATA_delay[241]; // rv 1 + assign SAXISRQTDATA_in[242] = (SAXISRQTDATA[242] === 1'bz) || SAXISRQTDATA_delay[242]; // rv 1 + assign SAXISRQTDATA_in[243] = (SAXISRQTDATA[243] === 1'bz) || SAXISRQTDATA_delay[243]; // rv 1 + assign SAXISRQTDATA_in[244] = (SAXISRQTDATA[244] === 1'bz) || SAXISRQTDATA_delay[244]; // rv 1 + assign SAXISRQTDATA_in[245] = (SAXISRQTDATA[245] === 1'bz) || SAXISRQTDATA_delay[245]; // rv 1 + assign SAXISRQTDATA_in[246] = (SAXISRQTDATA[246] === 1'bz) || SAXISRQTDATA_delay[246]; // rv 1 + assign SAXISRQTDATA_in[247] = (SAXISRQTDATA[247] === 1'bz) || SAXISRQTDATA_delay[247]; // rv 1 + assign SAXISRQTDATA_in[248] = (SAXISRQTDATA[248] === 1'bz) || SAXISRQTDATA_delay[248]; // rv 1 + assign SAXISRQTDATA_in[249] = (SAXISRQTDATA[249] === 1'bz) || SAXISRQTDATA_delay[249]; // rv 1 + assign SAXISRQTDATA_in[24] = (SAXISRQTDATA[24] === 1'bz) || SAXISRQTDATA_delay[24]; // rv 1 + assign SAXISRQTDATA_in[250] = (SAXISRQTDATA[250] === 1'bz) || SAXISRQTDATA_delay[250]; // rv 1 + assign SAXISRQTDATA_in[251] = (SAXISRQTDATA[251] === 1'bz) || SAXISRQTDATA_delay[251]; // rv 1 + assign SAXISRQTDATA_in[252] = (SAXISRQTDATA[252] === 1'bz) || SAXISRQTDATA_delay[252]; // rv 1 + assign SAXISRQTDATA_in[253] = (SAXISRQTDATA[253] === 1'bz) || SAXISRQTDATA_delay[253]; // rv 1 + assign SAXISRQTDATA_in[254] = (SAXISRQTDATA[254] === 1'bz) || SAXISRQTDATA_delay[254]; // rv 1 + assign SAXISRQTDATA_in[255] = (SAXISRQTDATA[255] === 1'bz) || SAXISRQTDATA_delay[255]; // rv 1 + assign SAXISRQTDATA_in[25] = (SAXISRQTDATA[25] === 1'bz) || SAXISRQTDATA_delay[25]; // rv 1 + assign SAXISRQTDATA_in[26] = (SAXISRQTDATA[26] === 1'bz) || SAXISRQTDATA_delay[26]; // rv 1 + assign SAXISRQTDATA_in[27] = (SAXISRQTDATA[27] === 1'bz) || SAXISRQTDATA_delay[27]; // rv 1 + assign SAXISRQTDATA_in[28] = (SAXISRQTDATA[28] === 1'bz) || SAXISRQTDATA_delay[28]; // rv 1 + assign SAXISRQTDATA_in[29] = (SAXISRQTDATA[29] === 1'bz) || SAXISRQTDATA_delay[29]; // rv 1 + assign SAXISRQTDATA_in[2] = (SAXISRQTDATA[2] === 1'bz) || SAXISRQTDATA_delay[2]; // rv 1 + assign SAXISRQTDATA_in[30] = (SAXISRQTDATA[30] === 1'bz) || SAXISRQTDATA_delay[30]; // rv 1 + assign SAXISRQTDATA_in[31] = (SAXISRQTDATA[31] === 1'bz) || SAXISRQTDATA_delay[31]; // rv 1 + assign SAXISRQTDATA_in[32] = (SAXISRQTDATA[32] === 1'bz) || SAXISRQTDATA_delay[32]; // rv 1 + assign SAXISRQTDATA_in[33] = (SAXISRQTDATA[33] === 1'bz) || SAXISRQTDATA_delay[33]; // rv 1 + assign SAXISRQTDATA_in[34] = (SAXISRQTDATA[34] === 1'bz) || SAXISRQTDATA_delay[34]; // rv 1 + assign SAXISRQTDATA_in[35] = (SAXISRQTDATA[35] === 1'bz) || SAXISRQTDATA_delay[35]; // rv 1 + assign SAXISRQTDATA_in[36] = (SAXISRQTDATA[36] === 1'bz) || SAXISRQTDATA_delay[36]; // rv 1 + assign SAXISRQTDATA_in[37] = (SAXISRQTDATA[37] === 1'bz) || SAXISRQTDATA_delay[37]; // rv 1 + assign SAXISRQTDATA_in[38] = (SAXISRQTDATA[38] === 1'bz) || SAXISRQTDATA_delay[38]; // rv 1 + assign SAXISRQTDATA_in[39] = (SAXISRQTDATA[39] === 1'bz) || SAXISRQTDATA_delay[39]; // rv 1 + assign SAXISRQTDATA_in[3] = (SAXISRQTDATA[3] === 1'bz) || SAXISRQTDATA_delay[3]; // rv 1 + assign SAXISRQTDATA_in[40] = (SAXISRQTDATA[40] === 1'bz) || SAXISRQTDATA_delay[40]; // rv 1 + assign SAXISRQTDATA_in[41] = (SAXISRQTDATA[41] === 1'bz) || SAXISRQTDATA_delay[41]; // rv 1 + assign SAXISRQTDATA_in[42] = (SAXISRQTDATA[42] === 1'bz) || SAXISRQTDATA_delay[42]; // rv 1 + assign SAXISRQTDATA_in[43] = (SAXISRQTDATA[43] === 1'bz) || SAXISRQTDATA_delay[43]; // rv 1 + assign SAXISRQTDATA_in[44] = (SAXISRQTDATA[44] === 1'bz) || SAXISRQTDATA_delay[44]; // rv 1 + assign SAXISRQTDATA_in[45] = (SAXISRQTDATA[45] === 1'bz) || SAXISRQTDATA_delay[45]; // rv 1 + assign SAXISRQTDATA_in[46] = (SAXISRQTDATA[46] === 1'bz) || SAXISRQTDATA_delay[46]; // rv 1 + assign SAXISRQTDATA_in[47] = (SAXISRQTDATA[47] === 1'bz) || SAXISRQTDATA_delay[47]; // rv 1 + assign SAXISRQTDATA_in[48] = (SAXISRQTDATA[48] === 1'bz) || SAXISRQTDATA_delay[48]; // rv 1 + assign SAXISRQTDATA_in[49] = (SAXISRQTDATA[49] === 1'bz) || SAXISRQTDATA_delay[49]; // rv 1 + assign SAXISRQTDATA_in[4] = (SAXISRQTDATA[4] === 1'bz) || SAXISRQTDATA_delay[4]; // rv 1 + assign SAXISRQTDATA_in[50] = (SAXISRQTDATA[50] === 1'bz) || SAXISRQTDATA_delay[50]; // rv 1 + assign SAXISRQTDATA_in[51] = (SAXISRQTDATA[51] === 1'bz) || SAXISRQTDATA_delay[51]; // rv 1 + assign SAXISRQTDATA_in[52] = (SAXISRQTDATA[52] === 1'bz) || SAXISRQTDATA_delay[52]; // rv 1 + assign SAXISRQTDATA_in[53] = (SAXISRQTDATA[53] === 1'bz) || SAXISRQTDATA_delay[53]; // rv 1 + assign SAXISRQTDATA_in[54] = (SAXISRQTDATA[54] === 1'bz) || SAXISRQTDATA_delay[54]; // rv 1 + assign SAXISRQTDATA_in[55] = (SAXISRQTDATA[55] === 1'bz) || SAXISRQTDATA_delay[55]; // rv 1 + assign SAXISRQTDATA_in[56] = (SAXISRQTDATA[56] === 1'bz) || SAXISRQTDATA_delay[56]; // rv 1 + assign SAXISRQTDATA_in[57] = (SAXISRQTDATA[57] === 1'bz) || SAXISRQTDATA_delay[57]; // rv 1 + assign SAXISRQTDATA_in[58] = (SAXISRQTDATA[58] === 1'bz) || SAXISRQTDATA_delay[58]; // rv 1 + assign SAXISRQTDATA_in[59] = (SAXISRQTDATA[59] === 1'bz) || SAXISRQTDATA_delay[59]; // rv 1 + assign SAXISRQTDATA_in[5] = (SAXISRQTDATA[5] === 1'bz) || SAXISRQTDATA_delay[5]; // rv 1 + assign SAXISRQTDATA_in[60] = (SAXISRQTDATA[60] === 1'bz) || SAXISRQTDATA_delay[60]; // rv 1 + assign SAXISRQTDATA_in[61] = (SAXISRQTDATA[61] === 1'bz) || SAXISRQTDATA_delay[61]; // rv 1 + assign SAXISRQTDATA_in[62] = (SAXISRQTDATA[62] === 1'bz) || SAXISRQTDATA_delay[62]; // rv 1 + assign SAXISRQTDATA_in[63] = (SAXISRQTDATA[63] === 1'bz) || SAXISRQTDATA_delay[63]; // rv 1 + assign SAXISRQTDATA_in[64] = (SAXISRQTDATA[64] === 1'bz) || SAXISRQTDATA_delay[64]; // rv 1 + assign SAXISRQTDATA_in[65] = (SAXISRQTDATA[65] === 1'bz) || SAXISRQTDATA_delay[65]; // rv 1 + assign SAXISRQTDATA_in[66] = (SAXISRQTDATA[66] === 1'bz) || SAXISRQTDATA_delay[66]; // rv 1 + assign SAXISRQTDATA_in[67] = (SAXISRQTDATA[67] === 1'bz) || SAXISRQTDATA_delay[67]; // rv 1 + assign SAXISRQTDATA_in[68] = (SAXISRQTDATA[68] === 1'bz) || SAXISRQTDATA_delay[68]; // rv 1 + assign SAXISRQTDATA_in[69] = (SAXISRQTDATA[69] === 1'bz) || SAXISRQTDATA_delay[69]; // rv 1 + assign SAXISRQTDATA_in[6] = (SAXISRQTDATA[6] === 1'bz) || SAXISRQTDATA_delay[6]; // rv 1 + assign SAXISRQTDATA_in[70] = (SAXISRQTDATA[70] === 1'bz) || SAXISRQTDATA_delay[70]; // rv 1 + assign SAXISRQTDATA_in[71] = (SAXISRQTDATA[71] === 1'bz) || SAXISRQTDATA_delay[71]; // rv 1 + assign SAXISRQTDATA_in[72] = (SAXISRQTDATA[72] === 1'bz) || SAXISRQTDATA_delay[72]; // rv 1 + assign SAXISRQTDATA_in[73] = (SAXISRQTDATA[73] === 1'bz) || SAXISRQTDATA_delay[73]; // rv 1 + assign SAXISRQTDATA_in[74] = (SAXISRQTDATA[74] === 1'bz) || SAXISRQTDATA_delay[74]; // rv 1 + assign SAXISRQTDATA_in[75] = (SAXISRQTDATA[75] === 1'bz) || SAXISRQTDATA_delay[75]; // rv 1 + assign SAXISRQTDATA_in[76] = (SAXISRQTDATA[76] === 1'bz) || SAXISRQTDATA_delay[76]; // rv 1 + assign SAXISRQTDATA_in[77] = (SAXISRQTDATA[77] === 1'bz) || SAXISRQTDATA_delay[77]; // rv 1 + assign SAXISRQTDATA_in[78] = (SAXISRQTDATA[78] === 1'bz) || SAXISRQTDATA_delay[78]; // rv 1 + assign SAXISRQTDATA_in[79] = (SAXISRQTDATA[79] === 1'bz) || SAXISRQTDATA_delay[79]; // rv 1 + assign SAXISRQTDATA_in[7] = (SAXISRQTDATA[7] === 1'bz) || SAXISRQTDATA_delay[7]; // rv 1 + assign SAXISRQTDATA_in[80] = (SAXISRQTDATA[80] === 1'bz) || SAXISRQTDATA_delay[80]; // rv 1 + assign SAXISRQTDATA_in[81] = (SAXISRQTDATA[81] === 1'bz) || SAXISRQTDATA_delay[81]; // rv 1 + assign SAXISRQTDATA_in[82] = (SAXISRQTDATA[82] === 1'bz) || SAXISRQTDATA_delay[82]; // rv 1 + assign SAXISRQTDATA_in[83] = (SAXISRQTDATA[83] === 1'bz) || SAXISRQTDATA_delay[83]; // rv 1 + assign SAXISRQTDATA_in[84] = (SAXISRQTDATA[84] === 1'bz) || SAXISRQTDATA_delay[84]; // rv 1 + assign SAXISRQTDATA_in[85] = (SAXISRQTDATA[85] === 1'bz) || SAXISRQTDATA_delay[85]; // rv 1 + assign SAXISRQTDATA_in[86] = (SAXISRQTDATA[86] === 1'bz) || SAXISRQTDATA_delay[86]; // rv 1 + assign SAXISRQTDATA_in[87] = (SAXISRQTDATA[87] === 1'bz) || SAXISRQTDATA_delay[87]; // rv 1 + assign SAXISRQTDATA_in[88] = (SAXISRQTDATA[88] === 1'bz) || SAXISRQTDATA_delay[88]; // rv 1 + assign SAXISRQTDATA_in[89] = (SAXISRQTDATA[89] === 1'bz) || SAXISRQTDATA_delay[89]; // rv 1 + assign SAXISRQTDATA_in[8] = (SAXISRQTDATA[8] === 1'bz) || SAXISRQTDATA_delay[8]; // rv 1 + assign SAXISRQTDATA_in[90] = (SAXISRQTDATA[90] === 1'bz) || SAXISRQTDATA_delay[90]; // rv 1 + assign SAXISRQTDATA_in[91] = (SAXISRQTDATA[91] === 1'bz) || SAXISRQTDATA_delay[91]; // rv 1 + assign SAXISRQTDATA_in[92] = (SAXISRQTDATA[92] === 1'bz) || SAXISRQTDATA_delay[92]; // rv 1 + assign SAXISRQTDATA_in[93] = (SAXISRQTDATA[93] === 1'bz) || SAXISRQTDATA_delay[93]; // rv 1 + assign SAXISRQTDATA_in[94] = (SAXISRQTDATA[94] === 1'bz) || SAXISRQTDATA_delay[94]; // rv 1 + assign SAXISRQTDATA_in[95] = (SAXISRQTDATA[95] === 1'bz) || SAXISRQTDATA_delay[95]; // rv 1 + assign SAXISRQTDATA_in[96] = (SAXISRQTDATA[96] === 1'bz) || SAXISRQTDATA_delay[96]; // rv 1 + assign SAXISRQTDATA_in[97] = (SAXISRQTDATA[97] === 1'bz) || SAXISRQTDATA_delay[97]; // rv 1 + assign SAXISRQTDATA_in[98] = (SAXISRQTDATA[98] === 1'bz) || SAXISRQTDATA_delay[98]; // rv 1 + assign SAXISRQTDATA_in[99] = (SAXISRQTDATA[99] === 1'bz) || SAXISRQTDATA_delay[99]; // rv 1 + assign SAXISRQTDATA_in[9] = (SAXISRQTDATA[9] === 1'bz) || SAXISRQTDATA_delay[9]; // rv 1 + assign SAXISRQTKEEP_in[0] = (SAXISRQTKEEP[0] !== 1'bz) && SAXISRQTKEEP_delay[0]; // rv 0 + assign SAXISRQTKEEP_in[1] = (SAXISRQTKEEP[1] !== 1'bz) && SAXISRQTKEEP_delay[1]; // rv 0 + assign SAXISRQTKEEP_in[2] = (SAXISRQTKEEP[2] !== 1'bz) && SAXISRQTKEEP_delay[2]; // rv 0 + assign SAXISRQTKEEP_in[3] = (SAXISRQTKEEP[3] !== 1'bz) && SAXISRQTKEEP_delay[3]; // rv 0 + assign SAXISRQTKEEP_in[4] = (SAXISRQTKEEP[4] !== 1'bz) && SAXISRQTKEEP_delay[4]; // rv 0 + assign SAXISRQTKEEP_in[5] = (SAXISRQTKEEP[5] !== 1'bz) && SAXISRQTKEEP_delay[5]; // rv 0 + assign SAXISRQTKEEP_in[6] = (SAXISRQTKEEP[6] !== 1'bz) && SAXISRQTKEEP_delay[6]; // rv 0 + assign SAXISRQTKEEP_in[7] = (SAXISRQTKEEP[7] !== 1'bz) && SAXISRQTKEEP_delay[7]; // rv 0 + assign SAXISRQTLAST_in = (SAXISRQTLAST === 1'bz) || SAXISRQTLAST_delay; // rv 1 + assign SAXISRQTUSER_in[0] = (SAXISRQTUSER[0] === 1'bz) || SAXISRQTUSER_delay[0]; // rv 1 + assign SAXISRQTUSER_in[10] = (SAXISRQTUSER[10] === 1'bz) || SAXISRQTUSER_delay[10]; // rv 1 + assign SAXISRQTUSER_in[11] = (SAXISRQTUSER[11] === 1'bz) || SAXISRQTUSER_delay[11]; // rv 1 + assign SAXISRQTUSER_in[12] = (SAXISRQTUSER[12] === 1'bz) || SAXISRQTUSER_delay[12]; // rv 1 + assign SAXISRQTUSER_in[13] = (SAXISRQTUSER[13] === 1'bz) || SAXISRQTUSER_delay[13]; // rv 1 + assign SAXISRQTUSER_in[14] = (SAXISRQTUSER[14] === 1'bz) || SAXISRQTUSER_delay[14]; // rv 1 + assign SAXISRQTUSER_in[15] = (SAXISRQTUSER[15] === 1'bz) || SAXISRQTUSER_delay[15]; // rv 1 + assign SAXISRQTUSER_in[16] = (SAXISRQTUSER[16] === 1'bz) || SAXISRQTUSER_delay[16]; // rv 1 + assign SAXISRQTUSER_in[17] = (SAXISRQTUSER[17] === 1'bz) || SAXISRQTUSER_delay[17]; // rv 1 + assign SAXISRQTUSER_in[18] = (SAXISRQTUSER[18] === 1'bz) || SAXISRQTUSER_delay[18]; // rv 1 + assign SAXISRQTUSER_in[19] = (SAXISRQTUSER[19] === 1'bz) || SAXISRQTUSER_delay[19]; // rv 1 + assign SAXISRQTUSER_in[1] = (SAXISRQTUSER[1] === 1'bz) || SAXISRQTUSER_delay[1]; // rv 1 + assign SAXISRQTUSER_in[20] = (SAXISRQTUSER[20] === 1'bz) || SAXISRQTUSER_delay[20]; // rv 1 + assign SAXISRQTUSER_in[21] = (SAXISRQTUSER[21] === 1'bz) || SAXISRQTUSER_delay[21]; // rv 1 + assign SAXISRQTUSER_in[22] = (SAXISRQTUSER[22] === 1'bz) || SAXISRQTUSER_delay[22]; // rv 1 + assign SAXISRQTUSER_in[23] = (SAXISRQTUSER[23] === 1'bz) || SAXISRQTUSER_delay[23]; // rv 1 + assign SAXISRQTUSER_in[24] = (SAXISRQTUSER[24] === 1'bz) || SAXISRQTUSER_delay[24]; // rv 1 + assign SAXISRQTUSER_in[25] = (SAXISRQTUSER[25] === 1'bz) || SAXISRQTUSER_delay[25]; // rv 1 + assign SAXISRQTUSER_in[26] = (SAXISRQTUSER[26] === 1'bz) || SAXISRQTUSER_delay[26]; // rv 1 + assign SAXISRQTUSER_in[27] = (SAXISRQTUSER[27] === 1'bz) || SAXISRQTUSER_delay[27]; // rv 1 + assign SAXISRQTUSER_in[28] = (SAXISRQTUSER[28] === 1'bz) || SAXISRQTUSER_delay[28]; // rv 1 + assign SAXISRQTUSER_in[29] = (SAXISRQTUSER[29] === 1'bz) || SAXISRQTUSER_delay[29]; // rv 1 + assign SAXISRQTUSER_in[2] = (SAXISRQTUSER[2] === 1'bz) || SAXISRQTUSER_delay[2]; // rv 1 + assign SAXISRQTUSER_in[30] = (SAXISRQTUSER[30] === 1'bz) || SAXISRQTUSER_delay[30]; // rv 1 + assign SAXISRQTUSER_in[31] = (SAXISRQTUSER[31] === 1'bz) || SAXISRQTUSER_delay[31]; // rv 1 + assign SAXISRQTUSER_in[32] = (SAXISRQTUSER[32] === 1'bz) || SAXISRQTUSER_delay[32]; // rv 1 + assign SAXISRQTUSER_in[33] = (SAXISRQTUSER[33] === 1'bz) || SAXISRQTUSER_delay[33]; // rv 1 + assign SAXISRQTUSER_in[34] = (SAXISRQTUSER[34] === 1'bz) || SAXISRQTUSER_delay[34]; // rv 1 + assign SAXISRQTUSER_in[35] = (SAXISRQTUSER[35] === 1'bz) || SAXISRQTUSER_delay[35]; // rv 1 + assign SAXISRQTUSER_in[36] = (SAXISRQTUSER[36] === 1'bz) || SAXISRQTUSER_delay[36]; // rv 1 + assign SAXISRQTUSER_in[37] = (SAXISRQTUSER[37] === 1'bz) || SAXISRQTUSER_delay[37]; // rv 1 + assign SAXISRQTUSER_in[38] = (SAXISRQTUSER[38] === 1'bz) || SAXISRQTUSER_delay[38]; // rv 1 + assign SAXISRQTUSER_in[39] = (SAXISRQTUSER[39] === 1'bz) || SAXISRQTUSER_delay[39]; // rv 1 + assign SAXISRQTUSER_in[3] = (SAXISRQTUSER[3] === 1'bz) || SAXISRQTUSER_delay[3]; // rv 1 + assign SAXISRQTUSER_in[40] = (SAXISRQTUSER[40] === 1'bz) || SAXISRQTUSER_delay[40]; // rv 1 + assign SAXISRQTUSER_in[41] = (SAXISRQTUSER[41] === 1'bz) || SAXISRQTUSER_delay[41]; // rv 1 + assign SAXISRQTUSER_in[42] = (SAXISRQTUSER[42] === 1'bz) || SAXISRQTUSER_delay[42]; // rv 1 + assign SAXISRQTUSER_in[43] = (SAXISRQTUSER[43] === 1'bz) || SAXISRQTUSER_delay[43]; // rv 1 + assign SAXISRQTUSER_in[44] = (SAXISRQTUSER[44] === 1'bz) || SAXISRQTUSER_delay[44]; // rv 1 + assign SAXISRQTUSER_in[45] = (SAXISRQTUSER[45] === 1'bz) || SAXISRQTUSER_delay[45]; // rv 1 + assign SAXISRQTUSER_in[46] = (SAXISRQTUSER[46] === 1'bz) || SAXISRQTUSER_delay[46]; // rv 1 + assign SAXISRQTUSER_in[47] = (SAXISRQTUSER[47] === 1'bz) || SAXISRQTUSER_delay[47]; // rv 1 + assign SAXISRQTUSER_in[48] = (SAXISRQTUSER[48] === 1'bz) || SAXISRQTUSER_delay[48]; // rv 1 + assign SAXISRQTUSER_in[49] = (SAXISRQTUSER[49] === 1'bz) || SAXISRQTUSER_delay[49]; // rv 1 + assign SAXISRQTUSER_in[4] = (SAXISRQTUSER[4] === 1'bz) || SAXISRQTUSER_delay[4]; // rv 1 + assign SAXISRQTUSER_in[50] = (SAXISRQTUSER[50] === 1'bz) || SAXISRQTUSER_delay[50]; // rv 1 + assign SAXISRQTUSER_in[51] = (SAXISRQTUSER[51] === 1'bz) || SAXISRQTUSER_delay[51]; // rv 1 + assign SAXISRQTUSER_in[52] = (SAXISRQTUSER[52] === 1'bz) || SAXISRQTUSER_delay[52]; // rv 1 + assign SAXISRQTUSER_in[53] = (SAXISRQTUSER[53] === 1'bz) || SAXISRQTUSER_delay[53]; // rv 1 + assign SAXISRQTUSER_in[54] = (SAXISRQTUSER[54] === 1'bz) || SAXISRQTUSER_delay[54]; // rv 1 + assign SAXISRQTUSER_in[55] = (SAXISRQTUSER[55] === 1'bz) || SAXISRQTUSER_delay[55]; // rv 1 + assign SAXISRQTUSER_in[56] = (SAXISRQTUSER[56] === 1'bz) || SAXISRQTUSER_delay[56]; // rv 1 + assign SAXISRQTUSER_in[57] = (SAXISRQTUSER[57] === 1'bz) || SAXISRQTUSER_delay[57]; // rv 1 + assign SAXISRQTUSER_in[58] = (SAXISRQTUSER[58] === 1'bz) || SAXISRQTUSER_delay[58]; // rv 1 + assign SAXISRQTUSER_in[59] = (SAXISRQTUSER[59] === 1'bz) || SAXISRQTUSER_delay[59]; // rv 1 + assign SAXISRQTUSER_in[5] = (SAXISRQTUSER[5] === 1'bz) || SAXISRQTUSER_delay[5]; // rv 1 + assign SAXISRQTUSER_in[60] = (SAXISRQTUSER[60] === 1'bz) || SAXISRQTUSER_delay[60]; // rv 1 + assign SAXISRQTUSER_in[61] = (SAXISRQTUSER[61] === 1'bz) || SAXISRQTUSER_delay[61]; // rv 1 + assign SAXISRQTUSER_in[6] = (SAXISRQTUSER[6] === 1'bz) || SAXISRQTUSER_delay[6]; // rv 1 + assign SAXISRQTUSER_in[7] = (SAXISRQTUSER[7] === 1'bz) || SAXISRQTUSER_delay[7]; // rv 1 + assign SAXISRQTUSER_in[8] = (SAXISRQTUSER[8] === 1'bz) || SAXISRQTUSER_delay[8]; // rv 1 + assign SAXISRQTUSER_in[9] = (SAXISRQTUSER[9] === 1'bz) || SAXISRQTUSER_delay[9]; // rv 1 + assign SAXISRQTVALID_in = (SAXISRQTVALID !== 1'bz) && SAXISRQTVALID_delay; // rv 0 + assign USERCLKEN_in = (USERCLKEN !== 1'bz) && USERCLKEN_delay; // rv 0 + assign USERSPAREIN_in[0] = (USERSPAREIN[0] === 1'bz) || USERSPAREIN_delay[0]; // rv 1 + assign USERSPAREIN_in[10] = (USERSPAREIN[10] === 1'bz) || USERSPAREIN_delay[10]; // rv 1 + assign USERSPAREIN_in[11] = (USERSPAREIN[11] === 1'bz) || USERSPAREIN_delay[11]; // rv 1 + assign USERSPAREIN_in[12] = (USERSPAREIN[12] === 1'bz) || USERSPAREIN_delay[12]; // rv 1 + assign USERSPAREIN_in[13] = (USERSPAREIN[13] === 1'bz) || USERSPAREIN_delay[13]; // rv 1 + assign USERSPAREIN_in[14] = (USERSPAREIN[14] === 1'bz) || USERSPAREIN_delay[14]; // rv 1 + assign USERSPAREIN_in[15] = (USERSPAREIN[15] === 1'bz) || USERSPAREIN_delay[15]; // rv 1 + assign USERSPAREIN_in[16] = (USERSPAREIN[16] === 1'bz) || USERSPAREIN_delay[16]; // rv 1 + assign USERSPAREIN_in[17] = (USERSPAREIN[17] === 1'bz) || USERSPAREIN_delay[17]; // rv 1 + assign USERSPAREIN_in[18] = (USERSPAREIN[18] === 1'bz) || USERSPAREIN_delay[18]; // rv 1 + assign USERSPAREIN_in[19] = (USERSPAREIN[19] === 1'bz) || USERSPAREIN_delay[19]; // rv 1 + assign USERSPAREIN_in[1] = (USERSPAREIN[1] === 1'bz) || USERSPAREIN_delay[1]; // rv 1 + assign USERSPAREIN_in[20] = (USERSPAREIN[20] === 1'bz) || USERSPAREIN_delay[20]; // rv 1 + assign USERSPAREIN_in[21] = (USERSPAREIN[21] === 1'bz) || USERSPAREIN_delay[21]; // rv 1 + assign USERSPAREIN_in[22] = (USERSPAREIN[22] === 1'bz) || USERSPAREIN_delay[22]; // rv 1 + assign USERSPAREIN_in[23] = (USERSPAREIN[23] === 1'bz) || USERSPAREIN_delay[23]; // rv 1 + assign USERSPAREIN_in[24] = (USERSPAREIN[24] === 1'bz) || USERSPAREIN_delay[24]; // rv 1 + assign USERSPAREIN_in[25] = (USERSPAREIN[25] === 1'bz) || USERSPAREIN_delay[25]; // rv 1 + assign USERSPAREIN_in[26] = (USERSPAREIN[26] === 1'bz) || USERSPAREIN_delay[26]; // rv 1 + assign USERSPAREIN_in[27] = (USERSPAREIN[27] === 1'bz) || USERSPAREIN_delay[27]; // rv 1 + assign USERSPAREIN_in[28] = (USERSPAREIN[28] === 1'bz) || USERSPAREIN_delay[28]; // rv 1 + assign USERSPAREIN_in[29] = (USERSPAREIN[29] === 1'bz) || USERSPAREIN_delay[29]; // rv 1 + assign USERSPAREIN_in[2] = (USERSPAREIN[2] === 1'bz) || USERSPAREIN_delay[2]; // rv 1 + assign USERSPAREIN_in[30] = (USERSPAREIN[30] === 1'bz) || USERSPAREIN_delay[30]; // rv 1 + assign USERSPAREIN_in[31] = (USERSPAREIN[31] === 1'bz) || USERSPAREIN_delay[31]; // rv 1 + assign USERSPAREIN_in[3] = (USERSPAREIN[3] === 1'bz) || USERSPAREIN_delay[3]; // rv 1 + assign USERSPAREIN_in[4] = (USERSPAREIN[4] === 1'bz) || USERSPAREIN_delay[4]; // rv 1 + assign USERSPAREIN_in[5] = (USERSPAREIN[5] === 1'bz) || USERSPAREIN_delay[5]; // rv 1 + assign USERSPAREIN_in[6] = (USERSPAREIN[6] === 1'bz) || USERSPAREIN_delay[6]; // rv 1 + assign USERSPAREIN_in[7] = (USERSPAREIN[7] === 1'bz) || USERSPAREIN_delay[7]; // rv 1 + assign USERSPAREIN_in[8] = (USERSPAREIN[8] === 1'bz) || USERSPAREIN_delay[8]; // rv 1 + assign USERSPAREIN_in[9] = (USERSPAREIN[9] === 1'bz) || USERSPAREIN_delay[9]; // rv 1 +`else + assign AXIUSERIN_in[0] = (AXIUSERIN[0] !== 1'bz) && AXIUSERIN[0]; // rv 0 + assign AXIUSERIN_in[1] = (AXIUSERIN[1] !== 1'bz) && AXIUSERIN[1]; // rv 0 + assign AXIUSERIN_in[2] = (AXIUSERIN[2] !== 1'bz) && AXIUSERIN[2]; // rv 0 + assign AXIUSERIN_in[3] = (AXIUSERIN[3] !== 1'bz) && AXIUSERIN[3]; // rv 0 + assign AXIUSERIN_in[4] = (AXIUSERIN[4] !== 1'bz) && AXIUSERIN[4]; // rv 0 + assign AXIUSERIN_in[5] = (AXIUSERIN[5] !== 1'bz) && AXIUSERIN[5]; // rv 0 + assign AXIUSERIN_in[6] = (AXIUSERIN[6] !== 1'bz) && AXIUSERIN[6]; // rv 0 + assign AXIUSERIN_in[7] = (AXIUSERIN[7] !== 1'bz) && AXIUSERIN[7]; // rv 0 + assign CCIXOPTIMIZEDTLPTXANDRXENABLE_in = (CCIXOPTIMIZEDTLPTXANDRXENABLE !== 1'bz) && CCIXOPTIMIZEDTLPTXANDRXENABLE; // rv 0 + assign CCIXRXTLPFORWARDED0_in = (CCIXRXTLPFORWARDED0 !== 1'bz) && CCIXRXTLPFORWARDED0; // rv 0 + assign CCIXRXTLPFORWARDED1_in = (CCIXRXTLPFORWARDED1 !== 1'bz) && CCIXRXTLPFORWARDED1; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[0] = (CCIXRXTLPFORWARDEDLENGTH0[0] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[0]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[1] = (CCIXRXTLPFORWARDEDLENGTH0[1] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[1]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[2] = (CCIXRXTLPFORWARDEDLENGTH0[2] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[2]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[3] = (CCIXRXTLPFORWARDEDLENGTH0[3] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[3]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[4] = (CCIXRXTLPFORWARDEDLENGTH0[4] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[4]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH0_in[5] = (CCIXRXTLPFORWARDEDLENGTH0[5] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH0[5]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[0] = (CCIXRXTLPFORWARDEDLENGTH1[0] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[0]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[1] = (CCIXRXTLPFORWARDEDLENGTH1[1] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[1]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[2] = (CCIXRXTLPFORWARDEDLENGTH1[2] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[2]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[3] = (CCIXRXTLPFORWARDEDLENGTH1[3] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[3]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[4] = (CCIXRXTLPFORWARDEDLENGTH1[4] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[4]; // rv 0 + assign CCIXRXTLPFORWARDEDLENGTH1_in[5] = (CCIXRXTLPFORWARDEDLENGTH1[5] !== 1'bz) && CCIXRXTLPFORWARDEDLENGTH1[5]; // rv 0 + assign CFGCONFIGSPACEENABLE_in = (CFGCONFIGSPACEENABLE === 1'bz) || CFGCONFIGSPACEENABLE; // rv 1 + assign CFGDEVIDPF0_in[0] = (CFGDEVIDPF0[0] !== 1'bz) && CFGDEVIDPF0[0]; // rv 0 + assign CFGDEVIDPF0_in[10] = (CFGDEVIDPF0[10] !== 1'bz) && CFGDEVIDPF0[10]; // rv 0 + assign CFGDEVIDPF0_in[11] = (CFGDEVIDPF0[11] !== 1'bz) && CFGDEVIDPF0[11]; // rv 0 + assign CFGDEVIDPF0_in[12] = (CFGDEVIDPF0[12] !== 1'bz) && CFGDEVIDPF0[12]; // rv 0 + assign CFGDEVIDPF0_in[13] = (CFGDEVIDPF0[13] !== 1'bz) && CFGDEVIDPF0[13]; // rv 0 + assign CFGDEVIDPF0_in[14] = (CFGDEVIDPF0[14] !== 1'bz) && CFGDEVIDPF0[14]; // rv 0 + assign CFGDEVIDPF0_in[15] = (CFGDEVIDPF0[15] !== 1'bz) && CFGDEVIDPF0[15]; // rv 0 + assign CFGDEVIDPF0_in[1] = (CFGDEVIDPF0[1] !== 1'bz) && CFGDEVIDPF0[1]; // rv 0 + assign CFGDEVIDPF0_in[2] = (CFGDEVIDPF0[2] !== 1'bz) && CFGDEVIDPF0[2]; // rv 0 + assign CFGDEVIDPF0_in[3] = (CFGDEVIDPF0[3] !== 1'bz) && CFGDEVIDPF0[3]; // rv 0 + assign CFGDEVIDPF0_in[4] = (CFGDEVIDPF0[4] !== 1'bz) && CFGDEVIDPF0[4]; // rv 0 + assign CFGDEVIDPF0_in[5] = (CFGDEVIDPF0[5] !== 1'bz) && CFGDEVIDPF0[5]; // rv 0 + assign CFGDEVIDPF0_in[6] = (CFGDEVIDPF0[6] !== 1'bz) && CFGDEVIDPF0[6]; // rv 0 + assign CFGDEVIDPF0_in[7] = (CFGDEVIDPF0[7] !== 1'bz) && CFGDEVIDPF0[7]; // rv 0 + assign CFGDEVIDPF0_in[8] = (CFGDEVIDPF0[8] !== 1'bz) && CFGDEVIDPF0[8]; // rv 0 + assign CFGDEVIDPF0_in[9] = (CFGDEVIDPF0[9] !== 1'bz) && CFGDEVIDPF0[9]; // rv 0 + assign CFGDEVIDPF1_in[0] = (CFGDEVIDPF1[0] !== 1'bz) && CFGDEVIDPF1[0]; // rv 0 + assign CFGDEVIDPF1_in[10] = (CFGDEVIDPF1[10] !== 1'bz) && CFGDEVIDPF1[10]; // rv 0 + assign CFGDEVIDPF1_in[11] = (CFGDEVIDPF1[11] !== 1'bz) && CFGDEVIDPF1[11]; // rv 0 + assign CFGDEVIDPF1_in[12] = (CFGDEVIDPF1[12] !== 1'bz) && CFGDEVIDPF1[12]; // rv 0 + assign CFGDEVIDPF1_in[13] = (CFGDEVIDPF1[13] !== 1'bz) && CFGDEVIDPF1[13]; // rv 0 + assign CFGDEVIDPF1_in[14] = (CFGDEVIDPF1[14] !== 1'bz) && CFGDEVIDPF1[14]; // rv 0 + assign CFGDEVIDPF1_in[15] = (CFGDEVIDPF1[15] !== 1'bz) && CFGDEVIDPF1[15]; // rv 0 + assign CFGDEVIDPF1_in[1] = (CFGDEVIDPF1[1] !== 1'bz) && CFGDEVIDPF1[1]; // rv 0 + assign CFGDEVIDPF1_in[2] = (CFGDEVIDPF1[2] !== 1'bz) && CFGDEVIDPF1[2]; // rv 0 + assign CFGDEVIDPF1_in[3] = (CFGDEVIDPF1[3] !== 1'bz) && CFGDEVIDPF1[3]; // rv 0 + assign CFGDEVIDPF1_in[4] = (CFGDEVIDPF1[4] !== 1'bz) && CFGDEVIDPF1[4]; // rv 0 + assign CFGDEVIDPF1_in[5] = (CFGDEVIDPF1[5] !== 1'bz) && CFGDEVIDPF1[5]; // rv 0 + assign CFGDEVIDPF1_in[6] = (CFGDEVIDPF1[6] !== 1'bz) && CFGDEVIDPF1[6]; // rv 0 + assign CFGDEVIDPF1_in[7] = (CFGDEVIDPF1[7] !== 1'bz) && CFGDEVIDPF1[7]; // rv 0 + assign CFGDEVIDPF1_in[8] = (CFGDEVIDPF1[8] !== 1'bz) && CFGDEVIDPF1[8]; // rv 0 + assign CFGDEVIDPF1_in[9] = (CFGDEVIDPF1[9] !== 1'bz) && CFGDEVIDPF1[9]; // rv 0 + assign CFGDEVIDPF2_in[0] = (CFGDEVIDPF2[0] !== 1'bz) && CFGDEVIDPF2[0]; // rv 0 + assign CFGDEVIDPF2_in[10] = (CFGDEVIDPF2[10] !== 1'bz) && CFGDEVIDPF2[10]; // rv 0 + assign CFGDEVIDPF2_in[11] = (CFGDEVIDPF2[11] !== 1'bz) && CFGDEVIDPF2[11]; // rv 0 + assign CFGDEVIDPF2_in[12] = (CFGDEVIDPF2[12] !== 1'bz) && CFGDEVIDPF2[12]; // rv 0 + assign CFGDEVIDPF2_in[13] = (CFGDEVIDPF2[13] !== 1'bz) && CFGDEVIDPF2[13]; // rv 0 + assign CFGDEVIDPF2_in[14] = (CFGDEVIDPF2[14] !== 1'bz) && CFGDEVIDPF2[14]; // rv 0 + assign CFGDEVIDPF2_in[15] = (CFGDEVIDPF2[15] !== 1'bz) && CFGDEVIDPF2[15]; // rv 0 + assign CFGDEVIDPF2_in[1] = (CFGDEVIDPF2[1] !== 1'bz) && CFGDEVIDPF2[1]; // rv 0 + assign CFGDEVIDPF2_in[2] = (CFGDEVIDPF2[2] !== 1'bz) && CFGDEVIDPF2[2]; // rv 0 + assign CFGDEVIDPF2_in[3] = (CFGDEVIDPF2[3] !== 1'bz) && CFGDEVIDPF2[3]; // rv 0 + assign CFGDEVIDPF2_in[4] = (CFGDEVIDPF2[4] !== 1'bz) && CFGDEVIDPF2[4]; // rv 0 + assign CFGDEVIDPF2_in[5] = (CFGDEVIDPF2[5] !== 1'bz) && CFGDEVIDPF2[5]; // rv 0 + assign CFGDEVIDPF2_in[6] = (CFGDEVIDPF2[6] !== 1'bz) && CFGDEVIDPF2[6]; // rv 0 + assign CFGDEVIDPF2_in[7] = (CFGDEVIDPF2[7] !== 1'bz) && CFGDEVIDPF2[7]; // rv 0 + assign CFGDEVIDPF2_in[8] = (CFGDEVIDPF2[8] !== 1'bz) && CFGDEVIDPF2[8]; // rv 0 + assign CFGDEVIDPF2_in[9] = (CFGDEVIDPF2[9] !== 1'bz) && CFGDEVIDPF2[9]; // rv 0 + assign CFGDEVIDPF3_in[0] = (CFGDEVIDPF3[0] !== 1'bz) && CFGDEVIDPF3[0]; // rv 0 + assign CFGDEVIDPF3_in[10] = (CFGDEVIDPF3[10] !== 1'bz) && CFGDEVIDPF3[10]; // rv 0 + assign CFGDEVIDPF3_in[11] = (CFGDEVIDPF3[11] !== 1'bz) && CFGDEVIDPF3[11]; // rv 0 + assign CFGDEVIDPF3_in[12] = (CFGDEVIDPF3[12] !== 1'bz) && CFGDEVIDPF3[12]; // rv 0 + assign CFGDEVIDPF3_in[13] = (CFGDEVIDPF3[13] !== 1'bz) && CFGDEVIDPF3[13]; // rv 0 + assign CFGDEVIDPF3_in[14] = (CFGDEVIDPF3[14] !== 1'bz) && CFGDEVIDPF3[14]; // rv 0 + assign CFGDEVIDPF3_in[15] = (CFGDEVIDPF3[15] !== 1'bz) && CFGDEVIDPF3[15]; // rv 0 + assign CFGDEVIDPF3_in[1] = (CFGDEVIDPF3[1] !== 1'bz) && CFGDEVIDPF3[1]; // rv 0 + assign CFGDEVIDPF3_in[2] = (CFGDEVIDPF3[2] !== 1'bz) && CFGDEVIDPF3[2]; // rv 0 + assign CFGDEVIDPF3_in[3] = (CFGDEVIDPF3[3] !== 1'bz) && CFGDEVIDPF3[3]; // rv 0 + assign CFGDEVIDPF3_in[4] = (CFGDEVIDPF3[4] !== 1'bz) && CFGDEVIDPF3[4]; // rv 0 + assign CFGDEVIDPF3_in[5] = (CFGDEVIDPF3[5] !== 1'bz) && CFGDEVIDPF3[5]; // rv 0 + assign CFGDEVIDPF3_in[6] = (CFGDEVIDPF3[6] !== 1'bz) && CFGDEVIDPF3[6]; // rv 0 + assign CFGDEVIDPF3_in[7] = (CFGDEVIDPF3[7] !== 1'bz) && CFGDEVIDPF3[7]; // rv 0 + assign CFGDEVIDPF3_in[8] = (CFGDEVIDPF3[8] !== 1'bz) && CFGDEVIDPF3[8]; // rv 0 + assign CFGDEVIDPF3_in[9] = (CFGDEVIDPF3[9] !== 1'bz) && CFGDEVIDPF3[9]; // rv 0 + assign CFGDSBUSNUMBER_in[0] = (CFGDSBUSNUMBER[0] !== 1'bz) && CFGDSBUSNUMBER[0]; // rv 0 + assign CFGDSBUSNUMBER_in[1] = (CFGDSBUSNUMBER[1] !== 1'bz) && CFGDSBUSNUMBER[1]; // rv 0 + assign CFGDSBUSNUMBER_in[2] = (CFGDSBUSNUMBER[2] !== 1'bz) && CFGDSBUSNUMBER[2]; // rv 0 + assign CFGDSBUSNUMBER_in[3] = (CFGDSBUSNUMBER[3] !== 1'bz) && CFGDSBUSNUMBER[3]; // rv 0 + assign CFGDSBUSNUMBER_in[4] = (CFGDSBUSNUMBER[4] !== 1'bz) && CFGDSBUSNUMBER[4]; // rv 0 + assign CFGDSBUSNUMBER_in[5] = (CFGDSBUSNUMBER[5] !== 1'bz) && CFGDSBUSNUMBER[5]; // rv 0 + assign CFGDSBUSNUMBER_in[6] = (CFGDSBUSNUMBER[6] !== 1'bz) && CFGDSBUSNUMBER[6]; // rv 0 + assign CFGDSBUSNUMBER_in[7] = (CFGDSBUSNUMBER[7] !== 1'bz) && CFGDSBUSNUMBER[7]; // rv 0 + assign CFGDSDEVICENUMBER_in[0] = (CFGDSDEVICENUMBER[0] !== 1'bz) && CFGDSDEVICENUMBER[0]; // rv 0 + assign CFGDSDEVICENUMBER_in[1] = (CFGDSDEVICENUMBER[1] !== 1'bz) && CFGDSDEVICENUMBER[1]; // rv 0 + assign CFGDSDEVICENUMBER_in[2] = (CFGDSDEVICENUMBER[2] !== 1'bz) && CFGDSDEVICENUMBER[2]; // rv 0 + assign CFGDSDEVICENUMBER_in[3] = (CFGDSDEVICENUMBER[3] !== 1'bz) && CFGDSDEVICENUMBER[3]; // rv 0 + assign CFGDSDEVICENUMBER_in[4] = (CFGDSDEVICENUMBER[4] !== 1'bz) && CFGDSDEVICENUMBER[4]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[0] = (CFGDSFUNCTIONNUMBER[0] !== 1'bz) && CFGDSFUNCTIONNUMBER[0]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[1] = (CFGDSFUNCTIONNUMBER[1] !== 1'bz) && CFGDSFUNCTIONNUMBER[1]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[2] = (CFGDSFUNCTIONNUMBER[2] !== 1'bz) && CFGDSFUNCTIONNUMBER[2]; // rv 0 + assign CFGDSN_in[0] = (CFGDSN[0] !== 1'bz) && CFGDSN[0]; // rv 0 + assign CFGDSN_in[10] = (CFGDSN[10] !== 1'bz) && CFGDSN[10]; // rv 0 + assign CFGDSN_in[11] = (CFGDSN[11] !== 1'bz) && CFGDSN[11]; // rv 0 + assign CFGDSN_in[12] = (CFGDSN[12] !== 1'bz) && CFGDSN[12]; // rv 0 + assign CFGDSN_in[13] = (CFGDSN[13] !== 1'bz) && CFGDSN[13]; // rv 0 + assign CFGDSN_in[14] = (CFGDSN[14] !== 1'bz) && CFGDSN[14]; // rv 0 + assign CFGDSN_in[15] = (CFGDSN[15] !== 1'bz) && CFGDSN[15]; // rv 0 + assign CFGDSN_in[16] = (CFGDSN[16] !== 1'bz) && CFGDSN[16]; // rv 0 + assign CFGDSN_in[17] = (CFGDSN[17] !== 1'bz) && CFGDSN[17]; // rv 0 + assign CFGDSN_in[18] = (CFGDSN[18] !== 1'bz) && CFGDSN[18]; // rv 0 + assign CFGDSN_in[19] = (CFGDSN[19] !== 1'bz) && CFGDSN[19]; // rv 0 + assign CFGDSN_in[1] = (CFGDSN[1] !== 1'bz) && CFGDSN[1]; // rv 0 + assign CFGDSN_in[20] = (CFGDSN[20] !== 1'bz) && CFGDSN[20]; // rv 0 + assign CFGDSN_in[21] = (CFGDSN[21] !== 1'bz) && CFGDSN[21]; // rv 0 + assign CFGDSN_in[22] = (CFGDSN[22] !== 1'bz) && CFGDSN[22]; // rv 0 + assign CFGDSN_in[23] = (CFGDSN[23] !== 1'bz) && CFGDSN[23]; // rv 0 + assign CFGDSN_in[24] = (CFGDSN[24] !== 1'bz) && CFGDSN[24]; // rv 0 + assign CFGDSN_in[25] = (CFGDSN[25] !== 1'bz) && CFGDSN[25]; // rv 0 + assign CFGDSN_in[26] = (CFGDSN[26] !== 1'bz) && CFGDSN[26]; // rv 0 + assign CFGDSN_in[27] = (CFGDSN[27] !== 1'bz) && CFGDSN[27]; // rv 0 + assign CFGDSN_in[28] = (CFGDSN[28] !== 1'bz) && CFGDSN[28]; // rv 0 + assign CFGDSN_in[29] = (CFGDSN[29] !== 1'bz) && CFGDSN[29]; // rv 0 + assign CFGDSN_in[2] = (CFGDSN[2] !== 1'bz) && CFGDSN[2]; // rv 0 + assign CFGDSN_in[30] = (CFGDSN[30] !== 1'bz) && CFGDSN[30]; // rv 0 + assign CFGDSN_in[31] = (CFGDSN[31] !== 1'bz) && CFGDSN[31]; // rv 0 + assign CFGDSN_in[32] = (CFGDSN[32] !== 1'bz) && CFGDSN[32]; // rv 0 + assign CFGDSN_in[33] = (CFGDSN[33] !== 1'bz) && CFGDSN[33]; // rv 0 + assign CFGDSN_in[34] = (CFGDSN[34] !== 1'bz) && CFGDSN[34]; // rv 0 + assign CFGDSN_in[35] = (CFGDSN[35] !== 1'bz) && CFGDSN[35]; // rv 0 + assign CFGDSN_in[36] = (CFGDSN[36] !== 1'bz) && CFGDSN[36]; // rv 0 + assign CFGDSN_in[37] = (CFGDSN[37] !== 1'bz) && CFGDSN[37]; // rv 0 + assign CFGDSN_in[38] = (CFGDSN[38] !== 1'bz) && CFGDSN[38]; // rv 0 + assign CFGDSN_in[39] = (CFGDSN[39] !== 1'bz) && CFGDSN[39]; // rv 0 + assign CFGDSN_in[3] = (CFGDSN[3] !== 1'bz) && CFGDSN[3]; // rv 0 + assign CFGDSN_in[40] = (CFGDSN[40] !== 1'bz) && CFGDSN[40]; // rv 0 + assign CFGDSN_in[41] = (CFGDSN[41] !== 1'bz) && CFGDSN[41]; // rv 0 + assign CFGDSN_in[42] = (CFGDSN[42] !== 1'bz) && CFGDSN[42]; // rv 0 + assign CFGDSN_in[43] = (CFGDSN[43] !== 1'bz) && CFGDSN[43]; // rv 0 + assign CFGDSN_in[44] = (CFGDSN[44] !== 1'bz) && CFGDSN[44]; // rv 0 + assign CFGDSN_in[45] = (CFGDSN[45] !== 1'bz) && CFGDSN[45]; // rv 0 + assign CFGDSN_in[46] = (CFGDSN[46] !== 1'bz) && CFGDSN[46]; // rv 0 + assign CFGDSN_in[47] = (CFGDSN[47] !== 1'bz) && CFGDSN[47]; // rv 0 + assign CFGDSN_in[48] = (CFGDSN[48] !== 1'bz) && CFGDSN[48]; // rv 0 + assign CFGDSN_in[49] = (CFGDSN[49] !== 1'bz) && CFGDSN[49]; // rv 0 + assign CFGDSN_in[4] = (CFGDSN[4] !== 1'bz) && CFGDSN[4]; // rv 0 + assign CFGDSN_in[50] = (CFGDSN[50] !== 1'bz) && CFGDSN[50]; // rv 0 + assign CFGDSN_in[51] = (CFGDSN[51] !== 1'bz) && CFGDSN[51]; // rv 0 + assign CFGDSN_in[52] = (CFGDSN[52] !== 1'bz) && CFGDSN[52]; // rv 0 + assign CFGDSN_in[53] = (CFGDSN[53] !== 1'bz) && CFGDSN[53]; // rv 0 + assign CFGDSN_in[54] = (CFGDSN[54] !== 1'bz) && CFGDSN[54]; // rv 0 + assign CFGDSN_in[55] = (CFGDSN[55] !== 1'bz) && CFGDSN[55]; // rv 0 + assign CFGDSN_in[56] = (CFGDSN[56] !== 1'bz) && CFGDSN[56]; // rv 0 + assign CFGDSN_in[57] = (CFGDSN[57] !== 1'bz) && CFGDSN[57]; // rv 0 + assign CFGDSN_in[58] = (CFGDSN[58] !== 1'bz) && CFGDSN[58]; // rv 0 + assign CFGDSN_in[59] = (CFGDSN[59] !== 1'bz) && CFGDSN[59]; // rv 0 + assign CFGDSN_in[5] = (CFGDSN[5] !== 1'bz) && CFGDSN[5]; // rv 0 + assign CFGDSN_in[60] = (CFGDSN[60] !== 1'bz) && CFGDSN[60]; // rv 0 + assign CFGDSN_in[61] = (CFGDSN[61] !== 1'bz) && CFGDSN[61]; // rv 0 + assign CFGDSN_in[62] = (CFGDSN[62] !== 1'bz) && CFGDSN[62]; // rv 0 + assign CFGDSN_in[63] = (CFGDSN[63] !== 1'bz) && CFGDSN[63]; // rv 0 + assign CFGDSN_in[6] = (CFGDSN[6] !== 1'bz) && CFGDSN[6]; // rv 0 + assign CFGDSN_in[7] = (CFGDSN[7] !== 1'bz) && CFGDSN[7]; // rv 0 + assign CFGDSN_in[8] = (CFGDSN[8] !== 1'bz) && CFGDSN[8]; // rv 0 + assign CFGDSN_in[9] = (CFGDSN[9] !== 1'bz) && CFGDSN[9]; // rv 0 + assign CFGDSPORTNUMBER_in[0] = (CFGDSPORTNUMBER[0] !== 1'bz) && CFGDSPORTNUMBER[0]; // rv 0 + assign CFGDSPORTNUMBER_in[1] = (CFGDSPORTNUMBER[1] !== 1'bz) && CFGDSPORTNUMBER[1]; // rv 0 + assign CFGDSPORTNUMBER_in[2] = (CFGDSPORTNUMBER[2] !== 1'bz) && CFGDSPORTNUMBER[2]; // rv 0 + assign CFGDSPORTNUMBER_in[3] = (CFGDSPORTNUMBER[3] !== 1'bz) && CFGDSPORTNUMBER[3]; // rv 0 + assign CFGDSPORTNUMBER_in[4] = (CFGDSPORTNUMBER[4] !== 1'bz) && CFGDSPORTNUMBER[4]; // rv 0 + assign CFGDSPORTNUMBER_in[5] = (CFGDSPORTNUMBER[5] !== 1'bz) && CFGDSPORTNUMBER[5]; // rv 0 + assign CFGDSPORTNUMBER_in[6] = (CFGDSPORTNUMBER[6] !== 1'bz) && CFGDSPORTNUMBER[6]; // rv 0 + assign CFGDSPORTNUMBER_in[7] = (CFGDSPORTNUMBER[7] !== 1'bz) && CFGDSPORTNUMBER[7]; // rv 0 + assign CFGERRCORIN_in = (CFGERRCORIN !== 1'bz) && CFGERRCORIN; // rv 0 + assign CFGERRUNCORIN_in = (CFGERRUNCORIN !== 1'bz) && CFGERRUNCORIN; // rv 0 + assign CFGEXTREADDATAVALID_in = (CFGEXTREADDATAVALID !== 1'bz) && CFGEXTREADDATAVALID; // rv 0 + assign CFGEXTREADDATA_in[0] = (CFGEXTREADDATA[0] !== 1'bz) && CFGEXTREADDATA[0]; // rv 0 + assign CFGEXTREADDATA_in[10] = (CFGEXTREADDATA[10] !== 1'bz) && CFGEXTREADDATA[10]; // rv 0 + assign CFGEXTREADDATA_in[11] = (CFGEXTREADDATA[11] !== 1'bz) && CFGEXTREADDATA[11]; // rv 0 + assign CFGEXTREADDATA_in[12] = (CFGEXTREADDATA[12] !== 1'bz) && CFGEXTREADDATA[12]; // rv 0 + assign CFGEXTREADDATA_in[13] = (CFGEXTREADDATA[13] !== 1'bz) && CFGEXTREADDATA[13]; // rv 0 + assign CFGEXTREADDATA_in[14] = (CFGEXTREADDATA[14] !== 1'bz) && CFGEXTREADDATA[14]; // rv 0 + assign CFGEXTREADDATA_in[15] = (CFGEXTREADDATA[15] !== 1'bz) && CFGEXTREADDATA[15]; // rv 0 + assign CFGEXTREADDATA_in[16] = (CFGEXTREADDATA[16] !== 1'bz) && CFGEXTREADDATA[16]; // rv 0 + assign CFGEXTREADDATA_in[17] = (CFGEXTREADDATA[17] !== 1'bz) && CFGEXTREADDATA[17]; // rv 0 + assign CFGEXTREADDATA_in[18] = (CFGEXTREADDATA[18] !== 1'bz) && CFGEXTREADDATA[18]; // rv 0 + assign CFGEXTREADDATA_in[19] = (CFGEXTREADDATA[19] !== 1'bz) && CFGEXTREADDATA[19]; // rv 0 + assign CFGEXTREADDATA_in[1] = (CFGEXTREADDATA[1] !== 1'bz) && CFGEXTREADDATA[1]; // rv 0 + assign CFGEXTREADDATA_in[20] = (CFGEXTREADDATA[20] !== 1'bz) && CFGEXTREADDATA[20]; // rv 0 + assign CFGEXTREADDATA_in[21] = (CFGEXTREADDATA[21] !== 1'bz) && CFGEXTREADDATA[21]; // rv 0 + assign CFGEXTREADDATA_in[22] = (CFGEXTREADDATA[22] !== 1'bz) && CFGEXTREADDATA[22]; // rv 0 + assign CFGEXTREADDATA_in[23] = (CFGEXTREADDATA[23] !== 1'bz) && CFGEXTREADDATA[23]; // rv 0 + assign CFGEXTREADDATA_in[24] = (CFGEXTREADDATA[24] !== 1'bz) && CFGEXTREADDATA[24]; // rv 0 + assign CFGEXTREADDATA_in[25] = (CFGEXTREADDATA[25] !== 1'bz) && CFGEXTREADDATA[25]; // rv 0 + assign CFGEXTREADDATA_in[26] = (CFGEXTREADDATA[26] !== 1'bz) && CFGEXTREADDATA[26]; // rv 0 + assign CFGEXTREADDATA_in[27] = (CFGEXTREADDATA[27] !== 1'bz) && CFGEXTREADDATA[27]; // rv 0 + assign CFGEXTREADDATA_in[28] = (CFGEXTREADDATA[28] !== 1'bz) && CFGEXTREADDATA[28]; // rv 0 + assign CFGEXTREADDATA_in[29] = (CFGEXTREADDATA[29] !== 1'bz) && CFGEXTREADDATA[29]; // rv 0 + assign CFGEXTREADDATA_in[2] = (CFGEXTREADDATA[2] !== 1'bz) && CFGEXTREADDATA[2]; // rv 0 + assign CFGEXTREADDATA_in[30] = (CFGEXTREADDATA[30] !== 1'bz) && CFGEXTREADDATA[30]; // rv 0 + assign CFGEXTREADDATA_in[31] = (CFGEXTREADDATA[31] !== 1'bz) && CFGEXTREADDATA[31]; // rv 0 + assign CFGEXTREADDATA_in[3] = (CFGEXTREADDATA[3] !== 1'bz) && CFGEXTREADDATA[3]; // rv 0 + assign CFGEXTREADDATA_in[4] = (CFGEXTREADDATA[4] !== 1'bz) && CFGEXTREADDATA[4]; // rv 0 + assign CFGEXTREADDATA_in[5] = (CFGEXTREADDATA[5] !== 1'bz) && CFGEXTREADDATA[5]; // rv 0 + assign CFGEXTREADDATA_in[6] = (CFGEXTREADDATA[6] !== 1'bz) && CFGEXTREADDATA[6]; // rv 0 + assign CFGEXTREADDATA_in[7] = (CFGEXTREADDATA[7] !== 1'bz) && CFGEXTREADDATA[7]; // rv 0 + assign CFGEXTREADDATA_in[8] = (CFGEXTREADDATA[8] !== 1'bz) && CFGEXTREADDATA[8]; // rv 0 + assign CFGEXTREADDATA_in[9] = (CFGEXTREADDATA[9] !== 1'bz) && CFGEXTREADDATA[9]; // rv 0 + assign CFGFCSEL_in[0] = (CFGFCSEL[0] !== 1'bz) && CFGFCSEL[0]; // rv 0 + assign CFGFCSEL_in[1] = (CFGFCSEL[1] !== 1'bz) && CFGFCSEL[1]; // rv 0 + assign CFGFCSEL_in[2] = (CFGFCSEL[2] !== 1'bz) && CFGFCSEL[2]; // rv 0 + assign CFGFCVCSEL_in = (CFGFCVCSEL !== 1'bz) && CFGFCVCSEL; // rv 0 + assign CFGFLRDONE_in[0] = (CFGFLRDONE[0] !== 1'bz) && CFGFLRDONE[0]; // rv 0 + assign CFGFLRDONE_in[1] = (CFGFLRDONE[1] !== 1'bz) && CFGFLRDONE[1]; // rv 0 + assign CFGFLRDONE_in[2] = (CFGFLRDONE[2] !== 1'bz) && CFGFLRDONE[2]; // rv 0 + assign CFGFLRDONE_in[3] = (CFGFLRDONE[3] !== 1'bz) && CFGFLRDONE[3]; // rv 0 + assign CFGHOTRESETIN_in = (CFGHOTRESETIN !== 1'bz) && CFGHOTRESETIN; // rv 0 + assign CFGINTERRUPTINT_in[0] = (CFGINTERRUPTINT[0] !== 1'bz) && CFGINTERRUPTINT[0]; // rv 0 + assign CFGINTERRUPTINT_in[1] = (CFGINTERRUPTINT[1] !== 1'bz) && CFGINTERRUPTINT[1]; // rv 0 + assign CFGINTERRUPTINT_in[2] = (CFGINTERRUPTINT[2] !== 1'bz) && CFGINTERRUPTINT[2]; // rv 0 + assign CFGINTERRUPTINT_in[3] = (CFGINTERRUPTINT[3] !== 1'bz) && CFGINTERRUPTINT[3]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[0] = (CFGINTERRUPTMSIATTR[0] !== 1'bz) && CFGINTERRUPTMSIATTR[0]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[1] = (CFGINTERRUPTMSIATTR[1] !== 1'bz) && CFGINTERRUPTMSIATTR[1]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[2] = (CFGINTERRUPTMSIATTR[2] !== 1'bz) && CFGINTERRUPTMSIATTR[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[0] = (CFGINTERRUPTMSIFUNCTIONNUMBER[0] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[0]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[1] = (CFGINTERRUPTMSIFUNCTIONNUMBER[1] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[1]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[2] = (CFGINTERRUPTMSIFUNCTIONNUMBER[2] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[3] = (CFGINTERRUPTMSIFUNCTIONNUMBER[3] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[3]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[4] = (CFGINTERRUPTMSIFUNCTIONNUMBER[4] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[4]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[5] = (CFGINTERRUPTMSIFUNCTIONNUMBER[5] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[5]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[6] = (CFGINTERRUPTMSIFUNCTIONNUMBER[6] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[6]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[7] = (CFGINTERRUPTMSIFUNCTIONNUMBER[7] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[0] = (CFGINTERRUPTMSIINT[0] !== 1'bz) && CFGINTERRUPTMSIINT[0]; // rv 0 + assign CFGINTERRUPTMSIINT_in[10] = (CFGINTERRUPTMSIINT[10] !== 1'bz) && CFGINTERRUPTMSIINT[10]; // rv 0 + assign CFGINTERRUPTMSIINT_in[11] = (CFGINTERRUPTMSIINT[11] !== 1'bz) && CFGINTERRUPTMSIINT[11]; // rv 0 + assign CFGINTERRUPTMSIINT_in[12] = (CFGINTERRUPTMSIINT[12] !== 1'bz) && CFGINTERRUPTMSIINT[12]; // rv 0 + assign CFGINTERRUPTMSIINT_in[13] = (CFGINTERRUPTMSIINT[13] !== 1'bz) && CFGINTERRUPTMSIINT[13]; // rv 0 + assign CFGINTERRUPTMSIINT_in[14] = (CFGINTERRUPTMSIINT[14] !== 1'bz) && CFGINTERRUPTMSIINT[14]; // rv 0 + assign CFGINTERRUPTMSIINT_in[15] = (CFGINTERRUPTMSIINT[15] !== 1'bz) && CFGINTERRUPTMSIINT[15]; // rv 0 + assign CFGINTERRUPTMSIINT_in[16] = (CFGINTERRUPTMSIINT[16] !== 1'bz) && CFGINTERRUPTMSIINT[16]; // rv 0 + assign CFGINTERRUPTMSIINT_in[17] = (CFGINTERRUPTMSIINT[17] !== 1'bz) && CFGINTERRUPTMSIINT[17]; // rv 0 + assign CFGINTERRUPTMSIINT_in[18] = (CFGINTERRUPTMSIINT[18] !== 1'bz) && CFGINTERRUPTMSIINT[18]; // rv 0 + assign CFGINTERRUPTMSIINT_in[19] = (CFGINTERRUPTMSIINT[19] !== 1'bz) && CFGINTERRUPTMSIINT[19]; // rv 0 + assign CFGINTERRUPTMSIINT_in[1] = (CFGINTERRUPTMSIINT[1] !== 1'bz) && CFGINTERRUPTMSIINT[1]; // rv 0 + assign CFGINTERRUPTMSIINT_in[20] = (CFGINTERRUPTMSIINT[20] !== 1'bz) && CFGINTERRUPTMSIINT[20]; // rv 0 + assign CFGINTERRUPTMSIINT_in[21] = (CFGINTERRUPTMSIINT[21] !== 1'bz) && CFGINTERRUPTMSIINT[21]; // rv 0 + assign CFGINTERRUPTMSIINT_in[22] = (CFGINTERRUPTMSIINT[22] !== 1'bz) && CFGINTERRUPTMSIINT[22]; // rv 0 + assign CFGINTERRUPTMSIINT_in[23] = (CFGINTERRUPTMSIINT[23] !== 1'bz) && CFGINTERRUPTMSIINT[23]; // rv 0 + assign CFGINTERRUPTMSIINT_in[24] = (CFGINTERRUPTMSIINT[24] !== 1'bz) && CFGINTERRUPTMSIINT[24]; // rv 0 + assign CFGINTERRUPTMSIINT_in[25] = (CFGINTERRUPTMSIINT[25] !== 1'bz) && CFGINTERRUPTMSIINT[25]; // rv 0 + assign CFGINTERRUPTMSIINT_in[26] = (CFGINTERRUPTMSIINT[26] !== 1'bz) && CFGINTERRUPTMSIINT[26]; // rv 0 + assign CFGINTERRUPTMSIINT_in[27] = (CFGINTERRUPTMSIINT[27] !== 1'bz) && CFGINTERRUPTMSIINT[27]; // rv 0 + assign CFGINTERRUPTMSIINT_in[28] = (CFGINTERRUPTMSIINT[28] !== 1'bz) && CFGINTERRUPTMSIINT[28]; // rv 0 + assign CFGINTERRUPTMSIINT_in[29] = (CFGINTERRUPTMSIINT[29] !== 1'bz) && CFGINTERRUPTMSIINT[29]; // rv 0 + assign CFGINTERRUPTMSIINT_in[2] = (CFGINTERRUPTMSIINT[2] !== 1'bz) && CFGINTERRUPTMSIINT[2]; // rv 0 + assign CFGINTERRUPTMSIINT_in[30] = (CFGINTERRUPTMSIINT[30] !== 1'bz) && CFGINTERRUPTMSIINT[30]; // rv 0 + assign CFGINTERRUPTMSIINT_in[31] = (CFGINTERRUPTMSIINT[31] !== 1'bz) && CFGINTERRUPTMSIINT[31]; // rv 0 + assign CFGINTERRUPTMSIINT_in[3] = (CFGINTERRUPTMSIINT[3] !== 1'bz) && CFGINTERRUPTMSIINT[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[4] = (CFGINTERRUPTMSIINT[4] !== 1'bz) && CFGINTERRUPTMSIINT[4]; // rv 0 + assign CFGINTERRUPTMSIINT_in[5] = (CFGINTERRUPTMSIINT[5] !== 1'bz) && CFGINTERRUPTMSIINT[5]; // rv 0 + assign CFGINTERRUPTMSIINT_in[6] = (CFGINTERRUPTMSIINT[6] !== 1'bz) && CFGINTERRUPTMSIINT[6]; // rv 0 + assign CFGINTERRUPTMSIINT_in[7] = (CFGINTERRUPTMSIINT[7] !== 1'bz) && CFGINTERRUPTMSIINT[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[8] = (CFGINTERRUPTMSIINT[8] !== 1'bz) && CFGINTERRUPTMSIINT[8]; // rv 0 + assign CFGINTERRUPTMSIINT_in[9] = (CFGINTERRUPTMSIINT[9] !== 1'bz) && CFGINTERRUPTMSIINT[9]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[0] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[1] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[0] = (CFGINTERRUPTMSIPENDINGSTATUS[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[10] = (CFGINTERRUPTMSIPENDINGSTATUS[10] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[10]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[11] = (CFGINTERRUPTMSIPENDINGSTATUS[11] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[11]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[12] = (CFGINTERRUPTMSIPENDINGSTATUS[12] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[12]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[13] = (CFGINTERRUPTMSIPENDINGSTATUS[13] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[13]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[14] = (CFGINTERRUPTMSIPENDINGSTATUS[14] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[14]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[15] = (CFGINTERRUPTMSIPENDINGSTATUS[15] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[15]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[16] = (CFGINTERRUPTMSIPENDINGSTATUS[16] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[16]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[17] = (CFGINTERRUPTMSIPENDINGSTATUS[17] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[17]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[18] = (CFGINTERRUPTMSIPENDINGSTATUS[18] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[18]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[19] = (CFGINTERRUPTMSIPENDINGSTATUS[19] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[19]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[1] = (CFGINTERRUPTMSIPENDINGSTATUS[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[20] = (CFGINTERRUPTMSIPENDINGSTATUS[20] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[20]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[21] = (CFGINTERRUPTMSIPENDINGSTATUS[21] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[21]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[22] = (CFGINTERRUPTMSIPENDINGSTATUS[22] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[22]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[23] = (CFGINTERRUPTMSIPENDINGSTATUS[23] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[23]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[24] = (CFGINTERRUPTMSIPENDINGSTATUS[24] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[24]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[25] = (CFGINTERRUPTMSIPENDINGSTATUS[25] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[25]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[26] = (CFGINTERRUPTMSIPENDINGSTATUS[26] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[26]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[27] = (CFGINTERRUPTMSIPENDINGSTATUS[27] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[27]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[28] = (CFGINTERRUPTMSIPENDINGSTATUS[28] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[28]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[29] = (CFGINTERRUPTMSIPENDINGSTATUS[29] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[29]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[2] = (CFGINTERRUPTMSIPENDINGSTATUS[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[30] = (CFGINTERRUPTMSIPENDINGSTATUS[30] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[30]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[31] = (CFGINTERRUPTMSIPENDINGSTATUS[31] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[31]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[3] = (CFGINTERRUPTMSIPENDINGSTATUS[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[4] = (CFGINTERRUPTMSIPENDINGSTATUS[4] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[4]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[5] = (CFGINTERRUPTMSIPENDINGSTATUS[5] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[5]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[6] = (CFGINTERRUPTMSIPENDINGSTATUS[6] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[6]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[7] = (CFGINTERRUPTMSIPENDINGSTATUS[7] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[7]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[8] = (CFGINTERRUPTMSIPENDINGSTATUS[8] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[8]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[9] = (CFGINTERRUPTMSIPENDINGSTATUS[9] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS[9]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[0] = (CFGINTERRUPTMSISELECT[0] !== 1'bz) && CFGINTERRUPTMSISELECT[0]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[1] = (CFGINTERRUPTMSISELECT[1] !== 1'bz) && CFGINTERRUPTMSISELECT[1]; // rv 0 + assign CFGINTERRUPTMSITPHPRESENT_in = (CFGINTERRUPTMSITPHPRESENT !== 1'bz) && CFGINTERRUPTMSITPHPRESENT; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[0] = (CFGINTERRUPTMSITPHSTTAG[0] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[0]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[1] = (CFGINTERRUPTMSITPHSTTAG[1] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[1]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[2] = (CFGINTERRUPTMSITPHSTTAG[2] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[2]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[3] = (CFGINTERRUPTMSITPHSTTAG[3] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[3]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[4] = (CFGINTERRUPTMSITPHSTTAG[4] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[4]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[5] = (CFGINTERRUPTMSITPHSTTAG[5] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[5]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[6] = (CFGINTERRUPTMSITPHSTTAG[6] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[6]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[7] = (CFGINTERRUPTMSITPHSTTAG[7] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG[7]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[0] = (CFGINTERRUPTMSITPHTYPE[0] !== 1'bz) && CFGINTERRUPTMSITPHTYPE[0]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[1] = (CFGINTERRUPTMSITPHTYPE[1] !== 1'bz) && CFGINTERRUPTMSITPHTYPE[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[0] = (CFGINTERRUPTMSIXADDRESS[0] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[0]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[10] = (CFGINTERRUPTMSIXADDRESS[10] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[10]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[11] = (CFGINTERRUPTMSIXADDRESS[11] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[11]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[12] = (CFGINTERRUPTMSIXADDRESS[12] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[12]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[13] = (CFGINTERRUPTMSIXADDRESS[13] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[13]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[14] = (CFGINTERRUPTMSIXADDRESS[14] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[14]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[15] = (CFGINTERRUPTMSIXADDRESS[15] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[15]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[16] = (CFGINTERRUPTMSIXADDRESS[16] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[16]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[17] = (CFGINTERRUPTMSIXADDRESS[17] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[17]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[18] = (CFGINTERRUPTMSIXADDRESS[18] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[18]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[19] = (CFGINTERRUPTMSIXADDRESS[19] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[19]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[1] = (CFGINTERRUPTMSIXADDRESS[1] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[20] = (CFGINTERRUPTMSIXADDRESS[20] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[20]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[21] = (CFGINTERRUPTMSIXADDRESS[21] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[21]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[22] = (CFGINTERRUPTMSIXADDRESS[22] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[22]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[23] = (CFGINTERRUPTMSIXADDRESS[23] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[23]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[24] = (CFGINTERRUPTMSIXADDRESS[24] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[24]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[25] = (CFGINTERRUPTMSIXADDRESS[25] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[25]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[26] = (CFGINTERRUPTMSIXADDRESS[26] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[26]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[27] = (CFGINTERRUPTMSIXADDRESS[27] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[27]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[28] = (CFGINTERRUPTMSIXADDRESS[28] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[28]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[29] = (CFGINTERRUPTMSIXADDRESS[29] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[29]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[2] = (CFGINTERRUPTMSIXADDRESS[2] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[2]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[30] = (CFGINTERRUPTMSIXADDRESS[30] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[30]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[31] = (CFGINTERRUPTMSIXADDRESS[31] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[31]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[32] = (CFGINTERRUPTMSIXADDRESS[32] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[32]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[33] = (CFGINTERRUPTMSIXADDRESS[33] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[33]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[34] = (CFGINTERRUPTMSIXADDRESS[34] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[34]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[35] = (CFGINTERRUPTMSIXADDRESS[35] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[35]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[36] = (CFGINTERRUPTMSIXADDRESS[36] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[36]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[37] = (CFGINTERRUPTMSIXADDRESS[37] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[37]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[38] = (CFGINTERRUPTMSIXADDRESS[38] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[38]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[39] = (CFGINTERRUPTMSIXADDRESS[39] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[39]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[3] = (CFGINTERRUPTMSIXADDRESS[3] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[3]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[40] = (CFGINTERRUPTMSIXADDRESS[40] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[40]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[41] = (CFGINTERRUPTMSIXADDRESS[41] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[41]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[42] = (CFGINTERRUPTMSIXADDRESS[42] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[42]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[43] = (CFGINTERRUPTMSIXADDRESS[43] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[43]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[44] = (CFGINTERRUPTMSIXADDRESS[44] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[44]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[45] = (CFGINTERRUPTMSIXADDRESS[45] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[45]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[46] = (CFGINTERRUPTMSIXADDRESS[46] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[46]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[47] = (CFGINTERRUPTMSIXADDRESS[47] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[47]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[48] = (CFGINTERRUPTMSIXADDRESS[48] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[48]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[49] = (CFGINTERRUPTMSIXADDRESS[49] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[49]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[4] = (CFGINTERRUPTMSIXADDRESS[4] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[4]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[50] = (CFGINTERRUPTMSIXADDRESS[50] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[50]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[51] = (CFGINTERRUPTMSIXADDRESS[51] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[51]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[52] = (CFGINTERRUPTMSIXADDRESS[52] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[52]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[53] = (CFGINTERRUPTMSIXADDRESS[53] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[53]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[54] = (CFGINTERRUPTMSIXADDRESS[54] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[54]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[55] = (CFGINTERRUPTMSIXADDRESS[55] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[55]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[56] = (CFGINTERRUPTMSIXADDRESS[56] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[56]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[57] = (CFGINTERRUPTMSIXADDRESS[57] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[57]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[58] = (CFGINTERRUPTMSIXADDRESS[58] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[58]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[59] = (CFGINTERRUPTMSIXADDRESS[59] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[59]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[5] = (CFGINTERRUPTMSIXADDRESS[5] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[5]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[60] = (CFGINTERRUPTMSIXADDRESS[60] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[60]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[61] = (CFGINTERRUPTMSIXADDRESS[61] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[61]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[62] = (CFGINTERRUPTMSIXADDRESS[62] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[62]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[63] = (CFGINTERRUPTMSIXADDRESS[63] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[63]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[6] = (CFGINTERRUPTMSIXADDRESS[6] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[6]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[7] = (CFGINTERRUPTMSIXADDRESS[7] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[7]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[8] = (CFGINTERRUPTMSIXADDRESS[8] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[8]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[9] = (CFGINTERRUPTMSIXADDRESS[9] !== 1'bz) && CFGINTERRUPTMSIXADDRESS[9]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[0] = (CFGINTERRUPTMSIXDATA[0] !== 1'bz) && CFGINTERRUPTMSIXDATA[0]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[10] = (CFGINTERRUPTMSIXDATA[10] !== 1'bz) && CFGINTERRUPTMSIXDATA[10]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[11] = (CFGINTERRUPTMSIXDATA[11] !== 1'bz) && CFGINTERRUPTMSIXDATA[11]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[12] = (CFGINTERRUPTMSIXDATA[12] !== 1'bz) && CFGINTERRUPTMSIXDATA[12]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[13] = (CFGINTERRUPTMSIXDATA[13] !== 1'bz) && CFGINTERRUPTMSIXDATA[13]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[14] = (CFGINTERRUPTMSIXDATA[14] !== 1'bz) && CFGINTERRUPTMSIXDATA[14]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[15] = (CFGINTERRUPTMSIXDATA[15] !== 1'bz) && CFGINTERRUPTMSIXDATA[15]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[16] = (CFGINTERRUPTMSIXDATA[16] !== 1'bz) && CFGINTERRUPTMSIXDATA[16]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[17] = (CFGINTERRUPTMSIXDATA[17] !== 1'bz) && CFGINTERRUPTMSIXDATA[17]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[18] = (CFGINTERRUPTMSIXDATA[18] !== 1'bz) && CFGINTERRUPTMSIXDATA[18]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[19] = (CFGINTERRUPTMSIXDATA[19] !== 1'bz) && CFGINTERRUPTMSIXDATA[19]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[1] = (CFGINTERRUPTMSIXDATA[1] !== 1'bz) && CFGINTERRUPTMSIXDATA[1]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[20] = (CFGINTERRUPTMSIXDATA[20] !== 1'bz) && CFGINTERRUPTMSIXDATA[20]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[21] = (CFGINTERRUPTMSIXDATA[21] !== 1'bz) && CFGINTERRUPTMSIXDATA[21]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[22] = (CFGINTERRUPTMSIXDATA[22] !== 1'bz) && CFGINTERRUPTMSIXDATA[22]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[23] = (CFGINTERRUPTMSIXDATA[23] !== 1'bz) && CFGINTERRUPTMSIXDATA[23]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[24] = (CFGINTERRUPTMSIXDATA[24] !== 1'bz) && CFGINTERRUPTMSIXDATA[24]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[25] = (CFGINTERRUPTMSIXDATA[25] !== 1'bz) && CFGINTERRUPTMSIXDATA[25]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[26] = (CFGINTERRUPTMSIXDATA[26] !== 1'bz) && CFGINTERRUPTMSIXDATA[26]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[27] = (CFGINTERRUPTMSIXDATA[27] !== 1'bz) && CFGINTERRUPTMSIXDATA[27]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[28] = (CFGINTERRUPTMSIXDATA[28] !== 1'bz) && CFGINTERRUPTMSIXDATA[28]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[29] = (CFGINTERRUPTMSIXDATA[29] !== 1'bz) && CFGINTERRUPTMSIXDATA[29]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[2] = (CFGINTERRUPTMSIXDATA[2] !== 1'bz) && CFGINTERRUPTMSIXDATA[2]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[30] = (CFGINTERRUPTMSIXDATA[30] !== 1'bz) && CFGINTERRUPTMSIXDATA[30]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[31] = (CFGINTERRUPTMSIXDATA[31] !== 1'bz) && CFGINTERRUPTMSIXDATA[31]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[3] = (CFGINTERRUPTMSIXDATA[3] !== 1'bz) && CFGINTERRUPTMSIXDATA[3]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[4] = (CFGINTERRUPTMSIXDATA[4] !== 1'bz) && CFGINTERRUPTMSIXDATA[4]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[5] = (CFGINTERRUPTMSIXDATA[5] !== 1'bz) && CFGINTERRUPTMSIXDATA[5]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[6] = (CFGINTERRUPTMSIXDATA[6] !== 1'bz) && CFGINTERRUPTMSIXDATA[6]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[7] = (CFGINTERRUPTMSIXDATA[7] !== 1'bz) && CFGINTERRUPTMSIXDATA[7]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[8] = (CFGINTERRUPTMSIXDATA[8] !== 1'bz) && CFGINTERRUPTMSIXDATA[8]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[9] = (CFGINTERRUPTMSIXDATA[9] !== 1'bz) && CFGINTERRUPTMSIXDATA[9]; // rv 0 + assign CFGINTERRUPTMSIXINT_in = (CFGINTERRUPTMSIXINT !== 1'bz) && CFGINTERRUPTMSIXINT; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[0] = (CFGINTERRUPTMSIXVECPENDING[0] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING[0]; // rv 0 + assign CFGINTERRUPTMSIXVECPENDING_in[1] = (CFGINTERRUPTMSIXVECPENDING[1] !== 1'bz) && CFGINTERRUPTMSIXVECPENDING[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[0] = (CFGINTERRUPTPENDING[0] !== 1'bz) && CFGINTERRUPTPENDING[0]; // rv 0 + assign CFGINTERRUPTPENDING_in[1] = (CFGINTERRUPTPENDING[1] !== 1'bz) && CFGINTERRUPTPENDING[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[2] = (CFGINTERRUPTPENDING[2] !== 1'bz) && CFGINTERRUPTPENDING[2]; // rv 0 + assign CFGINTERRUPTPENDING_in[3] = (CFGINTERRUPTPENDING[3] !== 1'bz) && CFGINTERRUPTPENDING[3]; // rv 0 + assign CFGLINKTRAININGENABLE_in = (CFGLINKTRAININGENABLE === 1'bz) || CFGLINKTRAININGENABLE; // rv 1 + assign CFGMGMTADDR_in[0] = (CFGMGMTADDR[0] !== 1'bz) && CFGMGMTADDR[0]; // rv 0 + assign CFGMGMTADDR_in[1] = (CFGMGMTADDR[1] !== 1'bz) && CFGMGMTADDR[1]; // rv 0 + assign CFGMGMTADDR_in[2] = (CFGMGMTADDR[2] !== 1'bz) && CFGMGMTADDR[2]; // rv 0 + assign CFGMGMTADDR_in[3] = (CFGMGMTADDR[3] !== 1'bz) && CFGMGMTADDR[3]; // rv 0 + assign CFGMGMTADDR_in[4] = (CFGMGMTADDR[4] !== 1'bz) && CFGMGMTADDR[4]; // rv 0 + assign CFGMGMTADDR_in[5] = (CFGMGMTADDR[5] !== 1'bz) && CFGMGMTADDR[5]; // rv 0 + assign CFGMGMTADDR_in[6] = (CFGMGMTADDR[6] !== 1'bz) && CFGMGMTADDR[6]; // rv 0 + assign CFGMGMTADDR_in[7] = (CFGMGMTADDR[7] !== 1'bz) && CFGMGMTADDR[7]; // rv 0 + assign CFGMGMTADDR_in[8] = (CFGMGMTADDR[8] !== 1'bz) && CFGMGMTADDR[8]; // rv 0 + assign CFGMGMTADDR_in[9] = (CFGMGMTADDR[9] !== 1'bz) && CFGMGMTADDR[9]; // rv 0 + assign CFGMGMTBYTEENABLE_in[0] = (CFGMGMTBYTEENABLE[0] !== 1'bz) && CFGMGMTBYTEENABLE[0]; // rv 0 + assign CFGMGMTBYTEENABLE_in[1] = (CFGMGMTBYTEENABLE[1] !== 1'bz) && CFGMGMTBYTEENABLE[1]; // rv 0 + assign CFGMGMTBYTEENABLE_in[2] = (CFGMGMTBYTEENABLE[2] !== 1'bz) && CFGMGMTBYTEENABLE[2]; // rv 0 + assign CFGMGMTBYTEENABLE_in[3] = (CFGMGMTBYTEENABLE[3] !== 1'bz) && CFGMGMTBYTEENABLE[3]; // rv 0 + assign CFGMGMTDEBUGACCESS_in = (CFGMGMTDEBUGACCESS !== 1'bz) && CFGMGMTDEBUGACCESS; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[0] = (CFGMGMTFUNCTIONNUMBER[0] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[0]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[1] = (CFGMGMTFUNCTIONNUMBER[1] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[1]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[2] = (CFGMGMTFUNCTIONNUMBER[2] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[2]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[3] = (CFGMGMTFUNCTIONNUMBER[3] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[3]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[4] = (CFGMGMTFUNCTIONNUMBER[4] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[4]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[5] = (CFGMGMTFUNCTIONNUMBER[5] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[5]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[6] = (CFGMGMTFUNCTIONNUMBER[6] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[6]; // rv 0 + assign CFGMGMTFUNCTIONNUMBER_in[7] = (CFGMGMTFUNCTIONNUMBER[7] !== 1'bz) && CFGMGMTFUNCTIONNUMBER[7]; // rv 0 + assign CFGMGMTREAD_in = (CFGMGMTREAD !== 1'bz) && CFGMGMTREAD; // rv 0 + assign CFGMGMTWRITEDATA_in[0] = (CFGMGMTWRITEDATA[0] !== 1'bz) && CFGMGMTWRITEDATA[0]; // rv 0 + assign CFGMGMTWRITEDATA_in[10] = (CFGMGMTWRITEDATA[10] !== 1'bz) && CFGMGMTWRITEDATA[10]; // rv 0 + assign CFGMGMTWRITEDATA_in[11] = (CFGMGMTWRITEDATA[11] !== 1'bz) && CFGMGMTWRITEDATA[11]; // rv 0 + assign CFGMGMTWRITEDATA_in[12] = (CFGMGMTWRITEDATA[12] !== 1'bz) && CFGMGMTWRITEDATA[12]; // rv 0 + assign CFGMGMTWRITEDATA_in[13] = (CFGMGMTWRITEDATA[13] !== 1'bz) && CFGMGMTWRITEDATA[13]; // rv 0 + assign CFGMGMTWRITEDATA_in[14] = (CFGMGMTWRITEDATA[14] !== 1'bz) && CFGMGMTWRITEDATA[14]; // rv 0 + assign CFGMGMTWRITEDATA_in[15] = (CFGMGMTWRITEDATA[15] !== 1'bz) && CFGMGMTWRITEDATA[15]; // rv 0 + assign CFGMGMTWRITEDATA_in[16] = (CFGMGMTWRITEDATA[16] !== 1'bz) && CFGMGMTWRITEDATA[16]; // rv 0 + assign CFGMGMTWRITEDATA_in[17] = (CFGMGMTWRITEDATA[17] !== 1'bz) && CFGMGMTWRITEDATA[17]; // rv 0 + assign CFGMGMTWRITEDATA_in[18] = (CFGMGMTWRITEDATA[18] !== 1'bz) && CFGMGMTWRITEDATA[18]; // rv 0 + assign CFGMGMTWRITEDATA_in[19] = (CFGMGMTWRITEDATA[19] !== 1'bz) && CFGMGMTWRITEDATA[19]; // rv 0 + assign CFGMGMTWRITEDATA_in[1] = (CFGMGMTWRITEDATA[1] !== 1'bz) && CFGMGMTWRITEDATA[1]; // rv 0 + assign CFGMGMTWRITEDATA_in[20] = (CFGMGMTWRITEDATA[20] !== 1'bz) && CFGMGMTWRITEDATA[20]; // rv 0 + assign CFGMGMTWRITEDATA_in[21] = (CFGMGMTWRITEDATA[21] !== 1'bz) && CFGMGMTWRITEDATA[21]; // rv 0 + assign CFGMGMTWRITEDATA_in[22] = (CFGMGMTWRITEDATA[22] !== 1'bz) && CFGMGMTWRITEDATA[22]; // rv 0 + assign CFGMGMTWRITEDATA_in[23] = (CFGMGMTWRITEDATA[23] !== 1'bz) && CFGMGMTWRITEDATA[23]; // rv 0 + assign CFGMGMTWRITEDATA_in[24] = (CFGMGMTWRITEDATA[24] !== 1'bz) && CFGMGMTWRITEDATA[24]; // rv 0 + assign CFGMGMTWRITEDATA_in[25] = (CFGMGMTWRITEDATA[25] !== 1'bz) && CFGMGMTWRITEDATA[25]; // rv 0 + assign CFGMGMTWRITEDATA_in[26] = (CFGMGMTWRITEDATA[26] !== 1'bz) && CFGMGMTWRITEDATA[26]; // rv 0 + assign CFGMGMTWRITEDATA_in[27] = (CFGMGMTWRITEDATA[27] !== 1'bz) && CFGMGMTWRITEDATA[27]; // rv 0 + assign CFGMGMTWRITEDATA_in[28] = (CFGMGMTWRITEDATA[28] !== 1'bz) && CFGMGMTWRITEDATA[28]; // rv 0 + assign CFGMGMTWRITEDATA_in[29] = (CFGMGMTWRITEDATA[29] !== 1'bz) && CFGMGMTWRITEDATA[29]; // rv 0 + assign CFGMGMTWRITEDATA_in[2] = (CFGMGMTWRITEDATA[2] !== 1'bz) && CFGMGMTWRITEDATA[2]; // rv 0 + assign CFGMGMTWRITEDATA_in[30] = (CFGMGMTWRITEDATA[30] !== 1'bz) && CFGMGMTWRITEDATA[30]; // rv 0 + assign CFGMGMTWRITEDATA_in[31] = (CFGMGMTWRITEDATA[31] !== 1'bz) && CFGMGMTWRITEDATA[31]; // rv 0 + assign CFGMGMTWRITEDATA_in[3] = (CFGMGMTWRITEDATA[3] !== 1'bz) && CFGMGMTWRITEDATA[3]; // rv 0 + assign CFGMGMTWRITEDATA_in[4] = (CFGMGMTWRITEDATA[4] !== 1'bz) && CFGMGMTWRITEDATA[4]; // rv 0 + assign CFGMGMTWRITEDATA_in[5] = (CFGMGMTWRITEDATA[5] !== 1'bz) && CFGMGMTWRITEDATA[5]; // rv 0 + assign CFGMGMTWRITEDATA_in[6] = (CFGMGMTWRITEDATA[6] !== 1'bz) && CFGMGMTWRITEDATA[6]; // rv 0 + assign CFGMGMTWRITEDATA_in[7] = (CFGMGMTWRITEDATA[7] !== 1'bz) && CFGMGMTWRITEDATA[7]; // rv 0 + assign CFGMGMTWRITEDATA_in[8] = (CFGMGMTWRITEDATA[8] !== 1'bz) && CFGMGMTWRITEDATA[8]; // rv 0 + assign CFGMGMTWRITEDATA_in[9] = (CFGMGMTWRITEDATA[9] !== 1'bz) && CFGMGMTWRITEDATA[9]; // rv 0 + assign CFGMGMTWRITE_in = (CFGMGMTWRITE !== 1'bz) && CFGMGMTWRITE; // rv 0 + assign CFGMSGTRANSMITDATA_in[0] = (CFGMSGTRANSMITDATA[0] !== 1'bz) && CFGMSGTRANSMITDATA[0]; // rv 0 + assign CFGMSGTRANSMITDATA_in[10] = (CFGMSGTRANSMITDATA[10] !== 1'bz) && CFGMSGTRANSMITDATA[10]; // rv 0 + assign CFGMSGTRANSMITDATA_in[11] = (CFGMSGTRANSMITDATA[11] !== 1'bz) && CFGMSGTRANSMITDATA[11]; // rv 0 + assign CFGMSGTRANSMITDATA_in[12] = (CFGMSGTRANSMITDATA[12] !== 1'bz) && CFGMSGTRANSMITDATA[12]; // rv 0 + assign CFGMSGTRANSMITDATA_in[13] = (CFGMSGTRANSMITDATA[13] !== 1'bz) && CFGMSGTRANSMITDATA[13]; // rv 0 + assign CFGMSGTRANSMITDATA_in[14] = (CFGMSGTRANSMITDATA[14] !== 1'bz) && CFGMSGTRANSMITDATA[14]; // rv 0 + assign CFGMSGTRANSMITDATA_in[15] = (CFGMSGTRANSMITDATA[15] !== 1'bz) && CFGMSGTRANSMITDATA[15]; // rv 0 + assign CFGMSGTRANSMITDATA_in[16] = (CFGMSGTRANSMITDATA[16] !== 1'bz) && CFGMSGTRANSMITDATA[16]; // rv 0 + assign CFGMSGTRANSMITDATA_in[17] = (CFGMSGTRANSMITDATA[17] !== 1'bz) && CFGMSGTRANSMITDATA[17]; // rv 0 + assign CFGMSGTRANSMITDATA_in[18] = (CFGMSGTRANSMITDATA[18] !== 1'bz) && CFGMSGTRANSMITDATA[18]; // rv 0 + assign CFGMSGTRANSMITDATA_in[19] = (CFGMSGTRANSMITDATA[19] !== 1'bz) && CFGMSGTRANSMITDATA[19]; // rv 0 + assign CFGMSGTRANSMITDATA_in[1] = (CFGMSGTRANSMITDATA[1] !== 1'bz) && CFGMSGTRANSMITDATA[1]; // rv 0 + assign CFGMSGTRANSMITDATA_in[20] = (CFGMSGTRANSMITDATA[20] !== 1'bz) && CFGMSGTRANSMITDATA[20]; // rv 0 + assign CFGMSGTRANSMITDATA_in[21] = (CFGMSGTRANSMITDATA[21] !== 1'bz) && CFGMSGTRANSMITDATA[21]; // rv 0 + assign CFGMSGTRANSMITDATA_in[22] = (CFGMSGTRANSMITDATA[22] !== 1'bz) && CFGMSGTRANSMITDATA[22]; // rv 0 + assign CFGMSGTRANSMITDATA_in[23] = (CFGMSGTRANSMITDATA[23] !== 1'bz) && CFGMSGTRANSMITDATA[23]; // rv 0 + assign CFGMSGTRANSMITDATA_in[24] = (CFGMSGTRANSMITDATA[24] !== 1'bz) && CFGMSGTRANSMITDATA[24]; // rv 0 + assign CFGMSGTRANSMITDATA_in[25] = (CFGMSGTRANSMITDATA[25] !== 1'bz) && CFGMSGTRANSMITDATA[25]; // rv 0 + assign CFGMSGTRANSMITDATA_in[26] = (CFGMSGTRANSMITDATA[26] !== 1'bz) && CFGMSGTRANSMITDATA[26]; // rv 0 + assign CFGMSGTRANSMITDATA_in[27] = (CFGMSGTRANSMITDATA[27] !== 1'bz) && CFGMSGTRANSMITDATA[27]; // rv 0 + assign CFGMSGTRANSMITDATA_in[28] = (CFGMSGTRANSMITDATA[28] !== 1'bz) && CFGMSGTRANSMITDATA[28]; // rv 0 + assign CFGMSGTRANSMITDATA_in[29] = (CFGMSGTRANSMITDATA[29] !== 1'bz) && CFGMSGTRANSMITDATA[29]; // rv 0 + assign CFGMSGTRANSMITDATA_in[2] = (CFGMSGTRANSMITDATA[2] !== 1'bz) && CFGMSGTRANSMITDATA[2]; // rv 0 + assign CFGMSGTRANSMITDATA_in[30] = (CFGMSGTRANSMITDATA[30] !== 1'bz) && CFGMSGTRANSMITDATA[30]; // rv 0 + assign CFGMSGTRANSMITDATA_in[31] = (CFGMSGTRANSMITDATA[31] !== 1'bz) && CFGMSGTRANSMITDATA[31]; // rv 0 + assign CFGMSGTRANSMITDATA_in[3] = (CFGMSGTRANSMITDATA[3] !== 1'bz) && CFGMSGTRANSMITDATA[3]; // rv 0 + assign CFGMSGTRANSMITDATA_in[4] = (CFGMSGTRANSMITDATA[4] !== 1'bz) && CFGMSGTRANSMITDATA[4]; // rv 0 + assign CFGMSGTRANSMITDATA_in[5] = (CFGMSGTRANSMITDATA[5] !== 1'bz) && CFGMSGTRANSMITDATA[5]; // rv 0 + assign CFGMSGTRANSMITDATA_in[6] = (CFGMSGTRANSMITDATA[6] !== 1'bz) && CFGMSGTRANSMITDATA[6]; // rv 0 + assign CFGMSGTRANSMITDATA_in[7] = (CFGMSGTRANSMITDATA[7] !== 1'bz) && CFGMSGTRANSMITDATA[7]; // rv 0 + assign CFGMSGTRANSMITDATA_in[8] = (CFGMSGTRANSMITDATA[8] !== 1'bz) && CFGMSGTRANSMITDATA[8]; // rv 0 + assign CFGMSGTRANSMITDATA_in[9] = (CFGMSGTRANSMITDATA[9] !== 1'bz) && CFGMSGTRANSMITDATA[9]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[0] = (CFGMSGTRANSMITTYPE[0] !== 1'bz) && CFGMSGTRANSMITTYPE[0]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[1] = (CFGMSGTRANSMITTYPE[1] !== 1'bz) && CFGMSGTRANSMITTYPE[1]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[2] = (CFGMSGTRANSMITTYPE[2] !== 1'bz) && CFGMSGTRANSMITTYPE[2]; // rv 0 + assign CFGMSGTRANSMIT_in = (CFGMSGTRANSMIT !== 1'bz) && CFGMSGTRANSMIT; // rv 0 + assign CFGMSIXRAMREADDATA_in[0] = (CFGMSIXRAMREADDATA[0] !== 1'bz) && CFGMSIXRAMREADDATA[0]; // rv 0 + assign CFGMSIXRAMREADDATA_in[10] = (CFGMSIXRAMREADDATA[10] !== 1'bz) && CFGMSIXRAMREADDATA[10]; // rv 0 + assign CFGMSIXRAMREADDATA_in[11] = (CFGMSIXRAMREADDATA[11] !== 1'bz) && CFGMSIXRAMREADDATA[11]; // rv 0 + assign CFGMSIXRAMREADDATA_in[12] = (CFGMSIXRAMREADDATA[12] !== 1'bz) && CFGMSIXRAMREADDATA[12]; // rv 0 + assign CFGMSIXRAMREADDATA_in[13] = (CFGMSIXRAMREADDATA[13] !== 1'bz) && CFGMSIXRAMREADDATA[13]; // rv 0 + assign CFGMSIXRAMREADDATA_in[14] = (CFGMSIXRAMREADDATA[14] !== 1'bz) && CFGMSIXRAMREADDATA[14]; // rv 0 + assign CFGMSIXRAMREADDATA_in[15] = (CFGMSIXRAMREADDATA[15] !== 1'bz) && CFGMSIXRAMREADDATA[15]; // rv 0 + assign CFGMSIXRAMREADDATA_in[16] = (CFGMSIXRAMREADDATA[16] !== 1'bz) && CFGMSIXRAMREADDATA[16]; // rv 0 + assign CFGMSIXRAMREADDATA_in[17] = (CFGMSIXRAMREADDATA[17] !== 1'bz) && CFGMSIXRAMREADDATA[17]; // rv 0 + assign CFGMSIXRAMREADDATA_in[18] = (CFGMSIXRAMREADDATA[18] !== 1'bz) && CFGMSIXRAMREADDATA[18]; // rv 0 + assign CFGMSIXRAMREADDATA_in[19] = (CFGMSIXRAMREADDATA[19] !== 1'bz) && CFGMSIXRAMREADDATA[19]; // rv 0 + assign CFGMSIXRAMREADDATA_in[1] = (CFGMSIXRAMREADDATA[1] !== 1'bz) && CFGMSIXRAMREADDATA[1]; // rv 0 + assign CFGMSIXRAMREADDATA_in[20] = (CFGMSIXRAMREADDATA[20] !== 1'bz) && CFGMSIXRAMREADDATA[20]; // rv 0 + assign CFGMSIXRAMREADDATA_in[21] = (CFGMSIXRAMREADDATA[21] !== 1'bz) && CFGMSIXRAMREADDATA[21]; // rv 0 + assign CFGMSIXRAMREADDATA_in[22] = (CFGMSIXRAMREADDATA[22] !== 1'bz) && CFGMSIXRAMREADDATA[22]; // rv 0 + assign CFGMSIXRAMREADDATA_in[23] = (CFGMSIXRAMREADDATA[23] !== 1'bz) && CFGMSIXRAMREADDATA[23]; // rv 0 + assign CFGMSIXRAMREADDATA_in[24] = (CFGMSIXRAMREADDATA[24] !== 1'bz) && CFGMSIXRAMREADDATA[24]; // rv 0 + assign CFGMSIXRAMREADDATA_in[25] = (CFGMSIXRAMREADDATA[25] !== 1'bz) && CFGMSIXRAMREADDATA[25]; // rv 0 + assign CFGMSIXRAMREADDATA_in[26] = (CFGMSIXRAMREADDATA[26] !== 1'bz) && CFGMSIXRAMREADDATA[26]; // rv 0 + assign CFGMSIXRAMREADDATA_in[27] = (CFGMSIXRAMREADDATA[27] !== 1'bz) && CFGMSIXRAMREADDATA[27]; // rv 0 + assign CFGMSIXRAMREADDATA_in[28] = (CFGMSIXRAMREADDATA[28] !== 1'bz) && CFGMSIXRAMREADDATA[28]; // rv 0 + assign CFGMSIXRAMREADDATA_in[29] = (CFGMSIXRAMREADDATA[29] !== 1'bz) && CFGMSIXRAMREADDATA[29]; // rv 0 + assign CFGMSIXRAMREADDATA_in[2] = (CFGMSIXRAMREADDATA[2] !== 1'bz) && CFGMSIXRAMREADDATA[2]; // rv 0 + assign CFGMSIXRAMREADDATA_in[30] = (CFGMSIXRAMREADDATA[30] !== 1'bz) && CFGMSIXRAMREADDATA[30]; // rv 0 + assign CFGMSIXRAMREADDATA_in[31] = (CFGMSIXRAMREADDATA[31] !== 1'bz) && CFGMSIXRAMREADDATA[31]; // rv 0 + assign CFGMSIXRAMREADDATA_in[32] = (CFGMSIXRAMREADDATA[32] !== 1'bz) && CFGMSIXRAMREADDATA[32]; // rv 0 + assign CFGMSIXRAMREADDATA_in[33] = (CFGMSIXRAMREADDATA[33] !== 1'bz) && CFGMSIXRAMREADDATA[33]; // rv 0 + assign CFGMSIXRAMREADDATA_in[34] = (CFGMSIXRAMREADDATA[34] !== 1'bz) && CFGMSIXRAMREADDATA[34]; // rv 0 + assign CFGMSIXRAMREADDATA_in[35] = (CFGMSIXRAMREADDATA[35] !== 1'bz) && CFGMSIXRAMREADDATA[35]; // rv 0 + assign CFGMSIXRAMREADDATA_in[3] = (CFGMSIXRAMREADDATA[3] !== 1'bz) && CFGMSIXRAMREADDATA[3]; // rv 0 + assign CFGMSIXRAMREADDATA_in[4] = (CFGMSIXRAMREADDATA[4] !== 1'bz) && CFGMSIXRAMREADDATA[4]; // rv 0 + assign CFGMSIXRAMREADDATA_in[5] = (CFGMSIXRAMREADDATA[5] !== 1'bz) && CFGMSIXRAMREADDATA[5]; // rv 0 + assign CFGMSIXRAMREADDATA_in[6] = (CFGMSIXRAMREADDATA[6] !== 1'bz) && CFGMSIXRAMREADDATA[6]; // rv 0 + assign CFGMSIXRAMREADDATA_in[7] = (CFGMSIXRAMREADDATA[7] !== 1'bz) && CFGMSIXRAMREADDATA[7]; // rv 0 + assign CFGMSIXRAMREADDATA_in[8] = (CFGMSIXRAMREADDATA[8] !== 1'bz) && CFGMSIXRAMREADDATA[8]; // rv 0 + assign CFGMSIXRAMREADDATA_in[9] = (CFGMSIXRAMREADDATA[9] !== 1'bz) && CFGMSIXRAMREADDATA[9]; // rv 0 + assign CFGPMASPML1ENTRYREJECT_in = (CFGPMASPML1ENTRYREJECT !== 1'bz) && CFGPMASPML1ENTRYREJECT; // rv 0 + assign CFGPMASPMTXL0SENTRYDISABLE_in = (CFGPMASPMTXL0SENTRYDISABLE !== 1'bz) && CFGPMASPMTXL0SENTRYDISABLE; // rv 0 + assign CFGPOWERSTATECHANGEACK_in = (CFGPOWERSTATECHANGEACK === 1'bz) || CFGPOWERSTATECHANGEACK; // rv 1 + assign CFGREQPMTRANSITIONL23READY_in = (CFGREQPMTRANSITIONL23READY !== 1'bz) && CFGREQPMTRANSITIONL23READY; // rv 0 + assign CFGREVIDPF0_in[0] = (CFGREVIDPF0[0] !== 1'bz) && CFGREVIDPF0[0]; // rv 0 + assign CFGREVIDPF0_in[1] = (CFGREVIDPF0[1] !== 1'bz) && CFGREVIDPF0[1]; // rv 0 + assign CFGREVIDPF0_in[2] = (CFGREVIDPF0[2] !== 1'bz) && CFGREVIDPF0[2]; // rv 0 + assign CFGREVIDPF0_in[3] = (CFGREVIDPF0[3] !== 1'bz) && CFGREVIDPF0[3]; // rv 0 + assign CFGREVIDPF0_in[4] = (CFGREVIDPF0[4] !== 1'bz) && CFGREVIDPF0[4]; // rv 0 + assign CFGREVIDPF0_in[5] = (CFGREVIDPF0[5] !== 1'bz) && CFGREVIDPF0[5]; // rv 0 + assign CFGREVIDPF0_in[6] = (CFGREVIDPF0[6] !== 1'bz) && CFGREVIDPF0[6]; // rv 0 + assign CFGREVIDPF0_in[7] = (CFGREVIDPF0[7] !== 1'bz) && CFGREVIDPF0[7]; // rv 0 + assign CFGREVIDPF1_in[0] = (CFGREVIDPF1[0] !== 1'bz) && CFGREVIDPF1[0]; // rv 0 + assign CFGREVIDPF1_in[1] = (CFGREVIDPF1[1] !== 1'bz) && CFGREVIDPF1[1]; // rv 0 + assign CFGREVIDPF1_in[2] = (CFGREVIDPF1[2] !== 1'bz) && CFGREVIDPF1[2]; // rv 0 + assign CFGREVIDPF1_in[3] = (CFGREVIDPF1[3] !== 1'bz) && CFGREVIDPF1[3]; // rv 0 + assign CFGREVIDPF1_in[4] = (CFGREVIDPF1[4] !== 1'bz) && CFGREVIDPF1[4]; // rv 0 + assign CFGREVIDPF1_in[5] = (CFGREVIDPF1[5] !== 1'bz) && CFGREVIDPF1[5]; // rv 0 + assign CFGREVIDPF1_in[6] = (CFGREVIDPF1[6] !== 1'bz) && CFGREVIDPF1[6]; // rv 0 + assign CFGREVIDPF1_in[7] = (CFGREVIDPF1[7] !== 1'bz) && CFGREVIDPF1[7]; // rv 0 + assign CFGREVIDPF2_in[0] = (CFGREVIDPF2[0] !== 1'bz) && CFGREVIDPF2[0]; // rv 0 + assign CFGREVIDPF2_in[1] = (CFGREVIDPF2[1] !== 1'bz) && CFGREVIDPF2[1]; // rv 0 + assign CFGREVIDPF2_in[2] = (CFGREVIDPF2[2] !== 1'bz) && CFGREVIDPF2[2]; // rv 0 + assign CFGREVIDPF2_in[3] = (CFGREVIDPF2[3] !== 1'bz) && CFGREVIDPF2[3]; // rv 0 + assign CFGREVIDPF2_in[4] = (CFGREVIDPF2[4] !== 1'bz) && CFGREVIDPF2[4]; // rv 0 + assign CFGREVIDPF2_in[5] = (CFGREVIDPF2[5] !== 1'bz) && CFGREVIDPF2[5]; // rv 0 + assign CFGREVIDPF2_in[6] = (CFGREVIDPF2[6] !== 1'bz) && CFGREVIDPF2[6]; // rv 0 + assign CFGREVIDPF2_in[7] = (CFGREVIDPF2[7] !== 1'bz) && CFGREVIDPF2[7]; // rv 0 + assign CFGREVIDPF3_in[0] = (CFGREVIDPF3[0] !== 1'bz) && CFGREVIDPF3[0]; // rv 0 + assign CFGREVIDPF3_in[1] = (CFGREVIDPF3[1] !== 1'bz) && CFGREVIDPF3[1]; // rv 0 + assign CFGREVIDPF3_in[2] = (CFGREVIDPF3[2] !== 1'bz) && CFGREVIDPF3[2]; // rv 0 + assign CFGREVIDPF3_in[3] = (CFGREVIDPF3[3] !== 1'bz) && CFGREVIDPF3[3]; // rv 0 + assign CFGREVIDPF3_in[4] = (CFGREVIDPF3[4] !== 1'bz) && CFGREVIDPF3[4]; // rv 0 + assign CFGREVIDPF3_in[5] = (CFGREVIDPF3[5] !== 1'bz) && CFGREVIDPF3[5]; // rv 0 + assign CFGREVIDPF3_in[6] = (CFGREVIDPF3[6] !== 1'bz) && CFGREVIDPF3[6]; // rv 0 + assign CFGREVIDPF3_in[7] = (CFGREVIDPF3[7] !== 1'bz) && CFGREVIDPF3[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[0] = (CFGSUBSYSIDPF0[0] !== 1'bz) && CFGSUBSYSIDPF0[0]; // rv 0 + assign CFGSUBSYSIDPF0_in[10] = (CFGSUBSYSIDPF0[10] !== 1'bz) && CFGSUBSYSIDPF0[10]; // rv 0 + assign CFGSUBSYSIDPF0_in[11] = (CFGSUBSYSIDPF0[11] !== 1'bz) && CFGSUBSYSIDPF0[11]; // rv 0 + assign CFGSUBSYSIDPF0_in[12] = (CFGSUBSYSIDPF0[12] !== 1'bz) && CFGSUBSYSIDPF0[12]; // rv 0 + assign CFGSUBSYSIDPF0_in[13] = (CFGSUBSYSIDPF0[13] !== 1'bz) && CFGSUBSYSIDPF0[13]; // rv 0 + assign CFGSUBSYSIDPF0_in[14] = (CFGSUBSYSIDPF0[14] !== 1'bz) && CFGSUBSYSIDPF0[14]; // rv 0 + assign CFGSUBSYSIDPF0_in[15] = (CFGSUBSYSIDPF0[15] !== 1'bz) && CFGSUBSYSIDPF0[15]; // rv 0 + assign CFGSUBSYSIDPF0_in[1] = (CFGSUBSYSIDPF0[1] !== 1'bz) && CFGSUBSYSIDPF0[1]; // rv 0 + assign CFGSUBSYSIDPF0_in[2] = (CFGSUBSYSIDPF0[2] !== 1'bz) && CFGSUBSYSIDPF0[2]; // rv 0 + assign CFGSUBSYSIDPF0_in[3] = (CFGSUBSYSIDPF0[3] !== 1'bz) && CFGSUBSYSIDPF0[3]; // rv 0 + assign CFGSUBSYSIDPF0_in[4] = (CFGSUBSYSIDPF0[4] !== 1'bz) && CFGSUBSYSIDPF0[4]; // rv 0 + assign CFGSUBSYSIDPF0_in[5] = (CFGSUBSYSIDPF0[5] !== 1'bz) && CFGSUBSYSIDPF0[5]; // rv 0 + assign CFGSUBSYSIDPF0_in[6] = (CFGSUBSYSIDPF0[6] !== 1'bz) && CFGSUBSYSIDPF0[6]; // rv 0 + assign CFGSUBSYSIDPF0_in[7] = (CFGSUBSYSIDPF0[7] !== 1'bz) && CFGSUBSYSIDPF0[7]; // rv 0 + assign CFGSUBSYSIDPF0_in[8] = (CFGSUBSYSIDPF0[8] !== 1'bz) && CFGSUBSYSIDPF0[8]; // rv 0 + assign CFGSUBSYSIDPF0_in[9] = (CFGSUBSYSIDPF0[9] !== 1'bz) && CFGSUBSYSIDPF0[9]; // rv 0 + assign CFGSUBSYSIDPF1_in[0] = (CFGSUBSYSIDPF1[0] !== 1'bz) && CFGSUBSYSIDPF1[0]; // rv 0 + assign CFGSUBSYSIDPF1_in[10] = (CFGSUBSYSIDPF1[10] !== 1'bz) && CFGSUBSYSIDPF1[10]; // rv 0 + assign CFGSUBSYSIDPF1_in[11] = (CFGSUBSYSIDPF1[11] !== 1'bz) && CFGSUBSYSIDPF1[11]; // rv 0 + assign CFGSUBSYSIDPF1_in[12] = (CFGSUBSYSIDPF1[12] !== 1'bz) && CFGSUBSYSIDPF1[12]; // rv 0 + assign CFGSUBSYSIDPF1_in[13] = (CFGSUBSYSIDPF1[13] !== 1'bz) && CFGSUBSYSIDPF1[13]; // rv 0 + assign CFGSUBSYSIDPF1_in[14] = (CFGSUBSYSIDPF1[14] !== 1'bz) && CFGSUBSYSIDPF1[14]; // rv 0 + assign CFGSUBSYSIDPF1_in[15] = (CFGSUBSYSIDPF1[15] !== 1'bz) && CFGSUBSYSIDPF1[15]; // rv 0 + assign CFGSUBSYSIDPF1_in[1] = (CFGSUBSYSIDPF1[1] !== 1'bz) && CFGSUBSYSIDPF1[1]; // rv 0 + assign CFGSUBSYSIDPF1_in[2] = (CFGSUBSYSIDPF1[2] !== 1'bz) && CFGSUBSYSIDPF1[2]; // rv 0 + assign CFGSUBSYSIDPF1_in[3] = (CFGSUBSYSIDPF1[3] !== 1'bz) && CFGSUBSYSIDPF1[3]; // rv 0 + assign CFGSUBSYSIDPF1_in[4] = (CFGSUBSYSIDPF1[4] !== 1'bz) && CFGSUBSYSIDPF1[4]; // rv 0 + assign CFGSUBSYSIDPF1_in[5] = (CFGSUBSYSIDPF1[5] !== 1'bz) && CFGSUBSYSIDPF1[5]; // rv 0 + assign CFGSUBSYSIDPF1_in[6] = (CFGSUBSYSIDPF1[6] !== 1'bz) && CFGSUBSYSIDPF1[6]; // rv 0 + assign CFGSUBSYSIDPF1_in[7] = (CFGSUBSYSIDPF1[7] !== 1'bz) && CFGSUBSYSIDPF1[7]; // rv 0 + assign CFGSUBSYSIDPF1_in[8] = (CFGSUBSYSIDPF1[8] !== 1'bz) && CFGSUBSYSIDPF1[8]; // rv 0 + assign CFGSUBSYSIDPF1_in[9] = (CFGSUBSYSIDPF1[9] !== 1'bz) && CFGSUBSYSIDPF1[9]; // rv 0 + assign CFGSUBSYSIDPF2_in[0] = (CFGSUBSYSIDPF2[0] !== 1'bz) && CFGSUBSYSIDPF2[0]; // rv 0 + assign CFGSUBSYSIDPF2_in[10] = (CFGSUBSYSIDPF2[10] !== 1'bz) && CFGSUBSYSIDPF2[10]; // rv 0 + assign CFGSUBSYSIDPF2_in[11] = (CFGSUBSYSIDPF2[11] !== 1'bz) && CFGSUBSYSIDPF2[11]; // rv 0 + assign CFGSUBSYSIDPF2_in[12] = (CFGSUBSYSIDPF2[12] !== 1'bz) && CFGSUBSYSIDPF2[12]; // rv 0 + assign CFGSUBSYSIDPF2_in[13] = (CFGSUBSYSIDPF2[13] !== 1'bz) && CFGSUBSYSIDPF2[13]; // rv 0 + assign CFGSUBSYSIDPF2_in[14] = (CFGSUBSYSIDPF2[14] !== 1'bz) && CFGSUBSYSIDPF2[14]; // rv 0 + assign CFGSUBSYSIDPF2_in[15] = (CFGSUBSYSIDPF2[15] !== 1'bz) && CFGSUBSYSIDPF2[15]; // rv 0 + assign CFGSUBSYSIDPF2_in[1] = (CFGSUBSYSIDPF2[1] !== 1'bz) && CFGSUBSYSIDPF2[1]; // rv 0 + assign CFGSUBSYSIDPF2_in[2] = (CFGSUBSYSIDPF2[2] !== 1'bz) && CFGSUBSYSIDPF2[2]; // rv 0 + assign CFGSUBSYSIDPF2_in[3] = (CFGSUBSYSIDPF2[3] !== 1'bz) && CFGSUBSYSIDPF2[3]; // rv 0 + assign CFGSUBSYSIDPF2_in[4] = (CFGSUBSYSIDPF2[4] !== 1'bz) && CFGSUBSYSIDPF2[4]; // rv 0 + assign CFGSUBSYSIDPF2_in[5] = (CFGSUBSYSIDPF2[5] !== 1'bz) && CFGSUBSYSIDPF2[5]; // rv 0 + assign CFGSUBSYSIDPF2_in[6] = (CFGSUBSYSIDPF2[6] !== 1'bz) && CFGSUBSYSIDPF2[6]; // rv 0 + assign CFGSUBSYSIDPF2_in[7] = (CFGSUBSYSIDPF2[7] !== 1'bz) && CFGSUBSYSIDPF2[7]; // rv 0 + assign CFGSUBSYSIDPF2_in[8] = (CFGSUBSYSIDPF2[8] !== 1'bz) && CFGSUBSYSIDPF2[8]; // rv 0 + assign CFGSUBSYSIDPF2_in[9] = (CFGSUBSYSIDPF2[9] !== 1'bz) && CFGSUBSYSIDPF2[9]; // rv 0 + assign CFGSUBSYSIDPF3_in[0] = (CFGSUBSYSIDPF3[0] !== 1'bz) && CFGSUBSYSIDPF3[0]; // rv 0 + assign CFGSUBSYSIDPF3_in[10] = (CFGSUBSYSIDPF3[10] !== 1'bz) && CFGSUBSYSIDPF3[10]; // rv 0 + assign CFGSUBSYSIDPF3_in[11] = (CFGSUBSYSIDPF3[11] !== 1'bz) && CFGSUBSYSIDPF3[11]; // rv 0 + assign CFGSUBSYSIDPF3_in[12] = (CFGSUBSYSIDPF3[12] !== 1'bz) && CFGSUBSYSIDPF3[12]; // rv 0 + assign CFGSUBSYSIDPF3_in[13] = (CFGSUBSYSIDPF3[13] !== 1'bz) && CFGSUBSYSIDPF3[13]; // rv 0 + assign CFGSUBSYSIDPF3_in[14] = (CFGSUBSYSIDPF3[14] !== 1'bz) && CFGSUBSYSIDPF3[14]; // rv 0 + assign CFGSUBSYSIDPF3_in[15] = (CFGSUBSYSIDPF3[15] !== 1'bz) && CFGSUBSYSIDPF3[15]; // rv 0 + assign CFGSUBSYSIDPF3_in[1] = (CFGSUBSYSIDPF3[1] !== 1'bz) && CFGSUBSYSIDPF3[1]; // rv 0 + assign CFGSUBSYSIDPF3_in[2] = (CFGSUBSYSIDPF3[2] !== 1'bz) && CFGSUBSYSIDPF3[2]; // rv 0 + assign CFGSUBSYSIDPF3_in[3] = (CFGSUBSYSIDPF3[3] !== 1'bz) && CFGSUBSYSIDPF3[3]; // rv 0 + assign CFGSUBSYSIDPF3_in[4] = (CFGSUBSYSIDPF3[4] !== 1'bz) && CFGSUBSYSIDPF3[4]; // rv 0 + assign CFGSUBSYSIDPF3_in[5] = (CFGSUBSYSIDPF3[5] !== 1'bz) && CFGSUBSYSIDPF3[5]; // rv 0 + assign CFGSUBSYSIDPF3_in[6] = (CFGSUBSYSIDPF3[6] !== 1'bz) && CFGSUBSYSIDPF3[6]; // rv 0 + assign CFGSUBSYSIDPF3_in[7] = (CFGSUBSYSIDPF3[7] !== 1'bz) && CFGSUBSYSIDPF3[7]; // rv 0 + assign CFGSUBSYSIDPF3_in[8] = (CFGSUBSYSIDPF3[8] !== 1'bz) && CFGSUBSYSIDPF3[8]; // rv 0 + assign CFGSUBSYSIDPF3_in[9] = (CFGSUBSYSIDPF3[9] !== 1'bz) && CFGSUBSYSIDPF3[9]; // rv 0 + assign CFGSUBSYSVENDID_in[0] = (CFGSUBSYSVENDID[0] !== 1'bz) && CFGSUBSYSVENDID[0]; // rv 0 + assign CFGSUBSYSVENDID_in[10] = (CFGSUBSYSVENDID[10] !== 1'bz) && CFGSUBSYSVENDID[10]; // rv 0 + assign CFGSUBSYSVENDID_in[11] = (CFGSUBSYSVENDID[11] !== 1'bz) && CFGSUBSYSVENDID[11]; // rv 0 + assign CFGSUBSYSVENDID_in[12] = (CFGSUBSYSVENDID[12] !== 1'bz) && CFGSUBSYSVENDID[12]; // rv 0 + assign CFGSUBSYSVENDID_in[13] = (CFGSUBSYSVENDID[13] !== 1'bz) && CFGSUBSYSVENDID[13]; // rv 0 + assign CFGSUBSYSVENDID_in[14] = (CFGSUBSYSVENDID[14] !== 1'bz) && CFGSUBSYSVENDID[14]; // rv 0 + assign CFGSUBSYSVENDID_in[15] = (CFGSUBSYSVENDID[15] !== 1'bz) && CFGSUBSYSVENDID[15]; // rv 0 + assign CFGSUBSYSVENDID_in[1] = (CFGSUBSYSVENDID[1] !== 1'bz) && CFGSUBSYSVENDID[1]; // rv 0 + assign CFGSUBSYSVENDID_in[2] = (CFGSUBSYSVENDID[2] !== 1'bz) && CFGSUBSYSVENDID[2]; // rv 0 + assign CFGSUBSYSVENDID_in[3] = (CFGSUBSYSVENDID[3] !== 1'bz) && CFGSUBSYSVENDID[3]; // rv 0 + assign CFGSUBSYSVENDID_in[4] = (CFGSUBSYSVENDID[4] !== 1'bz) && CFGSUBSYSVENDID[4]; // rv 0 + assign CFGSUBSYSVENDID_in[5] = (CFGSUBSYSVENDID[5] !== 1'bz) && CFGSUBSYSVENDID[5]; // rv 0 + assign CFGSUBSYSVENDID_in[6] = (CFGSUBSYSVENDID[6] !== 1'bz) && CFGSUBSYSVENDID[6]; // rv 0 + assign CFGSUBSYSVENDID_in[7] = (CFGSUBSYSVENDID[7] !== 1'bz) && CFGSUBSYSVENDID[7]; // rv 0 + assign CFGSUBSYSVENDID_in[8] = (CFGSUBSYSVENDID[8] !== 1'bz) && CFGSUBSYSVENDID[8]; // rv 0 + assign CFGSUBSYSVENDID_in[9] = (CFGSUBSYSVENDID[9] !== 1'bz) && CFGSUBSYSVENDID[9]; // rv 0 + assign CFGTPHRAMREADDATA_in[0] = (CFGTPHRAMREADDATA[0] !== 1'bz) && CFGTPHRAMREADDATA[0]; // rv 0 + assign CFGTPHRAMREADDATA_in[10] = (CFGTPHRAMREADDATA[10] !== 1'bz) && CFGTPHRAMREADDATA[10]; // rv 0 + assign CFGTPHRAMREADDATA_in[11] = (CFGTPHRAMREADDATA[11] !== 1'bz) && CFGTPHRAMREADDATA[11]; // rv 0 + assign CFGTPHRAMREADDATA_in[12] = (CFGTPHRAMREADDATA[12] !== 1'bz) && CFGTPHRAMREADDATA[12]; // rv 0 + assign CFGTPHRAMREADDATA_in[13] = (CFGTPHRAMREADDATA[13] !== 1'bz) && CFGTPHRAMREADDATA[13]; // rv 0 + assign CFGTPHRAMREADDATA_in[14] = (CFGTPHRAMREADDATA[14] !== 1'bz) && CFGTPHRAMREADDATA[14]; // rv 0 + assign CFGTPHRAMREADDATA_in[15] = (CFGTPHRAMREADDATA[15] !== 1'bz) && CFGTPHRAMREADDATA[15]; // rv 0 + assign CFGTPHRAMREADDATA_in[16] = (CFGTPHRAMREADDATA[16] !== 1'bz) && CFGTPHRAMREADDATA[16]; // rv 0 + assign CFGTPHRAMREADDATA_in[17] = (CFGTPHRAMREADDATA[17] !== 1'bz) && CFGTPHRAMREADDATA[17]; // rv 0 + assign CFGTPHRAMREADDATA_in[18] = (CFGTPHRAMREADDATA[18] !== 1'bz) && CFGTPHRAMREADDATA[18]; // rv 0 + assign CFGTPHRAMREADDATA_in[19] = (CFGTPHRAMREADDATA[19] !== 1'bz) && CFGTPHRAMREADDATA[19]; // rv 0 + assign CFGTPHRAMREADDATA_in[1] = (CFGTPHRAMREADDATA[1] !== 1'bz) && CFGTPHRAMREADDATA[1]; // rv 0 + assign CFGTPHRAMREADDATA_in[20] = (CFGTPHRAMREADDATA[20] !== 1'bz) && CFGTPHRAMREADDATA[20]; // rv 0 + assign CFGTPHRAMREADDATA_in[21] = (CFGTPHRAMREADDATA[21] !== 1'bz) && CFGTPHRAMREADDATA[21]; // rv 0 + assign CFGTPHRAMREADDATA_in[22] = (CFGTPHRAMREADDATA[22] !== 1'bz) && CFGTPHRAMREADDATA[22]; // rv 0 + assign CFGTPHRAMREADDATA_in[23] = (CFGTPHRAMREADDATA[23] !== 1'bz) && CFGTPHRAMREADDATA[23]; // rv 0 + assign CFGTPHRAMREADDATA_in[24] = (CFGTPHRAMREADDATA[24] !== 1'bz) && CFGTPHRAMREADDATA[24]; // rv 0 + assign CFGTPHRAMREADDATA_in[25] = (CFGTPHRAMREADDATA[25] !== 1'bz) && CFGTPHRAMREADDATA[25]; // rv 0 + assign CFGTPHRAMREADDATA_in[26] = (CFGTPHRAMREADDATA[26] !== 1'bz) && CFGTPHRAMREADDATA[26]; // rv 0 + assign CFGTPHRAMREADDATA_in[27] = (CFGTPHRAMREADDATA[27] !== 1'bz) && CFGTPHRAMREADDATA[27]; // rv 0 + assign CFGTPHRAMREADDATA_in[28] = (CFGTPHRAMREADDATA[28] !== 1'bz) && CFGTPHRAMREADDATA[28]; // rv 0 + assign CFGTPHRAMREADDATA_in[29] = (CFGTPHRAMREADDATA[29] !== 1'bz) && CFGTPHRAMREADDATA[29]; // rv 0 + assign CFGTPHRAMREADDATA_in[2] = (CFGTPHRAMREADDATA[2] !== 1'bz) && CFGTPHRAMREADDATA[2]; // rv 0 + assign CFGTPHRAMREADDATA_in[30] = (CFGTPHRAMREADDATA[30] !== 1'bz) && CFGTPHRAMREADDATA[30]; // rv 0 + assign CFGTPHRAMREADDATA_in[31] = (CFGTPHRAMREADDATA[31] !== 1'bz) && CFGTPHRAMREADDATA[31]; // rv 0 + assign CFGTPHRAMREADDATA_in[32] = (CFGTPHRAMREADDATA[32] !== 1'bz) && CFGTPHRAMREADDATA[32]; // rv 0 + assign CFGTPHRAMREADDATA_in[33] = (CFGTPHRAMREADDATA[33] !== 1'bz) && CFGTPHRAMREADDATA[33]; // rv 0 + assign CFGTPHRAMREADDATA_in[34] = (CFGTPHRAMREADDATA[34] !== 1'bz) && CFGTPHRAMREADDATA[34]; // rv 0 + assign CFGTPHRAMREADDATA_in[35] = (CFGTPHRAMREADDATA[35] !== 1'bz) && CFGTPHRAMREADDATA[35]; // rv 0 + assign CFGTPHRAMREADDATA_in[3] = (CFGTPHRAMREADDATA[3] !== 1'bz) && CFGTPHRAMREADDATA[3]; // rv 0 + assign CFGTPHRAMREADDATA_in[4] = (CFGTPHRAMREADDATA[4] !== 1'bz) && CFGTPHRAMREADDATA[4]; // rv 0 + assign CFGTPHRAMREADDATA_in[5] = (CFGTPHRAMREADDATA[5] !== 1'bz) && CFGTPHRAMREADDATA[5]; // rv 0 + assign CFGTPHRAMREADDATA_in[6] = (CFGTPHRAMREADDATA[6] !== 1'bz) && CFGTPHRAMREADDATA[6]; // rv 0 + assign CFGTPHRAMREADDATA_in[7] = (CFGTPHRAMREADDATA[7] !== 1'bz) && CFGTPHRAMREADDATA[7]; // rv 0 + assign CFGTPHRAMREADDATA_in[8] = (CFGTPHRAMREADDATA[8] !== 1'bz) && CFGTPHRAMREADDATA[8]; // rv 0 + assign CFGTPHRAMREADDATA_in[9] = (CFGTPHRAMREADDATA[9] !== 1'bz) && CFGTPHRAMREADDATA[9]; // rv 0 + assign CFGVENDID_in[0] = (CFGVENDID[0] !== 1'bz) && CFGVENDID[0]; // rv 0 + assign CFGVENDID_in[10] = (CFGVENDID[10] !== 1'bz) && CFGVENDID[10]; // rv 0 + assign CFGVENDID_in[11] = (CFGVENDID[11] !== 1'bz) && CFGVENDID[11]; // rv 0 + assign CFGVENDID_in[12] = (CFGVENDID[12] !== 1'bz) && CFGVENDID[12]; // rv 0 + assign CFGVENDID_in[13] = (CFGVENDID[13] !== 1'bz) && CFGVENDID[13]; // rv 0 + assign CFGVENDID_in[14] = (CFGVENDID[14] !== 1'bz) && CFGVENDID[14]; // rv 0 + assign CFGVENDID_in[15] = (CFGVENDID[15] !== 1'bz) && CFGVENDID[15]; // rv 0 + assign CFGVENDID_in[1] = (CFGVENDID[1] !== 1'bz) && CFGVENDID[1]; // rv 0 + assign CFGVENDID_in[2] = (CFGVENDID[2] !== 1'bz) && CFGVENDID[2]; // rv 0 + assign CFGVENDID_in[3] = (CFGVENDID[3] !== 1'bz) && CFGVENDID[3]; // rv 0 + assign CFGVENDID_in[4] = (CFGVENDID[4] !== 1'bz) && CFGVENDID[4]; // rv 0 + assign CFGVENDID_in[5] = (CFGVENDID[5] !== 1'bz) && CFGVENDID[5]; // rv 0 + assign CFGVENDID_in[6] = (CFGVENDID[6] !== 1'bz) && CFGVENDID[6]; // rv 0 + assign CFGVENDID_in[7] = (CFGVENDID[7] !== 1'bz) && CFGVENDID[7]; // rv 0 + assign CFGVENDID_in[8] = (CFGVENDID[8] !== 1'bz) && CFGVENDID[8]; // rv 0 + assign CFGVENDID_in[9] = (CFGVENDID[9] !== 1'bz) && CFGVENDID[9]; // rv 0 + assign CFGVFFLRDONE_in = (CFGVFFLRDONE !== 1'bz) && CFGVFFLRDONE; // rv 0 + assign CFGVFFLRFUNCNUM_in[0] = (CFGVFFLRFUNCNUM[0] !== 1'bz) && CFGVFFLRFUNCNUM[0]; // rv 0 + assign CFGVFFLRFUNCNUM_in[1] = (CFGVFFLRFUNCNUM[1] !== 1'bz) && CFGVFFLRFUNCNUM[1]; // rv 0 + assign CFGVFFLRFUNCNUM_in[2] = (CFGVFFLRFUNCNUM[2] !== 1'bz) && CFGVFFLRFUNCNUM[2]; // rv 0 + assign CFGVFFLRFUNCNUM_in[3] = (CFGVFFLRFUNCNUM[3] !== 1'bz) && CFGVFFLRFUNCNUM[3]; // rv 0 + assign CFGVFFLRFUNCNUM_in[4] = (CFGVFFLRFUNCNUM[4] !== 1'bz) && CFGVFFLRFUNCNUM[4]; // rv 0 + assign CFGVFFLRFUNCNUM_in[5] = (CFGVFFLRFUNCNUM[5] !== 1'bz) && CFGVFFLRFUNCNUM[5]; // rv 0 + assign CFGVFFLRFUNCNUM_in[6] = (CFGVFFLRFUNCNUM[6] !== 1'bz) && CFGVFFLRFUNCNUM[6]; // rv 0 + assign CFGVFFLRFUNCNUM_in[7] = (CFGVFFLRFUNCNUM[7] !== 1'bz) && CFGVFFLRFUNCNUM[7]; // rv 0 + assign CONFMCAPREQUESTBYCONF_in = (CONFMCAPREQUESTBYCONF !== 1'bz) && CONFMCAPREQUESTBYCONF; // rv 0 + assign CONFREQDATA_in[0] = (CONFREQDATA[0] !== 1'bz) && CONFREQDATA[0]; // rv 0 + assign CONFREQDATA_in[10] = (CONFREQDATA[10] !== 1'bz) && CONFREQDATA[10]; // rv 0 + assign CONFREQDATA_in[11] = (CONFREQDATA[11] !== 1'bz) && CONFREQDATA[11]; // rv 0 + assign CONFREQDATA_in[12] = (CONFREQDATA[12] !== 1'bz) && CONFREQDATA[12]; // rv 0 + assign CONFREQDATA_in[13] = (CONFREQDATA[13] !== 1'bz) && CONFREQDATA[13]; // rv 0 + assign CONFREQDATA_in[14] = (CONFREQDATA[14] !== 1'bz) && CONFREQDATA[14]; // rv 0 + assign CONFREQDATA_in[15] = (CONFREQDATA[15] !== 1'bz) && CONFREQDATA[15]; // rv 0 + assign CONFREQDATA_in[16] = (CONFREQDATA[16] !== 1'bz) && CONFREQDATA[16]; // rv 0 + assign CONFREQDATA_in[17] = (CONFREQDATA[17] !== 1'bz) && CONFREQDATA[17]; // rv 0 + assign CONFREQDATA_in[18] = (CONFREQDATA[18] !== 1'bz) && CONFREQDATA[18]; // rv 0 + assign CONFREQDATA_in[19] = (CONFREQDATA[19] !== 1'bz) && CONFREQDATA[19]; // rv 0 + assign CONFREQDATA_in[1] = (CONFREQDATA[1] !== 1'bz) && CONFREQDATA[1]; // rv 0 + assign CONFREQDATA_in[20] = (CONFREQDATA[20] !== 1'bz) && CONFREQDATA[20]; // rv 0 + assign CONFREQDATA_in[21] = (CONFREQDATA[21] !== 1'bz) && CONFREQDATA[21]; // rv 0 + assign CONFREQDATA_in[22] = (CONFREQDATA[22] !== 1'bz) && CONFREQDATA[22]; // rv 0 + assign CONFREQDATA_in[23] = (CONFREQDATA[23] !== 1'bz) && CONFREQDATA[23]; // rv 0 + assign CONFREQDATA_in[24] = (CONFREQDATA[24] !== 1'bz) && CONFREQDATA[24]; // rv 0 + assign CONFREQDATA_in[25] = (CONFREQDATA[25] !== 1'bz) && CONFREQDATA[25]; // rv 0 + assign CONFREQDATA_in[26] = (CONFREQDATA[26] !== 1'bz) && CONFREQDATA[26]; // rv 0 + assign CONFREQDATA_in[27] = (CONFREQDATA[27] !== 1'bz) && CONFREQDATA[27]; // rv 0 + assign CONFREQDATA_in[28] = (CONFREQDATA[28] !== 1'bz) && CONFREQDATA[28]; // rv 0 + assign CONFREQDATA_in[29] = (CONFREQDATA[29] !== 1'bz) && CONFREQDATA[29]; // rv 0 + assign CONFREQDATA_in[2] = (CONFREQDATA[2] !== 1'bz) && CONFREQDATA[2]; // rv 0 + assign CONFREQDATA_in[30] = (CONFREQDATA[30] !== 1'bz) && CONFREQDATA[30]; // rv 0 + assign CONFREQDATA_in[31] = (CONFREQDATA[31] !== 1'bz) && CONFREQDATA[31]; // rv 0 + assign CONFREQDATA_in[3] = (CONFREQDATA[3] !== 1'bz) && CONFREQDATA[3]; // rv 0 + assign CONFREQDATA_in[4] = (CONFREQDATA[4] !== 1'bz) && CONFREQDATA[4]; // rv 0 + assign CONFREQDATA_in[5] = (CONFREQDATA[5] !== 1'bz) && CONFREQDATA[5]; // rv 0 + assign CONFREQDATA_in[6] = (CONFREQDATA[6] !== 1'bz) && CONFREQDATA[6]; // rv 0 + assign CONFREQDATA_in[7] = (CONFREQDATA[7] !== 1'bz) && CONFREQDATA[7]; // rv 0 + assign CONFREQDATA_in[8] = (CONFREQDATA[8] !== 1'bz) && CONFREQDATA[8]; // rv 0 + assign CONFREQDATA_in[9] = (CONFREQDATA[9] !== 1'bz) && CONFREQDATA[9]; // rv 0 + assign CONFREQREGNUM_in[0] = (CONFREQREGNUM[0] !== 1'bz) && CONFREQREGNUM[0]; // rv 0 + assign CONFREQREGNUM_in[1] = (CONFREQREGNUM[1] !== 1'bz) && CONFREQREGNUM[1]; // rv 0 + assign CONFREQREGNUM_in[2] = (CONFREQREGNUM[2] !== 1'bz) && CONFREQREGNUM[2]; // rv 0 + assign CONFREQREGNUM_in[3] = (CONFREQREGNUM[3] !== 1'bz) && CONFREQREGNUM[3]; // rv 0 + assign CONFREQTYPE_in[0] = (CONFREQTYPE[0] !== 1'bz) && CONFREQTYPE[0]; // rv 0 + assign CONFREQTYPE_in[1] = (CONFREQTYPE[1] !== 1'bz) && CONFREQTYPE[1]; // rv 0 + assign CONFREQVALID_in = (CONFREQVALID !== 1'bz) && CONFREQVALID; // rv 0 + assign CORECLK_in = (CORECLK !== 1'bz) && CORECLK; // rv 0 + assign DBGSEL0_in[0] = (DBGSEL0[0] !== 1'bz) && DBGSEL0[0]; // rv 0 + assign DBGSEL0_in[1] = (DBGSEL0[1] !== 1'bz) && DBGSEL0[1]; // rv 0 + assign DBGSEL0_in[2] = (DBGSEL0[2] !== 1'bz) && DBGSEL0[2]; // rv 0 + assign DBGSEL0_in[3] = (DBGSEL0[3] !== 1'bz) && DBGSEL0[3]; // rv 0 + assign DBGSEL0_in[4] = (DBGSEL0[4] !== 1'bz) && DBGSEL0[4]; // rv 0 + assign DBGSEL0_in[5] = (DBGSEL0[5] !== 1'bz) && DBGSEL0[5]; // rv 0 + assign DBGSEL1_in[0] = (DBGSEL1[0] !== 1'bz) && DBGSEL1[0]; // rv 0 + assign DBGSEL1_in[1] = (DBGSEL1[1] !== 1'bz) && DBGSEL1[1]; // rv 0 + assign DBGSEL1_in[2] = (DBGSEL1[2] !== 1'bz) && DBGSEL1[2]; // rv 0 + assign DBGSEL1_in[3] = (DBGSEL1[3] !== 1'bz) && DBGSEL1[3]; // rv 0 + assign DBGSEL1_in[4] = (DBGSEL1[4] !== 1'bz) && DBGSEL1[4]; // rv 0 + assign DBGSEL1_in[5] = (DBGSEL1[5] !== 1'bz) && DBGSEL1[5]; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0 + assign MAXISCQTREADY_in[0] = (MAXISCQTREADY[0] !== 1'bz) && MAXISCQTREADY[0]; // rv 0 + assign MAXISCQTREADY_in[10] = (MAXISCQTREADY[10] !== 1'bz) && MAXISCQTREADY[10]; // rv 0 + assign MAXISCQTREADY_in[11] = (MAXISCQTREADY[11] !== 1'bz) && MAXISCQTREADY[11]; // rv 0 + assign MAXISCQTREADY_in[12] = (MAXISCQTREADY[12] !== 1'bz) && MAXISCQTREADY[12]; // rv 0 + assign MAXISCQTREADY_in[13] = (MAXISCQTREADY[13] !== 1'bz) && MAXISCQTREADY[13]; // rv 0 + assign MAXISCQTREADY_in[14] = (MAXISCQTREADY[14] !== 1'bz) && MAXISCQTREADY[14]; // rv 0 + assign MAXISCQTREADY_in[15] = (MAXISCQTREADY[15] !== 1'bz) && MAXISCQTREADY[15]; // rv 0 + assign MAXISCQTREADY_in[16] = (MAXISCQTREADY[16] !== 1'bz) && MAXISCQTREADY[16]; // rv 0 + assign MAXISCQTREADY_in[17] = (MAXISCQTREADY[17] !== 1'bz) && MAXISCQTREADY[17]; // rv 0 + assign MAXISCQTREADY_in[18] = (MAXISCQTREADY[18] !== 1'bz) && MAXISCQTREADY[18]; // rv 0 + assign MAXISCQTREADY_in[19] = (MAXISCQTREADY[19] !== 1'bz) && MAXISCQTREADY[19]; // rv 0 + assign MAXISCQTREADY_in[1] = (MAXISCQTREADY[1] !== 1'bz) && MAXISCQTREADY[1]; // rv 0 + assign MAXISCQTREADY_in[20] = (MAXISCQTREADY[20] !== 1'bz) && MAXISCQTREADY[20]; // rv 0 + assign MAXISCQTREADY_in[21] = (MAXISCQTREADY[21] !== 1'bz) && MAXISCQTREADY[21]; // rv 0 + assign MAXISCQTREADY_in[2] = (MAXISCQTREADY[2] !== 1'bz) && MAXISCQTREADY[2]; // rv 0 + assign MAXISCQTREADY_in[3] = (MAXISCQTREADY[3] !== 1'bz) && MAXISCQTREADY[3]; // rv 0 + assign MAXISCQTREADY_in[4] = (MAXISCQTREADY[4] !== 1'bz) && MAXISCQTREADY[4]; // rv 0 + assign MAXISCQTREADY_in[5] = (MAXISCQTREADY[5] !== 1'bz) && MAXISCQTREADY[5]; // rv 0 + assign MAXISCQTREADY_in[6] = (MAXISCQTREADY[6] !== 1'bz) && MAXISCQTREADY[6]; // rv 0 + assign MAXISCQTREADY_in[7] = (MAXISCQTREADY[7] !== 1'bz) && MAXISCQTREADY[7]; // rv 0 + assign MAXISCQTREADY_in[8] = (MAXISCQTREADY[8] !== 1'bz) && MAXISCQTREADY[8]; // rv 0 + assign MAXISCQTREADY_in[9] = (MAXISCQTREADY[9] !== 1'bz) && MAXISCQTREADY[9]; // rv 0 + assign MAXISRCTREADY_in[0] = (MAXISRCTREADY[0] !== 1'bz) && MAXISRCTREADY[0]; // rv 0 + assign MAXISRCTREADY_in[10] = (MAXISRCTREADY[10] !== 1'bz) && MAXISRCTREADY[10]; // rv 0 + assign MAXISRCTREADY_in[11] = (MAXISRCTREADY[11] !== 1'bz) && MAXISRCTREADY[11]; // rv 0 + assign MAXISRCTREADY_in[12] = (MAXISRCTREADY[12] !== 1'bz) && MAXISRCTREADY[12]; // rv 0 + assign MAXISRCTREADY_in[13] = (MAXISRCTREADY[13] !== 1'bz) && MAXISRCTREADY[13]; // rv 0 + assign MAXISRCTREADY_in[14] = (MAXISRCTREADY[14] !== 1'bz) && MAXISRCTREADY[14]; // rv 0 + assign MAXISRCTREADY_in[15] = (MAXISRCTREADY[15] !== 1'bz) && MAXISRCTREADY[15]; // rv 0 + assign MAXISRCTREADY_in[16] = (MAXISRCTREADY[16] !== 1'bz) && MAXISRCTREADY[16]; // rv 0 + assign MAXISRCTREADY_in[17] = (MAXISRCTREADY[17] !== 1'bz) && MAXISRCTREADY[17]; // rv 0 + assign MAXISRCTREADY_in[18] = (MAXISRCTREADY[18] !== 1'bz) && MAXISRCTREADY[18]; // rv 0 + assign MAXISRCTREADY_in[19] = (MAXISRCTREADY[19] !== 1'bz) && MAXISRCTREADY[19]; // rv 0 + assign MAXISRCTREADY_in[1] = (MAXISRCTREADY[1] !== 1'bz) && MAXISRCTREADY[1]; // rv 0 + assign MAXISRCTREADY_in[20] = (MAXISRCTREADY[20] !== 1'bz) && MAXISRCTREADY[20]; // rv 0 + assign MAXISRCTREADY_in[21] = (MAXISRCTREADY[21] !== 1'bz) && MAXISRCTREADY[21]; // rv 0 + assign MAXISRCTREADY_in[2] = (MAXISRCTREADY[2] !== 1'bz) && MAXISRCTREADY[2]; // rv 0 + assign MAXISRCTREADY_in[3] = (MAXISRCTREADY[3] !== 1'bz) && MAXISRCTREADY[3]; // rv 0 + assign MAXISRCTREADY_in[4] = (MAXISRCTREADY[4] !== 1'bz) && MAXISRCTREADY[4]; // rv 0 + assign MAXISRCTREADY_in[5] = (MAXISRCTREADY[5] !== 1'bz) && MAXISRCTREADY[5]; // rv 0 + assign MAXISRCTREADY_in[6] = (MAXISRCTREADY[6] !== 1'bz) && MAXISRCTREADY[6]; // rv 0 + assign MAXISRCTREADY_in[7] = (MAXISRCTREADY[7] !== 1'bz) && MAXISRCTREADY[7]; // rv 0 + assign MAXISRCTREADY_in[8] = (MAXISRCTREADY[8] !== 1'bz) && MAXISRCTREADY[8]; // rv 0 + assign MAXISRCTREADY_in[9] = (MAXISRCTREADY[9] !== 1'bz) && MAXISRCTREADY[9]; // rv 0 + assign MIREPLAYRAMERRCOR_in[0] = (MIREPLAYRAMERRCOR[0] !== 1'bz) && MIREPLAYRAMERRCOR[0]; // rv 0 + assign MIREPLAYRAMERRCOR_in[1] = (MIREPLAYRAMERRCOR[1] !== 1'bz) && MIREPLAYRAMERRCOR[1]; // rv 0 + assign MIREPLAYRAMERRCOR_in[2] = (MIREPLAYRAMERRCOR[2] !== 1'bz) && MIREPLAYRAMERRCOR[2]; // rv 0 + assign MIREPLAYRAMERRCOR_in[3] = (MIREPLAYRAMERRCOR[3] !== 1'bz) && MIREPLAYRAMERRCOR[3]; // rv 0 + assign MIREPLAYRAMERRCOR_in[4] = (MIREPLAYRAMERRCOR[4] !== 1'bz) && MIREPLAYRAMERRCOR[4]; // rv 0 + assign MIREPLAYRAMERRCOR_in[5] = (MIREPLAYRAMERRCOR[5] !== 1'bz) && MIREPLAYRAMERRCOR[5]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[0] = (MIREPLAYRAMERRUNCOR[0] !== 1'bz) && MIREPLAYRAMERRUNCOR[0]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[1] = (MIREPLAYRAMERRUNCOR[1] !== 1'bz) && MIREPLAYRAMERRUNCOR[1]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[2] = (MIREPLAYRAMERRUNCOR[2] !== 1'bz) && MIREPLAYRAMERRUNCOR[2]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[3] = (MIREPLAYRAMERRUNCOR[3] !== 1'bz) && MIREPLAYRAMERRUNCOR[3]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[4] = (MIREPLAYRAMERRUNCOR[4] !== 1'bz) && MIREPLAYRAMERRUNCOR[4]; // rv 0 + assign MIREPLAYRAMERRUNCOR_in[5] = (MIREPLAYRAMERRUNCOR[5] !== 1'bz) && MIREPLAYRAMERRUNCOR[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[0] = (MIREPLAYRAMREADDATA0[0] !== 1'bz) && MIREPLAYRAMREADDATA0[0]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[100] = (MIREPLAYRAMREADDATA0[100] !== 1'bz) && MIREPLAYRAMREADDATA0[100]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[101] = (MIREPLAYRAMREADDATA0[101] !== 1'bz) && MIREPLAYRAMREADDATA0[101]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[102] = (MIREPLAYRAMREADDATA0[102] !== 1'bz) && MIREPLAYRAMREADDATA0[102]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[103] = (MIREPLAYRAMREADDATA0[103] !== 1'bz) && MIREPLAYRAMREADDATA0[103]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[104] = (MIREPLAYRAMREADDATA0[104] !== 1'bz) && MIREPLAYRAMREADDATA0[104]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[105] = (MIREPLAYRAMREADDATA0[105] !== 1'bz) && MIREPLAYRAMREADDATA0[105]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[106] = (MIREPLAYRAMREADDATA0[106] !== 1'bz) && MIREPLAYRAMREADDATA0[106]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[107] = (MIREPLAYRAMREADDATA0[107] !== 1'bz) && MIREPLAYRAMREADDATA0[107]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[108] = (MIREPLAYRAMREADDATA0[108] !== 1'bz) && MIREPLAYRAMREADDATA0[108]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[109] = (MIREPLAYRAMREADDATA0[109] !== 1'bz) && MIREPLAYRAMREADDATA0[109]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[10] = (MIREPLAYRAMREADDATA0[10] !== 1'bz) && MIREPLAYRAMREADDATA0[10]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[110] = (MIREPLAYRAMREADDATA0[110] !== 1'bz) && MIREPLAYRAMREADDATA0[110]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[111] = (MIREPLAYRAMREADDATA0[111] !== 1'bz) && MIREPLAYRAMREADDATA0[111]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[112] = (MIREPLAYRAMREADDATA0[112] !== 1'bz) && MIREPLAYRAMREADDATA0[112]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[113] = (MIREPLAYRAMREADDATA0[113] !== 1'bz) && MIREPLAYRAMREADDATA0[113]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[114] = (MIREPLAYRAMREADDATA0[114] !== 1'bz) && MIREPLAYRAMREADDATA0[114]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[115] = (MIREPLAYRAMREADDATA0[115] !== 1'bz) && MIREPLAYRAMREADDATA0[115]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[116] = (MIREPLAYRAMREADDATA0[116] !== 1'bz) && MIREPLAYRAMREADDATA0[116]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[117] = (MIREPLAYRAMREADDATA0[117] !== 1'bz) && MIREPLAYRAMREADDATA0[117]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[118] = (MIREPLAYRAMREADDATA0[118] !== 1'bz) && MIREPLAYRAMREADDATA0[118]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[119] = (MIREPLAYRAMREADDATA0[119] !== 1'bz) && MIREPLAYRAMREADDATA0[119]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[11] = (MIREPLAYRAMREADDATA0[11] !== 1'bz) && MIREPLAYRAMREADDATA0[11]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[120] = (MIREPLAYRAMREADDATA0[120] !== 1'bz) && MIREPLAYRAMREADDATA0[120]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[121] = (MIREPLAYRAMREADDATA0[121] !== 1'bz) && MIREPLAYRAMREADDATA0[121]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[122] = (MIREPLAYRAMREADDATA0[122] !== 1'bz) && MIREPLAYRAMREADDATA0[122]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[123] = (MIREPLAYRAMREADDATA0[123] !== 1'bz) && MIREPLAYRAMREADDATA0[123]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[124] = (MIREPLAYRAMREADDATA0[124] !== 1'bz) && MIREPLAYRAMREADDATA0[124]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[125] = (MIREPLAYRAMREADDATA0[125] !== 1'bz) && MIREPLAYRAMREADDATA0[125]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[126] = (MIREPLAYRAMREADDATA0[126] !== 1'bz) && MIREPLAYRAMREADDATA0[126]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[127] = (MIREPLAYRAMREADDATA0[127] !== 1'bz) && MIREPLAYRAMREADDATA0[127]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[12] = (MIREPLAYRAMREADDATA0[12] !== 1'bz) && MIREPLAYRAMREADDATA0[12]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[13] = (MIREPLAYRAMREADDATA0[13] !== 1'bz) && MIREPLAYRAMREADDATA0[13]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[14] = (MIREPLAYRAMREADDATA0[14] !== 1'bz) && MIREPLAYRAMREADDATA0[14]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[15] = (MIREPLAYRAMREADDATA0[15] !== 1'bz) && MIREPLAYRAMREADDATA0[15]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[16] = (MIREPLAYRAMREADDATA0[16] !== 1'bz) && MIREPLAYRAMREADDATA0[16]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[17] = (MIREPLAYRAMREADDATA0[17] !== 1'bz) && MIREPLAYRAMREADDATA0[17]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[18] = (MIREPLAYRAMREADDATA0[18] !== 1'bz) && MIREPLAYRAMREADDATA0[18]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[19] = (MIREPLAYRAMREADDATA0[19] !== 1'bz) && MIREPLAYRAMREADDATA0[19]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[1] = (MIREPLAYRAMREADDATA0[1] !== 1'bz) && MIREPLAYRAMREADDATA0[1]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[20] = (MIREPLAYRAMREADDATA0[20] !== 1'bz) && MIREPLAYRAMREADDATA0[20]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[21] = (MIREPLAYRAMREADDATA0[21] !== 1'bz) && MIREPLAYRAMREADDATA0[21]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[22] = (MIREPLAYRAMREADDATA0[22] !== 1'bz) && MIREPLAYRAMREADDATA0[22]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[23] = (MIREPLAYRAMREADDATA0[23] !== 1'bz) && MIREPLAYRAMREADDATA0[23]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[24] = (MIREPLAYRAMREADDATA0[24] !== 1'bz) && MIREPLAYRAMREADDATA0[24]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[25] = (MIREPLAYRAMREADDATA0[25] !== 1'bz) && MIREPLAYRAMREADDATA0[25]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[26] = (MIREPLAYRAMREADDATA0[26] !== 1'bz) && MIREPLAYRAMREADDATA0[26]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[27] = (MIREPLAYRAMREADDATA0[27] !== 1'bz) && MIREPLAYRAMREADDATA0[27]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[28] = (MIREPLAYRAMREADDATA0[28] !== 1'bz) && MIREPLAYRAMREADDATA0[28]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[29] = (MIREPLAYRAMREADDATA0[29] !== 1'bz) && MIREPLAYRAMREADDATA0[29]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[2] = (MIREPLAYRAMREADDATA0[2] !== 1'bz) && MIREPLAYRAMREADDATA0[2]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[30] = (MIREPLAYRAMREADDATA0[30] !== 1'bz) && MIREPLAYRAMREADDATA0[30]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[31] = (MIREPLAYRAMREADDATA0[31] !== 1'bz) && MIREPLAYRAMREADDATA0[31]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[32] = (MIREPLAYRAMREADDATA0[32] !== 1'bz) && MIREPLAYRAMREADDATA0[32]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[33] = (MIREPLAYRAMREADDATA0[33] !== 1'bz) && MIREPLAYRAMREADDATA0[33]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[34] = (MIREPLAYRAMREADDATA0[34] !== 1'bz) && MIREPLAYRAMREADDATA0[34]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[35] = (MIREPLAYRAMREADDATA0[35] !== 1'bz) && MIREPLAYRAMREADDATA0[35]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[36] = (MIREPLAYRAMREADDATA0[36] !== 1'bz) && MIREPLAYRAMREADDATA0[36]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[37] = (MIREPLAYRAMREADDATA0[37] !== 1'bz) && MIREPLAYRAMREADDATA0[37]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[38] = (MIREPLAYRAMREADDATA0[38] !== 1'bz) && MIREPLAYRAMREADDATA0[38]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[39] = (MIREPLAYRAMREADDATA0[39] !== 1'bz) && MIREPLAYRAMREADDATA0[39]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[3] = (MIREPLAYRAMREADDATA0[3] !== 1'bz) && MIREPLAYRAMREADDATA0[3]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[40] = (MIREPLAYRAMREADDATA0[40] !== 1'bz) && MIREPLAYRAMREADDATA0[40]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[41] = (MIREPLAYRAMREADDATA0[41] !== 1'bz) && MIREPLAYRAMREADDATA0[41]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[42] = (MIREPLAYRAMREADDATA0[42] !== 1'bz) && MIREPLAYRAMREADDATA0[42]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[43] = (MIREPLAYRAMREADDATA0[43] !== 1'bz) && MIREPLAYRAMREADDATA0[43]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[44] = (MIREPLAYRAMREADDATA0[44] !== 1'bz) && MIREPLAYRAMREADDATA0[44]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[45] = (MIREPLAYRAMREADDATA0[45] !== 1'bz) && MIREPLAYRAMREADDATA0[45]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[46] = (MIREPLAYRAMREADDATA0[46] !== 1'bz) && MIREPLAYRAMREADDATA0[46]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[47] = (MIREPLAYRAMREADDATA0[47] !== 1'bz) && MIREPLAYRAMREADDATA0[47]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[48] = (MIREPLAYRAMREADDATA0[48] !== 1'bz) && MIREPLAYRAMREADDATA0[48]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[49] = (MIREPLAYRAMREADDATA0[49] !== 1'bz) && MIREPLAYRAMREADDATA0[49]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[4] = (MIREPLAYRAMREADDATA0[4] !== 1'bz) && MIREPLAYRAMREADDATA0[4]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[50] = (MIREPLAYRAMREADDATA0[50] !== 1'bz) && MIREPLAYRAMREADDATA0[50]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[51] = (MIREPLAYRAMREADDATA0[51] !== 1'bz) && MIREPLAYRAMREADDATA0[51]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[52] = (MIREPLAYRAMREADDATA0[52] !== 1'bz) && MIREPLAYRAMREADDATA0[52]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[53] = (MIREPLAYRAMREADDATA0[53] !== 1'bz) && MIREPLAYRAMREADDATA0[53]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[54] = (MIREPLAYRAMREADDATA0[54] !== 1'bz) && MIREPLAYRAMREADDATA0[54]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[55] = (MIREPLAYRAMREADDATA0[55] !== 1'bz) && MIREPLAYRAMREADDATA0[55]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[56] = (MIREPLAYRAMREADDATA0[56] !== 1'bz) && MIREPLAYRAMREADDATA0[56]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[57] = (MIREPLAYRAMREADDATA0[57] !== 1'bz) && MIREPLAYRAMREADDATA0[57]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[58] = (MIREPLAYRAMREADDATA0[58] !== 1'bz) && MIREPLAYRAMREADDATA0[58]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[59] = (MIREPLAYRAMREADDATA0[59] !== 1'bz) && MIREPLAYRAMREADDATA0[59]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[5] = (MIREPLAYRAMREADDATA0[5] !== 1'bz) && MIREPLAYRAMREADDATA0[5]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[60] = (MIREPLAYRAMREADDATA0[60] !== 1'bz) && MIREPLAYRAMREADDATA0[60]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[61] = (MIREPLAYRAMREADDATA0[61] !== 1'bz) && MIREPLAYRAMREADDATA0[61]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[62] = (MIREPLAYRAMREADDATA0[62] !== 1'bz) && MIREPLAYRAMREADDATA0[62]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[63] = (MIREPLAYRAMREADDATA0[63] !== 1'bz) && MIREPLAYRAMREADDATA0[63]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[64] = (MIREPLAYRAMREADDATA0[64] !== 1'bz) && MIREPLAYRAMREADDATA0[64]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[65] = (MIREPLAYRAMREADDATA0[65] !== 1'bz) && MIREPLAYRAMREADDATA0[65]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[66] = (MIREPLAYRAMREADDATA0[66] !== 1'bz) && MIREPLAYRAMREADDATA0[66]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[67] = (MIREPLAYRAMREADDATA0[67] !== 1'bz) && MIREPLAYRAMREADDATA0[67]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[68] = (MIREPLAYRAMREADDATA0[68] !== 1'bz) && MIREPLAYRAMREADDATA0[68]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[69] = (MIREPLAYRAMREADDATA0[69] !== 1'bz) && MIREPLAYRAMREADDATA0[69]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[6] = (MIREPLAYRAMREADDATA0[6] !== 1'bz) && MIREPLAYRAMREADDATA0[6]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[70] = (MIREPLAYRAMREADDATA0[70] !== 1'bz) && MIREPLAYRAMREADDATA0[70]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[71] = (MIREPLAYRAMREADDATA0[71] !== 1'bz) && MIREPLAYRAMREADDATA0[71]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[72] = (MIREPLAYRAMREADDATA0[72] !== 1'bz) && MIREPLAYRAMREADDATA0[72]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[73] = (MIREPLAYRAMREADDATA0[73] !== 1'bz) && MIREPLAYRAMREADDATA0[73]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[74] = (MIREPLAYRAMREADDATA0[74] !== 1'bz) && MIREPLAYRAMREADDATA0[74]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[75] = (MIREPLAYRAMREADDATA0[75] !== 1'bz) && MIREPLAYRAMREADDATA0[75]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[76] = (MIREPLAYRAMREADDATA0[76] !== 1'bz) && MIREPLAYRAMREADDATA0[76]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[77] = (MIREPLAYRAMREADDATA0[77] !== 1'bz) && MIREPLAYRAMREADDATA0[77]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[78] = (MIREPLAYRAMREADDATA0[78] !== 1'bz) && MIREPLAYRAMREADDATA0[78]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[79] = (MIREPLAYRAMREADDATA0[79] !== 1'bz) && MIREPLAYRAMREADDATA0[79]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[7] = (MIREPLAYRAMREADDATA0[7] !== 1'bz) && MIREPLAYRAMREADDATA0[7]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[80] = (MIREPLAYRAMREADDATA0[80] !== 1'bz) && MIREPLAYRAMREADDATA0[80]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[81] = (MIREPLAYRAMREADDATA0[81] !== 1'bz) && MIREPLAYRAMREADDATA0[81]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[82] = (MIREPLAYRAMREADDATA0[82] !== 1'bz) && MIREPLAYRAMREADDATA0[82]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[83] = (MIREPLAYRAMREADDATA0[83] !== 1'bz) && MIREPLAYRAMREADDATA0[83]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[84] = (MIREPLAYRAMREADDATA0[84] !== 1'bz) && MIREPLAYRAMREADDATA0[84]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[85] = (MIREPLAYRAMREADDATA0[85] !== 1'bz) && MIREPLAYRAMREADDATA0[85]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[86] = (MIREPLAYRAMREADDATA0[86] !== 1'bz) && MIREPLAYRAMREADDATA0[86]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[87] = (MIREPLAYRAMREADDATA0[87] !== 1'bz) && MIREPLAYRAMREADDATA0[87]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[88] = (MIREPLAYRAMREADDATA0[88] !== 1'bz) && MIREPLAYRAMREADDATA0[88]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[89] = (MIREPLAYRAMREADDATA0[89] !== 1'bz) && MIREPLAYRAMREADDATA0[89]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[8] = (MIREPLAYRAMREADDATA0[8] !== 1'bz) && MIREPLAYRAMREADDATA0[8]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[90] = (MIREPLAYRAMREADDATA0[90] !== 1'bz) && MIREPLAYRAMREADDATA0[90]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[91] = (MIREPLAYRAMREADDATA0[91] !== 1'bz) && MIREPLAYRAMREADDATA0[91]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[92] = (MIREPLAYRAMREADDATA0[92] !== 1'bz) && MIREPLAYRAMREADDATA0[92]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[93] = (MIREPLAYRAMREADDATA0[93] !== 1'bz) && MIREPLAYRAMREADDATA0[93]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[94] = (MIREPLAYRAMREADDATA0[94] !== 1'bz) && MIREPLAYRAMREADDATA0[94]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[95] = (MIREPLAYRAMREADDATA0[95] !== 1'bz) && MIREPLAYRAMREADDATA0[95]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[96] = (MIREPLAYRAMREADDATA0[96] !== 1'bz) && MIREPLAYRAMREADDATA0[96]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[97] = (MIREPLAYRAMREADDATA0[97] !== 1'bz) && MIREPLAYRAMREADDATA0[97]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[98] = (MIREPLAYRAMREADDATA0[98] !== 1'bz) && MIREPLAYRAMREADDATA0[98]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[99] = (MIREPLAYRAMREADDATA0[99] !== 1'bz) && MIREPLAYRAMREADDATA0[99]; // rv 0 + assign MIREPLAYRAMREADDATA0_in[9] = (MIREPLAYRAMREADDATA0[9] !== 1'bz) && MIREPLAYRAMREADDATA0[9]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[0] = (MIREPLAYRAMREADDATA1[0] !== 1'bz) && MIREPLAYRAMREADDATA1[0]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[100] = (MIREPLAYRAMREADDATA1[100] !== 1'bz) && MIREPLAYRAMREADDATA1[100]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[101] = (MIREPLAYRAMREADDATA1[101] !== 1'bz) && MIREPLAYRAMREADDATA1[101]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[102] = (MIREPLAYRAMREADDATA1[102] !== 1'bz) && MIREPLAYRAMREADDATA1[102]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[103] = (MIREPLAYRAMREADDATA1[103] !== 1'bz) && MIREPLAYRAMREADDATA1[103]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[104] = (MIREPLAYRAMREADDATA1[104] !== 1'bz) && MIREPLAYRAMREADDATA1[104]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[105] = (MIREPLAYRAMREADDATA1[105] !== 1'bz) && MIREPLAYRAMREADDATA1[105]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[106] = (MIREPLAYRAMREADDATA1[106] !== 1'bz) && MIREPLAYRAMREADDATA1[106]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[107] = (MIREPLAYRAMREADDATA1[107] !== 1'bz) && MIREPLAYRAMREADDATA1[107]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[108] = (MIREPLAYRAMREADDATA1[108] !== 1'bz) && MIREPLAYRAMREADDATA1[108]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[109] = (MIREPLAYRAMREADDATA1[109] !== 1'bz) && MIREPLAYRAMREADDATA1[109]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[10] = (MIREPLAYRAMREADDATA1[10] !== 1'bz) && MIREPLAYRAMREADDATA1[10]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[110] = (MIREPLAYRAMREADDATA1[110] !== 1'bz) && MIREPLAYRAMREADDATA1[110]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[111] = (MIREPLAYRAMREADDATA1[111] !== 1'bz) && MIREPLAYRAMREADDATA1[111]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[112] = (MIREPLAYRAMREADDATA1[112] !== 1'bz) && MIREPLAYRAMREADDATA1[112]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[113] = (MIREPLAYRAMREADDATA1[113] !== 1'bz) && MIREPLAYRAMREADDATA1[113]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[114] = (MIREPLAYRAMREADDATA1[114] !== 1'bz) && MIREPLAYRAMREADDATA1[114]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[115] = (MIREPLAYRAMREADDATA1[115] !== 1'bz) && MIREPLAYRAMREADDATA1[115]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[116] = (MIREPLAYRAMREADDATA1[116] !== 1'bz) && MIREPLAYRAMREADDATA1[116]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[117] = (MIREPLAYRAMREADDATA1[117] !== 1'bz) && MIREPLAYRAMREADDATA1[117]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[118] = (MIREPLAYRAMREADDATA1[118] !== 1'bz) && MIREPLAYRAMREADDATA1[118]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[119] = (MIREPLAYRAMREADDATA1[119] !== 1'bz) && MIREPLAYRAMREADDATA1[119]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[11] = (MIREPLAYRAMREADDATA1[11] !== 1'bz) && MIREPLAYRAMREADDATA1[11]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[120] = (MIREPLAYRAMREADDATA1[120] !== 1'bz) && MIREPLAYRAMREADDATA1[120]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[121] = (MIREPLAYRAMREADDATA1[121] !== 1'bz) && MIREPLAYRAMREADDATA1[121]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[122] = (MIREPLAYRAMREADDATA1[122] !== 1'bz) && MIREPLAYRAMREADDATA1[122]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[123] = (MIREPLAYRAMREADDATA1[123] !== 1'bz) && MIREPLAYRAMREADDATA1[123]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[124] = (MIREPLAYRAMREADDATA1[124] !== 1'bz) && MIREPLAYRAMREADDATA1[124]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[125] = (MIREPLAYRAMREADDATA1[125] !== 1'bz) && MIREPLAYRAMREADDATA1[125]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[126] = (MIREPLAYRAMREADDATA1[126] !== 1'bz) && MIREPLAYRAMREADDATA1[126]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[127] = (MIREPLAYRAMREADDATA1[127] !== 1'bz) && MIREPLAYRAMREADDATA1[127]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[12] = (MIREPLAYRAMREADDATA1[12] !== 1'bz) && MIREPLAYRAMREADDATA1[12]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[13] = (MIREPLAYRAMREADDATA1[13] !== 1'bz) && MIREPLAYRAMREADDATA1[13]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[14] = (MIREPLAYRAMREADDATA1[14] !== 1'bz) && MIREPLAYRAMREADDATA1[14]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[15] = (MIREPLAYRAMREADDATA1[15] !== 1'bz) && MIREPLAYRAMREADDATA1[15]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[16] = (MIREPLAYRAMREADDATA1[16] !== 1'bz) && MIREPLAYRAMREADDATA1[16]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[17] = (MIREPLAYRAMREADDATA1[17] !== 1'bz) && MIREPLAYRAMREADDATA1[17]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[18] = (MIREPLAYRAMREADDATA1[18] !== 1'bz) && MIREPLAYRAMREADDATA1[18]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[19] = (MIREPLAYRAMREADDATA1[19] !== 1'bz) && MIREPLAYRAMREADDATA1[19]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[1] = (MIREPLAYRAMREADDATA1[1] !== 1'bz) && MIREPLAYRAMREADDATA1[1]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[20] = (MIREPLAYRAMREADDATA1[20] !== 1'bz) && MIREPLAYRAMREADDATA1[20]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[21] = (MIREPLAYRAMREADDATA1[21] !== 1'bz) && MIREPLAYRAMREADDATA1[21]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[22] = (MIREPLAYRAMREADDATA1[22] !== 1'bz) && MIREPLAYRAMREADDATA1[22]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[23] = (MIREPLAYRAMREADDATA1[23] !== 1'bz) && MIREPLAYRAMREADDATA1[23]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[24] = (MIREPLAYRAMREADDATA1[24] !== 1'bz) && MIREPLAYRAMREADDATA1[24]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[25] = (MIREPLAYRAMREADDATA1[25] !== 1'bz) && MIREPLAYRAMREADDATA1[25]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[26] = (MIREPLAYRAMREADDATA1[26] !== 1'bz) && MIREPLAYRAMREADDATA1[26]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[27] = (MIREPLAYRAMREADDATA1[27] !== 1'bz) && MIREPLAYRAMREADDATA1[27]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[28] = (MIREPLAYRAMREADDATA1[28] !== 1'bz) && MIREPLAYRAMREADDATA1[28]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[29] = (MIREPLAYRAMREADDATA1[29] !== 1'bz) && MIREPLAYRAMREADDATA1[29]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[2] = (MIREPLAYRAMREADDATA1[2] !== 1'bz) && MIREPLAYRAMREADDATA1[2]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[30] = (MIREPLAYRAMREADDATA1[30] !== 1'bz) && MIREPLAYRAMREADDATA1[30]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[31] = (MIREPLAYRAMREADDATA1[31] !== 1'bz) && MIREPLAYRAMREADDATA1[31]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[32] = (MIREPLAYRAMREADDATA1[32] !== 1'bz) && MIREPLAYRAMREADDATA1[32]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[33] = (MIREPLAYRAMREADDATA1[33] !== 1'bz) && MIREPLAYRAMREADDATA1[33]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[34] = (MIREPLAYRAMREADDATA1[34] !== 1'bz) && MIREPLAYRAMREADDATA1[34]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[35] = (MIREPLAYRAMREADDATA1[35] !== 1'bz) && MIREPLAYRAMREADDATA1[35]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[36] = (MIREPLAYRAMREADDATA1[36] !== 1'bz) && MIREPLAYRAMREADDATA1[36]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[37] = (MIREPLAYRAMREADDATA1[37] !== 1'bz) && MIREPLAYRAMREADDATA1[37]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[38] = (MIREPLAYRAMREADDATA1[38] !== 1'bz) && MIREPLAYRAMREADDATA1[38]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[39] = (MIREPLAYRAMREADDATA1[39] !== 1'bz) && MIREPLAYRAMREADDATA1[39]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[3] = (MIREPLAYRAMREADDATA1[3] !== 1'bz) && MIREPLAYRAMREADDATA1[3]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[40] = (MIREPLAYRAMREADDATA1[40] !== 1'bz) && MIREPLAYRAMREADDATA1[40]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[41] = (MIREPLAYRAMREADDATA1[41] !== 1'bz) && MIREPLAYRAMREADDATA1[41]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[42] = (MIREPLAYRAMREADDATA1[42] !== 1'bz) && MIREPLAYRAMREADDATA1[42]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[43] = (MIREPLAYRAMREADDATA1[43] !== 1'bz) && MIREPLAYRAMREADDATA1[43]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[44] = (MIREPLAYRAMREADDATA1[44] !== 1'bz) && MIREPLAYRAMREADDATA1[44]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[45] = (MIREPLAYRAMREADDATA1[45] !== 1'bz) && MIREPLAYRAMREADDATA1[45]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[46] = (MIREPLAYRAMREADDATA1[46] !== 1'bz) && MIREPLAYRAMREADDATA1[46]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[47] = (MIREPLAYRAMREADDATA1[47] !== 1'bz) && MIREPLAYRAMREADDATA1[47]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[48] = (MIREPLAYRAMREADDATA1[48] !== 1'bz) && MIREPLAYRAMREADDATA1[48]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[49] = (MIREPLAYRAMREADDATA1[49] !== 1'bz) && MIREPLAYRAMREADDATA1[49]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[4] = (MIREPLAYRAMREADDATA1[4] !== 1'bz) && MIREPLAYRAMREADDATA1[4]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[50] = (MIREPLAYRAMREADDATA1[50] !== 1'bz) && MIREPLAYRAMREADDATA1[50]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[51] = (MIREPLAYRAMREADDATA1[51] !== 1'bz) && MIREPLAYRAMREADDATA1[51]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[52] = (MIREPLAYRAMREADDATA1[52] !== 1'bz) && MIREPLAYRAMREADDATA1[52]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[53] = (MIREPLAYRAMREADDATA1[53] !== 1'bz) && MIREPLAYRAMREADDATA1[53]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[54] = (MIREPLAYRAMREADDATA1[54] !== 1'bz) && MIREPLAYRAMREADDATA1[54]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[55] = (MIREPLAYRAMREADDATA1[55] !== 1'bz) && MIREPLAYRAMREADDATA1[55]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[56] = (MIREPLAYRAMREADDATA1[56] !== 1'bz) && MIREPLAYRAMREADDATA1[56]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[57] = (MIREPLAYRAMREADDATA1[57] !== 1'bz) && MIREPLAYRAMREADDATA1[57]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[58] = (MIREPLAYRAMREADDATA1[58] !== 1'bz) && MIREPLAYRAMREADDATA1[58]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[59] = (MIREPLAYRAMREADDATA1[59] !== 1'bz) && MIREPLAYRAMREADDATA1[59]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[5] = (MIREPLAYRAMREADDATA1[5] !== 1'bz) && MIREPLAYRAMREADDATA1[5]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[60] = (MIREPLAYRAMREADDATA1[60] !== 1'bz) && MIREPLAYRAMREADDATA1[60]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[61] = (MIREPLAYRAMREADDATA1[61] !== 1'bz) && MIREPLAYRAMREADDATA1[61]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[62] = (MIREPLAYRAMREADDATA1[62] !== 1'bz) && MIREPLAYRAMREADDATA1[62]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[63] = (MIREPLAYRAMREADDATA1[63] !== 1'bz) && MIREPLAYRAMREADDATA1[63]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[64] = (MIREPLAYRAMREADDATA1[64] !== 1'bz) && MIREPLAYRAMREADDATA1[64]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[65] = (MIREPLAYRAMREADDATA1[65] !== 1'bz) && MIREPLAYRAMREADDATA1[65]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[66] = (MIREPLAYRAMREADDATA1[66] !== 1'bz) && MIREPLAYRAMREADDATA1[66]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[67] = (MIREPLAYRAMREADDATA1[67] !== 1'bz) && MIREPLAYRAMREADDATA1[67]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[68] = (MIREPLAYRAMREADDATA1[68] !== 1'bz) && MIREPLAYRAMREADDATA1[68]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[69] = (MIREPLAYRAMREADDATA1[69] !== 1'bz) && MIREPLAYRAMREADDATA1[69]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[6] = (MIREPLAYRAMREADDATA1[6] !== 1'bz) && MIREPLAYRAMREADDATA1[6]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[70] = (MIREPLAYRAMREADDATA1[70] !== 1'bz) && MIREPLAYRAMREADDATA1[70]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[71] = (MIREPLAYRAMREADDATA1[71] !== 1'bz) && MIREPLAYRAMREADDATA1[71]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[72] = (MIREPLAYRAMREADDATA1[72] !== 1'bz) && MIREPLAYRAMREADDATA1[72]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[73] = (MIREPLAYRAMREADDATA1[73] !== 1'bz) && MIREPLAYRAMREADDATA1[73]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[74] = (MIREPLAYRAMREADDATA1[74] !== 1'bz) && MIREPLAYRAMREADDATA1[74]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[75] = (MIREPLAYRAMREADDATA1[75] !== 1'bz) && MIREPLAYRAMREADDATA1[75]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[76] = (MIREPLAYRAMREADDATA1[76] !== 1'bz) && MIREPLAYRAMREADDATA1[76]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[77] = (MIREPLAYRAMREADDATA1[77] !== 1'bz) && MIREPLAYRAMREADDATA1[77]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[78] = (MIREPLAYRAMREADDATA1[78] !== 1'bz) && MIREPLAYRAMREADDATA1[78]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[79] = (MIREPLAYRAMREADDATA1[79] !== 1'bz) && MIREPLAYRAMREADDATA1[79]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[7] = (MIREPLAYRAMREADDATA1[7] !== 1'bz) && MIREPLAYRAMREADDATA1[7]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[80] = (MIREPLAYRAMREADDATA1[80] !== 1'bz) && MIREPLAYRAMREADDATA1[80]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[81] = (MIREPLAYRAMREADDATA1[81] !== 1'bz) && MIREPLAYRAMREADDATA1[81]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[82] = (MIREPLAYRAMREADDATA1[82] !== 1'bz) && MIREPLAYRAMREADDATA1[82]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[83] = (MIREPLAYRAMREADDATA1[83] !== 1'bz) && MIREPLAYRAMREADDATA1[83]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[84] = (MIREPLAYRAMREADDATA1[84] !== 1'bz) && MIREPLAYRAMREADDATA1[84]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[85] = (MIREPLAYRAMREADDATA1[85] !== 1'bz) && MIREPLAYRAMREADDATA1[85]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[86] = (MIREPLAYRAMREADDATA1[86] !== 1'bz) && MIREPLAYRAMREADDATA1[86]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[87] = (MIREPLAYRAMREADDATA1[87] !== 1'bz) && MIREPLAYRAMREADDATA1[87]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[88] = (MIREPLAYRAMREADDATA1[88] !== 1'bz) && MIREPLAYRAMREADDATA1[88]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[89] = (MIREPLAYRAMREADDATA1[89] !== 1'bz) && MIREPLAYRAMREADDATA1[89]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[8] = (MIREPLAYRAMREADDATA1[8] !== 1'bz) && MIREPLAYRAMREADDATA1[8]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[90] = (MIREPLAYRAMREADDATA1[90] !== 1'bz) && MIREPLAYRAMREADDATA1[90]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[91] = (MIREPLAYRAMREADDATA1[91] !== 1'bz) && MIREPLAYRAMREADDATA1[91]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[92] = (MIREPLAYRAMREADDATA1[92] !== 1'bz) && MIREPLAYRAMREADDATA1[92]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[93] = (MIREPLAYRAMREADDATA1[93] !== 1'bz) && MIREPLAYRAMREADDATA1[93]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[94] = (MIREPLAYRAMREADDATA1[94] !== 1'bz) && MIREPLAYRAMREADDATA1[94]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[95] = (MIREPLAYRAMREADDATA1[95] !== 1'bz) && MIREPLAYRAMREADDATA1[95]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[96] = (MIREPLAYRAMREADDATA1[96] !== 1'bz) && MIREPLAYRAMREADDATA1[96]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[97] = (MIREPLAYRAMREADDATA1[97] !== 1'bz) && MIREPLAYRAMREADDATA1[97]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[98] = (MIREPLAYRAMREADDATA1[98] !== 1'bz) && MIREPLAYRAMREADDATA1[98]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[99] = (MIREPLAYRAMREADDATA1[99] !== 1'bz) && MIREPLAYRAMREADDATA1[99]; // rv 0 + assign MIREPLAYRAMREADDATA1_in[9] = (MIREPLAYRAMREADDATA1[9] !== 1'bz) && MIREPLAYRAMREADDATA1[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[0] = (MIRXCOMPLETIONRAMERRCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[10] = (MIRXCOMPLETIONRAMERRCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[11] = (MIRXCOMPLETIONRAMERRCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[1] = (MIRXCOMPLETIONRAMERRCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[2] = (MIRXCOMPLETIONRAMERRCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[3] = (MIRXCOMPLETIONRAMERRCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[4] = (MIRXCOMPLETIONRAMERRCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[5] = (MIRXCOMPLETIONRAMERRCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[6] = (MIRXCOMPLETIONRAMERRCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[7] = (MIRXCOMPLETIONRAMERRCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[8] = (MIRXCOMPLETIONRAMERRCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRCOR_in[9] = (MIRXCOMPLETIONRAMERRCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRCOR[9]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[0] = (MIRXCOMPLETIONRAMERRUNCOR[0] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[0]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[10] = (MIRXCOMPLETIONRAMERRUNCOR[10] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[10]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[11] = (MIRXCOMPLETIONRAMERRUNCOR[11] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[11]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[1] = (MIRXCOMPLETIONRAMERRUNCOR[1] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[1]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[2] = (MIRXCOMPLETIONRAMERRUNCOR[2] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[2]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[3] = (MIRXCOMPLETIONRAMERRUNCOR[3] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[3]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[4] = (MIRXCOMPLETIONRAMERRUNCOR[4] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[4]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[5] = (MIRXCOMPLETIONRAMERRUNCOR[5] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[5]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[6] = (MIRXCOMPLETIONRAMERRUNCOR[6] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[6]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[7] = (MIRXCOMPLETIONRAMERRUNCOR[7] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[7]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[8] = (MIRXCOMPLETIONRAMERRUNCOR[8] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[8]; // rv 0 + assign MIRXCOMPLETIONRAMERRUNCOR_in[9] = (MIRXCOMPLETIONRAMERRUNCOR[9] !== 1'bz) && MIRXCOMPLETIONRAMERRUNCOR[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[0] = (MIRXCOMPLETIONRAMREADDATA0[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[100] = (MIRXCOMPLETIONRAMREADDATA0[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[101] = (MIRXCOMPLETIONRAMREADDATA0[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[102] = (MIRXCOMPLETIONRAMREADDATA0[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[103] = (MIRXCOMPLETIONRAMREADDATA0[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[104] = (MIRXCOMPLETIONRAMREADDATA0[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[105] = (MIRXCOMPLETIONRAMREADDATA0[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[106] = (MIRXCOMPLETIONRAMREADDATA0[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[107] = (MIRXCOMPLETIONRAMREADDATA0[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[108] = (MIRXCOMPLETIONRAMREADDATA0[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[109] = (MIRXCOMPLETIONRAMREADDATA0[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[10] = (MIRXCOMPLETIONRAMREADDATA0[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[110] = (MIRXCOMPLETIONRAMREADDATA0[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[111] = (MIRXCOMPLETIONRAMREADDATA0[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[112] = (MIRXCOMPLETIONRAMREADDATA0[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[113] = (MIRXCOMPLETIONRAMREADDATA0[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[114] = (MIRXCOMPLETIONRAMREADDATA0[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[115] = (MIRXCOMPLETIONRAMREADDATA0[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[116] = (MIRXCOMPLETIONRAMREADDATA0[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[117] = (MIRXCOMPLETIONRAMREADDATA0[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[118] = (MIRXCOMPLETIONRAMREADDATA0[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[119] = (MIRXCOMPLETIONRAMREADDATA0[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[11] = (MIRXCOMPLETIONRAMREADDATA0[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[120] = (MIRXCOMPLETIONRAMREADDATA0[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[121] = (MIRXCOMPLETIONRAMREADDATA0[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[122] = (MIRXCOMPLETIONRAMREADDATA0[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[123] = (MIRXCOMPLETIONRAMREADDATA0[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[124] = (MIRXCOMPLETIONRAMREADDATA0[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[125] = (MIRXCOMPLETIONRAMREADDATA0[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[126] = (MIRXCOMPLETIONRAMREADDATA0[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[127] = (MIRXCOMPLETIONRAMREADDATA0[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[128] = (MIRXCOMPLETIONRAMREADDATA0[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[129] = (MIRXCOMPLETIONRAMREADDATA0[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[12] = (MIRXCOMPLETIONRAMREADDATA0[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[130] = (MIRXCOMPLETIONRAMREADDATA0[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[131] = (MIRXCOMPLETIONRAMREADDATA0[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[132] = (MIRXCOMPLETIONRAMREADDATA0[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[133] = (MIRXCOMPLETIONRAMREADDATA0[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[134] = (MIRXCOMPLETIONRAMREADDATA0[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[135] = (MIRXCOMPLETIONRAMREADDATA0[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[136] = (MIRXCOMPLETIONRAMREADDATA0[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[137] = (MIRXCOMPLETIONRAMREADDATA0[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[138] = (MIRXCOMPLETIONRAMREADDATA0[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[139] = (MIRXCOMPLETIONRAMREADDATA0[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[13] = (MIRXCOMPLETIONRAMREADDATA0[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[140] = (MIRXCOMPLETIONRAMREADDATA0[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[141] = (MIRXCOMPLETIONRAMREADDATA0[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[142] = (MIRXCOMPLETIONRAMREADDATA0[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[143] = (MIRXCOMPLETIONRAMREADDATA0[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[14] = (MIRXCOMPLETIONRAMREADDATA0[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[15] = (MIRXCOMPLETIONRAMREADDATA0[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[16] = (MIRXCOMPLETIONRAMREADDATA0[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[17] = (MIRXCOMPLETIONRAMREADDATA0[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[18] = (MIRXCOMPLETIONRAMREADDATA0[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[19] = (MIRXCOMPLETIONRAMREADDATA0[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[1] = (MIRXCOMPLETIONRAMREADDATA0[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[20] = (MIRXCOMPLETIONRAMREADDATA0[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[21] = (MIRXCOMPLETIONRAMREADDATA0[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[22] = (MIRXCOMPLETIONRAMREADDATA0[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[23] = (MIRXCOMPLETIONRAMREADDATA0[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[24] = (MIRXCOMPLETIONRAMREADDATA0[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[25] = (MIRXCOMPLETIONRAMREADDATA0[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[26] = (MIRXCOMPLETIONRAMREADDATA0[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[27] = (MIRXCOMPLETIONRAMREADDATA0[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[28] = (MIRXCOMPLETIONRAMREADDATA0[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[29] = (MIRXCOMPLETIONRAMREADDATA0[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[2] = (MIRXCOMPLETIONRAMREADDATA0[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[30] = (MIRXCOMPLETIONRAMREADDATA0[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[31] = (MIRXCOMPLETIONRAMREADDATA0[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[32] = (MIRXCOMPLETIONRAMREADDATA0[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[33] = (MIRXCOMPLETIONRAMREADDATA0[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[34] = (MIRXCOMPLETIONRAMREADDATA0[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[35] = (MIRXCOMPLETIONRAMREADDATA0[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[36] = (MIRXCOMPLETIONRAMREADDATA0[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[37] = (MIRXCOMPLETIONRAMREADDATA0[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[38] = (MIRXCOMPLETIONRAMREADDATA0[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[39] = (MIRXCOMPLETIONRAMREADDATA0[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[3] = (MIRXCOMPLETIONRAMREADDATA0[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[40] = (MIRXCOMPLETIONRAMREADDATA0[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[41] = (MIRXCOMPLETIONRAMREADDATA0[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[42] = (MIRXCOMPLETIONRAMREADDATA0[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[43] = (MIRXCOMPLETIONRAMREADDATA0[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[44] = (MIRXCOMPLETIONRAMREADDATA0[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[45] = (MIRXCOMPLETIONRAMREADDATA0[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[46] = (MIRXCOMPLETIONRAMREADDATA0[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[47] = (MIRXCOMPLETIONRAMREADDATA0[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[48] = (MIRXCOMPLETIONRAMREADDATA0[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[49] = (MIRXCOMPLETIONRAMREADDATA0[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[4] = (MIRXCOMPLETIONRAMREADDATA0[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[50] = (MIRXCOMPLETIONRAMREADDATA0[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[51] = (MIRXCOMPLETIONRAMREADDATA0[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[52] = (MIRXCOMPLETIONRAMREADDATA0[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[53] = (MIRXCOMPLETIONRAMREADDATA0[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[54] = (MIRXCOMPLETIONRAMREADDATA0[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[55] = (MIRXCOMPLETIONRAMREADDATA0[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[56] = (MIRXCOMPLETIONRAMREADDATA0[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[57] = (MIRXCOMPLETIONRAMREADDATA0[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[58] = (MIRXCOMPLETIONRAMREADDATA0[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[59] = (MIRXCOMPLETIONRAMREADDATA0[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[5] = (MIRXCOMPLETIONRAMREADDATA0[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[60] = (MIRXCOMPLETIONRAMREADDATA0[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[61] = (MIRXCOMPLETIONRAMREADDATA0[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[62] = (MIRXCOMPLETIONRAMREADDATA0[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[63] = (MIRXCOMPLETIONRAMREADDATA0[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[64] = (MIRXCOMPLETIONRAMREADDATA0[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[65] = (MIRXCOMPLETIONRAMREADDATA0[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[66] = (MIRXCOMPLETIONRAMREADDATA0[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[67] = (MIRXCOMPLETIONRAMREADDATA0[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[68] = (MIRXCOMPLETIONRAMREADDATA0[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[69] = (MIRXCOMPLETIONRAMREADDATA0[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[6] = (MIRXCOMPLETIONRAMREADDATA0[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[70] = (MIRXCOMPLETIONRAMREADDATA0[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[71] = (MIRXCOMPLETIONRAMREADDATA0[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[72] = (MIRXCOMPLETIONRAMREADDATA0[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[73] = (MIRXCOMPLETIONRAMREADDATA0[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[74] = (MIRXCOMPLETIONRAMREADDATA0[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[75] = (MIRXCOMPLETIONRAMREADDATA0[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[76] = (MIRXCOMPLETIONRAMREADDATA0[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[77] = (MIRXCOMPLETIONRAMREADDATA0[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[78] = (MIRXCOMPLETIONRAMREADDATA0[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[79] = (MIRXCOMPLETIONRAMREADDATA0[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[7] = (MIRXCOMPLETIONRAMREADDATA0[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[80] = (MIRXCOMPLETIONRAMREADDATA0[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[81] = (MIRXCOMPLETIONRAMREADDATA0[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[82] = (MIRXCOMPLETIONRAMREADDATA0[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[83] = (MIRXCOMPLETIONRAMREADDATA0[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[84] = (MIRXCOMPLETIONRAMREADDATA0[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[85] = (MIRXCOMPLETIONRAMREADDATA0[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[86] = (MIRXCOMPLETIONRAMREADDATA0[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[87] = (MIRXCOMPLETIONRAMREADDATA0[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[88] = (MIRXCOMPLETIONRAMREADDATA0[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[89] = (MIRXCOMPLETIONRAMREADDATA0[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[8] = (MIRXCOMPLETIONRAMREADDATA0[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[90] = (MIRXCOMPLETIONRAMREADDATA0[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[91] = (MIRXCOMPLETIONRAMREADDATA0[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[92] = (MIRXCOMPLETIONRAMREADDATA0[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[93] = (MIRXCOMPLETIONRAMREADDATA0[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[94] = (MIRXCOMPLETIONRAMREADDATA0[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[95] = (MIRXCOMPLETIONRAMREADDATA0[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[96] = (MIRXCOMPLETIONRAMREADDATA0[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[97] = (MIRXCOMPLETIONRAMREADDATA0[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[98] = (MIRXCOMPLETIONRAMREADDATA0[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[99] = (MIRXCOMPLETIONRAMREADDATA0[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA0_in[9] = (MIRXCOMPLETIONRAMREADDATA0[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA0[9]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[0] = (MIRXCOMPLETIONRAMREADDATA1[0] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[0]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[100] = (MIRXCOMPLETIONRAMREADDATA1[100] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[100]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[101] = (MIRXCOMPLETIONRAMREADDATA1[101] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[101]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[102] = (MIRXCOMPLETIONRAMREADDATA1[102] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[102]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[103] = (MIRXCOMPLETIONRAMREADDATA1[103] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[103]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[104] = (MIRXCOMPLETIONRAMREADDATA1[104] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[104]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[105] = (MIRXCOMPLETIONRAMREADDATA1[105] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[105]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[106] = (MIRXCOMPLETIONRAMREADDATA1[106] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[106]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[107] = (MIRXCOMPLETIONRAMREADDATA1[107] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[107]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[108] = (MIRXCOMPLETIONRAMREADDATA1[108] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[108]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[109] = (MIRXCOMPLETIONRAMREADDATA1[109] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[109]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[10] = (MIRXCOMPLETIONRAMREADDATA1[10] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[10]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[110] = (MIRXCOMPLETIONRAMREADDATA1[110] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[110]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[111] = (MIRXCOMPLETIONRAMREADDATA1[111] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[111]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[112] = (MIRXCOMPLETIONRAMREADDATA1[112] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[112]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[113] = (MIRXCOMPLETIONRAMREADDATA1[113] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[113]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[114] = (MIRXCOMPLETIONRAMREADDATA1[114] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[114]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[115] = (MIRXCOMPLETIONRAMREADDATA1[115] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[115]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[116] = (MIRXCOMPLETIONRAMREADDATA1[116] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[116]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[117] = (MIRXCOMPLETIONRAMREADDATA1[117] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[117]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[118] = (MIRXCOMPLETIONRAMREADDATA1[118] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[118]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[119] = (MIRXCOMPLETIONRAMREADDATA1[119] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[119]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[11] = (MIRXCOMPLETIONRAMREADDATA1[11] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[11]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[120] = (MIRXCOMPLETIONRAMREADDATA1[120] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[120]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[121] = (MIRXCOMPLETIONRAMREADDATA1[121] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[121]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[122] = (MIRXCOMPLETIONRAMREADDATA1[122] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[122]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[123] = (MIRXCOMPLETIONRAMREADDATA1[123] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[123]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[124] = (MIRXCOMPLETIONRAMREADDATA1[124] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[124]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[125] = (MIRXCOMPLETIONRAMREADDATA1[125] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[125]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[126] = (MIRXCOMPLETIONRAMREADDATA1[126] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[126]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[127] = (MIRXCOMPLETIONRAMREADDATA1[127] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[127]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[128] = (MIRXCOMPLETIONRAMREADDATA1[128] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[128]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[129] = (MIRXCOMPLETIONRAMREADDATA1[129] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[129]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[12] = (MIRXCOMPLETIONRAMREADDATA1[12] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[12]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[130] = (MIRXCOMPLETIONRAMREADDATA1[130] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[130]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[131] = (MIRXCOMPLETIONRAMREADDATA1[131] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[131]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[132] = (MIRXCOMPLETIONRAMREADDATA1[132] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[132]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[133] = (MIRXCOMPLETIONRAMREADDATA1[133] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[133]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[134] = (MIRXCOMPLETIONRAMREADDATA1[134] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[134]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[135] = (MIRXCOMPLETIONRAMREADDATA1[135] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[135]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[136] = (MIRXCOMPLETIONRAMREADDATA1[136] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[136]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[137] = (MIRXCOMPLETIONRAMREADDATA1[137] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[137]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[138] = (MIRXCOMPLETIONRAMREADDATA1[138] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[138]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[139] = (MIRXCOMPLETIONRAMREADDATA1[139] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[139]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[13] = (MIRXCOMPLETIONRAMREADDATA1[13] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[13]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[140] = (MIRXCOMPLETIONRAMREADDATA1[140] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[140]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[141] = (MIRXCOMPLETIONRAMREADDATA1[141] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[141]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[142] = (MIRXCOMPLETIONRAMREADDATA1[142] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[142]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[143] = (MIRXCOMPLETIONRAMREADDATA1[143] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[143]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[14] = (MIRXCOMPLETIONRAMREADDATA1[14] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[14]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[15] = (MIRXCOMPLETIONRAMREADDATA1[15] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[15]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[16] = (MIRXCOMPLETIONRAMREADDATA1[16] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[16]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[17] = (MIRXCOMPLETIONRAMREADDATA1[17] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[17]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[18] = (MIRXCOMPLETIONRAMREADDATA1[18] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[18]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[19] = (MIRXCOMPLETIONRAMREADDATA1[19] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[19]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[1] = (MIRXCOMPLETIONRAMREADDATA1[1] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[1]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[20] = (MIRXCOMPLETIONRAMREADDATA1[20] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[20]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[21] = (MIRXCOMPLETIONRAMREADDATA1[21] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[21]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[22] = (MIRXCOMPLETIONRAMREADDATA1[22] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[22]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[23] = (MIRXCOMPLETIONRAMREADDATA1[23] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[23]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[24] = (MIRXCOMPLETIONRAMREADDATA1[24] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[24]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[25] = (MIRXCOMPLETIONRAMREADDATA1[25] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[25]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[26] = (MIRXCOMPLETIONRAMREADDATA1[26] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[26]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[27] = (MIRXCOMPLETIONRAMREADDATA1[27] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[27]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[28] = (MIRXCOMPLETIONRAMREADDATA1[28] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[28]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[29] = (MIRXCOMPLETIONRAMREADDATA1[29] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[29]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[2] = (MIRXCOMPLETIONRAMREADDATA1[2] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[2]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[30] = (MIRXCOMPLETIONRAMREADDATA1[30] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[30]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[31] = (MIRXCOMPLETIONRAMREADDATA1[31] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[31]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[32] = (MIRXCOMPLETIONRAMREADDATA1[32] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[32]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[33] = (MIRXCOMPLETIONRAMREADDATA1[33] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[33]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[34] = (MIRXCOMPLETIONRAMREADDATA1[34] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[34]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[35] = (MIRXCOMPLETIONRAMREADDATA1[35] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[35]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[36] = (MIRXCOMPLETIONRAMREADDATA1[36] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[36]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[37] = (MIRXCOMPLETIONRAMREADDATA1[37] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[37]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[38] = (MIRXCOMPLETIONRAMREADDATA1[38] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[38]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[39] = (MIRXCOMPLETIONRAMREADDATA1[39] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[39]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[3] = (MIRXCOMPLETIONRAMREADDATA1[3] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[3]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[40] = (MIRXCOMPLETIONRAMREADDATA1[40] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[40]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[41] = (MIRXCOMPLETIONRAMREADDATA1[41] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[41]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[42] = (MIRXCOMPLETIONRAMREADDATA1[42] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[42]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[43] = (MIRXCOMPLETIONRAMREADDATA1[43] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[43]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[44] = (MIRXCOMPLETIONRAMREADDATA1[44] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[44]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[45] = (MIRXCOMPLETIONRAMREADDATA1[45] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[45]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[46] = (MIRXCOMPLETIONRAMREADDATA1[46] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[46]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[47] = (MIRXCOMPLETIONRAMREADDATA1[47] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[47]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[48] = (MIRXCOMPLETIONRAMREADDATA1[48] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[48]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[49] = (MIRXCOMPLETIONRAMREADDATA1[49] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[49]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[4] = (MIRXCOMPLETIONRAMREADDATA1[4] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[4]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[50] = (MIRXCOMPLETIONRAMREADDATA1[50] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[50]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[51] = (MIRXCOMPLETIONRAMREADDATA1[51] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[51]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[52] = (MIRXCOMPLETIONRAMREADDATA1[52] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[52]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[53] = (MIRXCOMPLETIONRAMREADDATA1[53] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[53]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[54] = (MIRXCOMPLETIONRAMREADDATA1[54] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[54]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[55] = (MIRXCOMPLETIONRAMREADDATA1[55] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[55]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[56] = (MIRXCOMPLETIONRAMREADDATA1[56] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[56]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[57] = (MIRXCOMPLETIONRAMREADDATA1[57] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[57]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[58] = (MIRXCOMPLETIONRAMREADDATA1[58] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[58]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[59] = (MIRXCOMPLETIONRAMREADDATA1[59] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[59]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[5] = (MIRXCOMPLETIONRAMREADDATA1[5] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[5]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[60] = (MIRXCOMPLETIONRAMREADDATA1[60] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[60]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[61] = (MIRXCOMPLETIONRAMREADDATA1[61] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[61]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[62] = (MIRXCOMPLETIONRAMREADDATA1[62] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[62]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[63] = (MIRXCOMPLETIONRAMREADDATA1[63] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[63]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[64] = (MIRXCOMPLETIONRAMREADDATA1[64] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[64]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[65] = (MIRXCOMPLETIONRAMREADDATA1[65] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[65]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[66] = (MIRXCOMPLETIONRAMREADDATA1[66] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[66]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[67] = (MIRXCOMPLETIONRAMREADDATA1[67] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[67]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[68] = (MIRXCOMPLETIONRAMREADDATA1[68] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[68]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[69] = (MIRXCOMPLETIONRAMREADDATA1[69] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[69]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[6] = (MIRXCOMPLETIONRAMREADDATA1[6] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[6]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[70] = (MIRXCOMPLETIONRAMREADDATA1[70] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[70]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[71] = (MIRXCOMPLETIONRAMREADDATA1[71] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[71]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[72] = (MIRXCOMPLETIONRAMREADDATA1[72] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[72]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[73] = (MIRXCOMPLETIONRAMREADDATA1[73] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[73]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[74] = (MIRXCOMPLETIONRAMREADDATA1[74] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[74]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[75] = (MIRXCOMPLETIONRAMREADDATA1[75] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[75]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[76] = (MIRXCOMPLETIONRAMREADDATA1[76] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[76]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[77] = (MIRXCOMPLETIONRAMREADDATA1[77] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[77]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[78] = (MIRXCOMPLETIONRAMREADDATA1[78] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[78]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[79] = (MIRXCOMPLETIONRAMREADDATA1[79] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[79]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[7] = (MIRXCOMPLETIONRAMREADDATA1[7] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[7]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[80] = (MIRXCOMPLETIONRAMREADDATA1[80] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[80]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[81] = (MIRXCOMPLETIONRAMREADDATA1[81] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[81]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[82] = (MIRXCOMPLETIONRAMREADDATA1[82] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[82]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[83] = (MIRXCOMPLETIONRAMREADDATA1[83] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[83]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[84] = (MIRXCOMPLETIONRAMREADDATA1[84] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[84]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[85] = (MIRXCOMPLETIONRAMREADDATA1[85] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[85]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[86] = (MIRXCOMPLETIONRAMREADDATA1[86] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[86]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[87] = (MIRXCOMPLETIONRAMREADDATA1[87] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[87]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[88] = (MIRXCOMPLETIONRAMREADDATA1[88] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[88]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[89] = (MIRXCOMPLETIONRAMREADDATA1[89] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[89]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[8] = (MIRXCOMPLETIONRAMREADDATA1[8] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[8]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[90] = (MIRXCOMPLETIONRAMREADDATA1[90] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[90]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[91] = (MIRXCOMPLETIONRAMREADDATA1[91] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[91]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[92] = (MIRXCOMPLETIONRAMREADDATA1[92] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[92]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[93] = (MIRXCOMPLETIONRAMREADDATA1[93] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[93]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[94] = (MIRXCOMPLETIONRAMREADDATA1[94] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[94]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[95] = (MIRXCOMPLETIONRAMREADDATA1[95] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[95]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[96] = (MIRXCOMPLETIONRAMREADDATA1[96] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[96]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[97] = (MIRXCOMPLETIONRAMREADDATA1[97] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[97]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[98] = (MIRXCOMPLETIONRAMREADDATA1[98] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[98]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[99] = (MIRXCOMPLETIONRAMREADDATA1[99] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[99]; // rv 0 + assign MIRXCOMPLETIONRAMREADDATA1_in[9] = (MIRXCOMPLETIONRAMREADDATA1[9] !== 1'bz) && MIRXCOMPLETIONRAMREADDATA1[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRCOR[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[0] = (MIRXPOSTEDREQUESTRAMERRUNCOR[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[1] = (MIRXPOSTEDREQUESTRAMERRUNCOR[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[2] = (MIRXPOSTEDREQUESTRAMERRUNCOR[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[3] = (MIRXPOSTEDREQUESTRAMERRUNCOR[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[4] = (MIRXPOSTEDREQUESTRAMERRUNCOR[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMERRUNCOR_in[5] = (MIRXPOSTEDREQUESTRAMERRUNCOR[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMERRUNCOR[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA0[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA0[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA0[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA0[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA0[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA0[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA0[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA0[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA0[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA0[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA0[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA0[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA0[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA0[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA0[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA0[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA0[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA0[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA0[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA0[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA0[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA0[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA0[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA0[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA0[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA0[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA0[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA0[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA0[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA0[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA0[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA0[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA0[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA0[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA0[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA0[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA0[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA0[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA0[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA0[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA0[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA0[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA0[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA0[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA0[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA0[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA0[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA0[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA0[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA0[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA0[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA0[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA0[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA0[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA0[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA0[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA0[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA0[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA0[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA0[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA0[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA0[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA0[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA0[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA0[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA0[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA0[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA0[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA0[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA0[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA0[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA0[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA0[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA0[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA0[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA0[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA0[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA0[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA0[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA0[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA0[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA0[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA0[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA0[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA0[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA0[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA0[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA0[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA0[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA0[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA0[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA0[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA0[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA0[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA0[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA0[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA0[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA0[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA0[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA0[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA0[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA0[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA0[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA0[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA0[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA0[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA0[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA0[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA0[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA0[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA0[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA0[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA0[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA0[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA0[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA0[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA0[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA0[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA0[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA0[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA0[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA0[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA0[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA0[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA0[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA0[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA0[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA0[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA0[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA0[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA0[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA0[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA0[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA0[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA0[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA0[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA0[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA0[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA0[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA0[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA0[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA0[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA0[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA0_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA0[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA0[9]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[0] = (MIRXPOSTEDREQUESTRAMREADDATA1[0] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[0]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[100] = (MIRXPOSTEDREQUESTRAMREADDATA1[100] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[100]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[101] = (MIRXPOSTEDREQUESTRAMREADDATA1[101] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[101]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[102] = (MIRXPOSTEDREQUESTRAMREADDATA1[102] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[102]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[103] = (MIRXPOSTEDREQUESTRAMREADDATA1[103] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[103]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[104] = (MIRXPOSTEDREQUESTRAMREADDATA1[104] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[104]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[105] = (MIRXPOSTEDREQUESTRAMREADDATA1[105] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[105]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[106] = (MIRXPOSTEDREQUESTRAMREADDATA1[106] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[106]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[107] = (MIRXPOSTEDREQUESTRAMREADDATA1[107] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[107]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[108] = (MIRXPOSTEDREQUESTRAMREADDATA1[108] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[108]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[109] = (MIRXPOSTEDREQUESTRAMREADDATA1[109] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[109]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[10] = (MIRXPOSTEDREQUESTRAMREADDATA1[10] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[10]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[110] = (MIRXPOSTEDREQUESTRAMREADDATA1[110] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[110]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[111] = (MIRXPOSTEDREQUESTRAMREADDATA1[111] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[111]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[112] = (MIRXPOSTEDREQUESTRAMREADDATA1[112] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[112]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[113] = (MIRXPOSTEDREQUESTRAMREADDATA1[113] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[113]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[114] = (MIRXPOSTEDREQUESTRAMREADDATA1[114] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[114]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[115] = (MIRXPOSTEDREQUESTRAMREADDATA1[115] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[115]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[116] = (MIRXPOSTEDREQUESTRAMREADDATA1[116] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[116]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[117] = (MIRXPOSTEDREQUESTRAMREADDATA1[117] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[117]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[118] = (MIRXPOSTEDREQUESTRAMREADDATA1[118] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[118]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[119] = (MIRXPOSTEDREQUESTRAMREADDATA1[119] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[119]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[11] = (MIRXPOSTEDREQUESTRAMREADDATA1[11] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[11]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[120] = (MIRXPOSTEDREQUESTRAMREADDATA1[120] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[120]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[121] = (MIRXPOSTEDREQUESTRAMREADDATA1[121] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[121]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[122] = (MIRXPOSTEDREQUESTRAMREADDATA1[122] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[122]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[123] = (MIRXPOSTEDREQUESTRAMREADDATA1[123] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[123]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[124] = (MIRXPOSTEDREQUESTRAMREADDATA1[124] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[124]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[125] = (MIRXPOSTEDREQUESTRAMREADDATA1[125] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[125]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[126] = (MIRXPOSTEDREQUESTRAMREADDATA1[126] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[126]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[127] = (MIRXPOSTEDREQUESTRAMREADDATA1[127] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[127]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[128] = (MIRXPOSTEDREQUESTRAMREADDATA1[128] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[128]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[129] = (MIRXPOSTEDREQUESTRAMREADDATA1[129] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[129]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[12] = (MIRXPOSTEDREQUESTRAMREADDATA1[12] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[12]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[130] = (MIRXPOSTEDREQUESTRAMREADDATA1[130] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[130]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[131] = (MIRXPOSTEDREQUESTRAMREADDATA1[131] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[131]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[132] = (MIRXPOSTEDREQUESTRAMREADDATA1[132] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[132]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[133] = (MIRXPOSTEDREQUESTRAMREADDATA1[133] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[133]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[134] = (MIRXPOSTEDREQUESTRAMREADDATA1[134] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[134]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[135] = (MIRXPOSTEDREQUESTRAMREADDATA1[135] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[135]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[136] = (MIRXPOSTEDREQUESTRAMREADDATA1[136] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[136]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[137] = (MIRXPOSTEDREQUESTRAMREADDATA1[137] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[137]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[138] = (MIRXPOSTEDREQUESTRAMREADDATA1[138] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[138]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[139] = (MIRXPOSTEDREQUESTRAMREADDATA1[139] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[139]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[13] = (MIRXPOSTEDREQUESTRAMREADDATA1[13] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[13]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[140] = (MIRXPOSTEDREQUESTRAMREADDATA1[140] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[140]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[141] = (MIRXPOSTEDREQUESTRAMREADDATA1[141] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[141]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[142] = (MIRXPOSTEDREQUESTRAMREADDATA1[142] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[142]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[143] = (MIRXPOSTEDREQUESTRAMREADDATA1[143] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[143]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[14] = (MIRXPOSTEDREQUESTRAMREADDATA1[14] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[14]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[15] = (MIRXPOSTEDREQUESTRAMREADDATA1[15] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[15]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[16] = (MIRXPOSTEDREQUESTRAMREADDATA1[16] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[16]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[17] = (MIRXPOSTEDREQUESTRAMREADDATA1[17] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[17]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[18] = (MIRXPOSTEDREQUESTRAMREADDATA1[18] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[18]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[19] = (MIRXPOSTEDREQUESTRAMREADDATA1[19] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[19]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[1] = (MIRXPOSTEDREQUESTRAMREADDATA1[1] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[1]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[20] = (MIRXPOSTEDREQUESTRAMREADDATA1[20] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[20]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[21] = (MIRXPOSTEDREQUESTRAMREADDATA1[21] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[21]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[22] = (MIRXPOSTEDREQUESTRAMREADDATA1[22] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[22]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[23] = (MIRXPOSTEDREQUESTRAMREADDATA1[23] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[23]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[24] = (MIRXPOSTEDREQUESTRAMREADDATA1[24] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[24]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[25] = (MIRXPOSTEDREQUESTRAMREADDATA1[25] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[25]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[26] = (MIRXPOSTEDREQUESTRAMREADDATA1[26] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[26]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[27] = (MIRXPOSTEDREQUESTRAMREADDATA1[27] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[27]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[28] = (MIRXPOSTEDREQUESTRAMREADDATA1[28] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[28]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[29] = (MIRXPOSTEDREQUESTRAMREADDATA1[29] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[29]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[2] = (MIRXPOSTEDREQUESTRAMREADDATA1[2] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[2]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[30] = (MIRXPOSTEDREQUESTRAMREADDATA1[30] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[30]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[31] = (MIRXPOSTEDREQUESTRAMREADDATA1[31] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[31]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[32] = (MIRXPOSTEDREQUESTRAMREADDATA1[32] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[32]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[33] = (MIRXPOSTEDREQUESTRAMREADDATA1[33] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[33]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[34] = (MIRXPOSTEDREQUESTRAMREADDATA1[34] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[34]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[35] = (MIRXPOSTEDREQUESTRAMREADDATA1[35] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[35]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[36] = (MIRXPOSTEDREQUESTRAMREADDATA1[36] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[36]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[37] = (MIRXPOSTEDREQUESTRAMREADDATA1[37] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[37]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[38] = (MIRXPOSTEDREQUESTRAMREADDATA1[38] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[38]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[39] = (MIRXPOSTEDREQUESTRAMREADDATA1[39] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[39]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[3] = (MIRXPOSTEDREQUESTRAMREADDATA1[3] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[3]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[40] = (MIRXPOSTEDREQUESTRAMREADDATA1[40] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[40]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[41] = (MIRXPOSTEDREQUESTRAMREADDATA1[41] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[41]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[42] = (MIRXPOSTEDREQUESTRAMREADDATA1[42] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[42]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[43] = (MIRXPOSTEDREQUESTRAMREADDATA1[43] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[43]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[44] = (MIRXPOSTEDREQUESTRAMREADDATA1[44] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[44]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[45] = (MIRXPOSTEDREQUESTRAMREADDATA1[45] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[45]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[46] = (MIRXPOSTEDREQUESTRAMREADDATA1[46] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[46]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[47] = (MIRXPOSTEDREQUESTRAMREADDATA1[47] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[47]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[48] = (MIRXPOSTEDREQUESTRAMREADDATA1[48] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[48]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[49] = (MIRXPOSTEDREQUESTRAMREADDATA1[49] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[49]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[4] = (MIRXPOSTEDREQUESTRAMREADDATA1[4] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[4]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[50] = (MIRXPOSTEDREQUESTRAMREADDATA1[50] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[50]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[51] = (MIRXPOSTEDREQUESTRAMREADDATA1[51] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[51]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[52] = (MIRXPOSTEDREQUESTRAMREADDATA1[52] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[52]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[53] = (MIRXPOSTEDREQUESTRAMREADDATA1[53] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[53]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[54] = (MIRXPOSTEDREQUESTRAMREADDATA1[54] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[54]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[55] = (MIRXPOSTEDREQUESTRAMREADDATA1[55] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[55]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[56] = (MIRXPOSTEDREQUESTRAMREADDATA1[56] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[56]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[57] = (MIRXPOSTEDREQUESTRAMREADDATA1[57] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[57]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[58] = (MIRXPOSTEDREQUESTRAMREADDATA1[58] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[58]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[59] = (MIRXPOSTEDREQUESTRAMREADDATA1[59] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[59]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[5] = (MIRXPOSTEDREQUESTRAMREADDATA1[5] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[5]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[60] = (MIRXPOSTEDREQUESTRAMREADDATA1[60] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[60]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[61] = (MIRXPOSTEDREQUESTRAMREADDATA1[61] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[61]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[62] = (MIRXPOSTEDREQUESTRAMREADDATA1[62] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[62]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[63] = (MIRXPOSTEDREQUESTRAMREADDATA1[63] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[63]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[64] = (MIRXPOSTEDREQUESTRAMREADDATA1[64] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[64]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[65] = (MIRXPOSTEDREQUESTRAMREADDATA1[65] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[65]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[66] = (MIRXPOSTEDREQUESTRAMREADDATA1[66] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[66]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[67] = (MIRXPOSTEDREQUESTRAMREADDATA1[67] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[67]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[68] = (MIRXPOSTEDREQUESTRAMREADDATA1[68] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[68]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[69] = (MIRXPOSTEDREQUESTRAMREADDATA1[69] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[69]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[6] = (MIRXPOSTEDREQUESTRAMREADDATA1[6] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[6]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[70] = (MIRXPOSTEDREQUESTRAMREADDATA1[70] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[70]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[71] = (MIRXPOSTEDREQUESTRAMREADDATA1[71] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[71]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[72] = (MIRXPOSTEDREQUESTRAMREADDATA1[72] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[72]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[73] = (MIRXPOSTEDREQUESTRAMREADDATA1[73] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[73]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[74] = (MIRXPOSTEDREQUESTRAMREADDATA1[74] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[74]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[75] = (MIRXPOSTEDREQUESTRAMREADDATA1[75] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[75]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[76] = (MIRXPOSTEDREQUESTRAMREADDATA1[76] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[76]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[77] = (MIRXPOSTEDREQUESTRAMREADDATA1[77] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[77]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[78] = (MIRXPOSTEDREQUESTRAMREADDATA1[78] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[78]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[79] = (MIRXPOSTEDREQUESTRAMREADDATA1[79] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[79]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[7] = (MIRXPOSTEDREQUESTRAMREADDATA1[7] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[7]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[80] = (MIRXPOSTEDREQUESTRAMREADDATA1[80] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[80]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[81] = (MIRXPOSTEDREQUESTRAMREADDATA1[81] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[81]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[82] = (MIRXPOSTEDREQUESTRAMREADDATA1[82] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[82]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[83] = (MIRXPOSTEDREQUESTRAMREADDATA1[83] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[83]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[84] = (MIRXPOSTEDREQUESTRAMREADDATA1[84] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[84]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[85] = (MIRXPOSTEDREQUESTRAMREADDATA1[85] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[85]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[86] = (MIRXPOSTEDREQUESTRAMREADDATA1[86] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[86]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[87] = (MIRXPOSTEDREQUESTRAMREADDATA1[87] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[87]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[88] = (MIRXPOSTEDREQUESTRAMREADDATA1[88] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[88]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[89] = (MIRXPOSTEDREQUESTRAMREADDATA1[89] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[89]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[8] = (MIRXPOSTEDREQUESTRAMREADDATA1[8] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[8]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[90] = (MIRXPOSTEDREQUESTRAMREADDATA1[90] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[90]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[91] = (MIRXPOSTEDREQUESTRAMREADDATA1[91] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[91]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[92] = (MIRXPOSTEDREQUESTRAMREADDATA1[92] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[92]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[93] = (MIRXPOSTEDREQUESTRAMREADDATA1[93] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[93]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[94] = (MIRXPOSTEDREQUESTRAMREADDATA1[94] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[94]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[95] = (MIRXPOSTEDREQUESTRAMREADDATA1[95] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[95]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[96] = (MIRXPOSTEDREQUESTRAMREADDATA1[96] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[96]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[97] = (MIRXPOSTEDREQUESTRAMREADDATA1[97] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[97]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[98] = (MIRXPOSTEDREQUESTRAMREADDATA1[98] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[98]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[99] = (MIRXPOSTEDREQUESTRAMREADDATA1[99] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[99]; // rv 0 + assign MIRXPOSTEDREQUESTRAMREADDATA1_in[9] = (MIRXPOSTEDREQUESTRAMREADDATA1[9] !== 1'bz) && MIRXPOSTEDREQUESTRAMREADDATA1[9]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[0] = (PCIECOMPLDELIVEREDTAG0[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[1] = (PCIECOMPLDELIVEREDTAG0[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[2] = (PCIECOMPLDELIVEREDTAG0[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[3] = (PCIECOMPLDELIVEREDTAG0[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[4] = (PCIECOMPLDELIVEREDTAG0[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[5] = (PCIECOMPLDELIVEREDTAG0[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[6] = (PCIECOMPLDELIVEREDTAG0[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG0_in[7] = (PCIECOMPLDELIVEREDTAG0[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG0[7]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[0] = (PCIECOMPLDELIVEREDTAG1[0] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[0]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[1] = (PCIECOMPLDELIVEREDTAG1[1] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[1]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[2] = (PCIECOMPLDELIVEREDTAG1[2] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[2]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[3] = (PCIECOMPLDELIVEREDTAG1[3] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[3]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[4] = (PCIECOMPLDELIVEREDTAG1[4] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[4]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[5] = (PCIECOMPLDELIVEREDTAG1[5] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[5]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[6] = (PCIECOMPLDELIVEREDTAG1[6] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[6]; // rv 0 + assign PCIECOMPLDELIVEREDTAG1_in[7] = (PCIECOMPLDELIVEREDTAG1[7] !== 1'bz) && PCIECOMPLDELIVEREDTAG1[7]; // rv 0 + assign PCIECOMPLDELIVERED_in[0] = (PCIECOMPLDELIVERED[0] !== 1'bz) && PCIECOMPLDELIVERED[0]; // rv 0 + assign PCIECOMPLDELIVERED_in[1] = (PCIECOMPLDELIVERED[1] !== 1'bz) && PCIECOMPLDELIVERED[1]; // rv 0 + assign PCIECQNPREQ_in[0] = (PCIECQNPREQ[0] === 1'bz) || PCIECQNPREQ[0]; // rv 1 + assign PCIECQNPREQ_in[1] = (PCIECQNPREQ[1] === 1'bz) || PCIECQNPREQ[1]; // rv 1 + assign PCIECQNPUSERCREDITRCVD_in = (PCIECQNPUSERCREDITRCVD !== 1'bz) && PCIECQNPUSERCREDITRCVD; // rv 0 + assign PCIECQPIPELINEEMPTY_in = (PCIECQPIPELINEEMPTY !== 1'bz) && PCIECQPIPELINEEMPTY; // rv 0 + assign PCIEPOSTEDREQDELIVERED_in = (PCIEPOSTEDREQDELIVERED !== 1'bz) && PCIEPOSTEDREQDELIVERED; // rv 0 + assign PIPECLK_in = (PIPECLK !== 1'bz) && PIPECLK; // rv 0 + assign PIPEEQFS_in[0] = (PIPEEQFS[0] !== 1'bz) && PIPEEQFS[0]; // rv 0 + assign PIPEEQFS_in[1] = (PIPEEQFS[1] !== 1'bz) && PIPEEQFS[1]; // rv 0 + assign PIPEEQFS_in[2] = (PIPEEQFS[2] !== 1'bz) && PIPEEQFS[2]; // rv 0 + assign PIPEEQFS_in[3] = (PIPEEQFS[3] !== 1'bz) && PIPEEQFS[3]; // rv 0 + assign PIPEEQFS_in[4] = (PIPEEQFS[4] !== 1'bz) && PIPEEQFS[4]; // rv 0 + assign PIPEEQFS_in[5] = (PIPEEQFS[5] !== 1'bz) && PIPEEQFS[5]; // rv 0 + assign PIPEEQLF_in[0] = (PIPEEQLF[0] !== 1'bz) && PIPEEQLF[0]; // rv 0 + assign PIPEEQLF_in[1] = (PIPEEQLF[1] !== 1'bz) && PIPEEQLF[1]; // rv 0 + assign PIPEEQLF_in[2] = (PIPEEQLF[2] !== 1'bz) && PIPEEQLF[2]; // rv 0 + assign PIPEEQLF_in[3] = (PIPEEQLF[3] !== 1'bz) && PIPEEQLF[3]; // rv 0 + assign PIPEEQLF_in[4] = (PIPEEQLF[4] !== 1'bz) && PIPEEQLF[4]; // rv 0 + assign PIPEEQLF_in[5] = (PIPEEQLF[5] !== 1'bz) && PIPEEQLF[5]; // rv 0 + assign PIPERX00CHARISK_in[0] = (PIPERX00CHARISK[0] === 1'bz) || PIPERX00CHARISK[0]; // rv 1 + assign PIPERX00CHARISK_in[1] = (PIPERX00CHARISK[1] === 1'bz) || PIPERX00CHARISK[1]; // rv 1 + assign PIPERX00DATAVALID_in = (PIPERX00DATAVALID !== 1'bz) && PIPERX00DATAVALID; // rv 0 + assign PIPERX00DATA_in[0] = (PIPERX00DATA[0] !== 1'bz) && PIPERX00DATA[0]; // rv 0 + assign PIPERX00DATA_in[10] = (PIPERX00DATA[10] !== 1'bz) && PIPERX00DATA[10]; // rv 0 + assign PIPERX00DATA_in[11] = (PIPERX00DATA[11] !== 1'bz) && PIPERX00DATA[11]; // rv 0 + assign PIPERX00DATA_in[12] = (PIPERX00DATA[12] !== 1'bz) && PIPERX00DATA[12]; // rv 0 + assign PIPERX00DATA_in[13] = (PIPERX00DATA[13] !== 1'bz) && PIPERX00DATA[13]; // rv 0 + assign PIPERX00DATA_in[14] = (PIPERX00DATA[14] !== 1'bz) && PIPERX00DATA[14]; // rv 0 + assign PIPERX00DATA_in[15] = (PIPERX00DATA[15] !== 1'bz) && PIPERX00DATA[15]; // rv 0 + assign PIPERX00DATA_in[16] = (PIPERX00DATA[16] !== 1'bz) && PIPERX00DATA[16]; // rv 0 + assign PIPERX00DATA_in[17] = (PIPERX00DATA[17] !== 1'bz) && PIPERX00DATA[17]; // rv 0 + assign PIPERX00DATA_in[18] = (PIPERX00DATA[18] !== 1'bz) && PIPERX00DATA[18]; // rv 0 + assign PIPERX00DATA_in[19] = (PIPERX00DATA[19] !== 1'bz) && PIPERX00DATA[19]; // rv 0 + assign PIPERX00DATA_in[1] = (PIPERX00DATA[1] !== 1'bz) && PIPERX00DATA[1]; // rv 0 + assign PIPERX00DATA_in[20] = (PIPERX00DATA[20] !== 1'bz) && PIPERX00DATA[20]; // rv 0 + assign PIPERX00DATA_in[21] = (PIPERX00DATA[21] !== 1'bz) && PIPERX00DATA[21]; // rv 0 + assign PIPERX00DATA_in[22] = (PIPERX00DATA[22] !== 1'bz) && PIPERX00DATA[22]; // rv 0 + assign PIPERX00DATA_in[23] = (PIPERX00DATA[23] !== 1'bz) && PIPERX00DATA[23]; // rv 0 + assign PIPERX00DATA_in[24] = (PIPERX00DATA[24] !== 1'bz) && PIPERX00DATA[24]; // rv 0 + assign PIPERX00DATA_in[25] = (PIPERX00DATA[25] !== 1'bz) && PIPERX00DATA[25]; // rv 0 + assign PIPERX00DATA_in[26] = (PIPERX00DATA[26] !== 1'bz) && PIPERX00DATA[26]; // rv 0 + assign PIPERX00DATA_in[27] = (PIPERX00DATA[27] !== 1'bz) && PIPERX00DATA[27]; // rv 0 + assign PIPERX00DATA_in[28] = (PIPERX00DATA[28] !== 1'bz) && PIPERX00DATA[28]; // rv 0 + assign PIPERX00DATA_in[29] = (PIPERX00DATA[29] !== 1'bz) && PIPERX00DATA[29]; // rv 0 + assign PIPERX00DATA_in[2] = (PIPERX00DATA[2] !== 1'bz) && PIPERX00DATA[2]; // rv 0 + assign PIPERX00DATA_in[30] = (PIPERX00DATA[30] !== 1'bz) && PIPERX00DATA[30]; // rv 0 + assign PIPERX00DATA_in[31] = (PIPERX00DATA[31] !== 1'bz) && PIPERX00DATA[31]; // rv 0 + assign PIPERX00DATA_in[3] = (PIPERX00DATA[3] !== 1'bz) && PIPERX00DATA[3]; // rv 0 + assign PIPERX00DATA_in[4] = (PIPERX00DATA[4] !== 1'bz) && PIPERX00DATA[4]; // rv 0 + assign PIPERX00DATA_in[5] = (PIPERX00DATA[5] !== 1'bz) && PIPERX00DATA[5]; // rv 0 + assign PIPERX00DATA_in[6] = (PIPERX00DATA[6] !== 1'bz) && PIPERX00DATA[6]; // rv 0 + assign PIPERX00DATA_in[7] = (PIPERX00DATA[7] !== 1'bz) && PIPERX00DATA[7]; // rv 0 + assign PIPERX00DATA_in[8] = (PIPERX00DATA[8] !== 1'bz) && PIPERX00DATA[8]; // rv 0 + assign PIPERX00DATA_in[9] = (PIPERX00DATA[9] !== 1'bz) && PIPERX00DATA[9]; // rv 0 + assign PIPERX00ELECIDLE_in = (PIPERX00ELECIDLE === 1'bz) || PIPERX00ELECIDLE; // rv 1 + assign PIPERX00EQDONE_in = (PIPERX00EQDONE !== 1'bz) && PIPERX00EQDONE; // rv 0 + assign PIPERX00EQLPADAPTDONE_in = (PIPERX00EQLPADAPTDONE !== 1'bz) && PIPERX00EQLPADAPTDONE; // rv 0 + assign PIPERX00EQLPLFFSSEL_in = (PIPERX00EQLPLFFSSEL !== 1'bz) && PIPERX00EQLPLFFSSEL; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX00EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX00EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX00EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX00EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX00EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX00EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX00EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX00EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX00EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX00EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX00EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX00EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX00EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX00EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX00EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX00EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX00EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX00EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX00EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX00EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX00PHYSTATUS_in = (PIPERX00PHYSTATUS === 1'bz) || PIPERX00PHYSTATUS; // rv 1 + assign PIPERX00STARTBLOCK_in[0] = (PIPERX00STARTBLOCK[0] !== 1'bz) && PIPERX00STARTBLOCK[0]; // rv 0 + assign PIPERX00STARTBLOCK_in[1] = (PIPERX00STARTBLOCK[1] !== 1'bz) && PIPERX00STARTBLOCK[1]; // rv 0 + assign PIPERX00STATUS_in[0] = (PIPERX00STATUS[0] !== 1'bz) && PIPERX00STATUS[0]; // rv 0 + assign PIPERX00STATUS_in[1] = (PIPERX00STATUS[1] !== 1'bz) && PIPERX00STATUS[1]; // rv 0 + assign PIPERX00STATUS_in[2] = (PIPERX00STATUS[2] !== 1'bz) && PIPERX00STATUS[2]; // rv 0 + assign PIPERX00SYNCHEADER_in[0] = (PIPERX00SYNCHEADER[0] !== 1'bz) && PIPERX00SYNCHEADER[0]; // rv 0 + assign PIPERX00SYNCHEADER_in[1] = (PIPERX00SYNCHEADER[1] !== 1'bz) && PIPERX00SYNCHEADER[1]; // rv 0 + assign PIPERX00VALID_in = (PIPERX00VALID !== 1'bz) && PIPERX00VALID; // rv 0 + assign PIPERX01CHARISK_in[0] = (PIPERX01CHARISK[0] === 1'bz) || PIPERX01CHARISK[0]; // rv 1 + assign PIPERX01CHARISK_in[1] = (PIPERX01CHARISK[1] === 1'bz) || PIPERX01CHARISK[1]; // rv 1 + assign PIPERX01DATAVALID_in = (PIPERX01DATAVALID !== 1'bz) && PIPERX01DATAVALID; // rv 0 + assign PIPERX01DATA_in[0] = (PIPERX01DATA[0] !== 1'bz) && PIPERX01DATA[0]; // rv 0 + assign PIPERX01DATA_in[10] = (PIPERX01DATA[10] !== 1'bz) && PIPERX01DATA[10]; // rv 0 + assign PIPERX01DATA_in[11] = (PIPERX01DATA[11] !== 1'bz) && PIPERX01DATA[11]; // rv 0 + assign PIPERX01DATA_in[12] = (PIPERX01DATA[12] !== 1'bz) && PIPERX01DATA[12]; // rv 0 + assign PIPERX01DATA_in[13] = (PIPERX01DATA[13] !== 1'bz) && PIPERX01DATA[13]; // rv 0 + assign PIPERX01DATA_in[14] = (PIPERX01DATA[14] !== 1'bz) && PIPERX01DATA[14]; // rv 0 + assign PIPERX01DATA_in[15] = (PIPERX01DATA[15] !== 1'bz) && PIPERX01DATA[15]; // rv 0 + assign PIPERX01DATA_in[16] = (PIPERX01DATA[16] !== 1'bz) && PIPERX01DATA[16]; // rv 0 + assign PIPERX01DATA_in[17] = (PIPERX01DATA[17] !== 1'bz) && PIPERX01DATA[17]; // rv 0 + assign PIPERX01DATA_in[18] = (PIPERX01DATA[18] !== 1'bz) && PIPERX01DATA[18]; // rv 0 + assign PIPERX01DATA_in[19] = (PIPERX01DATA[19] !== 1'bz) && PIPERX01DATA[19]; // rv 0 + assign PIPERX01DATA_in[1] = (PIPERX01DATA[1] !== 1'bz) && PIPERX01DATA[1]; // rv 0 + assign PIPERX01DATA_in[20] = (PIPERX01DATA[20] !== 1'bz) && PIPERX01DATA[20]; // rv 0 + assign PIPERX01DATA_in[21] = (PIPERX01DATA[21] !== 1'bz) && PIPERX01DATA[21]; // rv 0 + assign PIPERX01DATA_in[22] = (PIPERX01DATA[22] !== 1'bz) && PIPERX01DATA[22]; // rv 0 + assign PIPERX01DATA_in[23] = (PIPERX01DATA[23] !== 1'bz) && PIPERX01DATA[23]; // rv 0 + assign PIPERX01DATA_in[24] = (PIPERX01DATA[24] !== 1'bz) && PIPERX01DATA[24]; // rv 0 + assign PIPERX01DATA_in[25] = (PIPERX01DATA[25] !== 1'bz) && PIPERX01DATA[25]; // rv 0 + assign PIPERX01DATA_in[26] = (PIPERX01DATA[26] !== 1'bz) && PIPERX01DATA[26]; // rv 0 + assign PIPERX01DATA_in[27] = (PIPERX01DATA[27] !== 1'bz) && PIPERX01DATA[27]; // rv 0 + assign PIPERX01DATA_in[28] = (PIPERX01DATA[28] !== 1'bz) && PIPERX01DATA[28]; // rv 0 + assign PIPERX01DATA_in[29] = (PIPERX01DATA[29] !== 1'bz) && PIPERX01DATA[29]; // rv 0 + assign PIPERX01DATA_in[2] = (PIPERX01DATA[2] !== 1'bz) && PIPERX01DATA[2]; // rv 0 + assign PIPERX01DATA_in[30] = (PIPERX01DATA[30] !== 1'bz) && PIPERX01DATA[30]; // rv 0 + assign PIPERX01DATA_in[31] = (PIPERX01DATA[31] !== 1'bz) && PIPERX01DATA[31]; // rv 0 + assign PIPERX01DATA_in[3] = (PIPERX01DATA[3] !== 1'bz) && PIPERX01DATA[3]; // rv 0 + assign PIPERX01DATA_in[4] = (PIPERX01DATA[4] !== 1'bz) && PIPERX01DATA[4]; // rv 0 + assign PIPERX01DATA_in[5] = (PIPERX01DATA[5] !== 1'bz) && PIPERX01DATA[5]; // rv 0 + assign PIPERX01DATA_in[6] = (PIPERX01DATA[6] !== 1'bz) && PIPERX01DATA[6]; // rv 0 + assign PIPERX01DATA_in[7] = (PIPERX01DATA[7] !== 1'bz) && PIPERX01DATA[7]; // rv 0 + assign PIPERX01DATA_in[8] = (PIPERX01DATA[8] !== 1'bz) && PIPERX01DATA[8]; // rv 0 + assign PIPERX01DATA_in[9] = (PIPERX01DATA[9] !== 1'bz) && PIPERX01DATA[9]; // rv 0 + assign PIPERX01ELECIDLE_in = (PIPERX01ELECIDLE === 1'bz) || PIPERX01ELECIDLE; // rv 1 + assign PIPERX01EQDONE_in = (PIPERX01EQDONE !== 1'bz) && PIPERX01EQDONE; // rv 0 + assign PIPERX01EQLPADAPTDONE_in = (PIPERX01EQLPADAPTDONE !== 1'bz) && PIPERX01EQLPADAPTDONE; // rv 0 + assign PIPERX01EQLPLFFSSEL_in = (PIPERX01EQLPLFFSSEL !== 1'bz) && PIPERX01EQLPLFFSSEL; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX01EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX01EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX01EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX01EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX01EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX01EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX01EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX01EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX01EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX01EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX01EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX01EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX01EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX01EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX01EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX01EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX01EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX01EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX01EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX01EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX01PHYSTATUS_in = (PIPERX01PHYSTATUS === 1'bz) || PIPERX01PHYSTATUS; // rv 1 + assign PIPERX01STARTBLOCK_in[0] = (PIPERX01STARTBLOCK[0] !== 1'bz) && PIPERX01STARTBLOCK[0]; // rv 0 + assign PIPERX01STARTBLOCK_in[1] = (PIPERX01STARTBLOCK[1] !== 1'bz) && PIPERX01STARTBLOCK[1]; // rv 0 + assign PIPERX01STATUS_in[0] = (PIPERX01STATUS[0] !== 1'bz) && PIPERX01STATUS[0]; // rv 0 + assign PIPERX01STATUS_in[1] = (PIPERX01STATUS[1] !== 1'bz) && PIPERX01STATUS[1]; // rv 0 + assign PIPERX01STATUS_in[2] = (PIPERX01STATUS[2] !== 1'bz) && PIPERX01STATUS[2]; // rv 0 + assign PIPERX01SYNCHEADER_in[0] = (PIPERX01SYNCHEADER[0] !== 1'bz) && PIPERX01SYNCHEADER[0]; // rv 0 + assign PIPERX01SYNCHEADER_in[1] = (PIPERX01SYNCHEADER[1] !== 1'bz) && PIPERX01SYNCHEADER[1]; // rv 0 + assign PIPERX01VALID_in = (PIPERX01VALID !== 1'bz) && PIPERX01VALID; // rv 0 + assign PIPERX02CHARISK_in[0] = (PIPERX02CHARISK[0] === 1'bz) || PIPERX02CHARISK[0]; // rv 1 + assign PIPERX02CHARISK_in[1] = (PIPERX02CHARISK[1] === 1'bz) || PIPERX02CHARISK[1]; // rv 1 + assign PIPERX02DATAVALID_in = (PIPERX02DATAVALID !== 1'bz) && PIPERX02DATAVALID; // rv 0 + assign PIPERX02DATA_in[0] = (PIPERX02DATA[0] !== 1'bz) && PIPERX02DATA[0]; // rv 0 + assign PIPERX02DATA_in[10] = (PIPERX02DATA[10] !== 1'bz) && PIPERX02DATA[10]; // rv 0 + assign PIPERX02DATA_in[11] = (PIPERX02DATA[11] !== 1'bz) && PIPERX02DATA[11]; // rv 0 + assign PIPERX02DATA_in[12] = (PIPERX02DATA[12] !== 1'bz) && PIPERX02DATA[12]; // rv 0 + assign PIPERX02DATA_in[13] = (PIPERX02DATA[13] !== 1'bz) && PIPERX02DATA[13]; // rv 0 + assign PIPERX02DATA_in[14] = (PIPERX02DATA[14] !== 1'bz) && PIPERX02DATA[14]; // rv 0 + assign PIPERX02DATA_in[15] = (PIPERX02DATA[15] !== 1'bz) && PIPERX02DATA[15]; // rv 0 + assign PIPERX02DATA_in[16] = (PIPERX02DATA[16] !== 1'bz) && PIPERX02DATA[16]; // rv 0 + assign PIPERX02DATA_in[17] = (PIPERX02DATA[17] !== 1'bz) && PIPERX02DATA[17]; // rv 0 + assign PIPERX02DATA_in[18] = (PIPERX02DATA[18] !== 1'bz) && PIPERX02DATA[18]; // rv 0 + assign PIPERX02DATA_in[19] = (PIPERX02DATA[19] !== 1'bz) && PIPERX02DATA[19]; // rv 0 + assign PIPERX02DATA_in[1] = (PIPERX02DATA[1] !== 1'bz) && PIPERX02DATA[1]; // rv 0 + assign PIPERX02DATA_in[20] = (PIPERX02DATA[20] !== 1'bz) && PIPERX02DATA[20]; // rv 0 + assign PIPERX02DATA_in[21] = (PIPERX02DATA[21] !== 1'bz) && PIPERX02DATA[21]; // rv 0 + assign PIPERX02DATA_in[22] = (PIPERX02DATA[22] !== 1'bz) && PIPERX02DATA[22]; // rv 0 + assign PIPERX02DATA_in[23] = (PIPERX02DATA[23] !== 1'bz) && PIPERX02DATA[23]; // rv 0 + assign PIPERX02DATA_in[24] = (PIPERX02DATA[24] !== 1'bz) && PIPERX02DATA[24]; // rv 0 + assign PIPERX02DATA_in[25] = (PIPERX02DATA[25] !== 1'bz) && PIPERX02DATA[25]; // rv 0 + assign PIPERX02DATA_in[26] = (PIPERX02DATA[26] !== 1'bz) && PIPERX02DATA[26]; // rv 0 + assign PIPERX02DATA_in[27] = (PIPERX02DATA[27] !== 1'bz) && PIPERX02DATA[27]; // rv 0 + assign PIPERX02DATA_in[28] = (PIPERX02DATA[28] !== 1'bz) && PIPERX02DATA[28]; // rv 0 + assign PIPERX02DATA_in[29] = (PIPERX02DATA[29] !== 1'bz) && PIPERX02DATA[29]; // rv 0 + assign PIPERX02DATA_in[2] = (PIPERX02DATA[2] !== 1'bz) && PIPERX02DATA[2]; // rv 0 + assign PIPERX02DATA_in[30] = (PIPERX02DATA[30] !== 1'bz) && PIPERX02DATA[30]; // rv 0 + assign PIPERX02DATA_in[31] = (PIPERX02DATA[31] !== 1'bz) && PIPERX02DATA[31]; // rv 0 + assign PIPERX02DATA_in[3] = (PIPERX02DATA[3] !== 1'bz) && PIPERX02DATA[3]; // rv 0 + assign PIPERX02DATA_in[4] = (PIPERX02DATA[4] !== 1'bz) && PIPERX02DATA[4]; // rv 0 + assign PIPERX02DATA_in[5] = (PIPERX02DATA[5] !== 1'bz) && PIPERX02DATA[5]; // rv 0 + assign PIPERX02DATA_in[6] = (PIPERX02DATA[6] !== 1'bz) && PIPERX02DATA[6]; // rv 0 + assign PIPERX02DATA_in[7] = (PIPERX02DATA[7] !== 1'bz) && PIPERX02DATA[7]; // rv 0 + assign PIPERX02DATA_in[8] = (PIPERX02DATA[8] !== 1'bz) && PIPERX02DATA[8]; // rv 0 + assign PIPERX02DATA_in[9] = (PIPERX02DATA[9] !== 1'bz) && PIPERX02DATA[9]; // rv 0 + assign PIPERX02ELECIDLE_in = (PIPERX02ELECIDLE === 1'bz) || PIPERX02ELECIDLE; // rv 1 + assign PIPERX02EQDONE_in = (PIPERX02EQDONE !== 1'bz) && PIPERX02EQDONE; // rv 0 + assign PIPERX02EQLPADAPTDONE_in = (PIPERX02EQLPADAPTDONE !== 1'bz) && PIPERX02EQLPADAPTDONE; // rv 0 + assign PIPERX02EQLPLFFSSEL_in = (PIPERX02EQLPLFFSSEL !== 1'bz) && PIPERX02EQLPLFFSSEL; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX02EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX02EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX02EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX02EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX02EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX02EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX02EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX02EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX02EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX02EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX02EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX02EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX02EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX02EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX02EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX02EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX02EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX02EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX02EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX02EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX02PHYSTATUS_in = (PIPERX02PHYSTATUS === 1'bz) || PIPERX02PHYSTATUS; // rv 1 + assign PIPERX02STARTBLOCK_in[0] = (PIPERX02STARTBLOCK[0] !== 1'bz) && PIPERX02STARTBLOCK[0]; // rv 0 + assign PIPERX02STARTBLOCK_in[1] = (PIPERX02STARTBLOCK[1] !== 1'bz) && PIPERX02STARTBLOCK[1]; // rv 0 + assign PIPERX02STATUS_in[0] = (PIPERX02STATUS[0] !== 1'bz) && PIPERX02STATUS[0]; // rv 0 + assign PIPERX02STATUS_in[1] = (PIPERX02STATUS[1] !== 1'bz) && PIPERX02STATUS[1]; // rv 0 + assign PIPERX02STATUS_in[2] = (PIPERX02STATUS[2] !== 1'bz) && PIPERX02STATUS[2]; // rv 0 + assign PIPERX02SYNCHEADER_in[0] = (PIPERX02SYNCHEADER[0] !== 1'bz) && PIPERX02SYNCHEADER[0]; // rv 0 + assign PIPERX02SYNCHEADER_in[1] = (PIPERX02SYNCHEADER[1] !== 1'bz) && PIPERX02SYNCHEADER[1]; // rv 0 + assign PIPERX02VALID_in = (PIPERX02VALID !== 1'bz) && PIPERX02VALID; // rv 0 + assign PIPERX03CHARISK_in[0] = (PIPERX03CHARISK[0] === 1'bz) || PIPERX03CHARISK[0]; // rv 1 + assign PIPERX03CHARISK_in[1] = (PIPERX03CHARISK[1] === 1'bz) || PIPERX03CHARISK[1]; // rv 1 + assign PIPERX03DATAVALID_in = (PIPERX03DATAVALID !== 1'bz) && PIPERX03DATAVALID; // rv 0 + assign PIPERX03DATA_in[0] = (PIPERX03DATA[0] !== 1'bz) && PIPERX03DATA[0]; // rv 0 + assign PIPERX03DATA_in[10] = (PIPERX03DATA[10] !== 1'bz) && PIPERX03DATA[10]; // rv 0 + assign PIPERX03DATA_in[11] = (PIPERX03DATA[11] !== 1'bz) && PIPERX03DATA[11]; // rv 0 + assign PIPERX03DATA_in[12] = (PIPERX03DATA[12] !== 1'bz) && PIPERX03DATA[12]; // rv 0 + assign PIPERX03DATA_in[13] = (PIPERX03DATA[13] !== 1'bz) && PIPERX03DATA[13]; // rv 0 + assign PIPERX03DATA_in[14] = (PIPERX03DATA[14] !== 1'bz) && PIPERX03DATA[14]; // rv 0 + assign PIPERX03DATA_in[15] = (PIPERX03DATA[15] !== 1'bz) && PIPERX03DATA[15]; // rv 0 + assign PIPERX03DATA_in[16] = (PIPERX03DATA[16] !== 1'bz) && PIPERX03DATA[16]; // rv 0 + assign PIPERX03DATA_in[17] = (PIPERX03DATA[17] !== 1'bz) && PIPERX03DATA[17]; // rv 0 + assign PIPERX03DATA_in[18] = (PIPERX03DATA[18] !== 1'bz) && PIPERX03DATA[18]; // rv 0 + assign PIPERX03DATA_in[19] = (PIPERX03DATA[19] !== 1'bz) && PIPERX03DATA[19]; // rv 0 + assign PIPERX03DATA_in[1] = (PIPERX03DATA[1] !== 1'bz) && PIPERX03DATA[1]; // rv 0 + assign PIPERX03DATA_in[20] = (PIPERX03DATA[20] !== 1'bz) && PIPERX03DATA[20]; // rv 0 + assign PIPERX03DATA_in[21] = (PIPERX03DATA[21] !== 1'bz) && PIPERX03DATA[21]; // rv 0 + assign PIPERX03DATA_in[22] = (PIPERX03DATA[22] !== 1'bz) && PIPERX03DATA[22]; // rv 0 + assign PIPERX03DATA_in[23] = (PIPERX03DATA[23] !== 1'bz) && PIPERX03DATA[23]; // rv 0 + assign PIPERX03DATA_in[24] = (PIPERX03DATA[24] !== 1'bz) && PIPERX03DATA[24]; // rv 0 + assign PIPERX03DATA_in[25] = (PIPERX03DATA[25] !== 1'bz) && PIPERX03DATA[25]; // rv 0 + assign PIPERX03DATA_in[26] = (PIPERX03DATA[26] !== 1'bz) && PIPERX03DATA[26]; // rv 0 + assign PIPERX03DATA_in[27] = (PIPERX03DATA[27] !== 1'bz) && PIPERX03DATA[27]; // rv 0 + assign PIPERX03DATA_in[28] = (PIPERX03DATA[28] !== 1'bz) && PIPERX03DATA[28]; // rv 0 + assign PIPERX03DATA_in[29] = (PIPERX03DATA[29] !== 1'bz) && PIPERX03DATA[29]; // rv 0 + assign PIPERX03DATA_in[2] = (PIPERX03DATA[2] !== 1'bz) && PIPERX03DATA[2]; // rv 0 + assign PIPERX03DATA_in[30] = (PIPERX03DATA[30] !== 1'bz) && PIPERX03DATA[30]; // rv 0 + assign PIPERX03DATA_in[31] = (PIPERX03DATA[31] !== 1'bz) && PIPERX03DATA[31]; // rv 0 + assign PIPERX03DATA_in[3] = (PIPERX03DATA[3] !== 1'bz) && PIPERX03DATA[3]; // rv 0 + assign PIPERX03DATA_in[4] = (PIPERX03DATA[4] !== 1'bz) && PIPERX03DATA[4]; // rv 0 + assign PIPERX03DATA_in[5] = (PIPERX03DATA[5] !== 1'bz) && PIPERX03DATA[5]; // rv 0 + assign PIPERX03DATA_in[6] = (PIPERX03DATA[6] !== 1'bz) && PIPERX03DATA[6]; // rv 0 + assign PIPERX03DATA_in[7] = (PIPERX03DATA[7] !== 1'bz) && PIPERX03DATA[7]; // rv 0 + assign PIPERX03DATA_in[8] = (PIPERX03DATA[8] !== 1'bz) && PIPERX03DATA[8]; // rv 0 + assign PIPERX03DATA_in[9] = (PIPERX03DATA[9] !== 1'bz) && PIPERX03DATA[9]; // rv 0 + assign PIPERX03ELECIDLE_in = (PIPERX03ELECIDLE === 1'bz) || PIPERX03ELECIDLE; // rv 1 + assign PIPERX03EQDONE_in = (PIPERX03EQDONE !== 1'bz) && PIPERX03EQDONE; // rv 0 + assign PIPERX03EQLPADAPTDONE_in = (PIPERX03EQLPADAPTDONE !== 1'bz) && PIPERX03EQLPADAPTDONE; // rv 0 + assign PIPERX03EQLPLFFSSEL_in = (PIPERX03EQLPLFFSSEL !== 1'bz) && PIPERX03EQLPLFFSSEL; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX03EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX03EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX03EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX03EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX03EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX03EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX03EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX03EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX03EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX03EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX03EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX03EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX03EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX03EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX03EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX03EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX03EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX03EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX03EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX03EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX03PHYSTATUS_in = (PIPERX03PHYSTATUS === 1'bz) || PIPERX03PHYSTATUS; // rv 1 + assign PIPERX03STARTBLOCK_in[0] = (PIPERX03STARTBLOCK[0] !== 1'bz) && PIPERX03STARTBLOCK[0]; // rv 0 + assign PIPERX03STARTBLOCK_in[1] = (PIPERX03STARTBLOCK[1] !== 1'bz) && PIPERX03STARTBLOCK[1]; // rv 0 + assign PIPERX03STATUS_in[0] = (PIPERX03STATUS[0] !== 1'bz) && PIPERX03STATUS[0]; // rv 0 + assign PIPERX03STATUS_in[1] = (PIPERX03STATUS[1] !== 1'bz) && PIPERX03STATUS[1]; // rv 0 + assign PIPERX03STATUS_in[2] = (PIPERX03STATUS[2] !== 1'bz) && PIPERX03STATUS[2]; // rv 0 + assign PIPERX03SYNCHEADER_in[0] = (PIPERX03SYNCHEADER[0] !== 1'bz) && PIPERX03SYNCHEADER[0]; // rv 0 + assign PIPERX03SYNCHEADER_in[1] = (PIPERX03SYNCHEADER[1] !== 1'bz) && PIPERX03SYNCHEADER[1]; // rv 0 + assign PIPERX03VALID_in = (PIPERX03VALID !== 1'bz) && PIPERX03VALID; // rv 0 + assign PIPERX04CHARISK_in[0] = (PIPERX04CHARISK[0] === 1'bz) || PIPERX04CHARISK[0]; // rv 1 + assign PIPERX04CHARISK_in[1] = (PIPERX04CHARISK[1] === 1'bz) || PIPERX04CHARISK[1]; // rv 1 + assign PIPERX04DATAVALID_in = (PIPERX04DATAVALID !== 1'bz) && PIPERX04DATAVALID; // rv 0 + assign PIPERX04DATA_in[0] = (PIPERX04DATA[0] !== 1'bz) && PIPERX04DATA[0]; // rv 0 + assign PIPERX04DATA_in[10] = (PIPERX04DATA[10] !== 1'bz) && PIPERX04DATA[10]; // rv 0 + assign PIPERX04DATA_in[11] = (PIPERX04DATA[11] !== 1'bz) && PIPERX04DATA[11]; // rv 0 + assign PIPERX04DATA_in[12] = (PIPERX04DATA[12] !== 1'bz) && PIPERX04DATA[12]; // rv 0 + assign PIPERX04DATA_in[13] = (PIPERX04DATA[13] !== 1'bz) && PIPERX04DATA[13]; // rv 0 + assign PIPERX04DATA_in[14] = (PIPERX04DATA[14] !== 1'bz) && PIPERX04DATA[14]; // rv 0 + assign PIPERX04DATA_in[15] = (PIPERX04DATA[15] !== 1'bz) && PIPERX04DATA[15]; // rv 0 + assign PIPERX04DATA_in[16] = (PIPERX04DATA[16] !== 1'bz) && PIPERX04DATA[16]; // rv 0 + assign PIPERX04DATA_in[17] = (PIPERX04DATA[17] !== 1'bz) && PIPERX04DATA[17]; // rv 0 + assign PIPERX04DATA_in[18] = (PIPERX04DATA[18] !== 1'bz) && PIPERX04DATA[18]; // rv 0 + assign PIPERX04DATA_in[19] = (PIPERX04DATA[19] !== 1'bz) && PIPERX04DATA[19]; // rv 0 + assign PIPERX04DATA_in[1] = (PIPERX04DATA[1] !== 1'bz) && PIPERX04DATA[1]; // rv 0 + assign PIPERX04DATA_in[20] = (PIPERX04DATA[20] !== 1'bz) && PIPERX04DATA[20]; // rv 0 + assign PIPERX04DATA_in[21] = (PIPERX04DATA[21] !== 1'bz) && PIPERX04DATA[21]; // rv 0 + assign PIPERX04DATA_in[22] = (PIPERX04DATA[22] !== 1'bz) && PIPERX04DATA[22]; // rv 0 + assign PIPERX04DATA_in[23] = (PIPERX04DATA[23] !== 1'bz) && PIPERX04DATA[23]; // rv 0 + assign PIPERX04DATA_in[24] = (PIPERX04DATA[24] !== 1'bz) && PIPERX04DATA[24]; // rv 0 + assign PIPERX04DATA_in[25] = (PIPERX04DATA[25] !== 1'bz) && PIPERX04DATA[25]; // rv 0 + assign PIPERX04DATA_in[26] = (PIPERX04DATA[26] !== 1'bz) && PIPERX04DATA[26]; // rv 0 + assign PIPERX04DATA_in[27] = (PIPERX04DATA[27] !== 1'bz) && PIPERX04DATA[27]; // rv 0 + assign PIPERX04DATA_in[28] = (PIPERX04DATA[28] !== 1'bz) && PIPERX04DATA[28]; // rv 0 + assign PIPERX04DATA_in[29] = (PIPERX04DATA[29] !== 1'bz) && PIPERX04DATA[29]; // rv 0 + assign PIPERX04DATA_in[2] = (PIPERX04DATA[2] !== 1'bz) && PIPERX04DATA[2]; // rv 0 + assign PIPERX04DATA_in[30] = (PIPERX04DATA[30] !== 1'bz) && PIPERX04DATA[30]; // rv 0 + assign PIPERX04DATA_in[31] = (PIPERX04DATA[31] !== 1'bz) && PIPERX04DATA[31]; // rv 0 + assign PIPERX04DATA_in[3] = (PIPERX04DATA[3] !== 1'bz) && PIPERX04DATA[3]; // rv 0 + assign PIPERX04DATA_in[4] = (PIPERX04DATA[4] !== 1'bz) && PIPERX04DATA[4]; // rv 0 + assign PIPERX04DATA_in[5] = (PIPERX04DATA[5] !== 1'bz) && PIPERX04DATA[5]; // rv 0 + assign PIPERX04DATA_in[6] = (PIPERX04DATA[6] !== 1'bz) && PIPERX04DATA[6]; // rv 0 + assign PIPERX04DATA_in[7] = (PIPERX04DATA[7] !== 1'bz) && PIPERX04DATA[7]; // rv 0 + assign PIPERX04DATA_in[8] = (PIPERX04DATA[8] !== 1'bz) && PIPERX04DATA[8]; // rv 0 + assign PIPERX04DATA_in[9] = (PIPERX04DATA[9] !== 1'bz) && PIPERX04DATA[9]; // rv 0 + assign PIPERX04ELECIDLE_in = (PIPERX04ELECIDLE === 1'bz) || PIPERX04ELECIDLE; // rv 1 + assign PIPERX04EQDONE_in = (PIPERX04EQDONE !== 1'bz) && PIPERX04EQDONE; // rv 0 + assign PIPERX04EQLPADAPTDONE_in = (PIPERX04EQLPADAPTDONE !== 1'bz) && PIPERX04EQLPADAPTDONE; // rv 0 + assign PIPERX04EQLPLFFSSEL_in = (PIPERX04EQLPLFFSSEL !== 1'bz) && PIPERX04EQLPLFFSSEL; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX04EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX04EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX04EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX04EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX04EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX04EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX04EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX04EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX04EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX04EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX04EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX04EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX04EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX04EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX04EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX04EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX04EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX04EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX04EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX04EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX04PHYSTATUS_in = (PIPERX04PHYSTATUS === 1'bz) || PIPERX04PHYSTATUS; // rv 1 + assign PIPERX04STARTBLOCK_in[0] = (PIPERX04STARTBLOCK[0] !== 1'bz) && PIPERX04STARTBLOCK[0]; // rv 0 + assign PIPERX04STARTBLOCK_in[1] = (PIPERX04STARTBLOCK[1] !== 1'bz) && PIPERX04STARTBLOCK[1]; // rv 0 + assign PIPERX04STATUS_in[0] = (PIPERX04STATUS[0] !== 1'bz) && PIPERX04STATUS[0]; // rv 0 + assign PIPERX04STATUS_in[1] = (PIPERX04STATUS[1] !== 1'bz) && PIPERX04STATUS[1]; // rv 0 + assign PIPERX04STATUS_in[2] = (PIPERX04STATUS[2] !== 1'bz) && PIPERX04STATUS[2]; // rv 0 + assign PIPERX04SYNCHEADER_in[0] = (PIPERX04SYNCHEADER[0] !== 1'bz) && PIPERX04SYNCHEADER[0]; // rv 0 + assign PIPERX04SYNCHEADER_in[1] = (PIPERX04SYNCHEADER[1] !== 1'bz) && PIPERX04SYNCHEADER[1]; // rv 0 + assign PIPERX04VALID_in = (PIPERX04VALID !== 1'bz) && PIPERX04VALID; // rv 0 + assign PIPERX05CHARISK_in[0] = (PIPERX05CHARISK[0] === 1'bz) || PIPERX05CHARISK[0]; // rv 1 + assign PIPERX05CHARISK_in[1] = (PIPERX05CHARISK[1] === 1'bz) || PIPERX05CHARISK[1]; // rv 1 + assign PIPERX05DATAVALID_in = (PIPERX05DATAVALID !== 1'bz) && PIPERX05DATAVALID; // rv 0 + assign PIPERX05DATA_in[0] = (PIPERX05DATA[0] !== 1'bz) && PIPERX05DATA[0]; // rv 0 + assign PIPERX05DATA_in[10] = (PIPERX05DATA[10] !== 1'bz) && PIPERX05DATA[10]; // rv 0 + assign PIPERX05DATA_in[11] = (PIPERX05DATA[11] !== 1'bz) && PIPERX05DATA[11]; // rv 0 + assign PIPERX05DATA_in[12] = (PIPERX05DATA[12] !== 1'bz) && PIPERX05DATA[12]; // rv 0 + assign PIPERX05DATA_in[13] = (PIPERX05DATA[13] !== 1'bz) && PIPERX05DATA[13]; // rv 0 + assign PIPERX05DATA_in[14] = (PIPERX05DATA[14] !== 1'bz) && PIPERX05DATA[14]; // rv 0 + assign PIPERX05DATA_in[15] = (PIPERX05DATA[15] !== 1'bz) && PIPERX05DATA[15]; // rv 0 + assign PIPERX05DATA_in[16] = (PIPERX05DATA[16] !== 1'bz) && PIPERX05DATA[16]; // rv 0 + assign PIPERX05DATA_in[17] = (PIPERX05DATA[17] !== 1'bz) && PIPERX05DATA[17]; // rv 0 + assign PIPERX05DATA_in[18] = (PIPERX05DATA[18] !== 1'bz) && PIPERX05DATA[18]; // rv 0 + assign PIPERX05DATA_in[19] = (PIPERX05DATA[19] !== 1'bz) && PIPERX05DATA[19]; // rv 0 + assign PIPERX05DATA_in[1] = (PIPERX05DATA[1] !== 1'bz) && PIPERX05DATA[1]; // rv 0 + assign PIPERX05DATA_in[20] = (PIPERX05DATA[20] !== 1'bz) && PIPERX05DATA[20]; // rv 0 + assign PIPERX05DATA_in[21] = (PIPERX05DATA[21] !== 1'bz) && PIPERX05DATA[21]; // rv 0 + assign PIPERX05DATA_in[22] = (PIPERX05DATA[22] !== 1'bz) && PIPERX05DATA[22]; // rv 0 + assign PIPERX05DATA_in[23] = (PIPERX05DATA[23] !== 1'bz) && PIPERX05DATA[23]; // rv 0 + assign PIPERX05DATA_in[24] = (PIPERX05DATA[24] !== 1'bz) && PIPERX05DATA[24]; // rv 0 + assign PIPERX05DATA_in[25] = (PIPERX05DATA[25] !== 1'bz) && PIPERX05DATA[25]; // rv 0 + assign PIPERX05DATA_in[26] = (PIPERX05DATA[26] !== 1'bz) && PIPERX05DATA[26]; // rv 0 + assign PIPERX05DATA_in[27] = (PIPERX05DATA[27] !== 1'bz) && PIPERX05DATA[27]; // rv 0 + assign PIPERX05DATA_in[28] = (PIPERX05DATA[28] !== 1'bz) && PIPERX05DATA[28]; // rv 0 + assign PIPERX05DATA_in[29] = (PIPERX05DATA[29] !== 1'bz) && PIPERX05DATA[29]; // rv 0 + assign PIPERX05DATA_in[2] = (PIPERX05DATA[2] !== 1'bz) && PIPERX05DATA[2]; // rv 0 + assign PIPERX05DATA_in[30] = (PIPERX05DATA[30] !== 1'bz) && PIPERX05DATA[30]; // rv 0 + assign PIPERX05DATA_in[31] = (PIPERX05DATA[31] !== 1'bz) && PIPERX05DATA[31]; // rv 0 + assign PIPERX05DATA_in[3] = (PIPERX05DATA[3] !== 1'bz) && PIPERX05DATA[3]; // rv 0 + assign PIPERX05DATA_in[4] = (PIPERX05DATA[4] !== 1'bz) && PIPERX05DATA[4]; // rv 0 + assign PIPERX05DATA_in[5] = (PIPERX05DATA[5] !== 1'bz) && PIPERX05DATA[5]; // rv 0 + assign PIPERX05DATA_in[6] = (PIPERX05DATA[6] !== 1'bz) && PIPERX05DATA[6]; // rv 0 + assign PIPERX05DATA_in[7] = (PIPERX05DATA[7] !== 1'bz) && PIPERX05DATA[7]; // rv 0 + assign PIPERX05DATA_in[8] = (PIPERX05DATA[8] !== 1'bz) && PIPERX05DATA[8]; // rv 0 + assign PIPERX05DATA_in[9] = (PIPERX05DATA[9] !== 1'bz) && PIPERX05DATA[9]; // rv 0 + assign PIPERX05ELECIDLE_in = (PIPERX05ELECIDLE === 1'bz) || PIPERX05ELECIDLE; // rv 1 + assign PIPERX05EQDONE_in = (PIPERX05EQDONE !== 1'bz) && PIPERX05EQDONE; // rv 0 + assign PIPERX05EQLPADAPTDONE_in = (PIPERX05EQLPADAPTDONE !== 1'bz) && PIPERX05EQLPADAPTDONE; // rv 0 + assign PIPERX05EQLPLFFSSEL_in = (PIPERX05EQLPLFFSSEL !== 1'bz) && PIPERX05EQLPLFFSSEL; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX05EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX05EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX05EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX05EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX05EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX05EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX05EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX05EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX05EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX05EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX05EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX05EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX05EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX05EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX05EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX05EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX05EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX05EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX05EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX05EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX05PHYSTATUS_in = (PIPERX05PHYSTATUS === 1'bz) || PIPERX05PHYSTATUS; // rv 1 + assign PIPERX05STARTBLOCK_in[0] = (PIPERX05STARTBLOCK[0] !== 1'bz) && PIPERX05STARTBLOCK[0]; // rv 0 + assign PIPERX05STARTBLOCK_in[1] = (PIPERX05STARTBLOCK[1] !== 1'bz) && PIPERX05STARTBLOCK[1]; // rv 0 + assign PIPERX05STATUS_in[0] = (PIPERX05STATUS[0] !== 1'bz) && PIPERX05STATUS[0]; // rv 0 + assign PIPERX05STATUS_in[1] = (PIPERX05STATUS[1] !== 1'bz) && PIPERX05STATUS[1]; // rv 0 + assign PIPERX05STATUS_in[2] = (PIPERX05STATUS[2] !== 1'bz) && PIPERX05STATUS[2]; // rv 0 + assign PIPERX05SYNCHEADER_in[0] = (PIPERX05SYNCHEADER[0] !== 1'bz) && PIPERX05SYNCHEADER[0]; // rv 0 + assign PIPERX05SYNCHEADER_in[1] = (PIPERX05SYNCHEADER[1] !== 1'bz) && PIPERX05SYNCHEADER[1]; // rv 0 + assign PIPERX05VALID_in = (PIPERX05VALID !== 1'bz) && PIPERX05VALID; // rv 0 + assign PIPERX06CHARISK_in[0] = (PIPERX06CHARISK[0] === 1'bz) || PIPERX06CHARISK[0]; // rv 1 + assign PIPERX06CHARISK_in[1] = (PIPERX06CHARISK[1] === 1'bz) || PIPERX06CHARISK[1]; // rv 1 + assign PIPERX06DATAVALID_in = (PIPERX06DATAVALID !== 1'bz) && PIPERX06DATAVALID; // rv 0 + assign PIPERX06DATA_in[0] = (PIPERX06DATA[0] !== 1'bz) && PIPERX06DATA[0]; // rv 0 + assign PIPERX06DATA_in[10] = (PIPERX06DATA[10] !== 1'bz) && PIPERX06DATA[10]; // rv 0 + assign PIPERX06DATA_in[11] = (PIPERX06DATA[11] !== 1'bz) && PIPERX06DATA[11]; // rv 0 + assign PIPERX06DATA_in[12] = (PIPERX06DATA[12] !== 1'bz) && PIPERX06DATA[12]; // rv 0 + assign PIPERX06DATA_in[13] = (PIPERX06DATA[13] !== 1'bz) && PIPERX06DATA[13]; // rv 0 + assign PIPERX06DATA_in[14] = (PIPERX06DATA[14] !== 1'bz) && PIPERX06DATA[14]; // rv 0 + assign PIPERX06DATA_in[15] = (PIPERX06DATA[15] !== 1'bz) && PIPERX06DATA[15]; // rv 0 + assign PIPERX06DATA_in[16] = (PIPERX06DATA[16] !== 1'bz) && PIPERX06DATA[16]; // rv 0 + assign PIPERX06DATA_in[17] = (PIPERX06DATA[17] !== 1'bz) && PIPERX06DATA[17]; // rv 0 + assign PIPERX06DATA_in[18] = (PIPERX06DATA[18] !== 1'bz) && PIPERX06DATA[18]; // rv 0 + assign PIPERX06DATA_in[19] = (PIPERX06DATA[19] !== 1'bz) && PIPERX06DATA[19]; // rv 0 + assign PIPERX06DATA_in[1] = (PIPERX06DATA[1] !== 1'bz) && PIPERX06DATA[1]; // rv 0 + assign PIPERX06DATA_in[20] = (PIPERX06DATA[20] !== 1'bz) && PIPERX06DATA[20]; // rv 0 + assign PIPERX06DATA_in[21] = (PIPERX06DATA[21] !== 1'bz) && PIPERX06DATA[21]; // rv 0 + assign PIPERX06DATA_in[22] = (PIPERX06DATA[22] !== 1'bz) && PIPERX06DATA[22]; // rv 0 + assign PIPERX06DATA_in[23] = (PIPERX06DATA[23] !== 1'bz) && PIPERX06DATA[23]; // rv 0 + assign PIPERX06DATA_in[24] = (PIPERX06DATA[24] !== 1'bz) && PIPERX06DATA[24]; // rv 0 + assign PIPERX06DATA_in[25] = (PIPERX06DATA[25] !== 1'bz) && PIPERX06DATA[25]; // rv 0 + assign PIPERX06DATA_in[26] = (PIPERX06DATA[26] !== 1'bz) && PIPERX06DATA[26]; // rv 0 + assign PIPERX06DATA_in[27] = (PIPERX06DATA[27] !== 1'bz) && PIPERX06DATA[27]; // rv 0 + assign PIPERX06DATA_in[28] = (PIPERX06DATA[28] !== 1'bz) && PIPERX06DATA[28]; // rv 0 + assign PIPERX06DATA_in[29] = (PIPERX06DATA[29] !== 1'bz) && PIPERX06DATA[29]; // rv 0 + assign PIPERX06DATA_in[2] = (PIPERX06DATA[2] !== 1'bz) && PIPERX06DATA[2]; // rv 0 + assign PIPERX06DATA_in[30] = (PIPERX06DATA[30] !== 1'bz) && PIPERX06DATA[30]; // rv 0 + assign PIPERX06DATA_in[31] = (PIPERX06DATA[31] !== 1'bz) && PIPERX06DATA[31]; // rv 0 + assign PIPERX06DATA_in[3] = (PIPERX06DATA[3] !== 1'bz) && PIPERX06DATA[3]; // rv 0 + assign PIPERX06DATA_in[4] = (PIPERX06DATA[4] !== 1'bz) && PIPERX06DATA[4]; // rv 0 + assign PIPERX06DATA_in[5] = (PIPERX06DATA[5] !== 1'bz) && PIPERX06DATA[5]; // rv 0 + assign PIPERX06DATA_in[6] = (PIPERX06DATA[6] !== 1'bz) && PIPERX06DATA[6]; // rv 0 + assign PIPERX06DATA_in[7] = (PIPERX06DATA[7] !== 1'bz) && PIPERX06DATA[7]; // rv 0 + assign PIPERX06DATA_in[8] = (PIPERX06DATA[8] !== 1'bz) && PIPERX06DATA[8]; // rv 0 + assign PIPERX06DATA_in[9] = (PIPERX06DATA[9] !== 1'bz) && PIPERX06DATA[9]; // rv 0 + assign PIPERX06ELECIDLE_in = (PIPERX06ELECIDLE === 1'bz) || PIPERX06ELECIDLE; // rv 1 + assign PIPERX06EQDONE_in = (PIPERX06EQDONE !== 1'bz) && PIPERX06EQDONE; // rv 0 + assign PIPERX06EQLPADAPTDONE_in = (PIPERX06EQLPADAPTDONE !== 1'bz) && PIPERX06EQLPADAPTDONE; // rv 0 + assign PIPERX06EQLPLFFSSEL_in = (PIPERX06EQLPLFFSSEL !== 1'bz) && PIPERX06EQLPLFFSSEL; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX06EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX06EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX06EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX06EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX06EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX06EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX06EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX06EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX06EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX06EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX06EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX06EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX06EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX06EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX06EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX06EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX06EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX06EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX06EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX06EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX06PHYSTATUS_in = (PIPERX06PHYSTATUS === 1'bz) || PIPERX06PHYSTATUS; // rv 1 + assign PIPERX06STARTBLOCK_in[0] = (PIPERX06STARTBLOCK[0] !== 1'bz) && PIPERX06STARTBLOCK[0]; // rv 0 + assign PIPERX06STARTBLOCK_in[1] = (PIPERX06STARTBLOCK[1] !== 1'bz) && PIPERX06STARTBLOCK[1]; // rv 0 + assign PIPERX06STATUS_in[0] = (PIPERX06STATUS[0] !== 1'bz) && PIPERX06STATUS[0]; // rv 0 + assign PIPERX06STATUS_in[1] = (PIPERX06STATUS[1] !== 1'bz) && PIPERX06STATUS[1]; // rv 0 + assign PIPERX06STATUS_in[2] = (PIPERX06STATUS[2] !== 1'bz) && PIPERX06STATUS[2]; // rv 0 + assign PIPERX06SYNCHEADER_in[0] = (PIPERX06SYNCHEADER[0] !== 1'bz) && PIPERX06SYNCHEADER[0]; // rv 0 + assign PIPERX06SYNCHEADER_in[1] = (PIPERX06SYNCHEADER[1] !== 1'bz) && PIPERX06SYNCHEADER[1]; // rv 0 + assign PIPERX06VALID_in = (PIPERX06VALID !== 1'bz) && PIPERX06VALID; // rv 0 + assign PIPERX07CHARISK_in[0] = (PIPERX07CHARISK[0] === 1'bz) || PIPERX07CHARISK[0]; // rv 1 + assign PIPERX07CHARISK_in[1] = (PIPERX07CHARISK[1] === 1'bz) || PIPERX07CHARISK[1]; // rv 1 + assign PIPERX07DATAVALID_in = (PIPERX07DATAVALID !== 1'bz) && PIPERX07DATAVALID; // rv 0 + assign PIPERX07DATA_in[0] = (PIPERX07DATA[0] !== 1'bz) && PIPERX07DATA[0]; // rv 0 + assign PIPERX07DATA_in[10] = (PIPERX07DATA[10] !== 1'bz) && PIPERX07DATA[10]; // rv 0 + assign PIPERX07DATA_in[11] = (PIPERX07DATA[11] !== 1'bz) && PIPERX07DATA[11]; // rv 0 + assign PIPERX07DATA_in[12] = (PIPERX07DATA[12] !== 1'bz) && PIPERX07DATA[12]; // rv 0 + assign PIPERX07DATA_in[13] = (PIPERX07DATA[13] !== 1'bz) && PIPERX07DATA[13]; // rv 0 + assign PIPERX07DATA_in[14] = (PIPERX07DATA[14] !== 1'bz) && PIPERX07DATA[14]; // rv 0 + assign PIPERX07DATA_in[15] = (PIPERX07DATA[15] !== 1'bz) && PIPERX07DATA[15]; // rv 0 + assign PIPERX07DATA_in[16] = (PIPERX07DATA[16] !== 1'bz) && PIPERX07DATA[16]; // rv 0 + assign PIPERX07DATA_in[17] = (PIPERX07DATA[17] !== 1'bz) && PIPERX07DATA[17]; // rv 0 + assign PIPERX07DATA_in[18] = (PIPERX07DATA[18] !== 1'bz) && PIPERX07DATA[18]; // rv 0 + assign PIPERX07DATA_in[19] = (PIPERX07DATA[19] !== 1'bz) && PIPERX07DATA[19]; // rv 0 + assign PIPERX07DATA_in[1] = (PIPERX07DATA[1] !== 1'bz) && PIPERX07DATA[1]; // rv 0 + assign PIPERX07DATA_in[20] = (PIPERX07DATA[20] !== 1'bz) && PIPERX07DATA[20]; // rv 0 + assign PIPERX07DATA_in[21] = (PIPERX07DATA[21] !== 1'bz) && PIPERX07DATA[21]; // rv 0 + assign PIPERX07DATA_in[22] = (PIPERX07DATA[22] !== 1'bz) && PIPERX07DATA[22]; // rv 0 + assign PIPERX07DATA_in[23] = (PIPERX07DATA[23] !== 1'bz) && PIPERX07DATA[23]; // rv 0 + assign PIPERX07DATA_in[24] = (PIPERX07DATA[24] !== 1'bz) && PIPERX07DATA[24]; // rv 0 + assign PIPERX07DATA_in[25] = (PIPERX07DATA[25] !== 1'bz) && PIPERX07DATA[25]; // rv 0 + assign PIPERX07DATA_in[26] = (PIPERX07DATA[26] !== 1'bz) && PIPERX07DATA[26]; // rv 0 + assign PIPERX07DATA_in[27] = (PIPERX07DATA[27] !== 1'bz) && PIPERX07DATA[27]; // rv 0 + assign PIPERX07DATA_in[28] = (PIPERX07DATA[28] !== 1'bz) && PIPERX07DATA[28]; // rv 0 + assign PIPERX07DATA_in[29] = (PIPERX07DATA[29] !== 1'bz) && PIPERX07DATA[29]; // rv 0 + assign PIPERX07DATA_in[2] = (PIPERX07DATA[2] !== 1'bz) && PIPERX07DATA[2]; // rv 0 + assign PIPERX07DATA_in[30] = (PIPERX07DATA[30] !== 1'bz) && PIPERX07DATA[30]; // rv 0 + assign PIPERX07DATA_in[31] = (PIPERX07DATA[31] !== 1'bz) && PIPERX07DATA[31]; // rv 0 + assign PIPERX07DATA_in[3] = (PIPERX07DATA[3] !== 1'bz) && PIPERX07DATA[3]; // rv 0 + assign PIPERX07DATA_in[4] = (PIPERX07DATA[4] !== 1'bz) && PIPERX07DATA[4]; // rv 0 + assign PIPERX07DATA_in[5] = (PIPERX07DATA[5] !== 1'bz) && PIPERX07DATA[5]; // rv 0 + assign PIPERX07DATA_in[6] = (PIPERX07DATA[6] !== 1'bz) && PIPERX07DATA[6]; // rv 0 + assign PIPERX07DATA_in[7] = (PIPERX07DATA[7] !== 1'bz) && PIPERX07DATA[7]; // rv 0 + assign PIPERX07DATA_in[8] = (PIPERX07DATA[8] !== 1'bz) && PIPERX07DATA[8]; // rv 0 + assign PIPERX07DATA_in[9] = (PIPERX07DATA[9] !== 1'bz) && PIPERX07DATA[9]; // rv 0 + assign PIPERX07ELECIDLE_in = (PIPERX07ELECIDLE === 1'bz) || PIPERX07ELECIDLE; // rv 1 + assign PIPERX07EQDONE_in = (PIPERX07EQDONE !== 1'bz) && PIPERX07EQDONE; // rv 0 + assign PIPERX07EQLPADAPTDONE_in = (PIPERX07EQLPADAPTDONE !== 1'bz) && PIPERX07EQLPADAPTDONE; // rv 0 + assign PIPERX07EQLPLFFSSEL_in = (PIPERX07EQLPLFFSSEL !== 1'bz) && PIPERX07EQLPLFFSSEL; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX07EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX07EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX07EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX07EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX07EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX07EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX07EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX07EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX07EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX07EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX07EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX07EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX07EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX07EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX07EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX07EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX07EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX07EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX07EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX07EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX07PHYSTATUS_in = (PIPERX07PHYSTATUS === 1'bz) || PIPERX07PHYSTATUS; // rv 1 + assign PIPERX07STARTBLOCK_in[0] = (PIPERX07STARTBLOCK[0] !== 1'bz) && PIPERX07STARTBLOCK[0]; // rv 0 + assign PIPERX07STARTBLOCK_in[1] = (PIPERX07STARTBLOCK[1] !== 1'bz) && PIPERX07STARTBLOCK[1]; // rv 0 + assign PIPERX07STATUS_in[0] = (PIPERX07STATUS[0] !== 1'bz) && PIPERX07STATUS[0]; // rv 0 + assign PIPERX07STATUS_in[1] = (PIPERX07STATUS[1] !== 1'bz) && PIPERX07STATUS[1]; // rv 0 + assign PIPERX07STATUS_in[2] = (PIPERX07STATUS[2] !== 1'bz) && PIPERX07STATUS[2]; // rv 0 + assign PIPERX07SYNCHEADER_in[0] = (PIPERX07SYNCHEADER[0] !== 1'bz) && PIPERX07SYNCHEADER[0]; // rv 0 + assign PIPERX07SYNCHEADER_in[1] = (PIPERX07SYNCHEADER[1] !== 1'bz) && PIPERX07SYNCHEADER[1]; // rv 0 + assign PIPERX07VALID_in = (PIPERX07VALID !== 1'bz) && PIPERX07VALID; // rv 0 + assign PIPERX08CHARISK_in[0] = (PIPERX08CHARISK[0] === 1'bz) || PIPERX08CHARISK[0]; // rv 1 + assign PIPERX08CHARISK_in[1] = (PIPERX08CHARISK[1] === 1'bz) || PIPERX08CHARISK[1]; // rv 1 + assign PIPERX08DATAVALID_in = (PIPERX08DATAVALID !== 1'bz) && PIPERX08DATAVALID; // rv 0 + assign PIPERX08DATA_in[0] = (PIPERX08DATA[0] !== 1'bz) && PIPERX08DATA[0]; // rv 0 + assign PIPERX08DATA_in[10] = (PIPERX08DATA[10] !== 1'bz) && PIPERX08DATA[10]; // rv 0 + assign PIPERX08DATA_in[11] = (PIPERX08DATA[11] !== 1'bz) && PIPERX08DATA[11]; // rv 0 + assign PIPERX08DATA_in[12] = (PIPERX08DATA[12] !== 1'bz) && PIPERX08DATA[12]; // rv 0 + assign PIPERX08DATA_in[13] = (PIPERX08DATA[13] !== 1'bz) && PIPERX08DATA[13]; // rv 0 + assign PIPERX08DATA_in[14] = (PIPERX08DATA[14] !== 1'bz) && PIPERX08DATA[14]; // rv 0 + assign PIPERX08DATA_in[15] = (PIPERX08DATA[15] !== 1'bz) && PIPERX08DATA[15]; // rv 0 + assign PIPERX08DATA_in[16] = (PIPERX08DATA[16] !== 1'bz) && PIPERX08DATA[16]; // rv 0 + assign PIPERX08DATA_in[17] = (PIPERX08DATA[17] !== 1'bz) && PIPERX08DATA[17]; // rv 0 + assign PIPERX08DATA_in[18] = (PIPERX08DATA[18] !== 1'bz) && PIPERX08DATA[18]; // rv 0 + assign PIPERX08DATA_in[19] = (PIPERX08DATA[19] !== 1'bz) && PIPERX08DATA[19]; // rv 0 + assign PIPERX08DATA_in[1] = (PIPERX08DATA[1] !== 1'bz) && PIPERX08DATA[1]; // rv 0 + assign PIPERX08DATA_in[20] = (PIPERX08DATA[20] !== 1'bz) && PIPERX08DATA[20]; // rv 0 + assign PIPERX08DATA_in[21] = (PIPERX08DATA[21] !== 1'bz) && PIPERX08DATA[21]; // rv 0 + assign PIPERX08DATA_in[22] = (PIPERX08DATA[22] !== 1'bz) && PIPERX08DATA[22]; // rv 0 + assign PIPERX08DATA_in[23] = (PIPERX08DATA[23] !== 1'bz) && PIPERX08DATA[23]; // rv 0 + assign PIPERX08DATA_in[24] = (PIPERX08DATA[24] !== 1'bz) && PIPERX08DATA[24]; // rv 0 + assign PIPERX08DATA_in[25] = (PIPERX08DATA[25] !== 1'bz) && PIPERX08DATA[25]; // rv 0 + assign PIPERX08DATA_in[26] = (PIPERX08DATA[26] !== 1'bz) && PIPERX08DATA[26]; // rv 0 + assign PIPERX08DATA_in[27] = (PIPERX08DATA[27] !== 1'bz) && PIPERX08DATA[27]; // rv 0 + assign PIPERX08DATA_in[28] = (PIPERX08DATA[28] !== 1'bz) && PIPERX08DATA[28]; // rv 0 + assign PIPERX08DATA_in[29] = (PIPERX08DATA[29] !== 1'bz) && PIPERX08DATA[29]; // rv 0 + assign PIPERX08DATA_in[2] = (PIPERX08DATA[2] !== 1'bz) && PIPERX08DATA[2]; // rv 0 + assign PIPERX08DATA_in[30] = (PIPERX08DATA[30] !== 1'bz) && PIPERX08DATA[30]; // rv 0 + assign PIPERX08DATA_in[31] = (PIPERX08DATA[31] !== 1'bz) && PIPERX08DATA[31]; // rv 0 + assign PIPERX08DATA_in[3] = (PIPERX08DATA[3] !== 1'bz) && PIPERX08DATA[3]; // rv 0 + assign PIPERX08DATA_in[4] = (PIPERX08DATA[4] !== 1'bz) && PIPERX08DATA[4]; // rv 0 + assign PIPERX08DATA_in[5] = (PIPERX08DATA[5] !== 1'bz) && PIPERX08DATA[5]; // rv 0 + assign PIPERX08DATA_in[6] = (PIPERX08DATA[6] !== 1'bz) && PIPERX08DATA[6]; // rv 0 + assign PIPERX08DATA_in[7] = (PIPERX08DATA[7] !== 1'bz) && PIPERX08DATA[7]; // rv 0 + assign PIPERX08DATA_in[8] = (PIPERX08DATA[8] !== 1'bz) && PIPERX08DATA[8]; // rv 0 + assign PIPERX08DATA_in[9] = (PIPERX08DATA[9] !== 1'bz) && PIPERX08DATA[9]; // rv 0 + assign PIPERX08ELECIDLE_in = (PIPERX08ELECIDLE === 1'bz) || PIPERX08ELECIDLE; // rv 1 + assign PIPERX08EQDONE_in = (PIPERX08EQDONE !== 1'bz) && PIPERX08EQDONE; // rv 0 + assign PIPERX08EQLPADAPTDONE_in = (PIPERX08EQLPADAPTDONE !== 1'bz) && PIPERX08EQLPADAPTDONE; // rv 0 + assign PIPERX08EQLPLFFSSEL_in = (PIPERX08EQLPLFFSSEL !== 1'bz) && PIPERX08EQLPLFFSSEL; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX08EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX08EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX08EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX08EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX08EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX08EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX08EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX08EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX08EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX08EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX08EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX08EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX08EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX08EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX08EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX08EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX08EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX08EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX08EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX08EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX08PHYSTATUS_in = (PIPERX08PHYSTATUS === 1'bz) || PIPERX08PHYSTATUS; // rv 1 + assign PIPERX08STARTBLOCK_in[0] = (PIPERX08STARTBLOCK[0] !== 1'bz) && PIPERX08STARTBLOCK[0]; // rv 0 + assign PIPERX08STARTBLOCK_in[1] = (PIPERX08STARTBLOCK[1] !== 1'bz) && PIPERX08STARTBLOCK[1]; // rv 0 + assign PIPERX08STATUS_in[0] = (PIPERX08STATUS[0] !== 1'bz) && PIPERX08STATUS[0]; // rv 0 + assign PIPERX08STATUS_in[1] = (PIPERX08STATUS[1] !== 1'bz) && PIPERX08STATUS[1]; // rv 0 + assign PIPERX08STATUS_in[2] = (PIPERX08STATUS[2] !== 1'bz) && PIPERX08STATUS[2]; // rv 0 + assign PIPERX08SYNCHEADER_in[0] = (PIPERX08SYNCHEADER[0] !== 1'bz) && PIPERX08SYNCHEADER[0]; // rv 0 + assign PIPERX08SYNCHEADER_in[1] = (PIPERX08SYNCHEADER[1] !== 1'bz) && PIPERX08SYNCHEADER[1]; // rv 0 + assign PIPERX08VALID_in = (PIPERX08VALID !== 1'bz) && PIPERX08VALID; // rv 0 + assign PIPERX09CHARISK_in[0] = (PIPERX09CHARISK[0] === 1'bz) || PIPERX09CHARISK[0]; // rv 1 + assign PIPERX09CHARISK_in[1] = (PIPERX09CHARISK[1] === 1'bz) || PIPERX09CHARISK[1]; // rv 1 + assign PIPERX09DATAVALID_in = (PIPERX09DATAVALID !== 1'bz) && PIPERX09DATAVALID; // rv 0 + assign PIPERX09DATA_in[0] = (PIPERX09DATA[0] !== 1'bz) && PIPERX09DATA[0]; // rv 0 + assign PIPERX09DATA_in[10] = (PIPERX09DATA[10] !== 1'bz) && PIPERX09DATA[10]; // rv 0 + assign PIPERX09DATA_in[11] = (PIPERX09DATA[11] !== 1'bz) && PIPERX09DATA[11]; // rv 0 + assign PIPERX09DATA_in[12] = (PIPERX09DATA[12] !== 1'bz) && PIPERX09DATA[12]; // rv 0 + assign PIPERX09DATA_in[13] = (PIPERX09DATA[13] !== 1'bz) && PIPERX09DATA[13]; // rv 0 + assign PIPERX09DATA_in[14] = (PIPERX09DATA[14] !== 1'bz) && PIPERX09DATA[14]; // rv 0 + assign PIPERX09DATA_in[15] = (PIPERX09DATA[15] !== 1'bz) && PIPERX09DATA[15]; // rv 0 + assign PIPERX09DATA_in[16] = (PIPERX09DATA[16] !== 1'bz) && PIPERX09DATA[16]; // rv 0 + assign PIPERX09DATA_in[17] = (PIPERX09DATA[17] !== 1'bz) && PIPERX09DATA[17]; // rv 0 + assign PIPERX09DATA_in[18] = (PIPERX09DATA[18] !== 1'bz) && PIPERX09DATA[18]; // rv 0 + assign PIPERX09DATA_in[19] = (PIPERX09DATA[19] !== 1'bz) && PIPERX09DATA[19]; // rv 0 + assign PIPERX09DATA_in[1] = (PIPERX09DATA[1] !== 1'bz) && PIPERX09DATA[1]; // rv 0 + assign PIPERX09DATA_in[20] = (PIPERX09DATA[20] !== 1'bz) && PIPERX09DATA[20]; // rv 0 + assign PIPERX09DATA_in[21] = (PIPERX09DATA[21] !== 1'bz) && PIPERX09DATA[21]; // rv 0 + assign PIPERX09DATA_in[22] = (PIPERX09DATA[22] !== 1'bz) && PIPERX09DATA[22]; // rv 0 + assign PIPERX09DATA_in[23] = (PIPERX09DATA[23] !== 1'bz) && PIPERX09DATA[23]; // rv 0 + assign PIPERX09DATA_in[24] = (PIPERX09DATA[24] !== 1'bz) && PIPERX09DATA[24]; // rv 0 + assign PIPERX09DATA_in[25] = (PIPERX09DATA[25] !== 1'bz) && PIPERX09DATA[25]; // rv 0 + assign PIPERX09DATA_in[26] = (PIPERX09DATA[26] !== 1'bz) && PIPERX09DATA[26]; // rv 0 + assign PIPERX09DATA_in[27] = (PIPERX09DATA[27] !== 1'bz) && PIPERX09DATA[27]; // rv 0 + assign PIPERX09DATA_in[28] = (PIPERX09DATA[28] !== 1'bz) && PIPERX09DATA[28]; // rv 0 + assign PIPERX09DATA_in[29] = (PIPERX09DATA[29] !== 1'bz) && PIPERX09DATA[29]; // rv 0 + assign PIPERX09DATA_in[2] = (PIPERX09DATA[2] !== 1'bz) && PIPERX09DATA[2]; // rv 0 + assign PIPERX09DATA_in[30] = (PIPERX09DATA[30] !== 1'bz) && PIPERX09DATA[30]; // rv 0 + assign PIPERX09DATA_in[31] = (PIPERX09DATA[31] !== 1'bz) && PIPERX09DATA[31]; // rv 0 + assign PIPERX09DATA_in[3] = (PIPERX09DATA[3] !== 1'bz) && PIPERX09DATA[3]; // rv 0 + assign PIPERX09DATA_in[4] = (PIPERX09DATA[4] !== 1'bz) && PIPERX09DATA[4]; // rv 0 + assign PIPERX09DATA_in[5] = (PIPERX09DATA[5] !== 1'bz) && PIPERX09DATA[5]; // rv 0 + assign PIPERX09DATA_in[6] = (PIPERX09DATA[6] !== 1'bz) && PIPERX09DATA[6]; // rv 0 + assign PIPERX09DATA_in[7] = (PIPERX09DATA[7] !== 1'bz) && PIPERX09DATA[7]; // rv 0 + assign PIPERX09DATA_in[8] = (PIPERX09DATA[8] !== 1'bz) && PIPERX09DATA[8]; // rv 0 + assign PIPERX09DATA_in[9] = (PIPERX09DATA[9] !== 1'bz) && PIPERX09DATA[9]; // rv 0 + assign PIPERX09ELECIDLE_in = (PIPERX09ELECIDLE === 1'bz) || PIPERX09ELECIDLE; // rv 1 + assign PIPERX09EQDONE_in = (PIPERX09EQDONE !== 1'bz) && PIPERX09EQDONE; // rv 0 + assign PIPERX09EQLPADAPTDONE_in = (PIPERX09EQLPADAPTDONE !== 1'bz) && PIPERX09EQLPADAPTDONE; // rv 0 + assign PIPERX09EQLPLFFSSEL_in = (PIPERX09EQLPLFFSSEL !== 1'bz) && PIPERX09EQLPLFFSSEL; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX09EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX09EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX09EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX09EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX09EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX09EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX09EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX09EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX09EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX09EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX09EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX09EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX09EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX09EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX09EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX09EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX09EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX09EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX09EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX09EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX09PHYSTATUS_in = (PIPERX09PHYSTATUS === 1'bz) || PIPERX09PHYSTATUS; // rv 1 + assign PIPERX09STARTBLOCK_in[0] = (PIPERX09STARTBLOCK[0] !== 1'bz) && PIPERX09STARTBLOCK[0]; // rv 0 + assign PIPERX09STARTBLOCK_in[1] = (PIPERX09STARTBLOCK[1] !== 1'bz) && PIPERX09STARTBLOCK[1]; // rv 0 + assign PIPERX09STATUS_in[0] = (PIPERX09STATUS[0] !== 1'bz) && PIPERX09STATUS[0]; // rv 0 + assign PIPERX09STATUS_in[1] = (PIPERX09STATUS[1] !== 1'bz) && PIPERX09STATUS[1]; // rv 0 + assign PIPERX09STATUS_in[2] = (PIPERX09STATUS[2] !== 1'bz) && PIPERX09STATUS[2]; // rv 0 + assign PIPERX09SYNCHEADER_in[0] = (PIPERX09SYNCHEADER[0] !== 1'bz) && PIPERX09SYNCHEADER[0]; // rv 0 + assign PIPERX09SYNCHEADER_in[1] = (PIPERX09SYNCHEADER[1] !== 1'bz) && PIPERX09SYNCHEADER[1]; // rv 0 + assign PIPERX09VALID_in = (PIPERX09VALID !== 1'bz) && PIPERX09VALID; // rv 0 + assign PIPERX10CHARISK_in[0] = (PIPERX10CHARISK[0] === 1'bz) || PIPERX10CHARISK[0]; // rv 1 + assign PIPERX10CHARISK_in[1] = (PIPERX10CHARISK[1] === 1'bz) || PIPERX10CHARISK[1]; // rv 1 + assign PIPERX10DATAVALID_in = (PIPERX10DATAVALID !== 1'bz) && PIPERX10DATAVALID; // rv 0 + assign PIPERX10DATA_in[0] = (PIPERX10DATA[0] !== 1'bz) && PIPERX10DATA[0]; // rv 0 + assign PIPERX10DATA_in[10] = (PIPERX10DATA[10] !== 1'bz) && PIPERX10DATA[10]; // rv 0 + assign PIPERX10DATA_in[11] = (PIPERX10DATA[11] !== 1'bz) && PIPERX10DATA[11]; // rv 0 + assign PIPERX10DATA_in[12] = (PIPERX10DATA[12] !== 1'bz) && PIPERX10DATA[12]; // rv 0 + assign PIPERX10DATA_in[13] = (PIPERX10DATA[13] !== 1'bz) && PIPERX10DATA[13]; // rv 0 + assign PIPERX10DATA_in[14] = (PIPERX10DATA[14] !== 1'bz) && PIPERX10DATA[14]; // rv 0 + assign PIPERX10DATA_in[15] = (PIPERX10DATA[15] !== 1'bz) && PIPERX10DATA[15]; // rv 0 + assign PIPERX10DATA_in[16] = (PIPERX10DATA[16] !== 1'bz) && PIPERX10DATA[16]; // rv 0 + assign PIPERX10DATA_in[17] = (PIPERX10DATA[17] !== 1'bz) && PIPERX10DATA[17]; // rv 0 + assign PIPERX10DATA_in[18] = (PIPERX10DATA[18] !== 1'bz) && PIPERX10DATA[18]; // rv 0 + assign PIPERX10DATA_in[19] = (PIPERX10DATA[19] !== 1'bz) && PIPERX10DATA[19]; // rv 0 + assign PIPERX10DATA_in[1] = (PIPERX10DATA[1] !== 1'bz) && PIPERX10DATA[1]; // rv 0 + assign PIPERX10DATA_in[20] = (PIPERX10DATA[20] !== 1'bz) && PIPERX10DATA[20]; // rv 0 + assign PIPERX10DATA_in[21] = (PIPERX10DATA[21] !== 1'bz) && PIPERX10DATA[21]; // rv 0 + assign PIPERX10DATA_in[22] = (PIPERX10DATA[22] !== 1'bz) && PIPERX10DATA[22]; // rv 0 + assign PIPERX10DATA_in[23] = (PIPERX10DATA[23] !== 1'bz) && PIPERX10DATA[23]; // rv 0 + assign PIPERX10DATA_in[24] = (PIPERX10DATA[24] !== 1'bz) && PIPERX10DATA[24]; // rv 0 + assign PIPERX10DATA_in[25] = (PIPERX10DATA[25] !== 1'bz) && PIPERX10DATA[25]; // rv 0 + assign PIPERX10DATA_in[26] = (PIPERX10DATA[26] !== 1'bz) && PIPERX10DATA[26]; // rv 0 + assign PIPERX10DATA_in[27] = (PIPERX10DATA[27] !== 1'bz) && PIPERX10DATA[27]; // rv 0 + assign PIPERX10DATA_in[28] = (PIPERX10DATA[28] !== 1'bz) && PIPERX10DATA[28]; // rv 0 + assign PIPERX10DATA_in[29] = (PIPERX10DATA[29] !== 1'bz) && PIPERX10DATA[29]; // rv 0 + assign PIPERX10DATA_in[2] = (PIPERX10DATA[2] !== 1'bz) && PIPERX10DATA[2]; // rv 0 + assign PIPERX10DATA_in[30] = (PIPERX10DATA[30] !== 1'bz) && PIPERX10DATA[30]; // rv 0 + assign PIPERX10DATA_in[31] = (PIPERX10DATA[31] !== 1'bz) && PIPERX10DATA[31]; // rv 0 + assign PIPERX10DATA_in[3] = (PIPERX10DATA[3] !== 1'bz) && PIPERX10DATA[3]; // rv 0 + assign PIPERX10DATA_in[4] = (PIPERX10DATA[4] !== 1'bz) && PIPERX10DATA[4]; // rv 0 + assign PIPERX10DATA_in[5] = (PIPERX10DATA[5] !== 1'bz) && PIPERX10DATA[5]; // rv 0 + assign PIPERX10DATA_in[6] = (PIPERX10DATA[6] !== 1'bz) && PIPERX10DATA[6]; // rv 0 + assign PIPERX10DATA_in[7] = (PIPERX10DATA[7] !== 1'bz) && PIPERX10DATA[7]; // rv 0 + assign PIPERX10DATA_in[8] = (PIPERX10DATA[8] !== 1'bz) && PIPERX10DATA[8]; // rv 0 + assign PIPERX10DATA_in[9] = (PIPERX10DATA[9] !== 1'bz) && PIPERX10DATA[9]; // rv 0 + assign PIPERX10ELECIDLE_in = (PIPERX10ELECIDLE === 1'bz) || PIPERX10ELECIDLE; // rv 1 + assign PIPERX10EQDONE_in = (PIPERX10EQDONE !== 1'bz) && PIPERX10EQDONE; // rv 0 + assign PIPERX10EQLPADAPTDONE_in = (PIPERX10EQLPADAPTDONE !== 1'bz) && PIPERX10EQLPADAPTDONE; // rv 0 + assign PIPERX10EQLPLFFSSEL_in = (PIPERX10EQLPLFFSSEL !== 1'bz) && PIPERX10EQLPLFFSSEL; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX10EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX10EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX10EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX10EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX10EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX10EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX10EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX10EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX10EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX10EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX10EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX10EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX10EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX10EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX10EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX10EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX10EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX10EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX10EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX10EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX10PHYSTATUS_in = (PIPERX10PHYSTATUS === 1'bz) || PIPERX10PHYSTATUS; // rv 1 + assign PIPERX10STARTBLOCK_in[0] = (PIPERX10STARTBLOCK[0] !== 1'bz) && PIPERX10STARTBLOCK[0]; // rv 0 + assign PIPERX10STARTBLOCK_in[1] = (PIPERX10STARTBLOCK[1] !== 1'bz) && PIPERX10STARTBLOCK[1]; // rv 0 + assign PIPERX10STATUS_in[0] = (PIPERX10STATUS[0] !== 1'bz) && PIPERX10STATUS[0]; // rv 0 + assign PIPERX10STATUS_in[1] = (PIPERX10STATUS[1] !== 1'bz) && PIPERX10STATUS[1]; // rv 0 + assign PIPERX10STATUS_in[2] = (PIPERX10STATUS[2] !== 1'bz) && PIPERX10STATUS[2]; // rv 0 + assign PIPERX10SYNCHEADER_in[0] = (PIPERX10SYNCHEADER[0] !== 1'bz) && PIPERX10SYNCHEADER[0]; // rv 0 + assign PIPERX10SYNCHEADER_in[1] = (PIPERX10SYNCHEADER[1] !== 1'bz) && PIPERX10SYNCHEADER[1]; // rv 0 + assign PIPERX10VALID_in = (PIPERX10VALID !== 1'bz) && PIPERX10VALID; // rv 0 + assign PIPERX11CHARISK_in[0] = (PIPERX11CHARISK[0] === 1'bz) || PIPERX11CHARISK[0]; // rv 1 + assign PIPERX11CHARISK_in[1] = (PIPERX11CHARISK[1] === 1'bz) || PIPERX11CHARISK[1]; // rv 1 + assign PIPERX11DATAVALID_in = (PIPERX11DATAVALID !== 1'bz) && PIPERX11DATAVALID; // rv 0 + assign PIPERX11DATA_in[0] = (PIPERX11DATA[0] !== 1'bz) && PIPERX11DATA[0]; // rv 0 + assign PIPERX11DATA_in[10] = (PIPERX11DATA[10] !== 1'bz) && PIPERX11DATA[10]; // rv 0 + assign PIPERX11DATA_in[11] = (PIPERX11DATA[11] !== 1'bz) && PIPERX11DATA[11]; // rv 0 + assign PIPERX11DATA_in[12] = (PIPERX11DATA[12] !== 1'bz) && PIPERX11DATA[12]; // rv 0 + assign PIPERX11DATA_in[13] = (PIPERX11DATA[13] !== 1'bz) && PIPERX11DATA[13]; // rv 0 + assign PIPERX11DATA_in[14] = (PIPERX11DATA[14] !== 1'bz) && PIPERX11DATA[14]; // rv 0 + assign PIPERX11DATA_in[15] = (PIPERX11DATA[15] !== 1'bz) && PIPERX11DATA[15]; // rv 0 + assign PIPERX11DATA_in[16] = (PIPERX11DATA[16] !== 1'bz) && PIPERX11DATA[16]; // rv 0 + assign PIPERX11DATA_in[17] = (PIPERX11DATA[17] !== 1'bz) && PIPERX11DATA[17]; // rv 0 + assign PIPERX11DATA_in[18] = (PIPERX11DATA[18] !== 1'bz) && PIPERX11DATA[18]; // rv 0 + assign PIPERX11DATA_in[19] = (PIPERX11DATA[19] !== 1'bz) && PIPERX11DATA[19]; // rv 0 + assign PIPERX11DATA_in[1] = (PIPERX11DATA[1] !== 1'bz) && PIPERX11DATA[1]; // rv 0 + assign PIPERX11DATA_in[20] = (PIPERX11DATA[20] !== 1'bz) && PIPERX11DATA[20]; // rv 0 + assign PIPERX11DATA_in[21] = (PIPERX11DATA[21] !== 1'bz) && PIPERX11DATA[21]; // rv 0 + assign PIPERX11DATA_in[22] = (PIPERX11DATA[22] !== 1'bz) && PIPERX11DATA[22]; // rv 0 + assign PIPERX11DATA_in[23] = (PIPERX11DATA[23] !== 1'bz) && PIPERX11DATA[23]; // rv 0 + assign PIPERX11DATA_in[24] = (PIPERX11DATA[24] !== 1'bz) && PIPERX11DATA[24]; // rv 0 + assign PIPERX11DATA_in[25] = (PIPERX11DATA[25] !== 1'bz) && PIPERX11DATA[25]; // rv 0 + assign PIPERX11DATA_in[26] = (PIPERX11DATA[26] !== 1'bz) && PIPERX11DATA[26]; // rv 0 + assign PIPERX11DATA_in[27] = (PIPERX11DATA[27] !== 1'bz) && PIPERX11DATA[27]; // rv 0 + assign PIPERX11DATA_in[28] = (PIPERX11DATA[28] !== 1'bz) && PIPERX11DATA[28]; // rv 0 + assign PIPERX11DATA_in[29] = (PIPERX11DATA[29] !== 1'bz) && PIPERX11DATA[29]; // rv 0 + assign PIPERX11DATA_in[2] = (PIPERX11DATA[2] !== 1'bz) && PIPERX11DATA[2]; // rv 0 + assign PIPERX11DATA_in[30] = (PIPERX11DATA[30] !== 1'bz) && PIPERX11DATA[30]; // rv 0 + assign PIPERX11DATA_in[31] = (PIPERX11DATA[31] !== 1'bz) && PIPERX11DATA[31]; // rv 0 + assign PIPERX11DATA_in[3] = (PIPERX11DATA[3] !== 1'bz) && PIPERX11DATA[3]; // rv 0 + assign PIPERX11DATA_in[4] = (PIPERX11DATA[4] !== 1'bz) && PIPERX11DATA[4]; // rv 0 + assign PIPERX11DATA_in[5] = (PIPERX11DATA[5] !== 1'bz) && PIPERX11DATA[5]; // rv 0 + assign PIPERX11DATA_in[6] = (PIPERX11DATA[6] !== 1'bz) && PIPERX11DATA[6]; // rv 0 + assign PIPERX11DATA_in[7] = (PIPERX11DATA[7] !== 1'bz) && PIPERX11DATA[7]; // rv 0 + assign PIPERX11DATA_in[8] = (PIPERX11DATA[8] !== 1'bz) && PIPERX11DATA[8]; // rv 0 + assign PIPERX11DATA_in[9] = (PIPERX11DATA[9] !== 1'bz) && PIPERX11DATA[9]; // rv 0 + assign PIPERX11ELECIDLE_in = (PIPERX11ELECIDLE === 1'bz) || PIPERX11ELECIDLE; // rv 1 + assign PIPERX11EQDONE_in = (PIPERX11EQDONE !== 1'bz) && PIPERX11EQDONE; // rv 0 + assign PIPERX11EQLPADAPTDONE_in = (PIPERX11EQLPADAPTDONE !== 1'bz) && PIPERX11EQLPADAPTDONE; // rv 0 + assign PIPERX11EQLPLFFSSEL_in = (PIPERX11EQLPLFFSSEL !== 1'bz) && PIPERX11EQLPLFFSSEL; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX11EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX11EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX11EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX11EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX11EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX11EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX11EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX11EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX11EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX11EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX11EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX11EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX11EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX11EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX11EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX11EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX11EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX11EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX11EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX11EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX11PHYSTATUS_in = (PIPERX11PHYSTATUS === 1'bz) || PIPERX11PHYSTATUS; // rv 1 + assign PIPERX11STARTBLOCK_in[0] = (PIPERX11STARTBLOCK[0] !== 1'bz) && PIPERX11STARTBLOCK[0]; // rv 0 + assign PIPERX11STARTBLOCK_in[1] = (PIPERX11STARTBLOCK[1] !== 1'bz) && PIPERX11STARTBLOCK[1]; // rv 0 + assign PIPERX11STATUS_in[0] = (PIPERX11STATUS[0] !== 1'bz) && PIPERX11STATUS[0]; // rv 0 + assign PIPERX11STATUS_in[1] = (PIPERX11STATUS[1] !== 1'bz) && PIPERX11STATUS[1]; // rv 0 + assign PIPERX11STATUS_in[2] = (PIPERX11STATUS[2] !== 1'bz) && PIPERX11STATUS[2]; // rv 0 + assign PIPERX11SYNCHEADER_in[0] = (PIPERX11SYNCHEADER[0] !== 1'bz) && PIPERX11SYNCHEADER[0]; // rv 0 + assign PIPERX11SYNCHEADER_in[1] = (PIPERX11SYNCHEADER[1] !== 1'bz) && PIPERX11SYNCHEADER[1]; // rv 0 + assign PIPERX11VALID_in = (PIPERX11VALID !== 1'bz) && PIPERX11VALID; // rv 0 + assign PIPERX12CHARISK_in[0] = (PIPERX12CHARISK[0] === 1'bz) || PIPERX12CHARISK[0]; // rv 1 + assign PIPERX12CHARISK_in[1] = (PIPERX12CHARISK[1] === 1'bz) || PIPERX12CHARISK[1]; // rv 1 + assign PIPERX12DATAVALID_in = (PIPERX12DATAVALID !== 1'bz) && PIPERX12DATAVALID; // rv 0 + assign PIPERX12DATA_in[0] = (PIPERX12DATA[0] !== 1'bz) && PIPERX12DATA[0]; // rv 0 + assign PIPERX12DATA_in[10] = (PIPERX12DATA[10] !== 1'bz) && PIPERX12DATA[10]; // rv 0 + assign PIPERX12DATA_in[11] = (PIPERX12DATA[11] !== 1'bz) && PIPERX12DATA[11]; // rv 0 + assign PIPERX12DATA_in[12] = (PIPERX12DATA[12] !== 1'bz) && PIPERX12DATA[12]; // rv 0 + assign PIPERX12DATA_in[13] = (PIPERX12DATA[13] !== 1'bz) && PIPERX12DATA[13]; // rv 0 + assign PIPERX12DATA_in[14] = (PIPERX12DATA[14] !== 1'bz) && PIPERX12DATA[14]; // rv 0 + assign PIPERX12DATA_in[15] = (PIPERX12DATA[15] !== 1'bz) && PIPERX12DATA[15]; // rv 0 + assign PIPERX12DATA_in[16] = (PIPERX12DATA[16] !== 1'bz) && PIPERX12DATA[16]; // rv 0 + assign PIPERX12DATA_in[17] = (PIPERX12DATA[17] !== 1'bz) && PIPERX12DATA[17]; // rv 0 + assign PIPERX12DATA_in[18] = (PIPERX12DATA[18] !== 1'bz) && PIPERX12DATA[18]; // rv 0 + assign PIPERX12DATA_in[19] = (PIPERX12DATA[19] !== 1'bz) && PIPERX12DATA[19]; // rv 0 + assign PIPERX12DATA_in[1] = (PIPERX12DATA[1] !== 1'bz) && PIPERX12DATA[1]; // rv 0 + assign PIPERX12DATA_in[20] = (PIPERX12DATA[20] !== 1'bz) && PIPERX12DATA[20]; // rv 0 + assign PIPERX12DATA_in[21] = (PIPERX12DATA[21] !== 1'bz) && PIPERX12DATA[21]; // rv 0 + assign PIPERX12DATA_in[22] = (PIPERX12DATA[22] !== 1'bz) && PIPERX12DATA[22]; // rv 0 + assign PIPERX12DATA_in[23] = (PIPERX12DATA[23] !== 1'bz) && PIPERX12DATA[23]; // rv 0 + assign PIPERX12DATA_in[24] = (PIPERX12DATA[24] !== 1'bz) && PIPERX12DATA[24]; // rv 0 + assign PIPERX12DATA_in[25] = (PIPERX12DATA[25] !== 1'bz) && PIPERX12DATA[25]; // rv 0 + assign PIPERX12DATA_in[26] = (PIPERX12DATA[26] !== 1'bz) && PIPERX12DATA[26]; // rv 0 + assign PIPERX12DATA_in[27] = (PIPERX12DATA[27] !== 1'bz) && PIPERX12DATA[27]; // rv 0 + assign PIPERX12DATA_in[28] = (PIPERX12DATA[28] !== 1'bz) && PIPERX12DATA[28]; // rv 0 + assign PIPERX12DATA_in[29] = (PIPERX12DATA[29] !== 1'bz) && PIPERX12DATA[29]; // rv 0 + assign PIPERX12DATA_in[2] = (PIPERX12DATA[2] !== 1'bz) && PIPERX12DATA[2]; // rv 0 + assign PIPERX12DATA_in[30] = (PIPERX12DATA[30] !== 1'bz) && PIPERX12DATA[30]; // rv 0 + assign PIPERX12DATA_in[31] = (PIPERX12DATA[31] !== 1'bz) && PIPERX12DATA[31]; // rv 0 + assign PIPERX12DATA_in[3] = (PIPERX12DATA[3] !== 1'bz) && PIPERX12DATA[3]; // rv 0 + assign PIPERX12DATA_in[4] = (PIPERX12DATA[4] !== 1'bz) && PIPERX12DATA[4]; // rv 0 + assign PIPERX12DATA_in[5] = (PIPERX12DATA[5] !== 1'bz) && PIPERX12DATA[5]; // rv 0 + assign PIPERX12DATA_in[6] = (PIPERX12DATA[6] !== 1'bz) && PIPERX12DATA[6]; // rv 0 + assign PIPERX12DATA_in[7] = (PIPERX12DATA[7] !== 1'bz) && PIPERX12DATA[7]; // rv 0 + assign PIPERX12DATA_in[8] = (PIPERX12DATA[8] !== 1'bz) && PIPERX12DATA[8]; // rv 0 + assign PIPERX12DATA_in[9] = (PIPERX12DATA[9] !== 1'bz) && PIPERX12DATA[9]; // rv 0 + assign PIPERX12ELECIDLE_in = (PIPERX12ELECIDLE === 1'bz) || PIPERX12ELECIDLE; // rv 1 + assign PIPERX12EQDONE_in = (PIPERX12EQDONE !== 1'bz) && PIPERX12EQDONE; // rv 0 + assign PIPERX12EQLPADAPTDONE_in = (PIPERX12EQLPADAPTDONE !== 1'bz) && PIPERX12EQLPADAPTDONE; // rv 0 + assign PIPERX12EQLPLFFSSEL_in = (PIPERX12EQLPLFFSSEL !== 1'bz) && PIPERX12EQLPLFFSSEL; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX12EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX12EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX12EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX12EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX12EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX12EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX12EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX12EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX12EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX12EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX12EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX12EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX12EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX12EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX12EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX12EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX12EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX12EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX12EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX12EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX12PHYSTATUS_in = (PIPERX12PHYSTATUS === 1'bz) || PIPERX12PHYSTATUS; // rv 1 + assign PIPERX12STARTBLOCK_in[0] = (PIPERX12STARTBLOCK[0] !== 1'bz) && PIPERX12STARTBLOCK[0]; // rv 0 + assign PIPERX12STARTBLOCK_in[1] = (PIPERX12STARTBLOCK[1] !== 1'bz) && PIPERX12STARTBLOCK[1]; // rv 0 + assign PIPERX12STATUS_in[0] = (PIPERX12STATUS[0] !== 1'bz) && PIPERX12STATUS[0]; // rv 0 + assign PIPERX12STATUS_in[1] = (PIPERX12STATUS[1] !== 1'bz) && PIPERX12STATUS[1]; // rv 0 + assign PIPERX12STATUS_in[2] = (PIPERX12STATUS[2] !== 1'bz) && PIPERX12STATUS[2]; // rv 0 + assign PIPERX12SYNCHEADER_in[0] = (PIPERX12SYNCHEADER[0] !== 1'bz) && PIPERX12SYNCHEADER[0]; // rv 0 + assign PIPERX12SYNCHEADER_in[1] = (PIPERX12SYNCHEADER[1] !== 1'bz) && PIPERX12SYNCHEADER[1]; // rv 0 + assign PIPERX12VALID_in = (PIPERX12VALID !== 1'bz) && PIPERX12VALID; // rv 0 + assign PIPERX13CHARISK_in[0] = (PIPERX13CHARISK[0] === 1'bz) || PIPERX13CHARISK[0]; // rv 1 + assign PIPERX13CHARISK_in[1] = (PIPERX13CHARISK[1] === 1'bz) || PIPERX13CHARISK[1]; // rv 1 + assign PIPERX13DATAVALID_in = (PIPERX13DATAVALID !== 1'bz) && PIPERX13DATAVALID; // rv 0 + assign PIPERX13DATA_in[0] = (PIPERX13DATA[0] !== 1'bz) && PIPERX13DATA[0]; // rv 0 + assign PIPERX13DATA_in[10] = (PIPERX13DATA[10] !== 1'bz) && PIPERX13DATA[10]; // rv 0 + assign PIPERX13DATA_in[11] = (PIPERX13DATA[11] !== 1'bz) && PIPERX13DATA[11]; // rv 0 + assign PIPERX13DATA_in[12] = (PIPERX13DATA[12] !== 1'bz) && PIPERX13DATA[12]; // rv 0 + assign PIPERX13DATA_in[13] = (PIPERX13DATA[13] !== 1'bz) && PIPERX13DATA[13]; // rv 0 + assign PIPERX13DATA_in[14] = (PIPERX13DATA[14] !== 1'bz) && PIPERX13DATA[14]; // rv 0 + assign PIPERX13DATA_in[15] = (PIPERX13DATA[15] !== 1'bz) && PIPERX13DATA[15]; // rv 0 + assign PIPERX13DATA_in[16] = (PIPERX13DATA[16] !== 1'bz) && PIPERX13DATA[16]; // rv 0 + assign PIPERX13DATA_in[17] = (PIPERX13DATA[17] !== 1'bz) && PIPERX13DATA[17]; // rv 0 + assign PIPERX13DATA_in[18] = (PIPERX13DATA[18] !== 1'bz) && PIPERX13DATA[18]; // rv 0 + assign PIPERX13DATA_in[19] = (PIPERX13DATA[19] !== 1'bz) && PIPERX13DATA[19]; // rv 0 + assign PIPERX13DATA_in[1] = (PIPERX13DATA[1] !== 1'bz) && PIPERX13DATA[1]; // rv 0 + assign PIPERX13DATA_in[20] = (PIPERX13DATA[20] !== 1'bz) && PIPERX13DATA[20]; // rv 0 + assign PIPERX13DATA_in[21] = (PIPERX13DATA[21] !== 1'bz) && PIPERX13DATA[21]; // rv 0 + assign PIPERX13DATA_in[22] = (PIPERX13DATA[22] !== 1'bz) && PIPERX13DATA[22]; // rv 0 + assign PIPERX13DATA_in[23] = (PIPERX13DATA[23] !== 1'bz) && PIPERX13DATA[23]; // rv 0 + assign PIPERX13DATA_in[24] = (PIPERX13DATA[24] !== 1'bz) && PIPERX13DATA[24]; // rv 0 + assign PIPERX13DATA_in[25] = (PIPERX13DATA[25] !== 1'bz) && PIPERX13DATA[25]; // rv 0 + assign PIPERX13DATA_in[26] = (PIPERX13DATA[26] !== 1'bz) && PIPERX13DATA[26]; // rv 0 + assign PIPERX13DATA_in[27] = (PIPERX13DATA[27] !== 1'bz) && PIPERX13DATA[27]; // rv 0 + assign PIPERX13DATA_in[28] = (PIPERX13DATA[28] !== 1'bz) && PIPERX13DATA[28]; // rv 0 + assign PIPERX13DATA_in[29] = (PIPERX13DATA[29] !== 1'bz) && PIPERX13DATA[29]; // rv 0 + assign PIPERX13DATA_in[2] = (PIPERX13DATA[2] !== 1'bz) && PIPERX13DATA[2]; // rv 0 + assign PIPERX13DATA_in[30] = (PIPERX13DATA[30] !== 1'bz) && PIPERX13DATA[30]; // rv 0 + assign PIPERX13DATA_in[31] = (PIPERX13DATA[31] !== 1'bz) && PIPERX13DATA[31]; // rv 0 + assign PIPERX13DATA_in[3] = (PIPERX13DATA[3] !== 1'bz) && PIPERX13DATA[3]; // rv 0 + assign PIPERX13DATA_in[4] = (PIPERX13DATA[4] !== 1'bz) && PIPERX13DATA[4]; // rv 0 + assign PIPERX13DATA_in[5] = (PIPERX13DATA[5] !== 1'bz) && PIPERX13DATA[5]; // rv 0 + assign PIPERX13DATA_in[6] = (PIPERX13DATA[6] !== 1'bz) && PIPERX13DATA[6]; // rv 0 + assign PIPERX13DATA_in[7] = (PIPERX13DATA[7] !== 1'bz) && PIPERX13DATA[7]; // rv 0 + assign PIPERX13DATA_in[8] = (PIPERX13DATA[8] !== 1'bz) && PIPERX13DATA[8]; // rv 0 + assign PIPERX13DATA_in[9] = (PIPERX13DATA[9] !== 1'bz) && PIPERX13DATA[9]; // rv 0 + assign PIPERX13ELECIDLE_in = (PIPERX13ELECIDLE === 1'bz) || PIPERX13ELECIDLE; // rv 1 + assign PIPERX13EQDONE_in = (PIPERX13EQDONE !== 1'bz) && PIPERX13EQDONE; // rv 0 + assign PIPERX13EQLPADAPTDONE_in = (PIPERX13EQLPADAPTDONE !== 1'bz) && PIPERX13EQLPADAPTDONE; // rv 0 + assign PIPERX13EQLPLFFSSEL_in = (PIPERX13EQLPLFFSSEL !== 1'bz) && PIPERX13EQLPLFFSSEL; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX13EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX13EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX13EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX13EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX13EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX13EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX13EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX13EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX13EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX13EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX13EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX13EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX13EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX13EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX13EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX13EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX13EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX13EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX13EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX13EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX13PHYSTATUS_in = (PIPERX13PHYSTATUS === 1'bz) || PIPERX13PHYSTATUS; // rv 1 + assign PIPERX13STARTBLOCK_in[0] = (PIPERX13STARTBLOCK[0] !== 1'bz) && PIPERX13STARTBLOCK[0]; // rv 0 + assign PIPERX13STARTBLOCK_in[1] = (PIPERX13STARTBLOCK[1] !== 1'bz) && PIPERX13STARTBLOCK[1]; // rv 0 + assign PIPERX13STATUS_in[0] = (PIPERX13STATUS[0] !== 1'bz) && PIPERX13STATUS[0]; // rv 0 + assign PIPERX13STATUS_in[1] = (PIPERX13STATUS[1] !== 1'bz) && PIPERX13STATUS[1]; // rv 0 + assign PIPERX13STATUS_in[2] = (PIPERX13STATUS[2] !== 1'bz) && PIPERX13STATUS[2]; // rv 0 + assign PIPERX13SYNCHEADER_in[0] = (PIPERX13SYNCHEADER[0] !== 1'bz) && PIPERX13SYNCHEADER[0]; // rv 0 + assign PIPERX13SYNCHEADER_in[1] = (PIPERX13SYNCHEADER[1] !== 1'bz) && PIPERX13SYNCHEADER[1]; // rv 0 + assign PIPERX13VALID_in = (PIPERX13VALID !== 1'bz) && PIPERX13VALID; // rv 0 + assign PIPERX14CHARISK_in[0] = (PIPERX14CHARISK[0] === 1'bz) || PIPERX14CHARISK[0]; // rv 1 + assign PIPERX14CHARISK_in[1] = (PIPERX14CHARISK[1] === 1'bz) || PIPERX14CHARISK[1]; // rv 1 + assign PIPERX14DATAVALID_in = (PIPERX14DATAVALID !== 1'bz) && PIPERX14DATAVALID; // rv 0 + assign PIPERX14DATA_in[0] = (PIPERX14DATA[0] !== 1'bz) && PIPERX14DATA[0]; // rv 0 + assign PIPERX14DATA_in[10] = (PIPERX14DATA[10] !== 1'bz) && PIPERX14DATA[10]; // rv 0 + assign PIPERX14DATA_in[11] = (PIPERX14DATA[11] !== 1'bz) && PIPERX14DATA[11]; // rv 0 + assign PIPERX14DATA_in[12] = (PIPERX14DATA[12] !== 1'bz) && PIPERX14DATA[12]; // rv 0 + assign PIPERX14DATA_in[13] = (PIPERX14DATA[13] !== 1'bz) && PIPERX14DATA[13]; // rv 0 + assign PIPERX14DATA_in[14] = (PIPERX14DATA[14] !== 1'bz) && PIPERX14DATA[14]; // rv 0 + assign PIPERX14DATA_in[15] = (PIPERX14DATA[15] !== 1'bz) && PIPERX14DATA[15]; // rv 0 + assign PIPERX14DATA_in[16] = (PIPERX14DATA[16] !== 1'bz) && PIPERX14DATA[16]; // rv 0 + assign PIPERX14DATA_in[17] = (PIPERX14DATA[17] !== 1'bz) && PIPERX14DATA[17]; // rv 0 + assign PIPERX14DATA_in[18] = (PIPERX14DATA[18] !== 1'bz) && PIPERX14DATA[18]; // rv 0 + assign PIPERX14DATA_in[19] = (PIPERX14DATA[19] !== 1'bz) && PIPERX14DATA[19]; // rv 0 + assign PIPERX14DATA_in[1] = (PIPERX14DATA[1] !== 1'bz) && PIPERX14DATA[1]; // rv 0 + assign PIPERX14DATA_in[20] = (PIPERX14DATA[20] !== 1'bz) && PIPERX14DATA[20]; // rv 0 + assign PIPERX14DATA_in[21] = (PIPERX14DATA[21] !== 1'bz) && PIPERX14DATA[21]; // rv 0 + assign PIPERX14DATA_in[22] = (PIPERX14DATA[22] !== 1'bz) && PIPERX14DATA[22]; // rv 0 + assign PIPERX14DATA_in[23] = (PIPERX14DATA[23] !== 1'bz) && PIPERX14DATA[23]; // rv 0 + assign PIPERX14DATA_in[24] = (PIPERX14DATA[24] !== 1'bz) && PIPERX14DATA[24]; // rv 0 + assign PIPERX14DATA_in[25] = (PIPERX14DATA[25] !== 1'bz) && PIPERX14DATA[25]; // rv 0 + assign PIPERX14DATA_in[26] = (PIPERX14DATA[26] !== 1'bz) && PIPERX14DATA[26]; // rv 0 + assign PIPERX14DATA_in[27] = (PIPERX14DATA[27] !== 1'bz) && PIPERX14DATA[27]; // rv 0 + assign PIPERX14DATA_in[28] = (PIPERX14DATA[28] !== 1'bz) && PIPERX14DATA[28]; // rv 0 + assign PIPERX14DATA_in[29] = (PIPERX14DATA[29] !== 1'bz) && PIPERX14DATA[29]; // rv 0 + assign PIPERX14DATA_in[2] = (PIPERX14DATA[2] !== 1'bz) && PIPERX14DATA[2]; // rv 0 + assign PIPERX14DATA_in[30] = (PIPERX14DATA[30] !== 1'bz) && PIPERX14DATA[30]; // rv 0 + assign PIPERX14DATA_in[31] = (PIPERX14DATA[31] !== 1'bz) && PIPERX14DATA[31]; // rv 0 + assign PIPERX14DATA_in[3] = (PIPERX14DATA[3] !== 1'bz) && PIPERX14DATA[3]; // rv 0 + assign PIPERX14DATA_in[4] = (PIPERX14DATA[4] !== 1'bz) && PIPERX14DATA[4]; // rv 0 + assign PIPERX14DATA_in[5] = (PIPERX14DATA[5] !== 1'bz) && PIPERX14DATA[5]; // rv 0 + assign PIPERX14DATA_in[6] = (PIPERX14DATA[6] !== 1'bz) && PIPERX14DATA[6]; // rv 0 + assign PIPERX14DATA_in[7] = (PIPERX14DATA[7] !== 1'bz) && PIPERX14DATA[7]; // rv 0 + assign PIPERX14DATA_in[8] = (PIPERX14DATA[8] !== 1'bz) && PIPERX14DATA[8]; // rv 0 + assign PIPERX14DATA_in[9] = (PIPERX14DATA[9] !== 1'bz) && PIPERX14DATA[9]; // rv 0 + assign PIPERX14ELECIDLE_in = (PIPERX14ELECIDLE === 1'bz) || PIPERX14ELECIDLE; // rv 1 + assign PIPERX14EQDONE_in = (PIPERX14EQDONE !== 1'bz) && PIPERX14EQDONE; // rv 0 + assign PIPERX14EQLPADAPTDONE_in = (PIPERX14EQLPADAPTDONE !== 1'bz) && PIPERX14EQLPADAPTDONE; // rv 0 + assign PIPERX14EQLPLFFSSEL_in = (PIPERX14EQLPLFFSSEL !== 1'bz) && PIPERX14EQLPLFFSSEL; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX14EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX14EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX14EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX14EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX14EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX14EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX14EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX14EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX14EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX14EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX14EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX14EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX14EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX14EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX14EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX14EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX14EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX14EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX14EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX14EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX14PHYSTATUS_in = (PIPERX14PHYSTATUS === 1'bz) || PIPERX14PHYSTATUS; // rv 1 + assign PIPERX14STARTBLOCK_in[0] = (PIPERX14STARTBLOCK[0] !== 1'bz) && PIPERX14STARTBLOCK[0]; // rv 0 + assign PIPERX14STARTBLOCK_in[1] = (PIPERX14STARTBLOCK[1] !== 1'bz) && PIPERX14STARTBLOCK[1]; // rv 0 + assign PIPERX14STATUS_in[0] = (PIPERX14STATUS[0] !== 1'bz) && PIPERX14STATUS[0]; // rv 0 + assign PIPERX14STATUS_in[1] = (PIPERX14STATUS[1] !== 1'bz) && PIPERX14STATUS[1]; // rv 0 + assign PIPERX14STATUS_in[2] = (PIPERX14STATUS[2] !== 1'bz) && PIPERX14STATUS[2]; // rv 0 + assign PIPERX14SYNCHEADER_in[0] = (PIPERX14SYNCHEADER[0] !== 1'bz) && PIPERX14SYNCHEADER[0]; // rv 0 + assign PIPERX14SYNCHEADER_in[1] = (PIPERX14SYNCHEADER[1] !== 1'bz) && PIPERX14SYNCHEADER[1]; // rv 0 + assign PIPERX14VALID_in = (PIPERX14VALID !== 1'bz) && PIPERX14VALID; // rv 0 + assign PIPERX15CHARISK_in[0] = (PIPERX15CHARISK[0] === 1'bz) || PIPERX15CHARISK[0]; // rv 1 + assign PIPERX15CHARISK_in[1] = (PIPERX15CHARISK[1] === 1'bz) || PIPERX15CHARISK[1]; // rv 1 + assign PIPERX15DATAVALID_in = (PIPERX15DATAVALID !== 1'bz) && PIPERX15DATAVALID; // rv 0 + assign PIPERX15DATA_in[0] = (PIPERX15DATA[0] !== 1'bz) && PIPERX15DATA[0]; // rv 0 + assign PIPERX15DATA_in[10] = (PIPERX15DATA[10] !== 1'bz) && PIPERX15DATA[10]; // rv 0 + assign PIPERX15DATA_in[11] = (PIPERX15DATA[11] !== 1'bz) && PIPERX15DATA[11]; // rv 0 + assign PIPERX15DATA_in[12] = (PIPERX15DATA[12] !== 1'bz) && PIPERX15DATA[12]; // rv 0 + assign PIPERX15DATA_in[13] = (PIPERX15DATA[13] !== 1'bz) && PIPERX15DATA[13]; // rv 0 + assign PIPERX15DATA_in[14] = (PIPERX15DATA[14] !== 1'bz) && PIPERX15DATA[14]; // rv 0 + assign PIPERX15DATA_in[15] = (PIPERX15DATA[15] !== 1'bz) && PIPERX15DATA[15]; // rv 0 + assign PIPERX15DATA_in[16] = (PIPERX15DATA[16] !== 1'bz) && PIPERX15DATA[16]; // rv 0 + assign PIPERX15DATA_in[17] = (PIPERX15DATA[17] !== 1'bz) && PIPERX15DATA[17]; // rv 0 + assign PIPERX15DATA_in[18] = (PIPERX15DATA[18] !== 1'bz) && PIPERX15DATA[18]; // rv 0 + assign PIPERX15DATA_in[19] = (PIPERX15DATA[19] !== 1'bz) && PIPERX15DATA[19]; // rv 0 + assign PIPERX15DATA_in[1] = (PIPERX15DATA[1] !== 1'bz) && PIPERX15DATA[1]; // rv 0 + assign PIPERX15DATA_in[20] = (PIPERX15DATA[20] !== 1'bz) && PIPERX15DATA[20]; // rv 0 + assign PIPERX15DATA_in[21] = (PIPERX15DATA[21] !== 1'bz) && PIPERX15DATA[21]; // rv 0 + assign PIPERX15DATA_in[22] = (PIPERX15DATA[22] !== 1'bz) && PIPERX15DATA[22]; // rv 0 + assign PIPERX15DATA_in[23] = (PIPERX15DATA[23] !== 1'bz) && PIPERX15DATA[23]; // rv 0 + assign PIPERX15DATA_in[24] = (PIPERX15DATA[24] !== 1'bz) && PIPERX15DATA[24]; // rv 0 + assign PIPERX15DATA_in[25] = (PIPERX15DATA[25] !== 1'bz) && PIPERX15DATA[25]; // rv 0 + assign PIPERX15DATA_in[26] = (PIPERX15DATA[26] !== 1'bz) && PIPERX15DATA[26]; // rv 0 + assign PIPERX15DATA_in[27] = (PIPERX15DATA[27] !== 1'bz) && PIPERX15DATA[27]; // rv 0 + assign PIPERX15DATA_in[28] = (PIPERX15DATA[28] !== 1'bz) && PIPERX15DATA[28]; // rv 0 + assign PIPERX15DATA_in[29] = (PIPERX15DATA[29] !== 1'bz) && PIPERX15DATA[29]; // rv 0 + assign PIPERX15DATA_in[2] = (PIPERX15DATA[2] !== 1'bz) && PIPERX15DATA[2]; // rv 0 + assign PIPERX15DATA_in[30] = (PIPERX15DATA[30] !== 1'bz) && PIPERX15DATA[30]; // rv 0 + assign PIPERX15DATA_in[31] = (PIPERX15DATA[31] !== 1'bz) && PIPERX15DATA[31]; // rv 0 + assign PIPERX15DATA_in[3] = (PIPERX15DATA[3] !== 1'bz) && PIPERX15DATA[3]; // rv 0 + assign PIPERX15DATA_in[4] = (PIPERX15DATA[4] !== 1'bz) && PIPERX15DATA[4]; // rv 0 + assign PIPERX15DATA_in[5] = (PIPERX15DATA[5] !== 1'bz) && PIPERX15DATA[5]; // rv 0 + assign PIPERX15DATA_in[6] = (PIPERX15DATA[6] !== 1'bz) && PIPERX15DATA[6]; // rv 0 + assign PIPERX15DATA_in[7] = (PIPERX15DATA[7] !== 1'bz) && PIPERX15DATA[7]; // rv 0 + assign PIPERX15DATA_in[8] = (PIPERX15DATA[8] !== 1'bz) && PIPERX15DATA[8]; // rv 0 + assign PIPERX15DATA_in[9] = (PIPERX15DATA[9] !== 1'bz) && PIPERX15DATA[9]; // rv 0 + assign PIPERX15ELECIDLE_in = (PIPERX15ELECIDLE === 1'bz) || PIPERX15ELECIDLE; // rv 1 + assign PIPERX15EQDONE_in = (PIPERX15EQDONE !== 1'bz) && PIPERX15EQDONE; // rv 0 + assign PIPERX15EQLPADAPTDONE_in = (PIPERX15EQLPADAPTDONE !== 1'bz) && PIPERX15EQLPADAPTDONE; // rv 0 + assign PIPERX15EQLPLFFSSEL_in = (PIPERX15EQLPLFFSSEL !== 1'bz) && PIPERX15EQLPLFFSSEL; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX15EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[0]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX15EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[10]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX15EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[11]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX15EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[12]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX15EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[13]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX15EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[14]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX15EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[15]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX15EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[16]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX15EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[17]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX15EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[1]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX15EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[2]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX15EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[3]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX15EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[4]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX15EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[5]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX15EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[6]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX15EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[7]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX15EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[8]; // rv 0 + assign PIPERX15EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX15EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX15EQLPNEWTXCOEFFORPRESET[9]; // rv 0 + assign PIPERX15PHYSTATUS_in = (PIPERX15PHYSTATUS === 1'bz) || PIPERX15PHYSTATUS; // rv 1 + assign PIPERX15STARTBLOCK_in[0] = (PIPERX15STARTBLOCK[0] !== 1'bz) && PIPERX15STARTBLOCK[0]; // rv 0 + assign PIPERX15STARTBLOCK_in[1] = (PIPERX15STARTBLOCK[1] !== 1'bz) && PIPERX15STARTBLOCK[1]; // rv 0 + assign PIPERX15STATUS_in[0] = (PIPERX15STATUS[0] !== 1'bz) && PIPERX15STATUS[0]; // rv 0 + assign PIPERX15STATUS_in[1] = (PIPERX15STATUS[1] !== 1'bz) && PIPERX15STATUS[1]; // rv 0 + assign PIPERX15STATUS_in[2] = (PIPERX15STATUS[2] !== 1'bz) && PIPERX15STATUS[2]; // rv 0 + assign PIPERX15SYNCHEADER_in[0] = (PIPERX15SYNCHEADER[0] !== 1'bz) && PIPERX15SYNCHEADER[0]; // rv 0 + assign PIPERX15SYNCHEADER_in[1] = (PIPERX15SYNCHEADER[1] !== 1'bz) && PIPERX15SYNCHEADER[1]; // rv 0 + assign PIPERX15VALID_in = (PIPERX15VALID !== 1'bz) && PIPERX15VALID; // rv 0 + assign PIPETX00EQCOEFF_in[0] = (PIPETX00EQCOEFF[0] !== 1'bz) && PIPETX00EQCOEFF[0]; // rv 0 + assign PIPETX00EQCOEFF_in[10] = (PIPETX00EQCOEFF[10] !== 1'bz) && PIPETX00EQCOEFF[10]; // rv 0 + assign PIPETX00EQCOEFF_in[11] = (PIPETX00EQCOEFF[11] !== 1'bz) && PIPETX00EQCOEFF[11]; // rv 0 + assign PIPETX00EQCOEFF_in[12] = (PIPETX00EQCOEFF[12] !== 1'bz) && PIPETX00EQCOEFF[12]; // rv 0 + assign PIPETX00EQCOEFF_in[13] = (PIPETX00EQCOEFF[13] !== 1'bz) && PIPETX00EQCOEFF[13]; // rv 0 + assign PIPETX00EQCOEFF_in[14] = (PIPETX00EQCOEFF[14] !== 1'bz) && PIPETX00EQCOEFF[14]; // rv 0 + assign PIPETX00EQCOEFF_in[15] = (PIPETX00EQCOEFF[15] !== 1'bz) && PIPETX00EQCOEFF[15]; // rv 0 + assign PIPETX00EQCOEFF_in[16] = (PIPETX00EQCOEFF[16] !== 1'bz) && PIPETX00EQCOEFF[16]; // rv 0 + assign PIPETX00EQCOEFF_in[17] = (PIPETX00EQCOEFF[17] !== 1'bz) && PIPETX00EQCOEFF[17]; // rv 0 + assign PIPETX00EQCOEFF_in[1] = (PIPETX00EQCOEFF[1] !== 1'bz) && PIPETX00EQCOEFF[1]; // rv 0 + assign PIPETX00EQCOEFF_in[2] = (PIPETX00EQCOEFF[2] !== 1'bz) && PIPETX00EQCOEFF[2]; // rv 0 + assign PIPETX00EQCOEFF_in[3] = (PIPETX00EQCOEFF[3] !== 1'bz) && PIPETX00EQCOEFF[3]; // rv 0 + assign PIPETX00EQCOEFF_in[4] = (PIPETX00EQCOEFF[4] !== 1'bz) && PIPETX00EQCOEFF[4]; // rv 0 + assign PIPETX00EQCOEFF_in[5] = (PIPETX00EQCOEFF[5] !== 1'bz) && PIPETX00EQCOEFF[5]; // rv 0 + assign PIPETX00EQCOEFF_in[6] = (PIPETX00EQCOEFF[6] !== 1'bz) && PIPETX00EQCOEFF[6]; // rv 0 + assign PIPETX00EQCOEFF_in[7] = (PIPETX00EQCOEFF[7] !== 1'bz) && PIPETX00EQCOEFF[7]; // rv 0 + assign PIPETX00EQCOEFF_in[8] = (PIPETX00EQCOEFF[8] !== 1'bz) && PIPETX00EQCOEFF[8]; // rv 0 + assign PIPETX00EQCOEFF_in[9] = (PIPETX00EQCOEFF[9] !== 1'bz) && PIPETX00EQCOEFF[9]; // rv 0 + assign PIPETX00EQDONE_in = (PIPETX00EQDONE !== 1'bz) && PIPETX00EQDONE; // rv 0 + assign PIPETX01EQCOEFF_in[0] = (PIPETX01EQCOEFF[0] !== 1'bz) && PIPETX01EQCOEFF[0]; // rv 0 + assign PIPETX01EQCOEFF_in[10] = (PIPETX01EQCOEFF[10] !== 1'bz) && PIPETX01EQCOEFF[10]; // rv 0 + assign PIPETX01EQCOEFF_in[11] = (PIPETX01EQCOEFF[11] !== 1'bz) && PIPETX01EQCOEFF[11]; // rv 0 + assign PIPETX01EQCOEFF_in[12] = (PIPETX01EQCOEFF[12] !== 1'bz) && PIPETX01EQCOEFF[12]; // rv 0 + assign PIPETX01EQCOEFF_in[13] = (PIPETX01EQCOEFF[13] !== 1'bz) && PIPETX01EQCOEFF[13]; // rv 0 + assign PIPETX01EQCOEFF_in[14] = (PIPETX01EQCOEFF[14] !== 1'bz) && PIPETX01EQCOEFF[14]; // rv 0 + assign PIPETX01EQCOEFF_in[15] = (PIPETX01EQCOEFF[15] !== 1'bz) && PIPETX01EQCOEFF[15]; // rv 0 + assign PIPETX01EQCOEFF_in[16] = (PIPETX01EQCOEFF[16] !== 1'bz) && PIPETX01EQCOEFF[16]; // rv 0 + assign PIPETX01EQCOEFF_in[17] = (PIPETX01EQCOEFF[17] !== 1'bz) && PIPETX01EQCOEFF[17]; // rv 0 + assign PIPETX01EQCOEFF_in[1] = (PIPETX01EQCOEFF[1] !== 1'bz) && PIPETX01EQCOEFF[1]; // rv 0 + assign PIPETX01EQCOEFF_in[2] = (PIPETX01EQCOEFF[2] !== 1'bz) && PIPETX01EQCOEFF[2]; // rv 0 + assign PIPETX01EQCOEFF_in[3] = (PIPETX01EQCOEFF[3] !== 1'bz) && PIPETX01EQCOEFF[3]; // rv 0 + assign PIPETX01EQCOEFF_in[4] = (PIPETX01EQCOEFF[4] !== 1'bz) && PIPETX01EQCOEFF[4]; // rv 0 + assign PIPETX01EQCOEFF_in[5] = (PIPETX01EQCOEFF[5] !== 1'bz) && PIPETX01EQCOEFF[5]; // rv 0 + assign PIPETX01EQCOEFF_in[6] = (PIPETX01EQCOEFF[6] !== 1'bz) && PIPETX01EQCOEFF[6]; // rv 0 + assign PIPETX01EQCOEFF_in[7] = (PIPETX01EQCOEFF[7] !== 1'bz) && PIPETX01EQCOEFF[7]; // rv 0 + assign PIPETX01EQCOEFF_in[8] = (PIPETX01EQCOEFF[8] !== 1'bz) && PIPETX01EQCOEFF[8]; // rv 0 + assign PIPETX01EQCOEFF_in[9] = (PIPETX01EQCOEFF[9] !== 1'bz) && PIPETX01EQCOEFF[9]; // rv 0 + assign PIPETX01EQDONE_in = (PIPETX01EQDONE !== 1'bz) && PIPETX01EQDONE; // rv 0 + assign PIPETX02EQCOEFF_in[0] = (PIPETX02EQCOEFF[0] !== 1'bz) && PIPETX02EQCOEFF[0]; // rv 0 + assign PIPETX02EQCOEFF_in[10] = (PIPETX02EQCOEFF[10] !== 1'bz) && PIPETX02EQCOEFF[10]; // rv 0 + assign PIPETX02EQCOEFF_in[11] = (PIPETX02EQCOEFF[11] !== 1'bz) && PIPETX02EQCOEFF[11]; // rv 0 + assign PIPETX02EQCOEFF_in[12] = (PIPETX02EQCOEFF[12] !== 1'bz) && PIPETX02EQCOEFF[12]; // rv 0 + assign PIPETX02EQCOEFF_in[13] = (PIPETX02EQCOEFF[13] !== 1'bz) && PIPETX02EQCOEFF[13]; // rv 0 + assign PIPETX02EQCOEFF_in[14] = (PIPETX02EQCOEFF[14] !== 1'bz) && PIPETX02EQCOEFF[14]; // rv 0 + assign PIPETX02EQCOEFF_in[15] = (PIPETX02EQCOEFF[15] !== 1'bz) && PIPETX02EQCOEFF[15]; // rv 0 + assign PIPETX02EQCOEFF_in[16] = (PIPETX02EQCOEFF[16] !== 1'bz) && PIPETX02EQCOEFF[16]; // rv 0 + assign PIPETX02EQCOEFF_in[17] = (PIPETX02EQCOEFF[17] !== 1'bz) && PIPETX02EQCOEFF[17]; // rv 0 + assign PIPETX02EQCOEFF_in[1] = (PIPETX02EQCOEFF[1] !== 1'bz) && PIPETX02EQCOEFF[1]; // rv 0 + assign PIPETX02EQCOEFF_in[2] = (PIPETX02EQCOEFF[2] !== 1'bz) && PIPETX02EQCOEFF[2]; // rv 0 + assign PIPETX02EQCOEFF_in[3] = (PIPETX02EQCOEFF[3] !== 1'bz) && PIPETX02EQCOEFF[3]; // rv 0 + assign PIPETX02EQCOEFF_in[4] = (PIPETX02EQCOEFF[4] !== 1'bz) && PIPETX02EQCOEFF[4]; // rv 0 + assign PIPETX02EQCOEFF_in[5] = (PIPETX02EQCOEFF[5] !== 1'bz) && PIPETX02EQCOEFF[5]; // rv 0 + assign PIPETX02EQCOEFF_in[6] = (PIPETX02EQCOEFF[6] !== 1'bz) && PIPETX02EQCOEFF[6]; // rv 0 + assign PIPETX02EQCOEFF_in[7] = (PIPETX02EQCOEFF[7] !== 1'bz) && PIPETX02EQCOEFF[7]; // rv 0 + assign PIPETX02EQCOEFF_in[8] = (PIPETX02EQCOEFF[8] !== 1'bz) && PIPETX02EQCOEFF[8]; // rv 0 + assign PIPETX02EQCOEFF_in[9] = (PIPETX02EQCOEFF[9] !== 1'bz) && PIPETX02EQCOEFF[9]; // rv 0 + assign PIPETX02EQDONE_in = (PIPETX02EQDONE !== 1'bz) && PIPETX02EQDONE; // rv 0 + assign PIPETX03EQCOEFF_in[0] = (PIPETX03EQCOEFF[0] !== 1'bz) && PIPETX03EQCOEFF[0]; // rv 0 + assign PIPETX03EQCOEFF_in[10] = (PIPETX03EQCOEFF[10] !== 1'bz) && PIPETX03EQCOEFF[10]; // rv 0 + assign PIPETX03EQCOEFF_in[11] = (PIPETX03EQCOEFF[11] !== 1'bz) && PIPETX03EQCOEFF[11]; // rv 0 + assign PIPETX03EQCOEFF_in[12] = (PIPETX03EQCOEFF[12] !== 1'bz) && PIPETX03EQCOEFF[12]; // rv 0 + assign PIPETX03EQCOEFF_in[13] = (PIPETX03EQCOEFF[13] !== 1'bz) && PIPETX03EQCOEFF[13]; // rv 0 + assign PIPETX03EQCOEFF_in[14] = (PIPETX03EQCOEFF[14] !== 1'bz) && PIPETX03EQCOEFF[14]; // rv 0 + assign PIPETX03EQCOEFF_in[15] = (PIPETX03EQCOEFF[15] !== 1'bz) && PIPETX03EQCOEFF[15]; // rv 0 + assign PIPETX03EQCOEFF_in[16] = (PIPETX03EQCOEFF[16] !== 1'bz) && PIPETX03EQCOEFF[16]; // rv 0 + assign PIPETX03EQCOEFF_in[17] = (PIPETX03EQCOEFF[17] !== 1'bz) && PIPETX03EQCOEFF[17]; // rv 0 + assign PIPETX03EQCOEFF_in[1] = (PIPETX03EQCOEFF[1] !== 1'bz) && PIPETX03EQCOEFF[1]; // rv 0 + assign PIPETX03EQCOEFF_in[2] = (PIPETX03EQCOEFF[2] !== 1'bz) && PIPETX03EQCOEFF[2]; // rv 0 + assign PIPETX03EQCOEFF_in[3] = (PIPETX03EQCOEFF[3] !== 1'bz) && PIPETX03EQCOEFF[3]; // rv 0 + assign PIPETX03EQCOEFF_in[4] = (PIPETX03EQCOEFF[4] !== 1'bz) && PIPETX03EQCOEFF[4]; // rv 0 + assign PIPETX03EQCOEFF_in[5] = (PIPETX03EQCOEFF[5] !== 1'bz) && PIPETX03EQCOEFF[5]; // rv 0 + assign PIPETX03EQCOEFF_in[6] = (PIPETX03EQCOEFF[6] !== 1'bz) && PIPETX03EQCOEFF[6]; // rv 0 + assign PIPETX03EQCOEFF_in[7] = (PIPETX03EQCOEFF[7] !== 1'bz) && PIPETX03EQCOEFF[7]; // rv 0 + assign PIPETX03EQCOEFF_in[8] = (PIPETX03EQCOEFF[8] !== 1'bz) && PIPETX03EQCOEFF[8]; // rv 0 + assign PIPETX03EQCOEFF_in[9] = (PIPETX03EQCOEFF[9] !== 1'bz) && PIPETX03EQCOEFF[9]; // rv 0 + assign PIPETX03EQDONE_in = (PIPETX03EQDONE !== 1'bz) && PIPETX03EQDONE; // rv 0 + assign PIPETX04EQCOEFF_in[0] = (PIPETX04EQCOEFF[0] !== 1'bz) && PIPETX04EQCOEFF[0]; // rv 0 + assign PIPETX04EQCOEFF_in[10] = (PIPETX04EQCOEFF[10] !== 1'bz) && PIPETX04EQCOEFF[10]; // rv 0 + assign PIPETX04EQCOEFF_in[11] = (PIPETX04EQCOEFF[11] !== 1'bz) && PIPETX04EQCOEFF[11]; // rv 0 + assign PIPETX04EQCOEFF_in[12] = (PIPETX04EQCOEFF[12] !== 1'bz) && PIPETX04EQCOEFF[12]; // rv 0 + assign PIPETX04EQCOEFF_in[13] = (PIPETX04EQCOEFF[13] !== 1'bz) && PIPETX04EQCOEFF[13]; // rv 0 + assign PIPETX04EQCOEFF_in[14] = (PIPETX04EQCOEFF[14] !== 1'bz) && PIPETX04EQCOEFF[14]; // rv 0 + assign PIPETX04EQCOEFF_in[15] = (PIPETX04EQCOEFF[15] !== 1'bz) && PIPETX04EQCOEFF[15]; // rv 0 + assign PIPETX04EQCOEFF_in[16] = (PIPETX04EQCOEFF[16] !== 1'bz) && PIPETX04EQCOEFF[16]; // rv 0 + assign PIPETX04EQCOEFF_in[17] = (PIPETX04EQCOEFF[17] !== 1'bz) && PIPETX04EQCOEFF[17]; // rv 0 + assign PIPETX04EQCOEFF_in[1] = (PIPETX04EQCOEFF[1] !== 1'bz) && PIPETX04EQCOEFF[1]; // rv 0 + assign PIPETX04EQCOEFF_in[2] = (PIPETX04EQCOEFF[2] !== 1'bz) && PIPETX04EQCOEFF[2]; // rv 0 + assign PIPETX04EQCOEFF_in[3] = (PIPETX04EQCOEFF[3] !== 1'bz) && PIPETX04EQCOEFF[3]; // rv 0 + assign PIPETX04EQCOEFF_in[4] = (PIPETX04EQCOEFF[4] !== 1'bz) && PIPETX04EQCOEFF[4]; // rv 0 + assign PIPETX04EQCOEFF_in[5] = (PIPETX04EQCOEFF[5] !== 1'bz) && PIPETX04EQCOEFF[5]; // rv 0 + assign PIPETX04EQCOEFF_in[6] = (PIPETX04EQCOEFF[6] !== 1'bz) && PIPETX04EQCOEFF[6]; // rv 0 + assign PIPETX04EQCOEFF_in[7] = (PIPETX04EQCOEFF[7] !== 1'bz) && PIPETX04EQCOEFF[7]; // rv 0 + assign PIPETX04EQCOEFF_in[8] = (PIPETX04EQCOEFF[8] !== 1'bz) && PIPETX04EQCOEFF[8]; // rv 0 + assign PIPETX04EQCOEFF_in[9] = (PIPETX04EQCOEFF[9] !== 1'bz) && PIPETX04EQCOEFF[9]; // rv 0 + assign PIPETX04EQDONE_in = (PIPETX04EQDONE !== 1'bz) && PIPETX04EQDONE; // rv 0 + assign PIPETX05EQCOEFF_in[0] = (PIPETX05EQCOEFF[0] !== 1'bz) && PIPETX05EQCOEFF[0]; // rv 0 + assign PIPETX05EQCOEFF_in[10] = (PIPETX05EQCOEFF[10] !== 1'bz) && PIPETX05EQCOEFF[10]; // rv 0 + assign PIPETX05EQCOEFF_in[11] = (PIPETX05EQCOEFF[11] !== 1'bz) && PIPETX05EQCOEFF[11]; // rv 0 + assign PIPETX05EQCOEFF_in[12] = (PIPETX05EQCOEFF[12] !== 1'bz) && PIPETX05EQCOEFF[12]; // rv 0 + assign PIPETX05EQCOEFF_in[13] = (PIPETX05EQCOEFF[13] !== 1'bz) && PIPETX05EQCOEFF[13]; // rv 0 + assign PIPETX05EQCOEFF_in[14] = (PIPETX05EQCOEFF[14] !== 1'bz) && PIPETX05EQCOEFF[14]; // rv 0 + assign PIPETX05EQCOEFF_in[15] = (PIPETX05EQCOEFF[15] !== 1'bz) && PIPETX05EQCOEFF[15]; // rv 0 + assign PIPETX05EQCOEFF_in[16] = (PIPETX05EQCOEFF[16] !== 1'bz) && PIPETX05EQCOEFF[16]; // rv 0 + assign PIPETX05EQCOEFF_in[17] = (PIPETX05EQCOEFF[17] !== 1'bz) && PIPETX05EQCOEFF[17]; // rv 0 + assign PIPETX05EQCOEFF_in[1] = (PIPETX05EQCOEFF[1] !== 1'bz) && PIPETX05EQCOEFF[1]; // rv 0 + assign PIPETX05EQCOEFF_in[2] = (PIPETX05EQCOEFF[2] !== 1'bz) && PIPETX05EQCOEFF[2]; // rv 0 + assign PIPETX05EQCOEFF_in[3] = (PIPETX05EQCOEFF[3] !== 1'bz) && PIPETX05EQCOEFF[3]; // rv 0 + assign PIPETX05EQCOEFF_in[4] = (PIPETX05EQCOEFF[4] !== 1'bz) && PIPETX05EQCOEFF[4]; // rv 0 + assign PIPETX05EQCOEFF_in[5] = (PIPETX05EQCOEFF[5] !== 1'bz) && PIPETX05EQCOEFF[5]; // rv 0 + assign PIPETX05EQCOEFF_in[6] = (PIPETX05EQCOEFF[6] !== 1'bz) && PIPETX05EQCOEFF[6]; // rv 0 + assign PIPETX05EQCOEFF_in[7] = (PIPETX05EQCOEFF[7] !== 1'bz) && PIPETX05EQCOEFF[7]; // rv 0 + assign PIPETX05EQCOEFF_in[8] = (PIPETX05EQCOEFF[8] !== 1'bz) && PIPETX05EQCOEFF[8]; // rv 0 + assign PIPETX05EQCOEFF_in[9] = (PIPETX05EQCOEFF[9] !== 1'bz) && PIPETX05EQCOEFF[9]; // rv 0 + assign PIPETX05EQDONE_in = (PIPETX05EQDONE !== 1'bz) && PIPETX05EQDONE; // rv 0 + assign PIPETX06EQCOEFF_in[0] = (PIPETX06EQCOEFF[0] !== 1'bz) && PIPETX06EQCOEFF[0]; // rv 0 + assign PIPETX06EQCOEFF_in[10] = (PIPETX06EQCOEFF[10] !== 1'bz) && PIPETX06EQCOEFF[10]; // rv 0 + assign PIPETX06EQCOEFF_in[11] = (PIPETX06EQCOEFF[11] !== 1'bz) && PIPETX06EQCOEFF[11]; // rv 0 + assign PIPETX06EQCOEFF_in[12] = (PIPETX06EQCOEFF[12] !== 1'bz) && PIPETX06EQCOEFF[12]; // rv 0 + assign PIPETX06EQCOEFF_in[13] = (PIPETX06EQCOEFF[13] !== 1'bz) && PIPETX06EQCOEFF[13]; // rv 0 + assign PIPETX06EQCOEFF_in[14] = (PIPETX06EQCOEFF[14] !== 1'bz) && PIPETX06EQCOEFF[14]; // rv 0 + assign PIPETX06EQCOEFF_in[15] = (PIPETX06EQCOEFF[15] !== 1'bz) && PIPETX06EQCOEFF[15]; // rv 0 + assign PIPETX06EQCOEFF_in[16] = (PIPETX06EQCOEFF[16] !== 1'bz) && PIPETX06EQCOEFF[16]; // rv 0 + assign PIPETX06EQCOEFF_in[17] = (PIPETX06EQCOEFF[17] !== 1'bz) && PIPETX06EQCOEFF[17]; // rv 0 + assign PIPETX06EQCOEFF_in[1] = (PIPETX06EQCOEFF[1] !== 1'bz) && PIPETX06EQCOEFF[1]; // rv 0 + assign PIPETX06EQCOEFF_in[2] = (PIPETX06EQCOEFF[2] !== 1'bz) && PIPETX06EQCOEFF[2]; // rv 0 + assign PIPETX06EQCOEFF_in[3] = (PIPETX06EQCOEFF[3] !== 1'bz) && PIPETX06EQCOEFF[3]; // rv 0 + assign PIPETX06EQCOEFF_in[4] = (PIPETX06EQCOEFF[4] !== 1'bz) && PIPETX06EQCOEFF[4]; // rv 0 + assign PIPETX06EQCOEFF_in[5] = (PIPETX06EQCOEFF[5] !== 1'bz) && PIPETX06EQCOEFF[5]; // rv 0 + assign PIPETX06EQCOEFF_in[6] = (PIPETX06EQCOEFF[6] !== 1'bz) && PIPETX06EQCOEFF[6]; // rv 0 + assign PIPETX06EQCOEFF_in[7] = (PIPETX06EQCOEFF[7] !== 1'bz) && PIPETX06EQCOEFF[7]; // rv 0 + assign PIPETX06EQCOEFF_in[8] = (PIPETX06EQCOEFF[8] !== 1'bz) && PIPETX06EQCOEFF[8]; // rv 0 + assign PIPETX06EQCOEFF_in[9] = (PIPETX06EQCOEFF[9] !== 1'bz) && PIPETX06EQCOEFF[9]; // rv 0 + assign PIPETX06EQDONE_in = (PIPETX06EQDONE !== 1'bz) && PIPETX06EQDONE; // rv 0 + assign PIPETX07EQCOEFF_in[0] = (PIPETX07EQCOEFF[0] !== 1'bz) && PIPETX07EQCOEFF[0]; // rv 0 + assign PIPETX07EQCOEFF_in[10] = (PIPETX07EQCOEFF[10] !== 1'bz) && PIPETX07EQCOEFF[10]; // rv 0 + assign PIPETX07EQCOEFF_in[11] = (PIPETX07EQCOEFF[11] !== 1'bz) && PIPETX07EQCOEFF[11]; // rv 0 + assign PIPETX07EQCOEFF_in[12] = (PIPETX07EQCOEFF[12] !== 1'bz) && PIPETX07EQCOEFF[12]; // rv 0 + assign PIPETX07EQCOEFF_in[13] = (PIPETX07EQCOEFF[13] !== 1'bz) && PIPETX07EQCOEFF[13]; // rv 0 + assign PIPETX07EQCOEFF_in[14] = (PIPETX07EQCOEFF[14] !== 1'bz) && PIPETX07EQCOEFF[14]; // rv 0 + assign PIPETX07EQCOEFF_in[15] = (PIPETX07EQCOEFF[15] !== 1'bz) && PIPETX07EQCOEFF[15]; // rv 0 + assign PIPETX07EQCOEFF_in[16] = (PIPETX07EQCOEFF[16] !== 1'bz) && PIPETX07EQCOEFF[16]; // rv 0 + assign PIPETX07EQCOEFF_in[17] = (PIPETX07EQCOEFF[17] !== 1'bz) && PIPETX07EQCOEFF[17]; // rv 0 + assign PIPETX07EQCOEFF_in[1] = (PIPETX07EQCOEFF[1] !== 1'bz) && PIPETX07EQCOEFF[1]; // rv 0 + assign PIPETX07EQCOEFF_in[2] = (PIPETX07EQCOEFF[2] !== 1'bz) && PIPETX07EQCOEFF[2]; // rv 0 + assign PIPETX07EQCOEFF_in[3] = (PIPETX07EQCOEFF[3] !== 1'bz) && PIPETX07EQCOEFF[3]; // rv 0 + assign PIPETX07EQCOEFF_in[4] = (PIPETX07EQCOEFF[4] !== 1'bz) && PIPETX07EQCOEFF[4]; // rv 0 + assign PIPETX07EQCOEFF_in[5] = (PIPETX07EQCOEFF[5] !== 1'bz) && PIPETX07EQCOEFF[5]; // rv 0 + assign PIPETX07EQCOEFF_in[6] = (PIPETX07EQCOEFF[6] !== 1'bz) && PIPETX07EQCOEFF[6]; // rv 0 + assign PIPETX07EQCOEFF_in[7] = (PIPETX07EQCOEFF[7] !== 1'bz) && PIPETX07EQCOEFF[7]; // rv 0 + assign PIPETX07EQCOEFF_in[8] = (PIPETX07EQCOEFF[8] !== 1'bz) && PIPETX07EQCOEFF[8]; // rv 0 + assign PIPETX07EQCOEFF_in[9] = (PIPETX07EQCOEFF[9] !== 1'bz) && PIPETX07EQCOEFF[9]; // rv 0 + assign PIPETX07EQDONE_in = (PIPETX07EQDONE !== 1'bz) && PIPETX07EQDONE; // rv 0 + assign PIPETX08EQCOEFF_in[0] = (PIPETX08EQCOEFF[0] !== 1'bz) && PIPETX08EQCOEFF[0]; // rv 0 + assign PIPETX08EQCOEFF_in[10] = (PIPETX08EQCOEFF[10] !== 1'bz) && PIPETX08EQCOEFF[10]; // rv 0 + assign PIPETX08EQCOEFF_in[11] = (PIPETX08EQCOEFF[11] !== 1'bz) && PIPETX08EQCOEFF[11]; // rv 0 + assign PIPETX08EQCOEFF_in[12] = (PIPETX08EQCOEFF[12] !== 1'bz) && PIPETX08EQCOEFF[12]; // rv 0 + assign PIPETX08EQCOEFF_in[13] = (PIPETX08EQCOEFF[13] !== 1'bz) && PIPETX08EQCOEFF[13]; // rv 0 + assign PIPETX08EQCOEFF_in[14] = (PIPETX08EQCOEFF[14] !== 1'bz) && PIPETX08EQCOEFF[14]; // rv 0 + assign PIPETX08EQCOEFF_in[15] = (PIPETX08EQCOEFF[15] !== 1'bz) && PIPETX08EQCOEFF[15]; // rv 0 + assign PIPETX08EQCOEFF_in[16] = (PIPETX08EQCOEFF[16] !== 1'bz) && PIPETX08EQCOEFF[16]; // rv 0 + assign PIPETX08EQCOEFF_in[17] = (PIPETX08EQCOEFF[17] !== 1'bz) && PIPETX08EQCOEFF[17]; // rv 0 + assign PIPETX08EQCOEFF_in[1] = (PIPETX08EQCOEFF[1] !== 1'bz) && PIPETX08EQCOEFF[1]; // rv 0 + assign PIPETX08EQCOEFF_in[2] = (PIPETX08EQCOEFF[2] !== 1'bz) && PIPETX08EQCOEFF[2]; // rv 0 + assign PIPETX08EQCOEFF_in[3] = (PIPETX08EQCOEFF[3] !== 1'bz) && PIPETX08EQCOEFF[3]; // rv 0 + assign PIPETX08EQCOEFF_in[4] = (PIPETX08EQCOEFF[4] !== 1'bz) && PIPETX08EQCOEFF[4]; // rv 0 + assign PIPETX08EQCOEFF_in[5] = (PIPETX08EQCOEFF[5] !== 1'bz) && PIPETX08EQCOEFF[5]; // rv 0 + assign PIPETX08EQCOEFF_in[6] = (PIPETX08EQCOEFF[6] !== 1'bz) && PIPETX08EQCOEFF[6]; // rv 0 + assign PIPETX08EQCOEFF_in[7] = (PIPETX08EQCOEFF[7] !== 1'bz) && PIPETX08EQCOEFF[7]; // rv 0 + assign PIPETX08EQCOEFF_in[8] = (PIPETX08EQCOEFF[8] !== 1'bz) && PIPETX08EQCOEFF[8]; // rv 0 + assign PIPETX08EQCOEFF_in[9] = (PIPETX08EQCOEFF[9] !== 1'bz) && PIPETX08EQCOEFF[9]; // rv 0 + assign PIPETX08EQDONE_in = (PIPETX08EQDONE !== 1'bz) && PIPETX08EQDONE; // rv 0 + assign PIPETX09EQCOEFF_in[0] = (PIPETX09EQCOEFF[0] !== 1'bz) && PIPETX09EQCOEFF[0]; // rv 0 + assign PIPETX09EQCOEFF_in[10] = (PIPETX09EQCOEFF[10] !== 1'bz) && PIPETX09EQCOEFF[10]; // rv 0 + assign PIPETX09EQCOEFF_in[11] = (PIPETX09EQCOEFF[11] !== 1'bz) && PIPETX09EQCOEFF[11]; // rv 0 + assign PIPETX09EQCOEFF_in[12] = (PIPETX09EQCOEFF[12] !== 1'bz) && PIPETX09EQCOEFF[12]; // rv 0 + assign PIPETX09EQCOEFF_in[13] = (PIPETX09EQCOEFF[13] !== 1'bz) && PIPETX09EQCOEFF[13]; // rv 0 + assign PIPETX09EQCOEFF_in[14] = (PIPETX09EQCOEFF[14] !== 1'bz) && PIPETX09EQCOEFF[14]; // rv 0 + assign PIPETX09EQCOEFF_in[15] = (PIPETX09EQCOEFF[15] !== 1'bz) && PIPETX09EQCOEFF[15]; // rv 0 + assign PIPETX09EQCOEFF_in[16] = (PIPETX09EQCOEFF[16] !== 1'bz) && PIPETX09EQCOEFF[16]; // rv 0 + assign PIPETX09EQCOEFF_in[17] = (PIPETX09EQCOEFF[17] !== 1'bz) && PIPETX09EQCOEFF[17]; // rv 0 + assign PIPETX09EQCOEFF_in[1] = (PIPETX09EQCOEFF[1] !== 1'bz) && PIPETX09EQCOEFF[1]; // rv 0 + assign PIPETX09EQCOEFF_in[2] = (PIPETX09EQCOEFF[2] !== 1'bz) && PIPETX09EQCOEFF[2]; // rv 0 + assign PIPETX09EQCOEFF_in[3] = (PIPETX09EQCOEFF[3] !== 1'bz) && PIPETX09EQCOEFF[3]; // rv 0 + assign PIPETX09EQCOEFF_in[4] = (PIPETX09EQCOEFF[4] !== 1'bz) && PIPETX09EQCOEFF[4]; // rv 0 + assign PIPETX09EQCOEFF_in[5] = (PIPETX09EQCOEFF[5] !== 1'bz) && PIPETX09EQCOEFF[5]; // rv 0 + assign PIPETX09EQCOEFF_in[6] = (PIPETX09EQCOEFF[6] !== 1'bz) && PIPETX09EQCOEFF[6]; // rv 0 + assign PIPETX09EQCOEFF_in[7] = (PIPETX09EQCOEFF[7] !== 1'bz) && PIPETX09EQCOEFF[7]; // rv 0 + assign PIPETX09EQCOEFF_in[8] = (PIPETX09EQCOEFF[8] !== 1'bz) && PIPETX09EQCOEFF[8]; // rv 0 + assign PIPETX09EQCOEFF_in[9] = (PIPETX09EQCOEFF[9] !== 1'bz) && PIPETX09EQCOEFF[9]; // rv 0 + assign PIPETX09EQDONE_in = (PIPETX09EQDONE !== 1'bz) && PIPETX09EQDONE; // rv 0 + assign PIPETX10EQCOEFF_in[0] = (PIPETX10EQCOEFF[0] !== 1'bz) && PIPETX10EQCOEFF[0]; // rv 0 + assign PIPETX10EQCOEFF_in[10] = (PIPETX10EQCOEFF[10] !== 1'bz) && PIPETX10EQCOEFF[10]; // rv 0 + assign PIPETX10EQCOEFF_in[11] = (PIPETX10EQCOEFF[11] !== 1'bz) && PIPETX10EQCOEFF[11]; // rv 0 + assign PIPETX10EQCOEFF_in[12] = (PIPETX10EQCOEFF[12] !== 1'bz) && PIPETX10EQCOEFF[12]; // rv 0 + assign PIPETX10EQCOEFF_in[13] = (PIPETX10EQCOEFF[13] !== 1'bz) && PIPETX10EQCOEFF[13]; // rv 0 + assign PIPETX10EQCOEFF_in[14] = (PIPETX10EQCOEFF[14] !== 1'bz) && PIPETX10EQCOEFF[14]; // rv 0 + assign PIPETX10EQCOEFF_in[15] = (PIPETX10EQCOEFF[15] !== 1'bz) && PIPETX10EQCOEFF[15]; // rv 0 + assign PIPETX10EQCOEFF_in[16] = (PIPETX10EQCOEFF[16] !== 1'bz) && PIPETX10EQCOEFF[16]; // rv 0 + assign PIPETX10EQCOEFF_in[17] = (PIPETX10EQCOEFF[17] !== 1'bz) && PIPETX10EQCOEFF[17]; // rv 0 + assign PIPETX10EQCOEFF_in[1] = (PIPETX10EQCOEFF[1] !== 1'bz) && PIPETX10EQCOEFF[1]; // rv 0 + assign PIPETX10EQCOEFF_in[2] = (PIPETX10EQCOEFF[2] !== 1'bz) && PIPETX10EQCOEFF[2]; // rv 0 + assign PIPETX10EQCOEFF_in[3] = (PIPETX10EQCOEFF[3] !== 1'bz) && PIPETX10EQCOEFF[3]; // rv 0 + assign PIPETX10EQCOEFF_in[4] = (PIPETX10EQCOEFF[4] !== 1'bz) && PIPETX10EQCOEFF[4]; // rv 0 + assign PIPETX10EQCOEFF_in[5] = (PIPETX10EQCOEFF[5] !== 1'bz) && PIPETX10EQCOEFF[5]; // rv 0 + assign PIPETX10EQCOEFF_in[6] = (PIPETX10EQCOEFF[6] !== 1'bz) && PIPETX10EQCOEFF[6]; // rv 0 + assign PIPETX10EQCOEFF_in[7] = (PIPETX10EQCOEFF[7] !== 1'bz) && PIPETX10EQCOEFF[7]; // rv 0 + assign PIPETX10EQCOEFF_in[8] = (PIPETX10EQCOEFF[8] !== 1'bz) && PIPETX10EQCOEFF[8]; // rv 0 + assign PIPETX10EQCOEFF_in[9] = (PIPETX10EQCOEFF[9] !== 1'bz) && PIPETX10EQCOEFF[9]; // rv 0 + assign PIPETX10EQDONE_in = (PIPETX10EQDONE !== 1'bz) && PIPETX10EQDONE; // rv 0 + assign PIPETX11EQCOEFF_in[0] = (PIPETX11EQCOEFF[0] !== 1'bz) && PIPETX11EQCOEFF[0]; // rv 0 + assign PIPETX11EQCOEFF_in[10] = (PIPETX11EQCOEFF[10] !== 1'bz) && PIPETX11EQCOEFF[10]; // rv 0 + assign PIPETX11EQCOEFF_in[11] = (PIPETX11EQCOEFF[11] !== 1'bz) && PIPETX11EQCOEFF[11]; // rv 0 + assign PIPETX11EQCOEFF_in[12] = (PIPETX11EQCOEFF[12] !== 1'bz) && PIPETX11EQCOEFF[12]; // rv 0 + assign PIPETX11EQCOEFF_in[13] = (PIPETX11EQCOEFF[13] !== 1'bz) && PIPETX11EQCOEFF[13]; // rv 0 + assign PIPETX11EQCOEFF_in[14] = (PIPETX11EQCOEFF[14] !== 1'bz) && PIPETX11EQCOEFF[14]; // rv 0 + assign PIPETX11EQCOEFF_in[15] = (PIPETX11EQCOEFF[15] !== 1'bz) && PIPETX11EQCOEFF[15]; // rv 0 + assign PIPETX11EQCOEFF_in[16] = (PIPETX11EQCOEFF[16] !== 1'bz) && PIPETX11EQCOEFF[16]; // rv 0 + assign PIPETX11EQCOEFF_in[17] = (PIPETX11EQCOEFF[17] !== 1'bz) && PIPETX11EQCOEFF[17]; // rv 0 + assign PIPETX11EQCOEFF_in[1] = (PIPETX11EQCOEFF[1] !== 1'bz) && PIPETX11EQCOEFF[1]; // rv 0 + assign PIPETX11EQCOEFF_in[2] = (PIPETX11EQCOEFF[2] !== 1'bz) && PIPETX11EQCOEFF[2]; // rv 0 + assign PIPETX11EQCOEFF_in[3] = (PIPETX11EQCOEFF[3] !== 1'bz) && PIPETX11EQCOEFF[3]; // rv 0 + assign PIPETX11EQCOEFF_in[4] = (PIPETX11EQCOEFF[4] !== 1'bz) && PIPETX11EQCOEFF[4]; // rv 0 + assign PIPETX11EQCOEFF_in[5] = (PIPETX11EQCOEFF[5] !== 1'bz) && PIPETX11EQCOEFF[5]; // rv 0 + assign PIPETX11EQCOEFF_in[6] = (PIPETX11EQCOEFF[6] !== 1'bz) && PIPETX11EQCOEFF[6]; // rv 0 + assign PIPETX11EQCOEFF_in[7] = (PIPETX11EQCOEFF[7] !== 1'bz) && PIPETX11EQCOEFF[7]; // rv 0 + assign PIPETX11EQCOEFF_in[8] = (PIPETX11EQCOEFF[8] !== 1'bz) && PIPETX11EQCOEFF[8]; // rv 0 + assign PIPETX11EQCOEFF_in[9] = (PIPETX11EQCOEFF[9] !== 1'bz) && PIPETX11EQCOEFF[9]; // rv 0 + assign PIPETX11EQDONE_in = (PIPETX11EQDONE !== 1'bz) && PIPETX11EQDONE; // rv 0 + assign PIPETX12EQCOEFF_in[0] = (PIPETX12EQCOEFF[0] !== 1'bz) && PIPETX12EQCOEFF[0]; // rv 0 + assign PIPETX12EQCOEFF_in[10] = (PIPETX12EQCOEFF[10] !== 1'bz) && PIPETX12EQCOEFF[10]; // rv 0 + assign PIPETX12EQCOEFF_in[11] = (PIPETX12EQCOEFF[11] !== 1'bz) && PIPETX12EQCOEFF[11]; // rv 0 + assign PIPETX12EQCOEFF_in[12] = (PIPETX12EQCOEFF[12] !== 1'bz) && PIPETX12EQCOEFF[12]; // rv 0 + assign PIPETX12EQCOEFF_in[13] = (PIPETX12EQCOEFF[13] !== 1'bz) && PIPETX12EQCOEFF[13]; // rv 0 + assign PIPETX12EQCOEFF_in[14] = (PIPETX12EQCOEFF[14] !== 1'bz) && PIPETX12EQCOEFF[14]; // rv 0 + assign PIPETX12EQCOEFF_in[15] = (PIPETX12EQCOEFF[15] !== 1'bz) && PIPETX12EQCOEFF[15]; // rv 0 + assign PIPETX12EQCOEFF_in[16] = (PIPETX12EQCOEFF[16] !== 1'bz) && PIPETX12EQCOEFF[16]; // rv 0 + assign PIPETX12EQCOEFF_in[17] = (PIPETX12EQCOEFF[17] !== 1'bz) && PIPETX12EQCOEFF[17]; // rv 0 + assign PIPETX12EQCOEFF_in[1] = (PIPETX12EQCOEFF[1] !== 1'bz) && PIPETX12EQCOEFF[1]; // rv 0 + assign PIPETX12EQCOEFF_in[2] = (PIPETX12EQCOEFF[2] !== 1'bz) && PIPETX12EQCOEFF[2]; // rv 0 + assign PIPETX12EQCOEFF_in[3] = (PIPETX12EQCOEFF[3] !== 1'bz) && PIPETX12EQCOEFF[3]; // rv 0 + assign PIPETX12EQCOEFF_in[4] = (PIPETX12EQCOEFF[4] !== 1'bz) && PIPETX12EQCOEFF[4]; // rv 0 + assign PIPETX12EQCOEFF_in[5] = (PIPETX12EQCOEFF[5] !== 1'bz) && PIPETX12EQCOEFF[5]; // rv 0 + assign PIPETX12EQCOEFF_in[6] = (PIPETX12EQCOEFF[6] !== 1'bz) && PIPETX12EQCOEFF[6]; // rv 0 + assign PIPETX12EQCOEFF_in[7] = (PIPETX12EQCOEFF[7] !== 1'bz) && PIPETX12EQCOEFF[7]; // rv 0 + assign PIPETX12EQCOEFF_in[8] = (PIPETX12EQCOEFF[8] !== 1'bz) && PIPETX12EQCOEFF[8]; // rv 0 + assign PIPETX12EQCOEFF_in[9] = (PIPETX12EQCOEFF[9] !== 1'bz) && PIPETX12EQCOEFF[9]; // rv 0 + assign PIPETX12EQDONE_in = (PIPETX12EQDONE !== 1'bz) && PIPETX12EQDONE; // rv 0 + assign PIPETX13EQCOEFF_in[0] = (PIPETX13EQCOEFF[0] !== 1'bz) && PIPETX13EQCOEFF[0]; // rv 0 + assign PIPETX13EQCOEFF_in[10] = (PIPETX13EQCOEFF[10] !== 1'bz) && PIPETX13EQCOEFF[10]; // rv 0 + assign PIPETX13EQCOEFF_in[11] = (PIPETX13EQCOEFF[11] !== 1'bz) && PIPETX13EQCOEFF[11]; // rv 0 + assign PIPETX13EQCOEFF_in[12] = (PIPETX13EQCOEFF[12] !== 1'bz) && PIPETX13EQCOEFF[12]; // rv 0 + assign PIPETX13EQCOEFF_in[13] = (PIPETX13EQCOEFF[13] !== 1'bz) && PIPETX13EQCOEFF[13]; // rv 0 + assign PIPETX13EQCOEFF_in[14] = (PIPETX13EQCOEFF[14] !== 1'bz) && PIPETX13EQCOEFF[14]; // rv 0 + assign PIPETX13EQCOEFF_in[15] = (PIPETX13EQCOEFF[15] !== 1'bz) && PIPETX13EQCOEFF[15]; // rv 0 + assign PIPETX13EQCOEFF_in[16] = (PIPETX13EQCOEFF[16] !== 1'bz) && PIPETX13EQCOEFF[16]; // rv 0 + assign PIPETX13EQCOEFF_in[17] = (PIPETX13EQCOEFF[17] !== 1'bz) && PIPETX13EQCOEFF[17]; // rv 0 + assign PIPETX13EQCOEFF_in[1] = (PIPETX13EQCOEFF[1] !== 1'bz) && PIPETX13EQCOEFF[1]; // rv 0 + assign PIPETX13EQCOEFF_in[2] = (PIPETX13EQCOEFF[2] !== 1'bz) && PIPETX13EQCOEFF[2]; // rv 0 + assign PIPETX13EQCOEFF_in[3] = (PIPETX13EQCOEFF[3] !== 1'bz) && PIPETX13EQCOEFF[3]; // rv 0 + assign PIPETX13EQCOEFF_in[4] = (PIPETX13EQCOEFF[4] !== 1'bz) && PIPETX13EQCOEFF[4]; // rv 0 + assign PIPETX13EQCOEFF_in[5] = (PIPETX13EQCOEFF[5] !== 1'bz) && PIPETX13EQCOEFF[5]; // rv 0 + assign PIPETX13EQCOEFF_in[6] = (PIPETX13EQCOEFF[6] !== 1'bz) && PIPETX13EQCOEFF[6]; // rv 0 + assign PIPETX13EQCOEFF_in[7] = (PIPETX13EQCOEFF[7] !== 1'bz) && PIPETX13EQCOEFF[7]; // rv 0 + assign PIPETX13EQCOEFF_in[8] = (PIPETX13EQCOEFF[8] !== 1'bz) && PIPETX13EQCOEFF[8]; // rv 0 + assign PIPETX13EQCOEFF_in[9] = (PIPETX13EQCOEFF[9] !== 1'bz) && PIPETX13EQCOEFF[9]; // rv 0 + assign PIPETX13EQDONE_in = (PIPETX13EQDONE !== 1'bz) && PIPETX13EQDONE; // rv 0 + assign PIPETX14EQCOEFF_in[0] = (PIPETX14EQCOEFF[0] !== 1'bz) && PIPETX14EQCOEFF[0]; // rv 0 + assign PIPETX14EQCOEFF_in[10] = (PIPETX14EQCOEFF[10] !== 1'bz) && PIPETX14EQCOEFF[10]; // rv 0 + assign PIPETX14EQCOEFF_in[11] = (PIPETX14EQCOEFF[11] !== 1'bz) && PIPETX14EQCOEFF[11]; // rv 0 + assign PIPETX14EQCOEFF_in[12] = (PIPETX14EQCOEFF[12] !== 1'bz) && PIPETX14EQCOEFF[12]; // rv 0 + assign PIPETX14EQCOEFF_in[13] = (PIPETX14EQCOEFF[13] !== 1'bz) && PIPETX14EQCOEFF[13]; // rv 0 + assign PIPETX14EQCOEFF_in[14] = (PIPETX14EQCOEFF[14] !== 1'bz) && PIPETX14EQCOEFF[14]; // rv 0 + assign PIPETX14EQCOEFF_in[15] = (PIPETX14EQCOEFF[15] !== 1'bz) && PIPETX14EQCOEFF[15]; // rv 0 + assign PIPETX14EQCOEFF_in[16] = (PIPETX14EQCOEFF[16] !== 1'bz) && PIPETX14EQCOEFF[16]; // rv 0 + assign PIPETX14EQCOEFF_in[17] = (PIPETX14EQCOEFF[17] !== 1'bz) && PIPETX14EQCOEFF[17]; // rv 0 + assign PIPETX14EQCOEFF_in[1] = (PIPETX14EQCOEFF[1] !== 1'bz) && PIPETX14EQCOEFF[1]; // rv 0 + assign PIPETX14EQCOEFF_in[2] = (PIPETX14EQCOEFF[2] !== 1'bz) && PIPETX14EQCOEFF[2]; // rv 0 + assign PIPETX14EQCOEFF_in[3] = (PIPETX14EQCOEFF[3] !== 1'bz) && PIPETX14EQCOEFF[3]; // rv 0 + assign PIPETX14EQCOEFF_in[4] = (PIPETX14EQCOEFF[4] !== 1'bz) && PIPETX14EQCOEFF[4]; // rv 0 + assign PIPETX14EQCOEFF_in[5] = (PIPETX14EQCOEFF[5] !== 1'bz) && PIPETX14EQCOEFF[5]; // rv 0 + assign PIPETX14EQCOEFF_in[6] = (PIPETX14EQCOEFF[6] !== 1'bz) && PIPETX14EQCOEFF[6]; // rv 0 + assign PIPETX14EQCOEFF_in[7] = (PIPETX14EQCOEFF[7] !== 1'bz) && PIPETX14EQCOEFF[7]; // rv 0 + assign PIPETX14EQCOEFF_in[8] = (PIPETX14EQCOEFF[8] !== 1'bz) && PIPETX14EQCOEFF[8]; // rv 0 + assign PIPETX14EQCOEFF_in[9] = (PIPETX14EQCOEFF[9] !== 1'bz) && PIPETX14EQCOEFF[9]; // rv 0 + assign PIPETX14EQDONE_in = (PIPETX14EQDONE !== 1'bz) && PIPETX14EQDONE; // rv 0 + assign PIPETX15EQCOEFF_in[0] = (PIPETX15EQCOEFF[0] !== 1'bz) && PIPETX15EQCOEFF[0]; // rv 0 + assign PIPETX15EQCOEFF_in[10] = (PIPETX15EQCOEFF[10] !== 1'bz) && PIPETX15EQCOEFF[10]; // rv 0 + assign PIPETX15EQCOEFF_in[11] = (PIPETX15EQCOEFF[11] !== 1'bz) && PIPETX15EQCOEFF[11]; // rv 0 + assign PIPETX15EQCOEFF_in[12] = (PIPETX15EQCOEFF[12] !== 1'bz) && PIPETX15EQCOEFF[12]; // rv 0 + assign PIPETX15EQCOEFF_in[13] = (PIPETX15EQCOEFF[13] !== 1'bz) && PIPETX15EQCOEFF[13]; // rv 0 + assign PIPETX15EQCOEFF_in[14] = (PIPETX15EQCOEFF[14] !== 1'bz) && PIPETX15EQCOEFF[14]; // rv 0 + assign PIPETX15EQCOEFF_in[15] = (PIPETX15EQCOEFF[15] !== 1'bz) && PIPETX15EQCOEFF[15]; // rv 0 + assign PIPETX15EQCOEFF_in[16] = (PIPETX15EQCOEFF[16] !== 1'bz) && PIPETX15EQCOEFF[16]; // rv 0 + assign PIPETX15EQCOEFF_in[17] = (PIPETX15EQCOEFF[17] !== 1'bz) && PIPETX15EQCOEFF[17]; // rv 0 + assign PIPETX15EQCOEFF_in[1] = (PIPETX15EQCOEFF[1] !== 1'bz) && PIPETX15EQCOEFF[1]; // rv 0 + assign PIPETX15EQCOEFF_in[2] = (PIPETX15EQCOEFF[2] !== 1'bz) && PIPETX15EQCOEFF[2]; // rv 0 + assign PIPETX15EQCOEFF_in[3] = (PIPETX15EQCOEFF[3] !== 1'bz) && PIPETX15EQCOEFF[3]; // rv 0 + assign PIPETX15EQCOEFF_in[4] = (PIPETX15EQCOEFF[4] !== 1'bz) && PIPETX15EQCOEFF[4]; // rv 0 + assign PIPETX15EQCOEFF_in[5] = (PIPETX15EQCOEFF[5] !== 1'bz) && PIPETX15EQCOEFF[5]; // rv 0 + assign PIPETX15EQCOEFF_in[6] = (PIPETX15EQCOEFF[6] !== 1'bz) && PIPETX15EQCOEFF[6]; // rv 0 + assign PIPETX15EQCOEFF_in[7] = (PIPETX15EQCOEFF[7] !== 1'bz) && PIPETX15EQCOEFF[7]; // rv 0 + assign PIPETX15EQCOEFF_in[8] = (PIPETX15EQCOEFF[8] !== 1'bz) && PIPETX15EQCOEFF[8]; // rv 0 + assign PIPETX15EQCOEFF_in[9] = (PIPETX15EQCOEFF[9] !== 1'bz) && PIPETX15EQCOEFF[9]; // rv 0 + assign PIPETX15EQDONE_in = (PIPETX15EQDONE !== 1'bz) && PIPETX15EQDONE; // rv 0 + assign PLGEN2UPSTREAMPREFERDEEMPH_in = (PLGEN2UPSTREAMPREFERDEEMPH !== 1'bz) && PLGEN2UPSTREAMPREFERDEEMPH; // rv 0 + assign PLGEN34REDOEQSPEED_in = (PLGEN34REDOEQSPEED !== 1'bz) && PLGEN34REDOEQSPEED; // rv 0 + assign PLGEN34REDOEQUALIZATION_in = (PLGEN34REDOEQUALIZATION !== 1'bz) && PLGEN34REDOEQUALIZATION; // rv 0 + assign SAXISCCIXTXTDATA_in[0] = (SAXISCCIXTXTDATA[0] !== 1'bz) && SAXISCCIXTXTDATA[0]; // rv 0 + assign SAXISCCIXTXTDATA_in[100] = (SAXISCCIXTXTDATA[100] !== 1'bz) && SAXISCCIXTXTDATA[100]; // rv 0 + assign SAXISCCIXTXTDATA_in[101] = (SAXISCCIXTXTDATA[101] !== 1'bz) && SAXISCCIXTXTDATA[101]; // rv 0 + assign SAXISCCIXTXTDATA_in[102] = (SAXISCCIXTXTDATA[102] !== 1'bz) && SAXISCCIXTXTDATA[102]; // rv 0 + assign SAXISCCIXTXTDATA_in[103] = (SAXISCCIXTXTDATA[103] !== 1'bz) && SAXISCCIXTXTDATA[103]; // rv 0 + assign SAXISCCIXTXTDATA_in[104] = (SAXISCCIXTXTDATA[104] !== 1'bz) && SAXISCCIXTXTDATA[104]; // rv 0 + assign SAXISCCIXTXTDATA_in[105] = (SAXISCCIXTXTDATA[105] !== 1'bz) && SAXISCCIXTXTDATA[105]; // rv 0 + assign SAXISCCIXTXTDATA_in[106] = (SAXISCCIXTXTDATA[106] !== 1'bz) && SAXISCCIXTXTDATA[106]; // rv 0 + assign SAXISCCIXTXTDATA_in[107] = (SAXISCCIXTXTDATA[107] !== 1'bz) && SAXISCCIXTXTDATA[107]; // rv 0 + assign SAXISCCIXTXTDATA_in[108] = (SAXISCCIXTXTDATA[108] !== 1'bz) && SAXISCCIXTXTDATA[108]; // rv 0 + assign SAXISCCIXTXTDATA_in[109] = (SAXISCCIXTXTDATA[109] !== 1'bz) && SAXISCCIXTXTDATA[109]; // rv 0 + assign SAXISCCIXTXTDATA_in[10] = (SAXISCCIXTXTDATA[10] !== 1'bz) && SAXISCCIXTXTDATA[10]; // rv 0 + assign SAXISCCIXTXTDATA_in[110] = (SAXISCCIXTXTDATA[110] !== 1'bz) && SAXISCCIXTXTDATA[110]; // rv 0 + assign SAXISCCIXTXTDATA_in[111] = (SAXISCCIXTXTDATA[111] !== 1'bz) && SAXISCCIXTXTDATA[111]; // rv 0 + assign SAXISCCIXTXTDATA_in[112] = (SAXISCCIXTXTDATA[112] !== 1'bz) && SAXISCCIXTXTDATA[112]; // rv 0 + assign SAXISCCIXTXTDATA_in[113] = (SAXISCCIXTXTDATA[113] !== 1'bz) && SAXISCCIXTXTDATA[113]; // rv 0 + assign SAXISCCIXTXTDATA_in[114] = (SAXISCCIXTXTDATA[114] !== 1'bz) && SAXISCCIXTXTDATA[114]; // rv 0 + assign SAXISCCIXTXTDATA_in[115] = (SAXISCCIXTXTDATA[115] !== 1'bz) && SAXISCCIXTXTDATA[115]; // rv 0 + assign SAXISCCIXTXTDATA_in[116] = (SAXISCCIXTXTDATA[116] !== 1'bz) && SAXISCCIXTXTDATA[116]; // rv 0 + assign SAXISCCIXTXTDATA_in[117] = (SAXISCCIXTXTDATA[117] !== 1'bz) && SAXISCCIXTXTDATA[117]; // rv 0 + assign SAXISCCIXTXTDATA_in[118] = (SAXISCCIXTXTDATA[118] !== 1'bz) && SAXISCCIXTXTDATA[118]; // rv 0 + assign SAXISCCIXTXTDATA_in[119] = (SAXISCCIXTXTDATA[119] !== 1'bz) && SAXISCCIXTXTDATA[119]; // rv 0 + assign SAXISCCIXTXTDATA_in[11] = (SAXISCCIXTXTDATA[11] !== 1'bz) && SAXISCCIXTXTDATA[11]; // rv 0 + assign SAXISCCIXTXTDATA_in[120] = (SAXISCCIXTXTDATA[120] !== 1'bz) && SAXISCCIXTXTDATA[120]; // rv 0 + assign SAXISCCIXTXTDATA_in[121] = (SAXISCCIXTXTDATA[121] !== 1'bz) && SAXISCCIXTXTDATA[121]; // rv 0 + assign SAXISCCIXTXTDATA_in[122] = (SAXISCCIXTXTDATA[122] !== 1'bz) && SAXISCCIXTXTDATA[122]; // rv 0 + assign SAXISCCIXTXTDATA_in[123] = (SAXISCCIXTXTDATA[123] !== 1'bz) && SAXISCCIXTXTDATA[123]; // rv 0 + assign SAXISCCIXTXTDATA_in[124] = (SAXISCCIXTXTDATA[124] !== 1'bz) && SAXISCCIXTXTDATA[124]; // rv 0 + assign SAXISCCIXTXTDATA_in[125] = (SAXISCCIXTXTDATA[125] !== 1'bz) && SAXISCCIXTXTDATA[125]; // rv 0 + assign SAXISCCIXTXTDATA_in[126] = (SAXISCCIXTXTDATA[126] !== 1'bz) && SAXISCCIXTXTDATA[126]; // rv 0 + assign SAXISCCIXTXTDATA_in[127] = (SAXISCCIXTXTDATA[127] !== 1'bz) && SAXISCCIXTXTDATA[127]; // rv 0 + assign SAXISCCIXTXTDATA_in[128] = (SAXISCCIXTXTDATA[128] !== 1'bz) && SAXISCCIXTXTDATA[128]; // rv 0 + assign SAXISCCIXTXTDATA_in[129] = (SAXISCCIXTXTDATA[129] !== 1'bz) && SAXISCCIXTXTDATA[129]; // rv 0 + assign SAXISCCIXTXTDATA_in[12] = (SAXISCCIXTXTDATA[12] !== 1'bz) && SAXISCCIXTXTDATA[12]; // rv 0 + assign SAXISCCIXTXTDATA_in[130] = (SAXISCCIXTXTDATA[130] !== 1'bz) && SAXISCCIXTXTDATA[130]; // rv 0 + assign SAXISCCIXTXTDATA_in[131] = (SAXISCCIXTXTDATA[131] !== 1'bz) && SAXISCCIXTXTDATA[131]; // rv 0 + assign SAXISCCIXTXTDATA_in[132] = (SAXISCCIXTXTDATA[132] !== 1'bz) && SAXISCCIXTXTDATA[132]; // rv 0 + assign SAXISCCIXTXTDATA_in[133] = (SAXISCCIXTXTDATA[133] !== 1'bz) && SAXISCCIXTXTDATA[133]; // rv 0 + assign SAXISCCIXTXTDATA_in[134] = (SAXISCCIXTXTDATA[134] !== 1'bz) && SAXISCCIXTXTDATA[134]; // rv 0 + assign SAXISCCIXTXTDATA_in[135] = (SAXISCCIXTXTDATA[135] !== 1'bz) && SAXISCCIXTXTDATA[135]; // rv 0 + assign SAXISCCIXTXTDATA_in[136] = (SAXISCCIXTXTDATA[136] !== 1'bz) && SAXISCCIXTXTDATA[136]; // rv 0 + assign SAXISCCIXTXTDATA_in[137] = (SAXISCCIXTXTDATA[137] !== 1'bz) && SAXISCCIXTXTDATA[137]; // rv 0 + assign SAXISCCIXTXTDATA_in[138] = (SAXISCCIXTXTDATA[138] !== 1'bz) && SAXISCCIXTXTDATA[138]; // rv 0 + assign SAXISCCIXTXTDATA_in[139] = (SAXISCCIXTXTDATA[139] !== 1'bz) && SAXISCCIXTXTDATA[139]; // rv 0 + assign SAXISCCIXTXTDATA_in[13] = (SAXISCCIXTXTDATA[13] !== 1'bz) && SAXISCCIXTXTDATA[13]; // rv 0 + assign SAXISCCIXTXTDATA_in[140] = (SAXISCCIXTXTDATA[140] !== 1'bz) && SAXISCCIXTXTDATA[140]; // rv 0 + assign SAXISCCIXTXTDATA_in[141] = (SAXISCCIXTXTDATA[141] !== 1'bz) && SAXISCCIXTXTDATA[141]; // rv 0 + assign SAXISCCIXTXTDATA_in[142] = (SAXISCCIXTXTDATA[142] !== 1'bz) && SAXISCCIXTXTDATA[142]; // rv 0 + assign SAXISCCIXTXTDATA_in[143] = (SAXISCCIXTXTDATA[143] !== 1'bz) && SAXISCCIXTXTDATA[143]; // rv 0 + assign SAXISCCIXTXTDATA_in[144] = (SAXISCCIXTXTDATA[144] !== 1'bz) && SAXISCCIXTXTDATA[144]; // rv 0 + assign SAXISCCIXTXTDATA_in[145] = (SAXISCCIXTXTDATA[145] !== 1'bz) && SAXISCCIXTXTDATA[145]; // rv 0 + assign SAXISCCIXTXTDATA_in[146] = (SAXISCCIXTXTDATA[146] !== 1'bz) && SAXISCCIXTXTDATA[146]; // rv 0 + assign SAXISCCIXTXTDATA_in[147] = (SAXISCCIXTXTDATA[147] !== 1'bz) && SAXISCCIXTXTDATA[147]; // rv 0 + assign SAXISCCIXTXTDATA_in[148] = (SAXISCCIXTXTDATA[148] !== 1'bz) && SAXISCCIXTXTDATA[148]; // rv 0 + assign SAXISCCIXTXTDATA_in[149] = (SAXISCCIXTXTDATA[149] !== 1'bz) && SAXISCCIXTXTDATA[149]; // rv 0 + assign SAXISCCIXTXTDATA_in[14] = (SAXISCCIXTXTDATA[14] !== 1'bz) && SAXISCCIXTXTDATA[14]; // rv 0 + assign SAXISCCIXTXTDATA_in[150] = (SAXISCCIXTXTDATA[150] !== 1'bz) && SAXISCCIXTXTDATA[150]; // rv 0 + assign SAXISCCIXTXTDATA_in[151] = (SAXISCCIXTXTDATA[151] !== 1'bz) && SAXISCCIXTXTDATA[151]; // rv 0 + assign SAXISCCIXTXTDATA_in[152] = (SAXISCCIXTXTDATA[152] !== 1'bz) && SAXISCCIXTXTDATA[152]; // rv 0 + assign SAXISCCIXTXTDATA_in[153] = (SAXISCCIXTXTDATA[153] !== 1'bz) && SAXISCCIXTXTDATA[153]; // rv 0 + assign SAXISCCIXTXTDATA_in[154] = (SAXISCCIXTXTDATA[154] !== 1'bz) && SAXISCCIXTXTDATA[154]; // rv 0 + assign SAXISCCIXTXTDATA_in[155] = (SAXISCCIXTXTDATA[155] !== 1'bz) && SAXISCCIXTXTDATA[155]; // rv 0 + assign SAXISCCIXTXTDATA_in[156] = (SAXISCCIXTXTDATA[156] !== 1'bz) && SAXISCCIXTXTDATA[156]; // rv 0 + assign SAXISCCIXTXTDATA_in[157] = (SAXISCCIXTXTDATA[157] !== 1'bz) && SAXISCCIXTXTDATA[157]; // rv 0 + assign SAXISCCIXTXTDATA_in[158] = (SAXISCCIXTXTDATA[158] !== 1'bz) && SAXISCCIXTXTDATA[158]; // rv 0 + assign SAXISCCIXTXTDATA_in[159] = (SAXISCCIXTXTDATA[159] !== 1'bz) && SAXISCCIXTXTDATA[159]; // rv 0 + assign SAXISCCIXTXTDATA_in[15] = (SAXISCCIXTXTDATA[15] !== 1'bz) && SAXISCCIXTXTDATA[15]; // rv 0 + assign SAXISCCIXTXTDATA_in[160] = (SAXISCCIXTXTDATA[160] !== 1'bz) && SAXISCCIXTXTDATA[160]; // rv 0 + assign SAXISCCIXTXTDATA_in[161] = (SAXISCCIXTXTDATA[161] !== 1'bz) && SAXISCCIXTXTDATA[161]; // rv 0 + assign SAXISCCIXTXTDATA_in[162] = (SAXISCCIXTXTDATA[162] !== 1'bz) && SAXISCCIXTXTDATA[162]; // rv 0 + assign SAXISCCIXTXTDATA_in[163] = (SAXISCCIXTXTDATA[163] !== 1'bz) && SAXISCCIXTXTDATA[163]; // rv 0 + assign SAXISCCIXTXTDATA_in[164] = (SAXISCCIXTXTDATA[164] !== 1'bz) && SAXISCCIXTXTDATA[164]; // rv 0 + assign SAXISCCIXTXTDATA_in[165] = (SAXISCCIXTXTDATA[165] !== 1'bz) && SAXISCCIXTXTDATA[165]; // rv 0 + assign SAXISCCIXTXTDATA_in[166] = (SAXISCCIXTXTDATA[166] !== 1'bz) && SAXISCCIXTXTDATA[166]; // rv 0 + assign SAXISCCIXTXTDATA_in[167] = (SAXISCCIXTXTDATA[167] !== 1'bz) && SAXISCCIXTXTDATA[167]; // rv 0 + assign SAXISCCIXTXTDATA_in[168] = (SAXISCCIXTXTDATA[168] !== 1'bz) && SAXISCCIXTXTDATA[168]; // rv 0 + assign SAXISCCIXTXTDATA_in[169] = (SAXISCCIXTXTDATA[169] !== 1'bz) && SAXISCCIXTXTDATA[169]; // rv 0 + assign SAXISCCIXTXTDATA_in[16] = (SAXISCCIXTXTDATA[16] !== 1'bz) && SAXISCCIXTXTDATA[16]; // rv 0 + assign SAXISCCIXTXTDATA_in[170] = (SAXISCCIXTXTDATA[170] !== 1'bz) && SAXISCCIXTXTDATA[170]; // rv 0 + assign SAXISCCIXTXTDATA_in[171] = (SAXISCCIXTXTDATA[171] !== 1'bz) && SAXISCCIXTXTDATA[171]; // rv 0 + assign SAXISCCIXTXTDATA_in[172] = (SAXISCCIXTXTDATA[172] !== 1'bz) && SAXISCCIXTXTDATA[172]; // rv 0 + assign SAXISCCIXTXTDATA_in[173] = (SAXISCCIXTXTDATA[173] !== 1'bz) && SAXISCCIXTXTDATA[173]; // rv 0 + assign SAXISCCIXTXTDATA_in[174] = (SAXISCCIXTXTDATA[174] !== 1'bz) && SAXISCCIXTXTDATA[174]; // rv 0 + assign SAXISCCIXTXTDATA_in[175] = (SAXISCCIXTXTDATA[175] !== 1'bz) && SAXISCCIXTXTDATA[175]; // rv 0 + assign SAXISCCIXTXTDATA_in[176] = (SAXISCCIXTXTDATA[176] !== 1'bz) && SAXISCCIXTXTDATA[176]; // rv 0 + assign SAXISCCIXTXTDATA_in[177] = (SAXISCCIXTXTDATA[177] !== 1'bz) && SAXISCCIXTXTDATA[177]; // rv 0 + assign SAXISCCIXTXTDATA_in[178] = (SAXISCCIXTXTDATA[178] !== 1'bz) && SAXISCCIXTXTDATA[178]; // rv 0 + assign SAXISCCIXTXTDATA_in[179] = (SAXISCCIXTXTDATA[179] !== 1'bz) && SAXISCCIXTXTDATA[179]; // rv 0 + assign SAXISCCIXTXTDATA_in[17] = (SAXISCCIXTXTDATA[17] !== 1'bz) && SAXISCCIXTXTDATA[17]; // rv 0 + assign SAXISCCIXTXTDATA_in[180] = (SAXISCCIXTXTDATA[180] !== 1'bz) && SAXISCCIXTXTDATA[180]; // rv 0 + assign SAXISCCIXTXTDATA_in[181] = (SAXISCCIXTXTDATA[181] !== 1'bz) && SAXISCCIXTXTDATA[181]; // rv 0 + assign SAXISCCIXTXTDATA_in[182] = (SAXISCCIXTXTDATA[182] !== 1'bz) && SAXISCCIXTXTDATA[182]; // rv 0 + assign SAXISCCIXTXTDATA_in[183] = (SAXISCCIXTXTDATA[183] !== 1'bz) && SAXISCCIXTXTDATA[183]; // rv 0 + assign SAXISCCIXTXTDATA_in[184] = (SAXISCCIXTXTDATA[184] !== 1'bz) && SAXISCCIXTXTDATA[184]; // rv 0 + assign SAXISCCIXTXTDATA_in[185] = (SAXISCCIXTXTDATA[185] !== 1'bz) && SAXISCCIXTXTDATA[185]; // rv 0 + assign SAXISCCIXTXTDATA_in[186] = (SAXISCCIXTXTDATA[186] !== 1'bz) && SAXISCCIXTXTDATA[186]; // rv 0 + assign SAXISCCIXTXTDATA_in[187] = (SAXISCCIXTXTDATA[187] !== 1'bz) && SAXISCCIXTXTDATA[187]; // rv 0 + assign SAXISCCIXTXTDATA_in[188] = (SAXISCCIXTXTDATA[188] !== 1'bz) && SAXISCCIXTXTDATA[188]; // rv 0 + assign SAXISCCIXTXTDATA_in[189] = (SAXISCCIXTXTDATA[189] !== 1'bz) && SAXISCCIXTXTDATA[189]; // rv 0 + assign SAXISCCIXTXTDATA_in[18] = (SAXISCCIXTXTDATA[18] !== 1'bz) && SAXISCCIXTXTDATA[18]; // rv 0 + assign SAXISCCIXTXTDATA_in[190] = (SAXISCCIXTXTDATA[190] !== 1'bz) && SAXISCCIXTXTDATA[190]; // rv 0 + assign SAXISCCIXTXTDATA_in[191] = (SAXISCCIXTXTDATA[191] !== 1'bz) && SAXISCCIXTXTDATA[191]; // rv 0 + assign SAXISCCIXTXTDATA_in[192] = (SAXISCCIXTXTDATA[192] !== 1'bz) && SAXISCCIXTXTDATA[192]; // rv 0 + assign SAXISCCIXTXTDATA_in[193] = (SAXISCCIXTXTDATA[193] !== 1'bz) && SAXISCCIXTXTDATA[193]; // rv 0 + assign SAXISCCIXTXTDATA_in[194] = (SAXISCCIXTXTDATA[194] !== 1'bz) && SAXISCCIXTXTDATA[194]; // rv 0 + assign SAXISCCIXTXTDATA_in[195] = (SAXISCCIXTXTDATA[195] !== 1'bz) && SAXISCCIXTXTDATA[195]; // rv 0 + assign SAXISCCIXTXTDATA_in[196] = (SAXISCCIXTXTDATA[196] !== 1'bz) && SAXISCCIXTXTDATA[196]; // rv 0 + assign SAXISCCIXTXTDATA_in[197] = (SAXISCCIXTXTDATA[197] !== 1'bz) && SAXISCCIXTXTDATA[197]; // rv 0 + assign SAXISCCIXTXTDATA_in[198] = (SAXISCCIXTXTDATA[198] !== 1'bz) && SAXISCCIXTXTDATA[198]; // rv 0 + assign SAXISCCIXTXTDATA_in[199] = (SAXISCCIXTXTDATA[199] !== 1'bz) && SAXISCCIXTXTDATA[199]; // rv 0 + assign SAXISCCIXTXTDATA_in[19] = (SAXISCCIXTXTDATA[19] !== 1'bz) && SAXISCCIXTXTDATA[19]; // rv 0 + assign SAXISCCIXTXTDATA_in[1] = (SAXISCCIXTXTDATA[1] !== 1'bz) && SAXISCCIXTXTDATA[1]; // rv 0 + assign SAXISCCIXTXTDATA_in[200] = (SAXISCCIXTXTDATA[200] !== 1'bz) && SAXISCCIXTXTDATA[200]; // rv 0 + assign SAXISCCIXTXTDATA_in[201] = (SAXISCCIXTXTDATA[201] !== 1'bz) && SAXISCCIXTXTDATA[201]; // rv 0 + assign SAXISCCIXTXTDATA_in[202] = (SAXISCCIXTXTDATA[202] !== 1'bz) && SAXISCCIXTXTDATA[202]; // rv 0 + assign SAXISCCIXTXTDATA_in[203] = (SAXISCCIXTXTDATA[203] !== 1'bz) && SAXISCCIXTXTDATA[203]; // rv 0 + assign SAXISCCIXTXTDATA_in[204] = (SAXISCCIXTXTDATA[204] !== 1'bz) && SAXISCCIXTXTDATA[204]; // rv 0 + assign SAXISCCIXTXTDATA_in[205] = (SAXISCCIXTXTDATA[205] !== 1'bz) && SAXISCCIXTXTDATA[205]; // rv 0 + assign SAXISCCIXTXTDATA_in[206] = (SAXISCCIXTXTDATA[206] !== 1'bz) && SAXISCCIXTXTDATA[206]; // rv 0 + assign SAXISCCIXTXTDATA_in[207] = (SAXISCCIXTXTDATA[207] !== 1'bz) && SAXISCCIXTXTDATA[207]; // rv 0 + assign SAXISCCIXTXTDATA_in[208] = (SAXISCCIXTXTDATA[208] !== 1'bz) && SAXISCCIXTXTDATA[208]; // rv 0 + assign SAXISCCIXTXTDATA_in[209] = (SAXISCCIXTXTDATA[209] !== 1'bz) && SAXISCCIXTXTDATA[209]; // rv 0 + assign SAXISCCIXTXTDATA_in[20] = (SAXISCCIXTXTDATA[20] !== 1'bz) && SAXISCCIXTXTDATA[20]; // rv 0 + assign SAXISCCIXTXTDATA_in[210] = (SAXISCCIXTXTDATA[210] !== 1'bz) && SAXISCCIXTXTDATA[210]; // rv 0 + assign SAXISCCIXTXTDATA_in[211] = (SAXISCCIXTXTDATA[211] !== 1'bz) && SAXISCCIXTXTDATA[211]; // rv 0 + assign SAXISCCIXTXTDATA_in[212] = (SAXISCCIXTXTDATA[212] !== 1'bz) && SAXISCCIXTXTDATA[212]; // rv 0 + assign SAXISCCIXTXTDATA_in[213] = (SAXISCCIXTXTDATA[213] !== 1'bz) && SAXISCCIXTXTDATA[213]; // rv 0 + assign SAXISCCIXTXTDATA_in[214] = (SAXISCCIXTXTDATA[214] !== 1'bz) && SAXISCCIXTXTDATA[214]; // rv 0 + assign SAXISCCIXTXTDATA_in[215] = (SAXISCCIXTXTDATA[215] !== 1'bz) && SAXISCCIXTXTDATA[215]; // rv 0 + assign SAXISCCIXTXTDATA_in[216] = (SAXISCCIXTXTDATA[216] !== 1'bz) && SAXISCCIXTXTDATA[216]; // rv 0 + assign SAXISCCIXTXTDATA_in[217] = (SAXISCCIXTXTDATA[217] !== 1'bz) && SAXISCCIXTXTDATA[217]; // rv 0 + assign SAXISCCIXTXTDATA_in[218] = (SAXISCCIXTXTDATA[218] !== 1'bz) && SAXISCCIXTXTDATA[218]; // rv 0 + assign SAXISCCIXTXTDATA_in[219] = (SAXISCCIXTXTDATA[219] !== 1'bz) && SAXISCCIXTXTDATA[219]; // rv 0 + assign SAXISCCIXTXTDATA_in[21] = (SAXISCCIXTXTDATA[21] !== 1'bz) && SAXISCCIXTXTDATA[21]; // rv 0 + assign SAXISCCIXTXTDATA_in[220] = (SAXISCCIXTXTDATA[220] !== 1'bz) && SAXISCCIXTXTDATA[220]; // rv 0 + assign SAXISCCIXTXTDATA_in[221] = (SAXISCCIXTXTDATA[221] !== 1'bz) && SAXISCCIXTXTDATA[221]; // rv 0 + assign SAXISCCIXTXTDATA_in[222] = (SAXISCCIXTXTDATA[222] !== 1'bz) && SAXISCCIXTXTDATA[222]; // rv 0 + assign SAXISCCIXTXTDATA_in[223] = (SAXISCCIXTXTDATA[223] !== 1'bz) && SAXISCCIXTXTDATA[223]; // rv 0 + assign SAXISCCIXTXTDATA_in[224] = (SAXISCCIXTXTDATA[224] !== 1'bz) && SAXISCCIXTXTDATA[224]; // rv 0 + assign SAXISCCIXTXTDATA_in[225] = (SAXISCCIXTXTDATA[225] !== 1'bz) && SAXISCCIXTXTDATA[225]; // rv 0 + assign SAXISCCIXTXTDATA_in[226] = (SAXISCCIXTXTDATA[226] !== 1'bz) && SAXISCCIXTXTDATA[226]; // rv 0 + assign SAXISCCIXTXTDATA_in[227] = (SAXISCCIXTXTDATA[227] !== 1'bz) && SAXISCCIXTXTDATA[227]; // rv 0 + assign SAXISCCIXTXTDATA_in[228] = (SAXISCCIXTXTDATA[228] !== 1'bz) && SAXISCCIXTXTDATA[228]; // rv 0 + assign SAXISCCIXTXTDATA_in[229] = (SAXISCCIXTXTDATA[229] !== 1'bz) && SAXISCCIXTXTDATA[229]; // rv 0 + assign SAXISCCIXTXTDATA_in[22] = (SAXISCCIXTXTDATA[22] !== 1'bz) && SAXISCCIXTXTDATA[22]; // rv 0 + assign SAXISCCIXTXTDATA_in[230] = (SAXISCCIXTXTDATA[230] !== 1'bz) && SAXISCCIXTXTDATA[230]; // rv 0 + assign SAXISCCIXTXTDATA_in[231] = (SAXISCCIXTXTDATA[231] !== 1'bz) && SAXISCCIXTXTDATA[231]; // rv 0 + assign SAXISCCIXTXTDATA_in[232] = (SAXISCCIXTXTDATA[232] !== 1'bz) && SAXISCCIXTXTDATA[232]; // rv 0 + assign SAXISCCIXTXTDATA_in[233] = (SAXISCCIXTXTDATA[233] !== 1'bz) && SAXISCCIXTXTDATA[233]; // rv 0 + assign SAXISCCIXTXTDATA_in[234] = (SAXISCCIXTXTDATA[234] !== 1'bz) && SAXISCCIXTXTDATA[234]; // rv 0 + assign SAXISCCIXTXTDATA_in[235] = (SAXISCCIXTXTDATA[235] !== 1'bz) && SAXISCCIXTXTDATA[235]; // rv 0 + assign SAXISCCIXTXTDATA_in[236] = (SAXISCCIXTXTDATA[236] !== 1'bz) && SAXISCCIXTXTDATA[236]; // rv 0 + assign SAXISCCIXTXTDATA_in[237] = (SAXISCCIXTXTDATA[237] !== 1'bz) && SAXISCCIXTXTDATA[237]; // rv 0 + assign SAXISCCIXTXTDATA_in[238] = (SAXISCCIXTXTDATA[238] !== 1'bz) && SAXISCCIXTXTDATA[238]; // rv 0 + assign SAXISCCIXTXTDATA_in[239] = (SAXISCCIXTXTDATA[239] !== 1'bz) && SAXISCCIXTXTDATA[239]; // rv 0 + assign SAXISCCIXTXTDATA_in[23] = (SAXISCCIXTXTDATA[23] !== 1'bz) && SAXISCCIXTXTDATA[23]; // rv 0 + assign SAXISCCIXTXTDATA_in[240] = (SAXISCCIXTXTDATA[240] !== 1'bz) && SAXISCCIXTXTDATA[240]; // rv 0 + assign SAXISCCIXTXTDATA_in[241] = (SAXISCCIXTXTDATA[241] !== 1'bz) && SAXISCCIXTXTDATA[241]; // rv 0 + assign SAXISCCIXTXTDATA_in[242] = (SAXISCCIXTXTDATA[242] !== 1'bz) && SAXISCCIXTXTDATA[242]; // rv 0 + assign SAXISCCIXTXTDATA_in[243] = (SAXISCCIXTXTDATA[243] !== 1'bz) && SAXISCCIXTXTDATA[243]; // rv 0 + assign SAXISCCIXTXTDATA_in[244] = (SAXISCCIXTXTDATA[244] !== 1'bz) && SAXISCCIXTXTDATA[244]; // rv 0 + assign SAXISCCIXTXTDATA_in[245] = (SAXISCCIXTXTDATA[245] !== 1'bz) && SAXISCCIXTXTDATA[245]; // rv 0 + assign SAXISCCIXTXTDATA_in[246] = (SAXISCCIXTXTDATA[246] !== 1'bz) && SAXISCCIXTXTDATA[246]; // rv 0 + assign SAXISCCIXTXTDATA_in[247] = (SAXISCCIXTXTDATA[247] !== 1'bz) && SAXISCCIXTXTDATA[247]; // rv 0 + assign SAXISCCIXTXTDATA_in[248] = (SAXISCCIXTXTDATA[248] !== 1'bz) && SAXISCCIXTXTDATA[248]; // rv 0 + assign SAXISCCIXTXTDATA_in[249] = (SAXISCCIXTXTDATA[249] !== 1'bz) && SAXISCCIXTXTDATA[249]; // rv 0 + assign SAXISCCIXTXTDATA_in[24] = (SAXISCCIXTXTDATA[24] !== 1'bz) && SAXISCCIXTXTDATA[24]; // rv 0 + assign SAXISCCIXTXTDATA_in[250] = (SAXISCCIXTXTDATA[250] !== 1'bz) && SAXISCCIXTXTDATA[250]; // rv 0 + assign SAXISCCIXTXTDATA_in[251] = (SAXISCCIXTXTDATA[251] !== 1'bz) && SAXISCCIXTXTDATA[251]; // rv 0 + assign SAXISCCIXTXTDATA_in[252] = (SAXISCCIXTXTDATA[252] !== 1'bz) && SAXISCCIXTXTDATA[252]; // rv 0 + assign SAXISCCIXTXTDATA_in[253] = (SAXISCCIXTXTDATA[253] !== 1'bz) && SAXISCCIXTXTDATA[253]; // rv 0 + assign SAXISCCIXTXTDATA_in[254] = (SAXISCCIXTXTDATA[254] !== 1'bz) && SAXISCCIXTXTDATA[254]; // rv 0 + assign SAXISCCIXTXTDATA_in[255] = (SAXISCCIXTXTDATA[255] !== 1'bz) && SAXISCCIXTXTDATA[255]; // rv 0 + assign SAXISCCIXTXTDATA_in[25] = (SAXISCCIXTXTDATA[25] !== 1'bz) && SAXISCCIXTXTDATA[25]; // rv 0 + assign SAXISCCIXTXTDATA_in[26] = (SAXISCCIXTXTDATA[26] !== 1'bz) && SAXISCCIXTXTDATA[26]; // rv 0 + assign SAXISCCIXTXTDATA_in[27] = (SAXISCCIXTXTDATA[27] !== 1'bz) && SAXISCCIXTXTDATA[27]; // rv 0 + assign SAXISCCIXTXTDATA_in[28] = (SAXISCCIXTXTDATA[28] !== 1'bz) && SAXISCCIXTXTDATA[28]; // rv 0 + assign SAXISCCIXTXTDATA_in[29] = (SAXISCCIXTXTDATA[29] !== 1'bz) && SAXISCCIXTXTDATA[29]; // rv 0 + assign SAXISCCIXTXTDATA_in[2] = (SAXISCCIXTXTDATA[2] !== 1'bz) && SAXISCCIXTXTDATA[2]; // rv 0 + assign SAXISCCIXTXTDATA_in[30] = (SAXISCCIXTXTDATA[30] !== 1'bz) && SAXISCCIXTXTDATA[30]; // rv 0 + assign SAXISCCIXTXTDATA_in[31] = (SAXISCCIXTXTDATA[31] !== 1'bz) && SAXISCCIXTXTDATA[31]; // rv 0 + assign SAXISCCIXTXTDATA_in[32] = (SAXISCCIXTXTDATA[32] !== 1'bz) && SAXISCCIXTXTDATA[32]; // rv 0 + assign SAXISCCIXTXTDATA_in[33] = (SAXISCCIXTXTDATA[33] !== 1'bz) && SAXISCCIXTXTDATA[33]; // rv 0 + assign SAXISCCIXTXTDATA_in[34] = (SAXISCCIXTXTDATA[34] !== 1'bz) && SAXISCCIXTXTDATA[34]; // rv 0 + assign SAXISCCIXTXTDATA_in[35] = (SAXISCCIXTXTDATA[35] !== 1'bz) && SAXISCCIXTXTDATA[35]; // rv 0 + assign SAXISCCIXTXTDATA_in[36] = (SAXISCCIXTXTDATA[36] !== 1'bz) && SAXISCCIXTXTDATA[36]; // rv 0 + assign SAXISCCIXTXTDATA_in[37] = (SAXISCCIXTXTDATA[37] !== 1'bz) && SAXISCCIXTXTDATA[37]; // rv 0 + assign SAXISCCIXTXTDATA_in[38] = (SAXISCCIXTXTDATA[38] !== 1'bz) && SAXISCCIXTXTDATA[38]; // rv 0 + assign SAXISCCIXTXTDATA_in[39] = (SAXISCCIXTXTDATA[39] !== 1'bz) && SAXISCCIXTXTDATA[39]; // rv 0 + assign SAXISCCIXTXTDATA_in[3] = (SAXISCCIXTXTDATA[3] !== 1'bz) && SAXISCCIXTXTDATA[3]; // rv 0 + assign SAXISCCIXTXTDATA_in[40] = (SAXISCCIXTXTDATA[40] !== 1'bz) && SAXISCCIXTXTDATA[40]; // rv 0 + assign SAXISCCIXTXTDATA_in[41] = (SAXISCCIXTXTDATA[41] !== 1'bz) && SAXISCCIXTXTDATA[41]; // rv 0 + assign SAXISCCIXTXTDATA_in[42] = (SAXISCCIXTXTDATA[42] !== 1'bz) && SAXISCCIXTXTDATA[42]; // rv 0 + assign SAXISCCIXTXTDATA_in[43] = (SAXISCCIXTXTDATA[43] !== 1'bz) && SAXISCCIXTXTDATA[43]; // rv 0 + assign SAXISCCIXTXTDATA_in[44] = (SAXISCCIXTXTDATA[44] !== 1'bz) && SAXISCCIXTXTDATA[44]; // rv 0 + assign SAXISCCIXTXTDATA_in[45] = (SAXISCCIXTXTDATA[45] !== 1'bz) && SAXISCCIXTXTDATA[45]; // rv 0 + assign SAXISCCIXTXTDATA_in[46] = (SAXISCCIXTXTDATA[46] !== 1'bz) && SAXISCCIXTXTDATA[46]; // rv 0 + assign SAXISCCIXTXTDATA_in[47] = (SAXISCCIXTXTDATA[47] !== 1'bz) && SAXISCCIXTXTDATA[47]; // rv 0 + assign SAXISCCIXTXTDATA_in[48] = (SAXISCCIXTXTDATA[48] !== 1'bz) && SAXISCCIXTXTDATA[48]; // rv 0 + assign SAXISCCIXTXTDATA_in[49] = (SAXISCCIXTXTDATA[49] !== 1'bz) && SAXISCCIXTXTDATA[49]; // rv 0 + assign SAXISCCIXTXTDATA_in[4] = (SAXISCCIXTXTDATA[4] !== 1'bz) && SAXISCCIXTXTDATA[4]; // rv 0 + assign SAXISCCIXTXTDATA_in[50] = (SAXISCCIXTXTDATA[50] !== 1'bz) && SAXISCCIXTXTDATA[50]; // rv 0 + assign SAXISCCIXTXTDATA_in[51] = (SAXISCCIXTXTDATA[51] !== 1'bz) && SAXISCCIXTXTDATA[51]; // rv 0 + assign SAXISCCIXTXTDATA_in[52] = (SAXISCCIXTXTDATA[52] !== 1'bz) && SAXISCCIXTXTDATA[52]; // rv 0 + assign SAXISCCIXTXTDATA_in[53] = (SAXISCCIXTXTDATA[53] !== 1'bz) && SAXISCCIXTXTDATA[53]; // rv 0 + assign SAXISCCIXTXTDATA_in[54] = (SAXISCCIXTXTDATA[54] !== 1'bz) && SAXISCCIXTXTDATA[54]; // rv 0 + assign SAXISCCIXTXTDATA_in[55] = (SAXISCCIXTXTDATA[55] !== 1'bz) && SAXISCCIXTXTDATA[55]; // rv 0 + assign SAXISCCIXTXTDATA_in[56] = (SAXISCCIXTXTDATA[56] !== 1'bz) && SAXISCCIXTXTDATA[56]; // rv 0 + assign SAXISCCIXTXTDATA_in[57] = (SAXISCCIXTXTDATA[57] !== 1'bz) && SAXISCCIXTXTDATA[57]; // rv 0 + assign SAXISCCIXTXTDATA_in[58] = (SAXISCCIXTXTDATA[58] !== 1'bz) && SAXISCCIXTXTDATA[58]; // rv 0 + assign SAXISCCIXTXTDATA_in[59] = (SAXISCCIXTXTDATA[59] !== 1'bz) && SAXISCCIXTXTDATA[59]; // rv 0 + assign SAXISCCIXTXTDATA_in[5] = (SAXISCCIXTXTDATA[5] !== 1'bz) && SAXISCCIXTXTDATA[5]; // rv 0 + assign SAXISCCIXTXTDATA_in[60] = (SAXISCCIXTXTDATA[60] !== 1'bz) && SAXISCCIXTXTDATA[60]; // rv 0 + assign SAXISCCIXTXTDATA_in[61] = (SAXISCCIXTXTDATA[61] !== 1'bz) && SAXISCCIXTXTDATA[61]; // rv 0 + assign SAXISCCIXTXTDATA_in[62] = (SAXISCCIXTXTDATA[62] !== 1'bz) && SAXISCCIXTXTDATA[62]; // rv 0 + assign SAXISCCIXTXTDATA_in[63] = (SAXISCCIXTXTDATA[63] !== 1'bz) && SAXISCCIXTXTDATA[63]; // rv 0 + assign SAXISCCIXTXTDATA_in[64] = (SAXISCCIXTXTDATA[64] !== 1'bz) && SAXISCCIXTXTDATA[64]; // rv 0 + assign SAXISCCIXTXTDATA_in[65] = (SAXISCCIXTXTDATA[65] !== 1'bz) && SAXISCCIXTXTDATA[65]; // rv 0 + assign SAXISCCIXTXTDATA_in[66] = (SAXISCCIXTXTDATA[66] !== 1'bz) && SAXISCCIXTXTDATA[66]; // rv 0 + assign SAXISCCIXTXTDATA_in[67] = (SAXISCCIXTXTDATA[67] !== 1'bz) && SAXISCCIXTXTDATA[67]; // rv 0 + assign SAXISCCIXTXTDATA_in[68] = (SAXISCCIXTXTDATA[68] !== 1'bz) && SAXISCCIXTXTDATA[68]; // rv 0 + assign SAXISCCIXTXTDATA_in[69] = (SAXISCCIXTXTDATA[69] !== 1'bz) && SAXISCCIXTXTDATA[69]; // rv 0 + assign SAXISCCIXTXTDATA_in[6] = (SAXISCCIXTXTDATA[6] !== 1'bz) && SAXISCCIXTXTDATA[6]; // rv 0 + assign SAXISCCIXTXTDATA_in[70] = (SAXISCCIXTXTDATA[70] !== 1'bz) && SAXISCCIXTXTDATA[70]; // rv 0 + assign SAXISCCIXTXTDATA_in[71] = (SAXISCCIXTXTDATA[71] !== 1'bz) && SAXISCCIXTXTDATA[71]; // rv 0 + assign SAXISCCIXTXTDATA_in[72] = (SAXISCCIXTXTDATA[72] !== 1'bz) && SAXISCCIXTXTDATA[72]; // rv 0 + assign SAXISCCIXTXTDATA_in[73] = (SAXISCCIXTXTDATA[73] !== 1'bz) && SAXISCCIXTXTDATA[73]; // rv 0 + assign SAXISCCIXTXTDATA_in[74] = (SAXISCCIXTXTDATA[74] !== 1'bz) && SAXISCCIXTXTDATA[74]; // rv 0 + assign SAXISCCIXTXTDATA_in[75] = (SAXISCCIXTXTDATA[75] !== 1'bz) && SAXISCCIXTXTDATA[75]; // rv 0 + assign SAXISCCIXTXTDATA_in[76] = (SAXISCCIXTXTDATA[76] !== 1'bz) && SAXISCCIXTXTDATA[76]; // rv 0 + assign SAXISCCIXTXTDATA_in[77] = (SAXISCCIXTXTDATA[77] !== 1'bz) && SAXISCCIXTXTDATA[77]; // rv 0 + assign SAXISCCIXTXTDATA_in[78] = (SAXISCCIXTXTDATA[78] !== 1'bz) && SAXISCCIXTXTDATA[78]; // rv 0 + assign SAXISCCIXTXTDATA_in[79] = (SAXISCCIXTXTDATA[79] !== 1'bz) && SAXISCCIXTXTDATA[79]; // rv 0 + assign SAXISCCIXTXTDATA_in[7] = (SAXISCCIXTXTDATA[7] !== 1'bz) && SAXISCCIXTXTDATA[7]; // rv 0 + assign SAXISCCIXTXTDATA_in[80] = (SAXISCCIXTXTDATA[80] !== 1'bz) && SAXISCCIXTXTDATA[80]; // rv 0 + assign SAXISCCIXTXTDATA_in[81] = (SAXISCCIXTXTDATA[81] !== 1'bz) && SAXISCCIXTXTDATA[81]; // rv 0 + assign SAXISCCIXTXTDATA_in[82] = (SAXISCCIXTXTDATA[82] !== 1'bz) && SAXISCCIXTXTDATA[82]; // rv 0 + assign SAXISCCIXTXTDATA_in[83] = (SAXISCCIXTXTDATA[83] !== 1'bz) && SAXISCCIXTXTDATA[83]; // rv 0 + assign SAXISCCIXTXTDATA_in[84] = (SAXISCCIXTXTDATA[84] !== 1'bz) && SAXISCCIXTXTDATA[84]; // rv 0 + assign SAXISCCIXTXTDATA_in[85] = (SAXISCCIXTXTDATA[85] !== 1'bz) && SAXISCCIXTXTDATA[85]; // rv 0 + assign SAXISCCIXTXTDATA_in[86] = (SAXISCCIXTXTDATA[86] !== 1'bz) && SAXISCCIXTXTDATA[86]; // rv 0 + assign SAXISCCIXTXTDATA_in[87] = (SAXISCCIXTXTDATA[87] !== 1'bz) && SAXISCCIXTXTDATA[87]; // rv 0 + assign SAXISCCIXTXTDATA_in[88] = (SAXISCCIXTXTDATA[88] !== 1'bz) && SAXISCCIXTXTDATA[88]; // rv 0 + assign SAXISCCIXTXTDATA_in[89] = (SAXISCCIXTXTDATA[89] !== 1'bz) && SAXISCCIXTXTDATA[89]; // rv 0 + assign SAXISCCIXTXTDATA_in[8] = (SAXISCCIXTXTDATA[8] !== 1'bz) && SAXISCCIXTXTDATA[8]; // rv 0 + assign SAXISCCIXTXTDATA_in[90] = (SAXISCCIXTXTDATA[90] !== 1'bz) && SAXISCCIXTXTDATA[90]; // rv 0 + assign SAXISCCIXTXTDATA_in[91] = (SAXISCCIXTXTDATA[91] !== 1'bz) && SAXISCCIXTXTDATA[91]; // rv 0 + assign SAXISCCIXTXTDATA_in[92] = (SAXISCCIXTXTDATA[92] !== 1'bz) && SAXISCCIXTXTDATA[92]; // rv 0 + assign SAXISCCIXTXTDATA_in[93] = (SAXISCCIXTXTDATA[93] !== 1'bz) && SAXISCCIXTXTDATA[93]; // rv 0 + assign SAXISCCIXTXTDATA_in[94] = (SAXISCCIXTXTDATA[94] !== 1'bz) && SAXISCCIXTXTDATA[94]; // rv 0 + assign SAXISCCIXTXTDATA_in[95] = (SAXISCCIXTXTDATA[95] !== 1'bz) && SAXISCCIXTXTDATA[95]; // rv 0 + assign SAXISCCIXTXTDATA_in[96] = (SAXISCCIXTXTDATA[96] !== 1'bz) && SAXISCCIXTXTDATA[96]; // rv 0 + assign SAXISCCIXTXTDATA_in[97] = (SAXISCCIXTXTDATA[97] !== 1'bz) && SAXISCCIXTXTDATA[97]; // rv 0 + assign SAXISCCIXTXTDATA_in[98] = (SAXISCCIXTXTDATA[98] !== 1'bz) && SAXISCCIXTXTDATA[98]; // rv 0 + assign SAXISCCIXTXTDATA_in[99] = (SAXISCCIXTXTDATA[99] !== 1'bz) && SAXISCCIXTXTDATA[99]; // rv 0 + assign SAXISCCIXTXTDATA_in[9] = (SAXISCCIXTXTDATA[9] !== 1'bz) && SAXISCCIXTXTDATA[9]; // rv 0 + assign SAXISCCIXTXTUSER_in[0] = (SAXISCCIXTXTUSER[0] !== 1'bz) && SAXISCCIXTXTUSER[0]; // rv 0 + assign SAXISCCIXTXTUSER_in[10] = (SAXISCCIXTXTUSER[10] !== 1'bz) && SAXISCCIXTXTUSER[10]; // rv 0 + assign SAXISCCIXTXTUSER_in[11] = (SAXISCCIXTXTUSER[11] !== 1'bz) && SAXISCCIXTXTUSER[11]; // rv 0 + assign SAXISCCIXTXTUSER_in[12] = (SAXISCCIXTXTUSER[12] !== 1'bz) && SAXISCCIXTXTUSER[12]; // rv 0 + assign SAXISCCIXTXTUSER_in[13] = (SAXISCCIXTXTUSER[13] !== 1'bz) && SAXISCCIXTXTUSER[13]; // rv 0 + assign SAXISCCIXTXTUSER_in[14] = (SAXISCCIXTXTUSER[14] !== 1'bz) && SAXISCCIXTXTUSER[14]; // rv 0 + assign SAXISCCIXTXTUSER_in[15] = (SAXISCCIXTXTUSER[15] !== 1'bz) && SAXISCCIXTXTUSER[15]; // rv 0 + assign SAXISCCIXTXTUSER_in[16] = (SAXISCCIXTXTUSER[16] !== 1'bz) && SAXISCCIXTXTUSER[16]; // rv 0 + assign SAXISCCIXTXTUSER_in[17] = (SAXISCCIXTXTUSER[17] !== 1'bz) && SAXISCCIXTXTUSER[17]; // rv 0 + assign SAXISCCIXTXTUSER_in[18] = (SAXISCCIXTXTUSER[18] !== 1'bz) && SAXISCCIXTXTUSER[18]; // rv 0 + assign SAXISCCIXTXTUSER_in[19] = (SAXISCCIXTXTUSER[19] !== 1'bz) && SAXISCCIXTXTUSER[19]; // rv 0 + assign SAXISCCIXTXTUSER_in[1] = (SAXISCCIXTXTUSER[1] !== 1'bz) && SAXISCCIXTXTUSER[1]; // rv 0 + assign SAXISCCIXTXTUSER_in[20] = (SAXISCCIXTXTUSER[20] !== 1'bz) && SAXISCCIXTXTUSER[20]; // rv 0 + assign SAXISCCIXTXTUSER_in[21] = (SAXISCCIXTXTUSER[21] !== 1'bz) && SAXISCCIXTXTUSER[21]; // rv 0 + assign SAXISCCIXTXTUSER_in[22] = (SAXISCCIXTXTUSER[22] !== 1'bz) && SAXISCCIXTXTUSER[22]; // rv 0 + assign SAXISCCIXTXTUSER_in[23] = (SAXISCCIXTXTUSER[23] !== 1'bz) && SAXISCCIXTXTUSER[23]; // rv 0 + assign SAXISCCIXTXTUSER_in[24] = (SAXISCCIXTXTUSER[24] !== 1'bz) && SAXISCCIXTXTUSER[24]; // rv 0 + assign SAXISCCIXTXTUSER_in[25] = (SAXISCCIXTXTUSER[25] !== 1'bz) && SAXISCCIXTXTUSER[25]; // rv 0 + assign SAXISCCIXTXTUSER_in[26] = (SAXISCCIXTXTUSER[26] !== 1'bz) && SAXISCCIXTXTUSER[26]; // rv 0 + assign SAXISCCIXTXTUSER_in[27] = (SAXISCCIXTXTUSER[27] !== 1'bz) && SAXISCCIXTXTUSER[27]; // rv 0 + assign SAXISCCIXTXTUSER_in[28] = (SAXISCCIXTXTUSER[28] !== 1'bz) && SAXISCCIXTXTUSER[28]; // rv 0 + assign SAXISCCIXTXTUSER_in[29] = (SAXISCCIXTXTUSER[29] !== 1'bz) && SAXISCCIXTXTUSER[29]; // rv 0 + assign SAXISCCIXTXTUSER_in[2] = (SAXISCCIXTXTUSER[2] !== 1'bz) && SAXISCCIXTXTUSER[2]; // rv 0 + assign SAXISCCIXTXTUSER_in[30] = (SAXISCCIXTXTUSER[30] !== 1'bz) && SAXISCCIXTXTUSER[30]; // rv 0 + assign SAXISCCIXTXTUSER_in[31] = (SAXISCCIXTXTUSER[31] !== 1'bz) && SAXISCCIXTXTUSER[31]; // rv 0 + assign SAXISCCIXTXTUSER_in[32] = (SAXISCCIXTXTUSER[32] !== 1'bz) && SAXISCCIXTXTUSER[32]; // rv 0 + assign SAXISCCIXTXTUSER_in[33] = (SAXISCCIXTXTUSER[33] !== 1'bz) && SAXISCCIXTXTUSER[33]; // rv 0 + assign SAXISCCIXTXTUSER_in[34] = (SAXISCCIXTXTUSER[34] !== 1'bz) && SAXISCCIXTXTUSER[34]; // rv 0 + assign SAXISCCIXTXTUSER_in[35] = (SAXISCCIXTXTUSER[35] !== 1'bz) && SAXISCCIXTXTUSER[35]; // rv 0 + assign SAXISCCIXTXTUSER_in[36] = (SAXISCCIXTXTUSER[36] !== 1'bz) && SAXISCCIXTXTUSER[36]; // rv 0 + assign SAXISCCIXTXTUSER_in[37] = (SAXISCCIXTXTUSER[37] !== 1'bz) && SAXISCCIXTXTUSER[37]; // rv 0 + assign SAXISCCIXTXTUSER_in[38] = (SAXISCCIXTXTUSER[38] !== 1'bz) && SAXISCCIXTXTUSER[38]; // rv 0 + assign SAXISCCIXTXTUSER_in[39] = (SAXISCCIXTXTUSER[39] !== 1'bz) && SAXISCCIXTXTUSER[39]; // rv 0 + assign SAXISCCIXTXTUSER_in[3] = (SAXISCCIXTXTUSER[3] !== 1'bz) && SAXISCCIXTXTUSER[3]; // rv 0 + assign SAXISCCIXTXTUSER_in[40] = (SAXISCCIXTXTUSER[40] !== 1'bz) && SAXISCCIXTXTUSER[40]; // rv 0 + assign SAXISCCIXTXTUSER_in[41] = (SAXISCCIXTXTUSER[41] !== 1'bz) && SAXISCCIXTXTUSER[41]; // rv 0 + assign SAXISCCIXTXTUSER_in[42] = (SAXISCCIXTXTUSER[42] !== 1'bz) && SAXISCCIXTXTUSER[42]; // rv 0 + assign SAXISCCIXTXTUSER_in[43] = (SAXISCCIXTXTUSER[43] !== 1'bz) && SAXISCCIXTXTUSER[43]; // rv 0 + assign SAXISCCIXTXTUSER_in[44] = (SAXISCCIXTXTUSER[44] !== 1'bz) && SAXISCCIXTXTUSER[44]; // rv 0 + assign SAXISCCIXTXTUSER_in[45] = (SAXISCCIXTXTUSER[45] !== 1'bz) && SAXISCCIXTXTUSER[45]; // rv 0 + assign SAXISCCIXTXTUSER_in[4] = (SAXISCCIXTXTUSER[4] !== 1'bz) && SAXISCCIXTXTUSER[4]; // rv 0 + assign SAXISCCIXTXTUSER_in[5] = (SAXISCCIXTXTUSER[5] !== 1'bz) && SAXISCCIXTXTUSER[5]; // rv 0 + assign SAXISCCIXTXTUSER_in[6] = (SAXISCCIXTXTUSER[6] !== 1'bz) && SAXISCCIXTXTUSER[6]; // rv 0 + assign SAXISCCIXTXTUSER_in[7] = (SAXISCCIXTXTUSER[7] !== 1'bz) && SAXISCCIXTXTUSER[7]; // rv 0 + assign SAXISCCIXTXTUSER_in[8] = (SAXISCCIXTXTUSER[8] !== 1'bz) && SAXISCCIXTXTUSER[8]; // rv 0 + assign SAXISCCIXTXTUSER_in[9] = (SAXISCCIXTXTUSER[9] !== 1'bz) && SAXISCCIXTXTUSER[9]; // rv 0 + assign SAXISCCIXTXTVALID_in = (SAXISCCIXTXTVALID !== 1'bz) && SAXISCCIXTXTVALID; // rv 0 + assign SAXISCCTDATA_in[0] = (SAXISCCTDATA[0] === 1'bz) || SAXISCCTDATA[0]; // rv 1 + assign SAXISCCTDATA_in[100] = (SAXISCCTDATA[100] === 1'bz) || SAXISCCTDATA[100]; // rv 1 + assign SAXISCCTDATA_in[101] = (SAXISCCTDATA[101] === 1'bz) || SAXISCCTDATA[101]; // rv 1 + assign SAXISCCTDATA_in[102] = (SAXISCCTDATA[102] === 1'bz) || SAXISCCTDATA[102]; // rv 1 + assign SAXISCCTDATA_in[103] = (SAXISCCTDATA[103] === 1'bz) || SAXISCCTDATA[103]; // rv 1 + assign SAXISCCTDATA_in[104] = (SAXISCCTDATA[104] === 1'bz) || SAXISCCTDATA[104]; // rv 1 + assign SAXISCCTDATA_in[105] = (SAXISCCTDATA[105] === 1'bz) || SAXISCCTDATA[105]; // rv 1 + assign SAXISCCTDATA_in[106] = (SAXISCCTDATA[106] === 1'bz) || SAXISCCTDATA[106]; // rv 1 + assign SAXISCCTDATA_in[107] = (SAXISCCTDATA[107] === 1'bz) || SAXISCCTDATA[107]; // rv 1 + assign SAXISCCTDATA_in[108] = (SAXISCCTDATA[108] === 1'bz) || SAXISCCTDATA[108]; // rv 1 + assign SAXISCCTDATA_in[109] = (SAXISCCTDATA[109] === 1'bz) || SAXISCCTDATA[109]; // rv 1 + assign SAXISCCTDATA_in[10] = (SAXISCCTDATA[10] === 1'bz) || SAXISCCTDATA[10]; // rv 1 + assign SAXISCCTDATA_in[110] = (SAXISCCTDATA[110] === 1'bz) || SAXISCCTDATA[110]; // rv 1 + assign SAXISCCTDATA_in[111] = (SAXISCCTDATA[111] === 1'bz) || SAXISCCTDATA[111]; // rv 1 + assign SAXISCCTDATA_in[112] = (SAXISCCTDATA[112] === 1'bz) || SAXISCCTDATA[112]; // rv 1 + assign SAXISCCTDATA_in[113] = (SAXISCCTDATA[113] === 1'bz) || SAXISCCTDATA[113]; // rv 1 + assign SAXISCCTDATA_in[114] = (SAXISCCTDATA[114] === 1'bz) || SAXISCCTDATA[114]; // rv 1 + assign SAXISCCTDATA_in[115] = (SAXISCCTDATA[115] === 1'bz) || SAXISCCTDATA[115]; // rv 1 + assign SAXISCCTDATA_in[116] = (SAXISCCTDATA[116] === 1'bz) || SAXISCCTDATA[116]; // rv 1 + assign SAXISCCTDATA_in[117] = (SAXISCCTDATA[117] === 1'bz) || SAXISCCTDATA[117]; // rv 1 + assign SAXISCCTDATA_in[118] = (SAXISCCTDATA[118] === 1'bz) || SAXISCCTDATA[118]; // rv 1 + assign SAXISCCTDATA_in[119] = (SAXISCCTDATA[119] === 1'bz) || SAXISCCTDATA[119]; // rv 1 + assign SAXISCCTDATA_in[11] = (SAXISCCTDATA[11] === 1'bz) || SAXISCCTDATA[11]; // rv 1 + assign SAXISCCTDATA_in[120] = (SAXISCCTDATA[120] === 1'bz) || SAXISCCTDATA[120]; // rv 1 + assign SAXISCCTDATA_in[121] = (SAXISCCTDATA[121] === 1'bz) || SAXISCCTDATA[121]; // rv 1 + assign SAXISCCTDATA_in[122] = (SAXISCCTDATA[122] === 1'bz) || SAXISCCTDATA[122]; // rv 1 + assign SAXISCCTDATA_in[123] = (SAXISCCTDATA[123] === 1'bz) || SAXISCCTDATA[123]; // rv 1 + assign SAXISCCTDATA_in[124] = (SAXISCCTDATA[124] === 1'bz) || SAXISCCTDATA[124]; // rv 1 + assign SAXISCCTDATA_in[125] = (SAXISCCTDATA[125] === 1'bz) || SAXISCCTDATA[125]; // rv 1 + assign SAXISCCTDATA_in[126] = (SAXISCCTDATA[126] === 1'bz) || SAXISCCTDATA[126]; // rv 1 + assign SAXISCCTDATA_in[127] = (SAXISCCTDATA[127] === 1'bz) || SAXISCCTDATA[127]; // rv 1 + assign SAXISCCTDATA_in[128] = (SAXISCCTDATA[128] === 1'bz) || SAXISCCTDATA[128]; // rv 1 + assign SAXISCCTDATA_in[129] = (SAXISCCTDATA[129] === 1'bz) || SAXISCCTDATA[129]; // rv 1 + assign SAXISCCTDATA_in[12] = (SAXISCCTDATA[12] === 1'bz) || SAXISCCTDATA[12]; // rv 1 + assign SAXISCCTDATA_in[130] = (SAXISCCTDATA[130] === 1'bz) || SAXISCCTDATA[130]; // rv 1 + assign SAXISCCTDATA_in[131] = (SAXISCCTDATA[131] === 1'bz) || SAXISCCTDATA[131]; // rv 1 + assign SAXISCCTDATA_in[132] = (SAXISCCTDATA[132] === 1'bz) || SAXISCCTDATA[132]; // rv 1 + assign SAXISCCTDATA_in[133] = (SAXISCCTDATA[133] === 1'bz) || SAXISCCTDATA[133]; // rv 1 + assign SAXISCCTDATA_in[134] = (SAXISCCTDATA[134] === 1'bz) || SAXISCCTDATA[134]; // rv 1 + assign SAXISCCTDATA_in[135] = (SAXISCCTDATA[135] === 1'bz) || SAXISCCTDATA[135]; // rv 1 + assign SAXISCCTDATA_in[136] = (SAXISCCTDATA[136] === 1'bz) || SAXISCCTDATA[136]; // rv 1 + assign SAXISCCTDATA_in[137] = (SAXISCCTDATA[137] === 1'bz) || SAXISCCTDATA[137]; // rv 1 + assign SAXISCCTDATA_in[138] = (SAXISCCTDATA[138] === 1'bz) || SAXISCCTDATA[138]; // rv 1 + assign SAXISCCTDATA_in[139] = (SAXISCCTDATA[139] === 1'bz) || SAXISCCTDATA[139]; // rv 1 + assign SAXISCCTDATA_in[13] = (SAXISCCTDATA[13] === 1'bz) || SAXISCCTDATA[13]; // rv 1 + assign SAXISCCTDATA_in[140] = (SAXISCCTDATA[140] === 1'bz) || SAXISCCTDATA[140]; // rv 1 + assign SAXISCCTDATA_in[141] = (SAXISCCTDATA[141] === 1'bz) || SAXISCCTDATA[141]; // rv 1 + assign SAXISCCTDATA_in[142] = (SAXISCCTDATA[142] === 1'bz) || SAXISCCTDATA[142]; // rv 1 + assign SAXISCCTDATA_in[143] = (SAXISCCTDATA[143] === 1'bz) || SAXISCCTDATA[143]; // rv 1 + assign SAXISCCTDATA_in[144] = (SAXISCCTDATA[144] === 1'bz) || SAXISCCTDATA[144]; // rv 1 + assign SAXISCCTDATA_in[145] = (SAXISCCTDATA[145] === 1'bz) || SAXISCCTDATA[145]; // rv 1 + assign SAXISCCTDATA_in[146] = (SAXISCCTDATA[146] === 1'bz) || SAXISCCTDATA[146]; // rv 1 + assign SAXISCCTDATA_in[147] = (SAXISCCTDATA[147] === 1'bz) || SAXISCCTDATA[147]; // rv 1 + assign SAXISCCTDATA_in[148] = (SAXISCCTDATA[148] === 1'bz) || SAXISCCTDATA[148]; // rv 1 + assign SAXISCCTDATA_in[149] = (SAXISCCTDATA[149] === 1'bz) || SAXISCCTDATA[149]; // rv 1 + assign SAXISCCTDATA_in[14] = (SAXISCCTDATA[14] === 1'bz) || SAXISCCTDATA[14]; // rv 1 + assign SAXISCCTDATA_in[150] = (SAXISCCTDATA[150] === 1'bz) || SAXISCCTDATA[150]; // rv 1 + assign SAXISCCTDATA_in[151] = (SAXISCCTDATA[151] === 1'bz) || SAXISCCTDATA[151]; // rv 1 + assign SAXISCCTDATA_in[152] = (SAXISCCTDATA[152] === 1'bz) || SAXISCCTDATA[152]; // rv 1 + assign SAXISCCTDATA_in[153] = (SAXISCCTDATA[153] === 1'bz) || SAXISCCTDATA[153]; // rv 1 + assign SAXISCCTDATA_in[154] = (SAXISCCTDATA[154] === 1'bz) || SAXISCCTDATA[154]; // rv 1 + assign SAXISCCTDATA_in[155] = (SAXISCCTDATA[155] === 1'bz) || SAXISCCTDATA[155]; // rv 1 + assign SAXISCCTDATA_in[156] = (SAXISCCTDATA[156] === 1'bz) || SAXISCCTDATA[156]; // rv 1 + assign SAXISCCTDATA_in[157] = (SAXISCCTDATA[157] === 1'bz) || SAXISCCTDATA[157]; // rv 1 + assign SAXISCCTDATA_in[158] = (SAXISCCTDATA[158] === 1'bz) || SAXISCCTDATA[158]; // rv 1 + assign SAXISCCTDATA_in[159] = (SAXISCCTDATA[159] === 1'bz) || SAXISCCTDATA[159]; // rv 1 + assign SAXISCCTDATA_in[15] = (SAXISCCTDATA[15] === 1'bz) || SAXISCCTDATA[15]; // rv 1 + assign SAXISCCTDATA_in[160] = (SAXISCCTDATA[160] === 1'bz) || SAXISCCTDATA[160]; // rv 1 + assign SAXISCCTDATA_in[161] = (SAXISCCTDATA[161] === 1'bz) || SAXISCCTDATA[161]; // rv 1 + assign SAXISCCTDATA_in[162] = (SAXISCCTDATA[162] === 1'bz) || SAXISCCTDATA[162]; // rv 1 + assign SAXISCCTDATA_in[163] = (SAXISCCTDATA[163] === 1'bz) || SAXISCCTDATA[163]; // rv 1 + assign SAXISCCTDATA_in[164] = (SAXISCCTDATA[164] === 1'bz) || SAXISCCTDATA[164]; // rv 1 + assign SAXISCCTDATA_in[165] = (SAXISCCTDATA[165] === 1'bz) || SAXISCCTDATA[165]; // rv 1 + assign SAXISCCTDATA_in[166] = (SAXISCCTDATA[166] === 1'bz) || SAXISCCTDATA[166]; // rv 1 + assign SAXISCCTDATA_in[167] = (SAXISCCTDATA[167] === 1'bz) || SAXISCCTDATA[167]; // rv 1 + assign SAXISCCTDATA_in[168] = (SAXISCCTDATA[168] === 1'bz) || SAXISCCTDATA[168]; // rv 1 + assign SAXISCCTDATA_in[169] = (SAXISCCTDATA[169] === 1'bz) || SAXISCCTDATA[169]; // rv 1 + assign SAXISCCTDATA_in[16] = (SAXISCCTDATA[16] === 1'bz) || SAXISCCTDATA[16]; // rv 1 + assign SAXISCCTDATA_in[170] = (SAXISCCTDATA[170] === 1'bz) || SAXISCCTDATA[170]; // rv 1 + assign SAXISCCTDATA_in[171] = (SAXISCCTDATA[171] === 1'bz) || SAXISCCTDATA[171]; // rv 1 + assign SAXISCCTDATA_in[172] = (SAXISCCTDATA[172] === 1'bz) || SAXISCCTDATA[172]; // rv 1 + assign SAXISCCTDATA_in[173] = (SAXISCCTDATA[173] === 1'bz) || SAXISCCTDATA[173]; // rv 1 + assign SAXISCCTDATA_in[174] = (SAXISCCTDATA[174] === 1'bz) || SAXISCCTDATA[174]; // rv 1 + assign SAXISCCTDATA_in[175] = (SAXISCCTDATA[175] === 1'bz) || SAXISCCTDATA[175]; // rv 1 + assign SAXISCCTDATA_in[176] = (SAXISCCTDATA[176] === 1'bz) || SAXISCCTDATA[176]; // rv 1 + assign SAXISCCTDATA_in[177] = (SAXISCCTDATA[177] === 1'bz) || SAXISCCTDATA[177]; // rv 1 + assign SAXISCCTDATA_in[178] = (SAXISCCTDATA[178] === 1'bz) || SAXISCCTDATA[178]; // rv 1 + assign SAXISCCTDATA_in[179] = (SAXISCCTDATA[179] === 1'bz) || SAXISCCTDATA[179]; // rv 1 + assign SAXISCCTDATA_in[17] = (SAXISCCTDATA[17] === 1'bz) || SAXISCCTDATA[17]; // rv 1 + assign SAXISCCTDATA_in[180] = (SAXISCCTDATA[180] === 1'bz) || SAXISCCTDATA[180]; // rv 1 + assign SAXISCCTDATA_in[181] = (SAXISCCTDATA[181] === 1'bz) || SAXISCCTDATA[181]; // rv 1 + assign SAXISCCTDATA_in[182] = (SAXISCCTDATA[182] === 1'bz) || SAXISCCTDATA[182]; // rv 1 + assign SAXISCCTDATA_in[183] = (SAXISCCTDATA[183] === 1'bz) || SAXISCCTDATA[183]; // rv 1 + assign SAXISCCTDATA_in[184] = (SAXISCCTDATA[184] === 1'bz) || SAXISCCTDATA[184]; // rv 1 + assign SAXISCCTDATA_in[185] = (SAXISCCTDATA[185] === 1'bz) || SAXISCCTDATA[185]; // rv 1 + assign SAXISCCTDATA_in[186] = (SAXISCCTDATA[186] === 1'bz) || SAXISCCTDATA[186]; // rv 1 + assign SAXISCCTDATA_in[187] = (SAXISCCTDATA[187] === 1'bz) || SAXISCCTDATA[187]; // rv 1 + assign SAXISCCTDATA_in[188] = (SAXISCCTDATA[188] === 1'bz) || SAXISCCTDATA[188]; // rv 1 + assign SAXISCCTDATA_in[189] = (SAXISCCTDATA[189] === 1'bz) || SAXISCCTDATA[189]; // rv 1 + assign SAXISCCTDATA_in[18] = (SAXISCCTDATA[18] === 1'bz) || SAXISCCTDATA[18]; // rv 1 + assign SAXISCCTDATA_in[190] = (SAXISCCTDATA[190] === 1'bz) || SAXISCCTDATA[190]; // rv 1 + assign SAXISCCTDATA_in[191] = (SAXISCCTDATA[191] === 1'bz) || SAXISCCTDATA[191]; // rv 1 + assign SAXISCCTDATA_in[192] = (SAXISCCTDATA[192] === 1'bz) || SAXISCCTDATA[192]; // rv 1 + assign SAXISCCTDATA_in[193] = (SAXISCCTDATA[193] === 1'bz) || SAXISCCTDATA[193]; // rv 1 + assign SAXISCCTDATA_in[194] = (SAXISCCTDATA[194] === 1'bz) || SAXISCCTDATA[194]; // rv 1 + assign SAXISCCTDATA_in[195] = (SAXISCCTDATA[195] === 1'bz) || SAXISCCTDATA[195]; // rv 1 + assign SAXISCCTDATA_in[196] = (SAXISCCTDATA[196] === 1'bz) || SAXISCCTDATA[196]; // rv 1 + assign SAXISCCTDATA_in[197] = (SAXISCCTDATA[197] === 1'bz) || SAXISCCTDATA[197]; // rv 1 + assign SAXISCCTDATA_in[198] = (SAXISCCTDATA[198] === 1'bz) || SAXISCCTDATA[198]; // rv 1 + assign SAXISCCTDATA_in[199] = (SAXISCCTDATA[199] === 1'bz) || SAXISCCTDATA[199]; // rv 1 + assign SAXISCCTDATA_in[19] = (SAXISCCTDATA[19] === 1'bz) || SAXISCCTDATA[19]; // rv 1 + assign SAXISCCTDATA_in[1] = (SAXISCCTDATA[1] === 1'bz) || SAXISCCTDATA[1]; // rv 1 + assign SAXISCCTDATA_in[200] = (SAXISCCTDATA[200] === 1'bz) || SAXISCCTDATA[200]; // rv 1 + assign SAXISCCTDATA_in[201] = (SAXISCCTDATA[201] === 1'bz) || SAXISCCTDATA[201]; // rv 1 + assign SAXISCCTDATA_in[202] = (SAXISCCTDATA[202] === 1'bz) || SAXISCCTDATA[202]; // rv 1 + assign SAXISCCTDATA_in[203] = (SAXISCCTDATA[203] === 1'bz) || SAXISCCTDATA[203]; // rv 1 + assign SAXISCCTDATA_in[204] = (SAXISCCTDATA[204] === 1'bz) || SAXISCCTDATA[204]; // rv 1 + assign SAXISCCTDATA_in[205] = (SAXISCCTDATA[205] === 1'bz) || SAXISCCTDATA[205]; // rv 1 + assign SAXISCCTDATA_in[206] = (SAXISCCTDATA[206] === 1'bz) || SAXISCCTDATA[206]; // rv 1 + assign SAXISCCTDATA_in[207] = (SAXISCCTDATA[207] === 1'bz) || SAXISCCTDATA[207]; // rv 1 + assign SAXISCCTDATA_in[208] = (SAXISCCTDATA[208] === 1'bz) || SAXISCCTDATA[208]; // rv 1 + assign SAXISCCTDATA_in[209] = (SAXISCCTDATA[209] === 1'bz) || SAXISCCTDATA[209]; // rv 1 + assign SAXISCCTDATA_in[20] = (SAXISCCTDATA[20] === 1'bz) || SAXISCCTDATA[20]; // rv 1 + assign SAXISCCTDATA_in[210] = (SAXISCCTDATA[210] === 1'bz) || SAXISCCTDATA[210]; // rv 1 + assign SAXISCCTDATA_in[211] = (SAXISCCTDATA[211] === 1'bz) || SAXISCCTDATA[211]; // rv 1 + assign SAXISCCTDATA_in[212] = (SAXISCCTDATA[212] === 1'bz) || SAXISCCTDATA[212]; // rv 1 + assign SAXISCCTDATA_in[213] = (SAXISCCTDATA[213] === 1'bz) || SAXISCCTDATA[213]; // rv 1 + assign SAXISCCTDATA_in[214] = (SAXISCCTDATA[214] === 1'bz) || SAXISCCTDATA[214]; // rv 1 + assign SAXISCCTDATA_in[215] = (SAXISCCTDATA[215] === 1'bz) || SAXISCCTDATA[215]; // rv 1 + assign SAXISCCTDATA_in[216] = (SAXISCCTDATA[216] === 1'bz) || SAXISCCTDATA[216]; // rv 1 + assign SAXISCCTDATA_in[217] = (SAXISCCTDATA[217] === 1'bz) || SAXISCCTDATA[217]; // rv 1 + assign SAXISCCTDATA_in[218] = (SAXISCCTDATA[218] === 1'bz) || SAXISCCTDATA[218]; // rv 1 + assign SAXISCCTDATA_in[219] = (SAXISCCTDATA[219] === 1'bz) || SAXISCCTDATA[219]; // rv 1 + assign SAXISCCTDATA_in[21] = (SAXISCCTDATA[21] === 1'bz) || SAXISCCTDATA[21]; // rv 1 + assign SAXISCCTDATA_in[220] = (SAXISCCTDATA[220] === 1'bz) || SAXISCCTDATA[220]; // rv 1 + assign SAXISCCTDATA_in[221] = (SAXISCCTDATA[221] === 1'bz) || SAXISCCTDATA[221]; // rv 1 + assign SAXISCCTDATA_in[222] = (SAXISCCTDATA[222] === 1'bz) || SAXISCCTDATA[222]; // rv 1 + assign SAXISCCTDATA_in[223] = (SAXISCCTDATA[223] === 1'bz) || SAXISCCTDATA[223]; // rv 1 + assign SAXISCCTDATA_in[224] = (SAXISCCTDATA[224] === 1'bz) || SAXISCCTDATA[224]; // rv 1 + assign SAXISCCTDATA_in[225] = (SAXISCCTDATA[225] === 1'bz) || SAXISCCTDATA[225]; // rv 1 + assign SAXISCCTDATA_in[226] = (SAXISCCTDATA[226] === 1'bz) || SAXISCCTDATA[226]; // rv 1 + assign SAXISCCTDATA_in[227] = (SAXISCCTDATA[227] === 1'bz) || SAXISCCTDATA[227]; // rv 1 + assign SAXISCCTDATA_in[228] = (SAXISCCTDATA[228] === 1'bz) || SAXISCCTDATA[228]; // rv 1 + assign SAXISCCTDATA_in[229] = (SAXISCCTDATA[229] === 1'bz) || SAXISCCTDATA[229]; // rv 1 + assign SAXISCCTDATA_in[22] = (SAXISCCTDATA[22] === 1'bz) || SAXISCCTDATA[22]; // rv 1 + assign SAXISCCTDATA_in[230] = (SAXISCCTDATA[230] === 1'bz) || SAXISCCTDATA[230]; // rv 1 + assign SAXISCCTDATA_in[231] = (SAXISCCTDATA[231] === 1'bz) || SAXISCCTDATA[231]; // rv 1 + assign SAXISCCTDATA_in[232] = (SAXISCCTDATA[232] === 1'bz) || SAXISCCTDATA[232]; // rv 1 + assign SAXISCCTDATA_in[233] = (SAXISCCTDATA[233] === 1'bz) || SAXISCCTDATA[233]; // rv 1 + assign SAXISCCTDATA_in[234] = (SAXISCCTDATA[234] === 1'bz) || SAXISCCTDATA[234]; // rv 1 + assign SAXISCCTDATA_in[235] = (SAXISCCTDATA[235] === 1'bz) || SAXISCCTDATA[235]; // rv 1 + assign SAXISCCTDATA_in[236] = (SAXISCCTDATA[236] === 1'bz) || SAXISCCTDATA[236]; // rv 1 + assign SAXISCCTDATA_in[237] = (SAXISCCTDATA[237] === 1'bz) || SAXISCCTDATA[237]; // rv 1 + assign SAXISCCTDATA_in[238] = (SAXISCCTDATA[238] === 1'bz) || SAXISCCTDATA[238]; // rv 1 + assign SAXISCCTDATA_in[239] = (SAXISCCTDATA[239] === 1'bz) || SAXISCCTDATA[239]; // rv 1 + assign SAXISCCTDATA_in[23] = (SAXISCCTDATA[23] === 1'bz) || SAXISCCTDATA[23]; // rv 1 + assign SAXISCCTDATA_in[240] = (SAXISCCTDATA[240] === 1'bz) || SAXISCCTDATA[240]; // rv 1 + assign SAXISCCTDATA_in[241] = (SAXISCCTDATA[241] === 1'bz) || SAXISCCTDATA[241]; // rv 1 + assign SAXISCCTDATA_in[242] = (SAXISCCTDATA[242] === 1'bz) || SAXISCCTDATA[242]; // rv 1 + assign SAXISCCTDATA_in[243] = (SAXISCCTDATA[243] === 1'bz) || SAXISCCTDATA[243]; // rv 1 + assign SAXISCCTDATA_in[244] = (SAXISCCTDATA[244] === 1'bz) || SAXISCCTDATA[244]; // rv 1 + assign SAXISCCTDATA_in[245] = (SAXISCCTDATA[245] === 1'bz) || SAXISCCTDATA[245]; // rv 1 + assign SAXISCCTDATA_in[246] = (SAXISCCTDATA[246] === 1'bz) || SAXISCCTDATA[246]; // rv 1 + assign SAXISCCTDATA_in[247] = (SAXISCCTDATA[247] === 1'bz) || SAXISCCTDATA[247]; // rv 1 + assign SAXISCCTDATA_in[248] = (SAXISCCTDATA[248] === 1'bz) || SAXISCCTDATA[248]; // rv 1 + assign SAXISCCTDATA_in[249] = (SAXISCCTDATA[249] === 1'bz) || SAXISCCTDATA[249]; // rv 1 + assign SAXISCCTDATA_in[24] = (SAXISCCTDATA[24] === 1'bz) || SAXISCCTDATA[24]; // rv 1 + assign SAXISCCTDATA_in[250] = (SAXISCCTDATA[250] === 1'bz) || SAXISCCTDATA[250]; // rv 1 + assign SAXISCCTDATA_in[251] = (SAXISCCTDATA[251] === 1'bz) || SAXISCCTDATA[251]; // rv 1 + assign SAXISCCTDATA_in[252] = (SAXISCCTDATA[252] === 1'bz) || SAXISCCTDATA[252]; // rv 1 + assign SAXISCCTDATA_in[253] = (SAXISCCTDATA[253] === 1'bz) || SAXISCCTDATA[253]; // rv 1 + assign SAXISCCTDATA_in[254] = (SAXISCCTDATA[254] === 1'bz) || SAXISCCTDATA[254]; // rv 1 + assign SAXISCCTDATA_in[255] = (SAXISCCTDATA[255] === 1'bz) || SAXISCCTDATA[255]; // rv 1 + assign SAXISCCTDATA_in[25] = (SAXISCCTDATA[25] === 1'bz) || SAXISCCTDATA[25]; // rv 1 + assign SAXISCCTDATA_in[26] = (SAXISCCTDATA[26] === 1'bz) || SAXISCCTDATA[26]; // rv 1 + assign SAXISCCTDATA_in[27] = (SAXISCCTDATA[27] === 1'bz) || SAXISCCTDATA[27]; // rv 1 + assign SAXISCCTDATA_in[28] = (SAXISCCTDATA[28] === 1'bz) || SAXISCCTDATA[28]; // rv 1 + assign SAXISCCTDATA_in[29] = (SAXISCCTDATA[29] === 1'bz) || SAXISCCTDATA[29]; // rv 1 + assign SAXISCCTDATA_in[2] = (SAXISCCTDATA[2] === 1'bz) || SAXISCCTDATA[2]; // rv 1 + assign SAXISCCTDATA_in[30] = (SAXISCCTDATA[30] === 1'bz) || SAXISCCTDATA[30]; // rv 1 + assign SAXISCCTDATA_in[31] = (SAXISCCTDATA[31] === 1'bz) || SAXISCCTDATA[31]; // rv 1 + assign SAXISCCTDATA_in[32] = (SAXISCCTDATA[32] === 1'bz) || SAXISCCTDATA[32]; // rv 1 + assign SAXISCCTDATA_in[33] = (SAXISCCTDATA[33] === 1'bz) || SAXISCCTDATA[33]; // rv 1 + assign SAXISCCTDATA_in[34] = (SAXISCCTDATA[34] === 1'bz) || SAXISCCTDATA[34]; // rv 1 + assign SAXISCCTDATA_in[35] = (SAXISCCTDATA[35] === 1'bz) || SAXISCCTDATA[35]; // rv 1 + assign SAXISCCTDATA_in[36] = (SAXISCCTDATA[36] === 1'bz) || SAXISCCTDATA[36]; // rv 1 + assign SAXISCCTDATA_in[37] = (SAXISCCTDATA[37] === 1'bz) || SAXISCCTDATA[37]; // rv 1 + assign SAXISCCTDATA_in[38] = (SAXISCCTDATA[38] === 1'bz) || SAXISCCTDATA[38]; // rv 1 + assign SAXISCCTDATA_in[39] = (SAXISCCTDATA[39] === 1'bz) || SAXISCCTDATA[39]; // rv 1 + assign SAXISCCTDATA_in[3] = (SAXISCCTDATA[3] === 1'bz) || SAXISCCTDATA[3]; // rv 1 + assign SAXISCCTDATA_in[40] = (SAXISCCTDATA[40] === 1'bz) || SAXISCCTDATA[40]; // rv 1 + assign SAXISCCTDATA_in[41] = (SAXISCCTDATA[41] === 1'bz) || SAXISCCTDATA[41]; // rv 1 + assign SAXISCCTDATA_in[42] = (SAXISCCTDATA[42] === 1'bz) || SAXISCCTDATA[42]; // rv 1 + assign SAXISCCTDATA_in[43] = (SAXISCCTDATA[43] === 1'bz) || SAXISCCTDATA[43]; // rv 1 + assign SAXISCCTDATA_in[44] = (SAXISCCTDATA[44] === 1'bz) || SAXISCCTDATA[44]; // rv 1 + assign SAXISCCTDATA_in[45] = (SAXISCCTDATA[45] === 1'bz) || SAXISCCTDATA[45]; // rv 1 + assign SAXISCCTDATA_in[46] = (SAXISCCTDATA[46] === 1'bz) || SAXISCCTDATA[46]; // rv 1 + assign SAXISCCTDATA_in[47] = (SAXISCCTDATA[47] === 1'bz) || SAXISCCTDATA[47]; // rv 1 + assign SAXISCCTDATA_in[48] = (SAXISCCTDATA[48] === 1'bz) || SAXISCCTDATA[48]; // rv 1 + assign SAXISCCTDATA_in[49] = (SAXISCCTDATA[49] === 1'bz) || SAXISCCTDATA[49]; // rv 1 + assign SAXISCCTDATA_in[4] = (SAXISCCTDATA[4] === 1'bz) || SAXISCCTDATA[4]; // rv 1 + assign SAXISCCTDATA_in[50] = (SAXISCCTDATA[50] === 1'bz) || SAXISCCTDATA[50]; // rv 1 + assign SAXISCCTDATA_in[51] = (SAXISCCTDATA[51] === 1'bz) || SAXISCCTDATA[51]; // rv 1 + assign SAXISCCTDATA_in[52] = (SAXISCCTDATA[52] === 1'bz) || SAXISCCTDATA[52]; // rv 1 + assign SAXISCCTDATA_in[53] = (SAXISCCTDATA[53] === 1'bz) || SAXISCCTDATA[53]; // rv 1 + assign SAXISCCTDATA_in[54] = (SAXISCCTDATA[54] === 1'bz) || SAXISCCTDATA[54]; // rv 1 + assign SAXISCCTDATA_in[55] = (SAXISCCTDATA[55] === 1'bz) || SAXISCCTDATA[55]; // rv 1 + assign SAXISCCTDATA_in[56] = (SAXISCCTDATA[56] === 1'bz) || SAXISCCTDATA[56]; // rv 1 + assign SAXISCCTDATA_in[57] = (SAXISCCTDATA[57] === 1'bz) || SAXISCCTDATA[57]; // rv 1 + assign SAXISCCTDATA_in[58] = (SAXISCCTDATA[58] === 1'bz) || SAXISCCTDATA[58]; // rv 1 + assign SAXISCCTDATA_in[59] = (SAXISCCTDATA[59] === 1'bz) || SAXISCCTDATA[59]; // rv 1 + assign SAXISCCTDATA_in[5] = (SAXISCCTDATA[5] === 1'bz) || SAXISCCTDATA[5]; // rv 1 + assign SAXISCCTDATA_in[60] = (SAXISCCTDATA[60] === 1'bz) || SAXISCCTDATA[60]; // rv 1 + assign SAXISCCTDATA_in[61] = (SAXISCCTDATA[61] === 1'bz) || SAXISCCTDATA[61]; // rv 1 + assign SAXISCCTDATA_in[62] = (SAXISCCTDATA[62] === 1'bz) || SAXISCCTDATA[62]; // rv 1 + assign SAXISCCTDATA_in[63] = (SAXISCCTDATA[63] === 1'bz) || SAXISCCTDATA[63]; // rv 1 + assign SAXISCCTDATA_in[64] = (SAXISCCTDATA[64] === 1'bz) || SAXISCCTDATA[64]; // rv 1 + assign SAXISCCTDATA_in[65] = (SAXISCCTDATA[65] === 1'bz) || SAXISCCTDATA[65]; // rv 1 + assign SAXISCCTDATA_in[66] = (SAXISCCTDATA[66] === 1'bz) || SAXISCCTDATA[66]; // rv 1 + assign SAXISCCTDATA_in[67] = (SAXISCCTDATA[67] === 1'bz) || SAXISCCTDATA[67]; // rv 1 + assign SAXISCCTDATA_in[68] = (SAXISCCTDATA[68] === 1'bz) || SAXISCCTDATA[68]; // rv 1 + assign SAXISCCTDATA_in[69] = (SAXISCCTDATA[69] === 1'bz) || SAXISCCTDATA[69]; // rv 1 + assign SAXISCCTDATA_in[6] = (SAXISCCTDATA[6] === 1'bz) || SAXISCCTDATA[6]; // rv 1 + assign SAXISCCTDATA_in[70] = (SAXISCCTDATA[70] === 1'bz) || SAXISCCTDATA[70]; // rv 1 + assign SAXISCCTDATA_in[71] = (SAXISCCTDATA[71] === 1'bz) || SAXISCCTDATA[71]; // rv 1 + assign SAXISCCTDATA_in[72] = (SAXISCCTDATA[72] === 1'bz) || SAXISCCTDATA[72]; // rv 1 + assign SAXISCCTDATA_in[73] = (SAXISCCTDATA[73] === 1'bz) || SAXISCCTDATA[73]; // rv 1 + assign SAXISCCTDATA_in[74] = (SAXISCCTDATA[74] === 1'bz) || SAXISCCTDATA[74]; // rv 1 + assign SAXISCCTDATA_in[75] = (SAXISCCTDATA[75] === 1'bz) || SAXISCCTDATA[75]; // rv 1 + assign SAXISCCTDATA_in[76] = (SAXISCCTDATA[76] === 1'bz) || SAXISCCTDATA[76]; // rv 1 + assign SAXISCCTDATA_in[77] = (SAXISCCTDATA[77] === 1'bz) || SAXISCCTDATA[77]; // rv 1 + assign SAXISCCTDATA_in[78] = (SAXISCCTDATA[78] === 1'bz) || SAXISCCTDATA[78]; // rv 1 + assign SAXISCCTDATA_in[79] = (SAXISCCTDATA[79] === 1'bz) || SAXISCCTDATA[79]; // rv 1 + assign SAXISCCTDATA_in[7] = (SAXISCCTDATA[7] === 1'bz) || SAXISCCTDATA[7]; // rv 1 + assign SAXISCCTDATA_in[80] = (SAXISCCTDATA[80] === 1'bz) || SAXISCCTDATA[80]; // rv 1 + assign SAXISCCTDATA_in[81] = (SAXISCCTDATA[81] === 1'bz) || SAXISCCTDATA[81]; // rv 1 + assign SAXISCCTDATA_in[82] = (SAXISCCTDATA[82] === 1'bz) || SAXISCCTDATA[82]; // rv 1 + assign SAXISCCTDATA_in[83] = (SAXISCCTDATA[83] === 1'bz) || SAXISCCTDATA[83]; // rv 1 + assign SAXISCCTDATA_in[84] = (SAXISCCTDATA[84] === 1'bz) || SAXISCCTDATA[84]; // rv 1 + assign SAXISCCTDATA_in[85] = (SAXISCCTDATA[85] === 1'bz) || SAXISCCTDATA[85]; // rv 1 + assign SAXISCCTDATA_in[86] = (SAXISCCTDATA[86] === 1'bz) || SAXISCCTDATA[86]; // rv 1 + assign SAXISCCTDATA_in[87] = (SAXISCCTDATA[87] === 1'bz) || SAXISCCTDATA[87]; // rv 1 + assign SAXISCCTDATA_in[88] = (SAXISCCTDATA[88] === 1'bz) || SAXISCCTDATA[88]; // rv 1 + assign SAXISCCTDATA_in[89] = (SAXISCCTDATA[89] === 1'bz) || SAXISCCTDATA[89]; // rv 1 + assign SAXISCCTDATA_in[8] = (SAXISCCTDATA[8] === 1'bz) || SAXISCCTDATA[8]; // rv 1 + assign SAXISCCTDATA_in[90] = (SAXISCCTDATA[90] === 1'bz) || SAXISCCTDATA[90]; // rv 1 + assign SAXISCCTDATA_in[91] = (SAXISCCTDATA[91] === 1'bz) || SAXISCCTDATA[91]; // rv 1 + assign SAXISCCTDATA_in[92] = (SAXISCCTDATA[92] === 1'bz) || SAXISCCTDATA[92]; // rv 1 + assign SAXISCCTDATA_in[93] = (SAXISCCTDATA[93] === 1'bz) || SAXISCCTDATA[93]; // rv 1 + assign SAXISCCTDATA_in[94] = (SAXISCCTDATA[94] === 1'bz) || SAXISCCTDATA[94]; // rv 1 + assign SAXISCCTDATA_in[95] = (SAXISCCTDATA[95] === 1'bz) || SAXISCCTDATA[95]; // rv 1 + assign SAXISCCTDATA_in[96] = (SAXISCCTDATA[96] === 1'bz) || SAXISCCTDATA[96]; // rv 1 + assign SAXISCCTDATA_in[97] = (SAXISCCTDATA[97] === 1'bz) || SAXISCCTDATA[97]; // rv 1 + assign SAXISCCTDATA_in[98] = (SAXISCCTDATA[98] === 1'bz) || SAXISCCTDATA[98]; // rv 1 + assign SAXISCCTDATA_in[99] = (SAXISCCTDATA[99] === 1'bz) || SAXISCCTDATA[99]; // rv 1 + assign SAXISCCTDATA_in[9] = (SAXISCCTDATA[9] === 1'bz) || SAXISCCTDATA[9]; // rv 1 + assign SAXISCCTKEEP_in[0] = (SAXISCCTKEEP[0] !== 1'bz) && SAXISCCTKEEP[0]; // rv 0 + assign SAXISCCTKEEP_in[1] = (SAXISCCTKEEP[1] !== 1'bz) && SAXISCCTKEEP[1]; // rv 0 + assign SAXISCCTKEEP_in[2] = (SAXISCCTKEEP[2] !== 1'bz) && SAXISCCTKEEP[2]; // rv 0 + assign SAXISCCTKEEP_in[3] = (SAXISCCTKEEP[3] !== 1'bz) && SAXISCCTKEEP[3]; // rv 0 + assign SAXISCCTKEEP_in[4] = (SAXISCCTKEEP[4] !== 1'bz) && SAXISCCTKEEP[4]; // rv 0 + assign SAXISCCTKEEP_in[5] = (SAXISCCTKEEP[5] !== 1'bz) && SAXISCCTKEEP[5]; // rv 0 + assign SAXISCCTKEEP_in[6] = (SAXISCCTKEEP[6] !== 1'bz) && SAXISCCTKEEP[6]; // rv 0 + assign SAXISCCTKEEP_in[7] = (SAXISCCTKEEP[7] !== 1'bz) && SAXISCCTKEEP[7]; // rv 0 + assign SAXISCCTLAST_in = (SAXISCCTLAST === 1'bz) || SAXISCCTLAST; // rv 1 + assign SAXISCCTUSER_in[0] = (SAXISCCTUSER[0] === 1'bz) || SAXISCCTUSER[0]; // rv 1 + assign SAXISCCTUSER_in[10] = (SAXISCCTUSER[10] === 1'bz) || SAXISCCTUSER[10]; // rv 1 + assign SAXISCCTUSER_in[11] = (SAXISCCTUSER[11] === 1'bz) || SAXISCCTUSER[11]; // rv 1 + assign SAXISCCTUSER_in[12] = (SAXISCCTUSER[12] === 1'bz) || SAXISCCTUSER[12]; // rv 1 + assign SAXISCCTUSER_in[13] = (SAXISCCTUSER[13] === 1'bz) || SAXISCCTUSER[13]; // rv 1 + assign SAXISCCTUSER_in[14] = (SAXISCCTUSER[14] === 1'bz) || SAXISCCTUSER[14]; // rv 1 + assign SAXISCCTUSER_in[15] = (SAXISCCTUSER[15] === 1'bz) || SAXISCCTUSER[15]; // rv 1 + assign SAXISCCTUSER_in[16] = (SAXISCCTUSER[16] === 1'bz) || SAXISCCTUSER[16]; // rv 1 + assign SAXISCCTUSER_in[17] = (SAXISCCTUSER[17] === 1'bz) || SAXISCCTUSER[17]; // rv 1 + assign SAXISCCTUSER_in[18] = (SAXISCCTUSER[18] === 1'bz) || SAXISCCTUSER[18]; // rv 1 + assign SAXISCCTUSER_in[19] = (SAXISCCTUSER[19] === 1'bz) || SAXISCCTUSER[19]; // rv 1 + assign SAXISCCTUSER_in[1] = (SAXISCCTUSER[1] === 1'bz) || SAXISCCTUSER[1]; // rv 1 + assign SAXISCCTUSER_in[20] = (SAXISCCTUSER[20] === 1'bz) || SAXISCCTUSER[20]; // rv 1 + assign SAXISCCTUSER_in[21] = (SAXISCCTUSER[21] === 1'bz) || SAXISCCTUSER[21]; // rv 1 + assign SAXISCCTUSER_in[22] = (SAXISCCTUSER[22] === 1'bz) || SAXISCCTUSER[22]; // rv 1 + assign SAXISCCTUSER_in[23] = (SAXISCCTUSER[23] === 1'bz) || SAXISCCTUSER[23]; // rv 1 + assign SAXISCCTUSER_in[24] = (SAXISCCTUSER[24] === 1'bz) || SAXISCCTUSER[24]; // rv 1 + assign SAXISCCTUSER_in[25] = (SAXISCCTUSER[25] === 1'bz) || SAXISCCTUSER[25]; // rv 1 + assign SAXISCCTUSER_in[26] = (SAXISCCTUSER[26] === 1'bz) || SAXISCCTUSER[26]; // rv 1 + assign SAXISCCTUSER_in[27] = (SAXISCCTUSER[27] === 1'bz) || SAXISCCTUSER[27]; // rv 1 + assign SAXISCCTUSER_in[28] = (SAXISCCTUSER[28] === 1'bz) || SAXISCCTUSER[28]; // rv 1 + assign SAXISCCTUSER_in[29] = (SAXISCCTUSER[29] === 1'bz) || SAXISCCTUSER[29]; // rv 1 + assign SAXISCCTUSER_in[2] = (SAXISCCTUSER[2] === 1'bz) || SAXISCCTUSER[2]; // rv 1 + assign SAXISCCTUSER_in[30] = (SAXISCCTUSER[30] === 1'bz) || SAXISCCTUSER[30]; // rv 1 + assign SAXISCCTUSER_in[31] = (SAXISCCTUSER[31] === 1'bz) || SAXISCCTUSER[31]; // rv 1 + assign SAXISCCTUSER_in[32] = (SAXISCCTUSER[32] === 1'bz) || SAXISCCTUSER[32]; // rv 1 + assign SAXISCCTUSER_in[3] = (SAXISCCTUSER[3] === 1'bz) || SAXISCCTUSER[3]; // rv 1 + assign SAXISCCTUSER_in[4] = (SAXISCCTUSER[4] === 1'bz) || SAXISCCTUSER[4]; // rv 1 + assign SAXISCCTUSER_in[5] = (SAXISCCTUSER[5] === 1'bz) || SAXISCCTUSER[5]; // rv 1 + assign SAXISCCTUSER_in[6] = (SAXISCCTUSER[6] === 1'bz) || SAXISCCTUSER[6]; // rv 1 + assign SAXISCCTUSER_in[7] = (SAXISCCTUSER[7] === 1'bz) || SAXISCCTUSER[7]; // rv 1 + assign SAXISCCTUSER_in[8] = (SAXISCCTUSER[8] === 1'bz) || SAXISCCTUSER[8]; // rv 1 + assign SAXISCCTUSER_in[9] = (SAXISCCTUSER[9] === 1'bz) || SAXISCCTUSER[9]; // rv 1 + assign SAXISCCTVALID_in = (SAXISCCTVALID !== 1'bz) && SAXISCCTVALID; // rv 0 + assign SAXISRQTDATA_in[0] = (SAXISRQTDATA[0] === 1'bz) || SAXISRQTDATA[0]; // rv 1 + assign SAXISRQTDATA_in[100] = (SAXISRQTDATA[100] === 1'bz) || SAXISRQTDATA[100]; // rv 1 + assign SAXISRQTDATA_in[101] = (SAXISRQTDATA[101] === 1'bz) || SAXISRQTDATA[101]; // rv 1 + assign SAXISRQTDATA_in[102] = (SAXISRQTDATA[102] === 1'bz) || SAXISRQTDATA[102]; // rv 1 + assign SAXISRQTDATA_in[103] = (SAXISRQTDATA[103] === 1'bz) || SAXISRQTDATA[103]; // rv 1 + assign SAXISRQTDATA_in[104] = (SAXISRQTDATA[104] === 1'bz) || SAXISRQTDATA[104]; // rv 1 + assign SAXISRQTDATA_in[105] = (SAXISRQTDATA[105] === 1'bz) || SAXISRQTDATA[105]; // rv 1 + assign SAXISRQTDATA_in[106] = (SAXISRQTDATA[106] === 1'bz) || SAXISRQTDATA[106]; // rv 1 + assign SAXISRQTDATA_in[107] = (SAXISRQTDATA[107] === 1'bz) || SAXISRQTDATA[107]; // rv 1 + assign SAXISRQTDATA_in[108] = (SAXISRQTDATA[108] === 1'bz) || SAXISRQTDATA[108]; // rv 1 + assign SAXISRQTDATA_in[109] = (SAXISRQTDATA[109] === 1'bz) || SAXISRQTDATA[109]; // rv 1 + assign SAXISRQTDATA_in[10] = (SAXISRQTDATA[10] === 1'bz) || SAXISRQTDATA[10]; // rv 1 + assign SAXISRQTDATA_in[110] = (SAXISRQTDATA[110] === 1'bz) || SAXISRQTDATA[110]; // rv 1 + assign SAXISRQTDATA_in[111] = (SAXISRQTDATA[111] === 1'bz) || SAXISRQTDATA[111]; // rv 1 + assign SAXISRQTDATA_in[112] = (SAXISRQTDATA[112] === 1'bz) || SAXISRQTDATA[112]; // rv 1 + assign SAXISRQTDATA_in[113] = (SAXISRQTDATA[113] === 1'bz) || SAXISRQTDATA[113]; // rv 1 + assign SAXISRQTDATA_in[114] = (SAXISRQTDATA[114] === 1'bz) || SAXISRQTDATA[114]; // rv 1 + assign SAXISRQTDATA_in[115] = (SAXISRQTDATA[115] === 1'bz) || SAXISRQTDATA[115]; // rv 1 + assign SAXISRQTDATA_in[116] = (SAXISRQTDATA[116] === 1'bz) || SAXISRQTDATA[116]; // rv 1 + assign SAXISRQTDATA_in[117] = (SAXISRQTDATA[117] === 1'bz) || SAXISRQTDATA[117]; // rv 1 + assign SAXISRQTDATA_in[118] = (SAXISRQTDATA[118] === 1'bz) || SAXISRQTDATA[118]; // rv 1 + assign SAXISRQTDATA_in[119] = (SAXISRQTDATA[119] === 1'bz) || SAXISRQTDATA[119]; // rv 1 + assign SAXISRQTDATA_in[11] = (SAXISRQTDATA[11] === 1'bz) || SAXISRQTDATA[11]; // rv 1 + assign SAXISRQTDATA_in[120] = (SAXISRQTDATA[120] === 1'bz) || SAXISRQTDATA[120]; // rv 1 + assign SAXISRQTDATA_in[121] = (SAXISRQTDATA[121] === 1'bz) || SAXISRQTDATA[121]; // rv 1 + assign SAXISRQTDATA_in[122] = (SAXISRQTDATA[122] === 1'bz) || SAXISRQTDATA[122]; // rv 1 + assign SAXISRQTDATA_in[123] = (SAXISRQTDATA[123] === 1'bz) || SAXISRQTDATA[123]; // rv 1 + assign SAXISRQTDATA_in[124] = (SAXISRQTDATA[124] === 1'bz) || SAXISRQTDATA[124]; // rv 1 + assign SAXISRQTDATA_in[125] = (SAXISRQTDATA[125] === 1'bz) || SAXISRQTDATA[125]; // rv 1 + assign SAXISRQTDATA_in[126] = (SAXISRQTDATA[126] === 1'bz) || SAXISRQTDATA[126]; // rv 1 + assign SAXISRQTDATA_in[127] = (SAXISRQTDATA[127] === 1'bz) || SAXISRQTDATA[127]; // rv 1 + assign SAXISRQTDATA_in[128] = (SAXISRQTDATA[128] === 1'bz) || SAXISRQTDATA[128]; // rv 1 + assign SAXISRQTDATA_in[129] = (SAXISRQTDATA[129] === 1'bz) || SAXISRQTDATA[129]; // rv 1 + assign SAXISRQTDATA_in[12] = (SAXISRQTDATA[12] === 1'bz) || SAXISRQTDATA[12]; // rv 1 + assign SAXISRQTDATA_in[130] = (SAXISRQTDATA[130] === 1'bz) || SAXISRQTDATA[130]; // rv 1 + assign SAXISRQTDATA_in[131] = (SAXISRQTDATA[131] === 1'bz) || SAXISRQTDATA[131]; // rv 1 + assign SAXISRQTDATA_in[132] = (SAXISRQTDATA[132] === 1'bz) || SAXISRQTDATA[132]; // rv 1 + assign SAXISRQTDATA_in[133] = (SAXISRQTDATA[133] === 1'bz) || SAXISRQTDATA[133]; // rv 1 + assign SAXISRQTDATA_in[134] = (SAXISRQTDATA[134] === 1'bz) || SAXISRQTDATA[134]; // rv 1 + assign SAXISRQTDATA_in[135] = (SAXISRQTDATA[135] === 1'bz) || SAXISRQTDATA[135]; // rv 1 + assign SAXISRQTDATA_in[136] = (SAXISRQTDATA[136] === 1'bz) || SAXISRQTDATA[136]; // rv 1 + assign SAXISRQTDATA_in[137] = (SAXISRQTDATA[137] === 1'bz) || SAXISRQTDATA[137]; // rv 1 + assign SAXISRQTDATA_in[138] = (SAXISRQTDATA[138] === 1'bz) || SAXISRQTDATA[138]; // rv 1 + assign SAXISRQTDATA_in[139] = (SAXISRQTDATA[139] === 1'bz) || SAXISRQTDATA[139]; // rv 1 + assign SAXISRQTDATA_in[13] = (SAXISRQTDATA[13] === 1'bz) || SAXISRQTDATA[13]; // rv 1 + assign SAXISRQTDATA_in[140] = (SAXISRQTDATA[140] === 1'bz) || SAXISRQTDATA[140]; // rv 1 + assign SAXISRQTDATA_in[141] = (SAXISRQTDATA[141] === 1'bz) || SAXISRQTDATA[141]; // rv 1 + assign SAXISRQTDATA_in[142] = (SAXISRQTDATA[142] === 1'bz) || SAXISRQTDATA[142]; // rv 1 + assign SAXISRQTDATA_in[143] = (SAXISRQTDATA[143] === 1'bz) || SAXISRQTDATA[143]; // rv 1 + assign SAXISRQTDATA_in[144] = (SAXISRQTDATA[144] === 1'bz) || SAXISRQTDATA[144]; // rv 1 + assign SAXISRQTDATA_in[145] = (SAXISRQTDATA[145] === 1'bz) || SAXISRQTDATA[145]; // rv 1 + assign SAXISRQTDATA_in[146] = (SAXISRQTDATA[146] === 1'bz) || SAXISRQTDATA[146]; // rv 1 + assign SAXISRQTDATA_in[147] = (SAXISRQTDATA[147] === 1'bz) || SAXISRQTDATA[147]; // rv 1 + assign SAXISRQTDATA_in[148] = (SAXISRQTDATA[148] === 1'bz) || SAXISRQTDATA[148]; // rv 1 + assign SAXISRQTDATA_in[149] = (SAXISRQTDATA[149] === 1'bz) || SAXISRQTDATA[149]; // rv 1 + assign SAXISRQTDATA_in[14] = (SAXISRQTDATA[14] === 1'bz) || SAXISRQTDATA[14]; // rv 1 + assign SAXISRQTDATA_in[150] = (SAXISRQTDATA[150] === 1'bz) || SAXISRQTDATA[150]; // rv 1 + assign SAXISRQTDATA_in[151] = (SAXISRQTDATA[151] === 1'bz) || SAXISRQTDATA[151]; // rv 1 + assign SAXISRQTDATA_in[152] = (SAXISRQTDATA[152] === 1'bz) || SAXISRQTDATA[152]; // rv 1 + assign SAXISRQTDATA_in[153] = (SAXISRQTDATA[153] === 1'bz) || SAXISRQTDATA[153]; // rv 1 + assign SAXISRQTDATA_in[154] = (SAXISRQTDATA[154] === 1'bz) || SAXISRQTDATA[154]; // rv 1 + assign SAXISRQTDATA_in[155] = (SAXISRQTDATA[155] === 1'bz) || SAXISRQTDATA[155]; // rv 1 + assign SAXISRQTDATA_in[156] = (SAXISRQTDATA[156] === 1'bz) || SAXISRQTDATA[156]; // rv 1 + assign SAXISRQTDATA_in[157] = (SAXISRQTDATA[157] === 1'bz) || SAXISRQTDATA[157]; // rv 1 + assign SAXISRQTDATA_in[158] = (SAXISRQTDATA[158] === 1'bz) || SAXISRQTDATA[158]; // rv 1 + assign SAXISRQTDATA_in[159] = (SAXISRQTDATA[159] === 1'bz) || SAXISRQTDATA[159]; // rv 1 + assign SAXISRQTDATA_in[15] = (SAXISRQTDATA[15] === 1'bz) || SAXISRQTDATA[15]; // rv 1 + assign SAXISRQTDATA_in[160] = (SAXISRQTDATA[160] === 1'bz) || SAXISRQTDATA[160]; // rv 1 + assign SAXISRQTDATA_in[161] = (SAXISRQTDATA[161] === 1'bz) || SAXISRQTDATA[161]; // rv 1 + assign SAXISRQTDATA_in[162] = (SAXISRQTDATA[162] === 1'bz) || SAXISRQTDATA[162]; // rv 1 + assign SAXISRQTDATA_in[163] = (SAXISRQTDATA[163] === 1'bz) || SAXISRQTDATA[163]; // rv 1 + assign SAXISRQTDATA_in[164] = (SAXISRQTDATA[164] === 1'bz) || SAXISRQTDATA[164]; // rv 1 + assign SAXISRQTDATA_in[165] = (SAXISRQTDATA[165] === 1'bz) || SAXISRQTDATA[165]; // rv 1 + assign SAXISRQTDATA_in[166] = (SAXISRQTDATA[166] === 1'bz) || SAXISRQTDATA[166]; // rv 1 + assign SAXISRQTDATA_in[167] = (SAXISRQTDATA[167] === 1'bz) || SAXISRQTDATA[167]; // rv 1 + assign SAXISRQTDATA_in[168] = (SAXISRQTDATA[168] === 1'bz) || SAXISRQTDATA[168]; // rv 1 + assign SAXISRQTDATA_in[169] = (SAXISRQTDATA[169] === 1'bz) || SAXISRQTDATA[169]; // rv 1 + assign SAXISRQTDATA_in[16] = (SAXISRQTDATA[16] === 1'bz) || SAXISRQTDATA[16]; // rv 1 + assign SAXISRQTDATA_in[170] = (SAXISRQTDATA[170] === 1'bz) || SAXISRQTDATA[170]; // rv 1 + assign SAXISRQTDATA_in[171] = (SAXISRQTDATA[171] === 1'bz) || SAXISRQTDATA[171]; // rv 1 + assign SAXISRQTDATA_in[172] = (SAXISRQTDATA[172] === 1'bz) || SAXISRQTDATA[172]; // rv 1 + assign SAXISRQTDATA_in[173] = (SAXISRQTDATA[173] === 1'bz) || SAXISRQTDATA[173]; // rv 1 + assign SAXISRQTDATA_in[174] = (SAXISRQTDATA[174] === 1'bz) || SAXISRQTDATA[174]; // rv 1 + assign SAXISRQTDATA_in[175] = (SAXISRQTDATA[175] === 1'bz) || SAXISRQTDATA[175]; // rv 1 + assign SAXISRQTDATA_in[176] = (SAXISRQTDATA[176] === 1'bz) || SAXISRQTDATA[176]; // rv 1 + assign SAXISRQTDATA_in[177] = (SAXISRQTDATA[177] === 1'bz) || SAXISRQTDATA[177]; // rv 1 + assign SAXISRQTDATA_in[178] = (SAXISRQTDATA[178] === 1'bz) || SAXISRQTDATA[178]; // rv 1 + assign SAXISRQTDATA_in[179] = (SAXISRQTDATA[179] === 1'bz) || SAXISRQTDATA[179]; // rv 1 + assign SAXISRQTDATA_in[17] = (SAXISRQTDATA[17] === 1'bz) || SAXISRQTDATA[17]; // rv 1 + assign SAXISRQTDATA_in[180] = (SAXISRQTDATA[180] === 1'bz) || SAXISRQTDATA[180]; // rv 1 + assign SAXISRQTDATA_in[181] = (SAXISRQTDATA[181] === 1'bz) || SAXISRQTDATA[181]; // rv 1 + assign SAXISRQTDATA_in[182] = (SAXISRQTDATA[182] === 1'bz) || SAXISRQTDATA[182]; // rv 1 + assign SAXISRQTDATA_in[183] = (SAXISRQTDATA[183] === 1'bz) || SAXISRQTDATA[183]; // rv 1 + assign SAXISRQTDATA_in[184] = (SAXISRQTDATA[184] === 1'bz) || SAXISRQTDATA[184]; // rv 1 + assign SAXISRQTDATA_in[185] = (SAXISRQTDATA[185] === 1'bz) || SAXISRQTDATA[185]; // rv 1 + assign SAXISRQTDATA_in[186] = (SAXISRQTDATA[186] === 1'bz) || SAXISRQTDATA[186]; // rv 1 + assign SAXISRQTDATA_in[187] = (SAXISRQTDATA[187] === 1'bz) || SAXISRQTDATA[187]; // rv 1 + assign SAXISRQTDATA_in[188] = (SAXISRQTDATA[188] === 1'bz) || SAXISRQTDATA[188]; // rv 1 + assign SAXISRQTDATA_in[189] = (SAXISRQTDATA[189] === 1'bz) || SAXISRQTDATA[189]; // rv 1 + assign SAXISRQTDATA_in[18] = (SAXISRQTDATA[18] === 1'bz) || SAXISRQTDATA[18]; // rv 1 + assign SAXISRQTDATA_in[190] = (SAXISRQTDATA[190] === 1'bz) || SAXISRQTDATA[190]; // rv 1 + assign SAXISRQTDATA_in[191] = (SAXISRQTDATA[191] === 1'bz) || SAXISRQTDATA[191]; // rv 1 + assign SAXISRQTDATA_in[192] = (SAXISRQTDATA[192] === 1'bz) || SAXISRQTDATA[192]; // rv 1 + assign SAXISRQTDATA_in[193] = (SAXISRQTDATA[193] === 1'bz) || SAXISRQTDATA[193]; // rv 1 + assign SAXISRQTDATA_in[194] = (SAXISRQTDATA[194] === 1'bz) || SAXISRQTDATA[194]; // rv 1 + assign SAXISRQTDATA_in[195] = (SAXISRQTDATA[195] === 1'bz) || SAXISRQTDATA[195]; // rv 1 + assign SAXISRQTDATA_in[196] = (SAXISRQTDATA[196] === 1'bz) || SAXISRQTDATA[196]; // rv 1 + assign SAXISRQTDATA_in[197] = (SAXISRQTDATA[197] === 1'bz) || SAXISRQTDATA[197]; // rv 1 + assign SAXISRQTDATA_in[198] = (SAXISRQTDATA[198] === 1'bz) || SAXISRQTDATA[198]; // rv 1 + assign SAXISRQTDATA_in[199] = (SAXISRQTDATA[199] === 1'bz) || SAXISRQTDATA[199]; // rv 1 + assign SAXISRQTDATA_in[19] = (SAXISRQTDATA[19] === 1'bz) || SAXISRQTDATA[19]; // rv 1 + assign SAXISRQTDATA_in[1] = (SAXISRQTDATA[1] === 1'bz) || SAXISRQTDATA[1]; // rv 1 + assign SAXISRQTDATA_in[200] = (SAXISRQTDATA[200] === 1'bz) || SAXISRQTDATA[200]; // rv 1 + assign SAXISRQTDATA_in[201] = (SAXISRQTDATA[201] === 1'bz) || SAXISRQTDATA[201]; // rv 1 + assign SAXISRQTDATA_in[202] = (SAXISRQTDATA[202] === 1'bz) || SAXISRQTDATA[202]; // rv 1 + assign SAXISRQTDATA_in[203] = (SAXISRQTDATA[203] === 1'bz) || SAXISRQTDATA[203]; // rv 1 + assign SAXISRQTDATA_in[204] = (SAXISRQTDATA[204] === 1'bz) || SAXISRQTDATA[204]; // rv 1 + assign SAXISRQTDATA_in[205] = (SAXISRQTDATA[205] === 1'bz) || SAXISRQTDATA[205]; // rv 1 + assign SAXISRQTDATA_in[206] = (SAXISRQTDATA[206] === 1'bz) || SAXISRQTDATA[206]; // rv 1 + assign SAXISRQTDATA_in[207] = (SAXISRQTDATA[207] === 1'bz) || SAXISRQTDATA[207]; // rv 1 + assign SAXISRQTDATA_in[208] = (SAXISRQTDATA[208] === 1'bz) || SAXISRQTDATA[208]; // rv 1 + assign SAXISRQTDATA_in[209] = (SAXISRQTDATA[209] === 1'bz) || SAXISRQTDATA[209]; // rv 1 + assign SAXISRQTDATA_in[20] = (SAXISRQTDATA[20] === 1'bz) || SAXISRQTDATA[20]; // rv 1 + assign SAXISRQTDATA_in[210] = (SAXISRQTDATA[210] === 1'bz) || SAXISRQTDATA[210]; // rv 1 + assign SAXISRQTDATA_in[211] = (SAXISRQTDATA[211] === 1'bz) || SAXISRQTDATA[211]; // rv 1 + assign SAXISRQTDATA_in[212] = (SAXISRQTDATA[212] === 1'bz) || SAXISRQTDATA[212]; // rv 1 + assign SAXISRQTDATA_in[213] = (SAXISRQTDATA[213] === 1'bz) || SAXISRQTDATA[213]; // rv 1 + assign SAXISRQTDATA_in[214] = (SAXISRQTDATA[214] === 1'bz) || SAXISRQTDATA[214]; // rv 1 + assign SAXISRQTDATA_in[215] = (SAXISRQTDATA[215] === 1'bz) || SAXISRQTDATA[215]; // rv 1 + assign SAXISRQTDATA_in[216] = (SAXISRQTDATA[216] === 1'bz) || SAXISRQTDATA[216]; // rv 1 + assign SAXISRQTDATA_in[217] = (SAXISRQTDATA[217] === 1'bz) || SAXISRQTDATA[217]; // rv 1 + assign SAXISRQTDATA_in[218] = (SAXISRQTDATA[218] === 1'bz) || SAXISRQTDATA[218]; // rv 1 + assign SAXISRQTDATA_in[219] = (SAXISRQTDATA[219] === 1'bz) || SAXISRQTDATA[219]; // rv 1 + assign SAXISRQTDATA_in[21] = (SAXISRQTDATA[21] === 1'bz) || SAXISRQTDATA[21]; // rv 1 + assign SAXISRQTDATA_in[220] = (SAXISRQTDATA[220] === 1'bz) || SAXISRQTDATA[220]; // rv 1 + assign SAXISRQTDATA_in[221] = (SAXISRQTDATA[221] === 1'bz) || SAXISRQTDATA[221]; // rv 1 + assign SAXISRQTDATA_in[222] = (SAXISRQTDATA[222] === 1'bz) || SAXISRQTDATA[222]; // rv 1 + assign SAXISRQTDATA_in[223] = (SAXISRQTDATA[223] === 1'bz) || SAXISRQTDATA[223]; // rv 1 + assign SAXISRQTDATA_in[224] = (SAXISRQTDATA[224] === 1'bz) || SAXISRQTDATA[224]; // rv 1 + assign SAXISRQTDATA_in[225] = (SAXISRQTDATA[225] === 1'bz) || SAXISRQTDATA[225]; // rv 1 + assign SAXISRQTDATA_in[226] = (SAXISRQTDATA[226] === 1'bz) || SAXISRQTDATA[226]; // rv 1 + assign SAXISRQTDATA_in[227] = (SAXISRQTDATA[227] === 1'bz) || SAXISRQTDATA[227]; // rv 1 + assign SAXISRQTDATA_in[228] = (SAXISRQTDATA[228] === 1'bz) || SAXISRQTDATA[228]; // rv 1 + assign SAXISRQTDATA_in[229] = (SAXISRQTDATA[229] === 1'bz) || SAXISRQTDATA[229]; // rv 1 + assign SAXISRQTDATA_in[22] = (SAXISRQTDATA[22] === 1'bz) || SAXISRQTDATA[22]; // rv 1 + assign SAXISRQTDATA_in[230] = (SAXISRQTDATA[230] === 1'bz) || SAXISRQTDATA[230]; // rv 1 + assign SAXISRQTDATA_in[231] = (SAXISRQTDATA[231] === 1'bz) || SAXISRQTDATA[231]; // rv 1 + assign SAXISRQTDATA_in[232] = (SAXISRQTDATA[232] === 1'bz) || SAXISRQTDATA[232]; // rv 1 + assign SAXISRQTDATA_in[233] = (SAXISRQTDATA[233] === 1'bz) || SAXISRQTDATA[233]; // rv 1 + assign SAXISRQTDATA_in[234] = (SAXISRQTDATA[234] === 1'bz) || SAXISRQTDATA[234]; // rv 1 + assign SAXISRQTDATA_in[235] = (SAXISRQTDATA[235] === 1'bz) || SAXISRQTDATA[235]; // rv 1 + assign SAXISRQTDATA_in[236] = (SAXISRQTDATA[236] === 1'bz) || SAXISRQTDATA[236]; // rv 1 + assign SAXISRQTDATA_in[237] = (SAXISRQTDATA[237] === 1'bz) || SAXISRQTDATA[237]; // rv 1 + assign SAXISRQTDATA_in[238] = (SAXISRQTDATA[238] === 1'bz) || SAXISRQTDATA[238]; // rv 1 + assign SAXISRQTDATA_in[239] = (SAXISRQTDATA[239] === 1'bz) || SAXISRQTDATA[239]; // rv 1 + assign SAXISRQTDATA_in[23] = (SAXISRQTDATA[23] === 1'bz) || SAXISRQTDATA[23]; // rv 1 + assign SAXISRQTDATA_in[240] = (SAXISRQTDATA[240] === 1'bz) || SAXISRQTDATA[240]; // rv 1 + assign SAXISRQTDATA_in[241] = (SAXISRQTDATA[241] === 1'bz) || SAXISRQTDATA[241]; // rv 1 + assign SAXISRQTDATA_in[242] = (SAXISRQTDATA[242] === 1'bz) || SAXISRQTDATA[242]; // rv 1 + assign SAXISRQTDATA_in[243] = (SAXISRQTDATA[243] === 1'bz) || SAXISRQTDATA[243]; // rv 1 + assign SAXISRQTDATA_in[244] = (SAXISRQTDATA[244] === 1'bz) || SAXISRQTDATA[244]; // rv 1 + assign SAXISRQTDATA_in[245] = (SAXISRQTDATA[245] === 1'bz) || SAXISRQTDATA[245]; // rv 1 + assign SAXISRQTDATA_in[246] = (SAXISRQTDATA[246] === 1'bz) || SAXISRQTDATA[246]; // rv 1 + assign SAXISRQTDATA_in[247] = (SAXISRQTDATA[247] === 1'bz) || SAXISRQTDATA[247]; // rv 1 + assign SAXISRQTDATA_in[248] = (SAXISRQTDATA[248] === 1'bz) || SAXISRQTDATA[248]; // rv 1 + assign SAXISRQTDATA_in[249] = (SAXISRQTDATA[249] === 1'bz) || SAXISRQTDATA[249]; // rv 1 + assign SAXISRQTDATA_in[24] = (SAXISRQTDATA[24] === 1'bz) || SAXISRQTDATA[24]; // rv 1 + assign SAXISRQTDATA_in[250] = (SAXISRQTDATA[250] === 1'bz) || SAXISRQTDATA[250]; // rv 1 + assign SAXISRQTDATA_in[251] = (SAXISRQTDATA[251] === 1'bz) || SAXISRQTDATA[251]; // rv 1 + assign SAXISRQTDATA_in[252] = (SAXISRQTDATA[252] === 1'bz) || SAXISRQTDATA[252]; // rv 1 + assign SAXISRQTDATA_in[253] = (SAXISRQTDATA[253] === 1'bz) || SAXISRQTDATA[253]; // rv 1 + assign SAXISRQTDATA_in[254] = (SAXISRQTDATA[254] === 1'bz) || SAXISRQTDATA[254]; // rv 1 + assign SAXISRQTDATA_in[255] = (SAXISRQTDATA[255] === 1'bz) || SAXISRQTDATA[255]; // rv 1 + assign SAXISRQTDATA_in[25] = (SAXISRQTDATA[25] === 1'bz) || SAXISRQTDATA[25]; // rv 1 + assign SAXISRQTDATA_in[26] = (SAXISRQTDATA[26] === 1'bz) || SAXISRQTDATA[26]; // rv 1 + assign SAXISRQTDATA_in[27] = (SAXISRQTDATA[27] === 1'bz) || SAXISRQTDATA[27]; // rv 1 + assign SAXISRQTDATA_in[28] = (SAXISRQTDATA[28] === 1'bz) || SAXISRQTDATA[28]; // rv 1 + assign SAXISRQTDATA_in[29] = (SAXISRQTDATA[29] === 1'bz) || SAXISRQTDATA[29]; // rv 1 + assign SAXISRQTDATA_in[2] = (SAXISRQTDATA[2] === 1'bz) || SAXISRQTDATA[2]; // rv 1 + assign SAXISRQTDATA_in[30] = (SAXISRQTDATA[30] === 1'bz) || SAXISRQTDATA[30]; // rv 1 + assign SAXISRQTDATA_in[31] = (SAXISRQTDATA[31] === 1'bz) || SAXISRQTDATA[31]; // rv 1 + assign SAXISRQTDATA_in[32] = (SAXISRQTDATA[32] === 1'bz) || SAXISRQTDATA[32]; // rv 1 + assign SAXISRQTDATA_in[33] = (SAXISRQTDATA[33] === 1'bz) || SAXISRQTDATA[33]; // rv 1 + assign SAXISRQTDATA_in[34] = (SAXISRQTDATA[34] === 1'bz) || SAXISRQTDATA[34]; // rv 1 + assign SAXISRQTDATA_in[35] = (SAXISRQTDATA[35] === 1'bz) || SAXISRQTDATA[35]; // rv 1 + assign SAXISRQTDATA_in[36] = (SAXISRQTDATA[36] === 1'bz) || SAXISRQTDATA[36]; // rv 1 + assign SAXISRQTDATA_in[37] = (SAXISRQTDATA[37] === 1'bz) || SAXISRQTDATA[37]; // rv 1 + assign SAXISRQTDATA_in[38] = (SAXISRQTDATA[38] === 1'bz) || SAXISRQTDATA[38]; // rv 1 + assign SAXISRQTDATA_in[39] = (SAXISRQTDATA[39] === 1'bz) || SAXISRQTDATA[39]; // rv 1 + assign SAXISRQTDATA_in[3] = (SAXISRQTDATA[3] === 1'bz) || SAXISRQTDATA[3]; // rv 1 + assign SAXISRQTDATA_in[40] = (SAXISRQTDATA[40] === 1'bz) || SAXISRQTDATA[40]; // rv 1 + assign SAXISRQTDATA_in[41] = (SAXISRQTDATA[41] === 1'bz) || SAXISRQTDATA[41]; // rv 1 + assign SAXISRQTDATA_in[42] = (SAXISRQTDATA[42] === 1'bz) || SAXISRQTDATA[42]; // rv 1 + assign SAXISRQTDATA_in[43] = (SAXISRQTDATA[43] === 1'bz) || SAXISRQTDATA[43]; // rv 1 + assign SAXISRQTDATA_in[44] = (SAXISRQTDATA[44] === 1'bz) || SAXISRQTDATA[44]; // rv 1 + assign SAXISRQTDATA_in[45] = (SAXISRQTDATA[45] === 1'bz) || SAXISRQTDATA[45]; // rv 1 + assign SAXISRQTDATA_in[46] = (SAXISRQTDATA[46] === 1'bz) || SAXISRQTDATA[46]; // rv 1 + assign SAXISRQTDATA_in[47] = (SAXISRQTDATA[47] === 1'bz) || SAXISRQTDATA[47]; // rv 1 + assign SAXISRQTDATA_in[48] = (SAXISRQTDATA[48] === 1'bz) || SAXISRQTDATA[48]; // rv 1 + assign SAXISRQTDATA_in[49] = (SAXISRQTDATA[49] === 1'bz) || SAXISRQTDATA[49]; // rv 1 + assign SAXISRQTDATA_in[4] = (SAXISRQTDATA[4] === 1'bz) || SAXISRQTDATA[4]; // rv 1 + assign SAXISRQTDATA_in[50] = (SAXISRQTDATA[50] === 1'bz) || SAXISRQTDATA[50]; // rv 1 + assign SAXISRQTDATA_in[51] = (SAXISRQTDATA[51] === 1'bz) || SAXISRQTDATA[51]; // rv 1 + assign SAXISRQTDATA_in[52] = (SAXISRQTDATA[52] === 1'bz) || SAXISRQTDATA[52]; // rv 1 + assign SAXISRQTDATA_in[53] = (SAXISRQTDATA[53] === 1'bz) || SAXISRQTDATA[53]; // rv 1 + assign SAXISRQTDATA_in[54] = (SAXISRQTDATA[54] === 1'bz) || SAXISRQTDATA[54]; // rv 1 + assign SAXISRQTDATA_in[55] = (SAXISRQTDATA[55] === 1'bz) || SAXISRQTDATA[55]; // rv 1 + assign SAXISRQTDATA_in[56] = (SAXISRQTDATA[56] === 1'bz) || SAXISRQTDATA[56]; // rv 1 + assign SAXISRQTDATA_in[57] = (SAXISRQTDATA[57] === 1'bz) || SAXISRQTDATA[57]; // rv 1 + assign SAXISRQTDATA_in[58] = (SAXISRQTDATA[58] === 1'bz) || SAXISRQTDATA[58]; // rv 1 + assign SAXISRQTDATA_in[59] = (SAXISRQTDATA[59] === 1'bz) || SAXISRQTDATA[59]; // rv 1 + assign SAXISRQTDATA_in[5] = (SAXISRQTDATA[5] === 1'bz) || SAXISRQTDATA[5]; // rv 1 + assign SAXISRQTDATA_in[60] = (SAXISRQTDATA[60] === 1'bz) || SAXISRQTDATA[60]; // rv 1 + assign SAXISRQTDATA_in[61] = (SAXISRQTDATA[61] === 1'bz) || SAXISRQTDATA[61]; // rv 1 + assign SAXISRQTDATA_in[62] = (SAXISRQTDATA[62] === 1'bz) || SAXISRQTDATA[62]; // rv 1 + assign SAXISRQTDATA_in[63] = (SAXISRQTDATA[63] === 1'bz) || SAXISRQTDATA[63]; // rv 1 + assign SAXISRQTDATA_in[64] = (SAXISRQTDATA[64] === 1'bz) || SAXISRQTDATA[64]; // rv 1 + assign SAXISRQTDATA_in[65] = (SAXISRQTDATA[65] === 1'bz) || SAXISRQTDATA[65]; // rv 1 + assign SAXISRQTDATA_in[66] = (SAXISRQTDATA[66] === 1'bz) || SAXISRQTDATA[66]; // rv 1 + assign SAXISRQTDATA_in[67] = (SAXISRQTDATA[67] === 1'bz) || SAXISRQTDATA[67]; // rv 1 + assign SAXISRQTDATA_in[68] = (SAXISRQTDATA[68] === 1'bz) || SAXISRQTDATA[68]; // rv 1 + assign SAXISRQTDATA_in[69] = (SAXISRQTDATA[69] === 1'bz) || SAXISRQTDATA[69]; // rv 1 + assign SAXISRQTDATA_in[6] = (SAXISRQTDATA[6] === 1'bz) || SAXISRQTDATA[6]; // rv 1 + assign SAXISRQTDATA_in[70] = (SAXISRQTDATA[70] === 1'bz) || SAXISRQTDATA[70]; // rv 1 + assign SAXISRQTDATA_in[71] = (SAXISRQTDATA[71] === 1'bz) || SAXISRQTDATA[71]; // rv 1 + assign SAXISRQTDATA_in[72] = (SAXISRQTDATA[72] === 1'bz) || SAXISRQTDATA[72]; // rv 1 + assign SAXISRQTDATA_in[73] = (SAXISRQTDATA[73] === 1'bz) || SAXISRQTDATA[73]; // rv 1 + assign SAXISRQTDATA_in[74] = (SAXISRQTDATA[74] === 1'bz) || SAXISRQTDATA[74]; // rv 1 + assign SAXISRQTDATA_in[75] = (SAXISRQTDATA[75] === 1'bz) || SAXISRQTDATA[75]; // rv 1 + assign SAXISRQTDATA_in[76] = (SAXISRQTDATA[76] === 1'bz) || SAXISRQTDATA[76]; // rv 1 + assign SAXISRQTDATA_in[77] = (SAXISRQTDATA[77] === 1'bz) || SAXISRQTDATA[77]; // rv 1 + assign SAXISRQTDATA_in[78] = (SAXISRQTDATA[78] === 1'bz) || SAXISRQTDATA[78]; // rv 1 + assign SAXISRQTDATA_in[79] = (SAXISRQTDATA[79] === 1'bz) || SAXISRQTDATA[79]; // rv 1 + assign SAXISRQTDATA_in[7] = (SAXISRQTDATA[7] === 1'bz) || SAXISRQTDATA[7]; // rv 1 + assign SAXISRQTDATA_in[80] = (SAXISRQTDATA[80] === 1'bz) || SAXISRQTDATA[80]; // rv 1 + assign SAXISRQTDATA_in[81] = (SAXISRQTDATA[81] === 1'bz) || SAXISRQTDATA[81]; // rv 1 + assign SAXISRQTDATA_in[82] = (SAXISRQTDATA[82] === 1'bz) || SAXISRQTDATA[82]; // rv 1 + assign SAXISRQTDATA_in[83] = (SAXISRQTDATA[83] === 1'bz) || SAXISRQTDATA[83]; // rv 1 + assign SAXISRQTDATA_in[84] = (SAXISRQTDATA[84] === 1'bz) || SAXISRQTDATA[84]; // rv 1 + assign SAXISRQTDATA_in[85] = (SAXISRQTDATA[85] === 1'bz) || SAXISRQTDATA[85]; // rv 1 + assign SAXISRQTDATA_in[86] = (SAXISRQTDATA[86] === 1'bz) || SAXISRQTDATA[86]; // rv 1 + assign SAXISRQTDATA_in[87] = (SAXISRQTDATA[87] === 1'bz) || SAXISRQTDATA[87]; // rv 1 + assign SAXISRQTDATA_in[88] = (SAXISRQTDATA[88] === 1'bz) || SAXISRQTDATA[88]; // rv 1 + assign SAXISRQTDATA_in[89] = (SAXISRQTDATA[89] === 1'bz) || SAXISRQTDATA[89]; // rv 1 + assign SAXISRQTDATA_in[8] = (SAXISRQTDATA[8] === 1'bz) || SAXISRQTDATA[8]; // rv 1 + assign SAXISRQTDATA_in[90] = (SAXISRQTDATA[90] === 1'bz) || SAXISRQTDATA[90]; // rv 1 + assign SAXISRQTDATA_in[91] = (SAXISRQTDATA[91] === 1'bz) || SAXISRQTDATA[91]; // rv 1 + assign SAXISRQTDATA_in[92] = (SAXISRQTDATA[92] === 1'bz) || SAXISRQTDATA[92]; // rv 1 + assign SAXISRQTDATA_in[93] = (SAXISRQTDATA[93] === 1'bz) || SAXISRQTDATA[93]; // rv 1 + assign SAXISRQTDATA_in[94] = (SAXISRQTDATA[94] === 1'bz) || SAXISRQTDATA[94]; // rv 1 + assign SAXISRQTDATA_in[95] = (SAXISRQTDATA[95] === 1'bz) || SAXISRQTDATA[95]; // rv 1 + assign SAXISRQTDATA_in[96] = (SAXISRQTDATA[96] === 1'bz) || SAXISRQTDATA[96]; // rv 1 + assign SAXISRQTDATA_in[97] = (SAXISRQTDATA[97] === 1'bz) || SAXISRQTDATA[97]; // rv 1 + assign SAXISRQTDATA_in[98] = (SAXISRQTDATA[98] === 1'bz) || SAXISRQTDATA[98]; // rv 1 + assign SAXISRQTDATA_in[99] = (SAXISRQTDATA[99] === 1'bz) || SAXISRQTDATA[99]; // rv 1 + assign SAXISRQTDATA_in[9] = (SAXISRQTDATA[9] === 1'bz) || SAXISRQTDATA[9]; // rv 1 + assign SAXISRQTKEEP_in[0] = (SAXISRQTKEEP[0] !== 1'bz) && SAXISRQTKEEP[0]; // rv 0 + assign SAXISRQTKEEP_in[1] = (SAXISRQTKEEP[1] !== 1'bz) && SAXISRQTKEEP[1]; // rv 0 + assign SAXISRQTKEEP_in[2] = (SAXISRQTKEEP[2] !== 1'bz) && SAXISRQTKEEP[2]; // rv 0 + assign SAXISRQTKEEP_in[3] = (SAXISRQTKEEP[3] !== 1'bz) && SAXISRQTKEEP[3]; // rv 0 + assign SAXISRQTKEEP_in[4] = (SAXISRQTKEEP[4] !== 1'bz) && SAXISRQTKEEP[4]; // rv 0 + assign SAXISRQTKEEP_in[5] = (SAXISRQTKEEP[5] !== 1'bz) && SAXISRQTKEEP[5]; // rv 0 + assign SAXISRQTKEEP_in[6] = (SAXISRQTKEEP[6] !== 1'bz) && SAXISRQTKEEP[6]; // rv 0 + assign SAXISRQTKEEP_in[7] = (SAXISRQTKEEP[7] !== 1'bz) && SAXISRQTKEEP[7]; // rv 0 + assign SAXISRQTLAST_in = (SAXISRQTLAST === 1'bz) || SAXISRQTLAST; // rv 1 + assign SAXISRQTUSER_in[0] = (SAXISRQTUSER[0] === 1'bz) || SAXISRQTUSER[0]; // rv 1 + assign SAXISRQTUSER_in[10] = (SAXISRQTUSER[10] === 1'bz) || SAXISRQTUSER[10]; // rv 1 + assign SAXISRQTUSER_in[11] = (SAXISRQTUSER[11] === 1'bz) || SAXISRQTUSER[11]; // rv 1 + assign SAXISRQTUSER_in[12] = (SAXISRQTUSER[12] === 1'bz) || SAXISRQTUSER[12]; // rv 1 + assign SAXISRQTUSER_in[13] = (SAXISRQTUSER[13] === 1'bz) || SAXISRQTUSER[13]; // rv 1 + assign SAXISRQTUSER_in[14] = (SAXISRQTUSER[14] === 1'bz) || SAXISRQTUSER[14]; // rv 1 + assign SAXISRQTUSER_in[15] = (SAXISRQTUSER[15] === 1'bz) || SAXISRQTUSER[15]; // rv 1 + assign SAXISRQTUSER_in[16] = (SAXISRQTUSER[16] === 1'bz) || SAXISRQTUSER[16]; // rv 1 + assign SAXISRQTUSER_in[17] = (SAXISRQTUSER[17] === 1'bz) || SAXISRQTUSER[17]; // rv 1 + assign SAXISRQTUSER_in[18] = (SAXISRQTUSER[18] === 1'bz) || SAXISRQTUSER[18]; // rv 1 + assign SAXISRQTUSER_in[19] = (SAXISRQTUSER[19] === 1'bz) || SAXISRQTUSER[19]; // rv 1 + assign SAXISRQTUSER_in[1] = (SAXISRQTUSER[1] === 1'bz) || SAXISRQTUSER[1]; // rv 1 + assign SAXISRQTUSER_in[20] = (SAXISRQTUSER[20] === 1'bz) || SAXISRQTUSER[20]; // rv 1 + assign SAXISRQTUSER_in[21] = (SAXISRQTUSER[21] === 1'bz) || SAXISRQTUSER[21]; // rv 1 + assign SAXISRQTUSER_in[22] = (SAXISRQTUSER[22] === 1'bz) || SAXISRQTUSER[22]; // rv 1 + assign SAXISRQTUSER_in[23] = (SAXISRQTUSER[23] === 1'bz) || SAXISRQTUSER[23]; // rv 1 + assign SAXISRQTUSER_in[24] = (SAXISRQTUSER[24] === 1'bz) || SAXISRQTUSER[24]; // rv 1 + assign SAXISRQTUSER_in[25] = (SAXISRQTUSER[25] === 1'bz) || SAXISRQTUSER[25]; // rv 1 + assign SAXISRQTUSER_in[26] = (SAXISRQTUSER[26] === 1'bz) || SAXISRQTUSER[26]; // rv 1 + assign SAXISRQTUSER_in[27] = (SAXISRQTUSER[27] === 1'bz) || SAXISRQTUSER[27]; // rv 1 + assign SAXISRQTUSER_in[28] = (SAXISRQTUSER[28] === 1'bz) || SAXISRQTUSER[28]; // rv 1 + assign SAXISRQTUSER_in[29] = (SAXISRQTUSER[29] === 1'bz) || SAXISRQTUSER[29]; // rv 1 + assign SAXISRQTUSER_in[2] = (SAXISRQTUSER[2] === 1'bz) || SAXISRQTUSER[2]; // rv 1 + assign SAXISRQTUSER_in[30] = (SAXISRQTUSER[30] === 1'bz) || SAXISRQTUSER[30]; // rv 1 + assign SAXISRQTUSER_in[31] = (SAXISRQTUSER[31] === 1'bz) || SAXISRQTUSER[31]; // rv 1 + assign SAXISRQTUSER_in[32] = (SAXISRQTUSER[32] === 1'bz) || SAXISRQTUSER[32]; // rv 1 + assign SAXISRQTUSER_in[33] = (SAXISRQTUSER[33] === 1'bz) || SAXISRQTUSER[33]; // rv 1 + assign SAXISRQTUSER_in[34] = (SAXISRQTUSER[34] === 1'bz) || SAXISRQTUSER[34]; // rv 1 + assign SAXISRQTUSER_in[35] = (SAXISRQTUSER[35] === 1'bz) || SAXISRQTUSER[35]; // rv 1 + assign SAXISRQTUSER_in[36] = (SAXISRQTUSER[36] === 1'bz) || SAXISRQTUSER[36]; // rv 1 + assign SAXISRQTUSER_in[37] = (SAXISRQTUSER[37] === 1'bz) || SAXISRQTUSER[37]; // rv 1 + assign SAXISRQTUSER_in[38] = (SAXISRQTUSER[38] === 1'bz) || SAXISRQTUSER[38]; // rv 1 + assign SAXISRQTUSER_in[39] = (SAXISRQTUSER[39] === 1'bz) || SAXISRQTUSER[39]; // rv 1 + assign SAXISRQTUSER_in[3] = (SAXISRQTUSER[3] === 1'bz) || SAXISRQTUSER[3]; // rv 1 + assign SAXISRQTUSER_in[40] = (SAXISRQTUSER[40] === 1'bz) || SAXISRQTUSER[40]; // rv 1 + assign SAXISRQTUSER_in[41] = (SAXISRQTUSER[41] === 1'bz) || SAXISRQTUSER[41]; // rv 1 + assign SAXISRQTUSER_in[42] = (SAXISRQTUSER[42] === 1'bz) || SAXISRQTUSER[42]; // rv 1 + assign SAXISRQTUSER_in[43] = (SAXISRQTUSER[43] === 1'bz) || SAXISRQTUSER[43]; // rv 1 + assign SAXISRQTUSER_in[44] = (SAXISRQTUSER[44] === 1'bz) || SAXISRQTUSER[44]; // rv 1 + assign SAXISRQTUSER_in[45] = (SAXISRQTUSER[45] === 1'bz) || SAXISRQTUSER[45]; // rv 1 + assign SAXISRQTUSER_in[46] = (SAXISRQTUSER[46] === 1'bz) || SAXISRQTUSER[46]; // rv 1 + assign SAXISRQTUSER_in[47] = (SAXISRQTUSER[47] === 1'bz) || SAXISRQTUSER[47]; // rv 1 + assign SAXISRQTUSER_in[48] = (SAXISRQTUSER[48] === 1'bz) || SAXISRQTUSER[48]; // rv 1 + assign SAXISRQTUSER_in[49] = (SAXISRQTUSER[49] === 1'bz) || SAXISRQTUSER[49]; // rv 1 + assign SAXISRQTUSER_in[4] = (SAXISRQTUSER[4] === 1'bz) || SAXISRQTUSER[4]; // rv 1 + assign SAXISRQTUSER_in[50] = (SAXISRQTUSER[50] === 1'bz) || SAXISRQTUSER[50]; // rv 1 + assign SAXISRQTUSER_in[51] = (SAXISRQTUSER[51] === 1'bz) || SAXISRQTUSER[51]; // rv 1 + assign SAXISRQTUSER_in[52] = (SAXISRQTUSER[52] === 1'bz) || SAXISRQTUSER[52]; // rv 1 + assign SAXISRQTUSER_in[53] = (SAXISRQTUSER[53] === 1'bz) || SAXISRQTUSER[53]; // rv 1 + assign SAXISRQTUSER_in[54] = (SAXISRQTUSER[54] === 1'bz) || SAXISRQTUSER[54]; // rv 1 + assign SAXISRQTUSER_in[55] = (SAXISRQTUSER[55] === 1'bz) || SAXISRQTUSER[55]; // rv 1 + assign SAXISRQTUSER_in[56] = (SAXISRQTUSER[56] === 1'bz) || SAXISRQTUSER[56]; // rv 1 + assign SAXISRQTUSER_in[57] = (SAXISRQTUSER[57] === 1'bz) || SAXISRQTUSER[57]; // rv 1 + assign SAXISRQTUSER_in[58] = (SAXISRQTUSER[58] === 1'bz) || SAXISRQTUSER[58]; // rv 1 + assign SAXISRQTUSER_in[59] = (SAXISRQTUSER[59] === 1'bz) || SAXISRQTUSER[59]; // rv 1 + assign SAXISRQTUSER_in[5] = (SAXISRQTUSER[5] === 1'bz) || SAXISRQTUSER[5]; // rv 1 + assign SAXISRQTUSER_in[60] = (SAXISRQTUSER[60] === 1'bz) || SAXISRQTUSER[60]; // rv 1 + assign SAXISRQTUSER_in[61] = (SAXISRQTUSER[61] === 1'bz) || SAXISRQTUSER[61]; // rv 1 + assign SAXISRQTUSER_in[6] = (SAXISRQTUSER[6] === 1'bz) || SAXISRQTUSER[6]; // rv 1 + assign SAXISRQTUSER_in[7] = (SAXISRQTUSER[7] === 1'bz) || SAXISRQTUSER[7]; // rv 1 + assign SAXISRQTUSER_in[8] = (SAXISRQTUSER[8] === 1'bz) || SAXISRQTUSER[8]; // rv 1 + assign SAXISRQTUSER_in[9] = (SAXISRQTUSER[9] === 1'bz) || SAXISRQTUSER[9]; // rv 1 + assign SAXISRQTVALID_in = (SAXISRQTVALID !== 1'bz) && SAXISRQTVALID; // rv 0 + assign USERCLKEN_in = (USERCLKEN !== 1'bz) && USERCLKEN; // rv 0 + assign USERSPAREIN_in[0] = (USERSPAREIN[0] === 1'bz) || USERSPAREIN[0]; // rv 1 + assign USERSPAREIN_in[10] = (USERSPAREIN[10] === 1'bz) || USERSPAREIN[10]; // rv 1 + assign USERSPAREIN_in[11] = (USERSPAREIN[11] === 1'bz) || USERSPAREIN[11]; // rv 1 + assign USERSPAREIN_in[12] = (USERSPAREIN[12] === 1'bz) || USERSPAREIN[12]; // rv 1 + assign USERSPAREIN_in[13] = (USERSPAREIN[13] === 1'bz) || USERSPAREIN[13]; // rv 1 + assign USERSPAREIN_in[14] = (USERSPAREIN[14] === 1'bz) || USERSPAREIN[14]; // rv 1 + assign USERSPAREIN_in[15] = (USERSPAREIN[15] === 1'bz) || USERSPAREIN[15]; // rv 1 + assign USERSPAREIN_in[16] = (USERSPAREIN[16] === 1'bz) || USERSPAREIN[16]; // rv 1 + assign USERSPAREIN_in[17] = (USERSPAREIN[17] === 1'bz) || USERSPAREIN[17]; // rv 1 + assign USERSPAREIN_in[18] = (USERSPAREIN[18] === 1'bz) || USERSPAREIN[18]; // rv 1 + assign USERSPAREIN_in[19] = (USERSPAREIN[19] === 1'bz) || USERSPAREIN[19]; // rv 1 + assign USERSPAREIN_in[1] = (USERSPAREIN[1] === 1'bz) || USERSPAREIN[1]; // rv 1 + assign USERSPAREIN_in[20] = (USERSPAREIN[20] === 1'bz) || USERSPAREIN[20]; // rv 1 + assign USERSPAREIN_in[21] = (USERSPAREIN[21] === 1'bz) || USERSPAREIN[21]; // rv 1 + assign USERSPAREIN_in[22] = (USERSPAREIN[22] === 1'bz) || USERSPAREIN[22]; // rv 1 + assign USERSPAREIN_in[23] = (USERSPAREIN[23] === 1'bz) || USERSPAREIN[23]; // rv 1 + assign USERSPAREIN_in[24] = (USERSPAREIN[24] === 1'bz) || USERSPAREIN[24]; // rv 1 + assign USERSPAREIN_in[25] = (USERSPAREIN[25] === 1'bz) || USERSPAREIN[25]; // rv 1 + assign USERSPAREIN_in[26] = (USERSPAREIN[26] === 1'bz) || USERSPAREIN[26]; // rv 1 + assign USERSPAREIN_in[27] = (USERSPAREIN[27] === 1'bz) || USERSPAREIN[27]; // rv 1 + assign USERSPAREIN_in[28] = (USERSPAREIN[28] === 1'bz) || USERSPAREIN[28]; // rv 1 + assign USERSPAREIN_in[29] = (USERSPAREIN[29] === 1'bz) || USERSPAREIN[29]; // rv 1 + assign USERSPAREIN_in[2] = (USERSPAREIN[2] === 1'bz) || USERSPAREIN[2]; // rv 1 + assign USERSPAREIN_in[30] = (USERSPAREIN[30] === 1'bz) || USERSPAREIN[30]; // rv 1 + assign USERSPAREIN_in[31] = (USERSPAREIN[31] === 1'bz) || USERSPAREIN[31]; // rv 1 + assign USERSPAREIN_in[3] = (USERSPAREIN[3] === 1'bz) || USERSPAREIN[3]; // rv 1 + assign USERSPAREIN_in[4] = (USERSPAREIN[4] === 1'bz) || USERSPAREIN[4]; // rv 1 + assign USERSPAREIN_in[5] = (USERSPAREIN[5] === 1'bz) || USERSPAREIN[5]; // rv 1 + assign USERSPAREIN_in[6] = (USERSPAREIN[6] === 1'bz) || USERSPAREIN[6]; // rv 1 + assign USERSPAREIN_in[7] = (USERSPAREIN[7] === 1'bz) || USERSPAREIN[7]; // rv 1 + assign USERSPAREIN_in[8] = (USERSPAREIN[8] === 1'bz) || USERSPAREIN[8]; // rv 1 + assign USERSPAREIN_in[9] = (USERSPAREIN[9] === 1'bz) || USERSPAREIN[9]; // rv 1 +`endif + + assign CCIXRXCORRECTABLEERRORDETECTED_in = (CCIXRXCORRECTABLEERRORDETECTED !== 1'bz) && CCIXRXCORRECTABLEERRORDETECTED; // rv 0 + assign CCIXRXFIFOOVERFLOW_in = (CCIXRXFIFOOVERFLOW !== 1'bz) && CCIXRXFIFOOVERFLOW; // rv 0 + assign CCIXRXUNCORRECTABLEERRORDETECTED_in = (CCIXRXUNCORRECTABLEERRORDETECTED !== 1'bz) && CCIXRXUNCORRECTABLEERRORDETECTED; // rv 0 + assign CORECLKCCIX_in = (CORECLKCCIX !== 1'bz) && CORECLKCCIX; // rv 0 + assign CORECLKMIREPLAYRAM0_in = (CORECLKMIREPLAYRAM0 !== 1'bz) && CORECLKMIREPLAYRAM0; // rv 0 + assign CORECLKMIREPLAYRAM1_in = (CORECLKMIREPLAYRAM1 !== 1'bz) && CORECLKMIREPLAYRAM1; // rv 0 + assign CORECLKMIRXCOMPLETIONRAM0_in = (CORECLKMIRXCOMPLETIONRAM0 !== 1'bz) && CORECLKMIRXCOMPLETIONRAM0; // rv 0 + assign CORECLKMIRXCOMPLETIONRAM1_in = (CORECLKMIRXCOMPLETIONRAM1 !== 1'bz) && CORECLKMIRXCOMPLETIONRAM1; // rv 0 + assign CORECLKMIRXPOSTEDREQUESTRAM0_in = (CORECLKMIRXPOSTEDREQUESTRAM0 !== 1'bz) && CORECLKMIRXPOSTEDREQUESTRAM0; // rv 0 + assign CORECLKMIRXPOSTEDREQUESTRAM1_in = (CORECLKMIRXPOSTEDREQUESTRAM1 !== 1'bz) && CORECLKMIRXPOSTEDREQUESTRAM1; // rv 0 + assign MCAPCLK_in = (MCAPCLK !== 1'bz) && MCAPCLK; // rv 0 + assign MCAPPERST0B_in = (MCAPPERST0B === 1'bz) || MCAPPERST0B; // rv 1 + assign MCAPPERST1B_in = (MCAPPERST1B === 1'bz) || MCAPPERST1B; // rv 1 + assign MGMTRESETN_in = (MGMTRESETN !== 1'bz) && MGMTRESETN; // rv 0 + assign MGMTSTICKYRESETN_in = (MGMTSTICKYRESETN !== 1'bz) && MGMTSTICKYRESETN; // rv 0 + assign PIPECLKEN_in = (PIPECLKEN !== 1'bz) && PIPECLKEN; // rv 0 + assign PIPERESETN_in = (PIPERESETN !== 1'bz) && PIPERESETN; // rv 0 + assign PLEQRESETEIEOSCOUNT_in = (PLEQRESETEIEOSCOUNT !== 1'bz) && PLEQRESETEIEOSCOUNT; // rv 0 + assign RESETN_in = (RESETN !== 1'bz) && RESETN; // rv 0 + assign USERCLK2_in = (USERCLK2 !== 1'bz) && USERCLK2; // rv 0 + assign USERCLK_in = (USERCLK !== 1'bz) && USERCLK; // rv 0 + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ARI_CAP_ENABLE_REG != "FALSE") && + (ARI_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] ARI_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ARI_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AUTO_FLR_RESPONSE_REG != "FALSE") && + (AUTO_FLR_RESPONSE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] AUTO_FLR_RESPONSE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AUTO_FLR_RESPONSE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_CCIX_TX_REGISTERED_TREADY_REG != "FALSE") && + (AXISTEN_IF_CCIX_TX_REGISTERED_TREADY_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] AXISTEN_IF_CCIX_TX_REGISTERED_TREADY attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_CCIX_TX_REGISTERED_TREADY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG != "FALSE") && + (AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] AXISTEN_IF_CQ_EN_POISONED_MEM_WR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_256_TAGS_REG != "FALSE") && + (AXISTEN_IF_ENABLE_256_TAGS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] AXISTEN_IF_ENABLE_256_TAGS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_256_TAGS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "FALSE") && + (AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] AXISTEN_IF_ENABLE_CLIENT_TAG attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_CLIENT_TAG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG != "FALSE") && + (AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG != "TRUE") && + (AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-114] AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "FALSE") && + (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-116] AXISTEN_IF_ENABLE_RX_MSG_INTFC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_REG != "FALSE") && + (AXISTEN_IF_EXT_512_REG != "TRUE"))) begin + $display("Error: [Unisim %s-117] AXISTEN_IF_EXT_512 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_CC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_CC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-118] AXISTEN_IF_EXT_512_CC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_CC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_CQ_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_CQ_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-119] AXISTEN_IF_EXT_512_CQ_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_CQ_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_RC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_RC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-120] AXISTEN_IF_EXT_512_RC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_RC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_EXT_512_RQ_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_EXT_512_RQ_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-121] AXISTEN_IF_EXT_512_RQ_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_EXT_512_RQ_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_LEGACY_MODE_ENABLE_REG != "FALSE") && + (AXISTEN_IF_LEGACY_MODE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-122] AXISTEN_IF_LEGACY_MODE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_LEGACY_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG != "FALSE") && + (AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-123] AXISTEN_IF_MSIX_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_RX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_MSIX_RX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-124] AXISTEN_IF_MSIX_RX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_RX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG != "FALSE") && + (AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] AXISTEN_IF_MSIX_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_RC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_RC_STRADDLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-127] AXISTEN_IF_RC_STRADDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_RC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_RX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_RX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-129] AXISTEN_IF_RX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_RX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG != "FALSE") && + (AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AXISTEN_IF_TX_PARITY_EN_REG != "TRUE") && + (AXISTEN_IF_TX_PARITY_EN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-131] AXISTEN_IF_TX_PARITY_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, AXISTEN_IF_TX_PARITY_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CCIX_DIRECT_ATTACH_MODE_REG != "FALSE") && + (CCIX_DIRECT_ATTACH_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-133] CCIX_DIRECT_ATTACH_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CCIX_DIRECT_ATTACH_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CCIX_ENABLE_REG != "FALSE") && + (CCIX_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-134] CCIX_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CCIX_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CFG_BYPASS_MODE_ENABLE_REG != "FALSE") && + (CFG_BYPASS_MODE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-136] CFG_BYPASS_MODE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CFG_BYPASS_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CRM_CORE_CLK_FREQ_500_REG != "TRUE") && + (CRM_CORE_CLK_FREQ_500_REG != "FALSE"))) begin + $display("Error: [Unisim %s-137] CRM_CORE_CLK_FREQ_500 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CRM_CORE_CLK_FREQ_500_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-144] DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-145] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG != "FALSE") && + (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-146] DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG != "FALSE") && + (DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-147] DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG != "FALSE") && + (DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG != "TRUE"))) begin + $display("Error: [Unisim %s-148] DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_DISABLE_SCRAMBLING_REG != "FALSE") && + (DEBUG_PL_DISABLE_SCRAMBLING_REG != "TRUE"))) begin + $display("Error: [Unisim %s-149] DEBUG_PL_DISABLE_SCRAMBLING attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_DISABLE_SCRAMBLING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_PL_SIM_RESET_LFSR_REG != "FALSE") && + (DEBUG_PL_SIM_RESET_LFSR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-150] DEBUG_PL_SIM_RESET_LFSR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_PL_SIM_RESET_LFSR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_TL_DISABLE_FC_TIMEOUT_REG != "FALSE") && + (DEBUG_TL_DISABLE_FC_TIMEOUT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-152] DEBUG_TL_DISABLE_FC_TIMEOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_TL_DISABLE_FC_TIMEOUT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "FALSE") && + (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-153] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DSN_CAP_ENABLE_REG != "FALSE") && + (DSN_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-156] DSN_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DSN_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-157] EXTENDED_CFG_EXTEND_INTERFACE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((HEADER_TYPE_OVERRIDE_REG != "FALSE") && + (HEADER_TYPE_OVERRIDE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-158] HEADER_TYPE_OVERRIDE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, HEADER_TYPE_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_SWITCH_PORT_REG != "FALSE") && + (IS_SWITCH_PORT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-159] IS_SWITCH_PORT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IS_SWITCH_PORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-160] LEGACY_CFG_EXTEND_INTERFACE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_ACK_TIMEOUT_EN_REG != "FALSE") && + (LL_ACK_TIMEOUT_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-162] LL_ACK_TIMEOUT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_ACK_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_ACK_TIMEOUT_FUNC_REG != 0) && + (LL_ACK_TIMEOUT_FUNC_REG != 1) && + (LL_ACK_TIMEOUT_FUNC_REG != 2) && + (LL_ACK_TIMEOUT_FUNC_REG != 3))) begin + $display("Error: [Unisim %s-163] LL_ACK_TIMEOUT_FUNC attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, LL_ACK_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_DISABLE_SCHED_TX_NAK_REG != "FALSE") && + (LL_DISABLE_SCHED_TX_NAK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-164] LL_DISABLE_SCHED_TX_NAK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_DISABLE_SCHED_TX_NAK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_FROM_RAM_PIPELINE_REG != "FALSE") && + (LL_REPLAY_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-165] LL_REPLAY_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TIMEOUT_EN_REG != "FALSE") && + (LL_REPLAY_TIMEOUT_EN_REG != "TRUE"))) begin + $display("Error: [Unisim %s-167] LL_REPLAY_TIMEOUT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TIMEOUT_FUNC_REG != 0) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 1) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 2) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 3))) begin + $display("Error: [Unisim %s-168] LL_REPLAY_TIMEOUT_FUNC attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, LL_REPLAY_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_REPLAY_TO_RAM_PIPELINE_REG != "FALSE") && + (LL_REPLAY_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-169] LL_REPLAY_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LL_REPLAY_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_RX_TLP_PARITY_GEN_REG != "TRUE") && + (LL_RX_TLP_PARITY_GEN_REG != "FALSE"))) begin + $display("Error: [Unisim %s-170] LL_RX_TLP_PARITY_GEN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LL_RX_TLP_PARITY_GEN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LL_TX_TLP_PARITY_CHK_REG != "TRUE") && + (LL_TX_TLP_PARITY_CHK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-171] LL_TX_TLP_PARITY_CHK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, LL_TX_TLP_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-174] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-175] LTR_TX_MESSAGE_ON_LTR_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LTR_TX_MESSAGE_ON_LTR_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_CONFIGURE_OVERRIDE_REG != "FALSE") && + (MCAP_CONFIGURE_OVERRIDE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-177] MCAP_CONFIGURE_OVERRIDE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_CONFIGURE_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_ENABLE_REG != "FALSE") && + (MCAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-178] MCAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_EOS_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_EOS_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-179] MCAP_EOS_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_EOS_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-181] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-182] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "TRUE"))) begin + $display("Error: [Unisim %s-183] MCAP_INPUT_GATE_DESIGN_SWITCH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INPUT_GATE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INTERRUPT_ON_MCAP_EOS_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_EOS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-184] MCAP_INTERRUPT_ON_MCAP_EOS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_EOS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-185] MCAP_INTERRUPT_ON_MCAP_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG != "FALSE") && + (PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-189] PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_ATS_CAP_ON_REG != "FALSE") && + (PF0_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-196] PF0_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-211] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-212] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-213] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "FALSE") && + (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-214] PF0_DEV_CAP2_ARI_FORWARD_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "TRUE") && + (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-215] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_LTR_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_LTR_SUPPORT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-216] PF0_DEV_CAP2_LTR_SUPPORT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_LTR_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "FALSE") && + (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-218] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 7))) begin + $display("Error: [Unisim %s-219] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 7))) begin + $display("Error: [Unisim %s-220] PF0_DEV_CAP_ENDPOINT_L1_LATENCY attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "TRUE") && + (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "FALSE"))) begin + $display("Error: [Unisim %s-221] PF0_DEV_CAP_EXT_TAG_SUPPORTED attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "TRUE") && + (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-222] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF0_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-226] PF0_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_ASPM_SUPPORT_REG != 0) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 1) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 2) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 3))) begin + $display("Error: [Unisim %s-228] PF0_LINK_CAP_ASPM_SUPPORT attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PF0_LINK_CAP_ASPM_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-229] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-230] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-231] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-232] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-233] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-234] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-235] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-236] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-237] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-238] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-239] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-240] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 6))) begin + $display("Error: [Unisim %s-241] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 6))) begin + $display("Error: [Unisim %s-242] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 6))) begin + $display("Error: [Unisim %s-243] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG != 6))) begin + $display("Error: [Unisim %s-244] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 attribute is set to %d. Legal values for this attribute are 7, 0, 1, 2, 3, 4, 5 or 6. Instance: %m", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "TRUE") && + (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "FALSE"))) begin + $display("Error: [Unisim %s-246] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSIX_CAP_PBA_BIR_REG != 0) && + (PF0_MSIX_CAP_PBA_BIR_REG != 1) && + (PF0_MSIX_CAP_PBA_BIR_REG != 2) && + (PF0_MSIX_CAP_PBA_BIR_REG != 3) && + (PF0_MSIX_CAP_PBA_BIR_REG != 4) && + (PF0_MSIX_CAP_PBA_BIR_REG != 5) && + (PF0_MSIX_CAP_PBA_BIR_REG != 6) && + (PF0_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-252] PF0_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-254] PF0_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-258] PF0_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF0_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF0_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-260] PF0_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D0_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D0_REG != "FALSE"))) begin + $display("Error: [Unisim %s-264] PF0_PM_CAP_PMESUPPORT_D0 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D1_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D1_REG != "FALSE"))) begin + $display("Error: [Unisim %s-265] PF0_PM_CAP_PMESUPPORT_D1 attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-266] PF0_PM_CAP_PMESUPPORT_D3HOT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D3HOT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CAP_SUPP_D1_STATE_REG != "TRUE") && + (PF0_PM_CAP_SUPP_D1_STATE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-267] PF0_PM_CAP_SUPP_D1_STATE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CAP_SUPP_D1_STATE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PM_CSR_NOSOFTRESET_REG != "TRUE") && + (PF0_PM_CSR_NOSOFTRESET_REG != "FALSE"))) begin + $display("Error: [Unisim %s-269] PF0_PM_CSR_NOSOFTRESET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_PM_CSR_NOSOFTRESET_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_PRI_CAP_ON_REG != "FALSE") && + (PF0_PRI_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-271] PF0_PRI_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_PRI_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-274] PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-295] PF0_TPHR_CAP_DEV_SPECIFIC_MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF0_TPHR_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-296] PF0_TPHR_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-297] PF0_TPHR_CAP_INT_VEC_MODE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PF0_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_VC_CAP_ENABLE_REG != "FALSE") && + (PF0_VC_CAP_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-305] PF0_VC_CAP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_VC_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_VC_EXTENDED_COUNT_REG != "FALSE") && + (PF0_VC_EXTENDED_COUNT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-308] PF0_VC_EXTENDED_COUNT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_VC_EXTENDED_COUNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF0_VC_LOW_PRIORITY_EXTENDED_COUNT_REG != "FALSE") && + (PF0_VC_LOW_PRIORITY_EXTENDED_COUNT_REG != "TRUE"))) begin + $display("Error: [Unisim %s-309] PF0_VC_LOW_PRIORITY_EXTENDED_COUNT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF0_VC_LOW_PRIORITY_EXTENDED_COUNT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_ATS_CAP_ON_REG != "FALSE") && + (PF1_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-315] PF1_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF1_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-333] PF1_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSIX_CAP_PBA_BIR_REG != 0) && + (PF1_MSIX_CAP_PBA_BIR_REG != 1) && + (PF1_MSIX_CAP_PBA_BIR_REG != 2) && + (PF1_MSIX_CAP_PBA_BIR_REG != 3) && + (PF1_MSIX_CAP_PBA_BIR_REG != 4) && + (PF1_MSIX_CAP_PBA_BIR_REG != 5) && + (PF1_MSIX_CAP_PBA_BIR_REG != 6) && + (PF1_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-336] PF1_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-338] PF1_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-341] PF1_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF1_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF1_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-343] PF1_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_PRI_CAP_ON_REG != "FALSE") && + (PF1_PRI_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-347] PF1_PRI_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_PRI_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-349] PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_ATS_CAP_ON_REG != "FALSE") && + (PF2_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-377] PF2_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF2_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-395] PF2_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSIX_CAP_PBA_BIR_REG != 0) && + (PF2_MSIX_CAP_PBA_BIR_REG != 1) && + (PF2_MSIX_CAP_PBA_BIR_REG != 2) && + (PF2_MSIX_CAP_PBA_BIR_REG != 3) && + (PF2_MSIX_CAP_PBA_BIR_REG != 4) && + (PF2_MSIX_CAP_PBA_BIR_REG != 5) && + (PF2_MSIX_CAP_PBA_BIR_REG != 6) && + (PF2_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-398] PF2_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-400] PF2_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-403] PF2_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF2_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF2_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-405] PF2_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_PRI_CAP_ON_REG != "FALSE") && + (PF2_PRI_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-409] PF2_PRI_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_PRI_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-411] PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_ATS_CAP_ON_REG != "FALSE") && + (PF3_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-439] PF3_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF3_EXPANSION_ROM_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-457] PF3_EXPANSION_ROM_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSIX_CAP_PBA_BIR_REG != 0) && + (PF3_MSIX_CAP_PBA_BIR_REG != 1) && + (PF3_MSIX_CAP_PBA_BIR_REG != 2) && + (PF3_MSIX_CAP_PBA_BIR_REG != 3) && + (PF3_MSIX_CAP_PBA_BIR_REG != 4) && + (PF3_MSIX_CAP_PBA_BIR_REG != 5) && + (PF3_MSIX_CAP_PBA_BIR_REG != 6) && + (PF3_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-460] PF3_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-462] PF3_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 7))) begin + $display("Error: [Unisim %s-465] PF3_MSI_CAP_MULTIMSGCAP attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, PF3_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF3_MSI_CAP_PERVECMASKCAP_REG != "TRUE"))) begin + $display("Error: [Unisim %s-467] PF3_MSI_CAP_PERVECMASKCAP attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_PRI_CAP_ON_REG != "FALSE") && + (PF3_PRI_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-471] PF3_PRI_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_PRI_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "FALSE") && + (PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG != "TRUE"))) begin + $display("Error: [Unisim %s-473] PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_CFG_STATE_ROBUSTNESS_ENABLE_REG != "TRUE") && + (PL_CFG_STATE_ROBUSTNESS_ENABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-496] PL_CFG_STATE_ROBUSTNESS_ENABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_CFG_STATE_ROBUSTNESS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_CTRL_SKP_GEN_ENABLE_REG != "FALSE") && + (PL_CTRL_SKP_GEN_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-497] PL_CTRL_SKP_GEN_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_CTRL_SKP_GEN_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE_REG != "TRUE") && + (PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-498] PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DEEMPH_SOURCE_SELECT_REG != "TRUE") && + (PL_DEEMPH_SOURCE_SELECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-499] PL_DEEMPH_SOURCE_SELECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_DEEMPH_SOURCE_SELECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DESKEW_ON_SKIP_IN_GEN12_REG != "FALSE") && + (PL_DESKEW_ON_SKIP_IN_GEN12_REG != "TRUE"))) begin + $display("Error: [Unisim %s-500] PL_DESKEW_ON_SKIP_IN_GEN12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DESKEW_ON_SKIP_IN_GEN12_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "FALSE") && + (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "TRUE"))) begin + $display("Error: [Unisim %s-501] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG != "FALSE") && + (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG != "TRUE"))) begin + $display("Error: [Unisim %s-502] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "FALSE") && + (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "TRUE"))) begin + $display("Error: [Unisim %s-503] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_DC_BALANCE_REG != "FALSE") && + (PL_DISABLE_DC_BALANCE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-504] PL_DISABLE_DC_BALANCE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_DC_BALANCE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") && + (PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-505] PL_DISABLE_EI_INFER_IN_L0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_EI_INFER_IN_L0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_LANE_REVERSAL_REG != "FALSE") && + (PL_DISABLE_LANE_REVERSAL_REG != "TRUE"))) begin + $display("Error: [Unisim %s-506] PL_DISABLE_LANE_REVERSAL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_LANE_REVERSAL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_RETRAIN_ON_EB_ERROR_REG != "FALSE") && + (PL_DISABLE_RETRAIN_ON_EB_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-508] PL_DISABLE_RETRAIN_ON_EB_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_RETRAIN_ON_EB_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "FALSE") && + (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "TRUE"))) begin + $display("Error: [Unisim %s-509] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_DISABLE_UPCONFIG_CAPABLE_REG != "FALSE") && + (PL_DISABLE_UPCONFIG_CAPABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-511] PL_DISABLE_UPCONFIG_CAPABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_DISABLE_UPCONFIG_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_DISABLE_MISMATCH_CHECK_REG != "TRUE") && + (PL_EQ_DISABLE_MISMATCH_CHECK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-519] PL_EQ_DISABLE_MISMATCH_CHECK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_EQ_DISABLE_MISMATCH_CHECK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_SHORT_ADAPT_PHASE_REG != "FALSE") && + (PL_EQ_SHORT_ADAPT_PHASE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-522] PL_EQ_SHORT_ADAPT_PHASE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_EQ_SHORT_ADAPT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EQ_TX_8G_EQ_TS2_ENABLE_REG != "FALSE") && + (PL_EQ_TX_8G_EQ_TS2_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-523] PL_EQ_TX_8G_EQ_TS2_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_EQ_TX_8G_EQ_TS2_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG != "TRUE") && + (PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-524] PL_EXIT_LOOPBACK_ON_EI_ENTRY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG != "TRUE") && + (PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-525] PL_INFER_EI_DISABLE_LPBK_ACTIVE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_REC_RC_REG != "FALSE") && + (PL_INFER_EI_DISABLE_REC_RC_REG != "TRUE"))) begin + $display("Error: [Unisim %s-526] PL_INFER_EI_DISABLE_REC_RC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_REC_RC_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_INFER_EI_DISABLE_REC_SPD_REG != "FALSE") && + (PL_INFER_EI_DISABLE_REC_SPD_REG != "TRUE"))) begin + $display("Error: [Unisim %s-527] PL_INFER_EI_DISABLE_REC_SPD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_INFER_EI_DISABLE_REC_SPD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_N_FTS_REG < 0) || (PL_N_FTS_REG > 255))) begin + $display("Error: [Unisim %s-546] PL_N_FTS attribute is set to %d. Legal values for this attribute are 0 to 255. Instance: %m", MODULE_NAME, PL_N_FTS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_QUIESCE_GUARANTEE_DISABLE_REG != "FALSE") && + (PL_QUIESCE_GUARANTEE_DISABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-547] PL_QUIESCE_GUARANTEE_DISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_QUIESCE_GUARANTEE_DISABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_REDO_EQ_SOURCE_SELECT_REG != "TRUE") && + (PL_REDO_EQ_SOURCE_SELECT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-548] PL_REDO_EQ_SOURCE_SELECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_REDO_EQ_SOURCE_SELECT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_SRIS_ENABLE_REG != "FALSE") && + (PL_SRIS_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-558] PL_SRIS_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PL_SRIS_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PL_UPSTREAM_FACING_REG != "TRUE") && + (PL_UPSTREAM_FACING_REG != "FALSE"))) begin + $display("Error: [Unisim %s-561] PL_UPSTREAM_FACING attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PL_UPSTREAM_FACING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PM_ENABLE_L23_ENTRY_REG != "FALSE") && + (PM_ENABLE_L23_ENTRY_REG != "TRUE"))) begin + $display("Error: [Unisim %s-566] PM_ENABLE_L23_ENTRY attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PM_ENABLE_L23_ENTRY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((PM_ENABLE_SLOT_POWER_CAPTURE_REG != "TRUE") && + (PM_ENABLE_SLOT_POWER_CAPTURE_REG != "FALSE"))) begin + $display("Error: [Unisim %s-567] PM_ENABLE_SLOT_POWER_CAPTURE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, PM_ENABLE_SLOT_POWER_CAPTURE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-571] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != "1.0") && + (SIM_VERSION_REG != "1.1") && + (SIM_VERSION_REG != "1.2") && + (SIM_VERSION_REG != "1.3") && + (SIM_VERSION_REG != "2.0") && + (SIM_VERSION_REG != "3.0") && + (SIM_VERSION_REG != "4.0"))) begin + $display("Error: [Unisim %s-573] SIM_VERSION attribute is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0 or 4.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT0_REG != "FALSE") && + (SPARE_BIT0_REG != "TRUE"))) begin + $display("Error: [Unisim %s-574] SPARE_BIT0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SPARE_BIT0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT1_REG != 0) && + (SPARE_BIT1_REG != 1))) begin + $display("Error: [Unisim %s-575] SPARE_BIT1 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT2_REG != 0) && + (SPARE_BIT2_REG != 1))) begin + $display("Error: [Unisim %s-576] SPARE_BIT2 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT3_REG != "FALSE") && + (SPARE_BIT3_REG != "TRUE"))) begin + $display("Error: [Unisim %s-577] SPARE_BIT3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SPARE_BIT3_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT4_REG != 0) && + (SPARE_BIT4_REG != 1))) begin + $display("Error: [Unisim %s-578] SPARE_BIT4 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT4_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT5_REG != 0) && + (SPARE_BIT5_REG != 1))) begin + $display("Error: [Unisim %s-579] SPARE_BIT5 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT5_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT6_REG != 0) && + (SPARE_BIT6_REG != 1))) begin + $display("Error: [Unisim %s-580] SPARE_BIT6 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT6_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT7_REG != 0) && + (SPARE_BIT7_REG != 1))) begin + $display("Error: [Unisim %s-581] SPARE_BIT7 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT7_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SPARE_BIT8_REG != 0) && + (SPARE_BIT8_REG != 1))) begin + $display("Error: [Unisim %s-582] SPARE_BIT8 attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, SPARE_BIT8_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL2CFG_IF_PARITY_CHK_REG != "TRUE") && + (TL2CFG_IF_PARITY_CHK_REG != "FALSE"))) begin + $display("Error: [Unisim %s-593] TL2CFG_IF_PARITY_CHK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TL2CFG_IF_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_FEATURE_ENABLE_FC_SCALING_REG != "FALSE") && + (TL_FEATURE_ENABLE_FC_SCALING_REG != "TRUE"))) begin + $display("Error: [Unisim %s-612] TL_FEATURE_ENABLE_FC_SCALING attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_FEATURE_ENABLE_FC_SCALING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-615] TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-616] TL_RX_COMPLETION_TO_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG != "FALSE") && + (TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-617] TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-618] TL_RX_POSTED_FROM_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-619] TL_RX_POSTED_TO_RAM_READ_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG != "FALSE") && + (TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-620] TL_RX_POSTED_TO_RAM_WRITE_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_MUX_STRICT_PRIORITY_REG != "TRUE") && + (TL_TX_MUX_STRICT_PRIORITY_REG != "FALSE"))) begin + $display("Error: [Unisim %s-621] TL_TX_MUX_STRICT_PRIORITY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TL_TX_MUX_STRICT_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_TLP_STRADDLE_ENABLE_REG != "FALSE") && + (TL_TX_TLP_STRADDLE_ENABLE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-622] TL_TX_TLP_STRADDLE_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_TX_TLP_STRADDLE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TL_TX_TLP_TERMINATE_PARITY_REG != "FALSE") && + (TL_TX_TLP_TERMINATE_PARITY_REG != "TRUE"))) begin + $display("Error: [Unisim %s-623] TL_TX_TLP_TERMINATE_PARITY attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TL_TX_TLP_TERMINATE_PARITY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TPH_FROM_RAM_PIPELINE_REG != "FALSE") && + (TPH_FROM_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-625] TPH_FROM_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TPH_FROM_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TPH_TO_RAM_PIPELINE_REG != "FALSE") && + (TPH_TO_RAM_PIPELINE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-626] TPH_TO_RAM_PIPELINE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TPH_TO_RAM_PIPELINE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG0_ATS_CAP_ON_REG != "FALSE") && + (VFG0_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-631] VFG0_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, VFG0_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG0_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG0_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-633] VFG0_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG0_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG0_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-635] VFG0_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG1_ATS_CAP_ON_REG != "FALSE") && + (VFG1_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-644] VFG1_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, VFG1_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG1_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG1_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-646] VFG1_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG1_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG1_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-648] VFG1_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG2_ATS_CAP_ON_REG != "FALSE") && + (VFG2_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-657] VFG2_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, VFG2_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG2_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG2_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-659] VFG2_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG2_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG2_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-661] VFG2_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG3_ATS_CAP_ON_REG != "FALSE") && + (VFG3_ATS_CAP_ON_REG != "TRUE"))) begin + $display("Error: [Unisim %s-670] VFG3_ATS_CAP_ON attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, VFG3_ATS_CAP_ON_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG3_MSIX_CAP_PBA_BIR_REG != 0) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 1) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 2) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 3) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 4) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 5) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 6) && + (VFG3_MSIX_CAP_PBA_BIR_REG != 7))) begin + $display("Error: [Unisim %s-672] VFG3_MSIX_CAP_PBA_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((VFG3_MSIX_CAP_TABLE_BIR_REG != 0) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 1) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 2) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 3) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 4) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 5) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 6) && + (VFG3_MSIX_CAP_TABLE_BIR_REG != 7))) begin + $display("Error: [Unisim %s-674] VFG3_MSIX_CAP_TABLE_BIR attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, VFG3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + + +assign PMVDIVIDE_in = 2'b11; // tie off +assign PMVENABLEN_in = 1'b1; // tie off +assign PMVSELECT_in = 3'b111; // tie off +assign SCANENABLEN_in = 1'b1; // tie off +assign SCANIN_in = 130'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off +assign SCANMODEN_in = 1'b1; // tie off + + SIP_PCIE4CE4 #( + .MCAP_ENABLE_PAR (MCAP_ENABLE), + .SIM_JTAG_IDCODE (SIM_JTAG_IDCODE) + ) SIP_PCIE4CE4_INST ( + .ARI_CAP_ENABLE (ARI_CAP_ENABLE_REG), + .AUTO_FLR_RESPONSE (AUTO_FLR_RESPONSE_REG), + .AXISTEN_IF_CCIX_RX_CREDIT_LIMIT (AXISTEN_IF_CCIX_RX_CREDIT_LIMIT_REG), + .AXISTEN_IF_CCIX_TX_CREDIT_LIMIT (AXISTEN_IF_CCIX_TX_CREDIT_LIMIT_REG), + .AXISTEN_IF_CCIX_TX_REGISTERED_TREADY (AXISTEN_IF_CCIX_TX_REGISTERED_TREADY_REG), + .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_COMPL_TIMEOUT_REG0 (AXISTEN_IF_COMPL_TIMEOUT_REG0_REG), + .AXISTEN_IF_COMPL_TIMEOUT_REG1 (AXISTEN_IF_COMPL_TIMEOUT_REG1_REG), + .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_CQ_EN_POISONED_MEM_WR (AXISTEN_IF_CQ_EN_POISONED_MEM_WR_REG), + .AXISTEN_IF_ENABLE_256_TAGS (AXISTEN_IF_ENABLE_256_TAGS_REG), + .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG_REG), + .AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE (AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE_REG), + .AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK (AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK_REG), + .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE_REG), + .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG), + .AXISTEN_IF_EXT_512 (AXISTEN_IF_EXT_512_REG), + .AXISTEN_IF_EXT_512_CC_STRADDLE (AXISTEN_IF_EXT_512_CC_STRADDLE_REG), + .AXISTEN_IF_EXT_512_CQ_STRADDLE (AXISTEN_IF_EXT_512_CQ_STRADDLE_REG), + .AXISTEN_IF_EXT_512_RC_STRADDLE (AXISTEN_IF_EXT_512_RC_STRADDLE_REG), + .AXISTEN_IF_EXT_512_RQ_STRADDLE (AXISTEN_IF_EXT_512_RQ_STRADDLE_REG), + .AXISTEN_IF_LEGACY_MODE_ENABLE (AXISTEN_IF_LEGACY_MODE_ENABLE_REG), + .AXISTEN_IF_MSIX_FROM_RAM_PIPELINE (AXISTEN_IF_MSIX_FROM_RAM_PIPELINE_REG), + .AXISTEN_IF_MSIX_RX_PARITY_EN (AXISTEN_IF_MSIX_RX_PARITY_EN_REG), + .AXISTEN_IF_MSIX_TO_RAM_PIPELINE (AXISTEN_IF_MSIX_TO_RAM_PIPELINE_REG), + .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE_REG), + .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RX_PARITY_EN (AXISTEN_IF_RX_PARITY_EN_REG), + .AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT (AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT_REG), + .AXISTEN_IF_TX_PARITY_EN (AXISTEN_IF_TX_PARITY_EN_REG), + .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH_REG), + .CCIX_DIRECT_ATTACH_MODE (CCIX_DIRECT_ATTACH_MODE_REG), + .CCIX_ENABLE (CCIX_ENABLE_REG), + .CCIX_VENDOR_ID (CCIX_VENDOR_ID_REG), + .CFG_BYPASS_MODE_ENABLE (CFG_BYPASS_MODE_ENABLE_REG), + .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500_REG), + .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ_REG), + .DEBUG_AXI4ST_SPARE (DEBUG_AXI4ST_SPARE_REG), + .DEBUG_AXIST_DISABLE_FEATURE_BIT (DEBUG_AXIST_DISABLE_FEATURE_BIT_REG), + .DEBUG_CAR_SPARE (DEBUG_CAR_SPARE_REG), + .DEBUG_CFG_SPARE (DEBUG_CFG_SPARE_REG), + .DEBUG_LL_SPARE (DEBUG_LL_SPARE_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR_REG), + .DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR (DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR_REG), + .DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL (DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL_REG), + .DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW (DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW_REG), + .DEBUG_PL_DISABLE_SCRAMBLING (DEBUG_PL_DISABLE_SCRAMBLING_REG), + .DEBUG_PL_SIM_RESET_LFSR (DEBUG_PL_SIM_RESET_LFSR_REG), + .DEBUG_PL_SPARE (DEBUG_PL_SPARE_REG), + .DEBUG_TL_DISABLE_FC_TIMEOUT (DEBUG_TL_DISABLE_FC_TIMEOUT_REG), + .DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG), + .DEBUG_TL_SPARE (DEBUG_TL_SPARE_REG), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM_REG), + .DSN_CAP_ENABLE (DSN_CAP_ENABLE_REG), + .EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG), + .HEADER_TYPE_OVERRIDE (HEADER_TYPE_OVERRIDE_REG), + .IS_SWITCH_PORT (IS_SWITCH_PORT_REG), + .LEGACY_CFG_EXTEND_INTERFACE_ENABLE (LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT_REG), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN_REG), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC_REG), + .LL_DISABLE_SCHED_TX_NAK (LL_DISABLE_SCHED_TX_NAK_REG), + .LL_REPLAY_FROM_RAM_PIPELINE (LL_REPLAY_FROM_RAM_PIPELINE_REG), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT_REG), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN_REG), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC_REG), + .LL_REPLAY_TO_RAM_PIPELINE (LL_REPLAY_TO_RAM_PIPELINE_REG), + .LL_RX_TLP_PARITY_GEN (LL_RX_TLP_PARITY_GEN_REG), + .LL_TX_TLP_PARITY_CHK (LL_TX_TLP_PARITY_CHK_REG), + .LL_USER_SPARE (LL_USER_SPARE_REG), + .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG), + .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG), + .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG), + .MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR_REG), + .MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE_REG), + .MCAP_ENABLE (MCAP_ENABLE_REG), + .MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH_REG), + .MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION_REG), + .MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG), + .MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG), + .MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH_REG), + .MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS_REG), + .MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR_REG), + .MCAP_VSEC_ID (MCAP_VSEC_ID_REG), + .MCAP_VSEC_LEN (MCAP_VSEC_LEN_REG), + .MCAP_VSEC_REV (MCAP_VSEC_REV_REG), + .PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE (PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE_REG), + .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC_REG), + .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER_REG), + .PF0_ATS_CAP_INV_QUEUE_DEPTH (PF0_ATS_CAP_INV_QUEUE_DEPTH_REG), + .PF0_ATS_CAP_NEXTPTR (PF0_ATS_CAP_NEXTPTR_REG), + .PF0_ATS_CAP_ON (PF0_ATS_CAP_ON_REG), + .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE_REG), + .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL_REG), + .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE_REG), + .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL_REG), + .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE_REG), + .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL_REG), + .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE_REG), + .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL_REG), + .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE_REG), + .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL_REG), + .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE_REG), + .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL_REG), + .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER_REG), + .PF0_CLASS_CODE (PF0_CLASS_CODE_REG), + .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG), + .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG), + .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT_REG), + .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT_REG), + .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG), + .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG), + .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG), + .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG), + .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR_REG), + .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE_REG), + .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN_REG), + .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4_REG), + .PF0_LINK_CONTROL_RCB (PF0_LINK_CONTROL_RCB_REG), + .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG), + .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG), + .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT_REG), + .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR_REG), + .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER_REG), + .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR_REG), + .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR_REG), + .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR_REG), + .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE_REG), + .PF0_MSIX_VECTOR_COUNT (PF0_MSIX_VECTOR_COUNT_REG), + .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP_REG), + .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR_REG), + .PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP_REG), + .PF0_PCIE_CAP_NEXTPTR (PF0_PCIE_CAP_NEXTPTR_REG), + .PF0_PM_CAP_ID (PF0_PM_CAP_ID_REG), + .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR_REG), + .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0_REG), + .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1_REG), + .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT_REG), + .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE_REG), + .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID_REG), + .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET_REG), + .PF0_PRI_CAP_NEXTPTR (PF0_PRI_CAP_NEXTPTR_REG), + .PF0_PRI_CAP_ON (PF0_PRI_CAP_ON_REG), + .PF0_PRI_OST_PR_CAPACITY (PF0_PRI_OST_PR_CAPACITY_REG), + .PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG), + .PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL_REG), + .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL_REG), + .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL_REG), + .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL_REG), + .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL_REG), + .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL_REG), + .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF_REG), + .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR_REG), + .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF_REG), + .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER_REG), + .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET_REG), + .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK_REG), + .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID_REG), + .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE_REG), + .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE_REG), + .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR_REG), + .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL_REG), + .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC_REG), + .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER_REG), + .PF0_VC_ARB_CAPABILITY (PF0_VC_ARB_CAPABILITY_REG), + .PF0_VC_ARB_TBL_OFFSET (PF0_VC_ARB_TBL_OFFSET_REG), + .PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE_REG), + .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR_REG), + .PF0_VC_CAP_VER (PF0_VC_CAP_VER_REG), + .PF0_VC_EXTENDED_COUNT (PF0_VC_EXTENDED_COUNT_REG), + .PF0_VC_LOW_PRIORITY_EXTENDED_COUNT (PF0_VC_LOW_PRIORITY_EXTENDED_COUNT_REG), + .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC_REG), + .PF1_ATS_CAP_INV_QUEUE_DEPTH (PF1_ATS_CAP_INV_QUEUE_DEPTH_REG), + .PF1_ATS_CAP_NEXTPTR (PF1_ATS_CAP_NEXTPTR_REG), + .PF1_ATS_CAP_ON (PF1_ATS_CAP_ON_REG), + .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE_REG), + .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL_REG), + .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE_REG), + .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL_REG), + .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE_REG), + .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL_REG), + .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE_REG), + .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL_REG), + .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE_REG), + .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL_REG), + .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE_REG), + .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL_REG), + .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER_REG), + .PF1_CLASS_CODE (PF1_CLASS_CODE_REG), + .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR_REG), + .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE_REG), + .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN_REG), + .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR_REG), + .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR_REG), + .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR_REG), + .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE_REG), + .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP_REG), + .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR_REG), + .PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP_REG), + .PF1_PCIE_CAP_NEXTPTR (PF1_PCIE_CAP_NEXTPTR_REG), + .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR_REG), + .PF1_PRI_CAP_NEXTPTR (PF1_PRI_CAP_NEXTPTR_REG), + .PF1_PRI_CAP_ON (PF1_PRI_CAP_ON_REG), + .PF1_PRI_OST_PR_CAPACITY (PF1_PRI_OST_PR_CAPACITY_REG), + .PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL_REG), + .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL_REG), + .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL_REG), + .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL_REG), + .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL_REG), + .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL_REG), + .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF_REG), + .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR_REG), + .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF_REG), + .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER_REG), + .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET_REG), + .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK_REG), + .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID_REG), + .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR_REG), + .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL_REG), + .PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC_REG), + .PF2_ATS_CAP_INV_QUEUE_DEPTH (PF2_ATS_CAP_INV_QUEUE_DEPTH_REG), + .PF2_ATS_CAP_NEXTPTR (PF2_ATS_CAP_NEXTPTR_REG), + .PF2_ATS_CAP_ON (PF2_ATS_CAP_ON_REG), + .PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE_REG), + .PF2_BAR0_CONTROL (PF2_BAR0_CONTROL_REG), + .PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE_REG), + .PF2_BAR1_CONTROL (PF2_BAR1_CONTROL_REG), + .PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE_REG), + .PF2_BAR2_CONTROL (PF2_BAR2_CONTROL_REG), + .PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE_REG), + .PF2_BAR3_CONTROL (PF2_BAR3_CONTROL_REG), + .PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE_REG), + .PF2_BAR4_CONTROL (PF2_BAR4_CONTROL_REG), + .PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE_REG), + .PF2_BAR5_CONTROL (PF2_BAR5_CONTROL_REG), + .PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER_REG), + .PF2_CLASS_CODE (PF2_CLASS_CODE_REG), + .PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR_REG), + .PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE_REG), + .PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN_REG), + .PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR_REG), + .PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR_REG), + .PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR_REG), + .PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE_REG), + .PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP_REG), + .PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR_REG), + .PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP_REG), + .PF2_PCIE_CAP_NEXTPTR (PF2_PCIE_CAP_NEXTPTR_REG), + .PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR_REG), + .PF2_PRI_CAP_NEXTPTR (PF2_PRI_CAP_NEXTPTR_REG), + .PF2_PRI_CAP_ON (PF2_PRI_CAP_ON_REG), + .PF2_PRI_OST_PR_CAPACITY (PF2_PRI_OST_PR_CAPACITY_REG), + .PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL_REG), + .PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL_REG), + .PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL_REG), + .PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL_REG), + .PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL_REG), + .PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL_REG), + .PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF_REG), + .PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR_REG), + .PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF_REG), + .PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER_REG), + .PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET_REG), + .PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK_REG), + .PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID_REG), + .PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR_REG), + .PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL_REG), + .PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC_REG), + .PF3_ATS_CAP_INV_QUEUE_DEPTH (PF3_ATS_CAP_INV_QUEUE_DEPTH_REG), + .PF3_ATS_CAP_NEXTPTR (PF3_ATS_CAP_NEXTPTR_REG), + .PF3_ATS_CAP_ON (PF3_ATS_CAP_ON_REG), + .PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE_REG), + .PF3_BAR0_CONTROL (PF3_BAR0_CONTROL_REG), + .PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE_REG), + .PF3_BAR1_CONTROL (PF3_BAR1_CONTROL_REG), + .PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE_REG), + .PF3_BAR2_CONTROL (PF3_BAR2_CONTROL_REG), + .PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE_REG), + .PF3_BAR3_CONTROL (PF3_BAR3_CONTROL_REG), + .PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE_REG), + .PF3_BAR4_CONTROL (PF3_BAR4_CONTROL_REG), + .PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE_REG), + .PF3_BAR5_CONTROL (PF3_BAR5_CONTROL_REG), + .PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER_REG), + .PF3_CLASS_CODE (PF3_CLASS_CODE_REG), + .PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR_REG), + .PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE_REG), + .PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN_REG), + .PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR_REG), + .PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR_REG), + .PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR_REG), + .PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE_REG), + .PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP_REG), + .PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR_REG), + .PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP_REG), + .PF3_PCIE_CAP_NEXTPTR (PF3_PCIE_CAP_NEXTPTR_REG), + .PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR_REG), + .PF3_PRI_CAP_NEXTPTR (PF3_PRI_CAP_NEXTPTR_REG), + .PF3_PRI_CAP_ON (PF3_PRI_CAP_ON_REG), + .PF3_PRI_OST_PR_CAPACITY (PF3_PRI_OST_PR_CAPACITY_REG), + .PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED (PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED_REG), + .PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL_REG), + .PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL_REG), + .PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL_REG), + .PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL_REG), + .PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL_REG), + .PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL_REG), + .PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF_REG), + .PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR_REG), + .PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF_REG), + .PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER_REG), + .PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET_REG), + .PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK_REG), + .PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID_REG), + .PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR_REG), + .PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL_REG), + .PL_CFG_STATE_ROBUSTNESS_ENABLE (PL_CFG_STATE_ROBUSTNESS_ENABLE_REG), + .PL_CTRL_SKP_GEN_ENABLE (PL_CTRL_SKP_GEN_ENABLE_REG), + .PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE (PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE_REG), + .PL_DEEMPH_SOURCE_SELECT (PL_DEEMPH_SOURCE_SELECT_REG), + .PL_DESKEW_ON_SKIP_IN_GEN12 (PL_DESKEW_ON_SKIP_IN_GEN12_REG), + .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG), + .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4_REG), + .PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG), + .PL_DISABLE_DC_BALANCE (PL_DISABLE_DC_BALANCE_REG), + .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0_REG), + .PL_DISABLE_LANE_REVERSAL (PL_DISABLE_LANE_REVERSAL_REG), + .PL_DISABLE_LFSR_UPDATE_ON_SKP (PL_DISABLE_LFSR_UPDATE_ON_SKP_REG), + .PL_DISABLE_RETRAIN_ON_EB_ERROR (PL_DISABLE_RETRAIN_ON_EB_ERROR_REG), + .PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG), + .PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR_REG), + .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE_REG), + .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG), + .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG), + .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT_REG), + .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG), + .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23_REG), + .PL_EQ_DEFAULT_RX_PRESET_HINT (PL_EQ_DEFAULT_RX_PRESET_HINT_REG), + .PL_EQ_DEFAULT_TX_PRESET (PL_EQ_DEFAULT_TX_PRESET_REG), + .PL_EQ_DISABLE_MISMATCH_CHECK (PL_EQ_DISABLE_MISMATCH_CHECK_REG), + .PL_EQ_RX_ADAPT_EQ_PHASE0 (PL_EQ_RX_ADAPT_EQ_PHASE0_REG), + .PL_EQ_RX_ADAPT_EQ_PHASE1 (PL_EQ_RX_ADAPT_EQ_PHASE1_REG), + .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE_REG), + .PL_EQ_TX_8G_EQ_TS2_ENABLE (PL_EQ_TX_8G_EQ_TS2_ENABLE_REG), + .PL_EXIT_LOOPBACK_ON_EI_ENTRY (PL_EXIT_LOOPBACK_ON_EI_ENTRY_REG), + .PL_INFER_EI_DISABLE_LPBK_ACTIVE (PL_INFER_EI_DISABLE_LPBK_ACTIVE_REG), + .PL_INFER_EI_DISABLE_REC_RC (PL_INFER_EI_DISABLE_REC_RC_REG), + .PL_INFER_EI_DISABLE_REC_SPD (PL_INFER_EI_DISABLE_REC_SPD_REG), + .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL_REG), + .PL_LANE10_EQ_CONTROL (PL_LANE10_EQ_CONTROL_REG), + .PL_LANE11_EQ_CONTROL (PL_LANE11_EQ_CONTROL_REG), + .PL_LANE12_EQ_CONTROL (PL_LANE12_EQ_CONTROL_REG), + .PL_LANE13_EQ_CONTROL (PL_LANE13_EQ_CONTROL_REG), + .PL_LANE14_EQ_CONTROL (PL_LANE14_EQ_CONTROL_REG), + .PL_LANE15_EQ_CONTROL (PL_LANE15_EQ_CONTROL_REG), + .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL_REG), + .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL_REG), + .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL_REG), + .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL_REG), + .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL_REG), + .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL_REG), + .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL_REG), + .PL_LANE8_EQ_CONTROL (PL_LANE8_EQ_CONTROL_REG), + .PL_LANE9_EQ_CONTROL (PL_LANE9_EQ_CONTROL_REG), + .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED_REG), + .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH_REG), + .PL_N_FTS (PL_N_FTS_REG), + .PL_QUIESCE_GUARANTEE_DISABLE (PL_QUIESCE_GUARANTEE_DISABLE_REG), + .PL_REDO_EQ_SOURCE_SELECT (PL_REDO_EQ_SOURCE_SELECT_REG), + .PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS_REG), + .PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS (PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS_REG), + .PL_RX_ADAPT_TIMER_CLWS_GEN3 (PL_RX_ADAPT_TIMER_CLWS_GEN3_REG), + .PL_RX_ADAPT_TIMER_CLWS_GEN4 (PL_RX_ADAPT_TIMER_CLWS_GEN4_REG), + .PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS (PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS_REG), + .PL_RX_ADAPT_TIMER_RRL_GEN3 (PL_RX_ADAPT_TIMER_RRL_GEN3_REG), + .PL_RX_ADAPT_TIMER_RRL_GEN4 (PL_RX_ADAPT_TIMER_RRL_GEN4_REG), + .PL_RX_L0S_EXIT_TO_RECOVERY (PL_RX_L0S_EXIT_TO_RECOVERY_REG), + .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING_REG), + .PL_SRIS_ENABLE (PL_SRIS_ENABLE_REG), + .PL_SRIS_SKPOS_GEN_SPD_VEC (PL_SRIS_SKPOS_GEN_SPD_VEC_REG), + .PL_SRIS_SKPOS_REC_SPD_VEC (PL_SRIS_SKPOS_REC_SPD_VEC_REG), + .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING_REG), + .PL_USER_SPARE (PL_USER_SPARE_REG), + .PL_USER_SPARE2 (PL_USER_SPARE2_REG), + .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT_REG), + .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY_REG), + .PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY_REG), + .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE_REG), + .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY_REG), + .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY_REG), + .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY_REG), + //.SIM_DEVICE (SIM_DEVICE_REG), + //.SIM_JTAG_IDCODE (SIM_JTAG_IDCODE_REG), + //.SIM_VERSION (SIM_VERSION_REG), + .SPARE_BIT0 (SPARE_BIT0_REG), + .SPARE_BIT1 (SPARE_BIT1_REG), + .SPARE_BIT2 (SPARE_BIT2_REG), + .SPARE_BIT3 (SPARE_BIT3_REG), + .SPARE_BIT4 (SPARE_BIT4_REG), + .SPARE_BIT5 (SPARE_BIT5_REG), + .SPARE_BIT6 (SPARE_BIT6_REG), + .SPARE_BIT7 (SPARE_BIT7_REG), + .SPARE_BIT8 (SPARE_BIT8_REG), + .SPARE_BYTE0 (SPARE_BYTE0_REG), + .SPARE_BYTE1 (SPARE_BYTE1_REG), + .SPARE_BYTE2 (SPARE_BYTE2_REG), + .SPARE_BYTE3 (SPARE_BYTE3_REG), + .SPARE_WORD0 (SPARE_WORD0_REG), + .SPARE_WORD1 (SPARE_WORD1_REG), + .SPARE_WORD2 (SPARE_WORD2_REG), + .SPARE_WORD3 (SPARE_WORD3_REG), + .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .TL2CFG_IF_PARITY_CHK (TL2CFG_IF_PARITY_CHK_REG), + .TL_COMPLETION_RAM_NUM_TLPS (TL_COMPLETION_RAM_NUM_TLPS_REG), + .TL_COMPLETION_RAM_SIZE (TL_COMPLETION_RAM_SIZE_REG), + .TL_CREDITS_CD (TL_CREDITS_CD_REG), + .TL_CREDITS_CD_VC1 (TL_CREDITS_CD_VC1_REG), + .TL_CREDITS_CH (TL_CREDITS_CH_REG), + .TL_CREDITS_CH_VC1 (TL_CREDITS_CH_VC1_REG), + .TL_CREDITS_NPD (TL_CREDITS_NPD_REG), + .TL_CREDITS_NPD_VC1 (TL_CREDITS_NPD_VC1_REG), + .TL_CREDITS_NPH (TL_CREDITS_NPH_REG), + .TL_CREDITS_NPH_VC1 (TL_CREDITS_NPH_VC1_REG), + .TL_CREDITS_PD (TL_CREDITS_PD_REG), + .TL_CREDITS_PD_VC1 (TL_CREDITS_PD_VC1_REG), + .TL_CREDITS_PH (TL_CREDITS_PH_REG), + .TL_CREDITS_PH_VC1 (TL_CREDITS_PH_VC1_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TIME (TL_FC_UPDATE_MIN_INTERVAL_TIME_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 (TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT (TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_REG), + .TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 (TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1_REG), + .TL_FEATURE_ENABLE_FC_SCALING (TL_FEATURE_ENABLE_FC_SCALING_REG), + .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG_REG), + .TL_POSTED_RAM_SIZE (TL_POSTED_RAM_SIZE_REG), + .TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE (TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE_REG), + .TL_RX_COMPLETION_TO_RAM_READ_PIPELINE (TL_RX_COMPLETION_TO_RAM_READ_PIPELINE_REG), + .TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE (TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE_REG), + .TL_RX_POSTED_FROM_RAM_READ_PIPELINE (TL_RX_POSTED_FROM_RAM_READ_PIPELINE_REG), + .TL_RX_POSTED_TO_RAM_READ_PIPELINE (TL_RX_POSTED_TO_RAM_READ_PIPELINE_REG), + .TL_RX_POSTED_TO_RAM_WRITE_PIPELINE (TL_RX_POSTED_TO_RAM_WRITE_PIPELINE_REG), + .TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY_REG), + .TL_TX_TLP_STRADDLE_ENABLE (TL_TX_TLP_STRADDLE_ENABLE_REG), + .TL_TX_TLP_TERMINATE_PARITY (TL_TX_TLP_TERMINATE_PARITY_REG), + .TL_USER_SPARE (TL_USER_SPARE_REG), + .TPH_FROM_RAM_PIPELINE (TPH_FROM_RAM_PIPELINE_REG), + .TPH_TO_RAM_PIPELINE (TPH_TO_RAM_PIPELINE_REG), + .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER_REG), + .VFG0_ARI_CAP_NEXTPTR (VFG0_ARI_CAP_NEXTPTR_REG), + .VFG0_ATS_CAP_INV_QUEUE_DEPTH (VFG0_ATS_CAP_INV_QUEUE_DEPTH_REG), + .VFG0_ATS_CAP_NEXTPTR (VFG0_ATS_CAP_NEXTPTR_REG), + .VFG0_ATS_CAP_ON (VFG0_ATS_CAP_ON_REG), + .VFG0_MSIX_CAP_NEXTPTR (VFG0_MSIX_CAP_NEXTPTR_REG), + .VFG0_MSIX_CAP_PBA_BIR (VFG0_MSIX_CAP_PBA_BIR_REG), + .VFG0_MSIX_CAP_PBA_OFFSET (VFG0_MSIX_CAP_PBA_OFFSET_REG), + .VFG0_MSIX_CAP_TABLE_BIR (VFG0_MSIX_CAP_TABLE_BIR_REG), + .VFG0_MSIX_CAP_TABLE_OFFSET (VFG0_MSIX_CAP_TABLE_OFFSET_REG), + .VFG0_MSIX_CAP_TABLE_SIZE (VFG0_MSIX_CAP_TABLE_SIZE_REG), + .VFG0_PCIE_CAP_NEXTPTR (VFG0_PCIE_CAP_NEXTPTR_REG), + .VFG0_TPHR_CAP_NEXTPTR (VFG0_TPHR_CAP_NEXTPTR_REG), + .VFG0_TPHR_CAP_ST_MODE_SEL (VFG0_TPHR_CAP_ST_MODE_SEL_REG), + .VFG1_ARI_CAP_NEXTPTR (VFG1_ARI_CAP_NEXTPTR_REG), + .VFG1_ATS_CAP_INV_QUEUE_DEPTH (VFG1_ATS_CAP_INV_QUEUE_DEPTH_REG), + .VFG1_ATS_CAP_NEXTPTR (VFG1_ATS_CAP_NEXTPTR_REG), + .VFG1_ATS_CAP_ON (VFG1_ATS_CAP_ON_REG), + .VFG1_MSIX_CAP_NEXTPTR (VFG1_MSIX_CAP_NEXTPTR_REG), + .VFG1_MSIX_CAP_PBA_BIR (VFG1_MSIX_CAP_PBA_BIR_REG), + .VFG1_MSIX_CAP_PBA_OFFSET (VFG1_MSIX_CAP_PBA_OFFSET_REG), + .VFG1_MSIX_CAP_TABLE_BIR (VFG1_MSIX_CAP_TABLE_BIR_REG), + .VFG1_MSIX_CAP_TABLE_OFFSET (VFG1_MSIX_CAP_TABLE_OFFSET_REG), + .VFG1_MSIX_CAP_TABLE_SIZE (VFG1_MSIX_CAP_TABLE_SIZE_REG), + .VFG1_PCIE_CAP_NEXTPTR (VFG1_PCIE_CAP_NEXTPTR_REG), + .VFG1_TPHR_CAP_NEXTPTR (VFG1_TPHR_CAP_NEXTPTR_REG), + .VFG1_TPHR_CAP_ST_MODE_SEL (VFG1_TPHR_CAP_ST_MODE_SEL_REG), + .VFG2_ARI_CAP_NEXTPTR (VFG2_ARI_CAP_NEXTPTR_REG), + .VFG2_ATS_CAP_INV_QUEUE_DEPTH (VFG2_ATS_CAP_INV_QUEUE_DEPTH_REG), + .VFG2_ATS_CAP_NEXTPTR (VFG2_ATS_CAP_NEXTPTR_REG), + .VFG2_ATS_CAP_ON (VFG2_ATS_CAP_ON_REG), + .VFG2_MSIX_CAP_NEXTPTR (VFG2_MSIX_CAP_NEXTPTR_REG), + .VFG2_MSIX_CAP_PBA_BIR (VFG2_MSIX_CAP_PBA_BIR_REG), + .VFG2_MSIX_CAP_PBA_OFFSET (VFG2_MSIX_CAP_PBA_OFFSET_REG), + .VFG2_MSIX_CAP_TABLE_BIR (VFG2_MSIX_CAP_TABLE_BIR_REG), + .VFG2_MSIX_CAP_TABLE_OFFSET (VFG2_MSIX_CAP_TABLE_OFFSET_REG), + .VFG2_MSIX_CAP_TABLE_SIZE (VFG2_MSIX_CAP_TABLE_SIZE_REG), + .VFG2_PCIE_CAP_NEXTPTR (VFG2_PCIE_CAP_NEXTPTR_REG), + .VFG2_TPHR_CAP_NEXTPTR (VFG2_TPHR_CAP_NEXTPTR_REG), + .VFG2_TPHR_CAP_ST_MODE_SEL (VFG2_TPHR_CAP_ST_MODE_SEL_REG), + .VFG3_ARI_CAP_NEXTPTR (VFG3_ARI_CAP_NEXTPTR_REG), + .VFG3_ATS_CAP_INV_QUEUE_DEPTH (VFG3_ATS_CAP_INV_QUEUE_DEPTH_REG), + .VFG3_ATS_CAP_NEXTPTR (VFG3_ATS_CAP_NEXTPTR_REG), + .VFG3_ATS_CAP_ON (VFG3_ATS_CAP_ON_REG), + .VFG3_MSIX_CAP_NEXTPTR (VFG3_MSIX_CAP_NEXTPTR_REG), + .VFG3_MSIX_CAP_PBA_BIR (VFG3_MSIX_CAP_PBA_BIR_REG), + .VFG3_MSIX_CAP_PBA_OFFSET (VFG3_MSIX_CAP_PBA_OFFSET_REG), + .VFG3_MSIX_CAP_TABLE_BIR (VFG3_MSIX_CAP_TABLE_BIR_REG), + .VFG3_MSIX_CAP_TABLE_OFFSET (VFG3_MSIX_CAP_TABLE_OFFSET_REG), + .VFG3_MSIX_CAP_TABLE_SIZE (VFG3_MSIX_CAP_TABLE_SIZE_REG), + .VFG3_PCIE_CAP_NEXTPTR (VFG3_PCIE_CAP_NEXTPTR_REG), + .VFG3_TPHR_CAP_NEXTPTR (VFG3_TPHR_CAP_NEXTPTR_REG), + .VFG3_TPHR_CAP_ST_MODE_SEL (VFG3_TPHR_CAP_ST_MODE_SEL_REG), + .AXIUSEROUT (AXIUSEROUT_out), + .CCIXTXCREDIT (CCIXTXCREDIT_out), + .CFGBUSNUMBER (CFGBUSNUMBER_out), + .CFGCURRENTSPEED (CFGCURRENTSPEED_out), + .CFGERRCOROUT (CFGERRCOROUT_out), + .CFGERRFATALOUT (CFGERRFATALOUT_out), + .CFGERRNONFATALOUT (CFGERRNONFATALOUT_out), + .CFGEXTFUNCTIONNUMBER (CFGEXTFUNCTIONNUMBER_out), + .CFGEXTREADRECEIVED (CFGEXTREADRECEIVED_out), + .CFGEXTREGISTERNUMBER (CFGEXTREGISTERNUMBER_out), + .CFGEXTWRITEBYTEENABLE (CFGEXTWRITEBYTEENABLE_out), + .CFGEXTWRITEDATA (CFGEXTWRITEDATA_out), + .CFGEXTWRITERECEIVED (CFGEXTWRITERECEIVED_out), + .CFGFCCPLD (CFGFCCPLD_out), + .CFGFCCPLH (CFGFCCPLH_out), + .CFGFCNPD (CFGFCNPD_out), + .CFGFCNPH (CFGFCNPH_out), + .CFGFCPD (CFGFCPD_out), + .CFGFCPH (CFGFCPH_out), + .CFGFLRINPROCESS (CFGFLRINPROCESS_out), + .CFGFUNCTIONPOWERSTATE (CFGFUNCTIONPOWERSTATE_out), + .CFGFUNCTIONSTATUS (CFGFUNCTIONSTATUS_out), + .CFGHOTRESETOUT (CFGHOTRESETOUT_out), + .CFGINTERRUPTMSIDATA (CFGINTERRUPTMSIDATA_out), + .CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE_out), + .CFGINTERRUPTMSIFAIL (CFGINTERRUPTMSIFAIL_out), + .CFGINTERRUPTMSIMASKUPDATE (CFGINTERRUPTMSIMASKUPDATE_out), + .CFGINTERRUPTMSIMMENABLE (CFGINTERRUPTMSIMMENABLE_out), + .CFGINTERRUPTMSISENT (CFGINTERRUPTMSISENT_out), + .CFGINTERRUPTMSIXENABLE (CFGINTERRUPTMSIXENABLE_out), + .CFGINTERRUPTMSIXMASK (CFGINTERRUPTMSIXMASK_out), + .CFGINTERRUPTMSIXVECPENDINGSTATUS (CFGINTERRUPTMSIXVECPENDINGSTATUS_out), + .CFGINTERRUPTSENT (CFGINTERRUPTSENT_out), + .CFGLINKPOWERSTATE (CFGLINKPOWERSTATE_out), + .CFGLOCALERROROUT (CFGLOCALERROROUT_out), + .CFGLOCALERRORVALID (CFGLOCALERRORVALID_out), + .CFGLTRENABLE (CFGLTRENABLE_out), + .CFGLTSSMSTATE (CFGLTSSMSTATE_out), + .CFGMAXPAYLOAD (CFGMAXPAYLOAD_out), + .CFGMAXREADREQ (CFGMAXREADREQ_out), + .CFGMGMTREADDATA (CFGMGMTREADDATA_out), + .CFGMGMTREADWRITEDONE (CFGMGMTREADWRITEDONE_out), + .CFGMSGRECEIVED (CFGMSGRECEIVED_out), + .CFGMSGRECEIVEDDATA (CFGMSGRECEIVEDDATA_out), + .CFGMSGRECEIVEDTYPE (CFGMSGRECEIVEDTYPE_out), + .CFGMSGTRANSMITDONE (CFGMSGTRANSMITDONE_out), + .CFGMSIXRAMADDRESS (CFGMSIXRAMADDRESS_out), + .CFGMSIXRAMREADENABLE (CFGMSIXRAMREADENABLE_out), + .CFGMSIXRAMWRITEBYTEENABLE (CFGMSIXRAMWRITEBYTEENABLE_out), + .CFGMSIXRAMWRITEDATA (CFGMSIXRAMWRITEDATA_out), + .CFGNEGOTIATEDWIDTH (CFGNEGOTIATEDWIDTH_out), + .CFGOBFFENABLE (CFGOBFFENABLE_out), + .CFGPHYLINKDOWN (CFGPHYLINKDOWN_out), + .CFGPHYLINKSTATUS (CFGPHYLINKSTATUS_out), + .CFGPLSTATUSCHANGE (CFGPLSTATUSCHANGE_out), + .CFGPOWERSTATECHANGEINTERRUPT (CFGPOWERSTATECHANGEINTERRUPT_out), + .CFGRCBSTATUS (CFGRCBSTATUS_out), + .CFGRXPMSTATE (CFGRXPMSTATE_out), + .CFGTPHRAMADDRESS (CFGTPHRAMADDRESS_out), + .CFGTPHRAMREADENABLE (CFGTPHRAMREADENABLE_out), + .CFGTPHRAMWRITEBYTEENABLE (CFGTPHRAMWRITEBYTEENABLE_out), + .CFGTPHRAMWRITEDATA (CFGTPHRAMWRITEDATA_out), + .CFGTPHREQUESTERENABLE (CFGTPHREQUESTERENABLE_out), + .CFGTPHSTMODE (CFGTPHSTMODE_out), + .CFGTXPMSTATE (CFGTXPMSTATE_out), + .CFGVC1ENABLE (CFGVC1ENABLE_out), + .CFGVC1NEGOTIATIONPENDING (CFGVC1NEGOTIATIONPENDING_out), + .CONFMCAPDESIGNSWITCH (CONFMCAPDESIGNSWITCH_out), + .CONFMCAPEOS (CONFMCAPEOS_out), + .CONFMCAPINUSEBYPCIE (CONFMCAPINUSEBYPCIE_out), + .CONFREQREADY (CONFREQREADY_out), + .CONFRESPRDATA (CONFRESPRDATA_out), + .CONFRESPVALID (CONFRESPVALID_out), + .DBGCCIXOUT (DBGCCIXOUT_out), + .DBGCTRL0OUT (DBGCTRL0OUT_out), + .DBGCTRL1OUT (DBGCTRL1OUT_out), + .DBGDATA0OUT (DBGDATA0OUT_out), + .DBGDATA1OUT (DBGDATA1OUT_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .MAXISCCIXRXTUSER (MAXISCCIXRXTUSER_out), + .MAXISCCIXRXTVALID (MAXISCCIXRXTVALID_out), + .MAXISCQTDATA (MAXISCQTDATA_out), + .MAXISCQTKEEP (MAXISCQTKEEP_out), + .MAXISCQTLAST (MAXISCQTLAST_out), + .MAXISCQTUSER (MAXISCQTUSER_out), + .MAXISCQTVALID (MAXISCQTVALID_out), + .MAXISRCTDATA (MAXISRCTDATA_out), + .MAXISRCTKEEP (MAXISRCTKEEP_out), + .MAXISRCTLAST (MAXISRCTLAST_out), + .MAXISRCTUSER (MAXISRCTUSER_out), + .MAXISRCTVALID (MAXISRCTVALID_out), + .MIREPLAYRAMADDRESS0 (MIREPLAYRAMADDRESS0_out), + .MIREPLAYRAMADDRESS1 (MIREPLAYRAMADDRESS1_out), + .MIREPLAYRAMREADENABLE0 (MIREPLAYRAMREADENABLE0_out), + .MIREPLAYRAMREADENABLE1 (MIREPLAYRAMREADENABLE1_out), + .MIREPLAYRAMWRITEDATA0 (MIREPLAYRAMWRITEDATA0_out), + .MIREPLAYRAMWRITEDATA1 (MIREPLAYRAMWRITEDATA1_out), + .MIREPLAYRAMWRITEENABLE0 (MIREPLAYRAMWRITEENABLE0_out), + .MIREPLAYRAMWRITEENABLE1 (MIREPLAYRAMWRITEENABLE1_out), + .MIRXCOMPLETIONRAMREADADDRESS0 (MIRXCOMPLETIONRAMREADADDRESS0_out), + .MIRXCOMPLETIONRAMREADADDRESS1 (MIRXCOMPLETIONRAMREADADDRESS1_out), + .MIRXCOMPLETIONRAMREADENABLE0 (MIRXCOMPLETIONRAMREADENABLE0_out), + .MIRXCOMPLETIONRAMREADENABLE1 (MIRXCOMPLETIONRAMREADENABLE1_out), + .MIRXCOMPLETIONRAMWRITEADDRESS0 (MIRXCOMPLETIONRAMWRITEADDRESS0_out), + .MIRXCOMPLETIONRAMWRITEADDRESS1 (MIRXCOMPLETIONRAMWRITEADDRESS1_out), + .MIRXCOMPLETIONRAMWRITEDATA0 (MIRXCOMPLETIONRAMWRITEDATA0_out), + .MIRXCOMPLETIONRAMWRITEDATA1 (MIRXCOMPLETIONRAMWRITEDATA1_out), + .MIRXCOMPLETIONRAMWRITEENABLE0 (MIRXCOMPLETIONRAMWRITEENABLE0_out), + .MIRXCOMPLETIONRAMWRITEENABLE1 (MIRXCOMPLETIONRAMWRITEENABLE1_out), + .MIRXPOSTEDREQUESTRAMREADADDRESS0 (MIRXPOSTEDREQUESTRAMREADADDRESS0_out), + .MIRXPOSTEDREQUESTRAMREADADDRESS1 (MIRXPOSTEDREQUESTRAMREADADDRESS1_out), + .MIRXPOSTEDREQUESTRAMREADENABLE0 (MIRXPOSTEDREQUESTRAMREADENABLE0_out), + .MIRXPOSTEDREQUESTRAMREADENABLE1 (MIRXPOSTEDREQUESTRAMREADENABLE1_out), + .MIRXPOSTEDREQUESTRAMWRITEADDRESS0 (MIRXPOSTEDREQUESTRAMWRITEADDRESS0_out), + .MIRXPOSTEDREQUESTRAMWRITEADDRESS1 (MIRXPOSTEDREQUESTRAMWRITEADDRESS1_out), + .MIRXPOSTEDREQUESTRAMWRITEDATA0 (MIRXPOSTEDREQUESTRAMWRITEDATA0_out), + .MIRXPOSTEDREQUESTRAMWRITEDATA1 (MIRXPOSTEDREQUESTRAMWRITEDATA1_out), + .MIRXPOSTEDREQUESTRAMWRITEENABLE0 (MIRXPOSTEDREQUESTRAMWRITEENABLE0_out), + .MIRXPOSTEDREQUESTRAMWRITEENABLE1 (MIRXPOSTEDREQUESTRAMWRITEENABLE1_out), + .PCIECQNPREQCOUNT (PCIECQNPREQCOUNT_out), + .PCIEPERST0B (PCIEPERST0B_out), + .PCIEPERST1B (PCIEPERST1B_out), + .PCIERQSEQNUM0 (PCIERQSEQNUM0_out), + .PCIERQSEQNUM1 (PCIERQSEQNUM1_out), + .PCIERQSEQNUMVLD0 (PCIERQSEQNUMVLD0_out), + .PCIERQSEQNUMVLD1 (PCIERQSEQNUMVLD1_out), + .PCIERQTAG0 (PCIERQTAG0_out), + .PCIERQTAG1 (PCIERQTAG1_out), + .PCIERQTAGAV (PCIERQTAGAV_out), + .PCIERQTAGVLD0 (PCIERQTAGVLD0_out), + .PCIERQTAGVLD1 (PCIERQTAGVLD1_out), + .PCIETFCNPDAV (PCIETFCNPDAV_out), + .PCIETFCNPHAV (PCIETFCNPHAV_out), + .PIPERX00EQCONTROL (PIPERX00EQCONTROL_out), + .PIPERX00POLARITY (PIPERX00POLARITY_out), + .PIPERX01EQCONTROL (PIPERX01EQCONTROL_out), + .PIPERX01POLARITY (PIPERX01POLARITY_out), + .PIPERX02EQCONTROL (PIPERX02EQCONTROL_out), + .PIPERX02POLARITY (PIPERX02POLARITY_out), + .PIPERX03EQCONTROL (PIPERX03EQCONTROL_out), + .PIPERX03POLARITY (PIPERX03POLARITY_out), + .PIPERX04EQCONTROL (PIPERX04EQCONTROL_out), + .PIPERX04POLARITY (PIPERX04POLARITY_out), + .PIPERX05EQCONTROL (PIPERX05EQCONTROL_out), + .PIPERX05POLARITY (PIPERX05POLARITY_out), + .PIPERX06EQCONTROL (PIPERX06EQCONTROL_out), + .PIPERX06POLARITY (PIPERX06POLARITY_out), + .PIPERX07EQCONTROL (PIPERX07EQCONTROL_out), + .PIPERX07POLARITY (PIPERX07POLARITY_out), + .PIPERX08EQCONTROL (PIPERX08EQCONTROL_out), + .PIPERX08POLARITY (PIPERX08POLARITY_out), + .PIPERX09EQCONTROL (PIPERX09EQCONTROL_out), + .PIPERX09POLARITY (PIPERX09POLARITY_out), + .PIPERX10EQCONTROL (PIPERX10EQCONTROL_out), + .PIPERX10POLARITY (PIPERX10POLARITY_out), + .PIPERX11EQCONTROL (PIPERX11EQCONTROL_out), + .PIPERX11POLARITY (PIPERX11POLARITY_out), + .PIPERX12EQCONTROL (PIPERX12EQCONTROL_out), + .PIPERX12POLARITY (PIPERX12POLARITY_out), + .PIPERX13EQCONTROL (PIPERX13EQCONTROL_out), + .PIPERX13POLARITY (PIPERX13POLARITY_out), + .PIPERX14EQCONTROL (PIPERX14EQCONTROL_out), + .PIPERX14POLARITY (PIPERX14POLARITY_out), + .PIPERX15EQCONTROL (PIPERX15EQCONTROL_out), + .PIPERX15POLARITY (PIPERX15POLARITY_out), + .PIPERXEQLPLFFS (PIPERXEQLPLFFS_out), + .PIPERXEQLPTXPRESET (PIPERXEQLPTXPRESET_out), + .PIPETX00CHARISK (PIPETX00CHARISK_out), + .PIPETX00COMPLIANCE (PIPETX00COMPLIANCE_out), + .PIPETX00DATA (PIPETX00DATA_out), + .PIPETX00DATAVALID (PIPETX00DATAVALID_out), + .PIPETX00ELECIDLE (PIPETX00ELECIDLE_out), + .PIPETX00EQCONTROL (PIPETX00EQCONTROL_out), + .PIPETX00EQDEEMPH (PIPETX00EQDEEMPH_out), + .PIPETX00POWERDOWN (PIPETX00POWERDOWN_out), + .PIPETX00STARTBLOCK (PIPETX00STARTBLOCK_out), + .PIPETX00SYNCHEADER (PIPETX00SYNCHEADER_out), + .PIPETX01CHARISK (PIPETX01CHARISK_out), + .PIPETX01COMPLIANCE (PIPETX01COMPLIANCE_out), + .PIPETX01DATA (PIPETX01DATA_out), + .PIPETX01DATAVALID (PIPETX01DATAVALID_out), + .PIPETX01ELECIDLE (PIPETX01ELECIDLE_out), + .PIPETX01EQCONTROL (PIPETX01EQCONTROL_out), + .PIPETX01EQDEEMPH (PIPETX01EQDEEMPH_out), + .PIPETX01POWERDOWN (PIPETX01POWERDOWN_out), + .PIPETX01STARTBLOCK (PIPETX01STARTBLOCK_out), + .PIPETX01SYNCHEADER (PIPETX01SYNCHEADER_out), + .PIPETX02CHARISK (PIPETX02CHARISK_out), + .PIPETX02COMPLIANCE (PIPETX02COMPLIANCE_out), + .PIPETX02DATA (PIPETX02DATA_out), + .PIPETX02DATAVALID (PIPETX02DATAVALID_out), + .PIPETX02ELECIDLE (PIPETX02ELECIDLE_out), + .PIPETX02EQCONTROL (PIPETX02EQCONTROL_out), + .PIPETX02EQDEEMPH (PIPETX02EQDEEMPH_out), + .PIPETX02POWERDOWN (PIPETX02POWERDOWN_out), + .PIPETX02STARTBLOCK (PIPETX02STARTBLOCK_out), + .PIPETX02SYNCHEADER (PIPETX02SYNCHEADER_out), + .PIPETX03CHARISK (PIPETX03CHARISK_out), + .PIPETX03COMPLIANCE (PIPETX03COMPLIANCE_out), + .PIPETX03DATA (PIPETX03DATA_out), + .PIPETX03DATAVALID (PIPETX03DATAVALID_out), + .PIPETX03ELECIDLE (PIPETX03ELECIDLE_out), + .PIPETX03EQCONTROL (PIPETX03EQCONTROL_out), + .PIPETX03EQDEEMPH (PIPETX03EQDEEMPH_out), + .PIPETX03POWERDOWN (PIPETX03POWERDOWN_out), + .PIPETX03STARTBLOCK (PIPETX03STARTBLOCK_out), + .PIPETX03SYNCHEADER (PIPETX03SYNCHEADER_out), + .PIPETX04CHARISK (PIPETX04CHARISK_out), + .PIPETX04COMPLIANCE (PIPETX04COMPLIANCE_out), + .PIPETX04DATA (PIPETX04DATA_out), + .PIPETX04DATAVALID (PIPETX04DATAVALID_out), + .PIPETX04ELECIDLE (PIPETX04ELECIDLE_out), + .PIPETX04EQCONTROL (PIPETX04EQCONTROL_out), + .PIPETX04EQDEEMPH (PIPETX04EQDEEMPH_out), + .PIPETX04POWERDOWN (PIPETX04POWERDOWN_out), + .PIPETX04STARTBLOCK (PIPETX04STARTBLOCK_out), + .PIPETX04SYNCHEADER (PIPETX04SYNCHEADER_out), + .PIPETX05CHARISK (PIPETX05CHARISK_out), + .PIPETX05COMPLIANCE (PIPETX05COMPLIANCE_out), + .PIPETX05DATA (PIPETX05DATA_out), + .PIPETX05DATAVALID (PIPETX05DATAVALID_out), + .PIPETX05ELECIDLE (PIPETX05ELECIDLE_out), + .PIPETX05EQCONTROL (PIPETX05EQCONTROL_out), + .PIPETX05EQDEEMPH (PIPETX05EQDEEMPH_out), + .PIPETX05POWERDOWN (PIPETX05POWERDOWN_out), + .PIPETX05STARTBLOCK (PIPETX05STARTBLOCK_out), + .PIPETX05SYNCHEADER (PIPETX05SYNCHEADER_out), + .PIPETX06CHARISK (PIPETX06CHARISK_out), + .PIPETX06COMPLIANCE (PIPETX06COMPLIANCE_out), + .PIPETX06DATA (PIPETX06DATA_out), + .PIPETX06DATAVALID (PIPETX06DATAVALID_out), + .PIPETX06ELECIDLE (PIPETX06ELECIDLE_out), + .PIPETX06EQCONTROL (PIPETX06EQCONTROL_out), + .PIPETX06EQDEEMPH (PIPETX06EQDEEMPH_out), + .PIPETX06POWERDOWN (PIPETX06POWERDOWN_out), + .PIPETX06STARTBLOCK (PIPETX06STARTBLOCK_out), + .PIPETX06SYNCHEADER (PIPETX06SYNCHEADER_out), + .PIPETX07CHARISK (PIPETX07CHARISK_out), + .PIPETX07COMPLIANCE (PIPETX07COMPLIANCE_out), + .PIPETX07DATA (PIPETX07DATA_out), + .PIPETX07DATAVALID (PIPETX07DATAVALID_out), + .PIPETX07ELECIDLE (PIPETX07ELECIDLE_out), + .PIPETX07EQCONTROL (PIPETX07EQCONTROL_out), + .PIPETX07EQDEEMPH (PIPETX07EQDEEMPH_out), + .PIPETX07POWERDOWN (PIPETX07POWERDOWN_out), + .PIPETX07STARTBLOCK (PIPETX07STARTBLOCK_out), + .PIPETX07SYNCHEADER (PIPETX07SYNCHEADER_out), + .PIPETX08CHARISK (PIPETX08CHARISK_out), + .PIPETX08COMPLIANCE (PIPETX08COMPLIANCE_out), + .PIPETX08DATA (PIPETX08DATA_out), + .PIPETX08DATAVALID (PIPETX08DATAVALID_out), + .PIPETX08ELECIDLE (PIPETX08ELECIDLE_out), + .PIPETX08EQCONTROL (PIPETX08EQCONTROL_out), + .PIPETX08EQDEEMPH (PIPETX08EQDEEMPH_out), + .PIPETX08POWERDOWN (PIPETX08POWERDOWN_out), + .PIPETX08STARTBLOCK (PIPETX08STARTBLOCK_out), + .PIPETX08SYNCHEADER (PIPETX08SYNCHEADER_out), + .PIPETX09CHARISK (PIPETX09CHARISK_out), + .PIPETX09COMPLIANCE (PIPETX09COMPLIANCE_out), + .PIPETX09DATA (PIPETX09DATA_out), + .PIPETX09DATAVALID (PIPETX09DATAVALID_out), + .PIPETX09ELECIDLE (PIPETX09ELECIDLE_out), + .PIPETX09EQCONTROL (PIPETX09EQCONTROL_out), + .PIPETX09EQDEEMPH (PIPETX09EQDEEMPH_out), + .PIPETX09POWERDOWN (PIPETX09POWERDOWN_out), + .PIPETX09STARTBLOCK (PIPETX09STARTBLOCK_out), + .PIPETX09SYNCHEADER (PIPETX09SYNCHEADER_out), + .PIPETX10CHARISK (PIPETX10CHARISK_out), + .PIPETX10COMPLIANCE (PIPETX10COMPLIANCE_out), + .PIPETX10DATA (PIPETX10DATA_out), + .PIPETX10DATAVALID (PIPETX10DATAVALID_out), + .PIPETX10ELECIDLE (PIPETX10ELECIDLE_out), + .PIPETX10EQCONTROL (PIPETX10EQCONTROL_out), + .PIPETX10EQDEEMPH (PIPETX10EQDEEMPH_out), + .PIPETX10POWERDOWN (PIPETX10POWERDOWN_out), + .PIPETX10STARTBLOCK (PIPETX10STARTBLOCK_out), + .PIPETX10SYNCHEADER (PIPETX10SYNCHEADER_out), + .PIPETX11CHARISK (PIPETX11CHARISK_out), + .PIPETX11COMPLIANCE (PIPETX11COMPLIANCE_out), + .PIPETX11DATA (PIPETX11DATA_out), + .PIPETX11DATAVALID (PIPETX11DATAVALID_out), + .PIPETX11ELECIDLE (PIPETX11ELECIDLE_out), + .PIPETX11EQCONTROL (PIPETX11EQCONTROL_out), + .PIPETX11EQDEEMPH (PIPETX11EQDEEMPH_out), + .PIPETX11POWERDOWN (PIPETX11POWERDOWN_out), + .PIPETX11STARTBLOCK (PIPETX11STARTBLOCK_out), + .PIPETX11SYNCHEADER (PIPETX11SYNCHEADER_out), + .PIPETX12CHARISK (PIPETX12CHARISK_out), + .PIPETX12COMPLIANCE (PIPETX12COMPLIANCE_out), + .PIPETX12DATA (PIPETX12DATA_out), + .PIPETX12DATAVALID (PIPETX12DATAVALID_out), + .PIPETX12ELECIDLE (PIPETX12ELECIDLE_out), + .PIPETX12EQCONTROL (PIPETX12EQCONTROL_out), + .PIPETX12EQDEEMPH (PIPETX12EQDEEMPH_out), + .PIPETX12POWERDOWN (PIPETX12POWERDOWN_out), + .PIPETX12STARTBLOCK (PIPETX12STARTBLOCK_out), + .PIPETX12SYNCHEADER (PIPETX12SYNCHEADER_out), + .PIPETX13CHARISK (PIPETX13CHARISK_out), + .PIPETX13COMPLIANCE (PIPETX13COMPLIANCE_out), + .PIPETX13DATA (PIPETX13DATA_out), + .PIPETX13DATAVALID (PIPETX13DATAVALID_out), + .PIPETX13ELECIDLE (PIPETX13ELECIDLE_out), + .PIPETX13EQCONTROL (PIPETX13EQCONTROL_out), + .PIPETX13EQDEEMPH (PIPETX13EQDEEMPH_out), + .PIPETX13POWERDOWN (PIPETX13POWERDOWN_out), + .PIPETX13STARTBLOCK (PIPETX13STARTBLOCK_out), + .PIPETX13SYNCHEADER (PIPETX13SYNCHEADER_out), + .PIPETX14CHARISK (PIPETX14CHARISK_out), + .PIPETX14COMPLIANCE (PIPETX14COMPLIANCE_out), + .PIPETX14DATA (PIPETX14DATA_out), + .PIPETX14DATAVALID (PIPETX14DATAVALID_out), + .PIPETX14ELECIDLE (PIPETX14ELECIDLE_out), + .PIPETX14EQCONTROL (PIPETX14EQCONTROL_out), + .PIPETX14EQDEEMPH (PIPETX14EQDEEMPH_out), + .PIPETX14POWERDOWN (PIPETX14POWERDOWN_out), + .PIPETX14STARTBLOCK (PIPETX14STARTBLOCK_out), + .PIPETX14SYNCHEADER (PIPETX14SYNCHEADER_out), + .PIPETX15CHARISK (PIPETX15CHARISK_out), + .PIPETX15COMPLIANCE (PIPETX15COMPLIANCE_out), + .PIPETX15DATA (PIPETX15DATA_out), + .PIPETX15DATAVALID (PIPETX15DATAVALID_out), + .PIPETX15ELECIDLE (PIPETX15ELECIDLE_out), + .PIPETX15EQCONTROL (PIPETX15EQCONTROL_out), + .PIPETX15EQDEEMPH (PIPETX15EQDEEMPH_out), + .PIPETX15POWERDOWN (PIPETX15POWERDOWN_out), + .PIPETX15STARTBLOCK (PIPETX15STARTBLOCK_out), + .PIPETX15SYNCHEADER (PIPETX15SYNCHEADER_out), + .PIPETXDEEMPH (PIPETXDEEMPH_out), + .PIPETXMARGIN (PIPETXMARGIN_out), + .PIPETXRATE (PIPETXRATE_out), + .PIPETXRCVRDET (PIPETXRCVRDET_out), + .PIPETXRESET (PIPETXRESET_out), + .PIPETXSWING (PIPETXSWING_out), + .PLEQINPROGRESS (PLEQINPROGRESS_out), + .PLEQPHASE (PLEQPHASE_out), + .PLGEN34EQMISMATCH (PLGEN34EQMISMATCH_out), + .PMVOUT (PMVOUT_out), + .SAXISCCTREADY (SAXISCCTREADY_out), + .SAXISRQTREADY (SAXISRQTREADY_out), + .USERSPAREOUT (USERSPAREOUT_out), + .AXIUSERIN (AXIUSERIN_in), + .CCIXOPTIMIZEDTLPTXANDRXENABLE (CCIXOPTIMIZEDTLPTXANDRXENABLE_in), + .CCIXRXCORRECTABLEERRORDETECTED (CCIXRXCORRECTABLEERRORDETECTED_in), + .CCIXRXFIFOOVERFLOW (CCIXRXFIFOOVERFLOW_in), + .CCIXRXTLPFORWARDED0 (CCIXRXTLPFORWARDED0_in), + .CCIXRXTLPFORWARDED1 (CCIXRXTLPFORWARDED1_in), + .CCIXRXTLPFORWARDEDLENGTH0 (CCIXRXTLPFORWARDEDLENGTH0_in), + .CCIXRXTLPFORWARDEDLENGTH1 (CCIXRXTLPFORWARDEDLENGTH1_in), + .CCIXRXUNCORRECTABLEERRORDETECTED (CCIXRXUNCORRECTABLEERRORDETECTED_in), + .CFGCONFIGSPACEENABLE (CFGCONFIGSPACEENABLE_in), + .CFGDEVIDPF0 (CFGDEVIDPF0_in), + .CFGDEVIDPF1 (CFGDEVIDPF1_in), + .CFGDEVIDPF2 (CFGDEVIDPF2_in), + .CFGDEVIDPF3 (CFGDEVIDPF3_in), + .CFGDSBUSNUMBER (CFGDSBUSNUMBER_in), + .CFGDSDEVICENUMBER (CFGDSDEVICENUMBER_in), + .CFGDSFUNCTIONNUMBER (CFGDSFUNCTIONNUMBER_in), + .CFGDSN (CFGDSN_in), + .CFGDSPORTNUMBER (CFGDSPORTNUMBER_in), + .CFGERRCORIN (CFGERRCORIN_in), + .CFGERRUNCORIN (CFGERRUNCORIN_in), + .CFGEXTREADDATA (CFGEXTREADDATA_in), + .CFGEXTREADDATAVALID (CFGEXTREADDATAVALID_in), + .CFGFCSEL (CFGFCSEL_in), + .CFGFCVCSEL (CFGFCVCSEL_in), + .CFGFLRDONE (CFGFLRDONE_in), + .CFGHOTRESETIN (CFGHOTRESETIN_in), + .CFGINTERRUPTINT (CFGINTERRUPTINT_in), + .CFGINTERRUPTMSIATTR (CFGINTERRUPTMSIATTR_in), + .CFGINTERRUPTMSIFUNCTIONNUMBER (CFGINTERRUPTMSIFUNCTIONNUMBER_in), + .CFGINTERRUPTMSIINT (CFGINTERRUPTMSIINT_in), + .CFGINTERRUPTMSIPENDINGSTATUS (CFGINTERRUPTMSIPENDINGSTATUS_in), + .CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in), + .CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in), + .CFGINTERRUPTMSISELECT (CFGINTERRUPTMSISELECT_in), + .CFGINTERRUPTMSITPHPRESENT (CFGINTERRUPTMSITPHPRESENT_in), + .CFGINTERRUPTMSITPHSTTAG (CFGINTERRUPTMSITPHSTTAG_in), + .CFGINTERRUPTMSITPHTYPE (CFGINTERRUPTMSITPHTYPE_in), + .CFGINTERRUPTMSIXADDRESS (CFGINTERRUPTMSIXADDRESS_in), + .CFGINTERRUPTMSIXDATA (CFGINTERRUPTMSIXDATA_in), + .CFGINTERRUPTMSIXINT (CFGINTERRUPTMSIXINT_in), + .CFGINTERRUPTMSIXVECPENDING (CFGINTERRUPTMSIXVECPENDING_in), + .CFGINTERRUPTPENDING (CFGINTERRUPTPENDING_in), + .CFGLINKTRAININGENABLE (CFGLINKTRAININGENABLE_in), + .CFGMGMTADDR (CFGMGMTADDR_in), + .CFGMGMTBYTEENABLE (CFGMGMTBYTEENABLE_in), + .CFGMGMTDEBUGACCESS (CFGMGMTDEBUGACCESS_in), + .CFGMGMTFUNCTIONNUMBER (CFGMGMTFUNCTIONNUMBER_in), + .CFGMGMTREAD (CFGMGMTREAD_in), + .CFGMGMTWRITE (CFGMGMTWRITE_in), + .CFGMGMTWRITEDATA (CFGMGMTWRITEDATA_in), + .CFGMSGTRANSMIT (CFGMSGTRANSMIT_in), + .CFGMSGTRANSMITDATA (CFGMSGTRANSMITDATA_in), + .CFGMSGTRANSMITTYPE (CFGMSGTRANSMITTYPE_in), + .CFGMSIXRAMREADDATA (CFGMSIXRAMREADDATA_in), + .CFGPMASPML1ENTRYREJECT (CFGPMASPML1ENTRYREJECT_in), + .CFGPMASPMTXL0SENTRYDISABLE (CFGPMASPMTXL0SENTRYDISABLE_in), + .CFGPOWERSTATECHANGEACK (CFGPOWERSTATECHANGEACK_in), + .CFGREQPMTRANSITIONL23READY (CFGREQPMTRANSITIONL23READY_in), + .CFGREVIDPF0 (CFGREVIDPF0_in), + .CFGREVIDPF1 (CFGREVIDPF1_in), + .CFGREVIDPF2 (CFGREVIDPF2_in), + .CFGREVIDPF3 (CFGREVIDPF3_in), + .CFGSUBSYSIDPF0 (CFGSUBSYSIDPF0_in), + .CFGSUBSYSIDPF1 (CFGSUBSYSIDPF1_in), + .CFGSUBSYSIDPF2 (CFGSUBSYSIDPF2_in), + .CFGSUBSYSIDPF3 (CFGSUBSYSIDPF3_in), + .CFGSUBSYSVENDID (CFGSUBSYSVENDID_in), + .CFGTPHRAMREADDATA (CFGTPHRAMREADDATA_in), + .CFGVENDID (CFGVENDID_in), + .CFGVFFLRDONE (CFGVFFLRDONE_in), + .CFGVFFLRFUNCNUM (CFGVFFLRFUNCNUM_in), + .CONFMCAPREQUESTBYCONF (CONFMCAPREQUESTBYCONF_in), + .CONFREQDATA (CONFREQDATA_in), + .CONFREQREGNUM (CONFREQREGNUM_in), + .CONFREQTYPE (CONFREQTYPE_in), + .CONFREQVALID (CONFREQVALID_in), + .CORECLK (CORECLK_in), + .CORECLKCCIX (CORECLKCCIX_in), + .CORECLKMIREPLAYRAM0 (CORECLKMIREPLAYRAM0_in), + .CORECLKMIREPLAYRAM1 (CORECLKMIREPLAYRAM1_in), + .CORECLKMIRXCOMPLETIONRAM0 (CORECLKMIRXCOMPLETIONRAM0_in), + .CORECLKMIRXCOMPLETIONRAM1 (CORECLKMIRXCOMPLETIONRAM1_in), + .CORECLKMIRXPOSTEDREQUESTRAM0 (CORECLKMIRXPOSTEDREQUESTRAM0_in), + .CORECLKMIRXPOSTEDREQUESTRAM1 (CORECLKMIRXPOSTEDREQUESTRAM1_in), + .DBGSEL0 (DBGSEL0_in), + .DBGSEL1 (DBGSEL1_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .MAXISCQTREADY (MAXISCQTREADY_in), + .MAXISRCTREADY (MAXISRCTREADY_in), + .MCAPCLK (MCAPCLK_in), + .MCAPPERST0B (MCAPPERST0B_in), + .MCAPPERST1B (MCAPPERST1B_in), + .MGMTRESETN (MGMTRESETN_in), + .MGMTSTICKYRESETN (MGMTSTICKYRESETN_in), + .MIREPLAYRAMERRCOR (MIREPLAYRAMERRCOR_in), + .MIREPLAYRAMERRUNCOR (MIREPLAYRAMERRUNCOR_in), + .MIREPLAYRAMREADDATA0 (MIREPLAYRAMREADDATA0_in), + .MIREPLAYRAMREADDATA1 (MIREPLAYRAMREADDATA1_in), + .MIRXCOMPLETIONRAMERRCOR (MIRXCOMPLETIONRAMERRCOR_in), + .MIRXCOMPLETIONRAMERRUNCOR (MIRXCOMPLETIONRAMERRUNCOR_in), + .MIRXCOMPLETIONRAMREADDATA0 (MIRXCOMPLETIONRAMREADDATA0_in), + .MIRXCOMPLETIONRAMREADDATA1 (MIRXCOMPLETIONRAMREADDATA1_in), + .MIRXPOSTEDREQUESTRAMERRCOR (MIRXPOSTEDREQUESTRAMERRCOR_in), + .MIRXPOSTEDREQUESTRAMERRUNCOR (MIRXPOSTEDREQUESTRAMERRUNCOR_in), + .MIRXPOSTEDREQUESTRAMREADDATA0 (MIRXPOSTEDREQUESTRAMREADDATA0_in), + .MIRXPOSTEDREQUESTRAMREADDATA1 (MIRXPOSTEDREQUESTRAMREADDATA1_in), + .PCIECOMPLDELIVERED (PCIECOMPLDELIVERED_in), + .PCIECOMPLDELIVEREDTAG0 (PCIECOMPLDELIVEREDTAG0_in), + .PCIECOMPLDELIVEREDTAG1 (PCIECOMPLDELIVEREDTAG1_in), + .PCIECQNPREQ (PCIECQNPREQ_in), + .PCIECQNPUSERCREDITRCVD (PCIECQNPUSERCREDITRCVD_in), + .PCIECQPIPELINEEMPTY (PCIECQPIPELINEEMPTY_in), + .PCIEPOSTEDREQDELIVERED (PCIEPOSTEDREQDELIVERED_in), + .PIPECLK (PIPECLK_in), + .PIPECLKEN (PIPECLKEN_in), + .PIPEEQFS (PIPEEQFS_in), + .PIPEEQLF (PIPEEQLF_in), + .PIPERESETN (PIPERESETN_in), + .PIPERX00CHARISK (PIPERX00CHARISK_in), + .PIPERX00DATA (PIPERX00DATA_in), + .PIPERX00DATAVALID (PIPERX00DATAVALID_in), + .PIPERX00ELECIDLE (PIPERX00ELECIDLE_in), + .PIPERX00EQDONE (PIPERX00EQDONE_in), + .PIPERX00EQLPADAPTDONE (PIPERX00EQLPADAPTDONE_in), + .PIPERX00EQLPLFFSSEL (PIPERX00EQLPLFFSSEL_in), + .PIPERX00EQLPNEWTXCOEFFORPRESET (PIPERX00EQLPNEWTXCOEFFORPRESET_in), + .PIPERX00PHYSTATUS (PIPERX00PHYSTATUS_in), + .PIPERX00STARTBLOCK (PIPERX00STARTBLOCK_in), + .PIPERX00STATUS (PIPERX00STATUS_in), + .PIPERX00SYNCHEADER (PIPERX00SYNCHEADER_in), + .PIPERX00VALID (PIPERX00VALID_in), + .PIPERX01CHARISK (PIPERX01CHARISK_in), + .PIPERX01DATA (PIPERX01DATA_in), + .PIPERX01DATAVALID (PIPERX01DATAVALID_in), + .PIPERX01ELECIDLE (PIPERX01ELECIDLE_in), + .PIPERX01EQDONE (PIPERX01EQDONE_in), + .PIPERX01EQLPADAPTDONE (PIPERX01EQLPADAPTDONE_in), + .PIPERX01EQLPLFFSSEL (PIPERX01EQLPLFFSSEL_in), + .PIPERX01EQLPNEWTXCOEFFORPRESET (PIPERX01EQLPNEWTXCOEFFORPRESET_in), + .PIPERX01PHYSTATUS (PIPERX01PHYSTATUS_in), + .PIPERX01STARTBLOCK (PIPERX01STARTBLOCK_in), + .PIPERX01STATUS (PIPERX01STATUS_in), + .PIPERX01SYNCHEADER (PIPERX01SYNCHEADER_in), + .PIPERX01VALID (PIPERX01VALID_in), + .PIPERX02CHARISK (PIPERX02CHARISK_in), + .PIPERX02DATA (PIPERX02DATA_in), + .PIPERX02DATAVALID (PIPERX02DATAVALID_in), + .PIPERX02ELECIDLE (PIPERX02ELECIDLE_in), + .PIPERX02EQDONE (PIPERX02EQDONE_in), + .PIPERX02EQLPADAPTDONE (PIPERX02EQLPADAPTDONE_in), + .PIPERX02EQLPLFFSSEL (PIPERX02EQLPLFFSSEL_in), + .PIPERX02EQLPNEWTXCOEFFORPRESET (PIPERX02EQLPNEWTXCOEFFORPRESET_in), + .PIPERX02PHYSTATUS (PIPERX02PHYSTATUS_in), + .PIPERX02STARTBLOCK (PIPERX02STARTBLOCK_in), + .PIPERX02STATUS (PIPERX02STATUS_in), + .PIPERX02SYNCHEADER (PIPERX02SYNCHEADER_in), + .PIPERX02VALID (PIPERX02VALID_in), + .PIPERX03CHARISK (PIPERX03CHARISK_in), + .PIPERX03DATA (PIPERX03DATA_in), + .PIPERX03DATAVALID (PIPERX03DATAVALID_in), + .PIPERX03ELECIDLE (PIPERX03ELECIDLE_in), + .PIPERX03EQDONE (PIPERX03EQDONE_in), + .PIPERX03EQLPADAPTDONE (PIPERX03EQLPADAPTDONE_in), + .PIPERX03EQLPLFFSSEL (PIPERX03EQLPLFFSSEL_in), + .PIPERX03EQLPNEWTXCOEFFORPRESET (PIPERX03EQLPNEWTXCOEFFORPRESET_in), + .PIPERX03PHYSTATUS (PIPERX03PHYSTATUS_in), + .PIPERX03STARTBLOCK (PIPERX03STARTBLOCK_in), + .PIPERX03STATUS (PIPERX03STATUS_in), + .PIPERX03SYNCHEADER (PIPERX03SYNCHEADER_in), + .PIPERX03VALID (PIPERX03VALID_in), + .PIPERX04CHARISK (PIPERX04CHARISK_in), + .PIPERX04DATA (PIPERX04DATA_in), + .PIPERX04DATAVALID (PIPERX04DATAVALID_in), + .PIPERX04ELECIDLE (PIPERX04ELECIDLE_in), + .PIPERX04EQDONE (PIPERX04EQDONE_in), + .PIPERX04EQLPADAPTDONE (PIPERX04EQLPADAPTDONE_in), + .PIPERX04EQLPLFFSSEL (PIPERX04EQLPLFFSSEL_in), + .PIPERX04EQLPNEWTXCOEFFORPRESET (PIPERX04EQLPNEWTXCOEFFORPRESET_in), + .PIPERX04PHYSTATUS (PIPERX04PHYSTATUS_in), + .PIPERX04STARTBLOCK (PIPERX04STARTBLOCK_in), + .PIPERX04STATUS (PIPERX04STATUS_in), + .PIPERX04SYNCHEADER (PIPERX04SYNCHEADER_in), + .PIPERX04VALID (PIPERX04VALID_in), + .PIPERX05CHARISK (PIPERX05CHARISK_in), + .PIPERX05DATA (PIPERX05DATA_in), + .PIPERX05DATAVALID (PIPERX05DATAVALID_in), + .PIPERX05ELECIDLE (PIPERX05ELECIDLE_in), + .PIPERX05EQDONE (PIPERX05EQDONE_in), + .PIPERX05EQLPADAPTDONE (PIPERX05EQLPADAPTDONE_in), + .PIPERX05EQLPLFFSSEL (PIPERX05EQLPLFFSSEL_in), + .PIPERX05EQLPNEWTXCOEFFORPRESET (PIPERX05EQLPNEWTXCOEFFORPRESET_in), + .PIPERX05PHYSTATUS (PIPERX05PHYSTATUS_in), + .PIPERX05STARTBLOCK (PIPERX05STARTBLOCK_in), + .PIPERX05STATUS (PIPERX05STATUS_in), + .PIPERX05SYNCHEADER (PIPERX05SYNCHEADER_in), + .PIPERX05VALID (PIPERX05VALID_in), + .PIPERX06CHARISK (PIPERX06CHARISK_in), + .PIPERX06DATA (PIPERX06DATA_in), + .PIPERX06DATAVALID (PIPERX06DATAVALID_in), + .PIPERX06ELECIDLE (PIPERX06ELECIDLE_in), + .PIPERX06EQDONE (PIPERX06EQDONE_in), + .PIPERX06EQLPADAPTDONE (PIPERX06EQLPADAPTDONE_in), + .PIPERX06EQLPLFFSSEL (PIPERX06EQLPLFFSSEL_in), + .PIPERX06EQLPNEWTXCOEFFORPRESET (PIPERX06EQLPNEWTXCOEFFORPRESET_in), + .PIPERX06PHYSTATUS (PIPERX06PHYSTATUS_in), + .PIPERX06STARTBLOCK (PIPERX06STARTBLOCK_in), + .PIPERX06STATUS (PIPERX06STATUS_in), + .PIPERX06SYNCHEADER (PIPERX06SYNCHEADER_in), + .PIPERX06VALID (PIPERX06VALID_in), + .PIPERX07CHARISK (PIPERX07CHARISK_in), + .PIPERX07DATA (PIPERX07DATA_in), + .PIPERX07DATAVALID (PIPERX07DATAVALID_in), + .PIPERX07ELECIDLE (PIPERX07ELECIDLE_in), + .PIPERX07EQDONE (PIPERX07EQDONE_in), + .PIPERX07EQLPADAPTDONE (PIPERX07EQLPADAPTDONE_in), + .PIPERX07EQLPLFFSSEL (PIPERX07EQLPLFFSSEL_in), + .PIPERX07EQLPNEWTXCOEFFORPRESET (PIPERX07EQLPNEWTXCOEFFORPRESET_in), + .PIPERX07PHYSTATUS (PIPERX07PHYSTATUS_in), + .PIPERX07STARTBLOCK (PIPERX07STARTBLOCK_in), + .PIPERX07STATUS (PIPERX07STATUS_in), + .PIPERX07SYNCHEADER (PIPERX07SYNCHEADER_in), + .PIPERX07VALID (PIPERX07VALID_in), + .PIPERX08CHARISK (PIPERX08CHARISK_in), + .PIPERX08DATA (PIPERX08DATA_in), + .PIPERX08DATAVALID (PIPERX08DATAVALID_in), + .PIPERX08ELECIDLE (PIPERX08ELECIDLE_in), + .PIPERX08EQDONE (PIPERX08EQDONE_in), + .PIPERX08EQLPADAPTDONE (PIPERX08EQLPADAPTDONE_in), + .PIPERX08EQLPLFFSSEL (PIPERX08EQLPLFFSSEL_in), + .PIPERX08EQLPNEWTXCOEFFORPRESET (PIPERX08EQLPNEWTXCOEFFORPRESET_in), + .PIPERX08PHYSTATUS (PIPERX08PHYSTATUS_in), + .PIPERX08STARTBLOCK (PIPERX08STARTBLOCK_in), + .PIPERX08STATUS (PIPERX08STATUS_in), + .PIPERX08SYNCHEADER (PIPERX08SYNCHEADER_in), + .PIPERX08VALID (PIPERX08VALID_in), + .PIPERX09CHARISK (PIPERX09CHARISK_in), + .PIPERX09DATA (PIPERX09DATA_in), + .PIPERX09DATAVALID (PIPERX09DATAVALID_in), + .PIPERX09ELECIDLE (PIPERX09ELECIDLE_in), + .PIPERX09EQDONE (PIPERX09EQDONE_in), + .PIPERX09EQLPADAPTDONE (PIPERX09EQLPADAPTDONE_in), + .PIPERX09EQLPLFFSSEL (PIPERX09EQLPLFFSSEL_in), + .PIPERX09EQLPNEWTXCOEFFORPRESET (PIPERX09EQLPNEWTXCOEFFORPRESET_in), + .PIPERX09PHYSTATUS (PIPERX09PHYSTATUS_in), + .PIPERX09STARTBLOCK (PIPERX09STARTBLOCK_in), + .PIPERX09STATUS (PIPERX09STATUS_in), + .PIPERX09SYNCHEADER (PIPERX09SYNCHEADER_in), + .PIPERX09VALID (PIPERX09VALID_in), + .PIPERX10CHARISK (PIPERX10CHARISK_in), + .PIPERX10DATA (PIPERX10DATA_in), + .PIPERX10DATAVALID (PIPERX10DATAVALID_in), + .PIPERX10ELECIDLE (PIPERX10ELECIDLE_in), + .PIPERX10EQDONE (PIPERX10EQDONE_in), + .PIPERX10EQLPADAPTDONE (PIPERX10EQLPADAPTDONE_in), + .PIPERX10EQLPLFFSSEL (PIPERX10EQLPLFFSSEL_in), + .PIPERX10EQLPNEWTXCOEFFORPRESET (PIPERX10EQLPNEWTXCOEFFORPRESET_in), + .PIPERX10PHYSTATUS (PIPERX10PHYSTATUS_in), + .PIPERX10STARTBLOCK (PIPERX10STARTBLOCK_in), + .PIPERX10STATUS (PIPERX10STATUS_in), + .PIPERX10SYNCHEADER (PIPERX10SYNCHEADER_in), + .PIPERX10VALID (PIPERX10VALID_in), + .PIPERX11CHARISK (PIPERX11CHARISK_in), + .PIPERX11DATA (PIPERX11DATA_in), + .PIPERX11DATAVALID (PIPERX11DATAVALID_in), + .PIPERX11ELECIDLE (PIPERX11ELECIDLE_in), + .PIPERX11EQDONE (PIPERX11EQDONE_in), + .PIPERX11EQLPADAPTDONE (PIPERX11EQLPADAPTDONE_in), + .PIPERX11EQLPLFFSSEL (PIPERX11EQLPLFFSSEL_in), + .PIPERX11EQLPNEWTXCOEFFORPRESET (PIPERX11EQLPNEWTXCOEFFORPRESET_in), + .PIPERX11PHYSTATUS (PIPERX11PHYSTATUS_in), + .PIPERX11STARTBLOCK (PIPERX11STARTBLOCK_in), + .PIPERX11STATUS (PIPERX11STATUS_in), + .PIPERX11SYNCHEADER (PIPERX11SYNCHEADER_in), + .PIPERX11VALID (PIPERX11VALID_in), + .PIPERX12CHARISK (PIPERX12CHARISK_in), + .PIPERX12DATA (PIPERX12DATA_in), + .PIPERX12DATAVALID (PIPERX12DATAVALID_in), + .PIPERX12ELECIDLE (PIPERX12ELECIDLE_in), + .PIPERX12EQDONE (PIPERX12EQDONE_in), + .PIPERX12EQLPADAPTDONE (PIPERX12EQLPADAPTDONE_in), + .PIPERX12EQLPLFFSSEL (PIPERX12EQLPLFFSSEL_in), + .PIPERX12EQLPNEWTXCOEFFORPRESET (PIPERX12EQLPNEWTXCOEFFORPRESET_in), + .PIPERX12PHYSTATUS (PIPERX12PHYSTATUS_in), + .PIPERX12STARTBLOCK (PIPERX12STARTBLOCK_in), + .PIPERX12STATUS (PIPERX12STATUS_in), + .PIPERX12SYNCHEADER (PIPERX12SYNCHEADER_in), + .PIPERX12VALID (PIPERX12VALID_in), + .PIPERX13CHARISK (PIPERX13CHARISK_in), + .PIPERX13DATA (PIPERX13DATA_in), + .PIPERX13DATAVALID (PIPERX13DATAVALID_in), + .PIPERX13ELECIDLE (PIPERX13ELECIDLE_in), + .PIPERX13EQDONE (PIPERX13EQDONE_in), + .PIPERX13EQLPADAPTDONE (PIPERX13EQLPADAPTDONE_in), + .PIPERX13EQLPLFFSSEL (PIPERX13EQLPLFFSSEL_in), + .PIPERX13EQLPNEWTXCOEFFORPRESET (PIPERX13EQLPNEWTXCOEFFORPRESET_in), + .PIPERX13PHYSTATUS (PIPERX13PHYSTATUS_in), + .PIPERX13STARTBLOCK (PIPERX13STARTBLOCK_in), + .PIPERX13STATUS (PIPERX13STATUS_in), + .PIPERX13SYNCHEADER (PIPERX13SYNCHEADER_in), + .PIPERX13VALID (PIPERX13VALID_in), + .PIPERX14CHARISK (PIPERX14CHARISK_in), + .PIPERX14DATA (PIPERX14DATA_in), + .PIPERX14DATAVALID (PIPERX14DATAVALID_in), + .PIPERX14ELECIDLE (PIPERX14ELECIDLE_in), + .PIPERX14EQDONE (PIPERX14EQDONE_in), + .PIPERX14EQLPADAPTDONE (PIPERX14EQLPADAPTDONE_in), + .PIPERX14EQLPLFFSSEL (PIPERX14EQLPLFFSSEL_in), + .PIPERX14EQLPNEWTXCOEFFORPRESET (PIPERX14EQLPNEWTXCOEFFORPRESET_in), + .PIPERX14PHYSTATUS (PIPERX14PHYSTATUS_in), + .PIPERX14STARTBLOCK (PIPERX14STARTBLOCK_in), + .PIPERX14STATUS (PIPERX14STATUS_in), + .PIPERX14SYNCHEADER (PIPERX14SYNCHEADER_in), + .PIPERX14VALID (PIPERX14VALID_in), + .PIPERX15CHARISK (PIPERX15CHARISK_in), + .PIPERX15DATA (PIPERX15DATA_in), + .PIPERX15DATAVALID (PIPERX15DATAVALID_in), + .PIPERX15ELECIDLE (PIPERX15ELECIDLE_in), + .PIPERX15EQDONE (PIPERX15EQDONE_in), + .PIPERX15EQLPADAPTDONE (PIPERX15EQLPADAPTDONE_in), + .PIPERX15EQLPLFFSSEL (PIPERX15EQLPLFFSSEL_in), + .PIPERX15EQLPNEWTXCOEFFORPRESET (PIPERX15EQLPNEWTXCOEFFORPRESET_in), + .PIPERX15PHYSTATUS (PIPERX15PHYSTATUS_in), + .PIPERX15STARTBLOCK (PIPERX15STARTBLOCK_in), + .PIPERX15STATUS (PIPERX15STATUS_in), + .PIPERX15SYNCHEADER (PIPERX15SYNCHEADER_in), + .PIPERX15VALID (PIPERX15VALID_in), + .PIPETX00EQCOEFF (PIPETX00EQCOEFF_in), + .PIPETX00EQDONE (PIPETX00EQDONE_in), + .PIPETX01EQCOEFF (PIPETX01EQCOEFF_in), + .PIPETX01EQDONE (PIPETX01EQDONE_in), + .PIPETX02EQCOEFF (PIPETX02EQCOEFF_in), + .PIPETX02EQDONE (PIPETX02EQDONE_in), + .PIPETX03EQCOEFF (PIPETX03EQCOEFF_in), + .PIPETX03EQDONE (PIPETX03EQDONE_in), + .PIPETX04EQCOEFF (PIPETX04EQCOEFF_in), + .PIPETX04EQDONE (PIPETX04EQDONE_in), + .PIPETX05EQCOEFF (PIPETX05EQCOEFF_in), + .PIPETX05EQDONE (PIPETX05EQDONE_in), + .PIPETX06EQCOEFF (PIPETX06EQCOEFF_in), + .PIPETX06EQDONE (PIPETX06EQDONE_in), + .PIPETX07EQCOEFF (PIPETX07EQCOEFF_in), + .PIPETX07EQDONE (PIPETX07EQDONE_in), + .PIPETX08EQCOEFF (PIPETX08EQCOEFF_in), + .PIPETX08EQDONE (PIPETX08EQDONE_in), + .PIPETX09EQCOEFF (PIPETX09EQCOEFF_in), + .PIPETX09EQDONE (PIPETX09EQDONE_in), + .PIPETX10EQCOEFF (PIPETX10EQCOEFF_in), + .PIPETX10EQDONE (PIPETX10EQDONE_in), + .PIPETX11EQCOEFF (PIPETX11EQCOEFF_in), + .PIPETX11EQDONE (PIPETX11EQDONE_in), + .PIPETX12EQCOEFF (PIPETX12EQCOEFF_in), + .PIPETX12EQDONE (PIPETX12EQDONE_in), + .PIPETX13EQCOEFF (PIPETX13EQCOEFF_in), + .PIPETX13EQDONE (PIPETX13EQDONE_in), + .PIPETX14EQCOEFF (PIPETX14EQCOEFF_in), + .PIPETX14EQDONE (PIPETX14EQDONE_in), + .PIPETX15EQCOEFF (PIPETX15EQCOEFF_in), + .PIPETX15EQDONE (PIPETX15EQDONE_in), + .PLEQRESETEIEOSCOUNT (PLEQRESETEIEOSCOUNT_in), + .PLGEN2UPSTREAMPREFERDEEMPH (PLGEN2UPSTREAMPREFERDEEMPH_in), + .PLGEN34REDOEQSPEED (PLGEN34REDOEQSPEED_in), + .PLGEN34REDOEQUALIZATION (PLGEN34REDOEQUALIZATION_in), + .PMVDIVIDE (PMVDIVIDE_in), + .PMVENABLEN (PMVENABLEN_in), + .PMVSELECT (PMVSELECT_in), + .RESETN (RESETN_in), + .SAXISCCIXTXTDATA (SAXISCCIXTXTDATA_in), + .SAXISCCIXTXTUSER (SAXISCCIXTXTUSER_in), + .SAXISCCIXTXTVALID (SAXISCCIXTXTVALID_in), + .SAXISCCTDATA (SAXISCCTDATA_in), + .SAXISCCTKEEP (SAXISCCTKEEP_in), + .SAXISCCTLAST (SAXISCCTLAST_in), + .SAXISCCTUSER (SAXISCCTUSER_in), + .SAXISCCTVALID (SAXISCCTVALID_in), + .SAXISRQTDATA (SAXISRQTDATA_in), + .SAXISRQTKEEP (SAXISRQTKEEP_in), + .SAXISRQTLAST (SAXISRQTLAST_in), + .SAXISRQTUSER (SAXISRQTUSER_in), + .SAXISRQTVALID (SAXISRQTVALID_in), + .SCANENABLEN (SCANENABLEN_in), + .SCANIN (SCANIN_in), + .SCANMODEN (SCANMODEN_in), + .USERCLK (USERCLK_in), + .USERCLK2 (USERCLK2_in), + .USERCLKEN (USERCLKEN_in), + .USERSPAREIN (USERSPAREIN_in), + .GSR (glblGSR) +); + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (CORECLK => AXIUSEROUT[0]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[1]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[2]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[3]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[4]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[5]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[6]) = (100:100:100, 100:100:100); + (CORECLK => AXIUSEROUT[7]) = (100:100:100, 100:100:100); + (CORECLK => CCIXTXCREDIT) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGBUSNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGCURRENTSPEED[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGCURRENTSPEED[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGERRCOROUT) = (100:100:100, 100:100:100); + (CORECLK => CFGERRFATALOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGERRNONFATALOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTFUNCTIONNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREADRECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTREGISTERNUMBER[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGEXTWRITERECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCCPLH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCNPH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPD[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFCPH[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFLRINPROCESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONPOWERSTATE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGFUNCTIONSTATUS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGHOTRESETOUT) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIFAIL) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMASKUPDATE) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIMMENABLE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSISENT) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXMASK[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTMSIXVECPENDINGSTATUS) = (100:100:100, 100:100:100); + (CORECLK => CFGINTERRUPTSENT) = (100:100:100, 100:100:100); + (CORECLK => CFGLINKPOWERSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLINKPOWERSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERROROUT[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGLOCALERRORVALID) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGLTSSMSTATE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXPAYLOAD[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXPAYLOAD[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMAXREADREQ[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGMGMTREADWRITEDONE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVED) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGRECEIVEDTYPE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSGTRANSMITDONE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMADDRESS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMREADENABLE) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGMSIXRAMWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGNEGOTIATEDWIDTH[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKDOWN) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGPHYLINKSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGPLSTATUSCHANGE) = (100:100:100, 100:100:100); + (CORECLK => CFGPOWERSTATECHANGEINTERRUPT) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGRCBSTATUS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGRXPMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGRXPMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMADDRESS[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMREADENABLE) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEBYTEENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHRAMWRITEDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHREQUESTERENABLE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[10]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[11]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[2]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[3]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[4]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[5]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[6]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[7]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[8]) = (100:100:100, 100:100:100); + (CORECLK => CFGTPHSTMODE[9]) = (100:100:100, 100:100:100); + (CORECLK => CFGTXPMSTATE[0]) = (100:100:100, 100:100:100); + (CORECLK => CFGTXPMSTATE[1]) = (100:100:100, 100:100:100); + (CORECLK => CFGVC1ENABLE) = (100:100:100, 100:100:100); + (CORECLK => CFGVC1NEGOTIATIONPENDING) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPDESIGNSWITCH) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPEOS) = (100:100:100, 100:100:100); + (CORECLK => CONFMCAPINUSEBYPCIE) = (100:100:100, 100:100:100); + (CORECLK => CONFREQREADY) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPRDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => CONFRESPVALID) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGCCIXOUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL0OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGCTRL1OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[100]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[101]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[102]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[103]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[104]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[105]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[106]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[107]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[108]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[109]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[110]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[111]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[112]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[113]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[114]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[115]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[116]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[117]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[118]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[119]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[120]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[121]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[122]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[123]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[124]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[125]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[126]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[127]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[128]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[129]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[130]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[131]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[132]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[133]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[134]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[135]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[136]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[137]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[138]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[139]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[140]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[141]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[142]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[143]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[144]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[145]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[146]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[147]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[148]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[149]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[150]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[151]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[152]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[153]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[154]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[155]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[156]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[157]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[158]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[159]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[160]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[161]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[162]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[163]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[164]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[165]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[166]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[167]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[168]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[169]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[170]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[171]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[172]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[173]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[174]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[175]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[176]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[177]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[178]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[179]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[180]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[181]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[182]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[183]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[184]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[185]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[186]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[187]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[188]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[189]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[190]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[191]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[192]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[193]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[194]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[195]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[196]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[197]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[198]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[199]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[200]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[201]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[202]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[203]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[204]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[205]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[206]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[207]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[208]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[209]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[210]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[211]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[212]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[213]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[214]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[215]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[216]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[217]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[218]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[219]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[220]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[221]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[222]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[223]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[224]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[225]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[226]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[227]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[228]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[229]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[230]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[231]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[232]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[233]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[234]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[235]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[236]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[237]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[238]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[239]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[240]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[241]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[242]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[243]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[244]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[245]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[246]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[247]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[248]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[249]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[250]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[251]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[252]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[253]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[254]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[255]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[32]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[33]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[34]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[35]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[36]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[37]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[38]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[39]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[40]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[41]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[42]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[43]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[44]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[45]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[46]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[47]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[48]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[49]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[50]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[51]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[52]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[53]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[54]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[55]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[56]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[57]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[58]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[59]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[60]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[61]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[62]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[63]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[64]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[65]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[66]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[67]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[68]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[69]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[70]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[71]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[72]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[73]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[74]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[75]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[76]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[77]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[78]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[79]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[80]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[81]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[82]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[83]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[84]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[85]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[86]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[87]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[88]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[89]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[90]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[91]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[92]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[93]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[94]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[95]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[96]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[97]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[98]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[99]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA0OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[0]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[100]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[101]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[102]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[103]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[104]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[105]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[106]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[107]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[108]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[109]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[10]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[110]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[111]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[112]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[113]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[114]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[115]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[116]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[117]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[118]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[119]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[11]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[120]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[121]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[122]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[123]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[124]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[125]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[126]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[127]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[128]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[129]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[12]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[130]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[131]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[132]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[133]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[134]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[135]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[136]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[137]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[138]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[139]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[13]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[140]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[141]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[142]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[143]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[144]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[145]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[146]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[147]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[148]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[149]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[14]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[150]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[151]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[152]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[153]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[154]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[155]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[156]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[157]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[158]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[159]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[15]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[160]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[161]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[162]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[163]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[164]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[165]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[166]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[167]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[168]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[169]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[16]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[170]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[171]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[172]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[173]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[174]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[175]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[176]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[177]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[178]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[179]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[17]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[180]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[181]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[182]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[183]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[184]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[185]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[186]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[187]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[188]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[189]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[18]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[190]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[191]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[192]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[193]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[194]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[195]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[196]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[197]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[198]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[199]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[19]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[1]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[200]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[201]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[202]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[203]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[204]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[205]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[206]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[207]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[208]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[209]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[20]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[210]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[211]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[212]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[213]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[214]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[215]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[216]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[217]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[218]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[219]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[21]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[220]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[221]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[222]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[223]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[224]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[225]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[226]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[227]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[228]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[229]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[22]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[230]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[231]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[232]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[233]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[234]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[235]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[236]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[237]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[238]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[239]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[23]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[240]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[241]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[242]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[243]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[244]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[245]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[246]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[247]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[248]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[249]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[24]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[250]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[251]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[252]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[253]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[254]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[255]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[25]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[26]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[27]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[28]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[29]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[2]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[30]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[31]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[32]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[33]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[34]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[35]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[36]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[37]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[38]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[39]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[3]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[40]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[41]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[42]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[43]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[44]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[45]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[46]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[47]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[48]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[49]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[4]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[50]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[51]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[52]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[53]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[54]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[55]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[56]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[57]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[58]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[59]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[5]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[60]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[61]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[62]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[63]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[64]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[65]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[66]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[67]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[68]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[69]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[6]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[70]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[71]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[72]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[73]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[74]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[75]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[76]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[77]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[78]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[79]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[7]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[80]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[81]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[82]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[83]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[84]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[85]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[86]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[87]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[88]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[89]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[8]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[90]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[91]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[92]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[93]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[94]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[95]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[96]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[97]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[98]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[99]) = (100:100:100, 100:100:100); + (CORECLK => DBGDATA1OUT[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTUSER[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCCIXRXTVALID) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[100]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[101]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[102]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[103]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[104]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[105]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[106]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[107]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[108]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[109]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[110]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[111]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[112]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[113]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[114]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[115]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[116]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[117]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[118]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[119]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[120]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[121]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[122]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[123]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[124]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[125]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[126]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[127]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[128]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[129]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[130]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[131]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[132]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[133]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[134]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[135]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[136]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[137]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[138]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[139]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[140]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[141]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[142]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[143]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[144]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[145]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[146]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[147]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[148]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[149]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[150]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[151]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[152]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[153]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[154]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[155]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[156]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[157]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[158]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[159]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[160]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[161]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[162]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[163]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[164]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[165]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[166]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[167]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[168]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[169]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[170]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[171]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[172]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[173]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[174]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[175]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[176]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[177]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[178]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[179]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[180]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[181]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[182]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[183]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[184]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[185]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[186]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[187]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[188]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[189]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[190]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[191]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[192]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[193]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[194]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[195]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[196]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[197]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[198]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[199]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[200]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[201]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[202]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[203]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[204]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[205]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[206]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[207]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[208]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[209]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[210]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[211]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[212]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[213]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[214]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[215]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[216]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[217]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[218]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[219]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[220]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[221]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[222]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[223]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[224]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[225]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[226]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[227]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[228]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[229]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[230]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[231]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[232]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[233]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[234]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[235]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[236]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[237]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[238]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[239]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[240]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[241]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[242]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[243]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[244]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[245]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[246]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[247]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[248]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[249]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[250]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[251]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[252]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[253]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[254]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[255]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[88]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[89]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[90]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[91]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[92]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[93]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[94]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[95]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[96]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[97]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[98]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[99]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTKEEP[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTLAST) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTUSER[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISCQTVALID) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[100]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[101]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[102]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[103]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[104]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[105]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[106]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[107]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[108]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[109]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[110]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[111]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[112]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[113]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[114]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[115]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[116]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[117]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[118]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[119]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[120]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[121]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[122]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[123]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[124]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[125]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[126]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[127]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[128]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[129]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[130]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[131]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[132]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[133]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[134]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[135]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[136]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[137]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[138]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[139]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[140]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[141]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[142]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[143]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[144]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[145]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[146]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[147]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[148]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[149]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[150]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[151]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[152]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[153]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[154]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[155]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[156]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[157]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[158]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[159]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[160]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[161]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[162]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[163]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[164]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[165]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[166]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[167]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[168]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[169]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[170]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[171]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[172]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[173]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[174]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[175]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[176]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[177]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[178]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[179]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[180]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[181]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[182]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[183]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[184]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[185]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[186]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[187]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[188]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[189]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[190]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[191]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[192]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[193]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[194]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[195]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[196]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[197]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[198]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[199]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[200]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[201]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[202]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[203]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[204]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[205]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[206]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[207]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[208]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[209]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[210]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[211]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[212]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[213]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[214]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[215]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[216]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[217]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[218]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[219]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[220]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[221]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[222]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[223]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[224]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[225]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[226]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[227]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[228]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[229]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[230]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[231]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[232]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[233]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[234]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[235]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[236]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[237]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[238]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[239]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[240]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[241]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[242]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[243]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[244]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[245]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[246]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[247]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[248]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[249]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[250]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[251]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[252]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[253]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[254]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[255]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[75]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[76]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[77]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[78]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[79]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[80]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[81]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[82]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[83]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[84]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[85]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[86]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[87]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[88]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[89]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[90]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[91]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[92]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[93]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[94]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[95]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[96]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[97]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[98]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[99]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTDATA[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTKEEP[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTLAST) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[0]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[10]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[11]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[12]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[13]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[14]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[15]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[16]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[17]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[18]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[19]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[1]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[20]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[21]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[22]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[23]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[24]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[25]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[26]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[27]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[28]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[29]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[2]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[30]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[31]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[32]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[33]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[34]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[35]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[36]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[37]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[38]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[39]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[3]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[40]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[41]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[42]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[43]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[44]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[45]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[46]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[47]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[48]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[49]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[4]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[50]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[51]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[52]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[53]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[54]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[55]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[56]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[57]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[58]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[59]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[5]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[60]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[61]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[62]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[63]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[64]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[65]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[66]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[67]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[68]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[69]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[6]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[70]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[71]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[72]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[73]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[74]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[7]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[8]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTUSER[9]) = (100:100:100, 100:100:100); + (CORECLK => MAXISRCTVALID) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIECQNPREQCOUNT[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM0[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUM1[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUMVLD0) = (100:100:100, 100:100:100); + (CORECLK => PCIERQSEQNUMVLD1) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[6]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG0[7]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[4]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[5]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[6]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAG1[7]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGAV[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGVLD0) = (100:100:100, 100:100:100); + (CORECLK => PCIERQTAGVLD1) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPDAV[3]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[0]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[1]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[2]) = (100:100:100, 100:100:100); + (CORECLK => PCIETFCNPHAV[3]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[0]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[1]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[2]) = (100:100:100, 100:100:100); + (CORECLK => SAXISCCTREADY[3]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[0]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[1]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[2]) = (100:100:100, 100:100:100); + (CORECLK => SAXISRQTREADY[3]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[0]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[10]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[11]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[12]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[13]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[14]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[15]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[16]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[17]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[18]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[19]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[1]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[20]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[21]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[22]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[23]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[2]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[3]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[4]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[5]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[6]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[7]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[8]) = (100:100:100, 100:100:100); + (CORECLK => USERSPAREOUT[9]) = (100:100:100, 100:100:100); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMREADENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM0 => MIREPLAYRAMWRITEENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMREADENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM1 => MIREPLAYRAMWRITEENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADENABLE0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMREADENABLE0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEENABLE0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM0 => MIRXCOMPLETIONRAMWRITEENABLE0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADENABLE1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMREADENABLE1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEENABLE1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXCOMPLETIONRAM1 => MIRXCOMPLETIONRAMWRITEENABLE1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMREADENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEADDRESS0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEDATA0[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM0 => MIRXPOSTEDREQUESTRAMWRITEENABLE0) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => CFGTPHRAMWRITEDATA[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMREADENABLE1) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEADDRESS1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[0]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[100]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[101]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[102]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[103]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[104]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[105]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[106]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[107]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[108]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[109]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[10]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[110]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[111]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[112]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[113]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[114]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[115]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[116]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[117]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[118]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[119]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[11]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[120]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[121]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[122]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[123]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[124]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[125]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[126]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[127]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[128]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[129]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[12]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[130]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[131]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[132]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[133]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[134]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[135]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[136]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[137]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[138]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[139]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[13]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[140]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[141]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[142]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[143]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[14]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[15]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[16]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[17]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[18]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[19]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[1]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[20]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[21]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[22]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[23]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[24]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[25]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[26]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[27]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[28]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[29]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[2]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[30]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[31]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[32]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[33]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[34]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[35]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[36]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[37]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[38]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[39]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[3]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[40]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[41]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[42]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[43]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[44]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[45]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[46]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[47]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[48]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[49]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[4]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[50]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[51]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[52]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[53]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[54]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[55]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[56]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[57]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[58]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[59]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[5]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[60]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[61]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[62]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[63]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[64]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[65]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[66]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[67]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[68]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[69]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[6]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[70]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[71]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[72]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[73]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[74]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[75]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[76]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[77]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[78]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[79]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[7]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[80]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[81]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[82]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[83]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[84]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[85]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[86]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[87]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[88]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[89]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[8]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[90]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[91]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[92]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[93]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[94]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[95]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[96]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[97]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[98]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[99]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEDATA1[9]) = (0:0:0, 0:0:0); + (CORECLKMIRXPOSTEDREQUESTRAM1 => MIRXPOSTEDREQUESTRAMWRITEENABLE1) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100); + (DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100); + (DRPCLK => DRPRDY) = (100:100:100, 100:100:100); + (PIPECLK => CONFRESPRDATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => CONFRESPRDATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => CONFRESPRDATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX00POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX01POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX02POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX03POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX04POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX05POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX06POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX07POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX08POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX09POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX10POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX11POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX12POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX13POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX14POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERX15POLARITY) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPLFFS[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPERXEQLPTXPRESET[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX00SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX01SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX02SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX03SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX04SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX05SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX06SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX07SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX08SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX09SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX10SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX11SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX12SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX13SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX14SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15CHARISK[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15CHARISK[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15COMPLIANCE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATAVALID) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[10]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[11]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[12]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[13]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[14]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[15]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[16]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[17]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[18]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[19]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[20]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[21]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[22]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[23]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[24]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[25]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[26]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[27]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[28]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[29]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[30]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[31]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[6]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[7]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[8]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15DATA[9]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15ELECIDLE) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQCONTROL[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQCONTROL[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[2]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[3]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[4]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15EQDEEMPH[5]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15POWERDOWN[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15POWERDOWN[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15STARTBLOCK) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15SYNCHEADER[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETX15SYNCHEADER[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXDEEMPH) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRATE[0]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRATE[1]) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRCVRDET) = (100:100:100, 100:100:100); + (PIPECLK => PIPETXRESET) = (100:100:100, 100:100:100); + (PIPECLK => PLEQINPROGRESS) = (100:100:100, 100:100:100); + (PIPECLK => PLEQPHASE[0]) = (100:100:100, 100:100:100); + (PIPECLK => PLEQPHASE[1]) = (100:100:100, 100:100:100); + (PIPECLK => PLGEN34EQMISMATCH) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $setuphold (posedge CORECLK, negedge AXIUSERIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[0]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[1]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[2]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[3]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[4]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[5]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[6]); + $setuphold (posedge CORECLK, negedge AXIUSERIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[7]); + $setuphold (posedge CORECLK, negedge CCIXOPTIMIZEDTLPTXANDRXENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXOPTIMIZEDTLPTXANDRXENABLE_delay); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDED0, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDED0_delay); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDED1, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDED1_delay); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[0]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[1]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[2]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[3]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[4]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[5]); + $setuphold (posedge CORECLK, negedge CCIXRXTLPFORWARDEDLENGTH1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDEVIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[10]); + $setuphold (posedge CORECLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[11]); + $setuphold (posedge CORECLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[12]); + $setuphold (posedge CORECLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[13]); + $setuphold (posedge CORECLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[14]); + $setuphold (posedge CORECLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[15]); + $setuphold (posedge CORECLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[16]); + $setuphold (posedge CORECLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[17]); + $setuphold (posedge CORECLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[18]); + $setuphold (posedge CORECLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[19]); + $setuphold (posedge CORECLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[20]); + $setuphold (posedge CORECLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[21]); + $setuphold (posedge CORECLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[22]); + $setuphold (posedge CORECLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[23]); + $setuphold (posedge CORECLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[24]); + $setuphold (posedge CORECLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[25]); + $setuphold (posedge CORECLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[26]); + $setuphold (posedge CORECLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[27]); + $setuphold (posedge CORECLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[28]); + $setuphold (posedge CORECLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[29]); + $setuphold (posedge CORECLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[30]); + $setuphold (posedge CORECLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[31]); + $setuphold (posedge CORECLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[32]); + $setuphold (posedge CORECLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[33]); + $setuphold (posedge CORECLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[34]); + $setuphold (posedge CORECLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[35]); + $setuphold (posedge CORECLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[36]); + $setuphold (posedge CORECLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[37]); + $setuphold (posedge CORECLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[38]); + $setuphold (posedge CORECLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[39]); + $setuphold (posedge CORECLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[40]); + $setuphold (posedge CORECLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[41]); + $setuphold (posedge CORECLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[42]); + $setuphold (posedge CORECLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[43]); + $setuphold (posedge CORECLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[44]); + $setuphold (posedge CORECLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[45]); + $setuphold (posedge CORECLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[46]); + $setuphold (posedge CORECLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[47]); + $setuphold (posedge CORECLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[48]); + $setuphold (posedge CORECLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[49]); + $setuphold (posedge CORECLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[50]); + $setuphold (posedge CORECLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[51]); + $setuphold (posedge CORECLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[52]); + $setuphold (posedge CORECLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[53]); + $setuphold (posedge CORECLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[54]); + $setuphold (posedge CORECLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[55]); + $setuphold (posedge CORECLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[56]); + $setuphold (posedge CORECLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[57]); + $setuphold (posedge CORECLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[58]); + $setuphold (posedge CORECLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[59]); + $setuphold (posedge CORECLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[60]); + $setuphold (posedge CORECLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[61]); + $setuphold (posedge CORECLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[62]); + $setuphold (posedge CORECLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[63]); + $setuphold (posedge CORECLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[7]); + $setuphold (posedge CORECLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[8]); + $setuphold (posedge CORECLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[9]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRCORIN_delay); + $setuphold (posedge CORECLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge CORECLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge CORECLK, negedge CFGFCVCSEL, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCVCSEL_delay); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[3]); + $setuphold (posedge CORECLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXVECPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTMSIXVECPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[2]); + $setuphold (posedge CORECLK, negedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[3]); + $setuphold (posedge CORECLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTDEBUGACCESS, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTDEBUGACCESS_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGMSIXRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGPMASPML1ENTRYREJECT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPML1ENTRYREJECT_delay); + $setuphold (posedge CORECLK, negedge CFGPMASPMTXL0SENTRYDISABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPMTXL0SENTRYDISABLE_delay); + $setuphold (posedge CORECLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge CORECLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGREVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[9]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge CORECLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CFGTPHRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge CORECLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge CORECLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge CORECLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge CORECLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge CORECLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge CORECLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge CORECLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge CORECLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge CORECLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge CORECLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge CORECLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge CORECLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge CORECLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge CORECLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge CORECLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge CORECLK, negedge CFGVFFLRDONE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRDONE_delay); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[2]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[3]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[4]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[5]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[6]); + $setuphold (posedge CORECLK, negedge CFGVFFLRFUNCNUM[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[7]); + $setuphold (posedge CORECLK, negedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge CORECLK, negedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge CORECLK, negedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge CORECLK, negedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge CORECLK, negedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge CORECLK, negedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge CORECLK, negedge CONFREQVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQVALID_delay); + $setuphold (posedge CORECLK, negedge DBGSEL0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[0]); + $setuphold (posedge CORECLK, negedge DBGSEL0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[1]); + $setuphold (posedge CORECLK, negedge DBGSEL0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[2]); + $setuphold (posedge CORECLK, negedge DBGSEL0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[3]); + $setuphold (posedge CORECLK, negedge DBGSEL0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[4]); + $setuphold (posedge CORECLK, negedge DBGSEL0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[5]); + $setuphold (posedge CORECLK, negedge DBGSEL1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[0]); + $setuphold (posedge CORECLK, negedge DBGSEL1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[1]); + $setuphold (posedge CORECLK, negedge DBGSEL1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[2]); + $setuphold (posedge CORECLK, negedge DBGSEL1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[3]); + $setuphold (posedge CORECLK, negedge DBGSEL1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[4]); + $setuphold (posedge CORECLK, negedge DBGSEL1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge CORECLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge CORECLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMERRUNCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXCOMPLETIONRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, negedge MIRXPOSTEDREQUESTRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[2]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[3]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[4]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[5]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[6]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[7]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[2]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[3]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[4]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[5]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[6]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVEREDTAG1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[7]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVERED[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECOMPLDELIVERED[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[1]); + $setuphold (posedge CORECLK, negedge PCIECQNPREQ[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPREQ_delay[0]); + $setuphold (posedge CORECLK, negedge PCIECQNPUSERCREDITRCVD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPUSERCREDITRCVD_delay); + $setuphold (posedge CORECLK, negedge PCIECQPIPELINEEMPTY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQPIPELINEEMPTY_delay); + $setuphold (posedge CORECLK, negedge PCIEPOSTEDREQDELIVERED, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIEPOSTEDREQDELIVERED_delay); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[100]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[101]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[102]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[103]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[104]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[105]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[106]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[107]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[108]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[109]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[110]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[111]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[112]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[113]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[114]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[115]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[116]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[117]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[118]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[119]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[120]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[121]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[122]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[123]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[124]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[125]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[126]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[127]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[128]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[129]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[130]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[131]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[132]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[133]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[134]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[135]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[136]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[137]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[138]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[139]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[140]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[141]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[142]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[143]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[144]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[145]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[146]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[147]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[148]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[149]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[150]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[151]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[152]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[153]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[154]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[155]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[156]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[157]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[158]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[159]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[160]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[161]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[162]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[163]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[164]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[165]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[166]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[167]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[168]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[169]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[170]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[171]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[172]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[173]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[174]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[175]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[176]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[177]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[178]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[179]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[180]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[181]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[182]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[183]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[184]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[185]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[186]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[187]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[188]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[189]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[190]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[191]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[192]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[193]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[194]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[195]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[196]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[197]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[198]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[199]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[200]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[201]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[202]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[203]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[204]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[205]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[206]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[207]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[208]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[209]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[210]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[211]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[212]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[213]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[214]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[215]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[216]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[217]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[218]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[219]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[220]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[221]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[222]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[223]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[224]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[225]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[226]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[227]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[228]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[229]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[230]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[231]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[232]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[233]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[234]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[235]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[236]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[237]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[238]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[239]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[240]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[241]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[242]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[243]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[244]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[245]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[246]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[247]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[248]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[249]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[250]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[251]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[252]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[253]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[254]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[255]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[62]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[63]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[64]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[65]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[66]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[67]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[68]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[69]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[70]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[71]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[72]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[73]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[74]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[75]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[76]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[77]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[78]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[79]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[80]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[81]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[82]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[83]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[84]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[85]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[86]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[87]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[88]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[89]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[90]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[91]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[92]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[93]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[94]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[95]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[96]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[97]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[98]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[99]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCIXTXTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTVALID_delay); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge CORECLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge CORECLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[60]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[61]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge CORECLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge CORECLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTVALID_delay); + $setuphold (posedge CORECLK, negedge USERCLKEN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERCLKEN_delay); + $setuphold (posedge CORECLK, negedge USERSPAREIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[0]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[10]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[11]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[12]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[13]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[14]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[15]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[16]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[17]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[18]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[19]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[1]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[20]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[21]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[22]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[23]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[24]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[25]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[26]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[27]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[28]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[29]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[2]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[30]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[31]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[3]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[4]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[5]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[6]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[7]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[8]); + $setuphold (posedge CORECLK, negedge USERSPAREIN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[9]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[0]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[1]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[2]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[3]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[4]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[5]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[6]); + $setuphold (posedge CORECLK, posedge AXIUSERIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, AXIUSERIN_delay[7]); + $setuphold (posedge CORECLK, posedge CCIXOPTIMIZEDTLPTXANDRXENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXOPTIMIZEDTLPTXANDRXENABLE_delay); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDED0, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDED0_delay); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDED1, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDED1_delay); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[0]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[1]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[2]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[3]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[4]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH0_delay[5]); + $setuphold (posedge CORECLK, posedge CCIXRXTLPFORWARDEDLENGTH1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CCIXRXTLPFORWARDEDLENGTH1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF0_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF1_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF2_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDEVIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDEVIDPF3_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[10]); + $setuphold (posedge CORECLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[11]); + $setuphold (posedge CORECLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[12]); + $setuphold (posedge CORECLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[13]); + $setuphold (posedge CORECLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[14]); + $setuphold (posedge CORECLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[15]); + $setuphold (posedge CORECLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[16]); + $setuphold (posedge CORECLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[17]); + $setuphold (posedge CORECLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[18]); + $setuphold (posedge CORECLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[19]); + $setuphold (posedge CORECLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[20]); + $setuphold (posedge CORECLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[21]); + $setuphold (posedge CORECLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[22]); + $setuphold (posedge CORECLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[23]); + $setuphold (posedge CORECLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[24]); + $setuphold (posedge CORECLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[25]); + $setuphold (posedge CORECLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[26]); + $setuphold (posedge CORECLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[27]); + $setuphold (posedge CORECLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[28]); + $setuphold (posedge CORECLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[29]); + $setuphold (posedge CORECLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[30]); + $setuphold (posedge CORECLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[31]); + $setuphold (posedge CORECLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[32]); + $setuphold (posedge CORECLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[33]); + $setuphold (posedge CORECLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[34]); + $setuphold (posedge CORECLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[35]); + $setuphold (posedge CORECLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[36]); + $setuphold (posedge CORECLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[37]); + $setuphold (posedge CORECLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[38]); + $setuphold (posedge CORECLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[39]); + $setuphold (posedge CORECLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[40]); + $setuphold (posedge CORECLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[41]); + $setuphold (posedge CORECLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[42]); + $setuphold (posedge CORECLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[43]); + $setuphold (posedge CORECLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[44]); + $setuphold (posedge CORECLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[45]); + $setuphold (posedge CORECLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[46]); + $setuphold (posedge CORECLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[47]); + $setuphold (posedge CORECLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[48]); + $setuphold (posedge CORECLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[49]); + $setuphold (posedge CORECLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[50]); + $setuphold (posedge CORECLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[51]); + $setuphold (posedge CORECLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[52]); + $setuphold (posedge CORECLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[53]); + $setuphold (posedge CORECLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[54]); + $setuphold (posedge CORECLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[55]); + $setuphold (posedge CORECLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[56]); + $setuphold (posedge CORECLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[57]); + $setuphold (posedge CORECLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[58]); + $setuphold (posedge CORECLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[59]); + $setuphold (posedge CORECLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[60]); + $setuphold (posedge CORECLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[61]); + $setuphold (posedge CORECLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[62]); + $setuphold (posedge CORECLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[63]); + $setuphold (posedge CORECLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[7]); + $setuphold (posedge CORECLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[8]); + $setuphold (posedge CORECLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSN_delay[9]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRCORIN_delay); + $setuphold (posedge CORECLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge CORECLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge CORECLK, posedge CFGFCVCSEL, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFCVCSEL_delay); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGFLRDONE_delay[3]); + $setuphold (posedge CORECLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXVECPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTMSIXVECPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTMSIXVECPENDING_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[2]); + $setuphold (posedge CORECLK, posedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGINTERRUPTPENDING_delay[3]); + $setuphold (posedge CORECLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTDEBUGACCESS, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTDEBUGACCESS_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTFUNCTIONNUMBER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTFUNCTIONNUMBER_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGMSIXRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGMSIXRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGPMASPML1ENTRYREJECT, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPML1ENTRYREJECT_delay); + $setuphold (posedge CORECLK, posedge CFGPMASPMTXL0SENTRYDISABLE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPMASPMTXL0SENTRYDISABLE_delay); + $setuphold (posedge CORECLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge CORECLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGREVIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGREVIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF0_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF1_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF2[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF2_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSIDPF3[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSIDPF3_delay[9]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge CORECLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CFGTPHRAMREADDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGTPHRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge CORECLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge CORECLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge CORECLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge CORECLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge CORECLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge CORECLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge CORECLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge CORECLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge CORECLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge CORECLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge CORECLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge CORECLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge CORECLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge CORECLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge CORECLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge CORECLK, posedge CFGVFFLRDONE, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRDONE_delay); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[2]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[3]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[4]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[5]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[6]); + $setuphold (posedge CORECLK, posedge CFGVFFLRFUNCNUM[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CFGVFFLRFUNCNUM_delay[7]); + $setuphold (posedge CORECLK, posedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge CORECLK, posedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge CORECLK, posedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge CORECLK, posedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge CORECLK, posedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge CORECLK, posedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge CORECLK, posedge CONFREQVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, CONFREQVALID_delay); + $setuphold (posedge CORECLK, posedge DBGSEL0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[0]); + $setuphold (posedge CORECLK, posedge DBGSEL0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[1]); + $setuphold (posedge CORECLK, posedge DBGSEL0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[2]); + $setuphold (posedge CORECLK, posedge DBGSEL0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[3]); + $setuphold (posedge CORECLK, posedge DBGSEL0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[4]); + $setuphold (posedge CORECLK, posedge DBGSEL0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL0_delay[5]); + $setuphold (posedge CORECLK, posedge DBGSEL1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[0]); + $setuphold (posedge CORECLK, posedge DBGSEL1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[1]); + $setuphold (posedge CORECLK, posedge DBGSEL1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[2]); + $setuphold (posedge CORECLK, posedge DBGSEL1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[3]); + $setuphold (posedge CORECLK, posedge DBGSEL1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[4]); + $setuphold (posedge CORECLK, posedge DBGSEL1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, DBGSEL1_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge CORECLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge CORECLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIREPLAYRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRCOR_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMERRUNCOR[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMERRUNCOR_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXCOMPLETIONRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXCOMPLETIONRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMERRUNCOR[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMERRUNCOR_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA0[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA0_delay[9]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[0]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[100]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[101]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[102]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[103]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[104]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[105]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[106]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[107]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[108]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[109]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[10]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[110]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[111]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[112]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[113]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[114]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[115]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[116]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[117]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[118]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[119]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[11]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[120]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[121]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[122]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[123]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[124]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[125]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[126]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[127]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[128]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[129]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[12]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[130]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[131]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[132]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[133]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[134]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[135]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[136]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[137]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[138]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[139]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[13]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[140]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[141]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[142]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[143]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[14]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[15]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[16]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[17]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[18]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[19]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[1]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[20]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[21]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[22]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[23]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[24]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[25]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[26]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[27]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[28]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[29]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[2]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[30]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[31]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[32]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[33]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[34]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[35]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[36]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[37]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[38]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[39]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[3]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[40]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[41]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[42]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[43]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[44]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[45]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[46]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[47]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[48]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[49]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[4]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[50]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[51]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[52]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[53]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[54]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[55]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[56]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[57]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[58]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[59]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[5]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[60]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[61]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[62]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[63]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[64]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[65]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[66]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[67]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[68]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[69]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[6]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[70]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[71]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[72]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[73]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[74]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[75]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[76]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[77]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[78]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[79]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[7]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[80]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[81]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[82]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[83]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[84]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[85]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[86]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[87]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[88]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[89]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[8]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[90]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[91]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[92]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[93]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[94]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[95]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[96]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[97]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[98]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[99]); + $setuphold (posedge CORECLK, posedge MIRXPOSTEDREQUESTRAMREADDATA1[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, MIRXPOSTEDREQUESTRAMREADDATA1_delay[9]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[2]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[3]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[4]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[5]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[6]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG0[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG0_delay[7]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[2]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[3]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[4]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[5]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[6]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVEREDTAG1[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVEREDTAG1_delay[7]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVERED[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECOMPLDELIVERED[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECOMPLDELIVERED_delay[1]); + $setuphold (posedge CORECLK, posedge PCIECQNPREQ[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPREQ_delay[0]); + $setuphold (posedge CORECLK, posedge PCIECQNPUSERCREDITRCVD, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQNPUSERCREDITRCVD_delay); + $setuphold (posedge CORECLK, posedge PCIECQPIPELINEEMPTY, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIECQPIPELINEEMPTY_delay); + $setuphold (posedge CORECLK, posedge PCIEPOSTEDREQDELIVERED, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, PCIEPOSTEDREQDELIVERED_delay); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[100]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[101]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[102]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[103]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[104]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[105]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[106]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[107]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[108]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[109]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[110]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[111]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[112]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[113]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[114]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[115]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[116]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[117]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[118]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[119]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[120]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[121]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[122]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[123]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[124]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[125]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[126]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[127]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[128]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[129]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[130]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[131]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[132]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[133]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[134]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[135]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[136]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[137]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[138]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[139]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[140]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[141]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[142]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[143]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[144]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[145]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[146]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[147]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[148]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[149]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[150]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[151]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[152]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[153]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[154]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[155]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[156]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[157]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[158]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[159]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[160]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[161]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[162]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[163]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[164]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[165]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[166]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[167]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[168]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[169]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[170]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[171]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[172]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[173]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[174]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[175]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[176]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[177]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[178]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[179]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[180]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[181]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[182]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[183]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[184]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[185]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[186]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[187]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[188]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[189]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[190]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[191]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[192]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[193]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[194]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[195]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[196]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[197]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[198]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[199]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[200]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[201]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[202]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[203]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[204]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[205]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[206]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[207]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[208]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[209]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[210]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[211]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[212]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[213]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[214]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[215]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[216]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[217]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[218]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[219]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[220]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[221]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[222]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[223]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[224]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[225]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[226]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[227]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[228]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[229]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[230]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[231]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[232]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[233]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[234]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[235]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[236]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[237]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[238]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[239]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[240]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[241]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[242]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[243]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[244]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[245]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[246]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[247]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[248]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[249]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[250]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[251]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[252]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[253]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[254]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[255]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[62]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[63]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[64]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[65]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[66]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[67]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[68]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[69]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[70]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[71]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[72]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[73]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[74]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[75]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[76]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[77]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[78]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[79]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[80]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[81]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[82]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[83]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[84]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[85]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[86]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[87]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[88]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[89]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[90]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[91]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[92]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[93]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[94]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[95]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[96]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[97]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[98]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[99]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTDATA_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTUSER_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCIXTXTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCIXTXTVALID_delay); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge CORECLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge CORECLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[60], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[60]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[61], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[61]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge CORECLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge CORECLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, SAXISRQTVALID_delay); + $setuphold (posedge CORECLK, posedge USERCLKEN, 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERCLKEN_delay); + $setuphold (posedge CORECLK, posedge USERSPAREIN[0], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[0]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[10], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[10]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[11], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[11]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[12], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[12]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[13], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[13]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[14], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[14]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[15], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[15]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[16], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[16]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[17], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[17]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[18], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[18]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[19], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[19]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[1], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[1]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[20], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[20]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[21], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[21]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[22], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[22]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[23], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[23]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[24], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[24]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[25], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[25]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[26], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[26]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[27], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[27]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[28], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[28]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[29], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[29]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[2], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[2]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[30], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[30]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[31], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[31]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[3], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[3]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[4], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[4]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[5], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[5]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[6], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[6]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[7], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[7]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[8], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[8]); + $setuphold (posedge CORECLK, posedge USERSPAREIN[9], 0:0:0, 0:0:0, notifier, , , CORECLK_delay, USERSPAREIN_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX00DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX00ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX00EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX00PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX00STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX00SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX00SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX00VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX01DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX01ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX01EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX01PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX01STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX01SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX01SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX01VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX02DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX02ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX02EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX02PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX02STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX02SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX02SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX02VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX03DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX03ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX03EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX03PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX03STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX03SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX03SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX03VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX04DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX04ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX04EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX04PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX04STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX04SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX04SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX04VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX05DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX05ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX05EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX05PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX05STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX05SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX05SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX05VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX06DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX06ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX06EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX06PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX06STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX06SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX06SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX06VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX07DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX07ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX07EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX07PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX07STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX07SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX07SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX07VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX08DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX08ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX08EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX08PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX08STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX08SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX08SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX08VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX09DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX09ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX09EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX09PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX09STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX09SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX09SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX09VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX10DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX10ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX10EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX10PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX10STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX10SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX10SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX10VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX11DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX11ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX11EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX11PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX11STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX11SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX11SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX11VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX12DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX12ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX12EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX12PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX12STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX12SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX12SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX12VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX13DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX13ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX13EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX13PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX13STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX13SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX13SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX13VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX14DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX14ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX14EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX14PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX14STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX14SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX14SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX14VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX15DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX15ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX15EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX15PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX15STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX15SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX15SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX15VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge PIPECLK, negedge PLGEN34REDOEQSPEED, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQSPEED_delay); + $setuphold (posedge PIPECLK, negedge PLGEN34REDOEQUALIZATION, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQUALIZATION_delay); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX00DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX00ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX00EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX00PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX00STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX00SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX00SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX00VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX00VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX01DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX01ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX01EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX01PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX01STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX01SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX01SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX01VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX01VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX02DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX02ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX02EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX02PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX02STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX02SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX02SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX02VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX02VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX03DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX03ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX03EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX03PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX03STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX03SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX03SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX03VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX03VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX04DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX04ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX04EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX04PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX04STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX04SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX04SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX04VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX04VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX05DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX05ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX05EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX05PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX05STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX05SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX05SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX05VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX05VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX06DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX06ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX06EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX06PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX06STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX06SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX06SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX06VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX06VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX07DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX07ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX07EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX07PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX07STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX07SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX07SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX07VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX07VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX08DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX08ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX08EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX08PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX08STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX08SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX08SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX08VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX08VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX09DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX09ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX09EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX09PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX09STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX09SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX09SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX09VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX09VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX10DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX10ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX10EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX10PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX10STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX10SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX10SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX10VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX10VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX11DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX11ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX11EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX11PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX11STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX11SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX11SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX11VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX11VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX12DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX12ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX12EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX12PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX12STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX12SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX12SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX12VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX12VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX13DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX13ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX13EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX13PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX13STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX13SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX13SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX13VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX13VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX14DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX14ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX14EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX14PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX14STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX14SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX14SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX14VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX14VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15CHARISK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15CHARISK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATAVALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[18], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[19], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[20], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[21], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[22], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[23], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[24], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[25], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[26], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[27], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[28], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[29], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[30], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[31], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX15DATA[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX15ELECIDLE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPADAPTDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPLFFSSEL, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX15EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX15PHYSTATUS, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX15STARTBLOCK[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15STARTBLOCK[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STARTBLOCK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15STATUS[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX15SYNCHEADER[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX15SYNCHEADER[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX15VALID, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPERX15VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX00EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX00EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX01EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX01EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX02EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX02EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX03EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX03EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX04EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX04EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX05EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX05EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX06EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX06EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX07EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX07EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX08EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX08EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX09EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX09EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX10EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX10EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX11EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX11EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX12EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX12EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX13EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX13EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX14EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX14EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[0], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[10], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[11], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[12], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[13], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[14], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[15], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[16], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[17], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[1], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[2], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[3], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[4], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[5], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[6], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[7], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[8], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQCOEFF[9], 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX15EQDONE, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PIPETX15EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge PIPECLK, posedge PLGEN34REDOEQSPEED, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQSPEED_delay); + $setuphold (posedge PIPECLK, posedge PLGEN34REDOEQUALIZATION, 0:0:0, 0:0:0, notifier, , , PIPECLK_delay, PLGEN34REDOEQUALIZATION_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PCIE_2_1.v b/verilog/src/unisims/PCIE_2_1.v new file mode 100644 index 0000000..98303ea --- /dev/null +++ b/verilog/src/unisims/PCIE_2_1.v @@ -0,0 +1,7507 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : PCIE_2_1.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl +// Revision: 1.0 +// 01/18/13 - 695630 - added drp monitor +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PCIE_2_1 ( + CFGAERECRCCHECKEN, + CFGAERECRCGENEN, + CFGAERROOTERRCORRERRRECEIVED, + CFGAERROOTERRCORRERRREPORTINGEN, + CFGAERROOTERRFATALERRRECEIVED, + CFGAERROOTERRFATALERRREPORTINGEN, + CFGAERROOTERRNONFATALERRRECEIVED, + CFGAERROOTERRNONFATALERRREPORTINGEN, + CFGBRIDGESERREN, + CFGCOMMANDBUSMASTERENABLE, + CFGCOMMANDINTERRUPTDISABLE, + CFGCOMMANDIOENABLE, + CFGCOMMANDMEMENABLE, + CFGCOMMANDSERREN, + CFGDEVCONTROL2ARIFORWARDEN, + CFGDEVCONTROL2ATOMICEGRESSBLOCK, + CFGDEVCONTROL2ATOMICREQUESTEREN, + CFGDEVCONTROL2CPLTIMEOUTDIS, + CFGDEVCONTROL2CPLTIMEOUTVAL, + CFGDEVCONTROL2IDOCPLEN, + CFGDEVCONTROL2IDOREQEN, + CFGDEVCONTROL2LTREN, + CFGDEVCONTROL2TLPPREFIXBLOCK, + CFGDEVCONTROLAUXPOWEREN, + CFGDEVCONTROLCORRERRREPORTINGEN, + CFGDEVCONTROLENABLERO, + CFGDEVCONTROLEXTTAGEN, + CFGDEVCONTROLFATALERRREPORTINGEN, + CFGDEVCONTROLMAXPAYLOAD, + CFGDEVCONTROLMAXREADREQ, + CFGDEVCONTROLNONFATALREPORTINGEN, + CFGDEVCONTROLNOSNOOPEN, + CFGDEVCONTROLPHANTOMEN, + CFGDEVCONTROLURERRREPORTINGEN, + CFGDEVSTATUSCORRERRDETECTED, + CFGDEVSTATUSFATALERRDETECTED, + CFGDEVSTATUSNONFATALERRDETECTED, + CFGDEVSTATUSURDETECTED, + CFGERRAERHEADERLOGSETN, + CFGERRCPLRDYN, + CFGINTERRUPTDO, + CFGINTERRUPTMMENABLE, + CFGINTERRUPTMSIENABLE, + CFGINTERRUPTMSIXENABLE, + CFGINTERRUPTMSIXFM, + CFGINTERRUPTRDYN, + CFGLINKCONTROLASPMCONTROL, + CFGLINKCONTROLAUTOBANDWIDTHINTEN, + CFGLINKCONTROLBANDWIDTHINTEN, + CFGLINKCONTROLCLOCKPMEN, + CFGLINKCONTROLCOMMONCLOCK, + CFGLINKCONTROLEXTENDEDSYNC, + CFGLINKCONTROLHWAUTOWIDTHDIS, + CFGLINKCONTROLLINKDISABLE, + CFGLINKCONTROLRCB, + CFGLINKCONTROLRETRAINLINK, + CFGLINKSTATUSAUTOBANDWIDTHSTATUS, + CFGLINKSTATUSBANDWIDTHSTATUS, + CFGLINKSTATUSCURRENTSPEED, + CFGLINKSTATUSDLLACTIVE, + CFGLINKSTATUSLINKTRAINING, + CFGLINKSTATUSNEGOTIATEDWIDTH, + CFGMGMTDO, + CFGMGMTRDWRDONEN, + CFGMSGDATA, + CFGMSGRECEIVED, + CFGMSGRECEIVEDASSERTINTA, + CFGMSGRECEIVEDASSERTINTB, + CFGMSGRECEIVEDASSERTINTC, + CFGMSGRECEIVEDASSERTINTD, + CFGMSGRECEIVEDDEASSERTINTA, + CFGMSGRECEIVEDDEASSERTINTB, + CFGMSGRECEIVEDDEASSERTINTC, + CFGMSGRECEIVEDDEASSERTINTD, + CFGMSGRECEIVEDERRCOR, + CFGMSGRECEIVEDERRFATAL, + CFGMSGRECEIVEDERRNONFATAL, + CFGMSGRECEIVEDPMASNAK, + CFGMSGRECEIVEDPMETO, + CFGMSGRECEIVEDPMETOACK, + CFGMSGRECEIVEDPMPME, + CFGMSGRECEIVEDSETSLOTPOWERLIMIT, + CFGMSGRECEIVEDUNLOCK, + CFGPCIELINKSTATE, + CFGPMCSRPMEEN, + CFGPMCSRPMESTATUS, + CFGPMCSRPOWERSTATE, + CFGPMRCVASREQL1N, + CFGPMRCVENTERL1N, + CFGPMRCVENTERL23N, + CFGPMRCVREQACKN, + CFGROOTCONTROLPMEINTEN, + CFGROOTCONTROLSYSERRCORRERREN, + CFGROOTCONTROLSYSERRFATALERREN, + CFGROOTCONTROLSYSERRNONFATALERREN, + CFGSLOTCONTROLELECTROMECHILCTLPULSE, + CFGTRANSACTION, + CFGTRANSACTIONADDR, + CFGTRANSACTIONTYPE, + CFGVCTCVCMAP, + DBGSCLRA, + DBGSCLRB, + DBGSCLRC, + DBGSCLRD, + DBGSCLRE, + DBGSCLRF, + DBGSCLRG, + DBGSCLRH, + DBGSCLRI, + DBGSCLRJ, + DBGSCLRK, + DBGVECA, + DBGVECB, + DBGVECC, + DRPDO, + DRPRDY, + LL2BADDLLPERR, + LL2BADTLPERR, + LL2LINKSTATUS, + LL2PROTOCOLERR, + LL2RECEIVERERR, + LL2REPLAYROERR, + LL2REPLAYTOERR, + LL2SUSPENDOK, + LL2TFCINIT1SEQ, + LL2TFCINIT2SEQ, + LL2TXIDLE, + LNKCLKEN, + MIMRXRADDR, + MIMRXREN, + MIMRXWADDR, + MIMRXWDATA, + MIMRXWEN, + MIMTXRADDR, + MIMTXREN, + MIMTXWADDR, + MIMTXWDATA, + MIMTXWEN, + PIPERX0POLARITY, + PIPERX1POLARITY, + PIPERX2POLARITY, + PIPERX3POLARITY, + PIPERX4POLARITY, + PIPERX5POLARITY, + PIPERX6POLARITY, + PIPERX7POLARITY, + PIPETX0CHARISK, + PIPETX0COMPLIANCE, + PIPETX0DATA, + PIPETX0ELECIDLE, + PIPETX0POWERDOWN, + PIPETX1CHARISK, + PIPETX1COMPLIANCE, + PIPETX1DATA, + PIPETX1ELECIDLE, + PIPETX1POWERDOWN, + PIPETX2CHARISK, + PIPETX2COMPLIANCE, + PIPETX2DATA, + PIPETX2ELECIDLE, + PIPETX2POWERDOWN, + PIPETX3CHARISK, + PIPETX3COMPLIANCE, + PIPETX3DATA, + PIPETX3ELECIDLE, + PIPETX3POWERDOWN, + PIPETX4CHARISK, + PIPETX4COMPLIANCE, + PIPETX4DATA, + PIPETX4ELECIDLE, + PIPETX4POWERDOWN, + PIPETX5CHARISK, + PIPETX5COMPLIANCE, + PIPETX5DATA, + PIPETX5ELECIDLE, + PIPETX5POWERDOWN, + PIPETX6CHARISK, + PIPETX6COMPLIANCE, + PIPETX6DATA, + PIPETX6ELECIDLE, + PIPETX6POWERDOWN, + PIPETX7CHARISK, + PIPETX7COMPLIANCE, + PIPETX7DATA, + PIPETX7ELECIDLE, + PIPETX7POWERDOWN, + PIPETXDEEMPH, + PIPETXMARGIN, + PIPETXRATE, + PIPETXRCVRDET, + PIPETXRESET, + PL2L0REQ, + PL2LINKUP, + PL2RECEIVERERR, + PL2RECOVERY, + PL2RXELECIDLE, + PL2RXPMSTATE, + PL2SUSPENDOK, + PLDBGVEC, + PLDIRECTEDCHANGEDONE, + PLINITIALLINKWIDTH, + PLLANEREVERSALMODE, + PLLINKGEN2CAP, + PLLINKPARTNERGEN2SUPPORTED, + PLLINKUPCFGCAP, + PLLTSSMSTATE, + PLPHYLNKUPN, + PLRECEIVEDHOTRST, + PLRXPMSTATE, + PLSELLNKRATE, + PLSELLNKWIDTH, + PLTXPMSTATE, + RECEIVEDFUNCLVLRSTN, + TL2ASPMSUSPENDCREDITCHECKOK, + TL2ASPMSUSPENDREQ, + TL2ERRFCPE, + TL2ERRHDR, + TL2ERRMALFORMED, + TL2ERRRXOVERFLOW, + TL2PPMSUSPENDOK, + TRNFCCPLD, + TRNFCCPLH, + TRNFCNPD, + TRNFCNPH, + TRNFCPD, + TRNFCPH, + TRNLNKUP, + TRNRBARHIT, + TRNRD, + TRNRDLLPDATA, + TRNRDLLPSRCRDY, + TRNRECRCERR, + TRNREOF, + TRNRERRFWD, + TRNRREM, + TRNRSOF, + TRNRSRCDSC, + TRNRSRCRDY, + TRNTBUFAV, + TRNTCFGREQ, + TRNTDLLPDSTRDY, + TRNTDSTRDY, + TRNTERRDROP, + USERRSTN, + + CFGAERINTERRUPTMSGNUM, + CFGDEVID, + CFGDSBUSNUMBER, + CFGDSDEVICENUMBER, + CFGDSFUNCTIONNUMBER, + CFGDSN, + CFGERRACSN, + CFGERRAERHEADERLOG, + CFGERRATOMICEGRESSBLOCKEDN, + CFGERRCORN, + CFGERRCPLABORTN, + CFGERRCPLTIMEOUTN, + CFGERRCPLUNEXPECTN, + CFGERRECRCN, + CFGERRINTERNALCORN, + CFGERRINTERNALUNCORN, + CFGERRLOCKEDN, + CFGERRMALFORMEDN, + CFGERRMCBLOCKEDN, + CFGERRNORECOVERYN, + CFGERRPOISONEDN, + CFGERRPOSTEDN, + CFGERRTLPCPLHEADER, + CFGERRURN, + CFGFORCECOMMONCLOCKOFF, + CFGFORCEEXTENDEDSYNCON, + CFGFORCEMPS, + CFGINTERRUPTASSERTN, + CFGINTERRUPTDI, + CFGINTERRUPTN, + CFGINTERRUPTSTATN, + CFGMGMTBYTEENN, + CFGMGMTDI, + CFGMGMTDWADDR, + CFGMGMTRDENN, + CFGMGMTWRENN, + CFGMGMTWRREADONLYN, + CFGMGMTWRRW1CASRWN, + CFGPCIECAPINTERRUPTMSGNUM, + CFGPMFORCESTATE, + CFGPMFORCESTATEENN, + CFGPMHALTASPML0SN, + CFGPMHALTASPML1N, + CFGPMSENDPMETON, + CFGPMTURNOFFOKN, + CFGPMWAKEN, + CFGPORTNUMBER, + CFGREVID, + CFGSUBSYSID, + CFGSUBSYSVENDID, + CFGTRNPENDINGN, + CFGVENDID, + CMRSTN, + CMSTICKYRSTN, + DBGMODE, + DBGSUBMODE, + DLRSTN, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + FUNCLVLRSTN, + LL2SENDASREQL1, + LL2SENDENTERL1, + LL2SENDENTERL23, + LL2SENDPMACK, + LL2SUSPENDNOW, + LL2TLPRCV, + MIMRXRDATA, + MIMTXRDATA, + PIPECLK, + PIPERX0CHANISALIGNED, + PIPERX0CHARISK, + PIPERX0DATA, + PIPERX0ELECIDLE, + PIPERX0PHYSTATUS, + PIPERX0STATUS, + PIPERX0VALID, + PIPERX1CHANISALIGNED, + PIPERX1CHARISK, + PIPERX1DATA, + PIPERX1ELECIDLE, + PIPERX1PHYSTATUS, + PIPERX1STATUS, + PIPERX1VALID, + PIPERX2CHANISALIGNED, + PIPERX2CHARISK, + PIPERX2DATA, + PIPERX2ELECIDLE, + PIPERX2PHYSTATUS, + PIPERX2STATUS, + PIPERX2VALID, + PIPERX3CHANISALIGNED, + PIPERX3CHARISK, + PIPERX3DATA, + PIPERX3ELECIDLE, + PIPERX3PHYSTATUS, + PIPERX3STATUS, + PIPERX3VALID, + PIPERX4CHANISALIGNED, + PIPERX4CHARISK, + PIPERX4DATA, + PIPERX4ELECIDLE, + PIPERX4PHYSTATUS, + PIPERX4STATUS, + PIPERX4VALID, + PIPERX5CHANISALIGNED, + PIPERX5CHARISK, + PIPERX5DATA, + PIPERX5ELECIDLE, + PIPERX5PHYSTATUS, + PIPERX5STATUS, + PIPERX5VALID, + PIPERX6CHANISALIGNED, + PIPERX6CHARISK, + PIPERX6DATA, + PIPERX6ELECIDLE, + PIPERX6PHYSTATUS, + PIPERX6STATUS, + PIPERX6VALID, + PIPERX7CHANISALIGNED, + PIPERX7CHARISK, + PIPERX7DATA, + PIPERX7ELECIDLE, + PIPERX7PHYSTATUS, + PIPERX7STATUS, + PIPERX7VALID, + PL2DIRECTEDLSTATE, + PLDBGMODE, + PLDIRECTEDLINKAUTON, + PLDIRECTEDLINKCHANGE, + PLDIRECTEDLINKSPEED, + PLDIRECTEDLINKWIDTH, + PLDIRECTEDLTSSMNEW, + PLDIRECTEDLTSSMNEWVLD, + PLDIRECTEDLTSSMSTALL, + PLDOWNSTREAMDEEMPHSOURCE, + PLRSTN, + PLTRANSMITHOTRST, + PLUPSTREAMPREFERDEEMPH, + SYSRSTN, + TL2ASPMSUSPENDCREDITCHECK, + TL2PPMSUSPENDREQ, + TLRSTN, + TRNFCSEL, + TRNRDSTRDY, + TRNRFCPRET, + TRNRNPOK, + TRNRNPREQ, + TRNTCFGGNT, + TRNTD, + TRNTDLLPDATA, + TRNTDLLPSRCRDY, + TRNTECRCGEN, + TRNTEOF, + TRNTERRFWD, + TRNTREM, + TRNTSOF, + TRNTSRCDSC, + TRNTSRCRDY, + TRNTSTR, + USERCLK, + USERCLK2 +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter [11:0] AER_BASE_PTR = 12'h140; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter AER_CAP_MULTIHEADER = "FALSE"; + parameter [11:0] AER_CAP_NEXTPTR = 12'h178; + parameter AER_CAP_ON = "FALSE"; + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h2; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter integer CFG_ECRC_ERR_CPLSTAT = 0; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE"; + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE"; + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE"; + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0; + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE"; + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ERR_MSG = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_LOCKED_FILTER = "FALSE"; + parameter DISABLE_PPM_FILTER = "FALSE"; + parameter DISABLE_RX_POISONED_RESP = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter INTERRUPT_STAT_AUTO = "TRUE"; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF; + parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE"; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter MPS_FORCE = "FALSE"; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000; + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE"; + parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0; + parameter PM_ASPM_FASTEXIT = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter PM_MF = "FALSE"; + parameter [11:0] RBAR_BASE_PTR = 12'h178; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00; + parameter [15:0] RBAR_CAP_ID = 16'h0015; + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0; + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000; + parameter RBAR_CAP_ON = "FALSE"; + parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000; + parameter [3:0] RBAR_CAP_VERSION = 4'h1; + parameter [2:0] RBAR_NUM = 3'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter [1:0] RP_AUTO_SPD = 2'h1; + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SSL_MESSAGE_AUTO = "FALSE"; + parameter TECRC_EP_INV = "FALSE"; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter TRN_DW = "FALSE"; + parameter TRN_NP_FC = "FALSE"; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_ATOMIC = "TRUE"; + parameter UR_CFG1 = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter UR_PRS_RESPONSE = "TRUE"; + parameter USER_CLK2_DIV2 = "FALSE"; + parameter integer USER_CLK_FREQ = 3; + parameter USE_RID_PINS = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPD = 24; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [11:0] VSEC_BASE_PTR = 12'h128; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGAERROOTERRCORRERRRECEIVED; + output CFGAERROOTERRCORRERRREPORTINGEN; + output CFGAERROOTERRFATALERRRECEIVED; + output CFGAERROOTERRFATALERRREPORTINGEN; + output CFGAERROOTERRNONFATALERRRECEIVED; + output CFGAERROOTERRNONFATALERRREPORTINGEN; + output CFGBRIDGESERREN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2ARIFORWARDEN; + output CFGDEVCONTROL2ATOMICEGRESSBLOCK; + output CFGDEVCONTROL2ATOMICREQUESTEREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROL2IDOCPLEN; + output CFGDEVCONTROL2IDOREQEN; + output CFGDEVCONTROL2LTREN; + output CFGDEVCONTROL2TLPPREFIXBLOCK; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWIDTHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMGMTRDWRDONEN; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGROOTCONTROLPMEINTEN; + output CFGROOTCONTROLSYSERRCORRERREN; + output CFGROOTCONTROLSYSERRFATALERREN; + output CFGROOTCONTROLSYSERRNONFATALERREN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPRDY; + output LL2BADDLLPERR; + output LL2BADTLPERR; + output LL2PROTOCOLERR; + output LL2RECEIVERERR; + output LL2REPLAYROERR; + output LL2REPLAYTOERR; + output LL2SUSPENDOK; + output LL2TFCINIT1SEQ; + output LL2TFCINIT2SEQ; + output LL2TXIDLE; + output LNKCLKEN; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2L0REQ; + output PL2LINKUP; + output PL2RECEIVERERR; + output PL2RECOVERY; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLDIRECTEDCHANGEDONE; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOK; + output TL2ASPMSUSPENDREQ; + output TL2ERRFCPE; + output TL2ERRMALFORMED; + output TL2ERRRXOVERFLOW; + output TL2PPMSUSPENDOK; + output TRNLNKUP; + output TRNRECRCERR; + output TRNREOF; + output TRNRERRFWD; + output TRNRSOF; + output TRNRSRCDSC; + output TRNRSRCRDY; + output TRNTCFGREQ; + output TRNTDLLPDSTRDY; + output TRNTERRDROP; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [127:0] TRNRD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PL2RXPMSTATE; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [1:0] TRNRDLLPSRCRDY; + output [1:0] TRNRREM; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGMGMTDO; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [3:0] TRNTDSTRDY; + output [4:0] LL2LINKSTATUS; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TL2ERRHDR; + output [63:0] TRNRDLLPDATA; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + output [7:0] TRNRBARHIT; + + input CFGERRACSN; + input CFGERRATOMICEGRESSBLOCKEDN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRINTERNALCORN; + input CFGERRINTERNALUNCORN; + input CFGERRLOCKEDN; + input CFGERRMALFORMEDN; + input CFGERRMCBLOCKEDN; + input CFGERRNORECOVERYN; + input CFGERRPOISONEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGFORCECOMMONCLOCKOFF; + input CFGFORCEEXTENDEDSYNCON; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGINTERRUPTSTATN; + input CFGMGMTRDENN; + input CFGMGMTWRENN; + input CFGMGMTWRREADONLYN; + input CFGMGMTWRRW1CASRWN; + input CFGPMFORCESTATEENN; + input CFGPMHALTASPML0SN; + input CFGPMHALTASPML1N; + input CFGPMSENDPMETON; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGTRNPENDINGN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPEN; + input DRPWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1; + input LL2SENDENTERL1; + input LL2SENDENTERL23; + input LL2SENDPMACK; + input LL2SUSPENDNOW; + input LL2TLPRCV; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDIRECTEDLTSSMNEWVLD; + input PLDIRECTEDLTSSMSTALL; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECK; + input TL2PPMSUSPENDREQ; + input TLRSTN; + input TRNRDSTRDY; + input TRNRFCPRET; + input TRNRNPOK; + input TRNRNPREQ; + input TRNTCFGGNT; + input TRNTDLLPSRCRDY; + input TRNTECRCGEN; + input TRNTEOF; + input TRNTERRFWD; + input TRNTSOF; + input TRNTSRCDSC; + input TRNTSRCRDY; + input TRNTSTR; + input USERCLK2; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [127:0] TRNTD; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] CFGPMFORCESTATE; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [1:0] TRNTREM; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFORCEMPS; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGMGMTDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGMGMTBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGAERINTERRUPTMSGNUM; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] CFGPCIECAPINTERRUPTMSGNUM; + input [4:0] PL2DIRECTEDLSTATE; + input [5:0] PLDIRECTEDLTSSMNEW; + input [63:0] CFGDSN; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [7:0] CFGREVID; + input [8:0] DRPADDR; + input [9:0] CFGMGMTDWADDR; + + reg SIM_VERSION_BINARY; + reg [0:0] AER_CAP_ECRC_CHECK_CAPABLE_BINARY; + reg [0:0] AER_CAP_ECRC_GEN_CAPABLE_BINARY; + reg [0:0] AER_CAP_MULTIHEADER_BINARY; + reg [0:0] AER_CAP_ON_BINARY; + reg [0:0] AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY; + reg [0:0] ALLOW_X8_GEN2_BINARY; + reg [0:0] CMD_INTX_IMPLEMENTED_BINARY; + reg [0:0] CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY; + reg [0:0] DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY; + reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY; + reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY; + reg [0:0] DEV_CAP_EXT_TAG_SUPPORTED_BINARY; + reg [0:0] DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY; + reg [0:0] DEV_CAP_ROLE_BASED_ERROR_BINARY; + reg [0:0] DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY; + reg [0:0] DEV_CONTROL_EXT_TAG_DEFAULT_BINARY; + reg [0:0] DISABLE_ASPM_L1_TIMER_BINARY; + reg [0:0] DISABLE_BAR_FILTERING_BINARY; + reg [0:0] DISABLE_ERR_MSG_BINARY; + reg [0:0] DISABLE_ID_CHECK_BINARY; + reg [0:0] DISABLE_LANE_REVERSAL_BINARY; + reg [0:0] DISABLE_LOCKED_FILTER_BINARY; + reg [0:0] DISABLE_PPM_FILTER_BINARY; + reg [0:0] DISABLE_RX_POISONED_RESP_BINARY; + reg [0:0] DISABLE_RX_TC_FILTER_BINARY; + reg [0:0] DISABLE_SCRAMBLING_BINARY; + reg [0:0] DSN_CAP_ON_BINARY; + reg [0:0] ENABLE_RX_TD_ECRC_TRIM_BINARY; + reg [0:0] ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY; + reg [0:0] ENTER_RVRY_EI_L0_BINARY; + reg [0:0] EXIT_LOOPBACK_ON_EI_BINARY; + reg [0:0] INTERRUPT_STAT_AUTO_BINARY; + reg [0:0] IS_SWITCH_BINARY; + reg [0:0] LINK_CAP_ASPM_OPTIONALITY_BINARY; + reg [0:0] LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY; + reg [0:0] LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY; + reg [0:0] LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY; + reg [0:0] LINK_CAP_RSVD_23_BINARY; + reg [0:0] LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY; + reg [0:0] LINK_CONTROL_RCB_BINARY; + reg [0:0] LINK_CTRL2_DEEMPHASIS_BINARY; + reg [0:0] LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY; + reg [0:0] LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY; + reg [0:0] LL_ACK_TIMEOUT_EN_BINARY; + reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY; + reg [0:0] MPS_FORCE_BINARY; + reg [0:0] MSIX_CAP_ON_BINARY; + reg [0:0] MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY; + reg [0:0] MSI_CAP_MULTIMSG_EXTENSION_BINARY; + reg [0:0] MSI_CAP_ON_BINARY; + reg [0:0] MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY; + reg [0:0] PCIE_CAP_ON_BINARY; + reg [0:0] PCIE_CAP_SLOT_IMPLEMENTED_BINARY; + reg [0:0] PL_FAST_TRAIN_BINARY; + reg [0:0] PM_ASPML0S_TIMEOUT_EN_BINARY; + reg [0:0] PM_ASPM_FASTEXIT_BINARY; + reg [0:0] PM_CAP_D1SUPPORT_BINARY; + reg [0:0] PM_CAP_D2SUPPORT_BINARY; + reg [0:0] PM_CAP_DSI_BINARY; + reg [0:0] PM_CAP_ON_BINARY; + reg [0:0] PM_CAP_PME_CLOCK_BINARY; + reg [0:0] PM_CAP_RSVD_04_BINARY; + reg [0:0] PM_CSR_B2B3_BINARY; + reg [0:0] PM_CSR_BPCCEN_BINARY; + reg [0:0] PM_CSR_NOSOFTRST_BINARY; + reg [0:0] PM_MF_BINARY; + reg [0:0] RBAR_CAP_ON_BINARY; + reg [0:0] RECRC_CHK_TRIM_BINARY; + reg [0:0] ROOT_CAP_CRS_SW_VISIBILITY_BINARY; + reg [0:0] SELECT_DLL_IF_BINARY; + reg [0:0] SLOT_CAP_ATT_BUTTON_PRESENT_BINARY; + reg [0:0] SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY; + reg [0:0] SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY; + reg [0:0] SLOT_CAP_HOTPLUG_CAPABLE_BINARY; + reg [0:0] SLOT_CAP_HOTPLUG_SURPRISE_BINARY; + reg [0:0] SLOT_CAP_MRL_SENSOR_PRESENT_BINARY; + reg [0:0] SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY; + reg [0:0] SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY; + reg [0:0] SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY; + reg [0:0] SPARE_BIT0_BINARY; + reg [0:0] SPARE_BIT1_BINARY; + reg [0:0] SPARE_BIT2_BINARY; + reg [0:0] SPARE_BIT3_BINARY; + reg [0:0] SPARE_BIT4_BINARY; + reg [0:0] SPARE_BIT5_BINARY; + reg [0:0] SPARE_BIT6_BINARY; + reg [0:0] SPARE_BIT7_BINARY; + reg [0:0] SPARE_BIT8_BINARY; + reg [0:0] SSL_MESSAGE_AUTO_BINARY; + reg [0:0] TECRC_EP_INV_BINARY; + reg [0:0] TL_RBYPASS_BINARY; + reg [0:0] TL_RX_RAM_RADDR_LATENCY_BINARY; + reg [0:0] TL_RX_RAM_WRITE_LATENCY_BINARY; + reg [0:0] TL_TFC_DISABLE_BINARY; + reg [0:0] TL_TX_CHECKS_DISABLE_BINARY; + reg [0:0] TL_TX_RAM_RADDR_LATENCY_BINARY; + reg [0:0] TL_TX_RAM_WRITE_LATENCY_BINARY; + reg [0:0] TRN_DW_BINARY; + reg [0:0] TRN_NP_FC_BINARY; + reg [0:0] UPCONFIG_CAPABLE_BINARY; + reg [0:0] UPSTREAM_FACING_BINARY; + reg [0:0] UR_ATOMIC_BINARY; + reg [0:0] UR_CFG1_BINARY; + reg [0:0] UR_INV_REQ_BINARY; + reg [0:0] UR_PRS_RESPONSE_BINARY; + reg [0:0] USER_CLK2_DIV2_BINARY; + reg [0:0] USE_RID_PINS_BINARY; + reg [0:0] VC0_CPL_INFINITE_BINARY; + reg [0:0] VC_CAP_ON_BINARY; + reg [0:0] VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY; + reg [0:0] VSEC_CAP_IS_LINK_VISIBLE_BINARY; + reg [0:0] VSEC_CAP_ON_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_CD_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_NPD_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_PD_BINARY; + reg [1:0] CFG_ECRC_ERR_CPLSTAT_BINARY; + reg [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY; + reg [1:0] DEV_CAP_RSVD_17_16_BINARY; + reg [1:0] LINK_CAP_ASPM_SUPPORT_BINARY; + reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY; + reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY; + reg [1:0] PCIE_CAP_RSVD_15_14_BINARY; + reg [1:0] PM_ASPML0S_TIMEOUT_FUNC_BINARY; + reg [1:0] RECRC_CHK_BINARY; + reg [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY; + reg [1:0] TL_RX_RAM_RDATA_LATENCY_BINARY; + reg [1:0] TL_TX_RAM_RDATA_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L1_LATENCY_BINARY; + reg [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY; + reg [2:0] DEV_CAP_RSVD_14_12_BINARY; + reg [2:0] DEV_CAP_RSVD_31_29_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] PL_AUTO_CONFIG_BINARY; + reg [2:0] PM_CAP_AUXCURRENT_BINARY; + reg [2:0] PM_CAP_VERSION_BINARY; + reg [2:0] USER_CLK_FREQ_BINARY; + reg [3:0] PCIE_REVISION_BINARY; + reg [4:0] VC0_TX_LASTPACKET_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_CH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_NPH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_PH_BINARY; + reg [7:0] N_FTS_COMCLK_GEN1_BINARY; + reg [7:0] N_FTS_COMCLK_GEN2_BINARY; + reg [7:0] N_FTS_GEN1_BINARY; + reg [7:0] N_FTS_GEN2_BINARY; + +// tri0 GSR = glbl.GSR; + reg notifier; + + initial begin + case (AER_CAP_ECRC_CHECK_CAPABLE) + "FALSE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0; + "TRUE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_CHECK_CAPABLE); + #1 $finish; + end + endcase + + case (AER_CAP_ECRC_GEN_CAPABLE) + "FALSE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0; + "TRUE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_GEN_CAPABLE); + #1 $finish; + end + endcase + + case (AER_CAP_MULTIHEADER) + "FALSE" : AER_CAP_MULTIHEADER_BINARY = 1'b0; + "TRUE" : AER_CAP_MULTIHEADER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_MULTIHEADER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_MULTIHEADER); + #1 $finish; + end + endcase + + case (AER_CAP_ON) + "FALSE" : AER_CAP_ON_BINARY = 1'b0; + "TRUE" : AER_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ON); + #1 $finish; + end + endcase + + case (AER_CAP_PERMIT_ROOTERR_UPDATE) + "TRUE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b1; + "FALSE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_PERMIT_ROOTERR_UPDATE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AER_CAP_PERMIT_ROOTERR_UPDATE); + #1 $finish; + end + endcase + + case (ALLOW_X8_GEN2) + "FALSE" : ALLOW_X8_GEN2_BINARY = 1'b0; + "TRUE" : ALLOW_X8_GEN2_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALLOW_X8_GEN2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALLOW_X8_GEN2); + #1 $finish; + end + endcase + + case (CMD_INTX_IMPLEMENTED) + "TRUE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b1; + "FALSE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CMD_INTX_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CMD_INTX_IMPLEMENTED); + #1 $finish; + end + endcase + + case (CPL_TIMEOUT_DISABLE_SUPPORTED) + "FALSE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b0; + "TRUE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CPL_TIMEOUT_DISABLE_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CPL_TIMEOUT_DISABLE_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_ARI_FORWARDING_SUPPORTED) + "FALSE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_ARI_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ARI_FORWARDING_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED) + "FALSE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED) + "FALSE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED) + "FALSE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_CAS128_COMPLETER_SUPPORTED) + "FALSE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_CAS128_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_CAS128_COMPLETER_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED) + "FALSE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED) + "FALSE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_LTR_MECHANISM_SUPPORTED) + "FALSE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_LTR_MECHANISM_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_LTR_MECHANISM_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING) + "FALSE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b0; + "TRUE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING); + #1 $finish; + end + endcase + + case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE) + "TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b1; + "FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE); + #1 $finish; + end + endcase + + case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE) + "TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b1; + "FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE); + #1 $finish; + end + endcase + + case (DEV_CAP_EXT_TAG_SUPPORTED) + "TRUE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1; + "FALSE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_EXT_TAG_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE) + "FALSE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0; + "TRUE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE); + #1 $finish; + end + endcase + + case (DEV_CAP_ROLE_BASED_ERROR) + "TRUE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b1; + "FALSE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ROLE_BASED_ERROR on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ROLE_BASED_ERROR); + #1 $finish; + end + endcase + + case (DEV_CONTROL_AUX_POWER_SUPPORTED) + "FALSE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CONTROL_AUX_POWER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_AUX_POWER_SUPPORTED); + #1 $finish; + end + endcase + + case (DEV_CONTROL_EXT_TAG_DEFAULT) + "FALSE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b0; + "TRUE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CONTROL_EXT_TAG_DEFAULT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_EXT_TAG_DEFAULT); + #1 $finish; + end + endcase + + case (DISABLE_ASPM_L1_TIMER) + "FALSE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b0; + "TRUE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ASPM_L1_TIMER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ASPM_L1_TIMER); + #1 $finish; + end + endcase + + case (DISABLE_BAR_FILTERING) + "FALSE" : DISABLE_BAR_FILTERING_BINARY = 1'b0; + "TRUE" : DISABLE_BAR_FILTERING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_BAR_FILTERING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_BAR_FILTERING); + #1 $finish; + end + endcase + + case (DISABLE_ERR_MSG) + "FALSE" : DISABLE_ERR_MSG_BINARY = 1'b0; + "TRUE" : DISABLE_ERR_MSG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ERR_MSG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ERR_MSG); + #1 $finish; + end + endcase + + case (DISABLE_ID_CHECK) + "FALSE" : DISABLE_ID_CHECK_BINARY = 1'b0; + "TRUE" : DISABLE_ID_CHECK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ID_CHECK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ID_CHECK); + #1 $finish; + end + endcase + + case (DISABLE_LANE_REVERSAL) + "FALSE" : DISABLE_LANE_REVERSAL_BINARY = 1'b0; + "TRUE" : DISABLE_LANE_REVERSAL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_LANE_REVERSAL on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LANE_REVERSAL); + #1 $finish; + end + endcase + + case (DISABLE_LOCKED_FILTER) + "FALSE" : DISABLE_LOCKED_FILTER_BINARY = 1'b0; + "TRUE" : DISABLE_LOCKED_FILTER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_LOCKED_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LOCKED_FILTER); + #1 $finish; + end + endcase + + case (DISABLE_PPM_FILTER) + "FALSE" : DISABLE_PPM_FILTER_BINARY = 1'b0; + "TRUE" : DISABLE_PPM_FILTER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_PPM_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_PPM_FILTER); + #1 $finish; + end + endcase + + case (DISABLE_RX_POISONED_RESP) + "FALSE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b0; + "TRUE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_RX_POISONED_RESP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_POISONED_RESP); + #1 $finish; + end + endcase + + case (DISABLE_RX_TC_FILTER) + "FALSE" : DISABLE_RX_TC_FILTER_BINARY = 1'b0; + "TRUE" : DISABLE_RX_TC_FILTER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_RX_TC_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_TC_FILTER); + #1 $finish; + end + endcase + + case (DISABLE_SCRAMBLING) + "FALSE" : DISABLE_SCRAMBLING_BINARY = 1'b0; + "TRUE" : DISABLE_SCRAMBLING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_SCRAMBLING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_SCRAMBLING); + #1 $finish; + end + endcase + + case (DSN_CAP_ON) + "TRUE" : DSN_CAP_ON_BINARY = 1'b1; + "FALSE" : DSN_CAP_ON_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DSN_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DSN_CAP_ON); + #1 $finish; + end + endcase + + case (ENABLE_RX_TD_ECRC_TRIM) + "FALSE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b0; + "TRUE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ENABLE_RX_TD_ECRC_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENABLE_RX_TD_ECRC_TRIM); + #1 $finish; + end + endcase + + case (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED) + "FALSE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b0; + "TRUE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED); + #1 $finish; + end + endcase + + case (ENTER_RVRY_EI_L0) + "TRUE" : ENTER_RVRY_EI_L0_BINARY = 1'b1; + "FALSE" : ENTER_RVRY_EI_L0_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ENTER_RVRY_EI_L0 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ENTER_RVRY_EI_L0); + #1 $finish; + end + endcase + + case (EXIT_LOOPBACK_ON_EI) + "TRUE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b1; + "FALSE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute EXIT_LOOPBACK_ON_EI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", EXIT_LOOPBACK_ON_EI); + #1 $finish; + end + endcase + + case (INTERRUPT_STAT_AUTO) + "TRUE" : INTERRUPT_STAT_AUTO_BINARY = 1'b1; + "FALSE" : INTERRUPT_STAT_AUTO_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute INTERRUPT_STAT_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", INTERRUPT_STAT_AUTO); + #1 $finish; + end + endcase + + case (IS_SWITCH) + "FALSE" : IS_SWITCH_BINARY = 1'b0; + "TRUE" : IS_SWITCH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute IS_SWITCH on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", IS_SWITCH); + #1 $finish; + end + endcase + + case (LINK_CAP_ASPM_OPTIONALITY) + "TRUE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b1; + "FALSE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_OPTIONALITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_CAP_ASPM_OPTIONALITY); + #1 $finish; + end + endcase + + case (LINK_CAP_CLOCK_POWER_MANAGEMENT) + "FALSE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b0; + "TRUE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_CLOCK_POWER_MANAGEMENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_CLOCK_POWER_MANAGEMENT); + #1 $finish; + end + endcase + + case (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP) + "FALSE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b0; + "TRUE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP); + #1 $finish; + end + endcase + + case (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP) + "FALSE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b0; + "TRUE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP); + #1 $finish; + end + endcase + + case (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE) + "FALSE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b0; + "TRUE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE); + #1 $finish; + end + endcase + + case (LINK_CTRL2_DEEMPHASIS) + "FALSE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b0; + "TRUE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CTRL2_DEEMPHASIS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_DEEMPHASIS); + #1 $finish; + end + endcase + + case (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE) + "FALSE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b0; + "TRUE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE); + #1 $finish; + end + endcase + + case (LINK_STATUS_SLOT_CLOCK_CONFIG) + "TRUE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1; + "FALSE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_STATUS_SLOT_CLOCK_CONFIG); + #1 $finish; + end + endcase + + case (LL_ACK_TIMEOUT_EN) + "FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN); + #1 $finish; + end + endcase + + case (LL_REPLAY_TIMEOUT_EN) + "FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN); + #1 $finish; + end + endcase + + case (MPS_FORCE) + "FALSE" : MPS_FORCE_BINARY = 1'b0; + "TRUE" : MPS_FORCE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MPS_FORCE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MPS_FORCE); + #1 $finish; + end + endcase + + case (MSIX_CAP_ON) + "FALSE" : MSIX_CAP_ON_BINARY = 1'b0; + "TRUE" : MSIX_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSIX_CAP_ON); + #1 $finish; + end + endcase + + case (MSI_CAP_64_BIT_ADDR_CAPABLE) + "TRUE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b1; + "FALSE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_64_BIT_ADDR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_64_BIT_ADDR_CAPABLE); + #1 $finish; + end + endcase + + case (MSI_CAP_ON) + "FALSE" : MSI_CAP_ON_BINARY = 1'b0; + "TRUE" : MSI_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSI_CAP_ON); + #1 $finish; + end + endcase + + case (MSI_CAP_PER_VECTOR_MASKING_CAPABLE) + "TRUE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b1; + "FALSE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_PER_VECTOR_MASKING_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_PER_VECTOR_MASKING_CAPABLE); + #1 $finish; + end + endcase + + case (PCIE_CAP_ON) + "TRUE" : PCIE_CAP_ON_BINARY = 1'b1; + "FALSE" : PCIE_CAP_ON_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PCIE_CAP_ON); + #1 $finish; + end + endcase + + case (PCIE_CAP_SLOT_IMPLEMENTED) + "FALSE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b0; + "TRUE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_SLOT_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCIE_CAP_SLOT_IMPLEMENTED); + #1 $finish; + end + endcase + + case (PL_FAST_TRAIN) + "FALSE" : PL_FAST_TRAIN_BINARY = 1'b0; + "TRUE" : PL_FAST_TRAIN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_FAST_TRAIN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_FAST_TRAIN); + #1 $finish; + end + endcase + + case (PM_ASPML0S_TIMEOUT_EN) + "FALSE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPML0S_TIMEOUT_EN); + #1 $finish; + end + endcase + + case (PM_ASPM_FASTEXIT) + "FALSE" : PM_ASPM_FASTEXIT_BINARY = 1'b0; + "TRUE" : PM_ASPM_FASTEXIT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_ASPM_FASTEXIT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPM_FASTEXIT); + #1 $finish; + end + endcase + + case (PM_CAP_D1SUPPORT) + "TRUE" : PM_CAP_D1SUPPORT_BINARY = 1'b1; + "FALSE" : PM_CAP_D1SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D1SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D1SUPPORT); + #1 $finish; + end + endcase + + case (PM_CAP_D2SUPPORT) + "TRUE" : PM_CAP_D2SUPPORT_BINARY = 1'b1; + "FALSE" : PM_CAP_D2SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D2SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D2SUPPORT); + #1 $finish; + end + endcase + + case (PM_CAP_DSI) + "FALSE" : PM_CAP_DSI_BINARY = 1'b0; + "TRUE" : PM_CAP_DSI_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_DSI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_DSI); + #1 $finish; + end + endcase + + case (PM_CAP_ON) + "TRUE" : PM_CAP_ON_BINARY = 1'b1; + "FALSE" : PM_CAP_ON_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_ON); + #1 $finish; + end + endcase + + case (PM_CAP_PME_CLOCK) + "FALSE" : PM_CAP_PME_CLOCK_BINARY = 1'b0; + "TRUE" : PM_CAP_PME_CLOCK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_PME_CLOCK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_PME_CLOCK); + #1 $finish; + end + endcase + + case (PM_CSR_B2B3) + "FALSE" : PM_CSR_B2B3_BINARY = 1'b0; + "TRUE" : PM_CSR_B2B3_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_B2B3 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_B2B3); + #1 $finish; + end + endcase + + case (PM_CSR_BPCCEN) + "FALSE" : PM_CSR_BPCCEN_BINARY = 1'b0; + "TRUE" : PM_CSR_BPCCEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_BPCCEN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_BPCCEN); + #1 $finish; + end + endcase + + case (PM_CSR_NOSOFTRST) + "TRUE" : PM_CSR_NOSOFTRST_BINARY = 1'b1; + "FALSE" : PM_CSR_NOSOFTRST_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_NOSOFTRST on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CSR_NOSOFTRST); + #1 $finish; + end + endcase + + case (PM_MF) + "FALSE" : PM_MF_BINARY = 1'b0; + "TRUE" : PM_MF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_MF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_MF); + #1 $finish; + end + endcase + + case (RBAR_CAP_ON) + "FALSE" : RBAR_CAP_ON_BINARY = 1'b0; + "TRUE" : RBAR_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RBAR_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RBAR_CAP_ON); + #1 $finish; + end + endcase + + case (RECRC_CHK_TRIM) + "FALSE" : RECRC_CHK_TRIM_BINARY = 1'b0; + "TRUE" : RECRC_CHK_TRIM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RECRC_CHK_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RECRC_CHK_TRIM); + #1 $finish; + end + endcase + + case (ROOT_CAP_CRS_SW_VISIBILITY) + "FALSE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b0; + "TRUE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ROOT_CAP_CRS_SW_VISIBILITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ROOT_CAP_CRS_SW_VISIBILITY); + #1 $finish; + end + endcase + + case (SELECT_DLL_IF) + "FALSE" : SELECT_DLL_IF_BINARY = 1'b0; + "TRUE" : SELECT_DLL_IF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SELECT_DLL_IF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SELECT_DLL_IF); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "1.2" : SIM_VERSION_BINARY = 0; + "1.3" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + "3.0" : SIM_VERSION_BINARY = 0; + "4.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION); + #1 $finish; + end + endcase + + case (SLOT_CAP_ATT_BUTTON_PRESENT) + "FALSE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_BUTTON_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_BUTTON_PRESENT); + #1 $finish; + end + endcase + + case (SLOT_CAP_ATT_INDICATOR_PRESENT) + "FALSE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_INDICATOR_PRESENT); + #1 $finish; + end + endcase + + case (SLOT_CAP_ELEC_INTERLOCK_PRESENT) + "FALSE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ELEC_INTERLOCK_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ELEC_INTERLOCK_PRESENT); + #1 $finish; + end + endcase + + case (SLOT_CAP_HOTPLUG_CAPABLE) + "FALSE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b0; + "TRUE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_CAPABLE); + #1 $finish; + end + endcase + + case (SLOT_CAP_HOTPLUG_SURPRISE) + "FALSE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b0; + "TRUE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_SURPRISE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_SURPRISE); + #1 $finish; + end + endcase + + case (SLOT_CAP_MRL_SENSOR_PRESENT) + "FALSE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_MRL_SENSOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_MRL_SENSOR_PRESENT); + #1 $finish; + end + endcase + + case (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT) + "FALSE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_NO_CMD_COMPLETED_SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_NO_CMD_COMPLETED_SUPPORT); + #1 $finish; + end + endcase + + case (SLOT_CAP_POWER_CONTROLLER_PRESENT) + "FALSE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_CONTROLLER_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_CONTROLLER_PRESENT); + #1 $finish; + end + endcase + + case (SLOT_CAP_POWER_INDICATOR_PRESENT) + "FALSE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_INDICATOR_PRESENT); + #1 $finish; + end + endcase + + case (SSL_MESSAGE_AUTO) + "FALSE" : SSL_MESSAGE_AUTO_BINARY = 1'b0; + "TRUE" : SSL_MESSAGE_AUTO_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SSL_MESSAGE_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SSL_MESSAGE_AUTO); + #1 $finish; + end + endcase + + case (TECRC_EP_INV) + "FALSE" : TECRC_EP_INV_BINARY = 1'b0; + "TRUE" : TECRC_EP_INV_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TECRC_EP_INV on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TECRC_EP_INV); + #1 $finish; + end + endcase + + case (TL_RBYPASS) + "FALSE" : TL_RBYPASS_BINARY = 1'b0; + "TRUE" : TL_RBYPASS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_RBYPASS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_RBYPASS); + #1 $finish; + end + endcase + + case (TL_TFC_DISABLE) + "FALSE" : TL_TFC_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TFC_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TFC_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TFC_DISABLE); + #1 $finish; + end + endcase + + case (TL_TX_CHECKS_DISABLE) + "FALSE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TX_CHECKS_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TX_CHECKS_DISABLE); + #1 $finish; + end + endcase + + case (TRN_DW) + "FALSE" : TRN_DW_BINARY = 1'b0; + "TRUE" : TRN_DW_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TRN_DW on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_DW); + #1 $finish; + end + endcase + + case (TRN_NP_FC) + "FALSE" : TRN_NP_FC_BINARY = 1'b0; + "TRUE" : TRN_NP_FC_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TRN_NP_FC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_NP_FC); + #1 $finish; + end + endcase + + case (UPCONFIG_CAPABLE) + "TRUE" : UPCONFIG_CAPABLE_BINARY = 1'b1; + "FALSE" : UPCONFIG_CAPABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UPCONFIG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPCONFIG_CAPABLE); + #1 $finish; + end + endcase + + case (UPSTREAM_FACING) + "TRUE" : UPSTREAM_FACING_BINARY = 1'b1; + "FALSE" : UPSTREAM_FACING_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UPSTREAM_FACING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPSTREAM_FACING); + #1 $finish; + end + endcase + + case (UR_ATOMIC) + "TRUE" : UR_ATOMIC_BINARY = 1'b1; + "FALSE" : UR_ATOMIC_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UR_ATOMIC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_ATOMIC); + #1 $finish; + end + endcase + + case (UR_CFG1) + "TRUE" : UR_CFG1_BINARY = 1'b1; + "FALSE" : UR_CFG1_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UR_CFG1 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_CFG1); + #1 $finish; + end + endcase + + case (UR_INV_REQ) + "TRUE" : UR_INV_REQ_BINARY = 1'b1; + "FALSE" : UR_INV_REQ_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UR_INV_REQ on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_INV_REQ); + #1 $finish; + end + endcase + + case (UR_PRS_RESPONSE) + "TRUE" : UR_PRS_RESPONSE_BINARY = 1'b1; + "FALSE" : UR_PRS_RESPONSE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute UR_PRS_RESPONSE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_PRS_RESPONSE); + #1 $finish; + end + endcase + + case (USER_CLK2_DIV2) + "FALSE" : USER_CLK2_DIV2_BINARY = 1'b0; + "TRUE" : USER_CLK2_DIV2_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute USER_CLK2_DIV2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USER_CLK2_DIV2); + #1 $finish; + end + endcase + + case (USE_RID_PINS) + "FALSE" : USE_RID_PINS_BINARY = 1'b0; + "TRUE" : USE_RID_PINS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute USE_RID_PINS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USE_RID_PINS); + #1 $finish; + end + endcase + + case (VC0_CPL_INFINITE) + "TRUE" : VC0_CPL_INFINITE_BINARY = 1'b1; + "FALSE" : VC0_CPL_INFINITE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VC0_CPL_INFINITE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VC0_CPL_INFINITE); + #1 $finish; + end + endcase + + case (VC_CAP_ON) + "FALSE" : VC_CAP_ON_BINARY = 1'b0; + "TRUE" : VC_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_ON); + #1 $finish; + end + endcase + + case (VC_CAP_REJECT_SNOOP_TRANSACTIONS) + "FALSE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b0; + "TRUE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC_CAP_REJECT_SNOOP_TRANSACTIONS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_REJECT_SNOOP_TRANSACTIONS); + #1 $finish; + end + endcase + + case (VSEC_CAP_IS_LINK_VISIBLE) + "TRUE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b1; + "FALSE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VSEC_CAP_IS_LINK_VISIBLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VSEC_CAP_IS_LINK_VISIBLE); + #1 $finish; + end + endcase + + case (VSEC_CAP_ON) + "FALSE" : VSEC_CAP_ON_BINARY = 1'b0; + "TRUE" : VSEC_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VSEC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VSEC_CAP_ON); + #1 $finish; + end + endcase + + if ((CFG_ECRC_ERR_CPLSTAT >= 0) && (CFG_ECRC_ERR_CPLSTAT <= 3)) + CFG_ECRC_ERR_CPLSTAT_BINARY = CFG_ECRC_ERR_CPLSTAT; + else begin + $display("Attribute Syntax Error : The Attribute CFG_ECRC_ERR_CPLSTAT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", CFG_ECRC_ERR_CPLSTAT); + #1 $finish; + end + + if ((DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L0S_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = DEV_CAP_ENDPOINT_L0S_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L0S_LATENCY); + #1 $finish; + end + + if ((DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L1_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = DEV_CAP_ENDPOINT_L1_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L1_LATENCY); + #1 $finish; + end + + if ((DEV_CAP_MAX_PAYLOAD_SUPPORTED >= 0) && (DEV_CAP_MAX_PAYLOAD_SUPPORTED <= 7)) + DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY = DEV_CAP_MAX_PAYLOAD_SUPPORTED; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_MAX_PAYLOAD_SUPPORTED on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_MAX_PAYLOAD_SUPPORTED); + #1 $finish; + end + + if ((DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT >= 0) && (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT <= 3)) + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY = DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT); + #1 $finish; + end + + if ((DEV_CAP_RSVD_14_12 >= 0) && (DEV_CAP_RSVD_14_12 <= 7)) + DEV_CAP_RSVD_14_12_BINARY = DEV_CAP_RSVD_14_12; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_14_12 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_14_12); + #1 $finish; + end + + if ((DEV_CAP_RSVD_17_16 >= 0) && (DEV_CAP_RSVD_17_16 <= 3)) + DEV_CAP_RSVD_17_16_BINARY = DEV_CAP_RSVD_17_16; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_17_16 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_RSVD_17_16); + #1 $finish; + end + + if ((DEV_CAP_RSVD_31_29 >= 0) && (DEV_CAP_RSVD_31_29 <= 7)) + DEV_CAP_RSVD_31_29_BINARY = DEV_CAP_RSVD_31_29; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_31_29 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_31_29); + #1 $finish; + end + + if ((LINK_CAP_ASPM_SUPPORT >= 0) && (LINK_CAP_ASPM_SUPPORT <= 3)) + LINK_CAP_ASPM_SUPPORT_BINARY = LINK_CAP_ASPM_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LINK_CAP_ASPM_SUPPORT); + #1 $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1); + #1 $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2); + #1 $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN1); + #1 $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN2); + #1 $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1); + #1 $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2); + #1 $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN1); + #1 $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN2); + #1 $finish; + end + + if ((LINK_CAP_RSVD_23 >= 0) && (LINK_CAP_RSVD_23 <= 1)) + LINK_CAP_RSVD_23_BINARY = LINK_CAP_RSVD_23; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_RSVD_23 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CAP_RSVD_23); + #1 $finish; + end + + if ((LINK_CONTROL_RCB >= 0) && (LINK_CONTROL_RCB <= 1)) + LINK_CONTROL_RCB_BINARY = LINK_CONTROL_RCB; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CONTROL_RCB on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CONTROL_RCB); + #1 $finish; + end + + if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3)) + LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC); + #1 $finish; + end + + if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3)) + LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC); + #1 $finish; + end + + if ((MSIX_CAP_PBA_BIR >= 0) && (MSIX_CAP_PBA_BIR <= 7)) + MSIX_CAP_PBA_BIR_BINARY = MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_PBA_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((MSIX_CAP_TABLE_BIR >= 0) && (MSIX_CAP_TABLE_BIR <= 7)) + MSIX_CAP_TABLE_BIR_BINARY = MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_TABLE_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((MSI_CAP_MULTIMSGCAP >= 0) && (MSI_CAP_MULTIMSGCAP <= 7)) + MSI_CAP_MULTIMSGCAP_BINARY = MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSGCAP on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((MSI_CAP_MULTIMSG_EXTENSION >= 0) && (MSI_CAP_MULTIMSG_EXTENSION <= 1)) + MSI_CAP_MULTIMSG_EXTENSION_BINARY = MSI_CAP_MULTIMSG_EXTENSION; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSG_EXTENSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", MSI_CAP_MULTIMSG_EXTENSION); + #1 $finish; + end + + if ((N_FTS_COMCLK_GEN1 >= 0) && (N_FTS_COMCLK_GEN1 <= 255)) + N_FTS_COMCLK_GEN1_BINARY = N_FTS_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN1); + #1 $finish; + end + + if ((N_FTS_COMCLK_GEN2 >= 0) && (N_FTS_COMCLK_GEN2 <= 255)) + N_FTS_COMCLK_GEN2_BINARY = N_FTS_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN2); + #1 $finish; + end + + if ((N_FTS_GEN1 >= 0) && (N_FTS_GEN1 <= 255)) + N_FTS_GEN1_BINARY = N_FTS_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN1); + #1 $finish; + end + + if ((N_FTS_GEN2 >= 0) && (N_FTS_GEN2 <= 255)) + N_FTS_GEN2_BINARY = N_FTS_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN2); + #1 $finish; + end + + if ((PCIE_CAP_RSVD_15_14 >= 0) && (PCIE_CAP_RSVD_15_14 <= 3)) + PCIE_CAP_RSVD_15_14_BINARY = PCIE_CAP_RSVD_15_14; + else begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_RSVD_15_14 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PCIE_CAP_RSVD_15_14); + #1 $finish; + end + + if ((PCIE_REVISION >= 0) && (PCIE_REVISION <= 15)) + PCIE_REVISION_BINARY = PCIE_REVISION; + else begin + $display("Attribute Syntax Error : The Attribute PCIE_REVISION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", PCIE_REVISION); + #1 $finish; + end + + if ((PL_AUTO_CONFIG >= 0) && (PL_AUTO_CONFIG <= 7)) + PL_AUTO_CONFIG_BINARY = PL_AUTO_CONFIG; + else begin + $display("Attribute Syntax Error : The Attribute PL_AUTO_CONFIG on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PL_AUTO_CONFIG); + #1 $finish; + end + + if ((PM_ASPML0S_TIMEOUT_FUNC >= 0) && (PM_ASPML0S_TIMEOUT_FUNC <= 3)) + PM_ASPML0S_TIMEOUT_FUNC_BINARY = PM_ASPML0S_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PM_ASPML0S_TIMEOUT_FUNC); + #1 $finish; + end + + if ((PM_CAP_AUXCURRENT >= 0) && (PM_CAP_AUXCURRENT <= 7)) + PM_CAP_AUXCURRENT_BINARY = PM_CAP_AUXCURRENT; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_AUXCURRENT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_AUXCURRENT); + #1 $finish; + end + + if ((PM_CAP_RSVD_04 >= 0) && (PM_CAP_RSVD_04 <= 1)) + PM_CAP_RSVD_04_BINARY = PM_CAP_RSVD_04; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_RSVD_04 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", PM_CAP_RSVD_04); + #1 $finish; + end + + if ((PM_CAP_VERSION >= 0) && (PM_CAP_VERSION <= 7)) + PM_CAP_VERSION_BINARY = PM_CAP_VERSION; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_VERSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_VERSION); + #1 $finish; + end + + if ((RECRC_CHK >= 0) && (RECRC_CHK <= 3)) + RECRC_CHK_BINARY = RECRC_CHK; + else begin + $display("Attribute Syntax Error : The Attribute RECRC_CHK on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", RECRC_CHK); + #1 $finish; + end + + if ((SLOT_CAP_SLOT_POWER_LIMIT_SCALE >= 0) && (SLOT_CAP_SLOT_POWER_LIMIT_SCALE <= 3)) + SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY = SLOT_CAP_SLOT_POWER_LIMIT_SCALE; + else begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_SLOT_POWER_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", SLOT_CAP_SLOT_POWER_LIMIT_SCALE); + #1 $finish; + end + + if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1)) + SPARE_BIT0_BINARY = SPARE_BIT0; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0); + #1 $finish; + end + + if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1)) + SPARE_BIT1_BINARY = SPARE_BIT1; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1); + #1 $finish; + end + + if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1)) + SPARE_BIT2_BINARY = SPARE_BIT2; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2); + #1 $finish; + end + + if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1)) + SPARE_BIT3_BINARY = SPARE_BIT3; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3); + #1 $finish; + end + + if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1)) + SPARE_BIT4_BINARY = SPARE_BIT4; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4); + #1 $finish; + end + + if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1)) + SPARE_BIT5_BINARY = SPARE_BIT5; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5); + #1 $finish; + end + + if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1)) + SPARE_BIT6_BINARY = SPARE_BIT6; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6); + #1 $finish; + end + + if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1)) + SPARE_BIT7_BINARY = SPARE_BIT7; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7); + #1 $finish; + end + + if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1)) + SPARE_BIT8_BINARY = SPARE_BIT8; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8); + #1 $finish; + end + + if ((TL_RX_RAM_RADDR_LATENCY >= 0) && (TL_RX_RAM_RADDR_LATENCY <= 1)) + TL_RX_RAM_RADDR_LATENCY_BINARY = TL_RX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_RADDR_LATENCY); + #1 $finish; + end + + if ((TL_RX_RAM_RDATA_LATENCY >= 0) && (TL_RX_RAM_RDATA_LATENCY <= 3)) + TL_RX_RAM_RDATA_LATENCY_BINARY = TL_RX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_RX_RAM_RDATA_LATENCY); + #1 $finish; + end + + if ((TL_RX_RAM_WRITE_LATENCY >= 0) && (TL_RX_RAM_WRITE_LATENCY <= 1)) + TL_RX_RAM_WRITE_LATENCY_BINARY = TL_RX_RAM_WRITE_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_WRITE_LATENCY); + #1 $finish; + end + + if ((TL_TX_RAM_RADDR_LATENCY >= 0) && (TL_TX_RAM_RADDR_LATENCY <= 1)) + TL_TX_RAM_RADDR_LATENCY_BINARY = TL_TX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_RADDR_LATENCY); + #1 $finish; + end + + if ((TL_TX_RAM_RDATA_LATENCY >= 0) && (TL_TX_RAM_RDATA_LATENCY <= 3)) + TL_TX_RAM_RDATA_LATENCY_BINARY = TL_TX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_TX_RAM_RDATA_LATENCY); + #1 $finish; + end + + if ((TL_TX_RAM_WRITE_LATENCY >= 0) && (TL_TX_RAM_WRITE_LATENCY <= 1)) + TL_TX_RAM_WRITE_LATENCY_BINARY = TL_TX_RAM_WRITE_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_WRITE_LATENCY); + #1 $finish; + end + + if ((USER_CLK_FREQ >= 0) && (USER_CLK_FREQ <= 7)) + USER_CLK_FREQ_BINARY = USER_CLK_FREQ; + else begin + $display("Attribute Syntax Error : The Attribute USER_CLK_FREQ on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", USER_CLK_FREQ); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_CD >= 0) && (VC0_TOTAL_CREDITS_CD <= 2047)) + VC0_TOTAL_CREDITS_CD_BINARY = VC0_TOTAL_CREDITS_CD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_CD); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_CH >= 0) && (VC0_TOTAL_CREDITS_CH <= 127)) + VC0_TOTAL_CREDITS_CH_BINARY = VC0_TOTAL_CREDITS_CH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_CH); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_NPD >= 0) && (VC0_TOTAL_CREDITS_NPD <= 2047)) + VC0_TOTAL_CREDITS_NPD_BINARY = VC0_TOTAL_CREDITS_NPD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_NPD); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_NPH >= 0) && (VC0_TOTAL_CREDITS_NPH <= 127)) + VC0_TOTAL_CREDITS_NPH_BINARY = VC0_TOTAL_CREDITS_NPH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_NPH); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_PD >= 0) && (VC0_TOTAL_CREDITS_PD <= 2047)) + VC0_TOTAL_CREDITS_PD_BINARY = VC0_TOTAL_CREDITS_PD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_PD); + #1 $finish; + end + + if ((VC0_TOTAL_CREDITS_PH >= 0) && (VC0_TOTAL_CREDITS_PH <= 127)) + VC0_TOTAL_CREDITS_PH_BINARY = VC0_TOTAL_CREDITS_PH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_PH); + #1 $finish; + end + + if ((VC0_TX_LASTPACKET >= 0) && (VC0_TX_LASTPACKET <= 31)) + VC0_TX_LASTPACKET_BINARY = VC0_TX_LASTPACKET; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TX_LASTPACKET on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", VC0_TX_LASTPACKET); + #1 $finish; + end + + end + + wire [11:0] delay_DBGVECC; + wire [11:0] delay_PLDBGVEC; + wire [11:0] delay_TRNFCCPLD; + wire [11:0] delay_TRNFCNPD; + wire [11:0] delay_TRNFCPD; + wire [127:0] delay_TRNRD; + wire [12:0] delay_MIMRXRADDR; + wire [12:0] delay_MIMRXWADDR; + wire [12:0] delay_MIMTXRADDR; + wire [12:0] delay_MIMTXWADDR; + wire [15:0] delay_CFGMSGDATA; + wire [15:0] delay_DRPDO; + wire [15:0] delay_PIPETX0DATA; + wire [15:0] delay_PIPETX1DATA; + wire [15:0] delay_PIPETX2DATA; + wire [15:0] delay_PIPETX3DATA; + wire [15:0] delay_PIPETX4DATA; + wire [15:0] delay_PIPETX5DATA; + wire [15:0] delay_PIPETX6DATA; + wire [15:0] delay_PIPETX7DATA; + wire [1:0] delay_CFGLINKCONTROLASPMCONTROL; + wire [1:0] delay_CFGLINKSTATUSCURRENTSPEED; + wire [1:0] delay_CFGPMCSRPOWERSTATE; + wire [1:0] delay_PIPETX0CHARISK; + wire [1:0] delay_PIPETX0POWERDOWN; + wire [1:0] delay_PIPETX1CHARISK; + wire [1:0] delay_PIPETX1POWERDOWN; + wire [1:0] delay_PIPETX2CHARISK; + wire [1:0] delay_PIPETX2POWERDOWN; + wire [1:0] delay_PIPETX3CHARISK; + wire [1:0] delay_PIPETX3POWERDOWN; + wire [1:0] delay_PIPETX4CHARISK; + wire [1:0] delay_PIPETX4POWERDOWN; + wire [1:0] delay_PIPETX5CHARISK; + wire [1:0] delay_PIPETX5POWERDOWN; + wire [1:0] delay_PIPETX6CHARISK; + wire [1:0] delay_PIPETX6POWERDOWN; + wire [1:0] delay_PIPETX7CHARISK; + wire [1:0] delay_PIPETX7POWERDOWN; + wire [1:0] delay_PL2RXPMSTATE; + wire [1:0] delay_PLLANEREVERSALMODE; + wire [1:0] delay_PLRXPMSTATE; + wire [1:0] delay_PLSELLNKWIDTH; + wire [1:0] delay_TRNRDLLPSRCRDY; + wire [1:0] delay_TRNRREM; + wire [2:0] delay_CFGDEVCONTROLMAXPAYLOAD; + wire [2:0] delay_CFGDEVCONTROLMAXREADREQ; + wire [2:0] delay_CFGINTERRUPTMMENABLE; + wire [2:0] delay_CFGPCIELINKSTATE; + wire [2:0] delay_PIPETXMARGIN; + wire [2:0] delay_PLINITIALLINKWIDTH; + wire [2:0] delay_PLTXPMSTATE; + wire [31:0] delay_CFGMGMTDO; + wire [3:0] delay_CFGDEVCONTROL2CPLTIMEOUTVAL; + wire [3:0] delay_CFGLINKSTATUSNEGOTIATEDWIDTH; + wire [3:0] delay_TRNTDSTRDY; + wire [4:0] delay_LL2LINKSTATUS; + wire [5:0] delay_PLLTSSMSTATE; + wire [5:0] delay_TRNTBUFAV; + wire [63:0] delay_DBGVECA; + wire [63:0] delay_DBGVECB; + wire [63:0] delay_TL2ERRHDR; + wire [63:0] delay_TRNRDLLPDATA; + wire [67:0] delay_MIMRXWDATA; + wire [68:0] delay_MIMTXWDATA; + wire [6:0] delay_CFGTRANSACTIONADDR; + wire [6:0] delay_CFGVCTCVCMAP; + wire [7:0] delay_CFGINTERRUPTDO; + wire [7:0] delay_TRNFCCPLH; + wire [7:0] delay_TRNFCNPH; + wire [7:0] delay_TRNFCPH; + wire [7:0] delay_TRNRBARHIT; + wire delay_CFGAERECRCCHECKEN; + wire delay_CFGAERECRCGENEN; + wire delay_CFGAERROOTERRCORRERRRECEIVED; + wire delay_CFGAERROOTERRCORRERRREPORTINGEN; + wire delay_CFGAERROOTERRFATALERRRECEIVED; + wire delay_CFGAERROOTERRFATALERRREPORTINGEN; + wire delay_CFGAERROOTERRNONFATALERRRECEIVED; + wire delay_CFGAERROOTERRNONFATALERRREPORTINGEN; + wire delay_CFGBRIDGESERREN; + wire delay_CFGCOMMANDBUSMASTERENABLE; + wire delay_CFGCOMMANDINTERRUPTDISABLE; + wire delay_CFGCOMMANDIOENABLE; + wire delay_CFGCOMMANDMEMENABLE; + wire delay_CFGCOMMANDSERREN; + wire delay_CFGDEVCONTROL2ARIFORWARDEN; + wire delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK; + wire delay_CFGDEVCONTROL2ATOMICREQUESTEREN; + wire delay_CFGDEVCONTROL2CPLTIMEOUTDIS; + wire delay_CFGDEVCONTROL2IDOCPLEN; + wire delay_CFGDEVCONTROL2IDOREQEN; + wire delay_CFGDEVCONTROL2LTREN; + wire delay_CFGDEVCONTROL2TLPPREFIXBLOCK; + wire delay_CFGDEVCONTROLAUXPOWEREN; + wire delay_CFGDEVCONTROLCORRERRREPORTINGEN; + wire delay_CFGDEVCONTROLENABLERO; + wire delay_CFGDEVCONTROLEXTTAGEN; + wire delay_CFGDEVCONTROLFATALERRREPORTINGEN; + wire delay_CFGDEVCONTROLNONFATALREPORTINGEN; + wire delay_CFGDEVCONTROLNOSNOOPEN; + wire delay_CFGDEVCONTROLPHANTOMEN; + wire delay_CFGDEVCONTROLURERRREPORTINGEN; + wire delay_CFGDEVSTATUSCORRERRDETECTED; + wire delay_CFGDEVSTATUSFATALERRDETECTED; + wire delay_CFGDEVSTATUSNONFATALERRDETECTED; + wire delay_CFGDEVSTATUSURDETECTED; + wire delay_CFGERRAERHEADERLOGSETN; + wire delay_CFGERRCPLRDYN; + wire delay_CFGINTERRUPTMSIENABLE; + wire delay_CFGINTERRUPTMSIXENABLE; + wire delay_CFGINTERRUPTMSIXFM; + wire delay_CFGINTERRUPTRDYN; + wire delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN; + wire delay_CFGLINKCONTROLBANDWIDTHINTEN; + wire delay_CFGLINKCONTROLCLOCKPMEN; + wire delay_CFGLINKCONTROLCOMMONCLOCK; + wire delay_CFGLINKCONTROLEXTENDEDSYNC; + wire delay_CFGLINKCONTROLHWAUTOWIDTHDIS; + wire delay_CFGLINKCONTROLLINKDISABLE; + wire delay_CFGLINKCONTROLRCB; + wire delay_CFGLINKCONTROLRETRAINLINK; + wire delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + wire delay_CFGLINKSTATUSBANDWIDTHSTATUS; + wire delay_CFGLINKSTATUSDLLACTIVE; + wire delay_CFGLINKSTATUSLINKTRAINING; + wire delay_CFGMGMTRDWRDONEN; + wire delay_CFGMSGRECEIVED; + wire delay_CFGMSGRECEIVEDASSERTINTA; + wire delay_CFGMSGRECEIVEDASSERTINTB; + wire delay_CFGMSGRECEIVEDASSERTINTC; + wire delay_CFGMSGRECEIVEDASSERTINTD; + wire delay_CFGMSGRECEIVEDDEASSERTINTA; + wire delay_CFGMSGRECEIVEDDEASSERTINTB; + wire delay_CFGMSGRECEIVEDDEASSERTINTC; + wire delay_CFGMSGRECEIVEDDEASSERTINTD; + wire delay_CFGMSGRECEIVEDERRCOR; + wire delay_CFGMSGRECEIVEDERRFATAL; + wire delay_CFGMSGRECEIVEDERRNONFATAL; + wire delay_CFGMSGRECEIVEDPMASNAK; + wire delay_CFGMSGRECEIVEDPMETO; + wire delay_CFGMSGRECEIVEDPMETOACK; + wire delay_CFGMSGRECEIVEDPMPME; + wire delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + wire delay_CFGMSGRECEIVEDUNLOCK; + wire delay_CFGPMCSRPMEEN; + wire delay_CFGPMCSRPMESTATUS; + wire delay_CFGPMRCVASREQL1N; + wire delay_CFGPMRCVENTERL1N; + wire delay_CFGPMRCVENTERL23N; + wire delay_CFGPMRCVREQACKN; + wire delay_CFGROOTCONTROLPMEINTEN; + wire delay_CFGROOTCONTROLSYSERRCORRERREN; + wire delay_CFGROOTCONTROLSYSERRFATALERREN; + wire delay_CFGROOTCONTROLSYSERRNONFATALERREN; + wire delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE; + wire delay_CFGTRANSACTION; + wire delay_CFGTRANSACTIONTYPE; + wire delay_DBGSCLRA; + wire delay_DBGSCLRB; + wire delay_DBGSCLRC; + wire delay_DBGSCLRD; + wire delay_DBGSCLRE; + wire delay_DBGSCLRF; + wire delay_DBGSCLRG; + wire delay_DBGSCLRH; + wire delay_DBGSCLRI; + wire delay_DBGSCLRJ; + wire delay_DBGSCLRK; + wire delay_DRPRDY; + wire delay_LL2BADDLLPERR; + wire delay_LL2BADTLPERR; + wire delay_LL2PROTOCOLERR; + wire delay_LL2RECEIVERERR; + wire delay_LL2REPLAYROERR; + wire delay_LL2REPLAYTOERR; + wire delay_LL2SUSPENDOK; + wire delay_LL2TFCINIT1SEQ; + wire delay_LL2TFCINIT2SEQ; + wire delay_LL2TXIDLE; + wire delay_LNKCLKEN; + wire delay_MIMRXREN; + wire delay_MIMRXWEN; + wire delay_MIMTXREN; + wire delay_MIMTXWEN; + wire delay_PIPERX0POLARITY; + wire delay_PIPERX1POLARITY; + wire delay_PIPERX2POLARITY; + wire delay_PIPERX3POLARITY; + wire delay_PIPERX4POLARITY; + wire delay_PIPERX5POLARITY; + wire delay_PIPERX6POLARITY; + wire delay_PIPERX7POLARITY; + wire delay_PIPETX0COMPLIANCE; + wire delay_PIPETX0ELECIDLE; + wire delay_PIPETX1COMPLIANCE; + wire delay_PIPETX1ELECIDLE; + wire delay_PIPETX2COMPLIANCE; + wire delay_PIPETX2ELECIDLE; + wire delay_PIPETX3COMPLIANCE; + wire delay_PIPETX3ELECIDLE; + wire delay_PIPETX4COMPLIANCE; + wire delay_PIPETX4ELECIDLE; + wire delay_PIPETX5COMPLIANCE; + wire delay_PIPETX5ELECIDLE; + wire delay_PIPETX6COMPLIANCE; + wire delay_PIPETX6ELECIDLE; + wire delay_PIPETX7COMPLIANCE; + wire delay_PIPETX7ELECIDLE; + wire delay_PIPETXDEEMPH; + wire delay_PIPETXRATE; + wire delay_PIPETXRCVRDET; + wire delay_PIPETXRESET; + wire delay_PL2L0REQ; + wire delay_PL2LINKUP; + wire delay_PL2RECEIVERERR; + wire delay_PL2RECOVERY; + wire delay_PL2RXELECIDLE; + wire delay_PL2SUSPENDOK; + wire delay_PLDIRECTEDCHANGEDONE; + wire delay_PLLINKGEN2CAP; + wire delay_PLLINKPARTNERGEN2SUPPORTED; + wire delay_PLLINKUPCFGCAP; + wire delay_PLPHYLNKUPN; + wire delay_PLRECEIVEDHOTRST; + wire delay_PLSELLNKRATE; + wire delay_RECEIVEDFUNCLVLRSTN; + wire delay_TL2ASPMSUSPENDCREDITCHECKOK; + wire delay_TL2ASPMSUSPENDREQ; + wire delay_TL2ERRFCPE; + wire delay_TL2ERRMALFORMED; + wire delay_TL2ERRRXOVERFLOW; + wire delay_TL2PPMSUSPENDOK; + wire delay_TRNLNKUP; + wire delay_TRNRECRCERR; + wire delay_TRNREOF; + wire delay_TRNRERRFWD; + wire delay_TRNRSOF; + wire delay_TRNRSRCDSC; + wire delay_TRNRSRCRDY; + wire delay_TRNTCFGREQ; + wire delay_TRNTDLLPDSTRDY; + wire delay_TRNTERRDROP; + wire delay_USERRSTN; + + wire [127:0] delay_CFGERRAERHEADERLOG; + wire [127:0] delay_TRNTD; + wire [15:0] delay_CFGDEVID; + wire [15:0] delay_CFGSUBSYSID; + wire [15:0] delay_CFGSUBSYSVENDID; + wire [15:0] delay_CFGVENDID; + wire [15:0] delay_DRPDI; + wire [15:0] delay_PIPERX0DATA; + wire [15:0] delay_PIPERX1DATA; + wire [15:0] delay_PIPERX2DATA; + wire [15:0] delay_PIPERX3DATA; + wire [15:0] delay_PIPERX4DATA; + wire [15:0] delay_PIPERX5DATA; + wire [15:0] delay_PIPERX6DATA; + wire [15:0] delay_PIPERX7DATA; + wire [1:0] delay_CFGPMFORCESTATE; + wire [1:0] delay_DBGMODE; + wire [1:0] delay_PIPERX0CHARISK; + wire [1:0] delay_PIPERX1CHARISK; + wire [1:0] delay_PIPERX2CHARISK; + wire [1:0] delay_PIPERX3CHARISK; + wire [1:0] delay_PIPERX4CHARISK; + wire [1:0] delay_PIPERX5CHARISK; + wire [1:0] delay_PIPERX6CHARISK; + wire [1:0] delay_PIPERX7CHARISK; + wire [1:0] delay_PLDIRECTEDLINKCHANGE; + wire [1:0] delay_PLDIRECTEDLINKWIDTH; + wire [1:0] delay_TRNTREM; + wire [2:0] delay_CFGDSFUNCTIONNUMBER; + wire [2:0] delay_CFGFORCEMPS; + wire [2:0] delay_PIPERX0STATUS; + wire [2:0] delay_PIPERX1STATUS; + wire [2:0] delay_PIPERX2STATUS; + wire [2:0] delay_PIPERX3STATUS; + wire [2:0] delay_PIPERX4STATUS; + wire [2:0] delay_PIPERX5STATUS; + wire [2:0] delay_PIPERX6STATUS; + wire [2:0] delay_PIPERX7STATUS; + wire [2:0] delay_PLDBGMODE; + wire [2:0] delay_TRNFCSEL; + wire [31:0] delay_CFGMGMTDI; + wire [31:0] delay_TRNTDLLPDATA; + wire [3:0] delay_CFGMGMTBYTEENN; + wire [47:0] delay_CFGERRTLPCPLHEADER; + wire [4:0] delay_CFGAERINTERRUPTMSGNUM; + wire [4:0] delay_CFGDSDEVICENUMBER; + wire [4:0] delay_CFGPCIECAPINTERRUPTMSGNUM; + wire [4:0] delay_PL2DIRECTEDLSTATE; + wire [5:0] delay_PLDIRECTEDLTSSMNEW; + wire [63:0] delay_CFGDSN; + wire [67:0] delay_MIMRXRDATA; + wire [68:0] delay_MIMTXRDATA; + wire [7:0] delay_CFGDSBUSNUMBER; + wire [7:0] delay_CFGINTERRUPTDI; + wire [7:0] delay_CFGPORTNUMBER; + wire [7:0] delay_CFGREVID; + wire [8:0] delay_DRPADDR; + wire [9:0] delay_CFGMGMTDWADDR; + wire delay_CFGERRACSN; + wire delay_CFGERRATOMICEGRESSBLOCKEDN; + wire delay_CFGERRCORN; + wire delay_CFGERRCPLABORTN; + wire delay_CFGERRCPLTIMEOUTN; + wire delay_CFGERRCPLUNEXPECTN; + wire delay_CFGERRECRCN; + wire delay_CFGERRINTERNALCORN; + wire delay_CFGERRINTERNALUNCORN; + wire delay_CFGERRLOCKEDN; + wire delay_CFGERRMALFORMEDN; + wire delay_CFGERRMCBLOCKEDN; + wire delay_CFGERRNORECOVERYN; + wire delay_CFGERRPOISONEDN; + wire delay_CFGERRPOSTEDN; + wire delay_CFGERRURN; + wire delay_CFGFORCECOMMONCLOCKOFF; + wire delay_CFGFORCEEXTENDEDSYNCON; + wire delay_CFGINTERRUPTASSERTN; + wire delay_CFGINTERRUPTN; + wire delay_CFGINTERRUPTSTATN; + wire delay_CFGMGMTRDENN; + wire delay_CFGMGMTWRENN; + wire delay_CFGMGMTWRREADONLYN; + wire delay_CFGMGMTWRRW1CASRWN; + wire delay_CFGPMFORCESTATEENN; + wire delay_CFGPMHALTASPML0SN; + wire delay_CFGPMHALTASPML1N; + wire delay_CFGPMSENDPMETON; + wire delay_CFGPMTURNOFFOKN; + wire delay_CFGPMWAKEN; + wire delay_CFGTRNPENDINGN; + wire delay_CMRSTN; + wire delay_CMSTICKYRSTN; + wire delay_DBGSUBMODE; + wire delay_DLRSTN; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_FUNCLVLRSTN; + wire delay_LL2SENDASREQL1; + wire delay_LL2SENDENTERL1; + wire delay_LL2SENDENTERL23; + wire delay_LL2SENDPMACK; + wire delay_LL2SUSPENDNOW; + wire delay_LL2TLPRCV; + wire delay_PIPECLK; + wire delay_PIPERX0CHANISALIGNED; + wire delay_PIPERX0ELECIDLE; + wire delay_PIPERX0PHYSTATUS; + wire delay_PIPERX0VALID; + wire delay_PIPERX1CHANISALIGNED; + wire delay_PIPERX1ELECIDLE; + wire delay_PIPERX1PHYSTATUS; + wire delay_PIPERX1VALID; + wire delay_PIPERX2CHANISALIGNED; + wire delay_PIPERX2ELECIDLE; + wire delay_PIPERX2PHYSTATUS; + wire delay_PIPERX2VALID; + wire delay_PIPERX3CHANISALIGNED; + wire delay_PIPERX3ELECIDLE; + wire delay_PIPERX3PHYSTATUS; + wire delay_PIPERX3VALID; + wire delay_PIPERX4CHANISALIGNED; + wire delay_PIPERX4ELECIDLE; + wire delay_PIPERX4PHYSTATUS; + wire delay_PIPERX4VALID; + wire delay_PIPERX5CHANISALIGNED; + wire delay_PIPERX5ELECIDLE; + wire delay_PIPERX5PHYSTATUS; + wire delay_PIPERX5VALID; + wire delay_PIPERX6CHANISALIGNED; + wire delay_PIPERX6ELECIDLE; + wire delay_PIPERX6PHYSTATUS; + wire delay_PIPERX6VALID; + wire delay_PIPERX7CHANISALIGNED; + wire delay_PIPERX7ELECIDLE; + wire delay_PIPERX7PHYSTATUS; + wire delay_PIPERX7VALID; + wire delay_PLDIRECTEDLINKAUTON; + wire delay_PLDIRECTEDLINKSPEED; + wire delay_PLDIRECTEDLTSSMNEWVLD; + wire delay_PLDIRECTEDLTSSMSTALL; + wire delay_PLDOWNSTREAMDEEMPHSOURCE; + wire delay_PLRSTN; + wire delay_PLTRANSMITHOTRST; + wire delay_PLUPSTREAMPREFERDEEMPH; + wire delay_SYSRSTN; + wire delay_TL2ASPMSUSPENDCREDITCHECK; + wire delay_TL2PPMSUSPENDREQ; + wire delay_TLRSTN; + wire delay_TRNRDSTRDY; + wire delay_TRNRFCPRET; + wire delay_TRNRNPOK; + wire delay_TRNRNPREQ; + wire delay_TRNTCFGGNT; + wire delay_TRNTDLLPSRCRDY; + wire delay_TRNTECRCGEN; + wire delay_TRNTEOF; + wire delay_TRNTERRFWD; + wire delay_TRNTSOF; + wire delay_TRNTSRCDSC; + wire delay_TRNTSRCRDY; + wire delay_TRNTSTR; + wire delay_USERCLK2; + wire delay_USERCLK; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + + assign #(out_delay) CFGAERECRCCHECKEN = delay_CFGAERECRCCHECKEN; + assign #(out_delay) CFGAERECRCGENEN = delay_CFGAERECRCGENEN; + assign #(out_delay) CFGAERROOTERRCORRERRRECEIVED = delay_CFGAERROOTERRCORRERRRECEIVED; + assign #(out_delay) CFGAERROOTERRCORRERRREPORTINGEN = delay_CFGAERROOTERRCORRERRREPORTINGEN; + assign #(out_delay) CFGAERROOTERRFATALERRRECEIVED = delay_CFGAERROOTERRFATALERRRECEIVED; + assign #(out_delay) CFGAERROOTERRFATALERRREPORTINGEN = delay_CFGAERROOTERRFATALERRREPORTINGEN; + assign #(out_delay) CFGAERROOTERRNONFATALERRRECEIVED = delay_CFGAERROOTERRNONFATALERRRECEIVED; + assign #(out_delay) CFGAERROOTERRNONFATALERRREPORTINGEN = delay_CFGAERROOTERRNONFATALERRREPORTINGEN; + assign #(out_delay) CFGBRIDGESERREN = delay_CFGBRIDGESERREN; + assign #(out_delay) CFGCOMMANDBUSMASTERENABLE = delay_CFGCOMMANDBUSMASTERENABLE; + assign #(out_delay) CFGCOMMANDINTERRUPTDISABLE = delay_CFGCOMMANDINTERRUPTDISABLE; + assign #(out_delay) CFGCOMMANDIOENABLE = delay_CFGCOMMANDIOENABLE; + assign #(out_delay) CFGCOMMANDMEMENABLE = delay_CFGCOMMANDMEMENABLE; + assign #(out_delay) CFGCOMMANDSERREN = delay_CFGCOMMANDSERREN; + assign #(out_delay) CFGDEVCONTROL2ARIFORWARDEN = delay_CFGDEVCONTROL2ARIFORWARDEN; + assign #(out_delay) CFGDEVCONTROL2ATOMICEGRESSBLOCK = delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK; + assign #(out_delay) CFGDEVCONTROL2ATOMICREQUESTEREN = delay_CFGDEVCONTROL2ATOMICREQUESTEREN; + assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTDIS = delay_CFGDEVCONTROL2CPLTIMEOUTDIS; + assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTVAL = delay_CFGDEVCONTROL2CPLTIMEOUTVAL; + assign #(out_delay) CFGDEVCONTROL2IDOCPLEN = delay_CFGDEVCONTROL2IDOCPLEN; + assign #(out_delay) CFGDEVCONTROL2IDOREQEN = delay_CFGDEVCONTROL2IDOREQEN; + assign #(out_delay) CFGDEVCONTROL2LTREN = delay_CFGDEVCONTROL2LTREN; + assign #(out_delay) CFGDEVCONTROL2TLPPREFIXBLOCK = delay_CFGDEVCONTROL2TLPPREFIXBLOCK; + assign #(out_delay) CFGDEVCONTROLAUXPOWEREN = delay_CFGDEVCONTROLAUXPOWEREN; + assign #(out_delay) CFGDEVCONTROLCORRERRREPORTINGEN = delay_CFGDEVCONTROLCORRERRREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLENABLERO = delay_CFGDEVCONTROLENABLERO; + assign #(out_delay) CFGDEVCONTROLEXTTAGEN = delay_CFGDEVCONTROLEXTTAGEN; + assign #(out_delay) CFGDEVCONTROLFATALERRREPORTINGEN = delay_CFGDEVCONTROLFATALERRREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLMAXPAYLOAD = delay_CFGDEVCONTROLMAXPAYLOAD; + assign #(out_delay) CFGDEVCONTROLMAXREADREQ = delay_CFGDEVCONTROLMAXREADREQ; + assign #(out_delay) CFGDEVCONTROLNONFATALREPORTINGEN = delay_CFGDEVCONTROLNONFATALREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLNOSNOOPEN = delay_CFGDEVCONTROLNOSNOOPEN; + assign #(out_delay) CFGDEVCONTROLPHANTOMEN = delay_CFGDEVCONTROLPHANTOMEN; + assign #(out_delay) CFGDEVCONTROLURERRREPORTINGEN = delay_CFGDEVCONTROLURERRREPORTINGEN; + assign #(out_delay) CFGDEVSTATUSCORRERRDETECTED = delay_CFGDEVSTATUSCORRERRDETECTED; + assign #(out_delay) CFGDEVSTATUSFATALERRDETECTED = delay_CFGDEVSTATUSFATALERRDETECTED; + assign #(out_delay) CFGDEVSTATUSNONFATALERRDETECTED = delay_CFGDEVSTATUSNONFATALERRDETECTED; + assign #(out_delay) CFGDEVSTATUSURDETECTED = delay_CFGDEVSTATUSURDETECTED; + assign #(out_delay) CFGERRAERHEADERLOGSETN = delay_CFGERRAERHEADERLOGSETN; + assign #(out_delay) CFGERRCPLRDYN = delay_CFGERRCPLRDYN; + assign #(out_delay) CFGINTERRUPTDO = delay_CFGINTERRUPTDO; + assign #(out_delay) CFGINTERRUPTMMENABLE = delay_CFGINTERRUPTMMENABLE; + assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE; + assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE; + assign #(out_delay) CFGINTERRUPTMSIXFM = delay_CFGINTERRUPTMSIXFM; + assign #(out_delay) CFGINTERRUPTRDYN = delay_CFGINTERRUPTRDYN; + assign #(out_delay) CFGLINKCONTROLASPMCONTROL = delay_CFGLINKCONTROLASPMCONTROL; + assign #(out_delay) CFGLINKCONTROLAUTOBANDWIDTHINTEN = delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN; + assign #(out_delay) CFGLINKCONTROLBANDWIDTHINTEN = delay_CFGLINKCONTROLBANDWIDTHINTEN; + assign #(out_delay) CFGLINKCONTROLCLOCKPMEN = delay_CFGLINKCONTROLCLOCKPMEN; + assign #(out_delay) CFGLINKCONTROLCOMMONCLOCK = delay_CFGLINKCONTROLCOMMONCLOCK; + assign #(out_delay) CFGLINKCONTROLEXTENDEDSYNC = delay_CFGLINKCONTROLEXTENDEDSYNC; + assign #(out_delay) CFGLINKCONTROLHWAUTOWIDTHDIS = delay_CFGLINKCONTROLHWAUTOWIDTHDIS; + assign #(out_delay) CFGLINKCONTROLLINKDISABLE = delay_CFGLINKCONTROLLINKDISABLE; + assign #(out_delay) CFGLINKCONTROLRCB = delay_CFGLINKCONTROLRCB; + assign #(out_delay) CFGLINKCONTROLRETRAINLINK = delay_CFGLINKCONTROLRETRAINLINK; + assign #(out_delay) CFGLINKSTATUSAUTOBANDWIDTHSTATUS = delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + assign #(out_delay) CFGLINKSTATUSBANDWIDTHSTATUS = delay_CFGLINKSTATUSBANDWIDTHSTATUS; + assign #(out_delay) CFGLINKSTATUSCURRENTSPEED = delay_CFGLINKSTATUSCURRENTSPEED; + assign #(out_delay) CFGLINKSTATUSDLLACTIVE = delay_CFGLINKSTATUSDLLACTIVE; + assign #(out_delay) CFGLINKSTATUSLINKTRAINING = delay_CFGLINKSTATUSLINKTRAINING; + assign #(out_delay) CFGLINKSTATUSNEGOTIATEDWIDTH = delay_CFGLINKSTATUSNEGOTIATEDWIDTH; + assign #(out_delay) CFGMGMTDO = delay_CFGMGMTDO; + assign #(out_delay) CFGMGMTRDWRDONEN = delay_CFGMGMTRDWRDONEN; + assign #(out_delay) CFGMSGDATA = delay_CFGMSGDATA; + assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTA = delay_CFGMSGRECEIVEDASSERTINTA; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTB = delay_CFGMSGRECEIVEDASSERTINTB; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTC = delay_CFGMSGRECEIVEDASSERTINTC; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTD = delay_CFGMSGRECEIVEDASSERTINTD; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTA = delay_CFGMSGRECEIVEDDEASSERTINTA; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTB = delay_CFGMSGRECEIVEDDEASSERTINTB; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTC = delay_CFGMSGRECEIVEDDEASSERTINTC; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTD = delay_CFGMSGRECEIVEDDEASSERTINTD; + assign #(out_delay) CFGMSGRECEIVEDERRCOR = delay_CFGMSGRECEIVEDERRCOR; + assign #(out_delay) CFGMSGRECEIVEDERRFATAL = delay_CFGMSGRECEIVEDERRFATAL; + assign #(out_delay) CFGMSGRECEIVEDERRNONFATAL = delay_CFGMSGRECEIVEDERRNONFATAL; + assign #(out_delay) CFGMSGRECEIVEDPMASNAK = delay_CFGMSGRECEIVEDPMASNAK; + assign #(out_delay) CFGMSGRECEIVEDPMETO = delay_CFGMSGRECEIVEDPMETO; + assign #(out_delay) CFGMSGRECEIVEDPMETOACK = delay_CFGMSGRECEIVEDPMETOACK; + assign #(out_delay) CFGMSGRECEIVEDPMPME = delay_CFGMSGRECEIVEDPMPME; + assign #(out_delay) CFGMSGRECEIVEDSETSLOTPOWERLIMIT = delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + assign #(out_delay) CFGMSGRECEIVEDUNLOCK = delay_CFGMSGRECEIVEDUNLOCK; + assign #(out_delay) CFGPCIELINKSTATE = delay_CFGPCIELINKSTATE; + assign #(out_delay) CFGPMCSRPMEEN = delay_CFGPMCSRPMEEN; + assign #(out_delay) CFGPMCSRPMESTATUS = delay_CFGPMCSRPMESTATUS; + assign #(out_delay) CFGPMCSRPOWERSTATE = delay_CFGPMCSRPOWERSTATE; + assign #(out_delay) CFGPMRCVASREQL1N = delay_CFGPMRCVASREQL1N; + assign #(out_delay) CFGPMRCVENTERL1N = delay_CFGPMRCVENTERL1N; + assign #(out_delay) CFGPMRCVENTERL23N = delay_CFGPMRCVENTERL23N; + assign #(out_delay) CFGPMRCVREQACKN = delay_CFGPMRCVREQACKN; + assign #(out_delay) CFGROOTCONTROLPMEINTEN = delay_CFGROOTCONTROLPMEINTEN; + assign #(out_delay) CFGROOTCONTROLSYSERRCORRERREN = delay_CFGROOTCONTROLSYSERRCORRERREN; + assign #(out_delay) CFGROOTCONTROLSYSERRFATALERREN = delay_CFGROOTCONTROLSYSERRFATALERREN; + assign #(out_delay) CFGROOTCONTROLSYSERRNONFATALERREN = delay_CFGROOTCONTROLSYSERRNONFATALERREN; + assign #(out_delay) CFGSLOTCONTROLELECTROMECHILCTLPULSE = delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE; + assign #(out_delay) CFGTRANSACTION = delay_CFGTRANSACTION; + assign #(out_delay) CFGTRANSACTIONADDR = delay_CFGTRANSACTIONADDR; + assign #(out_delay) CFGTRANSACTIONTYPE = delay_CFGTRANSACTIONTYPE; + assign #(out_delay) CFGVCTCVCMAP = delay_CFGVCTCVCMAP; + assign #(out_delay) DBGSCLRA = delay_DBGSCLRA; + assign #(out_delay) DBGSCLRB = delay_DBGSCLRB; + assign #(out_delay) DBGSCLRC = delay_DBGSCLRC; + assign #(out_delay) DBGSCLRD = delay_DBGSCLRD; + assign #(out_delay) DBGSCLRE = delay_DBGSCLRE; + assign #(out_delay) DBGSCLRF = delay_DBGSCLRF; + assign #(out_delay) DBGSCLRG = delay_DBGSCLRG; + assign #(out_delay) DBGSCLRH = delay_DBGSCLRH; + assign #(out_delay) DBGSCLRI = delay_DBGSCLRI; + assign #(out_delay) DBGSCLRJ = delay_DBGSCLRJ; + assign #(out_delay) DBGSCLRK = delay_DBGSCLRK; + assign #(out_delay) DBGVECA = delay_DBGVECA; + assign #(out_delay) DBGVECB = delay_DBGVECB; + assign #(out_delay) DBGVECC = delay_DBGVECC; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPRDY = delay_DRPRDY; + assign #(out_delay) LL2BADDLLPERR = delay_LL2BADDLLPERR; + assign #(out_delay) LL2BADTLPERR = delay_LL2BADTLPERR; + assign #(out_delay) LL2LINKSTATUS = delay_LL2LINKSTATUS; + assign #(out_delay) LL2PROTOCOLERR = delay_LL2PROTOCOLERR; + assign #(out_delay) LL2RECEIVERERR = delay_LL2RECEIVERERR; + assign #(out_delay) LL2REPLAYROERR = delay_LL2REPLAYROERR; + assign #(out_delay) LL2REPLAYTOERR = delay_LL2REPLAYTOERR; + assign #(out_delay) LL2SUSPENDOK = delay_LL2SUSPENDOK; + assign #(out_delay) LL2TFCINIT1SEQ = delay_LL2TFCINIT1SEQ; + assign #(out_delay) LL2TFCINIT2SEQ = delay_LL2TFCINIT2SEQ; + assign #(out_delay) LL2TXIDLE = delay_LL2TXIDLE; + assign #(out_delay) LNKCLKEN = delay_LNKCLKEN; + assign #(out_delay) MIMRXRADDR = delay_MIMRXRADDR; + assign #(out_delay) MIMRXREN = delay_MIMRXREN; + assign #(out_delay) MIMRXWADDR = delay_MIMRXWADDR; + assign #(out_delay) MIMRXWDATA = delay_MIMRXWDATA; + assign #(out_delay) MIMRXWEN = delay_MIMRXWEN; + assign #(out_delay) MIMTXRADDR = delay_MIMTXRADDR; + assign #(out_delay) MIMTXREN = delay_MIMTXREN; + assign #(out_delay) MIMTXWADDR = delay_MIMTXWADDR; + assign #(out_delay) MIMTXWDATA = delay_MIMTXWDATA; + assign #(out_delay) MIMTXWEN = delay_MIMTXWEN; + assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY; + assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY; + assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY; + assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY; + assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY; + assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY; + assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY; + assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY; + assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK; + assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE; + assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA; + assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE; + assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN; + assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK; + assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE; + assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA; + assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE; + assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN; + assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK; + assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE; + assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA; + assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE; + assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN; + assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK; + assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE; + assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA; + assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE; + assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN; + assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK; + assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE; + assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA; + assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE; + assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN; + assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK; + assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE; + assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA; + assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE; + assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN; + assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK; + assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE; + assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA; + assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE; + assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN; + assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK; + assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE; + assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA; + assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE; + assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN; + assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH; + assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN; + assign #(out_delay) PIPETXRATE = delay_PIPETXRATE; + assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET; + assign #(out_delay) PIPETXRESET = delay_PIPETXRESET; + assign #(out_delay) PL2L0REQ = delay_PL2L0REQ; + assign #(out_delay) PL2LINKUP = delay_PL2LINKUP; + assign #(out_delay) PL2RECEIVERERR = delay_PL2RECEIVERERR; + assign #(out_delay) PL2RECOVERY = delay_PL2RECOVERY; + assign #(out_delay) PL2RXELECIDLE = delay_PL2RXELECIDLE; + assign #(out_delay) PL2RXPMSTATE = delay_PL2RXPMSTATE; + assign #(out_delay) PL2SUSPENDOK = delay_PL2SUSPENDOK; + assign #(out_delay) PLDBGVEC = delay_PLDBGVEC; + assign #(out_delay) PLDIRECTEDCHANGEDONE = delay_PLDIRECTEDCHANGEDONE; + assign #(out_delay) PLINITIALLINKWIDTH = delay_PLINITIALLINKWIDTH; + assign #(out_delay) PLLANEREVERSALMODE = delay_PLLANEREVERSALMODE; + assign #(out_delay) PLLINKGEN2CAP = delay_PLLINKGEN2CAP; + assign #(out_delay) PLLINKPARTNERGEN2SUPPORTED = delay_PLLINKPARTNERGEN2SUPPORTED; + assign #(out_delay) PLLINKUPCFGCAP = delay_PLLINKUPCFGCAP; + assign #(out_delay) PLLTSSMSTATE = delay_PLLTSSMSTATE; + assign #(out_delay) PLPHYLNKUPN = delay_PLPHYLNKUPN; + assign #(out_delay) PLRECEIVEDHOTRST = delay_PLRECEIVEDHOTRST; + assign #(out_delay) PLRXPMSTATE = delay_PLRXPMSTATE; + assign #(out_delay) PLSELLNKRATE = delay_PLSELLNKRATE; + assign #(out_delay) PLSELLNKWIDTH = delay_PLSELLNKWIDTH; + assign #(out_delay) PLTXPMSTATE = delay_PLTXPMSTATE; + assign #(out_delay) RECEIVEDFUNCLVLRSTN = delay_RECEIVEDFUNCLVLRSTN; + assign #(out_delay) TL2ASPMSUSPENDCREDITCHECKOK = delay_TL2ASPMSUSPENDCREDITCHECKOK; + assign #(out_delay) TL2ASPMSUSPENDREQ = delay_TL2ASPMSUSPENDREQ; + assign #(out_delay) TL2ERRFCPE = delay_TL2ERRFCPE; + assign #(out_delay) TL2ERRHDR = delay_TL2ERRHDR; + assign #(out_delay) TL2ERRMALFORMED = delay_TL2ERRMALFORMED; + assign #(out_delay) TL2ERRRXOVERFLOW = delay_TL2ERRRXOVERFLOW; + assign #(out_delay) TL2PPMSUSPENDOK = delay_TL2PPMSUSPENDOK; + assign #(out_delay) TRNFCCPLD = delay_TRNFCCPLD; + assign #(out_delay) TRNFCCPLH = delay_TRNFCCPLH; + assign #(out_delay) TRNFCNPD = delay_TRNFCNPD; + assign #(out_delay) TRNFCNPH = delay_TRNFCNPH; + assign #(out_delay) TRNFCPD = delay_TRNFCPD; + assign #(out_delay) TRNFCPH = delay_TRNFCPH; + assign #(out_delay) TRNLNKUP = delay_TRNLNKUP; + assign #(out_delay) TRNRBARHIT = delay_TRNRBARHIT; + assign #(out_delay) TRNRD = delay_TRNRD; + assign #(out_delay) TRNRDLLPDATA = delay_TRNRDLLPDATA; + assign #(out_delay) TRNRDLLPSRCRDY = delay_TRNRDLLPSRCRDY; + assign #(out_delay) TRNRECRCERR = delay_TRNRECRCERR; + assign #(out_delay) TRNREOF = delay_TRNREOF; + assign #(out_delay) TRNRERRFWD = delay_TRNRERRFWD; + assign #(out_delay) TRNRREM = delay_TRNRREM; + assign #(out_delay) TRNRSOF = delay_TRNRSOF; + assign #(out_delay) TRNRSRCDSC = delay_TRNRSRCDSC; + assign #(out_delay) TRNRSRCRDY = delay_TRNRSRCRDY; + assign #(out_delay) TRNTBUFAV = delay_TRNTBUFAV; + assign #(out_delay) TRNTCFGREQ = delay_TRNTCFGREQ; + assign #(out_delay) TRNTDLLPDSTRDY = delay_TRNTDLLPDSTRDY; + assign #(out_delay) TRNTDSTRDY = delay_TRNTDSTRDY; + assign #(out_delay) TRNTERRDROP = delay_TRNTERRDROP; + assign #(out_delay) USERRSTN = delay_USERRSTN; + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK; + assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK; + assign #(INCLK_DELAY) delay_USERCLK = USERCLK; + assign #(INCLK_DELAY) delay_USERCLK2 = USERCLK2; + + assign #(in_delay) delay_CFGAERINTERRUPTMSGNUM = CFGAERINTERRUPTMSGNUM; + assign #(in_delay) delay_CFGDEVID = CFGDEVID; + assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER; + assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER; + assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER; + assign #(in_delay) delay_CFGDSN = CFGDSN; + assign #(in_delay) delay_CFGERRACSN = CFGERRACSN; + assign #(in_delay) delay_CFGERRAERHEADERLOG = CFGERRAERHEADERLOG; + assign #(in_delay) delay_CFGERRATOMICEGRESSBLOCKEDN = CFGERRATOMICEGRESSBLOCKEDN; + assign #(in_delay) delay_CFGERRCORN = CFGERRCORN; + assign #(in_delay) delay_CFGERRCPLABORTN = CFGERRCPLABORTN; + assign #(in_delay) delay_CFGERRCPLTIMEOUTN = CFGERRCPLTIMEOUTN; + assign #(in_delay) delay_CFGERRCPLUNEXPECTN = CFGERRCPLUNEXPECTN; + assign #(in_delay) delay_CFGERRECRCN = CFGERRECRCN; + assign #(in_delay) delay_CFGERRINTERNALCORN = CFGERRINTERNALCORN; + assign #(in_delay) delay_CFGERRINTERNALUNCORN = CFGERRINTERNALUNCORN; + assign #(in_delay) delay_CFGERRLOCKEDN = CFGERRLOCKEDN; + assign #(in_delay) delay_CFGERRMALFORMEDN = CFGERRMALFORMEDN; + assign #(in_delay) delay_CFGERRMCBLOCKEDN = CFGERRMCBLOCKEDN; + assign #(in_delay) delay_CFGERRNORECOVERYN = CFGERRNORECOVERYN; + assign #(in_delay) delay_CFGERRPOISONEDN = CFGERRPOISONEDN; + assign #(in_delay) delay_CFGERRPOSTEDN = CFGERRPOSTEDN; + assign #(in_delay) delay_CFGERRTLPCPLHEADER = CFGERRTLPCPLHEADER; + assign #(in_delay) delay_CFGERRURN = CFGERRURN; + assign #(in_delay) delay_CFGFORCECOMMONCLOCKOFF = CFGFORCECOMMONCLOCKOFF; + assign #(in_delay) delay_CFGFORCEEXTENDEDSYNCON = CFGFORCEEXTENDEDSYNCON; + assign #(in_delay) delay_CFGFORCEMPS = CFGFORCEMPS; + assign #(in_delay) delay_CFGINTERRUPTASSERTN = CFGINTERRUPTASSERTN; + assign #(in_delay) delay_CFGINTERRUPTDI = CFGINTERRUPTDI; + assign #(in_delay) delay_CFGINTERRUPTN = CFGINTERRUPTN; + assign #(in_delay) delay_CFGINTERRUPTSTATN = CFGINTERRUPTSTATN; + assign #(in_delay) delay_CFGMGMTBYTEENN = CFGMGMTBYTEENN; + assign #(in_delay) delay_CFGMGMTDI = CFGMGMTDI; + assign #(in_delay) delay_CFGMGMTDWADDR = CFGMGMTDWADDR; + assign #(in_delay) delay_CFGMGMTRDENN = CFGMGMTRDENN; + assign #(in_delay) delay_CFGMGMTWRENN = CFGMGMTWRENN; + assign #(in_delay) delay_CFGMGMTWRREADONLYN = CFGMGMTWRREADONLYN; + assign #(in_delay) delay_CFGMGMTWRRW1CASRWN = CFGMGMTWRRW1CASRWN; + assign #(in_delay) delay_CFGPCIECAPINTERRUPTMSGNUM = CFGPCIECAPINTERRUPTMSGNUM; + assign #(in_delay) delay_CFGPMFORCESTATE = CFGPMFORCESTATE; + assign #(in_delay) delay_CFGPMFORCESTATEENN = CFGPMFORCESTATEENN; + assign #(in_delay) delay_CFGPMHALTASPML0SN = CFGPMHALTASPML0SN; + assign #(in_delay) delay_CFGPMHALTASPML1N = CFGPMHALTASPML1N; + assign #(in_delay) delay_CFGPMSENDPMETON = CFGPMSENDPMETON; + assign #(in_delay) delay_CFGPMTURNOFFOKN = CFGPMTURNOFFOKN; + assign #(in_delay) delay_CFGPMWAKEN = CFGPMWAKEN; + assign #(in_delay) delay_CFGPORTNUMBER = CFGPORTNUMBER; + assign #(in_delay) delay_CFGREVID = CFGREVID; + assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID; + assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID; + assign #(in_delay) delay_CFGTRNPENDINGN = CFGTRNPENDINGN; + assign #(in_delay) delay_CFGVENDID = CFGVENDID; + assign #(in_delay) delay_CMRSTN = CMRSTN; + assign #(in_delay) delay_CMSTICKYRSTN = CMSTICKYRSTN; + assign #(in_delay) delay_DBGMODE = DBGMODE; + assign #(in_delay) delay_DBGSUBMODE = DBGSUBMODE; + assign #(in_delay) delay_DLRSTN = DLRSTN; + assign #(in_delay) delay_DRPADDR = DRPADDR; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPEN = DRPEN; + assign #(in_delay) delay_DRPWE = DRPWE; + assign #(in_delay) delay_FUNCLVLRSTN = FUNCLVLRSTN; + assign #(in_delay) delay_LL2SENDASREQL1 = LL2SENDASREQL1; + assign #(in_delay) delay_LL2SENDENTERL1 = LL2SENDENTERL1; + assign #(in_delay) delay_LL2SENDENTERL23 = LL2SENDENTERL23; + assign #(in_delay) delay_LL2SENDPMACK = LL2SENDPMACK; + assign #(in_delay) delay_LL2SUSPENDNOW = LL2SUSPENDNOW; + assign #(in_delay) delay_LL2TLPRCV = LL2TLPRCV; + assign #(in_delay) delay_MIMRXRDATA = MIMRXRDATA; + assign #(in_delay) delay_MIMTXRDATA = MIMTXRDATA; + assign #(in_delay) delay_PIPERX0CHANISALIGNED = PIPERX0CHANISALIGNED; + assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK; + assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA; + assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE; + assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS; + assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS; + assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID; + assign #(in_delay) delay_PIPERX1CHANISALIGNED = PIPERX1CHANISALIGNED; + assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK; + assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA; + assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE; + assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS; + assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS; + assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID; + assign #(in_delay) delay_PIPERX2CHANISALIGNED = PIPERX2CHANISALIGNED; + assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK; + assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA; + assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE; + assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS; + assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS; + assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID; + assign #(in_delay) delay_PIPERX3CHANISALIGNED = PIPERX3CHANISALIGNED; + assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK; + assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA; + assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE; + assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS; + assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS; + assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID; + assign #(in_delay) delay_PIPERX4CHANISALIGNED = PIPERX4CHANISALIGNED; + assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK; + assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA; + assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE; + assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS; + assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS; + assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID; + assign #(in_delay) delay_PIPERX5CHANISALIGNED = PIPERX5CHANISALIGNED; + assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK; + assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA; + assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE; + assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS; + assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS; + assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID; + assign #(in_delay) delay_PIPERX6CHANISALIGNED = PIPERX6CHANISALIGNED; + assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK; + assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA; + assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE; + assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS; + assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS; + assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID; + assign #(in_delay) delay_PIPERX7CHANISALIGNED = PIPERX7CHANISALIGNED; + assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK; + assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA; + assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE; + assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS; + assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS; + assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID; + assign #(in_delay) delay_PL2DIRECTEDLSTATE = PL2DIRECTEDLSTATE; + assign #(in_delay) delay_PLDBGMODE = PLDBGMODE; + assign #(in_delay) delay_PLDIRECTEDLINKAUTON = PLDIRECTEDLINKAUTON; + assign #(in_delay) delay_PLDIRECTEDLINKCHANGE = PLDIRECTEDLINKCHANGE; + assign #(in_delay) delay_PLDIRECTEDLINKSPEED = PLDIRECTEDLINKSPEED; + assign #(in_delay) delay_PLDIRECTEDLINKWIDTH = PLDIRECTEDLINKWIDTH; + assign #(in_delay) delay_PLDIRECTEDLTSSMNEW = PLDIRECTEDLTSSMNEW; + assign #(in_delay) delay_PLDIRECTEDLTSSMNEWVLD = PLDIRECTEDLTSSMNEWVLD; + assign #(in_delay) delay_PLDIRECTEDLTSSMSTALL = PLDIRECTEDLTSSMSTALL; + assign #(in_delay) delay_PLDOWNSTREAMDEEMPHSOURCE = PLDOWNSTREAMDEEMPHSOURCE; + assign #(in_delay) delay_PLRSTN = PLRSTN; + assign #(in_delay) delay_PLTRANSMITHOTRST = PLTRANSMITHOTRST; + assign #(in_delay) delay_PLUPSTREAMPREFERDEEMPH = PLUPSTREAMPREFERDEEMPH; + assign #(in_delay) delay_SYSRSTN = SYSRSTN; + assign #(in_delay) delay_TL2ASPMSUSPENDCREDITCHECK = TL2ASPMSUSPENDCREDITCHECK; + assign #(in_delay) delay_TL2PPMSUSPENDREQ = TL2PPMSUSPENDREQ; + assign #(in_delay) delay_TLRSTN = TLRSTN; + assign #(in_delay) delay_TRNFCSEL = TRNFCSEL; + assign #(in_delay) delay_TRNRDSTRDY = TRNRDSTRDY; + assign #(in_delay) delay_TRNRFCPRET = TRNRFCPRET; + assign #(in_delay) delay_TRNRNPOK = TRNRNPOK; + assign #(in_delay) delay_TRNRNPREQ = TRNRNPREQ; + assign #(in_delay) delay_TRNTCFGGNT = TRNTCFGGNT; + assign #(in_delay) delay_TRNTD = TRNTD; + assign #(in_delay) delay_TRNTDLLPDATA = TRNTDLLPDATA; + assign #(in_delay) delay_TRNTDLLPSRCRDY = TRNTDLLPSRCRDY; + assign #(in_delay) delay_TRNTECRCGEN = TRNTECRCGEN; + assign #(in_delay) delay_TRNTEOF = TRNTEOF; + assign #(in_delay) delay_TRNTERRFWD = TRNTERRFWD; + assign #(in_delay) delay_TRNTREM = TRNTREM; + assign #(in_delay) delay_TRNTSOF = TRNTSOF; + assign #(in_delay) delay_TRNTSRCDSC = TRNTSRCDSC; + assign #(in_delay) delay_TRNTSRCRDY = TRNTSRCRDY; + assign #(in_delay) delay_TRNTSTR = TRNTSTR; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_SYSRSTN = SYSRSTN; +`endif + + B_PCIE_2_1 #( + .AER_BASE_PTR (AER_BASE_PTR), + .AER_CAP_ECRC_CHECK_CAPABLE (AER_CAP_ECRC_CHECK_CAPABLE), + .AER_CAP_ECRC_GEN_CAPABLE (AER_CAP_ECRC_GEN_CAPABLE), + .AER_CAP_ID (AER_CAP_ID), + .AER_CAP_MULTIHEADER (AER_CAP_MULTIHEADER), + .AER_CAP_NEXTPTR (AER_CAP_NEXTPTR), + .AER_CAP_ON (AER_CAP_ON), + .AER_CAP_OPTIONAL_ERR_SUPPORT (AER_CAP_OPTIONAL_ERR_SUPPORT), + .AER_CAP_PERMIT_ROOTERR_UPDATE (AER_CAP_PERMIT_ROOTERR_UPDATE), + .AER_CAP_VERSION (AER_CAP_VERSION), + .ALLOW_X8_GEN2 (ALLOW_X8_GEN2), + .BAR0 (BAR0), + .BAR1 (BAR1), + .BAR2 (BAR2), + .BAR3 (BAR3), + .BAR4 (BAR4), + .BAR5 (BAR5), + .CAPABILITIES_PTR (CAPABILITIES_PTR), + .CARDBUS_CIS_POINTER (CARDBUS_CIS_POINTER), + .CFG_ECRC_ERR_CPLSTAT (CFG_ECRC_ERR_CPLSTAT), + .CLASS_CODE (CLASS_CODE), + .CMD_INTX_IMPLEMENTED (CMD_INTX_IMPLEMENTED), + .CPL_TIMEOUT_DISABLE_SUPPORTED (CPL_TIMEOUT_DISABLE_SUPPORTED), + .CPL_TIMEOUT_RANGES_SUPPORTED (CPL_TIMEOUT_RANGES_SUPPORTED), + .CRM_MODULE_RSTS (CRM_MODULE_RSTS), + .DEV_CAP2_ARI_FORWARDING_SUPPORTED (DEV_CAP2_ARI_FORWARDING_SUPPORTED), + .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED), + .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED), + .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED), + .DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED), + .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED), + .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED), + .DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED), + .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES), + .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING), + .DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE), + .DEV_CAP_ENDPOINT_L0S_LATENCY (DEV_CAP_ENDPOINT_L0S_LATENCY), + .DEV_CAP_ENDPOINT_L1_LATENCY (DEV_CAP_ENDPOINT_L1_LATENCY), + .DEV_CAP_EXT_TAG_SUPPORTED (DEV_CAP_EXT_TAG_SUPPORTED), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED (DEV_CAP_MAX_PAYLOAD_SUPPORTED), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT), + .DEV_CAP_ROLE_BASED_ERROR (DEV_CAP_ROLE_BASED_ERROR), + .DEV_CAP_RSVD_14_12 (DEV_CAP_RSVD_14_12), + .DEV_CAP_RSVD_17_16 (DEV_CAP_RSVD_17_16), + .DEV_CAP_RSVD_31_29 (DEV_CAP_RSVD_31_29), + .DEV_CONTROL_AUX_POWER_SUPPORTED (DEV_CONTROL_AUX_POWER_SUPPORTED), + .DEV_CONTROL_EXT_TAG_DEFAULT (DEV_CONTROL_EXT_TAG_DEFAULT), + .DISABLE_ASPM_L1_TIMER (DISABLE_ASPM_L1_TIMER), + .DISABLE_BAR_FILTERING (DISABLE_BAR_FILTERING), + .DISABLE_ERR_MSG (DISABLE_ERR_MSG), + .DISABLE_ID_CHECK (DISABLE_ID_CHECK), + .DISABLE_LANE_REVERSAL (DISABLE_LANE_REVERSAL), + .DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER), + .DISABLE_PPM_FILTER (DISABLE_PPM_FILTER), + .DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP), + .DISABLE_RX_TC_FILTER (DISABLE_RX_TC_FILTER), + .DISABLE_SCRAMBLING (DISABLE_SCRAMBLING), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM), + .DSN_BASE_PTR (DSN_BASE_PTR), + .DSN_CAP_ID (DSN_CAP_ID), + .DSN_CAP_NEXTPTR (DSN_CAP_NEXTPTR), + .DSN_CAP_ON (DSN_CAP_ON), + .DSN_CAP_VERSION (DSN_CAP_VERSION), + .ENABLE_MSG_ROUTE (ENABLE_MSG_ROUTE), + .ENABLE_RX_TD_ECRC_TRIM (ENABLE_RX_TD_ECRC_TRIM), + .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED), + .ENTER_RVRY_EI_L0 (ENTER_RVRY_EI_L0), + .EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI), + .EXPANSION_ROM (EXPANSION_ROM), + .EXT_CFG_CAP_PTR (EXT_CFG_CAP_PTR), + .EXT_CFG_XP_CAP_PTR (EXT_CFG_XP_CAP_PTR), + .HEADER_TYPE (HEADER_TYPE), + .INFER_EI (INFER_EI), + .INTERRUPT_PIN (INTERRUPT_PIN), + .INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO), + .IS_SWITCH (IS_SWITCH), + .LAST_CONFIG_DWORD (LAST_CONFIG_DWORD), + .LINK_CAP_ASPM_OPTIONALITY (LINK_CAP_ASPM_OPTIONALITY), + .LINK_CAP_ASPM_SUPPORT (LINK_CAP_ASPM_SUPPORT), + .LINK_CAP_CLOCK_POWER_MANAGEMENT (LINK_CAP_CLOCK_POWER_MANAGEMENT), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_GEN1), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_GEN2), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2), + .LINK_CAP_L1_EXIT_LATENCY_GEN1 (LINK_CAP_L1_EXIT_LATENCY_GEN1), + .LINK_CAP_L1_EXIT_LATENCY_GEN2 (LINK_CAP_L1_EXIT_LATENCY_GEN2), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP), + .LINK_CAP_MAX_LINK_SPEED (LINK_CAP_MAX_LINK_SPEED), + .LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH), + .LINK_CAP_RSVD_23 (LINK_CAP_RSVD_23), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE), + .LINK_CONTROL_RCB (LINK_CONTROL_RCB), + .LINK_CTRL2_DEEMPHASIS (LINK_CTRL2_DEEMPHASIS), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE), + .LINK_CTRL2_TARGET_LINK_SPEED (LINK_CTRL2_TARGET_LINK_SPEED), + .LINK_STATUS_SLOT_CLOCK_CONFIG (LINK_STATUS_SLOT_CLOCK_CONFIG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC), + .LTSSM_MAX_LINK_WIDTH (LTSSM_MAX_LINK_WIDTH), + .MPS_FORCE (MPS_FORCE), + .MSIX_BASE_PTR (MSIX_BASE_PTR), + .MSIX_CAP_ID (MSIX_CAP_ID), + .MSIX_CAP_NEXTPTR (MSIX_CAP_NEXTPTR), + .MSIX_CAP_ON (MSIX_CAP_ON), + .MSIX_CAP_PBA_BIR (MSIX_CAP_PBA_BIR), + .MSIX_CAP_PBA_OFFSET (MSIX_CAP_PBA_OFFSET), + .MSIX_CAP_TABLE_BIR (MSIX_CAP_TABLE_BIR), + .MSIX_CAP_TABLE_OFFSET (MSIX_CAP_TABLE_OFFSET), + .MSIX_CAP_TABLE_SIZE (MSIX_CAP_TABLE_SIZE), + .MSI_BASE_PTR (MSI_BASE_PTR), + .MSI_CAP_64_BIT_ADDR_CAPABLE (MSI_CAP_64_BIT_ADDR_CAPABLE), + .MSI_CAP_ID (MSI_CAP_ID), + .MSI_CAP_MULTIMSGCAP (MSI_CAP_MULTIMSGCAP), + .MSI_CAP_MULTIMSG_EXTENSION (MSI_CAP_MULTIMSG_EXTENSION), + .MSI_CAP_NEXTPTR (MSI_CAP_NEXTPTR), + .MSI_CAP_ON (MSI_CAP_ON), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE (MSI_CAP_PER_VECTOR_MASKING_CAPABLE), + .N_FTS_COMCLK_GEN1 (N_FTS_COMCLK_GEN1), + .N_FTS_COMCLK_GEN2 (N_FTS_COMCLK_GEN2), + .N_FTS_GEN1 (N_FTS_GEN1), + .N_FTS_GEN2 (N_FTS_GEN2), + .PCIE_BASE_PTR (PCIE_BASE_PTR), + .PCIE_CAP_CAPABILITY_ID (PCIE_CAP_CAPABILITY_ID), + .PCIE_CAP_CAPABILITY_VERSION (PCIE_CAP_CAPABILITY_VERSION), + .PCIE_CAP_DEVICE_PORT_TYPE (PCIE_CAP_DEVICE_PORT_TYPE), + .PCIE_CAP_NEXTPTR (PCIE_CAP_NEXTPTR), + .PCIE_CAP_ON (PCIE_CAP_ON), + .PCIE_CAP_RSVD_15_14 (PCIE_CAP_RSVD_15_14), + .PCIE_CAP_SLOT_IMPLEMENTED (PCIE_CAP_SLOT_IMPLEMENTED), + .PCIE_REVISION (PCIE_REVISION), + .PL_AUTO_CONFIG (PL_AUTO_CONFIG), + .PL_FAST_TRAIN (PL_FAST_TRAIN), + .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT), + .PM_ASPML0S_TIMEOUT_EN (PM_ASPML0S_TIMEOUT_EN), + .PM_ASPML0S_TIMEOUT_FUNC (PM_ASPML0S_TIMEOUT_FUNC), + .PM_ASPM_FASTEXIT (PM_ASPM_FASTEXIT), + .PM_BASE_PTR (PM_BASE_PTR), + .PM_CAP_AUXCURRENT (PM_CAP_AUXCURRENT), + .PM_CAP_D1SUPPORT (PM_CAP_D1SUPPORT), + .PM_CAP_D2SUPPORT (PM_CAP_D2SUPPORT), + .PM_CAP_DSI (PM_CAP_DSI), + .PM_CAP_ID (PM_CAP_ID), + .PM_CAP_NEXTPTR (PM_CAP_NEXTPTR), + .PM_CAP_ON (PM_CAP_ON), + .PM_CAP_PMESUPPORT (PM_CAP_PMESUPPORT), + .PM_CAP_PME_CLOCK (PM_CAP_PME_CLOCK), + .PM_CAP_RSVD_04 (PM_CAP_RSVD_04), + .PM_CAP_VERSION (PM_CAP_VERSION), + .PM_CSR_B2B3 (PM_CSR_B2B3), + .PM_CSR_BPCCEN (PM_CSR_BPCCEN), + .PM_CSR_NOSOFTRST (PM_CSR_NOSOFTRST), + .PM_DATA0 (PM_DATA0), + .PM_DATA1 (PM_DATA1), + .PM_DATA2 (PM_DATA2), + .PM_DATA3 (PM_DATA3), + .PM_DATA4 (PM_DATA4), + .PM_DATA5 (PM_DATA5), + .PM_DATA6 (PM_DATA6), + .PM_DATA7 (PM_DATA7), + .PM_DATA_SCALE0 (PM_DATA_SCALE0), + .PM_DATA_SCALE1 (PM_DATA_SCALE1), + .PM_DATA_SCALE2 (PM_DATA_SCALE2), + .PM_DATA_SCALE3 (PM_DATA_SCALE3), + .PM_DATA_SCALE4 (PM_DATA_SCALE4), + .PM_DATA_SCALE5 (PM_DATA_SCALE5), + .PM_DATA_SCALE6 (PM_DATA_SCALE6), + .PM_DATA_SCALE7 (PM_DATA_SCALE7), + .PM_MF (PM_MF), + .RBAR_BASE_PTR (RBAR_BASE_PTR), + .RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0), + .RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1), + .RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2), + .RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3), + .RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4), + .RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5), + .RBAR_CAP_ID (RBAR_CAP_ID), + .RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0), + .RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1), + .RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2), + .RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3), + .RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4), + .RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5), + .RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR), + .RBAR_CAP_ON (RBAR_CAP_ON), + .RBAR_CAP_SUP0 (RBAR_CAP_SUP0), + .RBAR_CAP_SUP1 (RBAR_CAP_SUP1), + .RBAR_CAP_SUP2 (RBAR_CAP_SUP2), + .RBAR_CAP_SUP3 (RBAR_CAP_SUP3), + .RBAR_CAP_SUP4 (RBAR_CAP_SUP4), + .RBAR_CAP_SUP5 (RBAR_CAP_SUP5), + .RBAR_CAP_VERSION (RBAR_CAP_VERSION), + .RBAR_NUM (RBAR_NUM), + .RECRC_CHK (RECRC_CHK), + .RECRC_CHK_TRIM (RECRC_CHK_TRIM), + .ROOT_CAP_CRS_SW_VISIBILITY (ROOT_CAP_CRS_SW_VISIBILITY), + .RP_AUTO_SPD (RP_AUTO_SPD), + .RP_AUTO_SPD_LOOPCNT (RP_AUTO_SPD_LOOPCNT), + .SELECT_DLL_IF (SELECT_DLL_IF), + .SIM_VERSION (SIM_VERSION), + .SLOT_CAP_ATT_BUTTON_PRESENT (SLOT_CAP_ATT_BUTTON_PRESENT), + .SLOT_CAP_ATT_INDICATOR_PRESENT (SLOT_CAP_ATT_INDICATOR_PRESENT), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT (SLOT_CAP_ELEC_INTERLOCK_PRESENT), + .SLOT_CAP_HOTPLUG_CAPABLE (SLOT_CAP_HOTPLUG_CAPABLE), + .SLOT_CAP_HOTPLUG_SURPRISE (SLOT_CAP_HOTPLUG_SURPRISE), + .SLOT_CAP_MRL_SENSOR_PRESENT (SLOT_CAP_MRL_SENSOR_PRESENT), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT), + .SLOT_CAP_PHYSICAL_SLOT_NUM (SLOT_CAP_PHYSICAL_SLOT_NUM), + .SLOT_CAP_POWER_CONTROLLER_PRESENT (SLOT_CAP_POWER_CONTROLLER_PRESENT), + .SLOT_CAP_POWER_INDICATOR_PRESENT (SLOT_CAP_POWER_INDICATOR_PRESENT), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE (SLOT_CAP_SLOT_POWER_LIMIT_SCALE), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE (SLOT_CAP_SLOT_POWER_LIMIT_VALUE), + .SPARE_BIT0 (SPARE_BIT0), + .SPARE_BIT1 (SPARE_BIT1), + .SPARE_BIT2 (SPARE_BIT2), + .SPARE_BIT3 (SPARE_BIT3), + .SPARE_BIT4 (SPARE_BIT4), + .SPARE_BIT5 (SPARE_BIT5), + .SPARE_BIT6 (SPARE_BIT6), + .SPARE_BIT7 (SPARE_BIT7), + .SPARE_BIT8 (SPARE_BIT8), + .SPARE_BYTE0 (SPARE_BYTE0), + .SPARE_BYTE1 (SPARE_BYTE1), + .SPARE_BYTE2 (SPARE_BYTE2), + .SPARE_BYTE3 (SPARE_BYTE3), + .SPARE_WORD0 (SPARE_WORD0), + .SPARE_WORD1 (SPARE_WORD1), + .SPARE_WORD2 (SPARE_WORD2), + .SPARE_WORD3 (SPARE_WORD3), + .SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO), + .TECRC_EP_INV (TECRC_EP_INV), + .TL_RBYPASS (TL_RBYPASS), + .TL_RX_RAM_RADDR_LATENCY (TL_RX_RAM_RADDR_LATENCY), + .TL_RX_RAM_RDATA_LATENCY (TL_RX_RAM_RDATA_LATENCY), + .TL_RX_RAM_WRITE_LATENCY (TL_RX_RAM_WRITE_LATENCY), + .TL_TFC_DISABLE (TL_TFC_DISABLE), + .TL_TX_CHECKS_DISABLE (TL_TX_CHECKS_DISABLE), + .TL_TX_RAM_RADDR_LATENCY (TL_TX_RAM_RADDR_LATENCY), + .TL_TX_RAM_RDATA_LATENCY (TL_TX_RAM_RDATA_LATENCY), + .TL_TX_RAM_WRITE_LATENCY (TL_TX_RAM_WRITE_LATENCY), + .TRN_DW (TRN_DW), + .TRN_NP_FC (TRN_NP_FC), + .UPCONFIG_CAPABLE (UPCONFIG_CAPABLE), + .UPSTREAM_FACING (UPSTREAM_FACING), + .UR_ATOMIC (UR_ATOMIC), + .UR_CFG1 (UR_CFG1), + .UR_INV_REQ (UR_INV_REQ), + .UR_PRS_RESPONSE (UR_PRS_RESPONSE), + .USER_CLK2_DIV2 (USER_CLK2_DIV2), + .USER_CLK_FREQ (USER_CLK_FREQ), + .USE_RID_PINS (USE_RID_PINS), + .VC0_CPL_INFINITE (VC0_CPL_INFINITE), + .VC0_RX_RAM_LIMIT (VC0_RX_RAM_LIMIT), + .VC0_TOTAL_CREDITS_CD (VC0_TOTAL_CREDITS_CD), + .VC0_TOTAL_CREDITS_CH (VC0_TOTAL_CREDITS_CH), + .VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD), + .VC0_TOTAL_CREDITS_NPH (VC0_TOTAL_CREDITS_NPH), + .VC0_TOTAL_CREDITS_PD (VC0_TOTAL_CREDITS_PD), + .VC0_TOTAL_CREDITS_PH (VC0_TOTAL_CREDITS_PH), + .VC0_TX_LASTPACKET (VC0_TX_LASTPACKET), + .VC_BASE_PTR (VC_BASE_PTR), + .VC_CAP_ID (VC_CAP_ID), + .VC_CAP_NEXTPTR (VC_CAP_NEXTPTR), + .VC_CAP_ON (VC_CAP_ON), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS (VC_CAP_REJECT_SNOOP_TRANSACTIONS), + .VC_CAP_VERSION (VC_CAP_VERSION), + .VSEC_BASE_PTR (VSEC_BASE_PTR), + .VSEC_CAP_HDR_ID (VSEC_CAP_HDR_ID), + .VSEC_CAP_HDR_LENGTH (VSEC_CAP_HDR_LENGTH), + .VSEC_CAP_HDR_REVISION (VSEC_CAP_HDR_REVISION), + .VSEC_CAP_ID (VSEC_CAP_ID), + .VSEC_CAP_IS_LINK_VISIBLE (VSEC_CAP_IS_LINK_VISIBLE), + .VSEC_CAP_NEXTPTR (VSEC_CAP_NEXTPTR), + .VSEC_CAP_ON (VSEC_CAP_ON), + .VSEC_CAP_VERSION (VSEC_CAP_VERSION)) + + B_PCIE_2_1_INST ( + .CFGAERECRCCHECKEN (delay_CFGAERECRCCHECKEN), + .CFGAERECRCGENEN (delay_CFGAERECRCGENEN), + .CFGAERROOTERRCORRERRRECEIVED (delay_CFGAERROOTERRCORRERRRECEIVED), + .CFGAERROOTERRCORRERRREPORTINGEN (delay_CFGAERROOTERRCORRERRREPORTINGEN), + .CFGAERROOTERRFATALERRRECEIVED (delay_CFGAERROOTERRFATALERRRECEIVED), + .CFGAERROOTERRFATALERRREPORTINGEN (delay_CFGAERROOTERRFATALERRREPORTINGEN), + .CFGAERROOTERRNONFATALERRRECEIVED (delay_CFGAERROOTERRNONFATALERRRECEIVED), + .CFGAERROOTERRNONFATALERRREPORTINGEN (delay_CFGAERROOTERRNONFATALERRREPORTINGEN), + .CFGBRIDGESERREN (delay_CFGBRIDGESERREN), + .CFGCOMMANDBUSMASTERENABLE (delay_CFGCOMMANDBUSMASTERENABLE), + .CFGCOMMANDINTERRUPTDISABLE (delay_CFGCOMMANDINTERRUPTDISABLE), + .CFGCOMMANDIOENABLE (delay_CFGCOMMANDIOENABLE), + .CFGCOMMANDMEMENABLE (delay_CFGCOMMANDMEMENABLE), + .CFGCOMMANDSERREN (delay_CFGCOMMANDSERREN), + .CFGDEVCONTROL2ARIFORWARDEN (delay_CFGDEVCONTROL2ARIFORWARDEN), + .CFGDEVCONTROL2ATOMICEGRESSBLOCK (delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK), + .CFGDEVCONTROL2ATOMICREQUESTEREN (delay_CFGDEVCONTROL2ATOMICREQUESTEREN), + .CFGDEVCONTROL2CPLTIMEOUTDIS (delay_CFGDEVCONTROL2CPLTIMEOUTDIS), + .CFGDEVCONTROL2CPLTIMEOUTVAL (delay_CFGDEVCONTROL2CPLTIMEOUTVAL), + .CFGDEVCONTROL2IDOCPLEN (delay_CFGDEVCONTROL2IDOCPLEN), + .CFGDEVCONTROL2IDOREQEN (delay_CFGDEVCONTROL2IDOREQEN), + .CFGDEVCONTROL2LTREN (delay_CFGDEVCONTROL2LTREN), + .CFGDEVCONTROL2TLPPREFIXBLOCK (delay_CFGDEVCONTROL2TLPPREFIXBLOCK), + .CFGDEVCONTROLAUXPOWEREN (delay_CFGDEVCONTROLAUXPOWEREN), + .CFGDEVCONTROLCORRERRREPORTINGEN (delay_CFGDEVCONTROLCORRERRREPORTINGEN), + .CFGDEVCONTROLENABLERO (delay_CFGDEVCONTROLENABLERO), + .CFGDEVCONTROLEXTTAGEN (delay_CFGDEVCONTROLEXTTAGEN), + .CFGDEVCONTROLFATALERRREPORTINGEN (delay_CFGDEVCONTROLFATALERRREPORTINGEN), + .CFGDEVCONTROLMAXPAYLOAD (delay_CFGDEVCONTROLMAXPAYLOAD), + .CFGDEVCONTROLMAXREADREQ (delay_CFGDEVCONTROLMAXREADREQ), + .CFGDEVCONTROLNONFATALREPORTINGEN (delay_CFGDEVCONTROLNONFATALREPORTINGEN), + .CFGDEVCONTROLNOSNOOPEN (delay_CFGDEVCONTROLNOSNOOPEN), + .CFGDEVCONTROLPHANTOMEN (delay_CFGDEVCONTROLPHANTOMEN), + .CFGDEVCONTROLURERRREPORTINGEN (delay_CFGDEVCONTROLURERRREPORTINGEN), + .CFGDEVSTATUSCORRERRDETECTED (delay_CFGDEVSTATUSCORRERRDETECTED), + .CFGDEVSTATUSFATALERRDETECTED (delay_CFGDEVSTATUSFATALERRDETECTED), + .CFGDEVSTATUSNONFATALERRDETECTED (delay_CFGDEVSTATUSNONFATALERRDETECTED), + .CFGDEVSTATUSURDETECTED (delay_CFGDEVSTATUSURDETECTED), + .CFGERRAERHEADERLOGSETN (delay_CFGERRAERHEADERLOGSETN), + .CFGERRCPLRDYN (delay_CFGERRCPLRDYN), + .CFGINTERRUPTDO (delay_CFGINTERRUPTDO), + .CFGINTERRUPTMMENABLE (delay_CFGINTERRUPTMMENABLE), + .CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE), + .CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE), + .CFGINTERRUPTMSIXFM (delay_CFGINTERRUPTMSIXFM), + .CFGINTERRUPTRDYN (delay_CFGINTERRUPTRDYN), + .CFGLINKCONTROLASPMCONTROL (delay_CFGLINKCONTROLASPMCONTROL), + .CFGLINKCONTROLAUTOBANDWIDTHINTEN (delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN), + .CFGLINKCONTROLBANDWIDTHINTEN (delay_CFGLINKCONTROLBANDWIDTHINTEN), + .CFGLINKCONTROLCLOCKPMEN (delay_CFGLINKCONTROLCLOCKPMEN), + .CFGLINKCONTROLCOMMONCLOCK (delay_CFGLINKCONTROLCOMMONCLOCK), + .CFGLINKCONTROLEXTENDEDSYNC (delay_CFGLINKCONTROLEXTENDEDSYNC), + .CFGLINKCONTROLHWAUTOWIDTHDIS (delay_CFGLINKCONTROLHWAUTOWIDTHDIS), + .CFGLINKCONTROLLINKDISABLE (delay_CFGLINKCONTROLLINKDISABLE), + .CFGLINKCONTROLRCB (delay_CFGLINKCONTROLRCB), + .CFGLINKCONTROLRETRAINLINK (delay_CFGLINKCONTROLRETRAINLINK), + .CFGLINKSTATUSAUTOBANDWIDTHSTATUS (delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS), + .CFGLINKSTATUSBANDWIDTHSTATUS (delay_CFGLINKSTATUSBANDWIDTHSTATUS), + .CFGLINKSTATUSCURRENTSPEED (delay_CFGLINKSTATUSCURRENTSPEED), + .CFGLINKSTATUSDLLACTIVE (delay_CFGLINKSTATUSDLLACTIVE), + .CFGLINKSTATUSLINKTRAINING (delay_CFGLINKSTATUSLINKTRAINING), + .CFGLINKSTATUSNEGOTIATEDWIDTH (delay_CFGLINKSTATUSNEGOTIATEDWIDTH), + .CFGMGMTDO (delay_CFGMGMTDO), + .CFGMGMTRDWRDONEN (delay_CFGMGMTRDWRDONEN), + .CFGMSGDATA (delay_CFGMSGDATA), + .CFGMSGRECEIVED (delay_CFGMSGRECEIVED), + .CFGMSGRECEIVEDASSERTINTA (delay_CFGMSGRECEIVEDASSERTINTA), + .CFGMSGRECEIVEDASSERTINTB (delay_CFGMSGRECEIVEDASSERTINTB), + .CFGMSGRECEIVEDASSERTINTC (delay_CFGMSGRECEIVEDASSERTINTC), + .CFGMSGRECEIVEDASSERTINTD (delay_CFGMSGRECEIVEDASSERTINTD), + .CFGMSGRECEIVEDDEASSERTINTA (delay_CFGMSGRECEIVEDDEASSERTINTA), + .CFGMSGRECEIVEDDEASSERTINTB (delay_CFGMSGRECEIVEDDEASSERTINTB), + .CFGMSGRECEIVEDDEASSERTINTC (delay_CFGMSGRECEIVEDDEASSERTINTC), + .CFGMSGRECEIVEDDEASSERTINTD (delay_CFGMSGRECEIVEDDEASSERTINTD), + .CFGMSGRECEIVEDERRCOR (delay_CFGMSGRECEIVEDERRCOR), + .CFGMSGRECEIVEDERRFATAL (delay_CFGMSGRECEIVEDERRFATAL), + .CFGMSGRECEIVEDERRNONFATAL (delay_CFGMSGRECEIVEDERRNONFATAL), + .CFGMSGRECEIVEDPMASNAK (delay_CFGMSGRECEIVEDPMASNAK), + .CFGMSGRECEIVEDPMETO (delay_CFGMSGRECEIVEDPMETO), + .CFGMSGRECEIVEDPMETOACK (delay_CFGMSGRECEIVEDPMETOACK), + .CFGMSGRECEIVEDPMPME (delay_CFGMSGRECEIVEDPMPME), + .CFGMSGRECEIVEDSETSLOTPOWERLIMIT (delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT), + .CFGMSGRECEIVEDUNLOCK (delay_CFGMSGRECEIVEDUNLOCK), + .CFGPCIELINKSTATE (delay_CFGPCIELINKSTATE), + .CFGPMCSRPMEEN (delay_CFGPMCSRPMEEN), + .CFGPMCSRPMESTATUS (delay_CFGPMCSRPMESTATUS), + .CFGPMCSRPOWERSTATE (delay_CFGPMCSRPOWERSTATE), + .CFGPMRCVASREQL1N (delay_CFGPMRCVASREQL1N), + .CFGPMRCVENTERL1N (delay_CFGPMRCVENTERL1N), + .CFGPMRCVENTERL23N (delay_CFGPMRCVENTERL23N), + .CFGPMRCVREQACKN (delay_CFGPMRCVREQACKN), + .CFGROOTCONTROLPMEINTEN (delay_CFGROOTCONTROLPMEINTEN), + .CFGROOTCONTROLSYSERRCORRERREN (delay_CFGROOTCONTROLSYSERRCORRERREN), + .CFGROOTCONTROLSYSERRFATALERREN (delay_CFGROOTCONTROLSYSERRFATALERREN), + .CFGROOTCONTROLSYSERRNONFATALERREN (delay_CFGROOTCONTROLSYSERRNONFATALERREN), + .CFGSLOTCONTROLELECTROMECHILCTLPULSE (delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE), + .CFGTRANSACTION (delay_CFGTRANSACTION), + .CFGTRANSACTIONADDR (delay_CFGTRANSACTIONADDR), + .CFGTRANSACTIONTYPE (delay_CFGTRANSACTIONTYPE), + .CFGVCTCVCMAP (delay_CFGVCTCVCMAP), + .DBGSCLRA (delay_DBGSCLRA), + .DBGSCLRB (delay_DBGSCLRB), + .DBGSCLRC (delay_DBGSCLRC), + .DBGSCLRD (delay_DBGSCLRD), + .DBGSCLRE (delay_DBGSCLRE), + .DBGSCLRF (delay_DBGSCLRF), + .DBGSCLRG (delay_DBGSCLRG), + .DBGSCLRH (delay_DBGSCLRH), + .DBGSCLRI (delay_DBGSCLRI), + .DBGSCLRJ (delay_DBGSCLRJ), + .DBGSCLRK (delay_DBGSCLRK), + .DBGVECA (delay_DBGVECA), + .DBGVECB (delay_DBGVECB), + .DBGVECC (delay_DBGVECC), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .LL2BADDLLPERR (delay_LL2BADDLLPERR), + .LL2BADTLPERR (delay_LL2BADTLPERR), + .LL2LINKSTATUS (delay_LL2LINKSTATUS), + .LL2PROTOCOLERR (delay_LL2PROTOCOLERR), + .LL2RECEIVERERR (delay_LL2RECEIVERERR), + .LL2REPLAYROERR (delay_LL2REPLAYROERR), + .LL2REPLAYTOERR (delay_LL2REPLAYTOERR), + .LL2SUSPENDOK (delay_LL2SUSPENDOK), + .LL2TFCINIT1SEQ (delay_LL2TFCINIT1SEQ), + .LL2TFCINIT2SEQ (delay_LL2TFCINIT2SEQ), + .LL2TXIDLE (delay_LL2TXIDLE), + .LNKCLKEN (delay_LNKCLKEN), + .MIMRXRADDR (delay_MIMRXRADDR), + .MIMRXREN (delay_MIMRXREN), + .MIMRXWADDR (delay_MIMRXWADDR), + .MIMRXWDATA (delay_MIMRXWDATA), + .MIMRXWEN (delay_MIMRXWEN), + .MIMTXRADDR (delay_MIMTXRADDR), + .MIMTXREN (delay_MIMTXREN), + .MIMTXWADDR (delay_MIMTXWADDR), + .MIMTXWDATA (delay_MIMTXWDATA), + .MIMTXWEN (delay_MIMTXWEN), + .PIPERX0POLARITY (delay_PIPERX0POLARITY), + .PIPERX1POLARITY (delay_PIPERX1POLARITY), + .PIPERX2POLARITY (delay_PIPERX2POLARITY), + .PIPERX3POLARITY (delay_PIPERX3POLARITY), + .PIPERX4POLARITY (delay_PIPERX4POLARITY), + .PIPERX5POLARITY (delay_PIPERX5POLARITY), + .PIPERX6POLARITY (delay_PIPERX6POLARITY), + .PIPERX7POLARITY (delay_PIPERX7POLARITY), + .PIPETX0CHARISK (delay_PIPETX0CHARISK), + .PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE), + .PIPETX0DATA (delay_PIPETX0DATA), + .PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE), + .PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN), + .PIPETX1CHARISK (delay_PIPETX1CHARISK), + .PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE), + .PIPETX1DATA (delay_PIPETX1DATA), + .PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE), + .PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN), + .PIPETX2CHARISK (delay_PIPETX2CHARISK), + .PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE), + .PIPETX2DATA (delay_PIPETX2DATA), + .PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE), + .PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN), + .PIPETX3CHARISK (delay_PIPETX3CHARISK), + .PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE), + .PIPETX3DATA (delay_PIPETX3DATA), + .PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE), + .PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN), + .PIPETX4CHARISK (delay_PIPETX4CHARISK), + .PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE), + .PIPETX4DATA (delay_PIPETX4DATA), + .PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE), + .PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN), + .PIPETX5CHARISK (delay_PIPETX5CHARISK), + .PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE), + .PIPETX5DATA (delay_PIPETX5DATA), + .PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE), + .PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN), + .PIPETX6CHARISK (delay_PIPETX6CHARISK), + .PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE), + .PIPETX6DATA (delay_PIPETX6DATA), + .PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE), + .PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN), + .PIPETX7CHARISK (delay_PIPETX7CHARISK), + .PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE), + .PIPETX7DATA (delay_PIPETX7DATA), + .PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE), + .PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN), + .PIPETXDEEMPH (delay_PIPETXDEEMPH), + .PIPETXMARGIN (delay_PIPETXMARGIN), + .PIPETXRATE (delay_PIPETXRATE), + .PIPETXRCVRDET (delay_PIPETXRCVRDET), + .PIPETXRESET (delay_PIPETXRESET), + .PL2L0REQ (delay_PL2L0REQ), + .PL2LINKUP (delay_PL2LINKUP), + .PL2RECEIVERERR (delay_PL2RECEIVERERR), + .PL2RECOVERY (delay_PL2RECOVERY), + .PL2RXELECIDLE (delay_PL2RXELECIDLE), + .PL2RXPMSTATE (delay_PL2RXPMSTATE), + .PL2SUSPENDOK (delay_PL2SUSPENDOK), + .PLDBGVEC (delay_PLDBGVEC), + .PLDIRECTEDCHANGEDONE (delay_PLDIRECTEDCHANGEDONE), + .PLINITIALLINKWIDTH (delay_PLINITIALLINKWIDTH), + .PLLANEREVERSALMODE (delay_PLLANEREVERSALMODE), + .PLLINKGEN2CAP (delay_PLLINKGEN2CAP), + .PLLINKPARTNERGEN2SUPPORTED (delay_PLLINKPARTNERGEN2SUPPORTED), + .PLLINKUPCFGCAP (delay_PLLINKUPCFGCAP), + .PLLTSSMSTATE (delay_PLLTSSMSTATE), + .PLPHYLNKUPN (delay_PLPHYLNKUPN), + .PLRECEIVEDHOTRST (delay_PLRECEIVEDHOTRST), + .PLRXPMSTATE (delay_PLRXPMSTATE), + .PLSELLNKRATE (delay_PLSELLNKRATE), + .PLSELLNKWIDTH (delay_PLSELLNKWIDTH), + .PLTXPMSTATE (delay_PLTXPMSTATE), + .RECEIVEDFUNCLVLRSTN (delay_RECEIVEDFUNCLVLRSTN), + .TL2ASPMSUSPENDCREDITCHECKOK (delay_TL2ASPMSUSPENDCREDITCHECKOK), + .TL2ASPMSUSPENDREQ (delay_TL2ASPMSUSPENDREQ), + .TL2ERRFCPE (delay_TL2ERRFCPE), + .TL2ERRHDR (delay_TL2ERRHDR), + .TL2ERRMALFORMED (delay_TL2ERRMALFORMED), + .TL2ERRRXOVERFLOW (delay_TL2ERRRXOVERFLOW), + .TL2PPMSUSPENDOK (delay_TL2PPMSUSPENDOK), + .TRNFCCPLD (delay_TRNFCCPLD), + .TRNFCCPLH (delay_TRNFCCPLH), + .TRNFCNPD (delay_TRNFCNPD), + .TRNFCNPH (delay_TRNFCNPH), + .TRNFCPD (delay_TRNFCPD), + .TRNFCPH (delay_TRNFCPH), + .TRNLNKUP (delay_TRNLNKUP), + .TRNRBARHIT (delay_TRNRBARHIT), + .TRNRD (delay_TRNRD), + .TRNRDLLPDATA (delay_TRNRDLLPDATA), + .TRNRDLLPSRCRDY (delay_TRNRDLLPSRCRDY), + .TRNRECRCERR (delay_TRNRECRCERR), + .TRNREOF (delay_TRNREOF), + .TRNRERRFWD (delay_TRNRERRFWD), + .TRNRREM (delay_TRNRREM), + .TRNRSOF (delay_TRNRSOF), + .TRNRSRCDSC (delay_TRNRSRCDSC), + .TRNRSRCRDY (delay_TRNRSRCRDY), + .TRNTBUFAV (delay_TRNTBUFAV), + .TRNTCFGREQ (delay_TRNTCFGREQ), + .TRNTDLLPDSTRDY (delay_TRNTDLLPDSTRDY), + .TRNTDSTRDY (delay_TRNTDSTRDY), + .TRNTERRDROP (delay_TRNTERRDROP), + .USERRSTN (delay_USERRSTN), + .CFGAERINTERRUPTMSGNUM (delay_CFGAERINTERRUPTMSGNUM), + .CFGDEVID (delay_CFGDEVID), + .CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER), + .CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER), + .CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER), + .CFGDSN (delay_CFGDSN), + .CFGERRACSN (delay_CFGERRACSN), + .CFGERRAERHEADERLOG (delay_CFGERRAERHEADERLOG), + .CFGERRATOMICEGRESSBLOCKEDN (delay_CFGERRATOMICEGRESSBLOCKEDN), + .CFGERRCORN (delay_CFGERRCORN), + .CFGERRCPLABORTN (delay_CFGERRCPLABORTN), + .CFGERRCPLTIMEOUTN (delay_CFGERRCPLTIMEOUTN), + .CFGERRCPLUNEXPECTN (delay_CFGERRCPLUNEXPECTN), + .CFGERRECRCN (delay_CFGERRECRCN), + .CFGERRINTERNALCORN (delay_CFGERRINTERNALCORN), + .CFGERRINTERNALUNCORN (delay_CFGERRINTERNALUNCORN), + .CFGERRLOCKEDN (delay_CFGERRLOCKEDN), + .CFGERRMALFORMEDN (delay_CFGERRMALFORMEDN), + .CFGERRMCBLOCKEDN (delay_CFGERRMCBLOCKEDN), + .CFGERRNORECOVERYN (delay_CFGERRNORECOVERYN), + .CFGERRPOISONEDN (delay_CFGERRPOISONEDN), + .CFGERRPOSTEDN (delay_CFGERRPOSTEDN), + .CFGERRTLPCPLHEADER (delay_CFGERRTLPCPLHEADER), + .CFGERRURN (delay_CFGERRURN), + .CFGFORCECOMMONCLOCKOFF (delay_CFGFORCECOMMONCLOCKOFF), + .CFGFORCEEXTENDEDSYNCON (delay_CFGFORCEEXTENDEDSYNCON), + .CFGFORCEMPS (delay_CFGFORCEMPS), + .CFGINTERRUPTASSERTN (delay_CFGINTERRUPTASSERTN), + .CFGINTERRUPTDI (delay_CFGINTERRUPTDI), + .CFGINTERRUPTN (delay_CFGINTERRUPTN), + .CFGINTERRUPTSTATN (delay_CFGINTERRUPTSTATN), + .CFGMGMTBYTEENN (delay_CFGMGMTBYTEENN), + .CFGMGMTDI (delay_CFGMGMTDI), + .CFGMGMTDWADDR (delay_CFGMGMTDWADDR), + .CFGMGMTRDENN (delay_CFGMGMTRDENN), + .CFGMGMTWRENN (delay_CFGMGMTWRENN), + .CFGMGMTWRREADONLYN (delay_CFGMGMTWRREADONLYN), + .CFGMGMTWRRW1CASRWN (delay_CFGMGMTWRRW1CASRWN), + .CFGPCIECAPINTERRUPTMSGNUM (delay_CFGPCIECAPINTERRUPTMSGNUM), + .CFGPMFORCESTATE (delay_CFGPMFORCESTATE), + .CFGPMFORCESTATEENN (delay_CFGPMFORCESTATEENN), + .CFGPMHALTASPML0SN (delay_CFGPMHALTASPML0SN), + .CFGPMHALTASPML1N (delay_CFGPMHALTASPML1N), + .CFGPMSENDPMETON (delay_CFGPMSENDPMETON), + .CFGPMTURNOFFOKN (delay_CFGPMTURNOFFOKN), + .CFGPMWAKEN (delay_CFGPMWAKEN), + .CFGPORTNUMBER (delay_CFGPORTNUMBER), + .CFGREVID (delay_CFGREVID), + .CFGSUBSYSID (delay_CFGSUBSYSID), + .CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID), + .CFGTRNPENDINGN (delay_CFGTRNPENDINGN), + .CFGVENDID (delay_CFGVENDID), + .CMRSTN (delay_CMRSTN), + .CMSTICKYRSTN (delay_CMSTICKYRSTN), + .DBGMODE (delay_DBGMODE), + .DBGSUBMODE (delay_DBGSUBMODE), + .DLRSTN (delay_DLRSTN), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .FUNCLVLRSTN (delay_FUNCLVLRSTN), + .LL2SENDASREQL1 (delay_LL2SENDASREQL1), + .LL2SENDENTERL1 (delay_LL2SENDENTERL1), + .LL2SENDENTERL23 (delay_LL2SENDENTERL23), + .LL2SENDPMACK (delay_LL2SENDPMACK), + .LL2SUSPENDNOW (delay_LL2SUSPENDNOW), + .LL2TLPRCV (delay_LL2TLPRCV), + .MIMRXRDATA (delay_MIMRXRDATA), + .MIMTXRDATA (delay_MIMTXRDATA), + .PIPECLK (delay_PIPECLK), + .PIPERX0CHANISALIGNED (delay_PIPERX0CHANISALIGNED), + .PIPERX0CHARISK (delay_PIPERX0CHARISK), + .PIPERX0DATA (delay_PIPERX0DATA), + .PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE), + .PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS), + .PIPERX0STATUS (delay_PIPERX0STATUS), + .PIPERX0VALID (delay_PIPERX0VALID), + .PIPERX1CHANISALIGNED (delay_PIPERX1CHANISALIGNED), + .PIPERX1CHARISK (delay_PIPERX1CHARISK), + .PIPERX1DATA (delay_PIPERX1DATA), + .PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE), + .PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS), + .PIPERX1STATUS (delay_PIPERX1STATUS), + .PIPERX1VALID (delay_PIPERX1VALID), + .PIPERX2CHANISALIGNED (delay_PIPERX2CHANISALIGNED), + .PIPERX2CHARISK (delay_PIPERX2CHARISK), + .PIPERX2DATA (delay_PIPERX2DATA), + .PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE), + .PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS), + .PIPERX2STATUS (delay_PIPERX2STATUS), + .PIPERX2VALID (delay_PIPERX2VALID), + .PIPERX3CHANISALIGNED (delay_PIPERX3CHANISALIGNED), + .PIPERX3CHARISK (delay_PIPERX3CHARISK), + .PIPERX3DATA (delay_PIPERX3DATA), + .PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE), + .PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS), + .PIPERX3STATUS (delay_PIPERX3STATUS), + .PIPERX3VALID (delay_PIPERX3VALID), + .PIPERX4CHANISALIGNED (delay_PIPERX4CHANISALIGNED), + .PIPERX4CHARISK (delay_PIPERX4CHARISK), + .PIPERX4DATA (delay_PIPERX4DATA), + .PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE), + .PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS), + .PIPERX4STATUS (delay_PIPERX4STATUS), + .PIPERX4VALID (delay_PIPERX4VALID), + .PIPERX5CHANISALIGNED (delay_PIPERX5CHANISALIGNED), + .PIPERX5CHARISK (delay_PIPERX5CHARISK), + .PIPERX5DATA (delay_PIPERX5DATA), + .PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE), + .PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS), + .PIPERX5STATUS (delay_PIPERX5STATUS), + .PIPERX5VALID (delay_PIPERX5VALID), + .PIPERX6CHANISALIGNED (delay_PIPERX6CHANISALIGNED), + .PIPERX6CHARISK (delay_PIPERX6CHARISK), + .PIPERX6DATA (delay_PIPERX6DATA), + .PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE), + .PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS), + .PIPERX6STATUS (delay_PIPERX6STATUS), + .PIPERX6VALID (delay_PIPERX6VALID), + .PIPERX7CHANISALIGNED (delay_PIPERX7CHANISALIGNED), + .PIPERX7CHARISK (delay_PIPERX7CHARISK), + .PIPERX7DATA (delay_PIPERX7DATA), + .PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE), + .PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS), + .PIPERX7STATUS (delay_PIPERX7STATUS), + .PIPERX7VALID (delay_PIPERX7VALID), + .PL2DIRECTEDLSTATE (delay_PL2DIRECTEDLSTATE), + .PLDBGMODE (delay_PLDBGMODE), + .PLDIRECTEDLINKAUTON (delay_PLDIRECTEDLINKAUTON), + .PLDIRECTEDLINKCHANGE (delay_PLDIRECTEDLINKCHANGE), + .PLDIRECTEDLINKSPEED (delay_PLDIRECTEDLINKSPEED), + .PLDIRECTEDLINKWIDTH (delay_PLDIRECTEDLINKWIDTH), + .PLDIRECTEDLTSSMNEW (delay_PLDIRECTEDLTSSMNEW), + .PLDIRECTEDLTSSMNEWVLD (delay_PLDIRECTEDLTSSMNEWVLD), + .PLDIRECTEDLTSSMSTALL (delay_PLDIRECTEDLTSSMSTALL), + .PLDOWNSTREAMDEEMPHSOURCE (delay_PLDOWNSTREAMDEEMPHSOURCE), + .PLRSTN (delay_PLRSTN), + .PLTRANSMITHOTRST (delay_PLTRANSMITHOTRST), + .PLUPSTREAMPREFERDEEMPH (delay_PLUPSTREAMPREFERDEEMPH), + .SYSRSTN (delay_SYSRSTN), + .TL2ASPMSUSPENDCREDITCHECK (delay_TL2ASPMSUSPENDCREDITCHECK), + .TL2PPMSUSPENDREQ (delay_TL2PPMSUSPENDREQ), + .TLRSTN (delay_TLRSTN), + .TRNFCSEL (delay_TRNFCSEL), + .TRNRDSTRDY (delay_TRNRDSTRDY), + .TRNRFCPRET (delay_TRNRFCPRET), + .TRNRNPOK (delay_TRNRNPOK), + .TRNRNPREQ (delay_TRNRNPREQ), + .TRNTCFGGNT (delay_TRNTCFGGNT), + .TRNTD (delay_TRNTD), + .TRNTDLLPDATA (delay_TRNTDLLPDATA), + .TRNTDLLPSRCRDY (delay_TRNTDLLPSRCRDY), + .TRNTECRCGEN (delay_TRNTECRCGEN), + .TRNTEOF (delay_TRNTEOF), + .TRNTERRFWD (delay_TRNTERRFWD), + .TRNTREM (delay_TRNTREM), + .TRNTSOF (delay_TRNTSOF), + .TRNTSRCDSC (delay_TRNTSRCDSC), + .TRNTSRCRDY (delay_TRNTSRCRDY), + .TRNTSTR (delay_TRNTSTR), + .USERCLK (delay_USERCLK), + .USERCLK2 (delay_USERCLK2) +// .GSR (GSR) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge PIPECLK, 0:0:0, notifier); + $period (posedge USERCLK, 0:0:0, notifier); + $period (posedge USERCLK2, 0:0:0, notifier); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge PIPECLK, negedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID); + $setuphold (posedge PIPECLK, negedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID); + $setuphold (posedge PIPECLK, negedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID); + $setuphold (posedge PIPECLK, negedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID); + $setuphold (posedge PIPECLK, negedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID); + $setuphold (posedge PIPECLK, negedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID); + $setuphold (posedge PIPECLK, negedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID); + $setuphold (posedge PIPECLK, negedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED); + $setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]); + $setuphold (posedge PIPECLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE); + $setuphold (posedge PIPECLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID); + $setuphold (posedge PIPECLK, negedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]); + $setuphold (posedge PIPECLK, negedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]); + $setuphold (posedge PIPECLK, negedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]); + $setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL); + $setuphold (posedge PIPECLK, negedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE); + $setuphold (posedge PIPECLK, negedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN); + $setuphold (posedge PIPECLK, negedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST); + $setuphold (posedge PIPECLK, negedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH); + $setuphold (posedge PIPECLK, posedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID); + $setuphold (posedge PIPECLK, posedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID); + $setuphold (posedge PIPECLK, posedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID); + $setuphold (posedge PIPECLK, posedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID); + $setuphold (posedge PIPECLK, posedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID); + $setuphold (posedge PIPECLK, posedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID); + $setuphold (posedge PIPECLK, posedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID); + $setuphold (posedge PIPECLK, posedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED); + $setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]); + $setuphold (posedge PIPECLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE); + $setuphold (posedge PIPECLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID); + $setuphold (posedge PIPECLK, posedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]); + $setuphold (posedge PIPECLK, posedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]); + $setuphold (posedge PIPECLK, posedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]); + $setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL); + $setuphold (posedge PIPECLK, posedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE); + $setuphold (posedge PIPECLK, posedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN); + $setuphold (posedge PIPECLK, posedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST); + $setuphold (posedge PIPECLK, posedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]); + $setuphold (posedge USERCLK, negedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]); + $setuphold (posedge USERCLK, negedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]); + $setuphold (posedge USERCLK, posedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]); + $setuphold (posedge USERCLK, posedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]); + $setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]); + $setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]); + $setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]); + $setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]); + $setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]); + $setuphold (posedge USERCLK2, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]); + $setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]); + $setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]); + $setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]); + $setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]); + $setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]); + $setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]); + $setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK2, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]); + $setuphold (posedge USERCLK2, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]); + $setuphold (posedge USERCLK2, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]); + $setuphold (posedge USERCLK2, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]); + $setuphold (posedge USERCLK2, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]); + $setuphold (posedge USERCLK2, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]); + $setuphold (posedge USERCLK2, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]); + $setuphold (posedge USERCLK2, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]); + $setuphold (posedge USERCLK2, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]); + $setuphold (posedge USERCLK2, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]); + $setuphold (posedge USERCLK2, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]); + $setuphold (posedge USERCLK2, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]); + $setuphold (posedge USERCLK2, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]); + $setuphold (posedge USERCLK2, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]); + $setuphold (posedge USERCLK2, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]); + $setuphold (posedge USERCLK2, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]); + $setuphold (posedge USERCLK2, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]); + $setuphold (posedge USERCLK2, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]); + $setuphold (posedge USERCLK2, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]); + $setuphold (posedge USERCLK2, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]); + $setuphold (posedge USERCLK2, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]); + $setuphold (posedge USERCLK2, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]); + $setuphold (posedge USERCLK2, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]); + $setuphold (posedge USERCLK2, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]); + $setuphold (posedge USERCLK2, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]); + $setuphold (posedge USERCLK2, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]); + $setuphold (posedge USERCLK2, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]); + $setuphold (posedge USERCLK2, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]); + $setuphold (posedge USERCLK2, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]); + $setuphold (posedge USERCLK2, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]); + $setuphold (posedge USERCLK2, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]); + $setuphold (posedge USERCLK2, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]); + $setuphold (posedge USERCLK2, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]); + $setuphold (posedge USERCLK2, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]); + $setuphold (posedge USERCLK2, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]); + $setuphold (posedge USERCLK2, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]); + $setuphold (posedge USERCLK2, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]); + $setuphold (posedge USERCLK2, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]); + $setuphold (posedge USERCLK2, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]); + $setuphold (posedge USERCLK2, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]); + $setuphold (posedge USERCLK2, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]); + $setuphold (posedge USERCLK2, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]); + $setuphold (posedge USERCLK2, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]); + $setuphold (posedge USERCLK2, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]); + $setuphold (posedge USERCLK2, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]); + $setuphold (posedge USERCLK2, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]); + $setuphold (posedge USERCLK2, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]); + $setuphold (posedge USERCLK2, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]); + $setuphold (posedge USERCLK2, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]); + $setuphold (posedge USERCLK2, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]); + $setuphold (posedge USERCLK2, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]); + $setuphold (posedge USERCLK2, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]); + $setuphold (posedge USERCLK2, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]); + $setuphold (posedge USERCLK2, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]); + $setuphold (posedge USERCLK2, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]); + $setuphold (posedge USERCLK2, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]); + $setuphold (posedge USERCLK2, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]); + $setuphold (posedge USERCLK2, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]); + $setuphold (posedge USERCLK2, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]); + $setuphold (posedge USERCLK2, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]); + $setuphold (posedge USERCLK2, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]); + $setuphold (posedge USERCLK2, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]); + $setuphold (posedge USERCLK2, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]); + $setuphold (posedge USERCLK2, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]); + $setuphold (posedge USERCLK2, negedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]); + $setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]); + $setuphold (posedge USERCLK2, negedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN); + $setuphold (posedge USERCLK2, negedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN); + $setuphold (posedge USERCLK2, negedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN); + $setuphold (posedge USERCLK2, negedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN); + $setuphold (posedge USERCLK2, negedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN); + $setuphold (posedge USERCLK2, negedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN); + $setuphold (posedge USERCLK2, negedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN); + $setuphold (posedge USERCLK2, negedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN); + $setuphold (posedge USERCLK2, negedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN); + $setuphold (posedge USERCLK2, negedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN); + $setuphold (posedge USERCLK2, negedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN); + $setuphold (posedge USERCLK2, negedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN); + $setuphold (posedge USERCLK2, negedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN); + $setuphold (posedge USERCLK2, negedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]); + $setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]); + $setuphold (posedge USERCLK2, negedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN); + $setuphold (posedge USERCLK2, negedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF); + $setuphold (posedge USERCLK2, negedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON); + $setuphold (posedge USERCLK2, negedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]); + $setuphold (posedge USERCLK2, negedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]); + $setuphold (posedge USERCLK2, negedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN); + $setuphold (posedge USERCLK2, negedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN); + $setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]); + $setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]); + $setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]); + $setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]); + $setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]); + $setuphold (posedge USERCLK2, negedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN); + $setuphold (posedge USERCLK2, negedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN); + $setuphold (posedge USERCLK2, negedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN); + $setuphold (posedge USERCLK2, negedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN); + $setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]); + $setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]); + $setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]); + $setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]); + $setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]); + $setuphold (posedge USERCLK2, negedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN); + $setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]); + $setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]); + $setuphold (posedge USERCLK2, negedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN); + $setuphold (posedge USERCLK2, negedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N); + $setuphold (posedge USERCLK2, negedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON); + $setuphold (posedge USERCLK2, negedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN); + $setuphold (posedge USERCLK2, negedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]); + $setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]); + $setuphold (posedge USERCLK2, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]); + $setuphold (posedge USERCLK2, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]); + $setuphold (posedge USERCLK2, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]); + $setuphold (posedge USERCLK2, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]); + $setuphold (posedge USERCLK2, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]); + $setuphold (posedge USERCLK2, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]); + $setuphold (posedge USERCLK2, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]); + $setuphold (posedge USERCLK2, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]); + $setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]); + $setuphold (posedge USERCLK2, negedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN); + $setuphold (posedge USERCLK2, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]); + $setuphold (posedge USERCLK2, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]); + $setuphold (posedge USERCLK2, negedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN); + $setuphold (posedge USERCLK2, negedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN); + $setuphold (posedge USERCLK2, negedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]); + $setuphold (posedge USERCLK2, negedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]); + $setuphold (posedge USERCLK2, negedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE); + $setuphold (posedge USERCLK2, negedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN); + $setuphold (posedge USERCLK2, negedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN); + $setuphold (posedge USERCLK2, negedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1); + $setuphold (posedge USERCLK2, negedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1); + $setuphold (posedge USERCLK2, negedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23); + $setuphold (posedge USERCLK2, negedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK); + $setuphold (posedge USERCLK2, negedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW); + $setuphold (posedge USERCLK2, negedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV); + $setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]); + $setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]); + $setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]); + $setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]); + $setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]); + $setuphold (posedge USERCLK2, negedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK); + $setuphold (posedge USERCLK2, negedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ); + $setuphold (posedge USERCLK2, negedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN); + $setuphold (posedge USERCLK2, negedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]); + $setuphold (posedge USERCLK2, negedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]); + $setuphold (posedge USERCLK2, negedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]); + $setuphold (posedge USERCLK2, negedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY); + $setuphold (posedge USERCLK2, negedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET); + $setuphold (posedge USERCLK2, negedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK); + $setuphold (posedge USERCLK2, negedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ); + $setuphold (posedge USERCLK2, negedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]); + $setuphold (posedge USERCLK2, negedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY); + $setuphold (posedge USERCLK2, negedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]); + $setuphold (posedge USERCLK2, negedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]); + $setuphold (posedge USERCLK2, negedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]); + $setuphold (posedge USERCLK2, negedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]); + $setuphold (posedge USERCLK2, negedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]); + $setuphold (posedge USERCLK2, negedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]); + $setuphold (posedge USERCLK2, negedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]); + $setuphold (posedge USERCLK2, negedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]); + $setuphold (posedge USERCLK2, negedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]); + $setuphold (posedge USERCLK2, negedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]); + $setuphold (posedge USERCLK2, negedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]); + $setuphold (posedge USERCLK2, negedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]); + $setuphold (posedge USERCLK2, negedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]); + $setuphold (posedge USERCLK2, negedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]); + $setuphold (posedge USERCLK2, negedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]); + $setuphold (posedge USERCLK2, negedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]); + $setuphold (posedge USERCLK2, negedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]); + $setuphold (posedge USERCLK2, negedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]); + $setuphold (posedge USERCLK2, negedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]); + $setuphold (posedge USERCLK2, negedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]); + $setuphold (posedge USERCLK2, negedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]); + $setuphold (posedge USERCLK2, negedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]); + $setuphold (posedge USERCLK2, negedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]); + $setuphold (posedge USERCLK2, negedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]); + $setuphold (posedge USERCLK2, negedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]); + $setuphold (posedge USERCLK2, negedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]); + $setuphold (posedge USERCLK2, negedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]); + $setuphold (posedge USERCLK2, negedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]); + $setuphold (posedge USERCLK2, negedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]); + $setuphold (posedge USERCLK2, negedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]); + $setuphold (posedge USERCLK2, negedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]); + $setuphold (posedge USERCLK2, negedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]); + $setuphold (posedge USERCLK2, negedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]); + $setuphold (posedge USERCLK2, negedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]); + $setuphold (posedge USERCLK2, negedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]); + $setuphold (posedge USERCLK2, negedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]); + $setuphold (posedge USERCLK2, negedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]); + $setuphold (posedge USERCLK2, negedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]); + $setuphold (posedge USERCLK2, negedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]); + $setuphold (posedge USERCLK2, negedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]); + $setuphold (posedge USERCLK2, negedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]); + $setuphold (posedge USERCLK2, negedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]); + $setuphold (posedge USERCLK2, negedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]); + $setuphold (posedge USERCLK2, negedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]); + $setuphold (posedge USERCLK2, negedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]); + $setuphold (posedge USERCLK2, negedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]); + $setuphold (posedge USERCLK2, negedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]); + $setuphold (posedge USERCLK2, negedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]); + $setuphold (posedge USERCLK2, negedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]); + $setuphold (posedge USERCLK2, negedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]); + $setuphold (posedge USERCLK2, negedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]); + $setuphold (posedge USERCLK2, negedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]); + $setuphold (posedge USERCLK2, negedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]); + $setuphold (posedge USERCLK2, negedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]); + $setuphold (posedge USERCLK2, negedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]); + $setuphold (posedge USERCLK2, negedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]); + $setuphold (posedge USERCLK2, negedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]); + $setuphold (posedge USERCLK2, negedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]); + $setuphold (posedge USERCLK2, negedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]); + $setuphold (posedge USERCLK2, negedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]); + $setuphold (posedge USERCLK2, negedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]); + $setuphold (posedge USERCLK2, negedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]); + $setuphold (posedge USERCLK2, negedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]); + $setuphold (posedge USERCLK2, negedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]); + $setuphold (posedge USERCLK2, negedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]); + $setuphold (posedge USERCLK2, negedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]); + $setuphold (posedge USERCLK2, negedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]); + $setuphold (posedge USERCLK2, negedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]); + $setuphold (posedge USERCLK2, negedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]); + $setuphold (posedge USERCLK2, negedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]); + $setuphold (posedge USERCLK2, negedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]); + $setuphold (posedge USERCLK2, negedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]); + $setuphold (posedge USERCLK2, negedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]); + $setuphold (posedge USERCLK2, negedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]); + $setuphold (posedge USERCLK2, negedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]); + $setuphold (posedge USERCLK2, negedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]); + $setuphold (posedge USERCLK2, negedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]); + $setuphold (posedge USERCLK2, negedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]); + $setuphold (posedge USERCLK2, negedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]); + $setuphold (posedge USERCLK2, negedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]); + $setuphold (posedge USERCLK2, negedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]); + $setuphold (posedge USERCLK2, negedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]); + $setuphold (posedge USERCLK2, negedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]); + $setuphold (posedge USERCLK2, negedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]); + $setuphold (posedge USERCLK2, negedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]); + $setuphold (posedge USERCLK2, negedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]); + $setuphold (posedge USERCLK2, negedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]); + $setuphold (posedge USERCLK2, negedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]); + $setuphold (posedge USERCLK2, negedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]); + $setuphold (posedge USERCLK2, negedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]); + $setuphold (posedge USERCLK2, negedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]); + $setuphold (posedge USERCLK2, negedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]); + $setuphold (posedge USERCLK2, negedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]); + $setuphold (posedge USERCLK2, negedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]); + $setuphold (posedge USERCLK2, negedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]); + $setuphold (posedge USERCLK2, negedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]); + $setuphold (posedge USERCLK2, negedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]); + $setuphold (posedge USERCLK2, negedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]); + $setuphold (posedge USERCLK2, negedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]); + $setuphold (posedge USERCLK2, negedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]); + $setuphold (posedge USERCLK2, negedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]); + $setuphold (posedge USERCLK2, negedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]); + $setuphold (posedge USERCLK2, negedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]); + $setuphold (posedge USERCLK2, negedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]); + $setuphold (posedge USERCLK2, negedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]); + $setuphold (posedge USERCLK2, negedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]); + $setuphold (posedge USERCLK2, negedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]); + $setuphold (posedge USERCLK2, negedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]); + $setuphold (posedge USERCLK2, negedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]); + $setuphold (posedge USERCLK2, negedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]); + $setuphold (posedge USERCLK2, negedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]); + $setuphold (posedge USERCLK2, negedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]); + $setuphold (posedge USERCLK2, negedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]); + $setuphold (posedge USERCLK2, negedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]); + $setuphold (posedge USERCLK2, negedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]); + $setuphold (posedge USERCLK2, negedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]); + $setuphold (posedge USERCLK2, negedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]); + $setuphold (posedge USERCLK2, negedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]); + $setuphold (posedge USERCLK2, negedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]); + $setuphold (posedge USERCLK2, negedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]); + $setuphold (posedge USERCLK2, negedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]); + $setuphold (posedge USERCLK2, negedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]); + $setuphold (posedge USERCLK2, negedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]); + $setuphold (posedge USERCLK2, negedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]); + $setuphold (posedge USERCLK2, negedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]); + $setuphold (posedge USERCLK2, negedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]); + $setuphold (posedge USERCLK2, negedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]); + $setuphold (posedge USERCLK2, negedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]); + $setuphold (posedge USERCLK2, negedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN); + $setuphold (posedge USERCLK2, negedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF); + $setuphold (posedge USERCLK2, negedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD); + $setuphold (posedge USERCLK2, negedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]); + $setuphold (posedge USERCLK2, negedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]); + $setuphold (posedge USERCLK2, negedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF); + $setuphold (posedge USERCLK2, negedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC); + $setuphold (posedge USERCLK2, negedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY); + $setuphold (posedge USERCLK2, negedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR); + $setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]); + $setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]); + $setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]); + $setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]); + $setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]); + $setuphold (posedge USERCLK2, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]); + $setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]); + $setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]); + $setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]); + $setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]); + $setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]); + $setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]); + $setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK2, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]); + $setuphold (posedge USERCLK2, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]); + $setuphold (posedge USERCLK2, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]); + $setuphold (posedge USERCLK2, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]); + $setuphold (posedge USERCLK2, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]); + $setuphold (posedge USERCLK2, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]); + $setuphold (posedge USERCLK2, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]); + $setuphold (posedge USERCLK2, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]); + $setuphold (posedge USERCLK2, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]); + $setuphold (posedge USERCLK2, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]); + $setuphold (posedge USERCLK2, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]); + $setuphold (posedge USERCLK2, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]); + $setuphold (posedge USERCLK2, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]); + $setuphold (posedge USERCLK2, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]); + $setuphold (posedge USERCLK2, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]); + $setuphold (posedge USERCLK2, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]); + $setuphold (posedge USERCLK2, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]); + $setuphold (posedge USERCLK2, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]); + $setuphold (posedge USERCLK2, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]); + $setuphold (posedge USERCLK2, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]); + $setuphold (posedge USERCLK2, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]); + $setuphold (posedge USERCLK2, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]); + $setuphold (posedge USERCLK2, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]); + $setuphold (posedge USERCLK2, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]); + $setuphold (posedge USERCLK2, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]); + $setuphold (posedge USERCLK2, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]); + $setuphold (posedge USERCLK2, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]); + $setuphold (posedge USERCLK2, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]); + $setuphold (posedge USERCLK2, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]); + $setuphold (posedge USERCLK2, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]); + $setuphold (posedge USERCLK2, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]); + $setuphold (posedge USERCLK2, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]); + $setuphold (posedge USERCLK2, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]); + $setuphold (posedge USERCLK2, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]); + $setuphold (posedge USERCLK2, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]); + $setuphold (posedge USERCLK2, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]); + $setuphold (posedge USERCLK2, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]); + $setuphold (posedge USERCLK2, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]); + $setuphold (posedge USERCLK2, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]); + $setuphold (posedge USERCLK2, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]); + $setuphold (posedge USERCLK2, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]); + $setuphold (posedge USERCLK2, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]); + $setuphold (posedge USERCLK2, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]); + $setuphold (posedge USERCLK2, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]); + $setuphold (posedge USERCLK2, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]); + $setuphold (posedge USERCLK2, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]); + $setuphold (posedge USERCLK2, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]); + $setuphold (posedge USERCLK2, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]); + $setuphold (posedge USERCLK2, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]); + $setuphold (posedge USERCLK2, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]); + $setuphold (posedge USERCLK2, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]); + $setuphold (posedge USERCLK2, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]); + $setuphold (posedge USERCLK2, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]); + $setuphold (posedge USERCLK2, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]); + $setuphold (posedge USERCLK2, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]); + $setuphold (posedge USERCLK2, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]); + $setuphold (posedge USERCLK2, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]); + $setuphold (posedge USERCLK2, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]); + $setuphold (posedge USERCLK2, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]); + $setuphold (posedge USERCLK2, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]); + $setuphold (posedge USERCLK2, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]); + $setuphold (posedge USERCLK2, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]); + $setuphold (posedge USERCLK2, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]); + $setuphold (posedge USERCLK2, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]); + $setuphold (posedge USERCLK2, posedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]); + $setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]); + $setuphold (posedge USERCLK2, posedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN); + $setuphold (posedge USERCLK2, posedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN); + $setuphold (posedge USERCLK2, posedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN); + $setuphold (posedge USERCLK2, posedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN); + $setuphold (posedge USERCLK2, posedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN); + $setuphold (posedge USERCLK2, posedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN); + $setuphold (posedge USERCLK2, posedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN); + $setuphold (posedge USERCLK2, posedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN); + $setuphold (posedge USERCLK2, posedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN); + $setuphold (posedge USERCLK2, posedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN); + $setuphold (posedge USERCLK2, posedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN); + $setuphold (posedge USERCLK2, posedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN); + $setuphold (posedge USERCLK2, posedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN); + $setuphold (posedge USERCLK2, posedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]); + $setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]); + $setuphold (posedge USERCLK2, posedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN); + $setuphold (posedge USERCLK2, posedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF); + $setuphold (posedge USERCLK2, posedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON); + $setuphold (posedge USERCLK2, posedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]); + $setuphold (posedge USERCLK2, posedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]); + $setuphold (posedge USERCLK2, posedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN); + $setuphold (posedge USERCLK2, posedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN); + $setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]); + $setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]); + $setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]); + $setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]); + $setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]); + $setuphold (posedge USERCLK2, posedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN); + $setuphold (posedge USERCLK2, posedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN); + $setuphold (posedge USERCLK2, posedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN); + $setuphold (posedge USERCLK2, posedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN); + $setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]); + $setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]); + $setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]); + $setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]); + $setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]); + $setuphold (posedge USERCLK2, posedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN); + $setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]); + $setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]); + $setuphold (posedge USERCLK2, posedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN); + $setuphold (posedge USERCLK2, posedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N); + $setuphold (posedge USERCLK2, posedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON); + $setuphold (posedge USERCLK2, posedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN); + $setuphold (posedge USERCLK2, posedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]); + $setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]); + $setuphold (posedge USERCLK2, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]); + $setuphold (posedge USERCLK2, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]); + $setuphold (posedge USERCLK2, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]); + $setuphold (posedge USERCLK2, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]); + $setuphold (posedge USERCLK2, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]); + $setuphold (posedge USERCLK2, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]); + $setuphold (posedge USERCLK2, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]); + $setuphold (posedge USERCLK2, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]); + $setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]); + $setuphold (posedge USERCLK2, posedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN); + $setuphold (posedge USERCLK2, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]); + $setuphold (posedge USERCLK2, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]); + $setuphold (posedge USERCLK2, posedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN); + $setuphold (posedge USERCLK2, posedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN); + $setuphold (posedge USERCLK2, posedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]); + $setuphold (posedge USERCLK2, posedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]); + $setuphold (posedge USERCLK2, posedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE); + $setuphold (posedge USERCLK2, posedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN); + $setuphold (posedge USERCLK2, posedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN); + $setuphold (posedge USERCLK2, posedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1); + $setuphold (posedge USERCLK2, posedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1); + $setuphold (posedge USERCLK2, posedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23); + $setuphold (posedge USERCLK2, posedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK); + $setuphold (posedge USERCLK2, posedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW); + $setuphold (posedge USERCLK2, posedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV); + $setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]); + $setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]); + $setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]); + $setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]); + $setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]); + $setuphold (posedge USERCLK2, posedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK); + $setuphold (posedge USERCLK2, posedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ); + $setuphold (posedge USERCLK2, posedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN); + $setuphold (posedge USERCLK2, posedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]); + $setuphold (posedge USERCLK2, posedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]); + $setuphold (posedge USERCLK2, posedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]); + $setuphold (posedge USERCLK2, posedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY); + $setuphold (posedge USERCLK2, posedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET); + $setuphold (posedge USERCLK2, posedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK); + $setuphold (posedge USERCLK2, posedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ); + $setuphold (posedge USERCLK2, posedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]); + $setuphold (posedge USERCLK2, posedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY); + $setuphold (posedge USERCLK2, posedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]); + $setuphold (posedge USERCLK2, posedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]); + $setuphold (posedge USERCLK2, posedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]); + $setuphold (posedge USERCLK2, posedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]); + $setuphold (posedge USERCLK2, posedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]); + $setuphold (posedge USERCLK2, posedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]); + $setuphold (posedge USERCLK2, posedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]); + $setuphold (posedge USERCLK2, posedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]); + $setuphold (posedge USERCLK2, posedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]); + $setuphold (posedge USERCLK2, posedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]); + $setuphold (posedge USERCLK2, posedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]); + $setuphold (posedge USERCLK2, posedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]); + $setuphold (posedge USERCLK2, posedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]); + $setuphold (posedge USERCLK2, posedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]); + $setuphold (posedge USERCLK2, posedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]); + $setuphold (posedge USERCLK2, posedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]); + $setuphold (posedge USERCLK2, posedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]); + $setuphold (posedge USERCLK2, posedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]); + $setuphold (posedge USERCLK2, posedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]); + $setuphold (posedge USERCLK2, posedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]); + $setuphold (posedge USERCLK2, posedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]); + $setuphold (posedge USERCLK2, posedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]); + $setuphold (posedge USERCLK2, posedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]); + $setuphold (posedge USERCLK2, posedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]); + $setuphold (posedge USERCLK2, posedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]); + $setuphold (posedge USERCLK2, posedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]); + $setuphold (posedge USERCLK2, posedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]); + $setuphold (posedge USERCLK2, posedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]); + $setuphold (posedge USERCLK2, posedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]); + $setuphold (posedge USERCLK2, posedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]); + $setuphold (posedge USERCLK2, posedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]); + $setuphold (posedge USERCLK2, posedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]); + $setuphold (posedge USERCLK2, posedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]); + $setuphold (posedge USERCLK2, posedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]); + $setuphold (posedge USERCLK2, posedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]); + $setuphold (posedge USERCLK2, posedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]); + $setuphold (posedge USERCLK2, posedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]); + $setuphold (posedge USERCLK2, posedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]); + $setuphold (posedge USERCLK2, posedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]); + $setuphold (posedge USERCLK2, posedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]); + $setuphold (posedge USERCLK2, posedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]); + $setuphold (posedge USERCLK2, posedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]); + $setuphold (posedge USERCLK2, posedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]); + $setuphold (posedge USERCLK2, posedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]); + $setuphold (posedge USERCLK2, posedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]); + $setuphold (posedge USERCLK2, posedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]); + $setuphold (posedge USERCLK2, posedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]); + $setuphold (posedge USERCLK2, posedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]); + $setuphold (posedge USERCLK2, posedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]); + $setuphold (posedge USERCLK2, posedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]); + $setuphold (posedge USERCLK2, posedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]); + $setuphold (posedge USERCLK2, posedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]); + $setuphold (posedge USERCLK2, posedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]); + $setuphold (posedge USERCLK2, posedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]); + $setuphold (posedge USERCLK2, posedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]); + $setuphold (posedge USERCLK2, posedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]); + $setuphold (posedge USERCLK2, posedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]); + $setuphold (posedge USERCLK2, posedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]); + $setuphold (posedge USERCLK2, posedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]); + $setuphold (posedge USERCLK2, posedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]); + $setuphold (posedge USERCLK2, posedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]); + $setuphold (posedge USERCLK2, posedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]); + $setuphold (posedge USERCLK2, posedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]); + $setuphold (posedge USERCLK2, posedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]); + $setuphold (posedge USERCLK2, posedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]); + $setuphold (posedge USERCLK2, posedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]); + $setuphold (posedge USERCLK2, posedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]); + $setuphold (posedge USERCLK2, posedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]); + $setuphold (posedge USERCLK2, posedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]); + $setuphold (posedge USERCLK2, posedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]); + $setuphold (posedge USERCLK2, posedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]); + $setuphold (posedge USERCLK2, posedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]); + $setuphold (posedge USERCLK2, posedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]); + $setuphold (posedge USERCLK2, posedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]); + $setuphold (posedge USERCLK2, posedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]); + $setuphold (posedge USERCLK2, posedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]); + $setuphold (posedge USERCLK2, posedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]); + $setuphold (posedge USERCLK2, posedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]); + $setuphold (posedge USERCLK2, posedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]); + $setuphold (posedge USERCLK2, posedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]); + $setuphold (posedge USERCLK2, posedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]); + $setuphold (posedge USERCLK2, posedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]); + $setuphold (posedge USERCLK2, posedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]); + $setuphold (posedge USERCLK2, posedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]); + $setuphold (posedge USERCLK2, posedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]); + $setuphold (posedge USERCLK2, posedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]); + $setuphold (posedge USERCLK2, posedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]); + $setuphold (posedge USERCLK2, posedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]); + $setuphold (posedge USERCLK2, posedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]); + $setuphold (posedge USERCLK2, posedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]); + $setuphold (posedge USERCLK2, posedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]); + $setuphold (posedge USERCLK2, posedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]); + $setuphold (posedge USERCLK2, posedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]); + $setuphold (posedge USERCLK2, posedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]); + $setuphold (posedge USERCLK2, posedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]); + $setuphold (posedge USERCLK2, posedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]); + $setuphold (posedge USERCLK2, posedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]); + $setuphold (posedge USERCLK2, posedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]); + $setuphold (posedge USERCLK2, posedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]); + $setuphold (posedge USERCLK2, posedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]); + $setuphold (posedge USERCLK2, posedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]); + $setuphold (posedge USERCLK2, posedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]); + $setuphold (posedge USERCLK2, posedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]); + $setuphold (posedge USERCLK2, posedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]); + $setuphold (posedge USERCLK2, posedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]); + $setuphold (posedge USERCLK2, posedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]); + $setuphold (posedge USERCLK2, posedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]); + $setuphold (posedge USERCLK2, posedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]); + $setuphold (posedge USERCLK2, posedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]); + $setuphold (posedge USERCLK2, posedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]); + $setuphold (posedge USERCLK2, posedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]); + $setuphold (posedge USERCLK2, posedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]); + $setuphold (posedge USERCLK2, posedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]); + $setuphold (posedge USERCLK2, posedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]); + $setuphold (posedge USERCLK2, posedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]); + $setuphold (posedge USERCLK2, posedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]); + $setuphold (posedge USERCLK2, posedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]); + $setuphold (posedge USERCLK2, posedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]); + $setuphold (posedge USERCLK2, posedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]); + $setuphold (posedge USERCLK2, posedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]); + $setuphold (posedge USERCLK2, posedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]); + $setuphold (posedge USERCLK2, posedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]); + $setuphold (posedge USERCLK2, posedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]); + $setuphold (posedge USERCLK2, posedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]); + $setuphold (posedge USERCLK2, posedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]); + $setuphold (posedge USERCLK2, posedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]); + $setuphold (posedge USERCLK2, posedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]); + $setuphold (posedge USERCLK2, posedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]); + $setuphold (posedge USERCLK2, posedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN); + $setuphold (posedge USERCLK2, posedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF); + $setuphold (posedge USERCLK2, posedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD); + $setuphold (posedge USERCLK2, posedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]); + $setuphold (posedge USERCLK2, posedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]); + $setuphold (posedge USERCLK2, posedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF); + $setuphold (posedge USERCLK2, posedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC); + $setuphold (posedge USERCLK2, posedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY); + $setuphold (posedge USERCLK2, posedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR); +`endif + + ( DRPCLK *> DRPDO[0]) = (0, 0); + ( DRPCLK *> DRPDO[10]) = (0, 0); + ( DRPCLK *> DRPDO[11]) = (0, 0); + ( DRPCLK *> DRPDO[12]) = (0, 0); + ( DRPCLK *> DRPDO[13]) = (0, 0); + ( DRPCLK *> DRPDO[14]) = (0, 0); + ( DRPCLK *> DRPDO[15]) = (0, 0); + ( DRPCLK *> DRPDO[1]) = (0, 0); + ( DRPCLK *> DRPDO[2]) = (0, 0); + ( DRPCLK *> DRPDO[3]) = (0, 0); + ( DRPCLK *> DRPDO[4]) = (0, 0); + ( DRPCLK *> DRPDO[5]) = (0, 0); + ( DRPCLK *> DRPDO[6]) = (0, 0); + ( DRPCLK *> DRPDO[7]) = (0, 0); + ( DRPCLK *> DRPDO[8]) = (0, 0); + ( DRPCLK *> DRPDO[9]) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( PIPECLK *> PIPERX0POLARITY) = (0, 0); + ( PIPECLK *> PIPERX1POLARITY) = (0, 0); + ( PIPECLK *> PIPERX2POLARITY) = (0, 0); + ( PIPECLK *> PIPERX3POLARITY) = (0, 0); + ( PIPECLK *> PIPERX4POLARITY) = (0, 0); + ( PIPECLK *> PIPERX5POLARITY) = (0, 0); + ( PIPECLK *> PIPERX6POLARITY) = (0, 0); + ( PIPECLK *> PIPERX7POLARITY) = (0, 0); + ( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX0DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX0ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX1DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX1ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX2DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX2ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX3DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX3ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX4DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX4ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX5DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX5ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX6DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX6ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX7DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX7ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETXDEEMPH) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[0]) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[1]) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[2]) = (0, 0); + ( PIPECLK *> PIPETXRATE) = (0, 0); + ( PIPECLK *> PIPETXRCVRDET) = (0, 0); + ( PIPECLK *> PIPETXRESET) = (0, 0); + ( PIPECLK *> PLDBGVEC[0]) = (0, 0); + ( PIPECLK *> PLDBGVEC[10]) = (0, 0); + ( PIPECLK *> PLDBGVEC[11]) = (0, 0); + ( PIPECLK *> PLDBGVEC[1]) = (0, 0); + ( PIPECLK *> PLDBGVEC[2]) = (0, 0); + ( PIPECLK *> PLDBGVEC[3]) = (0, 0); + ( PIPECLK *> PLDBGVEC[4]) = (0, 0); + ( PIPECLK *> PLDBGVEC[5]) = (0, 0); + ( PIPECLK *> PLDBGVEC[6]) = (0, 0); + ( PIPECLK *> PLDBGVEC[7]) = (0, 0); + ( PIPECLK *> PLDBGVEC[8]) = (0, 0); + ( PIPECLK *> PLDBGVEC[9]) = (0, 0); + ( PIPECLK *> PLDIRECTEDCHANGEDONE) = (0, 0); + ( PIPECLK *> PLINITIALLINKWIDTH[0]) = (0, 0); + ( PIPECLK *> PLINITIALLINKWIDTH[1]) = (0, 0); + ( PIPECLK *> PLINITIALLINKWIDTH[2]) = (0, 0); + ( PIPECLK *> PLLANEREVERSALMODE[0]) = (0, 0); + ( PIPECLK *> PLLANEREVERSALMODE[1]) = (0, 0); + ( PIPECLK *> PLLINKGEN2CAP) = (0, 0); + ( PIPECLK *> PLLINKPARTNERGEN2SUPPORTED) = (0, 0); + ( PIPECLK *> PLLINKUPCFGCAP) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[0]) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[1]) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[2]) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[3]) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[4]) = (0, 0); + ( PIPECLK *> PLLTSSMSTATE[5]) = (0, 0); + ( PIPECLK *> PLPHYLNKUPN) = (0, 0); + ( PIPECLK *> PLRECEIVEDHOTRST) = (0, 0); + ( PIPECLK *> PLRXPMSTATE[0]) = (0, 0); + ( PIPECLK *> PLRXPMSTATE[1]) = (0, 0); + ( PIPECLK *> PLSELLNKRATE) = (0, 0); + ( PIPECLK *> PLSELLNKWIDTH[0]) = (0, 0); + ( PIPECLK *> PLSELLNKWIDTH[1]) = (0, 0); + ( PIPECLK *> PLTXPMSTATE[0]) = (0, 0); + ( PIPECLK *> PLTXPMSTATE[1]) = (0, 0); + ( PIPECLK *> PLTXPMSTATE[2]) = (0, 0); + ( USERCLK *> LNKCLKEN) = (0, 0); + ( USERCLK *> MIMRXRADDR[0]) = (0, 0); + ( USERCLK *> MIMRXRADDR[10]) = (0, 0); + ( USERCLK *> MIMRXRADDR[11]) = (0, 0); + ( USERCLK *> MIMRXRADDR[12]) = (0, 0); + ( USERCLK *> MIMRXRADDR[1]) = (0, 0); + ( USERCLK *> MIMRXRADDR[2]) = (0, 0); + ( USERCLK *> MIMRXRADDR[3]) = (0, 0); + ( USERCLK *> MIMRXRADDR[4]) = (0, 0); + ( USERCLK *> MIMRXRADDR[5]) = (0, 0); + ( USERCLK *> MIMRXRADDR[6]) = (0, 0); + ( USERCLK *> MIMRXRADDR[7]) = (0, 0); + ( USERCLK *> MIMRXRADDR[8]) = (0, 0); + ( USERCLK *> MIMRXRADDR[9]) = (0, 0); + ( USERCLK *> MIMRXREN) = (0, 0); + ( USERCLK *> MIMRXWADDR[0]) = (0, 0); + ( USERCLK *> MIMRXWADDR[10]) = (0, 0); + ( USERCLK *> MIMRXWADDR[11]) = (0, 0); + ( USERCLK *> MIMRXWADDR[12]) = (0, 0); + ( USERCLK *> MIMRXWADDR[1]) = (0, 0); + ( USERCLK *> MIMRXWADDR[2]) = (0, 0); + ( USERCLK *> MIMRXWADDR[3]) = (0, 0); + ( USERCLK *> MIMRXWADDR[4]) = (0, 0); + ( USERCLK *> MIMRXWADDR[5]) = (0, 0); + ( USERCLK *> MIMRXWADDR[6]) = (0, 0); + ( USERCLK *> MIMRXWADDR[7]) = (0, 0); + ( USERCLK *> MIMRXWADDR[8]) = (0, 0); + ( USERCLK *> MIMRXWADDR[9]) = (0, 0); + ( USERCLK *> MIMRXWDATA[0]) = (0, 0); + ( USERCLK *> MIMRXWDATA[10]) = (0, 0); + ( USERCLK *> MIMRXWDATA[11]) = (0, 0); + ( USERCLK *> MIMRXWDATA[12]) = (0, 0); + ( USERCLK *> MIMRXWDATA[13]) = (0, 0); + ( USERCLK *> MIMRXWDATA[14]) = (0, 0); + ( USERCLK *> MIMRXWDATA[15]) = (0, 0); + ( USERCLK *> MIMRXWDATA[16]) = (0, 0); + ( USERCLK *> MIMRXWDATA[17]) = (0, 0); + ( USERCLK *> MIMRXWDATA[18]) = (0, 0); + ( USERCLK *> MIMRXWDATA[19]) = (0, 0); + ( USERCLK *> MIMRXWDATA[1]) = (0, 0); + ( USERCLK *> MIMRXWDATA[20]) = (0, 0); + ( USERCLK *> MIMRXWDATA[21]) = (0, 0); + ( USERCLK *> MIMRXWDATA[22]) = (0, 0); + ( USERCLK *> MIMRXWDATA[23]) = (0, 0); + ( USERCLK *> MIMRXWDATA[24]) = (0, 0); + ( USERCLK *> MIMRXWDATA[25]) = (0, 0); + ( USERCLK *> MIMRXWDATA[26]) = (0, 0); + ( USERCLK *> MIMRXWDATA[27]) = (0, 0); + ( USERCLK *> MIMRXWDATA[28]) = (0, 0); + ( USERCLK *> MIMRXWDATA[29]) = (0, 0); + ( USERCLK *> MIMRXWDATA[2]) = (0, 0); + ( USERCLK *> MIMRXWDATA[30]) = (0, 0); + ( USERCLK *> MIMRXWDATA[31]) = (0, 0); + ( USERCLK *> MIMRXWDATA[32]) = (0, 0); + ( USERCLK *> MIMRXWDATA[33]) = (0, 0); + ( USERCLK *> MIMRXWDATA[34]) = (0, 0); + ( USERCLK *> MIMRXWDATA[35]) = (0, 0); + ( USERCLK *> MIMRXWDATA[36]) = (0, 0); + ( USERCLK *> MIMRXWDATA[37]) = (0, 0); + ( USERCLK *> MIMRXWDATA[38]) = (0, 0); + ( USERCLK *> MIMRXWDATA[39]) = (0, 0); + ( USERCLK *> MIMRXWDATA[3]) = (0, 0); + ( USERCLK *> MIMRXWDATA[40]) = (0, 0); + ( USERCLK *> MIMRXWDATA[41]) = (0, 0); + ( USERCLK *> MIMRXWDATA[42]) = (0, 0); + ( USERCLK *> MIMRXWDATA[43]) = (0, 0); + ( USERCLK *> MIMRXWDATA[44]) = (0, 0); + ( USERCLK *> MIMRXWDATA[45]) = (0, 0); + ( USERCLK *> MIMRXWDATA[46]) = (0, 0); + ( USERCLK *> MIMRXWDATA[47]) = (0, 0); + ( USERCLK *> MIMRXWDATA[48]) = (0, 0); + ( USERCLK *> MIMRXWDATA[49]) = (0, 0); + ( USERCLK *> MIMRXWDATA[4]) = (0, 0); + ( USERCLK *> MIMRXWDATA[50]) = (0, 0); + ( USERCLK *> MIMRXWDATA[51]) = (0, 0); + ( USERCLK *> MIMRXWDATA[52]) = (0, 0); + ( USERCLK *> MIMRXWDATA[53]) = (0, 0); + ( USERCLK *> MIMRXWDATA[54]) = (0, 0); + ( USERCLK *> MIMRXWDATA[55]) = (0, 0); + ( USERCLK *> MIMRXWDATA[56]) = (0, 0); + ( USERCLK *> MIMRXWDATA[57]) = (0, 0); + ( USERCLK *> MIMRXWDATA[58]) = (0, 0); + ( USERCLK *> MIMRXWDATA[59]) = (0, 0); + ( USERCLK *> MIMRXWDATA[5]) = (0, 0); + ( USERCLK *> MIMRXWDATA[60]) = (0, 0); + ( USERCLK *> MIMRXWDATA[61]) = (0, 0); + ( USERCLK *> MIMRXWDATA[62]) = (0, 0); + ( USERCLK *> MIMRXWDATA[63]) = (0, 0); + ( USERCLK *> MIMRXWDATA[64]) = (0, 0); + ( USERCLK *> MIMRXWDATA[65]) = (0, 0); + ( USERCLK *> MIMRXWDATA[66]) = (0, 0); + ( USERCLK *> MIMRXWDATA[67]) = (0, 0); + ( USERCLK *> MIMRXWDATA[6]) = (0, 0); + ( USERCLK *> MIMRXWDATA[7]) = (0, 0); + ( USERCLK *> MIMRXWDATA[8]) = (0, 0); + ( USERCLK *> MIMRXWDATA[9]) = (0, 0); + ( USERCLK *> MIMRXWEN) = (0, 0); + ( USERCLK *> MIMTXRADDR[0]) = (0, 0); + ( USERCLK *> MIMTXRADDR[10]) = (0, 0); + ( USERCLK *> MIMTXRADDR[11]) = (0, 0); + ( USERCLK *> MIMTXRADDR[12]) = (0, 0); + ( USERCLK *> MIMTXRADDR[1]) = (0, 0); + ( USERCLK *> MIMTXRADDR[2]) = (0, 0); + ( USERCLK *> MIMTXRADDR[3]) = (0, 0); + ( USERCLK *> MIMTXRADDR[4]) = (0, 0); + ( USERCLK *> MIMTXRADDR[5]) = (0, 0); + ( USERCLK *> MIMTXRADDR[6]) = (0, 0); + ( USERCLK *> MIMTXRADDR[7]) = (0, 0); + ( USERCLK *> MIMTXRADDR[8]) = (0, 0); + ( USERCLK *> MIMTXRADDR[9]) = (0, 0); + ( USERCLK *> MIMTXREN) = (0, 0); + ( USERCLK *> MIMTXWADDR[0]) = (0, 0); + ( USERCLK *> MIMTXWADDR[10]) = (0, 0); + ( USERCLK *> MIMTXWADDR[11]) = (0, 0); + ( USERCLK *> MIMTXWADDR[12]) = (0, 0); + ( USERCLK *> MIMTXWADDR[1]) = (0, 0); + ( USERCLK *> MIMTXWADDR[2]) = (0, 0); + ( USERCLK *> MIMTXWADDR[3]) = (0, 0); + ( USERCLK *> MIMTXWADDR[4]) = (0, 0); + ( USERCLK *> MIMTXWADDR[5]) = (0, 0); + ( USERCLK *> MIMTXWADDR[6]) = (0, 0); + ( USERCLK *> MIMTXWADDR[7]) = (0, 0); + ( USERCLK *> MIMTXWADDR[8]) = (0, 0); + ( USERCLK *> MIMTXWADDR[9]) = (0, 0); + ( USERCLK *> MIMTXWDATA[0]) = (0, 0); + ( USERCLK *> MIMTXWDATA[10]) = (0, 0); + ( USERCLK *> MIMTXWDATA[11]) = (0, 0); + ( USERCLK *> MIMTXWDATA[12]) = (0, 0); + ( USERCLK *> MIMTXWDATA[13]) = (0, 0); + ( USERCLK *> MIMTXWDATA[14]) = (0, 0); + ( USERCLK *> MIMTXWDATA[15]) = (0, 0); + ( USERCLK *> MIMTXWDATA[16]) = (0, 0); + ( USERCLK *> MIMTXWDATA[17]) = (0, 0); + ( USERCLK *> MIMTXWDATA[18]) = (0, 0); + ( USERCLK *> MIMTXWDATA[19]) = (0, 0); + ( USERCLK *> MIMTXWDATA[1]) = (0, 0); + ( USERCLK *> MIMTXWDATA[20]) = (0, 0); + ( USERCLK *> MIMTXWDATA[21]) = (0, 0); + ( USERCLK *> MIMTXWDATA[22]) = (0, 0); + ( USERCLK *> MIMTXWDATA[23]) = (0, 0); + ( USERCLK *> MIMTXWDATA[24]) = (0, 0); + ( USERCLK *> MIMTXWDATA[25]) = (0, 0); + ( USERCLK *> MIMTXWDATA[26]) = (0, 0); + ( USERCLK *> MIMTXWDATA[27]) = (0, 0); + ( USERCLK *> MIMTXWDATA[28]) = (0, 0); + ( USERCLK *> MIMTXWDATA[29]) = (0, 0); + ( USERCLK *> MIMTXWDATA[2]) = (0, 0); + ( USERCLK *> MIMTXWDATA[30]) = (0, 0); + ( USERCLK *> MIMTXWDATA[31]) = (0, 0); + ( USERCLK *> MIMTXWDATA[32]) = (0, 0); + ( USERCLK *> MIMTXWDATA[33]) = (0, 0); + ( USERCLK *> MIMTXWDATA[34]) = (0, 0); + ( USERCLK *> MIMTXWDATA[35]) = (0, 0); + ( USERCLK *> MIMTXWDATA[36]) = (0, 0); + ( USERCLK *> MIMTXWDATA[37]) = (0, 0); + ( USERCLK *> MIMTXWDATA[38]) = (0, 0); + ( USERCLK *> MIMTXWDATA[39]) = (0, 0); + ( USERCLK *> MIMTXWDATA[3]) = (0, 0); + ( USERCLK *> MIMTXWDATA[40]) = (0, 0); + ( USERCLK *> MIMTXWDATA[41]) = (0, 0); + ( USERCLK *> MIMTXWDATA[42]) = (0, 0); + ( USERCLK *> MIMTXWDATA[43]) = (0, 0); + ( USERCLK *> MIMTXWDATA[44]) = (0, 0); + ( USERCLK *> MIMTXWDATA[45]) = (0, 0); + ( USERCLK *> MIMTXWDATA[46]) = (0, 0); + ( USERCLK *> MIMTXWDATA[47]) = (0, 0); + ( USERCLK *> MIMTXWDATA[48]) = (0, 0); + ( USERCLK *> MIMTXWDATA[49]) = (0, 0); + ( USERCLK *> MIMTXWDATA[4]) = (0, 0); + ( USERCLK *> MIMTXWDATA[50]) = (0, 0); + ( USERCLK *> MIMTXWDATA[51]) = (0, 0); + ( USERCLK *> MIMTXWDATA[52]) = (0, 0); + ( USERCLK *> MIMTXWDATA[53]) = (0, 0); + ( USERCLK *> MIMTXWDATA[54]) = (0, 0); + ( USERCLK *> MIMTXWDATA[55]) = (0, 0); + ( USERCLK *> MIMTXWDATA[56]) = (0, 0); + ( USERCLK *> MIMTXWDATA[57]) = (0, 0); + ( USERCLK *> MIMTXWDATA[58]) = (0, 0); + ( USERCLK *> MIMTXWDATA[59]) = (0, 0); + ( USERCLK *> MIMTXWDATA[5]) = (0, 0); + ( USERCLK *> MIMTXWDATA[60]) = (0, 0); + ( USERCLK *> MIMTXWDATA[61]) = (0, 0); + ( USERCLK *> MIMTXWDATA[62]) = (0, 0); + ( USERCLK *> MIMTXWDATA[63]) = (0, 0); + ( USERCLK *> MIMTXWDATA[64]) = (0, 0); + ( USERCLK *> MIMTXWDATA[65]) = (0, 0); + ( USERCLK *> MIMTXWDATA[66]) = (0, 0); + ( USERCLK *> MIMTXWDATA[67]) = (0, 0); + ( USERCLK *> MIMTXWDATA[68]) = (0, 0); + ( USERCLK *> MIMTXWDATA[6]) = (0, 0); + ( USERCLK *> MIMTXWDATA[7]) = (0, 0); + ( USERCLK *> MIMTXWDATA[8]) = (0, 0); + ( USERCLK *> MIMTXWDATA[9]) = (0, 0); + ( USERCLK *> MIMTXWEN) = (0, 0); + ( USERCLK2 *> CFGAERECRCCHECKEN) = (0, 0); + ( USERCLK2 *> CFGAERECRCGENEN) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRCORRERRRECEIVED) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRCORRERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRFATALERRRECEIVED) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRFATALERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRNONFATALERRRECEIVED) = (0, 0); + ( USERCLK2 *> CFGAERROOTERRNONFATALERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGBRIDGESERREN) = (0, 0); + ( USERCLK2 *> CFGCOMMANDBUSMASTERENABLE) = (0, 0); + ( USERCLK2 *> CFGCOMMANDINTERRUPTDISABLE) = (0, 0); + ( USERCLK2 *> CFGCOMMANDIOENABLE) = (0, 0); + ( USERCLK2 *> CFGCOMMANDMEMENABLE) = (0, 0); + ( USERCLK2 *> CFGCOMMANDSERREN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2ARIFORWARDEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2ATOMICEGRESSBLOCK) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2ATOMICREQUESTEREN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTDIS) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[0]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[1]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[2]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[3]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2IDOCPLEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2IDOREQEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2LTREN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROL2TLPPREFIXBLOCK) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLAUXPOWEREN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLCORRERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLENABLERO) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLEXTTAGEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLFATALERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[0]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[1]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[2]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[0]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[1]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[2]) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLNONFATALREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLNOSNOOPEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLPHANTOMEN) = (0, 0); + ( USERCLK2 *> CFGDEVCONTROLURERRREPORTINGEN) = (0, 0); + ( USERCLK2 *> CFGDEVSTATUSCORRERRDETECTED) = (0, 0); + ( USERCLK2 *> CFGDEVSTATUSFATALERRDETECTED) = (0, 0); + ( USERCLK2 *> CFGDEVSTATUSNONFATALERRDETECTED) = (0, 0); + ( USERCLK2 *> CFGDEVSTATUSURDETECTED) = (0, 0); + ( USERCLK2 *> CFGERRAERHEADERLOGSETN) = (0, 0); + ( USERCLK2 *> CFGERRCPLRDYN) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[0]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[1]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[2]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[3]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[4]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[5]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[6]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTDO[7]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMMENABLE[0]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMMENABLE[1]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMMENABLE[2]) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMSIENABLE) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMSIXENABLE) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTMSIXFM) = (0, 0); + ( USERCLK2 *> CFGINTERRUPTRDYN) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[0]) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[1]) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLAUTOBANDWIDTHINTEN) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLBANDWIDTHINTEN) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLCLOCKPMEN) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLCOMMONCLOCK) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLEXTENDEDSYNC) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLHWAUTOWIDTHDIS) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLLINKDISABLE) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLRCB) = (0, 0); + ( USERCLK2 *> CFGLINKCONTROLRETRAINLINK) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSAUTOBANDWIDTHSTATUS) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSBANDWIDTHSTATUS) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[0]) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[1]) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSDLLACTIVE) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSLINKTRAINING) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[0]) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[1]) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[2]) = (0, 0); + ( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[3]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[0]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[10]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[11]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[12]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[13]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[14]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[15]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[16]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[17]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[18]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[19]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[1]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[20]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[21]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[22]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[23]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[24]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[25]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[26]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[27]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[28]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[29]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[2]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[30]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[31]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[3]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[4]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[5]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[6]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[7]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[8]) = (0, 0); + ( USERCLK2 *> CFGMGMTDO[9]) = (0, 0); + ( USERCLK2 *> CFGMGMTRDWRDONEN) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[0]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[10]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[11]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[12]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[13]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[14]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[15]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[1]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[2]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[3]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[4]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[5]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[6]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[7]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[8]) = (0, 0); + ( USERCLK2 *> CFGMSGDATA[9]) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVED) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDASSERTINTA) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDASSERTINTB) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDASSERTINTC) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDASSERTINTD) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTA) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTB) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTC) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTD) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDERRCOR) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDERRFATAL) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDERRNONFATAL) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDPMASNAK) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDPMETO) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDPMETOACK) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDPMPME) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDSETSLOTPOWERLIMIT) = (0, 0); + ( USERCLK2 *> CFGMSGRECEIVEDUNLOCK) = (0, 0); + ( USERCLK2 *> CFGPCIELINKSTATE[0]) = (0, 0); + ( USERCLK2 *> CFGPCIELINKSTATE[1]) = (0, 0); + ( USERCLK2 *> CFGPCIELINKSTATE[2]) = (0, 0); + ( USERCLK2 *> CFGPMCSRPMEEN) = (0, 0); + ( USERCLK2 *> CFGPMCSRPMESTATUS) = (0, 0); + ( USERCLK2 *> CFGPMCSRPOWERSTATE[0]) = (0, 0); + ( USERCLK2 *> CFGPMCSRPOWERSTATE[1]) = (0, 0); + ( USERCLK2 *> CFGPMRCVASREQL1N) = (0, 0); + ( USERCLK2 *> CFGPMRCVENTERL1N) = (0, 0); + ( USERCLK2 *> CFGPMRCVENTERL23N) = (0, 0); + ( USERCLK2 *> CFGPMRCVREQACKN) = (0, 0); + ( USERCLK2 *> CFGROOTCONTROLPMEINTEN) = (0, 0); + ( USERCLK2 *> CFGROOTCONTROLSYSERRCORRERREN) = (0, 0); + ( USERCLK2 *> CFGROOTCONTROLSYSERRFATALERREN) = (0, 0); + ( USERCLK2 *> CFGROOTCONTROLSYSERRNONFATALERREN) = (0, 0); + ( USERCLK2 *> CFGSLOTCONTROLELECTROMECHILCTLPULSE) = (0, 0); + ( USERCLK2 *> CFGTRANSACTION) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[0]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[1]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[2]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[3]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[4]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[5]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONADDR[6]) = (0, 0); + ( USERCLK2 *> CFGTRANSACTIONTYPE) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[0]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[1]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[2]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[3]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[4]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[5]) = (0, 0); + ( USERCLK2 *> CFGVCTCVCMAP[6]) = (0, 0); + ( USERCLK2 *> DBGSCLRA) = (0, 0); + ( USERCLK2 *> DBGSCLRB) = (0, 0); + ( USERCLK2 *> DBGSCLRC) = (0, 0); + ( USERCLK2 *> DBGSCLRD) = (0, 0); + ( USERCLK2 *> DBGSCLRE) = (0, 0); + ( USERCLK2 *> DBGSCLRF) = (0, 0); + ( USERCLK2 *> DBGSCLRG) = (0, 0); + ( USERCLK2 *> DBGSCLRH) = (0, 0); + ( USERCLK2 *> DBGSCLRI) = (0, 0); + ( USERCLK2 *> DBGSCLRJ) = (0, 0); + ( USERCLK2 *> DBGSCLRK) = (0, 0); + ( USERCLK2 *> DBGVECA[0]) = (0, 0); + ( USERCLK2 *> DBGVECA[10]) = (0, 0); + ( USERCLK2 *> DBGVECA[11]) = (0, 0); + ( USERCLK2 *> DBGVECA[12]) = (0, 0); + ( USERCLK2 *> DBGVECA[13]) = (0, 0); + ( USERCLK2 *> DBGVECA[14]) = (0, 0); + ( USERCLK2 *> DBGVECA[15]) = (0, 0); + ( USERCLK2 *> DBGVECA[16]) = (0, 0); + ( USERCLK2 *> DBGVECA[17]) = (0, 0); + ( USERCLK2 *> DBGVECA[18]) = (0, 0); + ( USERCLK2 *> DBGVECA[19]) = (0, 0); + ( USERCLK2 *> DBGVECA[1]) = (0, 0); + ( USERCLK2 *> DBGVECA[20]) = (0, 0); + ( USERCLK2 *> DBGVECA[21]) = (0, 0); + ( USERCLK2 *> DBGVECA[22]) = (0, 0); + ( USERCLK2 *> DBGVECA[23]) = (0, 0); + ( USERCLK2 *> DBGVECA[24]) = (0, 0); + ( USERCLK2 *> DBGVECA[25]) = (0, 0); + ( USERCLK2 *> DBGVECA[26]) = (0, 0); + ( USERCLK2 *> DBGVECA[27]) = (0, 0); + ( USERCLK2 *> DBGVECA[28]) = (0, 0); + ( USERCLK2 *> DBGVECA[29]) = (0, 0); + ( USERCLK2 *> DBGVECA[2]) = (0, 0); + ( USERCLK2 *> DBGVECA[30]) = (0, 0); + ( USERCLK2 *> DBGVECA[31]) = (0, 0); + ( USERCLK2 *> DBGVECA[32]) = (0, 0); + ( USERCLK2 *> DBGVECA[33]) = (0, 0); + ( USERCLK2 *> DBGVECA[34]) = (0, 0); + ( USERCLK2 *> DBGVECA[35]) = (0, 0); + ( USERCLK2 *> DBGVECA[36]) = (0, 0); + ( USERCLK2 *> DBGVECA[37]) = (0, 0); + ( USERCLK2 *> DBGVECA[38]) = (0, 0); + ( USERCLK2 *> DBGVECA[39]) = (0, 0); + ( USERCLK2 *> DBGVECA[3]) = (0, 0); + ( USERCLK2 *> DBGVECA[40]) = (0, 0); + ( USERCLK2 *> DBGVECA[41]) = (0, 0); + ( USERCLK2 *> DBGVECA[42]) = (0, 0); + ( USERCLK2 *> DBGVECA[43]) = (0, 0); + ( USERCLK2 *> DBGVECA[44]) = (0, 0); + ( USERCLK2 *> DBGVECA[45]) = (0, 0); + ( USERCLK2 *> DBGVECA[46]) = (0, 0); + ( USERCLK2 *> DBGVECA[47]) = (0, 0); + ( USERCLK2 *> DBGVECA[48]) = (0, 0); + ( USERCLK2 *> DBGVECA[49]) = (0, 0); + ( USERCLK2 *> DBGVECA[4]) = (0, 0); + ( USERCLK2 *> DBGVECA[50]) = (0, 0); + ( USERCLK2 *> DBGVECA[51]) = (0, 0); + ( USERCLK2 *> DBGVECA[52]) = (0, 0); + ( USERCLK2 *> DBGVECA[53]) = (0, 0); + ( USERCLK2 *> DBGVECA[54]) = (0, 0); + ( USERCLK2 *> DBGVECA[55]) = (0, 0); + ( USERCLK2 *> DBGVECA[56]) = (0, 0); + ( USERCLK2 *> DBGVECA[57]) = (0, 0); + ( USERCLK2 *> DBGVECA[58]) = (0, 0); + ( USERCLK2 *> DBGVECA[59]) = (0, 0); + ( USERCLK2 *> DBGVECA[5]) = (0, 0); + ( USERCLK2 *> DBGVECA[60]) = (0, 0); + ( USERCLK2 *> DBGVECA[61]) = (0, 0); + ( USERCLK2 *> DBGVECA[62]) = (0, 0); + ( USERCLK2 *> DBGVECA[63]) = (0, 0); + ( USERCLK2 *> DBGVECA[6]) = (0, 0); + ( USERCLK2 *> DBGVECA[7]) = (0, 0); + ( USERCLK2 *> DBGVECA[8]) = (0, 0); + ( USERCLK2 *> DBGVECA[9]) = (0, 0); + ( USERCLK2 *> DBGVECB[0]) = (0, 0); + ( USERCLK2 *> DBGVECB[10]) = (0, 0); + ( USERCLK2 *> DBGVECB[11]) = (0, 0); + ( USERCLK2 *> DBGVECB[12]) = (0, 0); + ( USERCLK2 *> DBGVECB[13]) = (0, 0); + ( USERCLK2 *> DBGVECB[14]) = (0, 0); + ( USERCLK2 *> DBGVECB[15]) = (0, 0); + ( USERCLK2 *> DBGVECB[16]) = (0, 0); + ( USERCLK2 *> DBGVECB[17]) = (0, 0); + ( USERCLK2 *> DBGVECB[18]) = (0, 0); + ( USERCLK2 *> DBGVECB[19]) = (0, 0); + ( USERCLK2 *> DBGVECB[1]) = (0, 0); + ( USERCLK2 *> DBGVECB[20]) = (0, 0); + ( USERCLK2 *> DBGVECB[21]) = (0, 0); + ( USERCLK2 *> DBGVECB[22]) = (0, 0); + ( USERCLK2 *> DBGVECB[23]) = (0, 0); + ( USERCLK2 *> DBGVECB[24]) = (0, 0); + ( USERCLK2 *> DBGVECB[25]) = (0, 0); + ( USERCLK2 *> DBGVECB[26]) = (0, 0); + ( USERCLK2 *> DBGVECB[27]) = (0, 0); + ( USERCLK2 *> DBGVECB[28]) = (0, 0); + ( USERCLK2 *> DBGVECB[29]) = (0, 0); + ( USERCLK2 *> DBGVECB[2]) = (0, 0); + ( USERCLK2 *> DBGVECB[30]) = (0, 0); + ( USERCLK2 *> DBGVECB[31]) = (0, 0); + ( USERCLK2 *> DBGVECB[32]) = (0, 0); + ( USERCLK2 *> DBGVECB[33]) = (0, 0); + ( USERCLK2 *> DBGVECB[34]) = (0, 0); + ( USERCLK2 *> DBGVECB[35]) = (0, 0); + ( USERCLK2 *> DBGVECB[36]) = (0, 0); + ( USERCLK2 *> DBGVECB[37]) = (0, 0); + ( USERCLK2 *> DBGVECB[38]) = (0, 0); + ( USERCLK2 *> DBGVECB[39]) = (0, 0); + ( USERCLK2 *> DBGVECB[3]) = (0, 0); + ( USERCLK2 *> DBGVECB[40]) = (0, 0); + ( USERCLK2 *> DBGVECB[41]) = (0, 0); + ( USERCLK2 *> DBGVECB[42]) = (0, 0); + ( USERCLK2 *> DBGVECB[43]) = (0, 0); + ( USERCLK2 *> DBGVECB[44]) = (0, 0); + ( USERCLK2 *> DBGVECB[45]) = (0, 0); + ( USERCLK2 *> DBGVECB[46]) = (0, 0); + ( USERCLK2 *> DBGVECB[47]) = (0, 0); + ( USERCLK2 *> DBGVECB[48]) = (0, 0); + ( USERCLK2 *> DBGVECB[49]) = (0, 0); + ( USERCLK2 *> DBGVECB[4]) = (0, 0); + ( USERCLK2 *> DBGVECB[50]) = (0, 0); + ( USERCLK2 *> DBGVECB[51]) = (0, 0); + ( USERCLK2 *> DBGVECB[52]) = (0, 0); + ( USERCLK2 *> DBGVECB[53]) = (0, 0); + ( USERCLK2 *> DBGVECB[54]) = (0, 0); + ( USERCLK2 *> DBGVECB[55]) = (0, 0); + ( USERCLK2 *> DBGVECB[56]) = (0, 0); + ( USERCLK2 *> DBGVECB[57]) = (0, 0); + ( USERCLK2 *> DBGVECB[58]) = (0, 0); + ( USERCLK2 *> DBGVECB[59]) = (0, 0); + ( USERCLK2 *> DBGVECB[5]) = (0, 0); + ( USERCLK2 *> DBGVECB[60]) = (0, 0); + ( USERCLK2 *> DBGVECB[61]) = (0, 0); + ( USERCLK2 *> DBGVECB[62]) = (0, 0); + ( USERCLK2 *> DBGVECB[63]) = (0, 0); + ( USERCLK2 *> DBGVECB[6]) = (0, 0); + ( USERCLK2 *> DBGVECB[7]) = (0, 0); + ( USERCLK2 *> DBGVECB[8]) = (0, 0); + ( USERCLK2 *> DBGVECB[9]) = (0, 0); + ( USERCLK2 *> DBGVECC[0]) = (0, 0); + ( USERCLK2 *> DBGVECC[10]) = (0, 0); + ( USERCLK2 *> DBGVECC[11]) = (0, 0); + ( USERCLK2 *> DBGVECC[1]) = (0, 0); + ( USERCLK2 *> DBGVECC[2]) = (0, 0); + ( USERCLK2 *> DBGVECC[3]) = (0, 0); + ( USERCLK2 *> DBGVECC[4]) = (0, 0); + ( USERCLK2 *> DBGVECC[5]) = (0, 0); + ( USERCLK2 *> DBGVECC[6]) = (0, 0); + ( USERCLK2 *> DBGVECC[7]) = (0, 0); + ( USERCLK2 *> DBGVECC[8]) = (0, 0); + ( USERCLK2 *> DBGVECC[9]) = (0, 0); + ( USERCLK2 *> LL2BADDLLPERR) = (0, 0); + ( USERCLK2 *> LL2BADTLPERR) = (0, 0); + ( USERCLK2 *> LL2LINKSTATUS[0]) = (0, 0); + ( USERCLK2 *> LL2LINKSTATUS[1]) = (0, 0); + ( USERCLK2 *> LL2LINKSTATUS[2]) = (0, 0); + ( USERCLK2 *> LL2LINKSTATUS[3]) = (0, 0); + ( USERCLK2 *> LL2LINKSTATUS[4]) = (0, 0); + ( USERCLK2 *> LL2PROTOCOLERR) = (0, 0); + ( USERCLK2 *> LL2RECEIVERERR) = (0, 0); + ( USERCLK2 *> LL2REPLAYROERR) = (0, 0); + ( USERCLK2 *> LL2REPLAYTOERR) = (0, 0); + ( USERCLK2 *> LL2SUSPENDOK) = (0, 0); + ( USERCLK2 *> LL2TFCINIT1SEQ) = (0, 0); + ( USERCLK2 *> LL2TFCINIT2SEQ) = (0, 0); + ( USERCLK2 *> LL2TXIDLE) = (0, 0); + ( USERCLK2 *> PL2L0REQ) = (0, 0); + ( USERCLK2 *> PL2LINKUP) = (0, 0); + ( USERCLK2 *> PL2RECEIVERERR) = (0, 0); + ( USERCLK2 *> PL2RECOVERY) = (0, 0); + ( USERCLK2 *> PL2RXELECIDLE) = (0, 0); + ( USERCLK2 *> PL2RXPMSTATE[0]) = (0, 0); + ( USERCLK2 *> PL2RXPMSTATE[1]) = (0, 0); + ( USERCLK2 *> PL2SUSPENDOK) = (0, 0); + ( USERCLK2 *> RECEIVEDFUNCLVLRSTN) = (0, 0); + ( USERCLK2 *> TL2ASPMSUSPENDCREDITCHECKOK) = (0, 0); + ( USERCLK2 *> TL2ASPMSUSPENDREQ) = (0, 0); + ( USERCLK2 *> TL2ERRFCPE) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[0]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[10]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[11]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[12]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[13]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[14]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[15]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[16]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[17]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[18]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[19]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[1]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[20]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[21]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[22]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[23]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[24]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[25]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[26]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[27]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[28]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[29]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[2]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[30]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[31]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[32]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[33]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[34]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[35]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[36]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[37]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[38]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[39]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[3]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[40]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[41]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[42]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[43]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[44]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[45]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[46]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[47]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[48]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[49]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[4]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[50]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[51]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[52]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[53]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[54]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[55]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[56]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[57]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[58]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[59]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[5]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[60]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[61]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[62]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[63]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[6]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[7]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[8]) = (0, 0); + ( USERCLK2 *> TL2ERRHDR[9]) = (0, 0); + ( USERCLK2 *> TL2ERRMALFORMED) = (0, 0); + ( USERCLK2 *> TL2ERRRXOVERFLOW) = (0, 0); + ( USERCLK2 *> TL2PPMSUSPENDOK) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[0]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[10]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[11]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[1]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[2]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[3]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[4]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[5]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[6]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[7]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[8]) = (0, 0); + ( USERCLK2 *> TRNFCCPLD[9]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[0]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[1]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[2]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[3]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[4]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[5]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[6]) = (0, 0); + ( USERCLK2 *> TRNFCCPLH[7]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[0]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[10]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[11]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[1]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[2]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[3]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[4]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[5]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[6]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[7]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[8]) = (0, 0); + ( USERCLK2 *> TRNFCNPD[9]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[0]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[1]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[2]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[3]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[4]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[5]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[6]) = (0, 0); + ( USERCLK2 *> TRNFCNPH[7]) = (0, 0); + ( USERCLK2 *> TRNFCPD[0]) = (0, 0); + ( USERCLK2 *> TRNFCPD[10]) = (0, 0); + ( USERCLK2 *> TRNFCPD[11]) = (0, 0); + ( USERCLK2 *> TRNFCPD[1]) = (0, 0); + ( USERCLK2 *> TRNFCPD[2]) = (0, 0); + ( USERCLK2 *> TRNFCPD[3]) = (0, 0); + ( USERCLK2 *> TRNFCPD[4]) = (0, 0); + ( USERCLK2 *> TRNFCPD[5]) = (0, 0); + ( USERCLK2 *> TRNFCPD[6]) = (0, 0); + ( USERCLK2 *> TRNFCPD[7]) = (0, 0); + ( USERCLK2 *> TRNFCPD[8]) = (0, 0); + ( USERCLK2 *> TRNFCPD[9]) = (0, 0); + ( USERCLK2 *> TRNFCPH[0]) = (0, 0); + ( USERCLK2 *> TRNFCPH[1]) = (0, 0); + ( USERCLK2 *> TRNFCPH[2]) = (0, 0); + ( USERCLK2 *> TRNFCPH[3]) = (0, 0); + ( USERCLK2 *> TRNFCPH[4]) = (0, 0); + ( USERCLK2 *> TRNFCPH[5]) = (0, 0); + ( USERCLK2 *> TRNFCPH[6]) = (0, 0); + ( USERCLK2 *> TRNFCPH[7]) = (0, 0); + ( USERCLK2 *> TRNLNKUP) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[0]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[1]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[2]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[3]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[4]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[5]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[6]) = (0, 0); + ( USERCLK2 *> TRNRBARHIT[7]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[0]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[10]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[11]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[12]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[13]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[14]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[15]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[16]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[17]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[18]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[19]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[1]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[20]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[21]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[22]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[23]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[24]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[25]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[26]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[27]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[28]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[29]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[2]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[30]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[31]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[32]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[33]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[34]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[35]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[36]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[37]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[38]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[39]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[3]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[40]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[41]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[42]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[43]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[44]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[45]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[46]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[47]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[48]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[49]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[4]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[50]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[51]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[52]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[53]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[54]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[55]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[56]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[57]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[58]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[59]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[5]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[60]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[61]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[62]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[63]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[6]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[7]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[8]) = (0, 0); + ( USERCLK2 *> TRNRDLLPDATA[9]) = (0, 0); + ( USERCLK2 *> TRNRDLLPSRCRDY[0]) = (0, 0); + ( USERCLK2 *> TRNRDLLPSRCRDY[1]) = (0, 0); + ( USERCLK2 *> TRNRD[0]) = (0, 0); + ( USERCLK2 *> TRNRD[100]) = (0, 0); + ( USERCLK2 *> TRNRD[101]) = (0, 0); + ( USERCLK2 *> TRNRD[102]) = (0, 0); + ( USERCLK2 *> TRNRD[103]) = (0, 0); + ( USERCLK2 *> TRNRD[104]) = (0, 0); + ( USERCLK2 *> TRNRD[105]) = (0, 0); + ( USERCLK2 *> TRNRD[106]) = (0, 0); + ( USERCLK2 *> TRNRD[107]) = (0, 0); + ( USERCLK2 *> TRNRD[108]) = (0, 0); + ( USERCLK2 *> TRNRD[109]) = (0, 0); + ( USERCLK2 *> TRNRD[10]) = (0, 0); + ( USERCLK2 *> TRNRD[110]) = (0, 0); + ( USERCLK2 *> TRNRD[111]) = (0, 0); + ( USERCLK2 *> TRNRD[112]) = (0, 0); + ( USERCLK2 *> TRNRD[113]) = (0, 0); + ( USERCLK2 *> TRNRD[114]) = (0, 0); + ( USERCLK2 *> TRNRD[115]) = (0, 0); + ( USERCLK2 *> TRNRD[116]) = (0, 0); + ( USERCLK2 *> TRNRD[117]) = (0, 0); + ( USERCLK2 *> TRNRD[118]) = (0, 0); + ( USERCLK2 *> TRNRD[119]) = (0, 0); + ( USERCLK2 *> TRNRD[11]) = (0, 0); + ( USERCLK2 *> TRNRD[120]) = (0, 0); + ( USERCLK2 *> TRNRD[121]) = (0, 0); + ( USERCLK2 *> TRNRD[122]) = (0, 0); + ( USERCLK2 *> TRNRD[123]) = (0, 0); + ( USERCLK2 *> TRNRD[124]) = (0, 0); + ( USERCLK2 *> TRNRD[125]) = (0, 0); + ( USERCLK2 *> TRNRD[126]) = (0, 0); + ( USERCLK2 *> TRNRD[127]) = (0, 0); + ( USERCLK2 *> TRNRD[12]) = (0, 0); + ( USERCLK2 *> TRNRD[13]) = (0, 0); + ( USERCLK2 *> TRNRD[14]) = (0, 0); + ( USERCLK2 *> TRNRD[15]) = (0, 0); + ( USERCLK2 *> TRNRD[16]) = (0, 0); + ( USERCLK2 *> TRNRD[17]) = (0, 0); + ( USERCLK2 *> TRNRD[18]) = (0, 0); + ( USERCLK2 *> TRNRD[19]) = (0, 0); + ( USERCLK2 *> TRNRD[1]) = (0, 0); + ( USERCLK2 *> TRNRD[20]) = (0, 0); + ( USERCLK2 *> TRNRD[21]) = (0, 0); + ( USERCLK2 *> TRNRD[22]) = (0, 0); + ( USERCLK2 *> TRNRD[23]) = (0, 0); + ( USERCLK2 *> TRNRD[24]) = (0, 0); + ( USERCLK2 *> TRNRD[25]) = (0, 0); + ( USERCLK2 *> TRNRD[26]) = (0, 0); + ( USERCLK2 *> TRNRD[27]) = (0, 0); + ( USERCLK2 *> TRNRD[28]) = (0, 0); + ( USERCLK2 *> TRNRD[29]) = (0, 0); + ( USERCLK2 *> TRNRD[2]) = (0, 0); + ( USERCLK2 *> TRNRD[30]) = (0, 0); + ( USERCLK2 *> TRNRD[31]) = (0, 0); + ( USERCLK2 *> TRNRD[32]) = (0, 0); + ( USERCLK2 *> TRNRD[33]) = (0, 0); + ( USERCLK2 *> TRNRD[34]) = (0, 0); + ( USERCLK2 *> TRNRD[35]) = (0, 0); + ( USERCLK2 *> TRNRD[36]) = (0, 0); + ( USERCLK2 *> TRNRD[37]) = (0, 0); + ( USERCLK2 *> TRNRD[38]) = (0, 0); + ( USERCLK2 *> TRNRD[39]) = (0, 0); + ( USERCLK2 *> TRNRD[3]) = (0, 0); + ( USERCLK2 *> TRNRD[40]) = (0, 0); + ( USERCLK2 *> TRNRD[41]) = (0, 0); + ( USERCLK2 *> TRNRD[42]) = (0, 0); + ( USERCLK2 *> TRNRD[43]) = (0, 0); + ( USERCLK2 *> TRNRD[44]) = (0, 0); + ( USERCLK2 *> TRNRD[45]) = (0, 0); + ( USERCLK2 *> TRNRD[46]) = (0, 0); + ( USERCLK2 *> TRNRD[47]) = (0, 0); + ( USERCLK2 *> TRNRD[48]) = (0, 0); + ( USERCLK2 *> TRNRD[49]) = (0, 0); + ( USERCLK2 *> TRNRD[4]) = (0, 0); + ( USERCLK2 *> TRNRD[50]) = (0, 0); + ( USERCLK2 *> TRNRD[51]) = (0, 0); + ( USERCLK2 *> TRNRD[52]) = (0, 0); + ( USERCLK2 *> TRNRD[53]) = (0, 0); + ( USERCLK2 *> TRNRD[54]) = (0, 0); + ( USERCLK2 *> TRNRD[55]) = (0, 0); + ( USERCLK2 *> TRNRD[56]) = (0, 0); + ( USERCLK2 *> TRNRD[57]) = (0, 0); + ( USERCLK2 *> TRNRD[58]) = (0, 0); + ( USERCLK2 *> TRNRD[59]) = (0, 0); + ( USERCLK2 *> TRNRD[5]) = (0, 0); + ( USERCLK2 *> TRNRD[60]) = (0, 0); + ( USERCLK2 *> TRNRD[61]) = (0, 0); + ( USERCLK2 *> TRNRD[62]) = (0, 0); + ( USERCLK2 *> TRNRD[63]) = (0, 0); + ( USERCLK2 *> TRNRD[64]) = (0, 0); + ( USERCLK2 *> TRNRD[65]) = (0, 0); + ( USERCLK2 *> TRNRD[66]) = (0, 0); + ( USERCLK2 *> TRNRD[67]) = (0, 0); + ( USERCLK2 *> TRNRD[68]) = (0, 0); + ( USERCLK2 *> TRNRD[69]) = (0, 0); + ( USERCLK2 *> TRNRD[6]) = (0, 0); + ( USERCLK2 *> TRNRD[70]) = (0, 0); + ( USERCLK2 *> TRNRD[71]) = (0, 0); + ( USERCLK2 *> TRNRD[72]) = (0, 0); + ( USERCLK2 *> TRNRD[73]) = (0, 0); + ( USERCLK2 *> TRNRD[74]) = (0, 0); + ( USERCLK2 *> TRNRD[75]) = (0, 0); + ( USERCLK2 *> TRNRD[76]) = (0, 0); + ( USERCLK2 *> TRNRD[77]) = (0, 0); + ( USERCLK2 *> TRNRD[78]) = (0, 0); + ( USERCLK2 *> TRNRD[79]) = (0, 0); + ( USERCLK2 *> TRNRD[7]) = (0, 0); + ( USERCLK2 *> TRNRD[80]) = (0, 0); + ( USERCLK2 *> TRNRD[81]) = (0, 0); + ( USERCLK2 *> TRNRD[82]) = (0, 0); + ( USERCLK2 *> TRNRD[83]) = (0, 0); + ( USERCLK2 *> TRNRD[84]) = (0, 0); + ( USERCLK2 *> TRNRD[85]) = (0, 0); + ( USERCLK2 *> TRNRD[86]) = (0, 0); + ( USERCLK2 *> TRNRD[87]) = (0, 0); + ( USERCLK2 *> TRNRD[88]) = (0, 0); + ( USERCLK2 *> TRNRD[89]) = (0, 0); + ( USERCLK2 *> TRNRD[8]) = (0, 0); + ( USERCLK2 *> TRNRD[90]) = (0, 0); + ( USERCLK2 *> TRNRD[91]) = (0, 0); + ( USERCLK2 *> TRNRD[92]) = (0, 0); + ( USERCLK2 *> TRNRD[93]) = (0, 0); + ( USERCLK2 *> TRNRD[94]) = (0, 0); + ( USERCLK2 *> TRNRD[95]) = (0, 0); + ( USERCLK2 *> TRNRD[96]) = (0, 0); + ( USERCLK2 *> TRNRD[97]) = (0, 0); + ( USERCLK2 *> TRNRD[98]) = (0, 0); + ( USERCLK2 *> TRNRD[99]) = (0, 0); + ( USERCLK2 *> TRNRD[9]) = (0, 0); + ( USERCLK2 *> TRNRECRCERR) = (0, 0); + ( USERCLK2 *> TRNREOF) = (0, 0); + ( USERCLK2 *> TRNRERRFWD) = (0, 0); + ( USERCLK2 *> TRNRREM[0]) = (0, 0); + ( USERCLK2 *> TRNRREM[1]) = (0, 0); + ( USERCLK2 *> TRNRSOF) = (0, 0); + ( USERCLK2 *> TRNRSRCDSC) = (0, 0); + ( USERCLK2 *> TRNRSRCRDY) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[0]) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[1]) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[2]) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[3]) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[4]) = (0, 0); + ( USERCLK2 *> TRNTBUFAV[5]) = (0, 0); + ( USERCLK2 *> TRNTCFGREQ) = (0, 0); + ( USERCLK2 *> TRNTDLLPDSTRDY) = (0, 0); + ( USERCLK2 *> TRNTDSTRDY[0]) = (0, 0); + ( USERCLK2 *> TRNTDSTRDY[1]) = (0, 0); + ( USERCLK2 *> TRNTDSTRDY[2]) = (0, 0); + ( USERCLK2 *> TRNTDSTRDY[3]) = (0, 0); + ( USERCLK2 *> TRNTERRDROP) = (0, 0); + ( USERCLK2 *> USERRSTN) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule diff --git a/verilog/src/unisims/PCIE_3_0.v b/verilog/src/unisims/PCIE_3_0.v new file mode 100644 index 0000000..227931c --- /dev/null +++ b/verilog/src/unisims/PCIE_3_0.v @@ -0,0 +1,11879 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : +// / / +// /__/ /\ Filename : PCIE_3_0.uniprim.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl +// Revision: 1.0 +// 01/18/13 - 695630 - added drp monitor +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PCIE_3_0 ( + CFGCURRENTSPEED, + CFGDPASUBSTATECHANGE, + CFGERRCOROUT, + CFGERRFATALOUT, + CFGERRNONFATALOUT, + CFGEXTFUNCTIONNUMBER, + CFGEXTREADRECEIVED, + CFGEXTREGISTERNUMBER, + CFGEXTWRITEBYTEENABLE, + CFGEXTWRITEDATA, + CFGEXTWRITERECEIVED, + CFGFCCPLD, + CFGFCCPLH, + CFGFCNPD, + CFGFCNPH, + CFGFCPD, + CFGFCPH, + CFGFLRINPROCESS, + CFGFUNCTIONPOWERSTATE, + CFGFUNCTIONSTATUS, + CFGHOTRESETOUT, + CFGINPUTUPDATEDONE, + CFGINTERRUPTAOUTPUT, + CFGINTERRUPTBOUTPUT, + CFGINTERRUPTCOUTPUT, + CFGINTERRUPTDOUTPUT, + CFGINTERRUPTMSIDATA, + CFGINTERRUPTMSIENABLE, + CFGINTERRUPTMSIFAIL, + CFGINTERRUPTMSIMASKUPDATE, + CFGINTERRUPTMSIMMENABLE, + CFGINTERRUPTMSISENT, + CFGINTERRUPTMSIVFENABLE, + CFGINTERRUPTMSIXENABLE, + CFGINTERRUPTMSIXFAIL, + CFGINTERRUPTMSIXMASK, + CFGINTERRUPTMSIXSENT, + CFGINTERRUPTMSIXVFENABLE, + CFGINTERRUPTMSIXVFMASK, + CFGINTERRUPTSENT, + CFGLINKPOWERSTATE, + CFGLOCALERROR, + CFGLTRENABLE, + CFGLTSSMSTATE, + CFGMAXPAYLOAD, + CFGMAXREADREQ, + CFGMCUPDATEDONE, + CFGMGMTREADDATA, + CFGMGMTREADWRITEDONE, + CFGMSGRECEIVED, + CFGMSGRECEIVEDDATA, + CFGMSGRECEIVEDTYPE, + CFGMSGTRANSMITDONE, + CFGNEGOTIATEDWIDTH, + CFGOBFFENABLE, + CFGPERFUNCSTATUSDATA, + CFGPERFUNCTIONUPDATEDONE, + CFGPHYLINKDOWN, + CFGPHYLINKSTATUS, + CFGPLSTATUSCHANGE, + CFGPOWERSTATECHANGEINTERRUPT, + CFGRCBSTATUS, + CFGTPHFUNCTIONNUM, + CFGTPHREQUESTERENABLE, + CFGTPHSTMODE, + CFGTPHSTTADDRESS, + CFGTPHSTTREADENABLE, + CFGTPHSTTWRITEBYTEVALID, + CFGTPHSTTWRITEDATA, + CFGTPHSTTWRITEENABLE, + CFGVFFLRINPROCESS, + CFGVFPOWERSTATE, + CFGVFSTATUS, + CFGVFTPHREQUESTERENABLE, + CFGVFTPHSTMODE, + DBGDATAOUT, + DRPDO, + DRPRDY, + MAXISCQTDATA, + MAXISCQTKEEP, + MAXISCQTLAST, + MAXISCQTUSER, + MAXISCQTVALID, + MAXISRCTDATA, + MAXISRCTKEEP, + MAXISRCTLAST, + MAXISRCTUSER, + MAXISRCTVALID, + MICOMPLETIONRAMREADADDRESSAL, + MICOMPLETIONRAMREADADDRESSAU, + MICOMPLETIONRAMREADADDRESSBL, + MICOMPLETIONRAMREADADDRESSBU, + MICOMPLETIONRAMREADENABLEL, + MICOMPLETIONRAMREADENABLEU, + MICOMPLETIONRAMWRITEADDRESSAL, + MICOMPLETIONRAMWRITEADDRESSAU, + MICOMPLETIONRAMWRITEADDRESSBL, + MICOMPLETIONRAMWRITEADDRESSBU, + MICOMPLETIONRAMWRITEDATAL, + MICOMPLETIONRAMWRITEDATAU, + MICOMPLETIONRAMWRITEENABLEL, + MICOMPLETIONRAMWRITEENABLEU, + MIREPLAYRAMADDRESS, + MIREPLAYRAMREADENABLE, + MIREPLAYRAMWRITEDATA, + MIREPLAYRAMWRITEENABLE, + MIREQUESTRAMREADADDRESSA, + MIREQUESTRAMREADADDRESSB, + MIREQUESTRAMREADENABLE, + MIREQUESTRAMWRITEADDRESSA, + MIREQUESTRAMWRITEADDRESSB, + MIREQUESTRAMWRITEDATA, + MIREQUESTRAMWRITEENABLE, + PCIECQNPREQCOUNT, + PCIERQSEQNUM, + PCIERQSEQNUMVLD, + PCIERQTAG, + PCIERQTAGAV, + PCIERQTAGVLD, + PCIETFCNPDAV, + PCIETFCNPHAV, + PIPERX0EQCONTROL, + PIPERX0EQLPLFFS, + PIPERX0EQLPTXPRESET, + PIPERX0EQPRESET, + PIPERX0POLARITY, + PIPERX1EQCONTROL, + PIPERX1EQLPLFFS, + PIPERX1EQLPTXPRESET, + PIPERX1EQPRESET, + PIPERX1POLARITY, + PIPERX2EQCONTROL, + PIPERX2EQLPLFFS, + PIPERX2EQLPTXPRESET, + PIPERX2EQPRESET, + PIPERX2POLARITY, + PIPERX3EQCONTROL, + PIPERX3EQLPLFFS, + PIPERX3EQLPTXPRESET, + PIPERX3EQPRESET, + PIPERX3POLARITY, + PIPERX4EQCONTROL, + PIPERX4EQLPLFFS, + PIPERX4EQLPTXPRESET, + PIPERX4EQPRESET, + PIPERX4POLARITY, + PIPERX5EQCONTROL, + PIPERX5EQLPLFFS, + PIPERX5EQLPTXPRESET, + PIPERX5EQPRESET, + PIPERX5POLARITY, + PIPERX6EQCONTROL, + PIPERX6EQLPLFFS, + PIPERX6EQLPTXPRESET, + PIPERX6EQPRESET, + PIPERX6POLARITY, + PIPERX7EQCONTROL, + PIPERX7EQLPLFFS, + PIPERX7EQLPTXPRESET, + PIPERX7EQPRESET, + PIPERX7POLARITY, + PIPETX0CHARISK, + PIPETX0COMPLIANCE, + PIPETX0DATA, + PIPETX0DATAVALID, + PIPETX0ELECIDLE, + PIPETX0EQCONTROL, + PIPETX0EQDEEMPH, + PIPETX0EQPRESET, + PIPETX0POWERDOWN, + PIPETX0STARTBLOCK, + PIPETX0SYNCHEADER, + PIPETX1CHARISK, + PIPETX1COMPLIANCE, + PIPETX1DATA, + PIPETX1DATAVALID, + PIPETX1ELECIDLE, + PIPETX1EQCONTROL, + PIPETX1EQDEEMPH, + PIPETX1EQPRESET, + PIPETX1POWERDOWN, + PIPETX1STARTBLOCK, + PIPETX1SYNCHEADER, + PIPETX2CHARISK, + PIPETX2COMPLIANCE, + PIPETX2DATA, + PIPETX2DATAVALID, + PIPETX2ELECIDLE, + PIPETX2EQCONTROL, + PIPETX2EQDEEMPH, + PIPETX2EQPRESET, + PIPETX2POWERDOWN, + PIPETX2STARTBLOCK, + PIPETX2SYNCHEADER, + PIPETX3CHARISK, + PIPETX3COMPLIANCE, + PIPETX3DATA, + PIPETX3DATAVALID, + PIPETX3ELECIDLE, + PIPETX3EQCONTROL, + PIPETX3EQDEEMPH, + PIPETX3EQPRESET, + PIPETX3POWERDOWN, + PIPETX3STARTBLOCK, + PIPETX3SYNCHEADER, + PIPETX4CHARISK, + PIPETX4COMPLIANCE, + PIPETX4DATA, + PIPETX4DATAVALID, + PIPETX4ELECIDLE, + PIPETX4EQCONTROL, + PIPETX4EQDEEMPH, + PIPETX4EQPRESET, + PIPETX4POWERDOWN, + PIPETX4STARTBLOCK, + PIPETX4SYNCHEADER, + PIPETX5CHARISK, + PIPETX5COMPLIANCE, + PIPETX5DATA, + PIPETX5DATAVALID, + PIPETX5ELECIDLE, + PIPETX5EQCONTROL, + PIPETX5EQDEEMPH, + PIPETX5EQPRESET, + PIPETX5POWERDOWN, + PIPETX5STARTBLOCK, + PIPETX5SYNCHEADER, + PIPETX6CHARISK, + PIPETX6COMPLIANCE, + PIPETX6DATA, + PIPETX6DATAVALID, + PIPETX6ELECIDLE, + PIPETX6EQCONTROL, + PIPETX6EQDEEMPH, + PIPETX6EQPRESET, + PIPETX6POWERDOWN, + PIPETX6STARTBLOCK, + PIPETX6SYNCHEADER, + PIPETX7CHARISK, + PIPETX7COMPLIANCE, + PIPETX7DATA, + PIPETX7DATAVALID, + PIPETX7ELECIDLE, + PIPETX7EQCONTROL, + PIPETX7EQDEEMPH, + PIPETX7EQPRESET, + PIPETX7POWERDOWN, + PIPETX7STARTBLOCK, + PIPETX7SYNCHEADER, + PIPETXDEEMPH, + PIPETXMARGIN, + PIPETXRATE, + PIPETXRCVRDET, + PIPETXRESET, + PIPETXSWING, + PLEQINPROGRESS, + PLEQPHASE, + PLGEN3PCSRXSLIDE, + SAXISCCTREADY, + SAXISRQTREADY, + + CFGCONFIGSPACEENABLE, + CFGDEVID, + CFGDSBUSNUMBER, + CFGDSDEVICENUMBER, + CFGDSFUNCTIONNUMBER, + CFGDSN, + CFGDSPORTNUMBER, + CFGERRCORIN, + CFGERRUNCORIN, + CFGEXTREADDATA, + CFGEXTREADDATAVALID, + CFGFCSEL, + CFGFLRDONE, + CFGHOTRESETIN, + CFGINPUTUPDATEREQUEST, + CFGINTERRUPTINT, + CFGINTERRUPTMSIATTR, + CFGINTERRUPTMSIFUNCTIONNUMBER, + CFGINTERRUPTMSIINT, + CFGINTERRUPTMSIPENDINGSTATUS, + CFGINTERRUPTMSISELECT, + CFGINTERRUPTMSITPHPRESENT, + CFGINTERRUPTMSITPHSTTAG, + CFGINTERRUPTMSITPHTYPE, + CFGINTERRUPTMSIXADDRESS, + CFGINTERRUPTMSIXDATA, + CFGINTERRUPTMSIXINT, + CFGINTERRUPTPENDING, + CFGLINKTRAININGENABLE, + CFGMCUPDATEREQUEST, + CFGMGMTADDR, + CFGMGMTBYTEENABLE, + CFGMGMTREAD, + CFGMGMTTYPE1CFGREGACCESS, + CFGMGMTWRITE, + CFGMGMTWRITEDATA, + CFGMSGTRANSMIT, + CFGMSGTRANSMITDATA, + CFGMSGTRANSMITTYPE, + CFGPERFUNCSTATUSCONTROL, + CFGPERFUNCTIONNUMBER, + CFGPERFUNCTIONOUTPUTREQUEST, + CFGPOWERSTATECHANGEACK, + CFGREQPMTRANSITIONL23READY, + CFGREVID, + CFGSUBSYSID, + CFGSUBSYSVENDID, + CFGTPHSTTREADDATA, + CFGTPHSTTREADDATAVALID, + CFGVENDID, + CFGVFFLRDONE, + CORECLK, + CORECLKMICOMPLETIONRAML, + CORECLKMICOMPLETIONRAMU, + CORECLKMIREPLAYRAM, + CORECLKMIREQUESTRAM, + DRPADDR, + DRPCLK, + DRPDI, + DRPEN, + DRPWE, + MAXISCQTREADY, + MAXISRCTREADY, + MGMTRESETN, + MGMTSTICKYRESETN, + MICOMPLETIONRAMREADDATA, + MIREPLAYRAMREADDATA, + MIREQUESTRAMREADDATA, + PCIECQNPREQ, + PIPECLK, + PIPEEQFS, + PIPEEQLF, + PIPERESETN, + PIPERX0CHARISK, + PIPERX0DATA, + PIPERX0DATAVALID, + PIPERX0ELECIDLE, + PIPERX0EQDONE, + PIPERX0EQLPADAPTDONE, + PIPERX0EQLPLFFSSEL, + PIPERX0EQLPNEWTXCOEFFORPRESET, + PIPERX0PHYSTATUS, + PIPERX0STARTBLOCK, + PIPERX0STATUS, + PIPERX0SYNCHEADER, + PIPERX0VALID, + PIPERX1CHARISK, + PIPERX1DATA, + PIPERX1DATAVALID, + PIPERX1ELECIDLE, + PIPERX1EQDONE, + PIPERX1EQLPADAPTDONE, + PIPERX1EQLPLFFSSEL, + PIPERX1EQLPNEWTXCOEFFORPRESET, + PIPERX1PHYSTATUS, + PIPERX1STARTBLOCK, + PIPERX1STATUS, + PIPERX1SYNCHEADER, + PIPERX1VALID, + PIPERX2CHARISK, + PIPERX2DATA, + PIPERX2DATAVALID, + PIPERX2ELECIDLE, + PIPERX2EQDONE, + PIPERX2EQLPADAPTDONE, + PIPERX2EQLPLFFSSEL, + PIPERX2EQLPNEWTXCOEFFORPRESET, + PIPERX2PHYSTATUS, + PIPERX2STARTBLOCK, + PIPERX2STATUS, + PIPERX2SYNCHEADER, + PIPERX2VALID, + PIPERX3CHARISK, + PIPERX3DATA, + PIPERX3DATAVALID, + PIPERX3ELECIDLE, + PIPERX3EQDONE, + PIPERX3EQLPADAPTDONE, + PIPERX3EQLPLFFSSEL, + PIPERX3EQLPNEWTXCOEFFORPRESET, + PIPERX3PHYSTATUS, + PIPERX3STARTBLOCK, + PIPERX3STATUS, + PIPERX3SYNCHEADER, + PIPERX3VALID, + PIPERX4CHARISK, + PIPERX4DATA, + PIPERX4DATAVALID, + PIPERX4ELECIDLE, + PIPERX4EQDONE, + PIPERX4EQLPADAPTDONE, + PIPERX4EQLPLFFSSEL, + PIPERX4EQLPNEWTXCOEFFORPRESET, + PIPERX4PHYSTATUS, + PIPERX4STARTBLOCK, + PIPERX4STATUS, + PIPERX4SYNCHEADER, + PIPERX4VALID, + PIPERX5CHARISK, + PIPERX5DATA, + PIPERX5DATAVALID, + PIPERX5ELECIDLE, + PIPERX5EQDONE, + PIPERX5EQLPADAPTDONE, + PIPERX5EQLPLFFSSEL, + PIPERX5EQLPNEWTXCOEFFORPRESET, + PIPERX5PHYSTATUS, + PIPERX5STARTBLOCK, + PIPERX5STATUS, + PIPERX5SYNCHEADER, + PIPERX5VALID, + PIPERX6CHARISK, + PIPERX6DATA, + PIPERX6DATAVALID, + PIPERX6ELECIDLE, + PIPERX6EQDONE, + PIPERX6EQLPADAPTDONE, + PIPERX6EQLPLFFSSEL, + PIPERX6EQLPNEWTXCOEFFORPRESET, + PIPERX6PHYSTATUS, + PIPERX6STARTBLOCK, + PIPERX6STATUS, + PIPERX6SYNCHEADER, + PIPERX6VALID, + PIPERX7CHARISK, + PIPERX7DATA, + PIPERX7DATAVALID, + PIPERX7ELECIDLE, + PIPERX7EQDONE, + PIPERX7EQLPADAPTDONE, + PIPERX7EQLPLFFSSEL, + PIPERX7EQLPNEWTXCOEFFORPRESET, + PIPERX7PHYSTATUS, + PIPERX7STARTBLOCK, + PIPERX7STATUS, + PIPERX7SYNCHEADER, + PIPERX7VALID, + PIPETX0EQCOEFF, + PIPETX0EQDONE, + PIPETX1EQCOEFF, + PIPETX1EQDONE, + PIPETX2EQCOEFF, + PIPETX2EQDONE, + PIPETX3EQCOEFF, + PIPETX3EQDONE, + PIPETX4EQCOEFF, + PIPETX4EQDONE, + PIPETX5EQCOEFF, + PIPETX5EQDONE, + PIPETX6EQCOEFF, + PIPETX6EQDONE, + PIPETX7EQCOEFF, + PIPETX7EQDONE, + PLDISABLESCRAMBLER, + PLEQRESETEIEOSCOUNT, + PLGEN3PCSDISABLE, + PLGEN3PCSRXSYNCDONE, + RECCLK, + RESETN, + SAXISCCTDATA, + SAXISCCTKEEP, + SAXISCCTLAST, + SAXISCCTUSER, + SAXISCCTVALID, + SAXISRQTDATA, + SAXISRQTKEEP, + SAXISRQTLAST, + SAXISRQTUSER, + SAXISRQTVALID, + USERCLK +); + + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED"; + `endif + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1; + parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_BIST_REGISTER = 8'h00; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter [15:0] PF0_DEVICE_ID = 16'h0000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF0_DPA_CAP_VER = 4'h1; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF0_PB_CAP_VER = 4'h1; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter PF0_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF0_RBAR_NUM = 3'h1; + parameter [7:0] PF0_REVISION_ID = 8'h00; + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_BIST_REGISTER = 8'h00; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [15:0] PF1_DEVICE_ID = 16'h0000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF1_DPA_CAP_VER = 4'h1; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF1_PB_CAP_VER = 4'h1; + parameter [7:0] PF1_PM_CAP_ID = 8'h01; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; + parameter PF1_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF1_RBAR_NUM = 3'h1; + parameter [7:0] PF1_REVISION_ID = 8'h00; + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF1_TPHR_CAP_ENABLE = "FALSE"; + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_SCRAMBLING = "FALSE"; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; + parameter integer PL_N_FTS_COMCLK_GEN1 = 255; + parameter integer PL_N_FTS_COMCLK_GEN2 = 255; + parameter integer PL_N_FTS_COMCLK_GEN3 = 255; + parameter integer PL_N_FTS_GEN1 = 255; + parameter integer PL_N_FTS_GEN2 = 255; + parameter integer PL_N_FTS_GEN3 = 255; + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; + parameter SIM_VERSION = "1.0"; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SRIOV_CAP_ENABLE = "FALSE"; + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000; + parameter [11:0] TL_CREDITS_CD = 12'h3E0; + parameter [7:0] TL_CREDITS_CH = 8'h20; + parameter [11:0] TL_CREDITS_NPD = 12'h028; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h198; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_MODE_ENABLE = "FALSE"; + parameter TL_PF_ENABLE_REG = "FALSE"; + parameter TL_TAG_MGMT_ENABLE = "TRUE"; + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; + parameter integer VF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF0_PM_CAP_ID = 8'h01; + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF0_TPHR_CAP_ENABLE = "FALSE"; + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF1_PM_CAP_ID = 8'h01; + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF1_TPHR_CAP_ENABLE = "FALSE"; + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF2_PM_CAP_ID = 8'h01; + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF2_TPHR_CAP_ENABLE = "FALSE"; + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF3_PM_CAP_ID = 8'h01; + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF3_TPHR_CAP_ENABLE = "FALSE"; + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF4_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF4_PM_CAP_ID = 8'h01; + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF4_TPHR_CAP_ENABLE = "FALSE"; + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF5_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF5_PM_CAP_ID = 8'h01; + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF5_TPHR_CAP_ENABLE = "FALSE"; + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output CFGEXTREADRECEIVED; + output CFGEXTWRITERECEIVED; + output CFGHOTRESETOUT; + output CFGINPUTUPDATEDONE; + output CFGINTERRUPTAOUTPUT; + output CFGINTERRUPTBOUTPUT; + output CFGINTERRUPTCOUTPUT; + output CFGINTERRUPTDOUTPUT; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output CFGINTERRUPTMSISENT; + output CFGINTERRUPTMSIXFAIL; + output CFGINTERRUPTMSIXSENT; + output CFGINTERRUPTSENT; + output CFGLOCALERROR; + output CFGLTRENABLE; + output CFGMCUPDATEDONE; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output CFGMSGTRANSMITDONE; + output CFGPERFUNCTIONUPDATEDONE; + output CFGPHYLINKDOWN; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output CFGTPHSTTREADENABLE; + output CFGTPHSTTWRITEENABLE; + output DRPRDY; + output MAXISCQTLAST; + output MAXISCQTVALID; + output MAXISRCTLAST; + output MAXISRCTVALID; + output PCIERQSEQNUMVLD; + output PCIERQTAGVLD; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0DATAVALID; + output PIPETX0ELECIDLE; + output PIPETX0STARTBLOCK; + output PIPETX1COMPLIANCE; + output PIPETX1DATAVALID; + output PIPETX1ELECIDLE; + output PIPETX1STARTBLOCK; + output PIPETX2COMPLIANCE; + output PIPETX2DATAVALID; + output PIPETX2ELECIDLE; + output PIPETX2STARTBLOCK; + output PIPETX3COMPLIANCE; + output PIPETX3DATAVALID; + output PIPETX3ELECIDLE; + output PIPETX3STARTBLOCK; + output PIPETX4COMPLIANCE; + output PIPETX4DATAVALID; + output PIPETX4ELECIDLE; + output PIPETX4STARTBLOCK; + output PIPETX5COMPLIANCE; + output PIPETX5DATAVALID; + output PIPETX5ELECIDLE; + output PIPETX5STARTBLOCK; + output PIPETX6COMPLIANCE; + output PIPETX6DATAVALID; + output PIPETX6ELECIDLE; + output PIPETX6STARTBLOCK; + output PIPETX7COMPLIANCE; + output PIPETX7DATAVALID; + output PIPETX7ELECIDLE; + output PIPETX7STARTBLOCK; + output PIPETXDEEMPH; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [11:0] CFGFCCPLD; + output [11:0] CFGFCNPD; + output [11:0] CFGFCPD; + output [11:0] CFGVFSTATUS; + output [143:0] MIREPLAYRAMWRITEDATA; + output [143:0] MIREQUESTRAMWRITEDATA; + output [15:0] CFGPERFUNCSTATUSDATA; + output [15:0] DBGDATAOUT; + output [15:0] DRPDO; + output [17:0] CFGVFPOWERSTATE; + output [17:0] CFGVFTPHSTMODE; + output [1:0] CFGDPASUBSTATECHANGE; + output [1:0] CFGFLRINPROCESS; + output [1:0] CFGINTERRUPTMSIENABLE; + output [1:0] CFGINTERRUPTMSIXENABLE; + output [1:0] CFGINTERRUPTMSIXMASK; + output [1:0] CFGLINKPOWERSTATE; + output [1:0] CFGOBFFENABLE; + output [1:0] CFGPHYLINKSTATUS; + output [1:0] CFGRCBSTATUS; + output [1:0] CFGTPHREQUESTERENABLE; + output [1:0] MIREPLAYRAMREADENABLE; + output [1:0] MIREPLAYRAMWRITEENABLE; + output [1:0] PCIERQTAGAV; + output [1:0] PCIETFCNPDAV; + output [1:0] PCIETFCNPHAV; + output [1:0] PIPERX0EQCONTROL; + output [1:0] PIPERX1EQCONTROL; + output [1:0] PIPERX2EQCONTROL; + output [1:0] PIPERX3EQCONTROL; + output [1:0] PIPERX4EQCONTROL; + output [1:0] PIPERX5EQCONTROL; + output [1:0] PIPERX6EQCONTROL; + output [1:0] PIPERX7EQCONTROL; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0EQCONTROL; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX0SYNCHEADER; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1EQCONTROL; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX1SYNCHEADER; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2EQCONTROL; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX2SYNCHEADER; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3EQCONTROL; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX3SYNCHEADER; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4EQCONTROL; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX4SYNCHEADER; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5EQCONTROL; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX5SYNCHEADER; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6EQCONTROL; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX6SYNCHEADER; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7EQCONTROL; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PIPETX7SYNCHEADER; + output [1:0] PIPETXRATE; + output [1:0] PLEQPHASE; + output [255:0] MAXISCQTDATA; + output [255:0] MAXISRCTDATA; + output [2:0] CFGCURRENTSPEED; + output [2:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [2:0] CFGTPHFUNCTIONNUM; + output [2:0] PIPERX0EQPRESET; + output [2:0] PIPERX1EQPRESET; + output [2:0] PIPERX2EQPRESET; + output [2:0] PIPERX3EQPRESET; + output [2:0] PIPERX4EQPRESET; + output [2:0] PIPERX5EQPRESET; + output [2:0] PIPERX6EQPRESET; + output [2:0] PIPERX7EQPRESET; + output [2:0] PIPETXMARGIN; + output [31:0] CFGEXTWRITEDATA; + output [31:0] CFGINTERRUPTMSIDATA; + output [31:0] CFGMGMTREADDATA; + output [31:0] CFGTPHSTTWRITEDATA; + output [31:0] PIPETX0DATA; + output [31:0] PIPETX1DATA; + output [31:0] PIPETX2DATA; + output [31:0] PIPETX3DATA; + output [31:0] PIPETX4DATA; + output [31:0] PIPETX5DATA; + output [31:0] PIPETX6DATA; + output [31:0] PIPETX7DATA; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [3:0] CFGNEGOTIATEDWIDTH; + output [3:0] CFGTPHSTTWRITEBYTEVALID; + output [3:0] MICOMPLETIONRAMREADENABLEL; + output [3:0] MICOMPLETIONRAMREADENABLEU; + output [3:0] MICOMPLETIONRAMWRITEENABLEL; + output [3:0] MICOMPLETIONRAMWRITEENABLEU; + output [3:0] MIREQUESTRAMREADENABLE; + output [3:0] MIREQUESTRAMWRITEENABLE; + output [3:0] PCIERQSEQNUM; + output [3:0] PIPERX0EQLPTXPRESET; + output [3:0] PIPERX1EQLPTXPRESET; + output [3:0] PIPERX2EQLPTXPRESET; + output [3:0] PIPERX3EQLPTXPRESET; + output [3:0] PIPERX4EQLPTXPRESET; + output [3:0] PIPERX5EQLPTXPRESET; + output [3:0] PIPERX6EQLPTXPRESET; + output [3:0] PIPERX7EQLPTXPRESET; + output [3:0] PIPETX0EQPRESET; + output [3:0] PIPETX1EQPRESET; + output [3:0] PIPETX2EQPRESET; + output [3:0] PIPETX3EQPRESET; + output [3:0] PIPETX4EQPRESET; + output [3:0] PIPETX5EQPRESET; + output [3:0] PIPETX6EQPRESET; + output [3:0] PIPETX7EQPRESET; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [4:0] CFGMSGRECEIVEDTYPE; + output [4:0] CFGTPHSTTADDRESS; + output [5:0] CFGFUNCTIONPOWERSTATE; + output [5:0] CFGINTERRUPTMSIMMENABLE; + output [5:0] CFGINTERRUPTMSIVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFMASK; + output [5:0] CFGLTSSMSTATE; + output [5:0] CFGTPHSTMODE; + output [5:0] CFGVFFLRINPROCESS; + output [5:0] CFGVFTPHREQUESTERENABLE; + output [5:0] PCIECQNPREQCOUNT; + output [5:0] PCIERQTAG; + output [5:0] PIPERX0EQLPLFFS; + output [5:0] PIPERX1EQLPLFFS; + output [5:0] PIPERX2EQLPLFFS; + output [5:0] PIPERX3EQLPLFFS; + output [5:0] PIPERX4EQLPLFFS; + output [5:0] PIPERX5EQLPLFFS; + output [5:0] PIPERX6EQLPLFFS; + output [5:0] PIPERX7EQLPLFFS; + output [5:0] PIPETX0EQDEEMPH; + output [5:0] PIPETX1EQDEEMPH; + output [5:0] PIPETX2EQDEEMPH; + output [5:0] PIPETX3EQDEEMPH; + output [5:0] PIPETX4EQDEEMPH; + output [5:0] PIPETX5EQDEEMPH; + output [5:0] PIPETX6EQDEEMPH; + output [5:0] PIPETX7EQDEEMPH; + output [71:0] MICOMPLETIONRAMWRITEDATAL; + output [71:0] MICOMPLETIONRAMWRITEDATAU; + output [74:0] MAXISRCTUSER; + output [7:0] CFGEXTFUNCTIONNUMBER; + output [7:0] CFGFCCPLH; + output [7:0] CFGFCNPH; + output [7:0] CFGFCPH; + output [7:0] CFGFUNCTIONSTATUS; + output [7:0] CFGMSGRECEIVEDDATA; + output [7:0] MAXISCQTKEEP; + output [7:0] MAXISRCTKEEP; + output [7:0] PLGEN3PCSRXSLIDE; + output [84:0] MAXISCQTUSER; + output [8:0] MIREPLAYRAMADDRESS; + output [8:0] MIREQUESTRAMREADADDRESSA; + output [8:0] MIREQUESTRAMREADADDRESSB; + output [8:0] MIREQUESTRAMWRITEADDRESSA; + output [8:0] MIREQUESTRAMWRITEADDRESSB; + output [9:0] CFGEXTREGISTERNUMBER; + output [9:0] MICOMPLETIONRAMREADADDRESSAL; + output [9:0] MICOMPLETIONRAMREADADDRESSAU; + output [9:0] MICOMPLETIONRAMREADADDRESSBL; + output [9:0] MICOMPLETIONRAMREADADDRESSBU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; + + input CFGCONFIGSPACEENABLE; + input CFGERRCORIN; + input CFGERRUNCORIN; + input CFGEXTREADDATAVALID; + input CFGHOTRESETIN; + input CFGINPUTUPDATEREQUEST; + input CFGINTERRUPTMSITPHPRESENT; + input CFGINTERRUPTMSIXINT; + input CFGLINKTRAININGENABLE; + input CFGMCUPDATEREQUEST; + input CFGMGMTREAD; + input CFGMGMTTYPE1CFGREGACCESS; + input CFGMGMTWRITE; + input CFGMSGTRANSMIT; + input CFGPERFUNCTIONOUTPUTREQUEST; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input CFGTPHSTTREADDATAVALID; + input CORECLK; + input CORECLKMICOMPLETIONRAML; + input CORECLKMICOMPLETIONRAMU; + input CORECLKMIREPLAYRAM; + input CORECLKMIREQUESTRAM; + input DRPCLK; + input DRPEN; + input DRPWE; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input PCIECQNPREQ; + input PIPECLK; + input PIPERESETN; + input PIPERX0DATAVALID; + input PIPERX0ELECIDLE; + input PIPERX0EQDONE; + input PIPERX0EQLPADAPTDONE; + input PIPERX0EQLPLFFSSEL; + input PIPERX0PHYSTATUS; + input PIPERX0STARTBLOCK; + input PIPERX0VALID; + input PIPERX1DATAVALID; + input PIPERX1ELECIDLE; + input PIPERX1EQDONE; + input PIPERX1EQLPADAPTDONE; + input PIPERX1EQLPLFFSSEL; + input PIPERX1PHYSTATUS; + input PIPERX1STARTBLOCK; + input PIPERX1VALID; + input PIPERX2DATAVALID; + input PIPERX2ELECIDLE; + input PIPERX2EQDONE; + input PIPERX2EQLPADAPTDONE; + input PIPERX2EQLPLFFSSEL; + input PIPERX2PHYSTATUS; + input PIPERX2STARTBLOCK; + input PIPERX2VALID; + input PIPERX3DATAVALID; + input PIPERX3ELECIDLE; + input PIPERX3EQDONE; + input PIPERX3EQLPADAPTDONE; + input PIPERX3EQLPLFFSSEL; + input PIPERX3PHYSTATUS; + input PIPERX3STARTBLOCK; + input PIPERX3VALID; + input PIPERX4DATAVALID; + input PIPERX4ELECIDLE; + input PIPERX4EQDONE; + input PIPERX4EQLPADAPTDONE; + input PIPERX4EQLPLFFSSEL; + input PIPERX4PHYSTATUS; + input PIPERX4STARTBLOCK; + input PIPERX4VALID; + input PIPERX5DATAVALID; + input PIPERX5ELECIDLE; + input PIPERX5EQDONE; + input PIPERX5EQLPADAPTDONE; + input PIPERX5EQLPLFFSSEL; + input PIPERX5PHYSTATUS; + input PIPERX5STARTBLOCK; + input PIPERX5VALID; + input PIPERX6DATAVALID; + input PIPERX6ELECIDLE; + input PIPERX6EQDONE; + input PIPERX6EQLPADAPTDONE; + input PIPERX6EQLPLFFSSEL; + input PIPERX6PHYSTATUS; + input PIPERX6STARTBLOCK; + input PIPERX6VALID; + input PIPERX7DATAVALID; + input PIPERX7ELECIDLE; + input PIPERX7EQDONE; + input PIPERX7EQLPADAPTDONE; + input PIPERX7EQLPLFFSSEL; + input PIPERX7PHYSTATUS; + input PIPERX7STARTBLOCK; + input PIPERX7VALID; + input PIPETX0EQDONE; + input PIPETX1EQDONE; + input PIPETX2EQDONE; + input PIPETX3EQDONE; + input PIPETX4EQDONE; + input PIPETX5EQDONE; + input PIPETX6EQDONE; + input PIPETX7EQDONE; + input PLDISABLESCRAMBLER; + input PLEQRESETEIEOSCOUNT; + input PLGEN3PCSDISABLE; + input RECCLK; + input RESETN; + input SAXISCCTLAST; + input SAXISCCTVALID; + input SAXISRQTLAST; + input SAXISRQTVALID; + input USERCLK; + input [10:0] DRPADDR; + input [143:0] MICOMPLETIONRAMREADDATA; + input [143:0] MIREPLAYRAMREADDATA; + input [143:0] MIREQUESTRAMREADDATA; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPETX0EQCOEFF; + input [17:0] PIPETX1EQCOEFF; + input [17:0] PIPETX2EQCOEFF; + input [17:0] PIPETX3EQCOEFF; + input [17:0] PIPETX4EQCOEFF; + input [17:0] PIPETX5EQCOEFF; + input [17:0] PIPETX6EQCOEFF; + input [17:0] PIPETX7EQCOEFF; + input [18:0] CFGMGMTADDR; + input [1:0] CFGFLRDONE; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [1:0] CFGINTERRUPTPENDING; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX0SYNCHEADER; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX1SYNCHEADER; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX2SYNCHEADER; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX3SYNCHEADER; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX4SYNCHEADER; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX5SYNCHEADER; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX6SYNCHEADER; + input [1:0] PIPERX7CHARISK; + input [1:0] PIPERX7SYNCHEADER; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input [255:0] SAXISCCTDATA; + input [255:0] SAXISRQTDATA; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFCSEL; + input [2:0] CFGINTERRUPTMSIATTR; + input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [2:0] CFGMSGTRANSMITTYPE; + input [2:0] CFGPERFUNCSTATUSCONTROL; + input [2:0] CFGPERFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [31:0] CFGEXTREADDATA; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIXDATA; + input [31:0] CFGMGMTWRITEDATA; + input [31:0] CFGMSGTRANSMITDATA; + input [31:0] CFGTPHSTTREADDATA; + input [31:0] PIPERX0DATA; + input [31:0] PIPERX1DATA; + input [31:0] PIPERX2DATA; + input [31:0] PIPERX3DATA; + input [31:0] PIPERX4DATA; + input [31:0] PIPERX5DATA; + input [31:0] PIPERX6DATA; + input [31:0] PIPERX7DATA; + input [32:0] SAXISCCTUSER; + input [3:0] CFGINTERRUPTINT; + input [3:0] CFGINTERRUPTMSISELECT; + input [3:0] CFGMGMTBYTEENABLE; + input [4:0] CFGDSDEVICENUMBER; + input [59:0] SAXISRQTUSER; + input [5:0] CFGVFFLRDONE; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input [63:0] CFGDSN; + input [63:0] CFGINTERRUPTMSIPENDINGSTATUS; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGDSPORTNUMBER; + input [7:0] CFGREVID; + input [7:0] PLGEN3PCSRXSYNCDONE; + input [7:0] SAXISCCTKEEP; + input [7:0] SAXISRQTKEEP; + input [8:0] CFGINTERRUPTMSITPHSTTAG; + + reg SIM_VERSION_BINARY; + reg [0:0] ARI_CAP_ENABLE_BINARY; + reg [0:0] AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY; + reg [0:0] AXISTEN_IF_CC_PARITY_CHK_BINARY; + reg [0:0] AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY; + reg [0:0] AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY; + reg [0:0] AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY; + reg [0:0] AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY; + reg [0:0] AXISTEN_IF_RC_STRADDLE_BINARY; + reg [0:0] AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY; + reg [0:0] AXISTEN_IF_RQ_PARITY_CHK_BINARY; + reg [0:0] CRM_CORE_CLK_FREQ_500_BINARY; + reg [0:0] GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY; + reg [0:0] LL_ACK_TIMEOUT_EN_BINARY; + reg [0:0] LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY; + reg [0:0] LL_FC_UPDATE_TIMER_OVERRIDE_BINARY; + reg [0:0] LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY; + reg [0:0] LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY; + reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY; + reg [0:0] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY; + reg [0:0] LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY; + reg [0:0] PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY; + reg [0:0] PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY; + reg [0:0] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY; + reg [0:0] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY; + reg [0:0] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY; + reg [0:0] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY; + reg [0:0] PF0_DEV_CAP2_LTR_SUPPORT_BINARY; + reg [0:0] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY; + reg [0:0] PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY; + reg [0:0] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY; + reg [0:0] PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY; + reg [0:0] PF0_EXPANSION_ROM_ENABLE_BINARY; + reg [0:0] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY; + reg [0:0] PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY; + reg [0:0] PF0_PM_CAP_PMESUPPORT_D0_BINARY; + reg [0:0] PF0_PM_CAP_PMESUPPORT_D1_BINARY; + reg [0:0] PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY; + reg [0:0] PF0_PM_CAP_SUPP_D1_STATE_BINARY; + reg [0:0] PF0_PM_CSR_NOSOFTRESET_BINARY; + reg [0:0] PF0_RBAR_CAP_ENABLE_BINARY; + reg [0:0] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] PF0_TPHR_CAP_ENABLE_BINARY; + reg [0:0] PF0_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY; + reg [0:0] PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY; + reg [0:0] PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY; + reg [0:0] PF1_EXPANSION_ROM_ENABLE_BINARY; + reg [0:0] PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY; + reg [0:0] PF1_RBAR_CAP_ENABLE_BINARY; + reg [0:0] PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] PF1_TPHR_CAP_ENABLE_BINARY; + reg [0:0] PF1_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] PL_DISABLE_EI_INFER_IN_L0_BINARY; + reg [0:0] PL_DISABLE_GEN3_DC_BALANCE_BINARY; + reg [0:0] PL_DISABLE_SCRAMBLING_BINARY; + reg [0:0] PL_DISABLE_UPCONFIG_CAPABLE_BINARY; + reg [0:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY; + reg [0:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY; + reg [0:0] PL_EQ_BYPASS_PHASE23_BINARY; + reg [0:0] PL_EQ_SHORT_ADAPT_PHASE_BINARY; + reg [0:0] PL_SIM_FAST_LINK_TRAINING_BINARY; + reg [0:0] PL_UPSTREAM_FACING_BINARY; + reg [0:0] PM_ENABLE_SLOT_POWER_CAPTURE_BINARY; + reg [0:0] SPARE_BIT0_BINARY; + reg [0:0] SPARE_BIT1_BINARY; + reg [0:0] SPARE_BIT2_BINARY; + reg [0:0] SPARE_BIT3_BINARY; + reg [0:0] SPARE_BIT4_BINARY; + reg [0:0] SPARE_BIT5_BINARY; + reg [0:0] SPARE_BIT6_BINARY; + reg [0:0] SPARE_BIT7_BINARY; + reg [0:0] SPARE_BIT8_BINARY; + reg [0:0] SRIOV_CAP_ENABLE_BINARY; + reg [0:0] TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY; + reg [0:0] TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY; + reg [0:0] TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY; + reg [0:0] TL_LEGACY_MODE_ENABLE_BINARY; + reg [0:0] TL_PF_ENABLE_REG_BINARY; + reg [0:0] TL_TAG_MGMT_ENABLE_BINARY; + reg [0:0] VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF0_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF0_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF1_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF1_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF2_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF2_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF3_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF3_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF4_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF4_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [0:0] VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY; + reg [0:0] VF5_TPHR_CAP_ENABLE_BINARY; + reg [0:0] VF5_TPHR_CAP_INT_VEC_MODE_BINARY; + reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY; + reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY; + reg [1:0] PF0_LINK_CAP_ASPM_SUPPORT_BINARY; + reg [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY; + reg [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY; + reg [2:0] PF0_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] PF0_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] PF0_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] PF1_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] PF1_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] PF1_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF0_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF0_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF0_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF1_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF1_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF1_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF2_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF2_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF2_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF3_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF3_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF3_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF4_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF4_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF4_MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] VF5_MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] VF5_MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] VF5_MSI_CAP_MULTIMSGCAP_BINARY; + reg [7:0] PL_N_FTS_COMCLK_GEN1_BINARY; + reg [7:0] PL_N_FTS_COMCLK_GEN2_BINARY; + reg [7:0] PL_N_FTS_COMCLK_GEN3_BINARY; + reg [7:0] PL_N_FTS_GEN1_BINARY; + reg [7:0] PL_N_FTS_GEN2_BINARY; + reg [7:0] PL_N_FTS_GEN3_BINARY; + + reg notifier; + + initial begin + case (ARI_CAP_ENABLE) + "FALSE" : ARI_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : ARI_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ARI_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ARI_CAP_ENABLE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_CC_ALIGNMENT_MODE) + "FALSE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CC_ALIGNMENT_MODE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_CC_PARITY_CHK) + "TRUE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b1; + "FALSE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_CC_PARITY_CHK); + #1 $finish; + end + endcase + + case (AXISTEN_IF_CQ_ALIGNMENT_MODE) + "FALSE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_CQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CQ_ALIGNMENT_MODE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_ENABLE_CLIENT_TAG) + "FALSE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_CLIENT_TAG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_CLIENT_TAG); + #1 $finish; + end + endcase + + case (AXISTEN_IF_ENABLE_RX_MSG_INTFC) + "FALSE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_RX_MSG_INTFC on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_RX_MSG_INTFC); + #1 $finish; + end + endcase + + case (AXISTEN_IF_RC_ALIGNMENT_MODE) + "FALSE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_ALIGNMENT_MODE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_RC_STRADDLE) + "FALSE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_STRADDLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_STRADDLE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_RQ_ALIGNMENT_MODE) + "FALSE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b0; + "TRUE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RQ_ALIGNMENT_MODE); + #1 $finish; + end + endcase + + case (AXISTEN_IF_RQ_PARITY_CHK) + "TRUE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b1; + "FALSE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_RQ_PARITY_CHK); + #1 $finish; + end + endcase + + case (CRM_CORE_CLK_FREQ_500) + "TRUE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b1; + "FALSE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CRM_CORE_CLK_FREQ_500 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CRM_CORE_CLK_FREQ_500); + #1 $finish; + end + endcase + + case (GEN3_PCS_RX_ELECIDLE_INTERNAL) + "TRUE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b1; + "FALSE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute GEN3_PCS_RX_ELECIDLE_INTERNAL on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", GEN3_PCS_RX_ELECIDLE_INTERNAL); + #1 $finish; + end + endcase + + case (LL_ACK_TIMEOUT_EN) + "FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN); + #1 $finish; + end + endcase + + case (LL_CPL_FC_UPDATE_TIMER_OVERRIDE) + "FALSE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0; + "TRUE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_CPL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_CPL_FC_UPDATE_TIMER_OVERRIDE); + #1 $finish; + end + endcase + + case (LL_FC_UPDATE_TIMER_OVERRIDE) + "FALSE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0; + "TRUE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_FC_UPDATE_TIMER_OVERRIDE); + #1 $finish; + end + endcase + + case (LL_NP_FC_UPDATE_TIMER_OVERRIDE) + "FALSE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0; + "TRUE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_NP_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_NP_FC_UPDATE_TIMER_OVERRIDE); + #1 $finish; + end + endcase + + case (LL_P_FC_UPDATE_TIMER_OVERRIDE) + "FALSE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0; + "TRUE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_P_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_P_FC_UPDATE_TIMER_OVERRIDE); + #1 $finish; + end + endcase + + case (LL_REPLAY_TIMEOUT_EN) + "FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN); + #1 $finish; + end + endcase + + case (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE) + "FALSE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b0; + "TRUE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE); + #1 $finish; + end + endcase + + case (LTR_TX_MESSAGE_ON_LTR_ENABLE) + "FALSE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b0; + "TRUE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_LTR_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_LTR_ENABLE); + #1 $finish; + end + endcase + + case (PF0_AER_CAP_ECRC_CHECK_CAPABLE) + "FALSE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0; + "TRUE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_CHECK_CAPABLE); + #1 $finish; + end + endcase + + case (PF0_AER_CAP_ECRC_GEN_CAPABLE) + "FALSE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0; + "TRUE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_GEN_CAPABLE); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT) + "TRUE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT) + "TRUE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT) + "TRUE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE) + "TRUE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_LTR_SUPPORT) + "TRUE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_LTR_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_LTR_SUPPORT); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT) + "FALSE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b0; + "TRUE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP_EXT_TAG_SUPPORTED) + "TRUE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_EXT_TAG_SUPPORTED); + #1 $finish; + end + endcase + + case (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE) + "TRUE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1; + "FALSE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE); + #1 $finish; + end + endcase + + case (PF0_DPA_CAP_SUB_STATE_CONTROL_EN) + "TRUE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1; + "FALSE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DPA_CAP_SUB_STATE_CONTROL_EN); + #1 $finish; + end + endcase + + case (PF0_EXPANSION_ROM_ENABLE) + "FALSE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b0; + "TRUE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_EXPANSION_ROM_ENABLE); + #1 $finish; + end + endcase + + case (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG) + "TRUE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1; + "FALSE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_LINK_STATUS_SLOT_CLOCK_CONFIG); + #1 $finish; + end + endcase + + case (PF0_PB_CAP_SYSTEM_ALLOCATED) + "FALSE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0; + "TRUE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_PB_CAP_SYSTEM_ALLOCATED); + #1 $finish; + end + endcase + + case (PF0_PM_CAP_PMESUPPORT_D0) + "TRUE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b1; + "FALSE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D0); + #1 $finish; + end + endcase + + case (PF0_PM_CAP_PMESUPPORT_D1) + "TRUE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b1; + "FALSE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D1 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D1); + #1 $finish; + end + endcase + + case (PF0_PM_CAP_PMESUPPORT_D3HOT) + "TRUE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b1; + "FALSE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D3HOT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D3HOT); + #1 $finish; + end + endcase + + case (PF0_PM_CAP_SUPP_D1_STATE) + "TRUE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b1; + "FALSE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PM_CAP_SUPP_D1_STATE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_SUPP_D1_STATE); + #1 $finish; + end + endcase + + case (PF0_PM_CSR_NOSOFTRESET) + "TRUE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b1; + "FALSE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_PM_CSR_NOSOFTRESET on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CSR_NOSOFTRESET); + #1 $finish; + end + endcase + + case (PF0_RBAR_CAP_ENABLE) + "FALSE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_RBAR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (PF0_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (PF0_TPHR_CAP_ENABLE) + "FALSE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (PF0_TPHR_CAP_INT_VEC_MODE) + "TRUE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (PF1_AER_CAP_ECRC_CHECK_CAPABLE) + "FALSE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0; + "TRUE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_CHECK_CAPABLE); + #1 $finish; + end + endcase + + case (PF1_AER_CAP_ECRC_GEN_CAPABLE) + "FALSE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0; + "TRUE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_GEN_CAPABLE); + #1 $finish; + end + endcase + + case (PF1_DPA_CAP_SUB_STATE_CONTROL_EN) + "TRUE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1; + "FALSE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_DPA_CAP_SUB_STATE_CONTROL_EN); + #1 $finish; + end + endcase + + case (PF1_EXPANSION_ROM_ENABLE) + "FALSE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b0; + "TRUE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_EXPANSION_ROM_ENABLE); + #1 $finish; + end + endcase + + case (PF1_PB_CAP_SYSTEM_ALLOCATED) + "FALSE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0; + "TRUE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_PB_CAP_SYSTEM_ALLOCATED); + #1 $finish; + end + endcase + + case (PF1_RBAR_CAP_ENABLE) + "FALSE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_RBAR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (PF1_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (PF1_TPHR_CAP_ENABLE) + "FALSE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (PF1_TPHR_CAP_INT_VEC_MODE) + "TRUE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (PL_DISABLE_EI_INFER_IN_L0) + "FALSE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b0; + "TRUE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_DISABLE_EI_INFER_IN_L0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_EI_INFER_IN_L0); + #1 $finish; + end + endcase + + case (PL_DISABLE_GEN3_DC_BALANCE) + "FALSE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b0; + "TRUE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_DISABLE_GEN3_DC_BALANCE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_GEN3_DC_BALANCE); + #1 $finish; + end + endcase + + case (PL_DISABLE_SCRAMBLING) + "FALSE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b0; + "TRUE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_DISABLE_SCRAMBLING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_SCRAMBLING); + #1 $finish; + end + endcase + + case (PL_DISABLE_UPCONFIG_CAPABLE) + "FALSE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b0; + "TRUE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_DISABLE_UPCONFIG_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_UPCONFIG_CAPABLE); + #1 $finish; + end + endcase + + case (PL_EQ_ADAPT_DISABLE_COEFF_CHECK) + "FALSE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b0; + "TRUE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_COEFF_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_COEFF_CHECK); + #1 $finish; + end + endcase + + case (PL_EQ_ADAPT_DISABLE_PRESET_CHECK) + "FALSE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b0; + "TRUE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_PRESET_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_PRESET_CHECK); + #1 $finish; + end + endcase + + case (PL_EQ_BYPASS_PHASE23) + "FALSE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b0; + "TRUE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_EQ_BYPASS_PHASE23 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_BYPASS_PHASE23); + #1 $finish; + end + endcase + + case (PL_EQ_SHORT_ADAPT_PHASE) + "FALSE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b0; + "TRUE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_EQ_SHORT_ADAPT_PHASE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_SHORT_ADAPT_PHASE); + #1 $finish; + end + endcase + + case (PL_SIM_FAST_LINK_TRAINING) + "FALSE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b0; + "TRUE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_SIM_FAST_LINK_TRAINING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_SIM_FAST_LINK_TRAINING); + #1 $finish; + end + endcase + + case (PL_UPSTREAM_FACING) + "TRUE" : PL_UPSTREAM_FACING_BINARY = 1'b1; + "FALSE" : PL_UPSTREAM_FACING_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PL_UPSTREAM_FACING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PL_UPSTREAM_FACING); + #1 $finish; + end + endcase + + case (PM_ENABLE_SLOT_POWER_CAPTURE) + "TRUE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b1; + "FALSE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PM_ENABLE_SLOT_POWER_CAPTURE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_ENABLE_SLOT_POWER_CAPTURE); + #1 $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "1.1" : SIM_VERSION_BINARY = 0; + "1.2" : SIM_VERSION_BINARY = 0; + "1.3" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + "3.0" : SIM_VERSION_BINARY = 0; + "4.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION); + #1 $finish; + end + endcase + + case (SRIOV_CAP_ENABLE) + "FALSE" : SRIOV_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : SRIOV_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SRIOV_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SRIOV_CAP_ENABLE); + #1 $finish; + end + endcase + + case (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE) + "TRUE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b1; + "FALSE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TL_ENABLE_MESSAGE_RID_CHECK_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_ENABLE_MESSAGE_RID_CHECK_ENABLE); + #1 $finish; + end + endcase + + case (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE) + "FALSE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0; + "TRUE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE); + #1 $finish; + end + endcase + + case (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE) + "FALSE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0; + "TRUE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE); + #1 $finish; + end + endcase + + case (TL_LEGACY_MODE_ENABLE) + "FALSE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b0; + "TRUE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_LEGACY_MODE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_MODE_ENABLE); + #1 $finish; + end + endcase + + case (TL_PF_ENABLE_REG) + "FALSE" : TL_PF_ENABLE_REG_BINARY = 1'b0; + "TRUE" : TL_PF_ENABLE_REG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_PF_ENABLE_REG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_PF_ENABLE_REG); + #1 $finish; + end + endcase + + case (TL_TAG_MGMT_ENABLE) + "TRUE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b1; + "FALSE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TAG_MGMT_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_TAG_MGMT_ENABLE); + #1 $finish; + end + endcase + + case (VF0_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF0_TPHR_CAP_ENABLE) + "FALSE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF0_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF0_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (VF1_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF1_TPHR_CAP_ENABLE) + "FALSE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF1_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF1_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (VF2_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF2_TPHR_CAP_ENABLE) + "FALSE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF2_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF2_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (VF3_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF3_TPHR_CAP_ENABLE) + "FALSE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF3_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF3_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (VF4_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF4_TPHR_CAP_ENABLE) + "FALSE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF4_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF4_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + case (VF5_TPHR_CAP_DEV_SPECIFIC_MODE) + "TRUE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1; + "FALSE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_DEV_SPECIFIC_MODE); + #1 $finish; + end + endcase + + case (VF5_TPHR_CAP_ENABLE) + "FALSE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b0; + "TRUE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF5_TPHR_CAP_ENABLE); + #1 $finish; + end + endcase + + case (VF5_TPHR_CAP_INT_VEC_MODE) + "TRUE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1; + "FALSE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_INT_VEC_MODE); + #1 $finish; + end + endcase + + if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3)) + LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC); + #1 $finish; + end + + if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3)) + LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC); + #1 $finish; + end + + if ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY <= 7)) + PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L0S_LATENCY); + #1 $finish; + end + + if ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L1_LATENCY <= 7)) + PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L1_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L1_LATENCY); + #1 $finish; + end + + if ((PF0_LINK_CAP_ASPM_SUPPORT >= 0) && (PF0_LINK_CAP_ASPM_SUPPORT <= 3)) + PF0_LINK_CAP_ASPM_SUPPORT_BINARY = PF0_LINK_CAP_ASPM_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_ASPM_SUPPORT on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PF0_LINK_CAP_ASPM_SUPPORT); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2); + #1 $finish; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 <= 7)) + PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2); + #1 $finish; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 <= 7)) + PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3); + #1 $finish; + end + + if ((PF0_MSIX_CAP_PBA_BIR >= 0) && (PF0_MSIX_CAP_PBA_BIR <= 7)) + PF0_MSIX_CAP_PBA_BIR_BINARY = PF0_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((PF0_MSIX_CAP_TABLE_BIR >= 0) && (PF0_MSIX_CAP_TABLE_BIR <= 7)) + PF0_MSIX_CAP_TABLE_BIR_BINARY = PF0_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((PF0_MSI_CAP_MULTIMSGCAP >= 0) && (PF0_MSI_CAP_MULTIMSGCAP <= 7)) + PF0_MSI_CAP_MULTIMSGCAP_BINARY = PF0_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute PF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((PF1_MSIX_CAP_PBA_BIR >= 0) && (PF1_MSIX_CAP_PBA_BIR <= 7)) + PF1_MSIX_CAP_PBA_BIR_BINARY = PF1_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((PF1_MSIX_CAP_TABLE_BIR >= 0) && (PF1_MSIX_CAP_TABLE_BIR <= 7)) + PF1_MSIX_CAP_TABLE_BIR_BINARY = PF1_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((PF1_MSI_CAP_MULTIMSGCAP >= 0) && (PF1_MSI_CAP_MULTIMSGCAP <= 7)) + PF1_MSI_CAP_MULTIMSGCAP_BINARY = PF1_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute PF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((PL_N_FTS_COMCLK_GEN1 >= 0) && (PL_N_FTS_COMCLK_GEN1 <= 255)) + PL_N_FTS_COMCLK_GEN1_BINARY = PL_N_FTS_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN1); + #1 $finish; + end + + if ((PL_N_FTS_COMCLK_GEN2 >= 0) && (PL_N_FTS_COMCLK_GEN2 <= 255)) + PL_N_FTS_COMCLK_GEN2_BINARY = PL_N_FTS_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN2); + #1 $finish; + end + + if ((PL_N_FTS_COMCLK_GEN3 >= 0) && (PL_N_FTS_COMCLK_GEN3 <= 255)) + PL_N_FTS_COMCLK_GEN3_BINARY = PL_N_FTS_COMCLK_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN3); + #1 $finish; + end + + if ((PL_N_FTS_GEN1 >= 0) && (PL_N_FTS_GEN1 <= 255)) + PL_N_FTS_GEN1_BINARY = PL_N_FTS_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN1); + #1 $finish; + end + + if ((PL_N_FTS_GEN2 >= 0) && (PL_N_FTS_GEN2 <= 255)) + PL_N_FTS_GEN2_BINARY = PL_N_FTS_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN2); + #1 $finish; + end + + if ((PL_N_FTS_GEN3 >= 0) && (PL_N_FTS_GEN3 <= 255)) + PL_N_FTS_GEN3_BINARY = PL_N_FTS_GEN3; + else begin + $display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN3); + #1 $finish; + end + + if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1)) + SPARE_BIT0_BINARY = SPARE_BIT0; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0); + #1 $finish; + end + + if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1)) + SPARE_BIT1_BINARY = SPARE_BIT1; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1); + #1 $finish; + end + + if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1)) + SPARE_BIT2_BINARY = SPARE_BIT2; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2); + #1 $finish; + end + + if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1)) + SPARE_BIT3_BINARY = SPARE_BIT3; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3); + #1 $finish; + end + + if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1)) + SPARE_BIT4_BINARY = SPARE_BIT4; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4); + #1 $finish; + end + + if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1)) + SPARE_BIT5_BINARY = SPARE_BIT5; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5); + #1 $finish; + end + + if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1)) + SPARE_BIT6_BINARY = SPARE_BIT6; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6); + #1 $finish; + end + + if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1)) + SPARE_BIT7_BINARY = SPARE_BIT7; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7); + #1 $finish; + end + + if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1)) + SPARE_BIT8_BINARY = SPARE_BIT8; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8); + #1 $finish; + end + + if ((VF0_MSIX_CAP_PBA_BIR >= 0) && (VF0_MSIX_CAP_PBA_BIR <= 7)) + VF0_MSIX_CAP_PBA_BIR_BINARY = VF0_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF0_MSIX_CAP_TABLE_BIR >= 0) && (VF0_MSIX_CAP_TABLE_BIR <= 7)) + VF0_MSIX_CAP_TABLE_BIR_BINARY = VF0_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF0_MSI_CAP_MULTIMSGCAP >= 0) && (VF0_MSI_CAP_MULTIMSGCAP <= 7)) + VF0_MSI_CAP_MULTIMSGCAP_BINARY = VF0_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((VF1_MSIX_CAP_PBA_BIR >= 0) && (VF1_MSIX_CAP_PBA_BIR <= 7)) + VF1_MSIX_CAP_PBA_BIR_BINARY = VF1_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF1_MSIX_CAP_TABLE_BIR >= 0) && (VF1_MSIX_CAP_TABLE_BIR <= 7)) + VF1_MSIX_CAP_TABLE_BIR_BINARY = VF1_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF1_MSI_CAP_MULTIMSGCAP >= 0) && (VF1_MSI_CAP_MULTIMSGCAP <= 7)) + VF1_MSI_CAP_MULTIMSGCAP_BINARY = VF1_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((VF2_MSIX_CAP_PBA_BIR >= 0) && (VF2_MSIX_CAP_PBA_BIR <= 7)) + VF2_MSIX_CAP_PBA_BIR_BINARY = VF2_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF2_MSIX_CAP_TABLE_BIR >= 0) && (VF2_MSIX_CAP_TABLE_BIR <= 7)) + VF2_MSIX_CAP_TABLE_BIR_BINARY = VF2_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF2_MSI_CAP_MULTIMSGCAP >= 0) && (VF2_MSI_CAP_MULTIMSGCAP <= 7)) + VF2_MSI_CAP_MULTIMSGCAP_BINARY = VF2_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF2_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((VF3_MSIX_CAP_PBA_BIR >= 0) && (VF3_MSIX_CAP_PBA_BIR <= 7)) + VF3_MSIX_CAP_PBA_BIR_BINARY = VF3_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF3_MSIX_CAP_TABLE_BIR >= 0) && (VF3_MSIX_CAP_TABLE_BIR <= 7)) + VF3_MSIX_CAP_TABLE_BIR_BINARY = VF3_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF3_MSI_CAP_MULTIMSGCAP >= 0) && (VF3_MSI_CAP_MULTIMSGCAP <= 7)) + VF3_MSI_CAP_MULTIMSGCAP_BINARY = VF3_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF3_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((VF4_MSIX_CAP_PBA_BIR >= 0) && (VF4_MSIX_CAP_PBA_BIR <= 7)) + VF4_MSIX_CAP_PBA_BIR_BINARY = VF4_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF4_MSIX_CAP_TABLE_BIR >= 0) && (VF4_MSIX_CAP_TABLE_BIR <= 7)) + VF4_MSIX_CAP_TABLE_BIR_BINARY = VF4_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF4_MSI_CAP_MULTIMSGCAP >= 0) && (VF4_MSI_CAP_MULTIMSGCAP <= 7)) + VF4_MSI_CAP_MULTIMSGCAP_BINARY = VF4_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF4_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + if ((VF5_MSIX_CAP_PBA_BIR >= 0) && (VF5_MSIX_CAP_PBA_BIR <= 7)) + VF5_MSIX_CAP_PBA_BIR_BINARY = VF5_MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_PBA_BIR); + #1 $finish; + end + + if ((VF5_MSIX_CAP_TABLE_BIR >= 0) && (VF5_MSIX_CAP_TABLE_BIR <= 7)) + VF5_MSIX_CAP_TABLE_BIR_BINARY = VF5_MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_TABLE_BIR); + #1 $finish; + end + + if ((VF5_MSI_CAP_MULTIMSGCAP >= 0) && (VF5_MSI_CAP_MULTIMSGCAP <= 7)) + VF5_MSI_CAP_MULTIMSGCAP_BINARY = VF5_MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute VF5_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSI_CAP_MULTIMSGCAP); + #1 $finish; + end + + end + + wire [11:0] delay_CFGFCCPLD; + wire [11:0] delay_CFGFCNPD; + wire [11:0] delay_CFGFCPD; + wire [11:0] delay_CFGVFSTATUS; + wire [143:0] delay_MIREPLAYRAMWRITEDATA; + wire [143:0] delay_MIREQUESTRAMWRITEDATA; + wire [15:0] delay_CFGPERFUNCSTATUSDATA; + wire [15:0] delay_DBGDATAOUT; + wire [15:0] delay_DRPDO; + wire [17:0] delay_CFGVFPOWERSTATE; + wire [17:0] delay_CFGVFTPHSTMODE; + wire [1:0] delay_CFGDPASUBSTATECHANGE; + wire [1:0] delay_CFGFLRINPROCESS; + wire [1:0] delay_CFGINTERRUPTMSIENABLE; + wire [1:0] delay_CFGINTERRUPTMSIXENABLE; + wire [1:0] delay_CFGINTERRUPTMSIXMASK; + wire [1:0] delay_CFGLINKPOWERSTATE; + wire [1:0] delay_CFGOBFFENABLE; + wire [1:0] delay_CFGPHYLINKSTATUS; + wire [1:0] delay_CFGRCBSTATUS; + wire [1:0] delay_CFGTPHREQUESTERENABLE; + wire [1:0] delay_MIREPLAYRAMREADENABLE; + wire [1:0] delay_MIREPLAYRAMWRITEENABLE; + wire [1:0] delay_PCIERQTAGAV; + wire [1:0] delay_PCIETFCNPDAV; + wire [1:0] delay_PCIETFCNPHAV; + wire [1:0] delay_PIPERX0EQCONTROL; + wire [1:0] delay_PIPERX1EQCONTROL; + wire [1:0] delay_PIPERX2EQCONTROL; + wire [1:0] delay_PIPERX3EQCONTROL; + wire [1:0] delay_PIPERX4EQCONTROL; + wire [1:0] delay_PIPERX5EQCONTROL; + wire [1:0] delay_PIPERX6EQCONTROL; + wire [1:0] delay_PIPERX7EQCONTROL; + wire [1:0] delay_PIPETX0CHARISK; + wire [1:0] delay_PIPETX0EQCONTROL; + wire [1:0] delay_PIPETX0POWERDOWN; + wire [1:0] delay_PIPETX0SYNCHEADER; + wire [1:0] delay_PIPETX1CHARISK; + wire [1:0] delay_PIPETX1EQCONTROL; + wire [1:0] delay_PIPETX1POWERDOWN; + wire [1:0] delay_PIPETX1SYNCHEADER; + wire [1:0] delay_PIPETX2CHARISK; + wire [1:0] delay_PIPETX2EQCONTROL; + wire [1:0] delay_PIPETX2POWERDOWN; + wire [1:0] delay_PIPETX2SYNCHEADER; + wire [1:0] delay_PIPETX3CHARISK; + wire [1:0] delay_PIPETX3EQCONTROL; + wire [1:0] delay_PIPETX3POWERDOWN; + wire [1:0] delay_PIPETX3SYNCHEADER; + wire [1:0] delay_PIPETX4CHARISK; + wire [1:0] delay_PIPETX4EQCONTROL; + wire [1:0] delay_PIPETX4POWERDOWN; + wire [1:0] delay_PIPETX4SYNCHEADER; + wire [1:0] delay_PIPETX5CHARISK; + wire [1:0] delay_PIPETX5EQCONTROL; + wire [1:0] delay_PIPETX5POWERDOWN; + wire [1:0] delay_PIPETX5SYNCHEADER; + wire [1:0] delay_PIPETX6CHARISK; + wire [1:0] delay_PIPETX6EQCONTROL; + wire [1:0] delay_PIPETX6POWERDOWN; + wire [1:0] delay_PIPETX6SYNCHEADER; + wire [1:0] delay_PIPETX7CHARISK; + wire [1:0] delay_PIPETX7EQCONTROL; + wire [1:0] delay_PIPETX7POWERDOWN; + wire [1:0] delay_PIPETX7SYNCHEADER; + wire [1:0] delay_PIPETXRATE; + wire [1:0] delay_PLEQPHASE; + wire [255:0] delay_MAXISCQTDATA; + wire [255:0] delay_MAXISRCTDATA; + wire [2:0] delay_CFGCURRENTSPEED; + wire [2:0] delay_CFGMAXPAYLOAD; + wire [2:0] delay_CFGMAXREADREQ; + wire [2:0] delay_CFGTPHFUNCTIONNUM; + wire [2:0] delay_PIPERX0EQPRESET; + wire [2:0] delay_PIPERX1EQPRESET; + wire [2:0] delay_PIPERX2EQPRESET; + wire [2:0] delay_PIPERX3EQPRESET; + wire [2:0] delay_PIPERX4EQPRESET; + wire [2:0] delay_PIPERX5EQPRESET; + wire [2:0] delay_PIPERX6EQPRESET; + wire [2:0] delay_PIPERX7EQPRESET; + wire [2:0] delay_PIPETXMARGIN; + wire [31:0] delay_CFGEXTWRITEDATA; + wire [31:0] delay_CFGINTERRUPTMSIDATA; + wire [31:0] delay_CFGMGMTREADDATA; + wire [31:0] delay_CFGTPHSTTWRITEDATA; + wire [31:0] delay_PIPETX0DATA; + wire [31:0] delay_PIPETX1DATA; + wire [31:0] delay_PIPETX2DATA; + wire [31:0] delay_PIPETX3DATA; + wire [31:0] delay_PIPETX4DATA; + wire [31:0] delay_PIPETX5DATA; + wire [31:0] delay_PIPETX6DATA; + wire [31:0] delay_PIPETX7DATA; + wire [3:0] delay_CFGEXTWRITEBYTEENABLE; + wire [3:0] delay_CFGNEGOTIATEDWIDTH; + wire [3:0] delay_CFGTPHSTTWRITEBYTEVALID; + wire [3:0] delay_MICOMPLETIONRAMREADENABLEL; + wire [3:0] delay_MICOMPLETIONRAMREADENABLEU; + wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEL; + wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEU; + wire [3:0] delay_MIREQUESTRAMREADENABLE; + wire [3:0] delay_MIREQUESTRAMWRITEENABLE; + wire [3:0] delay_PCIERQSEQNUM; + wire [3:0] delay_PIPERX0EQLPTXPRESET; + wire [3:0] delay_PIPERX1EQLPTXPRESET; + wire [3:0] delay_PIPERX2EQLPTXPRESET; + wire [3:0] delay_PIPERX3EQLPTXPRESET; + wire [3:0] delay_PIPERX4EQLPTXPRESET; + wire [3:0] delay_PIPERX5EQLPTXPRESET; + wire [3:0] delay_PIPERX6EQLPTXPRESET; + wire [3:0] delay_PIPERX7EQLPTXPRESET; + wire [3:0] delay_PIPETX0EQPRESET; + wire [3:0] delay_PIPETX1EQPRESET; + wire [3:0] delay_PIPETX2EQPRESET; + wire [3:0] delay_PIPETX3EQPRESET; + wire [3:0] delay_PIPETX4EQPRESET; + wire [3:0] delay_PIPETX5EQPRESET; + wire [3:0] delay_PIPETX6EQPRESET; + wire [3:0] delay_PIPETX7EQPRESET; + wire [3:0] delay_SAXISCCTREADY; + wire [3:0] delay_SAXISRQTREADY; + wire [4:0] delay_CFGMSGRECEIVEDTYPE; + wire [4:0] delay_CFGTPHSTTADDRESS; + wire [5:0] delay_CFGFUNCTIONPOWERSTATE; + wire [5:0] delay_CFGINTERRUPTMSIMMENABLE; + wire [5:0] delay_CFGINTERRUPTMSIVFENABLE; + wire [5:0] delay_CFGINTERRUPTMSIXVFENABLE; + wire [5:0] delay_CFGINTERRUPTMSIXVFMASK; + wire [5:0] delay_CFGLTSSMSTATE; + wire [5:0] delay_CFGTPHSTMODE; + wire [5:0] delay_CFGVFFLRINPROCESS; + wire [5:0] delay_CFGVFTPHREQUESTERENABLE; + wire [5:0] delay_PCIECQNPREQCOUNT; + wire [5:0] delay_PCIERQTAG; + wire [5:0] delay_PIPERX0EQLPLFFS; + wire [5:0] delay_PIPERX1EQLPLFFS; + wire [5:0] delay_PIPERX2EQLPLFFS; + wire [5:0] delay_PIPERX3EQLPLFFS; + wire [5:0] delay_PIPERX4EQLPLFFS; + wire [5:0] delay_PIPERX5EQLPLFFS; + wire [5:0] delay_PIPERX6EQLPLFFS; + wire [5:0] delay_PIPERX7EQLPLFFS; + wire [5:0] delay_PIPETX0EQDEEMPH; + wire [5:0] delay_PIPETX1EQDEEMPH; + wire [5:0] delay_PIPETX2EQDEEMPH; + wire [5:0] delay_PIPETX3EQDEEMPH; + wire [5:0] delay_PIPETX4EQDEEMPH; + wire [5:0] delay_PIPETX5EQDEEMPH; + wire [5:0] delay_PIPETX6EQDEEMPH; + wire [5:0] delay_PIPETX7EQDEEMPH; + wire [71:0] delay_MICOMPLETIONRAMWRITEDATAL; + wire [71:0] delay_MICOMPLETIONRAMWRITEDATAU; + wire [74:0] delay_MAXISRCTUSER; + wire [7:0] delay_CFGEXTFUNCTIONNUMBER; + wire [7:0] delay_CFGFCCPLH; + wire [7:0] delay_CFGFCNPH; + wire [7:0] delay_CFGFCPH; + wire [7:0] delay_CFGFUNCTIONSTATUS; + wire [7:0] delay_CFGMSGRECEIVEDDATA; + wire [7:0] delay_MAXISCQTKEEP; + wire [7:0] delay_MAXISRCTKEEP; + wire [7:0] delay_PLGEN3PCSRXSLIDE; + wire [84:0] delay_MAXISCQTUSER; + wire [8:0] delay_MIREPLAYRAMADDRESS; + wire [8:0] delay_MIREQUESTRAMREADADDRESSA; + wire [8:0] delay_MIREQUESTRAMREADADDRESSB; + wire [8:0] delay_MIREQUESTRAMWRITEADDRESSA; + wire [8:0] delay_MIREQUESTRAMWRITEADDRESSB; + wire [9:0] delay_CFGEXTREGISTERNUMBER; + wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAL; + wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAU; + wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBL; + wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBU; + wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAL; + wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAU; + wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBL; + wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBU; + wire delay_CFGERRCOROUT; + wire delay_CFGERRFATALOUT; + wire delay_CFGERRNONFATALOUT; + wire delay_CFGEXTREADRECEIVED; + wire delay_CFGEXTWRITERECEIVED; + wire delay_CFGHOTRESETOUT; + wire delay_CFGINPUTUPDATEDONE; + wire delay_CFGINTERRUPTAOUTPUT; + wire delay_CFGINTERRUPTBOUTPUT; + wire delay_CFGINTERRUPTCOUTPUT; + wire delay_CFGINTERRUPTDOUTPUT; + wire delay_CFGINTERRUPTMSIFAIL; + wire delay_CFGINTERRUPTMSIMASKUPDATE; + wire delay_CFGINTERRUPTMSISENT; + wire delay_CFGINTERRUPTMSIXFAIL; + wire delay_CFGINTERRUPTMSIXSENT; + wire delay_CFGINTERRUPTSENT; + wire delay_CFGLOCALERROR; + wire delay_CFGLTRENABLE; + wire delay_CFGMCUPDATEDONE; + wire delay_CFGMGMTREADWRITEDONE; + wire delay_CFGMSGRECEIVED; + wire delay_CFGMSGTRANSMITDONE; + wire delay_CFGPERFUNCTIONUPDATEDONE; + wire delay_CFGPHYLINKDOWN; + wire delay_CFGPLSTATUSCHANGE; + wire delay_CFGPOWERSTATECHANGEINTERRUPT; + wire delay_CFGTPHSTTREADENABLE; + wire delay_CFGTPHSTTWRITEENABLE; + wire delay_DRPRDY; + wire delay_MAXISCQTLAST; + wire delay_MAXISCQTVALID; + wire delay_MAXISRCTLAST; + wire delay_MAXISRCTVALID; + wire delay_PCIERQSEQNUMVLD; + wire delay_PCIERQTAGVLD; + wire delay_PIPERX0POLARITY; + wire delay_PIPERX1POLARITY; + wire delay_PIPERX2POLARITY; + wire delay_PIPERX3POLARITY; + wire delay_PIPERX4POLARITY; + wire delay_PIPERX5POLARITY; + wire delay_PIPERX6POLARITY; + wire delay_PIPERX7POLARITY; + wire delay_PIPETX0COMPLIANCE; + wire delay_PIPETX0DATAVALID; + wire delay_PIPETX0ELECIDLE; + wire delay_PIPETX0STARTBLOCK; + wire delay_PIPETX1COMPLIANCE; + wire delay_PIPETX1DATAVALID; + wire delay_PIPETX1ELECIDLE; + wire delay_PIPETX1STARTBLOCK; + wire delay_PIPETX2COMPLIANCE; + wire delay_PIPETX2DATAVALID; + wire delay_PIPETX2ELECIDLE; + wire delay_PIPETX2STARTBLOCK; + wire delay_PIPETX3COMPLIANCE; + wire delay_PIPETX3DATAVALID; + wire delay_PIPETX3ELECIDLE; + wire delay_PIPETX3STARTBLOCK; + wire delay_PIPETX4COMPLIANCE; + wire delay_PIPETX4DATAVALID; + wire delay_PIPETX4ELECIDLE; + wire delay_PIPETX4STARTBLOCK; + wire delay_PIPETX5COMPLIANCE; + wire delay_PIPETX5DATAVALID; + wire delay_PIPETX5ELECIDLE; + wire delay_PIPETX5STARTBLOCK; + wire delay_PIPETX6COMPLIANCE; + wire delay_PIPETX6DATAVALID; + wire delay_PIPETX6ELECIDLE; + wire delay_PIPETX6STARTBLOCK; + wire delay_PIPETX7COMPLIANCE; + wire delay_PIPETX7DATAVALID; + wire delay_PIPETX7ELECIDLE; + wire delay_PIPETX7STARTBLOCK; + wire delay_PIPETXDEEMPH; + wire delay_PIPETXRCVRDET; + wire delay_PIPETXRESET; + wire delay_PIPETXSWING; + wire delay_PLEQINPROGRESS; + + wire [10:0] delay_DRPADDR; + wire [143:0] delay_MICOMPLETIONRAMREADDATA; + wire [143:0] delay_MIREPLAYRAMREADDATA; + wire [143:0] delay_MIREQUESTRAMREADDATA; + wire [15:0] delay_CFGDEVID; + wire [15:0] delay_CFGSUBSYSID; + wire [15:0] delay_CFGSUBSYSVENDID; + wire [15:0] delay_CFGVENDID; + wire [15:0] delay_DRPDI; + wire [17:0] delay_PIPERX0EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX1EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX2EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX3EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX4EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX5EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX6EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPERX7EQLPNEWTXCOEFFORPRESET; + wire [17:0] delay_PIPETX0EQCOEFF; + wire [17:0] delay_PIPETX1EQCOEFF; + wire [17:0] delay_PIPETX2EQCOEFF; + wire [17:0] delay_PIPETX3EQCOEFF; + wire [17:0] delay_PIPETX4EQCOEFF; + wire [17:0] delay_PIPETX5EQCOEFF; + wire [17:0] delay_PIPETX6EQCOEFF; + wire [17:0] delay_PIPETX7EQCOEFF; + wire [18:0] delay_CFGMGMTADDR; + wire [1:0] delay_CFGFLRDONE; + wire [1:0] delay_CFGINTERRUPTMSITPHTYPE; + wire [1:0] delay_CFGINTERRUPTPENDING; + wire [1:0] delay_PIPERX0CHARISK; + wire [1:0] delay_PIPERX0SYNCHEADER; + wire [1:0] delay_PIPERX1CHARISK; + wire [1:0] delay_PIPERX1SYNCHEADER; + wire [1:0] delay_PIPERX2CHARISK; + wire [1:0] delay_PIPERX2SYNCHEADER; + wire [1:0] delay_PIPERX3CHARISK; + wire [1:0] delay_PIPERX3SYNCHEADER; + wire [1:0] delay_PIPERX4CHARISK; + wire [1:0] delay_PIPERX4SYNCHEADER; + wire [1:0] delay_PIPERX5CHARISK; + wire [1:0] delay_PIPERX5SYNCHEADER; + wire [1:0] delay_PIPERX6CHARISK; + wire [1:0] delay_PIPERX6SYNCHEADER; + wire [1:0] delay_PIPERX7CHARISK; + wire [1:0] delay_PIPERX7SYNCHEADER; + wire [21:0] delay_MAXISCQTREADY; + wire [21:0] delay_MAXISRCTREADY; + wire [255:0] delay_SAXISCCTDATA; + wire [255:0] delay_SAXISRQTDATA; + wire [2:0] delay_CFGDSFUNCTIONNUMBER; + wire [2:0] delay_CFGFCSEL; + wire [2:0] delay_CFGINTERRUPTMSIATTR; + wire [2:0] delay_CFGINTERRUPTMSIFUNCTIONNUMBER; + wire [2:0] delay_CFGMSGTRANSMITTYPE; + wire [2:0] delay_CFGPERFUNCSTATUSCONTROL; + wire [2:0] delay_CFGPERFUNCTIONNUMBER; + wire [2:0] delay_PIPERX0STATUS; + wire [2:0] delay_PIPERX1STATUS; + wire [2:0] delay_PIPERX2STATUS; + wire [2:0] delay_PIPERX3STATUS; + wire [2:0] delay_PIPERX4STATUS; + wire [2:0] delay_PIPERX5STATUS; + wire [2:0] delay_PIPERX6STATUS; + wire [2:0] delay_PIPERX7STATUS; + wire [31:0] delay_CFGEXTREADDATA; + wire [31:0] delay_CFGINTERRUPTMSIINT; + wire [31:0] delay_CFGINTERRUPTMSIXDATA; + wire [31:0] delay_CFGMGMTWRITEDATA; + wire [31:0] delay_CFGMSGTRANSMITDATA; + wire [31:0] delay_CFGTPHSTTREADDATA; + wire [31:0] delay_PIPERX0DATA; + wire [31:0] delay_PIPERX1DATA; + wire [31:0] delay_PIPERX2DATA; + wire [31:0] delay_PIPERX3DATA; + wire [31:0] delay_PIPERX4DATA; + wire [31:0] delay_PIPERX5DATA; + wire [31:0] delay_PIPERX6DATA; + wire [31:0] delay_PIPERX7DATA; + wire [32:0] delay_SAXISCCTUSER; + wire [3:0] delay_CFGINTERRUPTINT; + wire [3:0] delay_CFGINTERRUPTMSISELECT; + wire [3:0] delay_CFGMGMTBYTEENABLE; + wire [4:0] delay_CFGDSDEVICENUMBER; + wire [59:0] delay_SAXISRQTUSER; + wire [5:0] delay_CFGVFFLRDONE; + wire [5:0] delay_PIPEEQFS; + wire [5:0] delay_PIPEEQLF; + wire [63:0] delay_CFGDSN; + wire [63:0] delay_CFGINTERRUPTMSIPENDINGSTATUS; + wire [63:0] delay_CFGINTERRUPTMSIXADDRESS; + wire [7:0] delay_CFGDSBUSNUMBER; + wire [7:0] delay_CFGDSPORTNUMBER; + wire [7:0] delay_CFGREVID; + wire [7:0] delay_PLGEN3PCSRXSYNCDONE; + wire [7:0] delay_SAXISCCTKEEP; + wire [7:0] delay_SAXISRQTKEEP; + wire [8:0] delay_CFGINTERRUPTMSITPHSTTAG; + wire delay_CFGCONFIGSPACEENABLE; + wire delay_CFGERRCORIN; + wire delay_CFGERRUNCORIN; + wire delay_CFGEXTREADDATAVALID; + wire delay_CFGHOTRESETIN; + wire delay_CFGINPUTUPDATEREQUEST; + wire delay_CFGINTERRUPTMSITPHPRESENT; + wire delay_CFGINTERRUPTMSIXINT; + wire delay_CFGLINKTRAININGENABLE; + wire delay_CFGMCUPDATEREQUEST; + wire delay_CFGMGMTREAD; + wire delay_CFGMGMTTYPE1CFGREGACCESS; + wire delay_CFGMGMTWRITE; + wire delay_CFGMSGTRANSMIT; + wire delay_CFGPERFUNCTIONOUTPUTREQUEST; + wire delay_CFGPOWERSTATECHANGEACK; + wire delay_CFGREQPMTRANSITIONL23READY; + wire delay_CFGTPHSTTREADDATAVALID; + wire delay_CORECLK; + wire delay_CORECLKMICOMPLETIONRAML; + wire delay_CORECLKMICOMPLETIONRAMU; + wire delay_CORECLKMIREPLAYRAM; + wire delay_CORECLKMIREQUESTRAM; + wire delay_DRPCLK; + wire delay_DRPEN; + wire delay_DRPWE; + wire delay_MGMTRESETN; + wire delay_MGMTSTICKYRESETN; + wire delay_PCIECQNPREQ; + wire delay_PIPECLK; + wire delay_PIPERESETN; + wire delay_PIPERX0DATAVALID; + wire delay_PIPERX0ELECIDLE; + wire delay_PIPERX0EQDONE; + wire delay_PIPERX0EQLPADAPTDONE; + wire delay_PIPERX0EQLPLFFSSEL; + wire delay_PIPERX0PHYSTATUS; + wire delay_PIPERX0STARTBLOCK; + wire delay_PIPERX0VALID; + wire delay_PIPERX1DATAVALID; + wire delay_PIPERX1ELECIDLE; + wire delay_PIPERX1EQDONE; + wire delay_PIPERX1EQLPADAPTDONE; + wire delay_PIPERX1EQLPLFFSSEL; + wire delay_PIPERX1PHYSTATUS; + wire delay_PIPERX1STARTBLOCK; + wire delay_PIPERX1VALID; + wire delay_PIPERX2DATAVALID; + wire delay_PIPERX2ELECIDLE; + wire delay_PIPERX2EQDONE; + wire delay_PIPERX2EQLPADAPTDONE; + wire delay_PIPERX2EQLPLFFSSEL; + wire delay_PIPERX2PHYSTATUS; + wire delay_PIPERX2STARTBLOCK; + wire delay_PIPERX2VALID; + wire delay_PIPERX3DATAVALID; + wire delay_PIPERX3ELECIDLE; + wire delay_PIPERX3EQDONE; + wire delay_PIPERX3EQLPADAPTDONE; + wire delay_PIPERX3EQLPLFFSSEL; + wire delay_PIPERX3PHYSTATUS; + wire delay_PIPERX3STARTBLOCK; + wire delay_PIPERX3VALID; + wire delay_PIPERX4DATAVALID; + wire delay_PIPERX4ELECIDLE; + wire delay_PIPERX4EQDONE; + wire delay_PIPERX4EQLPADAPTDONE; + wire delay_PIPERX4EQLPLFFSSEL; + wire delay_PIPERX4PHYSTATUS; + wire delay_PIPERX4STARTBLOCK; + wire delay_PIPERX4VALID; + wire delay_PIPERX5DATAVALID; + wire delay_PIPERX5ELECIDLE; + wire delay_PIPERX5EQDONE; + wire delay_PIPERX5EQLPADAPTDONE; + wire delay_PIPERX5EQLPLFFSSEL; + wire delay_PIPERX5PHYSTATUS; + wire delay_PIPERX5STARTBLOCK; + wire delay_PIPERX5VALID; + wire delay_PIPERX6DATAVALID; + wire delay_PIPERX6ELECIDLE; + wire delay_PIPERX6EQDONE; + wire delay_PIPERX6EQLPADAPTDONE; + wire delay_PIPERX6EQLPLFFSSEL; + wire delay_PIPERX6PHYSTATUS; + wire delay_PIPERX6STARTBLOCK; + wire delay_PIPERX6VALID; + wire delay_PIPERX7DATAVALID; + wire delay_PIPERX7ELECIDLE; + wire delay_PIPERX7EQDONE; + wire delay_PIPERX7EQLPADAPTDONE; + wire delay_PIPERX7EQLPLFFSSEL; + wire delay_PIPERX7PHYSTATUS; + wire delay_PIPERX7STARTBLOCK; + wire delay_PIPERX7VALID; + wire delay_PIPETX0EQDONE; + wire delay_PIPETX1EQDONE; + wire delay_PIPETX2EQDONE; + wire delay_PIPETX3EQDONE; + wire delay_PIPETX4EQDONE; + wire delay_PIPETX5EQDONE; + wire delay_PIPETX6EQDONE; + wire delay_PIPETX7EQDONE; + wire delay_PLDISABLESCRAMBLER; + wire delay_PLEQRESETEIEOSCOUNT; + wire delay_PLGEN3PCSDISABLE; + wire delay_RECCLK; + wire delay_RESETN; + wire delay_SAXISCCTLAST; + wire delay_SAXISCCTVALID; + wire delay_SAXISRQTLAST; + wire delay_SAXISRQTVALID; + wire delay_USERCLK; + + + //drp monitor + reg drpen_r1 = 1'b0; + reg drpen_r2 = 1'b0; + reg drpwe_r1 = 1'b0; + reg drpwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge delay_DRPCLK) + begin + // pipeline the DRPEN and DRPWE + drpen_r1 <= delay_DRPEN; + drpwe_r1 <= delay_DRPWE; + drpen_r2 <= drpen_r1; + drpwe_r2 <= drpwe_r1; + + + // Check - if DRPEN or DRPWE is more than 1 DCLK + if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) + begin + $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) + begin + $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); + $finish; + end + + + //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. + case (sfsm) + FSM_IDLE: + begin + if(delay_DRPEN == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DRPEN, 4 cases can happen + // DRPEN DRPRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRPRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRPRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0) + begin + $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); + $finish; + end + + //Add the check for another DRPWE pulse + if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0)) + begin + $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); + $finish; + end + + if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge delay_DRPCLK) + //end drp monitor + + + assign #(out_delay) CFGCURRENTSPEED = delay_CFGCURRENTSPEED; + assign #(out_delay) CFGDPASUBSTATECHANGE = delay_CFGDPASUBSTATECHANGE; + assign #(out_delay) CFGERRCOROUT = delay_CFGERRCOROUT; + assign #(out_delay) CFGERRFATALOUT = delay_CFGERRFATALOUT; + assign #(out_delay) CFGERRNONFATALOUT = delay_CFGERRNONFATALOUT; + assign #(out_delay) CFGEXTFUNCTIONNUMBER = delay_CFGEXTFUNCTIONNUMBER; + assign #(out_delay) CFGEXTREADRECEIVED = delay_CFGEXTREADRECEIVED; + assign #(out_delay) CFGEXTREGISTERNUMBER = delay_CFGEXTREGISTERNUMBER; + assign #(out_delay) CFGEXTWRITEBYTEENABLE = delay_CFGEXTWRITEBYTEENABLE; + assign #(out_delay) CFGEXTWRITEDATA = delay_CFGEXTWRITEDATA; + assign #(out_delay) CFGEXTWRITERECEIVED = delay_CFGEXTWRITERECEIVED; + assign #(out_delay) CFGFCCPLD = delay_CFGFCCPLD; + assign #(out_delay) CFGFCCPLH = delay_CFGFCCPLH; + assign #(out_delay) CFGFCNPD = delay_CFGFCNPD; + assign #(out_delay) CFGFCNPH = delay_CFGFCNPH; + assign #(out_delay) CFGFCPD = delay_CFGFCPD; + assign #(out_delay) CFGFCPH = delay_CFGFCPH; + assign #(out_delay) CFGFLRINPROCESS = delay_CFGFLRINPROCESS; + assign #(out_delay) CFGFUNCTIONPOWERSTATE = delay_CFGFUNCTIONPOWERSTATE; + assign #(out_delay) CFGFUNCTIONSTATUS = delay_CFGFUNCTIONSTATUS; + assign #(out_delay) CFGHOTRESETOUT = delay_CFGHOTRESETOUT; + assign #(out_delay) CFGINPUTUPDATEDONE = delay_CFGINPUTUPDATEDONE; + assign #(out_delay) CFGINTERRUPTAOUTPUT = delay_CFGINTERRUPTAOUTPUT; + assign #(out_delay) CFGINTERRUPTBOUTPUT = delay_CFGINTERRUPTBOUTPUT; + assign #(out_delay) CFGINTERRUPTCOUTPUT = delay_CFGINTERRUPTCOUTPUT; + assign #(out_delay) CFGINTERRUPTDOUTPUT = delay_CFGINTERRUPTDOUTPUT; + assign #(out_delay) CFGINTERRUPTMSIDATA = delay_CFGINTERRUPTMSIDATA; + assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE; + assign #(out_delay) CFGINTERRUPTMSIFAIL = delay_CFGINTERRUPTMSIFAIL; + assign #(out_delay) CFGINTERRUPTMSIMASKUPDATE = delay_CFGINTERRUPTMSIMASKUPDATE; + assign #(out_delay) CFGINTERRUPTMSIMMENABLE = delay_CFGINTERRUPTMSIMMENABLE; + assign #(out_delay) CFGINTERRUPTMSISENT = delay_CFGINTERRUPTMSISENT; + assign #(out_delay) CFGINTERRUPTMSIVFENABLE = delay_CFGINTERRUPTMSIVFENABLE; + assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE; + assign #(out_delay) CFGINTERRUPTMSIXFAIL = delay_CFGINTERRUPTMSIXFAIL; + assign #(out_delay) CFGINTERRUPTMSIXMASK = delay_CFGINTERRUPTMSIXMASK; + assign #(out_delay) CFGINTERRUPTMSIXSENT = delay_CFGINTERRUPTMSIXSENT; + assign #(out_delay) CFGINTERRUPTMSIXVFENABLE = delay_CFGINTERRUPTMSIXVFENABLE; + assign #(out_delay) CFGINTERRUPTMSIXVFMASK = delay_CFGINTERRUPTMSIXVFMASK; + assign #(out_delay) CFGINTERRUPTSENT = delay_CFGINTERRUPTSENT; + assign #(out_delay) CFGLINKPOWERSTATE = delay_CFGLINKPOWERSTATE; + assign #(out_delay) CFGLOCALERROR = delay_CFGLOCALERROR; + assign #(out_delay) CFGLTRENABLE = delay_CFGLTRENABLE; + assign #(out_delay) CFGLTSSMSTATE = delay_CFGLTSSMSTATE; + assign #(out_delay) CFGMAXPAYLOAD = delay_CFGMAXPAYLOAD; + assign #(out_delay) CFGMAXREADREQ = delay_CFGMAXREADREQ; + assign #(out_delay) CFGMCUPDATEDONE = delay_CFGMCUPDATEDONE; + assign #(out_delay) CFGMGMTREADDATA = delay_CFGMGMTREADDATA; + assign #(out_delay) CFGMGMTREADWRITEDONE = delay_CFGMGMTREADWRITEDONE; + assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED; + assign #(out_delay) CFGMSGRECEIVEDDATA = delay_CFGMSGRECEIVEDDATA; + assign #(out_delay) CFGMSGRECEIVEDTYPE = delay_CFGMSGRECEIVEDTYPE; + assign #(out_delay) CFGMSGTRANSMITDONE = delay_CFGMSGTRANSMITDONE; + assign #(out_delay) CFGNEGOTIATEDWIDTH = delay_CFGNEGOTIATEDWIDTH; + assign #(out_delay) CFGOBFFENABLE = delay_CFGOBFFENABLE; + assign #(out_delay) CFGPERFUNCSTATUSDATA = delay_CFGPERFUNCSTATUSDATA; + assign #(out_delay) CFGPERFUNCTIONUPDATEDONE = delay_CFGPERFUNCTIONUPDATEDONE; + assign #(out_delay) CFGPHYLINKDOWN = delay_CFGPHYLINKDOWN; + assign #(out_delay) CFGPHYLINKSTATUS = delay_CFGPHYLINKSTATUS; + assign #(out_delay) CFGPLSTATUSCHANGE = delay_CFGPLSTATUSCHANGE; + assign #(out_delay) CFGPOWERSTATECHANGEINTERRUPT = delay_CFGPOWERSTATECHANGEINTERRUPT; + assign #(out_delay) CFGRCBSTATUS = delay_CFGRCBSTATUS; + assign #(out_delay) CFGTPHFUNCTIONNUM = delay_CFGTPHFUNCTIONNUM; + assign #(out_delay) CFGTPHREQUESTERENABLE = delay_CFGTPHREQUESTERENABLE; + assign #(out_delay) CFGTPHSTMODE = delay_CFGTPHSTMODE; + assign #(out_delay) CFGTPHSTTADDRESS = delay_CFGTPHSTTADDRESS; + assign #(out_delay) CFGTPHSTTREADENABLE = delay_CFGTPHSTTREADENABLE; + assign #(out_delay) CFGTPHSTTWRITEBYTEVALID = delay_CFGTPHSTTWRITEBYTEVALID; + assign #(out_delay) CFGTPHSTTWRITEDATA = delay_CFGTPHSTTWRITEDATA; + assign #(out_delay) CFGTPHSTTWRITEENABLE = delay_CFGTPHSTTWRITEENABLE; + assign #(out_delay) CFGVFFLRINPROCESS = delay_CFGVFFLRINPROCESS; + assign #(out_delay) CFGVFPOWERSTATE = delay_CFGVFPOWERSTATE; + assign #(out_delay) CFGVFSTATUS = delay_CFGVFSTATUS; + assign #(out_delay) CFGVFTPHREQUESTERENABLE = delay_CFGVFTPHREQUESTERENABLE; + assign #(out_delay) CFGVFTPHSTMODE = delay_CFGVFTPHSTMODE; + assign #(out_delay) DBGDATAOUT = delay_DBGDATAOUT; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPRDY = delay_DRPRDY; + assign #(out_delay) MAXISCQTDATA = delay_MAXISCQTDATA; + assign #(out_delay) MAXISCQTKEEP = delay_MAXISCQTKEEP; + assign #(out_delay) MAXISCQTLAST = delay_MAXISCQTLAST; + assign #(out_delay) MAXISCQTUSER = delay_MAXISCQTUSER; + assign #(out_delay) MAXISCQTVALID = delay_MAXISCQTVALID; + assign #(out_delay) MAXISRCTDATA = delay_MAXISRCTDATA; + assign #(out_delay) MAXISRCTKEEP = delay_MAXISRCTKEEP; + assign #(out_delay) MAXISRCTLAST = delay_MAXISRCTLAST; + assign #(out_delay) MAXISRCTUSER = delay_MAXISRCTUSER; + assign #(out_delay) MAXISRCTVALID = delay_MAXISRCTVALID; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSAL = delay_MICOMPLETIONRAMREADADDRESSAL; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSAU = delay_MICOMPLETIONRAMREADADDRESSAU; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSBL = delay_MICOMPLETIONRAMREADADDRESSBL; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSBU = delay_MICOMPLETIONRAMREADADDRESSBU; + assign #(out_delay) MICOMPLETIONRAMREADENABLEL = delay_MICOMPLETIONRAMREADENABLEL; + assign #(out_delay) MICOMPLETIONRAMREADENABLEU = delay_MICOMPLETIONRAMREADENABLEU; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAL = delay_MICOMPLETIONRAMWRITEADDRESSAL; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAU = delay_MICOMPLETIONRAMWRITEADDRESSAU; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBL = delay_MICOMPLETIONRAMWRITEADDRESSBL; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBU = delay_MICOMPLETIONRAMWRITEADDRESSBU; + assign #(out_delay) MICOMPLETIONRAMWRITEDATAL = delay_MICOMPLETIONRAMWRITEDATAL; + assign #(out_delay) MICOMPLETIONRAMWRITEDATAU = delay_MICOMPLETIONRAMWRITEDATAU; + assign #(out_delay) MICOMPLETIONRAMWRITEENABLEL = delay_MICOMPLETIONRAMWRITEENABLEL; + assign #(out_delay) MICOMPLETIONRAMWRITEENABLEU = delay_MICOMPLETIONRAMWRITEENABLEU; + assign #(out_delay) MIREPLAYRAMADDRESS = delay_MIREPLAYRAMADDRESS; + assign #(out_delay) MIREPLAYRAMREADENABLE = delay_MIREPLAYRAMREADENABLE; + assign #(out_delay) MIREPLAYRAMWRITEDATA = delay_MIREPLAYRAMWRITEDATA; + assign #(out_delay) MIREPLAYRAMWRITEENABLE = delay_MIREPLAYRAMWRITEENABLE; + assign #(out_delay) MIREQUESTRAMREADADDRESSA = delay_MIREQUESTRAMREADADDRESSA; + assign #(out_delay) MIREQUESTRAMREADADDRESSB = delay_MIREQUESTRAMREADADDRESSB; + assign #(out_delay) MIREQUESTRAMREADENABLE = delay_MIREQUESTRAMREADENABLE; + assign #(out_delay) MIREQUESTRAMWRITEADDRESSA = delay_MIREQUESTRAMWRITEADDRESSA; + assign #(out_delay) MIREQUESTRAMWRITEADDRESSB = delay_MIREQUESTRAMWRITEADDRESSB; + assign #(out_delay) MIREQUESTRAMWRITEDATA = delay_MIREQUESTRAMWRITEDATA; + assign #(out_delay) MIREQUESTRAMWRITEENABLE = delay_MIREQUESTRAMWRITEENABLE; + assign #(out_delay) PCIECQNPREQCOUNT = delay_PCIECQNPREQCOUNT; + assign #(out_delay) PCIERQSEQNUM = delay_PCIERQSEQNUM; + assign #(out_delay) PCIERQSEQNUMVLD = delay_PCIERQSEQNUMVLD; + assign #(out_delay) PCIERQTAG = delay_PCIERQTAG; + assign #(out_delay) PCIERQTAGAV = delay_PCIERQTAGAV; + assign #(out_delay) PCIERQTAGVLD = delay_PCIERQTAGVLD; + assign #(out_delay) PCIETFCNPDAV = delay_PCIETFCNPDAV; + assign #(out_delay) PCIETFCNPHAV = delay_PCIETFCNPHAV; + assign #(out_delay) PIPERX0EQCONTROL = delay_PIPERX0EQCONTROL; + assign #(out_delay) PIPERX0EQLPLFFS = delay_PIPERX0EQLPLFFS; + assign #(out_delay) PIPERX0EQLPTXPRESET = delay_PIPERX0EQLPTXPRESET; + assign #(out_delay) PIPERX0EQPRESET = delay_PIPERX0EQPRESET; + assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY; + assign #(out_delay) PIPERX1EQCONTROL = delay_PIPERX1EQCONTROL; + assign #(out_delay) PIPERX1EQLPLFFS = delay_PIPERX1EQLPLFFS; + assign #(out_delay) PIPERX1EQLPTXPRESET = delay_PIPERX1EQLPTXPRESET; + assign #(out_delay) PIPERX1EQPRESET = delay_PIPERX1EQPRESET; + assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY; + assign #(out_delay) PIPERX2EQCONTROL = delay_PIPERX2EQCONTROL; + assign #(out_delay) PIPERX2EQLPLFFS = delay_PIPERX2EQLPLFFS; + assign #(out_delay) PIPERX2EQLPTXPRESET = delay_PIPERX2EQLPTXPRESET; + assign #(out_delay) PIPERX2EQPRESET = delay_PIPERX2EQPRESET; + assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY; + assign #(out_delay) PIPERX3EQCONTROL = delay_PIPERX3EQCONTROL; + assign #(out_delay) PIPERX3EQLPLFFS = delay_PIPERX3EQLPLFFS; + assign #(out_delay) PIPERX3EQLPTXPRESET = delay_PIPERX3EQLPTXPRESET; + assign #(out_delay) PIPERX3EQPRESET = delay_PIPERX3EQPRESET; + assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY; + assign #(out_delay) PIPERX4EQCONTROL = delay_PIPERX4EQCONTROL; + assign #(out_delay) PIPERX4EQLPLFFS = delay_PIPERX4EQLPLFFS; + assign #(out_delay) PIPERX4EQLPTXPRESET = delay_PIPERX4EQLPTXPRESET; + assign #(out_delay) PIPERX4EQPRESET = delay_PIPERX4EQPRESET; + assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY; + assign #(out_delay) PIPERX5EQCONTROL = delay_PIPERX5EQCONTROL; + assign #(out_delay) PIPERX5EQLPLFFS = delay_PIPERX5EQLPLFFS; + assign #(out_delay) PIPERX5EQLPTXPRESET = delay_PIPERX5EQLPTXPRESET; + assign #(out_delay) PIPERX5EQPRESET = delay_PIPERX5EQPRESET; + assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY; + assign #(out_delay) PIPERX6EQCONTROL = delay_PIPERX6EQCONTROL; + assign #(out_delay) PIPERX6EQLPLFFS = delay_PIPERX6EQLPLFFS; + assign #(out_delay) PIPERX6EQLPTXPRESET = delay_PIPERX6EQLPTXPRESET; + assign #(out_delay) PIPERX6EQPRESET = delay_PIPERX6EQPRESET; + assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY; + assign #(out_delay) PIPERX7EQCONTROL = delay_PIPERX7EQCONTROL; + assign #(out_delay) PIPERX7EQLPLFFS = delay_PIPERX7EQLPLFFS; + assign #(out_delay) PIPERX7EQLPTXPRESET = delay_PIPERX7EQLPTXPRESET; + assign #(out_delay) PIPERX7EQPRESET = delay_PIPERX7EQPRESET; + assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY; + assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK; + assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE; + assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA; + assign #(out_delay) PIPETX0DATAVALID = delay_PIPETX0DATAVALID; + assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE; + assign #(out_delay) PIPETX0EQCONTROL = delay_PIPETX0EQCONTROL; + assign #(out_delay) PIPETX0EQDEEMPH = delay_PIPETX0EQDEEMPH; + assign #(out_delay) PIPETX0EQPRESET = delay_PIPETX0EQPRESET; + assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN; + assign #(out_delay) PIPETX0STARTBLOCK = delay_PIPETX0STARTBLOCK; + assign #(out_delay) PIPETX0SYNCHEADER = delay_PIPETX0SYNCHEADER; + assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK; + assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE; + assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA; + assign #(out_delay) PIPETX1DATAVALID = delay_PIPETX1DATAVALID; + assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE; + assign #(out_delay) PIPETX1EQCONTROL = delay_PIPETX1EQCONTROL; + assign #(out_delay) PIPETX1EQDEEMPH = delay_PIPETX1EQDEEMPH; + assign #(out_delay) PIPETX1EQPRESET = delay_PIPETX1EQPRESET; + assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN; + assign #(out_delay) PIPETX1STARTBLOCK = delay_PIPETX1STARTBLOCK; + assign #(out_delay) PIPETX1SYNCHEADER = delay_PIPETX1SYNCHEADER; + assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK; + assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE; + assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA; + assign #(out_delay) PIPETX2DATAVALID = delay_PIPETX2DATAVALID; + assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE; + assign #(out_delay) PIPETX2EQCONTROL = delay_PIPETX2EQCONTROL; + assign #(out_delay) PIPETX2EQDEEMPH = delay_PIPETX2EQDEEMPH; + assign #(out_delay) PIPETX2EQPRESET = delay_PIPETX2EQPRESET; + assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN; + assign #(out_delay) PIPETX2STARTBLOCK = delay_PIPETX2STARTBLOCK; + assign #(out_delay) PIPETX2SYNCHEADER = delay_PIPETX2SYNCHEADER; + assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK; + assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE; + assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA; + assign #(out_delay) PIPETX3DATAVALID = delay_PIPETX3DATAVALID; + assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE; + assign #(out_delay) PIPETX3EQCONTROL = delay_PIPETX3EQCONTROL; + assign #(out_delay) PIPETX3EQDEEMPH = delay_PIPETX3EQDEEMPH; + assign #(out_delay) PIPETX3EQPRESET = delay_PIPETX3EQPRESET; + assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN; + assign #(out_delay) PIPETX3STARTBLOCK = delay_PIPETX3STARTBLOCK; + assign #(out_delay) PIPETX3SYNCHEADER = delay_PIPETX3SYNCHEADER; + assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK; + assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE; + assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA; + assign #(out_delay) PIPETX4DATAVALID = delay_PIPETX4DATAVALID; + assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE; + assign #(out_delay) PIPETX4EQCONTROL = delay_PIPETX4EQCONTROL; + assign #(out_delay) PIPETX4EQDEEMPH = delay_PIPETX4EQDEEMPH; + assign #(out_delay) PIPETX4EQPRESET = delay_PIPETX4EQPRESET; + assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN; + assign #(out_delay) PIPETX4STARTBLOCK = delay_PIPETX4STARTBLOCK; + assign #(out_delay) PIPETX4SYNCHEADER = delay_PIPETX4SYNCHEADER; + assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK; + assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE; + assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA; + assign #(out_delay) PIPETX5DATAVALID = delay_PIPETX5DATAVALID; + assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE; + assign #(out_delay) PIPETX5EQCONTROL = delay_PIPETX5EQCONTROL; + assign #(out_delay) PIPETX5EQDEEMPH = delay_PIPETX5EQDEEMPH; + assign #(out_delay) PIPETX5EQPRESET = delay_PIPETX5EQPRESET; + assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN; + assign #(out_delay) PIPETX5STARTBLOCK = delay_PIPETX5STARTBLOCK; + assign #(out_delay) PIPETX5SYNCHEADER = delay_PIPETX5SYNCHEADER; + assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK; + assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE; + assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA; + assign #(out_delay) PIPETX6DATAVALID = delay_PIPETX6DATAVALID; + assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE; + assign #(out_delay) PIPETX6EQCONTROL = delay_PIPETX6EQCONTROL; + assign #(out_delay) PIPETX6EQDEEMPH = delay_PIPETX6EQDEEMPH; + assign #(out_delay) PIPETX6EQPRESET = delay_PIPETX6EQPRESET; + assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN; + assign #(out_delay) PIPETX6STARTBLOCK = delay_PIPETX6STARTBLOCK; + assign #(out_delay) PIPETX6SYNCHEADER = delay_PIPETX6SYNCHEADER; + assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK; + assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE; + assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA; + assign #(out_delay) PIPETX7DATAVALID = delay_PIPETX7DATAVALID; + assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE; + assign #(out_delay) PIPETX7EQCONTROL = delay_PIPETX7EQCONTROL; + assign #(out_delay) PIPETX7EQDEEMPH = delay_PIPETX7EQDEEMPH; + assign #(out_delay) PIPETX7EQPRESET = delay_PIPETX7EQPRESET; + assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN; + assign #(out_delay) PIPETX7STARTBLOCK = delay_PIPETX7STARTBLOCK; + assign #(out_delay) PIPETX7SYNCHEADER = delay_PIPETX7SYNCHEADER; + assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH; + assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN; + assign #(out_delay) PIPETXRATE = delay_PIPETXRATE; + assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET; + assign #(out_delay) PIPETXRESET = delay_PIPETXRESET; + assign #(out_delay) PIPETXSWING = delay_PIPETXSWING; + assign #(out_delay) PLEQINPROGRESS = delay_PLEQINPROGRESS; + assign #(out_delay) PLEQPHASE = delay_PLEQPHASE; + assign #(out_delay) PLGEN3PCSRXSLIDE = delay_PLGEN3PCSRXSLIDE; + assign #(out_delay) SAXISCCTREADY = delay_SAXISCCTREADY; + assign #(out_delay) SAXISRQTREADY = delay_SAXISRQTREADY; + +`ifndef XIL_TIMING // unisim + assign #(INCLK_DELAY) delay_CORECLK = CORECLK; + assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML; + assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU; + assign #(INCLK_DELAY) delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM; + assign #(INCLK_DELAY) delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM; + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK; + assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK; + assign #(INCLK_DELAY) delay_RECCLK = RECCLK; + assign #(INCLK_DELAY) delay_USERCLK = USERCLK; + + assign #(in_delay) delay_CFGCONFIGSPACEENABLE = CFGCONFIGSPACEENABLE; + assign #(in_delay) delay_CFGDEVID = CFGDEVID; + assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER; + assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER; + assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER; + assign #(in_delay) delay_CFGDSN = CFGDSN; + assign #(in_delay) delay_CFGDSPORTNUMBER = CFGDSPORTNUMBER; + assign #(in_delay) delay_CFGERRCORIN = CFGERRCORIN; + assign #(in_delay) delay_CFGERRUNCORIN = CFGERRUNCORIN; + assign #(in_delay) delay_CFGEXTREADDATA = CFGEXTREADDATA; + assign #(in_delay) delay_CFGEXTREADDATAVALID = CFGEXTREADDATAVALID; + assign #(in_delay) delay_CFGFCSEL = CFGFCSEL; + assign #(in_delay) delay_CFGFLRDONE = CFGFLRDONE; + assign #(in_delay) delay_CFGHOTRESETIN = CFGHOTRESETIN; + assign #(in_delay) delay_CFGINPUTUPDATEREQUEST = CFGINPUTUPDATEREQUEST; + assign #(in_delay) delay_CFGINTERRUPTINT = CFGINTERRUPTINT; + assign #(in_delay) delay_CFGINTERRUPTMSIATTR = CFGINTERRUPTMSIATTR; + assign #(in_delay) delay_CFGINTERRUPTMSIFUNCTIONNUMBER = CFGINTERRUPTMSIFUNCTIONNUMBER; + assign #(in_delay) delay_CFGINTERRUPTMSIINT = CFGINTERRUPTMSIINT; + assign #(in_delay) delay_CFGINTERRUPTMSIPENDINGSTATUS = CFGINTERRUPTMSIPENDINGSTATUS; + assign #(in_delay) delay_CFGINTERRUPTMSISELECT = CFGINTERRUPTMSISELECT; + assign #(in_delay) delay_CFGINTERRUPTMSITPHPRESENT = CFGINTERRUPTMSITPHPRESENT; + assign #(in_delay) delay_CFGINTERRUPTMSITPHSTTAG = CFGINTERRUPTMSITPHSTTAG; + assign #(in_delay) delay_CFGINTERRUPTMSITPHTYPE = CFGINTERRUPTMSITPHTYPE; + assign #(in_delay) delay_CFGINTERRUPTMSIXADDRESS = CFGINTERRUPTMSIXADDRESS; + assign #(in_delay) delay_CFGINTERRUPTMSIXDATA = CFGINTERRUPTMSIXDATA; + assign #(in_delay) delay_CFGINTERRUPTMSIXINT = CFGINTERRUPTMSIXINT; + assign #(in_delay) delay_CFGINTERRUPTPENDING = CFGINTERRUPTPENDING; + assign #(in_delay) delay_CFGLINKTRAININGENABLE = CFGLINKTRAININGENABLE; + assign #(in_delay) delay_CFGMCUPDATEREQUEST = CFGMCUPDATEREQUEST; + assign #(in_delay) delay_CFGMGMTADDR = CFGMGMTADDR; + assign #(in_delay) delay_CFGMGMTBYTEENABLE = CFGMGMTBYTEENABLE; + assign #(in_delay) delay_CFGMGMTREAD = CFGMGMTREAD; + assign #(in_delay) delay_CFGMGMTTYPE1CFGREGACCESS = CFGMGMTTYPE1CFGREGACCESS; + assign #(in_delay) delay_CFGMGMTWRITE = CFGMGMTWRITE; + assign #(in_delay) delay_CFGMGMTWRITEDATA = CFGMGMTWRITEDATA; + assign #(in_delay) delay_CFGMSGTRANSMIT = CFGMSGTRANSMIT; + assign #(in_delay) delay_CFGMSGTRANSMITDATA = CFGMSGTRANSMITDATA; + assign #(in_delay) delay_CFGMSGTRANSMITTYPE = CFGMSGTRANSMITTYPE; + assign #(in_delay) delay_CFGPERFUNCSTATUSCONTROL = CFGPERFUNCSTATUSCONTROL; + assign #(in_delay) delay_CFGPERFUNCTIONNUMBER = CFGPERFUNCTIONNUMBER; + assign #(in_delay) delay_CFGPERFUNCTIONOUTPUTREQUEST = CFGPERFUNCTIONOUTPUTREQUEST; + assign #(in_delay) delay_CFGPOWERSTATECHANGEACK = CFGPOWERSTATECHANGEACK; + assign #(in_delay) delay_CFGREQPMTRANSITIONL23READY = CFGREQPMTRANSITIONL23READY; + assign #(in_delay) delay_CFGREVID = CFGREVID; + assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID; + assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID; + assign #(in_delay) delay_CFGTPHSTTREADDATA = CFGTPHSTTREADDATA; + assign #(in_delay) delay_CFGTPHSTTREADDATAVALID = CFGTPHSTTREADDATAVALID; + assign #(in_delay) delay_CFGVENDID = CFGVENDID; + assign #(in_delay) delay_CFGVFFLRDONE = CFGVFFLRDONE; + assign #(in_delay) delay_DRPADDR = DRPADDR; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPEN = DRPEN; + assign #(in_delay) delay_DRPWE = DRPWE; + assign #(in_delay) delay_MAXISCQTREADY = MAXISCQTREADY; + assign #(in_delay) delay_MAXISRCTREADY = MAXISRCTREADY; + assign #(in_delay) delay_MGMTRESETN = MGMTRESETN; + assign #(in_delay) delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN; + assign #(in_delay) delay_MICOMPLETIONRAMREADDATA = MICOMPLETIONRAMREADDATA; + assign #(in_delay) delay_MIREPLAYRAMREADDATA = MIREPLAYRAMREADDATA; + assign #(in_delay) delay_MIREQUESTRAMREADDATA = MIREQUESTRAMREADDATA; + assign #(in_delay) delay_PCIECQNPREQ = PCIECQNPREQ; + assign #(in_delay) delay_PIPEEQFS = PIPEEQFS; + assign #(in_delay) delay_PIPEEQLF = PIPEEQLF; + assign #(in_delay) delay_PIPERESETN = PIPERESETN; + assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK; + assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA; + assign #(in_delay) delay_PIPERX0DATAVALID = PIPERX0DATAVALID; + assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE; + assign #(in_delay) delay_PIPERX0EQDONE = PIPERX0EQDONE; + assign #(in_delay) delay_PIPERX0EQLPADAPTDONE = PIPERX0EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX0EQLPLFFSSEL = PIPERX0EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX0EQLPNEWTXCOEFFORPRESET = PIPERX0EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS; + assign #(in_delay) delay_PIPERX0STARTBLOCK = PIPERX0STARTBLOCK; + assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS; + assign #(in_delay) delay_PIPERX0SYNCHEADER = PIPERX0SYNCHEADER; + assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID; + assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK; + assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA; + assign #(in_delay) delay_PIPERX1DATAVALID = PIPERX1DATAVALID; + assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE; + assign #(in_delay) delay_PIPERX1EQDONE = PIPERX1EQDONE; + assign #(in_delay) delay_PIPERX1EQLPADAPTDONE = PIPERX1EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX1EQLPLFFSSEL = PIPERX1EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX1EQLPNEWTXCOEFFORPRESET = PIPERX1EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS; + assign #(in_delay) delay_PIPERX1STARTBLOCK = PIPERX1STARTBLOCK; + assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS; + assign #(in_delay) delay_PIPERX1SYNCHEADER = PIPERX1SYNCHEADER; + assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID; + assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK; + assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA; + assign #(in_delay) delay_PIPERX2DATAVALID = PIPERX2DATAVALID; + assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE; + assign #(in_delay) delay_PIPERX2EQDONE = PIPERX2EQDONE; + assign #(in_delay) delay_PIPERX2EQLPADAPTDONE = PIPERX2EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX2EQLPLFFSSEL = PIPERX2EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX2EQLPNEWTXCOEFFORPRESET = PIPERX2EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS; + assign #(in_delay) delay_PIPERX2STARTBLOCK = PIPERX2STARTBLOCK; + assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS; + assign #(in_delay) delay_PIPERX2SYNCHEADER = PIPERX2SYNCHEADER; + assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID; + assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK; + assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA; + assign #(in_delay) delay_PIPERX3DATAVALID = PIPERX3DATAVALID; + assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE; + assign #(in_delay) delay_PIPERX3EQDONE = PIPERX3EQDONE; + assign #(in_delay) delay_PIPERX3EQLPADAPTDONE = PIPERX3EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX3EQLPLFFSSEL = PIPERX3EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX3EQLPNEWTXCOEFFORPRESET = PIPERX3EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS; + assign #(in_delay) delay_PIPERX3STARTBLOCK = PIPERX3STARTBLOCK; + assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS; + assign #(in_delay) delay_PIPERX3SYNCHEADER = PIPERX3SYNCHEADER; + assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID; + assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK; + assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA; + assign #(in_delay) delay_PIPERX4DATAVALID = PIPERX4DATAVALID; + assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE; + assign #(in_delay) delay_PIPERX4EQDONE = PIPERX4EQDONE; + assign #(in_delay) delay_PIPERX4EQLPADAPTDONE = PIPERX4EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX4EQLPLFFSSEL = PIPERX4EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX4EQLPNEWTXCOEFFORPRESET = PIPERX4EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS; + assign #(in_delay) delay_PIPERX4STARTBLOCK = PIPERX4STARTBLOCK; + assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS; + assign #(in_delay) delay_PIPERX4SYNCHEADER = PIPERX4SYNCHEADER; + assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID; + assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK; + assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA; + assign #(in_delay) delay_PIPERX5DATAVALID = PIPERX5DATAVALID; + assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE; + assign #(in_delay) delay_PIPERX5EQDONE = PIPERX5EQDONE; + assign #(in_delay) delay_PIPERX5EQLPADAPTDONE = PIPERX5EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX5EQLPLFFSSEL = PIPERX5EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX5EQLPNEWTXCOEFFORPRESET = PIPERX5EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS; + assign #(in_delay) delay_PIPERX5STARTBLOCK = PIPERX5STARTBLOCK; + assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS; + assign #(in_delay) delay_PIPERX5SYNCHEADER = PIPERX5SYNCHEADER; + assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID; + assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK; + assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA; + assign #(in_delay) delay_PIPERX6DATAVALID = PIPERX6DATAVALID; + assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE; + assign #(in_delay) delay_PIPERX6EQDONE = PIPERX6EQDONE; + assign #(in_delay) delay_PIPERX6EQLPADAPTDONE = PIPERX6EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX6EQLPLFFSSEL = PIPERX6EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX6EQLPNEWTXCOEFFORPRESET = PIPERX6EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS; + assign #(in_delay) delay_PIPERX6STARTBLOCK = PIPERX6STARTBLOCK; + assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS; + assign #(in_delay) delay_PIPERX6SYNCHEADER = PIPERX6SYNCHEADER; + assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID; + assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK; + assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA; + assign #(in_delay) delay_PIPERX7DATAVALID = PIPERX7DATAVALID; + assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE; + assign #(in_delay) delay_PIPERX7EQDONE = PIPERX7EQDONE; + assign #(in_delay) delay_PIPERX7EQLPADAPTDONE = PIPERX7EQLPADAPTDONE; + assign #(in_delay) delay_PIPERX7EQLPLFFSSEL = PIPERX7EQLPLFFSSEL; + assign #(in_delay) delay_PIPERX7EQLPNEWTXCOEFFORPRESET = PIPERX7EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS; + assign #(in_delay) delay_PIPERX7STARTBLOCK = PIPERX7STARTBLOCK; + assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS; + assign #(in_delay) delay_PIPERX7SYNCHEADER = PIPERX7SYNCHEADER; + assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID; + assign #(in_delay) delay_PIPETX0EQCOEFF = PIPETX0EQCOEFF; + assign #(in_delay) delay_PIPETX0EQDONE = PIPETX0EQDONE; + assign #(in_delay) delay_PIPETX1EQCOEFF = PIPETX1EQCOEFF; + assign #(in_delay) delay_PIPETX1EQDONE = PIPETX1EQDONE; + assign #(in_delay) delay_PIPETX2EQCOEFF = PIPETX2EQCOEFF; + assign #(in_delay) delay_PIPETX2EQDONE = PIPETX2EQDONE; + assign #(in_delay) delay_PIPETX3EQCOEFF = PIPETX3EQCOEFF; + assign #(in_delay) delay_PIPETX3EQDONE = PIPETX3EQDONE; + assign #(in_delay) delay_PIPETX4EQCOEFF = PIPETX4EQCOEFF; + assign #(in_delay) delay_PIPETX4EQDONE = PIPETX4EQDONE; + assign #(in_delay) delay_PIPETX5EQCOEFF = PIPETX5EQCOEFF; + assign #(in_delay) delay_PIPETX5EQDONE = PIPETX5EQDONE; + assign #(in_delay) delay_PIPETX6EQCOEFF = PIPETX6EQCOEFF; + assign #(in_delay) delay_PIPETX6EQDONE = PIPETX6EQDONE; + assign #(in_delay) delay_PIPETX7EQCOEFF = PIPETX7EQCOEFF; + assign #(in_delay) delay_PIPETX7EQDONE = PIPETX7EQDONE; + assign #(in_delay) delay_PLDISABLESCRAMBLER = PLDISABLESCRAMBLER; + assign #(in_delay) delay_PLEQRESETEIEOSCOUNT = PLEQRESETEIEOSCOUNT; + assign #(in_delay) delay_PLGEN3PCSDISABLE = PLGEN3PCSDISABLE; + assign #(in_delay) delay_PLGEN3PCSRXSYNCDONE = PLGEN3PCSRXSYNCDONE; + assign #(in_delay) delay_RESETN = RESETN; + assign #(in_delay) delay_SAXISCCTDATA = SAXISCCTDATA; + assign #(in_delay) delay_SAXISCCTKEEP = SAXISCCTKEEP; + assign #(in_delay) delay_SAXISCCTLAST = SAXISCCTLAST; + assign #(in_delay) delay_SAXISCCTUSER = SAXISCCTUSER; + assign #(in_delay) delay_SAXISCCTVALID = SAXISCCTVALID; + assign #(in_delay) delay_SAXISRQTDATA = SAXISRQTDATA; + assign #(in_delay) delay_SAXISRQTKEEP = SAXISRQTKEEP; + assign #(in_delay) delay_SAXISRQTLAST = SAXISRQTLAST; + assign #(in_delay) delay_SAXISRQTUSER = SAXISRQTUSER; + assign #(in_delay) delay_SAXISRQTVALID = SAXISRQTVALID; +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING //Simprim + assign delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML; + assign delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU; + assign delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM; + assign delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM; + assign delay_MGMTRESETN = MGMTRESETN; + assign delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN; + assign delay_PIPERESETN = PIPERESETN; + assign delay_RESETN = RESETN; +`endif + + B_PCIE_3_0 #( + .ARI_CAP_ENABLE (ARI_CAP_ENABLE), + .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE), + .AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK), + .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE), + .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG), + .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE), + .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC), + .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE), + .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE), + .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE), + .AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK), + .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH), + .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500), + .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM), + .GEN3_PCS_AUTO_REALIGN (GEN3_PCS_AUTO_REALIGN), + .GEN3_PCS_RX_ELECIDLE_INTERNAL (GEN3_PCS_RX_ELECIDLE_INTERNAL), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC), + .LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER), + .LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE), + .LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER), + .LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE), + .LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER), + .LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE), + .LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER), + .LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC), + .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL), + .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE), + .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE), + .PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE), + .PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE), + .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR), + .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR), + .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC), + .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER), + .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE), + .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL), + .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE), + .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL), + .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE), + .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL), + .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE), + .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL), + .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE), + .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL), + .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE), + .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL), + .PF0_BIST_REGISTER (PF0_BIST_REGISTER), + .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER), + .PF0_CLASS_CODE (PF0_CLASS_CODE), + .PF0_DEVICE_ID (PF0_DEVICE_ID), + .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT), + .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT), + .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT), + .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE), + .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT), + .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT), + .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT), + .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY), + .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY), + .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED), + .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE), + .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE), + .PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR), + .PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL), + .PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7), + .PF0_DPA_CAP_VER (PF0_DPA_CAP_VER), + .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR), + .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE), + .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE), + .PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE), + .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN), + .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3), + .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG), + .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT), + .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT), + .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR), + .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER), + .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR), + .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR), + .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET), + .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR), + .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET), + .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE), + .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP), + .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR), + .PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR), + .PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED), + .PF0_PB_CAP_VER (PF0_PB_CAP_VER), + .PF0_PM_CAP_ID (PF0_PM_CAP_ID), + .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR), + .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0), + .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1), + .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT), + .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE), + .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID), + .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET), + .PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE), + .PF0_RBAR_CAP_INDEX0 (PF0_RBAR_CAP_INDEX0), + .PF0_RBAR_CAP_INDEX1 (PF0_RBAR_CAP_INDEX1), + .PF0_RBAR_CAP_INDEX2 (PF0_RBAR_CAP_INDEX2), + .PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR), + .PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0), + .PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1), + .PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2), + .PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER), + .PF0_RBAR_NUM (PF0_RBAR_NUM), + .PF0_REVISION_ID (PF0_REVISION_ID), + .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE), + .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL), + .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE), + .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL), + .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE), + .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL), + .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE), + .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL), + .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE), + .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL), + .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE), + .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL), + .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF), + .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR), + .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF), + .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER), + .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET), + .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK), + .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE), + .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID), + .PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID), + .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE), + .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE), + .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE), + .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR), + .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL), + .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC), + .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE), + .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER), + .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR), + .PF0_VC_CAP_VER (PF0_VC_CAP_VER), + .PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE), + .PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE), + .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR), + .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR), + .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC), + .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE), + .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL), + .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE), + .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL), + .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE), + .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL), + .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE), + .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL), + .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE), + .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL), + .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE), + .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL), + .PF1_BIST_REGISTER (PF1_BIST_REGISTER), + .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER), + .PF1_CLASS_CODE (PF1_CLASS_CODE), + .PF1_DEVICE_ID (PF1_DEVICE_ID), + .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE), + .PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR), + .PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL), + .PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7), + .PF1_DPA_CAP_VER (PF1_DPA_CAP_VER), + .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR), + .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE), + .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE), + .PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE), + .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN), + .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR), + .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR), + .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET), + .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR), + .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET), + .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE), + .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP), + .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR), + .PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR), + .PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED), + .PF1_PB_CAP_VER (PF1_PB_CAP_VER), + .PF1_PM_CAP_ID (PF1_PM_CAP_ID), + .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR), + .PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID), + .PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE), + .PF1_RBAR_CAP_INDEX0 (PF1_RBAR_CAP_INDEX0), + .PF1_RBAR_CAP_INDEX1 (PF1_RBAR_CAP_INDEX1), + .PF1_RBAR_CAP_INDEX2 (PF1_RBAR_CAP_INDEX2), + .PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR), + .PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0), + .PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1), + .PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2), + .PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER), + .PF1_RBAR_NUM (PF1_RBAR_NUM), + .PF1_REVISION_ID (PF1_REVISION_ID), + .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE), + .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL), + .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE), + .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL), + .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE), + .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL), + .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE), + .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL), + .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE), + .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL), + .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE), + .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL), + .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF), + .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR), + .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF), + .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER), + .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET), + .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK), + .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE), + .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID), + .PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID), + .PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE), + .PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE), + .PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE), + .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR), + .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL), + .PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC), + .PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE), + .PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER), + .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0), + .PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE), + .PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING), + .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE), + .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK), + .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK), + .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT), + .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT), + .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23), + .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE), + .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL), + .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL), + .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL), + .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL), + .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL), + .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL), + .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL), + .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL), + .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED), + .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH), + .PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1), + .PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2), + .PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3), + .PL_N_FTS_GEN1 (PL_N_FTS_GEN1), + .PL_N_FTS_GEN2 (PL_N_FTS_GEN2), + .PL_N_FTS_GEN3 (PL_N_FTS_GEN3), + .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING), + .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING), + .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT), + .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY), + .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE), + .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY), + .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY), + .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY), + .SIM_VERSION (SIM_VERSION), + .SPARE_BIT0 (SPARE_BIT0), + .SPARE_BIT1 (SPARE_BIT1), + .SPARE_BIT2 (SPARE_BIT2), + .SPARE_BIT3 (SPARE_BIT3), + .SPARE_BIT4 (SPARE_BIT4), + .SPARE_BIT5 (SPARE_BIT5), + .SPARE_BIT6 (SPARE_BIT6), + .SPARE_BIT7 (SPARE_BIT7), + .SPARE_BIT8 (SPARE_BIT8), + .SPARE_BYTE0 (SPARE_BYTE0), + .SPARE_BYTE1 (SPARE_BYTE1), + .SPARE_BYTE2 (SPARE_BYTE2), + .SPARE_BYTE3 (SPARE_BYTE3), + .SPARE_WORD0 (SPARE_WORD0), + .SPARE_WORD1 (SPARE_WORD1), + .SPARE_WORD2 (SPARE_WORD2), + .SPARE_WORD3 (SPARE_WORD3), + .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE), + .TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0), + .TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1), + .TL_CREDITS_CD (TL_CREDITS_CD), + .TL_CREDITS_CH (TL_CREDITS_CH), + .TL_CREDITS_NPD (TL_CREDITS_NPD), + .TL_CREDITS_NPH (TL_CREDITS_NPH), + .TL_CREDITS_PD (TL_CREDITS_PD), + .TL_CREDITS_PH (TL_CREDITS_PH), + .TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE), + .TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE), + .TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE), + .TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE), + .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG), + .TL_TAG_MGMT_ENABLE (TL_TAG_MGMT_ENABLE), + .VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR), + .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER), + .VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR), + .VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET), + .VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR), + .VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET), + .VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE), + .VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP), + .VF0_PM_CAP_ID (VF0_PM_CAP_ID), + .VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR), + .VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID), + .VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE), + .VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE), + .VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR), + .VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL), + .VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC), + .VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE), + .VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER), + .VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR), + .VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR), + .VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET), + .VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR), + .VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET), + .VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE), + .VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP), + .VF1_PM_CAP_ID (VF1_PM_CAP_ID), + .VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR), + .VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID), + .VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE), + .VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE), + .VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR), + .VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL), + .VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC), + .VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE), + .VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER), + .VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR), + .VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR), + .VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET), + .VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR), + .VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET), + .VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE), + .VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP), + .VF2_PM_CAP_ID (VF2_PM_CAP_ID), + .VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR), + .VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID), + .VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE), + .VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE), + .VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR), + .VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL), + .VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC), + .VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE), + .VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER), + .VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR), + .VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR), + .VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET), + .VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR), + .VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET), + .VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE), + .VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP), + .VF3_PM_CAP_ID (VF3_PM_CAP_ID), + .VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR), + .VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID), + .VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE), + .VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE), + .VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR), + .VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL), + .VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC), + .VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE), + .VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER), + .VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR), + .VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR), + .VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET), + .VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR), + .VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET), + .VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE), + .VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP), + .VF4_PM_CAP_ID (VF4_PM_CAP_ID), + .VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR), + .VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID), + .VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE), + .VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE), + .VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR), + .VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL), + .VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC), + .VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE), + .VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER), + .VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR), + .VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR), + .VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET), + .VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR), + .VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET), + .VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE), + .VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP), + .VF5_PM_CAP_ID (VF5_PM_CAP_ID), + .VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR), + .VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID), + .VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE), + .VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE), + .VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE), + .VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR), + .VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL), + .VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC), + .VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE), + .VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER)) + + B_PCIE_3_0_INST ( + .CFGCURRENTSPEED (delay_CFGCURRENTSPEED), + .CFGDPASUBSTATECHANGE (delay_CFGDPASUBSTATECHANGE), + .CFGERRCOROUT (delay_CFGERRCOROUT), + .CFGERRFATALOUT (delay_CFGERRFATALOUT), + .CFGERRNONFATALOUT (delay_CFGERRNONFATALOUT), + .CFGEXTFUNCTIONNUMBER (delay_CFGEXTFUNCTIONNUMBER), + .CFGEXTREADRECEIVED (delay_CFGEXTREADRECEIVED), + .CFGEXTREGISTERNUMBER (delay_CFGEXTREGISTERNUMBER), + .CFGEXTWRITEBYTEENABLE (delay_CFGEXTWRITEBYTEENABLE), + .CFGEXTWRITEDATA (delay_CFGEXTWRITEDATA), + .CFGEXTWRITERECEIVED (delay_CFGEXTWRITERECEIVED), + .CFGFCCPLD (delay_CFGFCCPLD), + .CFGFCCPLH (delay_CFGFCCPLH), + .CFGFCNPD (delay_CFGFCNPD), + .CFGFCNPH (delay_CFGFCNPH), + .CFGFCPD (delay_CFGFCPD), + .CFGFCPH (delay_CFGFCPH), + .CFGFLRINPROCESS (delay_CFGFLRINPROCESS), + .CFGFUNCTIONPOWERSTATE (delay_CFGFUNCTIONPOWERSTATE), + .CFGFUNCTIONSTATUS (delay_CFGFUNCTIONSTATUS), + .CFGHOTRESETOUT (delay_CFGHOTRESETOUT), + .CFGINPUTUPDATEDONE (delay_CFGINPUTUPDATEDONE), + .CFGINTERRUPTAOUTPUT (delay_CFGINTERRUPTAOUTPUT), + .CFGINTERRUPTBOUTPUT (delay_CFGINTERRUPTBOUTPUT), + .CFGINTERRUPTCOUTPUT (delay_CFGINTERRUPTCOUTPUT), + .CFGINTERRUPTDOUTPUT (delay_CFGINTERRUPTDOUTPUT), + .CFGINTERRUPTMSIDATA (delay_CFGINTERRUPTMSIDATA), + .CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE), + .CFGINTERRUPTMSIFAIL (delay_CFGINTERRUPTMSIFAIL), + .CFGINTERRUPTMSIMASKUPDATE (delay_CFGINTERRUPTMSIMASKUPDATE), + .CFGINTERRUPTMSIMMENABLE (delay_CFGINTERRUPTMSIMMENABLE), + .CFGINTERRUPTMSISENT (delay_CFGINTERRUPTMSISENT), + .CFGINTERRUPTMSIVFENABLE (delay_CFGINTERRUPTMSIVFENABLE), + .CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE), + .CFGINTERRUPTMSIXFAIL (delay_CFGINTERRUPTMSIXFAIL), + .CFGINTERRUPTMSIXMASK (delay_CFGINTERRUPTMSIXMASK), + .CFGINTERRUPTMSIXSENT (delay_CFGINTERRUPTMSIXSENT), + .CFGINTERRUPTMSIXVFENABLE (delay_CFGINTERRUPTMSIXVFENABLE), + .CFGINTERRUPTMSIXVFMASK (delay_CFGINTERRUPTMSIXVFMASK), + .CFGINTERRUPTSENT (delay_CFGINTERRUPTSENT), + .CFGLINKPOWERSTATE (delay_CFGLINKPOWERSTATE), + .CFGLOCALERROR (delay_CFGLOCALERROR), + .CFGLTRENABLE (delay_CFGLTRENABLE), + .CFGLTSSMSTATE (delay_CFGLTSSMSTATE), + .CFGMAXPAYLOAD (delay_CFGMAXPAYLOAD), + .CFGMAXREADREQ (delay_CFGMAXREADREQ), + .CFGMCUPDATEDONE (delay_CFGMCUPDATEDONE), + .CFGMGMTREADDATA (delay_CFGMGMTREADDATA), + .CFGMGMTREADWRITEDONE (delay_CFGMGMTREADWRITEDONE), + .CFGMSGRECEIVED (delay_CFGMSGRECEIVED), + .CFGMSGRECEIVEDDATA (delay_CFGMSGRECEIVEDDATA), + .CFGMSGRECEIVEDTYPE (delay_CFGMSGRECEIVEDTYPE), + .CFGMSGTRANSMITDONE (delay_CFGMSGTRANSMITDONE), + .CFGNEGOTIATEDWIDTH (delay_CFGNEGOTIATEDWIDTH), + .CFGOBFFENABLE (delay_CFGOBFFENABLE), + .CFGPERFUNCSTATUSDATA (delay_CFGPERFUNCSTATUSDATA), + .CFGPERFUNCTIONUPDATEDONE (delay_CFGPERFUNCTIONUPDATEDONE), + .CFGPHYLINKDOWN (delay_CFGPHYLINKDOWN), + .CFGPHYLINKSTATUS (delay_CFGPHYLINKSTATUS), + .CFGPLSTATUSCHANGE (delay_CFGPLSTATUSCHANGE), + .CFGPOWERSTATECHANGEINTERRUPT (delay_CFGPOWERSTATECHANGEINTERRUPT), + .CFGRCBSTATUS (delay_CFGRCBSTATUS), + .CFGTPHFUNCTIONNUM (delay_CFGTPHFUNCTIONNUM), + .CFGTPHREQUESTERENABLE (delay_CFGTPHREQUESTERENABLE), + .CFGTPHSTMODE (delay_CFGTPHSTMODE), + .CFGTPHSTTADDRESS (delay_CFGTPHSTTADDRESS), + .CFGTPHSTTREADENABLE (delay_CFGTPHSTTREADENABLE), + .CFGTPHSTTWRITEBYTEVALID (delay_CFGTPHSTTWRITEBYTEVALID), + .CFGTPHSTTWRITEDATA (delay_CFGTPHSTTWRITEDATA), + .CFGTPHSTTWRITEENABLE (delay_CFGTPHSTTWRITEENABLE), + .CFGVFFLRINPROCESS (delay_CFGVFFLRINPROCESS), + .CFGVFPOWERSTATE (delay_CFGVFPOWERSTATE), + .CFGVFSTATUS (delay_CFGVFSTATUS), + .CFGVFTPHREQUESTERENABLE (delay_CFGVFTPHREQUESTERENABLE), + .CFGVFTPHSTMODE (delay_CFGVFTPHSTMODE), + .DBGDATAOUT (delay_DBGDATAOUT), + .DRPDO (delay_DRPDO), + .DRPRDY (delay_DRPRDY), + .MAXISCQTDATA (delay_MAXISCQTDATA), + .MAXISCQTKEEP (delay_MAXISCQTKEEP), + .MAXISCQTLAST (delay_MAXISCQTLAST), + .MAXISCQTUSER (delay_MAXISCQTUSER), + .MAXISCQTVALID (delay_MAXISCQTVALID), + .MAXISRCTDATA (delay_MAXISRCTDATA), + .MAXISRCTKEEP (delay_MAXISRCTKEEP), + .MAXISRCTLAST (delay_MAXISRCTLAST), + .MAXISRCTUSER (delay_MAXISRCTUSER), + .MAXISRCTVALID (delay_MAXISRCTVALID), + .MICOMPLETIONRAMREADADDRESSAL (delay_MICOMPLETIONRAMREADADDRESSAL), + .MICOMPLETIONRAMREADADDRESSAU (delay_MICOMPLETIONRAMREADADDRESSAU), + .MICOMPLETIONRAMREADADDRESSBL (delay_MICOMPLETIONRAMREADADDRESSBL), + .MICOMPLETIONRAMREADADDRESSBU (delay_MICOMPLETIONRAMREADADDRESSBU), + .MICOMPLETIONRAMREADENABLEL (delay_MICOMPLETIONRAMREADENABLEL), + .MICOMPLETIONRAMREADENABLEU (delay_MICOMPLETIONRAMREADENABLEU), + .MICOMPLETIONRAMWRITEADDRESSAL (delay_MICOMPLETIONRAMWRITEADDRESSAL), + .MICOMPLETIONRAMWRITEADDRESSAU (delay_MICOMPLETIONRAMWRITEADDRESSAU), + .MICOMPLETIONRAMWRITEADDRESSBL (delay_MICOMPLETIONRAMWRITEADDRESSBL), + .MICOMPLETIONRAMWRITEADDRESSBU (delay_MICOMPLETIONRAMWRITEADDRESSBU), + .MICOMPLETIONRAMWRITEDATAL (delay_MICOMPLETIONRAMWRITEDATAL), + .MICOMPLETIONRAMWRITEDATAU (delay_MICOMPLETIONRAMWRITEDATAU), + .MICOMPLETIONRAMWRITEENABLEL (delay_MICOMPLETIONRAMWRITEENABLEL), + .MICOMPLETIONRAMWRITEENABLEU (delay_MICOMPLETIONRAMWRITEENABLEU), + .MIREPLAYRAMADDRESS (delay_MIREPLAYRAMADDRESS), + .MIREPLAYRAMREADENABLE (delay_MIREPLAYRAMREADENABLE), + .MIREPLAYRAMWRITEDATA (delay_MIREPLAYRAMWRITEDATA), + .MIREPLAYRAMWRITEENABLE (delay_MIREPLAYRAMWRITEENABLE), + .MIREQUESTRAMREADADDRESSA (delay_MIREQUESTRAMREADADDRESSA), + .MIREQUESTRAMREADADDRESSB (delay_MIREQUESTRAMREADADDRESSB), + .MIREQUESTRAMREADENABLE (delay_MIREQUESTRAMREADENABLE), + .MIREQUESTRAMWRITEADDRESSA (delay_MIREQUESTRAMWRITEADDRESSA), + .MIREQUESTRAMWRITEADDRESSB (delay_MIREQUESTRAMWRITEADDRESSB), + .MIREQUESTRAMWRITEDATA (delay_MIREQUESTRAMWRITEDATA), + .MIREQUESTRAMWRITEENABLE (delay_MIREQUESTRAMWRITEENABLE), + .PCIECQNPREQCOUNT (delay_PCIECQNPREQCOUNT), + .PCIERQSEQNUM (delay_PCIERQSEQNUM), + .PCIERQSEQNUMVLD (delay_PCIERQSEQNUMVLD), + .PCIERQTAG (delay_PCIERQTAG), + .PCIERQTAGAV (delay_PCIERQTAGAV), + .PCIERQTAGVLD (delay_PCIERQTAGVLD), + .PCIETFCNPDAV (delay_PCIETFCNPDAV), + .PCIETFCNPHAV (delay_PCIETFCNPHAV), + .PIPERX0EQCONTROL (delay_PIPERX0EQCONTROL), + .PIPERX0EQLPLFFS (delay_PIPERX0EQLPLFFS), + .PIPERX0EQLPTXPRESET (delay_PIPERX0EQLPTXPRESET), + .PIPERX0EQPRESET (delay_PIPERX0EQPRESET), + .PIPERX0POLARITY (delay_PIPERX0POLARITY), + .PIPERX1EQCONTROL (delay_PIPERX1EQCONTROL), + .PIPERX1EQLPLFFS (delay_PIPERX1EQLPLFFS), + .PIPERX1EQLPTXPRESET (delay_PIPERX1EQLPTXPRESET), + .PIPERX1EQPRESET (delay_PIPERX1EQPRESET), + .PIPERX1POLARITY (delay_PIPERX1POLARITY), + .PIPERX2EQCONTROL (delay_PIPERX2EQCONTROL), + .PIPERX2EQLPLFFS (delay_PIPERX2EQLPLFFS), + .PIPERX2EQLPTXPRESET (delay_PIPERX2EQLPTXPRESET), + .PIPERX2EQPRESET (delay_PIPERX2EQPRESET), + .PIPERX2POLARITY (delay_PIPERX2POLARITY), + .PIPERX3EQCONTROL (delay_PIPERX3EQCONTROL), + .PIPERX3EQLPLFFS (delay_PIPERX3EQLPLFFS), + .PIPERX3EQLPTXPRESET (delay_PIPERX3EQLPTXPRESET), + .PIPERX3EQPRESET (delay_PIPERX3EQPRESET), + .PIPERX3POLARITY (delay_PIPERX3POLARITY), + .PIPERX4EQCONTROL (delay_PIPERX4EQCONTROL), + .PIPERX4EQLPLFFS (delay_PIPERX4EQLPLFFS), + .PIPERX4EQLPTXPRESET (delay_PIPERX4EQLPTXPRESET), + .PIPERX4EQPRESET (delay_PIPERX4EQPRESET), + .PIPERX4POLARITY (delay_PIPERX4POLARITY), + .PIPERX5EQCONTROL (delay_PIPERX5EQCONTROL), + .PIPERX5EQLPLFFS (delay_PIPERX5EQLPLFFS), + .PIPERX5EQLPTXPRESET (delay_PIPERX5EQLPTXPRESET), + .PIPERX5EQPRESET (delay_PIPERX5EQPRESET), + .PIPERX5POLARITY (delay_PIPERX5POLARITY), + .PIPERX6EQCONTROL (delay_PIPERX6EQCONTROL), + .PIPERX6EQLPLFFS (delay_PIPERX6EQLPLFFS), + .PIPERX6EQLPTXPRESET (delay_PIPERX6EQLPTXPRESET), + .PIPERX6EQPRESET (delay_PIPERX6EQPRESET), + .PIPERX6POLARITY (delay_PIPERX6POLARITY), + .PIPERX7EQCONTROL (delay_PIPERX7EQCONTROL), + .PIPERX7EQLPLFFS (delay_PIPERX7EQLPLFFS), + .PIPERX7EQLPTXPRESET (delay_PIPERX7EQLPTXPRESET), + .PIPERX7EQPRESET (delay_PIPERX7EQPRESET), + .PIPERX7POLARITY (delay_PIPERX7POLARITY), + .PIPETX0CHARISK (delay_PIPETX0CHARISK), + .PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE), + .PIPETX0DATA (delay_PIPETX0DATA), + .PIPETX0DATAVALID (delay_PIPETX0DATAVALID), + .PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE), + .PIPETX0EQCONTROL (delay_PIPETX0EQCONTROL), + .PIPETX0EQDEEMPH (delay_PIPETX0EQDEEMPH), + .PIPETX0EQPRESET (delay_PIPETX0EQPRESET), + .PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN), + .PIPETX0STARTBLOCK (delay_PIPETX0STARTBLOCK), + .PIPETX0SYNCHEADER (delay_PIPETX0SYNCHEADER), + .PIPETX1CHARISK (delay_PIPETX1CHARISK), + .PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE), + .PIPETX1DATA (delay_PIPETX1DATA), + .PIPETX1DATAVALID (delay_PIPETX1DATAVALID), + .PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE), + .PIPETX1EQCONTROL (delay_PIPETX1EQCONTROL), + .PIPETX1EQDEEMPH (delay_PIPETX1EQDEEMPH), + .PIPETX1EQPRESET (delay_PIPETX1EQPRESET), + .PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN), + .PIPETX1STARTBLOCK (delay_PIPETX1STARTBLOCK), + .PIPETX1SYNCHEADER (delay_PIPETX1SYNCHEADER), + .PIPETX2CHARISK (delay_PIPETX2CHARISK), + .PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE), + .PIPETX2DATA (delay_PIPETX2DATA), + .PIPETX2DATAVALID (delay_PIPETX2DATAVALID), + .PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE), + .PIPETX2EQCONTROL (delay_PIPETX2EQCONTROL), + .PIPETX2EQDEEMPH (delay_PIPETX2EQDEEMPH), + .PIPETX2EQPRESET (delay_PIPETX2EQPRESET), + .PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN), + .PIPETX2STARTBLOCK (delay_PIPETX2STARTBLOCK), + .PIPETX2SYNCHEADER (delay_PIPETX2SYNCHEADER), + .PIPETX3CHARISK (delay_PIPETX3CHARISK), + .PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE), + .PIPETX3DATA (delay_PIPETX3DATA), + .PIPETX3DATAVALID (delay_PIPETX3DATAVALID), + .PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE), + .PIPETX3EQCONTROL (delay_PIPETX3EQCONTROL), + .PIPETX3EQDEEMPH (delay_PIPETX3EQDEEMPH), + .PIPETX3EQPRESET (delay_PIPETX3EQPRESET), + .PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN), + .PIPETX3STARTBLOCK (delay_PIPETX3STARTBLOCK), + .PIPETX3SYNCHEADER (delay_PIPETX3SYNCHEADER), + .PIPETX4CHARISK (delay_PIPETX4CHARISK), + .PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE), + .PIPETX4DATA (delay_PIPETX4DATA), + .PIPETX4DATAVALID (delay_PIPETX4DATAVALID), + .PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE), + .PIPETX4EQCONTROL (delay_PIPETX4EQCONTROL), + .PIPETX4EQDEEMPH (delay_PIPETX4EQDEEMPH), + .PIPETX4EQPRESET (delay_PIPETX4EQPRESET), + .PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN), + .PIPETX4STARTBLOCK (delay_PIPETX4STARTBLOCK), + .PIPETX4SYNCHEADER (delay_PIPETX4SYNCHEADER), + .PIPETX5CHARISK (delay_PIPETX5CHARISK), + .PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE), + .PIPETX5DATA (delay_PIPETX5DATA), + .PIPETX5DATAVALID (delay_PIPETX5DATAVALID), + .PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE), + .PIPETX5EQCONTROL (delay_PIPETX5EQCONTROL), + .PIPETX5EQDEEMPH (delay_PIPETX5EQDEEMPH), + .PIPETX5EQPRESET (delay_PIPETX5EQPRESET), + .PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN), + .PIPETX5STARTBLOCK (delay_PIPETX5STARTBLOCK), + .PIPETX5SYNCHEADER (delay_PIPETX5SYNCHEADER), + .PIPETX6CHARISK (delay_PIPETX6CHARISK), + .PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE), + .PIPETX6DATA (delay_PIPETX6DATA), + .PIPETX6DATAVALID (delay_PIPETX6DATAVALID), + .PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE), + .PIPETX6EQCONTROL (delay_PIPETX6EQCONTROL), + .PIPETX6EQDEEMPH (delay_PIPETX6EQDEEMPH), + .PIPETX6EQPRESET (delay_PIPETX6EQPRESET), + .PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN), + .PIPETX6STARTBLOCK (delay_PIPETX6STARTBLOCK), + .PIPETX6SYNCHEADER (delay_PIPETX6SYNCHEADER), + .PIPETX7CHARISK (delay_PIPETX7CHARISK), + .PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE), + .PIPETX7DATA (delay_PIPETX7DATA), + .PIPETX7DATAVALID (delay_PIPETX7DATAVALID), + .PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE), + .PIPETX7EQCONTROL (delay_PIPETX7EQCONTROL), + .PIPETX7EQDEEMPH (delay_PIPETX7EQDEEMPH), + .PIPETX7EQPRESET (delay_PIPETX7EQPRESET), + .PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN), + .PIPETX7STARTBLOCK (delay_PIPETX7STARTBLOCK), + .PIPETX7SYNCHEADER (delay_PIPETX7SYNCHEADER), + .PIPETXDEEMPH (delay_PIPETXDEEMPH), + .PIPETXMARGIN (delay_PIPETXMARGIN), + .PIPETXRATE (delay_PIPETXRATE), + .PIPETXRCVRDET (delay_PIPETXRCVRDET), + .PIPETXRESET (delay_PIPETXRESET), + .PIPETXSWING (delay_PIPETXSWING), + .PLEQINPROGRESS (delay_PLEQINPROGRESS), + .PLEQPHASE (delay_PLEQPHASE), + .PLGEN3PCSRXSLIDE (delay_PLGEN3PCSRXSLIDE), + .SAXISCCTREADY (delay_SAXISCCTREADY), + .SAXISRQTREADY (delay_SAXISRQTREADY), + .CFGCONFIGSPACEENABLE (delay_CFGCONFIGSPACEENABLE), + .CFGDEVID (delay_CFGDEVID), + .CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER), + .CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER), + .CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER), + .CFGDSN (delay_CFGDSN), + .CFGDSPORTNUMBER (delay_CFGDSPORTNUMBER), + .CFGERRCORIN (delay_CFGERRCORIN), + .CFGERRUNCORIN (delay_CFGERRUNCORIN), + .CFGEXTREADDATA (delay_CFGEXTREADDATA), + .CFGEXTREADDATAVALID (delay_CFGEXTREADDATAVALID), + .CFGFCSEL (delay_CFGFCSEL), + .CFGFLRDONE (delay_CFGFLRDONE), + .CFGHOTRESETIN (delay_CFGHOTRESETIN), + .CFGINPUTUPDATEREQUEST (delay_CFGINPUTUPDATEREQUEST), + .CFGINTERRUPTINT (delay_CFGINTERRUPTINT), + .CFGINTERRUPTMSIATTR (delay_CFGINTERRUPTMSIATTR), + .CFGINTERRUPTMSIFUNCTIONNUMBER (delay_CFGINTERRUPTMSIFUNCTIONNUMBER), + .CFGINTERRUPTMSIINT (delay_CFGINTERRUPTMSIINT), + .CFGINTERRUPTMSIPENDINGSTATUS (delay_CFGINTERRUPTMSIPENDINGSTATUS), + .CFGINTERRUPTMSISELECT (delay_CFGINTERRUPTMSISELECT), + .CFGINTERRUPTMSITPHPRESENT (delay_CFGINTERRUPTMSITPHPRESENT), + .CFGINTERRUPTMSITPHSTTAG (delay_CFGINTERRUPTMSITPHSTTAG), + .CFGINTERRUPTMSITPHTYPE (delay_CFGINTERRUPTMSITPHTYPE), + .CFGINTERRUPTMSIXADDRESS (delay_CFGINTERRUPTMSIXADDRESS), + .CFGINTERRUPTMSIXDATA (delay_CFGINTERRUPTMSIXDATA), + .CFGINTERRUPTMSIXINT (delay_CFGINTERRUPTMSIXINT), + .CFGINTERRUPTPENDING (delay_CFGINTERRUPTPENDING), + .CFGLINKTRAININGENABLE (delay_CFGLINKTRAININGENABLE), + .CFGMCUPDATEREQUEST (delay_CFGMCUPDATEREQUEST), + .CFGMGMTADDR (delay_CFGMGMTADDR), + .CFGMGMTBYTEENABLE (delay_CFGMGMTBYTEENABLE), + .CFGMGMTREAD (delay_CFGMGMTREAD), + .CFGMGMTTYPE1CFGREGACCESS (delay_CFGMGMTTYPE1CFGREGACCESS), + .CFGMGMTWRITE (delay_CFGMGMTWRITE), + .CFGMGMTWRITEDATA (delay_CFGMGMTWRITEDATA), + .CFGMSGTRANSMIT (delay_CFGMSGTRANSMIT), + .CFGMSGTRANSMITDATA (delay_CFGMSGTRANSMITDATA), + .CFGMSGTRANSMITTYPE (delay_CFGMSGTRANSMITTYPE), + .CFGPERFUNCSTATUSCONTROL (delay_CFGPERFUNCSTATUSCONTROL), + .CFGPERFUNCTIONNUMBER (delay_CFGPERFUNCTIONNUMBER), + .CFGPERFUNCTIONOUTPUTREQUEST (delay_CFGPERFUNCTIONOUTPUTREQUEST), + .CFGPOWERSTATECHANGEACK (delay_CFGPOWERSTATECHANGEACK), + .CFGREQPMTRANSITIONL23READY (delay_CFGREQPMTRANSITIONL23READY), + .CFGREVID (delay_CFGREVID), + .CFGSUBSYSID (delay_CFGSUBSYSID), + .CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID), + .CFGTPHSTTREADDATA (delay_CFGTPHSTTREADDATA), + .CFGTPHSTTREADDATAVALID (delay_CFGTPHSTTREADDATAVALID), + .CFGVENDID (delay_CFGVENDID), + .CFGVFFLRDONE (delay_CFGVFFLRDONE), + .CORECLK (delay_CORECLK), + .CORECLKMICOMPLETIONRAML (delay_CORECLKMICOMPLETIONRAML), + .CORECLKMICOMPLETIONRAMU (delay_CORECLKMICOMPLETIONRAMU), + .CORECLKMIREPLAYRAM (delay_CORECLKMIREPLAYRAM), + .CORECLKMIREQUESTRAM (delay_CORECLKMIREQUESTRAM), + .DRPADDR (delay_DRPADDR), + .DRPCLK (delay_DRPCLK), + .DRPDI (delay_DRPDI), + .DRPEN (delay_DRPEN), + .DRPWE (delay_DRPWE), + .MAXISCQTREADY (delay_MAXISCQTREADY), + .MAXISRCTREADY (delay_MAXISRCTREADY), + .MGMTRESETN (delay_MGMTRESETN), + .MGMTSTICKYRESETN (delay_MGMTSTICKYRESETN), + .MICOMPLETIONRAMREADDATA (delay_MICOMPLETIONRAMREADDATA), + .MIREPLAYRAMREADDATA (delay_MIREPLAYRAMREADDATA), + .MIREQUESTRAMREADDATA (delay_MIREQUESTRAMREADDATA), + .PCIECQNPREQ (delay_PCIECQNPREQ), + .PIPECLK (delay_PIPECLK), + .PIPEEQFS (delay_PIPEEQFS), + .PIPEEQLF (delay_PIPEEQLF), + .PIPERESETN (delay_PIPERESETN), + .PIPERX0CHARISK (delay_PIPERX0CHARISK), + .PIPERX0DATA (delay_PIPERX0DATA), + .PIPERX0DATAVALID (delay_PIPERX0DATAVALID), + .PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE), + .PIPERX0EQDONE (delay_PIPERX0EQDONE), + .PIPERX0EQLPADAPTDONE (delay_PIPERX0EQLPADAPTDONE), + .PIPERX0EQLPLFFSSEL (delay_PIPERX0EQLPLFFSSEL), + .PIPERX0EQLPNEWTXCOEFFORPRESET (delay_PIPERX0EQLPNEWTXCOEFFORPRESET), + .PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS), + .PIPERX0STARTBLOCK (delay_PIPERX0STARTBLOCK), + .PIPERX0STATUS (delay_PIPERX0STATUS), + .PIPERX0SYNCHEADER (delay_PIPERX0SYNCHEADER), + .PIPERX0VALID (delay_PIPERX0VALID), + .PIPERX1CHARISK (delay_PIPERX1CHARISK), + .PIPERX1DATA (delay_PIPERX1DATA), + .PIPERX1DATAVALID (delay_PIPERX1DATAVALID), + .PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE), + .PIPERX1EQDONE (delay_PIPERX1EQDONE), + .PIPERX1EQLPADAPTDONE (delay_PIPERX1EQLPADAPTDONE), + .PIPERX1EQLPLFFSSEL (delay_PIPERX1EQLPLFFSSEL), + .PIPERX1EQLPNEWTXCOEFFORPRESET (delay_PIPERX1EQLPNEWTXCOEFFORPRESET), + .PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS), + .PIPERX1STARTBLOCK (delay_PIPERX1STARTBLOCK), + .PIPERX1STATUS (delay_PIPERX1STATUS), + .PIPERX1SYNCHEADER (delay_PIPERX1SYNCHEADER), + .PIPERX1VALID (delay_PIPERX1VALID), + .PIPERX2CHARISK (delay_PIPERX2CHARISK), + .PIPERX2DATA (delay_PIPERX2DATA), + .PIPERX2DATAVALID (delay_PIPERX2DATAVALID), + .PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE), + .PIPERX2EQDONE (delay_PIPERX2EQDONE), + .PIPERX2EQLPADAPTDONE (delay_PIPERX2EQLPADAPTDONE), + .PIPERX2EQLPLFFSSEL (delay_PIPERX2EQLPLFFSSEL), + .PIPERX2EQLPNEWTXCOEFFORPRESET (delay_PIPERX2EQLPNEWTXCOEFFORPRESET), + .PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS), + .PIPERX2STARTBLOCK (delay_PIPERX2STARTBLOCK), + .PIPERX2STATUS (delay_PIPERX2STATUS), + .PIPERX2SYNCHEADER (delay_PIPERX2SYNCHEADER), + .PIPERX2VALID (delay_PIPERX2VALID), + .PIPERX3CHARISK (delay_PIPERX3CHARISK), + .PIPERX3DATA (delay_PIPERX3DATA), + .PIPERX3DATAVALID (delay_PIPERX3DATAVALID), + .PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE), + .PIPERX3EQDONE (delay_PIPERX3EQDONE), + .PIPERX3EQLPADAPTDONE (delay_PIPERX3EQLPADAPTDONE), + .PIPERX3EQLPLFFSSEL (delay_PIPERX3EQLPLFFSSEL), + .PIPERX3EQLPNEWTXCOEFFORPRESET (delay_PIPERX3EQLPNEWTXCOEFFORPRESET), + .PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS), + .PIPERX3STARTBLOCK (delay_PIPERX3STARTBLOCK), + .PIPERX3STATUS (delay_PIPERX3STATUS), + .PIPERX3SYNCHEADER (delay_PIPERX3SYNCHEADER), + .PIPERX3VALID (delay_PIPERX3VALID), + .PIPERX4CHARISK (delay_PIPERX4CHARISK), + .PIPERX4DATA (delay_PIPERX4DATA), + .PIPERX4DATAVALID (delay_PIPERX4DATAVALID), + .PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE), + .PIPERX4EQDONE (delay_PIPERX4EQDONE), + .PIPERX4EQLPADAPTDONE (delay_PIPERX4EQLPADAPTDONE), + .PIPERX4EQLPLFFSSEL (delay_PIPERX4EQLPLFFSSEL), + .PIPERX4EQLPNEWTXCOEFFORPRESET (delay_PIPERX4EQLPNEWTXCOEFFORPRESET), + .PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS), + .PIPERX4STARTBLOCK (delay_PIPERX4STARTBLOCK), + .PIPERX4STATUS (delay_PIPERX4STATUS), + .PIPERX4SYNCHEADER (delay_PIPERX4SYNCHEADER), + .PIPERX4VALID (delay_PIPERX4VALID), + .PIPERX5CHARISK (delay_PIPERX5CHARISK), + .PIPERX5DATA (delay_PIPERX5DATA), + .PIPERX5DATAVALID (delay_PIPERX5DATAVALID), + .PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE), + .PIPERX5EQDONE (delay_PIPERX5EQDONE), + .PIPERX5EQLPADAPTDONE (delay_PIPERX5EQLPADAPTDONE), + .PIPERX5EQLPLFFSSEL (delay_PIPERX5EQLPLFFSSEL), + .PIPERX5EQLPNEWTXCOEFFORPRESET (delay_PIPERX5EQLPNEWTXCOEFFORPRESET), + .PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS), + .PIPERX5STARTBLOCK (delay_PIPERX5STARTBLOCK), + .PIPERX5STATUS (delay_PIPERX5STATUS), + .PIPERX5SYNCHEADER (delay_PIPERX5SYNCHEADER), + .PIPERX5VALID (delay_PIPERX5VALID), + .PIPERX6CHARISK (delay_PIPERX6CHARISK), + .PIPERX6DATA (delay_PIPERX6DATA), + .PIPERX6DATAVALID (delay_PIPERX6DATAVALID), + .PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE), + .PIPERX6EQDONE (delay_PIPERX6EQDONE), + .PIPERX6EQLPADAPTDONE (delay_PIPERX6EQLPADAPTDONE), + .PIPERX6EQLPLFFSSEL (delay_PIPERX6EQLPLFFSSEL), + .PIPERX6EQLPNEWTXCOEFFORPRESET (delay_PIPERX6EQLPNEWTXCOEFFORPRESET), + .PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS), + .PIPERX6STARTBLOCK (delay_PIPERX6STARTBLOCK), + .PIPERX6STATUS (delay_PIPERX6STATUS), + .PIPERX6SYNCHEADER (delay_PIPERX6SYNCHEADER), + .PIPERX6VALID (delay_PIPERX6VALID), + .PIPERX7CHARISK (delay_PIPERX7CHARISK), + .PIPERX7DATA (delay_PIPERX7DATA), + .PIPERX7DATAVALID (delay_PIPERX7DATAVALID), + .PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE), + .PIPERX7EQDONE (delay_PIPERX7EQDONE), + .PIPERX7EQLPADAPTDONE (delay_PIPERX7EQLPADAPTDONE), + .PIPERX7EQLPLFFSSEL (delay_PIPERX7EQLPLFFSSEL), + .PIPERX7EQLPNEWTXCOEFFORPRESET (delay_PIPERX7EQLPNEWTXCOEFFORPRESET), + .PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS), + .PIPERX7STARTBLOCK (delay_PIPERX7STARTBLOCK), + .PIPERX7STATUS (delay_PIPERX7STATUS), + .PIPERX7SYNCHEADER (delay_PIPERX7SYNCHEADER), + .PIPERX7VALID (delay_PIPERX7VALID), + .PIPETX0EQCOEFF (delay_PIPETX0EQCOEFF), + .PIPETX0EQDONE (delay_PIPETX0EQDONE), + .PIPETX1EQCOEFF (delay_PIPETX1EQCOEFF), + .PIPETX1EQDONE (delay_PIPETX1EQDONE), + .PIPETX2EQCOEFF (delay_PIPETX2EQCOEFF), + .PIPETX2EQDONE (delay_PIPETX2EQDONE), + .PIPETX3EQCOEFF (delay_PIPETX3EQCOEFF), + .PIPETX3EQDONE (delay_PIPETX3EQDONE), + .PIPETX4EQCOEFF (delay_PIPETX4EQCOEFF), + .PIPETX4EQDONE (delay_PIPETX4EQDONE), + .PIPETX5EQCOEFF (delay_PIPETX5EQCOEFF), + .PIPETX5EQDONE (delay_PIPETX5EQDONE), + .PIPETX6EQCOEFF (delay_PIPETX6EQCOEFF), + .PIPETX6EQDONE (delay_PIPETX6EQDONE), + .PIPETX7EQCOEFF (delay_PIPETX7EQCOEFF), + .PIPETX7EQDONE (delay_PIPETX7EQDONE), + .PLDISABLESCRAMBLER (delay_PLDISABLESCRAMBLER), + .PLEQRESETEIEOSCOUNT (delay_PLEQRESETEIEOSCOUNT), + .PLGEN3PCSDISABLE (delay_PLGEN3PCSDISABLE), + .PLGEN3PCSRXSYNCDONE (delay_PLGEN3PCSRXSYNCDONE), + .RECCLK (delay_RECCLK), + .RESETN (delay_RESETN), + .SAXISCCTDATA (delay_SAXISCCTDATA), + .SAXISCCTKEEP (delay_SAXISCCTKEEP), + .SAXISCCTLAST (delay_SAXISCCTLAST), + .SAXISCCTUSER (delay_SAXISCCTUSER), + .SAXISCCTVALID (delay_SAXISCCTVALID), + .SAXISRQTDATA (delay_SAXISRQTDATA), + .SAXISRQTKEEP (delay_SAXISRQTKEEP), + .SAXISRQTLAST (delay_SAXISRQTLAST), + .SAXISRQTUSER (delay_SAXISRQTUSER), + .SAXISRQTVALID (delay_SAXISRQTVALID), + .USERCLK (delay_USERCLK) + ); + + specify +`ifdef XIL_TIMING // Simprim + $period (posedge CORECLK, 0:0:0, notifier); + $period (posedge CORECLKMICOMPLETIONRAML, 0:0:0, notifier); + $period (posedge CORECLKMICOMPLETIONRAMU, 0:0:0, notifier); + $period (posedge CORECLKMIREPLAYRAM, 0:0:0, notifier); + $period (posedge CORECLKMIREQUESTRAM, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge PIPECLK, 0:0:0, notifier); + $period (posedge RECCLK, 0:0:0, notifier); + $period (posedge USERCLK, 0:0:0, notifier); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE); + $setuphold (posedge PIPECLK, negedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER); + $setuphold (posedge PIPECLK, negedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT); + $setuphold (posedge PIPECLK, negedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE); + $setuphold (posedge PIPECLK, posedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER); + $setuphold (posedge PIPECLK, posedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT); + $setuphold (posedge PIPECLK, posedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE); + $setuphold (posedge RECCLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID); + $setuphold (posedge RECCLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID); + $setuphold (posedge RECCLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID); + $setuphold (posedge RECCLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID); + $setuphold (posedge RECCLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID); + $setuphold (posedge RECCLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID); + $setuphold (posedge RECCLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID); + $setuphold (posedge RECCLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]); + $setuphold (posedge RECCLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]); + $setuphold (posedge RECCLK, negedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]); + $setuphold (posedge RECCLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]); + $setuphold (posedge RECCLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE); + $setuphold (posedge RECCLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS); + $setuphold (posedge RECCLK, negedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK); + $setuphold (posedge RECCLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]); + $setuphold (posedge RECCLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]); + $setuphold (posedge RECCLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]); + $setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]); + $setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]); + $setuphold (posedge RECCLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]); + $setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]); + $setuphold (posedge RECCLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID); + $setuphold (posedge RECCLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID); + $setuphold (posedge RECCLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID); + $setuphold (posedge RECCLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID); + $setuphold (posedge RECCLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID); + $setuphold (posedge RECCLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID); + $setuphold (posedge RECCLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID); + $setuphold (posedge RECCLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]); + $setuphold (posedge RECCLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]); + $setuphold (posedge RECCLK, posedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]); + $setuphold (posedge RECCLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]); + $setuphold (posedge RECCLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE); + $setuphold (posedge RECCLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS); + $setuphold (posedge RECCLK, posedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK); + $setuphold (posedge RECCLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]); + $setuphold (posedge RECCLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]); + $setuphold (posedge RECCLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]); + $setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]); + $setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]); + $setuphold (posedge RECCLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]); + $setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]); + $setuphold (posedge USERCLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE); + $setuphold (posedge USERCLK, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]); + $setuphold (posedge USERCLK, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]); + $setuphold (posedge USERCLK, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]); + $setuphold (posedge USERCLK, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]); + $setuphold (posedge USERCLK, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]); + $setuphold (posedge USERCLK, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]); + $setuphold (posedge USERCLK, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]); + $setuphold (posedge USERCLK, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]); + $setuphold (posedge USERCLK, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]); + $setuphold (posedge USERCLK, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]); + $setuphold (posedge USERCLK, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]); + $setuphold (posedge USERCLK, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]); + $setuphold (posedge USERCLK, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]); + $setuphold (posedge USERCLK, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]); + $setuphold (posedge USERCLK, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]); + $setuphold (posedge USERCLK, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]); + $setuphold (posedge USERCLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]); + $setuphold (posedge USERCLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]); + $setuphold (posedge USERCLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]); + $setuphold (posedge USERCLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]); + $setuphold (posedge USERCLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]); + $setuphold (posedge USERCLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]); + $setuphold (posedge USERCLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]); + $setuphold (posedge USERCLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]); + $setuphold (posedge USERCLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]); + $setuphold (posedge USERCLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]); + $setuphold (posedge USERCLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]); + $setuphold (posedge USERCLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]); + $setuphold (posedge USERCLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]); + $setuphold (posedge USERCLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]); + $setuphold (posedge USERCLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]); + $setuphold (posedge USERCLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]); + $setuphold (posedge USERCLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]); + $setuphold (posedge USERCLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]); + $setuphold (posedge USERCLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]); + $setuphold (posedge USERCLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]); + $setuphold (posedge USERCLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]); + $setuphold (posedge USERCLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]); + $setuphold (posedge USERCLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]); + $setuphold (posedge USERCLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]); + $setuphold (posedge USERCLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]); + $setuphold (posedge USERCLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]); + $setuphold (posedge USERCLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]); + $setuphold (posedge USERCLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]); + $setuphold (posedge USERCLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]); + $setuphold (posedge USERCLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]); + $setuphold (posedge USERCLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]); + $setuphold (posedge USERCLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]); + $setuphold (posedge USERCLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]); + $setuphold (posedge USERCLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]); + $setuphold (posedge USERCLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]); + $setuphold (posedge USERCLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]); + $setuphold (posedge USERCLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]); + $setuphold (posedge USERCLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]); + $setuphold (posedge USERCLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]); + $setuphold (posedge USERCLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]); + $setuphold (posedge USERCLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]); + $setuphold (posedge USERCLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]); + $setuphold (posedge USERCLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]); + $setuphold (posedge USERCLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]); + $setuphold (posedge USERCLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]); + $setuphold (posedge USERCLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]); + $setuphold (posedge USERCLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]); + $setuphold (posedge USERCLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]); + $setuphold (posedge USERCLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]); + $setuphold (posedge USERCLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]); + $setuphold (posedge USERCLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]); + $setuphold (posedge USERCLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]); + $setuphold (posedge USERCLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]); + $setuphold (posedge USERCLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]); + $setuphold (posedge USERCLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]); + $setuphold (posedge USERCLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]); + $setuphold (posedge USERCLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]); + $setuphold (posedge USERCLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]); + $setuphold (posedge USERCLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]); + $setuphold (posedge USERCLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]); + $setuphold (posedge USERCLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]); + $setuphold (posedge USERCLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]); + $setuphold (posedge USERCLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]); + $setuphold (posedge USERCLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN); + $setuphold (posedge USERCLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]); + $setuphold (posedge USERCLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]); + $setuphold (posedge USERCLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]); + $setuphold (posedge USERCLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN); + $setuphold (posedge USERCLK, negedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]); + $setuphold (posedge USERCLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE); + $setuphold (posedge USERCLK, negedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD); + $setuphold (posedge USERCLK, negedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST); + $setuphold (posedge USERCLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK); + $setuphold (posedge USERCLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY); + $setuphold (posedge USERCLK, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]); + $setuphold (posedge USERCLK, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]); + $setuphold (posedge USERCLK, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]); + $setuphold (posedge USERCLK, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]); + $setuphold (posedge USERCLK, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]); + $setuphold (posedge USERCLK, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]); + $setuphold (posedge USERCLK, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]); + $setuphold (posedge USERCLK, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]); + $setuphold (posedge USERCLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]); + $setuphold (posedge USERCLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]); + $setuphold (posedge USERCLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]); + $setuphold (posedge USERCLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]); + $setuphold (posedge USERCLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]); + $setuphold (posedge USERCLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]); + $setuphold (posedge USERCLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]); + $setuphold (posedge USERCLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]); + $setuphold (posedge USERCLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]); + $setuphold (posedge USERCLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]); + $setuphold (posedge USERCLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]); + $setuphold (posedge USERCLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]); + $setuphold (posedge USERCLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]); + $setuphold (posedge USERCLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]); + $setuphold (posedge USERCLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]); + $setuphold (posedge USERCLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]); + $setuphold (posedge USERCLK, negedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]); + $setuphold (posedge USERCLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]); + $setuphold (posedge USERCLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID); + $setuphold (posedge USERCLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE); + $setuphold (posedge USERCLK, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]); + $setuphold (posedge USERCLK, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]); + $setuphold (posedge USERCLK, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]); + $setuphold (posedge USERCLK, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]); + $setuphold (posedge USERCLK, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]); + $setuphold (posedge USERCLK, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]); + $setuphold (posedge USERCLK, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]); + $setuphold (posedge USERCLK, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]); + $setuphold (posedge USERCLK, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]); + $setuphold (posedge USERCLK, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]); + $setuphold (posedge USERCLK, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]); + $setuphold (posedge USERCLK, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]); + $setuphold (posedge USERCLK, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]); + $setuphold (posedge USERCLK, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]); + $setuphold (posedge USERCLK, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]); + $setuphold (posedge USERCLK, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]); + $setuphold (posedge USERCLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]); + $setuphold (posedge USERCLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]); + $setuphold (posedge USERCLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]); + $setuphold (posedge USERCLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]); + $setuphold (posedge USERCLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]); + $setuphold (posedge USERCLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]); + $setuphold (posedge USERCLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]); + $setuphold (posedge USERCLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]); + $setuphold (posedge USERCLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]); + $setuphold (posedge USERCLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]); + $setuphold (posedge USERCLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]); + $setuphold (posedge USERCLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]); + $setuphold (posedge USERCLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]); + $setuphold (posedge USERCLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]); + $setuphold (posedge USERCLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]); + $setuphold (posedge USERCLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]); + $setuphold (posedge USERCLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]); + $setuphold (posedge USERCLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]); + $setuphold (posedge USERCLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]); + $setuphold (posedge USERCLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]); + $setuphold (posedge USERCLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]); + $setuphold (posedge USERCLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]); + $setuphold (posedge USERCLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]); + $setuphold (posedge USERCLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]); + $setuphold (posedge USERCLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]); + $setuphold (posedge USERCLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]); + $setuphold (posedge USERCLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]); + $setuphold (posedge USERCLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]); + $setuphold (posedge USERCLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]); + $setuphold (posedge USERCLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]); + $setuphold (posedge USERCLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]); + $setuphold (posedge USERCLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]); + $setuphold (posedge USERCLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]); + $setuphold (posedge USERCLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]); + $setuphold (posedge USERCLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]); + $setuphold (posedge USERCLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]); + $setuphold (posedge USERCLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]); + $setuphold (posedge USERCLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]); + $setuphold (posedge USERCLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]); + $setuphold (posedge USERCLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]); + $setuphold (posedge USERCLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]); + $setuphold (posedge USERCLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]); + $setuphold (posedge USERCLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]); + $setuphold (posedge USERCLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]); + $setuphold (posedge USERCLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]); + $setuphold (posedge USERCLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]); + $setuphold (posedge USERCLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]); + $setuphold (posedge USERCLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]); + $setuphold (posedge USERCLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]); + $setuphold (posedge USERCLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]); + $setuphold (posedge USERCLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]); + $setuphold (posedge USERCLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]); + $setuphold (posedge USERCLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]); + $setuphold (posedge USERCLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]); + $setuphold (posedge USERCLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]); + $setuphold (posedge USERCLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]); + $setuphold (posedge USERCLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]); + $setuphold (posedge USERCLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]); + $setuphold (posedge USERCLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]); + $setuphold (posedge USERCLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]); + $setuphold (posedge USERCLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]); + $setuphold (posedge USERCLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]); + $setuphold (posedge USERCLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]); + $setuphold (posedge USERCLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN); + $setuphold (posedge USERCLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]); + $setuphold (posedge USERCLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]); + $setuphold (posedge USERCLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]); + $setuphold (posedge USERCLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN); + $setuphold (posedge USERCLK, posedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]); + $setuphold (posedge USERCLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE); + $setuphold (posedge USERCLK, posedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD); + $setuphold (posedge USERCLK, posedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST); + $setuphold (posedge USERCLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK); + $setuphold (posedge USERCLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY); + $setuphold (posedge USERCLK, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]); + $setuphold (posedge USERCLK, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]); + $setuphold (posedge USERCLK, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]); + $setuphold (posedge USERCLK, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]); + $setuphold (posedge USERCLK, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]); + $setuphold (posedge USERCLK, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]); + $setuphold (posedge USERCLK, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]); + $setuphold (posedge USERCLK, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]); + $setuphold (posedge USERCLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]); + $setuphold (posedge USERCLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]); + $setuphold (posedge USERCLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]); + $setuphold (posedge USERCLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]); + $setuphold (posedge USERCLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]); + $setuphold (posedge USERCLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]); + $setuphold (posedge USERCLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]); + $setuphold (posedge USERCLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]); + $setuphold (posedge USERCLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]); + $setuphold (posedge USERCLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]); + $setuphold (posedge USERCLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]); + $setuphold (posedge USERCLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]); + $setuphold (posedge USERCLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]); + $setuphold (posedge USERCLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]); + $setuphold (posedge USERCLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]); + $setuphold (posedge USERCLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]); + $setuphold (posedge USERCLK, posedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]); + $setuphold (posedge USERCLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]); + $setuphold (posedge USERCLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID); +`endif + + ( CORECLK *> DBGDATAOUT[0]) = (0, 0); + ( CORECLK *> DBGDATAOUT[10]) = (0, 0); + ( CORECLK *> DBGDATAOUT[11]) = (0, 0); + ( CORECLK *> DBGDATAOUT[12]) = (0, 0); + ( CORECLK *> DBGDATAOUT[13]) = (0, 0); + ( CORECLK *> DBGDATAOUT[14]) = (0, 0); + ( CORECLK *> DBGDATAOUT[15]) = (0, 0); + ( CORECLK *> DBGDATAOUT[1]) = (0, 0); + ( CORECLK *> DBGDATAOUT[2]) = (0, 0); + ( CORECLK *> DBGDATAOUT[3]) = (0, 0); + ( CORECLK *> DBGDATAOUT[4]) = (0, 0); + ( CORECLK *> DBGDATAOUT[5]) = (0, 0); + ( CORECLK *> DBGDATAOUT[6]) = (0, 0); + ( CORECLK *> DBGDATAOUT[7]) = (0, 0); + ( CORECLK *> DBGDATAOUT[8]) = (0, 0); + ( CORECLK *> DBGDATAOUT[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[10]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[11]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[12]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[13]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[14]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[15]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[16]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[17]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[18]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[19]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[20]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[21]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[22]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[23]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[24]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[25]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[26]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[27]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[28]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[29]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[30]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[31]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[32]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[33]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[34]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[35]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[36]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[37]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[38]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[39]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[40]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[41]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[42]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[43]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[44]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[45]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[46]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[47]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[48]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[49]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[50]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[51]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[52]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[53]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[54]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[55]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[56]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[57]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[58]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[59]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[60]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[61]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[62]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[63]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[64]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[65]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[66]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[67]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[68]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[69]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[70]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[71]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[10]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[11]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[12]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[13]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[14]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[15]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[16]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[17]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[18]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[19]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[20]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[21]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[22]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[23]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[24]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[25]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[26]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[27]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[28]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[29]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[30]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[31]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[32]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[33]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[34]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[35]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[36]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[37]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[38]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[39]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[3]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[40]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[41]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[42]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[43]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[44]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[45]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[46]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[47]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[48]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[49]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[4]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[50]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[51]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[52]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[53]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[54]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[55]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[56]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[57]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[58]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[59]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[5]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[60]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[61]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[62]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[63]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[64]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[65]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[66]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[67]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[68]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[69]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[6]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[70]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[71]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[7]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[8]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[9]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[0]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[1]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[2]) = (0, 0); + ( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[3]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[0]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[1]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[2]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[3]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[4]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[5]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[6]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[7]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[8]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[0]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[1]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[0]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[100]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[101]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[102]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[103]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[104]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[105]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[106]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[107]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[108]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[109]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[10]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[110]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[111]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[112]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[113]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[114]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[115]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[116]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[117]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[118]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[119]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[11]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[120]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[121]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[122]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[123]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[124]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[125]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[126]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[127]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[128]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[129]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[12]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[130]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[131]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[132]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[133]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[134]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[135]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[136]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[137]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[138]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[139]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[13]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[140]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[141]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[142]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[143]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[14]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[15]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[16]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[17]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[18]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[19]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[1]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[20]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[21]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[22]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[23]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[24]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[25]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[26]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[27]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[28]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[29]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[2]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[30]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[31]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[32]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[33]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[34]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[35]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[36]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[37]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[38]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[39]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[3]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[40]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[41]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[42]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[43]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[44]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[45]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[46]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[47]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[48]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[49]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[4]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[50]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[51]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[52]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[53]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[54]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[55]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[56]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[57]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[58]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[59]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[5]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[60]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[61]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[62]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[63]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[64]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[65]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[66]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[67]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[68]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[69]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[6]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[70]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[71]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[72]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[73]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[74]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[75]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[76]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[77]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[78]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[79]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[7]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[80]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[81]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[82]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[83]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[84]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[85]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[86]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[87]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[88]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[89]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[8]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[90]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[91]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[92]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[93]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[94]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[95]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[96]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[97]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[98]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[99]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[9]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[0]) = (0, 0); + ( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[4]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[5]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[6]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[7]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[8]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[4]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[5]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[6]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[7]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[8]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[4]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[5]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[6]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[7]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[8]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[4]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[5]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[6]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[7]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[8]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[100]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[101]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[102]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[103]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[104]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[105]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[106]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[107]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[108]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[109]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[10]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[110]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[111]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[112]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[113]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[114]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[115]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[116]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[117]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[118]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[119]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[11]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[120]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[121]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[122]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[123]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[124]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[125]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[126]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[127]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[128]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[129]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[12]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[130]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[131]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[132]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[133]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[134]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[135]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[136]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[137]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[138]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[139]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[13]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[140]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[141]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[142]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[143]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[14]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[15]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[16]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[17]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[18]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[19]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[20]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[21]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[22]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[23]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[24]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[25]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[26]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[27]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[28]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[29]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[30]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[31]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[32]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[33]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[34]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[35]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[36]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[37]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[38]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[39]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[3]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[40]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[41]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[42]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[43]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[44]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[45]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[46]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[47]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[48]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[49]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[4]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[50]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[51]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[52]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[53]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[54]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[55]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[56]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[57]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[58]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[59]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[5]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[60]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[61]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[62]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[63]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[64]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[65]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[66]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[67]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[68]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[69]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[6]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[70]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[71]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[72]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[73]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[74]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[75]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[76]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[77]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[78]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[79]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[7]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[80]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[81]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[82]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[83]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[84]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[85]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[86]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[87]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[88]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[89]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[8]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[90]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[91]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[92]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[93]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[94]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[95]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[96]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[97]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[98]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[99]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[9]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[0]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[1]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[2]) = (0, 0); + ( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[3]) = (0, 0); + ( DRPCLK *> DRPDO[0]) = (0, 0); + ( DRPCLK *> DRPDO[10]) = (0, 0); + ( DRPCLK *> DRPDO[11]) = (0, 0); + ( DRPCLK *> DRPDO[12]) = (0, 0); + ( DRPCLK *> DRPDO[13]) = (0, 0); + ( DRPCLK *> DRPDO[14]) = (0, 0); + ( DRPCLK *> DRPDO[15]) = (0, 0); + ( DRPCLK *> DRPDO[1]) = (0, 0); + ( DRPCLK *> DRPDO[2]) = (0, 0); + ( DRPCLK *> DRPDO[3]) = (0, 0); + ( DRPCLK *> DRPDO[4]) = (0, 0); + ( DRPCLK *> DRPDO[5]) = (0, 0); + ( DRPCLK *> DRPDO[6]) = (0, 0); + ( DRPCLK *> DRPDO[7]) = (0, 0); + ( DRPCLK *> DRPDO[8]) = (0, 0); + ( DRPCLK *> DRPDO[9]) = (0, 0); + ( DRPCLK *> DRPRDY) = (0, 0); + ( PIPECLK *> PIPERX0EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX0EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX0EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX0EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX0EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX0EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX0POLARITY) = (0, 0); + ( PIPECLK *> PIPERX1EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX1EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX1EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX1EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX1EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX1EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX1POLARITY) = (0, 0); + ( PIPECLK *> PIPERX2EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX2EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX2EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX2EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX2EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX2EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX2POLARITY) = (0, 0); + ( PIPECLK *> PIPERX3EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX3EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX3EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX3EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX3EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX3EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX3POLARITY) = (0, 0); + ( PIPECLK *> PIPERX4EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX4EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX4EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX4EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX4EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX4EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX4POLARITY) = (0, 0); + ( PIPECLK *> PIPERX5EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX5EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX5EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX5EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX5EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX5EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX5POLARITY) = (0, 0); + ( PIPECLK *> PIPERX6EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX6EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX6EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX6EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX6EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX6EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX6POLARITY) = (0, 0); + ( PIPECLK *> PIPERX7EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPERX7EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[0]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[1]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[2]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[3]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[4]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPLFFS[5]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPTXPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPTXPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPTXPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX7EQLPTXPRESET[3]) = (0, 0); + ( PIPECLK *> PIPERX7EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPERX7EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPERX7EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPERX7POLARITY) = (0, 0); + ( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX0DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX0DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX0DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX0ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX0EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX0EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX0EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX0EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX0EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX0EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX0EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX0STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX0SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX0SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX1DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX1DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX1DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX1ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX1EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX1EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX1EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX1EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX1EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX1EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX1EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX1STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX1SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX1SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX2DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX2DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX2DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX2ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX2EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX2EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX2EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX2EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX2EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX2EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX2EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX2STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX2SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX2SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX3DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX3DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX3DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX3ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX3EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX3EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX3EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX3EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX3EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX3EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX3EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX3STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX3SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX3SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX4DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX4DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX4DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX4ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX4EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX4EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX4EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX4EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX4EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX4EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX4EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX4STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX4SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX4SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX5DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX5DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX5DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX5ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX5EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX5EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX5EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX5EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX5EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX5EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX5EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX5STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX5SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX5SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX6DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX6DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX6DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX6ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX6EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX6EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX6EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX6EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX6EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX6EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX6EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX6STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX6SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX6SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0); + ( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0); + ( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0); + ( PIPECLK *> PIPETX7DATAVALID) = (0, 0); + ( PIPECLK *> PIPETX7DATA[0]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[10]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[11]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[12]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[13]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[14]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[15]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[16]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[17]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[18]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[19]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[1]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[20]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[21]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[22]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[23]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[24]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[25]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[26]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[27]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[28]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[29]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[2]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[30]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[31]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[3]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[4]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[5]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[6]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[7]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[8]) = (0, 0); + ( PIPECLK *> PIPETX7DATA[9]) = (0, 0); + ( PIPECLK *> PIPETX7ELECIDLE) = (0, 0); + ( PIPECLK *> PIPETX7EQCONTROL[0]) = (0, 0); + ( PIPECLK *> PIPETX7EQCONTROL[1]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[0]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[1]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[2]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[3]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[4]) = (0, 0); + ( PIPECLK *> PIPETX7EQDEEMPH[5]) = (0, 0); + ( PIPECLK *> PIPETX7EQPRESET[0]) = (0, 0); + ( PIPECLK *> PIPETX7EQPRESET[1]) = (0, 0); + ( PIPECLK *> PIPETX7EQPRESET[2]) = (0, 0); + ( PIPECLK *> PIPETX7EQPRESET[3]) = (0, 0); + ( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0); + ( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0); + ( PIPECLK *> PIPETX7STARTBLOCK) = (0, 0); + ( PIPECLK *> PIPETX7SYNCHEADER[0]) = (0, 0); + ( PIPECLK *> PIPETX7SYNCHEADER[1]) = (0, 0); + ( PIPECLK *> PIPETXDEEMPH) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[0]) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[1]) = (0, 0); + ( PIPECLK *> PIPETXMARGIN[2]) = (0, 0); + ( PIPECLK *> PIPETXRATE[0]) = (0, 0); + ( PIPECLK *> PIPETXRATE[1]) = (0, 0); + ( PIPECLK *> PIPETXRCVRDET) = (0, 0); + ( PIPECLK *> PIPETXRESET) = (0, 0); + ( PIPECLK *> PIPETXSWING) = (0, 0); + ( PIPECLK *> PLEQINPROGRESS) = (0, 0); + ( PIPECLK *> PLEQPHASE[0]) = (0, 0); + ( PIPECLK *> PLEQPHASE[1]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[0]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[1]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[2]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[3]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[4]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[5]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[6]) = (0, 0); + ( RECCLK *> PLGEN3PCSRXSLIDE[7]) = (0, 0); + ( USERCLK *> CFGCURRENTSPEED[0]) = (0, 0); + ( USERCLK *> CFGCURRENTSPEED[1]) = (0, 0); + ( USERCLK *> CFGCURRENTSPEED[2]) = (0, 0); + ( USERCLK *> CFGDPASUBSTATECHANGE[0]) = (0, 0); + ( USERCLK *> CFGDPASUBSTATECHANGE[1]) = (0, 0); + ( USERCLK *> CFGERRCOROUT) = (0, 0); + ( USERCLK *> CFGERRFATALOUT) = (0, 0); + ( USERCLK *> CFGERRNONFATALOUT) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[0]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[1]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[2]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[3]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[4]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[5]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[6]) = (0, 0); + ( USERCLK *> CFGEXTFUNCTIONNUMBER[7]) = (0, 0); + ( USERCLK *> CFGEXTREADRECEIVED) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[0]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[1]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[2]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[3]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[4]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[5]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[6]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[7]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[8]) = (0, 0); + ( USERCLK *> CFGEXTREGISTERNUMBER[9]) = (0, 0); + ( USERCLK *> CFGEXTWRITEBYTEENABLE[0]) = (0, 0); + ( USERCLK *> CFGEXTWRITEBYTEENABLE[1]) = (0, 0); + ( USERCLK *> CFGEXTWRITEBYTEENABLE[2]) = (0, 0); + ( USERCLK *> CFGEXTWRITEBYTEENABLE[3]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[0]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[10]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[11]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[12]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[13]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[14]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[15]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[16]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[17]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[18]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[19]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[1]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[20]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[21]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[22]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[23]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[24]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[25]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[26]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[27]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[28]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[29]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[2]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[30]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[31]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[3]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[4]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[5]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[6]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[7]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[8]) = (0, 0); + ( USERCLK *> CFGEXTWRITEDATA[9]) = (0, 0); + ( USERCLK *> CFGEXTWRITERECEIVED) = (0, 0); + ( USERCLK *> CFGFCCPLD[0]) = (0, 0); + ( USERCLK *> CFGFCCPLD[10]) = (0, 0); + ( USERCLK *> CFGFCCPLD[11]) = (0, 0); + ( USERCLK *> CFGFCCPLD[1]) = (0, 0); + ( USERCLK *> CFGFCCPLD[2]) = (0, 0); + ( USERCLK *> CFGFCCPLD[3]) = (0, 0); + ( USERCLK *> CFGFCCPLD[4]) = (0, 0); + ( USERCLK *> CFGFCCPLD[5]) = (0, 0); + ( USERCLK *> CFGFCCPLD[6]) = (0, 0); + ( USERCLK *> CFGFCCPLD[7]) = (0, 0); + ( USERCLK *> CFGFCCPLD[8]) = (0, 0); + ( USERCLK *> CFGFCCPLD[9]) = (0, 0); + ( USERCLK *> CFGFCCPLH[0]) = (0, 0); + ( USERCLK *> CFGFCCPLH[1]) = (0, 0); + ( USERCLK *> CFGFCCPLH[2]) = (0, 0); + ( USERCLK *> CFGFCCPLH[3]) = (0, 0); + ( USERCLK *> CFGFCCPLH[4]) = (0, 0); + ( USERCLK *> CFGFCCPLH[5]) = (0, 0); + ( USERCLK *> CFGFCCPLH[6]) = (0, 0); + ( USERCLK *> CFGFCCPLH[7]) = (0, 0); + ( USERCLK *> CFGFCNPD[0]) = (0, 0); + ( USERCLK *> CFGFCNPD[10]) = (0, 0); + ( USERCLK *> CFGFCNPD[11]) = (0, 0); + ( USERCLK *> CFGFCNPD[1]) = (0, 0); + ( USERCLK *> CFGFCNPD[2]) = (0, 0); + ( USERCLK *> CFGFCNPD[3]) = (0, 0); + ( USERCLK *> CFGFCNPD[4]) = (0, 0); + ( USERCLK *> CFGFCNPD[5]) = (0, 0); + ( USERCLK *> CFGFCNPD[6]) = (0, 0); + ( USERCLK *> CFGFCNPD[7]) = (0, 0); + ( USERCLK *> CFGFCNPD[8]) = (0, 0); + ( USERCLK *> CFGFCNPD[9]) = (0, 0); + ( USERCLK *> CFGFCNPH[0]) = (0, 0); + ( USERCLK *> CFGFCNPH[1]) = (0, 0); + ( USERCLK *> CFGFCNPH[2]) = (0, 0); + ( USERCLK *> CFGFCNPH[3]) = (0, 0); + ( USERCLK *> CFGFCNPH[4]) = (0, 0); + ( USERCLK *> CFGFCNPH[5]) = (0, 0); + ( USERCLK *> CFGFCNPH[6]) = (0, 0); + ( USERCLK *> CFGFCNPH[7]) = (0, 0); + ( USERCLK *> CFGFCPD[0]) = (0, 0); + ( USERCLK *> CFGFCPD[10]) = (0, 0); + ( USERCLK *> CFGFCPD[11]) = (0, 0); + ( USERCLK *> CFGFCPD[1]) = (0, 0); + ( USERCLK *> CFGFCPD[2]) = (0, 0); + ( USERCLK *> CFGFCPD[3]) = (0, 0); + ( USERCLK *> CFGFCPD[4]) = (0, 0); + ( USERCLK *> CFGFCPD[5]) = (0, 0); + ( USERCLK *> CFGFCPD[6]) = (0, 0); + ( USERCLK *> CFGFCPD[7]) = (0, 0); + ( USERCLK *> CFGFCPD[8]) = (0, 0); + ( USERCLK *> CFGFCPD[9]) = (0, 0); + ( USERCLK *> CFGFCPH[0]) = (0, 0); + ( USERCLK *> CFGFCPH[1]) = (0, 0); + ( USERCLK *> CFGFCPH[2]) = (0, 0); + ( USERCLK *> CFGFCPH[3]) = (0, 0); + ( USERCLK *> CFGFCPH[4]) = (0, 0); + ( USERCLK *> CFGFCPH[5]) = (0, 0); + ( USERCLK *> CFGFCPH[6]) = (0, 0); + ( USERCLK *> CFGFCPH[7]) = (0, 0); + ( USERCLK *> CFGFLRINPROCESS[0]) = (0, 0); + ( USERCLK *> CFGFLRINPROCESS[1]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[0]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[1]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[2]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[3]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[4]) = (0, 0); + ( USERCLK *> CFGFUNCTIONPOWERSTATE[5]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[0]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[1]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[2]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[3]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[4]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[5]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[6]) = (0, 0); + ( USERCLK *> CFGFUNCTIONSTATUS[7]) = (0, 0); + ( USERCLK *> CFGHOTRESETOUT) = (0, 0); + ( USERCLK *> CFGINPUTUPDATEDONE) = (0, 0); + ( USERCLK *> CFGINTERRUPTAOUTPUT) = (0, 0); + ( USERCLK *> CFGINTERRUPTBOUTPUT) = (0, 0); + ( USERCLK *> CFGINTERRUPTCOUTPUT) = (0, 0); + ( USERCLK *> CFGINTERRUPTDOUTPUT) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[10]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[11]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[12]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[13]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[14]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[15]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[16]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[17]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[18]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[19]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[20]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[21]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[22]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[23]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[24]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[25]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[26]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[27]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[28]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[29]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[2]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[30]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[31]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[3]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[4]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[5]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[6]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[7]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[8]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIDATA[9]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIENABLE[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIENABLE[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIFAIL) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMASKUPDATE) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[2]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[3]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[4]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIMMENABLE[5]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSISENT) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[2]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[3]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[4]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIVFENABLE[5]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXENABLE[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXENABLE[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXFAIL) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXMASK[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXMASK[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXSENT) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[2]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[3]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[4]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFENABLE[5]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[0]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[1]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[2]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[3]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[4]) = (0, 0); + ( USERCLK *> CFGINTERRUPTMSIXVFMASK[5]) = (0, 0); + ( USERCLK *> CFGINTERRUPTSENT) = (0, 0); + ( USERCLK *> CFGLINKPOWERSTATE[0]) = (0, 0); + ( USERCLK *> CFGLINKPOWERSTATE[1]) = (0, 0); + ( USERCLK *> CFGLOCALERROR) = (0, 0); + ( USERCLK *> CFGLTRENABLE) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[0]) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[1]) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[2]) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[3]) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[4]) = (0, 0); + ( USERCLK *> CFGLTSSMSTATE[5]) = (0, 0); + ( USERCLK *> CFGMAXPAYLOAD[0]) = (0, 0); + ( USERCLK *> CFGMAXPAYLOAD[1]) = (0, 0); + ( USERCLK *> CFGMAXPAYLOAD[2]) = (0, 0); + ( USERCLK *> CFGMAXREADREQ[0]) = (0, 0); + ( USERCLK *> CFGMAXREADREQ[1]) = (0, 0); + ( USERCLK *> CFGMAXREADREQ[2]) = (0, 0); + ( USERCLK *> CFGMCUPDATEDONE) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[0]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[10]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[11]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[12]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[13]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[14]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[15]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[16]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[17]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[18]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[19]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[1]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[20]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[21]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[22]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[23]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[24]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[25]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[26]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[27]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[28]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[29]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[2]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[30]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[31]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[3]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[4]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[5]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[6]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[7]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[8]) = (0, 0); + ( USERCLK *> CFGMGMTREADDATA[9]) = (0, 0); + ( USERCLK *> CFGMGMTREADWRITEDONE) = (0, 0); + ( USERCLK *> CFGMSGRECEIVED) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[0]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[1]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[2]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[3]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[4]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[5]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[6]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDDATA[7]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDTYPE[0]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDTYPE[1]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDTYPE[2]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDTYPE[3]) = (0, 0); + ( USERCLK *> CFGMSGRECEIVEDTYPE[4]) = (0, 0); + ( USERCLK *> CFGMSGTRANSMITDONE) = (0, 0); + ( USERCLK *> CFGNEGOTIATEDWIDTH[0]) = (0, 0); + ( USERCLK *> CFGNEGOTIATEDWIDTH[1]) = (0, 0); + ( USERCLK *> CFGNEGOTIATEDWIDTH[2]) = (0, 0); + ( USERCLK *> CFGNEGOTIATEDWIDTH[3]) = (0, 0); + ( USERCLK *> CFGOBFFENABLE[0]) = (0, 0); + ( USERCLK *> CFGOBFFENABLE[1]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[0]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[10]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[11]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[12]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[13]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[14]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[15]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[1]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[2]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[3]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[4]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[5]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[6]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[7]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[8]) = (0, 0); + ( USERCLK *> CFGPERFUNCSTATUSDATA[9]) = (0, 0); + ( USERCLK *> CFGPERFUNCTIONUPDATEDONE) = (0, 0); + ( USERCLK *> CFGPHYLINKDOWN) = (0, 0); + ( USERCLK *> CFGPHYLINKSTATUS[0]) = (0, 0); + ( USERCLK *> CFGPHYLINKSTATUS[1]) = (0, 0); + ( USERCLK *> CFGPLSTATUSCHANGE) = (0, 0); + ( USERCLK *> CFGPOWERSTATECHANGEINTERRUPT) = (0, 0); + ( USERCLK *> CFGRCBSTATUS[0]) = (0, 0); + ( USERCLK *> CFGRCBSTATUS[1]) = (0, 0); + ( USERCLK *> CFGTPHFUNCTIONNUM[0]) = (0, 0); + ( USERCLK *> CFGTPHFUNCTIONNUM[1]) = (0, 0); + ( USERCLK *> CFGTPHFUNCTIONNUM[2]) = (0, 0); + ( USERCLK *> CFGTPHREQUESTERENABLE[0]) = (0, 0); + ( USERCLK *> CFGTPHREQUESTERENABLE[1]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[0]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[1]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[2]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[3]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[4]) = (0, 0); + ( USERCLK *> CFGTPHSTMODE[5]) = (0, 0); + ( USERCLK *> CFGTPHSTTADDRESS[0]) = (0, 0); + ( USERCLK *> CFGTPHSTTADDRESS[1]) = (0, 0); + ( USERCLK *> CFGTPHSTTADDRESS[2]) = (0, 0); + ( USERCLK *> CFGTPHSTTADDRESS[3]) = (0, 0); + ( USERCLK *> CFGTPHSTTADDRESS[4]) = (0, 0); + ( USERCLK *> CFGTPHSTTREADENABLE) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEBYTEVALID[0]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEBYTEVALID[1]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEBYTEVALID[2]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEBYTEVALID[3]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[0]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[10]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[11]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[12]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[13]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[14]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[15]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[16]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[17]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[18]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[19]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[1]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[20]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[21]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[22]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[23]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[24]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[25]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[26]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[27]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[28]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[29]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[2]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[30]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[31]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[3]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[4]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[5]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[6]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[7]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[8]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEDATA[9]) = (0, 0); + ( USERCLK *> CFGTPHSTTWRITEENABLE) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[0]) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[1]) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[2]) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[3]) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[4]) = (0, 0); + ( USERCLK *> CFGVFFLRINPROCESS[5]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[0]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[10]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[11]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[12]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[13]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[14]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[15]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[16]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[17]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[1]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[2]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[3]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[4]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[5]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[6]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[7]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[8]) = (0, 0); + ( USERCLK *> CFGVFPOWERSTATE[9]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[0]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[10]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[11]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[1]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[2]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[3]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[4]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[5]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[6]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[7]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[8]) = (0, 0); + ( USERCLK *> CFGVFSTATUS[9]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[0]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[1]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[2]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[3]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[4]) = (0, 0); + ( USERCLK *> CFGVFTPHREQUESTERENABLE[5]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[0]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[10]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[11]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[12]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[13]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[14]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[15]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[16]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[17]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[1]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[2]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[3]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[4]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[5]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[6]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[7]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[8]) = (0, 0); + ( USERCLK *> CFGVFTPHSTMODE[9]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[0]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[100]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[101]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[102]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[103]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[104]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[105]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[106]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[107]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[108]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[109]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[10]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[110]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[111]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[112]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[113]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[114]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[115]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[116]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[117]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[118]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[119]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[11]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[120]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[121]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[122]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[123]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[124]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[125]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[126]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[127]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[128]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[129]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[12]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[130]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[131]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[132]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[133]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[134]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[135]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[136]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[137]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[138]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[139]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[13]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[140]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[141]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[142]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[143]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[144]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[145]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[146]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[147]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[148]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[149]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[14]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[150]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[151]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[152]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[153]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[154]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[155]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[156]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[157]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[158]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[159]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[15]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[160]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[161]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[162]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[163]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[164]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[165]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[166]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[167]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[168]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[169]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[16]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[170]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[171]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[172]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[173]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[174]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[175]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[176]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[177]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[178]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[179]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[17]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[180]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[181]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[182]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[183]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[184]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[185]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[186]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[187]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[188]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[189]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[18]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[190]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[191]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[192]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[193]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[194]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[195]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[196]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[197]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[198]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[199]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[19]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[1]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[200]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[201]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[202]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[203]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[204]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[205]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[206]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[207]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[208]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[209]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[20]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[210]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[211]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[212]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[213]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[214]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[215]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[216]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[217]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[218]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[219]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[21]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[220]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[221]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[222]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[223]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[224]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[225]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[226]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[227]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[228]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[229]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[22]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[230]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[231]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[232]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[233]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[234]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[235]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[236]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[237]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[238]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[239]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[23]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[240]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[241]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[242]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[243]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[244]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[245]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[246]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[247]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[248]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[249]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[24]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[250]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[251]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[252]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[253]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[254]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[255]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[25]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[26]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[27]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[28]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[29]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[2]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[30]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[31]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[32]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[33]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[34]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[35]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[36]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[37]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[38]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[39]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[3]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[40]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[41]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[42]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[43]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[44]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[45]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[46]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[47]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[48]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[49]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[4]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[50]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[51]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[52]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[53]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[54]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[55]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[56]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[57]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[58]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[59]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[5]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[60]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[61]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[62]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[63]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[64]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[65]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[66]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[67]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[68]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[69]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[6]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[70]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[71]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[72]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[73]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[74]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[75]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[76]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[77]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[78]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[79]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[7]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[80]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[81]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[82]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[83]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[84]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[85]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[86]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[87]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[88]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[89]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[8]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[90]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[91]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[92]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[93]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[94]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[95]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[96]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[97]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[98]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[99]) = (0, 0); + ( USERCLK *> MAXISCQTDATA[9]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[0]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[1]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[2]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[3]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[4]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[5]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[6]) = (0, 0); + ( USERCLK *> MAXISCQTKEEP[7]) = (0, 0); + ( USERCLK *> MAXISCQTLAST) = (0, 0); + ( USERCLK *> MAXISCQTUSER[0]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[10]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[11]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[12]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[13]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[14]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[15]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[16]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[17]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[18]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[19]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[1]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[20]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[21]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[22]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[23]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[24]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[25]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[26]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[27]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[28]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[29]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[2]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[30]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[31]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[32]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[33]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[34]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[35]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[36]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[37]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[38]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[39]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[3]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[40]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[41]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[42]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[43]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[44]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[45]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[46]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[47]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[48]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[49]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[4]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[50]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[51]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[52]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[53]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[54]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[55]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[56]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[57]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[58]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[59]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[5]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[60]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[61]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[62]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[63]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[64]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[65]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[66]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[67]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[68]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[69]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[6]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[70]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[71]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[72]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[73]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[74]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[75]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[76]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[77]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[78]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[79]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[7]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[80]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[81]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[82]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[83]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[84]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[8]) = (0, 0); + ( USERCLK *> MAXISCQTUSER[9]) = (0, 0); + ( USERCLK *> MAXISCQTVALID) = (0, 0); + ( USERCLK *> MAXISRCTDATA[0]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[100]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[101]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[102]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[103]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[104]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[105]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[106]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[107]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[108]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[109]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[10]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[110]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[111]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[112]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[113]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[114]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[115]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[116]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[117]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[118]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[119]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[11]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[120]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[121]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[122]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[123]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[124]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[125]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[126]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[127]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[128]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[129]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[12]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[130]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[131]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[132]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[133]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[134]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[135]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[136]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[137]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[138]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[139]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[13]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[140]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[141]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[142]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[143]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[144]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[145]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[146]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[147]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[148]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[149]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[14]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[150]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[151]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[152]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[153]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[154]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[155]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[156]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[157]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[158]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[159]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[15]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[160]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[161]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[162]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[163]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[164]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[165]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[166]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[167]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[168]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[169]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[16]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[170]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[171]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[172]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[173]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[174]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[175]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[176]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[177]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[178]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[179]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[17]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[180]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[181]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[182]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[183]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[184]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[185]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[186]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[187]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[188]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[189]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[18]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[190]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[191]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[192]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[193]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[194]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[195]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[196]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[197]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[198]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[199]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[19]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[1]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[200]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[201]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[202]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[203]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[204]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[205]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[206]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[207]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[208]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[209]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[20]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[210]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[211]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[212]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[213]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[214]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[215]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[216]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[217]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[218]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[219]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[21]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[220]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[221]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[222]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[223]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[224]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[225]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[226]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[227]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[228]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[229]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[22]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[230]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[231]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[232]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[233]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[234]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[235]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[236]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[237]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[238]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[239]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[23]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[240]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[241]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[242]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[243]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[244]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[245]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[246]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[247]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[248]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[249]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[24]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[250]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[251]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[252]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[253]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[254]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[255]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[25]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[26]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[27]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[28]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[29]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[2]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[30]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[31]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[32]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[33]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[34]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[35]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[36]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[37]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[38]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[39]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[3]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[40]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[41]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[42]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[43]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[44]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[45]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[46]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[47]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[48]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[49]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[4]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[50]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[51]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[52]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[53]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[54]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[55]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[56]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[57]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[58]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[59]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[5]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[60]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[61]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[62]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[63]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[64]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[65]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[66]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[67]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[68]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[69]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[6]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[70]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[71]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[72]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[73]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[74]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[75]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[76]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[77]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[78]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[79]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[7]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[80]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[81]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[82]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[83]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[84]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[85]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[86]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[87]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[88]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[89]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[8]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[90]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[91]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[92]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[93]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[94]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[95]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[96]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[97]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[98]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[99]) = (0, 0); + ( USERCLK *> MAXISRCTDATA[9]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[0]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[1]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[2]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[3]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[4]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[5]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[6]) = (0, 0); + ( USERCLK *> MAXISRCTKEEP[7]) = (0, 0); + ( USERCLK *> MAXISRCTLAST) = (0, 0); + ( USERCLK *> MAXISRCTUSER[0]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[10]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[11]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[12]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[13]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[14]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[15]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[16]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[17]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[18]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[19]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[1]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[20]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[21]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[22]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[23]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[24]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[25]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[26]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[27]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[28]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[29]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[2]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[30]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[31]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[32]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[33]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[34]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[35]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[36]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[37]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[38]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[39]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[3]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[40]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[41]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[42]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[43]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[44]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[45]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[46]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[47]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[48]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[49]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[4]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[50]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[51]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[52]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[53]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[54]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[55]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[56]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[57]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[58]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[59]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[5]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[60]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[61]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[62]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[63]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[64]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[65]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[66]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[67]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[68]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[69]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[6]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[70]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[71]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[72]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[73]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[74]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[7]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[8]) = (0, 0); + ( USERCLK *> MAXISRCTUSER[9]) = (0, 0); + ( USERCLK *> MAXISRCTVALID) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[0]) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[1]) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[2]) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[3]) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[4]) = (0, 0); + ( USERCLK *> PCIECQNPREQCOUNT[5]) = (0, 0); + ( USERCLK *> PCIERQSEQNUMVLD) = (0, 0); + ( USERCLK *> PCIERQSEQNUM[0]) = (0, 0); + ( USERCLK *> PCIERQSEQNUM[1]) = (0, 0); + ( USERCLK *> PCIERQSEQNUM[2]) = (0, 0); + ( USERCLK *> PCIERQSEQNUM[3]) = (0, 0); + ( USERCLK *> PCIERQTAGAV[0]) = (0, 0); + ( USERCLK *> PCIERQTAGAV[1]) = (0, 0); + ( USERCLK *> PCIERQTAGVLD) = (0, 0); + ( USERCLK *> PCIERQTAG[0]) = (0, 0); + ( USERCLK *> PCIERQTAG[1]) = (0, 0); + ( USERCLK *> PCIERQTAG[2]) = (0, 0); + ( USERCLK *> PCIERQTAG[3]) = (0, 0); + ( USERCLK *> PCIERQTAG[4]) = (0, 0); + ( USERCLK *> PCIERQTAG[5]) = (0, 0); + ( USERCLK *> PCIETFCNPDAV[0]) = (0, 0); + ( USERCLK *> PCIETFCNPDAV[1]) = (0, 0); + ( USERCLK *> PCIETFCNPHAV[0]) = (0, 0); + ( USERCLK *> PCIETFCNPHAV[1]) = (0, 0); + ( USERCLK *> SAXISCCTREADY[0]) = (0, 0); + ( USERCLK *> SAXISCCTREADY[1]) = (0, 0); + ( USERCLK *> SAXISCCTREADY[2]) = (0, 0); + ( USERCLK *> SAXISCCTREADY[3]) = (0, 0); + ( USERCLK *> SAXISRQTREADY[0]) = (0, 0); + ( USERCLK *> SAXISRQTREADY[1]) = (0, 0); + ( USERCLK *> SAXISRQTREADY[2]) = (0, 0); + ( USERCLK *> SAXISRQTREADY[3]) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PCIE_3_1.v b/verilog/src/unisims/PCIE_3_1.v new file mode 100644 index 0000000..4ffb528 --- /dev/null +++ b/verilog/src/unisims/PCIE_3_1.v @@ -0,0 +1,17038 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2011 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2012.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / +// /___/ /\ Filename : PCIE_3_1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine +module PCIE_3_1 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter ARI_CAP_ENABLE = "FALSE", + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE", + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE", + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE", + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE", + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000, + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE", + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE", + parameter AXISTEN_IF_RC_STRADDLE = "FALSE", + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE", + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE", + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2, + parameter CRM_CORE_CLK_FREQ_500 = "TRUE", + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2, + parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE", + parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE", + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE", + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + parameter [8:0] LL_ACK_TIMEOUT = 9'h000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000, + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE", + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000, + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE", + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000, + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE", + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000, + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE", + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0, + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA, + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE", + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE", + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000, + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE", + parameter MCAP_ENABLE = "FALSE", + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE", + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000, + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE", + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE", + parameter [15:0] MCAP_VSEC_ID = 16'h0000, + parameter [11:0] MCAP_VSEC_LEN = 12'h02C, + parameter [3:0] MCAP_VSEC_REV = 4'h0, + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [3:0] PF0_ARI_CAP_VER = 4'h1, + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF0_BAR0_CONTROL = 3'h4, + parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00, + parameter [2:0] PF0_BAR1_CONTROL = 3'h0, + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR3_CONTROL = 3'h0, + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_BAR5_CONTROL = 3'h0, + parameter [7:0] PF0_BIST_REGISTER = 8'h00, + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50, + parameter [23:0] PF0_CLASS_CODE = 24'h000000, + parameter [15:0] PF0_DEVICE_ID = 16'h0000, + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE", + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE", + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE", + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE", + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0, + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE", + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0, + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE", + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000, + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00, + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE", + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00, + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00, + parameter [3:0] PF0_DPA_CAP_VER = 4'h1, + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE", + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00, + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1, + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7, + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000, + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000, + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_LTR_CAP_VER = 4'h1, + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00, + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000, + parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000, + parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000, + parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000, + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000, + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE", + parameter [3:0] PF0_PB_CAP_VER = 4'h1, + parameter [7:0] PF0_PM_CAP_ID = 8'h01, + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00, + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE", + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE", + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE", + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3, + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE", + parameter PF0_RBAR_CAP_ENABLE = "FALSE", + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000, + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000, + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000, + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000, + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1, + parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0, + parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0, + parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0, + parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00, + parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00, + parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00, + parameter [2:0] PF0_RBAR_NUM = 3'h1, + parameter [7:0] PF0_REVISION_ID = 8'h00, + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000, + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0, + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0, + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000, + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF0_TPHR_CAP_ENABLE = "FALSE", + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1, + parameter PF0_VC_CAP_ENABLE = "FALSE", + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000, + parameter [3:0] PF0_VC_CAP_VER = 4'h1, + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF1_BAR0_CONTROL = 3'h4, + parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00, + parameter [2:0] PF1_BAR1_CONTROL = 3'h0, + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR3_CONTROL = 3'h0, + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_BAR5_CONTROL = 3'h0, + parameter [7:0] PF1_BIST_REGISTER = 8'h00, + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50, + parameter [23:0] PF1_CLASS_CODE = 24'h000000, + parameter [15:0] PF1_DEVICE_ID = 16'h0000, + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000, + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00, + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE", + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00, + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00, + parameter [3:0] PF1_DPA_CAP_VER = 4'h1, + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE", + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00, + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00, + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000, + parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000, + parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000, + parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000, + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000, + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE", + parameter [3:0] PF1_PB_CAP_VER = 4'h1, + parameter [7:0] PF1_PM_CAP_ID = 8'h01, + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3, + parameter PF1_RBAR_CAP_ENABLE = "FALSE", + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000, + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000, + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000, + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000, + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1, + parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0, + parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0, + parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0, + parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00, + parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00, + parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00, + parameter [2:0] PF1_RBAR_NUM = 3'h1, + parameter [7:0] PF1_REVISION_ID = 8'h00, + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0, + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0, + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000, + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF1_TPHR_CAP_ENABLE = "FALSE", + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1, + parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF2_BAR0_CONTROL = 3'h4, + parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00, + parameter [2:0] PF2_BAR1_CONTROL = 3'h0, + parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR3_CONTROL = 3'h0, + parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_BAR5_CONTROL = 3'h0, + parameter [7:0] PF2_BIST_REGISTER = 8'h00, + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50, + parameter [23:0] PF2_CLASS_CODE = 24'h000000, + parameter [15:0] PF2_DEVICE_ID = 16'h0000, + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000, + parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00, + parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE", + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00, + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00, + parameter [3:0] PF2_DPA_CAP_VER = 4'h1, + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE", + parameter [7:0] PF2_INTERRUPT_LINE = 8'h00, + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00, + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000, + parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000, + parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000, + parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000, + parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000, + parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE", + parameter [3:0] PF2_PB_CAP_VER = 4'h1, + parameter [7:0] PF2_PM_CAP_ID = 8'h01, + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3, + parameter PF2_RBAR_CAP_ENABLE = "FALSE", + parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000, + parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000, + parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000, + parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000, + parameter [3:0] PF2_RBAR_CAP_VER = 4'h1, + parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0, + parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0, + parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0, + parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00, + parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00, + parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00, + parameter [2:0] PF2_RBAR_NUM = 3'h1, + parameter [7:0] PF2_REVISION_ID = 8'h00, + parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0, + parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0, + parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000, + parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF2_TPHR_CAP_ENABLE = "FALSE", + parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF2_TPHR_CAP_VER = 4'h1, + parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000, + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00, + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03, + parameter [2:0] PF3_BAR0_CONTROL = 3'h4, + parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00, + parameter [2:0] PF3_BAR1_CONTROL = 3'h0, + parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR3_CONTROL = 3'h0, + parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_BAR5_CONTROL = 3'h0, + parameter [7:0] PF3_BIST_REGISTER = 8'h00, + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50, + parameter [23:0] PF3_CLASS_CODE = 24'h000000, + parameter [15:0] PF3_DEVICE_ID = 16'h0000, + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3, + parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000, + parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00, + parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE", + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00, + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00, + parameter [3:0] PF3_DPA_CAP_VER = 4'h1, + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C, + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03, + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE", + parameter [7:0] PF3_INTERRUPT_LINE = 8'h00, + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1, + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00, + parameter integer PF3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00, + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE", + parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000, + parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000, + parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000, + parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000, + parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000, + parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE", + parameter [3:0] PF3_PB_CAP_VER = 4'h1, + parameter [7:0] PF3_PM_CAP_ID = 8'h01, + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3, + parameter PF3_RBAR_CAP_ENABLE = "FALSE", + parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000, + parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000, + parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000, + parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000, + parameter [3:0] PF3_RBAR_CAP_VER = 4'h1, + parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0, + parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0, + parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0, + parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00, + parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00, + parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00, + parameter [2:0] PF3_RBAR_NUM = 3'h1, + parameter [7:0] PF3_REVISION_ID = 8'h00, + parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00, + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0, + parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0, + parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4, + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03, + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0, + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000, + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000, + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000, + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1, + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000, + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000, + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000, + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000, + parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000, + parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter PF3_TPHR_CAP_ENABLE = "FALSE", + parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] PF3_TPHR_CAP_VER = 4'h1, + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE", + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE", + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE", + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE", + parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE", + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE", + parameter PL_DISABLE_SCRAMBLING = "FALSE", + parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE", + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE", + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE", + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE", + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02, + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1, + parameter PL_EQ_BYPASS_PHASE23 = "FALSE", + parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3, + parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4, + parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE", + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE", + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00, + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00, + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8, + parameter integer PL_N_FTS_COMCLK_GEN1 = 255, + parameter integer PL_N_FTS_COMCLK_GEN2 = 255, + parameter integer PL_N_FTS_COMCLK_GEN3 = 255, + parameter integer PL_N_FTS_GEN1 = 255, + parameter integer PL_N_FTS_GEN2 = 255, + parameter integer PL_N_FTS_GEN3 = 255, + parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE", + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE", + parameter PL_UPSTREAM_FACING = "TRUE", + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC, + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000, + parameter PM_ENABLE_L23_ENTRY = "FALSE", + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE", + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000, + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0, + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064, + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000, + parameter SIM_VERSION = "1.0", + parameter integer SPARE_BIT0 = 0, + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter integer SPARE_BIT3 = 0, + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + parameter SRIOV_CAP_ENABLE = "FALSE", + parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE", + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20, + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080, + parameter [11:0] TL_CREDITS_CD = 12'h3E0, + parameter [7:0] TL_CREDITS_CH = 8'h20, + parameter [11:0] TL_CREDITS_NPD = 12'h028, + parameter [7:0] TL_CREDITS_NPH = 8'h20, + parameter [11:0] TL_CREDITS_PD = 12'h198, + parameter [7:0] TL_CREDITS_PH = 8'h20, + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE", + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE", + parameter TL_LEGACY_MODE_ENABLE = "FALSE", + parameter [1:0] TL_PF_ENABLE_REG = 2'h0, + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE", + parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE", + parameter TWO_LAYER_MODE_ENABLE = "FALSE", + parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE", + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000, + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50, + parameter integer VF0_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF0_PM_CAP_ID = 8'h01, + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3, + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF0_TPHR_CAP_ENABLE = "FALSE", + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF1_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF1_PM_CAP_ID = 8'h01, + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3, + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF1_TPHR_CAP_ENABLE = "FALSE", + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF2_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF2_PM_CAP_ID = 8'h01, + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3, + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF2_TPHR_CAP_ENABLE = "FALSE", + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF3_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF3_PM_CAP_ID = 8'h01, + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3, + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF3_TPHR_CAP_ENABLE = "FALSE", + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF4_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF4_PM_CAP_ID = 8'h01, + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3, + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF4_TPHR_CAP_ENABLE = "FALSE", + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF5_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF5_PM_CAP_ID = 8'h01, + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3, + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF5_TPHR_CAP_ENABLE = "FALSE", + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF6_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF6_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF6_PM_CAP_ID = 8'h01, + parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3, + parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF6_TPHR_CAP_ENABLE = "FALSE", + parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF6_TPHR_CAP_VER = 4'h1, + parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000, + parameter integer VF7_MSIX_CAP_PBA_BIR = 0, + parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer VF7_MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000, + parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0, + parameter [7:0] VF7_PM_CAP_ID = 8'h01, + parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00, + parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3, + parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE", + parameter VF7_TPHR_CAP_ENABLE = "FALSE", + parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE", + parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000, + parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0, + parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0, + parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000, + parameter [3:0] VF7_TPHR_CAP_VER = 4'h1 +)( + output [2:0] CFGCURRENTSPEED, + output [3:0] CFGDPASUBSTATECHANGE, + output CFGERRCOROUT, + output CFGERRFATALOUT, + output CFGERRNONFATALOUT, + output [7:0] CFGEXTFUNCTIONNUMBER, + output CFGEXTREADRECEIVED, + output [9:0] CFGEXTREGISTERNUMBER, + output [3:0] CFGEXTWRITEBYTEENABLE, + output [31:0] CFGEXTWRITEDATA, + output CFGEXTWRITERECEIVED, + output [11:0] CFGFCCPLD, + output [7:0] CFGFCCPLH, + output [11:0] CFGFCNPD, + output [7:0] CFGFCNPH, + output [11:0] CFGFCPD, + output [7:0] CFGFCPH, + output [3:0] CFGFLRINPROCESS, + output [11:0] CFGFUNCTIONPOWERSTATE, + output [15:0] CFGFUNCTIONSTATUS, + output CFGHOTRESETOUT, + output [31:0] CFGINTERRUPTMSIDATA, + output [3:0] CFGINTERRUPTMSIENABLE, + output CFGINTERRUPTMSIFAIL, + output CFGINTERRUPTMSIMASKUPDATE, + output [11:0] CFGINTERRUPTMSIMMENABLE, + output CFGINTERRUPTMSISENT, + output [7:0] CFGINTERRUPTMSIVFENABLE, + output [3:0] CFGINTERRUPTMSIXENABLE, + output CFGINTERRUPTMSIXFAIL, + output [3:0] CFGINTERRUPTMSIXMASK, + output CFGINTERRUPTMSIXSENT, + output [7:0] CFGINTERRUPTMSIXVFENABLE, + output [7:0] CFGINTERRUPTMSIXVFMASK, + output CFGINTERRUPTSENT, + output [1:0] CFGLINKPOWERSTATE, + output CFGLOCALERROR, + output CFGLTRENABLE, + output [5:0] CFGLTSSMSTATE, + output [2:0] CFGMAXPAYLOAD, + output [2:0] CFGMAXREADREQ, + output [31:0] CFGMGMTREADDATA, + output CFGMGMTREADWRITEDONE, + output CFGMSGRECEIVED, + output [7:0] CFGMSGRECEIVEDDATA, + output [4:0] CFGMSGRECEIVEDTYPE, + output CFGMSGTRANSMITDONE, + output [3:0] CFGNEGOTIATEDWIDTH, + output [1:0] CFGOBFFENABLE, + output [15:0] CFGPERFUNCSTATUSDATA, + output CFGPERFUNCTIONUPDATEDONE, + output CFGPHYLINKDOWN, + output [1:0] CFGPHYLINKSTATUS, + output CFGPLSTATUSCHANGE, + output CFGPOWERSTATECHANGEINTERRUPT, + output [3:0] CFGRCBSTATUS, + output [3:0] CFGTPHFUNCTIONNUM, + output [3:0] CFGTPHREQUESTERENABLE, + output [11:0] CFGTPHSTMODE, + output [4:0] CFGTPHSTTADDRESS, + output CFGTPHSTTREADENABLE, + output [3:0] CFGTPHSTTWRITEBYTEVALID, + output [31:0] CFGTPHSTTWRITEDATA, + output CFGTPHSTTWRITEENABLE, + output [7:0] CFGVFFLRINPROCESS, + output [23:0] CFGVFPOWERSTATE, + output [15:0] CFGVFSTATUS, + output [7:0] CFGVFTPHREQUESTERENABLE, + output [23:0] CFGVFTPHSTMODE, + output CONFMCAPDESIGNSWITCH, + output CONFMCAPEOS, + output CONFMCAPINUSEBYPCIE, + output CONFREQREADY, + output [31:0] CONFRESPRDATA, + output CONFRESPVALID, + output [15:0] DBGDATAOUT, + output DBGMCAPCSB, + output [31:0] DBGMCAPDATA, + output DBGMCAPEOS, + output DBGMCAPERROR, + output DBGMCAPMODE, + output DBGMCAPRDATAVALID, + output DBGMCAPRDWRB, + output DBGMCAPRESET, + output DBGPLDATABLOCKRECEIVEDAFTEREDS, + output DBGPLGEN3FRAMINGERRORDETECTED, + output DBGPLGEN3SYNCHEADERERRORDETECTED, + output [7:0] DBGPLINFERREDRXELECTRICALIDLE, + output [15:0] DRPDO, + output DRPRDY, + output LL2LMMASTERTLPSENT0, + output LL2LMMASTERTLPSENT1, + output [3:0] LL2LMMASTERTLPSENTTLPID0, + output [3:0] LL2LMMASTERTLPSENTTLPID1, + output [255:0] LL2LMMAXISRXTDATA, + output [17:0] LL2LMMAXISRXTUSER, + output [7:0] LL2LMMAXISRXTVALID, + output [7:0] LL2LMSAXISTXTREADY, + output [255:0] MAXISCQTDATA, + output [7:0] MAXISCQTKEEP, + output MAXISCQTLAST, + output [84:0] MAXISCQTUSER, + output MAXISCQTVALID, + output [255:0] MAXISRCTDATA, + output [7:0] MAXISRCTKEEP, + output MAXISRCTLAST, + output [74:0] MAXISRCTUSER, + output MAXISRCTVALID, + output [9:0] MICOMPLETIONRAMREADADDRESSAL, + output [9:0] MICOMPLETIONRAMREADADDRESSAU, + output [9:0] MICOMPLETIONRAMREADADDRESSBL, + output [9:0] MICOMPLETIONRAMREADADDRESSBU, + output [3:0] MICOMPLETIONRAMREADENABLEL, + output [3:0] MICOMPLETIONRAMREADENABLEU, + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL, + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU, + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL, + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU, + output [71:0] MICOMPLETIONRAMWRITEDATAL, + output [71:0] MICOMPLETIONRAMWRITEDATAU, + output [3:0] MICOMPLETIONRAMWRITEENABLEL, + output [3:0] MICOMPLETIONRAMWRITEENABLEU, + output [8:0] MIREPLAYRAMADDRESS, + output [1:0] MIREPLAYRAMREADENABLE, + output [143:0] MIREPLAYRAMWRITEDATA, + output [1:0] MIREPLAYRAMWRITEENABLE, + output [8:0] MIREQUESTRAMREADADDRESSA, + output [8:0] MIREQUESTRAMREADADDRESSB, + output [3:0] MIREQUESTRAMREADENABLE, + output [8:0] MIREQUESTRAMWRITEADDRESSA, + output [8:0] MIREQUESTRAMWRITEADDRESSB, + output [143:0] MIREQUESTRAMWRITEDATA, + output [3:0] MIREQUESTRAMWRITEENABLE, + output [5:0] PCIECQNPREQCOUNT, + output PCIEPERST0B, + output PCIEPERST1B, + output [3:0] PCIERQSEQNUM, + output PCIERQSEQNUMVLD, + output [5:0] PCIERQTAG, + output [1:0] PCIERQTAGAV, + output PCIERQTAGVLD, + output [1:0] PCIETFCNPDAV, + output [1:0] PCIETFCNPHAV, + output [1:0] PIPERX0EQCONTROL, + output [5:0] PIPERX0EQLPLFFS, + output [3:0] PIPERX0EQLPTXPRESET, + output [2:0] PIPERX0EQPRESET, + output PIPERX0POLARITY, + output [1:0] PIPERX1EQCONTROL, + output [5:0] PIPERX1EQLPLFFS, + output [3:0] PIPERX1EQLPTXPRESET, + output [2:0] PIPERX1EQPRESET, + output PIPERX1POLARITY, + output [1:0] PIPERX2EQCONTROL, + output [5:0] PIPERX2EQLPLFFS, + output [3:0] PIPERX2EQLPTXPRESET, + output [2:0] PIPERX2EQPRESET, + output PIPERX2POLARITY, + output [1:0] PIPERX3EQCONTROL, + output [5:0] PIPERX3EQLPLFFS, + output [3:0] PIPERX3EQLPTXPRESET, + output [2:0] PIPERX3EQPRESET, + output PIPERX3POLARITY, + output [1:0] PIPERX4EQCONTROL, + output [5:0] PIPERX4EQLPLFFS, + output [3:0] PIPERX4EQLPTXPRESET, + output [2:0] PIPERX4EQPRESET, + output PIPERX4POLARITY, + output [1:0] PIPERX5EQCONTROL, + output [5:0] PIPERX5EQLPLFFS, + output [3:0] PIPERX5EQLPTXPRESET, + output [2:0] PIPERX5EQPRESET, + output PIPERX5POLARITY, + output [1:0] PIPERX6EQCONTROL, + output [5:0] PIPERX6EQLPLFFS, + output [3:0] PIPERX6EQLPTXPRESET, + output [2:0] PIPERX6EQPRESET, + output PIPERX6POLARITY, + output [1:0] PIPERX7EQCONTROL, + output [5:0] PIPERX7EQLPLFFS, + output [3:0] PIPERX7EQLPTXPRESET, + output [2:0] PIPERX7EQPRESET, + output PIPERX7POLARITY, + output [1:0] PIPETX0CHARISK, + output PIPETX0COMPLIANCE, + output [31:0] PIPETX0DATA, + output PIPETX0DATAVALID, + output PIPETX0DEEMPH, + output PIPETX0ELECIDLE, + output [1:0] PIPETX0EQCONTROL, + output [5:0] PIPETX0EQDEEMPH, + output [3:0] PIPETX0EQPRESET, + output [2:0] PIPETX0MARGIN, + output [1:0] PIPETX0POWERDOWN, + output [1:0] PIPETX0RATE, + output PIPETX0RCVRDET, + output PIPETX0RESET, + output PIPETX0STARTBLOCK, + output PIPETX0SWING, + output [1:0] PIPETX0SYNCHEADER, + output [1:0] PIPETX1CHARISK, + output PIPETX1COMPLIANCE, + output [31:0] PIPETX1DATA, + output PIPETX1DATAVALID, + output PIPETX1DEEMPH, + output PIPETX1ELECIDLE, + output [1:0] PIPETX1EQCONTROL, + output [5:0] PIPETX1EQDEEMPH, + output [3:0] PIPETX1EQPRESET, + output [2:0] PIPETX1MARGIN, + output [1:0] PIPETX1POWERDOWN, + output [1:0] PIPETX1RATE, + output PIPETX1RCVRDET, + output PIPETX1RESET, + output PIPETX1STARTBLOCK, + output PIPETX1SWING, + output [1:0] PIPETX1SYNCHEADER, + output [1:0] PIPETX2CHARISK, + output PIPETX2COMPLIANCE, + output [31:0] PIPETX2DATA, + output PIPETX2DATAVALID, + output PIPETX2DEEMPH, + output PIPETX2ELECIDLE, + output [1:0] PIPETX2EQCONTROL, + output [5:0] PIPETX2EQDEEMPH, + output [3:0] PIPETX2EQPRESET, + output [2:0] PIPETX2MARGIN, + output [1:0] PIPETX2POWERDOWN, + output [1:0] PIPETX2RATE, + output PIPETX2RCVRDET, + output PIPETX2RESET, + output PIPETX2STARTBLOCK, + output PIPETX2SWING, + output [1:0] PIPETX2SYNCHEADER, + output [1:0] PIPETX3CHARISK, + output PIPETX3COMPLIANCE, + output [31:0] PIPETX3DATA, + output PIPETX3DATAVALID, + output PIPETX3DEEMPH, + output PIPETX3ELECIDLE, + output [1:0] PIPETX3EQCONTROL, + output [5:0] PIPETX3EQDEEMPH, + output [3:0] PIPETX3EQPRESET, + output [2:0] PIPETX3MARGIN, + output [1:0] PIPETX3POWERDOWN, + output [1:0] PIPETX3RATE, + output PIPETX3RCVRDET, + output PIPETX3RESET, + output PIPETX3STARTBLOCK, + output PIPETX3SWING, + output [1:0] PIPETX3SYNCHEADER, + output [1:0] PIPETX4CHARISK, + output PIPETX4COMPLIANCE, + output [31:0] PIPETX4DATA, + output PIPETX4DATAVALID, + output PIPETX4DEEMPH, + output PIPETX4ELECIDLE, + output [1:0] PIPETX4EQCONTROL, + output [5:0] PIPETX4EQDEEMPH, + output [3:0] PIPETX4EQPRESET, + output [2:0] PIPETX4MARGIN, + output [1:0] PIPETX4POWERDOWN, + output [1:0] PIPETX4RATE, + output PIPETX4RCVRDET, + output PIPETX4RESET, + output PIPETX4STARTBLOCK, + output PIPETX4SWING, + output [1:0] PIPETX4SYNCHEADER, + output [1:0] PIPETX5CHARISK, + output PIPETX5COMPLIANCE, + output [31:0] PIPETX5DATA, + output PIPETX5DATAVALID, + output PIPETX5DEEMPH, + output PIPETX5ELECIDLE, + output [1:0] PIPETX5EQCONTROL, + output [5:0] PIPETX5EQDEEMPH, + output [3:0] PIPETX5EQPRESET, + output [2:0] PIPETX5MARGIN, + output [1:0] PIPETX5POWERDOWN, + output [1:0] PIPETX5RATE, + output PIPETX5RCVRDET, + output PIPETX5RESET, + output PIPETX5STARTBLOCK, + output PIPETX5SWING, + output [1:0] PIPETX5SYNCHEADER, + output [1:0] PIPETX6CHARISK, + output PIPETX6COMPLIANCE, + output [31:0] PIPETX6DATA, + output PIPETX6DATAVALID, + output PIPETX6DEEMPH, + output PIPETX6ELECIDLE, + output [1:0] PIPETX6EQCONTROL, + output [5:0] PIPETX6EQDEEMPH, + output [3:0] PIPETX6EQPRESET, + output [2:0] PIPETX6MARGIN, + output [1:0] PIPETX6POWERDOWN, + output [1:0] PIPETX6RATE, + output PIPETX6RCVRDET, + output PIPETX6RESET, + output PIPETX6STARTBLOCK, + output PIPETX6SWING, + output [1:0] PIPETX6SYNCHEADER, + output [1:0] PIPETX7CHARISK, + output PIPETX7COMPLIANCE, + output [31:0] PIPETX7DATA, + output PIPETX7DATAVALID, + output PIPETX7DEEMPH, + output PIPETX7ELECIDLE, + output [1:0] PIPETX7EQCONTROL, + output [5:0] PIPETX7EQDEEMPH, + output [3:0] PIPETX7EQPRESET, + output [2:0] PIPETX7MARGIN, + output [1:0] PIPETX7POWERDOWN, + output [1:0] PIPETX7RATE, + output PIPETX7RCVRDET, + output PIPETX7RESET, + output PIPETX7STARTBLOCK, + output PIPETX7SWING, + output [1:0] PIPETX7SYNCHEADER, + output PLEQINPROGRESS, + output [1:0] PLEQPHASE, + output [3:0] SAXISCCTREADY, + output [3:0] SAXISRQTREADY, + output [31:0] SPAREOUT, + + input CFGCONFIGSPACEENABLE, + input [15:0] CFGDEVID, + input [7:0] CFGDSBUSNUMBER, + input [4:0] CFGDSDEVICENUMBER, + input [2:0] CFGDSFUNCTIONNUMBER, + input [63:0] CFGDSN, + input [7:0] CFGDSPORTNUMBER, + input CFGERRCORIN, + input CFGERRUNCORIN, + input [31:0] CFGEXTREADDATA, + input CFGEXTREADDATAVALID, + input [2:0] CFGFCSEL, + input [3:0] CFGFLRDONE, + input CFGHOTRESETIN, + input [3:0] CFGINTERRUPTINT, + input [2:0] CFGINTERRUPTMSIATTR, + input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER, + input [31:0] CFGINTERRUPTMSIINT, + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS, + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, + input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, + input [3:0] CFGINTERRUPTMSISELECT, + input CFGINTERRUPTMSITPHPRESENT, + input [8:0] CFGINTERRUPTMSITPHSTTAG, + input [1:0] CFGINTERRUPTMSITPHTYPE, + input [63:0] CFGINTERRUPTMSIXADDRESS, + input [31:0] CFGINTERRUPTMSIXDATA, + input CFGINTERRUPTMSIXINT, + input [3:0] CFGINTERRUPTPENDING, + input CFGLINKTRAININGENABLE, + input [18:0] CFGMGMTADDR, + input [3:0] CFGMGMTBYTEENABLE, + input CFGMGMTREAD, + input CFGMGMTTYPE1CFGREGACCESS, + input CFGMGMTWRITE, + input [31:0] CFGMGMTWRITEDATA, + input CFGMSGTRANSMIT, + input [31:0] CFGMSGTRANSMITDATA, + input [2:0] CFGMSGTRANSMITTYPE, + input [2:0] CFGPERFUNCSTATUSCONTROL, + input [3:0] CFGPERFUNCTIONNUMBER, + input CFGPERFUNCTIONOUTPUTREQUEST, + input CFGPOWERSTATECHANGEACK, + input CFGREQPMTRANSITIONL23READY, + input [7:0] CFGREVID, + input [15:0] CFGSUBSYSID, + input [15:0] CFGSUBSYSVENDID, + input [31:0] CFGTPHSTTREADDATA, + input CFGTPHSTTREADDATAVALID, + input [15:0] CFGVENDID, + input [7:0] CFGVFFLRDONE, + input CONFMCAPREQUESTBYCONF, + input [31:0] CONFREQDATA, + input [3:0] CONFREQREGNUM, + input [1:0] CONFREQTYPE, + input CONFREQVALID, + input CORECLK, + input CORECLKMICOMPLETIONRAML, + input CORECLKMICOMPLETIONRAMU, + input CORECLKMIREPLAYRAM, + input CORECLKMIREQUESTRAM, + input DBGCFGLOCALMGMTREGOVERRIDE, + input [3:0] DBGDATASEL, + input [9:0] DRPADDR, + input DRPCLK, + input [15:0] DRPDI, + input DRPEN, + input DRPWE, + input [13:0] LL2LMSAXISTXTUSER, + input LL2LMSAXISTXTVALID, + input [3:0] LL2LMTXTLPID0, + input [3:0] LL2LMTXTLPID1, + input [21:0] MAXISCQTREADY, + input [21:0] MAXISRCTREADY, + input MCAPCLK, + input MCAPPERST0B, + input MCAPPERST1B, + input MGMTRESETN, + input MGMTSTICKYRESETN, + input [143:0] MICOMPLETIONRAMREADDATA, + input [143:0] MIREPLAYRAMREADDATA, + input [143:0] MIREQUESTRAMREADDATA, + input PCIECQNPREQ, + input PIPECLK, + input [5:0] PIPEEQFS, + input [5:0] PIPEEQLF, + input PIPERESETN, + input [1:0] PIPERX0CHARISK, + input [31:0] PIPERX0DATA, + input PIPERX0DATAVALID, + input PIPERX0ELECIDLE, + input PIPERX0EQDONE, + input PIPERX0EQLPADAPTDONE, + input PIPERX0EQLPLFFSSEL, + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET, + input PIPERX0PHYSTATUS, + input PIPERX0STARTBLOCK, + input [2:0] PIPERX0STATUS, + input [1:0] PIPERX0SYNCHEADER, + input PIPERX0VALID, + input [1:0] PIPERX1CHARISK, + input [31:0] PIPERX1DATA, + input PIPERX1DATAVALID, + input PIPERX1ELECIDLE, + input PIPERX1EQDONE, + input PIPERX1EQLPADAPTDONE, + input PIPERX1EQLPLFFSSEL, + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET, + input PIPERX1PHYSTATUS, + input PIPERX1STARTBLOCK, + input [2:0] PIPERX1STATUS, + input [1:0] PIPERX1SYNCHEADER, + input PIPERX1VALID, + input [1:0] PIPERX2CHARISK, + input [31:0] PIPERX2DATA, + input PIPERX2DATAVALID, + input PIPERX2ELECIDLE, + input PIPERX2EQDONE, + input PIPERX2EQLPADAPTDONE, + input PIPERX2EQLPLFFSSEL, + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET, + input PIPERX2PHYSTATUS, + input PIPERX2STARTBLOCK, + input [2:0] PIPERX2STATUS, + input [1:0] PIPERX2SYNCHEADER, + input PIPERX2VALID, + input [1:0] PIPERX3CHARISK, + input [31:0] PIPERX3DATA, + input PIPERX3DATAVALID, + input PIPERX3ELECIDLE, + input PIPERX3EQDONE, + input PIPERX3EQLPADAPTDONE, + input PIPERX3EQLPLFFSSEL, + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET, + input PIPERX3PHYSTATUS, + input PIPERX3STARTBLOCK, + input [2:0] PIPERX3STATUS, + input [1:0] PIPERX3SYNCHEADER, + input PIPERX3VALID, + input [1:0] PIPERX4CHARISK, + input [31:0] PIPERX4DATA, + input PIPERX4DATAVALID, + input PIPERX4ELECIDLE, + input PIPERX4EQDONE, + input PIPERX4EQLPADAPTDONE, + input PIPERX4EQLPLFFSSEL, + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET, + input PIPERX4PHYSTATUS, + input PIPERX4STARTBLOCK, + input [2:0] PIPERX4STATUS, + input [1:0] PIPERX4SYNCHEADER, + input PIPERX4VALID, + input [1:0] PIPERX5CHARISK, + input [31:0] PIPERX5DATA, + input PIPERX5DATAVALID, + input PIPERX5ELECIDLE, + input PIPERX5EQDONE, + input PIPERX5EQLPADAPTDONE, + input PIPERX5EQLPLFFSSEL, + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET, + input PIPERX5PHYSTATUS, + input PIPERX5STARTBLOCK, + input [2:0] PIPERX5STATUS, + input [1:0] PIPERX5SYNCHEADER, + input PIPERX5VALID, + input [1:0] PIPERX6CHARISK, + input [31:0] PIPERX6DATA, + input PIPERX6DATAVALID, + input PIPERX6ELECIDLE, + input PIPERX6EQDONE, + input PIPERX6EQLPADAPTDONE, + input PIPERX6EQLPLFFSSEL, + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET, + input PIPERX6PHYSTATUS, + input PIPERX6STARTBLOCK, + input [2:0] PIPERX6STATUS, + input [1:0] PIPERX6SYNCHEADER, + input PIPERX6VALID, + input [1:0] PIPERX7CHARISK, + input [31:0] PIPERX7DATA, + input PIPERX7DATAVALID, + input PIPERX7ELECIDLE, + input PIPERX7EQDONE, + input PIPERX7EQLPADAPTDONE, + input PIPERX7EQLPLFFSSEL, + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET, + input PIPERX7PHYSTATUS, + input PIPERX7STARTBLOCK, + input [2:0] PIPERX7STATUS, + input [1:0] PIPERX7SYNCHEADER, + input PIPERX7VALID, + input [17:0] PIPETX0EQCOEFF, + input PIPETX0EQDONE, + input [17:0] PIPETX1EQCOEFF, + input PIPETX1EQDONE, + input [17:0] PIPETX2EQCOEFF, + input PIPETX2EQDONE, + input [17:0] PIPETX3EQCOEFF, + input PIPETX3EQDONE, + input [17:0] PIPETX4EQCOEFF, + input PIPETX4EQDONE, + input [17:0] PIPETX5EQCOEFF, + input PIPETX5EQDONE, + input [17:0] PIPETX6EQCOEFF, + input PIPETX6EQDONE, + input [17:0] PIPETX7EQCOEFF, + input PIPETX7EQDONE, + input PLEQRESETEIEOSCOUNT, + input PLGEN2UPSTREAMPREFERDEEMPH, + input RESETN, + input [255:0] SAXISCCTDATA, + input [7:0] SAXISCCTKEEP, + input SAXISCCTLAST, + input [32:0] SAXISCCTUSER, + input SAXISCCTVALID, + input [255:0] SAXISRQTDATA, + input [7:0] SAXISRQTKEEP, + input SAXISRQTLAST, + input [59:0] SAXISRQTUSER, + input SAXISRQTVALID, + input [31:0] SPAREIN, + input USERCLK +); + +// define constants + localparam MODULE_NAME = "PCIE_3_1"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + +// Parameter encodings and registers + + `ifndef XIL_DR + localparam [40:1] ARI_CAP_ENABLE_REG = ARI_CAP_ENABLE; + localparam [40:1] AXISTEN_IF_CC_ALIGNMENT_MODE_REG = AXISTEN_IF_CC_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_CC_PARITY_CHK_REG = AXISTEN_IF_CC_PARITY_CHK; + localparam [40:1] AXISTEN_IF_CQ_ALIGNMENT_MODE_REG = AXISTEN_IF_CQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_ENABLE_CLIENT_TAG_REG = AXISTEN_IF_ENABLE_CLIENT_TAG; + localparam [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE_REG = AXISTEN_IF_ENABLE_MSG_ROUTE; + localparam [40:1] AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG = AXISTEN_IF_ENABLE_RX_MSG_INTFC; + localparam [40:1] AXISTEN_IF_RC_ALIGNMENT_MODE_REG = AXISTEN_IF_RC_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RC_STRADDLE_REG = AXISTEN_IF_RC_STRADDLE; + localparam [40:1] AXISTEN_IF_RQ_ALIGNMENT_MODE_REG = AXISTEN_IF_RQ_ALIGNMENT_MODE; + localparam [40:1] AXISTEN_IF_RQ_PARITY_CHK_REG = AXISTEN_IF_RQ_PARITY_CHK; + localparam [1:0] AXISTEN_IF_WIDTH_REG = AXISTEN_IF_WIDTH; + localparam [40:1] CRM_CORE_CLK_FREQ_500_REG = CRM_CORE_CLK_FREQ_500; + localparam [1:0] CRM_USER_CLK_FREQ_REG = CRM_USER_CLK_FREQ; + localparam [40:1] DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG = DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE; + localparam [40:1] DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG = DEBUG_PL_DISABLE_EI_INFER_IN_L0; + localparam [40:1] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG = DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS; + localparam [7:0] DNSTREAM_LINK_NUM_REG = DNSTREAM_LINK_NUM; + localparam [8:0] LL_ACK_TIMEOUT_REG = LL_ACK_TIMEOUT; + localparam [40:1] LL_ACK_TIMEOUT_EN_REG = LL_ACK_TIMEOUT_EN; + localparam [1:0] LL_ACK_TIMEOUT_FUNC_REG = LL_ACK_TIMEOUT_FUNC; + localparam [15:0] LL_CPL_FC_UPDATE_TIMER_REG = LL_CPL_FC_UPDATE_TIMER; + localparam [40:1] LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG = LL_CPL_FC_UPDATE_TIMER_OVERRIDE; + localparam [15:0] LL_FC_UPDATE_TIMER_REG = LL_FC_UPDATE_TIMER; + localparam [40:1] LL_FC_UPDATE_TIMER_OVERRIDE_REG = LL_FC_UPDATE_TIMER_OVERRIDE; + localparam [15:0] LL_NP_FC_UPDATE_TIMER_REG = LL_NP_FC_UPDATE_TIMER; + localparam [40:1] LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG = LL_NP_FC_UPDATE_TIMER_OVERRIDE; + localparam [15:0] LL_P_FC_UPDATE_TIMER_REG = LL_P_FC_UPDATE_TIMER; + localparam [40:1] LL_P_FC_UPDATE_TIMER_OVERRIDE_REG = LL_P_FC_UPDATE_TIMER_OVERRIDE; + localparam [8:0] LL_REPLAY_TIMEOUT_REG = LL_REPLAY_TIMEOUT; + localparam [40:1] LL_REPLAY_TIMEOUT_EN_REG = LL_REPLAY_TIMEOUT_EN; + localparam [1:0] LL_REPLAY_TIMEOUT_FUNC_REG = LL_REPLAY_TIMEOUT_FUNC; + localparam [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG = LTR_TX_MESSAGE_MINIMUM_INTERVAL; + localparam [40:1] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG = LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE; + localparam [40:1] LTR_TX_MESSAGE_ON_LTR_ENABLE_REG = LTR_TX_MESSAGE_ON_LTR_ENABLE; + localparam [11:0] MCAP_CAP_NEXTPTR_REG = MCAP_CAP_NEXTPTR; + localparam [40:1] MCAP_CONFIGURE_OVERRIDE_REG = MCAP_CONFIGURE_OVERRIDE; + localparam [40:1] MCAP_ENABLE_REG = MCAP_ENABLE; + localparam [40:1] MCAP_EOS_DESIGN_SWITCH_REG = MCAP_EOS_DESIGN_SWITCH; + localparam [31:0] MCAP_FPGA_BITSTREAM_VERSION_REG = MCAP_FPGA_BITSTREAM_VERSION; + localparam [40:1] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_IO_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH; + localparam [40:1] MCAP_INPUT_GATE_DESIGN_SWITCH_REG = MCAP_INPUT_GATE_DESIGN_SWITCH; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_EOS_REG = MCAP_INTERRUPT_ON_MCAP_EOS; + localparam [40:1] MCAP_INTERRUPT_ON_MCAP_ERROR_REG = MCAP_INTERRUPT_ON_MCAP_ERROR; + localparam [15:0] MCAP_VSEC_ID_REG = MCAP_VSEC_ID; + localparam [11:0] MCAP_VSEC_LEN_REG = MCAP_VSEC_LEN; + localparam [3:0] MCAP_VSEC_REV_REG = MCAP_VSEC_REV; + localparam [40:1] PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF0_AER_CAP_ECRC_CHECK_CAPABLE; + localparam [40:1] PF0_AER_CAP_ECRC_GEN_CAPABLE_REG = PF0_AER_CAP_ECRC_GEN_CAPABLE; + localparam [11:0] PF0_AER_CAP_NEXTPTR_REG = PF0_AER_CAP_NEXTPTR; + localparam [11:0] PF0_ARI_CAP_NEXTPTR_REG = PF0_ARI_CAP_NEXTPTR; + localparam [7:0] PF0_ARI_CAP_NEXT_FUNC_REG = PF0_ARI_CAP_NEXT_FUNC; + localparam [3:0] PF0_ARI_CAP_VER_REG = PF0_ARI_CAP_VER; + localparam [5:0] PF0_BAR0_APERTURE_SIZE_REG = PF0_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_BAR0_CONTROL_REG = PF0_BAR0_CONTROL; + localparam [5:0] PF0_BAR1_APERTURE_SIZE_REG = PF0_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_BAR1_CONTROL_REG = PF0_BAR1_CONTROL; + localparam [4:0] PF0_BAR2_APERTURE_SIZE_REG = PF0_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_BAR2_CONTROL_REG = PF0_BAR2_CONTROL; + localparam [4:0] PF0_BAR3_APERTURE_SIZE_REG = PF0_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_BAR3_CONTROL_REG = PF0_BAR3_CONTROL; + localparam [4:0] PF0_BAR4_APERTURE_SIZE_REG = PF0_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_BAR4_CONTROL_REG = PF0_BAR4_CONTROL; + localparam [4:0] PF0_BAR5_APERTURE_SIZE_REG = PF0_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_BAR5_CONTROL_REG = PF0_BAR5_CONTROL; + localparam [7:0] PF0_BIST_REGISTER_REG = PF0_BIST_REGISTER; + localparam [7:0] PF0_CAPABILITY_POINTER_REG = PF0_CAPABILITY_POINTER; + localparam [23:0] PF0_CLASS_CODE_REG = PF0_CLASS_CODE; + localparam [15:0] PF0_DEVICE_ID_REG = PF0_DEVICE_ID; + localparam [40:1] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG = PF0_DEV_CAP2_ARI_FORWARD_ENABLE; + localparam [40:1] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG = PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE; + localparam [40:1] PF0_DEV_CAP2_LTR_SUPPORT_REG = PF0_DEV_CAP2_LTR_SUPPORT; + localparam [1:0] PF0_DEV_CAP2_OBFF_SUPPORT_REG = PF0_DEV_CAP2_OBFF_SUPPORT; + localparam [40:1] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY; + localparam [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L1_LATENCY; + localparam [40:1] PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG = PF0_DEV_CAP_EXT_TAG_SUPPORTED; + localparam [40:1] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG = PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE; + localparam [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF0_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF0_DPA_CAP_NEXTPTR_REG = PF0_DPA_CAP_NEXTPTR; + localparam [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL_REG = PF0_DPA_CAP_SUB_STATE_CONTROL; + localparam [40:1] PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF0_DPA_CAP_SUB_STATE_CONTROL_EN; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6; + localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7; + localparam [3:0] PF0_DPA_CAP_VER_REG = PF0_DPA_CAP_VER; + localparam [11:0] PF0_DSN_CAP_NEXTPTR_REG = PF0_DSN_CAP_NEXTPTR; + localparam [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE_REG = PF0_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF0_EXPANSION_ROM_ENABLE_REG = PF0_EXPANSION_ROM_ENABLE; + localparam [7:0] PF0_INTERRUPT_LINE_REG = PF0_INTERRUPT_LINE; + localparam [2:0] PF0_INTERRUPT_PIN_REG = PF0_INTERRUPT_PIN; + localparam [1:0] PF0_LINK_CAP_ASPM_SUPPORT_REG = PF0_LINK_CAP_ASPM_SUPPORT; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2; + localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3; + localparam [40:1] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG = PF0_LINK_STATUS_SLOT_CLOCK_CONFIG; + localparam [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG = PF0_LTR_CAP_MAX_NOSNOOP_LAT; + localparam [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT_REG = PF0_LTR_CAP_MAX_SNOOP_LAT; + localparam [11:0] PF0_LTR_CAP_NEXTPTR_REG = PF0_LTR_CAP_NEXTPTR; + localparam [3:0] PF0_LTR_CAP_VER_REG = PF0_LTR_CAP_VER; + localparam [7:0] PF0_MSIX_CAP_NEXTPTR_REG = PF0_MSIX_CAP_NEXTPTR; + localparam [2:0] PF0_MSIX_CAP_PBA_BIR_REG = PF0_MSIX_CAP_PBA_BIR; + localparam [28:0] PF0_MSIX_CAP_PBA_OFFSET_REG = PF0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF0_MSIX_CAP_TABLE_BIR_REG = PF0_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF0_MSIX_CAP_TABLE_OFFSET_REG = PF0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF0_MSIX_CAP_TABLE_SIZE_REG = PF0_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF0_MSI_CAP_MULTIMSGCAP_REG = PF0_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF0_MSI_CAP_NEXTPTR_REG = PF0_MSI_CAP_NEXTPTR; + localparam [40:1] PF0_MSI_CAP_PERVECMASKCAP_REG = PF0_MSI_CAP_PERVECMASKCAP; + localparam [31:0] PF0_PB_CAP_DATA_REG_D0_REG = PF0_PB_CAP_DATA_REG_D0; + localparam [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF0_PB_CAP_DATA_REG_D0_SUSTAINED; + localparam [31:0] PF0_PB_CAP_DATA_REG_D1_REG = PF0_PB_CAP_DATA_REG_D1; + localparam [31:0] PF0_PB_CAP_DATA_REG_D3HOT_REG = PF0_PB_CAP_DATA_REG_D3HOT; + localparam [11:0] PF0_PB_CAP_NEXTPTR_REG = PF0_PB_CAP_NEXTPTR; + localparam [40:1] PF0_PB_CAP_SYSTEM_ALLOCATED_REG = PF0_PB_CAP_SYSTEM_ALLOCATED; + localparam [3:0] PF0_PB_CAP_VER_REG = PF0_PB_CAP_VER; + localparam [7:0] PF0_PM_CAP_ID_REG = PF0_PM_CAP_ID; + localparam [7:0] PF0_PM_CAP_NEXTPTR_REG = PF0_PM_CAP_NEXTPTR; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D0_REG = PF0_PM_CAP_PMESUPPORT_D0; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D1_REG = PF0_PM_CAP_PMESUPPORT_D1; + localparam [40:1] PF0_PM_CAP_PMESUPPORT_D3HOT_REG = PF0_PM_CAP_PMESUPPORT_D3HOT; + localparam [40:1] PF0_PM_CAP_SUPP_D1_STATE_REG = PF0_PM_CAP_SUPP_D1_STATE; + localparam [2:0] PF0_PM_CAP_VER_ID_REG = PF0_PM_CAP_VER_ID; + localparam [40:1] PF0_PM_CSR_NOSOFTRESET_REG = PF0_PM_CSR_NOSOFTRESET; + localparam [40:1] PF0_RBAR_CAP_ENABLE_REG = PF0_RBAR_CAP_ENABLE; + localparam [11:0] PF0_RBAR_CAP_NEXTPTR_REG = PF0_RBAR_CAP_NEXTPTR; + localparam [19:0] PF0_RBAR_CAP_SIZE0_REG = PF0_RBAR_CAP_SIZE0; + localparam [19:0] PF0_RBAR_CAP_SIZE1_REG = PF0_RBAR_CAP_SIZE1; + localparam [19:0] PF0_RBAR_CAP_SIZE2_REG = PF0_RBAR_CAP_SIZE2; + localparam [3:0] PF0_RBAR_CAP_VER_REG = PF0_RBAR_CAP_VER; + localparam [2:0] PF0_RBAR_CONTROL_INDEX0_REG = PF0_RBAR_CONTROL_INDEX0; + localparam [2:0] PF0_RBAR_CONTROL_INDEX1_REG = PF0_RBAR_CONTROL_INDEX1; + localparam [2:0] PF0_RBAR_CONTROL_INDEX2_REG = PF0_RBAR_CONTROL_INDEX2; + localparam [4:0] PF0_RBAR_CONTROL_SIZE0_REG = PF0_RBAR_CONTROL_SIZE0; + localparam [4:0] PF0_RBAR_CONTROL_SIZE1_REG = PF0_RBAR_CONTROL_SIZE1; + localparam [4:0] PF0_RBAR_CONTROL_SIZE2_REG = PF0_RBAR_CONTROL_SIZE2; + localparam [2:0] PF0_RBAR_NUM_REG = PF0_RBAR_NUM; + localparam [7:0] PF0_REVISION_ID_REG = PF0_REVISION_ID; + localparam [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG = PF0_SECONDARY_PCIE_CAP_NEXTPTR; + localparam [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE_REG = PF0_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR0_CONTROL_REG = PF0_SRIOV_BAR0_CONTROL; + localparam [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE_REG = PF0_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR1_CONTROL_REG = PF0_SRIOV_BAR1_CONTROL; + localparam [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE_REG = PF0_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR2_CONTROL_REG = PF0_SRIOV_BAR2_CONTROL; + localparam [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE_REG = PF0_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR3_CONTROL_REG = PF0_SRIOV_BAR3_CONTROL; + localparam [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE_REG = PF0_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR4_CONTROL_REG = PF0_SRIOV_BAR4_CONTROL; + localparam [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE_REG = PF0_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF0_SRIOV_BAR5_CONTROL_REG = PF0_SRIOV_BAR5_CONTROL; + localparam [15:0] PF0_SRIOV_CAP_INITIAL_VF_REG = PF0_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF0_SRIOV_CAP_NEXTPTR_REG = PF0_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF0_SRIOV_CAP_TOTAL_VF_REG = PF0_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF0_SRIOV_CAP_VER_REG = PF0_SRIOV_CAP_VER; + localparam [15:0] PF0_SRIOV_FIRST_VF_OFFSET_REG = PF0_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF0_SRIOV_FUNC_DEP_LINK_REG = PF0_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF0_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF0_SRIOV_VF_DEVICE_ID_REG = PF0_SRIOV_VF_DEVICE_ID; + localparam [15:0] PF0_SUBSYSTEM_ID_REG = PF0_SUBSYSTEM_ID; + localparam [40:1] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF0_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF0_TPHR_CAP_ENABLE_REG = PF0_TPHR_CAP_ENABLE; + localparam [40:1] PF0_TPHR_CAP_INT_VEC_MODE_REG = PF0_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF0_TPHR_CAP_NEXTPTR_REG = PF0_TPHR_CAP_NEXTPTR; + localparam [2:0] PF0_TPHR_CAP_ST_MODE_SEL_REG = PF0_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF0_TPHR_CAP_ST_TABLE_LOC_REG = PF0_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE_REG = PF0_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF0_TPHR_CAP_VER_REG = PF0_TPHR_CAP_VER; + localparam [40:1] PF0_VC_CAP_ENABLE_REG = PF0_VC_CAP_ENABLE; + localparam [11:0] PF0_VC_CAP_NEXTPTR_REG = PF0_VC_CAP_NEXTPTR; + localparam [3:0] PF0_VC_CAP_VER_REG = PF0_VC_CAP_VER; + localparam [40:1] PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF1_AER_CAP_ECRC_CHECK_CAPABLE; + localparam [40:1] PF1_AER_CAP_ECRC_GEN_CAPABLE_REG = PF1_AER_CAP_ECRC_GEN_CAPABLE; + localparam [11:0] PF1_AER_CAP_NEXTPTR_REG = PF1_AER_CAP_NEXTPTR; + localparam [11:0] PF1_ARI_CAP_NEXTPTR_REG = PF1_ARI_CAP_NEXTPTR; + localparam [7:0] PF1_ARI_CAP_NEXT_FUNC_REG = PF1_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF1_BAR0_APERTURE_SIZE_REG = PF1_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_BAR0_CONTROL_REG = PF1_BAR0_CONTROL; + localparam [5:0] PF1_BAR1_APERTURE_SIZE_REG = PF1_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_BAR1_CONTROL_REG = PF1_BAR1_CONTROL; + localparam [4:0] PF1_BAR2_APERTURE_SIZE_REG = PF1_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_BAR2_CONTROL_REG = PF1_BAR2_CONTROL; + localparam [4:0] PF1_BAR3_APERTURE_SIZE_REG = PF1_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_BAR3_CONTROL_REG = PF1_BAR3_CONTROL; + localparam [4:0] PF1_BAR4_APERTURE_SIZE_REG = PF1_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_BAR4_CONTROL_REG = PF1_BAR4_CONTROL; + localparam [4:0] PF1_BAR5_APERTURE_SIZE_REG = PF1_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_BAR5_CONTROL_REG = PF1_BAR5_CONTROL; + localparam [7:0] PF1_BIST_REGISTER_REG = PF1_BIST_REGISTER; + localparam [7:0] PF1_CAPABILITY_POINTER_REG = PF1_CAPABILITY_POINTER; + localparam [23:0] PF1_CLASS_CODE_REG = PF1_CLASS_CODE; + localparam [15:0] PF1_DEVICE_ID_REG = PF1_DEVICE_ID; + localparam [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF1_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF1_DPA_CAP_NEXTPTR_REG = PF1_DPA_CAP_NEXTPTR; + localparam [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL_REG = PF1_DPA_CAP_SUB_STATE_CONTROL; + localparam [40:1] PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF1_DPA_CAP_SUB_STATE_CONTROL_EN; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6; + localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7; + localparam [3:0] PF1_DPA_CAP_VER_REG = PF1_DPA_CAP_VER; + localparam [11:0] PF1_DSN_CAP_NEXTPTR_REG = PF1_DSN_CAP_NEXTPTR; + localparam [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE_REG = PF1_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF1_EXPANSION_ROM_ENABLE_REG = PF1_EXPANSION_ROM_ENABLE; + localparam [7:0] PF1_INTERRUPT_LINE_REG = PF1_INTERRUPT_LINE; + localparam [2:0] PF1_INTERRUPT_PIN_REG = PF1_INTERRUPT_PIN; + localparam [7:0] PF1_MSIX_CAP_NEXTPTR_REG = PF1_MSIX_CAP_NEXTPTR; + localparam [2:0] PF1_MSIX_CAP_PBA_BIR_REG = PF1_MSIX_CAP_PBA_BIR; + localparam [28:0] PF1_MSIX_CAP_PBA_OFFSET_REG = PF1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF1_MSIX_CAP_TABLE_BIR_REG = PF1_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF1_MSIX_CAP_TABLE_OFFSET_REG = PF1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF1_MSIX_CAP_TABLE_SIZE_REG = PF1_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF1_MSI_CAP_MULTIMSGCAP_REG = PF1_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF1_MSI_CAP_NEXTPTR_REG = PF1_MSI_CAP_NEXTPTR; + localparam [40:1] PF1_MSI_CAP_PERVECMASKCAP_REG = PF1_MSI_CAP_PERVECMASKCAP; + localparam [31:0] PF1_PB_CAP_DATA_REG_D0_REG = PF1_PB_CAP_DATA_REG_D0; + localparam [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF1_PB_CAP_DATA_REG_D0_SUSTAINED; + localparam [31:0] PF1_PB_CAP_DATA_REG_D1_REG = PF1_PB_CAP_DATA_REG_D1; + localparam [31:0] PF1_PB_CAP_DATA_REG_D3HOT_REG = PF1_PB_CAP_DATA_REG_D3HOT; + localparam [11:0] PF1_PB_CAP_NEXTPTR_REG = PF1_PB_CAP_NEXTPTR; + localparam [40:1] PF1_PB_CAP_SYSTEM_ALLOCATED_REG = PF1_PB_CAP_SYSTEM_ALLOCATED; + localparam [3:0] PF1_PB_CAP_VER_REG = PF1_PB_CAP_VER; + localparam [7:0] PF1_PM_CAP_ID_REG = PF1_PM_CAP_ID; + localparam [7:0] PF1_PM_CAP_NEXTPTR_REG = PF1_PM_CAP_NEXTPTR; + localparam [2:0] PF1_PM_CAP_VER_ID_REG = PF1_PM_CAP_VER_ID; + localparam [40:1] PF1_RBAR_CAP_ENABLE_REG = PF1_RBAR_CAP_ENABLE; + localparam [11:0] PF1_RBAR_CAP_NEXTPTR_REG = PF1_RBAR_CAP_NEXTPTR; + localparam [19:0] PF1_RBAR_CAP_SIZE0_REG = PF1_RBAR_CAP_SIZE0; + localparam [19:0] PF1_RBAR_CAP_SIZE1_REG = PF1_RBAR_CAP_SIZE1; + localparam [19:0] PF1_RBAR_CAP_SIZE2_REG = PF1_RBAR_CAP_SIZE2; + localparam [3:0] PF1_RBAR_CAP_VER_REG = PF1_RBAR_CAP_VER; + localparam [2:0] PF1_RBAR_CONTROL_INDEX0_REG = PF1_RBAR_CONTROL_INDEX0; + localparam [2:0] PF1_RBAR_CONTROL_INDEX1_REG = PF1_RBAR_CONTROL_INDEX1; + localparam [2:0] PF1_RBAR_CONTROL_INDEX2_REG = PF1_RBAR_CONTROL_INDEX2; + localparam [4:0] PF1_RBAR_CONTROL_SIZE0_REG = PF1_RBAR_CONTROL_SIZE0; + localparam [4:0] PF1_RBAR_CONTROL_SIZE1_REG = PF1_RBAR_CONTROL_SIZE1; + localparam [4:0] PF1_RBAR_CONTROL_SIZE2_REG = PF1_RBAR_CONTROL_SIZE2; + localparam [2:0] PF1_RBAR_NUM_REG = PF1_RBAR_NUM; + localparam [7:0] PF1_REVISION_ID_REG = PF1_REVISION_ID; + localparam [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE_REG = PF1_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR0_CONTROL_REG = PF1_SRIOV_BAR0_CONTROL; + localparam [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE_REG = PF1_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR1_CONTROL_REG = PF1_SRIOV_BAR1_CONTROL; + localparam [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE_REG = PF1_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR2_CONTROL_REG = PF1_SRIOV_BAR2_CONTROL; + localparam [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE_REG = PF1_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR3_CONTROL_REG = PF1_SRIOV_BAR3_CONTROL; + localparam [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE_REG = PF1_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR4_CONTROL_REG = PF1_SRIOV_BAR4_CONTROL; + localparam [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE_REG = PF1_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF1_SRIOV_BAR5_CONTROL_REG = PF1_SRIOV_BAR5_CONTROL; + localparam [15:0] PF1_SRIOV_CAP_INITIAL_VF_REG = PF1_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF1_SRIOV_CAP_NEXTPTR_REG = PF1_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF1_SRIOV_CAP_TOTAL_VF_REG = PF1_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF1_SRIOV_CAP_VER_REG = PF1_SRIOV_CAP_VER; + localparam [15:0] PF1_SRIOV_FIRST_VF_OFFSET_REG = PF1_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF1_SRIOV_FUNC_DEP_LINK_REG = PF1_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF1_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF1_SRIOV_VF_DEVICE_ID_REG = PF1_SRIOV_VF_DEVICE_ID; + localparam [15:0] PF1_SUBSYSTEM_ID_REG = PF1_SUBSYSTEM_ID; + localparam [40:1] PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF1_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF1_TPHR_CAP_ENABLE_REG = PF1_TPHR_CAP_ENABLE; + localparam [40:1] PF1_TPHR_CAP_INT_VEC_MODE_REG = PF1_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF1_TPHR_CAP_NEXTPTR_REG = PF1_TPHR_CAP_NEXTPTR; + localparam [2:0] PF1_TPHR_CAP_ST_MODE_SEL_REG = PF1_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF1_TPHR_CAP_ST_TABLE_LOC_REG = PF1_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE_REG = PF1_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF1_TPHR_CAP_VER_REG = PF1_TPHR_CAP_VER; + localparam [40:1] PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF2_AER_CAP_ECRC_CHECK_CAPABLE; + localparam [40:1] PF2_AER_CAP_ECRC_GEN_CAPABLE_REG = PF2_AER_CAP_ECRC_GEN_CAPABLE; + localparam [11:0] PF2_AER_CAP_NEXTPTR_REG = PF2_AER_CAP_NEXTPTR; + localparam [11:0] PF2_ARI_CAP_NEXTPTR_REG = PF2_ARI_CAP_NEXTPTR; + localparam [7:0] PF2_ARI_CAP_NEXT_FUNC_REG = PF2_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF2_BAR0_APERTURE_SIZE_REG = PF2_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_BAR0_CONTROL_REG = PF2_BAR0_CONTROL; + localparam [5:0] PF2_BAR1_APERTURE_SIZE_REG = PF2_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_BAR1_CONTROL_REG = PF2_BAR1_CONTROL; + localparam [4:0] PF2_BAR2_APERTURE_SIZE_REG = PF2_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_BAR2_CONTROL_REG = PF2_BAR2_CONTROL; + localparam [4:0] PF2_BAR3_APERTURE_SIZE_REG = PF2_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_BAR3_CONTROL_REG = PF2_BAR3_CONTROL; + localparam [4:0] PF2_BAR4_APERTURE_SIZE_REG = PF2_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_BAR4_CONTROL_REG = PF2_BAR4_CONTROL; + localparam [4:0] PF2_BAR5_APERTURE_SIZE_REG = PF2_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_BAR5_CONTROL_REG = PF2_BAR5_CONTROL; + localparam [7:0] PF2_BIST_REGISTER_REG = PF2_BIST_REGISTER; + localparam [7:0] PF2_CAPABILITY_POINTER_REG = PF2_CAPABILITY_POINTER; + localparam [23:0] PF2_CLASS_CODE_REG = PF2_CLASS_CODE; + localparam [15:0] PF2_DEVICE_ID_REG = PF2_DEVICE_ID; + localparam [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF2_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF2_DPA_CAP_NEXTPTR_REG = PF2_DPA_CAP_NEXTPTR; + localparam [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL_REG = PF2_DPA_CAP_SUB_STATE_CONTROL; + localparam [40:1] PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF2_DPA_CAP_SUB_STATE_CONTROL_EN; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6; + localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7; + localparam [3:0] PF2_DPA_CAP_VER_REG = PF2_DPA_CAP_VER; + localparam [11:0] PF2_DSN_CAP_NEXTPTR_REG = PF2_DSN_CAP_NEXTPTR; + localparam [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE_REG = PF2_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF2_EXPANSION_ROM_ENABLE_REG = PF2_EXPANSION_ROM_ENABLE; + localparam [7:0] PF2_INTERRUPT_LINE_REG = PF2_INTERRUPT_LINE; + localparam [2:0] PF2_INTERRUPT_PIN_REG = PF2_INTERRUPT_PIN; + localparam [7:0] PF2_MSIX_CAP_NEXTPTR_REG = PF2_MSIX_CAP_NEXTPTR; + localparam [2:0] PF2_MSIX_CAP_PBA_BIR_REG = PF2_MSIX_CAP_PBA_BIR; + localparam [28:0] PF2_MSIX_CAP_PBA_OFFSET_REG = PF2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF2_MSIX_CAP_TABLE_BIR_REG = PF2_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF2_MSIX_CAP_TABLE_OFFSET_REG = PF2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF2_MSIX_CAP_TABLE_SIZE_REG = PF2_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF2_MSI_CAP_MULTIMSGCAP_REG = PF2_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF2_MSI_CAP_NEXTPTR_REG = PF2_MSI_CAP_NEXTPTR; + localparam [40:1] PF2_MSI_CAP_PERVECMASKCAP_REG = PF2_MSI_CAP_PERVECMASKCAP; + localparam [31:0] PF2_PB_CAP_DATA_REG_D0_REG = PF2_PB_CAP_DATA_REG_D0; + localparam [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF2_PB_CAP_DATA_REG_D0_SUSTAINED; + localparam [31:0] PF2_PB_CAP_DATA_REG_D1_REG = PF2_PB_CAP_DATA_REG_D1; + localparam [31:0] PF2_PB_CAP_DATA_REG_D3HOT_REG = PF2_PB_CAP_DATA_REG_D3HOT; + localparam [11:0] PF2_PB_CAP_NEXTPTR_REG = PF2_PB_CAP_NEXTPTR; + localparam [40:1] PF2_PB_CAP_SYSTEM_ALLOCATED_REG = PF2_PB_CAP_SYSTEM_ALLOCATED; + localparam [3:0] PF2_PB_CAP_VER_REG = PF2_PB_CAP_VER; + localparam [7:0] PF2_PM_CAP_ID_REG = PF2_PM_CAP_ID; + localparam [7:0] PF2_PM_CAP_NEXTPTR_REG = PF2_PM_CAP_NEXTPTR; + localparam [2:0] PF2_PM_CAP_VER_ID_REG = PF2_PM_CAP_VER_ID; + localparam [40:1] PF2_RBAR_CAP_ENABLE_REG = PF2_RBAR_CAP_ENABLE; + localparam [11:0] PF2_RBAR_CAP_NEXTPTR_REG = PF2_RBAR_CAP_NEXTPTR; + localparam [19:0] PF2_RBAR_CAP_SIZE0_REG = PF2_RBAR_CAP_SIZE0; + localparam [19:0] PF2_RBAR_CAP_SIZE1_REG = PF2_RBAR_CAP_SIZE1; + localparam [19:0] PF2_RBAR_CAP_SIZE2_REG = PF2_RBAR_CAP_SIZE2; + localparam [3:0] PF2_RBAR_CAP_VER_REG = PF2_RBAR_CAP_VER; + localparam [2:0] PF2_RBAR_CONTROL_INDEX0_REG = PF2_RBAR_CONTROL_INDEX0; + localparam [2:0] PF2_RBAR_CONTROL_INDEX1_REG = PF2_RBAR_CONTROL_INDEX1; + localparam [2:0] PF2_RBAR_CONTROL_INDEX2_REG = PF2_RBAR_CONTROL_INDEX2; + localparam [4:0] PF2_RBAR_CONTROL_SIZE0_REG = PF2_RBAR_CONTROL_SIZE0; + localparam [4:0] PF2_RBAR_CONTROL_SIZE1_REG = PF2_RBAR_CONTROL_SIZE1; + localparam [4:0] PF2_RBAR_CONTROL_SIZE2_REG = PF2_RBAR_CONTROL_SIZE2; + localparam [2:0] PF2_RBAR_NUM_REG = PF2_RBAR_NUM; + localparam [7:0] PF2_REVISION_ID_REG = PF2_REVISION_ID; + localparam [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE_REG = PF2_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR0_CONTROL_REG = PF2_SRIOV_BAR0_CONTROL; + localparam [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE_REG = PF2_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR1_CONTROL_REG = PF2_SRIOV_BAR1_CONTROL; + localparam [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE_REG = PF2_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR2_CONTROL_REG = PF2_SRIOV_BAR2_CONTROL; + localparam [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE_REG = PF2_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR3_CONTROL_REG = PF2_SRIOV_BAR3_CONTROL; + localparam [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE_REG = PF2_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR4_CONTROL_REG = PF2_SRIOV_BAR4_CONTROL; + localparam [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE_REG = PF2_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF2_SRIOV_BAR5_CONTROL_REG = PF2_SRIOV_BAR5_CONTROL; + localparam [15:0] PF2_SRIOV_CAP_INITIAL_VF_REG = PF2_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF2_SRIOV_CAP_NEXTPTR_REG = PF2_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF2_SRIOV_CAP_TOTAL_VF_REG = PF2_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF2_SRIOV_CAP_VER_REG = PF2_SRIOV_CAP_VER; + localparam [15:0] PF2_SRIOV_FIRST_VF_OFFSET_REG = PF2_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF2_SRIOV_FUNC_DEP_LINK_REG = PF2_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF2_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF2_SRIOV_VF_DEVICE_ID_REG = PF2_SRIOV_VF_DEVICE_ID; + localparam [15:0] PF2_SUBSYSTEM_ID_REG = PF2_SUBSYSTEM_ID; + localparam [40:1] PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF2_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF2_TPHR_CAP_ENABLE_REG = PF2_TPHR_CAP_ENABLE; + localparam [40:1] PF2_TPHR_CAP_INT_VEC_MODE_REG = PF2_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF2_TPHR_CAP_NEXTPTR_REG = PF2_TPHR_CAP_NEXTPTR; + localparam [2:0] PF2_TPHR_CAP_ST_MODE_SEL_REG = PF2_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF2_TPHR_CAP_ST_TABLE_LOC_REG = PF2_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE_REG = PF2_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF2_TPHR_CAP_VER_REG = PF2_TPHR_CAP_VER; + localparam [40:1] PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF3_AER_CAP_ECRC_CHECK_CAPABLE; + localparam [40:1] PF3_AER_CAP_ECRC_GEN_CAPABLE_REG = PF3_AER_CAP_ECRC_GEN_CAPABLE; + localparam [11:0] PF3_AER_CAP_NEXTPTR_REG = PF3_AER_CAP_NEXTPTR; + localparam [11:0] PF3_ARI_CAP_NEXTPTR_REG = PF3_ARI_CAP_NEXTPTR; + localparam [7:0] PF3_ARI_CAP_NEXT_FUNC_REG = PF3_ARI_CAP_NEXT_FUNC; + localparam [5:0] PF3_BAR0_APERTURE_SIZE_REG = PF3_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_BAR0_CONTROL_REG = PF3_BAR0_CONTROL; + localparam [5:0] PF3_BAR1_APERTURE_SIZE_REG = PF3_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_BAR1_CONTROL_REG = PF3_BAR1_CONTROL; + localparam [4:0] PF3_BAR2_APERTURE_SIZE_REG = PF3_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_BAR2_CONTROL_REG = PF3_BAR2_CONTROL; + localparam [4:0] PF3_BAR3_APERTURE_SIZE_REG = PF3_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_BAR3_CONTROL_REG = PF3_BAR3_CONTROL; + localparam [4:0] PF3_BAR4_APERTURE_SIZE_REG = PF3_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_BAR4_CONTROL_REG = PF3_BAR4_CONTROL; + localparam [4:0] PF3_BAR5_APERTURE_SIZE_REG = PF3_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_BAR5_CONTROL_REG = PF3_BAR5_CONTROL; + localparam [7:0] PF3_BIST_REGISTER_REG = PF3_BIST_REGISTER; + localparam [7:0] PF3_CAPABILITY_POINTER_REG = PF3_CAPABILITY_POINTER; + localparam [23:0] PF3_CLASS_CODE_REG = PF3_CLASS_CODE; + localparam [15:0] PF3_DEVICE_ID_REG = PF3_DEVICE_ID; + localparam [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF3_DEV_CAP_MAX_PAYLOAD_SIZE; + localparam [11:0] PF3_DPA_CAP_NEXTPTR_REG = PF3_DPA_CAP_NEXTPTR; + localparam [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL_REG = PF3_DPA_CAP_SUB_STATE_CONTROL; + localparam [40:1] PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF3_DPA_CAP_SUB_STATE_CONTROL_EN; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6; + localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7; + localparam [3:0] PF3_DPA_CAP_VER_REG = PF3_DPA_CAP_VER; + localparam [11:0] PF3_DSN_CAP_NEXTPTR_REG = PF3_DSN_CAP_NEXTPTR; + localparam [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE_REG = PF3_EXPANSION_ROM_APERTURE_SIZE; + localparam [40:1] PF3_EXPANSION_ROM_ENABLE_REG = PF3_EXPANSION_ROM_ENABLE; + localparam [7:0] PF3_INTERRUPT_LINE_REG = PF3_INTERRUPT_LINE; + localparam [2:0] PF3_INTERRUPT_PIN_REG = PF3_INTERRUPT_PIN; + localparam [7:0] PF3_MSIX_CAP_NEXTPTR_REG = PF3_MSIX_CAP_NEXTPTR; + localparam [2:0] PF3_MSIX_CAP_PBA_BIR_REG = PF3_MSIX_CAP_PBA_BIR; + localparam [28:0] PF3_MSIX_CAP_PBA_OFFSET_REG = PF3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] PF3_MSIX_CAP_TABLE_BIR_REG = PF3_MSIX_CAP_TABLE_BIR; + localparam [28:0] PF3_MSIX_CAP_TABLE_OFFSET_REG = PF3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] PF3_MSIX_CAP_TABLE_SIZE_REG = PF3_MSIX_CAP_TABLE_SIZE; + localparam [2:0] PF3_MSI_CAP_MULTIMSGCAP_REG = PF3_MSI_CAP_MULTIMSGCAP; + localparam [7:0] PF3_MSI_CAP_NEXTPTR_REG = PF3_MSI_CAP_NEXTPTR; + localparam [40:1] PF3_MSI_CAP_PERVECMASKCAP_REG = PF3_MSI_CAP_PERVECMASKCAP; + localparam [31:0] PF3_PB_CAP_DATA_REG_D0_REG = PF3_PB_CAP_DATA_REG_D0; + localparam [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF3_PB_CAP_DATA_REG_D0_SUSTAINED; + localparam [31:0] PF3_PB_CAP_DATA_REG_D1_REG = PF3_PB_CAP_DATA_REG_D1; + localparam [31:0] PF3_PB_CAP_DATA_REG_D3HOT_REG = PF3_PB_CAP_DATA_REG_D3HOT; + localparam [11:0] PF3_PB_CAP_NEXTPTR_REG = PF3_PB_CAP_NEXTPTR; + localparam [40:1] PF3_PB_CAP_SYSTEM_ALLOCATED_REG = PF3_PB_CAP_SYSTEM_ALLOCATED; + localparam [3:0] PF3_PB_CAP_VER_REG = PF3_PB_CAP_VER; + localparam [7:0] PF3_PM_CAP_ID_REG = PF3_PM_CAP_ID; + localparam [7:0] PF3_PM_CAP_NEXTPTR_REG = PF3_PM_CAP_NEXTPTR; + localparam [2:0] PF3_PM_CAP_VER_ID_REG = PF3_PM_CAP_VER_ID; + localparam [40:1] PF3_RBAR_CAP_ENABLE_REG = PF3_RBAR_CAP_ENABLE; + localparam [11:0] PF3_RBAR_CAP_NEXTPTR_REG = PF3_RBAR_CAP_NEXTPTR; + localparam [19:0] PF3_RBAR_CAP_SIZE0_REG = PF3_RBAR_CAP_SIZE0; + localparam [19:0] PF3_RBAR_CAP_SIZE1_REG = PF3_RBAR_CAP_SIZE1; + localparam [19:0] PF3_RBAR_CAP_SIZE2_REG = PF3_RBAR_CAP_SIZE2; + localparam [3:0] PF3_RBAR_CAP_VER_REG = PF3_RBAR_CAP_VER; + localparam [2:0] PF3_RBAR_CONTROL_INDEX0_REG = PF3_RBAR_CONTROL_INDEX0; + localparam [2:0] PF3_RBAR_CONTROL_INDEX1_REG = PF3_RBAR_CONTROL_INDEX1; + localparam [2:0] PF3_RBAR_CONTROL_INDEX2_REG = PF3_RBAR_CONTROL_INDEX2; + localparam [4:0] PF3_RBAR_CONTROL_SIZE0_REG = PF3_RBAR_CONTROL_SIZE0; + localparam [4:0] PF3_RBAR_CONTROL_SIZE1_REG = PF3_RBAR_CONTROL_SIZE1; + localparam [4:0] PF3_RBAR_CONTROL_SIZE2_REG = PF3_RBAR_CONTROL_SIZE2; + localparam [2:0] PF3_RBAR_NUM_REG = PF3_RBAR_NUM; + localparam [7:0] PF3_REVISION_ID_REG = PF3_REVISION_ID; + localparam [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE_REG = PF3_SRIOV_BAR0_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR0_CONTROL_REG = PF3_SRIOV_BAR0_CONTROL; + localparam [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE_REG = PF3_SRIOV_BAR1_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR1_CONTROL_REG = PF3_SRIOV_BAR1_CONTROL; + localparam [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE_REG = PF3_SRIOV_BAR2_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR2_CONTROL_REG = PF3_SRIOV_BAR2_CONTROL; + localparam [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE_REG = PF3_SRIOV_BAR3_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR3_CONTROL_REG = PF3_SRIOV_BAR3_CONTROL; + localparam [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE_REG = PF3_SRIOV_BAR4_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR4_CONTROL_REG = PF3_SRIOV_BAR4_CONTROL; + localparam [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE_REG = PF3_SRIOV_BAR5_APERTURE_SIZE; + localparam [2:0] PF3_SRIOV_BAR5_CONTROL_REG = PF3_SRIOV_BAR5_CONTROL; + localparam [15:0] PF3_SRIOV_CAP_INITIAL_VF_REG = PF3_SRIOV_CAP_INITIAL_VF; + localparam [11:0] PF3_SRIOV_CAP_NEXTPTR_REG = PF3_SRIOV_CAP_NEXTPTR; + localparam [15:0] PF3_SRIOV_CAP_TOTAL_VF_REG = PF3_SRIOV_CAP_TOTAL_VF; + localparam [3:0] PF3_SRIOV_CAP_VER_REG = PF3_SRIOV_CAP_VER; + localparam [15:0] PF3_SRIOV_FIRST_VF_OFFSET_REG = PF3_SRIOV_FIRST_VF_OFFSET; + localparam [15:0] PF3_SRIOV_FUNC_DEP_LINK_REG = PF3_SRIOV_FUNC_DEP_LINK; + localparam [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF3_SRIOV_SUPPORTED_PAGE_SIZE; + localparam [15:0] PF3_SRIOV_VF_DEVICE_ID_REG = PF3_SRIOV_VF_DEVICE_ID; + localparam [15:0] PF3_SUBSYSTEM_ID_REG = PF3_SUBSYSTEM_ID; + localparam [40:1] PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF3_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] PF3_TPHR_CAP_ENABLE_REG = PF3_TPHR_CAP_ENABLE; + localparam [40:1] PF3_TPHR_CAP_INT_VEC_MODE_REG = PF3_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] PF3_TPHR_CAP_NEXTPTR_REG = PF3_TPHR_CAP_NEXTPTR; + localparam [2:0] PF3_TPHR_CAP_ST_MODE_SEL_REG = PF3_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] PF3_TPHR_CAP_ST_TABLE_LOC_REG = PF3_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE_REG = PF3_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] PF3_TPHR_CAP_VER_REG = PF3_TPHR_CAP_VER; + localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3; + localparam [40:1] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG = PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2; + localparam [40:1] PL_DISABLE_EI_INFER_IN_L0_REG = PL_DISABLE_EI_INFER_IN_L0; + localparam [40:1] PL_DISABLE_GEN3_DC_BALANCE_REG = PL_DISABLE_GEN3_DC_BALANCE; + localparam [40:1] PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG = PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP; + localparam [40:1] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_FRAMING_ERROR; + localparam [40:1] PL_DISABLE_SCRAMBLING_REG = PL_DISABLE_SCRAMBLING; + localparam [40:1] PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG = PL_DISABLE_SYNC_HEADER_FRAMING_ERROR; + localparam [40:1] PL_DISABLE_UPCONFIG_CAPABLE_REG = PL_DISABLE_UPCONFIG_CAPABLE; + localparam [40:1] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG = PL_EQ_ADAPT_DISABLE_COEFF_CHECK; + localparam [40:1] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG = PL_EQ_ADAPT_DISABLE_PRESET_CHECK; + localparam [4:0] PL_EQ_ADAPT_ITER_COUNT_REG = PL_EQ_ADAPT_ITER_COUNT; + localparam [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG = PL_EQ_ADAPT_REJECT_RETRY_COUNT; + localparam [40:1] PL_EQ_BYPASS_PHASE23_REG = PL_EQ_BYPASS_PHASE23; + localparam [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT_REG = PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT; + localparam [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET_REG = PL_EQ_DEFAULT_GEN3_TX_PRESET; + localparam [40:1] PL_EQ_PHASE01_RX_ADAPT_REG = PL_EQ_PHASE01_RX_ADAPT; + localparam [40:1] PL_EQ_SHORT_ADAPT_PHASE_REG = PL_EQ_SHORT_ADAPT_PHASE; + localparam [15:0] PL_LANE0_EQ_CONTROL_REG = PL_LANE0_EQ_CONTROL; + localparam [15:0] PL_LANE1_EQ_CONTROL_REG = PL_LANE1_EQ_CONTROL; + localparam [15:0] PL_LANE2_EQ_CONTROL_REG = PL_LANE2_EQ_CONTROL; + localparam [15:0] PL_LANE3_EQ_CONTROL_REG = PL_LANE3_EQ_CONTROL; + localparam [15:0] PL_LANE4_EQ_CONTROL_REG = PL_LANE4_EQ_CONTROL; + localparam [15:0] PL_LANE5_EQ_CONTROL_REG = PL_LANE5_EQ_CONTROL; + localparam [15:0] PL_LANE6_EQ_CONTROL_REG = PL_LANE6_EQ_CONTROL; + localparam [15:0] PL_LANE7_EQ_CONTROL_REG = PL_LANE7_EQ_CONTROL; + localparam [2:0] PL_LINK_CAP_MAX_LINK_SPEED_REG = PL_LINK_CAP_MAX_LINK_SPEED; + localparam [3:0] PL_LINK_CAP_MAX_LINK_WIDTH_REG = PL_LINK_CAP_MAX_LINK_WIDTH; + localparam [7:0] PL_N_FTS_COMCLK_GEN1_REG = PL_N_FTS_COMCLK_GEN1; + localparam [7:0] PL_N_FTS_COMCLK_GEN2_REG = PL_N_FTS_COMCLK_GEN2; + localparam [7:0] PL_N_FTS_COMCLK_GEN3_REG = PL_N_FTS_COMCLK_GEN3; + localparam [7:0] PL_N_FTS_GEN1_REG = PL_N_FTS_GEN1; + localparam [7:0] PL_N_FTS_GEN2_REG = PL_N_FTS_GEN2; + localparam [7:0] PL_N_FTS_GEN3_REG = PL_N_FTS_GEN3; + localparam [40:1] PL_REPORT_ALL_PHY_ERRORS_REG = PL_REPORT_ALL_PHY_ERRORS; + localparam [40:1] PL_SIM_FAST_LINK_TRAINING_REG = PL_SIM_FAST_LINK_TRAINING; + localparam [40:1] PL_UPSTREAM_FACING_REG = PL_UPSTREAM_FACING; + localparam [15:0] PM_ASPML0S_TIMEOUT_REG = PM_ASPML0S_TIMEOUT; + localparam [19:0] PM_ASPML1_ENTRY_DELAY_REG = PM_ASPML1_ENTRY_DELAY; + localparam [40:1] PM_ENABLE_L23_ENTRY_REG = PM_ENABLE_L23_ENTRY; + localparam [40:1] PM_ENABLE_SLOT_POWER_CAPTURE_REG = PM_ENABLE_SLOT_POWER_CAPTURE; + localparam [31:0] PM_L1_REENTRY_DELAY_REG = PM_L1_REENTRY_DELAY; + localparam [19:0] PM_PME_SERVICE_TIMEOUT_DELAY_REG = PM_PME_SERVICE_TIMEOUT_DELAY; + localparam [15:0] PM_PME_TURNOFF_ACK_DELAY_REG = PM_PME_TURNOFF_ACK_DELAY; + localparam [31:0] SIM_JTAG_IDCODE_REG = SIM_JTAG_IDCODE; + localparam [24:1] SIM_VERSION_REG = SIM_VERSION; + localparam [0:0] SPARE_BIT0_REG = SPARE_BIT0; + localparam [0:0] SPARE_BIT1_REG = SPARE_BIT1; + localparam [0:0] SPARE_BIT2_REG = SPARE_BIT2; + localparam [0:0] SPARE_BIT3_REG = SPARE_BIT3; + localparam [0:0] SPARE_BIT4_REG = SPARE_BIT4; + localparam [0:0] SPARE_BIT5_REG = SPARE_BIT5; + localparam [0:0] SPARE_BIT6_REG = SPARE_BIT6; + localparam [0:0] SPARE_BIT7_REG = SPARE_BIT7; + localparam [0:0] SPARE_BIT8_REG = SPARE_BIT8; + localparam [7:0] SPARE_BYTE0_REG = SPARE_BYTE0; + localparam [7:0] SPARE_BYTE1_REG = SPARE_BYTE1; + localparam [7:0] SPARE_BYTE2_REG = SPARE_BYTE2; + localparam [7:0] SPARE_BYTE3_REG = SPARE_BYTE3; + localparam [31:0] SPARE_WORD0_REG = SPARE_WORD0; + localparam [31:0] SPARE_WORD1_REG = SPARE_WORD1; + localparam [31:0] SPARE_WORD2_REG = SPARE_WORD2; + localparam [31:0] SPARE_WORD3_REG = SPARE_WORD3; + localparam [40:1] SRIOV_CAP_ENABLE_REG = SRIOV_CAP_ENABLE; + localparam [40:1] TL_COMPLETION_RAM_SIZE_16K_REG = TL_COMPLETION_RAM_SIZE_16K; + localparam [23:0] TL_COMPL_TIMEOUT_REG0_REG = TL_COMPL_TIMEOUT_REG0; + localparam [27:0] TL_COMPL_TIMEOUT_REG1_REG = TL_COMPL_TIMEOUT_REG1; + localparam [11:0] TL_CREDITS_CD_REG = TL_CREDITS_CD; + localparam [7:0] TL_CREDITS_CH_REG = TL_CREDITS_CH; + localparam [11:0] TL_CREDITS_NPD_REG = TL_CREDITS_NPD; + localparam [7:0] TL_CREDITS_NPH_REG = TL_CREDITS_NPH; + localparam [11:0] TL_CREDITS_PD_REG = TL_CREDITS_PD; + localparam [7:0] TL_CREDITS_PH_REG = TL_CREDITS_PH; + localparam [40:1] TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG = TL_ENABLE_MESSAGE_RID_CHECK_ENABLE; + localparam [40:1] TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG = TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE; + localparam [40:1] TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG = TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE; + localparam [40:1] TL_LEGACY_MODE_ENABLE_REG = TL_LEGACY_MODE_ENABLE; + localparam [1:0] TL_PF_ENABLE_REG_REG = TL_PF_ENABLE_REG; + localparam [40:1] TL_TX_MUX_STRICT_PRIORITY_REG = TL_TX_MUX_STRICT_PRIORITY; + localparam [40:1] TWO_LAYER_MODE_DLCMSM_ENABLE_REG = TWO_LAYER_MODE_DLCMSM_ENABLE; + localparam [40:1] TWO_LAYER_MODE_ENABLE_REG = TWO_LAYER_MODE_ENABLE; + localparam [40:1] TWO_LAYER_MODE_WIDTH_256_REG = TWO_LAYER_MODE_WIDTH_256; + localparam [11:0] VF0_ARI_CAP_NEXTPTR_REG = VF0_ARI_CAP_NEXTPTR; + localparam [7:0] VF0_CAPABILITY_POINTER_REG = VF0_CAPABILITY_POINTER; + localparam [2:0] VF0_MSIX_CAP_PBA_BIR_REG = VF0_MSIX_CAP_PBA_BIR; + localparam [28:0] VF0_MSIX_CAP_PBA_OFFSET_REG = VF0_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF0_MSIX_CAP_TABLE_BIR_REG = VF0_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF0_MSIX_CAP_TABLE_OFFSET_REG = VF0_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF0_MSIX_CAP_TABLE_SIZE_REG = VF0_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF0_MSI_CAP_MULTIMSGCAP_REG = VF0_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF0_PM_CAP_ID_REG = VF0_PM_CAP_ID; + localparam [7:0] VF0_PM_CAP_NEXTPTR_REG = VF0_PM_CAP_NEXTPTR; + localparam [2:0] VF0_PM_CAP_VER_ID_REG = VF0_PM_CAP_VER_ID; + localparam [40:1] VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF0_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF0_TPHR_CAP_ENABLE_REG = VF0_TPHR_CAP_ENABLE; + localparam [40:1] VF0_TPHR_CAP_INT_VEC_MODE_REG = VF0_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF0_TPHR_CAP_NEXTPTR_REG = VF0_TPHR_CAP_NEXTPTR; + localparam [2:0] VF0_TPHR_CAP_ST_MODE_SEL_REG = VF0_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF0_TPHR_CAP_ST_TABLE_LOC_REG = VF0_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE_REG = VF0_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF0_TPHR_CAP_VER_REG = VF0_TPHR_CAP_VER; + localparam [11:0] VF1_ARI_CAP_NEXTPTR_REG = VF1_ARI_CAP_NEXTPTR; + localparam [2:0] VF1_MSIX_CAP_PBA_BIR_REG = VF1_MSIX_CAP_PBA_BIR; + localparam [28:0] VF1_MSIX_CAP_PBA_OFFSET_REG = VF1_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF1_MSIX_CAP_TABLE_BIR_REG = VF1_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF1_MSIX_CAP_TABLE_OFFSET_REG = VF1_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF1_MSIX_CAP_TABLE_SIZE_REG = VF1_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF1_MSI_CAP_MULTIMSGCAP_REG = VF1_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF1_PM_CAP_ID_REG = VF1_PM_CAP_ID; + localparam [7:0] VF1_PM_CAP_NEXTPTR_REG = VF1_PM_CAP_NEXTPTR; + localparam [2:0] VF1_PM_CAP_VER_ID_REG = VF1_PM_CAP_VER_ID; + localparam [40:1] VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF1_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF1_TPHR_CAP_ENABLE_REG = VF1_TPHR_CAP_ENABLE; + localparam [40:1] VF1_TPHR_CAP_INT_VEC_MODE_REG = VF1_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF1_TPHR_CAP_NEXTPTR_REG = VF1_TPHR_CAP_NEXTPTR; + localparam [2:0] VF1_TPHR_CAP_ST_MODE_SEL_REG = VF1_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF1_TPHR_CAP_ST_TABLE_LOC_REG = VF1_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE_REG = VF1_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF1_TPHR_CAP_VER_REG = VF1_TPHR_CAP_VER; + localparam [11:0] VF2_ARI_CAP_NEXTPTR_REG = VF2_ARI_CAP_NEXTPTR; + localparam [2:0] VF2_MSIX_CAP_PBA_BIR_REG = VF2_MSIX_CAP_PBA_BIR; + localparam [28:0] VF2_MSIX_CAP_PBA_OFFSET_REG = VF2_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF2_MSIX_CAP_TABLE_BIR_REG = VF2_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF2_MSIX_CAP_TABLE_OFFSET_REG = VF2_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF2_MSIX_CAP_TABLE_SIZE_REG = VF2_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF2_MSI_CAP_MULTIMSGCAP_REG = VF2_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF2_PM_CAP_ID_REG = VF2_PM_CAP_ID; + localparam [7:0] VF2_PM_CAP_NEXTPTR_REG = VF2_PM_CAP_NEXTPTR; + localparam [2:0] VF2_PM_CAP_VER_ID_REG = VF2_PM_CAP_VER_ID; + localparam [40:1] VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF2_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF2_TPHR_CAP_ENABLE_REG = VF2_TPHR_CAP_ENABLE; + localparam [40:1] VF2_TPHR_CAP_INT_VEC_MODE_REG = VF2_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF2_TPHR_CAP_NEXTPTR_REG = VF2_TPHR_CAP_NEXTPTR; + localparam [2:0] VF2_TPHR_CAP_ST_MODE_SEL_REG = VF2_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF2_TPHR_CAP_ST_TABLE_LOC_REG = VF2_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE_REG = VF2_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF2_TPHR_CAP_VER_REG = VF2_TPHR_CAP_VER; + localparam [11:0] VF3_ARI_CAP_NEXTPTR_REG = VF3_ARI_CAP_NEXTPTR; + localparam [2:0] VF3_MSIX_CAP_PBA_BIR_REG = VF3_MSIX_CAP_PBA_BIR; + localparam [28:0] VF3_MSIX_CAP_PBA_OFFSET_REG = VF3_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF3_MSIX_CAP_TABLE_BIR_REG = VF3_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF3_MSIX_CAP_TABLE_OFFSET_REG = VF3_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF3_MSIX_CAP_TABLE_SIZE_REG = VF3_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF3_MSI_CAP_MULTIMSGCAP_REG = VF3_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF3_PM_CAP_ID_REG = VF3_PM_CAP_ID; + localparam [7:0] VF3_PM_CAP_NEXTPTR_REG = VF3_PM_CAP_NEXTPTR; + localparam [2:0] VF3_PM_CAP_VER_ID_REG = VF3_PM_CAP_VER_ID; + localparam [40:1] VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF3_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF3_TPHR_CAP_ENABLE_REG = VF3_TPHR_CAP_ENABLE; + localparam [40:1] VF3_TPHR_CAP_INT_VEC_MODE_REG = VF3_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF3_TPHR_CAP_NEXTPTR_REG = VF3_TPHR_CAP_NEXTPTR; + localparam [2:0] VF3_TPHR_CAP_ST_MODE_SEL_REG = VF3_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF3_TPHR_CAP_ST_TABLE_LOC_REG = VF3_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE_REG = VF3_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF3_TPHR_CAP_VER_REG = VF3_TPHR_CAP_VER; + localparam [11:0] VF4_ARI_CAP_NEXTPTR_REG = VF4_ARI_CAP_NEXTPTR; + localparam [2:0] VF4_MSIX_CAP_PBA_BIR_REG = VF4_MSIX_CAP_PBA_BIR; + localparam [28:0] VF4_MSIX_CAP_PBA_OFFSET_REG = VF4_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF4_MSIX_CAP_TABLE_BIR_REG = VF4_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF4_MSIX_CAP_TABLE_OFFSET_REG = VF4_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF4_MSIX_CAP_TABLE_SIZE_REG = VF4_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF4_MSI_CAP_MULTIMSGCAP_REG = VF4_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF4_PM_CAP_ID_REG = VF4_PM_CAP_ID; + localparam [7:0] VF4_PM_CAP_NEXTPTR_REG = VF4_PM_CAP_NEXTPTR; + localparam [2:0] VF4_PM_CAP_VER_ID_REG = VF4_PM_CAP_VER_ID; + localparam [40:1] VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF4_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF4_TPHR_CAP_ENABLE_REG = VF4_TPHR_CAP_ENABLE; + localparam [40:1] VF4_TPHR_CAP_INT_VEC_MODE_REG = VF4_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF4_TPHR_CAP_NEXTPTR_REG = VF4_TPHR_CAP_NEXTPTR; + localparam [2:0] VF4_TPHR_CAP_ST_MODE_SEL_REG = VF4_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF4_TPHR_CAP_ST_TABLE_LOC_REG = VF4_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE_REG = VF4_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF4_TPHR_CAP_VER_REG = VF4_TPHR_CAP_VER; + localparam [11:0] VF5_ARI_CAP_NEXTPTR_REG = VF5_ARI_CAP_NEXTPTR; + localparam [2:0] VF5_MSIX_CAP_PBA_BIR_REG = VF5_MSIX_CAP_PBA_BIR; + localparam [28:0] VF5_MSIX_CAP_PBA_OFFSET_REG = VF5_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF5_MSIX_CAP_TABLE_BIR_REG = VF5_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF5_MSIX_CAP_TABLE_OFFSET_REG = VF5_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF5_MSIX_CAP_TABLE_SIZE_REG = VF5_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF5_MSI_CAP_MULTIMSGCAP_REG = VF5_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF5_PM_CAP_ID_REG = VF5_PM_CAP_ID; + localparam [7:0] VF5_PM_CAP_NEXTPTR_REG = VF5_PM_CAP_NEXTPTR; + localparam [2:0] VF5_PM_CAP_VER_ID_REG = VF5_PM_CAP_VER_ID; + localparam [40:1] VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF5_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF5_TPHR_CAP_ENABLE_REG = VF5_TPHR_CAP_ENABLE; + localparam [40:1] VF5_TPHR_CAP_INT_VEC_MODE_REG = VF5_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF5_TPHR_CAP_NEXTPTR_REG = VF5_TPHR_CAP_NEXTPTR; + localparam [2:0] VF5_TPHR_CAP_ST_MODE_SEL_REG = VF5_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF5_TPHR_CAP_ST_TABLE_LOC_REG = VF5_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE_REG = VF5_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF5_TPHR_CAP_VER_REG = VF5_TPHR_CAP_VER; + localparam [11:0] VF6_ARI_CAP_NEXTPTR_REG = VF6_ARI_CAP_NEXTPTR; + localparam [2:0] VF6_MSIX_CAP_PBA_BIR_REG = VF6_MSIX_CAP_PBA_BIR; + localparam [28:0] VF6_MSIX_CAP_PBA_OFFSET_REG = VF6_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF6_MSIX_CAP_TABLE_BIR_REG = VF6_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF6_MSIX_CAP_TABLE_OFFSET_REG = VF6_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF6_MSIX_CAP_TABLE_SIZE_REG = VF6_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF6_MSI_CAP_MULTIMSGCAP_REG = VF6_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF6_PM_CAP_ID_REG = VF6_PM_CAP_ID; + localparam [7:0] VF6_PM_CAP_NEXTPTR_REG = VF6_PM_CAP_NEXTPTR; + localparam [2:0] VF6_PM_CAP_VER_ID_REG = VF6_PM_CAP_VER_ID; + localparam [40:1] VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF6_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF6_TPHR_CAP_ENABLE_REG = VF6_TPHR_CAP_ENABLE; + localparam [40:1] VF6_TPHR_CAP_INT_VEC_MODE_REG = VF6_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF6_TPHR_CAP_NEXTPTR_REG = VF6_TPHR_CAP_NEXTPTR; + localparam [2:0] VF6_TPHR_CAP_ST_MODE_SEL_REG = VF6_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF6_TPHR_CAP_ST_TABLE_LOC_REG = VF6_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE_REG = VF6_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF6_TPHR_CAP_VER_REG = VF6_TPHR_CAP_VER; + localparam [11:0] VF7_ARI_CAP_NEXTPTR_REG = VF7_ARI_CAP_NEXTPTR; + localparam [2:0] VF7_MSIX_CAP_PBA_BIR_REG = VF7_MSIX_CAP_PBA_BIR; + localparam [28:0] VF7_MSIX_CAP_PBA_OFFSET_REG = VF7_MSIX_CAP_PBA_OFFSET; + localparam [2:0] VF7_MSIX_CAP_TABLE_BIR_REG = VF7_MSIX_CAP_TABLE_BIR; + localparam [28:0] VF7_MSIX_CAP_TABLE_OFFSET_REG = VF7_MSIX_CAP_TABLE_OFFSET; + localparam [10:0] VF7_MSIX_CAP_TABLE_SIZE_REG = VF7_MSIX_CAP_TABLE_SIZE; + localparam [2:0] VF7_MSI_CAP_MULTIMSGCAP_REG = VF7_MSI_CAP_MULTIMSGCAP; + localparam [7:0] VF7_PM_CAP_ID_REG = VF7_PM_CAP_ID; + localparam [7:0] VF7_PM_CAP_NEXTPTR_REG = VF7_PM_CAP_NEXTPTR; + localparam [2:0] VF7_PM_CAP_VER_ID_REG = VF7_PM_CAP_VER_ID; + localparam [40:1] VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF7_TPHR_CAP_DEV_SPECIFIC_MODE; + localparam [40:1] VF7_TPHR_CAP_ENABLE_REG = VF7_TPHR_CAP_ENABLE; + localparam [40:1] VF7_TPHR_CAP_INT_VEC_MODE_REG = VF7_TPHR_CAP_INT_VEC_MODE; + localparam [11:0] VF7_TPHR_CAP_NEXTPTR_REG = VF7_TPHR_CAP_NEXTPTR; + localparam [2:0] VF7_TPHR_CAP_ST_MODE_SEL_REG = VF7_TPHR_CAP_ST_MODE_SEL; + localparam [1:0] VF7_TPHR_CAP_ST_TABLE_LOC_REG = VF7_TPHR_CAP_ST_TABLE_LOC; + localparam [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE_REG = VF7_TPHR_CAP_ST_TABLE_SIZE; + localparam [3:0] VF7_TPHR_CAP_VER_REG = VF7_TPHR_CAP_VER; + `endif + + localparam [40:1] TEST_MODE_PIN_CHAR_REG = "FALSE"; + + tri0 glblGSR = glbl.GSR; + + `ifdef XIL_TIMING //Simprim + reg notifier; + `endif + reg trig_attr = 1'b0; + reg attr_err = 1'b0; + +// include dynamic registers - XILINX test only + `ifdef XIL_DR + `include "PCIE_3_1_dr.v" + `endif + + wire CFGERRCOROUT_out; + wire CFGERRFATALOUT_out; + wire CFGERRNONFATALOUT_out; + wire CFGEXTREADRECEIVED_out; + wire CFGEXTWRITERECEIVED_out; + wire CFGHOTRESETOUT_out; + wire CFGINTERRUPTMSIFAIL_out; + wire CFGINTERRUPTMSIMASKUPDATE_out; + wire CFGINTERRUPTMSISENT_out; + wire CFGINTERRUPTMSIXFAIL_out; + wire CFGINTERRUPTMSIXSENT_out; + wire CFGINTERRUPTSENT_out; + wire CFGLOCALERROR_out; + wire CFGLTRENABLE_out; + wire CFGMGMTREADWRITEDONE_out; + wire CFGMSGRECEIVED_out; + wire CFGMSGTRANSMITDONE_out; + wire CFGPERFUNCTIONUPDATEDONE_out; + wire CFGPHYLINKDOWN_out; + wire CFGPLSTATUSCHANGE_out; + wire CFGPOWERSTATECHANGEINTERRUPT_out; + wire CFGTPHSTTREADENABLE_out; + wire CFGTPHSTTWRITEENABLE_out; + wire CONFMCAPDESIGNSWITCH_out; + wire CONFMCAPEOS_out; + wire CONFMCAPINUSEBYPCIE_out; + wire CONFREQREADY_out; + wire CONFRESPVALID_out; + wire DBGMCAPCSB_out; + wire DBGMCAPEOS_out; + wire DBGMCAPERROR_out; + wire DBGMCAPMODE_out; + wire DBGMCAPRDATAVALID_out; + wire DBGMCAPRDWRB_out; + wire DBGMCAPRESET_out; + wire DBGPLDATABLOCKRECEIVEDAFTEREDS_out; + wire DBGPLGEN3FRAMINGERRORDETECTED_out; + wire DBGPLGEN3SYNCHEADERERRORDETECTED_out; + wire DRPRDY_out; + wire LL2LMMASTERTLPSENT0_out; + wire LL2LMMASTERTLPSENT1_out; + wire MAXISCQTLAST_out; + wire MAXISCQTVALID_out; + wire MAXISRCTLAST_out; + wire MAXISRCTVALID_out; + wire PCIEPERST0B_out; + wire PCIEPERST1B_out; + wire PCIERQSEQNUMVLD_out; + wire PCIERQTAGVLD_out; + wire PIPERX0POLARITY_out; + wire PIPERX1POLARITY_out; + wire PIPERX2POLARITY_out; + wire PIPERX3POLARITY_out; + wire PIPERX4POLARITY_out; + wire PIPERX5POLARITY_out; + wire PIPERX6POLARITY_out; + wire PIPERX7POLARITY_out; + wire PIPETX0COMPLIANCE_out; + wire PIPETX0DATAVALID_out; + wire PIPETX0DEEMPH_out; + wire PIPETX0ELECIDLE_out; + wire PIPETX0RCVRDET_out; + wire PIPETX0RESET_out; + wire PIPETX0STARTBLOCK_out; + wire PIPETX0SWING_out; + wire PIPETX1COMPLIANCE_out; + wire PIPETX1DATAVALID_out; + wire PIPETX1DEEMPH_out; + wire PIPETX1ELECIDLE_out; + wire PIPETX1RCVRDET_out; + wire PIPETX1RESET_out; + wire PIPETX1STARTBLOCK_out; + wire PIPETX1SWING_out; + wire PIPETX2COMPLIANCE_out; + wire PIPETX2DATAVALID_out; + wire PIPETX2DEEMPH_out; + wire PIPETX2ELECIDLE_out; + wire PIPETX2RCVRDET_out; + wire PIPETX2RESET_out; + wire PIPETX2STARTBLOCK_out; + wire PIPETX2SWING_out; + wire PIPETX3COMPLIANCE_out; + wire PIPETX3DATAVALID_out; + wire PIPETX3DEEMPH_out; + wire PIPETX3ELECIDLE_out; + wire PIPETX3RCVRDET_out; + wire PIPETX3RESET_out; + wire PIPETX3STARTBLOCK_out; + wire PIPETX3SWING_out; + wire PIPETX4COMPLIANCE_out; + wire PIPETX4DATAVALID_out; + wire PIPETX4DEEMPH_out; + wire PIPETX4ELECIDLE_out; + wire PIPETX4RCVRDET_out; + wire PIPETX4RESET_out; + wire PIPETX4STARTBLOCK_out; + wire PIPETX4SWING_out; + wire PIPETX5COMPLIANCE_out; + wire PIPETX5DATAVALID_out; + wire PIPETX5DEEMPH_out; + wire PIPETX5ELECIDLE_out; + wire PIPETX5RCVRDET_out; + wire PIPETX5RESET_out; + wire PIPETX5STARTBLOCK_out; + wire PIPETX5SWING_out; + wire PIPETX6COMPLIANCE_out; + wire PIPETX6DATAVALID_out; + wire PIPETX6DEEMPH_out; + wire PIPETX6ELECIDLE_out; + wire PIPETX6RCVRDET_out; + wire PIPETX6RESET_out; + wire PIPETX6STARTBLOCK_out; + wire PIPETX6SWING_out; + wire PIPETX7COMPLIANCE_out; + wire PIPETX7DATAVALID_out; + wire PIPETX7DEEMPH_out; + wire PIPETX7ELECIDLE_out; + wire PIPETX7RCVRDET_out; + wire PIPETX7RESET_out; + wire PIPETX7STARTBLOCK_out; + wire PIPETX7SWING_out; + wire PLEQINPROGRESS_out; + wire PMVOUT_out; + wire [11:0] CFGFCCPLD_out; + wire [11:0] CFGFCNPD_out; + wire [11:0] CFGFCPD_out; + wire [11:0] CFGFUNCTIONPOWERSTATE_out; + wire [11:0] CFGINTERRUPTMSIMMENABLE_out; + wire [11:0] CFGTPHSTMODE_out; + wire [143:0] MIREPLAYRAMWRITEDATA_out; + wire [143:0] MIREQUESTRAMWRITEDATA_out; + wire [15:0] CFGFUNCTIONSTATUS_out; + wire [15:0] CFGPERFUNCSTATUSDATA_out; + wire [15:0] CFGVFSTATUS_out; + wire [15:0] DBGDATAOUT_out; + wire [15:0] DRPDO_out; + wire [17:0] LL2LMMAXISRXTUSER_out; + wire [1:0] CFGLINKPOWERSTATE_out; + wire [1:0] CFGOBFFENABLE_out; + wire [1:0] CFGPHYLINKSTATUS_out; + wire [1:0] MIREPLAYRAMREADENABLE_out; + wire [1:0] MIREPLAYRAMWRITEENABLE_out; + wire [1:0] PCIERQTAGAV_out; + wire [1:0] PCIETFCNPDAV_out; + wire [1:0] PCIETFCNPHAV_out; + wire [1:0] PIPERX0EQCONTROL_out; + wire [1:0] PIPERX1EQCONTROL_out; + wire [1:0] PIPERX2EQCONTROL_out; + wire [1:0] PIPERX3EQCONTROL_out; + wire [1:0] PIPERX4EQCONTROL_out; + wire [1:0] PIPERX5EQCONTROL_out; + wire [1:0] PIPERX6EQCONTROL_out; + wire [1:0] PIPERX7EQCONTROL_out; + wire [1:0] PIPETX0CHARISK_out; + wire [1:0] PIPETX0EQCONTROL_out; + wire [1:0] PIPETX0POWERDOWN_out; + wire [1:0] PIPETX0RATE_out; + wire [1:0] PIPETX0SYNCHEADER_out; + wire [1:0] PIPETX1CHARISK_out; + wire [1:0] PIPETX1EQCONTROL_out; + wire [1:0] PIPETX1POWERDOWN_out; + wire [1:0] PIPETX1RATE_out; + wire [1:0] PIPETX1SYNCHEADER_out; + wire [1:0] PIPETX2CHARISK_out; + wire [1:0] PIPETX2EQCONTROL_out; + wire [1:0] PIPETX2POWERDOWN_out; + wire [1:0] PIPETX2RATE_out; + wire [1:0] PIPETX2SYNCHEADER_out; + wire [1:0] PIPETX3CHARISK_out; + wire [1:0] PIPETX3EQCONTROL_out; + wire [1:0] PIPETX3POWERDOWN_out; + wire [1:0] PIPETX3RATE_out; + wire [1:0] PIPETX3SYNCHEADER_out; + wire [1:0] PIPETX4CHARISK_out; + wire [1:0] PIPETX4EQCONTROL_out; + wire [1:0] PIPETX4POWERDOWN_out; + wire [1:0] PIPETX4RATE_out; + wire [1:0] PIPETX4SYNCHEADER_out; + wire [1:0] PIPETX5CHARISK_out; + wire [1:0] PIPETX5EQCONTROL_out; + wire [1:0] PIPETX5POWERDOWN_out; + wire [1:0] PIPETX5RATE_out; + wire [1:0] PIPETX5SYNCHEADER_out; + wire [1:0] PIPETX6CHARISK_out; + wire [1:0] PIPETX6EQCONTROL_out; + wire [1:0] PIPETX6POWERDOWN_out; + wire [1:0] PIPETX6RATE_out; + wire [1:0] PIPETX6SYNCHEADER_out; + wire [1:0] PIPETX7CHARISK_out; + wire [1:0] PIPETX7EQCONTROL_out; + wire [1:0] PIPETX7POWERDOWN_out; + wire [1:0] PIPETX7RATE_out; + wire [1:0] PIPETX7SYNCHEADER_out; + wire [1:0] PLEQPHASE_out; + wire [23:0] CFGVFPOWERSTATE_out; + wire [23:0] CFGVFTPHSTMODE_out; + wire [255:0] LL2LMMAXISRXTDATA_out; + wire [255:0] MAXISCQTDATA_out; + wire [255:0] MAXISRCTDATA_out; + wire [2:0] CFGCURRENTSPEED_out; + wire [2:0] CFGMAXPAYLOAD_out; + wire [2:0] CFGMAXREADREQ_out; + wire [2:0] PIPERX0EQPRESET_out; + wire [2:0] PIPERX1EQPRESET_out; + wire [2:0] PIPERX2EQPRESET_out; + wire [2:0] PIPERX3EQPRESET_out; + wire [2:0] PIPERX4EQPRESET_out; + wire [2:0] PIPERX5EQPRESET_out; + wire [2:0] PIPERX6EQPRESET_out; + wire [2:0] PIPERX7EQPRESET_out; + wire [2:0] PIPETX0MARGIN_out; + wire [2:0] PIPETX1MARGIN_out; + wire [2:0] PIPETX2MARGIN_out; + wire [2:0] PIPETX3MARGIN_out; + wire [2:0] PIPETX4MARGIN_out; + wire [2:0] PIPETX5MARGIN_out; + wire [2:0] PIPETX6MARGIN_out; + wire [2:0] PIPETX7MARGIN_out; + wire [31:0] CFGEXTWRITEDATA_out; + wire [31:0] CFGINTERRUPTMSIDATA_out; + wire [31:0] CFGMGMTREADDATA_out; + wire [31:0] CFGTPHSTTWRITEDATA_out; + wire [31:0] CONFRESPRDATA_out; + wire [31:0] DBGMCAPDATA_out; + wire [31:0] PIPETX0DATA_out; + wire [31:0] PIPETX1DATA_out; + wire [31:0] PIPETX2DATA_out; + wire [31:0] PIPETX3DATA_out; + wire [31:0] PIPETX4DATA_out; + wire [31:0] PIPETX5DATA_out; + wire [31:0] PIPETX6DATA_out; + wire [31:0] PIPETX7DATA_out; + wire [31:0] SPAREOUT_out; + wire [3:0] CFGDPASUBSTATECHANGE_out; + wire [3:0] CFGEXTWRITEBYTEENABLE_out; + wire [3:0] CFGFLRINPROCESS_out; + wire [3:0] CFGINTERRUPTMSIENABLE_out; + wire [3:0] CFGINTERRUPTMSIXENABLE_out; + wire [3:0] CFGINTERRUPTMSIXMASK_out; + wire [3:0] CFGNEGOTIATEDWIDTH_out; + wire [3:0] CFGRCBSTATUS_out; + wire [3:0] CFGTPHFUNCTIONNUM_out; + wire [3:0] CFGTPHREQUESTERENABLE_out; + wire [3:0] CFGTPHSTTWRITEBYTEVALID_out; + wire [3:0] LL2LMMASTERTLPSENTTLPID0_out; + wire [3:0] LL2LMMASTERTLPSENTTLPID1_out; + wire [3:0] MICOMPLETIONRAMREADENABLEL_out; + wire [3:0] MICOMPLETIONRAMREADENABLEU_out; + wire [3:0] MICOMPLETIONRAMWRITEENABLEL_out; + wire [3:0] MICOMPLETIONRAMWRITEENABLEU_out; + wire [3:0] MIREQUESTRAMREADENABLE_out; + wire [3:0] MIREQUESTRAMWRITEENABLE_out; + wire [3:0] PCIERQSEQNUM_out; + wire [3:0] PIPERX0EQLPTXPRESET_out; + wire [3:0] PIPERX1EQLPTXPRESET_out; + wire [3:0] PIPERX2EQLPTXPRESET_out; + wire [3:0] PIPERX3EQLPTXPRESET_out; + wire [3:0] PIPERX4EQLPTXPRESET_out; + wire [3:0] PIPERX5EQLPTXPRESET_out; + wire [3:0] PIPERX6EQLPTXPRESET_out; + wire [3:0] PIPERX7EQLPTXPRESET_out; + wire [3:0] PIPETX0EQPRESET_out; + wire [3:0] PIPETX1EQPRESET_out; + wire [3:0] PIPETX2EQPRESET_out; + wire [3:0] PIPETX3EQPRESET_out; + wire [3:0] PIPETX4EQPRESET_out; + wire [3:0] PIPETX5EQPRESET_out; + wire [3:0] PIPETX6EQPRESET_out; + wire [3:0] PIPETX7EQPRESET_out; + wire [3:0] SAXISCCTREADY_out; + wire [3:0] SAXISRQTREADY_out; + wire [479:0] XILUNCONNBOUT_out; + wire [4:0] CFGMSGRECEIVEDTYPE_out; + wire [4:0] CFGTPHSTTADDRESS_out; + wire [5:0] CFGLTSSMSTATE_out; + wire [5:0] PCIECQNPREQCOUNT_out; + wire [5:0] PCIERQTAG_out; + wire [5:0] PIPERX0EQLPLFFS_out; + wire [5:0] PIPERX1EQLPLFFS_out; + wire [5:0] PIPERX2EQLPLFFS_out; + wire [5:0] PIPERX3EQLPLFFS_out; + wire [5:0] PIPERX4EQLPLFFS_out; + wire [5:0] PIPERX5EQLPLFFS_out; + wire [5:0] PIPERX6EQLPLFFS_out; + wire [5:0] PIPERX7EQLPLFFS_out; + wire [5:0] PIPETX0EQDEEMPH_out; + wire [5:0] PIPETX1EQDEEMPH_out; + wire [5:0] PIPETX2EQDEEMPH_out; + wire [5:0] PIPETX3EQDEEMPH_out; + wire [5:0] PIPETX4EQDEEMPH_out; + wire [5:0] PIPETX5EQDEEMPH_out; + wire [5:0] PIPETX6EQDEEMPH_out; + wire [5:0] PIPETX7EQDEEMPH_out; + wire [71:0] MICOMPLETIONRAMWRITEDATAL_out; + wire [71:0] MICOMPLETIONRAMWRITEDATAU_out; + wire [74:0] MAXISRCTUSER_out; + wire [7:0] CFGEXTFUNCTIONNUMBER_out; + wire [7:0] CFGFCCPLH_out; + wire [7:0] CFGFCNPH_out; + wire [7:0] CFGFCPH_out; + wire [7:0] CFGINTERRUPTMSIVFENABLE_out; + wire [7:0] CFGINTERRUPTMSIXVFENABLE_out; + wire [7:0] CFGINTERRUPTMSIXVFMASK_out; + wire [7:0] CFGMSGRECEIVEDDATA_out; + wire [7:0] CFGVFFLRINPROCESS_out; + wire [7:0] CFGVFTPHREQUESTERENABLE_out; + wire [7:0] DBGPLINFERREDRXELECTRICALIDLE_out; + wire [7:0] LL2LMMAXISRXTVALID_out; + wire [7:0] LL2LMSAXISTXTREADY_out; + wire [7:0] MAXISCQTKEEP_out; + wire [7:0] MAXISRCTKEEP_out; + wire [84:0] MAXISCQTUSER_out; + wire [860:0] XILUNCONNOUT_out; + wire [8:0] MIREPLAYRAMADDRESS_out; + wire [8:0] MIREQUESTRAMREADADDRESSA_out; + wire [8:0] MIREQUESTRAMREADADDRESSB_out; + wire [8:0] MIREQUESTRAMWRITEADDRESSA_out; + wire [8:0] MIREQUESTRAMWRITEADDRESSB_out; + wire [95:0] SCANOUT_out; + wire [9:0] CFGEXTREGISTERNUMBER_out; + wire [9:0] MICOMPLETIONRAMREADADDRESSAL_out; + wire [9:0] MICOMPLETIONRAMREADADDRESSAU_out; + wire [9:0] MICOMPLETIONRAMREADADDRESSBL_out; + wire [9:0] MICOMPLETIONRAMREADADDRESSBU_out; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSAL_out; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSAU_out; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSBL_out; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSBU_out; + + wire CFGERRCOROUT_delay; + wire CFGERRFATALOUT_delay; + wire CFGERRNONFATALOUT_delay; + wire CFGEXTREADRECEIVED_delay; + wire CFGEXTWRITERECEIVED_delay; + wire CFGHOTRESETOUT_delay; + wire CFGINTERRUPTMSIFAIL_delay; + wire CFGINTERRUPTMSIMASKUPDATE_delay; + wire CFGINTERRUPTMSISENT_delay; + wire CFGINTERRUPTMSIXFAIL_delay; + wire CFGINTERRUPTMSIXSENT_delay; + wire CFGINTERRUPTSENT_delay; + wire CFGLOCALERROR_delay; + wire CFGLTRENABLE_delay; + wire CFGMGMTREADWRITEDONE_delay; + wire CFGMSGRECEIVED_delay; + wire CFGMSGTRANSMITDONE_delay; + wire CFGPERFUNCTIONUPDATEDONE_delay; + wire CFGPHYLINKDOWN_delay; + wire CFGPLSTATUSCHANGE_delay; + wire CFGPOWERSTATECHANGEINTERRUPT_delay; + wire CFGTPHSTTREADENABLE_delay; + wire CFGTPHSTTWRITEENABLE_delay; + wire CONFMCAPDESIGNSWITCH_delay; + wire CONFMCAPEOS_delay; + wire CONFMCAPINUSEBYPCIE_delay; + wire CONFREQREADY_delay; + wire CONFRESPVALID_delay; + wire DBGMCAPCSB_delay; + wire DBGMCAPEOS_delay; + wire DBGMCAPERROR_delay; + wire DBGMCAPMODE_delay; + wire DBGMCAPRDATAVALID_delay; + wire DBGMCAPRDWRB_delay; + wire DBGMCAPRESET_delay; + wire DBGPLDATABLOCKRECEIVEDAFTEREDS_delay; + wire DBGPLGEN3FRAMINGERRORDETECTED_delay; + wire DBGPLGEN3SYNCHEADERERRORDETECTED_delay; + wire DRPRDY_delay; + wire LL2LMMASTERTLPSENT0_delay; + wire LL2LMMASTERTLPSENT1_delay; + wire MAXISCQTLAST_delay; + wire MAXISCQTVALID_delay; + wire MAXISRCTLAST_delay; + wire MAXISRCTVALID_delay; + wire PCIEPERST0B_delay; + wire PCIEPERST1B_delay; + wire PCIERQSEQNUMVLD_delay; + wire PCIERQTAGVLD_delay; + wire PIPERX0POLARITY_delay; + wire PIPERX1POLARITY_delay; + wire PIPERX2POLARITY_delay; + wire PIPERX3POLARITY_delay; + wire PIPERX4POLARITY_delay; + wire PIPERX5POLARITY_delay; + wire PIPERX6POLARITY_delay; + wire PIPERX7POLARITY_delay; + wire PIPETX0COMPLIANCE_delay; + wire PIPETX0DATAVALID_delay; + wire PIPETX0DEEMPH_delay; + wire PIPETX0ELECIDLE_delay; + wire PIPETX0RCVRDET_delay; + wire PIPETX0RESET_delay; + wire PIPETX0STARTBLOCK_delay; + wire PIPETX0SWING_delay; + wire PIPETX1COMPLIANCE_delay; + wire PIPETX1DATAVALID_delay; + wire PIPETX1DEEMPH_delay; + wire PIPETX1ELECIDLE_delay; + wire PIPETX1RCVRDET_delay; + wire PIPETX1RESET_delay; + wire PIPETX1STARTBLOCK_delay; + wire PIPETX1SWING_delay; + wire PIPETX2COMPLIANCE_delay; + wire PIPETX2DATAVALID_delay; + wire PIPETX2DEEMPH_delay; + wire PIPETX2ELECIDLE_delay; + wire PIPETX2RCVRDET_delay; + wire PIPETX2RESET_delay; + wire PIPETX2STARTBLOCK_delay; + wire PIPETX2SWING_delay; + wire PIPETX3COMPLIANCE_delay; + wire PIPETX3DATAVALID_delay; + wire PIPETX3DEEMPH_delay; + wire PIPETX3ELECIDLE_delay; + wire PIPETX3RCVRDET_delay; + wire PIPETX3RESET_delay; + wire PIPETX3STARTBLOCK_delay; + wire PIPETX3SWING_delay; + wire PIPETX4COMPLIANCE_delay; + wire PIPETX4DATAVALID_delay; + wire PIPETX4DEEMPH_delay; + wire PIPETX4ELECIDLE_delay; + wire PIPETX4RCVRDET_delay; + wire PIPETX4RESET_delay; + wire PIPETX4STARTBLOCK_delay; + wire PIPETX4SWING_delay; + wire PIPETX5COMPLIANCE_delay; + wire PIPETX5DATAVALID_delay; + wire PIPETX5DEEMPH_delay; + wire PIPETX5ELECIDLE_delay; + wire PIPETX5RCVRDET_delay; + wire PIPETX5RESET_delay; + wire PIPETX5STARTBLOCK_delay; + wire PIPETX5SWING_delay; + wire PIPETX6COMPLIANCE_delay; + wire PIPETX6DATAVALID_delay; + wire PIPETX6DEEMPH_delay; + wire PIPETX6ELECIDLE_delay; + wire PIPETX6RCVRDET_delay; + wire PIPETX6RESET_delay; + wire PIPETX6STARTBLOCK_delay; + wire PIPETX6SWING_delay; + wire PIPETX7COMPLIANCE_delay; + wire PIPETX7DATAVALID_delay; + wire PIPETX7DEEMPH_delay; + wire PIPETX7ELECIDLE_delay; + wire PIPETX7RCVRDET_delay; + wire PIPETX7RESET_delay; + wire PIPETX7STARTBLOCK_delay; + wire PIPETX7SWING_delay; + wire PLEQINPROGRESS_delay; + wire [11:0] CFGFCCPLD_delay; + wire [11:0] CFGFCNPD_delay; + wire [11:0] CFGFCPD_delay; + wire [11:0] CFGFUNCTIONPOWERSTATE_delay; + wire [11:0] CFGINTERRUPTMSIMMENABLE_delay; + wire [11:0] CFGTPHSTMODE_delay; + wire [143:0] MIREPLAYRAMWRITEDATA_delay; + wire [143:0] MIREQUESTRAMWRITEDATA_delay; + wire [15:0] CFGFUNCTIONSTATUS_delay; + wire [15:0] CFGPERFUNCSTATUSDATA_delay; + wire [15:0] CFGVFSTATUS_delay; + wire [15:0] DBGDATAOUT_delay; + wire [15:0] DRPDO_delay; + wire [17:0] LL2LMMAXISRXTUSER_delay; + wire [1:0] CFGLINKPOWERSTATE_delay; + wire [1:0] CFGOBFFENABLE_delay; + wire [1:0] CFGPHYLINKSTATUS_delay; + wire [1:0] MIREPLAYRAMREADENABLE_delay; + wire [1:0] MIREPLAYRAMWRITEENABLE_delay; + wire [1:0] PCIERQTAGAV_delay; + wire [1:0] PCIETFCNPDAV_delay; + wire [1:0] PCIETFCNPHAV_delay; + wire [1:0] PIPERX0EQCONTROL_delay; + wire [1:0] PIPERX1EQCONTROL_delay; + wire [1:0] PIPERX2EQCONTROL_delay; + wire [1:0] PIPERX3EQCONTROL_delay; + wire [1:0] PIPERX4EQCONTROL_delay; + wire [1:0] PIPERX5EQCONTROL_delay; + wire [1:0] PIPERX6EQCONTROL_delay; + wire [1:0] PIPERX7EQCONTROL_delay; + wire [1:0] PIPETX0CHARISK_delay; + wire [1:0] PIPETX0EQCONTROL_delay; + wire [1:0] PIPETX0POWERDOWN_delay; + wire [1:0] PIPETX0RATE_delay; + wire [1:0] PIPETX0SYNCHEADER_delay; + wire [1:0] PIPETX1CHARISK_delay; + wire [1:0] PIPETX1EQCONTROL_delay; + wire [1:0] PIPETX1POWERDOWN_delay; + wire [1:0] PIPETX1RATE_delay; + wire [1:0] PIPETX1SYNCHEADER_delay; + wire [1:0] PIPETX2CHARISK_delay; + wire [1:0] PIPETX2EQCONTROL_delay; + wire [1:0] PIPETX2POWERDOWN_delay; + wire [1:0] PIPETX2RATE_delay; + wire [1:0] PIPETX2SYNCHEADER_delay; + wire [1:0] PIPETX3CHARISK_delay; + wire [1:0] PIPETX3EQCONTROL_delay; + wire [1:0] PIPETX3POWERDOWN_delay; + wire [1:0] PIPETX3RATE_delay; + wire [1:0] PIPETX3SYNCHEADER_delay; + wire [1:0] PIPETX4CHARISK_delay; + wire [1:0] PIPETX4EQCONTROL_delay; + wire [1:0] PIPETX4POWERDOWN_delay; + wire [1:0] PIPETX4RATE_delay; + wire [1:0] PIPETX4SYNCHEADER_delay; + wire [1:0] PIPETX5CHARISK_delay; + wire [1:0] PIPETX5EQCONTROL_delay; + wire [1:0] PIPETX5POWERDOWN_delay; + wire [1:0] PIPETX5RATE_delay; + wire [1:0] PIPETX5SYNCHEADER_delay; + wire [1:0] PIPETX6CHARISK_delay; + wire [1:0] PIPETX6EQCONTROL_delay; + wire [1:0] PIPETX6POWERDOWN_delay; + wire [1:0] PIPETX6RATE_delay; + wire [1:0] PIPETX6SYNCHEADER_delay; + wire [1:0] PIPETX7CHARISK_delay; + wire [1:0] PIPETX7EQCONTROL_delay; + wire [1:0] PIPETX7POWERDOWN_delay; + wire [1:0] PIPETX7RATE_delay; + wire [1:0] PIPETX7SYNCHEADER_delay; + wire [1:0] PLEQPHASE_delay; + wire [23:0] CFGVFPOWERSTATE_delay; + wire [23:0] CFGVFTPHSTMODE_delay; + wire [255:0] LL2LMMAXISRXTDATA_delay; + wire [255:0] MAXISCQTDATA_delay; + wire [255:0] MAXISRCTDATA_delay; + wire [2:0] CFGCURRENTSPEED_delay; + wire [2:0] CFGMAXPAYLOAD_delay; + wire [2:0] CFGMAXREADREQ_delay; + wire [2:0] PIPERX0EQPRESET_delay; + wire [2:0] PIPERX1EQPRESET_delay; + wire [2:0] PIPERX2EQPRESET_delay; + wire [2:0] PIPERX3EQPRESET_delay; + wire [2:0] PIPERX4EQPRESET_delay; + wire [2:0] PIPERX5EQPRESET_delay; + wire [2:0] PIPERX6EQPRESET_delay; + wire [2:0] PIPERX7EQPRESET_delay; + wire [2:0] PIPETX0MARGIN_delay; + wire [2:0] PIPETX1MARGIN_delay; + wire [2:0] PIPETX2MARGIN_delay; + wire [2:0] PIPETX3MARGIN_delay; + wire [2:0] PIPETX4MARGIN_delay; + wire [2:0] PIPETX5MARGIN_delay; + wire [2:0] PIPETX6MARGIN_delay; + wire [2:0] PIPETX7MARGIN_delay; + wire [31:0] CFGEXTWRITEDATA_delay; + wire [31:0] CFGINTERRUPTMSIDATA_delay; + wire [31:0] CFGMGMTREADDATA_delay; + wire [31:0] CFGTPHSTTWRITEDATA_delay; + wire [31:0] CONFRESPRDATA_delay; + wire [31:0] DBGMCAPDATA_delay; + wire [31:0] PIPETX0DATA_delay; + wire [31:0] PIPETX1DATA_delay; + wire [31:0] PIPETX2DATA_delay; + wire [31:0] PIPETX3DATA_delay; + wire [31:0] PIPETX4DATA_delay; + wire [31:0] PIPETX5DATA_delay; + wire [31:0] PIPETX6DATA_delay; + wire [31:0] PIPETX7DATA_delay; + wire [31:0] SPAREOUT_delay; + wire [3:0] CFGDPASUBSTATECHANGE_delay; + wire [3:0] CFGEXTWRITEBYTEENABLE_delay; + wire [3:0] CFGFLRINPROCESS_delay; + wire [3:0] CFGINTERRUPTMSIENABLE_delay; + wire [3:0] CFGINTERRUPTMSIXENABLE_delay; + wire [3:0] CFGINTERRUPTMSIXMASK_delay; + wire [3:0] CFGNEGOTIATEDWIDTH_delay; + wire [3:0] CFGRCBSTATUS_delay; + wire [3:0] CFGTPHFUNCTIONNUM_delay; + wire [3:0] CFGTPHREQUESTERENABLE_delay; + wire [3:0] CFGTPHSTTWRITEBYTEVALID_delay; + wire [3:0] LL2LMMASTERTLPSENTTLPID0_delay; + wire [3:0] LL2LMMASTERTLPSENTTLPID1_delay; + wire [3:0] MICOMPLETIONRAMREADENABLEL_delay; + wire [3:0] MICOMPLETIONRAMREADENABLEU_delay; + wire [3:0] MICOMPLETIONRAMWRITEENABLEL_delay; + wire [3:0] MICOMPLETIONRAMWRITEENABLEU_delay; + wire [3:0] MIREQUESTRAMREADENABLE_delay; + wire [3:0] MIREQUESTRAMWRITEENABLE_delay; + wire [3:0] PCIERQSEQNUM_delay; + wire [3:0] PIPERX0EQLPTXPRESET_delay; + wire [3:0] PIPERX1EQLPTXPRESET_delay; + wire [3:0] PIPERX2EQLPTXPRESET_delay; + wire [3:0] PIPERX3EQLPTXPRESET_delay; + wire [3:0] PIPERX4EQLPTXPRESET_delay; + wire [3:0] PIPERX5EQLPTXPRESET_delay; + wire [3:0] PIPERX6EQLPTXPRESET_delay; + wire [3:0] PIPERX7EQLPTXPRESET_delay; + wire [3:0] PIPETX0EQPRESET_delay; + wire [3:0] PIPETX1EQPRESET_delay; + wire [3:0] PIPETX2EQPRESET_delay; + wire [3:0] PIPETX3EQPRESET_delay; + wire [3:0] PIPETX4EQPRESET_delay; + wire [3:0] PIPETX5EQPRESET_delay; + wire [3:0] PIPETX6EQPRESET_delay; + wire [3:0] PIPETX7EQPRESET_delay; + wire [3:0] SAXISCCTREADY_delay; + wire [3:0] SAXISRQTREADY_delay; + wire [4:0] CFGMSGRECEIVEDTYPE_delay; + wire [4:0] CFGTPHSTTADDRESS_delay; + wire [5:0] CFGLTSSMSTATE_delay; + wire [5:0] PCIECQNPREQCOUNT_delay; + wire [5:0] PCIERQTAG_delay; + wire [5:0] PIPERX0EQLPLFFS_delay; + wire [5:0] PIPERX1EQLPLFFS_delay; + wire [5:0] PIPERX2EQLPLFFS_delay; + wire [5:0] PIPERX3EQLPLFFS_delay; + wire [5:0] PIPERX4EQLPLFFS_delay; + wire [5:0] PIPERX5EQLPLFFS_delay; + wire [5:0] PIPERX6EQLPLFFS_delay; + wire [5:0] PIPERX7EQLPLFFS_delay; + wire [5:0] PIPETX0EQDEEMPH_delay; + wire [5:0] PIPETX1EQDEEMPH_delay; + wire [5:0] PIPETX2EQDEEMPH_delay; + wire [5:0] PIPETX3EQDEEMPH_delay; + wire [5:0] PIPETX4EQDEEMPH_delay; + wire [5:0] PIPETX5EQDEEMPH_delay; + wire [5:0] PIPETX6EQDEEMPH_delay; + wire [5:0] PIPETX7EQDEEMPH_delay; + wire [71:0] MICOMPLETIONRAMWRITEDATAL_delay; + wire [71:0] MICOMPLETIONRAMWRITEDATAU_delay; + wire [74:0] MAXISRCTUSER_delay; + wire [7:0] CFGEXTFUNCTIONNUMBER_delay; + wire [7:0] CFGFCCPLH_delay; + wire [7:0] CFGFCNPH_delay; + wire [7:0] CFGFCPH_delay; + wire [7:0] CFGINTERRUPTMSIVFENABLE_delay; + wire [7:0] CFGINTERRUPTMSIXVFENABLE_delay; + wire [7:0] CFGINTERRUPTMSIXVFMASK_delay; + wire [7:0] CFGMSGRECEIVEDDATA_delay; + wire [7:0] CFGVFFLRINPROCESS_delay; + wire [7:0] CFGVFTPHREQUESTERENABLE_delay; + wire [7:0] DBGPLINFERREDRXELECTRICALIDLE_delay; + wire [7:0] LL2LMMAXISRXTVALID_delay; + wire [7:0] LL2LMSAXISTXTREADY_delay; + wire [7:0] MAXISCQTKEEP_delay; + wire [7:0] MAXISRCTKEEP_delay; + wire [84:0] MAXISCQTUSER_delay; + wire [8:0] MIREPLAYRAMADDRESS_delay; + wire [8:0] MIREQUESTRAMREADADDRESSA_delay; + wire [8:0] MIREQUESTRAMREADADDRESSB_delay; + wire [8:0] MIREQUESTRAMWRITEADDRESSA_delay; + wire [8:0] MIREQUESTRAMWRITEADDRESSB_delay; + wire [9:0] CFGEXTREGISTERNUMBER_delay; + wire [9:0] MICOMPLETIONRAMREADADDRESSAL_delay; + wire [9:0] MICOMPLETIONRAMREADADDRESSAU_delay; + wire [9:0] MICOMPLETIONRAMREADADDRESSBL_delay; + wire [9:0] MICOMPLETIONRAMREADADDRESSBU_delay; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSAL_delay; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSAU_delay; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSBL_delay; + wire [9:0] MICOMPLETIONRAMWRITEADDRESSBU_delay; + + wire CFGCONFIGSPACEENABLE_in; + wire CFGERRCORIN_in; + wire CFGERRUNCORIN_in; + wire CFGEXTREADDATAVALID_in; + wire CFGHOTRESETIN_in; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in; + wire CFGINTERRUPTMSITPHPRESENT_in; + wire CFGINTERRUPTMSIXINT_in; + wire CFGLINKTRAININGENABLE_in; + wire CFGMGMTREAD_in; + wire CFGMGMTTYPE1CFGREGACCESS_in; + wire CFGMGMTWRITE_in; + wire CFGMSGTRANSMIT_in; + wire CFGPERFUNCTIONOUTPUTREQUEST_in; + wire CFGPOWERSTATECHANGEACK_in; + wire CFGREQPMTRANSITIONL23READY_in; + wire CFGTPHSTTREADDATAVALID_in; + wire CONFMCAPREQUESTBYCONF_in; + wire CONFREQVALID_in; + wire CORECLKMICOMPLETIONRAML_in; + wire CORECLKMICOMPLETIONRAMU_in; + wire CORECLKMIREPLAYRAM_in; + wire CORECLKMIREQUESTRAM_in; + wire CORECLK_in; + wire DBGCFGLOCALMGMTREGOVERRIDE_in; + wire DRPCLK_in; + wire DRPEN_in; + wire DRPWE_in; + wire LL2LMSAXISTXTVALID_in; + wire MCAPCLK_in; + wire MCAPPERST0B_in; + wire MCAPPERST1B_in; + wire MGMTRESETN_in; + wire MGMTSTICKYRESETN_in; + wire PCIECQNPREQ_in; + wire PIPECLK_in; + wire PIPERESETN_in; + wire PIPERX0DATAVALID_in; + wire PIPERX0ELECIDLE_in; + wire PIPERX0EQDONE_in; + wire PIPERX0EQLPADAPTDONE_in; + wire PIPERX0EQLPLFFSSEL_in; + wire PIPERX0PHYSTATUS_in; + wire PIPERX0STARTBLOCK_in; + wire PIPERX0VALID_in; + wire PIPERX1DATAVALID_in; + wire PIPERX1ELECIDLE_in; + wire PIPERX1EQDONE_in; + wire PIPERX1EQLPADAPTDONE_in; + wire PIPERX1EQLPLFFSSEL_in; + wire PIPERX1PHYSTATUS_in; + wire PIPERX1STARTBLOCK_in; + wire PIPERX1VALID_in; + wire PIPERX2DATAVALID_in; + wire PIPERX2ELECIDLE_in; + wire PIPERX2EQDONE_in; + wire PIPERX2EQLPADAPTDONE_in; + wire PIPERX2EQLPLFFSSEL_in; + wire PIPERX2PHYSTATUS_in; + wire PIPERX2STARTBLOCK_in; + wire PIPERX2VALID_in; + wire PIPERX3DATAVALID_in; + wire PIPERX3ELECIDLE_in; + wire PIPERX3EQDONE_in; + wire PIPERX3EQLPADAPTDONE_in; + wire PIPERX3EQLPLFFSSEL_in; + wire PIPERX3PHYSTATUS_in; + wire PIPERX3STARTBLOCK_in; + wire PIPERX3VALID_in; + wire PIPERX4DATAVALID_in; + wire PIPERX4ELECIDLE_in; + wire PIPERX4EQDONE_in; + wire PIPERX4EQLPADAPTDONE_in; + wire PIPERX4EQLPLFFSSEL_in; + wire PIPERX4PHYSTATUS_in; + wire PIPERX4STARTBLOCK_in; + wire PIPERX4VALID_in; + wire PIPERX5DATAVALID_in; + wire PIPERX5ELECIDLE_in; + wire PIPERX5EQDONE_in; + wire PIPERX5EQLPADAPTDONE_in; + wire PIPERX5EQLPLFFSSEL_in; + wire PIPERX5PHYSTATUS_in; + wire PIPERX5STARTBLOCK_in; + wire PIPERX5VALID_in; + wire PIPERX6DATAVALID_in; + wire PIPERX6ELECIDLE_in; + wire PIPERX6EQDONE_in; + wire PIPERX6EQLPADAPTDONE_in; + wire PIPERX6EQLPLFFSSEL_in; + wire PIPERX6PHYSTATUS_in; + wire PIPERX6STARTBLOCK_in; + wire PIPERX6VALID_in; + wire PIPERX7DATAVALID_in; + wire PIPERX7ELECIDLE_in; + wire PIPERX7EQDONE_in; + wire PIPERX7EQLPADAPTDONE_in; + wire PIPERX7EQLPLFFSSEL_in; + wire PIPERX7PHYSTATUS_in; + wire PIPERX7STARTBLOCK_in; + wire PIPERX7VALID_in; + wire PIPETX0EQDONE_in; + wire PIPETX1EQDONE_in; + wire PIPETX2EQDONE_in; + wire PIPETX3EQDONE_in; + wire PIPETX4EQDONE_in; + wire PIPETX5EQDONE_in; + wire PIPETX6EQDONE_in; + wire PIPETX7EQDONE_in; + wire PLEQRESETEIEOSCOUNT_in; + wire PLGEN2UPSTREAMPREFERDEEMPH_in; + wire PMVENABLEN_in; + wire RESETN_in; + wire SAXISCCTLAST_in; + wire SAXISCCTVALID_in; + wire SAXISRQTLAST_in; + wire SAXISRQTVALID_in; + wire SCANENABLEN_in; + wire SCANMODEN_in; + wire USERCLK_in; + wire [13:0] LL2LMSAXISTXTUSER_in; + wire [143:0] MICOMPLETIONRAMREADDATA_in; + wire [143:0] MIREPLAYRAMREADDATA_in; + wire [143:0] MIREQUESTRAMREADDATA_in; + wire [15:0] CFGDEVID_in; + wire [15:0] CFGSUBSYSID_in; + wire [15:0] CFGSUBSYSVENDID_in; + wire [15:0] CFGVENDID_in; + wire [15:0] DRPDI_in; + wire [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET_in; + wire [17:0] PIPETX0EQCOEFF_in; + wire [17:0] PIPETX1EQCOEFF_in; + wire [17:0] PIPETX2EQCOEFF_in; + wire [17:0] PIPETX3EQCOEFF_in; + wire [17:0] PIPETX4EQCOEFF_in; + wire [17:0] PIPETX5EQCOEFF_in; + wire [17:0] PIPETX6EQCOEFF_in; + wire [17:0] PIPETX7EQCOEFF_in; + wire [18:0] CFGMGMTADDR_in; + wire [1919:0] XILUNCONNBYP_in; + wire [1:0] CFGINTERRUPTMSITPHTYPE_in; + wire [1:0] CONFREQTYPE_in; + wire [1:0] PIPERX0CHARISK_in; + wire [1:0] PIPERX0SYNCHEADER_in; + wire [1:0] PIPERX1CHARISK_in; + wire [1:0] PIPERX1SYNCHEADER_in; + wire [1:0] PIPERX2CHARISK_in; + wire [1:0] PIPERX2SYNCHEADER_in; + wire [1:0] PIPERX3CHARISK_in; + wire [1:0] PIPERX3SYNCHEADER_in; + wire [1:0] PIPERX4CHARISK_in; + wire [1:0] PIPERX4SYNCHEADER_in; + wire [1:0] PIPERX5CHARISK_in; + wire [1:0] PIPERX5SYNCHEADER_in; + wire [1:0] PIPERX6CHARISK_in; + wire [1:0] PIPERX6SYNCHEADER_in; + wire [1:0] PIPERX7CHARISK_in; + wire [1:0] PIPERX7SYNCHEADER_in; + wire [1:0] PMVDIVIDE_in; + wire [21:0] MAXISCQTREADY_in; + wire [21:0] MAXISRCTREADY_in; + wire [255:0] SAXISCCTDATA_in; + wire [255:0] SAXISRQTDATA_in; + wire [2:0] CFGDSFUNCTIONNUMBER_in; + wire [2:0] CFGFCSEL_in; + wire [2:0] CFGINTERRUPTMSIATTR_in; + wire [2:0] CFGMSGTRANSMITTYPE_in; + wire [2:0] CFGPERFUNCSTATUSCONTROL_in; + wire [2:0] PIPERX0STATUS_in; + wire [2:0] PIPERX1STATUS_in; + wire [2:0] PIPERX2STATUS_in; + wire [2:0] PIPERX3STATUS_in; + wire [2:0] PIPERX4STATUS_in; + wire [2:0] PIPERX5STATUS_in; + wire [2:0] PIPERX6STATUS_in; + wire [2:0] PIPERX7STATUS_in; + wire [2:0] PMVSELECT_in; + wire [3188:0] XILUNCONNIN_in; + wire [31:0] CFGEXTREADDATA_in; + wire [31:0] CFGINTERRUPTMSIINT_in; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_in; + wire [31:0] CFGINTERRUPTMSIXDATA_in; + wire [31:0] CFGMGMTWRITEDATA_in; + wire [31:0] CFGMSGTRANSMITDATA_in; + wire [31:0] CFGTPHSTTREADDATA_in; + wire [31:0] CONFREQDATA_in; + wire [31:0] PIPERX0DATA_in; + wire [31:0] PIPERX1DATA_in; + wire [31:0] PIPERX2DATA_in; + wire [31:0] PIPERX3DATA_in; + wire [31:0] PIPERX4DATA_in; + wire [31:0] PIPERX5DATA_in; + wire [31:0] PIPERX6DATA_in; + wire [31:0] PIPERX7DATA_in; + wire [31:0] SPAREIN_in; + wire [32:0] SAXISCCTUSER_in; + wire [3:0] CFGFLRDONE_in; + wire [3:0] CFGINTERRUPTINT_in; + wire [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER_in; + wire [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in; + wire [3:0] CFGINTERRUPTMSISELECT_in; + wire [3:0] CFGINTERRUPTPENDING_in; + wire [3:0] CFGMGMTBYTEENABLE_in; + wire [3:0] CFGPERFUNCTIONNUMBER_in; + wire [3:0] CONFREQREGNUM_in; + wire [3:0] DBGDATASEL_in; + wire [3:0] LL2LMTXTLPID0_in; + wire [3:0] LL2LMTXTLPID1_in; + wire [4:0] CFGDSDEVICENUMBER_in; + wire [59:0] SAXISRQTUSER_in; + wire [5:0] PIPEEQFS_in; + wire [5:0] PIPEEQLF_in; + wire [63:0] CFGDSN_in; + wire [63:0] CFGINTERRUPTMSIXADDRESS_in; + wire [7:0] CFGDSBUSNUMBER_in; + wire [7:0] CFGDSPORTNUMBER_in; + wire [7:0] CFGREVID_in; + wire [7:0] CFGVFFLRDONE_in; + wire [7:0] SAXISCCTKEEP_in; + wire [7:0] SAXISRQTKEEP_in; + wire [8:0] CFGINTERRUPTMSITPHSTTAG_in; + wire [950:0] XILUNCONNCLK_in; + wire [95:0] SCANIN_in; + wire [9:0] DRPADDR_in; + + wire CFGCONFIGSPACEENABLE_delay; + wire CFGERRCORIN_delay; + wire CFGERRUNCORIN_delay; + wire CFGEXTREADDATAVALID_delay; + wire CFGHOTRESETIN_delay; + wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; + wire CFGINTERRUPTMSITPHPRESENT_delay; + wire CFGINTERRUPTMSIXINT_delay; + wire CFGLINKTRAININGENABLE_delay; + wire CFGMGMTREAD_delay; + wire CFGMGMTTYPE1CFGREGACCESS_delay; + wire CFGMGMTWRITE_delay; + wire CFGMSGTRANSMIT_delay; + wire CFGPERFUNCTIONOUTPUTREQUEST_delay; + wire CFGPOWERSTATECHANGEACK_delay; + wire CFGREQPMTRANSITIONL23READY_delay; + wire CFGTPHSTTREADDATAVALID_delay; + wire CONFMCAPREQUESTBYCONF_delay; + wire CONFREQVALID_delay; + wire CORECLKMICOMPLETIONRAML_delay; + wire CORECLKMICOMPLETIONRAMU_delay; + wire CORECLKMIREPLAYRAM_delay; + wire CORECLKMIREQUESTRAM_delay; + wire CORECLK_delay; + wire DBGCFGLOCALMGMTREGOVERRIDE_delay; + wire DRPCLK_delay; + wire DRPEN_delay; + wire DRPWE_delay; + wire LL2LMSAXISTXTVALID_delay; + wire MCAPCLK_delay; + wire MCAPPERST0B_delay; + wire MCAPPERST1B_delay; + wire MGMTRESETN_delay; + wire MGMTSTICKYRESETN_delay; + wire PCIECQNPREQ_delay; + wire PIPECLK_delay; + wire PIPERESETN_delay; + wire PIPERX0DATAVALID_delay; + wire PIPERX0ELECIDLE_delay; + wire PIPERX0EQDONE_delay; + wire PIPERX0EQLPADAPTDONE_delay; + wire PIPERX0EQLPLFFSSEL_delay; + wire PIPERX0PHYSTATUS_delay; + wire PIPERX0STARTBLOCK_delay; + wire PIPERX0VALID_delay; + wire PIPERX1DATAVALID_delay; + wire PIPERX1ELECIDLE_delay; + wire PIPERX1EQDONE_delay; + wire PIPERX1EQLPADAPTDONE_delay; + wire PIPERX1EQLPLFFSSEL_delay; + wire PIPERX1PHYSTATUS_delay; + wire PIPERX1STARTBLOCK_delay; + wire PIPERX1VALID_delay; + wire PIPERX2DATAVALID_delay; + wire PIPERX2ELECIDLE_delay; + wire PIPERX2EQDONE_delay; + wire PIPERX2EQLPADAPTDONE_delay; + wire PIPERX2EQLPLFFSSEL_delay; + wire PIPERX2PHYSTATUS_delay; + wire PIPERX2STARTBLOCK_delay; + wire PIPERX2VALID_delay; + wire PIPERX3DATAVALID_delay; + wire PIPERX3ELECIDLE_delay; + wire PIPERX3EQDONE_delay; + wire PIPERX3EQLPADAPTDONE_delay; + wire PIPERX3EQLPLFFSSEL_delay; + wire PIPERX3PHYSTATUS_delay; + wire PIPERX3STARTBLOCK_delay; + wire PIPERX3VALID_delay; + wire PIPERX4DATAVALID_delay; + wire PIPERX4ELECIDLE_delay; + wire PIPERX4EQDONE_delay; + wire PIPERX4EQLPADAPTDONE_delay; + wire PIPERX4EQLPLFFSSEL_delay; + wire PIPERX4PHYSTATUS_delay; + wire PIPERX4STARTBLOCK_delay; + wire PIPERX4VALID_delay; + wire PIPERX5DATAVALID_delay; + wire PIPERX5ELECIDLE_delay; + wire PIPERX5EQDONE_delay; + wire PIPERX5EQLPADAPTDONE_delay; + wire PIPERX5EQLPLFFSSEL_delay; + wire PIPERX5PHYSTATUS_delay; + wire PIPERX5STARTBLOCK_delay; + wire PIPERX5VALID_delay; + wire PIPERX6DATAVALID_delay; + wire PIPERX6ELECIDLE_delay; + wire PIPERX6EQDONE_delay; + wire PIPERX6EQLPADAPTDONE_delay; + wire PIPERX6EQLPLFFSSEL_delay; + wire PIPERX6PHYSTATUS_delay; + wire PIPERX6STARTBLOCK_delay; + wire PIPERX6VALID_delay; + wire PIPERX7DATAVALID_delay; + wire PIPERX7ELECIDLE_delay; + wire PIPERX7EQDONE_delay; + wire PIPERX7EQLPADAPTDONE_delay; + wire PIPERX7EQLPLFFSSEL_delay; + wire PIPERX7PHYSTATUS_delay; + wire PIPERX7STARTBLOCK_delay; + wire PIPERX7VALID_delay; + wire PIPETX0EQDONE_delay; + wire PIPETX1EQDONE_delay; + wire PIPETX2EQDONE_delay; + wire PIPETX3EQDONE_delay; + wire PIPETX4EQDONE_delay; + wire PIPETX5EQDONE_delay; + wire PIPETX6EQDONE_delay; + wire PIPETX7EQDONE_delay; + wire PLEQRESETEIEOSCOUNT_delay; + wire PLGEN2UPSTREAMPREFERDEEMPH_delay; + wire RESETN_delay; + wire SAXISCCTLAST_delay; + wire SAXISCCTVALID_delay; + wire SAXISRQTLAST_delay; + wire SAXISRQTVALID_delay; + wire USERCLK_delay; + wire [13:0] LL2LMSAXISTXTUSER_delay; + wire [143:0] MICOMPLETIONRAMREADDATA_delay; + wire [143:0] MIREPLAYRAMREADDATA_delay; + wire [143:0] MIREQUESTRAMREADDATA_delay; + wire [15:0] CFGDEVID_delay; + wire [15:0] CFGSUBSYSID_delay; + wire [15:0] CFGSUBSYSVENDID_delay; + wire [15:0] CFGVENDID_delay; + wire [15:0] DRPDI_delay; + wire [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET_delay; + wire [17:0] PIPETX0EQCOEFF_delay; + wire [17:0] PIPETX1EQCOEFF_delay; + wire [17:0] PIPETX2EQCOEFF_delay; + wire [17:0] PIPETX3EQCOEFF_delay; + wire [17:0] PIPETX4EQCOEFF_delay; + wire [17:0] PIPETX5EQCOEFF_delay; + wire [17:0] PIPETX6EQCOEFF_delay; + wire [17:0] PIPETX7EQCOEFF_delay; + wire [18:0] CFGMGMTADDR_delay; + wire [1:0] CFGINTERRUPTMSITPHTYPE_delay; + wire [1:0] CONFREQTYPE_delay; + wire [1:0] PIPERX0CHARISK_delay; + wire [1:0] PIPERX0SYNCHEADER_delay; + wire [1:0] PIPERX1CHARISK_delay; + wire [1:0] PIPERX1SYNCHEADER_delay; + wire [1:0] PIPERX2CHARISK_delay; + wire [1:0] PIPERX2SYNCHEADER_delay; + wire [1:0] PIPERX3CHARISK_delay; + wire [1:0] PIPERX3SYNCHEADER_delay; + wire [1:0] PIPERX4CHARISK_delay; + wire [1:0] PIPERX4SYNCHEADER_delay; + wire [1:0] PIPERX5CHARISK_delay; + wire [1:0] PIPERX5SYNCHEADER_delay; + wire [1:0] PIPERX6CHARISK_delay; + wire [1:0] PIPERX6SYNCHEADER_delay; + wire [1:0] PIPERX7CHARISK_delay; + wire [1:0] PIPERX7SYNCHEADER_delay; + wire [21:0] MAXISCQTREADY_delay; + wire [21:0] MAXISRCTREADY_delay; + wire [255:0] SAXISCCTDATA_delay; + wire [255:0] SAXISRQTDATA_delay; + wire [2:0] CFGDSFUNCTIONNUMBER_delay; + wire [2:0] CFGFCSEL_delay; + wire [2:0] CFGINTERRUPTMSIATTR_delay; + wire [2:0] CFGMSGTRANSMITTYPE_delay; + wire [2:0] CFGPERFUNCSTATUSCONTROL_delay; + wire [2:0] PIPERX0STATUS_delay; + wire [2:0] PIPERX1STATUS_delay; + wire [2:0] PIPERX2STATUS_delay; + wire [2:0] PIPERX3STATUS_delay; + wire [2:0] PIPERX4STATUS_delay; + wire [2:0] PIPERX5STATUS_delay; + wire [2:0] PIPERX6STATUS_delay; + wire [2:0] PIPERX7STATUS_delay; + wire [31:0] CFGEXTREADDATA_delay; + wire [31:0] CFGINTERRUPTMSIINT_delay; + wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_delay; + wire [31:0] CFGINTERRUPTMSIXDATA_delay; + wire [31:0] CFGMGMTWRITEDATA_delay; + wire [31:0] CFGMSGTRANSMITDATA_delay; + wire [31:0] CFGTPHSTTREADDATA_delay; + wire [31:0] CONFREQDATA_delay; + wire [31:0] PIPERX0DATA_delay; + wire [31:0] PIPERX1DATA_delay; + wire [31:0] PIPERX2DATA_delay; + wire [31:0] PIPERX3DATA_delay; + wire [31:0] PIPERX4DATA_delay; + wire [31:0] PIPERX5DATA_delay; + wire [31:0] PIPERX6DATA_delay; + wire [31:0] PIPERX7DATA_delay; + wire [31:0] SPAREIN_delay; + wire [32:0] SAXISCCTUSER_delay; + wire [3:0] CFGFLRDONE_delay; + wire [3:0] CFGINTERRUPTINT_delay; + wire [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER_delay; + wire [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay; + wire [3:0] CFGINTERRUPTMSISELECT_delay; + wire [3:0] CFGINTERRUPTPENDING_delay; + wire [3:0] CFGMGMTBYTEENABLE_delay; + wire [3:0] CFGPERFUNCTIONNUMBER_delay; + wire [3:0] CONFREQREGNUM_delay; + wire [3:0] DBGDATASEL_delay; + wire [3:0] LL2LMTXTLPID0_delay; + wire [3:0] LL2LMTXTLPID1_delay; + wire [4:0] CFGDSDEVICENUMBER_delay; + wire [59:0] SAXISRQTUSER_delay; + wire [5:0] PIPEEQFS_delay; + wire [5:0] PIPEEQLF_delay; + wire [63:0] CFGDSN_delay; + wire [63:0] CFGINTERRUPTMSIXADDRESS_delay; + wire [7:0] CFGDSBUSNUMBER_delay; + wire [7:0] CFGDSPORTNUMBER_delay; + wire [7:0] CFGREVID_delay; + wire [7:0] CFGVFFLRDONE_delay; + wire [7:0] SAXISCCTKEEP_delay; + wire [7:0] SAXISRQTKEEP_delay; + wire [8:0] CFGINTERRUPTMSITPHSTTAG_delay; + wire [9:0] DRPADDR_delay; + + + assign #(out_delay) CFGCURRENTSPEED = CFGCURRENTSPEED_delay; + assign #(out_delay) CFGDPASUBSTATECHANGE = CFGDPASUBSTATECHANGE_delay; + assign #(out_delay) CFGERRCOROUT = CFGERRCOROUT_delay; + assign #(out_delay) CFGERRFATALOUT = CFGERRFATALOUT_delay; + assign #(out_delay) CFGERRNONFATALOUT = CFGERRNONFATALOUT_delay; + assign #(out_delay) CFGEXTFUNCTIONNUMBER = CFGEXTFUNCTIONNUMBER_delay; + assign #(out_delay) CFGEXTREADRECEIVED = CFGEXTREADRECEIVED_delay; + assign #(out_delay) CFGEXTREGISTERNUMBER = CFGEXTREGISTERNUMBER_delay; + assign #(out_delay) CFGEXTWRITEBYTEENABLE = CFGEXTWRITEBYTEENABLE_delay; + assign #(out_delay) CFGEXTWRITEDATA = CFGEXTWRITEDATA_delay; + assign #(out_delay) CFGEXTWRITERECEIVED = CFGEXTWRITERECEIVED_delay; + assign #(out_delay) CFGFCCPLD = CFGFCCPLD_delay; + assign #(out_delay) CFGFCCPLH = CFGFCCPLH_delay; + assign #(out_delay) CFGFCNPD = CFGFCNPD_delay; + assign #(out_delay) CFGFCNPH = CFGFCNPH_delay; + assign #(out_delay) CFGFCPD = CFGFCPD_delay; + assign #(out_delay) CFGFCPH = CFGFCPH_delay; + assign #(out_delay) CFGFLRINPROCESS = CFGFLRINPROCESS_delay; + assign #(out_delay) CFGFUNCTIONPOWERSTATE = CFGFUNCTIONPOWERSTATE_delay; + assign #(out_delay) CFGFUNCTIONSTATUS = CFGFUNCTIONSTATUS_delay; + assign #(out_delay) CFGHOTRESETOUT = CFGHOTRESETOUT_delay; + assign #(out_delay) CFGINTERRUPTMSIDATA = CFGINTERRUPTMSIDATA_delay; + assign #(out_delay) CFGINTERRUPTMSIENABLE = CFGINTERRUPTMSIENABLE_delay; + assign #(out_delay) CFGINTERRUPTMSIFAIL = CFGINTERRUPTMSIFAIL_delay; + assign #(out_delay) CFGINTERRUPTMSIMASKUPDATE = CFGINTERRUPTMSIMASKUPDATE_delay; + assign #(out_delay) CFGINTERRUPTMSIMMENABLE = CFGINTERRUPTMSIMMENABLE_delay; + assign #(out_delay) CFGINTERRUPTMSISENT = CFGINTERRUPTMSISENT_delay; + assign #(out_delay) CFGINTERRUPTMSIVFENABLE = CFGINTERRUPTMSIVFENABLE_delay; + assign #(out_delay) CFGINTERRUPTMSIXENABLE = CFGINTERRUPTMSIXENABLE_delay; + assign #(out_delay) CFGINTERRUPTMSIXFAIL = CFGINTERRUPTMSIXFAIL_delay; + assign #(out_delay) CFGINTERRUPTMSIXMASK = CFGINTERRUPTMSIXMASK_delay; + assign #(out_delay) CFGINTERRUPTMSIXSENT = CFGINTERRUPTMSIXSENT_delay; + assign #(out_delay) CFGINTERRUPTMSIXVFENABLE = CFGINTERRUPTMSIXVFENABLE_delay; + assign #(out_delay) CFGINTERRUPTMSIXVFMASK = CFGINTERRUPTMSIXVFMASK_delay; + assign #(out_delay) CFGINTERRUPTSENT = CFGINTERRUPTSENT_delay; + assign #(out_delay) CFGLINKPOWERSTATE = CFGLINKPOWERSTATE_delay; + assign #(out_delay) CFGLOCALERROR = CFGLOCALERROR_delay; + assign #(out_delay) CFGLTRENABLE = CFGLTRENABLE_delay; + assign #(out_delay) CFGLTSSMSTATE = CFGLTSSMSTATE_delay; + assign #(out_delay) CFGMAXPAYLOAD = CFGMAXPAYLOAD_delay; + assign #(out_delay) CFGMAXREADREQ = CFGMAXREADREQ_delay; + assign #(out_delay) CFGMGMTREADDATA = CFGMGMTREADDATA_delay; + assign #(out_delay) CFGMGMTREADWRITEDONE = CFGMGMTREADWRITEDONE_delay; + assign #(out_delay) CFGMSGRECEIVED = CFGMSGRECEIVED_delay; + assign #(out_delay) CFGMSGRECEIVEDDATA = CFGMSGRECEIVEDDATA_delay; + assign #(out_delay) CFGMSGRECEIVEDTYPE = CFGMSGRECEIVEDTYPE_delay; + assign #(out_delay) CFGMSGTRANSMITDONE = CFGMSGTRANSMITDONE_delay; + assign #(out_delay) CFGNEGOTIATEDWIDTH = CFGNEGOTIATEDWIDTH_delay; + assign #(out_delay) CFGOBFFENABLE = CFGOBFFENABLE_delay; + assign #(out_delay) CFGPERFUNCSTATUSDATA = CFGPERFUNCSTATUSDATA_delay; + assign #(out_delay) CFGPERFUNCTIONUPDATEDONE = CFGPERFUNCTIONUPDATEDONE_delay; + assign #(out_delay) CFGPHYLINKDOWN = CFGPHYLINKDOWN_delay; + assign #(out_delay) CFGPHYLINKSTATUS = CFGPHYLINKSTATUS_delay; + assign #(out_delay) CFGPLSTATUSCHANGE = CFGPLSTATUSCHANGE_delay; + assign #(out_delay) CFGPOWERSTATECHANGEINTERRUPT = CFGPOWERSTATECHANGEINTERRUPT_delay; + assign #(out_delay) CFGRCBSTATUS = CFGRCBSTATUS_delay; + assign #(out_delay) CFGTPHFUNCTIONNUM = CFGTPHFUNCTIONNUM_delay; + assign #(out_delay) CFGTPHREQUESTERENABLE = CFGTPHREQUESTERENABLE_delay; + assign #(out_delay) CFGTPHSTMODE = CFGTPHSTMODE_delay; + assign #(out_delay) CFGTPHSTTADDRESS = CFGTPHSTTADDRESS_delay; + assign #(out_delay) CFGTPHSTTREADENABLE = CFGTPHSTTREADENABLE_delay; + assign #(out_delay) CFGTPHSTTWRITEBYTEVALID = CFGTPHSTTWRITEBYTEVALID_delay; + assign #(out_delay) CFGTPHSTTWRITEDATA = CFGTPHSTTWRITEDATA_delay; + assign #(out_delay) CFGTPHSTTWRITEENABLE = CFGTPHSTTWRITEENABLE_delay; + assign #(out_delay) CFGVFFLRINPROCESS = CFGVFFLRINPROCESS_delay; + assign #(out_delay) CFGVFPOWERSTATE = CFGVFPOWERSTATE_delay; + assign #(out_delay) CFGVFSTATUS = CFGVFSTATUS_delay; + assign #(out_delay) CFGVFTPHREQUESTERENABLE = CFGVFTPHREQUESTERENABLE_delay; + assign #(out_delay) CFGVFTPHSTMODE = CFGVFTPHSTMODE_delay; + assign #(out_delay) CONFMCAPDESIGNSWITCH = CONFMCAPDESIGNSWITCH_delay; + assign #(out_delay) CONFMCAPEOS = CONFMCAPEOS_delay; + assign #(out_delay) CONFMCAPINUSEBYPCIE = CONFMCAPINUSEBYPCIE_delay; + assign #(out_delay) CONFREQREADY = CONFREQREADY_delay; + assign #(out_delay) CONFRESPRDATA = CONFRESPRDATA_delay; + assign #(out_delay) CONFRESPVALID = CONFRESPVALID_delay; + assign #(out_delay) DBGDATAOUT = DBGDATAOUT_delay; + assign #(out_delay) DBGMCAPCSB = DBGMCAPCSB_delay; + assign #(out_delay) DBGMCAPDATA = DBGMCAPDATA_delay; + assign #(out_delay) DBGMCAPEOS = DBGMCAPEOS_delay; + assign #(out_delay) DBGMCAPERROR = DBGMCAPERROR_delay; + assign #(out_delay) DBGMCAPMODE = DBGMCAPMODE_delay; + assign #(out_delay) DBGMCAPRDATAVALID = DBGMCAPRDATAVALID_delay; + assign #(out_delay) DBGMCAPRDWRB = DBGMCAPRDWRB_delay; + assign #(out_delay) DBGMCAPRESET = DBGMCAPRESET_delay; + assign #(out_delay) DBGPLDATABLOCKRECEIVEDAFTEREDS = DBGPLDATABLOCKRECEIVEDAFTEREDS_delay; + assign #(out_delay) DBGPLGEN3FRAMINGERRORDETECTED = DBGPLGEN3FRAMINGERRORDETECTED_delay; + assign #(out_delay) DBGPLGEN3SYNCHEADERERRORDETECTED = DBGPLGEN3SYNCHEADERERRORDETECTED_delay; + assign #(out_delay) DBGPLINFERREDRXELECTRICALIDLE = DBGPLINFERREDRXELECTRICALIDLE_delay; + assign #(out_delay) DRPDO = DRPDO_delay; + assign #(out_delay) DRPRDY = DRPRDY_delay; + assign #(out_delay) LL2LMMASTERTLPSENT0 = LL2LMMASTERTLPSENT0_delay; + assign #(out_delay) LL2LMMASTERTLPSENT1 = LL2LMMASTERTLPSENT1_delay; + assign #(out_delay) LL2LMMASTERTLPSENTTLPID0 = LL2LMMASTERTLPSENTTLPID0_delay; + assign #(out_delay) LL2LMMASTERTLPSENTTLPID1 = LL2LMMASTERTLPSENTTLPID1_delay; + assign #(out_delay) LL2LMMAXISRXTDATA = LL2LMMAXISRXTDATA_delay; + assign #(out_delay) LL2LMMAXISRXTUSER = LL2LMMAXISRXTUSER_delay; + assign #(out_delay) LL2LMMAXISRXTVALID = LL2LMMAXISRXTVALID_delay; + assign #(out_delay) LL2LMSAXISTXTREADY = LL2LMSAXISTXTREADY_delay; + assign #(out_delay) MAXISCQTDATA = MAXISCQTDATA_delay; + assign #(out_delay) MAXISCQTKEEP = MAXISCQTKEEP_delay; + assign #(out_delay) MAXISCQTLAST = MAXISCQTLAST_delay; + assign #(out_delay) MAXISCQTUSER = MAXISCQTUSER_delay; + assign #(out_delay) MAXISCQTVALID = MAXISCQTVALID_delay; + assign #(out_delay) MAXISRCTDATA = MAXISRCTDATA_delay; + assign #(out_delay) MAXISRCTKEEP = MAXISRCTKEEP_delay; + assign #(out_delay) MAXISRCTLAST = MAXISRCTLAST_delay; + assign #(out_delay) MAXISRCTUSER = MAXISRCTUSER_delay; + assign #(out_delay) MAXISRCTVALID = MAXISRCTVALID_delay; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSAL = MICOMPLETIONRAMREADADDRESSAL_delay; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSAU = MICOMPLETIONRAMREADADDRESSAU_delay; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSBL = MICOMPLETIONRAMREADADDRESSBL_delay; + assign #(out_delay) MICOMPLETIONRAMREADADDRESSBU = MICOMPLETIONRAMREADADDRESSBU_delay; + assign #(out_delay) MICOMPLETIONRAMREADENABLEL = MICOMPLETIONRAMREADENABLEL_delay; + assign #(out_delay) MICOMPLETIONRAMREADENABLEU = MICOMPLETIONRAMREADENABLEU_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAL = MICOMPLETIONRAMWRITEADDRESSAL_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAU = MICOMPLETIONRAMWRITEADDRESSAU_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBL = MICOMPLETIONRAMWRITEADDRESSBL_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBU = MICOMPLETIONRAMWRITEADDRESSBU_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEDATAL = MICOMPLETIONRAMWRITEDATAL_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEDATAU = MICOMPLETIONRAMWRITEDATAU_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEENABLEL = MICOMPLETIONRAMWRITEENABLEL_delay; + assign #(out_delay) MICOMPLETIONRAMWRITEENABLEU = MICOMPLETIONRAMWRITEENABLEU_delay; + assign #(out_delay) MIREPLAYRAMADDRESS = MIREPLAYRAMADDRESS_delay; + assign #(out_delay) MIREPLAYRAMREADENABLE = MIREPLAYRAMREADENABLE_delay; + assign #(out_delay) MIREPLAYRAMWRITEDATA = MIREPLAYRAMWRITEDATA_delay; + assign #(out_delay) MIREPLAYRAMWRITEENABLE = MIREPLAYRAMWRITEENABLE_delay; + assign #(out_delay) MIREQUESTRAMREADADDRESSA = MIREQUESTRAMREADADDRESSA_delay; + assign #(out_delay) MIREQUESTRAMREADADDRESSB = MIREQUESTRAMREADADDRESSB_delay; + assign #(out_delay) MIREQUESTRAMREADENABLE = MIREQUESTRAMREADENABLE_delay; + assign #(out_delay) MIREQUESTRAMWRITEADDRESSA = MIREQUESTRAMWRITEADDRESSA_delay; + assign #(out_delay) MIREQUESTRAMWRITEADDRESSB = MIREQUESTRAMWRITEADDRESSB_delay; + assign #(out_delay) MIREQUESTRAMWRITEDATA = MIREQUESTRAMWRITEDATA_delay; + assign #(out_delay) MIREQUESTRAMWRITEENABLE = MIREQUESTRAMWRITEENABLE_delay; + assign #(out_delay) PCIECQNPREQCOUNT = PCIECQNPREQCOUNT_delay; + assign #(out_delay) PCIEPERST0B = PCIEPERST0B_delay; + assign #(out_delay) PCIEPERST1B = PCIEPERST1B_delay; + assign #(out_delay) PCIERQSEQNUM = PCIERQSEQNUM_delay; + assign #(out_delay) PCIERQSEQNUMVLD = PCIERQSEQNUMVLD_delay; + assign #(out_delay) PCIERQTAG = PCIERQTAG_delay; + assign #(out_delay) PCIERQTAGAV = PCIERQTAGAV_delay; + assign #(out_delay) PCIERQTAGVLD = PCIERQTAGVLD_delay; + assign #(out_delay) PCIETFCNPDAV = PCIETFCNPDAV_delay; + assign #(out_delay) PCIETFCNPHAV = PCIETFCNPHAV_delay; + assign #(out_delay) PIPERX0EQCONTROL = PIPERX0EQCONTROL_delay; + assign #(out_delay) PIPERX0EQLPLFFS = PIPERX0EQLPLFFS_delay; + assign #(out_delay) PIPERX0EQLPTXPRESET = PIPERX0EQLPTXPRESET_delay; + assign #(out_delay) PIPERX0EQPRESET = PIPERX0EQPRESET_delay; + assign #(out_delay) PIPERX0POLARITY = PIPERX0POLARITY_delay; + assign #(out_delay) PIPERX1EQCONTROL = PIPERX1EQCONTROL_delay; + assign #(out_delay) PIPERX1EQLPLFFS = PIPERX1EQLPLFFS_delay; + assign #(out_delay) PIPERX1EQLPTXPRESET = PIPERX1EQLPTXPRESET_delay; + assign #(out_delay) PIPERX1EQPRESET = PIPERX1EQPRESET_delay; + assign #(out_delay) PIPERX1POLARITY = PIPERX1POLARITY_delay; + assign #(out_delay) PIPERX2EQCONTROL = PIPERX2EQCONTROL_delay; + assign #(out_delay) PIPERX2EQLPLFFS = PIPERX2EQLPLFFS_delay; + assign #(out_delay) PIPERX2EQLPTXPRESET = PIPERX2EQLPTXPRESET_delay; + assign #(out_delay) PIPERX2EQPRESET = PIPERX2EQPRESET_delay; + assign #(out_delay) PIPERX2POLARITY = PIPERX2POLARITY_delay; + assign #(out_delay) PIPERX3EQCONTROL = PIPERX3EQCONTROL_delay; + assign #(out_delay) PIPERX3EQLPLFFS = PIPERX3EQLPLFFS_delay; + assign #(out_delay) PIPERX3EQLPTXPRESET = PIPERX3EQLPTXPRESET_delay; + assign #(out_delay) PIPERX3EQPRESET = PIPERX3EQPRESET_delay; + assign #(out_delay) PIPERX3POLARITY = PIPERX3POLARITY_delay; + assign #(out_delay) PIPERX4EQCONTROL = PIPERX4EQCONTROL_delay; + assign #(out_delay) PIPERX4EQLPLFFS = PIPERX4EQLPLFFS_delay; + assign #(out_delay) PIPERX4EQLPTXPRESET = PIPERX4EQLPTXPRESET_delay; + assign #(out_delay) PIPERX4EQPRESET = PIPERX4EQPRESET_delay; + assign #(out_delay) PIPERX4POLARITY = PIPERX4POLARITY_delay; + assign #(out_delay) PIPERX5EQCONTROL = PIPERX5EQCONTROL_delay; + assign #(out_delay) PIPERX5EQLPLFFS = PIPERX5EQLPLFFS_delay; + assign #(out_delay) PIPERX5EQLPTXPRESET = PIPERX5EQLPTXPRESET_delay; + assign #(out_delay) PIPERX5EQPRESET = PIPERX5EQPRESET_delay; + assign #(out_delay) PIPERX5POLARITY = PIPERX5POLARITY_delay; + assign #(out_delay) PIPERX6EQCONTROL = PIPERX6EQCONTROL_delay; + assign #(out_delay) PIPERX6EQLPLFFS = PIPERX6EQLPLFFS_delay; + assign #(out_delay) PIPERX6EQLPTXPRESET = PIPERX6EQLPTXPRESET_delay; + assign #(out_delay) PIPERX6EQPRESET = PIPERX6EQPRESET_delay; + assign #(out_delay) PIPERX6POLARITY = PIPERX6POLARITY_delay; + assign #(out_delay) PIPERX7EQCONTROL = PIPERX7EQCONTROL_delay; + assign #(out_delay) PIPERX7EQLPLFFS = PIPERX7EQLPLFFS_delay; + assign #(out_delay) PIPERX7EQLPTXPRESET = PIPERX7EQLPTXPRESET_delay; + assign #(out_delay) PIPERX7EQPRESET = PIPERX7EQPRESET_delay; + assign #(out_delay) PIPERX7POLARITY = PIPERX7POLARITY_delay; + assign #(out_delay) PIPETX0CHARISK = PIPETX0CHARISK_delay; + assign #(out_delay) PIPETX0COMPLIANCE = PIPETX0COMPLIANCE_delay; + assign #(out_delay) PIPETX0DATA = PIPETX0DATA_delay; + assign #(out_delay) PIPETX0DATAVALID = PIPETX0DATAVALID_delay; + assign #(out_delay) PIPETX0DEEMPH = PIPETX0DEEMPH_delay; + assign #(out_delay) PIPETX0ELECIDLE = PIPETX0ELECIDLE_delay; + assign #(out_delay) PIPETX0EQCONTROL = PIPETX0EQCONTROL_delay; + assign #(out_delay) PIPETX0EQDEEMPH = PIPETX0EQDEEMPH_delay; + assign #(out_delay) PIPETX0EQPRESET = PIPETX0EQPRESET_delay; + assign #(out_delay) PIPETX0MARGIN = PIPETX0MARGIN_delay; + assign #(out_delay) PIPETX0POWERDOWN = PIPETX0POWERDOWN_delay; + assign #(out_delay) PIPETX0RATE = PIPETX0RATE_delay; + assign #(out_delay) PIPETX0RCVRDET = PIPETX0RCVRDET_delay; + assign #(out_delay) PIPETX0RESET = PIPETX0RESET_delay; + assign #(out_delay) PIPETX0STARTBLOCK = PIPETX0STARTBLOCK_delay; + assign #(out_delay) PIPETX0SWING = PIPETX0SWING_delay; + assign #(out_delay) PIPETX0SYNCHEADER = PIPETX0SYNCHEADER_delay; + assign #(out_delay) PIPETX1CHARISK = PIPETX1CHARISK_delay; + assign #(out_delay) PIPETX1COMPLIANCE = PIPETX1COMPLIANCE_delay; + assign #(out_delay) PIPETX1DATA = PIPETX1DATA_delay; + assign #(out_delay) PIPETX1DATAVALID = PIPETX1DATAVALID_delay; + assign #(out_delay) PIPETX1DEEMPH = PIPETX1DEEMPH_delay; + assign #(out_delay) PIPETX1ELECIDLE = PIPETX1ELECIDLE_delay; + assign #(out_delay) PIPETX1EQCONTROL = PIPETX1EQCONTROL_delay; + assign #(out_delay) PIPETX1EQDEEMPH = PIPETX1EQDEEMPH_delay; + assign #(out_delay) PIPETX1EQPRESET = PIPETX1EQPRESET_delay; + assign #(out_delay) PIPETX1MARGIN = PIPETX1MARGIN_delay; + assign #(out_delay) PIPETX1POWERDOWN = PIPETX1POWERDOWN_delay; + assign #(out_delay) PIPETX1RATE = PIPETX1RATE_delay; + assign #(out_delay) PIPETX1RCVRDET = PIPETX1RCVRDET_delay; + assign #(out_delay) PIPETX1RESET = PIPETX1RESET_delay; + assign #(out_delay) PIPETX1STARTBLOCK = PIPETX1STARTBLOCK_delay; + assign #(out_delay) PIPETX1SWING = PIPETX1SWING_delay; + assign #(out_delay) PIPETX1SYNCHEADER = PIPETX1SYNCHEADER_delay; + assign #(out_delay) PIPETX2CHARISK = PIPETX2CHARISK_delay; + assign #(out_delay) PIPETX2COMPLIANCE = PIPETX2COMPLIANCE_delay; + assign #(out_delay) PIPETX2DATA = PIPETX2DATA_delay; + assign #(out_delay) PIPETX2DATAVALID = PIPETX2DATAVALID_delay; + assign #(out_delay) PIPETX2DEEMPH = PIPETX2DEEMPH_delay; + assign #(out_delay) PIPETX2ELECIDLE = PIPETX2ELECIDLE_delay; + assign #(out_delay) PIPETX2EQCONTROL = PIPETX2EQCONTROL_delay; + assign #(out_delay) PIPETX2EQDEEMPH = PIPETX2EQDEEMPH_delay; + assign #(out_delay) PIPETX2EQPRESET = PIPETX2EQPRESET_delay; + assign #(out_delay) PIPETX2MARGIN = PIPETX2MARGIN_delay; + assign #(out_delay) PIPETX2POWERDOWN = PIPETX2POWERDOWN_delay; + assign #(out_delay) PIPETX2RATE = PIPETX2RATE_delay; + assign #(out_delay) PIPETX2RCVRDET = PIPETX2RCVRDET_delay; + assign #(out_delay) PIPETX2RESET = PIPETX2RESET_delay; + assign #(out_delay) PIPETX2STARTBLOCK = PIPETX2STARTBLOCK_delay; + assign #(out_delay) PIPETX2SWING = PIPETX2SWING_delay; + assign #(out_delay) PIPETX2SYNCHEADER = PIPETX2SYNCHEADER_delay; + assign #(out_delay) PIPETX3CHARISK = PIPETX3CHARISK_delay; + assign #(out_delay) PIPETX3COMPLIANCE = PIPETX3COMPLIANCE_delay; + assign #(out_delay) PIPETX3DATA = PIPETX3DATA_delay; + assign #(out_delay) PIPETX3DATAVALID = PIPETX3DATAVALID_delay; + assign #(out_delay) PIPETX3DEEMPH = PIPETX3DEEMPH_delay; + assign #(out_delay) PIPETX3ELECIDLE = PIPETX3ELECIDLE_delay; + assign #(out_delay) PIPETX3EQCONTROL = PIPETX3EQCONTROL_delay; + assign #(out_delay) PIPETX3EQDEEMPH = PIPETX3EQDEEMPH_delay; + assign #(out_delay) PIPETX3EQPRESET = PIPETX3EQPRESET_delay; + assign #(out_delay) PIPETX3MARGIN = PIPETX3MARGIN_delay; + assign #(out_delay) PIPETX3POWERDOWN = PIPETX3POWERDOWN_delay; + assign #(out_delay) PIPETX3RATE = PIPETX3RATE_delay; + assign #(out_delay) PIPETX3RCVRDET = PIPETX3RCVRDET_delay; + assign #(out_delay) PIPETX3RESET = PIPETX3RESET_delay; + assign #(out_delay) PIPETX3STARTBLOCK = PIPETX3STARTBLOCK_delay; + assign #(out_delay) PIPETX3SWING = PIPETX3SWING_delay; + assign #(out_delay) PIPETX3SYNCHEADER = PIPETX3SYNCHEADER_delay; + assign #(out_delay) PIPETX4CHARISK = PIPETX4CHARISK_delay; + assign #(out_delay) PIPETX4COMPLIANCE = PIPETX4COMPLIANCE_delay; + assign #(out_delay) PIPETX4DATA = PIPETX4DATA_delay; + assign #(out_delay) PIPETX4DATAVALID = PIPETX4DATAVALID_delay; + assign #(out_delay) PIPETX4DEEMPH = PIPETX4DEEMPH_delay; + assign #(out_delay) PIPETX4ELECIDLE = PIPETX4ELECIDLE_delay; + assign #(out_delay) PIPETX4EQCONTROL = PIPETX4EQCONTROL_delay; + assign #(out_delay) PIPETX4EQDEEMPH = PIPETX4EQDEEMPH_delay; + assign #(out_delay) PIPETX4EQPRESET = PIPETX4EQPRESET_delay; + assign #(out_delay) PIPETX4MARGIN = PIPETX4MARGIN_delay; + assign #(out_delay) PIPETX4POWERDOWN = PIPETX4POWERDOWN_delay; + assign #(out_delay) PIPETX4RATE = PIPETX4RATE_delay; + assign #(out_delay) PIPETX4RCVRDET = PIPETX4RCVRDET_delay; + assign #(out_delay) PIPETX4RESET = PIPETX4RESET_delay; + assign #(out_delay) PIPETX4STARTBLOCK = PIPETX4STARTBLOCK_delay; + assign #(out_delay) PIPETX4SWING = PIPETX4SWING_delay; + assign #(out_delay) PIPETX4SYNCHEADER = PIPETX4SYNCHEADER_delay; + assign #(out_delay) PIPETX5CHARISK = PIPETX5CHARISK_delay; + assign #(out_delay) PIPETX5COMPLIANCE = PIPETX5COMPLIANCE_delay; + assign #(out_delay) PIPETX5DATA = PIPETX5DATA_delay; + assign #(out_delay) PIPETX5DATAVALID = PIPETX5DATAVALID_delay; + assign #(out_delay) PIPETX5DEEMPH = PIPETX5DEEMPH_delay; + assign #(out_delay) PIPETX5ELECIDLE = PIPETX5ELECIDLE_delay; + assign #(out_delay) PIPETX5EQCONTROL = PIPETX5EQCONTROL_delay; + assign #(out_delay) PIPETX5EQDEEMPH = PIPETX5EQDEEMPH_delay; + assign #(out_delay) PIPETX5EQPRESET = PIPETX5EQPRESET_delay; + assign #(out_delay) PIPETX5MARGIN = PIPETX5MARGIN_delay; + assign #(out_delay) PIPETX5POWERDOWN = PIPETX5POWERDOWN_delay; + assign #(out_delay) PIPETX5RATE = PIPETX5RATE_delay; + assign #(out_delay) PIPETX5RCVRDET = PIPETX5RCVRDET_delay; + assign #(out_delay) PIPETX5RESET = PIPETX5RESET_delay; + assign #(out_delay) PIPETX5STARTBLOCK = PIPETX5STARTBLOCK_delay; + assign #(out_delay) PIPETX5SWING = PIPETX5SWING_delay; + assign #(out_delay) PIPETX5SYNCHEADER = PIPETX5SYNCHEADER_delay; + assign #(out_delay) PIPETX6CHARISK = PIPETX6CHARISK_delay; + assign #(out_delay) PIPETX6COMPLIANCE = PIPETX6COMPLIANCE_delay; + assign #(out_delay) PIPETX6DATA = PIPETX6DATA_delay; + assign #(out_delay) PIPETX6DATAVALID = PIPETX6DATAVALID_delay; + assign #(out_delay) PIPETX6DEEMPH = PIPETX6DEEMPH_delay; + assign #(out_delay) PIPETX6ELECIDLE = PIPETX6ELECIDLE_delay; + assign #(out_delay) PIPETX6EQCONTROL = PIPETX6EQCONTROL_delay; + assign #(out_delay) PIPETX6EQDEEMPH = PIPETX6EQDEEMPH_delay; + assign #(out_delay) PIPETX6EQPRESET = PIPETX6EQPRESET_delay; + assign #(out_delay) PIPETX6MARGIN = PIPETX6MARGIN_delay; + assign #(out_delay) PIPETX6POWERDOWN = PIPETX6POWERDOWN_delay; + assign #(out_delay) PIPETX6RATE = PIPETX6RATE_delay; + assign #(out_delay) PIPETX6RCVRDET = PIPETX6RCVRDET_delay; + assign #(out_delay) PIPETX6RESET = PIPETX6RESET_delay; + assign #(out_delay) PIPETX6STARTBLOCK = PIPETX6STARTBLOCK_delay; + assign #(out_delay) PIPETX6SWING = PIPETX6SWING_delay; + assign #(out_delay) PIPETX6SYNCHEADER = PIPETX6SYNCHEADER_delay; + assign #(out_delay) PIPETX7CHARISK = PIPETX7CHARISK_delay; + assign #(out_delay) PIPETX7COMPLIANCE = PIPETX7COMPLIANCE_delay; + assign #(out_delay) PIPETX7DATA = PIPETX7DATA_delay; + assign #(out_delay) PIPETX7DATAVALID = PIPETX7DATAVALID_delay; + assign #(out_delay) PIPETX7DEEMPH = PIPETX7DEEMPH_delay; + assign #(out_delay) PIPETX7ELECIDLE = PIPETX7ELECIDLE_delay; + assign #(out_delay) PIPETX7EQCONTROL = PIPETX7EQCONTROL_delay; + assign #(out_delay) PIPETX7EQDEEMPH = PIPETX7EQDEEMPH_delay; + assign #(out_delay) PIPETX7EQPRESET = PIPETX7EQPRESET_delay; + assign #(out_delay) PIPETX7MARGIN = PIPETX7MARGIN_delay; + assign #(out_delay) PIPETX7POWERDOWN = PIPETX7POWERDOWN_delay; + assign #(out_delay) PIPETX7RATE = PIPETX7RATE_delay; + assign #(out_delay) PIPETX7RCVRDET = PIPETX7RCVRDET_delay; + assign #(out_delay) PIPETX7RESET = PIPETX7RESET_delay; + assign #(out_delay) PIPETX7STARTBLOCK = PIPETX7STARTBLOCK_delay; + assign #(out_delay) PIPETX7SWING = PIPETX7SWING_delay; + assign #(out_delay) PIPETX7SYNCHEADER = PIPETX7SYNCHEADER_delay; + assign #(out_delay) PLEQINPROGRESS = PLEQINPROGRESS_delay; + assign #(out_delay) PLEQPHASE = PLEQPHASE_delay; + assign #(out_delay) SAXISCCTREADY = SAXISCCTREADY_delay; + assign #(out_delay) SAXISRQTREADY = SAXISRQTREADY_delay; + assign #(out_delay) SPAREOUT = SPAREOUT_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CORECLKMICOMPLETIONRAML_delay = CORECLKMICOMPLETIONRAML; + assign #(inclk_delay) CORECLKMICOMPLETIONRAMU_delay = CORECLKMICOMPLETIONRAMU; + assign #(inclk_delay) CORECLKMIREPLAYRAM_delay = CORECLKMIREPLAYRAM; + assign #(inclk_delay) CORECLKMIREQUESTRAM_delay = CORECLKMIREQUESTRAM; + assign #(inclk_delay) CORECLK_delay = CORECLK; + assign #(inclk_delay) DRPCLK_delay = DRPCLK; + assign #(inclk_delay) MCAPCLK_delay = MCAPCLK; + assign #(inclk_delay) PIPECLK_delay = PIPECLK; + assign #(inclk_delay) USERCLK_delay = USERCLK; + + assign #(in_delay) CFGCONFIGSPACEENABLE_delay = CFGCONFIGSPACEENABLE; + assign #(in_delay) CFGERRCORIN_delay = CFGERRCORIN; + assign #(in_delay) CFGERRUNCORIN_delay = CFGERRUNCORIN; + assign #(in_delay) CFGEXTREADDATAVALID_delay = CFGEXTREADDATAVALID; + assign #(in_delay) CFGHOTRESETIN_delay = CFGHOTRESETIN; + assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay = CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + assign #(in_delay) CFGINTERRUPTMSITPHPRESENT_delay = CFGINTERRUPTMSITPHPRESENT; + assign #(in_delay) CFGINTERRUPTMSIXINT_delay = CFGINTERRUPTMSIXINT; + assign #(in_delay) CFGLINKTRAININGENABLE_delay = CFGLINKTRAININGENABLE; + assign #(in_delay) CFGMGMTREAD_delay = CFGMGMTREAD; + assign #(in_delay) CFGMGMTTYPE1CFGREGACCESS_delay = CFGMGMTTYPE1CFGREGACCESS; + assign #(in_delay) CFGMGMTWRITE_delay = CFGMGMTWRITE; + assign #(in_delay) CFGMSGTRANSMIT_delay = CFGMSGTRANSMIT; + assign #(in_delay) CFGPERFUNCTIONOUTPUTREQUEST_delay = CFGPERFUNCTIONOUTPUTREQUEST; + assign #(in_delay) CFGPOWERSTATECHANGEACK_delay = CFGPOWERSTATECHANGEACK; + assign #(in_delay) CFGREQPMTRANSITIONL23READY_delay = CFGREQPMTRANSITIONL23READY; + assign #(in_delay) CFGTPHSTTREADDATAVALID_delay = CFGTPHSTTREADDATAVALID; + assign #(in_delay) CONFMCAPREQUESTBYCONF_delay = CONFMCAPREQUESTBYCONF; + assign #(in_delay) CONFREQVALID_delay = CONFREQVALID; + assign #(in_delay) DBGCFGLOCALMGMTREGOVERRIDE_delay = DBGCFGLOCALMGMTREGOVERRIDE; + assign #(in_delay) DRPEN_delay = DRPEN; + assign #(in_delay) DRPWE_delay = DRPWE; + assign #(in_delay) LL2LMSAXISTXTVALID_delay = LL2LMSAXISTXTVALID; + assign #(in_delay) PCIECQNPREQ_delay = PCIECQNPREQ; + assign #(in_delay) PIPERX0DATAVALID_delay = PIPERX0DATAVALID; + assign #(in_delay) PIPERX0ELECIDLE_delay = PIPERX0ELECIDLE; + assign #(in_delay) PIPERX0EQDONE_delay = PIPERX0EQDONE; + assign #(in_delay) PIPERX0EQLPADAPTDONE_delay = PIPERX0EQLPADAPTDONE; + assign #(in_delay) PIPERX0EQLPLFFSSEL_delay = PIPERX0EQLPLFFSSEL; + assign #(in_delay) PIPERX0PHYSTATUS_delay = PIPERX0PHYSTATUS; + assign #(in_delay) PIPERX0STARTBLOCK_delay = PIPERX0STARTBLOCK; + assign #(in_delay) PIPERX0VALID_delay = PIPERX0VALID; + assign #(in_delay) PIPERX1DATAVALID_delay = PIPERX1DATAVALID; + assign #(in_delay) PIPERX1ELECIDLE_delay = PIPERX1ELECIDLE; + assign #(in_delay) PIPERX1EQDONE_delay = PIPERX1EQDONE; + assign #(in_delay) PIPERX1EQLPADAPTDONE_delay = PIPERX1EQLPADAPTDONE; + assign #(in_delay) PIPERX1EQLPLFFSSEL_delay = PIPERX1EQLPLFFSSEL; + assign #(in_delay) PIPERX1PHYSTATUS_delay = PIPERX1PHYSTATUS; + assign #(in_delay) PIPERX1STARTBLOCK_delay = PIPERX1STARTBLOCK; + assign #(in_delay) PIPERX1VALID_delay = PIPERX1VALID; + assign #(in_delay) PIPERX2DATAVALID_delay = PIPERX2DATAVALID; + assign #(in_delay) PIPERX2ELECIDLE_delay = PIPERX2ELECIDLE; + assign #(in_delay) PIPERX2EQDONE_delay = PIPERX2EQDONE; + assign #(in_delay) PIPERX2EQLPADAPTDONE_delay = PIPERX2EQLPADAPTDONE; + assign #(in_delay) PIPERX2EQLPLFFSSEL_delay = PIPERX2EQLPLFFSSEL; + assign #(in_delay) PIPERX2PHYSTATUS_delay = PIPERX2PHYSTATUS; + assign #(in_delay) PIPERX2STARTBLOCK_delay = PIPERX2STARTBLOCK; + assign #(in_delay) PIPERX2VALID_delay = PIPERX2VALID; + assign #(in_delay) PIPERX3DATAVALID_delay = PIPERX3DATAVALID; + assign #(in_delay) PIPERX3ELECIDLE_delay = PIPERX3ELECIDLE; + assign #(in_delay) PIPERX3EQDONE_delay = PIPERX3EQDONE; + assign #(in_delay) PIPERX3EQLPADAPTDONE_delay = PIPERX3EQLPADAPTDONE; + assign #(in_delay) PIPERX3EQLPLFFSSEL_delay = PIPERX3EQLPLFFSSEL; + assign #(in_delay) PIPERX3PHYSTATUS_delay = PIPERX3PHYSTATUS; + assign #(in_delay) PIPERX3STARTBLOCK_delay = PIPERX3STARTBLOCK; + assign #(in_delay) PIPERX3VALID_delay = PIPERX3VALID; + assign #(in_delay) PIPERX4DATAVALID_delay = PIPERX4DATAVALID; + assign #(in_delay) PIPERX4ELECIDLE_delay = PIPERX4ELECIDLE; + assign #(in_delay) PIPERX4EQDONE_delay = PIPERX4EQDONE; + assign #(in_delay) PIPERX4EQLPADAPTDONE_delay = PIPERX4EQLPADAPTDONE; + assign #(in_delay) PIPERX4EQLPLFFSSEL_delay = PIPERX4EQLPLFFSSEL; + assign #(in_delay) PIPERX4PHYSTATUS_delay = PIPERX4PHYSTATUS; + assign #(in_delay) PIPERX4STARTBLOCK_delay = PIPERX4STARTBLOCK; + assign #(in_delay) PIPERX4VALID_delay = PIPERX4VALID; + assign #(in_delay) PIPERX5DATAVALID_delay = PIPERX5DATAVALID; + assign #(in_delay) PIPERX5ELECIDLE_delay = PIPERX5ELECIDLE; + assign #(in_delay) PIPERX5EQDONE_delay = PIPERX5EQDONE; + assign #(in_delay) PIPERX5EQLPADAPTDONE_delay = PIPERX5EQLPADAPTDONE; + assign #(in_delay) PIPERX5EQLPLFFSSEL_delay = PIPERX5EQLPLFFSSEL; + assign #(in_delay) PIPERX5PHYSTATUS_delay = PIPERX5PHYSTATUS; + assign #(in_delay) PIPERX5STARTBLOCK_delay = PIPERX5STARTBLOCK; + assign #(in_delay) PIPERX5VALID_delay = PIPERX5VALID; + assign #(in_delay) PIPERX6DATAVALID_delay = PIPERX6DATAVALID; + assign #(in_delay) PIPERX6ELECIDLE_delay = PIPERX6ELECIDLE; + assign #(in_delay) PIPERX6EQDONE_delay = PIPERX6EQDONE; + assign #(in_delay) PIPERX6EQLPADAPTDONE_delay = PIPERX6EQLPADAPTDONE; + assign #(in_delay) PIPERX6EQLPLFFSSEL_delay = PIPERX6EQLPLFFSSEL; + assign #(in_delay) PIPERX6PHYSTATUS_delay = PIPERX6PHYSTATUS; + assign #(in_delay) PIPERX6STARTBLOCK_delay = PIPERX6STARTBLOCK; + assign #(in_delay) PIPERX6VALID_delay = PIPERX6VALID; + assign #(in_delay) PIPERX7DATAVALID_delay = PIPERX7DATAVALID; + assign #(in_delay) PIPERX7ELECIDLE_delay = PIPERX7ELECIDLE; + assign #(in_delay) PIPERX7EQDONE_delay = PIPERX7EQDONE; + assign #(in_delay) PIPERX7EQLPADAPTDONE_delay = PIPERX7EQLPADAPTDONE; + assign #(in_delay) PIPERX7EQLPLFFSSEL_delay = PIPERX7EQLPLFFSSEL; + assign #(in_delay) PIPERX7PHYSTATUS_delay = PIPERX7PHYSTATUS; + assign #(in_delay) PIPERX7STARTBLOCK_delay = PIPERX7STARTBLOCK; + assign #(in_delay) PIPERX7VALID_delay = PIPERX7VALID; + assign #(in_delay) PIPETX0EQDONE_delay = PIPETX0EQDONE; + assign #(in_delay) PIPETX1EQDONE_delay = PIPETX1EQDONE; + assign #(in_delay) PIPETX2EQDONE_delay = PIPETX2EQDONE; + assign #(in_delay) PIPETX3EQDONE_delay = PIPETX3EQDONE; + assign #(in_delay) PIPETX4EQDONE_delay = PIPETX4EQDONE; + assign #(in_delay) PIPETX5EQDONE_delay = PIPETX5EQDONE; + assign #(in_delay) PIPETX6EQDONE_delay = PIPETX6EQDONE; + assign #(in_delay) PIPETX7EQDONE_delay = PIPETX7EQDONE; + assign #(in_delay) PLEQRESETEIEOSCOUNT_delay = PLEQRESETEIEOSCOUNT; + assign #(in_delay) PLGEN2UPSTREAMPREFERDEEMPH_delay = PLGEN2UPSTREAMPREFERDEEMPH; + assign #(in_delay) SAXISCCTLAST_delay = SAXISCCTLAST; + assign #(in_delay) SAXISCCTVALID_delay = SAXISCCTVALID; + assign #(in_delay) SAXISRQTLAST_delay = SAXISRQTLAST; + assign #(in_delay) SAXISRQTVALID_delay = SAXISRQTVALID; +`endif // `ifndef XIL_TIMING +// inputs with no timing checks + + assign #(in_delay) CFGDEVID_delay = CFGDEVID; + assign #(in_delay) CFGDSBUSNUMBER_delay = CFGDSBUSNUMBER; + assign #(in_delay) CFGDSDEVICENUMBER_delay = CFGDSDEVICENUMBER; + assign #(in_delay) CFGDSFUNCTIONNUMBER_delay = CFGDSFUNCTIONNUMBER; + assign #(in_delay) CFGDSN_delay = CFGDSN; + assign #(in_delay) CFGDSPORTNUMBER_delay = CFGDSPORTNUMBER; + assign #(in_delay) CFGEXTREADDATA_delay = CFGEXTREADDATA; + assign #(in_delay) CFGFCSEL_delay = CFGFCSEL; + assign #(in_delay) CFGFLRDONE_delay = CFGFLRDONE; + assign #(in_delay) CFGINTERRUPTINT_delay = CFGINTERRUPTINT; + assign #(in_delay) CFGINTERRUPTMSIATTR_delay = CFGINTERRUPTMSIATTR; + assign #(in_delay) CFGINTERRUPTMSIFUNCTIONNUMBER_delay = CFGINTERRUPTMSIFUNCTIONNUMBER; + assign #(in_delay) CFGINTERRUPTMSIINT_delay = CFGINTERRUPTMSIINT; + assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay = CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUS_delay = CFGINTERRUPTMSIPENDINGSTATUS; + assign #(in_delay) CFGINTERRUPTMSISELECT_delay = CFGINTERRUPTMSISELECT; + assign #(in_delay) CFGINTERRUPTMSITPHSTTAG_delay = CFGINTERRUPTMSITPHSTTAG; + assign #(in_delay) CFGINTERRUPTMSITPHTYPE_delay = CFGINTERRUPTMSITPHTYPE; + assign #(in_delay) CFGINTERRUPTMSIXADDRESS_delay = CFGINTERRUPTMSIXADDRESS; + assign #(in_delay) CFGINTERRUPTMSIXDATA_delay = CFGINTERRUPTMSIXDATA; + assign #(in_delay) CFGINTERRUPTPENDING_delay = CFGINTERRUPTPENDING; + assign #(in_delay) CFGMGMTADDR_delay = CFGMGMTADDR; + assign #(in_delay) CFGMGMTBYTEENABLE_delay = CFGMGMTBYTEENABLE; + assign #(in_delay) CFGMGMTWRITEDATA_delay = CFGMGMTWRITEDATA; + assign #(in_delay) CFGMSGTRANSMITDATA_delay = CFGMSGTRANSMITDATA; + assign #(in_delay) CFGMSGTRANSMITTYPE_delay = CFGMSGTRANSMITTYPE; + assign #(in_delay) CFGPERFUNCSTATUSCONTROL_delay = CFGPERFUNCSTATUSCONTROL; + assign #(in_delay) CFGPERFUNCTIONNUMBER_delay = CFGPERFUNCTIONNUMBER; + assign #(in_delay) CFGREVID_delay = CFGREVID; + assign #(in_delay) CFGSUBSYSID_delay = CFGSUBSYSID; + assign #(in_delay) CFGSUBSYSVENDID_delay = CFGSUBSYSVENDID; + assign #(in_delay) CFGTPHSTTREADDATA_delay = CFGTPHSTTREADDATA; + assign #(in_delay) CFGVENDID_delay = CFGVENDID; + assign #(in_delay) CFGVFFLRDONE_delay = CFGVFFLRDONE; + assign #(in_delay) CONFREQDATA_delay = CONFREQDATA; + assign #(in_delay) CONFREQREGNUM_delay = CONFREQREGNUM; + assign #(in_delay) CONFREQTYPE_delay = CONFREQTYPE; + assign #(in_delay) DBGDATASEL_delay = DBGDATASEL; + assign #(in_delay) DRPADDR_delay = DRPADDR; + assign #(in_delay) DRPDI_delay = DRPDI; + assign #(in_delay) LL2LMSAXISTXTUSER_delay = LL2LMSAXISTXTUSER; + assign #(in_delay) LL2LMTXTLPID0_delay = LL2LMTXTLPID0; + assign #(in_delay) LL2LMTXTLPID1_delay = LL2LMTXTLPID1; + assign #(in_delay) MAXISCQTREADY_delay = MAXISCQTREADY; + assign #(in_delay) MAXISRCTREADY_delay = MAXISRCTREADY; + assign #(in_delay) MCAPPERST0B_delay = MCAPPERST0B; + assign #(in_delay) MCAPPERST1B_delay = MCAPPERST1B; + assign #(in_delay) MGMTRESETN_delay = MGMTRESETN; + assign #(in_delay) MGMTSTICKYRESETN_delay = MGMTSTICKYRESETN; + assign #(in_delay) MICOMPLETIONRAMREADDATA_delay = MICOMPLETIONRAMREADDATA; + assign #(in_delay) MIREPLAYRAMREADDATA_delay = MIREPLAYRAMREADDATA; + assign #(in_delay) MIREQUESTRAMREADDATA_delay = MIREQUESTRAMREADDATA; + assign #(in_delay) PIPEEQFS_delay = PIPEEQFS; + assign #(in_delay) PIPEEQLF_delay = PIPEEQLF; + assign #(in_delay) PIPERESETN_delay = PIPERESETN; + assign #(in_delay) PIPERX0CHARISK_delay = PIPERX0CHARISK; + assign #(in_delay) PIPERX0DATA_delay = PIPERX0DATA; + assign #(in_delay) PIPERX0EQLPNEWTXCOEFFORPRESET_delay = PIPERX0EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX0STATUS_delay = PIPERX0STATUS; + assign #(in_delay) PIPERX0SYNCHEADER_delay = PIPERX0SYNCHEADER; + assign #(in_delay) PIPERX1CHARISK_delay = PIPERX1CHARISK; + assign #(in_delay) PIPERX1DATA_delay = PIPERX1DATA; + assign #(in_delay) PIPERX1EQLPNEWTXCOEFFORPRESET_delay = PIPERX1EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX1STATUS_delay = PIPERX1STATUS; + assign #(in_delay) PIPERX1SYNCHEADER_delay = PIPERX1SYNCHEADER; + assign #(in_delay) PIPERX2CHARISK_delay = PIPERX2CHARISK; + assign #(in_delay) PIPERX2DATA_delay = PIPERX2DATA; + assign #(in_delay) PIPERX2EQLPNEWTXCOEFFORPRESET_delay = PIPERX2EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX2STATUS_delay = PIPERX2STATUS; + assign #(in_delay) PIPERX2SYNCHEADER_delay = PIPERX2SYNCHEADER; + assign #(in_delay) PIPERX3CHARISK_delay = PIPERX3CHARISK; + assign #(in_delay) PIPERX3DATA_delay = PIPERX3DATA; + assign #(in_delay) PIPERX3EQLPNEWTXCOEFFORPRESET_delay = PIPERX3EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX3STATUS_delay = PIPERX3STATUS; + assign #(in_delay) PIPERX3SYNCHEADER_delay = PIPERX3SYNCHEADER; + assign #(in_delay) PIPERX4CHARISK_delay = PIPERX4CHARISK; + assign #(in_delay) PIPERX4DATA_delay = PIPERX4DATA; + assign #(in_delay) PIPERX4EQLPNEWTXCOEFFORPRESET_delay = PIPERX4EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX4STATUS_delay = PIPERX4STATUS; + assign #(in_delay) PIPERX4SYNCHEADER_delay = PIPERX4SYNCHEADER; + assign #(in_delay) PIPERX5CHARISK_delay = PIPERX5CHARISK; + assign #(in_delay) PIPERX5DATA_delay = PIPERX5DATA; + assign #(in_delay) PIPERX5EQLPNEWTXCOEFFORPRESET_delay = PIPERX5EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX5STATUS_delay = PIPERX5STATUS; + assign #(in_delay) PIPERX5SYNCHEADER_delay = PIPERX5SYNCHEADER; + assign #(in_delay) PIPERX6CHARISK_delay = PIPERX6CHARISK; + assign #(in_delay) PIPERX6DATA_delay = PIPERX6DATA; + assign #(in_delay) PIPERX6EQLPNEWTXCOEFFORPRESET_delay = PIPERX6EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX6STATUS_delay = PIPERX6STATUS; + assign #(in_delay) PIPERX6SYNCHEADER_delay = PIPERX6SYNCHEADER; + assign #(in_delay) PIPERX7CHARISK_delay = PIPERX7CHARISK; + assign #(in_delay) PIPERX7DATA_delay = PIPERX7DATA; + assign #(in_delay) PIPERX7EQLPNEWTXCOEFFORPRESET_delay = PIPERX7EQLPNEWTXCOEFFORPRESET; + assign #(in_delay) PIPERX7STATUS_delay = PIPERX7STATUS; + assign #(in_delay) PIPERX7SYNCHEADER_delay = PIPERX7SYNCHEADER; + assign #(in_delay) PIPETX0EQCOEFF_delay = PIPETX0EQCOEFF; + assign #(in_delay) PIPETX1EQCOEFF_delay = PIPETX1EQCOEFF; + assign #(in_delay) PIPETX2EQCOEFF_delay = PIPETX2EQCOEFF; + assign #(in_delay) PIPETX3EQCOEFF_delay = PIPETX3EQCOEFF; + assign #(in_delay) PIPETX4EQCOEFF_delay = PIPETX4EQCOEFF; + assign #(in_delay) PIPETX5EQCOEFF_delay = PIPETX5EQCOEFF; + assign #(in_delay) PIPETX6EQCOEFF_delay = PIPETX6EQCOEFF; + assign #(in_delay) PIPETX7EQCOEFF_delay = PIPETX7EQCOEFF; + assign #(in_delay) RESETN_delay = RESETN; + assign #(in_delay) SAXISCCTDATA_delay = SAXISCCTDATA; + assign #(in_delay) SAXISCCTKEEP_delay = SAXISCCTKEEP; + assign #(in_delay) SAXISCCTUSER_delay = SAXISCCTUSER; + assign #(in_delay) SAXISRQTDATA_delay = SAXISRQTDATA; + assign #(in_delay) SAXISRQTKEEP_delay = SAXISRQTKEEP; + assign #(in_delay) SAXISRQTUSER_delay = SAXISRQTUSER; + assign #(in_delay) SPAREIN_delay = SPAREIN; + + assign CFGCURRENTSPEED_delay = CFGCURRENTSPEED_out; + assign CFGDPASUBSTATECHANGE_delay = CFGDPASUBSTATECHANGE_out; + assign CFGERRCOROUT_delay = CFGERRCOROUT_out; + assign CFGERRFATALOUT_delay = CFGERRFATALOUT_out; + assign CFGERRNONFATALOUT_delay = CFGERRNONFATALOUT_out; + assign CFGEXTFUNCTIONNUMBER_delay = CFGEXTFUNCTIONNUMBER_out; + assign CFGEXTREADRECEIVED_delay = CFGEXTREADRECEIVED_out; + assign CFGEXTREGISTERNUMBER_delay = CFGEXTREGISTERNUMBER_out; + assign CFGEXTWRITEBYTEENABLE_delay = CFGEXTWRITEBYTEENABLE_out; + assign CFGEXTWRITEDATA_delay = CFGEXTWRITEDATA_out; + assign CFGEXTWRITERECEIVED_delay = CFGEXTWRITERECEIVED_out; + assign CFGFCCPLD_delay = CFGFCCPLD_out; + assign CFGFCCPLH_delay = CFGFCCPLH_out; + assign CFGFCNPD_delay = CFGFCNPD_out; + assign CFGFCNPH_delay = CFGFCNPH_out; + assign CFGFCPD_delay = CFGFCPD_out; + assign CFGFCPH_delay = CFGFCPH_out; + assign CFGFLRINPROCESS_delay = CFGFLRINPROCESS_out; + assign CFGFUNCTIONPOWERSTATE_delay = CFGFUNCTIONPOWERSTATE_out; + assign CFGFUNCTIONSTATUS_delay = CFGFUNCTIONSTATUS_out; + assign CFGHOTRESETOUT_delay = CFGHOTRESETOUT_out; + assign CFGINTERRUPTMSIDATA_delay = CFGINTERRUPTMSIDATA_out; + assign CFGINTERRUPTMSIENABLE_delay = CFGINTERRUPTMSIENABLE_out; + assign CFGINTERRUPTMSIFAIL_delay = CFGINTERRUPTMSIFAIL_out; + assign CFGINTERRUPTMSIMASKUPDATE_delay = CFGINTERRUPTMSIMASKUPDATE_out; + assign CFGINTERRUPTMSIMMENABLE_delay = CFGINTERRUPTMSIMMENABLE_out; + assign CFGINTERRUPTMSISENT_delay = CFGINTERRUPTMSISENT_out; + assign CFGINTERRUPTMSIVFENABLE_delay = CFGINTERRUPTMSIVFENABLE_out; + assign CFGINTERRUPTMSIXENABLE_delay = CFGINTERRUPTMSIXENABLE_out; + assign CFGINTERRUPTMSIXFAIL_delay = CFGINTERRUPTMSIXFAIL_out; + assign CFGINTERRUPTMSIXMASK_delay = CFGINTERRUPTMSIXMASK_out; + assign CFGINTERRUPTMSIXSENT_delay = CFGINTERRUPTMSIXSENT_out; + assign CFGINTERRUPTMSIXVFENABLE_delay = CFGINTERRUPTMSIXVFENABLE_out; + assign CFGINTERRUPTMSIXVFMASK_delay = CFGINTERRUPTMSIXVFMASK_out; + assign CFGINTERRUPTSENT_delay = CFGINTERRUPTSENT_out; + assign CFGLINKPOWERSTATE_delay = CFGLINKPOWERSTATE_out; + assign CFGLOCALERROR_delay = CFGLOCALERROR_out; + assign CFGLTRENABLE_delay = CFGLTRENABLE_out; + assign CFGLTSSMSTATE_delay = CFGLTSSMSTATE_out; + assign CFGMAXPAYLOAD_delay = CFGMAXPAYLOAD_out; + assign CFGMAXREADREQ_delay = CFGMAXREADREQ_out; + assign CFGMGMTREADDATA_delay = CFGMGMTREADDATA_out; + assign CFGMGMTREADWRITEDONE_delay = CFGMGMTREADWRITEDONE_out; + assign CFGMSGRECEIVEDDATA_delay = CFGMSGRECEIVEDDATA_out; + assign CFGMSGRECEIVEDTYPE_delay = CFGMSGRECEIVEDTYPE_out; + assign CFGMSGRECEIVED_delay = CFGMSGRECEIVED_out; + assign CFGMSGTRANSMITDONE_delay = CFGMSGTRANSMITDONE_out; + assign CFGNEGOTIATEDWIDTH_delay = CFGNEGOTIATEDWIDTH_out; + assign CFGOBFFENABLE_delay = CFGOBFFENABLE_out; + assign CFGPERFUNCSTATUSDATA_delay = CFGPERFUNCSTATUSDATA_out; + assign CFGPERFUNCTIONUPDATEDONE_delay = CFGPERFUNCTIONUPDATEDONE_out; + assign CFGPHYLINKDOWN_delay = CFGPHYLINKDOWN_out; + assign CFGPHYLINKSTATUS_delay = CFGPHYLINKSTATUS_out; + assign CFGPLSTATUSCHANGE_delay = CFGPLSTATUSCHANGE_out; + assign CFGPOWERSTATECHANGEINTERRUPT_delay = CFGPOWERSTATECHANGEINTERRUPT_out; + assign CFGRCBSTATUS_delay = CFGRCBSTATUS_out; + assign CFGTPHFUNCTIONNUM_delay = CFGTPHFUNCTIONNUM_out; + assign CFGTPHREQUESTERENABLE_delay = CFGTPHREQUESTERENABLE_out; + assign CFGTPHSTMODE_delay = CFGTPHSTMODE_out; + assign CFGTPHSTTADDRESS_delay = CFGTPHSTTADDRESS_out; + assign CFGTPHSTTREADENABLE_delay = CFGTPHSTTREADENABLE_out; + assign CFGTPHSTTWRITEBYTEVALID_delay = CFGTPHSTTWRITEBYTEVALID_out; + assign CFGTPHSTTWRITEDATA_delay = CFGTPHSTTWRITEDATA_out; + assign CFGTPHSTTWRITEENABLE_delay = CFGTPHSTTWRITEENABLE_out; + assign CFGVFFLRINPROCESS_delay = CFGVFFLRINPROCESS_out; + assign CFGVFPOWERSTATE_delay = CFGVFPOWERSTATE_out; + assign CFGVFSTATUS_delay = CFGVFSTATUS_out; + assign CFGVFTPHREQUESTERENABLE_delay = CFGVFTPHREQUESTERENABLE_out; + assign CFGVFTPHSTMODE_delay = CFGVFTPHSTMODE_out; + assign CONFMCAPDESIGNSWITCH_delay = CONFMCAPDESIGNSWITCH_out; + assign CONFMCAPEOS_delay = CONFMCAPEOS_out; + assign CONFMCAPINUSEBYPCIE_delay = CONFMCAPINUSEBYPCIE_out; + assign CONFREQREADY_delay = CONFREQREADY_out; + assign CONFRESPRDATA_delay = CONFRESPRDATA_out; + assign CONFRESPVALID_delay = CONFRESPVALID_out; + assign DBGDATAOUT_delay = DBGDATAOUT_out; + assign DBGMCAPCSB_delay = DBGMCAPCSB_out; + assign DBGMCAPDATA_delay = DBGMCAPDATA_out; + assign DBGMCAPEOS_delay = DBGMCAPEOS_out; + assign DBGMCAPERROR_delay = DBGMCAPERROR_out; + assign DBGMCAPMODE_delay = DBGMCAPMODE_out; + assign DBGMCAPRDATAVALID_delay = DBGMCAPRDATAVALID_out; + assign DBGMCAPRDWRB_delay = DBGMCAPRDWRB_out; + assign DBGMCAPRESET_delay = DBGMCAPRESET_out; + assign DBGPLDATABLOCKRECEIVEDAFTEREDS_delay = DBGPLDATABLOCKRECEIVEDAFTEREDS_out; + assign DBGPLGEN3FRAMINGERRORDETECTED_delay = DBGPLGEN3FRAMINGERRORDETECTED_out; + assign DBGPLGEN3SYNCHEADERERRORDETECTED_delay = DBGPLGEN3SYNCHEADERERRORDETECTED_out; + assign DBGPLINFERREDRXELECTRICALIDLE_delay = DBGPLINFERREDRXELECTRICALIDLE_out; + assign DRPDO_delay = DRPDO_out; + assign DRPRDY_delay = DRPRDY_out; + assign LL2LMMASTERTLPSENT0_delay = LL2LMMASTERTLPSENT0_out; + assign LL2LMMASTERTLPSENT1_delay = LL2LMMASTERTLPSENT1_out; + assign LL2LMMASTERTLPSENTTLPID0_delay = LL2LMMASTERTLPSENTTLPID0_out; + assign LL2LMMASTERTLPSENTTLPID1_delay = LL2LMMASTERTLPSENTTLPID1_out; + assign LL2LMMAXISRXTDATA_delay = LL2LMMAXISRXTDATA_out; + assign LL2LMMAXISRXTUSER_delay = LL2LMMAXISRXTUSER_out; + assign LL2LMMAXISRXTVALID_delay = LL2LMMAXISRXTVALID_out; + assign LL2LMSAXISTXTREADY_delay = LL2LMSAXISTXTREADY_out; + assign MAXISCQTDATA_delay = MAXISCQTDATA_out; + assign MAXISCQTKEEP_delay = MAXISCQTKEEP_out; + assign MAXISCQTLAST_delay = MAXISCQTLAST_out; + assign MAXISCQTUSER_delay = MAXISCQTUSER_out; + assign MAXISCQTVALID_delay = MAXISCQTVALID_out; + assign MAXISRCTDATA_delay = MAXISRCTDATA_out; + assign MAXISRCTKEEP_delay = MAXISRCTKEEP_out; + assign MAXISRCTLAST_delay = MAXISRCTLAST_out; + assign MAXISRCTUSER_delay = MAXISRCTUSER_out; + assign MAXISRCTVALID_delay = MAXISRCTVALID_out; + assign MICOMPLETIONRAMREADADDRESSAL_delay = MICOMPLETIONRAMREADADDRESSAL_out; + assign MICOMPLETIONRAMREADADDRESSAU_delay = MICOMPLETIONRAMREADADDRESSAU_out; + assign MICOMPLETIONRAMREADADDRESSBL_delay = MICOMPLETIONRAMREADADDRESSBL_out; + assign MICOMPLETIONRAMREADADDRESSBU_delay = MICOMPLETIONRAMREADADDRESSBU_out; + assign MICOMPLETIONRAMREADENABLEL_delay = MICOMPLETIONRAMREADENABLEL_out; + assign MICOMPLETIONRAMREADENABLEU_delay = MICOMPLETIONRAMREADENABLEU_out; + assign MICOMPLETIONRAMWRITEADDRESSAL_delay = MICOMPLETIONRAMWRITEADDRESSAL_out; + assign MICOMPLETIONRAMWRITEADDRESSAU_delay = MICOMPLETIONRAMWRITEADDRESSAU_out; + assign MICOMPLETIONRAMWRITEADDRESSBL_delay = MICOMPLETIONRAMWRITEADDRESSBL_out; + assign MICOMPLETIONRAMWRITEADDRESSBU_delay = MICOMPLETIONRAMWRITEADDRESSBU_out; + assign MICOMPLETIONRAMWRITEDATAL_delay = MICOMPLETIONRAMWRITEDATAL_out; + assign MICOMPLETIONRAMWRITEDATAU_delay = MICOMPLETIONRAMWRITEDATAU_out; + assign MICOMPLETIONRAMWRITEENABLEL_delay = MICOMPLETIONRAMWRITEENABLEL_out; + assign MICOMPLETIONRAMWRITEENABLEU_delay = MICOMPLETIONRAMWRITEENABLEU_out; + assign MIREPLAYRAMADDRESS_delay = MIREPLAYRAMADDRESS_out; + assign MIREPLAYRAMREADENABLE_delay = MIREPLAYRAMREADENABLE_out; + assign MIREPLAYRAMWRITEDATA_delay = MIREPLAYRAMWRITEDATA_out; + assign MIREPLAYRAMWRITEENABLE_delay = MIREPLAYRAMWRITEENABLE_out; + assign MIREQUESTRAMREADADDRESSA_delay = MIREQUESTRAMREADADDRESSA_out; + assign MIREQUESTRAMREADADDRESSB_delay = MIREQUESTRAMREADADDRESSB_out; + assign MIREQUESTRAMREADENABLE_delay = MIREQUESTRAMREADENABLE_out; + assign MIREQUESTRAMWRITEADDRESSA_delay = MIREQUESTRAMWRITEADDRESSA_out; + assign MIREQUESTRAMWRITEADDRESSB_delay = MIREQUESTRAMWRITEADDRESSB_out; + assign MIREQUESTRAMWRITEDATA_delay = MIREQUESTRAMWRITEDATA_out; + assign MIREQUESTRAMWRITEENABLE_delay = MIREQUESTRAMWRITEENABLE_out; + assign PCIECQNPREQCOUNT_delay = PCIECQNPREQCOUNT_out; + assign PCIEPERST0B_delay = PCIEPERST0B_out; + assign PCIEPERST1B_delay = PCIEPERST1B_out; + assign PCIERQSEQNUMVLD_delay = PCIERQSEQNUMVLD_out; + assign PCIERQSEQNUM_delay = PCIERQSEQNUM_out; + assign PCIERQTAGAV_delay = PCIERQTAGAV_out; + assign PCIERQTAGVLD_delay = PCIERQTAGVLD_out; + assign PCIERQTAG_delay = PCIERQTAG_out; + assign PCIETFCNPDAV_delay = PCIETFCNPDAV_out; + assign PCIETFCNPHAV_delay = PCIETFCNPHAV_out; + assign PIPERX0EQCONTROL_delay = PIPERX0EQCONTROL_out; + assign PIPERX0EQLPLFFS_delay = PIPERX0EQLPLFFS_out; + assign PIPERX0EQLPTXPRESET_delay = PIPERX0EQLPTXPRESET_out; + assign PIPERX0EQPRESET_delay = PIPERX0EQPRESET_out; + assign PIPERX0POLARITY_delay = PIPERX0POLARITY_out; + assign PIPERX1EQCONTROL_delay = PIPERX1EQCONTROL_out; + assign PIPERX1EQLPLFFS_delay = PIPERX1EQLPLFFS_out; + assign PIPERX1EQLPTXPRESET_delay = PIPERX1EQLPTXPRESET_out; + assign PIPERX1EQPRESET_delay = PIPERX1EQPRESET_out; + assign PIPERX1POLARITY_delay = PIPERX1POLARITY_out; + assign PIPERX2EQCONTROL_delay = PIPERX2EQCONTROL_out; + assign PIPERX2EQLPLFFS_delay = PIPERX2EQLPLFFS_out; + assign PIPERX2EQLPTXPRESET_delay = PIPERX2EQLPTXPRESET_out; + assign PIPERX2EQPRESET_delay = PIPERX2EQPRESET_out; + assign PIPERX2POLARITY_delay = PIPERX2POLARITY_out; + assign PIPERX3EQCONTROL_delay = PIPERX3EQCONTROL_out; + assign PIPERX3EQLPLFFS_delay = PIPERX3EQLPLFFS_out; + assign PIPERX3EQLPTXPRESET_delay = PIPERX3EQLPTXPRESET_out; + assign PIPERX3EQPRESET_delay = PIPERX3EQPRESET_out; + assign PIPERX3POLARITY_delay = PIPERX3POLARITY_out; + assign PIPERX4EQCONTROL_delay = PIPERX4EQCONTROL_out; + assign PIPERX4EQLPLFFS_delay = PIPERX4EQLPLFFS_out; + assign PIPERX4EQLPTXPRESET_delay = PIPERX4EQLPTXPRESET_out; + assign PIPERX4EQPRESET_delay = PIPERX4EQPRESET_out; + assign PIPERX4POLARITY_delay = PIPERX4POLARITY_out; + assign PIPERX5EQCONTROL_delay = PIPERX5EQCONTROL_out; + assign PIPERX5EQLPLFFS_delay = PIPERX5EQLPLFFS_out; + assign PIPERX5EQLPTXPRESET_delay = PIPERX5EQLPTXPRESET_out; + assign PIPERX5EQPRESET_delay = PIPERX5EQPRESET_out; + assign PIPERX5POLARITY_delay = PIPERX5POLARITY_out; + assign PIPERX6EQCONTROL_delay = PIPERX6EQCONTROL_out; + assign PIPERX6EQLPLFFS_delay = PIPERX6EQLPLFFS_out; + assign PIPERX6EQLPTXPRESET_delay = PIPERX6EQLPTXPRESET_out; + assign PIPERX6EQPRESET_delay = PIPERX6EQPRESET_out; + assign PIPERX6POLARITY_delay = PIPERX6POLARITY_out; + assign PIPERX7EQCONTROL_delay = PIPERX7EQCONTROL_out; + assign PIPERX7EQLPLFFS_delay = PIPERX7EQLPLFFS_out; + assign PIPERX7EQLPTXPRESET_delay = PIPERX7EQLPTXPRESET_out; + assign PIPERX7EQPRESET_delay = PIPERX7EQPRESET_out; + assign PIPERX7POLARITY_delay = PIPERX7POLARITY_out; + assign PIPETX0CHARISK_delay = PIPETX0CHARISK_out; + assign PIPETX0COMPLIANCE_delay = PIPETX0COMPLIANCE_out; + assign PIPETX0DATAVALID_delay = PIPETX0DATAVALID_out; + assign PIPETX0DATA_delay = PIPETX0DATA_out; + assign PIPETX0DEEMPH_delay = PIPETX0DEEMPH_out; + assign PIPETX0ELECIDLE_delay = PIPETX0ELECIDLE_out; + assign PIPETX0EQCONTROL_delay = PIPETX0EQCONTROL_out; + assign PIPETX0EQDEEMPH_delay = PIPETX0EQDEEMPH_out; + assign PIPETX0EQPRESET_delay = PIPETX0EQPRESET_out; + assign PIPETX0MARGIN_delay = PIPETX0MARGIN_out; + assign PIPETX0POWERDOWN_delay = PIPETX0POWERDOWN_out; + assign PIPETX0RATE_delay = PIPETX0RATE_out; + assign PIPETX0RCVRDET_delay = PIPETX0RCVRDET_out; + assign PIPETX0RESET_delay = PIPETX0RESET_out; + assign PIPETX0STARTBLOCK_delay = PIPETX0STARTBLOCK_out; + assign PIPETX0SWING_delay = PIPETX0SWING_out; + assign PIPETX0SYNCHEADER_delay = PIPETX0SYNCHEADER_out; + assign PIPETX1CHARISK_delay = PIPETX1CHARISK_out; + assign PIPETX1COMPLIANCE_delay = PIPETX1COMPLIANCE_out; + assign PIPETX1DATAVALID_delay = PIPETX1DATAVALID_out; + assign PIPETX1DATA_delay = PIPETX1DATA_out; + assign PIPETX1DEEMPH_delay = PIPETX1DEEMPH_out; + assign PIPETX1ELECIDLE_delay = PIPETX1ELECIDLE_out; + assign PIPETX1EQCONTROL_delay = PIPETX1EQCONTROL_out; + assign PIPETX1EQDEEMPH_delay = PIPETX1EQDEEMPH_out; + assign PIPETX1EQPRESET_delay = PIPETX1EQPRESET_out; + assign PIPETX1MARGIN_delay = PIPETX1MARGIN_out; + assign PIPETX1POWERDOWN_delay = PIPETX1POWERDOWN_out; + assign PIPETX1RATE_delay = PIPETX1RATE_out; + assign PIPETX1RCVRDET_delay = PIPETX1RCVRDET_out; + assign PIPETX1RESET_delay = PIPETX1RESET_out; + assign PIPETX1STARTBLOCK_delay = PIPETX1STARTBLOCK_out; + assign PIPETX1SWING_delay = PIPETX1SWING_out; + assign PIPETX1SYNCHEADER_delay = PIPETX1SYNCHEADER_out; + assign PIPETX2CHARISK_delay = PIPETX2CHARISK_out; + assign PIPETX2COMPLIANCE_delay = PIPETX2COMPLIANCE_out; + assign PIPETX2DATAVALID_delay = PIPETX2DATAVALID_out; + assign PIPETX2DATA_delay = PIPETX2DATA_out; + assign PIPETX2DEEMPH_delay = PIPETX2DEEMPH_out; + assign PIPETX2ELECIDLE_delay = PIPETX2ELECIDLE_out; + assign PIPETX2EQCONTROL_delay = PIPETX2EQCONTROL_out; + assign PIPETX2EQDEEMPH_delay = PIPETX2EQDEEMPH_out; + assign PIPETX2EQPRESET_delay = PIPETX2EQPRESET_out; + assign PIPETX2MARGIN_delay = PIPETX2MARGIN_out; + assign PIPETX2POWERDOWN_delay = PIPETX2POWERDOWN_out; + assign PIPETX2RATE_delay = PIPETX2RATE_out; + assign PIPETX2RCVRDET_delay = PIPETX2RCVRDET_out; + assign PIPETX2RESET_delay = PIPETX2RESET_out; + assign PIPETX2STARTBLOCK_delay = PIPETX2STARTBLOCK_out; + assign PIPETX2SWING_delay = PIPETX2SWING_out; + assign PIPETX2SYNCHEADER_delay = PIPETX2SYNCHEADER_out; + assign PIPETX3CHARISK_delay = PIPETX3CHARISK_out; + assign PIPETX3COMPLIANCE_delay = PIPETX3COMPLIANCE_out; + assign PIPETX3DATAVALID_delay = PIPETX3DATAVALID_out; + assign PIPETX3DATA_delay = PIPETX3DATA_out; + assign PIPETX3DEEMPH_delay = PIPETX3DEEMPH_out; + assign PIPETX3ELECIDLE_delay = PIPETX3ELECIDLE_out; + assign PIPETX3EQCONTROL_delay = PIPETX3EQCONTROL_out; + assign PIPETX3EQDEEMPH_delay = PIPETX3EQDEEMPH_out; + assign PIPETX3EQPRESET_delay = PIPETX3EQPRESET_out; + assign PIPETX3MARGIN_delay = PIPETX3MARGIN_out; + assign PIPETX3POWERDOWN_delay = PIPETX3POWERDOWN_out; + assign PIPETX3RATE_delay = PIPETX3RATE_out; + assign PIPETX3RCVRDET_delay = PIPETX3RCVRDET_out; + assign PIPETX3RESET_delay = PIPETX3RESET_out; + assign PIPETX3STARTBLOCK_delay = PIPETX3STARTBLOCK_out; + assign PIPETX3SWING_delay = PIPETX3SWING_out; + assign PIPETX3SYNCHEADER_delay = PIPETX3SYNCHEADER_out; + assign PIPETX4CHARISK_delay = PIPETX4CHARISK_out; + assign PIPETX4COMPLIANCE_delay = PIPETX4COMPLIANCE_out; + assign PIPETX4DATAVALID_delay = PIPETX4DATAVALID_out; + assign PIPETX4DATA_delay = PIPETX4DATA_out; + assign PIPETX4DEEMPH_delay = PIPETX4DEEMPH_out; + assign PIPETX4ELECIDLE_delay = PIPETX4ELECIDLE_out; + assign PIPETX4EQCONTROL_delay = PIPETX4EQCONTROL_out; + assign PIPETX4EQDEEMPH_delay = PIPETX4EQDEEMPH_out; + assign PIPETX4EQPRESET_delay = PIPETX4EQPRESET_out; + assign PIPETX4MARGIN_delay = PIPETX4MARGIN_out; + assign PIPETX4POWERDOWN_delay = PIPETX4POWERDOWN_out; + assign PIPETX4RATE_delay = PIPETX4RATE_out; + assign PIPETX4RCVRDET_delay = PIPETX4RCVRDET_out; + assign PIPETX4RESET_delay = PIPETX4RESET_out; + assign PIPETX4STARTBLOCK_delay = PIPETX4STARTBLOCK_out; + assign PIPETX4SWING_delay = PIPETX4SWING_out; + assign PIPETX4SYNCHEADER_delay = PIPETX4SYNCHEADER_out; + assign PIPETX5CHARISK_delay = PIPETX5CHARISK_out; + assign PIPETX5COMPLIANCE_delay = PIPETX5COMPLIANCE_out; + assign PIPETX5DATAVALID_delay = PIPETX5DATAVALID_out; + assign PIPETX5DATA_delay = PIPETX5DATA_out; + assign PIPETX5DEEMPH_delay = PIPETX5DEEMPH_out; + assign PIPETX5ELECIDLE_delay = PIPETX5ELECIDLE_out; + assign PIPETX5EQCONTROL_delay = PIPETX5EQCONTROL_out; + assign PIPETX5EQDEEMPH_delay = PIPETX5EQDEEMPH_out; + assign PIPETX5EQPRESET_delay = PIPETX5EQPRESET_out; + assign PIPETX5MARGIN_delay = PIPETX5MARGIN_out; + assign PIPETX5POWERDOWN_delay = PIPETX5POWERDOWN_out; + assign PIPETX5RATE_delay = PIPETX5RATE_out; + assign PIPETX5RCVRDET_delay = PIPETX5RCVRDET_out; + assign PIPETX5RESET_delay = PIPETX5RESET_out; + assign PIPETX5STARTBLOCK_delay = PIPETX5STARTBLOCK_out; + assign PIPETX5SWING_delay = PIPETX5SWING_out; + assign PIPETX5SYNCHEADER_delay = PIPETX5SYNCHEADER_out; + assign PIPETX6CHARISK_delay = PIPETX6CHARISK_out; + assign PIPETX6COMPLIANCE_delay = PIPETX6COMPLIANCE_out; + assign PIPETX6DATAVALID_delay = PIPETX6DATAVALID_out; + assign PIPETX6DATA_delay = PIPETX6DATA_out; + assign PIPETX6DEEMPH_delay = PIPETX6DEEMPH_out; + assign PIPETX6ELECIDLE_delay = PIPETX6ELECIDLE_out; + assign PIPETX6EQCONTROL_delay = PIPETX6EQCONTROL_out; + assign PIPETX6EQDEEMPH_delay = PIPETX6EQDEEMPH_out; + assign PIPETX6EQPRESET_delay = PIPETX6EQPRESET_out; + assign PIPETX6MARGIN_delay = PIPETX6MARGIN_out; + assign PIPETX6POWERDOWN_delay = PIPETX6POWERDOWN_out; + assign PIPETX6RATE_delay = PIPETX6RATE_out; + assign PIPETX6RCVRDET_delay = PIPETX6RCVRDET_out; + assign PIPETX6RESET_delay = PIPETX6RESET_out; + assign PIPETX6STARTBLOCK_delay = PIPETX6STARTBLOCK_out; + assign PIPETX6SWING_delay = PIPETX6SWING_out; + assign PIPETX6SYNCHEADER_delay = PIPETX6SYNCHEADER_out; + assign PIPETX7CHARISK_delay = PIPETX7CHARISK_out; + assign PIPETX7COMPLIANCE_delay = PIPETX7COMPLIANCE_out; + assign PIPETX7DATAVALID_delay = PIPETX7DATAVALID_out; + assign PIPETX7DATA_delay = PIPETX7DATA_out; + assign PIPETX7DEEMPH_delay = PIPETX7DEEMPH_out; + assign PIPETX7ELECIDLE_delay = PIPETX7ELECIDLE_out; + assign PIPETX7EQCONTROL_delay = PIPETX7EQCONTROL_out; + assign PIPETX7EQDEEMPH_delay = PIPETX7EQDEEMPH_out; + assign PIPETX7EQPRESET_delay = PIPETX7EQPRESET_out; + assign PIPETX7MARGIN_delay = PIPETX7MARGIN_out; + assign PIPETX7POWERDOWN_delay = PIPETX7POWERDOWN_out; + assign PIPETX7RATE_delay = PIPETX7RATE_out; + assign PIPETX7RCVRDET_delay = PIPETX7RCVRDET_out; + assign PIPETX7RESET_delay = PIPETX7RESET_out; + assign PIPETX7STARTBLOCK_delay = PIPETX7STARTBLOCK_out; + assign PIPETX7SWING_delay = PIPETX7SWING_out; + assign PIPETX7SYNCHEADER_delay = PIPETX7SYNCHEADER_out; + assign PLEQINPROGRESS_delay = PLEQINPROGRESS_out; + assign PLEQPHASE_delay = PLEQPHASE_out; + assign SAXISCCTREADY_delay = SAXISCCTREADY_out; + assign SAXISRQTREADY_delay = SAXISRQTREADY_out; + assign SPAREOUT_delay = SPAREOUT_out; + + assign CFGCONFIGSPACEENABLE_in = (CFGCONFIGSPACEENABLE === 1'bz) || CFGCONFIGSPACEENABLE_delay; // rv 1 + assign CFGDEVID_in[0] = (CFGDEVID[0] !== 1'bz) && CFGDEVID_delay[0]; // rv 0 + assign CFGDEVID_in[10] = (CFGDEVID[10] !== 1'bz) && CFGDEVID_delay[10]; // rv 0 + assign CFGDEVID_in[11] = (CFGDEVID[11] !== 1'bz) && CFGDEVID_delay[11]; // rv 0 + assign CFGDEVID_in[12] = (CFGDEVID[12] !== 1'bz) && CFGDEVID_delay[12]; // rv 0 + assign CFGDEVID_in[13] = (CFGDEVID[13] !== 1'bz) && CFGDEVID_delay[13]; // rv 0 + assign CFGDEVID_in[14] = (CFGDEVID[14] !== 1'bz) && CFGDEVID_delay[14]; // rv 0 + assign CFGDEVID_in[15] = (CFGDEVID[15] !== 1'bz) && CFGDEVID_delay[15]; // rv 0 + assign CFGDEVID_in[1] = (CFGDEVID[1] !== 1'bz) && CFGDEVID_delay[1]; // rv 0 + assign CFGDEVID_in[2] = (CFGDEVID[2] !== 1'bz) && CFGDEVID_delay[2]; // rv 0 + assign CFGDEVID_in[3] = (CFGDEVID[3] !== 1'bz) && CFGDEVID_delay[3]; // rv 0 + assign CFGDEVID_in[4] = (CFGDEVID[4] !== 1'bz) && CFGDEVID_delay[4]; // rv 0 + assign CFGDEVID_in[5] = (CFGDEVID[5] !== 1'bz) && CFGDEVID_delay[5]; // rv 0 + assign CFGDEVID_in[6] = (CFGDEVID[6] !== 1'bz) && CFGDEVID_delay[6]; // rv 0 + assign CFGDEVID_in[7] = (CFGDEVID[7] !== 1'bz) && CFGDEVID_delay[7]; // rv 0 + assign CFGDEVID_in[8] = (CFGDEVID[8] !== 1'bz) && CFGDEVID_delay[8]; // rv 0 + assign CFGDEVID_in[9] = (CFGDEVID[9] !== 1'bz) && CFGDEVID_delay[9]; // rv 0 + assign CFGDSBUSNUMBER_in[0] = (CFGDSBUSNUMBER[0] !== 1'bz) && CFGDSBUSNUMBER_delay[0]; // rv 0 + assign CFGDSBUSNUMBER_in[1] = (CFGDSBUSNUMBER[1] !== 1'bz) && CFGDSBUSNUMBER_delay[1]; // rv 0 + assign CFGDSBUSNUMBER_in[2] = (CFGDSBUSNUMBER[2] !== 1'bz) && CFGDSBUSNUMBER_delay[2]; // rv 0 + assign CFGDSBUSNUMBER_in[3] = (CFGDSBUSNUMBER[3] !== 1'bz) && CFGDSBUSNUMBER_delay[3]; // rv 0 + assign CFGDSBUSNUMBER_in[4] = (CFGDSBUSNUMBER[4] !== 1'bz) && CFGDSBUSNUMBER_delay[4]; // rv 0 + assign CFGDSBUSNUMBER_in[5] = (CFGDSBUSNUMBER[5] !== 1'bz) && CFGDSBUSNUMBER_delay[5]; // rv 0 + assign CFGDSBUSNUMBER_in[6] = (CFGDSBUSNUMBER[6] !== 1'bz) && CFGDSBUSNUMBER_delay[6]; // rv 0 + assign CFGDSBUSNUMBER_in[7] = (CFGDSBUSNUMBER[7] !== 1'bz) && CFGDSBUSNUMBER_delay[7]; // rv 0 + assign CFGDSDEVICENUMBER_in[0] = (CFGDSDEVICENUMBER[0] !== 1'bz) && CFGDSDEVICENUMBER_delay[0]; // rv 0 + assign CFGDSDEVICENUMBER_in[1] = (CFGDSDEVICENUMBER[1] !== 1'bz) && CFGDSDEVICENUMBER_delay[1]; // rv 0 + assign CFGDSDEVICENUMBER_in[2] = (CFGDSDEVICENUMBER[2] !== 1'bz) && CFGDSDEVICENUMBER_delay[2]; // rv 0 + assign CFGDSDEVICENUMBER_in[3] = (CFGDSDEVICENUMBER[3] !== 1'bz) && CFGDSDEVICENUMBER_delay[3]; // rv 0 + assign CFGDSDEVICENUMBER_in[4] = (CFGDSDEVICENUMBER[4] !== 1'bz) && CFGDSDEVICENUMBER_delay[4]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[0] = (CFGDSFUNCTIONNUMBER[0] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[1] = (CFGDSFUNCTIONNUMBER[1] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGDSFUNCTIONNUMBER_in[2] = (CFGDSFUNCTIONNUMBER[2] !== 1'bz) && CFGDSFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGDSN_in[0] = (CFGDSN[0] !== 1'bz) && CFGDSN_delay[0]; // rv 0 + assign CFGDSN_in[10] = (CFGDSN[10] !== 1'bz) && CFGDSN_delay[10]; // rv 0 + assign CFGDSN_in[11] = (CFGDSN[11] !== 1'bz) && CFGDSN_delay[11]; // rv 0 + assign CFGDSN_in[12] = (CFGDSN[12] !== 1'bz) && CFGDSN_delay[12]; // rv 0 + assign CFGDSN_in[13] = (CFGDSN[13] !== 1'bz) && CFGDSN_delay[13]; // rv 0 + assign CFGDSN_in[14] = (CFGDSN[14] !== 1'bz) && CFGDSN_delay[14]; // rv 0 + assign CFGDSN_in[15] = (CFGDSN[15] !== 1'bz) && CFGDSN_delay[15]; // rv 0 + assign CFGDSN_in[16] = (CFGDSN[16] !== 1'bz) && CFGDSN_delay[16]; // rv 0 + assign CFGDSN_in[17] = (CFGDSN[17] !== 1'bz) && CFGDSN_delay[17]; // rv 0 + assign CFGDSN_in[18] = (CFGDSN[18] !== 1'bz) && CFGDSN_delay[18]; // rv 0 + assign CFGDSN_in[19] = (CFGDSN[19] !== 1'bz) && CFGDSN_delay[19]; // rv 0 + assign CFGDSN_in[1] = (CFGDSN[1] !== 1'bz) && CFGDSN_delay[1]; // rv 0 + assign CFGDSN_in[20] = (CFGDSN[20] !== 1'bz) && CFGDSN_delay[20]; // rv 0 + assign CFGDSN_in[21] = (CFGDSN[21] !== 1'bz) && CFGDSN_delay[21]; // rv 0 + assign CFGDSN_in[22] = (CFGDSN[22] !== 1'bz) && CFGDSN_delay[22]; // rv 0 + assign CFGDSN_in[23] = (CFGDSN[23] !== 1'bz) && CFGDSN_delay[23]; // rv 0 + assign CFGDSN_in[24] = (CFGDSN[24] !== 1'bz) && CFGDSN_delay[24]; // rv 0 + assign CFGDSN_in[25] = (CFGDSN[25] !== 1'bz) && CFGDSN_delay[25]; // rv 0 + assign CFGDSN_in[26] = (CFGDSN[26] !== 1'bz) && CFGDSN_delay[26]; // rv 0 + assign CFGDSN_in[27] = (CFGDSN[27] !== 1'bz) && CFGDSN_delay[27]; // rv 0 + assign CFGDSN_in[28] = (CFGDSN[28] !== 1'bz) && CFGDSN_delay[28]; // rv 0 + assign CFGDSN_in[29] = (CFGDSN[29] !== 1'bz) && CFGDSN_delay[29]; // rv 0 + assign CFGDSN_in[2] = (CFGDSN[2] !== 1'bz) && CFGDSN_delay[2]; // rv 0 + assign CFGDSN_in[30] = (CFGDSN[30] !== 1'bz) && CFGDSN_delay[30]; // rv 0 + assign CFGDSN_in[31] = (CFGDSN[31] !== 1'bz) && CFGDSN_delay[31]; // rv 0 + assign CFGDSN_in[32] = (CFGDSN[32] !== 1'bz) && CFGDSN_delay[32]; // rv 0 + assign CFGDSN_in[33] = (CFGDSN[33] !== 1'bz) && CFGDSN_delay[33]; // rv 0 + assign CFGDSN_in[34] = (CFGDSN[34] !== 1'bz) && CFGDSN_delay[34]; // rv 0 + assign CFGDSN_in[35] = (CFGDSN[35] !== 1'bz) && CFGDSN_delay[35]; // rv 0 + assign CFGDSN_in[36] = (CFGDSN[36] !== 1'bz) && CFGDSN_delay[36]; // rv 0 + assign CFGDSN_in[37] = (CFGDSN[37] !== 1'bz) && CFGDSN_delay[37]; // rv 0 + assign CFGDSN_in[38] = (CFGDSN[38] !== 1'bz) && CFGDSN_delay[38]; // rv 0 + assign CFGDSN_in[39] = (CFGDSN[39] !== 1'bz) && CFGDSN_delay[39]; // rv 0 + assign CFGDSN_in[3] = (CFGDSN[3] !== 1'bz) && CFGDSN_delay[3]; // rv 0 + assign CFGDSN_in[40] = (CFGDSN[40] !== 1'bz) && CFGDSN_delay[40]; // rv 0 + assign CFGDSN_in[41] = (CFGDSN[41] !== 1'bz) && CFGDSN_delay[41]; // rv 0 + assign CFGDSN_in[42] = (CFGDSN[42] !== 1'bz) && CFGDSN_delay[42]; // rv 0 + assign CFGDSN_in[43] = (CFGDSN[43] !== 1'bz) && CFGDSN_delay[43]; // rv 0 + assign CFGDSN_in[44] = (CFGDSN[44] !== 1'bz) && CFGDSN_delay[44]; // rv 0 + assign CFGDSN_in[45] = (CFGDSN[45] !== 1'bz) && CFGDSN_delay[45]; // rv 0 + assign CFGDSN_in[46] = (CFGDSN[46] !== 1'bz) && CFGDSN_delay[46]; // rv 0 + assign CFGDSN_in[47] = (CFGDSN[47] !== 1'bz) && CFGDSN_delay[47]; // rv 0 + assign CFGDSN_in[48] = (CFGDSN[48] !== 1'bz) && CFGDSN_delay[48]; // rv 0 + assign CFGDSN_in[49] = (CFGDSN[49] !== 1'bz) && CFGDSN_delay[49]; // rv 0 + assign CFGDSN_in[4] = (CFGDSN[4] !== 1'bz) && CFGDSN_delay[4]; // rv 0 + assign CFGDSN_in[50] = (CFGDSN[50] !== 1'bz) && CFGDSN_delay[50]; // rv 0 + assign CFGDSN_in[51] = (CFGDSN[51] !== 1'bz) && CFGDSN_delay[51]; // rv 0 + assign CFGDSN_in[52] = (CFGDSN[52] !== 1'bz) && CFGDSN_delay[52]; // rv 0 + assign CFGDSN_in[53] = (CFGDSN[53] !== 1'bz) && CFGDSN_delay[53]; // rv 0 + assign CFGDSN_in[54] = (CFGDSN[54] !== 1'bz) && CFGDSN_delay[54]; // rv 0 + assign CFGDSN_in[55] = (CFGDSN[55] !== 1'bz) && CFGDSN_delay[55]; // rv 0 + assign CFGDSN_in[56] = (CFGDSN[56] !== 1'bz) && CFGDSN_delay[56]; // rv 0 + assign CFGDSN_in[57] = (CFGDSN[57] !== 1'bz) && CFGDSN_delay[57]; // rv 0 + assign CFGDSN_in[58] = (CFGDSN[58] !== 1'bz) && CFGDSN_delay[58]; // rv 0 + assign CFGDSN_in[59] = (CFGDSN[59] !== 1'bz) && CFGDSN_delay[59]; // rv 0 + assign CFGDSN_in[5] = (CFGDSN[5] !== 1'bz) && CFGDSN_delay[5]; // rv 0 + assign CFGDSN_in[60] = (CFGDSN[60] !== 1'bz) && CFGDSN_delay[60]; // rv 0 + assign CFGDSN_in[61] = (CFGDSN[61] !== 1'bz) && CFGDSN_delay[61]; // rv 0 + assign CFGDSN_in[62] = (CFGDSN[62] !== 1'bz) && CFGDSN_delay[62]; // rv 0 + assign CFGDSN_in[63] = (CFGDSN[63] !== 1'bz) && CFGDSN_delay[63]; // rv 0 + assign CFGDSN_in[6] = (CFGDSN[6] !== 1'bz) && CFGDSN_delay[6]; // rv 0 + assign CFGDSN_in[7] = (CFGDSN[7] !== 1'bz) && CFGDSN_delay[7]; // rv 0 + assign CFGDSN_in[8] = (CFGDSN[8] !== 1'bz) && CFGDSN_delay[8]; // rv 0 + assign CFGDSN_in[9] = (CFGDSN[9] !== 1'bz) && CFGDSN_delay[9]; // rv 0 + assign CFGDSPORTNUMBER_in[0] = (CFGDSPORTNUMBER[0] !== 1'bz) && CFGDSPORTNUMBER_delay[0]; // rv 0 + assign CFGDSPORTNUMBER_in[1] = (CFGDSPORTNUMBER[1] !== 1'bz) && CFGDSPORTNUMBER_delay[1]; // rv 0 + assign CFGDSPORTNUMBER_in[2] = (CFGDSPORTNUMBER[2] !== 1'bz) && CFGDSPORTNUMBER_delay[2]; // rv 0 + assign CFGDSPORTNUMBER_in[3] = (CFGDSPORTNUMBER[3] !== 1'bz) && CFGDSPORTNUMBER_delay[3]; // rv 0 + assign CFGDSPORTNUMBER_in[4] = (CFGDSPORTNUMBER[4] !== 1'bz) && CFGDSPORTNUMBER_delay[4]; // rv 0 + assign CFGDSPORTNUMBER_in[5] = (CFGDSPORTNUMBER[5] !== 1'bz) && CFGDSPORTNUMBER_delay[5]; // rv 0 + assign CFGDSPORTNUMBER_in[6] = (CFGDSPORTNUMBER[6] !== 1'bz) && CFGDSPORTNUMBER_delay[6]; // rv 0 + assign CFGDSPORTNUMBER_in[7] = (CFGDSPORTNUMBER[7] !== 1'bz) && CFGDSPORTNUMBER_delay[7]; // rv 0 + assign CFGERRCORIN_in = (CFGERRCORIN !== 1'bz) && CFGERRCORIN_delay; // rv 0 + assign CFGERRUNCORIN_in = (CFGERRUNCORIN !== 1'bz) && CFGERRUNCORIN_delay; // rv 0 + assign CFGEXTREADDATAVALID_in = (CFGEXTREADDATAVALID !== 1'bz) && CFGEXTREADDATAVALID_delay; // rv 0 + assign CFGEXTREADDATA_in[0] = (CFGEXTREADDATA[0] !== 1'bz) && CFGEXTREADDATA_delay[0]; // rv 0 + assign CFGEXTREADDATA_in[10] = (CFGEXTREADDATA[10] !== 1'bz) && CFGEXTREADDATA_delay[10]; // rv 0 + assign CFGEXTREADDATA_in[11] = (CFGEXTREADDATA[11] !== 1'bz) && CFGEXTREADDATA_delay[11]; // rv 0 + assign CFGEXTREADDATA_in[12] = (CFGEXTREADDATA[12] !== 1'bz) && CFGEXTREADDATA_delay[12]; // rv 0 + assign CFGEXTREADDATA_in[13] = (CFGEXTREADDATA[13] !== 1'bz) && CFGEXTREADDATA_delay[13]; // rv 0 + assign CFGEXTREADDATA_in[14] = (CFGEXTREADDATA[14] !== 1'bz) && CFGEXTREADDATA_delay[14]; // rv 0 + assign CFGEXTREADDATA_in[15] = (CFGEXTREADDATA[15] !== 1'bz) && CFGEXTREADDATA_delay[15]; // rv 0 + assign CFGEXTREADDATA_in[16] = (CFGEXTREADDATA[16] !== 1'bz) && CFGEXTREADDATA_delay[16]; // rv 0 + assign CFGEXTREADDATA_in[17] = (CFGEXTREADDATA[17] !== 1'bz) && CFGEXTREADDATA_delay[17]; // rv 0 + assign CFGEXTREADDATA_in[18] = (CFGEXTREADDATA[18] !== 1'bz) && CFGEXTREADDATA_delay[18]; // rv 0 + assign CFGEXTREADDATA_in[19] = (CFGEXTREADDATA[19] !== 1'bz) && CFGEXTREADDATA_delay[19]; // rv 0 + assign CFGEXTREADDATA_in[1] = (CFGEXTREADDATA[1] !== 1'bz) && CFGEXTREADDATA_delay[1]; // rv 0 + assign CFGEXTREADDATA_in[20] = (CFGEXTREADDATA[20] !== 1'bz) && CFGEXTREADDATA_delay[20]; // rv 0 + assign CFGEXTREADDATA_in[21] = (CFGEXTREADDATA[21] !== 1'bz) && CFGEXTREADDATA_delay[21]; // rv 0 + assign CFGEXTREADDATA_in[22] = (CFGEXTREADDATA[22] !== 1'bz) && CFGEXTREADDATA_delay[22]; // rv 0 + assign CFGEXTREADDATA_in[23] = (CFGEXTREADDATA[23] !== 1'bz) && CFGEXTREADDATA_delay[23]; // rv 0 + assign CFGEXTREADDATA_in[24] = (CFGEXTREADDATA[24] !== 1'bz) && CFGEXTREADDATA_delay[24]; // rv 0 + assign CFGEXTREADDATA_in[25] = (CFGEXTREADDATA[25] !== 1'bz) && CFGEXTREADDATA_delay[25]; // rv 0 + assign CFGEXTREADDATA_in[26] = (CFGEXTREADDATA[26] !== 1'bz) && CFGEXTREADDATA_delay[26]; // rv 0 + assign CFGEXTREADDATA_in[27] = (CFGEXTREADDATA[27] !== 1'bz) && CFGEXTREADDATA_delay[27]; // rv 0 + assign CFGEXTREADDATA_in[28] = (CFGEXTREADDATA[28] !== 1'bz) && CFGEXTREADDATA_delay[28]; // rv 0 + assign CFGEXTREADDATA_in[29] = (CFGEXTREADDATA[29] !== 1'bz) && CFGEXTREADDATA_delay[29]; // rv 0 + assign CFGEXTREADDATA_in[2] = (CFGEXTREADDATA[2] !== 1'bz) && CFGEXTREADDATA_delay[2]; // rv 0 + assign CFGEXTREADDATA_in[30] = (CFGEXTREADDATA[30] !== 1'bz) && CFGEXTREADDATA_delay[30]; // rv 0 + assign CFGEXTREADDATA_in[31] = (CFGEXTREADDATA[31] !== 1'bz) && CFGEXTREADDATA_delay[31]; // rv 0 + assign CFGEXTREADDATA_in[3] = (CFGEXTREADDATA[3] !== 1'bz) && CFGEXTREADDATA_delay[3]; // rv 0 + assign CFGEXTREADDATA_in[4] = (CFGEXTREADDATA[4] !== 1'bz) && CFGEXTREADDATA_delay[4]; // rv 0 + assign CFGEXTREADDATA_in[5] = (CFGEXTREADDATA[5] !== 1'bz) && CFGEXTREADDATA_delay[5]; // rv 0 + assign CFGEXTREADDATA_in[6] = (CFGEXTREADDATA[6] !== 1'bz) && CFGEXTREADDATA_delay[6]; // rv 0 + assign CFGEXTREADDATA_in[7] = (CFGEXTREADDATA[7] !== 1'bz) && CFGEXTREADDATA_delay[7]; // rv 0 + assign CFGEXTREADDATA_in[8] = (CFGEXTREADDATA[8] !== 1'bz) && CFGEXTREADDATA_delay[8]; // rv 0 + assign CFGEXTREADDATA_in[9] = (CFGEXTREADDATA[9] !== 1'bz) && CFGEXTREADDATA_delay[9]; // rv 0 + assign CFGFCSEL_in[0] = (CFGFCSEL[0] !== 1'bz) && CFGFCSEL_delay[0]; // rv 0 + assign CFGFCSEL_in[1] = (CFGFCSEL[1] !== 1'bz) && CFGFCSEL_delay[1]; // rv 0 + assign CFGFCSEL_in[2] = (CFGFCSEL[2] !== 1'bz) && CFGFCSEL_delay[2]; // rv 0 + assign CFGFLRDONE_in[0] = (CFGFLRDONE[0] !== 1'bz) && CFGFLRDONE_delay[0]; // rv 0 + assign CFGFLRDONE_in[1] = (CFGFLRDONE[1] !== 1'bz) && CFGFLRDONE_delay[1]; // rv 0 + assign CFGFLRDONE_in[2] = (CFGFLRDONE[2] !== 1'bz) && CFGFLRDONE_delay[2]; // rv 0 + assign CFGFLRDONE_in[3] = (CFGFLRDONE[3] !== 1'bz) && CFGFLRDONE_delay[3]; // rv 0 + assign CFGHOTRESETIN_in = (CFGHOTRESETIN !== 1'bz) && CFGHOTRESETIN_delay; // rv 0 + assign CFGINTERRUPTINT_in[0] = (CFGINTERRUPTINT[0] !== 1'bz) && CFGINTERRUPTINT_delay[0]; // rv 0 + assign CFGINTERRUPTINT_in[1] = (CFGINTERRUPTINT[1] !== 1'bz) && CFGINTERRUPTINT_delay[1]; // rv 0 + assign CFGINTERRUPTINT_in[2] = (CFGINTERRUPTINT[2] !== 1'bz) && CFGINTERRUPTINT_delay[2]; // rv 0 + assign CFGINTERRUPTINT_in[3] = (CFGINTERRUPTINT[3] !== 1'bz) && CFGINTERRUPTINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[0] = (CFGINTERRUPTMSIATTR[0] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[0]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[1] = (CFGINTERRUPTMSIATTR[1] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[1]; // rv 0 + assign CFGINTERRUPTMSIATTR_in[2] = (CFGINTERRUPTMSIATTR[2] !== 1'bz) && CFGINTERRUPTMSIATTR_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[0] = (CFGINTERRUPTMSIFUNCTIONNUMBER[0] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[1] = (CFGINTERRUPTMSIFUNCTIONNUMBER[1] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[2] = (CFGINTERRUPTMSIFUNCTIONNUMBER[2] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGINTERRUPTMSIFUNCTIONNUMBER_in[3] = (CFGINTERRUPTMSIFUNCTIONNUMBER[3] !== 1'bz) && CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[0] = (CFGINTERRUPTMSIINT[0] !== 1'bz) && CFGINTERRUPTMSIINT_delay[0]; // rv 0 + assign CFGINTERRUPTMSIINT_in[10] = (CFGINTERRUPTMSIINT[10] !== 1'bz) && CFGINTERRUPTMSIINT_delay[10]; // rv 0 + assign CFGINTERRUPTMSIINT_in[11] = (CFGINTERRUPTMSIINT[11] !== 1'bz) && CFGINTERRUPTMSIINT_delay[11]; // rv 0 + assign CFGINTERRUPTMSIINT_in[12] = (CFGINTERRUPTMSIINT[12] !== 1'bz) && CFGINTERRUPTMSIINT_delay[12]; // rv 0 + assign CFGINTERRUPTMSIINT_in[13] = (CFGINTERRUPTMSIINT[13] !== 1'bz) && CFGINTERRUPTMSIINT_delay[13]; // rv 0 + assign CFGINTERRUPTMSIINT_in[14] = (CFGINTERRUPTMSIINT[14] !== 1'bz) && CFGINTERRUPTMSIINT_delay[14]; // rv 0 + assign CFGINTERRUPTMSIINT_in[15] = (CFGINTERRUPTMSIINT[15] !== 1'bz) && CFGINTERRUPTMSIINT_delay[15]; // rv 0 + assign CFGINTERRUPTMSIINT_in[16] = (CFGINTERRUPTMSIINT[16] !== 1'bz) && CFGINTERRUPTMSIINT_delay[16]; // rv 0 + assign CFGINTERRUPTMSIINT_in[17] = (CFGINTERRUPTMSIINT[17] !== 1'bz) && CFGINTERRUPTMSIINT_delay[17]; // rv 0 + assign CFGINTERRUPTMSIINT_in[18] = (CFGINTERRUPTMSIINT[18] !== 1'bz) && CFGINTERRUPTMSIINT_delay[18]; // rv 0 + assign CFGINTERRUPTMSIINT_in[19] = (CFGINTERRUPTMSIINT[19] !== 1'bz) && CFGINTERRUPTMSIINT_delay[19]; // rv 0 + assign CFGINTERRUPTMSIINT_in[1] = (CFGINTERRUPTMSIINT[1] !== 1'bz) && CFGINTERRUPTMSIINT_delay[1]; // rv 0 + assign CFGINTERRUPTMSIINT_in[20] = (CFGINTERRUPTMSIINT[20] !== 1'bz) && CFGINTERRUPTMSIINT_delay[20]; // rv 0 + assign CFGINTERRUPTMSIINT_in[21] = (CFGINTERRUPTMSIINT[21] !== 1'bz) && CFGINTERRUPTMSIINT_delay[21]; // rv 0 + assign CFGINTERRUPTMSIINT_in[22] = (CFGINTERRUPTMSIINT[22] !== 1'bz) && CFGINTERRUPTMSIINT_delay[22]; // rv 0 + assign CFGINTERRUPTMSIINT_in[23] = (CFGINTERRUPTMSIINT[23] !== 1'bz) && CFGINTERRUPTMSIINT_delay[23]; // rv 0 + assign CFGINTERRUPTMSIINT_in[24] = (CFGINTERRUPTMSIINT[24] !== 1'bz) && CFGINTERRUPTMSIINT_delay[24]; // rv 0 + assign CFGINTERRUPTMSIINT_in[25] = (CFGINTERRUPTMSIINT[25] !== 1'bz) && CFGINTERRUPTMSIINT_delay[25]; // rv 0 + assign CFGINTERRUPTMSIINT_in[26] = (CFGINTERRUPTMSIINT[26] !== 1'bz) && CFGINTERRUPTMSIINT_delay[26]; // rv 0 + assign CFGINTERRUPTMSIINT_in[27] = (CFGINTERRUPTMSIINT[27] !== 1'bz) && CFGINTERRUPTMSIINT_delay[27]; // rv 0 + assign CFGINTERRUPTMSIINT_in[28] = (CFGINTERRUPTMSIINT[28] !== 1'bz) && CFGINTERRUPTMSIINT_delay[28]; // rv 0 + assign CFGINTERRUPTMSIINT_in[29] = (CFGINTERRUPTMSIINT[29] !== 1'bz) && CFGINTERRUPTMSIINT_delay[29]; // rv 0 + assign CFGINTERRUPTMSIINT_in[2] = (CFGINTERRUPTMSIINT[2] !== 1'bz) && CFGINTERRUPTMSIINT_delay[2]; // rv 0 + assign CFGINTERRUPTMSIINT_in[30] = (CFGINTERRUPTMSIINT[30] !== 1'bz) && CFGINTERRUPTMSIINT_delay[30]; // rv 0 + assign CFGINTERRUPTMSIINT_in[31] = (CFGINTERRUPTMSIINT[31] !== 1'bz) && CFGINTERRUPTMSIINT_delay[31]; // rv 0 + assign CFGINTERRUPTMSIINT_in[3] = (CFGINTERRUPTMSIINT[3] !== 1'bz) && CFGINTERRUPTMSIINT_delay[3]; // rv 0 + assign CFGINTERRUPTMSIINT_in[4] = (CFGINTERRUPTMSIINT[4] !== 1'bz) && CFGINTERRUPTMSIINT_delay[4]; // rv 0 + assign CFGINTERRUPTMSIINT_in[5] = (CFGINTERRUPTMSIINT[5] !== 1'bz) && CFGINTERRUPTMSIINT_delay[5]; // rv 0 + assign CFGINTERRUPTMSIINT_in[6] = (CFGINTERRUPTMSIINT[6] !== 1'bz) && CFGINTERRUPTMSIINT_delay[6]; // rv 0 + assign CFGINTERRUPTMSIINT_in[7] = (CFGINTERRUPTMSIINT[7] !== 1'bz) && CFGINTERRUPTMSIINT_delay[7]; // rv 0 + assign CFGINTERRUPTMSIINT_in[8] = (CFGINTERRUPTMSIINT[8] !== 1'bz) && CFGINTERRUPTMSIINT_delay[8]; // rv 0 + assign CFGINTERRUPTMSIINT_in[9] = (CFGINTERRUPTMSIINT[9] !== 1'bz) && CFGINTERRUPTMSIINT_delay[9]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[0] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[1] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[2] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in[3] = (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[0] = (CFGINTERRUPTMSIPENDINGSTATUS[0] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[10] = (CFGINTERRUPTMSIPENDINGSTATUS[10] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[11] = (CFGINTERRUPTMSIPENDINGSTATUS[11] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[12] = (CFGINTERRUPTMSIPENDINGSTATUS[12] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[13] = (CFGINTERRUPTMSIPENDINGSTATUS[13] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[14] = (CFGINTERRUPTMSIPENDINGSTATUS[14] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[15] = (CFGINTERRUPTMSIPENDINGSTATUS[15] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[16] = (CFGINTERRUPTMSIPENDINGSTATUS[16] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[17] = (CFGINTERRUPTMSIPENDINGSTATUS[17] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[18] = (CFGINTERRUPTMSIPENDINGSTATUS[18] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[19] = (CFGINTERRUPTMSIPENDINGSTATUS[19] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[1] = (CFGINTERRUPTMSIPENDINGSTATUS[1] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[20] = (CFGINTERRUPTMSIPENDINGSTATUS[20] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[21] = (CFGINTERRUPTMSIPENDINGSTATUS[21] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[22] = (CFGINTERRUPTMSIPENDINGSTATUS[22] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[23] = (CFGINTERRUPTMSIPENDINGSTATUS[23] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[24] = (CFGINTERRUPTMSIPENDINGSTATUS[24] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[25] = (CFGINTERRUPTMSIPENDINGSTATUS[25] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[26] = (CFGINTERRUPTMSIPENDINGSTATUS[26] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[27] = (CFGINTERRUPTMSIPENDINGSTATUS[27] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[28] = (CFGINTERRUPTMSIPENDINGSTATUS[28] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[29] = (CFGINTERRUPTMSIPENDINGSTATUS[29] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[2] = (CFGINTERRUPTMSIPENDINGSTATUS[2] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[30] = (CFGINTERRUPTMSIPENDINGSTATUS[30] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[31] = (CFGINTERRUPTMSIPENDINGSTATUS[31] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[3] = (CFGINTERRUPTMSIPENDINGSTATUS[3] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[4] = (CFGINTERRUPTMSIPENDINGSTATUS[4] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[5] = (CFGINTERRUPTMSIPENDINGSTATUS[5] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[6] = (CFGINTERRUPTMSIPENDINGSTATUS[6] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[7] = (CFGINTERRUPTMSIPENDINGSTATUS[7] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[8] = (CFGINTERRUPTMSIPENDINGSTATUS[8] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIPENDINGSTATUS_in[9] = (CFGINTERRUPTMSIPENDINGSTATUS[9] !== 1'bz) && CFGINTERRUPTMSIPENDINGSTATUS_delay[9]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[0] = (CFGINTERRUPTMSISELECT[0] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[0]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[1] = (CFGINTERRUPTMSISELECT[1] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[1]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[2] = (CFGINTERRUPTMSISELECT[2] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[2]; // rv 0 + assign CFGINTERRUPTMSISELECT_in[3] = (CFGINTERRUPTMSISELECT[3] !== 1'bz) && CFGINTERRUPTMSISELECT_delay[3]; // rv 0 + assign CFGINTERRUPTMSITPHPRESENT_in = (CFGINTERRUPTMSITPHPRESENT !== 1'bz) && CFGINTERRUPTMSITPHPRESENT_delay; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[0] = (CFGINTERRUPTMSITPHSTTAG[0] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[1] = (CFGINTERRUPTMSITPHSTTAG[1] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[1]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[2] = (CFGINTERRUPTMSITPHSTTAG[2] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[2]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[3] = (CFGINTERRUPTMSITPHSTTAG[3] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[3]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[4] = (CFGINTERRUPTMSITPHSTTAG[4] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[4]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[5] = (CFGINTERRUPTMSITPHSTTAG[5] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[5]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[6] = (CFGINTERRUPTMSITPHSTTAG[6] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[6]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[7] = (CFGINTERRUPTMSITPHSTTAG[7] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[7]; // rv 0 + assign CFGINTERRUPTMSITPHSTTAG_in[8] = (CFGINTERRUPTMSITPHSTTAG[8] !== 1'bz) && CFGINTERRUPTMSITPHSTTAG_delay[8]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[0] = (CFGINTERRUPTMSITPHTYPE[0] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[0]; // rv 0 + assign CFGINTERRUPTMSITPHTYPE_in[1] = (CFGINTERRUPTMSITPHTYPE[1] !== 1'bz) && CFGINTERRUPTMSITPHTYPE_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[0] = (CFGINTERRUPTMSIXADDRESS[0] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[10] = (CFGINTERRUPTMSIXADDRESS[10] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[11] = (CFGINTERRUPTMSIXADDRESS[11] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[12] = (CFGINTERRUPTMSIXADDRESS[12] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[13] = (CFGINTERRUPTMSIXADDRESS[13] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[14] = (CFGINTERRUPTMSIXADDRESS[14] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[15] = (CFGINTERRUPTMSIXADDRESS[15] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[16] = (CFGINTERRUPTMSIXADDRESS[16] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[17] = (CFGINTERRUPTMSIXADDRESS[17] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[18] = (CFGINTERRUPTMSIXADDRESS[18] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[19] = (CFGINTERRUPTMSIXADDRESS[19] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[1] = (CFGINTERRUPTMSIXADDRESS[1] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[20] = (CFGINTERRUPTMSIXADDRESS[20] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[21] = (CFGINTERRUPTMSIXADDRESS[21] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[22] = (CFGINTERRUPTMSIXADDRESS[22] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[23] = (CFGINTERRUPTMSIXADDRESS[23] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[24] = (CFGINTERRUPTMSIXADDRESS[24] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[25] = (CFGINTERRUPTMSIXADDRESS[25] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[26] = (CFGINTERRUPTMSIXADDRESS[26] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[27] = (CFGINTERRUPTMSIXADDRESS[27] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[28] = (CFGINTERRUPTMSIXADDRESS[28] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[29] = (CFGINTERRUPTMSIXADDRESS[29] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[2] = (CFGINTERRUPTMSIXADDRESS[2] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[30] = (CFGINTERRUPTMSIXADDRESS[30] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[31] = (CFGINTERRUPTMSIXADDRESS[31] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[32] = (CFGINTERRUPTMSIXADDRESS[32] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[32]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[33] = (CFGINTERRUPTMSIXADDRESS[33] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[33]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[34] = (CFGINTERRUPTMSIXADDRESS[34] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[34]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[35] = (CFGINTERRUPTMSIXADDRESS[35] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[35]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[36] = (CFGINTERRUPTMSIXADDRESS[36] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[36]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[37] = (CFGINTERRUPTMSIXADDRESS[37] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[37]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[38] = (CFGINTERRUPTMSIXADDRESS[38] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[38]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[39] = (CFGINTERRUPTMSIXADDRESS[39] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[39]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[3] = (CFGINTERRUPTMSIXADDRESS[3] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[40] = (CFGINTERRUPTMSIXADDRESS[40] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[40]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[41] = (CFGINTERRUPTMSIXADDRESS[41] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[41]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[42] = (CFGINTERRUPTMSIXADDRESS[42] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[42]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[43] = (CFGINTERRUPTMSIXADDRESS[43] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[43]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[44] = (CFGINTERRUPTMSIXADDRESS[44] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[44]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[45] = (CFGINTERRUPTMSIXADDRESS[45] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[45]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[46] = (CFGINTERRUPTMSIXADDRESS[46] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[46]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[47] = (CFGINTERRUPTMSIXADDRESS[47] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[47]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[48] = (CFGINTERRUPTMSIXADDRESS[48] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[48]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[49] = (CFGINTERRUPTMSIXADDRESS[49] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[49]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[4] = (CFGINTERRUPTMSIXADDRESS[4] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[50] = (CFGINTERRUPTMSIXADDRESS[50] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[50]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[51] = (CFGINTERRUPTMSIXADDRESS[51] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[51]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[52] = (CFGINTERRUPTMSIXADDRESS[52] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[52]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[53] = (CFGINTERRUPTMSIXADDRESS[53] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[53]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[54] = (CFGINTERRUPTMSIXADDRESS[54] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[54]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[55] = (CFGINTERRUPTMSIXADDRESS[55] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[55]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[56] = (CFGINTERRUPTMSIXADDRESS[56] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[56]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[57] = (CFGINTERRUPTMSIXADDRESS[57] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[57]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[58] = (CFGINTERRUPTMSIXADDRESS[58] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[58]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[59] = (CFGINTERRUPTMSIXADDRESS[59] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[59]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[5] = (CFGINTERRUPTMSIXADDRESS[5] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[60] = (CFGINTERRUPTMSIXADDRESS[60] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[60]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[61] = (CFGINTERRUPTMSIXADDRESS[61] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[61]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[62] = (CFGINTERRUPTMSIXADDRESS[62] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[62]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[63] = (CFGINTERRUPTMSIXADDRESS[63] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[63]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[6] = (CFGINTERRUPTMSIXADDRESS[6] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[7] = (CFGINTERRUPTMSIXADDRESS[7] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[8] = (CFGINTERRUPTMSIXADDRESS[8] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXADDRESS_in[9] = (CFGINTERRUPTMSIXADDRESS[9] !== 1'bz) && CFGINTERRUPTMSIXADDRESS_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[0] = (CFGINTERRUPTMSIXDATA[0] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[0]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[10] = (CFGINTERRUPTMSIXDATA[10] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[10]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[11] = (CFGINTERRUPTMSIXDATA[11] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[11]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[12] = (CFGINTERRUPTMSIXDATA[12] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[12]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[13] = (CFGINTERRUPTMSIXDATA[13] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[13]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[14] = (CFGINTERRUPTMSIXDATA[14] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[14]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[15] = (CFGINTERRUPTMSIXDATA[15] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[15]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[16] = (CFGINTERRUPTMSIXDATA[16] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[16]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[17] = (CFGINTERRUPTMSIXDATA[17] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[17]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[18] = (CFGINTERRUPTMSIXDATA[18] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[18]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[19] = (CFGINTERRUPTMSIXDATA[19] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[19]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[1] = (CFGINTERRUPTMSIXDATA[1] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[1]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[20] = (CFGINTERRUPTMSIXDATA[20] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[20]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[21] = (CFGINTERRUPTMSIXDATA[21] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[21]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[22] = (CFGINTERRUPTMSIXDATA[22] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[22]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[23] = (CFGINTERRUPTMSIXDATA[23] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[23]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[24] = (CFGINTERRUPTMSIXDATA[24] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[24]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[25] = (CFGINTERRUPTMSIXDATA[25] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[25]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[26] = (CFGINTERRUPTMSIXDATA[26] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[26]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[27] = (CFGINTERRUPTMSIXDATA[27] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[27]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[28] = (CFGINTERRUPTMSIXDATA[28] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[28]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[29] = (CFGINTERRUPTMSIXDATA[29] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[29]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[2] = (CFGINTERRUPTMSIXDATA[2] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[2]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[30] = (CFGINTERRUPTMSIXDATA[30] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[30]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[31] = (CFGINTERRUPTMSIXDATA[31] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[31]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[3] = (CFGINTERRUPTMSIXDATA[3] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[3]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[4] = (CFGINTERRUPTMSIXDATA[4] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[4]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[5] = (CFGINTERRUPTMSIXDATA[5] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[5]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[6] = (CFGINTERRUPTMSIXDATA[6] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[6]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[7] = (CFGINTERRUPTMSIXDATA[7] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[7]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[8] = (CFGINTERRUPTMSIXDATA[8] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[8]; // rv 0 + assign CFGINTERRUPTMSIXDATA_in[9] = (CFGINTERRUPTMSIXDATA[9] !== 1'bz) && CFGINTERRUPTMSIXDATA_delay[9]; // rv 0 + assign CFGINTERRUPTMSIXINT_in = (CFGINTERRUPTMSIXINT !== 1'bz) && CFGINTERRUPTMSIXINT_delay; // rv 0 + assign CFGINTERRUPTPENDING_in[0] = (CFGINTERRUPTPENDING[0] !== 1'bz) && CFGINTERRUPTPENDING_delay[0]; // rv 0 + assign CFGINTERRUPTPENDING_in[1] = (CFGINTERRUPTPENDING[1] !== 1'bz) && CFGINTERRUPTPENDING_delay[1]; // rv 0 + assign CFGINTERRUPTPENDING_in[2] = (CFGINTERRUPTPENDING[2] !== 1'bz) && CFGINTERRUPTPENDING_delay[2]; // rv 0 + assign CFGINTERRUPTPENDING_in[3] = (CFGINTERRUPTPENDING[3] !== 1'bz) && CFGINTERRUPTPENDING_delay[3]; // rv 0 + assign CFGLINKTRAININGENABLE_in = (CFGLINKTRAININGENABLE === 1'bz) || CFGLINKTRAININGENABLE_delay; // rv 1 + assign CFGMGMTADDR_in[0] = (CFGMGMTADDR[0] !== 1'bz) && CFGMGMTADDR_delay[0]; // rv 0 + assign CFGMGMTADDR_in[10] = (CFGMGMTADDR[10] !== 1'bz) && CFGMGMTADDR_delay[10]; // rv 0 + assign CFGMGMTADDR_in[11] = (CFGMGMTADDR[11] !== 1'bz) && CFGMGMTADDR_delay[11]; // rv 0 + assign CFGMGMTADDR_in[12] = (CFGMGMTADDR[12] !== 1'bz) && CFGMGMTADDR_delay[12]; // rv 0 + assign CFGMGMTADDR_in[13] = (CFGMGMTADDR[13] !== 1'bz) && CFGMGMTADDR_delay[13]; // rv 0 + assign CFGMGMTADDR_in[14] = (CFGMGMTADDR[14] !== 1'bz) && CFGMGMTADDR_delay[14]; // rv 0 + assign CFGMGMTADDR_in[15] = (CFGMGMTADDR[15] !== 1'bz) && CFGMGMTADDR_delay[15]; // rv 0 + assign CFGMGMTADDR_in[16] = (CFGMGMTADDR[16] !== 1'bz) && CFGMGMTADDR_delay[16]; // rv 0 + assign CFGMGMTADDR_in[17] = (CFGMGMTADDR[17] !== 1'bz) && CFGMGMTADDR_delay[17]; // rv 0 + assign CFGMGMTADDR_in[18] = (CFGMGMTADDR[18] !== 1'bz) && CFGMGMTADDR_delay[18]; // rv 0 + assign CFGMGMTADDR_in[1] = (CFGMGMTADDR[1] !== 1'bz) && CFGMGMTADDR_delay[1]; // rv 0 + assign CFGMGMTADDR_in[2] = (CFGMGMTADDR[2] !== 1'bz) && CFGMGMTADDR_delay[2]; // rv 0 + assign CFGMGMTADDR_in[3] = (CFGMGMTADDR[3] !== 1'bz) && CFGMGMTADDR_delay[3]; // rv 0 + assign CFGMGMTADDR_in[4] = (CFGMGMTADDR[4] !== 1'bz) && CFGMGMTADDR_delay[4]; // rv 0 + assign CFGMGMTADDR_in[5] = (CFGMGMTADDR[5] !== 1'bz) && CFGMGMTADDR_delay[5]; // rv 0 + assign CFGMGMTADDR_in[6] = (CFGMGMTADDR[6] !== 1'bz) && CFGMGMTADDR_delay[6]; // rv 0 + assign CFGMGMTADDR_in[7] = (CFGMGMTADDR[7] !== 1'bz) && CFGMGMTADDR_delay[7]; // rv 0 + assign CFGMGMTADDR_in[8] = (CFGMGMTADDR[8] !== 1'bz) && CFGMGMTADDR_delay[8]; // rv 0 + assign CFGMGMTADDR_in[9] = (CFGMGMTADDR[9] !== 1'bz) && CFGMGMTADDR_delay[9]; // rv 0 + assign CFGMGMTBYTEENABLE_in[0] = (CFGMGMTBYTEENABLE[0] !== 1'bz) && CFGMGMTBYTEENABLE_delay[0]; // rv 0 + assign CFGMGMTBYTEENABLE_in[1] = (CFGMGMTBYTEENABLE[1] !== 1'bz) && CFGMGMTBYTEENABLE_delay[1]; // rv 0 + assign CFGMGMTBYTEENABLE_in[2] = (CFGMGMTBYTEENABLE[2] !== 1'bz) && CFGMGMTBYTEENABLE_delay[2]; // rv 0 + assign CFGMGMTBYTEENABLE_in[3] = (CFGMGMTBYTEENABLE[3] !== 1'bz) && CFGMGMTBYTEENABLE_delay[3]; // rv 0 + assign CFGMGMTREAD_in = (CFGMGMTREAD !== 1'bz) && CFGMGMTREAD_delay; // rv 0 + assign CFGMGMTTYPE1CFGREGACCESS_in = (CFGMGMTTYPE1CFGREGACCESS !== 1'bz) && CFGMGMTTYPE1CFGREGACCESS_delay; // rv 0 + assign CFGMGMTWRITEDATA_in[0] = (CFGMGMTWRITEDATA[0] !== 1'bz) && CFGMGMTWRITEDATA_delay[0]; // rv 0 + assign CFGMGMTWRITEDATA_in[10] = (CFGMGMTWRITEDATA[10] !== 1'bz) && CFGMGMTWRITEDATA_delay[10]; // rv 0 + assign CFGMGMTWRITEDATA_in[11] = (CFGMGMTWRITEDATA[11] !== 1'bz) && CFGMGMTWRITEDATA_delay[11]; // rv 0 + assign CFGMGMTWRITEDATA_in[12] = (CFGMGMTWRITEDATA[12] !== 1'bz) && CFGMGMTWRITEDATA_delay[12]; // rv 0 + assign CFGMGMTWRITEDATA_in[13] = (CFGMGMTWRITEDATA[13] !== 1'bz) && CFGMGMTWRITEDATA_delay[13]; // rv 0 + assign CFGMGMTWRITEDATA_in[14] = (CFGMGMTWRITEDATA[14] !== 1'bz) && CFGMGMTWRITEDATA_delay[14]; // rv 0 + assign CFGMGMTWRITEDATA_in[15] = (CFGMGMTWRITEDATA[15] !== 1'bz) && CFGMGMTWRITEDATA_delay[15]; // rv 0 + assign CFGMGMTWRITEDATA_in[16] = (CFGMGMTWRITEDATA[16] !== 1'bz) && CFGMGMTWRITEDATA_delay[16]; // rv 0 + assign CFGMGMTWRITEDATA_in[17] = (CFGMGMTWRITEDATA[17] !== 1'bz) && CFGMGMTWRITEDATA_delay[17]; // rv 0 + assign CFGMGMTWRITEDATA_in[18] = (CFGMGMTWRITEDATA[18] !== 1'bz) && CFGMGMTWRITEDATA_delay[18]; // rv 0 + assign CFGMGMTWRITEDATA_in[19] = (CFGMGMTWRITEDATA[19] !== 1'bz) && CFGMGMTWRITEDATA_delay[19]; // rv 0 + assign CFGMGMTWRITEDATA_in[1] = (CFGMGMTWRITEDATA[1] !== 1'bz) && CFGMGMTWRITEDATA_delay[1]; // rv 0 + assign CFGMGMTWRITEDATA_in[20] = (CFGMGMTWRITEDATA[20] !== 1'bz) && CFGMGMTWRITEDATA_delay[20]; // rv 0 + assign CFGMGMTWRITEDATA_in[21] = (CFGMGMTWRITEDATA[21] !== 1'bz) && CFGMGMTWRITEDATA_delay[21]; // rv 0 + assign CFGMGMTWRITEDATA_in[22] = (CFGMGMTWRITEDATA[22] !== 1'bz) && CFGMGMTWRITEDATA_delay[22]; // rv 0 + assign CFGMGMTWRITEDATA_in[23] = (CFGMGMTWRITEDATA[23] !== 1'bz) && CFGMGMTWRITEDATA_delay[23]; // rv 0 + assign CFGMGMTWRITEDATA_in[24] = (CFGMGMTWRITEDATA[24] !== 1'bz) && CFGMGMTWRITEDATA_delay[24]; // rv 0 + assign CFGMGMTWRITEDATA_in[25] = (CFGMGMTWRITEDATA[25] !== 1'bz) && CFGMGMTWRITEDATA_delay[25]; // rv 0 + assign CFGMGMTWRITEDATA_in[26] = (CFGMGMTWRITEDATA[26] !== 1'bz) && CFGMGMTWRITEDATA_delay[26]; // rv 0 + assign CFGMGMTWRITEDATA_in[27] = (CFGMGMTWRITEDATA[27] !== 1'bz) && CFGMGMTWRITEDATA_delay[27]; // rv 0 + assign CFGMGMTWRITEDATA_in[28] = (CFGMGMTWRITEDATA[28] !== 1'bz) && CFGMGMTWRITEDATA_delay[28]; // rv 0 + assign CFGMGMTWRITEDATA_in[29] = (CFGMGMTWRITEDATA[29] !== 1'bz) && CFGMGMTWRITEDATA_delay[29]; // rv 0 + assign CFGMGMTWRITEDATA_in[2] = (CFGMGMTWRITEDATA[2] !== 1'bz) && CFGMGMTWRITEDATA_delay[2]; // rv 0 + assign CFGMGMTWRITEDATA_in[30] = (CFGMGMTWRITEDATA[30] !== 1'bz) && CFGMGMTWRITEDATA_delay[30]; // rv 0 + assign CFGMGMTWRITEDATA_in[31] = (CFGMGMTWRITEDATA[31] !== 1'bz) && CFGMGMTWRITEDATA_delay[31]; // rv 0 + assign CFGMGMTWRITEDATA_in[3] = (CFGMGMTWRITEDATA[3] !== 1'bz) && CFGMGMTWRITEDATA_delay[3]; // rv 0 + assign CFGMGMTWRITEDATA_in[4] = (CFGMGMTWRITEDATA[4] !== 1'bz) && CFGMGMTWRITEDATA_delay[4]; // rv 0 + assign CFGMGMTWRITEDATA_in[5] = (CFGMGMTWRITEDATA[5] !== 1'bz) && CFGMGMTWRITEDATA_delay[5]; // rv 0 + assign CFGMGMTWRITEDATA_in[6] = (CFGMGMTWRITEDATA[6] !== 1'bz) && CFGMGMTWRITEDATA_delay[6]; // rv 0 + assign CFGMGMTWRITEDATA_in[7] = (CFGMGMTWRITEDATA[7] !== 1'bz) && CFGMGMTWRITEDATA_delay[7]; // rv 0 + assign CFGMGMTWRITEDATA_in[8] = (CFGMGMTWRITEDATA[8] !== 1'bz) && CFGMGMTWRITEDATA_delay[8]; // rv 0 + assign CFGMGMTWRITEDATA_in[9] = (CFGMGMTWRITEDATA[9] !== 1'bz) && CFGMGMTWRITEDATA_delay[9]; // rv 0 + assign CFGMGMTWRITE_in = (CFGMGMTWRITE !== 1'bz) && CFGMGMTWRITE_delay; // rv 0 + assign CFGMSGTRANSMITDATA_in[0] = (CFGMSGTRANSMITDATA[0] !== 1'bz) && CFGMSGTRANSMITDATA_delay[0]; // rv 0 + assign CFGMSGTRANSMITDATA_in[10] = (CFGMSGTRANSMITDATA[10] !== 1'bz) && CFGMSGTRANSMITDATA_delay[10]; // rv 0 + assign CFGMSGTRANSMITDATA_in[11] = (CFGMSGTRANSMITDATA[11] !== 1'bz) && CFGMSGTRANSMITDATA_delay[11]; // rv 0 + assign CFGMSGTRANSMITDATA_in[12] = (CFGMSGTRANSMITDATA[12] !== 1'bz) && CFGMSGTRANSMITDATA_delay[12]; // rv 0 + assign CFGMSGTRANSMITDATA_in[13] = (CFGMSGTRANSMITDATA[13] !== 1'bz) && CFGMSGTRANSMITDATA_delay[13]; // rv 0 + assign CFGMSGTRANSMITDATA_in[14] = (CFGMSGTRANSMITDATA[14] !== 1'bz) && CFGMSGTRANSMITDATA_delay[14]; // rv 0 + assign CFGMSGTRANSMITDATA_in[15] = (CFGMSGTRANSMITDATA[15] !== 1'bz) && CFGMSGTRANSMITDATA_delay[15]; // rv 0 + assign CFGMSGTRANSMITDATA_in[16] = (CFGMSGTRANSMITDATA[16] !== 1'bz) && CFGMSGTRANSMITDATA_delay[16]; // rv 0 + assign CFGMSGTRANSMITDATA_in[17] = (CFGMSGTRANSMITDATA[17] !== 1'bz) && CFGMSGTRANSMITDATA_delay[17]; // rv 0 + assign CFGMSGTRANSMITDATA_in[18] = (CFGMSGTRANSMITDATA[18] !== 1'bz) && CFGMSGTRANSMITDATA_delay[18]; // rv 0 + assign CFGMSGTRANSMITDATA_in[19] = (CFGMSGTRANSMITDATA[19] !== 1'bz) && CFGMSGTRANSMITDATA_delay[19]; // rv 0 + assign CFGMSGTRANSMITDATA_in[1] = (CFGMSGTRANSMITDATA[1] !== 1'bz) && CFGMSGTRANSMITDATA_delay[1]; // rv 0 + assign CFGMSGTRANSMITDATA_in[20] = (CFGMSGTRANSMITDATA[20] !== 1'bz) && CFGMSGTRANSMITDATA_delay[20]; // rv 0 + assign CFGMSGTRANSMITDATA_in[21] = (CFGMSGTRANSMITDATA[21] !== 1'bz) && CFGMSGTRANSMITDATA_delay[21]; // rv 0 + assign CFGMSGTRANSMITDATA_in[22] = (CFGMSGTRANSMITDATA[22] !== 1'bz) && CFGMSGTRANSMITDATA_delay[22]; // rv 0 + assign CFGMSGTRANSMITDATA_in[23] = (CFGMSGTRANSMITDATA[23] !== 1'bz) && CFGMSGTRANSMITDATA_delay[23]; // rv 0 + assign CFGMSGTRANSMITDATA_in[24] = (CFGMSGTRANSMITDATA[24] !== 1'bz) && CFGMSGTRANSMITDATA_delay[24]; // rv 0 + assign CFGMSGTRANSMITDATA_in[25] = (CFGMSGTRANSMITDATA[25] !== 1'bz) && CFGMSGTRANSMITDATA_delay[25]; // rv 0 + assign CFGMSGTRANSMITDATA_in[26] = (CFGMSGTRANSMITDATA[26] !== 1'bz) && CFGMSGTRANSMITDATA_delay[26]; // rv 0 + assign CFGMSGTRANSMITDATA_in[27] = (CFGMSGTRANSMITDATA[27] !== 1'bz) && CFGMSGTRANSMITDATA_delay[27]; // rv 0 + assign CFGMSGTRANSMITDATA_in[28] = (CFGMSGTRANSMITDATA[28] !== 1'bz) && CFGMSGTRANSMITDATA_delay[28]; // rv 0 + assign CFGMSGTRANSMITDATA_in[29] = (CFGMSGTRANSMITDATA[29] !== 1'bz) && CFGMSGTRANSMITDATA_delay[29]; // rv 0 + assign CFGMSGTRANSMITDATA_in[2] = (CFGMSGTRANSMITDATA[2] !== 1'bz) && CFGMSGTRANSMITDATA_delay[2]; // rv 0 + assign CFGMSGTRANSMITDATA_in[30] = (CFGMSGTRANSMITDATA[30] !== 1'bz) && CFGMSGTRANSMITDATA_delay[30]; // rv 0 + assign CFGMSGTRANSMITDATA_in[31] = (CFGMSGTRANSMITDATA[31] !== 1'bz) && CFGMSGTRANSMITDATA_delay[31]; // rv 0 + assign CFGMSGTRANSMITDATA_in[3] = (CFGMSGTRANSMITDATA[3] !== 1'bz) && CFGMSGTRANSMITDATA_delay[3]; // rv 0 + assign CFGMSGTRANSMITDATA_in[4] = (CFGMSGTRANSMITDATA[4] !== 1'bz) && CFGMSGTRANSMITDATA_delay[4]; // rv 0 + assign CFGMSGTRANSMITDATA_in[5] = (CFGMSGTRANSMITDATA[5] !== 1'bz) && CFGMSGTRANSMITDATA_delay[5]; // rv 0 + assign CFGMSGTRANSMITDATA_in[6] = (CFGMSGTRANSMITDATA[6] !== 1'bz) && CFGMSGTRANSMITDATA_delay[6]; // rv 0 + assign CFGMSGTRANSMITDATA_in[7] = (CFGMSGTRANSMITDATA[7] !== 1'bz) && CFGMSGTRANSMITDATA_delay[7]; // rv 0 + assign CFGMSGTRANSMITDATA_in[8] = (CFGMSGTRANSMITDATA[8] !== 1'bz) && CFGMSGTRANSMITDATA_delay[8]; // rv 0 + assign CFGMSGTRANSMITDATA_in[9] = (CFGMSGTRANSMITDATA[9] !== 1'bz) && CFGMSGTRANSMITDATA_delay[9]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[0] = (CFGMSGTRANSMITTYPE[0] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[0]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[1] = (CFGMSGTRANSMITTYPE[1] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[1]; // rv 0 + assign CFGMSGTRANSMITTYPE_in[2] = (CFGMSGTRANSMITTYPE[2] !== 1'bz) && CFGMSGTRANSMITTYPE_delay[2]; // rv 0 + assign CFGMSGTRANSMIT_in = (CFGMSGTRANSMIT !== 1'bz) && CFGMSGTRANSMIT_delay; // rv 0 + assign CFGPERFUNCSTATUSCONTROL_in[0] = (CFGPERFUNCSTATUSCONTROL[0] !== 1'bz) && CFGPERFUNCSTATUSCONTROL_delay[0]; // rv 0 + assign CFGPERFUNCSTATUSCONTROL_in[1] = (CFGPERFUNCSTATUSCONTROL[1] !== 1'bz) && CFGPERFUNCSTATUSCONTROL_delay[1]; // rv 0 + assign CFGPERFUNCSTATUSCONTROL_in[2] = (CFGPERFUNCSTATUSCONTROL[2] !== 1'bz) && CFGPERFUNCSTATUSCONTROL_delay[2]; // rv 0 + assign CFGPERFUNCTIONNUMBER_in[0] = (CFGPERFUNCTIONNUMBER[0] !== 1'bz) && CFGPERFUNCTIONNUMBER_delay[0]; // rv 0 + assign CFGPERFUNCTIONNUMBER_in[1] = (CFGPERFUNCTIONNUMBER[1] !== 1'bz) && CFGPERFUNCTIONNUMBER_delay[1]; // rv 0 + assign CFGPERFUNCTIONNUMBER_in[2] = (CFGPERFUNCTIONNUMBER[2] !== 1'bz) && CFGPERFUNCTIONNUMBER_delay[2]; // rv 0 + assign CFGPERFUNCTIONNUMBER_in[3] = (CFGPERFUNCTIONNUMBER[3] !== 1'bz) && CFGPERFUNCTIONNUMBER_delay[3]; // rv 0 + assign CFGPERFUNCTIONOUTPUTREQUEST_in = (CFGPERFUNCTIONOUTPUTREQUEST !== 1'bz) && CFGPERFUNCTIONOUTPUTREQUEST_delay; // rv 0 + assign CFGPOWERSTATECHANGEACK_in = (CFGPOWERSTATECHANGEACK === 1'bz) || CFGPOWERSTATECHANGEACK_delay; // rv 1 + assign CFGREQPMTRANSITIONL23READY_in = (CFGREQPMTRANSITIONL23READY !== 1'bz) && CFGREQPMTRANSITIONL23READY_delay; // rv 0 + assign CFGREVID_in[0] = (CFGREVID[0] !== 1'bz) && CFGREVID_delay[0]; // rv 0 + assign CFGREVID_in[1] = (CFGREVID[1] !== 1'bz) && CFGREVID_delay[1]; // rv 0 + assign CFGREVID_in[2] = (CFGREVID[2] !== 1'bz) && CFGREVID_delay[2]; // rv 0 + assign CFGREVID_in[3] = (CFGREVID[3] !== 1'bz) && CFGREVID_delay[3]; // rv 0 + assign CFGREVID_in[4] = (CFGREVID[4] !== 1'bz) && CFGREVID_delay[4]; // rv 0 + assign CFGREVID_in[5] = (CFGREVID[5] !== 1'bz) && CFGREVID_delay[5]; // rv 0 + assign CFGREVID_in[6] = (CFGREVID[6] !== 1'bz) && CFGREVID_delay[6]; // rv 0 + assign CFGREVID_in[7] = (CFGREVID[7] !== 1'bz) && CFGREVID_delay[7]; // rv 0 + assign CFGSUBSYSID_in[0] = (CFGSUBSYSID[0] !== 1'bz) && CFGSUBSYSID_delay[0]; // rv 0 + assign CFGSUBSYSID_in[10] = (CFGSUBSYSID[10] !== 1'bz) && CFGSUBSYSID_delay[10]; // rv 0 + assign CFGSUBSYSID_in[11] = (CFGSUBSYSID[11] !== 1'bz) && CFGSUBSYSID_delay[11]; // rv 0 + assign CFGSUBSYSID_in[12] = (CFGSUBSYSID[12] !== 1'bz) && CFGSUBSYSID_delay[12]; // rv 0 + assign CFGSUBSYSID_in[13] = (CFGSUBSYSID[13] !== 1'bz) && CFGSUBSYSID_delay[13]; // rv 0 + assign CFGSUBSYSID_in[14] = (CFGSUBSYSID[14] !== 1'bz) && CFGSUBSYSID_delay[14]; // rv 0 + assign CFGSUBSYSID_in[15] = (CFGSUBSYSID[15] !== 1'bz) && CFGSUBSYSID_delay[15]; // rv 0 + assign CFGSUBSYSID_in[1] = (CFGSUBSYSID[1] !== 1'bz) && CFGSUBSYSID_delay[1]; // rv 0 + assign CFGSUBSYSID_in[2] = (CFGSUBSYSID[2] !== 1'bz) && CFGSUBSYSID_delay[2]; // rv 0 + assign CFGSUBSYSID_in[3] = (CFGSUBSYSID[3] !== 1'bz) && CFGSUBSYSID_delay[3]; // rv 0 + assign CFGSUBSYSID_in[4] = (CFGSUBSYSID[4] !== 1'bz) && CFGSUBSYSID_delay[4]; // rv 0 + assign CFGSUBSYSID_in[5] = (CFGSUBSYSID[5] !== 1'bz) && CFGSUBSYSID_delay[5]; // rv 0 + assign CFGSUBSYSID_in[6] = (CFGSUBSYSID[6] !== 1'bz) && CFGSUBSYSID_delay[6]; // rv 0 + assign CFGSUBSYSID_in[7] = (CFGSUBSYSID[7] !== 1'bz) && CFGSUBSYSID_delay[7]; // rv 0 + assign CFGSUBSYSID_in[8] = (CFGSUBSYSID[8] !== 1'bz) && CFGSUBSYSID_delay[8]; // rv 0 + assign CFGSUBSYSID_in[9] = (CFGSUBSYSID[9] !== 1'bz) && CFGSUBSYSID_delay[9]; // rv 0 + assign CFGSUBSYSVENDID_in[0] = (CFGSUBSYSVENDID[0] !== 1'bz) && CFGSUBSYSVENDID_delay[0]; // rv 0 + assign CFGSUBSYSVENDID_in[10] = (CFGSUBSYSVENDID[10] !== 1'bz) && CFGSUBSYSVENDID_delay[10]; // rv 0 + assign CFGSUBSYSVENDID_in[11] = (CFGSUBSYSVENDID[11] !== 1'bz) && CFGSUBSYSVENDID_delay[11]; // rv 0 + assign CFGSUBSYSVENDID_in[12] = (CFGSUBSYSVENDID[12] !== 1'bz) && CFGSUBSYSVENDID_delay[12]; // rv 0 + assign CFGSUBSYSVENDID_in[13] = (CFGSUBSYSVENDID[13] !== 1'bz) && CFGSUBSYSVENDID_delay[13]; // rv 0 + assign CFGSUBSYSVENDID_in[14] = (CFGSUBSYSVENDID[14] !== 1'bz) && CFGSUBSYSVENDID_delay[14]; // rv 0 + assign CFGSUBSYSVENDID_in[15] = (CFGSUBSYSVENDID[15] !== 1'bz) && CFGSUBSYSVENDID_delay[15]; // rv 0 + assign CFGSUBSYSVENDID_in[1] = (CFGSUBSYSVENDID[1] !== 1'bz) && CFGSUBSYSVENDID_delay[1]; // rv 0 + assign CFGSUBSYSVENDID_in[2] = (CFGSUBSYSVENDID[2] !== 1'bz) && CFGSUBSYSVENDID_delay[2]; // rv 0 + assign CFGSUBSYSVENDID_in[3] = (CFGSUBSYSVENDID[3] !== 1'bz) && CFGSUBSYSVENDID_delay[3]; // rv 0 + assign CFGSUBSYSVENDID_in[4] = (CFGSUBSYSVENDID[4] !== 1'bz) && CFGSUBSYSVENDID_delay[4]; // rv 0 + assign CFGSUBSYSVENDID_in[5] = (CFGSUBSYSVENDID[5] !== 1'bz) && CFGSUBSYSVENDID_delay[5]; // rv 0 + assign CFGSUBSYSVENDID_in[6] = (CFGSUBSYSVENDID[6] !== 1'bz) && CFGSUBSYSVENDID_delay[6]; // rv 0 + assign CFGSUBSYSVENDID_in[7] = (CFGSUBSYSVENDID[7] !== 1'bz) && CFGSUBSYSVENDID_delay[7]; // rv 0 + assign CFGSUBSYSVENDID_in[8] = (CFGSUBSYSVENDID[8] !== 1'bz) && CFGSUBSYSVENDID_delay[8]; // rv 0 + assign CFGSUBSYSVENDID_in[9] = (CFGSUBSYSVENDID[9] !== 1'bz) && CFGSUBSYSVENDID_delay[9]; // rv 0 + assign CFGTPHSTTREADDATAVALID_in = (CFGTPHSTTREADDATAVALID !== 1'bz) && CFGTPHSTTREADDATAVALID_delay; // rv 0 + assign CFGTPHSTTREADDATA_in[0] = (CFGTPHSTTREADDATA[0] !== 1'bz) && CFGTPHSTTREADDATA_delay[0]; // rv 0 + assign CFGTPHSTTREADDATA_in[10] = (CFGTPHSTTREADDATA[10] !== 1'bz) && CFGTPHSTTREADDATA_delay[10]; // rv 0 + assign CFGTPHSTTREADDATA_in[11] = (CFGTPHSTTREADDATA[11] !== 1'bz) && CFGTPHSTTREADDATA_delay[11]; // rv 0 + assign CFGTPHSTTREADDATA_in[12] = (CFGTPHSTTREADDATA[12] !== 1'bz) && CFGTPHSTTREADDATA_delay[12]; // rv 0 + assign CFGTPHSTTREADDATA_in[13] = (CFGTPHSTTREADDATA[13] !== 1'bz) && CFGTPHSTTREADDATA_delay[13]; // rv 0 + assign CFGTPHSTTREADDATA_in[14] = (CFGTPHSTTREADDATA[14] !== 1'bz) && CFGTPHSTTREADDATA_delay[14]; // rv 0 + assign CFGTPHSTTREADDATA_in[15] = (CFGTPHSTTREADDATA[15] !== 1'bz) && CFGTPHSTTREADDATA_delay[15]; // rv 0 + assign CFGTPHSTTREADDATA_in[16] = (CFGTPHSTTREADDATA[16] !== 1'bz) && CFGTPHSTTREADDATA_delay[16]; // rv 0 + assign CFGTPHSTTREADDATA_in[17] = (CFGTPHSTTREADDATA[17] !== 1'bz) && CFGTPHSTTREADDATA_delay[17]; // rv 0 + assign CFGTPHSTTREADDATA_in[18] = (CFGTPHSTTREADDATA[18] !== 1'bz) && CFGTPHSTTREADDATA_delay[18]; // rv 0 + assign CFGTPHSTTREADDATA_in[19] = (CFGTPHSTTREADDATA[19] !== 1'bz) && CFGTPHSTTREADDATA_delay[19]; // rv 0 + assign CFGTPHSTTREADDATA_in[1] = (CFGTPHSTTREADDATA[1] !== 1'bz) && CFGTPHSTTREADDATA_delay[1]; // rv 0 + assign CFGTPHSTTREADDATA_in[20] = (CFGTPHSTTREADDATA[20] !== 1'bz) && CFGTPHSTTREADDATA_delay[20]; // rv 0 + assign CFGTPHSTTREADDATA_in[21] = (CFGTPHSTTREADDATA[21] !== 1'bz) && CFGTPHSTTREADDATA_delay[21]; // rv 0 + assign CFGTPHSTTREADDATA_in[22] = (CFGTPHSTTREADDATA[22] !== 1'bz) && CFGTPHSTTREADDATA_delay[22]; // rv 0 + assign CFGTPHSTTREADDATA_in[23] = (CFGTPHSTTREADDATA[23] !== 1'bz) && CFGTPHSTTREADDATA_delay[23]; // rv 0 + assign CFGTPHSTTREADDATA_in[24] = (CFGTPHSTTREADDATA[24] !== 1'bz) && CFGTPHSTTREADDATA_delay[24]; // rv 0 + assign CFGTPHSTTREADDATA_in[25] = (CFGTPHSTTREADDATA[25] !== 1'bz) && CFGTPHSTTREADDATA_delay[25]; // rv 0 + assign CFGTPHSTTREADDATA_in[26] = (CFGTPHSTTREADDATA[26] !== 1'bz) && CFGTPHSTTREADDATA_delay[26]; // rv 0 + assign CFGTPHSTTREADDATA_in[27] = (CFGTPHSTTREADDATA[27] !== 1'bz) && CFGTPHSTTREADDATA_delay[27]; // rv 0 + assign CFGTPHSTTREADDATA_in[28] = (CFGTPHSTTREADDATA[28] !== 1'bz) && CFGTPHSTTREADDATA_delay[28]; // rv 0 + assign CFGTPHSTTREADDATA_in[29] = (CFGTPHSTTREADDATA[29] !== 1'bz) && CFGTPHSTTREADDATA_delay[29]; // rv 0 + assign CFGTPHSTTREADDATA_in[2] = (CFGTPHSTTREADDATA[2] !== 1'bz) && CFGTPHSTTREADDATA_delay[2]; // rv 0 + assign CFGTPHSTTREADDATA_in[30] = (CFGTPHSTTREADDATA[30] !== 1'bz) && CFGTPHSTTREADDATA_delay[30]; // rv 0 + assign CFGTPHSTTREADDATA_in[31] = (CFGTPHSTTREADDATA[31] !== 1'bz) && CFGTPHSTTREADDATA_delay[31]; // rv 0 + assign CFGTPHSTTREADDATA_in[3] = (CFGTPHSTTREADDATA[3] !== 1'bz) && CFGTPHSTTREADDATA_delay[3]; // rv 0 + assign CFGTPHSTTREADDATA_in[4] = (CFGTPHSTTREADDATA[4] !== 1'bz) && CFGTPHSTTREADDATA_delay[4]; // rv 0 + assign CFGTPHSTTREADDATA_in[5] = (CFGTPHSTTREADDATA[5] !== 1'bz) && CFGTPHSTTREADDATA_delay[5]; // rv 0 + assign CFGTPHSTTREADDATA_in[6] = (CFGTPHSTTREADDATA[6] !== 1'bz) && CFGTPHSTTREADDATA_delay[6]; // rv 0 + assign CFGTPHSTTREADDATA_in[7] = (CFGTPHSTTREADDATA[7] !== 1'bz) && CFGTPHSTTREADDATA_delay[7]; // rv 0 + assign CFGTPHSTTREADDATA_in[8] = (CFGTPHSTTREADDATA[8] !== 1'bz) && CFGTPHSTTREADDATA_delay[8]; // rv 0 + assign CFGTPHSTTREADDATA_in[9] = (CFGTPHSTTREADDATA[9] !== 1'bz) && CFGTPHSTTREADDATA_delay[9]; // rv 0 + assign CFGVENDID_in[0] = (CFGVENDID[0] !== 1'bz) && CFGVENDID_delay[0]; // rv 0 + assign CFGVENDID_in[10] = (CFGVENDID[10] !== 1'bz) && CFGVENDID_delay[10]; // rv 0 + assign CFGVENDID_in[11] = (CFGVENDID[11] !== 1'bz) && CFGVENDID_delay[11]; // rv 0 + assign CFGVENDID_in[12] = (CFGVENDID[12] !== 1'bz) && CFGVENDID_delay[12]; // rv 0 + assign CFGVENDID_in[13] = (CFGVENDID[13] !== 1'bz) && CFGVENDID_delay[13]; // rv 0 + assign CFGVENDID_in[14] = (CFGVENDID[14] !== 1'bz) && CFGVENDID_delay[14]; // rv 0 + assign CFGVENDID_in[15] = (CFGVENDID[15] !== 1'bz) && CFGVENDID_delay[15]; // rv 0 + assign CFGVENDID_in[1] = (CFGVENDID[1] !== 1'bz) && CFGVENDID_delay[1]; // rv 0 + assign CFGVENDID_in[2] = (CFGVENDID[2] !== 1'bz) && CFGVENDID_delay[2]; // rv 0 + assign CFGVENDID_in[3] = (CFGVENDID[3] !== 1'bz) && CFGVENDID_delay[3]; // rv 0 + assign CFGVENDID_in[4] = (CFGVENDID[4] !== 1'bz) && CFGVENDID_delay[4]; // rv 0 + assign CFGVENDID_in[5] = (CFGVENDID[5] !== 1'bz) && CFGVENDID_delay[5]; // rv 0 + assign CFGVENDID_in[6] = (CFGVENDID[6] !== 1'bz) && CFGVENDID_delay[6]; // rv 0 + assign CFGVENDID_in[7] = (CFGVENDID[7] !== 1'bz) && CFGVENDID_delay[7]; // rv 0 + assign CFGVENDID_in[8] = (CFGVENDID[8] !== 1'bz) && CFGVENDID_delay[8]; // rv 0 + assign CFGVENDID_in[9] = (CFGVENDID[9] !== 1'bz) && CFGVENDID_delay[9]; // rv 0 + assign CFGVFFLRDONE_in[0] = (CFGVFFLRDONE[0] !== 1'bz) && CFGVFFLRDONE_delay[0]; // rv 0 + assign CFGVFFLRDONE_in[1] = (CFGVFFLRDONE[1] !== 1'bz) && CFGVFFLRDONE_delay[1]; // rv 0 + assign CFGVFFLRDONE_in[2] = (CFGVFFLRDONE[2] !== 1'bz) && CFGVFFLRDONE_delay[2]; // rv 0 + assign CFGVFFLRDONE_in[3] = (CFGVFFLRDONE[3] !== 1'bz) && CFGVFFLRDONE_delay[3]; // rv 0 + assign CFGVFFLRDONE_in[4] = (CFGVFFLRDONE[4] !== 1'bz) && CFGVFFLRDONE_delay[4]; // rv 0 + assign CFGVFFLRDONE_in[5] = (CFGVFFLRDONE[5] !== 1'bz) && CFGVFFLRDONE_delay[5]; // rv 0 + assign CFGVFFLRDONE_in[6] = (CFGVFFLRDONE[6] !== 1'bz) && CFGVFFLRDONE_delay[6]; // rv 0 + assign CFGVFFLRDONE_in[7] = (CFGVFFLRDONE[7] !== 1'bz) && CFGVFFLRDONE_delay[7]; // rv 0 + assign CONFMCAPREQUESTBYCONF_in = (CONFMCAPREQUESTBYCONF !== 1'bz) && CONFMCAPREQUESTBYCONF_delay; // rv 0 + assign CONFREQDATA_in[0] = (CONFREQDATA[0] !== 1'bz) && CONFREQDATA_delay[0]; // rv 0 + assign CONFREQDATA_in[10] = (CONFREQDATA[10] !== 1'bz) && CONFREQDATA_delay[10]; // rv 0 + assign CONFREQDATA_in[11] = (CONFREQDATA[11] !== 1'bz) && CONFREQDATA_delay[11]; // rv 0 + assign CONFREQDATA_in[12] = (CONFREQDATA[12] !== 1'bz) && CONFREQDATA_delay[12]; // rv 0 + assign CONFREQDATA_in[13] = (CONFREQDATA[13] !== 1'bz) && CONFREQDATA_delay[13]; // rv 0 + assign CONFREQDATA_in[14] = (CONFREQDATA[14] !== 1'bz) && CONFREQDATA_delay[14]; // rv 0 + assign CONFREQDATA_in[15] = (CONFREQDATA[15] !== 1'bz) && CONFREQDATA_delay[15]; // rv 0 + assign CONFREQDATA_in[16] = (CONFREQDATA[16] !== 1'bz) && CONFREQDATA_delay[16]; // rv 0 + assign CONFREQDATA_in[17] = (CONFREQDATA[17] !== 1'bz) && CONFREQDATA_delay[17]; // rv 0 + assign CONFREQDATA_in[18] = (CONFREQDATA[18] !== 1'bz) && CONFREQDATA_delay[18]; // rv 0 + assign CONFREQDATA_in[19] = (CONFREQDATA[19] !== 1'bz) && CONFREQDATA_delay[19]; // rv 0 + assign CONFREQDATA_in[1] = (CONFREQDATA[1] !== 1'bz) && CONFREQDATA_delay[1]; // rv 0 + assign CONFREQDATA_in[20] = (CONFREQDATA[20] !== 1'bz) && CONFREQDATA_delay[20]; // rv 0 + assign CONFREQDATA_in[21] = (CONFREQDATA[21] !== 1'bz) && CONFREQDATA_delay[21]; // rv 0 + assign CONFREQDATA_in[22] = (CONFREQDATA[22] !== 1'bz) && CONFREQDATA_delay[22]; // rv 0 + assign CONFREQDATA_in[23] = (CONFREQDATA[23] !== 1'bz) && CONFREQDATA_delay[23]; // rv 0 + assign CONFREQDATA_in[24] = (CONFREQDATA[24] !== 1'bz) && CONFREQDATA_delay[24]; // rv 0 + assign CONFREQDATA_in[25] = (CONFREQDATA[25] !== 1'bz) && CONFREQDATA_delay[25]; // rv 0 + assign CONFREQDATA_in[26] = (CONFREQDATA[26] !== 1'bz) && CONFREQDATA_delay[26]; // rv 0 + assign CONFREQDATA_in[27] = (CONFREQDATA[27] !== 1'bz) && CONFREQDATA_delay[27]; // rv 0 + assign CONFREQDATA_in[28] = (CONFREQDATA[28] !== 1'bz) && CONFREQDATA_delay[28]; // rv 0 + assign CONFREQDATA_in[29] = (CONFREQDATA[29] !== 1'bz) && CONFREQDATA_delay[29]; // rv 0 + assign CONFREQDATA_in[2] = (CONFREQDATA[2] !== 1'bz) && CONFREQDATA_delay[2]; // rv 0 + assign CONFREQDATA_in[30] = (CONFREQDATA[30] !== 1'bz) && CONFREQDATA_delay[30]; // rv 0 + assign CONFREQDATA_in[31] = (CONFREQDATA[31] !== 1'bz) && CONFREQDATA_delay[31]; // rv 0 + assign CONFREQDATA_in[3] = (CONFREQDATA[3] !== 1'bz) && CONFREQDATA_delay[3]; // rv 0 + assign CONFREQDATA_in[4] = (CONFREQDATA[4] !== 1'bz) && CONFREQDATA_delay[4]; // rv 0 + assign CONFREQDATA_in[5] = (CONFREQDATA[5] !== 1'bz) && CONFREQDATA_delay[5]; // rv 0 + assign CONFREQDATA_in[6] = (CONFREQDATA[6] !== 1'bz) && CONFREQDATA_delay[6]; // rv 0 + assign CONFREQDATA_in[7] = (CONFREQDATA[7] !== 1'bz) && CONFREQDATA_delay[7]; // rv 0 + assign CONFREQDATA_in[8] = (CONFREQDATA[8] !== 1'bz) && CONFREQDATA_delay[8]; // rv 0 + assign CONFREQDATA_in[9] = (CONFREQDATA[9] !== 1'bz) && CONFREQDATA_delay[9]; // rv 0 + assign CONFREQREGNUM_in[0] = (CONFREQREGNUM[0] !== 1'bz) && CONFREQREGNUM_delay[0]; // rv 0 + assign CONFREQREGNUM_in[1] = (CONFREQREGNUM[1] !== 1'bz) && CONFREQREGNUM_delay[1]; // rv 0 + assign CONFREQREGNUM_in[2] = (CONFREQREGNUM[2] !== 1'bz) && CONFREQREGNUM_delay[2]; // rv 0 + assign CONFREQREGNUM_in[3] = (CONFREQREGNUM[3] !== 1'bz) && CONFREQREGNUM_delay[3]; // rv 0 + assign CONFREQTYPE_in[0] = (CONFREQTYPE[0] !== 1'bz) && CONFREQTYPE_delay[0]; // rv 0 + assign CONFREQTYPE_in[1] = (CONFREQTYPE[1] !== 1'bz) && CONFREQTYPE_delay[1]; // rv 0 + assign CONFREQVALID_in = (CONFREQVALID !== 1'bz) && CONFREQVALID_delay; // rv 0 + assign CORECLKMICOMPLETIONRAML_in = (CORECLKMICOMPLETIONRAML !== 1'bz) && CORECLKMICOMPLETIONRAML_delay; // rv 0 + assign CORECLKMICOMPLETIONRAMU_in = (CORECLKMICOMPLETIONRAMU !== 1'bz) && CORECLKMICOMPLETIONRAMU_delay; // rv 0 + assign CORECLKMIREPLAYRAM_in = (CORECLKMIREPLAYRAM !== 1'bz) && CORECLKMIREPLAYRAM_delay; // rv 0 + assign CORECLKMIREQUESTRAM_in = (CORECLKMIREQUESTRAM !== 1'bz) && CORECLKMIREQUESTRAM_delay; // rv 0 + assign CORECLK_in = (CORECLK !== 1'bz) && CORECLK_delay; // rv 0 + assign DBGCFGLOCALMGMTREGOVERRIDE_in = (DBGCFGLOCALMGMTREGOVERRIDE !== 1'bz) && DBGCFGLOCALMGMTREGOVERRIDE_delay; // rv 0 + assign DBGDATASEL_in[0] = (DBGDATASEL[0] !== 1'bz) && DBGDATASEL_delay[0]; // rv 0 + assign DBGDATASEL_in[1] = (DBGDATASEL[1] !== 1'bz) && DBGDATASEL_delay[1]; // rv 0 + assign DBGDATASEL_in[2] = (DBGDATASEL[2] !== 1'bz) && DBGDATASEL_delay[2]; // rv 0 + assign DBGDATASEL_in[3] = (DBGDATASEL[3] !== 1'bz) && DBGDATASEL_delay[3]; // rv 0 + assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0 + assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0 + assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0 + assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0 + assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0 + assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0 + assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0 + assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0 + assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0 + assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0 + assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0 + assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0 + assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0 + assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0 + assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0 + assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0 + assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0 + assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0 + assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0 + assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0 + assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0 + assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0 + assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0 + assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0 + assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0 + assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0 + assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0 + assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0 + assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0 + assign LL2LMSAXISTXTUSER_in[0] = (LL2LMSAXISTXTUSER[0] !== 1'bz) && LL2LMSAXISTXTUSER_delay[0]; // rv 0 + assign LL2LMSAXISTXTUSER_in[10] = (LL2LMSAXISTXTUSER[10] !== 1'bz) && LL2LMSAXISTXTUSER_delay[10]; // rv 0 + assign LL2LMSAXISTXTUSER_in[11] = (LL2LMSAXISTXTUSER[11] !== 1'bz) && LL2LMSAXISTXTUSER_delay[11]; // rv 0 + assign LL2LMSAXISTXTUSER_in[12] = (LL2LMSAXISTXTUSER[12] !== 1'bz) && LL2LMSAXISTXTUSER_delay[12]; // rv 0 + assign LL2LMSAXISTXTUSER_in[13] = (LL2LMSAXISTXTUSER[13] !== 1'bz) && LL2LMSAXISTXTUSER_delay[13]; // rv 0 + assign LL2LMSAXISTXTUSER_in[1] = (LL2LMSAXISTXTUSER[1] !== 1'bz) && LL2LMSAXISTXTUSER_delay[1]; // rv 0 + assign LL2LMSAXISTXTUSER_in[2] = (LL2LMSAXISTXTUSER[2] !== 1'bz) && LL2LMSAXISTXTUSER_delay[2]; // rv 0 + assign LL2LMSAXISTXTUSER_in[3] = (LL2LMSAXISTXTUSER[3] !== 1'bz) && LL2LMSAXISTXTUSER_delay[3]; // rv 0 + assign LL2LMSAXISTXTUSER_in[4] = (LL2LMSAXISTXTUSER[4] !== 1'bz) && LL2LMSAXISTXTUSER_delay[4]; // rv 0 + assign LL2LMSAXISTXTUSER_in[5] = (LL2LMSAXISTXTUSER[5] !== 1'bz) && LL2LMSAXISTXTUSER_delay[5]; // rv 0 + assign LL2LMSAXISTXTUSER_in[6] = (LL2LMSAXISTXTUSER[6] !== 1'bz) && LL2LMSAXISTXTUSER_delay[6]; // rv 0 + assign LL2LMSAXISTXTUSER_in[7] = (LL2LMSAXISTXTUSER[7] !== 1'bz) && LL2LMSAXISTXTUSER_delay[7]; // rv 0 + assign LL2LMSAXISTXTUSER_in[8] = (LL2LMSAXISTXTUSER[8] !== 1'bz) && LL2LMSAXISTXTUSER_delay[8]; // rv 0 + assign LL2LMSAXISTXTUSER_in[9] = (LL2LMSAXISTXTUSER[9] !== 1'bz) && LL2LMSAXISTXTUSER_delay[9]; // rv 0 + assign LL2LMSAXISTXTVALID_in = (LL2LMSAXISTXTVALID !== 1'bz) && LL2LMSAXISTXTVALID_delay; // rv 0 + assign LL2LMTXTLPID0_in[0] = (LL2LMTXTLPID0[0] !== 1'bz) && LL2LMTXTLPID0_delay[0]; // rv 0 + assign LL2LMTXTLPID0_in[1] = (LL2LMTXTLPID0[1] !== 1'bz) && LL2LMTXTLPID0_delay[1]; // rv 0 + assign LL2LMTXTLPID0_in[2] = (LL2LMTXTLPID0[2] !== 1'bz) && LL2LMTXTLPID0_delay[2]; // rv 0 + assign LL2LMTXTLPID0_in[3] = (LL2LMTXTLPID0[3] !== 1'bz) && LL2LMTXTLPID0_delay[3]; // rv 0 + assign LL2LMTXTLPID1_in[0] = (LL2LMTXTLPID1[0] !== 1'bz) && LL2LMTXTLPID1_delay[0]; // rv 0 + assign LL2LMTXTLPID1_in[1] = (LL2LMTXTLPID1[1] !== 1'bz) && LL2LMTXTLPID1_delay[1]; // rv 0 + assign LL2LMTXTLPID1_in[2] = (LL2LMTXTLPID1[2] !== 1'bz) && LL2LMTXTLPID1_delay[2]; // rv 0 + assign LL2LMTXTLPID1_in[3] = (LL2LMTXTLPID1[3] !== 1'bz) && LL2LMTXTLPID1_delay[3]; // rv 0 + assign MAXISCQTREADY_in[0] = (MAXISCQTREADY[0] !== 1'bz) && MAXISCQTREADY_delay[0]; // rv 0 + assign MAXISCQTREADY_in[10] = (MAXISCQTREADY[10] !== 1'bz) && MAXISCQTREADY_delay[10]; // rv 0 + assign MAXISCQTREADY_in[11] = (MAXISCQTREADY[11] !== 1'bz) && MAXISCQTREADY_delay[11]; // rv 0 + assign MAXISCQTREADY_in[12] = (MAXISCQTREADY[12] !== 1'bz) && MAXISCQTREADY_delay[12]; // rv 0 + assign MAXISCQTREADY_in[13] = (MAXISCQTREADY[13] !== 1'bz) && MAXISCQTREADY_delay[13]; // rv 0 + assign MAXISCQTREADY_in[14] = (MAXISCQTREADY[14] !== 1'bz) && MAXISCQTREADY_delay[14]; // rv 0 + assign MAXISCQTREADY_in[15] = (MAXISCQTREADY[15] !== 1'bz) && MAXISCQTREADY_delay[15]; // rv 0 + assign MAXISCQTREADY_in[16] = (MAXISCQTREADY[16] !== 1'bz) && MAXISCQTREADY_delay[16]; // rv 0 + assign MAXISCQTREADY_in[17] = (MAXISCQTREADY[17] !== 1'bz) && MAXISCQTREADY_delay[17]; // rv 0 + assign MAXISCQTREADY_in[18] = (MAXISCQTREADY[18] !== 1'bz) && MAXISCQTREADY_delay[18]; // rv 0 + assign MAXISCQTREADY_in[19] = (MAXISCQTREADY[19] !== 1'bz) && MAXISCQTREADY_delay[19]; // rv 0 + assign MAXISCQTREADY_in[1] = (MAXISCQTREADY[1] !== 1'bz) && MAXISCQTREADY_delay[1]; // rv 0 + assign MAXISCQTREADY_in[20] = (MAXISCQTREADY[20] !== 1'bz) && MAXISCQTREADY_delay[20]; // rv 0 + assign MAXISCQTREADY_in[21] = (MAXISCQTREADY[21] !== 1'bz) && MAXISCQTREADY_delay[21]; // rv 0 + assign MAXISCQTREADY_in[2] = (MAXISCQTREADY[2] !== 1'bz) && MAXISCQTREADY_delay[2]; // rv 0 + assign MAXISCQTREADY_in[3] = (MAXISCQTREADY[3] !== 1'bz) && MAXISCQTREADY_delay[3]; // rv 0 + assign MAXISCQTREADY_in[4] = (MAXISCQTREADY[4] !== 1'bz) && MAXISCQTREADY_delay[4]; // rv 0 + assign MAXISCQTREADY_in[5] = (MAXISCQTREADY[5] !== 1'bz) && MAXISCQTREADY_delay[5]; // rv 0 + assign MAXISCQTREADY_in[6] = (MAXISCQTREADY[6] !== 1'bz) && MAXISCQTREADY_delay[6]; // rv 0 + assign MAXISCQTREADY_in[7] = (MAXISCQTREADY[7] !== 1'bz) && MAXISCQTREADY_delay[7]; // rv 0 + assign MAXISCQTREADY_in[8] = (MAXISCQTREADY[8] !== 1'bz) && MAXISCQTREADY_delay[8]; // rv 0 + assign MAXISCQTREADY_in[9] = (MAXISCQTREADY[9] !== 1'bz) && MAXISCQTREADY_delay[9]; // rv 0 + assign MAXISRCTREADY_in[0] = (MAXISRCTREADY[0] !== 1'bz) && MAXISRCTREADY_delay[0]; // rv 0 + assign MAXISRCTREADY_in[10] = (MAXISRCTREADY[10] !== 1'bz) && MAXISRCTREADY_delay[10]; // rv 0 + assign MAXISRCTREADY_in[11] = (MAXISRCTREADY[11] !== 1'bz) && MAXISRCTREADY_delay[11]; // rv 0 + assign MAXISRCTREADY_in[12] = (MAXISRCTREADY[12] !== 1'bz) && MAXISRCTREADY_delay[12]; // rv 0 + assign MAXISRCTREADY_in[13] = (MAXISRCTREADY[13] !== 1'bz) && MAXISRCTREADY_delay[13]; // rv 0 + assign MAXISRCTREADY_in[14] = (MAXISRCTREADY[14] !== 1'bz) && MAXISRCTREADY_delay[14]; // rv 0 + assign MAXISRCTREADY_in[15] = (MAXISRCTREADY[15] !== 1'bz) && MAXISRCTREADY_delay[15]; // rv 0 + assign MAXISRCTREADY_in[16] = (MAXISRCTREADY[16] !== 1'bz) && MAXISRCTREADY_delay[16]; // rv 0 + assign MAXISRCTREADY_in[17] = (MAXISRCTREADY[17] !== 1'bz) && MAXISRCTREADY_delay[17]; // rv 0 + assign MAXISRCTREADY_in[18] = (MAXISRCTREADY[18] !== 1'bz) && MAXISRCTREADY_delay[18]; // rv 0 + assign MAXISRCTREADY_in[19] = (MAXISRCTREADY[19] !== 1'bz) && MAXISRCTREADY_delay[19]; // rv 0 + assign MAXISRCTREADY_in[1] = (MAXISRCTREADY[1] !== 1'bz) && MAXISRCTREADY_delay[1]; // rv 0 + assign MAXISRCTREADY_in[20] = (MAXISRCTREADY[20] !== 1'bz) && MAXISRCTREADY_delay[20]; // rv 0 + assign MAXISRCTREADY_in[21] = (MAXISRCTREADY[21] !== 1'bz) && MAXISRCTREADY_delay[21]; // rv 0 + assign MAXISRCTREADY_in[2] = (MAXISRCTREADY[2] !== 1'bz) && MAXISRCTREADY_delay[2]; // rv 0 + assign MAXISRCTREADY_in[3] = (MAXISRCTREADY[3] !== 1'bz) && MAXISRCTREADY_delay[3]; // rv 0 + assign MAXISRCTREADY_in[4] = (MAXISRCTREADY[4] !== 1'bz) && MAXISRCTREADY_delay[4]; // rv 0 + assign MAXISRCTREADY_in[5] = (MAXISRCTREADY[5] !== 1'bz) && MAXISRCTREADY_delay[5]; // rv 0 + assign MAXISRCTREADY_in[6] = (MAXISRCTREADY[6] !== 1'bz) && MAXISRCTREADY_delay[6]; // rv 0 + assign MAXISRCTREADY_in[7] = (MAXISRCTREADY[7] !== 1'bz) && MAXISRCTREADY_delay[7]; // rv 0 + assign MAXISRCTREADY_in[8] = (MAXISRCTREADY[8] !== 1'bz) && MAXISRCTREADY_delay[8]; // rv 0 + assign MAXISRCTREADY_in[9] = (MAXISRCTREADY[9] !== 1'bz) && MAXISRCTREADY_delay[9]; // rv 0 + assign MCAPCLK_in = (MCAPCLK !== 1'bz) && MCAPCLK_delay; // rv 0 + assign MCAPPERST0B_in = (MCAPPERST0B === 1'bz) || MCAPPERST0B_delay; // rv 1 + assign MCAPPERST1B_in = (MCAPPERST1B === 1'bz) || MCAPPERST1B_delay; // rv 1 + assign MGMTRESETN_in = (MGMTRESETN !== 1'bz) && MGMTRESETN_delay; // rv 0 + assign MGMTSTICKYRESETN_in = (MGMTSTICKYRESETN !== 1'bz) && MGMTSTICKYRESETN_delay; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[0] = (MICOMPLETIONRAMREADDATA[0] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[0]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[100] = (MICOMPLETIONRAMREADDATA[100] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[100]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[101] = (MICOMPLETIONRAMREADDATA[101] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[101]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[102] = (MICOMPLETIONRAMREADDATA[102] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[102]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[103] = (MICOMPLETIONRAMREADDATA[103] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[103]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[104] = (MICOMPLETIONRAMREADDATA[104] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[104]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[105] = (MICOMPLETIONRAMREADDATA[105] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[105]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[106] = (MICOMPLETIONRAMREADDATA[106] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[106]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[107] = (MICOMPLETIONRAMREADDATA[107] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[107]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[108] = (MICOMPLETIONRAMREADDATA[108] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[108]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[109] = (MICOMPLETIONRAMREADDATA[109] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[109]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[10] = (MICOMPLETIONRAMREADDATA[10] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[10]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[110] = (MICOMPLETIONRAMREADDATA[110] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[110]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[111] = (MICOMPLETIONRAMREADDATA[111] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[111]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[112] = (MICOMPLETIONRAMREADDATA[112] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[112]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[113] = (MICOMPLETIONRAMREADDATA[113] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[113]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[114] = (MICOMPLETIONRAMREADDATA[114] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[114]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[115] = (MICOMPLETIONRAMREADDATA[115] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[115]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[116] = (MICOMPLETIONRAMREADDATA[116] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[116]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[117] = (MICOMPLETIONRAMREADDATA[117] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[117]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[118] = (MICOMPLETIONRAMREADDATA[118] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[118]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[119] = (MICOMPLETIONRAMREADDATA[119] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[119]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[11] = (MICOMPLETIONRAMREADDATA[11] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[11]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[120] = (MICOMPLETIONRAMREADDATA[120] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[120]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[121] = (MICOMPLETIONRAMREADDATA[121] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[121]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[122] = (MICOMPLETIONRAMREADDATA[122] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[122]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[123] = (MICOMPLETIONRAMREADDATA[123] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[123]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[124] = (MICOMPLETIONRAMREADDATA[124] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[124]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[125] = (MICOMPLETIONRAMREADDATA[125] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[125]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[126] = (MICOMPLETIONRAMREADDATA[126] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[126]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[127] = (MICOMPLETIONRAMREADDATA[127] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[127]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[128] = (MICOMPLETIONRAMREADDATA[128] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[128]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[129] = (MICOMPLETIONRAMREADDATA[129] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[129]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[12] = (MICOMPLETIONRAMREADDATA[12] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[12]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[130] = (MICOMPLETIONRAMREADDATA[130] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[130]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[131] = (MICOMPLETIONRAMREADDATA[131] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[131]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[132] = (MICOMPLETIONRAMREADDATA[132] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[132]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[133] = (MICOMPLETIONRAMREADDATA[133] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[133]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[134] = (MICOMPLETIONRAMREADDATA[134] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[134]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[135] = (MICOMPLETIONRAMREADDATA[135] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[135]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[136] = (MICOMPLETIONRAMREADDATA[136] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[136]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[137] = (MICOMPLETIONRAMREADDATA[137] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[137]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[138] = (MICOMPLETIONRAMREADDATA[138] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[138]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[139] = (MICOMPLETIONRAMREADDATA[139] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[139]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[13] = (MICOMPLETIONRAMREADDATA[13] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[13]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[140] = (MICOMPLETIONRAMREADDATA[140] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[140]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[141] = (MICOMPLETIONRAMREADDATA[141] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[141]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[142] = (MICOMPLETIONRAMREADDATA[142] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[142]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[143] = (MICOMPLETIONRAMREADDATA[143] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[143]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[14] = (MICOMPLETIONRAMREADDATA[14] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[14]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[15] = (MICOMPLETIONRAMREADDATA[15] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[15]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[16] = (MICOMPLETIONRAMREADDATA[16] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[16]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[17] = (MICOMPLETIONRAMREADDATA[17] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[17]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[18] = (MICOMPLETIONRAMREADDATA[18] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[18]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[19] = (MICOMPLETIONRAMREADDATA[19] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[19]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[1] = (MICOMPLETIONRAMREADDATA[1] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[1]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[20] = (MICOMPLETIONRAMREADDATA[20] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[20]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[21] = (MICOMPLETIONRAMREADDATA[21] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[21]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[22] = (MICOMPLETIONRAMREADDATA[22] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[22]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[23] = (MICOMPLETIONRAMREADDATA[23] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[23]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[24] = (MICOMPLETIONRAMREADDATA[24] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[24]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[25] = (MICOMPLETIONRAMREADDATA[25] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[25]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[26] = (MICOMPLETIONRAMREADDATA[26] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[26]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[27] = (MICOMPLETIONRAMREADDATA[27] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[27]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[28] = (MICOMPLETIONRAMREADDATA[28] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[28]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[29] = (MICOMPLETIONRAMREADDATA[29] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[29]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[2] = (MICOMPLETIONRAMREADDATA[2] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[2]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[30] = (MICOMPLETIONRAMREADDATA[30] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[30]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[31] = (MICOMPLETIONRAMREADDATA[31] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[31]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[32] = (MICOMPLETIONRAMREADDATA[32] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[32]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[33] = (MICOMPLETIONRAMREADDATA[33] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[33]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[34] = (MICOMPLETIONRAMREADDATA[34] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[34]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[35] = (MICOMPLETIONRAMREADDATA[35] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[35]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[36] = (MICOMPLETIONRAMREADDATA[36] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[36]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[37] = (MICOMPLETIONRAMREADDATA[37] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[37]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[38] = (MICOMPLETIONRAMREADDATA[38] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[38]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[39] = (MICOMPLETIONRAMREADDATA[39] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[39]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[3] = (MICOMPLETIONRAMREADDATA[3] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[3]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[40] = (MICOMPLETIONRAMREADDATA[40] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[40]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[41] = (MICOMPLETIONRAMREADDATA[41] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[41]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[42] = (MICOMPLETIONRAMREADDATA[42] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[42]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[43] = (MICOMPLETIONRAMREADDATA[43] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[43]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[44] = (MICOMPLETIONRAMREADDATA[44] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[44]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[45] = (MICOMPLETIONRAMREADDATA[45] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[45]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[46] = (MICOMPLETIONRAMREADDATA[46] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[46]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[47] = (MICOMPLETIONRAMREADDATA[47] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[47]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[48] = (MICOMPLETIONRAMREADDATA[48] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[48]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[49] = (MICOMPLETIONRAMREADDATA[49] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[49]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[4] = (MICOMPLETIONRAMREADDATA[4] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[4]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[50] = (MICOMPLETIONRAMREADDATA[50] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[50]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[51] = (MICOMPLETIONRAMREADDATA[51] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[51]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[52] = (MICOMPLETIONRAMREADDATA[52] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[52]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[53] = (MICOMPLETIONRAMREADDATA[53] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[53]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[54] = (MICOMPLETIONRAMREADDATA[54] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[54]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[55] = (MICOMPLETIONRAMREADDATA[55] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[55]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[56] = (MICOMPLETIONRAMREADDATA[56] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[56]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[57] = (MICOMPLETIONRAMREADDATA[57] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[57]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[58] = (MICOMPLETIONRAMREADDATA[58] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[58]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[59] = (MICOMPLETIONRAMREADDATA[59] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[59]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[5] = (MICOMPLETIONRAMREADDATA[5] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[5]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[60] = (MICOMPLETIONRAMREADDATA[60] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[60]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[61] = (MICOMPLETIONRAMREADDATA[61] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[61]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[62] = (MICOMPLETIONRAMREADDATA[62] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[62]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[63] = (MICOMPLETIONRAMREADDATA[63] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[63]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[64] = (MICOMPLETIONRAMREADDATA[64] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[64]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[65] = (MICOMPLETIONRAMREADDATA[65] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[65]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[66] = (MICOMPLETIONRAMREADDATA[66] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[66]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[67] = (MICOMPLETIONRAMREADDATA[67] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[67]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[68] = (MICOMPLETIONRAMREADDATA[68] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[68]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[69] = (MICOMPLETIONRAMREADDATA[69] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[69]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[6] = (MICOMPLETIONRAMREADDATA[6] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[6]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[70] = (MICOMPLETIONRAMREADDATA[70] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[70]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[71] = (MICOMPLETIONRAMREADDATA[71] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[71]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[72] = (MICOMPLETIONRAMREADDATA[72] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[72]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[73] = (MICOMPLETIONRAMREADDATA[73] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[73]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[74] = (MICOMPLETIONRAMREADDATA[74] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[74]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[75] = (MICOMPLETIONRAMREADDATA[75] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[75]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[76] = (MICOMPLETIONRAMREADDATA[76] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[76]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[77] = (MICOMPLETIONRAMREADDATA[77] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[77]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[78] = (MICOMPLETIONRAMREADDATA[78] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[78]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[79] = (MICOMPLETIONRAMREADDATA[79] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[79]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[7] = (MICOMPLETIONRAMREADDATA[7] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[7]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[80] = (MICOMPLETIONRAMREADDATA[80] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[80]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[81] = (MICOMPLETIONRAMREADDATA[81] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[81]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[82] = (MICOMPLETIONRAMREADDATA[82] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[82]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[83] = (MICOMPLETIONRAMREADDATA[83] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[83]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[84] = (MICOMPLETIONRAMREADDATA[84] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[84]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[85] = (MICOMPLETIONRAMREADDATA[85] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[85]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[86] = (MICOMPLETIONRAMREADDATA[86] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[86]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[87] = (MICOMPLETIONRAMREADDATA[87] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[87]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[88] = (MICOMPLETIONRAMREADDATA[88] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[88]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[89] = (MICOMPLETIONRAMREADDATA[89] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[89]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[8] = (MICOMPLETIONRAMREADDATA[8] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[8]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[90] = (MICOMPLETIONRAMREADDATA[90] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[90]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[91] = (MICOMPLETIONRAMREADDATA[91] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[91]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[92] = (MICOMPLETIONRAMREADDATA[92] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[92]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[93] = (MICOMPLETIONRAMREADDATA[93] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[93]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[94] = (MICOMPLETIONRAMREADDATA[94] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[94]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[95] = (MICOMPLETIONRAMREADDATA[95] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[95]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[96] = (MICOMPLETIONRAMREADDATA[96] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[96]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[97] = (MICOMPLETIONRAMREADDATA[97] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[97]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[98] = (MICOMPLETIONRAMREADDATA[98] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[98]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[99] = (MICOMPLETIONRAMREADDATA[99] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[99]; // rv 0 + assign MICOMPLETIONRAMREADDATA_in[9] = (MICOMPLETIONRAMREADDATA[9] !== 1'bz) && MICOMPLETIONRAMREADDATA_delay[9]; // rv 0 + assign MIREPLAYRAMREADDATA_in[0] = (MIREPLAYRAMREADDATA[0] !== 1'bz) && MIREPLAYRAMREADDATA_delay[0]; // rv 0 + assign MIREPLAYRAMREADDATA_in[100] = (MIREPLAYRAMREADDATA[100] !== 1'bz) && MIREPLAYRAMREADDATA_delay[100]; // rv 0 + assign MIREPLAYRAMREADDATA_in[101] = (MIREPLAYRAMREADDATA[101] !== 1'bz) && MIREPLAYRAMREADDATA_delay[101]; // rv 0 + assign MIREPLAYRAMREADDATA_in[102] = (MIREPLAYRAMREADDATA[102] !== 1'bz) && MIREPLAYRAMREADDATA_delay[102]; // rv 0 + assign MIREPLAYRAMREADDATA_in[103] = (MIREPLAYRAMREADDATA[103] !== 1'bz) && MIREPLAYRAMREADDATA_delay[103]; // rv 0 + assign MIREPLAYRAMREADDATA_in[104] = (MIREPLAYRAMREADDATA[104] !== 1'bz) && MIREPLAYRAMREADDATA_delay[104]; // rv 0 + assign MIREPLAYRAMREADDATA_in[105] = (MIREPLAYRAMREADDATA[105] !== 1'bz) && MIREPLAYRAMREADDATA_delay[105]; // rv 0 + assign MIREPLAYRAMREADDATA_in[106] = (MIREPLAYRAMREADDATA[106] !== 1'bz) && MIREPLAYRAMREADDATA_delay[106]; // rv 0 + assign MIREPLAYRAMREADDATA_in[107] = (MIREPLAYRAMREADDATA[107] !== 1'bz) && MIREPLAYRAMREADDATA_delay[107]; // rv 0 + assign MIREPLAYRAMREADDATA_in[108] = (MIREPLAYRAMREADDATA[108] !== 1'bz) && MIREPLAYRAMREADDATA_delay[108]; // rv 0 + assign MIREPLAYRAMREADDATA_in[109] = (MIREPLAYRAMREADDATA[109] !== 1'bz) && MIREPLAYRAMREADDATA_delay[109]; // rv 0 + assign MIREPLAYRAMREADDATA_in[10] = (MIREPLAYRAMREADDATA[10] !== 1'bz) && MIREPLAYRAMREADDATA_delay[10]; // rv 0 + assign MIREPLAYRAMREADDATA_in[110] = (MIREPLAYRAMREADDATA[110] !== 1'bz) && MIREPLAYRAMREADDATA_delay[110]; // rv 0 + assign MIREPLAYRAMREADDATA_in[111] = (MIREPLAYRAMREADDATA[111] !== 1'bz) && MIREPLAYRAMREADDATA_delay[111]; // rv 0 + assign MIREPLAYRAMREADDATA_in[112] = (MIREPLAYRAMREADDATA[112] !== 1'bz) && MIREPLAYRAMREADDATA_delay[112]; // rv 0 + assign MIREPLAYRAMREADDATA_in[113] = (MIREPLAYRAMREADDATA[113] !== 1'bz) && MIREPLAYRAMREADDATA_delay[113]; // rv 0 + assign MIREPLAYRAMREADDATA_in[114] = (MIREPLAYRAMREADDATA[114] !== 1'bz) && MIREPLAYRAMREADDATA_delay[114]; // rv 0 + assign MIREPLAYRAMREADDATA_in[115] = (MIREPLAYRAMREADDATA[115] !== 1'bz) && MIREPLAYRAMREADDATA_delay[115]; // rv 0 + assign MIREPLAYRAMREADDATA_in[116] = (MIREPLAYRAMREADDATA[116] !== 1'bz) && MIREPLAYRAMREADDATA_delay[116]; // rv 0 + assign MIREPLAYRAMREADDATA_in[117] = (MIREPLAYRAMREADDATA[117] !== 1'bz) && MIREPLAYRAMREADDATA_delay[117]; // rv 0 + assign MIREPLAYRAMREADDATA_in[118] = (MIREPLAYRAMREADDATA[118] !== 1'bz) && MIREPLAYRAMREADDATA_delay[118]; // rv 0 + assign MIREPLAYRAMREADDATA_in[119] = (MIREPLAYRAMREADDATA[119] !== 1'bz) && MIREPLAYRAMREADDATA_delay[119]; // rv 0 + assign MIREPLAYRAMREADDATA_in[11] = (MIREPLAYRAMREADDATA[11] !== 1'bz) && MIREPLAYRAMREADDATA_delay[11]; // rv 0 + assign MIREPLAYRAMREADDATA_in[120] = (MIREPLAYRAMREADDATA[120] !== 1'bz) && MIREPLAYRAMREADDATA_delay[120]; // rv 0 + assign MIREPLAYRAMREADDATA_in[121] = (MIREPLAYRAMREADDATA[121] !== 1'bz) && MIREPLAYRAMREADDATA_delay[121]; // rv 0 + assign MIREPLAYRAMREADDATA_in[122] = (MIREPLAYRAMREADDATA[122] !== 1'bz) && MIREPLAYRAMREADDATA_delay[122]; // rv 0 + assign MIREPLAYRAMREADDATA_in[123] = (MIREPLAYRAMREADDATA[123] !== 1'bz) && MIREPLAYRAMREADDATA_delay[123]; // rv 0 + assign MIREPLAYRAMREADDATA_in[124] = (MIREPLAYRAMREADDATA[124] !== 1'bz) && MIREPLAYRAMREADDATA_delay[124]; // rv 0 + assign MIREPLAYRAMREADDATA_in[125] = (MIREPLAYRAMREADDATA[125] !== 1'bz) && MIREPLAYRAMREADDATA_delay[125]; // rv 0 + assign MIREPLAYRAMREADDATA_in[126] = (MIREPLAYRAMREADDATA[126] !== 1'bz) && MIREPLAYRAMREADDATA_delay[126]; // rv 0 + assign MIREPLAYRAMREADDATA_in[127] = (MIREPLAYRAMREADDATA[127] !== 1'bz) && MIREPLAYRAMREADDATA_delay[127]; // rv 0 + assign MIREPLAYRAMREADDATA_in[128] = (MIREPLAYRAMREADDATA[128] !== 1'bz) && MIREPLAYRAMREADDATA_delay[128]; // rv 0 + assign MIREPLAYRAMREADDATA_in[129] = (MIREPLAYRAMREADDATA[129] !== 1'bz) && MIREPLAYRAMREADDATA_delay[129]; // rv 0 + assign MIREPLAYRAMREADDATA_in[12] = (MIREPLAYRAMREADDATA[12] !== 1'bz) && MIREPLAYRAMREADDATA_delay[12]; // rv 0 + assign MIREPLAYRAMREADDATA_in[130] = (MIREPLAYRAMREADDATA[130] !== 1'bz) && MIREPLAYRAMREADDATA_delay[130]; // rv 0 + assign MIREPLAYRAMREADDATA_in[131] = (MIREPLAYRAMREADDATA[131] !== 1'bz) && MIREPLAYRAMREADDATA_delay[131]; // rv 0 + assign MIREPLAYRAMREADDATA_in[132] = (MIREPLAYRAMREADDATA[132] !== 1'bz) && MIREPLAYRAMREADDATA_delay[132]; // rv 0 + assign MIREPLAYRAMREADDATA_in[133] = (MIREPLAYRAMREADDATA[133] !== 1'bz) && MIREPLAYRAMREADDATA_delay[133]; // rv 0 + assign MIREPLAYRAMREADDATA_in[134] = (MIREPLAYRAMREADDATA[134] !== 1'bz) && MIREPLAYRAMREADDATA_delay[134]; // rv 0 + assign MIREPLAYRAMREADDATA_in[135] = (MIREPLAYRAMREADDATA[135] !== 1'bz) && MIREPLAYRAMREADDATA_delay[135]; // rv 0 + assign MIREPLAYRAMREADDATA_in[136] = (MIREPLAYRAMREADDATA[136] !== 1'bz) && MIREPLAYRAMREADDATA_delay[136]; // rv 0 + assign MIREPLAYRAMREADDATA_in[137] = (MIREPLAYRAMREADDATA[137] !== 1'bz) && MIREPLAYRAMREADDATA_delay[137]; // rv 0 + assign MIREPLAYRAMREADDATA_in[138] = (MIREPLAYRAMREADDATA[138] !== 1'bz) && MIREPLAYRAMREADDATA_delay[138]; // rv 0 + assign MIREPLAYRAMREADDATA_in[139] = (MIREPLAYRAMREADDATA[139] !== 1'bz) && MIREPLAYRAMREADDATA_delay[139]; // rv 0 + assign MIREPLAYRAMREADDATA_in[13] = (MIREPLAYRAMREADDATA[13] !== 1'bz) && MIREPLAYRAMREADDATA_delay[13]; // rv 0 + assign MIREPLAYRAMREADDATA_in[140] = (MIREPLAYRAMREADDATA[140] !== 1'bz) && MIREPLAYRAMREADDATA_delay[140]; // rv 0 + assign MIREPLAYRAMREADDATA_in[141] = (MIREPLAYRAMREADDATA[141] !== 1'bz) && MIREPLAYRAMREADDATA_delay[141]; // rv 0 + assign MIREPLAYRAMREADDATA_in[142] = (MIREPLAYRAMREADDATA[142] !== 1'bz) && MIREPLAYRAMREADDATA_delay[142]; // rv 0 + assign MIREPLAYRAMREADDATA_in[143] = (MIREPLAYRAMREADDATA[143] !== 1'bz) && MIREPLAYRAMREADDATA_delay[143]; // rv 0 + assign MIREPLAYRAMREADDATA_in[14] = (MIREPLAYRAMREADDATA[14] !== 1'bz) && MIREPLAYRAMREADDATA_delay[14]; // rv 0 + assign MIREPLAYRAMREADDATA_in[15] = (MIREPLAYRAMREADDATA[15] !== 1'bz) && MIREPLAYRAMREADDATA_delay[15]; // rv 0 + assign MIREPLAYRAMREADDATA_in[16] = (MIREPLAYRAMREADDATA[16] !== 1'bz) && MIREPLAYRAMREADDATA_delay[16]; // rv 0 + assign MIREPLAYRAMREADDATA_in[17] = (MIREPLAYRAMREADDATA[17] !== 1'bz) && MIREPLAYRAMREADDATA_delay[17]; // rv 0 + assign MIREPLAYRAMREADDATA_in[18] = (MIREPLAYRAMREADDATA[18] !== 1'bz) && MIREPLAYRAMREADDATA_delay[18]; // rv 0 + assign MIREPLAYRAMREADDATA_in[19] = (MIREPLAYRAMREADDATA[19] !== 1'bz) && MIREPLAYRAMREADDATA_delay[19]; // rv 0 + assign MIREPLAYRAMREADDATA_in[1] = (MIREPLAYRAMREADDATA[1] !== 1'bz) && MIREPLAYRAMREADDATA_delay[1]; // rv 0 + assign MIREPLAYRAMREADDATA_in[20] = (MIREPLAYRAMREADDATA[20] !== 1'bz) && MIREPLAYRAMREADDATA_delay[20]; // rv 0 + assign MIREPLAYRAMREADDATA_in[21] = (MIREPLAYRAMREADDATA[21] !== 1'bz) && MIREPLAYRAMREADDATA_delay[21]; // rv 0 + assign MIREPLAYRAMREADDATA_in[22] = (MIREPLAYRAMREADDATA[22] !== 1'bz) && MIREPLAYRAMREADDATA_delay[22]; // rv 0 + assign MIREPLAYRAMREADDATA_in[23] = (MIREPLAYRAMREADDATA[23] !== 1'bz) && MIREPLAYRAMREADDATA_delay[23]; // rv 0 + assign MIREPLAYRAMREADDATA_in[24] = (MIREPLAYRAMREADDATA[24] !== 1'bz) && MIREPLAYRAMREADDATA_delay[24]; // rv 0 + assign MIREPLAYRAMREADDATA_in[25] = (MIREPLAYRAMREADDATA[25] !== 1'bz) && MIREPLAYRAMREADDATA_delay[25]; // rv 0 + assign MIREPLAYRAMREADDATA_in[26] = (MIREPLAYRAMREADDATA[26] !== 1'bz) && MIREPLAYRAMREADDATA_delay[26]; // rv 0 + assign MIREPLAYRAMREADDATA_in[27] = (MIREPLAYRAMREADDATA[27] !== 1'bz) && MIREPLAYRAMREADDATA_delay[27]; // rv 0 + assign MIREPLAYRAMREADDATA_in[28] = (MIREPLAYRAMREADDATA[28] !== 1'bz) && MIREPLAYRAMREADDATA_delay[28]; // rv 0 + assign MIREPLAYRAMREADDATA_in[29] = (MIREPLAYRAMREADDATA[29] !== 1'bz) && MIREPLAYRAMREADDATA_delay[29]; // rv 0 + assign MIREPLAYRAMREADDATA_in[2] = (MIREPLAYRAMREADDATA[2] !== 1'bz) && MIREPLAYRAMREADDATA_delay[2]; // rv 0 + assign MIREPLAYRAMREADDATA_in[30] = (MIREPLAYRAMREADDATA[30] !== 1'bz) && MIREPLAYRAMREADDATA_delay[30]; // rv 0 + assign MIREPLAYRAMREADDATA_in[31] = (MIREPLAYRAMREADDATA[31] !== 1'bz) && MIREPLAYRAMREADDATA_delay[31]; // rv 0 + assign MIREPLAYRAMREADDATA_in[32] = (MIREPLAYRAMREADDATA[32] !== 1'bz) && MIREPLAYRAMREADDATA_delay[32]; // rv 0 + assign MIREPLAYRAMREADDATA_in[33] = (MIREPLAYRAMREADDATA[33] !== 1'bz) && MIREPLAYRAMREADDATA_delay[33]; // rv 0 + assign MIREPLAYRAMREADDATA_in[34] = (MIREPLAYRAMREADDATA[34] !== 1'bz) && MIREPLAYRAMREADDATA_delay[34]; // rv 0 + assign MIREPLAYRAMREADDATA_in[35] = (MIREPLAYRAMREADDATA[35] !== 1'bz) && MIREPLAYRAMREADDATA_delay[35]; // rv 0 + assign MIREPLAYRAMREADDATA_in[36] = (MIREPLAYRAMREADDATA[36] !== 1'bz) && MIREPLAYRAMREADDATA_delay[36]; // rv 0 + assign MIREPLAYRAMREADDATA_in[37] = (MIREPLAYRAMREADDATA[37] !== 1'bz) && MIREPLAYRAMREADDATA_delay[37]; // rv 0 + assign MIREPLAYRAMREADDATA_in[38] = (MIREPLAYRAMREADDATA[38] !== 1'bz) && MIREPLAYRAMREADDATA_delay[38]; // rv 0 + assign MIREPLAYRAMREADDATA_in[39] = (MIREPLAYRAMREADDATA[39] !== 1'bz) && MIREPLAYRAMREADDATA_delay[39]; // rv 0 + assign MIREPLAYRAMREADDATA_in[3] = (MIREPLAYRAMREADDATA[3] !== 1'bz) && MIREPLAYRAMREADDATA_delay[3]; // rv 0 + assign MIREPLAYRAMREADDATA_in[40] = (MIREPLAYRAMREADDATA[40] !== 1'bz) && MIREPLAYRAMREADDATA_delay[40]; // rv 0 + assign MIREPLAYRAMREADDATA_in[41] = (MIREPLAYRAMREADDATA[41] !== 1'bz) && MIREPLAYRAMREADDATA_delay[41]; // rv 0 + assign MIREPLAYRAMREADDATA_in[42] = (MIREPLAYRAMREADDATA[42] !== 1'bz) && MIREPLAYRAMREADDATA_delay[42]; // rv 0 + assign MIREPLAYRAMREADDATA_in[43] = (MIREPLAYRAMREADDATA[43] !== 1'bz) && MIREPLAYRAMREADDATA_delay[43]; // rv 0 + assign MIREPLAYRAMREADDATA_in[44] = (MIREPLAYRAMREADDATA[44] !== 1'bz) && MIREPLAYRAMREADDATA_delay[44]; // rv 0 + assign MIREPLAYRAMREADDATA_in[45] = (MIREPLAYRAMREADDATA[45] !== 1'bz) && MIREPLAYRAMREADDATA_delay[45]; // rv 0 + assign MIREPLAYRAMREADDATA_in[46] = (MIREPLAYRAMREADDATA[46] !== 1'bz) && MIREPLAYRAMREADDATA_delay[46]; // rv 0 + assign MIREPLAYRAMREADDATA_in[47] = (MIREPLAYRAMREADDATA[47] !== 1'bz) && MIREPLAYRAMREADDATA_delay[47]; // rv 0 + assign MIREPLAYRAMREADDATA_in[48] = (MIREPLAYRAMREADDATA[48] !== 1'bz) && MIREPLAYRAMREADDATA_delay[48]; // rv 0 + assign MIREPLAYRAMREADDATA_in[49] = (MIREPLAYRAMREADDATA[49] !== 1'bz) && MIREPLAYRAMREADDATA_delay[49]; // rv 0 + assign MIREPLAYRAMREADDATA_in[4] = (MIREPLAYRAMREADDATA[4] !== 1'bz) && MIREPLAYRAMREADDATA_delay[4]; // rv 0 + assign MIREPLAYRAMREADDATA_in[50] = (MIREPLAYRAMREADDATA[50] !== 1'bz) && MIREPLAYRAMREADDATA_delay[50]; // rv 0 + assign MIREPLAYRAMREADDATA_in[51] = (MIREPLAYRAMREADDATA[51] !== 1'bz) && MIREPLAYRAMREADDATA_delay[51]; // rv 0 + assign MIREPLAYRAMREADDATA_in[52] = (MIREPLAYRAMREADDATA[52] !== 1'bz) && MIREPLAYRAMREADDATA_delay[52]; // rv 0 + assign MIREPLAYRAMREADDATA_in[53] = (MIREPLAYRAMREADDATA[53] !== 1'bz) && MIREPLAYRAMREADDATA_delay[53]; // rv 0 + assign MIREPLAYRAMREADDATA_in[54] = (MIREPLAYRAMREADDATA[54] !== 1'bz) && MIREPLAYRAMREADDATA_delay[54]; // rv 0 + assign MIREPLAYRAMREADDATA_in[55] = (MIREPLAYRAMREADDATA[55] !== 1'bz) && MIREPLAYRAMREADDATA_delay[55]; // rv 0 + assign MIREPLAYRAMREADDATA_in[56] = (MIREPLAYRAMREADDATA[56] !== 1'bz) && MIREPLAYRAMREADDATA_delay[56]; // rv 0 + assign MIREPLAYRAMREADDATA_in[57] = (MIREPLAYRAMREADDATA[57] !== 1'bz) && MIREPLAYRAMREADDATA_delay[57]; // rv 0 + assign MIREPLAYRAMREADDATA_in[58] = (MIREPLAYRAMREADDATA[58] !== 1'bz) && MIREPLAYRAMREADDATA_delay[58]; // rv 0 + assign MIREPLAYRAMREADDATA_in[59] = (MIREPLAYRAMREADDATA[59] !== 1'bz) && MIREPLAYRAMREADDATA_delay[59]; // rv 0 + assign MIREPLAYRAMREADDATA_in[5] = (MIREPLAYRAMREADDATA[5] !== 1'bz) && MIREPLAYRAMREADDATA_delay[5]; // rv 0 + assign MIREPLAYRAMREADDATA_in[60] = (MIREPLAYRAMREADDATA[60] !== 1'bz) && MIREPLAYRAMREADDATA_delay[60]; // rv 0 + assign MIREPLAYRAMREADDATA_in[61] = (MIREPLAYRAMREADDATA[61] !== 1'bz) && MIREPLAYRAMREADDATA_delay[61]; // rv 0 + assign MIREPLAYRAMREADDATA_in[62] = (MIREPLAYRAMREADDATA[62] !== 1'bz) && MIREPLAYRAMREADDATA_delay[62]; // rv 0 + assign MIREPLAYRAMREADDATA_in[63] = (MIREPLAYRAMREADDATA[63] !== 1'bz) && MIREPLAYRAMREADDATA_delay[63]; // rv 0 + assign MIREPLAYRAMREADDATA_in[64] = (MIREPLAYRAMREADDATA[64] !== 1'bz) && MIREPLAYRAMREADDATA_delay[64]; // rv 0 + assign MIREPLAYRAMREADDATA_in[65] = (MIREPLAYRAMREADDATA[65] !== 1'bz) && MIREPLAYRAMREADDATA_delay[65]; // rv 0 + assign MIREPLAYRAMREADDATA_in[66] = (MIREPLAYRAMREADDATA[66] !== 1'bz) && MIREPLAYRAMREADDATA_delay[66]; // rv 0 + assign MIREPLAYRAMREADDATA_in[67] = (MIREPLAYRAMREADDATA[67] !== 1'bz) && MIREPLAYRAMREADDATA_delay[67]; // rv 0 + assign MIREPLAYRAMREADDATA_in[68] = (MIREPLAYRAMREADDATA[68] !== 1'bz) && MIREPLAYRAMREADDATA_delay[68]; // rv 0 + assign MIREPLAYRAMREADDATA_in[69] = (MIREPLAYRAMREADDATA[69] !== 1'bz) && MIREPLAYRAMREADDATA_delay[69]; // rv 0 + assign MIREPLAYRAMREADDATA_in[6] = (MIREPLAYRAMREADDATA[6] !== 1'bz) && MIREPLAYRAMREADDATA_delay[6]; // rv 0 + assign MIREPLAYRAMREADDATA_in[70] = (MIREPLAYRAMREADDATA[70] !== 1'bz) && MIREPLAYRAMREADDATA_delay[70]; // rv 0 + assign MIREPLAYRAMREADDATA_in[71] = (MIREPLAYRAMREADDATA[71] !== 1'bz) && MIREPLAYRAMREADDATA_delay[71]; // rv 0 + assign MIREPLAYRAMREADDATA_in[72] = (MIREPLAYRAMREADDATA[72] !== 1'bz) && MIREPLAYRAMREADDATA_delay[72]; // rv 0 + assign MIREPLAYRAMREADDATA_in[73] = (MIREPLAYRAMREADDATA[73] !== 1'bz) && MIREPLAYRAMREADDATA_delay[73]; // rv 0 + assign MIREPLAYRAMREADDATA_in[74] = (MIREPLAYRAMREADDATA[74] !== 1'bz) && MIREPLAYRAMREADDATA_delay[74]; // rv 0 + assign MIREPLAYRAMREADDATA_in[75] = (MIREPLAYRAMREADDATA[75] !== 1'bz) && MIREPLAYRAMREADDATA_delay[75]; // rv 0 + assign MIREPLAYRAMREADDATA_in[76] = (MIREPLAYRAMREADDATA[76] !== 1'bz) && MIREPLAYRAMREADDATA_delay[76]; // rv 0 + assign MIREPLAYRAMREADDATA_in[77] = (MIREPLAYRAMREADDATA[77] !== 1'bz) && MIREPLAYRAMREADDATA_delay[77]; // rv 0 + assign MIREPLAYRAMREADDATA_in[78] = (MIREPLAYRAMREADDATA[78] !== 1'bz) && MIREPLAYRAMREADDATA_delay[78]; // rv 0 + assign MIREPLAYRAMREADDATA_in[79] = (MIREPLAYRAMREADDATA[79] !== 1'bz) && MIREPLAYRAMREADDATA_delay[79]; // rv 0 + assign MIREPLAYRAMREADDATA_in[7] = (MIREPLAYRAMREADDATA[7] !== 1'bz) && MIREPLAYRAMREADDATA_delay[7]; // rv 0 + assign MIREPLAYRAMREADDATA_in[80] = (MIREPLAYRAMREADDATA[80] !== 1'bz) && MIREPLAYRAMREADDATA_delay[80]; // rv 0 + assign MIREPLAYRAMREADDATA_in[81] = (MIREPLAYRAMREADDATA[81] !== 1'bz) && MIREPLAYRAMREADDATA_delay[81]; // rv 0 + assign MIREPLAYRAMREADDATA_in[82] = (MIREPLAYRAMREADDATA[82] !== 1'bz) && MIREPLAYRAMREADDATA_delay[82]; // rv 0 + assign MIREPLAYRAMREADDATA_in[83] = (MIREPLAYRAMREADDATA[83] !== 1'bz) && MIREPLAYRAMREADDATA_delay[83]; // rv 0 + assign MIREPLAYRAMREADDATA_in[84] = (MIREPLAYRAMREADDATA[84] !== 1'bz) && MIREPLAYRAMREADDATA_delay[84]; // rv 0 + assign MIREPLAYRAMREADDATA_in[85] = (MIREPLAYRAMREADDATA[85] !== 1'bz) && MIREPLAYRAMREADDATA_delay[85]; // rv 0 + assign MIREPLAYRAMREADDATA_in[86] = (MIREPLAYRAMREADDATA[86] !== 1'bz) && MIREPLAYRAMREADDATA_delay[86]; // rv 0 + assign MIREPLAYRAMREADDATA_in[87] = (MIREPLAYRAMREADDATA[87] !== 1'bz) && MIREPLAYRAMREADDATA_delay[87]; // rv 0 + assign MIREPLAYRAMREADDATA_in[88] = (MIREPLAYRAMREADDATA[88] !== 1'bz) && MIREPLAYRAMREADDATA_delay[88]; // rv 0 + assign MIREPLAYRAMREADDATA_in[89] = (MIREPLAYRAMREADDATA[89] !== 1'bz) && MIREPLAYRAMREADDATA_delay[89]; // rv 0 + assign MIREPLAYRAMREADDATA_in[8] = (MIREPLAYRAMREADDATA[8] !== 1'bz) && MIREPLAYRAMREADDATA_delay[8]; // rv 0 + assign MIREPLAYRAMREADDATA_in[90] = (MIREPLAYRAMREADDATA[90] !== 1'bz) && MIREPLAYRAMREADDATA_delay[90]; // rv 0 + assign MIREPLAYRAMREADDATA_in[91] = (MIREPLAYRAMREADDATA[91] !== 1'bz) && MIREPLAYRAMREADDATA_delay[91]; // rv 0 + assign MIREPLAYRAMREADDATA_in[92] = (MIREPLAYRAMREADDATA[92] !== 1'bz) && MIREPLAYRAMREADDATA_delay[92]; // rv 0 + assign MIREPLAYRAMREADDATA_in[93] = (MIREPLAYRAMREADDATA[93] !== 1'bz) && MIREPLAYRAMREADDATA_delay[93]; // rv 0 + assign MIREPLAYRAMREADDATA_in[94] = (MIREPLAYRAMREADDATA[94] !== 1'bz) && MIREPLAYRAMREADDATA_delay[94]; // rv 0 + assign MIREPLAYRAMREADDATA_in[95] = (MIREPLAYRAMREADDATA[95] !== 1'bz) && MIREPLAYRAMREADDATA_delay[95]; // rv 0 + assign MIREPLAYRAMREADDATA_in[96] = (MIREPLAYRAMREADDATA[96] !== 1'bz) && MIREPLAYRAMREADDATA_delay[96]; // rv 0 + assign MIREPLAYRAMREADDATA_in[97] = (MIREPLAYRAMREADDATA[97] !== 1'bz) && MIREPLAYRAMREADDATA_delay[97]; // rv 0 + assign MIREPLAYRAMREADDATA_in[98] = (MIREPLAYRAMREADDATA[98] !== 1'bz) && MIREPLAYRAMREADDATA_delay[98]; // rv 0 + assign MIREPLAYRAMREADDATA_in[99] = (MIREPLAYRAMREADDATA[99] !== 1'bz) && MIREPLAYRAMREADDATA_delay[99]; // rv 0 + assign MIREPLAYRAMREADDATA_in[9] = (MIREPLAYRAMREADDATA[9] !== 1'bz) && MIREPLAYRAMREADDATA_delay[9]; // rv 0 + assign MIREQUESTRAMREADDATA_in[0] = (MIREQUESTRAMREADDATA[0] !== 1'bz) && MIREQUESTRAMREADDATA_delay[0]; // rv 0 + assign MIREQUESTRAMREADDATA_in[100] = (MIREQUESTRAMREADDATA[100] !== 1'bz) && MIREQUESTRAMREADDATA_delay[100]; // rv 0 + assign MIREQUESTRAMREADDATA_in[101] = (MIREQUESTRAMREADDATA[101] !== 1'bz) && MIREQUESTRAMREADDATA_delay[101]; // rv 0 + assign MIREQUESTRAMREADDATA_in[102] = (MIREQUESTRAMREADDATA[102] !== 1'bz) && MIREQUESTRAMREADDATA_delay[102]; // rv 0 + assign MIREQUESTRAMREADDATA_in[103] = (MIREQUESTRAMREADDATA[103] !== 1'bz) && MIREQUESTRAMREADDATA_delay[103]; // rv 0 + assign MIREQUESTRAMREADDATA_in[104] = (MIREQUESTRAMREADDATA[104] !== 1'bz) && MIREQUESTRAMREADDATA_delay[104]; // rv 0 + assign MIREQUESTRAMREADDATA_in[105] = (MIREQUESTRAMREADDATA[105] !== 1'bz) && MIREQUESTRAMREADDATA_delay[105]; // rv 0 + assign MIREQUESTRAMREADDATA_in[106] = (MIREQUESTRAMREADDATA[106] !== 1'bz) && MIREQUESTRAMREADDATA_delay[106]; // rv 0 + assign MIREQUESTRAMREADDATA_in[107] = (MIREQUESTRAMREADDATA[107] !== 1'bz) && MIREQUESTRAMREADDATA_delay[107]; // rv 0 + assign MIREQUESTRAMREADDATA_in[108] = (MIREQUESTRAMREADDATA[108] !== 1'bz) && MIREQUESTRAMREADDATA_delay[108]; // rv 0 + assign MIREQUESTRAMREADDATA_in[109] = (MIREQUESTRAMREADDATA[109] !== 1'bz) && MIREQUESTRAMREADDATA_delay[109]; // rv 0 + assign MIREQUESTRAMREADDATA_in[10] = (MIREQUESTRAMREADDATA[10] !== 1'bz) && MIREQUESTRAMREADDATA_delay[10]; // rv 0 + assign MIREQUESTRAMREADDATA_in[110] = (MIREQUESTRAMREADDATA[110] !== 1'bz) && MIREQUESTRAMREADDATA_delay[110]; // rv 0 + assign MIREQUESTRAMREADDATA_in[111] = (MIREQUESTRAMREADDATA[111] !== 1'bz) && MIREQUESTRAMREADDATA_delay[111]; // rv 0 + assign MIREQUESTRAMREADDATA_in[112] = (MIREQUESTRAMREADDATA[112] !== 1'bz) && MIREQUESTRAMREADDATA_delay[112]; // rv 0 + assign MIREQUESTRAMREADDATA_in[113] = (MIREQUESTRAMREADDATA[113] !== 1'bz) && MIREQUESTRAMREADDATA_delay[113]; // rv 0 + assign MIREQUESTRAMREADDATA_in[114] = (MIREQUESTRAMREADDATA[114] !== 1'bz) && MIREQUESTRAMREADDATA_delay[114]; // rv 0 + assign MIREQUESTRAMREADDATA_in[115] = (MIREQUESTRAMREADDATA[115] !== 1'bz) && MIREQUESTRAMREADDATA_delay[115]; // rv 0 + assign MIREQUESTRAMREADDATA_in[116] = (MIREQUESTRAMREADDATA[116] !== 1'bz) && MIREQUESTRAMREADDATA_delay[116]; // rv 0 + assign MIREQUESTRAMREADDATA_in[117] = (MIREQUESTRAMREADDATA[117] !== 1'bz) && MIREQUESTRAMREADDATA_delay[117]; // rv 0 + assign MIREQUESTRAMREADDATA_in[118] = (MIREQUESTRAMREADDATA[118] !== 1'bz) && MIREQUESTRAMREADDATA_delay[118]; // rv 0 + assign MIREQUESTRAMREADDATA_in[119] = (MIREQUESTRAMREADDATA[119] !== 1'bz) && MIREQUESTRAMREADDATA_delay[119]; // rv 0 + assign MIREQUESTRAMREADDATA_in[11] = (MIREQUESTRAMREADDATA[11] !== 1'bz) && MIREQUESTRAMREADDATA_delay[11]; // rv 0 + assign MIREQUESTRAMREADDATA_in[120] = (MIREQUESTRAMREADDATA[120] !== 1'bz) && MIREQUESTRAMREADDATA_delay[120]; // rv 0 + assign MIREQUESTRAMREADDATA_in[121] = (MIREQUESTRAMREADDATA[121] !== 1'bz) && MIREQUESTRAMREADDATA_delay[121]; // rv 0 + assign MIREQUESTRAMREADDATA_in[122] = (MIREQUESTRAMREADDATA[122] !== 1'bz) && MIREQUESTRAMREADDATA_delay[122]; // rv 0 + assign MIREQUESTRAMREADDATA_in[123] = (MIREQUESTRAMREADDATA[123] !== 1'bz) && MIREQUESTRAMREADDATA_delay[123]; // rv 0 + assign MIREQUESTRAMREADDATA_in[124] = (MIREQUESTRAMREADDATA[124] !== 1'bz) && MIREQUESTRAMREADDATA_delay[124]; // rv 0 + assign MIREQUESTRAMREADDATA_in[125] = (MIREQUESTRAMREADDATA[125] !== 1'bz) && MIREQUESTRAMREADDATA_delay[125]; // rv 0 + assign MIREQUESTRAMREADDATA_in[126] = (MIREQUESTRAMREADDATA[126] !== 1'bz) && MIREQUESTRAMREADDATA_delay[126]; // rv 0 + assign MIREQUESTRAMREADDATA_in[127] = (MIREQUESTRAMREADDATA[127] !== 1'bz) && MIREQUESTRAMREADDATA_delay[127]; // rv 0 + assign MIREQUESTRAMREADDATA_in[128] = (MIREQUESTRAMREADDATA[128] !== 1'bz) && MIREQUESTRAMREADDATA_delay[128]; // rv 0 + assign MIREQUESTRAMREADDATA_in[129] = (MIREQUESTRAMREADDATA[129] !== 1'bz) && MIREQUESTRAMREADDATA_delay[129]; // rv 0 + assign MIREQUESTRAMREADDATA_in[12] = (MIREQUESTRAMREADDATA[12] !== 1'bz) && MIREQUESTRAMREADDATA_delay[12]; // rv 0 + assign MIREQUESTRAMREADDATA_in[130] = (MIREQUESTRAMREADDATA[130] !== 1'bz) && MIREQUESTRAMREADDATA_delay[130]; // rv 0 + assign MIREQUESTRAMREADDATA_in[131] = (MIREQUESTRAMREADDATA[131] !== 1'bz) && MIREQUESTRAMREADDATA_delay[131]; // rv 0 + assign MIREQUESTRAMREADDATA_in[132] = (MIREQUESTRAMREADDATA[132] !== 1'bz) && MIREQUESTRAMREADDATA_delay[132]; // rv 0 + assign MIREQUESTRAMREADDATA_in[133] = (MIREQUESTRAMREADDATA[133] !== 1'bz) && MIREQUESTRAMREADDATA_delay[133]; // rv 0 + assign MIREQUESTRAMREADDATA_in[134] = (MIREQUESTRAMREADDATA[134] !== 1'bz) && MIREQUESTRAMREADDATA_delay[134]; // rv 0 + assign MIREQUESTRAMREADDATA_in[135] = (MIREQUESTRAMREADDATA[135] !== 1'bz) && MIREQUESTRAMREADDATA_delay[135]; // rv 0 + assign MIREQUESTRAMREADDATA_in[136] = (MIREQUESTRAMREADDATA[136] !== 1'bz) && MIREQUESTRAMREADDATA_delay[136]; // rv 0 + assign MIREQUESTRAMREADDATA_in[137] = (MIREQUESTRAMREADDATA[137] !== 1'bz) && MIREQUESTRAMREADDATA_delay[137]; // rv 0 + assign MIREQUESTRAMREADDATA_in[138] = (MIREQUESTRAMREADDATA[138] !== 1'bz) && MIREQUESTRAMREADDATA_delay[138]; // rv 0 + assign MIREQUESTRAMREADDATA_in[139] = (MIREQUESTRAMREADDATA[139] !== 1'bz) && MIREQUESTRAMREADDATA_delay[139]; // rv 0 + assign MIREQUESTRAMREADDATA_in[13] = (MIREQUESTRAMREADDATA[13] !== 1'bz) && MIREQUESTRAMREADDATA_delay[13]; // rv 0 + assign MIREQUESTRAMREADDATA_in[140] = (MIREQUESTRAMREADDATA[140] !== 1'bz) && MIREQUESTRAMREADDATA_delay[140]; // rv 0 + assign MIREQUESTRAMREADDATA_in[141] = (MIREQUESTRAMREADDATA[141] !== 1'bz) && MIREQUESTRAMREADDATA_delay[141]; // rv 0 + assign MIREQUESTRAMREADDATA_in[142] = (MIREQUESTRAMREADDATA[142] !== 1'bz) && MIREQUESTRAMREADDATA_delay[142]; // rv 0 + assign MIREQUESTRAMREADDATA_in[143] = (MIREQUESTRAMREADDATA[143] !== 1'bz) && MIREQUESTRAMREADDATA_delay[143]; // rv 0 + assign MIREQUESTRAMREADDATA_in[14] = (MIREQUESTRAMREADDATA[14] !== 1'bz) && MIREQUESTRAMREADDATA_delay[14]; // rv 0 + assign MIREQUESTRAMREADDATA_in[15] = (MIREQUESTRAMREADDATA[15] !== 1'bz) && MIREQUESTRAMREADDATA_delay[15]; // rv 0 + assign MIREQUESTRAMREADDATA_in[16] = (MIREQUESTRAMREADDATA[16] !== 1'bz) && MIREQUESTRAMREADDATA_delay[16]; // rv 0 + assign MIREQUESTRAMREADDATA_in[17] = (MIREQUESTRAMREADDATA[17] !== 1'bz) && MIREQUESTRAMREADDATA_delay[17]; // rv 0 + assign MIREQUESTRAMREADDATA_in[18] = (MIREQUESTRAMREADDATA[18] !== 1'bz) && MIREQUESTRAMREADDATA_delay[18]; // rv 0 + assign MIREQUESTRAMREADDATA_in[19] = (MIREQUESTRAMREADDATA[19] !== 1'bz) && MIREQUESTRAMREADDATA_delay[19]; // rv 0 + assign MIREQUESTRAMREADDATA_in[1] = (MIREQUESTRAMREADDATA[1] !== 1'bz) && MIREQUESTRAMREADDATA_delay[1]; // rv 0 + assign MIREQUESTRAMREADDATA_in[20] = (MIREQUESTRAMREADDATA[20] !== 1'bz) && MIREQUESTRAMREADDATA_delay[20]; // rv 0 + assign MIREQUESTRAMREADDATA_in[21] = (MIREQUESTRAMREADDATA[21] !== 1'bz) && MIREQUESTRAMREADDATA_delay[21]; // rv 0 + assign MIREQUESTRAMREADDATA_in[22] = (MIREQUESTRAMREADDATA[22] !== 1'bz) && MIREQUESTRAMREADDATA_delay[22]; // rv 0 + assign MIREQUESTRAMREADDATA_in[23] = (MIREQUESTRAMREADDATA[23] !== 1'bz) && MIREQUESTRAMREADDATA_delay[23]; // rv 0 + assign MIREQUESTRAMREADDATA_in[24] = (MIREQUESTRAMREADDATA[24] !== 1'bz) && MIREQUESTRAMREADDATA_delay[24]; // rv 0 + assign MIREQUESTRAMREADDATA_in[25] = (MIREQUESTRAMREADDATA[25] !== 1'bz) && MIREQUESTRAMREADDATA_delay[25]; // rv 0 + assign MIREQUESTRAMREADDATA_in[26] = (MIREQUESTRAMREADDATA[26] !== 1'bz) && MIREQUESTRAMREADDATA_delay[26]; // rv 0 + assign MIREQUESTRAMREADDATA_in[27] = (MIREQUESTRAMREADDATA[27] !== 1'bz) && MIREQUESTRAMREADDATA_delay[27]; // rv 0 + assign MIREQUESTRAMREADDATA_in[28] = (MIREQUESTRAMREADDATA[28] !== 1'bz) && MIREQUESTRAMREADDATA_delay[28]; // rv 0 + assign MIREQUESTRAMREADDATA_in[29] = (MIREQUESTRAMREADDATA[29] !== 1'bz) && MIREQUESTRAMREADDATA_delay[29]; // rv 0 + assign MIREQUESTRAMREADDATA_in[2] = (MIREQUESTRAMREADDATA[2] !== 1'bz) && MIREQUESTRAMREADDATA_delay[2]; // rv 0 + assign MIREQUESTRAMREADDATA_in[30] = (MIREQUESTRAMREADDATA[30] !== 1'bz) && MIREQUESTRAMREADDATA_delay[30]; // rv 0 + assign MIREQUESTRAMREADDATA_in[31] = (MIREQUESTRAMREADDATA[31] !== 1'bz) && MIREQUESTRAMREADDATA_delay[31]; // rv 0 + assign MIREQUESTRAMREADDATA_in[32] = (MIREQUESTRAMREADDATA[32] !== 1'bz) && MIREQUESTRAMREADDATA_delay[32]; // rv 0 + assign MIREQUESTRAMREADDATA_in[33] = (MIREQUESTRAMREADDATA[33] !== 1'bz) && MIREQUESTRAMREADDATA_delay[33]; // rv 0 + assign MIREQUESTRAMREADDATA_in[34] = (MIREQUESTRAMREADDATA[34] !== 1'bz) && MIREQUESTRAMREADDATA_delay[34]; // rv 0 + assign MIREQUESTRAMREADDATA_in[35] = (MIREQUESTRAMREADDATA[35] !== 1'bz) && MIREQUESTRAMREADDATA_delay[35]; // rv 0 + assign MIREQUESTRAMREADDATA_in[36] = (MIREQUESTRAMREADDATA[36] !== 1'bz) && MIREQUESTRAMREADDATA_delay[36]; // rv 0 + assign MIREQUESTRAMREADDATA_in[37] = (MIREQUESTRAMREADDATA[37] !== 1'bz) && MIREQUESTRAMREADDATA_delay[37]; // rv 0 + assign MIREQUESTRAMREADDATA_in[38] = (MIREQUESTRAMREADDATA[38] !== 1'bz) && MIREQUESTRAMREADDATA_delay[38]; // rv 0 + assign MIREQUESTRAMREADDATA_in[39] = (MIREQUESTRAMREADDATA[39] !== 1'bz) && MIREQUESTRAMREADDATA_delay[39]; // rv 0 + assign MIREQUESTRAMREADDATA_in[3] = (MIREQUESTRAMREADDATA[3] !== 1'bz) && MIREQUESTRAMREADDATA_delay[3]; // rv 0 + assign MIREQUESTRAMREADDATA_in[40] = (MIREQUESTRAMREADDATA[40] !== 1'bz) && MIREQUESTRAMREADDATA_delay[40]; // rv 0 + assign MIREQUESTRAMREADDATA_in[41] = (MIREQUESTRAMREADDATA[41] !== 1'bz) && MIREQUESTRAMREADDATA_delay[41]; // rv 0 + assign MIREQUESTRAMREADDATA_in[42] = (MIREQUESTRAMREADDATA[42] !== 1'bz) && MIREQUESTRAMREADDATA_delay[42]; // rv 0 + assign MIREQUESTRAMREADDATA_in[43] = (MIREQUESTRAMREADDATA[43] !== 1'bz) && MIREQUESTRAMREADDATA_delay[43]; // rv 0 + assign MIREQUESTRAMREADDATA_in[44] = (MIREQUESTRAMREADDATA[44] !== 1'bz) && MIREQUESTRAMREADDATA_delay[44]; // rv 0 + assign MIREQUESTRAMREADDATA_in[45] = (MIREQUESTRAMREADDATA[45] !== 1'bz) && MIREQUESTRAMREADDATA_delay[45]; // rv 0 + assign MIREQUESTRAMREADDATA_in[46] = (MIREQUESTRAMREADDATA[46] !== 1'bz) && MIREQUESTRAMREADDATA_delay[46]; // rv 0 + assign MIREQUESTRAMREADDATA_in[47] = (MIREQUESTRAMREADDATA[47] !== 1'bz) && MIREQUESTRAMREADDATA_delay[47]; // rv 0 + assign MIREQUESTRAMREADDATA_in[48] = (MIREQUESTRAMREADDATA[48] !== 1'bz) && MIREQUESTRAMREADDATA_delay[48]; // rv 0 + assign MIREQUESTRAMREADDATA_in[49] = (MIREQUESTRAMREADDATA[49] !== 1'bz) && MIREQUESTRAMREADDATA_delay[49]; // rv 0 + assign MIREQUESTRAMREADDATA_in[4] = (MIREQUESTRAMREADDATA[4] !== 1'bz) && MIREQUESTRAMREADDATA_delay[4]; // rv 0 + assign MIREQUESTRAMREADDATA_in[50] = (MIREQUESTRAMREADDATA[50] !== 1'bz) && MIREQUESTRAMREADDATA_delay[50]; // rv 0 + assign MIREQUESTRAMREADDATA_in[51] = (MIREQUESTRAMREADDATA[51] !== 1'bz) && MIREQUESTRAMREADDATA_delay[51]; // rv 0 + assign MIREQUESTRAMREADDATA_in[52] = (MIREQUESTRAMREADDATA[52] !== 1'bz) && MIREQUESTRAMREADDATA_delay[52]; // rv 0 + assign MIREQUESTRAMREADDATA_in[53] = (MIREQUESTRAMREADDATA[53] !== 1'bz) && MIREQUESTRAMREADDATA_delay[53]; // rv 0 + assign MIREQUESTRAMREADDATA_in[54] = (MIREQUESTRAMREADDATA[54] !== 1'bz) && MIREQUESTRAMREADDATA_delay[54]; // rv 0 + assign MIREQUESTRAMREADDATA_in[55] = (MIREQUESTRAMREADDATA[55] !== 1'bz) && MIREQUESTRAMREADDATA_delay[55]; // rv 0 + assign MIREQUESTRAMREADDATA_in[56] = (MIREQUESTRAMREADDATA[56] !== 1'bz) && MIREQUESTRAMREADDATA_delay[56]; // rv 0 + assign MIREQUESTRAMREADDATA_in[57] = (MIREQUESTRAMREADDATA[57] !== 1'bz) && MIREQUESTRAMREADDATA_delay[57]; // rv 0 + assign MIREQUESTRAMREADDATA_in[58] = (MIREQUESTRAMREADDATA[58] !== 1'bz) && MIREQUESTRAMREADDATA_delay[58]; // rv 0 + assign MIREQUESTRAMREADDATA_in[59] = (MIREQUESTRAMREADDATA[59] !== 1'bz) && MIREQUESTRAMREADDATA_delay[59]; // rv 0 + assign MIREQUESTRAMREADDATA_in[5] = (MIREQUESTRAMREADDATA[5] !== 1'bz) && MIREQUESTRAMREADDATA_delay[5]; // rv 0 + assign MIREQUESTRAMREADDATA_in[60] = (MIREQUESTRAMREADDATA[60] !== 1'bz) && MIREQUESTRAMREADDATA_delay[60]; // rv 0 + assign MIREQUESTRAMREADDATA_in[61] = (MIREQUESTRAMREADDATA[61] !== 1'bz) && MIREQUESTRAMREADDATA_delay[61]; // rv 0 + assign MIREQUESTRAMREADDATA_in[62] = (MIREQUESTRAMREADDATA[62] !== 1'bz) && MIREQUESTRAMREADDATA_delay[62]; // rv 0 + assign MIREQUESTRAMREADDATA_in[63] = (MIREQUESTRAMREADDATA[63] !== 1'bz) && MIREQUESTRAMREADDATA_delay[63]; // rv 0 + assign MIREQUESTRAMREADDATA_in[64] = (MIREQUESTRAMREADDATA[64] !== 1'bz) && MIREQUESTRAMREADDATA_delay[64]; // rv 0 + assign MIREQUESTRAMREADDATA_in[65] = (MIREQUESTRAMREADDATA[65] !== 1'bz) && MIREQUESTRAMREADDATA_delay[65]; // rv 0 + assign MIREQUESTRAMREADDATA_in[66] = (MIREQUESTRAMREADDATA[66] !== 1'bz) && MIREQUESTRAMREADDATA_delay[66]; // rv 0 + assign MIREQUESTRAMREADDATA_in[67] = (MIREQUESTRAMREADDATA[67] !== 1'bz) && MIREQUESTRAMREADDATA_delay[67]; // rv 0 + assign MIREQUESTRAMREADDATA_in[68] = (MIREQUESTRAMREADDATA[68] !== 1'bz) && MIREQUESTRAMREADDATA_delay[68]; // rv 0 + assign MIREQUESTRAMREADDATA_in[69] = (MIREQUESTRAMREADDATA[69] !== 1'bz) && MIREQUESTRAMREADDATA_delay[69]; // rv 0 + assign MIREQUESTRAMREADDATA_in[6] = (MIREQUESTRAMREADDATA[6] !== 1'bz) && MIREQUESTRAMREADDATA_delay[6]; // rv 0 + assign MIREQUESTRAMREADDATA_in[70] = (MIREQUESTRAMREADDATA[70] !== 1'bz) && MIREQUESTRAMREADDATA_delay[70]; // rv 0 + assign MIREQUESTRAMREADDATA_in[71] = (MIREQUESTRAMREADDATA[71] !== 1'bz) && MIREQUESTRAMREADDATA_delay[71]; // rv 0 + assign MIREQUESTRAMREADDATA_in[72] = (MIREQUESTRAMREADDATA[72] !== 1'bz) && MIREQUESTRAMREADDATA_delay[72]; // rv 0 + assign MIREQUESTRAMREADDATA_in[73] = (MIREQUESTRAMREADDATA[73] !== 1'bz) && MIREQUESTRAMREADDATA_delay[73]; // rv 0 + assign MIREQUESTRAMREADDATA_in[74] = (MIREQUESTRAMREADDATA[74] !== 1'bz) && MIREQUESTRAMREADDATA_delay[74]; // rv 0 + assign MIREQUESTRAMREADDATA_in[75] = (MIREQUESTRAMREADDATA[75] !== 1'bz) && MIREQUESTRAMREADDATA_delay[75]; // rv 0 + assign MIREQUESTRAMREADDATA_in[76] = (MIREQUESTRAMREADDATA[76] !== 1'bz) && MIREQUESTRAMREADDATA_delay[76]; // rv 0 + assign MIREQUESTRAMREADDATA_in[77] = (MIREQUESTRAMREADDATA[77] !== 1'bz) && MIREQUESTRAMREADDATA_delay[77]; // rv 0 + assign MIREQUESTRAMREADDATA_in[78] = (MIREQUESTRAMREADDATA[78] !== 1'bz) && MIREQUESTRAMREADDATA_delay[78]; // rv 0 + assign MIREQUESTRAMREADDATA_in[79] = (MIREQUESTRAMREADDATA[79] !== 1'bz) && MIREQUESTRAMREADDATA_delay[79]; // rv 0 + assign MIREQUESTRAMREADDATA_in[7] = (MIREQUESTRAMREADDATA[7] !== 1'bz) && MIREQUESTRAMREADDATA_delay[7]; // rv 0 + assign MIREQUESTRAMREADDATA_in[80] = (MIREQUESTRAMREADDATA[80] !== 1'bz) && MIREQUESTRAMREADDATA_delay[80]; // rv 0 + assign MIREQUESTRAMREADDATA_in[81] = (MIREQUESTRAMREADDATA[81] !== 1'bz) && MIREQUESTRAMREADDATA_delay[81]; // rv 0 + assign MIREQUESTRAMREADDATA_in[82] = (MIREQUESTRAMREADDATA[82] !== 1'bz) && MIREQUESTRAMREADDATA_delay[82]; // rv 0 + assign MIREQUESTRAMREADDATA_in[83] = (MIREQUESTRAMREADDATA[83] !== 1'bz) && MIREQUESTRAMREADDATA_delay[83]; // rv 0 + assign MIREQUESTRAMREADDATA_in[84] = (MIREQUESTRAMREADDATA[84] !== 1'bz) && MIREQUESTRAMREADDATA_delay[84]; // rv 0 + assign MIREQUESTRAMREADDATA_in[85] = (MIREQUESTRAMREADDATA[85] !== 1'bz) && MIREQUESTRAMREADDATA_delay[85]; // rv 0 + assign MIREQUESTRAMREADDATA_in[86] = (MIREQUESTRAMREADDATA[86] !== 1'bz) && MIREQUESTRAMREADDATA_delay[86]; // rv 0 + assign MIREQUESTRAMREADDATA_in[87] = (MIREQUESTRAMREADDATA[87] !== 1'bz) && MIREQUESTRAMREADDATA_delay[87]; // rv 0 + assign MIREQUESTRAMREADDATA_in[88] = (MIREQUESTRAMREADDATA[88] !== 1'bz) && MIREQUESTRAMREADDATA_delay[88]; // rv 0 + assign MIREQUESTRAMREADDATA_in[89] = (MIREQUESTRAMREADDATA[89] !== 1'bz) && MIREQUESTRAMREADDATA_delay[89]; // rv 0 + assign MIREQUESTRAMREADDATA_in[8] = (MIREQUESTRAMREADDATA[8] !== 1'bz) && MIREQUESTRAMREADDATA_delay[8]; // rv 0 + assign MIREQUESTRAMREADDATA_in[90] = (MIREQUESTRAMREADDATA[90] !== 1'bz) && MIREQUESTRAMREADDATA_delay[90]; // rv 0 + assign MIREQUESTRAMREADDATA_in[91] = (MIREQUESTRAMREADDATA[91] !== 1'bz) && MIREQUESTRAMREADDATA_delay[91]; // rv 0 + assign MIREQUESTRAMREADDATA_in[92] = (MIREQUESTRAMREADDATA[92] !== 1'bz) && MIREQUESTRAMREADDATA_delay[92]; // rv 0 + assign MIREQUESTRAMREADDATA_in[93] = (MIREQUESTRAMREADDATA[93] !== 1'bz) && MIREQUESTRAMREADDATA_delay[93]; // rv 0 + assign MIREQUESTRAMREADDATA_in[94] = (MIREQUESTRAMREADDATA[94] !== 1'bz) && MIREQUESTRAMREADDATA_delay[94]; // rv 0 + assign MIREQUESTRAMREADDATA_in[95] = (MIREQUESTRAMREADDATA[95] !== 1'bz) && MIREQUESTRAMREADDATA_delay[95]; // rv 0 + assign MIREQUESTRAMREADDATA_in[96] = (MIREQUESTRAMREADDATA[96] !== 1'bz) && MIREQUESTRAMREADDATA_delay[96]; // rv 0 + assign MIREQUESTRAMREADDATA_in[97] = (MIREQUESTRAMREADDATA[97] !== 1'bz) && MIREQUESTRAMREADDATA_delay[97]; // rv 0 + assign MIREQUESTRAMREADDATA_in[98] = (MIREQUESTRAMREADDATA[98] !== 1'bz) && MIREQUESTRAMREADDATA_delay[98]; // rv 0 + assign MIREQUESTRAMREADDATA_in[99] = (MIREQUESTRAMREADDATA[99] !== 1'bz) && MIREQUESTRAMREADDATA_delay[99]; // rv 0 + assign MIREQUESTRAMREADDATA_in[9] = (MIREQUESTRAMREADDATA[9] !== 1'bz) && MIREQUESTRAMREADDATA_delay[9]; // rv 0 + assign PCIECQNPREQ_in = (PCIECQNPREQ === 1'bz) || PCIECQNPREQ_delay; // rv 1 + assign PIPECLK_in = (PIPECLK !== 1'bz) && PIPECLK_delay; // rv 0 + assign PIPEEQFS_in[0] = (PIPEEQFS[0] !== 1'bz) && PIPEEQFS_delay[0]; // rv 0 + assign PIPEEQFS_in[1] = (PIPEEQFS[1] !== 1'bz) && PIPEEQFS_delay[1]; // rv 0 + assign PIPEEQFS_in[2] = (PIPEEQFS[2] !== 1'bz) && PIPEEQFS_delay[2]; // rv 0 + assign PIPEEQFS_in[3] = (PIPEEQFS[3] !== 1'bz) && PIPEEQFS_delay[3]; // rv 0 + assign PIPEEQFS_in[4] = (PIPEEQFS[4] !== 1'bz) && PIPEEQFS_delay[4]; // rv 0 + assign PIPEEQFS_in[5] = (PIPEEQFS[5] !== 1'bz) && PIPEEQFS_delay[5]; // rv 0 + assign PIPEEQLF_in[0] = (PIPEEQLF[0] !== 1'bz) && PIPEEQLF_delay[0]; // rv 0 + assign PIPEEQLF_in[1] = (PIPEEQLF[1] !== 1'bz) && PIPEEQLF_delay[1]; // rv 0 + assign PIPEEQLF_in[2] = (PIPEEQLF[2] !== 1'bz) && PIPEEQLF_delay[2]; // rv 0 + assign PIPEEQLF_in[3] = (PIPEEQLF[3] !== 1'bz) && PIPEEQLF_delay[3]; // rv 0 + assign PIPEEQLF_in[4] = (PIPEEQLF[4] !== 1'bz) && PIPEEQLF_delay[4]; // rv 0 + assign PIPEEQLF_in[5] = (PIPEEQLF[5] !== 1'bz) && PIPEEQLF_delay[5]; // rv 0 + assign PIPERESETN_in = (PIPERESETN !== 1'bz) && PIPERESETN_delay; // rv 0 + assign PIPERX0CHARISK_in[0] = (PIPERX0CHARISK[0] === 1'bz) || PIPERX0CHARISK_delay[0]; // rv 1 + assign PIPERX0CHARISK_in[1] = (PIPERX0CHARISK[1] === 1'bz) || PIPERX0CHARISK_delay[1]; // rv 1 + assign PIPERX0DATAVALID_in = (PIPERX0DATAVALID !== 1'bz) && PIPERX0DATAVALID_delay; // rv 0 + assign PIPERX0DATA_in[0] = (PIPERX0DATA[0] !== 1'bz) && PIPERX0DATA_delay[0]; // rv 0 + assign PIPERX0DATA_in[10] = (PIPERX0DATA[10] !== 1'bz) && PIPERX0DATA_delay[10]; // rv 0 + assign PIPERX0DATA_in[11] = (PIPERX0DATA[11] !== 1'bz) && PIPERX0DATA_delay[11]; // rv 0 + assign PIPERX0DATA_in[12] = (PIPERX0DATA[12] !== 1'bz) && PIPERX0DATA_delay[12]; // rv 0 + assign PIPERX0DATA_in[13] = (PIPERX0DATA[13] !== 1'bz) && PIPERX0DATA_delay[13]; // rv 0 + assign PIPERX0DATA_in[14] = (PIPERX0DATA[14] !== 1'bz) && PIPERX0DATA_delay[14]; // rv 0 + assign PIPERX0DATA_in[15] = (PIPERX0DATA[15] !== 1'bz) && PIPERX0DATA_delay[15]; // rv 0 + assign PIPERX0DATA_in[16] = (PIPERX0DATA[16] !== 1'bz) && PIPERX0DATA_delay[16]; // rv 0 + assign PIPERX0DATA_in[17] = (PIPERX0DATA[17] !== 1'bz) && PIPERX0DATA_delay[17]; // rv 0 + assign PIPERX0DATA_in[18] = (PIPERX0DATA[18] !== 1'bz) && PIPERX0DATA_delay[18]; // rv 0 + assign PIPERX0DATA_in[19] = (PIPERX0DATA[19] !== 1'bz) && PIPERX0DATA_delay[19]; // rv 0 + assign PIPERX0DATA_in[1] = (PIPERX0DATA[1] !== 1'bz) && PIPERX0DATA_delay[1]; // rv 0 + assign PIPERX0DATA_in[20] = (PIPERX0DATA[20] !== 1'bz) && PIPERX0DATA_delay[20]; // rv 0 + assign PIPERX0DATA_in[21] = (PIPERX0DATA[21] !== 1'bz) && PIPERX0DATA_delay[21]; // rv 0 + assign PIPERX0DATA_in[22] = (PIPERX0DATA[22] !== 1'bz) && PIPERX0DATA_delay[22]; // rv 0 + assign PIPERX0DATA_in[23] = (PIPERX0DATA[23] !== 1'bz) && PIPERX0DATA_delay[23]; // rv 0 + assign PIPERX0DATA_in[24] = (PIPERX0DATA[24] !== 1'bz) && PIPERX0DATA_delay[24]; // rv 0 + assign PIPERX0DATA_in[25] = (PIPERX0DATA[25] !== 1'bz) && PIPERX0DATA_delay[25]; // rv 0 + assign PIPERX0DATA_in[26] = (PIPERX0DATA[26] !== 1'bz) && PIPERX0DATA_delay[26]; // rv 0 + assign PIPERX0DATA_in[27] = (PIPERX0DATA[27] !== 1'bz) && PIPERX0DATA_delay[27]; // rv 0 + assign PIPERX0DATA_in[28] = (PIPERX0DATA[28] !== 1'bz) && PIPERX0DATA_delay[28]; // rv 0 + assign PIPERX0DATA_in[29] = (PIPERX0DATA[29] !== 1'bz) && PIPERX0DATA_delay[29]; // rv 0 + assign PIPERX0DATA_in[2] = (PIPERX0DATA[2] !== 1'bz) && PIPERX0DATA_delay[2]; // rv 0 + assign PIPERX0DATA_in[30] = (PIPERX0DATA[30] !== 1'bz) && PIPERX0DATA_delay[30]; // rv 0 + assign PIPERX0DATA_in[31] = (PIPERX0DATA[31] !== 1'bz) && PIPERX0DATA_delay[31]; // rv 0 + assign PIPERX0DATA_in[3] = (PIPERX0DATA[3] !== 1'bz) && PIPERX0DATA_delay[3]; // rv 0 + assign PIPERX0DATA_in[4] = (PIPERX0DATA[4] !== 1'bz) && PIPERX0DATA_delay[4]; // rv 0 + assign PIPERX0DATA_in[5] = (PIPERX0DATA[5] !== 1'bz) && PIPERX0DATA_delay[5]; // rv 0 + assign PIPERX0DATA_in[6] = (PIPERX0DATA[6] !== 1'bz) && PIPERX0DATA_delay[6]; // rv 0 + assign PIPERX0DATA_in[7] = (PIPERX0DATA[7] !== 1'bz) && PIPERX0DATA_delay[7]; // rv 0 + assign PIPERX0DATA_in[8] = (PIPERX0DATA[8] !== 1'bz) && PIPERX0DATA_delay[8]; // rv 0 + assign PIPERX0DATA_in[9] = (PIPERX0DATA[9] !== 1'bz) && PIPERX0DATA_delay[9]; // rv 0 + assign PIPERX0ELECIDLE_in = (PIPERX0ELECIDLE === 1'bz) || PIPERX0ELECIDLE_delay; // rv 1 + assign PIPERX0EQDONE_in = (PIPERX0EQDONE !== 1'bz) && PIPERX0EQDONE_delay; // rv 0 + assign PIPERX0EQLPADAPTDONE_in = (PIPERX0EQLPADAPTDONE !== 1'bz) && PIPERX0EQLPADAPTDONE_delay; // rv 0 + assign PIPERX0EQLPLFFSSEL_in = (PIPERX0EQLPLFFSSEL !== 1'bz) && PIPERX0EQLPLFFSSEL_delay; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX0EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX0EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX0EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX0EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX0EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX0EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX0EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX0EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX0EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX0EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX0EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX0EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX0EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX0EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX0EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX0EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX0EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX0EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX0EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX0EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX0PHYSTATUS_in = (PIPERX0PHYSTATUS === 1'bz) || PIPERX0PHYSTATUS_delay; // rv 1 + assign PIPERX0STARTBLOCK_in = (PIPERX0STARTBLOCK !== 1'bz) && PIPERX0STARTBLOCK_delay; // rv 0 + assign PIPERX0STATUS_in[0] = (PIPERX0STATUS[0] !== 1'bz) && PIPERX0STATUS_delay[0]; // rv 0 + assign PIPERX0STATUS_in[1] = (PIPERX0STATUS[1] !== 1'bz) && PIPERX0STATUS_delay[1]; // rv 0 + assign PIPERX0STATUS_in[2] = (PIPERX0STATUS[2] !== 1'bz) && PIPERX0STATUS_delay[2]; // rv 0 + assign PIPERX0SYNCHEADER_in[0] = (PIPERX0SYNCHEADER[0] !== 1'bz) && PIPERX0SYNCHEADER_delay[0]; // rv 0 + assign PIPERX0SYNCHEADER_in[1] = (PIPERX0SYNCHEADER[1] !== 1'bz) && PIPERX0SYNCHEADER_delay[1]; // rv 0 + assign PIPERX0VALID_in = (PIPERX0VALID !== 1'bz) && PIPERX0VALID_delay; // rv 0 + assign PIPERX1CHARISK_in[0] = (PIPERX1CHARISK[0] === 1'bz) || PIPERX1CHARISK_delay[0]; // rv 1 + assign PIPERX1CHARISK_in[1] = (PIPERX1CHARISK[1] === 1'bz) || PIPERX1CHARISK_delay[1]; // rv 1 + assign PIPERX1DATAVALID_in = (PIPERX1DATAVALID !== 1'bz) && PIPERX1DATAVALID_delay; // rv 0 + assign PIPERX1DATA_in[0] = (PIPERX1DATA[0] !== 1'bz) && PIPERX1DATA_delay[0]; // rv 0 + assign PIPERX1DATA_in[10] = (PIPERX1DATA[10] !== 1'bz) && PIPERX1DATA_delay[10]; // rv 0 + assign PIPERX1DATA_in[11] = (PIPERX1DATA[11] !== 1'bz) && PIPERX1DATA_delay[11]; // rv 0 + assign PIPERX1DATA_in[12] = (PIPERX1DATA[12] !== 1'bz) && PIPERX1DATA_delay[12]; // rv 0 + assign PIPERX1DATA_in[13] = (PIPERX1DATA[13] !== 1'bz) && PIPERX1DATA_delay[13]; // rv 0 + assign PIPERX1DATA_in[14] = (PIPERX1DATA[14] !== 1'bz) && PIPERX1DATA_delay[14]; // rv 0 + assign PIPERX1DATA_in[15] = (PIPERX1DATA[15] !== 1'bz) && PIPERX1DATA_delay[15]; // rv 0 + assign PIPERX1DATA_in[16] = (PIPERX1DATA[16] !== 1'bz) && PIPERX1DATA_delay[16]; // rv 0 + assign PIPERX1DATA_in[17] = (PIPERX1DATA[17] !== 1'bz) && PIPERX1DATA_delay[17]; // rv 0 + assign PIPERX1DATA_in[18] = (PIPERX1DATA[18] !== 1'bz) && PIPERX1DATA_delay[18]; // rv 0 + assign PIPERX1DATA_in[19] = (PIPERX1DATA[19] !== 1'bz) && PIPERX1DATA_delay[19]; // rv 0 + assign PIPERX1DATA_in[1] = (PIPERX1DATA[1] !== 1'bz) && PIPERX1DATA_delay[1]; // rv 0 + assign PIPERX1DATA_in[20] = (PIPERX1DATA[20] !== 1'bz) && PIPERX1DATA_delay[20]; // rv 0 + assign PIPERX1DATA_in[21] = (PIPERX1DATA[21] !== 1'bz) && PIPERX1DATA_delay[21]; // rv 0 + assign PIPERX1DATA_in[22] = (PIPERX1DATA[22] !== 1'bz) && PIPERX1DATA_delay[22]; // rv 0 + assign PIPERX1DATA_in[23] = (PIPERX1DATA[23] !== 1'bz) && PIPERX1DATA_delay[23]; // rv 0 + assign PIPERX1DATA_in[24] = (PIPERX1DATA[24] !== 1'bz) && PIPERX1DATA_delay[24]; // rv 0 + assign PIPERX1DATA_in[25] = (PIPERX1DATA[25] !== 1'bz) && PIPERX1DATA_delay[25]; // rv 0 + assign PIPERX1DATA_in[26] = (PIPERX1DATA[26] !== 1'bz) && PIPERX1DATA_delay[26]; // rv 0 + assign PIPERX1DATA_in[27] = (PIPERX1DATA[27] !== 1'bz) && PIPERX1DATA_delay[27]; // rv 0 + assign PIPERX1DATA_in[28] = (PIPERX1DATA[28] !== 1'bz) && PIPERX1DATA_delay[28]; // rv 0 + assign PIPERX1DATA_in[29] = (PIPERX1DATA[29] !== 1'bz) && PIPERX1DATA_delay[29]; // rv 0 + assign PIPERX1DATA_in[2] = (PIPERX1DATA[2] !== 1'bz) && PIPERX1DATA_delay[2]; // rv 0 + assign PIPERX1DATA_in[30] = (PIPERX1DATA[30] !== 1'bz) && PIPERX1DATA_delay[30]; // rv 0 + assign PIPERX1DATA_in[31] = (PIPERX1DATA[31] !== 1'bz) && PIPERX1DATA_delay[31]; // rv 0 + assign PIPERX1DATA_in[3] = (PIPERX1DATA[3] !== 1'bz) && PIPERX1DATA_delay[3]; // rv 0 + assign PIPERX1DATA_in[4] = (PIPERX1DATA[4] !== 1'bz) && PIPERX1DATA_delay[4]; // rv 0 + assign PIPERX1DATA_in[5] = (PIPERX1DATA[5] !== 1'bz) && PIPERX1DATA_delay[5]; // rv 0 + assign PIPERX1DATA_in[6] = (PIPERX1DATA[6] !== 1'bz) && PIPERX1DATA_delay[6]; // rv 0 + assign PIPERX1DATA_in[7] = (PIPERX1DATA[7] !== 1'bz) && PIPERX1DATA_delay[7]; // rv 0 + assign PIPERX1DATA_in[8] = (PIPERX1DATA[8] !== 1'bz) && PIPERX1DATA_delay[8]; // rv 0 + assign PIPERX1DATA_in[9] = (PIPERX1DATA[9] !== 1'bz) && PIPERX1DATA_delay[9]; // rv 0 + assign PIPERX1ELECIDLE_in = (PIPERX1ELECIDLE === 1'bz) || PIPERX1ELECIDLE_delay; // rv 1 + assign PIPERX1EQDONE_in = (PIPERX1EQDONE !== 1'bz) && PIPERX1EQDONE_delay; // rv 0 + assign PIPERX1EQLPADAPTDONE_in = (PIPERX1EQLPADAPTDONE !== 1'bz) && PIPERX1EQLPADAPTDONE_delay; // rv 0 + assign PIPERX1EQLPLFFSSEL_in = (PIPERX1EQLPLFFSSEL !== 1'bz) && PIPERX1EQLPLFFSSEL_delay; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX1EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX1EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX1EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX1EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX1EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX1EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX1EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX1EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX1EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX1EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX1EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX1EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX1EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX1EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX1EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX1EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX1EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX1EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX1EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX1EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX1PHYSTATUS_in = (PIPERX1PHYSTATUS === 1'bz) || PIPERX1PHYSTATUS_delay; // rv 1 + assign PIPERX1STARTBLOCK_in = (PIPERX1STARTBLOCK !== 1'bz) && PIPERX1STARTBLOCK_delay; // rv 0 + assign PIPERX1STATUS_in[0] = (PIPERX1STATUS[0] !== 1'bz) && PIPERX1STATUS_delay[0]; // rv 0 + assign PIPERX1STATUS_in[1] = (PIPERX1STATUS[1] !== 1'bz) && PIPERX1STATUS_delay[1]; // rv 0 + assign PIPERX1STATUS_in[2] = (PIPERX1STATUS[2] !== 1'bz) && PIPERX1STATUS_delay[2]; // rv 0 + assign PIPERX1SYNCHEADER_in[0] = (PIPERX1SYNCHEADER[0] !== 1'bz) && PIPERX1SYNCHEADER_delay[0]; // rv 0 + assign PIPERX1SYNCHEADER_in[1] = (PIPERX1SYNCHEADER[1] !== 1'bz) && PIPERX1SYNCHEADER_delay[1]; // rv 0 + assign PIPERX1VALID_in = (PIPERX1VALID !== 1'bz) && PIPERX1VALID_delay; // rv 0 + assign PIPERX2CHARISK_in[0] = (PIPERX2CHARISK[0] === 1'bz) || PIPERX2CHARISK_delay[0]; // rv 1 + assign PIPERX2CHARISK_in[1] = (PIPERX2CHARISK[1] === 1'bz) || PIPERX2CHARISK_delay[1]; // rv 1 + assign PIPERX2DATAVALID_in = (PIPERX2DATAVALID !== 1'bz) && PIPERX2DATAVALID_delay; // rv 0 + assign PIPERX2DATA_in[0] = (PIPERX2DATA[0] !== 1'bz) && PIPERX2DATA_delay[0]; // rv 0 + assign PIPERX2DATA_in[10] = (PIPERX2DATA[10] !== 1'bz) && PIPERX2DATA_delay[10]; // rv 0 + assign PIPERX2DATA_in[11] = (PIPERX2DATA[11] !== 1'bz) && PIPERX2DATA_delay[11]; // rv 0 + assign PIPERX2DATA_in[12] = (PIPERX2DATA[12] !== 1'bz) && PIPERX2DATA_delay[12]; // rv 0 + assign PIPERX2DATA_in[13] = (PIPERX2DATA[13] !== 1'bz) && PIPERX2DATA_delay[13]; // rv 0 + assign PIPERX2DATA_in[14] = (PIPERX2DATA[14] !== 1'bz) && PIPERX2DATA_delay[14]; // rv 0 + assign PIPERX2DATA_in[15] = (PIPERX2DATA[15] !== 1'bz) && PIPERX2DATA_delay[15]; // rv 0 + assign PIPERX2DATA_in[16] = (PIPERX2DATA[16] !== 1'bz) && PIPERX2DATA_delay[16]; // rv 0 + assign PIPERX2DATA_in[17] = (PIPERX2DATA[17] !== 1'bz) && PIPERX2DATA_delay[17]; // rv 0 + assign PIPERX2DATA_in[18] = (PIPERX2DATA[18] !== 1'bz) && PIPERX2DATA_delay[18]; // rv 0 + assign PIPERX2DATA_in[19] = (PIPERX2DATA[19] !== 1'bz) && PIPERX2DATA_delay[19]; // rv 0 + assign PIPERX2DATA_in[1] = (PIPERX2DATA[1] !== 1'bz) && PIPERX2DATA_delay[1]; // rv 0 + assign PIPERX2DATA_in[20] = (PIPERX2DATA[20] !== 1'bz) && PIPERX2DATA_delay[20]; // rv 0 + assign PIPERX2DATA_in[21] = (PIPERX2DATA[21] !== 1'bz) && PIPERX2DATA_delay[21]; // rv 0 + assign PIPERX2DATA_in[22] = (PIPERX2DATA[22] !== 1'bz) && PIPERX2DATA_delay[22]; // rv 0 + assign PIPERX2DATA_in[23] = (PIPERX2DATA[23] !== 1'bz) && PIPERX2DATA_delay[23]; // rv 0 + assign PIPERX2DATA_in[24] = (PIPERX2DATA[24] !== 1'bz) && PIPERX2DATA_delay[24]; // rv 0 + assign PIPERX2DATA_in[25] = (PIPERX2DATA[25] !== 1'bz) && PIPERX2DATA_delay[25]; // rv 0 + assign PIPERX2DATA_in[26] = (PIPERX2DATA[26] !== 1'bz) && PIPERX2DATA_delay[26]; // rv 0 + assign PIPERX2DATA_in[27] = (PIPERX2DATA[27] !== 1'bz) && PIPERX2DATA_delay[27]; // rv 0 + assign PIPERX2DATA_in[28] = (PIPERX2DATA[28] !== 1'bz) && PIPERX2DATA_delay[28]; // rv 0 + assign PIPERX2DATA_in[29] = (PIPERX2DATA[29] !== 1'bz) && PIPERX2DATA_delay[29]; // rv 0 + assign PIPERX2DATA_in[2] = (PIPERX2DATA[2] !== 1'bz) && PIPERX2DATA_delay[2]; // rv 0 + assign PIPERX2DATA_in[30] = (PIPERX2DATA[30] !== 1'bz) && PIPERX2DATA_delay[30]; // rv 0 + assign PIPERX2DATA_in[31] = (PIPERX2DATA[31] !== 1'bz) && PIPERX2DATA_delay[31]; // rv 0 + assign PIPERX2DATA_in[3] = (PIPERX2DATA[3] !== 1'bz) && PIPERX2DATA_delay[3]; // rv 0 + assign PIPERX2DATA_in[4] = (PIPERX2DATA[4] !== 1'bz) && PIPERX2DATA_delay[4]; // rv 0 + assign PIPERX2DATA_in[5] = (PIPERX2DATA[5] !== 1'bz) && PIPERX2DATA_delay[5]; // rv 0 + assign PIPERX2DATA_in[6] = (PIPERX2DATA[6] !== 1'bz) && PIPERX2DATA_delay[6]; // rv 0 + assign PIPERX2DATA_in[7] = (PIPERX2DATA[7] !== 1'bz) && PIPERX2DATA_delay[7]; // rv 0 + assign PIPERX2DATA_in[8] = (PIPERX2DATA[8] !== 1'bz) && PIPERX2DATA_delay[8]; // rv 0 + assign PIPERX2DATA_in[9] = (PIPERX2DATA[9] !== 1'bz) && PIPERX2DATA_delay[9]; // rv 0 + assign PIPERX2ELECIDLE_in = (PIPERX2ELECIDLE === 1'bz) || PIPERX2ELECIDLE_delay; // rv 1 + assign PIPERX2EQDONE_in = (PIPERX2EQDONE !== 1'bz) && PIPERX2EQDONE_delay; // rv 0 + assign PIPERX2EQLPADAPTDONE_in = (PIPERX2EQLPADAPTDONE !== 1'bz) && PIPERX2EQLPADAPTDONE_delay; // rv 0 + assign PIPERX2EQLPLFFSSEL_in = (PIPERX2EQLPLFFSSEL !== 1'bz) && PIPERX2EQLPLFFSSEL_delay; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX2EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX2EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX2EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX2EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX2EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX2EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX2EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX2EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX2EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX2EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX2EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX2EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX2EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX2EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX2EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX2EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX2EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX2EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX2EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX2EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX2PHYSTATUS_in = (PIPERX2PHYSTATUS === 1'bz) || PIPERX2PHYSTATUS_delay; // rv 1 + assign PIPERX2STARTBLOCK_in = (PIPERX2STARTBLOCK !== 1'bz) && PIPERX2STARTBLOCK_delay; // rv 0 + assign PIPERX2STATUS_in[0] = (PIPERX2STATUS[0] !== 1'bz) && PIPERX2STATUS_delay[0]; // rv 0 + assign PIPERX2STATUS_in[1] = (PIPERX2STATUS[1] !== 1'bz) && PIPERX2STATUS_delay[1]; // rv 0 + assign PIPERX2STATUS_in[2] = (PIPERX2STATUS[2] !== 1'bz) && PIPERX2STATUS_delay[2]; // rv 0 + assign PIPERX2SYNCHEADER_in[0] = (PIPERX2SYNCHEADER[0] !== 1'bz) && PIPERX2SYNCHEADER_delay[0]; // rv 0 + assign PIPERX2SYNCHEADER_in[1] = (PIPERX2SYNCHEADER[1] !== 1'bz) && PIPERX2SYNCHEADER_delay[1]; // rv 0 + assign PIPERX2VALID_in = (PIPERX2VALID !== 1'bz) && PIPERX2VALID_delay; // rv 0 + assign PIPERX3CHARISK_in[0] = (PIPERX3CHARISK[0] === 1'bz) || PIPERX3CHARISK_delay[0]; // rv 1 + assign PIPERX3CHARISK_in[1] = (PIPERX3CHARISK[1] === 1'bz) || PIPERX3CHARISK_delay[1]; // rv 1 + assign PIPERX3DATAVALID_in = (PIPERX3DATAVALID !== 1'bz) && PIPERX3DATAVALID_delay; // rv 0 + assign PIPERX3DATA_in[0] = (PIPERX3DATA[0] !== 1'bz) && PIPERX3DATA_delay[0]; // rv 0 + assign PIPERX3DATA_in[10] = (PIPERX3DATA[10] !== 1'bz) && PIPERX3DATA_delay[10]; // rv 0 + assign PIPERX3DATA_in[11] = (PIPERX3DATA[11] !== 1'bz) && PIPERX3DATA_delay[11]; // rv 0 + assign PIPERX3DATA_in[12] = (PIPERX3DATA[12] !== 1'bz) && PIPERX3DATA_delay[12]; // rv 0 + assign PIPERX3DATA_in[13] = (PIPERX3DATA[13] !== 1'bz) && PIPERX3DATA_delay[13]; // rv 0 + assign PIPERX3DATA_in[14] = (PIPERX3DATA[14] !== 1'bz) && PIPERX3DATA_delay[14]; // rv 0 + assign PIPERX3DATA_in[15] = (PIPERX3DATA[15] !== 1'bz) && PIPERX3DATA_delay[15]; // rv 0 + assign PIPERX3DATA_in[16] = (PIPERX3DATA[16] !== 1'bz) && PIPERX3DATA_delay[16]; // rv 0 + assign PIPERX3DATA_in[17] = (PIPERX3DATA[17] !== 1'bz) && PIPERX3DATA_delay[17]; // rv 0 + assign PIPERX3DATA_in[18] = (PIPERX3DATA[18] !== 1'bz) && PIPERX3DATA_delay[18]; // rv 0 + assign PIPERX3DATA_in[19] = (PIPERX3DATA[19] !== 1'bz) && PIPERX3DATA_delay[19]; // rv 0 + assign PIPERX3DATA_in[1] = (PIPERX3DATA[1] !== 1'bz) && PIPERX3DATA_delay[1]; // rv 0 + assign PIPERX3DATA_in[20] = (PIPERX3DATA[20] !== 1'bz) && PIPERX3DATA_delay[20]; // rv 0 + assign PIPERX3DATA_in[21] = (PIPERX3DATA[21] !== 1'bz) && PIPERX3DATA_delay[21]; // rv 0 + assign PIPERX3DATA_in[22] = (PIPERX3DATA[22] !== 1'bz) && PIPERX3DATA_delay[22]; // rv 0 + assign PIPERX3DATA_in[23] = (PIPERX3DATA[23] !== 1'bz) && PIPERX3DATA_delay[23]; // rv 0 + assign PIPERX3DATA_in[24] = (PIPERX3DATA[24] !== 1'bz) && PIPERX3DATA_delay[24]; // rv 0 + assign PIPERX3DATA_in[25] = (PIPERX3DATA[25] !== 1'bz) && PIPERX3DATA_delay[25]; // rv 0 + assign PIPERX3DATA_in[26] = (PIPERX3DATA[26] !== 1'bz) && PIPERX3DATA_delay[26]; // rv 0 + assign PIPERX3DATA_in[27] = (PIPERX3DATA[27] !== 1'bz) && PIPERX3DATA_delay[27]; // rv 0 + assign PIPERX3DATA_in[28] = (PIPERX3DATA[28] !== 1'bz) && PIPERX3DATA_delay[28]; // rv 0 + assign PIPERX3DATA_in[29] = (PIPERX3DATA[29] !== 1'bz) && PIPERX3DATA_delay[29]; // rv 0 + assign PIPERX3DATA_in[2] = (PIPERX3DATA[2] !== 1'bz) && PIPERX3DATA_delay[2]; // rv 0 + assign PIPERX3DATA_in[30] = (PIPERX3DATA[30] !== 1'bz) && PIPERX3DATA_delay[30]; // rv 0 + assign PIPERX3DATA_in[31] = (PIPERX3DATA[31] !== 1'bz) && PIPERX3DATA_delay[31]; // rv 0 + assign PIPERX3DATA_in[3] = (PIPERX3DATA[3] !== 1'bz) && PIPERX3DATA_delay[3]; // rv 0 + assign PIPERX3DATA_in[4] = (PIPERX3DATA[4] !== 1'bz) && PIPERX3DATA_delay[4]; // rv 0 + assign PIPERX3DATA_in[5] = (PIPERX3DATA[5] !== 1'bz) && PIPERX3DATA_delay[5]; // rv 0 + assign PIPERX3DATA_in[6] = (PIPERX3DATA[6] !== 1'bz) && PIPERX3DATA_delay[6]; // rv 0 + assign PIPERX3DATA_in[7] = (PIPERX3DATA[7] !== 1'bz) && PIPERX3DATA_delay[7]; // rv 0 + assign PIPERX3DATA_in[8] = (PIPERX3DATA[8] !== 1'bz) && PIPERX3DATA_delay[8]; // rv 0 + assign PIPERX3DATA_in[9] = (PIPERX3DATA[9] !== 1'bz) && PIPERX3DATA_delay[9]; // rv 0 + assign PIPERX3ELECIDLE_in = (PIPERX3ELECIDLE === 1'bz) || PIPERX3ELECIDLE_delay; // rv 1 + assign PIPERX3EQDONE_in = (PIPERX3EQDONE !== 1'bz) && PIPERX3EQDONE_delay; // rv 0 + assign PIPERX3EQLPADAPTDONE_in = (PIPERX3EQLPADAPTDONE !== 1'bz) && PIPERX3EQLPADAPTDONE_delay; // rv 0 + assign PIPERX3EQLPLFFSSEL_in = (PIPERX3EQLPLFFSSEL !== 1'bz) && PIPERX3EQLPLFFSSEL_delay; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX3EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX3EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX3EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX3EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX3EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX3EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX3EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX3EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX3EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX3EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX3EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX3EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX3EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX3EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX3EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX3EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX3EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX3EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX3EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX3EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX3PHYSTATUS_in = (PIPERX3PHYSTATUS === 1'bz) || PIPERX3PHYSTATUS_delay; // rv 1 + assign PIPERX3STARTBLOCK_in = (PIPERX3STARTBLOCK !== 1'bz) && PIPERX3STARTBLOCK_delay; // rv 0 + assign PIPERX3STATUS_in[0] = (PIPERX3STATUS[0] !== 1'bz) && PIPERX3STATUS_delay[0]; // rv 0 + assign PIPERX3STATUS_in[1] = (PIPERX3STATUS[1] !== 1'bz) && PIPERX3STATUS_delay[1]; // rv 0 + assign PIPERX3STATUS_in[2] = (PIPERX3STATUS[2] !== 1'bz) && PIPERX3STATUS_delay[2]; // rv 0 + assign PIPERX3SYNCHEADER_in[0] = (PIPERX3SYNCHEADER[0] !== 1'bz) && PIPERX3SYNCHEADER_delay[0]; // rv 0 + assign PIPERX3SYNCHEADER_in[1] = (PIPERX3SYNCHEADER[1] !== 1'bz) && PIPERX3SYNCHEADER_delay[1]; // rv 0 + assign PIPERX3VALID_in = (PIPERX3VALID !== 1'bz) && PIPERX3VALID_delay; // rv 0 + assign PIPERX4CHARISK_in[0] = (PIPERX4CHARISK[0] === 1'bz) || PIPERX4CHARISK_delay[0]; // rv 1 + assign PIPERX4CHARISK_in[1] = (PIPERX4CHARISK[1] === 1'bz) || PIPERX4CHARISK_delay[1]; // rv 1 + assign PIPERX4DATAVALID_in = (PIPERX4DATAVALID !== 1'bz) && PIPERX4DATAVALID_delay; // rv 0 + assign PIPERX4DATA_in[0] = (PIPERX4DATA[0] !== 1'bz) && PIPERX4DATA_delay[0]; // rv 0 + assign PIPERX4DATA_in[10] = (PIPERX4DATA[10] !== 1'bz) && PIPERX4DATA_delay[10]; // rv 0 + assign PIPERX4DATA_in[11] = (PIPERX4DATA[11] !== 1'bz) && PIPERX4DATA_delay[11]; // rv 0 + assign PIPERX4DATA_in[12] = (PIPERX4DATA[12] !== 1'bz) && PIPERX4DATA_delay[12]; // rv 0 + assign PIPERX4DATA_in[13] = (PIPERX4DATA[13] !== 1'bz) && PIPERX4DATA_delay[13]; // rv 0 + assign PIPERX4DATA_in[14] = (PIPERX4DATA[14] !== 1'bz) && PIPERX4DATA_delay[14]; // rv 0 + assign PIPERX4DATA_in[15] = (PIPERX4DATA[15] !== 1'bz) && PIPERX4DATA_delay[15]; // rv 0 + assign PIPERX4DATA_in[16] = (PIPERX4DATA[16] !== 1'bz) && PIPERX4DATA_delay[16]; // rv 0 + assign PIPERX4DATA_in[17] = (PIPERX4DATA[17] !== 1'bz) && PIPERX4DATA_delay[17]; // rv 0 + assign PIPERX4DATA_in[18] = (PIPERX4DATA[18] !== 1'bz) && PIPERX4DATA_delay[18]; // rv 0 + assign PIPERX4DATA_in[19] = (PIPERX4DATA[19] !== 1'bz) && PIPERX4DATA_delay[19]; // rv 0 + assign PIPERX4DATA_in[1] = (PIPERX4DATA[1] !== 1'bz) && PIPERX4DATA_delay[1]; // rv 0 + assign PIPERX4DATA_in[20] = (PIPERX4DATA[20] !== 1'bz) && PIPERX4DATA_delay[20]; // rv 0 + assign PIPERX4DATA_in[21] = (PIPERX4DATA[21] !== 1'bz) && PIPERX4DATA_delay[21]; // rv 0 + assign PIPERX4DATA_in[22] = (PIPERX4DATA[22] !== 1'bz) && PIPERX4DATA_delay[22]; // rv 0 + assign PIPERX4DATA_in[23] = (PIPERX4DATA[23] !== 1'bz) && PIPERX4DATA_delay[23]; // rv 0 + assign PIPERX4DATA_in[24] = (PIPERX4DATA[24] !== 1'bz) && PIPERX4DATA_delay[24]; // rv 0 + assign PIPERX4DATA_in[25] = (PIPERX4DATA[25] !== 1'bz) && PIPERX4DATA_delay[25]; // rv 0 + assign PIPERX4DATA_in[26] = (PIPERX4DATA[26] !== 1'bz) && PIPERX4DATA_delay[26]; // rv 0 + assign PIPERX4DATA_in[27] = (PIPERX4DATA[27] !== 1'bz) && PIPERX4DATA_delay[27]; // rv 0 + assign PIPERX4DATA_in[28] = (PIPERX4DATA[28] !== 1'bz) && PIPERX4DATA_delay[28]; // rv 0 + assign PIPERX4DATA_in[29] = (PIPERX4DATA[29] !== 1'bz) && PIPERX4DATA_delay[29]; // rv 0 + assign PIPERX4DATA_in[2] = (PIPERX4DATA[2] !== 1'bz) && PIPERX4DATA_delay[2]; // rv 0 + assign PIPERX4DATA_in[30] = (PIPERX4DATA[30] !== 1'bz) && PIPERX4DATA_delay[30]; // rv 0 + assign PIPERX4DATA_in[31] = (PIPERX4DATA[31] !== 1'bz) && PIPERX4DATA_delay[31]; // rv 0 + assign PIPERX4DATA_in[3] = (PIPERX4DATA[3] !== 1'bz) && PIPERX4DATA_delay[3]; // rv 0 + assign PIPERX4DATA_in[4] = (PIPERX4DATA[4] !== 1'bz) && PIPERX4DATA_delay[4]; // rv 0 + assign PIPERX4DATA_in[5] = (PIPERX4DATA[5] !== 1'bz) && PIPERX4DATA_delay[5]; // rv 0 + assign PIPERX4DATA_in[6] = (PIPERX4DATA[6] !== 1'bz) && PIPERX4DATA_delay[6]; // rv 0 + assign PIPERX4DATA_in[7] = (PIPERX4DATA[7] !== 1'bz) && PIPERX4DATA_delay[7]; // rv 0 + assign PIPERX4DATA_in[8] = (PIPERX4DATA[8] !== 1'bz) && PIPERX4DATA_delay[8]; // rv 0 + assign PIPERX4DATA_in[9] = (PIPERX4DATA[9] !== 1'bz) && PIPERX4DATA_delay[9]; // rv 0 + assign PIPERX4ELECIDLE_in = (PIPERX4ELECIDLE === 1'bz) || PIPERX4ELECIDLE_delay; // rv 1 + assign PIPERX4EQDONE_in = (PIPERX4EQDONE !== 1'bz) && PIPERX4EQDONE_delay; // rv 0 + assign PIPERX4EQLPADAPTDONE_in = (PIPERX4EQLPADAPTDONE !== 1'bz) && PIPERX4EQLPADAPTDONE_delay; // rv 0 + assign PIPERX4EQLPLFFSSEL_in = (PIPERX4EQLPLFFSSEL !== 1'bz) && PIPERX4EQLPLFFSSEL_delay; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX4EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX4EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX4EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX4EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX4EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX4EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX4EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX4EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX4EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX4EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX4EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX4EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX4EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX4EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX4EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX4EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX4EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX4EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX4EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX4EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX4PHYSTATUS_in = (PIPERX4PHYSTATUS === 1'bz) || PIPERX4PHYSTATUS_delay; // rv 1 + assign PIPERX4STARTBLOCK_in = (PIPERX4STARTBLOCK !== 1'bz) && PIPERX4STARTBLOCK_delay; // rv 0 + assign PIPERX4STATUS_in[0] = (PIPERX4STATUS[0] !== 1'bz) && PIPERX4STATUS_delay[0]; // rv 0 + assign PIPERX4STATUS_in[1] = (PIPERX4STATUS[1] !== 1'bz) && PIPERX4STATUS_delay[1]; // rv 0 + assign PIPERX4STATUS_in[2] = (PIPERX4STATUS[2] !== 1'bz) && PIPERX4STATUS_delay[2]; // rv 0 + assign PIPERX4SYNCHEADER_in[0] = (PIPERX4SYNCHEADER[0] !== 1'bz) && PIPERX4SYNCHEADER_delay[0]; // rv 0 + assign PIPERX4SYNCHEADER_in[1] = (PIPERX4SYNCHEADER[1] !== 1'bz) && PIPERX4SYNCHEADER_delay[1]; // rv 0 + assign PIPERX4VALID_in = (PIPERX4VALID !== 1'bz) && PIPERX4VALID_delay; // rv 0 + assign PIPERX5CHARISK_in[0] = (PIPERX5CHARISK[0] === 1'bz) || PIPERX5CHARISK_delay[0]; // rv 1 + assign PIPERX5CHARISK_in[1] = (PIPERX5CHARISK[1] === 1'bz) || PIPERX5CHARISK_delay[1]; // rv 1 + assign PIPERX5DATAVALID_in = (PIPERX5DATAVALID !== 1'bz) && PIPERX5DATAVALID_delay; // rv 0 + assign PIPERX5DATA_in[0] = (PIPERX5DATA[0] !== 1'bz) && PIPERX5DATA_delay[0]; // rv 0 + assign PIPERX5DATA_in[10] = (PIPERX5DATA[10] !== 1'bz) && PIPERX5DATA_delay[10]; // rv 0 + assign PIPERX5DATA_in[11] = (PIPERX5DATA[11] !== 1'bz) && PIPERX5DATA_delay[11]; // rv 0 + assign PIPERX5DATA_in[12] = (PIPERX5DATA[12] !== 1'bz) && PIPERX5DATA_delay[12]; // rv 0 + assign PIPERX5DATA_in[13] = (PIPERX5DATA[13] !== 1'bz) && PIPERX5DATA_delay[13]; // rv 0 + assign PIPERX5DATA_in[14] = (PIPERX5DATA[14] !== 1'bz) && PIPERX5DATA_delay[14]; // rv 0 + assign PIPERX5DATA_in[15] = (PIPERX5DATA[15] !== 1'bz) && PIPERX5DATA_delay[15]; // rv 0 + assign PIPERX5DATA_in[16] = (PIPERX5DATA[16] !== 1'bz) && PIPERX5DATA_delay[16]; // rv 0 + assign PIPERX5DATA_in[17] = (PIPERX5DATA[17] !== 1'bz) && PIPERX5DATA_delay[17]; // rv 0 + assign PIPERX5DATA_in[18] = (PIPERX5DATA[18] !== 1'bz) && PIPERX5DATA_delay[18]; // rv 0 + assign PIPERX5DATA_in[19] = (PIPERX5DATA[19] !== 1'bz) && PIPERX5DATA_delay[19]; // rv 0 + assign PIPERX5DATA_in[1] = (PIPERX5DATA[1] !== 1'bz) && PIPERX5DATA_delay[1]; // rv 0 + assign PIPERX5DATA_in[20] = (PIPERX5DATA[20] !== 1'bz) && PIPERX5DATA_delay[20]; // rv 0 + assign PIPERX5DATA_in[21] = (PIPERX5DATA[21] !== 1'bz) && PIPERX5DATA_delay[21]; // rv 0 + assign PIPERX5DATA_in[22] = (PIPERX5DATA[22] !== 1'bz) && PIPERX5DATA_delay[22]; // rv 0 + assign PIPERX5DATA_in[23] = (PIPERX5DATA[23] !== 1'bz) && PIPERX5DATA_delay[23]; // rv 0 + assign PIPERX5DATA_in[24] = (PIPERX5DATA[24] !== 1'bz) && PIPERX5DATA_delay[24]; // rv 0 + assign PIPERX5DATA_in[25] = (PIPERX5DATA[25] !== 1'bz) && PIPERX5DATA_delay[25]; // rv 0 + assign PIPERX5DATA_in[26] = (PIPERX5DATA[26] !== 1'bz) && PIPERX5DATA_delay[26]; // rv 0 + assign PIPERX5DATA_in[27] = (PIPERX5DATA[27] !== 1'bz) && PIPERX5DATA_delay[27]; // rv 0 + assign PIPERX5DATA_in[28] = (PIPERX5DATA[28] !== 1'bz) && PIPERX5DATA_delay[28]; // rv 0 + assign PIPERX5DATA_in[29] = (PIPERX5DATA[29] !== 1'bz) && PIPERX5DATA_delay[29]; // rv 0 + assign PIPERX5DATA_in[2] = (PIPERX5DATA[2] !== 1'bz) && PIPERX5DATA_delay[2]; // rv 0 + assign PIPERX5DATA_in[30] = (PIPERX5DATA[30] !== 1'bz) && PIPERX5DATA_delay[30]; // rv 0 + assign PIPERX5DATA_in[31] = (PIPERX5DATA[31] !== 1'bz) && PIPERX5DATA_delay[31]; // rv 0 + assign PIPERX5DATA_in[3] = (PIPERX5DATA[3] !== 1'bz) && PIPERX5DATA_delay[3]; // rv 0 + assign PIPERX5DATA_in[4] = (PIPERX5DATA[4] !== 1'bz) && PIPERX5DATA_delay[4]; // rv 0 + assign PIPERX5DATA_in[5] = (PIPERX5DATA[5] !== 1'bz) && PIPERX5DATA_delay[5]; // rv 0 + assign PIPERX5DATA_in[6] = (PIPERX5DATA[6] !== 1'bz) && PIPERX5DATA_delay[6]; // rv 0 + assign PIPERX5DATA_in[7] = (PIPERX5DATA[7] !== 1'bz) && PIPERX5DATA_delay[7]; // rv 0 + assign PIPERX5DATA_in[8] = (PIPERX5DATA[8] !== 1'bz) && PIPERX5DATA_delay[8]; // rv 0 + assign PIPERX5DATA_in[9] = (PIPERX5DATA[9] !== 1'bz) && PIPERX5DATA_delay[9]; // rv 0 + assign PIPERX5ELECIDLE_in = (PIPERX5ELECIDLE === 1'bz) || PIPERX5ELECIDLE_delay; // rv 1 + assign PIPERX5EQDONE_in = (PIPERX5EQDONE !== 1'bz) && PIPERX5EQDONE_delay; // rv 0 + assign PIPERX5EQLPADAPTDONE_in = (PIPERX5EQLPADAPTDONE !== 1'bz) && PIPERX5EQLPADAPTDONE_delay; // rv 0 + assign PIPERX5EQLPLFFSSEL_in = (PIPERX5EQLPLFFSSEL !== 1'bz) && PIPERX5EQLPLFFSSEL_delay; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX5EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX5EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX5EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX5EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX5EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX5EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX5EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX5EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX5EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX5EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX5EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX5EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX5EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX5EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX5EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX5EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX5EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX5EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX5EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX5EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX5PHYSTATUS_in = (PIPERX5PHYSTATUS === 1'bz) || PIPERX5PHYSTATUS_delay; // rv 1 + assign PIPERX5STARTBLOCK_in = (PIPERX5STARTBLOCK !== 1'bz) && PIPERX5STARTBLOCK_delay; // rv 0 + assign PIPERX5STATUS_in[0] = (PIPERX5STATUS[0] !== 1'bz) && PIPERX5STATUS_delay[0]; // rv 0 + assign PIPERX5STATUS_in[1] = (PIPERX5STATUS[1] !== 1'bz) && PIPERX5STATUS_delay[1]; // rv 0 + assign PIPERX5STATUS_in[2] = (PIPERX5STATUS[2] !== 1'bz) && PIPERX5STATUS_delay[2]; // rv 0 + assign PIPERX5SYNCHEADER_in[0] = (PIPERX5SYNCHEADER[0] !== 1'bz) && PIPERX5SYNCHEADER_delay[0]; // rv 0 + assign PIPERX5SYNCHEADER_in[1] = (PIPERX5SYNCHEADER[1] !== 1'bz) && PIPERX5SYNCHEADER_delay[1]; // rv 0 + assign PIPERX5VALID_in = (PIPERX5VALID !== 1'bz) && PIPERX5VALID_delay; // rv 0 + assign PIPERX6CHARISK_in[0] = (PIPERX6CHARISK[0] === 1'bz) || PIPERX6CHARISK_delay[0]; // rv 1 + assign PIPERX6CHARISK_in[1] = (PIPERX6CHARISK[1] === 1'bz) || PIPERX6CHARISK_delay[1]; // rv 1 + assign PIPERX6DATAVALID_in = (PIPERX6DATAVALID !== 1'bz) && PIPERX6DATAVALID_delay; // rv 0 + assign PIPERX6DATA_in[0] = (PIPERX6DATA[0] !== 1'bz) && PIPERX6DATA_delay[0]; // rv 0 + assign PIPERX6DATA_in[10] = (PIPERX6DATA[10] !== 1'bz) && PIPERX6DATA_delay[10]; // rv 0 + assign PIPERX6DATA_in[11] = (PIPERX6DATA[11] !== 1'bz) && PIPERX6DATA_delay[11]; // rv 0 + assign PIPERX6DATA_in[12] = (PIPERX6DATA[12] !== 1'bz) && PIPERX6DATA_delay[12]; // rv 0 + assign PIPERX6DATA_in[13] = (PIPERX6DATA[13] !== 1'bz) && PIPERX6DATA_delay[13]; // rv 0 + assign PIPERX6DATA_in[14] = (PIPERX6DATA[14] !== 1'bz) && PIPERX6DATA_delay[14]; // rv 0 + assign PIPERX6DATA_in[15] = (PIPERX6DATA[15] !== 1'bz) && PIPERX6DATA_delay[15]; // rv 0 + assign PIPERX6DATA_in[16] = (PIPERX6DATA[16] !== 1'bz) && PIPERX6DATA_delay[16]; // rv 0 + assign PIPERX6DATA_in[17] = (PIPERX6DATA[17] !== 1'bz) && PIPERX6DATA_delay[17]; // rv 0 + assign PIPERX6DATA_in[18] = (PIPERX6DATA[18] !== 1'bz) && PIPERX6DATA_delay[18]; // rv 0 + assign PIPERX6DATA_in[19] = (PIPERX6DATA[19] !== 1'bz) && PIPERX6DATA_delay[19]; // rv 0 + assign PIPERX6DATA_in[1] = (PIPERX6DATA[1] !== 1'bz) && PIPERX6DATA_delay[1]; // rv 0 + assign PIPERX6DATA_in[20] = (PIPERX6DATA[20] !== 1'bz) && PIPERX6DATA_delay[20]; // rv 0 + assign PIPERX6DATA_in[21] = (PIPERX6DATA[21] !== 1'bz) && PIPERX6DATA_delay[21]; // rv 0 + assign PIPERX6DATA_in[22] = (PIPERX6DATA[22] !== 1'bz) && PIPERX6DATA_delay[22]; // rv 0 + assign PIPERX6DATA_in[23] = (PIPERX6DATA[23] !== 1'bz) && PIPERX6DATA_delay[23]; // rv 0 + assign PIPERX6DATA_in[24] = (PIPERX6DATA[24] !== 1'bz) && PIPERX6DATA_delay[24]; // rv 0 + assign PIPERX6DATA_in[25] = (PIPERX6DATA[25] !== 1'bz) && PIPERX6DATA_delay[25]; // rv 0 + assign PIPERX6DATA_in[26] = (PIPERX6DATA[26] !== 1'bz) && PIPERX6DATA_delay[26]; // rv 0 + assign PIPERX6DATA_in[27] = (PIPERX6DATA[27] !== 1'bz) && PIPERX6DATA_delay[27]; // rv 0 + assign PIPERX6DATA_in[28] = (PIPERX6DATA[28] !== 1'bz) && PIPERX6DATA_delay[28]; // rv 0 + assign PIPERX6DATA_in[29] = (PIPERX6DATA[29] !== 1'bz) && PIPERX6DATA_delay[29]; // rv 0 + assign PIPERX6DATA_in[2] = (PIPERX6DATA[2] !== 1'bz) && PIPERX6DATA_delay[2]; // rv 0 + assign PIPERX6DATA_in[30] = (PIPERX6DATA[30] !== 1'bz) && PIPERX6DATA_delay[30]; // rv 0 + assign PIPERX6DATA_in[31] = (PIPERX6DATA[31] !== 1'bz) && PIPERX6DATA_delay[31]; // rv 0 + assign PIPERX6DATA_in[3] = (PIPERX6DATA[3] !== 1'bz) && PIPERX6DATA_delay[3]; // rv 0 + assign PIPERX6DATA_in[4] = (PIPERX6DATA[4] !== 1'bz) && PIPERX6DATA_delay[4]; // rv 0 + assign PIPERX6DATA_in[5] = (PIPERX6DATA[5] !== 1'bz) && PIPERX6DATA_delay[5]; // rv 0 + assign PIPERX6DATA_in[6] = (PIPERX6DATA[6] !== 1'bz) && PIPERX6DATA_delay[6]; // rv 0 + assign PIPERX6DATA_in[7] = (PIPERX6DATA[7] !== 1'bz) && PIPERX6DATA_delay[7]; // rv 0 + assign PIPERX6DATA_in[8] = (PIPERX6DATA[8] !== 1'bz) && PIPERX6DATA_delay[8]; // rv 0 + assign PIPERX6DATA_in[9] = (PIPERX6DATA[9] !== 1'bz) && PIPERX6DATA_delay[9]; // rv 0 + assign PIPERX6ELECIDLE_in = (PIPERX6ELECIDLE === 1'bz) || PIPERX6ELECIDLE_delay; // rv 1 + assign PIPERX6EQDONE_in = (PIPERX6EQDONE !== 1'bz) && PIPERX6EQDONE_delay; // rv 0 + assign PIPERX6EQLPADAPTDONE_in = (PIPERX6EQLPADAPTDONE !== 1'bz) && PIPERX6EQLPADAPTDONE_delay; // rv 0 + assign PIPERX6EQLPLFFSSEL_in = (PIPERX6EQLPLFFSSEL !== 1'bz) && PIPERX6EQLPLFFSSEL_delay; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX6EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX6EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX6EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX6EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX6EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX6EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX6EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX6EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX6EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX6EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX6EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX6EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX6EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX6EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX6EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX6EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX6EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX6EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX6EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX6EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX6PHYSTATUS_in = (PIPERX6PHYSTATUS === 1'bz) || PIPERX6PHYSTATUS_delay; // rv 1 + assign PIPERX6STARTBLOCK_in = (PIPERX6STARTBLOCK !== 1'bz) && PIPERX6STARTBLOCK_delay; // rv 0 + assign PIPERX6STATUS_in[0] = (PIPERX6STATUS[0] !== 1'bz) && PIPERX6STATUS_delay[0]; // rv 0 + assign PIPERX6STATUS_in[1] = (PIPERX6STATUS[1] !== 1'bz) && PIPERX6STATUS_delay[1]; // rv 0 + assign PIPERX6STATUS_in[2] = (PIPERX6STATUS[2] !== 1'bz) && PIPERX6STATUS_delay[2]; // rv 0 + assign PIPERX6SYNCHEADER_in[0] = (PIPERX6SYNCHEADER[0] !== 1'bz) && PIPERX6SYNCHEADER_delay[0]; // rv 0 + assign PIPERX6SYNCHEADER_in[1] = (PIPERX6SYNCHEADER[1] !== 1'bz) && PIPERX6SYNCHEADER_delay[1]; // rv 0 + assign PIPERX6VALID_in = (PIPERX6VALID !== 1'bz) && PIPERX6VALID_delay; // rv 0 + assign PIPERX7CHARISK_in[0] = (PIPERX7CHARISK[0] === 1'bz) || PIPERX7CHARISK_delay[0]; // rv 1 + assign PIPERX7CHARISK_in[1] = (PIPERX7CHARISK[1] === 1'bz) || PIPERX7CHARISK_delay[1]; // rv 1 + assign PIPERX7DATAVALID_in = (PIPERX7DATAVALID !== 1'bz) && PIPERX7DATAVALID_delay; // rv 0 + assign PIPERX7DATA_in[0] = (PIPERX7DATA[0] !== 1'bz) && PIPERX7DATA_delay[0]; // rv 0 + assign PIPERX7DATA_in[10] = (PIPERX7DATA[10] !== 1'bz) && PIPERX7DATA_delay[10]; // rv 0 + assign PIPERX7DATA_in[11] = (PIPERX7DATA[11] !== 1'bz) && PIPERX7DATA_delay[11]; // rv 0 + assign PIPERX7DATA_in[12] = (PIPERX7DATA[12] !== 1'bz) && PIPERX7DATA_delay[12]; // rv 0 + assign PIPERX7DATA_in[13] = (PIPERX7DATA[13] !== 1'bz) && PIPERX7DATA_delay[13]; // rv 0 + assign PIPERX7DATA_in[14] = (PIPERX7DATA[14] !== 1'bz) && PIPERX7DATA_delay[14]; // rv 0 + assign PIPERX7DATA_in[15] = (PIPERX7DATA[15] !== 1'bz) && PIPERX7DATA_delay[15]; // rv 0 + assign PIPERX7DATA_in[16] = (PIPERX7DATA[16] !== 1'bz) && PIPERX7DATA_delay[16]; // rv 0 + assign PIPERX7DATA_in[17] = (PIPERX7DATA[17] !== 1'bz) && PIPERX7DATA_delay[17]; // rv 0 + assign PIPERX7DATA_in[18] = (PIPERX7DATA[18] !== 1'bz) && PIPERX7DATA_delay[18]; // rv 0 + assign PIPERX7DATA_in[19] = (PIPERX7DATA[19] !== 1'bz) && PIPERX7DATA_delay[19]; // rv 0 + assign PIPERX7DATA_in[1] = (PIPERX7DATA[1] !== 1'bz) && PIPERX7DATA_delay[1]; // rv 0 + assign PIPERX7DATA_in[20] = (PIPERX7DATA[20] !== 1'bz) && PIPERX7DATA_delay[20]; // rv 0 + assign PIPERX7DATA_in[21] = (PIPERX7DATA[21] !== 1'bz) && PIPERX7DATA_delay[21]; // rv 0 + assign PIPERX7DATA_in[22] = (PIPERX7DATA[22] !== 1'bz) && PIPERX7DATA_delay[22]; // rv 0 + assign PIPERX7DATA_in[23] = (PIPERX7DATA[23] !== 1'bz) && PIPERX7DATA_delay[23]; // rv 0 + assign PIPERX7DATA_in[24] = (PIPERX7DATA[24] !== 1'bz) && PIPERX7DATA_delay[24]; // rv 0 + assign PIPERX7DATA_in[25] = (PIPERX7DATA[25] !== 1'bz) && PIPERX7DATA_delay[25]; // rv 0 + assign PIPERX7DATA_in[26] = (PIPERX7DATA[26] !== 1'bz) && PIPERX7DATA_delay[26]; // rv 0 + assign PIPERX7DATA_in[27] = (PIPERX7DATA[27] !== 1'bz) && PIPERX7DATA_delay[27]; // rv 0 + assign PIPERX7DATA_in[28] = (PIPERX7DATA[28] !== 1'bz) && PIPERX7DATA_delay[28]; // rv 0 + assign PIPERX7DATA_in[29] = (PIPERX7DATA[29] !== 1'bz) && PIPERX7DATA_delay[29]; // rv 0 + assign PIPERX7DATA_in[2] = (PIPERX7DATA[2] !== 1'bz) && PIPERX7DATA_delay[2]; // rv 0 + assign PIPERX7DATA_in[30] = (PIPERX7DATA[30] !== 1'bz) && PIPERX7DATA_delay[30]; // rv 0 + assign PIPERX7DATA_in[31] = (PIPERX7DATA[31] !== 1'bz) && PIPERX7DATA_delay[31]; // rv 0 + assign PIPERX7DATA_in[3] = (PIPERX7DATA[3] !== 1'bz) && PIPERX7DATA_delay[3]; // rv 0 + assign PIPERX7DATA_in[4] = (PIPERX7DATA[4] !== 1'bz) && PIPERX7DATA_delay[4]; // rv 0 + assign PIPERX7DATA_in[5] = (PIPERX7DATA[5] !== 1'bz) && PIPERX7DATA_delay[5]; // rv 0 + assign PIPERX7DATA_in[6] = (PIPERX7DATA[6] !== 1'bz) && PIPERX7DATA_delay[6]; // rv 0 + assign PIPERX7DATA_in[7] = (PIPERX7DATA[7] !== 1'bz) && PIPERX7DATA_delay[7]; // rv 0 + assign PIPERX7DATA_in[8] = (PIPERX7DATA[8] !== 1'bz) && PIPERX7DATA_delay[8]; // rv 0 + assign PIPERX7DATA_in[9] = (PIPERX7DATA[9] !== 1'bz) && PIPERX7DATA_delay[9]; // rv 0 + assign PIPERX7ELECIDLE_in = (PIPERX7ELECIDLE === 1'bz) || PIPERX7ELECIDLE_delay; // rv 1 + assign PIPERX7EQDONE_in = (PIPERX7EQDONE !== 1'bz) && PIPERX7EQDONE_delay; // rv 0 + assign PIPERX7EQLPADAPTDONE_in = (PIPERX7EQLPADAPTDONE !== 1'bz) && PIPERX7EQLPADAPTDONE_delay; // rv 0 + assign PIPERX7EQLPLFFSSEL_in = (PIPERX7EQLPLFFSSEL !== 1'bz) && PIPERX7EQLPLFFSSEL_delay; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[0] = (PIPERX7EQLPNEWTXCOEFFORPRESET[0] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[0]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[10] = (PIPERX7EQLPNEWTXCOEFFORPRESET[10] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[10]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[11] = (PIPERX7EQLPNEWTXCOEFFORPRESET[11] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[11]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[12] = (PIPERX7EQLPNEWTXCOEFFORPRESET[12] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[12]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[13] = (PIPERX7EQLPNEWTXCOEFFORPRESET[13] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[13]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[14] = (PIPERX7EQLPNEWTXCOEFFORPRESET[14] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[14]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[15] = (PIPERX7EQLPNEWTXCOEFFORPRESET[15] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[15]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[16] = (PIPERX7EQLPNEWTXCOEFFORPRESET[16] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[16]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[17] = (PIPERX7EQLPNEWTXCOEFFORPRESET[17] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[17]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[1] = (PIPERX7EQLPNEWTXCOEFFORPRESET[1] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[1]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[2] = (PIPERX7EQLPNEWTXCOEFFORPRESET[2] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[2]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[3] = (PIPERX7EQLPNEWTXCOEFFORPRESET[3] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[3]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[4] = (PIPERX7EQLPNEWTXCOEFFORPRESET[4] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[4]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[5] = (PIPERX7EQLPNEWTXCOEFFORPRESET[5] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[5]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[6] = (PIPERX7EQLPNEWTXCOEFFORPRESET[6] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[6]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[7] = (PIPERX7EQLPNEWTXCOEFFORPRESET[7] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[7]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[8] = (PIPERX7EQLPNEWTXCOEFFORPRESET[8] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[8]; // rv 0 + assign PIPERX7EQLPNEWTXCOEFFORPRESET_in[9] = (PIPERX7EQLPNEWTXCOEFFORPRESET[9] !== 1'bz) && PIPERX7EQLPNEWTXCOEFFORPRESET_delay[9]; // rv 0 + assign PIPERX7PHYSTATUS_in = (PIPERX7PHYSTATUS === 1'bz) || PIPERX7PHYSTATUS_delay; // rv 1 + assign PIPERX7STARTBLOCK_in = (PIPERX7STARTBLOCK !== 1'bz) && PIPERX7STARTBLOCK_delay; // rv 0 + assign PIPERX7STATUS_in[0] = (PIPERX7STATUS[0] !== 1'bz) && PIPERX7STATUS_delay[0]; // rv 0 + assign PIPERX7STATUS_in[1] = (PIPERX7STATUS[1] !== 1'bz) && PIPERX7STATUS_delay[1]; // rv 0 + assign PIPERX7STATUS_in[2] = (PIPERX7STATUS[2] !== 1'bz) && PIPERX7STATUS_delay[2]; // rv 0 + assign PIPERX7SYNCHEADER_in[0] = (PIPERX7SYNCHEADER[0] !== 1'bz) && PIPERX7SYNCHEADER_delay[0]; // rv 0 + assign PIPERX7SYNCHEADER_in[1] = (PIPERX7SYNCHEADER[1] !== 1'bz) && PIPERX7SYNCHEADER_delay[1]; // rv 0 + assign PIPERX7VALID_in = (PIPERX7VALID !== 1'bz) && PIPERX7VALID_delay; // rv 0 + assign PIPETX0EQCOEFF_in[0] = (PIPETX0EQCOEFF[0] !== 1'bz) && PIPETX0EQCOEFF_delay[0]; // rv 0 + assign PIPETX0EQCOEFF_in[10] = (PIPETX0EQCOEFF[10] !== 1'bz) && PIPETX0EQCOEFF_delay[10]; // rv 0 + assign PIPETX0EQCOEFF_in[11] = (PIPETX0EQCOEFF[11] !== 1'bz) && PIPETX0EQCOEFF_delay[11]; // rv 0 + assign PIPETX0EQCOEFF_in[12] = (PIPETX0EQCOEFF[12] !== 1'bz) && PIPETX0EQCOEFF_delay[12]; // rv 0 + assign PIPETX0EQCOEFF_in[13] = (PIPETX0EQCOEFF[13] !== 1'bz) && PIPETX0EQCOEFF_delay[13]; // rv 0 + assign PIPETX0EQCOEFF_in[14] = (PIPETX0EQCOEFF[14] !== 1'bz) && PIPETX0EQCOEFF_delay[14]; // rv 0 + assign PIPETX0EQCOEFF_in[15] = (PIPETX0EQCOEFF[15] !== 1'bz) && PIPETX0EQCOEFF_delay[15]; // rv 0 + assign PIPETX0EQCOEFF_in[16] = (PIPETX0EQCOEFF[16] !== 1'bz) && PIPETX0EQCOEFF_delay[16]; // rv 0 + assign PIPETX0EQCOEFF_in[17] = (PIPETX0EQCOEFF[17] !== 1'bz) && PIPETX0EQCOEFF_delay[17]; // rv 0 + assign PIPETX0EQCOEFF_in[1] = (PIPETX0EQCOEFF[1] !== 1'bz) && PIPETX0EQCOEFF_delay[1]; // rv 0 + assign PIPETX0EQCOEFF_in[2] = (PIPETX0EQCOEFF[2] !== 1'bz) && PIPETX0EQCOEFF_delay[2]; // rv 0 + assign PIPETX0EQCOEFF_in[3] = (PIPETX0EQCOEFF[3] !== 1'bz) && PIPETX0EQCOEFF_delay[3]; // rv 0 + assign PIPETX0EQCOEFF_in[4] = (PIPETX0EQCOEFF[4] !== 1'bz) && PIPETX0EQCOEFF_delay[4]; // rv 0 + assign PIPETX0EQCOEFF_in[5] = (PIPETX0EQCOEFF[5] !== 1'bz) && PIPETX0EQCOEFF_delay[5]; // rv 0 + assign PIPETX0EQCOEFF_in[6] = (PIPETX0EQCOEFF[6] !== 1'bz) && PIPETX0EQCOEFF_delay[6]; // rv 0 + assign PIPETX0EQCOEFF_in[7] = (PIPETX0EQCOEFF[7] !== 1'bz) && PIPETX0EQCOEFF_delay[7]; // rv 0 + assign PIPETX0EQCOEFF_in[8] = (PIPETX0EQCOEFF[8] !== 1'bz) && PIPETX0EQCOEFF_delay[8]; // rv 0 + assign PIPETX0EQCOEFF_in[9] = (PIPETX0EQCOEFF[9] !== 1'bz) && PIPETX0EQCOEFF_delay[9]; // rv 0 + assign PIPETX0EQDONE_in = (PIPETX0EQDONE !== 1'bz) && PIPETX0EQDONE_delay; // rv 0 + assign PIPETX1EQCOEFF_in[0] = (PIPETX1EQCOEFF[0] !== 1'bz) && PIPETX1EQCOEFF_delay[0]; // rv 0 + assign PIPETX1EQCOEFF_in[10] = (PIPETX1EQCOEFF[10] !== 1'bz) && PIPETX1EQCOEFF_delay[10]; // rv 0 + assign PIPETX1EQCOEFF_in[11] = (PIPETX1EQCOEFF[11] !== 1'bz) && PIPETX1EQCOEFF_delay[11]; // rv 0 + assign PIPETX1EQCOEFF_in[12] = (PIPETX1EQCOEFF[12] !== 1'bz) && PIPETX1EQCOEFF_delay[12]; // rv 0 + assign PIPETX1EQCOEFF_in[13] = (PIPETX1EQCOEFF[13] !== 1'bz) && PIPETX1EQCOEFF_delay[13]; // rv 0 + assign PIPETX1EQCOEFF_in[14] = (PIPETX1EQCOEFF[14] !== 1'bz) && PIPETX1EQCOEFF_delay[14]; // rv 0 + assign PIPETX1EQCOEFF_in[15] = (PIPETX1EQCOEFF[15] !== 1'bz) && PIPETX1EQCOEFF_delay[15]; // rv 0 + assign PIPETX1EQCOEFF_in[16] = (PIPETX1EQCOEFF[16] !== 1'bz) && PIPETX1EQCOEFF_delay[16]; // rv 0 + assign PIPETX1EQCOEFF_in[17] = (PIPETX1EQCOEFF[17] !== 1'bz) && PIPETX1EQCOEFF_delay[17]; // rv 0 + assign PIPETX1EQCOEFF_in[1] = (PIPETX1EQCOEFF[1] !== 1'bz) && PIPETX1EQCOEFF_delay[1]; // rv 0 + assign PIPETX1EQCOEFF_in[2] = (PIPETX1EQCOEFF[2] !== 1'bz) && PIPETX1EQCOEFF_delay[2]; // rv 0 + assign PIPETX1EQCOEFF_in[3] = (PIPETX1EQCOEFF[3] !== 1'bz) && PIPETX1EQCOEFF_delay[3]; // rv 0 + assign PIPETX1EQCOEFF_in[4] = (PIPETX1EQCOEFF[4] !== 1'bz) && PIPETX1EQCOEFF_delay[4]; // rv 0 + assign PIPETX1EQCOEFF_in[5] = (PIPETX1EQCOEFF[5] !== 1'bz) && PIPETX1EQCOEFF_delay[5]; // rv 0 + assign PIPETX1EQCOEFF_in[6] = (PIPETX1EQCOEFF[6] !== 1'bz) && PIPETX1EQCOEFF_delay[6]; // rv 0 + assign PIPETX1EQCOEFF_in[7] = (PIPETX1EQCOEFF[7] !== 1'bz) && PIPETX1EQCOEFF_delay[7]; // rv 0 + assign PIPETX1EQCOEFF_in[8] = (PIPETX1EQCOEFF[8] !== 1'bz) && PIPETX1EQCOEFF_delay[8]; // rv 0 + assign PIPETX1EQCOEFF_in[9] = (PIPETX1EQCOEFF[9] !== 1'bz) && PIPETX1EQCOEFF_delay[9]; // rv 0 + assign PIPETX1EQDONE_in = (PIPETX1EQDONE !== 1'bz) && PIPETX1EQDONE_delay; // rv 0 + assign PIPETX2EQCOEFF_in[0] = (PIPETX2EQCOEFF[0] !== 1'bz) && PIPETX2EQCOEFF_delay[0]; // rv 0 + assign PIPETX2EQCOEFF_in[10] = (PIPETX2EQCOEFF[10] !== 1'bz) && PIPETX2EQCOEFF_delay[10]; // rv 0 + assign PIPETX2EQCOEFF_in[11] = (PIPETX2EQCOEFF[11] !== 1'bz) && PIPETX2EQCOEFF_delay[11]; // rv 0 + assign PIPETX2EQCOEFF_in[12] = (PIPETX2EQCOEFF[12] !== 1'bz) && PIPETX2EQCOEFF_delay[12]; // rv 0 + assign PIPETX2EQCOEFF_in[13] = (PIPETX2EQCOEFF[13] !== 1'bz) && PIPETX2EQCOEFF_delay[13]; // rv 0 + assign PIPETX2EQCOEFF_in[14] = (PIPETX2EQCOEFF[14] !== 1'bz) && PIPETX2EQCOEFF_delay[14]; // rv 0 + assign PIPETX2EQCOEFF_in[15] = (PIPETX2EQCOEFF[15] !== 1'bz) && PIPETX2EQCOEFF_delay[15]; // rv 0 + assign PIPETX2EQCOEFF_in[16] = (PIPETX2EQCOEFF[16] !== 1'bz) && PIPETX2EQCOEFF_delay[16]; // rv 0 + assign PIPETX2EQCOEFF_in[17] = (PIPETX2EQCOEFF[17] !== 1'bz) && PIPETX2EQCOEFF_delay[17]; // rv 0 + assign PIPETX2EQCOEFF_in[1] = (PIPETX2EQCOEFF[1] !== 1'bz) && PIPETX2EQCOEFF_delay[1]; // rv 0 + assign PIPETX2EQCOEFF_in[2] = (PIPETX2EQCOEFF[2] !== 1'bz) && PIPETX2EQCOEFF_delay[2]; // rv 0 + assign PIPETX2EQCOEFF_in[3] = (PIPETX2EQCOEFF[3] !== 1'bz) && PIPETX2EQCOEFF_delay[3]; // rv 0 + assign PIPETX2EQCOEFF_in[4] = (PIPETX2EQCOEFF[4] !== 1'bz) && PIPETX2EQCOEFF_delay[4]; // rv 0 + assign PIPETX2EQCOEFF_in[5] = (PIPETX2EQCOEFF[5] !== 1'bz) && PIPETX2EQCOEFF_delay[5]; // rv 0 + assign PIPETX2EQCOEFF_in[6] = (PIPETX2EQCOEFF[6] !== 1'bz) && PIPETX2EQCOEFF_delay[6]; // rv 0 + assign PIPETX2EQCOEFF_in[7] = (PIPETX2EQCOEFF[7] !== 1'bz) && PIPETX2EQCOEFF_delay[7]; // rv 0 + assign PIPETX2EQCOEFF_in[8] = (PIPETX2EQCOEFF[8] !== 1'bz) && PIPETX2EQCOEFF_delay[8]; // rv 0 + assign PIPETX2EQCOEFF_in[9] = (PIPETX2EQCOEFF[9] !== 1'bz) && PIPETX2EQCOEFF_delay[9]; // rv 0 + assign PIPETX2EQDONE_in = (PIPETX2EQDONE !== 1'bz) && PIPETX2EQDONE_delay; // rv 0 + assign PIPETX3EQCOEFF_in[0] = (PIPETX3EQCOEFF[0] !== 1'bz) && PIPETX3EQCOEFF_delay[0]; // rv 0 + assign PIPETX3EQCOEFF_in[10] = (PIPETX3EQCOEFF[10] !== 1'bz) && PIPETX3EQCOEFF_delay[10]; // rv 0 + assign PIPETX3EQCOEFF_in[11] = (PIPETX3EQCOEFF[11] !== 1'bz) && PIPETX3EQCOEFF_delay[11]; // rv 0 + assign PIPETX3EQCOEFF_in[12] = (PIPETX3EQCOEFF[12] !== 1'bz) && PIPETX3EQCOEFF_delay[12]; // rv 0 + assign PIPETX3EQCOEFF_in[13] = (PIPETX3EQCOEFF[13] !== 1'bz) && PIPETX3EQCOEFF_delay[13]; // rv 0 + assign PIPETX3EQCOEFF_in[14] = (PIPETX3EQCOEFF[14] !== 1'bz) && PIPETX3EQCOEFF_delay[14]; // rv 0 + assign PIPETX3EQCOEFF_in[15] = (PIPETX3EQCOEFF[15] !== 1'bz) && PIPETX3EQCOEFF_delay[15]; // rv 0 + assign PIPETX3EQCOEFF_in[16] = (PIPETX3EQCOEFF[16] !== 1'bz) && PIPETX3EQCOEFF_delay[16]; // rv 0 + assign PIPETX3EQCOEFF_in[17] = (PIPETX3EQCOEFF[17] !== 1'bz) && PIPETX3EQCOEFF_delay[17]; // rv 0 + assign PIPETX3EQCOEFF_in[1] = (PIPETX3EQCOEFF[1] !== 1'bz) && PIPETX3EQCOEFF_delay[1]; // rv 0 + assign PIPETX3EQCOEFF_in[2] = (PIPETX3EQCOEFF[2] !== 1'bz) && PIPETX3EQCOEFF_delay[2]; // rv 0 + assign PIPETX3EQCOEFF_in[3] = (PIPETX3EQCOEFF[3] !== 1'bz) && PIPETX3EQCOEFF_delay[3]; // rv 0 + assign PIPETX3EQCOEFF_in[4] = (PIPETX3EQCOEFF[4] !== 1'bz) && PIPETX3EQCOEFF_delay[4]; // rv 0 + assign PIPETX3EQCOEFF_in[5] = (PIPETX3EQCOEFF[5] !== 1'bz) && PIPETX3EQCOEFF_delay[5]; // rv 0 + assign PIPETX3EQCOEFF_in[6] = (PIPETX3EQCOEFF[6] !== 1'bz) && PIPETX3EQCOEFF_delay[6]; // rv 0 + assign PIPETX3EQCOEFF_in[7] = (PIPETX3EQCOEFF[7] !== 1'bz) && PIPETX3EQCOEFF_delay[7]; // rv 0 + assign PIPETX3EQCOEFF_in[8] = (PIPETX3EQCOEFF[8] !== 1'bz) && PIPETX3EQCOEFF_delay[8]; // rv 0 + assign PIPETX3EQCOEFF_in[9] = (PIPETX3EQCOEFF[9] !== 1'bz) && PIPETX3EQCOEFF_delay[9]; // rv 0 + assign PIPETX3EQDONE_in = (PIPETX3EQDONE !== 1'bz) && PIPETX3EQDONE_delay; // rv 0 + assign PIPETX4EQCOEFF_in[0] = (PIPETX4EQCOEFF[0] !== 1'bz) && PIPETX4EQCOEFF_delay[0]; // rv 0 + assign PIPETX4EQCOEFF_in[10] = (PIPETX4EQCOEFF[10] !== 1'bz) && PIPETX4EQCOEFF_delay[10]; // rv 0 + assign PIPETX4EQCOEFF_in[11] = (PIPETX4EQCOEFF[11] !== 1'bz) && PIPETX4EQCOEFF_delay[11]; // rv 0 + assign PIPETX4EQCOEFF_in[12] = (PIPETX4EQCOEFF[12] !== 1'bz) && PIPETX4EQCOEFF_delay[12]; // rv 0 + assign PIPETX4EQCOEFF_in[13] = (PIPETX4EQCOEFF[13] !== 1'bz) && PIPETX4EQCOEFF_delay[13]; // rv 0 + assign PIPETX4EQCOEFF_in[14] = (PIPETX4EQCOEFF[14] !== 1'bz) && PIPETX4EQCOEFF_delay[14]; // rv 0 + assign PIPETX4EQCOEFF_in[15] = (PIPETX4EQCOEFF[15] !== 1'bz) && PIPETX4EQCOEFF_delay[15]; // rv 0 + assign PIPETX4EQCOEFF_in[16] = (PIPETX4EQCOEFF[16] !== 1'bz) && PIPETX4EQCOEFF_delay[16]; // rv 0 + assign PIPETX4EQCOEFF_in[17] = (PIPETX4EQCOEFF[17] !== 1'bz) && PIPETX4EQCOEFF_delay[17]; // rv 0 + assign PIPETX4EQCOEFF_in[1] = (PIPETX4EQCOEFF[1] !== 1'bz) && PIPETX4EQCOEFF_delay[1]; // rv 0 + assign PIPETX4EQCOEFF_in[2] = (PIPETX4EQCOEFF[2] !== 1'bz) && PIPETX4EQCOEFF_delay[2]; // rv 0 + assign PIPETX4EQCOEFF_in[3] = (PIPETX4EQCOEFF[3] !== 1'bz) && PIPETX4EQCOEFF_delay[3]; // rv 0 + assign PIPETX4EQCOEFF_in[4] = (PIPETX4EQCOEFF[4] !== 1'bz) && PIPETX4EQCOEFF_delay[4]; // rv 0 + assign PIPETX4EQCOEFF_in[5] = (PIPETX4EQCOEFF[5] !== 1'bz) && PIPETX4EQCOEFF_delay[5]; // rv 0 + assign PIPETX4EQCOEFF_in[6] = (PIPETX4EQCOEFF[6] !== 1'bz) && PIPETX4EQCOEFF_delay[6]; // rv 0 + assign PIPETX4EQCOEFF_in[7] = (PIPETX4EQCOEFF[7] !== 1'bz) && PIPETX4EQCOEFF_delay[7]; // rv 0 + assign PIPETX4EQCOEFF_in[8] = (PIPETX4EQCOEFF[8] !== 1'bz) && PIPETX4EQCOEFF_delay[8]; // rv 0 + assign PIPETX4EQCOEFF_in[9] = (PIPETX4EQCOEFF[9] !== 1'bz) && PIPETX4EQCOEFF_delay[9]; // rv 0 + assign PIPETX4EQDONE_in = (PIPETX4EQDONE !== 1'bz) && PIPETX4EQDONE_delay; // rv 0 + assign PIPETX5EQCOEFF_in[0] = (PIPETX5EQCOEFF[0] !== 1'bz) && PIPETX5EQCOEFF_delay[0]; // rv 0 + assign PIPETX5EQCOEFF_in[10] = (PIPETX5EQCOEFF[10] !== 1'bz) && PIPETX5EQCOEFF_delay[10]; // rv 0 + assign PIPETX5EQCOEFF_in[11] = (PIPETX5EQCOEFF[11] !== 1'bz) && PIPETX5EQCOEFF_delay[11]; // rv 0 + assign PIPETX5EQCOEFF_in[12] = (PIPETX5EQCOEFF[12] !== 1'bz) && PIPETX5EQCOEFF_delay[12]; // rv 0 + assign PIPETX5EQCOEFF_in[13] = (PIPETX5EQCOEFF[13] !== 1'bz) && PIPETX5EQCOEFF_delay[13]; // rv 0 + assign PIPETX5EQCOEFF_in[14] = (PIPETX5EQCOEFF[14] !== 1'bz) && PIPETX5EQCOEFF_delay[14]; // rv 0 + assign PIPETX5EQCOEFF_in[15] = (PIPETX5EQCOEFF[15] !== 1'bz) && PIPETX5EQCOEFF_delay[15]; // rv 0 + assign PIPETX5EQCOEFF_in[16] = (PIPETX5EQCOEFF[16] !== 1'bz) && PIPETX5EQCOEFF_delay[16]; // rv 0 + assign PIPETX5EQCOEFF_in[17] = (PIPETX5EQCOEFF[17] !== 1'bz) && PIPETX5EQCOEFF_delay[17]; // rv 0 + assign PIPETX5EQCOEFF_in[1] = (PIPETX5EQCOEFF[1] !== 1'bz) && PIPETX5EQCOEFF_delay[1]; // rv 0 + assign PIPETX5EQCOEFF_in[2] = (PIPETX5EQCOEFF[2] !== 1'bz) && PIPETX5EQCOEFF_delay[2]; // rv 0 + assign PIPETX5EQCOEFF_in[3] = (PIPETX5EQCOEFF[3] !== 1'bz) && PIPETX5EQCOEFF_delay[3]; // rv 0 + assign PIPETX5EQCOEFF_in[4] = (PIPETX5EQCOEFF[4] !== 1'bz) && PIPETX5EQCOEFF_delay[4]; // rv 0 + assign PIPETX5EQCOEFF_in[5] = (PIPETX5EQCOEFF[5] !== 1'bz) && PIPETX5EQCOEFF_delay[5]; // rv 0 + assign PIPETX5EQCOEFF_in[6] = (PIPETX5EQCOEFF[6] !== 1'bz) && PIPETX5EQCOEFF_delay[6]; // rv 0 + assign PIPETX5EQCOEFF_in[7] = (PIPETX5EQCOEFF[7] !== 1'bz) && PIPETX5EQCOEFF_delay[7]; // rv 0 + assign PIPETX5EQCOEFF_in[8] = (PIPETX5EQCOEFF[8] !== 1'bz) && PIPETX5EQCOEFF_delay[8]; // rv 0 + assign PIPETX5EQCOEFF_in[9] = (PIPETX5EQCOEFF[9] !== 1'bz) && PIPETX5EQCOEFF_delay[9]; // rv 0 + assign PIPETX5EQDONE_in = (PIPETX5EQDONE !== 1'bz) && PIPETX5EQDONE_delay; // rv 0 + assign PIPETX6EQCOEFF_in[0] = (PIPETX6EQCOEFF[0] !== 1'bz) && PIPETX6EQCOEFF_delay[0]; // rv 0 + assign PIPETX6EQCOEFF_in[10] = (PIPETX6EQCOEFF[10] !== 1'bz) && PIPETX6EQCOEFF_delay[10]; // rv 0 + assign PIPETX6EQCOEFF_in[11] = (PIPETX6EQCOEFF[11] !== 1'bz) && PIPETX6EQCOEFF_delay[11]; // rv 0 + assign PIPETX6EQCOEFF_in[12] = (PIPETX6EQCOEFF[12] !== 1'bz) && PIPETX6EQCOEFF_delay[12]; // rv 0 + assign PIPETX6EQCOEFF_in[13] = (PIPETX6EQCOEFF[13] !== 1'bz) && PIPETX6EQCOEFF_delay[13]; // rv 0 + assign PIPETX6EQCOEFF_in[14] = (PIPETX6EQCOEFF[14] !== 1'bz) && PIPETX6EQCOEFF_delay[14]; // rv 0 + assign PIPETX6EQCOEFF_in[15] = (PIPETX6EQCOEFF[15] !== 1'bz) && PIPETX6EQCOEFF_delay[15]; // rv 0 + assign PIPETX6EQCOEFF_in[16] = (PIPETX6EQCOEFF[16] !== 1'bz) && PIPETX6EQCOEFF_delay[16]; // rv 0 + assign PIPETX6EQCOEFF_in[17] = (PIPETX6EQCOEFF[17] !== 1'bz) && PIPETX6EQCOEFF_delay[17]; // rv 0 + assign PIPETX6EQCOEFF_in[1] = (PIPETX6EQCOEFF[1] !== 1'bz) && PIPETX6EQCOEFF_delay[1]; // rv 0 + assign PIPETX6EQCOEFF_in[2] = (PIPETX6EQCOEFF[2] !== 1'bz) && PIPETX6EQCOEFF_delay[2]; // rv 0 + assign PIPETX6EQCOEFF_in[3] = (PIPETX6EQCOEFF[3] !== 1'bz) && PIPETX6EQCOEFF_delay[3]; // rv 0 + assign PIPETX6EQCOEFF_in[4] = (PIPETX6EQCOEFF[4] !== 1'bz) && PIPETX6EQCOEFF_delay[4]; // rv 0 + assign PIPETX6EQCOEFF_in[5] = (PIPETX6EQCOEFF[5] !== 1'bz) && PIPETX6EQCOEFF_delay[5]; // rv 0 + assign PIPETX6EQCOEFF_in[6] = (PIPETX6EQCOEFF[6] !== 1'bz) && PIPETX6EQCOEFF_delay[6]; // rv 0 + assign PIPETX6EQCOEFF_in[7] = (PIPETX6EQCOEFF[7] !== 1'bz) && PIPETX6EQCOEFF_delay[7]; // rv 0 + assign PIPETX6EQCOEFF_in[8] = (PIPETX6EQCOEFF[8] !== 1'bz) && PIPETX6EQCOEFF_delay[8]; // rv 0 + assign PIPETX6EQCOEFF_in[9] = (PIPETX6EQCOEFF[9] !== 1'bz) && PIPETX6EQCOEFF_delay[9]; // rv 0 + assign PIPETX6EQDONE_in = (PIPETX6EQDONE !== 1'bz) && PIPETX6EQDONE_delay; // rv 0 + assign PIPETX7EQCOEFF_in[0] = (PIPETX7EQCOEFF[0] !== 1'bz) && PIPETX7EQCOEFF_delay[0]; // rv 0 + assign PIPETX7EQCOEFF_in[10] = (PIPETX7EQCOEFF[10] !== 1'bz) && PIPETX7EQCOEFF_delay[10]; // rv 0 + assign PIPETX7EQCOEFF_in[11] = (PIPETX7EQCOEFF[11] !== 1'bz) && PIPETX7EQCOEFF_delay[11]; // rv 0 + assign PIPETX7EQCOEFF_in[12] = (PIPETX7EQCOEFF[12] !== 1'bz) && PIPETX7EQCOEFF_delay[12]; // rv 0 + assign PIPETX7EQCOEFF_in[13] = (PIPETX7EQCOEFF[13] !== 1'bz) && PIPETX7EQCOEFF_delay[13]; // rv 0 + assign PIPETX7EQCOEFF_in[14] = (PIPETX7EQCOEFF[14] !== 1'bz) && PIPETX7EQCOEFF_delay[14]; // rv 0 + assign PIPETX7EQCOEFF_in[15] = (PIPETX7EQCOEFF[15] !== 1'bz) && PIPETX7EQCOEFF_delay[15]; // rv 0 + assign PIPETX7EQCOEFF_in[16] = (PIPETX7EQCOEFF[16] !== 1'bz) && PIPETX7EQCOEFF_delay[16]; // rv 0 + assign PIPETX7EQCOEFF_in[17] = (PIPETX7EQCOEFF[17] !== 1'bz) && PIPETX7EQCOEFF_delay[17]; // rv 0 + assign PIPETX7EQCOEFF_in[1] = (PIPETX7EQCOEFF[1] !== 1'bz) && PIPETX7EQCOEFF_delay[1]; // rv 0 + assign PIPETX7EQCOEFF_in[2] = (PIPETX7EQCOEFF[2] !== 1'bz) && PIPETX7EQCOEFF_delay[2]; // rv 0 + assign PIPETX7EQCOEFF_in[3] = (PIPETX7EQCOEFF[3] !== 1'bz) && PIPETX7EQCOEFF_delay[3]; // rv 0 + assign PIPETX7EQCOEFF_in[4] = (PIPETX7EQCOEFF[4] !== 1'bz) && PIPETX7EQCOEFF_delay[4]; // rv 0 + assign PIPETX7EQCOEFF_in[5] = (PIPETX7EQCOEFF[5] !== 1'bz) && PIPETX7EQCOEFF_delay[5]; // rv 0 + assign PIPETX7EQCOEFF_in[6] = (PIPETX7EQCOEFF[6] !== 1'bz) && PIPETX7EQCOEFF_delay[6]; // rv 0 + assign PIPETX7EQCOEFF_in[7] = (PIPETX7EQCOEFF[7] !== 1'bz) && PIPETX7EQCOEFF_delay[7]; // rv 0 + assign PIPETX7EQCOEFF_in[8] = (PIPETX7EQCOEFF[8] !== 1'bz) && PIPETX7EQCOEFF_delay[8]; // rv 0 + assign PIPETX7EQCOEFF_in[9] = (PIPETX7EQCOEFF[9] !== 1'bz) && PIPETX7EQCOEFF_delay[9]; // rv 0 + assign PIPETX7EQDONE_in = (PIPETX7EQDONE !== 1'bz) && PIPETX7EQDONE_delay; // rv 0 + assign PLEQRESETEIEOSCOUNT_in = (PLEQRESETEIEOSCOUNT !== 1'bz) && PLEQRESETEIEOSCOUNT_delay; // rv 0 + assign PLGEN2UPSTREAMPREFERDEEMPH_in = (PLGEN2UPSTREAMPREFERDEEMPH !== 1'bz) && PLGEN2UPSTREAMPREFERDEEMPH_delay; // rv 0 + assign RESETN_in = (RESETN !== 1'bz) && RESETN_delay; // rv 0 + assign SAXISCCTDATA_in[0] = (SAXISCCTDATA[0] === 1'bz) || SAXISCCTDATA_delay[0]; // rv 1 + assign SAXISCCTDATA_in[100] = (SAXISCCTDATA[100] === 1'bz) || SAXISCCTDATA_delay[100]; // rv 1 + assign SAXISCCTDATA_in[101] = (SAXISCCTDATA[101] === 1'bz) || SAXISCCTDATA_delay[101]; // rv 1 + assign SAXISCCTDATA_in[102] = (SAXISCCTDATA[102] === 1'bz) || SAXISCCTDATA_delay[102]; // rv 1 + assign SAXISCCTDATA_in[103] = (SAXISCCTDATA[103] === 1'bz) || SAXISCCTDATA_delay[103]; // rv 1 + assign SAXISCCTDATA_in[104] = (SAXISCCTDATA[104] === 1'bz) || SAXISCCTDATA_delay[104]; // rv 1 + assign SAXISCCTDATA_in[105] = (SAXISCCTDATA[105] === 1'bz) || SAXISCCTDATA_delay[105]; // rv 1 + assign SAXISCCTDATA_in[106] = (SAXISCCTDATA[106] === 1'bz) || SAXISCCTDATA_delay[106]; // rv 1 + assign SAXISCCTDATA_in[107] = (SAXISCCTDATA[107] === 1'bz) || SAXISCCTDATA_delay[107]; // rv 1 + assign SAXISCCTDATA_in[108] = (SAXISCCTDATA[108] === 1'bz) || SAXISCCTDATA_delay[108]; // rv 1 + assign SAXISCCTDATA_in[109] = (SAXISCCTDATA[109] === 1'bz) || SAXISCCTDATA_delay[109]; // rv 1 + assign SAXISCCTDATA_in[10] = (SAXISCCTDATA[10] === 1'bz) || SAXISCCTDATA_delay[10]; // rv 1 + assign SAXISCCTDATA_in[110] = (SAXISCCTDATA[110] === 1'bz) || SAXISCCTDATA_delay[110]; // rv 1 + assign SAXISCCTDATA_in[111] = (SAXISCCTDATA[111] === 1'bz) || SAXISCCTDATA_delay[111]; // rv 1 + assign SAXISCCTDATA_in[112] = (SAXISCCTDATA[112] === 1'bz) || SAXISCCTDATA_delay[112]; // rv 1 + assign SAXISCCTDATA_in[113] = (SAXISCCTDATA[113] === 1'bz) || SAXISCCTDATA_delay[113]; // rv 1 + assign SAXISCCTDATA_in[114] = (SAXISCCTDATA[114] === 1'bz) || SAXISCCTDATA_delay[114]; // rv 1 + assign SAXISCCTDATA_in[115] = (SAXISCCTDATA[115] === 1'bz) || SAXISCCTDATA_delay[115]; // rv 1 + assign SAXISCCTDATA_in[116] = (SAXISCCTDATA[116] === 1'bz) || SAXISCCTDATA_delay[116]; // rv 1 + assign SAXISCCTDATA_in[117] = (SAXISCCTDATA[117] === 1'bz) || SAXISCCTDATA_delay[117]; // rv 1 + assign SAXISCCTDATA_in[118] = (SAXISCCTDATA[118] === 1'bz) || SAXISCCTDATA_delay[118]; // rv 1 + assign SAXISCCTDATA_in[119] = (SAXISCCTDATA[119] === 1'bz) || SAXISCCTDATA_delay[119]; // rv 1 + assign SAXISCCTDATA_in[11] = (SAXISCCTDATA[11] === 1'bz) || SAXISCCTDATA_delay[11]; // rv 1 + assign SAXISCCTDATA_in[120] = (SAXISCCTDATA[120] === 1'bz) || SAXISCCTDATA_delay[120]; // rv 1 + assign SAXISCCTDATA_in[121] = (SAXISCCTDATA[121] === 1'bz) || SAXISCCTDATA_delay[121]; // rv 1 + assign SAXISCCTDATA_in[122] = (SAXISCCTDATA[122] === 1'bz) || SAXISCCTDATA_delay[122]; // rv 1 + assign SAXISCCTDATA_in[123] = (SAXISCCTDATA[123] === 1'bz) || SAXISCCTDATA_delay[123]; // rv 1 + assign SAXISCCTDATA_in[124] = (SAXISCCTDATA[124] === 1'bz) || SAXISCCTDATA_delay[124]; // rv 1 + assign SAXISCCTDATA_in[125] = (SAXISCCTDATA[125] === 1'bz) || SAXISCCTDATA_delay[125]; // rv 1 + assign SAXISCCTDATA_in[126] = (SAXISCCTDATA[126] === 1'bz) || SAXISCCTDATA_delay[126]; // rv 1 + assign SAXISCCTDATA_in[127] = (SAXISCCTDATA[127] === 1'bz) || SAXISCCTDATA_delay[127]; // rv 1 + assign SAXISCCTDATA_in[128] = (SAXISCCTDATA[128] === 1'bz) || SAXISCCTDATA_delay[128]; // rv 1 + assign SAXISCCTDATA_in[129] = (SAXISCCTDATA[129] === 1'bz) || SAXISCCTDATA_delay[129]; // rv 1 + assign SAXISCCTDATA_in[12] = (SAXISCCTDATA[12] === 1'bz) || SAXISCCTDATA_delay[12]; // rv 1 + assign SAXISCCTDATA_in[130] = (SAXISCCTDATA[130] === 1'bz) || SAXISCCTDATA_delay[130]; // rv 1 + assign SAXISCCTDATA_in[131] = (SAXISCCTDATA[131] === 1'bz) || SAXISCCTDATA_delay[131]; // rv 1 + assign SAXISCCTDATA_in[132] = (SAXISCCTDATA[132] === 1'bz) || SAXISCCTDATA_delay[132]; // rv 1 + assign SAXISCCTDATA_in[133] = (SAXISCCTDATA[133] === 1'bz) || SAXISCCTDATA_delay[133]; // rv 1 + assign SAXISCCTDATA_in[134] = (SAXISCCTDATA[134] === 1'bz) || SAXISCCTDATA_delay[134]; // rv 1 + assign SAXISCCTDATA_in[135] = (SAXISCCTDATA[135] === 1'bz) || SAXISCCTDATA_delay[135]; // rv 1 + assign SAXISCCTDATA_in[136] = (SAXISCCTDATA[136] === 1'bz) || SAXISCCTDATA_delay[136]; // rv 1 + assign SAXISCCTDATA_in[137] = (SAXISCCTDATA[137] === 1'bz) || SAXISCCTDATA_delay[137]; // rv 1 + assign SAXISCCTDATA_in[138] = (SAXISCCTDATA[138] === 1'bz) || SAXISCCTDATA_delay[138]; // rv 1 + assign SAXISCCTDATA_in[139] = (SAXISCCTDATA[139] === 1'bz) || SAXISCCTDATA_delay[139]; // rv 1 + assign SAXISCCTDATA_in[13] = (SAXISCCTDATA[13] === 1'bz) || SAXISCCTDATA_delay[13]; // rv 1 + assign SAXISCCTDATA_in[140] = (SAXISCCTDATA[140] === 1'bz) || SAXISCCTDATA_delay[140]; // rv 1 + assign SAXISCCTDATA_in[141] = (SAXISCCTDATA[141] === 1'bz) || SAXISCCTDATA_delay[141]; // rv 1 + assign SAXISCCTDATA_in[142] = (SAXISCCTDATA[142] === 1'bz) || SAXISCCTDATA_delay[142]; // rv 1 + assign SAXISCCTDATA_in[143] = (SAXISCCTDATA[143] === 1'bz) || SAXISCCTDATA_delay[143]; // rv 1 + assign SAXISCCTDATA_in[144] = (SAXISCCTDATA[144] === 1'bz) || SAXISCCTDATA_delay[144]; // rv 1 + assign SAXISCCTDATA_in[145] = (SAXISCCTDATA[145] === 1'bz) || SAXISCCTDATA_delay[145]; // rv 1 + assign SAXISCCTDATA_in[146] = (SAXISCCTDATA[146] === 1'bz) || SAXISCCTDATA_delay[146]; // rv 1 + assign SAXISCCTDATA_in[147] = (SAXISCCTDATA[147] === 1'bz) || SAXISCCTDATA_delay[147]; // rv 1 + assign SAXISCCTDATA_in[148] = (SAXISCCTDATA[148] === 1'bz) || SAXISCCTDATA_delay[148]; // rv 1 + assign SAXISCCTDATA_in[149] = (SAXISCCTDATA[149] === 1'bz) || SAXISCCTDATA_delay[149]; // rv 1 + assign SAXISCCTDATA_in[14] = (SAXISCCTDATA[14] === 1'bz) || SAXISCCTDATA_delay[14]; // rv 1 + assign SAXISCCTDATA_in[150] = (SAXISCCTDATA[150] === 1'bz) || SAXISCCTDATA_delay[150]; // rv 1 + assign SAXISCCTDATA_in[151] = (SAXISCCTDATA[151] === 1'bz) || SAXISCCTDATA_delay[151]; // rv 1 + assign SAXISCCTDATA_in[152] = (SAXISCCTDATA[152] === 1'bz) || SAXISCCTDATA_delay[152]; // rv 1 + assign SAXISCCTDATA_in[153] = (SAXISCCTDATA[153] === 1'bz) || SAXISCCTDATA_delay[153]; // rv 1 + assign SAXISCCTDATA_in[154] = (SAXISCCTDATA[154] === 1'bz) || SAXISCCTDATA_delay[154]; // rv 1 + assign SAXISCCTDATA_in[155] = (SAXISCCTDATA[155] === 1'bz) || SAXISCCTDATA_delay[155]; // rv 1 + assign SAXISCCTDATA_in[156] = (SAXISCCTDATA[156] === 1'bz) || SAXISCCTDATA_delay[156]; // rv 1 + assign SAXISCCTDATA_in[157] = (SAXISCCTDATA[157] === 1'bz) || SAXISCCTDATA_delay[157]; // rv 1 + assign SAXISCCTDATA_in[158] = (SAXISCCTDATA[158] === 1'bz) || SAXISCCTDATA_delay[158]; // rv 1 + assign SAXISCCTDATA_in[159] = (SAXISCCTDATA[159] === 1'bz) || SAXISCCTDATA_delay[159]; // rv 1 + assign SAXISCCTDATA_in[15] = (SAXISCCTDATA[15] === 1'bz) || SAXISCCTDATA_delay[15]; // rv 1 + assign SAXISCCTDATA_in[160] = (SAXISCCTDATA[160] === 1'bz) || SAXISCCTDATA_delay[160]; // rv 1 + assign SAXISCCTDATA_in[161] = (SAXISCCTDATA[161] === 1'bz) || SAXISCCTDATA_delay[161]; // rv 1 + assign SAXISCCTDATA_in[162] = (SAXISCCTDATA[162] === 1'bz) || SAXISCCTDATA_delay[162]; // rv 1 + assign SAXISCCTDATA_in[163] = (SAXISCCTDATA[163] === 1'bz) || SAXISCCTDATA_delay[163]; // rv 1 + assign SAXISCCTDATA_in[164] = (SAXISCCTDATA[164] === 1'bz) || SAXISCCTDATA_delay[164]; // rv 1 + assign SAXISCCTDATA_in[165] = (SAXISCCTDATA[165] === 1'bz) || SAXISCCTDATA_delay[165]; // rv 1 + assign SAXISCCTDATA_in[166] = (SAXISCCTDATA[166] === 1'bz) || SAXISCCTDATA_delay[166]; // rv 1 + assign SAXISCCTDATA_in[167] = (SAXISCCTDATA[167] === 1'bz) || SAXISCCTDATA_delay[167]; // rv 1 + assign SAXISCCTDATA_in[168] = (SAXISCCTDATA[168] === 1'bz) || SAXISCCTDATA_delay[168]; // rv 1 + assign SAXISCCTDATA_in[169] = (SAXISCCTDATA[169] === 1'bz) || SAXISCCTDATA_delay[169]; // rv 1 + assign SAXISCCTDATA_in[16] = (SAXISCCTDATA[16] === 1'bz) || SAXISCCTDATA_delay[16]; // rv 1 + assign SAXISCCTDATA_in[170] = (SAXISCCTDATA[170] === 1'bz) || SAXISCCTDATA_delay[170]; // rv 1 + assign SAXISCCTDATA_in[171] = (SAXISCCTDATA[171] === 1'bz) || SAXISCCTDATA_delay[171]; // rv 1 + assign SAXISCCTDATA_in[172] = (SAXISCCTDATA[172] === 1'bz) || SAXISCCTDATA_delay[172]; // rv 1 + assign SAXISCCTDATA_in[173] = (SAXISCCTDATA[173] === 1'bz) || SAXISCCTDATA_delay[173]; // rv 1 + assign SAXISCCTDATA_in[174] = (SAXISCCTDATA[174] === 1'bz) || SAXISCCTDATA_delay[174]; // rv 1 + assign SAXISCCTDATA_in[175] = (SAXISCCTDATA[175] === 1'bz) || SAXISCCTDATA_delay[175]; // rv 1 + assign SAXISCCTDATA_in[176] = (SAXISCCTDATA[176] === 1'bz) || SAXISCCTDATA_delay[176]; // rv 1 + assign SAXISCCTDATA_in[177] = (SAXISCCTDATA[177] === 1'bz) || SAXISCCTDATA_delay[177]; // rv 1 + assign SAXISCCTDATA_in[178] = (SAXISCCTDATA[178] === 1'bz) || SAXISCCTDATA_delay[178]; // rv 1 + assign SAXISCCTDATA_in[179] = (SAXISCCTDATA[179] === 1'bz) || SAXISCCTDATA_delay[179]; // rv 1 + assign SAXISCCTDATA_in[17] = (SAXISCCTDATA[17] === 1'bz) || SAXISCCTDATA_delay[17]; // rv 1 + assign SAXISCCTDATA_in[180] = (SAXISCCTDATA[180] === 1'bz) || SAXISCCTDATA_delay[180]; // rv 1 + assign SAXISCCTDATA_in[181] = (SAXISCCTDATA[181] === 1'bz) || SAXISCCTDATA_delay[181]; // rv 1 + assign SAXISCCTDATA_in[182] = (SAXISCCTDATA[182] === 1'bz) || SAXISCCTDATA_delay[182]; // rv 1 + assign SAXISCCTDATA_in[183] = (SAXISCCTDATA[183] === 1'bz) || SAXISCCTDATA_delay[183]; // rv 1 + assign SAXISCCTDATA_in[184] = (SAXISCCTDATA[184] === 1'bz) || SAXISCCTDATA_delay[184]; // rv 1 + assign SAXISCCTDATA_in[185] = (SAXISCCTDATA[185] === 1'bz) || SAXISCCTDATA_delay[185]; // rv 1 + assign SAXISCCTDATA_in[186] = (SAXISCCTDATA[186] === 1'bz) || SAXISCCTDATA_delay[186]; // rv 1 + assign SAXISCCTDATA_in[187] = (SAXISCCTDATA[187] === 1'bz) || SAXISCCTDATA_delay[187]; // rv 1 + assign SAXISCCTDATA_in[188] = (SAXISCCTDATA[188] === 1'bz) || SAXISCCTDATA_delay[188]; // rv 1 + assign SAXISCCTDATA_in[189] = (SAXISCCTDATA[189] === 1'bz) || SAXISCCTDATA_delay[189]; // rv 1 + assign SAXISCCTDATA_in[18] = (SAXISCCTDATA[18] === 1'bz) || SAXISCCTDATA_delay[18]; // rv 1 + assign SAXISCCTDATA_in[190] = (SAXISCCTDATA[190] === 1'bz) || SAXISCCTDATA_delay[190]; // rv 1 + assign SAXISCCTDATA_in[191] = (SAXISCCTDATA[191] === 1'bz) || SAXISCCTDATA_delay[191]; // rv 1 + assign SAXISCCTDATA_in[192] = (SAXISCCTDATA[192] === 1'bz) || SAXISCCTDATA_delay[192]; // rv 1 + assign SAXISCCTDATA_in[193] = (SAXISCCTDATA[193] === 1'bz) || SAXISCCTDATA_delay[193]; // rv 1 + assign SAXISCCTDATA_in[194] = (SAXISCCTDATA[194] === 1'bz) || SAXISCCTDATA_delay[194]; // rv 1 + assign SAXISCCTDATA_in[195] = (SAXISCCTDATA[195] === 1'bz) || SAXISCCTDATA_delay[195]; // rv 1 + assign SAXISCCTDATA_in[196] = (SAXISCCTDATA[196] === 1'bz) || SAXISCCTDATA_delay[196]; // rv 1 + assign SAXISCCTDATA_in[197] = (SAXISCCTDATA[197] === 1'bz) || SAXISCCTDATA_delay[197]; // rv 1 + assign SAXISCCTDATA_in[198] = (SAXISCCTDATA[198] === 1'bz) || SAXISCCTDATA_delay[198]; // rv 1 + assign SAXISCCTDATA_in[199] = (SAXISCCTDATA[199] === 1'bz) || SAXISCCTDATA_delay[199]; // rv 1 + assign SAXISCCTDATA_in[19] = (SAXISCCTDATA[19] === 1'bz) || SAXISCCTDATA_delay[19]; // rv 1 + assign SAXISCCTDATA_in[1] = (SAXISCCTDATA[1] === 1'bz) || SAXISCCTDATA_delay[1]; // rv 1 + assign SAXISCCTDATA_in[200] = (SAXISCCTDATA[200] === 1'bz) || SAXISCCTDATA_delay[200]; // rv 1 + assign SAXISCCTDATA_in[201] = (SAXISCCTDATA[201] === 1'bz) || SAXISCCTDATA_delay[201]; // rv 1 + assign SAXISCCTDATA_in[202] = (SAXISCCTDATA[202] === 1'bz) || SAXISCCTDATA_delay[202]; // rv 1 + assign SAXISCCTDATA_in[203] = (SAXISCCTDATA[203] === 1'bz) || SAXISCCTDATA_delay[203]; // rv 1 + assign SAXISCCTDATA_in[204] = (SAXISCCTDATA[204] === 1'bz) || SAXISCCTDATA_delay[204]; // rv 1 + assign SAXISCCTDATA_in[205] = (SAXISCCTDATA[205] === 1'bz) || SAXISCCTDATA_delay[205]; // rv 1 + assign SAXISCCTDATA_in[206] = (SAXISCCTDATA[206] === 1'bz) || SAXISCCTDATA_delay[206]; // rv 1 + assign SAXISCCTDATA_in[207] = (SAXISCCTDATA[207] === 1'bz) || SAXISCCTDATA_delay[207]; // rv 1 + assign SAXISCCTDATA_in[208] = (SAXISCCTDATA[208] === 1'bz) || SAXISCCTDATA_delay[208]; // rv 1 + assign SAXISCCTDATA_in[209] = (SAXISCCTDATA[209] === 1'bz) || SAXISCCTDATA_delay[209]; // rv 1 + assign SAXISCCTDATA_in[20] = (SAXISCCTDATA[20] === 1'bz) || SAXISCCTDATA_delay[20]; // rv 1 + assign SAXISCCTDATA_in[210] = (SAXISCCTDATA[210] === 1'bz) || SAXISCCTDATA_delay[210]; // rv 1 + assign SAXISCCTDATA_in[211] = (SAXISCCTDATA[211] === 1'bz) || SAXISCCTDATA_delay[211]; // rv 1 + assign SAXISCCTDATA_in[212] = (SAXISCCTDATA[212] === 1'bz) || SAXISCCTDATA_delay[212]; // rv 1 + assign SAXISCCTDATA_in[213] = (SAXISCCTDATA[213] === 1'bz) || SAXISCCTDATA_delay[213]; // rv 1 + assign SAXISCCTDATA_in[214] = (SAXISCCTDATA[214] === 1'bz) || SAXISCCTDATA_delay[214]; // rv 1 + assign SAXISCCTDATA_in[215] = (SAXISCCTDATA[215] === 1'bz) || SAXISCCTDATA_delay[215]; // rv 1 + assign SAXISCCTDATA_in[216] = (SAXISCCTDATA[216] === 1'bz) || SAXISCCTDATA_delay[216]; // rv 1 + assign SAXISCCTDATA_in[217] = (SAXISCCTDATA[217] === 1'bz) || SAXISCCTDATA_delay[217]; // rv 1 + assign SAXISCCTDATA_in[218] = (SAXISCCTDATA[218] === 1'bz) || SAXISCCTDATA_delay[218]; // rv 1 + assign SAXISCCTDATA_in[219] = (SAXISCCTDATA[219] === 1'bz) || SAXISCCTDATA_delay[219]; // rv 1 + assign SAXISCCTDATA_in[21] = (SAXISCCTDATA[21] === 1'bz) || SAXISCCTDATA_delay[21]; // rv 1 + assign SAXISCCTDATA_in[220] = (SAXISCCTDATA[220] === 1'bz) || SAXISCCTDATA_delay[220]; // rv 1 + assign SAXISCCTDATA_in[221] = (SAXISCCTDATA[221] === 1'bz) || SAXISCCTDATA_delay[221]; // rv 1 + assign SAXISCCTDATA_in[222] = (SAXISCCTDATA[222] === 1'bz) || SAXISCCTDATA_delay[222]; // rv 1 + assign SAXISCCTDATA_in[223] = (SAXISCCTDATA[223] === 1'bz) || SAXISCCTDATA_delay[223]; // rv 1 + assign SAXISCCTDATA_in[224] = (SAXISCCTDATA[224] === 1'bz) || SAXISCCTDATA_delay[224]; // rv 1 + assign SAXISCCTDATA_in[225] = (SAXISCCTDATA[225] === 1'bz) || SAXISCCTDATA_delay[225]; // rv 1 + assign SAXISCCTDATA_in[226] = (SAXISCCTDATA[226] === 1'bz) || SAXISCCTDATA_delay[226]; // rv 1 + assign SAXISCCTDATA_in[227] = (SAXISCCTDATA[227] === 1'bz) || SAXISCCTDATA_delay[227]; // rv 1 + assign SAXISCCTDATA_in[228] = (SAXISCCTDATA[228] === 1'bz) || SAXISCCTDATA_delay[228]; // rv 1 + assign SAXISCCTDATA_in[229] = (SAXISCCTDATA[229] === 1'bz) || SAXISCCTDATA_delay[229]; // rv 1 + assign SAXISCCTDATA_in[22] = (SAXISCCTDATA[22] === 1'bz) || SAXISCCTDATA_delay[22]; // rv 1 + assign SAXISCCTDATA_in[230] = (SAXISCCTDATA[230] === 1'bz) || SAXISCCTDATA_delay[230]; // rv 1 + assign SAXISCCTDATA_in[231] = (SAXISCCTDATA[231] === 1'bz) || SAXISCCTDATA_delay[231]; // rv 1 + assign SAXISCCTDATA_in[232] = (SAXISCCTDATA[232] === 1'bz) || SAXISCCTDATA_delay[232]; // rv 1 + assign SAXISCCTDATA_in[233] = (SAXISCCTDATA[233] === 1'bz) || SAXISCCTDATA_delay[233]; // rv 1 + assign SAXISCCTDATA_in[234] = (SAXISCCTDATA[234] === 1'bz) || SAXISCCTDATA_delay[234]; // rv 1 + assign SAXISCCTDATA_in[235] = (SAXISCCTDATA[235] === 1'bz) || SAXISCCTDATA_delay[235]; // rv 1 + assign SAXISCCTDATA_in[236] = (SAXISCCTDATA[236] === 1'bz) || SAXISCCTDATA_delay[236]; // rv 1 + assign SAXISCCTDATA_in[237] = (SAXISCCTDATA[237] === 1'bz) || SAXISCCTDATA_delay[237]; // rv 1 + assign SAXISCCTDATA_in[238] = (SAXISCCTDATA[238] === 1'bz) || SAXISCCTDATA_delay[238]; // rv 1 + assign SAXISCCTDATA_in[239] = (SAXISCCTDATA[239] === 1'bz) || SAXISCCTDATA_delay[239]; // rv 1 + assign SAXISCCTDATA_in[23] = (SAXISCCTDATA[23] === 1'bz) || SAXISCCTDATA_delay[23]; // rv 1 + assign SAXISCCTDATA_in[240] = (SAXISCCTDATA[240] === 1'bz) || SAXISCCTDATA_delay[240]; // rv 1 + assign SAXISCCTDATA_in[241] = (SAXISCCTDATA[241] === 1'bz) || SAXISCCTDATA_delay[241]; // rv 1 + assign SAXISCCTDATA_in[242] = (SAXISCCTDATA[242] === 1'bz) || SAXISCCTDATA_delay[242]; // rv 1 + assign SAXISCCTDATA_in[243] = (SAXISCCTDATA[243] === 1'bz) || SAXISCCTDATA_delay[243]; // rv 1 + assign SAXISCCTDATA_in[244] = (SAXISCCTDATA[244] === 1'bz) || SAXISCCTDATA_delay[244]; // rv 1 + assign SAXISCCTDATA_in[245] = (SAXISCCTDATA[245] === 1'bz) || SAXISCCTDATA_delay[245]; // rv 1 + assign SAXISCCTDATA_in[246] = (SAXISCCTDATA[246] === 1'bz) || SAXISCCTDATA_delay[246]; // rv 1 + assign SAXISCCTDATA_in[247] = (SAXISCCTDATA[247] === 1'bz) || SAXISCCTDATA_delay[247]; // rv 1 + assign SAXISCCTDATA_in[248] = (SAXISCCTDATA[248] === 1'bz) || SAXISCCTDATA_delay[248]; // rv 1 + assign SAXISCCTDATA_in[249] = (SAXISCCTDATA[249] === 1'bz) || SAXISCCTDATA_delay[249]; // rv 1 + assign SAXISCCTDATA_in[24] = (SAXISCCTDATA[24] === 1'bz) || SAXISCCTDATA_delay[24]; // rv 1 + assign SAXISCCTDATA_in[250] = (SAXISCCTDATA[250] === 1'bz) || SAXISCCTDATA_delay[250]; // rv 1 + assign SAXISCCTDATA_in[251] = (SAXISCCTDATA[251] === 1'bz) || SAXISCCTDATA_delay[251]; // rv 1 + assign SAXISCCTDATA_in[252] = (SAXISCCTDATA[252] === 1'bz) || SAXISCCTDATA_delay[252]; // rv 1 + assign SAXISCCTDATA_in[253] = (SAXISCCTDATA[253] === 1'bz) || SAXISCCTDATA_delay[253]; // rv 1 + assign SAXISCCTDATA_in[254] = (SAXISCCTDATA[254] === 1'bz) || SAXISCCTDATA_delay[254]; // rv 1 + assign SAXISCCTDATA_in[255] = (SAXISCCTDATA[255] === 1'bz) || SAXISCCTDATA_delay[255]; // rv 1 + assign SAXISCCTDATA_in[25] = (SAXISCCTDATA[25] === 1'bz) || SAXISCCTDATA_delay[25]; // rv 1 + assign SAXISCCTDATA_in[26] = (SAXISCCTDATA[26] === 1'bz) || SAXISCCTDATA_delay[26]; // rv 1 + assign SAXISCCTDATA_in[27] = (SAXISCCTDATA[27] === 1'bz) || SAXISCCTDATA_delay[27]; // rv 1 + assign SAXISCCTDATA_in[28] = (SAXISCCTDATA[28] === 1'bz) || SAXISCCTDATA_delay[28]; // rv 1 + assign SAXISCCTDATA_in[29] = (SAXISCCTDATA[29] === 1'bz) || SAXISCCTDATA_delay[29]; // rv 1 + assign SAXISCCTDATA_in[2] = (SAXISCCTDATA[2] === 1'bz) || SAXISCCTDATA_delay[2]; // rv 1 + assign SAXISCCTDATA_in[30] = (SAXISCCTDATA[30] === 1'bz) || SAXISCCTDATA_delay[30]; // rv 1 + assign SAXISCCTDATA_in[31] = (SAXISCCTDATA[31] === 1'bz) || SAXISCCTDATA_delay[31]; // rv 1 + assign SAXISCCTDATA_in[32] = (SAXISCCTDATA[32] === 1'bz) || SAXISCCTDATA_delay[32]; // rv 1 + assign SAXISCCTDATA_in[33] = (SAXISCCTDATA[33] === 1'bz) || SAXISCCTDATA_delay[33]; // rv 1 + assign SAXISCCTDATA_in[34] = (SAXISCCTDATA[34] === 1'bz) || SAXISCCTDATA_delay[34]; // rv 1 + assign SAXISCCTDATA_in[35] = (SAXISCCTDATA[35] === 1'bz) || SAXISCCTDATA_delay[35]; // rv 1 + assign SAXISCCTDATA_in[36] = (SAXISCCTDATA[36] === 1'bz) || SAXISCCTDATA_delay[36]; // rv 1 + assign SAXISCCTDATA_in[37] = (SAXISCCTDATA[37] === 1'bz) || SAXISCCTDATA_delay[37]; // rv 1 + assign SAXISCCTDATA_in[38] = (SAXISCCTDATA[38] === 1'bz) || SAXISCCTDATA_delay[38]; // rv 1 + assign SAXISCCTDATA_in[39] = (SAXISCCTDATA[39] === 1'bz) || SAXISCCTDATA_delay[39]; // rv 1 + assign SAXISCCTDATA_in[3] = (SAXISCCTDATA[3] === 1'bz) || SAXISCCTDATA_delay[3]; // rv 1 + assign SAXISCCTDATA_in[40] = (SAXISCCTDATA[40] === 1'bz) || SAXISCCTDATA_delay[40]; // rv 1 + assign SAXISCCTDATA_in[41] = (SAXISCCTDATA[41] === 1'bz) || SAXISCCTDATA_delay[41]; // rv 1 + assign SAXISCCTDATA_in[42] = (SAXISCCTDATA[42] === 1'bz) || SAXISCCTDATA_delay[42]; // rv 1 + assign SAXISCCTDATA_in[43] = (SAXISCCTDATA[43] === 1'bz) || SAXISCCTDATA_delay[43]; // rv 1 + assign SAXISCCTDATA_in[44] = (SAXISCCTDATA[44] === 1'bz) || SAXISCCTDATA_delay[44]; // rv 1 + assign SAXISCCTDATA_in[45] = (SAXISCCTDATA[45] === 1'bz) || SAXISCCTDATA_delay[45]; // rv 1 + assign SAXISCCTDATA_in[46] = (SAXISCCTDATA[46] === 1'bz) || SAXISCCTDATA_delay[46]; // rv 1 + assign SAXISCCTDATA_in[47] = (SAXISCCTDATA[47] === 1'bz) || SAXISCCTDATA_delay[47]; // rv 1 + assign SAXISCCTDATA_in[48] = (SAXISCCTDATA[48] === 1'bz) || SAXISCCTDATA_delay[48]; // rv 1 + assign SAXISCCTDATA_in[49] = (SAXISCCTDATA[49] === 1'bz) || SAXISCCTDATA_delay[49]; // rv 1 + assign SAXISCCTDATA_in[4] = (SAXISCCTDATA[4] === 1'bz) || SAXISCCTDATA_delay[4]; // rv 1 + assign SAXISCCTDATA_in[50] = (SAXISCCTDATA[50] === 1'bz) || SAXISCCTDATA_delay[50]; // rv 1 + assign SAXISCCTDATA_in[51] = (SAXISCCTDATA[51] === 1'bz) || SAXISCCTDATA_delay[51]; // rv 1 + assign SAXISCCTDATA_in[52] = (SAXISCCTDATA[52] === 1'bz) || SAXISCCTDATA_delay[52]; // rv 1 + assign SAXISCCTDATA_in[53] = (SAXISCCTDATA[53] === 1'bz) || SAXISCCTDATA_delay[53]; // rv 1 + assign SAXISCCTDATA_in[54] = (SAXISCCTDATA[54] === 1'bz) || SAXISCCTDATA_delay[54]; // rv 1 + assign SAXISCCTDATA_in[55] = (SAXISCCTDATA[55] === 1'bz) || SAXISCCTDATA_delay[55]; // rv 1 + assign SAXISCCTDATA_in[56] = (SAXISCCTDATA[56] === 1'bz) || SAXISCCTDATA_delay[56]; // rv 1 + assign SAXISCCTDATA_in[57] = (SAXISCCTDATA[57] === 1'bz) || SAXISCCTDATA_delay[57]; // rv 1 + assign SAXISCCTDATA_in[58] = (SAXISCCTDATA[58] === 1'bz) || SAXISCCTDATA_delay[58]; // rv 1 + assign SAXISCCTDATA_in[59] = (SAXISCCTDATA[59] === 1'bz) || SAXISCCTDATA_delay[59]; // rv 1 + assign SAXISCCTDATA_in[5] = (SAXISCCTDATA[5] === 1'bz) || SAXISCCTDATA_delay[5]; // rv 1 + assign SAXISCCTDATA_in[60] = (SAXISCCTDATA[60] === 1'bz) || SAXISCCTDATA_delay[60]; // rv 1 + assign SAXISCCTDATA_in[61] = (SAXISCCTDATA[61] === 1'bz) || SAXISCCTDATA_delay[61]; // rv 1 + assign SAXISCCTDATA_in[62] = (SAXISCCTDATA[62] === 1'bz) || SAXISCCTDATA_delay[62]; // rv 1 + assign SAXISCCTDATA_in[63] = (SAXISCCTDATA[63] === 1'bz) || SAXISCCTDATA_delay[63]; // rv 1 + assign SAXISCCTDATA_in[64] = (SAXISCCTDATA[64] === 1'bz) || SAXISCCTDATA_delay[64]; // rv 1 + assign SAXISCCTDATA_in[65] = (SAXISCCTDATA[65] === 1'bz) || SAXISCCTDATA_delay[65]; // rv 1 + assign SAXISCCTDATA_in[66] = (SAXISCCTDATA[66] === 1'bz) || SAXISCCTDATA_delay[66]; // rv 1 + assign SAXISCCTDATA_in[67] = (SAXISCCTDATA[67] === 1'bz) || SAXISCCTDATA_delay[67]; // rv 1 + assign SAXISCCTDATA_in[68] = (SAXISCCTDATA[68] === 1'bz) || SAXISCCTDATA_delay[68]; // rv 1 + assign SAXISCCTDATA_in[69] = (SAXISCCTDATA[69] === 1'bz) || SAXISCCTDATA_delay[69]; // rv 1 + assign SAXISCCTDATA_in[6] = (SAXISCCTDATA[6] === 1'bz) || SAXISCCTDATA_delay[6]; // rv 1 + assign SAXISCCTDATA_in[70] = (SAXISCCTDATA[70] === 1'bz) || SAXISCCTDATA_delay[70]; // rv 1 + assign SAXISCCTDATA_in[71] = (SAXISCCTDATA[71] === 1'bz) || SAXISCCTDATA_delay[71]; // rv 1 + assign SAXISCCTDATA_in[72] = (SAXISCCTDATA[72] === 1'bz) || SAXISCCTDATA_delay[72]; // rv 1 + assign SAXISCCTDATA_in[73] = (SAXISCCTDATA[73] === 1'bz) || SAXISCCTDATA_delay[73]; // rv 1 + assign SAXISCCTDATA_in[74] = (SAXISCCTDATA[74] === 1'bz) || SAXISCCTDATA_delay[74]; // rv 1 + assign SAXISCCTDATA_in[75] = (SAXISCCTDATA[75] === 1'bz) || SAXISCCTDATA_delay[75]; // rv 1 + assign SAXISCCTDATA_in[76] = (SAXISCCTDATA[76] === 1'bz) || SAXISCCTDATA_delay[76]; // rv 1 + assign SAXISCCTDATA_in[77] = (SAXISCCTDATA[77] === 1'bz) || SAXISCCTDATA_delay[77]; // rv 1 + assign SAXISCCTDATA_in[78] = (SAXISCCTDATA[78] === 1'bz) || SAXISCCTDATA_delay[78]; // rv 1 + assign SAXISCCTDATA_in[79] = (SAXISCCTDATA[79] === 1'bz) || SAXISCCTDATA_delay[79]; // rv 1 + assign SAXISCCTDATA_in[7] = (SAXISCCTDATA[7] === 1'bz) || SAXISCCTDATA_delay[7]; // rv 1 + assign SAXISCCTDATA_in[80] = (SAXISCCTDATA[80] === 1'bz) || SAXISCCTDATA_delay[80]; // rv 1 + assign SAXISCCTDATA_in[81] = (SAXISCCTDATA[81] === 1'bz) || SAXISCCTDATA_delay[81]; // rv 1 + assign SAXISCCTDATA_in[82] = (SAXISCCTDATA[82] === 1'bz) || SAXISCCTDATA_delay[82]; // rv 1 + assign SAXISCCTDATA_in[83] = (SAXISCCTDATA[83] === 1'bz) || SAXISCCTDATA_delay[83]; // rv 1 + assign SAXISCCTDATA_in[84] = (SAXISCCTDATA[84] === 1'bz) || SAXISCCTDATA_delay[84]; // rv 1 + assign SAXISCCTDATA_in[85] = (SAXISCCTDATA[85] === 1'bz) || SAXISCCTDATA_delay[85]; // rv 1 + assign SAXISCCTDATA_in[86] = (SAXISCCTDATA[86] === 1'bz) || SAXISCCTDATA_delay[86]; // rv 1 + assign SAXISCCTDATA_in[87] = (SAXISCCTDATA[87] === 1'bz) || SAXISCCTDATA_delay[87]; // rv 1 + assign SAXISCCTDATA_in[88] = (SAXISCCTDATA[88] === 1'bz) || SAXISCCTDATA_delay[88]; // rv 1 + assign SAXISCCTDATA_in[89] = (SAXISCCTDATA[89] === 1'bz) || SAXISCCTDATA_delay[89]; // rv 1 + assign SAXISCCTDATA_in[8] = (SAXISCCTDATA[8] === 1'bz) || SAXISCCTDATA_delay[8]; // rv 1 + assign SAXISCCTDATA_in[90] = (SAXISCCTDATA[90] === 1'bz) || SAXISCCTDATA_delay[90]; // rv 1 + assign SAXISCCTDATA_in[91] = (SAXISCCTDATA[91] === 1'bz) || SAXISCCTDATA_delay[91]; // rv 1 + assign SAXISCCTDATA_in[92] = (SAXISCCTDATA[92] === 1'bz) || SAXISCCTDATA_delay[92]; // rv 1 + assign SAXISCCTDATA_in[93] = (SAXISCCTDATA[93] === 1'bz) || SAXISCCTDATA_delay[93]; // rv 1 + assign SAXISCCTDATA_in[94] = (SAXISCCTDATA[94] === 1'bz) || SAXISCCTDATA_delay[94]; // rv 1 + assign SAXISCCTDATA_in[95] = (SAXISCCTDATA[95] === 1'bz) || SAXISCCTDATA_delay[95]; // rv 1 + assign SAXISCCTDATA_in[96] = (SAXISCCTDATA[96] === 1'bz) || SAXISCCTDATA_delay[96]; // rv 1 + assign SAXISCCTDATA_in[97] = (SAXISCCTDATA[97] === 1'bz) || SAXISCCTDATA_delay[97]; // rv 1 + assign SAXISCCTDATA_in[98] = (SAXISCCTDATA[98] === 1'bz) || SAXISCCTDATA_delay[98]; // rv 1 + assign SAXISCCTDATA_in[99] = (SAXISCCTDATA[99] === 1'bz) || SAXISCCTDATA_delay[99]; // rv 1 + assign SAXISCCTDATA_in[9] = (SAXISCCTDATA[9] === 1'bz) || SAXISCCTDATA_delay[9]; // rv 1 + assign SAXISCCTKEEP_in[0] = (SAXISCCTKEEP[0] !== 1'bz) && SAXISCCTKEEP_delay[0]; // rv 0 + assign SAXISCCTKEEP_in[1] = (SAXISCCTKEEP[1] !== 1'bz) && SAXISCCTKEEP_delay[1]; // rv 0 + assign SAXISCCTKEEP_in[2] = (SAXISCCTKEEP[2] !== 1'bz) && SAXISCCTKEEP_delay[2]; // rv 0 + assign SAXISCCTKEEP_in[3] = (SAXISCCTKEEP[3] !== 1'bz) && SAXISCCTKEEP_delay[3]; // rv 0 + assign SAXISCCTKEEP_in[4] = (SAXISCCTKEEP[4] !== 1'bz) && SAXISCCTKEEP_delay[4]; // rv 0 + assign SAXISCCTKEEP_in[5] = (SAXISCCTKEEP[5] !== 1'bz) && SAXISCCTKEEP_delay[5]; // rv 0 + assign SAXISCCTKEEP_in[6] = (SAXISCCTKEEP[6] !== 1'bz) && SAXISCCTKEEP_delay[6]; // rv 0 + assign SAXISCCTKEEP_in[7] = (SAXISCCTKEEP[7] !== 1'bz) && SAXISCCTKEEP_delay[7]; // rv 0 + assign SAXISCCTLAST_in = (SAXISCCTLAST === 1'bz) || SAXISCCTLAST_delay; // rv 1 + assign SAXISCCTUSER_in[0] = (SAXISCCTUSER[0] === 1'bz) || SAXISCCTUSER_delay[0]; // rv 1 + assign SAXISCCTUSER_in[10] = (SAXISCCTUSER[10] === 1'bz) || SAXISCCTUSER_delay[10]; // rv 1 + assign SAXISCCTUSER_in[11] = (SAXISCCTUSER[11] === 1'bz) || SAXISCCTUSER_delay[11]; // rv 1 + assign SAXISCCTUSER_in[12] = (SAXISCCTUSER[12] === 1'bz) || SAXISCCTUSER_delay[12]; // rv 1 + assign SAXISCCTUSER_in[13] = (SAXISCCTUSER[13] === 1'bz) || SAXISCCTUSER_delay[13]; // rv 1 + assign SAXISCCTUSER_in[14] = (SAXISCCTUSER[14] === 1'bz) || SAXISCCTUSER_delay[14]; // rv 1 + assign SAXISCCTUSER_in[15] = (SAXISCCTUSER[15] === 1'bz) || SAXISCCTUSER_delay[15]; // rv 1 + assign SAXISCCTUSER_in[16] = (SAXISCCTUSER[16] === 1'bz) || SAXISCCTUSER_delay[16]; // rv 1 + assign SAXISCCTUSER_in[17] = (SAXISCCTUSER[17] === 1'bz) || SAXISCCTUSER_delay[17]; // rv 1 + assign SAXISCCTUSER_in[18] = (SAXISCCTUSER[18] === 1'bz) || SAXISCCTUSER_delay[18]; // rv 1 + assign SAXISCCTUSER_in[19] = (SAXISCCTUSER[19] === 1'bz) || SAXISCCTUSER_delay[19]; // rv 1 + assign SAXISCCTUSER_in[1] = (SAXISCCTUSER[1] === 1'bz) || SAXISCCTUSER_delay[1]; // rv 1 + assign SAXISCCTUSER_in[20] = (SAXISCCTUSER[20] === 1'bz) || SAXISCCTUSER_delay[20]; // rv 1 + assign SAXISCCTUSER_in[21] = (SAXISCCTUSER[21] === 1'bz) || SAXISCCTUSER_delay[21]; // rv 1 + assign SAXISCCTUSER_in[22] = (SAXISCCTUSER[22] === 1'bz) || SAXISCCTUSER_delay[22]; // rv 1 + assign SAXISCCTUSER_in[23] = (SAXISCCTUSER[23] === 1'bz) || SAXISCCTUSER_delay[23]; // rv 1 + assign SAXISCCTUSER_in[24] = (SAXISCCTUSER[24] === 1'bz) || SAXISCCTUSER_delay[24]; // rv 1 + assign SAXISCCTUSER_in[25] = (SAXISCCTUSER[25] === 1'bz) || SAXISCCTUSER_delay[25]; // rv 1 + assign SAXISCCTUSER_in[26] = (SAXISCCTUSER[26] === 1'bz) || SAXISCCTUSER_delay[26]; // rv 1 + assign SAXISCCTUSER_in[27] = (SAXISCCTUSER[27] === 1'bz) || SAXISCCTUSER_delay[27]; // rv 1 + assign SAXISCCTUSER_in[28] = (SAXISCCTUSER[28] === 1'bz) || SAXISCCTUSER_delay[28]; // rv 1 + assign SAXISCCTUSER_in[29] = (SAXISCCTUSER[29] === 1'bz) || SAXISCCTUSER_delay[29]; // rv 1 + assign SAXISCCTUSER_in[2] = (SAXISCCTUSER[2] === 1'bz) || SAXISCCTUSER_delay[2]; // rv 1 + assign SAXISCCTUSER_in[30] = (SAXISCCTUSER[30] === 1'bz) || SAXISCCTUSER_delay[30]; // rv 1 + assign SAXISCCTUSER_in[31] = (SAXISCCTUSER[31] === 1'bz) || SAXISCCTUSER_delay[31]; // rv 1 + assign SAXISCCTUSER_in[32] = (SAXISCCTUSER[32] === 1'bz) || SAXISCCTUSER_delay[32]; // rv 1 + assign SAXISCCTUSER_in[3] = (SAXISCCTUSER[3] === 1'bz) || SAXISCCTUSER_delay[3]; // rv 1 + assign SAXISCCTUSER_in[4] = (SAXISCCTUSER[4] === 1'bz) || SAXISCCTUSER_delay[4]; // rv 1 + assign SAXISCCTUSER_in[5] = (SAXISCCTUSER[5] === 1'bz) || SAXISCCTUSER_delay[5]; // rv 1 + assign SAXISCCTUSER_in[6] = (SAXISCCTUSER[6] === 1'bz) || SAXISCCTUSER_delay[6]; // rv 1 + assign SAXISCCTUSER_in[7] = (SAXISCCTUSER[7] === 1'bz) || SAXISCCTUSER_delay[7]; // rv 1 + assign SAXISCCTUSER_in[8] = (SAXISCCTUSER[8] === 1'bz) || SAXISCCTUSER_delay[8]; // rv 1 + assign SAXISCCTUSER_in[9] = (SAXISCCTUSER[9] === 1'bz) || SAXISCCTUSER_delay[9]; // rv 1 + assign SAXISCCTVALID_in = (SAXISCCTVALID !== 1'bz) && SAXISCCTVALID_delay; // rv 0 + assign SAXISRQTDATA_in[0] = (SAXISRQTDATA[0] === 1'bz) || SAXISRQTDATA_delay[0]; // rv 1 + assign SAXISRQTDATA_in[100] = (SAXISRQTDATA[100] === 1'bz) || SAXISRQTDATA_delay[100]; // rv 1 + assign SAXISRQTDATA_in[101] = (SAXISRQTDATA[101] === 1'bz) || SAXISRQTDATA_delay[101]; // rv 1 + assign SAXISRQTDATA_in[102] = (SAXISRQTDATA[102] === 1'bz) || SAXISRQTDATA_delay[102]; // rv 1 + assign SAXISRQTDATA_in[103] = (SAXISRQTDATA[103] === 1'bz) || SAXISRQTDATA_delay[103]; // rv 1 + assign SAXISRQTDATA_in[104] = (SAXISRQTDATA[104] === 1'bz) || SAXISRQTDATA_delay[104]; // rv 1 + assign SAXISRQTDATA_in[105] = (SAXISRQTDATA[105] === 1'bz) || SAXISRQTDATA_delay[105]; // rv 1 + assign SAXISRQTDATA_in[106] = (SAXISRQTDATA[106] === 1'bz) || SAXISRQTDATA_delay[106]; // rv 1 + assign SAXISRQTDATA_in[107] = (SAXISRQTDATA[107] === 1'bz) || SAXISRQTDATA_delay[107]; // rv 1 + assign SAXISRQTDATA_in[108] = (SAXISRQTDATA[108] === 1'bz) || SAXISRQTDATA_delay[108]; // rv 1 + assign SAXISRQTDATA_in[109] = (SAXISRQTDATA[109] === 1'bz) || SAXISRQTDATA_delay[109]; // rv 1 + assign SAXISRQTDATA_in[10] = (SAXISRQTDATA[10] === 1'bz) || SAXISRQTDATA_delay[10]; // rv 1 + assign SAXISRQTDATA_in[110] = (SAXISRQTDATA[110] === 1'bz) || SAXISRQTDATA_delay[110]; // rv 1 + assign SAXISRQTDATA_in[111] = (SAXISRQTDATA[111] === 1'bz) || SAXISRQTDATA_delay[111]; // rv 1 + assign SAXISRQTDATA_in[112] = (SAXISRQTDATA[112] === 1'bz) || SAXISRQTDATA_delay[112]; // rv 1 + assign SAXISRQTDATA_in[113] = (SAXISRQTDATA[113] === 1'bz) || SAXISRQTDATA_delay[113]; // rv 1 + assign SAXISRQTDATA_in[114] = (SAXISRQTDATA[114] === 1'bz) || SAXISRQTDATA_delay[114]; // rv 1 + assign SAXISRQTDATA_in[115] = (SAXISRQTDATA[115] === 1'bz) || SAXISRQTDATA_delay[115]; // rv 1 + assign SAXISRQTDATA_in[116] = (SAXISRQTDATA[116] === 1'bz) || SAXISRQTDATA_delay[116]; // rv 1 + assign SAXISRQTDATA_in[117] = (SAXISRQTDATA[117] === 1'bz) || SAXISRQTDATA_delay[117]; // rv 1 + assign SAXISRQTDATA_in[118] = (SAXISRQTDATA[118] === 1'bz) || SAXISRQTDATA_delay[118]; // rv 1 + assign SAXISRQTDATA_in[119] = (SAXISRQTDATA[119] === 1'bz) || SAXISRQTDATA_delay[119]; // rv 1 + assign SAXISRQTDATA_in[11] = (SAXISRQTDATA[11] === 1'bz) || SAXISRQTDATA_delay[11]; // rv 1 + assign SAXISRQTDATA_in[120] = (SAXISRQTDATA[120] === 1'bz) || SAXISRQTDATA_delay[120]; // rv 1 + assign SAXISRQTDATA_in[121] = (SAXISRQTDATA[121] === 1'bz) || SAXISRQTDATA_delay[121]; // rv 1 + assign SAXISRQTDATA_in[122] = (SAXISRQTDATA[122] === 1'bz) || SAXISRQTDATA_delay[122]; // rv 1 + assign SAXISRQTDATA_in[123] = (SAXISRQTDATA[123] === 1'bz) || SAXISRQTDATA_delay[123]; // rv 1 + assign SAXISRQTDATA_in[124] = (SAXISRQTDATA[124] === 1'bz) || SAXISRQTDATA_delay[124]; // rv 1 + assign SAXISRQTDATA_in[125] = (SAXISRQTDATA[125] === 1'bz) || SAXISRQTDATA_delay[125]; // rv 1 + assign SAXISRQTDATA_in[126] = (SAXISRQTDATA[126] === 1'bz) || SAXISRQTDATA_delay[126]; // rv 1 + assign SAXISRQTDATA_in[127] = (SAXISRQTDATA[127] === 1'bz) || SAXISRQTDATA_delay[127]; // rv 1 + assign SAXISRQTDATA_in[128] = (SAXISRQTDATA[128] === 1'bz) || SAXISRQTDATA_delay[128]; // rv 1 + assign SAXISRQTDATA_in[129] = (SAXISRQTDATA[129] === 1'bz) || SAXISRQTDATA_delay[129]; // rv 1 + assign SAXISRQTDATA_in[12] = (SAXISRQTDATA[12] === 1'bz) || SAXISRQTDATA_delay[12]; // rv 1 + assign SAXISRQTDATA_in[130] = (SAXISRQTDATA[130] === 1'bz) || SAXISRQTDATA_delay[130]; // rv 1 + assign SAXISRQTDATA_in[131] = (SAXISRQTDATA[131] === 1'bz) || SAXISRQTDATA_delay[131]; // rv 1 + assign SAXISRQTDATA_in[132] = (SAXISRQTDATA[132] === 1'bz) || SAXISRQTDATA_delay[132]; // rv 1 + assign SAXISRQTDATA_in[133] = (SAXISRQTDATA[133] === 1'bz) || SAXISRQTDATA_delay[133]; // rv 1 + assign SAXISRQTDATA_in[134] = (SAXISRQTDATA[134] === 1'bz) || SAXISRQTDATA_delay[134]; // rv 1 + assign SAXISRQTDATA_in[135] = (SAXISRQTDATA[135] === 1'bz) || SAXISRQTDATA_delay[135]; // rv 1 + assign SAXISRQTDATA_in[136] = (SAXISRQTDATA[136] === 1'bz) || SAXISRQTDATA_delay[136]; // rv 1 + assign SAXISRQTDATA_in[137] = (SAXISRQTDATA[137] === 1'bz) || SAXISRQTDATA_delay[137]; // rv 1 + assign SAXISRQTDATA_in[138] = (SAXISRQTDATA[138] === 1'bz) || SAXISRQTDATA_delay[138]; // rv 1 + assign SAXISRQTDATA_in[139] = (SAXISRQTDATA[139] === 1'bz) || SAXISRQTDATA_delay[139]; // rv 1 + assign SAXISRQTDATA_in[13] = (SAXISRQTDATA[13] === 1'bz) || SAXISRQTDATA_delay[13]; // rv 1 + assign SAXISRQTDATA_in[140] = (SAXISRQTDATA[140] === 1'bz) || SAXISRQTDATA_delay[140]; // rv 1 + assign SAXISRQTDATA_in[141] = (SAXISRQTDATA[141] === 1'bz) || SAXISRQTDATA_delay[141]; // rv 1 + assign SAXISRQTDATA_in[142] = (SAXISRQTDATA[142] === 1'bz) || SAXISRQTDATA_delay[142]; // rv 1 + assign SAXISRQTDATA_in[143] = (SAXISRQTDATA[143] === 1'bz) || SAXISRQTDATA_delay[143]; // rv 1 + assign SAXISRQTDATA_in[144] = (SAXISRQTDATA[144] === 1'bz) || SAXISRQTDATA_delay[144]; // rv 1 + assign SAXISRQTDATA_in[145] = (SAXISRQTDATA[145] === 1'bz) || SAXISRQTDATA_delay[145]; // rv 1 + assign SAXISRQTDATA_in[146] = (SAXISRQTDATA[146] === 1'bz) || SAXISRQTDATA_delay[146]; // rv 1 + assign SAXISRQTDATA_in[147] = (SAXISRQTDATA[147] === 1'bz) || SAXISRQTDATA_delay[147]; // rv 1 + assign SAXISRQTDATA_in[148] = (SAXISRQTDATA[148] === 1'bz) || SAXISRQTDATA_delay[148]; // rv 1 + assign SAXISRQTDATA_in[149] = (SAXISRQTDATA[149] === 1'bz) || SAXISRQTDATA_delay[149]; // rv 1 + assign SAXISRQTDATA_in[14] = (SAXISRQTDATA[14] === 1'bz) || SAXISRQTDATA_delay[14]; // rv 1 + assign SAXISRQTDATA_in[150] = (SAXISRQTDATA[150] === 1'bz) || SAXISRQTDATA_delay[150]; // rv 1 + assign SAXISRQTDATA_in[151] = (SAXISRQTDATA[151] === 1'bz) || SAXISRQTDATA_delay[151]; // rv 1 + assign SAXISRQTDATA_in[152] = (SAXISRQTDATA[152] === 1'bz) || SAXISRQTDATA_delay[152]; // rv 1 + assign SAXISRQTDATA_in[153] = (SAXISRQTDATA[153] === 1'bz) || SAXISRQTDATA_delay[153]; // rv 1 + assign SAXISRQTDATA_in[154] = (SAXISRQTDATA[154] === 1'bz) || SAXISRQTDATA_delay[154]; // rv 1 + assign SAXISRQTDATA_in[155] = (SAXISRQTDATA[155] === 1'bz) || SAXISRQTDATA_delay[155]; // rv 1 + assign SAXISRQTDATA_in[156] = (SAXISRQTDATA[156] === 1'bz) || SAXISRQTDATA_delay[156]; // rv 1 + assign SAXISRQTDATA_in[157] = (SAXISRQTDATA[157] === 1'bz) || SAXISRQTDATA_delay[157]; // rv 1 + assign SAXISRQTDATA_in[158] = (SAXISRQTDATA[158] === 1'bz) || SAXISRQTDATA_delay[158]; // rv 1 + assign SAXISRQTDATA_in[159] = (SAXISRQTDATA[159] === 1'bz) || SAXISRQTDATA_delay[159]; // rv 1 + assign SAXISRQTDATA_in[15] = (SAXISRQTDATA[15] === 1'bz) || SAXISRQTDATA_delay[15]; // rv 1 + assign SAXISRQTDATA_in[160] = (SAXISRQTDATA[160] === 1'bz) || SAXISRQTDATA_delay[160]; // rv 1 + assign SAXISRQTDATA_in[161] = (SAXISRQTDATA[161] === 1'bz) || SAXISRQTDATA_delay[161]; // rv 1 + assign SAXISRQTDATA_in[162] = (SAXISRQTDATA[162] === 1'bz) || SAXISRQTDATA_delay[162]; // rv 1 + assign SAXISRQTDATA_in[163] = (SAXISRQTDATA[163] === 1'bz) || SAXISRQTDATA_delay[163]; // rv 1 + assign SAXISRQTDATA_in[164] = (SAXISRQTDATA[164] === 1'bz) || SAXISRQTDATA_delay[164]; // rv 1 + assign SAXISRQTDATA_in[165] = (SAXISRQTDATA[165] === 1'bz) || SAXISRQTDATA_delay[165]; // rv 1 + assign SAXISRQTDATA_in[166] = (SAXISRQTDATA[166] === 1'bz) || SAXISRQTDATA_delay[166]; // rv 1 + assign SAXISRQTDATA_in[167] = (SAXISRQTDATA[167] === 1'bz) || SAXISRQTDATA_delay[167]; // rv 1 + assign SAXISRQTDATA_in[168] = (SAXISRQTDATA[168] === 1'bz) || SAXISRQTDATA_delay[168]; // rv 1 + assign SAXISRQTDATA_in[169] = (SAXISRQTDATA[169] === 1'bz) || SAXISRQTDATA_delay[169]; // rv 1 + assign SAXISRQTDATA_in[16] = (SAXISRQTDATA[16] === 1'bz) || SAXISRQTDATA_delay[16]; // rv 1 + assign SAXISRQTDATA_in[170] = (SAXISRQTDATA[170] === 1'bz) || SAXISRQTDATA_delay[170]; // rv 1 + assign SAXISRQTDATA_in[171] = (SAXISRQTDATA[171] === 1'bz) || SAXISRQTDATA_delay[171]; // rv 1 + assign SAXISRQTDATA_in[172] = (SAXISRQTDATA[172] === 1'bz) || SAXISRQTDATA_delay[172]; // rv 1 + assign SAXISRQTDATA_in[173] = (SAXISRQTDATA[173] === 1'bz) || SAXISRQTDATA_delay[173]; // rv 1 + assign SAXISRQTDATA_in[174] = (SAXISRQTDATA[174] === 1'bz) || SAXISRQTDATA_delay[174]; // rv 1 + assign SAXISRQTDATA_in[175] = (SAXISRQTDATA[175] === 1'bz) || SAXISRQTDATA_delay[175]; // rv 1 + assign SAXISRQTDATA_in[176] = (SAXISRQTDATA[176] === 1'bz) || SAXISRQTDATA_delay[176]; // rv 1 + assign SAXISRQTDATA_in[177] = (SAXISRQTDATA[177] === 1'bz) || SAXISRQTDATA_delay[177]; // rv 1 + assign SAXISRQTDATA_in[178] = (SAXISRQTDATA[178] === 1'bz) || SAXISRQTDATA_delay[178]; // rv 1 + assign SAXISRQTDATA_in[179] = (SAXISRQTDATA[179] === 1'bz) || SAXISRQTDATA_delay[179]; // rv 1 + assign SAXISRQTDATA_in[17] = (SAXISRQTDATA[17] === 1'bz) || SAXISRQTDATA_delay[17]; // rv 1 + assign SAXISRQTDATA_in[180] = (SAXISRQTDATA[180] === 1'bz) || SAXISRQTDATA_delay[180]; // rv 1 + assign SAXISRQTDATA_in[181] = (SAXISRQTDATA[181] === 1'bz) || SAXISRQTDATA_delay[181]; // rv 1 + assign SAXISRQTDATA_in[182] = (SAXISRQTDATA[182] === 1'bz) || SAXISRQTDATA_delay[182]; // rv 1 + assign SAXISRQTDATA_in[183] = (SAXISRQTDATA[183] === 1'bz) || SAXISRQTDATA_delay[183]; // rv 1 + assign SAXISRQTDATA_in[184] = (SAXISRQTDATA[184] === 1'bz) || SAXISRQTDATA_delay[184]; // rv 1 + assign SAXISRQTDATA_in[185] = (SAXISRQTDATA[185] === 1'bz) || SAXISRQTDATA_delay[185]; // rv 1 + assign SAXISRQTDATA_in[186] = (SAXISRQTDATA[186] === 1'bz) || SAXISRQTDATA_delay[186]; // rv 1 + assign SAXISRQTDATA_in[187] = (SAXISRQTDATA[187] === 1'bz) || SAXISRQTDATA_delay[187]; // rv 1 + assign SAXISRQTDATA_in[188] = (SAXISRQTDATA[188] === 1'bz) || SAXISRQTDATA_delay[188]; // rv 1 + assign SAXISRQTDATA_in[189] = (SAXISRQTDATA[189] === 1'bz) || SAXISRQTDATA_delay[189]; // rv 1 + assign SAXISRQTDATA_in[18] = (SAXISRQTDATA[18] === 1'bz) || SAXISRQTDATA_delay[18]; // rv 1 + assign SAXISRQTDATA_in[190] = (SAXISRQTDATA[190] === 1'bz) || SAXISRQTDATA_delay[190]; // rv 1 + assign SAXISRQTDATA_in[191] = (SAXISRQTDATA[191] === 1'bz) || SAXISRQTDATA_delay[191]; // rv 1 + assign SAXISRQTDATA_in[192] = (SAXISRQTDATA[192] === 1'bz) || SAXISRQTDATA_delay[192]; // rv 1 + assign SAXISRQTDATA_in[193] = (SAXISRQTDATA[193] === 1'bz) || SAXISRQTDATA_delay[193]; // rv 1 + assign SAXISRQTDATA_in[194] = (SAXISRQTDATA[194] === 1'bz) || SAXISRQTDATA_delay[194]; // rv 1 + assign SAXISRQTDATA_in[195] = (SAXISRQTDATA[195] === 1'bz) || SAXISRQTDATA_delay[195]; // rv 1 + assign SAXISRQTDATA_in[196] = (SAXISRQTDATA[196] === 1'bz) || SAXISRQTDATA_delay[196]; // rv 1 + assign SAXISRQTDATA_in[197] = (SAXISRQTDATA[197] === 1'bz) || SAXISRQTDATA_delay[197]; // rv 1 + assign SAXISRQTDATA_in[198] = (SAXISRQTDATA[198] === 1'bz) || SAXISRQTDATA_delay[198]; // rv 1 + assign SAXISRQTDATA_in[199] = (SAXISRQTDATA[199] === 1'bz) || SAXISRQTDATA_delay[199]; // rv 1 + assign SAXISRQTDATA_in[19] = (SAXISRQTDATA[19] === 1'bz) || SAXISRQTDATA_delay[19]; // rv 1 + assign SAXISRQTDATA_in[1] = (SAXISRQTDATA[1] === 1'bz) || SAXISRQTDATA_delay[1]; // rv 1 + assign SAXISRQTDATA_in[200] = (SAXISRQTDATA[200] === 1'bz) || SAXISRQTDATA_delay[200]; // rv 1 + assign SAXISRQTDATA_in[201] = (SAXISRQTDATA[201] === 1'bz) || SAXISRQTDATA_delay[201]; // rv 1 + assign SAXISRQTDATA_in[202] = (SAXISRQTDATA[202] === 1'bz) || SAXISRQTDATA_delay[202]; // rv 1 + assign SAXISRQTDATA_in[203] = (SAXISRQTDATA[203] === 1'bz) || SAXISRQTDATA_delay[203]; // rv 1 + assign SAXISRQTDATA_in[204] = (SAXISRQTDATA[204] === 1'bz) || SAXISRQTDATA_delay[204]; // rv 1 + assign SAXISRQTDATA_in[205] = (SAXISRQTDATA[205] === 1'bz) || SAXISRQTDATA_delay[205]; // rv 1 + assign SAXISRQTDATA_in[206] = (SAXISRQTDATA[206] === 1'bz) || SAXISRQTDATA_delay[206]; // rv 1 + assign SAXISRQTDATA_in[207] = (SAXISRQTDATA[207] === 1'bz) || SAXISRQTDATA_delay[207]; // rv 1 + assign SAXISRQTDATA_in[208] = (SAXISRQTDATA[208] === 1'bz) || SAXISRQTDATA_delay[208]; // rv 1 + assign SAXISRQTDATA_in[209] = (SAXISRQTDATA[209] === 1'bz) || SAXISRQTDATA_delay[209]; // rv 1 + assign SAXISRQTDATA_in[20] = (SAXISRQTDATA[20] === 1'bz) || SAXISRQTDATA_delay[20]; // rv 1 + assign SAXISRQTDATA_in[210] = (SAXISRQTDATA[210] === 1'bz) || SAXISRQTDATA_delay[210]; // rv 1 + assign SAXISRQTDATA_in[211] = (SAXISRQTDATA[211] === 1'bz) || SAXISRQTDATA_delay[211]; // rv 1 + assign SAXISRQTDATA_in[212] = (SAXISRQTDATA[212] === 1'bz) || SAXISRQTDATA_delay[212]; // rv 1 + assign SAXISRQTDATA_in[213] = (SAXISRQTDATA[213] === 1'bz) || SAXISRQTDATA_delay[213]; // rv 1 + assign SAXISRQTDATA_in[214] = (SAXISRQTDATA[214] === 1'bz) || SAXISRQTDATA_delay[214]; // rv 1 + assign SAXISRQTDATA_in[215] = (SAXISRQTDATA[215] === 1'bz) || SAXISRQTDATA_delay[215]; // rv 1 + assign SAXISRQTDATA_in[216] = (SAXISRQTDATA[216] === 1'bz) || SAXISRQTDATA_delay[216]; // rv 1 + assign SAXISRQTDATA_in[217] = (SAXISRQTDATA[217] === 1'bz) || SAXISRQTDATA_delay[217]; // rv 1 + assign SAXISRQTDATA_in[218] = (SAXISRQTDATA[218] === 1'bz) || SAXISRQTDATA_delay[218]; // rv 1 + assign SAXISRQTDATA_in[219] = (SAXISRQTDATA[219] === 1'bz) || SAXISRQTDATA_delay[219]; // rv 1 + assign SAXISRQTDATA_in[21] = (SAXISRQTDATA[21] === 1'bz) || SAXISRQTDATA_delay[21]; // rv 1 + assign SAXISRQTDATA_in[220] = (SAXISRQTDATA[220] === 1'bz) || SAXISRQTDATA_delay[220]; // rv 1 + assign SAXISRQTDATA_in[221] = (SAXISRQTDATA[221] === 1'bz) || SAXISRQTDATA_delay[221]; // rv 1 + assign SAXISRQTDATA_in[222] = (SAXISRQTDATA[222] === 1'bz) || SAXISRQTDATA_delay[222]; // rv 1 + assign SAXISRQTDATA_in[223] = (SAXISRQTDATA[223] === 1'bz) || SAXISRQTDATA_delay[223]; // rv 1 + assign SAXISRQTDATA_in[224] = (SAXISRQTDATA[224] === 1'bz) || SAXISRQTDATA_delay[224]; // rv 1 + assign SAXISRQTDATA_in[225] = (SAXISRQTDATA[225] === 1'bz) || SAXISRQTDATA_delay[225]; // rv 1 + assign SAXISRQTDATA_in[226] = (SAXISRQTDATA[226] === 1'bz) || SAXISRQTDATA_delay[226]; // rv 1 + assign SAXISRQTDATA_in[227] = (SAXISRQTDATA[227] === 1'bz) || SAXISRQTDATA_delay[227]; // rv 1 + assign SAXISRQTDATA_in[228] = (SAXISRQTDATA[228] === 1'bz) || SAXISRQTDATA_delay[228]; // rv 1 + assign SAXISRQTDATA_in[229] = (SAXISRQTDATA[229] === 1'bz) || SAXISRQTDATA_delay[229]; // rv 1 + assign SAXISRQTDATA_in[22] = (SAXISRQTDATA[22] === 1'bz) || SAXISRQTDATA_delay[22]; // rv 1 + assign SAXISRQTDATA_in[230] = (SAXISRQTDATA[230] === 1'bz) || SAXISRQTDATA_delay[230]; // rv 1 + assign SAXISRQTDATA_in[231] = (SAXISRQTDATA[231] === 1'bz) || SAXISRQTDATA_delay[231]; // rv 1 + assign SAXISRQTDATA_in[232] = (SAXISRQTDATA[232] === 1'bz) || SAXISRQTDATA_delay[232]; // rv 1 + assign SAXISRQTDATA_in[233] = (SAXISRQTDATA[233] === 1'bz) || SAXISRQTDATA_delay[233]; // rv 1 + assign SAXISRQTDATA_in[234] = (SAXISRQTDATA[234] === 1'bz) || SAXISRQTDATA_delay[234]; // rv 1 + assign SAXISRQTDATA_in[235] = (SAXISRQTDATA[235] === 1'bz) || SAXISRQTDATA_delay[235]; // rv 1 + assign SAXISRQTDATA_in[236] = (SAXISRQTDATA[236] === 1'bz) || SAXISRQTDATA_delay[236]; // rv 1 + assign SAXISRQTDATA_in[237] = (SAXISRQTDATA[237] === 1'bz) || SAXISRQTDATA_delay[237]; // rv 1 + assign SAXISRQTDATA_in[238] = (SAXISRQTDATA[238] === 1'bz) || SAXISRQTDATA_delay[238]; // rv 1 + assign SAXISRQTDATA_in[239] = (SAXISRQTDATA[239] === 1'bz) || SAXISRQTDATA_delay[239]; // rv 1 + assign SAXISRQTDATA_in[23] = (SAXISRQTDATA[23] === 1'bz) || SAXISRQTDATA_delay[23]; // rv 1 + assign SAXISRQTDATA_in[240] = (SAXISRQTDATA[240] === 1'bz) || SAXISRQTDATA_delay[240]; // rv 1 + assign SAXISRQTDATA_in[241] = (SAXISRQTDATA[241] === 1'bz) || SAXISRQTDATA_delay[241]; // rv 1 + assign SAXISRQTDATA_in[242] = (SAXISRQTDATA[242] === 1'bz) || SAXISRQTDATA_delay[242]; // rv 1 + assign SAXISRQTDATA_in[243] = (SAXISRQTDATA[243] === 1'bz) || SAXISRQTDATA_delay[243]; // rv 1 + assign SAXISRQTDATA_in[244] = (SAXISRQTDATA[244] === 1'bz) || SAXISRQTDATA_delay[244]; // rv 1 + assign SAXISRQTDATA_in[245] = (SAXISRQTDATA[245] === 1'bz) || SAXISRQTDATA_delay[245]; // rv 1 + assign SAXISRQTDATA_in[246] = (SAXISRQTDATA[246] === 1'bz) || SAXISRQTDATA_delay[246]; // rv 1 + assign SAXISRQTDATA_in[247] = (SAXISRQTDATA[247] === 1'bz) || SAXISRQTDATA_delay[247]; // rv 1 + assign SAXISRQTDATA_in[248] = (SAXISRQTDATA[248] === 1'bz) || SAXISRQTDATA_delay[248]; // rv 1 + assign SAXISRQTDATA_in[249] = (SAXISRQTDATA[249] === 1'bz) || SAXISRQTDATA_delay[249]; // rv 1 + assign SAXISRQTDATA_in[24] = (SAXISRQTDATA[24] === 1'bz) || SAXISRQTDATA_delay[24]; // rv 1 + assign SAXISRQTDATA_in[250] = (SAXISRQTDATA[250] === 1'bz) || SAXISRQTDATA_delay[250]; // rv 1 + assign SAXISRQTDATA_in[251] = (SAXISRQTDATA[251] === 1'bz) || SAXISRQTDATA_delay[251]; // rv 1 + assign SAXISRQTDATA_in[252] = (SAXISRQTDATA[252] === 1'bz) || SAXISRQTDATA_delay[252]; // rv 1 + assign SAXISRQTDATA_in[253] = (SAXISRQTDATA[253] === 1'bz) || SAXISRQTDATA_delay[253]; // rv 1 + assign SAXISRQTDATA_in[254] = (SAXISRQTDATA[254] === 1'bz) || SAXISRQTDATA_delay[254]; // rv 1 + assign SAXISRQTDATA_in[255] = (SAXISRQTDATA[255] === 1'bz) || SAXISRQTDATA_delay[255]; // rv 1 + assign SAXISRQTDATA_in[25] = (SAXISRQTDATA[25] === 1'bz) || SAXISRQTDATA_delay[25]; // rv 1 + assign SAXISRQTDATA_in[26] = (SAXISRQTDATA[26] === 1'bz) || SAXISRQTDATA_delay[26]; // rv 1 + assign SAXISRQTDATA_in[27] = (SAXISRQTDATA[27] === 1'bz) || SAXISRQTDATA_delay[27]; // rv 1 + assign SAXISRQTDATA_in[28] = (SAXISRQTDATA[28] === 1'bz) || SAXISRQTDATA_delay[28]; // rv 1 + assign SAXISRQTDATA_in[29] = (SAXISRQTDATA[29] === 1'bz) || SAXISRQTDATA_delay[29]; // rv 1 + assign SAXISRQTDATA_in[2] = (SAXISRQTDATA[2] === 1'bz) || SAXISRQTDATA_delay[2]; // rv 1 + assign SAXISRQTDATA_in[30] = (SAXISRQTDATA[30] === 1'bz) || SAXISRQTDATA_delay[30]; // rv 1 + assign SAXISRQTDATA_in[31] = (SAXISRQTDATA[31] === 1'bz) || SAXISRQTDATA_delay[31]; // rv 1 + assign SAXISRQTDATA_in[32] = (SAXISRQTDATA[32] === 1'bz) || SAXISRQTDATA_delay[32]; // rv 1 + assign SAXISRQTDATA_in[33] = (SAXISRQTDATA[33] === 1'bz) || SAXISRQTDATA_delay[33]; // rv 1 + assign SAXISRQTDATA_in[34] = (SAXISRQTDATA[34] === 1'bz) || SAXISRQTDATA_delay[34]; // rv 1 + assign SAXISRQTDATA_in[35] = (SAXISRQTDATA[35] === 1'bz) || SAXISRQTDATA_delay[35]; // rv 1 + assign SAXISRQTDATA_in[36] = (SAXISRQTDATA[36] === 1'bz) || SAXISRQTDATA_delay[36]; // rv 1 + assign SAXISRQTDATA_in[37] = (SAXISRQTDATA[37] === 1'bz) || SAXISRQTDATA_delay[37]; // rv 1 + assign SAXISRQTDATA_in[38] = (SAXISRQTDATA[38] === 1'bz) || SAXISRQTDATA_delay[38]; // rv 1 + assign SAXISRQTDATA_in[39] = (SAXISRQTDATA[39] === 1'bz) || SAXISRQTDATA_delay[39]; // rv 1 + assign SAXISRQTDATA_in[3] = (SAXISRQTDATA[3] === 1'bz) || SAXISRQTDATA_delay[3]; // rv 1 + assign SAXISRQTDATA_in[40] = (SAXISRQTDATA[40] === 1'bz) || SAXISRQTDATA_delay[40]; // rv 1 + assign SAXISRQTDATA_in[41] = (SAXISRQTDATA[41] === 1'bz) || SAXISRQTDATA_delay[41]; // rv 1 + assign SAXISRQTDATA_in[42] = (SAXISRQTDATA[42] === 1'bz) || SAXISRQTDATA_delay[42]; // rv 1 + assign SAXISRQTDATA_in[43] = (SAXISRQTDATA[43] === 1'bz) || SAXISRQTDATA_delay[43]; // rv 1 + assign SAXISRQTDATA_in[44] = (SAXISRQTDATA[44] === 1'bz) || SAXISRQTDATA_delay[44]; // rv 1 + assign SAXISRQTDATA_in[45] = (SAXISRQTDATA[45] === 1'bz) || SAXISRQTDATA_delay[45]; // rv 1 + assign SAXISRQTDATA_in[46] = (SAXISRQTDATA[46] === 1'bz) || SAXISRQTDATA_delay[46]; // rv 1 + assign SAXISRQTDATA_in[47] = (SAXISRQTDATA[47] === 1'bz) || SAXISRQTDATA_delay[47]; // rv 1 + assign SAXISRQTDATA_in[48] = (SAXISRQTDATA[48] === 1'bz) || SAXISRQTDATA_delay[48]; // rv 1 + assign SAXISRQTDATA_in[49] = (SAXISRQTDATA[49] === 1'bz) || SAXISRQTDATA_delay[49]; // rv 1 + assign SAXISRQTDATA_in[4] = (SAXISRQTDATA[4] === 1'bz) || SAXISRQTDATA_delay[4]; // rv 1 + assign SAXISRQTDATA_in[50] = (SAXISRQTDATA[50] === 1'bz) || SAXISRQTDATA_delay[50]; // rv 1 + assign SAXISRQTDATA_in[51] = (SAXISRQTDATA[51] === 1'bz) || SAXISRQTDATA_delay[51]; // rv 1 + assign SAXISRQTDATA_in[52] = (SAXISRQTDATA[52] === 1'bz) || SAXISRQTDATA_delay[52]; // rv 1 + assign SAXISRQTDATA_in[53] = (SAXISRQTDATA[53] === 1'bz) || SAXISRQTDATA_delay[53]; // rv 1 + assign SAXISRQTDATA_in[54] = (SAXISRQTDATA[54] === 1'bz) || SAXISRQTDATA_delay[54]; // rv 1 + assign SAXISRQTDATA_in[55] = (SAXISRQTDATA[55] === 1'bz) || SAXISRQTDATA_delay[55]; // rv 1 + assign SAXISRQTDATA_in[56] = (SAXISRQTDATA[56] === 1'bz) || SAXISRQTDATA_delay[56]; // rv 1 + assign SAXISRQTDATA_in[57] = (SAXISRQTDATA[57] === 1'bz) || SAXISRQTDATA_delay[57]; // rv 1 + assign SAXISRQTDATA_in[58] = (SAXISRQTDATA[58] === 1'bz) || SAXISRQTDATA_delay[58]; // rv 1 + assign SAXISRQTDATA_in[59] = (SAXISRQTDATA[59] === 1'bz) || SAXISRQTDATA_delay[59]; // rv 1 + assign SAXISRQTDATA_in[5] = (SAXISRQTDATA[5] === 1'bz) || SAXISRQTDATA_delay[5]; // rv 1 + assign SAXISRQTDATA_in[60] = (SAXISRQTDATA[60] === 1'bz) || SAXISRQTDATA_delay[60]; // rv 1 + assign SAXISRQTDATA_in[61] = (SAXISRQTDATA[61] === 1'bz) || SAXISRQTDATA_delay[61]; // rv 1 + assign SAXISRQTDATA_in[62] = (SAXISRQTDATA[62] === 1'bz) || SAXISRQTDATA_delay[62]; // rv 1 + assign SAXISRQTDATA_in[63] = (SAXISRQTDATA[63] === 1'bz) || SAXISRQTDATA_delay[63]; // rv 1 + assign SAXISRQTDATA_in[64] = (SAXISRQTDATA[64] === 1'bz) || SAXISRQTDATA_delay[64]; // rv 1 + assign SAXISRQTDATA_in[65] = (SAXISRQTDATA[65] === 1'bz) || SAXISRQTDATA_delay[65]; // rv 1 + assign SAXISRQTDATA_in[66] = (SAXISRQTDATA[66] === 1'bz) || SAXISRQTDATA_delay[66]; // rv 1 + assign SAXISRQTDATA_in[67] = (SAXISRQTDATA[67] === 1'bz) || SAXISRQTDATA_delay[67]; // rv 1 + assign SAXISRQTDATA_in[68] = (SAXISRQTDATA[68] === 1'bz) || SAXISRQTDATA_delay[68]; // rv 1 + assign SAXISRQTDATA_in[69] = (SAXISRQTDATA[69] === 1'bz) || SAXISRQTDATA_delay[69]; // rv 1 + assign SAXISRQTDATA_in[6] = (SAXISRQTDATA[6] === 1'bz) || SAXISRQTDATA_delay[6]; // rv 1 + assign SAXISRQTDATA_in[70] = (SAXISRQTDATA[70] === 1'bz) || SAXISRQTDATA_delay[70]; // rv 1 + assign SAXISRQTDATA_in[71] = (SAXISRQTDATA[71] === 1'bz) || SAXISRQTDATA_delay[71]; // rv 1 + assign SAXISRQTDATA_in[72] = (SAXISRQTDATA[72] === 1'bz) || SAXISRQTDATA_delay[72]; // rv 1 + assign SAXISRQTDATA_in[73] = (SAXISRQTDATA[73] === 1'bz) || SAXISRQTDATA_delay[73]; // rv 1 + assign SAXISRQTDATA_in[74] = (SAXISRQTDATA[74] === 1'bz) || SAXISRQTDATA_delay[74]; // rv 1 + assign SAXISRQTDATA_in[75] = (SAXISRQTDATA[75] === 1'bz) || SAXISRQTDATA_delay[75]; // rv 1 + assign SAXISRQTDATA_in[76] = (SAXISRQTDATA[76] === 1'bz) || SAXISRQTDATA_delay[76]; // rv 1 + assign SAXISRQTDATA_in[77] = (SAXISRQTDATA[77] === 1'bz) || SAXISRQTDATA_delay[77]; // rv 1 + assign SAXISRQTDATA_in[78] = (SAXISRQTDATA[78] === 1'bz) || SAXISRQTDATA_delay[78]; // rv 1 + assign SAXISRQTDATA_in[79] = (SAXISRQTDATA[79] === 1'bz) || SAXISRQTDATA_delay[79]; // rv 1 + assign SAXISRQTDATA_in[7] = (SAXISRQTDATA[7] === 1'bz) || SAXISRQTDATA_delay[7]; // rv 1 + assign SAXISRQTDATA_in[80] = (SAXISRQTDATA[80] === 1'bz) || SAXISRQTDATA_delay[80]; // rv 1 + assign SAXISRQTDATA_in[81] = (SAXISRQTDATA[81] === 1'bz) || SAXISRQTDATA_delay[81]; // rv 1 + assign SAXISRQTDATA_in[82] = (SAXISRQTDATA[82] === 1'bz) || SAXISRQTDATA_delay[82]; // rv 1 + assign SAXISRQTDATA_in[83] = (SAXISRQTDATA[83] === 1'bz) || SAXISRQTDATA_delay[83]; // rv 1 + assign SAXISRQTDATA_in[84] = (SAXISRQTDATA[84] === 1'bz) || SAXISRQTDATA_delay[84]; // rv 1 + assign SAXISRQTDATA_in[85] = (SAXISRQTDATA[85] === 1'bz) || SAXISRQTDATA_delay[85]; // rv 1 + assign SAXISRQTDATA_in[86] = (SAXISRQTDATA[86] === 1'bz) || SAXISRQTDATA_delay[86]; // rv 1 + assign SAXISRQTDATA_in[87] = (SAXISRQTDATA[87] === 1'bz) || SAXISRQTDATA_delay[87]; // rv 1 + assign SAXISRQTDATA_in[88] = (SAXISRQTDATA[88] === 1'bz) || SAXISRQTDATA_delay[88]; // rv 1 + assign SAXISRQTDATA_in[89] = (SAXISRQTDATA[89] === 1'bz) || SAXISRQTDATA_delay[89]; // rv 1 + assign SAXISRQTDATA_in[8] = (SAXISRQTDATA[8] === 1'bz) || SAXISRQTDATA_delay[8]; // rv 1 + assign SAXISRQTDATA_in[90] = (SAXISRQTDATA[90] === 1'bz) || SAXISRQTDATA_delay[90]; // rv 1 + assign SAXISRQTDATA_in[91] = (SAXISRQTDATA[91] === 1'bz) || SAXISRQTDATA_delay[91]; // rv 1 + assign SAXISRQTDATA_in[92] = (SAXISRQTDATA[92] === 1'bz) || SAXISRQTDATA_delay[92]; // rv 1 + assign SAXISRQTDATA_in[93] = (SAXISRQTDATA[93] === 1'bz) || SAXISRQTDATA_delay[93]; // rv 1 + assign SAXISRQTDATA_in[94] = (SAXISRQTDATA[94] === 1'bz) || SAXISRQTDATA_delay[94]; // rv 1 + assign SAXISRQTDATA_in[95] = (SAXISRQTDATA[95] === 1'bz) || SAXISRQTDATA_delay[95]; // rv 1 + assign SAXISRQTDATA_in[96] = (SAXISRQTDATA[96] === 1'bz) || SAXISRQTDATA_delay[96]; // rv 1 + assign SAXISRQTDATA_in[97] = (SAXISRQTDATA[97] === 1'bz) || SAXISRQTDATA_delay[97]; // rv 1 + assign SAXISRQTDATA_in[98] = (SAXISRQTDATA[98] === 1'bz) || SAXISRQTDATA_delay[98]; // rv 1 + assign SAXISRQTDATA_in[99] = (SAXISRQTDATA[99] === 1'bz) || SAXISRQTDATA_delay[99]; // rv 1 + assign SAXISRQTDATA_in[9] = (SAXISRQTDATA[9] === 1'bz) || SAXISRQTDATA_delay[9]; // rv 1 + assign SAXISRQTKEEP_in[0] = (SAXISRQTKEEP[0] !== 1'bz) && SAXISRQTKEEP_delay[0]; // rv 0 + assign SAXISRQTKEEP_in[1] = (SAXISRQTKEEP[1] !== 1'bz) && SAXISRQTKEEP_delay[1]; // rv 0 + assign SAXISRQTKEEP_in[2] = (SAXISRQTKEEP[2] !== 1'bz) && SAXISRQTKEEP_delay[2]; // rv 0 + assign SAXISRQTKEEP_in[3] = (SAXISRQTKEEP[3] !== 1'bz) && SAXISRQTKEEP_delay[3]; // rv 0 + assign SAXISRQTKEEP_in[4] = (SAXISRQTKEEP[4] !== 1'bz) && SAXISRQTKEEP_delay[4]; // rv 0 + assign SAXISRQTKEEP_in[5] = (SAXISRQTKEEP[5] !== 1'bz) && SAXISRQTKEEP_delay[5]; // rv 0 + assign SAXISRQTKEEP_in[6] = (SAXISRQTKEEP[6] !== 1'bz) && SAXISRQTKEEP_delay[6]; // rv 0 + assign SAXISRQTKEEP_in[7] = (SAXISRQTKEEP[7] !== 1'bz) && SAXISRQTKEEP_delay[7]; // rv 0 + assign SAXISRQTLAST_in = (SAXISRQTLAST === 1'bz) || SAXISRQTLAST_delay; // rv 1 + assign SAXISRQTUSER_in[0] = (SAXISRQTUSER[0] === 1'bz) || SAXISRQTUSER_delay[0]; // rv 1 + assign SAXISRQTUSER_in[10] = (SAXISRQTUSER[10] === 1'bz) || SAXISRQTUSER_delay[10]; // rv 1 + assign SAXISRQTUSER_in[11] = (SAXISRQTUSER[11] === 1'bz) || SAXISRQTUSER_delay[11]; // rv 1 + assign SAXISRQTUSER_in[12] = (SAXISRQTUSER[12] === 1'bz) || SAXISRQTUSER_delay[12]; // rv 1 + assign SAXISRQTUSER_in[13] = (SAXISRQTUSER[13] === 1'bz) || SAXISRQTUSER_delay[13]; // rv 1 + assign SAXISRQTUSER_in[14] = (SAXISRQTUSER[14] === 1'bz) || SAXISRQTUSER_delay[14]; // rv 1 + assign SAXISRQTUSER_in[15] = (SAXISRQTUSER[15] === 1'bz) || SAXISRQTUSER_delay[15]; // rv 1 + assign SAXISRQTUSER_in[16] = (SAXISRQTUSER[16] === 1'bz) || SAXISRQTUSER_delay[16]; // rv 1 + assign SAXISRQTUSER_in[17] = (SAXISRQTUSER[17] === 1'bz) || SAXISRQTUSER_delay[17]; // rv 1 + assign SAXISRQTUSER_in[18] = (SAXISRQTUSER[18] === 1'bz) || SAXISRQTUSER_delay[18]; // rv 1 + assign SAXISRQTUSER_in[19] = (SAXISRQTUSER[19] === 1'bz) || SAXISRQTUSER_delay[19]; // rv 1 + assign SAXISRQTUSER_in[1] = (SAXISRQTUSER[1] === 1'bz) || SAXISRQTUSER_delay[1]; // rv 1 + assign SAXISRQTUSER_in[20] = (SAXISRQTUSER[20] === 1'bz) || SAXISRQTUSER_delay[20]; // rv 1 + assign SAXISRQTUSER_in[21] = (SAXISRQTUSER[21] === 1'bz) || SAXISRQTUSER_delay[21]; // rv 1 + assign SAXISRQTUSER_in[22] = (SAXISRQTUSER[22] === 1'bz) || SAXISRQTUSER_delay[22]; // rv 1 + assign SAXISRQTUSER_in[23] = (SAXISRQTUSER[23] === 1'bz) || SAXISRQTUSER_delay[23]; // rv 1 + assign SAXISRQTUSER_in[24] = (SAXISRQTUSER[24] === 1'bz) || SAXISRQTUSER_delay[24]; // rv 1 + assign SAXISRQTUSER_in[25] = (SAXISRQTUSER[25] === 1'bz) || SAXISRQTUSER_delay[25]; // rv 1 + assign SAXISRQTUSER_in[26] = (SAXISRQTUSER[26] === 1'bz) || SAXISRQTUSER_delay[26]; // rv 1 + assign SAXISRQTUSER_in[27] = (SAXISRQTUSER[27] === 1'bz) || SAXISRQTUSER_delay[27]; // rv 1 + assign SAXISRQTUSER_in[28] = (SAXISRQTUSER[28] === 1'bz) || SAXISRQTUSER_delay[28]; // rv 1 + assign SAXISRQTUSER_in[29] = (SAXISRQTUSER[29] === 1'bz) || SAXISRQTUSER_delay[29]; // rv 1 + assign SAXISRQTUSER_in[2] = (SAXISRQTUSER[2] === 1'bz) || SAXISRQTUSER_delay[2]; // rv 1 + assign SAXISRQTUSER_in[30] = (SAXISRQTUSER[30] === 1'bz) || SAXISRQTUSER_delay[30]; // rv 1 + assign SAXISRQTUSER_in[31] = (SAXISRQTUSER[31] === 1'bz) || SAXISRQTUSER_delay[31]; // rv 1 + assign SAXISRQTUSER_in[32] = (SAXISRQTUSER[32] === 1'bz) || SAXISRQTUSER_delay[32]; // rv 1 + assign SAXISRQTUSER_in[33] = (SAXISRQTUSER[33] === 1'bz) || SAXISRQTUSER_delay[33]; // rv 1 + assign SAXISRQTUSER_in[34] = (SAXISRQTUSER[34] === 1'bz) || SAXISRQTUSER_delay[34]; // rv 1 + assign SAXISRQTUSER_in[35] = (SAXISRQTUSER[35] === 1'bz) || SAXISRQTUSER_delay[35]; // rv 1 + assign SAXISRQTUSER_in[36] = (SAXISRQTUSER[36] === 1'bz) || SAXISRQTUSER_delay[36]; // rv 1 + assign SAXISRQTUSER_in[37] = (SAXISRQTUSER[37] === 1'bz) || SAXISRQTUSER_delay[37]; // rv 1 + assign SAXISRQTUSER_in[38] = (SAXISRQTUSER[38] === 1'bz) || SAXISRQTUSER_delay[38]; // rv 1 + assign SAXISRQTUSER_in[39] = (SAXISRQTUSER[39] === 1'bz) || SAXISRQTUSER_delay[39]; // rv 1 + assign SAXISRQTUSER_in[3] = (SAXISRQTUSER[3] === 1'bz) || SAXISRQTUSER_delay[3]; // rv 1 + assign SAXISRQTUSER_in[40] = (SAXISRQTUSER[40] === 1'bz) || SAXISRQTUSER_delay[40]; // rv 1 + assign SAXISRQTUSER_in[41] = (SAXISRQTUSER[41] === 1'bz) || SAXISRQTUSER_delay[41]; // rv 1 + assign SAXISRQTUSER_in[42] = (SAXISRQTUSER[42] === 1'bz) || SAXISRQTUSER_delay[42]; // rv 1 + assign SAXISRQTUSER_in[43] = (SAXISRQTUSER[43] === 1'bz) || SAXISRQTUSER_delay[43]; // rv 1 + assign SAXISRQTUSER_in[44] = (SAXISRQTUSER[44] === 1'bz) || SAXISRQTUSER_delay[44]; // rv 1 + assign SAXISRQTUSER_in[45] = (SAXISRQTUSER[45] === 1'bz) || SAXISRQTUSER_delay[45]; // rv 1 + assign SAXISRQTUSER_in[46] = (SAXISRQTUSER[46] === 1'bz) || SAXISRQTUSER_delay[46]; // rv 1 + assign SAXISRQTUSER_in[47] = (SAXISRQTUSER[47] === 1'bz) || SAXISRQTUSER_delay[47]; // rv 1 + assign SAXISRQTUSER_in[48] = (SAXISRQTUSER[48] === 1'bz) || SAXISRQTUSER_delay[48]; // rv 1 + assign SAXISRQTUSER_in[49] = (SAXISRQTUSER[49] === 1'bz) || SAXISRQTUSER_delay[49]; // rv 1 + assign SAXISRQTUSER_in[4] = (SAXISRQTUSER[4] === 1'bz) || SAXISRQTUSER_delay[4]; // rv 1 + assign SAXISRQTUSER_in[50] = (SAXISRQTUSER[50] === 1'bz) || SAXISRQTUSER_delay[50]; // rv 1 + assign SAXISRQTUSER_in[51] = (SAXISRQTUSER[51] === 1'bz) || SAXISRQTUSER_delay[51]; // rv 1 + assign SAXISRQTUSER_in[52] = (SAXISRQTUSER[52] === 1'bz) || SAXISRQTUSER_delay[52]; // rv 1 + assign SAXISRQTUSER_in[53] = (SAXISRQTUSER[53] === 1'bz) || SAXISRQTUSER_delay[53]; // rv 1 + assign SAXISRQTUSER_in[54] = (SAXISRQTUSER[54] === 1'bz) || SAXISRQTUSER_delay[54]; // rv 1 + assign SAXISRQTUSER_in[55] = (SAXISRQTUSER[55] === 1'bz) || SAXISRQTUSER_delay[55]; // rv 1 + assign SAXISRQTUSER_in[56] = (SAXISRQTUSER[56] === 1'bz) || SAXISRQTUSER_delay[56]; // rv 1 + assign SAXISRQTUSER_in[57] = (SAXISRQTUSER[57] === 1'bz) || SAXISRQTUSER_delay[57]; // rv 1 + assign SAXISRQTUSER_in[58] = (SAXISRQTUSER[58] === 1'bz) || SAXISRQTUSER_delay[58]; // rv 1 + assign SAXISRQTUSER_in[59] = (SAXISRQTUSER[59] === 1'bz) || SAXISRQTUSER_delay[59]; // rv 1 + assign SAXISRQTUSER_in[5] = (SAXISRQTUSER[5] === 1'bz) || SAXISRQTUSER_delay[5]; // rv 1 + assign SAXISRQTUSER_in[6] = (SAXISRQTUSER[6] === 1'bz) || SAXISRQTUSER_delay[6]; // rv 1 + assign SAXISRQTUSER_in[7] = (SAXISRQTUSER[7] === 1'bz) || SAXISRQTUSER_delay[7]; // rv 1 + assign SAXISRQTUSER_in[8] = (SAXISRQTUSER[8] === 1'bz) || SAXISRQTUSER_delay[8]; // rv 1 + assign SAXISRQTUSER_in[9] = (SAXISRQTUSER[9] === 1'bz) || SAXISRQTUSER_delay[9]; // rv 1 + assign SAXISRQTVALID_in = (SAXISRQTVALID !== 1'bz) && SAXISRQTVALID_delay; // rv 0 + assign SPAREIN_in[0] = (SPAREIN[0] === 1'bz) || SPAREIN_delay[0]; // rv 1 + assign SPAREIN_in[10] = (SPAREIN[10] === 1'bz) || SPAREIN_delay[10]; // rv 1 + assign SPAREIN_in[11] = (SPAREIN[11] === 1'bz) || SPAREIN_delay[11]; // rv 1 + assign SPAREIN_in[12] = (SPAREIN[12] === 1'bz) || SPAREIN_delay[12]; // rv 1 + assign SPAREIN_in[13] = (SPAREIN[13] === 1'bz) || SPAREIN_delay[13]; // rv 1 + assign SPAREIN_in[14] = (SPAREIN[14] === 1'bz) || SPAREIN_delay[14]; // rv 1 + assign SPAREIN_in[15] = (SPAREIN[15] === 1'bz) || SPAREIN_delay[15]; // rv 1 + assign SPAREIN_in[16] = (SPAREIN[16] === 1'bz) || SPAREIN_delay[16]; // rv 1 + assign SPAREIN_in[17] = (SPAREIN[17] === 1'bz) || SPAREIN_delay[17]; // rv 1 + assign SPAREIN_in[18] = (SPAREIN[18] === 1'bz) || SPAREIN_delay[18]; // rv 1 + assign SPAREIN_in[19] = (SPAREIN[19] === 1'bz) || SPAREIN_delay[19]; // rv 1 + assign SPAREIN_in[1] = (SPAREIN[1] === 1'bz) || SPAREIN_delay[1]; // rv 1 + assign SPAREIN_in[20] = (SPAREIN[20] === 1'bz) || SPAREIN_delay[20]; // rv 1 + assign SPAREIN_in[21] = (SPAREIN[21] === 1'bz) || SPAREIN_delay[21]; // rv 1 + assign SPAREIN_in[22] = (SPAREIN[22] === 1'bz) || SPAREIN_delay[22]; // rv 1 + assign SPAREIN_in[23] = (SPAREIN[23] === 1'bz) || SPAREIN_delay[23]; // rv 1 + assign SPAREIN_in[24] = (SPAREIN[24] === 1'bz) || SPAREIN_delay[24]; // rv 1 + assign SPAREIN_in[25] = (SPAREIN[25] === 1'bz) || SPAREIN_delay[25]; // rv 1 + assign SPAREIN_in[26] = (SPAREIN[26] === 1'bz) || SPAREIN_delay[26]; // rv 1 + assign SPAREIN_in[27] = (SPAREIN[27] === 1'bz) || SPAREIN_delay[27]; // rv 1 + assign SPAREIN_in[28] = (SPAREIN[28] === 1'bz) || SPAREIN_delay[28]; // rv 1 + assign SPAREIN_in[29] = (SPAREIN[29] === 1'bz) || SPAREIN_delay[29]; // rv 1 + assign SPAREIN_in[2] = (SPAREIN[2] === 1'bz) || SPAREIN_delay[2]; // rv 1 + assign SPAREIN_in[30] = (SPAREIN[30] === 1'bz) || SPAREIN_delay[30]; // rv 1 + assign SPAREIN_in[31] = (SPAREIN[31] === 1'bz) || SPAREIN_delay[31]; // rv 1 + assign SPAREIN_in[3] = (SPAREIN[3] === 1'bz) || SPAREIN_delay[3]; // rv 1 + assign SPAREIN_in[4] = (SPAREIN[4] === 1'bz) || SPAREIN_delay[4]; // rv 1 + assign SPAREIN_in[5] = (SPAREIN[5] === 1'bz) || SPAREIN_delay[5]; // rv 1 + assign SPAREIN_in[6] = (SPAREIN[6] === 1'bz) || SPAREIN_delay[6]; // rv 1 + assign SPAREIN_in[7] = (SPAREIN[7] === 1'bz) || SPAREIN_delay[7]; // rv 1 + assign SPAREIN_in[8] = (SPAREIN[8] === 1'bz) || SPAREIN_delay[8]; // rv 1 + assign SPAREIN_in[9] = (SPAREIN[9] === 1'bz) || SPAREIN_delay[9]; // rv 1 + assign USERCLK_in = (USERCLK !== 1'bz) && USERCLK_delay; // rv 0 + + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((ARI_CAP_ENABLE_REG != "FALSE") && + (ARI_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute ARI_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ARI_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_CC_ALIGNMENT_MODE_REG != "FALSE") && + (AXISTEN_IF_CC_ALIGNMENT_MODE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_CC_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_CC_ALIGNMENT_MODE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_CC_PARITY_CHK_REG != "TRUE") && + (AXISTEN_IF_CC_PARITY_CHK_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_CC_PARITY_CHK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AXISTEN_IF_CC_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_CQ_ALIGNMENT_MODE_REG != "FALSE") && + (AXISTEN_IF_CQ_ALIGNMENT_MODE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_CQ_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_CQ_ALIGNMENT_MODE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "FALSE") && + (AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_ENABLE_CLIENT_TAG on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_ENABLE_CLIENT_TAG_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "FALSE") && + (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_ENABLE_RX_MSG_INTFC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_RC_ALIGNMENT_MODE_REG != "FALSE") && + (AXISTEN_IF_RC_ALIGNMENT_MODE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_RC_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RC_ALIGNMENT_MODE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_RC_STRADDLE_REG != "FALSE") && + (AXISTEN_IF_RC_STRADDLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_RC_STRADDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RC_STRADDLE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_RQ_ALIGNMENT_MODE_REG != "FALSE") && + (AXISTEN_IF_RQ_ALIGNMENT_MODE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_RQ_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RQ_ALIGNMENT_MODE_REG); + attr_err = 1'b1; + end + + if ((AXISTEN_IF_RQ_PARITY_CHK_REG != "TRUE") && + (AXISTEN_IF_RQ_PARITY_CHK_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute AXISTEN_IF_RQ_PARITY_CHK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AXISTEN_IF_RQ_PARITY_CHK_REG); + attr_err = 1'b1; + end + + if ((CRM_CORE_CLK_FREQ_500_REG != "TRUE") && + (CRM_CORE_CLK_FREQ_500_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute CRM_CORE_CLK_FREQ_500 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CRM_CORE_CLK_FREQ_500_REG); + attr_err = 1'b1; + end + + if ((DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG != "FALSE") && + (DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") && + (DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute DEBUG_PL_DISABLE_EI_INFER_IN_L0 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG); + attr_err = 1'b1; + end + + if ((DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "FALSE") && + (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG); + attr_err = 1'b1; + end + + if ((LL_ACK_TIMEOUT_EN_REG != "FALSE") && + (LL_ACK_TIMEOUT_EN_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_ACK_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_ACK_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((LL_ACK_TIMEOUT_FUNC_REG != 0) && + (LL_ACK_TIMEOUT_FUNC_REG != 1) && + (LL_ACK_TIMEOUT_FUNC_REG != 2) && + (LL_ACK_TIMEOUT_FUNC_REG != 3)) begin + $display("Attribute Syntax Error : The attribute LL_ACK_TIMEOUT_FUNC on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, LL_ACK_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") && + (LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_CPL_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((LL_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") && + (LL_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_FC_UPDATE_TIMER_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") && + (LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_NP_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((LL_P_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") && + (LL_P_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_P_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_P_FC_UPDATE_TIMER_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((LL_REPLAY_TIMEOUT_EN_REG != "FALSE") && + (LL_REPLAY_TIMEOUT_EN_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LL_REPLAY_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_REPLAY_TIMEOUT_EN_REG); + attr_err = 1'b1; + end + + if ((LL_REPLAY_TIMEOUT_FUNC_REG != 0) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 1) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 2) && + (LL_REPLAY_TIMEOUT_FUNC_REG != 3)) begin + $display("Attribute Syntax Error : The attribute LL_REPLAY_TIMEOUT_FUNC on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, LL_REPLAY_TIMEOUT_FUNC_REG); + attr_err = 1'b1; + end + + if ((LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG); + attr_err = 1'b1; + end + + if ((LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "FALSE") && + (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute LTR_TX_MESSAGE_ON_LTR_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LTR_TX_MESSAGE_ON_LTR_ENABLE_REG); + attr_err = 1'b1; + end + + if ((MCAP_CONFIGURE_OVERRIDE_REG != "FALSE") && + (MCAP_CONFIGURE_OVERRIDE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_CONFIGURE_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_CONFIGURE_OVERRIDE_REG); + attr_err = 1'b1; + end + + if ((MCAP_ENABLE_REG != "FALSE") && + (MCAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((MCAP_EOS_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_EOS_DESIGN_SWITCH_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_EOS_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_EOS_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_GATE_IO_ENABLE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "FALSE") && + (MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_INPUT_GATE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INPUT_GATE_DESIGN_SWITCH_REG); + attr_err = 1'b1; + end + + if ((MCAP_INTERRUPT_ON_MCAP_EOS_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_EOS_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_INTERRUPT_ON_MCAP_EOS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_EOS_REG); + attr_err = 1'b1; + end + + if ((MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "FALSE") && + (MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute MCAP_INTERRUPT_ON_MCAP_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_ERROR_REG); + attr_err = 1'b1; + end + + if ((PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") && + (PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") && + (PF0_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_AER_CAP_ECRC_GEN_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "FALSE") && + (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_ARI_FORWARD_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "TRUE") && + (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_LTR_SUPPORT_REG != "TRUE") && + (PF0_DEV_CAP2_LTR_SUPPORT_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_LTR_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_LTR_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "FALSE") && + (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP_ENDPOINT_L0S_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 0) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 1) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 2) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 3) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 4) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 5) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 6) && + (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP_ENDPOINT_L1_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "TRUE") && + (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG); + attr_err = 1'b1; + end + + if ((PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "TRUE") && + (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") && + (PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG); + attr_err = 1'b1; + end + + if ((PF0_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF0_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_ASPM_SUPPORT_REG != 0) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 1) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 2) && + (PF0_LINK_CAP_ASPM_SUPPORT_REG != 3)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_ASPM_SUPPORT on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PF0_LINK_CAP_ASPM_SUPPORT_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 7) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 0) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 1) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 2) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 3) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 4) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 5) && + (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 6)) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG); + attr_err = 1'b1; + end + + if ((PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "TRUE") && + (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_LINK_STATUS_SLOT_CLOCK_CONFIG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG); + attr_err = 1'b1; + end + + if ((PF0_MSIX_CAP_PBA_BIR_REG != 0) && + (PF0_MSIX_CAP_PBA_BIR_REG != 1) && + (PF0_MSIX_CAP_PBA_BIR_REG != 2) && + (PF0_MSIX_CAP_PBA_BIR_REG != 3) && + (PF0_MSIX_CAP_PBA_BIR_REG != 4) && + (PF0_MSIX_CAP_PBA_BIR_REG != 5) && + (PF0_MSIX_CAP_PBA_BIR_REG != 6) && + (PF0_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF0_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((PF0_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF0_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF0_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((PF0_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF0_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF0_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((PF0_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF0_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((PF0_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") && + (PF0_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_PB_CAP_SYSTEM_ALLOCATED_REG); + attr_err = 1'b1; + end + + if ((PF0_PM_CAP_PMESUPPORT_D0_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D0_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D0_REG); + attr_err = 1'b1; + end + + if ((PF0_PM_CAP_PMESUPPORT_D1_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D1_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D1_REG); + attr_err = 1'b1; + end + + if ((PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "TRUE") && + (PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D3HOT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D3HOT_REG); + attr_err = 1'b1; + end + + if ((PF0_PM_CAP_SUPP_D1_STATE_REG != "TRUE") && + (PF0_PM_CAP_SUPP_D1_STATE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_PM_CAP_SUPP_D1_STATE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_SUPP_D1_STATE_REG); + attr_err = 1'b1; + end + + if ((PF0_PM_CSR_NOSOFTRESET_REG != "TRUE") && + (PF0_PM_CSR_NOSOFTRESET_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_PM_CSR_NOSOFTRESET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CSR_NOSOFTRESET_REG); + attr_err = 1'b1; + end + + if ((PF0_RBAR_CAP_ENABLE_REG != "FALSE") && + (PF0_RBAR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_RBAR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF0_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF0_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF0_VC_CAP_ENABLE_REG != "FALSE") && + (PF0_VC_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF0_VC_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_VC_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") && + (PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") && + (PF1_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_AER_CAP_ECRC_GEN_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") && + (PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF1_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG); + attr_err = 1'b1; + end + + if ((PF1_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF1_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_MSIX_CAP_PBA_BIR_REG != 0) && + (PF1_MSIX_CAP_PBA_BIR_REG != 1) && + (PF1_MSIX_CAP_PBA_BIR_REG != 2) && + (PF1_MSIX_CAP_PBA_BIR_REG != 3) && + (PF1_MSIX_CAP_PBA_BIR_REG != 4) && + (PF1_MSIX_CAP_PBA_BIR_REG != 5) && + (PF1_MSIX_CAP_PBA_BIR_REG != 6) && + (PF1_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF1_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((PF1_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF1_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF1_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((PF1_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF1_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF1_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((PF1_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF1_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((PF1_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") && + (PF1_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_PB_CAP_SYSTEM_ALLOCATED_REG); + attr_err = 1'b1; + end + + if ((PF1_RBAR_CAP_ENABLE_REG != "FALSE") && + (PF1_RBAR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_RBAR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF1_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF1_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF1_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF1_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") && + (PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF2_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") && + (PF2_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_AER_CAP_ECRC_GEN_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") && + (PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF2_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG); + attr_err = 1'b1; + end + + if ((PF2_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF2_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF2_MSIX_CAP_PBA_BIR_REG != 0) && + (PF2_MSIX_CAP_PBA_BIR_REG != 1) && + (PF2_MSIX_CAP_PBA_BIR_REG != 2) && + (PF2_MSIX_CAP_PBA_BIR_REG != 3) && + (PF2_MSIX_CAP_PBA_BIR_REG != 4) && + (PF2_MSIX_CAP_PBA_BIR_REG != 5) && + (PF2_MSIX_CAP_PBA_BIR_REG != 6) && + (PF2_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF2_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((PF2_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF2_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF2_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((PF2_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF2_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF2_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((PF2_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF2_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((PF2_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") && + (PF2_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_PB_CAP_SYSTEM_ALLOCATED_REG); + attr_err = 1'b1; + end + + if ((PF2_RBAR_CAP_ENABLE_REG != "FALSE") && + (PF2_RBAR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_RBAR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF2_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF2_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF2_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF2_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") && + (PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF3_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") && + (PF3_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_AER_CAP_ECRC_GEN_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") && + (PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF3_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG); + attr_err = 1'b1; + end + + if ((PF3_EXPANSION_ROM_ENABLE_REG != "FALSE") && + (PF3_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_EXPANSION_ROM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF3_MSIX_CAP_PBA_BIR_REG != 0) && + (PF3_MSIX_CAP_PBA_BIR_REG != 1) && + (PF3_MSIX_CAP_PBA_BIR_REG != 2) && + (PF3_MSIX_CAP_PBA_BIR_REG != 3) && + (PF3_MSIX_CAP_PBA_BIR_REG != 4) && + (PF3_MSIX_CAP_PBA_BIR_REG != 5) && + (PF3_MSIX_CAP_PBA_BIR_REG != 6) && + (PF3_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF3_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((PF3_MSIX_CAP_TABLE_BIR_REG != 0) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 1) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 2) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 3) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 4) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 5) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 6) && + (PF3_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF3_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((PF3_MSI_CAP_MULTIMSGCAP_REG != 0) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 1) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 2) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 3) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 4) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 5) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 6) && + (PF3_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute PF3_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((PF3_MSI_CAP_PERVECMASKCAP_REG != "FALSE") && + (PF3_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_MSI_CAP_PERVECMASKCAP_REG); + attr_err = 1'b1; + end + + if ((PF3_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") && + (PF3_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_PB_CAP_SYSTEM_ALLOCATED_REG); + attr_err = 1'b1; + end + + if ((PF3_RBAR_CAP_ENABLE_REG != "FALSE") && + (PF3_RBAR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_RBAR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((PF3_TPHR_CAP_ENABLE_REG != "FALSE") && + (PF3_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((PF3_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (PF3_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "FALSE") && + (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "FALSE") && + (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") && + (PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_EI_INFER_IN_L0 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_EI_INFER_IN_L0_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_GEN3_DC_BALANCE_REG != "FALSE") && + (PL_DISABLE_GEN3_DC_BALANCE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_GEN3_DC_BALANCE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_GEN3_DC_BALANCE_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG != "TRUE") && + (PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "FALSE") && + (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_RETRAIN_ON_FRAMING_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_SCRAMBLING_REG != "FALSE") && + (PL_DISABLE_SCRAMBLING_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_SCRAMBLING on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_SCRAMBLING_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG != "FALSE") && + (PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_SYNC_HEADER_FRAMING_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG); + attr_err = 1'b1; + end + + if ((PL_DISABLE_UPCONFIG_CAPABLE_REG != "FALSE") && + (PL_DISABLE_UPCONFIG_CAPABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_DISABLE_UPCONFIG_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_UPCONFIG_CAPABLE_REG); + attr_err = 1'b1; + end + + if ((PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG != "FALSE") && + (PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_EQ_ADAPT_DISABLE_COEFF_CHECK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG); + attr_err = 1'b1; + end + + if ((PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG != "FALSE") && + (PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_EQ_ADAPT_DISABLE_PRESET_CHECK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG); + attr_err = 1'b1; + end + + if ((PL_EQ_BYPASS_PHASE23_REG != "FALSE") && + (PL_EQ_BYPASS_PHASE23_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_EQ_BYPASS_PHASE23 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_BYPASS_PHASE23_REG); + attr_err = 1'b1; + end + + if ((PL_EQ_PHASE01_RX_ADAPT_REG != "FALSE") && + (PL_EQ_PHASE01_RX_ADAPT_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_EQ_PHASE01_RX_ADAPT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_PHASE01_RX_ADAPT_REG); + attr_err = 1'b1; + end + + if ((PL_EQ_SHORT_ADAPT_PHASE_REG != "FALSE") && + (PL_EQ_SHORT_ADAPT_PHASE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_EQ_SHORT_ADAPT_PHASE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_SHORT_ADAPT_PHASE_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_COMCLK_GEN1_REG < 0) || (PL_N_FTS_COMCLK_GEN1_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN1_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_COMCLK_GEN2_REG < 0) || (PL_N_FTS_COMCLK_GEN2_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN2_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_COMCLK_GEN3_REG < 0) || (PL_N_FTS_COMCLK_GEN3_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN3_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_GEN1_REG < 0) || (PL_N_FTS_GEN1_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN1_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_GEN2_REG < 0) || (PL_N_FTS_GEN2_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN2_REG); + attr_err = 1'b1; + end + + if ((PL_N_FTS_GEN3_REG < 0) || (PL_N_FTS_GEN3_REG > 255)) begin + $display("Attribute Syntax Error : The attribute PL_N_FTS_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN3_REG); + attr_err = 1'b1; + end + + if ((PL_REPORT_ALL_PHY_ERRORS_REG != "TRUE") && + (PL_REPORT_ALL_PHY_ERRORS_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PL_REPORT_ALL_PHY_ERRORS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PL_REPORT_ALL_PHY_ERRORS_REG); + attr_err = 1'b1; + end + + if ((PL_SIM_FAST_LINK_TRAINING_REG != "FALSE") && + (PL_SIM_FAST_LINK_TRAINING_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PL_SIM_FAST_LINK_TRAINING on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_SIM_FAST_LINK_TRAINING_REG); + attr_err = 1'b1; + end + + if ((PL_UPSTREAM_FACING_REG != "TRUE") && + (PL_UPSTREAM_FACING_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PL_UPSTREAM_FACING on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PL_UPSTREAM_FACING_REG); + attr_err = 1'b1; + end + + if ((PM_ENABLE_L23_ENTRY_REG != "FALSE") && + (PM_ENABLE_L23_ENTRY_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute PM_ENABLE_L23_ENTRY on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PM_ENABLE_L23_ENTRY_REG); + attr_err = 1'b1; + end + + if ((PM_ENABLE_SLOT_POWER_CAPTURE_REG != "TRUE") && + (PM_ENABLE_SLOT_POWER_CAPTURE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute PM_ENABLE_SLOT_POWER_CAPTURE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_ENABLE_SLOT_POWER_CAPTURE_REG); + attr_err = 1'b1; + end + + if ((SIM_VERSION_REG != "1.0") && + (SIM_VERSION_REG != "1.1") && + (SIM_VERSION_REG != "1.2") && + (SIM_VERSION_REG != "1.3") && + (SIM_VERSION_REG != "2.0") && + (SIM_VERSION_REG != "3.0") && + (SIM_VERSION_REG != "4.0")) begin + $display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0 or 4.0.", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT0_REG != 0) && + (SPARE_BIT0_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT0_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT1_REG != 0) && + (SPARE_BIT1_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT1_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT2_REG != 0) && + (SPARE_BIT2_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT2_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT3_REG != 0) && + (SPARE_BIT3_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT3_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT4_REG != 0) && + (SPARE_BIT4_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT4 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT4_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT5_REG != 0) && + (SPARE_BIT5_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT5 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT5_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT6_REG != 0) && + (SPARE_BIT6_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT6 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT6_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT7_REG != 0) && + (SPARE_BIT7_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT7 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT7_REG); + attr_err = 1'b1; + end + + if ((SPARE_BIT8_REG != 0) && + (SPARE_BIT8_REG != 1)) begin + $display("Attribute Syntax Error : The attribute SPARE_BIT8 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT8_REG); + attr_err = 1'b1; + end + + if ((SRIOV_CAP_ENABLE_REG != "FALSE") && + (SRIOV_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute SRIOV_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SRIOV_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TL_COMPLETION_RAM_SIZE_16K_REG != "TRUE") && + (TL_COMPLETION_RAM_SIZE_16K_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute TL_COMPLETION_RAM_SIZE_16K on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_COMPLETION_RAM_SIZE_16K_REG); + attr_err = 1'b1; + end + + if ((TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG != "TRUE") && + (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute TL_ENABLE_MESSAGE_RID_CHECK_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") && + (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TL_LEGACY_MODE_ENABLE_REG != "FALSE") && + (TL_LEGACY_MODE_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute TL_LEGACY_MODE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_LEGACY_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TL_TX_MUX_STRICT_PRIORITY_REG != "TRUE") && + (TL_TX_MUX_STRICT_PRIORITY_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute TL_TX_MUX_STRICT_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_TX_MUX_STRICT_PRIORITY_REG); + attr_err = 1'b1; + end + + if ((TWO_LAYER_MODE_DLCMSM_ENABLE_REG != "TRUE") && + (TWO_LAYER_MODE_DLCMSM_ENABLE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_DLCMSM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TWO_LAYER_MODE_DLCMSM_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TWO_LAYER_MODE_ENABLE_REG != "FALSE") && + (TWO_LAYER_MODE_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TWO_LAYER_MODE_ENABLE_REG); + attr_err = 1'b1; + end + + if ((TWO_LAYER_MODE_WIDTH_256_REG != "TRUE") && + (TWO_LAYER_MODE_WIDTH_256_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_WIDTH_256 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TWO_LAYER_MODE_WIDTH_256_REG); + attr_err = 1'b1; + end + + if ((VF0_MSIX_CAP_PBA_BIR_REG != 0) && + (VF0_MSIX_CAP_PBA_BIR_REG != 1) && + (VF0_MSIX_CAP_PBA_BIR_REG != 2) && + (VF0_MSIX_CAP_PBA_BIR_REG != 3) && + (VF0_MSIX_CAP_PBA_BIR_REG != 4) && + (VF0_MSIX_CAP_PBA_BIR_REG != 5) && + (VF0_MSIX_CAP_PBA_BIR_REG != 6) && + (VF0_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF0_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF0_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF0_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF0_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF0_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF0_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF0_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF0_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF0_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF0_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF0_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF1_MSIX_CAP_PBA_BIR_REG != 0) && + (VF1_MSIX_CAP_PBA_BIR_REG != 1) && + (VF1_MSIX_CAP_PBA_BIR_REG != 2) && + (VF1_MSIX_CAP_PBA_BIR_REG != 3) && + (VF1_MSIX_CAP_PBA_BIR_REG != 4) && + (VF1_MSIX_CAP_PBA_BIR_REG != 5) && + (VF1_MSIX_CAP_PBA_BIR_REG != 6) && + (VF1_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF1_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF1_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF1_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF1_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF1_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF1_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF1_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF1_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF1_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF1_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF1_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF1_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF1_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF2_MSIX_CAP_PBA_BIR_REG != 0) && + (VF2_MSIX_CAP_PBA_BIR_REG != 1) && + (VF2_MSIX_CAP_PBA_BIR_REG != 2) && + (VF2_MSIX_CAP_PBA_BIR_REG != 3) && + (VF2_MSIX_CAP_PBA_BIR_REG != 4) && + (VF2_MSIX_CAP_PBA_BIR_REG != 5) && + (VF2_MSIX_CAP_PBA_BIR_REG != 6) && + (VF2_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF2_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF2_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF2_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF2_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF2_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF2_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF2_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF2_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF2_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF2_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF2_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF2_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF2_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF3_MSIX_CAP_PBA_BIR_REG != 0) && + (VF3_MSIX_CAP_PBA_BIR_REG != 1) && + (VF3_MSIX_CAP_PBA_BIR_REG != 2) && + (VF3_MSIX_CAP_PBA_BIR_REG != 3) && + (VF3_MSIX_CAP_PBA_BIR_REG != 4) && + (VF3_MSIX_CAP_PBA_BIR_REG != 5) && + (VF3_MSIX_CAP_PBA_BIR_REG != 6) && + (VF3_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF3_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF3_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF3_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF3_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF3_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF3_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF3_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF3_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF3_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF3_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF3_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF3_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF3_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF4_MSIX_CAP_PBA_BIR_REG != 0) && + (VF4_MSIX_CAP_PBA_BIR_REG != 1) && + (VF4_MSIX_CAP_PBA_BIR_REG != 2) && + (VF4_MSIX_CAP_PBA_BIR_REG != 3) && + (VF4_MSIX_CAP_PBA_BIR_REG != 4) && + (VF4_MSIX_CAP_PBA_BIR_REG != 5) && + (VF4_MSIX_CAP_PBA_BIR_REG != 6) && + (VF4_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF4_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF4_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF4_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF4_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF4_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF4_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF4_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF4_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF4_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF4_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF4_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF4_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF4_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF5_MSIX_CAP_PBA_BIR_REG != 0) && + (VF5_MSIX_CAP_PBA_BIR_REG != 1) && + (VF5_MSIX_CAP_PBA_BIR_REG != 2) && + (VF5_MSIX_CAP_PBA_BIR_REG != 3) && + (VF5_MSIX_CAP_PBA_BIR_REG != 4) && + (VF5_MSIX_CAP_PBA_BIR_REG != 5) && + (VF5_MSIX_CAP_PBA_BIR_REG != 6) && + (VF5_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF5_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF5_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF5_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF5_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF5_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF5_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF5_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF5_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF5_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF5_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF5_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF5_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF5_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF6_MSIX_CAP_PBA_BIR_REG != 0) && + (VF6_MSIX_CAP_PBA_BIR_REG != 1) && + (VF6_MSIX_CAP_PBA_BIR_REG != 2) && + (VF6_MSIX_CAP_PBA_BIR_REG != 3) && + (VF6_MSIX_CAP_PBA_BIR_REG != 4) && + (VF6_MSIX_CAP_PBA_BIR_REG != 5) && + (VF6_MSIX_CAP_PBA_BIR_REG != 6) && + (VF6_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF6_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF6_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF6_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF6_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF6_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF6_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF6_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF6_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF6_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF6_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF6_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF6_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF6_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF7_MSIX_CAP_PBA_BIR_REG != 0) && + (VF7_MSIX_CAP_PBA_BIR_REG != 1) && + (VF7_MSIX_CAP_PBA_BIR_REG != 2) && + (VF7_MSIX_CAP_PBA_BIR_REG != 3) && + (VF7_MSIX_CAP_PBA_BIR_REG != 4) && + (VF7_MSIX_CAP_PBA_BIR_REG != 5) && + (VF7_MSIX_CAP_PBA_BIR_REG != 6) && + (VF7_MSIX_CAP_PBA_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF7_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSIX_CAP_PBA_BIR_REG); + attr_err = 1'b1; + end + + if ((VF7_MSIX_CAP_TABLE_BIR_REG != 0) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 1) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 2) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 3) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 4) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 5) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 6) && + (VF7_MSIX_CAP_TABLE_BIR_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF7_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSIX_CAP_TABLE_BIR_REG); + attr_err = 1'b1; + end + + if ((VF7_MSI_CAP_MULTIMSGCAP_REG != 0) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 1) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 2) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 3) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 4) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 5) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 6) && + (VF7_MSI_CAP_MULTIMSGCAP_REG != 7)) begin + $display("Attribute Syntax Error : The attribute VF7_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSI_CAP_MULTIMSGCAP_REG); + attr_err = 1'b1; + end + + if ((VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") && + (VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG); + attr_err = 1'b1; + end + + if ((VF7_TPHR_CAP_ENABLE_REG != "FALSE") && + (VF7_TPHR_CAP_ENABLE_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF7_TPHR_CAP_ENABLE_REG); + attr_err = 1'b1; + end + + if ((VF7_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") && + (VF7_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin + $display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF7_TPHR_CAP_INT_VEC_MODE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign XILUNCONNCLK_in = 951'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + + assign PMVDIVIDE_in = 2'b11; // tie off + assign PMVENABLEN_in = 1'b1; // tie off + assign PMVSELECT_in = 3'b111; // tie off + assign SCANENABLEN_in = 1'b1; // tie off + assign SCANIN_in = 96'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign SCANMODEN_in = 1'b1; // tie off + assign XILUNCONNBYP_in = 1920'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + assign XILUNCONNIN_in = 3189'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + + SIP_PCIE_3_1 # ( +.MCAP_ENABLE_PAR (MCAP_ENABLE), +.SIM_JTAG_IDCODE (SIM_JTAG_IDCODE) +) SIP_PCIE_3_1_INST ( + + .ARI_CAP_ENABLE (ARI_CAP_ENABLE_REG), + .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK_REG), + .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG_REG), + .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE_REG), + .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG), + .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE_REG), + .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE_REG), + .AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK_REG), + .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH_REG), + .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500_REG), + .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ_REG), + .DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE (DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG), + .DEBUG_PL_DISABLE_EI_INFER_IN_L0 (DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG), + .DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM_REG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT_REG), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN_REG), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC_REG), + .LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER_REG), + .LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG), + .LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER_REG), + .LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE_REG), + .LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER_REG), + .LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG), + .LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER_REG), + .LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE_REG), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT_REG), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN_REG), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC_REG), + .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG), + .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG), + .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG), + .MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR_REG), + .MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE_REG), + .MCAP_ENABLE (MCAP_ENABLE_REG), + .MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH_REG), + .MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION_REG), + .MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG), + .MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG), + .MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH_REG), + .MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS_REG), + .MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR_REG), + .MCAP_VSEC_ID (MCAP_VSEC_ID_REG), + .MCAP_VSEC_LEN (MCAP_VSEC_LEN_REG), + .MCAP_VSEC_REV (MCAP_VSEC_REV_REG), + .PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG), + .PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE_REG), + .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR_REG), + .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC_REG), + .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER_REG), + .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE_REG), + .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL_REG), + .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE_REG), + .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL_REG), + .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE_REG), + .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL_REG), + .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE_REG), + .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL_REG), + .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE_REG), + .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL_REG), + .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE_REG), + .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL_REG), + .PF0_BIST_REGISTER (PF0_BIST_REGISTER_REG), + .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER_REG), + .PF0_CLASS_CODE (PF0_CLASS_CODE_REG), + .PF0_DEVICE_ID (PF0_DEVICE_ID_REG), + .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG), + .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG), + .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT_REG), + .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT_REG), + .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG), + .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG), + .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG), + .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG), + .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG), + .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR_REG), + .PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL_REG), + .PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG), + .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG), + .PF0_DPA_CAP_VER (PF0_DPA_CAP_VER_REG), + .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR_REG), + .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE_REG), + .PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE_REG), + .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN_REG), + .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG), + .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG), + .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG), + .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG), + .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT_REG), + .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR_REG), + .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER_REG), + .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR_REG), + .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR_REG), + .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR_REG), + .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET_REG), + .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE_REG), + .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP_REG), + .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR_REG), + .PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP_REG), + .PF0_PB_CAP_DATA_REG_D0 (PF0_PB_CAP_DATA_REG_D0_REG), + .PF0_PB_CAP_DATA_REG_D0_SUSTAINED (PF0_PB_CAP_DATA_REG_D0_SUSTAINED_REG), + .PF0_PB_CAP_DATA_REG_D1 (PF0_PB_CAP_DATA_REG_D1_REG), + .PF0_PB_CAP_DATA_REG_D3HOT (PF0_PB_CAP_DATA_REG_D3HOT_REG), + .PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR_REG), + .PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED_REG), + .PF0_PB_CAP_VER (PF0_PB_CAP_VER_REG), + .PF0_PM_CAP_ID (PF0_PM_CAP_ID_REG), + .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR_REG), + .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0_REG), + .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1_REG), + .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT_REG), + .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE_REG), + .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID_REG), + .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET_REG), + .PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE_REG), + .PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR_REG), + .PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0_REG), + .PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1_REG), + .PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2_REG), + .PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER_REG), + .PF0_RBAR_CONTROL_INDEX0 (PF0_RBAR_CONTROL_INDEX0_REG), + .PF0_RBAR_CONTROL_INDEX1 (PF0_RBAR_CONTROL_INDEX1_REG), + .PF0_RBAR_CONTROL_INDEX2 (PF0_RBAR_CONTROL_INDEX2_REG), + .PF0_RBAR_CONTROL_SIZE0 (PF0_RBAR_CONTROL_SIZE0_REG), + .PF0_RBAR_CONTROL_SIZE1 (PF0_RBAR_CONTROL_SIZE1_REG), + .PF0_RBAR_CONTROL_SIZE2 (PF0_RBAR_CONTROL_SIZE2_REG), + .PF0_RBAR_NUM (PF0_RBAR_NUM_REG), + .PF0_REVISION_ID (PF0_REVISION_ID_REG), + .PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG), + .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL_REG), + .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL_REG), + .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL_REG), + .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL_REG), + .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL_REG), + .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL_REG), + .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF_REG), + .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR_REG), + .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF_REG), + .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER_REG), + .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET_REG), + .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK_REG), + .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID_REG), + .PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID_REG), + .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE_REG), + .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE_REG), + .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR_REG), + .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL_REG), + .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC_REG), + .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER_REG), + .PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE_REG), + .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR_REG), + .PF0_VC_CAP_VER (PF0_VC_CAP_VER_REG), + .PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG), + .PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE_REG), + .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR_REG), + .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC_REG), + .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE_REG), + .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL_REG), + .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE_REG), + .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL_REG), + .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE_REG), + .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL_REG), + .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE_REG), + .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL_REG), + .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE_REG), + .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL_REG), + .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE_REG), + .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL_REG), + .PF1_BIST_REGISTER (PF1_BIST_REGISTER_REG), + .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER_REG), + .PF1_CLASS_CODE (PF1_CLASS_CODE_REG), + .PF1_DEVICE_ID (PF1_DEVICE_ID_REG), + .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR_REG), + .PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL_REG), + .PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG), + .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG), + .PF1_DPA_CAP_VER (PF1_DPA_CAP_VER_REG), + .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR_REG), + .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE_REG), + .PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE_REG), + .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN_REG), + .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR_REG), + .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR_REG), + .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR_REG), + .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET_REG), + .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE_REG), + .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP_REG), + .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR_REG), + .PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP_REG), + .PF1_PB_CAP_DATA_REG_D0 (PF1_PB_CAP_DATA_REG_D0_REG), + .PF1_PB_CAP_DATA_REG_D0_SUSTAINED (PF1_PB_CAP_DATA_REG_D0_SUSTAINED_REG), + .PF1_PB_CAP_DATA_REG_D1 (PF1_PB_CAP_DATA_REG_D1_REG), + .PF1_PB_CAP_DATA_REG_D3HOT (PF1_PB_CAP_DATA_REG_D3HOT_REG), + .PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR_REG), + .PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED_REG), + .PF1_PB_CAP_VER (PF1_PB_CAP_VER_REG), + .PF1_PM_CAP_ID (PF1_PM_CAP_ID_REG), + .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR_REG), + .PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID_REG), + .PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE_REG), + .PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR_REG), + .PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0_REG), + .PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1_REG), + .PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2_REG), + .PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER_REG), + .PF1_RBAR_CONTROL_INDEX0 (PF1_RBAR_CONTROL_INDEX0_REG), + .PF1_RBAR_CONTROL_INDEX1 (PF1_RBAR_CONTROL_INDEX1_REG), + .PF1_RBAR_CONTROL_INDEX2 (PF1_RBAR_CONTROL_INDEX2_REG), + .PF1_RBAR_CONTROL_SIZE0 (PF1_RBAR_CONTROL_SIZE0_REG), + .PF1_RBAR_CONTROL_SIZE1 (PF1_RBAR_CONTROL_SIZE1_REG), + .PF1_RBAR_CONTROL_SIZE2 (PF1_RBAR_CONTROL_SIZE2_REG), + .PF1_RBAR_NUM (PF1_RBAR_NUM_REG), + .PF1_REVISION_ID (PF1_REVISION_ID_REG), + .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL_REG), + .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL_REG), + .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL_REG), + .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL_REG), + .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL_REG), + .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL_REG), + .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF_REG), + .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR_REG), + .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF_REG), + .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER_REG), + .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET_REG), + .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK_REG), + .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID_REG), + .PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID_REG), + .PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE_REG), + .PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE_REG), + .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR_REG), + .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL_REG), + .PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC_REG), + .PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER_REG), + .PF2_AER_CAP_ECRC_CHECK_CAPABLE (PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG), + .PF2_AER_CAP_ECRC_GEN_CAPABLE (PF2_AER_CAP_ECRC_GEN_CAPABLE_REG), + .PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR_REG), + .PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC_REG), + .PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE_REG), + .PF2_BAR0_CONTROL (PF2_BAR0_CONTROL_REG), + .PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE_REG), + .PF2_BAR1_CONTROL (PF2_BAR1_CONTROL_REG), + .PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE_REG), + .PF2_BAR2_CONTROL (PF2_BAR2_CONTROL_REG), + .PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE_REG), + .PF2_BAR3_CONTROL (PF2_BAR3_CONTROL_REG), + .PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE_REG), + .PF2_BAR4_CONTROL (PF2_BAR4_CONTROL_REG), + .PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE_REG), + .PF2_BAR5_CONTROL (PF2_BAR5_CONTROL_REG), + .PF2_BIST_REGISTER (PF2_BIST_REGISTER_REG), + .PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER_REG), + .PF2_CLASS_CODE (PF2_CLASS_CODE_REG), + .PF2_DEVICE_ID (PF2_DEVICE_ID_REG), + .PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF2_DPA_CAP_NEXTPTR (PF2_DPA_CAP_NEXTPTR_REG), + .PF2_DPA_CAP_SUB_STATE_CONTROL (PF2_DPA_CAP_SUB_STATE_CONTROL_REG), + .PF2_DPA_CAP_SUB_STATE_CONTROL_EN (PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG), + .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG), + .PF2_DPA_CAP_VER (PF2_DPA_CAP_VER_REG), + .PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR_REG), + .PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE_REG), + .PF2_INTERRUPT_LINE (PF2_INTERRUPT_LINE_REG), + .PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN_REG), + .PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR_REG), + .PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR_REG), + .PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR_REG), + .PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET_REG), + .PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE_REG), + .PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP_REG), + .PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR_REG), + .PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP_REG), + .PF2_PB_CAP_DATA_REG_D0 (PF2_PB_CAP_DATA_REG_D0_REG), + .PF2_PB_CAP_DATA_REG_D0_SUSTAINED (PF2_PB_CAP_DATA_REG_D0_SUSTAINED_REG), + .PF2_PB_CAP_DATA_REG_D1 (PF2_PB_CAP_DATA_REG_D1_REG), + .PF2_PB_CAP_DATA_REG_D3HOT (PF2_PB_CAP_DATA_REG_D3HOT_REG), + .PF2_PB_CAP_NEXTPTR (PF2_PB_CAP_NEXTPTR_REG), + .PF2_PB_CAP_SYSTEM_ALLOCATED (PF2_PB_CAP_SYSTEM_ALLOCATED_REG), + .PF2_PB_CAP_VER (PF2_PB_CAP_VER_REG), + .PF2_PM_CAP_ID (PF2_PM_CAP_ID_REG), + .PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR_REG), + .PF2_PM_CAP_VER_ID (PF2_PM_CAP_VER_ID_REG), + .PF2_RBAR_CAP_ENABLE (PF2_RBAR_CAP_ENABLE_REG), + .PF2_RBAR_CAP_NEXTPTR (PF2_RBAR_CAP_NEXTPTR_REG), + .PF2_RBAR_CAP_SIZE0 (PF2_RBAR_CAP_SIZE0_REG), + .PF2_RBAR_CAP_SIZE1 (PF2_RBAR_CAP_SIZE1_REG), + .PF2_RBAR_CAP_SIZE2 (PF2_RBAR_CAP_SIZE2_REG), + .PF2_RBAR_CAP_VER (PF2_RBAR_CAP_VER_REG), + .PF2_RBAR_CONTROL_INDEX0 (PF2_RBAR_CONTROL_INDEX0_REG), + .PF2_RBAR_CONTROL_INDEX1 (PF2_RBAR_CONTROL_INDEX1_REG), + .PF2_RBAR_CONTROL_INDEX2 (PF2_RBAR_CONTROL_INDEX2_REG), + .PF2_RBAR_CONTROL_SIZE0 (PF2_RBAR_CONTROL_SIZE0_REG), + .PF2_RBAR_CONTROL_SIZE1 (PF2_RBAR_CONTROL_SIZE1_REG), + .PF2_RBAR_CONTROL_SIZE2 (PF2_RBAR_CONTROL_SIZE2_REG), + .PF2_RBAR_NUM (PF2_RBAR_NUM_REG), + .PF2_REVISION_ID (PF2_REVISION_ID_REG), + .PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL_REG), + .PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL_REG), + .PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL_REG), + .PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL_REG), + .PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL_REG), + .PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL_REG), + .PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF_REG), + .PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR_REG), + .PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF_REG), + .PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER_REG), + .PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET_REG), + .PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK_REG), + .PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID_REG), + .PF2_SUBSYSTEM_ID (PF2_SUBSYSTEM_ID_REG), + .PF2_TPHR_CAP_DEV_SPECIFIC_MODE (PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF2_TPHR_CAP_ENABLE (PF2_TPHR_CAP_ENABLE_REG), + .PF2_TPHR_CAP_INT_VEC_MODE (PF2_TPHR_CAP_INT_VEC_MODE_REG), + .PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR_REG), + .PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL_REG), + .PF2_TPHR_CAP_ST_TABLE_LOC (PF2_TPHR_CAP_ST_TABLE_LOC_REG), + .PF2_TPHR_CAP_ST_TABLE_SIZE (PF2_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF2_TPHR_CAP_VER (PF2_TPHR_CAP_VER_REG), + .PF3_AER_CAP_ECRC_CHECK_CAPABLE (PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG), + .PF3_AER_CAP_ECRC_GEN_CAPABLE (PF3_AER_CAP_ECRC_GEN_CAPABLE_REG), + .PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR_REG), + .PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC_REG), + .PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE_REG), + .PF3_BAR0_CONTROL (PF3_BAR0_CONTROL_REG), + .PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE_REG), + .PF3_BAR1_CONTROL (PF3_BAR1_CONTROL_REG), + .PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE_REG), + .PF3_BAR2_CONTROL (PF3_BAR2_CONTROL_REG), + .PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE_REG), + .PF3_BAR3_CONTROL (PF3_BAR3_CONTROL_REG), + .PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE_REG), + .PF3_BAR4_CONTROL (PF3_BAR4_CONTROL_REG), + .PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE_REG), + .PF3_BAR5_CONTROL (PF3_BAR5_CONTROL_REG), + .PF3_BIST_REGISTER (PF3_BIST_REGISTER_REG), + .PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER_REG), + .PF3_CLASS_CODE (PF3_CLASS_CODE_REG), + .PF3_DEVICE_ID (PF3_DEVICE_ID_REG), + .PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG), + .PF3_DPA_CAP_NEXTPTR (PF3_DPA_CAP_NEXTPTR_REG), + .PF3_DPA_CAP_SUB_STATE_CONTROL (PF3_DPA_CAP_SUB_STATE_CONTROL_REG), + .PF3_DPA_CAP_SUB_STATE_CONTROL_EN (PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG), + .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG), + .PF3_DPA_CAP_VER (PF3_DPA_CAP_VER_REG), + .PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR_REG), + .PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE_REG), + .PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE_REG), + .PF3_INTERRUPT_LINE (PF3_INTERRUPT_LINE_REG), + .PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN_REG), + .PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR_REG), + .PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR_REG), + .PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR_REG), + .PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET_REG), + .PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE_REG), + .PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP_REG), + .PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR_REG), + .PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP_REG), + .PF3_PB_CAP_DATA_REG_D0 (PF3_PB_CAP_DATA_REG_D0_REG), + .PF3_PB_CAP_DATA_REG_D0_SUSTAINED (PF3_PB_CAP_DATA_REG_D0_SUSTAINED_REG), + .PF3_PB_CAP_DATA_REG_D1 (PF3_PB_CAP_DATA_REG_D1_REG), + .PF3_PB_CAP_DATA_REG_D3HOT (PF3_PB_CAP_DATA_REG_D3HOT_REG), + .PF3_PB_CAP_NEXTPTR (PF3_PB_CAP_NEXTPTR_REG), + .PF3_PB_CAP_SYSTEM_ALLOCATED (PF3_PB_CAP_SYSTEM_ALLOCATED_REG), + .PF3_PB_CAP_VER (PF3_PB_CAP_VER_REG), + .PF3_PM_CAP_ID (PF3_PM_CAP_ID_REG), + .PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR_REG), + .PF3_PM_CAP_VER_ID (PF3_PM_CAP_VER_ID_REG), + .PF3_RBAR_CAP_ENABLE (PF3_RBAR_CAP_ENABLE_REG), + .PF3_RBAR_CAP_NEXTPTR (PF3_RBAR_CAP_NEXTPTR_REG), + .PF3_RBAR_CAP_SIZE0 (PF3_RBAR_CAP_SIZE0_REG), + .PF3_RBAR_CAP_SIZE1 (PF3_RBAR_CAP_SIZE1_REG), + .PF3_RBAR_CAP_SIZE2 (PF3_RBAR_CAP_SIZE2_REG), + .PF3_RBAR_CAP_VER (PF3_RBAR_CAP_VER_REG), + .PF3_RBAR_CONTROL_INDEX0 (PF3_RBAR_CONTROL_INDEX0_REG), + .PF3_RBAR_CONTROL_INDEX1 (PF3_RBAR_CONTROL_INDEX1_REG), + .PF3_RBAR_CONTROL_INDEX2 (PF3_RBAR_CONTROL_INDEX2_REG), + .PF3_RBAR_CONTROL_SIZE0 (PF3_RBAR_CONTROL_SIZE0_REG), + .PF3_RBAR_CONTROL_SIZE1 (PF3_RBAR_CONTROL_SIZE1_REG), + .PF3_RBAR_CONTROL_SIZE2 (PF3_RBAR_CONTROL_SIZE2_REG), + .PF3_RBAR_NUM (PF3_RBAR_NUM_REG), + .PF3_REVISION_ID (PF3_REVISION_ID_REG), + .PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL_REG), + .PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL_REG), + .PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL_REG), + .PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL_REG), + .PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL_REG), + .PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE_REG), + .PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL_REG), + .PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF_REG), + .PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR_REG), + .PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF_REG), + .PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER_REG), + .PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET_REG), + .PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK_REG), + .PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG), + .PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID_REG), + .PF3_SUBSYSTEM_ID (PF3_SUBSYSTEM_ID_REG), + .PF3_TPHR_CAP_DEV_SPECIFIC_MODE (PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .PF3_TPHR_CAP_ENABLE (PF3_TPHR_CAP_ENABLE_REG), + .PF3_TPHR_CAP_INT_VEC_MODE (PF3_TPHR_CAP_INT_VEC_MODE_REG), + .PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR_REG), + .PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL_REG), + .PF3_TPHR_CAP_ST_TABLE_LOC (PF3_TPHR_CAP_ST_TABLE_LOC_REG), + .PF3_TPHR_CAP_ST_TABLE_SIZE (PF3_TPHR_CAP_ST_TABLE_SIZE_REG), + .PF3_TPHR_CAP_VER (PF3_TPHR_CAP_VER_REG), + .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG), + .PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG), + .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0_REG), + .PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE_REG), + .PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP (PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG), + .PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG), + .PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING_REG), + .PL_DISABLE_SYNC_HEADER_FRAMING_ERROR (PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG), + .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE_REG), + .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG), + .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG), + .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT_REG), + .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG), + .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23_REG), + .PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT (PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT_REG), + .PL_EQ_DEFAULT_GEN3_TX_PRESET (PL_EQ_DEFAULT_GEN3_TX_PRESET_REG), + .PL_EQ_PHASE01_RX_ADAPT (PL_EQ_PHASE01_RX_ADAPT_REG), + .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE_REG), + .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL_REG), + .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL_REG), + .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL_REG), + .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL_REG), + .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL_REG), + .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL_REG), + .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL_REG), + .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL_REG), + .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED_REG), + .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH_REG), + .PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1_REG), + .PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2_REG), + .PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3_REG), + .PL_N_FTS_GEN1 (PL_N_FTS_GEN1_REG), + .PL_N_FTS_GEN2 (PL_N_FTS_GEN2_REG), + .PL_N_FTS_GEN3 (PL_N_FTS_GEN3_REG), + .PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS_REG), + .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING_REG), + .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING_REG), + .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT_REG), + .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY_REG), + .PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY_REG), + .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE_REG), + .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY_REG), + .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY_REG), + .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY_REG), + .SPARE_BIT0 (SPARE_BIT0_REG), + .SPARE_BIT1 (SPARE_BIT1_REG), + .SPARE_BIT2 (SPARE_BIT2_REG), + .SPARE_BIT3 (SPARE_BIT3_REG), + .SPARE_BIT4 (SPARE_BIT4_REG), + .SPARE_BIT5 (SPARE_BIT5_REG), + .SPARE_BIT6 (SPARE_BIT6_REG), + .SPARE_BIT7 (SPARE_BIT7_REG), + .SPARE_BIT8 (SPARE_BIT8_REG), + .SPARE_BYTE0 (SPARE_BYTE0_REG), + .SPARE_BYTE1 (SPARE_BYTE1_REG), + .SPARE_BYTE2 (SPARE_BYTE2_REG), + .SPARE_BYTE3 (SPARE_BYTE3_REG), + .SPARE_WORD0 (SPARE_WORD0_REG), + .SPARE_WORD1 (SPARE_WORD1_REG), + .SPARE_WORD2 (SPARE_WORD2_REG), + .SPARE_WORD3 (SPARE_WORD3_REG), + .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE_REG), + .TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG), + .TL_COMPLETION_RAM_SIZE_16K (TL_COMPLETION_RAM_SIZE_16K_REG), + .TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0_REG), + .TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1_REG), + .TL_CREDITS_CD (TL_CREDITS_CD_REG), + .TL_CREDITS_CH (TL_CREDITS_CH_REG), + .TL_CREDITS_NPD (TL_CREDITS_NPD_REG), + .TL_CREDITS_NPH (TL_CREDITS_NPH_REG), + .TL_CREDITS_PD (TL_CREDITS_PD_REG), + .TL_CREDITS_PH (TL_CREDITS_PH_REG), + .TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG), + .TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG), + .TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG), + .TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE_REG), + .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG_REG), + .TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY_REG), + .TWO_LAYER_MODE_DLCMSM_ENABLE (TWO_LAYER_MODE_DLCMSM_ENABLE_REG), + .TWO_LAYER_MODE_ENABLE (TWO_LAYER_MODE_ENABLE_REG), + .TWO_LAYER_MODE_WIDTH_256 (TWO_LAYER_MODE_WIDTH_256_REG), + .VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR_REG), + .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER_REG), + .VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR_REG), + .VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET_REG), + .VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR_REG), + .VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET_REG), + .VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE_REG), + .VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP_REG), + .VF0_PM_CAP_ID (VF0_PM_CAP_ID_REG), + .VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR_REG), + .VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID_REG), + .VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE_REG), + .VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE_REG), + .VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR_REG), + .VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL_REG), + .VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC_REG), + .VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER_REG), + .VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR_REG), + .VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR_REG), + .VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET_REG), + .VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR_REG), + .VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET_REG), + .VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE_REG), + .VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP_REG), + .VF1_PM_CAP_ID (VF1_PM_CAP_ID_REG), + .VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR_REG), + .VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID_REG), + .VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE_REG), + .VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE_REG), + .VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR_REG), + .VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL_REG), + .VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC_REG), + .VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER_REG), + .VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR_REG), + .VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR_REG), + .VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET_REG), + .VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR_REG), + .VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET_REG), + .VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE_REG), + .VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP_REG), + .VF2_PM_CAP_ID (VF2_PM_CAP_ID_REG), + .VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR_REG), + .VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID_REG), + .VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE_REG), + .VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE_REG), + .VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR_REG), + .VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL_REG), + .VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC_REG), + .VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER_REG), + .VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR_REG), + .VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR_REG), + .VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET_REG), + .VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR_REG), + .VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET_REG), + .VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE_REG), + .VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP_REG), + .VF3_PM_CAP_ID (VF3_PM_CAP_ID_REG), + .VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR_REG), + .VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID_REG), + .VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE_REG), + .VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE_REG), + .VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR_REG), + .VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL_REG), + .VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC_REG), + .VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER_REG), + .VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR_REG), + .VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR_REG), + .VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET_REG), + .VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR_REG), + .VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET_REG), + .VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE_REG), + .VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP_REG), + .VF4_PM_CAP_ID (VF4_PM_CAP_ID_REG), + .VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR_REG), + .VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID_REG), + .VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE_REG), + .VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE_REG), + .VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR_REG), + .VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL_REG), + .VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC_REG), + .VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER_REG), + .VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR_REG), + .VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR_REG), + .VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET_REG), + .VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR_REG), + .VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET_REG), + .VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE_REG), + .VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP_REG), + .VF5_PM_CAP_ID (VF5_PM_CAP_ID_REG), + .VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR_REG), + .VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID_REG), + .VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE_REG), + .VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE_REG), + .VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR_REG), + .VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL_REG), + .VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC_REG), + .VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER_REG), + .VF6_ARI_CAP_NEXTPTR (VF6_ARI_CAP_NEXTPTR_REG), + .VF6_MSIX_CAP_PBA_BIR (VF6_MSIX_CAP_PBA_BIR_REG), + .VF6_MSIX_CAP_PBA_OFFSET (VF6_MSIX_CAP_PBA_OFFSET_REG), + .VF6_MSIX_CAP_TABLE_BIR (VF6_MSIX_CAP_TABLE_BIR_REG), + .VF6_MSIX_CAP_TABLE_OFFSET (VF6_MSIX_CAP_TABLE_OFFSET_REG), + .VF6_MSIX_CAP_TABLE_SIZE (VF6_MSIX_CAP_TABLE_SIZE_REG), + .VF6_MSI_CAP_MULTIMSGCAP (VF6_MSI_CAP_MULTIMSGCAP_REG), + .VF6_PM_CAP_ID (VF6_PM_CAP_ID_REG), + .VF6_PM_CAP_NEXTPTR (VF6_PM_CAP_NEXTPTR_REG), + .VF6_PM_CAP_VER_ID (VF6_PM_CAP_VER_ID_REG), + .VF6_TPHR_CAP_DEV_SPECIFIC_MODE (VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF6_TPHR_CAP_ENABLE (VF6_TPHR_CAP_ENABLE_REG), + .VF6_TPHR_CAP_INT_VEC_MODE (VF6_TPHR_CAP_INT_VEC_MODE_REG), + .VF6_TPHR_CAP_NEXTPTR (VF6_TPHR_CAP_NEXTPTR_REG), + .VF6_TPHR_CAP_ST_MODE_SEL (VF6_TPHR_CAP_ST_MODE_SEL_REG), + .VF6_TPHR_CAP_ST_TABLE_LOC (VF6_TPHR_CAP_ST_TABLE_LOC_REG), + .VF6_TPHR_CAP_ST_TABLE_SIZE (VF6_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF6_TPHR_CAP_VER (VF6_TPHR_CAP_VER_REG), + .VF7_ARI_CAP_NEXTPTR (VF7_ARI_CAP_NEXTPTR_REG), + .VF7_MSIX_CAP_PBA_BIR (VF7_MSIX_CAP_PBA_BIR_REG), + .VF7_MSIX_CAP_PBA_OFFSET (VF7_MSIX_CAP_PBA_OFFSET_REG), + .VF7_MSIX_CAP_TABLE_BIR (VF7_MSIX_CAP_TABLE_BIR_REG), + .VF7_MSIX_CAP_TABLE_OFFSET (VF7_MSIX_CAP_TABLE_OFFSET_REG), + .VF7_MSIX_CAP_TABLE_SIZE (VF7_MSIX_CAP_TABLE_SIZE_REG), + .VF7_MSI_CAP_MULTIMSGCAP (VF7_MSI_CAP_MULTIMSGCAP_REG), + .VF7_PM_CAP_ID (VF7_PM_CAP_ID_REG), + .VF7_PM_CAP_NEXTPTR (VF7_PM_CAP_NEXTPTR_REG), + .VF7_PM_CAP_VER_ID (VF7_PM_CAP_VER_ID_REG), + .VF7_TPHR_CAP_DEV_SPECIFIC_MODE (VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG), + .VF7_TPHR_CAP_ENABLE (VF7_TPHR_CAP_ENABLE_REG), + .VF7_TPHR_CAP_INT_VEC_MODE (VF7_TPHR_CAP_INT_VEC_MODE_REG), + .VF7_TPHR_CAP_NEXTPTR (VF7_TPHR_CAP_NEXTPTR_REG), + .VF7_TPHR_CAP_ST_MODE_SEL (VF7_TPHR_CAP_ST_MODE_SEL_REG), + .VF7_TPHR_CAP_ST_TABLE_LOC (VF7_TPHR_CAP_ST_TABLE_LOC_REG), + .VF7_TPHR_CAP_ST_TABLE_SIZE (VF7_TPHR_CAP_ST_TABLE_SIZE_REG), + .VF7_TPHR_CAP_VER (VF7_TPHR_CAP_VER_REG), + .CFGCURRENTSPEED (CFGCURRENTSPEED_out), + .CFGDPASUBSTATECHANGE (CFGDPASUBSTATECHANGE_out), + .CFGERRCOROUT (CFGERRCOROUT_out), + .CFGERRFATALOUT (CFGERRFATALOUT_out), + .CFGERRNONFATALOUT (CFGERRNONFATALOUT_out), + .CFGEXTFUNCTIONNUMBER (CFGEXTFUNCTIONNUMBER_out), + .CFGEXTREADRECEIVED (CFGEXTREADRECEIVED_out), + .CFGEXTREGISTERNUMBER (CFGEXTREGISTERNUMBER_out), + .CFGEXTWRITEBYTEENABLE (CFGEXTWRITEBYTEENABLE_out), + .CFGEXTWRITEDATA (CFGEXTWRITEDATA_out), + .CFGEXTWRITERECEIVED (CFGEXTWRITERECEIVED_out), + .CFGFCCPLD (CFGFCCPLD_out), + .CFGFCCPLH (CFGFCCPLH_out), + .CFGFCNPD (CFGFCNPD_out), + .CFGFCNPH (CFGFCNPH_out), + .CFGFCPD (CFGFCPD_out), + .CFGFCPH (CFGFCPH_out), + .CFGFLRINPROCESS (CFGFLRINPROCESS_out), + .CFGFUNCTIONPOWERSTATE (CFGFUNCTIONPOWERSTATE_out), + .CFGFUNCTIONSTATUS (CFGFUNCTIONSTATUS_out), + .CFGHOTRESETOUT (CFGHOTRESETOUT_out), + .CFGINTERRUPTMSIDATA (CFGINTERRUPTMSIDATA_out), + .CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE_out), + .CFGINTERRUPTMSIFAIL (CFGINTERRUPTMSIFAIL_out), + .CFGINTERRUPTMSIMASKUPDATE (CFGINTERRUPTMSIMASKUPDATE_out), + .CFGINTERRUPTMSIMMENABLE (CFGINTERRUPTMSIMMENABLE_out), + .CFGINTERRUPTMSISENT (CFGINTERRUPTMSISENT_out), + .CFGINTERRUPTMSIVFENABLE (CFGINTERRUPTMSIVFENABLE_out), + .CFGINTERRUPTMSIXENABLE (CFGINTERRUPTMSIXENABLE_out), + .CFGINTERRUPTMSIXFAIL (CFGINTERRUPTMSIXFAIL_out), + .CFGINTERRUPTMSIXMASK (CFGINTERRUPTMSIXMASK_out), + .CFGINTERRUPTMSIXSENT (CFGINTERRUPTMSIXSENT_out), + .CFGINTERRUPTMSIXVFENABLE (CFGINTERRUPTMSIXVFENABLE_out), + .CFGINTERRUPTMSIXVFMASK (CFGINTERRUPTMSIXVFMASK_out), + .CFGINTERRUPTSENT (CFGINTERRUPTSENT_out), + .CFGLINKPOWERSTATE (CFGLINKPOWERSTATE_out), + .CFGLOCALERROR (CFGLOCALERROR_out), + .CFGLTRENABLE (CFGLTRENABLE_out), + .CFGLTSSMSTATE (CFGLTSSMSTATE_out), + .CFGMAXPAYLOAD (CFGMAXPAYLOAD_out), + .CFGMAXREADREQ (CFGMAXREADREQ_out), + .CFGMGMTREADDATA (CFGMGMTREADDATA_out), + .CFGMGMTREADWRITEDONE (CFGMGMTREADWRITEDONE_out), + .CFGMSGRECEIVED (CFGMSGRECEIVED_out), + .CFGMSGRECEIVEDDATA (CFGMSGRECEIVEDDATA_out), + .CFGMSGRECEIVEDTYPE (CFGMSGRECEIVEDTYPE_out), + .CFGMSGTRANSMITDONE (CFGMSGTRANSMITDONE_out), + .CFGNEGOTIATEDWIDTH (CFGNEGOTIATEDWIDTH_out), + .CFGOBFFENABLE (CFGOBFFENABLE_out), + .CFGPERFUNCSTATUSDATA (CFGPERFUNCSTATUSDATA_out), + .CFGPERFUNCTIONUPDATEDONE (CFGPERFUNCTIONUPDATEDONE_out), + .CFGPHYLINKDOWN (CFGPHYLINKDOWN_out), + .CFGPHYLINKSTATUS (CFGPHYLINKSTATUS_out), + .CFGPLSTATUSCHANGE (CFGPLSTATUSCHANGE_out), + .CFGPOWERSTATECHANGEINTERRUPT (CFGPOWERSTATECHANGEINTERRUPT_out), + .CFGRCBSTATUS (CFGRCBSTATUS_out), + .CFGTPHFUNCTIONNUM (CFGTPHFUNCTIONNUM_out), + .CFGTPHREQUESTERENABLE (CFGTPHREQUESTERENABLE_out), + .CFGTPHSTMODE (CFGTPHSTMODE_out), + .CFGTPHSTTADDRESS (CFGTPHSTTADDRESS_out), + .CFGTPHSTTREADENABLE (CFGTPHSTTREADENABLE_out), + .CFGTPHSTTWRITEBYTEVALID (CFGTPHSTTWRITEBYTEVALID_out), + .CFGTPHSTTWRITEDATA (CFGTPHSTTWRITEDATA_out), + .CFGTPHSTTWRITEENABLE (CFGTPHSTTWRITEENABLE_out), + .CFGVFFLRINPROCESS (CFGVFFLRINPROCESS_out), + .CFGVFPOWERSTATE (CFGVFPOWERSTATE_out), + .CFGVFSTATUS (CFGVFSTATUS_out), + .CFGVFTPHREQUESTERENABLE (CFGVFTPHREQUESTERENABLE_out), + .CFGVFTPHSTMODE (CFGVFTPHSTMODE_out), + .CONFMCAPDESIGNSWITCH (CONFMCAPDESIGNSWITCH_out), + .CONFMCAPEOS (CONFMCAPEOS_out), + .CONFMCAPINUSEBYPCIE (CONFMCAPINUSEBYPCIE_out), + .CONFREQREADY (CONFREQREADY_out), + .CONFRESPRDATA (CONFRESPRDATA_out), + .CONFRESPVALID (CONFRESPVALID_out), + .DBGDATAOUT (DBGDATAOUT_out), + .DBGMCAPCSB (DBGMCAPCSB_out), + .DBGMCAPDATA (DBGMCAPDATA_out), + .DBGMCAPEOS (DBGMCAPEOS_out), + .DBGMCAPERROR (DBGMCAPERROR_out), + .DBGMCAPMODE (DBGMCAPMODE_out), + .DBGMCAPRDATAVALID (DBGMCAPRDATAVALID_out), + .DBGMCAPRDWRB (DBGMCAPRDWRB_out), + .DBGMCAPRESET (DBGMCAPRESET_out), + .DBGPLDATABLOCKRECEIVEDAFTEREDS (DBGPLDATABLOCKRECEIVEDAFTEREDS_out), + .DBGPLGEN3FRAMINGERRORDETECTED (DBGPLGEN3FRAMINGERRORDETECTED_out), + .DBGPLGEN3SYNCHEADERERRORDETECTED (DBGPLGEN3SYNCHEADERERRORDETECTED_out), + .DBGPLINFERREDRXELECTRICALIDLE (DBGPLINFERREDRXELECTRICALIDLE_out), + .DRPDO (DRPDO_out), + .DRPRDY (DRPRDY_out), + .LL2LMMASTERTLPSENT0 (LL2LMMASTERTLPSENT0_out), + .LL2LMMASTERTLPSENT1 (LL2LMMASTERTLPSENT1_out), + .LL2LMMASTERTLPSENTTLPID0 (LL2LMMASTERTLPSENTTLPID0_out), + .LL2LMMASTERTLPSENTTLPID1 (LL2LMMASTERTLPSENTTLPID1_out), + .LL2LMMAXISRXTDATA (LL2LMMAXISRXTDATA_out), + .LL2LMMAXISRXTUSER (LL2LMMAXISRXTUSER_out), + .LL2LMMAXISRXTVALID (LL2LMMAXISRXTVALID_out), + .LL2LMSAXISTXTREADY (LL2LMSAXISTXTREADY_out), + .MAXISCQTDATA (MAXISCQTDATA_out), + .MAXISCQTKEEP (MAXISCQTKEEP_out), + .MAXISCQTLAST (MAXISCQTLAST_out), + .MAXISCQTUSER (MAXISCQTUSER_out), + .MAXISCQTVALID (MAXISCQTVALID_out), + .MAXISRCTDATA (MAXISRCTDATA_out), + .MAXISRCTKEEP (MAXISRCTKEEP_out), + .MAXISRCTLAST (MAXISRCTLAST_out), + .MAXISRCTUSER (MAXISRCTUSER_out), + .MAXISRCTVALID (MAXISRCTVALID_out), + .MICOMPLETIONRAMREADADDRESSAL (MICOMPLETIONRAMREADADDRESSAL_out), + .MICOMPLETIONRAMREADADDRESSAU (MICOMPLETIONRAMREADADDRESSAU_out), + .MICOMPLETIONRAMREADADDRESSBL (MICOMPLETIONRAMREADADDRESSBL_out), + .MICOMPLETIONRAMREADADDRESSBU (MICOMPLETIONRAMREADADDRESSBU_out), + .MICOMPLETIONRAMREADENABLEL (MICOMPLETIONRAMREADENABLEL_out), + .MICOMPLETIONRAMREADENABLEU (MICOMPLETIONRAMREADENABLEU_out), + .MICOMPLETIONRAMWRITEADDRESSAL (MICOMPLETIONRAMWRITEADDRESSAL_out), + .MICOMPLETIONRAMWRITEADDRESSAU (MICOMPLETIONRAMWRITEADDRESSAU_out), + .MICOMPLETIONRAMWRITEADDRESSBL (MICOMPLETIONRAMWRITEADDRESSBL_out), + .MICOMPLETIONRAMWRITEADDRESSBU (MICOMPLETIONRAMWRITEADDRESSBU_out), + .MICOMPLETIONRAMWRITEDATAL (MICOMPLETIONRAMWRITEDATAL_out), + .MICOMPLETIONRAMWRITEDATAU (MICOMPLETIONRAMWRITEDATAU_out), + .MICOMPLETIONRAMWRITEENABLEL (MICOMPLETIONRAMWRITEENABLEL_out), + .MICOMPLETIONRAMWRITEENABLEU (MICOMPLETIONRAMWRITEENABLEU_out), + .MIREPLAYRAMADDRESS (MIREPLAYRAMADDRESS_out), + .MIREPLAYRAMREADENABLE (MIREPLAYRAMREADENABLE_out), + .MIREPLAYRAMWRITEDATA (MIREPLAYRAMWRITEDATA_out), + .MIREPLAYRAMWRITEENABLE (MIREPLAYRAMWRITEENABLE_out), + .MIREQUESTRAMREADADDRESSA (MIREQUESTRAMREADADDRESSA_out), + .MIREQUESTRAMREADADDRESSB (MIREQUESTRAMREADADDRESSB_out), + .MIREQUESTRAMREADENABLE (MIREQUESTRAMREADENABLE_out), + .MIREQUESTRAMWRITEADDRESSA (MIREQUESTRAMWRITEADDRESSA_out), + .MIREQUESTRAMWRITEADDRESSB (MIREQUESTRAMWRITEADDRESSB_out), + .MIREQUESTRAMWRITEDATA (MIREQUESTRAMWRITEDATA_out), + .MIREQUESTRAMWRITEENABLE (MIREQUESTRAMWRITEENABLE_out), + .PCIECQNPREQCOUNT (PCIECQNPREQCOUNT_out), + .PCIEPERST0B (PCIEPERST0B_out), + .PCIEPERST1B (PCIEPERST1B_out), + .PCIERQSEQNUM (PCIERQSEQNUM_out), + .PCIERQSEQNUMVLD (PCIERQSEQNUMVLD_out), + .PCIERQTAG (PCIERQTAG_out), + .PCIERQTAGAV (PCIERQTAGAV_out), + .PCIERQTAGVLD (PCIERQTAGVLD_out), + .PCIETFCNPDAV (PCIETFCNPDAV_out), + .PCIETFCNPHAV (PCIETFCNPHAV_out), + .PIPERX0EQCONTROL (PIPERX0EQCONTROL_out), + .PIPERX0EQLPLFFS (PIPERX0EQLPLFFS_out), + .PIPERX0EQLPTXPRESET (PIPERX0EQLPTXPRESET_out), + .PIPERX0EQPRESET (PIPERX0EQPRESET_out), + .PIPERX0POLARITY (PIPERX0POLARITY_out), + .PIPERX1EQCONTROL (PIPERX1EQCONTROL_out), + .PIPERX1EQLPLFFS (PIPERX1EQLPLFFS_out), + .PIPERX1EQLPTXPRESET (PIPERX1EQLPTXPRESET_out), + .PIPERX1EQPRESET (PIPERX1EQPRESET_out), + .PIPERX1POLARITY (PIPERX1POLARITY_out), + .PIPERX2EQCONTROL (PIPERX2EQCONTROL_out), + .PIPERX2EQLPLFFS (PIPERX2EQLPLFFS_out), + .PIPERX2EQLPTXPRESET (PIPERX2EQLPTXPRESET_out), + .PIPERX2EQPRESET (PIPERX2EQPRESET_out), + .PIPERX2POLARITY (PIPERX2POLARITY_out), + .PIPERX3EQCONTROL (PIPERX3EQCONTROL_out), + .PIPERX3EQLPLFFS (PIPERX3EQLPLFFS_out), + .PIPERX3EQLPTXPRESET (PIPERX3EQLPTXPRESET_out), + .PIPERX3EQPRESET (PIPERX3EQPRESET_out), + .PIPERX3POLARITY (PIPERX3POLARITY_out), + .PIPERX4EQCONTROL (PIPERX4EQCONTROL_out), + .PIPERX4EQLPLFFS (PIPERX4EQLPLFFS_out), + .PIPERX4EQLPTXPRESET (PIPERX4EQLPTXPRESET_out), + .PIPERX4EQPRESET (PIPERX4EQPRESET_out), + .PIPERX4POLARITY (PIPERX4POLARITY_out), + .PIPERX5EQCONTROL (PIPERX5EQCONTROL_out), + .PIPERX5EQLPLFFS (PIPERX5EQLPLFFS_out), + .PIPERX5EQLPTXPRESET (PIPERX5EQLPTXPRESET_out), + .PIPERX5EQPRESET (PIPERX5EQPRESET_out), + .PIPERX5POLARITY (PIPERX5POLARITY_out), + .PIPERX6EQCONTROL (PIPERX6EQCONTROL_out), + .PIPERX6EQLPLFFS (PIPERX6EQLPLFFS_out), + .PIPERX6EQLPTXPRESET (PIPERX6EQLPTXPRESET_out), + .PIPERX6EQPRESET (PIPERX6EQPRESET_out), + .PIPERX6POLARITY (PIPERX6POLARITY_out), + .PIPERX7EQCONTROL (PIPERX7EQCONTROL_out), + .PIPERX7EQLPLFFS (PIPERX7EQLPLFFS_out), + .PIPERX7EQLPTXPRESET (PIPERX7EQLPTXPRESET_out), + .PIPERX7EQPRESET (PIPERX7EQPRESET_out), + .PIPERX7POLARITY (PIPERX7POLARITY_out), + .PIPETX0CHARISK (PIPETX0CHARISK_out), + .PIPETX0COMPLIANCE (PIPETX0COMPLIANCE_out), + .PIPETX0DATA (PIPETX0DATA_out), + .PIPETX0DATAVALID (PIPETX0DATAVALID_out), + .PIPETX0DEEMPH (PIPETX0DEEMPH_out), + .PIPETX0ELECIDLE (PIPETX0ELECIDLE_out), + .PIPETX0EQCONTROL (PIPETX0EQCONTROL_out), + .PIPETX0EQDEEMPH (PIPETX0EQDEEMPH_out), + .PIPETX0EQPRESET (PIPETX0EQPRESET_out), + .PIPETX0MARGIN (PIPETX0MARGIN_out), + .PIPETX0POWERDOWN (PIPETX0POWERDOWN_out), + .PIPETX0RATE (PIPETX0RATE_out), + .PIPETX0RCVRDET (PIPETX0RCVRDET_out), + .PIPETX0RESET (PIPETX0RESET_out), + .PIPETX0STARTBLOCK (PIPETX0STARTBLOCK_out), + .PIPETX0SWING (PIPETX0SWING_out), + .PIPETX0SYNCHEADER (PIPETX0SYNCHEADER_out), + .PIPETX1CHARISK (PIPETX1CHARISK_out), + .PIPETX1COMPLIANCE (PIPETX1COMPLIANCE_out), + .PIPETX1DATA (PIPETX1DATA_out), + .PIPETX1DATAVALID (PIPETX1DATAVALID_out), + .PIPETX1DEEMPH (PIPETX1DEEMPH_out), + .PIPETX1ELECIDLE (PIPETX1ELECIDLE_out), + .PIPETX1EQCONTROL (PIPETX1EQCONTROL_out), + .PIPETX1EQDEEMPH (PIPETX1EQDEEMPH_out), + .PIPETX1EQPRESET (PIPETX1EQPRESET_out), + .PIPETX1MARGIN (PIPETX1MARGIN_out), + .PIPETX1POWERDOWN (PIPETX1POWERDOWN_out), + .PIPETX1RATE (PIPETX1RATE_out), + .PIPETX1RCVRDET (PIPETX1RCVRDET_out), + .PIPETX1RESET (PIPETX1RESET_out), + .PIPETX1STARTBLOCK (PIPETX1STARTBLOCK_out), + .PIPETX1SWING (PIPETX1SWING_out), + .PIPETX1SYNCHEADER (PIPETX1SYNCHEADER_out), + .PIPETX2CHARISK (PIPETX2CHARISK_out), + .PIPETX2COMPLIANCE (PIPETX2COMPLIANCE_out), + .PIPETX2DATA (PIPETX2DATA_out), + .PIPETX2DATAVALID (PIPETX2DATAVALID_out), + .PIPETX2DEEMPH (PIPETX2DEEMPH_out), + .PIPETX2ELECIDLE (PIPETX2ELECIDLE_out), + .PIPETX2EQCONTROL (PIPETX2EQCONTROL_out), + .PIPETX2EQDEEMPH (PIPETX2EQDEEMPH_out), + .PIPETX2EQPRESET (PIPETX2EQPRESET_out), + .PIPETX2MARGIN (PIPETX2MARGIN_out), + .PIPETX2POWERDOWN (PIPETX2POWERDOWN_out), + .PIPETX2RATE (PIPETX2RATE_out), + .PIPETX2RCVRDET (PIPETX2RCVRDET_out), + .PIPETX2RESET (PIPETX2RESET_out), + .PIPETX2STARTBLOCK (PIPETX2STARTBLOCK_out), + .PIPETX2SWING (PIPETX2SWING_out), + .PIPETX2SYNCHEADER (PIPETX2SYNCHEADER_out), + .PIPETX3CHARISK (PIPETX3CHARISK_out), + .PIPETX3COMPLIANCE (PIPETX3COMPLIANCE_out), + .PIPETX3DATA (PIPETX3DATA_out), + .PIPETX3DATAVALID (PIPETX3DATAVALID_out), + .PIPETX3DEEMPH (PIPETX3DEEMPH_out), + .PIPETX3ELECIDLE (PIPETX3ELECIDLE_out), + .PIPETX3EQCONTROL (PIPETX3EQCONTROL_out), + .PIPETX3EQDEEMPH (PIPETX3EQDEEMPH_out), + .PIPETX3EQPRESET (PIPETX3EQPRESET_out), + .PIPETX3MARGIN (PIPETX3MARGIN_out), + .PIPETX3POWERDOWN (PIPETX3POWERDOWN_out), + .PIPETX3RATE (PIPETX3RATE_out), + .PIPETX3RCVRDET (PIPETX3RCVRDET_out), + .PIPETX3RESET (PIPETX3RESET_out), + .PIPETX3STARTBLOCK (PIPETX3STARTBLOCK_out), + .PIPETX3SWING (PIPETX3SWING_out), + .PIPETX3SYNCHEADER (PIPETX3SYNCHEADER_out), + .PIPETX4CHARISK (PIPETX4CHARISK_out), + .PIPETX4COMPLIANCE (PIPETX4COMPLIANCE_out), + .PIPETX4DATA (PIPETX4DATA_out), + .PIPETX4DATAVALID (PIPETX4DATAVALID_out), + .PIPETX4DEEMPH (PIPETX4DEEMPH_out), + .PIPETX4ELECIDLE (PIPETX4ELECIDLE_out), + .PIPETX4EQCONTROL (PIPETX4EQCONTROL_out), + .PIPETX4EQDEEMPH (PIPETX4EQDEEMPH_out), + .PIPETX4EQPRESET (PIPETX4EQPRESET_out), + .PIPETX4MARGIN (PIPETX4MARGIN_out), + .PIPETX4POWERDOWN (PIPETX4POWERDOWN_out), + .PIPETX4RATE (PIPETX4RATE_out), + .PIPETX4RCVRDET (PIPETX4RCVRDET_out), + .PIPETX4RESET (PIPETX4RESET_out), + .PIPETX4STARTBLOCK (PIPETX4STARTBLOCK_out), + .PIPETX4SWING (PIPETX4SWING_out), + .PIPETX4SYNCHEADER (PIPETX4SYNCHEADER_out), + .PIPETX5CHARISK (PIPETX5CHARISK_out), + .PIPETX5COMPLIANCE (PIPETX5COMPLIANCE_out), + .PIPETX5DATA (PIPETX5DATA_out), + .PIPETX5DATAVALID (PIPETX5DATAVALID_out), + .PIPETX5DEEMPH (PIPETX5DEEMPH_out), + .PIPETX5ELECIDLE (PIPETX5ELECIDLE_out), + .PIPETX5EQCONTROL (PIPETX5EQCONTROL_out), + .PIPETX5EQDEEMPH (PIPETX5EQDEEMPH_out), + .PIPETX5EQPRESET (PIPETX5EQPRESET_out), + .PIPETX5MARGIN (PIPETX5MARGIN_out), + .PIPETX5POWERDOWN (PIPETX5POWERDOWN_out), + .PIPETX5RATE (PIPETX5RATE_out), + .PIPETX5RCVRDET (PIPETX5RCVRDET_out), + .PIPETX5RESET (PIPETX5RESET_out), + .PIPETX5STARTBLOCK (PIPETX5STARTBLOCK_out), + .PIPETX5SWING (PIPETX5SWING_out), + .PIPETX5SYNCHEADER (PIPETX5SYNCHEADER_out), + .PIPETX6CHARISK (PIPETX6CHARISK_out), + .PIPETX6COMPLIANCE (PIPETX6COMPLIANCE_out), + .PIPETX6DATA (PIPETX6DATA_out), + .PIPETX6DATAVALID (PIPETX6DATAVALID_out), + .PIPETX6DEEMPH (PIPETX6DEEMPH_out), + .PIPETX6ELECIDLE (PIPETX6ELECIDLE_out), + .PIPETX6EQCONTROL (PIPETX6EQCONTROL_out), + .PIPETX6EQDEEMPH (PIPETX6EQDEEMPH_out), + .PIPETX6EQPRESET (PIPETX6EQPRESET_out), + .PIPETX6MARGIN (PIPETX6MARGIN_out), + .PIPETX6POWERDOWN (PIPETX6POWERDOWN_out), + .PIPETX6RATE (PIPETX6RATE_out), + .PIPETX6RCVRDET (PIPETX6RCVRDET_out), + .PIPETX6RESET (PIPETX6RESET_out), + .PIPETX6STARTBLOCK (PIPETX6STARTBLOCK_out), + .PIPETX6SWING (PIPETX6SWING_out), + .PIPETX6SYNCHEADER (PIPETX6SYNCHEADER_out), + .PIPETX7CHARISK (PIPETX7CHARISK_out), + .PIPETX7COMPLIANCE (PIPETX7COMPLIANCE_out), + .PIPETX7DATA (PIPETX7DATA_out), + .PIPETX7DATAVALID (PIPETX7DATAVALID_out), + .PIPETX7DEEMPH (PIPETX7DEEMPH_out), + .PIPETX7ELECIDLE (PIPETX7ELECIDLE_out), + .PIPETX7EQCONTROL (PIPETX7EQCONTROL_out), + .PIPETX7EQDEEMPH (PIPETX7EQDEEMPH_out), + .PIPETX7EQPRESET (PIPETX7EQPRESET_out), + .PIPETX7MARGIN (PIPETX7MARGIN_out), + .PIPETX7POWERDOWN (PIPETX7POWERDOWN_out), + .PIPETX7RATE (PIPETX7RATE_out), + .PIPETX7RCVRDET (PIPETX7RCVRDET_out), + .PIPETX7RESET (PIPETX7RESET_out), + .PIPETX7STARTBLOCK (PIPETX7STARTBLOCK_out), + .PIPETX7SWING (PIPETX7SWING_out), + .PIPETX7SYNCHEADER (PIPETX7SYNCHEADER_out), + .PLEQINPROGRESS (PLEQINPROGRESS_out), + .PLEQPHASE (PLEQPHASE_out), + .PMVOUT (PMVOUT_out), + .SAXISCCTREADY (SAXISCCTREADY_out), + .SAXISRQTREADY (SAXISRQTREADY_out), + .SCANOUT (SCANOUT_out), + .SPAREOUT (SPAREOUT_out), + .XILUNCONNBOUT (XILUNCONNBOUT_out), + .XILUNCONNOUT (XILUNCONNOUT_out), + .CFGCONFIGSPACEENABLE (CFGCONFIGSPACEENABLE_in), + .CFGDEVID (CFGDEVID_in), + .CFGDSBUSNUMBER (CFGDSBUSNUMBER_in), + .CFGDSDEVICENUMBER (CFGDSDEVICENUMBER_in), + .CFGDSFUNCTIONNUMBER (CFGDSFUNCTIONNUMBER_in), + .CFGDSN (CFGDSN_in), + .CFGDSPORTNUMBER (CFGDSPORTNUMBER_in), + .CFGERRCORIN (CFGERRCORIN_in), + .CFGERRUNCORIN (CFGERRUNCORIN_in), + .CFGEXTREADDATA (CFGEXTREADDATA_in), + .CFGEXTREADDATAVALID (CFGEXTREADDATAVALID_in), + .CFGFCSEL (CFGFCSEL_in), + .CFGFLRDONE (CFGFLRDONE_in), + .CFGHOTRESETIN (CFGHOTRESETIN_in), + .CFGINTERRUPTINT (CFGINTERRUPTINT_in), + .CFGINTERRUPTMSIATTR (CFGINTERRUPTMSIATTR_in), + .CFGINTERRUPTMSIFUNCTIONNUMBER (CFGINTERRUPTMSIFUNCTIONNUMBER_in), + .CFGINTERRUPTMSIINT (CFGINTERRUPTMSIINT_in), + .CFGINTERRUPTMSIPENDINGSTATUS (CFGINTERRUPTMSIPENDINGSTATUS_in), + .CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in), + .CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in), + .CFGINTERRUPTMSISELECT (CFGINTERRUPTMSISELECT_in), + .CFGINTERRUPTMSITPHPRESENT (CFGINTERRUPTMSITPHPRESENT_in), + .CFGINTERRUPTMSITPHSTTAG (CFGINTERRUPTMSITPHSTTAG_in), + .CFGINTERRUPTMSITPHTYPE (CFGINTERRUPTMSITPHTYPE_in), + .CFGINTERRUPTMSIXADDRESS (CFGINTERRUPTMSIXADDRESS_in), + .CFGINTERRUPTMSIXDATA (CFGINTERRUPTMSIXDATA_in), + .CFGINTERRUPTMSIXINT (CFGINTERRUPTMSIXINT_in), + .CFGINTERRUPTPENDING (CFGINTERRUPTPENDING_in), + .CFGLINKTRAININGENABLE (CFGLINKTRAININGENABLE_in), + .CFGMGMTADDR (CFGMGMTADDR_in), + .CFGMGMTBYTEENABLE (CFGMGMTBYTEENABLE_in), + .CFGMGMTREAD (CFGMGMTREAD_in), + .CFGMGMTTYPE1CFGREGACCESS (CFGMGMTTYPE1CFGREGACCESS_in), + .CFGMGMTWRITE (CFGMGMTWRITE_in), + .CFGMGMTWRITEDATA (CFGMGMTWRITEDATA_in), + .CFGMSGTRANSMIT (CFGMSGTRANSMIT_in), + .CFGMSGTRANSMITDATA (CFGMSGTRANSMITDATA_in), + .CFGMSGTRANSMITTYPE (CFGMSGTRANSMITTYPE_in), + .CFGPERFUNCSTATUSCONTROL (CFGPERFUNCSTATUSCONTROL_in), + .CFGPERFUNCTIONNUMBER (CFGPERFUNCTIONNUMBER_in), + .CFGPERFUNCTIONOUTPUTREQUEST (CFGPERFUNCTIONOUTPUTREQUEST_in), + .CFGPOWERSTATECHANGEACK (CFGPOWERSTATECHANGEACK_in), + .CFGREQPMTRANSITIONL23READY (CFGREQPMTRANSITIONL23READY_in), + .CFGREVID (CFGREVID_in), + .CFGSUBSYSID (CFGSUBSYSID_in), + .CFGSUBSYSVENDID (CFGSUBSYSVENDID_in), + .CFGTPHSTTREADDATA (CFGTPHSTTREADDATA_in), + .CFGTPHSTTREADDATAVALID (CFGTPHSTTREADDATAVALID_in), + .CFGVENDID (CFGVENDID_in), + .CFGVFFLRDONE (CFGVFFLRDONE_in), + .CONFMCAPREQUESTBYCONF (CONFMCAPREQUESTBYCONF_in), + .CONFREQDATA (CONFREQDATA_in), + .CONFREQREGNUM (CONFREQREGNUM_in), + .CONFREQTYPE (CONFREQTYPE_in), + .CONFREQVALID (CONFREQVALID_in), + .CORECLK (CORECLK_in), + .CORECLKMICOMPLETIONRAML (CORECLKMICOMPLETIONRAML_in), + .CORECLKMICOMPLETIONRAMU (CORECLKMICOMPLETIONRAMU_in), + .CORECLKMIREPLAYRAM (CORECLKMIREPLAYRAM_in), + .CORECLKMIREQUESTRAM (CORECLKMIREQUESTRAM_in), + .DBGCFGLOCALMGMTREGOVERRIDE (DBGCFGLOCALMGMTREGOVERRIDE_in), + .DBGDATASEL (DBGDATASEL_in), + .DRPADDR (DRPADDR_in), + .DRPCLK (DRPCLK_in), + .DRPDI (DRPDI_in), + .DRPEN (DRPEN_in), + .DRPWE (DRPWE_in), + .LL2LMSAXISTXTUSER (LL2LMSAXISTXTUSER_in), + .LL2LMSAXISTXTVALID (LL2LMSAXISTXTVALID_in), + .LL2LMTXTLPID0 (LL2LMTXTLPID0_in), + .LL2LMTXTLPID1 (LL2LMTXTLPID1_in), + .MAXISCQTREADY (MAXISCQTREADY_in), + .MAXISRCTREADY (MAXISRCTREADY_in), + .MCAPCLK (MCAPCLK_in), + .MCAPPERST0B (MCAPPERST0B_in), + .MCAPPERST1B (MCAPPERST1B_in), + .MGMTRESETN (MGMTRESETN_in), + .MGMTSTICKYRESETN (MGMTSTICKYRESETN_in), + .MICOMPLETIONRAMREADDATA (MICOMPLETIONRAMREADDATA_in), + .MIREPLAYRAMREADDATA (MIREPLAYRAMREADDATA_in), + .MIREQUESTRAMREADDATA (MIREQUESTRAMREADDATA_in), + .PCIECQNPREQ (PCIECQNPREQ_in), + .PIPECLK (PIPECLK_in), + .PIPEEQFS (PIPEEQFS_in), + .PIPEEQLF (PIPEEQLF_in), + .PIPERESETN (PIPERESETN_in), + .PIPERX0CHARISK (PIPERX0CHARISK_in), + .PIPERX0DATA (PIPERX0DATA_in), + .PIPERX0DATAVALID (PIPERX0DATAVALID_in), + .PIPERX0ELECIDLE (PIPERX0ELECIDLE_in), + .PIPERX0EQDONE (PIPERX0EQDONE_in), + .PIPERX0EQLPADAPTDONE (PIPERX0EQLPADAPTDONE_in), + .PIPERX0EQLPLFFSSEL (PIPERX0EQLPLFFSSEL_in), + .PIPERX0EQLPNEWTXCOEFFORPRESET (PIPERX0EQLPNEWTXCOEFFORPRESET_in), + .PIPERX0PHYSTATUS (PIPERX0PHYSTATUS_in), + .PIPERX0STARTBLOCK (PIPERX0STARTBLOCK_in), + .PIPERX0STATUS (PIPERX0STATUS_in), + .PIPERX0SYNCHEADER (PIPERX0SYNCHEADER_in), + .PIPERX0VALID (PIPERX0VALID_in), + .PIPERX1CHARISK (PIPERX1CHARISK_in), + .PIPERX1DATA (PIPERX1DATA_in), + .PIPERX1DATAVALID (PIPERX1DATAVALID_in), + .PIPERX1ELECIDLE (PIPERX1ELECIDLE_in), + .PIPERX1EQDONE (PIPERX1EQDONE_in), + .PIPERX1EQLPADAPTDONE (PIPERX1EQLPADAPTDONE_in), + .PIPERX1EQLPLFFSSEL (PIPERX1EQLPLFFSSEL_in), + .PIPERX1EQLPNEWTXCOEFFORPRESET (PIPERX1EQLPNEWTXCOEFFORPRESET_in), + .PIPERX1PHYSTATUS (PIPERX1PHYSTATUS_in), + .PIPERX1STARTBLOCK (PIPERX1STARTBLOCK_in), + .PIPERX1STATUS (PIPERX1STATUS_in), + .PIPERX1SYNCHEADER (PIPERX1SYNCHEADER_in), + .PIPERX1VALID (PIPERX1VALID_in), + .PIPERX2CHARISK (PIPERX2CHARISK_in), + .PIPERX2DATA (PIPERX2DATA_in), + .PIPERX2DATAVALID (PIPERX2DATAVALID_in), + .PIPERX2ELECIDLE (PIPERX2ELECIDLE_in), + .PIPERX2EQDONE (PIPERX2EQDONE_in), + .PIPERX2EQLPADAPTDONE (PIPERX2EQLPADAPTDONE_in), + .PIPERX2EQLPLFFSSEL (PIPERX2EQLPLFFSSEL_in), + .PIPERX2EQLPNEWTXCOEFFORPRESET (PIPERX2EQLPNEWTXCOEFFORPRESET_in), + .PIPERX2PHYSTATUS (PIPERX2PHYSTATUS_in), + .PIPERX2STARTBLOCK (PIPERX2STARTBLOCK_in), + .PIPERX2STATUS (PIPERX2STATUS_in), + .PIPERX2SYNCHEADER (PIPERX2SYNCHEADER_in), + .PIPERX2VALID (PIPERX2VALID_in), + .PIPERX3CHARISK (PIPERX3CHARISK_in), + .PIPERX3DATA (PIPERX3DATA_in), + .PIPERX3DATAVALID (PIPERX3DATAVALID_in), + .PIPERX3ELECIDLE (PIPERX3ELECIDLE_in), + .PIPERX3EQDONE (PIPERX3EQDONE_in), + .PIPERX3EQLPADAPTDONE (PIPERX3EQLPADAPTDONE_in), + .PIPERX3EQLPLFFSSEL (PIPERX3EQLPLFFSSEL_in), + .PIPERX3EQLPNEWTXCOEFFORPRESET (PIPERX3EQLPNEWTXCOEFFORPRESET_in), + .PIPERX3PHYSTATUS (PIPERX3PHYSTATUS_in), + .PIPERX3STARTBLOCK (PIPERX3STARTBLOCK_in), + .PIPERX3STATUS (PIPERX3STATUS_in), + .PIPERX3SYNCHEADER (PIPERX3SYNCHEADER_in), + .PIPERX3VALID (PIPERX3VALID_in), + .PIPERX4CHARISK (PIPERX4CHARISK_in), + .PIPERX4DATA (PIPERX4DATA_in), + .PIPERX4DATAVALID (PIPERX4DATAVALID_in), + .PIPERX4ELECIDLE (PIPERX4ELECIDLE_in), + .PIPERX4EQDONE (PIPERX4EQDONE_in), + .PIPERX4EQLPADAPTDONE (PIPERX4EQLPADAPTDONE_in), + .PIPERX4EQLPLFFSSEL (PIPERX4EQLPLFFSSEL_in), + .PIPERX4EQLPNEWTXCOEFFORPRESET (PIPERX4EQLPNEWTXCOEFFORPRESET_in), + .PIPERX4PHYSTATUS (PIPERX4PHYSTATUS_in), + .PIPERX4STARTBLOCK (PIPERX4STARTBLOCK_in), + .PIPERX4STATUS (PIPERX4STATUS_in), + .PIPERX4SYNCHEADER (PIPERX4SYNCHEADER_in), + .PIPERX4VALID (PIPERX4VALID_in), + .PIPERX5CHARISK (PIPERX5CHARISK_in), + .PIPERX5DATA (PIPERX5DATA_in), + .PIPERX5DATAVALID (PIPERX5DATAVALID_in), + .PIPERX5ELECIDLE (PIPERX5ELECIDLE_in), + .PIPERX5EQDONE (PIPERX5EQDONE_in), + .PIPERX5EQLPADAPTDONE (PIPERX5EQLPADAPTDONE_in), + .PIPERX5EQLPLFFSSEL (PIPERX5EQLPLFFSSEL_in), + .PIPERX5EQLPNEWTXCOEFFORPRESET (PIPERX5EQLPNEWTXCOEFFORPRESET_in), + .PIPERX5PHYSTATUS (PIPERX5PHYSTATUS_in), + .PIPERX5STARTBLOCK (PIPERX5STARTBLOCK_in), + .PIPERX5STATUS (PIPERX5STATUS_in), + .PIPERX5SYNCHEADER (PIPERX5SYNCHEADER_in), + .PIPERX5VALID (PIPERX5VALID_in), + .PIPERX6CHARISK (PIPERX6CHARISK_in), + .PIPERX6DATA (PIPERX6DATA_in), + .PIPERX6DATAVALID (PIPERX6DATAVALID_in), + .PIPERX6ELECIDLE (PIPERX6ELECIDLE_in), + .PIPERX6EQDONE (PIPERX6EQDONE_in), + .PIPERX6EQLPADAPTDONE (PIPERX6EQLPADAPTDONE_in), + .PIPERX6EQLPLFFSSEL (PIPERX6EQLPLFFSSEL_in), + .PIPERX6EQLPNEWTXCOEFFORPRESET (PIPERX6EQLPNEWTXCOEFFORPRESET_in), + .PIPERX6PHYSTATUS (PIPERX6PHYSTATUS_in), + .PIPERX6STARTBLOCK (PIPERX6STARTBLOCK_in), + .PIPERX6STATUS (PIPERX6STATUS_in), + .PIPERX6SYNCHEADER (PIPERX6SYNCHEADER_in), + .PIPERX6VALID (PIPERX6VALID_in), + .PIPERX7CHARISK (PIPERX7CHARISK_in), + .PIPERX7DATA (PIPERX7DATA_in), + .PIPERX7DATAVALID (PIPERX7DATAVALID_in), + .PIPERX7ELECIDLE (PIPERX7ELECIDLE_in), + .PIPERX7EQDONE (PIPERX7EQDONE_in), + .PIPERX7EQLPADAPTDONE (PIPERX7EQLPADAPTDONE_in), + .PIPERX7EQLPLFFSSEL (PIPERX7EQLPLFFSSEL_in), + .PIPERX7EQLPNEWTXCOEFFORPRESET (PIPERX7EQLPNEWTXCOEFFORPRESET_in), + .PIPERX7PHYSTATUS (PIPERX7PHYSTATUS_in), + .PIPERX7STARTBLOCK (PIPERX7STARTBLOCK_in), + .PIPERX7STATUS (PIPERX7STATUS_in), + .PIPERX7SYNCHEADER (PIPERX7SYNCHEADER_in), + .PIPERX7VALID (PIPERX7VALID_in), + .PIPETX0EQCOEFF (PIPETX0EQCOEFF_in), + .PIPETX0EQDONE (PIPETX0EQDONE_in), + .PIPETX1EQCOEFF (PIPETX1EQCOEFF_in), + .PIPETX1EQDONE (PIPETX1EQDONE_in), + .PIPETX2EQCOEFF (PIPETX2EQCOEFF_in), + .PIPETX2EQDONE (PIPETX2EQDONE_in), + .PIPETX3EQCOEFF (PIPETX3EQCOEFF_in), + .PIPETX3EQDONE (PIPETX3EQDONE_in), + .PIPETX4EQCOEFF (PIPETX4EQCOEFF_in), + .PIPETX4EQDONE (PIPETX4EQDONE_in), + .PIPETX5EQCOEFF (PIPETX5EQCOEFF_in), + .PIPETX5EQDONE (PIPETX5EQDONE_in), + .PIPETX6EQCOEFF (PIPETX6EQCOEFF_in), + .PIPETX6EQDONE (PIPETX6EQDONE_in), + .PIPETX7EQCOEFF (PIPETX7EQCOEFF_in), + .PIPETX7EQDONE (PIPETX7EQDONE_in), + .PLEQRESETEIEOSCOUNT (PLEQRESETEIEOSCOUNT_in), + .PLGEN2UPSTREAMPREFERDEEMPH (PLGEN2UPSTREAMPREFERDEEMPH_in), + .PMVDIVIDE (PMVDIVIDE_in), + .PMVENABLEN (PMVENABLEN_in), + .PMVSELECT (PMVSELECT_in), + .RESETN (RESETN_in), + .SAXISCCTDATA (SAXISCCTDATA_in), + .SAXISCCTKEEP (SAXISCCTKEEP_in), + .SAXISCCTLAST (SAXISCCTLAST_in), + .SAXISCCTUSER (SAXISCCTUSER_in), + .SAXISCCTVALID (SAXISCCTVALID_in), + .SAXISRQTDATA (SAXISRQTDATA_in), + .SAXISRQTKEEP (SAXISRQTKEEP_in), + .SAXISRQTLAST (SAXISRQTLAST_in), + .SAXISRQTUSER (SAXISRQTUSER_in), + .SAXISRQTVALID (SAXISRQTVALID_in), + .SCANENABLEN (SCANENABLEN_in), + .SCANIN (SCANIN_in), + .SCANMODEN (SCANMODEN_in), + .SPAREIN (SPAREIN_in), + .USERCLK (USERCLK_in), + .XILUNCONNBYP (XILUNCONNBYP_in), + .XILUNCONNCLK (XILUNCONNCLK_in), + .XILUNCONNIN (XILUNCONNIN_in), + .GSR (glblGSR) + ); + + specify + (CORECLK => DBGDATAOUT[0]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[10]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[11]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[12]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[13]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[14]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[15]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[1]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[2]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[3]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[4]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[5]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[6]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[7]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[8]) = (0:0:0, 0:0:0); + (CORECLK => DBGDATAOUT[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[10]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[11]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[12]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[13]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[14]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[15]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[16]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[17]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[18]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[19]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[20]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[21]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[22]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[23]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[24]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[25]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[26]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[27]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[28]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[29]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[30]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[31]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[32]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[33]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[34]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[35]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[36]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[37]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[38]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[39]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[40]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[41]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[42]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[43]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[44]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[45]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[46]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[47]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[48]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[49]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[50]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[51]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[52]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[53]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[54]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[55]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[56]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[57]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[58]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[59]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[60]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[61]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[62]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[63]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[64]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[65]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[66]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[67]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[68]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[69]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[70]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[71]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[10]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[11]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[12]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[13]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[14]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[15]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[16]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[17]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[18]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[19]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[20]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[21]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[22]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[23]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[24]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[25]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[26]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[27]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[28]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[29]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[30]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[31]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[32]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[33]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[34]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[35]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[36]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[37]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[38]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[39]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[3]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[40]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[41]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[42]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[43]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[44]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[45]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[46]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[47]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[48]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[49]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[4]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[50]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[51]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[52]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[53]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[54]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[55]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[56]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[57]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[58]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[59]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[5]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[60]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[61]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[62]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[63]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[64]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[65]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[66]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[67]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[68]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[69]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[6]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[70]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[71]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[7]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[8]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[9]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[0]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[1]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[2]) = (0:0:0, 0:0:0); + (CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMREADENABLE[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMREADENABLE[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[100]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[101]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[102]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[103]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[104]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[105]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[106]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[107]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[108]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[109]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[10]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[110]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[111]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[112]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[113]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[114]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[115]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[116]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[117]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[118]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[119]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[11]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[120]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[121]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[122]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[123]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[124]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[125]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[126]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[127]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[128]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[129]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[12]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[130]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[131]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[132]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[133]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[134]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[135]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[136]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[137]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[138]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[139]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[13]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[140]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[141]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[142]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[143]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[14]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[15]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[16]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[17]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[18]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[19]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[1]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[20]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[21]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[22]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[23]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[24]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[25]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[26]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[27]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[28]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[29]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[2]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[30]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[31]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[32]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[33]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[34]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[35]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[36]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[37]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[38]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[39]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[3]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[40]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[41]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[42]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[43]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[44]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[45]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[46]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[47]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[48]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[49]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[4]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[50]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[51]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[52]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[53]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[54]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[55]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[56]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[57]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[58]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[59]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[5]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[60]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[61]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[62]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[63]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[64]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[65]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[66]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[67]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[68]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[69]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[6]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[70]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[71]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[72]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[73]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[74]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[75]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[76]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[77]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[78]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[79]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[7]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[80]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[81]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[82]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[83]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[84]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[85]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[86]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[87]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[88]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[89]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[8]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[90]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[91]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[92]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[93]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[94]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[95]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[96]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[97]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[98]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[99]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[9]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEENABLE[0]) = (0:0:0, 0:0:0); + (CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEENABLE[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[4]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[5]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[6]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[7]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[8]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[4]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[5]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[6]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[7]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[8]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[4]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[5]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[6]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[7]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[8]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[4]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[5]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[6]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[7]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[8]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[100]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[101]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[102]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[103]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[104]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[105]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[106]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[107]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[108]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[109]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[10]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[110]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[111]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[112]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[113]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[114]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[115]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[116]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[117]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[118]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[119]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[11]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[120]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[121]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[122]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[123]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[124]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[125]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[126]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[127]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[128]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[129]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[12]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[130]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[131]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[132]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[133]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[134]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[135]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[136]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[137]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[138]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[139]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[13]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[140]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[141]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[142]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[143]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[14]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[15]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[16]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[17]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[18]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[19]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[20]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[21]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[22]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[23]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[24]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[25]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[26]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[27]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[28]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[29]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[30]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[31]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[32]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[33]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[34]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[35]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[36]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[37]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[38]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[39]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[3]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[40]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[41]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[42]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[43]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[44]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[45]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[46]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[47]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[48]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[49]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[4]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[50]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[51]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[52]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[53]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[54]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[55]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[56]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[57]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[58]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[59]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[5]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[60]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[61]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[62]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[63]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[64]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[65]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[66]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[67]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[68]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[69]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[6]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[70]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[71]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[72]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[73]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[74]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[75]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[76]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[77]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[78]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[79]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[7]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[80]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[81]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[82]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[83]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[84]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[85]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[86]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[87]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[88]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[89]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[8]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[90]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[91]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[92]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[93]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[94]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[95]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[96]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[97]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[98]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[99]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[9]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[0]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[1]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[2]) = (0:0:0, 0:0:0); + (CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[3]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[0]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[10]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[11]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[12]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[13]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[14]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[15]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[1]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[2]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[3]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[4]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[5]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[6]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[7]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[8]) = (0:0:0, 0:0:0); + (DRPCLK => DRPDO[9]) = (0:0:0, 0:0:0); + (DRPCLK => DRPRDY) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPCSB) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[0]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[10]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[11]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[12]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[13]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[14]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[15]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[16]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[17]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[18]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[19]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[1]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[20]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[21]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[22]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[23]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[24]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[25]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[26]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[27]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[28]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[29]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[2]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[30]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[31]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[3]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[4]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[5]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[6]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[7]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[8]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPDATA[9]) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPEOS) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPERROR) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPMODE) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPRDATAVALID) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPRDWRB) = (0:0:0, 0:0:0); + (MCAPCLK => DBGMCAPRESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX0POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX1POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX2POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX3POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX4POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX5POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX6POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPLFFS[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPTXPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPTXPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPTXPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQLPTXPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPERX7POLARITY) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX0SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX1SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX2SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX3SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX4SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX5SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX6SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7CHARISK[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7CHARISK[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7COMPLIANCE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATAVALID) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[10]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[11]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[12]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[13]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[14]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[15]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[16]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[17]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[18]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[19]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[20]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[21]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[22]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[23]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[24]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[25]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[26]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[27]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[28]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[29]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[30]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[31]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[6]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[7]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[8]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DATA[9]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7DEEMPH) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7ELECIDLE) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQCONTROL[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQCONTROL[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[4]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQDEEMPH[5]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQPRESET[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQPRESET[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQPRESET[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7EQPRESET[3]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7MARGIN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7MARGIN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7MARGIN[2]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7POWERDOWN[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7POWERDOWN[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7RATE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7RATE[1]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7RCVRDET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7RESET) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7STARTBLOCK) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7SWING) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7SYNCHEADER[0]) = (0:0:0, 0:0:0); + (PIPECLK => PIPETX7SYNCHEADER[1]) = (0:0:0, 0:0:0); + (PIPECLK => PLEQINPROGRESS) = (0:0:0, 0:0:0); + (PIPECLK => PLEQPHASE[0]) = (0:0:0, 0:0:0); + (PIPECLK => PLEQPHASE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGCURRENTSPEED[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGCURRENTSPEED[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGCURRENTSPEED[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGDPASUBSTATECHANGE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGDPASUBSTATECHANGE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGERRCOROUT) = (0:0:0, 0:0:0); + (USERCLK => CFGERRFATALOUT) = (0:0:0, 0:0:0); + (USERCLK => CFGERRNONFATALOUT) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTFUNCTIONNUMBER[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREADRECEIVED) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTREGISTERNUMBER[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEBYTEENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEBYTEENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEBYTEENABLE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEBYTEENABLE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITEDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGEXTWRITERECEIVED) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLD[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCCPLH[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPD[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCNPH[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPD[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFCPH[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGFLRINPROCESS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFLRINPROCESS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONPOWERSTATE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGFUNCTIONSTATUS[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGHOTRESETOUT) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIFAIL) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMASKUPDATE) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIMMENABLE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSISENT) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIVFENABLE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXFAIL) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXMASK[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXMASK[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXSENT) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFENABLE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTMSIXVFMASK[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGINTERRUPTSENT) = (0:0:0, 0:0:0); + (USERCLK => CFGLINKPOWERSTATE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGLINKPOWERSTATE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGLOCALERROR) = (0:0:0, 0:0:0); + (USERCLK => CFGLTRENABLE) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGLTSSMSTATE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXPAYLOAD[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXPAYLOAD[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXPAYLOAD[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXREADREQ[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXREADREQ[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGMAXREADREQ[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGMGMTREADWRITEDONE) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVED) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDTYPE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDTYPE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDTYPE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDTYPE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGRECEIVEDTYPE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGMSGTRANSMITDONE) = (0:0:0, 0:0:0); + (USERCLK => CFGNEGOTIATEDWIDTH[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGNEGOTIATEDWIDTH[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGNEGOTIATEDWIDTH[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGNEGOTIATEDWIDTH[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGOBFFENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGOBFFENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCSTATUSDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGPERFUNCTIONUPDATEDONE) = (0:0:0, 0:0:0); + (USERCLK => CFGPHYLINKDOWN) = (0:0:0, 0:0:0); + (USERCLK => CFGPHYLINKSTATUS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGPHYLINKSTATUS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGPLSTATUSCHANGE) = (0:0:0, 0:0:0); + (USERCLK => CFGPOWERSTATECHANGEINTERRUPT) = (0:0:0, 0:0:0); + (USERCLK => CFGRCBSTATUS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGRCBSTATUS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHFUNCTIONNUM[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHFUNCTIONNUM[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHFUNCTIONNUM[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHFUNCTIONNUM[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHREQUESTERENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHREQUESTERENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTMODE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTADDRESS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTADDRESS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTADDRESS[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTADDRESS[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTADDRESS[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTREADENABLE) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEBYTEVALID[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEBYTEVALID[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEBYTEVALID[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEBYTEVALID[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGTPHSTTWRITEENABLE) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFFLRINPROCESS[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFPOWERSTATE[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFSTATUS[9]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHREQUESTERENABLE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[0]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[10]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[11]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[12]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[13]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[14]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[15]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[16]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[17]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[1]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[2]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[3]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[4]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[5]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[6]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[7]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[8]) = (0:0:0, 0:0:0); + (USERCLK => CFGVFTPHSTMODE[9]) = (0:0:0, 0:0:0); + (USERCLK => CONFMCAPDESIGNSWITCH) = (0:0:0, 0:0:0); + (USERCLK => CONFMCAPEOS) = (0:0:0, 0:0:0); + (USERCLK => CONFMCAPINUSEBYPCIE) = (0:0:0, 0:0:0); + (USERCLK => CONFREQREADY) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPRDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => CONFRESPVALID) = (0:0:0, 0:0:0); + (USERCLK => DBGPLDATABLOCKRECEIVEDAFTEREDS) = (0:0:0, 0:0:0); + (USERCLK => DBGPLGEN3FRAMINGERRORDETECTED) = (0:0:0, 0:0:0); + (USERCLK => DBGPLGEN3SYNCHEADERERRORDETECTED) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[0]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[1]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[2]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[3]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[4]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[5]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[6]) = (0:0:0, 0:0:0); + (USERCLK => DBGPLINFERREDRXELECTRICALIDLE[7]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENT0) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENT1) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID0[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID0[1]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID0[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID0[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID1[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID1[1]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID1[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMASTERTLPSENTTLPID1[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[100]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[101]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[102]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[103]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[104]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[105]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[106]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[107]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[108]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[109]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[110]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[111]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[112]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[113]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[114]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[115]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[116]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[117]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[118]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[119]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[120]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[121]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[122]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[123]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[124]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[125]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[126]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[127]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[128]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[129]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[130]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[131]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[132]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[133]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[134]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[135]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[136]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[137]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[138]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[139]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[140]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[141]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[142]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[143]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[144]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[145]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[146]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[147]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[148]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[149]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[150]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[151]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[152]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[153]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[154]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[155]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[156]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[157]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[158]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[159]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[160]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[161]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[162]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[163]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[164]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[165]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[166]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[167]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[168]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[169]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[170]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[171]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[172]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[173]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[174]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[175]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[176]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[177]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[178]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[179]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[180]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[181]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[182]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[183]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[184]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[185]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[186]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[187]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[188]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[189]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[190]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[191]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[192]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[193]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[194]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[195]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[196]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[197]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[198]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[199]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[200]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[201]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[202]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[203]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[204]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[205]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[206]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[207]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[208]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[209]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[210]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[211]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[212]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[213]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[214]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[215]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[216]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[217]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[218]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[219]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[220]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[221]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[222]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[223]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[224]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[225]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[226]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[227]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[228]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[229]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[230]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[231]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[232]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[233]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[234]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[235]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[236]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[237]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[238]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[239]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[240]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[241]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[242]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[243]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[244]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[245]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[246]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[247]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[248]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[249]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[250]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[251]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[252]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[253]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[254]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[255]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[32]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[33]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[34]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[35]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[36]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[37]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[38]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[39]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[40]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[41]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[42]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[43]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[44]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[45]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[46]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[47]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[48]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[49]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[50]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[51]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[52]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[53]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[54]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[55]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[56]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[57]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[58]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[59]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[60]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[61]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[62]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[63]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[64]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[65]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[66]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[67]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[68]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[69]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[70]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[71]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[72]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[73]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[74]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[75]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[76]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[77]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[78]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[79]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[80]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[81]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[82]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[83]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[84]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[85]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[86]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[87]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[88]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[89]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[90]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[91]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[92]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[93]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[94]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[95]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[96]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[97]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[98]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[99]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[10]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[11]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[12]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[13]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[14]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[15]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[16]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[17]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[4]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[5]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[6]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[7]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTUSER[8]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[1]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[4]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[5]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[6]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMMAXISRXTVALID[7]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[0]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[1]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[2]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[3]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[4]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[5]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[6]) = (0:0:0, 0:0:0); + (USERCLK => LL2LMSAXISTXTREADY[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[100]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[101]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[102]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[103]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[104]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[105]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[106]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[107]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[108]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[109]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[110]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[111]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[112]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[113]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[114]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[115]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[116]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[117]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[118]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[119]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[120]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[121]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[122]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[123]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[124]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[125]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[126]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[127]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[128]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[129]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[130]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[131]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[132]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[133]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[134]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[135]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[136]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[137]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[138]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[139]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[140]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[141]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[142]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[143]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[144]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[145]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[146]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[147]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[148]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[149]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[150]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[151]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[152]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[153]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[154]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[155]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[156]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[157]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[158]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[159]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[160]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[161]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[162]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[163]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[164]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[165]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[166]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[167]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[168]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[169]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[170]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[171]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[172]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[173]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[174]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[175]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[176]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[177]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[178]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[179]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[180]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[181]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[182]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[183]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[184]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[185]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[186]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[187]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[188]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[189]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[190]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[191]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[192]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[193]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[194]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[195]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[196]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[197]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[198]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[199]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[200]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[201]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[202]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[203]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[204]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[205]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[206]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[207]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[208]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[209]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[210]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[211]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[212]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[213]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[214]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[215]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[216]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[217]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[218]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[219]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[220]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[221]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[222]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[223]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[224]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[225]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[226]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[227]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[228]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[229]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[230]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[231]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[232]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[233]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[234]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[235]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[236]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[237]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[238]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[239]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[240]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[241]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[242]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[243]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[244]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[245]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[246]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[247]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[248]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[249]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[250]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[251]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[252]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[253]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[254]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[255]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[32]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[33]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[34]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[35]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[36]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[37]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[38]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[39]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[40]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[41]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[42]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[43]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[44]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[45]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[46]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[47]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[48]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[49]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[50]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[51]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[52]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[53]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[54]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[55]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[56]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[57]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[58]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[59]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[60]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[61]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[62]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[63]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[64]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[65]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[66]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[67]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[68]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[69]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[70]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[71]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[72]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[73]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[74]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[75]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[76]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[77]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[78]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[79]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[80]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[81]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[82]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[83]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[84]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[85]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[86]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[87]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[88]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[89]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[90]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[91]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[92]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[93]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[94]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[95]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[96]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[97]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[98]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[99]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTKEEP[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTLAST) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[10]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[11]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[12]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[13]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[14]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[15]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[16]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[17]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[18]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[19]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[20]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[21]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[22]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[23]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[24]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[25]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[26]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[27]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[28]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[29]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[30]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[31]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[32]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[33]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[34]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[35]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[36]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[37]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[38]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[39]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[40]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[41]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[42]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[43]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[44]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[45]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[46]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[47]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[48]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[49]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[50]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[51]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[52]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[53]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[54]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[55]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[56]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[57]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[58]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[59]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[60]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[61]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[62]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[63]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[64]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[65]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[66]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[67]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[68]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[69]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[70]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[71]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[72]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[73]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[74]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[75]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[76]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[77]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[78]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[79]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[80]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[81]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[82]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[83]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[84]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[8]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTUSER[9]) = (0:0:0, 0:0:0); + (USERCLK => MAXISCQTVALID) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[100]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[101]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[102]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[103]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[104]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[105]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[106]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[107]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[108]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[109]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[10]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[110]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[111]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[112]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[113]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[114]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[115]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[116]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[117]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[118]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[119]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[11]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[120]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[121]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[122]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[123]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[124]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[125]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[126]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[127]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[128]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[129]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[12]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[130]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[131]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[132]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[133]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[134]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[135]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[136]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[137]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[138]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[139]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[13]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[140]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[141]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[142]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[143]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[144]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[145]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[146]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[147]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[148]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[149]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[14]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[150]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[151]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[152]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[153]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[154]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[155]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[156]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[157]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[158]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[159]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[15]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[160]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[161]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[162]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[163]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[164]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[165]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[166]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[167]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[168]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[169]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[16]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[170]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[171]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[172]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[173]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[174]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[175]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[176]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[177]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[178]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[179]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[17]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[180]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[181]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[182]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[183]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[184]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[185]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[186]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[187]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[188]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[189]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[18]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[190]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[191]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[192]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[193]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[194]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[195]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[196]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[197]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[198]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[199]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[19]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[200]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[201]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[202]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[203]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[204]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[205]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[206]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[207]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[208]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[209]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[20]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[210]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[211]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[212]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[213]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[214]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[215]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[216]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[217]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[218]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[219]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[21]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[220]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[221]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[222]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[223]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[224]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[225]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[226]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[227]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[228]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[229]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[22]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[230]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[231]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[232]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[233]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[234]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[235]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[236]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[237]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[238]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[239]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[23]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[240]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[241]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[242]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[243]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[244]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[245]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[246]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[247]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[248]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[249]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[24]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[250]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[251]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[252]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[253]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[254]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[255]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[25]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[26]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[27]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[28]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[29]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[30]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[31]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[32]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[33]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[34]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[35]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[36]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[37]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[38]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[39]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[40]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[41]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[42]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[43]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[44]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[45]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[46]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[47]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[48]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[49]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[50]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[51]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[52]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[53]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[54]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[55]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[56]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[57]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[58]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[59]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[60]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[61]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[62]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[63]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[64]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[65]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[66]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[67]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[68]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[69]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[70]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[71]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[72]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[73]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[74]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[75]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[76]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[77]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[78]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[79]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[80]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[81]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[82]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[83]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[84]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[85]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[86]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[87]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[88]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[89]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[8]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[90]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[91]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[92]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[93]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[94]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[95]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[96]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[97]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[98]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[99]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTDATA[9]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTKEEP[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTLAST) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[0]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[10]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[11]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[12]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[13]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[14]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[15]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[16]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[17]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[18]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[19]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[1]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[20]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[21]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[22]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[23]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[24]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[25]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[26]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[27]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[28]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[29]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[2]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[30]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[31]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[32]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[33]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[34]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[35]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[36]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[37]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[38]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[39]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[3]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[40]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[41]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[42]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[43]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[44]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[45]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[46]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[47]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[48]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[49]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[4]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[50]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[51]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[52]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[53]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[54]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[55]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[56]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[57]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[58]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[59]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[5]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[60]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[61]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[62]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[63]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[64]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[65]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[66]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[67]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[68]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[69]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[6]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[70]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[71]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[72]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[73]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[74]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[7]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[8]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTUSER[9]) = (0:0:0, 0:0:0); + (USERCLK => MAXISRCTVALID) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[1]) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[2]) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[3]) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[4]) = (0:0:0, 0:0:0); + (USERCLK => PCIECQNPREQCOUNT[5]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQSEQNUMVLD) = (0:0:0, 0:0:0); + (USERCLK => PCIERQSEQNUM[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQSEQNUM[1]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQSEQNUM[2]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQSEQNUM[3]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAGAV[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAGAV[1]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAGVLD) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[1]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[2]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[3]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[4]) = (0:0:0, 0:0:0); + (USERCLK => PCIERQTAG[5]) = (0:0:0, 0:0:0); + (USERCLK => PCIETFCNPDAV[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIETFCNPDAV[1]) = (0:0:0, 0:0:0); + (USERCLK => PCIETFCNPHAV[0]) = (0:0:0, 0:0:0); + (USERCLK => PCIETFCNPHAV[1]) = (0:0:0, 0:0:0); + (USERCLK => SAXISCCTREADY[0]) = (0:0:0, 0:0:0); + (USERCLK => SAXISCCTREADY[1]) = (0:0:0, 0:0:0); + (USERCLK => SAXISCCTREADY[2]) = (0:0:0, 0:0:0); + (USERCLK => SAXISCCTREADY[3]) = (0:0:0, 0:0:0); + (USERCLK => SAXISRQTREADY[0]) = (0:0:0, 0:0:0); + (USERCLK => SAXISRQTREADY[1]) = (0:0:0, 0:0:0); + (USERCLK => SAXISRQTREADY[2]) = (0:0:0, 0:0:0); + (USERCLK => SAXISRQTREADY[3]) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING // Simprim + $period (negedge CORECLK, 0:0:0, notifier); + $period (negedge CORECLKMICOMPLETIONRAML, 0:0:0, notifier); + $period (negedge CORECLKMICOMPLETIONRAMU, 0:0:0, notifier); + $period (negedge CORECLKMIREPLAYRAM, 0:0:0, notifier); + $period (negedge CORECLKMIREQUESTRAM, 0:0:0, notifier); + $period (negedge DRPCLK, 0:0:0, notifier); + $period (negedge MCAPCLK, 0:0:0, notifier); + $period (negedge PIPECLK, 0:0:0, notifier); + $period (negedge USERCLK, 0:0:0, notifier); + $period (posedge CORECLK, 0:0:0, notifier); + $period (posedge CORECLKMICOMPLETIONRAML, 0:0:0, notifier); + $period (posedge CORECLKMICOMPLETIONRAMU, 0:0:0, notifier); + $period (posedge CORECLKMIREPLAYRAM, 0:0:0, notifier); + $period (posedge CORECLKMIREQUESTRAM, 0:0:0, notifier); + $period (posedge DRPCLK, 0:0:0, notifier); + $period (posedge MCAPCLK, 0:0:0, notifier); + $period (posedge PIPECLK, 0:0:0, notifier); + $period (posedge USERCLK, 0:0:0, notifier); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[9]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[0]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[100]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[101]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[102]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[103]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[104]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[105]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[106]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[107]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[108]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[109]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[10]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[110]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[111]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[112]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[113]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[114]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[115]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[116]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[117]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[118]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[119]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[11]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[120]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[121]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[122]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[123]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[124]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[125]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[126]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[127]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[128]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[129]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[12]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[130]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[131]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[132]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[133]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[134]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[135]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[136]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[137]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[138]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[139]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[13]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[140]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[141]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[142]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[143]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[14]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[15]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[16]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[17]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[18]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[19]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[1]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[20]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[21]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[22]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[23]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[24]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[25]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[26]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[27]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[28]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[29]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[2]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[30]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[31]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[32]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[33]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[34]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[35]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[36]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[37]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[38]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[39]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[3]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[40]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[41]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[42]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[43]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[44]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[45]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[46]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[47]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[48]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[49]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[4]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[50]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[51]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[52]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[53]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[54]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[55]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[56]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[57]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[58]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[59]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[5]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[60]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[61]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[62]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[63]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[64]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[65]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[66]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[67]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[68]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[69]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[6]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[70]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[71]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[72]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[73]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[74]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[75]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[76]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[77]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[78]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[79]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[7]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[80]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[81]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[82]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[83]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[84]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[85]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[86]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[87]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[88]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[89]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[8]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[90]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[91]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[92]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[93]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[94]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[95]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[96]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[97]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[98]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[99]); + $setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay); + $setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]); + $setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]); + $setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]); + $setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]); + $setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]); + $setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]); + $setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]); + $setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]); + $setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]); + $setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]); + $setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]); + $setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]); + $setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]); + $setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]); + $setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]); + $setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]); + $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay); + $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATAVALID_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[18]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[19]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[20]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[21]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[22]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[23]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[24]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[25]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[26]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[27]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[28]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[29]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[30]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[31]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7ELECIDLE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7PHYSTATUS_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STARTBLOCK_delay); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7VALID_delay); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, negedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQDONE_delay); + $setuphold (posedge PIPECLK, negedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLEQRESETEIEOSCOUNT_delay); + $setuphold (posedge PIPECLK, negedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATAVALID_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[18]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[19]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[20]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[21]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[22]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[23]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[24]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[25]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[26]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[27]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[28]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[29]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[30]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[31]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7ELECIDLE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPADAPTDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPLFFSSEL_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7PHYSTATUS_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STARTBLOCK_delay); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7VALID_delay); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[0]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[10]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[11]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[12]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[13]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[14]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[15]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[16]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[17]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[1]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[2]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[3]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[4]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[5]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[6]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[7]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[8]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[9]); + $setuphold (posedge PIPECLK, posedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQDONE_delay); + $setuphold (posedge PIPECLK, posedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLEQRESETEIEOSCOUNT_delay); + $setuphold (posedge PIPECLK, posedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay); + $setuphold (posedge USERCLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge USERCLK, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[10]); + $setuphold (posedge USERCLK, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[11]); + $setuphold (posedge USERCLK, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[12]); + $setuphold (posedge USERCLK, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[13]); + $setuphold (posedge USERCLK, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[14]); + $setuphold (posedge USERCLK, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[15]); + $setuphold (posedge USERCLK, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[3]); + $setuphold (posedge USERCLK, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[4]); + $setuphold (posedge USERCLK, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[5]); + $setuphold (posedge USERCLK, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[6]); + $setuphold (posedge USERCLK, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[7]); + $setuphold (posedge USERCLK, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[8]); + $setuphold (posedge USERCLK, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[9]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[10]); + $setuphold (posedge USERCLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[11]); + $setuphold (posedge USERCLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[12]); + $setuphold (posedge USERCLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[13]); + $setuphold (posedge USERCLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[14]); + $setuphold (posedge USERCLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[15]); + $setuphold (posedge USERCLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[16]); + $setuphold (posedge USERCLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[17]); + $setuphold (posedge USERCLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[18]); + $setuphold (posedge USERCLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[19]); + $setuphold (posedge USERCLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[20]); + $setuphold (posedge USERCLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[21]); + $setuphold (posedge USERCLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[22]); + $setuphold (posedge USERCLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[23]); + $setuphold (posedge USERCLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[24]); + $setuphold (posedge USERCLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[25]); + $setuphold (posedge USERCLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[26]); + $setuphold (posedge USERCLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[27]); + $setuphold (posedge USERCLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[28]); + $setuphold (posedge USERCLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[29]); + $setuphold (posedge USERCLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[30]); + $setuphold (posedge USERCLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[31]); + $setuphold (posedge USERCLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[32]); + $setuphold (posedge USERCLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[33]); + $setuphold (posedge USERCLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[34]); + $setuphold (posedge USERCLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[35]); + $setuphold (posedge USERCLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[36]); + $setuphold (posedge USERCLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[37]); + $setuphold (posedge USERCLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[38]); + $setuphold (posedge USERCLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[39]); + $setuphold (posedge USERCLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[3]); + $setuphold (posedge USERCLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[40]); + $setuphold (posedge USERCLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[41]); + $setuphold (posedge USERCLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[42]); + $setuphold (posedge USERCLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[43]); + $setuphold (posedge USERCLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[44]); + $setuphold (posedge USERCLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[45]); + $setuphold (posedge USERCLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[46]); + $setuphold (posedge USERCLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[47]); + $setuphold (posedge USERCLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[48]); + $setuphold (posedge USERCLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[49]); + $setuphold (posedge USERCLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[4]); + $setuphold (posedge USERCLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[50]); + $setuphold (posedge USERCLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[51]); + $setuphold (posedge USERCLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[52]); + $setuphold (posedge USERCLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[53]); + $setuphold (posedge USERCLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[54]); + $setuphold (posedge USERCLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[55]); + $setuphold (posedge USERCLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[56]); + $setuphold (posedge USERCLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[57]); + $setuphold (posedge USERCLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[58]); + $setuphold (posedge USERCLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[59]); + $setuphold (posedge USERCLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[5]); + $setuphold (posedge USERCLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[60]); + $setuphold (posedge USERCLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[61]); + $setuphold (posedge USERCLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[62]); + $setuphold (posedge USERCLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[63]); + $setuphold (posedge USERCLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[6]); + $setuphold (posedge USERCLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[7]); + $setuphold (posedge USERCLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[8]); + $setuphold (posedge USERCLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[9]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge USERCLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRCORIN_delay); + $setuphold (posedge USERCLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge USERCLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge USERCLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge USERCLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge USERCLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge USERCLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[10]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[11]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[12]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[13]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[14]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[15]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[16]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[17]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[18]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge USERCLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge USERCLK, negedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTTYPE1CFGREGACCESS_delay); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[0]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[1]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[3]); + $setuphold (posedge USERCLK, negedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONOUTPUTREQUEST_delay); + $setuphold (posedge USERCLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge USERCLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge USERCLK, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[0]); + $setuphold (posedge USERCLK, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[1]); + $setuphold (posedge USERCLK, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[2]); + $setuphold (posedge USERCLK, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[3]); + $setuphold (posedge USERCLK, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[4]); + $setuphold (posedge USERCLK, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[5]); + $setuphold (posedge USERCLK, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[6]); + $setuphold (posedge USERCLK, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[0]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[10]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[11]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[12]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[13]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[14]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[15]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[1]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[2]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[3]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[4]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[5]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[6]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[8]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[9]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATAVALID_delay); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge USERCLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge USERCLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge USERCLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge USERCLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge USERCLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge USERCLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge USERCLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge USERCLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge USERCLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge USERCLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge USERCLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge USERCLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge USERCLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge USERCLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge USERCLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[0]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[1]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[2]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[3]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[4]); + $setuphold (posedge USERCLK, negedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[5]); + $setuphold (posedge USERCLK, negedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge USERCLK, negedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge USERCLK, negedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge USERCLK, negedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge USERCLK, negedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge USERCLK, negedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge USERCLK, negedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge USERCLK, negedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge USERCLK, negedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge USERCLK, negedge CONFREQVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQVALID_delay); + $setuphold (posedge USERCLK, negedge DBGCFGLOCALMGMTREGOVERRIDE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGCFGLOCALMGMTREGOVERRIDE_delay); + $setuphold (posedge USERCLK, negedge DBGDATASEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[0]); + $setuphold (posedge USERCLK, negedge DBGDATASEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[1]); + $setuphold (posedge USERCLK, negedge DBGDATASEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[2]); + $setuphold (posedge USERCLK, negedge DBGDATASEL[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[3]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[0]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[10]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[11]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[12]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[13]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[1]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[2]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[3]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[4]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[5]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[6]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[7]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[8]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[9]); + $setuphold (posedge USERCLK, negedge LL2LMSAXISTXTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTVALID_delay); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[0]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[1]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[2]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[3]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[0]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[1]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[2]); + $setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[3]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge USERCLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge USERCLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge USERCLK, negedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, PCIECQNPREQ_delay); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge USERCLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge USERCLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge USERCLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge USERCLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge USERCLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge USERCLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTVALID_delay); + $setuphold (posedge USERCLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGCONFIGSPACEENABLE_delay); + $setuphold (posedge USERCLK, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[10]); + $setuphold (posedge USERCLK, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[11]); + $setuphold (posedge USERCLK, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[12]); + $setuphold (posedge USERCLK, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[13]); + $setuphold (posedge USERCLK, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[14]); + $setuphold (posedge USERCLK, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[15]); + $setuphold (posedge USERCLK, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[3]); + $setuphold (posedge USERCLK, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[4]); + $setuphold (posedge USERCLK, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[5]); + $setuphold (posedge USERCLK, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[6]); + $setuphold (posedge USERCLK, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[7]); + $setuphold (posedge USERCLK, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[8]); + $setuphold (posedge USERCLK, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[9]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[3]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[4]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[5]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[6]); + $setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[7]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[3]); + $setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[4]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[10]); + $setuphold (posedge USERCLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[11]); + $setuphold (posedge USERCLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[12]); + $setuphold (posedge USERCLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[13]); + $setuphold (posedge USERCLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[14]); + $setuphold (posedge USERCLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[15]); + $setuphold (posedge USERCLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[16]); + $setuphold (posedge USERCLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[17]); + $setuphold (posedge USERCLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[18]); + $setuphold (posedge USERCLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[19]); + $setuphold (posedge USERCLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[20]); + $setuphold (posedge USERCLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[21]); + $setuphold (posedge USERCLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[22]); + $setuphold (posedge USERCLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[23]); + $setuphold (posedge USERCLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[24]); + $setuphold (posedge USERCLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[25]); + $setuphold (posedge USERCLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[26]); + $setuphold (posedge USERCLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[27]); + $setuphold (posedge USERCLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[28]); + $setuphold (posedge USERCLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[29]); + $setuphold (posedge USERCLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[30]); + $setuphold (posedge USERCLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[31]); + $setuphold (posedge USERCLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[32]); + $setuphold (posedge USERCLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[33]); + $setuphold (posedge USERCLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[34]); + $setuphold (posedge USERCLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[35]); + $setuphold (posedge USERCLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[36]); + $setuphold (posedge USERCLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[37]); + $setuphold (posedge USERCLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[38]); + $setuphold (posedge USERCLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[39]); + $setuphold (posedge USERCLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[3]); + $setuphold (posedge USERCLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[40]); + $setuphold (posedge USERCLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[41]); + $setuphold (posedge USERCLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[42]); + $setuphold (posedge USERCLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[43]); + $setuphold (posedge USERCLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[44]); + $setuphold (posedge USERCLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[45]); + $setuphold (posedge USERCLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[46]); + $setuphold (posedge USERCLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[47]); + $setuphold (posedge USERCLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[48]); + $setuphold (posedge USERCLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[49]); + $setuphold (posedge USERCLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[4]); + $setuphold (posedge USERCLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[50]); + $setuphold (posedge USERCLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[51]); + $setuphold (posedge USERCLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[52]); + $setuphold (posedge USERCLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[53]); + $setuphold (posedge USERCLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[54]); + $setuphold (posedge USERCLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[55]); + $setuphold (posedge USERCLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[56]); + $setuphold (posedge USERCLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[57]); + $setuphold (posedge USERCLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[58]); + $setuphold (posedge USERCLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[59]); + $setuphold (posedge USERCLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[5]); + $setuphold (posedge USERCLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[60]); + $setuphold (posedge USERCLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[61]); + $setuphold (posedge USERCLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[62]); + $setuphold (posedge USERCLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[63]); + $setuphold (posedge USERCLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[6]); + $setuphold (posedge USERCLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[7]); + $setuphold (posedge USERCLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[8]); + $setuphold (posedge USERCLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[9]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[3]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[4]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[5]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[6]); + $setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[7]); + $setuphold (posedge USERCLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRCORIN_delay); + $setuphold (posedge USERCLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRUNCORIN_delay); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATAVALID_delay); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[0]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[1]); + $setuphold (posedge USERCLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[2]); + $setuphold (posedge USERCLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[0]); + $setuphold (posedge USERCLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[1]); + $setuphold (posedge USERCLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGHOTRESETIN_delay); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHPRESENT_delay); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXINT_delay); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[0]); + $setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[1]); + $setuphold (posedge USERCLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGLINKTRAININGENABLE_delay); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[10]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[11]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[12]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[13]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[14]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[15]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[16]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[17]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[18]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[4]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[5]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[6]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[7]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[8]); + $setuphold (posedge USERCLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[9]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTREAD_delay); + $setuphold (posedge USERCLK, posedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTTYPE1CFGREGACCESS_delay); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITE_delay); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMIT_delay); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[0]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[1]); + $setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[0]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[1]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[0]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[1]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[2]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[3]); + $setuphold (posedge USERCLK, posedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONOUTPUTREQUEST_delay); + $setuphold (posedge USERCLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPOWERSTATECHANGEACK_delay); + $setuphold (posedge USERCLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREQPMTRANSITIONL23READY_delay); + $setuphold (posedge USERCLK, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[0]); + $setuphold (posedge USERCLK, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[1]); + $setuphold (posedge USERCLK, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[2]); + $setuphold (posedge USERCLK, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[3]); + $setuphold (posedge USERCLK, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[4]); + $setuphold (posedge USERCLK, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[5]); + $setuphold (posedge USERCLK, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[6]); + $setuphold (posedge USERCLK, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[0]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[10]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[11]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[12]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[13]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[14]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[15]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[1]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[2]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[3]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[4]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[5]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[6]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[8]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[9]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[0]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[10]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[11]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[12]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[13]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[14]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[15]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[1]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[2]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[3]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[4]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[5]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[6]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[7]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[8]); + $setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[9]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATAVALID_delay); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[0]); + $setuphold (posedge USERCLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[10]); + $setuphold (posedge USERCLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[11]); + $setuphold (posedge USERCLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[12]); + $setuphold (posedge USERCLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[13]); + $setuphold (posedge USERCLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[14]); + $setuphold (posedge USERCLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[15]); + $setuphold (posedge USERCLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[1]); + $setuphold (posedge USERCLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[2]); + $setuphold (posedge USERCLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[3]); + $setuphold (posedge USERCLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[4]); + $setuphold (posedge USERCLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[5]); + $setuphold (posedge USERCLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[6]); + $setuphold (posedge USERCLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[7]); + $setuphold (posedge USERCLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[8]); + $setuphold (posedge USERCLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[9]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[0]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[1]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[2]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[3]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[4]); + $setuphold (posedge USERCLK, posedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[5]); + $setuphold (posedge USERCLK, posedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFMCAPREQUESTBYCONF_delay); + $setuphold (posedge USERCLK, posedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[0]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[10]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[11]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[12]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[13]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[14]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[15]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[16]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[17]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[18]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[19]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[1]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[20]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[21]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[22]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[23]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[24]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[25]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[26]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[27]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[28]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[29]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[2]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[30]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[31]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[3]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[4]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[5]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[6]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[7]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[8]); + $setuphold (posedge USERCLK, posedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[9]); + $setuphold (posedge USERCLK, posedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[0]); + $setuphold (posedge USERCLK, posedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[1]); + $setuphold (posedge USERCLK, posedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[2]); + $setuphold (posedge USERCLK, posedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[3]); + $setuphold (posedge USERCLK, posedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[0]); + $setuphold (posedge USERCLK, posedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[1]); + $setuphold (posedge USERCLK, posedge CONFREQVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQVALID_delay); + $setuphold (posedge USERCLK, posedge DBGCFGLOCALMGMTREGOVERRIDE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGCFGLOCALMGMTREGOVERRIDE_delay); + $setuphold (posedge USERCLK, posedge DBGDATASEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[0]); + $setuphold (posedge USERCLK, posedge DBGDATASEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[1]); + $setuphold (posedge USERCLK, posedge DBGDATASEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[2]); + $setuphold (posedge USERCLK, posedge DBGDATASEL[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[3]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[0]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[10]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[11]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[12]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[13]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[1]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[2]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[3]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[4]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[5]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[6]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[7]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[8]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[9]); + $setuphold (posedge USERCLK, posedge LL2LMSAXISTXTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTVALID_delay); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[0]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[1]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[2]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[3]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[0]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[1]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[2]); + $setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[3]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[0]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[10]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[11]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[12]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[13]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[14]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[15]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[16]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[17]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[18]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[19]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[1]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[20]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[21]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[2]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[3]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[4]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[5]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[6]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[7]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[8]); + $setuphold (posedge USERCLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[9]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[0]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[10]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[11]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[12]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[13]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[14]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[15]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[16]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[17]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[18]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[19]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[1]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[20]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[21]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[2]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[3]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[4]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[5]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[6]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[7]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[8]); + $setuphold (posedge USERCLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[9]); + $setuphold (posedge USERCLK, posedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, PCIECQNPREQ_delay); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[100]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[101]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[102]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[103]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[104]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[105]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[106]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[107]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[108]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[109]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[10]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[110]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[111]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[112]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[113]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[114]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[115]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[116]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[117]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[118]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[119]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[11]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[120]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[121]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[122]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[123]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[124]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[125]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[126]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[127]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[128]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[129]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[12]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[130]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[131]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[132]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[133]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[134]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[135]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[136]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[137]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[138]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[139]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[13]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[140]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[141]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[142]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[143]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[144]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[145]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[146]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[147]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[148]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[149]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[14]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[150]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[151]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[152]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[153]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[154]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[155]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[156]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[157]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[158]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[159]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[15]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[160]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[161]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[162]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[163]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[164]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[165]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[166]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[167]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[168]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[169]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[16]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[170]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[171]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[172]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[173]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[174]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[175]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[176]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[177]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[178]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[179]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[17]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[180]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[181]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[182]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[183]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[184]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[185]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[186]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[187]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[188]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[189]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[18]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[190]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[191]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[192]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[193]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[194]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[195]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[196]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[197]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[198]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[199]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[19]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[200]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[201]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[202]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[203]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[204]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[205]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[206]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[207]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[208]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[209]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[20]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[210]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[211]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[212]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[213]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[214]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[215]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[216]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[217]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[218]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[219]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[21]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[220]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[221]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[222]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[223]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[224]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[225]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[226]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[227]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[228]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[229]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[22]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[230]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[231]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[232]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[233]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[234]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[235]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[236]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[237]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[238]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[239]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[23]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[240]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[241]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[242]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[243]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[244]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[245]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[246]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[247]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[248]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[249]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[24]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[250]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[251]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[252]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[253]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[254]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[255]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[25]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[26]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[27]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[28]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[29]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[30]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[31]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[32]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[33]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[34]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[35]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[36]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[37]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[38]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[39]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[40]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[41]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[42]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[43]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[44]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[45]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[46]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[47]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[48]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[49]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[50]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[51]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[52]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[53]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[54]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[55]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[56]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[57]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[58]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[59]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[60]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[61]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[62]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[63]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[64]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[65]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[66]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[67]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[68]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[69]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[70]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[71]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[72]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[73]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[74]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[75]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[76]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[77]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[78]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[79]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[80]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[81]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[82]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[83]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[84]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[85]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[86]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[87]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[88]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[89]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[8]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[90]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[91]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[92]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[93]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[94]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[95]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[96]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[97]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[98]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[99]); + $setuphold (posedge USERCLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[9]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTLAST_delay); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[10]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[11]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[12]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[13]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[14]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[15]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[16]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[17]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[18]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[19]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[20]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[21]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[22]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[23]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[24]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[25]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[26]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[27]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[28]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[29]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[30]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[31]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[32]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[8]); + $setuphold (posedge USERCLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[9]); + $setuphold (posedge USERCLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTVALID_delay); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[100]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[101]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[102]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[103]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[104]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[105]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[106]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[107]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[108]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[109]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[10]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[110]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[111]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[112]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[113]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[114]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[115]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[116]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[117]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[118]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[119]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[11]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[120]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[121]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[122]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[123]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[124]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[125]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[126]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[127]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[128]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[129]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[12]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[130]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[131]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[132]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[133]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[134]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[135]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[136]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[137]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[138]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[139]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[13]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[140]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[141]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[142]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[143]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[144]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[145]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[146]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[147]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[148]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[149]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[14]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[150]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[151]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[152]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[153]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[154]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[155]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[156]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[157]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[158]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[159]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[15]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[160]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[161]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[162]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[163]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[164]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[165]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[166]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[167]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[168]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[169]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[16]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[170]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[171]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[172]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[173]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[174]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[175]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[176]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[177]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[178]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[179]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[17]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[180]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[181]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[182]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[183]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[184]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[185]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[186]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[187]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[188]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[189]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[18]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[190]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[191]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[192]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[193]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[194]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[195]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[196]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[197]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[198]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[199]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[19]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[200]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[201]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[202]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[203]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[204]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[205]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[206]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[207]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[208]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[209]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[20]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[210]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[211]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[212]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[213]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[214]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[215]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[216]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[217]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[218]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[219]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[21]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[220]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[221]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[222]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[223]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[224]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[225]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[226]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[227]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[228]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[229]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[22]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[230]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[231]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[232]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[233]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[234]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[235]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[236]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[237]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[238]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[239]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[23]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[240]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[241]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[242]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[243]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[244]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[245]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[246]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[247]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[248]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[249]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[24]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[250]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[251]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[252]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[253]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[254]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[255]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[25]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[26]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[27]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[28]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[29]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[30]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[31]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[32]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[33]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[34]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[35]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[36]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[37]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[38]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[39]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[40]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[41]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[42]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[43]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[44]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[45]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[46]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[47]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[48]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[49]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[50]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[51]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[52]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[53]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[54]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[55]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[56]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[57]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[58]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[59]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[60]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[61]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[62]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[63]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[64]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[65]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[66]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[67]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[68]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[69]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[70]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[71]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[72]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[73]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[74]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[75]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[76]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[77]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[78]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[79]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[80]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[81]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[82]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[83]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[84]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[85]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[86]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[87]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[88]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[89]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[8]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[90]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[91]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[92]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[93]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[94]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[95]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[96]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[97]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[98]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[99]); + $setuphold (posedge USERCLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[9]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTLAST_delay); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[0]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[10]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[11]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[12]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[13]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[14]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[15]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[16]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[17]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[18]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[19]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[1]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[20]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[21]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[22]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[23]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[24]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[25]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[26]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[27]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[28]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[29]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[2]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[30]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[31]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[32]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[33]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[34]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[35]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[36]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[37]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[38]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[39]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[3]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[40]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[41]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[42]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[43]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[44]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[45]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[46]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[47]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[48]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[49]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[4]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[50]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[51]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[52]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[53]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[54]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[55]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[56]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[57]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[58]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[59]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[5]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[6]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[7]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[8]); + $setuphold (posedge USERCLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[9]); + $setuphold (posedge USERCLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTVALID_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PHASER_IN.v b/verilog/src/unisims/PHASER_IN.v new file mode 100644 index 0000000..9e73333 --- /dev/null +++ b/verilog/src/unisims/PHASER_IN.v @@ -0,0 +1,538 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 7SERIES PHASER IN +// /__/ /\ Filename : PHASER_IN.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Comment: +// 22APR2010 Initial UNI/UNP/SIM version from yaml +// 03JUN2010 yaml update +// 12JUL2010 enable secureip +// 12AUG2010 yaml, rtl update +// 24SEP2010 yaml, rtl update +// 29SEP2010 add width checks +// 13OCT2010 yaml, rtl update +// 26OCT2010 delay yaml, rtl update +// 02NOV2010 yaml update +// 05NOV2010 secureip parameter name update +// 01DEC2010 yaml update, REFCLK_PERIOD max +// 09DEC2010 586079 yaml update, tie off defaults +// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 02FEB2011 592485 yaml, rtl update +// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN +// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter +// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed +// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default +// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert +// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart +// 22MAY2012 660507 DQS_AUTO_RECAL default value change +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHASER_IN #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer CLKOUT_DIV = 4, + parameter DQS_BIAS_MODE = "FALSE", + parameter EN_ISERDES_RST = "FALSE", + parameter integer FINE_DELAY = 0, + parameter FREQ_REF_DIV = "NONE", + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real MEMREFCLK_PERIOD = 0.000, + parameter OUTPUT_CLK_SRC = "PHASE_REF", + parameter real PHASEREFCLK_PERIOD = 0.000, + parameter real REFCLK_PERIOD = 0.000, + parameter integer SEL_CLK_OFFSET = 5, + parameter SYNC_IN_DIV_RST = "FALSE" +) ( + output [5:0] COUNTERREADVAL, + output FINEOVERFLOW, + output ICLK, + output ICLKDIV, + output ISERDESRST, + output RCLK, + + input COUNTERLOADEN, + input [5:0] COUNTERLOADVAL, + input COUNTERREADEN, + input DIVIDERST, + input EDGEADV, + input FINEENABLE, + input FINEINC, + input FREQREFCLK, + input MEMREFCLK, + input PHASEREFCLK, + input [1:0] RANKSEL, + input RST, + input SYNCIN, + input SYSCLK +); + +`ifdef XIL_TIMING + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; +`else + + localparam in_delay = 1; + localparam out_delay = 1; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 1; +`endif + localparam MODULE_NAME = "PHASER_IN"; + + reg MEMREFCLK_PERIOD_BINARY; + reg PHASEREFCLK_PERIOD_BINARY; + reg REFCLK_PERIOD_BINARY; + reg [0:0] BURST_MODE_BINARY; + reg [0:0] CALIB_EDGE_IN_INV_BINARY; + reg [0:0] CTL_MODE_BINARY; + reg [0:0] DQS_AUTO_RECAL_BINARY; + reg [0:0] DQS_BIAS_MODE_BINARY; + reg [0:0] EN_ISERDES_RST_BINARY; + reg [0:0] EN_TEST_RING_BINARY; + reg [0:0] GATE_SET_CLK_MUX_BINARY; + reg [0:0] HALF_CYCLE_ADJ_BINARY; + reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY; + reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + reg [0:0] PHASER_IN_EN_BINARY; + reg [0:0] REG_OPT_1_BINARY; + reg [0:0] REG_OPT_2_BINARY; + reg [0:0] REG_OPT_4_BINARY; + reg [0:0] RST_SEL_BINARY; + reg [0:0] SEL_OUT_BINARY; + reg [0:0] SYNC_IN_DIV_RST_BINARY; + reg [0:0] TEST_BP_BINARY; + reg [0:0] UPDATE_NONACTIVE_BINARY; + reg [0:0] WR_CYCLES_BINARY; + reg [1:0] FREQ_REF_DIV_BINARY; + reg [1:0] RD_ADDR_INIT_BINARY; + reg [2:0] DQS_FIND_PATTERN_BINARY; + reg [2:0] PD_REVERSE_BINARY; + reg [2:0] SEL_CLK_OFFSET_BINARY; + reg [2:0] STG1_PD_UPDATE_BINARY; + reg [3:0] CLKOUT_DIV_BINARY; + reg [3:0] CLKOUT_DIV_POS_BINARY; + reg [3:0] CLKOUT_DIV_ST_BINARY; + reg [3:0] OUTPUT_CLK_SRC_BINARY; + reg [5:0] FINE_DELAY_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + BURST_MODE_BINARY <= 1'b0; + + case (CLKOUT_DIV) + 4 : CLKOUT_DIV_BINARY <= 4'b0010; + 2 : CLKOUT_DIV_BINARY <= 4'b0000; + 3 : CLKOUT_DIV_BINARY <= 4'b0001; + 5 : CLKOUT_DIV_BINARY <= 4'b0011; + 6 : CLKOUT_DIV_BINARY <= 4'b0100; + 7 : CLKOUT_DIV_BINARY <= 4'b0101; + 8 : CLKOUT_DIV_BINARY <= 4'b0110; + 9 : CLKOUT_DIV_BINARY <= 4'b0111; + 10 : CLKOUT_DIV_BINARY <= 4'b1000; + 11 : CLKOUT_DIV_BINARY <= 4'b1001; + 12 : CLKOUT_DIV_BINARY <= 4'b1010; + 13 : CLKOUT_DIV_BINARY <= 4'b1011; + 14 : CLKOUT_DIV_BINARY <= 4'b1100; + 15 : CLKOUT_DIV_BINARY <= 4'b1101; + 16 : CLKOUT_DIV_BINARY <= 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV); + #1 $finish; + end + endcase + + CTL_MODE_BINARY <= 1'b0; // model alert + + case (DQS_BIAS_MODE) + "FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0; + "TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE); + #1 $finish; + end + endcase + + case (EN_ISERDES_RST) + "FALSE" : EN_ISERDES_RST_BINARY <= 1'b0; + "TRUE" : EN_ISERDES_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EN_ISERDES_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ISERDES_RST); + #1 $finish; + end + endcase + + EN_TEST_RING_BINARY <= 1'b0; + + case (FREQ_REF_DIV) + "NONE" : FREQ_REF_DIV_BINARY <= 2'b00; + "DIV2" : FREQ_REF_DIV_BINARY <= 2'b01; + default : begin + $display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV); + #1 $finish; + end + endcase + + HALF_CYCLE_ADJ_BINARY <= 1'b0; + + ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1; + + case (OUTPUT_CLK_SRC) + "PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000; + "DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101; + "DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011; + "DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001; + "FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000; + "MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010; + default : begin + $display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC); + #1 $finish; + end + endcase + + PD_REVERSE_BINARY <= 3'b011; + + PHASER_IN_EN_BINARY <= 1'b1; + + STG1_PD_UPDATE_BINARY <= 3'b000; + + case (SYNC_IN_DIV_RST) + "FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0; + "TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST); + #1 $finish; + end + endcase + + UPDATE_NONACTIVE_BINARY <= 1'b0; + + WR_CYCLES_BINARY <= 1'b0; + + CALIB_EDGE_IN_INV_BINARY <= 1'b0; + + case (CLKOUT_DIV) + 2 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 3 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 4 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 5 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 6 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 7 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 8 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 9 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 10 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 11 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 12 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 13 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 14 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 15 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 16 : CLKOUT_DIV_POS_BINARY <= 4'b1000; + default: CLKOUT_DIV_POS_BINARY <= 4'b0010; + endcase + + CLKOUT_DIV_ST_BINARY <= 4'b0000; + + DQS_AUTO_RECAL_BINARY <= 1'b1; + + DQS_FIND_PATTERN_BINARY <= 3'b001; + + if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63)) + FINE_DELAY_BINARY <= FINE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY); + #1 $finish; + end + + GATE_SET_CLK_MUX_BINARY <= 1'b0; + + if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000)) + MEMREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD); + #1 $finish; + end + + if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000)) + PHASEREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD); + #1 $finish; + end + + RD_ADDR_INIT_BINARY <= 2'b00; + + + if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500)) + REFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD); + #1 $finish; + end + + REG_OPT_1_BINARY <= 1'b0; + + REG_OPT_2_BINARY <= 1'b0; + + REG_OPT_4_BINARY <= 1'b0; + + RST_SEL_BINARY <= 1'b0; + + if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7)) + SEL_CLK_OFFSET_BINARY <= 0; // Model Alert + else begin + $display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET); + #1 $finish; + end + + SEL_OUT_BINARY <= 1'b0; + + TEST_BP_BINARY <= 1'b0; + + end + + wire [3:0] delay_TESTOUT; + wire [5:0] delay_COUNTERREADVAL; + wire [8:0] delay_STG1REGR; + wire delay_DQSFOUND; + wire delay_DQSOUTOFRANGE; + wire delay_FINEOVERFLOW; + wire delay_ICLK; + wire delay_ICLKDIV; + wire delay_ISERDESRST; + wire delay_PHASELOCKED; + wire delay_RCLK; + wire delay_SCANOUT; + wire delay_STG1OVERFLOW; + wire delay_WRENABLE; + + wire [13:0] delay_TESTIN = 14'h3fff; + wire [1:0] delay_ENCALIB = 2'b11; + wire [1:0] delay_ENCALIBPHY = 2'b0; + wire [1:0] delay_RANKSEL; + wire [1:0] delay_RANKSELPHY = 2'b0; + wire [5:0] delay_COUNTERLOADVAL; + wire [8:0] delay_STG1REGL = 9'h1ff; + wire delay_BURSTPENDING = 1'b1; + wire delay_BURSTPENDINGPHY = 1'b0; + wire delay_COUNTERLOADEN; + wire delay_COUNTERREADEN; + wire delay_DIVIDERST; + wire delay_EDGEADV; + wire delay_ENSTG1 = 1'b1; + wire delay_ENSTG1ADJUSTB = 1'b1; + wire delay_FINEENABLE; + wire delay_FINEINC; + wire delay_FREQREFCLK; + wire delay_MEMREFCLK; + wire delay_PHASEREFCLK; + wire delay_RST; + wire delay_RSTDQSFIND = 1'b1; + wire delay_SCANCLK = 1'b1; + wire delay_SCANENB = 1'b1; + wire delay_SCANIN = 1'b1; + wire delay_SCANMODEB = 1'b1; + wire delay_SELCALORSTG1 = 1'b1; + wire delay_STG1INCDEC = 1'b1; + wire delay_STG1LOAD = 1'b1; + wire delay_STG1READ = 1'b1; + wire delay_SYNCIN; + wire delay_SYSCLK; + wire delay_GSR; + + assign #(OUTCLK_DELAY) ICLK = delay_ICLK; + assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV; + assign #(OUTCLK_DELAY) RCLK = delay_RCLK; + + assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL; + assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW; + assign #(out_delay) ISERDESRST = delay_ISERDESRST; + +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK; + + assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN; + assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL; + assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN; + assign #(in_delay) delay_DIVIDERST = DIVIDERST; + assign #(in_delay) delay_EDGEADV = EDGEADV; + assign #(in_delay) delay_FINEENABLE = FINEENABLE; + assign #(in_delay) delay_FINEINC = FINEINC; +`endif + assign #(in_delay) delay_FREQREFCLK = FREQREFCLK; + assign #(in_delay) delay_MEMREFCLK = MEMREFCLK; + assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK; +`ifndef XIL_TIMING + assign #(in_delay) delay_RANKSEL = RANKSEL; +`endif + assign #(in_delay) delay_RST = RST; + assign #(in_delay) delay_SYNCIN = SYNCIN; + assign delay_GSR = GSR; + + SIP_PHASER_IN # ( + .REFCLK_PERIOD (REFCLK_PERIOD) + ) PHASER_IN_INST ( + .BURST_MODE (BURST_MODE_BINARY), + .CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY), + .CLKOUT_DIV (CLKOUT_DIV_BINARY), + .CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY), + .CTL_MODE (CTL_MODE_BINARY), + .DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY), + .DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY), + .DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY), + .EN_ISERDES_RST (EN_ISERDES_RST_BINARY), + .EN_TEST_RING (EN_TEST_RING_BINARY), + .FINE_DELAY (FINE_DELAY_BINARY), + .FREQ_REF_DIV (FREQ_REF_DIV_BINARY), + .GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY), + .HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY), + .ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY), + .OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY), + .PD_REVERSE (PD_REVERSE_BINARY), + .PHASER_IN_EN (PHASER_IN_EN_BINARY), + .RD_ADDR_INIT (RD_ADDR_INIT_BINARY), + .REG_OPT_1 (REG_OPT_1_BINARY), + .REG_OPT_2 (REG_OPT_2_BINARY), + .REG_OPT_4 (REG_OPT_4_BINARY), + .RST_SEL (RST_SEL_BINARY), + .SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY), + .SEL_OUT (SEL_OUT_BINARY), + .STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY), + .SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY), + .TEST_BP (TEST_BP_BINARY), + .UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY), + .WR_CYCLES (WR_CYCLES_BINARY), + .CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY), + + .COUNTERREADVAL (delay_COUNTERREADVAL), + .DQSFOUND (delay_DQSFOUND), + .DQSOUTOFRANGE (delay_DQSOUTOFRANGE), + .FINEOVERFLOW (delay_FINEOVERFLOW), + .ICLK (delay_ICLK), + .ICLKDIV (delay_ICLKDIV), + .ISERDESRST (delay_ISERDESRST), + .PHASELOCKED (delay_PHASELOCKED), + .RCLK (delay_RCLK), + .SCANOUT (delay_SCANOUT), + .STG1OVERFLOW (delay_STG1OVERFLOW), + .STG1REGR (delay_STG1REGR), + .TESTOUT (delay_TESTOUT), + .WRENABLE (delay_WRENABLE), + .BURSTPENDING (delay_BURSTPENDING), + .BURSTPENDINGPHY (delay_BURSTPENDINGPHY), + .COUNTERLOADEN (delay_COUNTERLOADEN), + .COUNTERLOADVAL (delay_COUNTERLOADVAL), + .COUNTERREADEN (delay_COUNTERREADEN), + .DIVIDERST (delay_DIVIDERST), + .EDGEADV (delay_EDGEADV), + .ENCALIB (delay_ENCALIB), + .ENCALIBPHY (delay_ENCALIBPHY), + .ENSTG1 (delay_ENSTG1), + .ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB), + .FINEENABLE (delay_FINEENABLE), + .FINEINC (delay_FINEINC), + .FREQREFCLK (delay_FREQREFCLK), + .MEMREFCLK (delay_MEMREFCLK), + .PHASEREFCLK (delay_PHASEREFCLK), + .RANKSEL (delay_RANKSEL), + .RANKSELPHY (delay_RANKSELPHY), + .RST (delay_RST ^ IS_RST_INVERTED_REG), + .RSTDQSFIND (delay_RSTDQSFIND), + .SCANCLK (delay_SCANCLK), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .SCANMODEB (delay_SCANMODEB), + .SELCALORSTG1 (delay_SELCALORSTG1), + .STG1INCDEC (delay_STG1INCDEC), + .STG1LOAD (delay_STG1LOAD), + .STG1READ (delay_STG1READ), + .STG1REGL (delay_STG1REGL), + .SYNCIN (delay_SYNCIN), + .SYSCLK (delay_SYSCLK), + .TESTIN (delay_TESTIN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (posedge SYSCLK, 0:0:0, notifier); + $setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, negedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST); + $setuphold (posedge SYSCLK, negedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV); + $setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, negedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL); + $setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, posedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST); + $setuphold (posedge SYSCLK, posedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV); + $setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, posedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL); + $width (negedge FREQREFCLK, 0:0:0, 0, notifier); + $width (negedge MEMREFCLK, 0:0:0, 0, notifier); + $width (negedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (negedge SYNCIN, 0:0:0, 0, notifier); + $width (negedge SYSCLK, 0:0:0, 0, notifier); + $width (posedge FREQREFCLK, 0:0:0, 0, notifier); + $width (posedge MEMREFCLK, 0:0:0, 0, notifier); + $width (posedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (posedge SYNCIN, 0:0:0, 0, notifier); + $width (posedge SYSCLK, 0:0:0, 0, notifier); + ( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10); + ( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHASER_IN + +`endcelldefine diff --git a/verilog/src/unisims/PHASER_IN_PHY.v b/verilog/src/unisims/PHASER_IN_PHY.v new file mode 100644 index 0000000..a863864 --- /dev/null +++ b/verilog/src/unisims/PHASER_IN_PHY.v @@ -0,0 +1,577 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 7SERIES PHASER IN +// /__/ /\ Filename : PHASER_IN_PHY.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Comment: +// 22APR2010 Initial UNI/UNP/SIM version from yaml +// 03JUN2010 yaml update +// 12JUL2010 enable secureip +// 12AUG2010 yaml, rtl update +// 24SEP2010 yaml, rtl update +// 29SEP2010 add width checks +// 13OCT2010 yaml, rtl update +// 26OCT2010 delay yaml, rtl update +// 02NOV2010 yaml update +// 05NOV2010 secureip parameter name update +// 11NOV2010 582473 multiple drivers on delay_MEMREFCLK +// 01DEC2010 yaml update, REFCLK_PERIOD max +// 09DEC2010 586079 yaml update, tie off defaults +// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 02FEB2011 592485 yaml, rtl update +// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN +// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter +// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed +// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default +// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert +// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart +// 22MAY2012 660507 DQS_AUTO_RECAL default value change +// 13JUN2012 664620 Change dly ref clk for DQSFOUND +// 10JUL2012 669266 Make DQS_AUTO_RECAL and DQS_FIND_PATTERN visible +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHASER_IN_PHY #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter BURST_MODE = "FALSE", + parameter integer CLKOUT_DIV = 4, + parameter [0:0] DQS_AUTO_RECAL = 1'b1, + parameter DQS_BIAS_MODE = "FALSE", + parameter [2:0] DQS_FIND_PATTERN = 3'b001, + parameter integer FINE_DELAY = 0, + parameter FREQ_REF_DIV = "NONE", + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real MEMREFCLK_PERIOD = 0.000, + parameter OUTPUT_CLK_SRC = "PHASE_REF", + parameter real PHASEREFCLK_PERIOD = 0.000, + parameter real REFCLK_PERIOD = 0.000, + parameter integer SEL_CLK_OFFSET = 5, + parameter SYNC_IN_DIV_RST = "FALSE", + parameter WR_CYCLES = "FALSE" +) ( + output [5:0] COUNTERREADVAL, + output DQSFOUND, + output DQSOUTOFRANGE, + output FINEOVERFLOW, + output ICLK, + output ICLKDIV, + output ISERDESRST, + output PHASELOCKED, + output RCLK, + output WRENABLE, + + input BURSTPENDINGPHY, + input COUNTERLOADEN, + input [5:0] COUNTERLOADVAL, + input COUNTERREADEN, + input [1:0] ENCALIBPHY, + input FINEENABLE, + input FINEINC, + input FREQREFCLK, + input MEMREFCLK, + input PHASEREFCLK, + input [1:0] RANKSELPHY, + input RST, + input RSTDQSFIND, + input SYNCIN, + input SYSCLK +); + +`ifdef XIL_TIMING + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; +`else + + localparam in_delay = 1; + localparam out_delay = 1; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 1; +`endif + localparam MODULE_NAME = "PHASER_IN_PHY"; + + reg MEMREFCLK_PERIOD_BINARY; + reg PHASEREFCLK_PERIOD_BINARY; + reg REFCLK_PERIOD_BINARY; + reg [0:0] BURST_MODE_BINARY; + reg [0:0] CALIB_EDGE_IN_INV_BINARY; + reg [0:0] CTL_MODE_BINARY; + reg [0:0] DQS_AUTO_RECAL_BINARY; + reg [0:0] DQS_BIAS_MODE_BINARY; + reg [0:0] EN_ISERDES_RST_BINARY; + reg [0:0] EN_TEST_RING_BINARY; + reg [0:0] GATE_SET_CLK_MUX_BINARY; + reg [0:0] HALF_CYCLE_ADJ_BINARY; + reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY; + reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + reg [0:0] PHASER_IN_EN_BINARY; + reg [0:0] REG_OPT_1_BINARY; + reg [0:0] REG_OPT_2_BINARY; + reg [0:0] REG_OPT_4_BINARY; + reg [0:0] RST_SEL_BINARY; + reg [0:0] SEL_OUT_BINARY; + reg [0:0] SYNC_IN_DIV_RST_BINARY; + reg [0:0] TEST_BP_BINARY; + reg [0:0] UPDATE_NONACTIVE_BINARY; + reg [0:0] WR_CYCLES_BINARY; + reg [1:0] FREQ_REF_DIV_BINARY; + reg [1:0] RD_ADDR_INIT_BINARY; + reg [2:0] DQS_FIND_PATTERN_BINARY; + reg [2:0] PD_REVERSE_BINARY; + reg [2:0] SEL_CLK_OFFSET_BINARY; + reg [2:0] STG1_PD_UPDATE_BINARY; + reg [3:0] CLKOUT_DIV_BINARY; + reg [3:0] CLKOUT_DIV_POS_BINARY; + reg [3:0] CLKOUT_DIV_ST_BINARY; + reg [3:0] OUTPUT_CLK_SRC_BINARY; + reg [5:0] FINE_DELAY_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (BURST_MODE) + "FALSE" : BURST_MODE_BINARY <= 1'b0; + "TRUE" : BURST_MODE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BURST_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BURST_MODE); + #1 $finish; + end + endcase + + case (CLKOUT_DIV) + 4 : CLKOUT_DIV_BINARY <= 4'b0010; + 2 : CLKOUT_DIV_BINARY <= 4'b0000; + 3 : CLKOUT_DIV_BINARY <= 4'b0001; + 5 : CLKOUT_DIV_BINARY <= 4'b0011; + 6 : CLKOUT_DIV_BINARY <= 4'b0100; + 7 : CLKOUT_DIV_BINARY <= 4'b0101; + 8 : CLKOUT_DIV_BINARY <= 4'b0110; + 9 : CLKOUT_DIV_BINARY <= 4'b0111; + 10 : CLKOUT_DIV_BINARY <= 4'b1000; + 11 : CLKOUT_DIV_BINARY <= 4'b1001; + 12 : CLKOUT_DIV_BINARY <= 4'b1010; + 13 : CLKOUT_DIV_BINARY <= 4'b1011; + 14 : CLKOUT_DIV_BINARY <= 4'b1100; + 15 : CLKOUT_DIV_BINARY <= 4'b1101; + 16 : CLKOUT_DIV_BINARY <= 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV); + #1 $finish; + end + endcase + + CTL_MODE_BINARY <= 1'b1; // model alert + + case (DQS_BIAS_MODE) + "FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0; + "TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE); + #1 $finish; + end + endcase + + EN_ISERDES_RST_BINARY <= 1'b0; + + EN_TEST_RING_BINARY <= 1'b0; + + case (FREQ_REF_DIV) + "NONE" : FREQ_REF_DIV_BINARY <= 2'b00; + "DIV2" : FREQ_REF_DIV_BINARY <= 2'b01; + default : begin + $display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV); + #1 $finish; + end + endcase + + HALF_CYCLE_ADJ_BINARY <= 1'b0; + + ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1; + + case (OUTPUT_CLK_SRC) + "PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000; + "DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101; + "DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011; + "DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001; + "FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000; + "MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010; + default : begin + $display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC); + #1 $finish; + end + endcase + + PD_REVERSE_BINARY <= 3'b011; + + PHASER_IN_EN_BINARY <= 1'b1; + + STG1_PD_UPDATE_BINARY <= 3'b000; + + case (SYNC_IN_DIV_RST) + "FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0; + "TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST); + #1 $finish; + end + endcase + + UPDATE_NONACTIVE_BINARY <= 1'b0; + + case (WR_CYCLES) + "FALSE" : WR_CYCLES_BINARY <= 1'b0; + "TRUE" : WR_CYCLES_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute WR_CYCLES on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, WR_CYCLES); + #1 $finish; + end + endcase + + CALIB_EDGE_IN_INV_BINARY <= 1'b0; + + case (CLKOUT_DIV) + 2 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 3 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 4 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 5 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 6 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 7 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 8 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 9 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 10 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 11 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 12 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 13 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 14 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 15 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 16 : CLKOUT_DIV_POS_BINARY <= 4'b1000; + default: CLKOUT_DIV_POS_BINARY <= 4'b0010; + endcase + + CLKOUT_DIV_ST_BINARY <= 4'b0000; + + if ((DQS_AUTO_RECAL >= 1'b0) && (DQS_AUTO_RECAL <= 1'b1)) + DQS_AUTO_RECAL_BINARY <= DQS_AUTO_RECAL; + else begin + $display("Attribute Syntax Error : The Attribute DQS_AUTO_RECAL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DQS_AUTO_RECAL); + #1 $finish; + end + + if ((DQS_FIND_PATTERN >= 3'b000) && (DQS_FIND_PATTERN <= 3'b111)) + DQS_FIND_PATTERN_BINARY <= DQS_FIND_PATTERN; + else begin + $display("Attribute Syntax Error : The Attribute DQS_FIND_PATTERN on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, DQS_FIND_PATTERN); + #1 $finish; + end + + if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63)) + FINE_DELAY_BINARY <= FINE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY); + #1 $finish; + end + + GATE_SET_CLK_MUX_BINARY <= 1'b0; + + if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000)) + MEMREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD); + #1 $finish; + end + + if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000)) + PHASEREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD); + #1 $finish; + end + + RD_ADDR_INIT_BINARY <= 2'b00; + + + if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500)) + REFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD); + #1 $finish; + end + + REG_OPT_1_BINARY <= 1'b0; + + REG_OPT_2_BINARY <= 1'b0; + + REG_OPT_4_BINARY <= 1'b0; + + RST_SEL_BINARY <= 1'b0; + + if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7)) + SEL_CLK_OFFSET_BINARY <= 0; // Model Alert + else begin + $display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET); + #1 $finish; + end + + SEL_OUT_BINARY <= 1'b0; + + TEST_BP_BINARY <= 1'b0; + + end + + wire [3:0] delay_TESTOUT; + wire [5:0] delay_COUNTERREADVAL; + wire [8:0] delay_STG1REGR; + wire delay_DQSFOUND; + wire delay_DQSOUTOFRANGE; + wire delay_FINEOVERFLOW; + wire delay_ICLK; + wire delay_ICLKDIV; + wire delay_ISERDESRST; + wire delay_PHASELOCKED; + wire delay_RCLK; + wire delay_SCANOUT; + wire delay_STG1OVERFLOW; + wire delay_WRENABLE; + + wire [13:0] delay_TESTIN = 14'h3fff; + wire [1:0] delay_ENCALIB = 2'b11; + wire [1:0] delay_ENCALIBPHY; + wire [1:0] delay_RANKSEL = 2'b0; + wire [1:0] delay_RANKSELPHY; + wire [5:0] delay_COUNTERLOADVAL; + wire [8:0] delay_STG1REGL = 9'h1ff; + wire delay_BURSTPENDING = 1'b1; + wire delay_BURSTPENDINGPHY; + wire delay_COUNTERLOADEN; + wire delay_COUNTERREADEN; + wire delay_DIVIDERST = 1'b0; + wire delay_EDGEADV = 1'b0; + wire delay_ENSTG1 = 1'b1; + wire delay_ENSTG1ADJUSTB = 1'b1; + wire delay_FINEENABLE; + wire delay_FINEINC; + wire delay_FREQREFCLK; + wire delay_MEMREFCLK; + wire delay_PHASEREFCLK; + wire delay_RST; + wire delay_RSTDQSFIND; + wire delay_SCANCLK = 1'b1; + wire delay_SCANENB = 1'b1; + wire delay_SCANIN = 1'b1; + wire delay_SCANMODEB = 1'b1; + wire delay_SELCALORSTG1 = 1'b1; + wire delay_STG1INCDEC = 1'b1; + wire delay_STG1LOAD = 1'b1; + wire delay_STG1READ = 1'b1; + wire delay_SYNCIN; + wire delay_SYSCLK; + wire delay_GSR; + + assign #(OUTCLK_DELAY) ICLK = delay_ICLK; + assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV; + assign #(OUTCLK_DELAY) RCLK = delay_RCLK; + + assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL; + assign #(out_delay) DQSFOUND = delay_DQSFOUND; + assign #(out_delay) DQSOUTOFRANGE = delay_DQSOUTOFRANGE; + assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW; + assign #(out_delay) ISERDESRST = delay_ISERDESRST; + assign #(out_delay) PHASELOCKED = delay_PHASELOCKED; + assign #(out_delay) WRENABLE = delay_WRENABLE; + +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK; +`endif + + assign #(in_delay) delay_BURSTPENDINGPHY = BURSTPENDINGPHY; +`ifndef XIL_TIMING + assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN; + assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL; + assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN; +`endif + assign #(in_delay) delay_ENCALIBPHY = ENCALIBPHY; +`ifndef XIL_TIMING + assign #(in_delay) delay_FINEENABLE = FINEENABLE; + assign #(in_delay) delay_FINEINC = FINEINC; +`endif + assign #(in_delay) delay_FREQREFCLK = FREQREFCLK; + assign #(in_delay) delay_MEMREFCLK = MEMREFCLK; + assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK; + assign #(in_delay) delay_RANKSELPHY = RANKSELPHY; + assign #(in_delay) delay_RST = RST; +`ifndef XIL_TIMING + assign #(in_delay) delay_RSTDQSFIND = RSTDQSFIND; +`endif + assign #(in_delay) delay_SYNCIN = SYNCIN; + assign delay_GSR = GSR; + + SIP_PHASER_IN # ( + .REFCLK_PERIOD (REFCLK_PERIOD) + ) PHASER_IN_INST ( + .BURST_MODE (BURST_MODE_BINARY), + .CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY), + .CLKOUT_DIV (CLKOUT_DIV_BINARY), + .CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY), + .CTL_MODE (CTL_MODE_BINARY), + .DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY), + .DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY), + .DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY), + .EN_ISERDES_RST (EN_ISERDES_RST_BINARY), + .EN_TEST_RING (EN_TEST_RING_BINARY), + .FINE_DELAY (FINE_DELAY_BINARY), + .FREQ_REF_DIV (FREQ_REF_DIV_BINARY), + .GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY), + .HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY), + .ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY), + .OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY), + .PD_REVERSE (PD_REVERSE_BINARY), + .PHASER_IN_EN (PHASER_IN_EN_BINARY), + .RD_ADDR_INIT (RD_ADDR_INIT_BINARY), + .REG_OPT_1 (REG_OPT_1_BINARY), + .REG_OPT_2 (REG_OPT_2_BINARY), + .REG_OPT_4 (REG_OPT_4_BINARY), + .RST_SEL (RST_SEL_BINARY), + .SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY), + .SEL_OUT (SEL_OUT_BINARY), + .STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY), + .SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY), + .TEST_BP (TEST_BP_BINARY), + .UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY), + .WR_CYCLES (WR_CYCLES_BINARY), + .CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY), + + .COUNTERREADVAL (delay_COUNTERREADVAL), + .DQSFOUND (delay_DQSFOUND), + .DQSOUTOFRANGE (delay_DQSOUTOFRANGE), + .FINEOVERFLOW (delay_FINEOVERFLOW), + .ICLK (delay_ICLK), + .ICLKDIV (delay_ICLKDIV), + .ISERDESRST (delay_ISERDESRST), + .PHASELOCKED (delay_PHASELOCKED), + .RCLK (delay_RCLK), + .SCANOUT (delay_SCANOUT), + .STG1OVERFLOW (delay_STG1OVERFLOW), + .STG1REGR (delay_STG1REGR), + .TESTOUT (delay_TESTOUT), + .WRENABLE (delay_WRENABLE), + .BURSTPENDING (delay_BURSTPENDING), + .BURSTPENDINGPHY (delay_BURSTPENDINGPHY), + .COUNTERLOADEN (delay_COUNTERLOADEN), + .COUNTERLOADVAL (delay_COUNTERLOADVAL), + .COUNTERREADEN (delay_COUNTERREADEN), + .DIVIDERST (delay_DIVIDERST), + .EDGEADV (delay_EDGEADV), + .ENCALIB (delay_ENCALIB), + .ENCALIBPHY (delay_ENCALIBPHY), + .ENSTG1 (delay_ENSTG1), + .ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB), + .FINEENABLE (delay_FINEENABLE), + .FINEINC (delay_FINEINC), + .FREQREFCLK (delay_FREQREFCLK), + .MEMREFCLK (delay_MEMREFCLK), + .PHASEREFCLK (delay_PHASEREFCLK), + .RANKSEL (delay_RANKSEL), + .RANKSELPHY (delay_RANKSELPHY), + .RST (delay_RST ^ IS_RST_INVERTED_REG), + .RSTDQSFIND (delay_RSTDQSFIND), + .SCANCLK (delay_SCANCLK), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .SCANMODEB (delay_SCANMODEB), + .SELCALORSTG1 (delay_SELCALORSTG1), + .STG1INCDEC (delay_STG1INCDEC), + .STG1LOAD (delay_STG1LOAD), + .STG1READ (delay_STG1READ), + .STG1REGL (delay_STG1REGL), + .SYNCIN (delay_SYNCIN), + .SYSCLK (delay_SYSCLK), + .TESTIN (delay_TESTIN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (posedge SYSCLK, 0:0:0, notifier); + $setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, negedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND); + $setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, posedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND); + $width (negedge FREQREFCLK, 0:0:0, 0, notifier); + $width (negedge MEMREFCLK, 0:0:0, 0, notifier); + $width (negedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (negedge SYNCIN, 0:0:0, 0, notifier); + $width (negedge SYSCLK, 0:0:0, 0, notifier); + $width (posedge FREQREFCLK, 0:0:0, 0, notifier); + $width (posedge MEMREFCLK, 0:0:0, 0, notifier); + $width (posedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (posedge SYNCIN, 0:0:0, 0, notifier); + $width (posedge SYSCLK, 0:0:0, 0, notifier); + ( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( FREQREFCLK *> WRENABLE) = (10:10:10, 10:10:10); + ( MEMREFCLK *> DQSFOUND) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> WRENABLE) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> WRENABLE) = (10:10:10, 10:10:10); + ( RST *> DQSOUTOFRANGE) = (10:10:10, 10:10:10); + ( RST *> PHASELOCKED) = (10:10:10, 10:10:10); + ( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10); + ( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHASER_IN_PHY + +`endcelldefine diff --git a/verilog/src/unisims/PHASER_OUT.v b/verilog/src/unisims/PHASER_OUT.v new file mode 100644 index 0000000..a3fd17f --- /dev/null +++ b/verilog/src/unisims/PHASER_OUT.v @@ -0,0 +1,509 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Simulation Library Component +// / / 7SERIES PHASER OUT +// /__/ /\ Filename : PHASER_OUT.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Comment: +// 22APR2010 Initial UNI/UNP/SIM version from yaml +// 12JUL2010 enable secureip +// 14JUL2010 Hook up GSR +// 26AUG2010 rtl, yaml update +// 24SEP2010 rtl, yaml update +// 29SEP2010 add width checks +// 13OCT2010 rtl, yaml update +// 26OCT2010 rtl update +// delay yaml update +// 02NOV2010 yaml update, correct tieoffs +// 05NOV2010 secureip parameter name update +// 01DEC2010 yaml update, REFCLK_PERIOD max +// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC, STG1_BYPASS +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 02FEB2011 592485 yaml, rtl update +// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter +// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed +// 15AUG2011 621681 yml update, remove SIM_SPEEDUP make default +// 02SEP2011 623558 dly.yml update +// 15FEB2012 646230 yml update, add param PO +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHASER_OUT ( + COARSEOVERFLOW, + COUNTERREADVAL, + FINEOVERFLOW, + OCLK, + OCLKDELAYED, + OCLKDIV, + OSERDESRST, + + COARSEENABLE, + COARSEINC, + COUNTERLOADEN, + COUNTERLOADVAL, + COUNTERREADEN, + DIVIDERST, + EDGEADV, + FINEENABLE, + FINEINC, + FREQREFCLK, + MEMREFCLK, + PHASEREFCLK, + RST, + SELFINEOCLKDELAY, + SYNCIN, + SYSCLK +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter EN_OSERDES_RST = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; +`else + localparam in_delay = 1; + localparam out_delay = 1; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 1; +`endif + localparam MODULE_NAME = "PHASER_OUT"; + + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output [8:0] COUNTERREADVAL; + + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input DIVIDERST; + input EDGEADV; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [8:0] COUNTERLOADVAL; + + reg MEMREFCLK_PERIOD_BINARY; + reg PHASEREFCLK_PERIOD_BINARY; + reg REFCLK_PERIOD_BINARY; + reg IS_RST_INVERTED_BIN = IS_RST_INVERTED; + reg [0:0] COARSE_BYPASS_BINARY; + reg [0:0] CTL_MODE_BINARY; + reg [0:0] DATA_CTL_N_BINARY; + reg [0:0] DATA_RD_CYCLES_BINARY; + reg [0:0] EN_OSERDES_RST_BINARY; + reg [0:0] EN_TEST_RING_BINARY; + reg [0:0] OCLKDELAY_INV_BINARY; + reg [0:0] PHASER_OUT_EN_BINARY; + reg [0:0] STG1_BYPASS_BINARY; + reg [0:0] SYNC_IN_DIV_RST_BINARY; + reg [10:0] TEST_OPT_BINARY; + reg [1:0] OUTPUT_CLK_SRC_BINARY; + reg [2:0] PO_BINARY; + reg [3:0] CLKOUT_DIV_BINARY; + reg [3:0] CLKOUT_DIV_POS_BINARY; + reg [3:0] CLKOUT_DIV_ST_BINARY; + reg [5:0] COARSE_DELAY_BINARY; + reg [5:0] FINE_DELAY_BINARY; + reg [5:0] OCLK_DELAY_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (CLKOUT_DIV) + 4 : CLKOUT_DIV_BINARY <= 4'b0010; + 2 : CLKOUT_DIV_BINARY <= 4'b0000; + 3 : CLKOUT_DIV_BINARY <= 4'b0001; + 5 : CLKOUT_DIV_BINARY <= 4'b0011; + 6 : CLKOUT_DIV_BINARY <= 4'b0100; + 7 : CLKOUT_DIV_BINARY <= 4'b0101; + 8 : CLKOUT_DIV_BINARY <= 4'b0110; + 9 : CLKOUT_DIV_BINARY <= 4'b0111; + 10 : CLKOUT_DIV_BINARY <= 4'b1000; + 11 : CLKOUT_DIV_BINARY <= 4'b1001; + 12 : CLKOUT_DIV_BINARY <= 4'b1010; + 13 : CLKOUT_DIV_BINARY <= 4'b1011; + 14 : CLKOUT_DIV_BINARY <= 4'b1100; + 15 : CLKOUT_DIV_BINARY <= 4'b1101; + 16 : CLKOUT_DIV_BINARY <= 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV); + #1 $finish; + end + endcase + + case (COARSE_BYPASS) + "FALSE" : COARSE_BYPASS_BINARY <= 1'b0; + "TRUE" : COARSE_BYPASS_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COARSE_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, COARSE_BYPASS); + #1 $finish; + end + endcase + + CTL_MODE_BINARY <= 1'b0; // model alert + + DATA_CTL_N_BINARY <= 1'b0; + + DATA_RD_CYCLES_BINARY <= 1'b0; + case (EN_OSERDES_RST) + "FALSE" : EN_OSERDES_RST_BINARY <= 1'b0; + "TRUE" : EN_OSERDES_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EN_OSERDES_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_OSERDES_RST); + #1 $finish; + end + endcase + + EN_TEST_RING_BINARY <= 1'b0; + + case (OCLKDELAY_INV) + "FALSE" : OCLKDELAY_INV_BINARY <= 1'b0; + "TRUE" : OCLKDELAY_INV_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute OCLKDELAY_INV on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OCLKDELAY_INV); + #1 $finish; + end + endcase + + case (OUTPUT_CLK_SRC) + "PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b00; + "DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b11; + "DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b01; + "FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_PHASE_REF, DELAYED_REF or FREQ_REF.", MODULE_NAME, OUTPUT_CLK_SRC); + #1 $finish; + end + endcase + + PHASER_OUT_EN_BINARY <= 1'b1; + + if (OUTPUT_CLK_SRC == "DELAYED_PHASE_REF") + STG1_BYPASS_BINARY <= 1'b0; + else + STG1_BYPASS_BINARY <= 1'b1; + + case (SYNC_IN_DIV_RST) + "FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0; + "TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST); + #1 $finish; + end + endcase + + case (CLKOUT_DIV) + 2 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 3 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 4 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 5 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 6 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 7 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 8 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 9 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 10 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 11 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 12 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 13 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 14 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 15 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 16 : CLKOUT_DIV_POS_BINARY <= 4'b1000; + default: CLKOUT_DIV_POS_BINARY <= 4'b0010; + endcase + + CLKOUT_DIV_ST_BINARY <= 4'b0000; + + if ((COARSE_DELAY >= 0) && (COARSE_DELAY <= 63)) + COARSE_DELAY_BINARY <= COARSE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute COARSE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, COARSE_DELAY); + #1 $finish; + end + + if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63)) + FINE_DELAY_BINARY <= FINE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY); + #1 $finish; + end + + if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000)) + MEMREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, MEMREFCLK_PERIOD); + #1 $finish; + end + + if ((OCLK_DELAY >= 0) && (OCLK_DELAY <= 63)) + OCLK_DELAY_BINARY <= OCLK_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute OCLK_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, OCLK_DELAY); + #1 $finish; + end + + if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000)) + PHASEREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD); + #1 $finish; + end + + if ((PO >= 3'b000) && (PO <= 3'b111)) + PO_BINARY <= PO; + else begin + $display("Attribute Syntax Error : The Attribute PO on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PO); + #1 $finish; + end + + if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500)) + REFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD); + #1 $finish; + end + + TEST_OPT_BINARY <= {2'b0,PO,6'b0}; + + end + + wire [1:0] delay_CTSBUS; + wire [1:0] delay_DQSBUS; + wire [1:0] delay_DTSBUS; + wire [3:0] delay_TESTOUT; + wire [8:0] delay_COUNTERREADVAL; + wire delay_COARSEOVERFLOW; + wire delay_FINEOVERFLOW; + wire delay_OCLK; + wire delay_OCLKDELAYED; + wire delay_OCLKDIV; + wire delay_OSERDESRST; + wire delay_RDENABLE; + wire delay_SCANOUT; + + wire [15:0] delay_TESTIN = 16'hffff; + wire [1:0] delay_ENCALIB = 2'b11; + wire [1:0] delay_ENCALIBPHY = 2'b0; + wire [8:0] delay_COUNTERLOADVAL; + wire delay_BURSTPENDING = 1'b1; + wire delay_BURSTPENDINGPHY = 1'b0; + wire delay_COARSEENABLE; + wire delay_COARSEINC; + wire delay_COUNTERLOADEN; + wire delay_COUNTERREADEN; + wire delay_DIVIDERST; + wire delay_EDGEADV; + wire delay_FINEENABLE; + wire delay_FINEINC; + wire delay_FREQREFCLK; + wire delay_MEMREFCLK; + wire delay_PHASEREFCLK; + wire delay_RST; + wire delay_SCANCLK = 1'b1; + wire delay_SCANENB = 1'b1; + wire delay_SCANIN = 1'b1; + wire delay_SCANMODEB = 1'b1; + wire delay_SELFINEOCLKDELAY; + wire delay_SYNCIN; + wire delay_SYSCLK; + wire delay_GSR; + + assign #(OUTCLK_DELAY) OCLKDELAYED = delay_OCLKDELAYED; + assign #(OUTCLK_DELAY) OCLKDIV = delay_OCLKDIV; + assign #(OUTCLK_DELAY) OCLK = delay_OCLK; + + assign #(out_delay) COARSEOVERFLOW = delay_COARSEOVERFLOW; + assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL; + assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW; + assign #(out_delay) OSERDESRST = delay_OSERDESRST; + + assign #(INCLK_DELAY) delay_FREQREFCLK = FREQREFCLK; +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK; + + assign #(in_delay) delay_COARSEENABLE = COARSEENABLE; + assign #(in_delay) delay_COARSEINC = COARSEINC; + assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN; + assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL; + assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN; +`endif + assign #(in_delay) delay_DIVIDERST = DIVIDERST; +`ifndef XIL_TIMING + assign #(in_delay) delay_EDGEADV = EDGEADV; + assign #(in_delay) delay_FINEENABLE = FINEENABLE; + assign #(in_delay) delay_FINEINC = FINEINC; +`endif + assign #(in_delay) delay_MEMREFCLK = MEMREFCLK; + assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK; + assign #(in_delay) delay_RST = RST; + assign #(in_delay) delay_SELFINEOCLKDELAY = SELFINEOCLKDELAY; + assign #(in_delay) delay_SYNCIN = SYNCIN; + assign delay_GSR = GSR; + + SIP_PHASER_OUT #( + .REFCLK_PERIOD (REFCLK_PERIOD) + ) PHASER_OUT_INST ( + .CLKOUT_DIV (CLKOUT_DIV_BINARY), + .CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY), + .CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY), + .COARSE_BYPASS (COARSE_BYPASS_BINARY), + .COARSE_DELAY (COARSE_DELAY_BINARY), + .CTL_MODE (CTL_MODE_BINARY), + .DATA_CTL_N (DATA_CTL_N_BINARY), + .DATA_RD_CYCLES (DATA_RD_CYCLES_BINARY), + .EN_OSERDES_RST (EN_OSERDES_RST_BINARY), + .EN_TEST_RING (EN_TEST_RING_BINARY), + .FINE_DELAY (FINE_DELAY_BINARY), + .OCLKDELAY_INV (OCLKDELAY_INV_BINARY), + .OCLK_DELAY (OCLK_DELAY_BINARY), + .OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY), + .PHASER_OUT_EN (PHASER_OUT_EN_BINARY), + .STG1_BYPASS (STG1_BYPASS_BINARY), + .SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY), + .TEST_OPT (TEST_OPT_BINARY), + + .COARSEOVERFLOW (delay_COARSEOVERFLOW), + .COUNTERREADVAL (delay_COUNTERREADVAL), + .CTSBUS (delay_CTSBUS), + .DQSBUS (delay_DQSBUS), + .DTSBUS (delay_DTSBUS), + .FINEOVERFLOW (delay_FINEOVERFLOW), + .OCLK (delay_OCLK), + .OCLKDELAYED (delay_OCLKDELAYED), + .OCLKDIV (delay_OCLKDIV), + .OSERDESRST (delay_OSERDESRST), + .RDENABLE (delay_RDENABLE), + .SCANOUT (delay_SCANOUT), + .TESTOUT (delay_TESTOUT), + .BURSTPENDING (delay_BURSTPENDING), + .BURSTPENDINGPHY (delay_BURSTPENDINGPHY), + .COARSEENABLE (delay_COARSEENABLE), + .COARSEINC (delay_COARSEINC), + .COUNTERLOADEN (delay_COUNTERLOADEN), + .COUNTERLOADVAL (delay_COUNTERLOADVAL), + .COUNTERREADEN (delay_COUNTERREADEN), + .DIVIDERST (delay_DIVIDERST), + .EDGEADV (delay_EDGEADV), + .ENCALIB (delay_ENCALIB), + .ENCALIBPHY (delay_ENCALIBPHY), + .FINEENABLE (delay_FINEENABLE), + .FINEINC (delay_FINEINC), + .FREQREFCLK (delay_FREQREFCLK), + .MEMREFCLK (delay_MEMREFCLK), + .PHASEREFCLK (delay_PHASEREFCLK), + .RST (delay_RST ^ IS_RST_INVERTED_BIN), + .SCANCLK (delay_SCANCLK), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .SCANMODEB (delay_SCANMODEB), + .SELFINEOCLKDELAY (delay_SELFINEOCLKDELAY), + .SYNCIN (delay_SYNCIN), + .SYSCLK (delay_SYSCLK), + .TESTIN (delay_TESTIN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (posedge FREQREFCLK, 0:0:0, notifier); + $period (posedge SYSCLK, 0:0:0, notifier); + $setuphold (posedge SYSCLK, negedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE); + $setuphold (posedge SYSCLK, negedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC); + $setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, negedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV); + $setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, posedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE); + $setuphold (posedge SYSCLK, posedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC); + $setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, posedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV); + $setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $width (negedge FREQREFCLK, 0:0:0, 0, notifier); + $width (negedge MEMREFCLK, 0:0:0, 0, notifier); + $width (negedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (negedge SYNCIN, 0:0:0, 0, notifier); + $width (negedge SYSCLK, 0:0:0, 0, notifier); + $width (posedge FREQREFCLK, 0:0:0, 0, notifier); + $width (posedge MEMREFCLK, 0:0:0, 0, notifier); + $width (posedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (posedge SYNCIN, 0:0:0, 0, notifier); + $width (posedge SYSCLK, 0:0:0, 0, notifier); + ( MEMREFCLK *> OCLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OCLKDIV) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OSERDESRST) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLKDIV) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OSERDESRST) = (10:10:10, 10:10:10); + ( SYSCLK *> COARSEOVERFLOW) = (10:10:10, 10:10:10); + ( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10); + ( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHASER_OUT + +`endcelldefine diff --git a/verilog/src/unisims/PHASER_OUT_PHY.v b/verilog/src/unisims/PHASER_OUT_PHY.v new file mode 100644 index 0000000..8ab4df3 --- /dev/null +++ b/verilog/src/unisims/PHASER_OUT_PHY.v @@ -0,0 +1,540 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Simulation Library Component +// / / 7SERIES PHASER OUT +// /__/ /\ Filename : PHASER_OUT_PHY.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Comment: +// 22APR2010 Initial UNI/UNP/SIM version from yaml +// 12JUL2010 enable secureip +// 14JUL2010 Hook up GSR +// 26AUG2010 rtl, yaml update +// 24SEP2010 rtl, yaml update +// 29SEP2010 add width checks +// 13OCT2010 rtl, yaml update +// 26OCT2010 rtl update +// delay yaml update +// 02NOV2010 yaml update, correct tieoffs +// 05NOV2010 secureip parameter name update +// 11NOV2010 582473 multiple drivers on delay_MEMREFCLK +// 01DEC2010 yaml update, REFCLK_PERIOD max +// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC, STG1_BYPASS +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 02FEB2011 592485 yaml, rtl update +// 19MAY2011 611139 remove period, setup/hold checks on MEM/PHASEREFCLK, SYNCIN +// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter +// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed +// 15AUG2011 621681 yml update, remove SIM_SPEEDUP make default +// 02SEP2011 623558 dly.yml update +// 15FEB2012 646230 yml update, add param PO +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHASER_OUT_PHY ( + COARSEOVERFLOW, + COUNTERREADVAL, + CTSBUS, + DQSBUS, + DTSBUS, + FINEOVERFLOW, + OCLK, + OCLKDELAYED, + OCLKDIV, + OSERDESRST, + RDENABLE, + + BURSTPENDINGPHY, + COARSEENABLE, + COARSEINC, + COUNTERLOADEN, + COUNTERLOADVAL, + COUNTERREADEN, + ENCALIBPHY, + FINEENABLE, + FINEINC, + FREQREFCLK, + MEMREFCLK, + PHASEREFCLK, + RST, + SELFINEOCLKDELAY, + SYNCIN, + SYSCLK +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter DATA_CTL_N = "FALSE"; + parameter DATA_RD_CYCLES = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; +`else + localparam in_delay = 1; + localparam out_delay = 1; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 1; +`endif + localparam MODULE_NAME = "PHASER_OUT_PHY"; + + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output RDENABLE; + output [1:0] CTSBUS; + output [1:0] DQSBUS; + output [1:0] DTSBUS; + output [8:0] COUNTERREADVAL; + + input BURSTPENDINGPHY; + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [1:0] ENCALIBPHY; + input [8:0] COUNTERLOADVAL; + + reg MEMREFCLK_PERIOD_BINARY; + reg PHASEREFCLK_PERIOD_BINARY; + reg REFCLK_PERIOD_BINARY; + reg IS_RST_INVERTED_BIN = IS_RST_INVERTED; + reg [0:0] COARSE_BYPASS_BINARY; + reg [0:0] CTL_MODE_BINARY; + reg [0:0] DATA_CTL_N_BINARY; + reg [0:0] DATA_RD_CYCLES_BINARY; + reg [0:0] EN_OSERDES_RST_BINARY; + reg [0:0] EN_TEST_RING_BINARY; + reg [0:0] OCLKDELAY_INV_BINARY; + reg [0:0] PHASER_OUT_EN_BINARY; + reg [0:0] STG1_BYPASS_BINARY; + reg [0:0] SYNC_IN_DIV_RST_BINARY; + reg [10:0] TEST_OPT_BINARY; + reg [1:0] OUTPUT_CLK_SRC_BINARY; + reg [2:0] PO_BINARY; + reg [3:0] CLKOUT_DIV_BINARY; + reg [3:0] CLKOUT_DIV_POS_BINARY; + reg [3:0] CLKOUT_DIV_ST_BINARY; + reg [5:0] COARSE_DELAY_BINARY; + reg [5:0] FINE_DELAY_BINARY; + reg [5:0] OCLK_DELAY_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (CLKOUT_DIV) + 4 : CLKOUT_DIV_BINARY <= 4'b0010; + 2 : CLKOUT_DIV_BINARY <= 4'b0000; + 3 : CLKOUT_DIV_BINARY <= 4'b0001; + 5 : CLKOUT_DIV_BINARY <= 4'b0011; + 6 : CLKOUT_DIV_BINARY <= 4'b0100; + 7 : CLKOUT_DIV_BINARY <= 4'b0101; + 8 : CLKOUT_DIV_BINARY <= 4'b0110; + 9 : CLKOUT_DIV_BINARY <= 4'b0111; + 10 : CLKOUT_DIV_BINARY <= 4'b1000; + 11 : CLKOUT_DIV_BINARY <= 4'b1001; + 12 : CLKOUT_DIV_BINARY <= 4'b1010; + 13 : CLKOUT_DIV_BINARY <= 4'b1011; + 14 : CLKOUT_DIV_BINARY <= 4'b1100; + 15 : CLKOUT_DIV_BINARY <= 4'b1101; + 16 : CLKOUT_DIV_BINARY <= 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV); + #1 $finish; + end + endcase + + case (COARSE_BYPASS) + "FALSE" : COARSE_BYPASS_BINARY <= 1'b0; + "TRUE" : COARSE_BYPASS_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COARSE_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, COARSE_BYPASS); + #1 $finish; + end + endcase + + CTL_MODE_BINARY <= 1'b1; // model alert + + case (DATA_CTL_N) + "FALSE" : DATA_CTL_N_BINARY <= 1'b0; + "TRUE" : DATA_CTL_N_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_CTL_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_N); + #1 $finish; + end + endcase + + case (DATA_RD_CYCLES) + "FALSE" : DATA_RD_CYCLES_BINARY <= 1'b0; + "TRUE" : DATA_RD_CYCLES_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_RD_CYCLES on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_RD_CYCLES); + #1 $finish; + end + endcase + + EN_OSERDES_RST_BINARY <= 1'b0; + + EN_TEST_RING_BINARY <= 1'b0; + + case (OCLKDELAY_INV) + "FALSE" : OCLKDELAY_INV_BINARY <= 1'b0; + "TRUE" : OCLKDELAY_INV_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute OCLKDELAY_INV on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OCLKDELAY_INV); + #1 $finish; + end + endcase + + case (OUTPUT_CLK_SRC) + "PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b00; + "DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b11; + "DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b01; + "FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_PHASE_REF, DELAYED_REF or FREQ_REF.", MODULE_NAME, OUTPUT_CLK_SRC); + #1 $finish; + end + endcase + + PHASER_OUT_EN_BINARY <= 1'b1; + + if (OUTPUT_CLK_SRC == "DELAYED_PHASE_REF") + STG1_BYPASS_BINARY <= 1'b0; + else + STG1_BYPASS_BINARY <= 1'b1; + + case (SYNC_IN_DIV_RST) + "FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0; + "TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST); + #1 $finish; + end + endcase + + case (CLKOUT_DIV) + 2 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 3 : CLKOUT_DIV_POS_BINARY <= 4'b0001; + 4 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 5 : CLKOUT_DIV_POS_BINARY <= 4'b0010; + 6 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 7 : CLKOUT_DIV_POS_BINARY <= 4'b0011; + 8 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 9 : CLKOUT_DIV_POS_BINARY <= 4'b0100; + 10 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 11 : CLKOUT_DIV_POS_BINARY <= 4'b0101; + 12 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 13 : CLKOUT_DIV_POS_BINARY <= 4'b0110; + 14 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 15 : CLKOUT_DIV_POS_BINARY <= 4'b0111; + 16 : CLKOUT_DIV_POS_BINARY <= 4'b1000; + default: CLKOUT_DIV_POS_BINARY <= 4'b0010; + endcase + + CLKOUT_DIV_ST_BINARY <= 4'b0000; + + if ((COARSE_DELAY >= 0) && (COARSE_DELAY <= 63)) + COARSE_DELAY_BINARY <= COARSE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute COARSE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, COARSE_DELAY); + #1 $finish; + end + + if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63)) + FINE_DELAY_BINARY <= FINE_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY); + #1 $finish; + end + + if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000)) + MEMREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, MEMREFCLK_PERIOD); + #1 $finish; + end + + if ((OCLK_DELAY >= 0) && (OCLK_DELAY <= 63)) + OCLK_DELAY_BINARY <= OCLK_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute OCLK_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, OCLK_DELAY); + #1 $finish; + end + + if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000)) + PHASEREFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD); + #1 $finish; + end + + if ((PO >= 3'b000) && (PO <= 3'b111)) + PO_BINARY <= PO; + else begin + $display("Attribute Syntax Error : The Attribute PO on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PO); + #1 $finish; + end + + if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500)) + REFCLK_PERIOD_BINARY <= 1'b1; + else begin + $display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD); + #1 $finish; + end + + TEST_OPT_BINARY <= {2'b0,PO,6'b0}; + + end + + wire [1:0] delay_CTSBUS; + wire [1:0] delay_DQSBUS; + wire [1:0] delay_DTSBUS; + wire [3:0] delay_TESTOUT; + wire [8:0] delay_COUNTERREADVAL; + wire delay_COARSEOVERFLOW; + wire delay_FINEOVERFLOW; + wire delay_OCLK; + wire delay_OCLKDELAYED; + wire delay_OCLKDIV; + wire delay_OSERDESRST; + wire delay_RDENABLE; + wire delay_SCANOUT; + + wire [15:0] delay_TESTIN = 16'hffff; + wire [1:0] delay_ENCALIB = 2'b11; + wire [1:0] delay_ENCALIBPHY; + wire [8:0] delay_COUNTERLOADVAL; + wire delay_BURSTPENDING = 1'b1; + wire delay_BURSTPENDINGPHY; + wire delay_COARSEENABLE; + wire delay_COARSEINC; + wire delay_COUNTERLOADEN; + wire delay_COUNTERREADEN; + wire delay_DIVIDERST = 1'b0; + wire delay_EDGEADV = 1'b0; + wire delay_FINEENABLE; + wire delay_FINEINC; + wire delay_FREQREFCLK; + wire delay_MEMREFCLK; + wire delay_PHASEREFCLK; + wire delay_RST; + wire delay_SCANCLK = 1'b1; + wire delay_SCANENB = 1'b1; + wire delay_SCANIN = 1'b1; + wire delay_SCANMODEB = 1'b1; + wire delay_SELFINEOCLKDELAY; + wire delay_SYNCIN; + wire delay_SYSCLK; + wire delay_GSR; + + assign #(OUTCLK_DELAY) OCLKDELAYED = delay_OCLKDELAYED; + assign #(OUTCLK_DELAY) OCLKDIV = delay_OCLKDIV; + assign #(OUTCLK_DELAY) OCLK = delay_OCLK; + + assign #(out_delay) COARSEOVERFLOW = delay_COARSEOVERFLOW; + assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL; + assign #(out_delay) CTSBUS = delay_CTSBUS; + assign #(out_delay) DQSBUS = delay_DQSBUS; + assign #(out_delay) DTSBUS = delay_DTSBUS; + assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW; + assign #(out_delay) OSERDESRST = delay_OSERDESRST; + assign #(out_delay) RDENABLE = delay_RDENABLE; + + assign #(INCLK_DELAY) delay_FREQREFCLK = FREQREFCLK; +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK; +`endif + + assign #(in_delay) delay_BURSTPENDINGPHY = BURSTPENDINGPHY; +`ifndef XIL_TIMING + assign #(in_delay) delay_COARSEENABLE = COARSEENABLE; + assign #(in_delay) delay_COARSEINC = COARSEINC; + assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN; + assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL; + assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN; +`endif + assign #(in_delay) delay_ENCALIBPHY = ENCALIBPHY; +`ifndef XIL_TIMING + assign #(in_delay) delay_FINEENABLE = FINEENABLE; + assign #(in_delay) delay_FINEINC = FINEINC; +`endif + assign #(in_delay) delay_MEMREFCLK = MEMREFCLK; + assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK; + assign #(in_delay) delay_RST = RST; + assign #(in_delay) delay_SELFINEOCLKDELAY = SELFINEOCLKDELAY; + assign #(in_delay) delay_SYNCIN = SYNCIN; + assign delay_GSR = GSR; + + SIP_PHASER_OUT #( + .REFCLK_PERIOD (REFCLK_PERIOD) + ) PHASER_OUT_INST ( + .CLKOUT_DIV (CLKOUT_DIV_BINARY), + .CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY), + .CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY), + .COARSE_BYPASS (COARSE_BYPASS_BINARY), + .COARSE_DELAY (COARSE_DELAY_BINARY), + .CTL_MODE (CTL_MODE_BINARY), + .DATA_CTL_N (DATA_CTL_N_BINARY), + .DATA_RD_CYCLES (DATA_RD_CYCLES_BINARY), + .EN_OSERDES_RST (EN_OSERDES_RST_BINARY), + .EN_TEST_RING (EN_TEST_RING_BINARY), + .FINE_DELAY (FINE_DELAY_BINARY), + .OCLKDELAY_INV (OCLKDELAY_INV_BINARY), + .OCLK_DELAY (OCLK_DELAY_BINARY), + .OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY), + .PHASER_OUT_EN (PHASER_OUT_EN_BINARY), + .STG1_BYPASS (STG1_BYPASS_BINARY), + .SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY), + .TEST_OPT (TEST_OPT_BINARY), + + .COARSEOVERFLOW (delay_COARSEOVERFLOW), + .COUNTERREADVAL (delay_COUNTERREADVAL), + .CTSBUS (delay_CTSBUS), + .DQSBUS (delay_DQSBUS), + .DTSBUS (delay_DTSBUS), + .FINEOVERFLOW (delay_FINEOVERFLOW), + .OCLK (delay_OCLK), + .OCLKDELAYED (delay_OCLKDELAYED), + .OCLKDIV (delay_OCLKDIV), + .OSERDESRST (delay_OSERDESRST), + .RDENABLE (delay_RDENABLE), + .SCANOUT (delay_SCANOUT), + .TESTOUT (delay_TESTOUT), + .BURSTPENDING (delay_BURSTPENDING), + .BURSTPENDINGPHY (delay_BURSTPENDINGPHY), + .COARSEENABLE (delay_COARSEENABLE), + .COARSEINC (delay_COARSEINC), + .COUNTERLOADEN (delay_COUNTERLOADEN), + .COUNTERLOADVAL (delay_COUNTERLOADVAL), + .COUNTERREADEN (delay_COUNTERREADEN), + .DIVIDERST (delay_DIVIDERST), + .EDGEADV (delay_EDGEADV), + .ENCALIB (delay_ENCALIB), + .ENCALIBPHY (delay_ENCALIBPHY), + .FINEENABLE (delay_FINEENABLE), + .FINEINC (delay_FINEINC), + .FREQREFCLK (delay_FREQREFCLK), + .MEMREFCLK (delay_MEMREFCLK), + .PHASEREFCLK (delay_PHASEREFCLK), + .RST (delay_RST ^ IS_RST_INVERTED_BIN), + .SCANCLK (delay_SCANCLK), + .SCANENB (delay_SCANENB), + .SCANIN (delay_SCANIN), + .SCANMODEB (delay_SCANMODEB), + .SELFINEOCLKDELAY (delay_SELFINEOCLKDELAY), + .SYNCIN (delay_SYNCIN), + .SYSCLK (delay_SYSCLK), + .TESTIN (delay_TESTIN), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (posedge FREQREFCLK, 0:0:0, notifier); + $period (posedge SYSCLK, 0:0:0, notifier); + $setuphold (posedge SYSCLK, negedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE); + $setuphold (posedge SYSCLK, negedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC); + $setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $setuphold (posedge SYSCLK, posedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE); + $setuphold (posedge SYSCLK, posedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC); + $setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN); + $setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL); + $setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN); + $setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE); + $setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC); + $width (negedge FREQREFCLK, 0:0:0, 0, notifier); + $width (negedge MEMREFCLK, 0:0:0, 0, notifier); + $width (negedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (negedge SYNCIN, 0:0:0, 0, notifier); + $width (negedge SYSCLK, 0:0:0, 0, notifier); + $width (posedge FREQREFCLK, 0:0:0, 0, notifier); + $width (posedge MEMREFCLK, 0:0:0, 0, notifier); + $width (posedge PHASEREFCLK, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + $width (posedge SYNCIN, 0:0:0, 0, notifier); + $width (posedge SYSCLK, 0:0:0, 0, notifier); + ( MEMREFCLK *> CTSBUS) = (10:10:10, 10:10:10); + ( MEMREFCLK *> DQSBUS) = (10:10:10, 10:10:10); + ( MEMREFCLK *> DTSBUS) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OCLK) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OCLKDIV) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OSERDESRST) = (10:10:10, 10:10:10); + ( MEMREFCLK *> RDENABLE) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> CTSBUS) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> DQSBUS) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> DTSBUS) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLK) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OCLKDIV) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> OSERDESRST) = (10:10:10, 10:10:10); + ( PHASEREFCLK *> RDENABLE) = (10:10:10, 10:10:10); + ( SYSCLK *> COARSEOVERFLOW) = (10:10:10, 10:10:10); + ( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10); + ( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHASER_OUT_PHY + +`endcelldefine diff --git a/verilog/src/unisims/PHASER_REF.v b/verilog/src/unisims/PHASER_REF.v new file mode 100644 index 0000000..911a24d --- /dev/null +++ b/verilog/src/unisims/PHASER_REF.v @@ -0,0 +1,187 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx Simulation Library Component +// / / 7SERIES PHASER REF +// /__/ /\ Filename : PHASER_REF.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Comment: +// 23APR2010 Initial UNI/UNP/SIM from yml +// 02JUL2010 add functionality +// 29SEP2010 update functionality based on rtl +// add width checks +// 28OCT2010 CR580289 ref_clock_input_freq_MHz_min/max < vs <= +// 09NOV2010 CR581863 blocking statements, clock counts to lock. +// 11NOV2010 CR582599 warning in place of LOCK +// 01DEC2010 clean up display of real numbers +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 15AUG2011 621681 remove SIM_SPEEDUP make default +// 16APR2012 655365 else missing from delay_LOCKED always block +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHASER_REF ( + LOCKED, + + CLKIN, + PWRDWN, + RST +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam INCLK_DELAY = 0; + localparam out_delay = 0; +`else + localparam in_delay = 1; + localparam INCLK_DELAY = 0; + localparam out_delay = 10; +`endif + localparam MODULE_NAME = "PHASER_REF"; + localparam real REF_CLK_JITTER_MAX = 100.000; + + output LOCKED; + + input CLKIN; + input PWRDWN; + input RST; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + wire delay_CLKIN; + wire delay_PWRDWN; + wire delay_RST; + wire delay_GSR; + + reg delay_LOCKED = 1'b1; + real ref_clock_input_period = 11.0; + real ref_clock_input_freq_MHz = 1.68; + real time_last_rising_edge = 1.0; + real last_ref_clock_input_period = 13.0; + real last_ref_clock_input_freq_MHz = 1.69; + integer same_period_count = 0; + integer different_period_count = 0; + integer same_period_count_last = 0; + integer count_clks = 0; + real ref_clock_input_freq_MHz_min = 400.000; // valid min freq in MHz + real ref_clock_input_freq_MHz_max = 1066.000; // valid max freq in MHz + reg IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED; + reg IS_RST_INVERTED_BIN = IS_RST_INVERTED; + + + assign #(out_delay) LOCKED = delay_LOCKED; + + assign #(INCLK_DELAY) delay_CLKIN = CLKIN; + assign #(in_delay) delay_PWRDWN = PWRDWN ^ IS_PWRDWN_INVERTED_BIN; + assign #(in_delay) delay_RST = RST ^ IS_RST_INVERTED_BIN; + assign delay_GSR = GSR; + + +always @(posedge delay_CLKIN) +begin + last_ref_clock_input_period <= ref_clock_input_period; + last_ref_clock_input_freq_MHz <= ref_clock_input_freq_MHz; + same_period_count_last <= same_period_count; + ref_clock_input_period <= $time - time_last_rising_edge; + ref_clock_input_freq_MHz <= 1e6/($time - time_last_rising_edge); + time_last_rising_edge <= $time/1.0; + if ( (delay_RST==0) && (delay_PWRDWN ==0) && + (ref_clock_input_period - last_ref_clock_input_period <= REF_CLK_JITTER_MAX) && + (last_ref_clock_input_period - ref_clock_input_period <= REF_CLK_JITTER_MAX) ) + begin + if (same_period_count < 6) same_period_count <= same_period_count + 1; + if ( same_period_count >= 3 && same_period_count != same_period_count_last && different_period_count != 0) + begin + different_period_count <= 0; //reset different_period_count + end + end + else // detecting different clock-preiod + begin + different_period_count = different_period_count + 1; + if ( different_period_count >= 1 && same_period_count != 0 ) + begin + same_period_count <= 0 ; //reset same_period_count + end + end +end + +always @(posedge delay_CLKIN or posedge delay_RST or posedge delay_PWRDWN) begin + if ( delay_RST||delay_PWRDWN) + begin + delay_LOCKED <= 1'b0; + count_clks <= 0; + end + else if ((same_period_count >= 1) && (count_clks < 6)) + begin + count_clks <= count_clks + 1; + end + else if (different_period_count >= 1) + begin + delay_LOCKED <= 1'b0; + count_clks <= 0; + end + else if ( (count_clks >= 5) && + ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 >= ref_clock_input_freq_MHz_min ) && + ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 <= ref_clock_input_freq_MHz_max ) ) + begin + delay_LOCKED <= 1'b1; + end +end + +always @(posedge delay_CLKIN) + if ( (count_clks == 5) && + ( ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 < ref_clock_input_freq_MHz_min) || + ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 > ref_clock_input_freq_MHz_max) ) ) begin + $display("Warning: Invalid average CLKIN frequency detected = %4.3f MHz", (ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000); + $display(" on %s instance %m at time %t ps.", MODULE_NAME, $time); + $display(" The valid CLKIN frequency range is:"); + $display(" Minimum = %4.3f MHz", ref_clock_input_freq_MHz_min ); + $display(" Maximum = %4.3f MHz", ref_clock_input_freq_MHz_max ); + end + +`ifdef XIL_TIMING + specify + $period (negedge CLKIN, 0:0:0, notifier); + $period (posedge CLKIN, 0:0:0, notifier); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHASER_REF + +`endcelldefine diff --git a/verilog/src/unisims/PHY_CONTROL.v b/verilog/src/unisims/PHY_CONTROL.v new file mode 100644 index 0000000..7936ab1 --- /dev/null +++ b/verilog/src/unisims/PHY_CONTROL.v @@ -0,0 +1,626 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.1 +// \ \ Description : Xilinx Simulation Library Component +// / / 7SERIES Phaser Phy Control +// /__/ /\ Filename : PHY_CONTROL.v +// \ \ / \ +// \__\/\__ \ +// +// Date: Comment: +// 23APR2010 Initial UNI/UNP/SIM version from yml +// 10JUN2010 yml update +// 02JUL2010 enable secureip +// 20AUG2010 yml, rtl update +// 28SEP2010 yml, rtl update +// 29SEP2010 yml update +// 28OCT2010 rtl update +// 05NOV2010 update defaults +// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG +// 14FEB2011 593832 yml, rtl update +// 16MAR2011 601917 dly.yml update +// 14APR2011 606310 yml update +// 15AUG2011 621681 remove SIM_SPEEDUP, make default +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PHY_CONTROL ( + AUXOUTPUT, + INBURSTPENDING, + INRANKA, + INRANKB, + INRANKC, + INRANKD, + OUTBURSTPENDING, + PCENABLECALIB, + PHYCTLALMOSTFULL, + PHYCTLEMPTY, + PHYCTLFULL, + PHYCTLREADY, + + MEMREFCLK, + PHYCLK, + PHYCTLMSTREMPTY, + PHYCTLWD, + PHYCTLWRENABLE, + PLLLOCK, + READCALIBENABLE, + REFDLLLOCK, + RESET, + SYNCIN, + WRITECALIBENABLE +); + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + parameter integer AO_TOGGLE = 0; + parameter [3:0] AO_WRLVL_EN = 4'b0000; + parameter BURST_MODE = "FALSE"; + parameter integer CLK_RATIO = 1; + parameter integer CMD_OFFSET = 0; + parameter integer CO_DURATION = 0; + parameter DATA_CTL_A_N = "FALSE"; + parameter DATA_CTL_B_N = "FALSE"; + parameter DATA_CTL_C_N = "FALSE"; + parameter DATA_CTL_D_N = "FALSE"; + parameter DISABLE_SEQ_MATCH = "TRUE"; + parameter integer DI_DURATION = 0; + parameter integer DO_DURATION = 0; + parameter integer EVENTS_DELAY = 63; + parameter integer FOUR_WINDOW_CLOCKS = 63; + parameter MULTI_REGION = "FALSE"; + parameter PHY_COUNT_ENABLE = "FALSE"; + parameter integer RD_CMD_OFFSET_0 = 0; + parameter integer RD_CMD_OFFSET_1 = 00; + parameter integer RD_CMD_OFFSET_2 = 0; + parameter integer RD_CMD_OFFSET_3 = 0; + parameter integer RD_DURATION_0 = 0; + parameter integer RD_DURATION_1 = 0; + parameter integer RD_DURATION_2 = 0; + parameter integer RD_DURATION_3 = 0; + parameter SYNC_MODE = "FALSE"; + parameter integer WR_CMD_OFFSET_0 = 0; + parameter integer WR_CMD_OFFSET_1 = 0; + parameter integer WR_CMD_OFFSET_2 = 0; + parameter integer WR_CMD_OFFSET_3 = 0; + parameter integer WR_DURATION_0 = 0; + parameter integer WR_DURATION_1 = 0; + parameter integer WR_DURATION_2 = 0; + parameter integer WR_DURATION_3 = 0; + +`ifdef XIL_TIMING + localparam in_delay = 0; + localparam out_delay = 0; +`else + localparam in_delay = 1; + localparam out_delay = 100; +`endif + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + localparam MODULE_NAME = "PHY_CONTROL"; + + output PHYCTLALMOSTFULL; + output PHYCTLEMPTY; + output PHYCTLFULL; + output PHYCTLREADY; + output [1:0] INRANKA; + output [1:0] INRANKB; + output [1:0] INRANKC; + output [1:0] INRANKD; + output [1:0] PCENABLECALIB; + output [3:0] AUXOUTPUT; + output [3:0] INBURSTPENDING; + output [3:0] OUTBURSTPENDING; + + input MEMREFCLK; + input PHYCLK; + input PHYCTLMSTREMPTY; + input PHYCTLWRENABLE; + input PLLLOCK; + input READCALIBENABLE; + input REFDLLLOCK; + input RESET; + input SYNCIN; + input WRITECALIBENABLE; + input [31:0] PHYCTLWD; + + reg [0:0] BURST_MODE_BINARY; + reg [0:0] DATA_CTL_A_N_BINARY; + reg [0:0] DATA_CTL_B_N_BINARY; + reg [0:0] DATA_CTL_C_N_BINARY; + reg [0:0] DATA_CTL_D_N_BINARY; + reg [0:0] DISABLE_SEQ_MATCH_BINARY; + reg [0:0] MULTI_REGION_BINARY; + reg [0:0] PHY_COUNT_ENABLE_BINARY; + reg [0:0] SPARE_BINARY; + reg [0:0] SYNC_MODE_BINARY; + reg [2:0] CLK_RATIO_BINARY; + reg [2:0] CO_DURATION_BINARY; + reg [2:0] DI_DURATION_BINARY; + reg [2:0] DO_DURATION_BINARY; + reg [3:0] AO_TOGGLE_BINARY; + reg [3:0] AO_WRLVL_EN_BINARY; + reg [5:0] CMD_OFFSET_BINARY; + reg [5:0] EVENTS_DELAY_BINARY; + reg [5:0] FOUR_WINDOW_CLOCKS_BINARY; + reg [5:0] RD_CMD_OFFSET_0_BINARY; + reg [5:0] RD_CMD_OFFSET_1_BINARY; + reg [5:0] RD_CMD_OFFSET_2_BINARY; + reg [5:0] RD_CMD_OFFSET_3_BINARY; + reg [5:0] RD_DURATION_0_BINARY; + reg [5:0] RD_DURATION_1_BINARY; + reg [5:0] RD_DURATION_2_BINARY; + reg [5:0] RD_DURATION_3_BINARY; + reg [5:0] WR_CMD_OFFSET_0_BINARY; + reg [5:0] WR_CMD_OFFSET_1_BINARY; + reg [5:0] WR_CMD_OFFSET_2_BINARY; + reg [5:0] WR_CMD_OFFSET_3_BINARY; + reg [5:0] WR_DURATION_0_BINARY; + reg [5:0] WR_DURATION_1_BINARY; + reg [5:0] WR_DURATION_2_BINARY; + reg [5:0] WR_DURATION_3_BINARY; + + tri0 GSR = glbl.GSR; +`ifdef XIL_TIMING + reg notifier; +`endif + + initial begin + case (BURST_MODE) + "FALSE" : BURST_MODE_BINARY <= 1'b0; + "TRUE" : BURST_MODE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BURST_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BURST_MODE); + #1 $finish; + end + endcase + + case (CLK_RATIO) + 1 : CLK_RATIO_BINARY <= 3'b000; + 2 : CLK_RATIO_BINARY <= 3'b001; + 4 : CLK_RATIO_BINARY <= 3'b010; + 8 : CLK_RATIO_BINARY <= 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_RATIO on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4 or 8.", MODULE_NAME, CLK_RATIO, 1); + #1 $finish; + end + endcase + + case (DATA_CTL_A_N) + "FALSE" : DATA_CTL_A_N_BINARY <= 1'b0; + "TRUE" : DATA_CTL_A_N_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_CTL_A_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_A_N); + #1 $finish; + end + endcase + + case (DATA_CTL_B_N) + "FALSE" : DATA_CTL_B_N_BINARY <= 1'b0; + "TRUE" : DATA_CTL_B_N_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_CTL_B_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_B_N); + #1 $finish; + end + endcase + + case (DATA_CTL_C_N) + "FALSE" : DATA_CTL_C_N_BINARY <= 1'b0; + "TRUE" : DATA_CTL_C_N_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_CTL_C_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_C_N); + #1 $finish; + end + endcase + + case (DATA_CTL_D_N) + "FALSE" : DATA_CTL_D_N_BINARY <= 1'b0; + "TRUE" : DATA_CTL_D_N_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DATA_CTL_D_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_D_N); + #1 $finish; + end + endcase + + case (DISABLE_SEQ_MATCH) + "TRUE" : DISABLE_SEQ_MATCH_BINARY <= 1'b1; + "FALSE" : DISABLE_SEQ_MATCH_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_SEQ_MATCH on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DISABLE_SEQ_MATCH); + #1 $finish; + end + endcase + + case (MULTI_REGION) + "FALSE" : MULTI_REGION_BINARY <= 1'b0; + "TRUE" : MULTI_REGION_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MULTI_REGION on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MULTI_REGION); + #1 $finish; + end + endcase + + case (PHY_COUNT_ENABLE) + "FALSE" : PHY_COUNT_ENABLE_BINARY <= 1'b0; + "TRUE" : PHY_COUNT_ENABLE_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PHY_COUNT_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PHY_COUNT_ENABLE); + #1 $finish; + end + endcase + + SPARE_BINARY <= 1'b0; + + case (SYNC_MODE) + "TRUE" : SYNC_MODE_BINARY <= 1'b1; + "FALSE" : SYNC_MODE_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SYNC_MODE); + #1 $finish; + end + endcase + + if ((AO_TOGGLE >= 0) && (AO_TOGGLE <= 15)) + AO_TOGGLE_BINARY <= AO_TOGGLE; + else begin + $display("Attribute Syntax Error : The Attribute AO_TOGGLE on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, AO_TOGGLE); + #1 $finish; + end + + if ((AO_WRLVL_EN >= 4'b0000) && (AO_WRLVL_EN <= 4'b1111)) + AO_WRLVL_EN_BINARY <= AO_WRLVL_EN; + else begin + $display("Attribute Syntax Error : The Attribute AO_WRLVL_EN on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, AO_WRLVL_EN); + #1 $finish; + end + + if ((CMD_OFFSET >= 0) && (CMD_OFFSET <= 63)) + CMD_OFFSET_BINARY <= CMD_OFFSET; + else begin + $display("Attribute Syntax Error : The Attribute CMD_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, CMD_OFFSET); + #1 $finish; + end + + if ((CO_DURATION >= 0) && (CO_DURATION <= 7)) + CO_DURATION_BINARY <= CO_DURATION; + else begin + $display("Attribute Syntax Error : The Attribute CO_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, CO_DURATION); + #1 $finish; + end + + if ((DI_DURATION >= 0) && (DI_DURATION <= 7)) + DI_DURATION_BINARY <= DI_DURATION; + else begin + $display("Attribute Syntax Error : The Attribute DI_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DI_DURATION); + #1 $finish; + end + + if ((DO_DURATION >= 0) && (DO_DURATION <= 7)) + DO_DURATION_BINARY <= DO_DURATION; + else begin + $display("Attribute Syntax Error : The Attribute DO_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DO_DURATION); + #1 $finish; + end + + if ((EVENTS_DELAY >= 0) && (EVENTS_DELAY <= 63)) + EVENTS_DELAY_BINARY <= EVENTS_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute EVENTS_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, EVENTS_DELAY); + #1 $finish; + end + + if ((FOUR_WINDOW_CLOCKS >= 0) && (FOUR_WINDOW_CLOCKS <= 63)) + FOUR_WINDOW_CLOCKS_BINARY <= FOUR_WINDOW_CLOCKS; + else begin + $display("Attribute Syntax Error : The Attribute FOUR_WINDOW_CLOCKS on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FOUR_WINDOW_CLOCKS); + #1 $finish; + end + + if ((RD_CMD_OFFSET_0 >= 0) && (RD_CMD_OFFSET_0 <= 63)) + RD_CMD_OFFSET_0_BINARY <= RD_CMD_OFFSET_0; + else begin + $display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_0); + #1 $finish; + end + + if ((RD_CMD_OFFSET_1 >= 0) && (RD_CMD_OFFSET_1 <= 63)) + RD_CMD_OFFSET_1_BINARY <= RD_CMD_OFFSET_1; + else begin + $display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_1); + #1 $finish; + end + + if ((RD_CMD_OFFSET_2 >= 0) && (RD_CMD_OFFSET_2 <= 63)) + RD_CMD_OFFSET_2_BINARY <= RD_CMD_OFFSET_2; + else begin + $display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_2); + #1 $finish; + end + + if ((RD_CMD_OFFSET_3 >= 0) && (RD_CMD_OFFSET_3 <= 63)) + RD_CMD_OFFSET_3_BINARY <= RD_CMD_OFFSET_3; + else begin + $display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_3); + #1 $finish; + end + + if ((RD_DURATION_0 >= 0) && (RD_DURATION_0 <= 63)) + RD_DURATION_0_BINARY <= RD_DURATION_0; + else begin + $display("Attribute Syntax Error : The Attribute RD_DURATION_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_0); + #1 $finish; + end + + if ((RD_DURATION_1 >= 0) && (RD_DURATION_1 <= 63)) + RD_DURATION_1_BINARY <= RD_DURATION_1; + else begin + $display("Attribute Syntax Error : The Attribute RD_DURATION_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_1); + #1 $finish; + end + + if ((RD_DURATION_2 >= 0) && (RD_DURATION_2 <= 63)) + RD_DURATION_2_BINARY <= RD_DURATION_2; + else begin + $display("Attribute Syntax Error : The Attribute RD_DURATION_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_2); + #1 $finish; + end + + if ((RD_DURATION_3 >= 0) && (RD_DURATION_3 <= 63)) + RD_DURATION_3_BINARY <= RD_DURATION_3; + else begin + $display("Attribute Syntax Error : The Attribute RD_DURATION_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_3); + #1 $finish; + end + + if ((WR_CMD_OFFSET_0 >= 0) && (WR_CMD_OFFSET_0 <= 63)) + WR_CMD_OFFSET_0_BINARY <= WR_CMD_OFFSET_0; + else begin + $display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_0); + #1 $finish; + end + + if ((WR_CMD_OFFSET_1 >= 0) && (WR_CMD_OFFSET_1 <= 63)) + WR_CMD_OFFSET_1_BINARY <= WR_CMD_OFFSET_1; + else begin + $display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_1); + #1 $finish; + end + + if ((WR_CMD_OFFSET_2 >= 0) && (WR_CMD_OFFSET_2 <= 63)) + WR_CMD_OFFSET_2_BINARY <= WR_CMD_OFFSET_2; + else begin + $display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_2); + #1 $finish; + end + + if ((WR_CMD_OFFSET_3 >= 0) && (WR_CMD_OFFSET_3 <= 63)) + WR_CMD_OFFSET_3_BINARY <= WR_CMD_OFFSET_3; + else begin + $display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_3); + #1 $finish; + end + + if ((WR_DURATION_0 >= 0) && (WR_DURATION_0 <= 63)) + WR_DURATION_0_BINARY <= WR_DURATION_0; + else begin + $display("Attribute Syntax Error : The Attribute WR_DURATION_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_0); + #1 $finish; + end + + if ((WR_DURATION_1 >= 0) && (WR_DURATION_1 <= 63)) + WR_DURATION_1_BINARY <= WR_DURATION_1; + else begin + $display("Attribute Syntax Error : The Attribute WR_DURATION_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_1); + #1 $finish; + end + + if ((WR_DURATION_2 >= 0) && (WR_DURATION_2 <= 63)) + WR_DURATION_2_BINARY <= WR_DURATION_2; + else begin + $display("Attribute Syntax Error : The Attribute WR_DURATION_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_2); + #1 $finish; + end + + if ((WR_DURATION_3 >= 0) && (WR_DURATION_3 <= 63)) + WR_DURATION_3_BINARY <= WR_DURATION_3; + else begin + $display("Attribute Syntax Error : The Attribute WR_DURATION_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_3); + #1 $finish; + end + + end + + wire [15:0] delay_TESTOUTPUT; + wire [1:0] delay_INRANKA; + wire [1:0] delay_INRANKB; + wire [1:0] delay_INRANKC; + wire [1:0] delay_INRANKD; + wire [1:0] delay_PCENABLECALIB; + wire [3:0] delay_AUXOUTPUT; + wire [3:0] delay_INBURSTPENDING; + wire [3:0] delay_OUTBURSTPENDING; + wire delay_PHYCTLALMOSTFULL; + wire delay_PHYCTLEMPTY; + wire delay_PHYCTLFULL; + wire delay_PHYCTLREADY; + + wire [15:0] delay_TESTINPUT = 16'hffff; + wire [2:0] delay_TESTSELECT = 3'b111; + wire [31:0] delay_PHYCTLWD; + wire delay_MEMREFCLK; + wire delay_PHYCLK; + wire delay_PHYCTLMSTREMPTY; + wire delay_PHYCTLWRENABLE; + wire delay_PLLLOCK; + wire delay_READCALIBENABLE; + wire delay_REFDLLLOCK; + wire delay_RESET; + wire delay_SCANENABLEN = 1'b1; + wire delay_SYNCIN; + wire delay_WRITECALIBENABLE; + wire delay_GSR; + + assign #(out_delay) AUXOUTPUT = delay_AUXOUTPUT; + assign #(out_delay) INBURSTPENDING = delay_INBURSTPENDING; + assign #(out_delay) INRANKA = delay_INRANKA; + assign #(out_delay) INRANKB = delay_INRANKB; + assign #(out_delay) INRANKC = delay_INRANKC; + assign #(out_delay) INRANKD = delay_INRANKD; + assign #(out_delay) OUTBURSTPENDING = delay_OUTBURSTPENDING; + assign #(out_delay) PCENABLECALIB = delay_PCENABLECALIB; + assign #(out_delay) PHYCTLALMOSTFULL = delay_PHYCTLALMOSTFULL; + assign #(out_delay) PHYCTLEMPTY = delay_PHYCTLEMPTY; + assign #(out_delay) PHYCTLFULL = delay_PHYCTLFULL; + assign #(out_delay) PHYCTLREADY = delay_PHYCTLREADY; + +`ifndef XIL_TIMING + assign #(INCLK_DELAY) delay_MEMREFCLK = MEMREFCLK; + assign #(INCLK_DELAY) delay_PHYCLK = PHYCLK; + + assign #(in_delay) delay_PHYCTLMSTREMPTY = PHYCTLMSTREMPTY; + assign #(in_delay) delay_PHYCTLWD = PHYCTLWD; + assign #(in_delay) delay_PHYCTLWRENABLE = PHYCTLWRENABLE; +`endif + assign #(in_delay) delay_PLLLOCK = PLLLOCK; + assign #(in_delay) delay_READCALIBENABLE = READCALIBENABLE; + assign #(in_delay) delay_REFDLLLOCK = REFDLLLOCK; + assign #(in_delay) delay_RESET = RESET; +`ifndef XIL_TIMING + assign #(in_delay) delay_SYNCIN = SYNCIN; +`endif + assign #(in_delay) delay_WRITECALIBENABLE = WRITECALIBENABLE; + assign delay_GSR = GSR; + + SIP_PHY_CONTROL PHY_CONTROL_INST ( + .AO_TOGGLE (AO_TOGGLE_BINARY), + .AO_WRLVL_EN (AO_WRLVL_EN_BINARY), + .BURST_MODE (BURST_MODE_BINARY), + .CLK_RATIO (CLK_RATIO_BINARY), + .CMD_OFFSET (CMD_OFFSET_BINARY), + .CO_DURATION (CO_DURATION_BINARY), + .DATA_CTL_A_N (DATA_CTL_A_N_BINARY), + .DATA_CTL_B_N (DATA_CTL_B_N_BINARY), + .DATA_CTL_C_N (DATA_CTL_C_N_BINARY), + .DATA_CTL_D_N (DATA_CTL_D_N_BINARY), + .DISABLE_SEQ_MATCH (DISABLE_SEQ_MATCH_BINARY), + .DI_DURATION (DI_DURATION_BINARY), + .DO_DURATION (DO_DURATION_BINARY), + .EVENTS_DELAY (EVENTS_DELAY_BINARY), + .FOUR_WINDOW_CLOCKS (FOUR_WINDOW_CLOCKS_BINARY), + .MULTI_REGION (MULTI_REGION_BINARY), + .PHY_COUNT_ENABLE (PHY_COUNT_ENABLE_BINARY), + .RD_CMD_OFFSET_0 (RD_CMD_OFFSET_0_BINARY), + .RD_CMD_OFFSET_1 (RD_CMD_OFFSET_1_BINARY), + .RD_CMD_OFFSET_2 (RD_CMD_OFFSET_2_BINARY), + .RD_CMD_OFFSET_3 (RD_CMD_OFFSET_3_BINARY), + .RD_DURATION_0 (RD_DURATION_0_BINARY), + .RD_DURATION_1 (RD_DURATION_1_BINARY), + .RD_DURATION_2 (RD_DURATION_2_BINARY), + .RD_DURATION_3 (RD_DURATION_3_BINARY), + .SPARE (SPARE_BINARY), + .SYNC_MODE (SYNC_MODE_BINARY), + .WR_CMD_OFFSET_0 (WR_CMD_OFFSET_0_BINARY), + .WR_CMD_OFFSET_1 (WR_CMD_OFFSET_1_BINARY), + .WR_CMD_OFFSET_2 (WR_CMD_OFFSET_2_BINARY), + .WR_CMD_OFFSET_3 (WR_CMD_OFFSET_3_BINARY), + .WR_DURATION_0 (WR_DURATION_0_BINARY), + .WR_DURATION_1 (WR_DURATION_1_BINARY), + .WR_DURATION_2 (WR_DURATION_2_BINARY), + .WR_DURATION_3 (WR_DURATION_3_BINARY), + + .AUXOUTPUT (delay_AUXOUTPUT), + .INBURSTPENDING (delay_INBURSTPENDING), + .INRANKA (delay_INRANKA), + .INRANKB (delay_INRANKB), + .INRANKC (delay_INRANKC), + .INRANKD (delay_INRANKD), + .OUTBURSTPENDING (delay_OUTBURSTPENDING), + .PCENABLECALIB (delay_PCENABLECALIB), + .PHYCTLALMOSTFULL (delay_PHYCTLALMOSTFULL), + .PHYCTLEMPTY (delay_PHYCTLEMPTY), + .PHYCTLFULL (delay_PHYCTLFULL), + .PHYCTLREADY (delay_PHYCTLREADY), + .TESTOUTPUT (delay_TESTOUTPUT), + .MEMREFCLK (delay_MEMREFCLK), + .PHYCLK (delay_PHYCLK), + .PHYCTLMSTREMPTY (delay_PHYCTLMSTREMPTY), + .PHYCTLWD (delay_PHYCTLWD), + .PHYCTLWRENABLE (delay_PHYCTLWRENABLE), + .PLLLOCK (delay_PLLLOCK), + .READCALIBENABLE (delay_READCALIBENABLE), + .REFDLLLOCK (delay_REFDLLLOCK), + .RESET (delay_RESET), + .SCANENABLEN (delay_SCANENABLEN), + .SYNCIN (delay_SYNCIN), + .TESTINPUT (delay_TESTINPUT), + .TESTSELECT (delay_TESTSELECT), + .WRITECALIBENABLE (delay_WRITECALIBENABLE), + .GSR (delay_GSR) + ); + +`ifdef XIL_TIMING + specify + $period (negedge MEMREFCLK, 0:0:0, notifier); + $period (negedge PHYCLK, 0:0:0, notifier); + $period (posedge MEMREFCLK, 0:0:0, notifier); + $period (posedge PHYCLK, 0:0:0, notifier); + $setuphold (posedge MEMREFCLK, negedge PHYCTLMSTREMPTY, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_PHYCTLMSTREMPTY); + $setuphold (posedge MEMREFCLK, negedge SYNCIN, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_SYNCIN); + $setuphold (posedge MEMREFCLK, posedge PHYCTLMSTREMPTY, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_PHYCTLMSTREMPTY); + $setuphold (posedge MEMREFCLK, posedge SYNCIN, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_SYNCIN); + $setuphold (posedge PHYCLK, negedge PHYCTLWD, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWD); + $setuphold (posedge PHYCLK, negedge PHYCTLWRENABLE, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWRENABLE); + $setuphold (posedge PHYCLK, posedge PHYCTLWD, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWD); + $setuphold (posedge PHYCLK, posedge PHYCTLWRENABLE, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWRENABLE); + $width (negedge MEMREFCLK, 0:0:0, 0, notifier); + $width (negedge PHYCLK, 0:0:0, 0, notifier); + $width (negedge READCALIBENABLE, 0:0:0, 0, notifier); + $width (negedge RESET, 0:0:0, 0, notifier); + $width (negedge SYNCIN, 0:0:0, 0, notifier); + $width (negedge WRITECALIBENABLE, 0:0:0, 0, notifier); + $width (posedge MEMREFCLK, 0:0:0, 0, notifier); + $width (posedge PHYCLK, 0:0:0, 0, notifier); + $width (posedge READCALIBENABLE, 0:0:0, 0, notifier); + $width (posedge RESET, 0:0:0, 0, notifier); + $width (posedge SYNCIN, 0:0:0, 0, notifier); + $width (posedge WRITECALIBENABLE, 0:0:0, 0, notifier); + ( MEMREFCLK *> AUXOUTPUT) = (10:10:10, 10:10:10); + ( MEMREFCLK *> INBURSTPENDING) = (10:10:10, 10:10:10); + ( MEMREFCLK *> INRANKA) = (10:10:10, 10:10:10); + ( MEMREFCLK *> INRANKB) = (10:10:10, 10:10:10); + ( MEMREFCLK *> INRANKC) = (10:10:10, 10:10:10); + ( MEMREFCLK *> INRANKD) = (10:10:10, 10:10:10); + ( MEMREFCLK *> OUTBURSTPENDING) = (10:10:10, 10:10:10); + ( MEMREFCLK *> PCENABLECALIB) = (10:10:10, 10:10:10); + ( MEMREFCLK *> PHYCTLEMPTY) = (10:10:10, 10:10:10); + ( PHYCLK *> PHYCTLALMOSTFULL) = (10:10:10, 10:10:10); + ( PHYCLK *> PHYCTLFULL) = (10:10:10, 10:10:10); + ( PHYCLK *> PHYCTLREADY) = (10:10:10, 10:10:10); + + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule // PHY_CONTROL + +`endcelldefine diff --git a/verilog/src/unisims/PLLE2_ADV.v b/verilog/src/unisims/PLLE2_ADV.v new file mode 100644 index 0000000..c387706 --- /dev/null +++ b/verilog/src/unisims/PLLE2_ADV.v @@ -0,0 +1,3498 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Phase-Locked Loop (PLL) +// /___/ /\ Filename : PLLE2_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 12/09/09 - Initial version. +// 03/24/10 - Change CLKFBOUT_MULT defaut to 5, CLKIN_PERIOD range. +// 04/28/10 - Fix CLKIN1_PERIOD check (CR557962) +// 06/03/10 - Change DIVCLK_DIVIDE range to 56 according yaml. +// 07/12/10 - Add RST to LOCKED iopath (CR567807) +// 07/28/10 - Change ref parameter values (CR569262) +// 08/06/10 - Remove CASCADE from COMPENSATION (CR571190) +// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324) +// 09/03/10 - Change to bus timing. +// 09/26/10 - Add RST to LOCKED timing path (CR567807) +// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003) +// 03/03/11 - Keep 100ps dealy only on RST to LOCKED for unisim (CR595354) +// 05/05/11 - Update cp_res table (CR609232) +// 10/26/11 - Add DRC check for samples CLKIN period with parameter setting (CR631150) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 02/22/12 - Modify DRC (638094). +// 03/07/12 - added vcoflag (CR 638088, CR 636493) +// 04/19/12 - 654951 - rounding issue with clk_out_para_cal +// 05/03/12 - jittery clock (CR 652401) +// 05/03/12 - incorrect period (CR 654951) +// 06/11/12 - update cp and res settings (CR 664278) +// 06/20/12 - modify reset drc (CR 643540) +// 04/04/13 - change error to warning (CR 708090) +// 04/09/13 - Added DRP monitor (CR 695630). +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE2_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 19.000, + parameter real CLKPFD_FREQ_MAX = 550.0, + parameter real CLKPFD_FREQ_MIN = 19.0, + parameter real VCOCLK_FREQ_MAX = 2133.000, + parameter real VCOCLK_FREQ_MIN = 800.000, +`endif + parameter BANDWIDTH = "OPTIMIZED", + parameter integer CLKFBOUT_MULT = 5, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKIN2_PERIOD = 0.000, + parameter integer CLKOUT0_DIVIDE = 1, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter COMPENSATION = "ZHOLD", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter real REF_JITTER2 = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKOUT0, + output CLKOUT1, + output CLKOUT2, + output CLKOUT3, + output CLKOUT4, + output CLKOUT5, + output [15:0] DO, + output DRDY, + output LOCKED, + + input CLKFBIN, + input CLKIN1, + input CLKIN2, + input CLKINSEL, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 19.000; + localparam real CLKPFD_FREQ_MAX = 550.000; + localparam real CLKPFD_FREQ_MIN = 19.000; + localparam real VCOCLK_FREQ_MAX = 2133.000; + localparam real VCOCLK_FREQ_MIN = 800.000; +`endif + +// define constants + localparam MODULE_NAME = "PLLE2_ADV"; + + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_EXTERNAL = 2; + localparam COMPENSATION_INTERNAL = 3; + localparam COMPENSATION_ZHOLD = 0; + localparam [64:1] COMPENSATION_REG = COMPENSATION; + wire [1:0] COMPENSATION_BIN; + localparam VCOCLK_FREQ_TARGET = 1200; + localparam M_MIN = 2; + localparam M_MAX = 64; + localparam D_MIN = 1; + localparam D_MAX = 56; + localparam O_MIN = 1; + localparam O_MAX = 128; + localparam O_MAX_HT_LT = 64; + localparam REF_CLK_JITTER_MAX = 1000; + localparam REF_CLK_JITTER_SCALE = 0.1; + localparam MAX_FEEDBACK_DELAY = 10.0; + localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; + localparam PLL_LOCK_TIME = 7; + localparam ps_max = 55; + localparam OSC_P2 = 250; + localparam SIM_DEVICE = "E2"; + localparam CLKFBOUT_USE_FINE_PS = "FALSE"; + localparam CLKOUT0_USE_FINE_PS = "FALSE"; + localparam CLKOUT1_USE_FINE_PS = "FALSE"; + localparam CLKOUT2_USE_FINE_PS = "FALSE"; + localparam CLKOUT3_USE_FINE_PS = "FALSE"; + localparam CLKOUT4_CASCADE = "FALSE"; + localparam CLKOUT4_USE_FINE_PS = "FALSE"; + localparam CLKOUT5_USE_FINE_PS = "FALSE"; + localparam CLKOUT6_USE_FINE_PS = "FALSE"; + localparam integer CLKOUT6_DIVIDE = 1; + localparam real CLKOUT6_DUTY_CYCLE = 0.500; + localparam real CLKOUT6_PHASE = 0.000; + + tri0 GSR = glbl.GSR; + tri1 p_up; + wire glock; + + integer pchk_tmp1, pchk_tmp2; + reg PSCLK = 0, PSINCDEC = 0, PSEN = 0; + integer clkfb_div_frac_int, clk0_div_frac_int, clkfb_div_fint, clk0_div_fint; + integer clkfb_div_fint_tmp1, clkfb_div_fint_odd; + integer clk0_div_fint_tmp1, clk0_div_fint_odd; + real clkfb_div_frac, clk0_div_frac; + reg clk0_frac_out, clkfbm1_frac_out; + reg clk0_nf_out, clkfbm1_nf_out; + integer clk0_frac_en; + integer clkfb_frac_en; + integer ps_in_init; + reg psdone_out, psdone_out1; + integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en; + integer clk5_fps_en, clk6_fps_en, clkfb_fps_en, fps_en; + reg clkinstopped_out=0; + reg clkin_hold_f = 0; + reg simd_f = 1; + reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0; + integer period_avg_stpi = 0, period_avg_stp = 0; + real tmp_stp1, tmp_stp2; + reg pd_stp_p = 0; + reg vco_stp_f = 0; + reg psen_w = 0; + reg clkinstopped_out_dly = 0; + reg clkinstopped_out1 = 0; + reg clkfbstopped_out1 = 0; + reg clkfb_stop_tmp=0, clkfbstopped_out=0, clkin_stop_tmp=0; + reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; + reg rst_clkinstopped_rc = 0; + reg rst_clkinstopped_lk=0, rst_clkfbstopped_lk=0; + integer clkin_lost_cnt, clkfb_lost_cnt; + reg clkinstopped_hold = 0; + integer ps_in_ps, ps_cnt; + integer ps_in_ps_neg, ps_cnt_neg; + reg clkout_ps, clkout_ps_tmp1, clkout_ps_tmp2; + time clkout_ps_eg = 0; + time clkout_ps_peg = 0; + time clkout_ps_w = 0; + reg clkvco_ps_tmp1, clkvco_ps_tmp2; + reg clkvco_ps_tmp2_en; + integer clkout4_cascade_int; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drdy_out, drdy_out1; + reg drp_lock; + integer drp_lock_lat = 4; + integer drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [160:0] tmp_string; + reg rst_in=0; + reg pwron_int; + wire orig_rst_in,rst_in_o; + wire locked_out; + reg locked_out1; + reg locked_out_tmp; + wire clk0_out, clkfbm1_out; + reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out; + reg clkfb_out; + reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; + integer clkout_en_val, clkout_en_t; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + reg clkvco_lk_osc=0, clkvco=0, clkvco_lk_tmp=0, clkvco_lk_tmp_en=0; + reg clkvco_ps_tmp2_pg=0; + reg clkvco_lk_dly_tmp=0; + reg clkvco_lk_en=0; + reg clkvco_lk=0; + reg fbclk_tmp=0; + reg clk_osc=0, clkin_p=0, clkfb_p=0; + reg clkinstopped_vco_f=0; + time rst_edge, rst_ht; + reg fb_delay_found, fb_delay_found_tmp; + reg clkfb_tst = 1'b0; + real fb_delay_max; + time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay, fbm1_comp_delay_tmp; + time dly_tmp1, tmp_ps_val2; + integer dly_tmp_int, tmp_ps_val1; + time clkin_edge, delay_edge; + real period_clkin, clkin_period_tmp; + integer clkin_period_tmp_t; + integer clkin_period [4:0]; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + integer period_vco_half_rm1, period_vco_half_rm2; + real cmpvco = 0.0; + real clkvco_pdrm; + integer period_vco_mf; + integer period_vco_tmp; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco_max, period_vco_min; + integer period_vco1, period_vco2, period_vco3, period_vco4; + integer period_vco5, period_vco6, period_vco7; + integer period_vco_target, period_vco_target_half; + integer period_fb, period_avg; + integer clk0_frac_lt, clk0_frac_ht; + integer clkfb_frac_lt, clkfb_frac_ht; + integer period_ps, period_ps_old; + reg ps_lock, ps_lock_dly; + real clkvco_freq_init_chk, clkfbm1pm_rl; + real tmp_real; + integer ik0, ik1, ik2, ik3, ik4, ib, i, j; + integer md_product, m_product, m_product2, clkin_stop_max, clkfb_stop_max; + integer mf_product, clk0f_product; + integer clkin_lost_val, clkfb_lost_val, clkin_lost_val_lk; + time pll_locked_delay, clkin_dly_t, clkfb_dly_t; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2, pll_locked_tmp2_dly; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock; + integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + wire init_trig, clkpll_r, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clk6in; + reg clkpll_tmp1, clkpll; + wire clkfbm1in, clkfbm1ps_en; + reg chk_ok; + wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en; + reg [7:0] clkout_mux, clkout_ps_mux; + reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel; + wire [2:0] clk0pm_sel1, clk5pm_sel1, clk6pm_sel1, clkfbm1pm_sel1; + reg [2:0] clk6pm_sel, clkfbm1pm_sel; + integer clk0pm_sel_int, clkfbm1pm_sel_int; + reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge, clk6_edge; + reg clkfbm1_edge, clkfbm2_edge, clkind_edge; + reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt; + reg clk6_nocnt, clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt; + reg clkfbtmp_nocnti; + reg clkind_edgei, clkind_nocnti; + reg [5:0] clk0_dly_cnt, clkout0_dly; + reg [5:0] clk1_dly_cnt, clkout1_dly; + reg [5:0] clk2_dly_cnt, clkout2_dly; + reg [5:0] clk3_dly_cnt, clkout3_dly; + reg [5:0] clk4_dly_cnt, clkout4_dly; + reg [5:0] clk5_dly_cnt, clkout5_dly; + reg [5:0] clk6_dly_cnt, clkout6_dly; + reg [6:0] clk0_ht, clk0_lt; + reg [6:0] clk1_ht, clk1_lt; + reg [6:0] clk2_ht, clk2_lt; + reg [6:0] clk3_ht, clk3_lt; + reg [6:0] clk4_ht, clk4_lt; + reg [6:0] clk5_ht, clk5_lt; + reg [6:0] clk6_ht, clk6_lt; + reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; + reg [6:0] clkfbm1_ht, clkfbm1_lt; + reg [6:0] clkfbm2_ht, clkfbm2_lt; + reg [7:0] clkind_ht, clkind_lt; + reg [7:0] clkind_hti, clkind_lti; + reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; + reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; + reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1; + reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1; + reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1; + reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1; + reg [7:0] clk6_ht1, clk6_cnt, clk6_div, clk6_div1; + reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; + real clkfbm1_f_div, clkfbm1_div_t; + integer clkfbm1_div_t_int; + reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti; + reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1; + reg [7:0] clkind_div, clkind_divi, clkind_div1, clkind_cnt, clkind_ht1; + reg clkind_out, clkind_out_tmp; + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + wire clkinsel_tmp; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + reg init_chk; + reg rst_clkinsel_flag = 0; + reg clkout0_out, clkout1_out, clkout2_out, clkout3_out, clkout4_out; + reg clkout5_out, clkout6_out; + reg clkfbm2_out, clkfbm2_out_tmp, clk6_out; + reg notifier; + wire [15:0] do_out, di_in; + reg [15:0] do_out1; + wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in; + wire clkinsel_in1; + wire psen_in, psclk_in, psincdec_in, pwrdwn_in; + wire pwrdwn_in1; + reg pwrdwn_in1_h = 0; + reg rst_input_r_h = 0; + reg pchk_clr = 0; + reg psincdec_chg = 0; + reg psincdec_chg_tmp = 0; + wire [6:0] daddr_in; + wire rst_input; + wire rst_input_r; + reg startup_wait_sig; + wire delay_PSINCDEC, delay_PSEN, delay_PSCLK, delay_DCLK, delay_DWE; + wire delay_DEN; + wire [15:0] delay_DI; + wire [6:0] delay_DADDR; + wire clkfbin_sel; + reg vcoflag = 0; + + reg [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED; + reg [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + + wire PSDONE; + wire CLKINSTOPPED; + wire CLKFBSTOPPED; + + `ifndef XIL_TIMING + assign CLKINSTOPPED = clkinstopped_out1; + assign CLKFBSTOPPED = clkfbstopped_out1; + assign clkin1_in = CLKIN1; + assign clkin2_in = CLKIN2; + assign clkfb_in = CLKFBIN; + assign clkinsel_in = ((CLKINSEL === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG; + assign rst_input_r = RST ^ IS_RST_INVERTED_REG; + assign daddr_in = DADDR; + assign di_in = DI; + assign dwe_in = DWE; + assign den_in = DEN; + assign dclk_in = DCLK; + assign psclk_in = PSCLK; + assign psen_in = PSEN; + assign psincdec_in = PSINCDEC; + assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_REG; + assign LOCKED = locked_out1; + assign DRDY = drdy_out1; + assign DO = do_out1; + assign PSDONE = psdone_out1; + + //drp monitor + reg den_r1 = 1'b0; + reg den_r2 = 1'b0; + reg dwe_r1 = 1'b0; + reg dwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge dclk_in) + begin + // pipeline the DEN and DWE + den_r1 <= den_in; + dwe_r1 <= dwe_in; + den_r2 <= den_r1; + dwe_r2 <= dwe_r1; + + + // Check - if DEN or DWE is more than 1 DCLK + if ((den_r1 == 1'b1) && (den_r2 == 1'b1)) + begin + $display("DRC Error : DEN is high for more than 1 DCLK on %m instance"); + $finish; + end + + if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1)) + begin + $display("DRC Error : DWE is high for more than 1 DCLK on %m instance"); + $finish; + end + + + //After the 1st DEN pulse, check the DEN and DRDY. + case (sfsm) + FSM_IDLE: + begin + if(den_in == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DEN, 4 cases can happen + // DEN DRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(den_in === 1'b1 && drdy_out === 1'b0) + begin + $display("DRC Error : DEN is enabled before DRDY returns on %m instance"); + $finish; + end + + //Add the check for another DWE pulse + if ((dwe_in === 1'b1) && (den_in === 1'b0)) + begin + $display("DRC Error : DWE is enabled before DRDY returns on %m instance"); + $finish; + end + + if ((drdy_out === 1'b1) && (den_in === 1'b0)) + begin + sfsm <= FSM_IDLE; + end + + if ((drdy_out === 1'b1) && (den_in === 1'b1)) + begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge DCLK) + //end drp monitor + + + always @(locked_out_tmp) + locked_out1 = locked_out_tmp; + always @(pll_locked_tmp2) + pll_locked_tmp2_dly = pll_locked_tmp2; + always @(drdy_out) + drdy_out1 = drdy_out; + always @(do_out) + do_out1 = do_out; + always @(psdone_out) + psdone_out1 = psdone_out; + `endif // `ifndef XIL_TIMING + + `ifdef XIL_TIMING + buf b_LOCK (LOCKED, locked_out_tmp); + buf b_DRDY (DRDY, drdy_out); + buf b_DO[15:0] (DO, do_out); + buf b_PSDONE (PSDONE, psdone_out); + buf b_CLKIN1 (clkin1_in, CLKIN1); + buf b_CLKIN2 (clkin2_in, CLKIN2); + buf b_CLKSRC (clkinsel_in1, CLKINSEL); + assign clkinsel_in = ((clkinsel_in1 === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG; + buf b_CLKFB (clkfb_in, CLKFBIN); + buf b_RST (rst_input_r, RST ^ IS_RST_INVERTED_REG); + buf b_DADDR[6:0] (daddr_in, delay_DADDR); + buf b_DI[15:0] (di_in, delay_DI); + buf b_DWE (dwe_in, delay_DWE); + buf b_DEN (den_in, delay_DEN); + buf b_DCLK (dclk_in, delay_DCLK); + buf b_CLKINSTOPPED (CLKINSTOPPED, clkinstopped_out1); + buf b_CLKFBSTOPPED ( CLKFBSTOPPED, clkfbstopped_out1); + buf b_PSEN (psen_in, delay_PSEN); + buf b_PSINCDEC (psincdec_in, delay_PSINCDEC); + buf b_PSCLK (psclk_in, delay_PSCLK); + buf b_PWRDWN (pwrdwn_in, PWRDWN ^ IS_PWRDWN_INVERTED_REG); + always @(pll_locked_tmp2) + pll_locked_tmp2_dly = pll_locked_tmp2; + `endif // `ifdef XIL_TIMING + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + COMPENSATION_ZHOLD; + + initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the PLLE2_ADV, the simulator resolution must be set to 1ps or smaller."); + #1 $finish; + end + end + + initial begin + case (STARTUP_WAIT) + "FALSE" : startup_wait_sig = 0; + "TRUE" : startup_wait_sig = 1; + default : begin + $display("Attribute Syntax Error : The Attribute STARTUP_WAIT on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", STARTUP_WAIT); + #1 $finish; + end + endcase + + case (BANDWIDTH) + "OPTIMIZED" : ; + "HIGH" : ; + "LOW" : ; + default : begin + $display("Attribute Syntax Error : The Attribute BANDWIDTH on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are OPTIMIZED, HIGH, or LOW.", BANDWIDTH); + #1 $finish; + end + endcase + + case (CLKFBOUT_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKFBOUT_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT0_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT0_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT1_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT1_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT2_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT2_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT3_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT3_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT4_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT5_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT5_USE_FINE_PS); + #1 $finish; + end + endcase + + case (CLKOUT6_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT6_USE_FINE_PS); + #1 $finish; + end + endcase + + clkin_hold_f = 0; + +// case (CLOCK_HOLD) +// "FALSE" : clkin_hold_f = 0; +// "TRUE" : clkin_hold_f = 1; +// default : begin +// $display("Attribute Syntax Error : The Attribute CLOCK_HOLD on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLOCK_HOLD); +// $finish; +// end +// endcase + + case (CLKOUT4_CASCADE) + "FALSE" : clkout4_cascade_int = 0; + "TRUE" : clkout4_cascade_int = 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT4_CASCADE on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_CASCADE); + #1 $finish; + end + endcase + + case (COMPENSATION) + "ZHOLD" : ; + "BUF_IN" : ; + "EXTERNAL" : ; + "INTERNAL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute COMPENSATION on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL, or INTERNAL.", COMPENSATION); + #1 $finish; + end + endcase + + clkfbm1_f_div = CLKFBOUT_MULT * 1.0; + clkfb_div_fint = CLKFBOUT_MULT; + clkfb_div_frac = 0.000; + clkfb_frac_en = 0; + clkfb_div_frac_int = 0; +// mf_product = clkfb_div_fint * 8 + clkfb_div_frac_int; + clk0_div_fint = CLKOUT0_DIVIDE; + clk0_div_frac = 0.000; + clk0_frac_en = 0; + clk0_div_frac_int = 0; + ps_in_init = 0; + ps_in_ps = ps_in_init; + ps_cnt = 0; + + if (CLKFBOUT_USE_FINE_PS == "TRUE") begin + if (clkfb_frac_en == 1) begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_USE_FINE_PS); + #1 $finish; + end + else + clkfb_fps_en = 1; + end + else + clkfb_fps_en = 0; + + if (CLKOUT0_USE_FINE_PS == "TRUE") begin + if (clk0_frac_en == 1) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_USE_FINE_PS); + #1 $finish; + end + else + clk0_fps_en = 1; + end + else + clk0_fps_en = 0; + + if (CLKOUT1_USE_FINE_PS == "TRUE") + clk1_fps_en = 1; + else + clk1_fps_en = 0; + + if (CLKOUT2_USE_FINE_PS == "TRUE") + clk2_fps_en = 1; + else + clk2_fps_en = 0; + + if (CLKOUT3_USE_FINE_PS == "TRUE") + clk3_fps_en = 1; + else + clk3_fps_en = 0; + + if (CLKOUT4_USE_FINE_PS == "TRUE") + clk4_fps_en = 1; + else + clk4_fps_en = 0; + + if (CLKOUT5_USE_FINE_PS == "TRUE") + clk5_fps_en = 1; + else + clk5_fps_en = 0; + + if (CLKOUT6_USE_FINE_PS == "TRUE") + clk6_fps_en = 1; + else + clk6_fps_en = 0; + + + fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en + || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfb_fps_en; + + tmp_string = "CLKOUT0_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT0_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT0_PHASE"; + if (clk0_frac_en == 0) + chk_ok = para_real_range_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0); + else + if (CLKOUT0_PHASE != 0.0) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_PHASE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_PHASE); + #1 $finish; + end + tmp_string = "CLKOUT0_DUTY_CYCLE"; + if (clk0_frac_en == 0) + chk_ok = para_real_range_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.001, 0.999); + else + if (CLKOUT0_DUTY_CYCLE != 0.5) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_DUTY_CYCLE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_DUTY_CYCLE); + #1 $finish; + end + tmp_string = "CLKOUT1_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT1_PHASE"; + chk_ok = para_real_range_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT2_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT2_PHASE"; + chk_ok = para_real_range_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT3_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT3_PHASE"; + chk_ok = para_real_range_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT4_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT4_PHASE"; + chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.001, 0.999); + if (clk0_frac_en == 0) begin + tmp_string = "CLKOUT5_DIVIDE"; + chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT5_PHASE"; + chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.001, 0.999); + end + if (clkfb_frac_en == 0) begin + tmp_string = "CLKOUT6_DIVIDE"; + chk_ok = para_int_range_chk (CLKOUT6_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT6_PHASE"; + chk_ok = para_real_range_chk(CLKOUT6_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = para_real_range_chk (CLKOUT6_DUTY_CYCLE, tmp_string, 0.001, 0.999); + end + tmp_string = "CLKFBOUT_MULT"; + chk_ok = para_real_range_chk(CLKFBOUT_MULT, tmp_string, 2, 64); + tmp_string = "CLKFBOUT_PHASE"; + if (clkfb_frac_en == 0) + chk_ok = para_real_range_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0); + else + if (CLKFBOUT_PHASE != 0.0) begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_PHASE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_PHASE); + #1 $finish; + end + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, D_MAX); + tmp_string = "REF_JITTER1"; + chk_ok = para_real_range_chk (REF_JITTER1, tmp_string, 0.000, 0.999); + tmp_string = "REF_JITTER2"; + chk_ok = para_real_range_chk (REF_JITTER2, tmp_string, 0.000, 0.999); + +// if (BANDWIDTH === "LOW") + pll_lfhf = 2'b00; +// else +// pll_lfhf = 2'b00; + + if (BANDWIDTH === "LOW") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end + 3 : begin pll_cp = 4'b0010; pll_res = 4'b0111; end + 4 : begin pll_cp = 4'b0010; pll_res = 4'b1101; end + 5 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end + 6 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end + 7 : begin pll_cp = 4'b0010; pll_res = 4'b1001; end + 8 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end + 9 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end + 10 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end + 11 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end + 12 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end + 13 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end + 14 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end + 15 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end + 16 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end + 17 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end + 18 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end + 19 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end + 20 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 21 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 22 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 23 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 25 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 27 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 28 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 29 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 30 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 31 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 32 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 33 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 34 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 35 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 36 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 37 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 38 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 39 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 40 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end + 41 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 42 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 43 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 44 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 45 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 46 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 47 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end + 48 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 49 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 50 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 51 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 52 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 53 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 54 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 55 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 56 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 57 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 58 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 59 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 60 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + endcase + else if (BANDWIDTH === "HIGH") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end + 2 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end + 3 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end + 4 : begin pll_cp = 4'b0111; pll_res = 4'b1111; end + 5 : begin pll_cp = 4'b0111; pll_res = 4'b1011; end + 6 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end + 7 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end + 8 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end + 9 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 10 : begin pll_cp = 4'b1111; pll_res = 4'b0111; end + 11 : begin pll_cp = 4'b1111; pll_res = 4'b1011; end + 12 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end + 14 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 19 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 20 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 21 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 22 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 27 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 28 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 29 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 30 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 31 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 32 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 33 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 34 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 35 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 36 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 37 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 38 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 39 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 41 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 47 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 48 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 49 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 50 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 51 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 52 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 53 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 54 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 55 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 56 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 57 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 58 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 59 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 60 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + endcase + else if (BANDWIDTH === "OPTIMIZED") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end + 2 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end + 3 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end + 4 : begin pll_cp = 4'b0111; pll_res = 4'b1111; end + 5 : begin pll_cp = 4'b0111; pll_res = 4'b1011; end + 6 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end + 7 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end + 8 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end + 9 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 10 : begin pll_cp = 4'b1111; pll_res = 4'b0111; end + 11 : begin pll_cp = 4'b1111; pll_res = 4'b1011; end + 12 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end + 14 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end + 19 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 20 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 21 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 22 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end + 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 27 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 28 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 29 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 30 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 31 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 32 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 33 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end + 34 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 35 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 36 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end + 37 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 38 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 39 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end + 41 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 47 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 48 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 49 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 50 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 51 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 52 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 53 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 54 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 55 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 56 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 57 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 58 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 59 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 60 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end + 61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + endcase + + case (clkfb_div_fint) + 1 : begin drp_lock_ref_dly = 5'b00110; + drp_lock_fb_dly = 5'b00110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 2 : begin drp_lock_ref_dly = 5'b00110; + drp_lock_fb_dly = 5'b00110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 3 : begin drp_lock_ref_dly = 5'b01000; + drp_lock_fb_dly = 5'b01000; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 4 : begin drp_lock_ref_dly = 5'b01011; + drp_lock_fb_dly = 5'b01011; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 5 : begin drp_lock_ref_dly = 5'b01110; + drp_lock_fb_dly = 5'b01110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 6 : begin drp_lock_ref_dly = 5'b10001; + drp_lock_fb_dly = 5'b10001; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 7 : begin drp_lock_ref_dly = 5'b10011; + drp_lock_fb_dly = 5'b10011; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 8 : begin drp_lock_ref_dly = 5'b10110; + drp_lock_fb_dly = 5'b10110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 9 : begin drp_lock_ref_dly = 5'b11001; + drp_lock_fb_dly = 5'b11001; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 10 : begin drp_lock_ref_dly = 5'b11100; + drp_lock_fb_dly = 5'b11100; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 11 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1110000100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 12 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1100111001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 13 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1011101110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 14 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1010111100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 15 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1010001010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 16 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1001110001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 17 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000111111; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 18 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000100110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 19 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000001101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 20 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111110100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 21 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111011011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 22 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111000010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 23 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110101001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 24 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110010000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 25 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110010000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 26 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101110111; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 27 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101011110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 28 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101011110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 29 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101000101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 30 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101000101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 31 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 32 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 33 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 34 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 35 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 36 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 37 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 38 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 39 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 40 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 41 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 42 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 43 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 44 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 45 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 46 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 47 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 48 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 49 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 50 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 51 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 52 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 53 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 54 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 55 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 56 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 57 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 58 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 59 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 60 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 61 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 62 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 63 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 64 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + endcase + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX); + if(clkfb_frac_en == 0) begin + tmp_string = "CLKFBOUT_MULT"; + chk_ok = para_int_range_chk (CLKFBOUT_MULT, tmp_string, M_MIN, M_MAX); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, tmp_string); + end + if(clk0_frac_en == 0) begin + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string); + end + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string); + period_vco_max = 1000000 / VCOCLK_FREQ_MIN; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + clk0f_product = CLKOUT0_DIVIDE * 8; + pll_lock_time = 12; + lock_period_time = 10; + if (clkfb_frac_en == 1) begin + md_product = clkfb_div_fint * DIVCLK_DIVIDE; + m_product = clkfb_div_fint; + mf_product = CLKFBOUT_MULT * 8; + clkout_en_val = mf_product - 2; + m_product2 = clkfb_div_fint / 2; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + md_product = clkfb_div_fint * DIVCLK_DIVIDE; + m_product = clkfb_div_fint; + mf_product = CLKFBOUT_MULT * 8; + m_product2 = clkfb_div_fint / 2; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + clkfb_stop_max = 3; + clkin_stop_max = DIVCLK_DIVIDE + 1; + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE); + clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE); + clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE); + clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE); + clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50); + tmp_string = "CLKOUT1_PHASE"; + clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string); + tmp_string = "CLKOUT2_PHASE"; + clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string); + tmp_string = "CLKOUT3_PHASE"; + clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string); + tmp_string = "CLKOUT4_PHASE"; + clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string); + if (clkfb_frac_en == 1) begin + clkfbm1_dly = clkfb_div_fint /2; + clkout6_dly = clkfb_div_fint /2; + if (clkfb_div_fint_odd > 0) begin + clk6pm_sel = (8 + clkfb_div_frac_int) / 2; + clkfbm1pm_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ; + clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ; + end + else begin + clkfbm1pm_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2; + clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2; + clk6pm_sel = clkfb_div_frac_int / 2; + end + end + else begin + tmp_string = "CLKOUT6_PHASE"; + clkout_dly_cal (clkout6_dly, clk6pm_sel, CLKOUT6_DIVIDE, CLKOUT6_PHASE, tmp_string); + tmp_string = "CLKFBOUT_PHASE"; + clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, clkfb_div_fint, CLKFBOUT_PHASE, tmp_string); + end + if (clk0_frac_en == 1) begin + clkout0_dly = clk0_div_fint /2; + clkout5_dly = clk0_div_fint /2; + if (clk0_div_fint_odd > 0) begin + clk5pm_sel = (8 + clk0_div_frac_int) / 2; + clk0pm_sel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2; + clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2; + end + else begin + clk0pm_sel = clk0_div_frac_int - clk0_div_frac_int / 2; + clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2; + clk5pm_sel = clk0_div_frac_int / 2; + end + end + else begin + tmp_string = "CLKOUT0_PHASE"; + clkout_dly_cal (clkout0_dly, clk0pm_sel, clk0_div_fint, CLKOUT0_PHASE, tmp_string); + tmp_string = "CLKOUT5_PHASE"; + clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string); + end + if (clk0_frac_en == 1) begin + end + else begin + clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, clk0_div_fint, CLKOUT0_DUTY_CYCLE); + clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE); + end + if (clkfb_frac_en == 1) begin + end + else begin + clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50); + clk_out_para_cal (clk6_ht, clk6_lt, clk6_nocnt, clk6_edge, CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE); + end + clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, 1, 0.50); + clkind_div = DIVCLK_DIVIDE; + + dr_sram[6] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[7] = {5'bx, 3'b0, clk5_edge, clk5_nocnt, clkout5_dly[5:0]}; + dr_sram[8] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; + dr_sram[10] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {6'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; + dr_sram[12] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[13] = {6'bx, 2'b0, clk2_edge, clk2_nocnt, clkout2_dly[5:0]}; + dr_sram[14] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[15] = {6'bx, 2'b0, clk3_edge, clk3_nocnt, clkout3_dly[5:0]}; + dr_sram[16] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[17] = {5'bx, 3'b0, clk4_edge, clk4_nocnt, clkout4_dly[5:0]}; + dr_sram[18] = {clk6pm_sel[2:0], 1'b1, clk6_ht[5:0], clk6_lt[5:0]}; + dr_sram[19] = {6'bx, 2'b0, clk6_edge, clk6_nocnt, clkout6_dly[5:0]}; + dr_sram[20] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; + dr_sram[21] = {1'bx, 7'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; + dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + dr_sram[116] = {5'bx, 6'b0, 5'b00001}; + end + + initial begin + clkpll_jitter_unlock = 0; + clkinstopped_vco_f = 0; + rst_clkfbstopped = 0; + rst_clkinstopped = 0; + rst_clkfbstopped_lk = 0; + rst_clkinstopped_lk = 0; + clkfb_stop_tmp = 0; + clkin_stop_tmp = 0; + clkout_ps = 0; + clkout_ps_tmp1 = 0; + clkout_ps_tmp2 = 0; + clkvco_ps_tmp1 = 0; + clkvco_ps_tmp2 = 0; + clkvco_ps_tmp2_en = 0; + clkvco_lk_osc = 0; + clkvco_lk_en = 0; + clkvco_lk_tmp = 0; + clkvco_lk_dly_tmp = 0; + clk_osc = 0; + clkin_p = 0; + clkfb_p = 0; + clkind_edgei = 0; + clkind_nocnti = 0; + clkind_hti = 0; + clkind_lti = 0; + clkind_divi = 1; + ps_lock = 0; + ps_lock_dly = 0; + psdone_out = 0; + psdone_out1 = 0; + rst_in = 0; + clkinstopped_out = 0; + clkfbstopped_out = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_period_tmp_t = 0; + period_avg = 0; + period_fb = 0; + clkin_lost_val = 500; + clkfb_lost_val = 500; + clkin_lost_val_lk = 500; + fb_delay = 0; + clkfbm1_div = 1; + clkfbm2_div = 1; + clkfbm1_div1 = 0; + clkfbm2_div1 = 0; + clkvco_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fbm1_comp_delay = 0; + clkfbm1pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + period_ps = 0; + period_ps_old = 0; + clkfb_frac_ht = 0; + clkfb_frac_lt = 0; + clk0_frac_ht = 0; + clk0_frac_lt = 0; + clkvco_rm_cnt = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + fbclk_tmp = 0; + clkfb_tst = 1'b0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tmp2_dly = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + clkout_mux = 8'b0; + clkout_ps_mux = 8'b0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + drdy_out = 0; + drdy_out1 = 0; + locked_out1 = 0; + locked_out_tmp = 0; + do_out1 = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 0; + clkout0_out = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clk6_dly_cnt = 6'b0; + clkfbm1_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clk6_cnt = 8'b0; + clkfbm1_cnt = 8'b0; + clkfbm2_cnt = 8'b0; + clkind_cnt = 8'b0; + clkout0_out = 0; + clkout1_out = 0; + clkout2_out = 0; + clkout3_out = 0; + clkout4_out = 0; + clkout5_out = 0; + clkout6_out = 0; + clk0_nf_out = 0; + clk0_frac_out = 0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clk6_out = 0; + clkfb_out = 0; + clkfbm1_nf_out = 0; + clkfbm1_frac_out = 0; + clkfbm2_out = 0; + clkfbm2_out_tmp = 0; + clkind_out = 0; + clkind_out_tmp = 0; + clk_osc = 0; + clkin_p = 0; + clkfb_p = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + +// assign CLKOUT6 = clkout6_out; + wire CLKOUT3B; + wire CLKOUT2B; + wire CLKOUT1B; + wire CLKOUT0B; + wire CLKFBOUTB; + assign CLKOUT5 = clkout5_out; + assign CLKOUT4 = clkout4_out; + assign CLKOUT3 = clkout3_out; + assign CLKOUT2 = clkout2_out; + assign CLKOUT1 = clkout1_out; + assign CLKOUT0 = clkout0_out; + assign CLKFBOUT = clkfb_out; + assign CLKOUT3B = ~clkout3_out; + assign CLKOUT2B = ~clkout2_out; + assign CLKOUT1B = ~clkout1_out; + assign CLKOUT0B = ~clkout0_out; + assign CLKFBOUTB = ~clkfb_out; + + assign #1 clkinsel_tmp = clkinsel_in; + + assign glock = (startup_wait_sig) ? locked_out_tmp : 1; + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + + initial begin + init_chk = 0; + #2; + init_chk = 1; + end + + always @(clkinsel_in or posedge init_chk ) begin + if ($time > 2 && rst_in === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Input Error : Input clock can only be switched when RST=1. CLKINSEL on PLLE2_ADV instance %m at time %t changed when RST low, which should change at RST high.", $time); + $finish; + end + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (clkinsel_in === 1 && $time > 1 || clkinsel_in !== 0 && init_chk == 1) begin + if (CLKIN1_PERIOD > clkin_chk_t1 || CLKIN1_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, clkin_chk_t2, clkin_chk_t1); + + $finish; + end + end + else if (clkinsel_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin + if (CLKIN2_PERIOD > clkin_chk_t1 || CLKIN2_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, clkin_chk_t2, clkin_chk_t1); + $finish; + end + end + period_clkin = (clkinsel_in === 0) ? CLKIN2_PERIOD : CLKIN1_PERIOD; + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT) / (period_clkin * DIVCLK_DIVIDE); + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + end + end + + assign init_trig = 1; + assign clkpll_r = (clkinsel_in) ? clkin1_in : clkin2_in; + assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0; + assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkpll_r or posedge rst_input) + if (rst_input) + rst_in <= 1; + else + rst_in <= rst_input ; + + assign rst_in_o = (rst_in || rst_clkfbstopped || rst_clkinstopped); + +//simprim_rst_h + always @(posedge pwrdwn_in1 or posedge pchk_clr) + if (pwrdwn_in1) + pwrdwn_in1_h <= 1; + else if (pchk_clr) + pwrdwn_in1_h <= 0; + + always @(posedge rst_input_r or posedge pchk_clr) + if (rst_input_r) + rst_input_r_h <= 1; + else if (pchk_clr) + rst_input_r_h <= 0; + + + always @(rst_input ) + if (rst_input==1) begin + rst_edge = $time; + pchk_clr = 0; + end + else if (rst_input==0 && rst_edge > 1) begin + rst_ht = $time - rst_edge; + if (rst_ht < 1500) begin + if (rst_input_r_h == 1 && pwrdwn_in1_h == 1) + $display("Input Error : RST and PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time); + else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0) + $display("Input Error : RST on instance %m at time %t must be asserted at least for 1.5 ns.", $time); + else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1) + $display("Input Error : PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time); + end + pchk_clr = 1; + end +//endsimprim_rst_h + + // + // DRP port read and write + // + + assign do_out = dr_sram[daddr_lat]; + + always @(posedge dclk_in or posedge GSR) + if (GSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 0; + end else begin + if (den_in == 1) begin + valid_daddr = addr_is_valid(daddr_in); + if (drp_lock == 1) begin + //$display(" Warning : DEN is high at PLLE2_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time); + end else begin + drp_lock <= 1; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + daddr_lat <= daddr_in; + end + if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 || + daddr_in == 7'b1001110 || daddr_in == 7'b0101000 || + (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || + (daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin + end + else begin + $display(" Warning : Address DADDR=%b is unsupported at PLLE2_ADV instance %m at time %t. ", DADDR, $time); + end + + if (dwe_in == 1) begin // write process + if (rst_input == 1) begin + if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 || + daddr_in == 7'b1001110 || daddr_in == 7'b0101000 || + (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || + (daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin + dr_sram[daddr_in] <= di_in; + end + if (daddr_in == 7'b0001001) // 9 + clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); + if (daddr_in == 7'b0001000) // 8 + clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001011) // 11 + clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); + if (daddr_in == 7'b0001010) // 10 + clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001101) // 13 + clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in); + if (daddr_in == 7'b0001100) // 12 + clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001111) // 15 + clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in); + if (daddr_in == 7'b0001110) // 14 + clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010001) // 17 + clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in); + if (daddr_in == 7'b0010000) // 16 + clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010011) // 19 + clkout_delay_para_drp (clkout6_dly, clk6_nocnt, clk6_edge, di_in, daddr_in); + if (daddr_in == 7'b0010010) // 18 + clkout_hl_para_drp (clk6_lt, clk6_ht, clk6pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0000111) // 7 + clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in); + if (daddr_in == 7'b0000110) // 6 + clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010101) begin // 21 + clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); + clkfbtmp_nocnti = di_in[12]; + end + if (daddr_in == 7'b0010100) begin // 20 + clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in); + clkfbtmp_lti = {2'b00, di_in[5:0]}; + clkfbtmp_hti = {2'b00, di_in[11:6]}; + if (clkfbtmp_nocnti == 1) + clkfbtmp_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkfbtmp_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkfbtmp_divi = 64 + clkfbtmp_hti; + else if (di_in[11:6] == 6'b0) + clkfbtmp_divi = 64 + clkfbtmp_lti; + else + clkfbtmp_divi = clkfbtmp_hti + clkfbtmp_lti; + if (SIM_DEVICE == "VIRTEX6") begin + if (clkfbtmp_divi > 64 || (clkfbtmp_divi < 5)) + $display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %b and over the range of %d to %d.", daddr_in, di_in, $time, clkfbtmp_divi, 5, 64); + end + else begin + if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN)) + $display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d.", daddr_in, di_in, $time, clkfbtmp_divi, M_MIN, M_MAX); + end + end + + if (daddr_in == 7'b0010110) begin // 22 + clkind_lti = {2'b00, di_in[5:0]}; + clkind_hti = {2'b00, di_in[11:6]}; + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnt <= di_in[12]; + clkind_nocnti = di_in[12]; + clkind_edgei = di_in[13]; + clkind_edge <= di_in[13]; + if (di_in[12] == 1) + clkind_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkind_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkind_divi = 64 + clkind_hti; + else if (di_in[11:6] == 6'b0) + clkind_divi = 64 + clkind_lti; + else + clkind_divi = clkind_hti + clkind_lti; + + clkind_div <= clkind_divi; + if (clkind_divi > D_MAX || (clkind_divi < 1 && clkind_nocnti == 0)) + $display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to %d.", daddr_in, di_in, clkind_divi, $time, D_MAX); + end + end + else begin + $display(" Error : RST is low at PLLE2_ADV instance %m at time %t. RST need to be high when change PLLE2_ADV paramters through DRP. ", $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; + end + else begin + drp_lock <= 0; + drdy_out <= 1; + drp_lock_lat_cnt <= 0; + end + end + + if (drdy_out == 1) drdy_out <= 0; + end + + function addr_is_valid; + input [6:0] daddr_funcin; + begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) + addr_is_valid = 0; + end + endfunction + + // end process drp; + + // + // determine clock period + // + + always @(posedge clkpll_r or posedge rst_in or posedge rst_clkinsel_flag) + if (rst_in || rst_clkinsel_flag) + begin + clkin_period[0] <= period_vco_target; + clkin_period[1] <= period_vco_target; + clkin_period[2] <= period_vco_target; + clkin_period[3] <= period_vco_target; + clkin_period[4] <= period_vco_target; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end else begin + clkin_edge <= $time; + if (clkin_edge != 0 && clkinstopped_out == 0 && rst_clkinsel_flag == 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(posedge pll_locked_tmp1) + if (clkinsel_in === 0) begin + pchk_tmp1 = CLKIN2_PERIOD * 1100; + pchk_tmp2 = CLKIN2_PERIOD * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning : input CLKIN2 period and attribute CLKIN2_PERIOD on PLLE2_ADV instance %m are not same."); + end + end + else begin + pchk_tmp1 = CLKIN1_PERIOD * 1100; + pchk_tmp2 = CLKIN1_PERIOD * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning : input CLKIN1 period and attribute CLKIN1_PERIOD on PLLE2_ADV instance %m are not same."); + end + end + + always @(m_product or mf_product or clkfb_frac_en) + if (clkfb_frac_en == 0) + clkout_en_val = m_product; + else + clkout_en_val = mf_product - 2; + + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + if (clkout_en0_tmp==0 ) + clkout_en0 = 0; + else begin + if (clkfb_frac_en == 1) begin + if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + else begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in_o ) + if (rst_in_o) + clkout_en = 0; + else + clkout_en = clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_in) + if (rst_in) begin + assign pll_locked_tmp2 = 0; + end + else begin + deassign pll_locked_tmp2; + end + + always @(rst_in) + if (rst_in) begin + assign clkout_en0 = 0; + assign clkout_en1 = 0; + end + else begin + deassign clkout_en0; + deassign clkout_en1; + end + + assign locked_out = (pll_locked_tm && pll_locked_tmp2_dly && ~pll_unlock && !unlock_recover) ? 1 : 0; + + + always @(rst_in or locked_out) + if (rst_in == 1) + locked_out_tmp <= #1000 0; + else + locked_out_tmp <= locked_out; + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4] or period_avg) begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; + + if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + end + +// assign clkinstopped_hold = (clkin_hold_f == 1) ? clkinstopped_out : 0; + + always @(clkinstopped_out_dly or rst_in) + if (rst_in) + clkinstopped_hold = 0; + else begin + if (clkinstopped_out) + clkinstopped_hold <= #1 1; + else begin + if (clkin_hold_f) + clkinstopped_hold = 0; + end + end + + always @(posedge clkinstopped_out) begin + period_avg_stpi <= period_avg; + pd_stp_p <= #1 1; + @(negedge clkvco) + pd_stp_p <= #1 0; + end + + always @(negedge clkvco or posedge rst_in or posedge pd_stp_p) + if (rst_in) begin + period_avg_stp <= 1000; + vco_stp_f <= 0; + end + else if (pd_stp_p) + period_avg_stp <= period_avg_stpi; + else begin + if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin + if (period_vco > 1739) + vco_stp_f <= 1; + else begin + period_avg_stp <= period_avg_stp + 1; + end + end + end + + + always @(period_avg or lock_period or clkind_div) + if (period_avg > 500 && lock_period == 1) begin + clkin_lost_val = ((period_avg * 1.5) / 500) - 1; + clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1; + end + + always @(clkfb_frac_en or clkfbm1_f_div or clkfbm1_div) + if (clkfb_frac_en) + clkfbm1_div_t = clkfbm1_f_div; + else + clkfbm1_div_t = clkfbm1_div; + + always @(period_avg or clkind_div or clkfbm1_div_t or clkinstopped_hold + or period_avg_stp or posedge rst_clkinstopped_rc) + if (period_avg > 0 ) begin + md_product = clkind_div * clkfbm1_div_t; + m_product = clkfbm1_div_t; + m_product2 = clkfbm1_div_t / 2; + period_fb = period_avg * clkind_div; + period_vco_tmp = period_fb / clkfbm1_div_t; + clkvco_pdrm = (period_avg * clkind_div / clkfbm1_div_t) - period_vco_tmp; + period_vco_mf = period_avg * 8; + if (clkinstopped_hold == 1) begin + if (clkin_hold_f) + period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + else + period_vco = period_avg_stp * clkind_div /clkfbm1_div_t; + end + else + period_vco = period_vco_tmp; + clkfbm1_div_t_int = $rtoi(clkfbm1_div_t); + period_vco_rm = period_fb % clkfbm1_div_t_int; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbm1_div_t; + clkin_dly_t = period_avg * (clkind_div + 1.25); + clkfb_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + clk0_frac_ht = period_vco * clkout0_dly + (period_vco * clk0pm_sel_int) / 8; + clk0_frac_lt = period_vco * clkout5_dly + (period_vco * clk5pm_sel) / 8; + clkfb_frac_ht = period_vco * clkfbm1_dly + (period_vco * clkfbm1pm_sel_int) / 8; + clkfb_frac_lt = period_vco * clkout6_dly + (period_vco * clk6pm_sel) / 8; + end + + always @(period_vco or ps_in_ps) + if (fps_en == 1) begin + period_ps_old = period_ps; + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && psincdec_in == 0) + period_ps = period_vco; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + + always @( clkpll_r ) + clkpll_tmp1 <= #(period_avg) clkpll_r; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(posedge clkinstopped_out or posedge rst_in) + if ( rst_in) + clkinstopped_vco_f <= 0; + else begin + clkinstopped_vco_f <= 1; + @(negedge clkinstopped_out or posedge rst_in ) + if (rst_in) + clkinstopped_vco_f <= 0; + else begin + @(posedge clkpll); + @(posedge clkpll) + clkinstopped_vco_f <= 0; + end + end + + always @(posedge clkinstopped_out or posedge rst_in) + if (rst_in === 1'b1) + clkinstopped_out1 <= 0; + else if (rst_in === 1'b0) begin + if (clkinstopped_out === 1'b1) begin + clkinstopped_out1 <= 1; + if (clkin_hold_f == 1) begin + @(posedge locked_out or posedge rst_in) + clkinstopped_out1 <= 0; + end + else begin + if (clkinsel_in == 1) + $display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + else + $display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time); + end + end + end + + always @(posedge clkfbstopped_out or posedge rst_in) + if (rst_in) + clkfbstopped_out1 <= 0; + else begin + clkfbstopped_out1 <= 1; + @(posedge locked_out) + clkfbstopped_out1 <= 0; + end + + + always @(clkout_en_t) + if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) + rst_clkinstopped_tm = 1; + else + rst_clkinstopped_tm = 0; + + always @(negedge clkinstopped_out or posedge rst_in) + if (rst_in) + rst_clkinstopped <= 0; + else + if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin + @(posedge rst_clkinstopped_tm) + rst_clkinstopped <= #period_vco4 1; + @(negedge rst_clkinstopped_tm ) begin + rst_clkinstopped <= #period_vco5 0; + rst_clkinstopped_rc <= #period_vco6 1; + rst_clkinstopped_rc <= #period_vco7 0; + end + end + + always @(posedge clkinstopped_out or posedge rst_in) + if (rst_in) + clkinstopped_out_dly <= 0; + else begin + clkinstopped_out_dly <= 1; + if (clkin_hold_f == 1) begin + @(negedge rst_clkinstopped_rc or posedge rst_in) + clkinstopped_out_dly <= 0; + end + end + + always @(clkinstopped_out or posedge rst_in) + if (rst_in) + clkinstopped_out_dly2 <= 0; + else + clkinstopped_out_dly2 <= #2 clkinstopped_out; + + always @(negedge rst_clkinstopped or posedge rst_in) + if (rst_in) + rst_clkinstopped_lk <= 0; + else begin + rst_clkinstopped_lk <= 1; + @(posedge locked_out) + rst_clkinstopped_lk <= 0; + end + + + + always @(clkinstopped_vco_f or clkinstopped_out1 or clkvco_lk or + clkvco_lk_tmp or rst_in) + if (rst_in) + clkvco_lk = 0; + else begin + if (clkinstopped_out1 == 1 && clkin_stop_f == 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else if (clkinstopped_vco_f == 1 && period_vco_half > 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else + clkvco_lk = clkvco_lk_tmp; + end + + + always @(posedge clkpll) + if (clkfb_frac_en == 1) begin + if (pll_locked_tm ==1 ) begin + clkvco_lk_tmp <= 1; + cmpvco = 0.0; + for (ik1=1; ik1 < mf_product; ik1=ik1+1) begin + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( cmpvco >= 1.0 ) begin + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco - 1.0 + clkvco_pdrm; + end + else if ( cmpvco <= -1.0 ) begin + #(period_vco_half_rm2) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco + 1.0 + clkvco_pdrm; + end + else begin + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco + clkvco_pdrm; + end + clkout_en_t <= ik1; + end + clkout_en_t <= ik1; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + end + else begin + if (pll_locked_tm ==1) begin + clkvco_lk_tmp <= 1; + clkvco_rm_cnt = 0; + clkout_en_t <= 0; + vcoflag = 0; + if ( period_vco_cmp_flag == 1) begin + vcoflag = 1; + for (ik2=1; ik2 < m_product; ik2=ik2+1) begin + clkout_en_t <= ik2; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) +// #(period_vco_half1) clkvco_lk_tmp <= 1; + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik2; + end + else if ( period_vco_cmp_flag == 2 ) begin + vcoflag = 1; + for (ik3=1; ik3 < m_product; ik3=ik3+1) begin + clkout_en_t <= ik3; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik3; + end + else begin + vcoflag = 1; + for (ik4=1; ik4 < m_product; ik4=ik4+1) begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + end + + #(period_vco_half) clkvco_lk_tmp <= 0; + +// if (clkpll == 1) begin + if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) begin + for (ik4=1; ik4 < m_product; ik4=ik4+1) begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or clkfbm1pm_rl + or lock_period or ps_in_ps ) + if (lock_period == 1) begin + if (clkfb_frac_en == 1) begin + fbm1_comp_delay = 0; +// val_tmp = period_vco * mf_product ; + val_tmp = period_vco_mf; + end + else begin + val_tmp = period_avg * DIVCLK_DIVIDE; + fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl); + end + dly_tmp1 = fb_delay + fbm1_comp_delay; + dly_tmp_int = 1; + if (clkfb_fps_en == 1) begin + if (ps_in_ps < 0) begin + tmp_ps_val1 = -1 * ps_in_ps; + tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; + if (tmp_ps_val2 > dly_tmp1 ) begin + dly_tmp_int = -1; + dly_tmp = tmp_ps_val2 - dly_tmp1; + end + else if (tmp_ps_val2 == dly_tmp1 ) begin + dly_tmp_int = 0; + dly_tmp = 0; + end + else begin + dly_tmp_int = 1; + dly_tmp = dly_tmp1 - tmp_ps_val2; + end + end + else + dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; + end + else + dly_tmp = dly_tmp1; + + if (dly_tmp_int < 0) + clkvco_delay = dly_tmp; + else begin + if (clkfb_frac_en == 1 && dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + end + + always @(period_vco or ps_in_ps ) + if (fps_en == 1) begin + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && psincdec_in == 0) + period_ps = period_vco; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + always @(clkfbm1pm_sel) + case (clkfbm1pm_sel) + 3'b000 : clkfbm1pm_rl = 0.0; + 3'b001 : clkfbm1pm_rl = 0.125; + 3'b010 : clkfbm1pm_rl = 0.25; + 3'b011 : clkfbm1pm_rl = 0.375; + 3'b100 : clkfbm1pm_rl = 0.50; + 3'b101 : clkfbm1pm_rl = 0.625; + 3'b110 : clkfbm1pm_rl = 0.75; + 3'b111 : clkfbm1pm_rl = 0.875; + endcase + + always @(clkvco_lk) + clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; + + always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) + if ( pll_locked_tm && vco_stp_f == 0) begin + if (dly_tmp == 0) + clkvco = clkvco_lk; + else + clkvco = clkvco_lk_dly_tmp; + end + else + clkvco = 0; + + always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge) + clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); + always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge) + clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); + always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge) + clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge); + always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge) + clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge); + always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge) + clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge); + always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge) + clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge); + always @(clk6_ht or clk6_lt or clk6_nocnt or init_trig or clk6_edge) + clkout_pm_cal(clk6_ht1, clk6_div, clk6_div1, clk6_ht, clk6_lt, clk6_nocnt, clk6_edge); + always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge) + if (clkfb_frac_en) begin + clkfbm1_div = CLKFBOUT_MULT; + end + else + clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); + always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge) + clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge); + always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge) + clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge); + + always @(posedge psclk_in or posedge rst_in) + if (rst_in) begin + ps_in_ps <= ps_in_init; + ps_cnt <= 0; + psen_w <= 0; + end else if (fps_en == 1) begin + if (psen_in) begin + if (psen_w == 1) + $display(" Error : PSEN on PLLE2_ADV instance %m is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period.", $time); + + psen_w <= 1; + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal on PLLE2_ADV instance %m at time %t before adjusting the Phase Shift.", $time); + else if (psincdec_in == 1) begin + if (ps_cnt < ps_max) + ps_cnt <= ps_cnt + 1; + else + ps_cnt <= 0; + + if (ps_in_ps < ps_max) + ps_in_ps <= ps_in_ps + 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + ps_cnt_neg = (-1) * ps_cnt; + ps_in_ps_neg = (-1) * ps_in_ps; + if (ps_cnt_neg < ps_max) + ps_cnt <= ps_cnt - 1; + else + ps_cnt <= 0; + + if (ps_in_ps_neg < ps_max) + ps_in_ps <= ps_in_ps - 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + end + else + psen_w <= 0; + + if ( psdone_out == 1) + ps_lock <= 0; + end + + always @(posedge ps_lock) + if (fps_en == 1) begin + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + begin + psdone_out = 1; + @(posedge psclk_in); + psdone_out = 0; + end + end + + always @(rst_in_o) + if (rst_in_o) begin + assign clkout_mux = 8'b0; + assign clkout_ps_mux = 8'b0; + assign clkout_ps = 0; + assign clkout_ps_tmp1 = 0; + assign clkout_ps_tmp2 = 0; + assign clk0_frac_out = 0; + assign clkfbm1_frac_out = 0; + end + else begin + deassign clkout_mux; + deassign clkout_ps_mux; + deassign clkout_ps; + deassign clkout_ps_tmp1; + deassign clkout_ps_tmp2; + deassign clk0_frac_out; + deassign clkfbm1_frac_out; + end + + always @(rst_clkinstopped) + if (rst_clkinstopped) begin + assign clkfb_frac_ht = 50; + assign clkfb_frac_lt = 50; + end + else begin + deassign clkfb_frac_ht; + deassign clkfb_frac_lt; + end + + //always @(clkvco or clkout_en ) + always @(clkvco) + if (clkout_en) begin + clkout_mux[0] = clkvco; + clkout_mux[1] <= #(period_vco1) clkvco; + clkout_mux[2] <= #(period_vco2) clkvco; + clkout_mux[3] <= #(period_vco3) clkvco; + clkout_mux[4] <= #(period_vco4) clkvco; + clkout_mux[5] <= #(period_vco5) clkvco; + clkout_mux[6] <= #(period_vco6) clkvco; + clkout_mux[7] <= #(period_vco7) clkvco; + end + + always @(clkout_ps or clkout_en ) + if (clkout_en) begin + clkout_ps_mux[0] = clkout_ps; + clkout_ps_mux[1] <= #(period_vco1) clkout_ps; + clkout_ps_mux[2] <= #(period_vco2) clkout_ps; + clkout_ps_mux[3] <= #(period_vco3) clkout_ps; + clkout_ps_mux[4] <= #(period_vco4) clkout_ps; + clkout_ps_mux[5] <= #(period_vco5) clkout_ps; + clkout_ps_mux[6] <= #(period_vco6) clkout_ps; + clkout_ps_mux[7] <= #(period_vco7) clkout_ps; + end + + always @(clkvco or clkout_en ) + if (fps_en == 1) begin + clkvco_ps_tmp1 <= #(period_ps) clkvco; + clkvco_ps_tmp2 <= #(period_ps_old) clkvco; + end + + always @(negedge clkout_ps) + clkout_ps_eg <= $time; + + always @(posedge clkout_ps) + clkout_ps_peg <= $time; + + always @(ps_lock) + ps_lock_dly <= #1 ps_lock; + + always @(posedge ps_lock_dly) + if ((period_ps - period_ps_old) > period_vco_half ) begin + if (clkout_ps == 0) begin + if (clkvco_ps_tmp2 == 1) begin + clkout_ps_w = $time - clkout_ps_eg; + if (clkout_ps_w > period_vco3) + clkvco_ps_tmp2_en <= 1; + else begin + @(negedge clkvco_ps_tmp2) + clkvco_ps_tmp2_en <= 1; + end + end + else + clkvco_ps_tmp2_en <= 1; + end + else begin + if (clkvco_ps_tmp2 == 0) begin + clkout_ps_w = $time - clkout_ps_peg; + if (clkout_ps_w > period_vco3) + clkvco_ps_tmp2_en <= 1; + else begin + @(posedge clkvco_ps_tmp2) + clkvco_ps_tmp2_en <= 1; + end + end + else + clkvco_ps_tmp2_en <= 1; + end + @(posedge clkvco_ps_tmp2); + @(negedge clkvco_ps_tmp2) + if (clkvco_ps_tmp1 == 0) + clkvco_ps_tmp2_en <= 0; + else + @(negedge clkvco_ps_tmp1) + clkvco_ps_tmp2_en <= 0; + end + + + always @(clkvco or clkvco_ps_tmp1 or clkvco_ps_tmp2 or clkvco_ps_tmp2_en ) + if (fps_en == 1) begin + if (ps_in_ps == 0 ) + clkout_ps = clkvco; + else if (clkvco_ps_tmp2_en == 1) + clkout_ps = clkvco_ps_tmp2; + else + clkout_ps = clkvco_ps_tmp1; + end + + + assign clk0in = (clk0_fps_en == 1) ? clkout_ps_mux[clk0pm_sel] : clkout_mux[clk0pm_sel1]; + assign clk1in = (clk1_fps_en == 1) ? clkout_ps_mux[clk1pm_sel] : clkout_mux[clk1pm_sel]; + assign clk2in = (clk2_fps_en == 1) ? clkout_ps_mux[clk2pm_sel] : clkout_mux[clk2pm_sel]; + assign clk3in = (clk3_fps_en == 1) ? clkout_ps_mux[clk3pm_sel] : clkout_mux[clk3pm_sel]; + assign clk4in = (clk4_fps_en == 1) ? clkout_ps_mux[clk4pm_sel] : ((clkout4_cascade_int == 1) ? clk6_out : clkout_mux[clk4pm_sel]); + assign clk5in = (clk5_fps_en == 1) ? clkout_ps_mux[clk5pm_sel] : clkout_mux[clk5pm_sel1]; + assign clk6in = (clk6_fps_en == 1) ? clkout_ps_mux[clk6pm_sel] : clkout_mux[clk6pm_sel1]; + assign clkfbm1in = (clkfb_fps_en == 1) ? clkout_ps_mux[clkfbm1pm_sel] : clkout_mux[clkfbm1pm_sel1]; + + assign clkfbm1pm_sel1 = (clkfb_frac_en) ? 3'b0 : clkfbm1pm_sel; + assign clk6pm_sel1 = (clkfb_frac_en) ? 3'b0 : clk6pm_sel; + assign clk0pm_sel1 = (clk0_frac_en) ? 3'b0 : clk0pm_sel; + assign clk5pm_sel1 = (clk0_frac_en) ? 3'b0 : clk5pm_sel; + + assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; + assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; + assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0; + assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0; + assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0; + assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0; + assign clk6ps_en = (clk6_dly_cnt == clkout6_dly) ? clkout_en : 0; + assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; + + always @(posedge clk0in) + if (clkout_en && clk0_frac_en) begin + clk0_frac_out <= 1; + for (ik0=1; ik0 < 8; ik0=ik0+1) begin + #(clk0_frac_ht) clk0_frac_out <= 0; + #(clk0_frac_lt) clk0_frac_out <= 1; + end + #(clk0_frac_ht) clk0_frac_out <= 0; +// #(clk0_frac_lt - 50); + #(clk0_frac_lt - period_vco1); + end + + always @(posedge clkfbm1in) + if (clkout_en && clkfb_frac_en) begin + clkfbm1_frac_out <= 1; + for (ib=1; ib < 8; ib=ib+1) begin + #(clkfb_frac_ht) clkfbm1_frac_out <= 0; + #(clkfb_frac_lt) clkfbm1_frac_out <= 1; + end + #(clkfb_frac_ht) clkfbm1_frac_out <= 0; + #(clkfb_frac_lt - period_vco1); + end + else + clkfbm1_frac_out <= 0; + + always @(negedge clk0in or posedge rst_in_o) + if (rst_in_o) + clk0_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clk0_frac_en == 0) begin + if (clk0_dly_cnt < clkout0_dly) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in_o) + if (rst_in_o) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in_o) + if (rst_in_o) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clkout2_dly && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in_o) + if (rst_in_o) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clkout3_dly && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in_o) + if (rst_in_o) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clkout4_dly && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in_o) + if (rst_in_o) + clk5_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clk0_frac_en == 0) begin + if (clk5_dly_cnt < clkout5_dly) + clk5_dly_cnt <= clk5_dly_cnt + 1; + end + + always @(negedge clk6in or posedge rst_in_o) + if (rst_in_o) + clk6_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clkfb_frac_en == 0) begin + if (clk6_dly_cnt < clkout6_dly) + clk6_dly_cnt <= clk6_dly_cnt + 1; + end + + always @(negedge clkfbm1in or posedge rst_in_o) + if (rst_in_o) + clkfbm1_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clkfb_frac_en == 0) begin + if (clkfbm1_dly_cnt < clkfbm1_dly) + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + end + + always @(posedge clk0in or negedge clk0in or posedge rst_in_o) + if (rst_in_o) begin + clk0_cnt <= 8'b0; + clk0_nf_out <= 0; + end + else if (clk0ps_en && clk0_frac_en == 1'b0) begin + if (clk0_cnt < clk0_div1) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + if (clk0_cnt < clk0_ht1) + clk0_nf_out <= 1; + else + clk0_nf_out <= 0; + end + else begin + clk0_cnt <= 8'b0; + clk0_nf_out <= 0; + end + + assign clk0_out = (clk0_frac_en) ? clk0_frac_out : clk0_nf_out; + + always @(posedge clk1in or negedge clk1in or posedge rst_in_o) + if (rst_in_o) begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + else if (clk1ps_en) begin + if (clk1_cnt < clk1_div1) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + if (clk1_cnt < clk1_ht1) + clk1_out <= 1; + else + clk1_out <= 0; + end + else begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in_o) + if (rst_in_o) begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + else if (clk2ps_en) begin + if (clk2_cnt < clk2_div1) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + if (clk2_cnt < clk2_ht1) + clk2_out <= 1; + else + clk2_out <= 0; + end + else begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in_o) + if (rst_in_o) begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + else if (clk3ps_en) begin + if (clk3_cnt < clk3_div1) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + if (clk3_cnt < clk3_ht1) + clk3_out <= 1; + else + clk3_out <= 0; + end + else begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + + + always @(posedge clk4in or negedge clk4in or posedge rst_in_o) + if (rst_in_o) begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + else if (clk4ps_en) begin + if (clk4_cnt < clk4_div1) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + if (clk4_cnt < clk4_ht1) + clk4_out <= 1; + else + clk4_out <= 0; + end + else begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + + always @(posedge clk5in or negedge clk5in or posedge rst_in_o) + if (rst_in_o) begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + else if (clk5ps_en && clk0_frac_en == 1'b0) begin + if (clk5_cnt < clk5_div1) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + if (clk5_cnt < clk5_ht1) + clk5_out <= 1; + else + clk5_out <= 0; + end + else begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + + always @(posedge clk6in or negedge clk6in or posedge rst_in_o) + if (rst_in_o) begin + clk6_cnt <= 8'b0; + clk6_out <= 0; + end + else if (clk6ps_en && clkfb_frac_en == 0) begin + if (clk6_cnt < clk6_div1) + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 8'b0; + if (clk6_cnt < clk6_ht1) + clk6_out <= 1; + else + clk6_out <= 0; + end + else begin + clk6_cnt <= 8'b0; + clk6_out <= 0; + end + + always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in_o) + if (rst_in_o) begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + else if (clkfbm1ps_en && clkfb_frac_en == 0) begin + if (clkfbm1_cnt < clkfbm1_div1) + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 8'b0; + if (clkfbm1_cnt < clkfbm1_ht1) + clkfbm1_nf_out <= 1; + else + clkfbm1_nf_out <= 0; + end + else begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + + assign clkfbm1_out = (clkfb_frac_en) ? clkfbm1_frac_out : clkfbm1_nf_out; + + always @(posedge clkfb_in or negedge clkfb_in or posedge rst_in) + if (rst_in) begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + else if (clkout_en) begin + if (clkfbm2_cnt < clkfbm2_div1) + clkfbm2_cnt <= clkfbm2_cnt + 1; + else + clkfbm2_cnt <= 8'b0; + if (clkfbm2_cnt < clkfbm2_ht1) + clkfbm2_out <= 1; + else + clkfbm2_out <= 0; + end + else begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + + always @(posedge clkpll_r or negedge clkpll_r or posedge rst_in) + if (rst_in) begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + else if (clkout_en) begin + if (clkind_cnt < clkind_div1) + clkind_cnt <= clkind_cnt + 1; + else + clkind_cnt <= 8'b0; + if (clkind_cnt < clkind_ht1) + clkind_out <= 1; + else + clkind_out <= 0; + end + else begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + + always @(clk0_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout0_out = clk0_out; + else + clkout0_out = clkfb_tst; + + always @(clk1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout1_out = clk1_out; + else + clkout1_out = clkfb_tst; + + always @(clk2_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout2_out = clk2_out; + else + clkout2_out = clkfb_tst; + + always @(clk3_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout3_out = clk3_out; + else + clkout3_out = clkfb_tst; + + always @(clk4_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout4_out = clk4_out; + else + clkout4_out = clkfb_tst; + + always @(clk5_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout5_out = clk5_out; + else + clkout5_out = clkfb_tst; + + always @(clk6_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout6_out = clk6_out; + else + clkout6_out = clkfb_tst; + + always @(clkfbm1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkfb_out = clkfbm1_out; + else + clkfb_out = clkfb_tst; + + // + // determine feedback delay + // + +// always @(rst_in) +// if (rst_in) +// assign clkfb_tst = 0; +// else +// deassign clkfb_tst; + + always @(posedge clkpll_r ) + if (pwron_int || rst_in || fb_delay_found) clkfb_tst <= 1'b0; + else clkfb_tst <= ~clkfb_tst; + + always @( posedge clkfb_tst or posedge rst_in ) + if (rst_in) + delay_edge <= 0; + else + delay_edge <= $time; + + assign clkfbin_sel = (COMPENSATION_BIN == COMPENSATION_INTERNAL); + + always @(posedge clkfb_in or posedge rst_in ) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end else if (clkfbin_sel == 1'b1) begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b1; + end else begin + if (fb_delay_found_tmp == 1'b0 ) begin + if ( delay_edge != 0) + fb_delay <= ($time - delay_edge); + else + fb_delay <= 0; + fb_delay_found_tmp <= 1'b1; + end + end + + always @(rst_in) + if (rst_in) + assign fb_delay_found = 1'b0; + else + deassign fb_delay_found; + + always @(negedge clkfb_tst) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay) + if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning : The feedback delay on PLLE2_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max); + end + + // + // generate unlock signal + // + + always @(clk_osc or rst_in) + if (rst_in) + clk_osc <= 0; + else + clk_osc <= #OSC_P2 ~clk_osc; + + always @(posedge clkpll_r or negedge clkpll_r) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge clkfb_in or negedge clkfb_in) begin + clkfb_p <= 1; + clkfb_p <= #100 0; + end + + + always @(posedge clk_osc or posedge rst_in or posedge clkin_p) + if (rst_in == 1) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out == 1) begin + @(posedge clkpll_r) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out <= 0; + end + else + clkinstopped_out <= 1; + end + + always @(posedge clk_osc or posedge rst_in or posedge clkfb_p) + if (rst_in == 1 || clkfb_p == 1) begin + clkfbstopped_out <= 0; + clkfb_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfb_lost_cnt < clkfb_lost_val) begin + clkfb_lost_cnt <= clkfb_lost_cnt + 1; + clkfbstopped_out <= 0; + end + else + clkfbstopped_out <= 1; + end + + + always @(clkin_jit or rst_in ) + if (rst_in) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2 && clkfbstopped_out == 0 && clkinstopped_out == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // tasks + + task clkout_dly_cal; + output [5:0] clkout_dly; + output [2:0] clkpm_sel; + input clkdiv; + input clk_ps; + input reg [160:0] clk_ps_name; + integer clkdiv; + real clk_ps; + real clk_ps_rl; + real clk_dly_rl, clk_dly_rem; + integer clkout_dly_tmp; + begin + if (clk_ps < 0.0) + clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; + else + clk_dly_rl = clk_ps * clkdiv / 360.0; + + clkout_dly_tmp = $rtoi(clk_dly_rl); + + if (clkout_dly_tmp > 63) begin + $display(" Warning : Attribute %s of PLLE2_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of PLLE2_ADV", clk_ps_name, clk_ps); + clkout_dly = 6'b111111; + end + else + clkout_dly = clkout_dly_tmp; + + clk_dly_rem = clk_dly_rl - clkout_dly; + + if (clk_dly_rem < 0.125) + clkpm_sel = 0; + else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25) + clkpm_sel = 1; + else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375) + clkpm_sel = 2; + else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5) + clkpm_sel = 3; + else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625) + clkpm_sel = 4; + else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75) + clkpm_sel = 5; + else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875) + clkpm_sel = 6; + else if (clk_dly_rem >= 0.875 ) + clkpm_sel = 7; + + if (clk_ps < 0.0) + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0; + else + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv; + + if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001)) + $display(" Warning : Attribute %s of PLLE2_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl); + + end + endtask + + task clk_out_para_cal; + output [6:0] clk_ht; + output [6:0] clk_lt; + output clk_nocnt; + output clk_edge; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + integer CLKOUT_DIVIDE; + real CLKOUT_DUTY_CYCLE; + real tmp_value, tmp_value0, tmp_value_rm; + integer tmp_value_round, tmp_value1, tmp_value_r; + real tmp_value2; + real tmp_value_rm1, tmp_value_r1; + integer tmp_value_r2; + begin + + tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; + tmp_value_r = $rtoi(tmp_value0); + tmp_value_rm = tmp_value0 - tmp_value_r; + if (tmp_value_rm < 0.1) + tmp_value = tmp_value_r * 1.0; + else if (tmp_value_rm > 0.9) + tmp_value = 1.0 * tmp_value_r + 1.0; + else begin + tmp_value_r1 = tmp_value0 * 2.0; + tmp_value_r2 = $rtoi(tmp_value_r1); + tmp_value_rm1 = tmp_value_r1 - tmp_value_r2; + if (tmp_value_rm1 > 0.995) + tmp_value = tmp_value0 + 0.002; + else + tmp_value = tmp_value0; + end + tmp_value_round = tmp_value * 2.0; + tmp_value1 = tmp_value_round % 2; + tmp_value2 = CLKOUT_DIVIDE - tmp_value; + + + if ((tmp_value2) >= O_MAX_HT_LT) begin + clk_lt = 7'b1000000; + end + else begin + if (tmp_value2 < 1.0) + clk_lt = 1; + else + if ( tmp_value1 != 0) + clk_lt = $rtoi(tmp_value2) + 1; + else + clk_lt = $rtoi(tmp_value2); + end + + if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT) + clk_ht = 7'b1000000; + else + clk_ht = CLKOUT_DIVIDE - clk_lt; + + clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; + if ( tmp_value < 1.0) + clk_edge = 1; + else if (tmp_value1 != 0) + clk_edge = 1; + else + clk_edge = 0; + end + endtask + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + integer para_in; + integer range_low; + integer range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on PLLE2_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; + end + endfunction + + function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + real para_in; + real range_low; + real range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on PLLE2_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); + $finish; + end + para_real_range_chk = 1'b0; + end + endfunction + + task clkout_pm_cal; + output [7:0] clk_ht1; + output [7:0] clk_div; + output [7:0] clk_div1; + input [6:0] clk_ht; + input [6:0] clk_lt; + input clk_nocnt; + input clk_edge; + begin + if (clk_nocnt ==1) begin + clk_div = 8'b00000001; + clk_div1 = 8'b00000001; + clk_ht1 = 8'b00000001; + end + else begin + if ( clk_edge == 1) + clk_ht1 = 2 * clk_ht + 1; + else + clk_ht1 = 2 * clk_ht; + clk_div = clk_ht + clk_lt ; + clk_div1 = 2 * clk_div -1; + end + end + endtask + + task clkout_delay_para_drp; + output [5:0] clkout_dly; + output clk_nocnt; + output clk_edge; + input [15:0] di_in; + input [6:0] daddr_in; + begin + clkout_dly = di_in[5:0]; + clk_nocnt = di_in[6]; + clk_edge = di_in[7]; + end + endtask + + task clkout_hl_para_drp; + output [6:0] clk_lt; + output [6:0] clk_ht; + output [2:0] clkpm_sel; + input [15:0] di_in_tmp; + input [6:0] daddr_in_tmp; + begin + if (di_in_tmp[12] != 1) begin + $display(" Error : PLLE2_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time); + end + if ( di_in_tmp[5:0] == 6'b0) + clk_lt = 7'b1000000; + else + clk_lt = { 1'b0, di_in_tmp[5:0]}; + if (di_in_tmp[11:6] == 6'b0) + clk_ht = 7'b1000000; + else + clk_ht = { 1'b0, di_in_tmp[11:6]}; + clkpm_sel = di_in_tmp[15:13]; + end + endtask + +// end behavioral model + + specify + (CLKIN1 => LOCKED) = (100:100:100, 100:100:100); + (CLKIN2 => LOCKED) = (100:100:100, 100:100:100); + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (RST => LOCKED) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKIN1, 0:0:0, notifier); + $period (negedge CLKIN2, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT2, 0:0:0, notifier); + $period (negedge CLKOUT3, 0:0:0, notifier); + $period (negedge CLKOUT4, 0:0:0, notifier); + $period (negedge CLKOUT5, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKIN1, 0:0:0, notifier); + $period (posedge CLKIN2, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT2, 0:0:0, notifier); + $period (posedge CLKOUT3, 0:0:0, notifier); + $period (posedge CLKOUT4, 0:0:0, notifier); + $period (posedge CLKOUT5, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE); + $width (negedge CLKIN1, 0:0:0, 0, notifier); + $width (negedge CLKIN2, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN1, 0:0:0, 0, notifier); + $width (posedge CLKIN2, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PLLE2_BASE.v b/verilog/src/unisims/PLLE2_BASE.v new file mode 100644 index 0000000..d08a6a5 --- /dev/null +++ b/verilog/src/unisims/PLLE2_BASE.v @@ -0,0 +1,157 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.i (O.4) +// \ \ Description : +// / / +// /__/ /\ Filename : PLLE2_BASE.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 12/09/09 - Initial version +// 03/23/10 - Change CLKFBOUT_MULT default from 1 to 5. +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE2_BASE ( + CLKFBOUT, + CLKOUT0, + CLKOUT1, + CLKOUT2, + CLKOUT3, + CLKOUT4, + CLKOUT5, + LOCKED, + CLKFBIN, + CLKIN1, + PWRDWN, + RST +); + + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif // + + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; + + wire OPEN_DRDY; + wire OPEN_PSDONE; + wire OPEN_FBS; + wire OPEN_INS; + wire [15:0] OPEN_DO; + + PLLE2_ADV #( + .BANDWIDTH(BANDWIDTH), + .STARTUP_WAIT(STARTUP_WAIT), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .CLKFBOUT_MULT(CLKFBOUT_MULT), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN1_PERIOD), + .CLKIN2_PERIOD(10), + .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .REF_JITTER1(REF_JITTER1) + ) + plle2_adv_1 ( + .CLKFBIN (CLKFBIN), + .CLKFBOUT (CLKFBOUT), + .CLKIN1 (CLKIN1), + .CLKIN2 (1'b0), + .CLKOUT0 (CLKOUT0), + .CLKOUT1 (CLKOUT1), + .CLKOUT2 (CLKOUT2), + .CLKOUT3 (CLKOUT3), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .DWE (1'b0), + .LOCKED (LOCKED), + .CLKINSEL(1'b1), + .PWRDWN(PWRDWN), + .RST (RST) + ); + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PLLE3_ADV.v b/verilog/src/unisims/PLLE3_ADV.v new file mode 100644 index 0000000..22bd83a --- /dev/null +++ b/verilog/src/unisims/PLLE3_ADV.v @@ -0,0 +1,2328 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Phase-Locked Loop (PLL) +// /___/ /\ Filename : PLLE3_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/22/2013 700625 - update PLLE3 for yml changes +// 02/28/2013 703674 - update vco_half attribute +// 03/25/2013 PLLE3 sync5 changes +// 04/04/2013 709484 - add PFD check +// 04/02/2013 709723 - fix Lock for lost clock +// 04/08/2013 709729 - Fix clkoutxiphy for CLKIN mode +// 04/09/2013 709725 - Fix clkout0 frequency after reset +// 04/09/2013 709726 - Fix clkout0 frequency +// 04/12/2013 Invertible pin changes +// 04/16/2013 Writer and invertible pin changes +// 04/22/2013 713959 - clkoutphy frequency fix after reset +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE3_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 70.000, + parameter real CLKPFD_FREQ_MAX = 667.500, + parameter real CLKPFD_FREQ_MIN = 70.000, + parameter real VCOCLK_FREQ_MAX = 1335.000, + parameter real VCOCLK_FREQ_MIN = 600.000, +`endif + parameter integer CLKFBOUT_MULT = 5, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN_PERIOD = 0.000, + parameter integer CLKOUT0_DIVIDE = 1, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUTPHY_MODE = "VCO_2X", + parameter COMPENSATION = "AUTO", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUTPHY, + output [15:0] DO, + output DRDY, + output LOCKED, + + input CLKFBIN, + input CLKIN, + input CLKOUTPHYEN, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 70.000; + localparam real CLKPFD_FREQ_MAX = 667.500; + localparam real CLKPFD_FREQ_MIN = 70.000; + localparam real VCOCLK_FREQ_MAX = 1335.000; + localparam real VCOCLK_FREQ_MIN = 600.000; +`endif + +// define constants + localparam MODULE_NAME = "PLLE3_ADV"; + +// Parameter encodings and registers + localparam CLKOUTPHY_MODE_VCO = 1; + localparam CLKOUTPHY_MODE_VCO_2X = 0; + localparam CLKOUTPHY_MODE_VCO_HALF = 2; + localparam COMPENSATION_AUTO = 0; + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_INTERNAL = 3; + localparam STARTUP_WAIT_FALSE = 0; + localparam STARTUP_WAIT_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "PLLE3_ADV_dr.v" +`else + localparam [4:0] CLKFBOUT_MULT_REG = CLKFBOUT_MULT; + localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; + localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; + localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; + localparam real CLKIN_PERIOD_REG = CLKIN_PERIOD; + localparam [7:0] CLKOUT0_DIVIDE_REG = CLKOUT0_DIVIDE; + localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; + localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; + localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; + localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; + localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; + localparam [64:1] CLKOUTPHY_MODE_REG = CLKOUTPHY_MODE; + localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; + localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; + localparam [64:1] COMPENSATION_REG = COMPENSATION; + localparam [3:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN_INVERTED_REG = IS_CLKIN_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REF_JITTER_REG = REF_JITTER; + localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; + localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; + localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; +`endif + + wire [2:0] COMPENSATION_BIN; + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + + localparam VCOCLK_FREQ_TARGET = 1200; + localparam M_MIN = 1; + localparam M_MAX = 19; + localparam real VF_MAX = 1335.000; + localparam real VF_MIN = 600.000; + localparam D_MIN = 1; + localparam D_MAX = 15; +// localparam O_MIN = 1; // not used + localparam O_MAX = 256; + localparam O_MAX_HT_LT = 128; // change from 64 + localparam REF_CLK_JITTER_MAX = 1000; + localparam OSC_P2 = 250; + + tri1 p_up; + reg [160:0] tmp_string; + reg chk_ok; + reg init_chk; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + real clkvco_freq_init_chk; + real clkpfd_freq_init_chk; + wire [1:0] xiphy_mode; + + wire [15:0] do_out; + wire [15:0] di_in; + wire [6:0] daddr_in; + reg [15:0] do_out1; + integer clkfb_div_fint; + + wire locked_out; + reg locked_out1; + reg locked_out_tmp; + + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drdy_out, drdy_out1; + reg drp_lock; + reg [2:0] drp_lock_lat = 3'b100; + reg [2:0] drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + + integer period_vco_max, period_vco_min; + integer period_vco_target, period_vco_target_half; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + integer md_product, m_product, m_product2; + integer clkout_en_val; + reg clkout0_out, clkout1_out; + + reg [7:0] clk0_ht, clk0_lt; + reg [7:0] clk1_ht, clk1_lt; + reg clk0_edge, clk1_edge; + reg clk0_nocnt, clk1_nocnt; + + reg rst_in = 1'b0; + integer clkin_period_tmp; + integer clkin_period [4:0]; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock = 1'b0; + integer clkin_jit; + integer pchk_tmp1, pchk_tmp2; + integer period_avg, period_fb; + wire clkin_in,clkfb_in; + reg clkout_en, clkout_en0_tmp, clkout_en0_tmp1=0, clkout_en0, clkout_en1; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2, pll_locked_tmp2_dly; + time clkin_edge, delay_edge; + time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay; + time dly_tmp1; + integer dly_tmp_int; + reg fb_delay_found, fb_delay_found_tmp; + real fb_delay_max; + integer period_vco_mf; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + integer period_vco_half_rm1, period_vco_half_rm2; + time pll_locked_delay, clkin_dly_t; + reg clkpll = 1'b0; + reg clkpll_tmp1 = 1'b0; + reg clkvco_lk = 1'b0, clkvco_lk_tmp = 1'b0, clkvco = 1'b0, clkvco_by2 = 1'b0, clkvco_2x = 1'b0; + reg clkvco_by8 = 1'b0; + integer i, ik2, ik3, ik4, j; + reg vcoflag = 1'b0; + integer clkout_en_t; + reg clk_osc=1'b0, clkin_p=1'b0, clkfb_p=1'b0; + reg clkinstopped_out; + reg clkfbstopped_out; + integer clkin_lost_cnt, clkfb_lost_cnt; + integer clkin_lost_val, clkfb_lost_val; + reg clkinstopped_out_dly = 0; + + reg pwron_int; + reg clkfb_tst = 1'b0; + reg [7:0] clkind_div; + reg [2:0] clkout_mux; + //reg [2:0] clk0pm_sel, clk1pm_sel, clkfbm1pm_sel; + reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti; + reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; + reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1; + reg [7:0] clkind_divi, clkind_div1, clkind_cnt, clkind_ht1; + reg clkfbtmp_nocnti; + reg clkind_edgei, clkind_nocnti; + reg clkind_out, clkind_out_tmp; + reg [6:0] clkfbm1_ht, clkfbm1_lt; + reg [6:0] clkfbin_ht, clkfbin_lt; + reg [7:0] clkind_ht, clkind_lt; + reg [7:0] clkind_hti, clkind_lti; + reg clkfbm1_nocnt, clkind_nocnt; + reg clkfbm1_edge, clkind_edge; + reg clkfbin_edge, clkfbin_nocnt; + reg clkfbm1_nf_out; + + integer period_vco1; + integer period_vco2; + reg clk0_out; + reg clk1_out; + reg clkfb_out; + wire clkfbm1_out; + reg clkfbm2_out; + reg [5:0] clk0_dly_cnt, clkout0_dly; + reg [5:0] clk1_dly_cnt, clkout1_dly; + reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; + reg [8:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; + reg [8:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; + wire init_trig, clk0in, clk1in; + + wire clkoutxiphy_int; + wire xiphyen_in; + reg xiphyen_sync=1'b0; + reg xiphyen_sync1=1'b0; + reg xiphyen_sync2=1'b0; + reg [1:0] clkvco_cnt=2'b00; + + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire [15:0] DI_delay; + wire [6:0] DADDR_delay; + + wire dclk_in; + wire den_in; + wire dwe_in; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING + assign DCLK_delay = DCLK; + + assign DADDR_delay = DADDR; + assign DEN_delay = DEN; + assign DI_delay = DI; + assign DWE_delay = DWE; +`endif + + wire CLKFBIN_int; + wire startup_wait_sig; + wire clkfbin_sel; + wire pwrdwn_in; + wire rst_input_r; + wire glock; + wire pwrdwn_in1; + wire rst_input; + wire clkfbm1in; + wire clk0ps_en, clk1ps_en; + wire clkfbm1ps_en; + assign clkfb_in = CLKFBIN ^ IS_CLKFBIN_INVERTED_REG; + assign clkin_in = CLKIN ^ IS_CLKIN_INVERTED_REG; + assign xiphyen_in = CLKOUTPHYEN; + assign daddr_in = DADDR_delay; + assign di_in = DI_delay; + assign dwe_in = DWE_delay; + assign den_in = DEN_delay; + assign dclk_in = DCLK_delay; + assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_REG; + assign rst_input_r = RST ^ IS_RST_INVERTED_REG; + assign LOCKED = locked_out1; + assign DRDY = drdy_out1; + assign DO = do_out1; + + always @(locked_out_tmp) + locked_out1 = locked_out_tmp; + always @(pll_locked_tmp2) + pll_locked_tmp2_dly = pll_locked_tmp2; + always @(drdy_out) + drdy_out1 = drdy_out; + always @(do_out) + do_out1 = do_out; + // `endif // `ifndef XIL_TIMING + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + COMPENSATION_AUTO; + + assign xiphy_mode = + (CLKOUTPHY_MODE_REG == "VCO_2X") ? CLKOUTPHY_MODE_VCO_2X : + (CLKOUTPHY_MODE_REG == "VCO") ? CLKOUTPHY_MODE_VCO : + (CLKOUTPHY_MODE_REG == "VCO_HALF") ? CLKOUTPHY_MODE_VCO_HALF : + CLKOUTPHY_MODE_VCO_2X; + + assign startup_wait_sig = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + initial begin + #1; + trig_attr = ~trig_attr; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLKFBOUT_MULT_REG < M_MIN) || (CLKFBOUT_MULT_REG > M_MAX))) begin + $display("Error: [Unisim %s-102] CLKFBOUT_MULT attribute is set to %d. Legal values for this attribute are %d to %d. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_REG, M_MIN, M_MAX); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin + $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MIN_REG < 70.000 || CLKIN_FREQ_MIN_REG > 70.000)) begin + $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 70.000 to 70.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_PERIOD_REG < 0.000 || CLKIN_PERIOD_REG > 14.286)) begin + $display("Error: [Unisim %s-105] CLKIN_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 14.286. Instance: %m", MODULE_NAME, CLKIN_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT0_DIVIDE_REG < 1) || (CLKOUT0_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-106] CLKOUT0_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUTPHY_MODE_REG != "VCO_2X") && + (CLKOUTPHY_MODE_REG != "VCO") && + (CLKOUTPHY_MODE_REG != "VCO_HALF"))) begin + $display("Error: [Unisim %s-112] CLKOUTPHY_MODE attribute is set to %s. Legal values for this attribute are VCO_2X, VCO or VCO_HALF. Instance: %m", MODULE_NAME, CLKOUTPHY_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MAX_REG < 600.000 || CLKPFD_FREQ_MAX_REG > 667.500)) begin + $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 550.000 to 667.500. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MIN_REG < 70.000 || CLKPFD_FREQ_MIN_REG > 70.000)) begin + $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 70.000 to 70.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((COMPENSATION_REG != "AUTO") && + (COMPENSATION_REG != "BUF_IN") && + (COMPENSATION_REG != "INTERNAL"))) begin + $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are AUTO, BUF_IN or INTERNAL. Instance: %m", MODULE_NAME, COMPENSATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 15))) begin + $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 15. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKIN_INVERTED_REG !== 1'b0) && (IS_CLKIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-143] IS_CLKIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER_REG < 0.000 || REF_JITTER_REG > 0.999)) begin + $display("Error: [Unisim %s-150] REF_JITTER attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_WAIT_REG != "TRUE") && + (STARTUP_WAIT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1335.000)) begin + $display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1335.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MIN_REG < VF_MIN || VCOCLK_FREQ_MIN_REG > VF_MIN)) begin + $display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute is %3.3f. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG, VF_MIN); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); + + + clkfb_div_fint = CLKFBOUT_MULT_REG; + clkfbm1_div = CLKFBOUT_MULT_REG; + clkind_div = DIVCLK_DIVIDE_REG; + period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + if (CLKIN_PERIOD_REG < 3.000) + fb_delay_max = CLKIN_PERIOD_REG; + else + fb_delay_max = 3.000; + pll_lock_time = 12; + lock_period_time = 10; + md_product = clkfb_div_fint * DIVCLK_DIVIDE_REG; + m_product = clkfb_div_fint; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + + clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG); + clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG); + clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE_REG, 0.50); + clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50); + tmp_string = "CLKOUT0_PHASE"; + clkout_dly_cal (clkout0_dly, CLKOUT0_DIVIDE_REG, CLKOUT0_PHASE_REG, tmp_string); + tmp_string = "CLKOUT1_PHASE"; + clkout_dly_cal (clkout1_dly, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, tmp_string); + tmp_string = "CLKFBOUT_PHASE"; + clkout_dly_cal (clkfbm1_dly, clkfb_div_fint, CLKFBOUT_PHASE_REG, tmp_string); + + case (clkfb_div_fint) + 2 : begin pll_cp = 4'd3; pll_res = 4'd7; end + 3 : begin pll_cp = 4'd5; pll_res = 4'd15;end + 4 : begin pll_cp = 4'd7; pll_res = 4'd15;end + 5 : begin pll_cp = 4'd7; pll_res = 4'd11;end + 6 : begin pll_cp = 4'd13; pll_res = 4'd7; end + 7 : begin pll_cp = 4'd14; pll_res = 4'd11;end + 8 : begin pll_cp = 4'd14; pll_res = 4'd13;end + 9 : begin pll_cp = 4'd15; pll_res = 4'd13;end + 10 : begin pll_cp = 4'd15; pll_res = 4'd3; end + 11 : begin pll_cp = 4'd14; pll_res = 4'd5; end + 12 : begin pll_cp = 4'd15; pll_res = 4'd5; end + 13 : begin pll_cp = 4'd15; pll_res = 4'd9; end + 14 : begin pll_cp = 4'd13; pll_res = 4'd1; end + 15 : begin pll_cp = 4'd15; pll_res = 4'd14; end + 16 : begin pll_cp = 4'd14; pll_res = 4'd1; end + 17 : begin pll_cp = 4'd15; pll_res = 4'd1; end + 18 : begin pll_cp = 4'd15; pll_res = 4'd1; end + 19 : begin pll_cp = 4'd15; pll_res = 4'd1; end + 20 : begin pll_cp = 4'd14; pll_res = 4'd6; end + 21 : begin pll_cp = 4'd14; pll_res = 4'd6; end + 22 : begin pll_cp = 4'd15; pll_res = 4'd6; end + 23 : begin pll_cp = 4'd15; pll_res = 4'd6; end + 24 : begin pll_cp = 4'd14; pll_res = 4'd10; end + 25 : begin pll_cp = 4'd14; pll_res = 4'd10; end + 26 : begin pll_cp = 4'd14; pll_res = 4'd10; end + 27 : begin pll_cp = 4'd13; pll_res = 4'd10; end + 28 : begin pll_cp = 4'd6; pll_res = 4'd2; end + 29 : begin pll_cp = 4'd6; pll_res = 4'd2; end + 30 : begin pll_cp = 4'd6; pll_res = 4'd2; end + 31 : begin pll_cp = 4'd13; pll_res = 4'd6; end + 32 : begin pll_cp = 4'd12; pll_res = 4'd10; end + 33 : begin pll_cp = 4'd6; pll_res = 4'd12; end + 34 : begin pll_cp = 4'd6; pll_res = 4'd12; end + 35 : begin pll_cp = 4'd5; pll_res = 4'd2; end + 36 : begin pll_cp = 4'd3; pll_res = 4'd4; end + 37 : begin pll_cp = 4'd3; pll_res = 4'd4; end + 38 : begin pll_cp = 4'd3; pll_res = 4'd4; end + 39 : begin pll_cp = 4'd3; pll_res = 4'd4; end + 40 : begin pll_cp = 4'd3; pll_res = 4'd4; end + 41 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 42 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 43 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 44 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 45 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 46 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 47 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 48 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 49 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 50 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 51 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 52 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 53 : begin pll_cp = 4'd2; pll_res = 4'd8; end + 54 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 55 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 56 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 57 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 58 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 59 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 60 : begin pll_cp = 4'd4; pll_res = 4'd12; end + 61 : begin pll_cp = 4'd2; pll_res = 4'd4; end + 62 : begin pll_cp = 4'd2; pll_res = 4'd4; end + 63 : begin pll_cp = 4'd2; pll_res = 4'd4; end + 64 : begin pll_cp = 4'd2; pll_res = 4'd4; end + endcase + + case (clkfb_div_fint) + 1 : begin + drp_lock_ref_dly = 32'd6; + drp_lock_fb_dly = 32'd6; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 2 : begin + drp_lock_ref_dly = 32'd6; + drp_lock_fb_dly = 32'd6; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 3 : begin + drp_lock_ref_dly = 32'd8; + drp_lock_fb_dly = 32'd8; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 4 : begin + drp_lock_ref_dly = 32'd11; + drp_lock_fb_dly = 32'd11; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 5 : begin + drp_lock_ref_dly = 32'd14; + drp_lock_fb_dly = 32'd14; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 6 : begin + drp_lock_ref_dly = 32'd17; + drp_lock_fb_dly = 32'd17; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 7 : begin + drp_lock_ref_dly = 32'd19; + drp_lock_fb_dly = 32'd19; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 8 : begin + drp_lock_ref_dly = 32'd22; + drp_lock_fb_dly = 32'd22; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 9 : begin + drp_lock_ref_dly = 32'd25; + drp_lock_fb_dly = 32'd25; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 10 : begin + drp_lock_ref_dly = 32'd28; + drp_lock_fb_dly = 32'd28; + drp_lock_cnt = 32'd1000; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 11 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd900; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 12 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd825; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 13 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd750; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 14 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd700; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 15 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd650; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 16 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd625; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 17 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd575; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 18 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd550; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 19 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd525; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 20 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd500; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 21 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd475; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 22 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd450; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 23 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd425; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 24 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd400; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 25 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd400; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 26 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd375; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 27 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd350; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 28 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd350; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 29 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd325; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 30 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd325; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 31 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd300; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 32 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd300; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 33 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd300; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 34 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd275; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 35 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd275; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 36 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd275; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 37 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 38 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 39 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 40 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 41 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 42 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 43 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 44 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 45 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 46 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 47 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 48 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 49 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 50 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 51 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 52 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 53 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 54 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 55 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 56 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 57 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 58 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 59 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 60 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 61 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 62 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 63 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + 64 : begin + drp_lock_ref_dly = 32'd31; + drp_lock_fb_dly = 32'd31; + drp_lock_cnt = 32'd250; + drp_lock_sat_high = 32'd1001; + drp_unlock_cnt = 32'd1; + end + endcase + dr_sram[8] = {3'bx, 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; + dr_sram[10] = {3'bx, 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {1'bx, xiphy_mode[1], xiphy_mode[0],3'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; + dr_sram[20] = {3'bx, 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; + dr_sram[21] = {8'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; + dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; + dr_sram[23] = {2'bx, clkfbin_edge, clkfbin_nocnt, clkfbin_ht[5:0], clkfbin_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[28] = {11'bx, 5'b0}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + end + + initial + begin + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_lost_val = 500; + clkfb_lost_val = 500; + period_avg = 0; + period_fb = 0; + period_vco = 0; + period_vco1 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + clkvco_rm_cnt = 0; + fb_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fbm1_comp_delay = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + clkfb_tst = 1'b0; + clkout_en = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tmp2_dly = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + clkout_mux = 3'b0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + drdy_out = 0; + drdy_out1 = 0; + locked_out1 = 0; + locked_out_tmp = 0; + do_out1 = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 3'b000; + clkout0_out = 0; + clk0_cnt = 9'b0; + clk1_cnt = 9'b0; + clkout0_out = 0; + clkout1_out = 0; + clk0_out = 0; + clk1_out = 0; + clkind_edgei = 0; + clkind_nocnti = 0; + clkind_hti = 0; + clkind_lti = 0; + clkind_divi = 1; + clkfbm1_div = 1; + clkfbm1_div1 = 0; + clkfbm1_cnt = 8'b0; + clkind_cnt = 8'b0; + clkfbm1_nf_out = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clkfbm1_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clkfbm1_cnt = 8'b0; + clkfbm2_cnt = 8'b0; + clkfb_out = 0; + clkfbm1_nf_out = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign CLKOUT0 = clkout0_out; + assign CLKOUT0B = ~clkout0_out; + assign CLKOUT1 = clkout1_out; + assign CLKOUT1B = ~clkout1_out; + assign CLKFBOUT = clkfb_out; +// assign clkoutxiphy_int = xiphy_mode[1] ? (xiphy_mode[0] ? clkind_out : clkvco_by2) : (xiphy_mode[0] ? clkvco : clkvco_2x); + assign clkoutxiphy_int = xiphy_mode[1] ? clkvco_by2 : (xiphy_mode[0] ? clkvco : clkvco_2x); + assign CLKOUTPHY = xiphyen_sync & clkoutxiphy_int; + + assign glock = (startup_wait_sig) ? locked_out_tmp : 1; // Are these needed + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + +initial +begin + init_chk = 0; + #2; + init_chk = 1; + end +always @(posedge init_chk ) +begin + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (($time > 1) && (CLKIN_PERIOD_REG > clkin_chk_t1 || CLKIN_PERIOD_REG < clkin_chk_t2)) + begin + $display ("Error: [Unisim %s-2] The attribute CLKIN_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns. Instance %m.", MODULE_NAME, CLKIN_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + #1 $finish; + end + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_REG) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG); + + if (($time > 1) && (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG)) + begin + $display ("Error: [Unisim %s-3] The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + clkpfd_freq_init_chk = (1000.0) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG); + + if ( ($time > 1) && (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG)) begin + $display ("Error: [Unisim %s-4] The calculation of PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + end + + assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0; + assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkin_in or posedge rst_input) + begin + if (rst_input) + rst_in <= 1; + else + rst_in <= rst_input ; + end + + // DRP port read write + + assign do_out = dr_sram[daddr_lat]; + + always @(posedge dclk_in or posedge glblGSR) + if (glblGSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 3'b000; + end else begin + if (den_in == 1) begin + valid_daddr = addr_is_valid(daddr_in); + if (drp_lock == 1) begin + $display("Warning: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); + end else begin + drp_lock <= 1; + daddr_lat <= daddr_in; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001; + end +// if (valid_daddr && ( daddr_in == 7'b1011100 || daddr_in == 7'b1001111 || +// daddr_in == 7'b1001110 || (daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) || +// daddr_in == 7'b0010110 || (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010))) begin +// end +// else begin + if (valid_daddr == 0) begin + $display("Warning: [Unisim %s-6] Address DADDR=%b is unsupported at time %t. Instance %m.", MODULE_NAME, DADDR, $time); + end + + if (dwe_in == 1) begin // write process + if (rst_input == 1) begin +// if (valid_daddr && +// ((daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) || // 8 - 11 +// (daddr_in >= 7'b0010100 && daddr_in <= 7'b0010110) || // 20 - 22 +// (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || // 24 - 26 +// daddr_in == 7'b1001110 || // 78 +// daddr_in == 7'b1001111 || // 79 +// daddr_in == 7'b1011100)) begin // 92 + if (valid_daddr) dr_sram[daddr_in] <= di_in; +// end + if (daddr_in == 7'b0001000) // 8 + clkout_hl_para_drp (clk0_lt, clk0_ht, di_in, daddr_in); + if (daddr_in == 7'b0001001) // 9 + clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); + if (daddr_in == 7'b0001010) // 10 + clkout_hl_para_drp (clk1_lt, clk1_ht, di_in, daddr_in); + if (daddr_in == 7'b0001011) // 11 + clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); + if (daddr_in == 7'b0010100) begin // 20 + clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, di_in, daddr_in); + clkfbtmp_divi = clkfbm1_ht + clkfbm1_lt; + if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN)) + $display("Error: [Unisim %s-7] DI at Address DADDR=%b is %h at at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d. Instance %m.", MODULE_NAME, daddr_in, di_in, $time, clkfbtmp_divi, M_MIN, M_MAX); + end + if (daddr_in == 7'b0010101) begin // 21 + clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); + clkfbtmp_nocnti = di_in[12]; + end + + if (daddr_in == 7'b0010110) begin // 22 + clkind_lti = {2'b00, di_in[5:0]}; + clkind_hti = {2'b00, di_in[11:6]}; + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnt <= di_in[12]; + clkind_nocnti = di_in[12]; + clkind_edgei = di_in[13]; + clkind_edge <= di_in[13]; + if (di_in[12] == 1) + clkind_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkind_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkind_divi = 64 + clkind_hti; + else if (di_in[11:6] == 6'b0) + clkind_divi = 64 + clkind_lti; + else + clkind_divi = clkind_hti + clkind_lti; + + clkind_div <= clkind_divi; + if (clkind_divi > D_MAX || (clkind_divi < D_MIN && clkind_nocnti == 0)) + $display("Error: [Unisim %s-8] DI at Address DADDR=%b is %h at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d. Instance %m.", MODULE_NAME, daddr_in, di_in, $time, clkind_divi, D_MIN, D_MAX); + end + end + else begin + $display("Error: [Unisim %s-9] RST is low at time %t. RST needs to be high when changing paramters through DRP. Instance %m ", MODULE_NAME, $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001; + end + else begin + drp_lock <= 0; + drp_lock_lat_cnt <= 3'b000; + drdy_out <= 1; + end + end + if (drdy_out == 1) drdy_out <= 0; + end + + function addr_is_valid; + input [6:0] daddr_funcin; + begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) begin + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) addr_is_valid = 0; + end + if (addr_is_valid == 1) begin + if ((daddr_funcin >= 7'b0001000 && daddr_funcin <= 7'b0001011) || // 8 - 11 + (daddr_funcin >= 7'b0010100 && daddr_funcin <= 7'b0010110) || // 20 - 22 + (daddr_funcin >= 7'b0011000 && daddr_funcin <= 7'b0011010) || // 24 - 26 + daddr_funcin == 7'b0011100 || // 28 + daddr_funcin == 7'b1001110 || // 78 + daddr_funcin == 7'b1001111 || // 79 + daddr_funcin == 7'b1011100) begin // 92 + addr_is_valid = 1; + end + else begin + addr_is_valid = 0; + end + end + end + endfunction + + +// Determine clock period + always @(posedge pll_locked_tmp1) + begin + pchk_tmp1 = CLKIN_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-10] input CLKIN period (%f) and attribute CLKIN_PERIOD (%f) are not same. Instance %m.", MODULE_NAME, period_avg, CLKIN_PERIOD_REG); + end + end + + always @(posedge clkin_in or posedge rst_in) + if (rst_in) + begin + clkin_period[0] <= period_vco_target; + clkin_period[1] <= period_vco_target; + clkin_period[2] <= period_vco_target; + clkin_period[3] <= period_vco_target; + clkin_period[4] <= period_vco_target; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end + else begin + clkin_edge <= $time; + if (clkin_edge != 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4] or period_avg) + begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp = clkin_period[1] - clkin_period[0]; + + if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + clkin_period[3] + clkin_period[4])/5; + end + + always @(period_avg or lock_period or clkind_div) + if (period_avg > 500 && lock_period == 1) begin + clkin_lost_val = ((period_avg * 1.5) / 500) - 1; + clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1; + end + + assign init_trig = 1; + always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge) + clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); + always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge) + clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); + always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge) + clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); + always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge) + clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge); + + +// Unlock due to jitter + + always @(clkin_jit or rst_in ) + begin + if (rst_in) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2) begin + if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + end + +// Determine feedback delay - only internal feedback + + always @(posedge clkin_in ) + if (fb_delay_found) clkfb_tst <= 1'b0; + else clkfb_tst <= ~clkfb_tst; + + always @( posedge clkfb_tst ) + delay_edge = $time; + + assign clkfbin_sel = ((COMPENSATION_BIN == COMPENSATION_INTERNAL) || + ((COMPENSATION_BIN == COMPENSATION_AUTO) && (CLKFBIN === 1'bz))); + + assign CLKFBIN_int = clkfbin_sel && clkfb_out || ~clkfbin_sel && clkfb_in; + + always @( posedge rst_in ) + begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end + + always @(posedge CLKFBIN_int ) + if (clkfbin_sel == 1 ) begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b1; + end else if (fb_delay_found_tmp == 1'b0 ) begin + if ( delay_edge != 0) begin + fb_delay <= ($time - delay_edge); + fb_delay_found_tmp <= 1'b1; + end else begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end + end + + always @(negedge clkfb_tst or negedge fb_delay_found_tmp) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay) + if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning: [Unisim %s-11] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m.", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); + end + + + always @(fb_delay_found_tmp) + fb_delay_found <= #1000 fb_delay_found_tmp; + + always @(period_avg or clkind_div or clkfbm1_div) + begin + if (period_avg > 0 ) + begin + md_product = clkind_div * clkfbm1_div; + m_product = clkfbm1_div; + m_product2 = clkfbm1_div / 2; + period_fb = period_avg * clkind_div; + period_vco = period_fb / clkfbm1_div; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco_mf = period_avg * 8; + period_vco_rm = period_fb % clkfbm1_div; + if (period_vco_rm > 1) + begin + if (period_vco_rm > m_product2) + begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else + begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbm1_div; + clkin_dly_t = period_avg * (clkind_div + 1.25); + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + end + + always @( clkin_in ) // Why these delays? + clkpll_tmp1 <= #(period_avg) clkin_in; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(clkvco or clkvco_lk_tmp or rst_in) + begin + if (rst_in) + clkvco = 0; + else + clkvco = clkvco_lk_tmp; + end + +// Xiphy clocks + + always @(posedge clkvco or negedge clkvco or posedge rst_in or negedge xiphyen_sync) + begin + if (!xiphyen_sync || rst_in) + clkvco_2x <= 0; + else + begin + clkvco_2x <= 1; + #(period_vco/ 4) + clkvco_2x <= 0; + end + end + + always @(posedge clkvco or posedge rst_in) + begin + if (!xiphyen_sync || rst_in) + clkvco_by2 <= 0; + else + clkvco_by2 <= ~clkvco_by2; + end + + always @(posedge clkvco or posedge rst_in) + begin + if (rst_in) begin + clkvco_by8 <= 1'b0; + clkvco_cnt <= 2'b0; + end + else begin + if (clkvco_cnt == 2'b0) clkvco_by8 <= ~clkvco_by8; + clkvco_cnt <= clkvco_cnt + 2'b01; + end + end + + always @(negedge clkvco_by8 or posedge rst_in) begin + if (rst_in) begin + xiphyen_sync2 <= 1'b0; + xiphyen_sync1 <= 1'b0; + end + else begin + xiphyen_sync2 <= xiphyen_in; + xiphyen_sync1 <= xiphyen_sync2; + end + end + + always @(negedge clkvco or posedge rst_in) begin + if (rst_in) begin + xiphyen_sync <= 1'b0; + end + else if (clkvco_cnt[1:0] == 2'b0) begin + xiphyen_sync <= xiphyen_sync1; + end + end + +// VCO clock generation + + always @(posedge clkpll) + begin + if (pll_locked_tm ==1) + begin + clkvco_lk_tmp <= 1; + clkvco_rm_cnt = 0; + clkout_en_t <= 0; + vcoflag = 0; + if ( period_vco_cmp_flag == 1) + begin + for (ik2=1; ik2 < m_product; ik2=ik2+1) + begin + vcoflag = 1; + clkout_en_t <= ik2; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik2; + end + else if ( period_vco_cmp_flag == 2 ) + begin + vcoflag = 1; + for (ik3=1; ik3 < m_product; ik3=ik3+1) + begin + clkout_en_t <= ik3; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik3; + end + else + begin + vcoflag = 1; + for (ik4=1; ik4 < m_product; ik4=ik4+1) + begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + end + #(period_vco_half) clkvco_lk_tmp <= 0; + if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) + begin + for (ik4=1; ik4 < m_product; ik4=ik4+1) + begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or lock_period) + begin + if (lock_period == 1) + begin + val_tmp = period_avg * DIVCLK_DIVIDE; + fbm1_comp_delay = period_vco * clkfbm1_dly; + end + dly_tmp1 = fb_delay + fbm1_comp_delay; + dly_tmp_int = 1; + dly_tmp = dly_tmp1; + if (dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + + always @(clkvco) + begin + if (clkout_en) + begin + clkout_mux[0] = clkvco; + clkout_mux[1] <= clkvco; + clkout_mux[2] <= clkvco; + end + end + + assign clk0in = clkout_mux[0]; + assign clk1in = clkout_mux[1]; + assign clkfbm1in = clkout_mux[2]; + + assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; + assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; + assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; + + always @(negedge clk0in or posedge rst_in) + begin + if (rst_in) + clk0_dly_cnt <= 6'b0; + else + if (clk0_dly_cnt < clkout0_dly && clkout_en == 1) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in) + begin + if (rst_in) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + end + + always @(negedge clkfbm1in or posedge rst_in) + begin + if (rst_in) + clkfbm1_dly_cnt <= 6'b0; + else + if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en == 1) + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + end + + always @(clk0_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkout0_out = clk0_out; + else + if(rst_in == 1'b0) + clkout0_out = clkfb_tst; + end + + always @(clk1_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkout1_out = clk1_out; + else + if(rst_in == 1'b0) + clkout1_out = clkfb_tst; + end + + always @(clkfbm1_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkfb_out = clkfbm1_out; + else + if(rst_in == 1'b0) + clkfb_out = clkfb_tst; + end + +// Generate unlock signal + always begin + if (rst_in) + clk_osc = 0; + else + clk_osc = ~clk_osc; + #OSC_P2; + end + + always @(posedge clkpll or negedge clkpll) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int) begin + clkfb_p <= 1; + clkfb_p <= #100 0; + end + + + always @(posedge clk_osc or posedge rst_in or posedge clkin_p) + begin + if (rst_in == 1) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out == 1) begin + @(posedge clkpll) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out <= 0; + end + else + clkinstopped_out <= 1; + end + end + + always @(posedge clkinstopped_out or posedge rst_in) + begin + if (rst_in); + else begin + $display("Warning: [Unisim %s-12] Input CLKIN is stopped at time %t. Reset is required when input clock returns. Instance %m.", MODULE_NAME, $time); + end + end + + always @(posedge clk_osc or posedge rst_in or posedge clkfb_p) + begin + if (rst_in == 1 || clkfb_p == 1) begin + clkfbstopped_out <= 0; + clkfb_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfb_lost_cnt < clkfb_lost_val) begin + clkfb_lost_cnt <= clkfb_lost_cnt + 1; + clkfbstopped_out <= 0; + end + else + clkfbstopped_out <= 1; + end + end + + always @(clkin_jit or rst_in ) + begin + if (rst_in) + clkpll_jitter_unlock = 0; + else + begin + if (pll_locked_tmp2) + begin + if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + end + end + + assign pll_unlock1 = (clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = ( clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // Generate lock signal + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + begin + if (clkout_en0_tmp==0 ) + clkout_en0 <= 0; + else + begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #(period_vco-1) clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in ) + if (rst_in) + clkout_en <= 0; + else + clkout_en <= clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 <= pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_in) + if (rst_in) begin + assign pll_locked_tmp2 = 0; + assign clkout_en0 = 0; + end + else begin + deassign pll_locked_tmp2; + deassign clkout_en0; + end + + assign locked_out = (pll_locked_tm && pll_locked_tmp2_dly && ~pll_unlock && !unlock_recover) ? 1 : 0; + + always @(rst_in or locked_out) + if (rst_in == 1) + locked_out_tmp <= #1000 0; + else + locked_out_tmp <= locked_out; + +// end of lock + + always @(posedge clk0in or negedge clk0in or posedge rst_in) + begin + if (rst_in) + begin + clk0_cnt <= 9'b0; + clk0_out <= 0; + end + else if (clk0ps_en) + begin + begin + if (clk0_cnt < clk0_div1) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 9'b0; + if (clk0_cnt < clk0_ht1) + clk0_out <= 1; + else + clk0_out <= 0; + end + end + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in) + begin + if (rst_in) + begin + clk1_cnt <= 9'b0; + clk1_out <= 0; + end + else if (clk1ps_en) + begin + if (clk1_cnt < clk1_div1) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 9'b0; + if (clk1_cnt < clk1_ht1) + clk1_out <= 1; + else + clk1_out <= 0; + end + end + + always @(posedge clkpll or negedge clkpll or posedge rst_in) + begin + if (rst_in) begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + else if (clkout_en) + begin + if (clkind_cnt < clkind_div1) + clkind_cnt <= clkind_cnt + 1; + else + clkind_cnt <= 8'b0; + if (clkind_cnt < clkind_ht1) + clkind_out <= 1; + else + clkind_out <= 0; + end + else begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + end + + always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in) + begin + if (rst_in) begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + else if (clkfbm1ps_en) + begin + if (clkfbm1_cnt < clkfbm1_div1) + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 8'b0; + if (clkfbm1_cnt < clkfbm1_ht1) + clkfbm1_nf_out <= 1; + else + clkfbm1_nf_out <= 0; + end + else + begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + end + + assign clkfbm1_out = clkfbm1_nf_out; + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int or posedge rst_in) + begin + if (rst_in) begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + else if (clkout_en) begin + if (clkfbm2_cnt < clkfbm2_div1) + clkfbm2_cnt <= clkfbm2_cnt + 1; + else + clkfbm2_cnt <= 8'b0; + if (clkfbm2_cnt < clkfbm2_ht1) + clkfbm2_out <= 1; + else + clkfbm2_out <= 0; + end + else begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + end + +// Phase task + task clkout_dly_cal; + output [5:0] clkout_dly; + input clkdiv; + input clk_ps; + input reg [160:0] clk_ps_name; + integer clkdiv; + real clk_ps; + real clk_ps_rl; + real clk_dly_rl, clk_dly_rem; + integer clkout_dly_tmp; + begin + if (clk_ps < 0.0) + clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; + else + clk_dly_rl = clk_ps * clkdiv / 360.0; + +// clkout_dly_tmp = $rtoi(clk_dly_rl); + clkout_dly_tmp = clk_dly_rl; + + if (clkout_dly_tmp > 63) begin + $display("Warning: [Unisim %s-13] Attribute %s is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting capability. Instance %m ", MODULE_NAME, clk_ps_name, clk_ps); + clkout_dly = 6'b111111; + end + else + clkout_dly = clkout_dly_tmp; + end + + endtask + +// Task to calculate final ht based on clk_edge + task clkout_pm_cal; + output [8:0] clk_ht1; + output [8:0] clk_div; + output [8:0] clk_div1; + input [7:0] clk_ht; + input [7:0] clk_lt; + input clk_nocnt; + input clk_edge; + begin + if (clk_nocnt ==1) begin + clk_div = 9'b000000001; + clk_div1 = 9'b000000001; + clk_ht1 = 9'b000000001; + end + else begin + if ( clk_edge == 1) + clk_ht1 = 2 * clk_ht + 1; + else + clk_ht1 = 2 * clk_ht; + clk_div = clk_ht + clk_lt ; + clk_div1 = 2 * clk_div -1; + end + end + endtask + + // Task to calculate ht, lt based on duty cycle + // also detects of clk_edge needs to be 1 + task clk_out_para_cal; + output [7:0] clk_ht; + output [7:0] clk_lt; + output clk_nocnt; + output clk_edge; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + integer CLKOUT_DIVIDE; + real CLKOUT_DUTY_CYCLE; + real tmp_value, tmp_value0, tmp_value_rm; + integer tmp_value_round, tmp_value1, tmp_value_r; + real tmp_value2; + real tmp_value_rm1, tmp_value_r1; + integer tmp_value_r2; + begin + + tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; + tmp_value_r = $rtoi(tmp_value0); + tmp_value_rm = tmp_value0 - tmp_value_r; + if (tmp_value_rm < 0.1) + tmp_value = tmp_value_r * 1.0; + else if (tmp_value_rm > 0.9) + tmp_value = 1.0 * tmp_value_r + 1.0; + else begin + tmp_value_r1 = tmp_value0 * 2.0; + tmp_value_r2 = $rtoi(tmp_value_r1); + tmp_value_rm1 = tmp_value_r1 - tmp_value_r2; + if (tmp_value_rm1 > 0.995) + tmp_value = tmp_value0 + 0.002; + else + tmp_value = tmp_value0; + end + tmp_value_round = tmp_value * 2.0; + tmp_value1 = tmp_value_round % 2; + tmp_value2 = CLKOUT_DIVIDE - tmp_value; + + + if ((tmp_value2) >= O_MAX_HT_LT) begin + clk_lt = 8'b10000000; + end + else begin + if (tmp_value2 < 1.0) + clk_lt = 1; + else + if ( tmp_value1 != 0) + clk_lt = $rtoi(tmp_value2) + 1; + else + clk_lt = $rtoi(tmp_value2); + end + + if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT) + clk_ht = 8'b10000000; + else + clk_ht = CLKOUT_DIVIDE - clk_lt; + + clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; + if ( tmp_value < 1.0) + clk_edge = 1; + else if (tmp_value1 != 0) + clk_edge = 1; + else + clk_edge = 0; + end + endtask + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.5; + CLK_DUTY_CYCLE_MIN_rnd = 0.5; + CLK_DUTY_CYCLE_MAX = 0.5; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (CLKOUT_DIVIDE - 0.5)/ CLKOUT_DIVIDE; + end + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + $display(" Instance %m "); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + task clkout_delay_para_drp; + output [5:0] clkout_dly; + output clk_nocnt; + output clk_edge; + input [15:0] di_in; + input [6:0] daddr_in; + begin + clkout_dly = di_in[5:0]; + clk_nocnt = di_in[6]; + clk_edge = di_in[7]; + end + endtask + + task clkout_hl_para_drp; + output [6:0] clk_lt; + output [6:0] clk_ht; + input [15:0] di_in_tmp; + input [6:0] daddr_in_tmp; + begin +// if (di_in_tmp[12] != 1) begin +// $display("Error: [Unisim %s-34] Input DI is %h at address DADDR=%b at time %t. The bit 12 needs to be set to 1. Instance %m ", MODULE_NAME, di_in_tmp, daddr_in_tmp, $time); +// end + if ( di_in_tmp[5:0] == 6'b0) + clk_lt = 7'b1000000; + else + clk_lt = { 1'b0, di_in_tmp[5:0]}; + if (di_in_tmp[11:6] == 6'b0) + clk_ht = 7'b1000000; + else + clk_ht = { 1'b0, di_in_tmp[11:6]}; + end + endtask + +// end behavioral model + + specify + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (PWRDWN => LOCKED) = (100:100:100, 100:100:100); + (RST => LOCKED) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKIN, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUTPHY, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKIN, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUTPHY, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PLLE3_BASE.v b/verilog/src/unisims/PLLE3_BASE.v new file mode 100644 index 0000000..6a2f33a --- /dev/null +++ b/verilog/src/unisims/PLLE3_BASE.v @@ -0,0 +1,168 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Base Phase-Locked Loop (PLL) +// /___/ /\ Filename : PLLE3_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE3_BASE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer CLKFBOUT_MULT = 5, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN_PERIOD = 0.000, + parameter integer CLKOUT0_DIVIDE = 1, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUTPHY_MODE = "VCO_2X", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUTPHY, + output LOCKED, + + input CLKFBIN, + input CLKIN, + input CLKOUTPHYEN, + input PWRDWN, + input RST +); + +// define constants + localparam MODULE_NAME = "PLLE3_BASE"; + + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end + + wire OPEN_DRDY; + wire OPEN_PSDONE; + wire OPEN_FBS; + wire OPEN_INS; + wire [15:0] OPEN_DO; + + PLLE3_ADV #( + .CLKFBOUT_MULT(CLKFBOUT_MULT), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN_PERIOD(CLKIN_PERIOD), + .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUTPHY_MODE(CLKOUTPHY_MODE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .IS_CLKFBIN_INVERTED(IS_CLKFBIN_INVERTED), + .IS_CLKIN_INVERTED(IS_CLKIN_INVERTED), + .IS_PWRDWN_INVERTED(IS_PWRDWN_INVERTED), + .IS_RST_INVERTED(IS_RST_INVERTED), + .REF_JITTER(REF_JITTER), + .STARTUP_WAIT(STARTUP_WAIT) + ) pll_adv_1 ( + .CLKFBOUT (CLKFBOUT), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUTPHY (CLKOUTPHY), + .CLKOUTPHYEN (CLKOUTPHYEN), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .LOCKED (LOCKED), + .CLKFBIN (CLKFBIN), + .CLKIN (CLKIN), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PWRDWN(PWRDWN), + .RST (RST) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (RST => LOCKED) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKIN, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUTPHY, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKIN, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUTPHY, 0:0:0, notifier); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PLLE4_ADV.v b/verilog/src/unisims/PLLE4_ADV.v new file mode 100644 index 0000000..4902a89 --- /dev/null +++ b/verilog/src/unisims/PLLE4_ADV.v @@ -0,0 +1,2069 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.4 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Advanced Phase-Locked Loop (PLL) +// /___/ /\ Filename : PLLE4_ADV.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/22/2013 700625 - update PLLE3 for yml changes +// 02/28/2013 703674 - update vco_half attribute +// 03/25/2013 PLLE3 sync5 changes +// 04/04/2013 709484 - add PFD check +// 04/02/2013 709723 - fix Lock for lost clock +// 04/08/2013 709729 - Fix clkoutxiphy for CLKIN mode +// 04/09/2013 709725 - Fix clkout0 frequency after reset +// 04/09/2013 709726 - Fix clkout0 frequency +// 04/12/2013 Invertible pin changes +// 04/16/2013 Writer and invertible pin changes +// 04/22/2013 713959 - clkoutphy frequency fix after reset +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE4_ADV #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", + parameter real CLKIN_FREQ_MAX = 1066.000, + parameter real CLKIN_FREQ_MIN = 70.000, + parameter real CLKPFD_FREQ_MAX = 667.500, + parameter real CLKPFD_FREQ_MIN = 70.000, + parameter real VCOCLK_FREQ_MAX = 1500.000, + parameter real VCOCLK_FREQ_MIN = 750.000, +`endif + parameter integer CLKFBOUT_MULT = 5, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN_PERIOD = 0.000, + parameter integer CLKOUT0_DIVIDE = 1, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUTPHY_MODE = "VCO_2X", + parameter COMPENSATION = "AUTO", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUTPHY, + output [15:0] DO, + output DRDY, + output LOCKED, + + input CLKFBIN, + input CLKIN, + input CLKOUTPHYEN, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PWRDWN, + input RST +); + +`ifndef XIL_TIMING + localparam real CLKIN_FREQ_MAX = 1066.000; + localparam real CLKIN_FREQ_MIN = 70.000; + localparam real CLKPFD_FREQ_MAX = 667.500; + localparam real CLKPFD_FREQ_MIN = 70.000; + localparam real VCOCLK_FREQ_MAX = 1500.000; + localparam real VCOCLK_FREQ_MIN = 750.000; +`endif + +// define constants + localparam MODULE_NAME = "PLLE4_ADV"; + +// Parameter encodings and registers + localparam CLKOUTPHY_MODE_VCO = 1; + localparam CLKOUTPHY_MODE_VCO_2X = 0; + localparam CLKOUTPHY_MODE_VCO_HALF = 2; + localparam COMPENSATION_AUTO = 0; + localparam COMPENSATION_BUF_IN = 1; + localparam COMPENSATION_INTERNAL = 3; + localparam COMPENSATION_PHY_ALIGN = 2; + localparam STARTUP_WAIT_FALSE = 0; + localparam STARTUP_WAIT_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "PLLE4_ADV_dr.v" +`else + localparam [4:0] CLKFBOUT_MULT_REG = CLKFBOUT_MULT; + localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; + localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; + localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; + localparam real CLKIN_PERIOD_REG = CLKIN_PERIOD; + localparam [7:0] CLKOUT0_DIVIDE_REG = CLKOUT0_DIVIDE; + localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; + localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; + localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; + localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; + localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; + localparam [64:1] CLKOUTPHY_MODE_REG = CLKOUTPHY_MODE; + localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; + localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; + localparam [72:1] COMPENSATION_REG = COMPENSATION; + localparam [3:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; + localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED; + localparam [0:0] IS_CLKIN_INVERTED_REG = IS_CLKIN_INVERTED; + localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REF_JITTER_REG = REF_JITTER; + localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; + localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; + localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; +`endif + + wire [2:0] COMPENSATION_BIN; + reg attr_test; + reg attr_err; + tri0 glblGSR = glbl.GSR; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + + localparam VCOCLK_FREQ_TARGET = 1200; + localparam M_MIN = 2; + localparam M_MAX = 21; + localparam real VF_MAX = 1500.000; + localparam real VF_MIN = 750.000; + localparam D_MIN = 1; + localparam D_MAX = 15; +// localparam O_MIN = 1; // not used + localparam O_MAX = 256; + localparam O_MAX_HT_LT = 128; // change from 64 + localparam REF_CLK_JITTER_MAX = 1000; + localparam OSC_P2 = 250; + + integer nBandwidth_HIGH=0; + integer nBandwidth_LOW=1; + integer nBandwidth_OPTIMIZED=2; + + tri1 p_up; + reg [160:0] tmp_string; + reg chk_ok; + reg init_chk; + real clkin_chk_t1, clkin_chk_t2; + real clkin_chk_t1_r, clkin_chk_t2_r; + integer clkin_chk_t1_i, clkin_chk_t2_i; + real clkvco_freq_init_chk; + real clkpfd_freq_init_chk; + wire [1:0] xiphy_mode; + + wire [15:0] do_out; + wire [15:0] di_in; + wire [6:0] daddr_in; + reg [15:0] do_out1; + integer clkfb_div_fint; + + wire locked_out; + reg locked_out1; + reg locked_out_tmp; + + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drdy_out, drdy_out1; + reg drp_lock; + reg [2:0] drp_lock_lat = 3'b100; + reg [2:0] drp_lock_lat_cnt; + reg [15:0] dr_sram [127:0]; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + + integer period_vco_max, period_vco_min; + integer period_vco_target, period_vco_target_half; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + integer md_product, m_product, m_product2; + integer clkout_en_val; + reg clkout0_out, clkout1_out; + + reg [7:0] clk0_ht, clk0_lt; + reg [7:0] clk1_ht, clk1_lt; + reg clk0_edge, clk1_edge; + reg clk0_nocnt, clk1_nocnt; + + reg rst_in = 1'b0; + integer clkin_period_tmp; + integer clkin_period [4:0]; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock = 1'b0; + integer clkin_jit; + integer pchk_tmp1, pchk_tmp2; + integer period_avg, period_fb; + wire clkin_in,clkfb_in; + reg clkout_en, clkout_en0_tmp, clkout_en0_tmp1=0, clkout_en0, clkout_en1; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2, pll_locked_tmp2_dly; + time clkin_edge, delay_edge; + time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay; + time dly_tmp1; + integer dly_tmp_int; + reg fb_delay_found, fb_delay_found_tmp; + real fb_delay_max; + integer period_vco_mf; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + integer period_vco_half_rm1, period_vco_half_rm2; + time pll_locked_delay, clkin_dly_t; + reg clkpll = 1'b0; + reg clkpll_tmp1 = 1'b0; + reg clkvco_lk = 1'b0, clkvco_lk_tmp = 1'b0, clkvco = 1'b0, clkvco_by2 = 1'b0, clkvco_2x = 1'b0; + reg clkvco_by8 = 1'b0; + integer i, ik2, ik3, ik4, j; + reg vcoflag = 1'b0; + integer clkout_en_t; + reg clk_osc=1'b0, clkin_p=1'b0, clkfb_p=1'b0; + reg clkinstopped_out; + reg clkfbstopped_out; + integer clkin_lost_cnt, clkfb_lost_cnt; + integer clkin_lost_val, clkfb_lost_val; + reg clkinstopped_out_dly = 0; + + reg pwron_int; + reg clkfb_tst = 1'b0; + reg [7:0] clkind_div; + reg [2:0] clkout_mux; + //reg [2:0] clk0pm_sel, clk1pm_sel, clkfbm1pm_sel; + reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti; + reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; + reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1; + reg [7:0] clkind_divi, clkind_div1, clkind_cnt, clkind_ht1; + reg clkfbtmp_nocnti; + reg clkind_edgei, clkind_nocnti; + reg clkind_out, clkind_out_tmp; + reg [6:0] clkfbm1_ht, clkfbm1_lt; + reg [6:0] clkfbin_ht, clkfbin_lt; + reg [7:0] clkind_ht, clkind_lt; + reg [7:0] clkind_hti, clkind_lti; + reg clkfbm1_nocnt, clkind_nocnt; + reg clkfbm1_edge, clkind_edge; + reg clkfbin_edge, clkfbin_nocnt; + reg clkfbm1_nf_out; + + integer period_vco1; + integer period_vco2; + reg clk0_out; + reg clk1_out; + reg clkfb_out; + wire clkfbm1_out; + reg clkfbm2_out; + reg [5:0] clk0_dly_cnt, clkout0_dly; + reg [5:0] clk1_dly_cnt, clkout1_dly; + reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; + reg [8:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; + reg [8:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; + wire init_trig, clk0in, clk1in; + + wire clkoutxiphy_int; + wire xiphyen_in; + reg xiphyen_sync=1'b0; + reg xiphyen_sync1=1'b0; + reg xiphyen_sync2=1'b0; + reg [1:0] clkvco_cnt=2'b00; + + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire [15:0] DI_delay; + wire [6:0] DADDR_delay; + + wire dwe_in; + wire den_in; + wire dclk_in; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING + assign DCLK_delay = DCLK; + + assign DADDR_delay = DADDR; + assign DEN_delay = DEN; + assign DI_delay = DI; + assign DWE_delay = DWE; +`endif + + wire CLKFBIN_int; + wire startup_wait_sig; + wire clkfbin_sel; + wire pwrdwn_in; + wire rst_input_r; + wire glock; + wire pwrdwn_in1; + wire rst_input; + wire clkfbm1in; + wire clk0ps_en, clk1ps_en; + wire clkfbm1ps_en; + reg drp_updt = 1'b0; + assign clkfb_in = CLKFBIN ^ IS_CLKFBIN_INVERTED_REG; + assign clkin_in = CLKIN ^ IS_CLKIN_INVERTED_REG; + assign xiphyen_in = CLKOUTPHYEN; + assign daddr_in = DADDR_delay; + assign di_in = DI_delay; + assign dwe_in = DWE_delay; + assign den_in = DEN_delay; + assign dclk_in = DCLK_delay; + assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_REG; + assign rst_input_r = RST ^ IS_RST_INVERTED_REG; + assign LOCKED = locked_out1; + assign DRDY = drdy_out1; + assign DO = do_out1; + + always @(locked_out_tmp) + locked_out1 = locked_out_tmp; + always @(pll_locked_tmp2) + pll_locked_tmp2_dly = pll_locked_tmp2; + always @(drdy_out) + drdy_out1 = drdy_out; + always @(do_out) + do_out1 = do_out; + // `endif // `ifndef XIL_TIMING + + assign COMPENSATION_BIN = + (COMPENSATION_REG == "AUTO") ? COMPENSATION_AUTO : + (COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN : + (COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL : + (COMPENSATION_REG == "PHY_ALIGN") ? COMPENSATION_PHY_ALIGN : + COMPENSATION_AUTO; + + assign xiphy_mode = + (CLKOUTPHY_MODE_REG == "VCO_2X") ? CLKOUTPHY_MODE_VCO_2X : + (CLKOUTPHY_MODE_REG == "VCO") ? CLKOUTPHY_MODE_VCO : + (CLKOUTPHY_MODE_REG == "VCO_HALF") ? CLKOUTPHY_MODE_VCO_HALF : + CLKOUTPHY_MODE_VCO_2X; + + assign startup_wait_sig = + (STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE : + (STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE : + STARTUP_WAIT_FALSE; + + initial begin + #1; + trig_attr = ~trig_attr; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CLKFBOUT_MULT_REG < M_MIN) || (CLKFBOUT_MULT_REG > M_MAX))) begin + $display("Error: [Unisim %s-102] CLKFBOUT_MULT attribute is set to %d. Legal values for this attribute are %d to %d. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_REG, M_MIN, M_MAX); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin + $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_FREQ_MIN_REG < 70.000 || CLKIN_FREQ_MIN_REG > 70.000)) begin + $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 70.000 to 70.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKIN_PERIOD_REG < 0.000 || CLKIN_PERIOD_REG > 14.286)) begin + $display("Error: [Unisim %s-105] CLKIN_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 14.286. Instance: %m", MODULE_NAME, CLKIN_PERIOD_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT0_DIVIDE_REG < 1) || (CLKOUT0_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-106] CLKOUT0_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin + $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin + $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin + $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CLKOUTPHY_MODE_REG != "VCO_2X") && + (CLKOUTPHY_MODE_REG != "VCO") && + (CLKOUTPHY_MODE_REG != "VCO_HALF"))) begin + $display("Error: [Unisim %s-112] CLKOUTPHY_MODE attribute is set to %s. Legal values for this attribute are VCO_2X, VCO or VCO_HALF. Instance: %m", MODULE_NAME, CLKOUTPHY_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MAX_REG < 600.000 || CLKPFD_FREQ_MAX_REG > 667.500)) begin + $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 550.000 to 667.500. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CLKPFD_FREQ_MIN_REG < 70.000 || CLKPFD_FREQ_MIN_REG > 70.000)) begin + $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 70.000 to 70.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((COMPENSATION_REG != "AUTO") && + (COMPENSATION_REG != "BUF_IN") && + (COMPENSATION_REG != "INTERNAL") && + (COMPENSATION_REG != "PHY_ALIGN"))) begin + $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are AUTO, BUF_IN, INTERNAL or PHY_ALIGN. Instance: %m", MODULE_NAME, COMPENSATION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 15))) begin + $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 15. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_CLKIN_INVERTED_REG !== 1'b0) && (IS_CLKIN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-143] IS_CLKIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin + $display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (REF_JITTER_REG < 0.000 || REF_JITTER_REG > 0.999)) begin + $display("Error: [Unisim %s-150] REF_JITTER attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((STARTUP_WAIT_REG != "TRUE") && + (STARTUP_WAIT_REG != "FALSE"))) begin + $display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1500.000)) begin + $display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1500.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (VCOCLK_FREQ_MIN_REG < VF_MIN || VCOCLK_FREQ_MIN_REG > VF_MIN)) begin + $display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute is %3.3f. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG, VF_MIN); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); + + + clkfb_div_fint = CLKFBOUT_MULT_REG; + clkfbm1_div = CLKFBOUT_MULT_REG; + clkind_div = DIVCLK_DIVIDE_REG; + period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + if (CLKIN_PERIOD_REG < 3.000) + fb_delay_max = CLKIN_PERIOD_REG; + else + fb_delay_max = 3.000; + pll_lock_time = 12; + lock_period_time = 10; + md_product = clkfb_div_fint * DIVCLK_DIVIDE_REG; + m_product = clkfb_div_fint; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + + clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG); + clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG); + clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE_REG, 0.50); + clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50); + tmp_string = "CLKOUT0_PHASE"; + clkout_dly_cal (clkout0_dly, CLKOUT0_DIVIDE_REG, CLKOUT0_PHASE_REG, tmp_string); + tmp_string = "CLKOUT1_PHASE"; + clkout_dly_cal (clkout1_dly, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, tmp_string); + tmp_string = "CLKFBOUT_PHASE"; + clkout_dly_cal (clkfbm1_dly, clkfb_div_fint, CLKFBOUT_PHASE_REG, tmp_string); + + GetMultVal(clkfb_div_fint,nBandwidth_OPTIMIZED,pll_cp,pll_res,pll_lfhf); + + GetLockDetSettings(clkfb_div_fint,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_lock_sat_high,drp_unlock_cnt); + + dr_sram[8] = {3'bx, 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; + dr_sram[10] = {3'bx, 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {1'bx, xiphy_mode[1], xiphy_mode[0],3'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; + dr_sram[20] = {3'bx, 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; + dr_sram[21] = {8'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; + dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; + dr_sram[23] = {2'bx, clkfbin_edge, clkfbin_nocnt, clkfbin_ht[5:0], clkfbin_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[28] = {11'bx, 5'b0}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + end + + initial + begin + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_lost_val = 500; + clkfb_lost_val = 500; + period_avg = 0; + period_fb = 0; + period_vco = 0; + period_vco1 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + clkvco_rm_cnt = 0; + fb_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fbm1_comp_delay = 0; + fb_delay_found = 1'b0; + fb_delay_found_tmp = 1'b0; + clkin_edge = 0; + delay_edge = 0; + clkfb_tst = 1'b0; + clkout_en = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tmp2_dly = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + clkout_mux = 3'b0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + drdy_out = 0; + drdy_out1 = 0; + locked_out1 = 0; + locked_out_tmp = 0; + do_out1 = 16'b0; + drp_lock = 0; + drp_lock_lat_cnt = 3'b000; + clkout0_out = 0; + clk0_cnt = 9'b0; + clk1_cnt = 9'b0; + clkout0_out = 0; + clkout1_out = 0; + clk0_out = 0; + clk1_out = 0; + clkind_edgei = 0; + clkind_nocnti = 0; + clkind_hti = 0; + clkind_lti = 0; + clkind_divi = 1; + clkfbm1_div = 1; + clkfbm1_div1 = 0; + clkfbm1_cnt = 8'b0; + clkind_cnt = 8'b0; + clkfbm1_nf_out = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clkfbm1_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clkfbm1_cnt = 8'b0; + clkfbm2_cnt = 8'b0; + clkfb_out = 0; + clkfbm1_nf_out = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign CLKOUT0 = clkout0_out; + assign CLKOUT0B = ~clkout0_out; + assign CLKOUT1 = clkout1_out; + assign CLKOUT1B = ~clkout1_out; + assign CLKFBOUT = clkfb_out; +// assign clkoutxiphy_int = xiphy_mode[1] ? (xiphy_mode[0] ? clkind_out : clkvco_by2) : (xiphy_mode[0] ? clkvco : clkvco_2x); + assign clkoutxiphy_int = xiphy_mode[1] ? clkvco_by2 : (xiphy_mode[0] ? clkvco : clkvco_2x); + assign CLKOUTPHY = xiphyen_sync & clkoutxiphy_int; + + assign glock = (startup_wait_sig) ? locked_out_tmp : 1; // Are these needed + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + +initial +begin + init_chk = 0; + #2; + init_chk = 1; + end +always @(posedge init_chk ) +begin + clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; + clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); + clkin_chk_t1 = 0.001 * clkin_chk_t1_i; + clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; + clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); + clkin_chk_t2 = 0.001 * clkin_chk_t2_i; + + if (($time > 1) && (CLKIN_PERIOD_REG > clkin_chk_t1 || CLKIN_PERIOD_REG < clkin_chk_t2)) + begin + $display ("Error: [Unisim %s-2] The attribute CLKIN_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns. Instance %m.", MODULE_NAME, CLKIN_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); + #1 $finish; + end + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_REG) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG); + + if (($time > 1) && (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG)) + begin + $display ("Error: [Unisim %s-3] The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); + #1 $finish; + end + clkpfd_freq_init_chk = (1000.0) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG); + + if ( ($time > 1) && (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG)) begin + $display ("Error: [Unisim %s-4] The calculation of PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted PFD frequency range. Instance %m", MODULE_NAME, clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG); + #1 $finish; + end + end + + assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0; + assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0; + + always @(posedge clkin_in or posedge rst_input) + begin + if (rst_input) + rst_in <= 1; + else + rst_in <= rst_input ; + end + + // DRP port read write + + assign do_out = dr_sram[daddr_lat]; + + always @(posedge dclk_in or posedge glblGSR) + if (glblGSR == 1) begin + drp_lock <= 0; + drp_lock_lat_cnt <= 3'b000; + drp_updt <= 1'b0; + end else begin + if (~rst_in && drp_updt) drp_updt <= 1'b0; + if (den_in == 1) begin + valid_daddr = addr_is_valid(daddr_in); + if (drp_lock == 1) begin + $display("Warning: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); + end else begin + drp_lock <= 1; + daddr_lat <= daddr_in; + drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001; + end +// if (valid_daddr && ( daddr_in == 7'b1011100 || daddr_in == 7'b1001111 || +// daddr_in == 7'b1001110 || (daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) || +// daddr_in == 7'b0010110 || (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010))) begin +// end +// else begin + if (valid_daddr == 0) begin + $display("Warning: [Unisim %s-6] Address DADDR=%b is unsupported at time %t. Instance %m.", MODULE_NAME, DADDR, $time); + end + + if (dwe_in == 1) begin // write process + if (rst_input == 1) begin +// if (valid_daddr && +// ((daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) || // 8 - 11 +// (daddr_in >= 7'b0010100 && daddr_in <= 7'b0010110) || // 20 - 22 +// (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || // 24 - 26 +// daddr_in == 7'b1001110 || // 78 +// daddr_in == 7'b1001111 || // 79 +// daddr_in == 7'b1011100)) begin // 92 + if (valid_daddr) dr_sram[daddr_in] <= di_in; + if (valid_daddr || drp_updt) drp_updt <= 1'b1; +// end + if (daddr_in == 7'b0001000) // 8 + clkout_hl_para_drp (clk0_lt, clk0_ht, di_in, daddr_in); + if (daddr_in == 7'b0001001) // 9 + clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); + if (daddr_in == 7'b0001010) // 10 + clkout_hl_para_drp (clk1_lt, clk1_ht, di_in, daddr_in); + if (daddr_in == 7'b0001011) // 11 + clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); + if (daddr_in == 7'b0010100) begin // 20 + clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, di_in, daddr_in); + clkfbtmp_divi = clkfbm1_ht + clkfbm1_lt; + if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN)) + $display("Error: [Unisim %s-7] DI at Address DADDR=%b is %h at at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d. Instance %m.", MODULE_NAME, daddr_in, di_in, $time, clkfbtmp_divi, M_MIN, M_MAX); + end + if (daddr_in == 7'b0010101) begin // 21 + clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); + clkfbtmp_nocnti = di_in[12]; + end + + if (daddr_in == 7'b0010110) begin // 22 + clkind_lti = {2'b00, di_in[5:0]}; + clkind_hti = {2'b00, di_in[11:6]}; + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnt <= di_in[12]; + clkind_nocnti = di_in[12]; + clkind_edgei = di_in[13]; + clkind_edge <= di_in[13]; + if (di_in[12] == 1) + clkind_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkind_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkind_divi = 64 + clkind_hti; + else if (di_in[11:6] == 6'b0) + clkind_divi = 64 + clkind_lti; + else + clkind_divi = clkind_hti + clkind_lti; + + clkind_div <= clkind_divi; + if (clkind_divi > D_MAX || (clkind_divi < D_MIN && clkind_nocnti == 0)) + $display("Error: [Unisim %s-8] DI at Address DADDR=%b is %h at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d. Instance %m.", MODULE_NAME, daddr_in, di_in, $time, clkind_divi, D_MIN, D_MAX); + end + if (daddr_in == 7'd24) + drp_lock_cnt = di_in[9:0]; + if (daddr_in == 7'd25) begin + drp_lock_fb_dly = di_in[14:10]; + drp_unlock_cnt = di_in[9:0]; + end + if (daddr_in == 7'd26) begin + drp_lock_ref_dly = di_in[14:10]; + drp_lock_sat_high = di_in[9:0]; + end + if (daddr_in == 7'd78) + pll_cp = {di_in[15],di_in[12],di_in[11],di_in[8]}; + if (daddr_in == 7'd79) + pll_res = {di_in[15],di_in[12],di_in[11],di_in[8]}; + end + else begin + $display("Error: [Unisim %s-9] RST is low at time %t. RST needs to be high when changing paramters through DRP. Instance %m ", MODULE_NAME, $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + if (drp_lock_lat_cnt < drp_lock_lat) begin + drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001; + end + else begin + drp_lock <= 0; + drp_lock_lat_cnt <= 3'b000; + drdy_out <= 1; + end + end + if (drdy_out == 1) drdy_out <= 0; + end + + always @ (negedge rst_in) begin + if (drp_updt) begin + clkfbtmp_divi = clkfbm1_ht + clkfbm1_lt; + check_m_settings(clkfbtmp_divi,pll_cp,pll_res,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_unlock_cnt,drp_lock_sat_high); + end + end + + function addr_is_valid; + input [6:0] daddr_funcin; + begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) begin + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) addr_is_valid = 0; + end + if (addr_is_valid == 1) begin + if ((daddr_funcin >= 7'b0001000 && daddr_funcin <= 7'b0001011) || // 8 - 11 + (daddr_funcin >= 7'b0010100 && daddr_funcin <= 7'b0010110) || // 20 - 22 + (daddr_funcin >= 7'b0011000 && daddr_funcin <= 7'b0011010) || // 24 - 26 + daddr_funcin == 7'b0011100 || // 28 + daddr_funcin == 7'b1001110 || // 78 + daddr_funcin == 7'b1001111 || // 79 + daddr_funcin == 7'b1011100) begin // 92 + addr_is_valid = 1; + end + else begin + addr_is_valid = 0; + end + end + end + endfunction + + +// Determine clock period + always @(posedge pll_locked_tmp1) + begin + pchk_tmp1 = CLKIN_PERIOD_REG * 1100; + pchk_tmp2 = CLKIN_PERIOD_REG * 900; + if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin + $display("Warning: [Unisim %s-10] input CLKIN period (%f) and attribute CLKIN_PERIOD (%f) are not same. Instance %m.", MODULE_NAME, period_avg, CLKIN_PERIOD_REG); + end + end + + always @(posedge clkin_in or posedge rst_in) + if (rst_in) + begin + clkin_period[0] <= period_vco_target; + clkin_period[1] <= period_vco_target; + clkin_period[2] <= period_vco_target; + clkin_period[3] <= period_vco_target; + clkin_period[4] <= period_vco_target; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end + else begin + clkin_edge <= $time; + if (clkin_edge != 0) begin + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4] or period_avg) + begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp = clkin_period[1] - clkin_period[0]; + + if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + clkin_period[3] + clkin_period[4])/5; + end + + always @(period_avg or lock_period or clkind_div) + if (period_avg > 500 && lock_period == 1) begin + clkin_lost_val = ((period_avg * 1.5) / 500) - 1; + clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1; + end + + assign init_trig = 1; + always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge) + clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); + always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge) + clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); + always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge) + clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); + always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge) + clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge); + + +// Unlock due to jitter + + always @(clkin_jit or rst_in ) + begin + if (rst_in) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2) begin + if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + end + +// Determine feedback delay - only internal feedback + + always @(posedge clkin_in ) + if (fb_delay_found) clkfb_tst <= 1'b0; + else clkfb_tst <= ~clkfb_tst; + + always @( posedge clkfb_tst ) + delay_edge = $time; + + assign clkfbin_sel = ((COMPENSATION_BIN == COMPENSATION_INTERNAL) || + ((COMPENSATION_BIN == COMPENSATION_AUTO) && (CLKFBIN === 1'bz))); + + assign CLKFBIN_int = clkfbin_sel && clkfb_out || ~clkfbin_sel && clkfb_in; + + always @( posedge rst_in ) + begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end + + always @(posedge CLKFBIN_int ) + if (clkfbin_sel == 1 ) begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b1; + end else if (fb_delay_found_tmp == 1'b0 ) begin + if ( delay_edge != 0) begin + fb_delay <= ($time - delay_edge); + fb_delay_found_tmp <= 1'b1; + end else begin + fb_delay <= 0; + fb_delay_found_tmp <= 1'b0; + end + end + + always @(negedge clkfb_tst or negedge fb_delay_found_tmp) + fb_delay_found <= fb_delay_found_tmp; + + always @(fb_delay) + if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning: [Unisim %s-11] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m.", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); + end + + + always @(fb_delay_found_tmp) + fb_delay_found <= #1000 fb_delay_found_tmp; + + always @(period_avg or clkind_div or clkfbm1_div) + begin + if (period_avg > 0 ) + begin + md_product = clkind_div * clkfbm1_div; + m_product = clkfbm1_div; + m_product2 = clkfbm1_div / 2; + period_fb = period_avg * clkind_div; + period_vco = period_fb / clkfbm1_div; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco_mf = period_avg * 8; + period_vco_rm = period_fb % clkfbm1_div; + if (period_vco_rm > 1) + begin + if (period_vco_rm > m_product2) + begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else + begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbm1_div; + clkin_dly_t = period_avg * (clkind_div + 1.25); + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + end + + always @( clkin_in ) // Why these delays? + clkpll_tmp1 <= #(period_avg) clkin_in; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(clkvco or clkvco_lk_tmp or rst_in) + begin + if (rst_in) + clkvco = 0; + else + clkvco = clkvco_lk_tmp; + end + +// Xiphy clocks + + always @(posedge clkvco or negedge clkvco or posedge rst_in or negedge xiphyen_sync) + begin + if (!xiphyen_sync || rst_in) + clkvco_2x <= 0; + else + begin + clkvco_2x <= 1; + #(period_vco/ 4) + clkvco_2x <= 0; + end + end + + always @(posedge clkvco or posedge rst_in) + begin + if (!xiphyen_sync || rst_in) + clkvco_by2 <= 0; + else + clkvco_by2 <= ~clkvco_by2; + end + + always @(posedge clkvco or posedge rst_in) + begin + if (rst_in) begin + clkvco_by8 <= 1'b0; + clkvco_cnt <= 2'b0; + end + else begin + if (clkvco_cnt == 2'b0) clkvco_by8 <= ~clkvco_by8; + clkvco_cnt <= clkvco_cnt + 2'b01; + end + end + + always @(negedge clkvco_by8 or posedge rst_in) begin + if (rst_in) begin + xiphyen_sync2 <= 1'b0; + xiphyen_sync1 <= 1'b0; + end + else begin + xiphyen_sync2 <= xiphyen_in; + xiphyen_sync1 <= xiphyen_sync2; + end + end + + always @(negedge clkvco or posedge rst_in) begin + if (rst_in) begin + xiphyen_sync <= 1'b0; + end + else if (clkvco_cnt[1:0] == 2'b0) begin + xiphyen_sync <= xiphyen_sync1; + end + end + +// VCO clock generation + + always @(posedge clkpll) + begin + if (pll_locked_tm ==1) + begin + clkvco_lk_tmp <= 1; + clkvco_rm_cnt = 0; + clkout_en_t <= 0; + vcoflag = 0; + if ( period_vco_cmp_flag == 1) + begin + for (ik2=1; ik2 < m_product; ik2=ik2+1) + begin + vcoflag = 1; + clkout_en_t <= ik2; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik2; + end + else if ( period_vco_cmp_flag == 2 ) + begin + vcoflag = 1; + for (ik3=1; ik3 < m_product; ik3=ik3+1) + begin + clkout_en_t <= ik3; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik3; + end + else + begin + vcoflag = 1; + for (ik4=1; ik4 < m_product; ik4=ik4+1) + begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + end + #(period_vco_half) clkvco_lk_tmp <= 0; + if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) + begin + for (ik4=1; ik4 < m_product; ik4=ik4+1) + begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or lock_period) + begin + if (lock_period == 1) + begin + val_tmp = period_avg * DIVCLK_DIVIDE; + fbm1_comp_delay = period_vco * clkfbm1_dly; + end + dly_tmp1 = fb_delay + fbm1_comp_delay; + dly_tmp_int = 1; + dly_tmp = dly_tmp1; + if (dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + + always @(clkvco) + begin + if (clkout_en) + begin + clkout_mux[0] = clkvco; + clkout_mux[1] <= clkvco; + clkout_mux[2] <= clkvco; + end + end + + assign clk0in = clkout_mux[0]; + assign clk1in = clkout_mux[1]; + assign clkfbm1in = clkout_mux[2]; + + assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; + assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; + assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; + + always @(negedge clk0in or posedge rst_in) + begin + if (rst_in) + clk0_dly_cnt <= 6'b0; + else + if (clk0_dly_cnt < clkout0_dly && clkout_en == 1) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in) + begin + if (rst_in) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + end + + always @(negedge clkfbm1in or posedge rst_in) + begin + if (rst_in) + clkfbm1_dly_cnt <= 6'b0; + else + if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en == 1) + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + end + + always @(clk0_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkout0_out = clk0_out; + else + if(rst_in == 1'b0) + clkout0_out = clkfb_tst; + end + + always @(clk1_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkout1_out = clk1_out; + else + if(rst_in == 1'b0) + clkout1_out = clkfb_tst; + end + + always @(clkfbm1_out or clkfb_tst or fb_delay_found or rst_in) + begin + if (fb_delay_found == 1) + clkfb_out = clkfbm1_out; + else + if(rst_in == 1'b0) + clkfb_out = clkfb_tst; + end + +// Generate unlock signal + always begin + if (rst_in) + clk_osc = 0; + else + clk_osc = ~clk_osc; + #OSC_P2; + end + + always @(posedge clkpll or negedge clkpll) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int) begin + clkfb_p <= 1; + clkfb_p <= #100 0; + end + + + always @(posedge clk_osc or posedge rst_in or posedge clkin_p) + begin + if (rst_in == 1) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + else if (clkin_p == 1) begin + if (clkinstopped_out == 1) begin + @(posedge clkpll) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out <= 0; + end + else + clkinstopped_out <= 1; + end + end + + always @(posedge clkinstopped_out or posedge rst_in) + begin + if (rst_in); + else begin + $display("Warning: [Unisim %s-12] Input CLKIN is stopped at time %t. Reset is required when input clock returns. Instance %m.", MODULE_NAME, $time); + end + end + + always @(posedge clk_osc or posedge rst_in or posedge clkfb_p) + begin + if (rst_in == 1 || clkfb_p == 1) begin + clkfbstopped_out <= 0; + clkfb_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfb_lost_cnt < clkfb_lost_val) begin + clkfb_lost_cnt <= clkfb_lost_cnt + 1; + clkfbstopped_out <= 0; + end + else + clkfbstopped_out <= 1; + end + end + + always @(clkin_jit or rst_in ) + begin + if (rst_in) + clkpll_jitter_unlock = 0; + else + begin + if (pll_locked_tmp2) + begin + if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + end + end + + assign pll_unlock1 = (clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = ( clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // Generate lock signal + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + begin + if (clkout_en0_tmp==0 ) + clkout_en0 <= 0; + else + begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #(period_vco-1) clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in ) + if (rst_in) + clkout_en <= 0; + else + clkout_en <= clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 <= pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_in) + if (rst_in) begin + assign pll_locked_tmp2 = 0; + assign clkout_en0 = 0; + end + else begin + deassign pll_locked_tmp2; + deassign clkout_en0; + end + + assign locked_out = (pll_locked_tm && pll_locked_tmp2_dly && ~pll_unlock && !unlock_recover) ? 1 : 0; + + always @(rst_in or locked_out) + if (rst_in == 1) + locked_out_tmp <= #1000 0; + else + locked_out_tmp <= locked_out; + +// end of lock + + always @(posedge clk0in or negedge clk0in or posedge rst_in) + begin + if (rst_in) + begin + clk0_cnt <= 9'b0; + clk0_out <= 0; + end + else if (clk0ps_en) + begin + begin + if (clk0_cnt < clk0_div1) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 9'b0; + if (clk0_cnt < clk0_ht1) + clk0_out <= 1; + else + clk0_out <= 0; + end + end + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in) + begin + if (rst_in) + begin + clk1_cnt <= 9'b0; + clk1_out <= 0; + end + else if (clk1ps_en) + begin + if (clk1_cnt < clk1_div1) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 9'b0; + if (clk1_cnt < clk1_ht1) + clk1_out <= 1; + else + clk1_out <= 0; + end + end + + always @(posedge clkpll or negedge clkpll or posedge rst_in) + begin + if (rst_in) begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + else if (clkout_en) + begin + if (clkind_cnt < clkind_div1) + clkind_cnt <= clkind_cnt + 1; + else + clkind_cnt <= 8'b0; + if (clkind_cnt < clkind_ht1) + clkind_out <= 1; + else + clkind_out <= 0; + end + else begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + end + + always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in) + begin + if (rst_in) begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + else if (clkfbm1ps_en) + begin + if (clkfbm1_cnt < clkfbm1_div1) + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 8'b0; + if (clkfbm1_cnt < clkfbm1_ht1) + clkfbm1_nf_out <= 1; + else + clkfbm1_nf_out <= 0; + end + else + begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + end + + assign clkfbm1_out = clkfbm1_nf_out; + + always @(posedge CLKFBIN_int or negedge CLKFBIN_int or posedge rst_in) + begin + if (rst_in) begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + else if (clkout_en) begin + if (clkfbm2_cnt < clkfbm2_div1) + clkfbm2_cnt <= clkfbm2_cnt + 1; + else + clkfbm2_cnt <= 8'b0; + if (clkfbm2_cnt < clkfbm2_ht1) + clkfbm2_out <= 1; + else + clkfbm2_out <= 0; + end + else begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + end + +// Phase task + task clkout_dly_cal; + output [5:0] clkout_dly; + input clkdiv; + input clk_ps; + input reg [160:0] clk_ps_name; + integer clkdiv; + real clk_ps; + real clk_ps_rl; + real clk_dly_rl, clk_dly_rem; + integer clkout_dly_tmp; + begin + if (clk_ps < 0.0) + clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; + else + clk_dly_rl = clk_ps * clkdiv / 360.0; + +// clkout_dly_tmp = $rtoi(clk_dly_rl); + clkout_dly_tmp = clk_dly_rl; + + if (clkout_dly_tmp > 63) begin + $display("Warning: [Unisim %s-13] Attribute %s is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting capability. Instance %m ", MODULE_NAME, clk_ps_name, clk_ps); + clkout_dly = 6'b111111; + end + else + clkout_dly = clkout_dly_tmp; + end + + endtask + +// Task to calculate final ht based on clk_edge + task clkout_pm_cal; + output [8:0] clk_ht1; + output [8:0] clk_div; + output [8:0] clk_div1; + input [7:0] clk_ht; + input [7:0] clk_lt; + input clk_nocnt; + input clk_edge; + begin + if (clk_nocnt ==1) begin + clk_div = 9'b000000001; + clk_div1 = 9'b000000001; + clk_ht1 = 9'b000000001; + end + else begin + if ( clk_edge == 1) + clk_ht1 = 2 * clk_ht + 1; + else + clk_ht1 = 2 * clk_ht; + clk_div = clk_ht + clk_lt ; + clk_div1 = 2 * clk_div -1; + end + end + endtask + + // Task to calculate ht, lt based on duty cycle + // also detects of clk_edge needs to be 1 + task clk_out_para_cal; + output [7:0] clk_ht; + output [7:0] clk_lt; + output clk_nocnt; + output clk_edge; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + integer CLKOUT_DIVIDE; + real CLKOUT_DUTY_CYCLE; + real tmp_value, tmp_value0, tmp_value_rm; + integer tmp_value_round, tmp_value1, tmp_value_r; + real tmp_value2; + real tmp_value_rm1, tmp_value_r1; + integer tmp_value_r2; + begin + + tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; + tmp_value_r = $rtoi(tmp_value0); + tmp_value_rm = tmp_value0 - tmp_value_r; + if (tmp_value_rm < 0.1) + tmp_value = tmp_value_r * 1.0; + else if (tmp_value_rm > 0.9) + tmp_value = 1.0 * tmp_value_r + 1.0; + else begin + tmp_value_r1 = tmp_value0 * 2.0; + tmp_value_r2 = $rtoi(tmp_value_r1); + tmp_value_rm1 = tmp_value_r1 - tmp_value_r2; + if (tmp_value_rm1 > 0.995) + tmp_value = tmp_value0 + 0.002; + else + tmp_value = tmp_value0; + end + tmp_value_round = tmp_value * 2.0; + tmp_value1 = tmp_value_round % 2; + tmp_value2 = CLKOUT_DIVIDE - tmp_value; + + + if ((tmp_value2) >= O_MAX_HT_LT) begin + clk_lt = 8'b10000000; + end + else begin + if (tmp_value2 < 1.0) + clk_lt = 1; + else + if ( tmp_value1 != 0) + clk_lt = $rtoi(tmp_value2) + 1; + else + clk_lt = $rtoi(tmp_value2); + end + + if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT) + clk_ht = 8'b10000000; + else + clk_ht = CLKOUT_DIVIDE - clk_lt; + + clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; + if ( tmp_value < 1.0) + clk_edge = 1; + else if (tmp_value1 != 0) + clk_edge = 1; + else + clk_edge = 0; + end + endtask + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.5; + CLK_DUTY_CYCLE_MIN_rnd = 0.5; + CLK_DUTY_CYCLE_MAX = 0.5; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (CLKOUT_DIVIDE - 0.5)/ CLKOUT_DIVIDE; + end + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + $display(" Instance %m "); + end + + clkout_duty_chk = 1'b1; + end + endfunction + +task check_m_settings; + input real clkfbout_f_div; + input [3:0] pll_cp; + input [3:0] pll_res; + input [4:0] drp_lock_ref_dly; + input [4:0] drp_lock_fb_dly; + input [9:0] drp_lock_cnt; + input [9:0] drp_unlock_cnt; + input [9:0] drp_lock_sat_high; + + integer clkfbout_div; + reg [3:0] pll_cp_low, pll_cp_high, pll_cp_optimized; + reg [3:0] pll_res_low, pll_res_high, pll_res_optimized; + reg [1:0] lfhf_unused; + reg [4:0] drp_lock_ref_dly_calc; + reg [4:0] drp_lock_fb_dly_calc; + reg [9:0] drp_lock_cnt_calc; + reg [9:0] drp_unlock_cnt_calc; + reg [9:0] drp_lock_sat_high_calc; + reg [47:0] actual; + reg [47:0] calc_low, calc_high, calc_optimized; + +begin + + actual = {pll_cp,pll_res,drp_lock_ref_dly,drp_lock_fb_dly,drp_lock_cnt,drp_lock_sat_high,drp_unlock_cnt}; + clkfbout_div = $rtoi(clkfbout_f_div); + GetMultVal(clkfbout_div,nBandwidth_LOW,pll_cp_low,pll_res_low,lfhf_unused); + GetMultVal(clkfbout_div,nBandwidth_HIGH,pll_cp_high,pll_res_high,lfhf_unused); + GetMultVal(clkfbout_div,nBandwidth_OPTIMIZED,pll_cp_optimized,pll_res_optimized,lfhf_unused); + GetLockDetSettings(clkfbout_div,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc); + calc_low = {pll_cp_low,pll_res_low,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + calc_high = {pll_cp_high,pll_res_high,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + calc_optimized = {pll_cp_optimized,pll_res_optimized,drp_lock_ref_dly_calc,drp_lock_fb_dly_calc,drp_lock_cnt_calc,drp_lock_sat_high_calc,drp_unlock_cnt_calc}; + + if (actual != calc_low && actual != calc_high && actual != calc_optimized) + $display("Error: [Unisim %s-35] Illegal cp, res, and/or lock DRP programming at time %t. Programmed vales do not match Bandwidth setting. Instance %m ", MODULE_NAME, $time); + +end +endtask + +task GetLockDetSettings (input integer fClkFbOutMultF, output [4:0] lock_ref_dly, output [4:0] lock_fb_dly, output [9:0] lock_cnt, output [9:0] lock_sat_high, output [9:0] unlock_cnt); + begin + lock_sat_high = 10'd1001; + unlock_cnt = 10'd1; + case (fClkFbOutMultF) + 2: begin + lock_ref_dly = 5'd6; + lock_fb_dly = 5'd6; + lock_cnt = 10'd1000; + end + 3: begin + lock_ref_dly = 5'd8; + lock_fb_dly = 5'd8; + lock_cnt = 10'd1000; + end + 4: begin + lock_ref_dly = 5'd11; + lock_fb_dly = 5'd11; + lock_cnt = 10'd1000; + end + 5: begin + lock_ref_dly = 5'd14; + lock_fb_dly = 5'd14; + lock_cnt = 10'd1000; + end + 6: begin + lock_ref_dly = 5'd17; + lock_fb_dly = 5'd17; + lock_cnt = 10'd1000; + end + 7: begin + lock_ref_dly = 5'd19; + lock_fb_dly = 5'd19; + lock_cnt = 10'd1000; + end + 8: begin + lock_ref_dly = 5'd22; + lock_fb_dly = 5'd22; + lock_cnt = 10'd1000; + end + 9: begin + lock_ref_dly = 5'd25; + lock_fb_dly = 5'd25; + lock_cnt = 10'd1000; + end + 10: begin + lock_ref_dly = 5'd28; + lock_fb_dly = 5'd28; + lock_cnt = 10'd1000; + end + 11: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd900; + end + 12: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd825; + end + 13: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd750; + end + 14: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd700; + end + 15: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd650; + end + 16: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd625; + end + 17: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd575; + end + 18: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd550; + end + 19: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd525; + end + 20: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd500; + end + 21: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd475; + end + default: begin + lock_ref_dly = 5'd31; + lock_fb_dly = 5'd31; + lock_cnt = 10'd250; + end + endcase + end +endtask + +task GetMultVal (input integer fClkFbOutMultF, input integer nBandwidth, output [3:0] cp, output [3:0] res, output [1:0] lfhf); + begin + if ((nBandwidth == nBandwidth_HIGH) || (nBandwidth == nBandwidth_OPTIMIZED) || (nBandwidth == nBandwidth_LOW)) + lfhf = 2'd3; + case (fClkFbOutMultF) + 2: begin + cp = 4'd3; res = 4'd7; + end + 3: begin + cp = 4'd3; res = 4'd3; + end + 4: begin + cp = 4'd3; res = 4'd9; + end + 5: begin + cp = 4'd3; res = 4'd1; + end + 6: begin + cp = 4'd4; res = 4'd14; + end + 7: begin + cp = 4'd3; res = 4'd6; + end + 8: begin + cp = 4'd3; res = 4'd10; + end + 9,10: begin + cp = 4'd7; res = 4'd9; + end + 11: begin + cp = 4'd5; res = 4'd6; + end + 12: begin + cp = 4'd12; res = 4'd5; + end + 13: begin + cp = 4'd5; res = 4'd10; + end + 14: begin + cp = 4'd6; res = 4'd6; + end + 15: begin + cp = 4'd6; res = 4'd10; + end + 16: begin + cp = 4'd7; res = 4'd6; + end + 17: begin + cp = 4'd15; res = 4'd5; + end + 18: begin + cp = 4'd12; res = 4'd6; + end + 19: begin + cp = 4'd14; res = 4'd1; + end + 20: begin + cp = 4'd13; res = 4'd6; + end + 21: begin + cp = 4'd15; res = 4'd1; + end + endcase + end +endtask + + task clkout_delay_para_drp; + output [5:0] clkout_dly; + output clk_nocnt; + output clk_edge; + input [15:0] di_in; + input [6:0] daddr_in; + begin + clkout_dly = di_in[5:0]; + clk_nocnt = di_in[6]; + clk_edge = di_in[7]; + end + endtask + + task clkout_hl_para_drp; + output [6:0] clk_lt; + output [6:0] clk_ht; + input [15:0] di_in_tmp; + input [6:0] daddr_in_tmp; + begin +// if (di_in_tmp[12] != 1) begin +// $display("Error: [Unisim %s-34] Input DI is %h at address DADDR=%b at time %t. The bit 12 needs to be set to 1. Instance %m ", MODULE_NAME, di_in_tmp, daddr_in_tmp, $time); +// end + if ( di_in_tmp[5:0] == 6'b0) + clk_lt = 7'b1000000; + else + clk_lt = { 1'b0, di_in_tmp[5:0]}; + if (di_in_tmp[11:6] == 6'b0) + clk_ht = 7'b1000000; + else + clk_ht = { 1'b0, di_in_tmp[11:6]}; + end + endtask + + +// end behavioral model + + specify + (DCLK *> DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (negedge PWRDWN => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge PWRDWN => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKIN, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUTPHY, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKIN, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUTPHY, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PLLE4_BASE.v b/verilog/src/unisims/PLLE4_BASE.v new file mode 100644 index 0000000..8ecf3e0 --- /dev/null +++ b/verilog/src/unisims/PLLE4_BASE.v @@ -0,0 +1,167 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Base Phase-Locked Loop (PLL) +// /___/ /\ Filename : PLLE4_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/22/2014 808642 - Added #1 to $finish +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PLLE4_BASE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer CLKFBOUT_MULT = 5, + parameter real CLKFBOUT_PHASE = 0.000, + parameter real CLKIN_PERIOD = 0.000, + parameter integer CLKOUT0_DIVIDE = 1, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUTPHY_MODE = "VCO_2X", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0, + parameter [0:0] IS_CLKIN_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER = 0.010, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUTPHY, + output LOCKED, + + input CLKFBIN, + input CLKIN, + input CLKOUTPHYEN, + input PWRDWN, + input RST +); + +// define constants + localparam MODULE_NAME = "PLLE4_BASE"; + + initial begin + #1; + if ($realtime == 0) begin + $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); + $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); + #1 $finish; + end + end + + wire OPEN_DRDY; + wire OPEN_PSDONE; + wire OPEN_FBS; + wire OPEN_INS; + wire [15:0] OPEN_DO; + + PLLE4_ADV #( + .CLKFBOUT_MULT(CLKFBOUT_MULT), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN_PERIOD(CLKIN_PERIOD), + .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUTPHY_MODE(CLKOUTPHY_MODE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .IS_CLKFBIN_INVERTED(IS_CLKFBIN_INVERTED), + .IS_CLKIN_INVERTED(IS_CLKIN_INVERTED), + .IS_PWRDWN_INVERTED(IS_PWRDWN_INVERTED), + .IS_RST_INVERTED(IS_RST_INVERTED), + .REF_JITTER(REF_JITTER), + .STARTUP_WAIT(STARTUP_WAIT) + ) pll_adv_1 ( + .CLKFBOUT (CLKFBOUT), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUTPHY (CLKOUTPHY), + .CLKOUTPHYEN (CLKOUTPHYEN), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .LOCKED (LOCKED), + .CLKFBIN (CLKFBIN), + .CLKIN (CLKIN), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PWRDWN(PWRDWN), + .RST (RST) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); + (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKFBIN, 0:0:0, notifier); + $period (negedge CLKFBOUT, 0:0:0, notifier); + $period (negedge CLKIN, 0:0:0, notifier); + $period (negedge CLKOUT0, 0:0:0, notifier); + $period (negedge CLKOUT0B, 0:0:0, notifier); + $period (negedge CLKOUT1, 0:0:0, notifier); + $period (negedge CLKOUT1B, 0:0:0, notifier); + $period (negedge CLKOUTPHY, 0:0:0, notifier); + $period (posedge CLKFBIN, 0:0:0, notifier); + $period (posedge CLKFBOUT, 0:0:0, notifier); + $period (posedge CLKIN, 0:0:0, notifier); + $period (posedge CLKOUT0, 0:0:0, notifier); + $period (posedge CLKOUT0B, 0:0:0, notifier); + $period (posedge CLKOUT1, 0:0:0, notifier); + $period (posedge CLKOUT1B, 0:0:0, notifier); + $period (posedge CLKOUTPHY, 0:0:0, notifier); + $width (negedge CLKIN, 0:0:0, 0, notifier); + $width (negedge PWRDWN, 0:0:0, 0, notifier); + $width (negedge RST, 0:0:0, 0, notifier); + $width (posedge CLKIN, 0:0:0, 0, notifier); + $width (posedge PWRDWN, 0:0:0, 0, notifier); + $width (posedge RST, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PS7.v b/verilog/src/unisims/PS7.v new file mode 100644 index 0000000..84efd82 --- /dev/null +++ b/verilog/src/unisims/PS7.v @@ -0,0 +1,9386 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / PS7 +// /___/ /\ Filename : PS7.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PS7 +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output [1:0] DMA0DATYPE, + output DMA0DAVALID, + output DMA0DRREADY, + output DMA0RSTN, + output [1:0] DMA1DATYPE, + output DMA1DAVALID, + output DMA1DRREADY, + output DMA1RSTN, + output [1:0] DMA2DATYPE, + output DMA2DAVALID, + output DMA2DRREADY, + output DMA2RSTN, + output [1:0] DMA3DATYPE, + output DMA3DAVALID, + output DMA3DRREADY, + output DMA3RSTN, + output EMIOCAN0PHYTX, + output EMIOCAN1PHYTX, + output [7:0] EMIOENET0GMIITXD, + output EMIOENET0GMIITXEN, + output EMIOENET0GMIITXER, + output EMIOENET0MDIOMDC, + output EMIOENET0MDIOO, + output EMIOENET0MDIOTN, + output EMIOENET0PTPDELAYREQRX, + output EMIOENET0PTPDELAYREQTX, + output EMIOENET0PTPPDELAYREQRX, + output EMIOENET0PTPPDELAYREQTX, + output EMIOENET0PTPPDELAYRESPRX, + output EMIOENET0PTPPDELAYRESPTX, + output EMIOENET0PTPSYNCFRAMERX, + output EMIOENET0PTPSYNCFRAMETX, + output EMIOENET0SOFRX, + output EMIOENET0SOFTX, + output [7:0] EMIOENET1GMIITXD, + output EMIOENET1GMIITXEN, + output EMIOENET1GMIITXER, + output EMIOENET1MDIOMDC, + output EMIOENET1MDIOO, + output EMIOENET1MDIOTN, + output EMIOENET1PTPDELAYREQRX, + output EMIOENET1PTPDELAYREQTX, + output EMIOENET1PTPPDELAYREQRX, + output EMIOENET1PTPPDELAYREQTX, + output EMIOENET1PTPPDELAYRESPRX, + output EMIOENET1PTPPDELAYRESPTX, + output EMIOENET1PTPSYNCFRAMERX, + output EMIOENET1PTPSYNCFRAMETX, + output EMIOENET1SOFRX, + output EMIOENET1SOFTX, + output [63:0] EMIOGPIOO, + output [63:0] EMIOGPIOTN, + output EMIOI2C0SCLO, + output EMIOI2C0SCLTN, + output EMIOI2C0SDAO, + output EMIOI2C0SDATN, + output EMIOI2C1SCLO, + output EMIOI2C1SCLTN, + output EMIOI2C1SDAO, + output EMIOI2C1SDATN, + output EMIOPJTAGTDO, + output EMIOPJTAGTDTN, + output EMIOSDIO0BUSPOW, + output [2:0] EMIOSDIO0BUSVOLT, + output EMIOSDIO0CLK, + output EMIOSDIO0CMDO, + output EMIOSDIO0CMDTN, + output [3:0] EMIOSDIO0DATAO, + output [3:0] EMIOSDIO0DATATN, + output EMIOSDIO0LED, + output EMIOSDIO1BUSPOW, + output [2:0] EMIOSDIO1BUSVOLT, + output EMIOSDIO1CLK, + output EMIOSDIO1CMDO, + output EMIOSDIO1CMDTN, + output [3:0] EMIOSDIO1DATAO, + output [3:0] EMIOSDIO1DATATN, + output EMIOSDIO1LED, + output EMIOSPI0MO, + output EMIOSPI0MOTN, + output EMIOSPI0SCLKO, + output EMIOSPI0SCLKTN, + output EMIOSPI0SO, + output EMIOSPI0SSNTN, + output [2:0] EMIOSPI0SSON, + output EMIOSPI0STN, + output EMIOSPI1MO, + output EMIOSPI1MOTN, + output EMIOSPI1SCLKO, + output EMIOSPI1SCLKTN, + output EMIOSPI1SO, + output EMIOSPI1SSNTN, + output [2:0] EMIOSPI1SSON, + output EMIOSPI1STN, + output EMIOTRACECTL, + output [31:0] EMIOTRACEDATA, + output [2:0] EMIOTTC0WAVEO, + output [2:0] EMIOTTC1WAVEO, + output EMIOUART0DTRN, + output EMIOUART0RTSN, + output EMIOUART0TX, + output EMIOUART1DTRN, + output EMIOUART1RTSN, + output EMIOUART1TX, + output [1:0] EMIOUSB0PORTINDCTL, + output EMIOUSB0VBUSPWRSELECT, + output [1:0] EMIOUSB1PORTINDCTL, + output EMIOUSB1VBUSPWRSELECT, + output EMIOWDTRSTO, + output EVENTEVENTO, + output [1:0] EVENTSTANDBYWFE, + output [1:0] EVENTSTANDBYWFI, + output [3:0] FCLKCLK, + output [3:0] FCLKRESETN, + output [3:0] FTMTF2PTRIGACK, + output [31:0] FTMTP2FDEBUG, + output [3:0] FTMTP2FTRIG, + output [28:0] IRQP2F, + output [31:0] MAXIGP0ARADDR, + output [1:0] MAXIGP0ARBURST, + output [3:0] MAXIGP0ARCACHE, + output MAXIGP0ARESETN, + output [11:0] MAXIGP0ARID, + output [3:0] MAXIGP0ARLEN, + output [1:0] MAXIGP0ARLOCK, + output [2:0] MAXIGP0ARPROT, + output [3:0] MAXIGP0ARQOS, + output [1:0] MAXIGP0ARSIZE, + output MAXIGP0ARVALID, + output [31:0] MAXIGP0AWADDR, + output [1:0] MAXIGP0AWBURST, + output [3:0] MAXIGP0AWCACHE, + output [11:0] MAXIGP0AWID, + output [3:0] MAXIGP0AWLEN, + output [1:0] MAXIGP0AWLOCK, + output [2:0] MAXIGP0AWPROT, + output [3:0] MAXIGP0AWQOS, + output [1:0] MAXIGP0AWSIZE, + output MAXIGP0AWVALID, + output MAXIGP0BREADY, + output MAXIGP0RREADY, + output [31:0] MAXIGP0WDATA, + output [11:0] MAXIGP0WID, + output MAXIGP0WLAST, + output [3:0] MAXIGP0WSTRB, + output MAXIGP0WVALID, + output [31:0] MAXIGP1ARADDR, + output [1:0] MAXIGP1ARBURST, + output [3:0] MAXIGP1ARCACHE, + output MAXIGP1ARESETN, + output [11:0] MAXIGP1ARID, + output [3:0] MAXIGP1ARLEN, + output [1:0] MAXIGP1ARLOCK, + output [2:0] MAXIGP1ARPROT, + output [3:0] MAXIGP1ARQOS, + output [1:0] MAXIGP1ARSIZE, + output MAXIGP1ARVALID, + output [31:0] MAXIGP1AWADDR, + output [1:0] MAXIGP1AWBURST, + output [3:0] MAXIGP1AWCACHE, + output [11:0] MAXIGP1AWID, + output [3:0] MAXIGP1AWLEN, + output [1:0] MAXIGP1AWLOCK, + output [2:0] MAXIGP1AWPROT, + output [3:0] MAXIGP1AWQOS, + output [1:0] MAXIGP1AWSIZE, + output MAXIGP1AWVALID, + output MAXIGP1BREADY, + output MAXIGP1RREADY, + output [31:0] MAXIGP1WDATA, + output [11:0] MAXIGP1WID, + output MAXIGP1WLAST, + output [3:0] MAXIGP1WSTRB, + output MAXIGP1WVALID, + output SAXIACPARESETN, + output SAXIACPARREADY, + output SAXIACPAWREADY, + output [2:0] SAXIACPBID, + output [1:0] SAXIACPBRESP, + output SAXIACPBVALID, + output [63:0] SAXIACPRDATA, + output [2:0] SAXIACPRID, + output SAXIACPRLAST, + output [1:0] SAXIACPRRESP, + output SAXIACPRVALID, + output SAXIACPWREADY, + output SAXIGP0ARESETN, + output SAXIGP0ARREADY, + output SAXIGP0AWREADY, + output [5:0] SAXIGP0BID, + output [1:0] SAXIGP0BRESP, + output SAXIGP0BVALID, + output [31:0] SAXIGP0RDATA, + output [5:0] SAXIGP0RID, + output SAXIGP0RLAST, + output [1:0] SAXIGP0RRESP, + output SAXIGP0RVALID, + output SAXIGP0WREADY, + output SAXIGP1ARESETN, + output SAXIGP1ARREADY, + output SAXIGP1AWREADY, + output [5:0] SAXIGP1BID, + output [1:0] SAXIGP1BRESP, + output SAXIGP1BVALID, + output [31:0] SAXIGP1RDATA, + output [5:0] SAXIGP1RID, + output SAXIGP1RLAST, + output [1:0] SAXIGP1RRESP, + output SAXIGP1RVALID, + output SAXIGP1WREADY, + output SAXIHP0ARESETN, + output SAXIHP0ARREADY, + output SAXIHP0AWREADY, + output [5:0] SAXIHP0BID, + output [1:0] SAXIHP0BRESP, + output SAXIHP0BVALID, + output [2:0] SAXIHP0RACOUNT, + output [7:0] SAXIHP0RCOUNT, + output [63:0] SAXIHP0RDATA, + output [5:0] SAXIHP0RID, + output SAXIHP0RLAST, + output [1:0] SAXIHP0RRESP, + output SAXIHP0RVALID, + output [5:0] SAXIHP0WACOUNT, + output [7:0] SAXIHP0WCOUNT, + output SAXIHP0WREADY, + output SAXIHP1ARESETN, + output SAXIHP1ARREADY, + output SAXIHP1AWREADY, + output [5:0] SAXIHP1BID, + output [1:0] SAXIHP1BRESP, + output SAXIHP1BVALID, + output [2:0] SAXIHP1RACOUNT, + output [7:0] SAXIHP1RCOUNT, + output [63:0] SAXIHP1RDATA, + output [5:0] SAXIHP1RID, + output SAXIHP1RLAST, + output [1:0] SAXIHP1RRESP, + output SAXIHP1RVALID, + output [5:0] SAXIHP1WACOUNT, + output [7:0] SAXIHP1WCOUNT, + output SAXIHP1WREADY, + output SAXIHP2ARESETN, + output SAXIHP2ARREADY, + output SAXIHP2AWREADY, + output [5:0] SAXIHP2BID, + output [1:0] SAXIHP2BRESP, + output SAXIHP2BVALID, + output [2:0] SAXIHP2RACOUNT, + output [7:0] SAXIHP2RCOUNT, + output [63:0] SAXIHP2RDATA, + output [5:0] SAXIHP2RID, + output SAXIHP2RLAST, + output [1:0] SAXIHP2RRESP, + output SAXIHP2RVALID, + output [5:0] SAXIHP2WACOUNT, + output [7:0] SAXIHP2WCOUNT, + output SAXIHP2WREADY, + output SAXIHP3ARESETN, + output SAXIHP3ARREADY, + output SAXIHP3AWREADY, + output [5:0] SAXIHP3BID, + output [1:0] SAXIHP3BRESP, + output SAXIHP3BVALID, + output [2:0] SAXIHP3RACOUNT, + output [7:0] SAXIHP3RCOUNT, + output [63:0] SAXIHP3RDATA, + output [5:0] SAXIHP3RID, + output SAXIHP3RLAST, + output [1:0] SAXIHP3RRESP, + output SAXIHP3RVALID, + output [5:0] SAXIHP3WACOUNT, + output [7:0] SAXIHP3WCOUNT, + output SAXIHP3WREADY, + + inout [14:0] DDRA, + inout [2:0] DDRBA, + inout DDRCASB, + inout DDRCKE, + inout DDRCKN, + inout DDRCKP, + inout DDRCSB, + inout [3:0] DDRDM, + inout [31:0] DDRDQ, + inout [3:0] DDRDQSN, + inout [3:0] DDRDQSP, + inout DDRDRSTB, + inout DDRODT, + inout DDRRASB, + inout DDRVRN, + inout DDRVRP, + inout DDRWEB, + inout [53:0] MIO, + inout PSCLK, + inout PSPORB, + inout PSSRSTB, + + input [3:0] DDRARB, + input DMA0ACLK, + input DMA0DAREADY, + input DMA0DRLAST, + input [1:0] DMA0DRTYPE, + input DMA0DRVALID, + input DMA1ACLK, + input DMA1DAREADY, + input DMA1DRLAST, + input [1:0] DMA1DRTYPE, + input DMA1DRVALID, + input DMA2ACLK, + input DMA2DAREADY, + input DMA2DRLAST, + input [1:0] DMA2DRTYPE, + input DMA2DRVALID, + input DMA3ACLK, + input DMA3DAREADY, + input DMA3DRLAST, + input [1:0] DMA3DRTYPE, + input DMA3DRVALID, + input EMIOCAN0PHYRX, + input EMIOCAN1PHYRX, + input EMIOENET0EXTINTIN, + input EMIOENET0GMIICOL, + input EMIOENET0GMIICRS, + input EMIOENET0GMIIRXCLK, + input [7:0] EMIOENET0GMIIRXD, + input EMIOENET0GMIIRXDV, + input EMIOENET0GMIIRXER, + input EMIOENET0GMIITXCLK, + input EMIOENET0MDIOI, + input EMIOENET1EXTINTIN, + input EMIOENET1GMIICOL, + input EMIOENET1GMIICRS, + input EMIOENET1GMIIRXCLK, + input [7:0] EMIOENET1GMIIRXD, + input EMIOENET1GMIIRXDV, + input EMIOENET1GMIIRXER, + input EMIOENET1GMIITXCLK, + input EMIOENET1MDIOI, + input [63:0] EMIOGPIOI, + input EMIOI2C0SCLI, + input EMIOI2C0SDAI, + input EMIOI2C1SCLI, + input EMIOI2C1SDAI, + input EMIOPJTAGTCK, + input EMIOPJTAGTDI, + input EMIOPJTAGTMS, + input EMIOSDIO0CDN, + input EMIOSDIO0CLKFB, + input EMIOSDIO0CMDI, + input [3:0] EMIOSDIO0DATAI, + input EMIOSDIO0WP, + input EMIOSDIO1CDN, + input EMIOSDIO1CLKFB, + input EMIOSDIO1CMDI, + input [3:0] EMIOSDIO1DATAI, + input EMIOSDIO1WP, + input EMIOSPI0MI, + input EMIOSPI0SCLKI, + input EMIOSPI0SI, + input EMIOSPI0SSIN, + input EMIOSPI1MI, + input EMIOSPI1SCLKI, + input EMIOSPI1SI, + input EMIOSPI1SSIN, + input EMIOSRAMINTIN, + input EMIOTRACECLK, + input [2:0] EMIOTTC0CLKI, + input [2:0] EMIOTTC1CLKI, + input EMIOUART0CTSN, + input EMIOUART0DCDN, + input EMIOUART0DSRN, + input EMIOUART0RIN, + input EMIOUART0RX, + input EMIOUART1CTSN, + input EMIOUART1DCDN, + input EMIOUART1DSRN, + input EMIOUART1RIN, + input EMIOUART1RX, + input EMIOUSB0VBUSPWRFAULT, + input EMIOUSB1VBUSPWRFAULT, + input EMIOWDTCLKI, + input EVENTEVENTI, + input [3:0] FCLKCLKTRIGN, + input FPGAIDLEN, + input [3:0] FTMDTRACEINATID, + input FTMDTRACEINCLOCK, + input [31:0] FTMDTRACEINDATA, + input FTMDTRACEINVALID, + input [31:0] FTMTF2PDEBUG, + input [3:0] FTMTF2PTRIG, + input [3:0] FTMTP2FTRIGACK, + input [19:0] IRQF2P, + input MAXIGP0ACLK, + input MAXIGP0ARREADY, + input MAXIGP0AWREADY, + input [11:0] MAXIGP0BID, + input [1:0] MAXIGP0BRESP, + input MAXIGP0BVALID, + input [31:0] MAXIGP0RDATA, + input [11:0] MAXIGP0RID, + input MAXIGP0RLAST, + input [1:0] MAXIGP0RRESP, + input MAXIGP0RVALID, + input MAXIGP0WREADY, + input MAXIGP1ACLK, + input MAXIGP1ARREADY, + input MAXIGP1AWREADY, + input [11:0] MAXIGP1BID, + input [1:0] MAXIGP1BRESP, + input MAXIGP1BVALID, + input [31:0] MAXIGP1RDATA, + input [11:0] MAXIGP1RID, + input MAXIGP1RLAST, + input [1:0] MAXIGP1RRESP, + input MAXIGP1RVALID, + input MAXIGP1WREADY, + input SAXIACPACLK, + input [31:0] SAXIACPARADDR, + input [1:0] SAXIACPARBURST, + input [3:0] SAXIACPARCACHE, + input [2:0] SAXIACPARID, + input [3:0] SAXIACPARLEN, + input [1:0] SAXIACPARLOCK, + input [2:0] SAXIACPARPROT, + input [3:0] SAXIACPARQOS, + input [1:0] SAXIACPARSIZE, + input [4:0] SAXIACPARUSER, + input SAXIACPARVALID, + input [31:0] SAXIACPAWADDR, + input [1:0] SAXIACPAWBURST, + input [3:0] SAXIACPAWCACHE, + input [2:0] SAXIACPAWID, + input [3:0] SAXIACPAWLEN, + input [1:0] SAXIACPAWLOCK, + input [2:0] SAXIACPAWPROT, + input [3:0] SAXIACPAWQOS, + input [1:0] SAXIACPAWSIZE, + input [4:0] SAXIACPAWUSER, + input SAXIACPAWVALID, + input SAXIACPBREADY, + input SAXIACPRREADY, + input [63:0] SAXIACPWDATA, + input [2:0] SAXIACPWID, + input SAXIACPWLAST, + input [7:0] SAXIACPWSTRB, + input SAXIACPWVALID, + input SAXIGP0ACLK, + input [31:0] SAXIGP0ARADDR, + input [1:0] SAXIGP0ARBURST, + input [3:0] SAXIGP0ARCACHE, + input [5:0] SAXIGP0ARID, + input [3:0] SAXIGP0ARLEN, + input [1:0] SAXIGP0ARLOCK, + input [2:0] SAXIGP0ARPROT, + input [3:0] SAXIGP0ARQOS, + input [1:0] SAXIGP0ARSIZE, + input SAXIGP0ARVALID, + input [31:0] SAXIGP0AWADDR, + input [1:0] SAXIGP0AWBURST, + input [3:0] SAXIGP0AWCACHE, + input [5:0] SAXIGP0AWID, + input [3:0] SAXIGP0AWLEN, + input [1:0] SAXIGP0AWLOCK, + input [2:0] SAXIGP0AWPROT, + input [3:0] SAXIGP0AWQOS, + input [1:0] SAXIGP0AWSIZE, + input SAXIGP0AWVALID, + input SAXIGP0BREADY, + input SAXIGP0RREADY, + input [31:0] SAXIGP0WDATA, + input [5:0] SAXIGP0WID, + input SAXIGP0WLAST, + input [3:0] SAXIGP0WSTRB, + input SAXIGP0WVALID, + input SAXIGP1ACLK, + input [31:0] SAXIGP1ARADDR, + input [1:0] SAXIGP1ARBURST, + input [3:0] SAXIGP1ARCACHE, + input [5:0] SAXIGP1ARID, + input [3:0] SAXIGP1ARLEN, + input [1:0] SAXIGP1ARLOCK, + input [2:0] SAXIGP1ARPROT, + input [3:0] SAXIGP1ARQOS, + input [1:0] SAXIGP1ARSIZE, + input SAXIGP1ARVALID, + input [31:0] SAXIGP1AWADDR, + input [1:0] SAXIGP1AWBURST, + input [3:0] SAXIGP1AWCACHE, + input [5:0] SAXIGP1AWID, + input [3:0] SAXIGP1AWLEN, + input [1:0] SAXIGP1AWLOCK, + input [2:0] SAXIGP1AWPROT, + input [3:0] SAXIGP1AWQOS, + input [1:0] SAXIGP1AWSIZE, + input SAXIGP1AWVALID, + input SAXIGP1BREADY, + input SAXIGP1RREADY, + input [31:0] SAXIGP1WDATA, + input [5:0] SAXIGP1WID, + input SAXIGP1WLAST, + input [3:0] SAXIGP1WSTRB, + input SAXIGP1WVALID, + input SAXIHP0ACLK, + input [31:0] SAXIHP0ARADDR, + input [1:0] SAXIHP0ARBURST, + input [3:0] SAXIHP0ARCACHE, + input [5:0] SAXIHP0ARID, + input [3:0] SAXIHP0ARLEN, + input [1:0] SAXIHP0ARLOCK, + input [2:0] SAXIHP0ARPROT, + input [3:0] SAXIHP0ARQOS, + input [1:0] SAXIHP0ARSIZE, + input SAXIHP0ARVALID, + input [31:0] SAXIHP0AWADDR, + input [1:0] SAXIHP0AWBURST, + input [3:0] SAXIHP0AWCACHE, + input [5:0] SAXIHP0AWID, + input [3:0] SAXIHP0AWLEN, + input [1:0] SAXIHP0AWLOCK, + input [2:0] SAXIHP0AWPROT, + input [3:0] SAXIHP0AWQOS, + input [1:0] SAXIHP0AWSIZE, + input SAXIHP0AWVALID, + input SAXIHP0BREADY, + input SAXIHP0RDISSUECAP1EN, + input SAXIHP0RREADY, + input [63:0] SAXIHP0WDATA, + input [5:0] SAXIHP0WID, + input SAXIHP0WLAST, + input SAXIHP0WRISSUECAP1EN, + input [7:0] SAXIHP0WSTRB, + input SAXIHP0WVALID, + input SAXIHP1ACLK, + input [31:0] SAXIHP1ARADDR, + input [1:0] SAXIHP1ARBURST, + input [3:0] SAXIHP1ARCACHE, + input [5:0] SAXIHP1ARID, + input [3:0] SAXIHP1ARLEN, + input [1:0] SAXIHP1ARLOCK, + input [2:0] SAXIHP1ARPROT, + input [3:0] SAXIHP1ARQOS, + input [1:0] SAXIHP1ARSIZE, + input SAXIHP1ARVALID, + input [31:0] SAXIHP1AWADDR, + input [1:0] SAXIHP1AWBURST, + input [3:0] SAXIHP1AWCACHE, + input [5:0] SAXIHP1AWID, + input [3:0] SAXIHP1AWLEN, + input [1:0] SAXIHP1AWLOCK, + input [2:0] SAXIHP1AWPROT, + input [3:0] SAXIHP1AWQOS, + input [1:0] SAXIHP1AWSIZE, + input SAXIHP1AWVALID, + input SAXIHP1BREADY, + input SAXIHP1RDISSUECAP1EN, + input SAXIHP1RREADY, + input [63:0] SAXIHP1WDATA, + input [5:0] SAXIHP1WID, + input SAXIHP1WLAST, + input SAXIHP1WRISSUECAP1EN, + input [7:0] SAXIHP1WSTRB, + input SAXIHP1WVALID, + input SAXIHP2ACLK, + input [31:0] SAXIHP2ARADDR, + input [1:0] SAXIHP2ARBURST, + input [3:0] SAXIHP2ARCACHE, + input [5:0] SAXIHP2ARID, + input [3:0] SAXIHP2ARLEN, + input [1:0] SAXIHP2ARLOCK, + input [2:0] SAXIHP2ARPROT, + input [3:0] SAXIHP2ARQOS, + input [1:0] SAXIHP2ARSIZE, + input SAXIHP2ARVALID, + input [31:0] SAXIHP2AWADDR, + input [1:0] SAXIHP2AWBURST, + input [3:0] SAXIHP2AWCACHE, + input [5:0] SAXIHP2AWID, + input [3:0] SAXIHP2AWLEN, + input [1:0] SAXIHP2AWLOCK, + input [2:0] SAXIHP2AWPROT, + input [3:0] SAXIHP2AWQOS, + input [1:0] SAXIHP2AWSIZE, + input SAXIHP2AWVALID, + input SAXIHP2BREADY, + input SAXIHP2RDISSUECAP1EN, + input SAXIHP2RREADY, + input [63:0] SAXIHP2WDATA, + input [5:0] SAXIHP2WID, + input SAXIHP2WLAST, + input SAXIHP2WRISSUECAP1EN, + input [7:0] SAXIHP2WSTRB, + input SAXIHP2WVALID, + input SAXIHP3ACLK, + input [31:0] SAXIHP3ARADDR, + input [1:0] SAXIHP3ARBURST, + input [3:0] SAXIHP3ARCACHE, + input [5:0] SAXIHP3ARID, + input [3:0] SAXIHP3ARLEN, + input [1:0] SAXIHP3ARLOCK, + input [2:0] SAXIHP3ARPROT, + input [3:0] SAXIHP3ARQOS, + input [1:0] SAXIHP3ARSIZE, + input SAXIHP3ARVALID, + input [31:0] SAXIHP3AWADDR, + input [1:0] SAXIHP3AWBURST, + input [3:0] SAXIHP3AWCACHE, + input [5:0] SAXIHP3AWID, + input [3:0] SAXIHP3AWLEN, + input [1:0] SAXIHP3AWLOCK, + input [2:0] SAXIHP3AWPROT, + input [3:0] SAXIHP3AWQOS, + input [1:0] SAXIHP3AWSIZE, + input SAXIHP3AWVALID, + input SAXIHP3BREADY, + input SAXIHP3RDISSUECAP1EN, + input SAXIHP3RREADY, + input [63:0] SAXIHP3WDATA, + input [5:0] SAXIHP3WID, + input SAXIHP3WLAST, + input SAXIHP3WRISSUECAP1EN, + input [7:0] SAXIHP3WSTRB, + input SAXIHP3WVALID +); + +// define constants + localparam MODULE_NAME = "PS7"; + + tri0 glblGSR = glbl.GSR; + + wire DMA0DAVALID_out; + wire DMA0DRREADY_out; + wire DMA0RSTN_out; + wire DMA1DAVALID_out; + wire DMA1DRREADY_out; + wire DMA1RSTN_out; + wire DMA2DAVALID_out; + wire DMA2DRREADY_out; + wire DMA2RSTN_out; + wire DMA3DAVALID_out; + wire DMA3DRREADY_out; + wire DMA3RSTN_out; + wire EMIOCAN0PHYTX_out; + wire EMIOCAN1PHYTX_out; + wire EMIOENET0GMIITXEN_out; + wire EMIOENET0GMIITXER_out; + wire EMIOENET0MDIOMDC_out; + wire EMIOENET0MDIOO_out; + wire EMIOENET0MDIOTN_out; + wire EMIOENET0PTPDELAYREQRX_out; + wire EMIOENET0PTPDELAYREQTX_out; + wire EMIOENET0PTPPDELAYREQRX_out; + wire EMIOENET0PTPPDELAYREQTX_out; + wire EMIOENET0PTPPDELAYRESPRX_out; + wire EMIOENET0PTPPDELAYRESPTX_out; + wire EMIOENET0PTPSYNCFRAMERX_out; + wire EMIOENET0PTPSYNCFRAMETX_out; + wire EMIOENET0SOFRX_out; + wire EMIOENET0SOFTX_out; + wire EMIOENET1GMIITXEN_out; + wire EMIOENET1GMIITXER_out; + wire EMIOENET1MDIOMDC_out; + wire EMIOENET1MDIOO_out; + wire EMIOENET1MDIOTN_out; + wire EMIOENET1PTPDELAYREQRX_out; + wire EMIOENET1PTPDELAYREQTX_out; + wire EMIOENET1PTPPDELAYREQRX_out; + wire EMIOENET1PTPPDELAYREQTX_out; + wire EMIOENET1PTPPDELAYRESPRX_out; + wire EMIOENET1PTPPDELAYRESPTX_out; + wire EMIOENET1PTPSYNCFRAMERX_out; + wire EMIOENET1PTPSYNCFRAMETX_out; + wire EMIOENET1SOFRX_out; + wire EMIOENET1SOFTX_out; + wire EMIOI2C0SCLO_out; + wire EMIOI2C0SCLTN_out; + wire EMIOI2C0SDAO_out; + wire EMIOI2C0SDATN_out; + wire EMIOI2C1SCLO_out; + wire EMIOI2C1SCLTN_out; + wire EMIOI2C1SDAO_out; + wire EMIOI2C1SDATN_out; + wire EMIOPJTAGTDO_out; + wire EMIOPJTAGTDTN_out; + wire EMIOSDIO0BUSPOW_out; + wire EMIOSDIO0CLK_out; + wire EMIOSDIO0CMDO_out; + wire EMIOSDIO0CMDTN_out; + wire EMIOSDIO0LED_out; + wire EMIOSDIO1BUSPOW_out; + wire EMIOSDIO1CLK_out; + wire EMIOSDIO1CMDO_out; + wire EMIOSDIO1CMDTN_out; + wire EMIOSDIO1LED_out; + wire EMIOSPI0MOTN_out; + wire EMIOSPI0MO_out; + wire EMIOSPI0SCLKO_out; + wire EMIOSPI0SCLKTN_out; + wire EMIOSPI0SO_out; + wire EMIOSPI0SSNTN_out; + wire EMIOSPI0STN_out; + wire EMIOSPI1MOTN_out; + wire EMIOSPI1MO_out; + wire EMIOSPI1SCLKO_out; + wire EMIOSPI1SCLKTN_out; + wire EMIOSPI1SO_out; + wire EMIOSPI1SSNTN_out; + wire EMIOSPI1STN_out; + wire EMIOTRACECTL_out; + wire EMIOUART0DTRN_out; + wire EMIOUART0RTSN_out; + wire EMIOUART0TX_out; + wire EMIOUART1DTRN_out; + wire EMIOUART1RTSN_out; + wire EMIOUART1TX_out; + wire EMIOUSB0VBUSPWRSELECT_out; + wire EMIOUSB1VBUSPWRSELECT_out; + wire EMIOWDTRSTO_out; + wire EVENTEVENTO_out; + wire MAXIGP0ARESETN_out; + wire MAXIGP0ARVALID_out; + wire MAXIGP0AWVALID_out; + wire MAXIGP0BREADY_out; + wire MAXIGP0RREADY_out; + wire MAXIGP0WLAST_out; + wire MAXIGP0WVALID_out; + wire MAXIGP1ARESETN_out; + wire MAXIGP1ARVALID_out; + wire MAXIGP1AWVALID_out; + wire MAXIGP1BREADY_out; + wire MAXIGP1RREADY_out; + wire MAXIGP1WLAST_out; + wire MAXIGP1WVALID_out; + wire SAXIACPARESETN_out; + wire SAXIACPARREADY_out; + wire SAXIACPAWREADY_out; + wire SAXIACPBVALID_out; + wire SAXIACPRLAST_out; + wire SAXIACPRVALID_out; + wire SAXIACPWREADY_out; + wire SAXIGP0ARESETN_out; + wire SAXIGP0ARREADY_out; + wire SAXIGP0AWREADY_out; + wire SAXIGP0BVALID_out; + wire SAXIGP0RLAST_out; + wire SAXIGP0RVALID_out; + wire SAXIGP0WREADY_out; + wire SAXIGP1ARESETN_out; + wire SAXIGP1ARREADY_out; + wire SAXIGP1AWREADY_out; + wire SAXIGP1BVALID_out; + wire SAXIGP1RLAST_out; + wire SAXIGP1RVALID_out; + wire SAXIGP1WREADY_out; + wire SAXIHP0ARESETN_out; + wire SAXIHP0ARREADY_out; + wire SAXIHP0AWREADY_out; + wire SAXIHP0BVALID_out; + wire SAXIHP0RLAST_out; + wire SAXIHP0RVALID_out; + wire SAXIHP0WREADY_out; + wire SAXIHP1ARESETN_out; + wire SAXIHP1ARREADY_out; + wire SAXIHP1AWREADY_out; + wire SAXIHP1BVALID_out; + wire SAXIHP1RLAST_out; + wire SAXIHP1RVALID_out; + wire SAXIHP1WREADY_out; + wire SAXIHP2ARESETN_out; + wire SAXIHP2ARREADY_out; + wire SAXIHP2AWREADY_out; + wire SAXIHP2BVALID_out; + wire SAXIHP2RLAST_out; + wire SAXIHP2RVALID_out; + wire SAXIHP2WREADY_out; + wire SAXIHP3ARESETN_out; + wire SAXIHP3ARREADY_out; + wire SAXIHP3AWREADY_out; + wire SAXIHP3BVALID_out; + wire SAXIHP3RLAST_out; + wire SAXIHP3RVALID_out; + wire SAXIHP3WREADY_out; + wire [11:0] MAXIGP0ARID_out; + wire [11:0] MAXIGP0AWID_out; + wire [11:0] MAXIGP0WID_out; + wire [11:0] MAXIGP1ARID_out; + wire [11:0] MAXIGP1AWID_out; + wire [11:0] MAXIGP1WID_out; + wire [1:0] DMA0DATYPE_out; + wire [1:0] DMA1DATYPE_out; + wire [1:0] DMA2DATYPE_out; + wire [1:0] DMA3DATYPE_out; + wire [1:0] EMIOUSB0PORTINDCTL_out; + wire [1:0] EMIOUSB1PORTINDCTL_out; + wire [1:0] EVENTSTANDBYWFE_out; + wire [1:0] EVENTSTANDBYWFI_out; + wire [1:0] MAXIGP0ARBURST_out; + wire [1:0] MAXIGP0ARLOCK_out; + wire [1:0] MAXIGP0ARSIZE_out; + wire [1:0] MAXIGP0AWBURST_out; + wire [1:0] MAXIGP0AWLOCK_out; + wire [1:0] MAXIGP0AWSIZE_out; + wire [1:0] MAXIGP1ARBURST_out; + wire [1:0] MAXIGP1ARLOCK_out; + wire [1:0] MAXIGP1ARSIZE_out; + wire [1:0] MAXIGP1AWBURST_out; + wire [1:0] MAXIGP1AWLOCK_out; + wire [1:0] MAXIGP1AWSIZE_out; + wire [1:0] SAXIACPBRESP_out; + wire [1:0] SAXIACPRRESP_out; + wire [1:0] SAXIGP0BRESP_out; + wire [1:0] SAXIGP0RRESP_out; + wire [1:0] SAXIGP1BRESP_out; + wire [1:0] SAXIGP1RRESP_out; + wire [1:0] SAXIHP0BRESP_out; + wire [1:0] SAXIHP0RRESP_out; + wire [1:0] SAXIHP1BRESP_out; + wire [1:0] SAXIHP1RRESP_out; + wire [1:0] SAXIHP2BRESP_out; + wire [1:0] SAXIHP2RRESP_out; + wire [1:0] SAXIHP3BRESP_out; + wire [1:0] SAXIHP3RRESP_out; + wire [28:0] IRQP2F_out; + wire [2:0] EMIOSDIO0BUSVOLT_out; + wire [2:0] EMIOSDIO1BUSVOLT_out; + wire [2:0] EMIOSPI0SSON_out; + wire [2:0] EMIOSPI1SSON_out; + wire [2:0] EMIOTTC0WAVEO_out; + wire [2:0] EMIOTTC1WAVEO_out; + wire [2:0] MAXIGP0ARPROT_out; + wire [2:0] MAXIGP0AWPROT_out; + wire [2:0] MAXIGP1ARPROT_out; + wire [2:0] MAXIGP1AWPROT_out; + wire [2:0] SAXIACPBID_out; + wire [2:0] SAXIACPRID_out; + wire [2:0] SAXIHP0RACOUNT_out; + wire [2:0] SAXIHP1RACOUNT_out; + wire [2:0] SAXIHP2RACOUNT_out; + wire [2:0] SAXIHP3RACOUNT_out; + wire [31:0] EMIOTRACEDATA_out; + wire [31:0] FTMTP2FDEBUG_out; + wire [31:0] MAXIGP0ARADDR_out; + wire [31:0] MAXIGP0AWADDR_out; + wire [31:0] MAXIGP0WDATA_out; + wire [31:0] MAXIGP1ARADDR_out; + wire [31:0] MAXIGP1AWADDR_out; + wire [31:0] MAXIGP1WDATA_out; + wire [31:0] SAXIGP0RDATA_out; + wire [31:0] SAXIGP1RDATA_out; + wire [3:0] EMIOSDIO0DATAO_out; + wire [3:0] EMIOSDIO0DATATN_out; + wire [3:0] EMIOSDIO1DATAO_out; + wire [3:0] EMIOSDIO1DATATN_out; + wire [3:0] FCLKCLK_out; + wire [3:0] FCLKRESETN_out; + wire [3:0] FTMTF2PTRIGACK_out; + wire [3:0] FTMTP2FTRIG_out; + wire [3:0] MAXIGP0ARCACHE_out; + wire [3:0] MAXIGP0ARLEN_out; + wire [3:0] MAXIGP0ARQOS_out; + wire [3:0] MAXIGP0AWCACHE_out; + wire [3:0] MAXIGP0AWLEN_out; + wire [3:0] MAXIGP0AWQOS_out; + wire [3:0] MAXIGP0WSTRB_out; + wire [3:0] MAXIGP1ARCACHE_out; + wire [3:0] MAXIGP1ARLEN_out; + wire [3:0] MAXIGP1ARQOS_out; + wire [3:0] MAXIGP1AWCACHE_out; + wire [3:0] MAXIGP1AWLEN_out; + wire [3:0] MAXIGP1AWQOS_out; + wire [3:0] MAXIGP1WSTRB_out; + wire [5:0] SAXIGP0BID_out; + wire [5:0] SAXIGP0RID_out; + wire [5:0] SAXIGP1BID_out; + wire [5:0] SAXIGP1RID_out; + wire [5:0] SAXIHP0BID_out; + wire [5:0] SAXIHP0RID_out; + wire [5:0] SAXIHP0WACOUNT_out; + wire [5:0] SAXIHP1BID_out; + wire [5:0] SAXIHP1RID_out; + wire [5:0] SAXIHP1WACOUNT_out; + wire [5:0] SAXIHP2BID_out; + wire [5:0] SAXIHP2RID_out; + wire [5:0] SAXIHP2WACOUNT_out; + wire [5:0] SAXIHP3BID_out; + wire [5:0] SAXIHP3RID_out; + wire [5:0] SAXIHP3WACOUNT_out; + wire [63:0] EMIOGPIOO_out; + wire [63:0] EMIOGPIOTN_out; + wire [63:0] SAXIACPRDATA_out; + wire [63:0] SAXIHP0RDATA_out; + wire [63:0] SAXIHP1RDATA_out; + wire [63:0] SAXIHP2RDATA_out; + wire [63:0] SAXIHP3RDATA_out; + wire [7:0] EMIOENET0GMIITXD_out; + wire [7:0] EMIOENET1GMIITXD_out; + wire [7:0] SAXIHP0RCOUNT_out; + wire [7:0] SAXIHP0WCOUNT_out; + wire [7:0] SAXIHP1RCOUNT_out; + wire [7:0] SAXIHP1WCOUNT_out; + wire [7:0] SAXIHP2RCOUNT_out; + wire [7:0] SAXIHP2WCOUNT_out; + wire [7:0] SAXIHP3RCOUNT_out; + wire [7:0] SAXIHP3WCOUNT_out; + + wire DMA0ACLK_in; + wire DMA0DAREADY_in; + wire DMA0DRLAST_in; + wire DMA0DRVALID_in; + wire DMA1ACLK_in; + wire DMA1DAREADY_in; + wire DMA1DRLAST_in; + wire DMA1DRVALID_in; + wire DMA2ACLK_in; + wire DMA2DAREADY_in; + wire DMA2DRLAST_in; + wire DMA2DRVALID_in; + wire DMA3ACLK_in; + wire DMA3DAREADY_in; + wire DMA3DRLAST_in; + wire DMA3DRVALID_in; + wire EMIOCAN0PHYRX_in; + wire EMIOCAN1PHYRX_in; + wire EMIOENET0EXTINTIN_in; + wire EMIOENET0GMIICOL_in; + wire EMIOENET0GMIICRS_in; + wire EMIOENET0GMIIRXCLK_in; + wire EMIOENET0GMIIRXDV_in; + wire EMIOENET0GMIIRXER_in; + wire EMIOENET0GMIITXCLK_in; + wire EMIOENET0MDIOI_in; + wire EMIOENET1EXTINTIN_in; + wire EMIOENET1GMIICOL_in; + wire EMIOENET1GMIICRS_in; + wire EMIOENET1GMIIRXCLK_in; + wire EMIOENET1GMIIRXDV_in; + wire EMIOENET1GMIIRXER_in; + wire EMIOENET1GMIITXCLK_in; + wire EMIOENET1MDIOI_in; + wire EMIOI2C0SCLI_in; + wire EMIOI2C0SDAI_in; + wire EMIOI2C1SCLI_in; + wire EMIOI2C1SDAI_in; + wire EMIOPJTAGTCK_in; + wire EMIOPJTAGTDI_in; + wire EMIOPJTAGTMS_in; + wire EMIOSDIO0CDN_in; + wire EMIOSDIO0CLKFB_in; + wire EMIOSDIO0CMDI_in; + wire EMIOSDIO0WP_in; + wire EMIOSDIO1CDN_in; + wire EMIOSDIO1CLKFB_in; + wire EMIOSDIO1CMDI_in; + wire EMIOSDIO1WP_in; + wire EMIOSPI0MI_in; + wire EMIOSPI0SCLKI_in; + wire EMIOSPI0SI_in; + wire EMIOSPI0SSIN_in; + wire EMIOSPI1MI_in; + wire EMIOSPI1SCLKI_in; + wire EMIOSPI1SI_in; + wire EMIOSPI1SSIN_in; + wire EMIOSRAMINTIN_in; + wire EMIOTRACECLK_in; + wire EMIOUART0CTSN_in; + wire EMIOUART0DCDN_in; + wire EMIOUART0DSRN_in; + wire EMIOUART0RIN_in; + wire EMIOUART0RX_in; + wire EMIOUART1CTSN_in; + wire EMIOUART1DCDN_in; + wire EMIOUART1DSRN_in; + wire EMIOUART1RIN_in; + wire EMIOUART1RX_in; + wire EMIOUSB0VBUSPWRFAULT_in; + wire EMIOUSB1VBUSPWRFAULT_in; + wire EMIOWDTCLKI_in; + wire EVENTEVENTI_in; + wire FPGAIDLEN_in; + wire FTMDTRACEINCLOCK_in; + wire FTMDTRACEINVALID_in; + wire MAXIGP0ACLK_in; + wire MAXIGP0ARREADY_in; + wire MAXIGP0AWREADY_in; + wire MAXIGP0BVALID_in; + wire MAXIGP0RLAST_in; + wire MAXIGP0RVALID_in; + wire MAXIGP0WREADY_in; + wire MAXIGP1ACLK_in; + wire MAXIGP1ARREADY_in; + wire MAXIGP1AWREADY_in; + wire MAXIGP1BVALID_in; + wire MAXIGP1RLAST_in; + wire MAXIGP1RVALID_in; + wire MAXIGP1WREADY_in; + wire SAXIACPACLK_in; + wire SAXIACPARVALID_in; + wire SAXIACPAWVALID_in; + wire SAXIACPBREADY_in; + wire SAXIACPRREADY_in; + wire SAXIACPWLAST_in; + wire SAXIACPWVALID_in; + wire SAXIGP0ACLK_in; + wire SAXIGP0ARVALID_in; + wire SAXIGP0AWVALID_in; + wire SAXIGP0BREADY_in; + wire SAXIGP0RREADY_in; + wire SAXIGP0WLAST_in; + wire SAXIGP0WVALID_in; + wire SAXIGP1ACLK_in; + wire SAXIGP1ARVALID_in; + wire SAXIGP1AWVALID_in; + wire SAXIGP1BREADY_in; + wire SAXIGP1RREADY_in; + wire SAXIGP1WLAST_in; + wire SAXIGP1WVALID_in; + wire SAXIHP0ACLK_in; + wire SAXIHP0ARVALID_in; + wire SAXIHP0AWVALID_in; + wire SAXIHP0BREADY_in; + wire SAXIHP0RDISSUECAP1EN_in; + wire SAXIHP0RREADY_in; + wire SAXIHP0WLAST_in; + wire SAXIHP0WRISSUECAP1EN_in; + wire SAXIHP0WVALID_in; + wire SAXIHP1ACLK_in; + wire SAXIHP1ARVALID_in; + wire SAXIHP1AWVALID_in; + wire SAXIHP1BREADY_in; + wire SAXIHP1RDISSUECAP1EN_in; + wire SAXIHP1RREADY_in; + wire SAXIHP1WLAST_in; + wire SAXIHP1WRISSUECAP1EN_in; + wire SAXIHP1WVALID_in; + wire SAXIHP2ACLK_in; + wire SAXIHP2ARVALID_in; + wire SAXIHP2AWVALID_in; + wire SAXIHP2BREADY_in; + wire SAXIHP2RDISSUECAP1EN_in; + wire SAXIHP2RREADY_in; + wire SAXIHP2WLAST_in; + wire SAXIHP2WRISSUECAP1EN_in; + wire SAXIHP2WVALID_in; + wire SAXIHP3ACLK_in; + wire SAXIHP3ARVALID_in; + wire SAXIHP3AWVALID_in; + wire SAXIHP3BREADY_in; + wire SAXIHP3RDISSUECAP1EN_in; + wire SAXIHP3RREADY_in; + wire SAXIHP3WLAST_in; + wire SAXIHP3WRISSUECAP1EN_in; + wire SAXIHP3WVALID_in; + wire [11:0] MAXIGP0BID_in; + wire [11:0] MAXIGP0RID_in; + wire [11:0] MAXIGP1BID_in; + wire [11:0] MAXIGP1RID_in; + wire [19:0] IRQF2P_in; + wire [1:0] DMA0DRTYPE_in; + wire [1:0] DMA1DRTYPE_in; + wire [1:0] DMA2DRTYPE_in; + wire [1:0] DMA3DRTYPE_in; + wire [1:0] MAXIGP0BRESP_in; + wire [1:0] MAXIGP0RRESP_in; + wire [1:0] MAXIGP1BRESP_in; + wire [1:0] MAXIGP1RRESP_in; + wire [1:0] SAXIACPARBURST_in; + wire [1:0] SAXIACPARLOCK_in; + wire [1:0] SAXIACPARSIZE_in; + wire [1:0] SAXIACPAWBURST_in; + wire [1:0] SAXIACPAWLOCK_in; + wire [1:0] SAXIACPAWSIZE_in; + wire [1:0] SAXIGP0ARBURST_in; + wire [1:0] SAXIGP0ARLOCK_in; + wire [1:0] SAXIGP0ARSIZE_in; + wire [1:0] SAXIGP0AWBURST_in; + wire [1:0] SAXIGP0AWLOCK_in; + wire [1:0] SAXIGP0AWSIZE_in; + wire [1:0] SAXIGP1ARBURST_in; + wire [1:0] SAXIGP1ARLOCK_in; + wire [1:0] SAXIGP1ARSIZE_in; + wire [1:0] SAXIGP1AWBURST_in; + wire [1:0] SAXIGP1AWLOCK_in; + wire [1:0] SAXIGP1AWSIZE_in; + wire [1:0] SAXIHP0ARBURST_in; + wire [1:0] SAXIHP0ARLOCK_in; + wire [1:0] SAXIHP0ARSIZE_in; + wire [1:0] SAXIHP0AWBURST_in; + wire [1:0] SAXIHP0AWLOCK_in; + wire [1:0] SAXIHP0AWSIZE_in; + wire [1:0] SAXIHP1ARBURST_in; + wire [1:0] SAXIHP1ARLOCK_in; + wire [1:0] SAXIHP1ARSIZE_in; + wire [1:0] SAXIHP1AWBURST_in; + wire [1:0] SAXIHP1AWLOCK_in; + wire [1:0] SAXIHP1AWSIZE_in; + wire [1:0] SAXIHP2ARBURST_in; + wire [1:0] SAXIHP2ARLOCK_in; + wire [1:0] SAXIHP2ARSIZE_in; + wire [1:0] SAXIHP2AWBURST_in; + wire [1:0] SAXIHP2AWLOCK_in; + wire [1:0] SAXIHP2AWSIZE_in; + wire [1:0] SAXIHP3ARBURST_in; + wire [1:0] SAXIHP3ARLOCK_in; + wire [1:0] SAXIHP3ARSIZE_in; + wire [1:0] SAXIHP3AWBURST_in; + wire [1:0] SAXIHP3AWLOCK_in; + wire [1:0] SAXIHP3AWSIZE_in; + wire [2:0] EMIOTTC0CLKI_in; + wire [2:0] EMIOTTC1CLKI_in; + wire [2:0] SAXIACPARID_in; + wire [2:0] SAXIACPARPROT_in; + wire [2:0] SAXIACPAWID_in; + wire [2:0] SAXIACPAWPROT_in; + wire [2:0] SAXIACPWID_in; + wire [2:0] SAXIGP0ARPROT_in; + wire [2:0] SAXIGP0AWPROT_in; + wire [2:0] SAXIGP1ARPROT_in; + wire [2:0] SAXIGP1AWPROT_in; + wire [2:0] SAXIHP0ARPROT_in; + wire [2:0] SAXIHP0AWPROT_in; + wire [2:0] SAXIHP1ARPROT_in; + wire [2:0] SAXIHP1AWPROT_in; + wire [2:0] SAXIHP2ARPROT_in; + wire [2:0] SAXIHP2AWPROT_in; + wire [2:0] SAXIHP3ARPROT_in; + wire [2:0] SAXIHP3AWPROT_in; + wire [31:0] FTMDTRACEINDATA_in; + wire [31:0] FTMTF2PDEBUG_in; + wire [31:0] MAXIGP0RDATA_in; + wire [31:0] MAXIGP1RDATA_in; + wire [31:0] SAXIACPARADDR_in; + wire [31:0] SAXIACPAWADDR_in; + wire [31:0] SAXIGP0ARADDR_in; + wire [31:0] SAXIGP0AWADDR_in; + wire [31:0] SAXIGP0WDATA_in; + wire [31:0] SAXIGP1ARADDR_in; + wire [31:0] SAXIGP1AWADDR_in; + wire [31:0] SAXIGP1WDATA_in; + wire [31:0] SAXIHP0ARADDR_in; + wire [31:0] SAXIHP0AWADDR_in; + wire [31:0] SAXIHP1ARADDR_in; + wire [31:0] SAXIHP1AWADDR_in; + wire [31:0] SAXIHP2ARADDR_in; + wire [31:0] SAXIHP2AWADDR_in; + wire [31:0] SAXIHP3ARADDR_in; + wire [31:0] SAXIHP3AWADDR_in; + wire [3:0] DDRARB_in; + wire [3:0] EMIOSDIO0DATAI_in; + wire [3:0] EMIOSDIO1DATAI_in; + wire [3:0] FCLKCLKTRIGN_in; + wire [3:0] FTMDTRACEINATID_in; + wire [3:0] FTMTF2PTRIG_in; + wire [3:0] FTMTP2FTRIGACK_in; + wire [3:0] SAXIACPARCACHE_in; + wire [3:0] SAXIACPARLEN_in; + wire [3:0] SAXIACPARQOS_in; + wire [3:0] SAXIACPAWCACHE_in; + wire [3:0] SAXIACPAWLEN_in; + wire [3:0] SAXIACPAWQOS_in; + wire [3:0] SAXIGP0ARCACHE_in; + wire [3:0] SAXIGP0ARLEN_in; + wire [3:0] SAXIGP0ARQOS_in; + wire [3:0] SAXIGP0AWCACHE_in; + wire [3:0] SAXIGP0AWLEN_in; + wire [3:0] SAXIGP0AWQOS_in; + wire [3:0] SAXIGP0WSTRB_in; + wire [3:0] SAXIGP1ARCACHE_in; + wire [3:0] SAXIGP1ARLEN_in; + wire [3:0] SAXIGP1ARQOS_in; + wire [3:0] SAXIGP1AWCACHE_in; + wire [3:0] SAXIGP1AWLEN_in; + wire [3:0] SAXIGP1AWQOS_in; + wire [3:0] SAXIGP1WSTRB_in; + wire [3:0] SAXIHP0ARCACHE_in; + wire [3:0] SAXIHP0ARLEN_in; + wire [3:0] SAXIHP0ARQOS_in; + wire [3:0] SAXIHP0AWCACHE_in; + wire [3:0] SAXIHP0AWLEN_in; + wire [3:0] SAXIHP0AWQOS_in; + wire [3:0] SAXIHP1ARCACHE_in; + wire [3:0] SAXIHP1ARLEN_in; + wire [3:0] SAXIHP1ARQOS_in; + wire [3:0] SAXIHP1AWCACHE_in; + wire [3:0] SAXIHP1AWLEN_in; + wire [3:0] SAXIHP1AWQOS_in; + wire [3:0] SAXIHP2ARCACHE_in; + wire [3:0] SAXIHP2ARLEN_in; + wire [3:0] SAXIHP2ARQOS_in; + wire [3:0] SAXIHP2AWCACHE_in; + wire [3:0] SAXIHP2AWLEN_in; + wire [3:0] SAXIHP2AWQOS_in; + wire [3:0] SAXIHP3ARCACHE_in; + wire [3:0] SAXIHP3ARLEN_in; + wire [3:0] SAXIHP3ARQOS_in; + wire [3:0] SAXIHP3AWCACHE_in; + wire [3:0] SAXIHP3AWLEN_in; + wire [3:0] SAXIHP3AWQOS_in; + wire [4:0] SAXIACPARUSER_in; + wire [4:0] SAXIACPAWUSER_in; + wire [5:0] SAXIGP0ARID_in; + wire [5:0] SAXIGP0AWID_in; + wire [5:0] SAXIGP0WID_in; + wire [5:0] SAXIGP1ARID_in; + wire [5:0] SAXIGP1AWID_in; + wire [5:0] SAXIGP1WID_in; + wire [5:0] SAXIHP0ARID_in; + wire [5:0] SAXIHP0AWID_in; + wire [5:0] SAXIHP0WID_in; + wire [5:0] SAXIHP1ARID_in; + wire [5:0] SAXIHP1AWID_in; + wire [5:0] SAXIHP1WID_in; + wire [5:0] SAXIHP2ARID_in; + wire [5:0] SAXIHP2AWID_in; + wire [5:0] SAXIHP2WID_in; + wire [5:0] SAXIHP3ARID_in; + wire [5:0] SAXIHP3AWID_in; + wire [5:0] SAXIHP3WID_in; + wire [63:0] EMIOGPIOI_in; + wire [63:0] SAXIACPWDATA_in; + wire [63:0] SAXIHP0WDATA_in; + wire [63:0] SAXIHP1WDATA_in; + wire [63:0] SAXIHP2WDATA_in; + wire [63:0] SAXIHP3WDATA_in; + wire [7:0] EMIOENET0GMIIRXD_in; + wire [7:0] EMIOENET1GMIIRXD_in; + wire [7:0] SAXIACPWSTRB_in; + wire [7:0] SAXIHP0WSTRB_in; + wire [7:0] SAXIHP1WSTRB_in; + wire [7:0] SAXIHP2WSTRB_in; + wire [7:0] SAXIHP3WSTRB_in; + +`ifdef XIL_TIMING + wire DMA0ACLK_delay; + wire DMA0DAREADY_delay; + wire DMA0DRLAST_delay; + wire DMA0DRVALID_delay; + wire DMA1ACLK_delay; + wire DMA1DAREADY_delay; + wire DMA1DRLAST_delay; + wire DMA1DRVALID_delay; + wire DMA2ACLK_delay; + wire DMA2DAREADY_delay; + wire DMA2DRLAST_delay; + wire DMA2DRVALID_delay; + wire DMA3ACLK_delay; + wire DMA3DAREADY_delay; + wire DMA3DRLAST_delay; + wire DMA3DRVALID_delay; + wire EMIOENET0GMIIRXCLK_delay; + wire EMIOENET0GMIIRXDV_delay; + wire EMIOENET0GMIIRXER_delay; + wire EMIOENET1GMIIRXCLK_delay; + wire EMIOENET1GMIIRXDV_delay; + wire EMIOENET1GMIIRXER_delay; + wire EMIOPJTAGTCK_delay; + wire EMIOPJTAGTDI_delay; + wire EMIOPJTAGTMS_delay; + wire EMIOSDIO0CLKFB_delay; + wire EMIOSDIO0CMDI_delay; + wire EMIOSDIO1CLKFB_delay; + wire EMIOSDIO1CMDI_delay; + wire FTMDTRACEINCLOCK_delay; + wire FTMDTRACEINVALID_delay; + wire MAXIGP0ACLK_delay; + wire MAXIGP0ARREADY_delay; + wire MAXIGP0AWREADY_delay; + wire MAXIGP0BVALID_delay; + wire MAXIGP0RLAST_delay; + wire MAXIGP0RVALID_delay; + wire MAXIGP0WREADY_delay; + wire MAXIGP1ACLK_delay; + wire MAXIGP1ARREADY_delay; + wire MAXIGP1AWREADY_delay; + wire MAXIGP1BVALID_delay; + wire MAXIGP1RLAST_delay; + wire MAXIGP1RVALID_delay; + wire MAXIGP1WREADY_delay; + wire SAXIACPACLK_delay; + wire SAXIACPARVALID_delay; + wire SAXIACPAWVALID_delay; + wire SAXIACPBREADY_delay; + wire SAXIACPRREADY_delay; + wire SAXIACPWLAST_delay; + wire SAXIACPWVALID_delay; + wire SAXIGP0ACLK_delay; + wire SAXIGP0ARVALID_delay; + wire SAXIGP0AWVALID_delay; + wire SAXIGP0BREADY_delay; + wire SAXIGP0RREADY_delay; + wire SAXIGP0WLAST_delay; + wire SAXIGP0WVALID_delay; + wire SAXIGP1ACLK_delay; + wire SAXIGP1ARVALID_delay; + wire SAXIGP1AWVALID_delay; + wire SAXIGP1BREADY_delay; + wire SAXIGP1RREADY_delay; + wire SAXIGP1WLAST_delay; + wire SAXIGP1WVALID_delay; + wire SAXIHP0ACLK_delay; + wire SAXIHP0ARVALID_delay; + wire SAXIHP0AWVALID_delay; + wire SAXIHP0BREADY_delay; + wire SAXIHP0RREADY_delay; + wire SAXIHP0WLAST_delay; + wire SAXIHP0WVALID_delay; + wire SAXIHP1ACLK_delay; + wire SAXIHP1ARVALID_delay; + wire SAXIHP1AWVALID_delay; + wire SAXIHP1BREADY_delay; + wire SAXIHP1RREADY_delay; + wire SAXIHP1WLAST_delay; + wire SAXIHP1WVALID_delay; + wire SAXIHP2ACLK_delay; + wire SAXIHP2ARVALID_delay; + wire SAXIHP2AWVALID_delay; + wire SAXIHP2BREADY_delay; + wire SAXIHP2RREADY_delay; + wire SAXIHP2WLAST_delay; + wire SAXIHP2WVALID_delay; + wire SAXIHP3ACLK_delay; + wire SAXIHP3ARVALID_delay; + wire SAXIHP3AWVALID_delay; + wire SAXIHP3BREADY_delay; + wire SAXIHP3RREADY_delay; + wire SAXIHP3WLAST_delay; + wire SAXIHP3WVALID_delay; + wire [11:0] MAXIGP0BID_delay; + wire [11:0] MAXIGP0RID_delay; + wire [11:0] MAXIGP1BID_delay; + wire [11:0] MAXIGP1RID_delay; + wire [1:0] DMA0DRTYPE_delay; + wire [1:0] DMA1DRTYPE_delay; + wire [1:0] DMA2DRTYPE_delay; + wire [1:0] DMA3DRTYPE_delay; + wire [1:0] MAXIGP0BRESP_delay; + wire [1:0] MAXIGP0RRESP_delay; + wire [1:0] MAXIGP1BRESP_delay; + wire [1:0] MAXIGP1RRESP_delay; + wire [1:0] SAXIACPARBURST_delay; + wire [1:0] SAXIACPARLOCK_delay; + wire [1:0] SAXIACPARSIZE_delay; + wire [1:0] SAXIACPAWBURST_delay; + wire [1:0] SAXIACPAWLOCK_delay; + wire [1:0] SAXIACPAWSIZE_delay; + wire [1:0] SAXIGP0ARBURST_delay; + wire [1:0] SAXIGP0ARLOCK_delay; + wire [1:0] SAXIGP0ARSIZE_delay; + wire [1:0] SAXIGP0AWBURST_delay; + wire [1:0] SAXIGP0AWLOCK_delay; + wire [1:0] SAXIGP0AWSIZE_delay; + wire [1:0] SAXIGP1ARBURST_delay; + wire [1:0] SAXIGP1ARLOCK_delay; + wire [1:0] SAXIGP1ARSIZE_delay; + wire [1:0] SAXIGP1AWBURST_delay; + wire [1:0] SAXIGP1AWLOCK_delay; + wire [1:0] SAXIGP1AWSIZE_delay; + wire [1:0] SAXIHP0ARBURST_delay; + wire [1:0] SAXIHP0ARLOCK_delay; + wire [1:0] SAXIHP0ARSIZE_delay; + wire [1:0] SAXIHP0AWBURST_delay; + wire [1:0] SAXIHP0AWLOCK_delay; + wire [1:0] SAXIHP0AWSIZE_delay; + wire [1:0] SAXIHP1ARBURST_delay; + wire [1:0] SAXIHP1ARLOCK_delay; + wire [1:0] SAXIHP1ARSIZE_delay; + wire [1:0] SAXIHP1AWBURST_delay; + wire [1:0] SAXIHP1AWLOCK_delay; + wire [1:0] SAXIHP1AWSIZE_delay; + wire [1:0] SAXIHP2ARBURST_delay; + wire [1:0] SAXIHP2ARLOCK_delay; + wire [1:0] SAXIHP2ARSIZE_delay; + wire [1:0] SAXIHP2AWBURST_delay; + wire [1:0] SAXIHP2AWLOCK_delay; + wire [1:0] SAXIHP2AWSIZE_delay; + wire [1:0] SAXIHP3ARBURST_delay; + wire [1:0] SAXIHP3ARLOCK_delay; + wire [1:0] SAXIHP3ARSIZE_delay; + wire [1:0] SAXIHP3AWBURST_delay; + wire [1:0] SAXIHP3AWLOCK_delay; + wire [1:0] SAXIHP3AWSIZE_delay; + wire [2:0] SAXIACPARID_delay; + wire [2:0] SAXIACPARPROT_delay; + wire [2:0] SAXIACPAWID_delay; + wire [2:0] SAXIACPAWPROT_delay; + wire [2:0] SAXIACPWID_delay; + wire [2:0] SAXIGP0ARPROT_delay; + wire [2:0] SAXIGP0AWPROT_delay; + wire [2:0] SAXIGP1ARPROT_delay; + wire [2:0] SAXIGP1AWPROT_delay; + wire [2:0] SAXIHP0ARPROT_delay; + wire [2:0] SAXIHP0AWPROT_delay; + wire [2:0] SAXIHP1ARPROT_delay; + wire [2:0] SAXIHP1AWPROT_delay; + wire [2:0] SAXIHP2ARPROT_delay; + wire [2:0] SAXIHP2AWPROT_delay; + wire [2:0] SAXIHP3ARPROT_delay; + wire [2:0] SAXIHP3AWPROT_delay; + wire [31:0] FTMDTRACEINDATA_delay; + wire [31:0] MAXIGP0RDATA_delay; + wire [31:0] MAXIGP1RDATA_delay; + wire [31:0] SAXIACPARADDR_delay; + wire [31:0] SAXIACPAWADDR_delay; + wire [31:0] SAXIGP0ARADDR_delay; + wire [31:0] SAXIGP0AWADDR_delay; + wire [31:0] SAXIGP0WDATA_delay; + wire [31:0] SAXIGP1ARADDR_delay; + wire [31:0] SAXIGP1AWADDR_delay; + wire [31:0] SAXIGP1WDATA_delay; + wire [31:0] SAXIHP0ARADDR_delay; + wire [31:0] SAXIHP0AWADDR_delay; + wire [31:0] SAXIHP1ARADDR_delay; + wire [31:0] SAXIHP1AWADDR_delay; + wire [31:0] SAXIHP2ARADDR_delay; + wire [31:0] SAXIHP2AWADDR_delay; + wire [31:0] SAXIHP3ARADDR_delay; + wire [31:0] SAXIHP3AWADDR_delay; + wire [3:0] EMIOSDIO0DATAI_delay; + wire [3:0] EMIOSDIO1DATAI_delay; + wire [3:0] FTMDTRACEINATID_delay; + wire [3:0] SAXIACPARCACHE_delay; + wire [3:0] SAXIACPARLEN_delay; + wire [3:0] SAXIACPAWCACHE_delay; + wire [3:0] SAXIACPAWLEN_delay; + wire [3:0] SAXIGP0ARCACHE_delay; + wire [3:0] SAXIGP0ARLEN_delay; + wire [3:0] SAXIGP0ARQOS_delay; + wire [3:0] SAXIGP0AWCACHE_delay; + wire [3:0] SAXIGP0AWLEN_delay; + wire [3:0] SAXIGP0AWQOS_delay; + wire [3:0] SAXIGP0WSTRB_delay; + wire [3:0] SAXIGP1ARCACHE_delay; + wire [3:0] SAXIGP1ARLEN_delay; + wire [3:0] SAXIGP1ARQOS_delay; + wire [3:0] SAXIGP1AWCACHE_delay; + wire [3:0] SAXIGP1AWLEN_delay; + wire [3:0] SAXIGP1AWQOS_delay; + wire [3:0] SAXIGP1WSTRB_delay; + wire [3:0] SAXIHP0ARCACHE_delay; + wire [3:0] SAXIHP0ARLEN_delay; + wire [3:0] SAXIHP0ARQOS_delay; + wire [3:0] SAXIHP0AWCACHE_delay; + wire [3:0] SAXIHP0AWLEN_delay; + wire [3:0] SAXIHP0AWQOS_delay; + wire [3:0] SAXIHP1ARCACHE_delay; + wire [3:0] SAXIHP1ARLEN_delay; + wire [3:0] SAXIHP1ARQOS_delay; + wire [3:0] SAXIHP1AWCACHE_delay; + wire [3:0] SAXIHP1AWLEN_delay; + wire [3:0] SAXIHP1AWQOS_delay; + wire [3:0] SAXIHP2ARCACHE_delay; + wire [3:0] SAXIHP2ARLEN_delay; + wire [3:0] SAXIHP2ARQOS_delay; + wire [3:0] SAXIHP2AWCACHE_delay; + wire [3:0] SAXIHP2AWLEN_delay; + wire [3:0] SAXIHP2AWQOS_delay; + wire [3:0] SAXIHP3ARCACHE_delay; + wire [3:0] SAXIHP3ARLEN_delay; + wire [3:0] SAXIHP3ARQOS_delay; + wire [3:0] SAXIHP3AWCACHE_delay; + wire [3:0] SAXIHP3AWLEN_delay; + wire [3:0] SAXIHP3AWQOS_delay; + wire [4:0] SAXIACPARUSER_delay; + wire [4:0] SAXIACPAWUSER_delay; + wire [5:0] SAXIGP0ARID_delay; + wire [5:0] SAXIGP0AWID_delay; + wire [5:0] SAXIGP0WID_delay; + wire [5:0] SAXIGP1ARID_delay; + wire [5:0] SAXIGP1AWID_delay; + wire [5:0] SAXIGP1WID_delay; + wire [5:0] SAXIHP0ARID_delay; + wire [5:0] SAXIHP0AWID_delay; + wire [5:0] SAXIHP0WID_delay; + wire [5:0] SAXIHP1ARID_delay; + wire [5:0] SAXIHP1AWID_delay; + wire [5:0] SAXIHP1WID_delay; + wire [5:0] SAXIHP2ARID_delay; + wire [5:0] SAXIHP2AWID_delay; + wire [5:0] SAXIHP2WID_delay; + wire [5:0] SAXIHP3ARID_delay; + wire [5:0] SAXIHP3AWID_delay; + wire [5:0] SAXIHP3WID_delay; + wire [63:0] SAXIACPWDATA_delay; + wire [63:0] SAXIHP0WDATA_delay; + wire [63:0] SAXIHP1WDATA_delay; + wire [63:0] SAXIHP2WDATA_delay; + wire [63:0] SAXIHP3WDATA_delay; + wire [7:0] EMIOENET0GMIIRXD_delay; + wire [7:0] EMIOENET1GMIIRXD_delay; + wire [7:0] SAXIACPWSTRB_delay; + wire [7:0] SAXIHP0WSTRB_delay; + wire [7:0] SAXIHP1WSTRB_delay; + wire [7:0] SAXIHP2WSTRB_delay; + wire [7:0] SAXIHP3WSTRB_delay; +`endif + + assign DMA0DATYPE = DMA0DATYPE_out; + assign DMA0DAVALID = DMA0DAVALID_out; + assign DMA0DRREADY = DMA0DRREADY_out; + assign DMA0RSTN = DMA0RSTN_out; + assign DMA1DATYPE = DMA1DATYPE_out; + assign DMA1DAVALID = DMA1DAVALID_out; + assign DMA1DRREADY = DMA1DRREADY_out; + assign DMA1RSTN = DMA1RSTN_out; + assign DMA2DATYPE = DMA2DATYPE_out; + assign DMA2DAVALID = DMA2DAVALID_out; + assign DMA2DRREADY = DMA2DRREADY_out; + assign DMA2RSTN = DMA2RSTN_out; + assign DMA3DATYPE = DMA3DATYPE_out; + assign DMA3DAVALID = DMA3DAVALID_out; + assign DMA3DRREADY = DMA3DRREADY_out; + assign DMA3RSTN = DMA3RSTN_out; + assign EMIOCAN0PHYTX = EMIOCAN0PHYTX_out; + assign EMIOCAN1PHYTX = EMIOCAN1PHYTX_out; + assign EMIOENET0GMIITXD = EMIOENET0GMIITXD_out; + assign EMIOENET0GMIITXEN = EMIOENET0GMIITXEN_out; + assign EMIOENET0GMIITXER = EMIOENET0GMIITXER_out; + assign EMIOENET0MDIOMDC = EMIOENET0MDIOMDC_out; + assign EMIOENET0MDIOO = EMIOENET0MDIOO_out; + assign EMIOENET0MDIOTN = EMIOENET0MDIOTN_out; + assign EMIOENET0PTPDELAYREQRX = EMIOENET0PTPDELAYREQRX_out; + assign EMIOENET0PTPDELAYREQTX = EMIOENET0PTPDELAYREQTX_out; + assign EMIOENET0PTPPDELAYREQRX = EMIOENET0PTPPDELAYREQRX_out; + assign EMIOENET0PTPPDELAYREQTX = EMIOENET0PTPPDELAYREQTX_out; + assign EMIOENET0PTPPDELAYRESPRX = EMIOENET0PTPPDELAYRESPRX_out; + assign EMIOENET0PTPPDELAYRESPTX = EMIOENET0PTPPDELAYRESPTX_out; + assign EMIOENET0PTPSYNCFRAMERX = EMIOENET0PTPSYNCFRAMERX_out; + assign EMIOENET0PTPSYNCFRAMETX = EMIOENET0PTPSYNCFRAMETX_out; + assign EMIOENET0SOFRX = EMIOENET0SOFRX_out; + assign EMIOENET0SOFTX = EMIOENET0SOFTX_out; + assign EMIOENET1GMIITXD = EMIOENET1GMIITXD_out; + assign EMIOENET1GMIITXEN = EMIOENET1GMIITXEN_out; + assign EMIOENET1GMIITXER = EMIOENET1GMIITXER_out; + assign EMIOENET1MDIOMDC = EMIOENET1MDIOMDC_out; + assign EMIOENET1MDIOO = EMIOENET1MDIOO_out; + assign EMIOENET1MDIOTN = EMIOENET1MDIOTN_out; + assign EMIOENET1PTPDELAYREQRX = EMIOENET1PTPDELAYREQRX_out; + assign EMIOENET1PTPDELAYREQTX = EMIOENET1PTPDELAYREQTX_out; + assign EMIOENET1PTPPDELAYREQRX = EMIOENET1PTPPDELAYREQRX_out; + assign EMIOENET1PTPPDELAYREQTX = EMIOENET1PTPPDELAYREQTX_out; + assign EMIOENET1PTPPDELAYRESPRX = EMIOENET1PTPPDELAYRESPRX_out; + assign EMIOENET1PTPPDELAYRESPTX = EMIOENET1PTPPDELAYRESPTX_out; + assign EMIOENET1PTPSYNCFRAMERX = EMIOENET1PTPSYNCFRAMERX_out; + assign EMIOENET1PTPSYNCFRAMETX = EMIOENET1PTPSYNCFRAMETX_out; + assign EMIOENET1SOFRX = EMIOENET1SOFRX_out; + assign EMIOENET1SOFTX = EMIOENET1SOFTX_out; + assign EMIOGPIOO = EMIOGPIOO_out; + assign EMIOGPIOTN = EMIOGPIOTN_out; + assign EMIOI2C0SCLO = EMIOI2C0SCLO_out; + assign EMIOI2C0SCLTN = EMIOI2C0SCLTN_out; + assign EMIOI2C0SDAO = EMIOI2C0SDAO_out; + assign EMIOI2C0SDATN = EMIOI2C0SDATN_out; + assign EMIOI2C1SCLO = EMIOI2C1SCLO_out; + assign EMIOI2C1SCLTN = EMIOI2C1SCLTN_out; + assign EMIOI2C1SDAO = EMIOI2C1SDAO_out; + assign EMIOI2C1SDATN = EMIOI2C1SDATN_out; + assign EMIOPJTAGTDO = EMIOPJTAGTDO_out; + assign EMIOPJTAGTDTN = EMIOPJTAGTDTN_out; + assign EMIOSDIO0BUSPOW = EMIOSDIO0BUSPOW_out; + assign EMIOSDIO0BUSVOLT = EMIOSDIO0BUSVOLT_out; + assign EMIOSDIO0CLK = EMIOSDIO0CLK_out; + assign EMIOSDIO0CMDO = EMIOSDIO0CMDO_out; + assign EMIOSDIO0CMDTN = EMIOSDIO0CMDTN_out; + assign EMIOSDIO0DATAO = EMIOSDIO0DATAO_out; + assign EMIOSDIO0DATATN = EMIOSDIO0DATATN_out; + assign EMIOSDIO0LED = EMIOSDIO0LED_out; + assign EMIOSDIO1BUSPOW = EMIOSDIO1BUSPOW_out; + assign EMIOSDIO1BUSVOLT = EMIOSDIO1BUSVOLT_out; + assign EMIOSDIO1CLK = EMIOSDIO1CLK_out; + assign EMIOSDIO1CMDO = EMIOSDIO1CMDO_out; + assign EMIOSDIO1CMDTN = EMIOSDIO1CMDTN_out; + assign EMIOSDIO1DATAO = EMIOSDIO1DATAO_out; + assign EMIOSDIO1DATATN = EMIOSDIO1DATATN_out; + assign EMIOSDIO1LED = EMIOSDIO1LED_out; + assign EMIOSPI0MO = EMIOSPI0MO_out; + assign EMIOSPI0MOTN = EMIOSPI0MOTN_out; + assign EMIOSPI0SCLKO = EMIOSPI0SCLKO_out; + assign EMIOSPI0SCLKTN = EMIOSPI0SCLKTN_out; + assign EMIOSPI0SO = EMIOSPI0SO_out; + assign EMIOSPI0SSNTN = EMIOSPI0SSNTN_out; + assign EMIOSPI0SSON = EMIOSPI0SSON_out; + assign EMIOSPI0STN = EMIOSPI0STN_out; + assign EMIOSPI1MO = EMIOSPI1MO_out; + assign EMIOSPI1MOTN = EMIOSPI1MOTN_out; + assign EMIOSPI1SCLKO = EMIOSPI1SCLKO_out; + assign EMIOSPI1SCLKTN = EMIOSPI1SCLKTN_out; + assign EMIOSPI1SO = EMIOSPI1SO_out; + assign EMIOSPI1SSNTN = EMIOSPI1SSNTN_out; + assign EMIOSPI1SSON = EMIOSPI1SSON_out; + assign EMIOSPI1STN = EMIOSPI1STN_out; + assign EMIOTRACECTL = EMIOTRACECTL_out; + assign EMIOTRACEDATA = EMIOTRACEDATA_out; + assign EMIOTTC0WAVEO = EMIOTTC0WAVEO_out; + assign EMIOTTC1WAVEO = EMIOTTC1WAVEO_out; + assign EMIOUART0DTRN = EMIOUART0DTRN_out; + assign EMIOUART0RTSN = EMIOUART0RTSN_out; + assign EMIOUART0TX = EMIOUART0TX_out; + assign EMIOUART1DTRN = EMIOUART1DTRN_out; + assign EMIOUART1RTSN = EMIOUART1RTSN_out; + assign EMIOUART1TX = EMIOUART1TX_out; + assign EMIOUSB0PORTINDCTL = EMIOUSB0PORTINDCTL_out; + assign EMIOUSB0VBUSPWRSELECT = EMIOUSB0VBUSPWRSELECT_out; + assign EMIOUSB1PORTINDCTL = EMIOUSB1PORTINDCTL_out; + assign EMIOUSB1VBUSPWRSELECT = EMIOUSB1VBUSPWRSELECT_out; + assign EMIOWDTRSTO = EMIOWDTRSTO_out; + assign EVENTEVENTO = EVENTEVENTO_out; + assign EVENTSTANDBYWFE = EVENTSTANDBYWFE_out; + assign EVENTSTANDBYWFI = EVENTSTANDBYWFI_out; + assign FCLKCLK = FCLKCLK_out; + assign FCLKRESETN = FCLKRESETN_out; + assign FTMTF2PTRIGACK = FTMTF2PTRIGACK_out; + assign FTMTP2FDEBUG = FTMTP2FDEBUG_out; + assign FTMTP2FTRIG = FTMTP2FTRIG_out; + assign IRQP2F = IRQP2F_out; + assign MAXIGP0ARADDR = MAXIGP0ARADDR_out; + assign MAXIGP0ARBURST = MAXIGP0ARBURST_out; + assign MAXIGP0ARCACHE = MAXIGP0ARCACHE_out; + assign MAXIGP0ARESETN = MAXIGP0ARESETN_out; + assign MAXIGP0ARID = MAXIGP0ARID_out; + assign MAXIGP0ARLEN = MAXIGP0ARLEN_out; + assign MAXIGP0ARLOCK = MAXIGP0ARLOCK_out; + assign MAXIGP0ARPROT = MAXIGP0ARPROT_out; + assign MAXIGP0ARQOS = MAXIGP0ARQOS_out; + assign MAXIGP0ARSIZE = MAXIGP0ARSIZE_out; + assign MAXIGP0ARVALID = MAXIGP0ARVALID_out; + assign MAXIGP0AWADDR = MAXIGP0AWADDR_out; + assign MAXIGP0AWBURST = MAXIGP0AWBURST_out; + assign MAXIGP0AWCACHE = MAXIGP0AWCACHE_out; + assign MAXIGP0AWID = MAXIGP0AWID_out; + assign MAXIGP0AWLEN = MAXIGP0AWLEN_out; + assign MAXIGP0AWLOCK = MAXIGP0AWLOCK_out; + assign MAXIGP0AWPROT = MAXIGP0AWPROT_out; + assign MAXIGP0AWQOS = MAXIGP0AWQOS_out; + assign MAXIGP0AWSIZE = MAXIGP0AWSIZE_out; + assign MAXIGP0AWVALID = MAXIGP0AWVALID_out; + assign MAXIGP0BREADY = MAXIGP0BREADY_out; + assign MAXIGP0RREADY = MAXIGP0RREADY_out; + assign MAXIGP0WDATA = MAXIGP0WDATA_out; + assign MAXIGP0WID = MAXIGP0WID_out; + assign MAXIGP0WLAST = MAXIGP0WLAST_out; + assign MAXIGP0WSTRB = MAXIGP0WSTRB_out; + assign MAXIGP0WVALID = MAXIGP0WVALID_out; + assign MAXIGP1ARADDR = MAXIGP1ARADDR_out; + assign MAXIGP1ARBURST = MAXIGP1ARBURST_out; + assign MAXIGP1ARCACHE = MAXIGP1ARCACHE_out; + assign MAXIGP1ARESETN = MAXIGP1ARESETN_out; + assign MAXIGP1ARID = MAXIGP1ARID_out; + assign MAXIGP1ARLEN = MAXIGP1ARLEN_out; + assign MAXIGP1ARLOCK = MAXIGP1ARLOCK_out; + assign MAXIGP1ARPROT = MAXIGP1ARPROT_out; + assign MAXIGP1ARQOS = MAXIGP1ARQOS_out; + assign MAXIGP1ARSIZE = MAXIGP1ARSIZE_out; + assign MAXIGP1ARVALID = MAXIGP1ARVALID_out; + assign MAXIGP1AWADDR = MAXIGP1AWADDR_out; + assign MAXIGP1AWBURST = MAXIGP1AWBURST_out; + assign MAXIGP1AWCACHE = MAXIGP1AWCACHE_out; + assign MAXIGP1AWID = MAXIGP1AWID_out; + assign MAXIGP1AWLEN = MAXIGP1AWLEN_out; + assign MAXIGP1AWLOCK = MAXIGP1AWLOCK_out; + assign MAXIGP1AWPROT = MAXIGP1AWPROT_out; + assign MAXIGP1AWQOS = MAXIGP1AWQOS_out; + assign MAXIGP1AWSIZE = MAXIGP1AWSIZE_out; + assign MAXIGP1AWVALID = MAXIGP1AWVALID_out; + assign MAXIGP1BREADY = MAXIGP1BREADY_out; + assign MAXIGP1RREADY = MAXIGP1RREADY_out; + assign MAXIGP1WDATA = MAXIGP1WDATA_out; + assign MAXIGP1WID = MAXIGP1WID_out; + assign MAXIGP1WLAST = MAXIGP1WLAST_out; + assign MAXIGP1WSTRB = MAXIGP1WSTRB_out; + assign MAXIGP1WVALID = MAXIGP1WVALID_out; + assign SAXIACPARESETN = SAXIACPARESETN_out; + assign SAXIACPARREADY = SAXIACPARREADY_out; + assign SAXIACPAWREADY = SAXIACPAWREADY_out; + assign SAXIACPBID = SAXIACPBID_out; + assign SAXIACPBRESP = SAXIACPBRESP_out; + assign SAXIACPBVALID = SAXIACPBVALID_out; + assign SAXIACPRDATA = SAXIACPRDATA_out; + assign SAXIACPRID = SAXIACPRID_out; + assign SAXIACPRLAST = SAXIACPRLAST_out; + assign SAXIACPRRESP = SAXIACPRRESP_out; + assign SAXIACPRVALID = SAXIACPRVALID_out; + assign SAXIACPWREADY = SAXIACPWREADY_out; + assign SAXIGP0ARESETN = SAXIGP0ARESETN_out; + assign SAXIGP0ARREADY = SAXIGP0ARREADY_out; + assign SAXIGP0AWREADY = SAXIGP0AWREADY_out; + assign SAXIGP0BID = SAXIGP0BID_out; + assign SAXIGP0BRESP = SAXIGP0BRESP_out; + assign SAXIGP0BVALID = SAXIGP0BVALID_out; + assign SAXIGP0RDATA = SAXIGP0RDATA_out; + assign SAXIGP0RID = SAXIGP0RID_out; + assign SAXIGP0RLAST = SAXIGP0RLAST_out; + assign SAXIGP0RRESP = SAXIGP0RRESP_out; + assign SAXIGP0RVALID = SAXIGP0RVALID_out; + assign SAXIGP0WREADY = SAXIGP0WREADY_out; + assign SAXIGP1ARESETN = SAXIGP1ARESETN_out; + assign SAXIGP1ARREADY = SAXIGP1ARREADY_out; + assign SAXIGP1AWREADY = SAXIGP1AWREADY_out; + assign SAXIGP1BID = SAXIGP1BID_out; + assign SAXIGP1BRESP = SAXIGP1BRESP_out; + assign SAXIGP1BVALID = SAXIGP1BVALID_out; + assign SAXIGP1RDATA = SAXIGP1RDATA_out; + assign SAXIGP1RID = SAXIGP1RID_out; + assign SAXIGP1RLAST = SAXIGP1RLAST_out; + assign SAXIGP1RRESP = SAXIGP1RRESP_out; + assign SAXIGP1RVALID = SAXIGP1RVALID_out; + assign SAXIGP1WREADY = SAXIGP1WREADY_out; + assign SAXIHP0ARESETN = SAXIHP0ARESETN_out; + assign SAXIHP0ARREADY = SAXIHP0ARREADY_out; + assign SAXIHP0AWREADY = SAXIHP0AWREADY_out; + assign SAXIHP0BID = SAXIHP0BID_out; + assign SAXIHP0BRESP = SAXIHP0BRESP_out; + assign SAXIHP0BVALID = SAXIHP0BVALID_out; + assign SAXIHP0RACOUNT = SAXIHP0RACOUNT_out; + assign SAXIHP0RCOUNT = SAXIHP0RCOUNT_out; + assign SAXIHP0RDATA = SAXIHP0RDATA_out; + assign SAXIHP0RID = SAXIHP0RID_out; + assign SAXIHP0RLAST = SAXIHP0RLAST_out; + assign SAXIHP0RRESP = SAXIHP0RRESP_out; + assign SAXIHP0RVALID = SAXIHP0RVALID_out; + assign SAXIHP0WACOUNT = SAXIHP0WACOUNT_out; + assign SAXIHP0WCOUNT = SAXIHP0WCOUNT_out; + assign SAXIHP0WREADY = SAXIHP0WREADY_out; + assign SAXIHP1ARESETN = SAXIHP1ARESETN_out; + assign SAXIHP1ARREADY = SAXIHP1ARREADY_out; + assign SAXIHP1AWREADY = SAXIHP1AWREADY_out; + assign SAXIHP1BID = SAXIHP1BID_out; + assign SAXIHP1BRESP = SAXIHP1BRESP_out; + assign SAXIHP1BVALID = SAXIHP1BVALID_out; + assign SAXIHP1RACOUNT = SAXIHP1RACOUNT_out; + assign SAXIHP1RCOUNT = SAXIHP1RCOUNT_out; + assign SAXIHP1RDATA = SAXIHP1RDATA_out; + assign SAXIHP1RID = SAXIHP1RID_out; + assign SAXIHP1RLAST = SAXIHP1RLAST_out; + assign SAXIHP1RRESP = SAXIHP1RRESP_out; + assign SAXIHP1RVALID = SAXIHP1RVALID_out; + assign SAXIHP1WACOUNT = SAXIHP1WACOUNT_out; + assign SAXIHP1WCOUNT = SAXIHP1WCOUNT_out; + assign SAXIHP1WREADY = SAXIHP1WREADY_out; + assign SAXIHP2ARESETN = SAXIHP2ARESETN_out; + assign SAXIHP2ARREADY = SAXIHP2ARREADY_out; + assign SAXIHP2AWREADY = SAXIHP2AWREADY_out; + assign SAXIHP2BID = SAXIHP2BID_out; + assign SAXIHP2BRESP = SAXIHP2BRESP_out; + assign SAXIHP2BVALID = SAXIHP2BVALID_out; + assign SAXIHP2RACOUNT = SAXIHP2RACOUNT_out; + assign SAXIHP2RCOUNT = SAXIHP2RCOUNT_out; + assign SAXIHP2RDATA = SAXIHP2RDATA_out; + assign SAXIHP2RID = SAXIHP2RID_out; + assign SAXIHP2RLAST = SAXIHP2RLAST_out; + assign SAXIHP2RRESP = SAXIHP2RRESP_out; + assign SAXIHP2RVALID = SAXIHP2RVALID_out; + assign SAXIHP2WACOUNT = SAXIHP2WACOUNT_out; + assign SAXIHP2WCOUNT = SAXIHP2WCOUNT_out; + assign SAXIHP2WREADY = SAXIHP2WREADY_out; + assign SAXIHP3ARESETN = SAXIHP3ARESETN_out; + assign SAXIHP3ARREADY = SAXIHP3ARREADY_out; + assign SAXIHP3AWREADY = SAXIHP3AWREADY_out; + assign SAXIHP3BID = SAXIHP3BID_out; + assign SAXIHP3BRESP = SAXIHP3BRESP_out; + assign SAXIHP3BVALID = SAXIHP3BVALID_out; + assign SAXIHP3RACOUNT = SAXIHP3RACOUNT_out; + assign SAXIHP3RCOUNT = SAXIHP3RCOUNT_out; + assign SAXIHP3RDATA = SAXIHP3RDATA_out; + assign SAXIHP3RID = SAXIHP3RID_out; + assign SAXIHP3RLAST = SAXIHP3RLAST_out; + assign SAXIHP3RRESP = SAXIHP3RRESP_out; + assign SAXIHP3RVALID = SAXIHP3RVALID_out; + assign SAXIHP3WACOUNT = SAXIHP3WACOUNT_out; + assign SAXIHP3WCOUNT = SAXIHP3WCOUNT_out; + assign SAXIHP3WREADY = SAXIHP3WREADY_out; + +`ifdef XIL_TIMING + assign DMA0ACLK_in = (DMA0ACLK !== 1'bz) && DMA0ACLK_delay; // rv 0 + assign DMA0DAREADY_in = (DMA0DAREADY !== 1'bz) && DMA0DAREADY_delay; // rv 0 + assign DMA0DRLAST_in = (DMA0DRLAST !== 1'bz) && DMA0DRLAST_delay; // rv 0 + assign DMA0DRTYPE_in[0] = (DMA0DRTYPE[0] !== 1'bz) && DMA0DRTYPE_delay[0]; // rv 0 + assign DMA0DRTYPE_in[1] = (DMA0DRTYPE[1] !== 1'bz) && DMA0DRTYPE_delay[1]; // rv 0 + assign DMA0DRVALID_in = (DMA0DRVALID !== 1'bz) && DMA0DRVALID_delay; // rv 0 + assign DMA1ACLK_in = (DMA1ACLK !== 1'bz) && DMA1ACLK_delay; // rv 0 + assign DMA1DAREADY_in = (DMA1DAREADY !== 1'bz) && DMA1DAREADY_delay; // rv 0 + assign DMA1DRLAST_in = (DMA1DRLAST !== 1'bz) && DMA1DRLAST_delay; // rv 0 + assign DMA1DRTYPE_in[0] = (DMA1DRTYPE[0] !== 1'bz) && DMA1DRTYPE_delay[0]; // rv 0 + assign DMA1DRTYPE_in[1] = (DMA1DRTYPE[1] !== 1'bz) && DMA1DRTYPE_delay[1]; // rv 0 + assign DMA1DRVALID_in = (DMA1DRVALID !== 1'bz) && DMA1DRVALID_delay; // rv 0 + assign DMA2ACLK_in = (DMA2ACLK !== 1'bz) && DMA2ACLK_delay; // rv 0 + assign DMA2DAREADY_in = (DMA2DAREADY !== 1'bz) && DMA2DAREADY_delay; // rv 0 + assign DMA2DRLAST_in = (DMA2DRLAST !== 1'bz) && DMA2DRLAST_delay; // rv 0 + assign DMA2DRTYPE_in[0] = (DMA2DRTYPE[0] !== 1'bz) && DMA2DRTYPE_delay[0]; // rv 0 + assign DMA2DRTYPE_in[1] = (DMA2DRTYPE[1] !== 1'bz) && DMA2DRTYPE_delay[1]; // rv 0 + assign DMA2DRVALID_in = (DMA2DRVALID !== 1'bz) && DMA2DRVALID_delay; // rv 0 + assign DMA3ACLK_in = (DMA3ACLK !== 1'bz) && DMA3ACLK_delay; // rv 0 + assign DMA3DAREADY_in = (DMA3DAREADY !== 1'bz) && DMA3DAREADY_delay; // rv 0 + assign DMA3DRLAST_in = (DMA3DRLAST !== 1'bz) && DMA3DRLAST_delay; // rv 0 + assign DMA3DRTYPE_in[0] = (DMA3DRTYPE[0] !== 1'bz) && DMA3DRTYPE_delay[0]; // rv 0 + assign DMA3DRTYPE_in[1] = (DMA3DRTYPE[1] !== 1'bz) && DMA3DRTYPE_delay[1]; // rv 0 + assign DMA3DRVALID_in = (DMA3DRVALID !== 1'bz) && DMA3DRVALID_delay; // rv 0 + assign EMIOENET0GMIIRXCLK_in = (EMIOENET0GMIIRXCLK !== 1'bz) && EMIOENET0GMIIRXCLK_delay; // rv 0 + assign EMIOENET0GMIIRXDV_in = (EMIOENET0GMIIRXDV !== 1'bz) && EMIOENET0GMIIRXDV_delay; // rv 0 + assign EMIOENET0GMIIRXD_in[0] = (EMIOENET0GMIIRXD[0] !== 1'bz) && EMIOENET0GMIIRXD_delay[0]; // rv 0 + assign EMIOENET0GMIIRXD_in[1] = (EMIOENET0GMIIRXD[1] !== 1'bz) && EMIOENET0GMIIRXD_delay[1]; // rv 0 + assign EMIOENET0GMIIRXD_in[2] = (EMIOENET0GMIIRXD[2] !== 1'bz) && EMIOENET0GMIIRXD_delay[2]; // rv 0 + assign EMIOENET0GMIIRXD_in[3] = (EMIOENET0GMIIRXD[3] !== 1'bz) && EMIOENET0GMIIRXD_delay[3]; // rv 0 + assign EMIOENET0GMIIRXD_in[4] = (EMIOENET0GMIIRXD[4] !== 1'bz) && EMIOENET0GMIIRXD_delay[4]; // rv 0 + assign EMIOENET0GMIIRXD_in[5] = (EMIOENET0GMIIRXD[5] !== 1'bz) && EMIOENET0GMIIRXD_delay[5]; // rv 0 + assign EMIOENET0GMIIRXD_in[6] = (EMIOENET0GMIIRXD[6] !== 1'bz) && EMIOENET0GMIIRXD_delay[6]; // rv 0 + assign EMIOENET0GMIIRXD_in[7] = (EMIOENET0GMIIRXD[7] !== 1'bz) && EMIOENET0GMIIRXD_delay[7]; // rv 0 + assign EMIOENET0GMIIRXER_in = (EMIOENET0GMIIRXER !== 1'bz) && EMIOENET0GMIIRXER_delay; // rv 0 + assign EMIOENET1GMIIRXCLK_in = (EMIOENET1GMIIRXCLK !== 1'bz) && EMIOENET1GMIIRXCLK_delay; // rv 0 + assign EMIOENET1GMIIRXDV_in = (EMIOENET1GMIIRXDV !== 1'bz) && EMIOENET1GMIIRXDV_delay; // rv 0 + assign EMIOENET1GMIIRXD_in[0] = (EMIOENET1GMIIRXD[0] !== 1'bz) && EMIOENET1GMIIRXD_delay[0]; // rv 0 + assign EMIOENET1GMIIRXD_in[1] = (EMIOENET1GMIIRXD[1] !== 1'bz) && EMIOENET1GMIIRXD_delay[1]; // rv 0 + assign EMIOENET1GMIIRXD_in[2] = (EMIOENET1GMIIRXD[2] !== 1'bz) && EMIOENET1GMIIRXD_delay[2]; // rv 0 + assign EMIOENET1GMIIRXD_in[3] = (EMIOENET1GMIIRXD[3] !== 1'bz) && EMIOENET1GMIIRXD_delay[3]; // rv 0 + assign EMIOENET1GMIIRXD_in[4] = (EMIOENET1GMIIRXD[4] !== 1'bz) && EMIOENET1GMIIRXD_delay[4]; // rv 0 + assign EMIOENET1GMIIRXD_in[5] = (EMIOENET1GMIIRXD[5] !== 1'bz) && EMIOENET1GMIIRXD_delay[5]; // rv 0 + assign EMIOENET1GMIIRXD_in[6] = (EMIOENET1GMIIRXD[6] !== 1'bz) && EMIOENET1GMIIRXD_delay[6]; // rv 0 + assign EMIOENET1GMIIRXD_in[7] = (EMIOENET1GMIIRXD[7] !== 1'bz) && EMIOENET1GMIIRXD_delay[7]; // rv 0 + assign EMIOENET1GMIIRXER_in = (EMIOENET1GMIIRXER !== 1'bz) && EMIOENET1GMIIRXER_delay; // rv 0 + assign EMIOPJTAGTCK_in = (EMIOPJTAGTCK !== 1'bz) && EMIOPJTAGTCK_delay; // rv 0 + assign EMIOPJTAGTDI_in = (EMIOPJTAGTDI !== 1'bz) && EMIOPJTAGTDI_delay; // rv 0 + assign EMIOPJTAGTMS_in = (EMIOPJTAGTMS !== 1'bz) && EMIOPJTAGTMS_delay; // rv 0 + assign EMIOSDIO0CLKFB_in = (EMIOSDIO0CLKFB !== 1'bz) && EMIOSDIO0CLKFB_delay; // rv 0 + assign EMIOSDIO0CMDI_in = (EMIOSDIO0CMDI !== 1'bz) && EMIOSDIO0CMDI_delay; // rv 0 + assign EMIOSDIO0DATAI_in[0] = (EMIOSDIO0DATAI[0] !== 1'bz) && EMIOSDIO0DATAI_delay[0]; // rv 0 + assign EMIOSDIO0DATAI_in[1] = (EMIOSDIO0DATAI[1] !== 1'bz) && EMIOSDIO0DATAI_delay[1]; // rv 0 + assign EMIOSDIO0DATAI_in[2] = (EMIOSDIO0DATAI[2] !== 1'bz) && EMIOSDIO0DATAI_delay[2]; // rv 0 + assign EMIOSDIO0DATAI_in[3] = (EMIOSDIO0DATAI[3] !== 1'bz) && EMIOSDIO0DATAI_delay[3]; // rv 0 + assign EMIOSDIO1CLKFB_in = (EMIOSDIO1CLKFB !== 1'bz) && EMIOSDIO1CLKFB_delay; // rv 0 + assign EMIOSDIO1CMDI_in = (EMIOSDIO1CMDI !== 1'bz) && EMIOSDIO1CMDI_delay; // rv 0 + assign EMIOSDIO1DATAI_in[0] = (EMIOSDIO1DATAI[0] !== 1'bz) && EMIOSDIO1DATAI_delay[0]; // rv 0 + assign EMIOSDIO1DATAI_in[1] = (EMIOSDIO1DATAI[1] !== 1'bz) && EMIOSDIO1DATAI_delay[1]; // rv 0 + assign EMIOSDIO1DATAI_in[2] = (EMIOSDIO1DATAI[2] !== 1'bz) && EMIOSDIO1DATAI_delay[2]; // rv 0 + assign EMIOSDIO1DATAI_in[3] = (EMIOSDIO1DATAI[3] !== 1'bz) && EMIOSDIO1DATAI_delay[3]; // rv 0 + assign FTMDTRACEINATID_in[0] = (FTMDTRACEINATID[0] !== 1'bz) && FTMDTRACEINATID_delay[0]; // rv 0 + assign FTMDTRACEINATID_in[1] = (FTMDTRACEINATID[1] !== 1'bz) && FTMDTRACEINATID_delay[1]; // rv 0 + assign FTMDTRACEINATID_in[2] = (FTMDTRACEINATID[2] !== 1'bz) && FTMDTRACEINATID_delay[2]; // rv 0 + assign FTMDTRACEINATID_in[3] = (FTMDTRACEINATID[3] !== 1'bz) && FTMDTRACEINATID_delay[3]; // rv 0 + assign FTMDTRACEINCLOCK_in = (FTMDTRACEINCLOCK !== 1'bz) && FTMDTRACEINCLOCK_delay; // rv 0 + assign FTMDTRACEINDATA_in[0] = (FTMDTRACEINDATA[0] !== 1'bz) && FTMDTRACEINDATA_delay[0]; // rv 0 + assign FTMDTRACEINDATA_in[10] = (FTMDTRACEINDATA[10] !== 1'bz) && FTMDTRACEINDATA_delay[10]; // rv 0 + assign FTMDTRACEINDATA_in[11] = (FTMDTRACEINDATA[11] !== 1'bz) && FTMDTRACEINDATA_delay[11]; // rv 0 + assign FTMDTRACEINDATA_in[12] = (FTMDTRACEINDATA[12] !== 1'bz) && FTMDTRACEINDATA_delay[12]; // rv 0 + assign FTMDTRACEINDATA_in[13] = (FTMDTRACEINDATA[13] !== 1'bz) && FTMDTRACEINDATA_delay[13]; // rv 0 + assign FTMDTRACEINDATA_in[14] = (FTMDTRACEINDATA[14] !== 1'bz) && FTMDTRACEINDATA_delay[14]; // rv 0 + assign FTMDTRACEINDATA_in[15] = (FTMDTRACEINDATA[15] !== 1'bz) && FTMDTRACEINDATA_delay[15]; // rv 0 + assign FTMDTRACEINDATA_in[16] = (FTMDTRACEINDATA[16] !== 1'bz) && FTMDTRACEINDATA_delay[16]; // rv 0 + assign FTMDTRACEINDATA_in[17] = (FTMDTRACEINDATA[17] !== 1'bz) && FTMDTRACEINDATA_delay[17]; // rv 0 + assign FTMDTRACEINDATA_in[18] = (FTMDTRACEINDATA[18] !== 1'bz) && FTMDTRACEINDATA_delay[18]; // rv 0 + assign FTMDTRACEINDATA_in[19] = (FTMDTRACEINDATA[19] !== 1'bz) && FTMDTRACEINDATA_delay[19]; // rv 0 + assign FTMDTRACEINDATA_in[1] = (FTMDTRACEINDATA[1] !== 1'bz) && FTMDTRACEINDATA_delay[1]; // rv 0 + assign FTMDTRACEINDATA_in[20] = (FTMDTRACEINDATA[20] !== 1'bz) && FTMDTRACEINDATA_delay[20]; // rv 0 + assign FTMDTRACEINDATA_in[21] = (FTMDTRACEINDATA[21] !== 1'bz) && FTMDTRACEINDATA_delay[21]; // rv 0 + assign FTMDTRACEINDATA_in[22] = (FTMDTRACEINDATA[22] !== 1'bz) && FTMDTRACEINDATA_delay[22]; // rv 0 + assign FTMDTRACEINDATA_in[23] = (FTMDTRACEINDATA[23] !== 1'bz) && FTMDTRACEINDATA_delay[23]; // rv 0 + assign FTMDTRACEINDATA_in[24] = (FTMDTRACEINDATA[24] !== 1'bz) && FTMDTRACEINDATA_delay[24]; // rv 0 + assign FTMDTRACEINDATA_in[25] = (FTMDTRACEINDATA[25] !== 1'bz) && FTMDTRACEINDATA_delay[25]; // rv 0 + assign FTMDTRACEINDATA_in[26] = (FTMDTRACEINDATA[26] !== 1'bz) && FTMDTRACEINDATA_delay[26]; // rv 0 + assign FTMDTRACEINDATA_in[27] = (FTMDTRACEINDATA[27] !== 1'bz) && FTMDTRACEINDATA_delay[27]; // rv 0 + assign FTMDTRACEINDATA_in[28] = (FTMDTRACEINDATA[28] !== 1'bz) && FTMDTRACEINDATA_delay[28]; // rv 0 + assign FTMDTRACEINDATA_in[29] = (FTMDTRACEINDATA[29] !== 1'bz) && FTMDTRACEINDATA_delay[29]; // rv 0 + assign FTMDTRACEINDATA_in[2] = (FTMDTRACEINDATA[2] !== 1'bz) && FTMDTRACEINDATA_delay[2]; // rv 0 + assign FTMDTRACEINDATA_in[30] = (FTMDTRACEINDATA[30] !== 1'bz) && FTMDTRACEINDATA_delay[30]; // rv 0 + assign FTMDTRACEINDATA_in[31] = (FTMDTRACEINDATA[31] !== 1'bz) && FTMDTRACEINDATA_delay[31]; // rv 0 + assign FTMDTRACEINDATA_in[3] = (FTMDTRACEINDATA[3] !== 1'bz) && FTMDTRACEINDATA_delay[3]; // rv 0 + assign FTMDTRACEINDATA_in[4] = (FTMDTRACEINDATA[4] !== 1'bz) && FTMDTRACEINDATA_delay[4]; // rv 0 + assign FTMDTRACEINDATA_in[5] = (FTMDTRACEINDATA[5] !== 1'bz) && FTMDTRACEINDATA_delay[5]; // rv 0 + assign FTMDTRACEINDATA_in[6] = (FTMDTRACEINDATA[6] !== 1'bz) && FTMDTRACEINDATA_delay[6]; // rv 0 + assign FTMDTRACEINDATA_in[7] = (FTMDTRACEINDATA[7] !== 1'bz) && FTMDTRACEINDATA_delay[7]; // rv 0 + assign FTMDTRACEINDATA_in[8] = (FTMDTRACEINDATA[8] !== 1'bz) && FTMDTRACEINDATA_delay[8]; // rv 0 + assign FTMDTRACEINDATA_in[9] = (FTMDTRACEINDATA[9] !== 1'bz) && FTMDTRACEINDATA_delay[9]; // rv 0 + assign FTMDTRACEINVALID_in = (FTMDTRACEINVALID !== 1'bz) && FTMDTRACEINVALID_delay; // rv 0 + assign MAXIGP0ACLK_in = (MAXIGP0ACLK !== 1'bz) && MAXIGP0ACLK_delay; // rv 0 + assign MAXIGP0ARREADY_in = (MAXIGP0ARREADY !== 1'bz) && MAXIGP0ARREADY_delay; // rv 0 + assign MAXIGP0AWREADY_in = (MAXIGP0AWREADY !== 1'bz) && MAXIGP0AWREADY_delay; // rv 0 + assign MAXIGP0BID_in[0] = (MAXIGP0BID[0] !== 1'bz) && MAXIGP0BID_delay[0]; // rv 0 + assign MAXIGP0BID_in[10] = (MAXIGP0BID[10] !== 1'bz) && MAXIGP0BID_delay[10]; // rv 0 + assign MAXIGP0BID_in[11] = (MAXIGP0BID[11] !== 1'bz) && MAXIGP0BID_delay[11]; // rv 0 + assign MAXIGP0BID_in[1] = (MAXIGP0BID[1] !== 1'bz) && MAXIGP0BID_delay[1]; // rv 0 + assign MAXIGP0BID_in[2] = (MAXIGP0BID[2] !== 1'bz) && MAXIGP0BID_delay[2]; // rv 0 + assign MAXIGP0BID_in[3] = (MAXIGP0BID[3] !== 1'bz) && MAXIGP0BID_delay[3]; // rv 0 + assign MAXIGP0BID_in[4] = (MAXIGP0BID[4] !== 1'bz) && MAXIGP0BID_delay[4]; // rv 0 + assign MAXIGP0BID_in[5] = (MAXIGP0BID[5] !== 1'bz) && MAXIGP0BID_delay[5]; // rv 0 + assign MAXIGP0BID_in[6] = (MAXIGP0BID[6] !== 1'bz) && MAXIGP0BID_delay[6]; // rv 0 + assign MAXIGP0BID_in[7] = (MAXIGP0BID[7] !== 1'bz) && MAXIGP0BID_delay[7]; // rv 0 + assign MAXIGP0BID_in[8] = (MAXIGP0BID[8] !== 1'bz) && MAXIGP0BID_delay[8]; // rv 0 + assign MAXIGP0BID_in[9] = (MAXIGP0BID[9] !== 1'bz) && MAXIGP0BID_delay[9]; // rv 0 + assign MAXIGP0BRESP_in[0] = (MAXIGP0BRESP[0] !== 1'bz) && MAXIGP0BRESP_delay[0]; // rv 0 + assign MAXIGP0BRESP_in[1] = (MAXIGP0BRESP[1] !== 1'bz) && MAXIGP0BRESP_delay[1]; // rv 0 + assign MAXIGP0BVALID_in = (MAXIGP0BVALID !== 1'bz) && MAXIGP0BVALID_delay; // rv 0 + assign MAXIGP0RDATA_in[0] = (MAXIGP0RDATA[0] !== 1'bz) && MAXIGP0RDATA_delay[0]; // rv 0 + assign MAXIGP0RDATA_in[10] = (MAXIGP0RDATA[10] !== 1'bz) && MAXIGP0RDATA_delay[10]; // rv 0 + assign MAXIGP0RDATA_in[11] = (MAXIGP0RDATA[11] !== 1'bz) && MAXIGP0RDATA_delay[11]; // rv 0 + assign MAXIGP0RDATA_in[12] = (MAXIGP0RDATA[12] !== 1'bz) && MAXIGP0RDATA_delay[12]; // rv 0 + assign MAXIGP0RDATA_in[13] = (MAXIGP0RDATA[13] !== 1'bz) && MAXIGP0RDATA_delay[13]; // rv 0 + assign MAXIGP0RDATA_in[14] = (MAXIGP0RDATA[14] !== 1'bz) && MAXIGP0RDATA_delay[14]; // rv 0 + assign MAXIGP0RDATA_in[15] = (MAXIGP0RDATA[15] !== 1'bz) && MAXIGP0RDATA_delay[15]; // rv 0 + assign MAXIGP0RDATA_in[16] = (MAXIGP0RDATA[16] !== 1'bz) && MAXIGP0RDATA_delay[16]; // rv 0 + assign MAXIGP0RDATA_in[17] = (MAXIGP0RDATA[17] !== 1'bz) && MAXIGP0RDATA_delay[17]; // rv 0 + assign MAXIGP0RDATA_in[18] = (MAXIGP0RDATA[18] !== 1'bz) && MAXIGP0RDATA_delay[18]; // rv 0 + assign MAXIGP0RDATA_in[19] = (MAXIGP0RDATA[19] !== 1'bz) && MAXIGP0RDATA_delay[19]; // rv 0 + assign MAXIGP0RDATA_in[1] = (MAXIGP0RDATA[1] !== 1'bz) && MAXIGP0RDATA_delay[1]; // rv 0 + assign MAXIGP0RDATA_in[20] = (MAXIGP0RDATA[20] !== 1'bz) && MAXIGP0RDATA_delay[20]; // rv 0 + assign MAXIGP0RDATA_in[21] = (MAXIGP0RDATA[21] !== 1'bz) && MAXIGP0RDATA_delay[21]; // rv 0 + assign MAXIGP0RDATA_in[22] = (MAXIGP0RDATA[22] !== 1'bz) && MAXIGP0RDATA_delay[22]; // rv 0 + assign MAXIGP0RDATA_in[23] = (MAXIGP0RDATA[23] !== 1'bz) && MAXIGP0RDATA_delay[23]; // rv 0 + assign MAXIGP0RDATA_in[24] = (MAXIGP0RDATA[24] !== 1'bz) && MAXIGP0RDATA_delay[24]; // rv 0 + assign MAXIGP0RDATA_in[25] = (MAXIGP0RDATA[25] !== 1'bz) && MAXIGP0RDATA_delay[25]; // rv 0 + assign MAXIGP0RDATA_in[26] = (MAXIGP0RDATA[26] !== 1'bz) && MAXIGP0RDATA_delay[26]; // rv 0 + assign MAXIGP0RDATA_in[27] = (MAXIGP0RDATA[27] !== 1'bz) && MAXIGP0RDATA_delay[27]; // rv 0 + assign MAXIGP0RDATA_in[28] = (MAXIGP0RDATA[28] !== 1'bz) && MAXIGP0RDATA_delay[28]; // rv 0 + assign MAXIGP0RDATA_in[29] = (MAXIGP0RDATA[29] !== 1'bz) && MAXIGP0RDATA_delay[29]; // rv 0 + assign MAXIGP0RDATA_in[2] = (MAXIGP0RDATA[2] !== 1'bz) && MAXIGP0RDATA_delay[2]; // rv 0 + assign MAXIGP0RDATA_in[30] = (MAXIGP0RDATA[30] !== 1'bz) && MAXIGP0RDATA_delay[30]; // rv 0 + assign MAXIGP0RDATA_in[31] = (MAXIGP0RDATA[31] !== 1'bz) && MAXIGP0RDATA_delay[31]; // rv 0 + assign MAXIGP0RDATA_in[3] = (MAXIGP0RDATA[3] !== 1'bz) && MAXIGP0RDATA_delay[3]; // rv 0 + assign MAXIGP0RDATA_in[4] = (MAXIGP0RDATA[4] !== 1'bz) && MAXIGP0RDATA_delay[4]; // rv 0 + assign MAXIGP0RDATA_in[5] = (MAXIGP0RDATA[5] !== 1'bz) && MAXIGP0RDATA_delay[5]; // rv 0 + assign MAXIGP0RDATA_in[6] = (MAXIGP0RDATA[6] !== 1'bz) && MAXIGP0RDATA_delay[6]; // rv 0 + assign MAXIGP0RDATA_in[7] = (MAXIGP0RDATA[7] !== 1'bz) && MAXIGP0RDATA_delay[7]; // rv 0 + assign MAXIGP0RDATA_in[8] = (MAXIGP0RDATA[8] !== 1'bz) && MAXIGP0RDATA_delay[8]; // rv 0 + assign MAXIGP0RDATA_in[9] = (MAXIGP0RDATA[9] !== 1'bz) && MAXIGP0RDATA_delay[9]; // rv 0 + assign MAXIGP0RID_in[0] = (MAXIGP0RID[0] !== 1'bz) && MAXIGP0RID_delay[0]; // rv 0 + assign MAXIGP0RID_in[10] = (MAXIGP0RID[10] !== 1'bz) && MAXIGP0RID_delay[10]; // rv 0 + assign MAXIGP0RID_in[11] = (MAXIGP0RID[11] !== 1'bz) && MAXIGP0RID_delay[11]; // rv 0 + assign MAXIGP0RID_in[1] = (MAXIGP0RID[1] !== 1'bz) && MAXIGP0RID_delay[1]; // rv 0 + assign MAXIGP0RID_in[2] = (MAXIGP0RID[2] !== 1'bz) && MAXIGP0RID_delay[2]; // rv 0 + assign MAXIGP0RID_in[3] = (MAXIGP0RID[3] !== 1'bz) && MAXIGP0RID_delay[3]; // rv 0 + assign MAXIGP0RID_in[4] = (MAXIGP0RID[4] !== 1'bz) && MAXIGP0RID_delay[4]; // rv 0 + assign MAXIGP0RID_in[5] = (MAXIGP0RID[5] !== 1'bz) && MAXIGP0RID_delay[5]; // rv 0 + assign MAXIGP0RID_in[6] = (MAXIGP0RID[6] !== 1'bz) && MAXIGP0RID_delay[6]; // rv 0 + assign MAXIGP0RID_in[7] = (MAXIGP0RID[7] !== 1'bz) && MAXIGP0RID_delay[7]; // rv 0 + assign MAXIGP0RID_in[8] = (MAXIGP0RID[8] !== 1'bz) && MAXIGP0RID_delay[8]; // rv 0 + assign MAXIGP0RID_in[9] = (MAXIGP0RID[9] !== 1'bz) && MAXIGP0RID_delay[9]; // rv 0 + assign MAXIGP0RLAST_in = (MAXIGP0RLAST !== 1'bz) && MAXIGP0RLAST_delay; // rv 0 + assign MAXIGP0RRESP_in[0] = (MAXIGP0RRESP[0] !== 1'bz) && MAXIGP0RRESP_delay[0]; // rv 0 + assign MAXIGP0RRESP_in[1] = (MAXIGP0RRESP[1] !== 1'bz) && MAXIGP0RRESP_delay[1]; // rv 0 + assign MAXIGP0RVALID_in = (MAXIGP0RVALID !== 1'bz) && MAXIGP0RVALID_delay; // rv 0 + assign MAXIGP0WREADY_in = (MAXIGP0WREADY !== 1'bz) && MAXIGP0WREADY_delay; // rv 0 + assign MAXIGP1ACLK_in = (MAXIGP1ACLK !== 1'bz) && MAXIGP1ACLK_delay; // rv 0 + assign MAXIGP1ARREADY_in = (MAXIGP1ARREADY !== 1'bz) && MAXIGP1ARREADY_delay; // rv 0 + assign MAXIGP1AWREADY_in = (MAXIGP1AWREADY !== 1'bz) && MAXIGP1AWREADY_delay; // rv 0 + assign MAXIGP1BID_in[0] = (MAXIGP1BID[0] !== 1'bz) && MAXIGP1BID_delay[0]; // rv 0 + assign MAXIGP1BID_in[10] = (MAXIGP1BID[10] !== 1'bz) && MAXIGP1BID_delay[10]; // rv 0 + assign MAXIGP1BID_in[11] = (MAXIGP1BID[11] !== 1'bz) && MAXIGP1BID_delay[11]; // rv 0 + assign MAXIGP1BID_in[1] = (MAXIGP1BID[1] !== 1'bz) && MAXIGP1BID_delay[1]; // rv 0 + assign MAXIGP1BID_in[2] = (MAXIGP1BID[2] !== 1'bz) && MAXIGP1BID_delay[2]; // rv 0 + assign MAXIGP1BID_in[3] = (MAXIGP1BID[3] !== 1'bz) && MAXIGP1BID_delay[3]; // rv 0 + assign MAXIGP1BID_in[4] = (MAXIGP1BID[4] !== 1'bz) && MAXIGP1BID_delay[4]; // rv 0 + assign MAXIGP1BID_in[5] = (MAXIGP1BID[5] !== 1'bz) && MAXIGP1BID_delay[5]; // rv 0 + assign MAXIGP1BID_in[6] = (MAXIGP1BID[6] !== 1'bz) && MAXIGP1BID_delay[6]; // rv 0 + assign MAXIGP1BID_in[7] = (MAXIGP1BID[7] !== 1'bz) && MAXIGP1BID_delay[7]; // rv 0 + assign MAXIGP1BID_in[8] = (MAXIGP1BID[8] !== 1'bz) && MAXIGP1BID_delay[8]; // rv 0 + assign MAXIGP1BID_in[9] = (MAXIGP1BID[9] !== 1'bz) && MAXIGP1BID_delay[9]; // rv 0 + assign MAXIGP1BRESP_in[0] = (MAXIGP1BRESP[0] !== 1'bz) && MAXIGP1BRESP_delay[0]; // rv 0 + assign MAXIGP1BRESP_in[1] = (MAXIGP1BRESP[1] !== 1'bz) && MAXIGP1BRESP_delay[1]; // rv 0 + assign MAXIGP1BVALID_in = (MAXIGP1BVALID !== 1'bz) && MAXIGP1BVALID_delay; // rv 0 + assign MAXIGP1RDATA_in[0] = (MAXIGP1RDATA[0] !== 1'bz) && MAXIGP1RDATA_delay[0]; // rv 0 + assign MAXIGP1RDATA_in[10] = (MAXIGP1RDATA[10] !== 1'bz) && MAXIGP1RDATA_delay[10]; // rv 0 + assign MAXIGP1RDATA_in[11] = (MAXIGP1RDATA[11] !== 1'bz) && MAXIGP1RDATA_delay[11]; // rv 0 + assign MAXIGP1RDATA_in[12] = (MAXIGP1RDATA[12] !== 1'bz) && MAXIGP1RDATA_delay[12]; // rv 0 + assign MAXIGP1RDATA_in[13] = (MAXIGP1RDATA[13] !== 1'bz) && MAXIGP1RDATA_delay[13]; // rv 0 + assign MAXIGP1RDATA_in[14] = (MAXIGP1RDATA[14] !== 1'bz) && MAXIGP1RDATA_delay[14]; // rv 0 + assign MAXIGP1RDATA_in[15] = (MAXIGP1RDATA[15] !== 1'bz) && MAXIGP1RDATA_delay[15]; // rv 0 + assign MAXIGP1RDATA_in[16] = (MAXIGP1RDATA[16] !== 1'bz) && MAXIGP1RDATA_delay[16]; // rv 0 + assign MAXIGP1RDATA_in[17] = (MAXIGP1RDATA[17] !== 1'bz) && MAXIGP1RDATA_delay[17]; // rv 0 + assign MAXIGP1RDATA_in[18] = (MAXIGP1RDATA[18] !== 1'bz) && MAXIGP1RDATA_delay[18]; // rv 0 + assign MAXIGP1RDATA_in[19] = (MAXIGP1RDATA[19] !== 1'bz) && MAXIGP1RDATA_delay[19]; // rv 0 + assign MAXIGP1RDATA_in[1] = (MAXIGP1RDATA[1] !== 1'bz) && MAXIGP1RDATA_delay[1]; // rv 0 + assign MAXIGP1RDATA_in[20] = (MAXIGP1RDATA[20] !== 1'bz) && MAXIGP1RDATA_delay[20]; // rv 0 + assign MAXIGP1RDATA_in[21] = (MAXIGP1RDATA[21] !== 1'bz) && MAXIGP1RDATA_delay[21]; // rv 0 + assign MAXIGP1RDATA_in[22] = (MAXIGP1RDATA[22] !== 1'bz) && MAXIGP1RDATA_delay[22]; // rv 0 + assign MAXIGP1RDATA_in[23] = (MAXIGP1RDATA[23] !== 1'bz) && MAXIGP1RDATA_delay[23]; // rv 0 + assign MAXIGP1RDATA_in[24] = (MAXIGP1RDATA[24] !== 1'bz) && MAXIGP1RDATA_delay[24]; // rv 0 + assign MAXIGP1RDATA_in[25] = (MAXIGP1RDATA[25] !== 1'bz) && MAXIGP1RDATA_delay[25]; // rv 0 + assign MAXIGP1RDATA_in[26] = (MAXIGP1RDATA[26] !== 1'bz) && MAXIGP1RDATA_delay[26]; // rv 0 + assign MAXIGP1RDATA_in[27] = (MAXIGP1RDATA[27] !== 1'bz) && MAXIGP1RDATA_delay[27]; // rv 0 + assign MAXIGP1RDATA_in[28] = (MAXIGP1RDATA[28] !== 1'bz) && MAXIGP1RDATA_delay[28]; // rv 0 + assign MAXIGP1RDATA_in[29] = (MAXIGP1RDATA[29] !== 1'bz) && MAXIGP1RDATA_delay[29]; // rv 0 + assign MAXIGP1RDATA_in[2] = (MAXIGP1RDATA[2] !== 1'bz) && MAXIGP1RDATA_delay[2]; // rv 0 + assign MAXIGP1RDATA_in[30] = (MAXIGP1RDATA[30] !== 1'bz) && MAXIGP1RDATA_delay[30]; // rv 0 + assign MAXIGP1RDATA_in[31] = (MAXIGP1RDATA[31] !== 1'bz) && MAXIGP1RDATA_delay[31]; // rv 0 + assign MAXIGP1RDATA_in[3] = (MAXIGP1RDATA[3] !== 1'bz) && MAXIGP1RDATA_delay[3]; // rv 0 + assign MAXIGP1RDATA_in[4] = (MAXIGP1RDATA[4] !== 1'bz) && MAXIGP1RDATA_delay[4]; // rv 0 + assign MAXIGP1RDATA_in[5] = (MAXIGP1RDATA[5] !== 1'bz) && MAXIGP1RDATA_delay[5]; // rv 0 + assign MAXIGP1RDATA_in[6] = (MAXIGP1RDATA[6] !== 1'bz) && MAXIGP1RDATA_delay[6]; // rv 0 + assign MAXIGP1RDATA_in[7] = (MAXIGP1RDATA[7] !== 1'bz) && MAXIGP1RDATA_delay[7]; // rv 0 + assign MAXIGP1RDATA_in[8] = (MAXIGP1RDATA[8] !== 1'bz) && MAXIGP1RDATA_delay[8]; // rv 0 + assign MAXIGP1RDATA_in[9] = (MAXIGP1RDATA[9] !== 1'bz) && MAXIGP1RDATA_delay[9]; // rv 0 + assign MAXIGP1RID_in[0] = (MAXIGP1RID[0] !== 1'bz) && MAXIGP1RID_delay[0]; // rv 0 + assign MAXIGP1RID_in[10] = (MAXIGP1RID[10] !== 1'bz) && MAXIGP1RID_delay[10]; // rv 0 + assign MAXIGP1RID_in[11] = (MAXIGP1RID[11] !== 1'bz) && MAXIGP1RID_delay[11]; // rv 0 + assign MAXIGP1RID_in[1] = (MAXIGP1RID[1] !== 1'bz) && MAXIGP1RID_delay[1]; // rv 0 + assign MAXIGP1RID_in[2] = (MAXIGP1RID[2] !== 1'bz) && MAXIGP1RID_delay[2]; // rv 0 + assign MAXIGP1RID_in[3] = (MAXIGP1RID[3] !== 1'bz) && MAXIGP1RID_delay[3]; // rv 0 + assign MAXIGP1RID_in[4] = (MAXIGP1RID[4] !== 1'bz) && MAXIGP1RID_delay[4]; // rv 0 + assign MAXIGP1RID_in[5] = (MAXIGP1RID[5] !== 1'bz) && MAXIGP1RID_delay[5]; // rv 0 + assign MAXIGP1RID_in[6] = (MAXIGP1RID[6] !== 1'bz) && MAXIGP1RID_delay[6]; // rv 0 + assign MAXIGP1RID_in[7] = (MAXIGP1RID[7] !== 1'bz) && MAXIGP1RID_delay[7]; // rv 0 + assign MAXIGP1RID_in[8] = (MAXIGP1RID[8] !== 1'bz) && MAXIGP1RID_delay[8]; // rv 0 + assign MAXIGP1RID_in[9] = (MAXIGP1RID[9] !== 1'bz) && MAXIGP1RID_delay[9]; // rv 0 + assign MAXIGP1RLAST_in = (MAXIGP1RLAST !== 1'bz) && MAXIGP1RLAST_delay; // rv 0 + assign MAXIGP1RRESP_in[0] = (MAXIGP1RRESP[0] !== 1'bz) && MAXIGP1RRESP_delay[0]; // rv 0 + assign MAXIGP1RRESP_in[1] = (MAXIGP1RRESP[1] !== 1'bz) && MAXIGP1RRESP_delay[1]; // rv 0 + assign MAXIGP1RVALID_in = (MAXIGP1RVALID !== 1'bz) && MAXIGP1RVALID_delay; // rv 0 + assign MAXIGP1WREADY_in = (MAXIGP1WREADY !== 1'bz) && MAXIGP1WREADY_delay; // rv 0 + assign SAXIACPACLK_in = (SAXIACPACLK !== 1'bz) && SAXIACPACLK_delay; // rv 0 + assign SAXIACPARADDR_in[0] = (SAXIACPARADDR[0] !== 1'bz) && SAXIACPARADDR_delay[0]; // rv 0 + assign SAXIACPARADDR_in[10] = (SAXIACPARADDR[10] !== 1'bz) && SAXIACPARADDR_delay[10]; // rv 0 + assign SAXIACPARADDR_in[11] = (SAXIACPARADDR[11] !== 1'bz) && SAXIACPARADDR_delay[11]; // rv 0 + assign SAXIACPARADDR_in[12] = (SAXIACPARADDR[12] !== 1'bz) && SAXIACPARADDR_delay[12]; // rv 0 + assign SAXIACPARADDR_in[13] = (SAXIACPARADDR[13] !== 1'bz) && SAXIACPARADDR_delay[13]; // rv 0 + assign SAXIACPARADDR_in[14] = (SAXIACPARADDR[14] !== 1'bz) && SAXIACPARADDR_delay[14]; // rv 0 + assign SAXIACPARADDR_in[15] = (SAXIACPARADDR[15] !== 1'bz) && SAXIACPARADDR_delay[15]; // rv 0 + assign SAXIACPARADDR_in[16] = (SAXIACPARADDR[16] !== 1'bz) && SAXIACPARADDR_delay[16]; // rv 0 + assign SAXIACPARADDR_in[17] = (SAXIACPARADDR[17] !== 1'bz) && SAXIACPARADDR_delay[17]; // rv 0 + assign SAXIACPARADDR_in[18] = (SAXIACPARADDR[18] !== 1'bz) && SAXIACPARADDR_delay[18]; // rv 0 + assign SAXIACPARADDR_in[19] = (SAXIACPARADDR[19] !== 1'bz) && SAXIACPARADDR_delay[19]; // rv 0 + assign SAXIACPARADDR_in[1] = (SAXIACPARADDR[1] !== 1'bz) && SAXIACPARADDR_delay[1]; // rv 0 + assign SAXIACPARADDR_in[20] = (SAXIACPARADDR[20] !== 1'bz) && SAXIACPARADDR_delay[20]; // rv 0 + assign SAXIACPARADDR_in[21] = (SAXIACPARADDR[21] !== 1'bz) && SAXIACPARADDR_delay[21]; // rv 0 + assign SAXIACPARADDR_in[22] = (SAXIACPARADDR[22] !== 1'bz) && SAXIACPARADDR_delay[22]; // rv 0 + assign SAXIACPARADDR_in[23] = (SAXIACPARADDR[23] !== 1'bz) && SAXIACPARADDR_delay[23]; // rv 0 + assign SAXIACPARADDR_in[24] = (SAXIACPARADDR[24] !== 1'bz) && SAXIACPARADDR_delay[24]; // rv 0 + assign SAXIACPARADDR_in[25] = (SAXIACPARADDR[25] !== 1'bz) && SAXIACPARADDR_delay[25]; // rv 0 + assign SAXIACPARADDR_in[26] = (SAXIACPARADDR[26] !== 1'bz) && SAXIACPARADDR_delay[26]; // rv 0 + assign SAXIACPARADDR_in[27] = (SAXIACPARADDR[27] !== 1'bz) && SAXIACPARADDR_delay[27]; // rv 0 + assign SAXIACPARADDR_in[28] = (SAXIACPARADDR[28] !== 1'bz) && SAXIACPARADDR_delay[28]; // rv 0 + assign SAXIACPARADDR_in[29] = (SAXIACPARADDR[29] !== 1'bz) && SAXIACPARADDR_delay[29]; // rv 0 + assign SAXIACPARADDR_in[2] = (SAXIACPARADDR[2] !== 1'bz) && SAXIACPARADDR_delay[2]; // rv 0 + assign SAXIACPARADDR_in[30] = (SAXIACPARADDR[30] !== 1'bz) && SAXIACPARADDR_delay[30]; // rv 0 + assign SAXIACPARADDR_in[31] = (SAXIACPARADDR[31] !== 1'bz) && SAXIACPARADDR_delay[31]; // rv 0 + assign SAXIACPARADDR_in[3] = (SAXIACPARADDR[3] !== 1'bz) && SAXIACPARADDR_delay[3]; // rv 0 + assign SAXIACPARADDR_in[4] = (SAXIACPARADDR[4] !== 1'bz) && SAXIACPARADDR_delay[4]; // rv 0 + assign SAXIACPARADDR_in[5] = (SAXIACPARADDR[5] !== 1'bz) && SAXIACPARADDR_delay[5]; // rv 0 + assign SAXIACPARADDR_in[6] = (SAXIACPARADDR[6] !== 1'bz) && SAXIACPARADDR_delay[6]; // rv 0 + assign SAXIACPARADDR_in[7] = (SAXIACPARADDR[7] !== 1'bz) && SAXIACPARADDR_delay[7]; // rv 0 + assign SAXIACPARADDR_in[8] = (SAXIACPARADDR[8] !== 1'bz) && SAXIACPARADDR_delay[8]; // rv 0 + assign SAXIACPARADDR_in[9] = (SAXIACPARADDR[9] !== 1'bz) && SAXIACPARADDR_delay[9]; // rv 0 + assign SAXIACPARBURST_in[0] = (SAXIACPARBURST[0] !== 1'bz) && SAXIACPARBURST_delay[0]; // rv 0 + assign SAXIACPARBURST_in[1] = (SAXIACPARBURST[1] !== 1'bz) && SAXIACPARBURST_delay[1]; // rv 0 + assign SAXIACPARCACHE_in[0] = (SAXIACPARCACHE[0] !== 1'bz) && SAXIACPARCACHE_delay[0]; // rv 0 + assign SAXIACPARCACHE_in[1] = (SAXIACPARCACHE[1] !== 1'bz) && SAXIACPARCACHE_delay[1]; // rv 0 + assign SAXIACPARCACHE_in[2] = (SAXIACPARCACHE[2] !== 1'bz) && SAXIACPARCACHE_delay[2]; // rv 0 + assign SAXIACPARCACHE_in[3] = (SAXIACPARCACHE[3] !== 1'bz) && SAXIACPARCACHE_delay[3]; // rv 0 + assign SAXIACPARID_in[0] = (SAXIACPARID[0] !== 1'bz) && SAXIACPARID_delay[0]; // rv 0 + assign SAXIACPARID_in[1] = (SAXIACPARID[1] !== 1'bz) && SAXIACPARID_delay[1]; // rv 0 + assign SAXIACPARID_in[2] = (SAXIACPARID[2] !== 1'bz) && SAXIACPARID_delay[2]; // rv 0 + assign SAXIACPARLEN_in[0] = (SAXIACPARLEN[0] !== 1'bz) && SAXIACPARLEN_delay[0]; // rv 0 + assign SAXIACPARLEN_in[1] = (SAXIACPARLEN[1] !== 1'bz) && SAXIACPARLEN_delay[1]; // rv 0 + assign SAXIACPARLEN_in[2] = (SAXIACPARLEN[2] !== 1'bz) && SAXIACPARLEN_delay[2]; // rv 0 + assign SAXIACPARLEN_in[3] = (SAXIACPARLEN[3] !== 1'bz) && SAXIACPARLEN_delay[3]; // rv 0 + assign SAXIACPARLOCK_in[0] = (SAXIACPARLOCK[0] !== 1'bz) && SAXIACPARLOCK_delay[0]; // rv 0 + assign SAXIACPARLOCK_in[1] = (SAXIACPARLOCK[1] !== 1'bz) && SAXIACPARLOCK_delay[1]; // rv 0 + assign SAXIACPARPROT_in[0] = (SAXIACPARPROT[0] !== 1'bz) && SAXIACPARPROT_delay[0]; // rv 0 + assign SAXIACPARPROT_in[1] = (SAXIACPARPROT[1] !== 1'bz) && SAXIACPARPROT_delay[1]; // rv 0 + assign SAXIACPARPROT_in[2] = (SAXIACPARPROT[2] !== 1'bz) && SAXIACPARPROT_delay[2]; // rv 0 + assign SAXIACPARSIZE_in[0] = (SAXIACPARSIZE[0] !== 1'bz) && SAXIACPARSIZE_delay[0]; // rv 0 + assign SAXIACPARSIZE_in[1] = (SAXIACPARSIZE[1] !== 1'bz) && SAXIACPARSIZE_delay[1]; // rv 0 + assign SAXIACPARUSER_in[0] = (SAXIACPARUSER[0] !== 1'bz) && SAXIACPARUSER_delay[0]; // rv 0 + assign SAXIACPARUSER_in[1] = (SAXIACPARUSER[1] !== 1'bz) && SAXIACPARUSER_delay[1]; // rv 0 + assign SAXIACPARUSER_in[2] = (SAXIACPARUSER[2] !== 1'bz) && SAXIACPARUSER_delay[2]; // rv 0 + assign SAXIACPARUSER_in[3] = (SAXIACPARUSER[3] !== 1'bz) && SAXIACPARUSER_delay[3]; // rv 0 + assign SAXIACPARUSER_in[4] = (SAXIACPARUSER[4] !== 1'bz) && SAXIACPARUSER_delay[4]; // rv 0 + assign SAXIACPARVALID_in = (SAXIACPARVALID !== 1'bz) && SAXIACPARVALID_delay; // rv 0 + assign SAXIACPAWADDR_in[0] = (SAXIACPAWADDR[0] !== 1'bz) && SAXIACPAWADDR_delay[0]; // rv 0 + assign SAXIACPAWADDR_in[10] = (SAXIACPAWADDR[10] !== 1'bz) && SAXIACPAWADDR_delay[10]; // rv 0 + assign SAXIACPAWADDR_in[11] = (SAXIACPAWADDR[11] !== 1'bz) && SAXIACPAWADDR_delay[11]; // rv 0 + assign SAXIACPAWADDR_in[12] = (SAXIACPAWADDR[12] !== 1'bz) && SAXIACPAWADDR_delay[12]; // rv 0 + assign SAXIACPAWADDR_in[13] = (SAXIACPAWADDR[13] !== 1'bz) && SAXIACPAWADDR_delay[13]; // rv 0 + assign SAXIACPAWADDR_in[14] = (SAXIACPAWADDR[14] !== 1'bz) && SAXIACPAWADDR_delay[14]; // rv 0 + assign SAXIACPAWADDR_in[15] = (SAXIACPAWADDR[15] !== 1'bz) && SAXIACPAWADDR_delay[15]; // rv 0 + assign SAXIACPAWADDR_in[16] = (SAXIACPAWADDR[16] !== 1'bz) && SAXIACPAWADDR_delay[16]; // rv 0 + assign SAXIACPAWADDR_in[17] = (SAXIACPAWADDR[17] !== 1'bz) && SAXIACPAWADDR_delay[17]; // rv 0 + assign SAXIACPAWADDR_in[18] = (SAXIACPAWADDR[18] !== 1'bz) && SAXIACPAWADDR_delay[18]; // rv 0 + assign SAXIACPAWADDR_in[19] = (SAXIACPAWADDR[19] !== 1'bz) && SAXIACPAWADDR_delay[19]; // rv 0 + assign SAXIACPAWADDR_in[1] = (SAXIACPAWADDR[1] !== 1'bz) && SAXIACPAWADDR_delay[1]; // rv 0 + assign SAXIACPAWADDR_in[20] = (SAXIACPAWADDR[20] !== 1'bz) && SAXIACPAWADDR_delay[20]; // rv 0 + assign SAXIACPAWADDR_in[21] = (SAXIACPAWADDR[21] !== 1'bz) && SAXIACPAWADDR_delay[21]; // rv 0 + assign SAXIACPAWADDR_in[22] = (SAXIACPAWADDR[22] !== 1'bz) && SAXIACPAWADDR_delay[22]; // rv 0 + assign SAXIACPAWADDR_in[23] = (SAXIACPAWADDR[23] !== 1'bz) && SAXIACPAWADDR_delay[23]; // rv 0 + assign SAXIACPAWADDR_in[24] = (SAXIACPAWADDR[24] !== 1'bz) && SAXIACPAWADDR_delay[24]; // rv 0 + assign SAXIACPAWADDR_in[25] = (SAXIACPAWADDR[25] !== 1'bz) && SAXIACPAWADDR_delay[25]; // rv 0 + assign SAXIACPAWADDR_in[26] = (SAXIACPAWADDR[26] !== 1'bz) && SAXIACPAWADDR_delay[26]; // rv 0 + assign SAXIACPAWADDR_in[27] = (SAXIACPAWADDR[27] !== 1'bz) && SAXIACPAWADDR_delay[27]; // rv 0 + assign SAXIACPAWADDR_in[28] = (SAXIACPAWADDR[28] !== 1'bz) && SAXIACPAWADDR_delay[28]; // rv 0 + assign SAXIACPAWADDR_in[29] = (SAXIACPAWADDR[29] !== 1'bz) && SAXIACPAWADDR_delay[29]; // rv 0 + assign SAXIACPAWADDR_in[2] = (SAXIACPAWADDR[2] !== 1'bz) && SAXIACPAWADDR_delay[2]; // rv 0 + assign SAXIACPAWADDR_in[30] = (SAXIACPAWADDR[30] !== 1'bz) && SAXIACPAWADDR_delay[30]; // rv 0 + assign SAXIACPAWADDR_in[31] = (SAXIACPAWADDR[31] !== 1'bz) && SAXIACPAWADDR_delay[31]; // rv 0 + assign SAXIACPAWADDR_in[3] = (SAXIACPAWADDR[3] !== 1'bz) && SAXIACPAWADDR_delay[3]; // rv 0 + assign SAXIACPAWADDR_in[4] = (SAXIACPAWADDR[4] !== 1'bz) && SAXIACPAWADDR_delay[4]; // rv 0 + assign SAXIACPAWADDR_in[5] = (SAXIACPAWADDR[5] !== 1'bz) && SAXIACPAWADDR_delay[5]; // rv 0 + assign SAXIACPAWADDR_in[6] = (SAXIACPAWADDR[6] !== 1'bz) && SAXIACPAWADDR_delay[6]; // rv 0 + assign SAXIACPAWADDR_in[7] = (SAXIACPAWADDR[7] !== 1'bz) && SAXIACPAWADDR_delay[7]; // rv 0 + assign SAXIACPAWADDR_in[8] = (SAXIACPAWADDR[8] !== 1'bz) && SAXIACPAWADDR_delay[8]; // rv 0 + assign SAXIACPAWADDR_in[9] = (SAXIACPAWADDR[9] !== 1'bz) && SAXIACPAWADDR_delay[9]; // rv 0 + assign SAXIACPAWBURST_in[0] = (SAXIACPAWBURST[0] !== 1'bz) && SAXIACPAWBURST_delay[0]; // rv 0 + assign SAXIACPAWBURST_in[1] = (SAXIACPAWBURST[1] !== 1'bz) && SAXIACPAWBURST_delay[1]; // rv 0 + assign SAXIACPAWCACHE_in[0] = (SAXIACPAWCACHE[0] !== 1'bz) && SAXIACPAWCACHE_delay[0]; // rv 0 + assign SAXIACPAWCACHE_in[1] = (SAXIACPAWCACHE[1] !== 1'bz) && SAXIACPAWCACHE_delay[1]; // rv 0 + assign SAXIACPAWCACHE_in[2] = (SAXIACPAWCACHE[2] !== 1'bz) && SAXIACPAWCACHE_delay[2]; // rv 0 + assign SAXIACPAWCACHE_in[3] = (SAXIACPAWCACHE[3] !== 1'bz) && SAXIACPAWCACHE_delay[3]; // rv 0 + assign SAXIACPAWID_in[0] = (SAXIACPAWID[0] !== 1'bz) && SAXIACPAWID_delay[0]; // rv 0 + assign SAXIACPAWID_in[1] = (SAXIACPAWID[1] !== 1'bz) && SAXIACPAWID_delay[1]; // rv 0 + assign SAXIACPAWID_in[2] = (SAXIACPAWID[2] !== 1'bz) && SAXIACPAWID_delay[2]; // rv 0 + assign SAXIACPAWLEN_in[0] = (SAXIACPAWLEN[0] !== 1'bz) && SAXIACPAWLEN_delay[0]; // rv 0 + assign SAXIACPAWLEN_in[1] = (SAXIACPAWLEN[1] !== 1'bz) && SAXIACPAWLEN_delay[1]; // rv 0 + assign SAXIACPAWLEN_in[2] = (SAXIACPAWLEN[2] !== 1'bz) && SAXIACPAWLEN_delay[2]; // rv 0 + assign SAXIACPAWLEN_in[3] = (SAXIACPAWLEN[3] !== 1'bz) && SAXIACPAWLEN_delay[3]; // rv 0 + assign SAXIACPAWLOCK_in[0] = (SAXIACPAWLOCK[0] !== 1'bz) && SAXIACPAWLOCK_delay[0]; // rv 0 + assign SAXIACPAWLOCK_in[1] = (SAXIACPAWLOCK[1] !== 1'bz) && SAXIACPAWLOCK_delay[1]; // rv 0 + assign SAXIACPAWPROT_in[0] = (SAXIACPAWPROT[0] !== 1'bz) && SAXIACPAWPROT_delay[0]; // rv 0 + assign SAXIACPAWPROT_in[1] = (SAXIACPAWPROT[1] !== 1'bz) && SAXIACPAWPROT_delay[1]; // rv 0 + assign SAXIACPAWPROT_in[2] = (SAXIACPAWPROT[2] !== 1'bz) && SAXIACPAWPROT_delay[2]; // rv 0 + assign SAXIACPAWSIZE_in[0] = (SAXIACPAWSIZE[0] !== 1'bz) && SAXIACPAWSIZE_delay[0]; // rv 0 + assign SAXIACPAWSIZE_in[1] = (SAXIACPAWSIZE[1] !== 1'bz) && SAXIACPAWSIZE_delay[1]; // rv 0 + assign SAXIACPAWUSER_in[0] = (SAXIACPAWUSER[0] !== 1'bz) && SAXIACPAWUSER_delay[0]; // rv 0 + assign SAXIACPAWUSER_in[1] = (SAXIACPAWUSER[1] !== 1'bz) && SAXIACPAWUSER_delay[1]; // rv 0 + assign SAXIACPAWUSER_in[2] = (SAXIACPAWUSER[2] !== 1'bz) && SAXIACPAWUSER_delay[2]; // rv 0 + assign SAXIACPAWUSER_in[3] = (SAXIACPAWUSER[3] !== 1'bz) && SAXIACPAWUSER_delay[3]; // rv 0 + assign SAXIACPAWUSER_in[4] = (SAXIACPAWUSER[4] !== 1'bz) && SAXIACPAWUSER_delay[4]; // rv 0 + assign SAXIACPAWVALID_in = (SAXIACPAWVALID !== 1'bz) && SAXIACPAWVALID_delay; // rv 0 + assign SAXIACPBREADY_in = (SAXIACPBREADY !== 1'bz) && SAXIACPBREADY_delay; // rv 0 + assign SAXIACPRREADY_in = (SAXIACPRREADY !== 1'bz) && SAXIACPRREADY_delay; // rv 0 + assign SAXIACPWDATA_in[0] = (SAXIACPWDATA[0] !== 1'bz) && SAXIACPWDATA_delay[0]; // rv 0 + assign SAXIACPWDATA_in[10] = (SAXIACPWDATA[10] !== 1'bz) && SAXIACPWDATA_delay[10]; // rv 0 + assign SAXIACPWDATA_in[11] = (SAXIACPWDATA[11] !== 1'bz) && SAXIACPWDATA_delay[11]; // rv 0 + assign SAXIACPWDATA_in[12] = (SAXIACPWDATA[12] !== 1'bz) && SAXIACPWDATA_delay[12]; // rv 0 + assign SAXIACPWDATA_in[13] = (SAXIACPWDATA[13] !== 1'bz) && SAXIACPWDATA_delay[13]; // rv 0 + assign SAXIACPWDATA_in[14] = (SAXIACPWDATA[14] !== 1'bz) && SAXIACPWDATA_delay[14]; // rv 0 + assign SAXIACPWDATA_in[15] = (SAXIACPWDATA[15] !== 1'bz) && SAXIACPWDATA_delay[15]; // rv 0 + assign SAXIACPWDATA_in[16] = (SAXIACPWDATA[16] !== 1'bz) && SAXIACPWDATA_delay[16]; // rv 0 + assign SAXIACPWDATA_in[17] = (SAXIACPWDATA[17] !== 1'bz) && SAXIACPWDATA_delay[17]; // rv 0 + assign SAXIACPWDATA_in[18] = (SAXIACPWDATA[18] !== 1'bz) && SAXIACPWDATA_delay[18]; // rv 0 + assign SAXIACPWDATA_in[19] = (SAXIACPWDATA[19] !== 1'bz) && SAXIACPWDATA_delay[19]; // rv 0 + assign SAXIACPWDATA_in[1] = (SAXIACPWDATA[1] !== 1'bz) && SAXIACPWDATA_delay[1]; // rv 0 + assign SAXIACPWDATA_in[20] = (SAXIACPWDATA[20] !== 1'bz) && SAXIACPWDATA_delay[20]; // rv 0 + assign SAXIACPWDATA_in[21] = (SAXIACPWDATA[21] !== 1'bz) && SAXIACPWDATA_delay[21]; // rv 0 + assign SAXIACPWDATA_in[22] = (SAXIACPWDATA[22] !== 1'bz) && SAXIACPWDATA_delay[22]; // rv 0 + assign SAXIACPWDATA_in[23] = (SAXIACPWDATA[23] !== 1'bz) && SAXIACPWDATA_delay[23]; // rv 0 + assign SAXIACPWDATA_in[24] = (SAXIACPWDATA[24] !== 1'bz) && SAXIACPWDATA_delay[24]; // rv 0 + assign SAXIACPWDATA_in[25] = (SAXIACPWDATA[25] !== 1'bz) && SAXIACPWDATA_delay[25]; // rv 0 + assign SAXIACPWDATA_in[26] = (SAXIACPWDATA[26] !== 1'bz) && SAXIACPWDATA_delay[26]; // rv 0 + assign SAXIACPWDATA_in[27] = (SAXIACPWDATA[27] !== 1'bz) && SAXIACPWDATA_delay[27]; // rv 0 + assign SAXIACPWDATA_in[28] = (SAXIACPWDATA[28] !== 1'bz) && SAXIACPWDATA_delay[28]; // rv 0 + assign SAXIACPWDATA_in[29] = (SAXIACPWDATA[29] !== 1'bz) && SAXIACPWDATA_delay[29]; // rv 0 + assign SAXIACPWDATA_in[2] = (SAXIACPWDATA[2] !== 1'bz) && SAXIACPWDATA_delay[2]; // rv 0 + assign SAXIACPWDATA_in[30] = (SAXIACPWDATA[30] !== 1'bz) && SAXIACPWDATA_delay[30]; // rv 0 + assign SAXIACPWDATA_in[31] = (SAXIACPWDATA[31] !== 1'bz) && SAXIACPWDATA_delay[31]; // rv 0 + assign SAXIACPWDATA_in[32] = (SAXIACPWDATA[32] !== 1'bz) && SAXIACPWDATA_delay[32]; // rv 0 + assign SAXIACPWDATA_in[33] = (SAXIACPWDATA[33] !== 1'bz) && SAXIACPWDATA_delay[33]; // rv 0 + assign SAXIACPWDATA_in[34] = (SAXIACPWDATA[34] !== 1'bz) && SAXIACPWDATA_delay[34]; // rv 0 + assign SAXIACPWDATA_in[35] = (SAXIACPWDATA[35] !== 1'bz) && SAXIACPWDATA_delay[35]; // rv 0 + assign SAXIACPWDATA_in[36] = (SAXIACPWDATA[36] !== 1'bz) && SAXIACPWDATA_delay[36]; // rv 0 + assign SAXIACPWDATA_in[37] = (SAXIACPWDATA[37] !== 1'bz) && SAXIACPWDATA_delay[37]; // rv 0 + assign SAXIACPWDATA_in[38] = (SAXIACPWDATA[38] !== 1'bz) && SAXIACPWDATA_delay[38]; // rv 0 + assign SAXIACPWDATA_in[39] = (SAXIACPWDATA[39] !== 1'bz) && SAXIACPWDATA_delay[39]; // rv 0 + assign SAXIACPWDATA_in[3] = (SAXIACPWDATA[3] !== 1'bz) && SAXIACPWDATA_delay[3]; // rv 0 + assign SAXIACPWDATA_in[40] = (SAXIACPWDATA[40] !== 1'bz) && SAXIACPWDATA_delay[40]; // rv 0 + assign SAXIACPWDATA_in[41] = (SAXIACPWDATA[41] !== 1'bz) && SAXIACPWDATA_delay[41]; // rv 0 + assign SAXIACPWDATA_in[42] = (SAXIACPWDATA[42] !== 1'bz) && SAXIACPWDATA_delay[42]; // rv 0 + assign SAXIACPWDATA_in[43] = (SAXIACPWDATA[43] !== 1'bz) && SAXIACPWDATA_delay[43]; // rv 0 + assign SAXIACPWDATA_in[44] = (SAXIACPWDATA[44] !== 1'bz) && SAXIACPWDATA_delay[44]; // rv 0 + assign SAXIACPWDATA_in[45] = (SAXIACPWDATA[45] !== 1'bz) && SAXIACPWDATA_delay[45]; // rv 0 + assign SAXIACPWDATA_in[46] = (SAXIACPWDATA[46] !== 1'bz) && SAXIACPWDATA_delay[46]; // rv 0 + assign SAXIACPWDATA_in[47] = (SAXIACPWDATA[47] !== 1'bz) && SAXIACPWDATA_delay[47]; // rv 0 + assign SAXIACPWDATA_in[48] = (SAXIACPWDATA[48] !== 1'bz) && SAXIACPWDATA_delay[48]; // rv 0 + assign SAXIACPWDATA_in[49] = (SAXIACPWDATA[49] !== 1'bz) && SAXIACPWDATA_delay[49]; // rv 0 + assign SAXIACPWDATA_in[4] = (SAXIACPWDATA[4] !== 1'bz) && SAXIACPWDATA_delay[4]; // rv 0 + assign SAXIACPWDATA_in[50] = (SAXIACPWDATA[50] !== 1'bz) && SAXIACPWDATA_delay[50]; // rv 0 + assign SAXIACPWDATA_in[51] = (SAXIACPWDATA[51] !== 1'bz) && SAXIACPWDATA_delay[51]; // rv 0 + assign SAXIACPWDATA_in[52] = (SAXIACPWDATA[52] !== 1'bz) && SAXIACPWDATA_delay[52]; // rv 0 + assign SAXIACPWDATA_in[53] = (SAXIACPWDATA[53] !== 1'bz) && SAXIACPWDATA_delay[53]; // rv 0 + assign SAXIACPWDATA_in[54] = (SAXIACPWDATA[54] !== 1'bz) && SAXIACPWDATA_delay[54]; // rv 0 + assign SAXIACPWDATA_in[55] = (SAXIACPWDATA[55] !== 1'bz) && SAXIACPWDATA_delay[55]; // rv 0 + assign SAXIACPWDATA_in[56] = (SAXIACPWDATA[56] !== 1'bz) && SAXIACPWDATA_delay[56]; // rv 0 + assign SAXIACPWDATA_in[57] = (SAXIACPWDATA[57] !== 1'bz) && SAXIACPWDATA_delay[57]; // rv 0 + assign SAXIACPWDATA_in[58] = (SAXIACPWDATA[58] !== 1'bz) && SAXIACPWDATA_delay[58]; // rv 0 + assign SAXIACPWDATA_in[59] = (SAXIACPWDATA[59] !== 1'bz) && SAXIACPWDATA_delay[59]; // rv 0 + assign SAXIACPWDATA_in[5] = (SAXIACPWDATA[5] !== 1'bz) && SAXIACPWDATA_delay[5]; // rv 0 + assign SAXIACPWDATA_in[60] = (SAXIACPWDATA[60] !== 1'bz) && SAXIACPWDATA_delay[60]; // rv 0 + assign SAXIACPWDATA_in[61] = (SAXIACPWDATA[61] !== 1'bz) && SAXIACPWDATA_delay[61]; // rv 0 + assign SAXIACPWDATA_in[62] = (SAXIACPWDATA[62] !== 1'bz) && SAXIACPWDATA_delay[62]; // rv 0 + assign SAXIACPWDATA_in[63] = (SAXIACPWDATA[63] !== 1'bz) && SAXIACPWDATA_delay[63]; // rv 0 + assign SAXIACPWDATA_in[6] = (SAXIACPWDATA[6] !== 1'bz) && SAXIACPWDATA_delay[6]; // rv 0 + assign SAXIACPWDATA_in[7] = (SAXIACPWDATA[7] !== 1'bz) && SAXIACPWDATA_delay[7]; // rv 0 + assign SAXIACPWDATA_in[8] = (SAXIACPWDATA[8] !== 1'bz) && SAXIACPWDATA_delay[8]; // rv 0 + assign SAXIACPWDATA_in[9] = (SAXIACPWDATA[9] !== 1'bz) && SAXIACPWDATA_delay[9]; // rv 0 + assign SAXIACPWID_in[0] = (SAXIACPWID[0] !== 1'bz) && SAXIACPWID_delay[0]; // rv 0 + assign SAXIACPWID_in[1] = (SAXIACPWID[1] !== 1'bz) && SAXIACPWID_delay[1]; // rv 0 + assign SAXIACPWID_in[2] = (SAXIACPWID[2] !== 1'bz) && SAXIACPWID_delay[2]; // rv 0 + assign SAXIACPWLAST_in = (SAXIACPWLAST !== 1'bz) && SAXIACPWLAST_delay; // rv 0 + assign SAXIACPWSTRB_in[0] = (SAXIACPWSTRB[0] !== 1'bz) && SAXIACPWSTRB_delay[0]; // rv 0 + assign SAXIACPWSTRB_in[1] = (SAXIACPWSTRB[1] !== 1'bz) && SAXIACPWSTRB_delay[1]; // rv 0 + assign SAXIACPWSTRB_in[2] = (SAXIACPWSTRB[2] !== 1'bz) && SAXIACPWSTRB_delay[2]; // rv 0 + assign SAXIACPWSTRB_in[3] = (SAXIACPWSTRB[3] !== 1'bz) && SAXIACPWSTRB_delay[3]; // rv 0 + assign SAXIACPWSTRB_in[4] = (SAXIACPWSTRB[4] !== 1'bz) && SAXIACPWSTRB_delay[4]; // rv 0 + assign SAXIACPWSTRB_in[5] = (SAXIACPWSTRB[5] !== 1'bz) && SAXIACPWSTRB_delay[5]; // rv 0 + assign SAXIACPWSTRB_in[6] = (SAXIACPWSTRB[6] !== 1'bz) && SAXIACPWSTRB_delay[6]; // rv 0 + assign SAXIACPWSTRB_in[7] = (SAXIACPWSTRB[7] !== 1'bz) && SAXIACPWSTRB_delay[7]; // rv 0 + assign SAXIACPWVALID_in = (SAXIACPWVALID !== 1'bz) && SAXIACPWVALID_delay; // rv 0 + assign SAXIGP0ACLK_in = (SAXIGP0ACLK !== 1'bz) && SAXIGP0ACLK_delay; // rv 0 + assign SAXIGP0ARADDR_in[0] = (SAXIGP0ARADDR[0] !== 1'bz) && SAXIGP0ARADDR_delay[0]; // rv 0 + assign SAXIGP0ARADDR_in[10] = (SAXIGP0ARADDR[10] !== 1'bz) && SAXIGP0ARADDR_delay[10]; // rv 0 + assign SAXIGP0ARADDR_in[11] = (SAXIGP0ARADDR[11] !== 1'bz) && SAXIGP0ARADDR_delay[11]; // rv 0 + assign SAXIGP0ARADDR_in[12] = (SAXIGP0ARADDR[12] !== 1'bz) && SAXIGP0ARADDR_delay[12]; // rv 0 + assign SAXIGP0ARADDR_in[13] = (SAXIGP0ARADDR[13] !== 1'bz) && SAXIGP0ARADDR_delay[13]; // rv 0 + assign SAXIGP0ARADDR_in[14] = (SAXIGP0ARADDR[14] !== 1'bz) && SAXIGP0ARADDR_delay[14]; // rv 0 + assign SAXIGP0ARADDR_in[15] = (SAXIGP0ARADDR[15] !== 1'bz) && SAXIGP0ARADDR_delay[15]; // rv 0 + assign SAXIGP0ARADDR_in[16] = (SAXIGP0ARADDR[16] !== 1'bz) && SAXIGP0ARADDR_delay[16]; // rv 0 + assign SAXIGP0ARADDR_in[17] = (SAXIGP0ARADDR[17] !== 1'bz) && SAXIGP0ARADDR_delay[17]; // rv 0 + assign SAXIGP0ARADDR_in[18] = (SAXIGP0ARADDR[18] !== 1'bz) && SAXIGP0ARADDR_delay[18]; // rv 0 + assign SAXIGP0ARADDR_in[19] = (SAXIGP0ARADDR[19] !== 1'bz) && SAXIGP0ARADDR_delay[19]; // rv 0 + assign SAXIGP0ARADDR_in[1] = (SAXIGP0ARADDR[1] !== 1'bz) && SAXIGP0ARADDR_delay[1]; // rv 0 + assign SAXIGP0ARADDR_in[20] = (SAXIGP0ARADDR[20] !== 1'bz) && SAXIGP0ARADDR_delay[20]; // rv 0 + assign SAXIGP0ARADDR_in[21] = (SAXIGP0ARADDR[21] !== 1'bz) && SAXIGP0ARADDR_delay[21]; // rv 0 + assign SAXIGP0ARADDR_in[22] = (SAXIGP0ARADDR[22] !== 1'bz) && SAXIGP0ARADDR_delay[22]; // rv 0 + assign SAXIGP0ARADDR_in[23] = (SAXIGP0ARADDR[23] !== 1'bz) && SAXIGP0ARADDR_delay[23]; // rv 0 + assign SAXIGP0ARADDR_in[24] = (SAXIGP0ARADDR[24] !== 1'bz) && SAXIGP0ARADDR_delay[24]; // rv 0 + assign SAXIGP0ARADDR_in[25] = (SAXIGP0ARADDR[25] !== 1'bz) && SAXIGP0ARADDR_delay[25]; // rv 0 + assign SAXIGP0ARADDR_in[26] = (SAXIGP0ARADDR[26] !== 1'bz) && SAXIGP0ARADDR_delay[26]; // rv 0 + assign SAXIGP0ARADDR_in[27] = (SAXIGP0ARADDR[27] !== 1'bz) && SAXIGP0ARADDR_delay[27]; // rv 0 + assign SAXIGP0ARADDR_in[28] = (SAXIGP0ARADDR[28] !== 1'bz) && SAXIGP0ARADDR_delay[28]; // rv 0 + assign SAXIGP0ARADDR_in[29] = (SAXIGP0ARADDR[29] !== 1'bz) && SAXIGP0ARADDR_delay[29]; // rv 0 + assign SAXIGP0ARADDR_in[2] = (SAXIGP0ARADDR[2] !== 1'bz) && SAXIGP0ARADDR_delay[2]; // rv 0 + assign SAXIGP0ARADDR_in[30] = (SAXIGP0ARADDR[30] !== 1'bz) && SAXIGP0ARADDR_delay[30]; // rv 0 + assign SAXIGP0ARADDR_in[31] = (SAXIGP0ARADDR[31] !== 1'bz) && SAXIGP0ARADDR_delay[31]; // rv 0 + assign SAXIGP0ARADDR_in[3] = (SAXIGP0ARADDR[3] !== 1'bz) && SAXIGP0ARADDR_delay[3]; // rv 0 + assign SAXIGP0ARADDR_in[4] = (SAXIGP0ARADDR[4] !== 1'bz) && SAXIGP0ARADDR_delay[4]; // rv 0 + assign SAXIGP0ARADDR_in[5] = (SAXIGP0ARADDR[5] !== 1'bz) && SAXIGP0ARADDR_delay[5]; // rv 0 + assign SAXIGP0ARADDR_in[6] = (SAXIGP0ARADDR[6] !== 1'bz) && SAXIGP0ARADDR_delay[6]; // rv 0 + assign SAXIGP0ARADDR_in[7] = (SAXIGP0ARADDR[7] !== 1'bz) && SAXIGP0ARADDR_delay[7]; // rv 0 + assign SAXIGP0ARADDR_in[8] = (SAXIGP0ARADDR[8] !== 1'bz) && SAXIGP0ARADDR_delay[8]; // rv 0 + assign SAXIGP0ARADDR_in[9] = (SAXIGP0ARADDR[9] !== 1'bz) && SAXIGP0ARADDR_delay[9]; // rv 0 + assign SAXIGP0ARBURST_in[0] = (SAXIGP0ARBURST[0] !== 1'bz) && SAXIGP0ARBURST_delay[0]; // rv 0 + assign SAXIGP0ARBURST_in[1] = (SAXIGP0ARBURST[1] !== 1'bz) && SAXIGP0ARBURST_delay[1]; // rv 0 + assign SAXIGP0ARCACHE_in[0] = (SAXIGP0ARCACHE[0] !== 1'bz) && SAXIGP0ARCACHE_delay[0]; // rv 0 + assign SAXIGP0ARCACHE_in[1] = (SAXIGP0ARCACHE[1] !== 1'bz) && SAXIGP0ARCACHE_delay[1]; // rv 0 + assign SAXIGP0ARCACHE_in[2] = (SAXIGP0ARCACHE[2] !== 1'bz) && SAXIGP0ARCACHE_delay[2]; // rv 0 + assign SAXIGP0ARCACHE_in[3] = (SAXIGP0ARCACHE[3] !== 1'bz) && SAXIGP0ARCACHE_delay[3]; // rv 0 + assign SAXIGP0ARID_in[0] = (SAXIGP0ARID[0] !== 1'bz) && SAXIGP0ARID_delay[0]; // rv 0 + assign SAXIGP0ARID_in[1] = (SAXIGP0ARID[1] !== 1'bz) && SAXIGP0ARID_delay[1]; // rv 0 + assign SAXIGP0ARID_in[2] = (SAXIGP0ARID[2] !== 1'bz) && SAXIGP0ARID_delay[2]; // rv 0 + assign SAXIGP0ARID_in[3] = (SAXIGP0ARID[3] !== 1'bz) && SAXIGP0ARID_delay[3]; // rv 0 + assign SAXIGP0ARID_in[4] = (SAXIGP0ARID[4] !== 1'bz) && SAXIGP0ARID_delay[4]; // rv 0 + assign SAXIGP0ARID_in[5] = (SAXIGP0ARID[5] !== 1'bz) && SAXIGP0ARID_delay[5]; // rv 0 + assign SAXIGP0ARLEN_in[0] = (SAXIGP0ARLEN[0] !== 1'bz) && SAXIGP0ARLEN_delay[0]; // rv 0 + assign SAXIGP0ARLEN_in[1] = (SAXIGP0ARLEN[1] !== 1'bz) && SAXIGP0ARLEN_delay[1]; // rv 0 + assign SAXIGP0ARLEN_in[2] = (SAXIGP0ARLEN[2] !== 1'bz) && SAXIGP0ARLEN_delay[2]; // rv 0 + assign SAXIGP0ARLEN_in[3] = (SAXIGP0ARLEN[3] !== 1'bz) && SAXIGP0ARLEN_delay[3]; // rv 0 + assign SAXIGP0ARLOCK_in[0] = (SAXIGP0ARLOCK[0] !== 1'bz) && SAXIGP0ARLOCK_delay[0]; // rv 0 + assign SAXIGP0ARLOCK_in[1] = (SAXIGP0ARLOCK[1] !== 1'bz) && SAXIGP0ARLOCK_delay[1]; // rv 0 + assign SAXIGP0ARPROT_in[0] = (SAXIGP0ARPROT[0] !== 1'bz) && SAXIGP0ARPROT_delay[0]; // rv 0 + assign SAXIGP0ARPROT_in[1] = (SAXIGP0ARPROT[1] !== 1'bz) && SAXIGP0ARPROT_delay[1]; // rv 0 + assign SAXIGP0ARPROT_in[2] = (SAXIGP0ARPROT[2] !== 1'bz) && SAXIGP0ARPROT_delay[2]; // rv 0 + assign SAXIGP0ARQOS_in[0] = (SAXIGP0ARQOS[0] !== 1'bz) && SAXIGP0ARQOS_delay[0]; // rv 0 + assign SAXIGP0ARQOS_in[1] = (SAXIGP0ARQOS[1] !== 1'bz) && SAXIGP0ARQOS_delay[1]; // rv 0 + assign SAXIGP0ARQOS_in[2] = (SAXIGP0ARQOS[2] !== 1'bz) && SAXIGP0ARQOS_delay[2]; // rv 0 + assign SAXIGP0ARQOS_in[3] = (SAXIGP0ARQOS[3] !== 1'bz) && SAXIGP0ARQOS_delay[3]; // rv 0 + assign SAXIGP0ARSIZE_in[0] = (SAXIGP0ARSIZE[0] !== 1'bz) && SAXIGP0ARSIZE_delay[0]; // rv 0 + assign SAXIGP0ARSIZE_in[1] = (SAXIGP0ARSIZE[1] !== 1'bz) && SAXIGP0ARSIZE_delay[1]; // rv 0 + assign SAXIGP0ARVALID_in = (SAXIGP0ARVALID !== 1'bz) && SAXIGP0ARVALID_delay; // rv 0 + assign SAXIGP0AWADDR_in[0] = (SAXIGP0AWADDR[0] !== 1'bz) && SAXIGP0AWADDR_delay[0]; // rv 0 + assign SAXIGP0AWADDR_in[10] = (SAXIGP0AWADDR[10] !== 1'bz) && SAXIGP0AWADDR_delay[10]; // rv 0 + assign SAXIGP0AWADDR_in[11] = (SAXIGP0AWADDR[11] !== 1'bz) && SAXIGP0AWADDR_delay[11]; // rv 0 + assign SAXIGP0AWADDR_in[12] = (SAXIGP0AWADDR[12] !== 1'bz) && SAXIGP0AWADDR_delay[12]; // rv 0 + assign SAXIGP0AWADDR_in[13] = (SAXIGP0AWADDR[13] !== 1'bz) && SAXIGP0AWADDR_delay[13]; // rv 0 + assign SAXIGP0AWADDR_in[14] = (SAXIGP0AWADDR[14] !== 1'bz) && SAXIGP0AWADDR_delay[14]; // rv 0 + assign SAXIGP0AWADDR_in[15] = (SAXIGP0AWADDR[15] !== 1'bz) && SAXIGP0AWADDR_delay[15]; // rv 0 + assign SAXIGP0AWADDR_in[16] = (SAXIGP0AWADDR[16] !== 1'bz) && SAXIGP0AWADDR_delay[16]; // rv 0 + assign SAXIGP0AWADDR_in[17] = (SAXIGP0AWADDR[17] !== 1'bz) && SAXIGP0AWADDR_delay[17]; // rv 0 + assign SAXIGP0AWADDR_in[18] = (SAXIGP0AWADDR[18] !== 1'bz) && SAXIGP0AWADDR_delay[18]; // rv 0 + assign SAXIGP0AWADDR_in[19] = (SAXIGP0AWADDR[19] !== 1'bz) && SAXIGP0AWADDR_delay[19]; // rv 0 + assign SAXIGP0AWADDR_in[1] = (SAXIGP0AWADDR[1] !== 1'bz) && SAXIGP0AWADDR_delay[1]; // rv 0 + assign SAXIGP0AWADDR_in[20] = (SAXIGP0AWADDR[20] !== 1'bz) && SAXIGP0AWADDR_delay[20]; // rv 0 + assign SAXIGP0AWADDR_in[21] = (SAXIGP0AWADDR[21] !== 1'bz) && SAXIGP0AWADDR_delay[21]; // rv 0 + assign SAXIGP0AWADDR_in[22] = (SAXIGP0AWADDR[22] !== 1'bz) && SAXIGP0AWADDR_delay[22]; // rv 0 + assign SAXIGP0AWADDR_in[23] = (SAXIGP0AWADDR[23] !== 1'bz) && SAXIGP0AWADDR_delay[23]; // rv 0 + assign SAXIGP0AWADDR_in[24] = (SAXIGP0AWADDR[24] !== 1'bz) && SAXIGP0AWADDR_delay[24]; // rv 0 + assign SAXIGP0AWADDR_in[25] = (SAXIGP0AWADDR[25] !== 1'bz) && SAXIGP0AWADDR_delay[25]; // rv 0 + assign SAXIGP0AWADDR_in[26] = (SAXIGP0AWADDR[26] !== 1'bz) && SAXIGP0AWADDR_delay[26]; // rv 0 + assign SAXIGP0AWADDR_in[27] = (SAXIGP0AWADDR[27] !== 1'bz) && SAXIGP0AWADDR_delay[27]; // rv 0 + assign SAXIGP0AWADDR_in[28] = (SAXIGP0AWADDR[28] !== 1'bz) && SAXIGP0AWADDR_delay[28]; // rv 0 + assign SAXIGP0AWADDR_in[29] = (SAXIGP0AWADDR[29] !== 1'bz) && SAXIGP0AWADDR_delay[29]; // rv 0 + assign SAXIGP0AWADDR_in[2] = (SAXIGP0AWADDR[2] !== 1'bz) && SAXIGP0AWADDR_delay[2]; // rv 0 + assign SAXIGP0AWADDR_in[30] = (SAXIGP0AWADDR[30] !== 1'bz) && SAXIGP0AWADDR_delay[30]; // rv 0 + assign SAXIGP0AWADDR_in[31] = (SAXIGP0AWADDR[31] !== 1'bz) && SAXIGP0AWADDR_delay[31]; // rv 0 + assign SAXIGP0AWADDR_in[3] = (SAXIGP0AWADDR[3] !== 1'bz) && SAXIGP0AWADDR_delay[3]; // rv 0 + assign SAXIGP0AWADDR_in[4] = (SAXIGP0AWADDR[4] !== 1'bz) && SAXIGP0AWADDR_delay[4]; // rv 0 + assign SAXIGP0AWADDR_in[5] = (SAXIGP0AWADDR[5] !== 1'bz) && SAXIGP0AWADDR_delay[5]; // rv 0 + assign SAXIGP0AWADDR_in[6] = (SAXIGP0AWADDR[6] !== 1'bz) && SAXIGP0AWADDR_delay[6]; // rv 0 + assign SAXIGP0AWADDR_in[7] = (SAXIGP0AWADDR[7] !== 1'bz) && SAXIGP0AWADDR_delay[7]; // rv 0 + assign SAXIGP0AWADDR_in[8] = (SAXIGP0AWADDR[8] !== 1'bz) && SAXIGP0AWADDR_delay[8]; // rv 0 + assign SAXIGP0AWADDR_in[9] = (SAXIGP0AWADDR[9] !== 1'bz) && SAXIGP0AWADDR_delay[9]; // rv 0 + assign SAXIGP0AWBURST_in[0] = (SAXIGP0AWBURST[0] !== 1'bz) && SAXIGP0AWBURST_delay[0]; // rv 0 + assign SAXIGP0AWBURST_in[1] = (SAXIGP0AWBURST[1] !== 1'bz) && SAXIGP0AWBURST_delay[1]; // rv 0 + assign SAXIGP0AWCACHE_in[0] = (SAXIGP0AWCACHE[0] !== 1'bz) && SAXIGP0AWCACHE_delay[0]; // rv 0 + assign SAXIGP0AWCACHE_in[1] = (SAXIGP0AWCACHE[1] !== 1'bz) && SAXIGP0AWCACHE_delay[1]; // rv 0 + assign SAXIGP0AWCACHE_in[2] = (SAXIGP0AWCACHE[2] !== 1'bz) && SAXIGP0AWCACHE_delay[2]; // rv 0 + assign SAXIGP0AWCACHE_in[3] = (SAXIGP0AWCACHE[3] !== 1'bz) && SAXIGP0AWCACHE_delay[3]; // rv 0 + assign SAXIGP0AWID_in[0] = (SAXIGP0AWID[0] !== 1'bz) && SAXIGP0AWID_delay[0]; // rv 0 + assign SAXIGP0AWID_in[1] = (SAXIGP0AWID[1] !== 1'bz) && SAXIGP0AWID_delay[1]; // rv 0 + assign SAXIGP0AWID_in[2] = (SAXIGP0AWID[2] !== 1'bz) && SAXIGP0AWID_delay[2]; // rv 0 + assign SAXIGP0AWID_in[3] = (SAXIGP0AWID[3] !== 1'bz) && SAXIGP0AWID_delay[3]; // rv 0 + assign SAXIGP0AWID_in[4] = (SAXIGP0AWID[4] !== 1'bz) && SAXIGP0AWID_delay[4]; // rv 0 + assign SAXIGP0AWID_in[5] = (SAXIGP0AWID[5] !== 1'bz) && SAXIGP0AWID_delay[5]; // rv 0 + assign SAXIGP0AWLEN_in[0] = (SAXIGP0AWLEN[0] !== 1'bz) && SAXIGP0AWLEN_delay[0]; // rv 0 + assign SAXIGP0AWLEN_in[1] = (SAXIGP0AWLEN[1] !== 1'bz) && SAXIGP0AWLEN_delay[1]; // rv 0 + assign SAXIGP0AWLEN_in[2] = (SAXIGP0AWLEN[2] !== 1'bz) && SAXIGP0AWLEN_delay[2]; // rv 0 + assign SAXIGP0AWLEN_in[3] = (SAXIGP0AWLEN[3] !== 1'bz) && SAXIGP0AWLEN_delay[3]; // rv 0 + assign SAXIGP0AWLOCK_in[0] = (SAXIGP0AWLOCK[0] !== 1'bz) && SAXIGP0AWLOCK_delay[0]; // rv 0 + assign SAXIGP0AWLOCK_in[1] = (SAXIGP0AWLOCK[1] !== 1'bz) && SAXIGP0AWLOCK_delay[1]; // rv 0 + assign SAXIGP0AWPROT_in[0] = (SAXIGP0AWPROT[0] !== 1'bz) && SAXIGP0AWPROT_delay[0]; // rv 0 + assign SAXIGP0AWPROT_in[1] = (SAXIGP0AWPROT[1] !== 1'bz) && SAXIGP0AWPROT_delay[1]; // rv 0 + assign SAXIGP0AWPROT_in[2] = (SAXIGP0AWPROT[2] !== 1'bz) && SAXIGP0AWPROT_delay[2]; // rv 0 + assign SAXIGP0AWQOS_in[0] = (SAXIGP0AWQOS[0] !== 1'bz) && SAXIGP0AWQOS_delay[0]; // rv 0 + assign SAXIGP0AWQOS_in[1] = (SAXIGP0AWQOS[1] !== 1'bz) && SAXIGP0AWQOS_delay[1]; // rv 0 + assign SAXIGP0AWQOS_in[2] = (SAXIGP0AWQOS[2] !== 1'bz) && SAXIGP0AWQOS_delay[2]; // rv 0 + assign SAXIGP0AWQOS_in[3] = (SAXIGP0AWQOS[3] !== 1'bz) && SAXIGP0AWQOS_delay[3]; // rv 0 + assign SAXIGP0AWSIZE_in[0] = (SAXIGP0AWSIZE[0] !== 1'bz) && SAXIGP0AWSIZE_delay[0]; // rv 0 + assign SAXIGP0AWSIZE_in[1] = (SAXIGP0AWSIZE[1] !== 1'bz) && SAXIGP0AWSIZE_delay[1]; // rv 0 + assign SAXIGP0AWVALID_in = (SAXIGP0AWVALID !== 1'bz) && SAXIGP0AWVALID_delay; // rv 0 + assign SAXIGP0BREADY_in = (SAXIGP0BREADY !== 1'bz) && SAXIGP0BREADY_delay; // rv 0 + assign SAXIGP0RREADY_in = (SAXIGP0RREADY !== 1'bz) && SAXIGP0RREADY_delay; // rv 0 + assign SAXIGP0WDATA_in[0] = (SAXIGP0WDATA[0] !== 1'bz) && SAXIGP0WDATA_delay[0]; // rv 0 + assign SAXIGP0WDATA_in[10] = (SAXIGP0WDATA[10] !== 1'bz) && SAXIGP0WDATA_delay[10]; // rv 0 + assign SAXIGP0WDATA_in[11] = (SAXIGP0WDATA[11] !== 1'bz) && SAXIGP0WDATA_delay[11]; // rv 0 + assign SAXIGP0WDATA_in[12] = (SAXIGP0WDATA[12] !== 1'bz) && SAXIGP0WDATA_delay[12]; // rv 0 + assign SAXIGP0WDATA_in[13] = (SAXIGP0WDATA[13] !== 1'bz) && SAXIGP0WDATA_delay[13]; // rv 0 + assign SAXIGP0WDATA_in[14] = (SAXIGP0WDATA[14] !== 1'bz) && SAXIGP0WDATA_delay[14]; // rv 0 + assign SAXIGP0WDATA_in[15] = (SAXIGP0WDATA[15] !== 1'bz) && SAXIGP0WDATA_delay[15]; // rv 0 + assign SAXIGP0WDATA_in[16] = (SAXIGP0WDATA[16] !== 1'bz) && SAXIGP0WDATA_delay[16]; // rv 0 + assign SAXIGP0WDATA_in[17] = (SAXIGP0WDATA[17] !== 1'bz) && SAXIGP0WDATA_delay[17]; // rv 0 + assign SAXIGP0WDATA_in[18] = (SAXIGP0WDATA[18] !== 1'bz) && SAXIGP0WDATA_delay[18]; // rv 0 + assign SAXIGP0WDATA_in[19] = (SAXIGP0WDATA[19] !== 1'bz) && SAXIGP0WDATA_delay[19]; // rv 0 + assign SAXIGP0WDATA_in[1] = (SAXIGP0WDATA[1] !== 1'bz) && SAXIGP0WDATA_delay[1]; // rv 0 + assign SAXIGP0WDATA_in[20] = (SAXIGP0WDATA[20] !== 1'bz) && SAXIGP0WDATA_delay[20]; // rv 0 + assign SAXIGP0WDATA_in[21] = (SAXIGP0WDATA[21] !== 1'bz) && SAXIGP0WDATA_delay[21]; // rv 0 + assign SAXIGP0WDATA_in[22] = (SAXIGP0WDATA[22] !== 1'bz) && SAXIGP0WDATA_delay[22]; // rv 0 + assign SAXIGP0WDATA_in[23] = (SAXIGP0WDATA[23] !== 1'bz) && SAXIGP0WDATA_delay[23]; // rv 0 + assign SAXIGP0WDATA_in[24] = (SAXIGP0WDATA[24] !== 1'bz) && SAXIGP0WDATA_delay[24]; // rv 0 + assign SAXIGP0WDATA_in[25] = (SAXIGP0WDATA[25] !== 1'bz) && SAXIGP0WDATA_delay[25]; // rv 0 + assign SAXIGP0WDATA_in[26] = (SAXIGP0WDATA[26] !== 1'bz) && SAXIGP0WDATA_delay[26]; // rv 0 + assign SAXIGP0WDATA_in[27] = (SAXIGP0WDATA[27] !== 1'bz) && SAXIGP0WDATA_delay[27]; // rv 0 + assign SAXIGP0WDATA_in[28] = (SAXIGP0WDATA[28] !== 1'bz) && SAXIGP0WDATA_delay[28]; // rv 0 + assign SAXIGP0WDATA_in[29] = (SAXIGP0WDATA[29] !== 1'bz) && SAXIGP0WDATA_delay[29]; // rv 0 + assign SAXIGP0WDATA_in[2] = (SAXIGP0WDATA[2] !== 1'bz) && SAXIGP0WDATA_delay[2]; // rv 0 + assign SAXIGP0WDATA_in[30] = (SAXIGP0WDATA[30] !== 1'bz) && SAXIGP0WDATA_delay[30]; // rv 0 + assign SAXIGP0WDATA_in[31] = (SAXIGP0WDATA[31] !== 1'bz) && SAXIGP0WDATA_delay[31]; // rv 0 + assign SAXIGP0WDATA_in[3] = (SAXIGP0WDATA[3] !== 1'bz) && SAXIGP0WDATA_delay[3]; // rv 0 + assign SAXIGP0WDATA_in[4] = (SAXIGP0WDATA[4] !== 1'bz) && SAXIGP0WDATA_delay[4]; // rv 0 + assign SAXIGP0WDATA_in[5] = (SAXIGP0WDATA[5] !== 1'bz) && SAXIGP0WDATA_delay[5]; // rv 0 + assign SAXIGP0WDATA_in[6] = (SAXIGP0WDATA[6] !== 1'bz) && SAXIGP0WDATA_delay[6]; // rv 0 + assign SAXIGP0WDATA_in[7] = (SAXIGP0WDATA[7] !== 1'bz) && SAXIGP0WDATA_delay[7]; // rv 0 + assign SAXIGP0WDATA_in[8] = (SAXIGP0WDATA[8] !== 1'bz) && SAXIGP0WDATA_delay[8]; // rv 0 + assign SAXIGP0WDATA_in[9] = (SAXIGP0WDATA[9] !== 1'bz) && SAXIGP0WDATA_delay[9]; // rv 0 + assign SAXIGP0WID_in[0] = (SAXIGP0WID[0] !== 1'bz) && SAXIGP0WID_delay[0]; // rv 0 + assign SAXIGP0WID_in[1] = (SAXIGP0WID[1] !== 1'bz) && SAXIGP0WID_delay[1]; // rv 0 + assign SAXIGP0WID_in[2] = (SAXIGP0WID[2] !== 1'bz) && SAXIGP0WID_delay[2]; // rv 0 + assign SAXIGP0WID_in[3] = (SAXIGP0WID[3] !== 1'bz) && SAXIGP0WID_delay[3]; // rv 0 + assign SAXIGP0WID_in[4] = (SAXIGP0WID[4] !== 1'bz) && SAXIGP0WID_delay[4]; // rv 0 + assign SAXIGP0WID_in[5] = (SAXIGP0WID[5] !== 1'bz) && SAXIGP0WID_delay[5]; // rv 0 + assign SAXIGP0WLAST_in = (SAXIGP0WLAST !== 1'bz) && SAXIGP0WLAST_delay; // rv 0 + assign SAXIGP0WSTRB_in[0] = (SAXIGP0WSTRB[0] !== 1'bz) && SAXIGP0WSTRB_delay[0]; // rv 0 + assign SAXIGP0WSTRB_in[1] = (SAXIGP0WSTRB[1] !== 1'bz) && SAXIGP0WSTRB_delay[1]; // rv 0 + assign SAXIGP0WSTRB_in[2] = (SAXIGP0WSTRB[2] !== 1'bz) && SAXIGP0WSTRB_delay[2]; // rv 0 + assign SAXIGP0WSTRB_in[3] = (SAXIGP0WSTRB[3] !== 1'bz) && SAXIGP0WSTRB_delay[3]; // rv 0 + assign SAXIGP0WVALID_in = (SAXIGP0WVALID !== 1'bz) && SAXIGP0WVALID_delay; // rv 0 + assign SAXIGP1ACLK_in = (SAXIGP1ACLK !== 1'bz) && SAXIGP1ACLK_delay; // rv 0 + assign SAXIGP1ARADDR_in[0] = (SAXIGP1ARADDR[0] !== 1'bz) && SAXIGP1ARADDR_delay[0]; // rv 0 + assign SAXIGP1ARADDR_in[10] = (SAXIGP1ARADDR[10] !== 1'bz) && SAXIGP1ARADDR_delay[10]; // rv 0 + assign SAXIGP1ARADDR_in[11] = (SAXIGP1ARADDR[11] !== 1'bz) && SAXIGP1ARADDR_delay[11]; // rv 0 + assign SAXIGP1ARADDR_in[12] = (SAXIGP1ARADDR[12] !== 1'bz) && SAXIGP1ARADDR_delay[12]; // rv 0 + assign SAXIGP1ARADDR_in[13] = (SAXIGP1ARADDR[13] !== 1'bz) && SAXIGP1ARADDR_delay[13]; // rv 0 + assign SAXIGP1ARADDR_in[14] = (SAXIGP1ARADDR[14] !== 1'bz) && SAXIGP1ARADDR_delay[14]; // rv 0 + assign SAXIGP1ARADDR_in[15] = (SAXIGP1ARADDR[15] !== 1'bz) && SAXIGP1ARADDR_delay[15]; // rv 0 + assign SAXIGP1ARADDR_in[16] = (SAXIGP1ARADDR[16] !== 1'bz) && SAXIGP1ARADDR_delay[16]; // rv 0 + assign SAXIGP1ARADDR_in[17] = (SAXIGP1ARADDR[17] !== 1'bz) && SAXIGP1ARADDR_delay[17]; // rv 0 + assign SAXIGP1ARADDR_in[18] = (SAXIGP1ARADDR[18] !== 1'bz) && SAXIGP1ARADDR_delay[18]; // rv 0 + assign SAXIGP1ARADDR_in[19] = (SAXIGP1ARADDR[19] !== 1'bz) && SAXIGP1ARADDR_delay[19]; // rv 0 + assign SAXIGP1ARADDR_in[1] = (SAXIGP1ARADDR[1] !== 1'bz) && SAXIGP1ARADDR_delay[1]; // rv 0 + assign SAXIGP1ARADDR_in[20] = (SAXIGP1ARADDR[20] !== 1'bz) && SAXIGP1ARADDR_delay[20]; // rv 0 + assign SAXIGP1ARADDR_in[21] = (SAXIGP1ARADDR[21] !== 1'bz) && SAXIGP1ARADDR_delay[21]; // rv 0 + assign SAXIGP1ARADDR_in[22] = (SAXIGP1ARADDR[22] !== 1'bz) && SAXIGP1ARADDR_delay[22]; // rv 0 + assign SAXIGP1ARADDR_in[23] = (SAXIGP1ARADDR[23] !== 1'bz) && SAXIGP1ARADDR_delay[23]; // rv 0 + assign SAXIGP1ARADDR_in[24] = (SAXIGP1ARADDR[24] !== 1'bz) && SAXIGP1ARADDR_delay[24]; // rv 0 + assign SAXIGP1ARADDR_in[25] = (SAXIGP1ARADDR[25] !== 1'bz) && SAXIGP1ARADDR_delay[25]; // rv 0 + assign SAXIGP1ARADDR_in[26] = (SAXIGP1ARADDR[26] !== 1'bz) && SAXIGP1ARADDR_delay[26]; // rv 0 + assign SAXIGP1ARADDR_in[27] = (SAXIGP1ARADDR[27] !== 1'bz) && SAXIGP1ARADDR_delay[27]; // rv 0 + assign SAXIGP1ARADDR_in[28] = (SAXIGP1ARADDR[28] !== 1'bz) && SAXIGP1ARADDR_delay[28]; // rv 0 + assign SAXIGP1ARADDR_in[29] = (SAXIGP1ARADDR[29] !== 1'bz) && SAXIGP1ARADDR_delay[29]; // rv 0 + assign SAXIGP1ARADDR_in[2] = (SAXIGP1ARADDR[2] !== 1'bz) && SAXIGP1ARADDR_delay[2]; // rv 0 + assign SAXIGP1ARADDR_in[30] = (SAXIGP1ARADDR[30] !== 1'bz) && SAXIGP1ARADDR_delay[30]; // rv 0 + assign SAXIGP1ARADDR_in[31] = (SAXIGP1ARADDR[31] !== 1'bz) && SAXIGP1ARADDR_delay[31]; // rv 0 + assign SAXIGP1ARADDR_in[3] = (SAXIGP1ARADDR[3] !== 1'bz) && SAXIGP1ARADDR_delay[3]; // rv 0 + assign SAXIGP1ARADDR_in[4] = (SAXIGP1ARADDR[4] !== 1'bz) && SAXIGP1ARADDR_delay[4]; // rv 0 + assign SAXIGP1ARADDR_in[5] = (SAXIGP1ARADDR[5] !== 1'bz) && SAXIGP1ARADDR_delay[5]; // rv 0 + assign SAXIGP1ARADDR_in[6] = (SAXIGP1ARADDR[6] !== 1'bz) && SAXIGP1ARADDR_delay[6]; // rv 0 + assign SAXIGP1ARADDR_in[7] = (SAXIGP1ARADDR[7] !== 1'bz) && SAXIGP1ARADDR_delay[7]; // rv 0 + assign SAXIGP1ARADDR_in[8] = (SAXIGP1ARADDR[8] !== 1'bz) && SAXIGP1ARADDR_delay[8]; // rv 0 + assign SAXIGP1ARADDR_in[9] = (SAXIGP1ARADDR[9] !== 1'bz) && SAXIGP1ARADDR_delay[9]; // rv 0 + assign SAXIGP1ARBURST_in[0] = (SAXIGP1ARBURST[0] !== 1'bz) && SAXIGP1ARBURST_delay[0]; // rv 0 + assign SAXIGP1ARBURST_in[1] = (SAXIGP1ARBURST[1] !== 1'bz) && SAXIGP1ARBURST_delay[1]; // rv 0 + assign SAXIGP1ARCACHE_in[0] = (SAXIGP1ARCACHE[0] !== 1'bz) && SAXIGP1ARCACHE_delay[0]; // rv 0 + assign SAXIGP1ARCACHE_in[1] = (SAXIGP1ARCACHE[1] !== 1'bz) && SAXIGP1ARCACHE_delay[1]; // rv 0 + assign SAXIGP1ARCACHE_in[2] = (SAXIGP1ARCACHE[2] !== 1'bz) && SAXIGP1ARCACHE_delay[2]; // rv 0 + assign SAXIGP1ARCACHE_in[3] = (SAXIGP1ARCACHE[3] !== 1'bz) && SAXIGP1ARCACHE_delay[3]; // rv 0 + assign SAXIGP1ARID_in[0] = (SAXIGP1ARID[0] !== 1'bz) && SAXIGP1ARID_delay[0]; // rv 0 + assign SAXIGP1ARID_in[1] = (SAXIGP1ARID[1] !== 1'bz) && SAXIGP1ARID_delay[1]; // rv 0 + assign SAXIGP1ARID_in[2] = (SAXIGP1ARID[2] !== 1'bz) && SAXIGP1ARID_delay[2]; // rv 0 + assign SAXIGP1ARID_in[3] = (SAXIGP1ARID[3] !== 1'bz) && SAXIGP1ARID_delay[3]; // rv 0 + assign SAXIGP1ARID_in[4] = (SAXIGP1ARID[4] !== 1'bz) && SAXIGP1ARID_delay[4]; // rv 0 + assign SAXIGP1ARID_in[5] = (SAXIGP1ARID[5] !== 1'bz) && SAXIGP1ARID_delay[5]; // rv 0 + assign SAXIGP1ARLEN_in[0] = (SAXIGP1ARLEN[0] !== 1'bz) && SAXIGP1ARLEN_delay[0]; // rv 0 + assign SAXIGP1ARLEN_in[1] = (SAXIGP1ARLEN[1] !== 1'bz) && SAXIGP1ARLEN_delay[1]; // rv 0 + assign SAXIGP1ARLEN_in[2] = (SAXIGP1ARLEN[2] !== 1'bz) && SAXIGP1ARLEN_delay[2]; // rv 0 + assign SAXIGP1ARLEN_in[3] = (SAXIGP1ARLEN[3] !== 1'bz) && SAXIGP1ARLEN_delay[3]; // rv 0 + assign SAXIGP1ARLOCK_in[0] = (SAXIGP1ARLOCK[0] !== 1'bz) && SAXIGP1ARLOCK_delay[0]; // rv 0 + assign SAXIGP1ARLOCK_in[1] = (SAXIGP1ARLOCK[1] !== 1'bz) && SAXIGP1ARLOCK_delay[1]; // rv 0 + assign SAXIGP1ARPROT_in[0] = (SAXIGP1ARPROT[0] !== 1'bz) && SAXIGP1ARPROT_delay[0]; // rv 0 + assign SAXIGP1ARPROT_in[1] = (SAXIGP1ARPROT[1] !== 1'bz) && SAXIGP1ARPROT_delay[1]; // rv 0 + assign SAXIGP1ARPROT_in[2] = (SAXIGP1ARPROT[2] !== 1'bz) && SAXIGP1ARPROT_delay[2]; // rv 0 + assign SAXIGP1ARQOS_in[0] = (SAXIGP1ARQOS[0] !== 1'bz) && SAXIGP1ARQOS_delay[0]; // rv 0 + assign SAXIGP1ARQOS_in[1] = (SAXIGP1ARQOS[1] !== 1'bz) && SAXIGP1ARQOS_delay[1]; // rv 0 + assign SAXIGP1ARQOS_in[2] = (SAXIGP1ARQOS[2] !== 1'bz) && SAXIGP1ARQOS_delay[2]; // rv 0 + assign SAXIGP1ARQOS_in[3] = (SAXIGP1ARQOS[3] !== 1'bz) && SAXIGP1ARQOS_delay[3]; // rv 0 + assign SAXIGP1ARSIZE_in[0] = (SAXIGP1ARSIZE[0] !== 1'bz) && SAXIGP1ARSIZE_delay[0]; // rv 0 + assign SAXIGP1ARSIZE_in[1] = (SAXIGP1ARSIZE[1] !== 1'bz) && SAXIGP1ARSIZE_delay[1]; // rv 0 + assign SAXIGP1ARVALID_in = (SAXIGP1ARVALID !== 1'bz) && SAXIGP1ARVALID_delay; // rv 0 + assign SAXIGP1AWADDR_in[0] = (SAXIGP1AWADDR[0] !== 1'bz) && SAXIGP1AWADDR_delay[0]; // rv 0 + assign SAXIGP1AWADDR_in[10] = (SAXIGP1AWADDR[10] !== 1'bz) && SAXIGP1AWADDR_delay[10]; // rv 0 + assign SAXIGP1AWADDR_in[11] = (SAXIGP1AWADDR[11] !== 1'bz) && SAXIGP1AWADDR_delay[11]; // rv 0 + assign SAXIGP1AWADDR_in[12] = (SAXIGP1AWADDR[12] !== 1'bz) && SAXIGP1AWADDR_delay[12]; // rv 0 + assign SAXIGP1AWADDR_in[13] = (SAXIGP1AWADDR[13] !== 1'bz) && SAXIGP1AWADDR_delay[13]; // rv 0 + assign SAXIGP1AWADDR_in[14] = (SAXIGP1AWADDR[14] !== 1'bz) && SAXIGP1AWADDR_delay[14]; // rv 0 + assign SAXIGP1AWADDR_in[15] = (SAXIGP1AWADDR[15] !== 1'bz) && SAXIGP1AWADDR_delay[15]; // rv 0 + assign SAXIGP1AWADDR_in[16] = (SAXIGP1AWADDR[16] !== 1'bz) && SAXIGP1AWADDR_delay[16]; // rv 0 + assign SAXIGP1AWADDR_in[17] = (SAXIGP1AWADDR[17] !== 1'bz) && SAXIGP1AWADDR_delay[17]; // rv 0 + assign SAXIGP1AWADDR_in[18] = (SAXIGP1AWADDR[18] !== 1'bz) && SAXIGP1AWADDR_delay[18]; // rv 0 + assign SAXIGP1AWADDR_in[19] = (SAXIGP1AWADDR[19] !== 1'bz) && SAXIGP1AWADDR_delay[19]; // rv 0 + assign SAXIGP1AWADDR_in[1] = (SAXIGP1AWADDR[1] !== 1'bz) && SAXIGP1AWADDR_delay[1]; // rv 0 + assign SAXIGP1AWADDR_in[20] = (SAXIGP1AWADDR[20] !== 1'bz) && SAXIGP1AWADDR_delay[20]; // rv 0 + assign SAXIGP1AWADDR_in[21] = (SAXIGP1AWADDR[21] !== 1'bz) && SAXIGP1AWADDR_delay[21]; // rv 0 + assign SAXIGP1AWADDR_in[22] = (SAXIGP1AWADDR[22] !== 1'bz) && SAXIGP1AWADDR_delay[22]; // rv 0 + assign SAXIGP1AWADDR_in[23] = (SAXIGP1AWADDR[23] !== 1'bz) && SAXIGP1AWADDR_delay[23]; // rv 0 + assign SAXIGP1AWADDR_in[24] = (SAXIGP1AWADDR[24] !== 1'bz) && SAXIGP1AWADDR_delay[24]; // rv 0 + assign SAXIGP1AWADDR_in[25] = (SAXIGP1AWADDR[25] !== 1'bz) && SAXIGP1AWADDR_delay[25]; // rv 0 + assign SAXIGP1AWADDR_in[26] = (SAXIGP1AWADDR[26] !== 1'bz) && SAXIGP1AWADDR_delay[26]; // rv 0 + assign SAXIGP1AWADDR_in[27] = (SAXIGP1AWADDR[27] !== 1'bz) && SAXIGP1AWADDR_delay[27]; // rv 0 + assign SAXIGP1AWADDR_in[28] = (SAXIGP1AWADDR[28] !== 1'bz) && SAXIGP1AWADDR_delay[28]; // rv 0 + assign SAXIGP1AWADDR_in[29] = (SAXIGP1AWADDR[29] !== 1'bz) && SAXIGP1AWADDR_delay[29]; // rv 0 + assign SAXIGP1AWADDR_in[2] = (SAXIGP1AWADDR[2] !== 1'bz) && SAXIGP1AWADDR_delay[2]; // rv 0 + assign SAXIGP1AWADDR_in[30] = (SAXIGP1AWADDR[30] !== 1'bz) && SAXIGP1AWADDR_delay[30]; // rv 0 + assign SAXIGP1AWADDR_in[31] = (SAXIGP1AWADDR[31] !== 1'bz) && SAXIGP1AWADDR_delay[31]; // rv 0 + assign SAXIGP1AWADDR_in[3] = (SAXIGP1AWADDR[3] !== 1'bz) && SAXIGP1AWADDR_delay[3]; // rv 0 + assign SAXIGP1AWADDR_in[4] = (SAXIGP1AWADDR[4] !== 1'bz) && SAXIGP1AWADDR_delay[4]; // rv 0 + assign SAXIGP1AWADDR_in[5] = (SAXIGP1AWADDR[5] !== 1'bz) && SAXIGP1AWADDR_delay[5]; // rv 0 + assign SAXIGP1AWADDR_in[6] = (SAXIGP1AWADDR[6] !== 1'bz) && SAXIGP1AWADDR_delay[6]; // rv 0 + assign SAXIGP1AWADDR_in[7] = (SAXIGP1AWADDR[7] !== 1'bz) && SAXIGP1AWADDR_delay[7]; // rv 0 + assign SAXIGP1AWADDR_in[8] = (SAXIGP1AWADDR[8] !== 1'bz) && SAXIGP1AWADDR_delay[8]; // rv 0 + assign SAXIGP1AWADDR_in[9] = (SAXIGP1AWADDR[9] !== 1'bz) && SAXIGP1AWADDR_delay[9]; // rv 0 + assign SAXIGP1AWBURST_in[0] = (SAXIGP1AWBURST[0] !== 1'bz) && SAXIGP1AWBURST_delay[0]; // rv 0 + assign SAXIGP1AWBURST_in[1] = (SAXIGP1AWBURST[1] !== 1'bz) && SAXIGP1AWBURST_delay[1]; // rv 0 + assign SAXIGP1AWCACHE_in[0] = (SAXIGP1AWCACHE[0] !== 1'bz) && SAXIGP1AWCACHE_delay[0]; // rv 0 + assign SAXIGP1AWCACHE_in[1] = (SAXIGP1AWCACHE[1] !== 1'bz) && SAXIGP1AWCACHE_delay[1]; // rv 0 + assign SAXIGP1AWCACHE_in[2] = (SAXIGP1AWCACHE[2] !== 1'bz) && SAXIGP1AWCACHE_delay[2]; // rv 0 + assign SAXIGP1AWCACHE_in[3] = (SAXIGP1AWCACHE[3] !== 1'bz) && SAXIGP1AWCACHE_delay[3]; // rv 0 + assign SAXIGP1AWID_in[0] = (SAXIGP1AWID[0] !== 1'bz) && SAXIGP1AWID_delay[0]; // rv 0 + assign SAXIGP1AWID_in[1] = (SAXIGP1AWID[1] !== 1'bz) && SAXIGP1AWID_delay[1]; // rv 0 + assign SAXIGP1AWID_in[2] = (SAXIGP1AWID[2] !== 1'bz) && SAXIGP1AWID_delay[2]; // rv 0 + assign SAXIGP1AWID_in[3] = (SAXIGP1AWID[3] !== 1'bz) && SAXIGP1AWID_delay[3]; // rv 0 + assign SAXIGP1AWID_in[4] = (SAXIGP1AWID[4] !== 1'bz) && SAXIGP1AWID_delay[4]; // rv 0 + assign SAXIGP1AWID_in[5] = (SAXIGP1AWID[5] !== 1'bz) && SAXIGP1AWID_delay[5]; // rv 0 + assign SAXIGP1AWLEN_in[0] = (SAXIGP1AWLEN[0] !== 1'bz) && SAXIGP1AWLEN_delay[0]; // rv 0 + assign SAXIGP1AWLEN_in[1] = (SAXIGP1AWLEN[1] !== 1'bz) && SAXIGP1AWLEN_delay[1]; // rv 0 + assign SAXIGP1AWLEN_in[2] = (SAXIGP1AWLEN[2] !== 1'bz) && SAXIGP1AWLEN_delay[2]; // rv 0 + assign SAXIGP1AWLEN_in[3] = (SAXIGP1AWLEN[3] !== 1'bz) && SAXIGP1AWLEN_delay[3]; // rv 0 + assign SAXIGP1AWLOCK_in[0] = (SAXIGP1AWLOCK[0] !== 1'bz) && SAXIGP1AWLOCK_delay[0]; // rv 0 + assign SAXIGP1AWLOCK_in[1] = (SAXIGP1AWLOCK[1] !== 1'bz) && SAXIGP1AWLOCK_delay[1]; // rv 0 + assign SAXIGP1AWPROT_in[0] = (SAXIGP1AWPROT[0] !== 1'bz) && SAXIGP1AWPROT_delay[0]; // rv 0 + assign SAXIGP1AWPROT_in[1] = (SAXIGP1AWPROT[1] !== 1'bz) && SAXIGP1AWPROT_delay[1]; // rv 0 + assign SAXIGP1AWPROT_in[2] = (SAXIGP1AWPROT[2] !== 1'bz) && SAXIGP1AWPROT_delay[2]; // rv 0 + assign SAXIGP1AWQOS_in[0] = (SAXIGP1AWQOS[0] !== 1'bz) && SAXIGP1AWQOS_delay[0]; // rv 0 + assign SAXIGP1AWQOS_in[1] = (SAXIGP1AWQOS[1] !== 1'bz) && SAXIGP1AWQOS_delay[1]; // rv 0 + assign SAXIGP1AWQOS_in[2] = (SAXIGP1AWQOS[2] !== 1'bz) && SAXIGP1AWQOS_delay[2]; // rv 0 + assign SAXIGP1AWQOS_in[3] = (SAXIGP1AWQOS[3] !== 1'bz) && SAXIGP1AWQOS_delay[3]; // rv 0 + assign SAXIGP1AWSIZE_in[0] = (SAXIGP1AWSIZE[0] !== 1'bz) && SAXIGP1AWSIZE_delay[0]; // rv 0 + assign SAXIGP1AWSIZE_in[1] = (SAXIGP1AWSIZE[1] !== 1'bz) && SAXIGP1AWSIZE_delay[1]; // rv 0 + assign SAXIGP1AWVALID_in = (SAXIGP1AWVALID !== 1'bz) && SAXIGP1AWVALID_delay; // rv 0 + assign SAXIGP1BREADY_in = (SAXIGP1BREADY !== 1'bz) && SAXIGP1BREADY_delay; // rv 0 + assign SAXIGP1RREADY_in = (SAXIGP1RREADY !== 1'bz) && SAXIGP1RREADY_delay; // rv 0 + assign SAXIGP1WDATA_in[0] = (SAXIGP1WDATA[0] !== 1'bz) && SAXIGP1WDATA_delay[0]; // rv 0 + assign SAXIGP1WDATA_in[10] = (SAXIGP1WDATA[10] !== 1'bz) && SAXIGP1WDATA_delay[10]; // rv 0 + assign SAXIGP1WDATA_in[11] = (SAXIGP1WDATA[11] !== 1'bz) && SAXIGP1WDATA_delay[11]; // rv 0 + assign SAXIGP1WDATA_in[12] = (SAXIGP1WDATA[12] !== 1'bz) && SAXIGP1WDATA_delay[12]; // rv 0 + assign SAXIGP1WDATA_in[13] = (SAXIGP1WDATA[13] !== 1'bz) && SAXIGP1WDATA_delay[13]; // rv 0 + assign SAXIGP1WDATA_in[14] = (SAXIGP1WDATA[14] !== 1'bz) && SAXIGP1WDATA_delay[14]; // rv 0 + assign SAXIGP1WDATA_in[15] = (SAXIGP1WDATA[15] !== 1'bz) && SAXIGP1WDATA_delay[15]; // rv 0 + assign SAXIGP1WDATA_in[16] = (SAXIGP1WDATA[16] !== 1'bz) && SAXIGP1WDATA_delay[16]; // rv 0 + assign SAXIGP1WDATA_in[17] = (SAXIGP1WDATA[17] !== 1'bz) && SAXIGP1WDATA_delay[17]; // rv 0 + assign SAXIGP1WDATA_in[18] = (SAXIGP1WDATA[18] !== 1'bz) && SAXIGP1WDATA_delay[18]; // rv 0 + assign SAXIGP1WDATA_in[19] = (SAXIGP1WDATA[19] !== 1'bz) && SAXIGP1WDATA_delay[19]; // rv 0 + assign SAXIGP1WDATA_in[1] = (SAXIGP1WDATA[1] !== 1'bz) && SAXIGP1WDATA_delay[1]; // rv 0 + assign SAXIGP1WDATA_in[20] = (SAXIGP1WDATA[20] !== 1'bz) && SAXIGP1WDATA_delay[20]; // rv 0 + assign SAXIGP1WDATA_in[21] = (SAXIGP1WDATA[21] !== 1'bz) && SAXIGP1WDATA_delay[21]; // rv 0 + assign SAXIGP1WDATA_in[22] = (SAXIGP1WDATA[22] !== 1'bz) && SAXIGP1WDATA_delay[22]; // rv 0 + assign SAXIGP1WDATA_in[23] = (SAXIGP1WDATA[23] !== 1'bz) && SAXIGP1WDATA_delay[23]; // rv 0 + assign SAXIGP1WDATA_in[24] = (SAXIGP1WDATA[24] !== 1'bz) && SAXIGP1WDATA_delay[24]; // rv 0 + assign SAXIGP1WDATA_in[25] = (SAXIGP1WDATA[25] !== 1'bz) && SAXIGP1WDATA_delay[25]; // rv 0 + assign SAXIGP1WDATA_in[26] = (SAXIGP1WDATA[26] !== 1'bz) && SAXIGP1WDATA_delay[26]; // rv 0 + assign SAXIGP1WDATA_in[27] = (SAXIGP1WDATA[27] !== 1'bz) && SAXIGP1WDATA_delay[27]; // rv 0 + assign SAXIGP1WDATA_in[28] = (SAXIGP1WDATA[28] !== 1'bz) && SAXIGP1WDATA_delay[28]; // rv 0 + assign SAXIGP1WDATA_in[29] = (SAXIGP1WDATA[29] !== 1'bz) && SAXIGP1WDATA_delay[29]; // rv 0 + assign SAXIGP1WDATA_in[2] = (SAXIGP1WDATA[2] !== 1'bz) && SAXIGP1WDATA_delay[2]; // rv 0 + assign SAXIGP1WDATA_in[30] = (SAXIGP1WDATA[30] !== 1'bz) && SAXIGP1WDATA_delay[30]; // rv 0 + assign SAXIGP1WDATA_in[31] = (SAXIGP1WDATA[31] !== 1'bz) && SAXIGP1WDATA_delay[31]; // rv 0 + assign SAXIGP1WDATA_in[3] = (SAXIGP1WDATA[3] !== 1'bz) && SAXIGP1WDATA_delay[3]; // rv 0 + assign SAXIGP1WDATA_in[4] = (SAXIGP1WDATA[4] !== 1'bz) && SAXIGP1WDATA_delay[4]; // rv 0 + assign SAXIGP1WDATA_in[5] = (SAXIGP1WDATA[5] !== 1'bz) && SAXIGP1WDATA_delay[5]; // rv 0 + assign SAXIGP1WDATA_in[6] = (SAXIGP1WDATA[6] !== 1'bz) && SAXIGP1WDATA_delay[6]; // rv 0 + assign SAXIGP1WDATA_in[7] = (SAXIGP1WDATA[7] !== 1'bz) && SAXIGP1WDATA_delay[7]; // rv 0 + assign SAXIGP1WDATA_in[8] = (SAXIGP1WDATA[8] !== 1'bz) && SAXIGP1WDATA_delay[8]; // rv 0 + assign SAXIGP1WDATA_in[9] = (SAXIGP1WDATA[9] !== 1'bz) && SAXIGP1WDATA_delay[9]; // rv 0 + assign SAXIGP1WID_in[0] = (SAXIGP1WID[0] !== 1'bz) && SAXIGP1WID_delay[0]; // rv 0 + assign SAXIGP1WID_in[1] = (SAXIGP1WID[1] !== 1'bz) && SAXIGP1WID_delay[1]; // rv 0 + assign SAXIGP1WID_in[2] = (SAXIGP1WID[2] !== 1'bz) && SAXIGP1WID_delay[2]; // rv 0 + assign SAXIGP1WID_in[3] = (SAXIGP1WID[3] !== 1'bz) && SAXIGP1WID_delay[3]; // rv 0 + assign SAXIGP1WID_in[4] = (SAXIGP1WID[4] !== 1'bz) && SAXIGP1WID_delay[4]; // rv 0 + assign SAXIGP1WID_in[5] = (SAXIGP1WID[5] !== 1'bz) && SAXIGP1WID_delay[5]; // rv 0 + assign SAXIGP1WLAST_in = (SAXIGP1WLAST !== 1'bz) && SAXIGP1WLAST_delay; // rv 0 + assign SAXIGP1WSTRB_in[0] = (SAXIGP1WSTRB[0] !== 1'bz) && SAXIGP1WSTRB_delay[0]; // rv 0 + assign SAXIGP1WSTRB_in[1] = (SAXIGP1WSTRB[1] !== 1'bz) && SAXIGP1WSTRB_delay[1]; // rv 0 + assign SAXIGP1WSTRB_in[2] = (SAXIGP1WSTRB[2] !== 1'bz) && SAXIGP1WSTRB_delay[2]; // rv 0 + assign SAXIGP1WSTRB_in[3] = (SAXIGP1WSTRB[3] !== 1'bz) && SAXIGP1WSTRB_delay[3]; // rv 0 + assign SAXIGP1WVALID_in = (SAXIGP1WVALID !== 1'bz) && SAXIGP1WVALID_delay; // rv 0 + assign SAXIHP0ACLK_in = (SAXIHP0ACLK !== 1'bz) && SAXIHP0ACLK_delay; // rv 0 + assign SAXIHP0ARADDR_in[0] = (SAXIHP0ARADDR[0] !== 1'bz) && SAXIHP0ARADDR_delay[0]; // rv 0 + assign SAXIHP0ARADDR_in[10] = (SAXIHP0ARADDR[10] !== 1'bz) && SAXIHP0ARADDR_delay[10]; // rv 0 + assign SAXIHP0ARADDR_in[11] = (SAXIHP0ARADDR[11] !== 1'bz) && SAXIHP0ARADDR_delay[11]; // rv 0 + assign SAXIHP0ARADDR_in[12] = (SAXIHP0ARADDR[12] !== 1'bz) && SAXIHP0ARADDR_delay[12]; // rv 0 + assign SAXIHP0ARADDR_in[13] = (SAXIHP0ARADDR[13] !== 1'bz) && SAXIHP0ARADDR_delay[13]; // rv 0 + assign SAXIHP0ARADDR_in[14] = (SAXIHP0ARADDR[14] !== 1'bz) && SAXIHP0ARADDR_delay[14]; // rv 0 + assign SAXIHP0ARADDR_in[15] = (SAXIHP0ARADDR[15] !== 1'bz) && SAXIHP0ARADDR_delay[15]; // rv 0 + assign SAXIHP0ARADDR_in[16] = (SAXIHP0ARADDR[16] !== 1'bz) && SAXIHP0ARADDR_delay[16]; // rv 0 + assign SAXIHP0ARADDR_in[17] = (SAXIHP0ARADDR[17] !== 1'bz) && SAXIHP0ARADDR_delay[17]; // rv 0 + assign SAXIHP0ARADDR_in[18] = (SAXIHP0ARADDR[18] !== 1'bz) && SAXIHP0ARADDR_delay[18]; // rv 0 + assign SAXIHP0ARADDR_in[19] = (SAXIHP0ARADDR[19] !== 1'bz) && SAXIHP0ARADDR_delay[19]; // rv 0 + assign SAXIHP0ARADDR_in[1] = (SAXIHP0ARADDR[1] !== 1'bz) && SAXIHP0ARADDR_delay[1]; // rv 0 + assign SAXIHP0ARADDR_in[20] = (SAXIHP0ARADDR[20] !== 1'bz) && SAXIHP0ARADDR_delay[20]; // rv 0 + assign SAXIHP0ARADDR_in[21] = (SAXIHP0ARADDR[21] !== 1'bz) && SAXIHP0ARADDR_delay[21]; // rv 0 + assign SAXIHP0ARADDR_in[22] = (SAXIHP0ARADDR[22] !== 1'bz) && SAXIHP0ARADDR_delay[22]; // rv 0 + assign SAXIHP0ARADDR_in[23] = (SAXIHP0ARADDR[23] !== 1'bz) && SAXIHP0ARADDR_delay[23]; // rv 0 + assign SAXIHP0ARADDR_in[24] = (SAXIHP0ARADDR[24] !== 1'bz) && SAXIHP0ARADDR_delay[24]; // rv 0 + assign SAXIHP0ARADDR_in[25] = (SAXIHP0ARADDR[25] !== 1'bz) && SAXIHP0ARADDR_delay[25]; // rv 0 + assign SAXIHP0ARADDR_in[26] = (SAXIHP0ARADDR[26] !== 1'bz) && SAXIHP0ARADDR_delay[26]; // rv 0 + assign SAXIHP0ARADDR_in[27] = (SAXIHP0ARADDR[27] !== 1'bz) && SAXIHP0ARADDR_delay[27]; // rv 0 + assign SAXIHP0ARADDR_in[28] = (SAXIHP0ARADDR[28] !== 1'bz) && SAXIHP0ARADDR_delay[28]; // rv 0 + assign SAXIHP0ARADDR_in[29] = (SAXIHP0ARADDR[29] !== 1'bz) && SAXIHP0ARADDR_delay[29]; // rv 0 + assign SAXIHP0ARADDR_in[2] = (SAXIHP0ARADDR[2] !== 1'bz) && SAXIHP0ARADDR_delay[2]; // rv 0 + assign SAXIHP0ARADDR_in[30] = (SAXIHP0ARADDR[30] !== 1'bz) && SAXIHP0ARADDR_delay[30]; // rv 0 + assign SAXIHP0ARADDR_in[31] = (SAXIHP0ARADDR[31] !== 1'bz) && SAXIHP0ARADDR_delay[31]; // rv 0 + assign SAXIHP0ARADDR_in[3] = (SAXIHP0ARADDR[3] !== 1'bz) && SAXIHP0ARADDR_delay[3]; // rv 0 + assign SAXIHP0ARADDR_in[4] = (SAXIHP0ARADDR[4] !== 1'bz) && SAXIHP0ARADDR_delay[4]; // rv 0 + assign SAXIHP0ARADDR_in[5] = (SAXIHP0ARADDR[5] !== 1'bz) && SAXIHP0ARADDR_delay[5]; // rv 0 + assign SAXIHP0ARADDR_in[6] = (SAXIHP0ARADDR[6] !== 1'bz) && SAXIHP0ARADDR_delay[6]; // rv 0 + assign SAXIHP0ARADDR_in[7] = (SAXIHP0ARADDR[7] !== 1'bz) && SAXIHP0ARADDR_delay[7]; // rv 0 + assign SAXIHP0ARADDR_in[8] = (SAXIHP0ARADDR[8] !== 1'bz) && SAXIHP0ARADDR_delay[8]; // rv 0 + assign SAXIHP0ARADDR_in[9] = (SAXIHP0ARADDR[9] !== 1'bz) && SAXIHP0ARADDR_delay[9]; // rv 0 + assign SAXIHP0ARBURST_in[0] = (SAXIHP0ARBURST[0] !== 1'bz) && SAXIHP0ARBURST_delay[0]; // rv 0 + assign SAXIHP0ARBURST_in[1] = (SAXIHP0ARBURST[1] !== 1'bz) && SAXIHP0ARBURST_delay[1]; // rv 0 + assign SAXIHP0ARCACHE_in[0] = (SAXIHP0ARCACHE[0] !== 1'bz) && SAXIHP0ARCACHE_delay[0]; // rv 0 + assign SAXIHP0ARCACHE_in[1] = (SAXIHP0ARCACHE[1] !== 1'bz) && SAXIHP0ARCACHE_delay[1]; // rv 0 + assign SAXIHP0ARCACHE_in[2] = (SAXIHP0ARCACHE[2] !== 1'bz) && SAXIHP0ARCACHE_delay[2]; // rv 0 + assign SAXIHP0ARCACHE_in[3] = (SAXIHP0ARCACHE[3] !== 1'bz) && SAXIHP0ARCACHE_delay[3]; // rv 0 + assign SAXIHP0ARID_in[0] = (SAXIHP0ARID[0] !== 1'bz) && SAXIHP0ARID_delay[0]; // rv 0 + assign SAXIHP0ARID_in[1] = (SAXIHP0ARID[1] !== 1'bz) && SAXIHP0ARID_delay[1]; // rv 0 + assign SAXIHP0ARID_in[2] = (SAXIHP0ARID[2] !== 1'bz) && SAXIHP0ARID_delay[2]; // rv 0 + assign SAXIHP0ARID_in[3] = (SAXIHP0ARID[3] !== 1'bz) && SAXIHP0ARID_delay[3]; // rv 0 + assign SAXIHP0ARID_in[4] = (SAXIHP0ARID[4] !== 1'bz) && SAXIHP0ARID_delay[4]; // rv 0 + assign SAXIHP0ARID_in[5] = (SAXIHP0ARID[5] !== 1'bz) && SAXIHP0ARID_delay[5]; // rv 0 + assign SAXIHP0ARLEN_in[0] = (SAXIHP0ARLEN[0] !== 1'bz) && SAXIHP0ARLEN_delay[0]; // rv 0 + assign SAXIHP0ARLEN_in[1] = (SAXIHP0ARLEN[1] !== 1'bz) && SAXIHP0ARLEN_delay[1]; // rv 0 + assign SAXIHP0ARLEN_in[2] = (SAXIHP0ARLEN[2] !== 1'bz) && SAXIHP0ARLEN_delay[2]; // rv 0 + assign SAXIHP0ARLEN_in[3] = (SAXIHP0ARLEN[3] !== 1'bz) && SAXIHP0ARLEN_delay[3]; // rv 0 + assign SAXIHP0ARLOCK_in[0] = (SAXIHP0ARLOCK[0] !== 1'bz) && SAXIHP0ARLOCK_delay[0]; // rv 0 + assign SAXIHP0ARLOCK_in[1] = (SAXIHP0ARLOCK[1] !== 1'bz) && SAXIHP0ARLOCK_delay[1]; // rv 0 + assign SAXIHP0ARPROT_in[0] = (SAXIHP0ARPROT[0] !== 1'bz) && SAXIHP0ARPROT_delay[0]; // rv 0 + assign SAXIHP0ARPROT_in[1] = (SAXIHP0ARPROT[1] !== 1'bz) && SAXIHP0ARPROT_delay[1]; // rv 0 + assign SAXIHP0ARPROT_in[2] = (SAXIHP0ARPROT[2] !== 1'bz) && SAXIHP0ARPROT_delay[2]; // rv 0 + assign SAXIHP0ARQOS_in[0] = (SAXIHP0ARQOS[0] !== 1'bz) && SAXIHP0ARQOS_delay[0]; // rv 0 + assign SAXIHP0ARQOS_in[1] = (SAXIHP0ARQOS[1] !== 1'bz) && SAXIHP0ARQOS_delay[1]; // rv 0 + assign SAXIHP0ARQOS_in[2] = (SAXIHP0ARQOS[2] !== 1'bz) && SAXIHP0ARQOS_delay[2]; // rv 0 + assign SAXIHP0ARQOS_in[3] = (SAXIHP0ARQOS[3] !== 1'bz) && SAXIHP0ARQOS_delay[3]; // rv 0 + assign SAXIHP0ARSIZE_in[0] = (SAXIHP0ARSIZE[0] !== 1'bz) && SAXIHP0ARSIZE_delay[0]; // rv 0 + assign SAXIHP0ARSIZE_in[1] = (SAXIHP0ARSIZE[1] !== 1'bz) && SAXIHP0ARSIZE_delay[1]; // rv 0 + assign SAXIHP0ARVALID_in = (SAXIHP0ARVALID !== 1'bz) && SAXIHP0ARVALID_delay; // rv 0 + assign SAXIHP0AWADDR_in[0] = (SAXIHP0AWADDR[0] !== 1'bz) && SAXIHP0AWADDR_delay[0]; // rv 0 + assign SAXIHP0AWADDR_in[10] = (SAXIHP0AWADDR[10] !== 1'bz) && SAXIHP0AWADDR_delay[10]; // rv 0 + assign SAXIHP0AWADDR_in[11] = (SAXIHP0AWADDR[11] !== 1'bz) && SAXIHP0AWADDR_delay[11]; // rv 0 + assign SAXIHP0AWADDR_in[12] = (SAXIHP0AWADDR[12] !== 1'bz) && SAXIHP0AWADDR_delay[12]; // rv 0 + assign SAXIHP0AWADDR_in[13] = (SAXIHP0AWADDR[13] !== 1'bz) && SAXIHP0AWADDR_delay[13]; // rv 0 + assign SAXIHP0AWADDR_in[14] = (SAXIHP0AWADDR[14] !== 1'bz) && SAXIHP0AWADDR_delay[14]; // rv 0 + assign SAXIHP0AWADDR_in[15] = (SAXIHP0AWADDR[15] !== 1'bz) && SAXIHP0AWADDR_delay[15]; // rv 0 + assign SAXIHP0AWADDR_in[16] = (SAXIHP0AWADDR[16] !== 1'bz) && SAXIHP0AWADDR_delay[16]; // rv 0 + assign SAXIHP0AWADDR_in[17] = (SAXIHP0AWADDR[17] !== 1'bz) && SAXIHP0AWADDR_delay[17]; // rv 0 + assign SAXIHP0AWADDR_in[18] = (SAXIHP0AWADDR[18] !== 1'bz) && SAXIHP0AWADDR_delay[18]; // rv 0 + assign SAXIHP0AWADDR_in[19] = (SAXIHP0AWADDR[19] !== 1'bz) && SAXIHP0AWADDR_delay[19]; // rv 0 + assign SAXIHP0AWADDR_in[1] = (SAXIHP0AWADDR[1] !== 1'bz) && SAXIHP0AWADDR_delay[1]; // rv 0 + assign SAXIHP0AWADDR_in[20] = (SAXIHP0AWADDR[20] !== 1'bz) && SAXIHP0AWADDR_delay[20]; // rv 0 + assign SAXIHP0AWADDR_in[21] = (SAXIHP0AWADDR[21] !== 1'bz) && SAXIHP0AWADDR_delay[21]; // rv 0 + assign SAXIHP0AWADDR_in[22] = (SAXIHP0AWADDR[22] !== 1'bz) && SAXIHP0AWADDR_delay[22]; // rv 0 + assign SAXIHP0AWADDR_in[23] = (SAXIHP0AWADDR[23] !== 1'bz) && SAXIHP0AWADDR_delay[23]; // rv 0 + assign SAXIHP0AWADDR_in[24] = (SAXIHP0AWADDR[24] !== 1'bz) && SAXIHP0AWADDR_delay[24]; // rv 0 + assign SAXIHP0AWADDR_in[25] = (SAXIHP0AWADDR[25] !== 1'bz) && SAXIHP0AWADDR_delay[25]; // rv 0 + assign SAXIHP0AWADDR_in[26] = (SAXIHP0AWADDR[26] !== 1'bz) && SAXIHP0AWADDR_delay[26]; // rv 0 + assign SAXIHP0AWADDR_in[27] = (SAXIHP0AWADDR[27] !== 1'bz) && SAXIHP0AWADDR_delay[27]; // rv 0 + assign SAXIHP0AWADDR_in[28] = (SAXIHP0AWADDR[28] !== 1'bz) && SAXIHP0AWADDR_delay[28]; // rv 0 + assign SAXIHP0AWADDR_in[29] = (SAXIHP0AWADDR[29] !== 1'bz) && SAXIHP0AWADDR_delay[29]; // rv 0 + assign SAXIHP0AWADDR_in[2] = (SAXIHP0AWADDR[2] !== 1'bz) && SAXIHP0AWADDR_delay[2]; // rv 0 + assign SAXIHP0AWADDR_in[30] = (SAXIHP0AWADDR[30] !== 1'bz) && SAXIHP0AWADDR_delay[30]; // rv 0 + assign SAXIHP0AWADDR_in[31] = (SAXIHP0AWADDR[31] !== 1'bz) && SAXIHP0AWADDR_delay[31]; // rv 0 + assign SAXIHP0AWADDR_in[3] = (SAXIHP0AWADDR[3] !== 1'bz) && SAXIHP0AWADDR_delay[3]; // rv 0 + assign SAXIHP0AWADDR_in[4] = (SAXIHP0AWADDR[4] !== 1'bz) && SAXIHP0AWADDR_delay[4]; // rv 0 + assign SAXIHP0AWADDR_in[5] = (SAXIHP0AWADDR[5] !== 1'bz) && SAXIHP0AWADDR_delay[5]; // rv 0 + assign SAXIHP0AWADDR_in[6] = (SAXIHP0AWADDR[6] !== 1'bz) && SAXIHP0AWADDR_delay[6]; // rv 0 + assign SAXIHP0AWADDR_in[7] = (SAXIHP0AWADDR[7] !== 1'bz) && SAXIHP0AWADDR_delay[7]; // rv 0 + assign SAXIHP0AWADDR_in[8] = (SAXIHP0AWADDR[8] !== 1'bz) && SAXIHP0AWADDR_delay[8]; // rv 0 + assign SAXIHP0AWADDR_in[9] = (SAXIHP0AWADDR[9] !== 1'bz) && SAXIHP0AWADDR_delay[9]; // rv 0 + assign SAXIHP0AWBURST_in[0] = (SAXIHP0AWBURST[0] !== 1'bz) && SAXIHP0AWBURST_delay[0]; // rv 0 + assign SAXIHP0AWBURST_in[1] = (SAXIHP0AWBURST[1] !== 1'bz) && SAXIHP0AWBURST_delay[1]; // rv 0 + assign SAXIHP0AWCACHE_in[0] = (SAXIHP0AWCACHE[0] !== 1'bz) && SAXIHP0AWCACHE_delay[0]; // rv 0 + assign SAXIHP0AWCACHE_in[1] = (SAXIHP0AWCACHE[1] !== 1'bz) && SAXIHP0AWCACHE_delay[1]; // rv 0 + assign SAXIHP0AWCACHE_in[2] = (SAXIHP0AWCACHE[2] !== 1'bz) && SAXIHP0AWCACHE_delay[2]; // rv 0 + assign SAXIHP0AWCACHE_in[3] = (SAXIHP0AWCACHE[3] !== 1'bz) && SAXIHP0AWCACHE_delay[3]; // rv 0 + assign SAXIHP0AWID_in[0] = (SAXIHP0AWID[0] !== 1'bz) && SAXIHP0AWID_delay[0]; // rv 0 + assign SAXIHP0AWID_in[1] = (SAXIHP0AWID[1] !== 1'bz) && SAXIHP0AWID_delay[1]; // rv 0 + assign SAXIHP0AWID_in[2] = (SAXIHP0AWID[2] !== 1'bz) && SAXIHP0AWID_delay[2]; // rv 0 + assign SAXIHP0AWID_in[3] = (SAXIHP0AWID[3] !== 1'bz) && SAXIHP0AWID_delay[3]; // rv 0 + assign SAXIHP0AWID_in[4] = (SAXIHP0AWID[4] !== 1'bz) && SAXIHP0AWID_delay[4]; // rv 0 + assign SAXIHP0AWID_in[5] = (SAXIHP0AWID[5] !== 1'bz) && SAXIHP0AWID_delay[5]; // rv 0 + assign SAXIHP0AWLEN_in[0] = (SAXIHP0AWLEN[0] !== 1'bz) && SAXIHP0AWLEN_delay[0]; // rv 0 + assign SAXIHP0AWLEN_in[1] = (SAXIHP0AWLEN[1] !== 1'bz) && SAXIHP0AWLEN_delay[1]; // rv 0 + assign SAXIHP0AWLEN_in[2] = (SAXIHP0AWLEN[2] !== 1'bz) && SAXIHP0AWLEN_delay[2]; // rv 0 + assign SAXIHP0AWLEN_in[3] = (SAXIHP0AWLEN[3] !== 1'bz) && SAXIHP0AWLEN_delay[3]; // rv 0 + assign SAXIHP0AWLOCK_in[0] = (SAXIHP0AWLOCK[0] !== 1'bz) && SAXIHP0AWLOCK_delay[0]; // rv 0 + assign SAXIHP0AWLOCK_in[1] = (SAXIHP0AWLOCK[1] !== 1'bz) && SAXIHP0AWLOCK_delay[1]; // rv 0 + assign SAXIHP0AWPROT_in[0] = (SAXIHP0AWPROT[0] !== 1'bz) && SAXIHP0AWPROT_delay[0]; // rv 0 + assign SAXIHP0AWPROT_in[1] = (SAXIHP0AWPROT[1] !== 1'bz) && SAXIHP0AWPROT_delay[1]; // rv 0 + assign SAXIHP0AWPROT_in[2] = (SAXIHP0AWPROT[2] !== 1'bz) && SAXIHP0AWPROT_delay[2]; // rv 0 + assign SAXIHP0AWQOS_in[0] = (SAXIHP0AWQOS[0] !== 1'bz) && SAXIHP0AWQOS_delay[0]; // rv 0 + assign SAXIHP0AWQOS_in[1] = (SAXIHP0AWQOS[1] !== 1'bz) && SAXIHP0AWQOS_delay[1]; // rv 0 + assign SAXIHP0AWQOS_in[2] = (SAXIHP0AWQOS[2] !== 1'bz) && SAXIHP0AWQOS_delay[2]; // rv 0 + assign SAXIHP0AWQOS_in[3] = (SAXIHP0AWQOS[3] !== 1'bz) && SAXIHP0AWQOS_delay[3]; // rv 0 + assign SAXIHP0AWSIZE_in[0] = (SAXIHP0AWSIZE[0] !== 1'bz) && SAXIHP0AWSIZE_delay[0]; // rv 0 + assign SAXIHP0AWSIZE_in[1] = (SAXIHP0AWSIZE[1] !== 1'bz) && SAXIHP0AWSIZE_delay[1]; // rv 0 + assign SAXIHP0AWVALID_in = (SAXIHP0AWVALID !== 1'bz) && SAXIHP0AWVALID_delay; // rv 0 + assign SAXIHP0BREADY_in = (SAXIHP0BREADY !== 1'bz) && SAXIHP0BREADY_delay; // rv 0 + assign SAXIHP0RREADY_in = (SAXIHP0RREADY !== 1'bz) && SAXIHP0RREADY_delay; // rv 0 + assign SAXIHP0WDATA_in[0] = (SAXIHP0WDATA[0] !== 1'bz) && SAXIHP0WDATA_delay[0]; // rv 0 + assign SAXIHP0WDATA_in[10] = (SAXIHP0WDATA[10] !== 1'bz) && SAXIHP0WDATA_delay[10]; // rv 0 + assign SAXIHP0WDATA_in[11] = (SAXIHP0WDATA[11] !== 1'bz) && SAXIHP0WDATA_delay[11]; // rv 0 + assign SAXIHP0WDATA_in[12] = (SAXIHP0WDATA[12] !== 1'bz) && SAXIHP0WDATA_delay[12]; // rv 0 + assign SAXIHP0WDATA_in[13] = (SAXIHP0WDATA[13] !== 1'bz) && SAXIHP0WDATA_delay[13]; // rv 0 + assign SAXIHP0WDATA_in[14] = (SAXIHP0WDATA[14] !== 1'bz) && SAXIHP0WDATA_delay[14]; // rv 0 + assign SAXIHP0WDATA_in[15] = (SAXIHP0WDATA[15] !== 1'bz) && SAXIHP0WDATA_delay[15]; // rv 0 + assign SAXIHP0WDATA_in[16] = (SAXIHP0WDATA[16] !== 1'bz) && SAXIHP0WDATA_delay[16]; // rv 0 + assign SAXIHP0WDATA_in[17] = (SAXIHP0WDATA[17] !== 1'bz) && SAXIHP0WDATA_delay[17]; // rv 0 + assign SAXIHP0WDATA_in[18] = (SAXIHP0WDATA[18] !== 1'bz) && SAXIHP0WDATA_delay[18]; // rv 0 + assign SAXIHP0WDATA_in[19] = (SAXIHP0WDATA[19] !== 1'bz) && SAXIHP0WDATA_delay[19]; // rv 0 + assign SAXIHP0WDATA_in[1] = (SAXIHP0WDATA[1] !== 1'bz) && SAXIHP0WDATA_delay[1]; // rv 0 + assign SAXIHP0WDATA_in[20] = (SAXIHP0WDATA[20] !== 1'bz) && SAXIHP0WDATA_delay[20]; // rv 0 + assign SAXIHP0WDATA_in[21] = (SAXIHP0WDATA[21] !== 1'bz) && SAXIHP0WDATA_delay[21]; // rv 0 + assign SAXIHP0WDATA_in[22] = (SAXIHP0WDATA[22] !== 1'bz) && SAXIHP0WDATA_delay[22]; // rv 0 + assign SAXIHP0WDATA_in[23] = (SAXIHP0WDATA[23] !== 1'bz) && SAXIHP0WDATA_delay[23]; // rv 0 + assign SAXIHP0WDATA_in[24] = (SAXIHP0WDATA[24] !== 1'bz) && SAXIHP0WDATA_delay[24]; // rv 0 + assign SAXIHP0WDATA_in[25] = (SAXIHP0WDATA[25] !== 1'bz) && SAXIHP0WDATA_delay[25]; // rv 0 + assign SAXIHP0WDATA_in[26] = (SAXIHP0WDATA[26] !== 1'bz) && SAXIHP0WDATA_delay[26]; // rv 0 + assign SAXIHP0WDATA_in[27] = (SAXIHP0WDATA[27] !== 1'bz) && SAXIHP0WDATA_delay[27]; // rv 0 + assign SAXIHP0WDATA_in[28] = (SAXIHP0WDATA[28] !== 1'bz) && SAXIHP0WDATA_delay[28]; // rv 0 + assign SAXIHP0WDATA_in[29] = (SAXIHP0WDATA[29] !== 1'bz) && SAXIHP0WDATA_delay[29]; // rv 0 + assign SAXIHP0WDATA_in[2] = (SAXIHP0WDATA[2] !== 1'bz) && SAXIHP0WDATA_delay[2]; // rv 0 + assign SAXIHP0WDATA_in[30] = (SAXIHP0WDATA[30] !== 1'bz) && SAXIHP0WDATA_delay[30]; // rv 0 + assign SAXIHP0WDATA_in[31] = (SAXIHP0WDATA[31] !== 1'bz) && SAXIHP0WDATA_delay[31]; // rv 0 + assign SAXIHP0WDATA_in[32] = (SAXIHP0WDATA[32] !== 1'bz) && SAXIHP0WDATA_delay[32]; // rv 0 + assign SAXIHP0WDATA_in[33] = (SAXIHP0WDATA[33] !== 1'bz) && SAXIHP0WDATA_delay[33]; // rv 0 + assign SAXIHP0WDATA_in[34] = (SAXIHP0WDATA[34] !== 1'bz) && SAXIHP0WDATA_delay[34]; // rv 0 + assign SAXIHP0WDATA_in[35] = (SAXIHP0WDATA[35] !== 1'bz) && SAXIHP0WDATA_delay[35]; // rv 0 + assign SAXIHP0WDATA_in[36] = (SAXIHP0WDATA[36] !== 1'bz) && SAXIHP0WDATA_delay[36]; // rv 0 + assign SAXIHP0WDATA_in[37] = (SAXIHP0WDATA[37] !== 1'bz) && SAXIHP0WDATA_delay[37]; // rv 0 + assign SAXIHP0WDATA_in[38] = (SAXIHP0WDATA[38] !== 1'bz) && SAXIHP0WDATA_delay[38]; // rv 0 + assign SAXIHP0WDATA_in[39] = (SAXIHP0WDATA[39] !== 1'bz) && SAXIHP0WDATA_delay[39]; // rv 0 + assign SAXIHP0WDATA_in[3] = (SAXIHP0WDATA[3] !== 1'bz) && SAXIHP0WDATA_delay[3]; // rv 0 + assign SAXIHP0WDATA_in[40] = (SAXIHP0WDATA[40] !== 1'bz) && SAXIHP0WDATA_delay[40]; // rv 0 + assign SAXIHP0WDATA_in[41] = (SAXIHP0WDATA[41] !== 1'bz) && SAXIHP0WDATA_delay[41]; // rv 0 + assign SAXIHP0WDATA_in[42] = (SAXIHP0WDATA[42] !== 1'bz) && SAXIHP0WDATA_delay[42]; // rv 0 + assign SAXIHP0WDATA_in[43] = (SAXIHP0WDATA[43] !== 1'bz) && SAXIHP0WDATA_delay[43]; // rv 0 + assign SAXIHP0WDATA_in[44] = (SAXIHP0WDATA[44] !== 1'bz) && SAXIHP0WDATA_delay[44]; // rv 0 + assign SAXIHP0WDATA_in[45] = (SAXIHP0WDATA[45] !== 1'bz) && SAXIHP0WDATA_delay[45]; // rv 0 + assign SAXIHP0WDATA_in[46] = (SAXIHP0WDATA[46] !== 1'bz) && SAXIHP0WDATA_delay[46]; // rv 0 + assign SAXIHP0WDATA_in[47] = (SAXIHP0WDATA[47] !== 1'bz) && SAXIHP0WDATA_delay[47]; // rv 0 + assign SAXIHP0WDATA_in[48] = (SAXIHP0WDATA[48] !== 1'bz) && SAXIHP0WDATA_delay[48]; // rv 0 + assign SAXIHP0WDATA_in[49] = (SAXIHP0WDATA[49] !== 1'bz) && SAXIHP0WDATA_delay[49]; // rv 0 + assign SAXIHP0WDATA_in[4] = (SAXIHP0WDATA[4] !== 1'bz) && SAXIHP0WDATA_delay[4]; // rv 0 + assign SAXIHP0WDATA_in[50] = (SAXIHP0WDATA[50] !== 1'bz) && SAXIHP0WDATA_delay[50]; // rv 0 + assign SAXIHP0WDATA_in[51] = (SAXIHP0WDATA[51] !== 1'bz) && SAXIHP0WDATA_delay[51]; // rv 0 + assign SAXIHP0WDATA_in[52] = (SAXIHP0WDATA[52] !== 1'bz) && SAXIHP0WDATA_delay[52]; // rv 0 + assign SAXIHP0WDATA_in[53] = (SAXIHP0WDATA[53] !== 1'bz) && SAXIHP0WDATA_delay[53]; // rv 0 + assign SAXIHP0WDATA_in[54] = (SAXIHP0WDATA[54] !== 1'bz) && SAXIHP0WDATA_delay[54]; // rv 0 + assign SAXIHP0WDATA_in[55] = (SAXIHP0WDATA[55] !== 1'bz) && SAXIHP0WDATA_delay[55]; // rv 0 + assign SAXIHP0WDATA_in[56] = (SAXIHP0WDATA[56] !== 1'bz) && SAXIHP0WDATA_delay[56]; // rv 0 + assign SAXIHP0WDATA_in[57] = (SAXIHP0WDATA[57] !== 1'bz) && SAXIHP0WDATA_delay[57]; // rv 0 + assign SAXIHP0WDATA_in[58] = (SAXIHP0WDATA[58] !== 1'bz) && SAXIHP0WDATA_delay[58]; // rv 0 + assign SAXIHP0WDATA_in[59] = (SAXIHP0WDATA[59] !== 1'bz) && SAXIHP0WDATA_delay[59]; // rv 0 + assign SAXIHP0WDATA_in[5] = (SAXIHP0WDATA[5] !== 1'bz) && SAXIHP0WDATA_delay[5]; // rv 0 + assign SAXIHP0WDATA_in[60] = (SAXIHP0WDATA[60] !== 1'bz) && SAXIHP0WDATA_delay[60]; // rv 0 + assign SAXIHP0WDATA_in[61] = (SAXIHP0WDATA[61] !== 1'bz) && SAXIHP0WDATA_delay[61]; // rv 0 + assign SAXIHP0WDATA_in[62] = (SAXIHP0WDATA[62] !== 1'bz) && SAXIHP0WDATA_delay[62]; // rv 0 + assign SAXIHP0WDATA_in[63] = (SAXIHP0WDATA[63] !== 1'bz) && SAXIHP0WDATA_delay[63]; // rv 0 + assign SAXIHP0WDATA_in[6] = (SAXIHP0WDATA[6] !== 1'bz) && SAXIHP0WDATA_delay[6]; // rv 0 + assign SAXIHP0WDATA_in[7] = (SAXIHP0WDATA[7] !== 1'bz) && SAXIHP0WDATA_delay[7]; // rv 0 + assign SAXIHP0WDATA_in[8] = (SAXIHP0WDATA[8] !== 1'bz) && SAXIHP0WDATA_delay[8]; // rv 0 + assign SAXIHP0WDATA_in[9] = (SAXIHP0WDATA[9] !== 1'bz) && SAXIHP0WDATA_delay[9]; // rv 0 + assign SAXIHP0WID_in[0] = (SAXIHP0WID[0] !== 1'bz) && SAXIHP0WID_delay[0]; // rv 0 + assign SAXIHP0WID_in[1] = (SAXIHP0WID[1] !== 1'bz) && SAXIHP0WID_delay[1]; // rv 0 + assign SAXIHP0WID_in[2] = (SAXIHP0WID[2] !== 1'bz) && SAXIHP0WID_delay[2]; // rv 0 + assign SAXIHP0WID_in[3] = (SAXIHP0WID[3] !== 1'bz) && SAXIHP0WID_delay[3]; // rv 0 + assign SAXIHP0WID_in[4] = (SAXIHP0WID[4] !== 1'bz) && SAXIHP0WID_delay[4]; // rv 0 + assign SAXIHP0WID_in[5] = (SAXIHP0WID[5] !== 1'bz) && SAXIHP0WID_delay[5]; // rv 0 + assign SAXIHP0WLAST_in = (SAXIHP0WLAST !== 1'bz) && SAXIHP0WLAST_delay; // rv 0 + assign SAXIHP0WSTRB_in[0] = (SAXIHP0WSTRB[0] !== 1'bz) && SAXIHP0WSTRB_delay[0]; // rv 0 + assign SAXIHP0WSTRB_in[1] = (SAXIHP0WSTRB[1] !== 1'bz) && SAXIHP0WSTRB_delay[1]; // rv 0 + assign SAXIHP0WSTRB_in[2] = (SAXIHP0WSTRB[2] !== 1'bz) && SAXIHP0WSTRB_delay[2]; // rv 0 + assign SAXIHP0WSTRB_in[3] = (SAXIHP0WSTRB[3] !== 1'bz) && SAXIHP0WSTRB_delay[3]; // rv 0 + assign SAXIHP0WSTRB_in[4] = (SAXIHP0WSTRB[4] !== 1'bz) && SAXIHP0WSTRB_delay[4]; // rv 0 + assign SAXIHP0WSTRB_in[5] = (SAXIHP0WSTRB[5] !== 1'bz) && SAXIHP0WSTRB_delay[5]; // rv 0 + assign SAXIHP0WSTRB_in[6] = (SAXIHP0WSTRB[6] !== 1'bz) && SAXIHP0WSTRB_delay[6]; // rv 0 + assign SAXIHP0WSTRB_in[7] = (SAXIHP0WSTRB[7] !== 1'bz) && SAXIHP0WSTRB_delay[7]; // rv 0 + assign SAXIHP0WVALID_in = (SAXIHP0WVALID !== 1'bz) && SAXIHP0WVALID_delay; // rv 0 + assign SAXIHP1ACLK_in = (SAXIHP1ACLK !== 1'bz) && SAXIHP1ACLK_delay; // rv 0 + assign SAXIHP1ARADDR_in[0] = (SAXIHP1ARADDR[0] !== 1'bz) && SAXIHP1ARADDR_delay[0]; // rv 0 + assign SAXIHP1ARADDR_in[10] = (SAXIHP1ARADDR[10] !== 1'bz) && SAXIHP1ARADDR_delay[10]; // rv 0 + assign SAXIHP1ARADDR_in[11] = (SAXIHP1ARADDR[11] !== 1'bz) && SAXIHP1ARADDR_delay[11]; // rv 0 + assign SAXIHP1ARADDR_in[12] = (SAXIHP1ARADDR[12] !== 1'bz) && SAXIHP1ARADDR_delay[12]; // rv 0 + assign SAXIHP1ARADDR_in[13] = (SAXIHP1ARADDR[13] !== 1'bz) && SAXIHP1ARADDR_delay[13]; // rv 0 + assign SAXIHP1ARADDR_in[14] = (SAXIHP1ARADDR[14] !== 1'bz) && SAXIHP1ARADDR_delay[14]; // rv 0 + assign SAXIHP1ARADDR_in[15] = (SAXIHP1ARADDR[15] !== 1'bz) && SAXIHP1ARADDR_delay[15]; // rv 0 + assign SAXIHP1ARADDR_in[16] = (SAXIHP1ARADDR[16] !== 1'bz) && SAXIHP1ARADDR_delay[16]; // rv 0 + assign SAXIHP1ARADDR_in[17] = (SAXIHP1ARADDR[17] !== 1'bz) && SAXIHP1ARADDR_delay[17]; // rv 0 + assign SAXIHP1ARADDR_in[18] = (SAXIHP1ARADDR[18] !== 1'bz) && SAXIHP1ARADDR_delay[18]; // rv 0 + assign SAXIHP1ARADDR_in[19] = (SAXIHP1ARADDR[19] !== 1'bz) && SAXIHP1ARADDR_delay[19]; // rv 0 + assign SAXIHP1ARADDR_in[1] = (SAXIHP1ARADDR[1] !== 1'bz) && SAXIHP1ARADDR_delay[1]; // rv 0 + assign SAXIHP1ARADDR_in[20] = (SAXIHP1ARADDR[20] !== 1'bz) && SAXIHP1ARADDR_delay[20]; // rv 0 + assign SAXIHP1ARADDR_in[21] = (SAXIHP1ARADDR[21] !== 1'bz) && SAXIHP1ARADDR_delay[21]; // rv 0 + assign SAXIHP1ARADDR_in[22] = (SAXIHP1ARADDR[22] !== 1'bz) && SAXIHP1ARADDR_delay[22]; // rv 0 + assign SAXIHP1ARADDR_in[23] = (SAXIHP1ARADDR[23] !== 1'bz) && SAXIHP1ARADDR_delay[23]; // rv 0 + assign SAXIHP1ARADDR_in[24] = (SAXIHP1ARADDR[24] !== 1'bz) && SAXIHP1ARADDR_delay[24]; // rv 0 + assign SAXIHP1ARADDR_in[25] = (SAXIHP1ARADDR[25] !== 1'bz) && SAXIHP1ARADDR_delay[25]; // rv 0 + assign SAXIHP1ARADDR_in[26] = (SAXIHP1ARADDR[26] !== 1'bz) && SAXIHP1ARADDR_delay[26]; // rv 0 + assign SAXIHP1ARADDR_in[27] = (SAXIHP1ARADDR[27] !== 1'bz) && SAXIHP1ARADDR_delay[27]; // rv 0 + assign SAXIHP1ARADDR_in[28] = (SAXIHP1ARADDR[28] !== 1'bz) && SAXIHP1ARADDR_delay[28]; // rv 0 + assign SAXIHP1ARADDR_in[29] = (SAXIHP1ARADDR[29] !== 1'bz) && SAXIHP1ARADDR_delay[29]; // rv 0 + assign SAXIHP1ARADDR_in[2] = (SAXIHP1ARADDR[2] !== 1'bz) && SAXIHP1ARADDR_delay[2]; // rv 0 + assign SAXIHP1ARADDR_in[30] = (SAXIHP1ARADDR[30] !== 1'bz) && SAXIHP1ARADDR_delay[30]; // rv 0 + assign SAXIHP1ARADDR_in[31] = (SAXIHP1ARADDR[31] !== 1'bz) && SAXIHP1ARADDR_delay[31]; // rv 0 + assign SAXIHP1ARADDR_in[3] = (SAXIHP1ARADDR[3] !== 1'bz) && SAXIHP1ARADDR_delay[3]; // rv 0 + assign SAXIHP1ARADDR_in[4] = (SAXIHP1ARADDR[4] !== 1'bz) && SAXIHP1ARADDR_delay[4]; // rv 0 + assign SAXIHP1ARADDR_in[5] = (SAXIHP1ARADDR[5] !== 1'bz) && SAXIHP1ARADDR_delay[5]; // rv 0 + assign SAXIHP1ARADDR_in[6] = (SAXIHP1ARADDR[6] !== 1'bz) && SAXIHP1ARADDR_delay[6]; // rv 0 + assign SAXIHP1ARADDR_in[7] = (SAXIHP1ARADDR[7] !== 1'bz) && SAXIHP1ARADDR_delay[7]; // rv 0 + assign SAXIHP1ARADDR_in[8] = (SAXIHP1ARADDR[8] !== 1'bz) && SAXIHP1ARADDR_delay[8]; // rv 0 + assign SAXIHP1ARADDR_in[9] = (SAXIHP1ARADDR[9] !== 1'bz) && SAXIHP1ARADDR_delay[9]; // rv 0 + assign SAXIHP1ARBURST_in[0] = (SAXIHP1ARBURST[0] !== 1'bz) && SAXIHP1ARBURST_delay[0]; // rv 0 + assign SAXIHP1ARBURST_in[1] = (SAXIHP1ARBURST[1] !== 1'bz) && SAXIHP1ARBURST_delay[1]; // rv 0 + assign SAXIHP1ARCACHE_in[0] = (SAXIHP1ARCACHE[0] !== 1'bz) && SAXIHP1ARCACHE_delay[0]; // rv 0 + assign SAXIHP1ARCACHE_in[1] = (SAXIHP1ARCACHE[1] !== 1'bz) && SAXIHP1ARCACHE_delay[1]; // rv 0 + assign SAXIHP1ARCACHE_in[2] = (SAXIHP1ARCACHE[2] !== 1'bz) && SAXIHP1ARCACHE_delay[2]; // rv 0 + assign SAXIHP1ARCACHE_in[3] = (SAXIHP1ARCACHE[3] !== 1'bz) && SAXIHP1ARCACHE_delay[3]; // rv 0 + assign SAXIHP1ARID_in[0] = (SAXIHP1ARID[0] !== 1'bz) && SAXIHP1ARID_delay[0]; // rv 0 + assign SAXIHP1ARID_in[1] = (SAXIHP1ARID[1] !== 1'bz) && SAXIHP1ARID_delay[1]; // rv 0 + assign SAXIHP1ARID_in[2] = (SAXIHP1ARID[2] !== 1'bz) && SAXIHP1ARID_delay[2]; // rv 0 + assign SAXIHP1ARID_in[3] = (SAXIHP1ARID[3] !== 1'bz) && SAXIHP1ARID_delay[3]; // rv 0 + assign SAXIHP1ARID_in[4] = (SAXIHP1ARID[4] !== 1'bz) && SAXIHP1ARID_delay[4]; // rv 0 + assign SAXIHP1ARID_in[5] = (SAXIHP1ARID[5] !== 1'bz) && SAXIHP1ARID_delay[5]; // rv 0 + assign SAXIHP1ARLEN_in[0] = (SAXIHP1ARLEN[0] !== 1'bz) && SAXIHP1ARLEN_delay[0]; // rv 0 + assign SAXIHP1ARLEN_in[1] = (SAXIHP1ARLEN[1] !== 1'bz) && SAXIHP1ARLEN_delay[1]; // rv 0 + assign SAXIHP1ARLEN_in[2] = (SAXIHP1ARLEN[2] !== 1'bz) && SAXIHP1ARLEN_delay[2]; // rv 0 + assign SAXIHP1ARLEN_in[3] = (SAXIHP1ARLEN[3] !== 1'bz) && SAXIHP1ARLEN_delay[3]; // rv 0 + assign SAXIHP1ARLOCK_in[0] = (SAXIHP1ARLOCK[0] !== 1'bz) && SAXIHP1ARLOCK_delay[0]; // rv 0 + assign SAXIHP1ARLOCK_in[1] = (SAXIHP1ARLOCK[1] !== 1'bz) && SAXIHP1ARLOCK_delay[1]; // rv 0 + assign SAXIHP1ARPROT_in[0] = (SAXIHP1ARPROT[0] !== 1'bz) && SAXIHP1ARPROT_delay[0]; // rv 0 + assign SAXIHP1ARPROT_in[1] = (SAXIHP1ARPROT[1] !== 1'bz) && SAXIHP1ARPROT_delay[1]; // rv 0 + assign SAXIHP1ARPROT_in[2] = (SAXIHP1ARPROT[2] !== 1'bz) && SAXIHP1ARPROT_delay[2]; // rv 0 + assign SAXIHP1ARQOS_in[0] = (SAXIHP1ARQOS[0] !== 1'bz) && SAXIHP1ARQOS_delay[0]; // rv 0 + assign SAXIHP1ARQOS_in[1] = (SAXIHP1ARQOS[1] !== 1'bz) && SAXIHP1ARQOS_delay[1]; // rv 0 + assign SAXIHP1ARQOS_in[2] = (SAXIHP1ARQOS[2] !== 1'bz) && SAXIHP1ARQOS_delay[2]; // rv 0 + assign SAXIHP1ARQOS_in[3] = (SAXIHP1ARQOS[3] !== 1'bz) && SAXIHP1ARQOS_delay[3]; // rv 0 + assign SAXIHP1ARSIZE_in[0] = (SAXIHP1ARSIZE[0] !== 1'bz) && SAXIHP1ARSIZE_delay[0]; // rv 0 + assign SAXIHP1ARSIZE_in[1] = (SAXIHP1ARSIZE[1] !== 1'bz) && SAXIHP1ARSIZE_delay[1]; // rv 0 + assign SAXIHP1ARVALID_in = (SAXIHP1ARVALID !== 1'bz) && SAXIHP1ARVALID_delay; // rv 0 + assign SAXIHP1AWADDR_in[0] = (SAXIHP1AWADDR[0] !== 1'bz) && SAXIHP1AWADDR_delay[0]; // rv 0 + assign SAXIHP1AWADDR_in[10] = (SAXIHP1AWADDR[10] !== 1'bz) && SAXIHP1AWADDR_delay[10]; // rv 0 + assign SAXIHP1AWADDR_in[11] = (SAXIHP1AWADDR[11] !== 1'bz) && SAXIHP1AWADDR_delay[11]; // rv 0 + assign SAXIHP1AWADDR_in[12] = (SAXIHP1AWADDR[12] !== 1'bz) && SAXIHP1AWADDR_delay[12]; // rv 0 + assign SAXIHP1AWADDR_in[13] = (SAXIHP1AWADDR[13] !== 1'bz) && SAXIHP1AWADDR_delay[13]; // rv 0 + assign SAXIHP1AWADDR_in[14] = (SAXIHP1AWADDR[14] !== 1'bz) && SAXIHP1AWADDR_delay[14]; // rv 0 + assign SAXIHP1AWADDR_in[15] = (SAXIHP1AWADDR[15] !== 1'bz) && SAXIHP1AWADDR_delay[15]; // rv 0 + assign SAXIHP1AWADDR_in[16] = (SAXIHP1AWADDR[16] !== 1'bz) && SAXIHP1AWADDR_delay[16]; // rv 0 + assign SAXIHP1AWADDR_in[17] = (SAXIHP1AWADDR[17] !== 1'bz) && SAXIHP1AWADDR_delay[17]; // rv 0 + assign SAXIHP1AWADDR_in[18] = (SAXIHP1AWADDR[18] !== 1'bz) && SAXIHP1AWADDR_delay[18]; // rv 0 + assign SAXIHP1AWADDR_in[19] = (SAXIHP1AWADDR[19] !== 1'bz) && SAXIHP1AWADDR_delay[19]; // rv 0 + assign SAXIHP1AWADDR_in[1] = (SAXIHP1AWADDR[1] !== 1'bz) && SAXIHP1AWADDR_delay[1]; // rv 0 + assign SAXIHP1AWADDR_in[20] = (SAXIHP1AWADDR[20] !== 1'bz) && SAXIHP1AWADDR_delay[20]; // rv 0 + assign SAXIHP1AWADDR_in[21] = (SAXIHP1AWADDR[21] !== 1'bz) && SAXIHP1AWADDR_delay[21]; // rv 0 + assign SAXIHP1AWADDR_in[22] = (SAXIHP1AWADDR[22] !== 1'bz) && SAXIHP1AWADDR_delay[22]; // rv 0 + assign SAXIHP1AWADDR_in[23] = (SAXIHP1AWADDR[23] !== 1'bz) && SAXIHP1AWADDR_delay[23]; // rv 0 + assign SAXIHP1AWADDR_in[24] = (SAXIHP1AWADDR[24] !== 1'bz) && SAXIHP1AWADDR_delay[24]; // rv 0 + assign SAXIHP1AWADDR_in[25] = (SAXIHP1AWADDR[25] !== 1'bz) && SAXIHP1AWADDR_delay[25]; // rv 0 + assign SAXIHP1AWADDR_in[26] = (SAXIHP1AWADDR[26] !== 1'bz) && SAXIHP1AWADDR_delay[26]; // rv 0 + assign SAXIHP1AWADDR_in[27] = (SAXIHP1AWADDR[27] !== 1'bz) && SAXIHP1AWADDR_delay[27]; // rv 0 + assign SAXIHP1AWADDR_in[28] = (SAXIHP1AWADDR[28] !== 1'bz) && SAXIHP1AWADDR_delay[28]; // rv 0 + assign SAXIHP1AWADDR_in[29] = (SAXIHP1AWADDR[29] !== 1'bz) && SAXIHP1AWADDR_delay[29]; // rv 0 + assign SAXIHP1AWADDR_in[2] = (SAXIHP1AWADDR[2] !== 1'bz) && SAXIHP1AWADDR_delay[2]; // rv 0 + assign SAXIHP1AWADDR_in[30] = (SAXIHP1AWADDR[30] !== 1'bz) && SAXIHP1AWADDR_delay[30]; // rv 0 + assign SAXIHP1AWADDR_in[31] = (SAXIHP1AWADDR[31] !== 1'bz) && SAXIHP1AWADDR_delay[31]; // rv 0 + assign SAXIHP1AWADDR_in[3] = (SAXIHP1AWADDR[3] !== 1'bz) && SAXIHP1AWADDR_delay[3]; // rv 0 + assign SAXIHP1AWADDR_in[4] = (SAXIHP1AWADDR[4] !== 1'bz) && SAXIHP1AWADDR_delay[4]; // rv 0 + assign SAXIHP1AWADDR_in[5] = (SAXIHP1AWADDR[5] !== 1'bz) && SAXIHP1AWADDR_delay[5]; // rv 0 + assign SAXIHP1AWADDR_in[6] = (SAXIHP1AWADDR[6] !== 1'bz) && SAXIHP1AWADDR_delay[6]; // rv 0 + assign SAXIHP1AWADDR_in[7] = (SAXIHP1AWADDR[7] !== 1'bz) && SAXIHP1AWADDR_delay[7]; // rv 0 + assign SAXIHP1AWADDR_in[8] = (SAXIHP1AWADDR[8] !== 1'bz) && SAXIHP1AWADDR_delay[8]; // rv 0 + assign SAXIHP1AWADDR_in[9] = (SAXIHP1AWADDR[9] !== 1'bz) && SAXIHP1AWADDR_delay[9]; // rv 0 + assign SAXIHP1AWBURST_in[0] = (SAXIHP1AWBURST[0] !== 1'bz) && SAXIHP1AWBURST_delay[0]; // rv 0 + assign SAXIHP1AWBURST_in[1] = (SAXIHP1AWBURST[1] !== 1'bz) && SAXIHP1AWBURST_delay[1]; // rv 0 + assign SAXIHP1AWCACHE_in[0] = (SAXIHP1AWCACHE[0] !== 1'bz) && SAXIHP1AWCACHE_delay[0]; // rv 0 + assign SAXIHP1AWCACHE_in[1] = (SAXIHP1AWCACHE[1] !== 1'bz) && SAXIHP1AWCACHE_delay[1]; // rv 0 + assign SAXIHP1AWCACHE_in[2] = (SAXIHP1AWCACHE[2] !== 1'bz) && SAXIHP1AWCACHE_delay[2]; // rv 0 + assign SAXIHP1AWCACHE_in[3] = (SAXIHP1AWCACHE[3] !== 1'bz) && SAXIHP1AWCACHE_delay[3]; // rv 0 + assign SAXIHP1AWID_in[0] = (SAXIHP1AWID[0] !== 1'bz) && SAXIHP1AWID_delay[0]; // rv 0 + assign SAXIHP1AWID_in[1] = (SAXIHP1AWID[1] !== 1'bz) && SAXIHP1AWID_delay[1]; // rv 0 + assign SAXIHP1AWID_in[2] = (SAXIHP1AWID[2] !== 1'bz) && SAXIHP1AWID_delay[2]; // rv 0 + assign SAXIHP1AWID_in[3] = (SAXIHP1AWID[3] !== 1'bz) && SAXIHP1AWID_delay[3]; // rv 0 + assign SAXIHP1AWID_in[4] = (SAXIHP1AWID[4] !== 1'bz) && SAXIHP1AWID_delay[4]; // rv 0 + assign SAXIHP1AWID_in[5] = (SAXIHP1AWID[5] !== 1'bz) && SAXIHP1AWID_delay[5]; // rv 0 + assign SAXIHP1AWLEN_in[0] = (SAXIHP1AWLEN[0] !== 1'bz) && SAXIHP1AWLEN_delay[0]; // rv 0 + assign SAXIHP1AWLEN_in[1] = (SAXIHP1AWLEN[1] !== 1'bz) && SAXIHP1AWLEN_delay[1]; // rv 0 + assign SAXIHP1AWLEN_in[2] = (SAXIHP1AWLEN[2] !== 1'bz) && SAXIHP1AWLEN_delay[2]; // rv 0 + assign SAXIHP1AWLEN_in[3] = (SAXIHP1AWLEN[3] !== 1'bz) && SAXIHP1AWLEN_delay[3]; // rv 0 + assign SAXIHP1AWLOCK_in[0] = (SAXIHP1AWLOCK[0] !== 1'bz) && SAXIHP1AWLOCK_delay[0]; // rv 0 + assign SAXIHP1AWLOCK_in[1] = (SAXIHP1AWLOCK[1] !== 1'bz) && SAXIHP1AWLOCK_delay[1]; // rv 0 + assign SAXIHP1AWPROT_in[0] = (SAXIHP1AWPROT[0] !== 1'bz) && SAXIHP1AWPROT_delay[0]; // rv 0 + assign SAXIHP1AWPROT_in[1] = (SAXIHP1AWPROT[1] !== 1'bz) && SAXIHP1AWPROT_delay[1]; // rv 0 + assign SAXIHP1AWPROT_in[2] = (SAXIHP1AWPROT[2] !== 1'bz) && SAXIHP1AWPROT_delay[2]; // rv 0 + assign SAXIHP1AWQOS_in[0] = (SAXIHP1AWQOS[0] !== 1'bz) && SAXIHP1AWQOS_delay[0]; // rv 0 + assign SAXIHP1AWQOS_in[1] = (SAXIHP1AWQOS[1] !== 1'bz) && SAXIHP1AWQOS_delay[1]; // rv 0 + assign SAXIHP1AWQOS_in[2] = (SAXIHP1AWQOS[2] !== 1'bz) && SAXIHP1AWQOS_delay[2]; // rv 0 + assign SAXIHP1AWQOS_in[3] = (SAXIHP1AWQOS[3] !== 1'bz) && SAXIHP1AWQOS_delay[3]; // rv 0 + assign SAXIHP1AWSIZE_in[0] = (SAXIHP1AWSIZE[0] !== 1'bz) && SAXIHP1AWSIZE_delay[0]; // rv 0 + assign SAXIHP1AWSIZE_in[1] = (SAXIHP1AWSIZE[1] !== 1'bz) && SAXIHP1AWSIZE_delay[1]; // rv 0 + assign SAXIHP1AWVALID_in = (SAXIHP1AWVALID !== 1'bz) && SAXIHP1AWVALID_delay; // rv 0 + assign SAXIHP1BREADY_in = (SAXIHP1BREADY !== 1'bz) && SAXIHP1BREADY_delay; // rv 0 + assign SAXIHP1RREADY_in = (SAXIHP1RREADY !== 1'bz) && SAXIHP1RREADY_delay; // rv 0 + assign SAXIHP1WDATA_in[0] = (SAXIHP1WDATA[0] !== 1'bz) && SAXIHP1WDATA_delay[0]; // rv 0 + assign SAXIHP1WDATA_in[10] = (SAXIHP1WDATA[10] !== 1'bz) && SAXIHP1WDATA_delay[10]; // rv 0 + assign SAXIHP1WDATA_in[11] = (SAXIHP1WDATA[11] !== 1'bz) && SAXIHP1WDATA_delay[11]; // rv 0 + assign SAXIHP1WDATA_in[12] = (SAXIHP1WDATA[12] !== 1'bz) && SAXIHP1WDATA_delay[12]; // rv 0 + assign SAXIHP1WDATA_in[13] = (SAXIHP1WDATA[13] !== 1'bz) && SAXIHP1WDATA_delay[13]; // rv 0 + assign SAXIHP1WDATA_in[14] = (SAXIHP1WDATA[14] !== 1'bz) && SAXIHP1WDATA_delay[14]; // rv 0 + assign SAXIHP1WDATA_in[15] = (SAXIHP1WDATA[15] !== 1'bz) && SAXIHP1WDATA_delay[15]; // rv 0 + assign SAXIHP1WDATA_in[16] = (SAXIHP1WDATA[16] !== 1'bz) && SAXIHP1WDATA_delay[16]; // rv 0 + assign SAXIHP1WDATA_in[17] = (SAXIHP1WDATA[17] !== 1'bz) && SAXIHP1WDATA_delay[17]; // rv 0 + assign SAXIHP1WDATA_in[18] = (SAXIHP1WDATA[18] !== 1'bz) && SAXIHP1WDATA_delay[18]; // rv 0 + assign SAXIHP1WDATA_in[19] = (SAXIHP1WDATA[19] !== 1'bz) && SAXIHP1WDATA_delay[19]; // rv 0 + assign SAXIHP1WDATA_in[1] = (SAXIHP1WDATA[1] !== 1'bz) && SAXIHP1WDATA_delay[1]; // rv 0 + assign SAXIHP1WDATA_in[20] = (SAXIHP1WDATA[20] !== 1'bz) && SAXIHP1WDATA_delay[20]; // rv 0 + assign SAXIHP1WDATA_in[21] = (SAXIHP1WDATA[21] !== 1'bz) && SAXIHP1WDATA_delay[21]; // rv 0 + assign SAXIHP1WDATA_in[22] = (SAXIHP1WDATA[22] !== 1'bz) && SAXIHP1WDATA_delay[22]; // rv 0 + assign SAXIHP1WDATA_in[23] = (SAXIHP1WDATA[23] !== 1'bz) && SAXIHP1WDATA_delay[23]; // rv 0 + assign SAXIHP1WDATA_in[24] = (SAXIHP1WDATA[24] !== 1'bz) && SAXIHP1WDATA_delay[24]; // rv 0 + assign SAXIHP1WDATA_in[25] = (SAXIHP1WDATA[25] !== 1'bz) && SAXIHP1WDATA_delay[25]; // rv 0 + assign SAXIHP1WDATA_in[26] = (SAXIHP1WDATA[26] !== 1'bz) && SAXIHP1WDATA_delay[26]; // rv 0 + assign SAXIHP1WDATA_in[27] = (SAXIHP1WDATA[27] !== 1'bz) && SAXIHP1WDATA_delay[27]; // rv 0 + assign SAXIHP1WDATA_in[28] = (SAXIHP1WDATA[28] !== 1'bz) && SAXIHP1WDATA_delay[28]; // rv 0 + assign SAXIHP1WDATA_in[29] = (SAXIHP1WDATA[29] !== 1'bz) && SAXIHP1WDATA_delay[29]; // rv 0 + assign SAXIHP1WDATA_in[2] = (SAXIHP1WDATA[2] !== 1'bz) && SAXIHP1WDATA_delay[2]; // rv 0 + assign SAXIHP1WDATA_in[30] = (SAXIHP1WDATA[30] !== 1'bz) && SAXIHP1WDATA_delay[30]; // rv 0 + assign SAXIHP1WDATA_in[31] = (SAXIHP1WDATA[31] !== 1'bz) && SAXIHP1WDATA_delay[31]; // rv 0 + assign SAXIHP1WDATA_in[32] = (SAXIHP1WDATA[32] !== 1'bz) && SAXIHP1WDATA_delay[32]; // rv 0 + assign SAXIHP1WDATA_in[33] = (SAXIHP1WDATA[33] !== 1'bz) && SAXIHP1WDATA_delay[33]; // rv 0 + assign SAXIHP1WDATA_in[34] = (SAXIHP1WDATA[34] !== 1'bz) && SAXIHP1WDATA_delay[34]; // rv 0 + assign SAXIHP1WDATA_in[35] = (SAXIHP1WDATA[35] !== 1'bz) && SAXIHP1WDATA_delay[35]; // rv 0 + assign SAXIHP1WDATA_in[36] = (SAXIHP1WDATA[36] !== 1'bz) && SAXIHP1WDATA_delay[36]; // rv 0 + assign SAXIHP1WDATA_in[37] = (SAXIHP1WDATA[37] !== 1'bz) && SAXIHP1WDATA_delay[37]; // rv 0 + assign SAXIHP1WDATA_in[38] = (SAXIHP1WDATA[38] !== 1'bz) && SAXIHP1WDATA_delay[38]; // rv 0 + assign SAXIHP1WDATA_in[39] = (SAXIHP1WDATA[39] !== 1'bz) && SAXIHP1WDATA_delay[39]; // rv 0 + assign SAXIHP1WDATA_in[3] = (SAXIHP1WDATA[3] !== 1'bz) && SAXIHP1WDATA_delay[3]; // rv 0 + assign SAXIHP1WDATA_in[40] = (SAXIHP1WDATA[40] !== 1'bz) && SAXIHP1WDATA_delay[40]; // rv 0 + assign SAXIHP1WDATA_in[41] = (SAXIHP1WDATA[41] !== 1'bz) && SAXIHP1WDATA_delay[41]; // rv 0 + assign SAXIHP1WDATA_in[42] = (SAXIHP1WDATA[42] !== 1'bz) && SAXIHP1WDATA_delay[42]; // rv 0 + assign SAXIHP1WDATA_in[43] = (SAXIHP1WDATA[43] !== 1'bz) && SAXIHP1WDATA_delay[43]; // rv 0 + assign SAXIHP1WDATA_in[44] = (SAXIHP1WDATA[44] !== 1'bz) && SAXIHP1WDATA_delay[44]; // rv 0 + assign SAXIHP1WDATA_in[45] = (SAXIHP1WDATA[45] !== 1'bz) && SAXIHP1WDATA_delay[45]; // rv 0 + assign SAXIHP1WDATA_in[46] = (SAXIHP1WDATA[46] !== 1'bz) && SAXIHP1WDATA_delay[46]; // rv 0 + assign SAXIHP1WDATA_in[47] = (SAXIHP1WDATA[47] !== 1'bz) && SAXIHP1WDATA_delay[47]; // rv 0 + assign SAXIHP1WDATA_in[48] = (SAXIHP1WDATA[48] !== 1'bz) && SAXIHP1WDATA_delay[48]; // rv 0 + assign SAXIHP1WDATA_in[49] = (SAXIHP1WDATA[49] !== 1'bz) && SAXIHP1WDATA_delay[49]; // rv 0 + assign SAXIHP1WDATA_in[4] = (SAXIHP1WDATA[4] !== 1'bz) && SAXIHP1WDATA_delay[4]; // rv 0 + assign SAXIHP1WDATA_in[50] = (SAXIHP1WDATA[50] !== 1'bz) && SAXIHP1WDATA_delay[50]; // rv 0 + assign SAXIHP1WDATA_in[51] = (SAXIHP1WDATA[51] !== 1'bz) && SAXIHP1WDATA_delay[51]; // rv 0 + assign SAXIHP1WDATA_in[52] = (SAXIHP1WDATA[52] !== 1'bz) && SAXIHP1WDATA_delay[52]; // rv 0 + assign SAXIHP1WDATA_in[53] = (SAXIHP1WDATA[53] !== 1'bz) && SAXIHP1WDATA_delay[53]; // rv 0 + assign SAXIHP1WDATA_in[54] = (SAXIHP1WDATA[54] !== 1'bz) && SAXIHP1WDATA_delay[54]; // rv 0 + assign SAXIHP1WDATA_in[55] = (SAXIHP1WDATA[55] !== 1'bz) && SAXIHP1WDATA_delay[55]; // rv 0 + assign SAXIHP1WDATA_in[56] = (SAXIHP1WDATA[56] !== 1'bz) && SAXIHP1WDATA_delay[56]; // rv 0 + assign SAXIHP1WDATA_in[57] = (SAXIHP1WDATA[57] !== 1'bz) && SAXIHP1WDATA_delay[57]; // rv 0 + assign SAXIHP1WDATA_in[58] = (SAXIHP1WDATA[58] !== 1'bz) && SAXIHP1WDATA_delay[58]; // rv 0 + assign SAXIHP1WDATA_in[59] = (SAXIHP1WDATA[59] !== 1'bz) && SAXIHP1WDATA_delay[59]; // rv 0 + assign SAXIHP1WDATA_in[5] = (SAXIHP1WDATA[5] !== 1'bz) && SAXIHP1WDATA_delay[5]; // rv 0 + assign SAXIHP1WDATA_in[60] = (SAXIHP1WDATA[60] !== 1'bz) && SAXIHP1WDATA_delay[60]; // rv 0 + assign SAXIHP1WDATA_in[61] = (SAXIHP1WDATA[61] !== 1'bz) && SAXIHP1WDATA_delay[61]; // rv 0 + assign SAXIHP1WDATA_in[62] = (SAXIHP1WDATA[62] !== 1'bz) && SAXIHP1WDATA_delay[62]; // rv 0 + assign SAXIHP1WDATA_in[63] = (SAXIHP1WDATA[63] !== 1'bz) && SAXIHP1WDATA_delay[63]; // rv 0 + assign SAXIHP1WDATA_in[6] = (SAXIHP1WDATA[6] !== 1'bz) && SAXIHP1WDATA_delay[6]; // rv 0 + assign SAXIHP1WDATA_in[7] = (SAXIHP1WDATA[7] !== 1'bz) && SAXIHP1WDATA_delay[7]; // rv 0 + assign SAXIHP1WDATA_in[8] = (SAXIHP1WDATA[8] !== 1'bz) && SAXIHP1WDATA_delay[8]; // rv 0 + assign SAXIHP1WDATA_in[9] = (SAXIHP1WDATA[9] !== 1'bz) && SAXIHP1WDATA_delay[9]; // rv 0 + assign SAXIHP1WID_in[0] = (SAXIHP1WID[0] !== 1'bz) && SAXIHP1WID_delay[0]; // rv 0 + assign SAXIHP1WID_in[1] = (SAXIHP1WID[1] !== 1'bz) && SAXIHP1WID_delay[1]; // rv 0 + assign SAXIHP1WID_in[2] = (SAXIHP1WID[2] !== 1'bz) && SAXIHP1WID_delay[2]; // rv 0 + assign SAXIHP1WID_in[3] = (SAXIHP1WID[3] !== 1'bz) && SAXIHP1WID_delay[3]; // rv 0 + assign SAXIHP1WID_in[4] = (SAXIHP1WID[4] !== 1'bz) && SAXIHP1WID_delay[4]; // rv 0 + assign SAXIHP1WID_in[5] = (SAXIHP1WID[5] !== 1'bz) && SAXIHP1WID_delay[5]; // rv 0 + assign SAXIHP1WLAST_in = (SAXIHP1WLAST !== 1'bz) && SAXIHP1WLAST_delay; // rv 0 + assign SAXIHP1WSTRB_in[0] = (SAXIHP1WSTRB[0] !== 1'bz) && SAXIHP1WSTRB_delay[0]; // rv 0 + assign SAXIHP1WSTRB_in[1] = (SAXIHP1WSTRB[1] !== 1'bz) && SAXIHP1WSTRB_delay[1]; // rv 0 + assign SAXIHP1WSTRB_in[2] = (SAXIHP1WSTRB[2] !== 1'bz) && SAXIHP1WSTRB_delay[2]; // rv 0 + assign SAXIHP1WSTRB_in[3] = (SAXIHP1WSTRB[3] !== 1'bz) && SAXIHP1WSTRB_delay[3]; // rv 0 + assign SAXIHP1WSTRB_in[4] = (SAXIHP1WSTRB[4] !== 1'bz) && SAXIHP1WSTRB_delay[4]; // rv 0 + assign SAXIHP1WSTRB_in[5] = (SAXIHP1WSTRB[5] !== 1'bz) && SAXIHP1WSTRB_delay[5]; // rv 0 + assign SAXIHP1WSTRB_in[6] = (SAXIHP1WSTRB[6] !== 1'bz) && SAXIHP1WSTRB_delay[6]; // rv 0 + assign SAXIHP1WSTRB_in[7] = (SAXIHP1WSTRB[7] !== 1'bz) && SAXIHP1WSTRB_delay[7]; // rv 0 + assign SAXIHP1WVALID_in = (SAXIHP1WVALID !== 1'bz) && SAXIHP1WVALID_delay; // rv 0 + assign SAXIHP2ACLK_in = (SAXIHP2ACLK !== 1'bz) && SAXIHP2ACLK_delay; // rv 0 + assign SAXIHP2ARADDR_in[0] = (SAXIHP2ARADDR[0] !== 1'bz) && SAXIHP2ARADDR_delay[0]; // rv 0 + assign SAXIHP2ARADDR_in[10] = (SAXIHP2ARADDR[10] !== 1'bz) && SAXIHP2ARADDR_delay[10]; // rv 0 + assign SAXIHP2ARADDR_in[11] = (SAXIHP2ARADDR[11] !== 1'bz) && SAXIHP2ARADDR_delay[11]; // rv 0 + assign SAXIHP2ARADDR_in[12] = (SAXIHP2ARADDR[12] !== 1'bz) && SAXIHP2ARADDR_delay[12]; // rv 0 + assign SAXIHP2ARADDR_in[13] = (SAXIHP2ARADDR[13] !== 1'bz) && SAXIHP2ARADDR_delay[13]; // rv 0 + assign SAXIHP2ARADDR_in[14] = (SAXIHP2ARADDR[14] !== 1'bz) && SAXIHP2ARADDR_delay[14]; // rv 0 + assign SAXIHP2ARADDR_in[15] = (SAXIHP2ARADDR[15] !== 1'bz) && SAXIHP2ARADDR_delay[15]; // rv 0 + assign SAXIHP2ARADDR_in[16] = (SAXIHP2ARADDR[16] !== 1'bz) && SAXIHP2ARADDR_delay[16]; // rv 0 + assign SAXIHP2ARADDR_in[17] = (SAXIHP2ARADDR[17] !== 1'bz) && SAXIHP2ARADDR_delay[17]; // rv 0 + assign SAXIHP2ARADDR_in[18] = (SAXIHP2ARADDR[18] !== 1'bz) && SAXIHP2ARADDR_delay[18]; // rv 0 + assign SAXIHP2ARADDR_in[19] = (SAXIHP2ARADDR[19] !== 1'bz) && SAXIHP2ARADDR_delay[19]; // rv 0 + assign SAXIHP2ARADDR_in[1] = (SAXIHP2ARADDR[1] !== 1'bz) && SAXIHP2ARADDR_delay[1]; // rv 0 + assign SAXIHP2ARADDR_in[20] = (SAXIHP2ARADDR[20] !== 1'bz) && SAXIHP2ARADDR_delay[20]; // rv 0 + assign SAXIHP2ARADDR_in[21] = (SAXIHP2ARADDR[21] !== 1'bz) && SAXIHP2ARADDR_delay[21]; // rv 0 + assign SAXIHP2ARADDR_in[22] = (SAXIHP2ARADDR[22] !== 1'bz) && SAXIHP2ARADDR_delay[22]; // rv 0 + assign SAXIHP2ARADDR_in[23] = (SAXIHP2ARADDR[23] !== 1'bz) && SAXIHP2ARADDR_delay[23]; // rv 0 + assign SAXIHP2ARADDR_in[24] = (SAXIHP2ARADDR[24] !== 1'bz) && SAXIHP2ARADDR_delay[24]; // rv 0 + assign SAXIHP2ARADDR_in[25] = (SAXIHP2ARADDR[25] !== 1'bz) && SAXIHP2ARADDR_delay[25]; // rv 0 + assign SAXIHP2ARADDR_in[26] = (SAXIHP2ARADDR[26] !== 1'bz) && SAXIHP2ARADDR_delay[26]; // rv 0 + assign SAXIHP2ARADDR_in[27] = (SAXIHP2ARADDR[27] !== 1'bz) && SAXIHP2ARADDR_delay[27]; // rv 0 + assign SAXIHP2ARADDR_in[28] = (SAXIHP2ARADDR[28] !== 1'bz) && SAXIHP2ARADDR_delay[28]; // rv 0 + assign SAXIHP2ARADDR_in[29] = (SAXIHP2ARADDR[29] !== 1'bz) && SAXIHP2ARADDR_delay[29]; // rv 0 + assign SAXIHP2ARADDR_in[2] = (SAXIHP2ARADDR[2] !== 1'bz) && SAXIHP2ARADDR_delay[2]; // rv 0 + assign SAXIHP2ARADDR_in[30] = (SAXIHP2ARADDR[30] !== 1'bz) && SAXIHP2ARADDR_delay[30]; // rv 0 + assign SAXIHP2ARADDR_in[31] = (SAXIHP2ARADDR[31] !== 1'bz) && SAXIHP2ARADDR_delay[31]; // rv 0 + assign SAXIHP2ARADDR_in[3] = (SAXIHP2ARADDR[3] !== 1'bz) && SAXIHP2ARADDR_delay[3]; // rv 0 + assign SAXIHP2ARADDR_in[4] = (SAXIHP2ARADDR[4] !== 1'bz) && SAXIHP2ARADDR_delay[4]; // rv 0 + assign SAXIHP2ARADDR_in[5] = (SAXIHP2ARADDR[5] !== 1'bz) && SAXIHP2ARADDR_delay[5]; // rv 0 + assign SAXIHP2ARADDR_in[6] = (SAXIHP2ARADDR[6] !== 1'bz) && SAXIHP2ARADDR_delay[6]; // rv 0 + assign SAXIHP2ARADDR_in[7] = (SAXIHP2ARADDR[7] !== 1'bz) && SAXIHP2ARADDR_delay[7]; // rv 0 + assign SAXIHP2ARADDR_in[8] = (SAXIHP2ARADDR[8] !== 1'bz) && SAXIHP2ARADDR_delay[8]; // rv 0 + assign SAXIHP2ARADDR_in[9] = (SAXIHP2ARADDR[9] !== 1'bz) && SAXIHP2ARADDR_delay[9]; // rv 0 + assign SAXIHP2ARBURST_in[0] = (SAXIHP2ARBURST[0] !== 1'bz) && SAXIHP2ARBURST_delay[0]; // rv 0 + assign SAXIHP2ARBURST_in[1] = (SAXIHP2ARBURST[1] !== 1'bz) && SAXIHP2ARBURST_delay[1]; // rv 0 + assign SAXIHP2ARCACHE_in[0] = (SAXIHP2ARCACHE[0] !== 1'bz) && SAXIHP2ARCACHE_delay[0]; // rv 0 + assign SAXIHP2ARCACHE_in[1] = (SAXIHP2ARCACHE[1] !== 1'bz) && SAXIHP2ARCACHE_delay[1]; // rv 0 + assign SAXIHP2ARCACHE_in[2] = (SAXIHP2ARCACHE[2] !== 1'bz) && SAXIHP2ARCACHE_delay[2]; // rv 0 + assign SAXIHP2ARCACHE_in[3] = (SAXIHP2ARCACHE[3] !== 1'bz) && SAXIHP2ARCACHE_delay[3]; // rv 0 + assign SAXIHP2ARID_in[0] = (SAXIHP2ARID[0] !== 1'bz) && SAXIHP2ARID_delay[0]; // rv 0 + assign SAXIHP2ARID_in[1] = (SAXIHP2ARID[1] !== 1'bz) && SAXIHP2ARID_delay[1]; // rv 0 + assign SAXIHP2ARID_in[2] = (SAXIHP2ARID[2] !== 1'bz) && SAXIHP2ARID_delay[2]; // rv 0 + assign SAXIHP2ARID_in[3] = (SAXIHP2ARID[3] !== 1'bz) && SAXIHP2ARID_delay[3]; // rv 0 + assign SAXIHP2ARID_in[4] = (SAXIHP2ARID[4] !== 1'bz) && SAXIHP2ARID_delay[4]; // rv 0 + assign SAXIHP2ARID_in[5] = (SAXIHP2ARID[5] !== 1'bz) && SAXIHP2ARID_delay[5]; // rv 0 + assign SAXIHP2ARLEN_in[0] = (SAXIHP2ARLEN[0] !== 1'bz) && SAXIHP2ARLEN_delay[0]; // rv 0 + assign SAXIHP2ARLEN_in[1] = (SAXIHP2ARLEN[1] !== 1'bz) && SAXIHP2ARLEN_delay[1]; // rv 0 + assign SAXIHP2ARLEN_in[2] = (SAXIHP2ARLEN[2] !== 1'bz) && SAXIHP2ARLEN_delay[2]; // rv 0 + assign SAXIHP2ARLEN_in[3] = (SAXIHP2ARLEN[3] !== 1'bz) && SAXIHP2ARLEN_delay[3]; // rv 0 + assign SAXIHP2ARLOCK_in[0] = (SAXIHP2ARLOCK[0] !== 1'bz) && SAXIHP2ARLOCK_delay[0]; // rv 0 + assign SAXIHP2ARLOCK_in[1] = (SAXIHP2ARLOCK[1] !== 1'bz) && SAXIHP2ARLOCK_delay[1]; // rv 0 + assign SAXIHP2ARPROT_in[0] = (SAXIHP2ARPROT[0] !== 1'bz) && SAXIHP2ARPROT_delay[0]; // rv 0 + assign SAXIHP2ARPROT_in[1] = (SAXIHP2ARPROT[1] !== 1'bz) && SAXIHP2ARPROT_delay[1]; // rv 0 + assign SAXIHP2ARPROT_in[2] = (SAXIHP2ARPROT[2] !== 1'bz) && SAXIHP2ARPROT_delay[2]; // rv 0 + assign SAXIHP2ARQOS_in[0] = (SAXIHP2ARQOS[0] !== 1'bz) && SAXIHP2ARQOS_delay[0]; // rv 0 + assign SAXIHP2ARQOS_in[1] = (SAXIHP2ARQOS[1] !== 1'bz) && SAXIHP2ARQOS_delay[1]; // rv 0 + assign SAXIHP2ARQOS_in[2] = (SAXIHP2ARQOS[2] !== 1'bz) && SAXIHP2ARQOS_delay[2]; // rv 0 + assign SAXIHP2ARQOS_in[3] = (SAXIHP2ARQOS[3] !== 1'bz) && SAXIHP2ARQOS_delay[3]; // rv 0 + assign SAXIHP2ARSIZE_in[0] = (SAXIHP2ARSIZE[0] !== 1'bz) && SAXIHP2ARSIZE_delay[0]; // rv 0 + assign SAXIHP2ARSIZE_in[1] = (SAXIHP2ARSIZE[1] !== 1'bz) && SAXIHP2ARSIZE_delay[1]; // rv 0 + assign SAXIHP2ARVALID_in = (SAXIHP2ARVALID !== 1'bz) && SAXIHP2ARVALID_delay; // rv 0 + assign SAXIHP2AWADDR_in[0] = (SAXIHP2AWADDR[0] !== 1'bz) && SAXIHP2AWADDR_delay[0]; // rv 0 + assign SAXIHP2AWADDR_in[10] = (SAXIHP2AWADDR[10] !== 1'bz) && SAXIHP2AWADDR_delay[10]; // rv 0 + assign SAXIHP2AWADDR_in[11] = (SAXIHP2AWADDR[11] !== 1'bz) && SAXIHP2AWADDR_delay[11]; // rv 0 + assign SAXIHP2AWADDR_in[12] = (SAXIHP2AWADDR[12] !== 1'bz) && SAXIHP2AWADDR_delay[12]; // rv 0 + assign SAXIHP2AWADDR_in[13] = (SAXIHP2AWADDR[13] !== 1'bz) && SAXIHP2AWADDR_delay[13]; // rv 0 + assign SAXIHP2AWADDR_in[14] = (SAXIHP2AWADDR[14] !== 1'bz) && SAXIHP2AWADDR_delay[14]; // rv 0 + assign SAXIHP2AWADDR_in[15] = (SAXIHP2AWADDR[15] !== 1'bz) && SAXIHP2AWADDR_delay[15]; // rv 0 + assign SAXIHP2AWADDR_in[16] = (SAXIHP2AWADDR[16] !== 1'bz) && SAXIHP2AWADDR_delay[16]; // rv 0 + assign SAXIHP2AWADDR_in[17] = (SAXIHP2AWADDR[17] !== 1'bz) && SAXIHP2AWADDR_delay[17]; // rv 0 + assign SAXIHP2AWADDR_in[18] = (SAXIHP2AWADDR[18] !== 1'bz) && SAXIHP2AWADDR_delay[18]; // rv 0 + assign SAXIHP2AWADDR_in[19] = (SAXIHP2AWADDR[19] !== 1'bz) && SAXIHP2AWADDR_delay[19]; // rv 0 + assign SAXIHP2AWADDR_in[1] = (SAXIHP2AWADDR[1] !== 1'bz) && SAXIHP2AWADDR_delay[1]; // rv 0 + assign SAXIHP2AWADDR_in[20] = (SAXIHP2AWADDR[20] !== 1'bz) && SAXIHP2AWADDR_delay[20]; // rv 0 + assign SAXIHP2AWADDR_in[21] = (SAXIHP2AWADDR[21] !== 1'bz) && SAXIHP2AWADDR_delay[21]; // rv 0 + assign SAXIHP2AWADDR_in[22] = (SAXIHP2AWADDR[22] !== 1'bz) && SAXIHP2AWADDR_delay[22]; // rv 0 + assign SAXIHP2AWADDR_in[23] = (SAXIHP2AWADDR[23] !== 1'bz) && SAXIHP2AWADDR_delay[23]; // rv 0 + assign SAXIHP2AWADDR_in[24] = (SAXIHP2AWADDR[24] !== 1'bz) && SAXIHP2AWADDR_delay[24]; // rv 0 + assign SAXIHP2AWADDR_in[25] = (SAXIHP2AWADDR[25] !== 1'bz) && SAXIHP2AWADDR_delay[25]; // rv 0 + assign SAXIHP2AWADDR_in[26] = (SAXIHP2AWADDR[26] !== 1'bz) && SAXIHP2AWADDR_delay[26]; // rv 0 + assign SAXIHP2AWADDR_in[27] = (SAXIHP2AWADDR[27] !== 1'bz) && SAXIHP2AWADDR_delay[27]; // rv 0 + assign SAXIHP2AWADDR_in[28] = (SAXIHP2AWADDR[28] !== 1'bz) && SAXIHP2AWADDR_delay[28]; // rv 0 + assign SAXIHP2AWADDR_in[29] = (SAXIHP2AWADDR[29] !== 1'bz) && SAXIHP2AWADDR_delay[29]; // rv 0 + assign SAXIHP2AWADDR_in[2] = (SAXIHP2AWADDR[2] !== 1'bz) && SAXIHP2AWADDR_delay[2]; // rv 0 + assign SAXIHP2AWADDR_in[30] = (SAXIHP2AWADDR[30] !== 1'bz) && SAXIHP2AWADDR_delay[30]; // rv 0 + assign SAXIHP2AWADDR_in[31] = (SAXIHP2AWADDR[31] !== 1'bz) && SAXIHP2AWADDR_delay[31]; // rv 0 + assign SAXIHP2AWADDR_in[3] = (SAXIHP2AWADDR[3] !== 1'bz) && SAXIHP2AWADDR_delay[3]; // rv 0 + assign SAXIHP2AWADDR_in[4] = (SAXIHP2AWADDR[4] !== 1'bz) && SAXIHP2AWADDR_delay[4]; // rv 0 + assign SAXIHP2AWADDR_in[5] = (SAXIHP2AWADDR[5] !== 1'bz) && SAXIHP2AWADDR_delay[5]; // rv 0 + assign SAXIHP2AWADDR_in[6] = (SAXIHP2AWADDR[6] !== 1'bz) && SAXIHP2AWADDR_delay[6]; // rv 0 + assign SAXIHP2AWADDR_in[7] = (SAXIHP2AWADDR[7] !== 1'bz) && SAXIHP2AWADDR_delay[7]; // rv 0 + assign SAXIHP2AWADDR_in[8] = (SAXIHP2AWADDR[8] !== 1'bz) && SAXIHP2AWADDR_delay[8]; // rv 0 + assign SAXIHP2AWADDR_in[9] = (SAXIHP2AWADDR[9] !== 1'bz) && SAXIHP2AWADDR_delay[9]; // rv 0 + assign SAXIHP2AWBURST_in[0] = (SAXIHP2AWBURST[0] !== 1'bz) && SAXIHP2AWBURST_delay[0]; // rv 0 + assign SAXIHP2AWBURST_in[1] = (SAXIHP2AWBURST[1] !== 1'bz) && SAXIHP2AWBURST_delay[1]; // rv 0 + assign SAXIHP2AWCACHE_in[0] = (SAXIHP2AWCACHE[0] !== 1'bz) && SAXIHP2AWCACHE_delay[0]; // rv 0 + assign SAXIHP2AWCACHE_in[1] = (SAXIHP2AWCACHE[1] !== 1'bz) && SAXIHP2AWCACHE_delay[1]; // rv 0 + assign SAXIHP2AWCACHE_in[2] = (SAXIHP2AWCACHE[2] !== 1'bz) && SAXIHP2AWCACHE_delay[2]; // rv 0 + assign SAXIHP2AWCACHE_in[3] = (SAXIHP2AWCACHE[3] !== 1'bz) && SAXIHP2AWCACHE_delay[3]; // rv 0 + assign SAXIHP2AWID_in[0] = (SAXIHP2AWID[0] !== 1'bz) && SAXIHP2AWID_delay[0]; // rv 0 + assign SAXIHP2AWID_in[1] = (SAXIHP2AWID[1] !== 1'bz) && SAXIHP2AWID_delay[1]; // rv 0 + assign SAXIHP2AWID_in[2] = (SAXIHP2AWID[2] !== 1'bz) && SAXIHP2AWID_delay[2]; // rv 0 + assign SAXIHP2AWID_in[3] = (SAXIHP2AWID[3] !== 1'bz) && SAXIHP2AWID_delay[3]; // rv 0 + assign SAXIHP2AWID_in[4] = (SAXIHP2AWID[4] !== 1'bz) && SAXIHP2AWID_delay[4]; // rv 0 + assign SAXIHP2AWID_in[5] = (SAXIHP2AWID[5] !== 1'bz) && SAXIHP2AWID_delay[5]; // rv 0 + assign SAXIHP2AWLEN_in[0] = (SAXIHP2AWLEN[0] !== 1'bz) && SAXIHP2AWLEN_delay[0]; // rv 0 + assign SAXIHP2AWLEN_in[1] = (SAXIHP2AWLEN[1] !== 1'bz) && SAXIHP2AWLEN_delay[1]; // rv 0 + assign SAXIHP2AWLEN_in[2] = (SAXIHP2AWLEN[2] !== 1'bz) && SAXIHP2AWLEN_delay[2]; // rv 0 + assign SAXIHP2AWLEN_in[3] = (SAXIHP2AWLEN[3] !== 1'bz) && SAXIHP2AWLEN_delay[3]; // rv 0 + assign SAXIHP2AWLOCK_in[0] = (SAXIHP2AWLOCK[0] !== 1'bz) && SAXIHP2AWLOCK_delay[0]; // rv 0 + assign SAXIHP2AWLOCK_in[1] = (SAXIHP2AWLOCK[1] !== 1'bz) && SAXIHP2AWLOCK_delay[1]; // rv 0 + assign SAXIHP2AWPROT_in[0] = (SAXIHP2AWPROT[0] !== 1'bz) && SAXIHP2AWPROT_delay[0]; // rv 0 + assign SAXIHP2AWPROT_in[1] = (SAXIHP2AWPROT[1] !== 1'bz) && SAXIHP2AWPROT_delay[1]; // rv 0 + assign SAXIHP2AWPROT_in[2] = (SAXIHP2AWPROT[2] !== 1'bz) && SAXIHP2AWPROT_delay[2]; // rv 0 + assign SAXIHP2AWQOS_in[0] = (SAXIHP2AWQOS[0] !== 1'bz) && SAXIHP2AWQOS_delay[0]; // rv 0 + assign SAXIHP2AWQOS_in[1] = (SAXIHP2AWQOS[1] !== 1'bz) && SAXIHP2AWQOS_delay[1]; // rv 0 + assign SAXIHP2AWQOS_in[2] = (SAXIHP2AWQOS[2] !== 1'bz) && SAXIHP2AWQOS_delay[2]; // rv 0 + assign SAXIHP2AWQOS_in[3] = (SAXIHP2AWQOS[3] !== 1'bz) && SAXIHP2AWQOS_delay[3]; // rv 0 + assign SAXIHP2AWSIZE_in[0] = (SAXIHP2AWSIZE[0] !== 1'bz) && SAXIHP2AWSIZE_delay[0]; // rv 0 + assign SAXIHP2AWSIZE_in[1] = (SAXIHP2AWSIZE[1] !== 1'bz) && SAXIHP2AWSIZE_delay[1]; // rv 0 + assign SAXIHP2AWVALID_in = (SAXIHP2AWVALID !== 1'bz) && SAXIHP2AWVALID_delay; // rv 0 + assign SAXIHP2BREADY_in = (SAXIHP2BREADY !== 1'bz) && SAXIHP2BREADY_delay; // rv 0 + assign SAXIHP2RREADY_in = (SAXIHP2RREADY !== 1'bz) && SAXIHP2RREADY_delay; // rv 0 + assign SAXIHP2WDATA_in[0] = (SAXIHP2WDATA[0] !== 1'bz) && SAXIHP2WDATA_delay[0]; // rv 0 + assign SAXIHP2WDATA_in[10] = (SAXIHP2WDATA[10] !== 1'bz) && SAXIHP2WDATA_delay[10]; // rv 0 + assign SAXIHP2WDATA_in[11] = (SAXIHP2WDATA[11] !== 1'bz) && SAXIHP2WDATA_delay[11]; // rv 0 + assign SAXIHP2WDATA_in[12] = (SAXIHP2WDATA[12] !== 1'bz) && SAXIHP2WDATA_delay[12]; // rv 0 + assign SAXIHP2WDATA_in[13] = (SAXIHP2WDATA[13] !== 1'bz) && SAXIHP2WDATA_delay[13]; // rv 0 + assign SAXIHP2WDATA_in[14] = (SAXIHP2WDATA[14] !== 1'bz) && SAXIHP2WDATA_delay[14]; // rv 0 + assign SAXIHP2WDATA_in[15] = (SAXIHP2WDATA[15] !== 1'bz) && SAXIHP2WDATA_delay[15]; // rv 0 + assign SAXIHP2WDATA_in[16] = (SAXIHP2WDATA[16] !== 1'bz) && SAXIHP2WDATA_delay[16]; // rv 0 + assign SAXIHP2WDATA_in[17] = (SAXIHP2WDATA[17] !== 1'bz) && SAXIHP2WDATA_delay[17]; // rv 0 + assign SAXIHP2WDATA_in[18] = (SAXIHP2WDATA[18] !== 1'bz) && SAXIHP2WDATA_delay[18]; // rv 0 + assign SAXIHP2WDATA_in[19] = (SAXIHP2WDATA[19] !== 1'bz) && SAXIHP2WDATA_delay[19]; // rv 0 + assign SAXIHP2WDATA_in[1] = (SAXIHP2WDATA[1] !== 1'bz) && SAXIHP2WDATA_delay[1]; // rv 0 + assign SAXIHP2WDATA_in[20] = (SAXIHP2WDATA[20] !== 1'bz) && SAXIHP2WDATA_delay[20]; // rv 0 + assign SAXIHP2WDATA_in[21] = (SAXIHP2WDATA[21] !== 1'bz) && SAXIHP2WDATA_delay[21]; // rv 0 + assign SAXIHP2WDATA_in[22] = (SAXIHP2WDATA[22] !== 1'bz) && SAXIHP2WDATA_delay[22]; // rv 0 + assign SAXIHP2WDATA_in[23] = (SAXIHP2WDATA[23] !== 1'bz) && SAXIHP2WDATA_delay[23]; // rv 0 + assign SAXIHP2WDATA_in[24] = (SAXIHP2WDATA[24] !== 1'bz) && SAXIHP2WDATA_delay[24]; // rv 0 + assign SAXIHP2WDATA_in[25] = (SAXIHP2WDATA[25] !== 1'bz) && SAXIHP2WDATA_delay[25]; // rv 0 + assign SAXIHP2WDATA_in[26] = (SAXIHP2WDATA[26] !== 1'bz) && SAXIHP2WDATA_delay[26]; // rv 0 + assign SAXIHP2WDATA_in[27] = (SAXIHP2WDATA[27] !== 1'bz) && SAXIHP2WDATA_delay[27]; // rv 0 + assign SAXIHP2WDATA_in[28] = (SAXIHP2WDATA[28] !== 1'bz) && SAXIHP2WDATA_delay[28]; // rv 0 + assign SAXIHP2WDATA_in[29] = (SAXIHP2WDATA[29] !== 1'bz) && SAXIHP2WDATA_delay[29]; // rv 0 + assign SAXIHP2WDATA_in[2] = (SAXIHP2WDATA[2] !== 1'bz) && SAXIHP2WDATA_delay[2]; // rv 0 + assign SAXIHP2WDATA_in[30] = (SAXIHP2WDATA[30] !== 1'bz) && SAXIHP2WDATA_delay[30]; // rv 0 + assign SAXIHP2WDATA_in[31] = (SAXIHP2WDATA[31] !== 1'bz) && SAXIHP2WDATA_delay[31]; // rv 0 + assign SAXIHP2WDATA_in[32] = (SAXIHP2WDATA[32] !== 1'bz) && SAXIHP2WDATA_delay[32]; // rv 0 + assign SAXIHP2WDATA_in[33] = (SAXIHP2WDATA[33] !== 1'bz) && SAXIHP2WDATA_delay[33]; // rv 0 + assign SAXIHP2WDATA_in[34] = (SAXIHP2WDATA[34] !== 1'bz) && SAXIHP2WDATA_delay[34]; // rv 0 + assign SAXIHP2WDATA_in[35] = (SAXIHP2WDATA[35] !== 1'bz) && SAXIHP2WDATA_delay[35]; // rv 0 + assign SAXIHP2WDATA_in[36] = (SAXIHP2WDATA[36] !== 1'bz) && SAXIHP2WDATA_delay[36]; // rv 0 + assign SAXIHP2WDATA_in[37] = (SAXIHP2WDATA[37] !== 1'bz) && SAXIHP2WDATA_delay[37]; // rv 0 + assign SAXIHP2WDATA_in[38] = (SAXIHP2WDATA[38] !== 1'bz) && SAXIHP2WDATA_delay[38]; // rv 0 + assign SAXIHP2WDATA_in[39] = (SAXIHP2WDATA[39] !== 1'bz) && SAXIHP2WDATA_delay[39]; // rv 0 + assign SAXIHP2WDATA_in[3] = (SAXIHP2WDATA[3] !== 1'bz) && SAXIHP2WDATA_delay[3]; // rv 0 + assign SAXIHP2WDATA_in[40] = (SAXIHP2WDATA[40] !== 1'bz) && SAXIHP2WDATA_delay[40]; // rv 0 + assign SAXIHP2WDATA_in[41] = (SAXIHP2WDATA[41] !== 1'bz) && SAXIHP2WDATA_delay[41]; // rv 0 + assign SAXIHP2WDATA_in[42] = (SAXIHP2WDATA[42] !== 1'bz) && SAXIHP2WDATA_delay[42]; // rv 0 + assign SAXIHP2WDATA_in[43] = (SAXIHP2WDATA[43] !== 1'bz) && SAXIHP2WDATA_delay[43]; // rv 0 + assign SAXIHP2WDATA_in[44] = (SAXIHP2WDATA[44] !== 1'bz) && SAXIHP2WDATA_delay[44]; // rv 0 + assign SAXIHP2WDATA_in[45] = (SAXIHP2WDATA[45] !== 1'bz) && SAXIHP2WDATA_delay[45]; // rv 0 + assign SAXIHP2WDATA_in[46] = (SAXIHP2WDATA[46] !== 1'bz) && SAXIHP2WDATA_delay[46]; // rv 0 + assign SAXIHP2WDATA_in[47] = (SAXIHP2WDATA[47] !== 1'bz) && SAXIHP2WDATA_delay[47]; // rv 0 + assign SAXIHP2WDATA_in[48] = (SAXIHP2WDATA[48] !== 1'bz) && SAXIHP2WDATA_delay[48]; // rv 0 + assign SAXIHP2WDATA_in[49] = (SAXIHP2WDATA[49] !== 1'bz) && SAXIHP2WDATA_delay[49]; // rv 0 + assign SAXIHP2WDATA_in[4] = (SAXIHP2WDATA[4] !== 1'bz) && SAXIHP2WDATA_delay[4]; // rv 0 + assign SAXIHP2WDATA_in[50] = (SAXIHP2WDATA[50] !== 1'bz) && SAXIHP2WDATA_delay[50]; // rv 0 + assign SAXIHP2WDATA_in[51] = (SAXIHP2WDATA[51] !== 1'bz) && SAXIHP2WDATA_delay[51]; // rv 0 + assign SAXIHP2WDATA_in[52] = (SAXIHP2WDATA[52] !== 1'bz) && SAXIHP2WDATA_delay[52]; // rv 0 + assign SAXIHP2WDATA_in[53] = (SAXIHP2WDATA[53] !== 1'bz) && SAXIHP2WDATA_delay[53]; // rv 0 + assign SAXIHP2WDATA_in[54] = (SAXIHP2WDATA[54] !== 1'bz) && SAXIHP2WDATA_delay[54]; // rv 0 + assign SAXIHP2WDATA_in[55] = (SAXIHP2WDATA[55] !== 1'bz) && SAXIHP2WDATA_delay[55]; // rv 0 + assign SAXIHP2WDATA_in[56] = (SAXIHP2WDATA[56] !== 1'bz) && SAXIHP2WDATA_delay[56]; // rv 0 + assign SAXIHP2WDATA_in[57] = (SAXIHP2WDATA[57] !== 1'bz) && SAXIHP2WDATA_delay[57]; // rv 0 + assign SAXIHP2WDATA_in[58] = (SAXIHP2WDATA[58] !== 1'bz) && SAXIHP2WDATA_delay[58]; // rv 0 + assign SAXIHP2WDATA_in[59] = (SAXIHP2WDATA[59] !== 1'bz) && SAXIHP2WDATA_delay[59]; // rv 0 + assign SAXIHP2WDATA_in[5] = (SAXIHP2WDATA[5] !== 1'bz) && SAXIHP2WDATA_delay[5]; // rv 0 + assign SAXIHP2WDATA_in[60] = (SAXIHP2WDATA[60] !== 1'bz) && SAXIHP2WDATA_delay[60]; // rv 0 + assign SAXIHP2WDATA_in[61] = (SAXIHP2WDATA[61] !== 1'bz) && SAXIHP2WDATA_delay[61]; // rv 0 + assign SAXIHP2WDATA_in[62] = (SAXIHP2WDATA[62] !== 1'bz) && SAXIHP2WDATA_delay[62]; // rv 0 + assign SAXIHP2WDATA_in[63] = (SAXIHP2WDATA[63] !== 1'bz) && SAXIHP2WDATA_delay[63]; // rv 0 + assign SAXIHP2WDATA_in[6] = (SAXIHP2WDATA[6] !== 1'bz) && SAXIHP2WDATA_delay[6]; // rv 0 + assign SAXIHP2WDATA_in[7] = (SAXIHP2WDATA[7] !== 1'bz) && SAXIHP2WDATA_delay[7]; // rv 0 + assign SAXIHP2WDATA_in[8] = (SAXIHP2WDATA[8] !== 1'bz) && SAXIHP2WDATA_delay[8]; // rv 0 + assign SAXIHP2WDATA_in[9] = (SAXIHP2WDATA[9] !== 1'bz) && SAXIHP2WDATA_delay[9]; // rv 0 + assign SAXIHP2WID_in[0] = (SAXIHP2WID[0] !== 1'bz) && SAXIHP2WID_delay[0]; // rv 0 + assign SAXIHP2WID_in[1] = (SAXIHP2WID[1] !== 1'bz) && SAXIHP2WID_delay[1]; // rv 0 + assign SAXIHP2WID_in[2] = (SAXIHP2WID[2] !== 1'bz) && SAXIHP2WID_delay[2]; // rv 0 + assign SAXIHP2WID_in[3] = (SAXIHP2WID[3] !== 1'bz) && SAXIHP2WID_delay[3]; // rv 0 + assign SAXIHP2WID_in[4] = (SAXIHP2WID[4] !== 1'bz) && SAXIHP2WID_delay[4]; // rv 0 + assign SAXIHP2WID_in[5] = (SAXIHP2WID[5] !== 1'bz) && SAXIHP2WID_delay[5]; // rv 0 + assign SAXIHP2WLAST_in = (SAXIHP2WLAST !== 1'bz) && SAXIHP2WLAST_delay; // rv 0 + assign SAXIHP2WSTRB_in[0] = (SAXIHP2WSTRB[0] !== 1'bz) && SAXIHP2WSTRB_delay[0]; // rv 0 + assign SAXIHP2WSTRB_in[1] = (SAXIHP2WSTRB[1] !== 1'bz) && SAXIHP2WSTRB_delay[1]; // rv 0 + assign SAXIHP2WSTRB_in[2] = (SAXIHP2WSTRB[2] !== 1'bz) && SAXIHP2WSTRB_delay[2]; // rv 0 + assign SAXIHP2WSTRB_in[3] = (SAXIHP2WSTRB[3] !== 1'bz) && SAXIHP2WSTRB_delay[3]; // rv 0 + assign SAXIHP2WSTRB_in[4] = (SAXIHP2WSTRB[4] !== 1'bz) && SAXIHP2WSTRB_delay[4]; // rv 0 + assign SAXIHP2WSTRB_in[5] = (SAXIHP2WSTRB[5] !== 1'bz) && SAXIHP2WSTRB_delay[5]; // rv 0 + assign SAXIHP2WSTRB_in[6] = (SAXIHP2WSTRB[6] !== 1'bz) && SAXIHP2WSTRB_delay[6]; // rv 0 + assign SAXIHP2WSTRB_in[7] = (SAXIHP2WSTRB[7] !== 1'bz) && SAXIHP2WSTRB_delay[7]; // rv 0 + assign SAXIHP2WVALID_in = (SAXIHP2WVALID !== 1'bz) && SAXIHP2WVALID_delay; // rv 0 + assign SAXIHP3ACLK_in = (SAXIHP3ACLK !== 1'bz) && SAXIHP3ACLK_delay; // rv 0 + assign SAXIHP3ARADDR_in[0] = (SAXIHP3ARADDR[0] !== 1'bz) && SAXIHP3ARADDR_delay[0]; // rv 0 + assign SAXIHP3ARADDR_in[10] = (SAXIHP3ARADDR[10] !== 1'bz) && SAXIHP3ARADDR_delay[10]; // rv 0 + assign SAXIHP3ARADDR_in[11] = (SAXIHP3ARADDR[11] !== 1'bz) && SAXIHP3ARADDR_delay[11]; // rv 0 + assign SAXIHP3ARADDR_in[12] = (SAXIHP3ARADDR[12] !== 1'bz) && SAXIHP3ARADDR_delay[12]; // rv 0 + assign SAXIHP3ARADDR_in[13] = (SAXIHP3ARADDR[13] !== 1'bz) && SAXIHP3ARADDR_delay[13]; // rv 0 + assign SAXIHP3ARADDR_in[14] = (SAXIHP3ARADDR[14] !== 1'bz) && SAXIHP3ARADDR_delay[14]; // rv 0 + assign SAXIHP3ARADDR_in[15] = (SAXIHP3ARADDR[15] !== 1'bz) && SAXIHP3ARADDR_delay[15]; // rv 0 + assign SAXIHP3ARADDR_in[16] = (SAXIHP3ARADDR[16] !== 1'bz) && SAXIHP3ARADDR_delay[16]; // rv 0 + assign SAXIHP3ARADDR_in[17] = (SAXIHP3ARADDR[17] !== 1'bz) && SAXIHP3ARADDR_delay[17]; // rv 0 + assign SAXIHP3ARADDR_in[18] = (SAXIHP3ARADDR[18] !== 1'bz) && SAXIHP3ARADDR_delay[18]; // rv 0 + assign SAXIHP3ARADDR_in[19] = (SAXIHP3ARADDR[19] !== 1'bz) && SAXIHP3ARADDR_delay[19]; // rv 0 + assign SAXIHP3ARADDR_in[1] = (SAXIHP3ARADDR[1] !== 1'bz) && SAXIHP3ARADDR_delay[1]; // rv 0 + assign SAXIHP3ARADDR_in[20] = (SAXIHP3ARADDR[20] !== 1'bz) && SAXIHP3ARADDR_delay[20]; // rv 0 + assign SAXIHP3ARADDR_in[21] = (SAXIHP3ARADDR[21] !== 1'bz) && SAXIHP3ARADDR_delay[21]; // rv 0 + assign SAXIHP3ARADDR_in[22] = (SAXIHP3ARADDR[22] !== 1'bz) && SAXIHP3ARADDR_delay[22]; // rv 0 + assign SAXIHP3ARADDR_in[23] = (SAXIHP3ARADDR[23] !== 1'bz) && SAXIHP3ARADDR_delay[23]; // rv 0 + assign SAXIHP3ARADDR_in[24] = (SAXIHP3ARADDR[24] !== 1'bz) && SAXIHP3ARADDR_delay[24]; // rv 0 + assign SAXIHP3ARADDR_in[25] = (SAXIHP3ARADDR[25] !== 1'bz) && SAXIHP3ARADDR_delay[25]; // rv 0 + assign SAXIHP3ARADDR_in[26] = (SAXIHP3ARADDR[26] !== 1'bz) && SAXIHP3ARADDR_delay[26]; // rv 0 + assign SAXIHP3ARADDR_in[27] = (SAXIHP3ARADDR[27] !== 1'bz) && SAXIHP3ARADDR_delay[27]; // rv 0 + assign SAXIHP3ARADDR_in[28] = (SAXIHP3ARADDR[28] !== 1'bz) && SAXIHP3ARADDR_delay[28]; // rv 0 + assign SAXIHP3ARADDR_in[29] = (SAXIHP3ARADDR[29] !== 1'bz) && SAXIHP3ARADDR_delay[29]; // rv 0 + assign SAXIHP3ARADDR_in[2] = (SAXIHP3ARADDR[2] !== 1'bz) && SAXIHP3ARADDR_delay[2]; // rv 0 + assign SAXIHP3ARADDR_in[30] = (SAXIHP3ARADDR[30] !== 1'bz) && SAXIHP3ARADDR_delay[30]; // rv 0 + assign SAXIHP3ARADDR_in[31] = (SAXIHP3ARADDR[31] !== 1'bz) && SAXIHP3ARADDR_delay[31]; // rv 0 + assign SAXIHP3ARADDR_in[3] = (SAXIHP3ARADDR[3] !== 1'bz) && SAXIHP3ARADDR_delay[3]; // rv 0 + assign SAXIHP3ARADDR_in[4] = (SAXIHP3ARADDR[4] !== 1'bz) && SAXIHP3ARADDR_delay[4]; // rv 0 + assign SAXIHP3ARADDR_in[5] = (SAXIHP3ARADDR[5] !== 1'bz) && SAXIHP3ARADDR_delay[5]; // rv 0 + assign SAXIHP3ARADDR_in[6] = (SAXIHP3ARADDR[6] !== 1'bz) && SAXIHP3ARADDR_delay[6]; // rv 0 + assign SAXIHP3ARADDR_in[7] = (SAXIHP3ARADDR[7] !== 1'bz) && SAXIHP3ARADDR_delay[7]; // rv 0 + assign SAXIHP3ARADDR_in[8] = (SAXIHP3ARADDR[8] !== 1'bz) && SAXIHP3ARADDR_delay[8]; // rv 0 + assign SAXIHP3ARADDR_in[9] = (SAXIHP3ARADDR[9] !== 1'bz) && SAXIHP3ARADDR_delay[9]; // rv 0 + assign SAXIHP3ARBURST_in[0] = (SAXIHP3ARBURST[0] !== 1'bz) && SAXIHP3ARBURST_delay[0]; // rv 0 + assign SAXIHP3ARBURST_in[1] = (SAXIHP3ARBURST[1] !== 1'bz) && SAXIHP3ARBURST_delay[1]; // rv 0 + assign SAXIHP3ARCACHE_in[0] = (SAXIHP3ARCACHE[0] !== 1'bz) && SAXIHP3ARCACHE_delay[0]; // rv 0 + assign SAXIHP3ARCACHE_in[1] = (SAXIHP3ARCACHE[1] !== 1'bz) && SAXIHP3ARCACHE_delay[1]; // rv 0 + assign SAXIHP3ARCACHE_in[2] = (SAXIHP3ARCACHE[2] !== 1'bz) && SAXIHP3ARCACHE_delay[2]; // rv 0 + assign SAXIHP3ARCACHE_in[3] = (SAXIHP3ARCACHE[3] !== 1'bz) && SAXIHP3ARCACHE_delay[3]; // rv 0 + assign SAXIHP3ARID_in[0] = (SAXIHP3ARID[0] !== 1'bz) && SAXIHP3ARID_delay[0]; // rv 0 + assign SAXIHP3ARID_in[1] = (SAXIHP3ARID[1] !== 1'bz) && SAXIHP3ARID_delay[1]; // rv 0 + assign SAXIHP3ARID_in[2] = (SAXIHP3ARID[2] !== 1'bz) && SAXIHP3ARID_delay[2]; // rv 0 + assign SAXIHP3ARID_in[3] = (SAXIHP3ARID[3] !== 1'bz) && SAXIHP3ARID_delay[3]; // rv 0 + assign SAXIHP3ARID_in[4] = (SAXIHP3ARID[4] !== 1'bz) && SAXIHP3ARID_delay[4]; // rv 0 + assign SAXIHP3ARID_in[5] = (SAXIHP3ARID[5] !== 1'bz) && SAXIHP3ARID_delay[5]; // rv 0 + assign SAXIHP3ARLEN_in[0] = (SAXIHP3ARLEN[0] !== 1'bz) && SAXIHP3ARLEN_delay[0]; // rv 0 + assign SAXIHP3ARLEN_in[1] = (SAXIHP3ARLEN[1] !== 1'bz) && SAXIHP3ARLEN_delay[1]; // rv 0 + assign SAXIHP3ARLEN_in[2] = (SAXIHP3ARLEN[2] !== 1'bz) && SAXIHP3ARLEN_delay[2]; // rv 0 + assign SAXIHP3ARLEN_in[3] = (SAXIHP3ARLEN[3] !== 1'bz) && SAXIHP3ARLEN_delay[3]; // rv 0 + assign SAXIHP3ARLOCK_in[0] = (SAXIHP3ARLOCK[0] !== 1'bz) && SAXIHP3ARLOCK_delay[0]; // rv 0 + assign SAXIHP3ARLOCK_in[1] = (SAXIHP3ARLOCK[1] !== 1'bz) && SAXIHP3ARLOCK_delay[1]; // rv 0 + assign SAXIHP3ARPROT_in[0] = (SAXIHP3ARPROT[0] !== 1'bz) && SAXIHP3ARPROT_delay[0]; // rv 0 + assign SAXIHP3ARPROT_in[1] = (SAXIHP3ARPROT[1] !== 1'bz) && SAXIHP3ARPROT_delay[1]; // rv 0 + assign SAXIHP3ARPROT_in[2] = (SAXIHP3ARPROT[2] !== 1'bz) && SAXIHP3ARPROT_delay[2]; // rv 0 + assign SAXIHP3ARQOS_in[0] = (SAXIHP3ARQOS[0] !== 1'bz) && SAXIHP3ARQOS_delay[0]; // rv 0 + assign SAXIHP3ARQOS_in[1] = (SAXIHP3ARQOS[1] !== 1'bz) && SAXIHP3ARQOS_delay[1]; // rv 0 + assign SAXIHP3ARQOS_in[2] = (SAXIHP3ARQOS[2] !== 1'bz) && SAXIHP3ARQOS_delay[2]; // rv 0 + assign SAXIHP3ARQOS_in[3] = (SAXIHP3ARQOS[3] !== 1'bz) && SAXIHP3ARQOS_delay[3]; // rv 0 + assign SAXIHP3ARSIZE_in[0] = (SAXIHP3ARSIZE[0] !== 1'bz) && SAXIHP3ARSIZE_delay[0]; // rv 0 + assign SAXIHP3ARSIZE_in[1] = (SAXIHP3ARSIZE[1] !== 1'bz) && SAXIHP3ARSIZE_delay[1]; // rv 0 + assign SAXIHP3ARVALID_in = (SAXIHP3ARVALID !== 1'bz) && SAXIHP3ARVALID_delay; // rv 0 + assign SAXIHP3AWADDR_in[0] = (SAXIHP3AWADDR[0] !== 1'bz) && SAXIHP3AWADDR_delay[0]; // rv 0 + assign SAXIHP3AWADDR_in[10] = (SAXIHP3AWADDR[10] !== 1'bz) && SAXIHP3AWADDR_delay[10]; // rv 0 + assign SAXIHP3AWADDR_in[11] = (SAXIHP3AWADDR[11] !== 1'bz) && SAXIHP3AWADDR_delay[11]; // rv 0 + assign SAXIHP3AWADDR_in[12] = (SAXIHP3AWADDR[12] !== 1'bz) && SAXIHP3AWADDR_delay[12]; // rv 0 + assign SAXIHP3AWADDR_in[13] = (SAXIHP3AWADDR[13] !== 1'bz) && SAXIHP3AWADDR_delay[13]; // rv 0 + assign SAXIHP3AWADDR_in[14] = (SAXIHP3AWADDR[14] !== 1'bz) && SAXIHP3AWADDR_delay[14]; // rv 0 + assign SAXIHP3AWADDR_in[15] = (SAXIHP3AWADDR[15] !== 1'bz) && SAXIHP3AWADDR_delay[15]; // rv 0 + assign SAXIHP3AWADDR_in[16] = (SAXIHP3AWADDR[16] !== 1'bz) && SAXIHP3AWADDR_delay[16]; // rv 0 + assign SAXIHP3AWADDR_in[17] = (SAXIHP3AWADDR[17] !== 1'bz) && SAXIHP3AWADDR_delay[17]; // rv 0 + assign SAXIHP3AWADDR_in[18] = (SAXIHP3AWADDR[18] !== 1'bz) && SAXIHP3AWADDR_delay[18]; // rv 0 + assign SAXIHP3AWADDR_in[19] = (SAXIHP3AWADDR[19] !== 1'bz) && SAXIHP3AWADDR_delay[19]; // rv 0 + assign SAXIHP3AWADDR_in[1] = (SAXIHP3AWADDR[1] !== 1'bz) && SAXIHP3AWADDR_delay[1]; // rv 0 + assign SAXIHP3AWADDR_in[20] = (SAXIHP3AWADDR[20] !== 1'bz) && SAXIHP3AWADDR_delay[20]; // rv 0 + assign SAXIHP3AWADDR_in[21] = (SAXIHP3AWADDR[21] !== 1'bz) && SAXIHP3AWADDR_delay[21]; // rv 0 + assign SAXIHP3AWADDR_in[22] = (SAXIHP3AWADDR[22] !== 1'bz) && SAXIHP3AWADDR_delay[22]; // rv 0 + assign SAXIHP3AWADDR_in[23] = (SAXIHP3AWADDR[23] !== 1'bz) && SAXIHP3AWADDR_delay[23]; // rv 0 + assign SAXIHP3AWADDR_in[24] = (SAXIHP3AWADDR[24] !== 1'bz) && SAXIHP3AWADDR_delay[24]; // rv 0 + assign SAXIHP3AWADDR_in[25] = (SAXIHP3AWADDR[25] !== 1'bz) && SAXIHP3AWADDR_delay[25]; // rv 0 + assign SAXIHP3AWADDR_in[26] = (SAXIHP3AWADDR[26] !== 1'bz) && SAXIHP3AWADDR_delay[26]; // rv 0 + assign SAXIHP3AWADDR_in[27] = (SAXIHP3AWADDR[27] !== 1'bz) && SAXIHP3AWADDR_delay[27]; // rv 0 + assign SAXIHP3AWADDR_in[28] = (SAXIHP3AWADDR[28] !== 1'bz) && SAXIHP3AWADDR_delay[28]; // rv 0 + assign SAXIHP3AWADDR_in[29] = (SAXIHP3AWADDR[29] !== 1'bz) && SAXIHP3AWADDR_delay[29]; // rv 0 + assign SAXIHP3AWADDR_in[2] = (SAXIHP3AWADDR[2] !== 1'bz) && SAXIHP3AWADDR_delay[2]; // rv 0 + assign SAXIHP3AWADDR_in[30] = (SAXIHP3AWADDR[30] !== 1'bz) && SAXIHP3AWADDR_delay[30]; // rv 0 + assign SAXIHP3AWADDR_in[31] = (SAXIHP3AWADDR[31] !== 1'bz) && SAXIHP3AWADDR_delay[31]; // rv 0 + assign SAXIHP3AWADDR_in[3] = (SAXIHP3AWADDR[3] !== 1'bz) && SAXIHP3AWADDR_delay[3]; // rv 0 + assign SAXIHP3AWADDR_in[4] = (SAXIHP3AWADDR[4] !== 1'bz) && SAXIHP3AWADDR_delay[4]; // rv 0 + assign SAXIHP3AWADDR_in[5] = (SAXIHP3AWADDR[5] !== 1'bz) && SAXIHP3AWADDR_delay[5]; // rv 0 + assign SAXIHP3AWADDR_in[6] = (SAXIHP3AWADDR[6] !== 1'bz) && SAXIHP3AWADDR_delay[6]; // rv 0 + assign SAXIHP3AWADDR_in[7] = (SAXIHP3AWADDR[7] !== 1'bz) && SAXIHP3AWADDR_delay[7]; // rv 0 + assign SAXIHP3AWADDR_in[8] = (SAXIHP3AWADDR[8] !== 1'bz) && SAXIHP3AWADDR_delay[8]; // rv 0 + assign SAXIHP3AWADDR_in[9] = (SAXIHP3AWADDR[9] !== 1'bz) && SAXIHP3AWADDR_delay[9]; // rv 0 + assign SAXIHP3AWBURST_in[0] = (SAXIHP3AWBURST[0] !== 1'bz) && SAXIHP3AWBURST_delay[0]; // rv 0 + assign SAXIHP3AWBURST_in[1] = (SAXIHP3AWBURST[1] !== 1'bz) && SAXIHP3AWBURST_delay[1]; // rv 0 + assign SAXIHP3AWCACHE_in[0] = (SAXIHP3AWCACHE[0] !== 1'bz) && SAXIHP3AWCACHE_delay[0]; // rv 0 + assign SAXIHP3AWCACHE_in[1] = (SAXIHP3AWCACHE[1] !== 1'bz) && SAXIHP3AWCACHE_delay[1]; // rv 0 + assign SAXIHP3AWCACHE_in[2] = (SAXIHP3AWCACHE[2] !== 1'bz) && SAXIHP3AWCACHE_delay[2]; // rv 0 + assign SAXIHP3AWCACHE_in[3] = (SAXIHP3AWCACHE[3] !== 1'bz) && SAXIHP3AWCACHE_delay[3]; // rv 0 + assign SAXIHP3AWID_in[0] = (SAXIHP3AWID[0] !== 1'bz) && SAXIHP3AWID_delay[0]; // rv 0 + assign SAXIHP3AWID_in[1] = (SAXIHP3AWID[1] !== 1'bz) && SAXIHP3AWID_delay[1]; // rv 0 + assign SAXIHP3AWID_in[2] = (SAXIHP3AWID[2] !== 1'bz) && SAXIHP3AWID_delay[2]; // rv 0 + assign SAXIHP3AWID_in[3] = (SAXIHP3AWID[3] !== 1'bz) && SAXIHP3AWID_delay[3]; // rv 0 + assign SAXIHP3AWID_in[4] = (SAXIHP3AWID[4] !== 1'bz) && SAXIHP3AWID_delay[4]; // rv 0 + assign SAXIHP3AWID_in[5] = (SAXIHP3AWID[5] !== 1'bz) && SAXIHP3AWID_delay[5]; // rv 0 + assign SAXIHP3AWLEN_in[0] = (SAXIHP3AWLEN[0] !== 1'bz) && SAXIHP3AWLEN_delay[0]; // rv 0 + assign SAXIHP3AWLEN_in[1] = (SAXIHP3AWLEN[1] !== 1'bz) && SAXIHP3AWLEN_delay[1]; // rv 0 + assign SAXIHP3AWLEN_in[2] = (SAXIHP3AWLEN[2] !== 1'bz) && SAXIHP3AWLEN_delay[2]; // rv 0 + assign SAXIHP3AWLEN_in[3] = (SAXIHP3AWLEN[3] !== 1'bz) && SAXIHP3AWLEN_delay[3]; // rv 0 + assign SAXIHP3AWLOCK_in[0] = (SAXIHP3AWLOCK[0] !== 1'bz) && SAXIHP3AWLOCK_delay[0]; // rv 0 + assign SAXIHP3AWLOCK_in[1] = (SAXIHP3AWLOCK[1] !== 1'bz) && SAXIHP3AWLOCK_delay[1]; // rv 0 + assign SAXIHP3AWPROT_in[0] = (SAXIHP3AWPROT[0] !== 1'bz) && SAXIHP3AWPROT_delay[0]; // rv 0 + assign SAXIHP3AWPROT_in[1] = (SAXIHP3AWPROT[1] !== 1'bz) && SAXIHP3AWPROT_delay[1]; // rv 0 + assign SAXIHP3AWPROT_in[2] = (SAXIHP3AWPROT[2] !== 1'bz) && SAXIHP3AWPROT_delay[2]; // rv 0 + assign SAXIHP3AWQOS_in[0] = (SAXIHP3AWQOS[0] !== 1'bz) && SAXIHP3AWQOS_delay[0]; // rv 0 + assign SAXIHP3AWQOS_in[1] = (SAXIHP3AWQOS[1] !== 1'bz) && SAXIHP3AWQOS_delay[1]; // rv 0 + assign SAXIHP3AWQOS_in[2] = (SAXIHP3AWQOS[2] !== 1'bz) && SAXIHP3AWQOS_delay[2]; // rv 0 + assign SAXIHP3AWQOS_in[3] = (SAXIHP3AWQOS[3] !== 1'bz) && SAXIHP3AWQOS_delay[3]; // rv 0 + assign SAXIHP3AWSIZE_in[0] = (SAXIHP3AWSIZE[0] !== 1'bz) && SAXIHP3AWSIZE_delay[0]; // rv 0 + assign SAXIHP3AWSIZE_in[1] = (SAXIHP3AWSIZE[1] !== 1'bz) && SAXIHP3AWSIZE_delay[1]; // rv 0 + assign SAXIHP3AWVALID_in = (SAXIHP3AWVALID !== 1'bz) && SAXIHP3AWVALID_delay; // rv 0 + assign SAXIHP3BREADY_in = (SAXIHP3BREADY !== 1'bz) && SAXIHP3BREADY_delay; // rv 0 + assign SAXIHP3RREADY_in = (SAXIHP3RREADY !== 1'bz) && SAXIHP3RREADY_delay; // rv 0 + assign SAXIHP3WDATA_in[0] = (SAXIHP3WDATA[0] !== 1'bz) && SAXIHP3WDATA_delay[0]; // rv 0 + assign SAXIHP3WDATA_in[10] = (SAXIHP3WDATA[10] !== 1'bz) && SAXIHP3WDATA_delay[10]; // rv 0 + assign SAXIHP3WDATA_in[11] = (SAXIHP3WDATA[11] !== 1'bz) && SAXIHP3WDATA_delay[11]; // rv 0 + assign SAXIHP3WDATA_in[12] = (SAXIHP3WDATA[12] !== 1'bz) && SAXIHP3WDATA_delay[12]; // rv 0 + assign SAXIHP3WDATA_in[13] = (SAXIHP3WDATA[13] !== 1'bz) && SAXIHP3WDATA_delay[13]; // rv 0 + assign SAXIHP3WDATA_in[14] = (SAXIHP3WDATA[14] !== 1'bz) && SAXIHP3WDATA_delay[14]; // rv 0 + assign SAXIHP3WDATA_in[15] = (SAXIHP3WDATA[15] !== 1'bz) && SAXIHP3WDATA_delay[15]; // rv 0 + assign SAXIHP3WDATA_in[16] = (SAXIHP3WDATA[16] !== 1'bz) && SAXIHP3WDATA_delay[16]; // rv 0 + assign SAXIHP3WDATA_in[17] = (SAXIHP3WDATA[17] !== 1'bz) && SAXIHP3WDATA_delay[17]; // rv 0 + assign SAXIHP3WDATA_in[18] = (SAXIHP3WDATA[18] !== 1'bz) && SAXIHP3WDATA_delay[18]; // rv 0 + assign SAXIHP3WDATA_in[19] = (SAXIHP3WDATA[19] !== 1'bz) && SAXIHP3WDATA_delay[19]; // rv 0 + assign SAXIHP3WDATA_in[1] = (SAXIHP3WDATA[1] !== 1'bz) && SAXIHP3WDATA_delay[1]; // rv 0 + assign SAXIHP3WDATA_in[20] = (SAXIHP3WDATA[20] !== 1'bz) && SAXIHP3WDATA_delay[20]; // rv 0 + assign SAXIHP3WDATA_in[21] = (SAXIHP3WDATA[21] !== 1'bz) && SAXIHP3WDATA_delay[21]; // rv 0 + assign SAXIHP3WDATA_in[22] = (SAXIHP3WDATA[22] !== 1'bz) && SAXIHP3WDATA_delay[22]; // rv 0 + assign SAXIHP3WDATA_in[23] = (SAXIHP3WDATA[23] !== 1'bz) && SAXIHP3WDATA_delay[23]; // rv 0 + assign SAXIHP3WDATA_in[24] = (SAXIHP3WDATA[24] !== 1'bz) && SAXIHP3WDATA_delay[24]; // rv 0 + assign SAXIHP3WDATA_in[25] = (SAXIHP3WDATA[25] !== 1'bz) && SAXIHP3WDATA_delay[25]; // rv 0 + assign SAXIHP3WDATA_in[26] = (SAXIHP3WDATA[26] !== 1'bz) && SAXIHP3WDATA_delay[26]; // rv 0 + assign SAXIHP3WDATA_in[27] = (SAXIHP3WDATA[27] !== 1'bz) && SAXIHP3WDATA_delay[27]; // rv 0 + assign SAXIHP3WDATA_in[28] = (SAXIHP3WDATA[28] !== 1'bz) && SAXIHP3WDATA_delay[28]; // rv 0 + assign SAXIHP3WDATA_in[29] = (SAXIHP3WDATA[29] !== 1'bz) && SAXIHP3WDATA_delay[29]; // rv 0 + assign SAXIHP3WDATA_in[2] = (SAXIHP3WDATA[2] !== 1'bz) && SAXIHP3WDATA_delay[2]; // rv 0 + assign SAXIHP3WDATA_in[30] = (SAXIHP3WDATA[30] !== 1'bz) && SAXIHP3WDATA_delay[30]; // rv 0 + assign SAXIHP3WDATA_in[31] = (SAXIHP3WDATA[31] !== 1'bz) && SAXIHP3WDATA_delay[31]; // rv 0 + assign SAXIHP3WDATA_in[32] = (SAXIHP3WDATA[32] !== 1'bz) && SAXIHP3WDATA_delay[32]; // rv 0 + assign SAXIHP3WDATA_in[33] = (SAXIHP3WDATA[33] !== 1'bz) && SAXIHP3WDATA_delay[33]; // rv 0 + assign SAXIHP3WDATA_in[34] = (SAXIHP3WDATA[34] !== 1'bz) && SAXIHP3WDATA_delay[34]; // rv 0 + assign SAXIHP3WDATA_in[35] = (SAXIHP3WDATA[35] !== 1'bz) && SAXIHP3WDATA_delay[35]; // rv 0 + assign SAXIHP3WDATA_in[36] = (SAXIHP3WDATA[36] !== 1'bz) && SAXIHP3WDATA_delay[36]; // rv 0 + assign SAXIHP3WDATA_in[37] = (SAXIHP3WDATA[37] !== 1'bz) && SAXIHP3WDATA_delay[37]; // rv 0 + assign SAXIHP3WDATA_in[38] = (SAXIHP3WDATA[38] !== 1'bz) && SAXIHP3WDATA_delay[38]; // rv 0 + assign SAXIHP3WDATA_in[39] = (SAXIHP3WDATA[39] !== 1'bz) && SAXIHP3WDATA_delay[39]; // rv 0 + assign SAXIHP3WDATA_in[3] = (SAXIHP3WDATA[3] !== 1'bz) && SAXIHP3WDATA_delay[3]; // rv 0 + assign SAXIHP3WDATA_in[40] = (SAXIHP3WDATA[40] !== 1'bz) && SAXIHP3WDATA_delay[40]; // rv 0 + assign SAXIHP3WDATA_in[41] = (SAXIHP3WDATA[41] !== 1'bz) && SAXIHP3WDATA_delay[41]; // rv 0 + assign SAXIHP3WDATA_in[42] = (SAXIHP3WDATA[42] !== 1'bz) && SAXIHP3WDATA_delay[42]; // rv 0 + assign SAXIHP3WDATA_in[43] = (SAXIHP3WDATA[43] !== 1'bz) && SAXIHP3WDATA_delay[43]; // rv 0 + assign SAXIHP3WDATA_in[44] = (SAXIHP3WDATA[44] !== 1'bz) && SAXIHP3WDATA_delay[44]; // rv 0 + assign SAXIHP3WDATA_in[45] = (SAXIHP3WDATA[45] !== 1'bz) && SAXIHP3WDATA_delay[45]; // rv 0 + assign SAXIHP3WDATA_in[46] = (SAXIHP3WDATA[46] !== 1'bz) && SAXIHP3WDATA_delay[46]; // rv 0 + assign SAXIHP3WDATA_in[47] = (SAXIHP3WDATA[47] !== 1'bz) && SAXIHP3WDATA_delay[47]; // rv 0 + assign SAXIHP3WDATA_in[48] = (SAXIHP3WDATA[48] !== 1'bz) && SAXIHP3WDATA_delay[48]; // rv 0 + assign SAXIHP3WDATA_in[49] = (SAXIHP3WDATA[49] !== 1'bz) && SAXIHP3WDATA_delay[49]; // rv 0 + assign SAXIHP3WDATA_in[4] = (SAXIHP3WDATA[4] !== 1'bz) && SAXIHP3WDATA_delay[4]; // rv 0 + assign SAXIHP3WDATA_in[50] = (SAXIHP3WDATA[50] !== 1'bz) && SAXIHP3WDATA_delay[50]; // rv 0 + assign SAXIHP3WDATA_in[51] = (SAXIHP3WDATA[51] !== 1'bz) && SAXIHP3WDATA_delay[51]; // rv 0 + assign SAXIHP3WDATA_in[52] = (SAXIHP3WDATA[52] !== 1'bz) && SAXIHP3WDATA_delay[52]; // rv 0 + assign SAXIHP3WDATA_in[53] = (SAXIHP3WDATA[53] !== 1'bz) && SAXIHP3WDATA_delay[53]; // rv 0 + assign SAXIHP3WDATA_in[54] = (SAXIHP3WDATA[54] !== 1'bz) && SAXIHP3WDATA_delay[54]; // rv 0 + assign SAXIHP3WDATA_in[55] = (SAXIHP3WDATA[55] !== 1'bz) && SAXIHP3WDATA_delay[55]; // rv 0 + assign SAXIHP3WDATA_in[56] = (SAXIHP3WDATA[56] !== 1'bz) && SAXIHP3WDATA_delay[56]; // rv 0 + assign SAXIHP3WDATA_in[57] = (SAXIHP3WDATA[57] !== 1'bz) && SAXIHP3WDATA_delay[57]; // rv 0 + assign SAXIHP3WDATA_in[58] = (SAXIHP3WDATA[58] !== 1'bz) && SAXIHP3WDATA_delay[58]; // rv 0 + assign SAXIHP3WDATA_in[59] = (SAXIHP3WDATA[59] !== 1'bz) && SAXIHP3WDATA_delay[59]; // rv 0 + assign SAXIHP3WDATA_in[5] = (SAXIHP3WDATA[5] !== 1'bz) && SAXIHP3WDATA_delay[5]; // rv 0 + assign SAXIHP3WDATA_in[60] = (SAXIHP3WDATA[60] !== 1'bz) && SAXIHP3WDATA_delay[60]; // rv 0 + assign SAXIHP3WDATA_in[61] = (SAXIHP3WDATA[61] !== 1'bz) && SAXIHP3WDATA_delay[61]; // rv 0 + assign SAXIHP3WDATA_in[62] = (SAXIHP3WDATA[62] !== 1'bz) && SAXIHP3WDATA_delay[62]; // rv 0 + assign SAXIHP3WDATA_in[63] = (SAXIHP3WDATA[63] !== 1'bz) && SAXIHP3WDATA_delay[63]; // rv 0 + assign SAXIHP3WDATA_in[6] = (SAXIHP3WDATA[6] !== 1'bz) && SAXIHP3WDATA_delay[6]; // rv 0 + assign SAXIHP3WDATA_in[7] = (SAXIHP3WDATA[7] !== 1'bz) && SAXIHP3WDATA_delay[7]; // rv 0 + assign SAXIHP3WDATA_in[8] = (SAXIHP3WDATA[8] !== 1'bz) && SAXIHP3WDATA_delay[8]; // rv 0 + assign SAXIHP3WDATA_in[9] = (SAXIHP3WDATA[9] !== 1'bz) && SAXIHP3WDATA_delay[9]; // rv 0 + assign SAXIHP3WID_in[0] = (SAXIHP3WID[0] !== 1'bz) && SAXIHP3WID_delay[0]; // rv 0 + assign SAXIHP3WID_in[1] = (SAXIHP3WID[1] !== 1'bz) && SAXIHP3WID_delay[1]; // rv 0 + assign SAXIHP3WID_in[2] = (SAXIHP3WID[2] !== 1'bz) && SAXIHP3WID_delay[2]; // rv 0 + assign SAXIHP3WID_in[3] = (SAXIHP3WID[3] !== 1'bz) && SAXIHP3WID_delay[3]; // rv 0 + assign SAXIHP3WID_in[4] = (SAXIHP3WID[4] !== 1'bz) && SAXIHP3WID_delay[4]; // rv 0 + assign SAXIHP3WID_in[5] = (SAXIHP3WID[5] !== 1'bz) && SAXIHP3WID_delay[5]; // rv 0 + assign SAXIHP3WLAST_in = (SAXIHP3WLAST !== 1'bz) && SAXIHP3WLAST_delay; // rv 0 + assign SAXIHP3WSTRB_in[0] = (SAXIHP3WSTRB[0] !== 1'bz) && SAXIHP3WSTRB_delay[0]; // rv 0 + assign SAXIHP3WSTRB_in[1] = (SAXIHP3WSTRB[1] !== 1'bz) && SAXIHP3WSTRB_delay[1]; // rv 0 + assign SAXIHP3WSTRB_in[2] = (SAXIHP3WSTRB[2] !== 1'bz) && SAXIHP3WSTRB_delay[2]; // rv 0 + assign SAXIHP3WSTRB_in[3] = (SAXIHP3WSTRB[3] !== 1'bz) && SAXIHP3WSTRB_delay[3]; // rv 0 + assign SAXIHP3WSTRB_in[4] = (SAXIHP3WSTRB[4] !== 1'bz) && SAXIHP3WSTRB_delay[4]; // rv 0 + assign SAXIHP3WSTRB_in[5] = (SAXIHP3WSTRB[5] !== 1'bz) && SAXIHP3WSTRB_delay[5]; // rv 0 + assign SAXIHP3WSTRB_in[6] = (SAXIHP3WSTRB[6] !== 1'bz) && SAXIHP3WSTRB_delay[6]; // rv 0 + assign SAXIHP3WSTRB_in[7] = (SAXIHP3WSTRB[7] !== 1'bz) && SAXIHP3WSTRB_delay[7]; // rv 0 + assign SAXIHP3WVALID_in = (SAXIHP3WVALID !== 1'bz) && SAXIHP3WVALID_delay; // rv 0 +`else + assign DMA0ACLK_in = (DMA0ACLK !== 1'bz) && DMA0ACLK; // rv 0 + assign DMA0DAREADY_in = (DMA0DAREADY !== 1'bz) && DMA0DAREADY; // rv 0 + assign DMA0DRLAST_in = (DMA0DRLAST !== 1'bz) && DMA0DRLAST; // rv 0 + assign DMA0DRTYPE_in[0] = (DMA0DRTYPE[0] !== 1'bz) && DMA0DRTYPE[0]; // rv 0 + assign DMA0DRTYPE_in[1] = (DMA0DRTYPE[1] !== 1'bz) && DMA0DRTYPE[1]; // rv 0 + assign DMA0DRVALID_in = (DMA0DRVALID !== 1'bz) && DMA0DRVALID; // rv 0 + assign DMA1ACLK_in = (DMA1ACLK !== 1'bz) && DMA1ACLK; // rv 0 + assign DMA1DAREADY_in = (DMA1DAREADY !== 1'bz) && DMA1DAREADY; // rv 0 + assign DMA1DRLAST_in = (DMA1DRLAST !== 1'bz) && DMA1DRLAST; // rv 0 + assign DMA1DRTYPE_in[0] = (DMA1DRTYPE[0] !== 1'bz) && DMA1DRTYPE[0]; // rv 0 + assign DMA1DRTYPE_in[1] = (DMA1DRTYPE[1] !== 1'bz) && DMA1DRTYPE[1]; // rv 0 + assign DMA1DRVALID_in = (DMA1DRVALID !== 1'bz) && DMA1DRVALID; // rv 0 + assign DMA2ACLK_in = (DMA2ACLK !== 1'bz) && DMA2ACLK; // rv 0 + assign DMA2DAREADY_in = (DMA2DAREADY !== 1'bz) && DMA2DAREADY; // rv 0 + assign DMA2DRLAST_in = (DMA2DRLAST !== 1'bz) && DMA2DRLAST; // rv 0 + assign DMA2DRTYPE_in[0] = (DMA2DRTYPE[0] !== 1'bz) && DMA2DRTYPE[0]; // rv 0 + assign DMA2DRTYPE_in[1] = (DMA2DRTYPE[1] !== 1'bz) && DMA2DRTYPE[1]; // rv 0 + assign DMA2DRVALID_in = (DMA2DRVALID !== 1'bz) && DMA2DRVALID; // rv 0 + assign DMA3ACLK_in = (DMA3ACLK !== 1'bz) && DMA3ACLK; // rv 0 + assign DMA3DAREADY_in = (DMA3DAREADY !== 1'bz) && DMA3DAREADY; // rv 0 + assign DMA3DRLAST_in = (DMA3DRLAST !== 1'bz) && DMA3DRLAST; // rv 0 + assign DMA3DRTYPE_in[0] = (DMA3DRTYPE[0] !== 1'bz) && DMA3DRTYPE[0]; // rv 0 + assign DMA3DRTYPE_in[1] = (DMA3DRTYPE[1] !== 1'bz) && DMA3DRTYPE[1]; // rv 0 + assign DMA3DRVALID_in = (DMA3DRVALID !== 1'bz) && DMA3DRVALID; // rv 0 + assign EMIOENET0GMIIRXCLK_in = (EMIOENET0GMIIRXCLK !== 1'bz) && EMIOENET0GMIIRXCLK; // rv 0 + assign EMIOENET0GMIIRXDV_in = (EMIOENET0GMIIRXDV !== 1'bz) && EMIOENET0GMIIRXDV; // rv 0 + assign EMIOENET0GMIIRXD_in[0] = (EMIOENET0GMIIRXD[0] !== 1'bz) && EMIOENET0GMIIRXD[0]; // rv 0 + assign EMIOENET0GMIIRXD_in[1] = (EMIOENET0GMIIRXD[1] !== 1'bz) && EMIOENET0GMIIRXD[1]; // rv 0 + assign EMIOENET0GMIIRXD_in[2] = (EMIOENET0GMIIRXD[2] !== 1'bz) && EMIOENET0GMIIRXD[2]; // rv 0 + assign EMIOENET0GMIIRXD_in[3] = (EMIOENET0GMIIRXD[3] !== 1'bz) && EMIOENET0GMIIRXD[3]; // rv 0 + assign EMIOENET0GMIIRXD_in[4] = (EMIOENET0GMIIRXD[4] !== 1'bz) && EMIOENET0GMIIRXD[4]; // rv 0 + assign EMIOENET0GMIIRXD_in[5] = (EMIOENET0GMIIRXD[5] !== 1'bz) && EMIOENET0GMIIRXD[5]; // rv 0 + assign EMIOENET0GMIIRXD_in[6] = (EMIOENET0GMIIRXD[6] !== 1'bz) && EMIOENET0GMIIRXD[6]; // rv 0 + assign EMIOENET0GMIIRXD_in[7] = (EMIOENET0GMIIRXD[7] !== 1'bz) && EMIOENET0GMIIRXD[7]; // rv 0 + assign EMIOENET0GMIIRXER_in = (EMIOENET0GMIIRXER !== 1'bz) && EMIOENET0GMIIRXER; // rv 0 + assign EMIOENET1GMIIRXCLK_in = (EMIOENET1GMIIRXCLK !== 1'bz) && EMIOENET1GMIIRXCLK; // rv 0 + assign EMIOENET1GMIIRXDV_in = (EMIOENET1GMIIRXDV !== 1'bz) && EMIOENET1GMIIRXDV; // rv 0 + assign EMIOENET1GMIIRXD_in[0] = (EMIOENET1GMIIRXD[0] !== 1'bz) && EMIOENET1GMIIRXD[0]; // rv 0 + assign EMIOENET1GMIIRXD_in[1] = (EMIOENET1GMIIRXD[1] !== 1'bz) && EMIOENET1GMIIRXD[1]; // rv 0 + assign EMIOENET1GMIIRXD_in[2] = (EMIOENET1GMIIRXD[2] !== 1'bz) && EMIOENET1GMIIRXD[2]; // rv 0 + assign EMIOENET1GMIIRXD_in[3] = (EMIOENET1GMIIRXD[3] !== 1'bz) && EMIOENET1GMIIRXD[3]; // rv 0 + assign EMIOENET1GMIIRXD_in[4] = (EMIOENET1GMIIRXD[4] !== 1'bz) && EMIOENET1GMIIRXD[4]; // rv 0 + assign EMIOENET1GMIIRXD_in[5] = (EMIOENET1GMIIRXD[5] !== 1'bz) && EMIOENET1GMIIRXD[5]; // rv 0 + assign EMIOENET1GMIIRXD_in[6] = (EMIOENET1GMIIRXD[6] !== 1'bz) && EMIOENET1GMIIRXD[6]; // rv 0 + assign EMIOENET1GMIIRXD_in[7] = (EMIOENET1GMIIRXD[7] !== 1'bz) && EMIOENET1GMIIRXD[7]; // rv 0 + assign EMIOENET1GMIIRXER_in = (EMIOENET1GMIIRXER !== 1'bz) && EMIOENET1GMIIRXER; // rv 0 + assign EMIOPJTAGTCK_in = (EMIOPJTAGTCK !== 1'bz) && EMIOPJTAGTCK; // rv 0 + assign EMIOPJTAGTDI_in = (EMIOPJTAGTDI !== 1'bz) && EMIOPJTAGTDI; // rv 0 + assign EMIOPJTAGTMS_in = (EMIOPJTAGTMS !== 1'bz) && EMIOPJTAGTMS; // rv 0 + assign EMIOSDIO0CLKFB_in = (EMIOSDIO0CLKFB !== 1'bz) && EMIOSDIO0CLKFB; // rv 0 + assign EMIOSDIO0CMDI_in = (EMIOSDIO0CMDI !== 1'bz) && EMIOSDIO0CMDI; // rv 0 + assign EMIOSDIO0DATAI_in[0] = (EMIOSDIO0DATAI[0] !== 1'bz) && EMIOSDIO0DATAI[0]; // rv 0 + assign EMIOSDIO0DATAI_in[1] = (EMIOSDIO0DATAI[1] !== 1'bz) && EMIOSDIO0DATAI[1]; // rv 0 + assign EMIOSDIO0DATAI_in[2] = (EMIOSDIO0DATAI[2] !== 1'bz) && EMIOSDIO0DATAI[2]; // rv 0 + assign EMIOSDIO0DATAI_in[3] = (EMIOSDIO0DATAI[3] !== 1'bz) && EMIOSDIO0DATAI[3]; // rv 0 + assign EMIOSDIO1CLKFB_in = (EMIOSDIO1CLKFB !== 1'bz) && EMIOSDIO1CLKFB; // rv 0 + assign EMIOSDIO1CMDI_in = (EMIOSDIO1CMDI !== 1'bz) && EMIOSDIO1CMDI; // rv 0 + assign EMIOSDIO1DATAI_in[0] = (EMIOSDIO1DATAI[0] !== 1'bz) && EMIOSDIO1DATAI[0]; // rv 0 + assign EMIOSDIO1DATAI_in[1] = (EMIOSDIO1DATAI[1] !== 1'bz) && EMIOSDIO1DATAI[1]; // rv 0 + assign EMIOSDIO1DATAI_in[2] = (EMIOSDIO1DATAI[2] !== 1'bz) && EMIOSDIO1DATAI[2]; // rv 0 + assign EMIOSDIO1DATAI_in[3] = (EMIOSDIO1DATAI[3] !== 1'bz) && EMIOSDIO1DATAI[3]; // rv 0 + assign FTMDTRACEINATID_in[0] = (FTMDTRACEINATID[0] !== 1'bz) && FTMDTRACEINATID[0]; // rv 0 + assign FTMDTRACEINATID_in[1] = (FTMDTRACEINATID[1] !== 1'bz) && FTMDTRACEINATID[1]; // rv 0 + assign FTMDTRACEINATID_in[2] = (FTMDTRACEINATID[2] !== 1'bz) && FTMDTRACEINATID[2]; // rv 0 + assign FTMDTRACEINATID_in[3] = (FTMDTRACEINATID[3] !== 1'bz) && FTMDTRACEINATID[3]; // rv 0 + assign FTMDTRACEINCLOCK_in = (FTMDTRACEINCLOCK !== 1'bz) && FTMDTRACEINCLOCK; // rv 0 + assign FTMDTRACEINDATA_in[0] = (FTMDTRACEINDATA[0] !== 1'bz) && FTMDTRACEINDATA[0]; // rv 0 + assign FTMDTRACEINDATA_in[10] = (FTMDTRACEINDATA[10] !== 1'bz) && FTMDTRACEINDATA[10]; // rv 0 + assign FTMDTRACEINDATA_in[11] = (FTMDTRACEINDATA[11] !== 1'bz) && FTMDTRACEINDATA[11]; // rv 0 + assign FTMDTRACEINDATA_in[12] = (FTMDTRACEINDATA[12] !== 1'bz) && FTMDTRACEINDATA[12]; // rv 0 + assign FTMDTRACEINDATA_in[13] = (FTMDTRACEINDATA[13] !== 1'bz) && FTMDTRACEINDATA[13]; // rv 0 + assign FTMDTRACEINDATA_in[14] = (FTMDTRACEINDATA[14] !== 1'bz) && FTMDTRACEINDATA[14]; // rv 0 + assign FTMDTRACEINDATA_in[15] = (FTMDTRACEINDATA[15] !== 1'bz) && FTMDTRACEINDATA[15]; // rv 0 + assign FTMDTRACEINDATA_in[16] = (FTMDTRACEINDATA[16] !== 1'bz) && FTMDTRACEINDATA[16]; // rv 0 + assign FTMDTRACEINDATA_in[17] = (FTMDTRACEINDATA[17] !== 1'bz) && FTMDTRACEINDATA[17]; // rv 0 + assign FTMDTRACEINDATA_in[18] = (FTMDTRACEINDATA[18] !== 1'bz) && FTMDTRACEINDATA[18]; // rv 0 + assign FTMDTRACEINDATA_in[19] = (FTMDTRACEINDATA[19] !== 1'bz) && FTMDTRACEINDATA[19]; // rv 0 + assign FTMDTRACEINDATA_in[1] = (FTMDTRACEINDATA[1] !== 1'bz) && FTMDTRACEINDATA[1]; // rv 0 + assign FTMDTRACEINDATA_in[20] = (FTMDTRACEINDATA[20] !== 1'bz) && FTMDTRACEINDATA[20]; // rv 0 + assign FTMDTRACEINDATA_in[21] = (FTMDTRACEINDATA[21] !== 1'bz) && FTMDTRACEINDATA[21]; // rv 0 + assign FTMDTRACEINDATA_in[22] = (FTMDTRACEINDATA[22] !== 1'bz) && FTMDTRACEINDATA[22]; // rv 0 + assign FTMDTRACEINDATA_in[23] = (FTMDTRACEINDATA[23] !== 1'bz) && FTMDTRACEINDATA[23]; // rv 0 + assign FTMDTRACEINDATA_in[24] = (FTMDTRACEINDATA[24] !== 1'bz) && FTMDTRACEINDATA[24]; // rv 0 + assign FTMDTRACEINDATA_in[25] = (FTMDTRACEINDATA[25] !== 1'bz) && FTMDTRACEINDATA[25]; // rv 0 + assign FTMDTRACEINDATA_in[26] = (FTMDTRACEINDATA[26] !== 1'bz) && FTMDTRACEINDATA[26]; // rv 0 + assign FTMDTRACEINDATA_in[27] = (FTMDTRACEINDATA[27] !== 1'bz) && FTMDTRACEINDATA[27]; // rv 0 + assign FTMDTRACEINDATA_in[28] = (FTMDTRACEINDATA[28] !== 1'bz) && FTMDTRACEINDATA[28]; // rv 0 + assign FTMDTRACEINDATA_in[29] = (FTMDTRACEINDATA[29] !== 1'bz) && FTMDTRACEINDATA[29]; // rv 0 + assign FTMDTRACEINDATA_in[2] = (FTMDTRACEINDATA[2] !== 1'bz) && FTMDTRACEINDATA[2]; // rv 0 + assign FTMDTRACEINDATA_in[30] = (FTMDTRACEINDATA[30] !== 1'bz) && FTMDTRACEINDATA[30]; // rv 0 + assign FTMDTRACEINDATA_in[31] = (FTMDTRACEINDATA[31] !== 1'bz) && FTMDTRACEINDATA[31]; // rv 0 + assign FTMDTRACEINDATA_in[3] = (FTMDTRACEINDATA[3] !== 1'bz) && FTMDTRACEINDATA[3]; // rv 0 + assign FTMDTRACEINDATA_in[4] = (FTMDTRACEINDATA[4] !== 1'bz) && FTMDTRACEINDATA[4]; // rv 0 + assign FTMDTRACEINDATA_in[5] = (FTMDTRACEINDATA[5] !== 1'bz) && FTMDTRACEINDATA[5]; // rv 0 + assign FTMDTRACEINDATA_in[6] = (FTMDTRACEINDATA[6] !== 1'bz) && FTMDTRACEINDATA[6]; // rv 0 + assign FTMDTRACEINDATA_in[7] = (FTMDTRACEINDATA[7] !== 1'bz) && FTMDTRACEINDATA[7]; // rv 0 + assign FTMDTRACEINDATA_in[8] = (FTMDTRACEINDATA[8] !== 1'bz) && FTMDTRACEINDATA[8]; // rv 0 + assign FTMDTRACEINDATA_in[9] = (FTMDTRACEINDATA[9] !== 1'bz) && FTMDTRACEINDATA[9]; // rv 0 + assign FTMDTRACEINVALID_in = (FTMDTRACEINVALID !== 1'bz) && FTMDTRACEINVALID; // rv 0 + assign MAXIGP0ACLK_in = (MAXIGP0ACLK !== 1'bz) && MAXIGP0ACLK; // rv 0 + assign MAXIGP0ARREADY_in = (MAXIGP0ARREADY !== 1'bz) && MAXIGP0ARREADY; // rv 0 + assign MAXIGP0AWREADY_in = (MAXIGP0AWREADY !== 1'bz) && MAXIGP0AWREADY; // rv 0 + assign MAXIGP0BID_in[0] = (MAXIGP0BID[0] !== 1'bz) && MAXIGP0BID[0]; // rv 0 + assign MAXIGP0BID_in[10] = (MAXIGP0BID[10] !== 1'bz) && MAXIGP0BID[10]; // rv 0 + assign MAXIGP0BID_in[11] = (MAXIGP0BID[11] !== 1'bz) && MAXIGP0BID[11]; // rv 0 + assign MAXIGP0BID_in[1] = (MAXIGP0BID[1] !== 1'bz) && MAXIGP0BID[1]; // rv 0 + assign MAXIGP0BID_in[2] = (MAXIGP0BID[2] !== 1'bz) && MAXIGP0BID[2]; // rv 0 + assign MAXIGP0BID_in[3] = (MAXIGP0BID[3] !== 1'bz) && MAXIGP0BID[3]; // rv 0 + assign MAXIGP0BID_in[4] = (MAXIGP0BID[4] !== 1'bz) && MAXIGP0BID[4]; // rv 0 + assign MAXIGP0BID_in[5] = (MAXIGP0BID[5] !== 1'bz) && MAXIGP0BID[5]; // rv 0 + assign MAXIGP0BID_in[6] = (MAXIGP0BID[6] !== 1'bz) && MAXIGP0BID[6]; // rv 0 + assign MAXIGP0BID_in[7] = (MAXIGP0BID[7] !== 1'bz) && MAXIGP0BID[7]; // rv 0 + assign MAXIGP0BID_in[8] = (MAXIGP0BID[8] !== 1'bz) && MAXIGP0BID[8]; // rv 0 + assign MAXIGP0BID_in[9] = (MAXIGP0BID[9] !== 1'bz) && MAXIGP0BID[9]; // rv 0 + assign MAXIGP0BRESP_in[0] = (MAXIGP0BRESP[0] !== 1'bz) && MAXIGP0BRESP[0]; // rv 0 + assign MAXIGP0BRESP_in[1] = (MAXIGP0BRESP[1] !== 1'bz) && MAXIGP0BRESP[1]; // rv 0 + assign MAXIGP0BVALID_in = (MAXIGP0BVALID !== 1'bz) && MAXIGP0BVALID; // rv 0 + assign MAXIGP0RDATA_in[0] = (MAXIGP0RDATA[0] !== 1'bz) && MAXIGP0RDATA[0]; // rv 0 + assign MAXIGP0RDATA_in[10] = (MAXIGP0RDATA[10] !== 1'bz) && MAXIGP0RDATA[10]; // rv 0 + assign MAXIGP0RDATA_in[11] = (MAXIGP0RDATA[11] !== 1'bz) && MAXIGP0RDATA[11]; // rv 0 + assign MAXIGP0RDATA_in[12] = (MAXIGP0RDATA[12] !== 1'bz) && MAXIGP0RDATA[12]; // rv 0 + assign MAXIGP0RDATA_in[13] = (MAXIGP0RDATA[13] !== 1'bz) && MAXIGP0RDATA[13]; // rv 0 + assign MAXIGP0RDATA_in[14] = (MAXIGP0RDATA[14] !== 1'bz) && MAXIGP0RDATA[14]; // rv 0 + assign MAXIGP0RDATA_in[15] = (MAXIGP0RDATA[15] !== 1'bz) && MAXIGP0RDATA[15]; // rv 0 + assign MAXIGP0RDATA_in[16] = (MAXIGP0RDATA[16] !== 1'bz) && MAXIGP0RDATA[16]; // rv 0 + assign MAXIGP0RDATA_in[17] = (MAXIGP0RDATA[17] !== 1'bz) && MAXIGP0RDATA[17]; // rv 0 + assign MAXIGP0RDATA_in[18] = (MAXIGP0RDATA[18] !== 1'bz) && MAXIGP0RDATA[18]; // rv 0 + assign MAXIGP0RDATA_in[19] = (MAXIGP0RDATA[19] !== 1'bz) && MAXIGP0RDATA[19]; // rv 0 + assign MAXIGP0RDATA_in[1] = (MAXIGP0RDATA[1] !== 1'bz) && MAXIGP0RDATA[1]; // rv 0 + assign MAXIGP0RDATA_in[20] = (MAXIGP0RDATA[20] !== 1'bz) && MAXIGP0RDATA[20]; // rv 0 + assign MAXIGP0RDATA_in[21] = (MAXIGP0RDATA[21] !== 1'bz) && MAXIGP0RDATA[21]; // rv 0 + assign MAXIGP0RDATA_in[22] = (MAXIGP0RDATA[22] !== 1'bz) && MAXIGP0RDATA[22]; // rv 0 + assign MAXIGP0RDATA_in[23] = (MAXIGP0RDATA[23] !== 1'bz) && MAXIGP0RDATA[23]; // rv 0 + assign MAXIGP0RDATA_in[24] = (MAXIGP0RDATA[24] !== 1'bz) && MAXIGP0RDATA[24]; // rv 0 + assign MAXIGP0RDATA_in[25] = (MAXIGP0RDATA[25] !== 1'bz) && MAXIGP0RDATA[25]; // rv 0 + assign MAXIGP0RDATA_in[26] = (MAXIGP0RDATA[26] !== 1'bz) && MAXIGP0RDATA[26]; // rv 0 + assign MAXIGP0RDATA_in[27] = (MAXIGP0RDATA[27] !== 1'bz) && MAXIGP0RDATA[27]; // rv 0 + assign MAXIGP0RDATA_in[28] = (MAXIGP0RDATA[28] !== 1'bz) && MAXIGP0RDATA[28]; // rv 0 + assign MAXIGP0RDATA_in[29] = (MAXIGP0RDATA[29] !== 1'bz) && MAXIGP0RDATA[29]; // rv 0 + assign MAXIGP0RDATA_in[2] = (MAXIGP0RDATA[2] !== 1'bz) && MAXIGP0RDATA[2]; // rv 0 + assign MAXIGP0RDATA_in[30] = (MAXIGP0RDATA[30] !== 1'bz) && MAXIGP0RDATA[30]; // rv 0 + assign MAXIGP0RDATA_in[31] = (MAXIGP0RDATA[31] !== 1'bz) && MAXIGP0RDATA[31]; // rv 0 + assign MAXIGP0RDATA_in[3] = (MAXIGP0RDATA[3] !== 1'bz) && MAXIGP0RDATA[3]; // rv 0 + assign MAXIGP0RDATA_in[4] = (MAXIGP0RDATA[4] !== 1'bz) && MAXIGP0RDATA[4]; // rv 0 + assign MAXIGP0RDATA_in[5] = (MAXIGP0RDATA[5] !== 1'bz) && MAXIGP0RDATA[5]; // rv 0 + assign MAXIGP0RDATA_in[6] = (MAXIGP0RDATA[6] !== 1'bz) && MAXIGP0RDATA[6]; // rv 0 + assign MAXIGP0RDATA_in[7] = (MAXIGP0RDATA[7] !== 1'bz) && MAXIGP0RDATA[7]; // rv 0 + assign MAXIGP0RDATA_in[8] = (MAXIGP0RDATA[8] !== 1'bz) && MAXIGP0RDATA[8]; // rv 0 + assign MAXIGP0RDATA_in[9] = (MAXIGP0RDATA[9] !== 1'bz) && MAXIGP0RDATA[9]; // rv 0 + assign MAXIGP0RID_in[0] = (MAXIGP0RID[0] !== 1'bz) && MAXIGP0RID[0]; // rv 0 + assign MAXIGP0RID_in[10] = (MAXIGP0RID[10] !== 1'bz) && MAXIGP0RID[10]; // rv 0 + assign MAXIGP0RID_in[11] = (MAXIGP0RID[11] !== 1'bz) && MAXIGP0RID[11]; // rv 0 + assign MAXIGP0RID_in[1] = (MAXIGP0RID[1] !== 1'bz) && MAXIGP0RID[1]; // rv 0 + assign MAXIGP0RID_in[2] = (MAXIGP0RID[2] !== 1'bz) && MAXIGP0RID[2]; // rv 0 + assign MAXIGP0RID_in[3] = (MAXIGP0RID[3] !== 1'bz) && MAXIGP0RID[3]; // rv 0 + assign MAXIGP0RID_in[4] = (MAXIGP0RID[4] !== 1'bz) && MAXIGP0RID[4]; // rv 0 + assign MAXIGP0RID_in[5] = (MAXIGP0RID[5] !== 1'bz) && MAXIGP0RID[5]; // rv 0 + assign MAXIGP0RID_in[6] = (MAXIGP0RID[6] !== 1'bz) && MAXIGP0RID[6]; // rv 0 + assign MAXIGP0RID_in[7] = (MAXIGP0RID[7] !== 1'bz) && MAXIGP0RID[7]; // rv 0 + assign MAXIGP0RID_in[8] = (MAXIGP0RID[8] !== 1'bz) && MAXIGP0RID[8]; // rv 0 + assign MAXIGP0RID_in[9] = (MAXIGP0RID[9] !== 1'bz) && MAXIGP0RID[9]; // rv 0 + assign MAXIGP0RLAST_in = (MAXIGP0RLAST !== 1'bz) && MAXIGP0RLAST; // rv 0 + assign MAXIGP0RRESP_in[0] = (MAXIGP0RRESP[0] !== 1'bz) && MAXIGP0RRESP[0]; // rv 0 + assign MAXIGP0RRESP_in[1] = (MAXIGP0RRESP[1] !== 1'bz) && MAXIGP0RRESP[1]; // rv 0 + assign MAXIGP0RVALID_in = (MAXIGP0RVALID !== 1'bz) && MAXIGP0RVALID; // rv 0 + assign MAXIGP0WREADY_in = (MAXIGP0WREADY !== 1'bz) && MAXIGP0WREADY; // rv 0 + assign MAXIGP1ACLK_in = (MAXIGP1ACLK !== 1'bz) && MAXIGP1ACLK; // rv 0 + assign MAXIGP1ARREADY_in = (MAXIGP1ARREADY !== 1'bz) && MAXIGP1ARREADY; // rv 0 + assign MAXIGP1AWREADY_in = (MAXIGP1AWREADY !== 1'bz) && MAXIGP1AWREADY; // rv 0 + assign MAXIGP1BID_in[0] = (MAXIGP1BID[0] !== 1'bz) && MAXIGP1BID[0]; // rv 0 + assign MAXIGP1BID_in[10] = (MAXIGP1BID[10] !== 1'bz) && MAXIGP1BID[10]; // rv 0 + assign MAXIGP1BID_in[11] = (MAXIGP1BID[11] !== 1'bz) && MAXIGP1BID[11]; // rv 0 + assign MAXIGP1BID_in[1] = (MAXIGP1BID[1] !== 1'bz) && MAXIGP1BID[1]; // rv 0 + assign MAXIGP1BID_in[2] = (MAXIGP1BID[2] !== 1'bz) && MAXIGP1BID[2]; // rv 0 + assign MAXIGP1BID_in[3] = (MAXIGP1BID[3] !== 1'bz) && MAXIGP1BID[3]; // rv 0 + assign MAXIGP1BID_in[4] = (MAXIGP1BID[4] !== 1'bz) && MAXIGP1BID[4]; // rv 0 + assign MAXIGP1BID_in[5] = (MAXIGP1BID[5] !== 1'bz) && MAXIGP1BID[5]; // rv 0 + assign MAXIGP1BID_in[6] = (MAXIGP1BID[6] !== 1'bz) && MAXIGP1BID[6]; // rv 0 + assign MAXIGP1BID_in[7] = (MAXIGP1BID[7] !== 1'bz) && MAXIGP1BID[7]; // rv 0 + assign MAXIGP1BID_in[8] = (MAXIGP1BID[8] !== 1'bz) && MAXIGP1BID[8]; // rv 0 + assign MAXIGP1BID_in[9] = (MAXIGP1BID[9] !== 1'bz) && MAXIGP1BID[9]; // rv 0 + assign MAXIGP1BRESP_in[0] = (MAXIGP1BRESP[0] !== 1'bz) && MAXIGP1BRESP[0]; // rv 0 + assign MAXIGP1BRESP_in[1] = (MAXIGP1BRESP[1] !== 1'bz) && MAXIGP1BRESP[1]; // rv 0 + assign MAXIGP1BVALID_in = (MAXIGP1BVALID !== 1'bz) && MAXIGP1BVALID; // rv 0 + assign MAXIGP1RDATA_in[0] = (MAXIGP1RDATA[0] !== 1'bz) && MAXIGP1RDATA[0]; // rv 0 + assign MAXIGP1RDATA_in[10] = (MAXIGP1RDATA[10] !== 1'bz) && MAXIGP1RDATA[10]; // rv 0 + assign MAXIGP1RDATA_in[11] = (MAXIGP1RDATA[11] !== 1'bz) && MAXIGP1RDATA[11]; // rv 0 + assign MAXIGP1RDATA_in[12] = (MAXIGP1RDATA[12] !== 1'bz) && MAXIGP1RDATA[12]; // rv 0 + assign MAXIGP1RDATA_in[13] = (MAXIGP1RDATA[13] !== 1'bz) && MAXIGP1RDATA[13]; // rv 0 + assign MAXIGP1RDATA_in[14] = (MAXIGP1RDATA[14] !== 1'bz) && MAXIGP1RDATA[14]; // rv 0 + assign MAXIGP1RDATA_in[15] = (MAXIGP1RDATA[15] !== 1'bz) && MAXIGP1RDATA[15]; // rv 0 + assign MAXIGP1RDATA_in[16] = (MAXIGP1RDATA[16] !== 1'bz) && MAXIGP1RDATA[16]; // rv 0 + assign MAXIGP1RDATA_in[17] = (MAXIGP1RDATA[17] !== 1'bz) && MAXIGP1RDATA[17]; // rv 0 + assign MAXIGP1RDATA_in[18] = (MAXIGP1RDATA[18] !== 1'bz) && MAXIGP1RDATA[18]; // rv 0 + assign MAXIGP1RDATA_in[19] = (MAXIGP1RDATA[19] !== 1'bz) && MAXIGP1RDATA[19]; // rv 0 + assign MAXIGP1RDATA_in[1] = (MAXIGP1RDATA[1] !== 1'bz) && MAXIGP1RDATA[1]; // rv 0 + assign MAXIGP1RDATA_in[20] = (MAXIGP1RDATA[20] !== 1'bz) && MAXIGP1RDATA[20]; // rv 0 + assign MAXIGP1RDATA_in[21] = (MAXIGP1RDATA[21] !== 1'bz) && MAXIGP1RDATA[21]; // rv 0 + assign MAXIGP1RDATA_in[22] = (MAXIGP1RDATA[22] !== 1'bz) && MAXIGP1RDATA[22]; // rv 0 + assign MAXIGP1RDATA_in[23] = (MAXIGP1RDATA[23] !== 1'bz) && MAXIGP1RDATA[23]; // rv 0 + assign MAXIGP1RDATA_in[24] = (MAXIGP1RDATA[24] !== 1'bz) && MAXIGP1RDATA[24]; // rv 0 + assign MAXIGP1RDATA_in[25] = (MAXIGP1RDATA[25] !== 1'bz) && MAXIGP1RDATA[25]; // rv 0 + assign MAXIGP1RDATA_in[26] = (MAXIGP1RDATA[26] !== 1'bz) && MAXIGP1RDATA[26]; // rv 0 + assign MAXIGP1RDATA_in[27] = (MAXIGP1RDATA[27] !== 1'bz) && MAXIGP1RDATA[27]; // rv 0 + assign MAXIGP1RDATA_in[28] = (MAXIGP1RDATA[28] !== 1'bz) && MAXIGP1RDATA[28]; // rv 0 + assign MAXIGP1RDATA_in[29] = (MAXIGP1RDATA[29] !== 1'bz) && MAXIGP1RDATA[29]; // rv 0 + assign MAXIGP1RDATA_in[2] = (MAXIGP1RDATA[2] !== 1'bz) && MAXIGP1RDATA[2]; // rv 0 + assign MAXIGP1RDATA_in[30] = (MAXIGP1RDATA[30] !== 1'bz) && MAXIGP1RDATA[30]; // rv 0 + assign MAXIGP1RDATA_in[31] = (MAXIGP1RDATA[31] !== 1'bz) && MAXIGP1RDATA[31]; // rv 0 + assign MAXIGP1RDATA_in[3] = (MAXIGP1RDATA[3] !== 1'bz) && MAXIGP1RDATA[3]; // rv 0 + assign MAXIGP1RDATA_in[4] = (MAXIGP1RDATA[4] !== 1'bz) && MAXIGP1RDATA[4]; // rv 0 + assign MAXIGP1RDATA_in[5] = (MAXIGP1RDATA[5] !== 1'bz) && MAXIGP1RDATA[5]; // rv 0 + assign MAXIGP1RDATA_in[6] = (MAXIGP1RDATA[6] !== 1'bz) && MAXIGP1RDATA[6]; // rv 0 + assign MAXIGP1RDATA_in[7] = (MAXIGP1RDATA[7] !== 1'bz) && MAXIGP1RDATA[7]; // rv 0 + assign MAXIGP1RDATA_in[8] = (MAXIGP1RDATA[8] !== 1'bz) && MAXIGP1RDATA[8]; // rv 0 + assign MAXIGP1RDATA_in[9] = (MAXIGP1RDATA[9] !== 1'bz) && MAXIGP1RDATA[9]; // rv 0 + assign MAXIGP1RID_in[0] = (MAXIGP1RID[0] !== 1'bz) && MAXIGP1RID[0]; // rv 0 + assign MAXIGP1RID_in[10] = (MAXIGP1RID[10] !== 1'bz) && MAXIGP1RID[10]; // rv 0 + assign MAXIGP1RID_in[11] = (MAXIGP1RID[11] !== 1'bz) && MAXIGP1RID[11]; // rv 0 + assign MAXIGP1RID_in[1] = (MAXIGP1RID[1] !== 1'bz) && MAXIGP1RID[1]; // rv 0 + assign MAXIGP1RID_in[2] = (MAXIGP1RID[2] !== 1'bz) && MAXIGP1RID[2]; // rv 0 + assign MAXIGP1RID_in[3] = (MAXIGP1RID[3] !== 1'bz) && MAXIGP1RID[3]; // rv 0 + assign MAXIGP1RID_in[4] = (MAXIGP1RID[4] !== 1'bz) && MAXIGP1RID[4]; // rv 0 + assign MAXIGP1RID_in[5] = (MAXIGP1RID[5] !== 1'bz) && MAXIGP1RID[5]; // rv 0 + assign MAXIGP1RID_in[6] = (MAXIGP1RID[6] !== 1'bz) && MAXIGP1RID[6]; // rv 0 + assign MAXIGP1RID_in[7] = (MAXIGP1RID[7] !== 1'bz) && MAXIGP1RID[7]; // rv 0 + assign MAXIGP1RID_in[8] = (MAXIGP1RID[8] !== 1'bz) && MAXIGP1RID[8]; // rv 0 + assign MAXIGP1RID_in[9] = (MAXIGP1RID[9] !== 1'bz) && MAXIGP1RID[9]; // rv 0 + assign MAXIGP1RLAST_in = (MAXIGP1RLAST !== 1'bz) && MAXIGP1RLAST; // rv 0 + assign MAXIGP1RRESP_in[0] = (MAXIGP1RRESP[0] !== 1'bz) && MAXIGP1RRESP[0]; // rv 0 + assign MAXIGP1RRESP_in[1] = (MAXIGP1RRESP[1] !== 1'bz) && MAXIGP1RRESP[1]; // rv 0 + assign MAXIGP1RVALID_in = (MAXIGP1RVALID !== 1'bz) && MAXIGP1RVALID; // rv 0 + assign MAXIGP1WREADY_in = (MAXIGP1WREADY !== 1'bz) && MAXIGP1WREADY; // rv 0 + assign SAXIACPACLK_in = (SAXIACPACLK !== 1'bz) && SAXIACPACLK; // rv 0 + assign SAXIACPARADDR_in[0] = (SAXIACPARADDR[0] !== 1'bz) && SAXIACPARADDR[0]; // rv 0 + assign SAXIACPARADDR_in[10] = (SAXIACPARADDR[10] !== 1'bz) && SAXIACPARADDR[10]; // rv 0 + assign SAXIACPARADDR_in[11] = (SAXIACPARADDR[11] !== 1'bz) && SAXIACPARADDR[11]; // rv 0 + assign SAXIACPARADDR_in[12] = (SAXIACPARADDR[12] !== 1'bz) && SAXIACPARADDR[12]; // rv 0 + assign SAXIACPARADDR_in[13] = (SAXIACPARADDR[13] !== 1'bz) && SAXIACPARADDR[13]; // rv 0 + assign SAXIACPARADDR_in[14] = (SAXIACPARADDR[14] !== 1'bz) && SAXIACPARADDR[14]; // rv 0 + assign SAXIACPARADDR_in[15] = (SAXIACPARADDR[15] !== 1'bz) && SAXIACPARADDR[15]; // rv 0 + assign SAXIACPARADDR_in[16] = (SAXIACPARADDR[16] !== 1'bz) && SAXIACPARADDR[16]; // rv 0 + assign SAXIACPARADDR_in[17] = (SAXIACPARADDR[17] !== 1'bz) && SAXIACPARADDR[17]; // rv 0 + assign SAXIACPARADDR_in[18] = (SAXIACPARADDR[18] !== 1'bz) && SAXIACPARADDR[18]; // rv 0 + assign SAXIACPARADDR_in[19] = (SAXIACPARADDR[19] !== 1'bz) && SAXIACPARADDR[19]; // rv 0 + assign SAXIACPARADDR_in[1] = (SAXIACPARADDR[1] !== 1'bz) && SAXIACPARADDR[1]; // rv 0 + assign SAXIACPARADDR_in[20] = (SAXIACPARADDR[20] !== 1'bz) && SAXIACPARADDR[20]; // rv 0 + assign SAXIACPARADDR_in[21] = (SAXIACPARADDR[21] !== 1'bz) && SAXIACPARADDR[21]; // rv 0 + assign SAXIACPARADDR_in[22] = (SAXIACPARADDR[22] !== 1'bz) && SAXIACPARADDR[22]; // rv 0 + assign SAXIACPARADDR_in[23] = (SAXIACPARADDR[23] !== 1'bz) && SAXIACPARADDR[23]; // rv 0 + assign SAXIACPARADDR_in[24] = (SAXIACPARADDR[24] !== 1'bz) && SAXIACPARADDR[24]; // rv 0 + assign SAXIACPARADDR_in[25] = (SAXIACPARADDR[25] !== 1'bz) && SAXIACPARADDR[25]; // rv 0 + assign SAXIACPARADDR_in[26] = (SAXIACPARADDR[26] !== 1'bz) && SAXIACPARADDR[26]; // rv 0 + assign SAXIACPARADDR_in[27] = (SAXIACPARADDR[27] !== 1'bz) && SAXIACPARADDR[27]; // rv 0 + assign SAXIACPARADDR_in[28] = (SAXIACPARADDR[28] !== 1'bz) && SAXIACPARADDR[28]; // rv 0 + assign SAXIACPARADDR_in[29] = (SAXIACPARADDR[29] !== 1'bz) && SAXIACPARADDR[29]; // rv 0 + assign SAXIACPARADDR_in[2] = (SAXIACPARADDR[2] !== 1'bz) && SAXIACPARADDR[2]; // rv 0 + assign SAXIACPARADDR_in[30] = (SAXIACPARADDR[30] !== 1'bz) && SAXIACPARADDR[30]; // rv 0 + assign SAXIACPARADDR_in[31] = (SAXIACPARADDR[31] !== 1'bz) && SAXIACPARADDR[31]; // rv 0 + assign SAXIACPARADDR_in[3] = (SAXIACPARADDR[3] !== 1'bz) && SAXIACPARADDR[3]; // rv 0 + assign SAXIACPARADDR_in[4] = (SAXIACPARADDR[4] !== 1'bz) && SAXIACPARADDR[4]; // rv 0 + assign SAXIACPARADDR_in[5] = (SAXIACPARADDR[5] !== 1'bz) && SAXIACPARADDR[5]; // rv 0 + assign SAXIACPARADDR_in[6] = (SAXIACPARADDR[6] !== 1'bz) && SAXIACPARADDR[6]; // rv 0 + assign SAXIACPARADDR_in[7] = (SAXIACPARADDR[7] !== 1'bz) && SAXIACPARADDR[7]; // rv 0 + assign SAXIACPARADDR_in[8] = (SAXIACPARADDR[8] !== 1'bz) && SAXIACPARADDR[8]; // rv 0 + assign SAXIACPARADDR_in[9] = (SAXIACPARADDR[9] !== 1'bz) && SAXIACPARADDR[9]; // rv 0 + assign SAXIACPARBURST_in[0] = (SAXIACPARBURST[0] !== 1'bz) && SAXIACPARBURST[0]; // rv 0 + assign SAXIACPARBURST_in[1] = (SAXIACPARBURST[1] !== 1'bz) && SAXIACPARBURST[1]; // rv 0 + assign SAXIACPARCACHE_in[0] = (SAXIACPARCACHE[0] !== 1'bz) && SAXIACPARCACHE[0]; // rv 0 + assign SAXIACPARCACHE_in[1] = (SAXIACPARCACHE[1] !== 1'bz) && SAXIACPARCACHE[1]; // rv 0 + assign SAXIACPARCACHE_in[2] = (SAXIACPARCACHE[2] !== 1'bz) && SAXIACPARCACHE[2]; // rv 0 + assign SAXIACPARCACHE_in[3] = (SAXIACPARCACHE[3] !== 1'bz) && SAXIACPARCACHE[3]; // rv 0 + assign SAXIACPARID_in[0] = (SAXIACPARID[0] !== 1'bz) && SAXIACPARID[0]; // rv 0 + assign SAXIACPARID_in[1] = (SAXIACPARID[1] !== 1'bz) && SAXIACPARID[1]; // rv 0 + assign SAXIACPARID_in[2] = (SAXIACPARID[2] !== 1'bz) && SAXIACPARID[2]; // rv 0 + assign SAXIACPARLEN_in[0] = (SAXIACPARLEN[0] !== 1'bz) && SAXIACPARLEN[0]; // rv 0 + assign SAXIACPARLEN_in[1] = (SAXIACPARLEN[1] !== 1'bz) && SAXIACPARLEN[1]; // rv 0 + assign SAXIACPARLEN_in[2] = (SAXIACPARLEN[2] !== 1'bz) && SAXIACPARLEN[2]; // rv 0 + assign SAXIACPARLEN_in[3] = (SAXIACPARLEN[3] !== 1'bz) && SAXIACPARLEN[3]; // rv 0 + assign SAXIACPARLOCK_in[0] = (SAXIACPARLOCK[0] !== 1'bz) && SAXIACPARLOCK[0]; // rv 0 + assign SAXIACPARLOCK_in[1] = (SAXIACPARLOCK[1] !== 1'bz) && SAXIACPARLOCK[1]; // rv 0 + assign SAXIACPARPROT_in[0] = (SAXIACPARPROT[0] !== 1'bz) && SAXIACPARPROT[0]; // rv 0 + assign SAXIACPARPROT_in[1] = (SAXIACPARPROT[1] !== 1'bz) && SAXIACPARPROT[1]; // rv 0 + assign SAXIACPARPROT_in[2] = (SAXIACPARPROT[2] !== 1'bz) && SAXIACPARPROT[2]; // rv 0 + assign SAXIACPARSIZE_in[0] = (SAXIACPARSIZE[0] !== 1'bz) && SAXIACPARSIZE[0]; // rv 0 + assign SAXIACPARSIZE_in[1] = (SAXIACPARSIZE[1] !== 1'bz) && SAXIACPARSIZE[1]; // rv 0 + assign SAXIACPARUSER_in[0] = (SAXIACPARUSER[0] !== 1'bz) && SAXIACPARUSER[0]; // rv 0 + assign SAXIACPARUSER_in[1] = (SAXIACPARUSER[1] !== 1'bz) && SAXIACPARUSER[1]; // rv 0 + assign SAXIACPARUSER_in[2] = (SAXIACPARUSER[2] !== 1'bz) && SAXIACPARUSER[2]; // rv 0 + assign SAXIACPARUSER_in[3] = (SAXIACPARUSER[3] !== 1'bz) && SAXIACPARUSER[3]; // rv 0 + assign SAXIACPARUSER_in[4] = (SAXIACPARUSER[4] !== 1'bz) && SAXIACPARUSER[4]; // rv 0 + assign SAXIACPARVALID_in = (SAXIACPARVALID !== 1'bz) && SAXIACPARVALID; // rv 0 + assign SAXIACPAWADDR_in[0] = (SAXIACPAWADDR[0] !== 1'bz) && SAXIACPAWADDR[0]; // rv 0 + assign SAXIACPAWADDR_in[10] = (SAXIACPAWADDR[10] !== 1'bz) && SAXIACPAWADDR[10]; // rv 0 + assign SAXIACPAWADDR_in[11] = (SAXIACPAWADDR[11] !== 1'bz) && SAXIACPAWADDR[11]; // rv 0 + assign SAXIACPAWADDR_in[12] = (SAXIACPAWADDR[12] !== 1'bz) && SAXIACPAWADDR[12]; // rv 0 + assign SAXIACPAWADDR_in[13] = (SAXIACPAWADDR[13] !== 1'bz) && SAXIACPAWADDR[13]; // rv 0 + assign SAXIACPAWADDR_in[14] = (SAXIACPAWADDR[14] !== 1'bz) && SAXIACPAWADDR[14]; // rv 0 + assign SAXIACPAWADDR_in[15] = (SAXIACPAWADDR[15] !== 1'bz) && SAXIACPAWADDR[15]; // rv 0 + assign SAXIACPAWADDR_in[16] = (SAXIACPAWADDR[16] !== 1'bz) && SAXIACPAWADDR[16]; // rv 0 + assign SAXIACPAWADDR_in[17] = (SAXIACPAWADDR[17] !== 1'bz) && SAXIACPAWADDR[17]; // rv 0 + assign SAXIACPAWADDR_in[18] = (SAXIACPAWADDR[18] !== 1'bz) && SAXIACPAWADDR[18]; // rv 0 + assign SAXIACPAWADDR_in[19] = (SAXIACPAWADDR[19] !== 1'bz) && SAXIACPAWADDR[19]; // rv 0 + assign SAXIACPAWADDR_in[1] = (SAXIACPAWADDR[1] !== 1'bz) && SAXIACPAWADDR[1]; // rv 0 + assign SAXIACPAWADDR_in[20] = (SAXIACPAWADDR[20] !== 1'bz) && SAXIACPAWADDR[20]; // rv 0 + assign SAXIACPAWADDR_in[21] = (SAXIACPAWADDR[21] !== 1'bz) && SAXIACPAWADDR[21]; // rv 0 + assign SAXIACPAWADDR_in[22] = (SAXIACPAWADDR[22] !== 1'bz) && SAXIACPAWADDR[22]; // rv 0 + assign SAXIACPAWADDR_in[23] = (SAXIACPAWADDR[23] !== 1'bz) && SAXIACPAWADDR[23]; // rv 0 + assign SAXIACPAWADDR_in[24] = (SAXIACPAWADDR[24] !== 1'bz) && SAXIACPAWADDR[24]; // rv 0 + assign SAXIACPAWADDR_in[25] = (SAXIACPAWADDR[25] !== 1'bz) && SAXIACPAWADDR[25]; // rv 0 + assign SAXIACPAWADDR_in[26] = (SAXIACPAWADDR[26] !== 1'bz) && SAXIACPAWADDR[26]; // rv 0 + assign SAXIACPAWADDR_in[27] = (SAXIACPAWADDR[27] !== 1'bz) && SAXIACPAWADDR[27]; // rv 0 + assign SAXIACPAWADDR_in[28] = (SAXIACPAWADDR[28] !== 1'bz) && SAXIACPAWADDR[28]; // rv 0 + assign SAXIACPAWADDR_in[29] = (SAXIACPAWADDR[29] !== 1'bz) && SAXIACPAWADDR[29]; // rv 0 + assign SAXIACPAWADDR_in[2] = (SAXIACPAWADDR[2] !== 1'bz) && SAXIACPAWADDR[2]; // rv 0 + assign SAXIACPAWADDR_in[30] = (SAXIACPAWADDR[30] !== 1'bz) && SAXIACPAWADDR[30]; // rv 0 + assign SAXIACPAWADDR_in[31] = (SAXIACPAWADDR[31] !== 1'bz) && SAXIACPAWADDR[31]; // rv 0 + assign SAXIACPAWADDR_in[3] = (SAXIACPAWADDR[3] !== 1'bz) && SAXIACPAWADDR[3]; // rv 0 + assign SAXIACPAWADDR_in[4] = (SAXIACPAWADDR[4] !== 1'bz) && SAXIACPAWADDR[4]; // rv 0 + assign SAXIACPAWADDR_in[5] = (SAXIACPAWADDR[5] !== 1'bz) && SAXIACPAWADDR[5]; // rv 0 + assign SAXIACPAWADDR_in[6] = (SAXIACPAWADDR[6] !== 1'bz) && SAXIACPAWADDR[6]; // rv 0 + assign SAXIACPAWADDR_in[7] = (SAXIACPAWADDR[7] !== 1'bz) && SAXIACPAWADDR[7]; // rv 0 + assign SAXIACPAWADDR_in[8] = (SAXIACPAWADDR[8] !== 1'bz) && SAXIACPAWADDR[8]; // rv 0 + assign SAXIACPAWADDR_in[9] = (SAXIACPAWADDR[9] !== 1'bz) && SAXIACPAWADDR[9]; // rv 0 + assign SAXIACPAWBURST_in[0] = (SAXIACPAWBURST[0] !== 1'bz) && SAXIACPAWBURST[0]; // rv 0 + assign SAXIACPAWBURST_in[1] = (SAXIACPAWBURST[1] !== 1'bz) && SAXIACPAWBURST[1]; // rv 0 + assign SAXIACPAWCACHE_in[0] = (SAXIACPAWCACHE[0] !== 1'bz) && SAXIACPAWCACHE[0]; // rv 0 + assign SAXIACPAWCACHE_in[1] = (SAXIACPAWCACHE[1] !== 1'bz) && SAXIACPAWCACHE[1]; // rv 0 + assign SAXIACPAWCACHE_in[2] = (SAXIACPAWCACHE[2] !== 1'bz) && SAXIACPAWCACHE[2]; // rv 0 + assign SAXIACPAWCACHE_in[3] = (SAXIACPAWCACHE[3] !== 1'bz) && SAXIACPAWCACHE[3]; // rv 0 + assign SAXIACPAWID_in[0] = (SAXIACPAWID[0] !== 1'bz) && SAXIACPAWID[0]; // rv 0 + assign SAXIACPAWID_in[1] = (SAXIACPAWID[1] !== 1'bz) && SAXIACPAWID[1]; // rv 0 + assign SAXIACPAWID_in[2] = (SAXIACPAWID[2] !== 1'bz) && SAXIACPAWID[2]; // rv 0 + assign SAXIACPAWLEN_in[0] = (SAXIACPAWLEN[0] !== 1'bz) && SAXIACPAWLEN[0]; // rv 0 + assign SAXIACPAWLEN_in[1] = (SAXIACPAWLEN[1] !== 1'bz) && SAXIACPAWLEN[1]; // rv 0 + assign SAXIACPAWLEN_in[2] = (SAXIACPAWLEN[2] !== 1'bz) && SAXIACPAWLEN[2]; // rv 0 + assign SAXIACPAWLEN_in[3] = (SAXIACPAWLEN[3] !== 1'bz) && SAXIACPAWLEN[3]; // rv 0 + assign SAXIACPAWLOCK_in[0] = (SAXIACPAWLOCK[0] !== 1'bz) && SAXIACPAWLOCK[0]; // rv 0 + assign SAXIACPAWLOCK_in[1] = (SAXIACPAWLOCK[1] !== 1'bz) && SAXIACPAWLOCK[1]; // rv 0 + assign SAXIACPAWPROT_in[0] = (SAXIACPAWPROT[0] !== 1'bz) && SAXIACPAWPROT[0]; // rv 0 + assign SAXIACPAWPROT_in[1] = (SAXIACPAWPROT[1] !== 1'bz) && SAXIACPAWPROT[1]; // rv 0 + assign SAXIACPAWPROT_in[2] = (SAXIACPAWPROT[2] !== 1'bz) && SAXIACPAWPROT[2]; // rv 0 + assign SAXIACPAWSIZE_in[0] = (SAXIACPAWSIZE[0] !== 1'bz) && SAXIACPAWSIZE[0]; // rv 0 + assign SAXIACPAWSIZE_in[1] = (SAXIACPAWSIZE[1] !== 1'bz) && SAXIACPAWSIZE[1]; // rv 0 + assign SAXIACPAWUSER_in[0] = (SAXIACPAWUSER[0] !== 1'bz) && SAXIACPAWUSER[0]; // rv 0 + assign SAXIACPAWUSER_in[1] = (SAXIACPAWUSER[1] !== 1'bz) && SAXIACPAWUSER[1]; // rv 0 + assign SAXIACPAWUSER_in[2] = (SAXIACPAWUSER[2] !== 1'bz) && SAXIACPAWUSER[2]; // rv 0 + assign SAXIACPAWUSER_in[3] = (SAXIACPAWUSER[3] !== 1'bz) && SAXIACPAWUSER[3]; // rv 0 + assign SAXIACPAWUSER_in[4] = (SAXIACPAWUSER[4] !== 1'bz) && SAXIACPAWUSER[4]; // rv 0 + assign SAXIACPAWVALID_in = (SAXIACPAWVALID !== 1'bz) && SAXIACPAWVALID; // rv 0 + assign SAXIACPBREADY_in = (SAXIACPBREADY !== 1'bz) && SAXIACPBREADY; // rv 0 + assign SAXIACPRREADY_in = (SAXIACPRREADY !== 1'bz) && SAXIACPRREADY; // rv 0 + assign SAXIACPWDATA_in[0] = (SAXIACPWDATA[0] !== 1'bz) && SAXIACPWDATA[0]; // rv 0 + assign SAXIACPWDATA_in[10] = (SAXIACPWDATA[10] !== 1'bz) && SAXIACPWDATA[10]; // rv 0 + assign SAXIACPWDATA_in[11] = (SAXIACPWDATA[11] !== 1'bz) && SAXIACPWDATA[11]; // rv 0 + assign SAXIACPWDATA_in[12] = (SAXIACPWDATA[12] !== 1'bz) && SAXIACPWDATA[12]; // rv 0 + assign SAXIACPWDATA_in[13] = (SAXIACPWDATA[13] !== 1'bz) && SAXIACPWDATA[13]; // rv 0 + assign SAXIACPWDATA_in[14] = (SAXIACPWDATA[14] !== 1'bz) && SAXIACPWDATA[14]; // rv 0 + assign SAXIACPWDATA_in[15] = (SAXIACPWDATA[15] !== 1'bz) && SAXIACPWDATA[15]; // rv 0 + assign SAXIACPWDATA_in[16] = (SAXIACPWDATA[16] !== 1'bz) && SAXIACPWDATA[16]; // rv 0 + assign SAXIACPWDATA_in[17] = (SAXIACPWDATA[17] !== 1'bz) && SAXIACPWDATA[17]; // rv 0 + assign SAXIACPWDATA_in[18] = (SAXIACPWDATA[18] !== 1'bz) && SAXIACPWDATA[18]; // rv 0 + assign SAXIACPWDATA_in[19] = (SAXIACPWDATA[19] !== 1'bz) && SAXIACPWDATA[19]; // rv 0 + assign SAXIACPWDATA_in[1] = (SAXIACPWDATA[1] !== 1'bz) && SAXIACPWDATA[1]; // rv 0 + assign SAXIACPWDATA_in[20] = (SAXIACPWDATA[20] !== 1'bz) && SAXIACPWDATA[20]; // rv 0 + assign SAXIACPWDATA_in[21] = (SAXIACPWDATA[21] !== 1'bz) && SAXIACPWDATA[21]; // rv 0 + assign SAXIACPWDATA_in[22] = (SAXIACPWDATA[22] !== 1'bz) && SAXIACPWDATA[22]; // rv 0 + assign SAXIACPWDATA_in[23] = (SAXIACPWDATA[23] !== 1'bz) && SAXIACPWDATA[23]; // rv 0 + assign SAXIACPWDATA_in[24] = (SAXIACPWDATA[24] !== 1'bz) && SAXIACPWDATA[24]; // rv 0 + assign SAXIACPWDATA_in[25] = (SAXIACPWDATA[25] !== 1'bz) && SAXIACPWDATA[25]; // rv 0 + assign SAXIACPWDATA_in[26] = (SAXIACPWDATA[26] !== 1'bz) && SAXIACPWDATA[26]; // rv 0 + assign SAXIACPWDATA_in[27] = (SAXIACPWDATA[27] !== 1'bz) && SAXIACPWDATA[27]; // rv 0 + assign SAXIACPWDATA_in[28] = (SAXIACPWDATA[28] !== 1'bz) && SAXIACPWDATA[28]; // rv 0 + assign SAXIACPWDATA_in[29] = (SAXIACPWDATA[29] !== 1'bz) && SAXIACPWDATA[29]; // rv 0 + assign SAXIACPWDATA_in[2] = (SAXIACPWDATA[2] !== 1'bz) && SAXIACPWDATA[2]; // rv 0 + assign SAXIACPWDATA_in[30] = (SAXIACPWDATA[30] !== 1'bz) && SAXIACPWDATA[30]; // rv 0 + assign SAXIACPWDATA_in[31] = (SAXIACPWDATA[31] !== 1'bz) && SAXIACPWDATA[31]; // rv 0 + assign SAXIACPWDATA_in[32] = (SAXIACPWDATA[32] !== 1'bz) && SAXIACPWDATA[32]; // rv 0 + assign SAXIACPWDATA_in[33] = (SAXIACPWDATA[33] !== 1'bz) && SAXIACPWDATA[33]; // rv 0 + assign SAXIACPWDATA_in[34] = (SAXIACPWDATA[34] !== 1'bz) && SAXIACPWDATA[34]; // rv 0 + assign SAXIACPWDATA_in[35] = (SAXIACPWDATA[35] !== 1'bz) && SAXIACPWDATA[35]; // rv 0 + assign SAXIACPWDATA_in[36] = (SAXIACPWDATA[36] !== 1'bz) && SAXIACPWDATA[36]; // rv 0 + assign SAXIACPWDATA_in[37] = (SAXIACPWDATA[37] !== 1'bz) && SAXIACPWDATA[37]; // rv 0 + assign SAXIACPWDATA_in[38] = (SAXIACPWDATA[38] !== 1'bz) && SAXIACPWDATA[38]; // rv 0 + assign SAXIACPWDATA_in[39] = (SAXIACPWDATA[39] !== 1'bz) && SAXIACPWDATA[39]; // rv 0 + assign SAXIACPWDATA_in[3] = (SAXIACPWDATA[3] !== 1'bz) && SAXIACPWDATA[3]; // rv 0 + assign SAXIACPWDATA_in[40] = (SAXIACPWDATA[40] !== 1'bz) && SAXIACPWDATA[40]; // rv 0 + assign SAXIACPWDATA_in[41] = (SAXIACPWDATA[41] !== 1'bz) && SAXIACPWDATA[41]; // rv 0 + assign SAXIACPWDATA_in[42] = (SAXIACPWDATA[42] !== 1'bz) && SAXIACPWDATA[42]; // rv 0 + assign SAXIACPWDATA_in[43] = (SAXIACPWDATA[43] !== 1'bz) && SAXIACPWDATA[43]; // rv 0 + assign SAXIACPWDATA_in[44] = (SAXIACPWDATA[44] !== 1'bz) && SAXIACPWDATA[44]; // rv 0 + assign SAXIACPWDATA_in[45] = (SAXIACPWDATA[45] !== 1'bz) && SAXIACPWDATA[45]; // rv 0 + assign SAXIACPWDATA_in[46] = (SAXIACPWDATA[46] !== 1'bz) && SAXIACPWDATA[46]; // rv 0 + assign SAXIACPWDATA_in[47] = (SAXIACPWDATA[47] !== 1'bz) && SAXIACPWDATA[47]; // rv 0 + assign SAXIACPWDATA_in[48] = (SAXIACPWDATA[48] !== 1'bz) && SAXIACPWDATA[48]; // rv 0 + assign SAXIACPWDATA_in[49] = (SAXIACPWDATA[49] !== 1'bz) && SAXIACPWDATA[49]; // rv 0 + assign SAXIACPWDATA_in[4] = (SAXIACPWDATA[4] !== 1'bz) && SAXIACPWDATA[4]; // rv 0 + assign SAXIACPWDATA_in[50] = (SAXIACPWDATA[50] !== 1'bz) && SAXIACPWDATA[50]; // rv 0 + assign SAXIACPWDATA_in[51] = (SAXIACPWDATA[51] !== 1'bz) && SAXIACPWDATA[51]; // rv 0 + assign SAXIACPWDATA_in[52] = (SAXIACPWDATA[52] !== 1'bz) && SAXIACPWDATA[52]; // rv 0 + assign SAXIACPWDATA_in[53] = (SAXIACPWDATA[53] !== 1'bz) && SAXIACPWDATA[53]; // rv 0 + assign SAXIACPWDATA_in[54] = (SAXIACPWDATA[54] !== 1'bz) && SAXIACPWDATA[54]; // rv 0 + assign SAXIACPWDATA_in[55] = (SAXIACPWDATA[55] !== 1'bz) && SAXIACPWDATA[55]; // rv 0 + assign SAXIACPWDATA_in[56] = (SAXIACPWDATA[56] !== 1'bz) && SAXIACPWDATA[56]; // rv 0 + assign SAXIACPWDATA_in[57] = (SAXIACPWDATA[57] !== 1'bz) && SAXIACPWDATA[57]; // rv 0 + assign SAXIACPWDATA_in[58] = (SAXIACPWDATA[58] !== 1'bz) && SAXIACPWDATA[58]; // rv 0 + assign SAXIACPWDATA_in[59] = (SAXIACPWDATA[59] !== 1'bz) && SAXIACPWDATA[59]; // rv 0 + assign SAXIACPWDATA_in[5] = (SAXIACPWDATA[5] !== 1'bz) && SAXIACPWDATA[5]; // rv 0 + assign SAXIACPWDATA_in[60] = (SAXIACPWDATA[60] !== 1'bz) && SAXIACPWDATA[60]; // rv 0 + assign SAXIACPWDATA_in[61] = (SAXIACPWDATA[61] !== 1'bz) && SAXIACPWDATA[61]; // rv 0 + assign SAXIACPWDATA_in[62] = (SAXIACPWDATA[62] !== 1'bz) && SAXIACPWDATA[62]; // rv 0 + assign SAXIACPWDATA_in[63] = (SAXIACPWDATA[63] !== 1'bz) && SAXIACPWDATA[63]; // rv 0 + assign SAXIACPWDATA_in[6] = (SAXIACPWDATA[6] !== 1'bz) && SAXIACPWDATA[6]; // rv 0 + assign SAXIACPWDATA_in[7] = (SAXIACPWDATA[7] !== 1'bz) && SAXIACPWDATA[7]; // rv 0 + assign SAXIACPWDATA_in[8] = (SAXIACPWDATA[8] !== 1'bz) && SAXIACPWDATA[8]; // rv 0 + assign SAXIACPWDATA_in[9] = (SAXIACPWDATA[9] !== 1'bz) && SAXIACPWDATA[9]; // rv 0 + assign SAXIACPWID_in[0] = (SAXIACPWID[0] !== 1'bz) && SAXIACPWID[0]; // rv 0 + assign SAXIACPWID_in[1] = (SAXIACPWID[1] !== 1'bz) && SAXIACPWID[1]; // rv 0 + assign SAXIACPWID_in[2] = (SAXIACPWID[2] !== 1'bz) && SAXIACPWID[2]; // rv 0 + assign SAXIACPWLAST_in = (SAXIACPWLAST !== 1'bz) && SAXIACPWLAST; // rv 0 + assign SAXIACPWSTRB_in[0] = (SAXIACPWSTRB[0] !== 1'bz) && SAXIACPWSTRB[0]; // rv 0 + assign SAXIACPWSTRB_in[1] = (SAXIACPWSTRB[1] !== 1'bz) && SAXIACPWSTRB[1]; // rv 0 + assign SAXIACPWSTRB_in[2] = (SAXIACPWSTRB[2] !== 1'bz) && SAXIACPWSTRB[2]; // rv 0 + assign SAXIACPWSTRB_in[3] = (SAXIACPWSTRB[3] !== 1'bz) && SAXIACPWSTRB[3]; // rv 0 + assign SAXIACPWSTRB_in[4] = (SAXIACPWSTRB[4] !== 1'bz) && SAXIACPWSTRB[4]; // rv 0 + assign SAXIACPWSTRB_in[5] = (SAXIACPWSTRB[5] !== 1'bz) && SAXIACPWSTRB[5]; // rv 0 + assign SAXIACPWSTRB_in[6] = (SAXIACPWSTRB[6] !== 1'bz) && SAXIACPWSTRB[6]; // rv 0 + assign SAXIACPWSTRB_in[7] = (SAXIACPWSTRB[7] !== 1'bz) && SAXIACPWSTRB[7]; // rv 0 + assign SAXIACPWVALID_in = (SAXIACPWVALID !== 1'bz) && SAXIACPWVALID; // rv 0 + assign SAXIGP0ACLK_in = (SAXIGP0ACLK !== 1'bz) && SAXIGP0ACLK; // rv 0 + assign SAXIGP0ARADDR_in[0] = (SAXIGP0ARADDR[0] !== 1'bz) && SAXIGP0ARADDR[0]; // rv 0 + assign SAXIGP0ARADDR_in[10] = (SAXIGP0ARADDR[10] !== 1'bz) && SAXIGP0ARADDR[10]; // rv 0 + assign SAXIGP0ARADDR_in[11] = (SAXIGP0ARADDR[11] !== 1'bz) && SAXIGP0ARADDR[11]; // rv 0 + assign SAXIGP0ARADDR_in[12] = (SAXIGP0ARADDR[12] !== 1'bz) && SAXIGP0ARADDR[12]; // rv 0 + assign SAXIGP0ARADDR_in[13] = (SAXIGP0ARADDR[13] !== 1'bz) && SAXIGP0ARADDR[13]; // rv 0 + assign SAXIGP0ARADDR_in[14] = (SAXIGP0ARADDR[14] !== 1'bz) && SAXIGP0ARADDR[14]; // rv 0 + assign SAXIGP0ARADDR_in[15] = (SAXIGP0ARADDR[15] !== 1'bz) && SAXIGP0ARADDR[15]; // rv 0 + assign SAXIGP0ARADDR_in[16] = (SAXIGP0ARADDR[16] !== 1'bz) && SAXIGP0ARADDR[16]; // rv 0 + assign SAXIGP0ARADDR_in[17] = (SAXIGP0ARADDR[17] !== 1'bz) && SAXIGP0ARADDR[17]; // rv 0 + assign SAXIGP0ARADDR_in[18] = (SAXIGP0ARADDR[18] !== 1'bz) && SAXIGP0ARADDR[18]; // rv 0 + assign SAXIGP0ARADDR_in[19] = (SAXIGP0ARADDR[19] !== 1'bz) && SAXIGP0ARADDR[19]; // rv 0 + assign SAXIGP0ARADDR_in[1] = (SAXIGP0ARADDR[1] !== 1'bz) && SAXIGP0ARADDR[1]; // rv 0 + assign SAXIGP0ARADDR_in[20] = (SAXIGP0ARADDR[20] !== 1'bz) && SAXIGP0ARADDR[20]; // rv 0 + assign SAXIGP0ARADDR_in[21] = (SAXIGP0ARADDR[21] !== 1'bz) && SAXIGP0ARADDR[21]; // rv 0 + assign SAXIGP0ARADDR_in[22] = (SAXIGP0ARADDR[22] !== 1'bz) && SAXIGP0ARADDR[22]; // rv 0 + assign SAXIGP0ARADDR_in[23] = (SAXIGP0ARADDR[23] !== 1'bz) && SAXIGP0ARADDR[23]; // rv 0 + assign SAXIGP0ARADDR_in[24] = (SAXIGP0ARADDR[24] !== 1'bz) && SAXIGP0ARADDR[24]; // rv 0 + assign SAXIGP0ARADDR_in[25] = (SAXIGP0ARADDR[25] !== 1'bz) && SAXIGP0ARADDR[25]; // rv 0 + assign SAXIGP0ARADDR_in[26] = (SAXIGP0ARADDR[26] !== 1'bz) && SAXIGP0ARADDR[26]; // rv 0 + assign SAXIGP0ARADDR_in[27] = (SAXIGP0ARADDR[27] !== 1'bz) && SAXIGP0ARADDR[27]; // rv 0 + assign SAXIGP0ARADDR_in[28] = (SAXIGP0ARADDR[28] !== 1'bz) && SAXIGP0ARADDR[28]; // rv 0 + assign SAXIGP0ARADDR_in[29] = (SAXIGP0ARADDR[29] !== 1'bz) && SAXIGP0ARADDR[29]; // rv 0 + assign SAXIGP0ARADDR_in[2] = (SAXIGP0ARADDR[2] !== 1'bz) && SAXIGP0ARADDR[2]; // rv 0 + assign SAXIGP0ARADDR_in[30] = (SAXIGP0ARADDR[30] !== 1'bz) && SAXIGP0ARADDR[30]; // rv 0 + assign SAXIGP0ARADDR_in[31] = (SAXIGP0ARADDR[31] !== 1'bz) && SAXIGP0ARADDR[31]; // rv 0 + assign SAXIGP0ARADDR_in[3] = (SAXIGP0ARADDR[3] !== 1'bz) && SAXIGP0ARADDR[3]; // rv 0 + assign SAXIGP0ARADDR_in[4] = (SAXIGP0ARADDR[4] !== 1'bz) && SAXIGP0ARADDR[4]; // rv 0 + assign SAXIGP0ARADDR_in[5] = (SAXIGP0ARADDR[5] !== 1'bz) && SAXIGP0ARADDR[5]; // rv 0 + assign SAXIGP0ARADDR_in[6] = (SAXIGP0ARADDR[6] !== 1'bz) && SAXIGP0ARADDR[6]; // rv 0 + assign SAXIGP0ARADDR_in[7] = (SAXIGP0ARADDR[7] !== 1'bz) && SAXIGP0ARADDR[7]; // rv 0 + assign SAXIGP0ARADDR_in[8] = (SAXIGP0ARADDR[8] !== 1'bz) && SAXIGP0ARADDR[8]; // rv 0 + assign SAXIGP0ARADDR_in[9] = (SAXIGP0ARADDR[9] !== 1'bz) && SAXIGP0ARADDR[9]; // rv 0 + assign SAXIGP0ARBURST_in[0] = (SAXIGP0ARBURST[0] !== 1'bz) && SAXIGP0ARBURST[0]; // rv 0 + assign SAXIGP0ARBURST_in[1] = (SAXIGP0ARBURST[1] !== 1'bz) && SAXIGP0ARBURST[1]; // rv 0 + assign SAXIGP0ARCACHE_in[0] = (SAXIGP0ARCACHE[0] !== 1'bz) && SAXIGP0ARCACHE[0]; // rv 0 + assign SAXIGP0ARCACHE_in[1] = (SAXIGP0ARCACHE[1] !== 1'bz) && SAXIGP0ARCACHE[1]; // rv 0 + assign SAXIGP0ARCACHE_in[2] = (SAXIGP0ARCACHE[2] !== 1'bz) && SAXIGP0ARCACHE[2]; // rv 0 + assign SAXIGP0ARCACHE_in[3] = (SAXIGP0ARCACHE[3] !== 1'bz) && SAXIGP0ARCACHE[3]; // rv 0 + assign SAXIGP0ARID_in[0] = (SAXIGP0ARID[0] !== 1'bz) && SAXIGP0ARID[0]; // rv 0 + assign SAXIGP0ARID_in[1] = (SAXIGP0ARID[1] !== 1'bz) && SAXIGP0ARID[1]; // rv 0 + assign SAXIGP0ARID_in[2] = (SAXIGP0ARID[2] !== 1'bz) && SAXIGP0ARID[2]; // rv 0 + assign SAXIGP0ARID_in[3] = (SAXIGP0ARID[3] !== 1'bz) && SAXIGP0ARID[3]; // rv 0 + assign SAXIGP0ARID_in[4] = (SAXIGP0ARID[4] !== 1'bz) && SAXIGP0ARID[4]; // rv 0 + assign SAXIGP0ARID_in[5] = (SAXIGP0ARID[5] !== 1'bz) && SAXIGP0ARID[5]; // rv 0 + assign SAXIGP0ARLEN_in[0] = (SAXIGP0ARLEN[0] !== 1'bz) && SAXIGP0ARLEN[0]; // rv 0 + assign SAXIGP0ARLEN_in[1] = (SAXIGP0ARLEN[1] !== 1'bz) && SAXIGP0ARLEN[1]; // rv 0 + assign SAXIGP0ARLEN_in[2] = (SAXIGP0ARLEN[2] !== 1'bz) && SAXIGP0ARLEN[2]; // rv 0 + assign SAXIGP0ARLEN_in[3] = (SAXIGP0ARLEN[3] !== 1'bz) && SAXIGP0ARLEN[3]; // rv 0 + assign SAXIGP0ARLOCK_in[0] = (SAXIGP0ARLOCK[0] !== 1'bz) && SAXIGP0ARLOCK[0]; // rv 0 + assign SAXIGP0ARLOCK_in[1] = (SAXIGP0ARLOCK[1] !== 1'bz) && SAXIGP0ARLOCK[1]; // rv 0 + assign SAXIGP0ARPROT_in[0] = (SAXIGP0ARPROT[0] !== 1'bz) && SAXIGP0ARPROT[0]; // rv 0 + assign SAXIGP0ARPROT_in[1] = (SAXIGP0ARPROT[1] !== 1'bz) && SAXIGP0ARPROT[1]; // rv 0 + assign SAXIGP0ARPROT_in[2] = (SAXIGP0ARPROT[2] !== 1'bz) && SAXIGP0ARPROT[2]; // rv 0 + assign SAXIGP0ARQOS_in[0] = (SAXIGP0ARQOS[0] !== 1'bz) && SAXIGP0ARQOS[0]; // rv 0 + assign SAXIGP0ARQOS_in[1] = (SAXIGP0ARQOS[1] !== 1'bz) && SAXIGP0ARQOS[1]; // rv 0 + assign SAXIGP0ARQOS_in[2] = (SAXIGP0ARQOS[2] !== 1'bz) && SAXIGP0ARQOS[2]; // rv 0 + assign SAXIGP0ARQOS_in[3] = (SAXIGP0ARQOS[3] !== 1'bz) && SAXIGP0ARQOS[3]; // rv 0 + assign SAXIGP0ARSIZE_in[0] = (SAXIGP0ARSIZE[0] !== 1'bz) && SAXIGP0ARSIZE[0]; // rv 0 + assign SAXIGP0ARSIZE_in[1] = (SAXIGP0ARSIZE[1] !== 1'bz) && SAXIGP0ARSIZE[1]; // rv 0 + assign SAXIGP0ARVALID_in = (SAXIGP0ARVALID !== 1'bz) && SAXIGP0ARVALID; // rv 0 + assign SAXIGP0AWADDR_in[0] = (SAXIGP0AWADDR[0] !== 1'bz) && SAXIGP0AWADDR[0]; // rv 0 + assign SAXIGP0AWADDR_in[10] = (SAXIGP0AWADDR[10] !== 1'bz) && SAXIGP0AWADDR[10]; // rv 0 + assign SAXIGP0AWADDR_in[11] = (SAXIGP0AWADDR[11] !== 1'bz) && SAXIGP0AWADDR[11]; // rv 0 + assign SAXIGP0AWADDR_in[12] = (SAXIGP0AWADDR[12] !== 1'bz) && SAXIGP0AWADDR[12]; // rv 0 + assign SAXIGP0AWADDR_in[13] = (SAXIGP0AWADDR[13] !== 1'bz) && SAXIGP0AWADDR[13]; // rv 0 + assign SAXIGP0AWADDR_in[14] = (SAXIGP0AWADDR[14] !== 1'bz) && SAXIGP0AWADDR[14]; // rv 0 + assign SAXIGP0AWADDR_in[15] = (SAXIGP0AWADDR[15] !== 1'bz) && SAXIGP0AWADDR[15]; // rv 0 + assign SAXIGP0AWADDR_in[16] = (SAXIGP0AWADDR[16] !== 1'bz) && SAXIGP0AWADDR[16]; // rv 0 + assign SAXIGP0AWADDR_in[17] = (SAXIGP0AWADDR[17] !== 1'bz) && SAXIGP0AWADDR[17]; // rv 0 + assign SAXIGP0AWADDR_in[18] = (SAXIGP0AWADDR[18] !== 1'bz) && SAXIGP0AWADDR[18]; // rv 0 + assign SAXIGP0AWADDR_in[19] = (SAXIGP0AWADDR[19] !== 1'bz) && SAXIGP0AWADDR[19]; // rv 0 + assign SAXIGP0AWADDR_in[1] = (SAXIGP0AWADDR[1] !== 1'bz) && SAXIGP0AWADDR[1]; // rv 0 + assign SAXIGP0AWADDR_in[20] = (SAXIGP0AWADDR[20] !== 1'bz) && SAXIGP0AWADDR[20]; // rv 0 + assign SAXIGP0AWADDR_in[21] = (SAXIGP0AWADDR[21] !== 1'bz) && SAXIGP0AWADDR[21]; // rv 0 + assign SAXIGP0AWADDR_in[22] = (SAXIGP0AWADDR[22] !== 1'bz) && SAXIGP0AWADDR[22]; // rv 0 + assign SAXIGP0AWADDR_in[23] = (SAXIGP0AWADDR[23] !== 1'bz) && SAXIGP0AWADDR[23]; // rv 0 + assign SAXIGP0AWADDR_in[24] = (SAXIGP0AWADDR[24] !== 1'bz) && SAXIGP0AWADDR[24]; // rv 0 + assign SAXIGP0AWADDR_in[25] = (SAXIGP0AWADDR[25] !== 1'bz) && SAXIGP0AWADDR[25]; // rv 0 + assign SAXIGP0AWADDR_in[26] = (SAXIGP0AWADDR[26] !== 1'bz) && SAXIGP0AWADDR[26]; // rv 0 + assign SAXIGP0AWADDR_in[27] = (SAXIGP0AWADDR[27] !== 1'bz) && SAXIGP0AWADDR[27]; // rv 0 + assign SAXIGP0AWADDR_in[28] = (SAXIGP0AWADDR[28] !== 1'bz) && SAXIGP0AWADDR[28]; // rv 0 + assign SAXIGP0AWADDR_in[29] = (SAXIGP0AWADDR[29] !== 1'bz) && SAXIGP0AWADDR[29]; // rv 0 + assign SAXIGP0AWADDR_in[2] = (SAXIGP0AWADDR[2] !== 1'bz) && SAXIGP0AWADDR[2]; // rv 0 + assign SAXIGP0AWADDR_in[30] = (SAXIGP0AWADDR[30] !== 1'bz) && SAXIGP0AWADDR[30]; // rv 0 + assign SAXIGP0AWADDR_in[31] = (SAXIGP0AWADDR[31] !== 1'bz) && SAXIGP0AWADDR[31]; // rv 0 + assign SAXIGP0AWADDR_in[3] = (SAXIGP0AWADDR[3] !== 1'bz) && SAXIGP0AWADDR[3]; // rv 0 + assign SAXIGP0AWADDR_in[4] = (SAXIGP0AWADDR[4] !== 1'bz) && SAXIGP0AWADDR[4]; // rv 0 + assign SAXIGP0AWADDR_in[5] = (SAXIGP0AWADDR[5] !== 1'bz) && SAXIGP0AWADDR[5]; // rv 0 + assign SAXIGP0AWADDR_in[6] = (SAXIGP0AWADDR[6] !== 1'bz) && SAXIGP0AWADDR[6]; // rv 0 + assign SAXIGP0AWADDR_in[7] = (SAXIGP0AWADDR[7] !== 1'bz) && SAXIGP0AWADDR[7]; // rv 0 + assign SAXIGP0AWADDR_in[8] = (SAXIGP0AWADDR[8] !== 1'bz) && SAXIGP0AWADDR[8]; // rv 0 + assign SAXIGP0AWADDR_in[9] = (SAXIGP0AWADDR[9] !== 1'bz) && SAXIGP0AWADDR[9]; // rv 0 + assign SAXIGP0AWBURST_in[0] = (SAXIGP0AWBURST[0] !== 1'bz) && SAXIGP0AWBURST[0]; // rv 0 + assign SAXIGP0AWBURST_in[1] = (SAXIGP0AWBURST[1] !== 1'bz) && SAXIGP0AWBURST[1]; // rv 0 + assign SAXIGP0AWCACHE_in[0] = (SAXIGP0AWCACHE[0] !== 1'bz) && SAXIGP0AWCACHE[0]; // rv 0 + assign SAXIGP0AWCACHE_in[1] = (SAXIGP0AWCACHE[1] !== 1'bz) && SAXIGP0AWCACHE[1]; // rv 0 + assign SAXIGP0AWCACHE_in[2] = (SAXIGP0AWCACHE[2] !== 1'bz) && SAXIGP0AWCACHE[2]; // rv 0 + assign SAXIGP0AWCACHE_in[3] = (SAXIGP0AWCACHE[3] !== 1'bz) && SAXIGP0AWCACHE[3]; // rv 0 + assign SAXIGP0AWID_in[0] = (SAXIGP0AWID[0] !== 1'bz) && SAXIGP0AWID[0]; // rv 0 + assign SAXIGP0AWID_in[1] = (SAXIGP0AWID[1] !== 1'bz) && SAXIGP0AWID[1]; // rv 0 + assign SAXIGP0AWID_in[2] = (SAXIGP0AWID[2] !== 1'bz) && SAXIGP0AWID[2]; // rv 0 + assign SAXIGP0AWID_in[3] = (SAXIGP0AWID[3] !== 1'bz) && SAXIGP0AWID[3]; // rv 0 + assign SAXIGP0AWID_in[4] = (SAXIGP0AWID[4] !== 1'bz) && SAXIGP0AWID[4]; // rv 0 + assign SAXIGP0AWID_in[5] = (SAXIGP0AWID[5] !== 1'bz) && SAXIGP0AWID[5]; // rv 0 + assign SAXIGP0AWLEN_in[0] = (SAXIGP0AWLEN[0] !== 1'bz) && SAXIGP0AWLEN[0]; // rv 0 + assign SAXIGP0AWLEN_in[1] = (SAXIGP0AWLEN[1] !== 1'bz) && SAXIGP0AWLEN[1]; // rv 0 + assign SAXIGP0AWLEN_in[2] = (SAXIGP0AWLEN[2] !== 1'bz) && SAXIGP0AWLEN[2]; // rv 0 + assign SAXIGP0AWLEN_in[3] = (SAXIGP0AWLEN[3] !== 1'bz) && SAXIGP0AWLEN[3]; // rv 0 + assign SAXIGP0AWLOCK_in[0] = (SAXIGP0AWLOCK[0] !== 1'bz) && SAXIGP0AWLOCK[0]; // rv 0 + assign SAXIGP0AWLOCK_in[1] = (SAXIGP0AWLOCK[1] !== 1'bz) && SAXIGP0AWLOCK[1]; // rv 0 + assign SAXIGP0AWPROT_in[0] = (SAXIGP0AWPROT[0] !== 1'bz) && SAXIGP0AWPROT[0]; // rv 0 + assign SAXIGP0AWPROT_in[1] = (SAXIGP0AWPROT[1] !== 1'bz) && SAXIGP0AWPROT[1]; // rv 0 + assign SAXIGP0AWPROT_in[2] = (SAXIGP0AWPROT[2] !== 1'bz) && SAXIGP0AWPROT[2]; // rv 0 + assign SAXIGP0AWQOS_in[0] = (SAXIGP0AWQOS[0] !== 1'bz) && SAXIGP0AWQOS[0]; // rv 0 + assign SAXIGP0AWQOS_in[1] = (SAXIGP0AWQOS[1] !== 1'bz) && SAXIGP0AWQOS[1]; // rv 0 + assign SAXIGP0AWQOS_in[2] = (SAXIGP0AWQOS[2] !== 1'bz) && SAXIGP0AWQOS[2]; // rv 0 + assign SAXIGP0AWQOS_in[3] = (SAXIGP0AWQOS[3] !== 1'bz) && SAXIGP0AWQOS[3]; // rv 0 + assign SAXIGP0AWSIZE_in[0] = (SAXIGP0AWSIZE[0] !== 1'bz) && SAXIGP0AWSIZE[0]; // rv 0 + assign SAXIGP0AWSIZE_in[1] = (SAXIGP0AWSIZE[1] !== 1'bz) && SAXIGP0AWSIZE[1]; // rv 0 + assign SAXIGP0AWVALID_in = (SAXIGP0AWVALID !== 1'bz) && SAXIGP0AWVALID; // rv 0 + assign SAXIGP0BREADY_in = (SAXIGP0BREADY !== 1'bz) && SAXIGP0BREADY; // rv 0 + assign SAXIGP0RREADY_in = (SAXIGP0RREADY !== 1'bz) && SAXIGP0RREADY; // rv 0 + assign SAXIGP0WDATA_in[0] = (SAXIGP0WDATA[0] !== 1'bz) && SAXIGP0WDATA[0]; // rv 0 + assign SAXIGP0WDATA_in[10] = (SAXIGP0WDATA[10] !== 1'bz) && SAXIGP0WDATA[10]; // rv 0 + assign SAXIGP0WDATA_in[11] = (SAXIGP0WDATA[11] !== 1'bz) && SAXIGP0WDATA[11]; // rv 0 + assign SAXIGP0WDATA_in[12] = (SAXIGP0WDATA[12] !== 1'bz) && SAXIGP0WDATA[12]; // rv 0 + assign SAXIGP0WDATA_in[13] = (SAXIGP0WDATA[13] !== 1'bz) && SAXIGP0WDATA[13]; // rv 0 + assign SAXIGP0WDATA_in[14] = (SAXIGP0WDATA[14] !== 1'bz) && SAXIGP0WDATA[14]; // rv 0 + assign SAXIGP0WDATA_in[15] = (SAXIGP0WDATA[15] !== 1'bz) && SAXIGP0WDATA[15]; // rv 0 + assign SAXIGP0WDATA_in[16] = (SAXIGP0WDATA[16] !== 1'bz) && SAXIGP0WDATA[16]; // rv 0 + assign SAXIGP0WDATA_in[17] = (SAXIGP0WDATA[17] !== 1'bz) && SAXIGP0WDATA[17]; // rv 0 + assign SAXIGP0WDATA_in[18] = (SAXIGP0WDATA[18] !== 1'bz) && SAXIGP0WDATA[18]; // rv 0 + assign SAXIGP0WDATA_in[19] = (SAXIGP0WDATA[19] !== 1'bz) && SAXIGP0WDATA[19]; // rv 0 + assign SAXIGP0WDATA_in[1] = (SAXIGP0WDATA[1] !== 1'bz) && SAXIGP0WDATA[1]; // rv 0 + assign SAXIGP0WDATA_in[20] = (SAXIGP0WDATA[20] !== 1'bz) && SAXIGP0WDATA[20]; // rv 0 + assign SAXIGP0WDATA_in[21] = (SAXIGP0WDATA[21] !== 1'bz) && SAXIGP0WDATA[21]; // rv 0 + assign SAXIGP0WDATA_in[22] = (SAXIGP0WDATA[22] !== 1'bz) && SAXIGP0WDATA[22]; // rv 0 + assign SAXIGP0WDATA_in[23] = (SAXIGP0WDATA[23] !== 1'bz) && SAXIGP0WDATA[23]; // rv 0 + assign SAXIGP0WDATA_in[24] = (SAXIGP0WDATA[24] !== 1'bz) && SAXIGP0WDATA[24]; // rv 0 + assign SAXIGP0WDATA_in[25] = (SAXIGP0WDATA[25] !== 1'bz) && SAXIGP0WDATA[25]; // rv 0 + assign SAXIGP0WDATA_in[26] = (SAXIGP0WDATA[26] !== 1'bz) && SAXIGP0WDATA[26]; // rv 0 + assign SAXIGP0WDATA_in[27] = (SAXIGP0WDATA[27] !== 1'bz) && SAXIGP0WDATA[27]; // rv 0 + assign SAXIGP0WDATA_in[28] = (SAXIGP0WDATA[28] !== 1'bz) && SAXIGP0WDATA[28]; // rv 0 + assign SAXIGP0WDATA_in[29] = (SAXIGP0WDATA[29] !== 1'bz) && SAXIGP0WDATA[29]; // rv 0 + assign SAXIGP0WDATA_in[2] = (SAXIGP0WDATA[2] !== 1'bz) && SAXIGP0WDATA[2]; // rv 0 + assign SAXIGP0WDATA_in[30] = (SAXIGP0WDATA[30] !== 1'bz) && SAXIGP0WDATA[30]; // rv 0 + assign SAXIGP0WDATA_in[31] = (SAXIGP0WDATA[31] !== 1'bz) && SAXIGP0WDATA[31]; // rv 0 + assign SAXIGP0WDATA_in[3] = (SAXIGP0WDATA[3] !== 1'bz) && SAXIGP0WDATA[3]; // rv 0 + assign SAXIGP0WDATA_in[4] = (SAXIGP0WDATA[4] !== 1'bz) && SAXIGP0WDATA[4]; // rv 0 + assign SAXIGP0WDATA_in[5] = (SAXIGP0WDATA[5] !== 1'bz) && SAXIGP0WDATA[5]; // rv 0 + assign SAXIGP0WDATA_in[6] = (SAXIGP0WDATA[6] !== 1'bz) && SAXIGP0WDATA[6]; // rv 0 + assign SAXIGP0WDATA_in[7] = (SAXIGP0WDATA[7] !== 1'bz) && SAXIGP0WDATA[7]; // rv 0 + assign SAXIGP0WDATA_in[8] = (SAXIGP0WDATA[8] !== 1'bz) && SAXIGP0WDATA[8]; // rv 0 + assign SAXIGP0WDATA_in[9] = (SAXIGP0WDATA[9] !== 1'bz) && SAXIGP0WDATA[9]; // rv 0 + assign SAXIGP0WID_in[0] = (SAXIGP0WID[0] !== 1'bz) && SAXIGP0WID[0]; // rv 0 + assign SAXIGP0WID_in[1] = (SAXIGP0WID[1] !== 1'bz) && SAXIGP0WID[1]; // rv 0 + assign SAXIGP0WID_in[2] = (SAXIGP0WID[2] !== 1'bz) && SAXIGP0WID[2]; // rv 0 + assign SAXIGP0WID_in[3] = (SAXIGP0WID[3] !== 1'bz) && SAXIGP0WID[3]; // rv 0 + assign SAXIGP0WID_in[4] = (SAXIGP0WID[4] !== 1'bz) && SAXIGP0WID[4]; // rv 0 + assign SAXIGP0WID_in[5] = (SAXIGP0WID[5] !== 1'bz) && SAXIGP0WID[5]; // rv 0 + assign SAXIGP0WLAST_in = (SAXIGP0WLAST !== 1'bz) && SAXIGP0WLAST; // rv 0 + assign SAXIGP0WSTRB_in[0] = (SAXIGP0WSTRB[0] !== 1'bz) && SAXIGP0WSTRB[0]; // rv 0 + assign SAXIGP0WSTRB_in[1] = (SAXIGP0WSTRB[1] !== 1'bz) && SAXIGP0WSTRB[1]; // rv 0 + assign SAXIGP0WSTRB_in[2] = (SAXIGP0WSTRB[2] !== 1'bz) && SAXIGP0WSTRB[2]; // rv 0 + assign SAXIGP0WSTRB_in[3] = (SAXIGP0WSTRB[3] !== 1'bz) && SAXIGP0WSTRB[3]; // rv 0 + assign SAXIGP0WVALID_in = (SAXIGP0WVALID !== 1'bz) && SAXIGP0WVALID; // rv 0 + assign SAXIGP1ACLK_in = (SAXIGP1ACLK !== 1'bz) && SAXIGP1ACLK; // rv 0 + assign SAXIGP1ARADDR_in[0] = (SAXIGP1ARADDR[0] !== 1'bz) && SAXIGP1ARADDR[0]; // rv 0 + assign SAXIGP1ARADDR_in[10] = (SAXIGP1ARADDR[10] !== 1'bz) && SAXIGP1ARADDR[10]; // rv 0 + assign SAXIGP1ARADDR_in[11] = (SAXIGP1ARADDR[11] !== 1'bz) && SAXIGP1ARADDR[11]; // rv 0 + assign SAXIGP1ARADDR_in[12] = (SAXIGP1ARADDR[12] !== 1'bz) && SAXIGP1ARADDR[12]; // rv 0 + assign SAXIGP1ARADDR_in[13] = (SAXIGP1ARADDR[13] !== 1'bz) && SAXIGP1ARADDR[13]; // rv 0 + assign SAXIGP1ARADDR_in[14] = (SAXIGP1ARADDR[14] !== 1'bz) && SAXIGP1ARADDR[14]; // rv 0 + assign SAXIGP1ARADDR_in[15] = (SAXIGP1ARADDR[15] !== 1'bz) && SAXIGP1ARADDR[15]; // rv 0 + assign SAXIGP1ARADDR_in[16] = (SAXIGP1ARADDR[16] !== 1'bz) && SAXIGP1ARADDR[16]; // rv 0 + assign SAXIGP1ARADDR_in[17] = (SAXIGP1ARADDR[17] !== 1'bz) && SAXIGP1ARADDR[17]; // rv 0 + assign SAXIGP1ARADDR_in[18] = (SAXIGP1ARADDR[18] !== 1'bz) && SAXIGP1ARADDR[18]; // rv 0 + assign SAXIGP1ARADDR_in[19] = (SAXIGP1ARADDR[19] !== 1'bz) && SAXIGP1ARADDR[19]; // rv 0 + assign SAXIGP1ARADDR_in[1] = (SAXIGP1ARADDR[1] !== 1'bz) && SAXIGP1ARADDR[1]; // rv 0 + assign SAXIGP1ARADDR_in[20] = (SAXIGP1ARADDR[20] !== 1'bz) && SAXIGP1ARADDR[20]; // rv 0 + assign SAXIGP1ARADDR_in[21] = (SAXIGP1ARADDR[21] !== 1'bz) && SAXIGP1ARADDR[21]; // rv 0 + assign SAXIGP1ARADDR_in[22] = (SAXIGP1ARADDR[22] !== 1'bz) && SAXIGP1ARADDR[22]; // rv 0 + assign SAXIGP1ARADDR_in[23] = (SAXIGP1ARADDR[23] !== 1'bz) && SAXIGP1ARADDR[23]; // rv 0 + assign SAXIGP1ARADDR_in[24] = (SAXIGP1ARADDR[24] !== 1'bz) && SAXIGP1ARADDR[24]; // rv 0 + assign SAXIGP1ARADDR_in[25] = (SAXIGP1ARADDR[25] !== 1'bz) && SAXIGP1ARADDR[25]; // rv 0 + assign SAXIGP1ARADDR_in[26] = (SAXIGP1ARADDR[26] !== 1'bz) && SAXIGP1ARADDR[26]; // rv 0 + assign SAXIGP1ARADDR_in[27] = (SAXIGP1ARADDR[27] !== 1'bz) && SAXIGP1ARADDR[27]; // rv 0 + assign SAXIGP1ARADDR_in[28] = (SAXIGP1ARADDR[28] !== 1'bz) && SAXIGP1ARADDR[28]; // rv 0 + assign SAXIGP1ARADDR_in[29] = (SAXIGP1ARADDR[29] !== 1'bz) && SAXIGP1ARADDR[29]; // rv 0 + assign SAXIGP1ARADDR_in[2] = (SAXIGP1ARADDR[2] !== 1'bz) && SAXIGP1ARADDR[2]; // rv 0 + assign SAXIGP1ARADDR_in[30] = (SAXIGP1ARADDR[30] !== 1'bz) && SAXIGP1ARADDR[30]; // rv 0 + assign SAXIGP1ARADDR_in[31] = (SAXIGP1ARADDR[31] !== 1'bz) && SAXIGP1ARADDR[31]; // rv 0 + assign SAXIGP1ARADDR_in[3] = (SAXIGP1ARADDR[3] !== 1'bz) && SAXIGP1ARADDR[3]; // rv 0 + assign SAXIGP1ARADDR_in[4] = (SAXIGP1ARADDR[4] !== 1'bz) && SAXIGP1ARADDR[4]; // rv 0 + assign SAXIGP1ARADDR_in[5] = (SAXIGP1ARADDR[5] !== 1'bz) && SAXIGP1ARADDR[5]; // rv 0 + assign SAXIGP1ARADDR_in[6] = (SAXIGP1ARADDR[6] !== 1'bz) && SAXIGP1ARADDR[6]; // rv 0 + assign SAXIGP1ARADDR_in[7] = (SAXIGP1ARADDR[7] !== 1'bz) && SAXIGP1ARADDR[7]; // rv 0 + assign SAXIGP1ARADDR_in[8] = (SAXIGP1ARADDR[8] !== 1'bz) && SAXIGP1ARADDR[8]; // rv 0 + assign SAXIGP1ARADDR_in[9] = (SAXIGP1ARADDR[9] !== 1'bz) && SAXIGP1ARADDR[9]; // rv 0 + assign SAXIGP1ARBURST_in[0] = (SAXIGP1ARBURST[0] !== 1'bz) && SAXIGP1ARBURST[0]; // rv 0 + assign SAXIGP1ARBURST_in[1] = (SAXIGP1ARBURST[1] !== 1'bz) && SAXIGP1ARBURST[1]; // rv 0 + assign SAXIGP1ARCACHE_in[0] = (SAXIGP1ARCACHE[0] !== 1'bz) && SAXIGP1ARCACHE[0]; // rv 0 + assign SAXIGP1ARCACHE_in[1] = (SAXIGP1ARCACHE[1] !== 1'bz) && SAXIGP1ARCACHE[1]; // rv 0 + assign SAXIGP1ARCACHE_in[2] = (SAXIGP1ARCACHE[2] !== 1'bz) && SAXIGP1ARCACHE[2]; // rv 0 + assign SAXIGP1ARCACHE_in[3] = (SAXIGP1ARCACHE[3] !== 1'bz) && SAXIGP1ARCACHE[3]; // rv 0 + assign SAXIGP1ARID_in[0] = (SAXIGP1ARID[0] !== 1'bz) && SAXIGP1ARID[0]; // rv 0 + assign SAXIGP1ARID_in[1] = (SAXIGP1ARID[1] !== 1'bz) && SAXIGP1ARID[1]; // rv 0 + assign SAXIGP1ARID_in[2] = (SAXIGP1ARID[2] !== 1'bz) && SAXIGP1ARID[2]; // rv 0 + assign SAXIGP1ARID_in[3] = (SAXIGP1ARID[3] !== 1'bz) && SAXIGP1ARID[3]; // rv 0 + assign SAXIGP1ARID_in[4] = (SAXIGP1ARID[4] !== 1'bz) && SAXIGP1ARID[4]; // rv 0 + assign SAXIGP1ARID_in[5] = (SAXIGP1ARID[5] !== 1'bz) && SAXIGP1ARID[5]; // rv 0 + assign SAXIGP1ARLEN_in[0] = (SAXIGP1ARLEN[0] !== 1'bz) && SAXIGP1ARLEN[0]; // rv 0 + assign SAXIGP1ARLEN_in[1] = (SAXIGP1ARLEN[1] !== 1'bz) && SAXIGP1ARLEN[1]; // rv 0 + assign SAXIGP1ARLEN_in[2] = (SAXIGP1ARLEN[2] !== 1'bz) && SAXIGP1ARLEN[2]; // rv 0 + assign SAXIGP1ARLEN_in[3] = (SAXIGP1ARLEN[3] !== 1'bz) && SAXIGP1ARLEN[3]; // rv 0 + assign SAXIGP1ARLOCK_in[0] = (SAXIGP1ARLOCK[0] !== 1'bz) && SAXIGP1ARLOCK[0]; // rv 0 + assign SAXIGP1ARLOCK_in[1] = (SAXIGP1ARLOCK[1] !== 1'bz) && SAXIGP1ARLOCK[1]; // rv 0 + assign SAXIGP1ARPROT_in[0] = (SAXIGP1ARPROT[0] !== 1'bz) && SAXIGP1ARPROT[0]; // rv 0 + assign SAXIGP1ARPROT_in[1] = (SAXIGP1ARPROT[1] !== 1'bz) && SAXIGP1ARPROT[1]; // rv 0 + assign SAXIGP1ARPROT_in[2] = (SAXIGP1ARPROT[2] !== 1'bz) && SAXIGP1ARPROT[2]; // rv 0 + assign SAXIGP1ARQOS_in[0] = (SAXIGP1ARQOS[0] !== 1'bz) && SAXIGP1ARQOS[0]; // rv 0 + assign SAXIGP1ARQOS_in[1] = (SAXIGP1ARQOS[1] !== 1'bz) && SAXIGP1ARQOS[1]; // rv 0 + assign SAXIGP1ARQOS_in[2] = (SAXIGP1ARQOS[2] !== 1'bz) && SAXIGP1ARQOS[2]; // rv 0 + assign SAXIGP1ARQOS_in[3] = (SAXIGP1ARQOS[3] !== 1'bz) && SAXIGP1ARQOS[3]; // rv 0 + assign SAXIGP1ARSIZE_in[0] = (SAXIGP1ARSIZE[0] !== 1'bz) && SAXIGP1ARSIZE[0]; // rv 0 + assign SAXIGP1ARSIZE_in[1] = (SAXIGP1ARSIZE[1] !== 1'bz) && SAXIGP1ARSIZE[1]; // rv 0 + assign SAXIGP1ARVALID_in = (SAXIGP1ARVALID !== 1'bz) && SAXIGP1ARVALID; // rv 0 + assign SAXIGP1AWADDR_in[0] = (SAXIGP1AWADDR[0] !== 1'bz) && SAXIGP1AWADDR[0]; // rv 0 + assign SAXIGP1AWADDR_in[10] = (SAXIGP1AWADDR[10] !== 1'bz) && SAXIGP1AWADDR[10]; // rv 0 + assign SAXIGP1AWADDR_in[11] = (SAXIGP1AWADDR[11] !== 1'bz) && SAXIGP1AWADDR[11]; // rv 0 + assign SAXIGP1AWADDR_in[12] = (SAXIGP1AWADDR[12] !== 1'bz) && SAXIGP1AWADDR[12]; // rv 0 + assign SAXIGP1AWADDR_in[13] = (SAXIGP1AWADDR[13] !== 1'bz) && SAXIGP1AWADDR[13]; // rv 0 + assign SAXIGP1AWADDR_in[14] = (SAXIGP1AWADDR[14] !== 1'bz) && SAXIGP1AWADDR[14]; // rv 0 + assign SAXIGP1AWADDR_in[15] = (SAXIGP1AWADDR[15] !== 1'bz) && SAXIGP1AWADDR[15]; // rv 0 + assign SAXIGP1AWADDR_in[16] = (SAXIGP1AWADDR[16] !== 1'bz) && SAXIGP1AWADDR[16]; // rv 0 + assign SAXIGP1AWADDR_in[17] = (SAXIGP1AWADDR[17] !== 1'bz) && SAXIGP1AWADDR[17]; // rv 0 + assign SAXIGP1AWADDR_in[18] = (SAXIGP1AWADDR[18] !== 1'bz) && SAXIGP1AWADDR[18]; // rv 0 + assign SAXIGP1AWADDR_in[19] = (SAXIGP1AWADDR[19] !== 1'bz) && SAXIGP1AWADDR[19]; // rv 0 + assign SAXIGP1AWADDR_in[1] = (SAXIGP1AWADDR[1] !== 1'bz) && SAXIGP1AWADDR[1]; // rv 0 + assign SAXIGP1AWADDR_in[20] = (SAXIGP1AWADDR[20] !== 1'bz) && SAXIGP1AWADDR[20]; // rv 0 + assign SAXIGP1AWADDR_in[21] = (SAXIGP1AWADDR[21] !== 1'bz) && SAXIGP1AWADDR[21]; // rv 0 + assign SAXIGP1AWADDR_in[22] = (SAXIGP1AWADDR[22] !== 1'bz) && SAXIGP1AWADDR[22]; // rv 0 + assign SAXIGP1AWADDR_in[23] = (SAXIGP1AWADDR[23] !== 1'bz) && SAXIGP1AWADDR[23]; // rv 0 + assign SAXIGP1AWADDR_in[24] = (SAXIGP1AWADDR[24] !== 1'bz) && SAXIGP1AWADDR[24]; // rv 0 + assign SAXIGP1AWADDR_in[25] = (SAXIGP1AWADDR[25] !== 1'bz) && SAXIGP1AWADDR[25]; // rv 0 + assign SAXIGP1AWADDR_in[26] = (SAXIGP1AWADDR[26] !== 1'bz) && SAXIGP1AWADDR[26]; // rv 0 + assign SAXIGP1AWADDR_in[27] = (SAXIGP1AWADDR[27] !== 1'bz) && SAXIGP1AWADDR[27]; // rv 0 + assign SAXIGP1AWADDR_in[28] = (SAXIGP1AWADDR[28] !== 1'bz) && SAXIGP1AWADDR[28]; // rv 0 + assign SAXIGP1AWADDR_in[29] = (SAXIGP1AWADDR[29] !== 1'bz) && SAXIGP1AWADDR[29]; // rv 0 + assign SAXIGP1AWADDR_in[2] = (SAXIGP1AWADDR[2] !== 1'bz) && SAXIGP1AWADDR[2]; // rv 0 + assign SAXIGP1AWADDR_in[30] = (SAXIGP1AWADDR[30] !== 1'bz) && SAXIGP1AWADDR[30]; // rv 0 + assign SAXIGP1AWADDR_in[31] = (SAXIGP1AWADDR[31] !== 1'bz) && SAXIGP1AWADDR[31]; // rv 0 + assign SAXIGP1AWADDR_in[3] = (SAXIGP1AWADDR[3] !== 1'bz) && SAXIGP1AWADDR[3]; // rv 0 + assign SAXIGP1AWADDR_in[4] = (SAXIGP1AWADDR[4] !== 1'bz) && SAXIGP1AWADDR[4]; // rv 0 + assign SAXIGP1AWADDR_in[5] = (SAXIGP1AWADDR[5] !== 1'bz) && SAXIGP1AWADDR[5]; // rv 0 + assign SAXIGP1AWADDR_in[6] = (SAXIGP1AWADDR[6] !== 1'bz) && SAXIGP1AWADDR[6]; // rv 0 + assign SAXIGP1AWADDR_in[7] = (SAXIGP1AWADDR[7] !== 1'bz) && SAXIGP1AWADDR[7]; // rv 0 + assign SAXIGP1AWADDR_in[8] = (SAXIGP1AWADDR[8] !== 1'bz) && SAXIGP1AWADDR[8]; // rv 0 + assign SAXIGP1AWADDR_in[9] = (SAXIGP1AWADDR[9] !== 1'bz) && SAXIGP1AWADDR[9]; // rv 0 + assign SAXIGP1AWBURST_in[0] = (SAXIGP1AWBURST[0] !== 1'bz) && SAXIGP1AWBURST[0]; // rv 0 + assign SAXIGP1AWBURST_in[1] = (SAXIGP1AWBURST[1] !== 1'bz) && SAXIGP1AWBURST[1]; // rv 0 + assign SAXIGP1AWCACHE_in[0] = (SAXIGP1AWCACHE[0] !== 1'bz) && SAXIGP1AWCACHE[0]; // rv 0 + assign SAXIGP1AWCACHE_in[1] = (SAXIGP1AWCACHE[1] !== 1'bz) && SAXIGP1AWCACHE[1]; // rv 0 + assign SAXIGP1AWCACHE_in[2] = (SAXIGP1AWCACHE[2] !== 1'bz) && SAXIGP1AWCACHE[2]; // rv 0 + assign SAXIGP1AWCACHE_in[3] = (SAXIGP1AWCACHE[3] !== 1'bz) && SAXIGP1AWCACHE[3]; // rv 0 + assign SAXIGP1AWID_in[0] = (SAXIGP1AWID[0] !== 1'bz) && SAXIGP1AWID[0]; // rv 0 + assign SAXIGP1AWID_in[1] = (SAXIGP1AWID[1] !== 1'bz) && SAXIGP1AWID[1]; // rv 0 + assign SAXIGP1AWID_in[2] = (SAXIGP1AWID[2] !== 1'bz) && SAXIGP1AWID[2]; // rv 0 + assign SAXIGP1AWID_in[3] = (SAXIGP1AWID[3] !== 1'bz) && SAXIGP1AWID[3]; // rv 0 + assign SAXIGP1AWID_in[4] = (SAXIGP1AWID[4] !== 1'bz) && SAXIGP1AWID[4]; // rv 0 + assign SAXIGP1AWID_in[5] = (SAXIGP1AWID[5] !== 1'bz) && SAXIGP1AWID[5]; // rv 0 + assign SAXIGP1AWLEN_in[0] = (SAXIGP1AWLEN[0] !== 1'bz) && SAXIGP1AWLEN[0]; // rv 0 + assign SAXIGP1AWLEN_in[1] = (SAXIGP1AWLEN[1] !== 1'bz) && SAXIGP1AWLEN[1]; // rv 0 + assign SAXIGP1AWLEN_in[2] = (SAXIGP1AWLEN[2] !== 1'bz) && SAXIGP1AWLEN[2]; // rv 0 + assign SAXIGP1AWLEN_in[3] = (SAXIGP1AWLEN[3] !== 1'bz) && SAXIGP1AWLEN[3]; // rv 0 + assign SAXIGP1AWLOCK_in[0] = (SAXIGP1AWLOCK[0] !== 1'bz) && SAXIGP1AWLOCK[0]; // rv 0 + assign SAXIGP1AWLOCK_in[1] = (SAXIGP1AWLOCK[1] !== 1'bz) && SAXIGP1AWLOCK[1]; // rv 0 + assign SAXIGP1AWPROT_in[0] = (SAXIGP1AWPROT[0] !== 1'bz) && SAXIGP1AWPROT[0]; // rv 0 + assign SAXIGP1AWPROT_in[1] = (SAXIGP1AWPROT[1] !== 1'bz) && SAXIGP1AWPROT[1]; // rv 0 + assign SAXIGP1AWPROT_in[2] = (SAXIGP1AWPROT[2] !== 1'bz) && SAXIGP1AWPROT[2]; // rv 0 + assign SAXIGP1AWQOS_in[0] = (SAXIGP1AWQOS[0] !== 1'bz) && SAXIGP1AWQOS[0]; // rv 0 + assign SAXIGP1AWQOS_in[1] = (SAXIGP1AWQOS[1] !== 1'bz) && SAXIGP1AWQOS[1]; // rv 0 + assign SAXIGP1AWQOS_in[2] = (SAXIGP1AWQOS[2] !== 1'bz) && SAXIGP1AWQOS[2]; // rv 0 + assign SAXIGP1AWQOS_in[3] = (SAXIGP1AWQOS[3] !== 1'bz) && SAXIGP1AWQOS[3]; // rv 0 + assign SAXIGP1AWSIZE_in[0] = (SAXIGP1AWSIZE[0] !== 1'bz) && SAXIGP1AWSIZE[0]; // rv 0 + assign SAXIGP1AWSIZE_in[1] = (SAXIGP1AWSIZE[1] !== 1'bz) && SAXIGP1AWSIZE[1]; // rv 0 + assign SAXIGP1AWVALID_in = (SAXIGP1AWVALID !== 1'bz) && SAXIGP1AWVALID; // rv 0 + assign SAXIGP1BREADY_in = (SAXIGP1BREADY !== 1'bz) && SAXIGP1BREADY; // rv 0 + assign SAXIGP1RREADY_in = (SAXIGP1RREADY !== 1'bz) && SAXIGP1RREADY; // rv 0 + assign SAXIGP1WDATA_in[0] = (SAXIGP1WDATA[0] !== 1'bz) && SAXIGP1WDATA[0]; // rv 0 + assign SAXIGP1WDATA_in[10] = (SAXIGP1WDATA[10] !== 1'bz) && SAXIGP1WDATA[10]; // rv 0 + assign SAXIGP1WDATA_in[11] = (SAXIGP1WDATA[11] !== 1'bz) && SAXIGP1WDATA[11]; // rv 0 + assign SAXIGP1WDATA_in[12] = (SAXIGP1WDATA[12] !== 1'bz) && SAXIGP1WDATA[12]; // rv 0 + assign SAXIGP1WDATA_in[13] = (SAXIGP1WDATA[13] !== 1'bz) && SAXIGP1WDATA[13]; // rv 0 + assign SAXIGP1WDATA_in[14] = (SAXIGP1WDATA[14] !== 1'bz) && SAXIGP1WDATA[14]; // rv 0 + assign SAXIGP1WDATA_in[15] = (SAXIGP1WDATA[15] !== 1'bz) && SAXIGP1WDATA[15]; // rv 0 + assign SAXIGP1WDATA_in[16] = (SAXIGP1WDATA[16] !== 1'bz) && SAXIGP1WDATA[16]; // rv 0 + assign SAXIGP1WDATA_in[17] = (SAXIGP1WDATA[17] !== 1'bz) && SAXIGP1WDATA[17]; // rv 0 + assign SAXIGP1WDATA_in[18] = (SAXIGP1WDATA[18] !== 1'bz) && SAXIGP1WDATA[18]; // rv 0 + assign SAXIGP1WDATA_in[19] = (SAXIGP1WDATA[19] !== 1'bz) && SAXIGP1WDATA[19]; // rv 0 + assign SAXIGP1WDATA_in[1] = (SAXIGP1WDATA[1] !== 1'bz) && SAXIGP1WDATA[1]; // rv 0 + assign SAXIGP1WDATA_in[20] = (SAXIGP1WDATA[20] !== 1'bz) && SAXIGP1WDATA[20]; // rv 0 + assign SAXIGP1WDATA_in[21] = (SAXIGP1WDATA[21] !== 1'bz) && SAXIGP1WDATA[21]; // rv 0 + assign SAXIGP1WDATA_in[22] = (SAXIGP1WDATA[22] !== 1'bz) && SAXIGP1WDATA[22]; // rv 0 + assign SAXIGP1WDATA_in[23] = (SAXIGP1WDATA[23] !== 1'bz) && SAXIGP1WDATA[23]; // rv 0 + assign SAXIGP1WDATA_in[24] = (SAXIGP1WDATA[24] !== 1'bz) && SAXIGP1WDATA[24]; // rv 0 + assign SAXIGP1WDATA_in[25] = (SAXIGP1WDATA[25] !== 1'bz) && SAXIGP1WDATA[25]; // rv 0 + assign SAXIGP1WDATA_in[26] = (SAXIGP1WDATA[26] !== 1'bz) && SAXIGP1WDATA[26]; // rv 0 + assign SAXIGP1WDATA_in[27] = (SAXIGP1WDATA[27] !== 1'bz) && SAXIGP1WDATA[27]; // rv 0 + assign SAXIGP1WDATA_in[28] = (SAXIGP1WDATA[28] !== 1'bz) && SAXIGP1WDATA[28]; // rv 0 + assign SAXIGP1WDATA_in[29] = (SAXIGP1WDATA[29] !== 1'bz) && SAXIGP1WDATA[29]; // rv 0 + assign SAXIGP1WDATA_in[2] = (SAXIGP1WDATA[2] !== 1'bz) && SAXIGP1WDATA[2]; // rv 0 + assign SAXIGP1WDATA_in[30] = (SAXIGP1WDATA[30] !== 1'bz) && SAXIGP1WDATA[30]; // rv 0 + assign SAXIGP1WDATA_in[31] = (SAXIGP1WDATA[31] !== 1'bz) && SAXIGP1WDATA[31]; // rv 0 + assign SAXIGP1WDATA_in[3] = (SAXIGP1WDATA[3] !== 1'bz) && SAXIGP1WDATA[3]; // rv 0 + assign SAXIGP1WDATA_in[4] = (SAXIGP1WDATA[4] !== 1'bz) && SAXIGP1WDATA[4]; // rv 0 + assign SAXIGP1WDATA_in[5] = (SAXIGP1WDATA[5] !== 1'bz) && SAXIGP1WDATA[5]; // rv 0 + assign SAXIGP1WDATA_in[6] = (SAXIGP1WDATA[6] !== 1'bz) && SAXIGP1WDATA[6]; // rv 0 + assign SAXIGP1WDATA_in[7] = (SAXIGP1WDATA[7] !== 1'bz) && SAXIGP1WDATA[7]; // rv 0 + assign SAXIGP1WDATA_in[8] = (SAXIGP1WDATA[8] !== 1'bz) && SAXIGP1WDATA[8]; // rv 0 + assign SAXIGP1WDATA_in[9] = (SAXIGP1WDATA[9] !== 1'bz) && SAXIGP1WDATA[9]; // rv 0 + assign SAXIGP1WID_in[0] = (SAXIGP1WID[0] !== 1'bz) && SAXIGP1WID[0]; // rv 0 + assign SAXIGP1WID_in[1] = (SAXIGP1WID[1] !== 1'bz) && SAXIGP1WID[1]; // rv 0 + assign SAXIGP1WID_in[2] = (SAXIGP1WID[2] !== 1'bz) && SAXIGP1WID[2]; // rv 0 + assign SAXIGP1WID_in[3] = (SAXIGP1WID[3] !== 1'bz) && SAXIGP1WID[3]; // rv 0 + assign SAXIGP1WID_in[4] = (SAXIGP1WID[4] !== 1'bz) && SAXIGP1WID[4]; // rv 0 + assign SAXIGP1WID_in[5] = (SAXIGP1WID[5] !== 1'bz) && SAXIGP1WID[5]; // rv 0 + assign SAXIGP1WLAST_in = (SAXIGP1WLAST !== 1'bz) && SAXIGP1WLAST; // rv 0 + assign SAXIGP1WSTRB_in[0] = (SAXIGP1WSTRB[0] !== 1'bz) && SAXIGP1WSTRB[0]; // rv 0 + assign SAXIGP1WSTRB_in[1] = (SAXIGP1WSTRB[1] !== 1'bz) && SAXIGP1WSTRB[1]; // rv 0 + assign SAXIGP1WSTRB_in[2] = (SAXIGP1WSTRB[2] !== 1'bz) && SAXIGP1WSTRB[2]; // rv 0 + assign SAXIGP1WSTRB_in[3] = (SAXIGP1WSTRB[3] !== 1'bz) && SAXIGP1WSTRB[3]; // rv 0 + assign SAXIGP1WVALID_in = (SAXIGP1WVALID !== 1'bz) && SAXIGP1WVALID; // rv 0 + assign SAXIHP0ACLK_in = (SAXIHP0ACLK !== 1'bz) && SAXIHP0ACLK; // rv 0 + assign SAXIHP0ARADDR_in[0] = (SAXIHP0ARADDR[0] !== 1'bz) && SAXIHP0ARADDR[0]; // rv 0 + assign SAXIHP0ARADDR_in[10] = (SAXIHP0ARADDR[10] !== 1'bz) && SAXIHP0ARADDR[10]; // rv 0 + assign SAXIHP0ARADDR_in[11] = (SAXIHP0ARADDR[11] !== 1'bz) && SAXIHP0ARADDR[11]; // rv 0 + assign SAXIHP0ARADDR_in[12] = (SAXIHP0ARADDR[12] !== 1'bz) && SAXIHP0ARADDR[12]; // rv 0 + assign SAXIHP0ARADDR_in[13] = (SAXIHP0ARADDR[13] !== 1'bz) && SAXIHP0ARADDR[13]; // rv 0 + assign SAXIHP0ARADDR_in[14] = (SAXIHP0ARADDR[14] !== 1'bz) && SAXIHP0ARADDR[14]; // rv 0 + assign SAXIHP0ARADDR_in[15] = (SAXIHP0ARADDR[15] !== 1'bz) && SAXIHP0ARADDR[15]; // rv 0 + assign SAXIHP0ARADDR_in[16] = (SAXIHP0ARADDR[16] !== 1'bz) && SAXIHP0ARADDR[16]; // rv 0 + assign SAXIHP0ARADDR_in[17] = (SAXIHP0ARADDR[17] !== 1'bz) && SAXIHP0ARADDR[17]; // rv 0 + assign SAXIHP0ARADDR_in[18] = (SAXIHP0ARADDR[18] !== 1'bz) && SAXIHP0ARADDR[18]; // rv 0 + assign SAXIHP0ARADDR_in[19] = (SAXIHP0ARADDR[19] !== 1'bz) && SAXIHP0ARADDR[19]; // rv 0 + assign SAXIHP0ARADDR_in[1] = (SAXIHP0ARADDR[1] !== 1'bz) && SAXIHP0ARADDR[1]; // rv 0 + assign SAXIHP0ARADDR_in[20] = (SAXIHP0ARADDR[20] !== 1'bz) && SAXIHP0ARADDR[20]; // rv 0 + assign SAXIHP0ARADDR_in[21] = (SAXIHP0ARADDR[21] !== 1'bz) && SAXIHP0ARADDR[21]; // rv 0 + assign SAXIHP0ARADDR_in[22] = (SAXIHP0ARADDR[22] !== 1'bz) && SAXIHP0ARADDR[22]; // rv 0 + assign SAXIHP0ARADDR_in[23] = (SAXIHP0ARADDR[23] !== 1'bz) && SAXIHP0ARADDR[23]; // rv 0 + assign SAXIHP0ARADDR_in[24] = (SAXIHP0ARADDR[24] !== 1'bz) && SAXIHP0ARADDR[24]; // rv 0 + assign SAXIHP0ARADDR_in[25] = (SAXIHP0ARADDR[25] !== 1'bz) && SAXIHP0ARADDR[25]; // rv 0 + assign SAXIHP0ARADDR_in[26] = (SAXIHP0ARADDR[26] !== 1'bz) && SAXIHP0ARADDR[26]; // rv 0 + assign SAXIHP0ARADDR_in[27] = (SAXIHP0ARADDR[27] !== 1'bz) && SAXIHP0ARADDR[27]; // rv 0 + assign SAXIHP0ARADDR_in[28] = (SAXIHP0ARADDR[28] !== 1'bz) && SAXIHP0ARADDR[28]; // rv 0 + assign SAXIHP0ARADDR_in[29] = (SAXIHP0ARADDR[29] !== 1'bz) && SAXIHP0ARADDR[29]; // rv 0 + assign SAXIHP0ARADDR_in[2] = (SAXIHP0ARADDR[2] !== 1'bz) && SAXIHP0ARADDR[2]; // rv 0 + assign SAXIHP0ARADDR_in[30] = (SAXIHP0ARADDR[30] !== 1'bz) && SAXIHP0ARADDR[30]; // rv 0 + assign SAXIHP0ARADDR_in[31] = (SAXIHP0ARADDR[31] !== 1'bz) && SAXIHP0ARADDR[31]; // rv 0 + assign SAXIHP0ARADDR_in[3] = (SAXIHP0ARADDR[3] !== 1'bz) && SAXIHP0ARADDR[3]; // rv 0 + assign SAXIHP0ARADDR_in[4] = (SAXIHP0ARADDR[4] !== 1'bz) && SAXIHP0ARADDR[4]; // rv 0 + assign SAXIHP0ARADDR_in[5] = (SAXIHP0ARADDR[5] !== 1'bz) && SAXIHP0ARADDR[5]; // rv 0 + assign SAXIHP0ARADDR_in[6] = (SAXIHP0ARADDR[6] !== 1'bz) && SAXIHP0ARADDR[6]; // rv 0 + assign SAXIHP0ARADDR_in[7] = (SAXIHP0ARADDR[7] !== 1'bz) && SAXIHP0ARADDR[7]; // rv 0 + assign SAXIHP0ARADDR_in[8] = (SAXIHP0ARADDR[8] !== 1'bz) && SAXIHP0ARADDR[8]; // rv 0 + assign SAXIHP0ARADDR_in[9] = (SAXIHP0ARADDR[9] !== 1'bz) && SAXIHP0ARADDR[9]; // rv 0 + assign SAXIHP0ARBURST_in[0] = (SAXIHP0ARBURST[0] !== 1'bz) && SAXIHP0ARBURST[0]; // rv 0 + assign SAXIHP0ARBURST_in[1] = (SAXIHP0ARBURST[1] !== 1'bz) && SAXIHP0ARBURST[1]; // rv 0 + assign SAXIHP0ARCACHE_in[0] = (SAXIHP0ARCACHE[0] !== 1'bz) && SAXIHP0ARCACHE[0]; // rv 0 + assign SAXIHP0ARCACHE_in[1] = (SAXIHP0ARCACHE[1] !== 1'bz) && SAXIHP0ARCACHE[1]; // rv 0 + assign SAXIHP0ARCACHE_in[2] = (SAXIHP0ARCACHE[2] !== 1'bz) && SAXIHP0ARCACHE[2]; // rv 0 + assign SAXIHP0ARCACHE_in[3] = (SAXIHP0ARCACHE[3] !== 1'bz) && SAXIHP0ARCACHE[3]; // rv 0 + assign SAXIHP0ARID_in[0] = (SAXIHP0ARID[0] !== 1'bz) && SAXIHP0ARID[0]; // rv 0 + assign SAXIHP0ARID_in[1] = (SAXIHP0ARID[1] !== 1'bz) && SAXIHP0ARID[1]; // rv 0 + assign SAXIHP0ARID_in[2] = (SAXIHP0ARID[2] !== 1'bz) && SAXIHP0ARID[2]; // rv 0 + assign SAXIHP0ARID_in[3] = (SAXIHP0ARID[3] !== 1'bz) && SAXIHP0ARID[3]; // rv 0 + assign SAXIHP0ARID_in[4] = (SAXIHP0ARID[4] !== 1'bz) && SAXIHP0ARID[4]; // rv 0 + assign SAXIHP0ARID_in[5] = (SAXIHP0ARID[5] !== 1'bz) && SAXIHP0ARID[5]; // rv 0 + assign SAXIHP0ARLEN_in[0] = (SAXIHP0ARLEN[0] !== 1'bz) && SAXIHP0ARLEN[0]; // rv 0 + assign SAXIHP0ARLEN_in[1] = (SAXIHP0ARLEN[1] !== 1'bz) && SAXIHP0ARLEN[1]; // rv 0 + assign SAXIHP0ARLEN_in[2] = (SAXIHP0ARLEN[2] !== 1'bz) && SAXIHP0ARLEN[2]; // rv 0 + assign SAXIHP0ARLEN_in[3] = (SAXIHP0ARLEN[3] !== 1'bz) && SAXIHP0ARLEN[3]; // rv 0 + assign SAXIHP0ARLOCK_in[0] = (SAXIHP0ARLOCK[0] !== 1'bz) && SAXIHP0ARLOCK[0]; // rv 0 + assign SAXIHP0ARLOCK_in[1] = (SAXIHP0ARLOCK[1] !== 1'bz) && SAXIHP0ARLOCK[1]; // rv 0 + assign SAXIHP0ARPROT_in[0] = (SAXIHP0ARPROT[0] !== 1'bz) && SAXIHP0ARPROT[0]; // rv 0 + assign SAXIHP0ARPROT_in[1] = (SAXIHP0ARPROT[1] !== 1'bz) && SAXIHP0ARPROT[1]; // rv 0 + assign SAXIHP0ARPROT_in[2] = (SAXIHP0ARPROT[2] !== 1'bz) && SAXIHP0ARPROT[2]; // rv 0 + assign SAXIHP0ARQOS_in[0] = (SAXIHP0ARQOS[0] !== 1'bz) && SAXIHP0ARQOS[0]; // rv 0 + assign SAXIHP0ARQOS_in[1] = (SAXIHP0ARQOS[1] !== 1'bz) && SAXIHP0ARQOS[1]; // rv 0 + assign SAXIHP0ARQOS_in[2] = (SAXIHP0ARQOS[2] !== 1'bz) && SAXIHP0ARQOS[2]; // rv 0 + assign SAXIHP0ARQOS_in[3] = (SAXIHP0ARQOS[3] !== 1'bz) && SAXIHP0ARQOS[3]; // rv 0 + assign SAXIHP0ARSIZE_in[0] = (SAXIHP0ARSIZE[0] !== 1'bz) && SAXIHP0ARSIZE[0]; // rv 0 + assign SAXIHP0ARSIZE_in[1] = (SAXIHP0ARSIZE[1] !== 1'bz) && SAXIHP0ARSIZE[1]; // rv 0 + assign SAXIHP0ARVALID_in = (SAXIHP0ARVALID !== 1'bz) && SAXIHP0ARVALID; // rv 0 + assign SAXIHP0AWADDR_in[0] = (SAXIHP0AWADDR[0] !== 1'bz) && SAXIHP0AWADDR[0]; // rv 0 + assign SAXIHP0AWADDR_in[10] = (SAXIHP0AWADDR[10] !== 1'bz) && SAXIHP0AWADDR[10]; // rv 0 + assign SAXIHP0AWADDR_in[11] = (SAXIHP0AWADDR[11] !== 1'bz) && SAXIHP0AWADDR[11]; // rv 0 + assign SAXIHP0AWADDR_in[12] = (SAXIHP0AWADDR[12] !== 1'bz) && SAXIHP0AWADDR[12]; // rv 0 + assign SAXIHP0AWADDR_in[13] = (SAXIHP0AWADDR[13] !== 1'bz) && SAXIHP0AWADDR[13]; // rv 0 + assign SAXIHP0AWADDR_in[14] = (SAXIHP0AWADDR[14] !== 1'bz) && SAXIHP0AWADDR[14]; // rv 0 + assign SAXIHP0AWADDR_in[15] = (SAXIHP0AWADDR[15] !== 1'bz) && SAXIHP0AWADDR[15]; // rv 0 + assign SAXIHP0AWADDR_in[16] = (SAXIHP0AWADDR[16] !== 1'bz) && SAXIHP0AWADDR[16]; // rv 0 + assign SAXIHP0AWADDR_in[17] = (SAXIHP0AWADDR[17] !== 1'bz) && SAXIHP0AWADDR[17]; // rv 0 + assign SAXIHP0AWADDR_in[18] = (SAXIHP0AWADDR[18] !== 1'bz) && SAXIHP0AWADDR[18]; // rv 0 + assign SAXIHP0AWADDR_in[19] = (SAXIHP0AWADDR[19] !== 1'bz) && SAXIHP0AWADDR[19]; // rv 0 + assign SAXIHP0AWADDR_in[1] = (SAXIHP0AWADDR[1] !== 1'bz) && SAXIHP0AWADDR[1]; // rv 0 + assign SAXIHP0AWADDR_in[20] = (SAXIHP0AWADDR[20] !== 1'bz) && SAXIHP0AWADDR[20]; // rv 0 + assign SAXIHP0AWADDR_in[21] = (SAXIHP0AWADDR[21] !== 1'bz) && SAXIHP0AWADDR[21]; // rv 0 + assign SAXIHP0AWADDR_in[22] = (SAXIHP0AWADDR[22] !== 1'bz) && SAXIHP0AWADDR[22]; // rv 0 + assign SAXIHP0AWADDR_in[23] = (SAXIHP0AWADDR[23] !== 1'bz) && SAXIHP0AWADDR[23]; // rv 0 + assign SAXIHP0AWADDR_in[24] = (SAXIHP0AWADDR[24] !== 1'bz) && SAXIHP0AWADDR[24]; // rv 0 + assign SAXIHP0AWADDR_in[25] = (SAXIHP0AWADDR[25] !== 1'bz) && SAXIHP0AWADDR[25]; // rv 0 + assign SAXIHP0AWADDR_in[26] = (SAXIHP0AWADDR[26] !== 1'bz) && SAXIHP0AWADDR[26]; // rv 0 + assign SAXIHP0AWADDR_in[27] = (SAXIHP0AWADDR[27] !== 1'bz) && SAXIHP0AWADDR[27]; // rv 0 + assign SAXIHP0AWADDR_in[28] = (SAXIHP0AWADDR[28] !== 1'bz) && SAXIHP0AWADDR[28]; // rv 0 + assign SAXIHP0AWADDR_in[29] = (SAXIHP0AWADDR[29] !== 1'bz) && SAXIHP0AWADDR[29]; // rv 0 + assign SAXIHP0AWADDR_in[2] = (SAXIHP0AWADDR[2] !== 1'bz) && SAXIHP0AWADDR[2]; // rv 0 + assign SAXIHP0AWADDR_in[30] = (SAXIHP0AWADDR[30] !== 1'bz) && SAXIHP0AWADDR[30]; // rv 0 + assign SAXIHP0AWADDR_in[31] = (SAXIHP0AWADDR[31] !== 1'bz) && SAXIHP0AWADDR[31]; // rv 0 + assign SAXIHP0AWADDR_in[3] = (SAXIHP0AWADDR[3] !== 1'bz) && SAXIHP0AWADDR[3]; // rv 0 + assign SAXIHP0AWADDR_in[4] = (SAXIHP0AWADDR[4] !== 1'bz) && SAXIHP0AWADDR[4]; // rv 0 + assign SAXIHP0AWADDR_in[5] = (SAXIHP0AWADDR[5] !== 1'bz) && SAXIHP0AWADDR[5]; // rv 0 + assign SAXIHP0AWADDR_in[6] = (SAXIHP0AWADDR[6] !== 1'bz) && SAXIHP0AWADDR[6]; // rv 0 + assign SAXIHP0AWADDR_in[7] = (SAXIHP0AWADDR[7] !== 1'bz) && SAXIHP0AWADDR[7]; // rv 0 + assign SAXIHP0AWADDR_in[8] = (SAXIHP0AWADDR[8] !== 1'bz) && SAXIHP0AWADDR[8]; // rv 0 + assign SAXIHP0AWADDR_in[9] = (SAXIHP0AWADDR[9] !== 1'bz) && SAXIHP0AWADDR[9]; // rv 0 + assign SAXIHP0AWBURST_in[0] = (SAXIHP0AWBURST[0] !== 1'bz) && SAXIHP0AWBURST[0]; // rv 0 + assign SAXIHP0AWBURST_in[1] = (SAXIHP0AWBURST[1] !== 1'bz) && SAXIHP0AWBURST[1]; // rv 0 + assign SAXIHP0AWCACHE_in[0] = (SAXIHP0AWCACHE[0] !== 1'bz) && SAXIHP0AWCACHE[0]; // rv 0 + assign SAXIHP0AWCACHE_in[1] = (SAXIHP0AWCACHE[1] !== 1'bz) && SAXIHP0AWCACHE[1]; // rv 0 + assign SAXIHP0AWCACHE_in[2] = (SAXIHP0AWCACHE[2] !== 1'bz) && SAXIHP0AWCACHE[2]; // rv 0 + assign SAXIHP0AWCACHE_in[3] = (SAXIHP0AWCACHE[3] !== 1'bz) && SAXIHP0AWCACHE[3]; // rv 0 + assign SAXIHP0AWID_in[0] = (SAXIHP0AWID[0] !== 1'bz) && SAXIHP0AWID[0]; // rv 0 + assign SAXIHP0AWID_in[1] = (SAXIHP0AWID[1] !== 1'bz) && SAXIHP0AWID[1]; // rv 0 + assign SAXIHP0AWID_in[2] = (SAXIHP0AWID[2] !== 1'bz) && SAXIHP0AWID[2]; // rv 0 + assign SAXIHP0AWID_in[3] = (SAXIHP0AWID[3] !== 1'bz) && SAXIHP0AWID[3]; // rv 0 + assign SAXIHP0AWID_in[4] = (SAXIHP0AWID[4] !== 1'bz) && SAXIHP0AWID[4]; // rv 0 + assign SAXIHP0AWID_in[5] = (SAXIHP0AWID[5] !== 1'bz) && SAXIHP0AWID[5]; // rv 0 + assign SAXIHP0AWLEN_in[0] = (SAXIHP0AWLEN[0] !== 1'bz) && SAXIHP0AWLEN[0]; // rv 0 + assign SAXIHP0AWLEN_in[1] = (SAXIHP0AWLEN[1] !== 1'bz) && SAXIHP0AWLEN[1]; // rv 0 + assign SAXIHP0AWLEN_in[2] = (SAXIHP0AWLEN[2] !== 1'bz) && SAXIHP0AWLEN[2]; // rv 0 + assign SAXIHP0AWLEN_in[3] = (SAXIHP0AWLEN[3] !== 1'bz) && SAXIHP0AWLEN[3]; // rv 0 + assign SAXIHP0AWLOCK_in[0] = (SAXIHP0AWLOCK[0] !== 1'bz) && SAXIHP0AWLOCK[0]; // rv 0 + assign SAXIHP0AWLOCK_in[1] = (SAXIHP0AWLOCK[1] !== 1'bz) && SAXIHP0AWLOCK[1]; // rv 0 + assign SAXIHP0AWPROT_in[0] = (SAXIHP0AWPROT[0] !== 1'bz) && SAXIHP0AWPROT[0]; // rv 0 + assign SAXIHP0AWPROT_in[1] = (SAXIHP0AWPROT[1] !== 1'bz) && SAXIHP0AWPROT[1]; // rv 0 + assign SAXIHP0AWPROT_in[2] = (SAXIHP0AWPROT[2] !== 1'bz) && SAXIHP0AWPROT[2]; // rv 0 + assign SAXIHP0AWQOS_in[0] = (SAXIHP0AWQOS[0] !== 1'bz) && SAXIHP0AWQOS[0]; // rv 0 + assign SAXIHP0AWQOS_in[1] = (SAXIHP0AWQOS[1] !== 1'bz) && SAXIHP0AWQOS[1]; // rv 0 + assign SAXIHP0AWQOS_in[2] = (SAXIHP0AWQOS[2] !== 1'bz) && SAXIHP0AWQOS[2]; // rv 0 + assign SAXIHP0AWQOS_in[3] = (SAXIHP0AWQOS[3] !== 1'bz) && SAXIHP0AWQOS[3]; // rv 0 + assign SAXIHP0AWSIZE_in[0] = (SAXIHP0AWSIZE[0] !== 1'bz) && SAXIHP0AWSIZE[0]; // rv 0 + assign SAXIHP0AWSIZE_in[1] = (SAXIHP0AWSIZE[1] !== 1'bz) && SAXIHP0AWSIZE[1]; // rv 0 + assign SAXIHP0AWVALID_in = (SAXIHP0AWVALID !== 1'bz) && SAXIHP0AWVALID; // rv 0 + assign SAXIHP0BREADY_in = (SAXIHP0BREADY !== 1'bz) && SAXIHP0BREADY; // rv 0 + assign SAXIHP0RREADY_in = (SAXIHP0RREADY !== 1'bz) && SAXIHP0RREADY; // rv 0 + assign SAXIHP0WDATA_in[0] = (SAXIHP0WDATA[0] !== 1'bz) && SAXIHP0WDATA[0]; // rv 0 + assign SAXIHP0WDATA_in[10] = (SAXIHP0WDATA[10] !== 1'bz) && SAXIHP0WDATA[10]; // rv 0 + assign SAXIHP0WDATA_in[11] = (SAXIHP0WDATA[11] !== 1'bz) && SAXIHP0WDATA[11]; // rv 0 + assign SAXIHP0WDATA_in[12] = (SAXIHP0WDATA[12] !== 1'bz) && SAXIHP0WDATA[12]; // rv 0 + assign SAXIHP0WDATA_in[13] = (SAXIHP0WDATA[13] !== 1'bz) && SAXIHP0WDATA[13]; // rv 0 + assign SAXIHP0WDATA_in[14] = (SAXIHP0WDATA[14] !== 1'bz) && SAXIHP0WDATA[14]; // rv 0 + assign SAXIHP0WDATA_in[15] = (SAXIHP0WDATA[15] !== 1'bz) && SAXIHP0WDATA[15]; // rv 0 + assign SAXIHP0WDATA_in[16] = (SAXIHP0WDATA[16] !== 1'bz) && SAXIHP0WDATA[16]; // rv 0 + assign SAXIHP0WDATA_in[17] = (SAXIHP0WDATA[17] !== 1'bz) && SAXIHP0WDATA[17]; // rv 0 + assign SAXIHP0WDATA_in[18] = (SAXIHP0WDATA[18] !== 1'bz) && SAXIHP0WDATA[18]; // rv 0 + assign SAXIHP0WDATA_in[19] = (SAXIHP0WDATA[19] !== 1'bz) && SAXIHP0WDATA[19]; // rv 0 + assign SAXIHP0WDATA_in[1] = (SAXIHP0WDATA[1] !== 1'bz) && SAXIHP0WDATA[1]; // rv 0 + assign SAXIHP0WDATA_in[20] = (SAXIHP0WDATA[20] !== 1'bz) && SAXIHP0WDATA[20]; // rv 0 + assign SAXIHP0WDATA_in[21] = (SAXIHP0WDATA[21] !== 1'bz) && SAXIHP0WDATA[21]; // rv 0 + assign SAXIHP0WDATA_in[22] = (SAXIHP0WDATA[22] !== 1'bz) && SAXIHP0WDATA[22]; // rv 0 + assign SAXIHP0WDATA_in[23] = (SAXIHP0WDATA[23] !== 1'bz) && SAXIHP0WDATA[23]; // rv 0 + assign SAXIHP0WDATA_in[24] = (SAXIHP0WDATA[24] !== 1'bz) && SAXIHP0WDATA[24]; // rv 0 + assign SAXIHP0WDATA_in[25] = (SAXIHP0WDATA[25] !== 1'bz) && SAXIHP0WDATA[25]; // rv 0 + assign SAXIHP0WDATA_in[26] = (SAXIHP0WDATA[26] !== 1'bz) && SAXIHP0WDATA[26]; // rv 0 + assign SAXIHP0WDATA_in[27] = (SAXIHP0WDATA[27] !== 1'bz) && SAXIHP0WDATA[27]; // rv 0 + assign SAXIHP0WDATA_in[28] = (SAXIHP0WDATA[28] !== 1'bz) && SAXIHP0WDATA[28]; // rv 0 + assign SAXIHP0WDATA_in[29] = (SAXIHP0WDATA[29] !== 1'bz) && SAXIHP0WDATA[29]; // rv 0 + assign SAXIHP0WDATA_in[2] = (SAXIHP0WDATA[2] !== 1'bz) && SAXIHP0WDATA[2]; // rv 0 + assign SAXIHP0WDATA_in[30] = (SAXIHP0WDATA[30] !== 1'bz) && SAXIHP0WDATA[30]; // rv 0 + assign SAXIHP0WDATA_in[31] = (SAXIHP0WDATA[31] !== 1'bz) && SAXIHP0WDATA[31]; // rv 0 + assign SAXIHP0WDATA_in[32] = (SAXIHP0WDATA[32] !== 1'bz) && SAXIHP0WDATA[32]; // rv 0 + assign SAXIHP0WDATA_in[33] = (SAXIHP0WDATA[33] !== 1'bz) && SAXIHP0WDATA[33]; // rv 0 + assign SAXIHP0WDATA_in[34] = (SAXIHP0WDATA[34] !== 1'bz) && SAXIHP0WDATA[34]; // rv 0 + assign SAXIHP0WDATA_in[35] = (SAXIHP0WDATA[35] !== 1'bz) && SAXIHP0WDATA[35]; // rv 0 + assign SAXIHP0WDATA_in[36] = (SAXIHP0WDATA[36] !== 1'bz) && SAXIHP0WDATA[36]; // rv 0 + assign SAXIHP0WDATA_in[37] = (SAXIHP0WDATA[37] !== 1'bz) && SAXIHP0WDATA[37]; // rv 0 + assign SAXIHP0WDATA_in[38] = (SAXIHP0WDATA[38] !== 1'bz) && SAXIHP0WDATA[38]; // rv 0 + assign SAXIHP0WDATA_in[39] = (SAXIHP0WDATA[39] !== 1'bz) && SAXIHP0WDATA[39]; // rv 0 + assign SAXIHP0WDATA_in[3] = (SAXIHP0WDATA[3] !== 1'bz) && SAXIHP0WDATA[3]; // rv 0 + assign SAXIHP0WDATA_in[40] = (SAXIHP0WDATA[40] !== 1'bz) && SAXIHP0WDATA[40]; // rv 0 + assign SAXIHP0WDATA_in[41] = (SAXIHP0WDATA[41] !== 1'bz) && SAXIHP0WDATA[41]; // rv 0 + assign SAXIHP0WDATA_in[42] = (SAXIHP0WDATA[42] !== 1'bz) && SAXIHP0WDATA[42]; // rv 0 + assign SAXIHP0WDATA_in[43] = (SAXIHP0WDATA[43] !== 1'bz) && SAXIHP0WDATA[43]; // rv 0 + assign SAXIHP0WDATA_in[44] = (SAXIHP0WDATA[44] !== 1'bz) && SAXIHP0WDATA[44]; // rv 0 + assign SAXIHP0WDATA_in[45] = (SAXIHP0WDATA[45] !== 1'bz) && SAXIHP0WDATA[45]; // rv 0 + assign SAXIHP0WDATA_in[46] = (SAXIHP0WDATA[46] !== 1'bz) && SAXIHP0WDATA[46]; // rv 0 + assign SAXIHP0WDATA_in[47] = (SAXIHP0WDATA[47] !== 1'bz) && SAXIHP0WDATA[47]; // rv 0 + assign SAXIHP0WDATA_in[48] = (SAXIHP0WDATA[48] !== 1'bz) && SAXIHP0WDATA[48]; // rv 0 + assign SAXIHP0WDATA_in[49] = (SAXIHP0WDATA[49] !== 1'bz) && SAXIHP0WDATA[49]; // rv 0 + assign SAXIHP0WDATA_in[4] = (SAXIHP0WDATA[4] !== 1'bz) && SAXIHP0WDATA[4]; // rv 0 + assign SAXIHP0WDATA_in[50] = (SAXIHP0WDATA[50] !== 1'bz) && SAXIHP0WDATA[50]; // rv 0 + assign SAXIHP0WDATA_in[51] = (SAXIHP0WDATA[51] !== 1'bz) && SAXIHP0WDATA[51]; // rv 0 + assign SAXIHP0WDATA_in[52] = (SAXIHP0WDATA[52] !== 1'bz) && SAXIHP0WDATA[52]; // rv 0 + assign SAXIHP0WDATA_in[53] = (SAXIHP0WDATA[53] !== 1'bz) && SAXIHP0WDATA[53]; // rv 0 + assign SAXIHP0WDATA_in[54] = (SAXIHP0WDATA[54] !== 1'bz) && SAXIHP0WDATA[54]; // rv 0 + assign SAXIHP0WDATA_in[55] = (SAXIHP0WDATA[55] !== 1'bz) && SAXIHP0WDATA[55]; // rv 0 + assign SAXIHP0WDATA_in[56] = (SAXIHP0WDATA[56] !== 1'bz) && SAXIHP0WDATA[56]; // rv 0 + assign SAXIHP0WDATA_in[57] = (SAXIHP0WDATA[57] !== 1'bz) && SAXIHP0WDATA[57]; // rv 0 + assign SAXIHP0WDATA_in[58] = (SAXIHP0WDATA[58] !== 1'bz) && SAXIHP0WDATA[58]; // rv 0 + assign SAXIHP0WDATA_in[59] = (SAXIHP0WDATA[59] !== 1'bz) && SAXIHP0WDATA[59]; // rv 0 + assign SAXIHP0WDATA_in[5] = (SAXIHP0WDATA[5] !== 1'bz) && SAXIHP0WDATA[5]; // rv 0 + assign SAXIHP0WDATA_in[60] = (SAXIHP0WDATA[60] !== 1'bz) && SAXIHP0WDATA[60]; // rv 0 + assign SAXIHP0WDATA_in[61] = (SAXIHP0WDATA[61] !== 1'bz) && SAXIHP0WDATA[61]; // rv 0 + assign SAXIHP0WDATA_in[62] = (SAXIHP0WDATA[62] !== 1'bz) && SAXIHP0WDATA[62]; // rv 0 + assign SAXIHP0WDATA_in[63] = (SAXIHP0WDATA[63] !== 1'bz) && SAXIHP0WDATA[63]; // rv 0 + assign SAXIHP0WDATA_in[6] = (SAXIHP0WDATA[6] !== 1'bz) && SAXIHP0WDATA[6]; // rv 0 + assign SAXIHP0WDATA_in[7] = (SAXIHP0WDATA[7] !== 1'bz) && SAXIHP0WDATA[7]; // rv 0 + assign SAXIHP0WDATA_in[8] = (SAXIHP0WDATA[8] !== 1'bz) && SAXIHP0WDATA[8]; // rv 0 + assign SAXIHP0WDATA_in[9] = (SAXIHP0WDATA[9] !== 1'bz) && SAXIHP0WDATA[9]; // rv 0 + assign SAXIHP0WID_in[0] = (SAXIHP0WID[0] !== 1'bz) && SAXIHP0WID[0]; // rv 0 + assign SAXIHP0WID_in[1] = (SAXIHP0WID[1] !== 1'bz) && SAXIHP0WID[1]; // rv 0 + assign SAXIHP0WID_in[2] = (SAXIHP0WID[2] !== 1'bz) && SAXIHP0WID[2]; // rv 0 + assign SAXIHP0WID_in[3] = (SAXIHP0WID[3] !== 1'bz) && SAXIHP0WID[3]; // rv 0 + assign SAXIHP0WID_in[4] = (SAXIHP0WID[4] !== 1'bz) && SAXIHP0WID[4]; // rv 0 + assign SAXIHP0WID_in[5] = (SAXIHP0WID[5] !== 1'bz) && SAXIHP0WID[5]; // rv 0 + assign SAXIHP0WLAST_in = (SAXIHP0WLAST !== 1'bz) && SAXIHP0WLAST; // rv 0 + assign SAXIHP0WSTRB_in[0] = (SAXIHP0WSTRB[0] !== 1'bz) && SAXIHP0WSTRB[0]; // rv 0 + assign SAXIHP0WSTRB_in[1] = (SAXIHP0WSTRB[1] !== 1'bz) && SAXIHP0WSTRB[1]; // rv 0 + assign SAXIHP0WSTRB_in[2] = (SAXIHP0WSTRB[2] !== 1'bz) && SAXIHP0WSTRB[2]; // rv 0 + assign SAXIHP0WSTRB_in[3] = (SAXIHP0WSTRB[3] !== 1'bz) && SAXIHP0WSTRB[3]; // rv 0 + assign SAXIHP0WSTRB_in[4] = (SAXIHP0WSTRB[4] !== 1'bz) && SAXIHP0WSTRB[4]; // rv 0 + assign SAXIHP0WSTRB_in[5] = (SAXIHP0WSTRB[5] !== 1'bz) && SAXIHP0WSTRB[5]; // rv 0 + assign SAXIHP0WSTRB_in[6] = (SAXIHP0WSTRB[6] !== 1'bz) && SAXIHP0WSTRB[6]; // rv 0 + assign SAXIHP0WSTRB_in[7] = (SAXIHP0WSTRB[7] !== 1'bz) && SAXIHP0WSTRB[7]; // rv 0 + assign SAXIHP0WVALID_in = (SAXIHP0WVALID !== 1'bz) && SAXIHP0WVALID; // rv 0 + assign SAXIHP1ACLK_in = (SAXIHP1ACLK !== 1'bz) && SAXIHP1ACLK; // rv 0 + assign SAXIHP1ARADDR_in[0] = (SAXIHP1ARADDR[0] !== 1'bz) && SAXIHP1ARADDR[0]; // rv 0 + assign SAXIHP1ARADDR_in[10] = (SAXIHP1ARADDR[10] !== 1'bz) && SAXIHP1ARADDR[10]; // rv 0 + assign SAXIHP1ARADDR_in[11] = (SAXIHP1ARADDR[11] !== 1'bz) && SAXIHP1ARADDR[11]; // rv 0 + assign SAXIHP1ARADDR_in[12] = (SAXIHP1ARADDR[12] !== 1'bz) && SAXIHP1ARADDR[12]; // rv 0 + assign SAXIHP1ARADDR_in[13] = (SAXIHP1ARADDR[13] !== 1'bz) && SAXIHP1ARADDR[13]; // rv 0 + assign SAXIHP1ARADDR_in[14] = (SAXIHP1ARADDR[14] !== 1'bz) && SAXIHP1ARADDR[14]; // rv 0 + assign SAXIHP1ARADDR_in[15] = (SAXIHP1ARADDR[15] !== 1'bz) && SAXIHP1ARADDR[15]; // rv 0 + assign SAXIHP1ARADDR_in[16] = (SAXIHP1ARADDR[16] !== 1'bz) && SAXIHP1ARADDR[16]; // rv 0 + assign SAXIHP1ARADDR_in[17] = (SAXIHP1ARADDR[17] !== 1'bz) && SAXIHP1ARADDR[17]; // rv 0 + assign SAXIHP1ARADDR_in[18] = (SAXIHP1ARADDR[18] !== 1'bz) && SAXIHP1ARADDR[18]; // rv 0 + assign SAXIHP1ARADDR_in[19] = (SAXIHP1ARADDR[19] !== 1'bz) && SAXIHP1ARADDR[19]; // rv 0 + assign SAXIHP1ARADDR_in[1] = (SAXIHP1ARADDR[1] !== 1'bz) && SAXIHP1ARADDR[1]; // rv 0 + assign SAXIHP1ARADDR_in[20] = (SAXIHP1ARADDR[20] !== 1'bz) && SAXIHP1ARADDR[20]; // rv 0 + assign SAXIHP1ARADDR_in[21] = (SAXIHP1ARADDR[21] !== 1'bz) && SAXIHP1ARADDR[21]; // rv 0 + assign SAXIHP1ARADDR_in[22] = (SAXIHP1ARADDR[22] !== 1'bz) && SAXIHP1ARADDR[22]; // rv 0 + assign SAXIHP1ARADDR_in[23] = (SAXIHP1ARADDR[23] !== 1'bz) && SAXIHP1ARADDR[23]; // rv 0 + assign SAXIHP1ARADDR_in[24] = (SAXIHP1ARADDR[24] !== 1'bz) && SAXIHP1ARADDR[24]; // rv 0 + assign SAXIHP1ARADDR_in[25] = (SAXIHP1ARADDR[25] !== 1'bz) && SAXIHP1ARADDR[25]; // rv 0 + assign SAXIHP1ARADDR_in[26] = (SAXIHP1ARADDR[26] !== 1'bz) && SAXIHP1ARADDR[26]; // rv 0 + assign SAXIHP1ARADDR_in[27] = (SAXIHP1ARADDR[27] !== 1'bz) && SAXIHP1ARADDR[27]; // rv 0 + assign SAXIHP1ARADDR_in[28] = (SAXIHP1ARADDR[28] !== 1'bz) && SAXIHP1ARADDR[28]; // rv 0 + assign SAXIHP1ARADDR_in[29] = (SAXIHP1ARADDR[29] !== 1'bz) && SAXIHP1ARADDR[29]; // rv 0 + assign SAXIHP1ARADDR_in[2] = (SAXIHP1ARADDR[2] !== 1'bz) && SAXIHP1ARADDR[2]; // rv 0 + assign SAXIHP1ARADDR_in[30] = (SAXIHP1ARADDR[30] !== 1'bz) && SAXIHP1ARADDR[30]; // rv 0 + assign SAXIHP1ARADDR_in[31] = (SAXIHP1ARADDR[31] !== 1'bz) && SAXIHP1ARADDR[31]; // rv 0 + assign SAXIHP1ARADDR_in[3] = (SAXIHP1ARADDR[3] !== 1'bz) && SAXIHP1ARADDR[3]; // rv 0 + assign SAXIHP1ARADDR_in[4] = (SAXIHP1ARADDR[4] !== 1'bz) && SAXIHP1ARADDR[4]; // rv 0 + assign SAXIHP1ARADDR_in[5] = (SAXIHP1ARADDR[5] !== 1'bz) && SAXIHP1ARADDR[5]; // rv 0 + assign SAXIHP1ARADDR_in[6] = (SAXIHP1ARADDR[6] !== 1'bz) && SAXIHP1ARADDR[6]; // rv 0 + assign SAXIHP1ARADDR_in[7] = (SAXIHP1ARADDR[7] !== 1'bz) && SAXIHP1ARADDR[7]; // rv 0 + assign SAXIHP1ARADDR_in[8] = (SAXIHP1ARADDR[8] !== 1'bz) && SAXIHP1ARADDR[8]; // rv 0 + assign SAXIHP1ARADDR_in[9] = (SAXIHP1ARADDR[9] !== 1'bz) && SAXIHP1ARADDR[9]; // rv 0 + assign SAXIHP1ARBURST_in[0] = (SAXIHP1ARBURST[0] !== 1'bz) && SAXIHP1ARBURST[0]; // rv 0 + assign SAXIHP1ARBURST_in[1] = (SAXIHP1ARBURST[1] !== 1'bz) && SAXIHP1ARBURST[1]; // rv 0 + assign SAXIHP1ARCACHE_in[0] = (SAXIHP1ARCACHE[0] !== 1'bz) && SAXIHP1ARCACHE[0]; // rv 0 + assign SAXIHP1ARCACHE_in[1] = (SAXIHP1ARCACHE[1] !== 1'bz) && SAXIHP1ARCACHE[1]; // rv 0 + assign SAXIHP1ARCACHE_in[2] = (SAXIHP1ARCACHE[2] !== 1'bz) && SAXIHP1ARCACHE[2]; // rv 0 + assign SAXIHP1ARCACHE_in[3] = (SAXIHP1ARCACHE[3] !== 1'bz) && SAXIHP1ARCACHE[3]; // rv 0 + assign SAXIHP1ARID_in[0] = (SAXIHP1ARID[0] !== 1'bz) && SAXIHP1ARID[0]; // rv 0 + assign SAXIHP1ARID_in[1] = (SAXIHP1ARID[1] !== 1'bz) && SAXIHP1ARID[1]; // rv 0 + assign SAXIHP1ARID_in[2] = (SAXIHP1ARID[2] !== 1'bz) && SAXIHP1ARID[2]; // rv 0 + assign SAXIHP1ARID_in[3] = (SAXIHP1ARID[3] !== 1'bz) && SAXIHP1ARID[3]; // rv 0 + assign SAXIHP1ARID_in[4] = (SAXIHP1ARID[4] !== 1'bz) && SAXIHP1ARID[4]; // rv 0 + assign SAXIHP1ARID_in[5] = (SAXIHP1ARID[5] !== 1'bz) && SAXIHP1ARID[5]; // rv 0 + assign SAXIHP1ARLEN_in[0] = (SAXIHP1ARLEN[0] !== 1'bz) && SAXIHP1ARLEN[0]; // rv 0 + assign SAXIHP1ARLEN_in[1] = (SAXIHP1ARLEN[1] !== 1'bz) && SAXIHP1ARLEN[1]; // rv 0 + assign SAXIHP1ARLEN_in[2] = (SAXIHP1ARLEN[2] !== 1'bz) && SAXIHP1ARLEN[2]; // rv 0 + assign SAXIHP1ARLEN_in[3] = (SAXIHP1ARLEN[3] !== 1'bz) && SAXIHP1ARLEN[3]; // rv 0 + assign SAXIHP1ARLOCK_in[0] = (SAXIHP1ARLOCK[0] !== 1'bz) && SAXIHP1ARLOCK[0]; // rv 0 + assign SAXIHP1ARLOCK_in[1] = (SAXIHP1ARLOCK[1] !== 1'bz) && SAXIHP1ARLOCK[1]; // rv 0 + assign SAXIHP1ARPROT_in[0] = (SAXIHP1ARPROT[0] !== 1'bz) && SAXIHP1ARPROT[0]; // rv 0 + assign SAXIHP1ARPROT_in[1] = (SAXIHP1ARPROT[1] !== 1'bz) && SAXIHP1ARPROT[1]; // rv 0 + assign SAXIHP1ARPROT_in[2] = (SAXIHP1ARPROT[2] !== 1'bz) && SAXIHP1ARPROT[2]; // rv 0 + assign SAXIHP1ARQOS_in[0] = (SAXIHP1ARQOS[0] !== 1'bz) && SAXIHP1ARQOS[0]; // rv 0 + assign SAXIHP1ARQOS_in[1] = (SAXIHP1ARQOS[1] !== 1'bz) && SAXIHP1ARQOS[1]; // rv 0 + assign SAXIHP1ARQOS_in[2] = (SAXIHP1ARQOS[2] !== 1'bz) && SAXIHP1ARQOS[2]; // rv 0 + assign SAXIHP1ARQOS_in[3] = (SAXIHP1ARQOS[3] !== 1'bz) && SAXIHP1ARQOS[3]; // rv 0 + assign SAXIHP1ARSIZE_in[0] = (SAXIHP1ARSIZE[0] !== 1'bz) && SAXIHP1ARSIZE[0]; // rv 0 + assign SAXIHP1ARSIZE_in[1] = (SAXIHP1ARSIZE[1] !== 1'bz) && SAXIHP1ARSIZE[1]; // rv 0 + assign SAXIHP1ARVALID_in = (SAXIHP1ARVALID !== 1'bz) && SAXIHP1ARVALID; // rv 0 + assign SAXIHP1AWADDR_in[0] = (SAXIHP1AWADDR[0] !== 1'bz) && SAXIHP1AWADDR[0]; // rv 0 + assign SAXIHP1AWADDR_in[10] = (SAXIHP1AWADDR[10] !== 1'bz) && SAXIHP1AWADDR[10]; // rv 0 + assign SAXIHP1AWADDR_in[11] = (SAXIHP1AWADDR[11] !== 1'bz) && SAXIHP1AWADDR[11]; // rv 0 + assign SAXIHP1AWADDR_in[12] = (SAXIHP1AWADDR[12] !== 1'bz) && SAXIHP1AWADDR[12]; // rv 0 + assign SAXIHP1AWADDR_in[13] = (SAXIHP1AWADDR[13] !== 1'bz) && SAXIHP1AWADDR[13]; // rv 0 + assign SAXIHP1AWADDR_in[14] = (SAXIHP1AWADDR[14] !== 1'bz) && SAXIHP1AWADDR[14]; // rv 0 + assign SAXIHP1AWADDR_in[15] = (SAXIHP1AWADDR[15] !== 1'bz) && SAXIHP1AWADDR[15]; // rv 0 + assign SAXIHP1AWADDR_in[16] = (SAXIHP1AWADDR[16] !== 1'bz) && SAXIHP1AWADDR[16]; // rv 0 + assign SAXIHP1AWADDR_in[17] = (SAXIHP1AWADDR[17] !== 1'bz) && SAXIHP1AWADDR[17]; // rv 0 + assign SAXIHP1AWADDR_in[18] = (SAXIHP1AWADDR[18] !== 1'bz) && SAXIHP1AWADDR[18]; // rv 0 + assign SAXIHP1AWADDR_in[19] = (SAXIHP1AWADDR[19] !== 1'bz) && SAXIHP1AWADDR[19]; // rv 0 + assign SAXIHP1AWADDR_in[1] = (SAXIHP1AWADDR[1] !== 1'bz) && SAXIHP1AWADDR[1]; // rv 0 + assign SAXIHP1AWADDR_in[20] = (SAXIHP1AWADDR[20] !== 1'bz) && SAXIHP1AWADDR[20]; // rv 0 + assign SAXIHP1AWADDR_in[21] = (SAXIHP1AWADDR[21] !== 1'bz) && SAXIHP1AWADDR[21]; // rv 0 + assign SAXIHP1AWADDR_in[22] = (SAXIHP1AWADDR[22] !== 1'bz) && SAXIHP1AWADDR[22]; // rv 0 + assign SAXIHP1AWADDR_in[23] = (SAXIHP1AWADDR[23] !== 1'bz) && SAXIHP1AWADDR[23]; // rv 0 + assign SAXIHP1AWADDR_in[24] = (SAXIHP1AWADDR[24] !== 1'bz) && SAXIHP1AWADDR[24]; // rv 0 + assign SAXIHP1AWADDR_in[25] = (SAXIHP1AWADDR[25] !== 1'bz) && SAXIHP1AWADDR[25]; // rv 0 + assign SAXIHP1AWADDR_in[26] = (SAXIHP1AWADDR[26] !== 1'bz) && SAXIHP1AWADDR[26]; // rv 0 + assign SAXIHP1AWADDR_in[27] = (SAXIHP1AWADDR[27] !== 1'bz) && SAXIHP1AWADDR[27]; // rv 0 + assign SAXIHP1AWADDR_in[28] = (SAXIHP1AWADDR[28] !== 1'bz) && SAXIHP1AWADDR[28]; // rv 0 + assign SAXIHP1AWADDR_in[29] = (SAXIHP1AWADDR[29] !== 1'bz) && SAXIHP1AWADDR[29]; // rv 0 + assign SAXIHP1AWADDR_in[2] = (SAXIHP1AWADDR[2] !== 1'bz) && SAXIHP1AWADDR[2]; // rv 0 + assign SAXIHP1AWADDR_in[30] = (SAXIHP1AWADDR[30] !== 1'bz) && SAXIHP1AWADDR[30]; // rv 0 + assign SAXIHP1AWADDR_in[31] = (SAXIHP1AWADDR[31] !== 1'bz) && SAXIHP1AWADDR[31]; // rv 0 + assign SAXIHP1AWADDR_in[3] = (SAXIHP1AWADDR[3] !== 1'bz) && SAXIHP1AWADDR[3]; // rv 0 + assign SAXIHP1AWADDR_in[4] = (SAXIHP1AWADDR[4] !== 1'bz) && SAXIHP1AWADDR[4]; // rv 0 + assign SAXIHP1AWADDR_in[5] = (SAXIHP1AWADDR[5] !== 1'bz) && SAXIHP1AWADDR[5]; // rv 0 + assign SAXIHP1AWADDR_in[6] = (SAXIHP1AWADDR[6] !== 1'bz) && SAXIHP1AWADDR[6]; // rv 0 + assign SAXIHP1AWADDR_in[7] = (SAXIHP1AWADDR[7] !== 1'bz) && SAXIHP1AWADDR[7]; // rv 0 + assign SAXIHP1AWADDR_in[8] = (SAXIHP1AWADDR[8] !== 1'bz) && SAXIHP1AWADDR[8]; // rv 0 + assign SAXIHP1AWADDR_in[9] = (SAXIHP1AWADDR[9] !== 1'bz) && SAXIHP1AWADDR[9]; // rv 0 + assign SAXIHP1AWBURST_in[0] = (SAXIHP1AWBURST[0] !== 1'bz) && SAXIHP1AWBURST[0]; // rv 0 + assign SAXIHP1AWBURST_in[1] = (SAXIHP1AWBURST[1] !== 1'bz) && SAXIHP1AWBURST[1]; // rv 0 + assign SAXIHP1AWCACHE_in[0] = (SAXIHP1AWCACHE[0] !== 1'bz) && SAXIHP1AWCACHE[0]; // rv 0 + assign SAXIHP1AWCACHE_in[1] = (SAXIHP1AWCACHE[1] !== 1'bz) && SAXIHP1AWCACHE[1]; // rv 0 + assign SAXIHP1AWCACHE_in[2] = (SAXIHP1AWCACHE[2] !== 1'bz) && SAXIHP1AWCACHE[2]; // rv 0 + assign SAXIHP1AWCACHE_in[3] = (SAXIHP1AWCACHE[3] !== 1'bz) && SAXIHP1AWCACHE[3]; // rv 0 + assign SAXIHP1AWID_in[0] = (SAXIHP1AWID[0] !== 1'bz) && SAXIHP1AWID[0]; // rv 0 + assign SAXIHP1AWID_in[1] = (SAXIHP1AWID[1] !== 1'bz) && SAXIHP1AWID[1]; // rv 0 + assign SAXIHP1AWID_in[2] = (SAXIHP1AWID[2] !== 1'bz) && SAXIHP1AWID[2]; // rv 0 + assign SAXIHP1AWID_in[3] = (SAXIHP1AWID[3] !== 1'bz) && SAXIHP1AWID[3]; // rv 0 + assign SAXIHP1AWID_in[4] = (SAXIHP1AWID[4] !== 1'bz) && SAXIHP1AWID[4]; // rv 0 + assign SAXIHP1AWID_in[5] = (SAXIHP1AWID[5] !== 1'bz) && SAXIHP1AWID[5]; // rv 0 + assign SAXIHP1AWLEN_in[0] = (SAXIHP1AWLEN[0] !== 1'bz) && SAXIHP1AWLEN[0]; // rv 0 + assign SAXIHP1AWLEN_in[1] = (SAXIHP1AWLEN[1] !== 1'bz) && SAXIHP1AWLEN[1]; // rv 0 + assign SAXIHP1AWLEN_in[2] = (SAXIHP1AWLEN[2] !== 1'bz) && SAXIHP1AWLEN[2]; // rv 0 + assign SAXIHP1AWLEN_in[3] = (SAXIHP1AWLEN[3] !== 1'bz) && SAXIHP1AWLEN[3]; // rv 0 + assign SAXIHP1AWLOCK_in[0] = (SAXIHP1AWLOCK[0] !== 1'bz) && SAXIHP1AWLOCK[0]; // rv 0 + assign SAXIHP1AWLOCK_in[1] = (SAXIHP1AWLOCK[1] !== 1'bz) && SAXIHP1AWLOCK[1]; // rv 0 + assign SAXIHP1AWPROT_in[0] = (SAXIHP1AWPROT[0] !== 1'bz) && SAXIHP1AWPROT[0]; // rv 0 + assign SAXIHP1AWPROT_in[1] = (SAXIHP1AWPROT[1] !== 1'bz) && SAXIHP1AWPROT[1]; // rv 0 + assign SAXIHP1AWPROT_in[2] = (SAXIHP1AWPROT[2] !== 1'bz) && SAXIHP1AWPROT[2]; // rv 0 + assign SAXIHP1AWQOS_in[0] = (SAXIHP1AWQOS[0] !== 1'bz) && SAXIHP1AWQOS[0]; // rv 0 + assign SAXIHP1AWQOS_in[1] = (SAXIHP1AWQOS[1] !== 1'bz) && SAXIHP1AWQOS[1]; // rv 0 + assign SAXIHP1AWQOS_in[2] = (SAXIHP1AWQOS[2] !== 1'bz) && SAXIHP1AWQOS[2]; // rv 0 + assign SAXIHP1AWQOS_in[3] = (SAXIHP1AWQOS[3] !== 1'bz) && SAXIHP1AWQOS[3]; // rv 0 + assign SAXIHP1AWSIZE_in[0] = (SAXIHP1AWSIZE[0] !== 1'bz) && SAXIHP1AWSIZE[0]; // rv 0 + assign SAXIHP1AWSIZE_in[1] = (SAXIHP1AWSIZE[1] !== 1'bz) && SAXIHP1AWSIZE[1]; // rv 0 + assign SAXIHP1AWVALID_in = (SAXIHP1AWVALID !== 1'bz) && SAXIHP1AWVALID; // rv 0 + assign SAXIHP1BREADY_in = (SAXIHP1BREADY !== 1'bz) && SAXIHP1BREADY; // rv 0 + assign SAXIHP1RREADY_in = (SAXIHP1RREADY !== 1'bz) && SAXIHP1RREADY; // rv 0 + assign SAXIHP1WDATA_in[0] = (SAXIHP1WDATA[0] !== 1'bz) && SAXIHP1WDATA[0]; // rv 0 + assign SAXIHP1WDATA_in[10] = (SAXIHP1WDATA[10] !== 1'bz) && SAXIHP1WDATA[10]; // rv 0 + assign SAXIHP1WDATA_in[11] = (SAXIHP1WDATA[11] !== 1'bz) && SAXIHP1WDATA[11]; // rv 0 + assign SAXIHP1WDATA_in[12] = (SAXIHP1WDATA[12] !== 1'bz) && SAXIHP1WDATA[12]; // rv 0 + assign SAXIHP1WDATA_in[13] = (SAXIHP1WDATA[13] !== 1'bz) && SAXIHP1WDATA[13]; // rv 0 + assign SAXIHP1WDATA_in[14] = (SAXIHP1WDATA[14] !== 1'bz) && SAXIHP1WDATA[14]; // rv 0 + assign SAXIHP1WDATA_in[15] = (SAXIHP1WDATA[15] !== 1'bz) && SAXIHP1WDATA[15]; // rv 0 + assign SAXIHP1WDATA_in[16] = (SAXIHP1WDATA[16] !== 1'bz) && SAXIHP1WDATA[16]; // rv 0 + assign SAXIHP1WDATA_in[17] = (SAXIHP1WDATA[17] !== 1'bz) && SAXIHP1WDATA[17]; // rv 0 + assign SAXIHP1WDATA_in[18] = (SAXIHP1WDATA[18] !== 1'bz) && SAXIHP1WDATA[18]; // rv 0 + assign SAXIHP1WDATA_in[19] = (SAXIHP1WDATA[19] !== 1'bz) && SAXIHP1WDATA[19]; // rv 0 + assign SAXIHP1WDATA_in[1] = (SAXIHP1WDATA[1] !== 1'bz) && SAXIHP1WDATA[1]; // rv 0 + assign SAXIHP1WDATA_in[20] = (SAXIHP1WDATA[20] !== 1'bz) && SAXIHP1WDATA[20]; // rv 0 + assign SAXIHP1WDATA_in[21] = (SAXIHP1WDATA[21] !== 1'bz) && SAXIHP1WDATA[21]; // rv 0 + assign SAXIHP1WDATA_in[22] = (SAXIHP1WDATA[22] !== 1'bz) && SAXIHP1WDATA[22]; // rv 0 + assign SAXIHP1WDATA_in[23] = (SAXIHP1WDATA[23] !== 1'bz) && SAXIHP1WDATA[23]; // rv 0 + assign SAXIHP1WDATA_in[24] = (SAXIHP1WDATA[24] !== 1'bz) && SAXIHP1WDATA[24]; // rv 0 + assign SAXIHP1WDATA_in[25] = (SAXIHP1WDATA[25] !== 1'bz) && SAXIHP1WDATA[25]; // rv 0 + assign SAXIHP1WDATA_in[26] = (SAXIHP1WDATA[26] !== 1'bz) && SAXIHP1WDATA[26]; // rv 0 + assign SAXIHP1WDATA_in[27] = (SAXIHP1WDATA[27] !== 1'bz) && SAXIHP1WDATA[27]; // rv 0 + assign SAXIHP1WDATA_in[28] = (SAXIHP1WDATA[28] !== 1'bz) && SAXIHP1WDATA[28]; // rv 0 + assign SAXIHP1WDATA_in[29] = (SAXIHP1WDATA[29] !== 1'bz) && SAXIHP1WDATA[29]; // rv 0 + assign SAXIHP1WDATA_in[2] = (SAXIHP1WDATA[2] !== 1'bz) && SAXIHP1WDATA[2]; // rv 0 + assign SAXIHP1WDATA_in[30] = (SAXIHP1WDATA[30] !== 1'bz) && SAXIHP1WDATA[30]; // rv 0 + assign SAXIHP1WDATA_in[31] = (SAXIHP1WDATA[31] !== 1'bz) && SAXIHP1WDATA[31]; // rv 0 + assign SAXIHP1WDATA_in[32] = (SAXIHP1WDATA[32] !== 1'bz) && SAXIHP1WDATA[32]; // rv 0 + assign SAXIHP1WDATA_in[33] = (SAXIHP1WDATA[33] !== 1'bz) && SAXIHP1WDATA[33]; // rv 0 + assign SAXIHP1WDATA_in[34] = (SAXIHP1WDATA[34] !== 1'bz) && SAXIHP1WDATA[34]; // rv 0 + assign SAXIHP1WDATA_in[35] = (SAXIHP1WDATA[35] !== 1'bz) && SAXIHP1WDATA[35]; // rv 0 + assign SAXIHP1WDATA_in[36] = (SAXIHP1WDATA[36] !== 1'bz) && SAXIHP1WDATA[36]; // rv 0 + assign SAXIHP1WDATA_in[37] = (SAXIHP1WDATA[37] !== 1'bz) && SAXIHP1WDATA[37]; // rv 0 + assign SAXIHP1WDATA_in[38] = (SAXIHP1WDATA[38] !== 1'bz) && SAXIHP1WDATA[38]; // rv 0 + assign SAXIHP1WDATA_in[39] = (SAXIHP1WDATA[39] !== 1'bz) && SAXIHP1WDATA[39]; // rv 0 + assign SAXIHP1WDATA_in[3] = (SAXIHP1WDATA[3] !== 1'bz) && SAXIHP1WDATA[3]; // rv 0 + assign SAXIHP1WDATA_in[40] = (SAXIHP1WDATA[40] !== 1'bz) && SAXIHP1WDATA[40]; // rv 0 + assign SAXIHP1WDATA_in[41] = (SAXIHP1WDATA[41] !== 1'bz) && SAXIHP1WDATA[41]; // rv 0 + assign SAXIHP1WDATA_in[42] = (SAXIHP1WDATA[42] !== 1'bz) && SAXIHP1WDATA[42]; // rv 0 + assign SAXIHP1WDATA_in[43] = (SAXIHP1WDATA[43] !== 1'bz) && SAXIHP1WDATA[43]; // rv 0 + assign SAXIHP1WDATA_in[44] = (SAXIHP1WDATA[44] !== 1'bz) && SAXIHP1WDATA[44]; // rv 0 + assign SAXIHP1WDATA_in[45] = (SAXIHP1WDATA[45] !== 1'bz) && SAXIHP1WDATA[45]; // rv 0 + assign SAXIHP1WDATA_in[46] = (SAXIHP1WDATA[46] !== 1'bz) && SAXIHP1WDATA[46]; // rv 0 + assign SAXIHP1WDATA_in[47] = (SAXIHP1WDATA[47] !== 1'bz) && SAXIHP1WDATA[47]; // rv 0 + assign SAXIHP1WDATA_in[48] = (SAXIHP1WDATA[48] !== 1'bz) && SAXIHP1WDATA[48]; // rv 0 + assign SAXIHP1WDATA_in[49] = (SAXIHP1WDATA[49] !== 1'bz) && SAXIHP1WDATA[49]; // rv 0 + assign SAXIHP1WDATA_in[4] = (SAXIHP1WDATA[4] !== 1'bz) && SAXIHP1WDATA[4]; // rv 0 + assign SAXIHP1WDATA_in[50] = (SAXIHP1WDATA[50] !== 1'bz) && SAXIHP1WDATA[50]; // rv 0 + assign SAXIHP1WDATA_in[51] = (SAXIHP1WDATA[51] !== 1'bz) && SAXIHP1WDATA[51]; // rv 0 + assign SAXIHP1WDATA_in[52] = (SAXIHP1WDATA[52] !== 1'bz) && SAXIHP1WDATA[52]; // rv 0 + assign SAXIHP1WDATA_in[53] = (SAXIHP1WDATA[53] !== 1'bz) && SAXIHP1WDATA[53]; // rv 0 + assign SAXIHP1WDATA_in[54] = (SAXIHP1WDATA[54] !== 1'bz) && SAXIHP1WDATA[54]; // rv 0 + assign SAXIHP1WDATA_in[55] = (SAXIHP1WDATA[55] !== 1'bz) && SAXIHP1WDATA[55]; // rv 0 + assign SAXIHP1WDATA_in[56] = (SAXIHP1WDATA[56] !== 1'bz) && SAXIHP1WDATA[56]; // rv 0 + assign SAXIHP1WDATA_in[57] = (SAXIHP1WDATA[57] !== 1'bz) && SAXIHP1WDATA[57]; // rv 0 + assign SAXIHP1WDATA_in[58] = (SAXIHP1WDATA[58] !== 1'bz) && SAXIHP1WDATA[58]; // rv 0 + assign SAXIHP1WDATA_in[59] = (SAXIHP1WDATA[59] !== 1'bz) && SAXIHP1WDATA[59]; // rv 0 + assign SAXIHP1WDATA_in[5] = (SAXIHP1WDATA[5] !== 1'bz) && SAXIHP1WDATA[5]; // rv 0 + assign SAXIHP1WDATA_in[60] = (SAXIHP1WDATA[60] !== 1'bz) && SAXIHP1WDATA[60]; // rv 0 + assign SAXIHP1WDATA_in[61] = (SAXIHP1WDATA[61] !== 1'bz) && SAXIHP1WDATA[61]; // rv 0 + assign SAXIHP1WDATA_in[62] = (SAXIHP1WDATA[62] !== 1'bz) && SAXIHP1WDATA[62]; // rv 0 + assign SAXIHP1WDATA_in[63] = (SAXIHP1WDATA[63] !== 1'bz) && SAXIHP1WDATA[63]; // rv 0 + assign SAXIHP1WDATA_in[6] = (SAXIHP1WDATA[6] !== 1'bz) && SAXIHP1WDATA[6]; // rv 0 + assign SAXIHP1WDATA_in[7] = (SAXIHP1WDATA[7] !== 1'bz) && SAXIHP1WDATA[7]; // rv 0 + assign SAXIHP1WDATA_in[8] = (SAXIHP1WDATA[8] !== 1'bz) && SAXIHP1WDATA[8]; // rv 0 + assign SAXIHP1WDATA_in[9] = (SAXIHP1WDATA[9] !== 1'bz) && SAXIHP1WDATA[9]; // rv 0 + assign SAXIHP1WID_in[0] = (SAXIHP1WID[0] !== 1'bz) && SAXIHP1WID[0]; // rv 0 + assign SAXIHP1WID_in[1] = (SAXIHP1WID[1] !== 1'bz) && SAXIHP1WID[1]; // rv 0 + assign SAXIHP1WID_in[2] = (SAXIHP1WID[2] !== 1'bz) && SAXIHP1WID[2]; // rv 0 + assign SAXIHP1WID_in[3] = (SAXIHP1WID[3] !== 1'bz) && SAXIHP1WID[3]; // rv 0 + assign SAXIHP1WID_in[4] = (SAXIHP1WID[4] !== 1'bz) && SAXIHP1WID[4]; // rv 0 + assign SAXIHP1WID_in[5] = (SAXIHP1WID[5] !== 1'bz) && SAXIHP1WID[5]; // rv 0 + assign SAXIHP1WLAST_in = (SAXIHP1WLAST !== 1'bz) && SAXIHP1WLAST; // rv 0 + assign SAXIHP1WSTRB_in[0] = (SAXIHP1WSTRB[0] !== 1'bz) && SAXIHP1WSTRB[0]; // rv 0 + assign SAXIHP1WSTRB_in[1] = (SAXIHP1WSTRB[1] !== 1'bz) && SAXIHP1WSTRB[1]; // rv 0 + assign SAXIHP1WSTRB_in[2] = (SAXIHP1WSTRB[2] !== 1'bz) && SAXIHP1WSTRB[2]; // rv 0 + assign SAXIHP1WSTRB_in[3] = (SAXIHP1WSTRB[3] !== 1'bz) && SAXIHP1WSTRB[3]; // rv 0 + assign SAXIHP1WSTRB_in[4] = (SAXIHP1WSTRB[4] !== 1'bz) && SAXIHP1WSTRB[4]; // rv 0 + assign SAXIHP1WSTRB_in[5] = (SAXIHP1WSTRB[5] !== 1'bz) && SAXIHP1WSTRB[5]; // rv 0 + assign SAXIHP1WSTRB_in[6] = (SAXIHP1WSTRB[6] !== 1'bz) && SAXIHP1WSTRB[6]; // rv 0 + assign SAXIHP1WSTRB_in[7] = (SAXIHP1WSTRB[7] !== 1'bz) && SAXIHP1WSTRB[7]; // rv 0 + assign SAXIHP1WVALID_in = (SAXIHP1WVALID !== 1'bz) && SAXIHP1WVALID; // rv 0 + assign SAXIHP2ACLK_in = (SAXIHP2ACLK !== 1'bz) && SAXIHP2ACLK; // rv 0 + assign SAXIHP2ARADDR_in[0] = (SAXIHP2ARADDR[0] !== 1'bz) && SAXIHP2ARADDR[0]; // rv 0 + assign SAXIHP2ARADDR_in[10] = (SAXIHP2ARADDR[10] !== 1'bz) && SAXIHP2ARADDR[10]; // rv 0 + assign SAXIHP2ARADDR_in[11] = (SAXIHP2ARADDR[11] !== 1'bz) && SAXIHP2ARADDR[11]; // rv 0 + assign SAXIHP2ARADDR_in[12] = (SAXIHP2ARADDR[12] !== 1'bz) && SAXIHP2ARADDR[12]; // rv 0 + assign SAXIHP2ARADDR_in[13] = (SAXIHP2ARADDR[13] !== 1'bz) && SAXIHP2ARADDR[13]; // rv 0 + assign SAXIHP2ARADDR_in[14] = (SAXIHP2ARADDR[14] !== 1'bz) && SAXIHP2ARADDR[14]; // rv 0 + assign SAXIHP2ARADDR_in[15] = (SAXIHP2ARADDR[15] !== 1'bz) && SAXIHP2ARADDR[15]; // rv 0 + assign SAXIHP2ARADDR_in[16] = (SAXIHP2ARADDR[16] !== 1'bz) && SAXIHP2ARADDR[16]; // rv 0 + assign SAXIHP2ARADDR_in[17] = (SAXIHP2ARADDR[17] !== 1'bz) && SAXIHP2ARADDR[17]; // rv 0 + assign SAXIHP2ARADDR_in[18] = (SAXIHP2ARADDR[18] !== 1'bz) && SAXIHP2ARADDR[18]; // rv 0 + assign SAXIHP2ARADDR_in[19] = (SAXIHP2ARADDR[19] !== 1'bz) && SAXIHP2ARADDR[19]; // rv 0 + assign SAXIHP2ARADDR_in[1] = (SAXIHP2ARADDR[1] !== 1'bz) && SAXIHP2ARADDR[1]; // rv 0 + assign SAXIHP2ARADDR_in[20] = (SAXIHP2ARADDR[20] !== 1'bz) && SAXIHP2ARADDR[20]; // rv 0 + assign SAXIHP2ARADDR_in[21] = (SAXIHP2ARADDR[21] !== 1'bz) && SAXIHP2ARADDR[21]; // rv 0 + assign SAXIHP2ARADDR_in[22] = (SAXIHP2ARADDR[22] !== 1'bz) && SAXIHP2ARADDR[22]; // rv 0 + assign SAXIHP2ARADDR_in[23] = (SAXIHP2ARADDR[23] !== 1'bz) && SAXIHP2ARADDR[23]; // rv 0 + assign SAXIHP2ARADDR_in[24] = (SAXIHP2ARADDR[24] !== 1'bz) && SAXIHP2ARADDR[24]; // rv 0 + assign SAXIHP2ARADDR_in[25] = (SAXIHP2ARADDR[25] !== 1'bz) && SAXIHP2ARADDR[25]; // rv 0 + assign SAXIHP2ARADDR_in[26] = (SAXIHP2ARADDR[26] !== 1'bz) && SAXIHP2ARADDR[26]; // rv 0 + assign SAXIHP2ARADDR_in[27] = (SAXIHP2ARADDR[27] !== 1'bz) && SAXIHP2ARADDR[27]; // rv 0 + assign SAXIHP2ARADDR_in[28] = (SAXIHP2ARADDR[28] !== 1'bz) && SAXIHP2ARADDR[28]; // rv 0 + assign SAXIHP2ARADDR_in[29] = (SAXIHP2ARADDR[29] !== 1'bz) && SAXIHP2ARADDR[29]; // rv 0 + assign SAXIHP2ARADDR_in[2] = (SAXIHP2ARADDR[2] !== 1'bz) && SAXIHP2ARADDR[2]; // rv 0 + assign SAXIHP2ARADDR_in[30] = (SAXIHP2ARADDR[30] !== 1'bz) && SAXIHP2ARADDR[30]; // rv 0 + assign SAXIHP2ARADDR_in[31] = (SAXIHP2ARADDR[31] !== 1'bz) && SAXIHP2ARADDR[31]; // rv 0 + assign SAXIHP2ARADDR_in[3] = (SAXIHP2ARADDR[3] !== 1'bz) && SAXIHP2ARADDR[3]; // rv 0 + assign SAXIHP2ARADDR_in[4] = (SAXIHP2ARADDR[4] !== 1'bz) && SAXIHP2ARADDR[4]; // rv 0 + assign SAXIHP2ARADDR_in[5] = (SAXIHP2ARADDR[5] !== 1'bz) && SAXIHP2ARADDR[5]; // rv 0 + assign SAXIHP2ARADDR_in[6] = (SAXIHP2ARADDR[6] !== 1'bz) && SAXIHP2ARADDR[6]; // rv 0 + assign SAXIHP2ARADDR_in[7] = (SAXIHP2ARADDR[7] !== 1'bz) && SAXIHP2ARADDR[7]; // rv 0 + assign SAXIHP2ARADDR_in[8] = (SAXIHP2ARADDR[8] !== 1'bz) && SAXIHP2ARADDR[8]; // rv 0 + assign SAXIHP2ARADDR_in[9] = (SAXIHP2ARADDR[9] !== 1'bz) && SAXIHP2ARADDR[9]; // rv 0 + assign SAXIHP2ARBURST_in[0] = (SAXIHP2ARBURST[0] !== 1'bz) && SAXIHP2ARBURST[0]; // rv 0 + assign SAXIHP2ARBURST_in[1] = (SAXIHP2ARBURST[1] !== 1'bz) && SAXIHP2ARBURST[1]; // rv 0 + assign SAXIHP2ARCACHE_in[0] = (SAXIHP2ARCACHE[0] !== 1'bz) && SAXIHP2ARCACHE[0]; // rv 0 + assign SAXIHP2ARCACHE_in[1] = (SAXIHP2ARCACHE[1] !== 1'bz) && SAXIHP2ARCACHE[1]; // rv 0 + assign SAXIHP2ARCACHE_in[2] = (SAXIHP2ARCACHE[2] !== 1'bz) && SAXIHP2ARCACHE[2]; // rv 0 + assign SAXIHP2ARCACHE_in[3] = (SAXIHP2ARCACHE[3] !== 1'bz) && SAXIHP2ARCACHE[3]; // rv 0 + assign SAXIHP2ARID_in[0] = (SAXIHP2ARID[0] !== 1'bz) && SAXIHP2ARID[0]; // rv 0 + assign SAXIHP2ARID_in[1] = (SAXIHP2ARID[1] !== 1'bz) && SAXIHP2ARID[1]; // rv 0 + assign SAXIHP2ARID_in[2] = (SAXIHP2ARID[2] !== 1'bz) && SAXIHP2ARID[2]; // rv 0 + assign SAXIHP2ARID_in[3] = (SAXIHP2ARID[3] !== 1'bz) && SAXIHP2ARID[3]; // rv 0 + assign SAXIHP2ARID_in[4] = (SAXIHP2ARID[4] !== 1'bz) && SAXIHP2ARID[4]; // rv 0 + assign SAXIHP2ARID_in[5] = (SAXIHP2ARID[5] !== 1'bz) && SAXIHP2ARID[5]; // rv 0 + assign SAXIHP2ARLEN_in[0] = (SAXIHP2ARLEN[0] !== 1'bz) && SAXIHP2ARLEN[0]; // rv 0 + assign SAXIHP2ARLEN_in[1] = (SAXIHP2ARLEN[1] !== 1'bz) && SAXIHP2ARLEN[1]; // rv 0 + assign SAXIHP2ARLEN_in[2] = (SAXIHP2ARLEN[2] !== 1'bz) && SAXIHP2ARLEN[2]; // rv 0 + assign SAXIHP2ARLEN_in[3] = (SAXIHP2ARLEN[3] !== 1'bz) && SAXIHP2ARLEN[3]; // rv 0 + assign SAXIHP2ARLOCK_in[0] = (SAXIHP2ARLOCK[0] !== 1'bz) && SAXIHP2ARLOCK[0]; // rv 0 + assign SAXIHP2ARLOCK_in[1] = (SAXIHP2ARLOCK[1] !== 1'bz) && SAXIHP2ARLOCK[1]; // rv 0 + assign SAXIHP2ARPROT_in[0] = (SAXIHP2ARPROT[0] !== 1'bz) && SAXIHP2ARPROT[0]; // rv 0 + assign SAXIHP2ARPROT_in[1] = (SAXIHP2ARPROT[1] !== 1'bz) && SAXIHP2ARPROT[1]; // rv 0 + assign SAXIHP2ARPROT_in[2] = (SAXIHP2ARPROT[2] !== 1'bz) && SAXIHP2ARPROT[2]; // rv 0 + assign SAXIHP2ARQOS_in[0] = (SAXIHP2ARQOS[0] !== 1'bz) && SAXIHP2ARQOS[0]; // rv 0 + assign SAXIHP2ARQOS_in[1] = (SAXIHP2ARQOS[1] !== 1'bz) && SAXIHP2ARQOS[1]; // rv 0 + assign SAXIHP2ARQOS_in[2] = (SAXIHP2ARQOS[2] !== 1'bz) && SAXIHP2ARQOS[2]; // rv 0 + assign SAXIHP2ARQOS_in[3] = (SAXIHP2ARQOS[3] !== 1'bz) && SAXIHP2ARQOS[3]; // rv 0 + assign SAXIHP2ARSIZE_in[0] = (SAXIHP2ARSIZE[0] !== 1'bz) && SAXIHP2ARSIZE[0]; // rv 0 + assign SAXIHP2ARSIZE_in[1] = (SAXIHP2ARSIZE[1] !== 1'bz) && SAXIHP2ARSIZE[1]; // rv 0 + assign SAXIHP2ARVALID_in = (SAXIHP2ARVALID !== 1'bz) && SAXIHP2ARVALID; // rv 0 + assign SAXIHP2AWADDR_in[0] = (SAXIHP2AWADDR[0] !== 1'bz) && SAXIHP2AWADDR[0]; // rv 0 + assign SAXIHP2AWADDR_in[10] = (SAXIHP2AWADDR[10] !== 1'bz) && SAXIHP2AWADDR[10]; // rv 0 + assign SAXIHP2AWADDR_in[11] = (SAXIHP2AWADDR[11] !== 1'bz) && SAXIHP2AWADDR[11]; // rv 0 + assign SAXIHP2AWADDR_in[12] = (SAXIHP2AWADDR[12] !== 1'bz) && SAXIHP2AWADDR[12]; // rv 0 + assign SAXIHP2AWADDR_in[13] = (SAXIHP2AWADDR[13] !== 1'bz) && SAXIHP2AWADDR[13]; // rv 0 + assign SAXIHP2AWADDR_in[14] = (SAXIHP2AWADDR[14] !== 1'bz) && SAXIHP2AWADDR[14]; // rv 0 + assign SAXIHP2AWADDR_in[15] = (SAXIHP2AWADDR[15] !== 1'bz) && SAXIHP2AWADDR[15]; // rv 0 + assign SAXIHP2AWADDR_in[16] = (SAXIHP2AWADDR[16] !== 1'bz) && SAXIHP2AWADDR[16]; // rv 0 + assign SAXIHP2AWADDR_in[17] = (SAXIHP2AWADDR[17] !== 1'bz) && SAXIHP2AWADDR[17]; // rv 0 + assign SAXIHP2AWADDR_in[18] = (SAXIHP2AWADDR[18] !== 1'bz) && SAXIHP2AWADDR[18]; // rv 0 + assign SAXIHP2AWADDR_in[19] = (SAXIHP2AWADDR[19] !== 1'bz) && SAXIHP2AWADDR[19]; // rv 0 + assign SAXIHP2AWADDR_in[1] = (SAXIHP2AWADDR[1] !== 1'bz) && SAXIHP2AWADDR[1]; // rv 0 + assign SAXIHP2AWADDR_in[20] = (SAXIHP2AWADDR[20] !== 1'bz) && SAXIHP2AWADDR[20]; // rv 0 + assign SAXIHP2AWADDR_in[21] = (SAXIHP2AWADDR[21] !== 1'bz) && SAXIHP2AWADDR[21]; // rv 0 + assign SAXIHP2AWADDR_in[22] = (SAXIHP2AWADDR[22] !== 1'bz) && SAXIHP2AWADDR[22]; // rv 0 + assign SAXIHP2AWADDR_in[23] = (SAXIHP2AWADDR[23] !== 1'bz) && SAXIHP2AWADDR[23]; // rv 0 + assign SAXIHP2AWADDR_in[24] = (SAXIHP2AWADDR[24] !== 1'bz) && SAXIHP2AWADDR[24]; // rv 0 + assign SAXIHP2AWADDR_in[25] = (SAXIHP2AWADDR[25] !== 1'bz) && SAXIHP2AWADDR[25]; // rv 0 + assign SAXIHP2AWADDR_in[26] = (SAXIHP2AWADDR[26] !== 1'bz) && SAXIHP2AWADDR[26]; // rv 0 + assign SAXIHP2AWADDR_in[27] = (SAXIHP2AWADDR[27] !== 1'bz) && SAXIHP2AWADDR[27]; // rv 0 + assign SAXIHP2AWADDR_in[28] = (SAXIHP2AWADDR[28] !== 1'bz) && SAXIHP2AWADDR[28]; // rv 0 + assign SAXIHP2AWADDR_in[29] = (SAXIHP2AWADDR[29] !== 1'bz) && SAXIHP2AWADDR[29]; // rv 0 + assign SAXIHP2AWADDR_in[2] = (SAXIHP2AWADDR[2] !== 1'bz) && SAXIHP2AWADDR[2]; // rv 0 + assign SAXIHP2AWADDR_in[30] = (SAXIHP2AWADDR[30] !== 1'bz) && SAXIHP2AWADDR[30]; // rv 0 + assign SAXIHP2AWADDR_in[31] = (SAXIHP2AWADDR[31] !== 1'bz) && SAXIHP2AWADDR[31]; // rv 0 + assign SAXIHP2AWADDR_in[3] = (SAXIHP2AWADDR[3] !== 1'bz) && SAXIHP2AWADDR[3]; // rv 0 + assign SAXIHP2AWADDR_in[4] = (SAXIHP2AWADDR[4] !== 1'bz) && SAXIHP2AWADDR[4]; // rv 0 + assign SAXIHP2AWADDR_in[5] = (SAXIHP2AWADDR[5] !== 1'bz) && SAXIHP2AWADDR[5]; // rv 0 + assign SAXIHP2AWADDR_in[6] = (SAXIHP2AWADDR[6] !== 1'bz) && SAXIHP2AWADDR[6]; // rv 0 + assign SAXIHP2AWADDR_in[7] = (SAXIHP2AWADDR[7] !== 1'bz) && SAXIHP2AWADDR[7]; // rv 0 + assign SAXIHP2AWADDR_in[8] = (SAXIHP2AWADDR[8] !== 1'bz) && SAXIHP2AWADDR[8]; // rv 0 + assign SAXIHP2AWADDR_in[9] = (SAXIHP2AWADDR[9] !== 1'bz) && SAXIHP2AWADDR[9]; // rv 0 + assign SAXIHP2AWBURST_in[0] = (SAXIHP2AWBURST[0] !== 1'bz) && SAXIHP2AWBURST[0]; // rv 0 + assign SAXIHP2AWBURST_in[1] = (SAXIHP2AWBURST[1] !== 1'bz) && SAXIHP2AWBURST[1]; // rv 0 + assign SAXIHP2AWCACHE_in[0] = (SAXIHP2AWCACHE[0] !== 1'bz) && SAXIHP2AWCACHE[0]; // rv 0 + assign SAXIHP2AWCACHE_in[1] = (SAXIHP2AWCACHE[1] !== 1'bz) && SAXIHP2AWCACHE[1]; // rv 0 + assign SAXIHP2AWCACHE_in[2] = (SAXIHP2AWCACHE[2] !== 1'bz) && SAXIHP2AWCACHE[2]; // rv 0 + assign SAXIHP2AWCACHE_in[3] = (SAXIHP2AWCACHE[3] !== 1'bz) && SAXIHP2AWCACHE[3]; // rv 0 + assign SAXIHP2AWID_in[0] = (SAXIHP2AWID[0] !== 1'bz) && SAXIHP2AWID[0]; // rv 0 + assign SAXIHP2AWID_in[1] = (SAXIHP2AWID[1] !== 1'bz) && SAXIHP2AWID[1]; // rv 0 + assign SAXIHP2AWID_in[2] = (SAXIHP2AWID[2] !== 1'bz) && SAXIHP2AWID[2]; // rv 0 + assign SAXIHP2AWID_in[3] = (SAXIHP2AWID[3] !== 1'bz) && SAXIHP2AWID[3]; // rv 0 + assign SAXIHP2AWID_in[4] = (SAXIHP2AWID[4] !== 1'bz) && SAXIHP2AWID[4]; // rv 0 + assign SAXIHP2AWID_in[5] = (SAXIHP2AWID[5] !== 1'bz) && SAXIHP2AWID[5]; // rv 0 + assign SAXIHP2AWLEN_in[0] = (SAXIHP2AWLEN[0] !== 1'bz) && SAXIHP2AWLEN[0]; // rv 0 + assign SAXIHP2AWLEN_in[1] = (SAXIHP2AWLEN[1] !== 1'bz) && SAXIHP2AWLEN[1]; // rv 0 + assign SAXIHP2AWLEN_in[2] = (SAXIHP2AWLEN[2] !== 1'bz) && SAXIHP2AWLEN[2]; // rv 0 + assign SAXIHP2AWLEN_in[3] = (SAXIHP2AWLEN[3] !== 1'bz) && SAXIHP2AWLEN[3]; // rv 0 + assign SAXIHP2AWLOCK_in[0] = (SAXIHP2AWLOCK[0] !== 1'bz) && SAXIHP2AWLOCK[0]; // rv 0 + assign SAXIHP2AWLOCK_in[1] = (SAXIHP2AWLOCK[1] !== 1'bz) && SAXIHP2AWLOCK[1]; // rv 0 + assign SAXIHP2AWPROT_in[0] = (SAXIHP2AWPROT[0] !== 1'bz) && SAXIHP2AWPROT[0]; // rv 0 + assign SAXIHP2AWPROT_in[1] = (SAXIHP2AWPROT[1] !== 1'bz) && SAXIHP2AWPROT[1]; // rv 0 + assign SAXIHP2AWPROT_in[2] = (SAXIHP2AWPROT[2] !== 1'bz) && SAXIHP2AWPROT[2]; // rv 0 + assign SAXIHP2AWQOS_in[0] = (SAXIHP2AWQOS[0] !== 1'bz) && SAXIHP2AWQOS[0]; // rv 0 + assign SAXIHP2AWQOS_in[1] = (SAXIHP2AWQOS[1] !== 1'bz) && SAXIHP2AWQOS[1]; // rv 0 + assign SAXIHP2AWQOS_in[2] = (SAXIHP2AWQOS[2] !== 1'bz) && SAXIHP2AWQOS[2]; // rv 0 + assign SAXIHP2AWQOS_in[3] = (SAXIHP2AWQOS[3] !== 1'bz) && SAXIHP2AWQOS[3]; // rv 0 + assign SAXIHP2AWSIZE_in[0] = (SAXIHP2AWSIZE[0] !== 1'bz) && SAXIHP2AWSIZE[0]; // rv 0 + assign SAXIHP2AWSIZE_in[1] = (SAXIHP2AWSIZE[1] !== 1'bz) && SAXIHP2AWSIZE[1]; // rv 0 + assign SAXIHP2AWVALID_in = (SAXIHP2AWVALID !== 1'bz) && SAXIHP2AWVALID; // rv 0 + assign SAXIHP2BREADY_in = (SAXIHP2BREADY !== 1'bz) && SAXIHP2BREADY; // rv 0 + assign SAXIHP2RREADY_in = (SAXIHP2RREADY !== 1'bz) && SAXIHP2RREADY; // rv 0 + assign SAXIHP2WDATA_in[0] = (SAXIHP2WDATA[0] !== 1'bz) && SAXIHP2WDATA[0]; // rv 0 + assign SAXIHP2WDATA_in[10] = (SAXIHP2WDATA[10] !== 1'bz) && SAXIHP2WDATA[10]; // rv 0 + assign SAXIHP2WDATA_in[11] = (SAXIHP2WDATA[11] !== 1'bz) && SAXIHP2WDATA[11]; // rv 0 + assign SAXIHP2WDATA_in[12] = (SAXIHP2WDATA[12] !== 1'bz) && SAXIHP2WDATA[12]; // rv 0 + assign SAXIHP2WDATA_in[13] = (SAXIHP2WDATA[13] !== 1'bz) && SAXIHP2WDATA[13]; // rv 0 + assign SAXIHP2WDATA_in[14] = (SAXIHP2WDATA[14] !== 1'bz) && SAXIHP2WDATA[14]; // rv 0 + assign SAXIHP2WDATA_in[15] = (SAXIHP2WDATA[15] !== 1'bz) && SAXIHP2WDATA[15]; // rv 0 + assign SAXIHP2WDATA_in[16] = (SAXIHP2WDATA[16] !== 1'bz) && SAXIHP2WDATA[16]; // rv 0 + assign SAXIHP2WDATA_in[17] = (SAXIHP2WDATA[17] !== 1'bz) && SAXIHP2WDATA[17]; // rv 0 + assign SAXIHP2WDATA_in[18] = (SAXIHP2WDATA[18] !== 1'bz) && SAXIHP2WDATA[18]; // rv 0 + assign SAXIHP2WDATA_in[19] = (SAXIHP2WDATA[19] !== 1'bz) && SAXIHP2WDATA[19]; // rv 0 + assign SAXIHP2WDATA_in[1] = (SAXIHP2WDATA[1] !== 1'bz) && SAXIHP2WDATA[1]; // rv 0 + assign SAXIHP2WDATA_in[20] = (SAXIHP2WDATA[20] !== 1'bz) && SAXIHP2WDATA[20]; // rv 0 + assign SAXIHP2WDATA_in[21] = (SAXIHP2WDATA[21] !== 1'bz) && SAXIHP2WDATA[21]; // rv 0 + assign SAXIHP2WDATA_in[22] = (SAXIHP2WDATA[22] !== 1'bz) && SAXIHP2WDATA[22]; // rv 0 + assign SAXIHP2WDATA_in[23] = (SAXIHP2WDATA[23] !== 1'bz) && SAXIHP2WDATA[23]; // rv 0 + assign SAXIHP2WDATA_in[24] = (SAXIHP2WDATA[24] !== 1'bz) && SAXIHP2WDATA[24]; // rv 0 + assign SAXIHP2WDATA_in[25] = (SAXIHP2WDATA[25] !== 1'bz) && SAXIHP2WDATA[25]; // rv 0 + assign SAXIHP2WDATA_in[26] = (SAXIHP2WDATA[26] !== 1'bz) && SAXIHP2WDATA[26]; // rv 0 + assign SAXIHP2WDATA_in[27] = (SAXIHP2WDATA[27] !== 1'bz) && SAXIHP2WDATA[27]; // rv 0 + assign SAXIHP2WDATA_in[28] = (SAXIHP2WDATA[28] !== 1'bz) && SAXIHP2WDATA[28]; // rv 0 + assign SAXIHP2WDATA_in[29] = (SAXIHP2WDATA[29] !== 1'bz) && SAXIHP2WDATA[29]; // rv 0 + assign SAXIHP2WDATA_in[2] = (SAXIHP2WDATA[2] !== 1'bz) && SAXIHP2WDATA[2]; // rv 0 + assign SAXIHP2WDATA_in[30] = (SAXIHP2WDATA[30] !== 1'bz) && SAXIHP2WDATA[30]; // rv 0 + assign SAXIHP2WDATA_in[31] = (SAXIHP2WDATA[31] !== 1'bz) && SAXIHP2WDATA[31]; // rv 0 + assign SAXIHP2WDATA_in[32] = (SAXIHP2WDATA[32] !== 1'bz) && SAXIHP2WDATA[32]; // rv 0 + assign SAXIHP2WDATA_in[33] = (SAXIHP2WDATA[33] !== 1'bz) && SAXIHP2WDATA[33]; // rv 0 + assign SAXIHP2WDATA_in[34] = (SAXIHP2WDATA[34] !== 1'bz) && SAXIHP2WDATA[34]; // rv 0 + assign SAXIHP2WDATA_in[35] = (SAXIHP2WDATA[35] !== 1'bz) && SAXIHP2WDATA[35]; // rv 0 + assign SAXIHP2WDATA_in[36] = (SAXIHP2WDATA[36] !== 1'bz) && SAXIHP2WDATA[36]; // rv 0 + assign SAXIHP2WDATA_in[37] = (SAXIHP2WDATA[37] !== 1'bz) && SAXIHP2WDATA[37]; // rv 0 + assign SAXIHP2WDATA_in[38] = (SAXIHP2WDATA[38] !== 1'bz) && SAXIHP2WDATA[38]; // rv 0 + assign SAXIHP2WDATA_in[39] = (SAXIHP2WDATA[39] !== 1'bz) && SAXIHP2WDATA[39]; // rv 0 + assign SAXIHP2WDATA_in[3] = (SAXIHP2WDATA[3] !== 1'bz) && SAXIHP2WDATA[3]; // rv 0 + assign SAXIHP2WDATA_in[40] = (SAXIHP2WDATA[40] !== 1'bz) && SAXIHP2WDATA[40]; // rv 0 + assign SAXIHP2WDATA_in[41] = (SAXIHP2WDATA[41] !== 1'bz) && SAXIHP2WDATA[41]; // rv 0 + assign SAXIHP2WDATA_in[42] = (SAXIHP2WDATA[42] !== 1'bz) && SAXIHP2WDATA[42]; // rv 0 + assign SAXIHP2WDATA_in[43] = (SAXIHP2WDATA[43] !== 1'bz) && SAXIHP2WDATA[43]; // rv 0 + assign SAXIHP2WDATA_in[44] = (SAXIHP2WDATA[44] !== 1'bz) && SAXIHP2WDATA[44]; // rv 0 + assign SAXIHP2WDATA_in[45] = (SAXIHP2WDATA[45] !== 1'bz) && SAXIHP2WDATA[45]; // rv 0 + assign SAXIHP2WDATA_in[46] = (SAXIHP2WDATA[46] !== 1'bz) && SAXIHP2WDATA[46]; // rv 0 + assign SAXIHP2WDATA_in[47] = (SAXIHP2WDATA[47] !== 1'bz) && SAXIHP2WDATA[47]; // rv 0 + assign SAXIHP2WDATA_in[48] = (SAXIHP2WDATA[48] !== 1'bz) && SAXIHP2WDATA[48]; // rv 0 + assign SAXIHP2WDATA_in[49] = (SAXIHP2WDATA[49] !== 1'bz) && SAXIHP2WDATA[49]; // rv 0 + assign SAXIHP2WDATA_in[4] = (SAXIHP2WDATA[4] !== 1'bz) && SAXIHP2WDATA[4]; // rv 0 + assign SAXIHP2WDATA_in[50] = (SAXIHP2WDATA[50] !== 1'bz) && SAXIHP2WDATA[50]; // rv 0 + assign SAXIHP2WDATA_in[51] = (SAXIHP2WDATA[51] !== 1'bz) && SAXIHP2WDATA[51]; // rv 0 + assign SAXIHP2WDATA_in[52] = (SAXIHP2WDATA[52] !== 1'bz) && SAXIHP2WDATA[52]; // rv 0 + assign SAXIHP2WDATA_in[53] = (SAXIHP2WDATA[53] !== 1'bz) && SAXIHP2WDATA[53]; // rv 0 + assign SAXIHP2WDATA_in[54] = (SAXIHP2WDATA[54] !== 1'bz) && SAXIHP2WDATA[54]; // rv 0 + assign SAXIHP2WDATA_in[55] = (SAXIHP2WDATA[55] !== 1'bz) && SAXIHP2WDATA[55]; // rv 0 + assign SAXIHP2WDATA_in[56] = (SAXIHP2WDATA[56] !== 1'bz) && SAXIHP2WDATA[56]; // rv 0 + assign SAXIHP2WDATA_in[57] = (SAXIHP2WDATA[57] !== 1'bz) && SAXIHP2WDATA[57]; // rv 0 + assign SAXIHP2WDATA_in[58] = (SAXIHP2WDATA[58] !== 1'bz) && SAXIHP2WDATA[58]; // rv 0 + assign SAXIHP2WDATA_in[59] = (SAXIHP2WDATA[59] !== 1'bz) && SAXIHP2WDATA[59]; // rv 0 + assign SAXIHP2WDATA_in[5] = (SAXIHP2WDATA[5] !== 1'bz) && SAXIHP2WDATA[5]; // rv 0 + assign SAXIHP2WDATA_in[60] = (SAXIHP2WDATA[60] !== 1'bz) && SAXIHP2WDATA[60]; // rv 0 + assign SAXIHP2WDATA_in[61] = (SAXIHP2WDATA[61] !== 1'bz) && SAXIHP2WDATA[61]; // rv 0 + assign SAXIHP2WDATA_in[62] = (SAXIHP2WDATA[62] !== 1'bz) && SAXIHP2WDATA[62]; // rv 0 + assign SAXIHP2WDATA_in[63] = (SAXIHP2WDATA[63] !== 1'bz) && SAXIHP2WDATA[63]; // rv 0 + assign SAXIHP2WDATA_in[6] = (SAXIHP2WDATA[6] !== 1'bz) && SAXIHP2WDATA[6]; // rv 0 + assign SAXIHP2WDATA_in[7] = (SAXIHP2WDATA[7] !== 1'bz) && SAXIHP2WDATA[7]; // rv 0 + assign SAXIHP2WDATA_in[8] = (SAXIHP2WDATA[8] !== 1'bz) && SAXIHP2WDATA[8]; // rv 0 + assign SAXIHP2WDATA_in[9] = (SAXIHP2WDATA[9] !== 1'bz) && SAXIHP2WDATA[9]; // rv 0 + assign SAXIHP2WID_in[0] = (SAXIHP2WID[0] !== 1'bz) && SAXIHP2WID[0]; // rv 0 + assign SAXIHP2WID_in[1] = (SAXIHP2WID[1] !== 1'bz) && SAXIHP2WID[1]; // rv 0 + assign SAXIHP2WID_in[2] = (SAXIHP2WID[2] !== 1'bz) && SAXIHP2WID[2]; // rv 0 + assign SAXIHP2WID_in[3] = (SAXIHP2WID[3] !== 1'bz) && SAXIHP2WID[3]; // rv 0 + assign SAXIHP2WID_in[4] = (SAXIHP2WID[4] !== 1'bz) && SAXIHP2WID[4]; // rv 0 + assign SAXIHP2WID_in[5] = (SAXIHP2WID[5] !== 1'bz) && SAXIHP2WID[5]; // rv 0 + assign SAXIHP2WLAST_in = (SAXIHP2WLAST !== 1'bz) && SAXIHP2WLAST; // rv 0 + assign SAXIHP2WSTRB_in[0] = (SAXIHP2WSTRB[0] !== 1'bz) && SAXIHP2WSTRB[0]; // rv 0 + assign SAXIHP2WSTRB_in[1] = (SAXIHP2WSTRB[1] !== 1'bz) && SAXIHP2WSTRB[1]; // rv 0 + assign SAXIHP2WSTRB_in[2] = (SAXIHP2WSTRB[2] !== 1'bz) && SAXIHP2WSTRB[2]; // rv 0 + assign SAXIHP2WSTRB_in[3] = (SAXIHP2WSTRB[3] !== 1'bz) && SAXIHP2WSTRB[3]; // rv 0 + assign SAXIHP2WSTRB_in[4] = (SAXIHP2WSTRB[4] !== 1'bz) && SAXIHP2WSTRB[4]; // rv 0 + assign SAXIHP2WSTRB_in[5] = (SAXIHP2WSTRB[5] !== 1'bz) && SAXIHP2WSTRB[5]; // rv 0 + assign SAXIHP2WSTRB_in[6] = (SAXIHP2WSTRB[6] !== 1'bz) && SAXIHP2WSTRB[6]; // rv 0 + assign SAXIHP2WSTRB_in[7] = (SAXIHP2WSTRB[7] !== 1'bz) && SAXIHP2WSTRB[7]; // rv 0 + assign SAXIHP2WVALID_in = (SAXIHP2WVALID !== 1'bz) && SAXIHP2WVALID; // rv 0 + assign SAXIHP3ACLK_in = (SAXIHP3ACLK !== 1'bz) && SAXIHP3ACLK; // rv 0 + assign SAXIHP3ARADDR_in[0] = (SAXIHP3ARADDR[0] !== 1'bz) && SAXIHP3ARADDR[0]; // rv 0 + assign SAXIHP3ARADDR_in[10] = (SAXIHP3ARADDR[10] !== 1'bz) && SAXIHP3ARADDR[10]; // rv 0 + assign SAXIHP3ARADDR_in[11] = (SAXIHP3ARADDR[11] !== 1'bz) && SAXIHP3ARADDR[11]; // rv 0 + assign SAXIHP3ARADDR_in[12] = (SAXIHP3ARADDR[12] !== 1'bz) && SAXIHP3ARADDR[12]; // rv 0 + assign SAXIHP3ARADDR_in[13] = (SAXIHP3ARADDR[13] !== 1'bz) && SAXIHP3ARADDR[13]; // rv 0 + assign SAXIHP3ARADDR_in[14] = (SAXIHP3ARADDR[14] !== 1'bz) && SAXIHP3ARADDR[14]; // rv 0 + assign SAXIHP3ARADDR_in[15] = (SAXIHP3ARADDR[15] !== 1'bz) && SAXIHP3ARADDR[15]; // rv 0 + assign SAXIHP3ARADDR_in[16] = (SAXIHP3ARADDR[16] !== 1'bz) && SAXIHP3ARADDR[16]; // rv 0 + assign SAXIHP3ARADDR_in[17] = (SAXIHP3ARADDR[17] !== 1'bz) && SAXIHP3ARADDR[17]; // rv 0 + assign SAXIHP3ARADDR_in[18] = (SAXIHP3ARADDR[18] !== 1'bz) && SAXIHP3ARADDR[18]; // rv 0 + assign SAXIHP3ARADDR_in[19] = (SAXIHP3ARADDR[19] !== 1'bz) && SAXIHP3ARADDR[19]; // rv 0 + assign SAXIHP3ARADDR_in[1] = (SAXIHP3ARADDR[1] !== 1'bz) && SAXIHP3ARADDR[1]; // rv 0 + assign SAXIHP3ARADDR_in[20] = (SAXIHP3ARADDR[20] !== 1'bz) && SAXIHP3ARADDR[20]; // rv 0 + assign SAXIHP3ARADDR_in[21] = (SAXIHP3ARADDR[21] !== 1'bz) && SAXIHP3ARADDR[21]; // rv 0 + assign SAXIHP3ARADDR_in[22] = (SAXIHP3ARADDR[22] !== 1'bz) && SAXIHP3ARADDR[22]; // rv 0 + assign SAXIHP3ARADDR_in[23] = (SAXIHP3ARADDR[23] !== 1'bz) && SAXIHP3ARADDR[23]; // rv 0 + assign SAXIHP3ARADDR_in[24] = (SAXIHP3ARADDR[24] !== 1'bz) && SAXIHP3ARADDR[24]; // rv 0 + assign SAXIHP3ARADDR_in[25] = (SAXIHP3ARADDR[25] !== 1'bz) && SAXIHP3ARADDR[25]; // rv 0 + assign SAXIHP3ARADDR_in[26] = (SAXIHP3ARADDR[26] !== 1'bz) && SAXIHP3ARADDR[26]; // rv 0 + assign SAXIHP3ARADDR_in[27] = (SAXIHP3ARADDR[27] !== 1'bz) && SAXIHP3ARADDR[27]; // rv 0 + assign SAXIHP3ARADDR_in[28] = (SAXIHP3ARADDR[28] !== 1'bz) && SAXIHP3ARADDR[28]; // rv 0 + assign SAXIHP3ARADDR_in[29] = (SAXIHP3ARADDR[29] !== 1'bz) && SAXIHP3ARADDR[29]; // rv 0 + assign SAXIHP3ARADDR_in[2] = (SAXIHP3ARADDR[2] !== 1'bz) && SAXIHP3ARADDR[2]; // rv 0 + assign SAXIHP3ARADDR_in[30] = (SAXIHP3ARADDR[30] !== 1'bz) && SAXIHP3ARADDR[30]; // rv 0 + assign SAXIHP3ARADDR_in[31] = (SAXIHP3ARADDR[31] !== 1'bz) && SAXIHP3ARADDR[31]; // rv 0 + assign SAXIHP3ARADDR_in[3] = (SAXIHP3ARADDR[3] !== 1'bz) && SAXIHP3ARADDR[3]; // rv 0 + assign SAXIHP3ARADDR_in[4] = (SAXIHP3ARADDR[4] !== 1'bz) && SAXIHP3ARADDR[4]; // rv 0 + assign SAXIHP3ARADDR_in[5] = (SAXIHP3ARADDR[5] !== 1'bz) && SAXIHP3ARADDR[5]; // rv 0 + assign SAXIHP3ARADDR_in[6] = (SAXIHP3ARADDR[6] !== 1'bz) && SAXIHP3ARADDR[6]; // rv 0 + assign SAXIHP3ARADDR_in[7] = (SAXIHP3ARADDR[7] !== 1'bz) && SAXIHP3ARADDR[7]; // rv 0 + assign SAXIHP3ARADDR_in[8] = (SAXIHP3ARADDR[8] !== 1'bz) && SAXIHP3ARADDR[8]; // rv 0 + assign SAXIHP3ARADDR_in[9] = (SAXIHP3ARADDR[9] !== 1'bz) && SAXIHP3ARADDR[9]; // rv 0 + assign SAXIHP3ARBURST_in[0] = (SAXIHP3ARBURST[0] !== 1'bz) && SAXIHP3ARBURST[0]; // rv 0 + assign SAXIHP3ARBURST_in[1] = (SAXIHP3ARBURST[1] !== 1'bz) && SAXIHP3ARBURST[1]; // rv 0 + assign SAXIHP3ARCACHE_in[0] = (SAXIHP3ARCACHE[0] !== 1'bz) && SAXIHP3ARCACHE[0]; // rv 0 + assign SAXIHP3ARCACHE_in[1] = (SAXIHP3ARCACHE[1] !== 1'bz) && SAXIHP3ARCACHE[1]; // rv 0 + assign SAXIHP3ARCACHE_in[2] = (SAXIHP3ARCACHE[2] !== 1'bz) && SAXIHP3ARCACHE[2]; // rv 0 + assign SAXIHP3ARCACHE_in[3] = (SAXIHP3ARCACHE[3] !== 1'bz) && SAXIHP3ARCACHE[3]; // rv 0 + assign SAXIHP3ARID_in[0] = (SAXIHP3ARID[0] !== 1'bz) && SAXIHP3ARID[0]; // rv 0 + assign SAXIHP3ARID_in[1] = (SAXIHP3ARID[1] !== 1'bz) && SAXIHP3ARID[1]; // rv 0 + assign SAXIHP3ARID_in[2] = (SAXIHP3ARID[2] !== 1'bz) && SAXIHP3ARID[2]; // rv 0 + assign SAXIHP3ARID_in[3] = (SAXIHP3ARID[3] !== 1'bz) && SAXIHP3ARID[3]; // rv 0 + assign SAXIHP3ARID_in[4] = (SAXIHP3ARID[4] !== 1'bz) && SAXIHP3ARID[4]; // rv 0 + assign SAXIHP3ARID_in[5] = (SAXIHP3ARID[5] !== 1'bz) && SAXIHP3ARID[5]; // rv 0 + assign SAXIHP3ARLEN_in[0] = (SAXIHP3ARLEN[0] !== 1'bz) && SAXIHP3ARLEN[0]; // rv 0 + assign SAXIHP3ARLEN_in[1] = (SAXIHP3ARLEN[1] !== 1'bz) && SAXIHP3ARLEN[1]; // rv 0 + assign SAXIHP3ARLEN_in[2] = (SAXIHP3ARLEN[2] !== 1'bz) && SAXIHP3ARLEN[2]; // rv 0 + assign SAXIHP3ARLEN_in[3] = (SAXIHP3ARLEN[3] !== 1'bz) && SAXIHP3ARLEN[3]; // rv 0 + assign SAXIHP3ARLOCK_in[0] = (SAXIHP3ARLOCK[0] !== 1'bz) && SAXIHP3ARLOCK[0]; // rv 0 + assign SAXIHP3ARLOCK_in[1] = (SAXIHP3ARLOCK[1] !== 1'bz) && SAXIHP3ARLOCK[1]; // rv 0 + assign SAXIHP3ARPROT_in[0] = (SAXIHP3ARPROT[0] !== 1'bz) && SAXIHP3ARPROT[0]; // rv 0 + assign SAXIHP3ARPROT_in[1] = (SAXIHP3ARPROT[1] !== 1'bz) && SAXIHP3ARPROT[1]; // rv 0 + assign SAXIHP3ARPROT_in[2] = (SAXIHP3ARPROT[2] !== 1'bz) && SAXIHP3ARPROT[2]; // rv 0 + assign SAXIHP3ARQOS_in[0] = (SAXIHP3ARQOS[0] !== 1'bz) && SAXIHP3ARQOS[0]; // rv 0 + assign SAXIHP3ARQOS_in[1] = (SAXIHP3ARQOS[1] !== 1'bz) && SAXIHP3ARQOS[1]; // rv 0 + assign SAXIHP3ARQOS_in[2] = (SAXIHP3ARQOS[2] !== 1'bz) && SAXIHP3ARQOS[2]; // rv 0 + assign SAXIHP3ARQOS_in[3] = (SAXIHP3ARQOS[3] !== 1'bz) && SAXIHP3ARQOS[3]; // rv 0 + assign SAXIHP3ARSIZE_in[0] = (SAXIHP3ARSIZE[0] !== 1'bz) && SAXIHP3ARSIZE[0]; // rv 0 + assign SAXIHP3ARSIZE_in[1] = (SAXIHP3ARSIZE[1] !== 1'bz) && SAXIHP3ARSIZE[1]; // rv 0 + assign SAXIHP3ARVALID_in = (SAXIHP3ARVALID !== 1'bz) && SAXIHP3ARVALID; // rv 0 + assign SAXIHP3AWADDR_in[0] = (SAXIHP3AWADDR[0] !== 1'bz) && SAXIHP3AWADDR[0]; // rv 0 + assign SAXIHP3AWADDR_in[10] = (SAXIHP3AWADDR[10] !== 1'bz) && SAXIHP3AWADDR[10]; // rv 0 + assign SAXIHP3AWADDR_in[11] = (SAXIHP3AWADDR[11] !== 1'bz) && SAXIHP3AWADDR[11]; // rv 0 + assign SAXIHP3AWADDR_in[12] = (SAXIHP3AWADDR[12] !== 1'bz) && SAXIHP3AWADDR[12]; // rv 0 + assign SAXIHP3AWADDR_in[13] = (SAXIHP3AWADDR[13] !== 1'bz) && SAXIHP3AWADDR[13]; // rv 0 + assign SAXIHP3AWADDR_in[14] = (SAXIHP3AWADDR[14] !== 1'bz) && SAXIHP3AWADDR[14]; // rv 0 + assign SAXIHP3AWADDR_in[15] = (SAXIHP3AWADDR[15] !== 1'bz) && SAXIHP3AWADDR[15]; // rv 0 + assign SAXIHP3AWADDR_in[16] = (SAXIHP3AWADDR[16] !== 1'bz) && SAXIHP3AWADDR[16]; // rv 0 + assign SAXIHP3AWADDR_in[17] = (SAXIHP3AWADDR[17] !== 1'bz) && SAXIHP3AWADDR[17]; // rv 0 + assign SAXIHP3AWADDR_in[18] = (SAXIHP3AWADDR[18] !== 1'bz) && SAXIHP3AWADDR[18]; // rv 0 + assign SAXIHP3AWADDR_in[19] = (SAXIHP3AWADDR[19] !== 1'bz) && SAXIHP3AWADDR[19]; // rv 0 + assign SAXIHP3AWADDR_in[1] = (SAXIHP3AWADDR[1] !== 1'bz) && SAXIHP3AWADDR[1]; // rv 0 + assign SAXIHP3AWADDR_in[20] = (SAXIHP3AWADDR[20] !== 1'bz) && SAXIHP3AWADDR[20]; // rv 0 + assign SAXIHP3AWADDR_in[21] = (SAXIHP3AWADDR[21] !== 1'bz) && SAXIHP3AWADDR[21]; // rv 0 + assign SAXIHP3AWADDR_in[22] = (SAXIHP3AWADDR[22] !== 1'bz) && SAXIHP3AWADDR[22]; // rv 0 + assign SAXIHP3AWADDR_in[23] = (SAXIHP3AWADDR[23] !== 1'bz) && SAXIHP3AWADDR[23]; // rv 0 + assign SAXIHP3AWADDR_in[24] = (SAXIHP3AWADDR[24] !== 1'bz) && SAXIHP3AWADDR[24]; // rv 0 + assign SAXIHP3AWADDR_in[25] = (SAXIHP3AWADDR[25] !== 1'bz) && SAXIHP3AWADDR[25]; // rv 0 + assign SAXIHP3AWADDR_in[26] = (SAXIHP3AWADDR[26] !== 1'bz) && SAXIHP3AWADDR[26]; // rv 0 + assign SAXIHP3AWADDR_in[27] = (SAXIHP3AWADDR[27] !== 1'bz) && SAXIHP3AWADDR[27]; // rv 0 + assign SAXIHP3AWADDR_in[28] = (SAXIHP3AWADDR[28] !== 1'bz) && SAXIHP3AWADDR[28]; // rv 0 + assign SAXIHP3AWADDR_in[29] = (SAXIHP3AWADDR[29] !== 1'bz) && SAXIHP3AWADDR[29]; // rv 0 + assign SAXIHP3AWADDR_in[2] = (SAXIHP3AWADDR[2] !== 1'bz) && SAXIHP3AWADDR[2]; // rv 0 + assign SAXIHP3AWADDR_in[30] = (SAXIHP3AWADDR[30] !== 1'bz) && SAXIHP3AWADDR[30]; // rv 0 + assign SAXIHP3AWADDR_in[31] = (SAXIHP3AWADDR[31] !== 1'bz) && SAXIHP3AWADDR[31]; // rv 0 + assign SAXIHP3AWADDR_in[3] = (SAXIHP3AWADDR[3] !== 1'bz) && SAXIHP3AWADDR[3]; // rv 0 + assign SAXIHP3AWADDR_in[4] = (SAXIHP3AWADDR[4] !== 1'bz) && SAXIHP3AWADDR[4]; // rv 0 + assign SAXIHP3AWADDR_in[5] = (SAXIHP3AWADDR[5] !== 1'bz) && SAXIHP3AWADDR[5]; // rv 0 + assign SAXIHP3AWADDR_in[6] = (SAXIHP3AWADDR[6] !== 1'bz) && SAXIHP3AWADDR[6]; // rv 0 + assign SAXIHP3AWADDR_in[7] = (SAXIHP3AWADDR[7] !== 1'bz) && SAXIHP3AWADDR[7]; // rv 0 + assign SAXIHP3AWADDR_in[8] = (SAXIHP3AWADDR[8] !== 1'bz) && SAXIHP3AWADDR[8]; // rv 0 + assign SAXIHP3AWADDR_in[9] = (SAXIHP3AWADDR[9] !== 1'bz) && SAXIHP3AWADDR[9]; // rv 0 + assign SAXIHP3AWBURST_in[0] = (SAXIHP3AWBURST[0] !== 1'bz) && SAXIHP3AWBURST[0]; // rv 0 + assign SAXIHP3AWBURST_in[1] = (SAXIHP3AWBURST[1] !== 1'bz) && SAXIHP3AWBURST[1]; // rv 0 + assign SAXIHP3AWCACHE_in[0] = (SAXIHP3AWCACHE[0] !== 1'bz) && SAXIHP3AWCACHE[0]; // rv 0 + assign SAXIHP3AWCACHE_in[1] = (SAXIHP3AWCACHE[1] !== 1'bz) && SAXIHP3AWCACHE[1]; // rv 0 + assign SAXIHP3AWCACHE_in[2] = (SAXIHP3AWCACHE[2] !== 1'bz) && SAXIHP3AWCACHE[2]; // rv 0 + assign SAXIHP3AWCACHE_in[3] = (SAXIHP3AWCACHE[3] !== 1'bz) && SAXIHP3AWCACHE[3]; // rv 0 + assign SAXIHP3AWID_in[0] = (SAXIHP3AWID[0] !== 1'bz) && SAXIHP3AWID[0]; // rv 0 + assign SAXIHP3AWID_in[1] = (SAXIHP3AWID[1] !== 1'bz) && SAXIHP3AWID[1]; // rv 0 + assign SAXIHP3AWID_in[2] = (SAXIHP3AWID[2] !== 1'bz) && SAXIHP3AWID[2]; // rv 0 + assign SAXIHP3AWID_in[3] = (SAXIHP3AWID[3] !== 1'bz) && SAXIHP3AWID[3]; // rv 0 + assign SAXIHP3AWID_in[4] = (SAXIHP3AWID[4] !== 1'bz) && SAXIHP3AWID[4]; // rv 0 + assign SAXIHP3AWID_in[5] = (SAXIHP3AWID[5] !== 1'bz) && SAXIHP3AWID[5]; // rv 0 + assign SAXIHP3AWLEN_in[0] = (SAXIHP3AWLEN[0] !== 1'bz) && SAXIHP3AWLEN[0]; // rv 0 + assign SAXIHP3AWLEN_in[1] = (SAXIHP3AWLEN[1] !== 1'bz) && SAXIHP3AWLEN[1]; // rv 0 + assign SAXIHP3AWLEN_in[2] = (SAXIHP3AWLEN[2] !== 1'bz) && SAXIHP3AWLEN[2]; // rv 0 + assign SAXIHP3AWLEN_in[3] = (SAXIHP3AWLEN[3] !== 1'bz) && SAXIHP3AWLEN[3]; // rv 0 + assign SAXIHP3AWLOCK_in[0] = (SAXIHP3AWLOCK[0] !== 1'bz) && SAXIHP3AWLOCK[0]; // rv 0 + assign SAXIHP3AWLOCK_in[1] = (SAXIHP3AWLOCK[1] !== 1'bz) && SAXIHP3AWLOCK[1]; // rv 0 + assign SAXIHP3AWPROT_in[0] = (SAXIHP3AWPROT[0] !== 1'bz) && SAXIHP3AWPROT[0]; // rv 0 + assign SAXIHP3AWPROT_in[1] = (SAXIHP3AWPROT[1] !== 1'bz) && SAXIHP3AWPROT[1]; // rv 0 + assign SAXIHP3AWPROT_in[2] = (SAXIHP3AWPROT[2] !== 1'bz) && SAXIHP3AWPROT[2]; // rv 0 + assign SAXIHP3AWQOS_in[0] = (SAXIHP3AWQOS[0] !== 1'bz) && SAXIHP3AWQOS[0]; // rv 0 + assign SAXIHP3AWQOS_in[1] = (SAXIHP3AWQOS[1] !== 1'bz) && SAXIHP3AWQOS[1]; // rv 0 + assign SAXIHP3AWQOS_in[2] = (SAXIHP3AWQOS[2] !== 1'bz) && SAXIHP3AWQOS[2]; // rv 0 + assign SAXIHP3AWQOS_in[3] = (SAXIHP3AWQOS[3] !== 1'bz) && SAXIHP3AWQOS[3]; // rv 0 + assign SAXIHP3AWSIZE_in[0] = (SAXIHP3AWSIZE[0] !== 1'bz) && SAXIHP3AWSIZE[0]; // rv 0 + assign SAXIHP3AWSIZE_in[1] = (SAXIHP3AWSIZE[1] !== 1'bz) && SAXIHP3AWSIZE[1]; // rv 0 + assign SAXIHP3AWVALID_in = (SAXIHP3AWVALID !== 1'bz) && SAXIHP3AWVALID; // rv 0 + assign SAXIHP3BREADY_in = (SAXIHP3BREADY !== 1'bz) && SAXIHP3BREADY; // rv 0 + assign SAXIHP3RREADY_in = (SAXIHP3RREADY !== 1'bz) && SAXIHP3RREADY; // rv 0 + assign SAXIHP3WDATA_in[0] = (SAXIHP3WDATA[0] !== 1'bz) && SAXIHP3WDATA[0]; // rv 0 + assign SAXIHP3WDATA_in[10] = (SAXIHP3WDATA[10] !== 1'bz) && SAXIHP3WDATA[10]; // rv 0 + assign SAXIHP3WDATA_in[11] = (SAXIHP3WDATA[11] !== 1'bz) && SAXIHP3WDATA[11]; // rv 0 + assign SAXIHP3WDATA_in[12] = (SAXIHP3WDATA[12] !== 1'bz) && SAXIHP3WDATA[12]; // rv 0 + assign SAXIHP3WDATA_in[13] = (SAXIHP3WDATA[13] !== 1'bz) && SAXIHP3WDATA[13]; // rv 0 + assign SAXIHP3WDATA_in[14] = (SAXIHP3WDATA[14] !== 1'bz) && SAXIHP3WDATA[14]; // rv 0 + assign SAXIHP3WDATA_in[15] = (SAXIHP3WDATA[15] !== 1'bz) && SAXIHP3WDATA[15]; // rv 0 + assign SAXIHP3WDATA_in[16] = (SAXIHP3WDATA[16] !== 1'bz) && SAXIHP3WDATA[16]; // rv 0 + assign SAXIHP3WDATA_in[17] = (SAXIHP3WDATA[17] !== 1'bz) && SAXIHP3WDATA[17]; // rv 0 + assign SAXIHP3WDATA_in[18] = (SAXIHP3WDATA[18] !== 1'bz) && SAXIHP3WDATA[18]; // rv 0 + assign SAXIHP3WDATA_in[19] = (SAXIHP3WDATA[19] !== 1'bz) && SAXIHP3WDATA[19]; // rv 0 + assign SAXIHP3WDATA_in[1] = (SAXIHP3WDATA[1] !== 1'bz) && SAXIHP3WDATA[1]; // rv 0 + assign SAXIHP3WDATA_in[20] = (SAXIHP3WDATA[20] !== 1'bz) && SAXIHP3WDATA[20]; // rv 0 + assign SAXIHP3WDATA_in[21] = (SAXIHP3WDATA[21] !== 1'bz) && SAXIHP3WDATA[21]; // rv 0 + assign SAXIHP3WDATA_in[22] = (SAXIHP3WDATA[22] !== 1'bz) && SAXIHP3WDATA[22]; // rv 0 + assign SAXIHP3WDATA_in[23] = (SAXIHP3WDATA[23] !== 1'bz) && SAXIHP3WDATA[23]; // rv 0 + assign SAXIHP3WDATA_in[24] = (SAXIHP3WDATA[24] !== 1'bz) && SAXIHP3WDATA[24]; // rv 0 + assign SAXIHP3WDATA_in[25] = (SAXIHP3WDATA[25] !== 1'bz) && SAXIHP3WDATA[25]; // rv 0 + assign SAXIHP3WDATA_in[26] = (SAXIHP3WDATA[26] !== 1'bz) && SAXIHP3WDATA[26]; // rv 0 + assign SAXIHP3WDATA_in[27] = (SAXIHP3WDATA[27] !== 1'bz) && SAXIHP3WDATA[27]; // rv 0 + assign SAXIHP3WDATA_in[28] = (SAXIHP3WDATA[28] !== 1'bz) && SAXIHP3WDATA[28]; // rv 0 + assign SAXIHP3WDATA_in[29] = (SAXIHP3WDATA[29] !== 1'bz) && SAXIHP3WDATA[29]; // rv 0 + assign SAXIHP3WDATA_in[2] = (SAXIHP3WDATA[2] !== 1'bz) && SAXIHP3WDATA[2]; // rv 0 + assign SAXIHP3WDATA_in[30] = (SAXIHP3WDATA[30] !== 1'bz) && SAXIHP3WDATA[30]; // rv 0 + assign SAXIHP3WDATA_in[31] = (SAXIHP3WDATA[31] !== 1'bz) && SAXIHP3WDATA[31]; // rv 0 + assign SAXIHP3WDATA_in[32] = (SAXIHP3WDATA[32] !== 1'bz) && SAXIHP3WDATA[32]; // rv 0 + assign SAXIHP3WDATA_in[33] = (SAXIHP3WDATA[33] !== 1'bz) && SAXIHP3WDATA[33]; // rv 0 + assign SAXIHP3WDATA_in[34] = (SAXIHP3WDATA[34] !== 1'bz) && SAXIHP3WDATA[34]; // rv 0 + assign SAXIHP3WDATA_in[35] = (SAXIHP3WDATA[35] !== 1'bz) && SAXIHP3WDATA[35]; // rv 0 + assign SAXIHP3WDATA_in[36] = (SAXIHP3WDATA[36] !== 1'bz) && SAXIHP3WDATA[36]; // rv 0 + assign SAXIHP3WDATA_in[37] = (SAXIHP3WDATA[37] !== 1'bz) && SAXIHP3WDATA[37]; // rv 0 + assign SAXIHP3WDATA_in[38] = (SAXIHP3WDATA[38] !== 1'bz) && SAXIHP3WDATA[38]; // rv 0 + assign SAXIHP3WDATA_in[39] = (SAXIHP3WDATA[39] !== 1'bz) && SAXIHP3WDATA[39]; // rv 0 + assign SAXIHP3WDATA_in[3] = (SAXIHP3WDATA[3] !== 1'bz) && SAXIHP3WDATA[3]; // rv 0 + assign SAXIHP3WDATA_in[40] = (SAXIHP3WDATA[40] !== 1'bz) && SAXIHP3WDATA[40]; // rv 0 + assign SAXIHP3WDATA_in[41] = (SAXIHP3WDATA[41] !== 1'bz) && SAXIHP3WDATA[41]; // rv 0 + assign SAXIHP3WDATA_in[42] = (SAXIHP3WDATA[42] !== 1'bz) && SAXIHP3WDATA[42]; // rv 0 + assign SAXIHP3WDATA_in[43] = (SAXIHP3WDATA[43] !== 1'bz) && SAXIHP3WDATA[43]; // rv 0 + assign SAXIHP3WDATA_in[44] = (SAXIHP3WDATA[44] !== 1'bz) && SAXIHP3WDATA[44]; // rv 0 + assign SAXIHP3WDATA_in[45] = (SAXIHP3WDATA[45] !== 1'bz) && SAXIHP3WDATA[45]; // rv 0 + assign SAXIHP3WDATA_in[46] = (SAXIHP3WDATA[46] !== 1'bz) && SAXIHP3WDATA[46]; // rv 0 + assign SAXIHP3WDATA_in[47] = (SAXIHP3WDATA[47] !== 1'bz) && SAXIHP3WDATA[47]; // rv 0 + assign SAXIHP3WDATA_in[48] = (SAXIHP3WDATA[48] !== 1'bz) && SAXIHP3WDATA[48]; // rv 0 + assign SAXIHP3WDATA_in[49] = (SAXIHP3WDATA[49] !== 1'bz) && SAXIHP3WDATA[49]; // rv 0 + assign SAXIHP3WDATA_in[4] = (SAXIHP3WDATA[4] !== 1'bz) && SAXIHP3WDATA[4]; // rv 0 + assign SAXIHP3WDATA_in[50] = (SAXIHP3WDATA[50] !== 1'bz) && SAXIHP3WDATA[50]; // rv 0 + assign SAXIHP3WDATA_in[51] = (SAXIHP3WDATA[51] !== 1'bz) && SAXIHP3WDATA[51]; // rv 0 + assign SAXIHP3WDATA_in[52] = (SAXIHP3WDATA[52] !== 1'bz) && SAXIHP3WDATA[52]; // rv 0 + assign SAXIHP3WDATA_in[53] = (SAXIHP3WDATA[53] !== 1'bz) && SAXIHP3WDATA[53]; // rv 0 + assign SAXIHP3WDATA_in[54] = (SAXIHP3WDATA[54] !== 1'bz) && SAXIHP3WDATA[54]; // rv 0 + assign SAXIHP3WDATA_in[55] = (SAXIHP3WDATA[55] !== 1'bz) && SAXIHP3WDATA[55]; // rv 0 + assign SAXIHP3WDATA_in[56] = (SAXIHP3WDATA[56] !== 1'bz) && SAXIHP3WDATA[56]; // rv 0 + assign SAXIHP3WDATA_in[57] = (SAXIHP3WDATA[57] !== 1'bz) && SAXIHP3WDATA[57]; // rv 0 + assign SAXIHP3WDATA_in[58] = (SAXIHP3WDATA[58] !== 1'bz) && SAXIHP3WDATA[58]; // rv 0 + assign SAXIHP3WDATA_in[59] = (SAXIHP3WDATA[59] !== 1'bz) && SAXIHP3WDATA[59]; // rv 0 + assign SAXIHP3WDATA_in[5] = (SAXIHP3WDATA[5] !== 1'bz) && SAXIHP3WDATA[5]; // rv 0 + assign SAXIHP3WDATA_in[60] = (SAXIHP3WDATA[60] !== 1'bz) && SAXIHP3WDATA[60]; // rv 0 + assign SAXIHP3WDATA_in[61] = (SAXIHP3WDATA[61] !== 1'bz) && SAXIHP3WDATA[61]; // rv 0 + assign SAXIHP3WDATA_in[62] = (SAXIHP3WDATA[62] !== 1'bz) && SAXIHP3WDATA[62]; // rv 0 + assign SAXIHP3WDATA_in[63] = (SAXIHP3WDATA[63] !== 1'bz) && SAXIHP3WDATA[63]; // rv 0 + assign SAXIHP3WDATA_in[6] = (SAXIHP3WDATA[6] !== 1'bz) && SAXIHP3WDATA[6]; // rv 0 + assign SAXIHP3WDATA_in[7] = (SAXIHP3WDATA[7] !== 1'bz) && SAXIHP3WDATA[7]; // rv 0 + assign SAXIHP3WDATA_in[8] = (SAXIHP3WDATA[8] !== 1'bz) && SAXIHP3WDATA[8]; // rv 0 + assign SAXIHP3WDATA_in[9] = (SAXIHP3WDATA[9] !== 1'bz) && SAXIHP3WDATA[9]; // rv 0 + assign SAXIHP3WID_in[0] = (SAXIHP3WID[0] !== 1'bz) && SAXIHP3WID[0]; // rv 0 + assign SAXIHP3WID_in[1] = (SAXIHP3WID[1] !== 1'bz) && SAXIHP3WID[1]; // rv 0 + assign SAXIHP3WID_in[2] = (SAXIHP3WID[2] !== 1'bz) && SAXIHP3WID[2]; // rv 0 + assign SAXIHP3WID_in[3] = (SAXIHP3WID[3] !== 1'bz) && SAXIHP3WID[3]; // rv 0 + assign SAXIHP3WID_in[4] = (SAXIHP3WID[4] !== 1'bz) && SAXIHP3WID[4]; // rv 0 + assign SAXIHP3WID_in[5] = (SAXIHP3WID[5] !== 1'bz) && SAXIHP3WID[5]; // rv 0 + assign SAXIHP3WLAST_in = (SAXIHP3WLAST !== 1'bz) && SAXIHP3WLAST; // rv 0 + assign SAXIHP3WSTRB_in[0] = (SAXIHP3WSTRB[0] !== 1'bz) && SAXIHP3WSTRB[0]; // rv 0 + assign SAXIHP3WSTRB_in[1] = (SAXIHP3WSTRB[1] !== 1'bz) && SAXIHP3WSTRB[1]; // rv 0 + assign SAXIHP3WSTRB_in[2] = (SAXIHP3WSTRB[2] !== 1'bz) && SAXIHP3WSTRB[2]; // rv 0 + assign SAXIHP3WSTRB_in[3] = (SAXIHP3WSTRB[3] !== 1'bz) && SAXIHP3WSTRB[3]; // rv 0 + assign SAXIHP3WSTRB_in[4] = (SAXIHP3WSTRB[4] !== 1'bz) && SAXIHP3WSTRB[4]; // rv 0 + assign SAXIHP3WSTRB_in[5] = (SAXIHP3WSTRB[5] !== 1'bz) && SAXIHP3WSTRB[5]; // rv 0 + assign SAXIHP3WSTRB_in[6] = (SAXIHP3WSTRB[6] !== 1'bz) && SAXIHP3WSTRB[6]; // rv 0 + assign SAXIHP3WSTRB_in[7] = (SAXIHP3WSTRB[7] !== 1'bz) && SAXIHP3WSTRB[7]; // rv 0 + assign SAXIHP3WVALID_in = (SAXIHP3WVALID !== 1'bz) && SAXIHP3WVALID; // rv 0 +`endif + assign DDRARB_in[0] = (DDRARB[0] !== 1'bz) && DDRARB[0]; // rv 0 + assign DDRARB_in[1] = (DDRARB[1] !== 1'bz) && DDRARB[1]; // rv 0 + assign DDRARB_in[2] = (DDRARB[2] !== 1'bz) && DDRARB[2]; // rv 0 + assign DDRARB_in[3] = (DDRARB[3] !== 1'bz) && DDRARB[3]; // rv 0 + assign EMIOCAN0PHYRX_in = (EMIOCAN0PHYRX !== 1'bz) && EMIOCAN0PHYRX; // rv 0 + assign EMIOCAN1PHYRX_in = (EMIOCAN1PHYRX !== 1'bz) && EMIOCAN1PHYRX; // rv 0 + assign EMIOENET0EXTINTIN_in = (EMIOENET0EXTINTIN !== 1'bz) && EMIOENET0EXTINTIN; // rv 0 + assign EMIOENET0GMIICOL_in = (EMIOENET0GMIICOL !== 1'bz) && EMIOENET0GMIICOL; // rv 0 + assign EMIOENET0GMIICRS_in = (EMIOENET0GMIICRS !== 1'bz) && EMIOENET0GMIICRS; // rv 0 + assign EMIOENET0GMIITXCLK_in = (EMIOENET0GMIITXCLK !== 1'bz) && EMIOENET0GMIITXCLK; // rv 0 + assign EMIOENET0MDIOI_in = (EMIOENET0MDIOI !== 1'bz) && EMIOENET0MDIOI; // rv 0 + assign EMIOENET1EXTINTIN_in = (EMIOENET1EXTINTIN !== 1'bz) && EMIOENET1EXTINTIN; // rv 0 + assign EMIOENET1GMIICOL_in = (EMIOENET1GMIICOL !== 1'bz) && EMIOENET1GMIICOL; // rv 0 + assign EMIOENET1GMIICRS_in = (EMIOENET1GMIICRS !== 1'bz) && EMIOENET1GMIICRS; // rv 0 + assign EMIOENET1GMIITXCLK_in = (EMIOENET1GMIITXCLK !== 1'bz) && EMIOENET1GMIITXCLK; // rv 0 + assign EMIOENET1MDIOI_in = (EMIOENET1MDIOI !== 1'bz) && EMIOENET1MDIOI; // rv 0 + assign EMIOGPIOI_in[0] = (EMIOGPIOI[0] !== 1'bz) && EMIOGPIOI[0]; // rv 0 + assign EMIOGPIOI_in[10] = (EMIOGPIOI[10] !== 1'bz) && EMIOGPIOI[10]; // rv 0 + assign EMIOGPIOI_in[11] = (EMIOGPIOI[11] !== 1'bz) && EMIOGPIOI[11]; // rv 0 + assign EMIOGPIOI_in[12] = (EMIOGPIOI[12] !== 1'bz) && EMIOGPIOI[12]; // rv 0 + assign EMIOGPIOI_in[13] = (EMIOGPIOI[13] !== 1'bz) && EMIOGPIOI[13]; // rv 0 + assign EMIOGPIOI_in[14] = (EMIOGPIOI[14] !== 1'bz) && EMIOGPIOI[14]; // rv 0 + assign EMIOGPIOI_in[15] = (EMIOGPIOI[15] !== 1'bz) && EMIOGPIOI[15]; // rv 0 + assign EMIOGPIOI_in[16] = (EMIOGPIOI[16] !== 1'bz) && EMIOGPIOI[16]; // rv 0 + assign EMIOGPIOI_in[17] = (EMIOGPIOI[17] !== 1'bz) && EMIOGPIOI[17]; // rv 0 + assign EMIOGPIOI_in[18] = (EMIOGPIOI[18] !== 1'bz) && EMIOGPIOI[18]; // rv 0 + assign EMIOGPIOI_in[19] = (EMIOGPIOI[19] !== 1'bz) && EMIOGPIOI[19]; // rv 0 + assign EMIOGPIOI_in[1] = (EMIOGPIOI[1] !== 1'bz) && EMIOGPIOI[1]; // rv 0 + assign EMIOGPIOI_in[20] = (EMIOGPIOI[20] !== 1'bz) && EMIOGPIOI[20]; // rv 0 + assign EMIOGPIOI_in[21] = (EMIOGPIOI[21] !== 1'bz) && EMIOGPIOI[21]; // rv 0 + assign EMIOGPIOI_in[22] = (EMIOGPIOI[22] !== 1'bz) && EMIOGPIOI[22]; // rv 0 + assign EMIOGPIOI_in[23] = (EMIOGPIOI[23] !== 1'bz) && EMIOGPIOI[23]; // rv 0 + assign EMIOGPIOI_in[24] = (EMIOGPIOI[24] !== 1'bz) && EMIOGPIOI[24]; // rv 0 + assign EMIOGPIOI_in[25] = (EMIOGPIOI[25] !== 1'bz) && EMIOGPIOI[25]; // rv 0 + assign EMIOGPIOI_in[26] = (EMIOGPIOI[26] !== 1'bz) && EMIOGPIOI[26]; // rv 0 + assign EMIOGPIOI_in[27] = (EMIOGPIOI[27] !== 1'bz) && EMIOGPIOI[27]; // rv 0 + assign EMIOGPIOI_in[28] = (EMIOGPIOI[28] !== 1'bz) && EMIOGPIOI[28]; // rv 0 + assign EMIOGPIOI_in[29] = (EMIOGPIOI[29] !== 1'bz) && EMIOGPIOI[29]; // rv 0 + assign EMIOGPIOI_in[2] = (EMIOGPIOI[2] !== 1'bz) && EMIOGPIOI[2]; // rv 0 + assign EMIOGPIOI_in[30] = (EMIOGPIOI[30] !== 1'bz) && EMIOGPIOI[30]; // rv 0 + assign EMIOGPIOI_in[31] = (EMIOGPIOI[31] !== 1'bz) && EMIOGPIOI[31]; // rv 0 + assign EMIOGPIOI_in[32] = (EMIOGPIOI[32] !== 1'bz) && EMIOGPIOI[32]; // rv 0 + assign EMIOGPIOI_in[33] = (EMIOGPIOI[33] !== 1'bz) && EMIOGPIOI[33]; // rv 0 + assign EMIOGPIOI_in[34] = (EMIOGPIOI[34] !== 1'bz) && EMIOGPIOI[34]; // rv 0 + assign EMIOGPIOI_in[35] = (EMIOGPIOI[35] !== 1'bz) && EMIOGPIOI[35]; // rv 0 + assign EMIOGPIOI_in[36] = (EMIOGPIOI[36] !== 1'bz) && EMIOGPIOI[36]; // rv 0 + assign EMIOGPIOI_in[37] = (EMIOGPIOI[37] !== 1'bz) && EMIOGPIOI[37]; // rv 0 + assign EMIOGPIOI_in[38] = (EMIOGPIOI[38] !== 1'bz) && EMIOGPIOI[38]; // rv 0 + assign EMIOGPIOI_in[39] = (EMIOGPIOI[39] !== 1'bz) && EMIOGPIOI[39]; // rv 0 + assign EMIOGPIOI_in[3] = (EMIOGPIOI[3] !== 1'bz) && EMIOGPIOI[3]; // rv 0 + assign EMIOGPIOI_in[40] = (EMIOGPIOI[40] !== 1'bz) && EMIOGPIOI[40]; // rv 0 + assign EMIOGPIOI_in[41] = (EMIOGPIOI[41] !== 1'bz) && EMIOGPIOI[41]; // rv 0 + assign EMIOGPIOI_in[42] = (EMIOGPIOI[42] !== 1'bz) && EMIOGPIOI[42]; // rv 0 + assign EMIOGPIOI_in[43] = (EMIOGPIOI[43] !== 1'bz) && EMIOGPIOI[43]; // rv 0 + assign EMIOGPIOI_in[44] = (EMIOGPIOI[44] !== 1'bz) && EMIOGPIOI[44]; // rv 0 + assign EMIOGPIOI_in[45] = (EMIOGPIOI[45] !== 1'bz) && EMIOGPIOI[45]; // rv 0 + assign EMIOGPIOI_in[46] = (EMIOGPIOI[46] !== 1'bz) && EMIOGPIOI[46]; // rv 0 + assign EMIOGPIOI_in[47] = (EMIOGPIOI[47] !== 1'bz) && EMIOGPIOI[47]; // rv 0 + assign EMIOGPIOI_in[48] = (EMIOGPIOI[48] !== 1'bz) && EMIOGPIOI[48]; // rv 0 + assign EMIOGPIOI_in[49] = (EMIOGPIOI[49] !== 1'bz) && EMIOGPIOI[49]; // rv 0 + assign EMIOGPIOI_in[4] = (EMIOGPIOI[4] !== 1'bz) && EMIOGPIOI[4]; // rv 0 + assign EMIOGPIOI_in[50] = (EMIOGPIOI[50] !== 1'bz) && EMIOGPIOI[50]; // rv 0 + assign EMIOGPIOI_in[51] = (EMIOGPIOI[51] !== 1'bz) && EMIOGPIOI[51]; // rv 0 + assign EMIOGPIOI_in[52] = (EMIOGPIOI[52] !== 1'bz) && EMIOGPIOI[52]; // rv 0 + assign EMIOGPIOI_in[53] = (EMIOGPIOI[53] !== 1'bz) && EMIOGPIOI[53]; // rv 0 + assign EMIOGPIOI_in[54] = (EMIOGPIOI[54] !== 1'bz) && EMIOGPIOI[54]; // rv 0 + assign EMIOGPIOI_in[55] = (EMIOGPIOI[55] !== 1'bz) && EMIOGPIOI[55]; // rv 0 + assign EMIOGPIOI_in[56] = (EMIOGPIOI[56] !== 1'bz) && EMIOGPIOI[56]; // rv 0 + assign EMIOGPIOI_in[57] = (EMIOGPIOI[57] !== 1'bz) && EMIOGPIOI[57]; // rv 0 + assign EMIOGPIOI_in[58] = (EMIOGPIOI[58] !== 1'bz) && EMIOGPIOI[58]; // rv 0 + assign EMIOGPIOI_in[59] = (EMIOGPIOI[59] !== 1'bz) && EMIOGPIOI[59]; // rv 0 + assign EMIOGPIOI_in[5] = (EMIOGPIOI[5] !== 1'bz) && EMIOGPIOI[5]; // rv 0 + assign EMIOGPIOI_in[60] = (EMIOGPIOI[60] !== 1'bz) && EMIOGPIOI[60]; // rv 0 + assign EMIOGPIOI_in[61] = (EMIOGPIOI[61] !== 1'bz) && EMIOGPIOI[61]; // rv 0 + assign EMIOGPIOI_in[62] = (EMIOGPIOI[62] !== 1'bz) && EMIOGPIOI[62]; // rv 0 + assign EMIOGPIOI_in[63] = (EMIOGPIOI[63] !== 1'bz) && EMIOGPIOI[63]; // rv 0 + assign EMIOGPIOI_in[6] = (EMIOGPIOI[6] !== 1'bz) && EMIOGPIOI[6]; // rv 0 + assign EMIOGPIOI_in[7] = (EMIOGPIOI[7] !== 1'bz) && EMIOGPIOI[7]; // rv 0 + assign EMIOGPIOI_in[8] = (EMIOGPIOI[8] !== 1'bz) && EMIOGPIOI[8]; // rv 0 + assign EMIOGPIOI_in[9] = (EMIOGPIOI[9] !== 1'bz) && EMIOGPIOI[9]; // rv 0 + assign EMIOI2C0SCLI_in = (EMIOI2C0SCLI !== 1'bz) && EMIOI2C0SCLI; // rv 0 + assign EMIOI2C0SDAI_in = (EMIOI2C0SDAI !== 1'bz) && EMIOI2C0SDAI; // rv 0 + assign EMIOI2C1SCLI_in = (EMIOI2C1SCLI !== 1'bz) && EMIOI2C1SCLI; // rv 0 + assign EMIOI2C1SDAI_in = (EMIOI2C1SDAI !== 1'bz) && EMIOI2C1SDAI; // rv 0 + assign EMIOSDIO0CDN_in = (EMIOSDIO0CDN !== 1'bz) && EMIOSDIO0CDN; // rv 0 + assign EMIOSDIO0WP_in = (EMIOSDIO0WP !== 1'bz) && EMIOSDIO0WP; // rv 0 + assign EMIOSDIO1CDN_in = (EMIOSDIO1CDN !== 1'bz) && EMIOSDIO1CDN; // rv 0 + assign EMIOSDIO1WP_in = (EMIOSDIO1WP !== 1'bz) && EMIOSDIO1WP; // rv 0 + assign EMIOSPI0MI_in = (EMIOSPI0MI !== 1'bz) && EMIOSPI0MI; // rv 0 + assign EMIOSPI0SCLKI_in = (EMIOSPI0SCLKI !== 1'bz) && EMIOSPI0SCLKI; // rv 0 + assign EMIOSPI0SI_in = (EMIOSPI0SI !== 1'bz) && EMIOSPI0SI; // rv 0 + assign EMIOSPI0SSIN_in = (EMIOSPI0SSIN !== 1'bz) && EMIOSPI0SSIN; // rv 0 + assign EMIOSPI1MI_in = (EMIOSPI1MI !== 1'bz) && EMIOSPI1MI; // rv 0 + assign EMIOSPI1SCLKI_in = (EMIOSPI1SCLKI !== 1'bz) && EMIOSPI1SCLKI; // rv 0 + assign EMIOSPI1SI_in = (EMIOSPI1SI !== 1'bz) && EMIOSPI1SI; // rv 0 + assign EMIOSPI1SSIN_in = (EMIOSPI1SSIN !== 1'bz) && EMIOSPI1SSIN; // rv 0 + assign EMIOSRAMINTIN_in = (EMIOSRAMINTIN !== 1'bz) && EMIOSRAMINTIN; // rv 0 + assign EMIOTRACECLK_in = (EMIOTRACECLK !== 1'bz) && EMIOTRACECLK; // rv 0 + assign EMIOTTC0CLKI_in[0] = (EMIOTTC0CLKI[0] !== 1'bz) && EMIOTTC0CLKI[0]; // rv 0 + assign EMIOTTC0CLKI_in[1] = (EMIOTTC0CLKI[1] !== 1'bz) && EMIOTTC0CLKI[1]; // rv 0 + assign EMIOTTC0CLKI_in[2] = (EMIOTTC0CLKI[2] !== 1'bz) && EMIOTTC0CLKI[2]; // rv 0 + assign EMIOTTC1CLKI_in[0] = (EMIOTTC1CLKI[0] !== 1'bz) && EMIOTTC1CLKI[0]; // rv 0 + assign EMIOTTC1CLKI_in[1] = (EMIOTTC1CLKI[1] !== 1'bz) && EMIOTTC1CLKI[1]; // rv 0 + assign EMIOTTC1CLKI_in[2] = (EMIOTTC1CLKI[2] !== 1'bz) && EMIOTTC1CLKI[2]; // rv 0 + assign EMIOUART0CTSN_in = (EMIOUART0CTSN !== 1'bz) && EMIOUART0CTSN; // rv 0 + assign EMIOUART0DCDN_in = (EMIOUART0DCDN !== 1'bz) && EMIOUART0DCDN; // rv 0 + assign EMIOUART0DSRN_in = (EMIOUART0DSRN !== 1'bz) && EMIOUART0DSRN; // rv 0 + assign EMIOUART0RIN_in = (EMIOUART0RIN !== 1'bz) && EMIOUART0RIN; // rv 0 + assign EMIOUART0RX_in = (EMIOUART0RX !== 1'bz) && EMIOUART0RX; // rv 0 + assign EMIOUART1CTSN_in = (EMIOUART1CTSN !== 1'bz) && EMIOUART1CTSN; // rv 0 + assign EMIOUART1DCDN_in = (EMIOUART1DCDN !== 1'bz) && EMIOUART1DCDN; // rv 0 + assign EMIOUART1DSRN_in = (EMIOUART1DSRN !== 1'bz) && EMIOUART1DSRN; // rv 0 + assign EMIOUART1RIN_in = (EMIOUART1RIN !== 1'bz) && EMIOUART1RIN; // rv 0 + assign EMIOUART1RX_in = (EMIOUART1RX !== 1'bz) && EMIOUART1RX; // rv 0 + assign EMIOUSB0VBUSPWRFAULT_in = (EMIOUSB0VBUSPWRFAULT !== 1'bz) && EMIOUSB0VBUSPWRFAULT; // rv 0 + assign EMIOUSB1VBUSPWRFAULT_in = (EMIOUSB1VBUSPWRFAULT !== 1'bz) && EMIOUSB1VBUSPWRFAULT; // rv 0 + assign EMIOWDTCLKI_in = (EMIOWDTCLKI !== 1'bz) && EMIOWDTCLKI; // rv 0 + assign EVENTEVENTI_in = (EVENTEVENTI !== 1'bz) && EVENTEVENTI; // rv 0 + assign FCLKCLKTRIGN_in[0] = (FCLKCLKTRIGN[0] !== 1'bz) && FCLKCLKTRIGN[0]; // rv 0 + assign FCLKCLKTRIGN_in[1] = (FCLKCLKTRIGN[1] !== 1'bz) && FCLKCLKTRIGN[1]; // rv 0 + assign FCLKCLKTRIGN_in[2] = (FCLKCLKTRIGN[2] !== 1'bz) && FCLKCLKTRIGN[2]; // rv 0 + assign FCLKCLKTRIGN_in[3] = (FCLKCLKTRIGN[3] !== 1'bz) && FCLKCLKTRIGN[3]; // rv 0 + assign FPGAIDLEN_in = (FPGAIDLEN !== 1'bz) && FPGAIDLEN; // rv 0 + assign FTMTF2PDEBUG_in[0] = (FTMTF2PDEBUG[0] !== 1'bz) && FTMTF2PDEBUG[0]; // rv 0 + assign FTMTF2PDEBUG_in[10] = (FTMTF2PDEBUG[10] !== 1'bz) && FTMTF2PDEBUG[10]; // rv 0 + assign FTMTF2PDEBUG_in[11] = (FTMTF2PDEBUG[11] !== 1'bz) && FTMTF2PDEBUG[11]; // rv 0 + assign FTMTF2PDEBUG_in[12] = (FTMTF2PDEBUG[12] !== 1'bz) && FTMTF2PDEBUG[12]; // rv 0 + assign FTMTF2PDEBUG_in[13] = (FTMTF2PDEBUG[13] !== 1'bz) && FTMTF2PDEBUG[13]; // rv 0 + assign FTMTF2PDEBUG_in[14] = (FTMTF2PDEBUG[14] !== 1'bz) && FTMTF2PDEBUG[14]; // rv 0 + assign FTMTF2PDEBUG_in[15] = (FTMTF2PDEBUG[15] !== 1'bz) && FTMTF2PDEBUG[15]; // rv 0 + assign FTMTF2PDEBUG_in[16] = (FTMTF2PDEBUG[16] !== 1'bz) && FTMTF2PDEBUG[16]; // rv 0 + assign FTMTF2PDEBUG_in[17] = (FTMTF2PDEBUG[17] !== 1'bz) && FTMTF2PDEBUG[17]; // rv 0 + assign FTMTF2PDEBUG_in[18] = (FTMTF2PDEBUG[18] !== 1'bz) && FTMTF2PDEBUG[18]; // rv 0 + assign FTMTF2PDEBUG_in[19] = (FTMTF2PDEBUG[19] !== 1'bz) && FTMTF2PDEBUG[19]; // rv 0 + assign FTMTF2PDEBUG_in[1] = (FTMTF2PDEBUG[1] !== 1'bz) && FTMTF2PDEBUG[1]; // rv 0 + assign FTMTF2PDEBUG_in[20] = (FTMTF2PDEBUG[20] !== 1'bz) && FTMTF2PDEBUG[20]; // rv 0 + assign FTMTF2PDEBUG_in[21] = (FTMTF2PDEBUG[21] !== 1'bz) && FTMTF2PDEBUG[21]; // rv 0 + assign FTMTF2PDEBUG_in[22] = (FTMTF2PDEBUG[22] !== 1'bz) && FTMTF2PDEBUG[22]; // rv 0 + assign FTMTF2PDEBUG_in[23] = (FTMTF2PDEBUG[23] !== 1'bz) && FTMTF2PDEBUG[23]; // rv 0 + assign FTMTF2PDEBUG_in[24] = (FTMTF2PDEBUG[24] !== 1'bz) && FTMTF2PDEBUG[24]; // rv 0 + assign FTMTF2PDEBUG_in[25] = (FTMTF2PDEBUG[25] !== 1'bz) && FTMTF2PDEBUG[25]; // rv 0 + assign FTMTF2PDEBUG_in[26] = (FTMTF2PDEBUG[26] !== 1'bz) && FTMTF2PDEBUG[26]; // rv 0 + assign FTMTF2PDEBUG_in[27] = (FTMTF2PDEBUG[27] !== 1'bz) && FTMTF2PDEBUG[27]; // rv 0 + assign FTMTF2PDEBUG_in[28] = (FTMTF2PDEBUG[28] !== 1'bz) && FTMTF2PDEBUG[28]; // rv 0 + assign FTMTF2PDEBUG_in[29] = (FTMTF2PDEBUG[29] !== 1'bz) && FTMTF2PDEBUG[29]; // rv 0 + assign FTMTF2PDEBUG_in[2] = (FTMTF2PDEBUG[2] !== 1'bz) && FTMTF2PDEBUG[2]; // rv 0 + assign FTMTF2PDEBUG_in[30] = (FTMTF2PDEBUG[30] !== 1'bz) && FTMTF2PDEBUG[30]; // rv 0 + assign FTMTF2PDEBUG_in[31] = (FTMTF2PDEBUG[31] !== 1'bz) && FTMTF2PDEBUG[31]; // rv 0 + assign FTMTF2PDEBUG_in[3] = (FTMTF2PDEBUG[3] !== 1'bz) && FTMTF2PDEBUG[3]; // rv 0 + assign FTMTF2PDEBUG_in[4] = (FTMTF2PDEBUG[4] !== 1'bz) && FTMTF2PDEBUG[4]; // rv 0 + assign FTMTF2PDEBUG_in[5] = (FTMTF2PDEBUG[5] !== 1'bz) && FTMTF2PDEBUG[5]; // rv 0 + assign FTMTF2PDEBUG_in[6] = (FTMTF2PDEBUG[6] !== 1'bz) && FTMTF2PDEBUG[6]; // rv 0 + assign FTMTF2PDEBUG_in[7] = (FTMTF2PDEBUG[7] !== 1'bz) && FTMTF2PDEBUG[7]; // rv 0 + assign FTMTF2PDEBUG_in[8] = (FTMTF2PDEBUG[8] !== 1'bz) && FTMTF2PDEBUG[8]; // rv 0 + assign FTMTF2PDEBUG_in[9] = (FTMTF2PDEBUG[9] !== 1'bz) && FTMTF2PDEBUG[9]; // rv 0 + assign FTMTF2PTRIG_in[0] = (FTMTF2PTRIG[0] !== 1'bz) && FTMTF2PTRIG[0]; // rv 0 + assign FTMTF2PTRIG_in[1] = (FTMTF2PTRIG[1] !== 1'bz) && FTMTF2PTRIG[1]; // rv 0 + assign FTMTF2PTRIG_in[2] = (FTMTF2PTRIG[2] !== 1'bz) && FTMTF2PTRIG[2]; // rv 0 + assign FTMTF2PTRIG_in[3] = (FTMTF2PTRIG[3] !== 1'bz) && FTMTF2PTRIG[3]; // rv 0 + assign FTMTP2FTRIGACK_in[0] = (FTMTP2FTRIGACK[0] !== 1'bz) && FTMTP2FTRIGACK[0]; // rv 0 + assign FTMTP2FTRIGACK_in[1] = (FTMTP2FTRIGACK[1] !== 1'bz) && FTMTP2FTRIGACK[1]; // rv 0 + assign FTMTP2FTRIGACK_in[2] = (FTMTP2FTRIGACK[2] !== 1'bz) && FTMTP2FTRIGACK[2]; // rv 0 + assign FTMTP2FTRIGACK_in[3] = (FTMTP2FTRIGACK[3] !== 1'bz) && FTMTP2FTRIGACK[3]; // rv 0 + assign IRQF2P_in[0] = (IRQF2P[0] !== 1'bz) && IRQF2P[0]; // rv 0 + assign IRQF2P_in[10] = (IRQF2P[10] !== 1'bz) && IRQF2P[10]; // rv 0 + assign IRQF2P_in[11] = (IRQF2P[11] !== 1'bz) && IRQF2P[11]; // rv 0 + assign IRQF2P_in[12] = (IRQF2P[12] !== 1'bz) && IRQF2P[12]; // rv 0 + assign IRQF2P_in[13] = (IRQF2P[13] !== 1'bz) && IRQF2P[13]; // rv 0 + assign IRQF2P_in[14] = (IRQF2P[14] !== 1'bz) && IRQF2P[14]; // rv 0 + assign IRQF2P_in[15] = (IRQF2P[15] !== 1'bz) && IRQF2P[15]; // rv 0 + assign IRQF2P_in[16] = (IRQF2P[16] !== 1'bz) && IRQF2P[16]; // rv 0 + assign IRQF2P_in[17] = (IRQF2P[17] !== 1'bz) && IRQF2P[17]; // rv 0 + assign IRQF2P_in[18] = (IRQF2P[18] !== 1'bz) && IRQF2P[18]; // rv 0 + assign IRQF2P_in[19] = (IRQF2P[19] !== 1'bz) && IRQF2P[19]; // rv 0 + assign IRQF2P_in[1] = (IRQF2P[1] !== 1'bz) && IRQF2P[1]; // rv 0 + assign IRQF2P_in[2] = (IRQF2P[2] !== 1'bz) && IRQF2P[2]; // rv 0 + assign IRQF2P_in[3] = (IRQF2P[3] !== 1'bz) && IRQF2P[3]; // rv 0 + assign IRQF2P_in[4] = (IRQF2P[4] !== 1'bz) && IRQF2P[4]; // rv 0 + assign IRQF2P_in[5] = (IRQF2P[5] !== 1'bz) && IRQF2P[5]; // rv 0 + assign IRQF2P_in[6] = (IRQF2P[6] !== 1'bz) && IRQF2P[6]; // rv 0 + assign IRQF2P_in[7] = (IRQF2P[7] !== 1'bz) && IRQF2P[7]; // rv 0 + assign IRQF2P_in[8] = (IRQF2P[8] !== 1'bz) && IRQF2P[8]; // rv 0 + assign IRQF2P_in[9] = (IRQF2P[9] !== 1'bz) && IRQF2P[9]; // rv 0 + assign SAXIACPARQOS_in[0] = (SAXIACPARQOS[0] !== 1'bz) && SAXIACPARQOS[0]; // rv 0 + assign SAXIACPARQOS_in[1] = (SAXIACPARQOS[1] !== 1'bz) && SAXIACPARQOS[1]; // rv 0 + assign SAXIACPARQOS_in[2] = (SAXIACPARQOS[2] !== 1'bz) && SAXIACPARQOS[2]; // rv 0 + assign SAXIACPARQOS_in[3] = (SAXIACPARQOS[3] !== 1'bz) && SAXIACPARQOS[3]; // rv 0 + assign SAXIACPAWQOS_in[0] = (SAXIACPAWQOS[0] !== 1'bz) && SAXIACPAWQOS[0]; // rv 0 + assign SAXIACPAWQOS_in[1] = (SAXIACPAWQOS[1] !== 1'bz) && SAXIACPAWQOS[1]; // rv 0 + assign SAXIACPAWQOS_in[2] = (SAXIACPAWQOS[2] !== 1'bz) && SAXIACPAWQOS[2]; // rv 0 + assign SAXIACPAWQOS_in[3] = (SAXIACPAWQOS[3] !== 1'bz) && SAXIACPAWQOS[3]; // rv 0 + assign SAXIHP0RDISSUECAP1EN_in = (SAXIHP0RDISSUECAP1EN !== 1'bz) && SAXIHP0RDISSUECAP1EN; // rv 0 + assign SAXIHP0WRISSUECAP1EN_in = (SAXIHP0WRISSUECAP1EN !== 1'bz) && SAXIHP0WRISSUECAP1EN; // rv 0 + assign SAXIHP1RDISSUECAP1EN_in = (SAXIHP1RDISSUECAP1EN !== 1'bz) && SAXIHP1RDISSUECAP1EN; // rv 0 + assign SAXIHP1WRISSUECAP1EN_in = (SAXIHP1WRISSUECAP1EN !== 1'bz) && SAXIHP1WRISSUECAP1EN; // rv 0 + assign SAXIHP2RDISSUECAP1EN_in = (SAXIHP2RDISSUECAP1EN !== 1'bz) && SAXIHP2RDISSUECAP1EN; // rv 0 + assign SAXIHP2WRISSUECAP1EN_in = (SAXIHP2WRISSUECAP1EN !== 1'bz) && SAXIHP2WRISSUECAP1EN; // rv 0 + assign SAXIHP3RDISSUECAP1EN_in = (SAXIHP3RDISSUECAP1EN !== 1'bz) && SAXIHP3RDISSUECAP1EN; // rv 0 + assign SAXIHP3WRISSUECAP1EN_in = (SAXIHP3WRISSUECAP1EN !== 1'bz) && SAXIHP3WRISSUECAP1EN; // rv 0 + + initial + begin + $display("Warning on instance %m : The Zynq-7000 All Programmable SoC does not have a simulation model. Behavioral simulation of Zynq-7000 (e.g. Zynq PS7 block) is not supported in any simulator. Please use the AXI BFM simulation model to verify the AXI transactions."); + + end + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (DMA0ACLK => DMA0DATYPE[0]) = (100:100:100, 100:100:100); + (DMA0ACLK => DMA0DATYPE[1]) = (100:100:100, 100:100:100); + (DMA0ACLK => DMA0DAVALID) = (100:100:100, 100:100:100); + (DMA0ACLK => DMA0DRREADY) = (100:100:100, 100:100:100); + (DMA1ACLK => DMA1DATYPE[0]) = (100:100:100, 100:100:100); + (DMA1ACLK => DMA1DATYPE[1]) = (100:100:100, 100:100:100); + (DMA1ACLK => DMA1DAVALID) = (100:100:100, 100:100:100); + (DMA1ACLK => DMA1DRREADY) = (100:100:100, 100:100:100); + (DMA2ACLK => DMA2DATYPE[0]) = (100:100:100, 100:100:100); + (DMA2ACLK => DMA2DATYPE[1]) = (100:100:100, 100:100:100); + (DMA2ACLK => DMA2DAVALID) = (100:100:100, 100:100:100); + (DMA2ACLK => DMA2DRREADY) = (100:100:100, 100:100:100); + (DMA3ACLK => DMA3DATYPE[0]) = (100:100:100, 100:100:100); + (DMA3ACLK => DMA3DATYPE[1]) = (100:100:100, 100:100:100); + (DMA3ACLK => DMA3DAVALID) = (100:100:100, 100:100:100); + (DMA3ACLK => DMA3DRREADY) = (100:100:100, 100:100:100); + (EMIOENET0GMIIRXCLK => EMIOENET0PTPDELAYREQRX) = (100:100:100, 100:100:100); + (EMIOENET0GMIIRXCLK => EMIOENET0PTPPDELAYREQRX) = (100:100:100, 100:100:100); + (EMIOENET0GMIIRXCLK => EMIOENET0PTPPDELAYRESPRX) = (100:100:100, 100:100:100); + (EMIOENET0GMIIRXCLK => EMIOENET0PTPSYNCFRAMERX) = (100:100:100, 100:100:100); + (EMIOENET0GMIIRXCLK => EMIOENET0SOFRX) = (100:100:100, 100:100:100); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXER) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0PTPDELAYREQTX) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0PTPPDELAYREQTX) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0PTPPDELAYRESPTX) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0PTPSYNCFRAMETX) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0SOFTX) = (0:0:0, 0:0:0); + (EMIOENET1GMIIRXCLK => EMIOENET1SOFRX) = (100:100:100, 100:100:100); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXER) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPDELAYREQRX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPDELAYREQTX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPPDELAYREQRX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPPDELAYREQTX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPPDELAYRESPRX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPPDELAYRESPTX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPSYNCFRAMERX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1PTPSYNCFRAMETX) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1SOFTX) = (0:0:0, 0:0:0); + (EMIOPJTAGTCK => EMIOPJTAGTDO) = (100:100:100, 100:100:100); + (EMIOPJTAGTCK => EMIOPJTAGTDTN) = (100:100:100, 100:100:100); + (EMIOTRACECLK => EMIOTRACECTL) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[0]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[10]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[11]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[12]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[13]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[14]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[15]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[16]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[17]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[18]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[19]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[1]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[20]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[21]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[22]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[23]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[24]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[25]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[26]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[27]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[28]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[29]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[2]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[30]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[31]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[3]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[4]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[5]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[6]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[7]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[8]) = (0:0:0, 0:0:0); + (EMIOTRACECLK => EMIOTRACEDATA[9]) = (0:0:0, 0:0:0); + (MAXIGP0ACLK => MAXIGP0ARADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLOCK[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLOCK[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARVALID) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLOCK[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLOCK[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWVALID) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0BREADY) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0RREADY) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WID[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WLAST) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLOCK[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLOCK[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLOCK[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLOCK[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1BREADY) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1RREADY) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WID[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WLAST) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WVALID) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPARREADY) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPAWREADY) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBRESP[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBRESP[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBVALID) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[10]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[11]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[12]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[13]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[14]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[15]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[16]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[17]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[18]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[19]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[20]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[21]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[22]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[23]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[24]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[25]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[26]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[27]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[28]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[29]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[30]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[31]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[32]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[33]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[34]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[35]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[36]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[37]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[38]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[39]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[3]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[40]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[41]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[42]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[43]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[44]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[45]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[46]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[47]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[48]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[49]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[4]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[50]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[51]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[52]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[53]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[54]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[55]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[56]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[57]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[58]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[59]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[5]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[60]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[61]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[62]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[63]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[6]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[7]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[8]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[9]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRLAST) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRRESP[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRRESP[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRVALID) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPWREADY) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0ARREADY) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0AWREADY) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[0]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[1]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[2]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[3]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[4]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BID[5]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0BVALID) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[0]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[1]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[2]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[3]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[4]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RID[5]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RLAST) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0RVALID) = (100:100:100, 100:100:100); + (SAXIGP0ACLK => SAXIGP0WREADY) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1ARREADY) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1AWREADY) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[0]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[1]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[2]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[3]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[4]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BID[5]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1BVALID) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[0]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[1]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[2]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[3]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[4]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RID[5]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RLAST) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1RVALID) = (100:100:100, 100:100:100); + (SAXIGP1ACLK => SAXIGP1WREADY) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0ARREADY) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0AWREADY) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BID[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0BVALID) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[10]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[11]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[12]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[13]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[14]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[15]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[16]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[17]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[18]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[19]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[20]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[21]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[22]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[23]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[24]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[25]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[26]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[27]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[28]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[29]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[30]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[31]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[32]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[33]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[34]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[35]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[36]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[37]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[38]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[39]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[40]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[41]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[42]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[43]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[44]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[45]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[46]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[47]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[48]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[49]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[50]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[51]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[52]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[53]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[54]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[55]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[56]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[57]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[58]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[59]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[60]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[61]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[62]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[63]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[6]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[7]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[8]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RDATA[9]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RID[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RLAST) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0RVALID) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WACOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP0ACLK => SAXIHP0WREADY) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1ARREADY) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1AWREADY) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BID[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1BVALID) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[10]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[11]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[12]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[13]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[14]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[15]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[16]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[17]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[18]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[19]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[20]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[21]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[22]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[23]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[24]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[25]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[26]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[27]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[28]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[29]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[30]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[31]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[32]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[33]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[34]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[35]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[36]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[37]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[38]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[39]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[40]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[41]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[42]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[43]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[44]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[45]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[46]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[47]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[48]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[49]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[50]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[51]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[52]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[53]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[54]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[55]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[56]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[57]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[58]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[59]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[60]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[61]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[62]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[63]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[6]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[7]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[8]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RDATA[9]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RID[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RLAST) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1RVALID) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WACOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP1ACLK => SAXIHP1WREADY) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2ARREADY) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2AWREADY) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BID[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2BVALID) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[10]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[11]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[12]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[13]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[14]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[15]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[16]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[17]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[18]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[19]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[20]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[21]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[22]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[23]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[24]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[25]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[26]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[27]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[28]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[29]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[30]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[31]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[32]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[33]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[34]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[35]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[36]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[37]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[38]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[39]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[40]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[41]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[42]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[43]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[44]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[45]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[46]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[47]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[48]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[49]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[50]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[51]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[52]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[53]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[54]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[55]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[56]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[57]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[58]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[59]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[60]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[61]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[62]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[63]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[6]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[7]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[8]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RDATA[9]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RID[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RLAST) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2RVALID) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WACOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP2ACLK => SAXIHP2WREADY) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3ARREADY) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3AWREADY) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BID[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3BVALID) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[10]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[11]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[12]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[13]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[14]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[15]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[16]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[17]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[18]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[19]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[20]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[21]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[22]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[23]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[24]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[25]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[26]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[27]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[28]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[29]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[30]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[31]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[32]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[33]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[34]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[35]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[36]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[37]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[38]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[39]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[40]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[41]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[42]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[43]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[44]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[45]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[46]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[47]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[48]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[49]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[50]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[51]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[52]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[53]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[54]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[55]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[56]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[57]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[58]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[59]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[60]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[61]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[62]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[63]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[6]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[7]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[8]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RDATA[9]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RID[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RLAST) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RRESP[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RRESP[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3RVALID) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WACOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIHP3ACLK => SAXIHP3WREADY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $setuphold (posedge DMA0ACLK, negedge DMA0DAREADY, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DAREADY_delay); + $setuphold (posedge DMA0ACLK, negedge DMA0DRLAST, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRLAST_delay); + $setuphold (posedge DMA0ACLK, negedge DMA0DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRTYPE_delay[0]); + $setuphold (posedge DMA0ACLK, negedge DMA0DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRTYPE_delay[1]); + $setuphold (posedge DMA0ACLK, negedge DMA0DRVALID, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRVALID_delay); + $setuphold (posedge DMA0ACLK, posedge DMA0DAREADY, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DAREADY_delay); + $setuphold (posedge DMA0ACLK, posedge DMA0DRLAST, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRLAST_delay); + $setuphold (posedge DMA0ACLK, posedge DMA0DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRTYPE_delay[0]); + $setuphold (posedge DMA0ACLK, posedge DMA0DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRTYPE_delay[1]); + $setuphold (posedge DMA0ACLK, posedge DMA0DRVALID, 0:0:0, 0:0:0, notifier, , , DMA0ACLK_delay, DMA0DRVALID_delay); + $setuphold (posedge DMA1ACLK, negedge DMA1DAREADY, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DAREADY_delay); + $setuphold (posedge DMA1ACLK, negedge DMA1DRLAST, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRLAST_delay); + $setuphold (posedge DMA1ACLK, negedge DMA1DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRTYPE_delay[0]); + $setuphold (posedge DMA1ACLK, negedge DMA1DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRTYPE_delay[1]); + $setuphold (posedge DMA1ACLK, negedge DMA1DRVALID, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRVALID_delay); + $setuphold (posedge DMA1ACLK, posedge DMA1DAREADY, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DAREADY_delay); + $setuphold (posedge DMA1ACLK, posedge DMA1DRLAST, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRLAST_delay); + $setuphold (posedge DMA1ACLK, posedge DMA1DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRTYPE_delay[0]); + $setuphold (posedge DMA1ACLK, posedge DMA1DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRTYPE_delay[1]); + $setuphold (posedge DMA1ACLK, posedge DMA1DRVALID, 0:0:0, 0:0:0, notifier, , , DMA1ACLK_delay, DMA1DRVALID_delay); + $setuphold (posedge DMA2ACLK, negedge DMA2DAREADY, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DAREADY_delay); + $setuphold (posedge DMA2ACLK, negedge DMA2DRLAST, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRLAST_delay); + $setuphold (posedge DMA2ACLK, negedge DMA2DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRTYPE_delay[0]); + $setuphold (posedge DMA2ACLK, negedge DMA2DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRTYPE_delay[1]); + $setuphold (posedge DMA2ACLK, negedge DMA2DRVALID, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRVALID_delay); + $setuphold (posedge DMA2ACLK, posedge DMA2DAREADY, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DAREADY_delay); + $setuphold (posedge DMA2ACLK, posedge DMA2DRLAST, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRLAST_delay); + $setuphold (posedge DMA2ACLK, posedge DMA2DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRTYPE_delay[0]); + $setuphold (posedge DMA2ACLK, posedge DMA2DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRTYPE_delay[1]); + $setuphold (posedge DMA2ACLK, posedge DMA2DRVALID, 0:0:0, 0:0:0, notifier, , , DMA2ACLK_delay, DMA2DRVALID_delay); + $setuphold (posedge DMA3ACLK, negedge DMA3DAREADY, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DAREADY_delay); + $setuphold (posedge DMA3ACLK, negedge DMA3DRLAST, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRLAST_delay); + $setuphold (posedge DMA3ACLK, negedge DMA3DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRTYPE_delay[0]); + $setuphold (posedge DMA3ACLK, negedge DMA3DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRTYPE_delay[1]); + $setuphold (posedge DMA3ACLK, negedge DMA3DRVALID, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRVALID_delay); + $setuphold (posedge DMA3ACLK, posedge DMA3DAREADY, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DAREADY_delay); + $setuphold (posedge DMA3ACLK, posedge DMA3DRLAST, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRLAST_delay); + $setuphold (posedge DMA3ACLK, posedge DMA3DRTYPE[0], 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRTYPE_delay[0]); + $setuphold (posedge DMA3ACLK, posedge DMA3DRTYPE[1], 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRTYPE_delay[1]); + $setuphold (posedge DMA3ACLK, posedge DMA3DRVALID, 0:0:0, 0:0:0, notifier, , , DMA3ACLK_delay, DMA3DRVALID_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXDV_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXER_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXDV_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXER_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXDV_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXER_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXDV_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXER_delay); + $setuphold (posedge EMIOPJTAGTCK, negedge EMIOPJTAGTDI, 0:0:0, 0:0:0, notifier, , , EMIOPJTAGTCK_delay, EMIOPJTAGTDI_delay); + $setuphold (posedge EMIOPJTAGTCK, negedge EMIOPJTAGTMS, 0:0:0, 0:0:0, notifier, , , EMIOPJTAGTCK_delay, EMIOPJTAGTMS_delay); + $setuphold (posedge EMIOPJTAGTCK, posedge EMIOPJTAGTDI, 0:0:0, 0:0:0, notifier, , , EMIOPJTAGTCK_delay, EMIOPJTAGTDI_delay); + $setuphold (posedge EMIOPJTAGTCK, posedge EMIOPJTAGTMS, 0:0:0, 0:0:0, notifier, , , EMIOPJTAGTCK_delay, EMIOPJTAGTMS_delay); + $setuphold (posedge EMIOSDIO0CLKFB, negedge EMIOSDIO0CMDI, 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0CMDI_delay); + $setuphold (posedge EMIOSDIO0CLKFB, negedge EMIOSDIO0DATAI[0], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[0]); + $setuphold (posedge EMIOSDIO0CLKFB, negedge EMIOSDIO0DATAI[1], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[1]); + $setuphold (posedge EMIOSDIO0CLKFB, negedge EMIOSDIO0DATAI[2], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[2]); + $setuphold (posedge EMIOSDIO0CLKFB, negedge EMIOSDIO0DATAI[3], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[3]); + $setuphold (posedge EMIOSDIO0CLKFB, posedge EMIOSDIO0CMDI, 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0CMDI_delay); + $setuphold (posedge EMIOSDIO0CLKFB, posedge EMIOSDIO0DATAI[0], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[0]); + $setuphold (posedge EMIOSDIO0CLKFB, posedge EMIOSDIO0DATAI[1], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[1]); + $setuphold (posedge EMIOSDIO0CLKFB, posedge EMIOSDIO0DATAI[2], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[2]); + $setuphold (posedge EMIOSDIO0CLKFB, posedge EMIOSDIO0DATAI[3], 0:0:0, 0:0:0, notifier, , , EMIOSDIO0CLKFB_delay, EMIOSDIO0DATAI_delay[3]); + $setuphold (posedge EMIOSDIO1CLKFB, negedge EMIOSDIO1CMDI, 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1CMDI_delay); + $setuphold (posedge EMIOSDIO1CLKFB, negedge EMIOSDIO1DATAI[0], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[0]); + $setuphold (posedge EMIOSDIO1CLKFB, negedge EMIOSDIO1DATAI[1], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[1]); + $setuphold (posedge EMIOSDIO1CLKFB, negedge EMIOSDIO1DATAI[2], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[2]); + $setuphold (posedge EMIOSDIO1CLKFB, negedge EMIOSDIO1DATAI[3], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[3]); + $setuphold (posedge EMIOSDIO1CLKFB, posedge EMIOSDIO1CMDI, 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1CMDI_delay); + $setuphold (posedge EMIOSDIO1CLKFB, posedge EMIOSDIO1DATAI[0], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[0]); + $setuphold (posedge EMIOSDIO1CLKFB, posedge EMIOSDIO1DATAI[1], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[1]); + $setuphold (posedge EMIOSDIO1CLKFB, posedge EMIOSDIO1DATAI[2], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[2]); + $setuphold (posedge EMIOSDIO1CLKFB, posedge EMIOSDIO1DATAI[3], 0:0:0, 0:0:0, notifier, , , EMIOSDIO1CLKFB_delay, EMIOSDIO1DATAI_delay[3]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINATID[0], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[0]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINATID[1], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[1]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINATID[2], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[2]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINATID[3], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[3]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[0], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[0]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[10], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[10]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[11], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[11]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[12], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[12]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[13], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[13]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[14], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[14]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[15], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[15]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[16], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[16]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[17], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[17]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[18], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[18]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[19], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[19]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[1], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[1]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[20], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[20]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[21], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[21]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[22], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[22]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[23], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[23]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[24], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[24]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[25], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[25]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[26], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[26]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[27], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[27]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[28], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[28]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[29], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[29]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[2], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[2]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[30], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[30]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[31], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[31]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[3], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[3]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[4], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[4]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[5], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[5]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[6], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[6]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[7], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[7]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[8], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[8]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINDATA[9], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[9]); + $setuphold (posedge FTMDTRACEINCLOCK, negedge FTMDTRACEINVALID, 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINVALID_delay); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINATID[0], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[0]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINATID[1], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[1]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINATID[2], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[2]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINATID[3], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINATID_delay[3]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[0], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[0]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[10], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[10]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[11], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[11]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[12], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[12]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[13], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[13]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[14], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[14]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[15], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[15]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[16], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[16]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[17], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[17]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[18], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[18]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[19], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[19]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[1], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[1]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[20], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[20]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[21], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[21]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[22], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[22]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[23], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[23]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[24], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[24]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[25], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[25]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[26], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[26]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[27], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[27]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[28], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[28]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[29], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[29]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[2], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[2]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[30], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[30]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[31], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[31]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[3], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[3]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[4], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[4]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[5], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[5]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[6], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[6]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[7], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[7]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[8], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[8]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINDATA[9], 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINDATA_delay[9]); + $setuphold (posedge FTMDTRACEINCLOCK, posedge FTMDTRACEINVALID, 0:0:0, 0:0:0, notifier, , , FTMDTRACEINCLOCK_delay, FTMDTRACEINVALID_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0ARREADY_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0AWREADY_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BVALID_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[12]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[13]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[14]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[15]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[16]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[17]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[18]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[19]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[20]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[21]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[22]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[23]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[24]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[25]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[26]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[27]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[28]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[29]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[30]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[31]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RLAST_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RVALID_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0WREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0ARREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0AWREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BVALID_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[12]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[13]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[14]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[15]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[16]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[17]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[18]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[19]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[20]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[21]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[22]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[23]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[24]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[25]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[26]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[27]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[28]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[29]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[30]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[31]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RLAST_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RVALID_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0WREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1ARREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1AWREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BVALID_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[12]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[13]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[14]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[15]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[16]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[17]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[18]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[19]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[20]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[21]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[22]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[23]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[24]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[25]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[26]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[27]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[28]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[29]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[30]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[31]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RLAST_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RVALID_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1WREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1ARREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1AWREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BVALID_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[12]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[13]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[14]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[15]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[16]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[17]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[18]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[19]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[20]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[21]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[22]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[23]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[24]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[25]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[26]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[27]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[28]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[29]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[30]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[31]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RLAST_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RVALID_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1WREADY_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARVALID_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWVALID_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPBREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPBREADY_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPRREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPRREADY_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[32]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[33]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[34]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[35]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[36]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[37]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[38]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[39]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[40]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[41]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[42]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[43]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[44]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[45]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[46]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[47]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[48]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[49]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[50]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[51]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[52]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[53]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[54]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[55]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[56]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[57]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[58]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[59]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[60]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[61]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[62]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[63]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWLAST, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWLAST_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPBREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPBREADY_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPRREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPRREADY_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[32]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[33]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[34]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[35]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[36]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[37]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[38]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[39]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[40]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[41]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[42]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[43]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[44]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[45]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[46]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[47]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[48]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[49]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[50]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[51]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[52]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[53]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[54]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[55]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[56]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[57]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[58]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[59]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[60]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[61]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[62]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[63]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWID_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWLAST, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWLAST_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWVALID_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[10]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[11]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[12]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[13]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[14]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[15]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[16]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[17]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[18]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[19]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[20]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[21]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[22]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[23]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[24]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[25]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[26]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[27]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[28]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[29]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[30]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[31]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[6]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[7]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[8]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[9]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARBURST_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARBURST_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLOCK_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLOCK_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARSIZE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARSIZE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARVALID_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[10]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[11]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[12]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[13]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[14]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[15]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[16]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[17]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[18]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[19]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[20]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[21]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[22]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[23]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[24]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[25]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[26]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[27]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[28]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[29]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[30]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[31]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[6]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[7]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[8]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[9]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWBURST_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWBURST_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLOCK_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLOCK_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWSIZE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWSIZE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWVALID_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0BREADY_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0RREADY_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[10]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[11]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[12]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[13]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[14]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[15]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[16]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[17]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[18]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[19]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[20]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[21]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[22]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[23]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[24]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[25]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[26]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[27]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[28]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[29]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[30]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[31]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[6]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[7]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[8]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[9]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WLAST_delay); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[0]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[1]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[2]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[3]); + $setuphold (posedge SAXIGP0ACLK, negedge SAXIGP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WVALID_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[10]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[11]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[12]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[13]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[14]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[15]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[16]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[17]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[18]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[19]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[20]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[21]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[22]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[23]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[24]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[25]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[26]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[27]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[28]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[29]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[30]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[31]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[6]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[7]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[8]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARADDR_delay[9]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARBURST_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARBURST_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARCACHE_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLEN_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLOCK_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARLOCK_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARPROT_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARQOS_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARSIZE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARSIZE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0ARVALID_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[10]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[11]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[12]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[13]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[14]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[15]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[16]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[17]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[18]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[19]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[20]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[21]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[22]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[23]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[24]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[25]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[26]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[27]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[28]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[29]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[30]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[31]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[6]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[7]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[8]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWADDR_delay[9]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWBURST_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWBURST_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWCACHE_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLEN_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLOCK_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWLOCK_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWPROT_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWQOS_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWSIZE_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWSIZE_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0AWVALID_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0BREADY_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0RREADY_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[10]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[11]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[12]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[13]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[14]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[15]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[16]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[17]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[18]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[19]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[20]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[21]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[22]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[23]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[24]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[25]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[26]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[27]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[28]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[29]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[30]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[31]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[6]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[7]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[8]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WDATA_delay[9]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[4]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WID_delay[5]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WLAST_delay); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[0]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[1]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[2]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WSTRB_delay[3]); + $setuphold (posedge SAXIGP0ACLK, posedge SAXIGP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0ACLK_delay, SAXIGP0WVALID_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[10]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[11]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[12]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[13]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[14]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[15]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[16]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[17]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[18]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[19]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[20]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[21]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[22]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[23]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[24]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[25]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[26]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[27]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[28]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[29]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[30]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[31]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[6]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[7]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[8]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[9]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARBURST_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARBURST_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLOCK_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLOCK_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARSIZE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARSIZE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARVALID_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[10]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[11]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[12]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[13]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[14]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[15]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[16]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[17]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[18]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[19]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[20]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[21]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[22]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[23]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[24]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[25]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[26]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[27]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[28]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[29]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[30]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[31]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[6]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[7]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[8]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[9]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWBURST_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWBURST_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLOCK_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLOCK_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWSIZE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWSIZE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWVALID_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1BREADY_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1RREADY_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[10]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[11]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[12]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[13]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[14]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[15]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[16]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[17]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[18]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[19]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[20]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[21]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[22]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[23]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[24]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[25]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[26]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[27]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[28]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[29]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[30]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[31]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[6]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[7]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[8]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[9]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WLAST_delay); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[0]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[1]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[2]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[3]); + $setuphold (posedge SAXIGP1ACLK, negedge SAXIGP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WVALID_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[10]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[11]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[12]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[13]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[14]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[15]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[16]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[17]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[18]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[19]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[20]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[21]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[22]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[23]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[24]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[25]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[26]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[27]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[28]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[29]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[30]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[31]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[6]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[7]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[8]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARADDR_delay[9]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARBURST_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARBURST_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARCACHE_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLEN_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLOCK_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARLOCK_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARPROT_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARQOS_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARSIZE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARSIZE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1ARVALID_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[10]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[11]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[12]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[13]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[14]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[15]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[16]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[17]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[18]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[19]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[20]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[21]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[22]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[23]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[24]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[25]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[26]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[27]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[28]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[29]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[30]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[31]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[6]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[7]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[8]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWADDR_delay[9]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWBURST_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWBURST_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWCACHE_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLEN_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLOCK_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWLOCK_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWPROT_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWQOS_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWSIZE_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWSIZE_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1AWVALID_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1BREADY_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1RREADY_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[10]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[11]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[12]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[13]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[14]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[15]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[16]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[17]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[18]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[19]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[20]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[21]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[22]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[23]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[24]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[25]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[26]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[27]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[28]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[29]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[30]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[31]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[6]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[7]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[8]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WDATA_delay[9]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[4]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WID_delay[5]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WLAST_delay); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[0]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[1]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[2]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WSTRB_delay[3]); + $setuphold (posedge SAXIGP1ACLK, posedge SAXIGP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1ACLK_delay, SAXIGP1WVALID_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[10]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[11]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[12]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[13]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[14]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[15]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[16]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[17]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[18]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[19]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[20]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[21]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[22]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[23]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[24]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[25]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[26]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[27]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[28]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[29]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[30]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[31]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[6]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[7]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[8]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[9]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARBURST_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARBURST_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLOCK_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLOCK_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARSIZE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARSIZE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARVALID_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[10]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[11]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[12]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[13]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[14]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[15]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[16]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[17]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[18]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[19]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[20]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[21]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[22]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[23]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[24]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[25]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[26]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[27]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[28]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[29]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[30]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[31]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[6]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[7]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[8]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[9]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWBURST_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWBURST_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLOCK_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLOCK_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWSIZE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWSIZE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWVALID_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0BREADY_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0RREADY_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[10]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[11]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[12]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[13]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[14]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[15]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[16]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[17]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[18]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[19]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[20]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[21]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[22]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[23]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[24]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[25]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[26]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[27]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[28]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[29]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[30]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[31]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[32]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[33]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[34]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[35]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[36]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[37]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[38]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[39]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[40]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[41]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[42]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[43]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[44]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[45]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[46]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[47]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[48]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[49]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[50]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[51]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[52]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[53]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[54]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[55]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[56]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[57]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[58]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[59]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[60]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[61]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[62]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[63]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[6]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[7]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[8]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[9]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WLAST_delay); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[0]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[1]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[2]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[3]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[4]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[5]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[6]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[7]); + $setuphold (posedge SAXIHP0ACLK, negedge SAXIHP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WVALID_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[10]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[11]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[12]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[13]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[14]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[15]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[16]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[17]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[18]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[19]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[20]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[21]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[22]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[23]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[24]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[25]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[26]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[27]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[28]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[29]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[30]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[31]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[6]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[7]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[8]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARADDR_delay[9]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARBURST_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARBURST_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARCACHE_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLEN_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLOCK_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARLOCK_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARPROT_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARQOS_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARSIZE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARSIZE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0ARVALID_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[10]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[11]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[12]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[13]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[14]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[15]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[16]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[17]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[18]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[19]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[20]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[21]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[22]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[23]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[24]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[25]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[26]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[27]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[28]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[29]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[30]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[31]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[6]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[7]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[8]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWADDR_delay[9]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWBURST_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWBURST_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWCACHE_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLEN_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLOCK_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWLOCK_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWPROT_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWQOS_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWSIZE_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWSIZE_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0AWVALID_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0BREADY_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0RREADY_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[10]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[11]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[12]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[13]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[14]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[15]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[16]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[17]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[18]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[19]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[20]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[21]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[22]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[23]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[24]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[25]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[26]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[27]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[28]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[29]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[30]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[31]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[32]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[33]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[34]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[35]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[36]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[37]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[38]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[39]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[40]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[41]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[42]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[43]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[44]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[45]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[46]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[47]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[48]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[49]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[50]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[51]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[52]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[53]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[54]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[55]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[56]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[57]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[58]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[59]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[60]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[61]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[62]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[63]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[6]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[7]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[8]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WDATA_delay[9]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WID_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WLAST_delay); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[0]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[1]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[2]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[3]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[4]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[5]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[6]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WSTRB_delay[7]); + $setuphold (posedge SAXIHP0ACLK, posedge SAXIHP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP0ACLK_delay, SAXIHP0WVALID_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[10]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[11]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[12]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[13]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[14]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[15]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[16]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[17]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[18]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[19]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[20]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[21]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[22]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[23]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[24]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[25]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[26]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[27]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[28]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[29]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[30]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[31]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[6]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[7]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[8]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[9]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARBURST_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARBURST_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLOCK_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLOCK_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARSIZE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARSIZE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARVALID_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[10]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[11]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[12]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[13]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[14]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[15]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[16]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[17]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[18]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[19]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[20]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[21]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[22]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[23]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[24]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[25]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[26]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[27]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[28]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[29]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[30]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[31]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[6]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[7]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[8]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[9]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWBURST_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWBURST_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLOCK_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLOCK_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWSIZE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWSIZE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWVALID_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1BREADY_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1RREADY_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[10]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[11]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[12]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[13]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[14]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[15]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[16]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[17]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[18]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[19]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[20]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[21]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[22]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[23]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[24]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[25]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[26]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[27]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[28]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[29]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[30]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[31]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[32]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[33]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[34]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[35]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[36]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[37]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[38]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[39]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[40]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[41]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[42]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[43]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[44]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[45]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[46]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[47]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[48]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[49]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[50]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[51]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[52]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[53]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[54]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[55]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[56]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[57]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[58]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[59]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[60]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[61]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[62]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[63]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[6]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[7]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[8]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[9]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WLAST_delay); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[0]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[1]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[2]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[3]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[4]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[5]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[6]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[7]); + $setuphold (posedge SAXIHP1ACLK, negedge SAXIHP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WVALID_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[10]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[11]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[12]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[13]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[14]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[15]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[16]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[17]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[18]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[19]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[20]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[21]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[22]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[23]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[24]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[25]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[26]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[27]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[28]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[29]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[30]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[31]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[6]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[7]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[8]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARADDR_delay[9]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARBURST_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARBURST_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARCACHE_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLEN_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLOCK_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARLOCK_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARPROT_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARQOS_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARSIZE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARSIZE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1ARVALID_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[10]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[11]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[12]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[13]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[14]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[15]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[16]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[17]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[18]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[19]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[20]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[21]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[22]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[23]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[24]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[25]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[26]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[27]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[28]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[29]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[30]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[31]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[6]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[7]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[8]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWADDR_delay[9]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWBURST_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWBURST_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWCACHE_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLEN_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLOCK_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWLOCK_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWPROT_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWQOS_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWSIZE_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWSIZE_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1AWVALID_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1BREADY_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1RREADY_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[10]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[11]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[12]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[13]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[14]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[15]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[16]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[17]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[18]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[19]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[20]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[21]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[22]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[23]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[24]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[25]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[26]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[27]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[28]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[29]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[30]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[31]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[32]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[33]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[34]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[35]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[36]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[37]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[38]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[39]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[40]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[41]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[42]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[43]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[44]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[45]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[46]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[47]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[48]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[49]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[50]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[51]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[52]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[53]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[54]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[55]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[56]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[57]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[58]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[59]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[60]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[61]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[62]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[63]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[6]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[7]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[8]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WDATA_delay[9]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WID_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WLAST_delay); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[0]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[1]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[2]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[3]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[4]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[5]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[6]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WSTRB_delay[7]); + $setuphold (posedge SAXIHP1ACLK, posedge SAXIHP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP1ACLK_delay, SAXIHP1WVALID_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[10]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[11]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[12]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[13]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[14]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[15]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[16]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[17]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[18]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[19]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[20]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[21]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[22]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[23]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[24]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[25]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[26]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[27]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[28]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[29]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[30]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[31]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[6]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[7]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[8]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[9]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARBURST_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARBURST_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLOCK_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLOCK_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARSIZE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARSIZE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARVALID_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[10]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[11]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[12]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[13]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[14]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[15]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[16]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[17]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[18]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[19]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[20]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[21]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[22]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[23]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[24]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[25]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[26]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[27]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[28]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[29]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[30]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[31]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[6]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[7]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[8]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[9]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWBURST_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWBURST_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLOCK_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLOCK_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWSIZE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWSIZE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWVALID_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2BREADY_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2RREADY_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[10]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[11]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[12]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[13]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[14]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[15]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[16]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[17]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[18]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[19]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[20]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[21]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[22]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[23]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[24]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[25]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[26]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[27]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[28]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[29]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[30]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[31]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[32]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[33]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[34]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[35]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[36]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[37]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[38]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[39]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[40]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[41]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[42]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[43]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[44]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[45]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[46]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[47]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[48]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[49]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[50]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[51]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[52]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[53]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[54]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[55]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[56]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[57]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[58]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[59]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[60]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[61]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[62]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[63]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[6]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[7]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[8]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[9]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WLAST_delay); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[0]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[1]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[2]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[3]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[4]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[5]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[6]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[7]); + $setuphold (posedge SAXIHP2ACLK, negedge SAXIHP2WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WVALID_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[10]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[11]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[12]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[13]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[14]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[15]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[16]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[17]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[18]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[19]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[20]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[21]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[22]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[23]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[24]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[25]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[26]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[27]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[28]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[29]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[30]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[31]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[6]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[7]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[8]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARADDR_delay[9]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARBURST_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARBURST_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARCACHE_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLEN_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLOCK_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARLOCK_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARPROT_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARQOS_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARSIZE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARSIZE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2ARVALID_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[10]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[11]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[12]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[13]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[14]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[15]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[16]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[17]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[18]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[19]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[20]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[21]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[22]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[23]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[24]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[25]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[26]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[27]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[28]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[29]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[30]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[31]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[6]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[7]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[8]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWADDR_delay[9]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWBURST_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWBURST_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWCACHE_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLEN_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLOCK_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWLOCK_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWPROT_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWQOS_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWSIZE_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWSIZE_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2AWVALID_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2BREADY_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2RREADY_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[10]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[11]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[12]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[13]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[14]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[15]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[16]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[17]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[18]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[19]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[20]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[21]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[22]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[23]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[24]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[25]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[26]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[27]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[28]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[29]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[30]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[31]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[32]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[33]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[34]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[35]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[36]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[37]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[38]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[39]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[40]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[41]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[42]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[43]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[44]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[45]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[46]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[47]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[48]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[49]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[50]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[51]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[52]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[53]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[54]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[55]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[56]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[57]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[58]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[59]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[60]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[61]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[62]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[63]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[6]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[7]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[8]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WDATA_delay[9]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WID_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WLAST_delay); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[0]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[1]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[2]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[3]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[4]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[5]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[6]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WSTRB_delay[7]); + $setuphold (posedge SAXIHP2ACLK, posedge SAXIHP2WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP2ACLK_delay, SAXIHP2WVALID_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[10]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[11]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[12]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[13]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[14]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[15]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[16]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[17]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[18]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[19]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[20]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[21]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[22]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[23]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[24]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[25]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[26]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[27]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[28]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[29]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[30]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[31]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[6]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[7]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[8]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[9]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARBURST_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARBURST_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLOCK_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLOCK_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARSIZE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARSIZE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARVALID_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[10]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[11]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[12]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[13]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[14]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[15]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[16]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[17]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[18]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[19]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[20]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[21]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[22]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[23]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[24]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[25]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[26]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[27]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[28]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[29]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[30]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[31]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[6]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[7]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[8]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[9]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWBURST_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWBURST_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLOCK_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLOCK_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWSIZE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWSIZE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWVALID_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3BREADY_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3RREADY_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[10]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[11]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[12]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[13]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[14]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[15]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[16]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[17]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[18]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[19]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[20]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[21]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[22]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[23]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[24]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[25]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[26]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[27]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[28]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[29]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[30]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[31]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[32]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[33]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[34]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[35]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[36]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[37]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[38]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[39]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[40]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[41]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[42]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[43]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[44]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[45]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[46]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[47]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[48]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[49]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[50]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[51]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[52]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[53]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[54]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[55]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[56]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[57]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[58]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[59]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[60]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[61]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[62]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[63]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[6]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[7]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[8]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[9]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WLAST_delay); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[0]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[1]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[2]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[3]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[4]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[5]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[6]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[7]); + $setuphold (posedge SAXIHP3ACLK, negedge SAXIHP3WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WVALID_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[10]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[11]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[12]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[13]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[14]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[15]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[16]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[17]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[18]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[19]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[20]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[21]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[22]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[23]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[24]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[25]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[26]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[27]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[28]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[29]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[30]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[31]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[6]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[7]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[8]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARADDR_delay[9]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARBURST_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARBURST_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARCACHE_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLEN_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLOCK_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARLOCK_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARPROT_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARQOS_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARSIZE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARSIZE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3ARVALID_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[10]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[11]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[12]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[13]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[14]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[15]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[16]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[17]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[18]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[19]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[20]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[21]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[22]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[23]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[24]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[25]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[26]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[27]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[28]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[29]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[30]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[31]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[6]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[7]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[8]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWADDR_delay[9]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWBURST_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWBURST_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWCACHE_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLEN_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLOCK[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLOCK_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWLOCK[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWLOCK_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWPROT_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWQOS_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWSIZE_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWSIZE_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3AWVALID_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3BREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3BREADY_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3RREADY, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3RREADY_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[10]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[11]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[12]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[13]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[14]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[15]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[16]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[17]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[18]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[19]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[20]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[21]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[22]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[23]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[24]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[25]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[26]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[27]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[28]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[29]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[30]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[31]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[32]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[33]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[34]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[35]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[36]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[37]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[38]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[39]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[40]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[41]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[42]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[43]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[44]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[45]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[46]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[47]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[48]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[49]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[50]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[51]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[52]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[53]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[54]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[55]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[56]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[57]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[58]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[59]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[60]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[61]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[62]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[63]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[6]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[7]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[8]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WDATA_delay[9]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WID[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WID_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WLAST, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WLAST_delay); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[0]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[1]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[2]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[3]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[4]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[5]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[6]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WSTRB_delay[7]); + $setuphold (posedge SAXIHP3ACLK, posedge SAXIHP3WVALID, 0:0:0, 0:0:0, notifier, , , SAXIHP3ACLK_delay, SAXIHP3WVALID_delay); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PS8.v b/verilog/src/unisims/PS8.v new file mode 100644 index 0000000..5db03a7 --- /dev/null +++ b/verilog/src/unisims/PS8.v @@ -0,0 +1,21982 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / PS8 +// /___/ /\ Filename : PS8.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module PS8 +`ifdef XIL_TIMING +#( + parameter LOC = "UNPLACED" +) +`endif +( + output [7:0] ADMA2PLCACK, + output [7:0] ADMA2PLTVLD, + output DPAUDIOREFCLK, + output DPAUXDATAOEN, + output DPAUXDATAOUT, + output DPLIVEVIDEODEOUT, + output [31:0] DPMAXISMIXEDAUDIOTDATA, + output DPMAXISMIXEDAUDIOTID, + output DPMAXISMIXEDAUDIOTVALID, + output DPSAXISAUDIOTREADY, + output DPVIDEOOUTHSYNC, + output [35:0] DPVIDEOOUTPIXEL1, + output DPVIDEOOUTVSYNC, + output DPVIDEOREFCLK, + output EMIOCAN0PHYTX, + output EMIOCAN1PHYTX, + output [1:0] EMIOENET0DMABUSWIDTH, + output EMIOENET0DMATXENDTOG, + output [93:0] EMIOENET0GEMTSUTIMERCNT, + output [7:0] EMIOENET0GMIITXD, + output EMIOENET0GMIITXEN, + output EMIOENET0GMIITXER, + output EMIOENET0MDIOMDC, + output EMIOENET0MDIOO, + output EMIOENET0MDIOTN, + output [7:0] EMIOENET0RXWDATA, + output EMIOENET0RXWEOP, + output EMIOENET0RXWERR, + output EMIOENET0RXWFLUSH, + output EMIOENET0RXWSOP, + output [44:0] EMIOENET0RXWSTATUS, + output EMIOENET0RXWWR, + output [2:0] EMIOENET0SPEEDMODE, + output EMIOENET0TXRRD, + output [3:0] EMIOENET0TXRSTATUS, + output [1:0] EMIOENET1DMABUSWIDTH, + output EMIOENET1DMATXENDTOG, + output [7:0] EMIOENET1GMIITXD, + output EMIOENET1GMIITXEN, + output EMIOENET1GMIITXER, + output EMIOENET1MDIOMDC, + output EMIOENET1MDIOO, + output EMIOENET1MDIOTN, + output [7:0] EMIOENET1RXWDATA, + output EMIOENET1RXWEOP, + output EMIOENET1RXWERR, + output EMIOENET1RXWFLUSH, + output EMIOENET1RXWSOP, + output [44:0] EMIOENET1RXWSTATUS, + output EMIOENET1RXWWR, + output [2:0] EMIOENET1SPEEDMODE, + output EMIOENET1TXRRD, + output [3:0] EMIOENET1TXRSTATUS, + output [1:0] EMIOENET2DMABUSWIDTH, + output EMIOENET2DMATXENDTOG, + output [7:0] EMIOENET2GMIITXD, + output EMIOENET2GMIITXEN, + output EMIOENET2GMIITXER, + output EMIOENET2MDIOMDC, + output EMIOENET2MDIOO, + output EMIOENET2MDIOTN, + output [7:0] EMIOENET2RXWDATA, + output EMIOENET2RXWEOP, + output EMIOENET2RXWERR, + output EMIOENET2RXWFLUSH, + output EMIOENET2RXWSOP, + output [44:0] EMIOENET2RXWSTATUS, + output EMIOENET2RXWWR, + output [2:0] EMIOENET2SPEEDMODE, + output EMIOENET2TXRRD, + output [3:0] EMIOENET2TXRSTATUS, + output [1:0] EMIOENET3DMABUSWIDTH, + output EMIOENET3DMATXENDTOG, + output [7:0] EMIOENET3GMIITXD, + output EMIOENET3GMIITXEN, + output EMIOENET3GMIITXER, + output EMIOENET3MDIOMDC, + output EMIOENET3MDIOO, + output EMIOENET3MDIOTN, + output [7:0] EMIOENET3RXWDATA, + output EMIOENET3RXWEOP, + output EMIOENET3RXWERR, + output EMIOENET3RXWFLUSH, + output EMIOENET3RXWSOP, + output [44:0] EMIOENET3RXWSTATUS, + output EMIOENET3RXWWR, + output [2:0] EMIOENET3SPEEDMODE, + output EMIOENET3TXRRD, + output [3:0] EMIOENET3TXRSTATUS, + output EMIOGEM0DELAYREQRX, + output EMIOGEM0DELAYREQTX, + output EMIOGEM0PDELAYREQRX, + output EMIOGEM0PDELAYREQTX, + output EMIOGEM0PDELAYRESPRX, + output EMIOGEM0PDELAYRESPTX, + output EMIOGEM0RXSOF, + output EMIOGEM0SYNCFRAMERX, + output EMIOGEM0SYNCFRAMETX, + output EMIOGEM0TSUTIMERCMPVAL, + output EMIOGEM0TXRFIXEDLAT, + output EMIOGEM0TXSOF, + output EMIOGEM1DELAYREQRX, + output EMIOGEM1DELAYREQTX, + output EMIOGEM1PDELAYREQRX, + output EMIOGEM1PDELAYREQTX, + output EMIOGEM1PDELAYRESPRX, + output EMIOGEM1PDELAYRESPTX, + output EMIOGEM1RXSOF, + output EMIOGEM1SYNCFRAMERX, + output EMIOGEM1SYNCFRAMETX, + output EMIOGEM1TSUTIMERCMPVAL, + output EMIOGEM1TXRFIXEDLAT, + output EMIOGEM1TXSOF, + output EMIOGEM2DELAYREQRX, + output EMIOGEM2DELAYREQTX, + output EMIOGEM2PDELAYREQRX, + output EMIOGEM2PDELAYREQTX, + output EMIOGEM2PDELAYRESPRX, + output EMIOGEM2PDELAYRESPTX, + output EMIOGEM2RXSOF, + output EMIOGEM2SYNCFRAMERX, + output EMIOGEM2SYNCFRAMETX, + output EMIOGEM2TSUTIMERCMPVAL, + output EMIOGEM2TXRFIXEDLAT, + output EMIOGEM2TXSOF, + output EMIOGEM3DELAYREQRX, + output EMIOGEM3DELAYREQTX, + output EMIOGEM3PDELAYREQRX, + output EMIOGEM3PDELAYREQTX, + output EMIOGEM3PDELAYRESPRX, + output EMIOGEM3PDELAYRESPTX, + output EMIOGEM3RXSOF, + output EMIOGEM3SYNCFRAMERX, + output EMIOGEM3SYNCFRAMETX, + output EMIOGEM3TSUTIMERCMPVAL, + output EMIOGEM3TXRFIXEDLAT, + output EMIOGEM3TXSOF, + output [95:0] EMIOGPIOO, + output [95:0] EMIOGPIOTN, + output EMIOI2C0SCLO, + output EMIOI2C0SCLTN, + output EMIOI2C0SDAO, + output EMIOI2C0SDATN, + output EMIOI2C1SCLO, + output EMIOI2C1SCLTN, + output EMIOI2C1SDAO, + output EMIOI2C1SDATN, + output EMIOSDIO0BUSPOWER, + output [2:0] EMIOSDIO0BUSVOLT, + output EMIOSDIO0CLKOUT, + output EMIOSDIO0CMDENA, + output EMIOSDIO0CMDOUT, + output [7:0] EMIOSDIO0DATAENA, + output [7:0] EMIOSDIO0DATAOUT, + output EMIOSDIO0LEDCONTROL, + output EMIOSDIO1BUSPOWER, + output [2:0] EMIOSDIO1BUSVOLT, + output EMIOSDIO1CLKOUT, + output EMIOSDIO1CMDENA, + output EMIOSDIO1CMDOUT, + output [7:0] EMIOSDIO1DATAENA, + output [7:0] EMIOSDIO1DATAOUT, + output EMIOSDIO1LEDCONTROL, + output EMIOSPI0MO, + output EMIOSPI0MOTN, + output EMIOSPI0SCLKO, + output EMIOSPI0SCLKTN, + output EMIOSPI0SO, + output EMIOSPI0SSNTN, + output [2:0] EMIOSPI0SSON, + output EMIOSPI0STN, + output EMIOSPI1MO, + output EMIOSPI1MOTN, + output EMIOSPI1SCLKO, + output EMIOSPI1SCLKTN, + output EMIOSPI1SO, + output EMIOSPI1SSNTN, + output [2:0] EMIOSPI1SSON, + output EMIOSPI1STN, + output [2:0] EMIOTTC0WAVEO, + output [2:0] EMIOTTC1WAVEO, + output [2:0] EMIOTTC2WAVEO, + output [2:0] EMIOTTC3WAVEO, + output EMIOU2DSPORTVBUSCTRLUSB30, + output EMIOU2DSPORTVBUSCTRLUSB31, + output EMIOU3DSPORTVBUSCTRLUSB30, + output EMIOU3DSPORTVBUSCTRLUSB31, + output EMIOUART0DTRN, + output EMIOUART0RTSN, + output EMIOUART0TX, + output EMIOUART1DTRN, + output EMIOUART1RTSN, + output EMIOUART1TX, + output EMIOWDT0RSTO, + output EMIOWDT1RSTO, + output FMIOGEM0FIFORXCLKTOPLBUFG, + output FMIOGEM0FIFOTXCLKTOPLBUFG, + output FMIOGEM1FIFORXCLKTOPLBUFG, + output FMIOGEM1FIFOTXCLKTOPLBUFG, + output FMIOGEM2FIFORXCLKTOPLBUFG, + output FMIOGEM2FIFOTXCLKTOPLBUFG, + output FMIOGEM3FIFORXCLKTOPLBUFG, + output FMIOGEM3FIFOTXCLKTOPLBUFG, + output FMIOGEMTSUCLKTOPLBUFG, + output [31:0] FTMGPO, + output [7:0] GDMA2PLCACK, + output [7:0] GDMA2PLTVLD, + output [39:0] MAXIGP0ARADDR, + output [1:0] MAXIGP0ARBURST, + output [3:0] MAXIGP0ARCACHE, + output [15:0] MAXIGP0ARID, + output [7:0] MAXIGP0ARLEN, + output MAXIGP0ARLOCK, + output [2:0] MAXIGP0ARPROT, + output [3:0] MAXIGP0ARQOS, + output [2:0] MAXIGP0ARSIZE, + output [15:0] MAXIGP0ARUSER, + output MAXIGP0ARVALID, + output [39:0] MAXIGP0AWADDR, + output [1:0] MAXIGP0AWBURST, + output [3:0] MAXIGP0AWCACHE, + output [15:0] MAXIGP0AWID, + output [7:0] MAXIGP0AWLEN, + output MAXIGP0AWLOCK, + output [2:0] MAXIGP0AWPROT, + output [3:0] MAXIGP0AWQOS, + output [2:0] MAXIGP0AWSIZE, + output [15:0] MAXIGP0AWUSER, + output MAXIGP0AWVALID, + output MAXIGP0BREADY, + output MAXIGP0RREADY, + output [127:0] MAXIGP0WDATA, + output MAXIGP0WLAST, + output [15:0] MAXIGP0WSTRB, + output MAXIGP0WVALID, + output [39:0] MAXIGP1ARADDR, + output [1:0] MAXIGP1ARBURST, + output [3:0] MAXIGP1ARCACHE, + output [15:0] MAXIGP1ARID, + output [7:0] MAXIGP1ARLEN, + output MAXIGP1ARLOCK, + output [2:0] MAXIGP1ARPROT, + output [3:0] MAXIGP1ARQOS, + output [2:0] MAXIGP1ARSIZE, + output [15:0] MAXIGP1ARUSER, + output MAXIGP1ARVALID, + output [39:0] MAXIGP1AWADDR, + output [1:0] MAXIGP1AWBURST, + output [3:0] MAXIGP1AWCACHE, + output [15:0] MAXIGP1AWID, + output [7:0] MAXIGP1AWLEN, + output MAXIGP1AWLOCK, + output [2:0] MAXIGP1AWPROT, + output [3:0] MAXIGP1AWQOS, + output [2:0] MAXIGP1AWSIZE, + output [15:0] MAXIGP1AWUSER, + output MAXIGP1AWVALID, + output MAXIGP1BREADY, + output MAXIGP1RREADY, + output [127:0] MAXIGP1WDATA, + output MAXIGP1WLAST, + output [15:0] MAXIGP1WSTRB, + output MAXIGP1WVALID, + output [39:0] MAXIGP2ARADDR, + output [1:0] MAXIGP2ARBURST, + output [3:0] MAXIGP2ARCACHE, + output [15:0] MAXIGP2ARID, + output [7:0] MAXIGP2ARLEN, + output MAXIGP2ARLOCK, + output [2:0] MAXIGP2ARPROT, + output [3:0] MAXIGP2ARQOS, + output [2:0] MAXIGP2ARSIZE, + output [15:0] MAXIGP2ARUSER, + output MAXIGP2ARVALID, + output [39:0] MAXIGP2AWADDR, + output [1:0] MAXIGP2AWBURST, + output [3:0] MAXIGP2AWCACHE, + output [15:0] MAXIGP2AWID, + output [7:0] MAXIGP2AWLEN, + output MAXIGP2AWLOCK, + output [2:0] MAXIGP2AWPROT, + output [3:0] MAXIGP2AWQOS, + output [2:0] MAXIGP2AWSIZE, + output [15:0] MAXIGP2AWUSER, + output MAXIGP2AWVALID, + output MAXIGP2BREADY, + output MAXIGP2RREADY, + output [127:0] MAXIGP2WDATA, + output MAXIGP2WLAST, + output [15:0] MAXIGP2WSTRB, + output MAXIGP2WVALID, + output OSCRTCCLK, + output [3:0] PLCLK, + output PMUAIBAFIFMFPDREQ, + output PMUAIBAFIFMLPDREQ, + output [46:0] PMUERRORTOPL, + output [31:0] PMUPLGPO, + output PSPLEVENTO, + output [63:0] PSPLIRQFPD, + output [99:0] PSPLIRQLPD, + output [3:0] PSPLSTANDBYWFE, + output [3:0] PSPLSTANDBYWFI, + output PSPLTRACECTL, + output [31:0] PSPLTRACEDATA, + output [3:0] PSPLTRIGACK, + output [3:0] PSPLTRIGGER, + output PSS_ALTO_CORE_PAD_MGTTXN0OUT, + output PSS_ALTO_CORE_PAD_MGTTXN1OUT, + output PSS_ALTO_CORE_PAD_MGTTXN2OUT, + output PSS_ALTO_CORE_PAD_MGTTXN3OUT, + output PSS_ALTO_CORE_PAD_MGTTXP0OUT, + output PSS_ALTO_CORE_PAD_MGTTXP1OUT, + output PSS_ALTO_CORE_PAD_MGTTXP2OUT, + output PSS_ALTO_CORE_PAD_MGTTXP3OUT, + output PSS_ALTO_CORE_PAD_PADO, + output RPUEVENTO0, + output RPUEVENTO1, + output [43:0] SACEFPDACADDR, + output [2:0] SACEFPDACPROT, + output [3:0] SACEFPDACSNOOP, + output SACEFPDACVALID, + output SACEFPDARREADY, + output SACEFPDAWREADY, + output [5:0] SACEFPDBID, + output [1:0] SACEFPDBRESP, + output SACEFPDBUSER, + output SACEFPDBVALID, + output SACEFPDCDREADY, + output SACEFPDCRREADY, + output [127:0] SACEFPDRDATA, + output [5:0] SACEFPDRID, + output SACEFPDRLAST, + output [3:0] SACEFPDRRESP, + output SACEFPDRUSER, + output SACEFPDRVALID, + output SACEFPDWREADY, + output SAXIACPARREADY, + output SAXIACPAWREADY, + output [4:0] SAXIACPBID, + output [1:0] SAXIACPBRESP, + output SAXIACPBVALID, + output [127:0] SAXIACPRDATA, + output [4:0] SAXIACPRID, + output SAXIACPRLAST, + output [1:0] SAXIACPRRESP, + output SAXIACPRVALID, + output SAXIACPWREADY, + output SAXIGP0ARREADY, + output SAXIGP0AWREADY, + output [5:0] SAXIGP0BID, + output [1:0] SAXIGP0BRESP, + output SAXIGP0BVALID, + output [3:0] SAXIGP0RACOUNT, + output [7:0] SAXIGP0RCOUNT, + output [127:0] SAXIGP0RDATA, + output [5:0] SAXIGP0RID, + output SAXIGP0RLAST, + output [1:0] SAXIGP0RRESP, + output SAXIGP0RVALID, + output [3:0] SAXIGP0WACOUNT, + output [7:0] SAXIGP0WCOUNT, + output SAXIGP0WREADY, + output SAXIGP1ARREADY, + output SAXIGP1AWREADY, + output [5:0] SAXIGP1BID, + output [1:0] SAXIGP1BRESP, + output SAXIGP1BVALID, + output [3:0] SAXIGP1RACOUNT, + output [7:0] SAXIGP1RCOUNT, + output [127:0] SAXIGP1RDATA, + output [5:0] SAXIGP1RID, + output SAXIGP1RLAST, + output [1:0] SAXIGP1RRESP, + output SAXIGP1RVALID, + output [3:0] SAXIGP1WACOUNT, + output [7:0] SAXIGP1WCOUNT, + output SAXIGP1WREADY, + output SAXIGP2ARREADY, + output SAXIGP2AWREADY, + output [5:0] SAXIGP2BID, + output [1:0] SAXIGP2BRESP, + output SAXIGP2BVALID, + output [3:0] SAXIGP2RACOUNT, + output [7:0] SAXIGP2RCOUNT, + output [127:0] SAXIGP2RDATA, + output [5:0] SAXIGP2RID, + output SAXIGP2RLAST, + output [1:0] SAXIGP2RRESP, + output SAXIGP2RVALID, + output [3:0] SAXIGP2WACOUNT, + output [7:0] SAXIGP2WCOUNT, + output SAXIGP2WREADY, + output SAXIGP3ARREADY, + output SAXIGP3AWREADY, + output [5:0] SAXIGP3BID, + output [1:0] SAXIGP3BRESP, + output SAXIGP3BVALID, + output [3:0] SAXIGP3RACOUNT, + output [7:0] SAXIGP3RCOUNT, + output [127:0] SAXIGP3RDATA, + output [5:0] SAXIGP3RID, + output SAXIGP3RLAST, + output [1:0] SAXIGP3RRESP, + output SAXIGP3RVALID, + output [3:0] SAXIGP3WACOUNT, + output [7:0] SAXIGP3WCOUNT, + output SAXIGP3WREADY, + output SAXIGP4ARREADY, + output SAXIGP4AWREADY, + output [5:0] SAXIGP4BID, + output [1:0] SAXIGP4BRESP, + output SAXIGP4BVALID, + output [3:0] SAXIGP4RACOUNT, + output [7:0] SAXIGP4RCOUNT, + output [127:0] SAXIGP4RDATA, + output [5:0] SAXIGP4RID, + output SAXIGP4RLAST, + output [1:0] SAXIGP4RRESP, + output SAXIGP4RVALID, + output [3:0] SAXIGP4WACOUNT, + output [7:0] SAXIGP4WCOUNT, + output SAXIGP4WREADY, + output SAXIGP5ARREADY, + output SAXIGP5AWREADY, + output [5:0] SAXIGP5BID, + output [1:0] SAXIGP5BRESP, + output SAXIGP5BVALID, + output [3:0] SAXIGP5RACOUNT, + output [7:0] SAXIGP5RCOUNT, + output [127:0] SAXIGP5RDATA, + output [5:0] SAXIGP5RID, + output SAXIGP5RLAST, + output [1:0] SAXIGP5RRESP, + output SAXIGP5RVALID, + output [3:0] SAXIGP5WACOUNT, + output [7:0] SAXIGP5WCOUNT, + output SAXIGP5WREADY, + output SAXIGP6ARREADY, + output SAXIGP6AWREADY, + output [5:0] SAXIGP6BID, + output [1:0] SAXIGP6BRESP, + output SAXIGP6BVALID, + output [3:0] SAXIGP6RACOUNT, + output [7:0] SAXIGP6RCOUNT, + output [127:0] SAXIGP6RDATA, + output [5:0] SAXIGP6RID, + output SAXIGP6RLAST, + output [1:0] SAXIGP6RRESP, + output SAXIGP6RVALID, + output [3:0] SAXIGP6WACOUNT, + output [7:0] SAXIGP6WCOUNT, + output SAXIGP6WREADY, + + inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE, + inout PSS_ALTO_CORE_PAD_CLK, + inout PSS_ALTO_CORE_PAD_DONEB, + inout [17:0] PSS_ALTO_CORE_PAD_DRAMA, + inout PSS_ALTO_CORE_PAD_DRAMACTN, + inout PSS_ALTO_CORE_PAD_DRAMALERTN, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN, + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM, + inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ, + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS, + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN, + inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT, + inout PSS_ALTO_CORE_PAD_DRAMPARITY, + inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN, + inout PSS_ALTO_CORE_PAD_ERROROUT, + inout PSS_ALTO_CORE_PAD_ERRORSTATUS, + inout PSS_ALTO_CORE_PAD_INITB, + inout PSS_ALTO_CORE_PAD_JTAGTCK, + inout PSS_ALTO_CORE_PAD_JTAGTDI, + inout PSS_ALTO_CORE_PAD_JTAGTDO, + inout PSS_ALTO_CORE_PAD_JTAGTMS, + inout [77:0] PSS_ALTO_CORE_PAD_MIO, + inout PSS_ALTO_CORE_PAD_PORB, + inout PSS_ALTO_CORE_PAD_PROGB, + inout PSS_ALTO_CORE_PAD_RCALIBINOUT, + inout PSS_ALTO_CORE_PAD_SRSTB, + inout PSS_ALTO_CORE_PAD_ZQ, + + input [7:0] ADMAFCICLK, + input AIBPMUAFIFMFPDACK, + input AIBPMUAFIFMLPDACK, + input DDRCEXTREFRESHRANK0REQ, + input DDRCEXTREFRESHRANK1REQ, + input DDRCREFRESHPLCLK, + input DPAUXDATAIN, + input DPEXTERNALCUSTOMEVENT1, + input DPEXTERNALCUSTOMEVENT2, + input DPEXTERNALVSYNCEVENT, + input DPHOTPLUGDETECT, + input [7:0] DPLIVEGFXALPHAIN, + input [35:0] DPLIVEGFXPIXEL1IN, + input DPLIVEVIDEOINDE, + input DPLIVEVIDEOINHSYNC, + input [35:0] DPLIVEVIDEOINPIXEL1, + input DPLIVEVIDEOINVSYNC, + input DPMAXISMIXEDAUDIOTREADY, + input DPSAXISAUDIOCLK, + input [31:0] DPSAXISAUDIOTDATA, + input DPSAXISAUDIOTID, + input DPSAXISAUDIOTVALID, + input DPVIDEOINCLK, + input EMIOCAN0PHYRX, + input EMIOCAN1PHYRX, + input EMIOENET0DMATXSTATUSTOG, + input EMIOENET0EXTINTIN, + input EMIOENET0GMIICOL, + input EMIOENET0GMIICRS, + input EMIOENET0GMIIRXCLK, + input [7:0] EMIOENET0GMIIRXD, + input EMIOENET0GMIIRXDV, + input EMIOENET0GMIIRXER, + input EMIOENET0GMIITXCLK, + input EMIOENET0MDIOI, + input EMIOENET0RXWOVERFLOW, + input EMIOENET0TXRCONTROL, + input [7:0] EMIOENET0TXRDATA, + input EMIOENET0TXRDATARDY, + input EMIOENET0TXREOP, + input EMIOENET0TXRERR, + input EMIOENET0TXRFLUSHED, + input EMIOENET0TXRSOP, + input EMIOENET0TXRUNDERFLOW, + input EMIOENET0TXRVALID, + input EMIOENET1DMATXSTATUSTOG, + input EMIOENET1EXTINTIN, + input EMIOENET1GMIICOL, + input EMIOENET1GMIICRS, + input EMIOENET1GMIIRXCLK, + input [7:0] EMIOENET1GMIIRXD, + input EMIOENET1GMIIRXDV, + input EMIOENET1GMIIRXER, + input EMIOENET1GMIITXCLK, + input EMIOENET1MDIOI, + input EMIOENET1RXWOVERFLOW, + input EMIOENET1TXRCONTROL, + input [7:0] EMIOENET1TXRDATA, + input EMIOENET1TXRDATARDY, + input EMIOENET1TXREOP, + input EMIOENET1TXRERR, + input EMIOENET1TXRFLUSHED, + input EMIOENET1TXRSOP, + input EMIOENET1TXRUNDERFLOW, + input EMIOENET1TXRVALID, + input EMIOENET2DMATXSTATUSTOG, + input EMIOENET2EXTINTIN, + input EMIOENET2GMIICOL, + input EMIOENET2GMIICRS, + input EMIOENET2GMIIRXCLK, + input [7:0] EMIOENET2GMIIRXD, + input EMIOENET2GMIIRXDV, + input EMIOENET2GMIIRXER, + input EMIOENET2GMIITXCLK, + input EMIOENET2MDIOI, + input EMIOENET2RXWOVERFLOW, + input EMIOENET2TXRCONTROL, + input [7:0] EMIOENET2TXRDATA, + input EMIOENET2TXRDATARDY, + input EMIOENET2TXREOP, + input EMIOENET2TXRERR, + input EMIOENET2TXRFLUSHED, + input EMIOENET2TXRSOP, + input EMIOENET2TXRUNDERFLOW, + input EMIOENET2TXRVALID, + input EMIOENET3DMATXSTATUSTOG, + input EMIOENET3EXTINTIN, + input EMIOENET3GMIICOL, + input EMIOENET3GMIICRS, + input EMIOENET3GMIIRXCLK, + input [7:0] EMIOENET3GMIIRXD, + input EMIOENET3GMIIRXDV, + input EMIOENET3GMIIRXER, + input EMIOENET3GMIITXCLK, + input EMIOENET3MDIOI, + input EMIOENET3RXWOVERFLOW, + input EMIOENET3TXRCONTROL, + input [7:0] EMIOENET3TXRDATA, + input EMIOENET3TXRDATARDY, + input EMIOENET3TXREOP, + input EMIOENET3TXRERR, + input EMIOENET3TXRFLUSHED, + input EMIOENET3TXRSOP, + input EMIOENET3TXRUNDERFLOW, + input EMIOENET3TXRVALID, + input EMIOENETTSUCLK, + input [1:0] EMIOGEM0TSUINCCTRL, + input [1:0] EMIOGEM1TSUINCCTRL, + input [1:0] EMIOGEM2TSUINCCTRL, + input [1:0] EMIOGEM3TSUINCCTRL, + input [95:0] EMIOGPIOI, + input EMIOHUBPORTOVERCRNTUSB20, + input EMIOHUBPORTOVERCRNTUSB21, + input EMIOHUBPORTOVERCRNTUSB30, + input EMIOHUBPORTOVERCRNTUSB31, + input EMIOI2C0SCLI, + input EMIOI2C0SDAI, + input EMIOI2C1SCLI, + input EMIOI2C1SDAI, + input EMIOSDIO0CDN, + input EMIOSDIO0CMDIN, + input [7:0] EMIOSDIO0DATAIN, + input EMIOSDIO0FBCLKIN, + input EMIOSDIO0WP, + input EMIOSDIO1CDN, + input EMIOSDIO1CMDIN, + input [7:0] EMIOSDIO1DATAIN, + input EMIOSDIO1FBCLKIN, + input EMIOSDIO1WP, + input EMIOSPI0MI, + input EMIOSPI0SCLKI, + input EMIOSPI0SI, + input EMIOSPI0SSIN, + input EMIOSPI1MI, + input EMIOSPI1SCLKI, + input EMIOSPI1SI, + input EMIOSPI1SSIN, + input [2:0] EMIOTTC0CLKI, + input [2:0] EMIOTTC1CLKI, + input [2:0] EMIOTTC2CLKI, + input [2:0] EMIOTTC3CLKI, + input EMIOUART0CTSN, + input EMIOUART0DCDN, + input EMIOUART0DSRN, + input EMIOUART0RIN, + input EMIOUART0RX, + input EMIOUART1CTSN, + input EMIOUART1DCDN, + input EMIOUART1DSRN, + input EMIOUART1RIN, + input EMIOUART1RX, + input EMIOWDT0CLKI, + input EMIOWDT1CLKI, + input FMIOGEM0FIFORXCLKFROMPL, + input FMIOGEM0FIFOTXCLKFROMPL, + input FMIOGEM0SIGNALDETECT, + input FMIOGEM1FIFORXCLKFROMPL, + input FMIOGEM1FIFOTXCLKFROMPL, + input FMIOGEM1SIGNALDETECT, + input FMIOGEM2FIFORXCLKFROMPL, + input FMIOGEM2FIFOTXCLKFROMPL, + input FMIOGEM2SIGNALDETECT, + input FMIOGEM3FIFORXCLKFROMPL, + input FMIOGEM3FIFOTXCLKFROMPL, + input FMIOGEM3SIGNALDETECT, + input FMIOGEMTSUCLKFROMPL, + input [31:0] FTMGPI, + input [7:0] GDMAFCICLK, + input MAXIGP0ACLK, + input MAXIGP0ARREADY, + input MAXIGP0AWREADY, + input [15:0] MAXIGP0BID, + input [1:0] MAXIGP0BRESP, + input MAXIGP0BVALID, + input [127:0] MAXIGP0RDATA, + input [15:0] MAXIGP0RID, + input MAXIGP0RLAST, + input [1:0] MAXIGP0RRESP, + input MAXIGP0RVALID, + input MAXIGP0WREADY, + input MAXIGP1ACLK, + input MAXIGP1ARREADY, + input MAXIGP1AWREADY, + input [15:0] MAXIGP1BID, + input [1:0] MAXIGP1BRESP, + input MAXIGP1BVALID, + input [127:0] MAXIGP1RDATA, + input [15:0] MAXIGP1RID, + input MAXIGP1RLAST, + input [1:0] MAXIGP1RRESP, + input MAXIGP1RVALID, + input MAXIGP1WREADY, + input MAXIGP2ACLK, + input MAXIGP2ARREADY, + input MAXIGP2AWREADY, + input [15:0] MAXIGP2BID, + input [1:0] MAXIGP2BRESP, + input MAXIGP2BVALID, + input [127:0] MAXIGP2RDATA, + input [15:0] MAXIGP2RID, + input MAXIGP2RLAST, + input [1:0] MAXIGP2RRESP, + input MAXIGP2RVALID, + input MAXIGP2WREADY, + input NFIQ0LPDRPU, + input NFIQ1LPDRPU, + input NIRQ0LPDRPU, + input NIRQ1LPDRPU, + input [7:0] PL2ADMACVLD, + input [7:0] PL2ADMATACK, + input [7:0] PL2GDMACVLD, + input [7:0] PL2GDMATACK, + input PLACECLK, + input PLACPINACT, + input [3:0] PLFPGASTOP, + input [2:0] PLLAUXREFCLKFPD, + input [1:0] PLLAUXREFCLKLPD, + input [31:0] PLPMUGPI, + input [3:0] PLPSAPUGICFIQ, + input [3:0] PLPSAPUGICIRQ, + input PLPSEVENTI, + input [7:0] PLPSIRQ0, + input [7:0] PLPSIRQ1, + input PLPSTRACECLK, + input [3:0] PLPSTRIGACK, + input [3:0] PLPSTRIGGER, + input [3:0] PMUERRORFROMPL, + input PSS_ALTO_CORE_PAD_MGTRXN0IN, + input PSS_ALTO_CORE_PAD_MGTRXN1IN, + input PSS_ALTO_CORE_PAD_MGTRXN2IN, + input PSS_ALTO_CORE_PAD_MGTRXN3IN, + input PSS_ALTO_CORE_PAD_MGTRXP0IN, + input PSS_ALTO_CORE_PAD_MGTRXP1IN, + input PSS_ALTO_CORE_PAD_MGTRXP2IN, + input PSS_ALTO_CORE_PAD_MGTRXP3IN, + input PSS_ALTO_CORE_PAD_PADI, + input PSS_ALTO_CORE_PAD_REFN0IN, + input PSS_ALTO_CORE_PAD_REFN1IN, + input PSS_ALTO_CORE_PAD_REFN2IN, + input PSS_ALTO_CORE_PAD_REFN3IN, + input PSS_ALTO_CORE_PAD_REFP0IN, + input PSS_ALTO_CORE_PAD_REFP1IN, + input PSS_ALTO_CORE_PAD_REFP2IN, + input PSS_ALTO_CORE_PAD_REFP3IN, + input RPUEVENTI0, + input RPUEVENTI1, + input SACEFPDACREADY, + input [43:0] SACEFPDARADDR, + input [1:0] SACEFPDARBAR, + input [1:0] SACEFPDARBURST, + input [3:0] SACEFPDARCACHE, + input [1:0] SACEFPDARDOMAIN, + input [5:0] SACEFPDARID, + input [7:0] SACEFPDARLEN, + input SACEFPDARLOCK, + input [2:0] SACEFPDARPROT, + input [3:0] SACEFPDARQOS, + input [3:0] SACEFPDARREGION, + input [2:0] SACEFPDARSIZE, + input [3:0] SACEFPDARSNOOP, + input [15:0] SACEFPDARUSER, + input SACEFPDARVALID, + input [43:0] SACEFPDAWADDR, + input [1:0] SACEFPDAWBAR, + input [1:0] SACEFPDAWBURST, + input [3:0] SACEFPDAWCACHE, + input [1:0] SACEFPDAWDOMAIN, + input [5:0] SACEFPDAWID, + input [7:0] SACEFPDAWLEN, + input SACEFPDAWLOCK, + input [2:0] SACEFPDAWPROT, + input [3:0] SACEFPDAWQOS, + input [3:0] SACEFPDAWREGION, + input [2:0] SACEFPDAWSIZE, + input [2:0] SACEFPDAWSNOOP, + input [15:0] SACEFPDAWUSER, + input SACEFPDAWVALID, + input SACEFPDBREADY, + input [127:0] SACEFPDCDDATA, + input SACEFPDCDLAST, + input SACEFPDCDVALID, + input [4:0] SACEFPDCRRESP, + input SACEFPDCRVALID, + input SACEFPDRACK, + input SACEFPDRREADY, + input SACEFPDWACK, + input [127:0] SACEFPDWDATA, + input SACEFPDWLAST, + input [15:0] SACEFPDWSTRB, + input SACEFPDWUSER, + input SACEFPDWVALID, + input SAXIACPACLK, + input [39:0] SAXIACPARADDR, + input [1:0] SAXIACPARBURST, + input [3:0] SAXIACPARCACHE, + input [4:0] SAXIACPARID, + input [7:0] SAXIACPARLEN, + input SAXIACPARLOCK, + input [2:0] SAXIACPARPROT, + input [3:0] SAXIACPARQOS, + input [2:0] SAXIACPARSIZE, + input [1:0] SAXIACPARUSER, + input SAXIACPARVALID, + input [39:0] SAXIACPAWADDR, + input [1:0] SAXIACPAWBURST, + input [3:0] SAXIACPAWCACHE, + input [4:0] SAXIACPAWID, + input [7:0] SAXIACPAWLEN, + input SAXIACPAWLOCK, + input [2:0] SAXIACPAWPROT, + input [3:0] SAXIACPAWQOS, + input [2:0] SAXIACPAWSIZE, + input [1:0] SAXIACPAWUSER, + input SAXIACPAWVALID, + input SAXIACPBREADY, + input SAXIACPRREADY, + input [127:0] SAXIACPWDATA, + input SAXIACPWLAST, + input [15:0] SAXIACPWSTRB, + input SAXIACPWVALID, + input [48:0] SAXIGP0ARADDR, + input [1:0] SAXIGP0ARBURST, + input [3:0] SAXIGP0ARCACHE, + input [5:0] SAXIGP0ARID, + input [7:0] SAXIGP0ARLEN, + input SAXIGP0ARLOCK, + input [2:0] SAXIGP0ARPROT, + input [3:0] SAXIGP0ARQOS, + input [2:0] SAXIGP0ARSIZE, + input SAXIGP0ARUSER, + input SAXIGP0ARVALID, + input [48:0] SAXIGP0AWADDR, + input [1:0] SAXIGP0AWBURST, + input [3:0] SAXIGP0AWCACHE, + input [5:0] SAXIGP0AWID, + input [7:0] SAXIGP0AWLEN, + input SAXIGP0AWLOCK, + input [2:0] SAXIGP0AWPROT, + input [3:0] SAXIGP0AWQOS, + input [2:0] SAXIGP0AWSIZE, + input SAXIGP0AWUSER, + input SAXIGP0AWVALID, + input SAXIGP0BREADY, + input SAXIGP0RCLK, + input SAXIGP0RREADY, + input SAXIGP0WCLK, + input [127:0] SAXIGP0WDATA, + input SAXIGP0WLAST, + input [15:0] SAXIGP0WSTRB, + input SAXIGP0WVALID, + input [48:0] SAXIGP1ARADDR, + input [1:0] SAXIGP1ARBURST, + input [3:0] SAXIGP1ARCACHE, + input [5:0] SAXIGP1ARID, + input [7:0] SAXIGP1ARLEN, + input SAXIGP1ARLOCK, + input [2:0] SAXIGP1ARPROT, + input [3:0] SAXIGP1ARQOS, + input [2:0] SAXIGP1ARSIZE, + input SAXIGP1ARUSER, + input SAXIGP1ARVALID, + input [48:0] SAXIGP1AWADDR, + input [1:0] SAXIGP1AWBURST, + input [3:0] SAXIGP1AWCACHE, + input [5:0] SAXIGP1AWID, + input [7:0] SAXIGP1AWLEN, + input SAXIGP1AWLOCK, + input [2:0] SAXIGP1AWPROT, + input [3:0] SAXIGP1AWQOS, + input [2:0] SAXIGP1AWSIZE, + input SAXIGP1AWUSER, + input SAXIGP1AWVALID, + input SAXIGP1BREADY, + input SAXIGP1RCLK, + input SAXIGP1RREADY, + input SAXIGP1WCLK, + input [127:0] SAXIGP1WDATA, + input SAXIGP1WLAST, + input [15:0] SAXIGP1WSTRB, + input SAXIGP1WVALID, + input [48:0] SAXIGP2ARADDR, + input [1:0] SAXIGP2ARBURST, + input [3:0] SAXIGP2ARCACHE, + input [5:0] SAXIGP2ARID, + input [7:0] SAXIGP2ARLEN, + input SAXIGP2ARLOCK, + input [2:0] SAXIGP2ARPROT, + input [3:0] SAXIGP2ARQOS, + input [2:0] SAXIGP2ARSIZE, + input SAXIGP2ARUSER, + input SAXIGP2ARVALID, + input [48:0] SAXIGP2AWADDR, + input [1:0] SAXIGP2AWBURST, + input [3:0] SAXIGP2AWCACHE, + input [5:0] SAXIGP2AWID, + input [7:0] SAXIGP2AWLEN, + input SAXIGP2AWLOCK, + input [2:0] SAXIGP2AWPROT, + input [3:0] SAXIGP2AWQOS, + input [2:0] SAXIGP2AWSIZE, + input SAXIGP2AWUSER, + input SAXIGP2AWVALID, + input SAXIGP2BREADY, + input SAXIGP2RCLK, + input SAXIGP2RREADY, + input SAXIGP2WCLK, + input [127:0] SAXIGP2WDATA, + input SAXIGP2WLAST, + input [15:0] SAXIGP2WSTRB, + input SAXIGP2WVALID, + input [48:0] SAXIGP3ARADDR, + input [1:0] SAXIGP3ARBURST, + input [3:0] SAXIGP3ARCACHE, + input [5:0] SAXIGP3ARID, + input [7:0] SAXIGP3ARLEN, + input SAXIGP3ARLOCK, + input [2:0] SAXIGP3ARPROT, + input [3:0] SAXIGP3ARQOS, + input [2:0] SAXIGP3ARSIZE, + input SAXIGP3ARUSER, + input SAXIGP3ARVALID, + input [48:0] SAXIGP3AWADDR, + input [1:0] SAXIGP3AWBURST, + input [3:0] SAXIGP3AWCACHE, + input [5:0] SAXIGP3AWID, + input [7:0] SAXIGP3AWLEN, + input SAXIGP3AWLOCK, + input [2:0] SAXIGP3AWPROT, + input [3:0] SAXIGP3AWQOS, + input [2:0] SAXIGP3AWSIZE, + input SAXIGP3AWUSER, + input SAXIGP3AWVALID, + input SAXIGP3BREADY, + input SAXIGP3RCLK, + input SAXIGP3RREADY, + input SAXIGP3WCLK, + input [127:0] SAXIGP3WDATA, + input SAXIGP3WLAST, + input [15:0] SAXIGP3WSTRB, + input SAXIGP3WVALID, + input [48:0] SAXIGP4ARADDR, + input [1:0] SAXIGP4ARBURST, + input [3:0] SAXIGP4ARCACHE, + input [5:0] SAXIGP4ARID, + input [7:0] SAXIGP4ARLEN, + input SAXIGP4ARLOCK, + input [2:0] SAXIGP4ARPROT, + input [3:0] SAXIGP4ARQOS, + input [2:0] SAXIGP4ARSIZE, + input SAXIGP4ARUSER, + input SAXIGP4ARVALID, + input [48:0] SAXIGP4AWADDR, + input [1:0] SAXIGP4AWBURST, + input [3:0] SAXIGP4AWCACHE, + input [5:0] SAXIGP4AWID, + input [7:0] SAXIGP4AWLEN, + input SAXIGP4AWLOCK, + input [2:0] SAXIGP4AWPROT, + input [3:0] SAXIGP4AWQOS, + input [2:0] SAXIGP4AWSIZE, + input SAXIGP4AWUSER, + input SAXIGP4AWVALID, + input SAXIGP4BREADY, + input SAXIGP4RCLK, + input SAXIGP4RREADY, + input SAXIGP4WCLK, + input [127:0] SAXIGP4WDATA, + input SAXIGP4WLAST, + input [15:0] SAXIGP4WSTRB, + input SAXIGP4WVALID, + input [48:0] SAXIGP5ARADDR, + input [1:0] SAXIGP5ARBURST, + input [3:0] SAXIGP5ARCACHE, + input [5:0] SAXIGP5ARID, + input [7:0] SAXIGP5ARLEN, + input SAXIGP5ARLOCK, + input [2:0] SAXIGP5ARPROT, + input [3:0] SAXIGP5ARQOS, + input [2:0] SAXIGP5ARSIZE, + input SAXIGP5ARUSER, + input SAXIGP5ARVALID, + input [48:0] SAXIGP5AWADDR, + input [1:0] SAXIGP5AWBURST, + input [3:0] SAXIGP5AWCACHE, + input [5:0] SAXIGP5AWID, + input [7:0] SAXIGP5AWLEN, + input SAXIGP5AWLOCK, + input [2:0] SAXIGP5AWPROT, + input [3:0] SAXIGP5AWQOS, + input [2:0] SAXIGP5AWSIZE, + input SAXIGP5AWUSER, + input SAXIGP5AWVALID, + input SAXIGP5BREADY, + input SAXIGP5RCLK, + input SAXIGP5RREADY, + input SAXIGP5WCLK, + input [127:0] SAXIGP5WDATA, + input SAXIGP5WLAST, + input [15:0] SAXIGP5WSTRB, + input SAXIGP5WVALID, + input [48:0] SAXIGP6ARADDR, + input [1:0] SAXIGP6ARBURST, + input [3:0] SAXIGP6ARCACHE, + input [5:0] SAXIGP6ARID, + input [7:0] SAXIGP6ARLEN, + input SAXIGP6ARLOCK, + input [2:0] SAXIGP6ARPROT, + input [3:0] SAXIGP6ARQOS, + input [2:0] SAXIGP6ARSIZE, + input SAXIGP6ARUSER, + input SAXIGP6ARVALID, + input [48:0] SAXIGP6AWADDR, + input [1:0] SAXIGP6AWBURST, + input [3:0] SAXIGP6AWCACHE, + input [5:0] SAXIGP6AWID, + input [7:0] SAXIGP6AWLEN, + input SAXIGP6AWLOCK, + input [2:0] SAXIGP6AWPROT, + input [3:0] SAXIGP6AWQOS, + input [2:0] SAXIGP6AWSIZE, + input SAXIGP6AWUSER, + input SAXIGP6AWVALID, + input SAXIGP6BREADY, + input SAXIGP6RCLK, + input SAXIGP6RREADY, + input SAXIGP6WCLK, + input [127:0] SAXIGP6WDATA, + input SAXIGP6WLAST, + input [15:0] SAXIGP6WSTRB, + input SAXIGP6WVALID, + input [59:0] STMEVENT +); + +// define constants + localparam MODULE_NAME = "PS8"; + + tri0 glblGSR = glbl.GSR; + + wire DPAUDIOREFCLK_out; + wire DPAUXDATAOEN_out; + wire DPAUXDATAOUT_out; + wire DPLIVEVIDEODEOUT_out; + wire DPMAXISMIXEDAUDIOTID_out; + wire DPMAXISMIXEDAUDIOTVALID_out; + wire DPSAXISAUDIOTREADY_out; + wire DPVIDEOOUTHSYNC_out; + wire DPVIDEOOUTVSYNC_out; + wire DPVIDEOREFCLK_out; + wire EMIOCAN0PHYTX_out; + wire EMIOCAN1PHYTX_out; + wire EMIOENET0DMATXENDTOG_out; + wire EMIOENET0GMIITXEN_out; + wire EMIOENET0GMIITXER_out; + wire EMIOENET0MDIOMDC_out; + wire EMIOENET0MDIOO_out; + wire EMIOENET0MDIOTN_out; + wire EMIOENET0RXWEOP_out; + wire EMIOENET0RXWERR_out; + wire EMIOENET0RXWFLUSH_out; + wire EMIOENET0RXWSOP_out; + wire EMIOENET0RXWWR_out; + wire EMIOENET0TXRRD_out; + wire EMIOENET1DMATXENDTOG_out; + wire EMIOENET1GMIITXEN_out; + wire EMIOENET1GMIITXER_out; + wire EMIOENET1MDIOMDC_out; + wire EMIOENET1MDIOO_out; + wire EMIOENET1MDIOTN_out; + wire EMIOENET1RXWEOP_out; + wire EMIOENET1RXWERR_out; + wire EMIOENET1RXWFLUSH_out; + wire EMIOENET1RXWSOP_out; + wire EMIOENET1RXWWR_out; + wire EMIOENET1TXRRD_out; + wire EMIOENET2DMATXENDTOG_out; + wire EMIOENET2GMIITXEN_out; + wire EMIOENET2GMIITXER_out; + wire EMIOENET2MDIOMDC_out; + wire EMIOENET2MDIOO_out; + wire EMIOENET2MDIOTN_out; + wire EMIOENET2RXWEOP_out; + wire EMIOENET2RXWERR_out; + wire EMIOENET2RXWFLUSH_out; + wire EMIOENET2RXWSOP_out; + wire EMIOENET2RXWWR_out; + wire EMIOENET2TXRRD_out; + wire EMIOENET3DMATXENDTOG_out; + wire EMIOENET3GMIITXEN_out; + wire EMIOENET3GMIITXER_out; + wire EMIOENET3MDIOMDC_out; + wire EMIOENET3MDIOO_out; + wire EMIOENET3MDIOTN_out; + wire EMIOENET3RXWEOP_out; + wire EMIOENET3RXWERR_out; + wire EMIOENET3RXWFLUSH_out; + wire EMIOENET3RXWSOP_out; + wire EMIOENET3RXWWR_out; + wire EMIOENET3TXRRD_out; + wire EMIOGEM0DELAYREQRX_out; + wire EMIOGEM0DELAYREQTX_out; + wire EMIOGEM0PDELAYREQRX_out; + wire EMIOGEM0PDELAYREQTX_out; + wire EMIOGEM0PDELAYRESPRX_out; + wire EMIOGEM0PDELAYRESPTX_out; + wire EMIOGEM0RXSOF_out; + wire EMIOGEM0SYNCFRAMERX_out; + wire EMIOGEM0SYNCFRAMETX_out; + wire EMIOGEM0TSUTIMERCMPVAL_out; + wire EMIOGEM0TXRFIXEDLAT_out; + wire EMIOGEM0TXSOF_out; + wire EMIOGEM1DELAYREQRX_out; + wire EMIOGEM1DELAYREQTX_out; + wire EMIOGEM1PDELAYREQRX_out; + wire EMIOGEM1PDELAYREQTX_out; + wire EMIOGEM1PDELAYRESPRX_out; + wire EMIOGEM1PDELAYRESPTX_out; + wire EMIOGEM1RXSOF_out; + wire EMIOGEM1SYNCFRAMERX_out; + wire EMIOGEM1SYNCFRAMETX_out; + wire EMIOGEM1TSUTIMERCMPVAL_out; + wire EMIOGEM1TXRFIXEDLAT_out; + wire EMIOGEM1TXSOF_out; + wire EMIOGEM2DELAYREQRX_out; + wire EMIOGEM2DELAYREQTX_out; + wire EMIOGEM2PDELAYREQRX_out; + wire EMIOGEM2PDELAYREQTX_out; + wire EMIOGEM2PDELAYRESPRX_out; + wire EMIOGEM2PDELAYRESPTX_out; + wire EMIOGEM2RXSOF_out; + wire EMIOGEM2SYNCFRAMERX_out; + wire EMIOGEM2SYNCFRAMETX_out; + wire EMIOGEM2TSUTIMERCMPVAL_out; + wire EMIOGEM2TXRFIXEDLAT_out; + wire EMIOGEM2TXSOF_out; + wire EMIOGEM3DELAYREQRX_out; + wire EMIOGEM3DELAYREQTX_out; + wire EMIOGEM3PDELAYREQRX_out; + wire EMIOGEM3PDELAYREQTX_out; + wire EMIOGEM3PDELAYRESPRX_out; + wire EMIOGEM3PDELAYRESPTX_out; + wire EMIOGEM3RXSOF_out; + wire EMIOGEM3SYNCFRAMERX_out; + wire EMIOGEM3SYNCFRAMETX_out; + wire EMIOGEM3TSUTIMERCMPVAL_out; + wire EMIOGEM3TXRFIXEDLAT_out; + wire EMIOGEM3TXSOF_out; + wire EMIOI2C0SCLO_out; + wire EMIOI2C0SCLTN_out; + wire EMIOI2C0SDAO_out; + wire EMIOI2C0SDATN_out; + wire EMIOI2C1SCLO_out; + wire EMIOI2C1SCLTN_out; + wire EMIOI2C1SDAO_out; + wire EMIOI2C1SDATN_out; + wire EMIOSDIO0BUSPOWER_out; + wire EMIOSDIO0CLKOUT_out; + wire EMIOSDIO0CMDENA_out; + wire EMIOSDIO0CMDOUT_out; + wire EMIOSDIO0LEDCONTROL_out; + wire EMIOSDIO1BUSPOWER_out; + wire EMIOSDIO1CLKOUT_out; + wire EMIOSDIO1CMDENA_out; + wire EMIOSDIO1CMDOUT_out; + wire EMIOSDIO1LEDCONTROL_out; + wire EMIOSPI0MOTN_out; + wire EMIOSPI0MO_out; + wire EMIOSPI0SCLKO_out; + wire EMIOSPI0SCLKTN_out; + wire EMIOSPI0SO_out; + wire EMIOSPI0SSNTN_out; + wire EMIOSPI0STN_out; + wire EMIOSPI1MOTN_out; + wire EMIOSPI1MO_out; + wire EMIOSPI1SCLKO_out; + wire EMIOSPI1SCLKTN_out; + wire EMIOSPI1SO_out; + wire EMIOSPI1SSNTN_out; + wire EMIOSPI1STN_out; + wire EMIOU2DSPORTVBUSCTRLUSB30_out; + wire EMIOU2DSPORTVBUSCTRLUSB31_out; + wire EMIOU3DSPORTVBUSCTRLUSB30_out; + wire EMIOU3DSPORTVBUSCTRLUSB31_out; + wire EMIOUART0DTRN_out; + wire EMIOUART0RTSN_out; + wire EMIOUART0TX_out; + wire EMIOUART1DTRN_out; + wire EMIOUART1RTSN_out; + wire EMIOUART1TX_out; + wire EMIOWDT0RSTO_out; + wire EMIOWDT1RSTO_out; + wire FMIOGEM0FIFORXCLKTOPLBUFG_out; + wire FMIOGEM0FIFOTXCLKTOPLBUFG_out; + wire FMIOGEM1FIFORXCLKTOPLBUFG_out; + wire FMIOGEM1FIFOTXCLKTOPLBUFG_out; + wire FMIOGEM2FIFORXCLKTOPLBUFG_out; + wire FMIOGEM2FIFOTXCLKTOPLBUFG_out; + wire FMIOGEM3FIFORXCLKTOPLBUFG_out; + wire FMIOGEM3FIFOTXCLKTOPLBUFG_out; + wire FMIOGEMTSUCLKTOPLBUFG_out; + wire MAXIGP0ARLOCK_out; + wire MAXIGP0ARVALID_out; + wire MAXIGP0AWLOCK_out; + wire MAXIGP0AWVALID_out; + wire MAXIGP0BREADY_out; + wire MAXIGP0RREADY_out; + wire MAXIGP0WLAST_out; + wire MAXIGP0WVALID_out; + wire MAXIGP1ARLOCK_out; + wire MAXIGP1ARVALID_out; + wire MAXIGP1AWLOCK_out; + wire MAXIGP1AWVALID_out; + wire MAXIGP1BREADY_out; + wire MAXIGP1RREADY_out; + wire MAXIGP1WLAST_out; + wire MAXIGP1WVALID_out; + wire MAXIGP2ARLOCK_out; + wire MAXIGP2ARVALID_out; + wire MAXIGP2AWLOCK_out; + wire MAXIGP2AWVALID_out; + wire MAXIGP2BREADY_out; + wire MAXIGP2RREADY_out; + wire MAXIGP2WLAST_out; + wire MAXIGP2WVALID_out; + wire OSCRTCCLK_out; + wire PMUAIBAFIFMFPDREQ_out; + wire PMUAIBAFIFMLPDREQ_out; + wire PSPLEVENTO_out; + wire PSPLTRACECTL_out; + wire PSS_ALTO_CORE_PAD_MGTTXN0OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXN1OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXN2OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXN3OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXP0OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXP1OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXP2OUT_out; + wire PSS_ALTO_CORE_PAD_MGTTXP3OUT_out; + wire PSS_ALTO_CORE_PAD_PADO_out; + wire RPUEVENTO0_out; + wire RPUEVENTO1_out; + wire SACEFPDACVALID_out; + wire SACEFPDARREADY_out; + wire SACEFPDAWREADY_out; + wire SACEFPDBUSER_out; + wire SACEFPDBVALID_out; + wire SACEFPDCDREADY_out; + wire SACEFPDCRREADY_out; + wire SACEFPDRLAST_out; + wire SACEFPDRUSER_out; + wire SACEFPDRVALID_out; + wire SACEFPDWREADY_out; + wire SAXIACPARREADY_out; + wire SAXIACPAWREADY_out; + wire SAXIACPBVALID_out; + wire SAXIACPRLAST_out; + wire SAXIACPRVALID_out; + wire SAXIACPWREADY_out; + wire SAXIGP0ARREADY_out; + wire SAXIGP0AWREADY_out; + wire SAXIGP0BVALID_out; + wire SAXIGP0RLAST_out; + wire SAXIGP0RVALID_out; + wire SAXIGP0WREADY_out; + wire SAXIGP1ARREADY_out; + wire SAXIGP1AWREADY_out; + wire SAXIGP1BVALID_out; + wire SAXIGP1RLAST_out; + wire SAXIGP1RVALID_out; + wire SAXIGP1WREADY_out; + wire SAXIGP2ARREADY_out; + wire SAXIGP2AWREADY_out; + wire SAXIGP2BVALID_out; + wire SAXIGP2RLAST_out; + wire SAXIGP2RVALID_out; + wire SAXIGP2WREADY_out; + wire SAXIGP3ARREADY_out; + wire SAXIGP3AWREADY_out; + wire SAXIGP3BVALID_out; + wire SAXIGP3RLAST_out; + wire SAXIGP3RVALID_out; + wire SAXIGP3WREADY_out; + wire SAXIGP4ARREADY_out; + wire SAXIGP4AWREADY_out; + wire SAXIGP4BVALID_out; + wire SAXIGP4RLAST_out; + wire SAXIGP4RVALID_out; + wire SAXIGP4WREADY_out; + wire SAXIGP5ARREADY_out; + wire SAXIGP5AWREADY_out; + wire SAXIGP5BVALID_out; + wire SAXIGP5RLAST_out; + wire SAXIGP5RVALID_out; + wire SAXIGP5WREADY_out; + wire SAXIGP6ARREADY_out; + wire SAXIGP6AWREADY_out; + wire SAXIGP6BVALID_out; + wire SAXIGP6RLAST_out; + wire SAXIGP6RVALID_out; + wire SAXIGP6WREADY_out; + wire [127:0] MAXIGP0WDATA_out; + wire [127:0] MAXIGP1WDATA_out; + wire [127:0] MAXIGP2WDATA_out; + wire [127:0] SACEFPDRDATA_out; + wire [127:0] SAXIACPRDATA_out; + wire [127:0] SAXIGP0RDATA_out; + wire [127:0] SAXIGP1RDATA_out; + wire [127:0] SAXIGP2RDATA_out; + wire [127:0] SAXIGP3RDATA_out; + wire [127:0] SAXIGP4RDATA_out; + wire [127:0] SAXIGP5RDATA_out; + wire [127:0] SAXIGP6RDATA_out; + wire [15:0] MAXIGP0ARID_out; + wire [15:0] MAXIGP0ARUSER_out; + wire [15:0] MAXIGP0AWID_out; + wire [15:0] MAXIGP0AWUSER_out; + wire [15:0] MAXIGP0WSTRB_out; + wire [15:0] MAXIGP1ARID_out; + wire [15:0] MAXIGP1ARUSER_out; + wire [15:0] MAXIGP1AWID_out; + wire [15:0] MAXIGP1AWUSER_out; + wire [15:0] MAXIGP1WSTRB_out; + wire [15:0] MAXIGP2ARID_out; + wire [15:0] MAXIGP2ARUSER_out; + wire [15:0] MAXIGP2AWID_out; + wire [15:0] MAXIGP2AWUSER_out; + wire [15:0] MAXIGP2WSTRB_out; + wire [1:0] EMIOENET0DMABUSWIDTH_out; + wire [1:0] EMIOENET1DMABUSWIDTH_out; + wire [1:0] EMIOENET2DMABUSWIDTH_out; + wire [1:0] EMIOENET3DMABUSWIDTH_out; + wire [1:0] MAXIGP0ARBURST_out; + wire [1:0] MAXIGP0AWBURST_out; + wire [1:0] MAXIGP1ARBURST_out; + wire [1:0] MAXIGP1AWBURST_out; + wire [1:0] MAXIGP2ARBURST_out; + wire [1:0] MAXIGP2AWBURST_out; + wire [1:0] SACEFPDBRESP_out; + wire [1:0] SAXIACPBRESP_out; + wire [1:0] SAXIACPRRESP_out; + wire [1:0] SAXIGP0BRESP_out; + wire [1:0] SAXIGP0RRESP_out; + wire [1:0] SAXIGP1BRESP_out; + wire [1:0] SAXIGP1RRESP_out; + wire [1:0] SAXIGP2BRESP_out; + wire [1:0] SAXIGP2RRESP_out; + wire [1:0] SAXIGP3BRESP_out; + wire [1:0] SAXIGP3RRESP_out; + wire [1:0] SAXIGP4BRESP_out; + wire [1:0] SAXIGP4RRESP_out; + wire [1:0] SAXIGP5BRESP_out; + wire [1:0] SAXIGP5RRESP_out; + wire [1:0] SAXIGP6BRESP_out; + wire [1:0] SAXIGP6RRESP_out; + wire [2:0] EMIOENET0SPEEDMODE_out; + wire [2:0] EMIOENET1SPEEDMODE_out; + wire [2:0] EMIOENET2SPEEDMODE_out; + wire [2:0] EMIOENET3SPEEDMODE_out; + wire [2:0] EMIOSDIO0BUSVOLT_out; + wire [2:0] EMIOSDIO1BUSVOLT_out; + wire [2:0] EMIOSPI0SSON_out; + wire [2:0] EMIOSPI1SSON_out; + wire [2:0] EMIOTTC0WAVEO_out; + wire [2:0] EMIOTTC1WAVEO_out; + wire [2:0] EMIOTTC2WAVEO_out; + wire [2:0] EMIOTTC3WAVEO_out; + wire [2:0] MAXIGP0ARPROT_out; + wire [2:0] MAXIGP0ARSIZE_out; + wire [2:0] MAXIGP0AWPROT_out; + wire [2:0] MAXIGP0AWSIZE_out; + wire [2:0] MAXIGP1ARPROT_out; + wire [2:0] MAXIGP1ARSIZE_out; + wire [2:0] MAXIGP1AWPROT_out; + wire [2:0] MAXIGP1AWSIZE_out; + wire [2:0] MAXIGP2ARPROT_out; + wire [2:0] MAXIGP2ARSIZE_out; + wire [2:0] MAXIGP2AWPROT_out; + wire [2:0] MAXIGP2AWSIZE_out; + wire [2:0] SACEFPDACPROT_out; + wire [31:0] DPMAXISMIXEDAUDIOTDATA_out; + wire [31:0] FTMGPO_out; + wire [31:0] PMUPLGPO_out; + wire [31:0] PSPLTRACEDATA_out; + wire [35:0] DPVIDEOOUTPIXEL1_out; + wire [39:0] MAXIGP0ARADDR_out; + wire [39:0] MAXIGP0AWADDR_out; + wire [39:0] MAXIGP1ARADDR_out; + wire [39:0] MAXIGP1AWADDR_out; + wire [39:0] MAXIGP2ARADDR_out; + wire [39:0] MAXIGP2AWADDR_out; + wire [3:0] EMIOENET0TXRSTATUS_out; + wire [3:0] EMIOENET1TXRSTATUS_out; + wire [3:0] EMIOENET2TXRSTATUS_out; + wire [3:0] EMIOENET3TXRSTATUS_out; + wire [3:0] MAXIGP0ARCACHE_out; + wire [3:0] MAXIGP0ARQOS_out; + wire [3:0] MAXIGP0AWCACHE_out; + wire [3:0] MAXIGP0AWQOS_out; + wire [3:0] MAXIGP1ARCACHE_out; + wire [3:0] MAXIGP1ARQOS_out; + wire [3:0] MAXIGP1AWCACHE_out; + wire [3:0] MAXIGP1AWQOS_out; + wire [3:0] MAXIGP2ARCACHE_out; + wire [3:0] MAXIGP2ARQOS_out; + wire [3:0] MAXIGP2AWCACHE_out; + wire [3:0] MAXIGP2AWQOS_out; + wire [3:0] PLCLK_out; + wire [3:0] PSPLSTANDBYWFE_out; + wire [3:0] PSPLSTANDBYWFI_out; + wire [3:0] PSPLTRIGACK_out; + wire [3:0] PSPLTRIGGER_out; + wire [3:0] SACEFPDACSNOOP_out; + wire [3:0] SACEFPDRRESP_out; + wire [3:0] SAXIGP0RACOUNT_out; + wire [3:0] SAXIGP0WACOUNT_out; + wire [3:0] SAXIGP1RACOUNT_out; + wire [3:0] SAXIGP1WACOUNT_out; + wire [3:0] SAXIGP2RACOUNT_out; + wire [3:0] SAXIGP2WACOUNT_out; + wire [3:0] SAXIGP3RACOUNT_out; + wire [3:0] SAXIGP3WACOUNT_out; + wire [3:0] SAXIGP4RACOUNT_out; + wire [3:0] SAXIGP4WACOUNT_out; + wire [3:0] SAXIGP5RACOUNT_out; + wire [3:0] SAXIGP5WACOUNT_out; + wire [3:0] SAXIGP6RACOUNT_out; + wire [3:0] SAXIGP6WACOUNT_out; + wire [43:0] SACEFPDACADDR_out; + wire [44:0] EMIOENET0RXWSTATUS_out; + wire [44:0] EMIOENET1RXWSTATUS_out; + wire [44:0] EMIOENET2RXWSTATUS_out; + wire [44:0] EMIOENET3RXWSTATUS_out; + wire [46:0] PMUERRORTOPL_out; + wire [4:0] SAXIACPBID_out; + wire [4:0] SAXIACPRID_out; + wire [5:0] SACEFPDBID_out; + wire [5:0] SACEFPDRID_out; + wire [5:0] SAXIGP0BID_out; + wire [5:0] SAXIGP0RID_out; + wire [5:0] SAXIGP1BID_out; + wire [5:0] SAXIGP1RID_out; + wire [5:0] SAXIGP2BID_out; + wire [5:0] SAXIGP2RID_out; + wire [5:0] SAXIGP3BID_out; + wire [5:0] SAXIGP3RID_out; + wire [5:0] SAXIGP4BID_out; + wire [5:0] SAXIGP4RID_out; + wire [5:0] SAXIGP5BID_out; + wire [5:0] SAXIGP5RID_out; + wire [5:0] SAXIGP6BID_out; + wire [5:0] SAXIGP6RID_out; + wire [63:0] PSPLIRQFPD_out; + wire [7:0] ADMA2PLCACK_out; + wire [7:0] ADMA2PLTVLD_out; + wire [7:0] EMIOENET0GMIITXD_out; + wire [7:0] EMIOENET0RXWDATA_out; + wire [7:0] EMIOENET1GMIITXD_out; + wire [7:0] EMIOENET1RXWDATA_out; + wire [7:0] EMIOENET2GMIITXD_out; + wire [7:0] EMIOENET2RXWDATA_out; + wire [7:0] EMIOENET3GMIITXD_out; + wire [7:0] EMIOENET3RXWDATA_out; + wire [7:0] EMIOSDIO0DATAENA_out; + wire [7:0] EMIOSDIO0DATAOUT_out; + wire [7:0] EMIOSDIO1DATAENA_out; + wire [7:0] EMIOSDIO1DATAOUT_out; + wire [7:0] GDMA2PLCACK_out; + wire [7:0] GDMA2PLTVLD_out; + wire [7:0] MAXIGP0ARLEN_out; + wire [7:0] MAXIGP0AWLEN_out; + wire [7:0] MAXIGP1ARLEN_out; + wire [7:0] MAXIGP1AWLEN_out; + wire [7:0] MAXIGP2ARLEN_out; + wire [7:0] MAXIGP2AWLEN_out; + wire [7:0] SAXIGP0RCOUNT_out; + wire [7:0] SAXIGP0WCOUNT_out; + wire [7:0] SAXIGP1RCOUNT_out; + wire [7:0] SAXIGP1WCOUNT_out; + wire [7:0] SAXIGP2RCOUNT_out; + wire [7:0] SAXIGP2WCOUNT_out; + wire [7:0] SAXIGP3RCOUNT_out; + wire [7:0] SAXIGP3WCOUNT_out; + wire [7:0] SAXIGP4RCOUNT_out; + wire [7:0] SAXIGP4WCOUNT_out; + wire [7:0] SAXIGP5RCOUNT_out; + wire [7:0] SAXIGP5WCOUNT_out; + wire [7:0] SAXIGP6RCOUNT_out; + wire [7:0] SAXIGP6WCOUNT_out; + wire [93:0] EMIOENET0GEMTSUTIMERCNT_out; + wire [95:0] EMIOGPIOO_out; + wire [95:0] EMIOGPIOTN_out; + wire [99:0] PSPLIRQLPD_out; + + wire AIBPMUAFIFMFPDACK_in; + wire AIBPMUAFIFMLPDACK_in; + wire DDRCEXTREFRESHRANK0REQ_in; + wire DDRCEXTREFRESHRANK1REQ_in; + wire DDRCREFRESHPLCLK_in; + wire DPAUXDATAIN_in; + wire DPEXTERNALCUSTOMEVENT1_in; + wire DPEXTERNALCUSTOMEVENT2_in; + wire DPEXTERNALVSYNCEVENT_in; + wire DPHOTPLUGDETECT_in; + wire DPLIVEVIDEOINDE_in; + wire DPLIVEVIDEOINHSYNC_in; + wire DPLIVEVIDEOINVSYNC_in; + wire DPMAXISMIXEDAUDIOTREADY_in; + wire DPSAXISAUDIOCLK_in; + wire DPSAXISAUDIOTID_in; + wire DPSAXISAUDIOTVALID_in; + wire DPVIDEOINCLK_in; + wire EMIOCAN0PHYRX_in; + wire EMIOCAN1PHYRX_in; + wire EMIOENET0DMATXSTATUSTOG_in; + wire EMIOENET0EXTINTIN_in; + wire EMIOENET0GMIICOL_in; + wire EMIOENET0GMIICRS_in; + wire EMIOENET0GMIIRXCLK_in; + wire EMIOENET0GMIIRXDV_in; + wire EMIOENET0GMIIRXER_in; + wire EMIOENET0GMIITXCLK_in; + wire EMIOENET0MDIOI_in; + wire EMIOENET0RXWOVERFLOW_in; + wire EMIOENET0TXRCONTROL_in; + wire EMIOENET0TXRDATARDY_in; + wire EMIOENET0TXREOP_in; + wire EMIOENET0TXRERR_in; + wire EMIOENET0TXRFLUSHED_in; + wire EMIOENET0TXRSOP_in; + wire EMIOENET0TXRUNDERFLOW_in; + wire EMIOENET0TXRVALID_in; + wire EMIOENET1DMATXSTATUSTOG_in; + wire EMIOENET1EXTINTIN_in; + wire EMIOENET1GMIICOL_in; + wire EMIOENET1GMIICRS_in; + wire EMIOENET1GMIIRXCLK_in; + wire EMIOENET1GMIIRXDV_in; + wire EMIOENET1GMIIRXER_in; + wire EMIOENET1GMIITXCLK_in; + wire EMIOENET1MDIOI_in; + wire EMIOENET1RXWOVERFLOW_in; + wire EMIOENET1TXRCONTROL_in; + wire EMIOENET1TXRDATARDY_in; + wire EMIOENET1TXREOP_in; + wire EMIOENET1TXRERR_in; + wire EMIOENET1TXRFLUSHED_in; + wire EMIOENET1TXRSOP_in; + wire EMIOENET1TXRUNDERFLOW_in; + wire EMIOENET1TXRVALID_in; + wire EMIOENET2DMATXSTATUSTOG_in; + wire EMIOENET2EXTINTIN_in; + wire EMIOENET2GMIICOL_in; + wire EMIOENET2GMIICRS_in; + wire EMIOENET2GMIIRXCLK_in; + wire EMIOENET2GMIIRXDV_in; + wire EMIOENET2GMIIRXER_in; + wire EMIOENET2GMIITXCLK_in; + wire EMIOENET2MDIOI_in; + wire EMIOENET2RXWOVERFLOW_in; + wire EMIOENET2TXRCONTROL_in; + wire EMIOENET2TXRDATARDY_in; + wire EMIOENET2TXREOP_in; + wire EMIOENET2TXRERR_in; + wire EMIOENET2TXRFLUSHED_in; + wire EMIOENET2TXRSOP_in; + wire EMIOENET2TXRUNDERFLOW_in; + wire EMIOENET2TXRVALID_in; + wire EMIOENET3DMATXSTATUSTOG_in; + wire EMIOENET3EXTINTIN_in; + wire EMIOENET3GMIICOL_in; + wire EMIOENET3GMIICRS_in; + wire EMIOENET3GMIIRXCLK_in; + wire EMIOENET3GMIIRXDV_in; + wire EMIOENET3GMIIRXER_in; + wire EMIOENET3GMIITXCLK_in; + wire EMIOENET3MDIOI_in; + wire EMIOENET3RXWOVERFLOW_in; + wire EMIOENET3TXRCONTROL_in; + wire EMIOENET3TXRDATARDY_in; + wire EMIOENET3TXREOP_in; + wire EMIOENET3TXRERR_in; + wire EMIOENET3TXRFLUSHED_in; + wire EMIOENET3TXRSOP_in; + wire EMIOENET3TXRUNDERFLOW_in; + wire EMIOENET3TXRVALID_in; + wire EMIOENETTSUCLK_in; + wire EMIOHUBPORTOVERCRNTUSB20_in; + wire EMIOHUBPORTOVERCRNTUSB21_in; + wire EMIOHUBPORTOVERCRNTUSB30_in; + wire EMIOHUBPORTOVERCRNTUSB31_in; + wire EMIOI2C0SCLI_in; + wire EMIOI2C0SDAI_in; + wire EMIOI2C1SCLI_in; + wire EMIOI2C1SDAI_in; + wire EMIOSDIO0CDN_in; + wire EMIOSDIO0CMDIN_in; + wire EMIOSDIO0FBCLKIN_in; + wire EMIOSDIO0WP_in; + wire EMIOSDIO1CDN_in; + wire EMIOSDIO1CMDIN_in; + wire EMIOSDIO1FBCLKIN_in; + wire EMIOSDIO1WP_in; + wire EMIOSPI0MI_in; + wire EMIOSPI0SCLKI_in; + wire EMIOSPI0SI_in; + wire EMIOSPI0SSIN_in; + wire EMIOSPI1MI_in; + wire EMIOSPI1SCLKI_in; + wire EMIOSPI1SI_in; + wire EMIOSPI1SSIN_in; + wire EMIOUART0CTSN_in; + wire EMIOUART0DCDN_in; + wire EMIOUART0DSRN_in; + wire EMIOUART0RIN_in; + wire EMIOUART0RX_in; + wire EMIOUART1CTSN_in; + wire EMIOUART1DCDN_in; + wire EMIOUART1DSRN_in; + wire EMIOUART1RIN_in; + wire EMIOUART1RX_in; + wire EMIOWDT0CLKI_in; + wire EMIOWDT1CLKI_in; + wire FMIOGEM0FIFORXCLKFROMPL_in; + wire FMIOGEM0FIFOTXCLKFROMPL_in; + wire FMIOGEM0SIGNALDETECT_in; + wire FMIOGEM1FIFORXCLKFROMPL_in; + wire FMIOGEM1FIFOTXCLKFROMPL_in; + wire FMIOGEM1SIGNALDETECT_in; + wire FMIOGEM2FIFORXCLKFROMPL_in; + wire FMIOGEM2FIFOTXCLKFROMPL_in; + wire FMIOGEM2SIGNALDETECT_in; + wire FMIOGEM3FIFORXCLKFROMPL_in; + wire FMIOGEM3FIFOTXCLKFROMPL_in; + wire FMIOGEM3SIGNALDETECT_in; + wire FMIOGEMTSUCLKFROMPL_in; + wire MAXIGP0ACLK_in; + wire MAXIGP0ARREADY_in; + wire MAXIGP0AWREADY_in; + wire MAXIGP0BVALID_in; + wire MAXIGP0RLAST_in; + wire MAXIGP0RVALID_in; + wire MAXIGP0WREADY_in; + wire MAXIGP1ACLK_in; + wire MAXIGP1ARREADY_in; + wire MAXIGP1AWREADY_in; + wire MAXIGP1BVALID_in; + wire MAXIGP1RLAST_in; + wire MAXIGP1RVALID_in; + wire MAXIGP1WREADY_in; + wire MAXIGP2ACLK_in; + wire MAXIGP2ARREADY_in; + wire MAXIGP2AWREADY_in; + wire MAXIGP2BVALID_in; + wire MAXIGP2RLAST_in; + wire MAXIGP2RVALID_in; + wire MAXIGP2WREADY_in; + wire NFIQ0LPDRPU_in; + wire NFIQ1LPDRPU_in; + wire NIRQ0LPDRPU_in; + wire NIRQ1LPDRPU_in; + wire PLACECLK_in; + wire PLACPINACT_in; + wire PLPSEVENTI_in; + wire PLPSTRACECLK_in; + wire PSS_ALTO_CORE_PAD_MGTRXN0IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXN1IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXN2IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXN3IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXP0IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXP1IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXP2IN_in; + wire PSS_ALTO_CORE_PAD_MGTRXP3IN_in; + wire PSS_ALTO_CORE_PAD_PADI_in; + wire PSS_ALTO_CORE_PAD_REFN0IN_in; + wire PSS_ALTO_CORE_PAD_REFN1IN_in; + wire PSS_ALTO_CORE_PAD_REFN2IN_in; + wire PSS_ALTO_CORE_PAD_REFN3IN_in; + wire PSS_ALTO_CORE_PAD_REFP0IN_in; + wire PSS_ALTO_CORE_PAD_REFP1IN_in; + wire PSS_ALTO_CORE_PAD_REFP2IN_in; + wire PSS_ALTO_CORE_PAD_REFP3IN_in; + wire RPUEVENTI0_in; + wire RPUEVENTI1_in; + wire SACEFPDACREADY_in; + wire SACEFPDARLOCK_in; + wire SACEFPDARVALID_in; + wire SACEFPDAWLOCK_in; + wire SACEFPDAWVALID_in; + wire SACEFPDBREADY_in; + wire SACEFPDCDLAST_in; + wire SACEFPDCDVALID_in; + wire SACEFPDCRVALID_in; + wire SACEFPDRACK_in; + wire SACEFPDRREADY_in; + wire SACEFPDWACK_in; + wire SACEFPDWLAST_in; + wire SACEFPDWUSER_in; + wire SACEFPDWVALID_in; + wire SAXIACPACLK_in; + wire SAXIACPARLOCK_in; + wire SAXIACPARVALID_in; + wire SAXIACPAWLOCK_in; + wire SAXIACPAWVALID_in; + wire SAXIACPBREADY_in; + wire SAXIACPRREADY_in; + wire SAXIACPWLAST_in; + wire SAXIACPWVALID_in; + wire SAXIGP0ARLOCK_in; + wire SAXIGP0ARUSER_in; + wire SAXIGP0ARVALID_in; + wire SAXIGP0AWLOCK_in; + wire SAXIGP0AWUSER_in; + wire SAXIGP0AWVALID_in; + wire SAXIGP0BREADY_in; + wire SAXIGP0RCLK_in; + wire SAXIGP0RREADY_in; + wire SAXIGP0WCLK_in; + wire SAXIGP0WLAST_in; + wire SAXIGP0WVALID_in; + wire SAXIGP1ARLOCK_in; + wire SAXIGP1ARUSER_in; + wire SAXIGP1ARVALID_in; + wire SAXIGP1AWLOCK_in; + wire SAXIGP1AWUSER_in; + wire SAXIGP1AWVALID_in; + wire SAXIGP1BREADY_in; + wire SAXIGP1RCLK_in; + wire SAXIGP1RREADY_in; + wire SAXIGP1WCLK_in; + wire SAXIGP1WLAST_in; + wire SAXIGP1WVALID_in; + wire SAXIGP2ARLOCK_in; + wire SAXIGP2ARUSER_in; + wire SAXIGP2ARVALID_in; + wire SAXIGP2AWLOCK_in; + wire SAXIGP2AWUSER_in; + wire SAXIGP2AWVALID_in; + wire SAXIGP2BREADY_in; + wire SAXIGP2RCLK_in; + wire SAXIGP2RREADY_in; + wire SAXIGP2WCLK_in; + wire SAXIGP2WLAST_in; + wire SAXIGP2WVALID_in; + wire SAXIGP3ARLOCK_in; + wire SAXIGP3ARUSER_in; + wire SAXIGP3ARVALID_in; + wire SAXIGP3AWLOCK_in; + wire SAXIGP3AWUSER_in; + wire SAXIGP3AWVALID_in; + wire SAXIGP3BREADY_in; + wire SAXIGP3RCLK_in; + wire SAXIGP3RREADY_in; + wire SAXIGP3WCLK_in; + wire SAXIGP3WLAST_in; + wire SAXIGP3WVALID_in; + wire SAXIGP4ARLOCK_in; + wire SAXIGP4ARUSER_in; + wire SAXIGP4ARVALID_in; + wire SAXIGP4AWLOCK_in; + wire SAXIGP4AWUSER_in; + wire SAXIGP4AWVALID_in; + wire SAXIGP4BREADY_in; + wire SAXIGP4RCLK_in; + wire SAXIGP4RREADY_in; + wire SAXIGP4WCLK_in; + wire SAXIGP4WLAST_in; + wire SAXIGP4WVALID_in; + wire SAXIGP5ARLOCK_in; + wire SAXIGP5ARUSER_in; + wire SAXIGP5ARVALID_in; + wire SAXIGP5AWLOCK_in; + wire SAXIGP5AWUSER_in; + wire SAXIGP5AWVALID_in; + wire SAXIGP5BREADY_in; + wire SAXIGP5RCLK_in; + wire SAXIGP5RREADY_in; + wire SAXIGP5WCLK_in; + wire SAXIGP5WLAST_in; + wire SAXIGP5WVALID_in; + wire SAXIGP6ARLOCK_in; + wire SAXIGP6ARUSER_in; + wire SAXIGP6ARVALID_in; + wire SAXIGP6AWLOCK_in; + wire SAXIGP6AWUSER_in; + wire SAXIGP6AWVALID_in; + wire SAXIGP6BREADY_in; + wire SAXIGP6RCLK_in; + wire SAXIGP6RREADY_in; + wire SAXIGP6WCLK_in; + wire SAXIGP6WLAST_in; + wire SAXIGP6WVALID_in; + wire [127:0] MAXIGP0RDATA_in; + wire [127:0] MAXIGP1RDATA_in; + wire [127:0] MAXIGP2RDATA_in; + wire [127:0] SACEFPDCDDATA_in; + wire [127:0] SACEFPDWDATA_in; + wire [127:0] SAXIACPWDATA_in; + wire [127:0] SAXIGP0WDATA_in; + wire [127:0] SAXIGP1WDATA_in; + wire [127:0] SAXIGP2WDATA_in; + wire [127:0] SAXIGP3WDATA_in; + wire [127:0] SAXIGP4WDATA_in; + wire [127:0] SAXIGP5WDATA_in; + wire [127:0] SAXIGP6WDATA_in; + wire [15:0] MAXIGP0BID_in; + wire [15:0] MAXIGP0RID_in; + wire [15:0] MAXIGP1BID_in; + wire [15:0] MAXIGP1RID_in; + wire [15:0] MAXIGP2BID_in; + wire [15:0] MAXIGP2RID_in; + wire [15:0] SACEFPDARUSER_in; + wire [15:0] SACEFPDAWUSER_in; + wire [15:0] SACEFPDWSTRB_in; + wire [15:0] SAXIACPWSTRB_in; + wire [15:0] SAXIGP0WSTRB_in; + wire [15:0] SAXIGP1WSTRB_in; + wire [15:0] SAXIGP2WSTRB_in; + wire [15:0] SAXIGP3WSTRB_in; + wire [15:0] SAXIGP4WSTRB_in; + wire [15:0] SAXIGP5WSTRB_in; + wire [15:0] SAXIGP6WSTRB_in; + wire [1:0] EMIOGEM0TSUINCCTRL_in; + wire [1:0] EMIOGEM1TSUINCCTRL_in; + wire [1:0] EMIOGEM2TSUINCCTRL_in; + wire [1:0] EMIOGEM3TSUINCCTRL_in; + wire [1:0] MAXIGP0BRESP_in; + wire [1:0] MAXIGP0RRESP_in; + wire [1:0] MAXIGP1BRESP_in; + wire [1:0] MAXIGP1RRESP_in; + wire [1:0] MAXIGP2BRESP_in; + wire [1:0] MAXIGP2RRESP_in; + wire [1:0] PLLAUXREFCLKLPD_in; + wire [1:0] SACEFPDARBAR_in; + wire [1:0] SACEFPDARBURST_in; + wire [1:0] SACEFPDARDOMAIN_in; + wire [1:0] SACEFPDAWBAR_in; + wire [1:0] SACEFPDAWBURST_in; + wire [1:0] SACEFPDAWDOMAIN_in; + wire [1:0] SAXIACPARBURST_in; + wire [1:0] SAXIACPARUSER_in; + wire [1:0] SAXIACPAWBURST_in; + wire [1:0] SAXIACPAWUSER_in; + wire [1:0] SAXIGP0ARBURST_in; + wire [1:0] SAXIGP0AWBURST_in; + wire [1:0] SAXIGP1ARBURST_in; + wire [1:0] SAXIGP1AWBURST_in; + wire [1:0] SAXIGP2ARBURST_in; + wire [1:0] SAXIGP2AWBURST_in; + wire [1:0] SAXIGP3ARBURST_in; + wire [1:0] SAXIGP3AWBURST_in; + wire [1:0] SAXIGP4ARBURST_in; + wire [1:0] SAXIGP4AWBURST_in; + wire [1:0] SAXIGP5ARBURST_in; + wire [1:0] SAXIGP5AWBURST_in; + wire [1:0] SAXIGP6ARBURST_in; + wire [1:0] SAXIGP6AWBURST_in; + wire [2:0] EMIOTTC0CLKI_in; + wire [2:0] EMIOTTC1CLKI_in; + wire [2:0] EMIOTTC2CLKI_in; + wire [2:0] EMIOTTC3CLKI_in; + wire [2:0] PLLAUXREFCLKFPD_in; + wire [2:0] SACEFPDARPROT_in; + wire [2:0] SACEFPDARSIZE_in; + wire [2:0] SACEFPDAWPROT_in; + wire [2:0] SACEFPDAWSIZE_in; + wire [2:0] SACEFPDAWSNOOP_in; + wire [2:0] SAXIACPARPROT_in; + wire [2:0] SAXIACPARSIZE_in; + wire [2:0] SAXIACPAWPROT_in; + wire [2:0] SAXIACPAWSIZE_in; + wire [2:0] SAXIGP0ARPROT_in; + wire [2:0] SAXIGP0ARSIZE_in; + wire [2:0] SAXIGP0AWPROT_in; + wire [2:0] SAXIGP0AWSIZE_in; + wire [2:0] SAXIGP1ARPROT_in; + wire [2:0] SAXIGP1ARSIZE_in; + wire [2:0] SAXIGP1AWPROT_in; + wire [2:0] SAXIGP1AWSIZE_in; + wire [2:0] SAXIGP2ARPROT_in; + wire [2:0] SAXIGP2ARSIZE_in; + wire [2:0] SAXIGP2AWPROT_in; + wire [2:0] SAXIGP2AWSIZE_in; + wire [2:0] SAXIGP3ARPROT_in; + wire [2:0] SAXIGP3ARSIZE_in; + wire [2:0] SAXIGP3AWPROT_in; + wire [2:0] SAXIGP3AWSIZE_in; + wire [2:0] SAXIGP4ARPROT_in; + wire [2:0] SAXIGP4ARSIZE_in; + wire [2:0] SAXIGP4AWPROT_in; + wire [2:0] SAXIGP4AWSIZE_in; + wire [2:0] SAXIGP5ARPROT_in; + wire [2:0] SAXIGP5ARSIZE_in; + wire [2:0] SAXIGP5AWPROT_in; + wire [2:0] SAXIGP5AWSIZE_in; + wire [2:0] SAXIGP6ARPROT_in; + wire [2:0] SAXIGP6ARSIZE_in; + wire [2:0] SAXIGP6AWPROT_in; + wire [2:0] SAXIGP6AWSIZE_in; + wire [31:0] DPSAXISAUDIOTDATA_in; + wire [31:0] FTMGPI_in; + wire [31:0] PLPMUGPI_in; + wire [35:0] DPLIVEGFXPIXEL1IN_in; + wire [35:0] DPLIVEVIDEOINPIXEL1_in; + wire [39:0] SAXIACPARADDR_in; + wire [39:0] SAXIACPAWADDR_in; + wire [3:0] PLFPGASTOP_in; + wire [3:0] PLPSAPUGICFIQ_in; + wire [3:0] PLPSAPUGICIRQ_in; + wire [3:0] PLPSTRIGACK_in; + wire [3:0] PLPSTRIGGER_in; + wire [3:0] PMUERRORFROMPL_in; + wire [3:0] SACEFPDARCACHE_in; + wire [3:0] SACEFPDARQOS_in; + wire [3:0] SACEFPDARREGION_in; + wire [3:0] SACEFPDARSNOOP_in; + wire [3:0] SACEFPDAWCACHE_in; + wire [3:0] SACEFPDAWQOS_in; + wire [3:0] SACEFPDAWREGION_in; + wire [3:0] SAXIACPARCACHE_in; + wire [3:0] SAXIACPARQOS_in; + wire [3:0] SAXIACPAWCACHE_in; + wire [3:0] SAXIACPAWQOS_in; + wire [3:0] SAXIGP0ARCACHE_in; + wire [3:0] SAXIGP0ARQOS_in; + wire [3:0] SAXIGP0AWCACHE_in; + wire [3:0] SAXIGP0AWQOS_in; + wire [3:0] SAXIGP1ARCACHE_in; + wire [3:0] SAXIGP1ARQOS_in; + wire [3:0] SAXIGP1AWCACHE_in; + wire [3:0] SAXIGP1AWQOS_in; + wire [3:0] SAXIGP2ARCACHE_in; + wire [3:0] SAXIGP2ARQOS_in; + wire [3:0] SAXIGP2AWCACHE_in; + wire [3:0] SAXIGP2AWQOS_in; + wire [3:0] SAXIGP3ARCACHE_in; + wire [3:0] SAXIGP3ARQOS_in; + wire [3:0] SAXIGP3AWCACHE_in; + wire [3:0] SAXIGP3AWQOS_in; + wire [3:0] SAXIGP4ARCACHE_in; + wire [3:0] SAXIGP4ARQOS_in; + wire [3:0] SAXIGP4AWCACHE_in; + wire [3:0] SAXIGP4AWQOS_in; + wire [3:0] SAXIGP5ARCACHE_in; + wire [3:0] SAXIGP5ARQOS_in; + wire [3:0] SAXIGP5AWCACHE_in; + wire [3:0] SAXIGP5AWQOS_in; + wire [3:0] SAXIGP6ARCACHE_in; + wire [3:0] SAXIGP6ARQOS_in; + wire [3:0] SAXIGP6AWCACHE_in; + wire [3:0] SAXIGP6AWQOS_in; + wire [43:0] SACEFPDARADDR_in; + wire [43:0] SACEFPDAWADDR_in; + wire [48:0] SAXIGP0ARADDR_in; + wire [48:0] SAXIGP0AWADDR_in; + wire [48:0] SAXIGP1ARADDR_in; + wire [48:0] SAXIGP1AWADDR_in; + wire [48:0] SAXIGP2ARADDR_in; + wire [48:0] SAXIGP2AWADDR_in; + wire [48:0] SAXIGP3ARADDR_in; + wire [48:0] SAXIGP3AWADDR_in; + wire [48:0] SAXIGP4ARADDR_in; + wire [48:0] SAXIGP4AWADDR_in; + wire [48:0] SAXIGP5ARADDR_in; + wire [48:0] SAXIGP5AWADDR_in; + wire [48:0] SAXIGP6ARADDR_in; + wire [48:0] SAXIGP6AWADDR_in; + wire [4:0] SACEFPDCRRESP_in; + wire [4:0] SAXIACPARID_in; + wire [4:0] SAXIACPAWID_in; + wire [59:0] STMEVENT_in; + wire [5:0] SACEFPDARID_in; + wire [5:0] SACEFPDAWID_in; + wire [5:0] SAXIGP0ARID_in; + wire [5:0] SAXIGP0AWID_in; + wire [5:0] SAXIGP1ARID_in; + wire [5:0] SAXIGP1AWID_in; + wire [5:0] SAXIGP2ARID_in; + wire [5:0] SAXIGP2AWID_in; + wire [5:0] SAXIGP3ARID_in; + wire [5:0] SAXIGP3AWID_in; + wire [5:0] SAXIGP4ARID_in; + wire [5:0] SAXIGP4AWID_in; + wire [5:0] SAXIGP5ARID_in; + wire [5:0] SAXIGP5AWID_in; + wire [5:0] SAXIGP6ARID_in; + wire [5:0] SAXIGP6AWID_in; + wire [7:0] ADMAFCICLK_in; + wire [7:0] DPLIVEGFXALPHAIN_in; + wire [7:0] EMIOENET0GMIIRXD_in; + wire [7:0] EMIOENET0TXRDATA_in; + wire [7:0] EMIOENET1GMIIRXD_in; + wire [7:0] EMIOENET1TXRDATA_in; + wire [7:0] EMIOENET2GMIIRXD_in; + wire [7:0] EMIOENET2TXRDATA_in; + wire [7:0] EMIOENET3GMIIRXD_in; + wire [7:0] EMIOENET3TXRDATA_in; + wire [7:0] EMIOSDIO0DATAIN_in; + wire [7:0] EMIOSDIO1DATAIN_in; + wire [7:0] GDMAFCICLK_in; + wire [7:0] PL2ADMACVLD_in; + wire [7:0] PL2ADMATACK_in; + wire [7:0] PL2GDMACVLD_in; + wire [7:0] PL2GDMATACK_in; + wire [7:0] PLPSIRQ0_in; + wire [7:0] PLPSIRQ1_in; + wire [7:0] SACEFPDARLEN_in; + wire [7:0] SACEFPDAWLEN_in; + wire [7:0] SAXIACPARLEN_in; + wire [7:0] SAXIACPAWLEN_in; + wire [7:0] SAXIGP0ARLEN_in; + wire [7:0] SAXIGP0AWLEN_in; + wire [7:0] SAXIGP1ARLEN_in; + wire [7:0] SAXIGP1AWLEN_in; + wire [7:0] SAXIGP2ARLEN_in; + wire [7:0] SAXIGP2AWLEN_in; + wire [7:0] SAXIGP3ARLEN_in; + wire [7:0] SAXIGP3AWLEN_in; + wire [7:0] SAXIGP4ARLEN_in; + wire [7:0] SAXIGP4AWLEN_in; + wire [7:0] SAXIGP5ARLEN_in; + wire [7:0] SAXIGP5AWLEN_in; + wire [7:0] SAXIGP6ARLEN_in; + wire [7:0] SAXIGP6AWLEN_in; + wire [95:0] EMIOGPIOI_in; + +`ifdef XIL_TIMING + wire DDRCEXTREFRESHRANK0REQ_delay; + wire DDRCEXTREFRESHRANK1REQ_delay; + wire DDRCREFRESHPLCLK_delay; + wire DPLIVEVIDEOINDE_delay; + wire DPLIVEVIDEOINHSYNC_delay; + wire DPLIVEVIDEOINVSYNC_delay; + wire DPMAXISMIXEDAUDIOTREADY_delay; + wire DPSAXISAUDIOCLK_delay; + wire DPSAXISAUDIOTID_delay; + wire DPSAXISAUDIOTVALID_delay; + wire DPVIDEOINCLK_delay; + wire EMIOENET0GMIIRXCLK_delay; + wire EMIOENET0GMIIRXDV_delay; + wire EMIOENET0GMIIRXER_delay; + wire EMIOENET0TXRCONTROL_delay; + wire EMIOENET0TXRDATARDY_delay; + wire EMIOENET0TXREOP_delay; + wire EMIOENET0TXRERR_delay; + wire EMIOENET0TXRFLUSHED_delay; + wire EMIOENET0TXRSOP_delay; + wire EMIOENET0TXRUNDERFLOW_delay; + wire EMIOENET0TXRVALID_delay; + wire EMIOENET1GMIIRXCLK_delay; + wire EMIOENET1GMIIRXDV_delay; + wire EMIOENET1GMIIRXER_delay; + wire EMIOENET1TXRCONTROL_delay; + wire EMIOENET1TXRDATARDY_delay; + wire EMIOENET1TXREOP_delay; + wire EMIOENET1TXRERR_delay; + wire EMIOENET1TXRFLUSHED_delay; + wire EMIOENET1TXRSOP_delay; + wire EMIOENET1TXRUNDERFLOW_delay; + wire EMIOENET1TXRVALID_delay; + wire EMIOENET2GMIIRXCLK_delay; + wire EMIOENET2GMIIRXDV_delay; + wire EMIOENET2GMIIRXER_delay; + wire EMIOENET2TXRCONTROL_delay; + wire EMIOENET2TXRDATARDY_delay; + wire EMIOENET2TXREOP_delay; + wire EMIOENET2TXRERR_delay; + wire EMIOENET2TXRFLUSHED_delay; + wire EMIOENET2TXRSOP_delay; + wire EMIOENET2TXRUNDERFLOW_delay; + wire EMIOENET2TXRVALID_delay; + wire EMIOENET3GMIIRXCLK_delay; + wire EMIOENET3GMIIRXDV_delay; + wire EMIOENET3GMIIRXER_delay; + wire EMIOENET3TXRCONTROL_delay; + wire EMIOENET3TXRDATARDY_delay; + wire EMIOENET3TXREOP_delay; + wire EMIOENET3TXRERR_delay; + wire EMIOENET3TXRFLUSHED_delay; + wire EMIOENET3TXRSOP_delay; + wire EMIOENET3TXRUNDERFLOW_delay; + wire EMIOENET3TXRVALID_delay; + wire EMIOSPI0SCLKI_delay; + wire EMIOSPI0SSIN_delay; + wire EMIOSPI1SCLKI_delay; + wire EMIOSPI1SSIN_delay; + wire FMIOGEM0FIFOTXCLKFROMPL_delay; + wire FMIOGEM1FIFOTXCLKFROMPL_delay; + wire FMIOGEM2FIFOTXCLKFROMPL_delay; + wire FMIOGEM3FIFOTXCLKFROMPL_delay; + wire FMIOGEMTSUCLKFROMPL_delay; + wire MAXIGP0ACLK_delay; + wire MAXIGP0ARREADY_delay; + wire MAXIGP0AWREADY_delay; + wire MAXIGP0BVALID_delay; + wire MAXIGP0RLAST_delay; + wire MAXIGP0RVALID_delay; + wire MAXIGP0WREADY_delay; + wire MAXIGP1ACLK_delay; + wire MAXIGP1ARREADY_delay; + wire MAXIGP1AWREADY_delay; + wire MAXIGP1BVALID_delay; + wire MAXIGP1RLAST_delay; + wire MAXIGP1RVALID_delay; + wire MAXIGP1WREADY_delay; + wire MAXIGP2ACLK_delay; + wire MAXIGP2ARREADY_delay; + wire MAXIGP2AWREADY_delay; + wire MAXIGP2BVALID_delay; + wire MAXIGP2RLAST_delay; + wire MAXIGP2RVALID_delay; + wire MAXIGP2WREADY_delay; + wire PLACECLK_delay; + wire SACEFPDACREADY_delay; + wire SACEFPDARLOCK_delay; + wire SACEFPDARVALID_delay; + wire SACEFPDAWLOCK_delay; + wire SACEFPDAWVALID_delay; + wire SACEFPDBREADY_delay; + wire SACEFPDCDLAST_delay; + wire SACEFPDCDVALID_delay; + wire SACEFPDCRVALID_delay; + wire SACEFPDRACK_delay; + wire SACEFPDRREADY_delay; + wire SACEFPDWACK_delay; + wire SACEFPDWLAST_delay; + wire SACEFPDWUSER_delay; + wire SACEFPDWVALID_delay; + wire SAXIACPACLK_delay; + wire SAXIACPARLOCK_delay; + wire SAXIACPARVALID_delay; + wire SAXIACPAWLOCK_delay; + wire SAXIACPAWVALID_delay; + wire SAXIACPBREADY_delay; + wire SAXIACPRREADY_delay; + wire SAXIACPWLAST_delay; + wire SAXIACPWVALID_delay; + wire SAXIGP0ARLOCK_delay; + wire SAXIGP0ARUSER_delay; + wire SAXIGP0ARVALID_delay; + wire SAXIGP0AWLOCK_delay; + wire SAXIGP0AWUSER_delay; + wire SAXIGP0AWVALID_delay; + wire SAXIGP0BREADY_delay; + wire SAXIGP0RCLK_delay; + wire SAXIGP0RREADY_delay; + wire SAXIGP0WCLK_delay; + wire SAXIGP0WLAST_delay; + wire SAXIGP0WVALID_delay; + wire SAXIGP1ARLOCK_delay; + wire SAXIGP1ARUSER_delay; + wire SAXIGP1ARVALID_delay; + wire SAXIGP1AWLOCK_delay; + wire SAXIGP1AWUSER_delay; + wire SAXIGP1AWVALID_delay; + wire SAXIGP1BREADY_delay; + wire SAXIGP1RCLK_delay; + wire SAXIGP1RREADY_delay; + wire SAXIGP1WCLK_delay; + wire SAXIGP1WLAST_delay; + wire SAXIGP1WVALID_delay; + wire SAXIGP2ARLOCK_delay; + wire SAXIGP2ARUSER_delay; + wire SAXIGP2ARVALID_delay; + wire SAXIGP2AWLOCK_delay; + wire SAXIGP2AWUSER_delay; + wire SAXIGP2AWVALID_delay; + wire SAXIGP2BREADY_delay; + wire SAXIGP2RCLK_delay; + wire SAXIGP2RREADY_delay; + wire SAXIGP2WCLK_delay; + wire SAXIGP2WLAST_delay; + wire SAXIGP2WVALID_delay; + wire SAXIGP3ARLOCK_delay; + wire SAXIGP3ARUSER_delay; + wire SAXIGP3ARVALID_delay; + wire SAXIGP3AWLOCK_delay; + wire SAXIGP3AWUSER_delay; + wire SAXIGP3AWVALID_delay; + wire SAXIGP3BREADY_delay; + wire SAXIGP3RCLK_delay; + wire SAXIGP3RREADY_delay; + wire SAXIGP3WCLK_delay; + wire SAXIGP3WLAST_delay; + wire SAXIGP3WVALID_delay; + wire SAXIGP4ARLOCK_delay; + wire SAXIGP4ARUSER_delay; + wire SAXIGP4ARVALID_delay; + wire SAXIGP4AWLOCK_delay; + wire SAXIGP4AWUSER_delay; + wire SAXIGP4AWVALID_delay; + wire SAXIGP4BREADY_delay; + wire SAXIGP4RCLK_delay; + wire SAXIGP4RREADY_delay; + wire SAXIGP4WCLK_delay; + wire SAXIGP4WLAST_delay; + wire SAXIGP4WVALID_delay; + wire SAXIGP5ARLOCK_delay; + wire SAXIGP5ARUSER_delay; + wire SAXIGP5ARVALID_delay; + wire SAXIGP5AWLOCK_delay; + wire SAXIGP5AWUSER_delay; + wire SAXIGP5AWVALID_delay; + wire SAXIGP5BREADY_delay; + wire SAXIGP5RCLK_delay; + wire SAXIGP5RREADY_delay; + wire SAXIGP5WCLK_delay; + wire SAXIGP5WLAST_delay; + wire SAXIGP5WVALID_delay; + wire SAXIGP6ARLOCK_delay; + wire SAXIGP6ARUSER_delay; + wire SAXIGP6ARVALID_delay; + wire SAXIGP6AWLOCK_delay; + wire SAXIGP6AWUSER_delay; + wire SAXIGP6AWVALID_delay; + wire SAXIGP6BREADY_delay; + wire SAXIGP6RCLK_delay; + wire SAXIGP6RREADY_delay; + wire SAXIGP6WCLK_delay; + wire SAXIGP6WLAST_delay; + wire SAXIGP6WVALID_delay; + wire [127:0] MAXIGP0RDATA_delay; + wire [127:0] MAXIGP1RDATA_delay; + wire [127:0] MAXIGP2RDATA_delay; + wire [127:0] SACEFPDCDDATA_delay; + wire [127:0] SACEFPDWDATA_delay; + wire [127:0] SAXIACPWDATA_delay; + wire [127:0] SAXIGP0WDATA_delay; + wire [127:0] SAXIGP1WDATA_delay; + wire [127:0] SAXIGP2WDATA_delay; + wire [127:0] SAXIGP3WDATA_delay; + wire [127:0] SAXIGP4WDATA_delay; + wire [127:0] SAXIGP5WDATA_delay; + wire [127:0] SAXIGP6WDATA_delay; + wire [15:0] MAXIGP0BID_delay; + wire [15:0] MAXIGP0RID_delay; + wire [15:0] MAXIGP1BID_delay; + wire [15:0] MAXIGP1RID_delay; + wire [15:0] MAXIGP2BID_delay; + wire [15:0] MAXIGP2RID_delay; + wire [15:0] SACEFPDARUSER_delay; + wire [15:0] SACEFPDAWUSER_delay; + wire [15:0] SACEFPDWSTRB_delay; + wire [15:0] SAXIACPWSTRB_delay; + wire [15:0] SAXIGP0WSTRB_delay; + wire [15:0] SAXIGP1WSTRB_delay; + wire [15:0] SAXIGP2WSTRB_delay; + wire [15:0] SAXIGP3WSTRB_delay; + wire [15:0] SAXIGP4WSTRB_delay; + wire [15:0] SAXIGP5WSTRB_delay; + wire [15:0] SAXIGP6WSTRB_delay; + wire [1:0] EMIOGEM0TSUINCCTRL_delay; + wire [1:0] EMIOGEM1TSUINCCTRL_delay; + wire [1:0] EMIOGEM2TSUINCCTRL_delay; + wire [1:0] EMIOGEM3TSUINCCTRL_delay; + wire [1:0] MAXIGP0BRESP_delay; + wire [1:0] MAXIGP0RRESP_delay; + wire [1:0] MAXIGP1BRESP_delay; + wire [1:0] MAXIGP1RRESP_delay; + wire [1:0] MAXIGP2BRESP_delay; + wire [1:0] MAXIGP2RRESP_delay; + wire [1:0] SACEFPDARBAR_delay; + wire [1:0] SACEFPDARBURST_delay; + wire [1:0] SACEFPDARDOMAIN_delay; + wire [1:0] SACEFPDAWBAR_delay; + wire [1:0] SACEFPDAWBURST_delay; + wire [1:0] SACEFPDAWDOMAIN_delay; + wire [1:0] SAXIACPARBURST_delay; + wire [1:0] SAXIACPARUSER_delay; + wire [1:0] SAXIACPAWBURST_delay; + wire [1:0] SAXIACPAWUSER_delay; + wire [1:0] SAXIGP0ARBURST_delay; + wire [1:0] SAXIGP0AWBURST_delay; + wire [1:0] SAXIGP1ARBURST_delay; + wire [1:0] SAXIGP1AWBURST_delay; + wire [1:0] SAXIGP2ARBURST_delay; + wire [1:0] SAXIGP2AWBURST_delay; + wire [1:0] SAXIGP3ARBURST_delay; + wire [1:0] SAXIGP3AWBURST_delay; + wire [1:0] SAXIGP4ARBURST_delay; + wire [1:0] SAXIGP4AWBURST_delay; + wire [1:0] SAXIGP5ARBURST_delay; + wire [1:0] SAXIGP5AWBURST_delay; + wire [1:0] SAXIGP6ARBURST_delay; + wire [1:0] SAXIGP6AWBURST_delay; + wire [2:0] SACEFPDARPROT_delay; + wire [2:0] SACEFPDARSIZE_delay; + wire [2:0] SACEFPDAWPROT_delay; + wire [2:0] SACEFPDAWSIZE_delay; + wire [2:0] SACEFPDAWSNOOP_delay; + wire [2:0] SAXIACPARPROT_delay; + wire [2:0] SAXIACPARSIZE_delay; + wire [2:0] SAXIACPAWPROT_delay; + wire [2:0] SAXIACPAWSIZE_delay; + wire [2:0] SAXIGP0ARPROT_delay; + wire [2:0] SAXIGP0ARSIZE_delay; + wire [2:0] SAXIGP0AWPROT_delay; + wire [2:0] SAXIGP0AWSIZE_delay; + wire [2:0] SAXIGP1ARPROT_delay; + wire [2:0] SAXIGP1ARSIZE_delay; + wire [2:0] SAXIGP1AWPROT_delay; + wire [2:0] SAXIGP1AWSIZE_delay; + wire [2:0] SAXIGP2ARPROT_delay; + wire [2:0] SAXIGP2ARSIZE_delay; + wire [2:0] SAXIGP2AWPROT_delay; + wire [2:0] SAXIGP2AWSIZE_delay; + wire [2:0] SAXIGP3ARPROT_delay; + wire [2:0] SAXIGP3ARSIZE_delay; + wire [2:0] SAXIGP3AWPROT_delay; + wire [2:0] SAXIGP3AWSIZE_delay; + wire [2:0] SAXIGP4ARPROT_delay; + wire [2:0] SAXIGP4ARSIZE_delay; + wire [2:0] SAXIGP4AWPROT_delay; + wire [2:0] SAXIGP4AWSIZE_delay; + wire [2:0] SAXIGP5ARPROT_delay; + wire [2:0] SAXIGP5ARSIZE_delay; + wire [2:0] SAXIGP5AWPROT_delay; + wire [2:0] SAXIGP5AWSIZE_delay; + wire [2:0] SAXIGP6ARPROT_delay; + wire [2:0] SAXIGP6ARSIZE_delay; + wire [2:0] SAXIGP6AWPROT_delay; + wire [2:0] SAXIGP6AWSIZE_delay; + wire [31:0] DPSAXISAUDIOTDATA_delay; + wire [35:0] DPLIVEGFXPIXEL1IN_delay; + wire [35:0] DPLIVEVIDEOINPIXEL1_delay; + wire [39:0] SAXIACPARADDR_delay; + wire [39:0] SAXIACPAWADDR_delay; + wire [3:0] SACEFPDARCACHE_delay; + wire [3:0] SACEFPDARQOS_delay; + wire [3:0] SACEFPDARREGION_delay; + wire [3:0] SACEFPDARSNOOP_delay; + wire [3:0] SACEFPDAWCACHE_delay; + wire [3:0] SACEFPDAWQOS_delay; + wire [3:0] SACEFPDAWREGION_delay; + wire [3:0] SAXIACPARCACHE_delay; + wire [3:0] SAXIACPARQOS_delay; + wire [3:0] SAXIACPAWCACHE_delay; + wire [3:0] SAXIACPAWQOS_delay; + wire [3:0] SAXIGP0ARCACHE_delay; + wire [3:0] SAXIGP0ARQOS_delay; + wire [3:0] SAXIGP0AWCACHE_delay; + wire [3:0] SAXIGP0AWQOS_delay; + wire [3:0] SAXIGP1ARCACHE_delay; + wire [3:0] SAXIGP1ARQOS_delay; + wire [3:0] SAXIGP1AWCACHE_delay; + wire [3:0] SAXIGP1AWQOS_delay; + wire [3:0] SAXIGP2ARCACHE_delay; + wire [3:0] SAXIGP2ARQOS_delay; + wire [3:0] SAXIGP2AWCACHE_delay; + wire [3:0] SAXIGP2AWQOS_delay; + wire [3:0] SAXIGP3ARCACHE_delay; + wire [3:0] SAXIGP3ARQOS_delay; + wire [3:0] SAXIGP3AWCACHE_delay; + wire [3:0] SAXIGP3AWQOS_delay; + wire [3:0] SAXIGP4ARCACHE_delay; + wire [3:0] SAXIGP4ARQOS_delay; + wire [3:0] SAXIGP4AWCACHE_delay; + wire [3:0] SAXIGP4AWQOS_delay; + wire [3:0] SAXIGP5ARCACHE_delay; + wire [3:0] SAXIGP5ARQOS_delay; + wire [3:0] SAXIGP5AWCACHE_delay; + wire [3:0] SAXIGP5AWQOS_delay; + wire [3:0] SAXIGP6ARCACHE_delay; + wire [3:0] SAXIGP6ARQOS_delay; + wire [3:0] SAXIGP6AWCACHE_delay; + wire [3:0] SAXIGP6AWQOS_delay; + wire [43:0] SACEFPDARADDR_delay; + wire [43:0] SACEFPDAWADDR_delay; + wire [48:0] SAXIGP0ARADDR_delay; + wire [48:0] SAXIGP0AWADDR_delay; + wire [48:0] SAXIGP1ARADDR_delay; + wire [48:0] SAXIGP1AWADDR_delay; + wire [48:0] SAXIGP2ARADDR_delay; + wire [48:0] SAXIGP2AWADDR_delay; + wire [48:0] SAXIGP3ARADDR_delay; + wire [48:0] SAXIGP3AWADDR_delay; + wire [48:0] SAXIGP4ARADDR_delay; + wire [48:0] SAXIGP4AWADDR_delay; + wire [48:0] SAXIGP5ARADDR_delay; + wire [48:0] SAXIGP5AWADDR_delay; + wire [48:0] SAXIGP6ARADDR_delay; + wire [48:0] SAXIGP6AWADDR_delay; + wire [4:0] SACEFPDCRRESP_delay; + wire [4:0] SAXIACPARID_delay; + wire [4:0] SAXIACPAWID_delay; + wire [5:0] SACEFPDARID_delay; + wire [5:0] SACEFPDAWID_delay; + wire [5:0] SAXIGP0ARID_delay; + wire [5:0] SAXIGP0AWID_delay; + wire [5:0] SAXIGP1ARID_delay; + wire [5:0] SAXIGP1AWID_delay; + wire [5:0] SAXIGP2ARID_delay; + wire [5:0] SAXIGP2AWID_delay; + wire [5:0] SAXIGP3ARID_delay; + wire [5:0] SAXIGP3AWID_delay; + wire [5:0] SAXIGP4ARID_delay; + wire [5:0] SAXIGP4AWID_delay; + wire [5:0] SAXIGP5ARID_delay; + wire [5:0] SAXIGP5AWID_delay; + wire [5:0] SAXIGP6ARID_delay; + wire [5:0] SAXIGP6AWID_delay; + wire [7:0] ADMAFCICLK_delay; + wire [7:0] DPLIVEGFXALPHAIN_delay; + wire [7:0] EMIOENET0GMIIRXD_delay; + wire [7:0] EMIOENET0TXRDATA_delay; + wire [7:0] EMIOENET1GMIIRXD_delay; + wire [7:0] EMIOENET1TXRDATA_delay; + wire [7:0] EMIOENET2GMIIRXD_delay; + wire [7:0] EMIOENET2TXRDATA_delay; + wire [7:0] EMIOENET3GMIIRXD_delay; + wire [7:0] EMIOENET3TXRDATA_delay; + wire [7:0] GDMAFCICLK_delay; + wire [7:0] PL2ADMACVLD_delay; + wire [7:0] PL2ADMATACK_delay; + wire [7:0] PL2GDMACVLD_delay; + wire [7:0] PL2GDMATACK_delay; + wire [7:0] SACEFPDARLEN_delay; + wire [7:0] SACEFPDAWLEN_delay; + wire [7:0] SAXIACPARLEN_delay; + wire [7:0] SAXIACPAWLEN_delay; + wire [7:0] SAXIGP0ARLEN_delay; + wire [7:0] SAXIGP0AWLEN_delay; + wire [7:0] SAXIGP1ARLEN_delay; + wire [7:0] SAXIGP1AWLEN_delay; + wire [7:0] SAXIGP2ARLEN_delay; + wire [7:0] SAXIGP2AWLEN_delay; + wire [7:0] SAXIGP3ARLEN_delay; + wire [7:0] SAXIGP3AWLEN_delay; + wire [7:0] SAXIGP4ARLEN_delay; + wire [7:0] SAXIGP4AWLEN_delay; + wire [7:0] SAXIGP5ARLEN_delay; + wire [7:0] SAXIGP5AWLEN_delay; + wire [7:0] SAXIGP6ARLEN_delay; + wire [7:0] SAXIGP6AWLEN_delay; +`endif + + assign ADMA2PLCACK = ADMA2PLCACK_out; + assign ADMA2PLTVLD = ADMA2PLTVLD_out; + assign DPAUDIOREFCLK = DPAUDIOREFCLK_out; + assign DPAUXDATAOEN = DPAUXDATAOEN_out; + assign DPAUXDATAOUT = DPAUXDATAOUT_out; + assign DPLIVEVIDEODEOUT = DPLIVEVIDEODEOUT_out; + assign DPMAXISMIXEDAUDIOTDATA = DPMAXISMIXEDAUDIOTDATA_out; + assign DPMAXISMIXEDAUDIOTID = DPMAXISMIXEDAUDIOTID_out; + assign DPMAXISMIXEDAUDIOTVALID = DPMAXISMIXEDAUDIOTVALID_out; + assign DPSAXISAUDIOTREADY = DPSAXISAUDIOTREADY_out; + assign DPVIDEOOUTHSYNC = DPVIDEOOUTHSYNC_out; + assign DPVIDEOOUTPIXEL1 = DPVIDEOOUTPIXEL1_out; + assign DPVIDEOOUTVSYNC = DPVIDEOOUTVSYNC_out; + assign DPVIDEOREFCLK = DPVIDEOREFCLK_out; + assign EMIOCAN0PHYTX = EMIOCAN0PHYTX_out; + assign EMIOCAN1PHYTX = EMIOCAN1PHYTX_out; + assign EMIOENET0DMABUSWIDTH = EMIOENET0DMABUSWIDTH_out; + assign EMIOENET0DMATXENDTOG = EMIOENET0DMATXENDTOG_out; + assign EMIOENET0GEMTSUTIMERCNT = EMIOENET0GEMTSUTIMERCNT_out; + assign EMIOENET0GMIITXD = EMIOENET0GMIITXD_out; + assign EMIOENET0GMIITXEN = EMIOENET0GMIITXEN_out; + assign EMIOENET0GMIITXER = EMIOENET0GMIITXER_out; + assign EMIOENET0MDIOMDC = EMIOENET0MDIOMDC_out; + assign EMIOENET0MDIOO = EMIOENET0MDIOO_out; + assign EMIOENET0MDIOTN = EMIOENET0MDIOTN_out; + assign EMIOENET0RXWDATA = EMIOENET0RXWDATA_out; + assign EMIOENET0RXWEOP = EMIOENET0RXWEOP_out; + assign EMIOENET0RXWERR = EMIOENET0RXWERR_out; + assign EMIOENET0RXWFLUSH = EMIOENET0RXWFLUSH_out; + assign EMIOENET0RXWSOP = EMIOENET0RXWSOP_out; + assign EMIOENET0RXWSTATUS = EMIOENET0RXWSTATUS_out; + assign EMIOENET0RXWWR = EMIOENET0RXWWR_out; + assign EMIOENET0SPEEDMODE = EMIOENET0SPEEDMODE_out; + assign EMIOENET0TXRRD = EMIOENET0TXRRD_out; + assign EMIOENET0TXRSTATUS = EMIOENET0TXRSTATUS_out; + assign EMIOENET1DMABUSWIDTH = EMIOENET1DMABUSWIDTH_out; + assign EMIOENET1DMATXENDTOG = EMIOENET1DMATXENDTOG_out; + assign EMIOENET1GMIITXD = EMIOENET1GMIITXD_out; + assign EMIOENET1GMIITXEN = EMIOENET1GMIITXEN_out; + assign EMIOENET1GMIITXER = EMIOENET1GMIITXER_out; + assign EMIOENET1MDIOMDC = EMIOENET1MDIOMDC_out; + assign EMIOENET1MDIOO = EMIOENET1MDIOO_out; + assign EMIOENET1MDIOTN = EMIOENET1MDIOTN_out; + assign EMIOENET1RXWDATA = EMIOENET1RXWDATA_out; + assign EMIOENET1RXWEOP = EMIOENET1RXWEOP_out; + assign EMIOENET1RXWERR = EMIOENET1RXWERR_out; + assign EMIOENET1RXWFLUSH = EMIOENET1RXWFLUSH_out; + assign EMIOENET1RXWSOP = EMIOENET1RXWSOP_out; + assign EMIOENET1RXWSTATUS = EMIOENET1RXWSTATUS_out; + assign EMIOENET1RXWWR = EMIOENET1RXWWR_out; + assign EMIOENET1SPEEDMODE = EMIOENET1SPEEDMODE_out; + assign EMIOENET1TXRRD = EMIOENET1TXRRD_out; + assign EMIOENET1TXRSTATUS = EMIOENET1TXRSTATUS_out; + assign EMIOENET2DMABUSWIDTH = EMIOENET2DMABUSWIDTH_out; + assign EMIOENET2DMATXENDTOG = EMIOENET2DMATXENDTOG_out; + assign EMIOENET2GMIITXD = EMIOENET2GMIITXD_out; + assign EMIOENET2GMIITXEN = EMIOENET2GMIITXEN_out; + assign EMIOENET2GMIITXER = EMIOENET2GMIITXER_out; + assign EMIOENET2MDIOMDC = EMIOENET2MDIOMDC_out; + assign EMIOENET2MDIOO = EMIOENET2MDIOO_out; + assign EMIOENET2MDIOTN = EMIOENET2MDIOTN_out; + assign EMIOENET2RXWDATA = EMIOENET2RXWDATA_out; + assign EMIOENET2RXWEOP = EMIOENET2RXWEOP_out; + assign EMIOENET2RXWERR = EMIOENET2RXWERR_out; + assign EMIOENET2RXWFLUSH = EMIOENET2RXWFLUSH_out; + assign EMIOENET2RXWSOP = EMIOENET2RXWSOP_out; + assign EMIOENET2RXWSTATUS = EMIOENET2RXWSTATUS_out; + assign EMIOENET2RXWWR = EMIOENET2RXWWR_out; + assign EMIOENET2SPEEDMODE = EMIOENET2SPEEDMODE_out; + assign EMIOENET2TXRRD = EMIOENET2TXRRD_out; + assign EMIOENET2TXRSTATUS = EMIOENET2TXRSTATUS_out; + assign EMIOENET3DMABUSWIDTH = EMIOENET3DMABUSWIDTH_out; + assign EMIOENET3DMATXENDTOG = EMIOENET3DMATXENDTOG_out; + assign EMIOENET3GMIITXD = EMIOENET3GMIITXD_out; + assign EMIOENET3GMIITXEN = EMIOENET3GMIITXEN_out; + assign EMIOENET3GMIITXER = EMIOENET3GMIITXER_out; + assign EMIOENET3MDIOMDC = EMIOENET3MDIOMDC_out; + assign EMIOENET3MDIOO = EMIOENET3MDIOO_out; + assign EMIOENET3MDIOTN = EMIOENET3MDIOTN_out; + assign EMIOENET3RXWDATA = EMIOENET3RXWDATA_out; + assign EMIOENET3RXWEOP = EMIOENET3RXWEOP_out; + assign EMIOENET3RXWERR = EMIOENET3RXWERR_out; + assign EMIOENET3RXWFLUSH = EMIOENET3RXWFLUSH_out; + assign EMIOENET3RXWSOP = EMIOENET3RXWSOP_out; + assign EMIOENET3RXWSTATUS = EMIOENET3RXWSTATUS_out; + assign EMIOENET3RXWWR = EMIOENET3RXWWR_out; + assign EMIOENET3SPEEDMODE = EMIOENET3SPEEDMODE_out; + assign EMIOENET3TXRRD = EMIOENET3TXRRD_out; + assign EMIOENET3TXRSTATUS = EMIOENET3TXRSTATUS_out; + assign EMIOGEM0DELAYREQRX = EMIOGEM0DELAYREQRX_out; + assign EMIOGEM0DELAYREQTX = EMIOGEM0DELAYREQTX_out; + assign EMIOGEM0PDELAYREQRX = EMIOGEM0PDELAYREQRX_out; + assign EMIOGEM0PDELAYREQTX = EMIOGEM0PDELAYREQTX_out; + assign EMIOGEM0PDELAYRESPRX = EMIOGEM0PDELAYRESPRX_out; + assign EMIOGEM0PDELAYRESPTX = EMIOGEM0PDELAYRESPTX_out; + assign EMIOGEM0RXSOF = EMIOGEM0RXSOF_out; + assign EMIOGEM0SYNCFRAMERX = EMIOGEM0SYNCFRAMERX_out; + assign EMIOGEM0SYNCFRAMETX = EMIOGEM0SYNCFRAMETX_out; + assign EMIOGEM0TSUTIMERCMPVAL = EMIOGEM0TSUTIMERCMPVAL_out; + assign EMIOGEM0TXRFIXEDLAT = EMIOGEM0TXRFIXEDLAT_out; + assign EMIOGEM0TXSOF = EMIOGEM0TXSOF_out; + assign EMIOGEM1DELAYREQRX = EMIOGEM1DELAYREQRX_out; + assign EMIOGEM1DELAYREQTX = EMIOGEM1DELAYREQTX_out; + assign EMIOGEM1PDELAYREQRX = EMIOGEM1PDELAYREQRX_out; + assign EMIOGEM1PDELAYREQTX = EMIOGEM1PDELAYREQTX_out; + assign EMIOGEM1PDELAYRESPRX = EMIOGEM1PDELAYRESPRX_out; + assign EMIOGEM1PDELAYRESPTX = EMIOGEM1PDELAYRESPTX_out; + assign EMIOGEM1RXSOF = EMIOGEM1RXSOF_out; + assign EMIOGEM1SYNCFRAMERX = EMIOGEM1SYNCFRAMERX_out; + assign EMIOGEM1SYNCFRAMETX = EMIOGEM1SYNCFRAMETX_out; + assign EMIOGEM1TSUTIMERCMPVAL = EMIOGEM1TSUTIMERCMPVAL_out; + assign EMIOGEM1TXRFIXEDLAT = EMIOGEM1TXRFIXEDLAT_out; + assign EMIOGEM1TXSOF = EMIOGEM1TXSOF_out; + assign EMIOGEM2DELAYREQRX = EMIOGEM2DELAYREQRX_out; + assign EMIOGEM2DELAYREQTX = EMIOGEM2DELAYREQTX_out; + assign EMIOGEM2PDELAYREQRX = EMIOGEM2PDELAYREQRX_out; + assign EMIOGEM2PDELAYREQTX = EMIOGEM2PDELAYREQTX_out; + assign EMIOGEM2PDELAYRESPRX = EMIOGEM2PDELAYRESPRX_out; + assign EMIOGEM2PDELAYRESPTX = EMIOGEM2PDELAYRESPTX_out; + assign EMIOGEM2RXSOF = EMIOGEM2RXSOF_out; + assign EMIOGEM2SYNCFRAMERX = EMIOGEM2SYNCFRAMERX_out; + assign EMIOGEM2SYNCFRAMETX = EMIOGEM2SYNCFRAMETX_out; + assign EMIOGEM2TSUTIMERCMPVAL = EMIOGEM2TSUTIMERCMPVAL_out; + assign EMIOGEM2TXRFIXEDLAT = EMIOGEM2TXRFIXEDLAT_out; + assign EMIOGEM2TXSOF = EMIOGEM2TXSOF_out; + assign EMIOGEM3DELAYREQRX = EMIOGEM3DELAYREQRX_out; + assign EMIOGEM3DELAYREQTX = EMIOGEM3DELAYREQTX_out; + assign EMIOGEM3PDELAYREQRX = EMIOGEM3PDELAYREQRX_out; + assign EMIOGEM3PDELAYREQTX = EMIOGEM3PDELAYREQTX_out; + assign EMIOGEM3PDELAYRESPRX = EMIOGEM3PDELAYRESPRX_out; + assign EMIOGEM3PDELAYRESPTX = EMIOGEM3PDELAYRESPTX_out; + assign EMIOGEM3RXSOF = EMIOGEM3RXSOF_out; + assign EMIOGEM3SYNCFRAMERX = EMIOGEM3SYNCFRAMERX_out; + assign EMIOGEM3SYNCFRAMETX = EMIOGEM3SYNCFRAMETX_out; + assign EMIOGEM3TSUTIMERCMPVAL = EMIOGEM3TSUTIMERCMPVAL_out; + assign EMIOGEM3TXRFIXEDLAT = EMIOGEM3TXRFIXEDLAT_out; + assign EMIOGEM3TXSOF = EMIOGEM3TXSOF_out; + assign EMIOGPIOO = EMIOGPIOO_out; + assign EMIOGPIOTN = EMIOGPIOTN_out; + assign EMIOI2C0SCLO = EMIOI2C0SCLO_out; + assign EMIOI2C0SCLTN = EMIOI2C0SCLTN_out; + assign EMIOI2C0SDAO = EMIOI2C0SDAO_out; + assign EMIOI2C0SDATN = EMIOI2C0SDATN_out; + assign EMIOI2C1SCLO = EMIOI2C1SCLO_out; + assign EMIOI2C1SCLTN = EMIOI2C1SCLTN_out; + assign EMIOI2C1SDAO = EMIOI2C1SDAO_out; + assign EMIOI2C1SDATN = EMIOI2C1SDATN_out; + assign EMIOSDIO0BUSPOWER = EMIOSDIO0BUSPOWER_out; + assign EMIOSDIO0BUSVOLT = EMIOSDIO0BUSVOLT_out; + assign EMIOSDIO0CLKOUT = EMIOSDIO0CLKOUT_out; + assign EMIOSDIO0CMDENA = EMIOSDIO0CMDENA_out; + assign EMIOSDIO0CMDOUT = EMIOSDIO0CMDOUT_out; + assign EMIOSDIO0DATAENA = EMIOSDIO0DATAENA_out; + assign EMIOSDIO0DATAOUT = EMIOSDIO0DATAOUT_out; + assign EMIOSDIO0LEDCONTROL = EMIOSDIO0LEDCONTROL_out; + assign EMIOSDIO1BUSPOWER = EMIOSDIO1BUSPOWER_out; + assign EMIOSDIO1BUSVOLT = EMIOSDIO1BUSVOLT_out; + assign EMIOSDIO1CLKOUT = EMIOSDIO1CLKOUT_out; + assign EMIOSDIO1CMDENA = EMIOSDIO1CMDENA_out; + assign EMIOSDIO1CMDOUT = EMIOSDIO1CMDOUT_out; + assign EMIOSDIO1DATAENA = EMIOSDIO1DATAENA_out; + assign EMIOSDIO1DATAOUT = EMIOSDIO1DATAOUT_out; + assign EMIOSDIO1LEDCONTROL = EMIOSDIO1LEDCONTROL_out; + assign EMIOSPI0MO = EMIOSPI0MO_out; + assign EMIOSPI0MOTN = EMIOSPI0MOTN_out; + assign EMIOSPI0SCLKO = EMIOSPI0SCLKO_out; + assign EMIOSPI0SCLKTN = EMIOSPI0SCLKTN_out; + assign EMIOSPI0SO = EMIOSPI0SO_out; + assign EMIOSPI0SSNTN = EMIOSPI0SSNTN_out; + assign EMIOSPI0SSON = EMIOSPI0SSON_out; + assign EMIOSPI0STN = EMIOSPI0STN_out; + assign EMIOSPI1MO = EMIOSPI1MO_out; + assign EMIOSPI1MOTN = EMIOSPI1MOTN_out; + assign EMIOSPI1SCLKO = EMIOSPI1SCLKO_out; + assign EMIOSPI1SCLKTN = EMIOSPI1SCLKTN_out; + assign EMIOSPI1SO = EMIOSPI1SO_out; + assign EMIOSPI1SSNTN = EMIOSPI1SSNTN_out; + assign EMIOSPI1SSON = EMIOSPI1SSON_out; + assign EMIOSPI1STN = EMIOSPI1STN_out; + assign EMIOTTC0WAVEO = EMIOTTC0WAVEO_out; + assign EMIOTTC1WAVEO = EMIOTTC1WAVEO_out; + assign EMIOTTC2WAVEO = EMIOTTC2WAVEO_out; + assign EMIOTTC3WAVEO = EMIOTTC3WAVEO_out; + assign EMIOU2DSPORTVBUSCTRLUSB30 = EMIOU2DSPORTVBUSCTRLUSB30_out; + assign EMIOU2DSPORTVBUSCTRLUSB31 = EMIOU2DSPORTVBUSCTRLUSB31_out; + assign EMIOU3DSPORTVBUSCTRLUSB30 = EMIOU3DSPORTVBUSCTRLUSB30_out; + assign EMIOU3DSPORTVBUSCTRLUSB31 = EMIOU3DSPORTVBUSCTRLUSB31_out; + assign EMIOUART0DTRN = EMIOUART0DTRN_out; + assign EMIOUART0RTSN = EMIOUART0RTSN_out; + assign EMIOUART0TX = EMIOUART0TX_out; + assign EMIOUART1DTRN = EMIOUART1DTRN_out; + assign EMIOUART1RTSN = EMIOUART1RTSN_out; + assign EMIOUART1TX = EMIOUART1TX_out; + assign EMIOWDT0RSTO = EMIOWDT0RSTO_out; + assign EMIOWDT1RSTO = EMIOWDT1RSTO_out; + assign FMIOGEM0FIFORXCLKTOPLBUFG = FMIOGEM0FIFORXCLKTOPLBUFG_out; + assign FMIOGEM0FIFOTXCLKTOPLBUFG = FMIOGEM0FIFOTXCLKTOPLBUFG_out; + assign FMIOGEM1FIFORXCLKTOPLBUFG = FMIOGEM1FIFORXCLKTOPLBUFG_out; + assign FMIOGEM1FIFOTXCLKTOPLBUFG = FMIOGEM1FIFOTXCLKTOPLBUFG_out; + assign FMIOGEM2FIFORXCLKTOPLBUFG = FMIOGEM2FIFORXCLKTOPLBUFG_out; + assign FMIOGEM2FIFOTXCLKTOPLBUFG = FMIOGEM2FIFOTXCLKTOPLBUFG_out; + assign FMIOGEM3FIFORXCLKTOPLBUFG = FMIOGEM3FIFORXCLKTOPLBUFG_out; + assign FMIOGEM3FIFOTXCLKTOPLBUFG = FMIOGEM3FIFOTXCLKTOPLBUFG_out; + assign FMIOGEMTSUCLKTOPLBUFG = FMIOGEMTSUCLKTOPLBUFG_out; + assign FTMGPO = FTMGPO_out; + assign GDMA2PLCACK = GDMA2PLCACK_out; + assign GDMA2PLTVLD = GDMA2PLTVLD_out; + assign MAXIGP0ARADDR = MAXIGP0ARADDR_out; + assign MAXIGP0ARBURST = MAXIGP0ARBURST_out; + assign MAXIGP0ARCACHE = MAXIGP0ARCACHE_out; + assign MAXIGP0ARID = MAXIGP0ARID_out; + assign MAXIGP0ARLEN = MAXIGP0ARLEN_out; + assign MAXIGP0ARLOCK = MAXIGP0ARLOCK_out; + assign MAXIGP0ARPROT = MAXIGP0ARPROT_out; + assign MAXIGP0ARQOS = MAXIGP0ARQOS_out; + assign MAXIGP0ARSIZE = MAXIGP0ARSIZE_out; + assign MAXIGP0ARUSER = MAXIGP0ARUSER_out; + assign MAXIGP0ARVALID = MAXIGP0ARVALID_out; + assign MAXIGP0AWADDR = MAXIGP0AWADDR_out; + assign MAXIGP0AWBURST = MAXIGP0AWBURST_out; + assign MAXIGP0AWCACHE = MAXIGP0AWCACHE_out; + assign MAXIGP0AWID = MAXIGP0AWID_out; + assign MAXIGP0AWLEN = MAXIGP0AWLEN_out; + assign MAXIGP0AWLOCK = MAXIGP0AWLOCK_out; + assign MAXIGP0AWPROT = MAXIGP0AWPROT_out; + assign MAXIGP0AWQOS = MAXIGP0AWQOS_out; + assign MAXIGP0AWSIZE = MAXIGP0AWSIZE_out; + assign MAXIGP0AWUSER = MAXIGP0AWUSER_out; + assign MAXIGP0AWVALID = MAXIGP0AWVALID_out; + assign MAXIGP0BREADY = MAXIGP0BREADY_out; + assign MAXIGP0RREADY = MAXIGP0RREADY_out; + assign MAXIGP0WDATA = MAXIGP0WDATA_out; + assign MAXIGP0WLAST = MAXIGP0WLAST_out; + assign MAXIGP0WSTRB = MAXIGP0WSTRB_out; + assign MAXIGP0WVALID = MAXIGP0WVALID_out; + assign MAXIGP1ARADDR = MAXIGP1ARADDR_out; + assign MAXIGP1ARBURST = MAXIGP1ARBURST_out; + assign MAXIGP1ARCACHE = MAXIGP1ARCACHE_out; + assign MAXIGP1ARID = MAXIGP1ARID_out; + assign MAXIGP1ARLEN = MAXIGP1ARLEN_out; + assign MAXIGP1ARLOCK = MAXIGP1ARLOCK_out; + assign MAXIGP1ARPROT = MAXIGP1ARPROT_out; + assign MAXIGP1ARQOS = MAXIGP1ARQOS_out; + assign MAXIGP1ARSIZE = MAXIGP1ARSIZE_out; + assign MAXIGP1ARUSER = MAXIGP1ARUSER_out; + assign MAXIGP1ARVALID = MAXIGP1ARVALID_out; + assign MAXIGP1AWADDR = MAXIGP1AWADDR_out; + assign MAXIGP1AWBURST = MAXIGP1AWBURST_out; + assign MAXIGP1AWCACHE = MAXIGP1AWCACHE_out; + assign MAXIGP1AWID = MAXIGP1AWID_out; + assign MAXIGP1AWLEN = MAXIGP1AWLEN_out; + assign MAXIGP1AWLOCK = MAXIGP1AWLOCK_out; + assign MAXIGP1AWPROT = MAXIGP1AWPROT_out; + assign MAXIGP1AWQOS = MAXIGP1AWQOS_out; + assign MAXIGP1AWSIZE = MAXIGP1AWSIZE_out; + assign MAXIGP1AWUSER = MAXIGP1AWUSER_out; + assign MAXIGP1AWVALID = MAXIGP1AWVALID_out; + assign MAXIGP1BREADY = MAXIGP1BREADY_out; + assign MAXIGP1RREADY = MAXIGP1RREADY_out; + assign MAXIGP1WDATA = MAXIGP1WDATA_out; + assign MAXIGP1WLAST = MAXIGP1WLAST_out; + assign MAXIGP1WSTRB = MAXIGP1WSTRB_out; + assign MAXIGP1WVALID = MAXIGP1WVALID_out; + assign MAXIGP2ARADDR = MAXIGP2ARADDR_out; + assign MAXIGP2ARBURST = MAXIGP2ARBURST_out; + assign MAXIGP2ARCACHE = MAXIGP2ARCACHE_out; + assign MAXIGP2ARID = MAXIGP2ARID_out; + assign MAXIGP2ARLEN = MAXIGP2ARLEN_out; + assign MAXIGP2ARLOCK = MAXIGP2ARLOCK_out; + assign MAXIGP2ARPROT = MAXIGP2ARPROT_out; + assign MAXIGP2ARQOS = MAXIGP2ARQOS_out; + assign MAXIGP2ARSIZE = MAXIGP2ARSIZE_out; + assign MAXIGP2ARUSER = MAXIGP2ARUSER_out; + assign MAXIGP2ARVALID = MAXIGP2ARVALID_out; + assign MAXIGP2AWADDR = MAXIGP2AWADDR_out; + assign MAXIGP2AWBURST = MAXIGP2AWBURST_out; + assign MAXIGP2AWCACHE = MAXIGP2AWCACHE_out; + assign MAXIGP2AWID = MAXIGP2AWID_out; + assign MAXIGP2AWLEN = MAXIGP2AWLEN_out; + assign MAXIGP2AWLOCK = MAXIGP2AWLOCK_out; + assign MAXIGP2AWPROT = MAXIGP2AWPROT_out; + assign MAXIGP2AWQOS = MAXIGP2AWQOS_out; + assign MAXIGP2AWSIZE = MAXIGP2AWSIZE_out; + assign MAXIGP2AWUSER = MAXIGP2AWUSER_out; + assign MAXIGP2AWVALID = MAXIGP2AWVALID_out; + assign MAXIGP2BREADY = MAXIGP2BREADY_out; + assign MAXIGP2RREADY = MAXIGP2RREADY_out; + assign MAXIGP2WDATA = MAXIGP2WDATA_out; + assign MAXIGP2WLAST = MAXIGP2WLAST_out; + assign MAXIGP2WSTRB = MAXIGP2WSTRB_out; + assign MAXIGP2WVALID = MAXIGP2WVALID_out; + assign OSCRTCCLK = OSCRTCCLK_out; + assign PLCLK = PLCLK_out; + assign PMUAIBAFIFMFPDREQ = PMUAIBAFIFMFPDREQ_out; + assign PMUAIBAFIFMLPDREQ = PMUAIBAFIFMLPDREQ_out; + assign PMUERRORTOPL = PMUERRORTOPL_out; + assign PMUPLGPO = PMUPLGPO_out; + assign PSPLEVENTO = PSPLEVENTO_out; + assign PSPLIRQFPD = PSPLIRQFPD_out; + assign PSPLIRQLPD = PSPLIRQLPD_out; + assign PSPLSTANDBYWFE = PSPLSTANDBYWFE_out; + assign PSPLSTANDBYWFI = PSPLSTANDBYWFI_out; + assign PSPLTRACECTL = PSPLTRACECTL_out; + assign PSPLTRACEDATA = PSPLTRACEDATA_out; + assign PSPLTRIGACK = PSPLTRIGACK_out; + assign PSPLTRIGGER = PSPLTRIGGER_out; + assign PSS_ALTO_CORE_PAD_MGTTXN0OUT = PSS_ALTO_CORE_PAD_MGTTXN0OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXN1OUT = PSS_ALTO_CORE_PAD_MGTTXN1OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXN2OUT = PSS_ALTO_CORE_PAD_MGTTXN2OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXN3OUT = PSS_ALTO_CORE_PAD_MGTTXN3OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXP0OUT = PSS_ALTO_CORE_PAD_MGTTXP0OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXP1OUT = PSS_ALTO_CORE_PAD_MGTTXP1OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXP2OUT = PSS_ALTO_CORE_PAD_MGTTXP2OUT_out; + assign PSS_ALTO_CORE_PAD_MGTTXP3OUT = PSS_ALTO_CORE_PAD_MGTTXP3OUT_out; + assign PSS_ALTO_CORE_PAD_PADO = PSS_ALTO_CORE_PAD_PADO_out; + assign RPUEVENTO0 = RPUEVENTO0_out; + assign RPUEVENTO1 = RPUEVENTO1_out; + assign SACEFPDACADDR = SACEFPDACADDR_out; + assign SACEFPDACPROT = SACEFPDACPROT_out; + assign SACEFPDACSNOOP = SACEFPDACSNOOP_out; + assign SACEFPDACVALID = SACEFPDACVALID_out; + assign SACEFPDARREADY = SACEFPDARREADY_out; + assign SACEFPDAWREADY = SACEFPDAWREADY_out; + assign SACEFPDBID = SACEFPDBID_out; + assign SACEFPDBRESP = SACEFPDBRESP_out; + assign SACEFPDBUSER = SACEFPDBUSER_out; + assign SACEFPDBVALID = SACEFPDBVALID_out; + assign SACEFPDCDREADY = SACEFPDCDREADY_out; + assign SACEFPDCRREADY = SACEFPDCRREADY_out; + assign SACEFPDRDATA = SACEFPDRDATA_out; + assign SACEFPDRID = SACEFPDRID_out; + assign SACEFPDRLAST = SACEFPDRLAST_out; + assign SACEFPDRRESP = SACEFPDRRESP_out; + assign SACEFPDRUSER = SACEFPDRUSER_out; + assign SACEFPDRVALID = SACEFPDRVALID_out; + assign SACEFPDWREADY = SACEFPDWREADY_out; + assign SAXIACPARREADY = SAXIACPARREADY_out; + assign SAXIACPAWREADY = SAXIACPAWREADY_out; + assign SAXIACPBID = SAXIACPBID_out; + assign SAXIACPBRESP = SAXIACPBRESP_out; + assign SAXIACPBVALID = SAXIACPBVALID_out; + assign SAXIACPRDATA = SAXIACPRDATA_out; + assign SAXIACPRID = SAXIACPRID_out; + assign SAXIACPRLAST = SAXIACPRLAST_out; + assign SAXIACPRRESP = SAXIACPRRESP_out; + assign SAXIACPRVALID = SAXIACPRVALID_out; + assign SAXIACPWREADY = SAXIACPWREADY_out; + assign SAXIGP0ARREADY = SAXIGP0ARREADY_out; + assign SAXIGP0AWREADY = SAXIGP0AWREADY_out; + assign SAXIGP0BID = SAXIGP0BID_out; + assign SAXIGP0BRESP = SAXIGP0BRESP_out; + assign SAXIGP0BVALID = SAXIGP0BVALID_out; + assign SAXIGP0RACOUNT = SAXIGP0RACOUNT_out; + assign SAXIGP0RCOUNT = SAXIGP0RCOUNT_out; + assign SAXIGP0RDATA = SAXIGP0RDATA_out; + assign SAXIGP0RID = SAXIGP0RID_out; + assign SAXIGP0RLAST = SAXIGP0RLAST_out; + assign SAXIGP0RRESP = SAXIGP0RRESP_out; + assign SAXIGP0RVALID = SAXIGP0RVALID_out; + assign SAXIGP0WACOUNT = SAXIGP0WACOUNT_out; + assign SAXIGP0WCOUNT = SAXIGP0WCOUNT_out; + assign SAXIGP0WREADY = SAXIGP0WREADY_out; + assign SAXIGP1ARREADY = SAXIGP1ARREADY_out; + assign SAXIGP1AWREADY = SAXIGP1AWREADY_out; + assign SAXIGP1BID = SAXIGP1BID_out; + assign SAXIGP1BRESP = SAXIGP1BRESP_out; + assign SAXIGP1BVALID = SAXIGP1BVALID_out; + assign SAXIGP1RACOUNT = SAXIGP1RACOUNT_out; + assign SAXIGP1RCOUNT = SAXIGP1RCOUNT_out; + assign SAXIGP1RDATA = SAXIGP1RDATA_out; + assign SAXIGP1RID = SAXIGP1RID_out; + assign SAXIGP1RLAST = SAXIGP1RLAST_out; + assign SAXIGP1RRESP = SAXIGP1RRESP_out; + assign SAXIGP1RVALID = SAXIGP1RVALID_out; + assign SAXIGP1WACOUNT = SAXIGP1WACOUNT_out; + assign SAXIGP1WCOUNT = SAXIGP1WCOUNT_out; + assign SAXIGP1WREADY = SAXIGP1WREADY_out; + assign SAXIGP2ARREADY = SAXIGP2ARREADY_out; + assign SAXIGP2AWREADY = SAXIGP2AWREADY_out; + assign SAXIGP2BID = SAXIGP2BID_out; + assign SAXIGP2BRESP = SAXIGP2BRESP_out; + assign SAXIGP2BVALID = SAXIGP2BVALID_out; + assign SAXIGP2RACOUNT = SAXIGP2RACOUNT_out; + assign SAXIGP2RCOUNT = SAXIGP2RCOUNT_out; + assign SAXIGP2RDATA = SAXIGP2RDATA_out; + assign SAXIGP2RID = SAXIGP2RID_out; + assign SAXIGP2RLAST = SAXIGP2RLAST_out; + assign SAXIGP2RRESP = SAXIGP2RRESP_out; + assign SAXIGP2RVALID = SAXIGP2RVALID_out; + assign SAXIGP2WACOUNT = SAXIGP2WACOUNT_out; + assign SAXIGP2WCOUNT = SAXIGP2WCOUNT_out; + assign SAXIGP2WREADY = SAXIGP2WREADY_out; + assign SAXIGP3ARREADY = SAXIGP3ARREADY_out; + assign SAXIGP3AWREADY = SAXIGP3AWREADY_out; + assign SAXIGP3BID = SAXIGP3BID_out; + assign SAXIGP3BRESP = SAXIGP3BRESP_out; + assign SAXIGP3BVALID = SAXIGP3BVALID_out; + assign SAXIGP3RACOUNT = SAXIGP3RACOUNT_out; + assign SAXIGP3RCOUNT = SAXIGP3RCOUNT_out; + assign SAXIGP3RDATA = SAXIGP3RDATA_out; + assign SAXIGP3RID = SAXIGP3RID_out; + assign SAXIGP3RLAST = SAXIGP3RLAST_out; + assign SAXIGP3RRESP = SAXIGP3RRESP_out; + assign SAXIGP3RVALID = SAXIGP3RVALID_out; + assign SAXIGP3WACOUNT = SAXIGP3WACOUNT_out; + assign SAXIGP3WCOUNT = SAXIGP3WCOUNT_out; + assign SAXIGP3WREADY = SAXIGP3WREADY_out; + assign SAXIGP4ARREADY = SAXIGP4ARREADY_out; + assign SAXIGP4AWREADY = SAXIGP4AWREADY_out; + assign SAXIGP4BID = SAXIGP4BID_out; + assign SAXIGP4BRESP = SAXIGP4BRESP_out; + assign SAXIGP4BVALID = SAXIGP4BVALID_out; + assign SAXIGP4RACOUNT = SAXIGP4RACOUNT_out; + assign SAXIGP4RCOUNT = SAXIGP4RCOUNT_out; + assign SAXIGP4RDATA = SAXIGP4RDATA_out; + assign SAXIGP4RID = SAXIGP4RID_out; + assign SAXIGP4RLAST = SAXIGP4RLAST_out; + assign SAXIGP4RRESP = SAXIGP4RRESP_out; + assign SAXIGP4RVALID = SAXIGP4RVALID_out; + assign SAXIGP4WACOUNT = SAXIGP4WACOUNT_out; + assign SAXIGP4WCOUNT = SAXIGP4WCOUNT_out; + assign SAXIGP4WREADY = SAXIGP4WREADY_out; + assign SAXIGP5ARREADY = SAXIGP5ARREADY_out; + assign SAXIGP5AWREADY = SAXIGP5AWREADY_out; + assign SAXIGP5BID = SAXIGP5BID_out; + assign SAXIGP5BRESP = SAXIGP5BRESP_out; + assign SAXIGP5BVALID = SAXIGP5BVALID_out; + assign SAXIGP5RACOUNT = SAXIGP5RACOUNT_out; + assign SAXIGP5RCOUNT = SAXIGP5RCOUNT_out; + assign SAXIGP5RDATA = SAXIGP5RDATA_out; + assign SAXIGP5RID = SAXIGP5RID_out; + assign SAXIGP5RLAST = SAXIGP5RLAST_out; + assign SAXIGP5RRESP = SAXIGP5RRESP_out; + assign SAXIGP5RVALID = SAXIGP5RVALID_out; + assign SAXIGP5WACOUNT = SAXIGP5WACOUNT_out; + assign SAXIGP5WCOUNT = SAXIGP5WCOUNT_out; + assign SAXIGP5WREADY = SAXIGP5WREADY_out; + assign SAXIGP6ARREADY = SAXIGP6ARREADY_out; + assign SAXIGP6AWREADY = SAXIGP6AWREADY_out; + assign SAXIGP6BID = SAXIGP6BID_out; + assign SAXIGP6BRESP = SAXIGP6BRESP_out; + assign SAXIGP6BVALID = SAXIGP6BVALID_out; + assign SAXIGP6RACOUNT = SAXIGP6RACOUNT_out; + assign SAXIGP6RCOUNT = SAXIGP6RCOUNT_out; + assign SAXIGP6RDATA = SAXIGP6RDATA_out; + assign SAXIGP6RID = SAXIGP6RID_out; + assign SAXIGP6RLAST = SAXIGP6RLAST_out; + assign SAXIGP6RRESP = SAXIGP6RRESP_out; + assign SAXIGP6RVALID = SAXIGP6RVALID_out; + assign SAXIGP6WACOUNT = SAXIGP6WACOUNT_out; + assign SAXIGP6WCOUNT = SAXIGP6WCOUNT_out; + assign SAXIGP6WREADY = SAXIGP6WREADY_out; + +`ifdef XIL_TIMING + assign ADMAFCICLK_in[0] = (ADMAFCICLK[0] !== 1'bz) && ADMAFCICLK_delay[0]; // rv 0 + assign ADMAFCICLK_in[1] = (ADMAFCICLK[1] !== 1'bz) && ADMAFCICLK_delay[1]; // rv 0 + assign ADMAFCICLK_in[2] = (ADMAFCICLK[2] !== 1'bz) && ADMAFCICLK_delay[2]; // rv 0 + assign ADMAFCICLK_in[3] = (ADMAFCICLK[3] !== 1'bz) && ADMAFCICLK_delay[3]; // rv 0 + assign ADMAFCICLK_in[4] = (ADMAFCICLK[4] !== 1'bz) && ADMAFCICLK_delay[4]; // rv 0 + assign ADMAFCICLK_in[5] = (ADMAFCICLK[5] !== 1'bz) && ADMAFCICLK_delay[5]; // rv 0 + assign ADMAFCICLK_in[6] = (ADMAFCICLK[6] !== 1'bz) && ADMAFCICLK_delay[6]; // rv 0 + assign ADMAFCICLK_in[7] = (ADMAFCICLK[7] !== 1'bz) && ADMAFCICLK_delay[7]; // rv 0 + assign DDRCEXTREFRESHRANK0REQ_in = (DDRCEXTREFRESHRANK0REQ !== 1'bz) && DDRCEXTREFRESHRANK0REQ_delay; // rv 0 + assign DDRCEXTREFRESHRANK1REQ_in = (DDRCEXTREFRESHRANK1REQ !== 1'bz) && DDRCEXTREFRESHRANK1REQ_delay; // rv 0 + assign DDRCREFRESHPLCLK_in = (DDRCREFRESHPLCLK !== 1'bz) && DDRCREFRESHPLCLK_delay; // rv 0 + assign DPLIVEGFXALPHAIN_in[0] = (DPLIVEGFXALPHAIN[0] !== 1'bz) && DPLIVEGFXALPHAIN_delay[0]; // rv 0 + assign DPLIVEGFXALPHAIN_in[1] = (DPLIVEGFXALPHAIN[1] !== 1'bz) && DPLIVEGFXALPHAIN_delay[1]; // rv 0 + assign DPLIVEGFXALPHAIN_in[2] = (DPLIVEGFXALPHAIN[2] !== 1'bz) && DPLIVEGFXALPHAIN_delay[2]; // rv 0 + assign DPLIVEGFXALPHAIN_in[3] = (DPLIVEGFXALPHAIN[3] !== 1'bz) && DPLIVEGFXALPHAIN_delay[3]; // rv 0 + assign DPLIVEGFXALPHAIN_in[4] = (DPLIVEGFXALPHAIN[4] !== 1'bz) && DPLIVEGFXALPHAIN_delay[4]; // rv 0 + assign DPLIVEGFXALPHAIN_in[5] = (DPLIVEGFXALPHAIN[5] !== 1'bz) && DPLIVEGFXALPHAIN_delay[5]; // rv 0 + assign DPLIVEGFXALPHAIN_in[6] = (DPLIVEGFXALPHAIN[6] !== 1'bz) && DPLIVEGFXALPHAIN_delay[6]; // rv 0 + assign DPLIVEGFXALPHAIN_in[7] = (DPLIVEGFXALPHAIN[7] !== 1'bz) && DPLIVEGFXALPHAIN_delay[7]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[0] = (DPLIVEGFXPIXEL1IN[0] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[0]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[10] = (DPLIVEGFXPIXEL1IN[10] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[10]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[11] = (DPLIVEGFXPIXEL1IN[11] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[11]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[12] = (DPLIVEGFXPIXEL1IN[12] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[12]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[13] = (DPLIVEGFXPIXEL1IN[13] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[13]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[14] = (DPLIVEGFXPIXEL1IN[14] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[14]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[15] = (DPLIVEGFXPIXEL1IN[15] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[15]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[16] = (DPLIVEGFXPIXEL1IN[16] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[16]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[17] = (DPLIVEGFXPIXEL1IN[17] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[17]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[18] = (DPLIVEGFXPIXEL1IN[18] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[18]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[19] = (DPLIVEGFXPIXEL1IN[19] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[19]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[1] = (DPLIVEGFXPIXEL1IN[1] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[1]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[20] = (DPLIVEGFXPIXEL1IN[20] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[20]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[21] = (DPLIVEGFXPIXEL1IN[21] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[21]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[22] = (DPLIVEGFXPIXEL1IN[22] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[22]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[23] = (DPLIVEGFXPIXEL1IN[23] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[23]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[24] = (DPLIVEGFXPIXEL1IN[24] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[24]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[25] = (DPLIVEGFXPIXEL1IN[25] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[25]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[26] = (DPLIVEGFXPIXEL1IN[26] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[26]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[27] = (DPLIVEGFXPIXEL1IN[27] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[27]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[28] = (DPLIVEGFXPIXEL1IN[28] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[28]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[29] = (DPLIVEGFXPIXEL1IN[29] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[29]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[2] = (DPLIVEGFXPIXEL1IN[2] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[2]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[30] = (DPLIVEGFXPIXEL1IN[30] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[30]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[31] = (DPLIVEGFXPIXEL1IN[31] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[31]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[32] = (DPLIVEGFXPIXEL1IN[32] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[32]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[33] = (DPLIVEGFXPIXEL1IN[33] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[33]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[34] = (DPLIVEGFXPIXEL1IN[34] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[34]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[35] = (DPLIVEGFXPIXEL1IN[35] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[35]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[3] = (DPLIVEGFXPIXEL1IN[3] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[3]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[4] = (DPLIVEGFXPIXEL1IN[4] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[4]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[5] = (DPLIVEGFXPIXEL1IN[5] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[5]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[6] = (DPLIVEGFXPIXEL1IN[6] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[6]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[7] = (DPLIVEGFXPIXEL1IN[7] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[7]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[8] = (DPLIVEGFXPIXEL1IN[8] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[8]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[9] = (DPLIVEGFXPIXEL1IN[9] !== 1'bz) && DPLIVEGFXPIXEL1IN_delay[9]; // rv 0 + assign DPLIVEVIDEOINDE_in = (DPLIVEVIDEOINDE !== 1'bz) && DPLIVEVIDEOINDE_delay; // rv 0 + assign DPLIVEVIDEOINHSYNC_in = (DPLIVEVIDEOINHSYNC !== 1'bz) && DPLIVEVIDEOINHSYNC_delay; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[0] = (DPLIVEVIDEOINPIXEL1[0] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[0]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[10] = (DPLIVEVIDEOINPIXEL1[10] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[10]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[11] = (DPLIVEVIDEOINPIXEL1[11] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[11]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[12] = (DPLIVEVIDEOINPIXEL1[12] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[12]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[13] = (DPLIVEVIDEOINPIXEL1[13] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[13]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[14] = (DPLIVEVIDEOINPIXEL1[14] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[14]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[15] = (DPLIVEVIDEOINPIXEL1[15] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[15]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[16] = (DPLIVEVIDEOINPIXEL1[16] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[16]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[17] = (DPLIVEVIDEOINPIXEL1[17] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[17]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[18] = (DPLIVEVIDEOINPIXEL1[18] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[18]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[19] = (DPLIVEVIDEOINPIXEL1[19] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[19]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[1] = (DPLIVEVIDEOINPIXEL1[1] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[1]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[20] = (DPLIVEVIDEOINPIXEL1[20] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[20]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[21] = (DPLIVEVIDEOINPIXEL1[21] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[21]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[22] = (DPLIVEVIDEOINPIXEL1[22] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[22]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[23] = (DPLIVEVIDEOINPIXEL1[23] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[23]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[24] = (DPLIVEVIDEOINPIXEL1[24] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[24]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[25] = (DPLIVEVIDEOINPIXEL1[25] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[25]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[26] = (DPLIVEVIDEOINPIXEL1[26] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[26]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[27] = (DPLIVEVIDEOINPIXEL1[27] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[27]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[28] = (DPLIVEVIDEOINPIXEL1[28] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[28]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[29] = (DPLIVEVIDEOINPIXEL1[29] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[29]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[2] = (DPLIVEVIDEOINPIXEL1[2] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[2]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[30] = (DPLIVEVIDEOINPIXEL1[30] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[30]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[31] = (DPLIVEVIDEOINPIXEL1[31] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[31]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[32] = (DPLIVEVIDEOINPIXEL1[32] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[32]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[33] = (DPLIVEVIDEOINPIXEL1[33] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[33]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[34] = (DPLIVEVIDEOINPIXEL1[34] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[34]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[35] = (DPLIVEVIDEOINPIXEL1[35] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[35]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[3] = (DPLIVEVIDEOINPIXEL1[3] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[3]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[4] = (DPLIVEVIDEOINPIXEL1[4] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[4]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[5] = (DPLIVEVIDEOINPIXEL1[5] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[5]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[6] = (DPLIVEVIDEOINPIXEL1[6] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[6]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[7] = (DPLIVEVIDEOINPIXEL1[7] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[7]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[8] = (DPLIVEVIDEOINPIXEL1[8] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[8]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[9] = (DPLIVEVIDEOINPIXEL1[9] !== 1'bz) && DPLIVEVIDEOINPIXEL1_delay[9]; // rv 0 + assign DPLIVEVIDEOINVSYNC_in = (DPLIVEVIDEOINVSYNC !== 1'bz) && DPLIVEVIDEOINVSYNC_delay; // rv 0 + assign DPMAXISMIXEDAUDIOTREADY_in = (DPMAXISMIXEDAUDIOTREADY !== 1'bz) && DPMAXISMIXEDAUDIOTREADY_delay; // rv 0 + assign DPSAXISAUDIOCLK_in = (DPSAXISAUDIOCLK === 1'bz) || DPSAXISAUDIOCLK_delay; // rv 1 + assign DPSAXISAUDIOTDATA_in[0] = (DPSAXISAUDIOTDATA[0] !== 1'bz) && DPSAXISAUDIOTDATA_delay[0]; // rv 0 + assign DPSAXISAUDIOTDATA_in[10] = (DPSAXISAUDIOTDATA[10] !== 1'bz) && DPSAXISAUDIOTDATA_delay[10]; // rv 0 + assign DPSAXISAUDIOTDATA_in[11] = (DPSAXISAUDIOTDATA[11] !== 1'bz) && DPSAXISAUDIOTDATA_delay[11]; // rv 0 + assign DPSAXISAUDIOTDATA_in[12] = (DPSAXISAUDIOTDATA[12] !== 1'bz) && DPSAXISAUDIOTDATA_delay[12]; // rv 0 + assign DPSAXISAUDIOTDATA_in[13] = (DPSAXISAUDIOTDATA[13] !== 1'bz) && DPSAXISAUDIOTDATA_delay[13]; // rv 0 + assign DPSAXISAUDIOTDATA_in[14] = (DPSAXISAUDIOTDATA[14] !== 1'bz) && DPSAXISAUDIOTDATA_delay[14]; // rv 0 + assign DPSAXISAUDIOTDATA_in[15] = (DPSAXISAUDIOTDATA[15] !== 1'bz) && DPSAXISAUDIOTDATA_delay[15]; // rv 0 + assign DPSAXISAUDIOTDATA_in[16] = (DPSAXISAUDIOTDATA[16] !== 1'bz) && DPSAXISAUDIOTDATA_delay[16]; // rv 0 + assign DPSAXISAUDIOTDATA_in[17] = (DPSAXISAUDIOTDATA[17] !== 1'bz) && DPSAXISAUDIOTDATA_delay[17]; // rv 0 + assign DPSAXISAUDIOTDATA_in[18] = (DPSAXISAUDIOTDATA[18] !== 1'bz) && DPSAXISAUDIOTDATA_delay[18]; // rv 0 + assign DPSAXISAUDIOTDATA_in[19] = (DPSAXISAUDIOTDATA[19] !== 1'bz) && DPSAXISAUDIOTDATA_delay[19]; // rv 0 + assign DPSAXISAUDIOTDATA_in[1] = (DPSAXISAUDIOTDATA[1] !== 1'bz) && DPSAXISAUDIOTDATA_delay[1]; // rv 0 + assign DPSAXISAUDIOTDATA_in[20] = (DPSAXISAUDIOTDATA[20] !== 1'bz) && DPSAXISAUDIOTDATA_delay[20]; // rv 0 + assign DPSAXISAUDIOTDATA_in[21] = (DPSAXISAUDIOTDATA[21] !== 1'bz) && DPSAXISAUDIOTDATA_delay[21]; // rv 0 + assign DPSAXISAUDIOTDATA_in[22] = (DPSAXISAUDIOTDATA[22] !== 1'bz) && DPSAXISAUDIOTDATA_delay[22]; // rv 0 + assign DPSAXISAUDIOTDATA_in[23] = (DPSAXISAUDIOTDATA[23] !== 1'bz) && DPSAXISAUDIOTDATA_delay[23]; // rv 0 + assign DPSAXISAUDIOTDATA_in[24] = (DPSAXISAUDIOTDATA[24] !== 1'bz) && DPSAXISAUDIOTDATA_delay[24]; // rv 0 + assign DPSAXISAUDIOTDATA_in[25] = (DPSAXISAUDIOTDATA[25] !== 1'bz) && DPSAXISAUDIOTDATA_delay[25]; // rv 0 + assign DPSAXISAUDIOTDATA_in[26] = (DPSAXISAUDIOTDATA[26] !== 1'bz) && DPSAXISAUDIOTDATA_delay[26]; // rv 0 + assign DPSAXISAUDIOTDATA_in[27] = (DPSAXISAUDIOTDATA[27] !== 1'bz) && DPSAXISAUDIOTDATA_delay[27]; // rv 0 + assign DPSAXISAUDIOTDATA_in[28] = (DPSAXISAUDIOTDATA[28] !== 1'bz) && DPSAXISAUDIOTDATA_delay[28]; // rv 0 + assign DPSAXISAUDIOTDATA_in[29] = (DPSAXISAUDIOTDATA[29] !== 1'bz) && DPSAXISAUDIOTDATA_delay[29]; // rv 0 + assign DPSAXISAUDIOTDATA_in[2] = (DPSAXISAUDIOTDATA[2] !== 1'bz) && DPSAXISAUDIOTDATA_delay[2]; // rv 0 + assign DPSAXISAUDIOTDATA_in[30] = (DPSAXISAUDIOTDATA[30] !== 1'bz) && DPSAXISAUDIOTDATA_delay[30]; // rv 0 + assign DPSAXISAUDIOTDATA_in[31] = (DPSAXISAUDIOTDATA[31] !== 1'bz) && DPSAXISAUDIOTDATA_delay[31]; // rv 0 + assign DPSAXISAUDIOTDATA_in[3] = (DPSAXISAUDIOTDATA[3] !== 1'bz) && DPSAXISAUDIOTDATA_delay[3]; // rv 0 + assign DPSAXISAUDIOTDATA_in[4] = (DPSAXISAUDIOTDATA[4] !== 1'bz) && DPSAXISAUDIOTDATA_delay[4]; // rv 0 + assign DPSAXISAUDIOTDATA_in[5] = (DPSAXISAUDIOTDATA[5] !== 1'bz) && DPSAXISAUDIOTDATA_delay[5]; // rv 0 + assign DPSAXISAUDIOTDATA_in[6] = (DPSAXISAUDIOTDATA[6] !== 1'bz) && DPSAXISAUDIOTDATA_delay[6]; // rv 0 + assign DPSAXISAUDIOTDATA_in[7] = (DPSAXISAUDIOTDATA[7] !== 1'bz) && DPSAXISAUDIOTDATA_delay[7]; // rv 0 + assign DPSAXISAUDIOTDATA_in[8] = (DPSAXISAUDIOTDATA[8] !== 1'bz) && DPSAXISAUDIOTDATA_delay[8]; // rv 0 + assign DPSAXISAUDIOTDATA_in[9] = (DPSAXISAUDIOTDATA[9] !== 1'bz) && DPSAXISAUDIOTDATA_delay[9]; // rv 0 + assign DPSAXISAUDIOTID_in = (DPSAXISAUDIOTID !== 1'bz) && DPSAXISAUDIOTID_delay; // rv 0 + assign DPSAXISAUDIOTVALID_in = (DPSAXISAUDIOTVALID !== 1'bz) && DPSAXISAUDIOTVALID_delay; // rv 0 + assign DPVIDEOINCLK_in = (DPVIDEOINCLK === 1'bz) || DPVIDEOINCLK_delay; // rv 1 + assign EMIOENET0GMIIRXCLK_in = (EMIOENET0GMIIRXCLK !== 1'bz) && EMIOENET0GMIIRXCLK_delay; // rv 0 + assign EMIOENET0GMIIRXDV_in = (EMIOENET0GMIIRXDV !== 1'bz) && EMIOENET0GMIIRXDV_delay; // rv 0 + assign EMIOENET0GMIIRXD_in[0] = (EMIOENET0GMIIRXD[0] !== 1'bz) && EMIOENET0GMIIRXD_delay[0]; // rv 0 + assign EMIOENET0GMIIRXD_in[1] = (EMIOENET0GMIIRXD[1] !== 1'bz) && EMIOENET0GMIIRXD_delay[1]; // rv 0 + assign EMIOENET0GMIIRXD_in[2] = (EMIOENET0GMIIRXD[2] !== 1'bz) && EMIOENET0GMIIRXD_delay[2]; // rv 0 + assign EMIOENET0GMIIRXD_in[3] = (EMIOENET0GMIIRXD[3] !== 1'bz) && EMIOENET0GMIIRXD_delay[3]; // rv 0 + assign EMIOENET0GMIIRXD_in[4] = (EMIOENET0GMIIRXD[4] !== 1'bz) && EMIOENET0GMIIRXD_delay[4]; // rv 0 + assign EMIOENET0GMIIRXD_in[5] = (EMIOENET0GMIIRXD[5] !== 1'bz) && EMIOENET0GMIIRXD_delay[5]; // rv 0 + assign EMIOENET0GMIIRXD_in[6] = (EMIOENET0GMIIRXD[6] !== 1'bz) && EMIOENET0GMIIRXD_delay[6]; // rv 0 + assign EMIOENET0GMIIRXD_in[7] = (EMIOENET0GMIIRXD[7] !== 1'bz) && EMIOENET0GMIIRXD_delay[7]; // rv 0 + assign EMIOENET0GMIIRXER_in = (EMIOENET0GMIIRXER !== 1'bz) && EMIOENET0GMIIRXER_delay; // rv 0 + assign EMIOENET0TXRCONTROL_in = (EMIOENET0TXRCONTROL !== 1'bz) && EMIOENET0TXRCONTROL_delay; // rv 0 + assign EMIOENET0TXRDATARDY_in = (EMIOENET0TXRDATARDY !== 1'bz) && EMIOENET0TXRDATARDY_delay; // rv 0 + assign EMIOENET0TXRDATA_in[0] = (EMIOENET0TXRDATA[0] !== 1'bz) && EMIOENET0TXRDATA_delay[0]; // rv 0 + assign EMIOENET0TXRDATA_in[1] = (EMIOENET0TXRDATA[1] !== 1'bz) && EMIOENET0TXRDATA_delay[1]; // rv 0 + assign EMIOENET0TXRDATA_in[2] = (EMIOENET0TXRDATA[2] !== 1'bz) && EMIOENET0TXRDATA_delay[2]; // rv 0 + assign EMIOENET0TXRDATA_in[3] = (EMIOENET0TXRDATA[3] !== 1'bz) && EMIOENET0TXRDATA_delay[3]; // rv 0 + assign EMIOENET0TXRDATA_in[4] = (EMIOENET0TXRDATA[4] !== 1'bz) && EMIOENET0TXRDATA_delay[4]; // rv 0 + assign EMIOENET0TXRDATA_in[5] = (EMIOENET0TXRDATA[5] !== 1'bz) && EMIOENET0TXRDATA_delay[5]; // rv 0 + assign EMIOENET0TXRDATA_in[6] = (EMIOENET0TXRDATA[6] !== 1'bz) && EMIOENET0TXRDATA_delay[6]; // rv 0 + assign EMIOENET0TXRDATA_in[7] = (EMIOENET0TXRDATA[7] !== 1'bz) && EMIOENET0TXRDATA_delay[7]; // rv 0 + assign EMIOENET0TXREOP_in = (EMIOENET0TXREOP === 1'bz) || EMIOENET0TXREOP_delay; // rv 1 + assign EMIOENET0TXRERR_in = (EMIOENET0TXRERR !== 1'bz) && EMIOENET0TXRERR_delay; // rv 0 + assign EMIOENET0TXRFLUSHED_in = (EMIOENET0TXRFLUSHED !== 1'bz) && EMIOENET0TXRFLUSHED_delay; // rv 0 + assign EMIOENET0TXRSOP_in = (EMIOENET0TXRSOP === 1'bz) || EMIOENET0TXRSOP_delay; // rv 1 + assign EMIOENET0TXRUNDERFLOW_in = (EMIOENET0TXRUNDERFLOW !== 1'bz) && EMIOENET0TXRUNDERFLOW_delay; // rv 0 + assign EMIOENET0TXRVALID_in = (EMIOENET0TXRVALID !== 1'bz) && EMIOENET0TXRVALID_delay; // rv 0 + assign EMIOENET1GMIIRXCLK_in = (EMIOENET1GMIIRXCLK !== 1'bz) && EMIOENET1GMIIRXCLK_delay; // rv 0 + assign EMIOENET1GMIIRXDV_in = (EMIOENET1GMIIRXDV !== 1'bz) && EMIOENET1GMIIRXDV_delay; // rv 0 + assign EMIOENET1GMIIRXD_in[0] = (EMIOENET1GMIIRXD[0] !== 1'bz) && EMIOENET1GMIIRXD_delay[0]; // rv 0 + assign EMIOENET1GMIIRXD_in[1] = (EMIOENET1GMIIRXD[1] !== 1'bz) && EMIOENET1GMIIRXD_delay[1]; // rv 0 + assign EMIOENET1GMIIRXD_in[2] = (EMIOENET1GMIIRXD[2] !== 1'bz) && EMIOENET1GMIIRXD_delay[2]; // rv 0 + assign EMIOENET1GMIIRXD_in[3] = (EMIOENET1GMIIRXD[3] !== 1'bz) && EMIOENET1GMIIRXD_delay[3]; // rv 0 + assign EMIOENET1GMIIRXD_in[4] = (EMIOENET1GMIIRXD[4] !== 1'bz) && EMIOENET1GMIIRXD_delay[4]; // rv 0 + assign EMIOENET1GMIIRXD_in[5] = (EMIOENET1GMIIRXD[5] !== 1'bz) && EMIOENET1GMIIRXD_delay[5]; // rv 0 + assign EMIOENET1GMIIRXD_in[6] = (EMIOENET1GMIIRXD[6] !== 1'bz) && EMIOENET1GMIIRXD_delay[6]; // rv 0 + assign EMIOENET1GMIIRXD_in[7] = (EMIOENET1GMIIRXD[7] !== 1'bz) && EMIOENET1GMIIRXD_delay[7]; // rv 0 + assign EMIOENET1GMIIRXER_in = (EMIOENET1GMIIRXER !== 1'bz) && EMIOENET1GMIIRXER_delay; // rv 0 + assign EMIOENET1TXRCONTROL_in = (EMIOENET1TXRCONTROL !== 1'bz) && EMIOENET1TXRCONTROL_delay; // rv 0 + assign EMIOENET1TXRDATARDY_in = (EMIOENET1TXRDATARDY !== 1'bz) && EMIOENET1TXRDATARDY_delay; // rv 0 + assign EMIOENET1TXRDATA_in[0] = (EMIOENET1TXRDATA[0] !== 1'bz) && EMIOENET1TXRDATA_delay[0]; // rv 0 + assign EMIOENET1TXRDATA_in[1] = (EMIOENET1TXRDATA[1] !== 1'bz) && EMIOENET1TXRDATA_delay[1]; // rv 0 + assign EMIOENET1TXRDATA_in[2] = (EMIOENET1TXRDATA[2] !== 1'bz) && EMIOENET1TXRDATA_delay[2]; // rv 0 + assign EMIOENET1TXRDATA_in[3] = (EMIOENET1TXRDATA[3] !== 1'bz) && EMIOENET1TXRDATA_delay[3]; // rv 0 + assign EMIOENET1TXRDATA_in[4] = (EMIOENET1TXRDATA[4] !== 1'bz) && EMIOENET1TXRDATA_delay[4]; // rv 0 + assign EMIOENET1TXRDATA_in[5] = (EMIOENET1TXRDATA[5] !== 1'bz) && EMIOENET1TXRDATA_delay[5]; // rv 0 + assign EMIOENET1TXRDATA_in[6] = (EMIOENET1TXRDATA[6] !== 1'bz) && EMIOENET1TXRDATA_delay[6]; // rv 0 + assign EMIOENET1TXRDATA_in[7] = (EMIOENET1TXRDATA[7] !== 1'bz) && EMIOENET1TXRDATA_delay[7]; // rv 0 + assign EMIOENET1TXREOP_in = (EMIOENET1TXREOP === 1'bz) || EMIOENET1TXREOP_delay; // rv 1 + assign EMIOENET1TXRERR_in = (EMIOENET1TXRERR !== 1'bz) && EMIOENET1TXRERR_delay; // rv 0 + assign EMIOENET1TXRFLUSHED_in = (EMIOENET1TXRFLUSHED !== 1'bz) && EMIOENET1TXRFLUSHED_delay; // rv 0 + assign EMIOENET1TXRSOP_in = (EMIOENET1TXRSOP === 1'bz) || EMIOENET1TXRSOP_delay; // rv 1 + assign EMIOENET1TXRUNDERFLOW_in = (EMIOENET1TXRUNDERFLOW !== 1'bz) && EMIOENET1TXRUNDERFLOW_delay; // rv 0 + assign EMIOENET1TXRVALID_in = (EMIOENET1TXRVALID !== 1'bz) && EMIOENET1TXRVALID_delay; // rv 0 + assign EMIOENET2GMIIRXCLK_in = (EMIOENET2GMIIRXCLK !== 1'bz) && EMIOENET2GMIIRXCLK_delay; // rv 0 + assign EMIOENET2GMIIRXDV_in = (EMIOENET2GMIIRXDV !== 1'bz) && EMIOENET2GMIIRXDV_delay; // rv 0 + assign EMIOENET2GMIIRXD_in[0] = (EMIOENET2GMIIRXD[0] !== 1'bz) && EMIOENET2GMIIRXD_delay[0]; // rv 0 + assign EMIOENET2GMIIRXD_in[1] = (EMIOENET2GMIIRXD[1] !== 1'bz) && EMIOENET2GMIIRXD_delay[1]; // rv 0 + assign EMIOENET2GMIIRXD_in[2] = (EMIOENET2GMIIRXD[2] !== 1'bz) && EMIOENET2GMIIRXD_delay[2]; // rv 0 + assign EMIOENET2GMIIRXD_in[3] = (EMIOENET2GMIIRXD[3] !== 1'bz) && EMIOENET2GMIIRXD_delay[3]; // rv 0 + assign EMIOENET2GMIIRXD_in[4] = (EMIOENET2GMIIRXD[4] !== 1'bz) && EMIOENET2GMIIRXD_delay[4]; // rv 0 + assign EMIOENET2GMIIRXD_in[5] = (EMIOENET2GMIIRXD[5] !== 1'bz) && EMIOENET2GMIIRXD_delay[5]; // rv 0 + assign EMIOENET2GMIIRXD_in[6] = (EMIOENET2GMIIRXD[6] !== 1'bz) && EMIOENET2GMIIRXD_delay[6]; // rv 0 + assign EMIOENET2GMIIRXD_in[7] = (EMIOENET2GMIIRXD[7] !== 1'bz) && EMIOENET2GMIIRXD_delay[7]; // rv 0 + assign EMIOENET2GMIIRXER_in = (EMIOENET2GMIIRXER !== 1'bz) && EMIOENET2GMIIRXER_delay; // rv 0 + assign EMIOENET2TXRCONTROL_in = (EMIOENET2TXRCONTROL !== 1'bz) && EMIOENET2TXRCONTROL_delay; // rv 0 + assign EMIOENET2TXRDATARDY_in = (EMIOENET2TXRDATARDY !== 1'bz) && EMIOENET2TXRDATARDY_delay; // rv 0 + assign EMIOENET2TXRDATA_in[0] = (EMIOENET2TXRDATA[0] !== 1'bz) && EMIOENET2TXRDATA_delay[0]; // rv 0 + assign EMIOENET2TXRDATA_in[1] = (EMIOENET2TXRDATA[1] !== 1'bz) && EMIOENET2TXRDATA_delay[1]; // rv 0 + assign EMIOENET2TXRDATA_in[2] = (EMIOENET2TXRDATA[2] !== 1'bz) && EMIOENET2TXRDATA_delay[2]; // rv 0 + assign EMIOENET2TXRDATA_in[3] = (EMIOENET2TXRDATA[3] !== 1'bz) && EMIOENET2TXRDATA_delay[3]; // rv 0 + assign EMIOENET2TXRDATA_in[4] = (EMIOENET2TXRDATA[4] !== 1'bz) && EMIOENET2TXRDATA_delay[4]; // rv 0 + assign EMIOENET2TXRDATA_in[5] = (EMIOENET2TXRDATA[5] !== 1'bz) && EMIOENET2TXRDATA_delay[5]; // rv 0 + assign EMIOENET2TXRDATA_in[6] = (EMIOENET2TXRDATA[6] !== 1'bz) && EMIOENET2TXRDATA_delay[6]; // rv 0 + assign EMIOENET2TXRDATA_in[7] = (EMIOENET2TXRDATA[7] !== 1'bz) && EMIOENET2TXRDATA_delay[7]; // rv 0 + assign EMIOENET2TXREOP_in = (EMIOENET2TXREOP === 1'bz) || EMIOENET2TXREOP_delay; // rv 1 + assign EMIOENET2TXRERR_in = (EMIOENET2TXRERR !== 1'bz) && EMIOENET2TXRERR_delay; // rv 0 + assign EMIOENET2TXRFLUSHED_in = (EMIOENET2TXRFLUSHED !== 1'bz) && EMIOENET2TXRFLUSHED_delay; // rv 0 + assign EMIOENET2TXRSOP_in = (EMIOENET2TXRSOP === 1'bz) || EMIOENET2TXRSOP_delay; // rv 1 + assign EMIOENET2TXRUNDERFLOW_in = (EMIOENET2TXRUNDERFLOW !== 1'bz) && EMIOENET2TXRUNDERFLOW_delay; // rv 0 + assign EMIOENET2TXRVALID_in = (EMIOENET2TXRVALID !== 1'bz) && EMIOENET2TXRVALID_delay; // rv 0 + assign EMIOENET3GMIIRXCLK_in = (EMIOENET3GMIIRXCLK !== 1'bz) && EMIOENET3GMIIRXCLK_delay; // rv 0 + assign EMIOENET3GMIIRXDV_in = (EMIOENET3GMIIRXDV !== 1'bz) && EMIOENET3GMIIRXDV_delay; // rv 0 + assign EMIOENET3GMIIRXD_in[0] = (EMIOENET3GMIIRXD[0] !== 1'bz) && EMIOENET3GMIIRXD_delay[0]; // rv 0 + assign EMIOENET3GMIIRXD_in[1] = (EMIOENET3GMIIRXD[1] !== 1'bz) && EMIOENET3GMIIRXD_delay[1]; // rv 0 + assign EMIOENET3GMIIRXD_in[2] = (EMIOENET3GMIIRXD[2] !== 1'bz) && EMIOENET3GMIIRXD_delay[2]; // rv 0 + assign EMIOENET3GMIIRXD_in[3] = (EMIOENET3GMIIRXD[3] !== 1'bz) && EMIOENET3GMIIRXD_delay[3]; // rv 0 + assign EMIOENET3GMIIRXD_in[4] = (EMIOENET3GMIIRXD[4] !== 1'bz) && EMIOENET3GMIIRXD_delay[4]; // rv 0 + assign EMIOENET3GMIIRXD_in[5] = (EMIOENET3GMIIRXD[5] !== 1'bz) && EMIOENET3GMIIRXD_delay[5]; // rv 0 + assign EMIOENET3GMIIRXD_in[6] = (EMIOENET3GMIIRXD[6] !== 1'bz) && EMIOENET3GMIIRXD_delay[6]; // rv 0 + assign EMIOENET3GMIIRXD_in[7] = (EMIOENET3GMIIRXD[7] !== 1'bz) && EMIOENET3GMIIRXD_delay[7]; // rv 0 + assign EMIOENET3GMIIRXER_in = (EMIOENET3GMIIRXER !== 1'bz) && EMIOENET3GMIIRXER_delay; // rv 0 + assign EMIOENET3TXRCONTROL_in = (EMIOENET3TXRCONTROL !== 1'bz) && EMIOENET3TXRCONTROL_delay; // rv 0 + assign EMIOENET3TXRDATARDY_in = (EMIOENET3TXRDATARDY !== 1'bz) && EMIOENET3TXRDATARDY_delay; // rv 0 + assign EMIOENET3TXRDATA_in[0] = (EMIOENET3TXRDATA[0] !== 1'bz) && EMIOENET3TXRDATA_delay[0]; // rv 0 + assign EMIOENET3TXRDATA_in[1] = (EMIOENET3TXRDATA[1] !== 1'bz) && EMIOENET3TXRDATA_delay[1]; // rv 0 + assign EMIOENET3TXRDATA_in[2] = (EMIOENET3TXRDATA[2] !== 1'bz) && EMIOENET3TXRDATA_delay[2]; // rv 0 + assign EMIOENET3TXRDATA_in[3] = (EMIOENET3TXRDATA[3] !== 1'bz) && EMIOENET3TXRDATA_delay[3]; // rv 0 + assign EMIOENET3TXRDATA_in[4] = (EMIOENET3TXRDATA[4] !== 1'bz) && EMIOENET3TXRDATA_delay[4]; // rv 0 + assign EMIOENET3TXRDATA_in[5] = (EMIOENET3TXRDATA[5] !== 1'bz) && EMIOENET3TXRDATA_delay[5]; // rv 0 + assign EMIOENET3TXRDATA_in[6] = (EMIOENET3TXRDATA[6] !== 1'bz) && EMIOENET3TXRDATA_delay[6]; // rv 0 + assign EMIOENET3TXRDATA_in[7] = (EMIOENET3TXRDATA[7] !== 1'bz) && EMIOENET3TXRDATA_delay[7]; // rv 0 + assign EMIOENET3TXREOP_in = (EMIOENET3TXREOP === 1'bz) || EMIOENET3TXREOP_delay; // rv 1 + assign EMIOENET3TXRERR_in = (EMIOENET3TXRERR !== 1'bz) && EMIOENET3TXRERR_delay; // rv 0 + assign EMIOENET3TXRFLUSHED_in = (EMIOENET3TXRFLUSHED !== 1'bz) && EMIOENET3TXRFLUSHED_delay; // rv 0 + assign EMIOENET3TXRSOP_in = (EMIOENET3TXRSOP === 1'bz) || EMIOENET3TXRSOP_delay; // rv 1 + assign EMIOENET3TXRUNDERFLOW_in = (EMIOENET3TXRUNDERFLOW !== 1'bz) && EMIOENET3TXRUNDERFLOW_delay; // rv 0 + assign EMIOENET3TXRVALID_in = (EMIOENET3TXRVALID !== 1'bz) && EMIOENET3TXRVALID_delay; // rv 0 + assign EMIOGEM0TSUINCCTRL_in[0] = (EMIOGEM0TSUINCCTRL[0] !== 1'bz) && EMIOGEM0TSUINCCTRL_delay[0]; // rv 0 + assign EMIOGEM0TSUINCCTRL_in[1] = (EMIOGEM0TSUINCCTRL[1] !== 1'bz) && EMIOGEM0TSUINCCTRL_delay[1]; // rv 0 + assign EMIOGEM1TSUINCCTRL_in[0] = (EMIOGEM1TSUINCCTRL[0] !== 1'bz) && EMIOGEM1TSUINCCTRL_delay[0]; // rv 0 + assign EMIOGEM1TSUINCCTRL_in[1] = (EMIOGEM1TSUINCCTRL[1] !== 1'bz) && EMIOGEM1TSUINCCTRL_delay[1]; // rv 0 + assign EMIOGEM2TSUINCCTRL_in[0] = (EMIOGEM2TSUINCCTRL[0] !== 1'bz) && EMIOGEM2TSUINCCTRL_delay[0]; // rv 0 + assign EMIOGEM2TSUINCCTRL_in[1] = (EMIOGEM2TSUINCCTRL[1] !== 1'bz) && EMIOGEM2TSUINCCTRL_delay[1]; // rv 0 + assign EMIOGEM3TSUINCCTRL_in[0] = (EMIOGEM3TSUINCCTRL[0] !== 1'bz) && EMIOGEM3TSUINCCTRL_delay[0]; // rv 0 + assign EMIOGEM3TSUINCCTRL_in[1] = (EMIOGEM3TSUINCCTRL[1] !== 1'bz) && EMIOGEM3TSUINCCTRL_delay[1]; // rv 0 + assign EMIOSPI0SCLKI_in = (EMIOSPI0SCLKI !== 1'bz) && EMIOSPI0SCLKI_delay; // rv 0 + assign EMIOSPI0SSIN_in = (EMIOSPI0SSIN === 1'bz) || EMIOSPI0SSIN_delay; // rv 1 + assign EMIOSPI1SCLKI_in = (EMIOSPI1SCLKI !== 1'bz) && EMIOSPI1SCLKI_delay; // rv 0 + assign EMIOSPI1SSIN_in = (EMIOSPI1SSIN === 1'bz) || EMIOSPI1SSIN_delay; // rv 1 + assign FMIOGEM0FIFOTXCLKFROMPL_in = (FMIOGEM0FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM0FIFOTXCLKFROMPL_delay; // rv 0 + assign FMIOGEM1FIFOTXCLKFROMPL_in = (FMIOGEM1FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM1FIFOTXCLKFROMPL_delay; // rv 0 + assign FMIOGEM2FIFOTXCLKFROMPL_in = (FMIOGEM2FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM2FIFOTXCLKFROMPL_delay; // rv 0 + assign FMIOGEM3FIFOTXCLKFROMPL_in = (FMIOGEM3FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM3FIFOTXCLKFROMPL_delay; // rv 0 + assign FMIOGEMTSUCLKFROMPL_in = (FMIOGEMTSUCLKFROMPL !== 1'bz) && FMIOGEMTSUCLKFROMPL_delay; // rv 0 + assign GDMAFCICLK_in[0] = (GDMAFCICLK[0] !== 1'bz) && GDMAFCICLK_delay[0]; // rv 0 + assign GDMAFCICLK_in[1] = (GDMAFCICLK[1] !== 1'bz) && GDMAFCICLK_delay[1]; // rv 0 + assign GDMAFCICLK_in[2] = (GDMAFCICLK[2] !== 1'bz) && GDMAFCICLK_delay[2]; // rv 0 + assign GDMAFCICLK_in[3] = (GDMAFCICLK[3] !== 1'bz) && GDMAFCICLK_delay[3]; // rv 0 + assign GDMAFCICLK_in[4] = (GDMAFCICLK[4] !== 1'bz) && GDMAFCICLK_delay[4]; // rv 0 + assign GDMAFCICLK_in[5] = (GDMAFCICLK[5] !== 1'bz) && GDMAFCICLK_delay[5]; // rv 0 + assign GDMAFCICLK_in[6] = (GDMAFCICLK[6] !== 1'bz) && GDMAFCICLK_delay[6]; // rv 0 + assign GDMAFCICLK_in[7] = (GDMAFCICLK[7] !== 1'bz) && GDMAFCICLK_delay[7]; // rv 0 + assign MAXIGP0ACLK_in = (MAXIGP0ACLK !== 1'bz) && MAXIGP0ACLK_delay; // rv 0 + assign MAXIGP0ARREADY_in = (MAXIGP0ARREADY !== 1'bz) && MAXIGP0ARREADY_delay; // rv 0 + assign MAXIGP0AWREADY_in = (MAXIGP0AWREADY !== 1'bz) && MAXIGP0AWREADY_delay; // rv 0 + assign MAXIGP0BID_in[0] = (MAXIGP0BID[0] !== 1'bz) && MAXIGP0BID_delay[0]; // rv 0 + assign MAXIGP0BID_in[10] = (MAXIGP0BID[10] !== 1'bz) && MAXIGP0BID_delay[10]; // rv 0 + assign MAXIGP0BID_in[11] = (MAXIGP0BID[11] !== 1'bz) && MAXIGP0BID_delay[11]; // rv 0 + assign MAXIGP0BID_in[12] = (MAXIGP0BID[12] !== 1'bz) && MAXIGP0BID_delay[12]; // rv 0 + assign MAXIGP0BID_in[13] = (MAXIGP0BID[13] !== 1'bz) && MAXIGP0BID_delay[13]; // rv 0 + assign MAXIGP0BID_in[14] = (MAXIGP0BID[14] !== 1'bz) && MAXIGP0BID_delay[14]; // rv 0 + assign MAXIGP0BID_in[15] = (MAXIGP0BID[15] !== 1'bz) && MAXIGP0BID_delay[15]; // rv 0 + assign MAXIGP0BID_in[1] = (MAXIGP0BID[1] !== 1'bz) && MAXIGP0BID_delay[1]; // rv 0 + assign MAXIGP0BID_in[2] = (MAXIGP0BID[2] !== 1'bz) && MAXIGP0BID_delay[2]; // rv 0 + assign MAXIGP0BID_in[3] = (MAXIGP0BID[3] !== 1'bz) && MAXIGP0BID_delay[3]; // rv 0 + assign MAXIGP0BID_in[4] = (MAXIGP0BID[4] !== 1'bz) && MAXIGP0BID_delay[4]; // rv 0 + assign MAXIGP0BID_in[5] = (MAXIGP0BID[5] !== 1'bz) && MAXIGP0BID_delay[5]; // rv 0 + assign MAXIGP0BID_in[6] = (MAXIGP0BID[6] !== 1'bz) && MAXIGP0BID_delay[6]; // rv 0 + assign MAXIGP0BID_in[7] = (MAXIGP0BID[7] !== 1'bz) && MAXIGP0BID_delay[7]; // rv 0 + assign MAXIGP0BID_in[8] = (MAXIGP0BID[8] !== 1'bz) && MAXIGP0BID_delay[8]; // rv 0 + assign MAXIGP0BID_in[9] = (MAXIGP0BID[9] !== 1'bz) && MAXIGP0BID_delay[9]; // rv 0 + assign MAXIGP0BRESP_in[0] = (MAXIGP0BRESP[0] !== 1'bz) && MAXIGP0BRESP_delay[0]; // rv 0 + assign MAXIGP0BRESP_in[1] = (MAXIGP0BRESP[1] !== 1'bz) && MAXIGP0BRESP_delay[1]; // rv 0 + assign MAXIGP0BVALID_in = (MAXIGP0BVALID !== 1'bz) && MAXIGP0BVALID_delay; // rv 0 + assign MAXIGP0RDATA_in[0] = (MAXIGP0RDATA[0] !== 1'bz) && MAXIGP0RDATA_delay[0]; // rv 0 + assign MAXIGP0RDATA_in[100] = (MAXIGP0RDATA[100] !== 1'bz) && MAXIGP0RDATA_delay[100]; // rv 0 + assign MAXIGP0RDATA_in[101] = (MAXIGP0RDATA[101] !== 1'bz) && MAXIGP0RDATA_delay[101]; // rv 0 + assign MAXIGP0RDATA_in[102] = (MAXIGP0RDATA[102] !== 1'bz) && MAXIGP0RDATA_delay[102]; // rv 0 + assign MAXIGP0RDATA_in[103] = (MAXIGP0RDATA[103] !== 1'bz) && MAXIGP0RDATA_delay[103]; // rv 0 + assign MAXIGP0RDATA_in[104] = (MAXIGP0RDATA[104] !== 1'bz) && MAXIGP0RDATA_delay[104]; // rv 0 + assign MAXIGP0RDATA_in[105] = (MAXIGP0RDATA[105] !== 1'bz) && MAXIGP0RDATA_delay[105]; // rv 0 + assign MAXIGP0RDATA_in[106] = (MAXIGP0RDATA[106] !== 1'bz) && MAXIGP0RDATA_delay[106]; // rv 0 + assign MAXIGP0RDATA_in[107] = (MAXIGP0RDATA[107] !== 1'bz) && MAXIGP0RDATA_delay[107]; // rv 0 + assign MAXIGP0RDATA_in[108] = (MAXIGP0RDATA[108] !== 1'bz) && MAXIGP0RDATA_delay[108]; // rv 0 + assign MAXIGP0RDATA_in[109] = (MAXIGP0RDATA[109] !== 1'bz) && MAXIGP0RDATA_delay[109]; // rv 0 + assign MAXIGP0RDATA_in[10] = (MAXIGP0RDATA[10] !== 1'bz) && MAXIGP0RDATA_delay[10]; // rv 0 + assign MAXIGP0RDATA_in[110] = (MAXIGP0RDATA[110] !== 1'bz) && MAXIGP0RDATA_delay[110]; // rv 0 + assign MAXIGP0RDATA_in[111] = (MAXIGP0RDATA[111] !== 1'bz) && MAXIGP0RDATA_delay[111]; // rv 0 + assign MAXIGP0RDATA_in[112] = (MAXIGP0RDATA[112] !== 1'bz) && MAXIGP0RDATA_delay[112]; // rv 0 + assign MAXIGP0RDATA_in[113] = (MAXIGP0RDATA[113] !== 1'bz) && MAXIGP0RDATA_delay[113]; // rv 0 + assign MAXIGP0RDATA_in[114] = (MAXIGP0RDATA[114] !== 1'bz) && MAXIGP0RDATA_delay[114]; // rv 0 + assign MAXIGP0RDATA_in[115] = (MAXIGP0RDATA[115] !== 1'bz) && MAXIGP0RDATA_delay[115]; // rv 0 + assign MAXIGP0RDATA_in[116] = (MAXIGP0RDATA[116] !== 1'bz) && MAXIGP0RDATA_delay[116]; // rv 0 + assign MAXIGP0RDATA_in[117] = (MAXIGP0RDATA[117] !== 1'bz) && MAXIGP0RDATA_delay[117]; // rv 0 + assign MAXIGP0RDATA_in[118] = (MAXIGP0RDATA[118] !== 1'bz) && MAXIGP0RDATA_delay[118]; // rv 0 + assign MAXIGP0RDATA_in[119] = (MAXIGP0RDATA[119] !== 1'bz) && MAXIGP0RDATA_delay[119]; // rv 0 + assign MAXIGP0RDATA_in[11] = (MAXIGP0RDATA[11] !== 1'bz) && MAXIGP0RDATA_delay[11]; // rv 0 + assign MAXIGP0RDATA_in[120] = (MAXIGP0RDATA[120] !== 1'bz) && MAXIGP0RDATA_delay[120]; // rv 0 + assign MAXIGP0RDATA_in[121] = (MAXIGP0RDATA[121] !== 1'bz) && MAXIGP0RDATA_delay[121]; // rv 0 + assign MAXIGP0RDATA_in[122] = (MAXIGP0RDATA[122] !== 1'bz) && MAXIGP0RDATA_delay[122]; // rv 0 + assign MAXIGP0RDATA_in[123] = (MAXIGP0RDATA[123] !== 1'bz) && MAXIGP0RDATA_delay[123]; // rv 0 + assign MAXIGP0RDATA_in[124] = (MAXIGP0RDATA[124] !== 1'bz) && MAXIGP0RDATA_delay[124]; // rv 0 + assign MAXIGP0RDATA_in[125] = (MAXIGP0RDATA[125] !== 1'bz) && MAXIGP0RDATA_delay[125]; // rv 0 + assign MAXIGP0RDATA_in[126] = (MAXIGP0RDATA[126] !== 1'bz) && MAXIGP0RDATA_delay[126]; // rv 0 + assign MAXIGP0RDATA_in[127] = (MAXIGP0RDATA[127] !== 1'bz) && MAXIGP0RDATA_delay[127]; // rv 0 + assign MAXIGP0RDATA_in[12] = (MAXIGP0RDATA[12] !== 1'bz) && MAXIGP0RDATA_delay[12]; // rv 0 + assign MAXIGP0RDATA_in[13] = (MAXIGP0RDATA[13] !== 1'bz) && MAXIGP0RDATA_delay[13]; // rv 0 + assign MAXIGP0RDATA_in[14] = (MAXIGP0RDATA[14] !== 1'bz) && MAXIGP0RDATA_delay[14]; // rv 0 + assign MAXIGP0RDATA_in[15] = (MAXIGP0RDATA[15] !== 1'bz) && MAXIGP0RDATA_delay[15]; // rv 0 + assign MAXIGP0RDATA_in[16] = (MAXIGP0RDATA[16] !== 1'bz) && MAXIGP0RDATA_delay[16]; // rv 0 + assign MAXIGP0RDATA_in[17] = (MAXIGP0RDATA[17] !== 1'bz) && MAXIGP0RDATA_delay[17]; // rv 0 + assign MAXIGP0RDATA_in[18] = (MAXIGP0RDATA[18] !== 1'bz) && MAXIGP0RDATA_delay[18]; // rv 0 + assign MAXIGP0RDATA_in[19] = (MAXIGP0RDATA[19] !== 1'bz) && MAXIGP0RDATA_delay[19]; // rv 0 + assign MAXIGP0RDATA_in[1] = (MAXIGP0RDATA[1] !== 1'bz) && MAXIGP0RDATA_delay[1]; // rv 0 + assign MAXIGP0RDATA_in[20] = (MAXIGP0RDATA[20] !== 1'bz) && MAXIGP0RDATA_delay[20]; // rv 0 + assign MAXIGP0RDATA_in[21] = (MAXIGP0RDATA[21] !== 1'bz) && MAXIGP0RDATA_delay[21]; // rv 0 + assign MAXIGP0RDATA_in[22] = (MAXIGP0RDATA[22] !== 1'bz) && MAXIGP0RDATA_delay[22]; // rv 0 + assign MAXIGP0RDATA_in[23] = (MAXIGP0RDATA[23] !== 1'bz) && MAXIGP0RDATA_delay[23]; // rv 0 + assign MAXIGP0RDATA_in[24] = (MAXIGP0RDATA[24] !== 1'bz) && MAXIGP0RDATA_delay[24]; // rv 0 + assign MAXIGP0RDATA_in[25] = (MAXIGP0RDATA[25] !== 1'bz) && MAXIGP0RDATA_delay[25]; // rv 0 + assign MAXIGP0RDATA_in[26] = (MAXIGP0RDATA[26] !== 1'bz) && MAXIGP0RDATA_delay[26]; // rv 0 + assign MAXIGP0RDATA_in[27] = (MAXIGP0RDATA[27] !== 1'bz) && MAXIGP0RDATA_delay[27]; // rv 0 + assign MAXIGP0RDATA_in[28] = (MAXIGP0RDATA[28] !== 1'bz) && MAXIGP0RDATA_delay[28]; // rv 0 + assign MAXIGP0RDATA_in[29] = (MAXIGP0RDATA[29] !== 1'bz) && MAXIGP0RDATA_delay[29]; // rv 0 + assign MAXIGP0RDATA_in[2] = (MAXIGP0RDATA[2] !== 1'bz) && MAXIGP0RDATA_delay[2]; // rv 0 + assign MAXIGP0RDATA_in[30] = (MAXIGP0RDATA[30] !== 1'bz) && MAXIGP0RDATA_delay[30]; // rv 0 + assign MAXIGP0RDATA_in[31] = (MAXIGP0RDATA[31] !== 1'bz) && MAXIGP0RDATA_delay[31]; // rv 0 + assign MAXIGP0RDATA_in[32] = (MAXIGP0RDATA[32] !== 1'bz) && MAXIGP0RDATA_delay[32]; // rv 0 + assign MAXIGP0RDATA_in[33] = (MAXIGP0RDATA[33] !== 1'bz) && MAXIGP0RDATA_delay[33]; // rv 0 + assign MAXIGP0RDATA_in[34] = (MAXIGP0RDATA[34] !== 1'bz) && MAXIGP0RDATA_delay[34]; // rv 0 + assign MAXIGP0RDATA_in[35] = (MAXIGP0RDATA[35] !== 1'bz) && MAXIGP0RDATA_delay[35]; // rv 0 + assign MAXIGP0RDATA_in[36] = (MAXIGP0RDATA[36] !== 1'bz) && MAXIGP0RDATA_delay[36]; // rv 0 + assign MAXIGP0RDATA_in[37] = (MAXIGP0RDATA[37] !== 1'bz) && MAXIGP0RDATA_delay[37]; // rv 0 + assign MAXIGP0RDATA_in[38] = (MAXIGP0RDATA[38] !== 1'bz) && MAXIGP0RDATA_delay[38]; // rv 0 + assign MAXIGP0RDATA_in[39] = (MAXIGP0RDATA[39] !== 1'bz) && MAXIGP0RDATA_delay[39]; // rv 0 + assign MAXIGP0RDATA_in[3] = (MAXIGP0RDATA[3] !== 1'bz) && MAXIGP0RDATA_delay[3]; // rv 0 + assign MAXIGP0RDATA_in[40] = (MAXIGP0RDATA[40] !== 1'bz) && MAXIGP0RDATA_delay[40]; // rv 0 + assign MAXIGP0RDATA_in[41] = (MAXIGP0RDATA[41] !== 1'bz) && MAXIGP0RDATA_delay[41]; // rv 0 + assign MAXIGP0RDATA_in[42] = (MAXIGP0RDATA[42] !== 1'bz) && MAXIGP0RDATA_delay[42]; // rv 0 + assign MAXIGP0RDATA_in[43] = (MAXIGP0RDATA[43] !== 1'bz) && MAXIGP0RDATA_delay[43]; // rv 0 + assign MAXIGP0RDATA_in[44] = (MAXIGP0RDATA[44] !== 1'bz) && MAXIGP0RDATA_delay[44]; // rv 0 + assign MAXIGP0RDATA_in[45] = (MAXIGP0RDATA[45] !== 1'bz) && MAXIGP0RDATA_delay[45]; // rv 0 + assign MAXIGP0RDATA_in[46] = (MAXIGP0RDATA[46] !== 1'bz) && MAXIGP0RDATA_delay[46]; // rv 0 + assign MAXIGP0RDATA_in[47] = (MAXIGP0RDATA[47] !== 1'bz) && MAXIGP0RDATA_delay[47]; // rv 0 + assign MAXIGP0RDATA_in[48] = (MAXIGP0RDATA[48] !== 1'bz) && MAXIGP0RDATA_delay[48]; // rv 0 + assign MAXIGP0RDATA_in[49] = (MAXIGP0RDATA[49] !== 1'bz) && MAXIGP0RDATA_delay[49]; // rv 0 + assign MAXIGP0RDATA_in[4] = (MAXIGP0RDATA[4] !== 1'bz) && MAXIGP0RDATA_delay[4]; // rv 0 + assign MAXIGP0RDATA_in[50] = (MAXIGP0RDATA[50] !== 1'bz) && MAXIGP0RDATA_delay[50]; // rv 0 + assign MAXIGP0RDATA_in[51] = (MAXIGP0RDATA[51] !== 1'bz) && MAXIGP0RDATA_delay[51]; // rv 0 + assign MAXIGP0RDATA_in[52] = (MAXIGP0RDATA[52] !== 1'bz) && MAXIGP0RDATA_delay[52]; // rv 0 + assign MAXIGP0RDATA_in[53] = (MAXIGP0RDATA[53] !== 1'bz) && MAXIGP0RDATA_delay[53]; // rv 0 + assign MAXIGP0RDATA_in[54] = (MAXIGP0RDATA[54] !== 1'bz) && MAXIGP0RDATA_delay[54]; // rv 0 + assign MAXIGP0RDATA_in[55] = (MAXIGP0RDATA[55] !== 1'bz) && MAXIGP0RDATA_delay[55]; // rv 0 + assign MAXIGP0RDATA_in[56] = (MAXIGP0RDATA[56] !== 1'bz) && MAXIGP0RDATA_delay[56]; // rv 0 + assign MAXIGP0RDATA_in[57] = (MAXIGP0RDATA[57] !== 1'bz) && MAXIGP0RDATA_delay[57]; // rv 0 + assign MAXIGP0RDATA_in[58] = (MAXIGP0RDATA[58] !== 1'bz) && MAXIGP0RDATA_delay[58]; // rv 0 + assign MAXIGP0RDATA_in[59] = (MAXIGP0RDATA[59] !== 1'bz) && MAXIGP0RDATA_delay[59]; // rv 0 + assign MAXIGP0RDATA_in[5] = (MAXIGP0RDATA[5] !== 1'bz) && MAXIGP0RDATA_delay[5]; // rv 0 + assign MAXIGP0RDATA_in[60] = (MAXIGP0RDATA[60] !== 1'bz) && MAXIGP0RDATA_delay[60]; // rv 0 + assign MAXIGP0RDATA_in[61] = (MAXIGP0RDATA[61] !== 1'bz) && MAXIGP0RDATA_delay[61]; // rv 0 + assign MAXIGP0RDATA_in[62] = (MAXIGP0RDATA[62] !== 1'bz) && MAXIGP0RDATA_delay[62]; // rv 0 + assign MAXIGP0RDATA_in[63] = (MAXIGP0RDATA[63] !== 1'bz) && MAXIGP0RDATA_delay[63]; // rv 0 + assign MAXIGP0RDATA_in[64] = (MAXIGP0RDATA[64] !== 1'bz) && MAXIGP0RDATA_delay[64]; // rv 0 + assign MAXIGP0RDATA_in[65] = (MAXIGP0RDATA[65] !== 1'bz) && MAXIGP0RDATA_delay[65]; // rv 0 + assign MAXIGP0RDATA_in[66] = (MAXIGP0RDATA[66] !== 1'bz) && MAXIGP0RDATA_delay[66]; // rv 0 + assign MAXIGP0RDATA_in[67] = (MAXIGP0RDATA[67] !== 1'bz) && MAXIGP0RDATA_delay[67]; // rv 0 + assign MAXIGP0RDATA_in[68] = (MAXIGP0RDATA[68] !== 1'bz) && MAXIGP0RDATA_delay[68]; // rv 0 + assign MAXIGP0RDATA_in[69] = (MAXIGP0RDATA[69] !== 1'bz) && MAXIGP0RDATA_delay[69]; // rv 0 + assign MAXIGP0RDATA_in[6] = (MAXIGP0RDATA[6] !== 1'bz) && MAXIGP0RDATA_delay[6]; // rv 0 + assign MAXIGP0RDATA_in[70] = (MAXIGP0RDATA[70] !== 1'bz) && MAXIGP0RDATA_delay[70]; // rv 0 + assign MAXIGP0RDATA_in[71] = (MAXIGP0RDATA[71] !== 1'bz) && MAXIGP0RDATA_delay[71]; // rv 0 + assign MAXIGP0RDATA_in[72] = (MAXIGP0RDATA[72] !== 1'bz) && MAXIGP0RDATA_delay[72]; // rv 0 + assign MAXIGP0RDATA_in[73] = (MAXIGP0RDATA[73] !== 1'bz) && MAXIGP0RDATA_delay[73]; // rv 0 + assign MAXIGP0RDATA_in[74] = (MAXIGP0RDATA[74] !== 1'bz) && MAXIGP0RDATA_delay[74]; // rv 0 + assign MAXIGP0RDATA_in[75] = (MAXIGP0RDATA[75] !== 1'bz) && MAXIGP0RDATA_delay[75]; // rv 0 + assign MAXIGP0RDATA_in[76] = (MAXIGP0RDATA[76] !== 1'bz) && MAXIGP0RDATA_delay[76]; // rv 0 + assign MAXIGP0RDATA_in[77] = (MAXIGP0RDATA[77] !== 1'bz) && MAXIGP0RDATA_delay[77]; // rv 0 + assign MAXIGP0RDATA_in[78] = (MAXIGP0RDATA[78] !== 1'bz) && MAXIGP0RDATA_delay[78]; // rv 0 + assign MAXIGP0RDATA_in[79] = (MAXIGP0RDATA[79] !== 1'bz) && MAXIGP0RDATA_delay[79]; // rv 0 + assign MAXIGP0RDATA_in[7] = (MAXIGP0RDATA[7] !== 1'bz) && MAXIGP0RDATA_delay[7]; // rv 0 + assign MAXIGP0RDATA_in[80] = (MAXIGP0RDATA[80] !== 1'bz) && MAXIGP0RDATA_delay[80]; // rv 0 + assign MAXIGP0RDATA_in[81] = (MAXIGP0RDATA[81] !== 1'bz) && MAXIGP0RDATA_delay[81]; // rv 0 + assign MAXIGP0RDATA_in[82] = (MAXIGP0RDATA[82] !== 1'bz) && MAXIGP0RDATA_delay[82]; // rv 0 + assign MAXIGP0RDATA_in[83] = (MAXIGP0RDATA[83] !== 1'bz) && MAXIGP0RDATA_delay[83]; // rv 0 + assign MAXIGP0RDATA_in[84] = (MAXIGP0RDATA[84] !== 1'bz) && MAXIGP0RDATA_delay[84]; // rv 0 + assign MAXIGP0RDATA_in[85] = (MAXIGP0RDATA[85] !== 1'bz) && MAXIGP0RDATA_delay[85]; // rv 0 + assign MAXIGP0RDATA_in[86] = (MAXIGP0RDATA[86] !== 1'bz) && MAXIGP0RDATA_delay[86]; // rv 0 + assign MAXIGP0RDATA_in[87] = (MAXIGP0RDATA[87] !== 1'bz) && MAXIGP0RDATA_delay[87]; // rv 0 + assign MAXIGP0RDATA_in[88] = (MAXIGP0RDATA[88] !== 1'bz) && MAXIGP0RDATA_delay[88]; // rv 0 + assign MAXIGP0RDATA_in[89] = (MAXIGP0RDATA[89] !== 1'bz) && MAXIGP0RDATA_delay[89]; // rv 0 + assign MAXIGP0RDATA_in[8] = (MAXIGP0RDATA[8] !== 1'bz) && MAXIGP0RDATA_delay[8]; // rv 0 + assign MAXIGP0RDATA_in[90] = (MAXIGP0RDATA[90] !== 1'bz) && MAXIGP0RDATA_delay[90]; // rv 0 + assign MAXIGP0RDATA_in[91] = (MAXIGP0RDATA[91] !== 1'bz) && MAXIGP0RDATA_delay[91]; // rv 0 + assign MAXIGP0RDATA_in[92] = (MAXIGP0RDATA[92] !== 1'bz) && MAXIGP0RDATA_delay[92]; // rv 0 + assign MAXIGP0RDATA_in[93] = (MAXIGP0RDATA[93] !== 1'bz) && MAXIGP0RDATA_delay[93]; // rv 0 + assign MAXIGP0RDATA_in[94] = (MAXIGP0RDATA[94] !== 1'bz) && MAXIGP0RDATA_delay[94]; // rv 0 + assign MAXIGP0RDATA_in[95] = (MAXIGP0RDATA[95] !== 1'bz) && MAXIGP0RDATA_delay[95]; // rv 0 + assign MAXIGP0RDATA_in[96] = (MAXIGP0RDATA[96] !== 1'bz) && MAXIGP0RDATA_delay[96]; // rv 0 + assign MAXIGP0RDATA_in[97] = (MAXIGP0RDATA[97] !== 1'bz) && MAXIGP0RDATA_delay[97]; // rv 0 + assign MAXIGP0RDATA_in[98] = (MAXIGP0RDATA[98] !== 1'bz) && MAXIGP0RDATA_delay[98]; // rv 0 + assign MAXIGP0RDATA_in[99] = (MAXIGP0RDATA[99] !== 1'bz) && MAXIGP0RDATA_delay[99]; // rv 0 + assign MAXIGP0RDATA_in[9] = (MAXIGP0RDATA[9] !== 1'bz) && MAXIGP0RDATA_delay[9]; // rv 0 + assign MAXIGP0RID_in[0] = (MAXIGP0RID[0] !== 1'bz) && MAXIGP0RID_delay[0]; // rv 0 + assign MAXIGP0RID_in[10] = (MAXIGP0RID[10] !== 1'bz) && MAXIGP0RID_delay[10]; // rv 0 + assign MAXIGP0RID_in[11] = (MAXIGP0RID[11] !== 1'bz) && MAXIGP0RID_delay[11]; // rv 0 + assign MAXIGP0RID_in[12] = (MAXIGP0RID[12] !== 1'bz) && MAXIGP0RID_delay[12]; // rv 0 + assign MAXIGP0RID_in[13] = (MAXIGP0RID[13] !== 1'bz) && MAXIGP0RID_delay[13]; // rv 0 + assign MAXIGP0RID_in[14] = (MAXIGP0RID[14] !== 1'bz) && MAXIGP0RID_delay[14]; // rv 0 + assign MAXIGP0RID_in[15] = (MAXIGP0RID[15] !== 1'bz) && MAXIGP0RID_delay[15]; // rv 0 + assign MAXIGP0RID_in[1] = (MAXIGP0RID[1] !== 1'bz) && MAXIGP0RID_delay[1]; // rv 0 + assign MAXIGP0RID_in[2] = (MAXIGP0RID[2] !== 1'bz) && MAXIGP0RID_delay[2]; // rv 0 + assign MAXIGP0RID_in[3] = (MAXIGP0RID[3] !== 1'bz) && MAXIGP0RID_delay[3]; // rv 0 + assign MAXIGP0RID_in[4] = (MAXIGP0RID[4] !== 1'bz) && MAXIGP0RID_delay[4]; // rv 0 + assign MAXIGP0RID_in[5] = (MAXIGP0RID[5] !== 1'bz) && MAXIGP0RID_delay[5]; // rv 0 + assign MAXIGP0RID_in[6] = (MAXIGP0RID[6] !== 1'bz) && MAXIGP0RID_delay[6]; // rv 0 + assign MAXIGP0RID_in[7] = (MAXIGP0RID[7] !== 1'bz) && MAXIGP0RID_delay[7]; // rv 0 + assign MAXIGP0RID_in[8] = (MAXIGP0RID[8] !== 1'bz) && MAXIGP0RID_delay[8]; // rv 0 + assign MAXIGP0RID_in[9] = (MAXIGP0RID[9] !== 1'bz) && MAXIGP0RID_delay[9]; // rv 0 + assign MAXIGP0RLAST_in = (MAXIGP0RLAST !== 1'bz) && MAXIGP0RLAST_delay; // rv 0 + assign MAXIGP0RRESP_in[0] = (MAXIGP0RRESP[0] !== 1'bz) && MAXIGP0RRESP_delay[0]; // rv 0 + assign MAXIGP0RRESP_in[1] = (MAXIGP0RRESP[1] !== 1'bz) && MAXIGP0RRESP_delay[1]; // rv 0 + assign MAXIGP0RVALID_in = (MAXIGP0RVALID !== 1'bz) && MAXIGP0RVALID_delay; // rv 0 + assign MAXIGP0WREADY_in = (MAXIGP0WREADY !== 1'bz) && MAXIGP0WREADY_delay; // rv 0 + assign MAXIGP1ACLK_in = (MAXIGP1ACLK !== 1'bz) && MAXIGP1ACLK_delay; // rv 0 + assign MAXIGP1ARREADY_in = (MAXIGP1ARREADY !== 1'bz) && MAXIGP1ARREADY_delay; // rv 0 + assign MAXIGP1AWREADY_in = (MAXIGP1AWREADY !== 1'bz) && MAXIGP1AWREADY_delay; // rv 0 + assign MAXIGP1BID_in[0] = (MAXIGP1BID[0] !== 1'bz) && MAXIGP1BID_delay[0]; // rv 0 + assign MAXIGP1BID_in[10] = (MAXIGP1BID[10] !== 1'bz) && MAXIGP1BID_delay[10]; // rv 0 + assign MAXIGP1BID_in[11] = (MAXIGP1BID[11] !== 1'bz) && MAXIGP1BID_delay[11]; // rv 0 + assign MAXIGP1BID_in[12] = (MAXIGP1BID[12] !== 1'bz) && MAXIGP1BID_delay[12]; // rv 0 + assign MAXIGP1BID_in[13] = (MAXIGP1BID[13] !== 1'bz) && MAXIGP1BID_delay[13]; // rv 0 + assign MAXIGP1BID_in[14] = (MAXIGP1BID[14] !== 1'bz) && MAXIGP1BID_delay[14]; // rv 0 + assign MAXIGP1BID_in[15] = (MAXIGP1BID[15] !== 1'bz) && MAXIGP1BID_delay[15]; // rv 0 + assign MAXIGP1BID_in[1] = (MAXIGP1BID[1] !== 1'bz) && MAXIGP1BID_delay[1]; // rv 0 + assign MAXIGP1BID_in[2] = (MAXIGP1BID[2] !== 1'bz) && MAXIGP1BID_delay[2]; // rv 0 + assign MAXIGP1BID_in[3] = (MAXIGP1BID[3] !== 1'bz) && MAXIGP1BID_delay[3]; // rv 0 + assign MAXIGP1BID_in[4] = (MAXIGP1BID[4] !== 1'bz) && MAXIGP1BID_delay[4]; // rv 0 + assign MAXIGP1BID_in[5] = (MAXIGP1BID[5] !== 1'bz) && MAXIGP1BID_delay[5]; // rv 0 + assign MAXIGP1BID_in[6] = (MAXIGP1BID[6] !== 1'bz) && MAXIGP1BID_delay[6]; // rv 0 + assign MAXIGP1BID_in[7] = (MAXIGP1BID[7] !== 1'bz) && MAXIGP1BID_delay[7]; // rv 0 + assign MAXIGP1BID_in[8] = (MAXIGP1BID[8] !== 1'bz) && MAXIGP1BID_delay[8]; // rv 0 + assign MAXIGP1BID_in[9] = (MAXIGP1BID[9] !== 1'bz) && MAXIGP1BID_delay[9]; // rv 0 + assign MAXIGP1BRESP_in[0] = (MAXIGP1BRESP[0] !== 1'bz) && MAXIGP1BRESP_delay[0]; // rv 0 + assign MAXIGP1BRESP_in[1] = (MAXIGP1BRESP[1] !== 1'bz) && MAXIGP1BRESP_delay[1]; // rv 0 + assign MAXIGP1BVALID_in = (MAXIGP1BVALID !== 1'bz) && MAXIGP1BVALID_delay; // rv 0 + assign MAXIGP1RDATA_in[0] = (MAXIGP1RDATA[0] !== 1'bz) && MAXIGP1RDATA_delay[0]; // rv 0 + assign MAXIGP1RDATA_in[100] = (MAXIGP1RDATA[100] !== 1'bz) && MAXIGP1RDATA_delay[100]; // rv 0 + assign MAXIGP1RDATA_in[101] = (MAXIGP1RDATA[101] !== 1'bz) && MAXIGP1RDATA_delay[101]; // rv 0 + assign MAXIGP1RDATA_in[102] = (MAXIGP1RDATA[102] !== 1'bz) && MAXIGP1RDATA_delay[102]; // rv 0 + assign MAXIGP1RDATA_in[103] = (MAXIGP1RDATA[103] !== 1'bz) && MAXIGP1RDATA_delay[103]; // rv 0 + assign MAXIGP1RDATA_in[104] = (MAXIGP1RDATA[104] !== 1'bz) && MAXIGP1RDATA_delay[104]; // rv 0 + assign MAXIGP1RDATA_in[105] = (MAXIGP1RDATA[105] !== 1'bz) && MAXIGP1RDATA_delay[105]; // rv 0 + assign MAXIGP1RDATA_in[106] = (MAXIGP1RDATA[106] !== 1'bz) && MAXIGP1RDATA_delay[106]; // rv 0 + assign MAXIGP1RDATA_in[107] = (MAXIGP1RDATA[107] !== 1'bz) && MAXIGP1RDATA_delay[107]; // rv 0 + assign MAXIGP1RDATA_in[108] = (MAXIGP1RDATA[108] !== 1'bz) && MAXIGP1RDATA_delay[108]; // rv 0 + assign MAXIGP1RDATA_in[109] = (MAXIGP1RDATA[109] !== 1'bz) && MAXIGP1RDATA_delay[109]; // rv 0 + assign MAXIGP1RDATA_in[10] = (MAXIGP1RDATA[10] !== 1'bz) && MAXIGP1RDATA_delay[10]; // rv 0 + assign MAXIGP1RDATA_in[110] = (MAXIGP1RDATA[110] !== 1'bz) && MAXIGP1RDATA_delay[110]; // rv 0 + assign MAXIGP1RDATA_in[111] = (MAXIGP1RDATA[111] !== 1'bz) && MAXIGP1RDATA_delay[111]; // rv 0 + assign MAXIGP1RDATA_in[112] = (MAXIGP1RDATA[112] !== 1'bz) && MAXIGP1RDATA_delay[112]; // rv 0 + assign MAXIGP1RDATA_in[113] = (MAXIGP1RDATA[113] !== 1'bz) && MAXIGP1RDATA_delay[113]; // rv 0 + assign MAXIGP1RDATA_in[114] = (MAXIGP1RDATA[114] !== 1'bz) && MAXIGP1RDATA_delay[114]; // rv 0 + assign MAXIGP1RDATA_in[115] = (MAXIGP1RDATA[115] !== 1'bz) && MAXIGP1RDATA_delay[115]; // rv 0 + assign MAXIGP1RDATA_in[116] = (MAXIGP1RDATA[116] !== 1'bz) && MAXIGP1RDATA_delay[116]; // rv 0 + assign MAXIGP1RDATA_in[117] = (MAXIGP1RDATA[117] !== 1'bz) && MAXIGP1RDATA_delay[117]; // rv 0 + assign MAXIGP1RDATA_in[118] = (MAXIGP1RDATA[118] !== 1'bz) && MAXIGP1RDATA_delay[118]; // rv 0 + assign MAXIGP1RDATA_in[119] = (MAXIGP1RDATA[119] !== 1'bz) && MAXIGP1RDATA_delay[119]; // rv 0 + assign MAXIGP1RDATA_in[11] = (MAXIGP1RDATA[11] !== 1'bz) && MAXIGP1RDATA_delay[11]; // rv 0 + assign MAXIGP1RDATA_in[120] = (MAXIGP1RDATA[120] !== 1'bz) && MAXIGP1RDATA_delay[120]; // rv 0 + assign MAXIGP1RDATA_in[121] = (MAXIGP1RDATA[121] !== 1'bz) && MAXIGP1RDATA_delay[121]; // rv 0 + assign MAXIGP1RDATA_in[122] = (MAXIGP1RDATA[122] !== 1'bz) && MAXIGP1RDATA_delay[122]; // rv 0 + assign MAXIGP1RDATA_in[123] = (MAXIGP1RDATA[123] !== 1'bz) && MAXIGP1RDATA_delay[123]; // rv 0 + assign MAXIGP1RDATA_in[124] = (MAXIGP1RDATA[124] !== 1'bz) && MAXIGP1RDATA_delay[124]; // rv 0 + assign MAXIGP1RDATA_in[125] = (MAXIGP1RDATA[125] !== 1'bz) && MAXIGP1RDATA_delay[125]; // rv 0 + assign MAXIGP1RDATA_in[126] = (MAXIGP1RDATA[126] !== 1'bz) && MAXIGP1RDATA_delay[126]; // rv 0 + assign MAXIGP1RDATA_in[127] = (MAXIGP1RDATA[127] !== 1'bz) && MAXIGP1RDATA_delay[127]; // rv 0 + assign MAXIGP1RDATA_in[12] = (MAXIGP1RDATA[12] !== 1'bz) && MAXIGP1RDATA_delay[12]; // rv 0 + assign MAXIGP1RDATA_in[13] = (MAXIGP1RDATA[13] !== 1'bz) && MAXIGP1RDATA_delay[13]; // rv 0 + assign MAXIGP1RDATA_in[14] = (MAXIGP1RDATA[14] !== 1'bz) && MAXIGP1RDATA_delay[14]; // rv 0 + assign MAXIGP1RDATA_in[15] = (MAXIGP1RDATA[15] !== 1'bz) && MAXIGP1RDATA_delay[15]; // rv 0 + assign MAXIGP1RDATA_in[16] = (MAXIGP1RDATA[16] !== 1'bz) && MAXIGP1RDATA_delay[16]; // rv 0 + assign MAXIGP1RDATA_in[17] = (MAXIGP1RDATA[17] !== 1'bz) && MAXIGP1RDATA_delay[17]; // rv 0 + assign MAXIGP1RDATA_in[18] = (MAXIGP1RDATA[18] !== 1'bz) && MAXIGP1RDATA_delay[18]; // rv 0 + assign MAXIGP1RDATA_in[19] = (MAXIGP1RDATA[19] !== 1'bz) && MAXIGP1RDATA_delay[19]; // rv 0 + assign MAXIGP1RDATA_in[1] = (MAXIGP1RDATA[1] !== 1'bz) && MAXIGP1RDATA_delay[1]; // rv 0 + assign MAXIGP1RDATA_in[20] = (MAXIGP1RDATA[20] !== 1'bz) && MAXIGP1RDATA_delay[20]; // rv 0 + assign MAXIGP1RDATA_in[21] = (MAXIGP1RDATA[21] !== 1'bz) && MAXIGP1RDATA_delay[21]; // rv 0 + assign MAXIGP1RDATA_in[22] = (MAXIGP1RDATA[22] !== 1'bz) && MAXIGP1RDATA_delay[22]; // rv 0 + assign MAXIGP1RDATA_in[23] = (MAXIGP1RDATA[23] !== 1'bz) && MAXIGP1RDATA_delay[23]; // rv 0 + assign MAXIGP1RDATA_in[24] = (MAXIGP1RDATA[24] !== 1'bz) && MAXIGP1RDATA_delay[24]; // rv 0 + assign MAXIGP1RDATA_in[25] = (MAXIGP1RDATA[25] !== 1'bz) && MAXIGP1RDATA_delay[25]; // rv 0 + assign MAXIGP1RDATA_in[26] = (MAXIGP1RDATA[26] !== 1'bz) && MAXIGP1RDATA_delay[26]; // rv 0 + assign MAXIGP1RDATA_in[27] = (MAXIGP1RDATA[27] !== 1'bz) && MAXIGP1RDATA_delay[27]; // rv 0 + assign MAXIGP1RDATA_in[28] = (MAXIGP1RDATA[28] !== 1'bz) && MAXIGP1RDATA_delay[28]; // rv 0 + assign MAXIGP1RDATA_in[29] = (MAXIGP1RDATA[29] !== 1'bz) && MAXIGP1RDATA_delay[29]; // rv 0 + assign MAXIGP1RDATA_in[2] = (MAXIGP1RDATA[2] !== 1'bz) && MAXIGP1RDATA_delay[2]; // rv 0 + assign MAXIGP1RDATA_in[30] = (MAXIGP1RDATA[30] !== 1'bz) && MAXIGP1RDATA_delay[30]; // rv 0 + assign MAXIGP1RDATA_in[31] = (MAXIGP1RDATA[31] !== 1'bz) && MAXIGP1RDATA_delay[31]; // rv 0 + assign MAXIGP1RDATA_in[32] = (MAXIGP1RDATA[32] !== 1'bz) && MAXIGP1RDATA_delay[32]; // rv 0 + assign MAXIGP1RDATA_in[33] = (MAXIGP1RDATA[33] !== 1'bz) && MAXIGP1RDATA_delay[33]; // rv 0 + assign MAXIGP1RDATA_in[34] = (MAXIGP1RDATA[34] !== 1'bz) && MAXIGP1RDATA_delay[34]; // rv 0 + assign MAXIGP1RDATA_in[35] = (MAXIGP1RDATA[35] !== 1'bz) && MAXIGP1RDATA_delay[35]; // rv 0 + assign MAXIGP1RDATA_in[36] = (MAXIGP1RDATA[36] !== 1'bz) && MAXIGP1RDATA_delay[36]; // rv 0 + assign MAXIGP1RDATA_in[37] = (MAXIGP1RDATA[37] !== 1'bz) && MAXIGP1RDATA_delay[37]; // rv 0 + assign MAXIGP1RDATA_in[38] = (MAXIGP1RDATA[38] !== 1'bz) && MAXIGP1RDATA_delay[38]; // rv 0 + assign MAXIGP1RDATA_in[39] = (MAXIGP1RDATA[39] !== 1'bz) && MAXIGP1RDATA_delay[39]; // rv 0 + assign MAXIGP1RDATA_in[3] = (MAXIGP1RDATA[3] !== 1'bz) && MAXIGP1RDATA_delay[3]; // rv 0 + assign MAXIGP1RDATA_in[40] = (MAXIGP1RDATA[40] !== 1'bz) && MAXIGP1RDATA_delay[40]; // rv 0 + assign MAXIGP1RDATA_in[41] = (MAXIGP1RDATA[41] !== 1'bz) && MAXIGP1RDATA_delay[41]; // rv 0 + assign MAXIGP1RDATA_in[42] = (MAXIGP1RDATA[42] !== 1'bz) && MAXIGP1RDATA_delay[42]; // rv 0 + assign MAXIGP1RDATA_in[43] = (MAXIGP1RDATA[43] !== 1'bz) && MAXIGP1RDATA_delay[43]; // rv 0 + assign MAXIGP1RDATA_in[44] = (MAXIGP1RDATA[44] !== 1'bz) && MAXIGP1RDATA_delay[44]; // rv 0 + assign MAXIGP1RDATA_in[45] = (MAXIGP1RDATA[45] !== 1'bz) && MAXIGP1RDATA_delay[45]; // rv 0 + assign MAXIGP1RDATA_in[46] = (MAXIGP1RDATA[46] !== 1'bz) && MAXIGP1RDATA_delay[46]; // rv 0 + assign MAXIGP1RDATA_in[47] = (MAXIGP1RDATA[47] !== 1'bz) && MAXIGP1RDATA_delay[47]; // rv 0 + assign MAXIGP1RDATA_in[48] = (MAXIGP1RDATA[48] !== 1'bz) && MAXIGP1RDATA_delay[48]; // rv 0 + assign MAXIGP1RDATA_in[49] = (MAXIGP1RDATA[49] !== 1'bz) && MAXIGP1RDATA_delay[49]; // rv 0 + assign MAXIGP1RDATA_in[4] = (MAXIGP1RDATA[4] !== 1'bz) && MAXIGP1RDATA_delay[4]; // rv 0 + assign MAXIGP1RDATA_in[50] = (MAXIGP1RDATA[50] !== 1'bz) && MAXIGP1RDATA_delay[50]; // rv 0 + assign MAXIGP1RDATA_in[51] = (MAXIGP1RDATA[51] !== 1'bz) && MAXIGP1RDATA_delay[51]; // rv 0 + assign MAXIGP1RDATA_in[52] = (MAXIGP1RDATA[52] !== 1'bz) && MAXIGP1RDATA_delay[52]; // rv 0 + assign MAXIGP1RDATA_in[53] = (MAXIGP1RDATA[53] !== 1'bz) && MAXIGP1RDATA_delay[53]; // rv 0 + assign MAXIGP1RDATA_in[54] = (MAXIGP1RDATA[54] !== 1'bz) && MAXIGP1RDATA_delay[54]; // rv 0 + assign MAXIGP1RDATA_in[55] = (MAXIGP1RDATA[55] !== 1'bz) && MAXIGP1RDATA_delay[55]; // rv 0 + assign MAXIGP1RDATA_in[56] = (MAXIGP1RDATA[56] !== 1'bz) && MAXIGP1RDATA_delay[56]; // rv 0 + assign MAXIGP1RDATA_in[57] = (MAXIGP1RDATA[57] !== 1'bz) && MAXIGP1RDATA_delay[57]; // rv 0 + assign MAXIGP1RDATA_in[58] = (MAXIGP1RDATA[58] !== 1'bz) && MAXIGP1RDATA_delay[58]; // rv 0 + assign MAXIGP1RDATA_in[59] = (MAXIGP1RDATA[59] !== 1'bz) && MAXIGP1RDATA_delay[59]; // rv 0 + assign MAXIGP1RDATA_in[5] = (MAXIGP1RDATA[5] !== 1'bz) && MAXIGP1RDATA_delay[5]; // rv 0 + assign MAXIGP1RDATA_in[60] = (MAXIGP1RDATA[60] !== 1'bz) && MAXIGP1RDATA_delay[60]; // rv 0 + assign MAXIGP1RDATA_in[61] = (MAXIGP1RDATA[61] !== 1'bz) && MAXIGP1RDATA_delay[61]; // rv 0 + assign MAXIGP1RDATA_in[62] = (MAXIGP1RDATA[62] !== 1'bz) && MAXIGP1RDATA_delay[62]; // rv 0 + assign MAXIGP1RDATA_in[63] = (MAXIGP1RDATA[63] !== 1'bz) && MAXIGP1RDATA_delay[63]; // rv 0 + assign MAXIGP1RDATA_in[64] = (MAXIGP1RDATA[64] !== 1'bz) && MAXIGP1RDATA_delay[64]; // rv 0 + assign MAXIGP1RDATA_in[65] = (MAXIGP1RDATA[65] !== 1'bz) && MAXIGP1RDATA_delay[65]; // rv 0 + assign MAXIGP1RDATA_in[66] = (MAXIGP1RDATA[66] !== 1'bz) && MAXIGP1RDATA_delay[66]; // rv 0 + assign MAXIGP1RDATA_in[67] = (MAXIGP1RDATA[67] !== 1'bz) && MAXIGP1RDATA_delay[67]; // rv 0 + assign MAXIGP1RDATA_in[68] = (MAXIGP1RDATA[68] !== 1'bz) && MAXIGP1RDATA_delay[68]; // rv 0 + assign MAXIGP1RDATA_in[69] = (MAXIGP1RDATA[69] !== 1'bz) && MAXIGP1RDATA_delay[69]; // rv 0 + assign MAXIGP1RDATA_in[6] = (MAXIGP1RDATA[6] !== 1'bz) && MAXIGP1RDATA_delay[6]; // rv 0 + assign MAXIGP1RDATA_in[70] = (MAXIGP1RDATA[70] !== 1'bz) && MAXIGP1RDATA_delay[70]; // rv 0 + assign MAXIGP1RDATA_in[71] = (MAXIGP1RDATA[71] !== 1'bz) && MAXIGP1RDATA_delay[71]; // rv 0 + assign MAXIGP1RDATA_in[72] = (MAXIGP1RDATA[72] !== 1'bz) && MAXIGP1RDATA_delay[72]; // rv 0 + assign MAXIGP1RDATA_in[73] = (MAXIGP1RDATA[73] !== 1'bz) && MAXIGP1RDATA_delay[73]; // rv 0 + assign MAXIGP1RDATA_in[74] = (MAXIGP1RDATA[74] !== 1'bz) && MAXIGP1RDATA_delay[74]; // rv 0 + assign MAXIGP1RDATA_in[75] = (MAXIGP1RDATA[75] !== 1'bz) && MAXIGP1RDATA_delay[75]; // rv 0 + assign MAXIGP1RDATA_in[76] = (MAXIGP1RDATA[76] !== 1'bz) && MAXIGP1RDATA_delay[76]; // rv 0 + assign MAXIGP1RDATA_in[77] = (MAXIGP1RDATA[77] !== 1'bz) && MAXIGP1RDATA_delay[77]; // rv 0 + assign MAXIGP1RDATA_in[78] = (MAXIGP1RDATA[78] !== 1'bz) && MAXIGP1RDATA_delay[78]; // rv 0 + assign MAXIGP1RDATA_in[79] = (MAXIGP1RDATA[79] !== 1'bz) && MAXIGP1RDATA_delay[79]; // rv 0 + assign MAXIGP1RDATA_in[7] = (MAXIGP1RDATA[7] !== 1'bz) && MAXIGP1RDATA_delay[7]; // rv 0 + assign MAXIGP1RDATA_in[80] = (MAXIGP1RDATA[80] !== 1'bz) && MAXIGP1RDATA_delay[80]; // rv 0 + assign MAXIGP1RDATA_in[81] = (MAXIGP1RDATA[81] !== 1'bz) && MAXIGP1RDATA_delay[81]; // rv 0 + assign MAXIGP1RDATA_in[82] = (MAXIGP1RDATA[82] !== 1'bz) && MAXIGP1RDATA_delay[82]; // rv 0 + assign MAXIGP1RDATA_in[83] = (MAXIGP1RDATA[83] !== 1'bz) && MAXIGP1RDATA_delay[83]; // rv 0 + assign MAXIGP1RDATA_in[84] = (MAXIGP1RDATA[84] !== 1'bz) && MAXIGP1RDATA_delay[84]; // rv 0 + assign MAXIGP1RDATA_in[85] = (MAXIGP1RDATA[85] !== 1'bz) && MAXIGP1RDATA_delay[85]; // rv 0 + assign MAXIGP1RDATA_in[86] = (MAXIGP1RDATA[86] !== 1'bz) && MAXIGP1RDATA_delay[86]; // rv 0 + assign MAXIGP1RDATA_in[87] = (MAXIGP1RDATA[87] !== 1'bz) && MAXIGP1RDATA_delay[87]; // rv 0 + assign MAXIGP1RDATA_in[88] = (MAXIGP1RDATA[88] !== 1'bz) && MAXIGP1RDATA_delay[88]; // rv 0 + assign MAXIGP1RDATA_in[89] = (MAXIGP1RDATA[89] !== 1'bz) && MAXIGP1RDATA_delay[89]; // rv 0 + assign MAXIGP1RDATA_in[8] = (MAXIGP1RDATA[8] !== 1'bz) && MAXIGP1RDATA_delay[8]; // rv 0 + assign MAXIGP1RDATA_in[90] = (MAXIGP1RDATA[90] !== 1'bz) && MAXIGP1RDATA_delay[90]; // rv 0 + assign MAXIGP1RDATA_in[91] = (MAXIGP1RDATA[91] !== 1'bz) && MAXIGP1RDATA_delay[91]; // rv 0 + assign MAXIGP1RDATA_in[92] = (MAXIGP1RDATA[92] !== 1'bz) && MAXIGP1RDATA_delay[92]; // rv 0 + assign MAXIGP1RDATA_in[93] = (MAXIGP1RDATA[93] !== 1'bz) && MAXIGP1RDATA_delay[93]; // rv 0 + assign MAXIGP1RDATA_in[94] = (MAXIGP1RDATA[94] !== 1'bz) && MAXIGP1RDATA_delay[94]; // rv 0 + assign MAXIGP1RDATA_in[95] = (MAXIGP1RDATA[95] !== 1'bz) && MAXIGP1RDATA_delay[95]; // rv 0 + assign MAXIGP1RDATA_in[96] = (MAXIGP1RDATA[96] !== 1'bz) && MAXIGP1RDATA_delay[96]; // rv 0 + assign MAXIGP1RDATA_in[97] = (MAXIGP1RDATA[97] !== 1'bz) && MAXIGP1RDATA_delay[97]; // rv 0 + assign MAXIGP1RDATA_in[98] = (MAXIGP1RDATA[98] !== 1'bz) && MAXIGP1RDATA_delay[98]; // rv 0 + assign MAXIGP1RDATA_in[99] = (MAXIGP1RDATA[99] !== 1'bz) && MAXIGP1RDATA_delay[99]; // rv 0 + assign MAXIGP1RDATA_in[9] = (MAXIGP1RDATA[9] !== 1'bz) && MAXIGP1RDATA_delay[9]; // rv 0 + assign MAXIGP1RID_in[0] = (MAXIGP1RID[0] !== 1'bz) && MAXIGP1RID_delay[0]; // rv 0 + assign MAXIGP1RID_in[10] = (MAXIGP1RID[10] !== 1'bz) && MAXIGP1RID_delay[10]; // rv 0 + assign MAXIGP1RID_in[11] = (MAXIGP1RID[11] !== 1'bz) && MAXIGP1RID_delay[11]; // rv 0 + assign MAXIGP1RID_in[12] = (MAXIGP1RID[12] !== 1'bz) && MAXIGP1RID_delay[12]; // rv 0 + assign MAXIGP1RID_in[13] = (MAXIGP1RID[13] !== 1'bz) && MAXIGP1RID_delay[13]; // rv 0 + assign MAXIGP1RID_in[14] = (MAXIGP1RID[14] !== 1'bz) && MAXIGP1RID_delay[14]; // rv 0 + assign MAXIGP1RID_in[15] = (MAXIGP1RID[15] !== 1'bz) && MAXIGP1RID_delay[15]; // rv 0 + assign MAXIGP1RID_in[1] = (MAXIGP1RID[1] !== 1'bz) && MAXIGP1RID_delay[1]; // rv 0 + assign MAXIGP1RID_in[2] = (MAXIGP1RID[2] !== 1'bz) && MAXIGP1RID_delay[2]; // rv 0 + assign MAXIGP1RID_in[3] = (MAXIGP1RID[3] !== 1'bz) && MAXIGP1RID_delay[3]; // rv 0 + assign MAXIGP1RID_in[4] = (MAXIGP1RID[4] !== 1'bz) && MAXIGP1RID_delay[4]; // rv 0 + assign MAXIGP1RID_in[5] = (MAXIGP1RID[5] !== 1'bz) && MAXIGP1RID_delay[5]; // rv 0 + assign MAXIGP1RID_in[6] = (MAXIGP1RID[6] !== 1'bz) && MAXIGP1RID_delay[6]; // rv 0 + assign MAXIGP1RID_in[7] = (MAXIGP1RID[7] !== 1'bz) && MAXIGP1RID_delay[7]; // rv 0 + assign MAXIGP1RID_in[8] = (MAXIGP1RID[8] !== 1'bz) && MAXIGP1RID_delay[8]; // rv 0 + assign MAXIGP1RID_in[9] = (MAXIGP1RID[9] !== 1'bz) && MAXIGP1RID_delay[9]; // rv 0 + assign MAXIGP1RLAST_in = (MAXIGP1RLAST !== 1'bz) && MAXIGP1RLAST_delay; // rv 0 + assign MAXIGP1RRESP_in[0] = (MAXIGP1RRESP[0] !== 1'bz) && MAXIGP1RRESP_delay[0]; // rv 0 + assign MAXIGP1RRESP_in[1] = (MAXIGP1RRESP[1] !== 1'bz) && MAXIGP1RRESP_delay[1]; // rv 0 + assign MAXIGP1RVALID_in = (MAXIGP1RVALID !== 1'bz) && MAXIGP1RVALID_delay; // rv 0 + assign MAXIGP1WREADY_in = (MAXIGP1WREADY !== 1'bz) && MAXIGP1WREADY_delay; // rv 0 + assign MAXIGP2ACLK_in = (MAXIGP2ACLK !== 1'bz) && MAXIGP2ACLK_delay; // rv 0 + assign MAXIGP2ARREADY_in = (MAXIGP2ARREADY !== 1'bz) && MAXIGP2ARREADY_delay; // rv 0 + assign MAXIGP2AWREADY_in = (MAXIGP2AWREADY !== 1'bz) && MAXIGP2AWREADY_delay; // rv 0 + assign MAXIGP2BID_in[0] = (MAXIGP2BID[0] !== 1'bz) && MAXIGP2BID_delay[0]; // rv 0 + assign MAXIGP2BID_in[10] = (MAXIGP2BID[10] !== 1'bz) && MAXIGP2BID_delay[10]; // rv 0 + assign MAXIGP2BID_in[11] = (MAXIGP2BID[11] !== 1'bz) && MAXIGP2BID_delay[11]; // rv 0 + assign MAXIGP2BID_in[12] = (MAXIGP2BID[12] !== 1'bz) && MAXIGP2BID_delay[12]; // rv 0 + assign MAXIGP2BID_in[13] = (MAXIGP2BID[13] !== 1'bz) && MAXIGP2BID_delay[13]; // rv 0 + assign MAXIGP2BID_in[14] = (MAXIGP2BID[14] !== 1'bz) && MAXIGP2BID_delay[14]; // rv 0 + assign MAXIGP2BID_in[15] = (MAXIGP2BID[15] !== 1'bz) && MAXIGP2BID_delay[15]; // rv 0 + assign MAXIGP2BID_in[1] = (MAXIGP2BID[1] !== 1'bz) && MAXIGP2BID_delay[1]; // rv 0 + assign MAXIGP2BID_in[2] = (MAXIGP2BID[2] !== 1'bz) && MAXIGP2BID_delay[2]; // rv 0 + assign MAXIGP2BID_in[3] = (MAXIGP2BID[3] !== 1'bz) && MAXIGP2BID_delay[3]; // rv 0 + assign MAXIGP2BID_in[4] = (MAXIGP2BID[4] !== 1'bz) && MAXIGP2BID_delay[4]; // rv 0 + assign MAXIGP2BID_in[5] = (MAXIGP2BID[5] !== 1'bz) && MAXIGP2BID_delay[5]; // rv 0 + assign MAXIGP2BID_in[6] = (MAXIGP2BID[6] !== 1'bz) && MAXIGP2BID_delay[6]; // rv 0 + assign MAXIGP2BID_in[7] = (MAXIGP2BID[7] !== 1'bz) && MAXIGP2BID_delay[7]; // rv 0 + assign MAXIGP2BID_in[8] = (MAXIGP2BID[8] !== 1'bz) && MAXIGP2BID_delay[8]; // rv 0 + assign MAXIGP2BID_in[9] = (MAXIGP2BID[9] !== 1'bz) && MAXIGP2BID_delay[9]; // rv 0 + assign MAXIGP2BRESP_in[0] = (MAXIGP2BRESP[0] !== 1'bz) && MAXIGP2BRESP_delay[0]; // rv 0 + assign MAXIGP2BRESP_in[1] = (MAXIGP2BRESP[1] !== 1'bz) && MAXIGP2BRESP_delay[1]; // rv 0 + assign MAXIGP2BVALID_in = (MAXIGP2BVALID !== 1'bz) && MAXIGP2BVALID_delay; // rv 0 + assign MAXIGP2RDATA_in[0] = (MAXIGP2RDATA[0] !== 1'bz) && MAXIGP2RDATA_delay[0]; // rv 0 + assign MAXIGP2RDATA_in[100] = (MAXIGP2RDATA[100] !== 1'bz) && MAXIGP2RDATA_delay[100]; // rv 0 + assign MAXIGP2RDATA_in[101] = (MAXIGP2RDATA[101] !== 1'bz) && MAXIGP2RDATA_delay[101]; // rv 0 + assign MAXIGP2RDATA_in[102] = (MAXIGP2RDATA[102] !== 1'bz) && MAXIGP2RDATA_delay[102]; // rv 0 + assign MAXIGP2RDATA_in[103] = (MAXIGP2RDATA[103] !== 1'bz) && MAXIGP2RDATA_delay[103]; // rv 0 + assign MAXIGP2RDATA_in[104] = (MAXIGP2RDATA[104] !== 1'bz) && MAXIGP2RDATA_delay[104]; // rv 0 + assign MAXIGP2RDATA_in[105] = (MAXIGP2RDATA[105] !== 1'bz) && MAXIGP2RDATA_delay[105]; // rv 0 + assign MAXIGP2RDATA_in[106] = (MAXIGP2RDATA[106] !== 1'bz) && MAXIGP2RDATA_delay[106]; // rv 0 + assign MAXIGP2RDATA_in[107] = (MAXIGP2RDATA[107] !== 1'bz) && MAXIGP2RDATA_delay[107]; // rv 0 + assign MAXIGP2RDATA_in[108] = (MAXIGP2RDATA[108] !== 1'bz) && MAXIGP2RDATA_delay[108]; // rv 0 + assign MAXIGP2RDATA_in[109] = (MAXIGP2RDATA[109] !== 1'bz) && MAXIGP2RDATA_delay[109]; // rv 0 + assign MAXIGP2RDATA_in[10] = (MAXIGP2RDATA[10] !== 1'bz) && MAXIGP2RDATA_delay[10]; // rv 0 + assign MAXIGP2RDATA_in[110] = (MAXIGP2RDATA[110] !== 1'bz) && MAXIGP2RDATA_delay[110]; // rv 0 + assign MAXIGP2RDATA_in[111] = (MAXIGP2RDATA[111] !== 1'bz) && MAXIGP2RDATA_delay[111]; // rv 0 + assign MAXIGP2RDATA_in[112] = (MAXIGP2RDATA[112] !== 1'bz) && MAXIGP2RDATA_delay[112]; // rv 0 + assign MAXIGP2RDATA_in[113] = (MAXIGP2RDATA[113] !== 1'bz) && MAXIGP2RDATA_delay[113]; // rv 0 + assign MAXIGP2RDATA_in[114] = (MAXIGP2RDATA[114] !== 1'bz) && MAXIGP2RDATA_delay[114]; // rv 0 + assign MAXIGP2RDATA_in[115] = (MAXIGP2RDATA[115] !== 1'bz) && MAXIGP2RDATA_delay[115]; // rv 0 + assign MAXIGP2RDATA_in[116] = (MAXIGP2RDATA[116] !== 1'bz) && MAXIGP2RDATA_delay[116]; // rv 0 + assign MAXIGP2RDATA_in[117] = (MAXIGP2RDATA[117] !== 1'bz) && MAXIGP2RDATA_delay[117]; // rv 0 + assign MAXIGP2RDATA_in[118] = (MAXIGP2RDATA[118] !== 1'bz) && MAXIGP2RDATA_delay[118]; // rv 0 + assign MAXIGP2RDATA_in[119] = (MAXIGP2RDATA[119] !== 1'bz) && MAXIGP2RDATA_delay[119]; // rv 0 + assign MAXIGP2RDATA_in[11] = (MAXIGP2RDATA[11] !== 1'bz) && MAXIGP2RDATA_delay[11]; // rv 0 + assign MAXIGP2RDATA_in[120] = (MAXIGP2RDATA[120] !== 1'bz) && MAXIGP2RDATA_delay[120]; // rv 0 + assign MAXIGP2RDATA_in[121] = (MAXIGP2RDATA[121] !== 1'bz) && MAXIGP2RDATA_delay[121]; // rv 0 + assign MAXIGP2RDATA_in[122] = (MAXIGP2RDATA[122] !== 1'bz) && MAXIGP2RDATA_delay[122]; // rv 0 + assign MAXIGP2RDATA_in[123] = (MAXIGP2RDATA[123] !== 1'bz) && MAXIGP2RDATA_delay[123]; // rv 0 + assign MAXIGP2RDATA_in[124] = (MAXIGP2RDATA[124] !== 1'bz) && MAXIGP2RDATA_delay[124]; // rv 0 + assign MAXIGP2RDATA_in[125] = (MAXIGP2RDATA[125] !== 1'bz) && MAXIGP2RDATA_delay[125]; // rv 0 + assign MAXIGP2RDATA_in[126] = (MAXIGP2RDATA[126] !== 1'bz) && MAXIGP2RDATA_delay[126]; // rv 0 + assign MAXIGP2RDATA_in[127] = (MAXIGP2RDATA[127] !== 1'bz) && MAXIGP2RDATA_delay[127]; // rv 0 + assign MAXIGP2RDATA_in[12] = (MAXIGP2RDATA[12] !== 1'bz) && MAXIGP2RDATA_delay[12]; // rv 0 + assign MAXIGP2RDATA_in[13] = (MAXIGP2RDATA[13] !== 1'bz) && MAXIGP2RDATA_delay[13]; // rv 0 + assign MAXIGP2RDATA_in[14] = (MAXIGP2RDATA[14] !== 1'bz) && MAXIGP2RDATA_delay[14]; // rv 0 + assign MAXIGP2RDATA_in[15] = (MAXIGP2RDATA[15] !== 1'bz) && MAXIGP2RDATA_delay[15]; // rv 0 + assign MAXIGP2RDATA_in[16] = (MAXIGP2RDATA[16] !== 1'bz) && MAXIGP2RDATA_delay[16]; // rv 0 + assign MAXIGP2RDATA_in[17] = (MAXIGP2RDATA[17] !== 1'bz) && MAXIGP2RDATA_delay[17]; // rv 0 + assign MAXIGP2RDATA_in[18] = (MAXIGP2RDATA[18] !== 1'bz) && MAXIGP2RDATA_delay[18]; // rv 0 + assign MAXIGP2RDATA_in[19] = (MAXIGP2RDATA[19] !== 1'bz) && MAXIGP2RDATA_delay[19]; // rv 0 + assign MAXIGP2RDATA_in[1] = (MAXIGP2RDATA[1] !== 1'bz) && MAXIGP2RDATA_delay[1]; // rv 0 + assign MAXIGP2RDATA_in[20] = (MAXIGP2RDATA[20] !== 1'bz) && MAXIGP2RDATA_delay[20]; // rv 0 + assign MAXIGP2RDATA_in[21] = (MAXIGP2RDATA[21] !== 1'bz) && MAXIGP2RDATA_delay[21]; // rv 0 + assign MAXIGP2RDATA_in[22] = (MAXIGP2RDATA[22] !== 1'bz) && MAXIGP2RDATA_delay[22]; // rv 0 + assign MAXIGP2RDATA_in[23] = (MAXIGP2RDATA[23] !== 1'bz) && MAXIGP2RDATA_delay[23]; // rv 0 + assign MAXIGP2RDATA_in[24] = (MAXIGP2RDATA[24] !== 1'bz) && MAXIGP2RDATA_delay[24]; // rv 0 + assign MAXIGP2RDATA_in[25] = (MAXIGP2RDATA[25] !== 1'bz) && MAXIGP2RDATA_delay[25]; // rv 0 + assign MAXIGP2RDATA_in[26] = (MAXIGP2RDATA[26] !== 1'bz) && MAXIGP2RDATA_delay[26]; // rv 0 + assign MAXIGP2RDATA_in[27] = (MAXIGP2RDATA[27] !== 1'bz) && MAXIGP2RDATA_delay[27]; // rv 0 + assign MAXIGP2RDATA_in[28] = (MAXIGP2RDATA[28] !== 1'bz) && MAXIGP2RDATA_delay[28]; // rv 0 + assign MAXIGP2RDATA_in[29] = (MAXIGP2RDATA[29] !== 1'bz) && MAXIGP2RDATA_delay[29]; // rv 0 + assign MAXIGP2RDATA_in[2] = (MAXIGP2RDATA[2] !== 1'bz) && MAXIGP2RDATA_delay[2]; // rv 0 + assign MAXIGP2RDATA_in[30] = (MAXIGP2RDATA[30] !== 1'bz) && MAXIGP2RDATA_delay[30]; // rv 0 + assign MAXIGP2RDATA_in[31] = (MAXIGP2RDATA[31] !== 1'bz) && MAXIGP2RDATA_delay[31]; // rv 0 + assign MAXIGP2RDATA_in[32] = (MAXIGP2RDATA[32] !== 1'bz) && MAXIGP2RDATA_delay[32]; // rv 0 + assign MAXIGP2RDATA_in[33] = (MAXIGP2RDATA[33] !== 1'bz) && MAXIGP2RDATA_delay[33]; // rv 0 + assign MAXIGP2RDATA_in[34] = (MAXIGP2RDATA[34] !== 1'bz) && MAXIGP2RDATA_delay[34]; // rv 0 + assign MAXIGP2RDATA_in[35] = (MAXIGP2RDATA[35] !== 1'bz) && MAXIGP2RDATA_delay[35]; // rv 0 + assign MAXIGP2RDATA_in[36] = (MAXIGP2RDATA[36] !== 1'bz) && MAXIGP2RDATA_delay[36]; // rv 0 + assign MAXIGP2RDATA_in[37] = (MAXIGP2RDATA[37] !== 1'bz) && MAXIGP2RDATA_delay[37]; // rv 0 + assign MAXIGP2RDATA_in[38] = (MAXIGP2RDATA[38] !== 1'bz) && MAXIGP2RDATA_delay[38]; // rv 0 + assign MAXIGP2RDATA_in[39] = (MAXIGP2RDATA[39] !== 1'bz) && MAXIGP2RDATA_delay[39]; // rv 0 + assign MAXIGP2RDATA_in[3] = (MAXIGP2RDATA[3] !== 1'bz) && MAXIGP2RDATA_delay[3]; // rv 0 + assign MAXIGP2RDATA_in[40] = (MAXIGP2RDATA[40] !== 1'bz) && MAXIGP2RDATA_delay[40]; // rv 0 + assign MAXIGP2RDATA_in[41] = (MAXIGP2RDATA[41] !== 1'bz) && MAXIGP2RDATA_delay[41]; // rv 0 + assign MAXIGP2RDATA_in[42] = (MAXIGP2RDATA[42] !== 1'bz) && MAXIGP2RDATA_delay[42]; // rv 0 + assign MAXIGP2RDATA_in[43] = (MAXIGP2RDATA[43] !== 1'bz) && MAXIGP2RDATA_delay[43]; // rv 0 + assign MAXIGP2RDATA_in[44] = (MAXIGP2RDATA[44] !== 1'bz) && MAXIGP2RDATA_delay[44]; // rv 0 + assign MAXIGP2RDATA_in[45] = (MAXIGP2RDATA[45] !== 1'bz) && MAXIGP2RDATA_delay[45]; // rv 0 + assign MAXIGP2RDATA_in[46] = (MAXIGP2RDATA[46] !== 1'bz) && MAXIGP2RDATA_delay[46]; // rv 0 + assign MAXIGP2RDATA_in[47] = (MAXIGP2RDATA[47] !== 1'bz) && MAXIGP2RDATA_delay[47]; // rv 0 + assign MAXIGP2RDATA_in[48] = (MAXIGP2RDATA[48] !== 1'bz) && MAXIGP2RDATA_delay[48]; // rv 0 + assign MAXIGP2RDATA_in[49] = (MAXIGP2RDATA[49] !== 1'bz) && MAXIGP2RDATA_delay[49]; // rv 0 + assign MAXIGP2RDATA_in[4] = (MAXIGP2RDATA[4] !== 1'bz) && MAXIGP2RDATA_delay[4]; // rv 0 + assign MAXIGP2RDATA_in[50] = (MAXIGP2RDATA[50] !== 1'bz) && MAXIGP2RDATA_delay[50]; // rv 0 + assign MAXIGP2RDATA_in[51] = (MAXIGP2RDATA[51] !== 1'bz) && MAXIGP2RDATA_delay[51]; // rv 0 + assign MAXIGP2RDATA_in[52] = (MAXIGP2RDATA[52] !== 1'bz) && MAXIGP2RDATA_delay[52]; // rv 0 + assign MAXIGP2RDATA_in[53] = (MAXIGP2RDATA[53] !== 1'bz) && MAXIGP2RDATA_delay[53]; // rv 0 + assign MAXIGP2RDATA_in[54] = (MAXIGP2RDATA[54] !== 1'bz) && MAXIGP2RDATA_delay[54]; // rv 0 + assign MAXIGP2RDATA_in[55] = (MAXIGP2RDATA[55] !== 1'bz) && MAXIGP2RDATA_delay[55]; // rv 0 + assign MAXIGP2RDATA_in[56] = (MAXIGP2RDATA[56] !== 1'bz) && MAXIGP2RDATA_delay[56]; // rv 0 + assign MAXIGP2RDATA_in[57] = (MAXIGP2RDATA[57] !== 1'bz) && MAXIGP2RDATA_delay[57]; // rv 0 + assign MAXIGP2RDATA_in[58] = (MAXIGP2RDATA[58] !== 1'bz) && MAXIGP2RDATA_delay[58]; // rv 0 + assign MAXIGP2RDATA_in[59] = (MAXIGP2RDATA[59] !== 1'bz) && MAXIGP2RDATA_delay[59]; // rv 0 + assign MAXIGP2RDATA_in[5] = (MAXIGP2RDATA[5] !== 1'bz) && MAXIGP2RDATA_delay[5]; // rv 0 + assign MAXIGP2RDATA_in[60] = (MAXIGP2RDATA[60] !== 1'bz) && MAXIGP2RDATA_delay[60]; // rv 0 + assign MAXIGP2RDATA_in[61] = (MAXIGP2RDATA[61] !== 1'bz) && MAXIGP2RDATA_delay[61]; // rv 0 + assign MAXIGP2RDATA_in[62] = (MAXIGP2RDATA[62] !== 1'bz) && MAXIGP2RDATA_delay[62]; // rv 0 + assign MAXIGP2RDATA_in[63] = (MAXIGP2RDATA[63] !== 1'bz) && MAXIGP2RDATA_delay[63]; // rv 0 + assign MAXIGP2RDATA_in[64] = (MAXIGP2RDATA[64] !== 1'bz) && MAXIGP2RDATA_delay[64]; // rv 0 + assign MAXIGP2RDATA_in[65] = (MAXIGP2RDATA[65] !== 1'bz) && MAXIGP2RDATA_delay[65]; // rv 0 + assign MAXIGP2RDATA_in[66] = (MAXIGP2RDATA[66] !== 1'bz) && MAXIGP2RDATA_delay[66]; // rv 0 + assign MAXIGP2RDATA_in[67] = (MAXIGP2RDATA[67] !== 1'bz) && MAXIGP2RDATA_delay[67]; // rv 0 + assign MAXIGP2RDATA_in[68] = (MAXIGP2RDATA[68] !== 1'bz) && MAXIGP2RDATA_delay[68]; // rv 0 + assign MAXIGP2RDATA_in[69] = (MAXIGP2RDATA[69] !== 1'bz) && MAXIGP2RDATA_delay[69]; // rv 0 + assign MAXIGP2RDATA_in[6] = (MAXIGP2RDATA[6] !== 1'bz) && MAXIGP2RDATA_delay[6]; // rv 0 + assign MAXIGP2RDATA_in[70] = (MAXIGP2RDATA[70] !== 1'bz) && MAXIGP2RDATA_delay[70]; // rv 0 + assign MAXIGP2RDATA_in[71] = (MAXIGP2RDATA[71] !== 1'bz) && MAXIGP2RDATA_delay[71]; // rv 0 + assign MAXIGP2RDATA_in[72] = (MAXIGP2RDATA[72] !== 1'bz) && MAXIGP2RDATA_delay[72]; // rv 0 + assign MAXIGP2RDATA_in[73] = (MAXIGP2RDATA[73] !== 1'bz) && MAXIGP2RDATA_delay[73]; // rv 0 + assign MAXIGP2RDATA_in[74] = (MAXIGP2RDATA[74] !== 1'bz) && MAXIGP2RDATA_delay[74]; // rv 0 + assign MAXIGP2RDATA_in[75] = (MAXIGP2RDATA[75] !== 1'bz) && MAXIGP2RDATA_delay[75]; // rv 0 + assign MAXIGP2RDATA_in[76] = (MAXIGP2RDATA[76] !== 1'bz) && MAXIGP2RDATA_delay[76]; // rv 0 + assign MAXIGP2RDATA_in[77] = (MAXIGP2RDATA[77] !== 1'bz) && MAXIGP2RDATA_delay[77]; // rv 0 + assign MAXIGP2RDATA_in[78] = (MAXIGP2RDATA[78] !== 1'bz) && MAXIGP2RDATA_delay[78]; // rv 0 + assign MAXIGP2RDATA_in[79] = (MAXIGP2RDATA[79] !== 1'bz) && MAXIGP2RDATA_delay[79]; // rv 0 + assign MAXIGP2RDATA_in[7] = (MAXIGP2RDATA[7] !== 1'bz) && MAXIGP2RDATA_delay[7]; // rv 0 + assign MAXIGP2RDATA_in[80] = (MAXIGP2RDATA[80] !== 1'bz) && MAXIGP2RDATA_delay[80]; // rv 0 + assign MAXIGP2RDATA_in[81] = (MAXIGP2RDATA[81] !== 1'bz) && MAXIGP2RDATA_delay[81]; // rv 0 + assign MAXIGP2RDATA_in[82] = (MAXIGP2RDATA[82] !== 1'bz) && MAXIGP2RDATA_delay[82]; // rv 0 + assign MAXIGP2RDATA_in[83] = (MAXIGP2RDATA[83] !== 1'bz) && MAXIGP2RDATA_delay[83]; // rv 0 + assign MAXIGP2RDATA_in[84] = (MAXIGP2RDATA[84] !== 1'bz) && MAXIGP2RDATA_delay[84]; // rv 0 + assign MAXIGP2RDATA_in[85] = (MAXIGP2RDATA[85] !== 1'bz) && MAXIGP2RDATA_delay[85]; // rv 0 + assign MAXIGP2RDATA_in[86] = (MAXIGP2RDATA[86] !== 1'bz) && MAXIGP2RDATA_delay[86]; // rv 0 + assign MAXIGP2RDATA_in[87] = (MAXIGP2RDATA[87] !== 1'bz) && MAXIGP2RDATA_delay[87]; // rv 0 + assign MAXIGP2RDATA_in[88] = (MAXIGP2RDATA[88] !== 1'bz) && MAXIGP2RDATA_delay[88]; // rv 0 + assign MAXIGP2RDATA_in[89] = (MAXIGP2RDATA[89] !== 1'bz) && MAXIGP2RDATA_delay[89]; // rv 0 + assign MAXIGP2RDATA_in[8] = (MAXIGP2RDATA[8] !== 1'bz) && MAXIGP2RDATA_delay[8]; // rv 0 + assign MAXIGP2RDATA_in[90] = (MAXIGP2RDATA[90] !== 1'bz) && MAXIGP2RDATA_delay[90]; // rv 0 + assign MAXIGP2RDATA_in[91] = (MAXIGP2RDATA[91] !== 1'bz) && MAXIGP2RDATA_delay[91]; // rv 0 + assign MAXIGP2RDATA_in[92] = (MAXIGP2RDATA[92] !== 1'bz) && MAXIGP2RDATA_delay[92]; // rv 0 + assign MAXIGP2RDATA_in[93] = (MAXIGP2RDATA[93] !== 1'bz) && MAXIGP2RDATA_delay[93]; // rv 0 + assign MAXIGP2RDATA_in[94] = (MAXIGP2RDATA[94] !== 1'bz) && MAXIGP2RDATA_delay[94]; // rv 0 + assign MAXIGP2RDATA_in[95] = (MAXIGP2RDATA[95] !== 1'bz) && MAXIGP2RDATA_delay[95]; // rv 0 + assign MAXIGP2RDATA_in[96] = (MAXIGP2RDATA[96] !== 1'bz) && MAXIGP2RDATA_delay[96]; // rv 0 + assign MAXIGP2RDATA_in[97] = (MAXIGP2RDATA[97] !== 1'bz) && MAXIGP2RDATA_delay[97]; // rv 0 + assign MAXIGP2RDATA_in[98] = (MAXIGP2RDATA[98] !== 1'bz) && MAXIGP2RDATA_delay[98]; // rv 0 + assign MAXIGP2RDATA_in[99] = (MAXIGP2RDATA[99] !== 1'bz) && MAXIGP2RDATA_delay[99]; // rv 0 + assign MAXIGP2RDATA_in[9] = (MAXIGP2RDATA[9] !== 1'bz) && MAXIGP2RDATA_delay[9]; // rv 0 + assign MAXIGP2RID_in[0] = (MAXIGP2RID[0] !== 1'bz) && MAXIGP2RID_delay[0]; // rv 0 + assign MAXIGP2RID_in[10] = (MAXIGP2RID[10] !== 1'bz) && MAXIGP2RID_delay[10]; // rv 0 + assign MAXIGP2RID_in[11] = (MAXIGP2RID[11] !== 1'bz) && MAXIGP2RID_delay[11]; // rv 0 + assign MAXIGP2RID_in[12] = (MAXIGP2RID[12] !== 1'bz) && MAXIGP2RID_delay[12]; // rv 0 + assign MAXIGP2RID_in[13] = (MAXIGP2RID[13] !== 1'bz) && MAXIGP2RID_delay[13]; // rv 0 + assign MAXIGP2RID_in[14] = (MAXIGP2RID[14] !== 1'bz) && MAXIGP2RID_delay[14]; // rv 0 + assign MAXIGP2RID_in[15] = (MAXIGP2RID[15] !== 1'bz) && MAXIGP2RID_delay[15]; // rv 0 + assign MAXIGP2RID_in[1] = (MAXIGP2RID[1] !== 1'bz) && MAXIGP2RID_delay[1]; // rv 0 + assign MAXIGP2RID_in[2] = (MAXIGP2RID[2] !== 1'bz) && MAXIGP2RID_delay[2]; // rv 0 + assign MAXIGP2RID_in[3] = (MAXIGP2RID[3] !== 1'bz) && MAXIGP2RID_delay[3]; // rv 0 + assign MAXIGP2RID_in[4] = (MAXIGP2RID[4] !== 1'bz) && MAXIGP2RID_delay[4]; // rv 0 + assign MAXIGP2RID_in[5] = (MAXIGP2RID[5] !== 1'bz) && MAXIGP2RID_delay[5]; // rv 0 + assign MAXIGP2RID_in[6] = (MAXIGP2RID[6] !== 1'bz) && MAXIGP2RID_delay[6]; // rv 0 + assign MAXIGP2RID_in[7] = (MAXIGP2RID[7] !== 1'bz) && MAXIGP2RID_delay[7]; // rv 0 + assign MAXIGP2RID_in[8] = (MAXIGP2RID[8] !== 1'bz) && MAXIGP2RID_delay[8]; // rv 0 + assign MAXIGP2RID_in[9] = (MAXIGP2RID[9] !== 1'bz) && MAXIGP2RID_delay[9]; // rv 0 + assign MAXIGP2RLAST_in = (MAXIGP2RLAST !== 1'bz) && MAXIGP2RLAST_delay; // rv 0 + assign MAXIGP2RRESP_in[0] = (MAXIGP2RRESP[0] !== 1'bz) && MAXIGP2RRESP_delay[0]; // rv 0 + assign MAXIGP2RRESP_in[1] = (MAXIGP2RRESP[1] !== 1'bz) && MAXIGP2RRESP_delay[1]; // rv 0 + assign MAXIGP2RVALID_in = (MAXIGP2RVALID !== 1'bz) && MAXIGP2RVALID_delay; // rv 0 + assign MAXIGP2WREADY_in = (MAXIGP2WREADY !== 1'bz) && MAXIGP2WREADY_delay; // rv 0 + assign PL2ADMACVLD_in[0] = (PL2ADMACVLD[0] !== 1'bz) && PL2ADMACVLD_delay[0]; // rv 0 + assign PL2ADMACVLD_in[1] = (PL2ADMACVLD[1] !== 1'bz) && PL2ADMACVLD_delay[1]; // rv 0 + assign PL2ADMACVLD_in[2] = (PL2ADMACVLD[2] !== 1'bz) && PL2ADMACVLD_delay[2]; // rv 0 + assign PL2ADMACVLD_in[3] = (PL2ADMACVLD[3] !== 1'bz) && PL2ADMACVLD_delay[3]; // rv 0 + assign PL2ADMACVLD_in[4] = (PL2ADMACVLD[4] !== 1'bz) && PL2ADMACVLD_delay[4]; // rv 0 + assign PL2ADMACVLD_in[5] = (PL2ADMACVLD[5] !== 1'bz) && PL2ADMACVLD_delay[5]; // rv 0 + assign PL2ADMACVLD_in[6] = (PL2ADMACVLD[6] !== 1'bz) && PL2ADMACVLD_delay[6]; // rv 0 + assign PL2ADMACVLD_in[7] = (PL2ADMACVLD[7] !== 1'bz) && PL2ADMACVLD_delay[7]; // rv 0 + assign PL2ADMATACK_in[0] = (PL2ADMATACK[0] !== 1'bz) && PL2ADMATACK_delay[0]; // rv 0 + assign PL2ADMATACK_in[1] = (PL2ADMATACK[1] !== 1'bz) && PL2ADMATACK_delay[1]; // rv 0 + assign PL2ADMATACK_in[2] = (PL2ADMATACK[2] !== 1'bz) && PL2ADMATACK_delay[2]; // rv 0 + assign PL2ADMATACK_in[3] = (PL2ADMATACK[3] !== 1'bz) && PL2ADMATACK_delay[3]; // rv 0 + assign PL2ADMATACK_in[4] = (PL2ADMATACK[4] !== 1'bz) && PL2ADMATACK_delay[4]; // rv 0 + assign PL2ADMATACK_in[5] = (PL2ADMATACK[5] !== 1'bz) && PL2ADMATACK_delay[5]; // rv 0 + assign PL2ADMATACK_in[6] = (PL2ADMATACK[6] !== 1'bz) && PL2ADMATACK_delay[6]; // rv 0 + assign PL2ADMATACK_in[7] = (PL2ADMATACK[7] !== 1'bz) && PL2ADMATACK_delay[7]; // rv 0 + assign PL2GDMACVLD_in[0] = (PL2GDMACVLD[0] !== 1'bz) && PL2GDMACVLD_delay[0]; // rv 0 + assign PL2GDMACVLD_in[1] = (PL2GDMACVLD[1] !== 1'bz) && PL2GDMACVLD_delay[1]; // rv 0 + assign PL2GDMACVLD_in[2] = (PL2GDMACVLD[2] !== 1'bz) && PL2GDMACVLD_delay[2]; // rv 0 + assign PL2GDMACVLD_in[3] = (PL2GDMACVLD[3] !== 1'bz) && PL2GDMACVLD_delay[3]; // rv 0 + assign PL2GDMACVLD_in[4] = (PL2GDMACVLD[4] !== 1'bz) && PL2GDMACVLD_delay[4]; // rv 0 + assign PL2GDMACVLD_in[5] = (PL2GDMACVLD[5] !== 1'bz) && PL2GDMACVLD_delay[5]; // rv 0 + assign PL2GDMACVLD_in[6] = (PL2GDMACVLD[6] !== 1'bz) && PL2GDMACVLD_delay[6]; // rv 0 + assign PL2GDMACVLD_in[7] = (PL2GDMACVLD[7] !== 1'bz) && PL2GDMACVLD_delay[7]; // rv 0 + assign PL2GDMATACK_in[0] = (PL2GDMATACK[0] !== 1'bz) && PL2GDMATACK_delay[0]; // rv 0 + assign PL2GDMATACK_in[1] = (PL2GDMATACK[1] !== 1'bz) && PL2GDMATACK_delay[1]; // rv 0 + assign PL2GDMATACK_in[2] = (PL2GDMATACK[2] !== 1'bz) && PL2GDMATACK_delay[2]; // rv 0 + assign PL2GDMATACK_in[3] = (PL2GDMATACK[3] !== 1'bz) && PL2GDMATACK_delay[3]; // rv 0 + assign PL2GDMATACK_in[4] = (PL2GDMATACK[4] !== 1'bz) && PL2GDMATACK_delay[4]; // rv 0 + assign PL2GDMATACK_in[5] = (PL2GDMATACK[5] !== 1'bz) && PL2GDMATACK_delay[5]; // rv 0 + assign PL2GDMATACK_in[6] = (PL2GDMATACK[6] !== 1'bz) && PL2GDMATACK_delay[6]; // rv 0 + assign PL2GDMATACK_in[7] = (PL2GDMATACK[7] !== 1'bz) && PL2GDMATACK_delay[7]; // rv 0 + assign PLACECLK_in = (PLACECLK !== 1'bz) && PLACECLK_delay; // rv 0 + assign SACEFPDACREADY_in = (SACEFPDACREADY !== 1'bz) && SACEFPDACREADY_delay; // rv 0 + assign SACEFPDARADDR_in[0] = (SACEFPDARADDR[0] !== 1'bz) && SACEFPDARADDR_delay[0]; // rv 0 + assign SACEFPDARADDR_in[10] = (SACEFPDARADDR[10] !== 1'bz) && SACEFPDARADDR_delay[10]; // rv 0 + assign SACEFPDARADDR_in[11] = (SACEFPDARADDR[11] !== 1'bz) && SACEFPDARADDR_delay[11]; // rv 0 + assign SACEFPDARADDR_in[12] = (SACEFPDARADDR[12] !== 1'bz) && SACEFPDARADDR_delay[12]; // rv 0 + assign SACEFPDARADDR_in[13] = (SACEFPDARADDR[13] !== 1'bz) && SACEFPDARADDR_delay[13]; // rv 0 + assign SACEFPDARADDR_in[14] = (SACEFPDARADDR[14] !== 1'bz) && SACEFPDARADDR_delay[14]; // rv 0 + assign SACEFPDARADDR_in[15] = (SACEFPDARADDR[15] !== 1'bz) && SACEFPDARADDR_delay[15]; // rv 0 + assign SACEFPDARADDR_in[16] = (SACEFPDARADDR[16] !== 1'bz) && SACEFPDARADDR_delay[16]; // rv 0 + assign SACEFPDARADDR_in[17] = (SACEFPDARADDR[17] !== 1'bz) && SACEFPDARADDR_delay[17]; // rv 0 + assign SACEFPDARADDR_in[18] = (SACEFPDARADDR[18] !== 1'bz) && SACEFPDARADDR_delay[18]; // rv 0 + assign SACEFPDARADDR_in[19] = (SACEFPDARADDR[19] !== 1'bz) && SACEFPDARADDR_delay[19]; // rv 0 + assign SACEFPDARADDR_in[1] = (SACEFPDARADDR[1] !== 1'bz) && SACEFPDARADDR_delay[1]; // rv 0 + assign SACEFPDARADDR_in[20] = (SACEFPDARADDR[20] !== 1'bz) && SACEFPDARADDR_delay[20]; // rv 0 + assign SACEFPDARADDR_in[21] = (SACEFPDARADDR[21] !== 1'bz) && SACEFPDARADDR_delay[21]; // rv 0 + assign SACEFPDARADDR_in[22] = (SACEFPDARADDR[22] !== 1'bz) && SACEFPDARADDR_delay[22]; // rv 0 + assign SACEFPDARADDR_in[23] = (SACEFPDARADDR[23] !== 1'bz) && SACEFPDARADDR_delay[23]; // rv 0 + assign SACEFPDARADDR_in[24] = (SACEFPDARADDR[24] !== 1'bz) && SACEFPDARADDR_delay[24]; // rv 0 + assign SACEFPDARADDR_in[25] = (SACEFPDARADDR[25] !== 1'bz) && SACEFPDARADDR_delay[25]; // rv 0 + assign SACEFPDARADDR_in[26] = (SACEFPDARADDR[26] !== 1'bz) && SACEFPDARADDR_delay[26]; // rv 0 + assign SACEFPDARADDR_in[27] = (SACEFPDARADDR[27] !== 1'bz) && SACEFPDARADDR_delay[27]; // rv 0 + assign SACEFPDARADDR_in[28] = (SACEFPDARADDR[28] !== 1'bz) && SACEFPDARADDR_delay[28]; // rv 0 + assign SACEFPDARADDR_in[29] = (SACEFPDARADDR[29] !== 1'bz) && SACEFPDARADDR_delay[29]; // rv 0 + assign SACEFPDARADDR_in[2] = (SACEFPDARADDR[2] !== 1'bz) && SACEFPDARADDR_delay[2]; // rv 0 + assign SACEFPDARADDR_in[30] = (SACEFPDARADDR[30] !== 1'bz) && SACEFPDARADDR_delay[30]; // rv 0 + assign SACEFPDARADDR_in[31] = (SACEFPDARADDR[31] !== 1'bz) && SACEFPDARADDR_delay[31]; // rv 0 + assign SACEFPDARADDR_in[32] = (SACEFPDARADDR[32] !== 1'bz) && SACEFPDARADDR_delay[32]; // rv 0 + assign SACEFPDARADDR_in[33] = (SACEFPDARADDR[33] !== 1'bz) && SACEFPDARADDR_delay[33]; // rv 0 + assign SACEFPDARADDR_in[34] = (SACEFPDARADDR[34] !== 1'bz) && SACEFPDARADDR_delay[34]; // rv 0 + assign SACEFPDARADDR_in[35] = (SACEFPDARADDR[35] !== 1'bz) && SACEFPDARADDR_delay[35]; // rv 0 + assign SACEFPDARADDR_in[36] = (SACEFPDARADDR[36] !== 1'bz) && SACEFPDARADDR_delay[36]; // rv 0 + assign SACEFPDARADDR_in[37] = (SACEFPDARADDR[37] !== 1'bz) && SACEFPDARADDR_delay[37]; // rv 0 + assign SACEFPDARADDR_in[38] = (SACEFPDARADDR[38] !== 1'bz) && SACEFPDARADDR_delay[38]; // rv 0 + assign SACEFPDARADDR_in[39] = (SACEFPDARADDR[39] !== 1'bz) && SACEFPDARADDR_delay[39]; // rv 0 + assign SACEFPDARADDR_in[3] = (SACEFPDARADDR[3] !== 1'bz) && SACEFPDARADDR_delay[3]; // rv 0 + assign SACEFPDARADDR_in[40] = (SACEFPDARADDR[40] !== 1'bz) && SACEFPDARADDR_delay[40]; // rv 0 + assign SACEFPDARADDR_in[41] = (SACEFPDARADDR[41] !== 1'bz) && SACEFPDARADDR_delay[41]; // rv 0 + assign SACEFPDARADDR_in[42] = (SACEFPDARADDR[42] !== 1'bz) && SACEFPDARADDR_delay[42]; // rv 0 + assign SACEFPDARADDR_in[43] = (SACEFPDARADDR[43] !== 1'bz) && SACEFPDARADDR_delay[43]; // rv 0 + assign SACEFPDARADDR_in[4] = (SACEFPDARADDR[4] !== 1'bz) && SACEFPDARADDR_delay[4]; // rv 0 + assign SACEFPDARADDR_in[5] = (SACEFPDARADDR[5] !== 1'bz) && SACEFPDARADDR_delay[5]; // rv 0 + assign SACEFPDARADDR_in[6] = (SACEFPDARADDR[6] !== 1'bz) && SACEFPDARADDR_delay[6]; // rv 0 + assign SACEFPDARADDR_in[7] = (SACEFPDARADDR[7] !== 1'bz) && SACEFPDARADDR_delay[7]; // rv 0 + assign SACEFPDARADDR_in[8] = (SACEFPDARADDR[8] !== 1'bz) && SACEFPDARADDR_delay[8]; // rv 0 + assign SACEFPDARADDR_in[9] = (SACEFPDARADDR[9] !== 1'bz) && SACEFPDARADDR_delay[9]; // rv 0 + assign SACEFPDARBAR_in[0] = (SACEFPDARBAR[0] !== 1'bz) && SACEFPDARBAR_delay[0]; // rv 0 + assign SACEFPDARBAR_in[1] = (SACEFPDARBAR[1] !== 1'bz) && SACEFPDARBAR_delay[1]; // rv 0 + assign SACEFPDARBURST_in[0] = (SACEFPDARBURST[0] !== 1'bz) && SACEFPDARBURST_delay[0]; // rv 0 + assign SACEFPDARBURST_in[1] = (SACEFPDARBURST[1] !== 1'bz) && SACEFPDARBURST_delay[1]; // rv 0 + assign SACEFPDARCACHE_in[0] = (SACEFPDARCACHE[0] !== 1'bz) && SACEFPDARCACHE_delay[0]; // rv 0 + assign SACEFPDARCACHE_in[1] = (SACEFPDARCACHE[1] !== 1'bz) && SACEFPDARCACHE_delay[1]; // rv 0 + assign SACEFPDARCACHE_in[2] = (SACEFPDARCACHE[2] !== 1'bz) && SACEFPDARCACHE_delay[2]; // rv 0 + assign SACEFPDARCACHE_in[3] = (SACEFPDARCACHE[3] !== 1'bz) && SACEFPDARCACHE_delay[3]; // rv 0 + assign SACEFPDARDOMAIN_in[0] = (SACEFPDARDOMAIN[0] !== 1'bz) && SACEFPDARDOMAIN_delay[0]; // rv 0 + assign SACEFPDARDOMAIN_in[1] = (SACEFPDARDOMAIN[1] !== 1'bz) && SACEFPDARDOMAIN_delay[1]; // rv 0 + assign SACEFPDARID_in[0] = (SACEFPDARID[0] !== 1'bz) && SACEFPDARID_delay[0]; // rv 0 + assign SACEFPDARID_in[1] = (SACEFPDARID[1] !== 1'bz) && SACEFPDARID_delay[1]; // rv 0 + assign SACEFPDARID_in[2] = (SACEFPDARID[2] !== 1'bz) && SACEFPDARID_delay[2]; // rv 0 + assign SACEFPDARID_in[3] = (SACEFPDARID[3] !== 1'bz) && SACEFPDARID_delay[3]; // rv 0 + assign SACEFPDARID_in[4] = (SACEFPDARID[4] !== 1'bz) && SACEFPDARID_delay[4]; // rv 0 + assign SACEFPDARID_in[5] = (SACEFPDARID[5] !== 1'bz) && SACEFPDARID_delay[5]; // rv 0 + assign SACEFPDARLEN_in[0] = (SACEFPDARLEN[0] !== 1'bz) && SACEFPDARLEN_delay[0]; // rv 0 + assign SACEFPDARLEN_in[1] = (SACEFPDARLEN[1] !== 1'bz) && SACEFPDARLEN_delay[1]; // rv 0 + assign SACEFPDARLEN_in[2] = (SACEFPDARLEN[2] !== 1'bz) && SACEFPDARLEN_delay[2]; // rv 0 + assign SACEFPDARLEN_in[3] = (SACEFPDARLEN[3] !== 1'bz) && SACEFPDARLEN_delay[3]; // rv 0 + assign SACEFPDARLEN_in[4] = (SACEFPDARLEN[4] !== 1'bz) && SACEFPDARLEN_delay[4]; // rv 0 + assign SACEFPDARLEN_in[5] = (SACEFPDARLEN[5] !== 1'bz) && SACEFPDARLEN_delay[5]; // rv 0 + assign SACEFPDARLEN_in[6] = (SACEFPDARLEN[6] !== 1'bz) && SACEFPDARLEN_delay[6]; // rv 0 + assign SACEFPDARLEN_in[7] = (SACEFPDARLEN[7] !== 1'bz) && SACEFPDARLEN_delay[7]; // rv 0 + assign SACEFPDARLOCK_in = (SACEFPDARLOCK !== 1'bz) && SACEFPDARLOCK_delay; // rv 0 + assign SACEFPDARPROT_in[0] = (SACEFPDARPROT[0] !== 1'bz) && SACEFPDARPROT_delay[0]; // rv 0 + assign SACEFPDARPROT_in[1] = (SACEFPDARPROT[1] !== 1'bz) && SACEFPDARPROT_delay[1]; // rv 0 + assign SACEFPDARPROT_in[2] = (SACEFPDARPROT[2] !== 1'bz) && SACEFPDARPROT_delay[2]; // rv 0 + assign SACEFPDARQOS_in[0] = (SACEFPDARQOS[0] !== 1'bz) && SACEFPDARQOS_delay[0]; // rv 0 + assign SACEFPDARQOS_in[1] = (SACEFPDARQOS[1] !== 1'bz) && SACEFPDARQOS_delay[1]; // rv 0 + assign SACEFPDARQOS_in[2] = (SACEFPDARQOS[2] !== 1'bz) && SACEFPDARQOS_delay[2]; // rv 0 + assign SACEFPDARQOS_in[3] = (SACEFPDARQOS[3] !== 1'bz) && SACEFPDARQOS_delay[3]; // rv 0 + assign SACEFPDARREGION_in[0] = (SACEFPDARREGION[0] !== 1'bz) && SACEFPDARREGION_delay[0]; // rv 0 + assign SACEFPDARREGION_in[1] = (SACEFPDARREGION[1] !== 1'bz) && SACEFPDARREGION_delay[1]; // rv 0 + assign SACEFPDARREGION_in[2] = (SACEFPDARREGION[2] !== 1'bz) && SACEFPDARREGION_delay[2]; // rv 0 + assign SACEFPDARREGION_in[3] = (SACEFPDARREGION[3] !== 1'bz) && SACEFPDARREGION_delay[3]; // rv 0 + assign SACEFPDARSIZE_in[0] = (SACEFPDARSIZE[0] !== 1'bz) && SACEFPDARSIZE_delay[0]; // rv 0 + assign SACEFPDARSIZE_in[1] = (SACEFPDARSIZE[1] !== 1'bz) && SACEFPDARSIZE_delay[1]; // rv 0 + assign SACEFPDARSIZE_in[2] = (SACEFPDARSIZE[2] !== 1'bz) && SACEFPDARSIZE_delay[2]; // rv 0 + assign SACEFPDARSNOOP_in[0] = (SACEFPDARSNOOP[0] !== 1'bz) && SACEFPDARSNOOP_delay[0]; // rv 0 + assign SACEFPDARSNOOP_in[1] = (SACEFPDARSNOOP[1] !== 1'bz) && SACEFPDARSNOOP_delay[1]; // rv 0 + assign SACEFPDARSNOOP_in[2] = (SACEFPDARSNOOP[2] !== 1'bz) && SACEFPDARSNOOP_delay[2]; // rv 0 + assign SACEFPDARSNOOP_in[3] = (SACEFPDARSNOOP[3] !== 1'bz) && SACEFPDARSNOOP_delay[3]; // rv 0 + assign SACEFPDARUSER_in[0] = (SACEFPDARUSER[0] !== 1'bz) && SACEFPDARUSER_delay[0]; // rv 0 + assign SACEFPDARUSER_in[10] = (SACEFPDARUSER[10] !== 1'bz) && SACEFPDARUSER_delay[10]; // rv 0 + assign SACEFPDARUSER_in[11] = (SACEFPDARUSER[11] !== 1'bz) && SACEFPDARUSER_delay[11]; // rv 0 + assign SACEFPDARUSER_in[12] = (SACEFPDARUSER[12] !== 1'bz) && SACEFPDARUSER_delay[12]; // rv 0 + assign SACEFPDARUSER_in[13] = (SACEFPDARUSER[13] !== 1'bz) && SACEFPDARUSER_delay[13]; // rv 0 + assign SACEFPDARUSER_in[14] = (SACEFPDARUSER[14] !== 1'bz) && SACEFPDARUSER_delay[14]; // rv 0 + assign SACEFPDARUSER_in[15] = (SACEFPDARUSER[15] !== 1'bz) && SACEFPDARUSER_delay[15]; // rv 0 + assign SACEFPDARUSER_in[1] = (SACEFPDARUSER[1] !== 1'bz) && SACEFPDARUSER_delay[1]; // rv 0 + assign SACEFPDARUSER_in[2] = (SACEFPDARUSER[2] !== 1'bz) && SACEFPDARUSER_delay[2]; // rv 0 + assign SACEFPDARUSER_in[3] = (SACEFPDARUSER[3] !== 1'bz) && SACEFPDARUSER_delay[3]; // rv 0 + assign SACEFPDARUSER_in[4] = (SACEFPDARUSER[4] !== 1'bz) && SACEFPDARUSER_delay[4]; // rv 0 + assign SACEFPDARUSER_in[5] = (SACEFPDARUSER[5] !== 1'bz) && SACEFPDARUSER_delay[5]; // rv 0 + assign SACEFPDARUSER_in[6] = (SACEFPDARUSER[6] !== 1'bz) && SACEFPDARUSER_delay[6]; // rv 0 + assign SACEFPDARUSER_in[7] = (SACEFPDARUSER[7] !== 1'bz) && SACEFPDARUSER_delay[7]; // rv 0 + assign SACEFPDARUSER_in[8] = (SACEFPDARUSER[8] !== 1'bz) && SACEFPDARUSER_delay[8]; // rv 0 + assign SACEFPDARUSER_in[9] = (SACEFPDARUSER[9] !== 1'bz) && SACEFPDARUSER_delay[9]; // rv 0 + assign SACEFPDARVALID_in = (SACEFPDARVALID !== 1'bz) && SACEFPDARVALID_delay; // rv 0 + assign SACEFPDAWADDR_in[0] = (SACEFPDAWADDR[0] !== 1'bz) && SACEFPDAWADDR_delay[0]; // rv 0 + assign SACEFPDAWADDR_in[10] = (SACEFPDAWADDR[10] !== 1'bz) && SACEFPDAWADDR_delay[10]; // rv 0 + assign SACEFPDAWADDR_in[11] = (SACEFPDAWADDR[11] !== 1'bz) && SACEFPDAWADDR_delay[11]; // rv 0 + assign SACEFPDAWADDR_in[12] = (SACEFPDAWADDR[12] !== 1'bz) && SACEFPDAWADDR_delay[12]; // rv 0 + assign SACEFPDAWADDR_in[13] = (SACEFPDAWADDR[13] !== 1'bz) && SACEFPDAWADDR_delay[13]; // rv 0 + assign SACEFPDAWADDR_in[14] = (SACEFPDAWADDR[14] !== 1'bz) && SACEFPDAWADDR_delay[14]; // rv 0 + assign SACEFPDAWADDR_in[15] = (SACEFPDAWADDR[15] !== 1'bz) && SACEFPDAWADDR_delay[15]; // rv 0 + assign SACEFPDAWADDR_in[16] = (SACEFPDAWADDR[16] !== 1'bz) && SACEFPDAWADDR_delay[16]; // rv 0 + assign SACEFPDAWADDR_in[17] = (SACEFPDAWADDR[17] !== 1'bz) && SACEFPDAWADDR_delay[17]; // rv 0 + assign SACEFPDAWADDR_in[18] = (SACEFPDAWADDR[18] !== 1'bz) && SACEFPDAWADDR_delay[18]; // rv 0 + assign SACEFPDAWADDR_in[19] = (SACEFPDAWADDR[19] !== 1'bz) && SACEFPDAWADDR_delay[19]; // rv 0 + assign SACEFPDAWADDR_in[1] = (SACEFPDAWADDR[1] !== 1'bz) && SACEFPDAWADDR_delay[1]; // rv 0 + assign SACEFPDAWADDR_in[20] = (SACEFPDAWADDR[20] !== 1'bz) && SACEFPDAWADDR_delay[20]; // rv 0 + assign SACEFPDAWADDR_in[21] = (SACEFPDAWADDR[21] !== 1'bz) && SACEFPDAWADDR_delay[21]; // rv 0 + assign SACEFPDAWADDR_in[22] = (SACEFPDAWADDR[22] !== 1'bz) && SACEFPDAWADDR_delay[22]; // rv 0 + assign SACEFPDAWADDR_in[23] = (SACEFPDAWADDR[23] !== 1'bz) && SACEFPDAWADDR_delay[23]; // rv 0 + assign SACEFPDAWADDR_in[24] = (SACEFPDAWADDR[24] !== 1'bz) && SACEFPDAWADDR_delay[24]; // rv 0 + assign SACEFPDAWADDR_in[25] = (SACEFPDAWADDR[25] !== 1'bz) && SACEFPDAWADDR_delay[25]; // rv 0 + assign SACEFPDAWADDR_in[26] = (SACEFPDAWADDR[26] !== 1'bz) && SACEFPDAWADDR_delay[26]; // rv 0 + assign SACEFPDAWADDR_in[27] = (SACEFPDAWADDR[27] !== 1'bz) && SACEFPDAWADDR_delay[27]; // rv 0 + assign SACEFPDAWADDR_in[28] = (SACEFPDAWADDR[28] !== 1'bz) && SACEFPDAWADDR_delay[28]; // rv 0 + assign SACEFPDAWADDR_in[29] = (SACEFPDAWADDR[29] !== 1'bz) && SACEFPDAWADDR_delay[29]; // rv 0 + assign SACEFPDAWADDR_in[2] = (SACEFPDAWADDR[2] !== 1'bz) && SACEFPDAWADDR_delay[2]; // rv 0 + assign SACEFPDAWADDR_in[30] = (SACEFPDAWADDR[30] !== 1'bz) && SACEFPDAWADDR_delay[30]; // rv 0 + assign SACEFPDAWADDR_in[31] = (SACEFPDAWADDR[31] !== 1'bz) && SACEFPDAWADDR_delay[31]; // rv 0 + assign SACEFPDAWADDR_in[32] = (SACEFPDAWADDR[32] !== 1'bz) && SACEFPDAWADDR_delay[32]; // rv 0 + assign SACEFPDAWADDR_in[33] = (SACEFPDAWADDR[33] !== 1'bz) && SACEFPDAWADDR_delay[33]; // rv 0 + assign SACEFPDAWADDR_in[34] = (SACEFPDAWADDR[34] !== 1'bz) && SACEFPDAWADDR_delay[34]; // rv 0 + assign SACEFPDAWADDR_in[35] = (SACEFPDAWADDR[35] !== 1'bz) && SACEFPDAWADDR_delay[35]; // rv 0 + assign SACEFPDAWADDR_in[36] = (SACEFPDAWADDR[36] !== 1'bz) && SACEFPDAWADDR_delay[36]; // rv 0 + assign SACEFPDAWADDR_in[37] = (SACEFPDAWADDR[37] !== 1'bz) && SACEFPDAWADDR_delay[37]; // rv 0 + assign SACEFPDAWADDR_in[38] = (SACEFPDAWADDR[38] !== 1'bz) && SACEFPDAWADDR_delay[38]; // rv 0 + assign SACEFPDAWADDR_in[39] = (SACEFPDAWADDR[39] !== 1'bz) && SACEFPDAWADDR_delay[39]; // rv 0 + assign SACEFPDAWADDR_in[3] = (SACEFPDAWADDR[3] !== 1'bz) && SACEFPDAWADDR_delay[3]; // rv 0 + assign SACEFPDAWADDR_in[40] = (SACEFPDAWADDR[40] !== 1'bz) && SACEFPDAWADDR_delay[40]; // rv 0 + assign SACEFPDAWADDR_in[41] = (SACEFPDAWADDR[41] !== 1'bz) && SACEFPDAWADDR_delay[41]; // rv 0 + assign SACEFPDAWADDR_in[42] = (SACEFPDAWADDR[42] !== 1'bz) && SACEFPDAWADDR_delay[42]; // rv 0 + assign SACEFPDAWADDR_in[43] = (SACEFPDAWADDR[43] !== 1'bz) && SACEFPDAWADDR_delay[43]; // rv 0 + assign SACEFPDAWADDR_in[4] = (SACEFPDAWADDR[4] !== 1'bz) && SACEFPDAWADDR_delay[4]; // rv 0 + assign SACEFPDAWADDR_in[5] = (SACEFPDAWADDR[5] !== 1'bz) && SACEFPDAWADDR_delay[5]; // rv 0 + assign SACEFPDAWADDR_in[6] = (SACEFPDAWADDR[6] !== 1'bz) && SACEFPDAWADDR_delay[6]; // rv 0 + assign SACEFPDAWADDR_in[7] = (SACEFPDAWADDR[7] !== 1'bz) && SACEFPDAWADDR_delay[7]; // rv 0 + assign SACEFPDAWADDR_in[8] = (SACEFPDAWADDR[8] !== 1'bz) && SACEFPDAWADDR_delay[8]; // rv 0 + assign SACEFPDAWADDR_in[9] = (SACEFPDAWADDR[9] !== 1'bz) && SACEFPDAWADDR_delay[9]; // rv 0 + assign SACEFPDAWBAR_in[0] = (SACEFPDAWBAR[0] !== 1'bz) && SACEFPDAWBAR_delay[0]; // rv 0 + assign SACEFPDAWBAR_in[1] = (SACEFPDAWBAR[1] !== 1'bz) && SACEFPDAWBAR_delay[1]; // rv 0 + assign SACEFPDAWBURST_in[0] = (SACEFPDAWBURST[0] !== 1'bz) && SACEFPDAWBURST_delay[0]; // rv 0 + assign SACEFPDAWBURST_in[1] = (SACEFPDAWBURST[1] !== 1'bz) && SACEFPDAWBURST_delay[1]; // rv 0 + assign SACEFPDAWCACHE_in[0] = (SACEFPDAWCACHE[0] !== 1'bz) && SACEFPDAWCACHE_delay[0]; // rv 0 + assign SACEFPDAWCACHE_in[1] = (SACEFPDAWCACHE[1] !== 1'bz) && SACEFPDAWCACHE_delay[1]; // rv 0 + assign SACEFPDAWCACHE_in[2] = (SACEFPDAWCACHE[2] !== 1'bz) && SACEFPDAWCACHE_delay[2]; // rv 0 + assign SACEFPDAWCACHE_in[3] = (SACEFPDAWCACHE[3] !== 1'bz) && SACEFPDAWCACHE_delay[3]; // rv 0 + assign SACEFPDAWDOMAIN_in[0] = (SACEFPDAWDOMAIN[0] !== 1'bz) && SACEFPDAWDOMAIN_delay[0]; // rv 0 + assign SACEFPDAWDOMAIN_in[1] = (SACEFPDAWDOMAIN[1] !== 1'bz) && SACEFPDAWDOMAIN_delay[1]; // rv 0 + assign SACEFPDAWID_in[0] = (SACEFPDAWID[0] !== 1'bz) && SACEFPDAWID_delay[0]; // rv 0 + assign SACEFPDAWID_in[1] = (SACEFPDAWID[1] !== 1'bz) && SACEFPDAWID_delay[1]; // rv 0 + assign SACEFPDAWID_in[2] = (SACEFPDAWID[2] !== 1'bz) && SACEFPDAWID_delay[2]; // rv 0 + assign SACEFPDAWID_in[3] = (SACEFPDAWID[3] !== 1'bz) && SACEFPDAWID_delay[3]; // rv 0 + assign SACEFPDAWID_in[4] = (SACEFPDAWID[4] !== 1'bz) && SACEFPDAWID_delay[4]; // rv 0 + assign SACEFPDAWID_in[5] = (SACEFPDAWID[5] !== 1'bz) && SACEFPDAWID_delay[5]; // rv 0 + assign SACEFPDAWLEN_in[0] = (SACEFPDAWLEN[0] !== 1'bz) && SACEFPDAWLEN_delay[0]; // rv 0 + assign SACEFPDAWLEN_in[1] = (SACEFPDAWLEN[1] !== 1'bz) && SACEFPDAWLEN_delay[1]; // rv 0 + assign SACEFPDAWLEN_in[2] = (SACEFPDAWLEN[2] !== 1'bz) && SACEFPDAWLEN_delay[2]; // rv 0 + assign SACEFPDAWLEN_in[3] = (SACEFPDAWLEN[3] !== 1'bz) && SACEFPDAWLEN_delay[3]; // rv 0 + assign SACEFPDAWLEN_in[4] = (SACEFPDAWLEN[4] !== 1'bz) && SACEFPDAWLEN_delay[4]; // rv 0 + assign SACEFPDAWLEN_in[5] = (SACEFPDAWLEN[5] !== 1'bz) && SACEFPDAWLEN_delay[5]; // rv 0 + assign SACEFPDAWLEN_in[6] = (SACEFPDAWLEN[6] !== 1'bz) && SACEFPDAWLEN_delay[6]; // rv 0 + assign SACEFPDAWLEN_in[7] = (SACEFPDAWLEN[7] !== 1'bz) && SACEFPDAWLEN_delay[7]; // rv 0 + assign SACEFPDAWLOCK_in = (SACEFPDAWLOCK !== 1'bz) && SACEFPDAWLOCK_delay; // rv 0 + assign SACEFPDAWPROT_in[0] = (SACEFPDAWPROT[0] !== 1'bz) && SACEFPDAWPROT_delay[0]; // rv 0 + assign SACEFPDAWPROT_in[1] = (SACEFPDAWPROT[1] !== 1'bz) && SACEFPDAWPROT_delay[1]; // rv 0 + assign SACEFPDAWPROT_in[2] = (SACEFPDAWPROT[2] !== 1'bz) && SACEFPDAWPROT_delay[2]; // rv 0 + assign SACEFPDAWQOS_in[0] = (SACEFPDAWQOS[0] !== 1'bz) && SACEFPDAWQOS_delay[0]; // rv 0 + assign SACEFPDAWQOS_in[1] = (SACEFPDAWQOS[1] !== 1'bz) && SACEFPDAWQOS_delay[1]; // rv 0 + assign SACEFPDAWQOS_in[2] = (SACEFPDAWQOS[2] !== 1'bz) && SACEFPDAWQOS_delay[2]; // rv 0 + assign SACEFPDAWQOS_in[3] = (SACEFPDAWQOS[3] !== 1'bz) && SACEFPDAWQOS_delay[3]; // rv 0 + assign SACEFPDAWREGION_in[0] = (SACEFPDAWREGION[0] !== 1'bz) && SACEFPDAWREGION_delay[0]; // rv 0 + assign SACEFPDAWREGION_in[1] = (SACEFPDAWREGION[1] !== 1'bz) && SACEFPDAWREGION_delay[1]; // rv 0 + assign SACEFPDAWREGION_in[2] = (SACEFPDAWREGION[2] !== 1'bz) && SACEFPDAWREGION_delay[2]; // rv 0 + assign SACEFPDAWREGION_in[3] = (SACEFPDAWREGION[3] !== 1'bz) && SACEFPDAWREGION_delay[3]; // rv 0 + assign SACEFPDAWSIZE_in[0] = (SACEFPDAWSIZE[0] !== 1'bz) && SACEFPDAWSIZE_delay[0]; // rv 0 + assign SACEFPDAWSIZE_in[1] = (SACEFPDAWSIZE[1] !== 1'bz) && SACEFPDAWSIZE_delay[1]; // rv 0 + assign SACEFPDAWSIZE_in[2] = (SACEFPDAWSIZE[2] !== 1'bz) && SACEFPDAWSIZE_delay[2]; // rv 0 + assign SACEFPDAWSNOOP_in[0] = (SACEFPDAWSNOOP[0] !== 1'bz) && SACEFPDAWSNOOP_delay[0]; // rv 0 + assign SACEFPDAWSNOOP_in[1] = (SACEFPDAWSNOOP[1] !== 1'bz) && SACEFPDAWSNOOP_delay[1]; // rv 0 + assign SACEFPDAWSNOOP_in[2] = (SACEFPDAWSNOOP[2] !== 1'bz) && SACEFPDAWSNOOP_delay[2]; // rv 0 + assign SACEFPDAWUSER_in[0] = (SACEFPDAWUSER[0] !== 1'bz) && SACEFPDAWUSER_delay[0]; // rv 0 + assign SACEFPDAWUSER_in[10] = (SACEFPDAWUSER[10] !== 1'bz) && SACEFPDAWUSER_delay[10]; // rv 0 + assign SACEFPDAWUSER_in[11] = (SACEFPDAWUSER[11] !== 1'bz) && SACEFPDAWUSER_delay[11]; // rv 0 + assign SACEFPDAWUSER_in[12] = (SACEFPDAWUSER[12] !== 1'bz) && SACEFPDAWUSER_delay[12]; // rv 0 + assign SACEFPDAWUSER_in[13] = (SACEFPDAWUSER[13] !== 1'bz) && SACEFPDAWUSER_delay[13]; // rv 0 + assign SACEFPDAWUSER_in[14] = (SACEFPDAWUSER[14] !== 1'bz) && SACEFPDAWUSER_delay[14]; // rv 0 + assign SACEFPDAWUSER_in[15] = (SACEFPDAWUSER[15] !== 1'bz) && SACEFPDAWUSER_delay[15]; // rv 0 + assign SACEFPDAWUSER_in[1] = (SACEFPDAWUSER[1] !== 1'bz) && SACEFPDAWUSER_delay[1]; // rv 0 + assign SACEFPDAWUSER_in[2] = (SACEFPDAWUSER[2] !== 1'bz) && SACEFPDAWUSER_delay[2]; // rv 0 + assign SACEFPDAWUSER_in[3] = (SACEFPDAWUSER[3] !== 1'bz) && SACEFPDAWUSER_delay[3]; // rv 0 + assign SACEFPDAWUSER_in[4] = (SACEFPDAWUSER[4] !== 1'bz) && SACEFPDAWUSER_delay[4]; // rv 0 + assign SACEFPDAWUSER_in[5] = (SACEFPDAWUSER[5] !== 1'bz) && SACEFPDAWUSER_delay[5]; // rv 0 + assign SACEFPDAWUSER_in[6] = (SACEFPDAWUSER[6] !== 1'bz) && SACEFPDAWUSER_delay[6]; // rv 0 + assign SACEFPDAWUSER_in[7] = (SACEFPDAWUSER[7] !== 1'bz) && SACEFPDAWUSER_delay[7]; // rv 0 + assign SACEFPDAWUSER_in[8] = (SACEFPDAWUSER[8] !== 1'bz) && SACEFPDAWUSER_delay[8]; // rv 0 + assign SACEFPDAWUSER_in[9] = (SACEFPDAWUSER[9] !== 1'bz) && SACEFPDAWUSER_delay[9]; // rv 0 + assign SACEFPDAWVALID_in = (SACEFPDAWVALID !== 1'bz) && SACEFPDAWVALID_delay; // rv 0 + assign SACEFPDBREADY_in = (SACEFPDBREADY !== 1'bz) && SACEFPDBREADY_delay; // rv 0 + assign SACEFPDCDDATA_in[0] = (SACEFPDCDDATA[0] !== 1'bz) && SACEFPDCDDATA_delay[0]; // rv 0 + assign SACEFPDCDDATA_in[100] = (SACEFPDCDDATA[100] !== 1'bz) && SACEFPDCDDATA_delay[100]; // rv 0 + assign SACEFPDCDDATA_in[101] = (SACEFPDCDDATA[101] !== 1'bz) && SACEFPDCDDATA_delay[101]; // rv 0 + assign SACEFPDCDDATA_in[102] = (SACEFPDCDDATA[102] !== 1'bz) && SACEFPDCDDATA_delay[102]; // rv 0 + assign SACEFPDCDDATA_in[103] = (SACEFPDCDDATA[103] !== 1'bz) && SACEFPDCDDATA_delay[103]; // rv 0 + assign SACEFPDCDDATA_in[104] = (SACEFPDCDDATA[104] !== 1'bz) && SACEFPDCDDATA_delay[104]; // rv 0 + assign SACEFPDCDDATA_in[105] = (SACEFPDCDDATA[105] !== 1'bz) && SACEFPDCDDATA_delay[105]; // rv 0 + assign SACEFPDCDDATA_in[106] = (SACEFPDCDDATA[106] !== 1'bz) && SACEFPDCDDATA_delay[106]; // rv 0 + assign SACEFPDCDDATA_in[107] = (SACEFPDCDDATA[107] !== 1'bz) && SACEFPDCDDATA_delay[107]; // rv 0 + assign SACEFPDCDDATA_in[108] = (SACEFPDCDDATA[108] !== 1'bz) && SACEFPDCDDATA_delay[108]; // rv 0 + assign SACEFPDCDDATA_in[109] = (SACEFPDCDDATA[109] !== 1'bz) && SACEFPDCDDATA_delay[109]; // rv 0 + assign SACEFPDCDDATA_in[10] = (SACEFPDCDDATA[10] !== 1'bz) && SACEFPDCDDATA_delay[10]; // rv 0 + assign SACEFPDCDDATA_in[110] = (SACEFPDCDDATA[110] !== 1'bz) && SACEFPDCDDATA_delay[110]; // rv 0 + assign SACEFPDCDDATA_in[111] = (SACEFPDCDDATA[111] !== 1'bz) && SACEFPDCDDATA_delay[111]; // rv 0 + assign SACEFPDCDDATA_in[112] = (SACEFPDCDDATA[112] !== 1'bz) && SACEFPDCDDATA_delay[112]; // rv 0 + assign SACEFPDCDDATA_in[113] = (SACEFPDCDDATA[113] !== 1'bz) && SACEFPDCDDATA_delay[113]; // rv 0 + assign SACEFPDCDDATA_in[114] = (SACEFPDCDDATA[114] !== 1'bz) && SACEFPDCDDATA_delay[114]; // rv 0 + assign SACEFPDCDDATA_in[115] = (SACEFPDCDDATA[115] !== 1'bz) && SACEFPDCDDATA_delay[115]; // rv 0 + assign SACEFPDCDDATA_in[116] = (SACEFPDCDDATA[116] !== 1'bz) && SACEFPDCDDATA_delay[116]; // rv 0 + assign SACEFPDCDDATA_in[117] = (SACEFPDCDDATA[117] !== 1'bz) && SACEFPDCDDATA_delay[117]; // rv 0 + assign SACEFPDCDDATA_in[118] = (SACEFPDCDDATA[118] !== 1'bz) && SACEFPDCDDATA_delay[118]; // rv 0 + assign SACEFPDCDDATA_in[119] = (SACEFPDCDDATA[119] !== 1'bz) && SACEFPDCDDATA_delay[119]; // rv 0 + assign SACEFPDCDDATA_in[11] = (SACEFPDCDDATA[11] !== 1'bz) && SACEFPDCDDATA_delay[11]; // rv 0 + assign SACEFPDCDDATA_in[120] = (SACEFPDCDDATA[120] !== 1'bz) && SACEFPDCDDATA_delay[120]; // rv 0 + assign SACEFPDCDDATA_in[121] = (SACEFPDCDDATA[121] !== 1'bz) && SACEFPDCDDATA_delay[121]; // rv 0 + assign SACEFPDCDDATA_in[122] = (SACEFPDCDDATA[122] !== 1'bz) && SACEFPDCDDATA_delay[122]; // rv 0 + assign SACEFPDCDDATA_in[123] = (SACEFPDCDDATA[123] !== 1'bz) && SACEFPDCDDATA_delay[123]; // rv 0 + assign SACEFPDCDDATA_in[124] = (SACEFPDCDDATA[124] !== 1'bz) && SACEFPDCDDATA_delay[124]; // rv 0 + assign SACEFPDCDDATA_in[125] = (SACEFPDCDDATA[125] !== 1'bz) && SACEFPDCDDATA_delay[125]; // rv 0 + assign SACEFPDCDDATA_in[126] = (SACEFPDCDDATA[126] !== 1'bz) && SACEFPDCDDATA_delay[126]; // rv 0 + assign SACEFPDCDDATA_in[127] = (SACEFPDCDDATA[127] !== 1'bz) && SACEFPDCDDATA_delay[127]; // rv 0 + assign SACEFPDCDDATA_in[12] = (SACEFPDCDDATA[12] !== 1'bz) && SACEFPDCDDATA_delay[12]; // rv 0 + assign SACEFPDCDDATA_in[13] = (SACEFPDCDDATA[13] !== 1'bz) && SACEFPDCDDATA_delay[13]; // rv 0 + assign SACEFPDCDDATA_in[14] = (SACEFPDCDDATA[14] !== 1'bz) && SACEFPDCDDATA_delay[14]; // rv 0 + assign SACEFPDCDDATA_in[15] = (SACEFPDCDDATA[15] !== 1'bz) && SACEFPDCDDATA_delay[15]; // rv 0 + assign SACEFPDCDDATA_in[16] = (SACEFPDCDDATA[16] !== 1'bz) && SACEFPDCDDATA_delay[16]; // rv 0 + assign SACEFPDCDDATA_in[17] = (SACEFPDCDDATA[17] !== 1'bz) && SACEFPDCDDATA_delay[17]; // rv 0 + assign SACEFPDCDDATA_in[18] = (SACEFPDCDDATA[18] !== 1'bz) && SACEFPDCDDATA_delay[18]; // rv 0 + assign SACEFPDCDDATA_in[19] = (SACEFPDCDDATA[19] !== 1'bz) && SACEFPDCDDATA_delay[19]; // rv 0 + assign SACEFPDCDDATA_in[1] = (SACEFPDCDDATA[1] !== 1'bz) && SACEFPDCDDATA_delay[1]; // rv 0 + assign SACEFPDCDDATA_in[20] = (SACEFPDCDDATA[20] !== 1'bz) && SACEFPDCDDATA_delay[20]; // rv 0 + assign SACEFPDCDDATA_in[21] = (SACEFPDCDDATA[21] !== 1'bz) && SACEFPDCDDATA_delay[21]; // rv 0 + assign SACEFPDCDDATA_in[22] = (SACEFPDCDDATA[22] !== 1'bz) && SACEFPDCDDATA_delay[22]; // rv 0 + assign SACEFPDCDDATA_in[23] = (SACEFPDCDDATA[23] !== 1'bz) && SACEFPDCDDATA_delay[23]; // rv 0 + assign SACEFPDCDDATA_in[24] = (SACEFPDCDDATA[24] !== 1'bz) && SACEFPDCDDATA_delay[24]; // rv 0 + assign SACEFPDCDDATA_in[25] = (SACEFPDCDDATA[25] !== 1'bz) && SACEFPDCDDATA_delay[25]; // rv 0 + assign SACEFPDCDDATA_in[26] = (SACEFPDCDDATA[26] !== 1'bz) && SACEFPDCDDATA_delay[26]; // rv 0 + assign SACEFPDCDDATA_in[27] = (SACEFPDCDDATA[27] !== 1'bz) && SACEFPDCDDATA_delay[27]; // rv 0 + assign SACEFPDCDDATA_in[28] = (SACEFPDCDDATA[28] !== 1'bz) && SACEFPDCDDATA_delay[28]; // rv 0 + assign SACEFPDCDDATA_in[29] = (SACEFPDCDDATA[29] !== 1'bz) && SACEFPDCDDATA_delay[29]; // rv 0 + assign SACEFPDCDDATA_in[2] = (SACEFPDCDDATA[2] !== 1'bz) && SACEFPDCDDATA_delay[2]; // rv 0 + assign SACEFPDCDDATA_in[30] = (SACEFPDCDDATA[30] !== 1'bz) && SACEFPDCDDATA_delay[30]; // rv 0 + assign SACEFPDCDDATA_in[31] = (SACEFPDCDDATA[31] !== 1'bz) && SACEFPDCDDATA_delay[31]; // rv 0 + assign SACEFPDCDDATA_in[32] = (SACEFPDCDDATA[32] !== 1'bz) && SACEFPDCDDATA_delay[32]; // rv 0 + assign SACEFPDCDDATA_in[33] = (SACEFPDCDDATA[33] !== 1'bz) && SACEFPDCDDATA_delay[33]; // rv 0 + assign SACEFPDCDDATA_in[34] = (SACEFPDCDDATA[34] !== 1'bz) && SACEFPDCDDATA_delay[34]; // rv 0 + assign SACEFPDCDDATA_in[35] = (SACEFPDCDDATA[35] !== 1'bz) && SACEFPDCDDATA_delay[35]; // rv 0 + assign SACEFPDCDDATA_in[36] = (SACEFPDCDDATA[36] !== 1'bz) && SACEFPDCDDATA_delay[36]; // rv 0 + assign SACEFPDCDDATA_in[37] = (SACEFPDCDDATA[37] !== 1'bz) && SACEFPDCDDATA_delay[37]; // rv 0 + assign SACEFPDCDDATA_in[38] = (SACEFPDCDDATA[38] !== 1'bz) && SACEFPDCDDATA_delay[38]; // rv 0 + assign SACEFPDCDDATA_in[39] = (SACEFPDCDDATA[39] !== 1'bz) && SACEFPDCDDATA_delay[39]; // rv 0 + assign SACEFPDCDDATA_in[3] = (SACEFPDCDDATA[3] !== 1'bz) && SACEFPDCDDATA_delay[3]; // rv 0 + assign SACEFPDCDDATA_in[40] = (SACEFPDCDDATA[40] !== 1'bz) && SACEFPDCDDATA_delay[40]; // rv 0 + assign SACEFPDCDDATA_in[41] = (SACEFPDCDDATA[41] !== 1'bz) && SACEFPDCDDATA_delay[41]; // rv 0 + assign SACEFPDCDDATA_in[42] = (SACEFPDCDDATA[42] !== 1'bz) && SACEFPDCDDATA_delay[42]; // rv 0 + assign SACEFPDCDDATA_in[43] = (SACEFPDCDDATA[43] !== 1'bz) && SACEFPDCDDATA_delay[43]; // rv 0 + assign SACEFPDCDDATA_in[44] = (SACEFPDCDDATA[44] !== 1'bz) && SACEFPDCDDATA_delay[44]; // rv 0 + assign SACEFPDCDDATA_in[45] = (SACEFPDCDDATA[45] !== 1'bz) && SACEFPDCDDATA_delay[45]; // rv 0 + assign SACEFPDCDDATA_in[46] = (SACEFPDCDDATA[46] !== 1'bz) && SACEFPDCDDATA_delay[46]; // rv 0 + assign SACEFPDCDDATA_in[47] = (SACEFPDCDDATA[47] !== 1'bz) && SACEFPDCDDATA_delay[47]; // rv 0 + assign SACEFPDCDDATA_in[48] = (SACEFPDCDDATA[48] !== 1'bz) && SACEFPDCDDATA_delay[48]; // rv 0 + assign SACEFPDCDDATA_in[49] = (SACEFPDCDDATA[49] !== 1'bz) && SACEFPDCDDATA_delay[49]; // rv 0 + assign SACEFPDCDDATA_in[4] = (SACEFPDCDDATA[4] !== 1'bz) && SACEFPDCDDATA_delay[4]; // rv 0 + assign SACEFPDCDDATA_in[50] = (SACEFPDCDDATA[50] !== 1'bz) && SACEFPDCDDATA_delay[50]; // rv 0 + assign SACEFPDCDDATA_in[51] = (SACEFPDCDDATA[51] !== 1'bz) && SACEFPDCDDATA_delay[51]; // rv 0 + assign SACEFPDCDDATA_in[52] = (SACEFPDCDDATA[52] !== 1'bz) && SACEFPDCDDATA_delay[52]; // rv 0 + assign SACEFPDCDDATA_in[53] = (SACEFPDCDDATA[53] !== 1'bz) && SACEFPDCDDATA_delay[53]; // rv 0 + assign SACEFPDCDDATA_in[54] = (SACEFPDCDDATA[54] !== 1'bz) && SACEFPDCDDATA_delay[54]; // rv 0 + assign SACEFPDCDDATA_in[55] = (SACEFPDCDDATA[55] !== 1'bz) && SACEFPDCDDATA_delay[55]; // rv 0 + assign SACEFPDCDDATA_in[56] = (SACEFPDCDDATA[56] !== 1'bz) && SACEFPDCDDATA_delay[56]; // rv 0 + assign SACEFPDCDDATA_in[57] = (SACEFPDCDDATA[57] !== 1'bz) && SACEFPDCDDATA_delay[57]; // rv 0 + assign SACEFPDCDDATA_in[58] = (SACEFPDCDDATA[58] !== 1'bz) && SACEFPDCDDATA_delay[58]; // rv 0 + assign SACEFPDCDDATA_in[59] = (SACEFPDCDDATA[59] !== 1'bz) && SACEFPDCDDATA_delay[59]; // rv 0 + assign SACEFPDCDDATA_in[5] = (SACEFPDCDDATA[5] !== 1'bz) && SACEFPDCDDATA_delay[5]; // rv 0 + assign SACEFPDCDDATA_in[60] = (SACEFPDCDDATA[60] !== 1'bz) && SACEFPDCDDATA_delay[60]; // rv 0 + assign SACEFPDCDDATA_in[61] = (SACEFPDCDDATA[61] !== 1'bz) && SACEFPDCDDATA_delay[61]; // rv 0 + assign SACEFPDCDDATA_in[62] = (SACEFPDCDDATA[62] !== 1'bz) && SACEFPDCDDATA_delay[62]; // rv 0 + assign SACEFPDCDDATA_in[63] = (SACEFPDCDDATA[63] !== 1'bz) && SACEFPDCDDATA_delay[63]; // rv 0 + assign SACEFPDCDDATA_in[64] = (SACEFPDCDDATA[64] !== 1'bz) && SACEFPDCDDATA_delay[64]; // rv 0 + assign SACEFPDCDDATA_in[65] = (SACEFPDCDDATA[65] !== 1'bz) && SACEFPDCDDATA_delay[65]; // rv 0 + assign SACEFPDCDDATA_in[66] = (SACEFPDCDDATA[66] !== 1'bz) && SACEFPDCDDATA_delay[66]; // rv 0 + assign SACEFPDCDDATA_in[67] = (SACEFPDCDDATA[67] !== 1'bz) && SACEFPDCDDATA_delay[67]; // rv 0 + assign SACEFPDCDDATA_in[68] = (SACEFPDCDDATA[68] !== 1'bz) && SACEFPDCDDATA_delay[68]; // rv 0 + assign SACEFPDCDDATA_in[69] = (SACEFPDCDDATA[69] !== 1'bz) && SACEFPDCDDATA_delay[69]; // rv 0 + assign SACEFPDCDDATA_in[6] = (SACEFPDCDDATA[6] !== 1'bz) && SACEFPDCDDATA_delay[6]; // rv 0 + assign SACEFPDCDDATA_in[70] = (SACEFPDCDDATA[70] !== 1'bz) && SACEFPDCDDATA_delay[70]; // rv 0 + assign SACEFPDCDDATA_in[71] = (SACEFPDCDDATA[71] !== 1'bz) && SACEFPDCDDATA_delay[71]; // rv 0 + assign SACEFPDCDDATA_in[72] = (SACEFPDCDDATA[72] !== 1'bz) && SACEFPDCDDATA_delay[72]; // rv 0 + assign SACEFPDCDDATA_in[73] = (SACEFPDCDDATA[73] !== 1'bz) && SACEFPDCDDATA_delay[73]; // rv 0 + assign SACEFPDCDDATA_in[74] = (SACEFPDCDDATA[74] !== 1'bz) && SACEFPDCDDATA_delay[74]; // rv 0 + assign SACEFPDCDDATA_in[75] = (SACEFPDCDDATA[75] !== 1'bz) && SACEFPDCDDATA_delay[75]; // rv 0 + assign SACEFPDCDDATA_in[76] = (SACEFPDCDDATA[76] !== 1'bz) && SACEFPDCDDATA_delay[76]; // rv 0 + assign SACEFPDCDDATA_in[77] = (SACEFPDCDDATA[77] !== 1'bz) && SACEFPDCDDATA_delay[77]; // rv 0 + assign SACEFPDCDDATA_in[78] = (SACEFPDCDDATA[78] !== 1'bz) && SACEFPDCDDATA_delay[78]; // rv 0 + assign SACEFPDCDDATA_in[79] = (SACEFPDCDDATA[79] !== 1'bz) && SACEFPDCDDATA_delay[79]; // rv 0 + assign SACEFPDCDDATA_in[7] = (SACEFPDCDDATA[7] !== 1'bz) && SACEFPDCDDATA_delay[7]; // rv 0 + assign SACEFPDCDDATA_in[80] = (SACEFPDCDDATA[80] !== 1'bz) && SACEFPDCDDATA_delay[80]; // rv 0 + assign SACEFPDCDDATA_in[81] = (SACEFPDCDDATA[81] !== 1'bz) && SACEFPDCDDATA_delay[81]; // rv 0 + assign SACEFPDCDDATA_in[82] = (SACEFPDCDDATA[82] !== 1'bz) && SACEFPDCDDATA_delay[82]; // rv 0 + assign SACEFPDCDDATA_in[83] = (SACEFPDCDDATA[83] !== 1'bz) && SACEFPDCDDATA_delay[83]; // rv 0 + assign SACEFPDCDDATA_in[84] = (SACEFPDCDDATA[84] !== 1'bz) && SACEFPDCDDATA_delay[84]; // rv 0 + assign SACEFPDCDDATA_in[85] = (SACEFPDCDDATA[85] !== 1'bz) && SACEFPDCDDATA_delay[85]; // rv 0 + assign SACEFPDCDDATA_in[86] = (SACEFPDCDDATA[86] !== 1'bz) && SACEFPDCDDATA_delay[86]; // rv 0 + assign SACEFPDCDDATA_in[87] = (SACEFPDCDDATA[87] !== 1'bz) && SACEFPDCDDATA_delay[87]; // rv 0 + assign SACEFPDCDDATA_in[88] = (SACEFPDCDDATA[88] !== 1'bz) && SACEFPDCDDATA_delay[88]; // rv 0 + assign SACEFPDCDDATA_in[89] = (SACEFPDCDDATA[89] !== 1'bz) && SACEFPDCDDATA_delay[89]; // rv 0 + assign SACEFPDCDDATA_in[8] = (SACEFPDCDDATA[8] !== 1'bz) && SACEFPDCDDATA_delay[8]; // rv 0 + assign SACEFPDCDDATA_in[90] = (SACEFPDCDDATA[90] !== 1'bz) && SACEFPDCDDATA_delay[90]; // rv 0 + assign SACEFPDCDDATA_in[91] = (SACEFPDCDDATA[91] !== 1'bz) && SACEFPDCDDATA_delay[91]; // rv 0 + assign SACEFPDCDDATA_in[92] = (SACEFPDCDDATA[92] !== 1'bz) && SACEFPDCDDATA_delay[92]; // rv 0 + assign SACEFPDCDDATA_in[93] = (SACEFPDCDDATA[93] !== 1'bz) && SACEFPDCDDATA_delay[93]; // rv 0 + assign SACEFPDCDDATA_in[94] = (SACEFPDCDDATA[94] !== 1'bz) && SACEFPDCDDATA_delay[94]; // rv 0 + assign SACEFPDCDDATA_in[95] = (SACEFPDCDDATA[95] !== 1'bz) && SACEFPDCDDATA_delay[95]; // rv 0 + assign SACEFPDCDDATA_in[96] = (SACEFPDCDDATA[96] !== 1'bz) && SACEFPDCDDATA_delay[96]; // rv 0 + assign SACEFPDCDDATA_in[97] = (SACEFPDCDDATA[97] !== 1'bz) && SACEFPDCDDATA_delay[97]; // rv 0 + assign SACEFPDCDDATA_in[98] = (SACEFPDCDDATA[98] !== 1'bz) && SACEFPDCDDATA_delay[98]; // rv 0 + assign SACEFPDCDDATA_in[99] = (SACEFPDCDDATA[99] !== 1'bz) && SACEFPDCDDATA_delay[99]; // rv 0 + assign SACEFPDCDDATA_in[9] = (SACEFPDCDDATA[9] !== 1'bz) && SACEFPDCDDATA_delay[9]; // rv 0 + assign SACEFPDCDLAST_in = (SACEFPDCDLAST !== 1'bz) && SACEFPDCDLAST_delay; // rv 0 + assign SACEFPDCDVALID_in = (SACEFPDCDVALID !== 1'bz) && SACEFPDCDVALID_delay; // rv 0 + assign SACEFPDCRRESP_in[0] = (SACEFPDCRRESP[0] !== 1'bz) && SACEFPDCRRESP_delay[0]; // rv 0 + assign SACEFPDCRRESP_in[1] = (SACEFPDCRRESP[1] !== 1'bz) && SACEFPDCRRESP_delay[1]; // rv 0 + assign SACEFPDCRRESP_in[2] = (SACEFPDCRRESP[2] !== 1'bz) && SACEFPDCRRESP_delay[2]; // rv 0 + assign SACEFPDCRRESP_in[3] = (SACEFPDCRRESP[3] !== 1'bz) && SACEFPDCRRESP_delay[3]; // rv 0 + assign SACEFPDCRRESP_in[4] = (SACEFPDCRRESP[4] !== 1'bz) && SACEFPDCRRESP_delay[4]; // rv 0 + assign SACEFPDCRVALID_in = (SACEFPDCRVALID !== 1'bz) && SACEFPDCRVALID_delay; // rv 0 + assign SACEFPDRACK_in = (SACEFPDRACK !== 1'bz) && SACEFPDRACK_delay; // rv 0 + assign SACEFPDRREADY_in = (SACEFPDRREADY !== 1'bz) && SACEFPDRREADY_delay; // rv 0 + assign SACEFPDWACK_in = (SACEFPDWACK !== 1'bz) && SACEFPDWACK_delay; // rv 0 + assign SACEFPDWDATA_in[0] = (SACEFPDWDATA[0] !== 1'bz) && SACEFPDWDATA_delay[0]; // rv 0 + assign SACEFPDWDATA_in[100] = (SACEFPDWDATA[100] !== 1'bz) && SACEFPDWDATA_delay[100]; // rv 0 + assign SACEFPDWDATA_in[101] = (SACEFPDWDATA[101] !== 1'bz) && SACEFPDWDATA_delay[101]; // rv 0 + assign SACEFPDWDATA_in[102] = (SACEFPDWDATA[102] !== 1'bz) && SACEFPDWDATA_delay[102]; // rv 0 + assign SACEFPDWDATA_in[103] = (SACEFPDWDATA[103] !== 1'bz) && SACEFPDWDATA_delay[103]; // rv 0 + assign SACEFPDWDATA_in[104] = (SACEFPDWDATA[104] !== 1'bz) && SACEFPDWDATA_delay[104]; // rv 0 + assign SACEFPDWDATA_in[105] = (SACEFPDWDATA[105] !== 1'bz) && SACEFPDWDATA_delay[105]; // rv 0 + assign SACEFPDWDATA_in[106] = (SACEFPDWDATA[106] !== 1'bz) && SACEFPDWDATA_delay[106]; // rv 0 + assign SACEFPDWDATA_in[107] = (SACEFPDWDATA[107] !== 1'bz) && SACEFPDWDATA_delay[107]; // rv 0 + assign SACEFPDWDATA_in[108] = (SACEFPDWDATA[108] !== 1'bz) && SACEFPDWDATA_delay[108]; // rv 0 + assign SACEFPDWDATA_in[109] = (SACEFPDWDATA[109] !== 1'bz) && SACEFPDWDATA_delay[109]; // rv 0 + assign SACEFPDWDATA_in[10] = (SACEFPDWDATA[10] !== 1'bz) && SACEFPDWDATA_delay[10]; // rv 0 + assign SACEFPDWDATA_in[110] = (SACEFPDWDATA[110] !== 1'bz) && SACEFPDWDATA_delay[110]; // rv 0 + assign SACEFPDWDATA_in[111] = (SACEFPDWDATA[111] !== 1'bz) && SACEFPDWDATA_delay[111]; // rv 0 + assign SACEFPDWDATA_in[112] = (SACEFPDWDATA[112] !== 1'bz) && SACEFPDWDATA_delay[112]; // rv 0 + assign SACEFPDWDATA_in[113] = (SACEFPDWDATA[113] !== 1'bz) && SACEFPDWDATA_delay[113]; // rv 0 + assign SACEFPDWDATA_in[114] = (SACEFPDWDATA[114] !== 1'bz) && SACEFPDWDATA_delay[114]; // rv 0 + assign SACEFPDWDATA_in[115] = (SACEFPDWDATA[115] !== 1'bz) && SACEFPDWDATA_delay[115]; // rv 0 + assign SACEFPDWDATA_in[116] = (SACEFPDWDATA[116] !== 1'bz) && SACEFPDWDATA_delay[116]; // rv 0 + assign SACEFPDWDATA_in[117] = (SACEFPDWDATA[117] !== 1'bz) && SACEFPDWDATA_delay[117]; // rv 0 + assign SACEFPDWDATA_in[118] = (SACEFPDWDATA[118] !== 1'bz) && SACEFPDWDATA_delay[118]; // rv 0 + assign SACEFPDWDATA_in[119] = (SACEFPDWDATA[119] !== 1'bz) && SACEFPDWDATA_delay[119]; // rv 0 + assign SACEFPDWDATA_in[11] = (SACEFPDWDATA[11] !== 1'bz) && SACEFPDWDATA_delay[11]; // rv 0 + assign SACEFPDWDATA_in[120] = (SACEFPDWDATA[120] !== 1'bz) && SACEFPDWDATA_delay[120]; // rv 0 + assign SACEFPDWDATA_in[121] = (SACEFPDWDATA[121] !== 1'bz) && SACEFPDWDATA_delay[121]; // rv 0 + assign SACEFPDWDATA_in[122] = (SACEFPDWDATA[122] !== 1'bz) && SACEFPDWDATA_delay[122]; // rv 0 + assign SACEFPDWDATA_in[123] = (SACEFPDWDATA[123] !== 1'bz) && SACEFPDWDATA_delay[123]; // rv 0 + assign SACEFPDWDATA_in[124] = (SACEFPDWDATA[124] !== 1'bz) && SACEFPDWDATA_delay[124]; // rv 0 + assign SACEFPDWDATA_in[125] = (SACEFPDWDATA[125] !== 1'bz) && SACEFPDWDATA_delay[125]; // rv 0 + assign SACEFPDWDATA_in[126] = (SACEFPDWDATA[126] !== 1'bz) && SACEFPDWDATA_delay[126]; // rv 0 + assign SACEFPDWDATA_in[127] = (SACEFPDWDATA[127] !== 1'bz) && SACEFPDWDATA_delay[127]; // rv 0 + assign SACEFPDWDATA_in[12] = (SACEFPDWDATA[12] !== 1'bz) && SACEFPDWDATA_delay[12]; // rv 0 + assign SACEFPDWDATA_in[13] = (SACEFPDWDATA[13] !== 1'bz) && SACEFPDWDATA_delay[13]; // rv 0 + assign SACEFPDWDATA_in[14] = (SACEFPDWDATA[14] !== 1'bz) && SACEFPDWDATA_delay[14]; // rv 0 + assign SACEFPDWDATA_in[15] = (SACEFPDWDATA[15] !== 1'bz) && SACEFPDWDATA_delay[15]; // rv 0 + assign SACEFPDWDATA_in[16] = (SACEFPDWDATA[16] !== 1'bz) && SACEFPDWDATA_delay[16]; // rv 0 + assign SACEFPDWDATA_in[17] = (SACEFPDWDATA[17] !== 1'bz) && SACEFPDWDATA_delay[17]; // rv 0 + assign SACEFPDWDATA_in[18] = (SACEFPDWDATA[18] !== 1'bz) && SACEFPDWDATA_delay[18]; // rv 0 + assign SACEFPDWDATA_in[19] = (SACEFPDWDATA[19] !== 1'bz) && SACEFPDWDATA_delay[19]; // rv 0 + assign SACEFPDWDATA_in[1] = (SACEFPDWDATA[1] !== 1'bz) && SACEFPDWDATA_delay[1]; // rv 0 + assign SACEFPDWDATA_in[20] = (SACEFPDWDATA[20] !== 1'bz) && SACEFPDWDATA_delay[20]; // rv 0 + assign SACEFPDWDATA_in[21] = (SACEFPDWDATA[21] !== 1'bz) && SACEFPDWDATA_delay[21]; // rv 0 + assign SACEFPDWDATA_in[22] = (SACEFPDWDATA[22] !== 1'bz) && SACEFPDWDATA_delay[22]; // rv 0 + assign SACEFPDWDATA_in[23] = (SACEFPDWDATA[23] !== 1'bz) && SACEFPDWDATA_delay[23]; // rv 0 + assign SACEFPDWDATA_in[24] = (SACEFPDWDATA[24] !== 1'bz) && SACEFPDWDATA_delay[24]; // rv 0 + assign SACEFPDWDATA_in[25] = (SACEFPDWDATA[25] !== 1'bz) && SACEFPDWDATA_delay[25]; // rv 0 + assign SACEFPDWDATA_in[26] = (SACEFPDWDATA[26] !== 1'bz) && SACEFPDWDATA_delay[26]; // rv 0 + assign SACEFPDWDATA_in[27] = (SACEFPDWDATA[27] !== 1'bz) && SACEFPDWDATA_delay[27]; // rv 0 + assign SACEFPDWDATA_in[28] = (SACEFPDWDATA[28] !== 1'bz) && SACEFPDWDATA_delay[28]; // rv 0 + assign SACEFPDWDATA_in[29] = (SACEFPDWDATA[29] !== 1'bz) && SACEFPDWDATA_delay[29]; // rv 0 + assign SACEFPDWDATA_in[2] = (SACEFPDWDATA[2] !== 1'bz) && SACEFPDWDATA_delay[2]; // rv 0 + assign SACEFPDWDATA_in[30] = (SACEFPDWDATA[30] !== 1'bz) && SACEFPDWDATA_delay[30]; // rv 0 + assign SACEFPDWDATA_in[31] = (SACEFPDWDATA[31] !== 1'bz) && SACEFPDWDATA_delay[31]; // rv 0 + assign SACEFPDWDATA_in[32] = (SACEFPDWDATA[32] !== 1'bz) && SACEFPDWDATA_delay[32]; // rv 0 + assign SACEFPDWDATA_in[33] = (SACEFPDWDATA[33] !== 1'bz) && SACEFPDWDATA_delay[33]; // rv 0 + assign SACEFPDWDATA_in[34] = (SACEFPDWDATA[34] !== 1'bz) && SACEFPDWDATA_delay[34]; // rv 0 + assign SACEFPDWDATA_in[35] = (SACEFPDWDATA[35] !== 1'bz) && SACEFPDWDATA_delay[35]; // rv 0 + assign SACEFPDWDATA_in[36] = (SACEFPDWDATA[36] !== 1'bz) && SACEFPDWDATA_delay[36]; // rv 0 + assign SACEFPDWDATA_in[37] = (SACEFPDWDATA[37] !== 1'bz) && SACEFPDWDATA_delay[37]; // rv 0 + assign SACEFPDWDATA_in[38] = (SACEFPDWDATA[38] !== 1'bz) && SACEFPDWDATA_delay[38]; // rv 0 + assign SACEFPDWDATA_in[39] = (SACEFPDWDATA[39] !== 1'bz) && SACEFPDWDATA_delay[39]; // rv 0 + assign SACEFPDWDATA_in[3] = (SACEFPDWDATA[3] !== 1'bz) && SACEFPDWDATA_delay[3]; // rv 0 + assign SACEFPDWDATA_in[40] = (SACEFPDWDATA[40] !== 1'bz) && SACEFPDWDATA_delay[40]; // rv 0 + assign SACEFPDWDATA_in[41] = (SACEFPDWDATA[41] !== 1'bz) && SACEFPDWDATA_delay[41]; // rv 0 + assign SACEFPDWDATA_in[42] = (SACEFPDWDATA[42] !== 1'bz) && SACEFPDWDATA_delay[42]; // rv 0 + assign SACEFPDWDATA_in[43] = (SACEFPDWDATA[43] !== 1'bz) && SACEFPDWDATA_delay[43]; // rv 0 + assign SACEFPDWDATA_in[44] = (SACEFPDWDATA[44] !== 1'bz) && SACEFPDWDATA_delay[44]; // rv 0 + assign SACEFPDWDATA_in[45] = (SACEFPDWDATA[45] !== 1'bz) && SACEFPDWDATA_delay[45]; // rv 0 + assign SACEFPDWDATA_in[46] = (SACEFPDWDATA[46] !== 1'bz) && SACEFPDWDATA_delay[46]; // rv 0 + assign SACEFPDWDATA_in[47] = (SACEFPDWDATA[47] !== 1'bz) && SACEFPDWDATA_delay[47]; // rv 0 + assign SACEFPDWDATA_in[48] = (SACEFPDWDATA[48] !== 1'bz) && SACEFPDWDATA_delay[48]; // rv 0 + assign SACEFPDWDATA_in[49] = (SACEFPDWDATA[49] !== 1'bz) && SACEFPDWDATA_delay[49]; // rv 0 + assign SACEFPDWDATA_in[4] = (SACEFPDWDATA[4] !== 1'bz) && SACEFPDWDATA_delay[4]; // rv 0 + assign SACEFPDWDATA_in[50] = (SACEFPDWDATA[50] !== 1'bz) && SACEFPDWDATA_delay[50]; // rv 0 + assign SACEFPDWDATA_in[51] = (SACEFPDWDATA[51] !== 1'bz) && SACEFPDWDATA_delay[51]; // rv 0 + assign SACEFPDWDATA_in[52] = (SACEFPDWDATA[52] !== 1'bz) && SACEFPDWDATA_delay[52]; // rv 0 + assign SACEFPDWDATA_in[53] = (SACEFPDWDATA[53] !== 1'bz) && SACEFPDWDATA_delay[53]; // rv 0 + assign SACEFPDWDATA_in[54] = (SACEFPDWDATA[54] !== 1'bz) && SACEFPDWDATA_delay[54]; // rv 0 + assign SACEFPDWDATA_in[55] = (SACEFPDWDATA[55] !== 1'bz) && SACEFPDWDATA_delay[55]; // rv 0 + assign SACEFPDWDATA_in[56] = (SACEFPDWDATA[56] !== 1'bz) && SACEFPDWDATA_delay[56]; // rv 0 + assign SACEFPDWDATA_in[57] = (SACEFPDWDATA[57] !== 1'bz) && SACEFPDWDATA_delay[57]; // rv 0 + assign SACEFPDWDATA_in[58] = (SACEFPDWDATA[58] !== 1'bz) && SACEFPDWDATA_delay[58]; // rv 0 + assign SACEFPDWDATA_in[59] = (SACEFPDWDATA[59] !== 1'bz) && SACEFPDWDATA_delay[59]; // rv 0 + assign SACEFPDWDATA_in[5] = (SACEFPDWDATA[5] !== 1'bz) && SACEFPDWDATA_delay[5]; // rv 0 + assign SACEFPDWDATA_in[60] = (SACEFPDWDATA[60] !== 1'bz) && SACEFPDWDATA_delay[60]; // rv 0 + assign SACEFPDWDATA_in[61] = (SACEFPDWDATA[61] !== 1'bz) && SACEFPDWDATA_delay[61]; // rv 0 + assign SACEFPDWDATA_in[62] = (SACEFPDWDATA[62] !== 1'bz) && SACEFPDWDATA_delay[62]; // rv 0 + assign SACEFPDWDATA_in[63] = (SACEFPDWDATA[63] !== 1'bz) && SACEFPDWDATA_delay[63]; // rv 0 + assign SACEFPDWDATA_in[64] = (SACEFPDWDATA[64] !== 1'bz) && SACEFPDWDATA_delay[64]; // rv 0 + assign SACEFPDWDATA_in[65] = (SACEFPDWDATA[65] !== 1'bz) && SACEFPDWDATA_delay[65]; // rv 0 + assign SACEFPDWDATA_in[66] = (SACEFPDWDATA[66] !== 1'bz) && SACEFPDWDATA_delay[66]; // rv 0 + assign SACEFPDWDATA_in[67] = (SACEFPDWDATA[67] !== 1'bz) && SACEFPDWDATA_delay[67]; // rv 0 + assign SACEFPDWDATA_in[68] = (SACEFPDWDATA[68] !== 1'bz) && SACEFPDWDATA_delay[68]; // rv 0 + assign SACEFPDWDATA_in[69] = (SACEFPDWDATA[69] !== 1'bz) && SACEFPDWDATA_delay[69]; // rv 0 + assign SACEFPDWDATA_in[6] = (SACEFPDWDATA[6] !== 1'bz) && SACEFPDWDATA_delay[6]; // rv 0 + assign SACEFPDWDATA_in[70] = (SACEFPDWDATA[70] !== 1'bz) && SACEFPDWDATA_delay[70]; // rv 0 + assign SACEFPDWDATA_in[71] = (SACEFPDWDATA[71] !== 1'bz) && SACEFPDWDATA_delay[71]; // rv 0 + assign SACEFPDWDATA_in[72] = (SACEFPDWDATA[72] !== 1'bz) && SACEFPDWDATA_delay[72]; // rv 0 + assign SACEFPDWDATA_in[73] = (SACEFPDWDATA[73] !== 1'bz) && SACEFPDWDATA_delay[73]; // rv 0 + assign SACEFPDWDATA_in[74] = (SACEFPDWDATA[74] !== 1'bz) && SACEFPDWDATA_delay[74]; // rv 0 + assign SACEFPDWDATA_in[75] = (SACEFPDWDATA[75] !== 1'bz) && SACEFPDWDATA_delay[75]; // rv 0 + assign SACEFPDWDATA_in[76] = (SACEFPDWDATA[76] !== 1'bz) && SACEFPDWDATA_delay[76]; // rv 0 + assign SACEFPDWDATA_in[77] = (SACEFPDWDATA[77] !== 1'bz) && SACEFPDWDATA_delay[77]; // rv 0 + assign SACEFPDWDATA_in[78] = (SACEFPDWDATA[78] !== 1'bz) && SACEFPDWDATA_delay[78]; // rv 0 + assign SACEFPDWDATA_in[79] = (SACEFPDWDATA[79] !== 1'bz) && SACEFPDWDATA_delay[79]; // rv 0 + assign SACEFPDWDATA_in[7] = (SACEFPDWDATA[7] !== 1'bz) && SACEFPDWDATA_delay[7]; // rv 0 + assign SACEFPDWDATA_in[80] = (SACEFPDWDATA[80] !== 1'bz) && SACEFPDWDATA_delay[80]; // rv 0 + assign SACEFPDWDATA_in[81] = (SACEFPDWDATA[81] !== 1'bz) && SACEFPDWDATA_delay[81]; // rv 0 + assign SACEFPDWDATA_in[82] = (SACEFPDWDATA[82] !== 1'bz) && SACEFPDWDATA_delay[82]; // rv 0 + assign SACEFPDWDATA_in[83] = (SACEFPDWDATA[83] !== 1'bz) && SACEFPDWDATA_delay[83]; // rv 0 + assign SACEFPDWDATA_in[84] = (SACEFPDWDATA[84] !== 1'bz) && SACEFPDWDATA_delay[84]; // rv 0 + assign SACEFPDWDATA_in[85] = (SACEFPDWDATA[85] !== 1'bz) && SACEFPDWDATA_delay[85]; // rv 0 + assign SACEFPDWDATA_in[86] = (SACEFPDWDATA[86] !== 1'bz) && SACEFPDWDATA_delay[86]; // rv 0 + assign SACEFPDWDATA_in[87] = (SACEFPDWDATA[87] !== 1'bz) && SACEFPDWDATA_delay[87]; // rv 0 + assign SACEFPDWDATA_in[88] = (SACEFPDWDATA[88] !== 1'bz) && SACEFPDWDATA_delay[88]; // rv 0 + assign SACEFPDWDATA_in[89] = (SACEFPDWDATA[89] !== 1'bz) && SACEFPDWDATA_delay[89]; // rv 0 + assign SACEFPDWDATA_in[8] = (SACEFPDWDATA[8] !== 1'bz) && SACEFPDWDATA_delay[8]; // rv 0 + assign SACEFPDWDATA_in[90] = (SACEFPDWDATA[90] !== 1'bz) && SACEFPDWDATA_delay[90]; // rv 0 + assign SACEFPDWDATA_in[91] = (SACEFPDWDATA[91] !== 1'bz) && SACEFPDWDATA_delay[91]; // rv 0 + assign SACEFPDWDATA_in[92] = (SACEFPDWDATA[92] !== 1'bz) && SACEFPDWDATA_delay[92]; // rv 0 + assign SACEFPDWDATA_in[93] = (SACEFPDWDATA[93] !== 1'bz) && SACEFPDWDATA_delay[93]; // rv 0 + assign SACEFPDWDATA_in[94] = (SACEFPDWDATA[94] !== 1'bz) && SACEFPDWDATA_delay[94]; // rv 0 + assign SACEFPDWDATA_in[95] = (SACEFPDWDATA[95] !== 1'bz) && SACEFPDWDATA_delay[95]; // rv 0 + assign SACEFPDWDATA_in[96] = (SACEFPDWDATA[96] !== 1'bz) && SACEFPDWDATA_delay[96]; // rv 0 + assign SACEFPDWDATA_in[97] = (SACEFPDWDATA[97] !== 1'bz) && SACEFPDWDATA_delay[97]; // rv 0 + assign SACEFPDWDATA_in[98] = (SACEFPDWDATA[98] !== 1'bz) && SACEFPDWDATA_delay[98]; // rv 0 + assign SACEFPDWDATA_in[99] = (SACEFPDWDATA[99] !== 1'bz) && SACEFPDWDATA_delay[99]; // rv 0 + assign SACEFPDWDATA_in[9] = (SACEFPDWDATA[9] !== 1'bz) && SACEFPDWDATA_delay[9]; // rv 0 + assign SACEFPDWLAST_in = (SACEFPDWLAST !== 1'bz) && SACEFPDWLAST_delay; // rv 0 + assign SACEFPDWSTRB_in[0] = (SACEFPDWSTRB[0] !== 1'bz) && SACEFPDWSTRB_delay[0]; // rv 0 + assign SACEFPDWSTRB_in[10] = (SACEFPDWSTRB[10] !== 1'bz) && SACEFPDWSTRB_delay[10]; // rv 0 + assign SACEFPDWSTRB_in[11] = (SACEFPDWSTRB[11] !== 1'bz) && SACEFPDWSTRB_delay[11]; // rv 0 + assign SACEFPDWSTRB_in[12] = (SACEFPDWSTRB[12] !== 1'bz) && SACEFPDWSTRB_delay[12]; // rv 0 + assign SACEFPDWSTRB_in[13] = (SACEFPDWSTRB[13] !== 1'bz) && SACEFPDWSTRB_delay[13]; // rv 0 + assign SACEFPDWSTRB_in[14] = (SACEFPDWSTRB[14] !== 1'bz) && SACEFPDWSTRB_delay[14]; // rv 0 + assign SACEFPDWSTRB_in[15] = (SACEFPDWSTRB[15] !== 1'bz) && SACEFPDWSTRB_delay[15]; // rv 0 + assign SACEFPDWSTRB_in[1] = (SACEFPDWSTRB[1] !== 1'bz) && SACEFPDWSTRB_delay[1]; // rv 0 + assign SACEFPDWSTRB_in[2] = (SACEFPDWSTRB[2] !== 1'bz) && SACEFPDWSTRB_delay[2]; // rv 0 + assign SACEFPDWSTRB_in[3] = (SACEFPDWSTRB[3] !== 1'bz) && SACEFPDWSTRB_delay[3]; // rv 0 + assign SACEFPDWSTRB_in[4] = (SACEFPDWSTRB[4] !== 1'bz) && SACEFPDWSTRB_delay[4]; // rv 0 + assign SACEFPDWSTRB_in[5] = (SACEFPDWSTRB[5] !== 1'bz) && SACEFPDWSTRB_delay[5]; // rv 0 + assign SACEFPDWSTRB_in[6] = (SACEFPDWSTRB[6] !== 1'bz) && SACEFPDWSTRB_delay[6]; // rv 0 + assign SACEFPDWSTRB_in[7] = (SACEFPDWSTRB[7] !== 1'bz) && SACEFPDWSTRB_delay[7]; // rv 0 + assign SACEFPDWSTRB_in[8] = (SACEFPDWSTRB[8] !== 1'bz) && SACEFPDWSTRB_delay[8]; // rv 0 + assign SACEFPDWSTRB_in[9] = (SACEFPDWSTRB[9] !== 1'bz) && SACEFPDWSTRB_delay[9]; // rv 0 + assign SACEFPDWUSER_in = (SACEFPDWUSER !== 1'bz) && SACEFPDWUSER_delay; // rv 0 + assign SACEFPDWVALID_in = (SACEFPDWVALID !== 1'bz) && SACEFPDWVALID_delay; // rv 0 + assign SAXIACPACLK_in = (SAXIACPACLK !== 1'bz) && SAXIACPACLK_delay; // rv 0 + assign SAXIACPARADDR_in[0] = (SAXIACPARADDR[0] !== 1'bz) && SAXIACPARADDR_delay[0]; // rv 0 + assign SAXIACPARADDR_in[10] = (SAXIACPARADDR[10] !== 1'bz) && SAXIACPARADDR_delay[10]; // rv 0 + assign SAXIACPARADDR_in[11] = (SAXIACPARADDR[11] !== 1'bz) && SAXIACPARADDR_delay[11]; // rv 0 + assign SAXIACPARADDR_in[12] = (SAXIACPARADDR[12] !== 1'bz) && SAXIACPARADDR_delay[12]; // rv 0 + assign SAXIACPARADDR_in[13] = (SAXIACPARADDR[13] !== 1'bz) && SAXIACPARADDR_delay[13]; // rv 0 + assign SAXIACPARADDR_in[14] = (SAXIACPARADDR[14] !== 1'bz) && SAXIACPARADDR_delay[14]; // rv 0 + assign SAXIACPARADDR_in[15] = (SAXIACPARADDR[15] !== 1'bz) && SAXIACPARADDR_delay[15]; // rv 0 + assign SAXIACPARADDR_in[16] = (SAXIACPARADDR[16] !== 1'bz) && SAXIACPARADDR_delay[16]; // rv 0 + assign SAXIACPARADDR_in[17] = (SAXIACPARADDR[17] !== 1'bz) && SAXIACPARADDR_delay[17]; // rv 0 + assign SAXIACPARADDR_in[18] = (SAXIACPARADDR[18] !== 1'bz) && SAXIACPARADDR_delay[18]; // rv 0 + assign SAXIACPARADDR_in[19] = (SAXIACPARADDR[19] !== 1'bz) && SAXIACPARADDR_delay[19]; // rv 0 + assign SAXIACPARADDR_in[1] = (SAXIACPARADDR[1] !== 1'bz) && SAXIACPARADDR_delay[1]; // rv 0 + assign SAXIACPARADDR_in[20] = (SAXIACPARADDR[20] !== 1'bz) && SAXIACPARADDR_delay[20]; // rv 0 + assign SAXIACPARADDR_in[21] = (SAXIACPARADDR[21] !== 1'bz) && SAXIACPARADDR_delay[21]; // rv 0 + assign SAXIACPARADDR_in[22] = (SAXIACPARADDR[22] !== 1'bz) && SAXIACPARADDR_delay[22]; // rv 0 + assign SAXIACPARADDR_in[23] = (SAXIACPARADDR[23] !== 1'bz) && SAXIACPARADDR_delay[23]; // rv 0 + assign SAXIACPARADDR_in[24] = (SAXIACPARADDR[24] !== 1'bz) && SAXIACPARADDR_delay[24]; // rv 0 + assign SAXIACPARADDR_in[25] = (SAXIACPARADDR[25] !== 1'bz) && SAXIACPARADDR_delay[25]; // rv 0 + assign SAXIACPARADDR_in[26] = (SAXIACPARADDR[26] !== 1'bz) && SAXIACPARADDR_delay[26]; // rv 0 + assign SAXIACPARADDR_in[27] = (SAXIACPARADDR[27] !== 1'bz) && SAXIACPARADDR_delay[27]; // rv 0 + assign SAXIACPARADDR_in[28] = (SAXIACPARADDR[28] !== 1'bz) && SAXIACPARADDR_delay[28]; // rv 0 + assign SAXIACPARADDR_in[29] = (SAXIACPARADDR[29] !== 1'bz) && SAXIACPARADDR_delay[29]; // rv 0 + assign SAXIACPARADDR_in[2] = (SAXIACPARADDR[2] !== 1'bz) && SAXIACPARADDR_delay[2]; // rv 0 + assign SAXIACPARADDR_in[30] = (SAXIACPARADDR[30] !== 1'bz) && SAXIACPARADDR_delay[30]; // rv 0 + assign SAXIACPARADDR_in[31] = (SAXIACPARADDR[31] !== 1'bz) && SAXIACPARADDR_delay[31]; // rv 0 + assign SAXIACPARADDR_in[32] = (SAXIACPARADDR[32] !== 1'bz) && SAXIACPARADDR_delay[32]; // rv 0 + assign SAXIACPARADDR_in[33] = (SAXIACPARADDR[33] !== 1'bz) && SAXIACPARADDR_delay[33]; // rv 0 + assign SAXIACPARADDR_in[34] = (SAXIACPARADDR[34] !== 1'bz) && SAXIACPARADDR_delay[34]; // rv 0 + assign SAXIACPARADDR_in[35] = (SAXIACPARADDR[35] !== 1'bz) && SAXIACPARADDR_delay[35]; // rv 0 + assign SAXIACPARADDR_in[36] = (SAXIACPARADDR[36] !== 1'bz) && SAXIACPARADDR_delay[36]; // rv 0 + assign SAXIACPARADDR_in[37] = (SAXIACPARADDR[37] !== 1'bz) && SAXIACPARADDR_delay[37]; // rv 0 + assign SAXIACPARADDR_in[38] = (SAXIACPARADDR[38] !== 1'bz) && SAXIACPARADDR_delay[38]; // rv 0 + assign SAXIACPARADDR_in[39] = (SAXIACPARADDR[39] !== 1'bz) && SAXIACPARADDR_delay[39]; // rv 0 + assign SAXIACPARADDR_in[3] = (SAXIACPARADDR[3] !== 1'bz) && SAXIACPARADDR_delay[3]; // rv 0 + assign SAXIACPARADDR_in[4] = (SAXIACPARADDR[4] !== 1'bz) && SAXIACPARADDR_delay[4]; // rv 0 + assign SAXIACPARADDR_in[5] = (SAXIACPARADDR[5] !== 1'bz) && SAXIACPARADDR_delay[5]; // rv 0 + assign SAXIACPARADDR_in[6] = (SAXIACPARADDR[6] !== 1'bz) && SAXIACPARADDR_delay[6]; // rv 0 + assign SAXIACPARADDR_in[7] = (SAXIACPARADDR[7] !== 1'bz) && SAXIACPARADDR_delay[7]; // rv 0 + assign SAXIACPARADDR_in[8] = (SAXIACPARADDR[8] !== 1'bz) && SAXIACPARADDR_delay[8]; // rv 0 + assign SAXIACPARADDR_in[9] = (SAXIACPARADDR[9] !== 1'bz) && SAXIACPARADDR_delay[9]; // rv 0 + assign SAXIACPARBURST_in[0] = (SAXIACPARBURST[0] !== 1'bz) && SAXIACPARBURST_delay[0]; // rv 0 + assign SAXIACPARBURST_in[1] = (SAXIACPARBURST[1] !== 1'bz) && SAXIACPARBURST_delay[1]; // rv 0 + assign SAXIACPARCACHE_in[0] = (SAXIACPARCACHE[0] !== 1'bz) && SAXIACPARCACHE_delay[0]; // rv 0 + assign SAXIACPARCACHE_in[1] = (SAXIACPARCACHE[1] !== 1'bz) && SAXIACPARCACHE_delay[1]; // rv 0 + assign SAXIACPARCACHE_in[2] = (SAXIACPARCACHE[2] !== 1'bz) && SAXIACPARCACHE_delay[2]; // rv 0 + assign SAXIACPARCACHE_in[3] = (SAXIACPARCACHE[3] !== 1'bz) && SAXIACPARCACHE_delay[3]; // rv 0 + assign SAXIACPARID_in[0] = (SAXIACPARID[0] !== 1'bz) && SAXIACPARID_delay[0]; // rv 0 + assign SAXIACPARID_in[1] = (SAXIACPARID[1] !== 1'bz) && SAXIACPARID_delay[1]; // rv 0 + assign SAXIACPARID_in[2] = (SAXIACPARID[2] !== 1'bz) && SAXIACPARID_delay[2]; // rv 0 + assign SAXIACPARID_in[3] = (SAXIACPARID[3] !== 1'bz) && SAXIACPARID_delay[3]; // rv 0 + assign SAXIACPARID_in[4] = (SAXIACPARID[4] !== 1'bz) && SAXIACPARID_delay[4]; // rv 0 + assign SAXIACPARLEN_in[0] = (SAXIACPARLEN[0] !== 1'bz) && SAXIACPARLEN_delay[0]; // rv 0 + assign SAXIACPARLEN_in[1] = (SAXIACPARLEN[1] !== 1'bz) && SAXIACPARLEN_delay[1]; // rv 0 + assign SAXIACPARLEN_in[2] = (SAXIACPARLEN[2] !== 1'bz) && SAXIACPARLEN_delay[2]; // rv 0 + assign SAXIACPARLEN_in[3] = (SAXIACPARLEN[3] !== 1'bz) && SAXIACPARLEN_delay[3]; // rv 0 + assign SAXIACPARLEN_in[4] = (SAXIACPARLEN[4] !== 1'bz) && SAXIACPARLEN_delay[4]; // rv 0 + assign SAXIACPARLEN_in[5] = (SAXIACPARLEN[5] !== 1'bz) && SAXIACPARLEN_delay[5]; // rv 0 + assign SAXIACPARLEN_in[6] = (SAXIACPARLEN[6] !== 1'bz) && SAXIACPARLEN_delay[6]; // rv 0 + assign SAXIACPARLEN_in[7] = (SAXIACPARLEN[7] !== 1'bz) && SAXIACPARLEN_delay[7]; // rv 0 + assign SAXIACPARLOCK_in = (SAXIACPARLOCK !== 1'bz) && SAXIACPARLOCK_delay; // rv 0 + assign SAXIACPARPROT_in[0] = (SAXIACPARPROT[0] !== 1'bz) && SAXIACPARPROT_delay[0]; // rv 0 + assign SAXIACPARPROT_in[1] = (SAXIACPARPROT[1] !== 1'bz) && SAXIACPARPROT_delay[1]; // rv 0 + assign SAXIACPARPROT_in[2] = (SAXIACPARPROT[2] !== 1'bz) && SAXIACPARPROT_delay[2]; // rv 0 + assign SAXIACPARQOS_in[0] = (SAXIACPARQOS[0] !== 1'bz) && SAXIACPARQOS_delay[0]; // rv 0 + assign SAXIACPARQOS_in[1] = (SAXIACPARQOS[1] !== 1'bz) && SAXIACPARQOS_delay[1]; // rv 0 + assign SAXIACPARQOS_in[2] = (SAXIACPARQOS[2] !== 1'bz) && SAXIACPARQOS_delay[2]; // rv 0 + assign SAXIACPARQOS_in[3] = (SAXIACPARQOS[3] !== 1'bz) && SAXIACPARQOS_delay[3]; // rv 0 + assign SAXIACPARSIZE_in[0] = (SAXIACPARSIZE[0] !== 1'bz) && SAXIACPARSIZE_delay[0]; // rv 0 + assign SAXIACPARSIZE_in[1] = (SAXIACPARSIZE[1] !== 1'bz) && SAXIACPARSIZE_delay[1]; // rv 0 + assign SAXIACPARSIZE_in[2] = (SAXIACPARSIZE[2] !== 1'bz) && SAXIACPARSIZE_delay[2]; // rv 0 + assign SAXIACPARUSER_in[0] = (SAXIACPARUSER[0] !== 1'bz) && SAXIACPARUSER_delay[0]; // rv 0 + assign SAXIACPARUSER_in[1] = (SAXIACPARUSER[1] !== 1'bz) && SAXIACPARUSER_delay[1]; // rv 0 + assign SAXIACPARVALID_in = (SAXIACPARVALID !== 1'bz) && SAXIACPARVALID_delay; // rv 0 + assign SAXIACPAWADDR_in[0] = (SAXIACPAWADDR[0] !== 1'bz) && SAXIACPAWADDR_delay[0]; // rv 0 + assign SAXIACPAWADDR_in[10] = (SAXIACPAWADDR[10] !== 1'bz) && SAXIACPAWADDR_delay[10]; // rv 0 + assign SAXIACPAWADDR_in[11] = (SAXIACPAWADDR[11] !== 1'bz) && SAXIACPAWADDR_delay[11]; // rv 0 + assign SAXIACPAWADDR_in[12] = (SAXIACPAWADDR[12] !== 1'bz) && SAXIACPAWADDR_delay[12]; // rv 0 + assign SAXIACPAWADDR_in[13] = (SAXIACPAWADDR[13] !== 1'bz) && SAXIACPAWADDR_delay[13]; // rv 0 + assign SAXIACPAWADDR_in[14] = (SAXIACPAWADDR[14] !== 1'bz) && SAXIACPAWADDR_delay[14]; // rv 0 + assign SAXIACPAWADDR_in[15] = (SAXIACPAWADDR[15] !== 1'bz) && SAXIACPAWADDR_delay[15]; // rv 0 + assign SAXIACPAWADDR_in[16] = (SAXIACPAWADDR[16] !== 1'bz) && SAXIACPAWADDR_delay[16]; // rv 0 + assign SAXIACPAWADDR_in[17] = (SAXIACPAWADDR[17] !== 1'bz) && SAXIACPAWADDR_delay[17]; // rv 0 + assign SAXIACPAWADDR_in[18] = (SAXIACPAWADDR[18] !== 1'bz) && SAXIACPAWADDR_delay[18]; // rv 0 + assign SAXIACPAWADDR_in[19] = (SAXIACPAWADDR[19] !== 1'bz) && SAXIACPAWADDR_delay[19]; // rv 0 + assign SAXIACPAWADDR_in[1] = (SAXIACPAWADDR[1] !== 1'bz) && SAXIACPAWADDR_delay[1]; // rv 0 + assign SAXIACPAWADDR_in[20] = (SAXIACPAWADDR[20] !== 1'bz) && SAXIACPAWADDR_delay[20]; // rv 0 + assign SAXIACPAWADDR_in[21] = (SAXIACPAWADDR[21] !== 1'bz) && SAXIACPAWADDR_delay[21]; // rv 0 + assign SAXIACPAWADDR_in[22] = (SAXIACPAWADDR[22] !== 1'bz) && SAXIACPAWADDR_delay[22]; // rv 0 + assign SAXIACPAWADDR_in[23] = (SAXIACPAWADDR[23] !== 1'bz) && SAXIACPAWADDR_delay[23]; // rv 0 + assign SAXIACPAWADDR_in[24] = (SAXIACPAWADDR[24] !== 1'bz) && SAXIACPAWADDR_delay[24]; // rv 0 + assign SAXIACPAWADDR_in[25] = (SAXIACPAWADDR[25] !== 1'bz) && SAXIACPAWADDR_delay[25]; // rv 0 + assign SAXIACPAWADDR_in[26] = (SAXIACPAWADDR[26] !== 1'bz) && SAXIACPAWADDR_delay[26]; // rv 0 + assign SAXIACPAWADDR_in[27] = (SAXIACPAWADDR[27] !== 1'bz) && SAXIACPAWADDR_delay[27]; // rv 0 + assign SAXIACPAWADDR_in[28] = (SAXIACPAWADDR[28] !== 1'bz) && SAXIACPAWADDR_delay[28]; // rv 0 + assign SAXIACPAWADDR_in[29] = (SAXIACPAWADDR[29] !== 1'bz) && SAXIACPAWADDR_delay[29]; // rv 0 + assign SAXIACPAWADDR_in[2] = (SAXIACPAWADDR[2] !== 1'bz) && SAXIACPAWADDR_delay[2]; // rv 0 + assign SAXIACPAWADDR_in[30] = (SAXIACPAWADDR[30] !== 1'bz) && SAXIACPAWADDR_delay[30]; // rv 0 + assign SAXIACPAWADDR_in[31] = (SAXIACPAWADDR[31] !== 1'bz) && SAXIACPAWADDR_delay[31]; // rv 0 + assign SAXIACPAWADDR_in[32] = (SAXIACPAWADDR[32] !== 1'bz) && SAXIACPAWADDR_delay[32]; // rv 0 + assign SAXIACPAWADDR_in[33] = (SAXIACPAWADDR[33] !== 1'bz) && SAXIACPAWADDR_delay[33]; // rv 0 + assign SAXIACPAWADDR_in[34] = (SAXIACPAWADDR[34] !== 1'bz) && SAXIACPAWADDR_delay[34]; // rv 0 + assign SAXIACPAWADDR_in[35] = (SAXIACPAWADDR[35] !== 1'bz) && SAXIACPAWADDR_delay[35]; // rv 0 + assign SAXIACPAWADDR_in[36] = (SAXIACPAWADDR[36] !== 1'bz) && SAXIACPAWADDR_delay[36]; // rv 0 + assign SAXIACPAWADDR_in[37] = (SAXIACPAWADDR[37] !== 1'bz) && SAXIACPAWADDR_delay[37]; // rv 0 + assign SAXIACPAWADDR_in[38] = (SAXIACPAWADDR[38] !== 1'bz) && SAXIACPAWADDR_delay[38]; // rv 0 + assign SAXIACPAWADDR_in[39] = (SAXIACPAWADDR[39] !== 1'bz) && SAXIACPAWADDR_delay[39]; // rv 0 + assign SAXIACPAWADDR_in[3] = (SAXIACPAWADDR[3] !== 1'bz) && SAXIACPAWADDR_delay[3]; // rv 0 + assign SAXIACPAWADDR_in[4] = (SAXIACPAWADDR[4] !== 1'bz) && SAXIACPAWADDR_delay[4]; // rv 0 + assign SAXIACPAWADDR_in[5] = (SAXIACPAWADDR[5] !== 1'bz) && SAXIACPAWADDR_delay[5]; // rv 0 + assign SAXIACPAWADDR_in[6] = (SAXIACPAWADDR[6] !== 1'bz) && SAXIACPAWADDR_delay[6]; // rv 0 + assign SAXIACPAWADDR_in[7] = (SAXIACPAWADDR[7] !== 1'bz) && SAXIACPAWADDR_delay[7]; // rv 0 + assign SAXIACPAWADDR_in[8] = (SAXIACPAWADDR[8] !== 1'bz) && SAXIACPAWADDR_delay[8]; // rv 0 + assign SAXIACPAWADDR_in[9] = (SAXIACPAWADDR[9] !== 1'bz) && SAXIACPAWADDR_delay[9]; // rv 0 + assign SAXIACPAWBURST_in[0] = (SAXIACPAWBURST[0] !== 1'bz) && SAXIACPAWBURST_delay[0]; // rv 0 + assign SAXIACPAWBURST_in[1] = (SAXIACPAWBURST[1] !== 1'bz) && SAXIACPAWBURST_delay[1]; // rv 0 + assign SAXIACPAWCACHE_in[0] = (SAXIACPAWCACHE[0] !== 1'bz) && SAXIACPAWCACHE_delay[0]; // rv 0 + assign SAXIACPAWCACHE_in[1] = (SAXIACPAWCACHE[1] !== 1'bz) && SAXIACPAWCACHE_delay[1]; // rv 0 + assign SAXIACPAWCACHE_in[2] = (SAXIACPAWCACHE[2] !== 1'bz) && SAXIACPAWCACHE_delay[2]; // rv 0 + assign SAXIACPAWCACHE_in[3] = (SAXIACPAWCACHE[3] !== 1'bz) && SAXIACPAWCACHE_delay[3]; // rv 0 + assign SAXIACPAWID_in[0] = (SAXIACPAWID[0] !== 1'bz) && SAXIACPAWID_delay[0]; // rv 0 + assign SAXIACPAWID_in[1] = (SAXIACPAWID[1] !== 1'bz) && SAXIACPAWID_delay[1]; // rv 0 + assign SAXIACPAWID_in[2] = (SAXIACPAWID[2] !== 1'bz) && SAXIACPAWID_delay[2]; // rv 0 + assign SAXIACPAWID_in[3] = (SAXIACPAWID[3] !== 1'bz) && SAXIACPAWID_delay[3]; // rv 0 + assign SAXIACPAWID_in[4] = (SAXIACPAWID[4] !== 1'bz) && SAXIACPAWID_delay[4]; // rv 0 + assign SAXIACPAWLEN_in[0] = (SAXIACPAWLEN[0] !== 1'bz) && SAXIACPAWLEN_delay[0]; // rv 0 + assign SAXIACPAWLEN_in[1] = (SAXIACPAWLEN[1] !== 1'bz) && SAXIACPAWLEN_delay[1]; // rv 0 + assign SAXIACPAWLEN_in[2] = (SAXIACPAWLEN[2] !== 1'bz) && SAXIACPAWLEN_delay[2]; // rv 0 + assign SAXIACPAWLEN_in[3] = (SAXIACPAWLEN[3] !== 1'bz) && SAXIACPAWLEN_delay[3]; // rv 0 + assign SAXIACPAWLEN_in[4] = (SAXIACPAWLEN[4] !== 1'bz) && SAXIACPAWLEN_delay[4]; // rv 0 + assign SAXIACPAWLEN_in[5] = (SAXIACPAWLEN[5] !== 1'bz) && SAXIACPAWLEN_delay[5]; // rv 0 + assign SAXIACPAWLEN_in[6] = (SAXIACPAWLEN[6] !== 1'bz) && SAXIACPAWLEN_delay[6]; // rv 0 + assign SAXIACPAWLEN_in[7] = (SAXIACPAWLEN[7] !== 1'bz) && SAXIACPAWLEN_delay[7]; // rv 0 + assign SAXIACPAWLOCK_in = (SAXIACPAWLOCK !== 1'bz) && SAXIACPAWLOCK_delay; // rv 0 + assign SAXIACPAWPROT_in[0] = (SAXIACPAWPROT[0] !== 1'bz) && SAXIACPAWPROT_delay[0]; // rv 0 + assign SAXIACPAWPROT_in[1] = (SAXIACPAWPROT[1] !== 1'bz) && SAXIACPAWPROT_delay[1]; // rv 0 + assign SAXIACPAWPROT_in[2] = (SAXIACPAWPROT[2] !== 1'bz) && SAXIACPAWPROT_delay[2]; // rv 0 + assign SAXIACPAWQOS_in[0] = (SAXIACPAWQOS[0] !== 1'bz) && SAXIACPAWQOS_delay[0]; // rv 0 + assign SAXIACPAWQOS_in[1] = (SAXIACPAWQOS[1] !== 1'bz) && SAXIACPAWQOS_delay[1]; // rv 0 + assign SAXIACPAWQOS_in[2] = (SAXIACPAWQOS[2] !== 1'bz) && SAXIACPAWQOS_delay[2]; // rv 0 + assign SAXIACPAWQOS_in[3] = (SAXIACPAWQOS[3] !== 1'bz) && SAXIACPAWQOS_delay[3]; // rv 0 + assign SAXIACPAWSIZE_in[0] = (SAXIACPAWSIZE[0] !== 1'bz) && SAXIACPAWSIZE_delay[0]; // rv 0 + assign SAXIACPAWSIZE_in[1] = (SAXIACPAWSIZE[1] !== 1'bz) && SAXIACPAWSIZE_delay[1]; // rv 0 + assign SAXIACPAWSIZE_in[2] = (SAXIACPAWSIZE[2] !== 1'bz) && SAXIACPAWSIZE_delay[2]; // rv 0 + assign SAXIACPAWUSER_in[0] = (SAXIACPAWUSER[0] !== 1'bz) && SAXIACPAWUSER_delay[0]; // rv 0 + assign SAXIACPAWUSER_in[1] = (SAXIACPAWUSER[1] !== 1'bz) && SAXIACPAWUSER_delay[1]; // rv 0 + assign SAXIACPAWVALID_in = (SAXIACPAWVALID !== 1'bz) && SAXIACPAWVALID_delay; // rv 0 + assign SAXIACPBREADY_in = (SAXIACPBREADY !== 1'bz) && SAXIACPBREADY_delay; // rv 0 + assign SAXIACPRREADY_in = (SAXIACPRREADY !== 1'bz) && SAXIACPRREADY_delay; // rv 0 + assign SAXIACPWDATA_in[0] = (SAXIACPWDATA[0] !== 1'bz) && SAXIACPWDATA_delay[0]; // rv 0 + assign SAXIACPWDATA_in[100] = (SAXIACPWDATA[100] !== 1'bz) && SAXIACPWDATA_delay[100]; // rv 0 + assign SAXIACPWDATA_in[101] = (SAXIACPWDATA[101] !== 1'bz) && SAXIACPWDATA_delay[101]; // rv 0 + assign SAXIACPWDATA_in[102] = (SAXIACPWDATA[102] !== 1'bz) && SAXIACPWDATA_delay[102]; // rv 0 + assign SAXIACPWDATA_in[103] = (SAXIACPWDATA[103] !== 1'bz) && SAXIACPWDATA_delay[103]; // rv 0 + assign SAXIACPWDATA_in[104] = (SAXIACPWDATA[104] !== 1'bz) && SAXIACPWDATA_delay[104]; // rv 0 + assign SAXIACPWDATA_in[105] = (SAXIACPWDATA[105] !== 1'bz) && SAXIACPWDATA_delay[105]; // rv 0 + assign SAXIACPWDATA_in[106] = (SAXIACPWDATA[106] !== 1'bz) && SAXIACPWDATA_delay[106]; // rv 0 + assign SAXIACPWDATA_in[107] = (SAXIACPWDATA[107] !== 1'bz) && SAXIACPWDATA_delay[107]; // rv 0 + assign SAXIACPWDATA_in[108] = (SAXIACPWDATA[108] !== 1'bz) && SAXIACPWDATA_delay[108]; // rv 0 + assign SAXIACPWDATA_in[109] = (SAXIACPWDATA[109] !== 1'bz) && SAXIACPWDATA_delay[109]; // rv 0 + assign SAXIACPWDATA_in[10] = (SAXIACPWDATA[10] !== 1'bz) && SAXIACPWDATA_delay[10]; // rv 0 + assign SAXIACPWDATA_in[110] = (SAXIACPWDATA[110] !== 1'bz) && SAXIACPWDATA_delay[110]; // rv 0 + assign SAXIACPWDATA_in[111] = (SAXIACPWDATA[111] !== 1'bz) && SAXIACPWDATA_delay[111]; // rv 0 + assign SAXIACPWDATA_in[112] = (SAXIACPWDATA[112] !== 1'bz) && SAXIACPWDATA_delay[112]; // rv 0 + assign SAXIACPWDATA_in[113] = (SAXIACPWDATA[113] !== 1'bz) && SAXIACPWDATA_delay[113]; // rv 0 + assign SAXIACPWDATA_in[114] = (SAXIACPWDATA[114] !== 1'bz) && SAXIACPWDATA_delay[114]; // rv 0 + assign SAXIACPWDATA_in[115] = (SAXIACPWDATA[115] !== 1'bz) && SAXIACPWDATA_delay[115]; // rv 0 + assign SAXIACPWDATA_in[116] = (SAXIACPWDATA[116] !== 1'bz) && SAXIACPWDATA_delay[116]; // rv 0 + assign SAXIACPWDATA_in[117] = (SAXIACPWDATA[117] !== 1'bz) && SAXIACPWDATA_delay[117]; // rv 0 + assign SAXIACPWDATA_in[118] = (SAXIACPWDATA[118] !== 1'bz) && SAXIACPWDATA_delay[118]; // rv 0 + assign SAXIACPWDATA_in[119] = (SAXIACPWDATA[119] !== 1'bz) && SAXIACPWDATA_delay[119]; // rv 0 + assign SAXIACPWDATA_in[11] = (SAXIACPWDATA[11] !== 1'bz) && SAXIACPWDATA_delay[11]; // rv 0 + assign SAXIACPWDATA_in[120] = (SAXIACPWDATA[120] !== 1'bz) && SAXIACPWDATA_delay[120]; // rv 0 + assign SAXIACPWDATA_in[121] = (SAXIACPWDATA[121] !== 1'bz) && SAXIACPWDATA_delay[121]; // rv 0 + assign SAXIACPWDATA_in[122] = (SAXIACPWDATA[122] !== 1'bz) && SAXIACPWDATA_delay[122]; // rv 0 + assign SAXIACPWDATA_in[123] = (SAXIACPWDATA[123] !== 1'bz) && SAXIACPWDATA_delay[123]; // rv 0 + assign SAXIACPWDATA_in[124] = (SAXIACPWDATA[124] !== 1'bz) && SAXIACPWDATA_delay[124]; // rv 0 + assign SAXIACPWDATA_in[125] = (SAXIACPWDATA[125] !== 1'bz) && SAXIACPWDATA_delay[125]; // rv 0 + assign SAXIACPWDATA_in[126] = (SAXIACPWDATA[126] !== 1'bz) && SAXIACPWDATA_delay[126]; // rv 0 + assign SAXIACPWDATA_in[127] = (SAXIACPWDATA[127] !== 1'bz) && SAXIACPWDATA_delay[127]; // rv 0 + assign SAXIACPWDATA_in[12] = (SAXIACPWDATA[12] !== 1'bz) && SAXIACPWDATA_delay[12]; // rv 0 + assign SAXIACPWDATA_in[13] = (SAXIACPWDATA[13] !== 1'bz) && SAXIACPWDATA_delay[13]; // rv 0 + assign SAXIACPWDATA_in[14] = (SAXIACPWDATA[14] !== 1'bz) && SAXIACPWDATA_delay[14]; // rv 0 + assign SAXIACPWDATA_in[15] = (SAXIACPWDATA[15] !== 1'bz) && SAXIACPWDATA_delay[15]; // rv 0 + assign SAXIACPWDATA_in[16] = (SAXIACPWDATA[16] !== 1'bz) && SAXIACPWDATA_delay[16]; // rv 0 + assign SAXIACPWDATA_in[17] = (SAXIACPWDATA[17] !== 1'bz) && SAXIACPWDATA_delay[17]; // rv 0 + assign SAXIACPWDATA_in[18] = (SAXIACPWDATA[18] !== 1'bz) && SAXIACPWDATA_delay[18]; // rv 0 + assign SAXIACPWDATA_in[19] = (SAXIACPWDATA[19] !== 1'bz) && SAXIACPWDATA_delay[19]; // rv 0 + assign SAXIACPWDATA_in[1] = (SAXIACPWDATA[1] !== 1'bz) && SAXIACPWDATA_delay[1]; // rv 0 + assign SAXIACPWDATA_in[20] = (SAXIACPWDATA[20] !== 1'bz) && SAXIACPWDATA_delay[20]; // rv 0 + assign SAXIACPWDATA_in[21] = (SAXIACPWDATA[21] !== 1'bz) && SAXIACPWDATA_delay[21]; // rv 0 + assign SAXIACPWDATA_in[22] = (SAXIACPWDATA[22] !== 1'bz) && SAXIACPWDATA_delay[22]; // rv 0 + assign SAXIACPWDATA_in[23] = (SAXIACPWDATA[23] !== 1'bz) && SAXIACPWDATA_delay[23]; // rv 0 + assign SAXIACPWDATA_in[24] = (SAXIACPWDATA[24] !== 1'bz) && SAXIACPWDATA_delay[24]; // rv 0 + assign SAXIACPWDATA_in[25] = (SAXIACPWDATA[25] !== 1'bz) && SAXIACPWDATA_delay[25]; // rv 0 + assign SAXIACPWDATA_in[26] = (SAXIACPWDATA[26] !== 1'bz) && SAXIACPWDATA_delay[26]; // rv 0 + assign SAXIACPWDATA_in[27] = (SAXIACPWDATA[27] !== 1'bz) && SAXIACPWDATA_delay[27]; // rv 0 + assign SAXIACPWDATA_in[28] = (SAXIACPWDATA[28] !== 1'bz) && SAXIACPWDATA_delay[28]; // rv 0 + assign SAXIACPWDATA_in[29] = (SAXIACPWDATA[29] !== 1'bz) && SAXIACPWDATA_delay[29]; // rv 0 + assign SAXIACPWDATA_in[2] = (SAXIACPWDATA[2] !== 1'bz) && SAXIACPWDATA_delay[2]; // rv 0 + assign SAXIACPWDATA_in[30] = (SAXIACPWDATA[30] !== 1'bz) && SAXIACPWDATA_delay[30]; // rv 0 + assign SAXIACPWDATA_in[31] = (SAXIACPWDATA[31] !== 1'bz) && SAXIACPWDATA_delay[31]; // rv 0 + assign SAXIACPWDATA_in[32] = (SAXIACPWDATA[32] !== 1'bz) && SAXIACPWDATA_delay[32]; // rv 0 + assign SAXIACPWDATA_in[33] = (SAXIACPWDATA[33] !== 1'bz) && SAXIACPWDATA_delay[33]; // rv 0 + assign SAXIACPWDATA_in[34] = (SAXIACPWDATA[34] !== 1'bz) && SAXIACPWDATA_delay[34]; // rv 0 + assign SAXIACPWDATA_in[35] = (SAXIACPWDATA[35] !== 1'bz) && SAXIACPWDATA_delay[35]; // rv 0 + assign SAXIACPWDATA_in[36] = (SAXIACPWDATA[36] !== 1'bz) && SAXIACPWDATA_delay[36]; // rv 0 + assign SAXIACPWDATA_in[37] = (SAXIACPWDATA[37] !== 1'bz) && SAXIACPWDATA_delay[37]; // rv 0 + assign SAXIACPWDATA_in[38] = (SAXIACPWDATA[38] !== 1'bz) && SAXIACPWDATA_delay[38]; // rv 0 + assign SAXIACPWDATA_in[39] = (SAXIACPWDATA[39] !== 1'bz) && SAXIACPWDATA_delay[39]; // rv 0 + assign SAXIACPWDATA_in[3] = (SAXIACPWDATA[3] !== 1'bz) && SAXIACPWDATA_delay[3]; // rv 0 + assign SAXIACPWDATA_in[40] = (SAXIACPWDATA[40] !== 1'bz) && SAXIACPWDATA_delay[40]; // rv 0 + assign SAXIACPWDATA_in[41] = (SAXIACPWDATA[41] !== 1'bz) && SAXIACPWDATA_delay[41]; // rv 0 + assign SAXIACPWDATA_in[42] = (SAXIACPWDATA[42] !== 1'bz) && SAXIACPWDATA_delay[42]; // rv 0 + assign SAXIACPWDATA_in[43] = (SAXIACPWDATA[43] !== 1'bz) && SAXIACPWDATA_delay[43]; // rv 0 + assign SAXIACPWDATA_in[44] = (SAXIACPWDATA[44] !== 1'bz) && SAXIACPWDATA_delay[44]; // rv 0 + assign SAXIACPWDATA_in[45] = (SAXIACPWDATA[45] !== 1'bz) && SAXIACPWDATA_delay[45]; // rv 0 + assign SAXIACPWDATA_in[46] = (SAXIACPWDATA[46] !== 1'bz) && SAXIACPWDATA_delay[46]; // rv 0 + assign SAXIACPWDATA_in[47] = (SAXIACPWDATA[47] !== 1'bz) && SAXIACPWDATA_delay[47]; // rv 0 + assign SAXIACPWDATA_in[48] = (SAXIACPWDATA[48] !== 1'bz) && SAXIACPWDATA_delay[48]; // rv 0 + assign SAXIACPWDATA_in[49] = (SAXIACPWDATA[49] !== 1'bz) && SAXIACPWDATA_delay[49]; // rv 0 + assign SAXIACPWDATA_in[4] = (SAXIACPWDATA[4] !== 1'bz) && SAXIACPWDATA_delay[4]; // rv 0 + assign SAXIACPWDATA_in[50] = (SAXIACPWDATA[50] !== 1'bz) && SAXIACPWDATA_delay[50]; // rv 0 + assign SAXIACPWDATA_in[51] = (SAXIACPWDATA[51] !== 1'bz) && SAXIACPWDATA_delay[51]; // rv 0 + assign SAXIACPWDATA_in[52] = (SAXIACPWDATA[52] !== 1'bz) && SAXIACPWDATA_delay[52]; // rv 0 + assign SAXIACPWDATA_in[53] = (SAXIACPWDATA[53] !== 1'bz) && SAXIACPWDATA_delay[53]; // rv 0 + assign SAXIACPWDATA_in[54] = (SAXIACPWDATA[54] !== 1'bz) && SAXIACPWDATA_delay[54]; // rv 0 + assign SAXIACPWDATA_in[55] = (SAXIACPWDATA[55] !== 1'bz) && SAXIACPWDATA_delay[55]; // rv 0 + assign SAXIACPWDATA_in[56] = (SAXIACPWDATA[56] !== 1'bz) && SAXIACPWDATA_delay[56]; // rv 0 + assign SAXIACPWDATA_in[57] = (SAXIACPWDATA[57] !== 1'bz) && SAXIACPWDATA_delay[57]; // rv 0 + assign SAXIACPWDATA_in[58] = (SAXIACPWDATA[58] !== 1'bz) && SAXIACPWDATA_delay[58]; // rv 0 + assign SAXIACPWDATA_in[59] = (SAXIACPWDATA[59] !== 1'bz) && SAXIACPWDATA_delay[59]; // rv 0 + assign SAXIACPWDATA_in[5] = (SAXIACPWDATA[5] !== 1'bz) && SAXIACPWDATA_delay[5]; // rv 0 + assign SAXIACPWDATA_in[60] = (SAXIACPWDATA[60] !== 1'bz) && SAXIACPWDATA_delay[60]; // rv 0 + assign SAXIACPWDATA_in[61] = (SAXIACPWDATA[61] !== 1'bz) && SAXIACPWDATA_delay[61]; // rv 0 + assign SAXIACPWDATA_in[62] = (SAXIACPWDATA[62] !== 1'bz) && SAXIACPWDATA_delay[62]; // rv 0 + assign SAXIACPWDATA_in[63] = (SAXIACPWDATA[63] !== 1'bz) && SAXIACPWDATA_delay[63]; // rv 0 + assign SAXIACPWDATA_in[64] = (SAXIACPWDATA[64] !== 1'bz) && SAXIACPWDATA_delay[64]; // rv 0 + assign SAXIACPWDATA_in[65] = (SAXIACPWDATA[65] !== 1'bz) && SAXIACPWDATA_delay[65]; // rv 0 + assign SAXIACPWDATA_in[66] = (SAXIACPWDATA[66] !== 1'bz) && SAXIACPWDATA_delay[66]; // rv 0 + assign SAXIACPWDATA_in[67] = (SAXIACPWDATA[67] !== 1'bz) && SAXIACPWDATA_delay[67]; // rv 0 + assign SAXIACPWDATA_in[68] = (SAXIACPWDATA[68] !== 1'bz) && SAXIACPWDATA_delay[68]; // rv 0 + assign SAXIACPWDATA_in[69] = (SAXIACPWDATA[69] !== 1'bz) && SAXIACPWDATA_delay[69]; // rv 0 + assign SAXIACPWDATA_in[6] = (SAXIACPWDATA[6] !== 1'bz) && SAXIACPWDATA_delay[6]; // rv 0 + assign SAXIACPWDATA_in[70] = (SAXIACPWDATA[70] !== 1'bz) && SAXIACPWDATA_delay[70]; // rv 0 + assign SAXIACPWDATA_in[71] = (SAXIACPWDATA[71] !== 1'bz) && SAXIACPWDATA_delay[71]; // rv 0 + assign SAXIACPWDATA_in[72] = (SAXIACPWDATA[72] !== 1'bz) && SAXIACPWDATA_delay[72]; // rv 0 + assign SAXIACPWDATA_in[73] = (SAXIACPWDATA[73] !== 1'bz) && SAXIACPWDATA_delay[73]; // rv 0 + assign SAXIACPWDATA_in[74] = (SAXIACPWDATA[74] !== 1'bz) && SAXIACPWDATA_delay[74]; // rv 0 + assign SAXIACPWDATA_in[75] = (SAXIACPWDATA[75] !== 1'bz) && SAXIACPWDATA_delay[75]; // rv 0 + assign SAXIACPWDATA_in[76] = (SAXIACPWDATA[76] !== 1'bz) && SAXIACPWDATA_delay[76]; // rv 0 + assign SAXIACPWDATA_in[77] = (SAXIACPWDATA[77] !== 1'bz) && SAXIACPWDATA_delay[77]; // rv 0 + assign SAXIACPWDATA_in[78] = (SAXIACPWDATA[78] !== 1'bz) && SAXIACPWDATA_delay[78]; // rv 0 + assign SAXIACPWDATA_in[79] = (SAXIACPWDATA[79] !== 1'bz) && SAXIACPWDATA_delay[79]; // rv 0 + assign SAXIACPWDATA_in[7] = (SAXIACPWDATA[7] !== 1'bz) && SAXIACPWDATA_delay[7]; // rv 0 + assign SAXIACPWDATA_in[80] = (SAXIACPWDATA[80] !== 1'bz) && SAXIACPWDATA_delay[80]; // rv 0 + assign SAXIACPWDATA_in[81] = (SAXIACPWDATA[81] !== 1'bz) && SAXIACPWDATA_delay[81]; // rv 0 + assign SAXIACPWDATA_in[82] = (SAXIACPWDATA[82] !== 1'bz) && SAXIACPWDATA_delay[82]; // rv 0 + assign SAXIACPWDATA_in[83] = (SAXIACPWDATA[83] !== 1'bz) && SAXIACPWDATA_delay[83]; // rv 0 + assign SAXIACPWDATA_in[84] = (SAXIACPWDATA[84] !== 1'bz) && SAXIACPWDATA_delay[84]; // rv 0 + assign SAXIACPWDATA_in[85] = (SAXIACPWDATA[85] !== 1'bz) && SAXIACPWDATA_delay[85]; // rv 0 + assign SAXIACPWDATA_in[86] = (SAXIACPWDATA[86] !== 1'bz) && SAXIACPWDATA_delay[86]; // rv 0 + assign SAXIACPWDATA_in[87] = (SAXIACPWDATA[87] !== 1'bz) && SAXIACPWDATA_delay[87]; // rv 0 + assign SAXIACPWDATA_in[88] = (SAXIACPWDATA[88] !== 1'bz) && SAXIACPWDATA_delay[88]; // rv 0 + assign SAXIACPWDATA_in[89] = (SAXIACPWDATA[89] !== 1'bz) && SAXIACPWDATA_delay[89]; // rv 0 + assign SAXIACPWDATA_in[8] = (SAXIACPWDATA[8] !== 1'bz) && SAXIACPWDATA_delay[8]; // rv 0 + assign SAXIACPWDATA_in[90] = (SAXIACPWDATA[90] !== 1'bz) && SAXIACPWDATA_delay[90]; // rv 0 + assign SAXIACPWDATA_in[91] = (SAXIACPWDATA[91] !== 1'bz) && SAXIACPWDATA_delay[91]; // rv 0 + assign SAXIACPWDATA_in[92] = (SAXIACPWDATA[92] !== 1'bz) && SAXIACPWDATA_delay[92]; // rv 0 + assign SAXIACPWDATA_in[93] = (SAXIACPWDATA[93] !== 1'bz) && SAXIACPWDATA_delay[93]; // rv 0 + assign SAXIACPWDATA_in[94] = (SAXIACPWDATA[94] !== 1'bz) && SAXIACPWDATA_delay[94]; // rv 0 + assign SAXIACPWDATA_in[95] = (SAXIACPWDATA[95] !== 1'bz) && SAXIACPWDATA_delay[95]; // rv 0 + assign SAXIACPWDATA_in[96] = (SAXIACPWDATA[96] !== 1'bz) && SAXIACPWDATA_delay[96]; // rv 0 + assign SAXIACPWDATA_in[97] = (SAXIACPWDATA[97] !== 1'bz) && SAXIACPWDATA_delay[97]; // rv 0 + assign SAXIACPWDATA_in[98] = (SAXIACPWDATA[98] !== 1'bz) && SAXIACPWDATA_delay[98]; // rv 0 + assign SAXIACPWDATA_in[99] = (SAXIACPWDATA[99] !== 1'bz) && SAXIACPWDATA_delay[99]; // rv 0 + assign SAXIACPWDATA_in[9] = (SAXIACPWDATA[9] !== 1'bz) && SAXIACPWDATA_delay[9]; // rv 0 + assign SAXIACPWLAST_in = (SAXIACPWLAST !== 1'bz) && SAXIACPWLAST_delay; // rv 0 + assign SAXIACPWSTRB_in[0] = (SAXIACPWSTRB[0] !== 1'bz) && SAXIACPWSTRB_delay[0]; // rv 0 + assign SAXIACPWSTRB_in[10] = (SAXIACPWSTRB[10] !== 1'bz) && SAXIACPWSTRB_delay[10]; // rv 0 + assign SAXIACPWSTRB_in[11] = (SAXIACPWSTRB[11] !== 1'bz) && SAXIACPWSTRB_delay[11]; // rv 0 + assign SAXIACPWSTRB_in[12] = (SAXIACPWSTRB[12] !== 1'bz) && SAXIACPWSTRB_delay[12]; // rv 0 + assign SAXIACPWSTRB_in[13] = (SAXIACPWSTRB[13] !== 1'bz) && SAXIACPWSTRB_delay[13]; // rv 0 + assign SAXIACPWSTRB_in[14] = (SAXIACPWSTRB[14] !== 1'bz) && SAXIACPWSTRB_delay[14]; // rv 0 + assign SAXIACPWSTRB_in[15] = (SAXIACPWSTRB[15] !== 1'bz) && SAXIACPWSTRB_delay[15]; // rv 0 + assign SAXIACPWSTRB_in[1] = (SAXIACPWSTRB[1] !== 1'bz) && SAXIACPWSTRB_delay[1]; // rv 0 + assign SAXIACPWSTRB_in[2] = (SAXIACPWSTRB[2] !== 1'bz) && SAXIACPWSTRB_delay[2]; // rv 0 + assign SAXIACPWSTRB_in[3] = (SAXIACPWSTRB[3] !== 1'bz) && SAXIACPWSTRB_delay[3]; // rv 0 + assign SAXIACPWSTRB_in[4] = (SAXIACPWSTRB[4] !== 1'bz) && SAXIACPWSTRB_delay[4]; // rv 0 + assign SAXIACPWSTRB_in[5] = (SAXIACPWSTRB[5] !== 1'bz) && SAXIACPWSTRB_delay[5]; // rv 0 + assign SAXIACPWSTRB_in[6] = (SAXIACPWSTRB[6] !== 1'bz) && SAXIACPWSTRB_delay[6]; // rv 0 + assign SAXIACPWSTRB_in[7] = (SAXIACPWSTRB[7] !== 1'bz) && SAXIACPWSTRB_delay[7]; // rv 0 + assign SAXIACPWSTRB_in[8] = (SAXIACPWSTRB[8] !== 1'bz) && SAXIACPWSTRB_delay[8]; // rv 0 + assign SAXIACPWSTRB_in[9] = (SAXIACPWSTRB[9] !== 1'bz) && SAXIACPWSTRB_delay[9]; // rv 0 + assign SAXIACPWVALID_in = (SAXIACPWVALID !== 1'bz) && SAXIACPWVALID_delay; // rv 0 + assign SAXIGP0ARADDR_in[0] = (SAXIGP0ARADDR[0] !== 1'bz) && SAXIGP0ARADDR_delay[0]; // rv 0 + assign SAXIGP0ARADDR_in[10] = (SAXIGP0ARADDR[10] !== 1'bz) && SAXIGP0ARADDR_delay[10]; // rv 0 + assign SAXIGP0ARADDR_in[11] = (SAXIGP0ARADDR[11] !== 1'bz) && SAXIGP0ARADDR_delay[11]; // rv 0 + assign SAXIGP0ARADDR_in[12] = (SAXIGP0ARADDR[12] !== 1'bz) && SAXIGP0ARADDR_delay[12]; // rv 0 + assign SAXIGP0ARADDR_in[13] = (SAXIGP0ARADDR[13] !== 1'bz) && SAXIGP0ARADDR_delay[13]; // rv 0 + assign SAXIGP0ARADDR_in[14] = (SAXIGP0ARADDR[14] !== 1'bz) && SAXIGP0ARADDR_delay[14]; // rv 0 + assign SAXIGP0ARADDR_in[15] = (SAXIGP0ARADDR[15] !== 1'bz) && SAXIGP0ARADDR_delay[15]; // rv 0 + assign SAXIGP0ARADDR_in[16] = (SAXIGP0ARADDR[16] !== 1'bz) && SAXIGP0ARADDR_delay[16]; // rv 0 + assign SAXIGP0ARADDR_in[17] = (SAXIGP0ARADDR[17] !== 1'bz) && SAXIGP0ARADDR_delay[17]; // rv 0 + assign SAXIGP0ARADDR_in[18] = (SAXIGP0ARADDR[18] !== 1'bz) && SAXIGP0ARADDR_delay[18]; // rv 0 + assign SAXIGP0ARADDR_in[19] = (SAXIGP0ARADDR[19] !== 1'bz) && SAXIGP0ARADDR_delay[19]; // rv 0 + assign SAXIGP0ARADDR_in[1] = (SAXIGP0ARADDR[1] !== 1'bz) && SAXIGP0ARADDR_delay[1]; // rv 0 + assign SAXIGP0ARADDR_in[20] = (SAXIGP0ARADDR[20] !== 1'bz) && SAXIGP0ARADDR_delay[20]; // rv 0 + assign SAXIGP0ARADDR_in[21] = (SAXIGP0ARADDR[21] !== 1'bz) && SAXIGP0ARADDR_delay[21]; // rv 0 + assign SAXIGP0ARADDR_in[22] = (SAXIGP0ARADDR[22] !== 1'bz) && SAXIGP0ARADDR_delay[22]; // rv 0 + assign SAXIGP0ARADDR_in[23] = (SAXIGP0ARADDR[23] !== 1'bz) && SAXIGP0ARADDR_delay[23]; // rv 0 + assign SAXIGP0ARADDR_in[24] = (SAXIGP0ARADDR[24] !== 1'bz) && SAXIGP0ARADDR_delay[24]; // rv 0 + assign SAXIGP0ARADDR_in[25] = (SAXIGP0ARADDR[25] !== 1'bz) && SAXIGP0ARADDR_delay[25]; // rv 0 + assign SAXIGP0ARADDR_in[26] = (SAXIGP0ARADDR[26] !== 1'bz) && SAXIGP0ARADDR_delay[26]; // rv 0 + assign SAXIGP0ARADDR_in[27] = (SAXIGP0ARADDR[27] !== 1'bz) && SAXIGP0ARADDR_delay[27]; // rv 0 + assign SAXIGP0ARADDR_in[28] = (SAXIGP0ARADDR[28] !== 1'bz) && SAXIGP0ARADDR_delay[28]; // rv 0 + assign SAXIGP0ARADDR_in[29] = (SAXIGP0ARADDR[29] !== 1'bz) && SAXIGP0ARADDR_delay[29]; // rv 0 + assign SAXIGP0ARADDR_in[2] = (SAXIGP0ARADDR[2] !== 1'bz) && SAXIGP0ARADDR_delay[2]; // rv 0 + assign SAXIGP0ARADDR_in[30] = (SAXIGP0ARADDR[30] !== 1'bz) && SAXIGP0ARADDR_delay[30]; // rv 0 + assign SAXIGP0ARADDR_in[31] = (SAXIGP0ARADDR[31] !== 1'bz) && SAXIGP0ARADDR_delay[31]; // rv 0 + assign SAXIGP0ARADDR_in[32] = (SAXIGP0ARADDR[32] !== 1'bz) && SAXIGP0ARADDR_delay[32]; // rv 0 + assign SAXIGP0ARADDR_in[33] = (SAXIGP0ARADDR[33] !== 1'bz) && SAXIGP0ARADDR_delay[33]; // rv 0 + assign SAXIGP0ARADDR_in[34] = (SAXIGP0ARADDR[34] !== 1'bz) && SAXIGP0ARADDR_delay[34]; // rv 0 + assign SAXIGP0ARADDR_in[35] = (SAXIGP0ARADDR[35] !== 1'bz) && SAXIGP0ARADDR_delay[35]; // rv 0 + assign SAXIGP0ARADDR_in[36] = (SAXIGP0ARADDR[36] !== 1'bz) && SAXIGP0ARADDR_delay[36]; // rv 0 + assign SAXIGP0ARADDR_in[37] = (SAXIGP0ARADDR[37] !== 1'bz) && SAXIGP0ARADDR_delay[37]; // rv 0 + assign SAXIGP0ARADDR_in[38] = (SAXIGP0ARADDR[38] !== 1'bz) && SAXIGP0ARADDR_delay[38]; // rv 0 + assign SAXIGP0ARADDR_in[39] = (SAXIGP0ARADDR[39] !== 1'bz) && SAXIGP0ARADDR_delay[39]; // rv 0 + assign SAXIGP0ARADDR_in[3] = (SAXIGP0ARADDR[3] !== 1'bz) && SAXIGP0ARADDR_delay[3]; // rv 0 + assign SAXIGP0ARADDR_in[40] = (SAXIGP0ARADDR[40] !== 1'bz) && SAXIGP0ARADDR_delay[40]; // rv 0 + assign SAXIGP0ARADDR_in[41] = (SAXIGP0ARADDR[41] !== 1'bz) && SAXIGP0ARADDR_delay[41]; // rv 0 + assign SAXIGP0ARADDR_in[42] = (SAXIGP0ARADDR[42] !== 1'bz) && SAXIGP0ARADDR_delay[42]; // rv 0 + assign SAXIGP0ARADDR_in[43] = (SAXIGP0ARADDR[43] !== 1'bz) && SAXIGP0ARADDR_delay[43]; // rv 0 + assign SAXIGP0ARADDR_in[44] = (SAXIGP0ARADDR[44] !== 1'bz) && SAXIGP0ARADDR_delay[44]; // rv 0 + assign SAXIGP0ARADDR_in[45] = (SAXIGP0ARADDR[45] !== 1'bz) && SAXIGP0ARADDR_delay[45]; // rv 0 + assign SAXIGP0ARADDR_in[46] = (SAXIGP0ARADDR[46] !== 1'bz) && SAXIGP0ARADDR_delay[46]; // rv 0 + assign SAXIGP0ARADDR_in[47] = (SAXIGP0ARADDR[47] !== 1'bz) && SAXIGP0ARADDR_delay[47]; // rv 0 + assign SAXIGP0ARADDR_in[48] = (SAXIGP0ARADDR[48] !== 1'bz) && SAXIGP0ARADDR_delay[48]; // rv 0 + assign SAXIGP0ARADDR_in[4] = (SAXIGP0ARADDR[4] !== 1'bz) && SAXIGP0ARADDR_delay[4]; // rv 0 + assign SAXIGP0ARADDR_in[5] = (SAXIGP0ARADDR[5] !== 1'bz) && SAXIGP0ARADDR_delay[5]; // rv 0 + assign SAXIGP0ARADDR_in[6] = (SAXIGP0ARADDR[6] !== 1'bz) && SAXIGP0ARADDR_delay[6]; // rv 0 + assign SAXIGP0ARADDR_in[7] = (SAXIGP0ARADDR[7] !== 1'bz) && SAXIGP0ARADDR_delay[7]; // rv 0 + assign SAXIGP0ARADDR_in[8] = (SAXIGP0ARADDR[8] !== 1'bz) && SAXIGP0ARADDR_delay[8]; // rv 0 + assign SAXIGP0ARADDR_in[9] = (SAXIGP0ARADDR[9] !== 1'bz) && SAXIGP0ARADDR_delay[9]; // rv 0 + assign SAXIGP0ARBURST_in[0] = (SAXIGP0ARBURST[0] !== 1'bz) && SAXIGP0ARBURST_delay[0]; // rv 0 + assign SAXIGP0ARBURST_in[1] = (SAXIGP0ARBURST[1] !== 1'bz) && SAXIGP0ARBURST_delay[1]; // rv 0 + assign SAXIGP0ARCACHE_in[0] = (SAXIGP0ARCACHE[0] !== 1'bz) && SAXIGP0ARCACHE_delay[0]; // rv 0 + assign SAXIGP0ARCACHE_in[1] = (SAXIGP0ARCACHE[1] !== 1'bz) && SAXIGP0ARCACHE_delay[1]; // rv 0 + assign SAXIGP0ARCACHE_in[2] = (SAXIGP0ARCACHE[2] !== 1'bz) && SAXIGP0ARCACHE_delay[2]; // rv 0 + assign SAXIGP0ARCACHE_in[3] = (SAXIGP0ARCACHE[3] !== 1'bz) && SAXIGP0ARCACHE_delay[3]; // rv 0 + assign SAXIGP0ARID_in[0] = (SAXIGP0ARID[0] !== 1'bz) && SAXIGP0ARID_delay[0]; // rv 0 + assign SAXIGP0ARID_in[1] = (SAXIGP0ARID[1] !== 1'bz) && SAXIGP0ARID_delay[1]; // rv 0 + assign SAXIGP0ARID_in[2] = (SAXIGP0ARID[2] !== 1'bz) && SAXIGP0ARID_delay[2]; // rv 0 + assign SAXIGP0ARID_in[3] = (SAXIGP0ARID[3] !== 1'bz) && SAXIGP0ARID_delay[3]; // rv 0 + assign SAXIGP0ARID_in[4] = (SAXIGP0ARID[4] !== 1'bz) && SAXIGP0ARID_delay[4]; // rv 0 + assign SAXIGP0ARID_in[5] = (SAXIGP0ARID[5] !== 1'bz) && SAXIGP0ARID_delay[5]; // rv 0 + assign SAXIGP0ARLEN_in[0] = (SAXIGP0ARLEN[0] !== 1'bz) && SAXIGP0ARLEN_delay[0]; // rv 0 + assign SAXIGP0ARLEN_in[1] = (SAXIGP0ARLEN[1] !== 1'bz) && SAXIGP0ARLEN_delay[1]; // rv 0 + assign SAXIGP0ARLEN_in[2] = (SAXIGP0ARLEN[2] !== 1'bz) && SAXIGP0ARLEN_delay[2]; // rv 0 + assign SAXIGP0ARLEN_in[3] = (SAXIGP0ARLEN[3] !== 1'bz) && SAXIGP0ARLEN_delay[3]; // rv 0 + assign SAXIGP0ARLEN_in[4] = (SAXIGP0ARLEN[4] !== 1'bz) && SAXIGP0ARLEN_delay[4]; // rv 0 + assign SAXIGP0ARLEN_in[5] = (SAXIGP0ARLEN[5] !== 1'bz) && SAXIGP0ARLEN_delay[5]; // rv 0 + assign SAXIGP0ARLEN_in[6] = (SAXIGP0ARLEN[6] !== 1'bz) && SAXIGP0ARLEN_delay[6]; // rv 0 + assign SAXIGP0ARLEN_in[7] = (SAXIGP0ARLEN[7] !== 1'bz) && SAXIGP0ARLEN_delay[7]; // rv 0 + assign SAXIGP0ARLOCK_in = (SAXIGP0ARLOCK !== 1'bz) && SAXIGP0ARLOCK_delay; // rv 0 + assign SAXIGP0ARPROT_in[0] = (SAXIGP0ARPROT[0] !== 1'bz) && SAXIGP0ARPROT_delay[0]; // rv 0 + assign SAXIGP0ARPROT_in[1] = (SAXIGP0ARPROT[1] !== 1'bz) && SAXIGP0ARPROT_delay[1]; // rv 0 + assign SAXIGP0ARPROT_in[2] = (SAXIGP0ARPROT[2] !== 1'bz) && SAXIGP0ARPROT_delay[2]; // rv 0 + assign SAXIGP0ARQOS_in[0] = (SAXIGP0ARQOS[0] !== 1'bz) && SAXIGP0ARQOS_delay[0]; // rv 0 + assign SAXIGP0ARQOS_in[1] = (SAXIGP0ARQOS[1] !== 1'bz) && SAXIGP0ARQOS_delay[1]; // rv 0 + assign SAXIGP0ARQOS_in[2] = (SAXIGP0ARQOS[2] !== 1'bz) && SAXIGP0ARQOS_delay[2]; // rv 0 + assign SAXIGP0ARQOS_in[3] = (SAXIGP0ARQOS[3] !== 1'bz) && SAXIGP0ARQOS_delay[3]; // rv 0 + assign SAXIGP0ARSIZE_in[0] = (SAXIGP0ARSIZE[0] !== 1'bz) && SAXIGP0ARSIZE_delay[0]; // rv 0 + assign SAXIGP0ARSIZE_in[1] = (SAXIGP0ARSIZE[1] !== 1'bz) && SAXIGP0ARSIZE_delay[1]; // rv 0 + assign SAXIGP0ARSIZE_in[2] = (SAXIGP0ARSIZE[2] !== 1'bz) && SAXIGP0ARSIZE_delay[2]; // rv 0 + assign SAXIGP0ARUSER_in = (SAXIGP0ARUSER !== 1'bz) && SAXIGP0ARUSER_delay; // rv 0 + assign SAXIGP0ARVALID_in = (SAXIGP0ARVALID !== 1'bz) && SAXIGP0ARVALID_delay; // rv 0 + assign SAXIGP0AWADDR_in[0] = (SAXIGP0AWADDR[0] !== 1'bz) && SAXIGP0AWADDR_delay[0]; // rv 0 + assign SAXIGP0AWADDR_in[10] = (SAXIGP0AWADDR[10] !== 1'bz) && SAXIGP0AWADDR_delay[10]; // rv 0 + assign SAXIGP0AWADDR_in[11] = (SAXIGP0AWADDR[11] !== 1'bz) && SAXIGP0AWADDR_delay[11]; // rv 0 + assign SAXIGP0AWADDR_in[12] = (SAXIGP0AWADDR[12] !== 1'bz) && SAXIGP0AWADDR_delay[12]; // rv 0 + assign SAXIGP0AWADDR_in[13] = (SAXIGP0AWADDR[13] !== 1'bz) && SAXIGP0AWADDR_delay[13]; // rv 0 + assign SAXIGP0AWADDR_in[14] = (SAXIGP0AWADDR[14] !== 1'bz) && SAXIGP0AWADDR_delay[14]; // rv 0 + assign SAXIGP0AWADDR_in[15] = (SAXIGP0AWADDR[15] !== 1'bz) && SAXIGP0AWADDR_delay[15]; // rv 0 + assign SAXIGP0AWADDR_in[16] = (SAXIGP0AWADDR[16] !== 1'bz) && SAXIGP0AWADDR_delay[16]; // rv 0 + assign SAXIGP0AWADDR_in[17] = (SAXIGP0AWADDR[17] !== 1'bz) && SAXIGP0AWADDR_delay[17]; // rv 0 + assign SAXIGP0AWADDR_in[18] = (SAXIGP0AWADDR[18] !== 1'bz) && SAXIGP0AWADDR_delay[18]; // rv 0 + assign SAXIGP0AWADDR_in[19] = (SAXIGP0AWADDR[19] !== 1'bz) && SAXIGP0AWADDR_delay[19]; // rv 0 + assign SAXIGP0AWADDR_in[1] = (SAXIGP0AWADDR[1] !== 1'bz) && SAXIGP0AWADDR_delay[1]; // rv 0 + assign SAXIGP0AWADDR_in[20] = (SAXIGP0AWADDR[20] !== 1'bz) && SAXIGP0AWADDR_delay[20]; // rv 0 + assign SAXIGP0AWADDR_in[21] = (SAXIGP0AWADDR[21] !== 1'bz) && SAXIGP0AWADDR_delay[21]; // rv 0 + assign SAXIGP0AWADDR_in[22] = (SAXIGP0AWADDR[22] !== 1'bz) && SAXIGP0AWADDR_delay[22]; // rv 0 + assign SAXIGP0AWADDR_in[23] = (SAXIGP0AWADDR[23] !== 1'bz) && SAXIGP0AWADDR_delay[23]; // rv 0 + assign SAXIGP0AWADDR_in[24] = (SAXIGP0AWADDR[24] !== 1'bz) && SAXIGP0AWADDR_delay[24]; // rv 0 + assign SAXIGP0AWADDR_in[25] = (SAXIGP0AWADDR[25] !== 1'bz) && SAXIGP0AWADDR_delay[25]; // rv 0 + assign SAXIGP0AWADDR_in[26] = (SAXIGP0AWADDR[26] !== 1'bz) && SAXIGP0AWADDR_delay[26]; // rv 0 + assign SAXIGP0AWADDR_in[27] = (SAXIGP0AWADDR[27] !== 1'bz) && SAXIGP0AWADDR_delay[27]; // rv 0 + assign SAXIGP0AWADDR_in[28] = (SAXIGP0AWADDR[28] !== 1'bz) && SAXIGP0AWADDR_delay[28]; // rv 0 + assign SAXIGP0AWADDR_in[29] = (SAXIGP0AWADDR[29] !== 1'bz) && SAXIGP0AWADDR_delay[29]; // rv 0 + assign SAXIGP0AWADDR_in[2] = (SAXIGP0AWADDR[2] !== 1'bz) && SAXIGP0AWADDR_delay[2]; // rv 0 + assign SAXIGP0AWADDR_in[30] = (SAXIGP0AWADDR[30] !== 1'bz) && SAXIGP0AWADDR_delay[30]; // rv 0 + assign SAXIGP0AWADDR_in[31] = (SAXIGP0AWADDR[31] !== 1'bz) && SAXIGP0AWADDR_delay[31]; // rv 0 + assign SAXIGP0AWADDR_in[32] = (SAXIGP0AWADDR[32] !== 1'bz) && SAXIGP0AWADDR_delay[32]; // rv 0 + assign SAXIGP0AWADDR_in[33] = (SAXIGP0AWADDR[33] !== 1'bz) && SAXIGP0AWADDR_delay[33]; // rv 0 + assign SAXIGP0AWADDR_in[34] = (SAXIGP0AWADDR[34] !== 1'bz) && SAXIGP0AWADDR_delay[34]; // rv 0 + assign SAXIGP0AWADDR_in[35] = (SAXIGP0AWADDR[35] !== 1'bz) && SAXIGP0AWADDR_delay[35]; // rv 0 + assign SAXIGP0AWADDR_in[36] = (SAXIGP0AWADDR[36] !== 1'bz) && SAXIGP0AWADDR_delay[36]; // rv 0 + assign SAXIGP0AWADDR_in[37] = (SAXIGP0AWADDR[37] !== 1'bz) && SAXIGP0AWADDR_delay[37]; // rv 0 + assign SAXIGP0AWADDR_in[38] = (SAXIGP0AWADDR[38] !== 1'bz) && SAXIGP0AWADDR_delay[38]; // rv 0 + assign SAXIGP0AWADDR_in[39] = (SAXIGP0AWADDR[39] !== 1'bz) && SAXIGP0AWADDR_delay[39]; // rv 0 + assign SAXIGP0AWADDR_in[3] = (SAXIGP0AWADDR[3] !== 1'bz) && SAXIGP0AWADDR_delay[3]; // rv 0 + assign SAXIGP0AWADDR_in[40] = (SAXIGP0AWADDR[40] !== 1'bz) && SAXIGP0AWADDR_delay[40]; // rv 0 + assign SAXIGP0AWADDR_in[41] = (SAXIGP0AWADDR[41] !== 1'bz) && SAXIGP0AWADDR_delay[41]; // rv 0 + assign SAXIGP0AWADDR_in[42] = (SAXIGP0AWADDR[42] !== 1'bz) && SAXIGP0AWADDR_delay[42]; // rv 0 + assign SAXIGP0AWADDR_in[43] = (SAXIGP0AWADDR[43] !== 1'bz) && SAXIGP0AWADDR_delay[43]; // rv 0 + assign SAXIGP0AWADDR_in[44] = (SAXIGP0AWADDR[44] !== 1'bz) && SAXIGP0AWADDR_delay[44]; // rv 0 + assign SAXIGP0AWADDR_in[45] = (SAXIGP0AWADDR[45] !== 1'bz) && SAXIGP0AWADDR_delay[45]; // rv 0 + assign SAXIGP0AWADDR_in[46] = (SAXIGP0AWADDR[46] !== 1'bz) && SAXIGP0AWADDR_delay[46]; // rv 0 + assign SAXIGP0AWADDR_in[47] = (SAXIGP0AWADDR[47] !== 1'bz) && SAXIGP0AWADDR_delay[47]; // rv 0 + assign SAXIGP0AWADDR_in[48] = (SAXIGP0AWADDR[48] !== 1'bz) && SAXIGP0AWADDR_delay[48]; // rv 0 + assign SAXIGP0AWADDR_in[4] = (SAXIGP0AWADDR[4] !== 1'bz) && SAXIGP0AWADDR_delay[4]; // rv 0 + assign SAXIGP0AWADDR_in[5] = (SAXIGP0AWADDR[5] !== 1'bz) && SAXIGP0AWADDR_delay[5]; // rv 0 + assign SAXIGP0AWADDR_in[6] = (SAXIGP0AWADDR[6] !== 1'bz) && SAXIGP0AWADDR_delay[6]; // rv 0 + assign SAXIGP0AWADDR_in[7] = (SAXIGP0AWADDR[7] !== 1'bz) && SAXIGP0AWADDR_delay[7]; // rv 0 + assign SAXIGP0AWADDR_in[8] = (SAXIGP0AWADDR[8] !== 1'bz) && SAXIGP0AWADDR_delay[8]; // rv 0 + assign SAXIGP0AWADDR_in[9] = (SAXIGP0AWADDR[9] !== 1'bz) && SAXIGP0AWADDR_delay[9]; // rv 0 + assign SAXIGP0AWBURST_in[0] = (SAXIGP0AWBURST[0] !== 1'bz) && SAXIGP0AWBURST_delay[0]; // rv 0 + assign SAXIGP0AWBURST_in[1] = (SAXIGP0AWBURST[1] !== 1'bz) && SAXIGP0AWBURST_delay[1]; // rv 0 + assign SAXIGP0AWCACHE_in[0] = (SAXIGP0AWCACHE[0] !== 1'bz) && SAXIGP0AWCACHE_delay[0]; // rv 0 + assign SAXIGP0AWCACHE_in[1] = (SAXIGP0AWCACHE[1] !== 1'bz) && SAXIGP0AWCACHE_delay[1]; // rv 0 + assign SAXIGP0AWCACHE_in[2] = (SAXIGP0AWCACHE[2] !== 1'bz) && SAXIGP0AWCACHE_delay[2]; // rv 0 + assign SAXIGP0AWCACHE_in[3] = (SAXIGP0AWCACHE[3] !== 1'bz) && SAXIGP0AWCACHE_delay[3]; // rv 0 + assign SAXIGP0AWID_in[0] = (SAXIGP0AWID[0] !== 1'bz) && SAXIGP0AWID_delay[0]; // rv 0 + assign SAXIGP0AWID_in[1] = (SAXIGP0AWID[1] !== 1'bz) && SAXIGP0AWID_delay[1]; // rv 0 + assign SAXIGP0AWID_in[2] = (SAXIGP0AWID[2] !== 1'bz) && SAXIGP0AWID_delay[2]; // rv 0 + assign SAXIGP0AWID_in[3] = (SAXIGP0AWID[3] !== 1'bz) && SAXIGP0AWID_delay[3]; // rv 0 + assign SAXIGP0AWID_in[4] = (SAXIGP0AWID[4] !== 1'bz) && SAXIGP0AWID_delay[4]; // rv 0 + assign SAXIGP0AWID_in[5] = (SAXIGP0AWID[5] !== 1'bz) && SAXIGP0AWID_delay[5]; // rv 0 + assign SAXIGP0AWLEN_in[0] = (SAXIGP0AWLEN[0] !== 1'bz) && SAXIGP0AWLEN_delay[0]; // rv 0 + assign SAXIGP0AWLEN_in[1] = (SAXIGP0AWLEN[1] !== 1'bz) && SAXIGP0AWLEN_delay[1]; // rv 0 + assign SAXIGP0AWLEN_in[2] = (SAXIGP0AWLEN[2] !== 1'bz) && SAXIGP0AWLEN_delay[2]; // rv 0 + assign SAXIGP0AWLEN_in[3] = (SAXIGP0AWLEN[3] !== 1'bz) && SAXIGP0AWLEN_delay[3]; // rv 0 + assign SAXIGP0AWLEN_in[4] = (SAXIGP0AWLEN[4] !== 1'bz) && SAXIGP0AWLEN_delay[4]; // rv 0 + assign SAXIGP0AWLEN_in[5] = (SAXIGP0AWLEN[5] !== 1'bz) && SAXIGP0AWLEN_delay[5]; // rv 0 + assign SAXIGP0AWLEN_in[6] = (SAXIGP0AWLEN[6] !== 1'bz) && SAXIGP0AWLEN_delay[6]; // rv 0 + assign SAXIGP0AWLEN_in[7] = (SAXIGP0AWLEN[7] !== 1'bz) && SAXIGP0AWLEN_delay[7]; // rv 0 + assign SAXIGP0AWLOCK_in = (SAXIGP0AWLOCK !== 1'bz) && SAXIGP0AWLOCK_delay; // rv 0 + assign SAXIGP0AWPROT_in[0] = (SAXIGP0AWPROT[0] !== 1'bz) && SAXIGP0AWPROT_delay[0]; // rv 0 + assign SAXIGP0AWPROT_in[1] = (SAXIGP0AWPROT[1] !== 1'bz) && SAXIGP0AWPROT_delay[1]; // rv 0 + assign SAXIGP0AWPROT_in[2] = (SAXIGP0AWPROT[2] !== 1'bz) && SAXIGP0AWPROT_delay[2]; // rv 0 + assign SAXIGP0AWQOS_in[0] = (SAXIGP0AWQOS[0] !== 1'bz) && SAXIGP0AWQOS_delay[0]; // rv 0 + assign SAXIGP0AWQOS_in[1] = (SAXIGP0AWQOS[1] !== 1'bz) && SAXIGP0AWQOS_delay[1]; // rv 0 + assign SAXIGP0AWQOS_in[2] = (SAXIGP0AWQOS[2] !== 1'bz) && SAXIGP0AWQOS_delay[2]; // rv 0 + assign SAXIGP0AWQOS_in[3] = (SAXIGP0AWQOS[3] !== 1'bz) && SAXIGP0AWQOS_delay[3]; // rv 0 + assign SAXIGP0AWSIZE_in[0] = (SAXIGP0AWSIZE[0] !== 1'bz) && SAXIGP0AWSIZE_delay[0]; // rv 0 + assign SAXIGP0AWSIZE_in[1] = (SAXIGP0AWSIZE[1] !== 1'bz) && SAXIGP0AWSIZE_delay[1]; // rv 0 + assign SAXIGP0AWSIZE_in[2] = (SAXIGP0AWSIZE[2] !== 1'bz) && SAXIGP0AWSIZE_delay[2]; // rv 0 + assign SAXIGP0AWUSER_in = (SAXIGP0AWUSER !== 1'bz) && SAXIGP0AWUSER_delay; // rv 0 + assign SAXIGP0AWVALID_in = (SAXIGP0AWVALID !== 1'bz) && SAXIGP0AWVALID_delay; // rv 0 + assign SAXIGP0BREADY_in = (SAXIGP0BREADY !== 1'bz) && SAXIGP0BREADY_delay; // rv 0 + assign SAXIGP0RCLK_in = (SAXIGP0RCLK !== 1'bz) && SAXIGP0RCLK_delay; // rv 0 + assign SAXIGP0RREADY_in = (SAXIGP0RREADY !== 1'bz) && SAXIGP0RREADY_delay; // rv 0 + assign SAXIGP0WCLK_in = (SAXIGP0WCLK !== 1'bz) && SAXIGP0WCLK_delay; // rv 0 + assign SAXIGP0WDATA_in[0] = (SAXIGP0WDATA[0] !== 1'bz) && SAXIGP0WDATA_delay[0]; // rv 0 + assign SAXIGP0WDATA_in[100] = (SAXIGP0WDATA[100] !== 1'bz) && SAXIGP0WDATA_delay[100]; // rv 0 + assign SAXIGP0WDATA_in[101] = (SAXIGP0WDATA[101] !== 1'bz) && SAXIGP0WDATA_delay[101]; // rv 0 + assign SAXIGP0WDATA_in[102] = (SAXIGP0WDATA[102] !== 1'bz) && SAXIGP0WDATA_delay[102]; // rv 0 + assign SAXIGP0WDATA_in[103] = (SAXIGP0WDATA[103] !== 1'bz) && SAXIGP0WDATA_delay[103]; // rv 0 + assign SAXIGP0WDATA_in[104] = (SAXIGP0WDATA[104] !== 1'bz) && SAXIGP0WDATA_delay[104]; // rv 0 + assign SAXIGP0WDATA_in[105] = (SAXIGP0WDATA[105] !== 1'bz) && SAXIGP0WDATA_delay[105]; // rv 0 + assign SAXIGP0WDATA_in[106] = (SAXIGP0WDATA[106] !== 1'bz) && SAXIGP0WDATA_delay[106]; // rv 0 + assign SAXIGP0WDATA_in[107] = (SAXIGP0WDATA[107] !== 1'bz) && SAXIGP0WDATA_delay[107]; // rv 0 + assign SAXIGP0WDATA_in[108] = (SAXIGP0WDATA[108] !== 1'bz) && SAXIGP0WDATA_delay[108]; // rv 0 + assign SAXIGP0WDATA_in[109] = (SAXIGP0WDATA[109] !== 1'bz) && SAXIGP0WDATA_delay[109]; // rv 0 + assign SAXIGP0WDATA_in[10] = (SAXIGP0WDATA[10] !== 1'bz) && SAXIGP0WDATA_delay[10]; // rv 0 + assign SAXIGP0WDATA_in[110] = (SAXIGP0WDATA[110] !== 1'bz) && SAXIGP0WDATA_delay[110]; // rv 0 + assign SAXIGP0WDATA_in[111] = (SAXIGP0WDATA[111] !== 1'bz) && SAXIGP0WDATA_delay[111]; // rv 0 + assign SAXIGP0WDATA_in[112] = (SAXIGP0WDATA[112] !== 1'bz) && SAXIGP0WDATA_delay[112]; // rv 0 + assign SAXIGP0WDATA_in[113] = (SAXIGP0WDATA[113] !== 1'bz) && SAXIGP0WDATA_delay[113]; // rv 0 + assign SAXIGP0WDATA_in[114] = (SAXIGP0WDATA[114] !== 1'bz) && SAXIGP0WDATA_delay[114]; // rv 0 + assign SAXIGP0WDATA_in[115] = (SAXIGP0WDATA[115] !== 1'bz) && SAXIGP0WDATA_delay[115]; // rv 0 + assign SAXIGP0WDATA_in[116] = (SAXIGP0WDATA[116] !== 1'bz) && SAXIGP0WDATA_delay[116]; // rv 0 + assign SAXIGP0WDATA_in[117] = (SAXIGP0WDATA[117] !== 1'bz) && SAXIGP0WDATA_delay[117]; // rv 0 + assign SAXIGP0WDATA_in[118] = (SAXIGP0WDATA[118] !== 1'bz) && SAXIGP0WDATA_delay[118]; // rv 0 + assign SAXIGP0WDATA_in[119] = (SAXIGP0WDATA[119] !== 1'bz) && SAXIGP0WDATA_delay[119]; // rv 0 + assign SAXIGP0WDATA_in[11] = (SAXIGP0WDATA[11] !== 1'bz) && SAXIGP0WDATA_delay[11]; // rv 0 + assign SAXIGP0WDATA_in[120] = (SAXIGP0WDATA[120] !== 1'bz) && SAXIGP0WDATA_delay[120]; // rv 0 + assign SAXIGP0WDATA_in[121] = (SAXIGP0WDATA[121] !== 1'bz) && SAXIGP0WDATA_delay[121]; // rv 0 + assign SAXIGP0WDATA_in[122] = (SAXIGP0WDATA[122] !== 1'bz) && SAXIGP0WDATA_delay[122]; // rv 0 + assign SAXIGP0WDATA_in[123] = (SAXIGP0WDATA[123] !== 1'bz) && SAXIGP0WDATA_delay[123]; // rv 0 + assign SAXIGP0WDATA_in[124] = (SAXIGP0WDATA[124] !== 1'bz) && SAXIGP0WDATA_delay[124]; // rv 0 + assign SAXIGP0WDATA_in[125] = (SAXIGP0WDATA[125] !== 1'bz) && SAXIGP0WDATA_delay[125]; // rv 0 + assign SAXIGP0WDATA_in[126] = (SAXIGP0WDATA[126] !== 1'bz) && SAXIGP0WDATA_delay[126]; // rv 0 + assign SAXIGP0WDATA_in[127] = (SAXIGP0WDATA[127] !== 1'bz) && SAXIGP0WDATA_delay[127]; // rv 0 + assign SAXIGP0WDATA_in[12] = (SAXIGP0WDATA[12] !== 1'bz) && SAXIGP0WDATA_delay[12]; // rv 0 + assign SAXIGP0WDATA_in[13] = (SAXIGP0WDATA[13] !== 1'bz) && SAXIGP0WDATA_delay[13]; // rv 0 + assign SAXIGP0WDATA_in[14] = (SAXIGP0WDATA[14] !== 1'bz) && SAXIGP0WDATA_delay[14]; // rv 0 + assign SAXIGP0WDATA_in[15] = (SAXIGP0WDATA[15] !== 1'bz) && SAXIGP0WDATA_delay[15]; // rv 0 + assign SAXIGP0WDATA_in[16] = (SAXIGP0WDATA[16] !== 1'bz) && SAXIGP0WDATA_delay[16]; // rv 0 + assign SAXIGP0WDATA_in[17] = (SAXIGP0WDATA[17] !== 1'bz) && SAXIGP0WDATA_delay[17]; // rv 0 + assign SAXIGP0WDATA_in[18] = (SAXIGP0WDATA[18] !== 1'bz) && SAXIGP0WDATA_delay[18]; // rv 0 + assign SAXIGP0WDATA_in[19] = (SAXIGP0WDATA[19] !== 1'bz) && SAXIGP0WDATA_delay[19]; // rv 0 + assign SAXIGP0WDATA_in[1] = (SAXIGP0WDATA[1] !== 1'bz) && SAXIGP0WDATA_delay[1]; // rv 0 + assign SAXIGP0WDATA_in[20] = (SAXIGP0WDATA[20] !== 1'bz) && SAXIGP0WDATA_delay[20]; // rv 0 + assign SAXIGP0WDATA_in[21] = (SAXIGP0WDATA[21] !== 1'bz) && SAXIGP0WDATA_delay[21]; // rv 0 + assign SAXIGP0WDATA_in[22] = (SAXIGP0WDATA[22] !== 1'bz) && SAXIGP0WDATA_delay[22]; // rv 0 + assign SAXIGP0WDATA_in[23] = (SAXIGP0WDATA[23] !== 1'bz) && SAXIGP0WDATA_delay[23]; // rv 0 + assign SAXIGP0WDATA_in[24] = (SAXIGP0WDATA[24] !== 1'bz) && SAXIGP0WDATA_delay[24]; // rv 0 + assign SAXIGP0WDATA_in[25] = (SAXIGP0WDATA[25] !== 1'bz) && SAXIGP0WDATA_delay[25]; // rv 0 + assign SAXIGP0WDATA_in[26] = (SAXIGP0WDATA[26] !== 1'bz) && SAXIGP0WDATA_delay[26]; // rv 0 + assign SAXIGP0WDATA_in[27] = (SAXIGP0WDATA[27] !== 1'bz) && SAXIGP0WDATA_delay[27]; // rv 0 + assign SAXIGP0WDATA_in[28] = (SAXIGP0WDATA[28] !== 1'bz) && SAXIGP0WDATA_delay[28]; // rv 0 + assign SAXIGP0WDATA_in[29] = (SAXIGP0WDATA[29] !== 1'bz) && SAXIGP0WDATA_delay[29]; // rv 0 + assign SAXIGP0WDATA_in[2] = (SAXIGP0WDATA[2] !== 1'bz) && SAXIGP0WDATA_delay[2]; // rv 0 + assign SAXIGP0WDATA_in[30] = (SAXIGP0WDATA[30] !== 1'bz) && SAXIGP0WDATA_delay[30]; // rv 0 + assign SAXIGP0WDATA_in[31] = (SAXIGP0WDATA[31] !== 1'bz) && SAXIGP0WDATA_delay[31]; // rv 0 + assign SAXIGP0WDATA_in[32] = (SAXIGP0WDATA[32] !== 1'bz) && SAXIGP0WDATA_delay[32]; // rv 0 + assign SAXIGP0WDATA_in[33] = (SAXIGP0WDATA[33] !== 1'bz) && SAXIGP0WDATA_delay[33]; // rv 0 + assign SAXIGP0WDATA_in[34] = (SAXIGP0WDATA[34] !== 1'bz) && SAXIGP0WDATA_delay[34]; // rv 0 + assign SAXIGP0WDATA_in[35] = (SAXIGP0WDATA[35] !== 1'bz) && SAXIGP0WDATA_delay[35]; // rv 0 + assign SAXIGP0WDATA_in[36] = (SAXIGP0WDATA[36] !== 1'bz) && SAXIGP0WDATA_delay[36]; // rv 0 + assign SAXIGP0WDATA_in[37] = (SAXIGP0WDATA[37] !== 1'bz) && SAXIGP0WDATA_delay[37]; // rv 0 + assign SAXIGP0WDATA_in[38] = (SAXIGP0WDATA[38] !== 1'bz) && SAXIGP0WDATA_delay[38]; // rv 0 + assign SAXIGP0WDATA_in[39] = (SAXIGP0WDATA[39] !== 1'bz) && SAXIGP0WDATA_delay[39]; // rv 0 + assign SAXIGP0WDATA_in[3] = (SAXIGP0WDATA[3] !== 1'bz) && SAXIGP0WDATA_delay[3]; // rv 0 + assign SAXIGP0WDATA_in[40] = (SAXIGP0WDATA[40] !== 1'bz) && SAXIGP0WDATA_delay[40]; // rv 0 + assign SAXIGP0WDATA_in[41] = (SAXIGP0WDATA[41] !== 1'bz) && SAXIGP0WDATA_delay[41]; // rv 0 + assign SAXIGP0WDATA_in[42] = (SAXIGP0WDATA[42] !== 1'bz) && SAXIGP0WDATA_delay[42]; // rv 0 + assign SAXIGP0WDATA_in[43] = (SAXIGP0WDATA[43] !== 1'bz) && SAXIGP0WDATA_delay[43]; // rv 0 + assign SAXIGP0WDATA_in[44] = (SAXIGP0WDATA[44] !== 1'bz) && SAXIGP0WDATA_delay[44]; // rv 0 + assign SAXIGP0WDATA_in[45] = (SAXIGP0WDATA[45] !== 1'bz) && SAXIGP0WDATA_delay[45]; // rv 0 + assign SAXIGP0WDATA_in[46] = (SAXIGP0WDATA[46] !== 1'bz) && SAXIGP0WDATA_delay[46]; // rv 0 + assign SAXIGP0WDATA_in[47] = (SAXIGP0WDATA[47] !== 1'bz) && SAXIGP0WDATA_delay[47]; // rv 0 + assign SAXIGP0WDATA_in[48] = (SAXIGP0WDATA[48] !== 1'bz) && SAXIGP0WDATA_delay[48]; // rv 0 + assign SAXIGP0WDATA_in[49] = (SAXIGP0WDATA[49] !== 1'bz) && SAXIGP0WDATA_delay[49]; // rv 0 + assign SAXIGP0WDATA_in[4] = (SAXIGP0WDATA[4] !== 1'bz) && SAXIGP0WDATA_delay[4]; // rv 0 + assign SAXIGP0WDATA_in[50] = (SAXIGP0WDATA[50] !== 1'bz) && SAXIGP0WDATA_delay[50]; // rv 0 + assign SAXIGP0WDATA_in[51] = (SAXIGP0WDATA[51] !== 1'bz) && SAXIGP0WDATA_delay[51]; // rv 0 + assign SAXIGP0WDATA_in[52] = (SAXIGP0WDATA[52] !== 1'bz) && SAXIGP0WDATA_delay[52]; // rv 0 + assign SAXIGP0WDATA_in[53] = (SAXIGP0WDATA[53] !== 1'bz) && SAXIGP0WDATA_delay[53]; // rv 0 + assign SAXIGP0WDATA_in[54] = (SAXIGP0WDATA[54] !== 1'bz) && SAXIGP0WDATA_delay[54]; // rv 0 + assign SAXIGP0WDATA_in[55] = (SAXIGP0WDATA[55] !== 1'bz) && SAXIGP0WDATA_delay[55]; // rv 0 + assign SAXIGP0WDATA_in[56] = (SAXIGP0WDATA[56] !== 1'bz) && SAXIGP0WDATA_delay[56]; // rv 0 + assign SAXIGP0WDATA_in[57] = (SAXIGP0WDATA[57] !== 1'bz) && SAXIGP0WDATA_delay[57]; // rv 0 + assign SAXIGP0WDATA_in[58] = (SAXIGP0WDATA[58] !== 1'bz) && SAXIGP0WDATA_delay[58]; // rv 0 + assign SAXIGP0WDATA_in[59] = (SAXIGP0WDATA[59] !== 1'bz) && SAXIGP0WDATA_delay[59]; // rv 0 + assign SAXIGP0WDATA_in[5] = (SAXIGP0WDATA[5] !== 1'bz) && SAXIGP0WDATA_delay[5]; // rv 0 + assign SAXIGP0WDATA_in[60] = (SAXIGP0WDATA[60] !== 1'bz) && SAXIGP0WDATA_delay[60]; // rv 0 + assign SAXIGP0WDATA_in[61] = (SAXIGP0WDATA[61] !== 1'bz) && SAXIGP0WDATA_delay[61]; // rv 0 + assign SAXIGP0WDATA_in[62] = (SAXIGP0WDATA[62] !== 1'bz) && SAXIGP0WDATA_delay[62]; // rv 0 + assign SAXIGP0WDATA_in[63] = (SAXIGP0WDATA[63] !== 1'bz) && SAXIGP0WDATA_delay[63]; // rv 0 + assign SAXIGP0WDATA_in[64] = (SAXIGP0WDATA[64] !== 1'bz) && SAXIGP0WDATA_delay[64]; // rv 0 + assign SAXIGP0WDATA_in[65] = (SAXIGP0WDATA[65] !== 1'bz) && SAXIGP0WDATA_delay[65]; // rv 0 + assign SAXIGP0WDATA_in[66] = (SAXIGP0WDATA[66] !== 1'bz) && SAXIGP0WDATA_delay[66]; // rv 0 + assign SAXIGP0WDATA_in[67] = (SAXIGP0WDATA[67] !== 1'bz) && SAXIGP0WDATA_delay[67]; // rv 0 + assign SAXIGP0WDATA_in[68] = (SAXIGP0WDATA[68] !== 1'bz) && SAXIGP0WDATA_delay[68]; // rv 0 + assign SAXIGP0WDATA_in[69] = (SAXIGP0WDATA[69] !== 1'bz) && SAXIGP0WDATA_delay[69]; // rv 0 + assign SAXIGP0WDATA_in[6] = (SAXIGP0WDATA[6] !== 1'bz) && SAXIGP0WDATA_delay[6]; // rv 0 + assign SAXIGP0WDATA_in[70] = (SAXIGP0WDATA[70] !== 1'bz) && SAXIGP0WDATA_delay[70]; // rv 0 + assign SAXIGP0WDATA_in[71] = (SAXIGP0WDATA[71] !== 1'bz) && SAXIGP0WDATA_delay[71]; // rv 0 + assign SAXIGP0WDATA_in[72] = (SAXIGP0WDATA[72] !== 1'bz) && SAXIGP0WDATA_delay[72]; // rv 0 + assign SAXIGP0WDATA_in[73] = (SAXIGP0WDATA[73] !== 1'bz) && SAXIGP0WDATA_delay[73]; // rv 0 + assign SAXIGP0WDATA_in[74] = (SAXIGP0WDATA[74] !== 1'bz) && SAXIGP0WDATA_delay[74]; // rv 0 + assign SAXIGP0WDATA_in[75] = (SAXIGP0WDATA[75] !== 1'bz) && SAXIGP0WDATA_delay[75]; // rv 0 + assign SAXIGP0WDATA_in[76] = (SAXIGP0WDATA[76] !== 1'bz) && SAXIGP0WDATA_delay[76]; // rv 0 + assign SAXIGP0WDATA_in[77] = (SAXIGP0WDATA[77] !== 1'bz) && SAXIGP0WDATA_delay[77]; // rv 0 + assign SAXIGP0WDATA_in[78] = (SAXIGP0WDATA[78] !== 1'bz) && SAXIGP0WDATA_delay[78]; // rv 0 + assign SAXIGP0WDATA_in[79] = (SAXIGP0WDATA[79] !== 1'bz) && SAXIGP0WDATA_delay[79]; // rv 0 + assign SAXIGP0WDATA_in[7] = (SAXIGP0WDATA[7] !== 1'bz) && SAXIGP0WDATA_delay[7]; // rv 0 + assign SAXIGP0WDATA_in[80] = (SAXIGP0WDATA[80] !== 1'bz) && SAXIGP0WDATA_delay[80]; // rv 0 + assign SAXIGP0WDATA_in[81] = (SAXIGP0WDATA[81] !== 1'bz) && SAXIGP0WDATA_delay[81]; // rv 0 + assign SAXIGP0WDATA_in[82] = (SAXIGP0WDATA[82] !== 1'bz) && SAXIGP0WDATA_delay[82]; // rv 0 + assign SAXIGP0WDATA_in[83] = (SAXIGP0WDATA[83] !== 1'bz) && SAXIGP0WDATA_delay[83]; // rv 0 + assign SAXIGP0WDATA_in[84] = (SAXIGP0WDATA[84] !== 1'bz) && SAXIGP0WDATA_delay[84]; // rv 0 + assign SAXIGP0WDATA_in[85] = (SAXIGP0WDATA[85] !== 1'bz) && SAXIGP0WDATA_delay[85]; // rv 0 + assign SAXIGP0WDATA_in[86] = (SAXIGP0WDATA[86] !== 1'bz) && SAXIGP0WDATA_delay[86]; // rv 0 + assign SAXIGP0WDATA_in[87] = (SAXIGP0WDATA[87] !== 1'bz) && SAXIGP0WDATA_delay[87]; // rv 0 + assign SAXIGP0WDATA_in[88] = (SAXIGP0WDATA[88] !== 1'bz) && SAXIGP0WDATA_delay[88]; // rv 0 + assign SAXIGP0WDATA_in[89] = (SAXIGP0WDATA[89] !== 1'bz) && SAXIGP0WDATA_delay[89]; // rv 0 + assign SAXIGP0WDATA_in[8] = (SAXIGP0WDATA[8] !== 1'bz) && SAXIGP0WDATA_delay[8]; // rv 0 + assign SAXIGP0WDATA_in[90] = (SAXIGP0WDATA[90] !== 1'bz) && SAXIGP0WDATA_delay[90]; // rv 0 + assign SAXIGP0WDATA_in[91] = (SAXIGP0WDATA[91] !== 1'bz) && SAXIGP0WDATA_delay[91]; // rv 0 + assign SAXIGP0WDATA_in[92] = (SAXIGP0WDATA[92] !== 1'bz) && SAXIGP0WDATA_delay[92]; // rv 0 + assign SAXIGP0WDATA_in[93] = (SAXIGP0WDATA[93] !== 1'bz) && SAXIGP0WDATA_delay[93]; // rv 0 + assign SAXIGP0WDATA_in[94] = (SAXIGP0WDATA[94] !== 1'bz) && SAXIGP0WDATA_delay[94]; // rv 0 + assign SAXIGP0WDATA_in[95] = (SAXIGP0WDATA[95] !== 1'bz) && SAXIGP0WDATA_delay[95]; // rv 0 + assign SAXIGP0WDATA_in[96] = (SAXIGP0WDATA[96] !== 1'bz) && SAXIGP0WDATA_delay[96]; // rv 0 + assign SAXIGP0WDATA_in[97] = (SAXIGP0WDATA[97] !== 1'bz) && SAXIGP0WDATA_delay[97]; // rv 0 + assign SAXIGP0WDATA_in[98] = (SAXIGP0WDATA[98] !== 1'bz) && SAXIGP0WDATA_delay[98]; // rv 0 + assign SAXIGP0WDATA_in[99] = (SAXIGP0WDATA[99] !== 1'bz) && SAXIGP0WDATA_delay[99]; // rv 0 + assign SAXIGP0WDATA_in[9] = (SAXIGP0WDATA[9] !== 1'bz) && SAXIGP0WDATA_delay[9]; // rv 0 + assign SAXIGP0WLAST_in = (SAXIGP0WLAST !== 1'bz) && SAXIGP0WLAST_delay; // rv 0 + assign SAXIGP0WSTRB_in[0] = (SAXIGP0WSTRB[0] !== 1'bz) && SAXIGP0WSTRB_delay[0]; // rv 0 + assign SAXIGP0WSTRB_in[10] = (SAXIGP0WSTRB[10] !== 1'bz) && SAXIGP0WSTRB_delay[10]; // rv 0 + assign SAXIGP0WSTRB_in[11] = (SAXIGP0WSTRB[11] !== 1'bz) && SAXIGP0WSTRB_delay[11]; // rv 0 + assign SAXIGP0WSTRB_in[12] = (SAXIGP0WSTRB[12] !== 1'bz) && SAXIGP0WSTRB_delay[12]; // rv 0 + assign SAXIGP0WSTRB_in[13] = (SAXIGP0WSTRB[13] !== 1'bz) && SAXIGP0WSTRB_delay[13]; // rv 0 + assign SAXIGP0WSTRB_in[14] = (SAXIGP0WSTRB[14] !== 1'bz) && SAXIGP0WSTRB_delay[14]; // rv 0 + assign SAXIGP0WSTRB_in[15] = (SAXIGP0WSTRB[15] !== 1'bz) && SAXIGP0WSTRB_delay[15]; // rv 0 + assign SAXIGP0WSTRB_in[1] = (SAXIGP0WSTRB[1] !== 1'bz) && SAXIGP0WSTRB_delay[1]; // rv 0 + assign SAXIGP0WSTRB_in[2] = (SAXIGP0WSTRB[2] !== 1'bz) && SAXIGP0WSTRB_delay[2]; // rv 0 + assign SAXIGP0WSTRB_in[3] = (SAXIGP0WSTRB[3] !== 1'bz) && SAXIGP0WSTRB_delay[3]; // rv 0 + assign SAXIGP0WSTRB_in[4] = (SAXIGP0WSTRB[4] !== 1'bz) && SAXIGP0WSTRB_delay[4]; // rv 0 + assign SAXIGP0WSTRB_in[5] = (SAXIGP0WSTRB[5] !== 1'bz) && SAXIGP0WSTRB_delay[5]; // rv 0 + assign SAXIGP0WSTRB_in[6] = (SAXIGP0WSTRB[6] !== 1'bz) && SAXIGP0WSTRB_delay[6]; // rv 0 + assign SAXIGP0WSTRB_in[7] = (SAXIGP0WSTRB[7] !== 1'bz) && SAXIGP0WSTRB_delay[7]; // rv 0 + assign SAXIGP0WSTRB_in[8] = (SAXIGP0WSTRB[8] !== 1'bz) && SAXIGP0WSTRB_delay[8]; // rv 0 + assign SAXIGP0WSTRB_in[9] = (SAXIGP0WSTRB[9] !== 1'bz) && SAXIGP0WSTRB_delay[9]; // rv 0 + assign SAXIGP0WVALID_in = (SAXIGP0WVALID !== 1'bz) && SAXIGP0WVALID_delay; // rv 0 + assign SAXIGP1ARADDR_in[0] = (SAXIGP1ARADDR[0] !== 1'bz) && SAXIGP1ARADDR_delay[0]; // rv 0 + assign SAXIGP1ARADDR_in[10] = (SAXIGP1ARADDR[10] !== 1'bz) && SAXIGP1ARADDR_delay[10]; // rv 0 + assign SAXIGP1ARADDR_in[11] = (SAXIGP1ARADDR[11] !== 1'bz) && SAXIGP1ARADDR_delay[11]; // rv 0 + assign SAXIGP1ARADDR_in[12] = (SAXIGP1ARADDR[12] !== 1'bz) && SAXIGP1ARADDR_delay[12]; // rv 0 + assign SAXIGP1ARADDR_in[13] = (SAXIGP1ARADDR[13] !== 1'bz) && SAXIGP1ARADDR_delay[13]; // rv 0 + assign SAXIGP1ARADDR_in[14] = (SAXIGP1ARADDR[14] !== 1'bz) && SAXIGP1ARADDR_delay[14]; // rv 0 + assign SAXIGP1ARADDR_in[15] = (SAXIGP1ARADDR[15] !== 1'bz) && SAXIGP1ARADDR_delay[15]; // rv 0 + assign SAXIGP1ARADDR_in[16] = (SAXIGP1ARADDR[16] !== 1'bz) && SAXIGP1ARADDR_delay[16]; // rv 0 + assign SAXIGP1ARADDR_in[17] = (SAXIGP1ARADDR[17] !== 1'bz) && SAXIGP1ARADDR_delay[17]; // rv 0 + assign SAXIGP1ARADDR_in[18] = (SAXIGP1ARADDR[18] !== 1'bz) && SAXIGP1ARADDR_delay[18]; // rv 0 + assign SAXIGP1ARADDR_in[19] = (SAXIGP1ARADDR[19] !== 1'bz) && SAXIGP1ARADDR_delay[19]; // rv 0 + assign SAXIGP1ARADDR_in[1] = (SAXIGP1ARADDR[1] !== 1'bz) && SAXIGP1ARADDR_delay[1]; // rv 0 + assign SAXIGP1ARADDR_in[20] = (SAXIGP1ARADDR[20] !== 1'bz) && SAXIGP1ARADDR_delay[20]; // rv 0 + assign SAXIGP1ARADDR_in[21] = (SAXIGP1ARADDR[21] !== 1'bz) && SAXIGP1ARADDR_delay[21]; // rv 0 + assign SAXIGP1ARADDR_in[22] = (SAXIGP1ARADDR[22] !== 1'bz) && SAXIGP1ARADDR_delay[22]; // rv 0 + assign SAXIGP1ARADDR_in[23] = (SAXIGP1ARADDR[23] !== 1'bz) && SAXIGP1ARADDR_delay[23]; // rv 0 + assign SAXIGP1ARADDR_in[24] = (SAXIGP1ARADDR[24] !== 1'bz) && SAXIGP1ARADDR_delay[24]; // rv 0 + assign SAXIGP1ARADDR_in[25] = (SAXIGP1ARADDR[25] !== 1'bz) && SAXIGP1ARADDR_delay[25]; // rv 0 + assign SAXIGP1ARADDR_in[26] = (SAXIGP1ARADDR[26] !== 1'bz) && SAXIGP1ARADDR_delay[26]; // rv 0 + assign SAXIGP1ARADDR_in[27] = (SAXIGP1ARADDR[27] !== 1'bz) && SAXIGP1ARADDR_delay[27]; // rv 0 + assign SAXIGP1ARADDR_in[28] = (SAXIGP1ARADDR[28] !== 1'bz) && SAXIGP1ARADDR_delay[28]; // rv 0 + assign SAXIGP1ARADDR_in[29] = (SAXIGP1ARADDR[29] !== 1'bz) && SAXIGP1ARADDR_delay[29]; // rv 0 + assign SAXIGP1ARADDR_in[2] = (SAXIGP1ARADDR[2] !== 1'bz) && SAXIGP1ARADDR_delay[2]; // rv 0 + assign SAXIGP1ARADDR_in[30] = (SAXIGP1ARADDR[30] !== 1'bz) && SAXIGP1ARADDR_delay[30]; // rv 0 + assign SAXIGP1ARADDR_in[31] = (SAXIGP1ARADDR[31] !== 1'bz) && SAXIGP1ARADDR_delay[31]; // rv 0 + assign SAXIGP1ARADDR_in[32] = (SAXIGP1ARADDR[32] !== 1'bz) && SAXIGP1ARADDR_delay[32]; // rv 0 + assign SAXIGP1ARADDR_in[33] = (SAXIGP1ARADDR[33] !== 1'bz) && SAXIGP1ARADDR_delay[33]; // rv 0 + assign SAXIGP1ARADDR_in[34] = (SAXIGP1ARADDR[34] !== 1'bz) && SAXIGP1ARADDR_delay[34]; // rv 0 + assign SAXIGP1ARADDR_in[35] = (SAXIGP1ARADDR[35] !== 1'bz) && SAXIGP1ARADDR_delay[35]; // rv 0 + assign SAXIGP1ARADDR_in[36] = (SAXIGP1ARADDR[36] !== 1'bz) && SAXIGP1ARADDR_delay[36]; // rv 0 + assign SAXIGP1ARADDR_in[37] = (SAXIGP1ARADDR[37] !== 1'bz) && SAXIGP1ARADDR_delay[37]; // rv 0 + assign SAXIGP1ARADDR_in[38] = (SAXIGP1ARADDR[38] !== 1'bz) && SAXIGP1ARADDR_delay[38]; // rv 0 + assign SAXIGP1ARADDR_in[39] = (SAXIGP1ARADDR[39] !== 1'bz) && SAXIGP1ARADDR_delay[39]; // rv 0 + assign SAXIGP1ARADDR_in[3] = (SAXIGP1ARADDR[3] !== 1'bz) && SAXIGP1ARADDR_delay[3]; // rv 0 + assign SAXIGP1ARADDR_in[40] = (SAXIGP1ARADDR[40] !== 1'bz) && SAXIGP1ARADDR_delay[40]; // rv 0 + assign SAXIGP1ARADDR_in[41] = (SAXIGP1ARADDR[41] !== 1'bz) && SAXIGP1ARADDR_delay[41]; // rv 0 + assign SAXIGP1ARADDR_in[42] = (SAXIGP1ARADDR[42] !== 1'bz) && SAXIGP1ARADDR_delay[42]; // rv 0 + assign SAXIGP1ARADDR_in[43] = (SAXIGP1ARADDR[43] !== 1'bz) && SAXIGP1ARADDR_delay[43]; // rv 0 + assign SAXIGP1ARADDR_in[44] = (SAXIGP1ARADDR[44] !== 1'bz) && SAXIGP1ARADDR_delay[44]; // rv 0 + assign SAXIGP1ARADDR_in[45] = (SAXIGP1ARADDR[45] !== 1'bz) && SAXIGP1ARADDR_delay[45]; // rv 0 + assign SAXIGP1ARADDR_in[46] = (SAXIGP1ARADDR[46] !== 1'bz) && SAXIGP1ARADDR_delay[46]; // rv 0 + assign SAXIGP1ARADDR_in[47] = (SAXIGP1ARADDR[47] !== 1'bz) && SAXIGP1ARADDR_delay[47]; // rv 0 + assign SAXIGP1ARADDR_in[48] = (SAXIGP1ARADDR[48] !== 1'bz) && SAXIGP1ARADDR_delay[48]; // rv 0 + assign SAXIGP1ARADDR_in[4] = (SAXIGP1ARADDR[4] !== 1'bz) && SAXIGP1ARADDR_delay[4]; // rv 0 + assign SAXIGP1ARADDR_in[5] = (SAXIGP1ARADDR[5] !== 1'bz) && SAXIGP1ARADDR_delay[5]; // rv 0 + assign SAXIGP1ARADDR_in[6] = (SAXIGP1ARADDR[6] !== 1'bz) && SAXIGP1ARADDR_delay[6]; // rv 0 + assign SAXIGP1ARADDR_in[7] = (SAXIGP1ARADDR[7] !== 1'bz) && SAXIGP1ARADDR_delay[7]; // rv 0 + assign SAXIGP1ARADDR_in[8] = (SAXIGP1ARADDR[8] !== 1'bz) && SAXIGP1ARADDR_delay[8]; // rv 0 + assign SAXIGP1ARADDR_in[9] = (SAXIGP1ARADDR[9] !== 1'bz) && SAXIGP1ARADDR_delay[9]; // rv 0 + assign SAXIGP1ARBURST_in[0] = (SAXIGP1ARBURST[0] !== 1'bz) && SAXIGP1ARBURST_delay[0]; // rv 0 + assign SAXIGP1ARBURST_in[1] = (SAXIGP1ARBURST[1] !== 1'bz) && SAXIGP1ARBURST_delay[1]; // rv 0 + assign SAXIGP1ARCACHE_in[0] = (SAXIGP1ARCACHE[0] !== 1'bz) && SAXIGP1ARCACHE_delay[0]; // rv 0 + assign SAXIGP1ARCACHE_in[1] = (SAXIGP1ARCACHE[1] !== 1'bz) && SAXIGP1ARCACHE_delay[1]; // rv 0 + assign SAXIGP1ARCACHE_in[2] = (SAXIGP1ARCACHE[2] !== 1'bz) && SAXIGP1ARCACHE_delay[2]; // rv 0 + assign SAXIGP1ARCACHE_in[3] = (SAXIGP1ARCACHE[3] !== 1'bz) && SAXIGP1ARCACHE_delay[3]; // rv 0 + assign SAXIGP1ARID_in[0] = (SAXIGP1ARID[0] !== 1'bz) && SAXIGP1ARID_delay[0]; // rv 0 + assign SAXIGP1ARID_in[1] = (SAXIGP1ARID[1] !== 1'bz) && SAXIGP1ARID_delay[1]; // rv 0 + assign SAXIGP1ARID_in[2] = (SAXIGP1ARID[2] !== 1'bz) && SAXIGP1ARID_delay[2]; // rv 0 + assign SAXIGP1ARID_in[3] = (SAXIGP1ARID[3] !== 1'bz) && SAXIGP1ARID_delay[3]; // rv 0 + assign SAXIGP1ARID_in[4] = (SAXIGP1ARID[4] !== 1'bz) && SAXIGP1ARID_delay[4]; // rv 0 + assign SAXIGP1ARID_in[5] = (SAXIGP1ARID[5] !== 1'bz) && SAXIGP1ARID_delay[5]; // rv 0 + assign SAXIGP1ARLEN_in[0] = (SAXIGP1ARLEN[0] !== 1'bz) && SAXIGP1ARLEN_delay[0]; // rv 0 + assign SAXIGP1ARLEN_in[1] = (SAXIGP1ARLEN[1] !== 1'bz) && SAXIGP1ARLEN_delay[1]; // rv 0 + assign SAXIGP1ARLEN_in[2] = (SAXIGP1ARLEN[2] !== 1'bz) && SAXIGP1ARLEN_delay[2]; // rv 0 + assign SAXIGP1ARLEN_in[3] = (SAXIGP1ARLEN[3] !== 1'bz) && SAXIGP1ARLEN_delay[3]; // rv 0 + assign SAXIGP1ARLEN_in[4] = (SAXIGP1ARLEN[4] !== 1'bz) && SAXIGP1ARLEN_delay[4]; // rv 0 + assign SAXIGP1ARLEN_in[5] = (SAXIGP1ARLEN[5] !== 1'bz) && SAXIGP1ARLEN_delay[5]; // rv 0 + assign SAXIGP1ARLEN_in[6] = (SAXIGP1ARLEN[6] !== 1'bz) && SAXIGP1ARLEN_delay[6]; // rv 0 + assign SAXIGP1ARLEN_in[7] = (SAXIGP1ARLEN[7] !== 1'bz) && SAXIGP1ARLEN_delay[7]; // rv 0 + assign SAXIGP1ARLOCK_in = (SAXIGP1ARLOCK !== 1'bz) && SAXIGP1ARLOCK_delay; // rv 0 + assign SAXIGP1ARPROT_in[0] = (SAXIGP1ARPROT[0] !== 1'bz) && SAXIGP1ARPROT_delay[0]; // rv 0 + assign SAXIGP1ARPROT_in[1] = (SAXIGP1ARPROT[1] !== 1'bz) && SAXIGP1ARPROT_delay[1]; // rv 0 + assign SAXIGP1ARPROT_in[2] = (SAXIGP1ARPROT[2] !== 1'bz) && SAXIGP1ARPROT_delay[2]; // rv 0 + assign SAXIGP1ARQOS_in[0] = (SAXIGP1ARQOS[0] !== 1'bz) && SAXIGP1ARQOS_delay[0]; // rv 0 + assign SAXIGP1ARQOS_in[1] = (SAXIGP1ARQOS[1] !== 1'bz) && SAXIGP1ARQOS_delay[1]; // rv 0 + assign SAXIGP1ARQOS_in[2] = (SAXIGP1ARQOS[2] !== 1'bz) && SAXIGP1ARQOS_delay[2]; // rv 0 + assign SAXIGP1ARQOS_in[3] = (SAXIGP1ARQOS[3] !== 1'bz) && SAXIGP1ARQOS_delay[3]; // rv 0 + assign SAXIGP1ARSIZE_in[0] = (SAXIGP1ARSIZE[0] !== 1'bz) && SAXIGP1ARSIZE_delay[0]; // rv 0 + assign SAXIGP1ARSIZE_in[1] = (SAXIGP1ARSIZE[1] !== 1'bz) && SAXIGP1ARSIZE_delay[1]; // rv 0 + assign SAXIGP1ARSIZE_in[2] = (SAXIGP1ARSIZE[2] !== 1'bz) && SAXIGP1ARSIZE_delay[2]; // rv 0 + assign SAXIGP1ARUSER_in = (SAXIGP1ARUSER !== 1'bz) && SAXIGP1ARUSER_delay; // rv 0 + assign SAXIGP1ARVALID_in = (SAXIGP1ARVALID !== 1'bz) && SAXIGP1ARVALID_delay; // rv 0 + assign SAXIGP1AWADDR_in[0] = (SAXIGP1AWADDR[0] !== 1'bz) && SAXIGP1AWADDR_delay[0]; // rv 0 + assign SAXIGP1AWADDR_in[10] = (SAXIGP1AWADDR[10] !== 1'bz) && SAXIGP1AWADDR_delay[10]; // rv 0 + assign SAXIGP1AWADDR_in[11] = (SAXIGP1AWADDR[11] !== 1'bz) && SAXIGP1AWADDR_delay[11]; // rv 0 + assign SAXIGP1AWADDR_in[12] = (SAXIGP1AWADDR[12] !== 1'bz) && SAXIGP1AWADDR_delay[12]; // rv 0 + assign SAXIGP1AWADDR_in[13] = (SAXIGP1AWADDR[13] !== 1'bz) && SAXIGP1AWADDR_delay[13]; // rv 0 + assign SAXIGP1AWADDR_in[14] = (SAXIGP1AWADDR[14] !== 1'bz) && SAXIGP1AWADDR_delay[14]; // rv 0 + assign SAXIGP1AWADDR_in[15] = (SAXIGP1AWADDR[15] !== 1'bz) && SAXIGP1AWADDR_delay[15]; // rv 0 + assign SAXIGP1AWADDR_in[16] = (SAXIGP1AWADDR[16] !== 1'bz) && SAXIGP1AWADDR_delay[16]; // rv 0 + assign SAXIGP1AWADDR_in[17] = (SAXIGP1AWADDR[17] !== 1'bz) && SAXIGP1AWADDR_delay[17]; // rv 0 + assign SAXIGP1AWADDR_in[18] = (SAXIGP1AWADDR[18] !== 1'bz) && SAXIGP1AWADDR_delay[18]; // rv 0 + assign SAXIGP1AWADDR_in[19] = (SAXIGP1AWADDR[19] !== 1'bz) && SAXIGP1AWADDR_delay[19]; // rv 0 + assign SAXIGP1AWADDR_in[1] = (SAXIGP1AWADDR[1] !== 1'bz) && SAXIGP1AWADDR_delay[1]; // rv 0 + assign SAXIGP1AWADDR_in[20] = (SAXIGP1AWADDR[20] !== 1'bz) && SAXIGP1AWADDR_delay[20]; // rv 0 + assign SAXIGP1AWADDR_in[21] = (SAXIGP1AWADDR[21] !== 1'bz) && SAXIGP1AWADDR_delay[21]; // rv 0 + assign SAXIGP1AWADDR_in[22] = (SAXIGP1AWADDR[22] !== 1'bz) && SAXIGP1AWADDR_delay[22]; // rv 0 + assign SAXIGP1AWADDR_in[23] = (SAXIGP1AWADDR[23] !== 1'bz) && SAXIGP1AWADDR_delay[23]; // rv 0 + assign SAXIGP1AWADDR_in[24] = (SAXIGP1AWADDR[24] !== 1'bz) && SAXIGP1AWADDR_delay[24]; // rv 0 + assign SAXIGP1AWADDR_in[25] = (SAXIGP1AWADDR[25] !== 1'bz) && SAXIGP1AWADDR_delay[25]; // rv 0 + assign SAXIGP1AWADDR_in[26] = (SAXIGP1AWADDR[26] !== 1'bz) && SAXIGP1AWADDR_delay[26]; // rv 0 + assign SAXIGP1AWADDR_in[27] = (SAXIGP1AWADDR[27] !== 1'bz) && SAXIGP1AWADDR_delay[27]; // rv 0 + assign SAXIGP1AWADDR_in[28] = (SAXIGP1AWADDR[28] !== 1'bz) && SAXIGP1AWADDR_delay[28]; // rv 0 + assign SAXIGP1AWADDR_in[29] = (SAXIGP1AWADDR[29] !== 1'bz) && SAXIGP1AWADDR_delay[29]; // rv 0 + assign SAXIGP1AWADDR_in[2] = (SAXIGP1AWADDR[2] !== 1'bz) && SAXIGP1AWADDR_delay[2]; // rv 0 + assign SAXIGP1AWADDR_in[30] = (SAXIGP1AWADDR[30] !== 1'bz) && SAXIGP1AWADDR_delay[30]; // rv 0 + assign SAXIGP1AWADDR_in[31] = (SAXIGP1AWADDR[31] !== 1'bz) && SAXIGP1AWADDR_delay[31]; // rv 0 + assign SAXIGP1AWADDR_in[32] = (SAXIGP1AWADDR[32] !== 1'bz) && SAXIGP1AWADDR_delay[32]; // rv 0 + assign SAXIGP1AWADDR_in[33] = (SAXIGP1AWADDR[33] !== 1'bz) && SAXIGP1AWADDR_delay[33]; // rv 0 + assign SAXIGP1AWADDR_in[34] = (SAXIGP1AWADDR[34] !== 1'bz) && SAXIGP1AWADDR_delay[34]; // rv 0 + assign SAXIGP1AWADDR_in[35] = (SAXIGP1AWADDR[35] !== 1'bz) && SAXIGP1AWADDR_delay[35]; // rv 0 + assign SAXIGP1AWADDR_in[36] = (SAXIGP1AWADDR[36] !== 1'bz) && SAXIGP1AWADDR_delay[36]; // rv 0 + assign SAXIGP1AWADDR_in[37] = (SAXIGP1AWADDR[37] !== 1'bz) && SAXIGP1AWADDR_delay[37]; // rv 0 + assign SAXIGP1AWADDR_in[38] = (SAXIGP1AWADDR[38] !== 1'bz) && SAXIGP1AWADDR_delay[38]; // rv 0 + assign SAXIGP1AWADDR_in[39] = (SAXIGP1AWADDR[39] !== 1'bz) && SAXIGP1AWADDR_delay[39]; // rv 0 + assign SAXIGP1AWADDR_in[3] = (SAXIGP1AWADDR[3] !== 1'bz) && SAXIGP1AWADDR_delay[3]; // rv 0 + assign SAXIGP1AWADDR_in[40] = (SAXIGP1AWADDR[40] !== 1'bz) && SAXIGP1AWADDR_delay[40]; // rv 0 + assign SAXIGP1AWADDR_in[41] = (SAXIGP1AWADDR[41] !== 1'bz) && SAXIGP1AWADDR_delay[41]; // rv 0 + assign SAXIGP1AWADDR_in[42] = (SAXIGP1AWADDR[42] !== 1'bz) && SAXIGP1AWADDR_delay[42]; // rv 0 + assign SAXIGP1AWADDR_in[43] = (SAXIGP1AWADDR[43] !== 1'bz) && SAXIGP1AWADDR_delay[43]; // rv 0 + assign SAXIGP1AWADDR_in[44] = (SAXIGP1AWADDR[44] !== 1'bz) && SAXIGP1AWADDR_delay[44]; // rv 0 + assign SAXIGP1AWADDR_in[45] = (SAXIGP1AWADDR[45] !== 1'bz) && SAXIGP1AWADDR_delay[45]; // rv 0 + assign SAXIGP1AWADDR_in[46] = (SAXIGP1AWADDR[46] !== 1'bz) && SAXIGP1AWADDR_delay[46]; // rv 0 + assign SAXIGP1AWADDR_in[47] = (SAXIGP1AWADDR[47] !== 1'bz) && SAXIGP1AWADDR_delay[47]; // rv 0 + assign SAXIGP1AWADDR_in[48] = (SAXIGP1AWADDR[48] !== 1'bz) && SAXIGP1AWADDR_delay[48]; // rv 0 + assign SAXIGP1AWADDR_in[4] = (SAXIGP1AWADDR[4] !== 1'bz) && SAXIGP1AWADDR_delay[4]; // rv 0 + assign SAXIGP1AWADDR_in[5] = (SAXIGP1AWADDR[5] !== 1'bz) && SAXIGP1AWADDR_delay[5]; // rv 0 + assign SAXIGP1AWADDR_in[6] = (SAXIGP1AWADDR[6] !== 1'bz) && SAXIGP1AWADDR_delay[6]; // rv 0 + assign SAXIGP1AWADDR_in[7] = (SAXIGP1AWADDR[7] !== 1'bz) && SAXIGP1AWADDR_delay[7]; // rv 0 + assign SAXIGP1AWADDR_in[8] = (SAXIGP1AWADDR[8] !== 1'bz) && SAXIGP1AWADDR_delay[8]; // rv 0 + assign SAXIGP1AWADDR_in[9] = (SAXIGP1AWADDR[9] !== 1'bz) && SAXIGP1AWADDR_delay[9]; // rv 0 + assign SAXIGP1AWBURST_in[0] = (SAXIGP1AWBURST[0] !== 1'bz) && SAXIGP1AWBURST_delay[0]; // rv 0 + assign SAXIGP1AWBURST_in[1] = (SAXIGP1AWBURST[1] !== 1'bz) && SAXIGP1AWBURST_delay[1]; // rv 0 + assign SAXIGP1AWCACHE_in[0] = (SAXIGP1AWCACHE[0] !== 1'bz) && SAXIGP1AWCACHE_delay[0]; // rv 0 + assign SAXIGP1AWCACHE_in[1] = (SAXIGP1AWCACHE[1] !== 1'bz) && SAXIGP1AWCACHE_delay[1]; // rv 0 + assign SAXIGP1AWCACHE_in[2] = (SAXIGP1AWCACHE[2] !== 1'bz) && SAXIGP1AWCACHE_delay[2]; // rv 0 + assign SAXIGP1AWCACHE_in[3] = (SAXIGP1AWCACHE[3] !== 1'bz) && SAXIGP1AWCACHE_delay[3]; // rv 0 + assign SAXIGP1AWID_in[0] = (SAXIGP1AWID[0] !== 1'bz) && SAXIGP1AWID_delay[0]; // rv 0 + assign SAXIGP1AWID_in[1] = (SAXIGP1AWID[1] !== 1'bz) && SAXIGP1AWID_delay[1]; // rv 0 + assign SAXIGP1AWID_in[2] = (SAXIGP1AWID[2] !== 1'bz) && SAXIGP1AWID_delay[2]; // rv 0 + assign SAXIGP1AWID_in[3] = (SAXIGP1AWID[3] !== 1'bz) && SAXIGP1AWID_delay[3]; // rv 0 + assign SAXIGP1AWID_in[4] = (SAXIGP1AWID[4] !== 1'bz) && SAXIGP1AWID_delay[4]; // rv 0 + assign SAXIGP1AWID_in[5] = (SAXIGP1AWID[5] !== 1'bz) && SAXIGP1AWID_delay[5]; // rv 0 + assign SAXIGP1AWLEN_in[0] = (SAXIGP1AWLEN[0] !== 1'bz) && SAXIGP1AWLEN_delay[0]; // rv 0 + assign SAXIGP1AWLEN_in[1] = (SAXIGP1AWLEN[1] !== 1'bz) && SAXIGP1AWLEN_delay[1]; // rv 0 + assign SAXIGP1AWLEN_in[2] = (SAXIGP1AWLEN[2] !== 1'bz) && SAXIGP1AWLEN_delay[2]; // rv 0 + assign SAXIGP1AWLEN_in[3] = (SAXIGP1AWLEN[3] !== 1'bz) && SAXIGP1AWLEN_delay[3]; // rv 0 + assign SAXIGP1AWLEN_in[4] = (SAXIGP1AWLEN[4] !== 1'bz) && SAXIGP1AWLEN_delay[4]; // rv 0 + assign SAXIGP1AWLEN_in[5] = (SAXIGP1AWLEN[5] !== 1'bz) && SAXIGP1AWLEN_delay[5]; // rv 0 + assign SAXIGP1AWLEN_in[6] = (SAXIGP1AWLEN[6] !== 1'bz) && SAXIGP1AWLEN_delay[6]; // rv 0 + assign SAXIGP1AWLEN_in[7] = (SAXIGP1AWLEN[7] !== 1'bz) && SAXIGP1AWLEN_delay[7]; // rv 0 + assign SAXIGP1AWLOCK_in = (SAXIGP1AWLOCK !== 1'bz) && SAXIGP1AWLOCK_delay; // rv 0 + assign SAXIGP1AWPROT_in[0] = (SAXIGP1AWPROT[0] !== 1'bz) && SAXIGP1AWPROT_delay[0]; // rv 0 + assign SAXIGP1AWPROT_in[1] = (SAXIGP1AWPROT[1] !== 1'bz) && SAXIGP1AWPROT_delay[1]; // rv 0 + assign SAXIGP1AWPROT_in[2] = (SAXIGP1AWPROT[2] !== 1'bz) && SAXIGP1AWPROT_delay[2]; // rv 0 + assign SAXIGP1AWQOS_in[0] = (SAXIGP1AWQOS[0] !== 1'bz) && SAXIGP1AWQOS_delay[0]; // rv 0 + assign SAXIGP1AWQOS_in[1] = (SAXIGP1AWQOS[1] !== 1'bz) && SAXIGP1AWQOS_delay[1]; // rv 0 + assign SAXIGP1AWQOS_in[2] = (SAXIGP1AWQOS[2] !== 1'bz) && SAXIGP1AWQOS_delay[2]; // rv 0 + assign SAXIGP1AWQOS_in[3] = (SAXIGP1AWQOS[3] !== 1'bz) && SAXIGP1AWQOS_delay[3]; // rv 0 + assign SAXIGP1AWSIZE_in[0] = (SAXIGP1AWSIZE[0] !== 1'bz) && SAXIGP1AWSIZE_delay[0]; // rv 0 + assign SAXIGP1AWSIZE_in[1] = (SAXIGP1AWSIZE[1] !== 1'bz) && SAXIGP1AWSIZE_delay[1]; // rv 0 + assign SAXIGP1AWSIZE_in[2] = (SAXIGP1AWSIZE[2] !== 1'bz) && SAXIGP1AWSIZE_delay[2]; // rv 0 + assign SAXIGP1AWUSER_in = (SAXIGP1AWUSER !== 1'bz) && SAXIGP1AWUSER_delay; // rv 0 + assign SAXIGP1AWVALID_in = (SAXIGP1AWVALID !== 1'bz) && SAXIGP1AWVALID_delay; // rv 0 + assign SAXIGP1BREADY_in = (SAXIGP1BREADY !== 1'bz) && SAXIGP1BREADY_delay; // rv 0 + assign SAXIGP1RCLK_in = (SAXIGP1RCLK !== 1'bz) && SAXIGP1RCLK_delay; // rv 0 + assign SAXIGP1RREADY_in = (SAXIGP1RREADY !== 1'bz) && SAXIGP1RREADY_delay; // rv 0 + assign SAXIGP1WCLK_in = (SAXIGP1WCLK !== 1'bz) && SAXIGP1WCLK_delay; // rv 0 + assign SAXIGP1WDATA_in[0] = (SAXIGP1WDATA[0] !== 1'bz) && SAXIGP1WDATA_delay[0]; // rv 0 + assign SAXIGP1WDATA_in[100] = (SAXIGP1WDATA[100] !== 1'bz) && SAXIGP1WDATA_delay[100]; // rv 0 + assign SAXIGP1WDATA_in[101] = (SAXIGP1WDATA[101] !== 1'bz) && SAXIGP1WDATA_delay[101]; // rv 0 + assign SAXIGP1WDATA_in[102] = (SAXIGP1WDATA[102] !== 1'bz) && SAXIGP1WDATA_delay[102]; // rv 0 + assign SAXIGP1WDATA_in[103] = (SAXIGP1WDATA[103] !== 1'bz) && SAXIGP1WDATA_delay[103]; // rv 0 + assign SAXIGP1WDATA_in[104] = (SAXIGP1WDATA[104] !== 1'bz) && SAXIGP1WDATA_delay[104]; // rv 0 + assign SAXIGP1WDATA_in[105] = (SAXIGP1WDATA[105] !== 1'bz) && SAXIGP1WDATA_delay[105]; // rv 0 + assign SAXIGP1WDATA_in[106] = (SAXIGP1WDATA[106] !== 1'bz) && SAXIGP1WDATA_delay[106]; // rv 0 + assign SAXIGP1WDATA_in[107] = (SAXIGP1WDATA[107] !== 1'bz) && SAXIGP1WDATA_delay[107]; // rv 0 + assign SAXIGP1WDATA_in[108] = (SAXIGP1WDATA[108] !== 1'bz) && SAXIGP1WDATA_delay[108]; // rv 0 + assign SAXIGP1WDATA_in[109] = (SAXIGP1WDATA[109] !== 1'bz) && SAXIGP1WDATA_delay[109]; // rv 0 + assign SAXIGP1WDATA_in[10] = (SAXIGP1WDATA[10] !== 1'bz) && SAXIGP1WDATA_delay[10]; // rv 0 + assign SAXIGP1WDATA_in[110] = (SAXIGP1WDATA[110] !== 1'bz) && SAXIGP1WDATA_delay[110]; // rv 0 + assign SAXIGP1WDATA_in[111] = (SAXIGP1WDATA[111] !== 1'bz) && SAXIGP1WDATA_delay[111]; // rv 0 + assign SAXIGP1WDATA_in[112] = (SAXIGP1WDATA[112] !== 1'bz) && SAXIGP1WDATA_delay[112]; // rv 0 + assign SAXIGP1WDATA_in[113] = (SAXIGP1WDATA[113] !== 1'bz) && SAXIGP1WDATA_delay[113]; // rv 0 + assign SAXIGP1WDATA_in[114] = (SAXIGP1WDATA[114] !== 1'bz) && SAXIGP1WDATA_delay[114]; // rv 0 + assign SAXIGP1WDATA_in[115] = (SAXIGP1WDATA[115] !== 1'bz) && SAXIGP1WDATA_delay[115]; // rv 0 + assign SAXIGP1WDATA_in[116] = (SAXIGP1WDATA[116] !== 1'bz) && SAXIGP1WDATA_delay[116]; // rv 0 + assign SAXIGP1WDATA_in[117] = (SAXIGP1WDATA[117] !== 1'bz) && SAXIGP1WDATA_delay[117]; // rv 0 + assign SAXIGP1WDATA_in[118] = (SAXIGP1WDATA[118] !== 1'bz) && SAXIGP1WDATA_delay[118]; // rv 0 + assign SAXIGP1WDATA_in[119] = (SAXIGP1WDATA[119] !== 1'bz) && SAXIGP1WDATA_delay[119]; // rv 0 + assign SAXIGP1WDATA_in[11] = (SAXIGP1WDATA[11] !== 1'bz) && SAXIGP1WDATA_delay[11]; // rv 0 + assign SAXIGP1WDATA_in[120] = (SAXIGP1WDATA[120] !== 1'bz) && SAXIGP1WDATA_delay[120]; // rv 0 + assign SAXIGP1WDATA_in[121] = (SAXIGP1WDATA[121] !== 1'bz) && SAXIGP1WDATA_delay[121]; // rv 0 + assign SAXIGP1WDATA_in[122] = (SAXIGP1WDATA[122] !== 1'bz) && SAXIGP1WDATA_delay[122]; // rv 0 + assign SAXIGP1WDATA_in[123] = (SAXIGP1WDATA[123] !== 1'bz) && SAXIGP1WDATA_delay[123]; // rv 0 + assign SAXIGP1WDATA_in[124] = (SAXIGP1WDATA[124] !== 1'bz) && SAXIGP1WDATA_delay[124]; // rv 0 + assign SAXIGP1WDATA_in[125] = (SAXIGP1WDATA[125] !== 1'bz) && SAXIGP1WDATA_delay[125]; // rv 0 + assign SAXIGP1WDATA_in[126] = (SAXIGP1WDATA[126] !== 1'bz) && SAXIGP1WDATA_delay[126]; // rv 0 + assign SAXIGP1WDATA_in[127] = (SAXIGP1WDATA[127] !== 1'bz) && SAXIGP1WDATA_delay[127]; // rv 0 + assign SAXIGP1WDATA_in[12] = (SAXIGP1WDATA[12] !== 1'bz) && SAXIGP1WDATA_delay[12]; // rv 0 + assign SAXIGP1WDATA_in[13] = (SAXIGP1WDATA[13] !== 1'bz) && SAXIGP1WDATA_delay[13]; // rv 0 + assign SAXIGP1WDATA_in[14] = (SAXIGP1WDATA[14] !== 1'bz) && SAXIGP1WDATA_delay[14]; // rv 0 + assign SAXIGP1WDATA_in[15] = (SAXIGP1WDATA[15] !== 1'bz) && SAXIGP1WDATA_delay[15]; // rv 0 + assign SAXIGP1WDATA_in[16] = (SAXIGP1WDATA[16] !== 1'bz) && SAXIGP1WDATA_delay[16]; // rv 0 + assign SAXIGP1WDATA_in[17] = (SAXIGP1WDATA[17] !== 1'bz) && SAXIGP1WDATA_delay[17]; // rv 0 + assign SAXIGP1WDATA_in[18] = (SAXIGP1WDATA[18] !== 1'bz) && SAXIGP1WDATA_delay[18]; // rv 0 + assign SAXIGP1WDATA_in[19] = (SAXIGP1WDATA[19] !== 1'bz) && SAXIGP1WDATA_delay[19]; // rv 0 + assign SAXIGP1WDATA_in[1] = (SAXIGP1WDATA[1] !== 1'bz) && SAXIGP1WDATA_delay[1]; // rv 0 + assign SAXIGP1WDATA_in[20] = (SAXIGP1WDATA[20] !== 1'bz) && SAXIGP1WDATA_delay[20]; // rv 0 + assign SAXIGP1WDATA_in[21] = (SAXIGP1WDATA[21] !== 1'bz) && SAXIGP1WDATA_delay[21]; // rv 0 + assign SAXIGP1WDATA_in[22] = (SAXIGP1WDATA[22] !== 1'bz) && SAXIGP1WDATA_delay[22]; // rv 0 + assign SAXIGP1WDATA_in[23] = (SAXIGP1WDATA[23] !== 1'bz) && SAXIGP1WDATA_delay[23]; // rv 0 + assign SAXIGP1WDATA_in[24] = (SAXIGP1WDATA[24] !== 1'bz) && SAXIGP1WDATA_delay[24]; // rv 0 + assign SAXIGP1WDATA_in[25] = (SAXIGP1WDATA[25] !== 1'bz) && SAXIGP1WDATA_delay[25]; // rv 0 + assign SAXIGP1WDATA_in[26] = (SAXIGP1WDATA[26] !== 1'bz) && SAXIGP1WDATA_delay[26]; // rv 0 + assign SAXIGP1WDATA_in[27] = (SAXIGP1WDATA[27] !== 1'bz) && SAXIGP1WDATA_delay[27]; // rv 0 + assign SAXIGP1WDATA_in[28] = (SAXIGP1WDATA[28] !== 1'bz) && SAXIGP1WDATA_delay[28]; // rv 0 + assign SAXIGP1WDATA_in[29] = (SAXIGP1WDATA[29] !== 1'bz) && SAXIGP1WDATA_delay[29]; // rv 0 + assign SAXIGP1WDATA_in[2] = (SAXIGP1WDATA[2] !== 1'bz) && SAXIGP1WDATA_delay[2]; // rv 0 + assign SAXIGP1WDATA_in[30] = (SAXIGP1WDATA[30] !== 1'bz) && SAXIGP1WDATA_delay[30]; // rv 0 + assign SAXIGP1WDATA_in[31] = (SAXIGP1WDATA[31] !== 1'bz) && SAXIGP1WDATA_delay[31]; // rv 0 + assign SAXIGP1WDATA_in[32] = (SAXIGP1WDATA[32] !== 1'bz) && SAXIGP1WDATA_delay[32]; // rv 0 + assign SAXIGP1WDATA_in[33] = (SAXIGP1WDATA[33] !== 1'bz) && SAXIGP1WDATA_delay[33]; // rv 0 + assign SAXIGP1WDATA_in[34] = (SAXIGP1WDATA[34] !== 1'bz) && SAXIGP1WDATA_delay[34]; // rv 0 + assign SAXIGP1WDATA_in[35] = (SAXIGP1WDATA[35] !== 1'bz) && SAXIGP1WDATA_delay[35]; // rv 0 + assign SAXIGP1WDATA_in[36] = (SAXIGP1WDATA[36] !== 1'bz) && SAXIGP1WDATA_delay[36]; // rv 0 + assign SAXIGP1WDATA_in[37] = (SAXIGP1WDATA[37] !== 1'bz) && SAXIGP1WDATA_delay[37]; // rv 0 + assign SAXIGP1WDATA_in[38] = (SAXIGP1WDATA[38] !== 1'bz) && SAXIGP1WDATA_delay[38]; // rv 0 + assign SAXIGP1WDATA_in[39] = (SAXIGP1WDATA[39] !== 1'bz) && SAXIGP1WDATA_delay[39]; // rv 0 + assign SAXIGP1WDATA_in[3] = (SAXIGP1WDATA[3] !== 1'bz) && SAXIGP1WDATA_delay[3]; // rv 0 + assign SAXIGP1WDATA_in[40] = (SAXIGP1WDATA[40] !== 1'bz) && SAXIGP1WDATA_delay[40]; // rv 0 + assign SAXIGP1WDATA_in[41] = (SAXIGP1WDATA[41] !== 1'bz) && SAXIGP1WDATA_delay[41]; // rv 0 + assign SAXIGP1WDATA_in[42] = (SAXIGP1WDATA[42] !== 1'bz) && SAXIGP1WDATA_delay[42]; // rv 0 + assign SAXIGP1WDATA_in[43] = (SAXIGP1WDATA[43] !== 1'bz) && SAXIGP1WDATA_delay[43]; // rv 0 + assign SAXIGP1WDATA_in[44] = (SAXIGP1WDATA[44] !== 1'bz) && SAXIGP1WDATA_delay[44]; // rv 0 + assign SAXIGP1WDATA_in[45] = (SAXIGP1WDATA[45] !== 1'bz) && SAXIGP1WDATA_delay[45]; // rv 0 + assign SAXIGP1WDATA_in[46] = (SAXIGP1WDATA[46] !== 1'bz) && SAXIGP1WDATA_delay[46]; // rv 0 + assign SAXIGP1WDATA_in[47] = (SAXIGP1WDATA[47] !== 1'bz) && SAXIGP1WDATA_delay[47]; // rv 0 + assign SAXIGP1WDATA_in[48] = (SAXIGP1WDATA[48] !== 1'bz) && SAXIGP1WDATA_delay[48]; // rv 0 + assign SAXIGP1WDATA_in[49] = (SAXIGP1WDATA[49] !== 1'bz) && SAXIGP1WDATA_delay[49]; // rv 0 + assign SAXIGP1WDATA_in[4] = (SAXIGP1WDATA[4] !== 1'bz) && SAXIGP1WDATA_delay[4]; // rv 0 + assign SAXIGP1WDATA_in[50] = (SAXIGP1WDATA[50] !== 1'bz) && SAXIGP1WDATA_delay[50]; // rv 0 + assign SAXIGP1WDATA_in[51] = (SAXIGP1WDATA[51] !== 1'bz) && SAXIGP1WDATA_delay[51]; // rv 0 + assign SAXIGP1WDATA_in[52] = (SAXIGP1WDATA[52] !== 1'bz) && SAXIGP1WDATA_delay[52]; // rv 0 + assign SAXIGP1WDATA_in[53] = (SAXIGP1WDATA[53] !== 1'bz) && SAXIGP1WDATA_delay[53]; // rv 0 + assign SAXIGP1WDATA_in[54] = (SAXIGP1WDATA[54] !== 1'bz) && SAXIGP1WDATA_delay[54]; // rv 0 + assign SAXIGP1WDATA_in[55] = (SAXIGP1WDATA[55] !== 1'bz) && SAXIGP1WDATA_delay[55]; // rv 0 + assign SAXIGP1WDATA_in[56] = (SAXIGP1WDATA[56] !== 1'bz) && SAXIGP1WDATA_delay[56]; // rv 0 + assign SAXIGP1WDATA_in[57] = (SAXIGP1WDATA[57] !== 1'bz) && SAXIGP1WDATA_delay[57]; // rv 0 + assign SAXIGP1WDATA_in[58] = (SAXIGP1WDATA[58] !== 1'bz) && SAXIGP1WDATA_delay[58]; // rv 0 + assign SAXIGP1WDATA_in[59] = (SAXIGP1WDATA[59] !== 1'bz) && SAXIGP1WDATA_delay[59]; // rv 0 + assign SAXIGP1WDATA_in[5] = (SAXIGP1WDATA[5] !== 1'bz) && SAXIGP1WDATA_delay[5]; // rv 0 + assign SAXIGP1WDATA_in[60] = (SAXIGP1WDATA[60] !== 1'bz) && SAXIGP1WDATA_delay[60]; // rv 0 + assign SAXIGP1WDATA_in[61] = (SAXIGP1WDATA[61] !== 1'bz) && SAXIGP1WDATA_delay[61]; // rv 0 + assign SAXIGP1WDATA_in[62] = (SAXIGP1WDATA[62] !== 1'bz) && SAXIGP1WDATA_delay[62]; // rv 0 + assign SAXIGP1WDATA_in[63] = (SAXIGP1WDATA[63] !== 1'bz) && SAXIGP1WDATA_delay[63]; // rv 0 + assign SAXIGP1WDATA_in[64] = (SAXIGP1WDATA[64] !== 1'bz) && SAXIGP1WDATA_delay[64]; // rv 0 + assign SAXIGP1WDATA_in[65] = (SAXIGP1WDATA[65] !== 1'bz) && SAXIGP1WDATA_delay[65]; // rv 0 + assign SAXIGP1WDATA_in[66] = (SAXIGP1WDATA[66] !== 1'bz) && SAXIGP1WDATA_delay[66]; // rv 0 + assign SAXIGP1WDATA_in[67] = (SAXIGP1WDATA[67] !== 1'bz) && SAXIGP1WDATA_delay[67]; // rv 0 + assign SAXIGP1WDATA_in[68] = (SAXIGP1WDATA[68] !== 1'bz) && SAXIGP1WDATA_delay[68]; // rv 0 + assign SAXIGP1WDATA_in[69] = (SAXIGP1WDATA[69] !== 1'bz) && SAXIGP1WDATA_delay[69]; // rv 0 + assign SAXIGP1WDATA_in[6] = (SAXIGP1WDATA[6] !== 1'bz) && SAXIGP1WDATA_delay[6]; // rv 0 + assign SAXIGP1WDATA_in[70] = (SAXIGP1WDATA[70] !== 1'bz) && SAXIGP1WDATA_delay[70]; // rv 0 + assign SAXIGP1WDATA_in[71] = (SAXIGP1WDATA[71] !== 1'bz) && SAXIGP1WDATA_delay[71]; // rv 0 + assign SAXIGP1WDATA_in[72] = (SAXIGP1WDATA[72] !== 1'bz) && SAXIGP1WDATA_delay[72]; // rv 0 + assign SAXIGP1WDATA_in[73] = (SAXIGP1WDATA[73] !== 1'bz) && SAXIGP1WDATA_delay[73]; // rv 0 + assign SAXIGP1WDATA_in[74] = (SAXIGP1WDATA[74] !== 1'bz) && SAXIGP1WDATA_delay[74]; // rv 0 + assign SAXIGP1WDATA_in[75] = (SAXIGP1WDATA[75] !== 1'bz) && SAXIGP1WDATA_delay[75]; // rv 0 + assign SAXIGP1WDATA_in[76] = (SAXIGP1WDATA[76] !== 1'bz) && SAXIGP1WDATA_delay[76]; // rv 0 + assign SAXIGP1WDATA_in[77] = (SAXIGP1WDATA[77] !== 1'bz) && SAXIGP1WDATA_delay[77]; // rv 0 + assign SAXIGP1WDATA_in[78] = (SAXIGP1WDATA[78] !== 1'bz) && SAXIGP1WDATA_delay[78]; // rv 0 + assign SAXIGP1WDATA_in[79] = (SAXIGP1WDATA[79] !== 1'bz) && SAXIGP1WDATA_delay[79]; // rv 0 + assign SAXIGP1WDATA_in[7] = (SAXIGP1WDATA[7] !== 1'bz) && SAXIGP1WDATA_delay[7]; // rv 0 + assign SAXIGP1WDATA_in[80] = (SAXIGP1WDATA[80] !== 1'bz) && SAXIGP1WDATA_delay[80]; // rv 0 + assign SAXIGP1WDATA_in[81] = (SAXIGP1WDATA[81] !== 1'bz) && SAXIGP1WDATA_delay[81]; // rv 0 + assign SAXIGP1WDATA_in[82] = (SAXIGP1WDATA[82] !== 1'bz) && SAXIGP1WDATA_delay[82]; // rv 0 + assign SAXIGP1WDATA_in[83] = (SAXIGP1WDATA[83] !== 1'bz) && SAXIGP1WDATA_delay[83]; // rv 0 + assign SAXIGP1WDATA_in[84] = (SAXIGP1WDATA[84] !== 1'bz) && SAXIGP1WDATA_delay[84]; // rv 0 + assign SAXIGP1WDATA_in[85] = (SAXIGP1WDATA[85] !== 1'bz) && SAXIGP1WDATA_delay[85]; // rv 0 + assign SAXIGP1WDATA_in[86] = (SAXIGP1WDATA[86] !== 1'bz) && SAXIGP1WDATA_delay[86]; // rv 0 + assign SAXIGP1WDATA_in[87] = (SAXIGP1WDATA[87] !== 1'bz) && SAXIGP1WDATA_delay[87]; // rv 0 + assign SAXIGP1WDATA_in[88] = (SAXIGP1WDATA[88] !== 1'bz) && SAXIGP1WDATA_delay[88]; // rv 0 + assign SAXIGP1WDATA_in[89] = (SAXIGP1WDATA[89] !== 1'bz) && SAXIGP1WDATA_delay[89]; // rv 0 + assign SAXIGP1WDATA_in[8] = (SAXIGP1WDATA[8] !== 1'bz) && SAXIGP1WDATA_delay[8]; // rv 0 + assign SAXIGP1WDATA_in[90] = (SAXIGP1WDATA[90] !== 1'bz) && SAXIGP1WDATA_delay[90]; // rv 0 + assign SAXIGP1WDATA_in[91] = (SAXIGP1WDATA[91] !== 1'bz) && SAXIGP1WDATA_delay[91]; // rv 0 + assign SAXIGP1WDATA_in[92] = (SAXIGP1WDATA[92] !== 1'bz) && SAXIGP1WDATA_delay[92]; // rv 0 + assign SAXIGP1WDATA_in[93] = (SAXIGP1WDATA[93] !== 1'bz) && SAXIGP1WDATA_delay[93]; // rv 0 + assign SAXIGP1WDATA_in[94] = (SAXIGP1WDATA[94] !== 1'bz) && SAXIGP1WDATA_delay[94]; // rv 0 + assign SAXIGP1WDATA_in[95] = (SAXIGP1WDATA[95] !== 1'bz) && SAXIGP1WDATA_delay[95]; // rv 0 + assign SAXIGP1WDATA_in[96] = (SAXIGP1WDATA[96] !== 1'bz) && SAXIGP1WDATA_delay[96]; // rv 0 + assign SAXIGP1WDATA_in[97] = (SAXIGP1WDATA[97] !== 1'bz) && SAXIGP1WDATA_delay[97]; // rv 0 + assign SAXIGP1WDATA_in[98] = (SAXIGP1WDATA[98] !== 1'bz) && SAXIGP1WDATA_delay[98]; // rv 0 + assign SAXIGP1WDATA_in[99] = (SAXIGP1WDATA[99] !== 1'bz) && SAXIGP1WDATA_delay[99]; // rv 0 + assign SAXIGP1WDATA_in[9] = (SAXIGP1WDATA[9] !== 1'bz) && SAXIGP1WDATA_delay[9]; // rv 0 + assign SAXIGP1WLAST_in = (SAXIGP1WLAST !== 1'bz) && SAXIGP1WLAST_delay; // rv 0 + assign SAXIGP1WSTRB_in[0] = (SAXIGP1WSTRB[0] !== 1'bz) && SAXIGP1WSTRB_delay[0]; // rv 0 + assign SAXIGP1WSTRB_in[10] = (SAXIGP1WSTRB[10] !== 1'bz) && SAXIGP1WSTRB_delay[10]; // rv 0 + assign SAXIGP1WSTRB_in[11] = (SAXIGP1WSTRB[11] !== 1'bz) && SAXIGP1WSTRB_delay[11]; // rv 0 + assign SAXIGP1WSTRB_in[12] = (SAXIGP1WSTRB[12] !== 1'bz) && SAXIGP1WSTRB_delay[12]; // rv 0 + assign SAXIGP1WSTRB_in[13] = (SAXIGP1WSTRB[13] !== 1'bz) && SAXIGP1WSTRB_delay[13]; // rv 0 + assign SAXIGP1WSTRB_in[14] = (SAXIGP1WSTRB[14] !== 1'bz) && SAXIGP1WSTRB_delay[14]; // rv 0 + assign SAXIGP1WSTRB_in[15] = (SAXIGP1WSTRB[15] !== 1'bz) && SAXIGP1WSTRB_delay[15]; // rv 0 + assign SAXIGP1WSTRB_in[1] = (SAXIGP1WSTRB[1] !== 1'bz) && SAXIGP1WSTRB_delay[1]; // rv 0 + assign SAXIGP1WSTRB_in[2] = (SAXIGP1WSTRB[2] !== 1'bz) && SAXIGP1WSTRB_delay[2]; // rv 0 + assign SAXIGP1WSTRB_in[3] = (SAXIGP1WSTRB[3] !== 1'bz) && SAXIGP1WSTRB_delay[3]; // rv 0 + assign SAXIGP1WSTRB_in[4] = (SAXIGP1WSTRB[4] !== 1'bz) && SAXIGP1WSTRB_delay[4]; // rv 0 + assign SAXIGP1WSTRB_in[5] = (SAXIGP1WSTRB[5] !== 1'bz) && SAXIGP1WSTRB_delay[5]; // rv 0 + assign SAXIGP1WSTRB_in[6] = (SAXIGP1WSTRB[6] !== 1'bz) && SAXIGP1WSTRB_delay[6]; // rv 0 + assign SAXIGP1WSTRB_in[7] = (SAXIGP1WSTRB[7] !== 1'bz) && SAXIGP1WSTRB_delay[7]; // rv 0 + assign SAXIGP1WSTRB_in[8] = (SAXIGP1WSTRB[8] !== 1'bz) && SAXIGP1WSTRB_delay[8]; // rv 0 + assign SAXIGP1WSTRB_in[9] = (SAXIGP1WSTRB[9] !== 1'bz) && SAXIGP1WSTRB_delay[9]; // rv 0 + assign SAXIGP1WVALID_in = (SAXIGP1WVALID !== 1'bz) && SAXIGP1WVALID_delay; // rv 0 + assign SAXIGP2ARADDR_in[0] = (SAXIGP2ARADDR[0] !== 1'bz) && SAXIGP2ARADDR_delay[0]; // rv 0 + assign SAXIGP2ARADDR_in[10] = (SAXIGP2ARADDR[10] !== 1'bz) && SAXIGP2ARADDR_delay[10]; // rv 0 + assign SAXIGP2ARADDR_in[11] = (SAXIGP2ARADDR[11] !== 1'bz) && SAXIGP2ARADDR_delay[11]; // rv 0 + assign SAXIGP2ARADDR_in[12] = (SAXIGP2ARADDR[12] !== 1'bz) && SAXIGP2ARADDR_delay[12]; // rv 0 + assign SAXIGP2ARADDR_in[13] = (SAXIGP2ARADDR[13] !== 1'bz) && SAXIGP2ARADDR_delay[13]; // rv 0 + assign SAXIGP2ARADDR_in[14] = (SAXIGP2ARADDR[14] !== 1'bz) && SAXIGP2ARADDR_delay[14]; // rv 0 + assign SAXIGP2ARADDR_in[15] = (SAXIGP2ARADDR[15] !== 1'bz) && SAXIGP2ARADDR_delay[15]; // rv 0 + assign SAXIGP2ARADDR_in[16] = (SAXIGP2ARADDR[16] !== 1'bz) && SAXIGP2ARADDR_delay[16]; // rv 0 + assign SAXIGP2ARADDR_in[17] = (SAXIGP2ARADDR[17] !== 1'bz) && SAXIGP2ARADDR_delay[17]; // rv 0 + assign SAXIGP2ARADDR_in[18] = (SAXIGP2ARADDR[18] !== 1'bz) && SAXIGP2ARADDR_delay[18]; // rv 0 + assign SAXIGP2ARADDR_in[19] = (SAXIGP2ARADDR[19] !== 1'bz) && SAXIGP2ARADDR_delay[19]; // rv 0 + assign SAXIGP2ARADDR_in[1] = (SAXIGP2ARADDR[1] !== 1'bz) && SAXIGP2ARADDR_delay[1]; // rv 0 + assign SAXIGP2ARADDR_in[20] = (SAXIGP2ARADDR[20] !== 1'bz) && SAXIGP2ARADDR_delay[20]; // rv 0 + assign SAXIGP2ARADDR_in[21] = (SAXIGP2ARADDR[21] !== 1'bz) && SAXIGP2ARADDR_delay[21]; // rv 0 + assign SAXIGP2ARADDR_in[22] = (SAXIGP2ARADDR[22] !== 1'bz) && SAXIGP2ARADDR_delay[22]; // rv 0 + assign SAXIGP2ARADDR_in[23] = (SAXIGP2ARADDR[23] !== 1'bz) && SAXIGP2ARADDR_delay[23]; // rv 0 + assign SAXIGP2ARADDR_in[24] = (SAXIGP2ARADDR[24] !== 1'bz) && SAXIGP2ARADDR_delay[24]; // rv 0 + assign SAXIGP2ARADDR_in[25] = (SAXIGP2ARADDR[25] !== 1'bz) && SAXIGP2ARADDR_delay[25]; // rv 0 + assign SAXIGP2ARADDR_in[26] = (SAXIGP2ARADDR[26] !== 1'bz) && SAXIGP2ARADDR_delay[26]; // rv 0 + assign SAXIGP2ARADDR_in[27] = (SAXIGP2ARADDR[27] !== 1'bz) && SAXIGP2ARADDR_delay[27]; // rv 0 + assign SAXIGP2ARADDR_in[28] = (SAXIGP2ARADDR[28] !== 1'bz) && SAXIGP2ARADDR_delay[28]; // rv 0 + assign SAXIGP2ARADDR_in[29] = (SAXIGP2ARADDR[29] !== 1'bz) && SAXIGP2ARADDR_delay[29]; // rv 0 + assign SAXIGP2ARADDR_in[2] = (SAXIGP2ARADDR[2] !== 1'bz) && SAXIGP2ARADDR_delay[2]; // rv 0 + assign SAXIGP2ARADDR_in[30] = (SAXIGP2ARADDR[30] !== 1'bz) && SAXIGP2ARADDR_delay[30]; // rv 0 + assign SAXIGP2ARADDR_in[31] = (SAXIGP2ARADDR[31] !== 1'bz) && SAXIGP2ARADDR_delay[31]; // rv 0 + assign SAXIGP2ARADDR_in[32] = (SAXIGP2ARADDR[32] !== 1'bz) && SAXIGP2ARADDR_delay[32]; // rv 0 + assign SAXIGP2ARADDR_in[33] = (SAXIGP2ARADDR[33] !== 1'bz) && SAXIGP2ARADDR_delay[33]; // rv 0 + assign SAXIGP2ARADDR_in[34] = (SAXIGP2ARADDR[34] !== 1'bz) && SAXIGP2ARADDR_delay[34]; // rv 0 + assign SAXIGP2ARADDR_in[35] = (SAXIGP2ARADDR[35] !== 1'bz) && SAXIGP2ARADDR_delay[35]; // rv 0 + assign SAXIGP2ARADDR_in[36] = (SAXIGP2ARADDR[36] !== 1'bz) && SAXIGP2ARADDR_delay[36]; // rv 0 + assign SAXIGP2ARADDR_in[37] = (SAXIGP2ARADDR[37] !== 1'bz) && SAXIGP2ARADDR_delay[37]; // rv 0 + assign SAXIGP2ARADDR_in[38] = (SAXIGP2ARADDR[38] !== 1'bz) && SAXIGP2ARADDR_delay[38]; // rv 0 + assign SAXIGP2ARADDR_in[39] = (SAXIGP2ARADDR[39] !== 1'bz) && SAXIGP2ARADDR_delay[39]; // rv 0 + assign SAXIGP2ARADDR_in[3] = (SAXIGP2ARADDR[3] !== 1'bz) && SAXIGP2ARADDR_delay[3]; // rv 0 + assign SAXIGP2ARADDR_in[40] = (SAXIGP2ARADDR[40] !== 1'bz) && SAXIGP2ARADDR_delay[40]; // rv 0 + assign SAXIGP2ARADDR_in[41] = (SAXIGP2ARADDR[41] !== 1'bz) && SAXIGP2ARADDR_delay[41]; // rv 0 + assign SAXIGP2ARADDR_in[42] = (SAXIGP2ARADDR[42] !== 1'bz) && SAXIGP2ARADDR_delay[42]; // rv 0 + assign SAXIGP2ARADDR_in[43] = (SAXIGP2ARADDR[43] !== 1'bz) && SAXIGP2ARADDR_delay[43]; // rv 0 + assign SAXIGP2ARADDR_in[44] = (SAXIGP2ARADDR[44] !== 1'bz) && SAXIGP2ARADDR_delay[44]; // rv 0 + assign SAXIGP2ARADDR_in[45] = (SAXIGP2ARADDR[45] !== 1'bz) && SAXIGP2ARADDR_delay[45]; // rv 0 + assign SAXIGP2ARADDR_in[46] = (SAXIGP2ARADDR[46] !== 1'bz) && SAXIGP2ARADDR_delay[46]; // rv 0 + assign SAXIGP2ARADDR_in[47] = (SAXIGP2ARADDR[47] !== 1'bz) && SAXIGP2ARADDR_delay[47]; // rv 0 + assign SAXIGP2ARADDR_in[48] = (SAXIGP2ARADDR[48] !== 1'bz) && SAXIGP2ARADDR_delay[48]; // rv 0 + assign SAXIGP2ARADDR_in[4] = (SAXIGP2ARADDR[4] !== 1'bz) && SAXIGP2ARADDR_delay[4]; // rv 0 + assign SAXIGP2ARADDR_in[5] = (SAXIGP2ARADDR[5] !== 1'bz) && SAXIGP2ARADDR_delay[5]; // rv 0 + assign SAXIGP2ARADDR_in[6] = (SAXIGP2ARADDR[6] !== 1'bz) && SAXIGP2ARADDR_delay[6]; // rv 0 + assign SAXIGP2ARADDR_in[7] = (SAXIGP2ARADDR[7] !== 1'bz) && SAXIGP2ARADDR_delay[7]; // rv 0 + assign SAXIGP2ARADDR_in[8] = (SAXIGP2ARADDR[8] !== 1'bz) && SAXIGP2ARADDR_delay[8]; // rv 0 + assign SAXIGP2ARADDR_in[9] = (SAXIGP2ARADDR[9] !== 1'bz) && SAXIGP2ARADDR_delay[9]; // rv 0 + assign SAXIGP2ARBURST_in[0] = (SAXIGP2ARBURST[0] !== 1'bz) && SAXIGP2ARBURST_delay[0]; // rv 0 + assign SAXIGP2ARBURST_in[1] = (SAXIGP2ARBURST[1] !== 1'bz) && SAXIGP2ARBURST_delay[1]; // rv 0 + assign SAXIGP2ARCACHE_in[0] = (SAXIGP2ARCACHE[0] !== 1'bz) && SAXIGP2ARCACHE_delay[0]; // rv 0 + assign SAXIGP2ARCACHE_in[1] = (SAXIGP2ARCACHE[1] !== 1'bz) && SAXIGP2ARCACHE_delay[1]; // rv 0 + assign SAXIGP2ARCACHE_in[2] = (SAXIGP2ARCACHE[2] !== 1'bz) && SAXIGP2ARCACHE_delay[2]; // rv 0 + assign SAXIGP2ARCACHE_in[3] = (SAXIGP2ARCACHE[3] !== 1'bz) && SAXIGP2ARCACHE_delay[3]; // rv 0 + assign SAXIGP2ARID_in[0] = (SAXIGP2ARID[0] !== 1'bz) && SAXIGP2ARID_delay[0]; // rv 0 + assign SAXIGP2ARID_in[1] = (SAXIGP2ARID[1] !== 1'bz) && SAXIGP2ARID_delay[1]; // rv 0 + assign SAXIGP2ARID_in[2] = (SAXIGP2ARID[2] !== 1'bz) && SAXIGP2ARID_delay[2]; // rv 0 + assign SAXIGP2ARID_in[3] = (SAXIGP2ARID[3] !== 1'bz) && SAXIGP2ARID_delay[3]; // rv 0 + assign SAXIGP2ARID_in[4] = (SAXIGP2ARID[4] !== 1'bz) && SAXIGP2ARID_delay[4]; // rv 0 + assign SAXIGP2ARID_in[5] = (SAXIGP2ARID[5] !== 1'bz) && SAXIGP2ARID_delay[5]; // rv 0 + assign SAXIGP2ARLEN_in[0] = (SAXIGP2ARLEN[0] !== 1'bz) && SAXIGP2ARLEN_delay[0]; // rv 0 + assign SAXIGP2ARLEN_in[1] = (SAXIGP2ARLEN[1] !== 1'bz) && SAXIGP2ARLEN_delay[1]; // rv 0 + assign SAXIGP2ARLEN_in[2] = (SAXIGP2ARLEN[2] !== 1'bz) && SAXIGP2ARLEN_delay[2]; // rv 0 + assign SAXIGP2ARLEN_in[3] = (SAXIGP2ARLEN[3] !== 1'bz) && SAXIGP2ARLEN_delay[3]; // rv 0 + assign SAXIGP2ARLEN_in[4] = (SAXIGP2ARLEN[4] !== 1'bz) && SAXIGP2ARLEN_delay[4]; // rv 0 + assign SAXIGP2ARLEN_in[5] = (SAXIGP2ARLEN[5] !== 1'bz) && SAXIGP2ARLEN_delay[5]; // rv 0 + assign SAXIGP2ARLEN_in[6] = (SAXIGP2ARLEN[6] !== 1'bz) && SAXIGP2ARLEN_delay[6]; // rv 0 + assign SAXIGP2ARLEN_in[7] = (SAXIGP2ARLEN[7] !== 1'bz) && SAXIGP2ARLEN_delay[7]; // rv 0 + assign SAXIGP2ARLOCK_in = (SAXIGP2ARLOCK !== 1'bz) && SAXIGP2ARLOCK_delay; // rv 0 + assign SAXIGP2ARPROT_in[0] = (SAXIGP2ARPROT[0] !== 1'bz) && SAXIGP2ARPROT_delay[0]; // rv 0 + assign SAXIGP2ARPROT_in[1] = (SAXIGP2ARPROT[1] !== 1'bz) && SAXIGP2ARPROT_delay[1]; // rv 0 + assign SAXIGP2ARPROT_in[2] = (SAXIGP2ARPROT[2] !== 1'bz) && SAXIGP2ARPROT_delay[2]; // rv 0 + assign SAXIGP2ARQOS_in[0] = (SAXIGP2ARQOS[0] !== 1'bz) && SAXIGP2ARQOS_delay[0]; // rv 0 + assign SAXIGP2ARQOS_in[1] = (SAXIGP2ARQOS[1] !== 1'bz) && SAXIGP2ARQOS_delay[1]; // rv 0 + assign SAXIGP2ARQOS_in[2] = (SAXIGP2ARQOS[2] !== 1'bz) && SAXIGP2ARQOS_delay[2]; // rv 0 + assign SAXIGP2ARQOS_in[3] = (SAXIGP2ARQOS[3] !== 1'bz) && SAXIGP2ARQOS_delay[3]; // rv 0 + assign SAXIGP2ARSIZE_in[0] = (SAXIGP2ARSIZE[0] !== 1'bz) && SAXIGP2ARSIZE_delay[0]; // rv 0 + assign SAXIGP2ARSIZE_in[1] = (SAXIGP2ARSIZE[1] !== 1'bz) && SAXIGP2ARSIZE_delay[1]; // rv 0 + assign SAXIGP2ARSIZE_in[2] = (SAXIGP2ARSIZE[2] !== 1'bz) && SAXIGP2ARSIZE_delay[2]; // rv 0 + assign SAXIGP2ARUSER_in = (SAXIGP2ARUSER !== 1'bz) && SAXIGP2ARUSER_delay; // rv 0 + assign SAXIGP2ARVALID_in = (SAXIGP2ARVALID !== 1'bz) && SAXIGP2ARVALID_delay; // rv 0 + assign SAXIGP2AWADDR_in[0] = (SAXIGP2AWADDR[0] !== 1'bz) && SAXIGP2AWADDR_delay[0]; // rv 0 + assign SAXIGP2AWADDR_in[10] = (SAXIGP2AWADDR[10] !== 1'bz) && SAXIGP2AWADDR_delay[10]; // rv 0 + assign SAXIGP2AWADDR_in[11] = (SAXIGP2AWADDR[11] !== 1'bz) && SAXIGP2AWADDR_delay[11]; // rv 0 + assign SAXIGP2AWADDR_in[12] = (SAXIGP2AWADDR[12] !== 1'bz) && SAXIGP2AWADDR_delay[12]; // rv 0 + assign SAXIGP2AWADDR_in[13] = (SAXIGP2AWADDR[13] !== 1'bz) && SAXIGP2AWADDR_delay[13]; // rv 0 + assign SAXIGP2AWADDR_in[14] = (SAXIGP2AWADDR[14] !== 1'bz) && SAXIGP2AWADDR_delay[14]; // rv 0 + assign SAXIGP2AWADDR_in[15] = (SAXIGP2AWADDR[15] !== 1'bz) && SAXIGP2AWADDR_delay[15]; // rv 0 + assign SAXIGP2AWADDR_in[16] = (SAXIGP2AWADDR[16] !== 1'bz) && SAXIGP2AWADDR_delay[16]; // rv 0 + assign SAXIGP2AWADDR_in[17] = (SAXIGP2AWADDR[17] !== 1'bz) && SAXIGP2AWADDR_delay[17]; // rv 0 + assign SAXIGP2AWADDR_in[18] = (SAXIGP2AWADDR[18] !== 1'bz) && SAXIGP2AWADDR_delay[18]; // rv 0 + assign SAXIGP2AWADDR_in[19] = (SAXIGP2AWADDR[19] !== 1'bz) && SAXIGP2AWADDR_delay[19]; // rv 0 + assign SAXIGP2AWADDR_in[1] = (SAXIGP2AWADDR[1] !== 1'bz) && SAXIGP2AWADDR_delay[1]; // rv 0 + assign SAXIGP2AWADDR_in[20] = (SAXIGP2AWADDR[20] !== 1'bz) && SAXIGP2AWADDR_delay[20]; // rv 0 + assign SAXIGP2AWADDR_in[21] = (SAXIGP2AWADDR[21] !== 1'bz) && SAXIGP2AWADDR_delay[21]; // rv 0 + assign SAXIGP2AWADDR_in[22] = (SAXIGP2AWADDR[22] !== 1'bz) && SAXIGP2AWADDR_delay[22]; // rv 0 + assign SAXIGP2AWADDR_in[23] = (SAXIGP2AWADDR[23] !== 1'bz) && SAXIGP2AWADDR_delay[23]; // rv 0 + assign SAXIGP2AWADDR_in[24] = (SAXIGP2AWADDR[24] !== 1'bz) && SAXIGP2AWADDR_delay[24]; // rv 0 + assign SAXIGP2AWADDR_in[25] = (SAXIGP2AWADDR[25] !== 1'bz) && SAXIGP2AWADDR_delay[25]; // rv 0 + assign SAXIGP2AWADDR_in[26] = (SAXIGP2AWADDR[26] !== 1'bz) && SAXIGP2AWADDR_delay[26]; // rv 0 + assign SAXIGP2AWADDR_in[27] = (SAXIGP2AWADDR[27] !== 1'bz) && SAXIGP2AWADDR_delay[27]; // rv 0 + assign SAXIGP2AWADDR_in[28] = (SAXIGP2AWADDR[28] !== 1'bz) && SAXIGP2AWADDR_delay[28]; // rv 0 + assign SAXIGP2AWADDR_in[29] = (SAXIGP2AWADDR[29] !== 1'bz) && SAXIGP2AWADDR_delay[29]; // rv 0 + assign SAXIGP2AWADDR_in[2] = (SAXIGP2AWADDR[2] !== 1'bz) && SAXIGP2AWADDR_delay[2]; // rv 0 + assign SAXIGP2AWADDR_in[30] = (SAXIGP2AWADDR[30] !== 1'bz) && SAXIGP2AWADDR_delay[30]; // rv 0 + assign SAXIGP2AWADDR_in[31] = (SAXIGP2AWADDR[31] !== 1'bz) && SAXIGP2AWADDR_delay[31]; // rv 0 + assign SAXIGP2AWADDR_in[32] = (SAXIGP2AWADDR[32] !== 1'bz) && SAXIGP2AWADDR_delay[32]; // rv 0 + assign SAXIGP2AWADDR_in[33] = (SAXIGP2AWADDR[33] !== 1'bz) && SAXIGP2AWADDR_delay[33]; // rv 0 + assign SAXIGP2AWADDR_in[34] = (SAXIGP2AWADDR[34] !== 1'bz) && SAXIGP2AWADDR_delay[34]; // rv 0 + assign SAXIGP2AWADDR_in[35] = (SAXIGP2AWADDR[35] !== 1'bz) && SAXIGP2AWADDR_delay[35]; // rv 0 + assign SAXIGP2AWADDR_in[36] = (SAXIGP2AWADDR[36] !== 1'bz) && SAXIGP2AWADDR_delay[36]; // rv 0 + assign SAXIGP2AWADDR_in[37] = (SAXIGP2AWADDR[37] !== 1'bz) && SAXIGP2AWADDR_delay[37]; // rv 0 + assign SAXIGP2AWADDR_in[38] = (SAXIGP2AWADDR[38] !== 1'bz) && SAXIGP2AWADDR_delay[38]; // rv 0 + assign SAXIGP2AWADDR_in[39] = (SAXIGP2AWADDR[39] !== 1'bz) && SAXIGP2AWADDR_delay[39]; // rv 0 + assign SAXIGP2AWADDR_in[3] = (SAXIGP2AWADDR[3] !== 1'bz) && SAXIGP2AWADDR_delay[3]; // rv 0 + assign SAXIGP2AWADDR_in[40] = (SAXIGP2AWADDR[40] !== 1'bz) && SAXIGP2AWADDR_delay[40]; // rv 0 + assign SAXIGP2AWADDR_in[41] = (SAXIGP2AWADDR[41] !== 1'bz) && SAXIGP2AWADDR_delay[41]; // rv 0 + assign SAXIGP2AWADDR_in[42] = (SAXIGP2AWADDR[42] !== 1'bz) && SAXIGP2AWADDR_delay[42]; // rv 0 + assign SAXIGP2AWADDR_in[43] = (SAXIGP2AWADDR[43] !== 1'bz) && SAXIGP2AWADDR_delay[43]; // rv 0 + assign SAXIGP2AWADDR_in[44] = (SAXIGP2AWADDR[44] !== 1'bz) && SAXIGP2AWADDR_delay[44]; // rv 0 + assign SAXIGP2AWADDR_in[45] = (SAXIGP2AWADDR[45] !== 1'bz) && SAXIGP2AWADDR_delay[45]; // rv 0 + assign SAXIGP2AWADDR_in[46] = (SAXIGP2AWADDR[46] !== 1'bz) && SAXIGP2AWADDR_delay[46]; // rv 0 + assign SAXIGP2AWADDR_in[47] = (SAXIGP2AWADDR[47] !== 1'bz) && SAXIGP2AWADDR_delay[47]; // rv 0 + assign SAXIGP2AWADDR_in[48] = (SAXIGP2AWADDR[48] !== 1'bz) && SAXIGP2AWADDR_delay[48]; // rv 0 + assign SAXIGP2AWADDR_in[4] = (SAXIGP2AWADDR[4] !== 1'bz) && SAXIGP2AWADDR_delay[4]; // rv 0 + assign SAXIGP2AWADDR_in[5] = (SAXIGP2AWADDR[5] !== 1'bz) && SAXIGP2AWADDR_delay[5]; // rv 0 + assign SAXIGP2AWADDR_in[6] = (SAXIGP2AWADDR[6] !== 1'bz) && SAXIGP2AWADDR_delay[6]; // rv 0 + assign SAXIGP2AWADDR_in[7] = (SAXIGP2AWADDR[7] !== 1'bz) && SAXIGP2AWADDR_delay[7]; // rv 0 + assign SAXIGP2AWADDR_in[8] = (SAXIGP2AWADDR[8] !== 1'bz) && SAXIGP2AWADDR_delay[8]; // rv 0 + assign SAXIGP2AWADDR_in[9] = (SAXIGP2AWADDR[9] !== 1'bz) && SAXIGP2AWADDR_delay[9]; // rv 0 + assign SAXIGP2AWBURST_in[0] = (SAXIGP2AWBURST[0] !== 1'bz) && SAXIGP2AWBURST_delay[0]; // rv 0 + assign SAXIGP2AWBURST_in[1] = (SAXIGP2AWBURST[1] !== 1'bz) && SAXIGP2AWBURST_delay[1]; // rv 0 + assign SAXIGP2AWCACHE_in[0] = (SAXIGP2AWCACHE[0] !== 1'bz) && SAXIGP2AWCACHE_delay[0]; // rv 0 + assign SAXIGP2AWCACHE_in[1] = (SAXIGP2AWCACHE[1] !== 1'bz) && SAXIGP2AWCACHE_delay[1]; // rv 0 + assign SAXIGP2AWCACHE_in[2] = (SAXIGP2AWCACHE[2] !== 1'bz) && SAXIGP2AWCACHE_delay[2]; // rv 0 + assign SAXIGP2AWCACHE_in[3] = (SAXIGP2AWCACHE[3] !== 1'bz) && SAXIGP2AWCACHE_delay[3]; // rv 0 + assign SAXIGP2AWID_in[0] = (SAXIGP2AWID[0] !== 1'bz) && SAXIGP2AWID_delay[0]; // rv 0 + assign SAXIGP2AWID_in[1] = (SAXIGP2AWID[1] !== 1'bz) && SAXIGP2AWID_delay[1]; // rv 0 + assign SAXIGP2AWID_in[2] = (SAXIGP2AWID[2] !== 1'bz) && SAXIGP2AWID_delay[2]; // rv 0 + assign SAXIGP2AWID_in[3] = (SAXIGP2AWID[3] !== 1'bz) && SAXIGP2AWID_delay[3]; // rv 0 + assign SAXIGP2AWID_in[4] = (SAXIGP2AWID[4] !== 1'bz) && SAXIGP2AWID_delay[4]; // rv 0 + assign SAXIGP2AWID_in[5] = (SAXIGP2AWID[5] !== 1'bz) && SAXIGP2AWID_delay[5]; // rv 0 + assign SAXIGP2AWLEN_in[0] = (SAXIGP2AWLEN[0] !== 1'bz) && SAXIGP2AWLEN_delay[0]; // rv 0 + assign SAXIGP2AWLEN_in[1] = (SAXIGP2AWLEN[1] !== 1'bz) && SAXIGP2AWLEN_delay[1]; // rv 0 + assign SAXIGP2AWLEN_in[2] = (SAXIGP2AWLEN[2] !== 1'bz) && SAXIGP2AWLEN_delay[2]; // rv 0 + assign SAXIGP2AWLEN_in[3] = (SAXIGP2AWLEN[3] !== 1'bz) && SAXIGP2AWLEN_delay[3]; // rv 0 + assign SAXIGP2AWLEN_in[4] = (SAXIGP2AWLEN[4] !== 1'bz) && SAXIGP2AWLEN_delay[4]; // rv 0 + assign SAXIGP2AWLEN_in[5] = (SAXIGP2AWLEN[5] !== 1'bz) && SAXIGP2AWLEN_delay[5]; // rv 0 + assign SAXIGP2AWLEN_in[6] = (SAXIGP2AWLEN[6] !== 1'bz) && SAXIGP2AWLEN_delay[6]; // rv 0 + assign SAXIGP2AWLEN_in[7] = (SAXIGP2AWLEN[7] !== 1'bz) && SAXIGP2AWLEN_delay[7]; // rv 0 + assign SAXIGP2AWLOCK_in = (SAXIGP2AWLOCK !== 1'bz) && SAXIGP2AWLOCK_delay; // rv 0 + assign SAXIGP2AWPROT_in[0] = (SAXIGP2AWPROT[0] !== 1'bz) && SAXIGP2AWPROT_delay[0]; // rv 0 + assign SAXIGP2AWPROT_in[1] = (SAXIGP2AWPROT[1] !== 1'bz) && SAXIGP2AWPROT_delay[1]; // rv 0 + assign SAXIGP2AWPROT_in[2] = (SAXIGP2AWPROT[2] !== 1'bz) && SAXIGP2AWPROT_delay[2]; // rv 0 + assign SAXIGP2AWQOS_in[0] = (SAXIGP2AWQOS[0] !== 1'bz) && SAXIGP2AWQOS_delay[0]; // rv 0 + assign SAXIGP2AWQOS_in[1] = (SAXIGP2AWQOS[1] !== 1'bz) && SAXIGP2AWQOS_delay[1]; // rv 0 + assign SAXIGP2AWQOS_in[2] = (SAXIGP2AWQOS[2] !== 1'bz) && SAXIGP2AWQOS_delay[2]; // rv 0 + assign SAXIGP2AWQOS_in[3] = (SAXIGP2AWQOS[3] !== 1'bz) && SAXIGP2AWQOS_delay[3]; // rv 0 + assign SAXIGP2AWSIZE_in[0] = (SAXIGP2AWSIZE[0] !== 1'bz) && SAXIGP2AWSIZE_delay[0]; // rv 0 + assign SAXIGP2AWSIZE_in[1] = (SAXIGP2AWSIZE[1] !== 1'bz) && SAXIGP2AWSIZE_delay[1]; // rv 0 + assign SAXIGP2AWSIZE_in[2] = (SAXIGP2AWSIZE[2] !== 1'bz) && SAXIGP2AWSIZE_delay[2]; // rv 0 + assign SAXIGP2AWUSER_in = (SAXIGP2AWUSER !== 1'bz) && SAXIGP2AWUSER_delay; // rv 0 + assign SAXIGP2AWVALID_in = (SAXIGP2AWVALID !== 1'bz) && SAXIGP2AWVALID_delay; // rv 0 + assign SAXIGP2BREADY_in = (SAXIGP2BREADY !== 1'bz) && SAXIGP2BREADY_delay; // rv 0 + assign SAXIGP2RCLK_in = (SAXIGP2RCLK !== 1'bz) && SAXIGP2RCLK_delay; // rv 0 + assign SAXIGP2RREADY_in = (SAXIGP2RREADY !== 1'bz) && SAXIGP2RREADY_delay; // rv 0 + assign SAXIGP2WCLK_in = (SAXIGP2WCLK !== 1'bz) && SAXIGP2WCLK_delay; // rv 0 + assign SAXIGP2WDATA_in[0] = (SAXIGP2WDATA[0] !== 1'bz) && SAXIGP2WDATA_delay[0]; // rv 0 + assign SAXIGP2WDATA_in[100] = (SAXIGP2WDATA[100] !== 1'bz) && SAXIGP2WDATA_delay[100]; // rv 0 + assign SAXIGP2WDATA_in[101] = (SAXIGP2WDATA[101] !== 1'bz) && SAXIGP2WDATA_delay[101]; // rv 0 + assign SAXIGP2WDATA_in[102] = (SAXIGP2WDATA[102] !== 1'bz) && SAXIGP2WDATA_delay[102]; // rv 0 + assign SAXIGP2WDATA_in[103] = (SAXIGP2WDATA[103] !== 1'bz) && SAXIGP2WDATA_delay[103]; // rv 0 + assign SAXIGP2WDATA_in[104] = (SAXIGP2WDATA[104] !== 1'bz) && SAXIGP2WDATA_delay[104]; // rv 0 + assign SAXIGP2WDATA_in[105] = (SAXIGP2WDATA[105] !== 1'bz) && SAXIGP2WDATA_delay[105]; // rv 0 + assign SAXIGP2WDATA_in[106] = (SAXIGP2WDATA[106] !== 1'bz) && SAXIGP2WDATA_delay[106]; // rv 0 + assign SAXIGP2WDATA_in[107] = (SAXIGP2WDATA[107] !== 1'bz) && SAXIGP2WDATA_delay[107]; // rv 0 + assign SAXIGP2WDATA_in[108] = (SAXIGP2WDATA[108] !== 1'bz) && SAXIGP2WDATA_delay[108]; // rv 0 + assign SAXIGP2WDATA_in[109] = (SAXIGP2WDATA[109] !== 1'bz) && SAXIGP2WDATA_delay[109]; // rv 0 + assign SAXIGP2WDATA_in[10] = (SAXIGP2WDATA[10] !== 1'bz) && SAXIGP2WDATA_delay[10]; // rv 0 + assign SAXIGP2WDATA_in[110] = (SAXIGP2WDATA[110] !== 1'bz) && SAXIGP2WDATA_delay[110]; // rv 0 + assign SAXIGP2WDATA_in[111] = (SAXIGP2WDATA[111] !== 1'bz) && SAXIGP2WDATA_delay[111]; // rv 0 + assign SAXIGP2WDATA_in[112] = (SAXIGP2WDATA[112] !== 1'bz) && SAXIGP2WDATA_delay[112]; // rv 0 + assign SAXIGP2WDATA_in[113] = (SAXIGP2WDATA[113] !== 1'bz) && SAXIGP2WDATA_delay[113]; // rv 0 + assign SAXIGP2WDATA_in[114] = (SAXIGP2WDATA[114] !== 1'bz) && SAXIGP2WDATA_delay[114]; // rv 0 + assign SAXIGP2WDATA_in[115] = (SAXIGP2WDATA[115] !== 1'bz) && SAXIGP2WDATA_delay[115]; // rv 0 + assign SAXIGP2WDATA_in[116] = (SAXIGP2WDATA[116] !== 1'bz) && SAXIGP2WDATA_delay[116]; // rv 0 + assign SAXIGP2WDATA_in[117] = (SAXIGP2WDATA[117] !== 1'bz) && SAXIGP2WDATA_delay[117]; // rv 0 + assign SAXIGP2WDATA_in[118] = (SAXIGP2WDATA[118] !== 1'bz) && SAXIGP2WDATA_delay[118]; // rv 0 + assign SAXIGP2WDATA_in[119] = (SAXIGP2WDATA[119] !== 1'bz) && SAXIGP2WDATA_delay[119]; // rv 0 + assign SAXIGP2WDATA_in[11] = (SAXIGP2WDATA[11] !== 1'bz) && SAXIGP2WDATA_delay[11]; // rv 0 + assign SAXIGP2WDATA_in[120] = (SAXIGP2WDATA[120] !== 1'bz) && SAXIGP2WDATA_delay[120]; // rv 0 + assign SAXIGP2WDATA_in[121] = (SAXIGP2WDATA[121] !== 1'bz) && SAXIGP2WDATA_delay[121]; // rv 0 + assign SAXIGP2WDATA_in[122] = (SAXIGP2WDATA[122] !== 1'bz) && SAXIGP2WDATA_delay[122]; // rv 0 + assign SAXIGP2WDATA_in[123] = (SAXIGP2WDATA[123] !== 1'bz) && SAXIGP2WDATA_delay[123]; // rv 0 + assign SAXIGP2WDATA_in[124] = (SAXIGP2WDATA[124] !== 1'bz) && SAXIGP2WDATA_delay[124]; // rv 0 + assign SAXIGP2WDATA_in[125] = (SAXIGP2WDATA[125] !== 1'bz) && SAXIGP2WDATA_delay[125]; // rv 0 + assign SAXIGP2WDATA_in[126] = (SAXIGP2WDATA[126] !== 1'bz) && SAXIGP2WDATA_delay[126]; // rv 0 + assign SAXIGP2WDATA_in[127] = (SAXIGP2WDATA[127] !== 1'bz) && SAXIGP2WDATA_delay[127]; // rv 0 + assign SAXIGP2WDATA_in[12] = (SAXIGP2WDATA[12] !== 1'bz) && SAXIGP2WDATA_delay[12]; // rv 0 + assign SAXIGP2WDATA_in[13] = (SAXIGP2WDATA[13] !== 1'bz) && SAXIGP2WDATA_delay[13]; // rv 0 + assign SAXIGP2WDATA_in[14] = (SAXIGP2WDATA[14] !== 1'bz) && SAXIGP2WDATA_delay[14]; // rv 0 + assign SAXIGP2WDATA_in[15] = (SAXIGP2WDATA[15] !== 1'bz) && SAXIGP2WDATA_delay[15]; // rv 0 + assign SAXIGP2WDATA_in[16] = (SAXIGP2WDATA[16] !== 1'bz) && SAXIGP2WDATA_delay[16]; // rv 0 + assign SAXIGP2WDATA_in[17] = (SAXIGP2WDATA[17] !== 1'bz) && SAXIGP2WDATA_delay[17]; // rv 0 + assign SAXIGP2WDATA_in[18] = (SAXIGP2WDATA[18] !== 1'bz) && SAXIGP2WDATA_delay[18]; // rv 0 + assign SAXIGP2WDATA_in[19] = (SAXIGP2WDATA[19] !== 1'bz) && SAXIGP2WDATA_delay[19]; // rv 0 + assign SAXIGP2WDATA_in[1] = (SAXIGP2WDATA[1] !== 1'bz) && SAXIGP2WDATA_delay[1]; // rv 0 + assign SAXIGP2WDATA_in[20] = (SAXIGP2WDATA[20] !== 1'bz) && SAXIGP2WDATA_delay[20]; // rv 0 + assign SAXIGP2WDATA_in[21] = (SAXIGP2WDATA[21] !== 1'bz) && SAXIGP2WDATA_delay[21]; // rv 0 + assign SAXIGP2WDATA_in[22] = (SAXIGP2WDATA[22] !== 1'bz) && SAXIGP2WDATA_delay[22]; // rv 0 + assign SAXIGP2WDATA_in[23] = (SAXIGP2WDATA[23] !== 1'bz) && SAXIGP2WDATA_delay[23]; // rv 0 + assign SAXIGP2WDATA_in[24] = (SAXIGP2WDATA[24] !== 1'bz) && SAXIGP2WDATA_delay[24]; // rv 0 + assign SAXIGP2WDATA_in[25] = (SAXIGP2WDATA[25] !== 1'bz) && SAXIGP2WDATA_delay[25]; // rv 0 + assign SAXIGP2WDATA_in[26] = (SAXIGP2WDATA[26] !== 1'bz) && SAXIGP2WDATA_delay[26]; // rv 0 + assign SAXIGP2WDATA_in[27] = (SAXIGP2WDATA[27] !== 1'bz) && SAXIGP2WDATA_delay[27]; // rv 0 + assign SAXIGP2WDATA_in[28] = (SAXIGP2WDATA[28] !== 1'bz) && SAXIGP2WDATA_delay[28]; // rv 0 + assign SAXIGP2WDATA_in[29] = (SAXIGP2WDATA[29] !== 1'bz) && SAXIGP2WDATA_delay[29]; // rv 0 + assign SAXIGP2WDATA_in[2] = (SAXIGP2WDATA[2] !== 1'bz) && SAXIGP2WDATA_delay[2]; // rv 0 + assign SAXIGP2WDATA_in[30] = (SAXIGP2WDATA[30] !== 1'bz) && SAXIGP2WDATA_delay[30]; // rv 0 + assign SAXIGP2WDATA_in[31] = (SAXIGP2WDATA[31] !== 1'bz) && SAXIGP2WDATA_delay[31]; // rv 0 + assign SAXIGP2WDATA_in[32] = (SAXIGP2WDATA[32] !== 1'bz) && SAXIGP2WDATA_delay[32]; // rv 0 + assign SAXIGP2WDATA_in[33] = (SAXIGP2WDATA[33] !== 1'bz) && SAXIGP2WDATA_delay[33]; // rv 0 + assign SAXIGP2WDATA_in[34] = (SAXIGP2WDATA[34] !== 1'bz) && SAXIGP2WDATA_delay[34]; // rv 0 + assign SAXIGP2WDATA_in[35] = (SAXIGP2WDATA[35] !== 1'bz) && SAXIGP2WDATA_delay[35]; // rv 0 + assign SAXIGP2WDATA_in[36] = (SAXIGP2WDATA[36] !== 1'bz) && SAXIGP2WDATA_delay[36]; // rv 0 + assign SAXIGP2WDATA_in[37] = (SAXIGP2WDATA[37] !== 1'bz) && SAXIGP2WDATA_delay[37]; // rv 0 + assign SAXIGP2WDATA_in[38] = (SAXIGP2WDATA[38] !== 1'bz) && SAXIGP2WDATA_delay[38]; // rv 0 + assign SAXIGP2WDATA_in[39] = (SAXIGP2WDATA[39] !== 1'bz) && SAXIGP2WDATA_delay[39]; // rv 0 + assign SAXIGP2WDATA_in[3] = (SAXIGP2WDATA[3] !== 1'bz) && SAXIGP2WDATA_delay[3]; // rv 0 + assign SAXIGP2WDATA_in[40] = (SAXIGP2WDATA[40] !== 1'bz) && SAXIGP2WDATA_delay[40]; // rv 0 + assign SAXIGP2WDATA_in[41] = (SAXIGP2WDATA[41] !== 1'bz) && SAXIGP2WDATA_delay[41]; // rv 0 + assign SAXIGP2WDATA_in[42] = (SAXIGP2WDATA[42] !== 1'bz) && SAXIGP2WDATA_delay[42]; // rv 0 + assign SAXIGP2WDATA_in[43] = (SAXIGP2WDATA[43] !== 1'bz) && SAXIGP2WDATA_delay[43]; // rv 0 + assign SAXIGP2WDATA_in[44] = (SAXIGP2WDATA[44] !== 1'bz) && SAXIGP2WDATA_delay[44]; // rv 0 + assign SAXIGP2WDATA_in[45] = (SAXIGP2WDATA[45] !== 1'bz) && SAXIGP2WDATA_delay[45]; // rv 0 + assign SAXIGP2WDATA_in[46] = (SAXIGP2WDATA[46] !== 1'bz) && SAXIGP2WDATA_delay[46]; // rv 0 + assign SAXIGP2WDATA_in[47] = (SAXIGP2WDATA[47] !== 1'bz) && SAXIGP2WDATA_delay[47]; // rv 0 + assign SAXIGP2WDATA_in[48] = (SAXIGP2WDATA[48] !== 1'bz) && SAXIGP2WDATA_delay[48]; // rv 0 + assign SAXIGP2WDATA_in[49] = (SAXIGP2WDATA[49] !== 1'bz) && SAXIGP2WDATA_delay[49]; // rv 0 + assign SAXIGP2WDATA_in[4] = (SAXIGP2WDATA[4] !== 1'bz) && SAXIGP2WDATA_delay[4]; // rv 0 + assign SAXIGP2WDATA_in[50] = (SAXIGP2WDATA[50] !== 1'bz) && SAXIGP2WDATA_delay[50]; // rv 0 + assign SAXIGP2WDATA_in[51] = (SAXIGP2WDATA[51] !== 1'bz) && SAXIGP2WDATA_delay[51]; // rv 0 + assign SAXIGP2WDATA_in[52] = (SAXIGP2WDATA[52] !== 1'bz) && SAXIGP2WDATA_delay[52]; // rv 0 + assign SAXIGP2WDATA_in[53] = (SAXIGP2WDATA[53] !== 1'bz) && SAXIGP2WDATA_delay[53]; // rv 0 + assign SAXIGP2WDATA_in[54] = (SAXIGP2WDATA[54] !== 1'bz) && SAXIGP2WDATA_delay[54]; // rv 0 + assign SAXIGP2WDATA_in[55] = (SAXIGP2WDATA[55] !== 1'bz) && SAXIGP2WDATA_delay[55]; // rv 0 + assign SAXIGP2WDATA_in[56] = (SAXIGP2WDATA[56] !== 1'bz) && SAXIGP2WDATA_delay[56]; // rv 0 + assign SAXIGP2WDATA_in[57] = (SAXIGP2WDATA[57] !== 1'bz) && SAXIGP2WDATA_delay[57]; // rv 0 + assign SAXIGP2WDATA_in[58] = (SAXIGP2WDATA[58] !== 1'bz) && SAXIGP2WDATA_delay[58]; // rv 0 + assign SAXIGP2WDATA_in[59] = (SAXIGP2WDATA[59] !== 1'bz) && SAXIGP2WDATA_delay[59]; // rv 0 + assign SAXIGP2WDATA_in[5] = (SAXIGP2WDATA[5] !== 1'bz) && SAXIGP2WDATA_delay[5]; // rv 0 + assign SAXIGP2WDATA_in[60] = (SAXIGP2WDATA[60] !== 1'bz) && SAXIGP2WDATA_delay[60]; // rv 0 + assign SAXIGP2WDATA_in[61] = (SAXIGP2WDATA[61] !== 1'bz) && SAXIGP2WDATA_delay[61]; // rv 0 + assign SAXIGP2WDATA_in[62] = (SAXIGP2WDATA[62] !== 1'bz) && SAXIGP2WDATA_delay[62]; // rv 0 + assign SAXIGP2WDATA_in[63] = (SAXIGP2WDATA[63] !== 1'bz) && SAXIGP2WDATA_delay[63]; // rv 0 + assign SAXIGP2WDATA_in[64] = (SAXIGP2WDATA[64] !== 1'bz) && SAXIGP2WDATA_delay[64]; // rv 0 + assign SAXIGP2WDATA_in[65] = (SAXIGP2WDATA[65] !== 1'bz) && SAXIGP2WDATA_delay[65]; // rv 0 + assign SAXIGP2WDATA_in[66] = (SAXIGP2WDATA[66] !== 1'bz) && SAXIGP2WDATA_delay[66]; // rv 0 + assign SAXIGP2WDATA_in[67] = (SAXIGP2WDATA[67] !== 1'bz) && SAXIGP2WDATA_delay[67]; // rv 0 + assign SAXIGP2WDATA_in[68] = (SAXIGP2WDATA[68] !== 1'bz) && SAXIGP2WDATA_delay[68]; // rv 0 + assign SAXIGP2WDATA_in[69] = (SAXIGP2WDATA[69] !== 1'bz) && SAXIGP2WDATA_delay[69]; // rv 0 + assign SAXIGP2WDATA_in[6] = (SAXIGP2WDATA[6] !== 1'bz) && SAXIGP2WDATA_delay[6]; // rv 0 + assign SAXIGP2WDATA_in[70] = (SAXIGP2WDATA[70] !== 1'bz) && SAXIGP2WDATA_delay[70]; // rv 0 + assign SAXIGP2WDATA_in[71] = (SAXIGP2WDATA[71] !== 1'bz) && SAXIGP2WDATA_delay[71]; // rv 0 + assign SAXIGP2WDATA_in[72] = (SAXIGP2WDATA[72] !== 1'bz) && SAXIGP2WDATA_delay[72]; // rv 0 + assign SAXIGP2WDATA_in[73] = (SAXIGP2WDATA[73] !== 1'bz) && SAXIGP2WDATA_delay[73]; // rv 0 + assign SAXIGP2WDATA_in[74] = (SAXIGP2WDATA[74] !== 1'bz) && SAXIGP2WDATA_delay[74]; // rv 0 + assign SAXIGP2WDATA_in[75] = (SAXIGP2WDATA[75] !== 1'bz) && SAXIGP2WDATA_delay[75]; // rv 0 + assign SAXIGP2WDATA_in[76] = (SAXIGP2WDATA[76] !== 1'bz) && SAXIGP2WDATA_delay[76]; // rv 0 + assign SAXIGP2WDATA_in[77] = (SAXIGP2WDATA[77] !== 1'bz) && SAXIGP2WDATA_delay[77]; // rv 0 + assign SAXIGP2WDATA_in[78] = (SAXIGP2WDATA[78] !== 1'bz) && SAXIGP2WDATA_delay[78]; // rv 0 + assign SAXIGP2WDATA_in[79] = (SAXIGP2WDATA[79] !== 1'bz) && SAXIGP2WDATA_delay[79]; // rv 0 + assign SAXIGP2WDATA_in[7] = (SAXIGP2WDATA[7] !== 1'bz) && SAXIGP2WDATA_delay[7]; // rv 0 + assign SAXIGP2WDATA_in[80] = (SAXIGP2WDATA[80] !== 1'bz) && SAXIGP2WDATA_delay[80]; // rv 0 + assign SAXIGP2WDATA_in[81] = (SAXIGP2WDATA[81] !== 1'bz) && SAXIGP2WDATA_delay[81]; // rv 0 + assign SAXIGP2WDATA_in[82] = (SAXIGP2WDATA[82] !== 1'bz) && SAXIGP2WDATA_delay[82]; // rv 0 + assign SAXIGP2WDATA_in[83] = (SAXIGP2WDATA[83] !== 1'bz) && SAXIGP2WDATA_delay[83]; // rv 0 + assign SAXIGP2WDATA_in[84] = (SAXIGP2WDATA[84] !== 1'bz) && SAXIGP2WDATA_delay[84]; // rv 0 + assign SAXIGP2WDATA_in[85] = (SAXIGP2WDATA[85] !== 1'bz) && SAXIGP2WDATA_delay[85]; // rv 0 + assign SAXIGP2WDATA_in[86] = (SAXIGP2WDATA[86] !== 1'bz) && SAXIGP2WDATA_delay[86]; // rv 0 + assign SAXIGP2WDATA_in[87] = (SAXIGP2WDATA[87] !== 1'bz) && SAXIGP2WDATA_delay[87]; // rv 0 + assign SAXIGP2WDATA_in[88] = (SAXIGP2WDATA[88] !== 1'bz) && SAXIGP2WDATA_delay[88]; // rv 0 + assign SAXIGP2WDATA_in[89] = (SAXIGP2WDATA[89] !== 1'bz) && SAXIGP2WDATA_delay[89]; // rv 0 + assign SAXIGP2WDATA_in[8] = (SAXIGP2WDATA[8] !== 1'bz) && SAXIGP2WDATA_delay[8]; // rv 0 + assign SAXIGP2WDATA_in[90] = (SAXIGP2WDATA[90] !== 1'bz) && SAXIGP2WDATA_delay[90]; // rv 0 + assign SAXIGP2WDATA_in[91] = (SAXIGP2WDATA[91] !== 1'bz) && SAXIGP2WDATA_delay[91]; // rv 0 + assign SAXIGP2WDATA_in[92] = (SAXIGP2WDATA[92] !== 1'bz) && SAXIGP2WDATA_delay[92]; // rv 0 + assign SAXIGP2WDATA_in[93] = (SAXIGP2WDATA[93] !== 1'bz) && SAXIGP2WDATA_delay[93]; // rv 0 + assign SAXIGP2WDATA_in[94] = (SAXIGP2WDATA[94] !== 1'bz) && SAXIGP2WDATA_delay[94]; // rv 0 + assign SAXIGP2WDATA_in[95] = (SAXIGP2WDATA[95] !== 1'bz) && SAXIGP2WDATA_delay[95]; // rv 0 + assign SAXIGP2WDATA_in[96] = (SAXIGP2WDATA[96] !== 1'bz) && SAXIGP2WDATA_delay[96]; // rv 0 + assign SAXIGP2WDATA_in[97] = (SAXIGP2WDATA[97] !== 1'bz) && SAXIGP2WDATA_delay[97]; // rv 0 + assign SAXIGP2WDATA_in[98] = (SAXIGP2WDATA[98] !== 1'bz) && SAXIGP2WDATA_delay[98]; // rv 0 + assign SAXIGP2WDATA_in[99] = (SAXIGP2WDATA[99] !== 1'bz) && SAXIGP2WDATA_delay[99]; // rv 0 + assign SAXIGP2WDATA_in[9] = (SAXIGP2WDATA[9] !== 1'bz) && SAXIGP2WDATA_delay[9]; // rv 0 + assign SAXIGP2WLAST_in = (SAXIGP2WLAST !== 1'bz) && SAXIGP2WLAST_delay; // rv 0 + assign SAXIGP2WSTRB_in[0] = (SAXIGP2WSTRB[0] !== 1'bz) && SAXIGP2WSTRB_delay[0]; // rv 0 + assign SAXIGP2WSTRB_in[10] = (SAXIGP2WSTRB[10] !== 1'bz) && SAXIGP2WSTRB_delay[10]; // rv 0 + assign SAXIGP2WSTRB_in[11] = (SAXIGP2WSTRB[11] !== 1'bz) && SAXIGP2WSTRB_delay[11]; // rv 0 + assign SAXIGP2WSTRB_in[12] = (SAXIGP2WSTRB[12] !== 1'bz) && SAXIGP2WSTRB_delay[12]; // rv 0 + assign SAXIGP2WSTRB_in[13] = (SAXIGP2WSTRB[13] !== 1'bz) && SAXIGP2WSTRB_delay[13]; // rv 0 + assign SAXIGP2WSTRB_in[14] = (SAXIGP2WSTRB[14] !== 1'bz) && SAXIGP2WSTRB_delay[14]; // rv 0 + assign SAXIGP2WSTRB_in[15] = (SAXIGP2WSTRB[15] !== 1'bz) && SAXIGP2WSTRB_delay[15]; // rv 0 + assign SAXIGP2WSTRB_in[1] = (SAXIGP2WSTRB[1] !== 1'bz) && SAXIGP2WSTRB_delay[1]; // rv 0 + assign SAXIGP2WSTRB_in[2] = (SAXIGP2WSTRB[2] !== 1'bz) && SAXIGP2WSTRB_delay[2]; // rv 0 + assign SAXIGP2WSTRB_in[3] = (SAXIGP2WSTRB[3] !== 1'bz) && SAXIGP2WSTRB_delay[3]; // rv 0 + assign SAXIGP2WSTRB_in[4] = (SAXIGP2WSTRB[4] !== 1'bz) && SAXIGP2WSTRB_delay[4]; // rv 0 + assign SAXIGP2WSTRB_in[5] = (SAXIGP2WSTRB[5] !== 1'bz) && SAXIGP2WSTRB_delay[5]; // rv 0 + assign SAXIGP2WSTRB_in[6] = (SAXIGP2WSTRB[6] !== 1'bz) && SAXIGP2WSTRB_delay[6]; // rv 0 + assign SAXIGP2WSTRB_in[7] = (SAXIGP2WSTRB[7] !== 1'bz) && SAXIGP2WSTRB_delay[7]; // rv 0 + assign SAXIGP2WSTRB_in[8] = (SAXIGP2WSTRB[8] !== 1'bz) && SAXIGP2WSTRB_delay[8]; // rv 0 + assign SAXIGP2WSTRB_in[9] = (SAXIGP2WSTRB[9] !== 1'bz) && SAXIGP2WSTRB_delay[9]; // rv 0 + assign SAXIGP2WVALID_in = (SAXIGP2WVALID !== 1'bz) && SAXIGP2WVALID_delay; // rv 0 + assign SAXIGP3ARADDR_in[0] = (SAXIGP3ARADDR[0] !== 1'bz) && SAXIGP3ARADDR_delay[0]; // rv 0 + assign SAXIGP3ARADDR_in[10] = (SAXIGP3ARADDR[10] !== 1'bz) && SAXIGP3ARADDR_delay[10]; // rv 0 + assign SAXIGP3ARADDR_in[11] = (SAXIGP3ARADDR[11] !== 1'bz) && SAXIGP3ARADDR_delay[11]; // rv 0 + assign SAXIGP3ARADDR_in[12] = (SAXIGP3ARADDR[12] !== 1'bz) && SAXIGP3ARADDR_delay[12]; // rv 0 + assign SAXIGP3ARADDR_in[13] = (SAXIGP3ARADDR[13] !== 1'bz) && SAXIGP3ARADDR_delay[13]; // rv 0 + assign SAXIGP3ARADDR_in[14] = (SAXIGP3ARADDR[14] !== 1'bz) && SAXIGP3ARADDR_delay[14]; // rv 0 + assign SAXIGP3ARADDR_in[15] = (SAXIGP3ARADDR[15] !== 1'bz) && SAXIGP3ARADDR_delay[15]; // rv 0 + assign SAXIGP3ARADDR_in[16] = (SAXIGP3ARADDR[16] !== 1'bz) && SAXIGP3ARADDR_delay[16]; // rv 0 + assign SAXIGP3ARADDR_in[17] = (SAXIGP3ARADDR[17] !== 1'bz) && SAXIGP3ARADDR_delay[17]; // rv 0 + assign SAXIGP3ARADDR_in[18] = (SAXIGP3ARADDR[18] !== 1'bz) && SAXIGP3ARADDR_delay[18]; // rv 0 + assign SAXIGP3ARADDR_in[19] = (SAXIGP3ARADDR[19] !== 1'bz) && SAXIGP3ARADDR_delay[19]; // rv 0 + assign SAXIGP3ARADDR_in[1] = (SAXIGP3ARADDR[1] !== 1'bz) && SAXIGP3ARADDR_delay[1]; // rv 0 + assign SAXIGP3ARADDR_in[20] = (SAXIGP3ARADDR[20] !== 1'bz) && SAXIGP3ARADDR_delay[20]; // rv 0 + assign SAXIGP3ARADDR_in[21] = (SAXIGP3ARADDR[21] !== 1'bz) && SAXIGP3ARADDR_delay[21]; // rv 0 + assign SAXIGP3ARADDR_in[22] = (SAXIGP3ARADDR[22] !== 1'bz) && SAXIGP3ARADDR_delay[22]; // rv 0 + assign SAXIGP3ARADDR_in[23] = (SAXIGP3ARADDR[23] !== 1'bz) && SAXIGP3ARADDR_delay[23]; // rv 0 + assign SAXIGP3ARADDR_in[24] = (SAXIGP3ARADDR[24] !== 1'bz) && SAXIGP3ARADDR_delay[24]; // rv 0 + assign SAXIGP3ARADDR_in[25] = (SAXIGP3ARADDR[25] !== 1'bz) && SAXIGP3ARADDR_delay[25]; // rv 0 + assign SAXIGP3ARADDR_in[26] = (SAXIGP3ARADDR[26] !== 1'bz) && SAXIGP3ARADDR_delay[26]; // rv 0 + assign SAXIGP3ARADDR_in[27] = (SAXIGP3ARADDR[27] !== 1'bz) && SAXIGP3ARADDR_delay[27]; // rv 0 + assign SAXIGP3ARADDR_in[28] = (SAXIGP3ARADDR[28] !== 1'bz) && SAXIGP3ARADDR_delay[28]; // rv 0 + assign SAXIGP3ARADDR_in[29] = (SAXIGP3ARADDR[29] !== 1'bz) && SAXIGP3ARADDR_delay[29]; // rv 0 + assign SAXIGP3ARADDR_in[2] = (SAXIGP3ARADDR[2] !== 1'bz) && SAXIGP3ARADDR_delay[2]; // rv 0 + assign SAXIGP3ARADDR_in[30] = (SAXIGP3ARADDR[30] !== 1'bz) && SAXIGP3ARADDR_delay[30]; // rv 0 + assign SAXIGP3ARADDR_in[31] = (SAXIGP3ARADDR[31] !== 1'bz) && SAXIGP3ARADDR_delay[31]; // rv 0 + assign SAXIGP3ARADDR_in[32] = (SAXIGP3ARADDR[32] !== 1'bz) && SAXIGP3ARADDR_delay[32]; // rv 0 + assign SAXIGP3ARADDR_in[33] = (SAXIGP3ARADDR[33] !== 1'bz) && SAXIGP3ARADDR_delay[33]; // rv 0 + assign SAXIGP3ARADDR_in[34] = (SAXIGP3ARADDR[34] !== 1'bz) && SAXIGP3ARADDR_delay[34]; // rv 0 + assign SAXIGP3ARADDR_in[35] = (SAXIGP3ARADDR[35] !== 1'bz) && SAXIGP3ARADDR_delay[35]; // rv 0 + assign SAXIGP3ARADDR_in[36] = (SAXIGP3ARADDR[36] !== 1'bz) && SAXIGP3ARADDR_delay[36]; // rv 0 + assign SAXIGP3ARADDR_in[37] = (SAXIGP3ARADDR[37] !== 1'bz) && SAXIGP3ARADDR_delay[37]; // rv 0 + assign SAXIGP3ARADDR_in[38] = (SAXIGP3ARADDR[38] !== 1'bz) && SAXIGP3ARADDR_delay[38]; // rv 0 + assign SAXIGP3ARADDR_in[39] = (SAXIGP3ARADDR[39] !== 1'bz) && SAXIGP3ARADDR_delay[39]; // rv 0 + assign SAXIGP3ARADDR_in[3] = (SAXIGP3ARADDR[3] !== 1'bz) && SAXIGP3ARADDR_delay[3]; // rv 0 + assign SAXIGP3ARADDR_in[40] = (SAXIGP3ARADDR[40] !== 1'bz) && SAXIGP3ARADDR_delay[40]; // rv 0 + assign SAXIGP3ARADDR_in[41] = (SAXIGP3ARADDR[41] !== 1'bz) && SAXIGP3ARADDR_delay[41]; // rv 0 + assign SAXIGP3ARADDR_in[42] = (SAXIGP3ARADDR[42] !== 1'bz) && SAXIGP3ARADDR_delay[42]; // rv 0 + assign SAXIGP3ARADDR_in[43] = (SAXIGP3ARADDR[43] !== 1'bz) && SAXIGP3ARADDR_delay[43]; // rv 0 + assign SAXIGP3ARADDR_in[44] = (SAXIGP3ARADDR[44] !== 1'bz) && SAXIGP3ARADDR_delay[44]; // rv 0 + assign SAXIGP3ARADDR_in[45] = (SAXIGP3ARADDR[45] !== 1'bz) && SAXIGP3ARADDR_delay[45]; // rv 0 + assign SAXIGP3ARADDR_in[46] = (SAXIGP3ARADDR[46] !== 1'bz) && SAXIGP3ARADDR_delay[46]; // rv 0 + assign SAXIGP3ARADDR_in[47] = (SAXIGP3ARADDR[47] !== 1'bz) && SAXIGP3ARADDR_delay[47]; // rv 0 + assign SAXIGP3ARADDR_in[48] = (SAXIGP3ARADDR[48] !== 1'bz) && SAXIGP3ARADDR_delay[48]; // rv 0 + assign SAXIGP3ARADDR_in[4] = (SAXIGP3ARADDR[4] !== 1'bz) && SAXIGP3ARADDR_delay[4]; // rv 0 + assign SAXIGP3ARADDR_in[5] = (SAXIGP3ARADDR[5] !== 1'bz) && SAXIGP3ARADDR_delay[5]; // rv 0 + assign SAXIGP3ARADDR_in[6] = (SAXIGP3ARADDR[6] !== 1'bz) && SAXIGP3ARADDR_delay[6]; // rv 0 + assign SAXIGP3ARADDR_in[7] = (SAXIGP3ARADDR[7] !== 1'bz) && SAXIGP3ARADDR_delay[7]; // rv 0 + assign SAXIGP3ARADDR_in[8] = (SAXIGP3ARADDR[8] !== 1'bz) && SAXIGP3ARADDR_delay[8]; // rv 0 + assign SAXIGP3ARADDR_in[9] = (SAXIGP3ARADDR[9] !== 1'bz) && SAXIGP3ARADDR_delay[9]; // rv 0 + assign SAXIGP3ARBURST_in[0] = (SAXIGP3ARBURST[0] !== 1'bz) && SAXIGP3ARBURST_delay[0]; // rv 0 + assign SAXIGP3ARBURST_in[1] = (SAXIGP3ARBURST[1] !== 1'bz) && SAXIGP3ARBURST_delay[1]; // rv 0 + assign SAXIGP3ARCACHE_in[0] = (SAXIGP3ARCACHE[0] !== 1'bz) && SAXIGP3ARCACHE_delay[0]; // rv 0 + assign SAXIGP3ARCACHE_in[1] = (SAXIGP3ARCACHE[1] !== 1'bz) && SAXIGP3ARCACHE_delay[1]; // rv 0 + assign SAXIGP3ARCACHE_in[2] = (SAXIGP3ARCACHE[2] !== 1'bz) && SAXIGP3ARCACHE_delay[2]; // rv 0 + assign SAXIGP3ARCACHE_in[3] = (SAXIGP3ARCACHE[3] !== 1'bz) && SAXIGP3ARCACHE_delay[3]; // rv 0 + assign SAXIGP3ARID_in[0] = (SAXIGP3ARID[0] !== 1'bz) && SAXIGP3ARID_delay[0]; // rv 0 + assign SAXIGP3ARID_in[1] = (SAXIGP3ARID[1] !== 1'bz) && SAXIGP3ARID_delay[1]; // rv 0 + assign SAXIGP3ARID_in[2] = (SAXIGP3ARID[2] !== 1'bz) && SAXIGP3ARID_delay[2]; // rv 0 + assign SAXIGP3ARID_in[3] = (SAXIGP3ARID[3] !== 1'bz) && SAXIGP3ARID_delay[3]; // rv 0 + assign SAXIGP3ARID_in[4] = (SAXIGP3ARID[4] !== 1'bz) && SAXIGP3ARID_delay[4]; // rv 0 + assign SAXIGP3ARID_in[5] = (SAXIGP3ARID[5] !== 1'bz) && SAXIGP3ARID_delay[5]; // rv 0 + assign SAXIGP3ARLEN_in[0] = (SAXIGP3ARLEN[0] !== 1'bz) && SAXIGP3ARLEN_delay[0]; // rv 0 + assign SAXIGP3ARLEN_in[1] = (SAXIGP3ARLEN[1] !== 1'bz) && SAXIGP3ARLEN_delay[1]; // rv 0 + assign SAXIGP3ARLEN_in[2] = (SAXIGP3ARLEN[2] !== 1'bz) && SAXIGP3ARLEN_delay[2]; // rv 0 + assign SAXIGP3ARLEN_in[3] = (SAXIGP3ARLEN[3] !== 1'bz) && SAXIGP3ARLEN_delay[3]; // rv 0 + assign SAXIGP3ARLEN_in[4] = (SAXIGP3ARLEN[4] !== 1'bz) && SAXIGP3ARLEN_delay[4]; // rv 0 + assign SAXIGP3ARLEN_in[5] = (SAXIGP3ARLEN[5] !== 1'bz) && SAXIGP3ARLEN_delay[5]; // rv 0 + assign SAXIGP3ARLEN_in[6] = (SAXIGP3ARLEN[6] !== 1'bz) && SAXIGP3ARLEN_delay[6]; // rv 0 + assign SAXIGP3ARLEN_in[7] = (SAXIGP3ARLEN[7] !== 1'bz) && SAXIGP3ARLEN_delay[7]; // rv 0 + assign SAXIGP3ARLOCK_in = (SAXIGP3ARLOCK !== 1'bz) && SAXIGP3ARLOCK_delay; // rv 0 + assign SAXIGP3ARPROT_in[0] = (SAXIGP3ARPROT[0] !== 1'bz) && SAXIGP3ARPROT_delay[0]; // rv 0 + assign SAXIGP3ARPROT_in[1] = (SAXIGP3ARPROT[1] !== 1'bz) && SAXIGP3ARPROT_delay[1]; // rv 0 + assign SAXIGP3ARPROT_in[2] = (SAXIGP3ARPROT[2] !== 1'bz) && SAXIGP3ARPROT_delay[2]; // rv 0 + assign SAXIGP3ARQOS_in[0] = (SAXIGP3ARQOS[0] !== 1'bz) && SAXIGP3ARQOS_delay[0]; // rv 0 + assign SAXIGP3ARQOS_in[1] = (SAXIGP3ARQOS[1] !== 1'bz) && SAXIGP3ARQOS_delay[1]; // rv 0 + assign SAXIGP3ARQOS_in[2] = (SAXIGP3ARQOS[2] !== 1'bz) && SAXIGP3ARQOS_delay[2]; // rv 0 + assign SAXIGP3ARQOS_in[3] = (SAXIGP3ARQOS[3] !== 1'bz) && SAXIGP3ARQOS_delay[3]; // rv 0 + assign SAXIGP3ARSIZE_in[0] = (SAXIGP3ARSIZE[0] !== 1'bz) && SAXIGP3ARSIZE_delay[0]; // rv 0 + assign SAXIGP3ARSIZE_in[1] = (SAXIGP3ARSIZE[1] !== 1'bz) && SAXIGP3ARSIZE_delay[1]; // rv 0 + assign SAXIGP3ARSIZE_in[2] = (SAXIGP3ARSIZE[2] !== 1'bz) && SAXIGP3ARSIZE_delay[2]; // rv 0 + assign SAXIGP3ARUSER_in = (SAXIGP3ARUSER !== 1'bz) && SAXIGP3ARUSER_delay; // rv 0 + assign SAXIGP3ARVALID_in = (SAXIGP3ARVALID !== 1'bz) && SAXIGP3ARVALID_delay; // rv 0 + assign SAXIGP3AWADDR_in[0] = (SAXIGP3AWADDR[0] !== 1'bz) && SAXIGP3AWADDR_delay[0]; // rv 0 + assign SAXIGP3AWADDR_in[10] = (SAXIGP3AWADDR[10] !== 1'bz) && SAXIGP3AWADDR_delay[10]; // rv 0 + assign SAXIGP3AWADDR_in[11] = (SAXIGP3AWADDR[11] !== 1'bz) && SAXIGP3AWADDR_delay[11]; // rv 0 + assign SAXIGP3AWADDR_in[12] = (SAXIGP3AWADDR[12] !== 1'bz) && SAXIGP3AWADDR_delay[12]; // rv 0 + assign SAXIGP3AWADDR_in[13] = (SAXIGP3AWADDR[13] !== 1'bz) && SAXIGP3AWADDR_delay[13]; // rv 0 + assign SAXIGP3AWADDR_in[14] = (SAXIGP3AWADDR[14] !== 1'bz) && SAXIGP3AWADDR_delay[14]; // rv 0 + assign SAXIGP3AWADDR_in[15] = (SAXIGP3AWADDR[15] !== 1'bz) && SAXIGP3AWADDR_delay[15]; // rv 0 + assign SAXIGP3AWADDR_in[16] = (SAXIGP3AWADDR[16] !== 1'bz) && SAXIGP3AWADDR_delay[16]; // rv 0 + assign SAXIGP3AWADDR_in[17] = (SAXIGP3AWADDR[17] !== 1'bz) && SAXIGP3AWADDR_delay[17]; // rv 0 + assign SAXIGP3AWADDR_in[18] = (SAXIGP3AWADDR[18] !== 1'bz) && SAXIGP3AWADDR_delay[18]; // rv 0 + assign SAXIGP3AWADDR_in[19] = (SAXIGP3AWADDR[19] !== 1'bz) && SAXIGP3AWADDR_delay[19]; // rv 0 + assign SAXIGP3AWADDR_in[1] = (SAXIGP3AWADDR[1] !== 1'bz) && SAXIGP3AWADDR_delay[1]; // rv 0 + assign SAXIGP3AWADDR_in[20] = (SAXIGP3AWADDR[20] !== 1'bz) && SAXIGP3AWADDR_delay[20]; // rv 0 + assign SAXIGP3AWADDR_in[21] = (SAXIGP3AWADDR[21] !== 1'bz) && SAXIGP3AWADDR_delay[21]; // rv 0 + assign SAXIGP3AWADDR_in[22] = (SAXIGP3AWADDR[22] !== 1'bz) && SAXIGP3AWADDR_delay[22]; // rv 0 + assign SAXIGP3AWADDR_in[23] = (SAXIGP3AWADDR[23] !== 1'bz) && SAXIGP3AWADDR_delay[23]; // rv 0 + assign SAXIGP3AWADDR_in[24] = (SAXIGP3AWADDR[24] !== 1'bz) && SAXIGP3AWADDR_delay[24]; // rv 0 + assign SAXIGP3AWADDR_in[25] = (SAXIGP3AWADDR[25] !== 1'bz) && SAXIGP3AWADDR_delay[25]; // rv 0 + assign SAXIGP3AWADDR_in[26] = (SAXIGP3AWADDR[26] !== 1'bz) && SAXIGP3AWADDR_delay[26]; // rv 0 + assign SAXIGP3AWADDR_in[27] = (SAXIGP3AWADDR[27] !== 1'bz) && SAXIGP3AWADDR_delay[27]; // rv 0 + assign SAXIGP3AWADDR_in[28] = (SAXIGP3AWADDR[28] !== 1'bz) && SAXIGP3AWADDR_delay[28]; // rv 0 + assign SAXIGP3AWADDR_in[29] = (SAXIGP3AWADDR[29] !== 1'bz) && SAXIGP3AWADDR_delay[29]; // rv 0 + assign SAXIGP3AWADDR_in[2] = (SAXIGP3AWADDR[2] !== 1'bz) && SAXIGP3AWADDR_delay[2]; // rv 0 + assign SAXIGP3AWADDR_in[30] = (SAXIGP3AWADDR[30] !== 1'bz) && SAXIGP3AWADDR_delay[30]; // rv 0 + assign SAXIGP3AWADDR_in[31] = (SAXIGP3AWADDR[31] !== 1'bz) && SAXIGP3AWADDR_delay[31]; // rv 0 + assign SAXIGP3AWADDR_in[32] = (SAXIGP3AWADDR[32] !== 1'bz) && SAXIGP3AWADDR_delay[32]; // rv 0 + assign SAXIGP3AWADDR_in[33] = (SAXIGP3AWADDR[33] !== 1'bz) && SAXIGP3AWADDR_delay[33]; // rv 0 + assign SAXIGP3AWADDR_in[34] = (SAXIGP3AWADDR[34] !== 1'bz) && SAXIGP3AWADDR_delay[34]; // rv 0 + assign SAXIGP3AWADDR_in[35] = (SAXIGP3AWADDR[35] !== 1'bz) && SAXIGP3AWADDR_delay[35]; // rv 0 + assign SAXIGP3AWADDR_in[36] = (SAXIGP3AWADDR[36] !== 1'bz) && SAXIGP3AWADDR_delay[36]; // rv 0 + assign SAXIGP3AWADDR_in[37] = (SAXIGP3AWADDR[37] !== 1'bz) && SAXIGP3AWADDR_delay[37]; // rv 0 + assign SAXIGP3AWADDR_in[38] = (SAXIGP3AWADDR[38] !== 1'bz) && SAXIGP3AWADDR_delay[38]; // rv 0 + assign SAXIGP3AWADDR_in[39] = (SAXIGP3AWADDR[39] !== 1'bz) && SAXIGP3AWADDR_delay[39]; // rv 0 + assign SAXIGP3AWADDR_in[3] = (SAXIGP3AWADDR[3] !== 1'bz) && SAXIGP3AWADDR_delay[3]; // rv 0 + assign SAXIGP3AWADDR_in[40] = (SAXIGP3AWADDR[40] !== 1'bz) && SAXIGP3AWADDR_delay[40]; // rv 0 + assign SAXIGP3AWADDR_in[41] = (SAXIGP3AWADDR[41] !== 1'bz) && SAXIGP3AWADDR_delay[41]; // rv 0 + assign SAXIGP3AWADDR_in[42] = (SAXIGP3AWADDR[42] !== 1'bz) && SAXIGP3AWADDR_delay[42]; // rv 0 + assign SAXIGP3AWADDR_in[43] = (SAXIGP3AWADDR[43] !== 1'bz) && SAXIGP3AWADDR_delay[43]; // rv 0 + assign SAXIGP3AWADDR_in[44] = (SAXIGP3AWADDR[44] !== 1'bz) && SAXIGP3AWADDR_delay[44]; // rv 0 + assign SAXIGP3AWADDR_in[45] = (SAXIGP3AWADDR[45] !== 1'bz) && SAXIGP3AWADDR_delay[45]; // rv 0 + assign SAXIGP3AWADDR_in[46] = (SAXIGP3AWADDR[46] !== 1'bz) && SAXIGP3AWADDR_delay[46]; // rv 0 + assign SAXIGP3AWADDR_in[47] = (SAXIGP3AWADDR[47] !== 1'bz) && SAXIGP3AWADDR_delay[47]; // rv 0 + assign SAXIGP3AWADDR_in[48] = (SAXIGP3AWADDR[48] !== 1'bz) && SAXIGP3AWADDR_delay[48]; // rv 0 + assign SAXIGP3AWADDR_in[4] = (SAXIGP3AWADDR[4] !== 1'bz) && SAXIGP3AWADDR_delay[4]; // rv 0 + assign SAXIGP3AWADDR_in[5] = (SAXIGP3AWADDR[5] !== 1'bz) && SAXIGP3AWADDR_delay[5]; // rv 0 + assign SAXIGP3AWADDR_in[6] = (SAXIGP3AWADDR[6] !== 1'bz) && SAXIGP3AWADDR_delay[6]; // rv 0 + assign SAXIGP3AWADDR_in[7] = (SAXIGP3AWADDR[7] !== 1'bz) && SAXIGP3AWADDR_delay[7]; // rv 0 + assign SAXIGP3AWADDR_in[8] = (SAXIGP3AWADDR[8] !== 1'bz) && SAXIGP3AWADDR_delay[8]; // rv 0 + assign SAXIGP3AWADDR_in[9] = (SAXIGP3AWADDR[9] !== 1'bz) && SAXIGP3AWADDR_delay[9]; // rv 0 + assign SAXIGP3AWBURST_in[0] = (SAXIGP3AWBURST[0] !== 1'bz) && SAXIGP3AWBURST_delay[0]; // rv 0 + assign SAXIGP3AWBURST_in[1] = (SAXIGP3AWBURST[1] !== 1'bz) && SAXIGP3AWBURST_delay[1]; // rv 0 + assign SAXIGP3AWCACHE_in[0] = (SAXIGP3AWCACHE[0] !== 1'bz) && SAXIGP3AWCACHE_delay[0]; // rv 0 + assign SAXIGP3AWCACHE_in[1] = (SAXIGP3AWCACHE[1] !== 1'bz) && SAXIGP3AWCACHE_delay[1]; // rv 0 + assign SAXIGP3AWCACHE_in[2] = (SAXIGP3AWCACHE[2] !== 1'bz) && SAXIGP3AWCACHE_delay[2]; // rv 0 + assign SAXIGP3AWCACHE_in[3] = (SAXIGP3AWCACHE[3] !== 1'bz) && SAXIGP3AWCACHE_delay[3]; // rv 0 + assign SAXIGP3AWID_in[0] = (SAXIGP3AWID[0] !== 1'bz) && SAXIGP3AWID_delay[0]; // rv 0 + assign SAXIGP3AWID_in[1] = (SAXIGP3AWID[1] !== 1'bz) && SAXIGP3AWID_delay[1]; // rv 0 + assign SAXIGP3AWID_in[2] = (SAXIGP3AWID[2] !== 1'bz) && SAXIGP3AWID_delay[2]; // rv 0 + assign SAXIGP3AWID_in[3] = (SAXIGP3AWID[3] !== 1'bz) && SAXIGP3AWID_delay[3]; // rv 0 + assign SAXIGP3AWID_in[4] = (SAXIGP3AWID[4] !== 1'bz) && SAXIGP3AWID_delay[4]; // rv 0 + assign SAXIGP3AWID_in[5] = (SAXIGP3AWID[5] !== 1'bz) && SAXIGP3AWID_delay[5]; // rv 0 + assign SAXIGP3AWLEN_in[0] = (SAXIGP3AWLEN[0] !== 1'bz) && SAXIGP3AWLEN_delay[0]; // rv 0 + assign SAXIGP3AWLEN_in[1] = (SAXIGP3AWLEN[1] !== 1'bz) && SAXIGP3AWLEN_delay[1]; // rv 0 + assign SAXIGP3AWLEN_in[2] = (SAXIGP3AWLEN[2] !== 1'bz) && SAXIGP3AWLEN_delay[2]; // rv 0 + assign SAXIGP3AWLEN_in[3] = (SAXIGP3AWLEN[3] !== 1'bz) && SAXIGP3AWLEN_delay[3]; // rv 0 + assign SAXIGP3AWLEN_in[4] = (SAXIGP3AWLEN[4] !== 1'bz) && SAXIGP3AWLEN_delay[4]; // rv 0 + assign SAXIGP3AWLEN_in[5] = (SAXIGP3AWLEN[5] !== 1'bz) && SAXIGP3AWLEN_delay[5]; // rv 0 + assign SAXIGP3AWLEN_in[6] = (SAXIGP3AWLEN[6] !== 1'bz) && SAXIGP3AWLEN_delay[6]; // rv 0 + assign SAXIGP3AWLEN_in[7] = (SAXIGP3AWLEN[7] !== 1'bz) && SAXIGP3AWLEN_delay[7]; // rv 0 + assign SAXIGP3AWLOCK_in = (SAXIGP3AWLOCK !== 1'bz) && SAXIGP3AWLOCK_delay; // rv 0 + assign SAXIGP3AWPROT_in[0] = (SAXIGP3AWPROT[0] !== 1'bz) && SAXIGP3AWPROT_delay[0]; // rv 0 + assign SAXIGP3AWPROT_in[1] = (SAXIGP3AWPROT[1] !== 1'bz) && SAXIGP3AWPROT_delay[1]; // rv 0 + assign SAXIGP3AWPROT_in[2] = (SAXIGP3AWPROT[2] !== 1'bz) && SAXIGP3AWPROT_delay[2]; // rv 0 + assign SAXIGP3AWQOS_in[0] = (SAXIGP3AWQOS[0] !== 1'bz) && SAXIGP3AWQOS_delay[0]; // rv 0 + assign SAXIGP3AWQOS_in[1] = (SAXIGP3AWQOS[1] !== 1'bz) && SAXIGP3AWQOS_delay[1]; // rv 0 + assign SAXIGP3AWQOS_in[2] = (SAXIGP3AWQOS[2] !== 1'bz) && SAXIGP3AWQOS_delay[2]; // rv 0 + assign SAXIGP3AWQOS_in[3] = (SAXIGP3AWQOS[3] !== 1'bz) && SAXIGP3AWQOS_delay[3]; // rv 0 + assign SAXIGP3AWSIZE_in[0] = (SAXIGP3AWSIZE[0] !== 1'bz) && SAXIGP3AWSIZE_delay[0]; // rv 0 + assign SAXIGP3AWSIZE_in[1] = (SAXIGP3AWSIZE[1] !== 1'bz) && SAXIGP3AWSIZE_delay[1]; // rv 0 + assign SAXIGP3AWSIZE_in[2] = (SAXIGP3AWSIZE[2] !== 1'bz) && SAXIGP3AWSIZE_delay[2]; // rv 0 + assign SAXIGP3AWUSER_in = (SAXIGP3AWUSER !== 1'bz) && SAXIGP3AWUSER_delay; // rv 0 + assign SAXIGP3AWVALID_in = (SAXIGP3AWVALID !== 1'bz) && SAXIGP3AWVALID_delay; // rv 0 + assign SAXIGP3BREADY_in = (SAXIGP3BREADY !== 1'bz) && SAXIGP3BREADY_delay; // rv 0 + assign SAXIGP3RCLK_in = (SAXIGP3RCLK !== 1'bz) && SAXIGP3RCLK_delay; // rv 0 + assign SAXIGP3RREADY_in = (SAXIGP3RREADY !== 1'bz) && SAXIGP3RREADY_delay; // rv 0 + assign SAXIGP3WCLK_in = (SAXIGP3WCLK !== 1'bz) && SAXIGP3WCLK_delay; // rv 0 + assign SAXIGP3WDATA_in[0] = (SAXIGP3WDATA[0] !== 1'bz) && SAXIGP3WDATA_delay[0]; // rv 0 + assign SAXIGP3WDATA_in[100] = (SAXIGP3WDATA[100] !== 1'bz) && SAXIGP3WDATA_delay[100]; // rv 0 + assign SAXIGP3WDATA_in[101] = (SAXIGP3WDATA[101] !== 1'bz) && SAXIGP3WDATA_delay[101]; // rv 0 + assign SAXIGP3WDATA_in[102] = (SAXIGP3WDATA[102] !== 1'bz) && SAXIGP3WDATA_delay[102]; // rv 0 + assign SAXIGP3WDATA_in[103] = (SAXIGP3WDATA[103] !== 1'bz) && SAXIGP3WDATA_delay[103]; // rv 0 + assign SAXIGP3WDATA_in[104] = (SAXIGP3WDATA[104] !== 1'bz) && SAXIGP3WDATA_delay[104]; // rv 0 + assign SAXIGP3WDATA_in[105] = (SAXIGP3WDATA[105] !== 1'bz) && SAXIGP3WDATA_delay[105]; // rv 0 + assign SAXIGP3WDATA_in[106] = (SAXIGP3WDATA[106] !== 1'bz) && SAXIGP3WDATA_delay[106]; // rv 0 + assign SAXIGP3WDATA_in[107] = (SAXIGP3WDATA[107] !== 1'bz) && SAXIGP3WDATA_delay[107]; // rv 0 + assign SAXIGP3WDATA_in[108] = (SAXIGP3WDATA[108] !== 1'bz) && SAXIGP3WDATA_delay[108]; // rv 0 + assign SAXIGP3WDATA_in[109] = (SAXIGP3WDATA[109] !== 1'bz) && SAXIGP3WDATA_delay[109]; // rv 0 + assign SAXIGP3WDATA_in[10] = (SAXIGP3WDATA[10] !== 1'bz) && SAXIGP3WDATA_delay[10]; // rv 0 + assign SAXIGP3WDATA_in[110] = (SAXIGP3WDATA[110] !== 1'bz) && SAXIGP3WDATA_delay[110]; // rv 0 + assign SAXIGP3WDATA_in[111] = (SAXIGP3WDATA[111] !== 1'bz) && SAXIGP3WDATA_delay[111]; // rv 0 + assign SAXIGP3WDATA_in[112] = (SAXIGP3WDATA[112] !== 1'bz) && SAXIGP3WDATA_delay[112]; // rv 0 + assign SAXIGP3WDATA_in[113] = (SAXIGP3WDATA[113] !== 1'bz) && SAXIGP3WDATA_delay[113]; // rv 0 + assign SAXIGP3WDATA_in[114] = (SAXIGP3WDATA[114] !== 1'bz) && SAXIGP3WDATA_delay[114]; // rv 0 + assign SAXIGP3WDATA_in[115] = (SAXIGP3WDATA[115] !== 1'bz) && SAXIGP3WDATA_delay[115]; // rv 0 + assign SAXIGP3WDATA_in[116] = (SAXIGP3WDATA[116] !== 1'bz) && SAXIGP3WDATA_delay[116]; // rv 0 + assign SAXIGP3WDATA_in[117] = (SAXIGP3WDATA[117] !== 1'bz) && SAXIGP3WDATA_delay[117]; // rv 0 + assign SAXIGP3WDATA_in[118] = (SAXIGP3WDATA[118] !== 1'bz) && SAXIGP3WDATA_delay[118]; // rv 0 + assign SAXIGP3WDATA_in[119] = (SAXIGP3WDATA[119] !== 1'bz) && SAXIGP3WDATA_delay[119]; // rv 0 + assign SAXIGP3WDATA_in[11] = (SAXIGP3WDATA[11] !== 1'bz) && SAXIGP3WDATA_delay[11]; // rv 0 + assign SAXIGP3WDATA_in[120] = (SAXIGP3WDATA[120] !== 1'bz) && SAXIGP3WDATA_delay[120]; // rv 0 + assign SAXIGP3WDATA_in[121] = (SAXIGP3WDATA[121] !== 1'bz) && SAXIGP3WDATA_delay[121]; // rv 0 + assign SAXIGP3WDATA_in[122] = (SAXIGP3WDATA[122] !== 1'bz) && SAXIGP3WDATA_delay[122]; // rv 0 + assign SAXIGP3WDATA_in[123] = (SAXIGP3WDATA[123] !== 1'bz) && SAXIGP3WDATA_delay[123]; // rv 0 + assign SAXIGP3WDATA_in[124] = (SAXIGP3WDATA[124] !== 1'bz) && SAXIGP3WDATA_delay[124]; // rv 0 + assign SAXIGP3WDATA_in[125] = (SAXIGP3WDATA[125] !== 1'bz) && SAXIGP3WDATA_delay[125]; // rv 0 + assign SAXIGP3WDATA_in[126] = (SAXIGP3WDATA[126] !== 1'bz) && SAXIGP3WDATA_delay[126]; // rv 0 + assign SAXIGP3WDATA_in[127] = (SAXIGP3WDATA[127] !== 1'bz) && SAXIGP3WDATA_delay[127]; // rv 0 + assign SAXIGP3WDATA_in[12] = (SAXIGP3WDATA[12] !== 1'bz) && SAXIGP3WDATA_delay[12]; // rv 0 + assign SAXIGP3WDATA_in[13] = (SAXIGP3WDATA[13] !== 1'bz) && SAXIGP3WDATA_delay[13]; // rv 0 + assign SAXIGP3WDATA_in[14] = (SAXIGP3WDATA[14] !== 1'bz) && SAXIGP3WDATA_delay[14]; // rv 0 + assign SAXIGP3WDATA_in[15] = (SAXIGP3WDATA[15] !== 1'bz) && SAXIGP3WDATA_delay[15]; // rv 0 + assign SAXIGP3WDATA_in[16] = (SAXIGP3WDATA[16] !== 1'bz) && SAXIGP3WDATA_delay[16]; // rv 0 + assign SAXIGP3WDATA_in[17] = (SAXIGP3WDATA[17] !== 1'bz) && SAXIGP3WDATA_delay[17]; // rv 0 + assign SAXIGP3WDATA_in[18] = (SAXIGP3WDATA[18] !== 1'bz) && SAXIGP3WDATA_delay[18]; // rv 0 + assign SAXIGP3WDATA_in[19] = (SAXIGP3WDATA[19] !== 1'bz) && SAXIGP3WDATA_delay[19]; // rv 0 + assign SAXIGP3WDATA_in[1] = (SAXIGP3WDATA[1] !== 1'bz) && SAXIGP3WDATA_delay[1]; // rv 0 + assign SAXIGP3WDATA_in[20] = (SAXIGP3WDATA[20] !== 1'bz) && SAXIGP3WDATA_delay[20]; // rv 0 + assign SAXIGP3WDATA_in[21] = (SAXIGP3WDATA[21] !== 1'bz) && SAXIGP3WDATA_delay[21]; // rv 0 + assign SAXIGP3WDATA_in[22] = (SAXIGP3WDATA[22] !== 1'bz) && SAXIGP3WDATA_delay[22]; // rv 0 + assign SAXIGP3WDATA_in[23] = (SAXIGP3WDATA[23] !== 1'bz) && SAXIGP3WDATA_delay[23]; // rv 0 + assign SAXIGP3WDATA_in[24] = (SAXIGP3WDATA[24] !== 1'bz) && SAXIGP3WDATA_delay[24]; // rv 0 + assign SAXIGP3WDATA_in[25] = (SAXIGP3WDATA[25] !== 1'bz) && SAXIGP3WDATA_delay[25]; // rv 0 + assign SAXIGP3WDATA_in[26] = (SAXIGP3WDATA[26] !== 1'bz) && SAXIGP3WDATA_delay[26]; // rv 0 + assign SAXIGP3WDATA_in[27] = (SAXIGP3WDATA[27] !== 1'bz) && SAXIGP3WDATA_delay[27]; // rv 0 + assign SAXIGP3WDATA_in[28] = (SAXIGP3WDATA[28] !== 1'bz) && SAXIGP3WDATA_delay[28]; // rv 0 + assign SAXIGP3WDATA_in[29] = (SAXIGP3WDATA[29] !== 1'bz) && SAXIGP3WDATA_delay[29]; // rv 0 + assign SAXIGP3WDATA_in[2] = (SAXIGP3WDATA[2] !== 1'bz) && SAXIGP3WDATA_delay[2]; // rv 0 + assign SAXIGP3WDATA_in[30] = (SAXIGP3WDATA[30] !== 1'bz) && SAXIGP3WDATA_delay[30]; // rv 0 + assign SAXIGP3WDATA_in[31] = (SAXIGP3WDATA[31] !== 1'bz) && SAXIGP3WDATA_delay[31]; // rv 0 + assign SAXIGP3WDATA_in[32] = (SAXIGP3WDATA[32] !== 1'bz) && SAXIGP3WDATA_delay[32]; // rv 0 + assign SAXIGP3WDATA_in[33] = (SAXIGP3WDATA[33] !== 1'bz) && SAXIGP3WDATA_delay[33]; // rv 0 + assign SAXIGP3WDATA_in[34] = (SAXIGP3WDATA[34] !== 1'bz) && SAXIGP3WDATA_delay[34]; // rv 0 + assign SAXIGP3WDATA_in[35] = (SAXIGP3WDATA[35] !== 1'bz) && SAXIGP3WDATA_delay[35]; // rv 0 + assign SAXIGP3WDATA_in[36] = (SAXIGP3WDATA[36] !== 1'bz) && SAXIGP3WDATA_delay[36]; // rv 0 + assign SAXIGP3WDATA_in[37] = (SAXIGP3WDATA[37] !== 1'bz) && SAXIGP3WDATA_delay[37]; // rv 0 + assign SAXIGP3WDATA_in[38] = (SAXIGP3WDATA[38] !== 1'bz) && SAXIGP3WDATA_delay[38]; // rv 0 + assign SAXIGP3WDATA_in[39] = (SAXIGP3WDATA[39] !== 1'bz) && SAXIGP3WDATA_delay[39]; // rv 0 + assign SAXIGP3WDATA_in[3] = (SAXIGP3WDATA[3] !== 1'bz) && SAXIGP3WDATA_delay[3]; // rv 0 + assign SAXIGP3WDATA_in[40] = (SAXIGP3WDATA[40] !== 1'bz) && SAXIGP3WDATA_delay[40]; // rv 0 + assign SAXIGP3WDATA_in[41] = (SAXIGP3WDATA[41] !== 1'bz) && SAXIGP3WDATA_delay[41]; // rv 0 + assign SAXIGP3WDATA_in[42] = (SAXIGP3WDATA[42] !== 1'bz) && SAXIGP3WDATA_delay[42]; // rv 0 + assign SAXIGP3WDATA_in[43] = (SAXIGP3WDATA[43] !== 1'bz) && SAXIGP3WDATA_delay[43]; // rv 0 + assign SAXIGP3WDATA_in[44] = (SAXIGP3WDATA[44] !== 1'bz) && SAXIGP3WDATA_delay[44]; // rv 0 + assign SAXIGP3WDATA_in[45] = (SAXIGP3WDATA[45] !== 1'bz) && SAXIGP3WDATA_delay[45]; // rv 0 + assign SAXIGP3WDATA_in[46] = (SAXIGP3WDATA[46] !== 1'bz) && SAXIGP3WDATA_delay[46]; // rv 0 + assign SAXIGP3WDATA_in[47] = (SAXIGP3WDATA[47] !== 1'bz) && SAXIGP3WDATA_delay[47]; // rv 0 + assign SAXIGP3WDATA_in[48] = (SAXIGP3WDATA[48] !== 1'bz) && SAXIGP3WDATA_delay[48]; // rv 0 + assign SAXIGP3WDATA_in[49] = (SAXIGP3WDATA[49] !== 1'bz) && SAXIGP3WDATA_delay[49]; // rv 0 + assign SAXIGP3WDATA_in[4] = (SAXIGP3WDATA[4] !== 1'bz) && SAXIGP3WDATA_delay[4]; // rv 0 + assign SAXIGP3WDATA_in[50] = (SAXIGP3WDATA[50] !== 1'bz) && SAXIGP3WDATA_delay[50]; // rv 0 + assign SAXIGP3WDATA_in[51] = (SAXIGP3WDATA[51] !== 1'bz) && SAXIGP3WDATA_delay[51]; // rv 0 + assign SAXIGP3WDATA_in[52] = (SAXIGP3WDATA[52] !== 1'bz) && SAXIGP3WDATA_delay[52]; // rv 0 + assign SAXIGP3WDATA_in[53] = (SAXIGP3WDATA[53] !== 1'bz) && SAXIGP3WDATA_delay[53]; // rv 0 + assign SAXIGP3WDATA_in[54] = (SAXIGP3WDATA[54] !== 1'bz) && SAXIGP3WDATA_delay[54]; // rv 0 + assign SAXIGP3WDATA_in[55] = (SAXIGP3WDATA[55] !== 1'bz) && SAXIGP3WDATA_delay[55]; // rv 0 + assign SAXIGP3WDATA_in[56] = (SAXIGP3WDATA[56] !== 1'bz) && SAXIGP3WDATA_delay[56]; // rv 0 + assign SAXIGP3WDATA_in[57] = (SAXIGP3WDATA[57] !== 1'bz) && SAXIGP3WDATA_delay[57]; // rv 0 + assign SAXIGP3WDATA_in[58] = (SAXIGP3WDATA[58] !== 1'bz) && SAXIGP3WDATA_delay[58]; // rv 0 + assign SAXIGP3WDATA_in[59] = (SAXIGP3WDATA[59] !== 1'bz) && SAXIGP3WDATA_delay[59]; // rv 0 + assign SAXIGP3WDATA_in[5] = (SAXIGP3WDATA[5] !== 1'bz) && SAXIGP3WDATA_delay[5]; // rv 0 + assign SAXIGP3WDATA_in[60] = (SAXIGP3WDATA[60] !== 1'bz) && SAXIGP3WDATA_delay[60]; // rv 0 + assign SAXIGP3WDATA_in[61] = (SAXIGP3WDATA[61] !== 1'bz) && SAXIGP3WDATA_delay[61]; // rv 0 + assign SAXIGP3WDATA_in[62] = (SAXIGP3WDATA[62] !== 1'bz) && SAXIGP3WDATA_delay[62]; // rv 0 + assign SAXIGP3WDATA_in[63] = (SAXIGP3WDATA[63] !== 1'bz) && SAXIGP3WDATA_delay[63]; // rv 0 + assign SAXIGP3WDATA_in[64] = (SAXIGP3WDATA[64] !== 1'bz) && SAXIGP3WDATA_delay[64]; // rv 0 + assign SAXIGP3WDATA_in[65] = (SAXIGP3WDATA[65] !== 1'bz) && SAXIGP3WDATA_delay[65]; // rv 0 + assign SAXIGP3WDATA_in[66] = (SAXIGP3WDATA[66] !== 1'bz) && SAXIGP3WDATA_delay[66]; // rv 0 + assign SAXIGP3WDATA_in[67] = (SAXIGP3WDATA[67] !== 1'bz) && SAXIGP3WDATA_delay[67]; // rv 0 + assign SAXIGP3WDATA_in[68] = (SAXIGP3WDATA[68] !== 1'bz) && SAXIGP3WDATA_delay[68]; // rv 0 + assign SAXIGP3WDATA_in[69] = (SAXIGP3WDATA[69] !== 1'bz) && SAXIGP3WDATA_delay[69]; // rv 0 + assign SAXIGP3WDATA_in[6] = (SAXIGP3WDATA[6] !== 1'bz) && SAXIGP3WDATA_delay[6]; // rv 0 + assign SAXIGP3WDATA_in[70] = (SAXIGP3WDATA[70] !== 1'bz) && SAXIGP3WDATA_delay[70]; // rv 0 + assign SAXIGP3WDATA_in[71] = (SAXIGP3WDATA[71] !== 1'bz) && SAXIGP3WDATA_delay[71]; // rv 0 + assign SAXIGP3WDATA_in[72] = (SAXIGP3WDATA[72] !== 1'bz) && SAXIGP3WDATA_delay[72]; // rv 0 + assign SAXIGP3WDATA_in[73] = (SAXIGP3WDATA[73] !== 1'bz) && SAXIGP3WDATA_delay[73]; // rv 0 + assign SAXIGP3WDATA_in[74] = (SAXIGP3WDATA[74] !== 1'bz) && SAXIGP3WDATA_delay[74]; // rv 0 + assign SAXIGP3WDATA_in[75] = (SAXIGP3WDATA[75] !== 1'bz) && SAXIGP3WDATA_delay[75]; // rv 0 + assign SAXIGP3WDATA_in[76] = (SAXIGP3WDATA[76] !== 1'bz) && SAXIGP3WDATA_delay[76]; // rv 0 + assign SAXIGP3WDATA_in[77] = (SAXIGP3WDATA[77] !== 1'bz) && SAXIGP3WDATA_delay[77]; // rv 0 + assign SAXIGP3WDATA_in[78] = (SAXIGP3WDATA[78] !== 1'bz) && SAXIGP3WDATA_delay[78]; // rv 0 + assign SAXIGP3WDATA_in[79] = (SAXIGP3WDATA[79] !== 1'bz) && SAXIGP3WDATA_delay[79]; // rv 0 + assign SAXIGP3WDATA_in[7] = (SAXIGP3WDATA[7] !== 1'bz) && SAXIGP3WDATA_delay[7]; // rv 0 + assign SAXIGP3WDATA_in[80] = (SAXIGP3WDATA[80] !== 1'bz) && SAXIGP3WDATA_delay[80]; // rv 0 + assign SAXIGP3WDATA_in[81] = (SAXIGP3WDATA[81] !== 1'bz) && SAXIGP3WDATA_delay[81]; // rv 0 + assign SAXIGP3WDATA_in[82] = (SAXIGP3WDATA[82] !== 1'bz) && SAXIGP3WDATA_delay[82]; // rv 0 + assign SAXIGP3WDATA_in[83] = (SAXIGP3WDATA[83] !== 1'bz) && SAXIGP3WDATA_delay[83]; // rv 0 + assign SAXIGP3WDATA_in[84] = (SAXIGP3WDATA[84] !== 1'bz) && SAXIGP3WDATA_delay[84]; // rv 0 + assign SAXIGP3WDATA_in[85] = (SAXIGP3WDATA[85] !== 1'bz) && SAXIGP3WDATA_delay[85]; // rv 0 + assign SAXIGP3WDATA_in[86] = (SAXIGP3WDATA[86] !== 1'bz) && SAXIGP3WDATA_delay[86]; // rv 0 + assign SAXIGP3WDATA_in[87] = (SAXIGP3WDATA[87] !== 1'bz) && SAXIGP3WDATA_delay[87]; // rv 0 + assign SAXIGP3WDATA_in[88] = (SAXIGP3WDATA[88] !== 1'bz) && SAXIGP3WDATA_delay[88]; // rv 0 + assign SAXIGP3WDATA_in[89] = (SAXIGP3WDATA[89] !== 1'bz) && SAXIGP3WDATA_delay[89]; // rv 0 + assign SAXIGP3WDATA_in[8] = (SAXIGP3WDATA[8] !== 1'bz) && SAXIGP3WDATA_delay[8]; // rv 0 + assign SAXIGP3WDATA_in[90] = (SAXIGP3WDATA[90] !== 1'bz) && SAXIGP3WDATA_delay[90]; // rv 0 + assign SAXIGP3WDATA_in[91] = (SAXIGP3WDATA[91] !== 1'bz) && SAXIGP3WDATA_delay[91]; // rv 0 + assign SAXIGP3WDATA_in[92] = (SAXIGP3WDATA[92] !== 1'bz) && SAXIGP3WDATA_delay[92]; // rv 0 + assign SAXIGP3WDATA_in[93] = (SAXIGP3WDATA[93] !== 1'bz) && SAXIGP3WDATA_delay[93]; // rv 0 + assign SAXIGP3WDATA_in[94] = (SAXIGP3WDATA[94] !== 1'bz) && SAXIGP3WDATA_delay[94]; // rv 0 + assign SAXIGP3WDATA_in[95] = (SAXIGP3WDATA[95] !== 1'bz) && SAXIGP3WDATA_delay[95]; // rv 0 + assign SAXIGP3WDATA_in[96] = (SAXIGP3WDATA[96] !== 1'bz) && SAXIGP3WDATA_delay[96]; // rv 0 + assign SAXIGP3WDATA_in[97] = (SAXIGP3WDATA[97] !== 1'bz) && SAXIGP3WDATA_delay[97]; // rv 0 + assign SAXIGP3WDATA_in[98] = (SAXIGP3WDATA[98] !== 1'bz) && SAXIGP3WDATA_delay[98]; // rv 0 + assign SAXIGP3WDATA_in[99] = (SAXIGP3WDATA[99] !== 1'bz) && SAXIGP3WDATA_delay[99]; // rv 0 + assign SAXIGP3WDATA_in[9] = (SAXIGP3WDATA[9] !== 1'bz) && SAXIGP3WDATA_delay[9]; // rv 0 + assign SAXIGP3WLAST_in = (SAXIGP3WLAST !== 1'bz) && SAXIGP3WLAST_delay; // rv 0 + assign SAXIGP3WSTRB_in[0] = (SAXIGP3WSTRB[0] !== 1'bz) && SAXIGP3WSTRB_delay[0]; // rv 0 + assign SAXIGP3WSTRB_in[10] = (SAXIGP3WSTRB[10] !== 1'bz) && SAXIGP3WSTRB_delay[10]; // rv 0 + assign SAXIGP3WSTRB_in[11] = (SAXIGP3WSTRB[11] !== 1'bz) && SAXIGP3WSTRB_delay[11]; // rv 0 + assign SAXIGP3WSTRB_in[12] = (SAXIGP3WSTRB[12] !== 1'bz) && SAXIGP3WSTRB_delay[12]; // rv 0 + assign SAXIGP3WSTRB_in[13] = (SAXIGP3WSTRB[13] !== 1'bz) && SAXIGP3WSTRB_delay[13]; // rv 0 + assign SAXIGP3WSTRB_in[14] = (SAXIGP3WSTRB[14] !== 1'bz) && SAXIGP3WSTRB_delay[14]; // rv 0 + assign SAXIGP3WSTRB_in[15] = (SAXIGP3WSTRB[15] !== 1'bz) && SAXIGP3WSTRB_delay[15]; // rv 0 + assign SAXIGP3WSTRB_in[1] = (SAXIGP3WSTRB[1] !== 1'bz) && SAXIGP3WSTRB_delay[1]; // rv 0 + assign SAXIGP3WSTRB_in[2] = (SAXIGP3WSTRB[2] !== 1'bz) && SAXIGP3WSTRB_delay[2]; // rv 0 + assign SAXIGP3WSTRB_in[3] = (SAXIGP3WSTRB[3] !== 1'bz) && SAXIGP3WSTRB_delay[3]; // rv 0 + assign SAXIGP3WSTRB_in[4] = (SAXIGP3WSTRB[4] !== 1'bz) && SAXIGP3WSTRB_delay[4]; // rv 0 + assign SAXIGP3WSTRB_in[5] = (SAXIGP3WSTRB[5] !== 1'bz) && SAXIGP3WSTRB_delay[5]; // rv 0 + assign SAXIGP3WSTRB_in[6] = (SAXIGP3WSTRB[6] !== 1'bz) && SAXIGP3WSTRB_delay[6]; // rv 0 + assign SAXIGP3WSTRB_in[7] = (SAXIGP3WSTRB[7] !== 1'bz) && SAXIGP3WSTRB_delay[7]; // rv 0 + assign SAXIGP3WSTRB_in[8] = (SAXIGP3WSTRB[8] !== 1'bz) && SAXIGP3WSTRB_delay[8]; // rv 0 + assign SAXIGP3WSTRB_in[9] = (SAXIGP3WSTRB[9] !== 1'bz) && SAXIGP3WSTRB_delay[9]; // rv 0 + assign SAXIGP3WVALID_in = (SAXIGP3WVALID !== 1'bz) && SAXIGP3WVALID_delay; // rv 0 + assign SAXIGP4ARADDR_in[0] = (SAXIGP4ARADDR[0] !== 1'bz) && SAXIGP4ARADDR_delay[0]; // rv 0 + assign SAXIGP4ARADDR_in[10] = (SAXIGP4ARADDR[10] !== 1'bz) && SAXIGP4ARADDR_delay[10]; // rv 0 + assign SAXIGP4ARADDR_in[11] = (SAXIGP4ARADDR[11] !== 1'bz) && SAXIGP4ARADDR_delay[11]; // rv 0 + assign SAXIGP4ARADDR_in[12] = (SAXIGP4ARADDR[12] !== 1'bz) && SAXIGP4ARADDR_delay[12]; // rv 0 + assign SAXIGP4ARADDR_in[13] = (SAXIGP4ARADDR[13] !== 1'bz) && SAXIGP4ARADDR_delay[13]; // rv 0 + assign SAXIGP4ARADDR_in[14] = (SAXIGP4ARADDR[14] !== 1'bz) && SAXIGP4ARADDR_delay[14]; // rv 0 + assign SAXIGP4ARADDR_in[15] = (SAXIGP4ARADDR[15] !== 1'bz) && SAXIGP4ARADDR_delay[15]; // rv 0 + assign SAXIGP4ARADDR_in[16] = (SAXIGP4ARADDR[16] !== 1'bz) && SAXIGP4ARADDR_delay[16]; // rv 0 + assign SAXIGP4ARADDR_in[17] = (SAXIGP4ARADDR[17] !== 1'bz) && SAXIGP4ARADDR_delay[17]; // rv 0 + assign SAXIGP4ARADDR_in[18] = (SAXIGP4ARADDR[18] !== 1'bz) && SAXIGP4ARADDR_delay[18]; // rv 0 + assign SAXIGP4ARADDR_in[19] = (SAXIGP4ARADDR[19] !== 1'bz) && SAXIGP4ARADDR_delay[19]; // rv 0 + assign SAXIGP4ARADDR_in[1] = (SAXIGP4ARADDR[1] !== 1'bz) && SAXIGP4ARADDR_delay[1]; // rv 0 + assign SAXIGP4ARADDR_in[20] = (SAXIGP4ARADDR[20] !== 1'bz) && SAXIGP4ARADDR_delay[20]; // rv 0 + assign SAXIGP4ARADDR_in[21] = (SAXIGP4ARADDR[21] !== 1'bz) && SAXIGP4ARADDR_delay[21]; // rv 0 + assign SAXIGP4ARADDR_in[22] = (SAXIGP4ARADDR[22] !== 1'bz) && SAXIGP4ARADDR_delay[22]; // rv 0 + assign SAXIGP4ARADDR_in[23] = (SAXIGP4ARADDR[23] !== 1'bz) && SAXIGP4ARADDR_delay[23]; // rv 0 + assign SAXIGP4ARADDR_in[24] = (SAXIGP4ARADDR[24] !== 1'bz) && SAXIGP4ARADDR_delay[24]; // rv 0 + assign SAXIGP4ARADDR_in[25] = (SAXIGP4ARADDR[25] !== 1'bz) && SAXIGP4ARADDR_delay[25]; // rv 0 + assign SAXIGP4ARADDR_in[26] = (SAXIGP4ARADDR[26] !== 1'bz) && SAXIGP4ARADDR_delay[26]; // rv 0 + assign SAXIGP4ARADDR_in[27] = (SAXIGP4ARADDR[27] !== 1'bz) && SAXIGP4ARADDR_delay[27]; // rv 0 + assign SAXIGP4ARADDR_in[28] = (SAXIGP4ARADDR[28] !== 1'bz) && SAXIGP4ARADDR_delay[28]; // rv 0 + assign SAXIGP4ARADDR_in[29] = (SAXIGP4ARADDR[29] !== 1'bz) && SAXIGP4ARADDR_delay[29]; // rv 0 + assign SAXIGP4ARADDR_in[2] = (SAXIGP4ARADDR[2] !== 1'bz) && SAXIGP4ARADDR_delay[2]; // rv 0 + assign SAXIGP4ARADDR_in[30] = (SAXIGP4ARADDR[30] !== 1'bz) && SAXIGP4ARADDR_delay[30]; // rv 0 + assign SAXIGP4ARADDR_in[31] = (SAXIGP4ARADDR[31] !== 1'bz) && SAXIGP4ARADDR_delay[31]; // rv 0 + assign SAXIGP4ARADDR_in[32] = (SAXIGP4ARADDR[32] !== 1'bz) && SAXIGP4ARADDR_delay[32]; // rv 0 + assign SAXIGP4ARADDR_in[33] = (SAXIGP4ARADDR[33] !== 1'bz) && SAXIGP4ARADDR_delay[33]; // rv 0 + assign SAXIGP4ARADDR_in[34] = (SAXIGP4ARADDR[34] !== 1'bz) && SAXIGP4ARADDR_delay[34]; // rv 0 + assign SAXIGP4ARADDR_in[35] = (SAXIGP4ARADDR[35] !== 1'bz) && SAXIGP4ARADDR_delay[35]; // rv 0 + assign SAXIGP4ARADDR_in[36] = (SAXIGP4ARADDR[36] !== 1'bz) && SAXIGP4ARADDR_delay[36]; // rv 0 + assign SAXIGP4ARADDR_in[37] = (SAXIGP4ARADDR[37] !== 1'bz) && SAXIGP4ARADDR_delay[37]; // rv 0 + assign SAXIGP4ARADDR_in[38] = (SAXIGP4ARADDR[38] !== 1'bz) && SAXIGP4ARADDR_delay[38]; // rv 0 + assign SAXIGP4ARADDR_in[39] = (SAXIGP4ARADDR[39] !== 1'bz) && SAXIGP4ARADDR_delay[39]; // rv 0 + assign SAXIGP4ARADDR_in[3] = (SAXIGP4ARADDR[3] !== 1'bz) && SAXIGP4ARADDR_delay[3]; // rv 0 + assign SAXIGP4ARADDR_in[40] = (SAXIGP4ARADDR[40] !== 1'bz) && SAXIGP4ARADDR_delay[40]; // rv 0 + assign SAXIGP4ARADDR_in[41] = (SAXIGP4ARADDR[41] !== 1'bz) && SAXIGP4ARADDR_delay[41]; // rv 0 + assign SAXIGP4ARADDR_in[42] = (SAXIGP4ARADDR[42] !== 1'bz) && SAXIGP4ARADDR_delay[42]; // rv 0 + assign SAXIGP4ARADDR_in[43] = (SAXIGP4ARADDR[43] !== 1'bz) && SAXIGP4ARADDR_delay[43]; // rv 0 + assign SAXIGP4ARADDR_in[44] = (SAXIGP4ARADDR[44] !== 1'bz) && SAXIGP4ARADDR_delay[44]; // rv 0 + assign SAXIGP4ARADDR_in[45] = (SAXIGP4ARADDR[45] !== 1'bz) && SAXIGP4ARADDR_delay[45]; // rv 0 + assign SAXIGP4ARADDR_in[46] = (SAXIGP4ARADDR[46] !== 1'bz) && SAXIGP4ARADDR_delay[46]; // rv 0 + assign SAXIGP4ARADDR_in[47] = (SAXIGP4ARADDR[47] !== 1'bz) && SAXIGP4ARADDR_delay[47]; // rv 0 + assign SAXIGP4ARADDR_in[48] = (SAXIGP4ARADDR[48] !== 1'bz) && SAXIGP4ARADDR_delay[48]; // rv 0 + assign SAXIGP4ARADDR_in[4] = (SAXIGP4ARADDR[4] !== 1'bz) && SAXIGP4ARADDR_delay[4]; // rv 0 + assign SAXIGP4ARADDR_in[5] = (SAXIGP4ARADDR[5] !== 1'bz) && SAXIGP4ARADDR_delay[5]; // rv 0 + assign SAXIGP4ARADDR_in[6] = (SAXIGP4ARADDR[6] !== 1'bz) && SAXIGP4ARADDR_delay[6]; // rv 0 + assign SAXIGP4ARADDR_in[7] = (SAXIGP4ARADDR[7] !== 1'bz) && SAXIGP4ARADDR_delay[7]; // rv 0 + assign SAXIGP4ARADDR_in[8] = (SAXIGP4ARADDR[8] !== 1'bz) && SAXIGP4ARADDR_delay[8]; // rv 0 + assign SAXIGP4ARADDR_in[9] = (SAXIGP4ARADDR[9] !== 1'bz) && SAXIGP4ARADDR_delay[9]; // rv 0 + assign SAXIGP4ARBURST_in[0] = (SAXIGP4ARBURST[0] !== 1'bz) && SAXIGP4ARBURST_delay[0]; // rv 0 + assign SAXIGP4ARBURST_in[1] = (SAXIGP4ARBURST[1] !== 1'bz) && SAXIGP4ARBURST_delay[1]; // rv 0 + assign SAXIGP4ARCACHE_in[0] = (SAXIGP4ARCACHE[0] !== 1'bz) && SAXIGP4ARCACHE_delay[0]; // rv 0 + assign SAXIGP4ARCACHE_in[1] = (SAXIGP4ARCACHE[1] !== 1'bz) && SAXIGP4ARCACHE_delay[1]; // rv 0 + assign SAXIGP4ARCACHE_in[2] = (SAXIGP4ARCACHE[2] !== 1'bz) && SAXIGP4ARCACHE_delay[2]; // rv 0 + assign SAXIGP4ARCACHE_in[3] = (SAXIGP4ARCACHE[3] !== 1'bz) && SAXIGP4ARCACHE_delay[3]; // rv 0 + assign SAXIGP4ARID_in[0] = (SAXIGP4ARID[0] !== 1'bz) && SAXIGP4ARID_delay[0]; // rv 0 + assign SAXIGP4ARID_in[1] = (SAXIGP4ARID[1] !== 1'bz) && SAXIGP4ARID_delay[1]; // rv 0 + assign SAXIGP4ARID_in[2] = (SAXIGP4ARID[2] !== 1'bz) && SAXIGP4ARID_delay[2]; // rv 0 + assign SAXIGP4ARID_in[3] = (SAXIGP4ARID[3] !== 1'bz) && SAXIGP4ARID_delay[3]; // rv 0 + assign SAXIGP4ARID_in[4] = (SAXIGP4ARID[4] !== 1'bz) && SAXIGP4ARID_delay[4]; // rv 0 + assign SAXIGP4ARID_in[5] = (SAXIGP4ARID[5] !== 1'bz) && SAXIGP4ARID_delay[5]; // rv 0 + assign SAXIGP4ARLEN_in[0] = (SAXIGP4ARLEN[0] !== 1'bz) && SAXIGP4ARLEN_delay[0]; // rv 0 + assign SAXIGP4ARLEN_in[1] = (SAXIGP4ARLEN[1] !== 1'bz) && SAXIGP4ARLEN_delay[1]; // rv 0 + assign SAXIGP4ARLEN_in[2] = (SAXIGP4ARLEN[2] !== 1'bz) && SAXIGP4ARLEN_delay[2]; // rv 0 + assign SAXIGP4ARLEN_in[3] = (SAXIGP4ARLEN[3] !== 1'bz) && SAXIGP4ARLEN_delay[3]; // rv 0 + assign SAXIGP4ARLEN_in[4] = (SAXIGP4ARLEN[4] !== 1'bz) && SAXIGP4ARLEN_delay[4]; // rv 0 + assign SAXIGP4ARLEN_in[5] = (SAXIGP4ARLEN[5] !== 1'bz) && SAXIGP4ARLEN_delay[5]; // rv 0 + assign SAXIGP4ARLEN_in[6] = (SAXIGP4ARLEN[6] !== 1'bz) && SAXIGP4ARLEN_delay[6]; // rv 0 + assign SAXIGP4ARLEN_in[7] = (SAXIGP4ARLEN[7] !== 1'bz) && SAXIGP4ARLEN_delay[7]; // rv 0 + assign SAXIGP4ARLOCK_in = (SAXIGP4ARLOCK !== 1'bz) && SAXIGP4ARLOCK_delay; // rv 0 + assign SAXIGP4ARPROT_in[0] = (SAXIGP4ARPROT[0] !== 1'bz) && SAXIGP4ARPROT_delay[0]; // rv 0 + assign SAXIGP4ARPROT_in[1] = (SAXIGP4ARPROT[1] !== 1'bz) && SAXIGP4ARPROT_delay[1]; // rv 0 + assign SAXIGP4ARPROT_in[2] = (SAXIGP4ARPROT[2] !== 1'bz) && SAXIGP4ARPROT_delay[2]; // rv 0 + assign SAXIGP4ARQOS_in[0] = (SAXIGP4ARQOS[0] !== 1'bz) && SAXIGP4ARQOS_delay[0]; // rv 0 + assign SAXIGP4ARQOS_in[1] = (SAXIGP4ARQOS[1] !== 1'bz) && SAXIGP4ARQOS_delay[1]; // rv 0 + assign SAXIGP4ARQOS_in[2] = (SAXIGP4ARQOS[2] !== 1'bz) && SAXIGP4ARQOS_delay[2]; // rv 0 + assign SAXIGP4ARQOS_in[3] = (SAXIGP4ARQOS[3] !== 1'bz) && SAXIGP4ARQOS_delay[3]; // rv 0 + assign SAXIGP4ARSIZE_in[0] = (SAXIGP4ARSIZE[0] !== 1'bz) && SAXIGP4ARSIZE_delay[0]; // rv 0 + assign SAXIGP4ARSIZE_in[1] = (SAXIGP4ARSIZE[1] !== 1'bz) && SAXIGP4ARSIZE_delay[1]; // rv 0 + assign SAXIGP4ARSIZE_in[2] = (SAXIGP4ARSIZE[2] !== 1'bz) && SAXIGP4ARSIZE_delay[2]; // rv 0 + assign SAXIGP4ARUSER_in = (SAXIGP4ARUSER !== 1'bz) && SAXIGP4ARUSER_delay; // rv 0 + assign SAXIGP4ARVALID_in = (SAXIGP4ARVALID !== 1'bz) && SAXIGP4ARVALID_delay; // rv 0 + assign SAXIGP4AWADDR_in[0] = (SAXIGP4AWADDR[0] !== 1'bz) && SAXIGP4AWADDR_delay[0]; // rv 0 + assign SAXIGP4AWADDR_in[10] = (SAXIGP4AWADDR[10] !== 1'bz) && SAXIGP4AWADDR_delay[10]; // rv 0 + assign SAXIGP4AWADDR_in[11] = (SAXIGP4AWADDR[11] !== 1'bz) && SAXIGP4AWADDR_delay[11]; // rv 0 + assign SAXIGP4AWADDR_in[12] = (SAXIGP4AWADDR[12] !== 1'bz) && SAXIGP4AWADDR_delay[12]; // rv 0 + assign SAXIGP4AWADDR_in[13] = (SAXIGP4AWADDR[13] !== 1'bz) && SAXIGP4AWADDR_delay[13]; // rv 0 + assign SAXIGP4AWADDR_in[14] = (SAXIGP4AWADDR[14] !== 1'bz) && SAXIGP4AWADDR_delay[14]; // rv 0 + assign SAXIGP4AWADDR_in[15] = (SAXIGP4AWADDR[15] !== 1'bz) && SAXIGP4AWADDR_delay[15]; // rv 0 + assign SAXIGP4AWADDR_in[16] = (SAXIGP4AWADDR[16] !== 1'bz) && SAXIGP4AWADDR_delay[16]; // rv 0 + assign SAXIGP4AWADDR_in[17] = (SAXIGP4AWADDR[17] !== 1'bz) && SAXIGP4AWADDR_delay[17]; // rv 0 + assign SAXIGP4AWADDR_in[18] = (SAXIGP4AWADDR[18] !== 1'bz) && SAXIGP4AWADDR_delay[18]; // rv 0 + assign SAXIGP4AWADDR_in[19] = (SAXIGP4AWADDR[19] !== 1'bz) && SAXIGP4AWADDR_delay[19]; // rv 0 + assign SAXIGP4AWADDR_in[1] = (SAXIGP4AWADDR[1] !== 1'bz) && SAXIGP4AWADDR_delay[1]; // rv 0 + assign SAXIGP4AWADDR_in[20] = (SAXIGP4AWADDR[20] !== 1'bz) && SAXIGP4AWADDR_delay[20]; // rv 0 + assign SAXIGP4AWADDR_in[21] = (SAXIGP4AWADDR[21] !== 1'bz) && SAXIGP4AWADDR_delay[21]; // rv 0 + assign SAXIGP4AWADDR_in[22] = (SAXIGP4AWADDR[22] !== 1'bz) && SAXIGP4AWADDR_delay[22]; // rv 0 + assign SAXIGP4AWADDR_in[23] = (SAXIGP4AWADDR[23] !== 1'bz) && SAXIGP4AWADDR_delay[23]; // rv 0 + assign SAXIGP4AWADDR_in[24] = (SAXIGP4AWADDR[24] !== 1'bz) && SAXIGP4AWADDR_delay[24]; // rv 0 + assign SAXIGP4AWADDR_in[25] = (SAXIGP4AWADDR[25] !== 1'bz) && SAXIGP4AWADDR_delay[25]; // rv 0 + assign SAXIGP4AWADDR_in[26] = (SAXIGP4AWADDR[26] !== 1'bz) && SAXIGP4AWADDR_delay[26]; // rv 0 + assign SAXIGP4AWADDR_in[27] = (SAXIGP4AWADDR[27] !== 1'bz) && SAXIGP4AWADDR_delay[27]; // rv 0 + assign SAXIGP4AWADDR_in[28] = (SAXIGP4AWADDR[28] !== 1'bz) && SAXIGP4AWADDR_delay[28]; // rv 0 + assign SAXIGP4AWADDR_in[29] = (SAXIGP4AWADDR[29] !== 1'bz) && SAXIGP4AWADDR_delay[29]; // rv 0 + assign SAXIGP4AWADDR_in[2] = (SAXIGP4AWADDR[2] !== 1'bz) && SAXIGP4AWADDR_delay[2]; // rv 0 + assign SAXIGP4AWADDR_in[30] = (SAXIGP4AWADDR[30] !== 1'bz) && SAXIGP4AWADDR_delay[30]; // rv 0 + assign SAXIGP4AWADDR_in[31] = (SAXIGP4AWADDR[31] !== 1'bz) && SAXIGP4AWADDR_delay[31]; // rv 0 + assign SAXIGP4AWADDR_in[32] = (SAXIGP4AWADDR[32] !== 1'bz) && SAXIGP4AWADDR_delay[32]; // rv 0 + assign SAXIGP4AWADDR_in[33] = (SAXIGP4AWADDR[33] !== 1'bz) && SAXIGP4AWADDR_delay[33]; // rv 0 + assign SAXIGP4AWADDR_in[34] = (SAXIGP4AWADDR[34] !== 1'bz) && SAXIGP4AWADDR_delay[34]; // rv 0 + assign SAXIGP4AWADDR_in[35] = (SAXIGP4AWADDR[35] !== 1'bz) && SAXIGP4AWADDR_delay[35]; // rv 0 + assign SAXIGP4AWADDR_in[36] = (SAXIGP4AWADDR[36] !== 1'bz) && SAXIGP4AWADDR_delay[36]; // rv 0 + assign SAXIGP4AWADDR_in[37] = (SAXIGP4AWADDR[37] !== 1'bz) && SAXIGP4AWADDR_delay[37]; // rv 0 + assign SAXIGP4AWADDR_in[38] = (SAXIGP4AWADDR[38] !== 1'bz) && SAXIGP4AWADDR_delay[38]; // rv 0 + assign SAXIGP4AWADDR_in[39] = (SAXIGP4AWADDR[39] !== 1'bz) && SAXIGP4AWADDR_delay[39]; // rv 0 + assign SAXIGP4AWADDR_in[3] = (SAXIGP4AWADDR[3] !== 1'bz) && SAXIGP4AWADDR_delay[3]; // rv 0 + assign SAXIGP4AWADDR_in[40] = (SAXIGP4AWADDR[40] !== 1'bz) && SAXIGP4AWADDR_delay[40]; // rv 0 + assign SAXIGP4AWADDR_in[41] = (SAXIGP4AWADDR[41] !== 1'bz) && SAXIGP4AWADDR_delay[41]; // rv 0 + assign SAXIGP4AWADDR_in[42] = (SAXIGP4AWADDR[42] !== 1'bz) && SAXIGP4AWADDR_delay[42]; // rv 0 + assign SAXIGP4AWADDR_in[43] = (SAXIGP4AWADDR[43] !== 1'bz) && SAXIGP4AWADDR_delay[43]; // rv 0 + assign SAXIGP4AWADDR_in[44] = (SAXIGP4AWADDR[44] !== 1'bz) && SAXIGP4AWADDR_delay[44]; // rv 0 + assign SAXIGP4AWADDR_in[45] = (SAXIGP4AWADDR[45] !== 1'bz) && SAXIGP4AWADDR_delay[45]; // rv 0 + assign SAXIGP4AWADDR_in[46] = (SAXIGP4AWADDR[46] !== 1'bz) && SAXIGP4AWADDR_delay[46]; // rv 0 + assign SAXIGP4AWADDR_in[47] = (SAXIGP4AWADDR[47] !== 1'bz) && SAXIGP4AWADDR_delay[47]; // rv 0 + assign SAXIGP4AWADDR_in[48] = (SAXIGP4AWADDR[48] !== 1'bz) && SAXIGP4AWADDR_delay[48]; // rv 0 + assign SAXIGP4AWADDR_in[4] = (SAXIGP4AWADDR[4] !== 1'bz) && SAXIGP4AWADDR_delay[4]; // rv 0 + assign SAXIGP4AWADDR_in[5] = (SAXIGP4AWADDR[5] !== 1'bz) && SAXIGP4AWADDR_delay[5]; // rv 0 + assign SAXIGP4AWADDR_in[6] = (SAXIGP4AWADDR[6] !== 1'bz) && SAXIGP4AWADDR_delay[6]; // rv 0 + assign SAXIGP4AWADDR_in[7] = (SAXIGP4AWADDR[7] !== 1'bz) && SAXIGP4AWADDR_delay[7]; // rv 0 + assign SAXIGP4AWADDR_in[8] = (SAXIGP4AWADDR[8] !== 1'bz) && SAXIGP4AWADDR_delay[8]; // rv 0 + assign SAXIGP4AWADDR_in[9] = (SAXIGP4AWADDR[9] !== 1'bz) && SAXIGP4AWADDR_delay[9]; // rv 0 + assign SAXIGP4AWBURST_in[0] = (SAXIGP4AWBURST[0] !== 1'bz) && SAXIGP4AWBURST_delay[0]; // rv 0 + assign SAXIGP4AWBURST_in[1] = (SAXIGP4AWBURST[1] !== 1'bz) && SAXIGP4AWBURST_delay[1]; // rv 0 + assign SAXIGP4AWCACHE_in[0] = (SAXIGP4AWCACHE[0] !== 1'bz) && SAXIGP4AWCACHE_delay[0]; // rv 0 + assign SAXIGP4AWCACHE_in[1] = (SAXIGP4AWCACHE[1] !== 1'bz) && SAXIGP4AWCACHE_delay[1]; // rv 0 + assign SAXIGP4AWCACHE_in[2] = (SAXIGP4AWCACHE[2] !== 1'bz) && SAXIGP4AWCACHE_delay[2]; // rv 0 + assign SAXIGP4AWCACHE_in[3] = (SAXIGP4AWCACHE[3] !== 1'bz) && SAXIGP4AWCACHE_delay[3]; // rv 0 + assign SAXIGP4AWID_in[0] = (SAXIGP4AWID[0] !== 1'bz) && SAXIGP4AWID_delay[0]; // rv 0 + assign SAXIGP4AWID_in[1] = (SAXIGP4AWID[1] !== 1'bz) && SAXIGP4AWID_delay[1]; // rv 0 + assign SAXIGP4AWID_in[2] = (SAXIGP4AWID[2] !== 1'bz) && SAXIGP4AWID_delay[2]; // rv 0 + assign SAXIGP4AWID_in[3] = (SAXIGP4AWID[3] !== 1'bz) && SAXIGP4AWID_delay[3]; // rv 0 + assign SAXIGP4AWID_in[4] = (SAXIGP4AWID[4] !== 1'bz) && SAXIGP4AWID_delay[4]; // rv 0 + assign SAXIGP4AWID_in[5] = (SAXIGP4AWID[5] !== 1'bz) && SAXIGP4AWID_delay[5]; // rv 0 + assign SAXIGP4AWLEN_in[0] = (SAXIGP4AWLEN[0] !== 1'bz) && SAXIGP4AWLEN_delay[0]; // rv 0 + assign SAXIGP4AWLEN_in[1] = (SAXIGP4AWLEN[1] !== 1'bz) && SAXIGP4AWLEN_delay[1]; // rv 0 + assign SAXIGP4AWLEN_in[2] = (SAXIGP4AWLEN[2] !== 1'bz) && SAXIGP4AWLEN_delay[2]; // rv 0 + assign SAXIGP4AWLEN_in[3] = (SAXIGP4AWLEN[3] !== 1'bz) && SAXIGP4AWLEN_delay[3]; // rv 0 + assign SAXIGP4AWLEN_in[4] = (SAXIGP4AWLEN[4] !== 1'bz) && SAXIGP4AWLEN_delay[4]; // rv 0 + assign SAXIGP4AWLEN_in[5] = (SAXIGP4AWLEN[5] !== 1'bz) && SAXIGP4AWLEN_delay[5]; // rv 0 + assign SAXIGP4AWLEN_in[6] = (SAXIGP4AWLEN[6] !== 1'bz) && SAXIGP4AWLEN_delay[6]; // rv 0 + assign SAXIGP4AWLEN_in[7] = (SAXIGP4AWLEN[7] !== 1'bz) && SAXIGP4AWLEN_delay[7]; // rv 0 + assign SAXIGP4AWLOCK_in = (SAXIGP4AWLOCK !== 1'bz) && SAXIGP4AWLOCK_delay; // rv 0 + assign SAXIGP4AWPROT_in[0] = (SAXIGP4AWPROT[0] !== 1'bz) && SAXIGP4AWPROT_delay[0]; // rv 0 + assign SAXIGP4AWPROT_in[1] = (SAXIGP4AWPROT[1] !== 1'bz) && SAXIGP4AWPROT_delay[1]; // rv 0 + assign SAXIGP4AWPROT_in[2] = (SAXIGP4AWPROT[2] !== 1'bz) && SAXIGP4AWPROT_delay[2]; // rv 0 + assign SAXIGP4AWQOS_in[0] = (SAXIGP4AWQOS[0] !== 1'bz) && SAXIGP4AWQOS_delay[0]; // rv 0 + assign SAXIGP4AWQOS_in[1] = (SAXIGP4AWQOS[1] !== 1'bz) && SAXIGP4AWQOS_delay[1]; // rv 0 + assign SAXIGP4AWQOS_in[2] = (SAXIGP4AWQOS[2] !== 1'bz) && SAXIGP4AWQOS_delay[2]; // rv 0 + assign SAXIGP4AWQOS_in[3] = (SAXIGP4AWQOS[3] !== 1'bz) && SAXIGP4AWQOS_delay[3]; // rv 0 + assign SAXIGP4AWSIZE_in[0] = (SAXIGP4AWSIZE[0] !== 1'bz) && SAXIGP4AWSIZE_delay[0]; // rv 0 + assign SAXIGP4AWSIZE_in[1] = (SAXIGP4AWSIZE[1] !== 1'bz) && SAXIGP4AWSIZE_delay[1]; // rv 0 + assign SAXIGP4AWSIZE_in[2] = (SAXIGP4AWSIZE[2] !== 1'bz) && SAXIGP4AWSIZE_delay[2]; // rv 0 + assign SAXIGP4AWUSER_in = (SAXIGP4AWUSER !== 1'bz) && SAXIGP4AWUSER_delay; // rv 0 + assign SAXIGP4AWVALID_in = (SAXIGP4AWVALID !== 1'bz) && SAXIGP4AWVALID_delay; // rv 0 + assign SAXIGP4BREADY_in = (SAXIGP4BREADY !== 1'bz) && SAXIGP4BREADY_delay; // rv 0 + assign SAXIGP4RCLK_in = (SAXIGP4RCLK !== 1'bz) && SAXIGP4RCLK_delay; // rv 0 + assign SAXIGP4RREADY_in = (SAXIGP4RREADY !== 1'bz) && SAXIGP4RREADY_delay; // rv 0 + assign SAXIGP4WCLK_in = (SAXIGP4WCLK !== 1'bz) && SAXIGP4WCLK_delay; // rv 0 + assign SAXIGP4WDATA_in[0] = (SAXIGP4WDATA[0] !== 1'bz) && SAXIGP4WDATA_delay[0]; // rv 0 + assign SAXIGP4WDATA_in[100] = (SAXIGP4WDATA[100] !== 1'bz) && SAXIGP4WDATA_delay[100]; // rv 0 + assign SAXIGP4WDATA_in[101] = (SAXIGP4WDATA[101] !== 1'bz) && SAXIGP4WDATA_delay[101]; // rv 0 + assign SAXIGP4WDATA_in[102] = (SAXIGP4WDATA[102] !== 1'bz) && SAXIGP4WDATA_delay[102]; // rv 0 + assign SAXIGP4WDATA_in[103] = (SAXIGP4WDATA[103] !== 1'bz) && SAXIGP4WDATA_delay[103]; // rv 0 + assign SAXIGP4WDATA_in[104] = (SAXIGP4WDATA[104] !== 1'bz) && SAXIGP4WDATA_delay[104]; // rv 0 + assign SAXIGP4WDATA_in[105] = (SAXIGP4WDATA[105] !== 1'bz) && SAXIGP4WDATA_delay[105]; // rv 0 + assign SAXIGP4WDATA_in[106] = (SAXIGP4WDATA[106] !== 1'bz) && SAXIGP4WDATA_delay[106]; // rv 0 + assign SAXIGP4WDATA_in[107] = (SAXIGP4WDATA[107] !== 1'bz) && SAXIGP4WDATA_delay[107]; // rv 0 + assign SAXIGP4WDATA_in[108] = (SAXIGP4WDATA[108] !== 1'bz) && SAXIGP4WDATA_delay[108]; // rv 0 + assign SAXIGP4WDATA_in[109] = (SAXIGP4WDATA[109] !== 1'bz) && SAXIGP4WDATA_delay[109]; // rv 0 + assign SAXIGP4WDATA_in[10] = (SAXIGP4WDATA[10] !== 1'bz) && SAXIGP4WDATA_delay[10]; // rv 0 + assign SAXIGP4WDATA_in[110] = (SAXIGP4WDATA[110] !== 1'bz) && SAXIGP4WDATA_delay[110]; // rv 0 + assign SAXIGP4WDATA_in[111] = (SAXIGP4WDATA[111] !== 1'bz) && SAXIGP4WDATA_delay[111]; // rv 0 + assign SAXIGP4WDATA_in[112] = (SAXIGP4WDATA[112] !== 1'bz) && SAXIGP4WDATA_delay[112]; // rv 0 + assign SAXIGP4WDATA_in[113] = (SAXIGP4WDATA[113] !== 1'bz) && SAXIGP4WDATA_delay[113]; // rv 0 + assign SAXIGP4WDATA_in[114] = (SAXIGP4WDATA[114] !== 1'bz) && SAXIGP4WDATA_delay[114]; // rv 0 + assign SAXIGP4WDATA_in[115] = (SAXIGP4WDATA[115] !== 1'bz) && SAXIGP4WDATA_delay[115]; // rv 0 + assign SAXIGP4WDATA_in[116] = (SAXIGP4WDATA[116] !== 1'bz) && SAXIGP4WDATA_delay[116]; // rv 0 + assign SAXIGP4WDATA_in[117] = (SAXIGP4WDATA[117] !== 1'bz) && SAXIGP4WDATA_delay[117]; // rv 0 + assign SAXIGP4WDATA_in[118] = (SAXIGP4WDATA[118] !== 1'bz) && SAXIGP4WDATA_delay[118]; // rv 0 + assign SAXIGP4WDATA_in[119] = (SAXIGP4WDATA[119] !== 1'bz) && SAXIGP4WDATA_delay[119]; // rv 0 + assign SAXIGP4WDATA_in[11] = (SAXIGP4WDATA[11] !== 1'bz) && SAXIGP4WDATA_delay[11]; // rv 0 + assign SAXIGP4WDATA_in[120] = (SAXIGP4WDATA[120] !== 1'bz) && SAXIGP4WDATA_delay[120]; // rv 0 + assign SAXIGP4WDATA_in[121] = (SAXIGP4WDATA[121] !== 1'bz) && SAXIGP4WDATA_delay[121]; // rv 0 + assign SAXIGP4WDATA_in[122] = (SAXIGP4WDATA[122] !== 1'bz) && SAXIGP4WDATA_delay[122]; // rv 0 + assign SAXIGP4WDATA_in[123] = (SAXIGP4WDATA[123] !== 1'bz) && SAXIGP4WDATA_delay[123]; // rv 0 + assign SAXIGP4WDATA_in[124] = (SAXIGP4WDATA[124] !== 1'bz) && SAXIGP4WDATA_delay[124]; // rv 0 + assign SAXIGP4WDATA_in[125] = (SAXIGP4WDATA[125] !== 1'bz) && SAXIGP4WDATA_delay[125]; // rv 0 + assign SAXIGP4WDATA_in[126] = (SAXIGP4WDATA[126] !== 1'bz) && SAXIGP4WDATA_delay[126]; // rv 0 + assign SAXIGP4WDATA_in[127] = (SAXIGP4WDATA[127] !== 1'bz) && SAXIGP4WDATA_delay[127]; // rv 0 + assign SAXIGP4WDATA_in[12] = (SAXIGP4WDATA[12] !== 1'bz) && SAXIGP4WDATA_delay[12]; // rv 0 + assign SAXIGP4WDATA_in[13] = (SAXIGP4WDATA[13] !== 1'bz) && SAXIGP4WDATA_delay[13]; // rv 0 + assign SAXIGP4WDATA_in[14] = (SAXIGP4WDATA[14] !== 1'bz) && SAXIGP4WDATA_delay[14]; // rv 0 + assign SAXIGP4WDATA_in[15] = (SAXIGP4WDATA[15] !== 1'bz) && SAXIGP4WDATA_delay[15]; // rv 0 + assign SAXIGP4WDATA_in[16] = (SAXIGP4WDATA[16] !== 1'bz) && SAXIGP4WDATA_delay[16]; // rv 0 + assign SAXIGP4WDATA_in[17] = (SAXIGP4WDATA[17] !== 1'bz) && SAXIGP4WDATA_delay[17]; // rv 0 + assign SAXIGP4WDATA_in[18] = (SAXIGP4WDATA[18] !== 1'bz) && SAXIGP4WDATA_delay[18]; // rv 0 + assign SAXIGP4WDATA_in[19] = (SAXIGP4WDATA[19] !== 1'bz) && SAXIGP4WDATA_delay[19]; // rv 0 + assign SAXIGP4WDATA_in[1] = (SAXIGP4WDATA[1] !== 1'bz) && SAXIGP4WDATA_delay[1]; // rv 0 + assign SAXIGP4WDATA_in[20] = (SAXIGP4WDATA[20] !== 1'bz) && SAXIGP4WDATA_delay[20]; // rv 0 + assign SAXIGP4WDATA_in[21] = (SAXIGP4WDATA[21] !== 1'bz) && SAXIGP4WDATA_delay[21]; // rv 0 + assign SAXIGP4WDATA_in[22] = (SAXIGP4WDATA[22] !== 1'bz) && SAXIGP4WDATA_delay[22]; // rv 0 + assign SAXIGP4WDATA_in[23] = (SAXIGP4WDATA[23] !== 1'bz) && SAXIGP4WDATA_delay[23]; // rv 0 + assign SAXIGP4WDATA_in[24] = (SAXIGP4WDATA[24] !== 1'bz) && SAXIGP4WDATA_delay[24]; // rv 0 + assign SAXIGP4WDATA_in[25] = (SAXIGP4WDATA[25] !== 1'bz) && SAXIGP4WDATA_delay[25]; // rv 0 + assign SAXIGP4WDATA_in[26] = (SAXIGP4WDATA[26] !== 1'bz) && SAXIGP4WDATA_delay[26]; // rv 0 + assign SAXIGP4WDATA_in[27] = (SAXIGP4WDATA[27] !== 1'bz) && SAXIGP4WDATA_delay[27]; // rv 0 + assign SAXIGP4WDATA_in[28] = (SAXIGP4WDATA[28] !== 1'bz) && SAXIGP4WDATA_delay[28]; // rv 0 + assign SAXIGP4WDATA_in[29] = (SAXIGP4WDATA[29] !== 1'bz) && SAXIGP4WDATA_delay[29]; // rv 0 + assign SAXIGP4WDATA_in[2] = (SAXIGP4WDATA[2] !== 1'bz) && SAXIGP4WDATA_delay[2]; // rv 0 + assign SAXIGP4WDATA_in[30] = (SAXIGP4WDATA[30] !== 1'bz) && SAXIGP4WDATA_delay[30]; // rv 0 + assign SAXIGP4WDATA_in[31] = (SAXIGP4WDATA[31] !== 1'bz) && SAXIGP4WDATA_delay[31]; // rv 0 + assign SAXIGP4WDATA_in[32] = (SAXIGP4WDATA[32] !== 1'bz) && SAXIGP4WDATA_delay[32]; // rv 0 + assign SAXIGP4WDATA_in[33] = (SAXIGP4WDATA[33] !== 1'bz) && SAXIGP4WDATA_delay[33]; // rv 0 + assign SAXIGP4WDATA_in[34] = (SAXIGP4WDATA[34] !== 1'bz) && SAXIGP4WDATA_delay[34]; // rv 0 + assign SAXIGP4WDATA_in[35] = (SAXIGP4WDATA[35] !== 1'bz) && SAXIGP4WDATA_delay[35]; // rv 0 + assign SAXIGP4WDATA_in[36] = (SAXIGP4WDATA[36] !== 1'bz) && SAXIGP4WDATA_delay[36]; // rv 0 + assign SAXIGP4WDATA_in[37] = (SAXIGP4WDATA[37] !== 1'bz) && SAXIGP4WDATA_delay[37]; // rv 0 + assign SAXIGP4WDATA_in[38] = (SAXIGP4WDATA[38] !== 1'bz) && SAXIGP4WDATA_delay[38]; // rv 0 + assign SAXIGP4WDATA_in[39] = (SAXIGP4WDATA[39] !== 1'bz) && SAXIGP4WDATA_delay[39]; // rv 0 + assign SAXIGP4WDATA_in[3] = (SAXIGP4WDATA[3] !== 1'bz) && SAXIGP4WDATA_delay[3]; // rv 0 + assign SAXIGP4WDATA_in[40] = (SAXIGP4WDATA[40] !== 1'bz) && SAXIGP4WDATA_delay[40]; // rv 0 + assign SAXIGP4WDATA_in[41] = (SAXIGP4WDATA[41] !== 1'bz) && SAXIGP4WDATA_delay[41]; // rv 0 + assign SAXIGP4WDATA_in[42] = (SAXIGP4WDATA[42] !== 1'bz) && SAXIGP4WDATA_delay[42]; // rv 0 + assign SAXIGP4WDATA_in[43] = (SAXIGP4WDATA[43] !== 1'bz) && SAXIGP4WDATA_delay[43]; // rv 0 + assign SAXIGP4WDATA_in[44] = (SAXIGP4WDATA[44] !== 1'bz) && SAXIGP4WDATA_delay[44]; // rv 0 + assign SAXIGP4WDATA_in[45] = (SAXIGP4WDATA[45] !== 1'bz) && SAXIGP4WDATA_delay[45]; // rv 0 + assign SAXIGP4WDATA_in[46] = (SAXIGP4WDATA[46] !== 1'bz) && SAXIGP4WDATA_delay[46]; // rv 0 + assign SAXIGP4WDATA_in[47] = (SAXIGP4WDATA[47] !== 1'bz) && SAXIGP4WDATA_delay[47]; // rv 0 + assign SAXIGP4WDATA_in[48] = (SAXIGP4WDATA[48] !== 1'bz) && SAXIGP4WDATA_delay[48]; // rv 0 + assign SAXIGP4WDATA_in[49] = (SAXIGP4WDATA[49] !== 1'bz) && SAXIGP4WDATA_delay[49]; // rv 0 + assign SAXIGP4WDATA_in[4] = (SAXIGP4WDATA[4] !== 1'bz) && SAXIGP4WDATA_delay[4]; // rv 0 + assign SAXIGP4WDATA_in[50] = (SAXIGP4WDATA[50] !== 1'bz) && SAXIGP4WDATA_delay[50]; // rv 0 + assign SAXIGP4WDATA_in[51] = (SAXIGP4WDATA[51] !== 1'bz) && SAXIGP4WDATA_delay[51]; // rv 0 + assign SAXIGP4WDATA_in[52] = (SAXIGP4WDATA[52] !== 1'bz) && SAXIGP4WDATA_delay[52]; // rv 0 + assign SAXIGP4WDATA_in[53] = (SAXIGP4WDATA[53] !== 1'bz) && SAXIGP4WDATA_delay[53]; // rv 0 + assign SAXIGP4WDATA_in[54] = (SAXIGP4WDATA[54] !== 1'bz) && SAXIGP4WDATA_delay[54]; // rv 0 + assign SAXIGP4WDATA_in[55] = (SAXIGP4WDATA[55] !== 1'bz) && SAXIGP4WDATA_delay[55]; // rv 0 + assign SAXIGP4WDATA_in[56] = (SAXIGP4WDATA[56] !== 1'bz) && SAXIGP4WDATA_delay[56]; // rv 0 + assign SAXIGP4WDATA_in[57] = (SAXIGP4WDATA[57] !== 1'bz) && SAXIGP4WDATA_delay[57]; // rv 0 + assign SAXIGP4WDATA_in[58] = (SAXIGP4WDATA[58] !== 1'bz) && SAXIGP4WDATA_delay[58]; // rv 0 + assign SAXIGP4WDATA_in[59] = (SAXIGP4WDATA[59] !== 1'bz) && SAXIGP4WDATA_delay[59]; // rv 0 + assign SAXIGP4WDATA_in[5] = (SAXIGP4WDATA[5] !== 1'bz) && SAXIGP4WDATA_delay[5]; // rv 0 + assign SAXIGP4WDATA_in[60] = (SAXIGP4WDATA[60] !== 1'bz) && SAXIGP4WDATA_delay[60]; // rv 0 + assign SAXIGP4WDATA_in[61] = (SAXIGP4WDATA[61] !== 1'bz) && SAXIGP4WDATA_delay[61]; // rv 0 + assign SAXIGP4WDATA_in[62] = (SAXIGP4WDATA[62] !== 1'bz) && SAXIGP4WDATA_delay[62]; // rv 0 + assign SAXIGP4WDATA_in[63] = (SAXIGP4WDATA[63] !== 1'bz) && SAXIGP4WDATA_delay[63]; // rv 0 + assign SAXIGP4WDATA_in[64] = (SAXIGP4WDATA[64] !== 1'bz) && SAXIGP4WDATA_delay[64]; // rv 0 + assign SAXIGP4WDATA_in[65] = (SAXIGP4WDATA[65] !== 1'bz) && SAXIGP4WDATA_delay[65]; // rv 0 + assign SAXIGP4WDATA_in[66] = (SAXIGP4WDATA[66] !== 1'bz) && SAXIGP4WDATA_delay[66]; // rv 0 + assign SAXIGP4WDATA_in[67] = (SAXIGP4WDATA[67] !== 1'bz) && SAXIGP4WDATA_delay[67]; // rv 0 + assign SAXIGP4WDATA_in[68] = (SAXIGP4WDATA[68] !== 1'bz) && SAXIGP4WDATA_delay[68]; // rv 0 + assign SAXIGP4WDATA_in[69] = (SAXIGP4WDATA[69] !== 1'bz) && SAXIGP4WDATA_delay[69]; // rv 0 + assign SAXIGP4WDATA_in[6] = (SAXIGP4WDATA[6] !== 1'bz) && SAXIGP4WDATA_delay[6]; // rv 0 + assign SAXIGP4WDATA_in[70] = (SAXIGP4WDATA[70] !== 1'bz) && SAXIGP4WDATA_delay[70]; // rv 0 + assign SAXIGP4WDATA_in[71] = (SAXIGP4WDATA[71] !== 1'bz) && SAXIGP4WDATA_delay[71]; // rv 0 + assign SAXIGP4WDATA_in[72] = (SAXIGP4WDATA[72] !== 1'bz) && SAXIGP4WDATA_delay[72]; // rv 0 + assign SAXIGP4WDATA_in[73] = (SAXIGP4WDATA[73] !== 1'bz) && SAXIGP4WDATA_delay[73]; // rv 0 + assign SAXIGP4WDATA_in[74] = (SAXIGP4WDATA[74] !== 1'bz) && SAXIGP4WDATA_delay[74]; // rv 0 + assign SAXIGP4WDATA_in[75] = (SAXIGP4WDATA[75] !== 1'bz) && SAXIGP4WDATA_delay[75]; // rv 0 + assign SAXIGP4WDATA_in[76] = (SAXIGP4WDATA[76] !== 1'bz) && SAXIGP4WDATA_delay[76]; // rv 0 + assign SAXIGP4WDATA_in[77] = (SAXIGP4WDATA[77] !== 1'bz) && SAXIGP4WDATA_delay[77]; // rv 0 + assign SAXIGP4WDATA_in[78] = (SAXIGP4WDATA[78] !== 1'bz) && SAXIGP4WDATA_delay[78]; // rv 0 + assign SAXIGP4WDATA_in[79] = (SAXIGP4WDATA[79] !== 1'bz) && SAXIGP4WDATA_delay[79]; // rv 0 + assign SAXIGP4WDATA_in[7] = (SAXIGP4WDATA[7] !== 1'bz) && SAXIGP4WDATA_delay[7]; // rv 0 + assign SAXIGP4WDATA_in[80] = (SAXIGP4WDATA[80] !== 1'bz) && SAXIGP4WDATA_delay[80]; // rv 0 + assign SAXIGP4WDATA_in[81] = (SAXIGP4WDATA[81] !== 1'bz) && SAXIGP4WDATA_delay[81]; // rv 0 + assign SAXIGP4WDATA_in[82] = (SAXIGP4WDATA[82] !== 1'bz) && SAXIGP4WDATA_delay[82]; // rv 0 + assign SAXIGP4WDATA_in[83] = (SAXIGP4WDATA[83] !== 1'bz) && SAXIGP4WDATA_delay[83]; // rv 0 + assign SAXIGP4WDATA_in[84] = (SAXIGP4WDATA[84] !== 1'bz) && SAXIGP4WDATA_delay[84]; // rv 0 + assign SAXIGP4WDATA_in[85] = (SAXIGP4WDATA[85] !== 1'bz) && SAXIGP4WDATA_delay[85]; // rv 0 + assign SAXIGP4WDATA_in[86] = (SAXIGP4WDATA[86] !== 1'bz) && SAXIGP4WDATA_delay[86]; // rv 0 + assign SAXIGP4WDATA_in[87] = (SAXIGP4WDATA[87] !== 1'bz) && SAXIGP4WDATA_delay[87]; // rv 0 + assign SAXIGP4WDATA_in[88] = (SAXIGP4WDATA[88] !== 1'bz) && SAXIGP4WDATA_delay[88]; // rv 0 + assign SAXIGP4WDATA_in[89] = (SAXIGP4WDATA[89] !== 1'bz) && SAXIGP4WDATA_delay[89]; // rv 0 + assign SAXIGP4WDATA_in[8] = (SAXIGP4WDATA[8] !== 1'bz) && SAXIGP4WDATA_delay[8]; // rv 0 + assign SAXIGP4WDATA_in[90] = (SAXIGP4WDATA[90] !== 1'bz) && SAXIGP4WDATA_delay[90]; // rv 0 + assign SAXIGP4WDATA_in[91] = (SAXIGP4WDATA[91] !== 1'bz) && SAXIGP4WDATA_delay[91]; // rv 0 + assign SAXIGP4WDATA_in[92] = (SAXIGP4WDATA[92] !== 1'bz) && SAXIGP4WDATA_delay[92]; // rv 0 + assign SAXIGP4WDATA_in[93] = (SAXIGP4WDATA[93] !== 1'bz) && SAXIGP4WDATA_delay[93]; // rv 0 + assign SAXIGP4WDATA_in[94] = (SAXIGP4WDATA[94] !== 1'bz) && SAXIGP4WDATA_delay[94]; // rv 0 + assign SAXIGP4WDATA_in[95] = (SAXIGP4WDATA[95] !== 1'bz) && SAXIGP4WDATA_delay[95]; // rv 0 + assign SAXIGP4WDATA_in[96] = (SAXIGP4WDATA[96] !== 1'bz) && SAXIGP4WDATA_delay[96]; // rv 0 + assign SAXIGP4WDATA_in[97] = (SAXIGP4WDATA[97] !== 1'bz) && SAXIGP4WDATA_delay[97]; // rv 0 + assign SAXIGP4WDATA_in[98] = (SAXIGP4WDATA[98] !== 1'bz) && SAXIGP4WDATA_delay[98]; // rv 0 + assign SAXIGP4WDATA_in[99] = (SAXIGP4WDATA[99] !== 1'bz) && SAXIGP4WDATA_delay[99]; // rv 0 + assign SAXIGP4WDATA_in[9] = (SAXIGP4WDATA[9] !== 1'bz) && SAXIGP4WDATA_delay[9]; // rv 0 + assign SAXIGP4WLAST_in = (SAXIGP4WLAST !== 1'bz) && SAXIGP4WLAST_delay; // rv 0 + assign SAXIGP4WSTRB_in[0] = (SAXIGP4WSTRB[0] !== 1'bz) && SAXIGP4WSTRB_delay[0]; // rv 0 + assign SAXIGP4WSTRB_in[10] = (SAXIGP4WSTRB[10] !== 1'bz) && SAXIGP4WSTRB_delay[10]; // rv 0 + assign SAXIGP4WSTRB_in[11] = (SAXIGP4WSTRB[11] !== 1'bz) && SAXIGP4WSTRB_delay[11]; // rv 0 + assign SAXIGP4WSTRB_in[12] = (SAXIGP4WSTRB[12] !== 1'bz) && SAXIGP4WSTRB_delay[12]; // rv 0 + assign SAXIGP4WSTRB_in[13] = (SAXIGP4WSTRB[13] !== 1'bz) && SAXIGP4WSTRB_delay[13]; // rv 0 + assign SAXIGP4WSTRB_in[14] = (SAXIGP4WSTRB[14] !== 1'bz) && SAXIGP4WSTRB_delay[14]; // rv 0 + assign SAXIGP4WSTRB_in[15] = (SAXIGP4WSTRB[15] !== 1'bz) && SAXIGP4WSTRB_delay[15]; // rv 0 + assign SAXIGP4WSTRB_in[1] = (SAXIGP4WSTRB[1] !== 1'bz) && SAXIGP4WSTRB_delay[1]; // rv 0 + assign SAXIGP4WSTRB_in[2] = (SAXIGP4WSTRB[2] !== 1'bz) && SAXIGP4WSTRB_delay[2]; // rv 0 + assign SAXIGP4WSTRB_in[3] = (SAXIGP4WSTRB[3] !== 1'bz) && SAXIGP4WSTRB_delay[3]; // rv 0 + assign SAXIGP4WSTRB_in[4] = (SAXIGP4WSTRB[4] !== 1'bz) && SAXIGP4WSTRB_delay[4]; // rv 0 + assign SAXIGP4WSTRB_in[5] = (SAXIGP4WSTRB[5] !== 1'bz) && SAXIGP4WSTRB_delay[5]; // rv 0 + assign SAXIGP4WSTRB_in[6] = (SAXIGP4WSTRB[6] !== 1'bz) && SAXIGP4WSTRB_delay[6]; // rv 0 + assign SAXIGP4WSTRB_in[7] = (SAXIGP4WSTRB[7] !== 1'bz) && SAXIGP4WSTRB_delay[7]; // rv 0 + assign SAXIGP4WSTRB_in[8] = (SAXIGP4WSTRB[8] !== 1'bz) && SAXIGP4WSTRB_delay[8]; // rv 0 + assign SAXIGP4WSTRB_in[9] = (SAXIGP4WSTRB[9] !== 1'bz) && SAXIGP4WSTRB_delay[9]; // rv 0 + assign SAXIGP4WVALID_in = (SAXIGP4WVALID !== 1'bz) && SAXIGP4WVALID_delay; // rv 0 + assign SAXIGP5ARADDR_in[0] = (SAXIGP5ARADDR[0] !== 1'bz) && SAXIGP5ARADDR_delay[0]; // rv 0 + assign SAXIGP5ARADDR_in[10] = (SAXIGP5ARADDR[10] !== 1'bz) && SAXIGP5ARADDR_delay[10]; // rv 0 + assign SAXIGP5ARADDR_in[11] = (SAXIGP5ARADDR[11] !== 1'bz) && SAXIGP5ARADDR_delay[11]; // rv 0 + assign SAXIGP5ARADDR_in[12] = (SAXIGP5ARADDR[12] !== 1'bz) && SAXIGP5ARADDR_delay[12]; // rv 0 + assign SAXIGP5ARADDR_in[13] = (SAXIGP5ARADDR[13] !== 1'bz) && SAXIGP5ARADDR_delay[13]; // rv 0 + assign SAXIGP5ARADDR_in[14] = (SAXIGP5ARADDR[14] !== 1'bz) && SAXIGP5ARADDR_delay[14]; // rv 0 + assign SAXIGP5ARADDR_in[15] = (SAXIGP5ARADDR[15] !== 1'bz) && SAXIGP5ARADDR_delay[15]; // rv 0 + assign SAXIGP5ARADDR_in[16] = (SAXIGP5ARADDR[16] !== 1'bz) && SAXIGP5ARADDR_delay[16]; // rv 0 + assign SAXIGP5ARADDR_in[17] = (SAXIGP5ARADDR[17] !== 1'bz) && SAXIGP5ARADDR_delay[17]; // rv 0 + assign SAXIGP5ARADDR_in[18] = (SAXIGP5ARADDR[18] !== 1'bz) && SAXIGP5ARADDR_delay[18]; // rv 0 + assign SAXIGP5ARADDR_in[19] = (SAXIGP5ARADDR[19] !== 1'bz) && SAXIGP5ARADDR_delay[19]; // rv 0 + assign SAXIGP5ARADDR_in[1] = (SAXIGP5ARADDR[1] !== 1'bz) && SAXIGP5ARADDR_delay[1]; // rv 0 + assign SAXIGP5ARADDR_in[20] = (SAXIGP5ARADDR[20] !== 1'bz) && SAXIGP5ARADDR_delay[20]; // rv 0 + assign SAXIGP5ARADDR_in[21] = (SAXIGP5ARADDR[21] !== 1'bz) && SAXIGP5ARADDR_delay[21]; // rv 0 + assign SAXIGP5ARADDR_in[22] = (SAXIGP5ARADDR[22] !== 1'bz) && SAXIGP5ARADDR_delay[22]; // rv 0 + assign SAXIGP5ARADDR_in[23] = (SAXIGP5ARADDR[23] !== 1'bz) && SAXIGP5ARADDR_delay[23]; // rv 0 + assign SAXIGP5ARADDR_in[24] = (SAXIGP5ARADDR[24] !== 1'bz) && SAXIGP5ARADDR_delay[24]; // rv 0 + assign SAXIGP5ARADDR_in[25] = (SAXIGP5ARADDR[25] !== 1'bz) && SAXIGP5ARADDR_delay[25]; // rv 0 + assign SAXIGP5ARADDR_in[26] = (SAXIGP5ARADDR[26] !== 1'bz) && SAXIGP5ARADDR_delay[26]; // rv 0 + assign SAXIGP5ARADDR_in[27] = (SAXIGP5ARADDR[27] !== 1'bz) && SAXIGP5ARADDR_delay[27]; // rv 0 + assign SAXIGP5ARADDR_in[28] = (SAXIGP5ARADDR[28] !== 1'bz) && SAXIGP5ARADDR_delay[28]; // rv 0 + assign SAXIGP5ARADDR_in[29] = (SAXIGP5ARADDR[29] !== 1'bz) && SAXIGP5ARADDR_delay[29]; // rv 0 + assign SAXIGP5ARADDR_in[2] = (SAXIGP5ARADDR[2] !== 1'bz) && SAXIGP5ARADDR_delay[2]; // rv 0 + assign SAXIGP5ARADDR_in[30] = (SAXIGP5ARADDR[30] !== 1'bz) && SAXIGP5ARADDR_delay[30]; // rv 0 + assign SAXIGP5ARADDR_in[31] = (SAXIGP5ARADDR[31] !== 1'bz) && SAXIGP5ARADDR_delay[31]; // rv 0 + assign SAXIGP5ARADDR_in[32] = (SAXIGP5ARADDR[32] !== 1'bz) && SAXIGP5ARADDR_delay[32]; // rv 0 + assign SAXIGP5ARADDR_in[33] = (SAXIGP5ARADDR[33] !== 1'bz) && SAXIGP5ARADDR_delay[33]; // rv 0 + assign SAXIGP5ARADDR_in[34] = (SAXIGP5ARADDR[34] !== 1'bz) && SAXIGP5ARADDR_delay[34]; // rv 0 + assign SAXIGP5ARADDR_in[35] = (SAXIGP5ARADDR[35] !== 1'bz) && SAXIGP5ARADDR_delay[35]; // rv 0 + assign SAXIGP5ARADDR_in[36] = (SAXIGP5ARADDR[36] !== 1'bz) && SAXIGP5ARADDR_delay[36]; // rv 0 + assign SAXIGP5ARADDR_in[37] = (SAXIGP5ARADDR[37] !== 1'bz) && SAXIGP5ARADDR_delay[37]; // rv 0 + assign SAXIGP5ARADDR_in[38] = (SAXIGP5ARADDR[38] !== 1'bz) && SAXIGP5ARADDR_delay[38]; // rv 0 + assign SAXIGP5ARADDR_in[39] = (SAXIGP5ARADDR[39] !== 1'bz) && SAXIGP5ARADDR_delay[39]; // rv 0 + assign SAXIGP5ARADDR_in[3] = (SAXIGP5ARADDR[3] !== 1'bz) && SAXIGP5ARADDR_delay[3]; // rv 0 + assign SAXIGP5ARADDR_in[40] = (SAXIGP5ARADDR[40] !== 1'bz) && SAXIGP5ARADDR_delay[40]; // rv 0 + assign SAXIGP5ARADDR_in[41] = (SAXIGP5ARADDR[41] !== 1'bz) && SAXIGP5ARADDR_delay[41]; // rv 0 + assign SAXIGP5ARADDR_in[42] = (SAXIGP5ARADDR[42] !== 1'bz) && SAXIGP5ARADDR_delay[42]; // rv 0 + assign SAXIGP5ARADDR_in[43] = (SAXIGP5ARADDR[43] !== 1'bz) && SAXIGP5ARADDR_delay[43]; // rv 0 + assign SAXIGP5ARADDR_in[44] = (SAXIGP5ARADDR[44] !== 1'bz) && SAXIGP5ARADDR_delay[44]; // rv 0 + assign SAXIGP5ARADDR_in[45] = (SAXIGP5ARADDR[45] !== 1'bz) && SAXIGP5ARADDR_delay[45]; // rv 0 + assign SAXIGP5ARADDR_in[46] = (SAXIGP5ARADDR[46] !== 1'bz) && SAXIGP5ARADDR_delay[46]; // rv 0 + assign SAXIGP5ARADDR_in[47] = (SAXIGP5ARADDR[47] !== 1'bz) && SAXIGP5ARADDR_delay[47]; // rv 0 + assign SAXIGP5ARADDR_in[48] = (SAXIGP5ARADDR[48] !== 1'bz) && SAXIGP5ARADDR_delay[48]; // rv 0 + assign SAXIGP5ARADDR_in[4] = (SAXIGP5ARADDR[4] !== 1'bz) && SAXIGP5ARADDR_delay[4]; // rv 0 + assign SAXIGP5ARADDR_in[5] = (SAXIGP5ARADDR[5] !== 1'bz) && SAXIGP5ARADDR_delay[5]; // rv 0 + assign SAXIGP5ARADDR_in[6] = (SAXIGP5ARADDR[6] !== 1'bz) && SAXIGP5ARADDR_delay[6]; // rv 0 + assign SAXIGP5ARADDR_in[7] = (SAXIGP5ARADDR[7] !== 1'bz) && SAXIGP5ARADDR_delay[7]; // rv 0 + assign SAXIGP5ARADDR_in[8] = (SAXIGP5ARADDR[8] !== 1'bz) && SAXIGP5ARADDR_delay[8]; // rv 0 + assign SAXIGP5ARADDR_in[9] = (SAXIGP5ARADDR[9] !== 1'bz) && SAXIGP5ARADDR_delay[9]; // rv 0 + assign SAXIGP5ARBURST_in[0] = (SAXIGP5ARBURST[0] !== 1'bz) && SAXIGP5ARBURST_delay[0]; // rv 0 + assign SAXIGP5ARBURST_in[1] = (SAXIGP5ARBURST[1] !== 1'bz) && SAXIGP5ARBURST_delay[1]; // rv 0 + assign SAXIGP5ARCACHE_in[0] = (SAXIGP5ARCACHE[0] !== 1'bz) && SAXIGP5ARCACHE_delay[0]; // rv 0 + assign SAXIGP5ARCACHE_in[1] = (SAXIGP5ARCACHE[1] !== 1'bz) && SAXIGP5ARCACHE_delay[1]; // rv 0 + assign SAXIGP5ARCACHE_in[2] = (SAXIGP5ARCACHE[2] !== 1'bz) && SAXIGP5ARCACHE_delay[2]; // rv 0 + assign SAXIGP5ARCACHE_in[3] = (SAXIGP5ARCACHE[3] !== 1'bz) && SAXIGP5ARCACHE_delay[3]; // rv 0 + assign SAXIGP5ARID_in[0] = (SAXIGP5ARID[0] !== 1'bz) && SAXIGP5ARID_delay[0]; // rv 0 + assign SAXIGP5ARID_in[1] = (SAXIGP5ARID[1] !== 1'bz) && SAXIGP5ARID_delay[1]; // rv 0 + assign SAXIGP5ARID_in[2] = (SAXIGP5ARID[2] !== 1'bz) && SAXIGP5ARID_delay[2]; // rv 0 + assign SAXIGP5ARID_in[3] = (SAXIGP5ARID[3] !== 1'bz) && SAXIGP5ARID_delay[3]; // rv 0 + assign SAXIGP5ARID_in[4] = (SAXIGP5ARID[4] !== 1'bz) && SAXIGP5ARID_delay[4]; // rv 0 + assign SAXIGP5ARID_in[5] = (SAXIGP5ARID[5] !== 1'bz) && SAXIGP5ARID_delay[5]; // rv 0 + assign SAXIGP5ARLEN_in[0] = (SAXIGP5ARLEN[0] !== 1'bz) && SAXIGP5ARLEN_delay[0]; // rv 0 + assign SAXIGP5ARLEN_in[1] = (SAXIGP5ARLEN[1] !== 1'bz) && SAXIGP5ARLEN_delay[1]; // rv 0 + assign SAXIGP5ARLEN_in[2] = (SAXIGP5ARLEN[2] !== 1'bz) && SAXIGP5ARLEN_delay[2]; // rv 0 + assign SAXIGP5ARLEN_in[3] = (SAXIGP5ARLEN[3] !== 1'bz) && SAXIGP5ARLEN_delay[3]; // rv 0 + assign SAXIGP5ARLEN_in[4] = (SAXIGP5ARLEN[4] !== 1'bz) && SAXIGP5ARLEN_delay[4]; // rv 0 + assign SAXIGP5ARLEN_in[5] = (SAXIGP5ARLEN[5] !== 1'bz) && SAXIGP5ARLEN_delay[5]; // rv 0 + assign SAXIGP5ARLEN_in[6] = (SAXIGP5ARLEN[6] !== 1'bz) && SAXIGP5ARLEN_delay[6]; // rv 0 + assign SAXIGP5ARLEN_in[7] = (SAXIGP5ARLEN[7] !== 1'bz) && SAXIGP5ARLEN_delay[7]; // rv 0 + assign SAXIGP5ARLOCK_in = (SAXIGP5ARLOCK !== 1'bz) && SAXIGP5ARLOCK_delay; // rv 0 + assign SAXIGP5ARPROT_in[0] = (SAXIGP5ARPROT[0] !== 1'bz) && SAXIGP5ARPROT_delay[0]; // rv 0 + assign SAXIGP5ARPROT_in[1] = (SAXIGP5ARPROT[1] !== 1'bz) && SAXIGP5ARPROT_delay[1]; // rv 0 + assign SAXIGP5ARPROT_in[2] = (SAXIGP5ARPROT[2] !== 1'bz) && SAXIGP5ARPROT_delay[2]; // rv 0 + assign SAXIGP5ARQOS_in[0] = (SAXIGP5ARQOS[0] !== 1'bz) && SAXIGP5ARQOS_delay[0]; // rv 0 + assign SAXIGP5ARQOS_in[1] = (SAXIGP5ARQOS[1] !== 1'bz) && SAXIGP5ARQOS_delay[1]; // rv 0 + assign SAXIGP5ARQOS_in[2] = (SAXIGP5ARQOS[2] !== 1'bz) && SAXIGP5ARQOS_delay[2]; // rv 0 + assign SAXIGP5ARQOS_in[3] = (SAXIGP5ARQOS[3] !== 1'bz) && SAXIGP5ARQOS_delay[3]; // rv 0 + assign SAXIGP5ARSIZE_in[0] = (SAXIGP5ARSIZE[0] !== 1'bz) && SAXIGP5ARSIZE_delay[0]; // rv 0 + assign SAXIGP5ARSIZE_in[1] = (SAXIGP5ARSIZE[1] !== 1'bz) && SAXIGP5ARSIZE_delay[1]; // rv 0 + assign SAXIGP5ARSIZE_in[2] = (SAXIGP5ARSIZE[2] !== 1'bz) && SAXIGP5ARSIZE_delay[2]; // rv 0 + assign SAXIGP5ARUSER_in = (SAXIGP5ARUSER !== 1'bz) && SAXIGP5ARUSER_delay; // rv 0 + assign SAXIGP5ARVALID_in = (SAXIGP5ARVALID !== 1'bz) && SAXIGP5ARVALID_delay; // rv 0 + assign SAXIGP5AWADDR_in[0] = (SAXIGP5AWADDR[0] !== 1'bz) && SAXIGP5AWADDR_delay[0]; // rv 0 + assign SAXIGP5AWADDR_in[10] = (SAXIGP5AWADDR[10] !== 1'bz) && SAXIGP5AWADDR_delay[10]; // rv 0 + assign SAXIGP5AWADDR_in[11] = (SAXIGP5AWADDR[11] !== 1'bz) && SAXIGP5AWADDR_delay[11]; // rv 0 + assign SAXIGP5AWADDR_in[12] = (SAXIGP5AWADDR[12] !== 1'bz) && SAXIGP5AWADDR_delay[12]; // rv 0 + assign SAXIGP5AWADDR_in[13] = (SAXIGP5AWADDR[13] !== 1'bz) && SAXIGP5AWADDR_delay[13]; // rv 0 + assign SAXIGP5AWADDR_in[14] = (SAXIGP5AWADDR[14] !== 1'bz) && SAXIGP5AWADDR_delay[14]; // rv 0 + assign SAXIGP5AWADDR_in[15] = (SAXIGP5AWADDR[15] !== 1'bz) && SAXIGP5AWADDR_delay[15]; // rv 0 + assign SAXIGP5AWADDR_in[16] = (SAXIGP5AWADDR[16] !== 1'bz) && SAXIGP5AWADDR_delay[16]; // rv 0 + assign SAXIGP5AWADDR_in[17] = (SAXIGP5AWADDR[17] !== 1'bz) && SAXIGP5AWADDR_delay[17]; // rv 0 + assign SAXIGP5AWADDR_in[18] = (SAXIGP5AWADDR[18] !== 1'bz) && SAXIGP5AWADDR_delay[18]; // rv 0 + assign SAXIGP5AWADDR_in[19] = (SAXIGP5AWADDR[19] !== 1'bz) && SAXIGP5AWADDR_delay[19]; // rv 0 + assign SAXIGP5AWADDR_in[1] = (SAXIGP5AWADDR[1] !== 1'bz) && SAXIGP5AWADDR_delay[1]; // rv 0 + assign SAXIGP5AWADDR_in[20] = (SAXIGP5AWADDR[20] !== 1'bz) && SAXIGP5AWADDR_delay[20]; // rv 0 + assign SAXIGP5AWADDR_in[21] = (SAXIGP5AWADDR[21] !== 1'bz) && SAXIGP5AWADDR_delay[21]; // rv 0 + assign SAXIGP5AWADDR_in[22] = (SAXIGP5AWADDR[22] !== 1'bz) && SAXIGP5AWADDR_delay[22]; // rv 0 + assign SAXIGP5AWADDR_in[23] = (SAXIGP5AWADDR[23] !== 1'bz) && SAXIGP5AWADDR_delay[23]; // rv 0 + assign SAXIGP5AWADDR_in[24] = (SAXIGP5AWADDR[24] !== 1'bz) && SAXIGP5AWADDR_delay[24]; // rv 0 + assign SAXIGP5AWADDR_in[25] = (SAXIGP5AWADDR[25] !== 1'bz) && SAXIGP5AWADDR_delay[25]; // rv 0 + assign SAXIGP5AWADDR_in[26] = (SAXIGP5AWADDR[26] !== 1'bz) && SAXIGP5AWADDR_delay[26]; // rv 0 + assign SAXIGP5AWADDR_in[27] = (SAXIGP5AWADDR[27] !== 1'bz) && SAXIGP5AWADDR_delay[27]; // rv 0 + assign SAXIGP5AWADDR_in[28] = (SAXIGP5AWADDR[28] !== 1'bz) && SAXIGP5AWADDR_delay[28]; // rv 0 + assign SAXIGP5AWADDR_in[29] = (SAXIGP5AWADDR[29] !== 1'bz) && SAXIGP5AWADDR_delay[29]; // rv 0 + assign SAXIGP5AWADDR_in[2] = (SAXIGP5AWADDR[2] !== 1'bz) && SAXIGP5AWADDR_delay[2]; // rv 0 + assign SAXIGP5AWADDR_in[30] = (SAXIGP5AWADDR[30] !== 1'bz) && SAXIGP5AWADDR_delay[30]; // rv 0 + assign SAXIGP5AWADDR_in[31] = (SAXIGP5AWADDR[31] !== 1'bz) && SAXIGP5AWADDR_delay[31]; // rv 0 + assign SAXIGP5AWADDR_in[32] = (SAXIGP5AWADDR[32] !== 1'bz) && SAXIGP5AWADDR_delay[32]; // rv 0 + assign SAXIGP5AWADDR_in[33] = (SAXIGP5AWADDR[33] !== 1'bz) && SAXIGP5AWADDR_delay[33]; // rv 0 + assign SAXIGP5AWADDR_in[34] = (SAXIGP5AWADDR[34] !== 1'bz) && SAXIGP5AWADDR_delay[34]; // rv 0 + assign SAXIGP5AWADDR_in[35] = (SAXIGP5AWADDR[35] !== 1'bz) && SAXIGP5AWADDR_delay[35]; // rv 0 + assign SAXIGP5AWADDR_in[36] = (SAXIGP5AWADDR[36] !== 1'bz) && SAXIGP5AWADDR_delay[36]; // rv 0 + assign SAXIGP5AWADDR_in[37] = (SAXIGP5AWADDR[37] !== 1'bz) && SAXIGP5AWADDR_delay[37]; // rv 0 + assign SAXIGP5AWADDR_in[38] = (SAXIGP5AWADDR[38] !== 1'bz) && SAXIGP5AWADDR_delay[38]; // rv 0 + assign SAXIGP5AWADDR_in[39] = (SAXIGP5AWADDR[39] !== 1'bz) && SAXIGP5AWADDR_delay[39]; // rv 0 + assign SAXIGP5AWADDR_in[3] = (SAXIGP5AWADDR[3] !== 1'bz) && SAXIGP5AWADDR_delay[3]; // rv 0 + assign SAXIGP5AWADDR_in[40] = (SAXIGP5AWADDR[40] !== 1'bz) && SAXIGP5AWADDR_delay[40]; // rv 0 + assign SAXIGP5AWADDR_in[41] = (SAXIGP5AWADDR[41] !== 1'bz) && SAXIGP5AWADDR_delay[41]; // rv 0 + assign SAXIGP5AWADDR_in[42] = (SAXIGP5AWADDR[42] !== 1'bz) && SAXIGP5AWADDR_delay[42]; // rv 0 + assign SAXIGP5AWADDR_in[43] = (SAXIGP5AWADDR[43] !== 1'bz) && SAXIGP5AWADDR_delay[43]; // rv 0 + assign SAXIGP5AWADDR_in[44] = (SAXIGP5AWADDR[44] !== 1'bz) && SAXIGP5AWADDR_delay[44]; // rv 0 + assign SAXIGP5AWADDR_in[45] = (SAXIGP5AWADDR[45] !== 1'bz) && SAXIGP5AWADDR_delay[45]; // rv 0 + assign SAXIGP5AWADDR_in[46] = (SAXIGP5AWADDR[46] !== 1'bz) && SAXIGP5AWADDR_delay[46]; // rv 0 + assign SAXIGP5AWADDR_in[47] = (SAXIGP5AWADDR[47] !== 1'bz) && SAXIGP5AWADDR_delay[47]; // rv 0 + assign SAXIGP5AWADDR_in[48] = (SAXIGP5AWADDR[48] !== 1'bz) && SAXIGP5AWADDR_delay[48]; // rv 0 + assign SAXIGP5AWADDR_in[4] = (SAXIGP5AWADDR[4] !== 1'bz) && SAXIGP5AWADDR_delay[4]; // rv 0 + assign SAXIGP5AWADDR_in[5] = (SAXIGP5AWADDR[5] !== 1'bz) && SAXIGP5AWADDR_delay[5]; // rv 0 + assign SAXIGP5AWADDR_in[6] = (SAXIGP5AWADDR[6] !== 1'bz) && SAXIGP5AWADDR_delay[6]; // rv 0 + assign SAXIGP5AWADDR_in[7] = (SAXIGP5AWADDR[7] !== 1'bz) && SAXIGP5AWADDR_delay[7]; // rv 0 + assign SAXIGP5AWADDR_in[8] = (SAXIGP5AWADDR[8] !== 1'bz) && SAXIGP5AWADDR_delay[8]; // rv 0 + assign SAXIGP5AWADDR_in[9] = (SAXIGP5AWADDR[9] !== 1'bz) && SAXIGP5AWADDR_delay[9]; // rv 0 + assign SAXIGP5AWBURST_in[0] = (SAXIGP5AWBURST[0] !== 1'bz) && SAXIGP5AWBURST_delay[0]; // rv 0 + assign SAXIGP5AWBURST_in[1] = (SAXIGP5AWBURST[1] !== 1'bz) && SAXIGP5AWBURST_delay[1]; // rv 0 + assign SAXIGP5AWCACHE_in[0] = (SAXIGP5AWCACHE[0] !== 1'bz) && SAXIGP5AWCACHE_delay[0]; // rv 0 + assign SAXIGP5AWCACHE_in[1] = (SAXIGP5AWCACHE[1] !== 1'bz) && SAXIGP5AWCACHE_delay[1]; // rv 0 + assign SAXIGP5AWCACHE_in[2] = (SAXIGP5AWCACHE[2] !== 1'bz) && SAXIGP5AWCACHE_delay[2]; // rv 0 + assign SAXIGP5AWCACHE_in[3] = (SAXIGP5AWCACHE[3] !== 1'bz) && SAXIGP5AWCACHE_delay[3]; // rv 0 + assign SAXIGP5AWID_in[0] = (SAXIGP5AWID[0] !== 1'bz) && SAXIGP5AWID_delay[0]; // rv 0 + assign SAXIGP5AWID_in[1] = (SAXIGP5AWID[1] !== 1'bz) && SAXIGP5AWID_delay[1]; // rv 0 + assign SAXIGP5AWID_in[2] = (SAXIGP5AWID[2] !== 1'bz) && SAXIGP5AWID_delay[2]; // rv 0 + assign SAXIGP5AWID_in[3] = (SAXIGP5AWID[3] !== 1'bz) && SAXIGP5AWID_delay[3]; // rv 0 + assign SAXIGP5AWID_in[4] = (SAXIGP5AWID[4] !== 1'bz) && SAXIGP5AWID_delay[4]; // rv 0 + assign SAXIGP5AWID_in[5] = (SAXIGP5AWID[5] !== 1'bz) && SAXIGP5AWID_delay[5]; // rv 0 + assign SAXIGP5AWLEN_in[0] = (SAXIGP5AWLEN[0] !== 1'bz) && SAXIGP5AWLEN_delay[0]; // rv 0 + assign SAXIGP5AWLEN_in[1] = (SAXIGP5AWLEN[1] !== 1'bz) && SAXIGP5AWLEN_delay[1]; // rv 0 + assign SAXIGP5AWLEN_in[2] = (SAXIGP5AWLEN[2] !== 1'bz) && SAXIGP5AWLEN_delay[2]; // rv 0 + assign SAXIGP5AWLEN_in[3] = (SAXIGP5AWLEN[3] !== 1'bz) && SAXIGP5AWLEN_delay[3]; // rv 0 + assign SAXIGP5AWLEN_in[4] = (SAXIGP5AWLEN[4] !== 1'bz) && SAXIGP5AWLEN_delay[4]; // rv 0 + assign SAXIGP5AWLEN_in[5] = (SAXIGP5AWLEN[5] !== 1'bz) && SAXIGP5AWLEN_delay[5]; // rv 0 + assign SAXIGP5AWLEN_in[6] = (SAXIGP5AWLEN[6] !== 1'bz) && SAXIGP5AWLEN_delay[6]; // rv 0 + assign SAXIGP5AWLEN_in[7] = (SAXIGP5AWLEN[7] !== 1'bz) && SAXIGP5AWLEN_delay[7]; // rv 0 + assign SAXIGP5AWLOCK_in = (SAXIGP5AWLOCK !== 1'bz) && SAXIGP5AWLOCK_delay; // rv 0 + assign SAXIGP5AWPROT_in[0] = (SAXIGP5AWPROT[0] !== 1'bz) && SAXIGP5AWPROT_delay[0]; // rv 0 + assign SAXIGP5AWPROT_in[1] = (SAXIGP5AWPROT[1] !== 1'bz) && SAXIGP5AWPROT_delay[1]; // rv 0 + assign SAXIGP5AWPROT_in[2] = (SAXIGP5AWPROT[2] !== 1'bz) && SAXIGP5AWPROT_delay[2]; // rv 0 + assign SAXIGP5AWQOS_in[0] = (SAXIGP5AWQOS[0] !== 1'bz) && SAXIGP5AWQOS_delay[0]; // rv 0 + assign SAXIGP5AWQOS_in[1] = (SAXIGP5AWQOS[1] !== 1'bz) && SAXIGP5AWQOS_delay[1]; // rv 0 + assign SAXIGP5AWQOS_in[2] = (SAXIGP5AWQOS[2] !== 1'bz) && SAXIGP5AWQOS_delay[2]; // rv 0 + assign SAXIGP5AWQOS_in[3] = (SAXIGP5AWQOS[3] !== 1'bz) && SAXIGP5AWQOS_delay[3]; // rv 0 + assign SAXIGP5AWSIZE_in[0] = (SAXIGP5AWSIZE[0] !== 1'bz) && SAXIGP5AWSIZE_delay[0]; // rv 0 + assign SAXIGP5AWSIZE_in[1] = (SAXIGP5AWSIZE[1] !== 1'bz) && SAXIGP5AWSIZE_delay[1]; // rv 0 + assign SAXIGP5AWSIZE_in[2] = (SAXIGP5AWSIZE[2] !== 1'bz) && SAXIGP5AWSIZE_delay[2]; // rv 0 + assign SAXIGP5AWUSER_in = (SAXIGP5AWUSER !== 1'bz) && SAXIGP5AWUSER_delay; // rv 0 + assign SAXIGP5AWVALID_in = (SAXIGP5AWVALID !== 1'bz) && SAXIGP5AWVALID_delay; // rv 0 + assign SAXIGP5BREADY_in = (SAXIGP5BREADY !== 1'bz) && SAXIGP5BREADY_delay; // rv 0 + assign SAXIGP5RCLK_in = (SAXIGP5RCLK !== 1'bz) && SAXIGP5RCLK_delay; // rv 0 + assign SAXIGP5RREADY_in = (SAXIGP5RREADY !== 1'bz) && SAXIGP5RREADY_delay; // rv 0 + assign SAXIGP5WCLK_in = (SAXIGP5WCLK !== 1'bz) && SAXIGP5WCLK_delay; // rv 0 + assign SAXIGP5WDATA_in[0] = (SAXIGP5WDATA[0] !== 1'bz) && SAXIGP5WDATA_delay[0]; // rv 0 + assign SAXIGP5WDATA_in[100] = (SAXIGP5WDATA[100] !== 1'bz) && SAXIGP5WDATA_delay[100]; // rv 0 + assign SAXIGP5WDATA_in[101] = (SAXIGP5WDATA[101] !== 1'bz) && SAXIGP5WDATA_delay[101]; // rv 0 + assign SAXIGP5WDATA_in[102] = (SAXIGP5WDATA[102] !== 1'bz) && SAXIGP5WDATA_delay[102]; // rv 0 + assign SAXIGP5WDATA_in[103] = (SAXIGP5WDATA[103] !== 1'bz) && SAXIGP5WDATA_delay[103]; // rv 0 + assign SAXIGP5WDATA_in[104] = (SAXIGP5WDATA[104] !== 1'bz) && SAXIGP5WDATA_delay[104]; // rv 0 + assign SAXIGP5WDATA_in[105] = (SAXIGP5WDATA[105] !== 1'bz) && SAXIGP5WDATA_delay[105]; // rv 0 + assign SAXIGP5WDATA_in[106] = (SAXIGP5WDATA[106] !== 1'bz) && SAXIGP5WDATA_delay[106]; // rv 0 + assign SAXIGP5WDATA_in[107] = (SAXIGP5WDATA[107] !== 1'bz) && SAXIGP5WDATA_delay[107]; // rv 0 + assign SAXIGP5WDATA_in[108] = (SAXIGP5WDATA[108] !== 1'bz) && SAXIGP5WDATA_delay[108]; // rv 0 + assign SAXIGP5WDATA_in[109] = (SAXIGP5WDATA[109] !== 1'bz) && SAXIGP5WDATA_delay[109]; // rv 0 + assign SAXIGP5WDATA_in[10] = (SAXIGP5WDATA[10] !== 1'bz) && SAXIGP5WDATA_delay[10]; // rv 0 + assign SAXIGP5WDATA_in[110] = (SAXIGP5WDATA[110] !== 1'bz) && SAXIGP5WDATA_delay[110]; // rv 0 + assign SAXIGP5WDATA_in[111] = (SAXIGP5WDATA[111] !== 1'bz) && SAXIGP5WDATA_delay[111]; // rv 0 + assign SAXIGP5WDATA_in[112] = (SAXIGP5WDATA[112] !== 1'bz) && SAXIGP5WDATA_delay[112]; // rv 0 + assign SAXIGP5WDATA_in[113] = (SAXIGP5WDATA[113] !== 1'bz) && SAXIGP5WDATA_delay[113]; // rv 0 + assign SAXIGP5WDATA_in[114] = (SAXIGP5WDATA[114] !== 1'bz) && SAXIGP5WDATA_delay[114]; // rv 0 + assign SAXIGP5WDATA_in[115] = (SAXIGP5WDATA[115] !== 1'bz) && SAXIGP5WDATA_delay[115]; // rv 0 + assign SAXIGP5WDATA_in[116] = (SAXIGP5WDATA[116] !== 1'bz) && SAXIGP5WDATA_delay[116]; // rv 0 + assign SAXIGP5WDATA_in[117] = (SAXIGP5WDATA[117] !== 1'bz) && SAXIGP5WDATA_delay[117]; // rv 0 + assign SAXIGP5WDATA_in[118] = (SAXIGP5WDATA[118] !== 1'bz) && SAXIGP5WDATA_delay[118]; // rv 0 + assign SAXIGP5WDATA_in[119] = (SAXIGP5WDATA[119] !== 1'bz) && SAXIGP5WDATA_delay[119]; // rv 0 + assign SAXIGP5WDATA_in[11] = (SAXIGP5WDATA[11] !== 1'bz) && SAXIGP5WDATA_delay[11]; // rv 0 + assign SAXIGP5WDATA_in[120] = (SAXIGP5WDATA[120] !== 1'bz) && SAXIGP5WDATA_delay[120]; // rv 0 + assign SAXIGP5WDATA_in[121] = (SAXIGP5WDATA[121] !== 1'bz) && SAXIGP5WDATA_delay[121]; // rv 0 + assign SAXIGP5WDATA_in[122] = (SAXIGP5WDATA[122] !== 1'bz) && SAXIGP5WDATA_delay[122]; // rv 0 + assign SAXIGP5WDATA_in[123] = (SAXIGP5WDATA[123] !== 1'bz) && SAXIGP5WDATA_delay[123]; // rv 0 + assign SAXIGP5WDATA_in[124] = (SAXIGP5WDATA[124] !== 1'bz) && SAXIGP5WDATA_delay[124]; // rv 0 + assign SAXIGP5WDATA_in[125] = (SAXIGP5WDATA[125] !== 1'bz) && SAXIGP5WDATA_delay[125]; // rv 0 + assign SAXIGP5WDATA_in[126] = (SAXIGP5WDATA[126] !== 1'bz) && SAXIGP5WDATA_delay[126]; // rv 0 + assign SAXIGP5WDATA_in[127] = (SAXIGP5WDATA[127] !== 1'bz) && SAXIGP5WDATA_delay[127]; // rv 0 + assign SAXIGP5WDATA_in[12] = (SAXIGP5WDATA[12] !== 1'bz) && SAXIGP5WDATA_delay[12]; // rv 0 + assign SAXIGP5WDATA_in[13] = (SAXIGP5WDATA[13] !== 1'bz) && SAXIGP5WDATA_delay[13]; // rv 0 + assign SAXIGP5WDATA_in[14] = (SAXIGP5WDATA[14] !== 1'bz) && SAXIGP5WDATA_delay[14]; // rv 0 + assign SAXIGP5WDATA_in[15] = (SAXIGP5WDATA[15] !== 1'bz) && SAXIGP5WDATA_delay[15]; // rv 0 + assign SAXIGP5WDATA_in[16] = (SAXIGP5WDATA[16] !== 1'bz) && SAXIGP5WDATA_delay[16]; // rv 0 + assign SAXIGP5WDATA_in[17] = (SAXIGP5WDATA[17] !== 1'bz) && SAXIGP5WDATA_delay[17]; // rv 0 + assign SAXIGP5WDATA_in[18] = (SAXIGP5WDATA[18] !== 1'bz) && SAXIGP5WDATA_delay[18]; // rv 0 + assign SAXIGP5WDATA_in[19] = (SAXIGP5WDATA[19] !== 1'bz) && SAXIGP5WDATA_delay[19]; // rv 0 + assign SAXIGP5WDATA_in[1] = (SAXIGP5WDATA[1] !== 1'bz) && SAXIGP5WDATA_delay[1]; // rv 0 + assign SAXIGP5WDATA_in[20] = (SAXIGP5WDATA[20] !== 1'bz) && SAXIGP5WDATA_delay[20]; // rv 0 + assign SAXIGP5WDATA_in[21] = (SAXIGP5WDATA[21] !== 1'bz) && SAXIGP5WDATA_delay[21]; // rv 0 + assign SAXIGP5WDATA_in[22] = (SAXIGP5WDATA[22] !== 1'bz) && SAXIGP5WDATA_delay[22]; // rv 0 + assign SAXIGP5WDATA_in[23] = (SAXIGP5WDATA[23] !== 1'bz) && SAXIGP5WDATA_delay[23]; // rv 0 + assign SAXIGP5WDATA_in[24] = (SAXIGP5WDATA[24] !== 1'bz) && SAXIGP5WDATA_delay[24]; // rv 0 + assign SAXIGP5WDATA_in[25] = (SAXIGP5WDATA[25] !== 1'bz) && SAXIGP5WDATA_delay[25]; // rv 0 + assign SAXIGP5WDATA_in[26] = (SAXIGP5WDATA[26] !== 1'bz) && SAXIGP5WDATA_delay[26]; // rv 0 + assign SAXIGP5WDATA_in[27] = (SAXIGP5WDATA[27] !== 1'bz) && SAXIGP5WDATA_delay[27]; // rv 0 + assign SAXIGP5WDATA_in[28] = (SAXIGP5WDATA[28] !== 1'bz) && SAXIGP5WDATA_delay[28]; // rv 0 + assign SAXIGP5WDATA_in[29] = (SAXIGP5WDATA[29] !== 1'bz) && SAXIGP5WDATA_delay[29]; // rv 0 + assign SAXIGP5WDATA_in[2] = (SAXIGP5WDATA[2] !== 1'bz) && SAXIGP5WDATA_delay[2]; // rv 0 + assign SAXIGP5WDATA_in[30] = (SAXIGP5WDATA[30] !== 1'bz) && SAXIGP5WDATA_delay[30]; // rv 0 + assign SAXIGP5WDATA_in[31] = (SAXIGP5WDATA[31] !== 1'bz) && SAXIGP5WDATA_delay[31]; // rv 0 + assign SAXIGP5WDATA_in[32] = (SAXIGP5WDATA[32] !== 1'bz) && SAXIGP5WDATA_delay[32]; // rv 0 + assign SAXIGP5WDATA_in[33] = (SAXIGP5WDATA[33] !== 1'bz) && SAXIGP5WDATA_delay[33]; // rv 0 + assign SAXIGP5WDATA_in[34] = (SAXIGP5WDATA[34] !== 1'bz) && SAXIGP5WDATA_delay[34]; // rv 0 + assign SAXIGP5WDATA_in[35] = (SAXIGP5WDATA[35] !== 1'bz) && SAXIGP5WDATA_delay[35]; // rv 0 + assign SAXIGP5WDATA_in[36] = (SAXIGP5WDATA[36] !== 1'bz) && SAXIGP5WDATA_delay[36]; // rv 0 + assign SAXIGP5WDATA_in[37] = (SAXIGP5WDATA[37] !== 1'bz) && SAXIGP5WDATA_delay[37]; // rv 0 + assign SAXIGP5WDATA_in[38] = (SAXIGP5WDATA[38] !== 1'bz) && SAXIGP5WDATA_delay[38]; // rv 0 + assign SAXIGP5WDATA_in[39] = (SAXIGP5WDATA[39] !== 1'bz) && SAXIGP5WDATA_delay[39]; // rv 0 + assign SAXIGP5WDATA_in[3] = (SAXIGP5WDATA[3] !== 1'bz) && SAXIGP5WDATA_delay[3]; // rv 0 + assign SAXIGP5WDATA_in[40] = (SAXIGP5WDATA[40] !== 1'bz) && SAXIGP5WDATA_delay[40]; // rv 0 + assign SAXIGP5WDATA_in[41] = (SAXIGP5WDATA[41] !== 1'bz) && SAXIGP5WDATA_delay[41]; // rv 0 + assign SAXIGP5WDATA_in[42] = (SAXIGP5WDATA[42] !== 1'bz) && SAXIGP5WDATA_delay[42]; // rv 0 + assign SAXIGP5WDATA_in[43] = (SAXIGP5WDATA[43] !== 1'bz) && SAXIGP5WDATA_delay[43]; // rv 0 + assign SAXIGP5WDATA_in[44] = (SAXIGP5WDATA[44] !== 1'bz) && SAXIGP5WDATA_delay[44]; // rv 0 + assign SAXIGP5WDATA_in[45] = (SAXIGP5WDATA[45] !== 1'bz) && SAXIGP5WDATA_delay[45]; // rv 0 + assign SAXIGP5WDATA_in[46] = (SAXIGP5WDATA[46] !== 1'bz) && SAXIGP5WDATA_delay[46]; // rv 0 + assign SAXIGP5WDATA_in[47] = (SAXIGP5WDATA[47] !== 1'bz) && SAXIGP5WDATA_delay[47]; // rv 0 + assign SAXIGP5WDATA_in[48] = (SAXIGP5WDATA[48] !== 1'bz) && SAXIGP5WDATA_delay[48]; // rv 0 + assign SAXIGP5WDATA_in[49] = (SAXIGP5WDATA[49] !== 1'bz) && SAXIGP5WDATA_delay[49]; // rv 0 + assign SAXIGP5WDATA_in[4] = (SAXIGP5WDATA[4] !== 1'bz) && SAXIGP5WDATA_delay[4]; // rv 0 + assign SAXIGP5WDATA_in[50] = (SAXIGP5WDATA[50] !== 1'bz) && SAXIGP5WDATA_delay[50]; // rv 0 + assign SAXIGP5WDATA_in[51] = (SAXIGP5WDATA[51] !== 1'bz) && SAXIGP5WDATA_delay[51]; // rv 0 + assign SAXIGP5WDATA_in[52] = (SAXIGP5WDATA[52] !== 1'bz) && SAXIGP5WDATA_delay[52]; // rv 0 + assign SAXIGP5WDATA_in[53] = (SAXIGP5WDATA[53] !== 1'bz) && SAXIGP5WDATA_delay[53]; // rv 0 + assign SAXIGP5WDATA_in[54] = (SAXIGP5WDATA[54] !== 1'bz) && SAXIGP5WDATA_delay[54]; // rv 0 + assign SAXIGP5WDATA_in[55] = (SAXIGP5WDATA[55] !== 1'bz) && SAXIGP5WDATA_delay[55]; // rv 0 + assign SAXIGP5WDATA_in[56] = (SAXIGP5WDATA[56] !== 1'bz) && SAXIGP5WDATA_delay[56]; // rv 0 + assign SAXIGP5WDATA_in[57] = (SAXIGP5WDATA[57] !== 1'bz) && SAXIGP5WDATA_delay[57]; // rv 0 + assign SAXIGP5WDATA_in[58] = (SAXIGP5WDATA[58] !== 1'bz) && SAXIGP5WDATA_delay[58]; // rv 0 + assign SAXIGP5WDATA_in[59] = (SAXIGP5WDATA[59] !== 1'bz) && SAXIGP5WDATA_delay[59]; // rv 0 + assign SAXIGP5WDATA_in[5] = (SAXIGP5WDATA[5] !== 1'bz) && SAXIGP5WDATA_delay[5]; // rv 0 + assign SAXIGP5WDATA_in[60] = (SAXIGP5WDATA[60] !== 1'bz) && SAXIGP5WDATA_delay[60]; // rv 0 + assign SAXIGP5WDATA_in[61] = (SAXIGP5WDATA[61] !== 1'bz) && SAXIGP5WDATA_delay[61]; // rv 0 + assign SAXIGP5WDATA_in[62] = (SAXIGP5WDATA[62] !== 1'bz) && SAXIGP5WDATA_delay[62]; // rv 0 + assign SAXIGP5WDATA_in[63] = (SAXIGP5WDATA[63] !== 1'bz) && SAXIGP5WDATA_delay[63]; // rv 0 + assign SAXIGP5WDATA_in[64] = (SAXIGP5WDATA[64] !== 1'bz) && SAXIGP5WDATA_delay[64]; // rv 0 + assign SAXIGP5WDATA_in[65] = (SAXIGP5WDATA[65] !== 1'bz) && SAXIGP5WDATA_delay[65]; // rv 0 + assign SAXIGP5WDATA_in[66] = (SAXIGP5WDATA[66] !== 1'bz) && SAXIGP5WDATA_delay[66]; // rv 0 + assign SAXIGP5WDATA_in[67] = (SAXIGP5WDATA[67] !== 1'bz) && SAXIGP5WDATA_delay[67]; // rv 0 + assign SAXIGP5WDATA_in[68] = (SAXIGP5WDATA[68] !== 1'bz) && SAXIGP5WDATA_delay[68]; // rv 0 + assign SAXIGP5WDATA_in[69] = (SAXIGP5WDATA[69] !== 1'bz) && SAXIGP5WDATA_delay[69]; // rv 0 + assign SAXIGP5WDATA_in[6] = (SAXIGP5WDATA[6] !== 1'bz) && SAXIGP5WDATA_delay[6]; // rv 0 + assign SAXIGP5WDATA_in[70] = (SAXIGP5WDATA[70] !== 1'bz) && SAXIGP5WDATA_delay[70]; // rv 0 + assign SAXIGP5WDATA_in[71] = (SAXIGP5WDATA[71] !== 1'bz) && SAXIGP5WDATA_delay[71]; // rv 0 + assign SAXIGP5WDATA_in[72] = (SAXIGP5WDATA[72] !== 1'bz) && SAXIGP5WDATA_delay[72]; // rv 0 + assign SAXIGP5WDATA_in[73] = (SAXIGP5WDATA[73] !== 1'bz) && SAXIGP5WDATA_delay[73]; // rv 0 + assign SAXIGP5WDATA_in[74] = (SAXIGP5WDATA[74] !== 1'bz) && SAXIGP5WDATA_delay[74]; // rv 0 + assign SAXIGP5WDATA_in[75] = (SAXIGP5WDATA[75] !== 1'bz) && SAXIGP5WDATA_delay[75]; // rv 0 + assign SAXIGP5WDATA_in[76] = (SAXIGP5WDATA[76] !== 1'bz) && SAXIGP5WDATA_delay[76]; // rv 0 + assign SAXIGP5WDATA_in[77] = (SAXIGP5WDATA[77] !== 1'bz) && SAXIGP5WDATA_delay[77]; // rv 0 + assign SAXIGP5WDATA_in[78] = (SAXIGP5WDATA[78] !== 1'bz) && SAXIGP5WDATA_delay[78]; // rv 0 + assign SAXIGP5WDATA_in[79] = (SAXIGP5WDATA[79] !== 1'bz) && SAXIGP5WDATA_delay[79]; // rv 0 + assign SAXIGP5WDATA_in[7] = (SAXIGP5WDATA[7] !== 1'bz) && SAXIGP5WDATA_delay[7]; // rv 0 + assign SAXIGP5WDATA_in[80] = (SAXIGP5WDATA[80] !== 1'bz) && SAXIGP5WDATA_delay[80]; // rv 0 + assign SAXIGP5WDATA_in[81] = (SAXIGP5WDATA[81] !== 1'bz) && SAXIGP5WDATA_delay[81]; // rv 0 + assign SAXIGP5WDATA_in[82] = (SAXIGP5WDATA[82] !== 1'bz) && SAXIGP5WDATA_delay[82]; // rv 0 + assign SAXIGP5WDATA_in[83] = (SAXIGP5WDATA[83] !== 1'bz) && SAXIGP5WDATA_delay[83]; // rv 0 + assign SAXIGP5WDATA_in[84] = (SAXIGP5WDATA[84] !== 1'bz) && SAXIGP5WDATA_delay[84]; // rv 0 + assign SAXIGP5WDATA_in[85] = (SAXIGP5WDATA[85] !== 1'bz) && SAXIGP5WDATA_delay[85]; // rv 0 + assign SAXIGP5WDATA_in[86] = (SAXIGP5WDATA[86] !== 1'bz) && SAXIGP5WDATA_delay[86]; // rv 0 + assign SAXIGP5WDATA_in[87] = (SAXIGP5WDATA[87] !== 1'bz) && SAXIGP5WDATA_delay[87]; // rv 0 + assign SAXIGP5WDATA_in[88] = (SAXIGP5WDATA[88] !== 1'bz) && SAXIGP5WDATA_delay[88]; // rv 0 + assign SAXIGP5WDATA_in[89] = (SAXIGP5WDATA[89] !== 1'bz) && SAXIGP5WDATA_delay[89]; // rv 0 + assign SAXIGP5WDATA_in[8] = (SAXIGP5WDATA[8] !== 1'bz) && SAXIGP5WDATA_delay[8]; // rv 0 + assign SAXIGP5WDATA_in[90] = (SAXIGP5WDATA[90] !== 1'bz) && SAXIGP5WDATA_delay[90]; // rv 0 + assign SAXIGP5WDATA_in[91] = (SAXIGP5WDATA[91] !== 1'bz) && SAXIGP5WDATA_delay[91]; // rv 0 + assign SAXIGP5WDATA_in[92] = (SAXIGP5WDATA[92] !== 1'bz) && SAXIGP5WDATA_delay[92]; // rv 0 + assign SAXIGP5WDATA_in[93] = (SAXIGP5WDATA[93] !== 1'bz) && SAXIGP5WDATA_delay[93]; // rv 0 + assign SAXIGP5WDATA_in[94] = (SAXIGP5WDATA[94] !== 1'bz) && SAXIGP5WDATA_delay[94]; // rv 0 + assign SAXIGP5WDATA_in[95] = (SAXIGP5WDATA[95] !== 1'bz) && SAXIGP5WDATA_delay[95]; // rv 0 + assign SAXIGP5WDATA_in[96] = (SAXIGP5WDATA[96] !== 1'bz) && SAXIGP5WDATA_delay[96]; // rv 0 + assign SAXIGP5WDATA_in[97] = (SAXIGP5WDATA[97] !== 1'bz) && SAXIGP5WDATA_delay[97]; // rv 0 + assign SAXIGP5WDATA_in[98] = (SAXIGP5WDATA[98] !== 1'bz) && SAXIGP5WDATA_delay[98]; // rv 0 + assign SAXIGP5WDATA_in[99] = (SAXIGP5WDATA[99] !== 1'bz) && SAXIGP5WDATA_delay[99]; // rv 0 + assign SAXIGP5WDATA_in[9] = (SAXIGP5WDATA[9] !== 1'bz) && SAXIGP5WDATA_delay[9]; // rv 0 + assign SAXIGP5WLAST_in = (SAXIGP5WLAST !== 1'bz) && SAXIGP5WLAST_delay; // rv 0 + assign SAXIGP5WSTRB_in[0] = (SAXIGP5WSTRB[0] !== 1'bz) && SAXIGP5WSTRB_delay[0]; // rv 0 + assign SAXIGP5WSTRB_in[10] = (SAXIGP5WSTRB[10] !== 1'bz) && SAXIGP5WSTRB_delay[10]; // rv 0 + assign SAXIGP5WSTRB_in[11] = (SAXIGP5WSTRB[11] !== 1'bz) && SAXIGP5WSTRB_delay[11]; // rv 0 + assign SAXIGP5WSTRB_in[12] = (SAXIGP5WSTRB[12] !== 1'bz) && SAXIGP5WSTRB_delay[12]; // rv 0 + assign SAXIGP5WSTRB_in[13] = (SAXIGP5WSTRB[13] !== 1'bz) && SAXIGP5WSTRB_delay[13]; // rv 0 + assign SAXIGP5WSTRB_in[14] = (SAXIGP5WSTRB[14] !== 1'bz) && SAXIGP5WSTRB_delay[14]; // rv 0 + assign SAXIGP5WSTRB_in[15] = (SAXIGP5WSTRB[15] !== 1'bz) && SAXIGP5WSTRB_delay[15]; // rv 0 + assign SAXIGP5WSTRB_in[1] = (SAXIGP5WSTRB[1] !== 1'bz) && SAXIGP5WSTRB_delay[1]; // rv 0 + assign SAXIGP5WSTRB_in[2] = (SAXIGP5WSTRB[2] !== 1'bz) && SAXIGP5WSTRB_delay[2]; // rv 0 + assign SAXIGP5WSTRB_in[3] = (SAXIGP5WSTRB[3] !== 1'bz) && SAXIGP5WSTRB_delay[3]; // rv 0 + assign SAXIGP5WSTRB_in[4] = (SAXIGP5WSTRB[4] !== 1'bz) && SAXIGP5WSTRB_delay[4]; // rv 0 + assign SAXIGP5WSTRB_in[5] = (SAXIGP5WSTRB[5] !== 1'bz) && SAXIGP5WSTRB_delay[5]; // rv 0 + assign SAXIGP5WSTRB_in[6] = (SAXIGP5WSTRB[6] !== 1'bz) && SAXIGP5WSTRB_delay[6]; // rv 0 + assign SAXIGP5WSTRB_in[7] = (SAXIGP5WSTRB[7] !== 1'bz) && SAXIGP5WSTRB_delay[7]; // rv 0 + assign SAXIGP5WSTRB_in[8] = (SAXIGP5WSTRB[8] !== 1'bz) && SAXIGP5WSTRB_delay[8]; // rv 0 + assign SAXIGP5WSTRB_in[9] = (SAXIGP5WSTRB[9] !== 1'bz) && SAXIGP5WSTRB_delay[9]; // rv 0 + assign SAXIGP5WVALID_in = (SAXIGP5WVALID !== 1'bz) && SAXIGP5WVALID_delay; // rv 0 + assign SAXIGP6ARADDR_in[0] = (SAXIGP6ARADDR[0] !== 1'bz) && SAXIGP6ARADDR_delay[0]; // rv 0 + assign SAXIGP6ARADDR_in[10] = (SAXIGP6ARADDR[10] !== 1'bz) && SAXIGP6ARADDR_delay[10]; // rv 0 + assign SAXIGP6ARADDR_in[11] = (SAXIGP6ARADDR[11] !== 1'bz) && SAXIGP6ARADDR_delay[11]; // rv 0 + assign SAXIGP6ARADDR_in[12] = (SAXIGP6ARADDR[12] !== 1'bz) && SAXIGP6ARADDR_delay[12]; // rv 0 + assign SAXIGP6ARADDR_in[13] = (SAXIGP6ARADDR[13] !== 1'bz) && SAXIGP6ARADDR_delay[13]; // rv 0 + assign SAXIGP6ARADDR_in[14] = (SAXIGP6ARADDR[14] !== 1'bz) && SAXIGP6ARADDR_delay[14]; // rv 0 + assign SAXIGP6ARADDR_in[15] = (SAXIGP6ARADDR[15] !== 1'bz) && SAXIGP6ARADDR_delay[15]; // rv 0 + assign SAXIGP6ARADDR_in[16] = (SAXIGP6ARADDR[16] !== 1'bz) && SAXIGP6ARADDR_delay[16]; // rv 0 + assign SAXIGP6ARADDR_in[17] = (SAXIGP6ARADDR[17] !== 1'bz) && SAXIGP6ARADDR_delay[17]; // rv 0 + assign SAXIGP6ARADDR_in[18] = (SAXIGP6ARADDR[18] !== 1'bz) && SAXIGP6ARADDR_delay[18]; // rv 0 + assign SAXIGP6ARADDR_in[19] = (SAXIGP6ARADDR[19] !== 1'bz) && SAXIGP6ARADDR_delay[19]; // rv 0 + assign SAXIGP6ARADDR_in[1] = (SAXIGP6ARADDR[1] !== 1'bz) && SAXIGP6ARADDR_delay[1]; // rv 0 + assign SAXIGP6ARADDR_in[20] = (SAXIGP6ARADDR[20] !== 1'bz) && SAXIGP6ARADDR_delay[20]; // rv 0 + assign SAXIGP6ARADDR_in[21] = (SAXIGP6ARADDR[21] !== 1'bz) && SAXIGP6ARADDR_delay[21]; // rv 0 + assign SAXIGP6ARADDR_in[22] = (SAXIGP6ARADDR[22] !== 1'bz) && SAXIGP6ARADDR_delay[22]; // rv 0 + assign SAXIGP6ARADDR_in[23] = (SAXIGP6ARADDR[23] !== 1'bz) && SAXIGP6ARADDR_delay[23]; // rv 0 + assign SAXIGP6ARADDR_in[24] = (SAXIGP6ARADDR[24] !== 1'bz) && SAXIGP6ARADDR_delay[24]; // rv 0 + assign SAXIGP6ARADDR_in[25] = (SAXIGP6ARADDR[25] !== 1'bz) && SAXIGP6ARADDR_delay[25]; // rv 0 + assign SAXIGP6ARADDR_in[26] = (SAXIGP6ARADDR[26] !== 1'bz) && SAXIGP6ARADDR_delay[26]; // rv 0 + assign SAXIGP6ARADDR_in[27] = (SAXIGP6ARADDR[27] !== 1'bz) && SAXIGP6ARADDR_delay[27]; // rv 0 + assign SAXIGP6ARADDR_in[28] = (SAXIGP6ARADDR[28] !== 1'bz) && SAXIGP6ARADDR_delay[28]; // rv 0 + assign SAXIGP6ARADDR_in[29] = (SAXIGP6ARADDR[29] !== 1'bz) && SAXIGP6ARADDR_delay[29]; // rv 0 + assign SAXIGP6ARADDR_in[2] = (SAXIGP6ARADDR[2] !== 1'bz) && SAXIGP6ARADDR_delay[2]; // rv 0 + assign SAXIGP6ARADDR_in[30] = (SAXIGP6ARADDR[30] !== 1'bz) && SAXIGP6ARADDR_delay[30]; // rv 0 + assign SAXIGP6ARADDR_in[31] = (SAXIGP6ARADDR[31] !== 1'bz) && SAXIGP6ARADDR_delay[31]; // rv 0 + assign SAXIGP6ARADDR_in[32] = (SAXIGP6ARADDR[32] !== 1'bz) && SAXIGP6ARADDR_delay[32]; // rv 0 + assign SAXIGP6ARADDR_in[33] = (SAXIGP6ARADDR[33] !== 1'bz) && SAXIGP6ARADDR_delay[33]; // rv 0 + assign SAXIGP6ARADDR_in[34] = (SAXIGP6ARADDR[34] !== 1'bz) && SAXIGP6ARADDR_delay[34]; // rv 0 + assign SAXIGP6ARADDR_in[35] = (SAXIGP6ARADDR[35] !== 1'bz) && SAXIGP6ARADDR_delay[35]; // rv 0 + assign SAXIGP6ARADDR_in[36] = (SAXIGP6ARADDR[36] !== 1'bz) && SAXIGP6ARADDR_delay[36]; // rv 0 + assign SAXIGP6ARADDR_in[37] = (SAXIGP6ARADDR[37] !== 1'bz) && SAXIGP6ARADDR_delay[37]; // rv 0 + assign SAXIGP6ARADDR_in[38] = (SAXIGP6ARADDR[38] !== 1'bz) && SAXIGP6ARADDR_delay[38]; // rv 0 + assign SAXIGP6ARADDR_in[39] = (SAXIGP6ARADDR[39] !== 1'bz) && SAXIGP6ARADDR_delay[39]; // rv 0 + assign SAXIGP6ARADDR_in[3] = (SAXIGP6ARADDR[3] !== 1'bz) && SAXIGP6ARADDR_delay[3]; // rv 0 + assign SAXIGP6ARADDR_in[40] = (SAXIGP6ARADDR[40] !== 1'bz) && SAXIGP6ARADDR_delay[40]; // rv 0 + assign SAXIGP6ARADDR_in[41] = (SAXIGP6ARADDR[41] !== 1'bz) && SAXIGP6ARADDR_delay[41]; // rv 0 + assign SAXIGP6ARADDR_in[42] = (SAXIGP6ARADDR[42] !== 1'bz) && SAXIGP6ARADDR_delay[42]; // rv 0 + assign SAXIGP6ARADDR_in[43] = (SAXIGP6ARADDR[43] !== 1'bz) && SAXIGP6ARADDR_delay[43]; // rv 0 + assign SAXIGP6ARADDR_in[44] = (SAXIGP6ARADDR[44] !== 1'bz) && SAXIGP6ARADDR_delay[44]; // rv 0 + assign SAXIGP6ARADDR_in[45] = (SAXIGP6ARADDR[45] !== 1'bz) && SAXIGP6ARADDR_delay[45]; // rv 0 + assign SAXIGP6ARADDR_in[46] = (SAXIGP6ARADDR[46] !== 1'bz) && SAXIGP6ARADDR_delay[46]; // rv 0 + assign SAXIGP6ARADDR_in[47] = (SAXIGP6ARADDR[47] !== 1'bz) && SAXIGP6ARADDR_delay[47]; // rv 0 + assign SAXIGP6ARADDR_in[48] = (SAXIGP6ARADDR[48] !== 1'bz) && SAXIGP6ARADDR_delay[48]; // rv 0 + assign SAXIGP6ARADDR_in[4] = (SAXIGP6ARADDR[4] !== 1'bz) && SAXIGP6ARADDR_delay[4]; // rv 0 + assign SAXIGP6ARADDR_in[5] = (SAXIGP6ARADDR[5] !== 1'bz) && SAXIGP6ARADDR_delay[5]; // rv 0 + assign SAXIGP6ARADDR_in[6] = (SAXIGP6ARADDR[6] !== 1'bz) && SAXIGP6ARADDR_delay[6]; // rv 0 + assign SAXIGP6ARADDR_in[7] = (SAXIGP6ARADDR[7] !== 1'bz) && SAXIGP6ARADDR_delay[7]; // rv 0 + assign SAXIGP6ARADDR_in[8] = (SAXIGP6ARADDR[8] !== 1'bz) && SAXIGP6ARADDR_delay[8]; // rv 0 + assign SAXIGP6ARADDR_in[9] = (SAXIGP6ARADDR[9] !== 1'bz) && SAXIGP6ARADDR_delay[9]; // rv 0 + assign SAXIGP6ARBURST_in[0] = (SAXIGP6ARBURST[0] !== 1'bz) && SAXIGP6ARBURST_delay[0]; // rv 0 + assign SAXIGP6ARBURST_in[1] = (SAXIGP6ARBURST[1] !== 1'bz) && SAXIGP6ARBURST_delay[1]; // rv 0 + assign SAXIGP6ARCACHE_in[0] = (SAXIGP6ARCACHE[0] !== 1'bz) && SAXIGP6ARCACHE_delay[0]; // rv 0 + assign SAXIGP6ARCACHE_in[1] = (SAXIGP6ARCACHE[1] !== 1'bz) && SAXIGP6ARCACHE_delay[1]; // rv 0 + assign SAXIGP6ARCACHE_in[2] = (SAXIGP6ARCACHE[2] !== 1'bz) && SAXIGP6ARCACHE_delay[2]; // rv 0 + assign SAXIGP6ARCACHE_in[3] = (SAXIGP6ARCACHE[3] !== 1'bz) && SAXIGP6ARCACHE_delay[3]; // rv 0 + assign SAXIGP6ARID_in[0] = (SAXIGP6ARID[0] !== 1'bz) && SAXIGP6ARID_delay[0]; // rv 0 + assign SAXIGP6ARID_in[1] = (SAXIGP6ARID[1] !== 1'bz) && SAXIGP6ARID_delay[1]; // rv 0 + assign SAXIGP6ARID_in[2] = (SAXIGP6ARID[2] !== 1'bz) && SAXIGP6ARID_delay[2]; // rv 0 + assign SAXIGP6ARID_in[3] = (SAXIGP6ARID[3] !== 1'bz) && SAXIGP6ARID_delay[3]; // rv 0 + assign SAXIGP6ARID_in[4] = (SAXIGP6ARID[4] !== 1'bz) && SAXIGP6ARID_delay[4]; // rv 0 + assign SAXIGP6ARID_in[5] = (SAXIGP6ARID[5] !== 1'bz) && SAXIGP6ARID_delay[5]; // rv 0 + assign SAXIGP6ARLEN_in[0] = (SAXIGP6ARLEN[0] !== 1'bz) && SAXIGP6ARLEN_delay[0]; // rv 0 + assign SAXIGP6ARLEN_in[1] = (SAXIGP6ARLEN[1] !== 1'bz) && SAXIGP6ARLEN_delay[1]; // rv 0 + assign SAXIGP6ARLEN_in[2] = (SAXIGP6ARLEN[2] !== 1'bz) && SAXIGP6ARLEN_delay[2]; // rv 0 + assign SAXIGP6ARLEN_in[3] = (SAXIGP6ARLEN[3] !== 1'bz) && SAXIGP6ARLEN_delay[3]; // rv 0 + assign SAXIGP6ARLEN_in[4] = (SAXIGP6ARLEN[4] !== 1'bz) && SAXIGP6ARLEN_delay[4]; // rv 0 + assign SAXIGP6ARLEN_in[5] = (SAXIGP6ARLEN[5] !== 1'bz) && SAXIGP6ARLEN_delay[5]; // rv 0 + assign SAXIGP6ARLEN_in[6] = (SAXIGP6ARLEN[6] !== 1'bz) && SAXIGP6ARLEN_delay[6]; // rv 0 + assign SAXIGP6ARLEN_in[7] = (SAXIGP6ARLEN[7] !== 1'bz) && SAXIGP6ARLEN_delay[7]; // rv 0 + assign SAXIGP6ARLOCK_in = (SAXIGP6ARLOCK !== 1'bz) && SAXIGP6ARLOCK_delay; // rv 0 + assign SAXIGP6ARPROT_in[0] = (SAXIGP6ARPROT[0] !== 1'bz) && SAXIGP6ARPROT_delay[0]; // rv 0 + assign SAXIGP6ARPROT_in[1] = (SAXIGP6ARPROT[1] !== 1'bz) && SAXIGP6ARPROT_delay[1]; // rv 0 + assign SAXIGP6ARPROT_in[2] = (SAXIGP6ARPROT[2] !== 1'bz) && SAXIGP6ARPROT_delay[2]; // rv 0 + assign SAXIGP6ARQOS_in[0] = (SAXIGP6ARQOS[0] !== 1'bz) && SAXIGP6ARQOS_delay[0]; // rv 0 + assign SAXIGP6ARQOS_in[1] = (SAXIGP6ARQOS[1] !== 1'bz) && SAXIGP6ARQOS_delay[1]; // rv 0 + assign SAXIGP6ARQOS_in[2] = (SAXIGP6ARQOS[2] !== 1'bz) && SAXIGP6ARQOS_delay[2]; // rv 0 + assign SAXIGP6ARQOS_in[3] = (SAXIGP6ARQOS[3] !== 1'bz) && SAXIGP6ARQOS_delay[3]; // rv 0 + assign SAXIGP6ARSIZE_in[0] = (SAXIGP6ARSIZE[0] !== 1'bz) && SAXIGP6ARSIZE_delay[0]; // rv 0 + assign SAXIGP6ARSIZE_in[1] = (SAXIGP6ARSIZE[1] !== 1'bz) && SAXIGP6ARSIZE_delay[1]; // rv 0 + assign SAXIGP6ARSIZE_in[2] = (SAXIGP6ARSIZE[2] !== 1'bz) && SAXIGP6ARSIZE_delay[2]; // rv 0 + assign SAXIGP6ARUSER_in = (SAXIGP6ARUSER !== 1'bz) && SAXIGP6ARUSER_delay; // rv 0 + assign SAXIGP6ARVALID_in = (SAXIGP6ARVALID !== 1'bz) && SAXIGP6ARVALID_delay; // rv 0 + assign SAXIGP6AWADDR_in[0] = (SAXIGP6AWADDR[0] !== 1'bz) && SAXIGP6AWADDR_delay[0]; // rv 0 + assign SAXIGP6AWADDR_in[10] = (SAXIGP6AWADDR[10] !== 1'bz) && SAXIGP6AWADDR_delay[10]; // rv 0 + assign SAXIGP6AWADDR_in[11] = (SAXIGP6AWADDR[11] !== 1'bz) && SAXIGP6AWADDR_delay[11]; // rv 0 + assign SAXIGP6AWADDR_in[12] = (SAXIGP6AWADDR[12] !== 1'bz) && SAXIGP6AWADDR_delay[12]; // rv 0 + assign SAXIGP6AWADDR_in[13] = (SAXIGP6AWADDR[13] !== 1'bz) && SAXIGP6AWADDR_delay[13]; // rv 0 + assign SAXIGP6AWADDR_in[14] = (SAXIGP6AWADDR[14] !== 1'bz) && SAXIGP6AWADDR_delay[14]; // rv 0 + assign SAXIGP6AWADDR_in[15] = (SAXIGP6AWADDR[15] !== 1'bz) && SAXIGP6AWADDR_delay[15]; // rv 0 + assign SAXIGP6AWADDR_in[16] = (SAXIGP6AWADDR[16] !== 1'bz) && SAXIGP6AWADDR_delay[16]; // rv 0 + assign SAXIGP6AWADDR_in[17] = (SAXIGP6AWADDR[17] !== 1'bz) && SAXIGP6AWADDR_delay[17]; // rv 0 + assign SAXIGP6AWADDR_in[18] = (SAXIGP6AWADDR[18] !== 1'bz) && SAXIGP6AWADDR_delay[18]; // rv 0 + assign SAXIGP6AWADDR_in[19] = (SAXIGP6AWADDR[19] !== 1'bz) && SAXIGP6AWADDR_delay[19]; // rv 0 + assign SAXIGP6AWADDR_in[1] = (SAXIGP6AWADDR[1] !== 1'bz) && SAXIGP6AWADDR_delay[1]; // rv 0 + assign SAXIGP6AWADDR_in[20] = (SAXIGP6AWADDR[20] !== 1'bz) && SAXIGP6AWADDR_delay[20]; // rv 0 + assign SAXIGP6AWADDR_in[21] = (SAXIGP6AWADDR[21] !== 1'bz) && SAXIGP6AWADDR_delay[21]; // rv 0 + assign SAXIGP6AWADDR_in[22] = (SAXIGP6AWADDR[22] !== 1'bz) && SAXIGP6AWADDR_delay[22]; // rv 0 + assign SAXIGP6AWADDR_in[23] = (SAXIGP6AWADDR[23] !== 1'bz) && SAXIGP6AWADDR_delay[23]; // rv 0 + assign SAXIGP6AWADDR_in[24] = (SAXIGP6AWADDR[24] !== 1'bz) && SAXIGP6AWADDR_delay[24]; // rv 0 + assign SAXIGP6AWADDR_in[25] = (SAXIGP6AWADDR[25] !== 1'bz) && SAXIGP6AWADDR_delay[25]; // rv 0 + assign SAXIGP6AWADDR_in[26] = (SAXIGP6AWADDR[26] !== 1'bz) && SAXIGP6AWADDR_delay[26]; // rv 0 + assign SAXIGP6AWADDR_in[27] = (SAXIGP6AWADDR[27] !== 1'bz) && SAXIGP6AWADDR_delay[27]; // rv 0 + assign SAXIGP6AWADDR_in[28] = (SAXIGP6AWADDR[28] !== 1'bz) && SAXIGP6AWADDR_delay[28]; // rv 0 + assign SAXIGP6AWADDR_in[29] = (SAXIGP6AWADDR[29] !== 1'bz) && SAXIGP6AWADDR_delay[29]; // rv 0 + assign SAXIGP6AWADDR_in[2] = (SAXIGP6AWADDR[2] !== 1'bz) && SAXIGP6AWADDR_delay[2]; // rv 0 + assign SAXIGP6AWADDR_in[30] = (SAXIGP6AWADDR[30] !== 1'bz) && SAXIGP6AWADDR_delay[30]; // rv 0 + assign SAXIGP6AWADDR_in[31] = (SAXIGP6AWADDR[31] !== 1'bz) && SAXIGP6AWADDR_delay[31]; // rv 0 + assign SAXIGP6AWADDR_in[32] = (SAXIGP6AWADDR[32] !== 1'bz) && SAXIGP6AWADDR_delay[32]; // rv 0 + assign SAXIGP6AWADDR_in[33] = (SAXIGP6AWADDR[33] !== 1'bz) && SAXIGP6AWADDR_delay[33]; // rv 0 + assign SAXIGP6AWADDR_in[34] = (SAXIGP6AWADDR[34] !== 1'bz) && SAXIGP6AWADDR_delay[34]; // rv 0 + assign SAXIGP6AWADDR_in[35] = (SAXIGP6AWADDR[35] !== 1'bz) && SAXIGP6AWADDR_delay[35]; // rv 0 + assign SAXIGP6AWADDR_in[36] = (SAXIGP6AWADDR[36] !== 1'bz) && SAXIGP6AWADDR_delay[36]; // rv 0 + assign SAXIGP6AWADDR_in[37] = (SAXIGP6AWADDR[37] !== 1'bz) && SAXIGP6AWADDR_delay[37]; // rv 0 + assign SAXIGP6AWADDR_in[38] = (SAXIGP6AWADDR[38] !== 1'bz) && SAXIGP6AWADDR_delay[38]; // rv 0 + assign SAXIGP6AWADDR_in[39] = (SAXIGP6AWADDR[39] !== 1'bz) && SAXIGP6AWADDR_delay[39]; // rv 0 + assign SAXIGP6AWADDR_in[3] = (SAXIGP6AWADDR[3] !== 1'bz) && SAXIGP6AWADDR_delay[3]; // rv 0 + assign SAXIGP6AWADDR_in[40] = (SAXIGP6AWADDR[40] !== 1'bz) && SAXIGP6AWADDR_delay[40]; // rv 0 + assign SAXIGP6AWADDR_in[41] = (SAXIGP6AWADDR[41] !== 1'bz) && SAXIGP6AWADDR_delay[41]; // rv 0 + assign SAXIGP6AWADDR_in[42] = (SAXIGP6AWADDR[42] !== 1'bz) && SAXIGP6AWADDR_delay[42]; // rv 0 + assign SAXIGP6AWADDR_in[43] = (SAXIGP6AWADDR[43] !== 1'bz) && SAXIGP6AWADDR_delay[43]; // rv 0 + assign SAXIGP6AWADDR_in[44] = (SAXIGP6AWADDR[44] !== 1'bz) && SAXIGP6AWADDR_delay[44]; // rv 0 + assign SAXIGP6AWADDR_in[45] = (SAXIGP6AWADDR[45] !== 1'bz) && SAXIGP6AWADDR_delay[45]; // rv 0 + assign SAXIGP6AWADDR_in[46] = (SAXIGP6AWADDR[46] !== 1'bz) && SAXIGP6AWADDR_delay[46]; // rv 0 + assign SAXIGP6AWADDR_in[47] = (SAXIGP6AWADDR[47] !== 1'bz) && SAXIGP6AWADDR_delay[47]; // rv 0 + assign SAXIGP6AWADDR_in[48] = (SAXIGP6AWADDR[48] !== 1'bz) && SAXIGP6AWADDR_delay[48]; // rv 0 + assign SAXIGP6AWADDR_in[4] = (SAXIGP6AWADDR[4] !== 1'bz) && SAXIGP6AWADDR_delay[4]; // rv 0 + assign SAXIGP6AWADDR_in[5] = (SAXIGP6AWADDR[5] !== 1'bz) && SAXIGP6AWADDR_delay[5]; // rv 0 + assign SAXIGP6AWADDR_in[6] = (SAXIGP6AWADDR[6] !== 1'bz) && SAXIGP6AWADDR_delay[6]; // rv 0 + assign SAXIGP6AWADDR_in[7] = (SAXIGP6AWADDR[7] !== 1'bz) && SAXIGP6AWADDR_delay[7]; // rv 0 + assign SAXIGP6AWADDR_in[8] = (SAXIGP6AWADDR[8] !== 1'bz) && SAXIGP6AWADDR_delay[8]; // rv 0 + assign SAXIGP6AWADDR_in[9] = (SAXIGP6AWADDR[9] !== 1'bz) && SAXIGP6AWADDR_delay[9]; // rv 0 + assign SAXIGP6AWBURST_in[0] = (SAXIGP6AWBURST[0] !== 1'bz) && SAXIGP6AWBURST_delay[0]; // rv 0 + assign SAXIGP6AWBURST_in[1] = (SAXIGP6AWBURST[1] !== 1'bz) && SAXIGP6AWBURST_delay[1]; // rv 0 + assign SAXIGP6AWCACHE_in[0] = (SAXIGP6AWCACHE[0] !== 1'bz) && SAXIGP6AWCACHE_delay[0]; // rv 0 + assign SAXIGP6AWCACHE_in[1] = (SAXIGP6AWCACHE[1] !== 1'bz) && SAXIGP6AWCACHE_delay[1]; // rv 0 + assign SAXIGP6AWCACHE_in[2] = (SAXIGP6AWCACHE[2] !== 1'bz) && SAXIGP6AWCACHE_delay[2]; // rv 0 + assign SAXIGP6AWCACHE_in[3] = (SAXIGP6AWCACHE[3] !== 1'bz) && SAXIGP6AWCACHE_delay[3]; // rv 0 + assign SAXIGP6AWID_in[0] = (SAXIGP6AWID[0] !== 1'bz) && SAXIGP6AWID_delay[0]; // rv 0 + assign SAXIGP6AWID_in[1] = (SAXIGP6AWID[1] !== 1'bz) && SAXIGP6AWID_delay[1]; // rv 0 + assign SAXIGP6AWID_in[2] = (SAXIGP6AWID[2] !== 1'bz) && SAXIGP6AWID_delay[2]; // rv 0 + assign SAXIGP6AWID_in[3] = (SAXIGP6AWID[3] !== 1'bz) && SAXIGP6AWID_delay[3]; // rv 0 + assign SAXIGP6AWID_in[4] = (SAXIGP6AWID[4] !== 1'bz) && SAXIGP6AWID_delay[4]; // rv 0 + assign SAXIGP6AWID_in[5] = (SAXIGP6AWID[5] !== 1'bz) && SAXIGP6AWID_delay[5]; // rv 0 + assign SAXIGP6AWLEN_in[0] = (SAXIGP6AWLEN[0] !== 1'bz) && SAXIGP6AWLEN_delay[0]; // rv 0 + assign SAXIGP6AWLEN_in[1] = (SAXIGP6AWLEN[1] !== 1'bz) && SAXIGP6AWLEN_delay[1]; // rv 0 + assign SAXIGP6AWLEN_in[2] = (SAXIGP6AWLEN[2] !== 1'bz) && SAXIGP6AWLEN_delay[2]; // rv 0 + assign SAXIGP6AWLEN_in[3] = (SAXIGP6AWLEN[3] !== 1'bz) && SAXIGP6AWLEN_delay[3]; // rv 0 + assign SAXIGP6AWLEN_in[4] = (SAXIGP6AWLEN[4] !== 1'bz) && SAXIGP6AWLEN_delay[4]; // rv 0 + assign SAXIGP6AWLEN_in[5] = (SAXIGP6AWLEN[5] !== 1'bz) && SAXIGP6AWLEN_delay[5]; // rv 0 + assign SAXIGP6AWLEN_in[6] = (SAXIGP6AWLEN[6] !== 1'bz) && SAXIGP6AWLEN_delay[6]; // rv 0 + assign SAXIGP6AWLEN_in[7] = (SAXIGP6AWLEN[7] !== 1'bz) && SAXIGP6AWLEN_delay[7]; // rv 0 + assign SAXIGP6AWLOCK_in = (SAXIGP6AWLOCK !== 1'bz) && SAXIGP6AWLOCK_delay; // rv 0 + assign SAXIGP6AWPROT_in[0] = (SAXIGP6AWPROT[0] !== 1'bz) && SAXIGP6AWPROT_delay[0]; // rv 0 + assign SAXIGP6AWPROT_in[1] = (SAXIGP6AWPROT[1] !== 1'bz) && SAXIGP6AWPROT_delay[1]; // rv 0 + assign SAXIGP6AWPROT_in[2] = (SAXIGP6AWPROT[2] !== 1'bz) && SAXIGP6AWPROT_delay[2]; // rv 0 + assign SAXIGP6AWQOS_in[0] = (SAXIGP6AWQOS[0] !== 1'bz) && SAXIGP6AWQOS_delay[0]; // rv 0 + assign SAXIGP6AWQOS_in[1] = (SAXIGP6AWQOS[1] !== 1'bz) && SAXIGP6AWQOS_delay[1]; // rv 0 + assign SAXIGP6AWQOS_in[2] = (SAXIGP6AWQOS[2] !== 1'bz) && SAXIGP6AWQOS_delay[2]; // rv 0 + assign SAXIGP6AWQOS_in[3] = (SAXIGP6AWQOS[3] !== 1'bz) && SAXIGP6AWQOS_delay[3]; // rv 0 + assign SAXIGP6AWSIZE_in[0] = (SAXIGP6AWSIZE[0] !== 1'bz) && SAXIGP6AWSIZE_delay[0]; // rv 0 + assign SAXIGP6AWSIZE_in[1] = (SAXIGP6AWSIZE[1] !== 1'bz) && SAXIGP6AWSIZE_delay[1]; // rv 0 + assign SAXIGP6AWSIZE_in[2] = (SAXIGP6AWSIZE[2] !== 1'bz) && SAXIGP6AWSIZE_delay[2]; // rv 0 + assign SAXIGP6AWUSER_in = (SAXIGP6AWUSER !== 1'bz) && SAXIGP6AWUSER_delay; // rv 0 + assign SAXIGP6AWVALID_in = (SAXIGP6AWVALID !== 1'bz) && SAXIGP6AWVALID_delay; // rv 0 + assign SAXIGP6BREADY_in = (SAXIGP6BREADY !== 1'bz) && SAXIGP6BREADY_delay; // rv 0 + assign SAXIGP6RCLK_in = (SAXIGP6RCLK !== 1'bz) && SAXIGP6RCLK_delay; // rv 0 + assign SAXIGP6RREADY_in = (SAXIGP6RREADY !== 1'bz) && SAXIGP6RREADY_delay; // rv 0 + assign SAXIGP6WCLK_in = (SAXIGP6WCLK !== 1'bz) && SAXIGP6WCLK_delay; // rv 0 + assign SAXIGP6WDATA_in[0] = (SAXIGP6WDATA[0] !== 1'bz) && SAXIGP6WDATA_delay[0]; // rv 0 + assign SAXIGP6WDATA_in[100] = (SAXIGP6WDATA[100] !== 1'bz) && SAXIGP6WDATA_delay[100]; // rv 0 + assign SAXIGP6WDATA_in[101] = (SAXIGP6WDATA[101] !== 1'bz) && SAXIGP6WDATA_delay[101]; // rv 0 + assign SAXIGP6WDATA_in[102] = (SAXIGP6WDATA[102] !== 1'bz) && SAXIGP6WDATA_delay[102]; // rv 0 + assign SAXIGP6WDATA_in[103] = (SAXIGP6WDATA[103] !== 1'bz) && SAXIGP6WDATA_delay[103]; // rv 0 + assign SAXIGP6WDATA_in[104] = (SAXIGP6WDATA[104] !== 1'bz) && SAXIGP6WDATA_delay[104]; // rv 0 + assign SAXIGP6WDATA_in[105] = (SAXIGP6WDATA[105] !== 1'bz) && SAXIGP6WDATA_delay[105]; // rv 0 + assign SAXIGP6WDATA_in[106] = (SAXIGP6WDATA[106] !== 1'bz) && SAXIGP6WDATA_delay[106]; // rv 0 + assign SAXIGP6WDATA_in[107] = (SAXIGP6WDATA[107] !== 1'bz) && SAXIGP6WDATA_delay[107]; // rv 0 + assign SAXIGP6WDATA_in[108] = (SAXIGP6WDATA[108] !== 1'bz) && SAXIGP6WDATA_delay[108]; // rv 0 + assign SAXIGP6WDATA_in[109] = (SAXIGP6WDATA[109] !== 1'bz) && SAXIGP6WDATA_delay[109]; // rv 0 + assign SAXIGP6WDATA_in[10] = (SAXIGP6WDATA[10] !== 1'bz) && SAXIGP6WDATA_delay[10]; // rv 0 + assign SAXIGP6WDATA_in[110] = (SAXIGP6WDATA[110] !== 1'bz) && SAXIGP6WDATA_delay[110]; // rv 0 + assign SAXIGP6WDATA_in[111] = (SAXIGP6WDATA[111] !== 1'bz) && SAXIGP6WDATA_delay[111]; // rv 0 + assign SAXIGP6WDATA_in[112] = (SAXIGP6WDATA[112] !== 1'bz) && SAXIGP6WDATA_delay[112]; // rv 0 + assign SAXIGP6WDATA_in[113] = (SAXIGP6WDATA[113] !== 1'bz) && SAXIGP6WDATA_delay[113]; // rv 0 + assign SAXIGP6WDATA_in[114] = (SAXIGP6WDATA[114] !== 1'bz) && SAXIGP6WDATA_delay[114]; // rv 0 + assign SAXIGP6WDATA_in[115] = (SAXIGP6WDATA[115] !== 1'bz) && SAXIGP6WDATA_delay[115]; // rv 0 + assign SAXIGP6WDATA_in[116] = (SAXIGP6WDATA[116] !== 1'bz) && SAXIGP6WDATA_delay[116]; // rv 0 + assign SAXIGP6WDATA_in[117] = (SAXIGP6WDATA[117] !== 1'bz) && SAXIGP6WDATA_delay[117]; // rv 0 + assign SAXIGP6WDATA_in[118] = (SAXIGP6WDATA[118] !== 1'bz) && SAXIGP6WDATA_delay[118]; // rv 0 + assign SAXIGP6WDATA_in[119] = (SAXIGP6WDATA[119] !== 1'bz) && SAXIGP6WDATA_delay[119]; // rv 0 + assign SAXIGP6WDATA_in[11] = (SAXIGP6WDATA[11] !== 1'bz) && SAXIGP6WDATA_delay[11]; // rv 0 + assign SAXIGP6WDATA_in[120] = (SAXIGP6WDATA[120] !== 1'bz) && SAXIGP6WDATA_delay[120]; // rv 0 + assign SAXIGP6WDATA_in[121] = (SAXIGP6WDATA[121] !== 1'bz) && SAXIGP6WDATA_delay[121]; // rv 0 + assign SAXIGP6WDATA_in[122] = (SAXIGP6WDATA[122] !== 1'bz) && SAXIGP6WDATA_delay[122]; // rv 0 + assign SAXIGP6WDATA_in[123] = (SAXIGP6WDATA[123] !== 1'bz) && SAXIGP6WDATA_delay[123]; // rv 0 + assign SAXIGP6WDATA_in[124] = (SAXIGP6WDATA[124] !== 1'bz) && SAXIGP6WDATA_delay[124]; // rv 0 + assign SAXIGP6WDATA_in[125] = (SAXIGP6WDATA[125] !== 1'bz) && SAXIGP6WDATA_delay[125]; // rv 0 + assign SAXIGP6WDATA_in[126] = (SAXIGP6WDATA[126] !== 1'bz) && SAXIGP6WDATA_delay[126]; // rv 0 + assign SAXIGP6WDATA_in[127] = (SAXIGP6WDATA[127] !== 1'bz) && SAXIGP6WDATA_delay[127]; // rv 0 + assign SAXIGP6WDATA_in[12] = (SAXIGP6WDATA[12] !== 1'bz) && SAXIGP6WDATA_delay[12]; // rv 0 + assign SAXIGP6WDATA_in[13] = (SAXIGP6WDATA[13] !== 1'bz) && SAXIGP6WDATA_delay[13]; // rv 0 + assign SAXIGP6WDATA_in[14] = (SAXIGP6WDATA[14] !== 1'bz) && SAXIGP6WDATA_delay[14]; // rv 0 + assign SAXIGP6WDATA_in[15] = (SAXIGP6WDATA[15] !== 1'bz) && SAXIGP6WDATA_delay[15]; // rv 0 + assign SAXIGP6WDATA_in[16] = (SAXIGP6WDATA[16] !== 1'bz) && SAXIGP6WDATA_delay[16]; // rv 0 + assign SAXIGP6WDATA_in[17] = (SAXIGP6WDATA[17] !== 1'bz) && SAXIGP6WDATA_delay[17]; // rv 0 + assign SAXIGP6WDATA_in[18] = (SAXIGP6WDATA[18] !== 1'bz) && SAXIGP6WDATA_delay[18]; // rv 0 + assign SAXIGP6WDATA_in[19] = (SAXIGP6WDATA[19] !== 1'bz) && SAXIGP6WDATA_delay[19]; // rv 0 + assign SAXIGP6WDATA_in[1] = (SAXIGP6WDATA[1] !== 1'bz) && SAXIGP6WDATA_delay[1]; // rv 0 + assign SAXIGP6WDATA_in[20] = (SAXIGP6WDATA[20] !== 1'bz) && SAXIGP6WDATA_delay[20]; // rv 0 + assign SAXIGP6WDATA_in[21] = (SAXIGP6WDATA[21] !== 1'bz) && SAXIGP6WDATA_delay[21]; // rv 0 + assign SAXIGP6WDATA_in[22] = (SAXIGP6WDATA[22] !== 1'bz) && SAXIGP6WDATA_delay[22]; // rv 0 + assign SAXIGP6WDATA_in[23] = (SAXIGP6WDATA[23] !== 1'bz) && SAXIGP6WDATA_delay[23]; // rv 0 + assign SAXIGP6WDATA_in[24] = (SAXIGP6WDATA[24] !== 1'bz) && SAXIGP6WDATA_delay[24]; // rv 0 + assign SAXIGP6WDATA_in[25] = (SAXIGP6WDATA[25] !== 1'bz) && SAXIGP6WDATA_delay[25]; // rv 0 + assign SAXIGP6WDATA_in[26] = (SAXIGP6WDATA[26] !== 1'bz) && SAXIGP6WDATA_delay[26]; // rv 0 + assign SAXIGP6WDATA_in[27] = (SAXIGP6WDATA[27] !== 1'bz) && SAXIGP6WDATA_delay[27]; // rv 0 + assign SAXIGP6WDATA_in[28] = (SAXIGP6WDATA[28] !== 1'bz) && SAXIGP6WDATA_delay[28]; // rv 0 + assign SAXIGP6WDATA_in[29] = (SAXIGP6WDATA[29] !== 1'bz) && SAXIGP6WDATA_delay[29]; // rv 0 + assign SAXIGP6WDATA_in[2] = (SAXIGP6WDATA[2] !== 1'bz) && SAXIGP6WDATA_delay[2]; // rv 0 + assign SAXIGP6WDATA_in[30] = (SAXIGP6WDATA[30] !== 1'bz) && SAXIGP6WDATA_delay[30]; // rv 0 + assign SAXIGP6WDATA_in[31] = (SAXIGP6WDATA[31] !== 1'bz) && SAXIGP6WDATA_delay[31]; // rv 0 + assign SAXIGP6WDATA_in[32] = (SAXIGP6WDATA[32] !== 1'bz) && SAXIGP6WDATA_delay[32]; // rv 0 + assign SAXIGP6WDATA_in[33] = (SAXIGP6WDATA[33] !== 1'bz) && SAXIGP6WDATA_delay[33]; // rv 0 + assign SAXIGP6WDATA_in[34] = (SAXIGP6WDATA[34] !== 1'bz) && SAXIGP6WDATA_delay[34]; // rv 0 + assign SAXIGP6WDATA_in[35] = (SAXIGP6WDATA[35] !== 1'bz) && SAXIGP6WDATA_delay[35]; // rv 0 + assign SAXIGP6WDATA_in[36] = (SAXIGP6WDATA[36] !== 1'bz) && SAXIGP6WDATA_delay[36]; // rv 0 + assign SAXIGP6WDATA_in[37] = (SAXIGP6WDATA[37] !== 1'bz) && SAXIGP6WDATA_delay[37]; // rv 0 + assign SAXIGP6WDATA_in[38] = (SAXIGP6WDATA[38] !== 1'bz) && SAXIGP6WDATA_delay[38]; // rv 0 + assign SAXIGP6WDATA_in[39] = (SAXIGP6WDATA[39] !== 1'bz) && SAXIGP6WDATA_delay[39]; // rv 0 + assign SAXIGP6WDATA_in[3] = (SAXIGP6WDATA[3] !== 1'bz) && SAXIGP6WDATA_delay[3]; // rv 0 + assign SAXIGP6WDATA_in[40] = (SAXIGP6WDATA[40] !== 1'bz) && SAXIGP6WDATA_delay[40]; // rv 0 + assign SAXIGP6WDATA_in[41] = (SAXIGP6WDATA[41] !== 1'bz) && SAXIGP6WDATA_delay[41]; // rv 0 + assign SAXIGP6WDATA_in[42] = (SAXIGP6WDATA[42] !== 1'bz) && SAXIGP6WDATA_delay[42]; // rv 0 + assign SAXIGP6WDATA_in[43] = (SAXIGP6WDATA[43] !== 1'bz) && SAXIGP6WDATA_delay[43]; // rv 0 + assign SAXIGP6WDATA_in[44] = (SAXIGP6WDATA[44] !== 1'bz) && SAXIGP6WDATA_delay[44]; // rv 0 + assign SAXIGP6WDATA_in[45] = (SAXIGP6WDATA[45] !== 1'bz) && SAXIGP6WDATA_delay[45]; // rv 0 + assign SAXIGP6WDATA_in[46] = (SAXIGP6WDATA[46] !== 1'bz) && SAXIGP6WDATA_delay[46]; // rv 0 + assign SAXIGP6WDATA_in[47] = (SAXIGP6WDATA[47] !== 1'bz) && SAXIGP6WDATA_delay[47]; // rv 0 + assign SAXIGP6WDATA_in[48] = (SAXIGP6WDATA[48] !== 1'bz) && SAXIGP6WDATA_delay[48]; // rv 0 + assign SAXIGP6WDATA_in[49] = (SAXIGP6WDATA[49] !== 1'bz) && SAXIGP6WDATA_delay[49]; // rv 0 + assign SAXIGP6WDATA_in[4] = (SAXIGP6WDATA[4] !== 1'bz) && SAXIGP6WDATA_delay[4]; // rv 0 + assign SAXIGP6WDATA_in[50] = (SAXIGP6WDATA[50] !== 1'bz) && SAXIGP6WDATA_delay[50]; // rv 0 + assign SAXIGP6WDATA_in[51] = (SAXIGP6WDATA[51] !== 1'bz) && SAXIGP6WDATA_delay[51]; // rv 0 + assign SAXIGP6WDATA_in[52] = (SAXIGP6WDATA[52] !== 1'bz) && SAXIGP6WDATA_delay[52]; // rv 0 + assign SAXIGP6WDATA_in[53] = (SAXIGP6WDATA[53] !== 1'bz) && SAXIGP6WDATA_delay[53]; // rv 0 + assign SAXIGP6WDATA_in[54] = (SAXIGP6WDATA[54] !== 1'bz) && SAXIGP6WDATA_delay[54]; // rv 0 + assign SAXIGP6WDATA_in[55] = (SAXIGP6WDATA[55] !== 1'bz) && SAXIGP6WDATA_delay[55]; // rv 0 + assign SAXIGP6WDATA_in[56] = (SAXIGP6WDATA[56] !== 1'bz) && SAXIGP6WDATA_delay[56]; // rv 0 + assign SAXIGP6WDATA_in[57] = (SAXIGP6WDATA[57] !== 1'bz) && SAXIGP6WDATA_delay[57]; // rv 0 + assign SAXIGP6WDATA_in[58] = (SAXIGP6WDATA[58] !== 1'bz) && SAXIGP6WDATA_delay[58]; // rv 0 + assign SAXIGP6WDATA_in[59] = (SAXIGP6WDATA[59] !== 1'bz) && SAXIGP6WDATA_delay[59]; // rv 0 + assign SAXIGP6WDATA_in[5] = (SAXIGP6WDATA[5] !== 1'bz) && SAXIGP6WDATA_delay[5]; // rv 0 + assign SAXIGP6WDATA_in[60] = (SAXIGP6WDATA[60] !== 1'bz) && SAXIGP6WDATA_delay[60]; // rv 0 + assign SAXIGP6WDATA_in[61] = (SAXIGP6WDATA[61] !== 1'bz) && SAXIGP6WDATA_delay[61]; // rv 0 + assign SAXIGP6WDATA_in[62] = (SAXIGP6WDATA[62] !== 1'bz) && SAXIGP6WDATA_delay[62]; // rv 0 + assign SAXIGP6WDATA_in[63] = (SAXIGP6WDATA[63] !== 1'bz) && SAXIGP6WDATA_delay[63]; // rv 0 + assign SAXIGP6WDATA_in[64] = (SAXIGP6WDATA[64] !== 1'bz) && SAXIGP6WDATA_delay[64]; // rv 0 + assign SAXIGP6WDATA_in[65] = (SAXIGP6WDATA[65] !== 1'bz) && SAXIGP6WDATA_delay[65]; // rv 0 + assign SAXIGP6WDATA_in[66] = (SAXIGP6WDATA[66] !== 1'bz) && SAXIGP6WDATA_delay[66]; // rv 0 + assign SAXIGP6WDATA_in[67] = (SAXIGP6WDATA[67] !== 1'bz) && SAXIGP6WDATA_delay[67]; // rv 0 + assign SAXIGP6WDATA_in[68] = (SAXIGP6WDATA[68] !== 1'bz) && SAXIGP6WDATA_delay[68]; // rv 0 + assign SAXIGP6WDATA_in[69] = (SAXIGP6WDATA[69] !== 1'bz) && SAXIGP6WDATA_delay[69]; // rv 0 + assign SAXIGP6WDATA_in[6] = (SAXIGP6WDATA[6] !== 1'bz) && SAXIGP6WDATA_delay[6]; // rv 0 + assign SAXIGP6WDATA_in[70] = (SAXIGP6WDATA[70] !== 1'bz) && SAXIGP6WDATA_delay[70]; // rv 0 + assign SAXIGP6WDATA_in[71] = (SAXIGP6WDATA[71] !== 1'bz) && SAXIGP6WDATA_delay[71]; // rv 0 + assign SAXIGP6WDATA_in[72] = (SAXIGP6WDATA[72] !== 1'bz) && SAXIGP6WDATA_delay[72]; // rv 0 + assign SAXIGP6WDATA_in[73] = (SAXIGP6WDATA[73] !== 1'bz) && SAXIGP6WDATA_delay[73]; // rv 0 + assign SAXIGP6WDATA_in[74] = (SAXIGP6WDATA[74] !== 1'bz) && SAXIGP6WDATA_delay[74]; // rv 0 + assign SAXIGP6WDATA_in[75] = (SAXIGP6WDATA[75] !== 1'bz) && SAXIGP6WDATA_delay[75]; // rv 0 + assign SAXIGP6WDATA_in[76] = (SAXIGP6WDATA[76] !== 1'bz) && SAXIGP6WDATA_delay[76]; // rv 0 + assign SAXIGP6WDATA_in[77] = (SAXIGP6WDATA[77] !== 1'bz) && SAXIGP6WDATA_delay[77]; // rv 0 + assign SAXIGP6WDATA_in[78] = (SAXIGP6WDATA[78] !== 1'bz) && SAXIGP6WDATA_delay[78]; // rv 0 + assign SAXIGP6WDATA_in[79] = (SAXIGP6WDATA[79] !== 1'bz) && SAXIGP6WDATA_delay[79]; // rv 0 + assign SAXIGP6WDATA_in[7] = (SAXIGP6WDATA[7] !== 1'bz) && SAXIGP6WDATA_delay[7]; // rv 0 + assign SAXIGP6WDATA_in[80] = (SAXIGP6WDATA[80] !== 1'bz) && SAXIGP6WDATA_delay[80]; // rv 0 + assign SAXIGP6WDATA_in[81] = (SAXIGP6WDATA[81] !== 1'bz) && SAXIGP6WDATA_delay[81]; // rv 0 + assign SAXIGP6WDATA_in[82] = (SAXIGP6WDATA[82] !== 1'bz) && SAXIGP6WDATA_delay[82]; // rv 0 + assign SAXIGP6WDATA_in[83] = (SAXIGP6WDATA[83] !== 1'bz) && SAXIGP6WDATA_delay[83]; // rv 0 + assign SAXIGP6WDATA_in[84] = (SAXIGP6WDATA[84] !== 1'bz) && SAXIGP6WDATA_delay[84]; // rv 0 + assign SAXIGP6WDATA_in[85] = (SAXIGP6WDATA[85] !== 1'bz) && SAXIGP6WDATA_delay[85]; // rv 0 + assign SAXIGP6WDATA_in[86] = (SAXIGP6WDATA[86] !== 1'bz) && SAXIGP6WDATA_delay[86]; // rv 0 + assign SAXIGP6WDATA_in[87] = (SAXIGP6WDATA[87] !== 1'bz) && SAXIGP6WDATA_delay[87]; // rv 0 + assign SAXIGP6WDATA_in[88] = (SAXIGP6WDATA[88] !== 1'bz) && SAXIGP6WDATA_delay[88]; // rv 0 + assign SAXIGP6WDATA_in[89] = (SAXIGP6WDATA[89] !== 1'bz) && SAXIGP6WDATA_delay[89]; // rv 0 + assign SAXIGP6WDATA_in[8] = (SAXIGP6WDATA[8] !== 1'bz) && SAXIGP6WDATA_delay[8]; // rv 0 + assign SAXIGP6WDATA_in[90] = (SAXIGP6WDATA[90] !== 1'bz) && SAXIGP6WDATA_delay[90]; // rv 0 + assign SAXIGP6WDATA_in[91] = (SAXIGP6WDATA[91] !== 1'bz) && SAXIGP6WDATA_delay[91]; // rv 0 + assign SAXIGP6WDATA_in[92] = (SAXIGP6WDATA[92] !== 1'bz) && SAXIGP6WDATA_delay[92]; // rv 0 + assign SAXIGP6WDATA_in[93] = (SAXIGP6WDATA[93] !== 1'bz) && SAXIGP6WDATA_delay[93]; // rv 0 + assign SAXIGP6WDATA_in[94] = (SAXIGP6WDATA[94] !== 1'bz) && SAXIGP6WDATA_delay[94]; // rv 0 + assign SAXIGP6WDATA_in[95] = (SAXIGP6WDATA[95] !== 1'bz) && SAXIGP6WDATA_delay[95]; // rv 0 + assign SAXIGP6WDATA_in[96] = (SAXIGP6WDATA[96] !== 1'bz) && SAXIGP6WDATA_delay[96]; // rv 0 + assign SAXIGP6WDATA_in[97] = (SAXIGP6WDATA[97] !== 1'bz) && SAXIGP6WDATA_delay[97]; // rv 0 + assign SAXIGP6WDATA_in[98] = (SAXIGP6WDATA[98] !== 1'bz) && SAXIGP6WDATA_delay[98]; // rv 0 + assign SAXIGP6WDATA_in[99] = (SAXIGP6WDATA[99] !== 1'bz) && SAXIGP6WDATA_delay[99]; // rv 0 + assign SAXIGP6WDATA_in[9] = (SAXIGP6WDATA[9] !== 1'bz) && SAXIGP6WDATA_delay[9]; // rv 0 + assign SAXIGP6WLAST_in = (SAXIGP6WLAST !== 1'bz) && SAXIGP6WLAST_delay; // rv 0 + assign SAXIGP6WSTRB_in[0] = (SAXIGP6WSTRB[0] !== 1'bz) && SAXIGP6WSTRB_delay[0]; // rv 0 + assign SAXIGP6WSTRB_in[10] = (SAXIGP6WSTRB[10] !== 1'bz) && SAXIGP6WSTRB_delay[10]; // rv 0 + assign SAXIGP6WSTRB_in[11] = (SAXIGP6WSTRB[11] !== 1'bz) && SAXIGP6WSTRB_delay[11]; // rv 0 + assign SAXIGP6WSTRB_in[12] = (SAXIGP6WSTRB[12] !== 1'bz) && SAXIGP6WSTRB_delay[12]; // rv 0 + assign SAXIGP6WSTRB_in[13] = (SAXIGP6WSTRB[13] !== 1'bz) && SAXIGP6WSTRB_delay[13]; // rv 0 + assign SAXIGP6WSTRB_in[14] = (SAXIGP6WSTRB[14] !== 1'bz) && SAXIGP6WSTRB_delay[14]; // rv 0 + assign SAXIGP6WSTRB_in[15] = (SAXIGP6WSTRB[15] !== 1'bz) && SAXIGP6WSTRB_delay[15]; // rv 0 + assign SAXIGP6WSTRB_in[1] = (SAXIGP6WSTRB[1] !== 1'bz) && SAXIGP6WSTRB_delay[1]; // rv 0 + assign SAXIGP6WSTRB_in[2] = (SAXIGP6WSTRB[2] !== 1'bz) && SAXIGP6WSTRB_delay[2]; // rv 0 + assign SAXIGP6WSTRB_in[3] = (SAXIGP6WSTRB[3] !== 1'bz) && SAXIGP6WSTRB_delay[3]; // rv 0 + assign SAXIGP6WSTRB_in[4] = (SAXIGP6WSTRB[4] !== 1'bz) && SAXIGP6WSTRB_delay[4]; // rv 0 + assign SAXIGP6WSTRB_in[5] = (SAXIGP6WSTRB[5] !== 1'bz) && SAXIGP6WSTRB_delay[5]; // rv 0 + assign SAXIGP6WSTRB_in[6] = (SAXIGP6WSTRB[6] !== 1'bz) && SAXIGP6WSTRB_delay[6]; // rv 0 + assign SAXIGP6WSTRB_in[7] = (SAXIGP6WSTRB[7] !== 1'bz) && SAXIGP6WSTRB_delay[7]; // rv 0 + assign SAXIGP6WSTRB_in[8] = (SAXIGP6WSTRB[8] !== 1'bz) && SAXIGP6WSTRB_delay[8]; // rv 0 + assign SAXIGP6WSTRB_in[9] = (SAXIGP6WSTRB[9] !== 1'bz) && SAXIGP6WSTRB_delay[9]; // rv 0 + assign SAXIGP6WVALID_in = (SAXIGP6WVALID !== 1'bz) && SAXIGP6WVALID_delay; // rv 0 +`else + assign ADMAFCICLK_in[0] = (ADMAFCICLK[0] !== 1'bz) && ADMAFCICLK[0]; // rv 0 + assign ADMAFCICLK_in[1] = (ADMAFCICLK[1] !== 1'bz) && ADMAFCICLK[1]; // rv 0 + assign ADMAFCICLK_in[2] = (ADMAFCICLK[2] !== 1'bz) && ADMAFCICLK[2]; // rv 0 + assign ADMAFCICLK_in[3] = (ADMAFCICLK[3] !== 1'bz) && ADMAFCICLK[3]; // rv 0 + assign ADMAFCICLK_in[4] = (ADMAFCICLK[4] !== 1'bz) && ADMAFCICLK[4]; // rv 0 + assign ADMAFCICLK_in[5] = (ADMAFCICLK[5] !== 1'bz) && ADMAFCICLK[5]; // rv 0 + assign ADMAFCICLK_in[6] = (ADMAFCICLK[6] !== 1'bz) && ADMAFCICLK[6]; // rv 0 + assign ADMAFCICLK_in[7] = (ADMAFCICLK[7] !== 1'bz) && ADMAFCICLK[7]; // rv 0 + assign DDRCEXTREFRESHRANK0REQ_in = (DDRCEXTREFRESHRANK0REQ !== 1'bz) && DDRCEXTREFRESHRANK0REQ; // rv 0 + assign DDRCEXTREFRESHRANK1REQ_in = (DDRCEXTREFRESHRANK1REQ !== 1'bz) && DDRCEXTREFRESHRANK1REQ; // rv 0 + assign DDRCREFRESHPLCLK_in = (DDRCREFRESHPLCLK !== 1'bz) && DDRCREFRESHPLCLK; // rv 0 + assign DPLIVEGFXALPHAIN_in[0] = (DPLIVEGFXALPHAIN[0] !== 1'bz) && DPLIVEGFXALPHAIN[0]; // rv 0 + assign DPLIVEGFXALPHAIN_in[1] = (DPLIVEGFXALPHAIN[1] !== 1'bz) && DPLIVEGFXALPHAIN[1]; // rv 0 + assign DPLIVEGFXALPHAIN_in[2] = (DPLIVEGFXALPHAIN[2] !== 1'bz) && DPLIVEGFXALPHAIN[2]; // rv 0 + assign DPLIVEGFXALPHAIN_in[3] = (DPLIVEGFXALPHAIN[3] !== 1'bz) && DPLIVEGFXALPHAIN[3]; // rv 0 + assign DPLIVEGFXALPHAIN_in[4] = (DPLIVEGFXALPHAIN[4] !== 1'bz) && DPLIVEGFXALPHAIN[4]; // rv 0 + assign DPLIVEGFXALPHAIN_in[5] = (DPLIVEGFXALPHAIN[5] !== 1'bz) && DPLIVEGFXALPHAIN[5]; // rv 0 + assign DPLIVEGFXALPHAIN_in[6] = (DPLIVEGFXALPHAIN[6] !== 1'bz) && DPLIVEGFXALPHAIN[6]; // rv 0 + assign DPLIVEGFXALPHAIN_in[7] = (DPLIVEGFXALPHAIN[7] !== 1'bz) && DPLIVEGFXALPHAIN[7]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[0] = (DPLIVEGFXPIXEL1IN[0] !== 1'bz) && DPLIVEGFXPIXEL1IN[0]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[10] = (DPLIVEGFXPIXEL1IN[10] !== 1'bz) && DPLIVEGFXPIXEL1IN[10]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[11] = (DPLIVEGFXPIXEL1IN[11] !== 1'bz) && DPLIVEGFXPIXEL1IN[11]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[12] = (DPLIVEGFXPIXEL1IN[12] !== 1'bz) && DPLIVEGFXPIXEL1IN[12]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[13] = (DPLIVEGFXPIXEL1IN[13] !== 1'bz) && DPLIVEGFXPIXEL1IN[13]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[14] = (DPLIVEGFXPIXEL1IN[14] !== 1'bz) && DPLIVEGFXPIXEL1IN[14]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[15] = (DPLIVEGFXPIXEL1IN[15] !== 1'bz) && DPLIVEGFXPIXEL1IN[15]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[16] = (DPLIVEGFXPIXEL1IN[16] !== 1'bz) && DPLIVEGFXPIXEL1IN[16]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[17] = (DPLIVEGFXPIXEL1IN[17] !== 1'bz) && DPLIVEGFXPIXEL1IN[17]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[18] = (DPLIVEGFXPIXEL1IN[18] !== 1'bz) && DPLIVEGFXPIXEL1IN[18]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[19] = (DPLIVEGFXPIXEL1IN[19] !== 1'bz) && DPLIVEGFXPIXEL1IN[19]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[1] = (DPLIVEGFXPIXEL1IN[1] !== 1'bz) && DPLIVEGFXPIXEL1IN[1]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[20] = (DPLIVEGFXPIXEL1IN[20] !== 1'bz) && DPLIVEGFXPIXEL1IN[20]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[21] = (DPLIVEGFXPIXEL1IN[21] !== 1'bz) && DPLIVEGFXPIXEL1IN[21]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[22] = (DPLIVEGFXPIXEL1IN[22] !== 1'bz) && DPLIVEGFXPIXEL1IN[22]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[23] = (DPLIVEGFXPIXEL1IN[23] !== 1'bz) && DPLIVEGFXPIXEL1IN[23]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[24] = (DPLIVEGFXPIXEL1IN[24] !== 1'bz) && DPLIVEGFXPIXEL1IN[24]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[25] = (DPLIVEGFXPIXEL1IN[25] !== 1'bz) && DPLIVEGFXPIXEL1IN[25]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[26] = (DPLIVEGFXPIXEL1IN[26] !== 1'bz) && DPLIVEGFXPIXEL1IN[26]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[27] = (DPLIVEGFXPIXEL1IN[27] !== 1'bz) && DPLIVEGFXPIXEL1IN[27]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[28] = (DPLIVEGFXPIXEL1IN[28] !== 1'bz) && DPLIVEGFXPIXEL1IN[28]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[29] = (DPLIVEGFXPIXEL1IN[29] !== 1'bz) && DPLIVEGFXPIXEL1IN[29]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[2] = (DPLIVEGFXPIXEL1IN[2] !== 1'bz) && DPLIVEGFXPIXEL1IN[2]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[30] = (DPLIVEGFXPIXEL1IN[30] !== 1'bz) && DPLIVEGFXPIXEL1IN[30]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[31] = (DPLIVEGFXPIXEL1IN[31] !== 1'bz) && DPLIVEGFXPIXEL1IN[31]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[32] = (DPLIVEGFXPIXEL1IN[32] !== 1'bz) && DPLIVEGFXPIXEL1IN[32]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[33] = (DPLIVEGFXPIXEL1IN[33] !== 1'bz) && DPLIVEGFXPIXEL1IN[33]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[34] = (DPLIVEGFXPIXEL1IN[34] !== 1'bz) && DPLIVEGFXPIXEL1IN[34]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[35] = (DPLIVEGFXPIXEL1IN[35] !== 1'bz) && DPLIVEGFXPIXEL1IN[35]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[3] = (DPLIVEGFXPIXEL1IN[3] !== 1'bz) && DPLIVEGFXPIXEL1IN[3]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[4] = (DPLIVEGFXPIXEL1IN[4] !== 1'bz) && DPLIVEGFXPIXEL1IN[4]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[5] = (DPLIVEGFXPIXEL1IN[5] !== 1'bz) && DPLIVEGFXPIXEL1IN[5]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[6] = (DPLIVEGFXPIXEL1IN[6] !== 1'bz) && DPLIVEGFXPIXEL1IN[6]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[7] = (DPLIVEGFXPIXEL1IN[7] !== 1'bz) && DPLIVEGFXPIXEL1IN[7]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[8] = (DPLIVEGFXPIXEL1IN[8] !== 1'bz) && DPLIVEGFXPIXEL1IN[8]; // rv 0 + assign DPLIVEGFXPIXEL1IN_in[9] = (DPLIVEGFXPIXEL1IN[9] !== 1'bz) && DPLIVEGFXPIXEL1IN[9]; // rv 0 + assign DPLIVEVIDEOINDE_in = (DPLIVEVIDEOINDE !== 1'bz) && DPLIVEVIDEOINDE; // rv 0 + assign DPLIVEVIDEOINHSYNC_in = (DPLIVEVIDEOINHSYNC !== 1'bz) && DPLIVEVIDEOINHSYNC; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[0] = (DPLIVEVIDEOINPIXEL1[0] !== 1'bz) && DPLIVEVIDEOINPIXEL1[0]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[10] = (DPLIVEVIDEOINPIXEL1[10] !== 1'bz) && DPLIVEVIDEOINPIXEL1[10]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[11] = (DPLIVEVIDEOINPIXEL1[11] !== 1'bz) && DPLIVEVIDEOINPIXEL1[11]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[12] = (DPLIVEVIDEOINPIXEL1[12] !== 1'bz) && DPLIVEVIDEOINPIXEL1[12]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[13] = (DPLIVEVIDEOINPIXEL1[13] !== 1'bz) && DPLIVEVIDEOINPIXEL1[13]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[14] = (DPLIVEVIDEOINPIXEL1[14] !== 1'bz) && DPLIVEVIDEOINPIXEL1[14]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[15] = (DPLIVEVIDEOINPIXEL1[15] !== 1'bz) && DPLIVEVIDEOINPIXEL1[15]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[16] = (DPLIVEVIDEOINPIXEL1[16] !== 1'bz) && DPLIVEVIDEOINPIXEL1[16]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[17] = (DPLIVEVIDEOINPIXEL1[17] !== 1'bz) && DPLIVEVIDEOINPIXEL1[17]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[18] = (DPLIVEVIDEOINPIXEL1[18] !== 1'bz) && DPLIVEVIDEOINPIXEL1[18]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[19] = (DPLIVEVIDEOINPIXEL1[19] !== 1'bz) && DPLIVEVIDEOINPIXEL1[19]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[1] = (DPLIVEVIDEOINPIXEL1[1] !== 1'bz) && DPLIVEVIDEOINPIXEL1[1]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[20] = (DPLIVEVIDEOINPIXEL1[20] !== 1'bz) && DPLIVEVIDEOINPIXEL1[20]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[21] = (DPLIVEVIDEOINPIXEL1[21] !== 1'bz) && DPLIVEVIDEOINPIXEL1[21]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[22] = (DPLIVEVIDEOINPIXEL1[22] !== 1'bz) && DPLIVEVIDEOINPIXEL1[22]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[23] = (DPLIVEVIDEOINPIXEL1[23] !== 1'bz) && DPLIVEVIDEOINPIXEL1[23]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[24] = (DPLIVEVIDEOINPIXEL1[24] !== 1'bz) && DPLIVEVIDEOINPIXEL1[24]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[25] = (DPLIVEVIDEOINPIXEL1[25] !== 1'bz) && DPLIVEVIDEOINPIXEL1[25]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[26] = (DPLIVEVIDEOINPIXEL1[26] !== 1'bz) && DPLIVEVIDEOINPIXEL1[26]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[27] = (DPLIVEVIDEOINPIXEL1[27] !== 1'bz) && DPLIVEVIDEOINPIXEL1[27]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[28] = (DPLIVEVIDEOINPIXEL1[28] !== 1'bz) && DPLIVEVIDEOINPIXEL1[28]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[29] = (DPLIVEVIDEOINPIXEL1[29] !== 1'bz) && DPLIVEVIDEOINPIXEL1[29]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[2] = (DPLIVEVIDEOINPIXEL1[2] !== 1'bz) && DPLIVEVIDEOINPIXEL1[2]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[30] = (DPLIVEVIDEOINPIXEL1[30] !== 1'bz) && DPLIVEVIDEOINPIXEL1[30]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[31] = (DPLIVEVIDEOINPIXEL1[31] !== 1'bz) && DPLIVEVIDEOINPIXEL1[31]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[32] = (DPLIVEVIDEOINPIXEL1[32] !== 1'bz) && DPLIVEVIDEOINPIXEL1[32]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[33] = (DPLIVEVIDEOINPIXEL1[33] !== 1'bz) && DPLIVEVIDEOINPIXEL1[33]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[34] = (DPLIVEVIDEOINPIXEL1[34] !== 1'bz) && DPLIVEVIDEOINPIXEL1[34]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[35] = (DPLIVEVIDEOINPIXEL1[35] !== 1'bz) && DPLIVEVIDEOINPIXEL1[35]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[3] = (DPLIVEVIDEOINPIXEL1[3] !== 1'bz) && DPLIVEVIDEOINPIXEL1[3]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[4] = (DPLIVEVIDEOINPIXEL1[4] !== 1'bz) && DPLIVEVIDEOINPIXEL1[4]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[5] = (DPLIVEVIDEOINPIXEL1[5] !== 1'bz) && DPLIVEVIDEOINPIXEL1[5]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[6] = (DPLIVEVIDEOINPIXEL1[6] !== 1'bz) && DPLIVEVIDEOINPIXEL1[6]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[7] = (DPLIVEVIDEOINPIXEL1[7] !== 1'bz) && DPLIVEVIDEOINPIXEL1[7]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[8] = (DPLIVEVIDEOINPIXEL1[8] !== 1'bz) && DPLIVEVIDEOINPIXEL1[8]; // rv 0 + assign DPLIVEVIDEOINPIXEL1_in[9] = (DPLIVEVIDEOINPIXEL1[9] !== 1'bz) && DPLIVEVIDEOINPIXEL1[9]; // rv 0 + assign DPLIVEVIDEOINVSYNC_in = (DPLIVEVIDEOINVSYNC !== 1'bz) && DPLIVEVIDEOINVSYNC; // rv 0 + assign DPMAXISMIXEDAUDIOTREADY_in = (DPMAXISMIXEDAUDIOTREADY !== 1'bz) && DPMAXISMIXEDAUDIOTREADY; // rv 0 + assign DPSAXISAUDIOCLK_in = (DPSAXISAUDIOCLK === 1'bz) || DPSAXISAUDIOCLK; // rv 1 + assign DPSAXISAUDIOTDATA_in[0] = (DPSAXISAUDIOTDATA[0] !== 1'bz) && DPSAXISAUDIOTDATA[0]; // rv 0 + assign DPSAXISAUDIOTDATA_in[10] = (DPSAXISAUDIOTDATA[10] !== 1'bz) && DPSAXISAUDIOTDATA[10]; // rv 0 + assign DPSAXISAUDIOTDATA_in[11] = (DPSAXISAUDIOTDATA[11] !== 1'bz) && DPSAXISAUDIOTDATA[11]; // rv 0 + assign DPSAXISAUDIOTDATA_in[12] = (DPSAXISAUDIOTDATA[12] !== 1'bz) && DPSAXISAUDIOTDATA[12]; // rv 0 + assign DPSAXISAUDIOTDATA_in[13] = (DPSAXISAUDIOTDATA[13] !== 1'bz) && DPSAXISAUDIOTDATA[13]; // rv 0 + assign DPSAXISAUDIOTDATA_in[14] = (DPSAXISAUDIOTDATA[14] !== 1'bz) && DPSAXISAUDIOTDATA[14]; // rv 0 + assign DPSAXISAUDIOTDATA_in[15] = (DPSAXISAUDIOTDATA[15] !== 1'bz) && DPSAXISAUDIOTDATA[15]; // rv 0 + assign DPSAXISAUDIOTDATA_in[16] = (DPSAXISAUDIOTDATA[16] !== 1'bz) && DPSAXISAUDIOTDATA[16]; // rv 0 + assign DPSAXISAUDIOTDATA_in[17] = (DPSAXISAUDIOTDATA[17] !== 1'bz) && DPSAXISAUDIOTDATA[17]; // rv 0 + assign DPSAXISAUDIOTDATA_in[18] = (DPSAXISAUDIOTDATA[18] !== 1'bz) && DPSAXISAUDIOTDATA[18]; // rv 0 + assign DPSAXISAUDIOTDATA_in[19] = (DPSAXISAUDIOTDATA[19] !== 1'bz) && DPSAXISAUDIOTDATA[19]; // rv 0 + assign DPSAXISAUDIOTDATA_in[1] = (DPSAXISAUDIOTDATA[1] !== 1'bz) && DPSAXISAUDIOTDATA[1]; // rv 0 + assign DPSAXISAUDIOTDATA_in[20] = (DPSAXISAUDIOTDATA[20] !== 1'bz) && DPSAXISAUDIOTDATA[20]; // rv 0 + assign DPSAXISAUDIOTDATA_in[21] = (DPSAXISAUDIOTDATA[21] !== 1'bz) && DPSAXISAUDIOTDATA[21]; // rv 0 + assign DPSAXISAUDIOTDATA_in[22] = (DPSAXISAUDIOTDATA[22] !== 1'bz) && DPSAXISAUDIOTDATA[22]; // rv 0 + assign DPSAXISAUDIOTDATA_in[23] = (DPSAXISAUDIOTDATA[23] !== 1'bz) && DPSAXISAUDIOTDATA[23]; // rv 0 + assign DPSAXISAUDIOTDATA_in[24] = (DPSAXISAUDIOTDATA[24] !== 1'bz) && DPSAXISAUDIOTDATA[24]; // rv 0 + assign DPSAXISAUDIOTDATA_in[25] = (DPSAXISAUDIOTDATA[25] !== 1'bz) && DPSAXISAUDIOTDATA[25]; // rv 0 + assign DPSAXISAUDIOTDATA_in[26] = (DPSAXISAUDIOTDATA[26] !== 1'bz) && DPSAXISAUDIOTDATA[26]; // rv 0 + assign DPSAXISAUDIOTDATA_in[27] = (DPSAXISAUDIOTDATA[27] !== 1'bz) && DPSAXISAUDIOTDATA[27]; // rv 0 + assign DPSAXISAUDIOTDATA_in[28] = (DPSAXISAUDIOTDATA[28] !== 1'bz) && DPSAXISAUDIOTDATA[28]; // rv 0 + assign DPSAXISAUDIOTDATA_in[29] = (DPSAXISAUDIOTDATA[29] !== 1'bz) && DPSAXISAUDIOTDATA[29]; // rv 0 + assign DPSAXISAUDIOTDATA_in[2] = (DPSAXISAUDIOTDATA[2] !== 1'bz) && DPSAXISAUDIOTDATA[2]; // rv 0 + assign DPSAXISAUDIOTDATA_in[30] = (DPSAXISAUDIOTDATA[30] !== 1'bz) && DPSAXISAUDIOTDATA[30]; // rv 0 + assign DPSAXISAUDIOTDATA_in[31] = (DPSAXISAUDIOTDATA[31] !== 1'bz) && DPSAXISAUDIOTDATA[31]; // rv 0 + assign DPSAXISAUDIOTDATA_in[3] = (DPSAXISAUDIOTDATA[3] !== 1'bz) && DPSAXISAUDIOTDATA[3]; // rv 0 + assign DPSAXISAUDIOTDATA_in[4] = (DPSAXISAUDIOTDATA[4] !== 1'bz) && DPSAXISAUDIOTDATA[4]; // rv 0 + assign DPSAXISAUDIOTDATA_in[5] = (DPSAXISAUDIOTDATA[5] !== 1'bz) && DPSAXISAUDIOTDATA[5]; // rv 0 + assign DPSAXISAUDIOTDATA_in[6] = (DPSAXISAUDIOTDATA[6] !== 1'bz) && DPSAXISAUDIOTDATA[6]; // rv 0 + assign DPSAXISAUDIOTDATA_in[7] = (DPSAXISAUDIOTDATA[7] !== 1'bz) && DPSAXISAUDIOTDATA[7]; // rv 0 + assign DPSAXISAUDIOTDATA_in[8] = (DPSAXISAUDIOTDATA[8] !== 1'bz) && DPSAXISAUDIOTDATA[8]; // rv 0 + assign DPSAXISAUDIOTDATA_in[9] = (DPSAXISAUDIOTDATA[9] !== 1'bz) && DPSAXISAUDIOTDATA[9]; // rv 0 + assign DPSAXISAUDIOTID_in = (DPSAXISAUDIOTID !== 1'bz) && DPSAXISAUDIOTID; // rv 0 + assign DPSAXISAUDIOTVALID_in = (DPSAXISAUDIOTVALID !== 1'bz) && DPSAXISAUDIOTVALID; // rv 0 + assign DPVIDEOINCLK_in = (DPVIDEOINCLK === 1'bz) || DPVIDEOINCLK; // rv 1 + assign EMIOENET0GMIIRXCLK_in = (EMIOENET0GMIIRXCLK !== 1'bz) && EMIOENET0GMIIRXCLK; // rv 0 + assign EMIOENET0GMIIRXDV_in = (EMIOENET0GMIIRXDV !== 1'bz) && EMIOENET0GMIIRXDV; // rv 0 + assign EMIOENET0GMIIRXD_in[0] = (EMIOENET0GMIIRXD[0] !== 1'bz) && EMIOENET0GMIIRXD[0]; // rv 0 + assign EMIOENET0GMIIRXD_in[1] = (EMIOENET0GMIIRXD[1] !== 1'bz) && EMIOENET0GMIIRXD[1]; // rv 0 + assign EMIOENET0GMIIRXD_in[2] = (EMIOENET0GMIIRXD[2] !== 1'bz) && EMIOENET0GMIIRXD[2]; // rv 0 + assign EMIOENET0GMIIRXD_in[3] = (EMIOENET0GMIIRXD[3] !== 1'bz) && EMIOENET0GMIIRXD[3]; // rv 0 + assign EMIOENET0GMIIRXD_in[4] = (EMIOENET0GMIIRXD[4] !== 1'bz) && EMIOENET0GMIIRXD[4]; // rv 0 + assign EMIOENET0GMIIRXD_in[5] = (EMIOENET0GMIIRXD[5] !== 1'bz) && EMIOENET0GMIIRXD[5]; // rv 0 + assign EMIOENET0GMIIRXD_in[6] = (EMIOENET0GMIIRXD[6] !== 1'bz) && EMIOENET0GMIIRXD[6]; // rv 0 + assign EMIOENET0GMIIRXD_in[7] = (EMIOENET0GMIIRXD[7] !== 1'bz) && EMIOENET0GMIIRXD[7]; // rv 0 + assign EMIOENET0GMIIRXER_in = (EMIOENET0GMIIRXER !== 1'bz) && EMIOENET0GMIIRXER; // rv 0 + assign EMIOENET0TXRCONTROL_in = (EMIOENET0TXRCONTROL !== 1'bz) && EMIOENET0TXRCONTROL; // rv 0 + assign EMIOENET0TXRDATARDY_in = (EMIOENET0TXRDATARDY !== 1'bz) && EMIOENET0TXRDATARDY; // rv 0 + assign EMIOENET0TXRDATA_in[0] = (EMIOENET0TXRDATA[0] !== 1'bz) && EMIOENET0TXRDATA[0]; // rv 0 + assign EMIOENET0TXRDATA_in[1] = (EMIOENET0TXRDATA[1] !== 1'bz) && EMIOENET0TXRDATA[1]; // rv 0 + assign EMIOENET0TXRDATA_in[2] = (EMIOENET0TXRDATA[2] !== 1'bz) && EMIOENET0TXRDATA[2]; // rv 0 + assign EMIOENET0TXRDATA_in[3] = (EMIOENET0TXRDATA[3] !== 1'bz) && EMIOENET0TXRDATA[3]; // rv 0 + assign EMIOENET0TXRDATA_in[4] = (EMIOENET0TXRDATA[4] !== 1'bz) && EMIOENET0TXRDATA[4]; // rv 0 + assign EMIOENET0TXRDATA_in[5] = (EMIOENET0TXRDATA[5] !== 1'bz) && EMIOENET0TXRDATA[5]; // rv 0 + assign EMIOENET0TXRDATA_in[6] = (EMIOENET0TXRDATA[6] !== 1'bz) && EMIOENET0TXRDATA[6]; // rv 0 + assign EMIOENET0TXRDATA_in[7] = (EMIOENET0TXRDATA[7] !== 1'bz) && EMIOENET0TXRDATA[7]; // rv 0 + assign EMIOENET0TXREOP_in = (EMIOENET0TXREOP === 1'bz) || EMIOENET0TXREOP; // rv 1 + assign EMIOENET0TXRERR_in = (EMIOENET0TXRERR !== 1'bz) && EMIOENET0TXRERR; // rv 0 + assign EMIOENET0TXRFLUSHED_in = (EMIOENET0TXRFLUSHED !== 1'bz) && EMIOENET0TXRFLUSHED; // rv 0 + assign EMIOENET0TXRSOP_in = (EMIOENET0TXRSOP === 1'bz) || EMIOENET0TXRSOP; // rv 1 + assign EMIOENET0TXRUNDERFLOW_in = (EMIOENET0TXRUNDERFLOW !== 1'bz) && EMIOENET0TXRUNDERFLOW; // rv 0 + assign EMIOENET0TXRVALID_in = (EMIOENET0TXRVALID !== 1'bz) && EMIOENET0TXRVALID; // rv 0 + assign EMIOENET1GMIIRXCLK_in = (EMIOENET1GMIIRXCLK !== 1'bz) && EMIOENET1GMIIRXCLK; // rv 0 + assign EMIOENET1GMIIRXDV_in = (EMIOENET1GMIIRXDV !== 1'bz) && EMIOENET1GMIIRXDV; // rv 0 + assign EMIOENET1GMIIRXD_in[0] = (EMIOENET1GMIIRXD[0] !== 1'bz) && EMIOENET1GMIIRXD[0]; // rv 0 + assign EMIOENET1GMIIRXD_in[1] = (EMIOENET1GMIIRXD[1] !== 1'bz) && EMIOENET1GMIIRXD[1]; // rv 0 + assign EMIOENET1GMIIRXD_in[2] = (EMIOENET1GMIIRXD[2] !== 1'bz) && EMIOENET1GMIIRXD[2]; // rv 0 + assign EMIOENET1GMIIRXD_in[3] = (EMIOENET1GMIIRXD[3] !== 1'bz) && EMIOENET1GMIIRXD[3]; // rv 0 + assign EMIOENET1GMIIRXD_in[4] = (EMIOENET1GMIIRXD[4] !== 1'bz) && EMIOENET1GMIIRXD[4]; // rv 0 + assign EMIOENET1GMIIRXD_in[5] = (EMIOENET1GMIIRXD[5] !== 1'bz) && EMIOENET1GMIIRXD[5]; // rv 0 + assign EMIOENET1GMIIRXD_in[6] = (EMIOENET1GMIIRXD[6] !== 1'bz) && EMIOENET1GMIIRXD[6]; // rv 0 + assign EMIOENET1GMIIRXD_in[7] = (EMIOENET1GMIIRXD[7] !== 1'bz) && EMIOENET1GMIIRXD[7]; // rv 0 + assign EMIOENET1GMIIRXER_in = (EMIOENET1GMIIRXER !== 1'bz) && EMIOENET1GMIIRXER; // rv 0 + assign EMIOENET1TXRCONTROL_in = (EMIOENET1TXRCONTROL !== 1'bz) && EMIOENET1TXRCONTROL; // rv 0 + assign EMIOENET1TXRDATARDY_in = (EMIOENET1TXRDATARDY !== 1'bz) && EMIOENET1TXRDATARDY; // rv 0 + assign EMIOENET1TXRDATA_in[0] = (EMIOENET1TXRDATA[0] !== 1'bz) && EMIOENET1TXRDATA[0]; // rv 0 + assign EMIOENET1TXRDATA_in[1] = (EMIOENET1TXRDATA[1] !== 1'bz) && EMIOENET1TXRDATA[1]; // rv 0 + assign EMIOENET1TXRDATA_in[2] = (EMIOENET1TXRDATA[2] !== 1'bz) && EMIOENET1TXRDATA[2]; // rv 0 + assign EMIOENET1TXRDATA_in[3] = (EMIOENET1TXRDATA[3] !== 1'bz) && EMIOENET1TXRDATA[3]; // rv 0 + assign EMIOENET1TXRDATA_in[4] = (EMIOENET1TXRDATA[4] !== 1'bz) && EMIOENET1TXRDATA[4]; // rv 0 + assign EMIOENET1TXRDATA_in[5] = (EMIOENET1TXRDATA[5] !== 1'bz) && EMIOENET1TXRDATA[5]; // rv 0 + assign EMIOENET1TXRDATA_in[6] = (EMIOENET1TXRDATA[6] !== 1'bz) && EMIOENET1TXRDATA[6]; // rv 0 + assign EMIOENET1TXRDATA_in[7] = (EMIOENET1TXRDATA[7] !== 1'bz) && EMIOENET1TXRDATA[7]; // rv 0 + assign EMIOENET1TXREOP_in = (EMIOENET1TXREOP === 1'bz) || EMIOENET1TXREOP; // rv 1 + assign EMIOENET1TXRERR_in = (EMIOENET1TXRERR !== 1'bz) && EMIOENET1TXRERR; // rv 0 + assign EMIOENET1TXRFLUSHED_in = (EMIOENET1TXRFLUSHED !== 1'bz) && EMIOENET1TXRFLUSHED; // rv 0 + assign EMIOENET1TXRSOP_in = (EMIOENET1TXRSOP === 1'bz) || EMIOENET1TXRSOP; // rv 1 + assign EMIOENET1TXRUNDERFLOW_in = (EMIOENET1TXRUNDERFLOW !== 1'bz) && EMIOENET1TXRUNDERFLOW; // rv 0 + assign EMIOENET1TXRVALID_in = (EMIOENET1TXRVALID !== 1'bz) && EMIOENET1TXRVALID; // rv 0 + assign EMIOENET2GMIIRXCLK_in = (EMIOENET2GMIIRXCLK !== 1'bz) && EMIOENET2GMIIRXCLK; // rv 0 + assign EMIOENET2GMIIRXDV_in = (EMIOENET2GMIIRXDV !== 1'bz) && EMIOENET2GMIIRXDV; // rv 0 + assign EMIOENET2GMIIRXD_in[0] = (EMIOENET2GMIIRXD[0] !== 1'bz) && EMIOENET2GMIIRXD[0]; // rv 0 + assign EMIOENET2GMIIRXD_in[1] = (EMIOENET2GMIIRXD[1] !== 1'bz) && EMIOENET2GMIIRXD[1]; // rv 0 + assign EMIOENET2GMIIRXD_in[2] = (EMIOENET2GMIIRXD[2] !== 1'bz) && EMIOENET2GMIIRXD[2]; // rv 0 + assign EMIOENET2GMIIRXD_in[3] = (EMIOENET2GMIIRXD[3] !== 1'bz) && EMIOENET2GMIIRXD[3]; // rv 0 + assign EMIOENET2GMIIRXD_in[4] = (EMIOENET2GMIIRXD[4] !== 1'bz) && EMIOENET2GMIIRXD[4]; // rv 0 + assign EMIOENET2GMIIRXD_in[5] = (EMIOENET2GMIIRXD[5] !== 1'bz) && EMIOENET2GMIIRXD[5]; // rv 0 + assign EMIOENET2GMIIRXD_in[6] = (EMIOENET2GMIIRXD[6] !== 1'bz) && EMIOENET2GMIIRXD[6]; // rv 0 + assign EMIOENET2GMIIRXD_in[7] = (EMIOENET2GMIIRXD[7] !== 1'bz) && EMIOENET2GMIIRXD[7]; // rv 0 + assign EMIOENET2GMIIRXER_in = (EMIOENET2GMIIRXER !== 1'bz) && EMIOENET2GMIIRXER; // rv 0 + assign EMIOENET2TXRCONTROL_in = (EMIOENET2TXRCONTROL !== 1'bz) && EMIOENET2TXRCONTROL; // rv 0 + assign EMIOENET2TXRDATARDY_in = (EMIOENET2TXRDATARDY !== 1'bz) && EMIOENET2TXRDATARDY; // rv 0 + assign EMIOENET2TXRDATA_in[0] = (EMIOENET2TXRDATA[0] !== 1'bz) && EMIOENET2TXRDATA[0]; // rv 0 + assign EMIOENET2TXRDATA_in[1] = (EMIOENET2TXRDATA[1] !== 1'bz) && EMIOENET2TXRDATA[1]; // rv 0 + assign EMIOENET2TXRDATA_in[2] = (EMIOENET2TXRDATA[2] !== 1'bz) && EMIOENET2TXRDATA[2]; // rv 0 + assign EMIOENET2TXRDATA_in[3] = (EMIOENET2TXRDATA[3] !== 1'bz) && EMIOENET2TXRDATA[3]; // rv 0 + assign EMIOENET2TXRDATA_in[4] = (EMIOENET2TXRDATA[4] !== 1'bz) && EMIOENET2TXRDATA[4]; // rv 0 + assign EMIOENET2TXRDATA_in[5] = (EMIOENET2TXRDATA[5] !== 1'bz) && EMIOENET2TXRDATA[5]; // rv 0 + assign EMIOENET2TXRDATA_in[6] = (EMIOENET2TXRDATA[6] !== 1'bz) && EMIOENET2TXRDATA[6]; // rv 0 + assign EMIOENET2TXRDATA_in[7] = (EMIOENET2TXRDATA[7] !== 1'bz) && EMIOENET2TXRDATA[7]; // rv 0 + assign EMIOENET2TXREOP_in = (EMIOENET2TXREOP === 1'bz) || EMIOENET2TXREOP; // rv 1 + assign EMIOENET2TXRERR_in = (EMIOENET2TXRERR !== 1'bz) && EMIOENET2TXRERR; // rv 0 + assign EMIOENET2TXRFLUSHED_in = (EMIOENET2TXRFLUSHED !== 1'bz) && EMIOENET2TXRFLUSHED; // rv 0 + assign EMIOENET2TXRSOP_in = (EMIOENET2TXRSOP === 1'bz) || EMIOENET2TXRSOP; // rv 1 + assign EMIOENET2TXRUNDERFLOW_in = (EMIOENET2TXRUNDERFLOW !== 1'bz) && EMIOENET2TXRUNDERFLOW; // rv 0 + assign EMIOENET2TXRVALID_in = (EMIOENET2TXRVALID !== 1'bz) && EMIOENET2TXRVALID; // rv 0 + assign EMIOENET3GMIIRXCLK_in = (EMIOENET3GMIIRXCLK !== 1'bz) && EMIOENET3GMIIRXCLK; // rv 0 + assign EMIOENET3GMIIRXDV_in = (EMIOENET3GMIIRXDV !== 1'bz) && EMIOENET3GMIIRXDV; // rv 0 + assign EMIOENET3GMIIRXD_in[0] = (EMIOENET3GMIIRXD[0] !== 1'bz) && EMIOENET3GMIIRXD[0]; // rv 0 + assign EMIOENET3GMIIRXD_in[1] = (EMIOENET3GMIIRXD[1] !== 1'bz) && EMIOENET3GMIIRXD[1]; // rv 0 + assign EMIOENET3GMIIRXD_in[2] = (EMIOENET3GMIIRXD[2] !== 1'bz) && EMIOENET3GMIIRXD[2]; // rv 0 + assign EMIOENET3GMIIRXD_in[3] = (EMIOENET3GMIIRXD[3] !== 1'bz) && EMIOENET3GMIIRXD[3]; // rv 0 + assign EMIOENET3GMIIRXD_in[4] = (EMIOENET3GMIIRXD[4] !== 1'bz) && EMIOENET3GMIIRXD[4]; // rv 0 + assign EMIOENET3GMIIRXD_in[5] = (EMIOENET3GMIIRXD[5] !== 1'bz) && EMIOENET3GMIIRXD[5]; // rv 0 + assign EMIOENET3GMIIRXD_in[6] = (EMIOENET3GMIIRXD[6] !== 1'bz) && EMIOENET3GMIIRXD[6]; // rv 0 + assign EMIOENET3GMIIRXD_in[7] = (EMIOENET3GMIIRXD[7] !== 1'bz) && EMIOENET3GMIIRXD[7]; // rv 0 + assign EMIOENET3GMIIRXER_in = (EMIOENET3GMIIRXER !== 1'bz) && EMIOENET3GMIIRXER; // rv 0 + assign EMIOENET3TXRCONTROL_in = (EMIOENET3TXRCONTROL !== 1'bz) && EMIOENET3TXRCONTROL; // rv 0 + assign EMIOENET3TXRDATARDY_in = (EMIOENET3TXRDATARDY !== 1'bz) && EMIOENET3TXRDATARDY; // rv 0 + assign EMIOENET3TXRDATA_in[0] = (EMIOENET3TXRDATA[0] !== 1'bz) && EMIOENET3TXRDATA[0]; // rv 0 + assign EMIOENET3TXRDATA_in[1] = (EMIOENET3TXRDATA[1] !== 1'bz) && EMIOENET3TXRDATA[1]; // rv 0 + assign EMIOENET3TXRDATA_in[2] = (EMIOENET3TXRDATA[2] !== 1'bz) && EMIOENET3TXRDATA[2]; // rv 0 + assign EMIOENET3TXRDATA_in[3] = (EMIOENET3TXRDATA[3] !== 1'bz) && EMIOENET3TXRDATA[3]; // rv 0 + assign EMIOENET3TXRDATA_in[4] = (EMIOENET3TXRDATA[4] !== 1'bz) && EMIOENET3TXRDATA[4]; // rv 0 + assign EMIOENET3TXRDATA_in[5] = (EMIOENET3TXRDATA[5] !== 1'bz) && EMIOENET3TXRDATA[5]; // rv 0 + assign EMIOENET3TXRDATA_in[6] = (EMIOENET3TXRDATA[6] !== 1'bz) && EMIOENET3TXRDATA[6]; // rv 0 + assign EMIOENET3TXRDATA_in[7] = (EMIOENET3TXRDATA[7] !== 1'bz) && EMIOENET3TXRDATA[7]; // rv 0 + assign EMIOENET3TXREOP_in = (EMIOENET3TXREOP === 1'bz) || EMIOENET3TXREOP; // rv 1 + assign EMIOENET3TXRERR_in = (EMIOENET3TXRERR !== 1'bz) && EMIOENET3TXRERR; // rv 0 + assign EMIOENET3TXRFLUSHED_in = (EMIOENET3TXRFLUSHED !== 1'bz) && EMIOENET3TXRFLUSHED; // rv 0 + assign EMIOENET3TXRSOP_in = (EMIOENET3TXRSOP === 1'bz) || EMIOENET3TXRSOP; // rv 1 + assign EMIOENET3TXRUNDERFLOW_in = (EMIOENET3TXRUNDERFLOW !== 1'bz) && EMIOENET3TXRUNDERFLOW; // rv 0 + assign EMIOENET3TXRVALID_in = (EMIOENET3TXRVALID !== 1'bz) && EMIOENET3TXRVALID; // rv 0 + assign EMIOGEM0TSUINCCTRL_in[0] = (EMIOGEM0TSUINCCTRL[0] !== 1'bz) && EMIOGEM0TSUINCCTRL[0]; // rv 0 + assign EMIOGEM0TSUINCCTRL_in[1] = (EMIOGEM0TSUINCCTRL[1] !== 1'bz) && EMIOGEM0TSUINCCTRL[1]; // rv 0 + assign EMIOGEM1TSUINCCTRL_in[0] = (EMIOGEM1TSUINCCTRL[0] !== 1'bz) && EMIOGEM1TSUINCCTRL[0]; // rv 0 + assign EMIOGEM1TSUINCCTRL_in[1] = (EMIOGEM1TSUINCCTRL[1] !== 1'bz) && EMIOGEM1TSUINCCTRL[1]; // rv 0 + assign EMIOGEM2TSUINCCTRL_in[0] = (EMIOGEM2TSUINCCTRL[0] !== 1'bz) && EMIOGEM2TSUINCCTRL[0]; // rv 0 + assign EMIOGEM2TSUINCCTRL_in[1] = (EMIOGEM2TSUINCCTRL[1] !== 1'bz) && EMIOGEM2TSUINCCTRL[1]; // rv 0 + assign EMIOGEM3TSUINCCTRL_in[0] = (EMIOGEM3TSUINCCTRL[0] !== 1'bz) && EMIOGEM3TSUINCCTRL[0]; // rv 0 + assign EMIOGEM3TSUINCCTRL_in[1] = (EMIOGEM3TSUINCCTRL[1] !== 1'bz) && EMIOGEM3TSUINCCTRL[1]; // rv 0 + assign EMIOSPI0SCLKI_in = (EMIOSPI0SCLKI !== 1'bz) && EMIOSPI0SCLKI; // rv 0 + assign EMIOSPI0SSIN_in = (EMIOSPI0SSIN === 1'bz) || EMIOSPI0SSIN; // rv 1 + assign EMIOSPI1SCLKI_in = (EMIOSPI1SCLKI !== 1'bz) && EMIOSPI1SCLKI; // rv 0 + assign EMIOSPI1SSIN_in = (EMIOSPI1SSIN === 1'bz) || EMIOSPI1SSIN; // rv 1 + assign FMIOGEM0FIFOTXCLKFROMPL_in = (FMIOGEM0FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM0FIFOTXCLKFROMPL; // rv 0 + assign FMIOGEM1FIFOTXCLKFROMPL_in = (FMIOGEM1FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM1FIFOTXCLKFROMPL; // rv 0 + assign FMIOGEM2FIFOTXCLKFROMPL_in = (FMIOGEM2FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM2FIFOTXCLKFROMPL; // rv 0 + assign FMIOGEM3FIFOTXCLKFROMPL_in = (FMIOGEM3FIFOTXCLKFROMPL !== 1'bz) && FMIOGEM3FIFOTXCLKFROMPL; // rv 0 + assign FMIOGEMTSUCLKFROMPL_in = (FMIOGEMTSUCLKFROMPL !== 1'bz) && FMIOGEMTSUCLKFROMPL; // rv 0 + assign GDMAFCICLK_in[0] = (GDMAFCICLK[0] !== 1'bz) && GDMAFCICLK[0]; // rv 0 + assign GDMAFCICLK_in[1] = (GDMAFCICLK[1] !== 1'bz) && GDMAFCICLK[1]; // rv 0 + assign GDMAFCICLK_in[2] = (GDMAFCICLK[2] !== 1'bz) && GDMAFCICLK[2]; // rv 0 + assign GDMAFCICLK_in[3] = (GDMAFCICLK[3] !== 1'bz) && GDMAFCICLK[3]; // rv 0 + assign GDMAFCICLK_in[4] = (GDMAFCICLK[4] !== 1'bz) && GDMAFCICLK[4]; // rv 0 + assign GDMAFCICLK_in[5] = (GDMAFCICLK[5] !== 1'bz) && GDMAFCICLK[5]; // rv 0 + assign GDMAFCICLK_in[6] = (GDMAFCICLK[6] !== 1'bz) && GDMAFCICLK[6]; // rv 0 + assign GDMAFCICLK_in[7] = (GDMAFCICLK[7] !== 1'bz) && GDMAFCICLK[7]; // rv 0 + assign MAXIGP0ACLK_in = (MAXIGP0ACLK !== 1'bz) && MAXIGP0ACLK; // rv 0 + assign MAXIGP0ARREADY_in = (MAXIGP0ARREADY !== 1'bz) && MAXIGP0ARREADY; // rv 0 + assign MAXIGP0AWREADY_in = (MAXIGP0AWREADY !== 1'bz) && MAXIGP0AWREADY; // rv 0 + assign MAXIGP0BID_in[0] = (MAXIGP0BID[0] !== 1'bz) && MAXIGP0BID[0]; // rv 0 + assign MAXIGP0BID_in[10] = (MAXIGP0BID[10] !== 1'bz) && MAXIGP0BID[10]; // rv 0 + assign MAXIGP0BID_in[11] = (MAXIGP0BID[11] !== 1'bz) && MAXIGP0BID[11]; // rv 0 + assign MAXIGP0BID_in[12] = (MAXIGP0BID[12] !== 1'bz) && MAXIGP0BID[12]; // rv 0 + assign MAXIGP0BID_in[13] = (MAXIGP0BID[13] !== 1'bz) && MAXIGP0BID[13]; // rv 0 + assign MAXIGP0BID_in[14] = (MAXIGP0BID[14] !== 1'bz) && MAXIGP0BID[14]; // rv 0 + assign MAXIGP0BID_in[15] = (MAXIGP0BID[15] !== 1'bz) && MAXIGP0BID[15]; // rv 0 + assign MAXIGP0BID_in[1] = (MAXIGP0BID[1] !== 1'bz) && MAXIGP0BID[1]; // rv 0 + assign MAXIGP0BID_in[2] = (MAXIGP0BID[2] !== 1'bz) && MAXIGP0BID[2]; // rv 0 + assign MAXIGP0BID_in[3] = (MAXIGP0BID[3] !== 1'bz) && MAXIGP0BID[3]; // rv 0 + assign MAXIGP0BID_in[4] = (MAXIGP0BID[4] !== 1'bz) && MAXIGP0BID[4]; // rv 0 + assign MAXIGP0BID_in[5] = (MAXIGP0BID[5] !== 1'bz) && MAXIGP0BID[5]; // rv 0 + assign MAXIGP0BID_in[6] = (MAXIGP0BID[6] !== 1'bz) && MAXIGP0BID[6]; // rv 0 + assign MAXIGP0BID_in[7] = (MAXIGP0BID[7] !== 1'bz) && MAXIGP0BID[7]; // rv 0 + assign MAXIGP0BID_in[8] = (MAXIGP0BID[8] !== 1'bz) && MAXIGP0BID[8]; // rv 0 + assign MAXIGP0BID_in[9] = (MAXIGP0BID[9] !== 1'bz) && MAXIGP0BID[9]; // rv 0 + assign MAXIGP0BRESP_in[0] = (MAXIGP0BRESP[0] !== 1'bz) && MAXIGP0BRESP[0]; // rv 0 + assign MAXIGP0BRESP_in[1] = (MAXIGP0BRESP[1] !== 1'bz) && MAXIGP0BRESP[1]; // rv 0 + assign MAXIGP0BVALID_in = (MAXIGP0BVALID !== 1'bz) && MAXIGP0BVALID; // rv 0 + assign MAXIGP0RDATA_in[0] = (MAXIGP0RDATA[0] !== 1'bz) && MAXIGP0RDATA[0]; // rv 0 + assign MAXIGP0RDATA_in[100] = (MAXIGP0RDATA[100] !== 1'bz) && MAXIGP0RDATA[100]; // rv 0 + assign MAXIGP0RDATA_in[101] = (MAXIGP0RDATA[101] !== 1'bz) && MAXIGP0RDATA[101]; // rv 0 + assign MAXIGP0RDATA_in[102] = (MAXIGP0RDATA[102] !== 1'bz) && MAXIGP0RDATA[102]; // rv 0 + assign MAXIGP0RDATA_in[103] = (MAXIGP0RDATA[103] !== 1'bz) && MAXIGP0RDATA[103]; // rv 0 + assign MAXIGP0RDATA_in[104] = (MAXIGP0RDATA[104] !== 1'bz) && MAXIGP0RDATA[104]; // rv 0 + assign MAXIGP0RDATA_in[105] = (MAXIGP0RDATA[105] !== 1'bz) && MAXIGP0RDATA[105]; // rv 0 + assign MAXIGP0RDATA_in[106] = (MAXIGP0RDATA[106] !== 1'bz) && MAXIGP0RDATA[106]; // rv 0 + assign MAXIGP0RDATA_in[107] = (MAXIGP0RDATA[107] !== 1'bz) && MAXIGP0RDATA[107]; // rv 0 + assign MAXIGP0RDATA_in[108] = (MAXIGP0RDATA[108] !== 1'bz) && MAXIGP0RDATA[108]; // rv 0 + assign MAXIGP0RDATA_in[109] = (MAXIGP0RDATA[109] !== 1'bz) && MAXIGP0RDATA[109]; // rv 0 + assign MAXIGP0RDATA_in[10] = (MAXIGP0RDATA[10] !== 1'bz) && MAXIGP0RDATA[10]; // rv 0 + assign MAXIGP0RDATA_in[110] = (MAXIGP0RDATA[110] !== 1'bz) && MAXIGP0RDATA[110]; // rv 0 + assign MAXIGP0RDATA_in[111] = (MAXIGP0RDATA[111] !== 1'bz) && MAXIGP0RDATA[111]; // rv 0 + assign MAXIGP0RDATA_in[112] = (MAXIGP0RDATA[112] !== 1'bz) && MAXIGP0RDATA[112]; // rv 0 + assign MAXIGP0RDATA_in[113] = (MAXIGP0RDATA[113] !== 1'bz) && MAXIGP0RDATA[113]; // rv 0 + assign MAXIGP0RDATA_in[114] = (MAXIGP0RDATA[114] !== 1'bz) && MAXIGP0RDATA[114]; // rv 0 + assign MAXIGP0RDATA_in[115] = (MAXIGP0RDATA[115] !== 1'bz) && MAXIGP0RDATA[115]; // rv 0 + assign MAXIGP0RDATA_in[116] = (MAXIGP0RDATA[116] !== 1'bz) && MAXIGP0RDATA[116]; // rv 0 + assign MAXIGP0RDATA_in[117] = (MAXIGP0RDATA[117] !== 1'bz) && MAXIGP0RDATA[117]; // rv 0 + assign MAXIGP0RDATA_in[118] = (MAXIGP0RDATA[118] !== 1'bz) && MAXIGP0RDATA[118]; // rv 0 + assign MAXIGP0RDATA_in[119] = (MAXIGP0RDATA[119] !== 1'bz) && MAXIGP0RDATA[119]; // rv 0 + assign MAXIGP0RDATA_in[11] = (MAXIGP0RDATA[11] !== 1'bz) && MAXIGP0RDATA[11]; // rv 0 + assign MAXIGP0RDATA_in[120] = (MAXIGP0RDATA[120] !== 1'bz) && MAXIGP0RDATA[120]; // rv 0 + assign MAXIGP0RDATA_in[121] = (MAXIGP0RDATA[121] !== 1'bz) && MAXIGP0RDATA[121]; // rv 0 + assign MAXIGP0RDATA_in[122] = (MAXIGP0RDATA[122] !== 1'bz) && MAXIGP0RDATA[122]; // rv 0 + assign MAXIGP0RDATA_in[123] = (MAXIGP0RDATA[123] !== 1'bz) && MAXIGP0RDATA[123]; // rv 0 + assign MAXIGP0RDATA_in[124] = (MAXIGP0RDATA[124] !== 1'bz) && MAXIGP0RDATA[124]; // rv 0 + assign MAXIGP0RDATA_in[125] = (MAXIGP0RDATA[125] !== 1'bz) && MAXIGP0RDATA[125]; // rv 0 + assign MAXIGP0RDATA_in[126] = (MAXIGP0RDATA[126] !== 1'bz) && MAXIGP0RDATA[126]; // rv 0 + assign MAXIGP0RDATA_in[127] = (MAXIGP0RDATA[127] !== 1'bz) && MAXIGP0RDATA[127]; // rv 0 + assign MAXIGP0RDATA_in[12] = (MAXIGP0RDATA[12] !== 1'bz) && MAXIGP0RDATA[12]; // rv 0 + assign MAXIGP0RDATA_in[13] = (MAXIGP0RDATA[13] !== 1'bz) && MAXIGP0RDATA[13]; // rv 0 + assign MAXIGP0RDATA_in[14] = (MAXIGP0RDATA[14] !== 1'bz) && MAXIGP0RDATA[14]; // rv 0 + assign MAXIGP0RDATA_in[15] = (MAXIGP0RDATA[15] !== 1'bz) && MAXIGP0RDATA[15]; // rv 0 + assign MAXIGP0RDATA_in[16] = (MAXIGP0RDATA[16] !== 1'bz) && MAXIGP0RDATA[16]; // rv 0 + assign MAXIGP0RDATA_in[17] = (MAXIGP0RDATA[17] !== 1'bz) && MAXIGP0RDATA[17]; // rv 0 + assign MAXIGP0RDATA_in[18] = (MAXIGP0RDATA[18] !== 1'bz) && MAXIGP0RDATA[18]; // rv 0 + assign MAXIGP0RDATA_in[19] = (MAXIGP0RDATA[19] !== 1'bz) && MAXIGP0RDATA[19]; // rv 0 + assign MAXIGP0RDATA_in[1] = (MAXIGP0RDATA[1] !== 1'bz) && MAXIGP0RDATA[1]; // rv 0 + assign MAXIGP0RDATA_in[20] = (MAXIGP0RDATA[20] !== 1'bz) && MAXIGP0RDATA[20]; // rv 0 + assign MAXIGP0RDATA_in[21] = (MAXIGP0RDATA[21] !== 1'bz) && MAXIGP0RDATA[21]; // rv 0 + assign MAXIGP0RDATA_in[22] = (MAXIGP0RDATA[22] !== 1'bz) && MAXIGP0RDATA[22]; // rv 0 + assign MAXIGP0RDATA_in[23] = (MAXIGP0RDATA[23] !== 1'bz) && MAXIGP0RDATA[23]; // rv 0 + assign MAXIGP0RDATA_in[24] = (MAXIGP0RDATA[24] !== 1'bz) && MAXIGP0RDATA[24]; // rv 0 + assign MAXIGP0RDATA_in[25] = (MAXIGP0RDATA[25] !== 1'bz) && MAXIGP0RDATA[25]; // rv 0 + assign MAXIGP0RDATA_in[26] = (MAXIGP0RDATA[26] !== 1'bz) && MAXIGP0RDATA[26]; // rv 0 + assign MAXIGP0RDATA_in[27] = (MAXIGP0RDATA[27] !== 1'bz) && MAXIGP0RDATA[27]; // rv 0 + assign MAXIGP0RDATA_in[28] = (MAXIGP0RDATA[28] !== 1'bz) && MAXIGP0RDATA[28]; // rv 0 + assign MAXIGP0RDATA_in[29] = (MAXIGP0RDATA[29] !== 1'bz) && MAXIGP0RDATA[29]; // rv 0 + assign MAXIGP0RDATA_in[2] = (MAXIGP0RDATA[2] !== 1'bz) && MAXIGP0RDATA[2]; // rv 0 + assign MAXIGP0RDATA_in[30] = (MAXIGP0RDATA[30] !== 1'bz) && MAXIGP0RDATA[30]; // rv 0 + assign MAXIGP0RDATA_in[31] = (MAXIGP0RDATA[31] !== 1'bz) && MAXIGP0RDATA[31]; // rv 0 + assign MAXIGP0RDATA_in[32] = (MAXIGP0RDATA[32] !== 1'bz) && MAXIGP0RDATA[32]; // rv 0 + assign MAXIGP0RDATA_in[33] = (MAXIGP0RDATA[33] !== 1'bz) && MAXIGP0RDATA[33]; // rv 0 + assign MAXIGP0RDATA_in[34] = (MAXIGP0RDATA[34] !== 1'bz) && MAXIGP0RDATA[34]; // rv 0 + assign MAXIGP0RDATA_in[35] = (MAXIGP0RDATA[35] !== 1'bz) && MAXIGP0RDATA[35]; // rv 0 + assign MAXIGP0RDATA_in[36] = (MAXIGP0RDATA[36] !== 1'bz) && MAXIGP0RDATA[36]; // rv 0 + assign MAXIGP0RDATA_in[37] = (MAXIGP0RDATA[37] !== 1'bz) && MAXIGP0RDATA[37]; // rv 0 + assign MAXIGP0RDATA_in[38] = (MAXIGP0RDATA[38] !== 1'bz) && MAXIGP0RDATA[38]; // rv 0 + assign MAXIGP0RDATA_in[39] = (MAXIGP0RDATA[39] !== 1'bz) && MAXIGP0RDATA[39]; // rv 0 + assign MAXIGP0RDATA_in[3] = (MAXIGP0RDATA[3] !== 1'bz) && MAXIGP0RDATA[3]; // rv 0 + assign MAXIGP0RDATA_in[40] = (MAXIGP0RDATA[40] !== 1'bz) && MAXIGP0RDATA[40]; // rv 0 + assign MAXIGP0RDATA_in[41] = (MAXIGP0RDATA[41] !== 1'bz) && MAXIGP0RDATA[41]; // rv 0 + assign MAXIGP0RDATA_in[42] = (MAXIGP0RDATA[42] !== 1'bz) && MAXIGP0RDATA[42]; // rv 0 + assign MAXIGP0RDATA_in[43] = (MAXIGP0RDATA[43] !== 1'bz) && MAXIGP0RDATA[43]; // rv 0 + assign MAXIGP0RDATA_in[44] = (MAXIGP0RDATA[44] !== 1'bz) && MAXIGP0RDATA[44]; // rv 0 + assign MAXIGP0RDATA_in[45] = (MAXIGP0RDATA[45] !== 1'bz) && MAXIGP0RDATA[45]; // rv 0 + assign MAXIGP0RDATA_in[46] = (MAXIGP0RDATA[46] !== 1'bz) && MAXIGP0RDATA[46]; // rv 0 + assign MAXIGP0RDATA_in[47] = (MAXIGP0RDATA[47] !== 1'bz) && MAXIGP0RDATA[47]; // rv 0 + assign MAXIGP0RDATA_in[48] = (MAXIGP0RDATA[48] !== 1'bz) && MAXIGP0RDATA[48]; // rv 0 + assign MAXIGP0RDATA_in[49] = (MAXIGP0RDATA[49] !== 1'bz) && MAXIGP0RDATA[49]; // rv 0 + assign MAXIGP0RDATA_in[4] = (MAXIGP0RDATA[4] !== 1'bz) && MAXIGP0RDATA[4]; // rv 0 + assign MAXIGP0RDATA_in[50] = (MAXIGP0RDATA[50] !== 1'bz) && MAXIGP0RDATA[50]; // rv 0 + assign MAXIGP0RDATA_in[51] = (MAXIGP0RDATA[51] !== 1'bz) && MAXIGP0RDATA[51]; // rv 0 + assign MAXIGP0RDATA_in[52] = (MAXIGP0RDATA[52] !== 1'bz) && MAXIGP0RDATA[52]; // rv 0 + assign MAXIGP0RDATA_in[53] = (MAXIGP0RDATA[53] !== 1'bz) && MAXIGP0RDATA[53]; // rv 0 + assign MAXIGP0RDATA_in[54] = (MAXIGP0RDATA[54] !== 1'bz) && MAXIGP0RDATA[54]; // rv 0 + assign MAXIGP0RDATA_in[55] = (MAXIGP0RDATA[55] !== 1'bz) && MAXIGP0RDATA[55]; // rv 0 + assign MAXIGP0RDATA_in[56] = (MAXIGP0RDATA[56] !== 1'bz) && MAXIGP0RDATA[56]; // rv 0 + assign MAXIGP0RDATA_in[57] = (MAXIGP0RDATA[57] !== 1'bz) && MAXIGP0RDATA[57]; // rv 0 + assign MAXIGP0RDATA_in[58] = (MAXIGP0RDATA[58] !== 1'bz) && MAXIGP0RDATA[58]; // rv 0 + assign MAXIGP0RDATA_in[59] = (MAXIGP0RDATA[59] !== 1'bz) && MAXIGP0RDATA[59]; // rv 0 + assign MAXIGP0RDATA_in[5] = (MAXIGP0RDATA[5] !== 1'bz) && MAXIGP0RDATA[5]; // rv 0 + assign MAXIGP0RDATA_in[60] = (MAXIGP0RDATA[60] !== 1'bz) && MAXIGP0RDATA[60]; // rv 0 + assign MAXIGP0RDATA_in[61] = (MAXIGP0RDATA[61] !== 1'bz) && MAXIGP0RDATA[61]; // rv 0 + assign MAXIGP0RDATA_in[62] = (MAXIGP0RDATA[62] !== 1'bz) && MAXIGP0RDATA[62]; // rv 0 + assign MAXIGP0RDATA_in[63] = (MAXIGP0RDATA[63] !== 1'bz) && MAXIGP0RDATA[63]; // rv 0 + assign MAXIGP0RDATA_in[64] = (MAXIGP0RDATA[64] !== 1'bz) && MAXIGP0RDATA[64]; // rv 0 + assign MAXIGP0RDATA_in[65] = (MAXIGP0RDATA[65] !== 1'bz) && MAXIGP0RDATA[65]; // rv 0 + assign MAXIGP0RDATA_in[66] = (MAXIGP0RDATA[66] !== 1'bz) && MAXIGP0RDATA[66]; // rv 0 + assign MAXIGP0RDATA_in[67] = (MAXIGP0RDATA[67] !== 1'bz) && MAXIGP0RDATA[67]; // rv 0 + assign MAXIGP0RDATA_in[68] = (MAXIGP0RDATA[68] !== 1'bz) && MAXIGP0RDATA[68]; // rv 0 + assign MAXIGP0RDATA_in[69] = (MAXIGP0RDATA[69] !== 1'bz) && MAXIGP0RDATA[69]; // rv 0 + assign MAXIGP0RDATA_in[6] = (MAXIGP0RDATA[6] !== 1'bz) && MAXIGP0RDATA[6]; // rv 0 + assign MAXIGP0RDATA_in[70] = (MAXIGP0RDATA[70] !== 1'bz) && MAXIGP0RDATA[70]; // rv 0 + assign MAXIGP0RDATA_in[71] = (MAXIGP0RDATA[71] !== 1'bz) && MAXIGP0RDATA[71]; // rv 0 + assign MAXIGP0RDATA_in[72] = (MAXIGP0RDATA[72] !== 1'bz) && MAXIGP0RDATA[72]; // rv 0 + assign MAXIGP0RDATA_in[73] = (MAXIGP0RDATA[73] !== 1'bz) && MAXIGP0RDATA[73]; // rv 0 + assign MAXIGP0RDATA_in[74] = (MAXIGP0RDATA[74] !== 1'bz) && MAXIGP0RDATA[74]; // rv 0 + assign MAXIGP0RDATA_in[75] = (MAXIGP0RDATA[75] !== 1'bz) && MAXIGP0RDATA[75]; // rv 0 + assign MAXIGP0RDATA_in[76] = (MAXIGP0RDATA[76] !== 1'bz) && MAXIGP0RDATA[76]; // rv 0 + assign MAXIGP0RDATA_in[77] = (MAXIGP0RDATA[77] !== 1'bz) && MAXIGP0RDATA[77]; // rv 0 + assign MAXIGP0RDATA_in[78] = (MAXIGP0RDATA[78] !== 1'bz) && MAXIGP0RDATA[78]; // rv 0 + assign MAXIGP0RDATA_in[79] = (MAXIGP0RDATA[79] !== 1'bz) && MAXIGP0RDATA[79]; // rv 0 + assign MAXIGP0RDATA_in[7] = (MAXIGP0RDATA[7] !== 1'bz) && MAXIGP0RDATA[7]; // rv 0 + assign MAXIGP0RDATA_in[80] = (MAXIGP0RDATA[80] !== 1'bz) && MAXIGP0RDATA[80]; // rv 0 + assign MAXIGP0RDATA_in[81] = (MAXIGP0RDATA[81] !== 1'bz) && MAXIGP0RDATA[81]; // rv 0 + assign MAXIGP0RDATA_in[82] = (MAXIGP0RDATA[82] !== 1'bz) && MAXIGP0RDATA[82]; // rv 0 + assign MAXIGP0RDATA_in[83] = (MAXIGP0RDATA[83] !== 1'bz) && MAXIGP0RDATA[83]; // rv 0 + assign MAXIGP0RDATA_in[84] = (MAXIGP0RDATA[84] !== 1'bz) && MAXIGP0RDATA[84]; // rv 0 + assign MAXIGP0RDATA_in[85] = (MAXIGP0RDATA[85] !== 1'bz) && MAXIGP0RDATA[85]; // rv 0 + assign MAXIGP0RDATA_in[86] = (MAXIGP0RDATA[86] !== 1'bz) && MAXIGP0RDATA[86]; // rv 0 + assign MAXIGP0RDATA_in[87] = (MAXIGP0RDATA[87] !== 1'bz) && MAXIGP0RDATA[87]; // rv 0 + assign MAXIGP0RDATA_in[88] = (MAXIGP0RDATA[88] !== 1'bz) && MAXIGP0RDATA[88]; // rv 0 + assign MAXIGP0RDATA_in[89] = (MAXIGP0RDATA[89] !== 1'bz) && MAXIGP0RDATA[89]; // rv 0 + assign MAXIGP0RDATA_in[8] = (MAXIGP0RDATA[8] !== 1'bz) && MAXIGP0RDATA[8]; // rv 0 + assign MAXIGP0RDATA_in[90] = (MAXIGP0RDATA[90] !== 1'bz) && MAXIGP0RDATA[90]; // rv 0 + assign MAXIGP0RDATA_in[91] = (MAXIGP0RDATA[91] !== 1'bz) && MAXIGP0RDATA[91]; // rv 0 + assign MAXIGP0RDATA_in[92] = (MAXIGP0RDATA[92] !== 1'bz) && MAXIGP0RDATA[92]; // rv 0 + assign MAXIGP0RDATA_in[93] = (MAXIGP0RDATA[93] !== 1'bz) && MAXIGP0RDATA[93]; // rv 0 + assign MAXIGP0RDATA_in[94] = (MAXIGP0RDATA[94] !== 1'bz) && MAXIGP0RDATA[94]; // rv 0 + assign MAXIGP0RDATA_in[95] = (MAXIGP0RDATA[95] !== 1'bz) && MAXIGP0RDATA[95]; // rv 0 + assign MAXIGP0RDATA_in[96] = (MAXIGP0RDATA[96] !== 1'bz) && MAXIGP0RDATA[96]; // rv 0 + assign MAXIGP0RDATA_in[97] = (MAXIGP0RDATA[97] !== 1'bz) && MAXIGP0RDATA[97]; // rv 0 + assign MAXIGP0RDATA_in[98] = (MAXIGP0RDATA[98] !== 1'bz) && MAXIGP0RDATA[98]; // rv 0 + assign MAXIGP0RDATA_in[99] = (MAXIGP0RDATA[99] !== 1'bz) && MAXIGP0RDATA[99]; // rv 0 + assign MAXIGP0RDATA_in[9] = (MAXIGP0RDATA[9] !== 1'bz) && MAXIGP0RDATA[9]; // rv 0 + assign MAXIGP0RID_in[0] = (MAXIGP0RID[0] !== 1'bz) && MAXIGP0RID[0]; // rv 0 + assign MAXIGP0RID_in[10] = (MAXIGP0RID[10] !== 1'bz) && MAXIGP0RID[10]; // rv 0 + assign MAXIGP0RID_in[11] = (MAXIGP0RID[11] !== 1'bz) && MAXIGP0RID[11]; // rv 0 + assign MAXIGP0RID_in[12] = (MAXIGP0RID[12] !== 1'bz) && MAXIGP0RID[12]; // rv 0 + assign MAXIGP0RID_in[13] = (MAXIGP0RID[13] !== 1'bz) && MAXIGP0RID[13]; // rv 0 + assign MAXIGP0RID_in[14] = (MAXIGP0RID[14] !== 1'bz) && MAXIGP0RID[14]; // rv 0 + assign MAXIGP0RID_in[15] = (MAXIGP0RID[15] !== 1'bz) && MAXIGP0RID[15]; // rv 0 + assign MAXIGP0RID_in[1] = (MAXIGP0RID[1] !== 1'bz) && MAXIGP0RID[1]; // rv 0 + assign MAXIGP0RID_in[2] = (MAXIGP0RID[2] !== 1'bz) && MAXIGP0RID[2]; // rv 0 + assign MAXIGP0RID_in[3] = (MAXIGP0RID[3] !== 1'bz) && MAXIGP0RID[3]; // rv 0 + assign MAXIGP0RID_in[4] = (MAXIGP0RID[4] !== 1'bz) && MAXIGP0RID[4]; // rv 0 + assign MAXIGP0RID_in[5] = (MAXIGP0RID[5] !== 1'bz) && MAXIGP0RID[5]; // rv 0 + assign MAXIGP0RID_in[6] = (MAXIGP0RID[6] !== 1'bz) && MAXIGP0RID[6]; // rv 0 + assign MAXIGP0RID_in[7] = (MAXIGP0RID[7] !== 1'bz) && MAXIGP0RID[7]; // rv 0 + assign MAXIGP0RID_in[8] = (MAXIGP0RID[8] !== 1'bz) && MAXIGP0RID[8]; // rv 0 + assign MAXIGP0RID_in[9] = (MAXIGP0RID[9] !== 1'bz) && MAXIGP0RID[9]; // rv 0 + assign MAXIGP0RLAST_in = (MAXIGP0RLAST !== 1'bz) && MAXIGP0RLAST; // rv 0 + assign MAXIGP0RRESP_in[0] = (MAXIGP0RRESP[0] !== 1'bz) && MAXIGP0RRESP[0]; // rv 0 + assign MAXIGP0RRESP_in[1] = (MAXIGP0RRESP[1] !== 1'bz) && MAXIGP0RRESP[1]; // rv 0 + assign MAXIGP0RVALID_in = (MAXIGP0RVALID !== 1'bz) && MAXIGP0RVALID; // rv 0 + assign MAXIGP0WREADY_in = (MAXIGP0WREADY !== 1'bz) && MAXIGP0WREADY; // rv 0 + assign MAXIGP1ACLK_in = (MAXIGP1ACLK !== 1'bz) && MAXIGP1ACLK; // rv 0 + assign MAXIGP1ARREADY_in = (MAXIGP1ARREADY !== 1'bz) && MAXIGP1ARREADY; // rv 0 + assign MAXIGP1AWREADY_in = (MAXIGP1AWREADY !== 1'bz) && MAXIGP1AWREADY; // rv 0 + assign MAXIGP1BID_in[0] = (MAXIGP1BID[0] !== 1'bz) && MAXIGP1BID[0]; // rv 0 + assign MAXIGP1BID_in[10] = (MAXIGP1BID[10] !== 1'bz) && MAXIGP1BID[10]; // rv 0 + assign MAXIGP1BID_in[11] = (MAXIGP1BID[11] !== 1'bz) && MAXIGP1BID[11]; // rv 0 + assign MAXIGP1BID_in[12] = (MAXIGP1BID[12] !== 1'bz) && MAXIGP1BID[12]; // rv 0 + assign MAXIGP1BID_in[13] = (MAXIGP1BID[13] !== 1'bz) && MAXIGP1BID[13]; // rv 0 + assign MAXIGP1BID_in[14] = (MAXIGP1BID[14] !== 1'bz) && MAXIGP1BID[14]; // rv 0 + assign MAXIGP1BID_in[15] = (MAXIGP1BID[15] !== 1'bz) && MAXIGP1BID[15]; // rv 0 + assign MAXIGP1BID_in[1] = (MAXIGP1BID[1] !== 1'bz) && MAXIGP1BID[1]; // rv 0 + assign MAXIGP1BID_in[2] = (MAXIGP1BID[2] !== 1'bz) && MAXIGP1BID[2]; // rv 0 + assign MAXIGP1BID_in[3] = (MAXIGP1BID[3] !== 1'bz) && MAXIGP1BID[3]; // rv 0 + assign MAXIGP1BID_in[4] = (MAXIGP1BID[4] !== 1'bz) && MAXIGP1BID[4]; // rv 0 + assign MAXIGP1BID_in[5] = (MAXIGP1BID[5] !== 1'bz) && MAXIGP1BID[5]; // rv 0 + assign MAXIGP1BID_in[6] = (MAXIGP1BID[6] !== 1'bz) && MAXIGP1BID[6]; // rv 0 + assign MAXIGP1BID_in[7] = (MAXIGP1BID[7] !== 1'bz) && MAXIGP1BID[7]; // rv 0 + assign MAXIGP1BID_in[8] = (MAXIGP1BID[8] !== 1'bz) && MAXIGP1BID[8]; // rv 0 + assign MAXIGP1BID_in[9] = (MAXIGP1BID[9] !== 1'bz) && MAXIGP1BID[9]; // rv 0 + assign MAXIGP1BRESP_in[0] = (MAXIGP1BRESP[0] !== 1'bz) && MAXIGP1BRESP[0]; // rv 0 + assign MAXIGP1BRESP_in[1] = (MAXIGP1BRESP[1] !== 1'bz) && MAXIGP1BRESP[1]; // rv 0 + assign MAXIGP1BVALID_in = (MAXIGP1BVALID !== 1'bz) && MAXIGP1BVALID; // rv 0 + assign MAXIGP1RDATA_in[0] = (MAXIGP1RDATA[0] !== 1'bz) && MAXIGP1RDATA[0]; // rv 0 + assign MAXIGP1RDATA_in[100] = (MAXIGP1RDATA[100] !== 1'bz) && MAXIGP1RDATA[100]; // rv 0 + assign MAXIGP1RDATA_in[101] = (MAXIGP1RDATA[101] !== 1'bz) && MAXIGP1RDATA[101]; // rv 0 + assign MAXIGP1RDATA_in[102] = (MAXIGP1RDATA[102] !== 1'bz) && MAXIGP1RDATA[102]; // rv 0 + assign MAXIGP1RDATA_in[103] = (MAXIGP1RDATA[103] !== 1'bz) && MAXIGP1RDATA[103]; // rv 0 + assign MAXIGP1RDATA_in[104] = (MAXIGP1RDATA[104] !== 1'bz) && MAXIGP1RDATA[104]; // rv 0 + assign MAXIGP1RDATA_in[105] = (MAXIGP1RDATA[105] !== 1'bz) && MAXIGP1RDATA[105]; // rv 0 + assign MAXIGP1RDATA_in[106] = (MAXIGP1RDATA[106] !== 1'bz) && MAXIGP1RDATA[106]; // rv 0 + assign MAXIGP1RDATA_in[107] = (MAXIGP1RDATA[107] !== 1'bz) && MAXIGP1RDATA[107]; // rv 0 + assign MAXIGP1RDATA_in[108] = (MAXIGP1RDATA[108] !== 1'bz) && MAXIGP1RDATA[108]; // rv 0 + assign MAXIGP1RDATA_in[109] = (MAXIGP1RDATA[109] !== 1'bz) && MAXIGP1RDATA[109]; // rv 0 + assign MAXIGP1RDATA_in[10] = (MAXIGP1RDATA[10] !== 1'bz) && MAXIGP1RDATA[10]; // rv 0 + assign MAXIGP1RDATA_in[110] = (MAXIGP1RDATA[110] !== 1'bz) && MAXIGP1RDATA[110]; // rv 0 + assign MAXIGP1RDATA_in[111] = (MAXIGP1RDATA[111] !== 1'bz) && MAXIGP1RDATA[111]; // rv 0 + assign MAXIGP1RDATA_in[112] = (MAXIGP1RDATA[112] !== 1'bz) && MAXIGP1RDATA[112]; // rv 0 + assign MAXIGP1RDATA_in[113] = (MAXIGP1RDATA[113] !== 1'bz) && MAXIGP1RDATA[113]; // rv 0 + assign MAXIGP1RDATA_in[114] = (MAXIGP1RDATA[114] !== 1'bz) && MAXIGP1RDATA[114]; // rv 0 + assign MAXIGP1RDATA_in[115] = (MAXIGP1RDATA[115] !== 1'bz) && MAXIGP1RDATA[115]; // rv 0 + assign MAXIGP1RDATA_in[116] = (MAXIGP1RDATA[116] !== 1'bz) && MAXIGP1RDATA[116]; // rv 0 + assign MAXIGP1RDATA_in[117] = (MAXIGP1RDATA[117] !== 1'bz) && MAXIGP1RDATA[117]; // rv 0 + assign MAXIGP1RDATA_in[118] = (MAXIGP1RDATA[118] !== 1'bz) && MAXIGP1RDATA[118]; // rv 0 + assign MAXIGP1RDATA_in[119] = (MAXIGP1RDATA[119] !== 1'bz) && MAXIGP1RDATA[119]; // rv 0 + assign MAXIGP1RDATA_in[11] = (MAXIGP1RDATA[11] !== 1'bz) && MAXIGP1RDATA[11]; // rv 0 + assign MAXIGP1RDATA_in[120] = (MAXIGP1RDATA[120] !== 1'bz) && MAXIGP1RDATA[120]; // rv 0 + assign MAXIGP1RDATA_in[121] = (MAXIGP1RDATA[121] !== 1'bz) && MAXIGP1RDATA[121]; // rv 0 + assign MAXIGP1RDATA_in[122] = (MAXIGP1RDATA[122] !== 1'bz) && MAXIGP1RDATA[122]; // rv 0 + assign MAXIGP1RDATA_in[123] = (MAXIGP1RDATA[123] !== 1'bz) && MAXIGP1RDATA[123]; // rv 0 + assign MAXIGP1RDATA_in[124] = (MAXIGP1RDATA[124] !== 1'bz) && MAXIGP1RDATA[124]; // rv 0 + assign MAXIGP1RDATA_in[125] = (MAXIGP1RDATA[125] !== 1'bz) && MAXIGP1RDATA[125]; // rv 0 + assign MAXIGP1RDATA_in[126] = (MAXIGP1RDATA[126] !== 1'bz) && MAXIGP1RDATA[126]; // rv 0 + assign MAXIGP1RDATA_in[127] = (MAXIGP1RDATA[127] !== 1'bz) && MAXIGP1RDATA[127]; // rv 0 + assign MAXIGP1RDATA_in[12] = (MAXIGP1RDATA[12] !== 1'bz) && MAXIGP1RDATA[12]; // rv 0 + assign MAXIGP1RDATA_in[13] = (MAXIGP1RDATA[13] !== 1'bz) && MAXIGP1RDATA[13]; // rv 0 + assign MAXIGP1RDATA_in[14] = (MAXIGP1RDATA[14] !== 1'bz) && MAXIGP1RDATA[14]; // rv 0 + assign MAXIGP1RDATA_in[15] = (MAXIGP1RDATA[15] !== 1'bz) && MAXIGP1RDATA[15]; // rv 0 + assign MAXIGP1RDATA_in[16] = (MAXIGP1RDATA[16] !== 1'bz) && MAXIGP1RDATA[16]; // rv 0 + assign MAXIGP1RDATA_in[17] = (MAXIGP1RDATA[17] !== 1'bz) && MAXIGP1RDATA[17]; // rv 0 + assign MAXIGP1RDATA_in[18] = (MAXIGP1RDATA[18] !== 1'bz) && MAXIGP1RDATA[18]; // rv 0 + assign MAXIGP1RDATA_in[19] = (MAXIGP1RDATA[19] !== 1'bz) && MAXIGP1RDATA[19]; // rv 0 + assign MAXIGP1RDATA_in[1] = (MAXIGP1RDATA[1] !== 1'bz) && MAXIGP1RDATA[1]; // rv 0 + assign MAXIGP1RDATA_in[20] = (MAXIGP1RDATA[20] !== 1'bz) && MAXIGP1RDATA[20]; // rv 0 + assign MAXIGP1RDATA_in[21] = (MAXIGP1RDATA[21] !== 1'bz) && MAXIGP1RDATA[21]; // rv 0 + assign MAXIGP1RDATA_in[22] = (MAXIGP1RDATA[22] !== 1'bz) && MAXIGP1RDATA[22]; // rv 0 + assign MAXIGP1RDATA_in[23] = (MAXIGP1RDATA[23] !== 1'bz) && MAXIGP1RDATA[23]; // rv 0 + assign MAXIGP1RDATA_in[24] = (MAXIGP1RDATA[24] !== 1'bz) && MAXIGP1RDATA[24]; // rv 0 + assign MAXIGP1RDATA_in[25] = (MAXIGP1RDATA[25] !== 1'bz) && MAXIGP1RDATA[25]; // rv 0 + assign MAXIGP1RDATA_in[26] = (MAXIGP1RDATA[26] !== 1'bz) && MAXIGP1RDATA[26]; // rv 0 + assign MAXIGP1RDATA_in[27] = (MAXIGP1RDATA[27] !== 1'bz) && MAXIGP1RDATA[27]; // rv 0 + assign MAXIGP1RDATA_in[28] = (MAXIGP1RDATA[28] !== 1'bz) && MAXIGP1RDATA[28]; // rv 0 + assign MAXIGP1RDATA_in[29] = (MAXIGP1RDATA[29] !== 1'bz) && MAXIGP1RDATA[29]; // rv 0 + assign MAXIGP1RDATA_in[2] = (MAXIGP1RDATA[2] !== 1'bz) && MAXIGP1RDATA[2]; // rv 0 + assign MAXIGP1RDATA_in[30] = (MAXIGP1RDATA[30] !== 1'bz) && MAXIGP1RDATA[30]; // rv 0 + assign MAXIGP1RDATA_in[31] = (MAXIGP1RDATA[31] !== 1'bz) && MAXIGP1RDATA[31]; // rv 0 + assign MAXIGP1RDATA_in[32] = (MAXIGP1RDATA[32] !== 1'bz) && MAXIGP1RDATA[32]; // rv 0 + assign MAXIGP1RDATA_in[33] = (MAXIGP1RDATA[33] !== 1'bz) && MAXIGP1RDATA[33]; // rv 0 + assign MAXIGP1RDATA_in[34] = (MAXIGP1RDATA[34] !== 1'bz) && MAXIGP1RDATA[34]; // rv 0 + assign MAXIGP1RDATA_in[35] = (MAXIGP1RDATA[35] !== 1'bz) && MAXIGP1RDATA[35]; // rv 0 + assign MAXIGP1RDATA_in[36] = (MAXIGP1RDATA[36] !== 1'bz) && MAXIGP1RDATA[36]; // rv 0 + assign MAXIGP1RDATA_in[37] = (MAXIGP1RDATA[37] !== 1'bz) && MAXIGP1RDATA[37]; // rv 0 + assign MAXIGP1RDATA_in[38] = (MAXIGP1RDATA[38] !== 1'bz) && MAXIGP1RDATA[38]; // rv 0 + assign MAXIGP1RDATA_in[39] = (MAXIGP1RDATA[39] !== 1'bz) && MAXIGP1RDATA[39]; // rv 0 + assign MAXIGP1RDATA_in[3] = (MAXIGP1RDATA[3] !== 1'bz) && MAXIGP1RDATA[3]; // rv 0 + assign MAXIGP1RDATA_in[40] = (MAXIGP1RDATA[40] !== 1'bz) && MAXIGP1RDATA[40]; // rv 0 + assign MAXIGP1RDATA_in[41] = (MAXIGP1RDATA[41] !== 1'bz) && MAXIGP1RDATA[41]; // rv 0 + assign MAXIGP1RDATA_in[42] = (MAXIGP1RDATA[42] !== 1'bz) && MAXIGP1RDATA[42]; // rv 0 + assign MAXIGP1RDATA_in[43] = (MAXIGP1RDATA[43] !== 1'bz) && MAXIGP1RDATA[43]; // rv 0 + assign MAXIGP1RDATA_in[44] = (MAXIGP1RDATA[44] !== 1'bz) && MAXIGP1RDATA[44]; // rv 0 + assign MAXIGP1RDATA_in[45] = (MAXIGP1RDATA[45] !== 1'bz) && MAXIGP1RDATA[45]; // rv 0 + assign MAXIGP1RDATA_in[46] = (MAXIGP1RDATA[46] !== 1'bz) && MAXIGP1RDATA[46]; // rv 0 + assign MAXIGP1RDATA_in[47] = (MAXIGP1RDATA[47] !== 1'bz) && MAXIGP1RDATA[47]; // rv 0 + assign MAXIGP1RDATA_in[48] = (MAXIGP1RDATA[48] !== 1'bz) && MAXIGP1RDATA[48]; // rv 0 + assign MAXIGP1RDATA_in[49] = (MAXIGP1RDATA[49] !== 1'bz) && MAXIGP1RDATA[49]; // rv 0 + assign MAXIGP1RDATA_in[4] = (MAXIGP1RDATA[4] !== 1'bz) && MAXIGP1RDATA[4]; // rv 0 + assign MAXIGP1RDATA_in[50] = (MAXIGP1RDATA[50] !== 1'bz) && MAXIGP1RDATA[50]; // rv 0 + assign MAXIGP1RDATA_in[51] = (MAXIGP1RDATA[51] !== 1'bz) && MAXIGP1RDATA[51]; // rv 0 + assign MAXIGP1RDATA_in[52] = (MAXIGP1RDATA[52] !== 1'bz) && MAXIGP1RDATA[52]; // rv 0 + assign MAXIGP1RDATA_in[53] = (MAXIGP1RDATA[53] !== 1'bz) && MAXIGP1RDATA[53]; // rv 0 + assign MAXIGP1RDATA_in[54] = (MAXIGP1RDATA[54] !== 1'bz) && MAXIGP1RDATA[54]; // rv 0 + assign MAXIGP1RDATA_in[55] = (MAXIGP1RDATA[55] !== 1'bz) && MAXIGP1RDATA[55]; // rv 0 + assign MAXIGP1RDATA_in[56] = (MAXIGP1RDATA[56] !== 1'bz) && MAXIGP1RDATA[56]; // rv 0 + assign MAXIGP1RDATA_in[57] = (MAXIGP1RDATA[57] !== 1'bz) && MAXIGP1RDATA[57]; // rv 0 + assign MAXIGP1RDATA_in[58] = (MAXIGP1RDATA[58] !== 1'bz) && MAXIGP1RDATA[58]; // rv 0 + assign MAXIGP1RDATA_in[59] = (MAXIGP1RDATA[59] !== 1'bz) && MAXIGP1RDATA[59]; // rv 0 + assign MAXIGP1RDATA_in[5] = (MAXIGP1RDATA[5] !== 1'bz) && MAXIGP1RDATA[5]; // rv 0 + assign MAXIGP1RDATA_in[60] = (MAXIGP1RDATA[60] !== 1'bz) && MAXIGP1RDATA[60]; // rv 0 + assign MAXIGP1RDATA_in[61] = (MAXIGP1RDATA[61] !== 1'bz) && MAXIGP1RDATA[61]; // rv 0 + assign MAXIGP1RDATA_in[62] = (MAXIGP1RDATA[62] !== 1'bz) && MAXIGP1RDATA[62]; // rv 0 + assign MAXIGP1RDATA_in[63] = (MAXIGP1RDATA[63] !== 1'bz) && MAXIGP1RDATA[63]; // rv 0 + assign MAXIGP1RDATA_in[64] = (MAXIGP1RDATA[64] !== 1'bz) && MAXIGP1RDATA[64]; // rv 0 + assign MAXIGP1RDATA_in[65] = (MAXIGP1RDATA[65] !== 1'bz) && MAXIGP1RDATA[65]; // rv 0 + assign MAXIGP1RDATA_in[66] = (MAXIGP1RDATA[66] !== 1'bz) && MAXIGP1RDATA[66]; // rv 0 + assign MAXIGP1RDATA_in[67] = (MAXIGP1RDATA[67] !== 1'bz) && MAXIGP1RDATA[67]; // rv 0 + assign MAXIGP1RDATA_in[68] = (MAXIGP1RDATA[68] !== 1'bz) && MAXIGP1RDATA[68]; // rv 0 + assign MAXIGP1RDATA_in[69] = (MAXIGP1RDATA[69] !== 1'bz) && MAXIGP1RDATA[69]; // rv 0 + assign MAXIGP1RDATA_in[6] = (MAXIGP1RDATA[6] !== 1'bz) && MAXIGP1RDATA[6]; // rv 0 + assign MAXIGP1RDATA_in[70] = (MAXIGP1RDATA[70] !== 1'bz) && MAXIGP1RDATA[70]; // rv 0 + assign MAXIGP1RDATA_in[71] = (MAXIGP1RDATA[71] !== 1'bz) && MAXIGP1RDATA[71]; // rv 0 + assign MAXIGP1RDATA_in[72] = (MAXIGP1RDATA[72] !== 1'bz) && MAXIGP1RDATA[72]; // rv 0 + assign MAXIGP1RDATA_in[73] = (MAXIGP1RDATA[73] !== 1'bz) && MAXIGP1RDATA[73]; // rv 0 + assign MAXIGP1RDATA_in[74] = (MAXIGP1RDATA[74] !== 1'bz) && MAXIGP1RDATA[74]; // rv 0 + assign MAXIGP1RDATA_in[75] = (MAXIGP1RDATA[75] !== 1'bz) && MAXIGP1RDATA[75]; // rv 0 + assign MAXIGP1RDATA_in[76] = (MAXIGP1RDATA[76] !== 1'bz) && MAXIGP1RDATA[76]; // rv 0 + assign MAXIGP1RDATA_in[77] = (MAXIGP1RDATA[77] !== 1'bz) && MAXIGP1RDATA[77]; // rv 0 + assign MAXIGP1RDATA_in[78] = (MAXIGP1RDATA[78] !== 1'bz) && MAXIGP1RDATA[78]; // rv 0 + assign MAXIGP1RDATA_in[79] = (MAXIGP1RDATA[79] !== 1'bz) && MAXIGP1RDATA[79]; // rv 0 + assign MAXIGP1RDATA_in[7] = (MAXIGP1RDATA[7] !== 1'bz) && MAXIGP1RDATA[7]; // rv 0 + assign MAXIGP1RDATA_in[80] = (MAXIGP1RDATA[80] !== 1'bz) && MAXIGP1RDATA[80]; // rv 0 + assign MAXIGP1RDATA_in[81] = (MAXIGP1RDATA[81] !== 1'bz) && MAXIGP1RDATA[81]; // rv 0 + assign MAXIGP1RDATA_in[82] = (MAXIGP1RDATA[82] !== 1'bz) && MAXIGP1RDATA[82]; // rv 0 + assign MAXIGP1RDATA_in[83] = (MAXIGP1RDATA[83] !== 1'bz) && MAXIGP1RDATA[83]; // rv 0 + assign MAXIGP1RDATA_in[84] = (MAXIGP1RDATA[84] !== 1'bz) && MAXIGP1RDATA[84]; // rv 0 + assign MAXIGP1RDATA_in[85] = (MAXIGP1RDATA[85] !== 1'bz) && MAXIGP1RDATA[85]; // rv 0 + assign MAXIGP1RDATA_in[86] = (MAXIGP1RDATA[86] !== 1'bz) && MAXIGP1RDATA[86]; // rv 0 + assign MAXIGP1RDATA_in[87] = (MAXIGP1RDATA[87] !== 1'bz) && MAXIGP1RDATA[87]; // rv 0 + assign MAXIGP1RDATA_in[88] = (MAXIGP1RDATA[88] !== 1'bz) && MAXIGP1RDATA[88]; // rv 0 + assign MAXIGP1RDATA_in[89] = (MAXIGP1RDATA[89] !== 1'bz) && MAXIGP1RDATA[89]; // rv 0 + assign MAXIGP1RDATA_in[8] = (MAXIGP1RDATA[8] !== 1'bz) && MAXIGP1RDATA[8]; // rv 0 + assign MAXIGP1RDATA_in[90] = (MAXIGP1RDATA[90] !== 1'bz) && MAXIGP1RDATA[90]; // rv 0 + assign MAXIGP1RDATA_in[91] = (MAXIGP1RDATA[91] !== 1'bz) && MAXIGP1RDATA[91]; // rv 0 + assign MAXIGP1RDATA_in[92] = (MAXIGP1RDATA[92] !== 1'bz) && MAXIGP1RDATA[92]; // rv 0 + assign MAXIGP1RDATA_in[93] = (MAXIGP1RDATA[93] !== 1'bz) && MAXIGP1RDATA[93]; // rv 0 + assign MAXIGP1RDATA_in[94] = (MAXIGP1RDATA[94] !== 1'bz) && MAXIGP1RDATA[94]; // rv 0 + assign MAXIGP1RDATA_in[95] = (MAXIGP1RDATA[95] !== 1'bz) && MAXIGP1RDATA[95]; // rv 0 + assign MAXIGP1RDATA_in[96] = (MAXIGP1RDATA[96] !== 1'bz) && MAXIGP1RDATA[96]; // rv 0 + assign MAXIGP1RDATA_in[97] = (MAXIGP1RDATA[97] !== 1'bz) && MAXIGP1RDATA[97]; // rv 0 + assign MAXIGP1RDATA_in[98] = (MAXIGP1RDATA[98] !== 1'bz) && MAXIGP1RDATA[98]; // rv 0 + assign MAXIGP1RDATA_in[99] = (MAXIGP1RDATA[99] !== 1'bz) && MAXIGP1RDATA[99]; // rv 0 + assign MAXIGP1RDATA_in[9] = (MAXIGP1RDATA[9] !== 1'bz) && MAXIGP1RDATA[9]; // rv 0 + assign MAXIGP1RID_in[0] = (MAXIGP1RID[0] !== 1'bz) && MAXIGP1RID[0]; // rv 0 + assign MAXIGP1RID_in[10] = (MAXIGP1RID[10] !== 1'bz) && MAXIGP1RID[10]; // rv 0 + assign MAXIGP1RID_in[11] = (MAXIGP1RID[11] !== 1'bz) && MAXIGP1RID[11]; // rv 0 + assign MAXIGP1RID_in[12] = (MAXIGP1RID[12] !== 1'bz) && MAXIGP1RID[12]; // rv 0 + assign MAXIGP1RID_in[13] = (MAXIGP1RID[13] !== 1'bz) && MAXIGP1RID[13]; // rv 0 + assign MAXIGP1RID_in[14] = (MAXIGP1RID[14] !== 1'bz) && MAXIGP1RID[14]; // rv 0 + assign MAXIGP1RID_in[15] = (MAXIGP1RID[15] !== 1'bz) && MAXIGP1RID[15]; // rv 0 + assign MAXIGP1RID_in[1] = (MAXIGP1RID[1] !== 1'bz) && MAXIGP1RID[1]; // rv 0 + assign MAXIGP1RID_in[2] = (MAXIGP1RID[2] !== 1'bz) && MAXIGP1RID[2]; // rv 0 + assign MAXIGP1RID_in[3] = (MAXIGP1RID[3] !== 1'bz) && MAXIGP1RID[3]; // rv 0 + assign MAXIGP1RID_in[4] = (MAXIGP1RID[4] !== 1'bz) && MAXIGP1RID[4]; // rv 0 + assign MAXIGP1RID_in[5] = (MAXIGP1RID[5] !== 1'bz) && MAXIGP1RID[5]; // rv 0 + assign MAXIGP1RID_in[6] = (MAXIGP1RID[6] !== 1'bz) && MAXIGP1RID[6]; // rv 0 + assign MAXIGP1RID_in[7] = (MAXIGP1RID[7] !== 1'bz) && MAXIGP1RID[7]; // rv 0 + assign MAXIGP1RID_in[8] = (MAXIGP1RID[8] !== 1'bz) && MAXIGP1RID[8]; // rv 0 + assign MAXIGP1RID_in[9] = (MAXIGP1RID[9] !== 1'bz) && MAXIGP1RID[9]; // rv 0 + assign MAXIGP1RLAST_in = (MAXIGP1RLAST !== 1'bz) && MAXIGP1RLAST; // rv 0 + assign MAXIGP1RRESP_in[0] = (MAXIGP1RRESP[0] !== 1'bz) && MAXIGP1RRESP[0]; // rv 0 + assign MAXIGP1RRESP_in[1] = (MAXIGP1RRESP[1] !== 1'bz) && MAXIGP1RRESP[1]; // rv 0 + assign MAXIGP1RVALID_in = (MAXIGP1RVALID !== 1'bz) && MAXIGP1RVALID; // rv 0 + assign MAXIGP1WREADY_in = (MAXIGP1WREADY !== 1'bz) && MAXIGP1WREADY; // rv 0 + assign MAXIGP2ACLK_in = (MAXIGP2ACLK !== 1'bz) && MAXIGP2ACLK; // rv 0 + assign MAXIGP2ARREADY_in = (MAXIGP2ARREADY !== 1'bz) && MAXIGP2ARREADY; // rv 0 + assign MAXIGP2AWREADY_in = (MAXIGP2AWREADY !== 1'bz) && MAXIGP2AWREADY; // rv 0 + assign MAXIGP2BID_in[0] = (MAXIGP2BID[0] !== 1'bz) && MAXIGP2BID[0]; // rv 0 + assign MAXIGP2BID_in[10] = (MAXIGP2BID[10] !== 1'bz) && MAXIGP2BID[10]; // rv 0 + assign MAXIGP2BID_in[11] = (MAXIGP2BID[11] !== 1'bz) && MAXIGP2BID[11]; // rv 0 + assign MAXIGP2BID_in[12] = (MAXIGP2BID[12] !== 1'bz) && MAXIGP2BID[12]; // rv 0 + assign MAXIGP2BID_in[13] = (MAXIGP2BID[13] !== 1'bz) && MAXIGP2BID[13]; // rv 0 + assign MAXIGP2BID_in[14] = (MAXIGP2BID[14] !== 1'bz) && MAXIGP2BID[14]; // rv 0 + assign MAXIGP2BID_in[15] = (MAXIGP2BID[15] !== 1'bz) && MAXIGP2BID[15]; // rv 0 + assign MAXIGP2BID_in[1] = (MAXIGP2BID[1] !== 1'bz) && MAXIGP2BID[1]; // rv 0 + assign MAXIGP2BID_in[2] = (MAXIGP2BID[2] !== 1'bz) && MAXIGP2BID[2]; // rv 0 + assign MAXIGP2BID_in[3] = (MAXIGP2BID[3] !== 1'bz) && MAXIGP2BID[3]; // rv 0 + assign MAXIGP2BID_in[4] = (MAXIGP2BID[4] !== 1'bz) && MAXIGP2BID[4]; // rv 0 + assign MAXIGP2BID_in[5] = (MAXIGP2BID[5] !== 1'bz) && MAXIGP2BID[5]; // rv 0 + assign MAXIGP2BID_in[6] = (MAXIGP2BID[6] !== 1'bz) && MAXIGP2BID[6]; // rv 0 + assign MAXIGP2BID_in[7] = (MAXIGP2BID[7] !== 1'bz) && MAXIGP2BID[7]; // rv 0 + assign MAXIGP2BID_in[8] = (MAXIGP2BID[8] !== 1'bz) && MAXIGP2BID[8]; // rv 0 + assign MAXIGP2BID_in[9] = (MAXIGP2BID[9] !== 1'bz) && MAXIGP2BID[9]; // rv 0 + assign MAXIGP2BRESP_in[0] = (MAXIGP2BRESP[0] !== 1'bz) && MAXIGP2BRESP[0]; // rv 0 + assign MAXIGP2BRESP_in[1] = (MAXIGP2BRESP[1] !== 1'bz) && MAXIGP2BRESP[1]; // rv 0 + assign MAXIGP2BVALID_in = (MAXIGP2BVALID !== 1'bz) && MAXIGP2BVALID; // rv 0 + assign MAXIGP2RDATA_in[0] = (MAXIGP2RDATA[0] !== 1'bz) && MAXIGP2RDATA[0]; // rv 0 + assign MAXIGP2RDATA_in[100] = (MAXIGP2RDATA[100] !== 1'bz) && MAXIGP2RDATA[100]; // rv 0 + assign MAXIGP2RDATA_in[101] = (MAXIGP2RDATA[101] !== 1'bz) && MAXIGP2RDATA[101]; // rv 0 + assign MAXIGP2RDATA_in[102] = (MAXIGP2RDATA[102] !== 1'bz) && MAXIGP2RDATA[102]; // rv 0 + assign MAXIGP2RDATA_in[103] = (MAXIGP2RDATA[103] !== 1'bz) && MAXIGP2RDATA[103]; // rv 0 + assign MAXIGP2RDATA_in[104] = (MAXIGP2RDATA[104] !== 1'bz) && MAXIGP2RDATA[104]; // rv 0 + assign MAXIGP2RDATA_in[105] = (MAXIGP2RDATA[105] !== 1'bz) && MAXIGP2RDATA[105]; // rv 0 + assign MAXIGP2RDATA_in[106] = (MAXIGP2RDATA[106] !== 1'bz) && MAXIGP2RDATA[106]; // rv 0 + assign MAXIGP2RDATA_in[107] = (MAXIGP2RDATA[107] !== 1'bz) && MAXIGP2RDATA[107]; // rv 0 + assign MAXIGP2RDATA_in[108] = (MAXIGP2RDATA[108] !== 1'bz) && MAXIGP2RDATA[108]; // rv 0 + assign MAXIGP2RDATA_in[109] = (MAXIGP2RDATA[109] !== 1'bz) && MAXIGP2RDATA[109]; // rv 0 + assign MAXIGP2RDATA_in[10] = (MAXIGP2RDATA[10] !== 1'bz) && MAXIGP2RDATA[10]; // rv 0 + assign MAXIGP2RDATA_in[110] = (MAXIGP2RDATA[110] !== 1'bz) && MAXIGP2RDATA[110]; // rv 0 + assign MAXIGP2RDATA_in[111] = (MAXIGP2RDATA[111] !== 1'bz) && MAXIGP2RDATA[111]; // rv 0 + assign MAXIGP2RDATA_in[112] = (MAXIGP2RDATA[112] !== 1'bz) && MAXIGP2RDATA[112]; // rv 0 + assign MAXIGP2RDATA_in[113] = (MAXIGP2RDATA[113] !== 1'bz) && MAXIGP2RDATA[113]; // rv 0 + assign MAXIGP2RDATA_in[114] = (MAXIGP2RDATA[114] !== 1'bz) && MAXIGP2RDATA[114]; // rv 0 + assign MAXIGP2RDATA_in[115] = (MAXIGP2RDATA[115] !== 1'bz) && MAXIGP2RDATA[115]; // rv 0 + assign MAXIGP2RDATA_in[116] = (MAXIGP2RDATA[116] !== 1'bz) && MAXIGP2RDATA[116]; // rv 0 + assign MAXIGP2RDATA_in[117] = (MAXIGP2RDATA[117] !== 1'bz) && MAXIGP2RDATA[117]; // rv 0 + assign MAXIGP2RDATA_in[118] = (MAXIGP2RDATA[118] !== 1'bz) && MAXIGP2RDATA[118]; // rv 0 + assign MAXIGP2RDATA_in[119] = (MAXIGP2RDATA[119] !== 1'bz) && MAXIGP2RDATA[119]; // rv 0 + assign MAXIGP2RDATA_in[11] = (MAXIGP2RDATA[11] !== 1'bz) && MAXIGP2RDATA[11]; // rv 0 + assign MAXIGP2RDATA_in[120] = (MAXIGP2RDATA[120] !== 1'bz) && MAXIGP2RDATA[120]; // rv 0 + assign MAXIGP2RDATA_in[121] = (MAXIGP2RDATA[121] !== 1'bz) && MAXIGP2RDATA[121]; // rv 0 + assign MAXIGP2RDATA_in[122] = (MAXIGP2RDATA[122] !== 1'bz) && MAXIGP2RDATA[122]; // rv 0 + assign MAXIGP2RDATA_in[123] = (MAXIGP2RDATA[123] !== 1'bz) && MAXIGP2RDATA[123]; // rv 0 + assign MAXIGP2RDATA_in[124] = (MAXIGP2RDATA[124] !== 1'bz) && MAXIGP2RDATA[124]; // rv 0 + assign MAXIGP2RDATA_in[125] = (MAXIGP2RDATA[125] !== 1'bz) && MAXIGP2RDATA[125]; // rv 0 + assign MAXIGP2RDATA_in[126] = (MAXIGP2RDATA[126] !== 1'bz) && MAXIGP2RDATA[126]; // rv 0 + assign MAXIGP2RDATA_in[127] = (MAXIGP2RDATA[127] !== 1'bz) && MAXIGP2RDATA[127]; // rv 0 + assign MAXIGP2RDATA_in[12] = (MAXIGP2RDATA[12] !== 1'bz) && MAXIGP2RDATA[12]; // rv 0 + assign MAXIGP2RDATA_in[13] = (MAXIGP2RDATA[13] !== 1'bz) && MAXIGP2RDATA[13]; // rv 0 + assign MAXIGP2RDATA_in[14] = (MAXIGP2RDATA[14] !== 1'bz) && MAXIGP2RDATA[14]; // rv 0 + assign MAXIGP2RDATA_in[15] = (MAXIGP2RDATA[15] !== 1'bz) && MAXIGP2RDATA[15]; // rv 0 + assign MAXIGP2RDATA_in[16] = (MAXIGP2RDATA[16] !== 1'bz) && MAXIGP2RDATA[16]; // rv 0 + assign MAXIGP2RDATA_in[17] = (MAXIGP2RDATA[17] !== 1'bz) && MAXIGP2RDATA[17]; // rv 0 + assign MAXIGP2RDATA_in[18] = (MAXIGP2RDATA[18] !== 1'bz) && MAXIGP2RDATA[18]; // rv 0 + assign MAXIGP2RDATA_in[19] = (MAXIGP2RDATA[19] !== 1'bz) && MAXIGP2RDATA[19]; // rv 0 + assign MAXIGP2RDATA_in[1] = (MAXIGP2RDATA[1] !== 1'bz) && MAXIGP2RDATA[1]; // rv 0 + assign MAXIGP2RDATA_in[20] = (MAXIGP2RDATA[20] !== 1'bz) && MAXIGP2RDATA[20]; // rv 0 + assign MAXIGP2RDATA_in[21] = (MAXIGP2RDATA[21] !== 1'bz) && MAXIGP2RDATA[21]; // rv 0 + assign MAXIGP2RDATA_in[22] = (MAXIGP2RDATA[22] !== 1'bz) && MAXIGP2RDATA[22]; // rv 0 + assign MAXIGP2RDATA_in[23] = (MAXIGP2RDATA[23] !== 1'bz) && MAXIGP2RDATA[23]; // rv 0 + assign MAXIGP2RDATA_in[24] = (MAXIGP2RDATA[24] !== 1'bz) && MAXIGP2RDATA[24]; // rv 0 + assign MAXIGP2RDATA_in[25] = (MAXIGP2RDATA[25] !== 1'bz) && MAXIGP2RDATA[25]; // rv 0 + assign MAXIGP2RDATA_in[26] = (MAXIGP2RDATA[26] !== 1'bz) && MAXIGP2RDATA[26]; // rv 0 + assign MAXIGP2RDATA_in[27] = (MAXIGP2RDATA[27] !== 1'bz) && MAXIGP2RDATA[27]; // rv 0 + assign MAXIGP2RDATA_in[28] = (MAXIGP2RDATA[28] !== 1'bz) && MAXIGP2RDATA[28]; // rv 0 + assign MAXIGP2RDATA_in[29] = (MAXIGP2RDATA[29] !== 1'bz) && MAXIGP2RDATA[29]; // rv 0 + assign MAXIGP2RDATA_in[2] = (MAXIGP2RDATA[2] !== 1'bz) && MAXIGP2RDATA[2]; // rv 0 + assign MAXIGP2RDATA_in[30] = (MAXIGP2RDATA[30] !== 1'bz) && MAXIGP2RDATA[30]; // rv 0 + assign MAXIGP2RDATA_in[31] = (MAXIGP2RDATA[31] !== 1'bz) && MAXIGP2RDATA[31]; // rv 0 + assign MAXIGP2RDATA_in[32] = (MAXIGP2RDATA[32] !== 1'bz) && MAXIGP2RDATA[32]; // rv 0 + assign MAXIGP2RDATA_in[33] = (MAXIGP2RDATA[33] !== 1'bz) && MAXIGP2RDATA[33]; // rv 0 + assign MAXIGP2RDATA_in[34] = (MAXIGP2RDATA[34] !== 1'bz) && MAXIGP2RDATA[34]; // rv 0 + assign MAXIGP2RDATA_in[35] = (MAXIGP2RDATA[35] !== 1'bz) && MAXIGP2RDATA[35]; // rv 0 + assign MAXIGP2RDATA_in[36] = (MAXIGP2RDATA[36] !== 1'bz) && MAXIGP2RDATA[36]; // rv 0 + assign MAXIGP2RDATA_in[37] = (MAXIGP2RDATA[37] !== 1'bz) && MAXIGP2RDATA[37]; // rv 0 + assign MAXIGP2RDATA_in[38] = (MAXIGP2RDATA[38] !== 1'bz) && MAXIGP2RDATA[38]; // rv 0 + assign MAXIGP2RDATA_in[39] = (MAXIGP2RDATA[39] !== 1'bz) && MAXIGP2RDATA[39]; // rv 0 + assign MAXIGP2RDATA_in[3] = (MAXIGP2RDATA[3] !== 1'bz) && MAXIGP2RDATA[3]; // rv 0 + assign MAXIGP2RDATA_in[40] = (MAXIGP2RDATA[40] !== 1'bz) && MAXIGP2RDATA[40]; // rv 0 + assign MAXIGP2RDATA_in[41] = (MAXIGP2RDATA[41] !== 1'bz) && MAXIGP2RDATA[41]; // rv 0 + assign MAXIGP2RDATA_in[42] = (MAXIGP2RDATA[42] !== 1'bz) && MAXIGP2RDATA[42]; // rv 0 + assign MAXIGP2RDATA_in[43] = (MAXIGP2RDATA[43] !== 1'bz) && MAXIGP2RDATA[43]; // rv 0 + assign MAXIGP2RDATA_in[44] = (MAXIGP2RDATA[44] !== 1'bz) && MAXIGP2RDATA[44]; // rv 0 + assign MAXIGP2RDATA_in[45] = (MAXIGP2RDATA[45] !== 1'bz) && MAXIGP2RDATA[45]; // rv 0 + assign MAXIGP2RDATA_in[46] = (MAXIGP2RDATA[46] !== 1'bz) && MAXIGP2RDATA[46]; // rv 0 + assign MAXIGP2RDATA_in[47] = (MAXIGP2RDATA[47] !== 1'bz) && MAXIGP2RDATA[47]; // rv 0 + assign MAXIGP2RDATA_in[48] = (MAXIGP2RDATA[48] !== 1'bz) && MAXIGP2RDATA[48]; // rv 0 + assign MAXIGP2RDATA_in[49] = (MAXIGP2RDATA[49] !== 1'bz) && MAXIGP2RDATA[49]; // rv 0 + assign MAXIGP2RDATA_in[4] = (MAXIGP2RDATA[4] !== 1'bz) && MAXIGP2RDATA[4]; // rv 0 + assign MAXIGP2RDATA_in[50] = (MAXIGP2RDATA[50] !== 1'bz) && MAXIGP2RDATA[50]; // rv 0 + assign MAXIGP2RDATA_in[51] = (MAXIGP2RDATA[51] !== 1'bz) && MAXIGP2RDATA[51]; // rv 0 + assign MAXIGP2RDATA_in[52] = (MAXIGP2RDATA[52] !== 1'bz) && MAXIGP2RDATA[52]; // rv 0 + assign MAXIGP2RDATA_in[53] = (MAXIGP2RDATA[53] !== 1'bz) && MAXIGP2RDATA[53]; // rv 0 + assign MAXIGP2RDATA_in[54] = (MAXIGP2RDATA[54] !== 1'bz) && MAXIGP2RDATA[54]; // rv 0 + assign MAXIGP2RDATA_in[55] = (MAXIGP2RDATA[55] !== 1'bz) && MAXIGP2RDATA[55]; // rv 0 + assign MAXIGP2RDATA_in[56] = (MAXIGP2RDATA[56] !== 1'bz) && MAXIGP2RDATA[56]; // rv 0 + assign MAXIGP2RDATA_in[57] = (MAXIGP2RDATA[57] !== 1'bz) && MAXIGP2RDATA[57]; // rv 0 + assign MAXIGP2RDATA_in[58] = (MAXIGP2RDATA[58] !== 1'bz) && MAXIGP2RDATA[58]; // rv 0 + assign MAXIGP2RDATA_in[59] = (MAXIGP2RDATA[59] !== 1'bz) && MAXIGP2RDATA[59]; // rv 0 + assign MAXIGP2RDATA_in[5] = (MAXIGP2RDATA[5] !== 1'bz) && MAXIGP2RDATA[5]; // rv 0 + assign MAXIGP2RDATA_in[60] = (MAXIGP2RDATA[60] !== 1'bz) && MAXIGP2RDATA[60]; // rv 0 + assign MAXIGP2RDATA_in[61] = (MAXIGP2RDATA[61] !== 1'bz) && MAXIGP2RDATA[61]; // rv 0 + assign MAXIGP2RDATA_in[62] = (MAXIGP2RDATA[62] !== 1'bz) && MAXIGP2RDATA[62]; // rv 0 + assign MAXIGP2RDATA_in[63] = (MAXIGP2RDATA[63] !== 1'bz) && MAXIGP2RDATA[63]; // rv 0 + assign MAXIGP2RDATA_in[64] = (MAXIGP2RDATA[64] !== 1'bz) && MAXIGP2RDATA[64]; // rv 0 + assign MAXIGP2RDATA_in[65] = (MAXIGP2RDATA[65] !== 1'bz) && MAXIGP2RDATA[65]; // rv 0 + assign MAXIGP2RDATA_in[66] = (MAXIGP2RDATA[66] !== 1'bz) && MAXIGP2RDATA[66]; // rv 0 + assign MAXIGP2RDATA_in[67] = (MAXIGP2RDATA[67] !== 1'bz) && MAXIGP2RDATA[67]; // rv 0 + assign MAXIGP2RDATA_in[68] = (MAXIGP2RDATA[68] !== 1'bz) && MAXIGP2RDATA[68]; // rv 0 + assign MAXIGP2RDATA_in[69] = (MAXIGP2RDATA[69] !== 1'bz) && MAXIGP2RDATA[69]; // rv 0 + assign MAXIGP2RDATA_in[6] = (MAXIGP2RDATA[6] !== 1'bz) && MAXIGP2RDATA[6]; // rv 0 + assign MAXIGP2RDATA_in[70] = (MAXIGP2RDATA[70] !== 1'bz) && MAXIGP2RDATA[70]; // rv 0 + assign MAXIGP2RDATA_in[71] = (MAXIGP2RDATA[71] !== 1'bz) && MAXIGP2RDATA[71]; // rv 0 + assign MAXIGP2RDATA_in[72] = (MAXIGP2RDATA[72] !== 1'bz) && MAXIGP2RDATA[72]; // rv 0 + assign MAXIGP2RDATA_in[73] = (MAXIGP2RDATA[73] !== 1'bz) && MAXIGP2RDATA[73]; // rv 0 + assign MAXIGP2RDATA_in[74] = (MAXIGP2RDATA[74] !== 1'bz) && MAXIGP2RDATA[74]; // rv 0 + assign MAXIGP2RDATA_in[75] = (MAXIGP2RDATA[75] !== 1'bz) && MAXIGP2RDATA[75]; // rv 0 + assign MAXIGP2RDATA_in[76] = (MAXIGP2RDATA[76] !== 1'bz) && MAXIGP2RDATA[76]; // rv 0 + assign MAXIGP2RDATA_in[77] = (MAXIGP2RDATA[77] !== 1'bz) && MAXIGP2RDATA[77]; // rv 0 + assign MAXIGP2RDATA_in[78] = (MAXIGP2RDATA[78] !== 1'bz) && MAXIGP2RDATA[78]; // rv 0 + assign MAXIGP2RDATA_in[79] = (MAXIGP2RDATA[79] !== 1'bz) && MAXIGP2RDATA[79]; // rv 0 + assign MAXIGP2RDATA_in[7] = (MAXIGP2RDATA[7] !== 1'bz) && MAXIGP2RDATA[7]; // rv 0 + assign MAXIGP2RDATA_in[80] = (MAXIGP2RDATA[80] !== 1'bz) && MAXIGP2RDATA[80]; // rv 0 + assign MAXIGP2RDATA_in[81] = (MAXIGP2RDATA[81] !== 1'bz) && MAXIGP2RDATA[81]; // rv 0 + assign MAXIGP2RDATA_in[82] = (MAXIGP2RDATA[82] !== 1'bz) && MAXIGP2RDATA[82]; // rv 0 + assign MAXIGP2RDATA_in[83] = (MAXIGP2RDATA[83] !== 1'bz) && MAXIGP2RDATA[83]; // rv 0 + assign MAXIGP2RDATA_in[84] = (MAXIGP2RDATA[84] !== 1'bz) && MAXIGP2RDATA[84]; // rv 0 + assign MAXIGP2RDATA_in[85] = (MAXIGP2RDATA[85] !== 1'bz) && MAXIGP2RDATA[85]; // rv 0 + assign MAXIGP2RDATA_in[86] = (MAXIGP2RDATA[86] !== 1'bz) && MAXIGP2RDATA[86]; // rv 0 + assign MAXIGP2RDATA_in[87] = (MAXIGP2RDATA[87] !== 1'bz) && MAXIGP2RDATA[87]; // rv 0 + assign MAXIGP2RDATA_in[88] = (MAXIGP2RDATA[88] !== 1'bz) && MAXIGP2RDATA[88]; // rv 0 + assign MAXIGP2RDATA_in[89] = (MAXIGP2RDATA[89] !== 1'bz) && MAXIGP2RDATA[89]; // rv 0 + assign MAXIGP2RDATA_in[8] = (MAXIGP2RDATA[8] !== 1'bz) && MAXIGP2RDATA[8]; // rv 0 + assign MAXIGP2RDATA_in[90] = (MAXIGP2RDATA[90] !== 1'bz) && MAXIGP2RDATA[90]; // rv 0 + assign MAXIGP2RDATA_in[91] = (MAXIGP2RDATA[91] !== 1'bz) && MAXIGP2RDATA[91]; // rv 0 + assign MAXIGP2RDATA_in[92] = (MAXIGP2RDATA[92] !== 1'bz) && MAXIGP2RDATA[92]; // rv 0 + assign MAXIGP2RDATA_in[93] = (MAXIGP2RDATA[93] !== 1'bz) && MAXIGP2RDATA[93]; // rv 0 + assign MAXIGP2RDATA_in[94] = (MAXIGP2RDATA[94] !== 1'bz) && MAXIGP2RDATA[94]; // rv 0 + assign MAXIGP2RDATA_in[95] = (MAXIGP2RDATA[95] !== 1'bz) && MAXIGP2RDATA[95]; // rv 0 + assign MAXIGP2RDATA_in[96] = (MAXIGP2RDATA[96] !== 1'bz) && MAXIGP2RDATA[96]; // rv 0 + assign MAXIGP2RDATA_in[97] = (MAXIGP2RDATA[97] !== 1'bz) && MAXIGP2RDATA[97]; // rv 0 + assign MAXIGP2RDATA_in[98] = (MAXIGP2RDATA[98] !== 1'bz) && MAXIGP2RDATA[98]; // rv 0 + assign MAXIGP2RDATA_in[99] = (MAXIGP2RDATA[99] !== 1'bz) && MAXIGP2RDATA[99]; // rv 0 + assign MAXIGP2RDATA_in[9] = (MAXIGP2RDATA[9] !== 1'bz) && MAXIGP2RDATA[9]; // rv 0 + assign MAXIGP2RID_in[0] = (MAXIGP2RID[0] !== 1'bz) && MAXIGP2RID[0]; // rv 0 + assign MAXIGP2RID_in[10] = (MAXIGP2RID[10] !== 1'bz) && MAXIGP2RID[10]; // rv 0 + assign MAXIGP2RID_in[11] = (MAXIGP2RID[11] !== 1'bz) && MAXIGP2RID[11]; // rv 0 + assign MAXIGP2RID_in[12] = (MAXIGP2RID[12] !== 1'bz) && MAXIGP2RID[12]; // rv 0 + assign MAXIGP2RID_in[13] = (MAXIGP2RID[13] !== 1'bz) && MAXIGP2RID[13]; // rv 0 + assign MAXIGP2RID_in[14] = (MAXIGP2RID[14] !== 1'bz) && MAXIGP2RID[14]; // rv 0 + assign MAXIGP2RID_in[15] = (MAXIGP2RID[15] !== 1'bz) && MAXIGP2RID[15]; // rv 0 + assign MAXIGP2RID_in[1] = (MAXIGP2RID[1] !== 1'bz) && MAXIGP2RID[1]; // rv 0 + assign MAXIGP2RID_in[2] = (MAXIGP2RID[2] !== 1'bz) && MAXIGP2RID[2]; // rv 0 + assign MAXIGP2RID_in[3] = (MAXIGP2RID[3] !== 1'bz) && MAXIGP2RID[3]; // rv 0 + assign MAXIGP2RID_in[4] = (MAXIGP2RID[4] !== 1'bz) && MAXIGP2RID[4]; // rv 0 + assign MAXIGP2RID_in[5] = (MAXIGP2RID[5] !== 1'bz) && MAXIGP2RID[5]; // rv 0 + assign MAXIGP2RID_in[6] = (MAXIGP2RID[6] !== 1'bz) && MAXIGP2RID[6]; // rv 0 + assign MAXIGP2RID_in[7] = (MAXIGP2RID[7] !== 1'bz) && MAXIGP2RID[7]; // rv 0 + assign MAXIGP2RID_in[8] = (MAXIGP2RID[8] !== 1'bz) && MAXIGP2RID[8]; // rv 0 + assign MAXIGP2RID_in[9] = (MAXIGP2RID[9] !== 1'bz) && MAXIGP2RID[9]; // rv 0 + assign MAXIGP2RLAST_in = (MAXIGP2RLAST !== 1'bz) && MAXIGP2RLAST; // rv 0 + assign MAXIGP2RRESP_in[0] = (MAXIGP2RRESP[0] !== 1'bz) && MAXIGP2RRESP[0]; // rv 0 + assign MAXIGP2RRESP_in[1] = (MAXIGP2RRESP[1] !== 1'bz) && MAXIGP2RRESP[1]; // rv 0 + assign MAXIGP2RVALID_in = (MAXIGP2RVALID !== 1'bz) && MAXIGP2RVALID; // rv 0 + assign MAXIGP2WREADY_in = (MAXIGP2WREADY !== 1'bz) && MAXIGP2WREADY; // rv 0 + assign PL2ADMACVLD_in[0] = (PL2ADMACVLD[0] !== 1'bz) && PL2ADMACVLD[0]; // rv 0 + assign PL2ADMACVLD_in[1] = (PL2ADMACVLD[1] !== 1'bz) && PL2ADMACVLD[1]; // rv 0 + assign PL2ADMACVLD_in[2] = (PL2ADMACVLD[2] !== 1'bz) && PL2ADMACVLD[2]; // rv 0 + assign PL2ADMACVLD_in[3] = (PL2ADMACVLD[3] !== 1'bz) && PL2ADMACVLD[3]; // rv 0 + assign PL2ADMACVLD_in[4] = (PL2ADMACVLD[4] !== 1'bz) && PL2ADMACVLD[4]; // rv 0 + assign PL2ADMACVLD_in[5] = (PL2ADMACVLD[5] !== 1'bz) && PL2ADMACVLD[5]; // rv 0 + assign PL2ADMACVLD_in[6] = (PL2ADMACVLD[6] !== 1'bz) && PL2ADMACVLD[6]; // rv 0 + assign PL2ADMACVLD_in[7] = (PL2ADMACVLD[7] !== 1'bz) && PL2ADMACVLD[7]; // rv 0 + assign PL2ADMATACK_in[0] = (PL2ADMATACK[0] !== 1'bz) && PL2ADMATACK[0]; // rv 0 + assign PL2ADMATACK_in[1] = (PL2ADMATACK[1] !== 1'bz) && PL2ADMATACK[1]; // rv 0 + assign PL2ADMATACK_in[2] = (PL2ADMATACK[2] !== 1'bz) && PL2ADMATACK[2]; // rv 0 + assign PL2ADMATACK_in[3] = (PL2ADMATACK[3] !== 1'bz) && PL2ADMATACK[3]; // rv 0 + assign PL2ADMATACK_in[4] = (PL2ADMATACK[4] !== 1'bz) && PL2ADMATACK[4]; // rv 0 + assign PL2ADMATACK_in[5] = (PL2ADMATACK[5] !== 1'bz) && PL2ADMATACK[5]; // rv 0 + assign PL2ADMATACK_in[6] = (PL2ADMATACK[6] !== 1'bz) && PL2ADMATACK[6]; // rv 0 + assign PL2ADMATACK_in[7] = (PL2ADMATACK[7] !== 1'bz) && PL2ADMATACK[7]; // rv 0 + assign PL2GDMACVLD_in[0] = (PL2GDMACVLD[0] !== 1'bz) && PL2GDMACVLD[0]; // rv 0 + assign PL2GDMACVLD_in[1] = (PL2GDMACVLD[1] !== 1'bz) && PL2GDMACVLD[1]; // rv 0 + assign PL2GDMACVLD_in[2] = (PL2GDMACVLD[2] !== 1'bz) && PL2GDMACVLD[2]; // rv 0 + assign PL2GDMACVLD_in[3] = (PL2GDMACVLD[3] !== 1'bz) && PL2GDMACVLD[3]; // rv 0 + assign PL2GDMACVLD_in[4] = (PL2GDMACVLD[4] !== 1'bz) && PL2GDMACVLD[4]; // rv 0 + assign PL2GDMACVLD_in[5] = (PL2GDMACVLD[5] !== 1'bz) && PL2GDMACVLD[5]; // rv 0 + assign PL2GDMACVLD_in[6] = (PL2GDMACVLD[6] !== 1'bz) && PL2GDMACVLD[6]; // rv 0 + assign PL2GDMACVLD_in[7] = (PL2GDMACVLD[7] !== 1'bz) && PL2GDMACVLD[7]; // rv 0 + assign PL2GDMATACK_in[0] = (PL2GDMATACK[0] !== 1'bz) && PL2GDMATACK[0]; // rv 0 + assign PL2GDMATACK_in[1] = (PL2GDMATACK[1] !== 1'bz) && PL2GDMATACK[1]; // rv 0 + assign PL2GDMATACK_in[2] = (PL2GDMATACK[2] !== 1'bz) && PL2GDMATACK[2]; // rv 0 + assign PL2GDMATACK_in[3] = (PL2GDMATACK[3] !== 1'bz) && PL2GDMATACK[3]; // rv 0 + assign PL2GDMATACK_in[4] = (PL2GDMATACK[4] !== 1'bz) && PL2GDMATACK[4]; // rv 0 + assign PL2GDMATACK_in[5] = (PL2GDMATACK[5] !== 1'bz) && PL2GDMATACK[5]; // rv 0 + assign PL2GDMATACK_in[6] = (PL2GDMATACK[6] !== 1'bz) && PL2GDMATACK[6]; // rv 0 + assign PL2GDMATACK_in[7] = (PL2GDMATACK[7] !== 1'bz) && PL2GDMATACK[7]; // rv 0 + assign PLACECLK_in = (PLACECLK !== 1'bz) && PLACECLK; // rv 0 + assign SACEFPDACREADY_in = (SACEFPDACREADY !== 1'bz) && SACEFPDACREADY; // rv 0 + assign SACEFPDARADDR_in[0] = (SACEFPDARADDR[0] !== 1'bz) && SACEFPDARADDR[0]; // rv 0 + assign SACEFPDARADDR_in[10] = (SACEFPDARADDR[10] !== 1'bz) && SACEFPDARADDR[10]; // rv 0 + assign SACEFPDARADDR_in[11] = (SACEFPDARADDR[11] !== 1'bz) && SACEFPDARADDR[11]; // rv 0 + assign SACEFPDARADDR_in[12] = (SACEFPDARADDR[12] !== 1'bz) && SACEFPDARADDR[12]; // rv 0 + assign SACEFPDARADDR_in[13] = (SACEFPDARADDR[13] !== 1'bz) && SACEFPDARADDR[13]; // rv 0 + assign SACEFPDARADDR_in[14] = (SACEFPDARADDR[14] !== 1'bz) && SACEFPDARADDR[14]; // rv 0 + assign SACEFPDARADDR_in[15] = (SACEFPDARADDR[15] !== 1'bz) && SACEFPDARADDR[15]; // rv 0 + assign SACEFPDARADDR_in[16] = (SACEFPDARADDR[16] !== 1'bz) && SACEFPDARADDR[16]; // rv 0 + assign SACEFPDARADDR_in[17] = (SACEFPDARADDR[17] !== 1'bz) && SACEFPDARADDR[17]; // rv 0 + assign SACEFPDARADDR_in[18] = (SACEFPDARADDR[18] !== 1'bz) && SACEFPDARADDR[18]; // rv 0 + assign SACEFPDARADDR_in[19] = (SACEFPDARADDR[19] !== 1'bz) && SACEFPDARADDR[19]; // rv 0 + assign SACEFPDARADDR_in[1] = (SACEFPDARADDR[1] !== 1'bz) && SACEFPDARADDR[1]; // rv 0 + assign SACEFPDARADDR_in[20] = (SACEFPDARADDR[20] !== 1'bz) && SACEFPDARADDR[20]; // rv 0 + assign SACEFPDARADDR_in[21] = (SACEFPDARADDR[21] !== 1'bz) && SACEFPDARADDR[21]; // rv 0 + assign SACEFPDARADDR_in[22] = (SACEFPDARADDR[22] !== 1'bz) && SACEFPDARADDR[22]; // rv 0 + assign SACEFPDARADDR_in[23] = (SACEFPDARADDR[23] !== 1'bz) && SACEFPDARADDR[23]; // rv 0 + assign SACEFPDARADDR_in[24] = (SACEFPDARADDR[24] !== 1'bz) && SACEFPDARADDR[24]; // rv 0 + assign SACEFPDARADDR_in[25] = (SACEFPDARADDR[25] !== 1'bz) && SACEFPDARADDR[25]; // rv 0 + assign SACEFPDARADDR_in[26] = (SACEFPDARADDR[26] !== 1'bz) && SACEFPDARADDR[26]; // rv 0 + assign SACEFPDARADDR_in[27] = (SACEFPDARADDR[27] !== 1'bz) && SACEFPDARADDR[27]; // rv 0 + assign SACEFPDARADDR_in[28] = (SACEFPDARADDR[28] !== 1'bz) && SACEFPDARADDR[28]; // rv 0 + assign SACEFPDARADDR_in[29] = (SACEFPDARADDR[29] !== 1'bz) && SACEFPDARADDR[29]; // rv 0 + assign SACEFPDARADDR_in[2] = (SACEFPDARADDR[2] !== 1'bz) && SACEFPDARADDR[2]; // rv 0 + assign SACEFPDARADDR_in[30] = (SACEFPDARADDR[30] !== 1'bz) && SACEFPDARADDR[30]; // rv 0 + assign SACEFPDARADDR_in[31] = (SACEFPDARADDR[31] !== 1'bz) && SACEFPDARADDR[31]; // rv 0 + assign SACEFPDARADDR_in[32] = (SACEFPDARADDR[32] !== 1'bz) && SACEFPDARADDR[32]; // rv 0 + assign SACEFPDARADDR_in[33] = (SACEFPDARADDR[33] !== 1'bz) && SACEFPDARADDR[33]; // rv 0 + assign SACEFPDARADDR_in[34] = (SACEFPDARADDR[34] !== 1'bz) && SACEFPDARADDR[34]; // rv 0 + assign SACEFPDARADDR_in[35] = (SACEFPDARADDR[35] !== 1'bz) && SACEFPDARADDR[35]; // rv 0 + assign SACEFPDARADDR_in[36] = (SACEFPDARADDR[36] !== 1'bz) && SACEFPDARADDR[36]; // rv 0 + assign SACEFPDARADDR_in[37] = (SACEFPDARADDR[37] !== 1'bz) && SACEFPDARADDR[37]; // rv 0 + assign SACEFPDARADDR_in[38] = (SACEFPDARADDR[38] !== 1'bz) && SACEFPDARADDR[38]; // rv 0 + assign SACEFPDARADDR_in[39] = (SACEFPDARADDR[39] !== 1'bz) && SACEFPDARADDR[39]; // rv 0 + assign SACEFPDARADDR_in[3] = (SACEFPDARADDR[3] !== 1'bz) && SACEFPDARADDR[3]; // rv 0 + assign SACEFPDARADDR_in[40] = (SACEFPDARADDR[40] !== 1'bz) && SACEFPDARADDR[40]; // rv 0 + assign SACEFPDARADDR_in[41] = (SACEFPDARADDR[41] !== 1'bz) && SACEFPDARADDR[41]; // rv 0 + assign SACEFPDARADDR_in[42] = (SACEFPDARADDR[42] !== 1'bz) && SACEFPDARADDR[42]; // rv 0 + assign SACEFPDARADDR_in[43] = (SACEFPDARADDR[43] !== 1'bz) && SACEFPDARADDR[43]; // rv 0 + assign SACEFPDARADDR_in[4] = (SACEFPDARADDR[4] !== 1'bz) && SACEFPDARADDR[4]; // rv 0 + assign SACEFPDARADDR_in[5] = (SACEFPDARADDR[5] !== 1'bz) && SACEFPDARADDR[5]; // rv 0 + assign SACEFPDARADDR_in[6] = (SACEFPDARADDR[6] !== 1'bz) && SACEFPDARADDR[6]; // rv 0 + assign SACEFPDARADDR_in[7] = (SACEFPDARADDR[7] !== 1'bz) && SACEFPDARADDR[7]; // rv 0 + assign SACEFPDARADDR_in[8] = (SACEFPDARADDR[8] !== 1'bz) && SACEFPDARADDR[8]; // rv 0 + assign SACEFPDARADDR_in[9] = (SACEFPDARADDR[9] !== 1'bz) && SACEFPDARADDR[9]; // rv 0 + assign SACEFPDARBAR_in[0] = (SACEFPDARBAR[0] !== 1'bz) && SACEFPDARBAR[0]; // rv 0 + assign SACEFPDARBAR_in[1] = (SACEFPDARBAR[1] !== 1'bz) && SACEFPDARBAR[1]; // rv 0 + assign SACEFPDARBURST_in[0] = (SACEFPDARBURST[0] !== 1'bz) && SACEFPDARBURST[0]; // rv 0 + assign SACEFPDARBURST_in[1] = (SACEFPDARBURST[1] !== 1'bz) && SACEFPDARBURST[1]; // rv 0 + assign SACEFPDARCACHE_in[0] = (SACEFPDARCACHE[0] !== 1'bz) && SACEFPDARCACHE[0]; // rv 0 + assign SACEFPDARCACHE_in[1] = (SACEFPDARCACHE[1] !== 1'bz) && SACEFPDARCACHE[1]; // rv 0 + assign SACEFPDARCACHE_in[2] = (SACEFPDARCACHE[2] !== 1'bz) && SACEFPDARCACHE[2]; // rv 0 + assign SACEFPDARCACHE_in[3] = (SACEFPDARCACHE[3] !== 1'bz) && SACEFPDARCACHE[3]; // rv 0 + assign SACEFPDARDOMAIN_in[0] = (SACEFPDARDOMAIN[0] !== 1'bz) && SACEFPDARDOMAIN[0]; // rv 0 + assign SACEFPDARDOMAIN_in[1] = (SACEFPDARDOMAIN[1] !== 1'bz) && SACEFPDARDOMAIN[1]; // rv 0 + assign SACEFPDARID_in[0] = (SACEFPDARID[0] !== 1'bz) && SACEFPDARID[0]; // rv 0 + assign SACEFPDARID_in[1] = (SACEFPDARID[1] !== 1'bz) && SACEFPDARID[1]; // rv 0 + assign SACEFPDARID_in[2] = (SACEFPDARID[2] !== 1'bz) && SACEFPDARID[2]; // rv 0 + assign SACEFPDARID_in[3] = (SACEFPDARID[3] !== 1'bz) && SACEFPDARID[3]; // rv 0 + assign SACEFPDARID_in[4] = (SACEFPDARID[4] !== 1'bz) && SACEFPDARID[4]; // rv 0 + assign SACEFPDARID_in[5] = (SACEFPDARID[5] !== 1'bz) && SACEFPDARID[5]; // rv 0 + assign SACEFPDARLEN_in[0] = (SACEFPDARLEN[0] !== 1'bz) && SACEFPDARLEN[0]; // rv 0 + assign SACEFPDARLEN_in[1] = (SACEFPDARLEN[1] !== 1'bz) && SACEFPDARLEN[1]; // rv 0 + assign SACEFPDARLEN_in[2] = (SACEFPDARLEN[2] !== 1'bz) && SACEFPDARLEN[2]; // rv 0 + assign SACEFPDARLEN_in[3] = (SACEFPDARLEN[3] !== 1'bz) && SACEFPDARLEN[3]; // rv 0 + assign SACEFPDARLEN_in[4] = (SACEFPDARLEN[4] !== 1'bz) && SACEFPDARLEN[4]; // rv 0 + assign SACEFPDARLEN_in[5] = (SACEFPDARLEN[5] !== 1'bz) && SACEFPDARLEN[5]; // rv 0 + assign SACEFPDARLEN_in[6] = (SACEFPDARLEN[6] !== 1'bz) && SACEFPDARLEN[6]; // rv 0 + assign SACEFPDARLEN_in[7] = (SACEFPDARLEN[7] !== 1'bz) && SACEFPDARLEN[7]; // rv 0 + assign SACEFPDARLOCK_in = (SACEFPDARLOCK !== 1'bz) && SACEFPDARLOCK; // rv 0 + assign SACEFPDARPROT_in[0] = (SACEFPDARPROT[0] !== 1'bz) && SACEFPDARPROT[0]; // rv 0 + assign SACEFPDARPROT_in[1] = (SACEFPDARPROT[1] !== 1'bz) && SACEFPDARPROT[1]; // rv 0 + assign SACEFPDARPROT_in[2] = (SACEFPDARPROT[2] !== 1'bz) && SACEFPDARPROT[2]; // rv 0 + assign SACEFPDARQOS_in[0] = (SACEFPDARQOS[0] !== 1'bz) && SACEFPDARQOS[0]; // rv 0 + assign SACEFPDARQOS_in[1] = (SACEFPDARQOS[1] !== 1'bz) && SACEFPDARQOS[1]; // rv 0 + assign SACEFPDARQOS_in[2] = (SACEFPDARQOS[2] !== 1'bz) && SACEFPDARQOS[2]; // rv 0 + assign SACEFPDARQOS_in[3] = (SACEFPDARQOS[3] !== 1'bz) && SACEFPDARQOS[3]; // rv 0 + assign SACEFPDARREGION_in[0] = (SACEFPDARREGION[0] !== 1'bz) && SACEFPDARREGION[0]; // rv 0 + assign SACEFPDARREGION_in[1] = (SACEFPDARREGION[1] !== 1'bz) && SACEFPDARREGION[1]; // rv 0 + assign SACEFPDARREGION_in[2] = (SACEFPDARREGION[2] !== 1'bz) && SACEFPDARREGION[2]; // rv 0 + assign SACEFPDARREGION_in[3] = (SACEFPDARREGION[3] !== 1'bz) && SACEFPDARREGION[3]; // rv 0 + assign SACEFPDARSIZE_in[0] = (SACEFPDARSIZE[0] !== 1'bz) && SACEFPDARSIZE[0]; // rv 0 + assign SACEFPDARSIZE_in[1] = (SACEFPDARSIZE[1] !== 1'bz) && SACEFPDARSIZE[1]; // rv 0 + assign SACEFPDARSIZE_in[2] = (SACEFPDARSIZE[2] !== 1'bz) && SACEFPDARSIZE[2]; // rv 0 + assign SACEFPDARSNOOP_in[0] = (SACEFPDARSNOOP[0] !== 1'bz) && SACEFPDARSNOOP[0]; // rv 0 + assign SACEFPDARSNOOP_in[1] = (SACEFPDARSNOOP[1] !== 1'bz) && SACEFPDARSNOOP[1]; // rv 0 + assign SACEFPDARSNOOP_in[2] = (SACEFPDARSNOOP[2] !== 1'bz) && SACEFPDARSNOOP[2]; // rv 0 + assign SACEFPDARSNOOP_in[3] = (SACEFPDARSNOOP[3] !== 1'bz) && SACEFPDARSNOOP[3]; // rv 0 + assign SACEFPDARUSER_in[0] = (SACEFPDARUSER[0] !== 1'bz) && SACEFPDARUSER[0]; // rv 0 + assign SACEFPDARUSER_in[10] = (SACEFPDARUSER[10] !== 1'bz) && SACEFPDARUSER[10]; // rv 0 + assign SACEFPDARUSER_in[11] = (SACEFPDARUSER[11] !== 1'bz) && SACEFPDARUSER[11]; // rv 0 + assign SACEFPDARUSER_in[12] = (SACEFPDARUSER[12] !== 1'bz) && SACEFPDARUSER[12]; // rv 0 + assign SACEFPDARUSER_in[13] = (SACEFPDARUSER[13] !== 1'bz) && SACEFPDARUSER[13]; // rv 0 + assign SACEFPDARUSER_in[14] = (SACEFPDARUSER[14] !== 1'bz) && SACEFPDARUSER[14]; // rv 0 + assign SACEFPDARUSER_in[15] = (SACEFPDARUSER[15] !== 1'bz) && SACEFPDARUSER[15]; // rv 0 + assign SACEFPDARUSER_in[1] = (SACEFPDARUSER[1] !== 1'bz) && SACEFPDARUSER[1]; // rv 0 + assign SACEFPDARUSER_in[2] = (SACEFPDARUSER[2] !== 1'bz) && SACEFPDARUSER[2]; // rv 0 + assign SACEFPDARUSER_in[3] = (SACEFPDARUSER[3] !== 1'bz) && SACEFPDARUSER[3]; // rv 0 + assign SACEFPDARUSER_in[4] = (SACEFPDARUSER[4] !== 1'bz) && SACEFPDARUSER[4]; // rv 0 + assign SACEFPDARUSER_in[5] = (SACEFPDARUSER[5] !== 1'bz) && SACEFPDARUSER[5]; // rv 0 + assign SACEFPDARUSER_in[6] = (SACEFPDARUSER[6] !== 1'bz) && SACEFPDARUSER[6]; // rv 0 + assign SACEFPDARUSER_in[7] = (SACEFPDARUSER[7] !== 1'bz) && SACEFPDARUSER[7]; // rv 0 + assign SACEFPDARUSER_in[8] = (SACEFPDARUSER[8] !== 1'bz) && SACEFPDARUSER[8]; // rv 0 + assign SACEFPDARUSER_in[9] = (SACEFPDARUSER[9] !== 1'bz) && SACEFPDARUSER[9]; // rv 0 + assign SACEFPDARVALID_in = (SACEFPDARVALID !== 1'bz) && SACEFPDARVALID; // rv 0 + assign SACEFPDAWADDR_in[0] = (SACEFPDAWADDR[0] !== 1'bz) && SACEFPDAWADDR[0]; // rv 0 + assign SACEFPDAWADDR_in[10] = (SACEFPDAWADDR[10] !== 1'bz) && SACEFPDAWADDR[10]; // rv 0 + assign SACEFPDAWADDR_in[11] = (SACEFPDAWADDR[11] !== 1'bz) && SACEFPDAWADDR[11]; // rv 0 + assign SACEFPDAWADDR_in[12] = (SACEFPDAWADDR[12] !== 1'bz) && SACEFPDAWADDR[12]; // rv 0 + assign SACEFPDAWADDR_in[13] = (SACEFPDAWADDR[13] !== 1'bz) && SACEFPDAWADDR[13]; // rv 0 + assign SACEFPDAWADDR_in[14] = (SACEFPDAWADDR[14] !== 1'bz) && SACEFPDAWADDR[14]; // rv 0 + assign SACEFPDAWADDR_in[15] = (SACEFPDAWADDR[15] !== 1'bz) && SACEFPDAWADDR[15]; // rv 0 + assign SACEFPDAWADDR_in[16] = (SACEFPDAWADDR[16] !== 1'bz) && SACEFPDAWADDR[16]; // rv 0 + assign SACEFPDAWADDR_in[17] = (SACEFPDAWADDR[17] !== 1'bz) && SACEFPDAWADDR[17]; // rv 0 + assign SACEFPDAWADDR_in[18] = (SACEFPDAWADDR[18] !== 1'bz) && SACEFPDAWADDR[18]; // rv 0 + assign SACEFPDAWADDR_in[19] = (SACEFPDAWADDR[19] !== 1'bz) && SACEFPDAWADDR[19]; // rv 0 + assign SACEFPDAWADDR_in[1] = (SACEFPDAWADDR[1] !== 1'bz) && SACEFPDAWADDR[1]; // rv 0 + assign SACEFPDAWADDR_in[20] = (SACEFPDAWADDR[20] !== 1'bz) && SACEFPDAWADDR[20]; // rv 0 + assign SACEFPDAWADDR_in[21] = (SACEFPDAWADDR[21] !== 1'bz) && SACEFPDAWADDR[21]; // rv 0 + assign SACEFPDAWADDR_in[22] = (SACEFPDAWADDR[22] !== 1'bz) && SACEFPDAWADDR[22]; // rv 0 + assign SACEFPDAWADDR_in[23] = (SACEFPDAWADDR[23] !== 1'bz) && SACEFPDAWADDR[23]; // rv 0 + assign SACEFPDAWADDR_in[24] = (SACEFPDAWADDR[24] !== 1'bz) && SACEFPDAWADDR[24]; // rv 0 + assign SACEFPDAWADDR_in[25] = (SACEFPDAWADDR[25] !== 1'bz) && SACEFPDAWADDR[25]; // rv 0 + assign SACEFPDAWADDR_in[26] = (SACEFPDAWADDR[26] !== 1'bz) && SACEFPDAWADDR[26]; // rv 0 + assign SACEFPDAWADDR_in[27] = (SACEFPDAWADDR[27] !== 1'bz) && SACEFPDAWADDR[27]; // rv 0 + assign SACEFPDAWADDR_in[28] = (SACEFPDAWADDR[28] !== 1'bz) && SACEFPDAWADDR[28]; // rv 0 + assign SACEFPDAWADDR_in[29] = (SACEFPDAWADDR[29] !== 1'bz) && SACEFPDAWADDR[29]; // rv 0 + assign SACEFPDAWADDR_in[2] = (SACEFPDAWADDR[2] !== 1'bz) && SACEFPDAWADDR[2]; // rv 0 + assign SACEFPDAWADDR_in[30] = (SACEFPDAWADDR[30] !== 1'bz) && SACEFPDAWADDR[30]; // rv 0 + assign SACEFPDAWADDR_in[31] = (SACEFPDAWADDR[31] !== 1'bz) && SACEFPDAWADDR[31]; // rv 0 + assign SACEFPDAWADDR_in[32] = (SACEFPDAWADDR[32] !== 1'bz) && SACEFPDAWADDR[32]; // rv 0 + assign SACEFPDAWADDR_in[33] = (SACEFPDAWADDR[33] !== 1'bz) && SACEFPDAWADDR[33]; // rv 0 + assign SACEFPDAWADDR_in[34] = (SACEFPDAWADDR[34] !== 1'bz) && SACEFPDAWADDR[34]; // rv 0 + assign SACEFPDAWADDR_in[35] = (SACEFPDAWADDR[35] !== 1'bz) && SACEFPDAWADDR[35]; // rv 0 + assign SACEFPDAWADDR_in[36] = (SACEFPDAWADDR[36] !== 1'bz) && SACEFPDAWADDR[36]; // rv 0 + assign SACEFPDAWADDR_in[37] = (SACEFPDAWADDR[37] !== 1'bz) && SACEFPDAWADDR[37]; // rv 0 + assign SACEFPDAWADDR_in[38] = (SACEFPDAWADDR[38] !== 1'bz) && SACEFPDAWADDR[38]; // rv 0 + assign SACEFPDAWADDR_in[39] = (SACEFPDAWADDR[39] !== 1'bz) && SACEFPDAWADDR[39]; // rv 0 + assign SACEFPDAWADDR_in[3] = (SACEFPDAWADDR[3] !== 1'bz) && SACEFPDAWADDR[3]; // rv 0 + assign SACEFPDAWADDR_in[40] = (SACEFPDAWADDR[40] !== 1'bz) && SACEFPDAWADDR[40]; // rv 0 + assign SACEFPDAWADDR_in[41] = (SACEFPDAWADDR[41] !== 1'bz) && SACEFPDAWADDR[41]; // rv 0 + assign SACEFPDAWADDR_in[42] = (SACEFPDAWADDR[42] !== 1'bz) && SACEFPDAWADDR[42]; // rv 0 + assign SACEFPDAWADDR_in[43] = (SACEFPDAWADDR[43] !== 1'bz) && SACEFPDAWADDR[43]; // rv 0 + assign SACEFPDAWADDR_in[4] = (SACEFPDAWADDR[4] !== 1'bz) && SACEFPDAWADDR[4]; // rv 0 + assign SACEFPDAWADDR_in[5] = (SACEFPDAWADDR[5] !== 1'bz) && SACEFPDAWADDR[5]; // rv 0 + assign SACEFPDAWADDR_in[6] = (SACEFPDAWADDR[6] !== 1'bz) && SACEFPDAWADDR[6]; // rv 0 + assign SACEFPDAWADDR_in[7] = (SACEFPDAWADDR[7] !== 1'bz) && SACEFPDAWADDR[7]; // rv 0 + assign SACEFPDAWADDR_in[8] = (SACEFPDAWADDR[8] !== 1'bz) && SACEFPDAWADDR[8]; // rv 0 + assign SACEFPDAWADDR_in[9] = (SACEFPDAWADDR[9] !== 1'bz) && SACEFPDAWADDR[9]; // rv 0 + assign SACEFPDAWBAR_in[0] = (SACEFPDAWBAR[0] !== 1'bz) && SACEFPDAWBAR[0]; // rv 0 + assign SACEFPDAWBAR_in[1] = (SACEFPDAWBAR[1] !== 1'bz) && SACEFPDAWBAR[1]; // rv 0 + assign SACEFPDAWBURST_in[0] = (SACEFPDAWBURST[0] !== 1'bz) && SACEFPDAWBURST[0]; // rv 0 + assign SACEFPDAWBURST_in[1] = (SACEFPDAWBURST[1] !== 1'bz) && SACEFPDAWBURST[1]; // rv 0 + assign SACEFPDAWCACHE_in[0] = (SACEFPDAWCACHE[0] !== 1'bz) && SACEFPDAWCACHE[0]; // rv 0 + assign SACEFPDAWCACHE_in[1] = (SACEFPDAWCACHE[1] !== 1'bz) && SACEFPDAWCACHE[1]; // rv 0 + assign SACEFPDAWCACHE_in[2] = (SACEFPDAWCACHE[2] !== 1'bz) && SACEFPDAWCACHE[2]; // rv 0 + assign SACEFPDAWCACHE_in[3] = (SACEFPDAWCACHE[3] !== 1'bz) && SACEFPDAWCACHE[3]; // rv 0 + assign SACEFPDAWDOMAIN_in[0] = (SACEFPDAWDOMAIN[0] !== 1'bz) && SACEFPDAWDOMAIN[0]; // rv 0 + assign SACEFPDAWDOMAIN_in[1] = (SACEFPDAWDOMAIN[1] !== 1'bz) && SACEFPDAWDOMAIN[1]; // rv 0 + assign SACEFPDAWID_in[0] = (SACEFPDAWID[0] !== 1'bz) && SACEFPDAWID[0]; // rv 0 + assign SACEFPDAWID_in[1] = (SACEFPDAWID[1] !== 1'bz) && SACEFPDAWID[1]; // rv 0 + assign SACEFPDAWID_in[2] = (SACEFPDAWID[2] !== 1'bz) && SACEFPDAWID[2]; // rv 0 + assign SACEFPDAWID_in[3] = (SACEFPDAWID[3] !== 1'bz) && SACEFPDAWID[3]; // rv 0 + assign SACEFPDAWID_in[4] = (SACEFPDAWID[4] !== 1'bz) && SACEFPDAWID[4]; // rv 0 + assign SACEFPDAWID_in[5] = (SACEFPDAWID[5] !== 1'bz) && SACEFPDAWID[5]; // rv 0 + assign SACEFPDAWLEN_in[0] = (SACEFPDAWLEN[0] !== 1'bz) && SACEFPDAWLEN[0]; // rv 0 + assign SACEFPDAWLEN_in[1] = (SACEFPDAWLEN[1] !== 1'bz) && SACEFPDAWLEN[1]; // rv 0 + assign SACEFPDAWLEN_in[2] = (SACEFPDAWLEN[2] !== 1'bz) && SACEFPDAWLEN[2]; // rv 0 + assign SACEFPDAWLEN_in[3] = (SACEFPDAWLEN[3] !== 1'bz) && SACEFPDAWLEN[3]; // rv 0 + assign SACEFPDAWLEN_in[4] = (SACEFPDAWLEN[4] !== 1'bz) && SACEFPDAWLEN[4]; // rv 0 + assign SACEFPDAWLEN_in[5] = (SACEFPDAWLEN[5] !== 1'bz) && SACEFPDAWLEN[5]; // rv 0 + assign SACEFPDAWLEN_in[6] = (SACEFPDAWLEN[6] !== 1'bz) && SACEFPDAWLEN[6]; // rv 0 + assign SACEFPDAWLEN_in[7] = (SACEFPDAWLEN[7] !== 1'bz) && SACEFPDAWLEN[7]; // rv 0 + assign SACEFPDAWLOCK_in = (SACEFPDAWLOCK !== 1'bz) && SACEFPDAWLOCK; // rv 0 + assign SACEFPDAWPROT_in[0] = (SACEFPDAWPROT[0] !== 1'bz) && SACEFPDAWPROT[0]; // rv 0 + assign SACEFPDAWPROT_in[1] = (SACEFPDAWPROT[1] !== 1'bz) && SACEFPDAWPROT[1]; // rv 0 + assign SACEFPDAWPROT_in[2] = (SACEFPDAWPROT[2] !== 1'bz) && SACEFPDAWPROT[2]; // rv 0 + assign SACEFPDAWQOS_in[0] = (SACEFPDAWQOS[0] !== 1'bz) && SACEFPDAWQOS[0]; // rv 0 + assign SACEFPDAWQOS_in[1] = (SACEFPDAWQOS[1] !== 1'bz) && SACEFPDAWQOS[1]; // rv 0 + assign SACEFPDAWQOS_in[2] = (SACEFPDAWQOS[2] !== 1'bz) && SACEFPDAWQOS[2]; // rv 0 + assign SACEFPDAWQOS_in[3] = (SACEFPDAWQOS[3] !== 1'bz) && SACEFPDAWQOS[3]; // rv 0 + assign SACEFPDAWREGION_in[0] = (SACEFPDAWREGION[0] !== 1'bz) && SACEFPDAWREGION[0]; // rv 0 + assign SACEFPDAWREGION_in[1] = (SACEFPDAWREGION[1] !== 1'bz) && SACEFPDAWREGION[1]; // rv 0 + assign SACEFPDAWREGION_in[2] = (SACEFPDAWREGION[2] !== 1'bz) && SACEFPDAWREGION[2]; // rv 0 + assign SACEFPDAWREGION_in[3] = (SACEFPDAWREGION[3] !== 1'bz) && SACEFPDAWREGION[3]; // rv 0 + assign SACEFPDAWSIZE_in[0] = (SACEFPDAWSIZE[0] !== 1'bz) && SACEFPDAWSIZE[0]; // rv 0 + assign SACEFPDAWSIZE_in[1] = (SACEFPDAWSIZE[1] !== 1'bz) && SACEFPDAWSIZE[1]; // rv 0 + assign SACEFPDAWSIZE_in[2] = (SACEFPDAWSIZE[2] !== 1'bz) && SACEFPDAWSIZE[2]; // rv 0 + assign SACEFPDAWSNOOP_in[0] = (SACEFPDAWSNOOP[0] !== 1'bz) && SACEFPDAWSNOOP[0]; // rv 0 + assign SACEFPDAWSNOOP_in[1] = (SACEFPDAWSNOOP[1] !== 1'bz) && SACEFPDAWSNOOP[1]; // rv 0 + assign SACEFPDAWSNOOP_in[2] = (SACEFPDAWSNOOP[2] !== 1'bz) && SACEFPDAWSNOOP[2]; // rv 0 + assign SACEFPDAWUSER_in[0] = (SACEFPDAWUSER[0] !== 1'bz) && SACEFPDAWUSER[0]; // rv 0 + assign SACEFPDAWUSER_in[10] = (SACEFPDAWUSER[10] !== 1'bz) && SACEFPDAWUSER[10]; // rv 0 + assign SACEFPDAWUSER_in[11] = (SACEFPDAWUSER[11] !== 1'bz) && SACEFPDAWUSER[11]; // rv 0 + assign SACEFPDAWUSER_in[12] = (SACEFPDAWUSER[12] !== 1'bz) && SACEFPDAWUSER[12]; // rv 0 + assign SACEFPDAWUSER_in[13] = (SACEFPDAWUSER[13] !== 1'bz) && SACEFPDAWUSER[13]; // rv 0 + assign SACEFPDAWUSER_in[14] = (SACEFPDAWUSER[14] !== 1'bz) && SACEFPDAWUSER[14]; // rv 0 + assign SACEFPDAWUSER_in[15] = (SACEFPDAWUSER[15] !== 1'bz) && SACEFPDAWUSER[15]; // rv 0 + assign SACEFPDAWUSER_in[1] = (SACEFPDAWUSER[1] !== 1'bz) && SACEFPDAWUSER[1]; // rv 0 + assign SACEFPDAWUSER_in[2] = (SACEFPDAWUSER[2] !== 1'bz) && SACEFPDAWUSER[2]; // rv 0 + assign SACEFPDAWUSER_in[3] = (SACEFPDAWUSER[3] !== 1'bz) && SACEFPDAWUSER[3]; // rv 0 + assign SACEFPDAWUSER_in[4] = (SACEFPDAWUSER[4] !== 1'bz) && SACEFPDAWUSER[4]; // rv 0 + assign SACEFPDAWUSER_in[5] = (SACEFPDAWUSER[5] !== 1'bz) && SACEFPDAWUSER[5]; // rv 0 + assign SACEFPDAWUSER_in[6] = (SACEFPDAWUSER[6] !== 1'bz) && SACEFPDAWUSER[6]; // rv 0 + assign SACEFPDAWUSER_in[7] = (SACEFPDAWUSER[7] !== 1'bz) && SACEFPDAWUSER[7]; // rv 0 + assign SACEFPDAWUSER_in[8] = (SACEFPDAWUSER[8] !== 1'bz) && SACEFPDAWUSER[8]; // rv 0 + assign SACEFPDAWUSER_in[9] = (SACEFPDAWUSER[9] !== 1'bz) && SACEFPDAWUSER[9]; // rv 0 + assign SACEFPDAWVALID_in = (SACEFPDAWVALID !== 1'bz) && SACEFPDAWVALID; // rv 0 + assign SACEFPDBREADY_in = (SACEFPDBREADY !== 1'bz) && SACEFPDBREADY; // rv 0 + assign SACEFPDCDDATA_in[0] = (SACEFPDCDDATA[0] !== 1'bz) && SACEFPDCDDATA[0]; // rv 0 + assign SACEFPDCDDATA_in[100] = (SACEFPDCDDATA[100] !== 1'bz) && SACEFPDCDDATA[100]; // rv 0 + assign SACEFPDCDDATA_in[101] = (SACEFPDCDDATA[101] !== 1'bz) && SACEFPDCDDATA[101]; // rv 0 + assign SACEFPDCDDATA_in[102] = (SACEFPDCDDATA[102] !== 1'bz) && SACEFPDCDDATA[102]; // rv 0 + assign SACEFPDCDDATA_in[103] = (SACEFPDCDDATA[103] !== 1'bz) && SACEFPDCDDATA[103]; // rv 0 + assign SACEFPDCDDATA_in[104] = (SACEFPDCDDATA[104] !== 1'bz) && SACEFPDCDDATA[104]; // rv 0 + assign SACEFPDCDDATA_in[105] = (SACEFPDCDDATA[105] !== 1'bz) && SACEFPDCDDATA[105]; // rv 0 + assign SACEFPDCDDATA_in[106] = (SACEFPDCDDATA[106] !== 1'bz) && SACEFPDCDDATA[106]; // rv 0 + assign SACEFPDCDDATA_in[107] = (SACEFPDCDDATA[107] !== 1'bz) && SACEFPDCDDATA[107]; // rv 0 + assign SACEFPDCDDATA_in[108] = (SACEFPDCDDATA[108] !== 1'bz) && SACEFPDCDDATA[108]; // rv 0 + assign SACEFPDCDDATA_in[109] = (SACEFPDCDDATA[109] !== 1'bz) && SACEFPDCDDATA[109]; // rv 0 + assign SACEFPDCDDATA_in[10] = (SACEFPDCDDATA[10] !== 1'bz) && SACEFPDCDDATA[10]; // rv 0 + assign SACEFPDCDDATA_in[110] = (SACEFPDCDDATA[110] !== 1'bz) && SACEFPDCDDATA[110]; // rv 0 + assign SACEFPDCDDATA_in[111] = (SACEFPDCDDATA[111] !== 1'bz) && SACEFPDCDDATA[111]; // rv 0 + assign SACEFPDCDDATA_in[112] = (SACEFPDCDDATA[112] !== 1'bz) && SACEFPDCDDATA[112]; // rv 0 + assign SACEFPDCDDATA_in[113] = (SACEFPDCDDATA[113] !== 1'bz) && SACEFPDCDDATA[113]; // rv 0 + assign SACEFPDCDDATA_in[114] = (SACEFPDCDDATA[114] !== 1'bz) && SACEFPDCDDATA[114]; // rv 0 + assign SACEFPDCDDATA_in[115] = (SACEFPDCDDATA[115] !== 1'bz) && SACEFPDCDDATA[115]; // rv 0 + assign SACEFPDCDDATA_in[116] = (SACEFPDCDDATA[116] !== 1'bz) && SACEFPDCDDATA[116]; // rv 0 + assign SACEFPDCDDATA_in[117] = (SACEFPDCDDATA[117] !== 1'bz) && SACEFPDCDDATA[117]; // rv 0 + assign SACEFPDCDDATA_in[118] = (SACEFPDCDDATA[118] !== 1'bz) && SACEFPDCDDATA[118]; // rv 0 + assign SACEFPDCDDATA_in[119] = (SACEFPDCDDATA[119] !== 1'bz) && SACEFPDCDDATA[119]; // rv 0 + assign SACEFPDCDDATA_in[11] = (SACEFPDCDDATA[11] !== 1'bz) && SACEFPDCDDATA[11]; // rv 0 + assign SACEFPDCDDATA_in[120] = (SACEFPDCDDATA[120] !== 1'bz) && SACEFPDCDDATA[120]; // rv 0 + assign SACEFPDCDDATA_in[121] = (SACEFPDCDDATA[121] !== 1'bz) && SACEFPDCDDATA[121]; // rv 0 + assign SACEFPDCDDATA_in[122] = (SACEFPDCDDATA[122] !== 1'bz) && SACEFPDCDDATA[122]; // rv 0 + assign SACEFPDCDDATA_in[123] = (SACEFPDCDDATA[123] !== 1'bz) && SACEFPDCDDATA[123]; // rv 0 + assign SACEFPDCDDATA_in[124] = (SACEFPDCDDATA[124] !== 1'bz) && SACEFPDCDDATA[124]; // rv 0 + assign SACEFPDCDDATA_in[125] = (SACEFPDCDDATA[125] !== 1'bz) && SACEFPDCDDATA[125]; // rv 0 + assign SACEFPDCDDATA_in[126] = (SACEFPDCDDATA[126] !== 1'bz) && SACEFPDCDDATA[126]; // rv 0 + assign SACEFPDCDDATA_in[127] = (SACEFPDCDDATA[127] !== 1'bz) && SACEFPDCDDATA[127]; // rv 0 + assign SACEFPDCDDATA_in[12] = (SACEFPDCDDATA[12] !== 1'bz) && SACEFPDCDDATA[12]; // rv 0 + assign SACEFPDCDDATA_in[13] = (SACEFPDCDDATA[13] !== 1'bz) && SACEFPDCDDATA[13]; // rv 0 + assign SACEFPDCDDATA_in[14] = (SACEFPDCDDATA[14] !== 1'bz) && SACEFPDCDDATA[14]; // rv 0 + assign SACEFPDCDDATA_in[15] = (SACEFPDCDDATA[15] !== 1'bz) && SACEFPDCDDATA[15]; // rv 0 + assign SACEFPDCDDATA_in[16] = (SACEFPDCDDATA[16] !== 1'bz) && SACEFPDCDDATA[16]; // rv 0 + assign SACEFPDCDDATA_in[17] = (SACEFPDCDDATA[17] !== 1'bz) && SACEFPDCDDATA[17]; // rv 0 + assign SACEFPDCDDATA_in[18] = (SACEFPDCDDATA[18] !== 1'bz) && SACEFPDCDDATA[18]; // rv 0 + assign SACEFPDCDDATA_in[19] = (SACEFPDCDDATA[19] !== 1'bz) && SACEFPDCDDATA[19]; // rv 0 + assign SACEFPDCDDATA_in[1] = (SACEFPDCDDATA[1] !== 1'bz) && SACEFPDCDDATA[1]; // rv 0 + assign SACEFPDCDDATA_in[20] = (SACEFPDCDDATA[20] !== 1'bz) && SACEFPDCDDATA[20]; // rv 0 + assign SACEFPDCDDATA_in[21] = (SACEFPDCDDATA[21] !== 1'bz) && SACEFPDCDDATA[21]; // rv 0 + assign SACEFPDCDDATA_in[22] = (SACEFPDCDDATA[22] !== 1'bz) && SACEFPDCDDATA[22]; // rv 0 + assign SACEFPDCDDATA_in[23] = (SACEFPDCDDATA[23] !== 1'bz) && SACEFPDCDDATA[23]; // rv 0 + assign SACEFPDCDDATA_in[24] = (SACEFPDCDDATA[24] !== 1'bz) && SACEFPDCDDATA[24]; // rv 0 + assign SACEFPDCDDATA_in[25] = (SACEFPDCDDATA[25] !== 1'bz) && SACEFPDCDDATA[25]; // rv 0 + assign SACEFPDCDDATA_in[26] = (SACEFPDCDDATA[26] !== 1'bz) && SACEFPDCDDATA[26]; // rv 0 + assign SACEFPDCDDATA_in[27] = (SACEFPDCDDATA[27] !== 1'bz) && SACEFPDCDDATA[27]; // rv 0 + assign SACEFPDCDDATA_in[28] = (SACEFPDCDDATA[28] !== 1'bz) && SACEFPDCDDATA[28]; // rv 0 + assign SACEFPDCDDATA_in[29] = (SACEFPDCDDATA[29] !== 1'bz) && SACEFPDCDDATA[29]; // rv 0 + assign SACEFPDCDDATA_in[2] = (SACEFPDCDDATA[2] !== 1'bz) && SACEFPDCDDATA[2]; // rv 0 + assign SACEFPDCDDATA_in[30] = (SACEFPDCDDATA[30] !== 1'bz) && SACEFPDCDDATA[30]; // rv 0 + assign SACEFPDCDDATA_in[31] = (SACEFPDCDDATA[31] !== 1'bz) && SACEFPDCDDATA[31]; // rv 0 + assign SACEFPDCDDATA_in[32] = (SACEFPDCDDATA[32] !== 1'bz) && SACEFPDCDDATA[32]; // rv 0 + assign SACEFPDCDDATA_in[33] = (SACEFPDCDDATA[33] !== 1'bz) && SACEFPDCDDATA[33]; // rv 0 + assign SACEFPDCDDATA_in[34] = (SACEFPDCDDATA[34] !== 1'bz) && SACEFPDCDDATA[34]; // rv 0 + assign SACEFPDCDDATA_in[35] = (SACEFPDCDDATA[35] !== 1'bz) && SACEFPDCDDATA[35]; // rv 0 + assign SACEFPDCDDATA_in[36] = (SACEFPDCDDATA[36] !== 1'bz) && SACEFPDCDDATA[36]; // rv 0 + assign SACEFPDCDDATA_in[37] = (SACEFPDCDDATA[37] !== 1'bz) && SACEFPDCDDATA[37]; // rv 0 + assign SACEFPDCDDATA_in[38] = (SACEFPDCDDATA[38] !== 1'bz) && SACEFPDCDDATA[38]; // rv 0 + assign SACEFPDCDDATA_in[39] = (SACEFPDCDDATA[39] !== 1'bz) && SACEFPDCDDATA[39]; // rv 0 + assign SACEFPDCDDATA_in[3] = (SACEFPDCDDATA[3] !== 1'bz) && SACEFPDCDDATA[3]; // rv 0 + assign SACEFPDCDDATA_in[40] = (SACEFPDCDDATA[40] !== 1'bz) && SACEFPDCDDATA[40]; // rv 0 + assign SACEFPDCDDATA_in[41] = (SACEFPDCDDATA[41] !== 1'bz) && SACEFPDCDDATA[41]; // rv 0 + assign SACEFPDCDDATA_in[42] = (SACEFPDCDDATA[42] !== 1'bz) && SACEFPDCDDATA[42]; // rv 0 + assign SACEFPDCDDATA_in[43] = (SACEFPDCDDATA[43] !== 1'bz) && SACEFPDCDDATA[43]; // rv 0 + assign SACEFPDCDDATA_in[44] = (SACEFPDCDDATA[44] !== 1'bz) && SACEFPDCDDATA[44]; // rv 0 + assign SACEFPDCDDATA_in[45] = (SACEFPDCDDATA[45] !== 1'bz) && SACEFPDCDDATA[45]; // rv 0 + assign SACEFPDCDDATA_in[46] = (SACEFPDCDDATA[46] !== 1'bz) && SACEFPDCDDATA[46]; // rv 0 + assign SACEFPDCDDATA_in[47] = (SACEFPDCDDATA[47] !== 1'bz) && SACEFPDCDDATA[47]; // rv 0 + assign SACEFPDCDDATA_in[48] = (SACEFPDCDDATA[48] !== 1'bz) && SACEFPDCDDATA[48]; // rv 0 + assign SACEFPDCDDATA_in[49] = (SACEFPDCDDATA[49] !== 1'bz) && SACEFPDCDDATA[49]; // rv 0 + assign SACEFPDCDDATA_in[4] = (SACEFPDCDDATA[4] !== 1'bz) && SACEFPDCDDATA[4]; // rv 0 + assign SACEFPDCDDATA_in[50] = (SACEFPDCDDATA[50] !== 1'bz) && SACEFPDCDDATA[50]; // rv 0 + assign SACEFPDCDDATA_in[51] = (SACEFPDCDDATA[51] !== 1'bz) && SACEFPDCDDATA[51]; // rv 0 + assign SACEFPDCDDATA_in[52] = (SACEFPDCDDATA[52] !== 1'bz) && SACEFPDCDDATA[52]; // rv 0 + assign SACEFPDCDDATA_in[53] = (SACEFPDCDDATA[53] !== 1'bz) && SACEFPDCDDATA[53]; // rv 0 + assign SACEFPDCDDATA_in[54] = (SACEFPDCDDATA[54] !== 1'bz) && SACEFPDCDDATA[54]; // rv 0 + assign SACEFPDCDDATA_in[55] = (SACEFPDCDDATA[55] !== 1'bz) && SACEFPDCDDATA[55]; // rv 0 + assign SACEFPDCDDATA_in[56] = (SACEFPDCDDATA[56] !== 1'bz) && SACEFPDCDDATA[56]; // rv 0 + assign SACEFPDCDDATA_in[57] = (SACEFPDCDDATA[57] !== 1'bz) && SACEFPDCDDATA[57]; // rv 0 + assign SACEFPDCDDATA_in[58] = (SACEFPDCDDATA[58] !== 1'bz) && SACEFPDCDDATA[58]; // rv 0 + assign SACEFPDCDDATA_in[59] = (SACEFPDCDDATA[59] !== 1'bz) && SACEFPDCDDATA[59]; // rv 0 + assign SACEFPDCDDATA_in[5] = (SACEFPDCDDATA[5] !== 1'bz) && SACEFPDCDDATA[5]; // rv 0 + assign SACEFPDCDDATA_in[60] = (SACEFPDCDDATA[60] !== 1'bz) && SACEFPDCDDATA[60]; // rv 0 + assign SACEFPDCDDATA_in[61] = (SACEFPDCDDATA[61] !== 1'bz) && SACEFPDCDDATA[61]; // rv 0 + assign SACEFPDCDDATA_in[62] = (SACEFPDCDDATA[62] !== 1'bz) && SACEFPDCDDATA[62]; // rv 0 + assign SACEFPDCDDATA_in[63] = (SACEFPDCDDATA[63] !== 1'bz) && SACEFPDCDDATA[63]; // rv 0 + assign SACEFPDCDDATA_in[64] = (SACEFPDCDDATA[64] !== 1'bz) && SACEFPDCDDATA[64]; // rv 0 + assign SACEFPDCDDATA_in[65] = (SACEFPDCDDATA[65] !== 1'bz) && SACEFPDCDDATA[65]; // rv 0 + assign SACEFPDCDDATA_in[66] = (SACEFPDCDDATA[66] !== 1'bz) && SACEFPDCDDATA[66]; // rv 0 + assign SACEFPDCDDATA_in[67] = (SACEFPDCDDATA[67] !== 1'bz) && SACEFPDCDDATA[67]; // rv 0 + assign SACEFPDCDDATA_in[68] = (SACEFPDCDDATA[68] !== 1'bz) && SACEFPDCDDATA[68]; // rv 0 + assign SACEFPDCDDATA_in[69] = (SACEFPDCDDATA[69] !== 1'bz) && SACEFPDCDDATA[69]; // rv 0 + assign SACEFPDCDDATA_in[6] = (SACEFPDCDDATA[6] !== 1'bz) && SACEFPDCDDATA[6]; // rv 0 + assign SACEFPDCDDATA_in[70] = (SACEFPDCDDATA[70] !== 1'bz) && SACEFPDCDDATA[70]; // rv 0 + assign SACEFPDCDDATA_in[71] = (SACEFPDCDDATA[71] !== 1'bz) && SACEFPDCDDATA[71]; // rv 0 + assign SACEFPDCDDATA_in[72] = (SACEFPDCDDATA[72] !== 1'bz) && SACEFPDCDDATA[72]; // rv 0 + assign SACEFPDCDDATA_in[73] = (SACEFPDCDDATA[73] !== 1'bz) && SACEFPDCDDATA[73]; // rv 0 + assign SACEFPDCDDATA_in[74] = (SACEFPDCDDATA[74] !== 1'bz) && SACEFPDCDDATA[74]; // rv 0 + assign SACEFPDCDDATA_in[75] = (SACEFPDCDDATA[75] !== 1'bz) && SACEFPDCDDATA[75]; // rv 0 + assign SACEFPDCDDATA_in[76] = (SACEFPDCDDATA[76] !== 1'bz) && SACEFPDCDDATA[76]; // rv 0 + assign SACEFPDCDDATA_in[77] = (SACEFPDCDDATA[77] !== 1'bz) && SACEFPDCDDATA[77]; // rv 0 + assign SACEFPDCDDATA_in[78] = (SACEFPDCDDATA[78] !== 1'bz) && SACEFPDCDDATA[78]; // rv 0 + assign SACEFPDCDDATA_in[79] = (SACEFPDCDDATA[79] !== 1'bz) && SACEFPDCDDATA[79]; // rv 0 + assign SACEFPDCDDATA_in[7] = (SACEFPDCDDATA[7] !== 1'bz) && SACEFPDCDDATA[7]; // rv 0 + assign SACEFPDCDDATA_in[80] = (SACEFPDCDDATA[80] !== 1'bz) && SACEFPDCDDATA[80]; // rv 0 + assign SACEFPDCDDATA_in[81] = (SACEFPDCDDATA[81] !== 1'bz) && SACEFPDCDDATA[81]; // rv 0 + assign SACEFPDCDDATA_in[82] = (SACEFPDCDDATA[82] !== 1'bz) && SACEFPDCDDATA[82]; // rv 0 + assign SACEFPDCDDATA_in[83] = (SACEFPDCDDATA[83] !== 1'bz) && SACEFPDCDDATA[83]; // rv 0 + assign SACEFPDCDDATA_in[84] = (SACEFPDCDDATA[84] !== 1'bz) && SACEFPDCDDATA[84]; // rv 0 + assign SACEFPDCDDATA_in[85] = (SACEFPDCDDATA[85] !== 1'bz) && SACEFPDCDDATA[85]; // rv 0 + assign SACEFPDCDDATA_in[86] = (SACEFPDCDDATA[86] !== 1'bz) && SACEFPDCDDATA[86]; // rv 0 + assign SACEFPDCDDATA_in[87] = (SACEFPDCDDATA[87] !== 1'bz) && SACEFPDCDDATA[87]; // rv 0 + assign SACEFPDCDDATA_in[88] = (SACEFPDCDDATA[88] !== 1'bz) && SACEFPDCDDATA[88]; // rv 0 + assign SACEFPDCDDATA_in[89] = (SACEFPDCDDATA[89] !== 1'bz) && SACEFPDCDDATA[89]; // rv 0 + assign SACEFPDCDDATA_in[8] = (SACEFPDCDDATA[8] !== 1'bz) && SACEFPDCDDATA[8]; // rv 0 + assign SACEFPDCDDATA_in[90] = (SACEFPDCDDATA[90] !== 1'bz) && SACEFPDCDDATA[90]; // rv 0 + assign SACEFPDCDDATA_in[91] = (SACEFPDCDDATA[91] !== 1'bz) && SACEFPDCDDATA[91]; // rv 0 + assign SACEFPDCDDATA_in[92] = (SACEFPDCDDATA[92] !== 1'bz) && SACEFPDCDDATA[92]; // rv 0 + assign SACEFPDCDDATA_in[93] = (SACEFPDCDDATA[93] !== 1'bz) && SACEFPDCDDATA[93]; // rv 0 + assign SACEFPDCDDATA_in[94] = (SACEFPDCDDATA[94] !== 1'bz) && SACEFPDCDDATA[94]; // rv 0 + assign SACEFPDCDDATA_in[95] = (SACEFPDCDDATA[95] !== 1'bz) && SACEFPDCDDATA[95]; // rv 0 + assign SACEFPDCDDATA_in[96] = (SACEFPDCDDATA[96] !== 1'bz) && SACEFPDCDDATA[96]; // rv 0 + assign SACEFPDCDDATA_in[97] = (SACEFPDCDDATA[97] !== 1'bz) && SACEFPDCDDATA[97]; // rv 0 + assign SACEFPDCDDATA_in[98] = (SACEFPDCDDATA[98] !== 1'bz) && SACEFPDCDDATA[98]; // rv 0 + assign SACEFPDCDDATA_in[99] = (SACEFPDCDDATA[99] !== 1'bz) && SACEFPDCDDATA[99]; // rv 0 + assign SACEFPDCDDATA_in[9] = (SACEFPDCDDATA[9] !== 1'bz) && SACEFPDCDDATA[9]; // rv 0 + assign SACEFPDCDLAST_in = (SACEFPDCDLAST !== 1'bz) && SACEFPDCDLAST; // rv 0 + assign SACEFPDCDVALID_in = (SACEFPDCDVALID !== 1'bz) && SACEFPDCDVALID; // rv 0 + assign SACEFPDCRRESP_in[0] = (SACEFPDCRRESP[0] !== 1'bz) && SACEFPDCRRESP[0]; // rv 0 + assign SACEFPDCRRESP_in[1] = (SACEFPDCRRESP[1] !== 1'bz) && SACEFPDCRRESP[1]; // rv 0 + assign SACEFPDCRRESP_in[2] = (SACEFPDCRRESP[2] !== 1'bz) && SACEFPDCRRESP[2]; // rv 0 + assign SACEFPDCRRESP_in[3] = (SACEFPDCRRESP[3] !== 1'bz) && SACEFPDCRRESP[3]; // rv 0 + assign SACEFPDCRRESP_in[4] = (SACEFPDCRRESP[4] !== 1'bz) && SACEFPDCRRESP[4]; // rv 0 + assign SACEFPDCRVALID_in = (SACEFPDCRVALID !== 1'bz) && SACEFPDCRVALID; // rv 0 + assign SACEFPDRACK_in = (SACEFPDRACK !== 1'bz) && SACEFPDRACK; // rv 0 + assign SACEFPDRREADY_in = (SACEFPDRREADY !== 1'bz) && SACEFPDRREADY; // rv 0 + assign SACEFPDWACK_in = (SACEFPDWACK !== 1'bz) && SACEFPDWACK; // rv 0 + assign SACEFPDWDATA_in[0] = (SACEFPDWDATA[0] !== 1'bz) && SACEFPDWDATA[0]; // rv 0 + assign SACEFPDWDATA_in[100] = (SACEFPDWDATA[100] !== 1'bz) && SACEFPDWDATA[100]; // rv 0 + assign SACEFPDWDATA_in[101] = (SACEFPDWDATA[101] !== 1'bz) && SACEFPDWDATA[101]; // rv 0 + assign SACEFPDWDATA_in[102] = (SACEFPDWDATA[102] !== 1'bz) && SACEFPDWDATA[102]; // rv 0 + assign SACEFPDWDATA_in[103] = (SACEFPDWDATA[103] !== 1'bz) && SACEFPDWDATA[103]; // rv 0 + assign SACEFPDWDATA_in[104] = (SACEFPDWDATA[104] !== 1'bz) && SACEFPDWDATA[104]; // rv 0 + assign SACEFPDWDATA_in[105] = (SACEFPDWDATA[105] !== 1'bz) && SACEFPDWDATA[105]; // rv 0 + assign SACEFPDWDATA_in[106] = (SACEFPDWDATA[106] !== 1'bz) && SACEFPDWDATA[106]; // rv 0 + assign SACEFPDWDATA_in[107] = (SACEFPDWDATA[107] !== 1'bz) && SACEFPDWDATA[107]; // rv 0 + assign SACEFPDWDATA_in[108] = (SACEFPDWDATA[108] !== 1'bz) && SACEFPDWDATA[108]; // rv 0 + assign SACEFPDWDATA_in[109] = (SACEFPDWDATA[109] !== 1'bz) && SACEFPDWDATA[109]; // rv 0 + assign SACEFPDWDATA_in[10] = (SACEFPDWDATA[10] !== 1'bz) && SACEFPDWDATA[10]; // rv 0 + assign SACEFPDWDATA_in[110] = (SACEFPDWDATA[110] !== 1'bz) && SACEFPDWDATA[110]; // rv 0 + assign SACEFPDWDATA_in[111] = (SACEFPDWDATA[111] !== 1'bz) && SACEFPDWDATA[111]; // rv 0 + assign SACEFPDWDATA_in[112] = (SACEFPDWDATA[112] !== 1'bz) && SACEFPDWDATA[112]; // rv 0 + assign SACEFPDWDATA_in[113] = (SACEFPDWDATA[113] !== 1'bz) && SACEFPDWDATA[113]; // rv 0 + assign SACEFPDWDATA_in[114] = (SACEFPDWDATA[114] !== 1'bz) && SACEFPDWDATA[114]; // rv 0 + assign SACEFPDWDATA_in[115] = (SACEFPDWDATA[115] !== 1'bz) && SACEFPDWDATA[115]; // rv 0 + assign SACEFPDWDATA_in[116] = (SACEFPDWDATA[116] !== 1'bz) && SACEFPDWDATA[116]; // rv 0 + assign SACEFPDWDATA_in[117] = (SACEFPDWDATA[117] !== 1'bz) && SACEFPDWDATA[117]; // rv 0 + assign SACEFPDWDATA_in[118] = (SACEFPDWDATA[118] !== 1'bz) && SACEFPDWDATA[118]; // rv 0 + assign SACEFPDWDATA_in[119] = (SACEFPDWDATA[119] !== 1'bz) && SACEFPDWDATA[119]; // rv 0 + assign SACEFPDWDATA_in[11] = (SACEFPDWDATA[11] !== 1'bz) && SACEFPDWDATA[11]; // rv 0 + assign SACEFPDWDATA_in[120] = (SACEFPDWDATA[120] !== 1'bz) && SACEFPDWDATA[120]; // rv 0 + assign SACEFPDWDATA_in[121] = (SACEFPDWDATA[121] !== 1'bz) && SACEFPDWDATA[121]; // rv 0 + assign SACEFPDWDATA_in[122] = (SACEFPDWDATA[122] !== 1'bz) && SACEFPDWDATA[122]; // rv 0 + assign SACEFPDWDATA_in[123] = (SACEFPDWDATA[123] !== 1'bz) && SACEFPDWDATA[123]; // rv 0 + assign SACEFPDWDATA_in[124] = (SACEFPDWDATA[124] !== 1'bz) && SACEFPDWDATA[124]; // rv 0 + assign SACEFPDWDATA_in[125] = (SACEFPDWDATA[125] !== 1'bz) && SACEFPDWDATA[125]; // rv 0 + assign SACEFPDWDATA_in[126] = (SACEFPDWDATA[126] !== 1'bz) && SACEFPDWDATA[126]; // rv 0 + assign SACEFPDWDATA_in[127] = (SACEFPDWDATA[127] !== 1'bz) && SACEFPDWDATA[127]; // rv 0 + assign SACEFPDWDATA_in[12] = (SACEFPDWDATA[12] !== 1'bz) && SACEFPDWDATA[12]; // rv 0 + assign SACEFPDWDATA_in[13] = (SACEFPDWDATA[13] !== 1'bz) && SACEFPDWDATA[13]; // rv 0 + assign SACEFPDWDATA_in[14] = (SACEFPDWDATA[14] !== 1'bz) && SACEFPDWDATA[14]; // rv 0 + assign SACEFPDWDATA_in[15] = (SACEFPDWDATA[15] !== 1'bz) && SACEFPDWDATA[15]; // rv 0 + assign SACEFPDWDATA_in[16] = (SACEFPDWDATA[16] !== 1'bz) && SACEFPDWDATA[16]; // rv 0 + assign SACEFPDWDATA_in[17] = (SACEFPDWDATA[17] !== 1'bz) && SACEFPDWDATA[17]; // rv 0 + assign SACEFPDWDATA_in[18] = (SACEFPDWDATA[18] !== 1'bz) && SACEFPDWDATA[18]; // rv 0 + assign SACEFPDWDATA_in[19] = (SACEFPDWDATA[19] !== 1'bz) && SACEFPDWDATA[19]; // rv 0 + assign SACEFPDWDATA_in[1] = (SACEFPDWDATA[1] !== 1'bz) && SACEFPDWDATA[1]; // rv 0 + assign SACEFPDWDATA_in[20] = (SACEFPDWDATA[20] !== 1'bz) && SACEFPDWDATA[20]; // rv 0 + assign SACEFPDWDATA_in[21] = (SACEFPDWDATA[21] !== 1'bz) && SACEFPDWDATA[21]; // rv 0 + assign SACEFPDWDATA_in[22] = (SACEFPDWDATA[22] !== 1'bz) && SACEFPDWDATA[22]; // rv 0 + assign SACEFPDWDATA_in[23] = (SACEFPDWDATA[23] !== 1'bz) && SACEFPDWDATA[23]; // rv 0 + assign SACEFPDWDATA_in[24] = (SACEFPDWDATA[24] !== 1'bz) && SACEFPDWDATA[24]; // rv 0 + assign SACEFPDWDATA_in[25] = (SACEFPDWDATA[25] !== 1'bz) && SACEFPDWDATA[25]; // rv 0 + assign SACEFPDWDATA_in[26] = (SACEFPDWDATA[26] !== 1'bz) && SACEFPDWDATA[26]; // rv 0 + assign SACEFPDWDATA_in[27] = (SACEFPDWDATA[27] !== 1'bz) && SACEFPDWDATA[27]; // rv 0 + assign SACEFPDWDATA_in[28] = (SACEFPDWDATA[28] !== 1'bz) && SACEFPDWDATA[28]; // rv 0 + assign SACEFPDWDATA_in[29] = (SACEFPDWDATA[29] !== 1'bz) && SACEFPDWDATA[29]; // rv 0 + assign SACEFPDWDATA_in[2] = (SACEFPDWDATA[2] !== 1'bz) && SACEFPDWDATA[2]; // rv 0 + assign SACEFPDWDATA_in[30] = (SACEFPDWDATA[30] !== 1'bz) && SACEFPDWDATA[30]; // rv 0 + assign SACEFPDWDATA_in[31] = (SACEFPDWDATA[31] !== 1'bz) && SACEFPDWDATA[31]; // rv 0 + assign SACEFPDWDATA_in[32] = (SACEFPDWDATA[32] !== 1'bz) && SACEFPDWDATA[32]; // rv 0 + assign SACEFPDWDATA_in[33] = (SACEFPDWDATA[33] !== 1'bz) && SACEFPDWDATA[33]; // rv 0 + assign SACEFPDWDATA_in[34] = (SACEFPDWDATA[34] !== 1'bz) && SACEFPDWDATA[34]; // rv 0 + assign SACEFPDWDATA_in[35] = (SACEFPDWDATA[35] !== 1'bz) && SACEFPDWDATA[35]; // rv 0 + assign SACEFPDWDATA_in[36] = (SACEFPDWDATA[36] !== 1'bz) && SACEFPDWDATA[36]; // rv 0 + assign SACEFPDWDATA_in[37] = (SACEFPDWDATA[37] !== 1'bz) && SACEFPDWDATA[37]; // rv 0 + assign SACEFPDWDATA_in[38] = (SACEFPDWDATA[38] !== 1'bz) && SACEFPDWDATA[38]; // rv 0 + assign SACEFPDWDATA_in[39] = (SACEFPDWDATA[39] !== 1'bz) && SACEFPDWDATA[39]; // rv 0 + assign SACEFPDWDATA_in[3] = (SACEFPDWDATA[3] !== 1'bz) && SACEFPDWDATA[3]; // rv 0 + assign SACEFPDWDATA_in[40] = (SACEFPDWDATA[40] !== 1'bz) && SACEFPDWDATA[40]; // rv 0 + assign SACEFPDWDATA_in[41] = (SACEFPDWDATA[41] !== 1'bz) && SACEFPDWDATA[41]; // rv 0 + assign SACEFPDWDATA_in[42] = (SACEFPDWDATA[42] !== 1'bz) && SACEFPDWDATA[42]; // rv 0 + assign SACEFPDWDATA_in[43] = (SACEFPDWDATA[43] !== 1'bz) && SACEFPDWDATA[43]; // rv 0 + assign SACEFPDWDATA_in[44] = (SACEFPDWDATA[44] !== 1'bz) && SACEFPDWDATA[44]; // rv 0 + assign SACEFPDWDATA_in[45] = (SACEFPDWDATA[45] !== 1'bz) && SACEFPDWDATA[45]; // rv 0 + assign SACEFPDWDATA_in[46] = (SACEFPDWDATA[46] !== 1'bz) && SACEFPDWDATA[46]; // rv 0 + assign SACEFPDWDATA_in[47] = (SACEFPDWDATA[47] !== 1'bz) && SACEFPDWDATA[47]; // rv 0 + assign SACEFPDWDATA_in[48] = (SACEFPDWDATA[48] !== 1'bz) && SACEFPDWDATA[48]; // rv 0 + assign SACEFPDWDATA_in[49] = (SACEFPDWDATA[49] !== 1'bz) && SACEFPDWDATA[49]; // rv 0 + assign SACEFPDWDATA_in[4] = (SACEFPDWDATA[4] !== 1'bz) && SACEFPDWDATA[4]; // rv 0 + assign SACEFPDWDATA_in[50] = (SACEFPDWDATA[50] !== 1'bz) && SACEFPDWDATA[50]; // rv 0 + assign SACEFPDWDATA_in[51] = (SACEFPDWDATA[51] !== 1'bz) && SACEFPDWDATA[51]; // rv 0 + assign SACEFPDWDATA_in[52] = (SACEFPDWDATA[52] !== 1'bz) && SACEFPDWDATA[52]; // rv 0 + assign SACEFPDWDATA_in[53] = (SACEFPDWDATA[53] !== 1'bz) && SACEFPDWDATA[53]; // rv 0 + assign SACEFPDWDATA_in[54] = (SACEFPDWDATA[54] !== 1'bz) && SACEFPDWDATA[54]; // rv 0 + assign SACEFPDWDATA_in[55] = (SACEFPDWDATA[55] !== 1'bz) && SACEFPDWDATA[55]; // rv 0 + assign SACEFPDWDATA_in[56] = (SACEFPDWDATA[56] !== 1'bz) && SACEFPDWDATA[56]; // rv 0 + assign SACEFPDWDATA_in[57] = (SACEFPDWDATA[57] !== 1'bz) && SACEFPDWDATA[57]; // rv 0 + assign SACEFPDWDATA_in[58] = (SACEFPDWDATA[58] !== 1'bz) && SACEFPDWDATA[58]; // rv 0 + assign SACEFPDWDATA_in[59] = (SACEFPDWDATA[59] !== 1'bz) && SACEFPDWDATA[59]; // rv 0 + assign SACEFPDWDATA_in[5] = (SACEFPDWDATA[5] !== 1'bz) && SACEFPDWDATA[5]; // rv 0 + assign SACEFPDWDATA_in[60] = (SACEFPDWDATA[60] !== 1'bz) && SACEFPDWDATA[60]; // rv 0 + assign SACEFPDWDATA_in[61] = (SACEFPDWDATA[61] !== 1'bz) && SACEFPDWDATA[61]; // rv 0 + assign SACEFPDWDATA_in[62] = (SACEFPDWDATA[62] !== 1'bz) && SACEFPDWDATA[62]; // rv 0 + assign SACEFPDWDATA_in[63] = (SACEFPDWDATA[63] !== 1'bz) && SACEFPDWDATA[63]; // rv 0 + assign SACEFPDWDATA_in[64] = (SACEFPDWDATA[64] !== 1'bz) && SACEFPDWDATA[64]; // rv 0 + assign SACEFPDWDATA_in[65] = (SACEFPDWDATA[65] !== 1'bz) && SACEFPDWDATA[65]; // rv 0 + assign SACEFPDWDATA_in[66] = (SACEFPDWDATA[66] !== 1'bz) && SACEFPDWDATA[66]; // rv 0 + assign SACEFPDWDATA_in[67] = (SACEFPDWDATA[67] !== 1'bz) && SACEFPDWDATA[67]; // rv 0 + assign SACEFPDWDATA_in[68] = (SACEFPDWDATA[68] !== 1'bz) && SACEFPDWDATA[68]; // rv 0 + assign SACEFPDWDATA_in[69] = (SACEFPDWDATA[69] !== 1'bz) && SACEFPDWDATA[69]; // rv 0 + assign SACEFPDWDATA_in[6] = (SACEFPDWDATA[6] !== 1'bz) && SACEFPDWDATA[6]; // rv 0 + assign SACEFPDWDATA_in[70] = (SACEFPDWDATA[70] !== 1'bz) && SACEFPDWDATA[70]; // rv 0 + assign SACEFPDWDATA_in[71] = (SACEFPDWDATA[71] !== 1'bz) && SACEFPDWDATA[71]; // rv 0 + assign SACEFPDWDATA_in[72] = (SACEFPDWDATA[72] !== 1'bz) && SACEFPDWDATA[72]; // rv 0 + assign SACEFPDWDATA_in[73] = (SACEFPDWDATA[73] !== 1'bz) && SACEFPDWDATA[73]; // rv 0 + assign SACEFPDWDATA_in[74] = (SACEFPDWDATA[74] !== 1'bz) && SACEFPDWDATA[74]; // rv 0 + assign SACEFPDWDATA_in[75] = (SACEFPDWDATA[75] !== 1'bz) && SACEFPDWDATA[75]; // rv 0 + assign SACEFPDWDATA_in[76] = (SACEFPDWDATA[76] !== 1'bz) && SACEFPDWDATA[76]; // rv 0 + assign SACEFPDWDATA_in[77] = (SACEFPDWDATA[77] !== 1'bz) && SACEFPDWDATA[77]; // rv 0 + assign SACEFPDWDATA_in[78] = (SACEFPDWDATA[78] !== 1'bz) && SACEFPDWDATA[78]; // rv 0 + assign SACEFPDWDATA_in[79] = (SACEFPDWDATA[79] !== 1'bz) && SACEFPDWDATA[79]; // rv 0 + assign SACEFPDWDATA_in[7] = (SACEFPDWDATA[7] !== 1'bz) && SACEFPDWDATA[7]; // rv 0 + assign SACEFPDWDATA_in[80] = (SACEFPDWDATA[80] !== 1'bz) && SACEFPDWDATA[80]; // rv 0 + assign SACEFPDWDATA_in[81] = (SACEFPDWDATA[81] !== 1'bz) && SACEFPDWDATA[81]; // rv 0 + assign SACEFPDWDATA_in[82] = (SACEFPDWDATA[82] !== 1'bz) && SACEFPDWDATA[82]; // rv 0 + assign SACEFPDWDATA_in[83] = (SACEFPDWDATA[83] !== 1'bz) && SACEFPDWDATA[83]; // rv 0 + assign SACEFPDWDATA_in[84] = (SACEFPDWDATA[84] !== 1'bz) && SACEFPDWDATA[84]; // rv 0 + assign SACEFPDWDATA_in[85] = (SACEFPDWDATA[85] !== 1'bz) && SACEFPDWDATA[85]; // rv 0 + assign SACEFPDWDATA_in[86] = (SACEFPDWDATA[86] !== 1'bz) && SACEFPDWDATA[86]; // rv 0 + assign SACEFPDWDATA_in[87] = (SACEFPDWDATA[87] !== 1'bz) && SACEFPDWDATA[87]; // rv 0 + assign SACEFPDWDATA_in[88] = (SACEFPDWDATA[88] !== 1'bz) && SACEFPDWDATA[88]; // rv 0 + assign SACEFPDWDATA_in[89] = (SACEFPDWDATA[89] !== 1'bz) && SACEFPDWDATA[89]; // rv 0 + assign SACEFPDWDATA_in[8] = (SACEFPDWDATA[8] !== 1'bz) && SACEFPDWDATA[8]; // rv 0 + assign SACEFPDWDATA_in[90] = (SACEFPDWDATA[90] !== 1'bz) && SACEFPDWDATA[90]; // rv 0 + assign SACEFPDWDATA_in[91] = (SACEFPDWDATA[91] !== 1'bz) && SACEFPDWDATA[91]; // rv 0 + assign SACEFPDWDATA_in[92] = (SACEFPDWDATA[92] !== 1'bz) && SACEFPDWDATA[92]; // rv 0 + assign SACEFPDWDATA_in[93] = (SACEFPDWDATA[93] !== 1'bz) && SACEFPDWDATA[93]; // rv 0 + assign SACEFPDWDATA_in[94] = (SACEFPDWDATA[94] !== 1'bz) && SACEFPDWDATA[94]; // rv 0 + assign SACEFPDWDATA_in[95] = (SACEFPDWDATA[95] !== 1'bz) && SACEFPDWDATA[95]; // rv 0 + assign SACEFPDWDATA_in[96] = (SACEFPDWDATA[96] !== 1'bz) && SACEFPDWDATA[96]; // rv 0 + assign SACEFPDWDATA_in[97] = (SACEFPDWDATA[97] !== 1'bz) && SACEFPDWDATA[97]; // rv 0 + assign SACEFPDWDATA_in[98] = (SACEFPDWDATA[98] !== 1'bz) && SACEFPDWDATA[98]; // rv 0 + assign SACEFPDWDATA_in[99] = (SACEFPDWDATA[99] !== 1'bz) && SACEFPDWDATA[99]; // rv 0 + assign SACEFPDWDATA_in[9] = (SACEFPDWDATA[9] !== 1'bz) && SACEFPDWDATA[9]; // rv 0 + assign SACEFPDWLAST_in = (SACEFPDWLAST !== 1'bz) && SACEFPDWLAST; // rv 0 + assign SACEFPDWSTRB_in[0] = (SACEFPDWSTRB[0] !== 1'bz) && SACEFPDWSTRB[0]; // rv 0 + assign SACEFPDWSTRB_in[10] = (SACEFPDWSTRB[10] !== 1'bz) && SACEFPDWSTRB[10]; // rv 0 + assign SACEFPDWSTRB_in[11] = (SACEFPDWSTRB[11] !== 1'bz) && SACEFPDWSTRB[11]; // rv 0 + assign SACEFPDWSTRB_in[12] = (SACEFPDWSTRB[12] !== 1'bz) && SACEFPDWSTRB[12]; // rv 0 + assign SACEFPDWSTRB_in[13] = (SACEFPDWSTRB[13] !== 1'bz) && SACEFPDWSTRB[13]; // rv 0 + assign SACEFPDWSTRB_in[14] = (SACEFPDWSTRB[14] !== 1'bz) && SACEFPDWSTRB[14]; // rv 0 + assign SACEFPDWSTRB_in[15] = (SACEFPDWSTRB[15] !== 1'bz) && SACEFPDWSTRB[15]; // rv 0 + assign SACEFPDWSTRB_in[1] = (SACEFPDWSTRB[1] !== 1'bz) && SACEFPDWSTRB[1]; // rv 0 + assign SACEFPDWSTRB_in[2] = (SACEFPDWSTRB[2] !== 1'bz) && SACEFPDWSTRB[2]; // rv 0 + assign SACEFPDWSTRB_in[3] = (SACEFPDWSTRB[3] !== 1'bz) && SACEFPDWSTRB[3]; // rv 0 + assign SACEFPDWSTRB_in[4] = (SACEFPDWSTRB[4] !== 1'bz) && SACEFPDWSTRB[4]; // rv 0 + assign SACEFPDWSTRB_in[5] = (SACEFPDWSTRB[5] !== 1'bz) && SACEFPDWSTRB[5]; // rv 0 + assign SACEFPDWSTRB_in[6] = (SACEFPDWSTRB[6] !== 1'bz) && SACEFPDWSTRB[6]; // rv 0 + assign SACEFPDWSTRB_in[7] = (SACEFPDWSTRB[7] !== 1'bz) && SACEFPDWSTRB[7]; // rv 0 + assign SACEFPDWSTRB_in[8] = (SACEFPDWSTRB[8] !== 1'bz) && SACEFPDWSTRB[8]; // rv 0 + assign SACEFPDWSTRB_in[9] = (SACEFPDWSTRB[9] !== 1'bz) && SACEFPDWSTRB[9]; // rv 0 + assign SACEFPDWUSER_in = (SACEFPDWUSER !== 1'bz) && SACEFPDWUSER; // rv 0 + assign SACEFPDWVALID_in = (SACEFPDWVALID !== 1'bz) && SACEFPDWVALID; // rv 0 + assign SAXIACPACLK_in = (SAXIACPACLK !== 1'bz) && SAXIACPACLK; // rv 0 + assign SAXIACPARADDR_in[0] = (SAXIACPARADDR[0] !== 1'bz) && SAXIACPARADDR[0]; // rv 0 + assign SAXIACPARADDR_in[10] = (SAXIACPARADDR[10] !== 1'bz) && SAXIACPARADDR[10]; // rv 0 + assign SAXIACPARADDR_in[11] = (SAXIACPARADDR[11] !== 1'bz) && SAXIACPARADDR[11]; // rv 0 + assign SAXIACPARADDR_in[12] = (SAXIACPARADDR[12] !== 1'bz) && SAXIACPARADDR[12]; // rv 0 + assign SAXIACPARADDR_in[13] = (SAXIACPARADDR[13] !== 1'bz) && SAXIACPARADDR[13]; // rv 0 + assign SAXIACPARADDR_in[14] = (SAXIACPARADDR[14] !== 1'bz) && SAXIACPARADDR[14]; // rv 0 + assign SAXIACPARADDR_in[15] = (SAXIACPARADDR[15] !== 1'bz) && SAXIACPARADDR[15]; // rv 0 + assign SAXIACPARADDR_in[16] = (SAXIACPARADDR[16] !== 1'bz) && SAXIACPARADDR[16]; // rv 0 + assign SAXIACPARADDR_in[17] = (SAXIACPARADDR[17] !== 1'bz) && SAXIACPARADDR[17]; // rv 0 + assign SAXIACPARADDR_in[18] = (SAXIACPARADDR[18] !== 1'bz) && SAXIACPARADDR[18]; // rv 0 + assign SAXIACPARADDR_in[19] = (SAXIACPARADDR[19] !== 1'bz) && SAXIACPARADDR[19]; // rv 0 + assign SAXIACPARADDR_in[1] = (SAXIACPARADDR[1] !== 1'bz) && SAXIACPARADDR[1]; // rv 0 + assign SAXIACPARADDR_in[20] = (SAXIACPARADDR[20] !== 1'bz) && SAXIACPARADDR[20]; // rv 0 + assign SAXIACPARADDR_in[21] = (SAXIACPARADDR[21] !== 1'bz) && SAXIACPARADDR[21]; // rv 0 + assign SAXIACPARADDR_in[22] = (SAXIACPARADDR[22] !== 1'bz) && SAXIACPARADDR[22]; // rv 0 + assign SAXIACPARADDR_in[23] = (SAXIACPARADDR[23] !== 1'bz) && SAXIACPARADDR[23]; // rv 0 + assign SAXIACPARADDR_in[24] = (SAXIACPARADDR[24] !== 1'bz) && SAXIACPARADDR[24]; // rv 0 + assign SAXIACPARADDR_in[25] = (SAXIACPARADDR[25] !== 1'bz) && SAXIACPARADDR[25]; // rv 0 + assign SAXIACPARADDR_in[26] = (SAXIACPARADDR[26] !== 1'bz) && SAXIACPARADDR[26]; // rv 0 + assign SAXIACPARADDR_in[27] = (SAXIACPARADDR[27] !== 1'bz) && SAXIACPARADDR[27]; // rv 0 + assign SAXIACPARADDR_in[28] = (SAXIACPARADDR[28] !== 1'bz) && SAXIACPARADDR[28]; // rv 0 + assign SAXIACPARADDR_in[29] = (SAXIACPARADDR[29] !== 1'bz) && SAXIACPARADDR[29]; // rv 0 + assign SAXIACPARADDR_in[2] = (SAXIACPARADDR[2] !== 1'bz) && SAXIACPARADDR[2]; // rv 0 + assign SAXIACPARADDR_in[30] = (SAXIACPARADDR[30] !== 1'bz) && SAXIACPARADDR[30]; // rv 0 + assign SAXIACPARADDR_in[31] = (SAXIACPARADDR[31] !== 1'bz) && SAXIACPARADDR[31]; // rv 0 + assign SAXIACPARADDR_in[32] = (SAXIACPARADDR[32] !== 1'bz) && SAXIACPARADDR[32]; // rv 0 + assign SAXIACPARADDR_in[33] = (SAXIACPARADDR[33] !== 1'bz) && SAXIACPARADDR[33]; // rv 0 + assign SAXIACPARADDR_in[34] = (SAXIACPARADDR[34] !== 1'bz) && SAXIACPARADDR[34]; // rv 0 + assign SAXIACPARADDR_in[35] = (SAXIACPARADDR[35] !== 1'bz) && SAXIACPARADDR[35]; // rv 0 + assign SAXIACPARADDR_in[36] = (SAXIACPARADDR[36] !== 1'bz) && SAXIACPARADDR[36]; // rv 0 + assign SAXIACPARADDR_in[37] = (SAXIACPARADDR[37] !== 1'bz) && SAXIACPARADDR[37]; // rv 0 + assign SAXIACPARADDR_in[38] = (SAXIACPARADDR[38] !== 1'bz) && SAXIACPARADDR[38]; // rv 0 + assign SAXIACPARADDR_in[39] = (SAXIACPARADDR[39] !== 1'bz) && SAXIACPARADDR[39]; // rv 0 + assign SAXIACPARADDR_in[3] = (SAXIACPARADDR[3] !== 1'bz) && SAXIACPARADDR[3]; // rv 0 + assign SAXIACPARADDR_in[4] = (SAXIACPARADDR[4] !== 1'bz) && SAXIACPARADDR[4]; // rv 0 + assign SAXIACPARADDR_in[5] = (SAXIACPARADDR[5] !== 1'bz) && SAXIACPARADDR[5]; // rv 0 + assign SAXIACPARADDR_in[6] = (SAXIACPARADDR[6] !== 1'bz) && SAXIACPARADDR[6]; // rv 0 + assign SAXIACPARADDR_in[7] = (SAXIACPARADDR[7] !== 1'bz) && SAXIACPARADDR[7]; // rv 0 + assign SAXIACPARADDR_in[8] = (SAXIACPARADDR[8] !== 1'bz) && SAXIACPARADDR[8]; // rv 0 + assign SAXIACPARADDR_in[9] = (SAXIACPARADDR[9] !== 1'bz) && SAXIACPARADDR[9]; // rv 0 + assign SAXIACPARBURST_in[0] = (SAXIACPARBURST[0] !== 1'bz) && SAXIACPARBURST[0]; // rv 0 + assign SAXIACPARBURST_in[1] = (SAXIACPARBURST[1] !== 1'bz) && SAXIACPARBURST[1]; // rv 0 + assign SAXIACPARCACHE_in[0] = (SAXIACPARCACHE[0] !== 1'bz) && SAXIACPARCACHE[0]; // rv 0 + assign SAXIACPARCACHE_in[1] = (SAXIACPARCACHE[1] !== 1'bz) && SAXIACPARCACHE[1]; // rv 0 + assign SAXIACPARCACHE_in[2] = (SAXIACPARCACHE[2] !== 1'bz) && SAXIACPARCACHE[2]; // rv 0 + assign SAXIACPARCACHE_in[3] = (SAXIACPARCACHE[3] !== 1'bz) && SAXIACPARCACHE[3]; // rv 0 + assign SAXIACPARID_in[0] = (SAXIACPARID[0] !== 1'bz) && SAXIACPARID[0]; // rv 0 + assign SAXIACPARID_in[1] = (SAXIACPARID[1] !== 1'bz) && SAXIACPARID[1]; // rv 0 + assign SAXIACPARID_in[2] = (SAXIACPARID[2] !== 1'bz) && SAXIACPARID[2]; // rv 0 + assign SAXIACPARID_in[3] = (SAXIACPARID[3] !== 1'bz) && SAXIACPARID[3]; // rv 0 + assign SAXIACPARID_in[4] = (SAXIACPARID[4] !== 1'bz) && SAXIACPARID[4]; // rv 0 + assign SAXIACPARLEN_in[0] = (SAXIACPARLEN[0] !== 1'bz) && SAXIACPARLEN[0]; // rv 0 + assign SAXIACPARLEN_in[1] = (SAXIACPARLEN[1] !== 1'bz) && SAXIACPARLEN[1]; // rv 0 + assign SAXIACPARLEN_in[2] = (SAXIACPARLEN[2] !== 1'bz) && SAXIACPARLEN[2]; // rv 0 + assign SAXIACPARLEN_in[3] = (SAXIACPARLEN[3] !== 1'bz) && SAXIACPARLEN[3]; // rv 0 + assign SAXIACPARLEN_in[4] = (SAXIACPARLEN[4] !== 1'bz) && SAXIACPARLEN[4]; // rv 0 + assign SAXIACPARLEN_in[5] = (SAXIACPARLEN[5] !== 1'bz) && SAXIACPARLEN[5]; // rv 0 + assign SAXIACPARLEN_in[6] = (SAXIACPARLEN[6] !== 1'bz) && SAXIACPARLEN[6]; // rv 0 + assign SAXIACPARLEN_in[7] = (SAXIACPARLEN[7] !== 1'bz) && SAXIACPARLEN[7]; // rv 0 + assign SAXIACPARLOCK_in = (SAXIACPARLOCK !== 1'bz) && SAXIACPARLOCK; // rv 0 + assign SAXIACPARPROT_in[0] = (SAXIACPARPROT[0] !== 1'bz) && SAXIACPARPROT[0]; // rv 0 + assign SAXIACPARPROT_in[1] = (SAXIACPARPROT[1] !== 1'bz) && SAXIACPARPROT[1]; // rv 0 + assign SAXIACPARPROT_in[2] = (SAXIACPARPROT[2] !== 1'bz) && SAXIACPARPROT[2]; // rv 0 + assign SAXIACPARQOS_in[0] = (SAXIACPARQOS[0] !== 1'bz) && SAXIACPARQOS[0]; // rv 0 + assign SAXIACPARQOS_in[1] = (SAXIACPARQOS[1] !== 1'bz) && SAXIACPARQOS[1]; // rv 0 + assign SAXIACPARQOS_in[2] = (SAXIACPARQOS[2] !== 1'bz) && SAXIACPARQOS[2]; // rv 0 + assign SAXIACPARQOS_in[3] = (SAXIACPARQOS[3] !== 1'bz) && SAXIACPARQOS[3]; // rv 0 + assign SAXIACPARSIZE_in[0] = (SAXIACPARSIZE[0] !== 1'bz) && SAXIACPARSIZE[0]; // rv 0 + assign SAXIACPARSIZE_in[1] = (SAXIACPARSIZE[1] !== 1'bz) && SAXIACPARSIZE[1]; // rv 0 + assign SAXIACPARSIZE_in[2] = (SAXIACPARSIZE[2] !== 1'bz) && SAXIACPARSIZE[2]; // rv 0 + assign SAXIACPARUSER_in[0] = (SAXIACPARUSER[0] !== 1'bz) && SAXIACPARUSER[0]; // rv 0 + assign SAXIACPARUSER_in[1] = (SAXIACPARUSER[1] !== 1'bz) && SAXIACPARUSER[1]; // rv 0 + assign SAXIACPARVALID_in = (SAXIACPARVALID !== 1'bz) && SAXIACPARVALID; // rv 0 + assign SAXIACPAWADDR_in[0] = (SAXIACPAWADDR[0] !== 1'bz) && SAXIACPAWADDR[0]; // rv 0 + assign SAXIACPAWADDR_in[10] = (SAXIACPAWADDR[10] !== 1'bz) && SAXIACPAWADDR[10]; // rv 0 + assign SAXIACPAWADDR_in[11] = (SAXIACPAWADDR[11] !== 1'bz) && SAXIACPAWADDR[11]; // rv 0 + assign SAXIACPAWADDR_in[12] = (SAXIACPAWADDR[12] !== 1'bz) && SAXIACPAWADDR[12]; // rv 0 + assign SAXIACPAWADDR_in[13] = (SAXIACPAWADDR[13] !== 1'bz) && SAXIACPAWADDR[13]; // rv 0 + assign SAXIACPAWADDR_in[14] = (SAXIACPAWADDR[14] !== 1'bz) && SAXIACPAWADDR[14]; // rv 0 + assign SAXIACPAWADDR_in[15] = (SAXIACPAWADDR[15] !== 1'bz) && SAXIACPAWADDR[15]; // rv 0 + assign SAXIACPAWADDR_in[16] = (SAXIACPAWADDR[16] !== 1'bz) && SAXIACPAWADDR[16]; // rv 0 + assign SAXIACPAWADDR_in[17] = (SAXIACPAWADDR[17] !== 1'bz) && SAXIACPAWADDR[17]; // rv 0 + assign SAXIACPAWADDR_in[18] = (SAXIACPAWADDR[18] !== 1'bz) && SAXIACPAWADDR[18]; // rv 0 + assign SAXIACPAWADDR_in[19] = (SAXIACPAWADDR[19] !== 1'bz) && SAXIACPAWADDR[19]; // rv 0 + assign SAXIACPAWADDR_in[1] = (SAXIACPAWADDR[1] !== 1'bz) && SAXIACPAWADDR[1]; // rv 0 + assign SAXIACPAWADDR_in[20] = (SAXIACPAWADDR[20] !== 1'bz) && SAXIACPAWADDR[20]; // rv 0 + assign SAXIACPAWADDR_in[21] = (SAXIACPAWADDR[21] !== 1'bz) && SAXIACPAWADDR[21]; // rv 0 + assign SAXIACPAWADDR_in[22] = (SAXIACPAWADDR[22] !== 1'bz) && SAXIACPAWADDR[22]; // rv 0 + assign SAXIACPAWADDR_in[23] = (SAXIACPAWADDR[23] !== 1'bz) && SAXIACPAWADDR[23]; // rv 0 + assign SAXIACPAWADDR_in[24] = (SAXIACPAWADDR[24] !== 1'bz) && SAXIACPAWADDR[24]; // rv 0 + assign SAXIACPAWADDR_in[25] = (SAXIACPAWADDR[25] !== 1'bz) && SAXIACPAWADDR[25]; // rv 0 + assign SAXIACPAWADDR_in[26] = (SAXIACPAWADDR[26] !== 1'bz) && SAXIACPAWADDR[26]; // rv 0 + assign SAXIACPAWADDR_in[27] = (SAXIACPAWADDR[27] !== 1'bz) && SAXIACPAWADDR[27]; // rv 0 + assign SAXIACPAWADDR_in[28] = (SAXIACPAWADDR[28] !== 1'bz) && SAXIACPAWADDR[28]; // rv 0 + assign SAXIACPAWADDR_in[29] = (SAXIACPAWADDR[29] !== 1'bz) && SAXIACPAWADDR[29]; // rv 0 + assign SAXIACPAWADDR_in[2] = (SAXIACPAWADDR[2] !== 1'bz) && SAXIACPAWADDR[2]; // rv 0 + assign SAXIACPAWADDR_in[30] = (SAXIACPAWADDR[30] !== 1'bz) && SAXIACPAWADDR[30]; // rv 0 + assign SAXIACPAWADDR_in[31] = (SAXIACPAWADDR[31] !== 1'bz) && SAXIACPAWADDR[31]; // rv 0 + assign SAXIACPAWADDR_in[32] = (SAXIACPAWADDR[32] !== 1'bz) && SAXIACPAWADDR[32]; // rv 0 + assign SAXIACPAWADDR_in[33] = (SAXIACPAWADDR[33] !== 1'bz) && SAXIACPAWADDR[33]; // rv 0 + assign SAXIACPAWADDR_in[34] = (SAXIACPAWADDR[34] !== 1'bz) && SAXIACPAWADDR[34]; // rv 0 + assign SAXIACPAWADDR_in[35] = (SAXIACPAWADDR[35] !== 1'bz) && SAXIACPAWADDR[35]; // rv 0 + assign SAXIACPAWADDR_in[36] = (SAXIACPAWADDR[36] !== 1'bz) && SAXIACPAWADDR[36]; // rv 0 + assign SAXIACPAWADDR_in[37] = (SAXIACPAWADDR[37] !== 1'bz) && SAXIACPAWADDR[37]; // rv 0 + assign SAXIACPAWADDR_in[38] = (SAXIACPAWADDR[38] !== 1'bz) && SAXIACPAWADDR[38]; // rv 0 + assign SAXIACPAWADDR_in[39] = (SAXIACPAWADDR[39] !== 1'bz) && SAXIACPAWADDR[39]; // rv 0 + assign SAXIACPAWADDR_in[3] = (SAXIACPAWADDR[3] !== 1'bz) && SAXIACPAWADDR[3]; // rv 0 + assign SAXIACPAWADDR_in[4] = (SAXIACPAWADDR[4] !== 1'bz) && SAXIACPAWADDR[4]; // rv 0 + assign SAXIACPAWADDR_in[5] = (SAXIACPAWADDR[5] !== 1'bz) && SAXIACPAWADDR[5]; // rv 0 + assign SAXIACPAWADDR_in[6] = (SAXIACPAWADDR[6] !== 1'bz) && SAXIACPAWADDR[6]; // rv 0 + assign SAXIACPAWADDR_in[7] = (SAXIACPAWADDR[7] !== 1'bz) && SAXIACPAWADDR[7]; // rv 0 + assign SAXIACPAWADDR_in[8] = (SAXIACPAWADDR[8] !== 1'bz) && SAXIACPAWADDR[8]; // rv 0 + assign SAXIACPAWADDR_in[9] = (SAXIACPAWADDR[9] !== 1'bz) && SAXIACPAWADDR[9]; // rv 0 + assign SAXIACPAWBURST_in[0] = (SAXIACPAWBURST[0] !== 1'bz) && SAXIACPAWBURST[0]; // rv 0 + assign SAXIACPAWBURST_in[1] = (SAXIACPAWBURST[1] !== 1'bz) && SAXIACPAWBURST[1]; // rv 0 + assign SAXIACPAWCACHE_in[0] = (SAXIACPAWCACHE[0] !== 1'bz) && SAXIACPAWCACHE[0]; // rv 0 + assign SAXIACPAWCACHE_in[1] = (SAXIACPAWCACHE[1] !== 1'bz) && SAXIACPAWCACHE[1]; // rv 0 + assign SAXIACPAWCACHE_in[2] = (SAXIACPAWCACHE[2] !== 1'bz) && SAXIACPAWCACHE[2]; // rv 0 + assign SAXIACPAWCACHE_in[3] = (SAXIACPAWCACHE[3] !== 1'bz) && SAXIACPAWCACHE[3]; // rv 0 + assign SAXIACPAWID_in[0] = (SAXIACPAWID[0] !== 1'bz) && SAXIACPAWID[0]; // rv 0 + assign SAXIACPAWID_in[1] = (SAXIACPAWID[1] !== 1'bz) && SAXIACPAWID[1]; // rv 0 + assign SAXIACPAWID_in[2] = (SAXIACPAWID[2] !== 1'bz) && SAXIACPAWID[2]; // rv 0 + assign SAXIACPAWID_in[3] = (SAXIACPAWID[3] !== 1'bz) && SAXIACPAWID[3]; // rv 0 + assign SAXIACPAWID_in[4] = (SAXIACPAWID[4] !== 1'bz) && SAXIACPAWID[4]; // rv 0 + assign SAXIACPAWLEN_in[0] = (SAXIACPAWLEN[0] !== 1'bz) && SAXIACPAWLEN[0]; // rv 0 + assign SAXIACPAWLEN_in[1] = (SAXIACPAWLEN[1] !== 1'bz) && SAXIACPAWLEN[1]; // rv 0 + assign SAXIACPAWLEN_in[2] = (SAXIACPAWLEN[2] !== 1'bz) && SAXIACPAWLEN[2]; // rv 0 + assign SAXIACPAWLEN_in[3] = (SAXIACPAWLEN[3] !== 1'bz) && SAXIACPAWLEN[3]; // rv 0 + assign SAXIACPAWLEN_in[4] = (SAXIACPAWLEN[4] !== 1'bz) && SAXIACPAWLEN[4]; // rv 0 + assign SAXIACPAWLEN_in[5] = (SAXIACPAWLEN[5] !== 1'bz) && SAXIACPAWLEN[5]; // rv 0 + assign SAXIACPAWLEN_in[6] = (SAXIACPAWLEN[6] !== 1'bz) && SAXIACPAWLEN[6]; // rv 0 + assign SAXIACPAWLEN_in[7] = (SAXIACPAWLEN[7] !== 1'bz) && SAXIACPAWLEN[7]; // rv 0 + assign SAXIACPAWLOCK_in = (SAXIACPAWLOCK !== 1'bz) && SAXIACPAWLOCK; // rv 0 + assign SAXIACPAWPROT_in[0] = (SAXIACPAWPROT[0] !== 1'bz) && SAXIACPAWPROT[0]; // rv 0 + assign SAXIACPAWPROT_in[1] = (SAXIACPAWPROT[1] !== 1'bz) && SAXIACPAWPROT[1]; // rv 0 + assign SAXIACPAWPROT_in[2] = (SAXIACPAWPROT[2] !== 1'bz) && SAXIACPAWPROT[2]; // rv 0 + assign SAXIACPAWQOS_in[0] = (SAXIACPAWQOS[0] !== 1'bz) && SAXIACPAWQOS[0]; // rv 0 + assign SAXIACPAWQOS_in[1] = (SAXIACPAWQOS[1] !== 1'bz) && SAXIACPAWQOS[1]; // rv 0 + assign SAXIACPAWQOS_in[2] = (SAXIACPAWQOS[2] !== 1'bz) && SAXIACPAWQOS[2]; // rv 0 + assign SAXIACPAWQOS_in[3] = (SAXIACPAWQOS[3] !== 1'bz) && SAXIACPAWQOS[3]; // rv 0 + assign SAXIACPAWSIZE_in[0] = (SAXIACPAWSIZE[0] !== 1'bz) && SAXIACPAWSIZE[0]; // rv 0 + assign SAXIACPAWSIZE_in[1] = (SAXIACPAWSIZE[1] !== 1'bz) && SAXIACPAWSIZE[1]; // rv 0 + assign SAXIACPAWSIZE_in[2] = (SAXIACPAWSIZE[2] !== 1'bz) && SAXIACPAWSIZE[2]; // rv 0 + assign SAXIACPAWUSER_in[0] = (SAXIACPAWUSER[0] !== 1'bz) && SAXIACPAWUSER[0]; // rv 0 + assign SAXIACPAWUSER_in[1] = (SAXIACPAWUSER[1] !== 1'bz) && SAXIACPAWUSER[1]; // rv 0 + assign SAXIACPAWVALID_in = (SAXIACPAWVALID !== 1'bz) && SAXIACPAWVALID; // rv 0 + assign SAXIACPBREADY_in = (SAXIACPBREADY !== 1'bz) && SAXIACPBREADY; // rv 0 + assign SAXIACPRREADY_in = (SAXIACPRREADY !== 1'bz) && SAXIACPRREADY; // rv 0 + assign SAXIACPWDATA_in[0] = (SAXIACPWDATA[0] !== 1'bz) && SAXIACPWDATA[0]; // rv 0 + assign SAXIACPWDATA_in[100] = (SAXIACPWDATA[100] !== 1'bz) && SAXIACPWDATA[100]; // rv 0 + assign SAXIACPWDATA_in[101] = (SAXIACPWDATA[101] !== 1'bz) && SAXIACPWDATA[101]; // rv 0 + assign SAXIACPWDATA_in[102] = (SAXIACPWDATA[102] !== 1'bz) && SAXIACPWDATA[102]; // rv 0 + assign SAXIACPWDATA_in[103] = (SAXIACPWDATA[103] !== 1'bz) && SAXIACPWDATA[103]; // rv 0 + assign SAXIACPWDATA_in[104] = (SAXIACPWDATA[104] !== 1'bz) && SAXIACPWDATA[104]; // rv 0 + assign SAXIACPWDATA_in[105] = (SAXIACPWDATA[105] !== 1'bz) && SAXIACPWDATA[105]; // rv 0 + assign SAXIACPWDATA_in[106] = (SAXIACPWDATA[106] !== 1'bz) && SAXIACPWDATA[106]; // rv 0 + assign SAXIACPWDATA_in[107] = (SAXIACPWDATA[107] !== 1'bz) && SAXIACPWDATA[107]; // rv 0 + assign SAXIACPWDATA_in[108] = (SAXIACPWDATA[108] !== 1'bz) && SAXIACPWDATA[108]; // rv 0 + assign SAXIACPWDATA_in[109] = (SAXIACPWDATA[109] !== 1'bz) && SAXIACPWDATA[109]; // rv 0 + assign SAXIACPWDATA_in[10] = (SAXIACPWDATA[10] !== 1'bz) && SAXIACPWDATA[10]; // rv 0 + assign SAXIACPWDATA_in[110] = (SAXIACPWDATA[110] !== 1'bz) && SAXIACPWDATA[110]; // rv 0 + assign SAXIACPWDATA_in[111] = (SAXIACPWDATA[111] !== 1'bz) && SAXIACPWDATA[111]; // rv 0 + assign SAXIACPWDATA_in[112] = (SAXIACPWDATA[112] !== 1'bz) && SAXIACPWDATA[112]; // rv 0 + assign SAXIACPWDATA_in[113] = (SAXIACPWDATA[113] !== 1'bz) && SAXIACPWDATA[113]; // rv 0 + assign SAXIACPWDATA_in[114] = (SAXIACPWDATA[114] !== 1'bz) && SAXIACPWDATA[114]; // rv 0 + assign SAXIACPWDATA_in[115] = (SAXIACPWDATA[115] !== 1'bz) && SAXIACPWDATA[115]; // rv 0 + assign SAXIACPWDATA_in[116] = (SAXIACPWDATA[116] !== 1'bz) && SAXIACPWDATA[116]; // rv 0 + assign SAXIACPWDATA_in[117] = (SAXIACPWDATA[117] !== 1'bz) && SAXIACPWDATA[117]; // rv 0 + assign SAXIACPWDATA_in[118] = (SAXIACPWDATA[118] !== 1'bz) && SAXIACPWDATA[118]; // rv 0 + assign SAXIACPWDATA_in[119] = (SAXIACPWDATA[119] !== 1'bz) && SAXIACPWDATA[119]; // rv 0 + assign SAXIACPWDATA_in[11] = (SAXIACPWDATA[11] !== 1'bz) && SAXIACPWDATA[11]; // rv 0 + assign SAXIACPWDATA_in[120] = (SAXIACPWDATA[120] !== 1'bz) && SAXIACPWDATA[120]; // rv 0 + assign SAXIACPWDATA_in[121] = (SAXIACPWDATA[121] !== 1'bz) && SAXIACPWDATA[121]; // rv 0 + assign SAXIACPWDATA_in[122] = (SAXIACPWDATA[122] !== 1'bz) && SAXIACPWDATA[122]; // rv 0 + assign SAXIACPWDATA_in[123] = (SAXIACPWDATA[123] !== 1'bz) && SAXIACPWDATA[123]; // rv 0 + assign SAXIACPWDATA_in[124] = (SAXIACPWDATA[124] !== 1'bz) && SAXIACPWDATA[124]; // rv 0 + assign SAXIACPWDATA_in[125] = (SAXIACPWDATA[125] !== 1'bz) && SAXIACPWDATA[125]; // rv 0 + assign SAXIACPWDATA_in[126] = (SAXIACPWDATA[126] !== 1'bz) && SAXIACPWDATA[126]; // rv 0 + assign SAXIACPWDATA_in[127] = (SAXIACPWDATA[127] !== 1'bz) && SAXIACPWDATA[127]; // rv 0 + assign SAXIACPWDATA_in[12] = (SAXIACPWDATA[12] !== 1'bz) && SAXIACPWDATA[12]; // rv 0 + assign SAXIACPWDATA_in[13] = (SAXIACPWDATA[13] !== 1'bz) && SAXIACPWDATA[13]; // rv 0 + assign SAXIACPWDATA_in[14] = (SAXIACPWDATA[14] !== 1'bz) && SAXIACPWDATA[14]; // rv 0 + assign SAXIACPWDATA_in[15] = (SAXIACPWDATA[15] !== 1'bz) && SAXIACPWDATA[15]; // rv 0 + assign SAXIACPWDATA_in[16] = (SAXIACPWDATA[16] !== 1'bz) && SAXIACPWDATA[16]; // rv 0 + assign SAXIACPWDATA_in[17] = (SAXIACPWDATA[17] !== 1'bz) && SAXIACPWDATA[17]; // rv 0 + assign SAXIACPWDATA_in[18] = (SAXIACPWDATA[18] !== 1'bz) && SAXIACPWDATA[18]; // rv 0 + assign SAXIACPWDATA_in[19] = (SAXIACPWDATA[19] !== 1'bz) && SAXIACPWDATA[19]; // rv 0 + assign SAXIACPWDATA_in[1] = (SAXIACPWDATA[1] !== 1'bz) && SAXIACPWDATA[1]; // rv 0 + assign SAXIACPWDATA_in[20] = (SAXIACPWDATA[20] !== 1'bz) && SAXIACPWDATA[20]; // rv 0 + assign SAXIACPWDATA_in[21] = (SAXIACPWDATA[21] !== 1'bz) && SAXIACPWDATA[21]; // rv 0 + assign SAXIACPWDATA_in[22] = (SAXIACPWDATA[22] !== 1'bz) && SAXIACPWDATA[22]; // rv 0 + assign SAXIACPWDATA_in[23] = (SAXIACPWDATA[23] !== 1'bz) && SAXIACPWDATA[23]; // rv 0 + assign SAXIACPWDATA_in[24] = (SAXIACPWDATA[24] !== 1'bz) && SAXIACPWDATA[24]; // rv 0 + assign SAXIACPWDATA_in[25] = (SAXIACPWDATA[25] !== 1'bz) && SAXIACPWDATA[25]; // rv 0 + assign SAXIACPWDATA_in[26] = (SAXIACPWDATA[26] !== 1'bz) && SAXIACPWDATA[26]; // rv 0 + assign SAXIACPWDATA_in[27] = (SAXIACPWDATA[27] !== 1'bz) && SAXIACPWDATA[27]; // rv 0 + assign SAXIACPWDATA_in[28] = (SAXIACPWDATA[28] !== 1'bz) && SAXIACPWDATA[28]; // rv 0 + assign SAXIACPWDATA_in[29] = (SAXIACPWDATA[29] !== 1'bz) && SAXIACPWDATA[29]; // rv 0 + assign SAXIACPWDATA_in[2] = (SAXIACPWDATA[2] !== 1'bz) && SAXIACPWDATA[2]; // rv 0 + assign SAXIACPWDATA_in[30] = (SAXIACPWDATA[30] !== 1'bz) && SAXIACPWDATA[30]; // rv 0 + assign SAXIACPWDATA_in[31] = (SAXIACPWDATA[31] !== 1'bz) && SAXIACPWDATA[31]; // rv 0 + assign SAXIACPWDATA_in[32] = (SAXIACPWDATA[32] !== 1'bz) && SAXIACPWDATA[32]; // rv 0 + assign SAXIACPWDATA_in[33] = (SAXIACPWDATA[33] !== 1'bz) && SAXIACPWDATA[33]; // rv 0 + assign SAXIACPWDATA_in[34] = (SAXIACPWDATA[34] !== 1'bz) && SAXIACPWDATA[34]; // rv 0 + assign SAXIACPWDATA_in[35] = (SAXIACPWDATA[35] !== 1'bz) && SAXIACPWDATA[35]; // rv 0 + assign SAXIACPWDATA_in[36] = (SAXIACPWDATA[36] !== 1'bz) && SAXIACPWDATA[36]; // rv 0 + assign SAXIACPWDATA_in[37] = (SAXIACPWDATA[37] !== 1'bz) && SAXIACPWDATA[37]; // rv 0 + assign SAXIACPWDATA_in[38] = (SAXIACPWDATA[38] !== 1'bz) && SAXIACPWDATA[38]; // rv 0 + assign SAXIACPWDATA_in[39] = (SAXIACPWDATA[39] !== 1'bz) && SAXIACPWDATA[39]; // rv 0 + assign SAXIACPWDATA_in[3] = (SAXIACPWDATA[3] !== 1'bz) && SAXIACPWDATA[3]; // rv 0 + assign SAXIACPWDATA_in[40] = (SAXIACPWDATA[40] !== 1'bz) && SAXIACPWDATA[40]; // rv 0 + assign SAXIACPWDATA_in[41] = (SAXIACPWDATA[41] !== 1'bz) && SAXIACPWDATA[41]; // rv 0 + assign SAXIACPWDATA_in[42] = (SAXIACPWDATA[42] !== 1'bz) && SAXIACPWDATA[42]; // rv 0 + assign SAXIACPWDATA_in[43] = (SAXIACPWDATA[43] !== 1'bz) && SAXIACPWDATA[43]; // rv 0 + assign SAXIACPWDATA_in[44] = (SAXIACPWDATA[44] !== 1'bz) && SAXIACPWDATA[44]; // rv 0 + assign SAXIACPWDATA_in[45] = (SAXIACPWDATA[45] !== 1'bz) && SAXIACPWDATA[45]; // rv 0 + assign SAXIACPWDATA_in[46] = (SAXIACPWDATA[46] !== 1'bz) && SAXIACPWDATA[46]; // rv 0 + assign SAXIACPWDATA_in[47] = (SAXIACPWDATA[47] !== 1'bz) && SAXIACPWDATA[47]; // rv 0 + assign SAXIACPWDATA_in[48] = (SAXIACPWDATA[48] !== 1'bz) && SAXIACPWDATA[48]; // rv 0 + assign SAXIACPWDATA_in[49] = (SAXIACPWDATA[49] !== 1'bz) && SAXIACPWDATA[49]; // rv 0 + assign SAXIACPWDATA_in[4] = (SAXIACPWDATA[4] !== 1'bz) && SAXIACPWDATA[4]; // rv 0 + assign SAXIACPWDATA_in[50] = (SAXIACPWDATA[50] !== 1'bz) && SAXIACPWDATA[50]; // rv 0 + assign SAXIACPWDATA_in[51] = (SAXIACPWDATA[51] !== 1'bz) && SAXIACPWDATA[51]; // rv 0 + assign SAXIACPWDATA_in[52] = (SAXIACPWDATA[52] !== 1'bz) && SAXIACPWDATA[52]; // rv 0 + assign SAXIACPWDATA_in[53] = (SAXIACPWDATA[53] !== 1'bz) && SAXIACPWDATA[53]; // rv 0 + assign SAXIACPWDATA_in[54] = (SAXIACPWDATA[54] !== 1'bz) && SAXIACPWDATA[54]; // rv 0 + assign SAXIACPWDATA_in[55] = (SAXIACPWDATA[55] !== 1'bz) && SAXIACPWDATA[55]; // rv 0 + assign SAXIACPWDATA_in[56] = (SAXIACPWDATA[56] !== 1'bz) && SAXIACPWDATA[56]; // rv 0 + assign SAXIACPWDATA_in[57] = (SAXIACPWDATA[57] !== 1'bz) && SAXIACPWDATA[57]; // rv 0 + assign SAXIACPWDATA_in[58] = (SAXIACPWDATA[58] !== 1'bz) && SAXIACPWDATA[58]; // rv 0 + assign SAXIACPWDATA_in[59] = (SAXIACPWDATA[59] !== 1'bz) && SAXIACPWDATA[59]; // rv 0 + assign SAXIACPWDATA_in[5] = (SAXIACPWDATA[5] !== 1'bz) && SAXIACPWDATA[5]; // rv 0 + assign SAXIACPWDATA_in[60] = (SAXIACPWDATA[60] !== 1'bz) && SAXIACPWDATA[60]; // rv 0 + assign SAXIACPWDATA_in[61] = (SAXIACPWDATA[61] !== 1'bz) && SAXIACPWDATA[61]; // rv 0 + assign SAXIACPWDATA_in[62] = (SAXIACPWDATA[62] !== 1'bz) && SAXIACPWDATA[62]; // rv 0 + assign SAXIACPWDATA_in[63] = (SAXIACPWDATA[63] !== 1'bz) && SAXIACPWDATA[63]; // rv 0 + assign SAXIACPWDATA_in[64] = (SAXIACPWDATA[64] !== 1'bz) && SAXIACPWDATA[64]; // rv 0 + assign SAXIACPWDATA_in[65] = (SAXIACPWDATA[65] !== 1'bz) && SAXIACPWDATA[65]; // rv 0 + assign SAXIACPWDATA_in[66] = (SAXIACPWDATA[66] !== 1'bz) && SAXIACPWDATA[66]; // rv 0 + assign SAXIACPWDATA_in[67] = (SAXIACPWDATA[67] !== 1'bz) && SAXIACPWDATA[67]; // rv 0 + assign SAXIACPWDATA_in[68] = (SAXIACPWDATA[68] !== 1'bz) && SAXIACPWDATA[68]; // rv 0 + assign SAXIACPWDATA_in[69] = (SAXIACPWDATA[69] !== 1'bz) && SAXIACPWDATA[69]; // rv 0 + assign SAXIACPWDATA_in[6] = (SAXIACPWDATA[6] !== 1'bz) && SAXIACPWDATA[6]; // rv 0 + assign SAXIACPWDATA_in[70] = (SAXIACPWDATA[70] !== 1'bz) && SAXIACPWDATA[70]; // rv 0 + assign SAXIACPWDATA_in[71] = (SAXIACPWDATA[71] !== 1'bz) && SAXIACPWDATA[71]; // rv 0 + assign SAXIACPWDATA_in[72] = (SAXIACPWDATA[72] !== 1'bz) && SAXIACPWDATA[72]; // rv 0 + assign SAXIACPWDATA_in[73] = (SAXIACPWDATA[73] !== 1'bz) && SAXIACPWDATA[73]; // rv 0 + assign SAXIACPWDATA_in[74] = (SAXIACPWDATA[74] !== 1'bz) && SAXIACPWDATA[74]; // rv 0 + assign SAXIACPWDATA_in[75] = (SAXIACPWDATA[75] !== 1'bz) && SAXIACPWDATA[75]; // rv 0 + assign SAXIACPWDATA_in[76] = (SAXIACPWDATA[76] !== 1'bz) && SAXIACPWDATA[76]; // rv 0 + assign SAXIACPWDATA_in[77] = (SAXIACPWDATA[77] !== 1'bz) && SAXIACPWDATA[77]; // rv 0 + assign SAXIACPWDATA_in[78] = (SAXIACPWDATA[78] !== 1'bz) && SAXIACPWDATA[78]; // rv 0 + assign SAXIACPWDATA_in[79] = (SAXIACPWDATA[79] !== 1'bz) && SAXIACPWDATA[79]; // rv 0 + assign SAXIACPWDATA_in[7] = (SAXIACPWDATA[7] !== 1'bz) && SAXIACPWDATA[7]; // rv 0 + assign SAXIACPWDATA_in[80] = (SAXIACPWDATA[80] !== 1'bz) && SAXIACPWDATA[80]; // rv 0 + assign SAXIACPWDATA_in[81] = (SAXIACPWDATA[81] !== 1'bz) && SAXIACPWDATA[81]; // rv 0 + assign SAXIACPWDATA_in[82] = (SAXIACPWDATA[82] !== 1'bz) && SAXIACPWDATA[82]; // rv 0 + assign SAXIACPWDATA_in[83] = (SAXIACPWDATA[83] !== 1'bz) && SAXIACPWDATA[83]; // rv 0 + assign SAXIACPWDATA_in[84] = (SAXIACPWDATA[84] !== 1'bz) && SAXIACPWDATA[84]; // rv 0 + assign SAXIACPWDATA_in[85] = (SAXIACPWDATA[85] !== 1'bz) && SAXIACPWDATA[85]; // rv 0 + assign SAXIACPWDATA_in[86] = (SAXIACPWDATA[86] !== 1'bz) && SAXIACPWDATA[86]; // rv 0 + assign SAXIACPWDATA_in[87] = (SAXIACPWDATA[87] !== 1'bz) && SAXIACPWDATA[87]; // rv 0 + assign SAXIACPWDATA_in[88] = (SAXIACPWDATA[88] !== 1'bz) && SAXIACPWDATA[88]; // rv 0 + assign SAXIACPWDATA_in[89] = (SAXIACPWDATA[89] !== 1'bz) && SAXIACPWDATA[89]; // rv 0 + assign SAXIACPWDATA_in[8] = (SAXIACPWDATA[8] !== 1'bz) && SAXIACPWDATA[8]; // rv 0 + assign SAXIACPWDATA_in[90] = (SAXIACPWDATA[90] !== 1'bz) && SAXIACPWDATA[90]; // rv 0 + assign SAXIACPWDATA_in[91] = (SAXIACPWDATA[91] !== 1'bz) && SAXIACPWDATA[91]; // rv 0 + assign SAXIACPWDATA_in[92] = (SAXIACPWDATA[92] !== 1'bz) && SAXIACPWDATA[92]; // rv 0 + assign SAXIACPWDATA_in[93] = (SAXIACPWDATA[93] !== 1'bz) && SAXIACPWDATA[93]; // rv 0 + assign SAXIACPWDATA_in[94] = (SAXIACPWDATA[94] !== 1'bz) && SAXIACPWDATA[94]; // rv 0 + assign SAXIACPWDATA_in[95] = (SAXIACPWDATA[95] !== 1'bz) && SAXIACPWDATA[95]; // rv 0 + assign SAXIACPWDATA_in[96] = (SAXIACPWDATA[96] !== 1'bz) && SAXIACPWDATA[96]; // rv 0 + assign SAXIACPWDATA_in[97] = (SAXIACPWDATA[97] !== 1'bz) && SAXIACPWDATA[97]; // rv 0 + assign SAXIACPWDATA_in[98] = (SAXIACPWDATA[98] !== 1'bz) && SAXIACPWDATA[98]; // rv 0 + assign SAXIACPWDATA_in[99] = (SAXIACPWDATA[99] !== 1'bz) && SAXIACPWDATA[99]; // rv 0 + assign SAXIACPWDATA_in[9] = (SAXIACPWDATA[9] !== 1'bz) && SAXIACPWDATA[9]; // rv 0 + assign SAXIACPWLAST_in = (SAXIACPWLAST !== 1'bz) && SAXIACPWLAST; // rv 0 + assign SAXIACPWSTRB_in[0] = (SAXIACPWSTRB[0] !== 1'bz) && SAXIACPWSTRB[0]; // rv 0 + assign SAXIACPWSTRB_in[10] = (SAXIACPWSTRB[10] !== 1'bz) && SAXIACPWSTRB[10]; // rv 0 + assign SAXIACPWSTRB_in[11] = (SAXIACPWSTRB[11] !== 1'bz) && SAXIACPWSTRB[11]; // rv 0 + assign SAXIACPWSTRB_in[12] = (SAXIACPWSTRB[12] !== 1'bz) && SAXIACPWSTRB[12]; // rv 0 + assign SAXIACPWSTRB_in[13] = (SAXIACPWSTRB[13] !== 1'bz) && SAXIACPWSTRB[13]; // rv 0 + assign SAXIACPWSTRB_in[14] = (SAXIACPWSTRB[14] !== 1'bz) && SAXIACPWSTRB[14]; // rv 0 + assign SAXIACPWSTRB_in[15] = (SAXIACPWSTRB[15] !== 1'bz) && SAXIACPWSTRB[15]; // rv 0 + assign SAXIACPWSTRB_in[1] = (SAXIACPWSTRB[1] !== 1'bz) && SAXIACPWSTRB[1]; // rv 0 + assign SAXIACPWSTRB_in[2] = (SAXIACPWSTRB[2] !== 1'bz) && SAXIACPWSTRB[2]; // rv 0 + assign SAXIACPWSTRB_in[3] = (SAXIACPWSTRB[3] !== 1'bz) && SAXIACPWSTRB[3]; // rv 0 + assign SAXIACPWSTRB_in[4] = (SAXIACPWSTRB[4] !== 1'bz) && SAXIACPWSTRB[4]; // rv 0 + assign SAXIACPWSTRB_in[5] = (SAXIACPWSTRB[5] !== 1'bz) && SAXIACPWSTRB[5]; // rv 0 + assign SAXIACPWSTRB_in[6] = (SAXIACPWSTRB[6] !== 1'bz) && SAXIACPWSTRB[6]; // rv 0 + assign SAXIACPWSTRB_in[7] = (SAXIACPWSTRB[7] !== 1'bz) && SAXIACPWSTRB[7]; // rv 0 + assign SAXIACPWSTRB_in[8] = (SAXIACPWSTRB[8] !== 1'bz) && SAXIACPWSTRB[8]; // rv 0 + assign SAXIACPWSTRB_in[9] = (SAXIACPWSTRB[9] !== 1'bz) && SAXIACPWSTRB[9]; // rv 0 + assign SAXIACPWVALID_in = (SAXIACPWVALID !== 1'bz) && SAXIACPWVALID; // rv 0 + assign SAXIGP0ARADDR_in[0] = (SAXIGP0ARADDR[0] !== 1'bz) && SAXIGP0ARADDR[0]; // rv 0 + assign SAXIGP0ARADDR_in[10] = (SAXIGP0ARADDR[10] !== 1'bz) && SAXIGP0ARADDR[10]; // rv 0 + assign SAXIGP0ARADDR_in[11] = (SAXIGP0ARADDR[11] !== 1'bz) && SAXIGP0ARADDR[11]; // rv 0 + assign SAXIGP0ARADDR_in[12] = (SAXIGP0ARADDR[12] !== 1'bz) && SAXIGP0ARADDR[12]; // rv 0 + assign SAXIGP0ARADDR_in[13] = (SAXIGP0ARADDR[13] !== 1'bz) && SAXIGP0ARADDR[13]; // rv 0 + assign SAXIGP0ARADDR_in[14] = (SAXIGP0ARADDR[14] !== 1'bz) && SAXIGP0ARADDR[14]; // rv 0 + assign SAXIGP0ARADDR_in[15] = (SAXIGP0ARADDR[15] !== 1'bz) && SAXIGP0ARADDR[15]; // rv 0 + assign SAXIGP0ARADDR_in[16] = (SAXIGP0ARADDR[16] !== 1'bz) && SAXIGP0ARADDR[16]; // rv 0 + assign SAXIGP0ARADDR_in[17] = (SAXIGP0ARADDR[17] !== 1'bz) && SAXIGP0ARADDR[17]; // rv 0 + assign SAXIGP0ARADDR_in[18] = (SAXIGP0ARADDR[18] !== 1'bz) && SAXIGP0ARADDR[18]; // rv 0 + assign SAXIGP0ARADDR_in[19] = (SAXIGP0ARADDR[19] !== 1'bz) && SAXIGP0ARADDR[19]; // rv 0 + assign SAXIGP0ARADDR_in[1] = (SAXIGP0ARADDR[1] !== 1'bz) && SAXIGP0ARADDR[1]; // rv 0 + assign SAXIGP0ARADDR_in[20] = (SAXIGP0ARADDR[20] !== 1'bz) && SAXIGP0ARADDR[20]; // rv 0 + assign SAXIGP0ARADDR_in[21] = (SAXIGP0ARADDR[21] !== 1'bz) && SAXIGP0ARADDR[21]; // rv 0 + assign SAXIGP0ARADDR_in[22] = (SAXIGP0ARADDR[22] !== 1'bz) && SAXIGP0ARADDR[22]; // rv 0 + assign SAXIGP0ARADDR_in[23] = (SAXIGP0ARADDR[23] !== 1'bz) && SAXIGP0ARADDR[23]; // rv 0 + assign SAXIGP0ARADDR_in[24] = (SAXIGP0ARADDR[24] !== 1'bz) && SAXIGP0ARADDR[24]; // rv 0 + assign SAXIGP0ARADDR_in[25] = (SAXIGP0ARADDR[25] !== 1'bz) && SAXIGP0ARADDR[25]; // rv 0 + assign SAXIGP0ARADDR_in[26] = (SAXIGP0ARADDR[26] !== 1'bz) && SAXIGP0ARADDR[26]; // rv 0 + assign SAXIGP0ARADDR_in[27] = (SAXIGP0ARADDR[27] !== 1'bz) && SAXIGP0ARADDR[27]; // rv 0 + assign SAXIGP0ARADDR_in[28] = (SAXIGP0ARADDR[28] !== 1'bz) && SAXIGP0ARADDR[28]; // rv 0 + assign SAXIGP0ARADDR_in[29] = (SAXIGP0ARADDR[29] !== 1'bz) && SAXIGP0ARADDR[29]; // rv 0 + assign SAXIGP0ARADDR_in[2] = (SAXIGP0ARADDR[2] !== 1'bz) && SAXIGP0ARADDR[2]; // rv 0 + assign SAXIGP0ARADDR_in[30] = (SAXIGP0ARADDR[30] !== 1'bz) && SAXIGP0ARADDR[30]; // rv 0 + assign SAXIGP0ARADDR_in[31] = (SAXIGP0ARADDR[31] !== 1'bz) && SAXIGP0ARADDR[31]; // rv 0 + assign SAXIGP0ARADDR_in[32] = (SAXIGP0ARADDR[32] !== 1'bz) && SAXIGP0ARADDR[32]; // rv 0 + assign SAXIGP0ARADDR_in[33] = (SAXIGP0ARADDR[33] !== 1'bz) && SAXIGP0ARADDR[33]; // rv 0 + assign SAXIGP0ARADDR_in[34] = (SAXIGP0ARADDR[34] !== 1'bz) && SAXIGP0ARADDR[34]; // rv 0 + assign SAXIGP0ARADDR_in[35] = (SAXIGP0ARADDR[35] !== 1'bz) && SAXIGP0ARADDR[35]; // rv 0 + assign SAXIGP0ARADDR_in[36] = (SAXIGP0ARADDR[36] !== 1'bz) && SAXIGP0ARADDR[36]; // rv 0 + assign SAXIGP0ARADDR_in[37] = (SAXIGP0ARADDR[37] !== 1'bz) && SAXIGP0ARADDR[37]; // rv 0 + assign SAXIGP0ARADDR_in[38] = (SAXIGP0ARADDR[38] !== 1'bz) && SAXIGP0ARADDR[38]; // rv 0 + assign SAXIGP0ARADDR_in[39] = (SAXIGP0ARADDR[39] !== 1'bz) && SAXIGP0ARADDR[39]; // rv 0 + assign SAXIGP0ARADDR_in[3] = (SAXIGP0ARADDR[3] !== 1'bz) && SAXIGP0ARADDR[3]; // rv 0 + assign SAXIGP0ARADDR_in[40] = (SAXIGP0ARADDR[40] !== 1'bz) && SAXIGP0ARADDR[40]; // rv 0 + assign SAXIGP0ARADDR_in[41] = (SAXIGP0ARADDR[41] !== 1'bz) && SAXIGP0ARADDR[41]; // rv 0 + assign SAXIGP0ARADDR_in[42] = (SAXIGP0ARADDR[42] !== 1'bz) && SAXIGP0ARADDR[42]; // rv 0 + assign SAXIGP0ARADDR_in[43] = (SAXIGP0ARADDR[43] !== 1'bz) && SAXIGP0ARADDR[43]; // rv 0 + assign SAXIGP0ARADDR_in[44] = (SAXIGP0ARADDR[44] !== 1'bz) && SAXIGP0ARADDR[44]; // rv 0 + assign SAXIGP0ARADDR_in[45] = (SAXIGP0ARADDR[45] !== 1'bz) && SAXIGP0ARADDR[45]; // rv 0 + assign SAXIGP0ARADDR_in[46] = (SAXIGP0ARADDR[46] !== 1'bz) && SAXIGP0ARADDR[46]; // rv 0 + assign SAXIGP0ARADDR_in[47] = (SAXIGP0ARADDR[47] !== 1'bz) && SAXIGP0ARADDR[47]; // rv 0 + assign SAXIGP0ARADDR_in[48] = (SAXIGP0ARADDR[48] !== 1'bz) && SAXIGP0ARADDR[48]; // rv 0 + assign SAXIGP0ARADDR_in[4] = (SAXIGP0ARADDR[4] !== 1'bz) && SAXIGP0ARADDR[4]; // rv 0 + assign SAXIGP0ARADDR_in[5] = (SAXIGP0ARADDR[5] !== 1'bz) && SAXIGP0ARADDR[5]; // rv 0 + assign SAXIGP0ARADDR_in[6] = (SAXIGP0ARADDR[6] !== 1'bz) && SAXIGP0ARADDR[6]; // rv 0 + assign SAXIGP0ARADDR_in[7] = (SAXIGP0ARADDR[7] !== 1'bz) && SAXIGP0ARADDR[7]; // rv 0 + assign SAXIGP0ARADDR_in[8] = (SAXIGP0ARADDR[8] !== 1'bz) && SAXIGP0ARADDR[8]; // rv 0 + assign SAXIGP0ARADDR_in[9] = (SAXIGP0ARADDR[9] !== 1'bz) && SAXIGP0ARADDR[9]; // rv 0 + assign SAXIGP0ARBURST_in[0] = (SAXIGP0ARBURST[0] !== 1'bz) && SAXIGP0ARBURST[0]; // rv 0 + assign SAXIGP0ARBURST_in[1] = (SAXIGP0ARBURST[1] !== 1'bz) && SAXIGP0ARBURST[1]; // rv 0 + assign SAXIGP0ARCACHE_in[0] = (SAXIGP0ARCACHE[0] !== 1'bz) && SAXIGP0ARCACHE[0]; // rv 0 + assign SAXIGP0ARCACHE_in[1] = (SAXIGP0ARCACHE[1] !== 1'bz) && SAXIGP0ARCACHE[1]; // rv 0 + assign SAXIGP0ARCACHE_in[2] = (SAXIGP0ARCACHE[2] !== 1'bz) && SAXIGP0ARCACHE[2]; // rv 0 + assign SAXIGP0ARCACHE_in[3] = (SAXIGP0ARCACHE[3] !== 1'bz) && SAXIGP0ARCACHE[3]; // rv 0 + assign SAXIGP0ARID_in[0] = (SAXIGP0ARID[0] !== 1'bz) && SAXIGP0ARID[0]; // rv 0 + assign SAXIGP0ARID_in[1] = (SAXIGP0ARID[1] !== 1'bz) && SAXIGP0ARID[1]; // rv 0 + assign SAXIGP0ARID_in[2] = (SAXIGP0ARID[2] !== 1'bz) && SAXIGP0ARID[2]; // rv 0 + assign SAXIGP0ARID_in[3] = (SAXIGP0ARID[3] !== 1'bz) && SAXIGP0ARID[3]; // rv 0 + assign SAXIGP0ARID_in[4] = (SAXIGP0ARID[4] !== 1'bz) && SAXIGP0ARID[4]; // rv 0 + assign SAXIGP0ARID_in[5] = (SAXIGP0ARID[5] !== 1'bz) && SAXIGP0ARID[5]; // rv 0 + assign SAXIGP0ARLEN_in[0] = (SAXIGP0ARLEN[0] !== 1'bz) && SAXIGP0ARLEN[0]; // rv 0 + assign SAXIGP0ARLEN_in[1] = (SAXIGP0ARLEN[1] !== 1'bz) && SAXIGP0ARLEN[1]; // rv 0 + assign SAXIGP0ARLEN_in[2] = (SAXIGP0ARLEN[2] !== 1'bz) && SAXIGP0ARLEN[2]; // rv 0 + assign SAXIGP0ARLEN_in[3] = (SAXIGP0ARLEN[3] !== 1'bz) && SAXIGP0ARLEN[3]; // rv 0 + assign SAXIGP0ARLEN_in[4] = (SAXIGP0ARLEN[4] !== 1'bz) && SAXIGP0ARLEN[4]; // rv 0 + assign SAXIGP0ARLEN_in[5] = (SAXIGP0ARLEN[5] !== 1'bz) && SAXIGP0ARLEN[5]; // rv 0 + assign SAXIGP0ARLEN_in[6] = (SAXIGP0ARLEN[6] !== 1'bz) && SAXIGP0ARLEN[6]; // rv 0 + assign SAXIGP0ARLEN_in[7] = (SAXIGP0ARLEN[7] !== 1'bz) && SAXIGP0ARLEN[7]; // rv 0 + assign SAXIGP0ARLOCK_in = (SAXIGP0ARLOCK !== 1'bz) && SAXIGP0ARLOCK; // rv 0 + assign SAXIGP0ARPROT_in[0] = (SAXIGP0ARPROT[0] !== 1'bz) && SAXIGP0ARPROT[0]; // rv 0 + assign SAXIGP0ARPROT_in[1] = (SAXIGP0ARPROT[1] !== 1'bz) && SAXIGP0ARPROT[1]; // rv 0 + assign SAXIGP0ARPROT_in[2] = (SAXIGP0ARPROT[2] !== 1'bz) && SAXIGP0ARPROT[2]; // rv 0 + assign SAXIGP0ARQOS_in[0] = (SAXIGP0ARQOS[0] !== 1'bz) && SAXIGP0ARQOS[0]; // rv 0 + assign SAXIGP0ARQOS_in[1] = (SAXIGP0ARQOS[1] !== 1'bz) && SAXIGP0ARQOS[1]; // rv 0 + assign SAXIGP0ARQOS_in[2] = (SAXIGP0ARQOS[2] !== 1'bz) && SAXIGP0ARQOS[2]; // rv 0 + assign SAXIGP0ARQOS_in[3] = (SAXIGP0ARQOS[3] !== 1'bz) && SAXIGP0ARQOS[3]; // rv 0 + assign SAXIGP0ARSIZE_in[0] = (SAXIGP0ARSIZE[0] !== 1'bz) && SAXIGP0ARSIZE[0]; // rv 0 + assign SAXIGP0ARSIZE_in[1] = (SAXIGP0ARSIZE[1] !== 1'bz) && SAXIGP0ARSIZE[1]; // rv 0 + assign SAXIGP0ARSIZE_in[2] = (SAXIGP0ARSIZE[2] !== 1'bz) && SAXIGP0ARSIZE[2]; // rv 0 + assign SAXIGP0ARUSER_in = (SAXIGP0ARUSER !== 1'bz) && SAXIGP0ARUSER; // rv 0 + assign SAXIGP0ARVALID_in = (SAXIGP0ARVALID !== 1'bz) && SAXIGP0ARVALID; // rv 0 + assign SAXIGP0AWADDR_in[0] = (SAXIGP0AWADDR[0] !== 1'bz) && SAXIGP0AWADDR[0]; // rv 0 + assign SAXIGP0AWADDR_in[10] = (SAXIGP0AWADDR[10] !== 1'bz) && SAXIGP0AWADDR[10]; // rv 0 + assign SAXIGP0AWADDR_in[11] = (SAXIGP0AWADDR[11] !== 1'bz) && SAXIGP0AWADDR[11]; // rv 0 + assign SAXIGP0AWADDR_in[12] = (SAXIGP0AWADDR[12] !== 1'bz) && SAXIGP0AWADDR[12]; // rv 0 + assign SAXIGP0AWADDR_in[13] = (SAXIGP0AWADDR[13] !== 1'bz) && SAXIGP0AWADDR[13]; // rv 0 + assign SAXIGP0AWADDR_in[14] = (SAXIGP0AWADDR[14] !== 1'bz) && SAXIGP0AWADDR[14]; // rv 0 + assign SAXIGP0AWADDR_in[15] = (SAXIGP0AWADDR[15] !== 1'bz) && SAXIGP0AWADDR[15]; // rv 0 + assign SAXIGP0AWADDR_in[16] = (SAXIGP0AWADDR[16] !== 1'bz) && SAXIGP0AWADDR[16]; // rv 0 + assign SAXIGP0AWADDR_in[17] = (SAXIGP0AWADDR[17] !== 1'bz) && SAXIGP0AWADDR[17]; // rv 0 + assign SAXIGP0AWADDR_in[18] = (SAXIGP0AWADDR[18] !== 1'bz) && SAXIGP0AWADDR[18]; // rv 0 + assign SAXIGP0AWADDR_in[19] = (SAXIGP0AWADDR[19] !== 1'bz) && SAXIGP0AWADDR[19]; // rv 0 + assign SAXIGP0AWADDR_in[1] = (SAXIGP0AWADDR[1] !== 1'bz) && SAXIGP0AWADDR[1]; // rv 0 + assign SAXIGP0AWADDR_in[20] = (SAXIGP0AWADDR[20] !== 1'bz) && SAXIGP0AWADDR[20]; // rv 0 + assign SAXIGP0AWADDR_in[21] = (SAXIGP0AWADDR[21] !== 1'bz) && SAXIGP0AWADDR[21]; // rv 0 + assign SAXIGP0AWADDR_in[22] = (SAXIGP0AWADDR[22] !== 1'bz) && SAXIGP0AWADDR[22]; // rv 0 + assign SAXIGP0AWADDR_in[23] = (SAXIGP0AWADDR[23] !== 1'bz) && SAXIGP0AWADDR[23]; // rv 0 + assign SAXIGP0AWADDR_in[24] = (SAXIGP0AWADDR[24] !== 1'bz) && SAXIGP0AWADDR[24]; // rv 0 + assign SAXIGP0AWADDR_in[25] = (SAXIGP0AWADDR[25] !== 1'bz) && SAXIGP0AWADDR[25]; // rv 0 + assign SAXIGP0AWADDR_in[26] = (SAXIGP0AWADDR[26] !== 1'bz) && SAXIGP0AWADDR[26]; // rv 0 + assign SAXIGP0AWADDR_in[27] = (SAXIGP0AWADDR[27] !== 1'bz) && SAXIGP0AWADDR[27]; // rv 0 + assign SAXIGP0AWADDR_in[28] = (SAXIGP0AWADDR[28] !== 1'bz) && SAXIGP0AWADDR[28]; // rv 0 + assign SAXIGP0AWADDR_in[29] = (SAXIGP0AWADDR[29] !== 1'bz) && SAXIGP0AWADDR[29]; // rv 0 + assign SAXIGP0AWADDR_in[2] = (SAXIGP0AWADDR[2] !== 1'bz) && SAXIGP0AWADDR[2]; // rv 0 + assign SAXIGP0AWADDR_in[30] = (SAXIGP0AWADDR[30] !== 1'bz) && SAXIGP0AWADDR[30]; // rv 0 + assign SAXIGP0AWADDR_in[31] = (SAXIGP0AWADDR[31] !== 1'bz) && SAXIGP0AWADDR[31]; // rv 0 + assign SAXIGP0AWADDR_in[32] = (SAXIGP0AWADDR[32] !== 1'bz) && SAXIGP0AWADDR[32]; // rv 0 + assign SAXIGP0AWADDR_in[33] = (SAXIGP0AWADDR[33] !== 1'bz) && SAXIGP0AWADDR[33]; // rv 0 + assign SAXIGP0AWADDR_in[34] = (SAXIGP0AWADDR[34] !== 1'bz) && SAXIGP0AWADDR[34]; // rv 0 + assign SAXIGP0AWADDR_in[35] = (SAXIGP0AWADDR[35] !== 1'bz) && SAXIGP0AWADDR[35]; // rv 0 + assign SAXIGP0AWADDR_in[36] = (SAXIGP0AWADDR[36] !== 1'bz) && SAXIGP0AWADDR[36]; // rv 0 + assign SAXIGP0AWADDR_in[37] = (SAXIGP0AWADDR[37] !== 1'bz) && SAXIGP0AWADDR[37]; // rv 0 + assign SAXIGP0AWADDR_in[38] = (SAXIGP0AWADDR[38] !== 1'bz) && SAXIGP0AWADDR[38]; // rv 0 + assign SAXIGP0AWADDR_in[39] = (SAXIGP0AWADDR[39] !== 1'bz) && SAXIGP0AWADDR[39]; // rv 0 + assign SAXIGP0AWADDR_in[3] = (SAXIGP0AWADDR[3] !== 1'bz) && SAXIGP0AWADDR[3]; // rv 0 + assign SAXIGP0AWADDR_in[40] = (SAXIGP0AWADDR[40] !== 1'bz) && SAXIGP0AWADDR[40]; // rv 0 + assign SAXIGP0AWADDR_in[41] = (SAXIGP0AWADDR[41] !== 1'bz) && SAXIGP0AWADDR[41]; // rv 0 + assign SAXIGP0AWADDR_in[42] = (SAXIGP0AWADDR[42] !== 1'bz) && SAXIGP0AWADDR[42]; // rv 0 + assign SAXIGP0AWADDR_in[43] = (SAXIGP0AWADDR[43] !== 1'bz) && SAXIGP0AWADDR[43]; // rv 0 + assign SAXIGP0AWADDR_in[44] = (SAXIGP0AWADDR[44] !== 1'bz) && SAXIGP0AWADDR[44]; // rv 0 + assign SAXIGP0AWADDR_in[45] = (SAXIGP0AWADDR[45] !== 1'bz) && SAXIGP0AWADDR[45]; // rv 0 + assign SAXIGP0AWADDR_in[46] = (SAXIGP0AWADDR[46] !== 1'bz) && SAXIGP0AWADDR[46]; // rv 0 + assign SAXIGP0AWADDR_in[47] = (SAXIGP0AWADDR[47] !== 1'bz) && SAXIGP0AWADDR[47]; // rv 0 + assign SAXIGP0AWADDR_in[48] = (SAXIGP0AWADDR[48] !== 1'bz) && SAXIGP0AWADDR[48]; // rv 0 + assign SAXIGP0AWADDR_in[4] = (SAXIGP0AWADDR[4] !== 1'bz) && SAXIGP0AWADDR[4]; // rv 0 + assign SAXIGP0AWADDR_in[5] = (SAXIGP0AWADDR[5] !== 1'bz) && SAXIGP0AWADDR[5]; // rv 0 + assign SAXIGP0AWADDR_in[6] = (SAXIGP0AWADDR[6] !== 1'bz) && SAXIGP0AWADDR[6]; // rv 0 + assign SAXIGP0AWADDR_in[7] = (SAXIGP0AWADDR[7] !== 1'bz) && SAXIGP0AWADDR[7]; // rv 0 + assign SAXIGP0AWADDR_in[8] = (SAXIGP0AWADDR[8] !== 1'bz) && SAXIGP0AWADDR[8]; // rv 0 + assign SAXIGP0AWADDR_in[9] = (SAXIGP0AWADDR[9] !== 1'bz) && SAXIGP0AWADDR[9]; // rv 0 + assign SAXIGP0AWBURST_in[0] = (SAXIGP0AWBURST[0] !== 1'bz) && SAXIGP0AWBURST[0]; // rv 0 + assign SAXIGP0AWBURST_in[1] = (SAXIGP0AWBURST[1] !== 1'bz) && SAXIGP0AWBURST[1]; // rv 0 + assign SAXIGP0AWCACHE_in[0] = (SAXIGP0AWCACHE[0] !== 1'bz) && SAXIGP0AWCACHE[0]; // rv 0 + assign SAXIGP0AWCACHE_in[1] = (SAXIGP0AWCACHE[1] !== 1'bz) && SAXIGP0AWCACHE[1]; // rv 0 + assign SAXIGP0AWCACHE_in[2] = (SAXIGP0AWCACHE[2] !== 1'bz) && SAXIGP0AWCACHE[2]; // rv 0 + assign SAXIGP0AWCACHE_in[3] = (SAXIGP0AWCACHE[3] !== 1'bz) && SAXIGP0AWCACHE[3]; // rv 0 + assign SAXIGP0AWID_in[0] = (SAXIGP0AWID[0] !== 1'bz) && SAXIGP0AWID[0]; // rv 0 + assign SAXIGP0AWID_in[1] = (SAXIGP0AWID[1] !== 1'bz) && SAXIGP0AWID[1]; // rv 0 + assign SAXIGP0AWID_in[2] = (SAXIGP0AWID[2] !== 1'bz) && SAXIGP0AWID[2]; // rv 0 + assign SAXIGP0AWID_in[3] = (SAXIGP0AWID[3] !== 1'bz) && SAXIGP0AWID[3]; // rv 0 + assign SAXIGP0AWID_in[4] = (SAXIGP0AWID[4] !== 1'bz) && SAXIGP0AWID[4]; // rv 0 + assign SAXIGP0AWID_in[5] = (SAXIGP0AWID[5] !== 1'bz) && SAXIGP0AWID[5]; // rv 0 + assign SAXIGP0AWLEN_in[0] = (SAXIGP0AWLEN[0] !== 1'bz) && SAXIGP0AWLEN[0]; // rv 0 + assign SAXIGP0AWLEN_in[1] = (SAXIGP0AWLEN[1] !== 1'bz) && SAXIGP0AWLEN[1]; // rv 0 + assign SAXIGP0AWLEN_in[2] = (SAXIGP0AWLEN[2] !== 1'bz) && SAXIGP0AWLEN[2]; // rv 0 + assign SAXIGP0AWLEN_in[3] = (SAXIGP0AWLEN[3] !== 1'bz) && SAXIGP0AWLEN[3]; // rv 0 + assign SAXIGP0AWLEN_in[4] = (SAXIGP0AWLEN[4] !== 1'bz) && SAXIGP0AWLEN[4]; // rv 0 + assign SAXIGP0AWLEN_in[5] = (SAXIGP0AWLEN[5] !== 1'bz) && SAXIGP0AWLEN[5]; // rv 0 + assign SAXIGP0AWLEN_in[6] = (SAXIGP0AWLEN[6] !== 1'bz) && SAXIGP0AWLEN[6]; // rv 0 + assign SAXIGP0AWLEN_in[7] = (SAXIGP0AWLEN[7] !== 1'bz) && SAXIGP0AWLEN[7]; // rv 0 + assign SAXIGP0AWLOCK_in = (SAXIGP0AWLOCK !== 1'bz) && SAXIGP0AWLOCK; // rv 0 + assign SAXIGP0AWPROT_in[0] = (SAXIGP0AWPROT[0] !== 1'bz) && SAXIGP0AWPROT[0]; // rv 0 + assign SAXIGP0AWPROT_in[1] = (SAXIGP0AWPROT[1] !== 1'bz) && SAXIGP0AWPROT[1]; // rv 0 + assign SAXIGP0AWPROT_in[2] = (SAXIGP0AWPROT[2] !== 1'bz) && SAXIGP0AWPROT[2]; // rv 0 + assign SAXIGP0AWQOS_in[0] = (SAXIGP0AWQOS[0] !== 1'bz) && SAXIGP0AWQOS[0]; // rv 0 + assign SAXIGP0AWQOS_in[1] = (SAXIGP0AWQOS[1] !== 1'bz) && SAXIGP0AWQOS[1]; // rv 0 + assign SAXIGP0AWQOS_in[2] = (SAXIGP0AWQOS[2] !== 1'bz) && SAXIGP0AWQOS[2]; // rv 0 + assign SAXIGP0AWQOS_in[3] = (SAXIGP0AWQOS[3] !== 1'bz) && SAXIGP0AWQOS[3]; // rv 0 + assign SAXIGP0AWSIZE_in[0] = (SAXIGP0AWSIZE[0] !== 1'bz) && SAXIGP0AWSIZE[0]; // rv 0 + assign SAXIGP0AWSIZE_in[1] = (SAXIGP0AWSIZE[1] !== 1'bz) && SAXIGP0AWSIZE[1]; // rv 0 + assign SAXIGP0AWSIZE_in[2] = (SAXIGP0AWSIZE[2] !== 1'bz) && SAXIGP0AWSIZE[2]; // rv 0 + assign SAXIGP0AWUSER_in = (SAXIGP0AWUSER !== 1'bz) && SAXIGP0AWUSER; // rv 0 + assign SAXIGP0AWVALID_in = (SAXIGP0AWVALID !== 1'bz) && SAXIGP0AWVALID; // rv 0 + assign SAXIGP0BREADY_in = (SAXIGP0BREADY !== 1'bz) && SAXIGP0BREADY; // rv 0 + assign SAXIGP0RCLK_in = (SAXIGP0RCLK !== 1'bz) && SAXIGP0RCLK; // rv 0 + assign SAXIGP0RREADY_in = (SAXIGP0RREADY !== 1'bz) && SAXIGP0RREADY; // rv 0 + assign SAXIGP0WCLK_in = (SAXIGP0WCLK !== 1'bz) && SAXIGP0WCLK; // rv 0 + assign SAXIGP0WDATA_in[0] = (SAXIGP0WDATA[0] !== 1'bz) && SAXIGP0WDATA[0]; // rv 0 + assign SAXIGP0WDATA_in[100] = (SAXIGP0WDATA[100] !== 1'bz) && SAXIGP0WDATA[100]; // rv 0 + assign SAXIGP0WDATA_in[101] = (SAXIGP0WDATA[101] !== 1'bz) && SAXIGP0WDATA[101]; // rv 0 + assign SAXIGP0WDATA_in[102] = (SAXIGP0WDATA[102] !== 1'bz) && SAXIGP0WDATA[102]; // rv 0 + assign SAXIGP0WDATA_in[103] = (SAXIGP0WDATA[103] !== 1'bz) && SAXIGP0WDATA[103]; // rv 0 + assign SAXIGP0WDATA_in[104] = (SAXIGP0WDATA[104] !== 1'bz) && SAXIGP0WDATA[104]; // rv 0 + assign SAXIGP0WDATA_in[105] = (SAXIGP0WDATA[105] !== 1'bz) && SAXIGP0WDATA[105]; // rv 0 + assign SAXIGP0WDATA_in[106] = (SAXIGP0WDATA[106] !== 1'bz) && SAXIGP0WDATA[106]; // rv 0 + assign SAXIGP0WDATA_in[107] = (SAXIGP0WDATA[107] !== 1'bz) && SAXIGP0WDATA[107]; // rv 0 + assign SAXIGP0WDATA_in[108] = (SAXIGP0WDATA[108] !== 1'bz) && SAXIGP0WDATA[108]; // rv 0 + assign SAXIGP0WDATA_in[109] = (SAXIGP0WDATA[109] !== 1'bz) && SAXIGP0WDATA[109]; // rv 0 + assign SAXIGP0WDATA_in[10] = (SAXIGP0WDATA[10] !== 1'bz) && SAXIGP0WDATA[10]; // rv 0 + assign SAXIGP0WDATA_in[110] = (SAXIGP0WDATA[110] !== 1'bz) && SAXIGP0WDATA[110]; // rv 0 + assign SAXIGP0WDATA_in[111] = (SAXIGP0WDATA[111] !== 1'bz) && SAXIGP0WDATA[111]; // rv 0 + assign SAXIGP0WDATA_in[112] = (SAXIGP0WDATA[112] !== 1'bz) && SAXIGP0WDATA[112]; // rv 0 + assign SAXIGP0WDATA_in[113] = (SAXIGP0WDATA[113] !== 1'bz) && SAXIGP0WDATA[113]; // rv 0 + assign SAXIGP0WDATA_in[114] = (SAXIGP0WDATA[114] !== 1'bz) && SAXIGP0WDATA[114]; // rv 0 + assign SAXIGP0WDATA_in[115] = (SAXIGP0WDATA[115] !== 1'bz) && SAXIGP0WDATA[115]; // rv 0 + assign SAXIGP0WDATA_in[116] = (SAXIGP0WDATA[116] !== 1'bz) && SAXIGP0WDATA[116]; // rv 0 + assign SAXIGP0WDATA_in[117] = (SAXIGP0WDATA[117] !== 1'bz) && SAXIGP0WDATA[117]; // rv 0 + assign SAXIGP0WDATA_in[118] = (SAXIGP0WDATA[118] !== 1'bz) && SAXIGP0WDATA[118]; // rv 0 + assign SAXIGP0WDATA_in[119] = (SAXIGP0WDATA[119] !== 1'bz) && SAXIGP0WDATA[119]; // rv 0 + assign SAXIGP0WDATA_in[11] = (SAXIGP0WDATA[11] !== 1'bz) && SAXIGP0WDATA[11]; // rv 0 + assign SAXIGP0WDATA_in[120] = (SAXIGP0WDATA[120] !== 1'bz) && SAXIGP0WDATA[120]; // rv 0 + assign SAXIGP0WDATA_in[121] = (SAXIGP0WDATA[121] !== 1'bz) && SAXIGP0WDATA[121]; // rv 0 + assign SAXIGP0WDATA_in[122] = (SAXIGP0WDATA[122] !== 1'bz) && SAXIGP0WDATA[122]; // rv 0 + assign SAXIGP0WDATA_in[123] = (SAXIGP0WDATA[123] !== 1'bz) && SAXIGP0WDATA[123]; // rv 0 + assign SAXIGP0WDATA_in[124] = (SAXIGP0WDATA[124] !== 1'bz) && SAXIGP0WDATA[124]; // rv 0 + assign SAXIGP0WDATA_in[125] = (SAXIGP0WDATA[125] !== 1'bz) && SAXIGP0WDATA[125]; // rv 0 + assign SAXIGP0WDATA_in[126] = (SAXIGP0WDATA[126] !== 1'bz) && SAXIGP0WDATA[126]; // rv 0 + assign SAXIGP0WDATA_in[127] = (SAXIGP0WDATA[127] !== 1'bz) && SAXIGP0WDATA[127]; // rv 0 + assign SAXIGP0WDATA_in[12] = (SAXIGP0WDATA[12] !== 1'bz) && SAXIGP0WDATA[12]; // rv 0 + assign SAXIGP0WDATA_in[13] = (SAXIGP0WDATA[13] !== 1'bz) && SAXIGP0WDATA[13]; // rv 0 + assign SAXIGP0WDATA_in[14] = (SAXIGP0WDATA[14] !== 1'bz) && SAXIGP0WDATA[14]; // rv 0 + assign SAXIGP0WDATA_in[15] = (SAXIGP0WDATA[15] !== 1'bz) && SAXIGP0WDATA[15]; // rv 0 + assign SAXIGP0WDATA_in[16] = (SAXIGP0WDATA[16] !== 1'bz) && SAXIGP0WDATA[16]; // rv 0 + assign SAXIGP0WDATA_in[17] = (SAXIGP0WDATA[17] !== 1'bz) && SAXIGP0WDATA[17]; // rv 0 + assign SAXIGP0WDATA_in[18] = (SAXIGP0WDATA[18] !== 1'bz) && SAXIGP0WDATA[18]; // rv 0 + assign SAXIGP0WDATA_in[19] = (SAXIGP0WDATA[19] !== 1'bz) && SAXIGP0WDATA[19]; // rv 0 + assign SAXIGP0WDATA_in[1] = (SAXIGP0WDATA[1] !== 1'bz) && SAXIGP0WDATA[1]; // rv 0 + assign SAXIGP0WDATA_in[20] = (SAXIGP0WDATA[20] !== 1'bz) && SAXIGP0WDATA[20]; // rv 0 + assign SAXIGP0WDATA_in[21] = (SAXIGP0WDATA[21] !== 1'bz) && SAXIGP0WDATA[21]; // rv 0 + assign SAXIGP0WDATA_in[22] = (SAXIGP0WDATA[22] !== 1'bz) && SAXIGP0WDATA[22]; // rv 0 + assign SAXIGP0WDATA_in[23] = (SAXIGP0WDATA[23] !== 1'bz) && SAXIGP0WDATA[23]; // rv 0 + assign SAXIGP0WDATA_in[24] = (SAXIGP0WDATA[24] !== 1'bz) && SAXIGP0WDATA[24]; // rv 0 + assign SAXIGP0WDATA_in[25] = (SAXIGP0WDATA[25] !== 1'bz) && SAXIGP0WDATA[25]; // rv 0 + assign SAXIGP0WDATA_in[26] = (SAXIGP0WDATA[26] !== 1'bz) && SAXIGP0WDATA[26]; // rv 0 + assign SAXIGP0WDATA_in[27] = (SAXIGP0WDATA[27] !== 1'bz) && SAXIGP0WDATA[27]; // rv 0 + assign SAXIGP0WDATA_in[28] = (SAXIGP0WDATA[28] !== 1'bz) && SAXIGP0WDATA[28]; // rv 0 + assign SAXIGP0WDATA_in[29] = (SAXIGP0WDATA[29] !== 1'bz) && SAXIGP0WDATA[29]; // rv 0 + assign SAXIGP0WDATA_in[2] = (SAXIGP0WDATA[2] !== 1'bz) && SAXIGP0WDATA[2]; // rv 0 + assign SAXIGP0WDATA_in[30] = (SAXIGP0WDATA[30] !== 1'bz) && SAXIGP0WDATA[30]; // rv 0 + assign SAXIGP0WDATA_in[31] = (SAXIGP0WDATA[31] !== 1'bz) && SAXIGP0WDATA[31]; // rv 0 + assign SAXIGP0WDATA_in[32] = (SAXIGP0WDATA[32] !== 1'bz) && SAXIGP0WDATA[32]; // rv 0 + assign SAXIGP0WDATA_in[33] = (SAXIGP0WDATA[33] !== 1'bz) && SAXIGP0WDATA[33]; // rv 0 + assign SAXIGP0WDATA_in[34] = (SAXIGP0WDATA[34] !== 1'bz) && SAXIGP0WDATA[34]; // rv 0 + assign SAXIGP0WDATA_in[35] = (SAXIGP0WDATA[35] !== 1'bz) && SAXIGP0WDATA[35]; // rv 0 + assign SAXIGP0WDATA_in[36] = (SAXIGP0WDATA[36] !== 1'bz) && SAXIGP0WDATA[36]; // rv 0 + assign SAXIGP0WDATA_in[37] = (SAXIGP0WDATA[37] !== 1'bz) && SAXIGP0WDATA[37]; // rv 0 + assign SAXIGP0WDATA_in[38] = (SAXIGP0WDATA[38] !== 1'bz) && SAXIGP0WDATA[38]; // rv 0 + assign SAXIGP0WDATA_in[39] = (SAXIGP0WDATA[39] !== 1'bz) && SAXIGP0WDATA[39]; // rv 0 + assign SAXIGP0WDATA_in[3] = (SAXIGP0WDATA[3] !== 1'bz) && SAXIGP0WDATA[3]; // rv 0 + assign SAXIGP0WDATA_in[40] = (SAXIGP0WDATA[40] !== 1'bz) && SAXIGP0WDATA[40]; // rv 0 + assign SAXIGP0WDATA_in[41] = (SAXIGP0WDATA[41] !== 1'bz) && SAXIGP0WDATA[41]; // rv 0 + assign SAXIGP0WDATA_in[42] = (SAXIGP0WDATA[42] !== 1'bz) && SAXIGP0WDATA[42]; // rv 0 + assign SAXIGP0WDATA_in[43] = (SAXIGP0WDATA[43] !== 1'bz) && SAXIGP0WDATA[43]; // rv 0 + assign SAXIGP0WDATA_in[44] = (SAXIGP0WDATA[44] !== 1'bz) && SAXIGP0WDATA[44]; // rv 0 + assign SAXIGP0WDATA_in[45] = (SAXIGP0WDATA[45] !== 1'bz) && SAXIGP0WDATA[45]; // rv 0 + assign SAXIGP0WDATA_in[46] = (SAXIGP0WDATA[46] !== 1'bz) && SAXIGP0WDATA[46]; // rv 0 + assign SAXIGP0WDATA_in[47] = (SAXIGP0WDATA[47] !== 1'bz) && SAXIGP0WDATA[47]; // rv 0 + assign SAXIGP0WDATA_in[48] = (SAXIGP0WDATA[48] !== 1'bz) && SAXIGP0WDATA[48]; // rv 0 + assign SAXIGP0WDATA_in[49] = (SAXIGP0WDATA[49] !== 1'bz) && SAXIGP0WDATA[49]; // rv 0 + assign SAXIGP0WDATA_in[4] = (SAXIGP0WDATA[4] !== 1'bz) && SAXIGP0WDATA[4]; // rv 0 + assign SAXIGP0WDATA_in[50] = (SAXIGP0WDATA[50] !== 1'bz) && SAXIGP0WDATA[50]; // rv 0 + assign SAXIGP0WDATA_in[51] = (SAXIGP0WDATA[51] !== 1'bz) && SAXIGP0WDATA[51]; // rv 0 + assign SAXIGP0WDATA_in[52] = (SAXIGP0WDATA[52] !== 1'bz) && SAXIGP0WDATA[52]; // rv 0 + assign SAXIGP0WDATA_in[53] = (SAXIGP0WDATA[53] !== 1'bz) && SAXIGP0WDATA[53]; // rv 0 + assign SAXIGP0WDATA_in[54] = (SAXIGP0WDATA[54] !== 1'bz) && SAXIGP0WDATA[54]; // rv 0 + assign SAXIGP0WDATA_in[55] = (SAXIGP0WDATA[55] !== 1'bz) && SAXIGP0WDATA[55]; // rv 0 + assign SAXIGP0WDATA_in[56] = (SAXIGP0WDATA[56] !== 1'bz) && SAXIGP0WDATA[56]; // rv 0 + assign SAXIGP0WDATA_in[57] = (SAXIGP0WDATA[57] !== 1'bz) && SAXIGP0WDATA[57]; // rv 0 + assign SAXIGP0WDATA_in[58] = (SAXIGP0WDATA[58] !== 1'bz) && SAXIGP0WDATA[58]; // rv 0 + assign SAXIGP0WDATA_in[59] = (SAXIGP0WDATA[59] !== 1'bz) && SAXIGP0WDATA[59]; // rv 0 + assign SAXIGP0WDATA_in[5] = (SAXIGP0WDATA[5] !== 1'bz) && SAXIGP0WDATA[5]; // rv 0 + assign SAXIGP0WDATA_in[60] = (SAXIGP0WDATA[60] !== 1'bz) && SAXIGP0WDATA[60]; // rv 0 + assign SAXIGP0WDATA_in[61] = (SAXIGP0WDATA[61] !== 1'bz) && SAXIGP0WDATA[61]; // rv 0 + assign SAXIGP0WDATA_in[62] = (SAXIGP0WDATA[62] !== 1'bz) && SAXIGP0WDATA[62]; // rv 0 + assign SAXIGP0WDATA_in[63] = (SAXIGP0WDATA[63] !== 1'bz) && SAXIGP0WDATA[63]; // rv 0 + assign SAXIGP0WDATA_in[64] = (SAXIGP0WDATA[64] !== 1'bz) && SAXIGP0WDATA[64]; // rv 0 + assign SAXIGP0WDATA_in[65] = (SAXIGP0WDATA[65] !== 1'bz) && SAXIGP0WDATA[65]; // rv 0 + assign SAXIGP0WDATA_in[66] = (SAXIGP0WDATA[66] !== 1'bz) && SAXIGP0WDATA[66]; // rv 0 + assign SAXIGP0WDATA_in[67] = (SAXIGP0WDATA[67] !== 1'bz) && SAXIGP0WDATA[67]; // rv 0 + assign SAXIGP0WDATA_in[68] = (SAXIGP0WDATA[68] !== 1'bz) && SAXIGP0WDATA[68]; // rv 0 + assign SAXIGP0WDATA_in[69] = (SAXIGP0WDATA[69] !== 1'bz) && SAXIGP0WDATA[69]; // rv 0 + assign SAXIGP0WDATA_in[6] = (SAXIGP0WDATA[6] !== 1'bz) && SAXIGP0WDATA[6]; // rv 0 + assign SAXIGP0WDATA_in[70] = (SAXIGP0WDATA[70] !== 1'bz) && SAXIGP0WDATA[70]; // rv 0 + assign SAXIGP0WDATA_in[71] = (SAXIGP0WDATA[71] !== 1'bz) && SAXIGP0WDATA[71]; // rv 0 + assign SAXIGP0WDATA_in[72] = (SAXIGP0WDATA[72] !== 1'bz) && SAXIGP0WDATA[72]; // rv 0 + assign SAXIGP0WDATA_in[73] = (SAXIGP0WDATA[73] !== 1'bz) && SAXIGP0WDATA[73]; // rv 0 + assign SAXIGP0WDATA_in[74] = (SAXIGP0WDATA[74] !== 1'bz) && SAXIGP0WDATA[74]; // rv 0 + assign SAXIGP0WDATA_in[75] = (SAXIGP0WDATA[75] !== 1'bz) && SAXIGP0WDATA[75]; // rv 0 + assign SAXIGP0WDATA_in[76] = (SAXIGP0WDATA[76] !== 1'bz) && SAXIGP0WDATA[76]; // rv 0 + assign SAXIGP0WDATA_in[77] = (SAXIGP0WDATA[77] !== 1'bz) && SAXIGP0WDATA[77]; // rv 0 + assign SAXIGP0WDATA_in[78] = (SAXIGP0WDATA[78] !== 1'bz) && SAXIGP0WDATA[78]; // rv 0 + assign SAXIGP0WDATA_in[79] = (SAXIGP0WDATA[79] !== 1'bz) && SAXIGP0WDATA[79]; // rv 0 + assign SAXIGP0WDATA_in[7] = (SAXIGP0WDATA[7] !== 1'bz) && SAXIGP0WDATA[7]; // rv 0 + assign SAXIGP0WDATA_in[80] = (SAXIGP0WDATA[80] !== 1'bz) && SAXIGP0WDATA[80]; // rv 0 + assign SAXIGP0WDATA_in[81] = (SAXIGP0WDATA[81] !== 1'bz) && SAXIGP0WDATA[81]; // rv 0 + assign SAXIGP0WDATA_in[82] = (SAXIGP0WDATA[82] !== 1'bz) && SAXIGP0WDATA[82]; // rv 0 + assign SAXIGP0WDATA_in[83] = (SAXIGP0WDATA[83] !== 1'bz) && SAXIGP0WDATA[83]; // rv 0 + assign SAXIGP0WDATA_in[84] = (SAXIGP0WDATA[84] !== 1'bz) && SAXIGP0WDATA[84]; // rv 0 + assign SAXIGP0WDATA_in[85] = (SAXIGP0WDATA[85] !== 1'bz) && SAXIGP0WDATA[85]; // rv 0 + assign SAXIGP0WDATA_in[86] = (SAXIGP0WDATA[86] !== 1'bz) && SAXIGP0WDATA[86]; // rv 0 + assign SAXIGP0WDATA_in[87] = (SAXIGP0WDATA[87] !== 1'bz) && SAXIGP0WDATA[87]; // rv 0 + assign SAXIGP0WDATA_in[88] = (SAXIGP0WDATA[88] !== 1'bz) && SAXIGP0WDATA[88]; // rv 0 + assign SAXIGP0WDATA_in[89] = (SAXIGP0WDATA[89] !== 1'bz) && SAXIGP0WDATA[89]; // rv 0 + assign SAXIGP0WDATA_in[8] = (SAXIGP0WDATA[8] !== 1'bz) && SAXIGP0WDATA[8]; // rv 0 + assign SAXIGP0WDATA_in[90] = (SAXIGP0WDATA[90] !== 1'bz) && SAXIGP0WDATA[90]; // rv 0 + assign SAXIGP0WDATA_in[91] = (SAXIGP0WDATA[91] !== 1'bz) && SAXIGP0WDATA[91]; // rv 0 + assign SAXIGP0WDATA_in[92] = (SAXIGP0WDATA[92] !== 1'bz) && SAXIGP0WDATA[92]; // rv 0 + assign SAXIGP0WDATA_in[93] = (SAXIGP0WDATA[93] !== 1'bz) && SAXIGP0WDATA[93]; // rv 0 + assign SAXIGP0WDATA_in[94] = (SAXIGP0WDATA[94] !== 1'bz) && SAXIGP0WDATA[94]; // rv 0 + assign SAXIGP0WDATA_in[95] = (SAXIGP0WDATA[95] !== 1'bz) && SAXIGP0WDATA[95]; // rv 0 + assign SAXIGP0WDATA_in[96] = (SAXIGP0WDATA[96] !== 1'bz) && SAXIGP0WDATA[96]; // rv 0 + assign SAXIGP0WDATA_in[97] = (SAXIGP0WDATA[97] !== 1'bz) && SAXIGP0WDATA[97]; // rv 0 + assign SAXIGP0WDATA_in[98] = (SAXIGP0WDATA[98] !== 1'bz) && SAXIGP0WDATA[98]; // rv 0 + assign SAXIGP0WDATA_in[99] = (SAXIGP0WDATA[99] !== 1'bz) && SAXIGP0WDATA[99]; // rv 0 + assign SAXIGP0WDATA_in[9] = (SAXIGP0WDATA[9] !== 1'bz) && SAXIGP0WDATA[9]; // rv 0 + assign SAXIGP0WLAST_in = (SAXIGP0WLAST !== 1'bz) && SAXIGP0WLAST; // rv 0 + assign SAXIGP0WSTRB_in[0] = (SAXIGP0WSTRB[0] !== 1'bz) && SAXIGP0WSTRB[0]; // rv 0 + assign SAXIGP0WSTRB_in[10] = (SAXIGP0WSTRB[10] !== 1'bz) && SAXIGP0WSTRB[10]; // rv 0 + assign SAXIGP0WSTRB_in[11] = (SAXIGP0WSTRB[11] !== 1'bz) && SAXIGP0WSTRB[11]; // rv 0 + assign SAXIGP0WSTRB_in[12] = (SAXIGP0WSTRB[12] !== 1'bz) && SAXIGP0WSTRB[12]; // rv 0 + assign SAXIGP0WSTRB_in[13] = (SAXIGP0WSTRB[13] !== 1'bz) && SAXIGP0WSTRB[13]; // rv 0 + assign SAXIGP0WSTRB_in[14] = (SAXIGP0WSTRB[14] !== 1'bz) && SAXIGP0WSTRB[14]; // rv 0 + assign SAXIGP0WSTRB_in[15] = (SAXIGP0WSTRB[15] !== 1'bz) && SAXIGP0WSTRB[15]; // rv 0 + assign SAXIGP0WSTRB_in[1] = (SAXIGP0WSTRB[1] !== 1'bz) && SAXIGP0WSTRB[1]; // rv 0 + assign SAXIGP0WSTRB_in[2] = (SAXIGP0WSTRB[2] !== 1'bz) && SAXIGP0WSTRB[2]; // rv 0 + assign SAXIGP0WSTRB_in[3] = (SAXIGP0WSTRB[3] !== 1'bz) && SAXIGP0WSTRB[3]; // rv 0 + assign SAXIGP0WSTRB_in[4] = (SAXIGP0WSTRB[4] !== 1'bz) && SAXIGP0WSTRB[4]; // rv 0 + assign SAXIGP0WSTRB_in[5] = (SAXIGP0WSTRB[5] !== 1'bz) && SAXIGP0WSTRB[5]; // rv 0 + assign SAXIGP0WSTRB_in[6] = (SAXIGP0WSTRB[6] !== 1'bz) && SAXIGP0WSTRB[6]; // rv 0 + assign SAXIGP0WSTRB_in[7] = (SAXIGP0WSTRB[7] !== 1'bz) && SAXIGP0WSTRB[7]; // rv 0 + assign SAXIGP0WSTRB_in[8] = (SAXIGP0WSTRB[8] !== 1'bz) && SAXIGP0WSTRB[8]; // rv 0 + assign SAXIGP0WSTRB_in[9] = (SAXIGP0WSTRB[9] !== 1'bz) && SAXIGP0WSTRB[9]; // rv 0 + assign SAXIGP0WVALID_in = (SAXIGP0WVALID !== 1'bz) && SAXIGP0WVALID; // rv 0 + assign SAXIGP1ARADDR_in[0] = (SAXIGP1ARADDR[0] !== 1'bz) && SAXIGP1ARADDR[0]; // rv 0 + assign SAXIGP1ARADDR_in[10] = (SAXIGP1ARADDR[10] !== 1'bz) && SAXIGP1ARADDR[10]; // rv 0 + assign SAXIGP1ARADDR_in[11] = (SAXIGP1ARADDR[11] !== 1'bz) && SAXIGP1ARADDR[11]; // rv 0 + assign SAXIGP1ARADDR_in[12] = (SAXIGP1ARADDR[12] !== 1'bz) && SAXIGP1ARADDR[12]; // rv 0 + assign SAXIGP1ARADDR_in[13] = (SAXIGP1ARADDR[13] !== 1'bz) && SAXIGP1ARADDR[13]; // rv 0 + assign SAXIGP1ARADDR_in[14] = (SAXIGP1ARADDR[14] !== 1'bz) && SAXIGP1ARADDR[14]; // rv 0 + assign SAXIGP1ARADDR_in[15] = (SAXIGP1ARADDR[15] !== 1'bz) && SAXIGP1ARADDR[15]; // rv 0 + assign SAXIGP1ARADDR_in[16] = (SAXIGP1ARADDR[16] !== 1'bz) && SAXIGP1ARADDR[16]; // rv 0 + assign SAXIGP1ARADDR_in[17] = (SAXIGP1ARADDR[17] !== 1'bz) && SAXIGP1ARADDR[17]; // rv 0 + assign SAXIGP1ARADDR_in[18] = (SAXIGP1ARADDR[18] !== 1'bz) && SAXIGP1ARADDR[18]; // rv 0 + assign SAXIGP1ARADDR_in[19] = (SAXIGP1ARADDR[19] !== 1'bz) && SAXIGP1ARADDR[19]; // rv 0 + assign SAXIGP1ARADDR_in[1] = (SAXIGP1ARADDR[1] !== 1'bz) && SAXIGP1ARADDR[1]; // rv 0 + assign SAXIGP1ARADDR_in[20] = (SAXIGP1ARADDR[20] !== 1'bz) && SAXIGP1ARADDR[20]; // rv 0 + assign SAXIGP1ARADDR_in[21] = (SAXIGP1ARADDR[21] !== 1'bz) && SAXIGP1ARADDR[21]; // rv 0 + assign SAXIGP1ARADDR_in[22] = (SAXIGP1ARADDR[22] !== 1'bz) && SAXIGP1ARADDR[22]; // rv 0 + assign SAXIGP1ARADDR_in[23] = (SAXIGP1ARADDR[23] !== 1'bz) && SAXIGP1ARADDR[23]; // rv 0 + assign SAXIGP1ARADDR_in[24] = (SAXIGP1ARADDR[24] !== 1'bz) && SAXIGP1ARADDR[24]; // rv 0 + assign SAXIGP1ARADDR_in[25] = (SAXIGP1ARADDR[25] !== 1'bz) && SAXIGP1ARADDR[25]; // rv 0 + assign SAXIGP1ARADDR_in[26] = (SAXIGP1ARADDR[26] !== 1'bz) && SAXIGP1ARADDR[26]; // rv 0 + assign SAXIGP1ARADDR_in[27] = (SAXIGP1ARADDR[27] !== 1'bz) && SAXIGP1ARADDR[27]; // rv 0 + assign SAXIGP1ARADDR_in[28] = (SAXIGP1ARADDR[28] !== 1'bz) && SAXIGP1ARADDR[28]; // rv 0 + assign SAXIGP1ARADDR_in[29] = (SAXIGP1ARADDR[29] !== 1'bz) && SAXIGP1ARADDR[29]; // rv 0 + assign SAXIGP1ARADDR_in[2] = (SAXIGP1ARADDR[2] !== 1'bz) && SAXIGP1ARADDR[2]; // rv 0 + assign SAXIGP1ARADDR_in[30] = (SAXIGP1ARADDR[30] !== 1'bz) && SAXIGP1ARADDR[30]; // rv 0 + assign SAXIGP1ARADDR_in[31] = (SAXIGP1ARADDR[31] !== 1'bz) && SAXIGP1ARADDR[31]; // rv 0 + assign SAXIGP1ARADDR_in[32] = (SAXIGP1ARADDR[32] !== 1'bz) && SAXIGP1ARADDR[32]; // rv 0 + assign SAXIGP1ARADDR_in[33] = (SAXIGP1ARADDR[33] !== 1'bz) && SAXIGP1ARADDR[33]; // rv 0 + assign SAXIGP1ARADDR_in[34] = (SAXIGP1ARADDR[34] !== 1'bz) && SAXIGP1ARADDR[34]; // rv 0 + assign SAXIGP1ARADDR_in[35] = (SAXIGP1ARADDR[35] !== 1'bz) && SAXIGP1ARADDR[35]; // rv 0 + assign SAXIGP1ARADDR_in[36] = (SAXIGP1ARADDR[36] !== 1'bz) && SAXIGP1ARADDR[36]; // rv 0 + assign SAXIGP1ARADDR_in[37] = (SAXIGP1ARADDR[37] !== 1'bz) && SAXIGP1ARADDR[37]; // rv 0 + assign SAXIGP1ARADDR_in[38] = (SAXIGP1ARADDR[38] !== 1'bz) && SAXIGP1ARADDR[38]; // rv 0 + assign SAXIGP1ARADDR_in[39] = (SAXIGP1ARADDR[39] !== 1'bz) && SAXIGP1ARADDR[39]; // rv 0 + assign SAXIGP1ARADDR_in[3] = (SAXIGP1ARADDR[3] !== 1'bz) && SAXIGP1ARADDR[3]; // rv 0 + assign SAXIGP1ARADDR_in[40] = (SAXIGP1ARADDR[40] !== 1'bz) && SAXIGP1ARADDR[40]; // rv 0 + assign SAXIGP1ARADDR_in[41] = (SAXIGP1ARADDR[41] !== 1'bz) && SAXIGP1ARADDR[41]; // rv 0 + assign SAXIGP1ARADDR_in[42] = (SAXIGP1ARADDR[42] !== 1'bz) && SAXIGP1ARADDR[42]; // rv 0 + assign SAXIGP1ARADDR_in[43] = (SAXIGP1ARADDR[43] !== 1'bz) && SAXIGP1ARADDR[43]; // rv 0 + assign SAXIGP1ARADDR_in[44] = (SAXIGP1ARADDR[44] !== 1'bz) && SAXIGP1ARADDR[44]; // rv 0 + assign SAXIGP1ARADDR_in[45] = (SAXIGP1ARADDR[45] !== 1'bz) && SAXIGP1ARADDR[45]; // rv 0 + assign SAXIGP1ARADDR_in[46] = (SAXIGP1ARADDR[46] !== 1'bz) && SAXIGP1ARADDR[46]; // rv 0 + assign SAXIGP1ARADDR_in[47] = (SAXIGP1ARADDR[47] !== 1'bz) && SAXIGP1ARADDR[47]; // rv 0 + assign SAXIGP1ARADDR_in[48] = (SAXIGP1ARADDR[48] !== 1'bz) && SAXIGP1ARADDR[48]; // rv 0 + assign SAXIGP1ARADDR_in[4] = (SAXIGP1ARADDR[4] !== 1'bz) && SAXIGP1ARADDR[4]; // rv 0 + assign SAXIGP1ARADDR_in[5] = (SAXIGP1ARADDR[5] !== 1'bz) && SAXIGP1ARADDR[5]; // rv 0 + assign SAXIGP1ARADDR_in[6] = (SAXIGP1ARADDR[6] !== 1'bz) && SAXIGP1ARADDR[6]; // rv 0 + assign SAXIGP1ARADDR_in[7] = (SAXIGP1ARADDR[7] !== 1'bz) && SAXIGP1ARADDR[7]; // rv 0 + assign SAXIGP1ARADDR_in[8] = (SAXIGP1ARADDR[8] !== 1'bz) && SAXIGP1ARADDR[8]; // rv 0 + assign SAXIGP1ARADDR_in[9] = (SAXIGP1ARADDR[9] !== 1'bz) && SAXIGP1ARADDR[9]; // rv 0 + assign SAXIGP1ARBURST_in[0] = (SAXIGP1ARBURST[0] !== 1'bz) && SAXIGP1ARBURST[0]; // rv 0 + assign SAXIGP1ARBURST_in[1] = (SAXIGP1ARBURST[1] !== 1'bz) && SAXIGP1ARBURST[1]; // rv 0 + assign SAXIGP1ARCACHE_in[0] = (SAXIGP1ARCACHE[0] !== 1'bz) && SAXIGP1ARCACHE[0]; // rv 0 + assign SAXIGP1ARCACHE_in[1] = (SAXIGP1ARCACHE[1] !== 1'bz) && SAXIGP1ARCACHE[1]; // rv 0 + assign SAXIGP1ARCACHE_in[2] = (SAXIGP1ARCACHE[2] !== 1'bz) && SAXIGP1ARCACHE[2]; // rv 0 + assign SAXIGP1ARCACHE_in[3] = (SAXIGP1ARCACHE[3] !== 1'bz) && SAXIGP1ARCACHE[3]; // rv 0 + assign SAXIGP1ARID_in[0] = (SAXIGP1ARID[0] !== 1'bz) && SAXIGP1ARID[0]; // rv 0 + assign SAXIGP1ARID_in[1] = (SAXIGP1ARID[1] !== 1'bz) && SAXIGP1ARID[1]; // rv 0 + assign SAXIGP1ARID_in[2] = (SAXIGP1ARID[2] !== 1'bz) && SAXIGP1ARID[2]; // rv 0 + assign SAXIGP1ARID_in[3] = (SAXIGP1ARID[3] !== 1'bz) && SAXIGP1ARID[3]; // rv 0 + assign SAXIGP1ARID_in[4] = (SAXIGP1ARID[4] !== 1'bz) && SAXIGP1ARID[4]; // rv 0 + assign SAXIGP1ARID_in[5] = (SAXIGP1ARID[5] !== 1'bz) && SAXIGP1ARID[5]; // rv 0 + assign SAXIGP1ARLEN_in[0] = (SAXIGP1ARLEN[0] !== 1'bz) && SAXIGP1ARLEN[0]; // rv 0 + assign SAXIGP1ARLEN_in[1] = (SAXIGP1ARLEN[1] !== 1'bz) && SAXIGP1ARLEN[1]; // rv 0 + assign SAXIGP1ARLEN_in[2] = (SAXIGP1ARLEN[2] !== 1'bz) && SAXIGP1ARLEN[2]; // rv 0 + assign SAXIGP1ARLEN_in[3] = (SAXIGP1ARLEN[3] !== 1'bz) && SAXIGP1ARLEN[3]; // rv 0 + assign SAXIGP1ARLEN_in[4] = (SAXIGP1ARLEN[4] !== 1'bz) && SAXIGP1ARLEN[4]; // rv 0 + assign SAXIGP1ARLEN_in[5] = (SAXIGP1ARLEN[5] !== 1'bz) && SAXIGP1ARLEN[5]; // rv 0 + assign SAXIGP1ARLEN_in[6] = (SAXIGP1ARLEN[6] !== 1'bz) && SAXIGP1ARLEN[6]; // rv 0 + assign SAXIGP1ARLEN_in[7] = (SAXIGP1ARLEN[7] !== 1'bz) && SAXIGP1ARLEN[7]; // rv 0 + assign SAXIGP1ARLOCK_in = (SAXIGP1ARLOCK !== 1'bz) && SAXIGP1ARLOCK; // rv 0 + assign SAXIGP1ARPROT_in[0] = (SAXIGP1ARPROT[0] !== 1'bz) && SAXIGP1ARPROT[0]; // rv 0 + assign SAXIGP1ARPROT_in[1] = (SAXIGP1ARPROT[1] !== 1'bz) && SAXIGP1ARPROT[1]; // rv 0 + assign SAXIGP1ARPROT_in[2] = (SAXIGP1ARPROT[2] !== 1'bz) && SAXIGP1ARPROT[2]; // rv 0 + assign SAXIGP1ARQOS_in[0] = (SAXIGP1ARQOS[0] !== 1'bz) && SAXIGP1ARQOS[0]; // rv 0 + assign SAXIGP1ARQOS_in[1] = (SAXIGP1ARQOS[1] !== 1'bz) && SAXIGP1ARQOS[1]; // rv 0 + assign SAXIGP1ARQOS_in[2] = (SAXIGP1ARQOS[2] !== 1'bz) && SAXIGP1ARQOS[2]; // rv 0 + assign SAXIGP1ARQOS_in[3] = (SAXIGP1ARQOS[3] !== 1'bz) && SAXIGP1ARQOS[3]; // rv 0 + assign SAXIGP1ARSIZE_in[0] = (SAXIGP1ARSIZE[0] !== 1'bz) && SAXIGP1ARSIZE[0]; // rv 0 + assign SAXIGP1ARSIZE_in[1] = (SAXIGP1ARSIZE[1] !== 1'bz) && SAXIGP1ARSIZE[1]; // rv 0 + assign SAXIGP1ARSIZE_in[2] = (SAXIGP1ARSIZE[2] !== 1'bz) && SAXIGP1ARSIZE[2]; // rv 0 + assign SAXIGP1ARUSER_in = (SAXIGP1ARUSER !== 1'bz) && SAXIGP1ARUSER; // rv 0 + assign SAXIGP1ARVALID_in = (SAXIGP1ARVALID !== 1'bz) && SAXIGP1ARVALID; // rv 0 + assign SAXIGP1AWADDR_in[0] = (SAXIGP1AWADDR[0] !== 1'bz) && SAXIGP1AWADDR[0]; // rv 0 + assign SAXIGP1AWADDR_in[10] = (SAXIGP1AWADDR[10] !== 1'bz) && SAXIGP1AWADDR[10]; // rv 0 + assign SAXIGP1AWADDR_in[11] = (SAXIGP1AWADDR[11] !== 1'bz) && SAXIGP1AWADDR[11]; // rv 0 + assign SAXIGP1AWADDR_in[12] = (SAXIGP1AWADDR[12] !== 1'bz) && SAXIGP1AWADDR[12]; // rv 0 + assign SAXIGP1AWADDR_in[13] = (SAXIGP1AWADDR[13] !== 1'bz) && SAXIGP1AWADDR[13]; // rv 0 + assign SAXIGP1AWADDR_in[14] = (SAXIGP1AWADDR[14] !== 1'bz) && SAXIGP1AWADDR[14]; // rv 0 + assign SAXIGP1AWADDR_in[15] = (SAXIGP1AWADDR[15] !== 1'bz) && SAXIGP1AWADDR[15]; // rv 0 + assign SAXIGP1AWADDR_in[16] = (SAXIGP1AWADDR[16] !== 1'bz) && SAXIGP1AWADDR[16]; // rv 0 + assign SAXIGP1AWADDR_in[17] = (SAXIGP1AWADDR[17] !== 1'bz) && SAXIGP1AWADDR[17]; // rv 0 + assign SAXIGP1AWADDR_in[18] = (SAXIGP1AWADDR[18] !== 1'bz) && SAXIGP1AWADDR[18]; // rv 0 + assign SAXIGP1AWADDR_in[19] = (SAXIGP1AWADDR[19] !== 1'bz) && SAXIGP1AWADDR[19]; // rv 0 + assign SAXIGP1AWADDR_in[1] = (SAXIGP1AWADDR[1] !== 1'bz) && SAXIGP1AWADDR[1]; // rv 0 + assign SAXIGP1AWADDR_in[20] = (SAXIGP1AWADDR[20] !== 1'bz) && SAXIGP1AWADDR[20]; // rv 0 + assign SAXIGP1AWADDR_in[21] = (SAXIGP1AWADDR[21] !== 1'bz) && SAXIGP1AWADDR[21]; // rv 0 + assign SAXIGP1AWADDR_in[22] = (SAXIGP1AWADDR[22] !== 1'bz) && SAXIGP1AWADDR[22]; // rv 0 + assign SAXIGP1AWADDR_in[23] = (SAXIGP1AWADDR[23] !== 1'bz) && SAXIGP1AWADDR[23]; // rv 0 + assign SAXIGP1AWADDR_in[24] = (SAXIGP1AWADDR[24] !== 1'bz) && SAXIGP1AWADDR[24]; // rv 0 + assign SAXIGP1AWADDR_in[25] = (SAXIGP1AWADDR[25] !== 1'bz) && SAXIGP1AWADDR[25]; // rv 0 + assign SAXIGP1AWADDR_in[26] = (SAXIGP1AWADDR[26] !== 1'bz) && SAXIGP1AWADDR[26]; // rv 0 + assign SAXIGP1AWADDR_in[27] = (SAXIGP1AWADDR[27] !== 1'bz) && SAXIGP1AWADDR[27]; // rv 0 + assign SAXIGP1AWADDR_in[28] = (SAXIGP1AWADDR[28] !== 1'bz) && SAXIGP1AWADDR[28]; // rv 0 + assign SAXIGP1AWADDR_in[29] = (SAXIGP1AWADDR[29] !== 1'bz) && SAXIGP1AWADDR[29]; // rv 0 + assign SAXIGP1AWADDR_in[2] = (SAXIGP1AWADDR[2] !== 1'bz) && SAXIGP1AWADDR[2]; // rv 0 + assign SAXIGP1AWADDR_in[30] = (SAXIGP1AWADDR[30] !== 1'bz) && SAXIGP1AWADDR[30]; // rv 0 + assign SAXIGP1AWADDR_in[31] = (SAXIGP1AWADDR[31] !== 1'bz) && SAXIGP1AWADDR[31]; // rv 0 + assign SAXIGP1AWADDR_in[32] = (SAXIGP1AWADDR[32] !== 1'bz) && SAXIGP1AWADDR[32]; // rv 0 + assign SAXIGP1AWADDR_in[33] = (SAXIGP1AWADDR[33] !== 1'bz) && SAXIGP1AWADDR[33]; // rv 0 + assign SAXIGP1AWADDR_in[34] = (SAXIGP1AWADDR[34] !== 1'bz) && SAXIGP1AWADDR[34]; // rv 0 + assign SAXIGP1AWADDR_in[35] = (SAXIGP1AWADDR[35] !== 1'bz) && SAXIGP1AWADDR[35]; // rv 0 + assign SAXIGP1AWADDR_in[36] = (SAXIGP1AWADDR[36] !== 1'bz) && SAXIGP1AWADDR[36]; // rv 0 + assign SAXIGP1AWADDR_in[37] = (SAXIGP1AWADDR[37] !== 1'bz) && SAXIGP1AWADDR[37]; // rv 0 + assign SAXIGP1AWADDR_in[38] = (SAXIGP1AWADDR[38] !== 1'bz) && SAXIGP1AWADDR[38]; // rv 0 + assign SAXIGP1AWADDR_in[39] = (SAXIGP1AWADDR[39] !== 1'bz) && SAXIGP1AWADDR[39]; // rv 0 + assign SAXIGP1AWADDR_in[3] = (SAXIGP1AWADDR[3] !== 1'bz) && SAXIGP1AWADDR[3]; // rv 0 + assign SAXIGP1AWADDR_in[40] = (SAXIGP1AWADDR[40] !== 1'bz) && SAXIGP1AWADDR[40]; // rv 0 + assign SAXIGP1AWADDR_in[41] = (SAXIGP1AWADDR[41] !== 1'bz) && SAXIGP1AWADDR[41]; // rv 0 + assign SAXIGP1AWADDR_in[42] = (SAXIGP1AWADDR[42] !== 1'bz) && SAXIGP1AWADDR[42]; // rv 0 + assign SAXIGP1AWADDR_in[43] = (SAXIGP1AWADDR[43] !== 1'bz) && SAXIGP1AWADDR[43]; // rv 0 + assign SAXIGP1AWADDR_in[44] = (SAXIGP1AWADDR[44] !== 1'bz) && SAXIGP1AWADDR[44]; // rv 0 + assign SAXIGP1AWADDR_in[45] = (SAXIGP1AWADDR[45] !== 1'bz) && SAXIGP1AWADDR[45]; // rv 0 + assign SAXIGP1AWADDR_in[46] = (SAXIGP1AWADDR[46] !== 1'bz) && SAXIGP1AWADDR[46]; // rv 0 + assign SAXIGP1AWADDR_in[47] = (SAXIGP1AWADDR[47] !== 1'bz) && SAXIGP1AWADDR[47]; // rv 0 + assign SAXIGP1AWADDR_in[48] = (SAXIGP1AWADDR[48] !== 1'bz) && SAXIGP1AWADDR[48]; // rv 0 + assign SAXIGP1AWADDR_in[4] = (SAXIGP1AWADDR[4] !== 1'bz) && SAXIGP1AWADDR[4]; // rv 0 + assign SAXIGP1AWADDR_in[5] = (SAXIGP1AWADDR[5] !== 1'bz) && SAXIGP1AWADDR[5]; // rv 0 + assign SAXIGP1AWADDR_in[6] = (SAXIGP1AWADDR[6] !== 1'bz) && SAXIGP1AWADDR[6]; // rv 0 + assign SAXIGP1AWADDR_in[7] = (SAXIGP1AWADDR[7] !== 1'bz) && SAXIGP1AWADDR[7]; // rv 0 + assign SAXIGP1AWADDR_in[8] = (SAXIGP1AWADDR[8] !== 1'bz) && SAXIGP1AWADDR[8]; // rv 0 + assign SAXIGP1AWADDR_in[9] = (SAXIGP1AWADDR[9] !== 1'bz) && SAXIGP1AWADDR[9]; // rv 0 + assign SAXIGP1AWBURST_in[0] = (SAXIGP1AWBURST[0] !== 1'bz) && SAXIGP1AWBURST[0]; // rv 0 + assign SAXIGP1AWBURST_in[1] = (SAXIGP1AWBURST[1] !== 1'bz) && SAXIGP1AWBURST[1]; // rv 0 + assign SAXIGP1AWCACHE_in[0] = (SAXIGP1AWCACHE[0] !== 1'bz) && SAXIGP1AWCACHE[0]; // rv 0 + assign SAXIGP1AWCACHE_in[1] = (SAXIGP1AWCACHE[1] !== 1'bz) && SAXIGP1AWCACHE[1]; // rv 0 + assign SAXIGP1AWCACHE_in[2] = (SAXIGP1AWCACHE[2] !== 1'bz) && SAXIGP1AWCACHE[2]; // rv 0 + assign SAXIGP1AWCACHE_in[3] = (SAXIGP1AWCACHE[3] !== 1'bz) && SAXIGP1AWCACHE[3]; // rv 0 + assign SAXIGP1AWID_in[0] = (SAXIGP1AWID[0] !== 1'bz) && SAXIGP1AWID[0]; // rv 0 + assign SAXIGP1AWID_in[1] = (SAXIGP1AWID[1] !== 1'bz) && SAXIGP1AWID[1]; // rv 0 + assign SAXIGP1AWID_in[2] = (SAXIGP1AWID[2] !== 1'bz) && SAXIGP1AWID[2]; // rv 0 + assign SAXIGP1AWID_in[3] = (SAXIGP1AWID[3] !== 1'bz) && SAXIGP1AWID[3]; // rv 0 + assign SAXIGP1AWID_in[4] = (SAXIGP1AWID[4] !== 1'bz) && SAXIGP1AWID[4]; // rv 0 + assign SAXIGP1AWID_in[5] = (SAXIGP1AWID[5] !== 1'bz) && SAXIGP1AWID[5]; // rv 0 + assign SAXIGP1AWLEN_in[0] = (SAXIGP1AWLEN[0] !== 1'bz) && SAXIGP1AWLEN[0]; // rv 0 + assign SAXIGP1AWLEN_in[1] = (SAXIGP1AWLEN[1] !== 1'bz) && SAXIGP1AWLEN[1]; // rv 0 + assign SAXIGP1AWLEN_in[2] = (SAXIGP1AWLEN[2] !== 1'bz) && SAXIGP1AWLEN[2]; // rv 0 + assign SAXIGP1AWLEN_in[3] = (SAXIGP1AWLEN[3] !== 1'bz) && SAXIGP1AWLEN[3]; // rv 0 + assign SAXIGP1AWLEN_in[4] = (SAXIGP1AWLEN[4] !== 1'bz) && SAXIGP1AWLEN[4]; // rv 0 + assign SAXIGP1AWLEN_in[5] = (SAXIGP1AWLEN[5] !== 1'bz) && SAXIGP1AWLEN[5]; // rv 0 + assign SAXIGP1AWLEN_in[6] = (SAXIGP1AWLEN[6] !== 1'bz) && SAXIGP1AWLEN[6]; // rv 0 + assign SAXIGP1AWLEN_in[7] = (SAXIGP1AWLEN[7] !== 1'bz) && SAXIGP1AWLEN[7]; // rv 0 + assign SAXIGP1AWLOCK_in = (SAXIGP1AWLOCK !== 1'bz) && SAXIGP1AWLOCK; // rv 0 + assign SAXIGP1AWPROT_in[0] = (SAXIGP1AWPROT[0] !== 1'bz) && SAXIGP1AWPROT[0]; // rv 0 + assign SAXIGP1AWPROT_in[1] = (SAXIGP1AWPROT[1] !== 1'bz) && SAXIGP1AWPROT[1]; // rv 0 + assign SAXIGP1AWPROT_in[2] = (SAXIGP1AWPROT[2] !== 1'bz) && SAXIGP1AWPROT[2]; // rv 0 + assign SAXIGP1AWQOS_in[0] = (SAXIGP1AWQOS[0] !== 1'bz) && SAXIGP1AWQOS[0]; // rv 0 + assign SAXIGP1AWQOS_in[1] = (SAXIGP1AWQOS[1] !== 1'bz) && SAXIGP1AWQOS[1]; // rv 0 + assign SAXIGP1AWQOS_in[2] = (SAXIGP1AWQOS[2] !== 1'bz) && SAXIGP1AWQOS[2]; // rv 0 + assign SAXIGP1AWQOS_in[3] = (SAXIGP1AWQOS[3] !== 1'bz) && SAXIGP1AWQOS[3]; // rv 0 + assign SAXIGP1AWSIZE_in[0] = (SAXIGP1AWSIZE[0] !== 1'bz) && SAXIGP1AWSIZE[0]; // rv 0 + assign SAXIGP1AWSIZE_in[1] = (SAXIGP1AWSIZE[1] !== 1'bz) && SAXIGP1AWSIZE[1]; // rv 0 + assign SAXIGP1AWSIZE_in[2] = (SAXIGP1AWSIZE[2] !== 1'bz) && SAXIGP1AWSIZE[2]; // rv 0 + assign SAXIGP1AWUSER_in = (SAXIGP1AWUSER !== 1'bz) && SAXIGP1AWUSER; // rv 0 + assign SAXIGP1AWVALID_in = (SAXIGP1AWVALID !== 1'bz) && SAXIGP1AWVALID; // rv 0 + assign SAXIGP1BREADY_in = (SAXIGP1BREADY !== 1'bz) && SAXIGP1BREADY; // rv 0 + assign SAXIGP1RCLK_in = (SAXIGP1RCLK !== 1'bz) && SAXIGP1RCLK; // rv 0 + assign SAXIGP1RREADY_in = (SAXIGP1RREADY !== 1'bz) && SAXIGP1RREADY; // rv 0 + assign SAXIGP1WCLK_in = (SAXIGP1WCLK !== 1'bz) && SAXIGP1WCLK; // rv 0 + assign SAXIGP1WDATA_in[0] = (SAXIGP1WDATA[0] !== 1'bz) && SAXIGP1WDATA[0]; // rv 0 + assign SAXIGP1WDATA_in[100] = (SAXIGP1WDATA[100] !== 1'bz) && SAXIGP1WDATA[100]; // rv 0 + assign SAXIGP1WDATA_in[101] = (SAXIGP1WDATA[101] !== 1'bz) && SAXIGP1WDATA[101]; // rv 0 + assign SAXIGP1WDATA_in[102] = (SAXIGP1WDATA[102] !== 1'bz) && SAXIGP1WDATA[102]; // rv 0 + assign SAXIGP1WDATA_in[103] = (SAXIGP1WDATA[103] !== 1'bz) && SAXIGP1WDATA[103]; // rv 0 + assign SAXIGP1WDATA_in[104] = (SAXIGP1WDATA[104] !== 1'bz) && SAXIGP1WDATA[104]; // rv 0 + assign SAXIGP1WDATA_in[105] = (SAXIGP1WDATA[105] !== 1'bz) && SAXIGP1WDATA[105]; // rv 0 + assign SAXIGP1WDATA_in[106] = (SAXIGP1WDATA[106] !== 1'bz) && SAXIGP1WDATA[106]; // rv 0 + assign SAXIGP1WDATA_in[107] = (SAXIGP1WDATA[107] !== 1'bz) && SAXIGP1WDATA[107]; // rv 0 + assign SAXIGP1WDATA_in[108] = (SAXIGP1WDATA[108] !== 1'bz) && SAXIGP1WDATA[108]; // rv 0 + assign SAXIGP1WDATA_in[109] = (SAXIGP1WDATA[109] !== 1'bz) && SAXIGP1WDATA[109]; // rv 0 + assign SAXIGP1WDATA_in[10] = (SAXIGP1WDATA[10] !== 1'bz) && SAXIGP1WDATA[10]; // rv 0 + assign SAXIGP1WDATA_in[110] = (SAXIGP1WDATA[110] !== 1'bz) && SAXIGP1WDATA[110]; // rv 0 + assign SAXIGP1WDATA_in[111] = (SAXIGP1WDATA[111] !== 1'bz) && SAXIGP1WDATA[111]; // rv 0 + assign SAXIGP1WDATA_in[112] = (SAXIGP1WDATA[112] !== 1'bz) && SAXIGP1WDATA[112]; // rv 0 + assign SAXIGP1WDATA_in[113] = (SAXIGP1WDATA[113] !== 1'bz) && SAXIGP1WDATA[113]; // rv 0 + assign SAXIGP1WDATA_in[114] = (SAXIGP1WDATA[114] !== 1'bz) && SAXIGP1WDATA[114]; // rv 0 + assign SAXIGP1WDATA_in[115] = (SAXIGP1WDATA[115] !== 1'bz) && SAXIGP1WDATA[115]; // rv 0 + assign SAXIGP1WDATA_in[116] = (SAXIGP1WDATA[116] !== 1'bz) && SAXIGP1WDATA[116]; // rv 0 + assign SAXIGP1WDATA_in[117] = (SAXIGP1WDATA[117] !== 1'bz) && SAXIGP1WDATA[117]; // rv 0 + assign SAXIGP1WDATA_in[118] = (SAXIGP1WDATA[118] !== 1'bz) && SAXIGP1WDATA[118]; // rv 0 + assign SAXIGP1WDATA_in[119] = (SAXIGP1WDATA[119] !== 1'bz) && SAXIGP1WDATA[119]; // rv 0 + assign SAXIGP1WDATA_in[11] = (SAXIGP1WDATA[11] !== 1'bz) && SAXIGP1WDATA[11]; // rv 0 + assign SAXIGP1WDATA_in[120] = (SAXIGP1WDATA[120] !== 1'bz) && SAXIGP1WDATA[120]; // rv 0 + assign SAXIGP1WDATA_in[121] = (SAXIGP1WDATA[121] !== 1'bz) && SAXIGP1WDATA[121]; // rv 0 + assign SAXIGP1WDATA_in[122] = (SAXIGP1WDATA[122] !== 1'bz) && SAXIGP1WDATA[122]; // rv 0 + assign SAXIGP1WDATA_in[123] = (SAXIGP1WDATA[123] !== 1'bz) && SAXIGP1WDATA[123]; // rv 0 + assign SAXIGP1WDATA_in[124] = (SAXIGP1WDATA[124] !== 1'bz) && SAXIGP1WDATA[124]; // rv 0 + assign SAXIGP1WDATA_in[125] = (SAXIGP1WDATA[125] !== 1'bz) && SAXIGP1WDATA[125]; // rv 0 + assign SAXIGP1WDATA_in[126] = (SAXIGP1WDATA[126] !== 1'bz) && SAXIGP1WDATA[126]; // rv 0 + assign SAXIGP1WDATA_in[127] = (SAXIGP1WDATA[127] !== 1'bz) && SAXIGP1WDATA[127]; // rv 0 + assign SAXIGP1WDATA_in[12] = (SAXIGP1WDATA[12] !== 1'bz) && SAXIGP1WDATA[12]; // rv 0 + assign SAXIGP1WDATA_in[13] = (SAXIGP1WDATA[13] !== 1'bz) && SAXIGP1WDATA[13]; // rv 0 + assign SAXIGP1WDATA_in[14] = (SAXIGP1WDATA[14] !== 1'bz) && SAXIGP1WDATA[14]; // rv 0 + assign SAXIGP1WDATA_in[15] = (SAXIGP1WDATA[15] !== 1'bz) && SAXIGP1WDATA[15]; // rv 0 + assign SAXIGP1WDATA_in[16] = (SAXIGP1WDATA[16] !== 1'bz) && SAXIGP1WDATA[16]; // rv 0 + assign SAXIGP1WDATA_in[17] = (SAXIGP1WDATA[17] !== 1'bz) && SAXIGP1WDATA[17]; // rv 0 + assign SAXIGP1WDATA_in[18] = (SAXIGP1WDATA[18] !== 1'bz) && SAXIGP1WDATA[18]; // rv 0 + assign SAXIGP1WDATA_in[19] = (SAXIGP1WDATA[19] !== 1'bz) && SAXIGP1WDATA[19]; // rv 0 + assign SAXIGP1WDATA_in[1] = (SAXIGP1WDATA[1] !== 1'bz) && SAXIGP1WDATA[1]; // rv 0 + assign SAXIGP1WDATA_in[20] = (SAXIGP1WDATA[20] !== 1'bz) && SAXIGP1WDATA[20]; // rv 0 + assign SAXIGP1WDATA_in[21] = (SAXIGP1WDATA[21] !== 1'bz) && SAXIGP1WDATA[21]; // rv 0 + assign SAXIGP1WDATA_in[22] = (SAXIGP1WDATA[22] !== 1'bz) && SAXIGP1WDATA[22]; // rv 0 + assign SAXIGP1WDATA_in[23] = (SAXIGP1WDATA[23] !== 1'bz) && SAXIGP1WDATA[23]; // rv 0 + assign SAXIGP1WDATA_in[24] = (SAXIGP1WDATA[24] !== 1'bz) && SAXIGP1WDATA[24]; // rv 0 + assign SAXIGP1WDATA_in[25] = (SAXIGP1WDATA[25] !== 1'bz) && SAXIGP1WDATA[25]; // rv 0 + assign SAXIGP1WDATA_in[26] = (SAXIGP1WDATA[26] !== 1'bz) && SAXIGP1WDATA[26]; // rv 0 + assign SAXIGP1WDATA_in[27] = (SAXIGP1WDATA[27] !== 1'bz) && SAXIGP1WDATA[27]; // rv 0 + assign SAXIGP1WDATA_in[28] = (SAXIGP1WDATA[28] !== 1'bz) && SAXIGP1WDATA[28]; // rv 0 + assign SAXIGP1WDATA_in[29] = (SAXIGP1WDATA[29] !== 1'bz) && SAXIGP1WDATA[29]; // rv 0 + assign SAXIGP1WDATA_in[2] = (SAXIGP1WDATA[2] !== 1'bz) && SAXIGP1WDATA[2]; // rv 0 + assign SAXIGP1WDATA_in[30] = (SAXIGP1WDATA[30] !== 1'bz) && SAXIGP1WDATA[30]; // rv 0 + assign SAXIGP1WDATA_in[31] = (SAXIGP1WDATA[31] !== 1'bz) && SAXIGP1WDATA[31]; // rv 0 + assign SAXIGP1WDATA_in[32] = (SAXIGP1WDATA[32] !== 1'bz) && SAXIGP1WDATA[32]; // rv 0 + assign SAXIGP1WDATA_in[33] = (SAXIGP1WDATA[33] !== 1'bz) && SAXIGP1WDATA[33]; // rv 0 + assign SAXIGP1WDATA_in[34] = (SAXIGP1WDATA[34] !== 1'bz) && SAXIGP1WDATA[34]; // rv 0 + assign SAXIGP1WDATA_in[35] = (SAXIGP1WDATA[35] !== 1'bz) && SAXIGP1WDATA[35]; // rv 0 + assign SAXIGP1WDATA_in[36] = (SAXIGP1WDATA[36] !== 1'bz) && SAXIGP1WDATA[36]; // rv 0 + assign SAXIGP1WDATA_in[37] = (SAXIGP1WDATA[37] !== 1'bz) && SAXIGP1WDATA[37]; // rv 0 + assign SAXIGP1WDATA_in[38] = (SAXIGP1WDATA[38] !== 1'bz) && SAXIGP1WDATA[38]; // rv 0 + assign SAXIGP1WDATA_in[39] = (SAXIGP1WDATA[39] !== 1'bz) && SAXIGP1WDATA[39]; // rv 0 + assign SAXIGP1WDATA_in[3] = (SAXIGP1WDATA[3] !== 1'bz) && SAXIGP1WDATA[3]; // rv 0 + assign SAXIGP1WDATA_in[40] = (SAXIGP1WDATA[40] !== 1'bz) && SAXIGP1WDATA[40]; // rv 0 + assign SAXIGP1WDATA_in[41] = (SAXIGP1WDATA[41] !== 1'bz) && SAXIGP1WDATA[41]; // rv 0 + assign SAXIGP1WDATA_in[42] = (SAXIGP1WDATA[42] !== 1'bz) && SAXIGP1WDATA[42]; // rv 0 + assign SAXIGP1WDATA_in[43] = (SAXIGP1WDATA[43] !== 1'bz) && SAXIGP1WDATA[43]; // rv 0 + assign SAXIGP1WDATA_in[44] = (SAXIGP1WDATA[44] !== 1'bz) && SAXIGP1WDATA[44]; // rv 0 + assign SAXIGP1WDATA_in[45] = (SAXIGP1WDATA[45] !== 1'bz) && SAXIGP1WDATA[45]; // rv 0 + assign SAXIGP1WDATA_in[46] = (SAXIGP1WDATA[46] !== 1'bz) && SAXIGP1WDATA[46]; // rv 0 + assign SAXIGP1WDATA_in[47] = (SAXIGP1WDATA[47] !== 1'bz) && SAXIGP1WDATA[47]; // rv 0 + assign SAXIGP1WDATA_in[48] = (SAXIGP1WDATA[48] !== 1'bz) && SAXIGP1WDATA[48]; // rv 0 + assign SAXIGP1WDATA_in[49] = (SAXIGP1WDATA[49] !== 1'bz) && SAXIGP1WDATA[49]; // rv 0 + assign SAXIGP1WDATA_in[4] = (SAXIGP1WDATA[4] !== 1'bz) && SAXIGP1WDATA[4]; // rv 0 + assign SAXIGP1WDATA_in[50] = (SAXIGP1WDATA[50] !== 1'bz) && SAXIGP1WDATA[50]; // rv 0 + assign SAXIGP1WDATA_in[51] = (SAXIGP1WDATA[51] !== 1'bz) && SAXIGP1WDATA[51]; // rv 0 + assign SAXIGP1WDATA_in[52] = (SAXIGP1WDATA[52] !== 1'bz) && SAXIGP1WDATA[52]; // rv 0 + assign SAXIGP1WDATA_in[53] = (SAXIGP1WDATA[53] !== 1'bz) && SAXIGP1WDATA[53]; // rv 0 + assign SAXIGP1WDATA_in[54] = (SAXIGP1WDATA[54] !== 1'bz) && SAXIGP1WDATA[54]; // rv 0 + assign SAXIGP1WDATA_in[55] = (SAXIGP1WDATA[55] !== 1'bz) && SAXIGP1WDATA[55]; // rv 0 + assign SAXIGP1WDATA_in[56] = (SAXIGP1WDATA[56] !== 1'bz) && SAXIGP1WDATA[56]; // rv 0 + assign SAXIGP1WDATA_in[57] = (SAXIGP1WDATA[57] !== 1'bz) && SAXIGP1WDATA[57]; // rv 0 + assign SAXIGP1WDATA_in[58] = (SAXIGP1WDATA[58] !== 1'bz) && SAXIGP1WDATA[58]; // rv 0 + assign SAXIGP1WDATA_in[59] = (SAXIGP1WDATA[59] !== 1'bz) && SAXIGP1WDATA[59]; // rv 0 + assign SAXIGP1WDATA_in[5] = (SAXIGP1WDATA[5] !== 1'bz) && SAXIGP1WDATA[5]; // rv 0 + assign SAXIGP1WDATA_in[60] = (SAXIGP1WDATA[60] !== 1'bz) && SAXIGP1WDATA[60]; // rv 0 + assign SAXIGP1WDATA_in[61] = (SAXIGP1WDATA[61] !== 1'bz) && SAXIGP1WDATA[61]; // rv 0 + assign SAXIGP1WDATA_in[62] = (SAXIGP1WDATA[62] !== 1'bz) && SAXIGP1WDATA[62]; // rv 0 + assign SAXIGP1WDATA_in[63] = (SAXIGP1WDATA[63] !== 1'bz) && SAXIGP1WDATA[63]; // rv 0 + assign SAXIGP1WDATA_in[64] = (SAXIGP1WDATA[64] !== 1'bz) && SAXIGP1WDATA[64]; // rv 0 + assign SAXIGP1WDATA_in[65] = (SAXIGP1WDATA[65] !== 1'bz) && SAXIGP1WDATA[65]; // rv 0 + assign SAXIGP1WDATA_in[66] = (SAXIGP1WDATA[66] !== 1'bz) && SAXIGP1WDATA[66]; // rv 0 + assign SAXIGP1WDATA_in[67] = (SAXIGP1WDATA[67] !== 1'bz) && SAXIGP1WDATA[67]; // rv 0 + assign SAXIGP1WDATA_in[68] = (SAXIGP1WDATA[68] !== 1'bz) && SAXIGP1WDATA[68]; // rv 0 + assign SAXIGP1WDATA_in[69] = (SAXIGP1WDATA[69] !== 1'bz) && SAXIGP1WDATA[69]; // rv 0 + assign SAXIGP1WDATA_in[6] = (SAXIGP1WDATA[6] !== 1'bz) && SAXIGP1WDATA[6]; // rv 0 + assign SAXIGP1WDATA_in[70] = (SAXIGP1WDATA[70] !== 1'bz) && SAXIGP1WDATA[70]; // rv 0 + assign SAXIGP1WDATA_in[71] = (SAXIGP1WDATA[71] !== 1'bz) && SAXIGP1WDATA[71]; // rv 0 + assign SAXIGP1WDATA_in[72] = (SAXIGP1WDATA[72] !== 1'bz) && SAXIGP1WDATA[72]; // rv 0 + assign SAXIGP1WDATA_in[73] = (SAXIGP1WDATA[73] !== 1'bz) && SAXIGP1WDATA[73]; // rv 0 + assign SAXIGP1WDATA_in[74] = (SAXIGP1WDATA[74] !== 1'bz) && SAXIGP1WDATA[74]; // rv 0 + assign SAXIGP1WDATA_in[75] = (SAXIGP1WDATA[75] !== 1'bz) && SAXIGP1WDATA[75]; // rv 0 + assign SAXIGP1WDATA_in[76] = (SAXIGP1WDATA[76] !== 1'bz) && SAXIGP1WDATA[76]; // rv 0 + assign SAXIGP1WDATA_in[77] = (SAXIGP1WDATA[77] !== 1'bz) && SAXIGP1WDATA[77]; // rv 0 + assign SAXIGP1WDATA_in[78] = (SAXIGP1WDATA[78] !== 1'bz) && SAXIGP1WDATA[78]; // rv 0 + assign SAXIGP1WDATA_in[79] = (SAXIGP1WDATA[79] !== 1'bz) && SAXIGP1WDATA[79]; // rv 0 + assign SAXIGP1WDATA_in[7] = (SAXIGP1WDATA[7] !== 1'bz) && SAXIGP1WDATA[7]; // rv 0 + assign SAXIGP1WDATA_in[80] = (SAXIGP1WDATA[80] !== 1'bz) && SAXIGP1WDATA[80]; // rv 0 + assign SAXIGP1WDATA_in[81] = (SAXIGP1WDATA[81] !== 1'bz) && SAXIGP1WDATA[81]; // rv 0 + assign SAXIGP1WDATA_in[82] = (SAXIGP1WDATA[82] !== 1'bz) && SAXIGP1WDATA[82]; // rv 0 + assign SAXIGP1WDATA_in[83] = (SAXIGP1WDATA[83] !== 1'bz) && SAXIGP1WDATA[83]; // rv 0 + assign SAXIGP1WDATA_in[84] = (SAXIGP1WDATA[84] !== 1'bz) && SAXIGP1WDATA[84]; // rv 0 + assign SAXIGP1WDATA_in[85] = (SAXIGP1WDATA[85] !== 1'bz) && SAXIGP1WDATA[85]; // rv 0 + assign SAXIGP1WDATA_in[86] = (SAXIGP1WDATA[86] !== 1'bz) && SAXIGP1WDATA[86]; // rv 0 + assign SAXIGP1WDATA_in[87] = (SAXIGP1WDATA[87] !== 1'bz) && SAXIGP1WDATA[87]; // rv 0 + assign SAXIGP1WDATA_in[88] = (SAXIGP1WDATA[88] !== 1'bz) && SAXIGP1WDATA[88]; // rv 0 + assign SAXIGP1WDATA_in[89] = (SAXIGP1WDATA[89] !== 1'bz) && SAXIGP1WDATA[89]; // rv 0 + assign SAXIGP1WDATA_in[8] = (SAXIGP1WDATA[8] !== 1'bz) && SAXIGP1WDATA[8]; // rv 0 + assign SAXIGP1WDATA_in[90] = (SAXIGP1WDATA[90] !== 1'bz) && SAXIGP1WDATA[90]; // rv 0 + assign SAXIGP1WDATA_in[91] = (SAXIGP1WDATA[91] !== 1'bz) && SAXIGP1WDATA[91]; // rv 0 + assign SAXIGP1WDATA_in[92] = (SAXIGP1WDATA[92] !== 1'bz) && SAXIGP1WDATA[92]; // rv 0 + assign SAXIGP1WDATA_in[93] = (SAXIGP1WDATA[93] !== 1'bz) && SAXIGP1WDATA[93]; // rv 0 + assign SAXIGP1WDATA_in[94] = (SAXIGP1WDATA[94] !== 1'bz) && SAXIGP1WDATA[94]; // rv 0 + assign SAXIGP1WDATA_in[95] = (SAXIGP1WDATA[95] !== 1'bz) && SAXIGP1WDATA[95]; // rv 0 + assign SAXIGP1WDATA_in[96] = (SAXIGP1WDATA[96] !== 1'bz) && SAXIGP1WDATA[96]; // rv 0 + assign SAXIGP1WDATA_in[97] = (SAXIGP1WDATA[97] !== 1'bz) && SAXIGP1WDATA[97]; // rv 0 + assign SAXIGP1WDATA_in[98] = (SAXIGP1WDATA[98] !== 1'bz) && SAXIGP1WDATA[98]; // rv 0 + assign SAXIGP1WDATA_in[99] = (SAXIGP1WDATA[99] !== 1'bz) && SAXIGP1WDATA[99]; // rv 0 + assign SAXIGP1WDATA_in[9] = (SAXIGP1WDATA[9] !== 1'bz) && SAXIGP1WDATA[9]; // rv 0 + assign SAXIGP1WLAST_in = (SAXIGP1WLAST !== 1'bz) && SAXIGP1WLAST; // rv 0 + assign SAXIGP1WSTRB_in[0] = (SAXIGP1WSTRB[0] !== 1'bz) && SAXIGP1WSTRB[0]; // rv 0 + assign SAXIGP1WSTRB_in[10] = (SAXIGP1WSTRB[10] !== 1'bz) && SAXIGP1WSTRB[10]; // rv 0 + assign SAXIGP1WSTRB_in[11] = (SAXIGP1WSTRB[11] !== 1'bz) && SAXIGP1WSTRB[11]; // rv 0 + assign SAXIGP1WSTRB_in[12] = (SAXIGP1WSTRB[12] !== 1'bz) && SAXIGP1WSTRB[12]; // rv 0 + assign SAXIGP1WSTRB_in[13] = (SAXIGP1WSTRB[13] !== 1'bz) && SAXIGP1WSTRB[13]; // rv 0 + assign SAXIGP1WSTRB_in[14] = (SAXIGP1WSTRB[14] !== 1'bz) && SAXIGP1WSTRB[14]; // rv 0 + assign SAXIGP1WSTRB_in[15] = (SAXIGP1WSTRB[15] !== 1'bz) && SAXIGP1WSTRB[15]; // rv 0 + assign SAXIGP1WSTRB_in[1] = (SAXIGP1WSTRB[1] !== 1'bz) && SAXIGP1WSTRB[1]; // rv 0 + assign SAXIGP1WSTRB_in[2] = (SAXIGP1WSTRB[2] !== 1'bz) && SAXIGP1WSTRB[2]; // rv 0 + assign SAXIGP1WSTRB_in[3] = (SAXIGP1WSTRB[3] !== 1'bz) && SAXIGP1WSTRB[3]; // rv 0 + assign SAXIGP1WSTRB_in[4] = (SAXIGP1WSTRB[4] !== 1'bz) && SAXIGP1WSTRB[4]; // rv 0 + assign SAXIGP1WSTRB_in[5] = (SAXIGP1WSTRB[5] !== 1'bz) && SAXIGP1WSTRB[5]; // rv 0 + assign SAXIGP1WSTRB_in[6] = (SAXIGP1WSTRB[6] !== 1'bz) && SAXIGP1WSTRB[6]; // rv 0 + assign SAXIGP1WSTRB_in[7] = (SAXIGP1WSTRB[7] !== 1'bz) && SAXIGP1WSTRB[7]; // rv 0 + assign SAXIGP1WSTRB_in[8] = (SAXIGP1WSTRB[8] !== 1'bz) && SAXIGP1WSTRB[8]; // rv 0 + assign SAXIGP1WSTRB_in[9] = (SAXIGP1WSTRB[9] !== 1'bz) && SAXIGP1WSTRB[9]; // rv 0 + assign SAXIGP1WVALID_in = (SAXIGP1WVALID !== 1'bz) && SAXIGP1WVALID; // rv 0 + assign SAXIGP2ARADDR_in[0] = (SAXIGP2ARADDR[0] !== 1'bz) && SAXIGP2ARADDR[0]; // rv 0 + assign SAXIGP2ARADDR_in[10] = (SAXIGP2ARADDR[10] !== 1'bz) && SAXIGP2ARADDR[10]; // rv 0 + assign SAXIGP2ARADDR_in[11] = (SAXIGP2ARADDR[11] !== 1'bz) && SAXIGP2ARADDR[11]; // rv 0 + assign SAXIGP2ARADDR_in[12] = (SAXIGP2ARADDR[12] !== 1'bz) && SAXIGP2ARADDR[12]; // rv 0 + assign SAXIGP2ARADDR_in[13] = (SAXIGP2ARADDR[13] !== 1'bz) && SAXIGP2ARADDR[13]; // rv 0 + assign SAXIGP2ARADDR_in[14] = (SAXIGP2ARADDR[14] !== 1'bz) && SAXIGP2ARADDR[14]; // rv 0 + assign SAXIGP2ARADDR_in[15] = (SAXIGP2ARADDR[15] !== 1'bz) && SAXIGP2ARADDR[15]; // rv 0 + assign SAXIGP2ARADDR_in[16] = (SAXIGP2ARADDR[16] !== 1'bz) && SAXIGP2ARADDR[16]; // rv 0 + assign SAXIGP2ARADDR_in[17] = (SAXIGP2ARADDR[17] !== 1'bz) && SAXIGP2ARADDR[17]; // rv 0 + assign SAXIGP2ARADDR_in[18] = (SAXIGP2ARADDR[18] !== 1'bz) && SAXIGP2ARADDR[18]; // rv 0 + assign SAXIGP2ARADDR_in[19] = (SAXIGP2ARADDR[19] !== 1'bz) && SAXIGP2ARADDR[19]; // rv 0 + assign SAXIGP2ARADDR_in[1] = (SAXIGP2ARADDR[1] !== 1'bz) && SAXIGP2ARADDR[1]; // rv 0 + assign SAXIGP2ARADDR_in[20] = (SAXIGP2ARADDR[20] !== 1'bz) && SAXIGP2ARADDR[20]; // rv 0 + assign SAXIGP2ARADDR_in[21] = (SAXIGP2ARADDR[21] !== 1'bz) && SAXIGP2ARADDR[21]; // rv 0 + assign SAXIGP2ARADDR_in[22] = (SAXIGP2ARADDR[22] !== 1'bz) && SAXIGP2ARADDR[22]; // rv 0 + assign SAXIGP2ARADDR_in[23] = (SAXIGP2ARADDR[23] !== 1'bz) && SAXIGP2ARADDR[23]; // rv 0 + assign SAXIGP2ARADDR_in[24] = (SAXIGP2ARADDR[24] !== 1'bz) && SAXIGP2ARADDR[24]; // rv 0 + assign SAXIGP2ARADDR_in[25] = (SAXIGP2ARADDR[25] !== 1'bz) && SAXIGP2ARADDR[25]; // rv 0 + assign SAXIGP2ARADDR_in[26] = (SAXIGP2ARADDR[26] !== 1'bz) && SAXIGP2ARADDR[26]; // rv 0 + assign SAXIGP2ARADDR_in[27] = (SAXIGP2ARADDR[27] !== 1'bz) && SAXIGP2ARADDR[27]; // rv 0 + assign SAXIGP2ARADDR_in[28] = (SAXIGP2ARADDR[28] !== 1'bz) && SAXIGP2ARADDR[28]; // rv 0 + assign SAXIGP2ARADDR_in[29] = (SAXIGP2ARADDR[29] !== 1'bz) && SAXIGP2ARADDR[29]; // rv 0 + assign SAXIGP2ARADDR_in[2] = (SAXIGP2ARADDR[2] !== 1'bz) && SAXIGP2ARADDR[2]; // rv 0 + assign SAXIGP2ARADDR_in[30] = (SAXIGP2ARADDR[30] !== 1'bz) && SAXIGP2ARADDR[30]; // rv 0 + assign SAXIGP2ARADDR_in[31] = (SAXIGP2ARADDR[31] !== 1'bz) && SAXIGP2ARADDR[31]; // rv 0 + assign SAXIGP2ARADDR_in[32] = (SAXIGP2ARADDR[32] !== 1'bz) && SAXIGP2ARADDR[32]; // rv 0 + assign SAXIGP2ARADDR_in[33] = (SAXIGP2ARADDR[33] !== 1'bz) && SAXIGP2ARADDR[33]; // rv 0 + assign SAXIGP2ARADDR_in[34] = (SAXIGP2ARADDR[34] !== 1'bz) && SAXIGP2ARADDR[34]; // rv 0 + assign SAXIGP2ARADDR_in[35] = (SAXIGP2ARADDR[35] !== 1'bz) && SAXIGP2ARADDR[35]; // rv 0 + assign SAXIGP2ARADDR_in[36] = (SAXIGP2ARADDR[36] !== 1'bz) && SAXIGP2ARADDR[36]; // rv 0 + assign SAXIGP2ARADDR_in[37] = (SAXIGP2ARADDR[37] !== 1'bz) && SAXIGP2ARADDR[37]; // rv 0 + assign SAXIGP2ARADDR_in[38] = (SAXIGP2ARADDR[38] !== 1'bz) && SAXIGP2ARADDR[38]; // rv 0 + assign SAXIGP2ARADDR_in[39] = (SAXIGP2ARADDR[39] !== 1'bz) && SAXIGP2ARADDR[39]; // rv 0 + assign SAXIGP2ARADDR_in[3] = (SAXIGP2ARADDR[3] !== 1'bz) && SAXIGP2ARADDR[3]; // rv 0 + assign SAXIGP2ARADDR_in[40] = (SAXIGP2ARADDR[40] !== 1'bz) && SAXIGP2ARADDR[40]; // rv 0 + assign SAXIGP2ARADDR_in[41] = (SAXIGP2ARADDR[41] !== 1'bz) && SAXIGP2ARADDR[41]; // rv 0 + assign SAXIGP2ARADDR_in[42] = (SAXIGP2ARADDR[42] !== 1'bz) && SAXIGP2ARADDR[42]; // rv 0 + assign SAXIGP2ARADDR_in[43] = (SAXIGP2ARADDR[43] !== 1'bz) && SAXIGP2ARADDR[43]; // rv 0 + assign SAXIGP2ARADDR_in[44] = (SAXIGP2ARADDR[44] !== 1'bz) && SAXIGP2ARADDR[44]; // rv 0 + assign SAXIGP2ARADDR_in[45] = (SAXIGP2ARADDR[45] !== 1'bz) && SAXIGP2ARADDR[45]; // rv 0 + assign SAXIGP2ARADDR_in[46] = (SAXIGP2ARADDR[46] !== 1'bz) && SAXIGP2ARADDR[46]; // rv 0 + assign SAXIGP2ARADDR_in[47] = (SAXIGP2ARADDR[47] !== 1'bz) && SAXIGP2ARADDR[47]; // rv 0 + assign SAXIGP2ARADDR_in[48] = (SAXIGP2ARADDR[48] !== 1'bz) && SAXIGP2ARADDR[48]; // rv 0 + assign SAXIGP2ARADDR_in[4] = (SAXIGP2ARADDR[4] !== 1'bz) && SAXIGP2ARADDR[4]; // rv 0 + assign SAXIGP2ARADDR_in[5] = (SAXIGP2ARADDR[5] !== 1'bz) && SAXIGP2ARADDR[5]; // rv 0 + assign SAXIGP2ARADDR_in[6] = (SAXIGP2ARADDR[6] !== 1'bz) && SAXIGP2ARADDR[6]; // rv 0 + assign SAXIGP2ARADDR_in[7] = (SAXIGP2ARADDR[7] !== 1'bz) && SAXIGP2ARADDR[7]; // rv 0 + assign SAXIGP2ARADDR_in[8] = (SAXIGP2ARADDR[8] !== 1'bz) && SAXIGP2ARADDR[8]; // rv 0 + assign SAXIGP2ARADDR_in[9] = (SAXIGP2ARADDR[9] !== 1'bz) && SAXIGP2ARADDR[9]; // rv 0 + assign SAXIGP2ARBURST_in[0] = (SAXIGP2ARBURST[0] !== 1'bz) && SAXIGP2ARBURST[0]; // rv 0 + assign SAXIGP2ARBURST_in[1] = (SAXIGP2ARBURST[1] !== 1'bz) && SAXIGP2ARBURST[1]; // rv 0 + assign SAXIGP2ARCACHE_in[0] = (SAXIGP2ARCACHE[0] !== 1'bz) && SAXIGP2ARCACHE[0]; // rv 0 + assign SAXIGP2ARCACHE_in[1] = (SAXIGP2ARCACHE[1] !== 1'bz) && SAXIGP2ARCACHE[1]; // rv 0 + assign SAXIGP2ARCACHE_in[2] = (SAXIGP2ARCACHE[2] !== 1'bz) && SAXIGP2ARCACHE[2]; // rv 0 + assign SAXIGP2ARCACHE_in[3] = (SAXIGP2ARCACHE[3] !== 1'bz) && SAXIGP2ARCACHE[3]; // rv 0 + assign SAXIGP2ARID_in[0] = (SAXIGP2ARID[0] !== 1'bz) && SAXIGP2ARID[0]; // rv 0 + assign SAXIGP2ARID_in[1] = (SAXIGP2ARID[1] !== 1'bz) && SAXIGP2ARID[1]; // rv 0 + assign SAXIGP2ARID_in[2] = (SAXIGP2ARID[2] !== 1'bz) && SAXIGP2ARID[2]; // rv 0 + assign SAXIGP2ARID_in[3] = (SAXIGP2ARID[3] !== 1'bz) && SAXIGP2ARID[3]; // rv 0 + assign SAXIGP2ARID_in[4] = (SAXIGP2ARID[4] !== 1'bz) && SAXIGP2ARID[4]; // rv 0 + assign SAXIGP2ARID_in[5] = (SAXIGP2ARID[5] !== 1'bz) && SAXIGP2ARID[5]; // rv 0 + assign SAXIGP2ARLEN_in[0] = (SAXIGP2ARLEN[0] !== 1'bz) && SAXIGP2ARLEN[0]; // rv 0 + assign SAXIGP2ARLEN_in[1] = (SAXIGP2ARLEN[1] !== 1'bz) && SAXIGP2ARLEN[1]; // rv 0 + assign SAXIGP2ARLEN_in[2] = (SAXIGP2ARLEN[2] !== 1'bz) && SAXIGP2ARLEN[2]; // rv 0 + assign SAXIGP2ARLEN_in[3] = (SAXIGP2ARLEN[3] !== 1'bz) && SAXIGP2ARLEN[3]; // rv 0 + assign SAXIGP2ARLEN_in[4] = (SAXIGP2ARLEN[4] !== 1'bz) && SAXIGP2ARLEN[4]; // rv 0 + assign SAXIGP2ARLEN_in[5] = (SAXIGP2ARLEN[5] !== 1'bz) && SAXIGP2ARLEN[5]; // rv 0 + assign SAXIGP2ARLEN_in[6] = (SAXIGP2ARLEN[6] !== 1'bz) && SAXIGP2ARLEN[6]; // rv 0 + assign SAXIGP2ARLEN_in[7] = (SAXIGP2ARLEN[7] !== 1'bz) && SAXIGP2ARLEN[7]; // rv 0 + assign SAXIGP2ARLOCK_in = (SAXIGP2ARLOCK !== 1'bz) && SAXIGP2ARLOCK; // rv 0 + assign SAXIGP2ARPROT_in[0] = (SAXIGP2ARPROT[0] !== 1'bz) && SAXIGP2ARPROT[0]; // rv 0 + assign SAXIGP2ARPROT_in[1] = (SAXIGP2ARPROT[1] !== 1'bz) && SAXIGP2ARPROT[1]; // rv 0 + assign SAXIGP2ARPROT_in[2] = (SAXIGP2ARPROT[2] !== 1'bz) && SAXIGP2ARPROT[2]; // rv 0 + assign SAXIGP2ARQOS_in[0] = (SAXIGP2ARQOS[0] !== 1'bz) && SAXIGP2ARQOS[0]; // rv 0 + assign SAXIGP2ARQOS_in[1] = (SAXIGP2ARQOS[1] !== 1'bz) && SAXIGP2ARQOS[1]; // rv 0 + assign SAXIGP2ARQOS_in[2] = (SAXIGP2ARQOS[2] !== 1'bz) && SAXIGP2ARQOS[2]; // rv 0 + assign SAXIGP2ARQOS_in[3] = (SAXIGP2ARQOS[3] !== 1'bz) && SAXIGP2ARQOS[3]; // rv 0 + assign SAXIGP2ARSIZE_in[0] = (SAXIGP2ARSIZE[0] !== 1'bz) && SAXIGP2ARSIZE[0]; // rv 0 + assign SAXIGP2ARSIZE_in[1] = (SAXIGP2ARSIZE[1] !== 1'bz) && SAXIGP2ARSIZE[1]; // rv 0 + assign SAXIGP2ARSIZE_in[2] = (SAXIGP2ARSIZE[2] !== 1'bz) && SAXIGP2ARSIZE[2]; // rv 0 + assign SAXIGP2ARUSER_in = (SAXIGP2ARUSER !== 1'bz) && SAXIGP2ARUSER; // rv 0 + assign SAXIGP2ARVALID_in = (SAXIGP2ARVALID !== 1'bz) && SAXIGP2ARVALID; // rv 0 + assign SAXIGP2AWADDR_in[0] = (SAXIGP2AWADDR[0] !== 1'bz) && SAXIGP2AWADDR[0]; // rv 0 + assign SAXIGP2AWADDR_in[10] = (SAXIGP2AWADDR[10] !== 1'bz) && SAXIGP2AWADDR[10]; // rv 0 + assign SAXIGP2AWADDR_in[11] = (SAXIGP2AWADDR[11] !== 1'bz) && SAXIGP2AWADDR[11]; // rv 0 + assign SAXIGP2AWADDR_in[12] = (SAXIGP2AWADDR[12] !== 1'bz) && SAXIGP2AWADDR[12]; // rv 0 + assign SAXIGP2AWADDR_in[13] = (SAXIGP2AWADDR[13] !== 1'bz) && SAXIGP2AWADDR[13]; // rv 0 + assign SAXIGP2AWADDR_in[14] = (SAXIGP2AWADDR[14] !== 1'bz) && SAXIGP2AWADDR[14]; // rv 0 + assign SAXIGP2AWADDR_in[15] = (SAXIGP2AWADDR[15] !== 1'bz) && SAXIGP2AWADDR[15]; // rv 0 + assign SAXIGP2AWADDR_in[16] = (SAXIGP2AWADDR[16] !== 1'bz) && SAXIGP2AWADDR[16]; // rv 0 + assign SAXIGP2AWADDR_in[17] = (SAXIGP2AWADDR[17] !== 1'bz) && SAXIGP2AWADDR[17]; // rv 0 + assign SAXIGP2AWADDR_in[18] = (SAXIGP2AWADDR[18] !== 1'bz) && SAXIGP2AWADDR[18]; // rv 0 + assign SAXIGP2AWADDR_in[19] = (SAXIGP2AWADDR[19] !== 1'bz) && SAXIGP2AWADDR[19]; // rv 0 + assign SAXIGP2AWADDR_in[1] = (SAXIGP2AWADDR[1] !== 1'bz) && SAXIGP2AWADDR[1]; // rv 0 + assign SAXIGP2AWADDR_in[20] = (SAXIGP2AWADDR[20] !== 1'bz) && SAXIGP2AWADDR[20]; // rv 0 + assign SAXIGP2AWADDR_in[21] = (SAXIGP2AWADDR[21] !== 1'bz) && SAXIGP2AWADDR[21]; // rv 0 + assign SAXIGP2AWADDR_in[22] = (SAXIGP2AWADDR[22] !== 1'bz) && SAXIGP2AWADDR[22]; // rv 0 + assign SAXIGP2AWADDR_in[23] = (SAXIGP2AWADDR[23] !== 1'bz) && SAXIGP2AWADDR[23]; // rv 0 + assign SAXIGP2AWADDR_in[24] = (SAXIGP2AWADDR[24] !== 1'bz) && SAXIGP2AWADDR[24]; // rv 0 + assign SAXIGP2AWADDR_in[25] = (SAXIGP2AWADDR[25] !== 1'bz) && SAXIGP2AWADDR[25]; // rv 0 + assign SAXIGP2AWADDR_in[26] = (SAXIGP2AWADDR[26] !== 1'bz) && SAXIGP2AWADDR[26]; // rv 0 + assign SAXIGP2AWADDR_in[27] = (SAXIGP2AWADDR[27] !== 1'bz) && SAXIGP2AWADDR[27]; // rv 0 + assign SAXIGP2AWADDR_in[28] = (SAXIGP2AWADDR[28] !== 1'bz) && SAXIGP2AWADDR[28]; // rv 0 + assign SAXIGP2AWADDR_in[29] = (SAXIGP2AWADDR[29] !== 1'bz) && SAXIGP2AWADDR[29]; // rv 0 + assign SAXIGP2AWADDR_in[2] = (SAXIGP2AWADDR[2] !== 1'bz) && SAXIGP2AWADDR[2]; // rv 0 + assign SAXIGP2AWADDR_in[30] = (SAXIGP2AWADDR[30] !== 1'bz) && SAXIGP2AWADDR[30]; // rv 0 + assign SAXIGP2AWADDR_in[31] = (SAXIGP2AWADDR[31] !== 1'bz) && SAXIGP2AWADDR[31]; // rv 0 + assign SAXIGP2AWADDR_in[32] = (SAXIGP2AWADDR[32] !== 1'bz) && SAXIGP2AWADDR[32]; // rv 0 + assign SAXIGP2AWADDR_in[33] = (SAXIGP2AWADDR[33] !== 1'bz) && SAXIGP2AWADDR[33]; // rv 0 + assign SAXIGP2AWADDR_in[34] = (SAXIGP2AWADDR[34] !== 1'bz) && SAXIGP2AWADDR[34]; // rv 0 + assign SAXIGP2AWADDR_in[35] = (SAXIGP2AWADDR[35] !== 1'bz) && SAXIGP2AWADDR[35]; // rv 0 + assign SAXIGP2AWADDR_in[36] = (SAXIGP2AWADDR[36] !== 1'bz) && SAXIGP2AWADDR[36]; // rv 0 + assign SAXIGP2AWADDR_in[37] = (SAXIGP2AWADDR[37] !== 1'bz) && SAXIGP2AWADDR[37]; // rv 0 + assign SAXIGP2AWADDR_in[38] = (SAXIGP2AWADDR[38] !== 1'bz) && SAXIGP2AWADDR[38]; // rv 0 + assign SAXIGP2AWADDR_in[39] = (SAXIGP2AWADDR[39] !== 1'bz) && SAXIGP2AWADDR[39]; // rv 0 + assign SAXIGP2AWADDR_in[3] = (SAXIGP2AWADDR[3] !== 1'bz) && SAXIGP2AWADDR[3]; // rv 0 + assign SAXIGP2AWADDR_in[40] = (SAXIGP2AWADDR[40] !== 1'bz) && SAXIGP2AWADDR[40]; // rv 0 + assign SAXIGP2AWADDR_in[41] = (SAXIGP2AWADDR[41] !== 1'bz) && SAXIGP2AWADDR[41]; // rv 0 + assign SAXIGP2AWADDR_in[42] = (SAXIGP2AWADDR[42] !== 1'bz) && SAXIGP2AWADDR[42]; // rv 0 + assign SAXIGP2AWADDR_in[43] = (SAXIGP2AWADDR[43] !== 1'bz) && SAXIGP2AWADDR[43]; // rv 0 + assign SAXIGP2AWADDR_in[44] = (SAXIGP2AWADDR[44] !== 1'bz) && SAXIGP2AWADDR[44]; // rv 0 + assign SAXIGP2AWADDR_in[45] = (SAXIGP2AWADDR[45] !== 1'bz) && SAXIGP2AWADDR[45]; // rv 0 + assign SAXIGP2AWADDR_in[46] = (SAXIGP2AWADDR[46] !== 1'bz) && SAXIGP2AWADDR[46]; // rv 0 + assign SAXIGP2AWADDR_in[47] = (SAXIGP2AWADDR[47] !== 1'bz) && SAXIGP2AWADDR[47]; // rv 0 + assign SAXIGP2AWADDR_in[48] = (SAXIGP2AWADDR[48] !== 1'bz) && SAXIGP2AWADDR[48]; // rv 0 + assign SAXIGP2AWADDR_in[4] = (SAXIGP2AWADDR[4] !== 1'bz) && SAXIGP2AWADDR[4]; // rv 0 + assign SAXIGP2AWADDR_in[5] = (SAXIGP2AWADDR[5] !== 1'bz) && SAXIGP2AWADDR[5]; // rv 0 + assign SAXIGP2AWADDR_in[6] = (SAXIGP2AWADDR[6] !== 1'bz) && SAXIGP2AWADDR[6]; // rv 0 + assign SAXIGP2AWADDR_in[7] = (SAXIGP2AWADDR[7] !== 1'bz) && SAXIGP2AWADDR[7]; // rv 0 + assign SAXIGP2AWADDR_in[8] = (SAXIGP2AWADDR[8] !== 1'bz) && SAXIGP2AWADDR[8]; // rv 0 + assign SAXIGP2AWADDR_in[9] = (SAXIGP2AWADDR[9] !== 1'bz) && SAXIGP2AWADDR[9]; // rv 0 + assign SAXIGP2AWBURST_in[0] = (SAXIGP2AWBURST[0] !== 1'bz) && SAXIGP2AWBURST[0]; // rv 0 + assign SAXIGP2AWBURST_in[1] = (SAXIGP2AWBURST[1] !== 1'bz) && SAXIGP2AWBURST[1]; // rv 0 + assign SAXIGP2AWCACHE_in[0] = (SAXIGP2AWCACHE[0] !== 1'bz) && SAXIGP2AWCACHE[0]; // rv 0 + assign SAXIGP2AWCACHE_in[1] = (SAXIGP2AWCACHE[1] !== 1'bz) && SAXIGP2AWCACHE[1]; // rv 0 + assign SAXIGP2AWCACHE_in[2] = (SAXIGP2AWCACHE[2] !== 1'bz) && SAXIGP2AWCACHE[2]; // rv 0 + assign SAXIGP2AWCACHE_in[3] = (SAXIGP2AWCACHE[3] !== 1'bz) && SAXIGP2AWCACHE[3]; // rv 0 + assign SAXIGP2AWID_in[0] = (SAXIGP2AWID[0] !== 1'bz) && SAXIGP2AWID[0]; // rv 0 + assign SAXIGP2AWID_in[1] = (SAXIGP2AWID[1] !== 1'bz) && SAXIGP2AWID[1]; // rv 0 + assign SAXIGP2AWID_in[2] = (SAXIGP2AWID[2] !== 1'bz) && SAXIGP2AWID[2]; // rv 0 + assign SAXIGP2AWID_in[3] = (SAXIGP2AWID[3] !== 1'bz) && SAXIGP2AWID[3]; // rv 0 + assign SAXIGP2AWID_in[4] = (SAXIGP2AWID[4] !== 1'bz) && SAXIGP2AWID[4]; // rv 0 + assign SAXIGP2AWID_in[5] = (SAXIGP2AWID[5] !== 1'bz) && SAXIGP2AWID[5]; // rv 0 + assign SAXIGP2AWLEN_in[0] = (SAXIGP2AWLEN[0] !== 1'bz) && SAXIGP2AWLEN[0]; // rv 0 + assign SAXIGP2AWLEN_in[1] = (SAXIGP2AWLEN[1] !== 1'bz) && SAXIGP2AWLEN[1]; // rv 0 + assign SAXIGP2AWLEN_in[2] = (SAXIGP2AWLEN[2] !== 1'bz) && SAXIGP2AWLEN[2]; // rv 0 + assign SAXIGP2AWLEN_in[3] = (SAXIGP2AWLEN[3] !== 1'bz) && SAXIGP2AWLEN[3]; // rv 0 + assign SAXIGP2AWLEN_in[4] = (SAXIGP2AWLEN[4] !== 1'bz) && SAXIGP2AWLEN[4]; // rv 0 + assign SAXIGP2AWLEN_in[5] = (SAXIGP2AWLEN[5] !== 1'bz) && SAXIGP2AWLEN[5]; // rv 0 + assign SAXIGP2AWLEN_in[6] = (SAXIGP2AWLEN[6] !== 1'bz) && SAXIGP2AWLEN[6]; // rv 0 + assign SAXIGP2AWLEN_in[7] = (SAXIGP2AWLEN[7] !== 1'bz) && SAXIGP2AWLEN[7]; // rv 0 + assign SAXIGP2AWLOCK_in = (SAXIGP2AWLOCK !== 1'bz) && SAXIGP2AWLOCK; // rv 0 + assign SAXIGP2AWPROT_in[0] = (SAXIGP2AWPROT[0] !== 1'bz) && SAXIGP2AWPROT[0]; // rv 0 + assign SAXIGP2AWPROT_in[1] = (SAXIGP2AWPROT[1] !== 1'bz) && SAXIGP2AWPROT[1]; // rv 0 + assign SAXIGP2AWPROT_in[2] = (SAXIGP2AWPROT[2] !== 1'bz) && SAXIGP2AWPROT[2]; // rv 0 + assign SAXIGP2AWQOS_in[0] = (SAXIGP2AWQOS[0] !== 1'bz) && SAXIGP2AWQOS[0]; // rv 0 + assign SAXIGP2AWQOS_in[1] = (SAXIGP2AWQOS[1] !== 1'bz) && SAXIGP2AWQOS[1]; // rv 0 + assign SAXIGP2AWQOS_in[2] = (SAXIGP2AWQOS[2] !== 1'bz) && SAXIGP2AWQOS[2]; // rv 0 + assign SAXIGP2AWQOS_in[3] = (SAXIGP2AWQOS[3] !== 1'bz) && SAXIGP2AWQOS[3]; // rv 0 + assign SAXIGP2AWSIZE_in[0] = (SAXIGP2AWSIZE[0] !== 1'bz) && SAXIGP2AWSIZE[0]; // rv 0 + assign SAXIGP2AWSIZE_in[1] = (SAXIGP2AWSIZE[1] !== 1'bz) && SAXIGP2AWSIZE[1]; // rv 0 + assign SAXIGP2AWSIZE_in[2] = (SAXIGP2AWSIZE[2] !== 1'bz) && SAXIGP2AWSIZE[2]; // rv 0 + assign SAXIGP2AWUSER_in = (SAXIGP2AWUSER !== 1'bz) && SAXIGP2AWUSER; // rv 0 + assign SAXIGP2AWVALID_in = (SAXIGP2AWVALID !== 1'bz) && SAXIGP2AWVALID; // rv 0 + assign SAXIGP2BREADY_in = (SAXIGP2BREADY !== 1'bz) && SAXIGP2BREADY; // rv 0 + assign SAXIGP2RCLK_in = (SAXIGP2RCLK !== 1'bz) && SAXIGP2RCLK; // rv 0 + assign SAXIGP2RREADY_in = (SAXIGP2RREADY !== 1'bz) && SAXIGP2RREADY; // rv 0 + assign SAXIGP2WCLK_in = (SAXIGP2WCLK !== 1'bz) && SAXIGP2WCLK; // rv 0 + assign SAXIGP2WDATA_in[0] = (SAXIGP2WDATA[0] !== 1'bz) && SAXIGP2WDATA[0]; // rv 0 + assign SAXIGP2WDATA_in[100] = (SAXIGP2WDATA[100] !== 1'bz) && SAXIGP2WDATA[100]; // rv 0 + assign SAXIGP2WDATA_in[101] = (SAXIGP2WDATA[101] !== 1'bz) && SAXIGP2WDATA[101]; // rv 0 + assign SAXIGP2WDATA_in[102] = (SAXIGP2WDATA[102] !== 1'bz) && SAXIGP2WDATA[102]; // rv 0 + assign SAXIGP2WDATA_in[103] = (SAXIGP2WDATA[103] !== 1'bz) && SAXIGP2WDATA[103]; // rv 0 + assign SAXIGP2WDATA_in[104] = (SAXIGP2WDATA[104] !== 1'bz) && SAXIGP2WDATA[104]; // rv 0 + assign SAXIGP2WDATA_in[105] = (SAXIGP2WDATA[105] !== 1'bz) && SAXIGP2WDATA[105]; // rv 0 + assign SAXIGP2WDATA_in[106] = (SAXIGP2WDATA[106] !== 1'bz) && SAXIGP2WDATA[106]; // rv 0 + assign SAXIGP2WDATA_in[107] = (SAXIGP2WDATA[107] !== 1'bz) && SAXIGP2WDATA[107]; // rv 0 + assign SAXIGP2WDATA_in[108] = (SAXIGP2WDATA[108] !== 1'bz) && SAXIGP2WDATA[108]; // rv 0 + assign SAXIGP2WDATA_in[109] = (SAXIGP2WDATA[109] !== 1'bz) && SAXIGP2WDATA[109]; // rv 0 + assign SAXIGP2WDATA_in[10] = (SAXIGP2WDATA[10] !== 1'bz) && SAXIGP2WDATA[10]; // rv 0 + assign SAXIGP2WDATA_in[110] = (SAXIGP2WDATA[110] !== 1'bz) && SAXIGP2WDATA[110]; // rv 0 + assign SAXIGP2WDATA_in[111] = (SAXIGP2WDATA[111] !== 1'bz) && SAXIGP2WDATA[111]; // rv 0 + assign SAXIGP2WDATA_in[112] = (SAXIGP2WDATA[112] !== 1'bz) && SAXIGP2WDATA[112]; // rv 0 + assign SAXIGP2WDATA_in[113] = (SAXIGP2WDATA[113] !== 1'bz) && SAXIGP2WDATA[113]; // rv 0 + assign SAXIGP2WDATA_in[114] = (SAXIGP2WDATA[114] !== 1'bz) && SAXIGP2WDATA[114]; // rv 0 + assign SAXIGP2WDATA_in[115] = (SAXIGP2WDATA[115] !== 1'bz) && SAXIGP2WDATA[115]; // rv 0 + assign SAXIGP2WDATA_in[116] = (SAXIGP2WDATA[116] !== 1'bz) && SAXIGP2WDATA[116]; // rv 0 + assign SAXIGP2WDATA_in[117] = (SAXIGP2WDATA[117] !== 1'bz) && SAXIGP2WDATA[117]; // rv 0 + assign SAXIGP2WDATA_in[118] = (SAXIGP2WDATA[118] !== 1'bz) && SAXIGP2WDATA[118]; // rv 0 + assign SAXIGP2WDATA_in[119] = (SAXIGP2WDATA[119] !== 1'bz) && SAXIGP2WDATA[119]; // rv 0 + assign SAXIGP2WDATA_in[11] = (SAXIGP2WDATA[11] !== 1'bz) && SAXIGP2WDATA[11]; // rv 0 + assign SAXIGP2WDATA_in[120] = (SAXIGP2WDATA[120] !== 1'bz) && SAXIGP2WDATA[120]; // rv 0 + assign SAXIGP2WDATA_in[121] = (SAXIGP2WDATA[121] !== 1'bz) && SAXIGP2WDATA[121]; // rv 0 + assign SAXIGP2WDATA_in[122] = (SAXIGP2WDATA[122] !== 1'bz) && SAXIGP2WDATA[122]; // rv 0 + assign SAXIGP2WDATA_in[123] = (SAXIGP2WDATA[123] !== 1'bz) && SAXIGP2WDATA[123]; // rv 0 + assign SAXIGP2WDATA_in[124] = (SAXIGP2WDATA[124] !== 1'bz) && SAXIGP2WDATA[124]; // rv 0 + assign SAXIGP2WDATA_in[125] = (SAXIGP2WDATA[125] !== 1'bz) && SAXIGP2WDATA[125]; // rv 0 + assign SAXIGP2WDATA_in[126] = (SAXIGP2WDATA[126] !== 1'bz) && SAXIGP2WDATA[126]; // rv 0 + assign SAXIGP2WDATA_in[127] = (SAXIGP2WDATA[127] !== 1'bz) && SAXIGP2WDATA[127]; // rv 0 + assign SAXIGP2WDATA_in[12] = (SAXIGP2WDATA[12] !== 1'bz) && SAXIGP2WDATA[12]; // rv 0 + assign SAXIGP2WDATA_in[13] = (SAXIGP2WDATA[13] !== 1'bz) && SAXIGP2WDATA[13]; // rv 0 + assign SAXIGP2WDATA_in[14] = (SAXIGP2WDATA[14] !== 1'bz) && SAXIGP2WDATA[14]; // rv 0 + assign SAXIGP2WDATA_in[15] = (SAXIGP2WDATA[15] !== 1'bz) && SAXIGP2WDATA[15]; // rv 0 + assign SAXIGP2WDATA_in[16] = (SAXIGP2WDATA[16] !== 1'bz) && SAXIGP2WDATA[16]; // rv 0 + assign SAXIGP2WDATA_in[17] = (SAXIGP2WDATA[17] !== 1'bz) && SAXIGP2WDATA[17]; // rv 0 + assign SAXIGP2WDATA_in[18] = (SAXIGP2WDATA[18] !== 1'bz) && SAXIGP2WDATA[18]; // rv 0 + assign SAXIGP2WDATA_in[19] = (SAXIGP2WDATA[19] !== 1'bz) && SAXIGP2WDATA[19]; // rv 0 + assign SAXIGP2WDATA_in[1] = (SAXIGP2WDATA[1] !== 1'bz) && SAXIGP2WDATA[1]; // rv 0 + assign SAXIGP2WDATA_in[20] = (SAXIGP2WDATA[20] !== 1'bz) && SAXIGP2WDATA[20]; // rv 0 + assign SAXIGP2WDATA_in[21] = (SAXIGP2WDATA[21] !== 1'bz) && SAXIGP2WDATA[21]; // rv 0 + assign SAXIGP2WDATA_in[22] = (SAXIGP2WDATA[22] !== 1'bz) && SAXIGP2WDATA[22]; // rv 0 + assign SAXIGP2WDATA_in[23] = (SAXIGP2WDATA[23] !== 1'bz) && SAXIGP2WDATA[23]; // rv 0 + assign SAXIGP2WDATA_in[24] = (SAXIGP2WDATA[24] !== 1'bz) && SAXIGP2WDATA[24]; // rv 0 + assign SAXIGP2WDATA_in[25] = (SAXIGP2WDATA[25] !== 1'bz) && SAXIGP2WDATA[25]; // rv 0 + assign SAXIGP2WDATA_in[26] = (SAXIGP2WDATA[26] !== 1'bz) && SAXIGP2WDATA[26]; // rv 0 + assign SAXIGP2WDATA_in[27] = (SAXIGP2WDATA[27] !== 1'bz) && SAXIGP2WDATA[27]; // rv 0 + assign SAXIGP2WDATA_in[28] = (SAXIGP2WDATA[28] !== 1'bz) && SAXIGP2WDATA[28]; // rv 0 + assign SAXIGP2WDATA_in[29] = (SAXIGP2WDATA[29] !== 1'bz) && SAXIGP2WDATA[29]; // rv 0 + assign SAXIGP2WDATA_in[2] = (SAXIGP2WDATA[2] !== 1'bz) && SAXIGP2WDATA[2]; // rv 0 + assign SAXIGP2WDATA_in[30] = (SAXIGP2WDATA[30] !== 1'bz) && SAXIGP2WDATA[30]; // rv 0 + assign SAXIGP2WDATA_in[31] = (SAXIGP2WDATA[31] !== 1'bz) && SAXIGP2WDATA[31]; // rv 0 + assign SAXIGP2WDATA_in[32] = (SAXIGP2WDATA[32] !== 1'bz) && SAXIGP2WDATA[32]; // rv 0 + assign SAXIGP2WDATA_in[33] = (SAXIGP2WDATA[33] !== 1'bz) && SAXIGP2WDATA[33]; // rv 0 + assign SAXIGP2WDATA_in[34] = (SAXIGP2WDATA[34] !== 1'bz) && SAXIGP2WDATA[34]; // rv 0 + assign SAXIGP2WDATA_in[35] = (SAXIGP2WDATA[35] !== 1'bz) && SAXIGP2WDATA[35]; // rv 0 + assign SAXIGP2WDATA_in[36] = (SAXIGP2WDATA[36] !== 1'bz) && SAXIGP2WDATA[36]; // rv 0 + assign SAXIGP2WDATA_in[37] = (SAXIGP2WDATA[37] !== 1'bz) && SAXIGP2WDATA[37]; // rv 0 + assign SAXIGP2WDATA_in[38] = (SAXIGP2WDATA[38] !== 1'bz) && SAXIGP2WDATA[38]; // rv 0 + assign SAXIGP2WDATA_in[39] = (SAXIGP2WDATA[39] !== 1'bz) && SAXIGP2WDATA[39]; // rv 0 + assign SAXIGP2WDATA_in[3] = (SAXIGP2WDATA[3] !== 1'bz) && SAXIGP2WDATA[3]; // rv 0 + assign SAXIGP2WDATA_in[40] = (SAXIGP2WDATA[40] !== 1'bz) && SAXIGP2WDATA[40]; // rv 0 + assign SAXIGP2WDATA_in[41] = (SAXIGP2WDATA[41] !== 1'bz) && SAXIGP2WDATA[41]; // rv 0 + assign SAXIGP2WDATA_in[42] = (SAXIGP2WDATA[42] !== 1'bz) && SAXIGP2WDATA[42]; // rv 0 + assign SAXIGP2WDATA_in[43] = (SAXIGP2WDATA[43] !== 1'bz) && SAXIGP2WDATA[43]; // rv 0 + assign SAXIGP2WDATA_in[44] = (SAXIGP2WDATA[44] !== 1'bz) && SAXIGP2WDATA[44]; // rv 0 + assign SAXIGP2WDATA_in[45] = (SAXIGP2WDATA[45] !== 1'bz) && SAXIGP2WDATA[45]; // rv 0 + assign SAXIGP2WDATA_in[46] = (SAXIGP2WDATA[46] !== 1'bz) && SAXIGP2WDATA[46]; // rv 0 + assign SAXIGP2WDATA_in[47] = (SAXIGP2WDATA[47] !== 1'bz) && SAXIGP2WDATA[47]; // rv 0 + assign SAXIGP2WDATA_in[48] = (SAXIGP2WDATA[48] !== 1'bz) && SAXIGP2WDATA[48]; // rv 0 + assign SAXIGP2WDATA_in[49] = (SAXIGP2WDATA[49] !== 1'bz) && SAXIGP2WDATA[49]; // rv 0 + assign SAXIGP2WDATA_in[4] = (SAXIGP2WDATA[4] !== 1'bz) && SAXIGP2WDATA[4]; // rv 0 + assign SAXIGP2WDATA_in[50] = (SAXIGP2WDATA[50] !== 1'bz) && SAXIGP2WDATA[50]; // rv 0 + assign SAXIGP2WDATA_in[51] = (SAXIGP2WDATA[51] !== 1'bz) && SAXIGP2WDATA[51]; // rv 0 + assign SAXIGP2WDATA_in[52] = (SAXIGP2WDATA[52] !== 1'bz) && SAXIGP2WDATA[52]; // rv 0 + assign SAXIGP2WDATA_in[53] = (SAXIGP2WDATA[53] !== 1'bz) && SAXIGP2WDATA[53]; // rv 0 + assign SAXIGP2WDATA_in[54] = (SAXIGP2WDATA[54] !== 1'bz) && SAXIGP2WDATA[54]; // rv 0 + assign SAXIGP2WDATA_in[55] = (SAXIGP2WDATA[55] !== 1'bz) && SAXIGP2WDATA[55]; // rv 0 + assign SAXIGP2WDATA_in[56] = (SAXIGP2WDATA[56] !== 1'bz) && SAXIGP2WDATA[56]; // rv 0 + assign SAXIGP2WDATA_in[57] = (SAXIGP2WDATA[57] !== 1'bz) && SAXIGP2WDATA[57]; // rv 0 + assign SAXIGP2WDATA_in[58] = (SAXIGP2WDATA[58] !== 1'bz) && SAXIGP2WDATA[58]; // rv 0 + assign SAXIGP2WDATA_in[59] = (SAXIGP2WDATA[59] !== 1'bz) && SAXIGP2WDATA[59]; // rv 0 + assign SAXIGP2WDATA_in[5] = (SAXIGP2WDATA[5] !== 1'bz) && SAXIGP2WDATA[5]; // rv 0 + assign SAXIGP2WDATA_in[60] = (SAXIGP2WDATA[60] !== 1'bz) && SAXIGP2WDATA[60]; // rv 0 + assign SAXIGP2WDATA_in[61] = (SAXIGP2WDATA[61] !== 1'bz) && SAXIGP2WDATA[61]; // rv 0 + assign SAXIGP2WDATA_in[62] = (SAXIGP2WDATA[62] !== 1'bz) && SAXIGP2WDATA[62]; // rv 0 + assign SAXIGP2WDATA_in[63] = (SAXIGP2WDATA[63] !== 1'bz) && SAXIGP2WDATA[63]; // rv 0 + assign SAXIGP2WDATA_in[64] = (SAXIGP2WDATA[64] !== 1'bz) && SAXIGP2WDATA[64]; // rv 0 + assign SAXIGP2WDATA_in[65] = (SAXIGP2WDATA[65] !== 1'bz) && SAXIGP2WDATA[65]; // rv 0 + assign SAXIGP2WDATA_in[66] = (SAXIGP2WDATA[66] !== 1'bz) && SAXIGP2WDATA[66]; // rv 0 + assign SAXIGP2WDATA_in[67] = (SAXIGP2WDATA[67] !== 1'bz) && SAXIGP2WDATA[67]; // rv 0 + assign SAXIGP2WDATA_in[68] = (SAXIGP2WDATA[68] !== 1'bz) && SAXIGP2WDATA[68]; // rv 0 + assign SAXIGP2WDATA_in[69] = (SAXIGP2WDATA[69] !== 1'bz) && SAXIGP2WDATA[69]; // rv 0 + assign SAXIGP2WDATA_in[6] = (SAXIGP2WDATA[6] !== 1'bz) && SAXIGP2WDATA[6]; // rv 0 + assign SAXIGP2WDATA_in[70] = (SAXIGP2WDATA[70] !== 1'bz) && SAXIGP2WDATA[70]; // rv 0 + assign SAXIGP2WDATA_in[71] = (SAXIGP2WDATA[71] !== 1'bz) && SAXIGP2WDATA[71]; // rv 0 + assign SAXIGP2WDATA_in[72] = (SAXIGP2WDATA[72] !== 1'bz) && SAXIGP2WDATA[72]; // rv 0 + assign SAXIGP2WDATA_in[73] = (SAXIGP2WDATA[73] !== 1'bz) && SAXIGP2WDATA[73]; // rv 0 + assign SAXIGP2WDATA_in[74] = (SAXIGP2WDATA[74] !== 1'bz) && SAXIGP2WDATA[74]; // rv 0 + assign SAXIGP2WDATA_in[75] = (SAXIGP2WDATA[75] !== 1'bz) && SAXIGP2WDATA[75]; // rv 0 + assign SAXIGP2WDATA_in[76] = (SAXIGP2WDATA[76] !== 1'bz) && SAXIGP2WDATA[76]; // rv 0 + assign SAXIGP2WDATA_in[77] = (SAXIGP2WDATA[77] !== 1'bz) && SAXIGP2WDATA[77]; // rv 0 + assign SAXIGP2WDATA_in[78] = (SAXIGP2WDATA[78] !== 1'bz) && SAXIGP2WDATA[78]; // rv 0 + assign SAXIGP2WDATA_in[79] = (SAXIGP2WDATA[79] !== 1'bz) && SAXIGP2WDATA[79]; // rv 0 + assign SAXIGP2WDATA_in[7] = (SAXIGP2WDATA[7] !== 1'bz) && SAXIGP2WDATA[7]; // rv 0 + assign SAXIGP2WDATA_in[80] = (SAXIGP2WDATA[80] !== 1'bz) && SAXIGP2WDATA[80]; // rv 0 + assign SAXIGP2WDATA_in[81] = (SAXIGP2WDATA[81] !== 1'bz) && SAXIGP2WDATA[81]; // rv 0 + assign SAXIGP2WDATA_in[82] = (SAXIGP2WDATA[82] !== 1'bz) && SAXIGP2WDATA[82]; // rv 0 + assign SAXIGP2WDATA_in[83] = (SAXIGP2WDATA[83] !== 1'bz) && SAXIGP2WDATA[83]; // rv 0 + assign SAXIGP2WDATA_in[84] = (SAXIGP2WDATA[84] !== 1'bz) && SAXIGP2WDATA[84]; // rv 0 + assign SAXIGP2WDATA_in[85] = (SAXIGP2WDATA[85] !== 1'bz) && SAXIGP2WDATA[85]; // rv 0 + assign SAXIGP2WDATA_in[86] = (SAXIGP2WDATA[86] !== 1'bz) && SAXIGP2WDATA[86]; // rv 0 + assign SAXIGP2WDATA_in[87] = (SAXIGP2WDATA[87] !== 1'bz) && SAXIGP2WDATA[87]; // rv 0 + assign SAXIGP2WDATA_in[88] = (SAXIGP2WDATA[88] !== 1'bz) && SAXIGP2WDATA[88]; // rv 0 + assign SAXIGP2WDATA_in[89] = (SAXIGP2WDATA[89] !== 1'bz) && SAXIGP2WDATA[89]; // rv 0 + assign SAXIGP2WDATA_in[8] = (SAXIGP2WDATA[8] !== 1'bz) && SAXIGP2WDATA[8]; // rv 0 + assign SAXIGP2WDATA_in[90] = (SAXIGP2WDATA[90] !== 1'bz) && SAXIGP2WDATA[90]; // rv 0 + assign SAXIGP2WDATA_in[91] = (SAXIGP2WDATA[91] !== 1'bz) && SAXIGP2WDATA[91]; // rv 0 + assign SAXIGP2WDATA_in[92] = (SAXIGP2WDATA[92] !== 1'bz) && SAXIGP2WDATA[92]; // rv 0 + assign SAXIGP2WDATA_in[93] = (SAXIGP2WDATA[93] !== 1'bz) && SAXIGP2WDATA[93]; // rv 0 + assign SAXIGP2WDATA_in[94] = (SAXIGP2WDATA[94] !== 1'bz) && SAXIGP2WDATA[94]; // rv 0 + assign SAXIGP2WDATA_in[95] = (SAXIGP2WDATA[95] !== 1'bz) && SAXIGP2WDATA[95]; // rv 0 + assign SAXIGP2WDATA_in[96] = (SAXIGP2WDATA[96] !== 1'bz) && SAXIGP2WDATA[96]; // rv 0 + assign SAXIGP2WDATA_in[97] = (SAXIGP2WDATA[97] !== 1'bz) && SAXIGP2WDATA[97]; // rv 0 + assign SAXIGP2WDATA_in[98] = (SAXIGP2WDATA[98] !== 1'bz) && SAXIGP2WDATA[98]; // rv 0 + assign SAXIGP2WDATA_in[99] = (SAXIGP2WDATA[99] !== 1'bz) && SAXIGP2WDATA[99]; // rv 0 + assign SAXIGP2WDATA_in[9] = (SAXIGP2WDATA[9] !== 1'bz) && SAXIGP2WDATA[9]; // rv 0 + assign SAXIGP2WLAST_in = (SAXIGP2WLAST !== 1'bz) && SAXIGP2WLAST; // rv 0 + assign SAXIGP2WSTRB_in[0] = (SAXIGP2WSTRB[0] !== 1'bz) && SAXIGP2WSTRB[0]; // rv 0 + assign SAXIGP2WSTRB_in[10] = (SAXIGP2WSTRB[10] !== 1'bz) && SAXIGP2WSTRB[10]; // rv 0 + assign SAXIGP2WSTRB_in[11] = (SAXIGP2WSTRB[11] !== 1'bz) && SAXIGP2WSTRB[11]; // rv 0 + assign SAXIGP2WSTRB_in[12] = (SAXIGP2WSTRB[12] !== 1'bz) && SAXIGP2WSTRB[12]; // rv 0 + assign SAXIGP2WSTRB_in[13] = (SAXIGP2WSTRB[13] !== 1'bz) && SAXIGP2WSTRB[13]; // rv 0 + assign SAXIGP2WSTRB_in[14] = (SAXIGP2WSTRB[14] !== 1'bz) && SAXIGP2WSTRB[14]; // rv 0 + assign SAXIGP2WSTRB_in[15] = (SAXIGP2WSTRB[15] !== 1'bz) && SAXIGP2WSTRB[15]; // rv 0 + assign SAXIGP2WSTRB_in[1] = (SAXIGP2WSTRB[1] !== 1'bz) && SAXIGP2WSTRB[1]; // rv 0 + assign SAXIGP2WSTRB_in[2] = (SAXIGP2WSTRB[2] !== 1'bz) && SAXIGP2WSTRB[2]; // rv 0 + assign SAXIGP2WSTRB_in[3] = (SAXIGP2WSTRB[3] !== 1'bz) && SAXIGP2WSTRB[3]; // rv 0 + assign SAXIGP2WSTRB_in[4] = (SAXIGP2WSTRB[4] !== 1'bz) && SAXIGP2WSTRB[4]; // rv 0 + assign SAXIGP2WSTRB_in[5] = (SAXIGP2WSTRB[5] !== 1'bz) && SAXIGP2WSTRB[5]; // rv 0 + assign SAXIGP2WSTRB_in[6] = (SAXIGP2WSTRB[6] !== 1'bz) && SAXIGP2WSTRB[6]; // rv 0 + assign SAXIGP2WSTRB_in[7] = (SAXIGP2WSTRB[7] !== 1'bz) && SAXIGP2WSTRB[7]; // rv 0 + assign SAXIGP2WSTRB_in[8] = (SAXIGP2WSTRB[8] !== 1'bz) && SAXIGP2WSTRB[8]; // rv 0 + assign SAXIGP2WSTRB_in[9] = (SAXIGP2WSTRB[9] !== 1'bz) && SAXIGP2WSTRB[9]; // rv 0 + assign SAXIGP2WVALID_in = (SAXIGP2WVALID !== 1'bz) && SAXIGP2WVALID; // rv 0 + assign SAXIGP3ARADDR_in[0] = (SAXIGP3ARADDR[0] !== 1'bz) && SAXIGP3ARADDR[0]; // rv 0 + assign SAXIGP3ARADDR_in[10] = (SAXIGP3ARADDR[10] !== 1'bz) && SAXIGP3ARADDR[10]; // rv 0 + assign SAXIGP3ARADDR_in[11] = (SAXIGP3ARADDR[11] !== 1'bz) && SAXIGP3ARADDR[11]; // rv 0 + assign SAXIGP3ARADDR_in[12] = (SAXIGP3ARADDR[12] !== 1'bz) && SAXIGP3ARADDR[12]; // rv 0 + assign SAXIGP3ARADDR_in[13] = (SAXIGP3ARADDR[13] !== 1'bz) && SAXIGP3ARADDR[13]; // rv 0 + assign SAXIGP3ARADDR_in[14] = (SAXIGP3ARADDR[14] !== 1'bz) && SAXIGP3ARADDR[14]; // rv 0 + assign SAXIGP3ARADDR_in[15] = (SAXIGP3ARADDR[15] !== 1'bz) && SAXIGP3ARADDR[15]; // rv 0 + assign SAXIGP3ARADDR_in[16] = (SAXIGP3ARADDR[16] !== 1'bz) && SAXIGP3ARADDR[16]; // rv 0 + assign SAXIGP3ARADDR_in[17] = (SAXIGP3ARADDR[17] !== 1'bz) && SAXIGP3ARADDR[17]; // rv 0 + assign SAXIGP3ARADDR_in[18] = (SAXIGP3ARADDR[18] !== 1'bz) && SAXIGP3ARADDR[18]; // rv 0 + assign SAXIGP3ARADDR_in[19] = (SAXIGP3ARADDR[19] !== 1'bz) && SAXIGP3ARADDR[19]; // rv 0 + assign SAXIGP3ARADDR_in[1] = (SAXIGP3ARADDR[1] !== 1'bz) && SAXIGP3ARADDR[1]; // rv 0 + assign SAXIGP3ARADDR_in[20] = (SAXIGP3ARADDR[20] !== 1'bz) && SAXIGP3ARADDR[20]; // rv 0 + assign SAXIGP3ARADDR_in[21] = (SAXIGP3ARADDR[21] !== 1'bz) && SAXIGP3ARADDR[21]; // rv 0 + assign SAXIGP3ARADDR_in[22] = (SAXIGP3ARADDR[22] !== 1'bz) && SAXIGP3ARADDR[22]; // rv 0 + assign SAXIGP3ARADDR_in[23] = (SAXIGP3ARADDR[23] !== 1'bz) && SAXIGP3ARADDR[23]; // rv 0 + assign SAXIGP3ARADDR_in[24] = (SAXIGP3ARADDR[24] !== 1'bz) && SAXIGP3ARADDR[24]; // rv 0 + assign SAXIGP3ARADDR_in[25] = (SAXIGP3ARADDR[25] !== 1'bz) && SAXIGP3ARADDR[25]; // rv 0 + assign SAXIGP3ARADDR_in[26] = (SAXIGP3ARADDR[26] !== 1'bz) && SAXIGP3ARADDR[26]; // rv 0 + assign SAXIGP3ARADDR_in[27] = (SAXIGP3ARADDR[27] !== 1'bz) && SAXIGP3ARADDR[27]; // rv 0 + assign SAXIGP3ARADDR_in[28] = (SAXIGP3ARADDR[28] !== 1'bz) && SAXIGP3ARADDR[28]; // rv 0 + assign SAXIGP3ARADDR_in[29] = (SAXIGP3ARADDR[29] !== 1'bz) && SAXIGP3ARADDR[29]; // rv 0 + assign SAXIGP3ARADDR_in[2] = (SAXIGP3ARADDR[2] !== 1'bz) && SAXIGP3ARADDR[2]; // rv 0 + assign SAXIGP3ARADDR_in[30] = (SAXIGP3ARADDR[30] !== 1'bz) && SAXIGP3ARADDR[30]; // rv 0 + assign SAXIGP3ARADDR_in[31] = (SAXIGP3ARADDR[31] !== 1'bz) && SAXIGP3ARADDR[31]; // rv 0 + assign SAXIGP3ARADDR_in[32] = (SAXIGP3ARADDR[32] !== 1'bz) && SAXIGP3ARADDR[32]; // rv 0 + assign SAXIGP3ARADDR_in[33] = (SAXIGP3ARADDR[33] !== 1'bz) && SAXIGP3ARADDR[33]; // rv 0 + assign SAXIGP3ARADDR_in[34] = (SAXIGP3ARADDR[34] !== 1'bz) && SAXIGP3ARADDR[34]; // rv 0 + assign SAXIGP3ARADDR_in[35] = (SAXIGP3ARADDR[35] !== 1'bz) && SAXIGP3ARADDR[35]; // rv 0 + assign SAXIGP3ARADDR_in[36] = (SAXIGP3ARADDR[36] !== 1'bz) && SAXIGP3ARADDR[36]; // rv 0 + assign SAXIGP3ARADDR_in[37] = (SAXIGP3ARADDR[37] !== 1'bz) && SAXIGP3ARADDR[37]; // rv 0 + assign SAXIGP3ARADDR_in[38] = (SAXIGP3ARADDR[38] !== 1'bz) && SAXIGP3ARADDR[38]; // rv 0 + assign SAXIGP3ARADDR_in[39] = (SAXIGP3ARADDR[39] !== 1'bz) && SAXIGP3ARADDR[39]; // rv 0 + assign SAXIGP3ARADDR_in[3] = (SAXIGP3ARADDR[3] !== 1'bz) && SAXIGP3ARADDR[3]; // rv 0 + assign SAXIGP3ARADDR_in[40] = (SAXIGP3ARADDR[40] !== 1'bz) && SAXIGP3ARADDR[40]; // rv 0 + assign SAXIGP3ARADDR_in[41] = (SAXIGP3ARADDR[41] !== 1'bz) && SAXIGP3ARADDR[41]; // rv 0 + assign SAXIGP3ARADDR_in[42] = (SAXIGP3ARADDR[42] !== 1'bz) && SAXIGP3ARADDR[42]; // rv 0 + assign SAXIGP3ARADDR_in[43] = (SAXIGP3ARADDR[43] !== 1'bz) && SAXIGP3ARADDR[43]; // rv 0 + assign SAXIGP3ARADDR_in[44] = (SAXIGP3ARADDR[44] !== 1'bz) && SAXIGP3ARADDR[44]; // rv 0 + assign SAXIGP3ARADDR_in[45] = (SAXIGP3ARADDR[45] !== 1'bz) && SAXIGP3ARADDR[45]; // rv 0 + assign SAXIGP3ARADDR_in[46] = (SAXIGP3ARADDR[46] !== 1'bz) && SAXIGP3ARADDR[46]; // rv 0 + assign SAXIGP3ARADDR_in[47] = (SAXIGP3ARADDR[47] !== 1'bz) && SAXIGP3ARADDR[47]; // rv 0 + assign SAXIGP3ARADDR_in[48] = (SAXIGP3ARADDR[48] !== 1'bz) && SAXIGP3ARADDR[48]; // rv 0 + assign SAXIGP3ARADDR_in[4] = (SAXIGP3ARADDR[4] !== 1'bz) && SAXIGP3ARADDR[4]; // rv 0 + assign SAXIGP3ARADDR_in[5] = (SAXIGP3ARADDR[5] !== 1'bz) && SAXIGP3ARADDR[5]; // rv 0 + assign SAXIGP3ARADDR_in[6] = (SAXIGP3ARADDR[6] !== 1'bz) && SAXIGP3ARADDR[6]; // rv 0 + assign SAXIGP3ARADDR_in[7] = (SAXIGP3ARADDR[7] !== 1'bz) && SAXIGP3ARADDR[7]; // rv 0 + assign SAXIGP3ARADDR_in[8] = (SAXIGP3ARADDR[8] !== 1'bz) && SAXIGP3ARADDR[8]; // rv 0 + assign SAXIGP3ARADDR_in[9] = (SAXIGP3ARADDR[9] !== 1'bz) && SAXIGP3ARADDR[9]; // rv 0 + assign SAXIGP3ARBURST_in[0] = (SAXIGP3ARBURST[0] !== 1'bz) && SAXIGP3ARBURST[0]; // rv 0 + assign SAXIGP3ARBURST_in[1] = (SAXIGP3ARBURST[1] !== 1'bz) && SAXIGP3ARBURST[1]; // rv 0 + assign SAXIGP3ARCACHE_in[0] = (SAXIGP3ARCACHE[0] !== 1'bz) && SAXIGP3ARCACHE[0]; // rv 0 + assign SAXIGP3ARCACHE_in[1] = (SAXIGP3ARCACHE[1] !== 1'bz) && SAXIGP3ARCACHE[1]; // rv 0 + assign SAXIGP3ARCACHE_in[2] = (SAXIGP3ARCACHE[2] !== 1'bz) && SAXIGP3ARCACHE[2]; // rv 0 + assign SAXIGP3ARCACHE_in[3] = (SAXIGP3ARCACHE[3] !== 1'bz) && SAXIGP3ARCACHE[3]; // rv 0 + assign SAXIGP3ARID_in[0] = (SAXIGP3ARID[0] !== 1'bz) && SAXIGP3ARID[0]; // rv 0 + assign SAXIGP3ARID_in[1] = (SAXIGP3ARID[1] !== 1'bz) && SAXIGP3ARID[1]; // rv 0 + assign SAXIGP3ARID_in[2] = (SAXIGP3ARID[2] !== 1'bz) && SAXIGP3ARID[2]; // rv 0 + assign SAXIGP3ARID_in[3] = (SAXIGP3ARID[3] !== 1'bz) && SAXIGP3ARID[3]; // rv 0 + assign SAXIGP3ARID_in[4] = (SAXIGP3ARID[4] !== 1'bz) && SAXIGP3ARID[4]; // rv 0 + assign SAXIGP3ARID_in[5] = (SAXIGP3ARID[5] !== 1'bz) && SAXIGP3ARID[5]; // rv 0 + assign SAXIGP3ARLEN_in[0] = (SAXIGP3ARLEN[0] !== 1'bz) && SAXIGP3ARLEN[0]; // rv 0 + assign SAXIGP3ARLEN_in[1] = (SAXIGP3ARLEN[1] !== 1'bz) && SAXIGP3ARLEN[1]; // rv 0 + assign SAXIGP3ARLEN_in[2] = (SAXIGP3ARLEN[2] !== 1'bz) && SAXIGP3ARLEN[2]; // rv 0 + assign SAXIGP3ARLEN_in[3] = (SAXIGP3ARLEN[3] !== 1'bz) && SAXIGP3ARLEN[3]; // rv 0 + assign SAXIGP3ARLEN_in[4] = (SAXIGP3ARLEN[4] !== 1'bz) && SAXIGP3ARLEN[4]; // rv 0 + assign SAXIGP3ARLEN_in[5] = (SAXIGP3ARLEN[5] !== 1'bz) && SAXIGP3ARLEN[5]; // rv 0 + assign SAXIGP3ARLEN_in[6] = (SAXIGP3ARLEN[6] !== 1'bz) && SAXIGP3ARLEN[6]; // rv 0 + assign SAXIGP3ARLEN_in[7] = (SAXIGP3ARLEN[7] !== 1'bz) && SAXIGP3ARLEN[7]; // rv 0 + assign SAXIGP3ARLOCK_in = (SAXIGP3ARLOCK !== 1'bz) && SAXIGP3ARLOCK; // rv 0 + assign SAXIGP3ARPROT_in[0] = (SAXIGP3ARPROT[0] !== 1'bz) && SAXIGP3ARPROT[0]; // rv 0 + assign SAXIGP3ARPROT_in[1] = (SAXIGP3ARPROT[1] !== 1'bz) && SAXIGP3ARPROT[1]; // rv 0 + assign SAXIGP3ARPROT_in[2] = (SAXIGP3ARPROT[2] !== 1'bz) && SAXIGP3ARPROT[2]; // rv 0 + assign SAXIGP3ARQOS_in[0] = (SAXIGP3ARQOS[0] !== 1'bz) && SAXIGP3ARQOS[0]; // rv 0 + assign SAXIGP3ARQOS_in[1] = (SAXIGP3ARQOS[1] !== 1'bz) && SAXIGP3ARQOS[1]; // rv 0 + assign SAXIGP3ARQOS_in[2] = (SAXIGP3ARQOS[2] !== 1'bz) && SAXIGP3ARQOS[2]; // rv 0 + assign SAXIGP3ARQOS_in[3] = (SAXIGP3ARQOS[3] !== 1'bz) && SAXIGP3ARQOS[3]; // rv 0 + assign SAXIGP3ARSIZE_in[0] = (SAXIGP3ARSIZE[0] !== 1'bz) && SAXIGP3ARSIZE[0]; // rv 0 + assign SAXIGP3ARSIZE_in[1] = (SAXIGP3ARSIZE[1] !== 1'bz) && SAXIGP3ARSIZE[1]; // rv 0 + assign SAXIGP3ARSIZE_in[2] = (SAXIGP3ARSIZE[2] !== 1'bz) && SAXIGP3ARSIZE[2]; // rv 0 + assign SAXIGP3ARUSER_in = (SAXIGP3ARUSER !== 1'bz) && SAXIGP3ARUSER; // rv 0 + assign SAXIGP3ARVALID_in = (SAXIGP3ARVALID !== 1'bz) && SAXIGP3ARVALID; // rv 0 + assign SAXIGP3AWADDR_in[0] = (SAXIGP3AWADDR[0] !== 1'bz) && SAXIGP3AWADDR[0]; // rv 0 + assign SAXIGP3AWADDR_in[10] = (SAXIGP3AWADDR[10] !== 1'bz) && SAXIGP3AWADDR[10]; // rv 0 + assign SAXIGP3AWADDR_in[11] = (SAXIGP3AWADDR[11] !== 1'bz) && SAXIGP3AWADDR[11]; // rv 0 + assign SAXIGP3AWADDR_in[12] = (SAXIGP3AWADDR[12] !== 1'bz) && SAXIGP3AWADDR[12]; // rv 0 + assign SAXIGP3AWADDR_in[13] = (SAXIGP3AWADDR[13] !== 1'bz) && SAXIGP3AWADDR[13]; // rv 0 + assign SAXIGP3AWADDR_in[14] = (SAXIGP3AWADDR[14] !== 1'bz) && SAXIGP3AWADDR[14]; // rv 0 + assign SAXIGP3AWADDR_in[15] = (SAXIGP3AWADDR[15] !== 1'bz) && SAXIGP3AWADDR[15]; // rv 0 + assign SAXIGP3AWADDR_in[16] = (SAXIGP3AWADDR[16] !== 1'bz) && SAXIGP3AWADDR[16]; // rv 0 + assign SAXIGP3AWADDR_in[17] = (SAXIGP3AWADDR[17] !== 1'bz) && SAXIGP3AWADDR[17]; // rv 0 + assign SAXIGP3AWADDR_in[18] = (SAXIGP3AWADDR[18] !== 1'bz) && SAXIGP3AWADDR[18]; // rv 0 + assign SAXIGP3AWADDR_in[19] = (SAXIGP3AWADDR[19] !== 1'bz) && SAXIGP3AWADDR[19]; // rv 0 + assign SAXIGP3AWADDR_in[1] = (SAXIGP3AWADDR[1] !== 1'bz) && SAXIGP3AWADDR[1]; // rv 0 + assign SAXIGP3AWADDR_in[20] = (SAXIGP3AWADDR[20] !== 1'bz) && SAXIGP3AWADDR[20]; // rv 0 + assign SAXIGP3AWADDR_in[21] = (SAXIGP3AWADDR[21] !== 1'bz) && SAXIGP3AWADDR[21]; // rv 0 + assign SAXIGP3AWADDR_in[22] = (SAXIGP3AWADDR[22] !== 1'bz) && SAXIGP3AWADDR[22]; // rv 0 + assign SAXIGP3AWADDR_in[23] = (SAXIGP3AWADDR[23] !== 1'bz) && SAXIGP3AWADDR[23]; // rv 0 + assign SAXIGP3AWADDR_in[24] = (SAXIGP3AWADDR[24] !== 1'bz) && SAXIGP3AWADDR[24]; // rv 0 + assign SAXIGP3AWADDR_in[25] = (SAXIGP3AWADDR[25] !== 1'bz) && SAXIGP3AWADDR[25]; // rv 0 + assign SAXIGP3AWADDR_in[26] = (SAXIGP3AWADDR[26] !== 1'bz) && SAXIGP3AWADDR[26]; // rv 0 + assign SAXIGP3AWADDR_in[27] = (SAXIGP3AWADDR[27] !== 1'bz) && SAXIGP3AWADDR[27]; // rv 0 + assign SAXIGP3AWADDR_in[28] = (SAXIGP3AWADDR[28] !== 1'bz) && SAXIGP3AWADDR[28]; // rv 0 + assign SAXIGP3AWADDR_in[29] = (SAXIGP3AWADDR[29] !== 1'bz) && SAXIGP3AWADDR[29]; // rv 0 + assign SAXIGP3AWADDR_in[2] = (SAXIGP3AWADDR[2] !== 1'bz) && SAXIGP3AWADDR[2]; // rv 0 + assign SAXIGP3AWADDR_in[30] = (SAXIGP3AWADDR[30] !== 1'bz) && SAXIGP3AWADDR[30]; // rv 0 + assign SAXIGP3AWADDR_in[31] = (SAXIGP3AWADDR[31] !== 1'bz) && SAXIGP3AWADDR[31]; // rv 0 + assign SAXIGP3AWADDR_in[32] = (SAXIGP3AWADDR[32] !== 1'bz) && SAXIGP3AWADDR[32]; // rv 0 + assign SAXIGP3AWADDR_in[33] = (SAXIGP3AWADDR[33] !== 1'bz) && SAXIGP3AWADDR[33]; // rv 0 + assign SAXIGP3AWADDR_in[34] = (SAXIGP3AWADDR[34] !== 1'bz) && SAXIGP3AWADDR[34]; // rv 0 + assign SAXIGP3AWADDR_in[35] = (SAXIGP3AWADDR[35] !== 1'bz) && SAXIGP3AWADDR[35]; // rv 0 + assign SAXIGP3AWADDR_in[36] = (SAXIGP3AWADDR[36] !== 1'bz) && SAXIGP3AWADDR[36]; // rv 0 + assign SAXIGP3AWADDR_in[37] = (SAXIGP3AWADDR[37] !== 1'bz) && SAXIGP3AWADDR[37]; // rv 0 + assign SAXIGP3AWADDR_in[38] = (SAXIGP3AWADDR[38] !== 1'bz) && SAXIGP3AWADDR[38]; // rv 0 + assign SAXIGP3AWADDR_in[39] = (SAXIGP3AWADDR[39] !== 1'bz) && SAXIGP3AWADDR[39]; // rv 0 + assign SAXIGP3AWADDR_in[3] = (SAXIGP3AWADDR[3] !== 1'bz) && SAXIGP3AWADDR[3]; // rv 0 + assign SAXIGP3AWADDR_in[40] = (SAXIGP3AWADDR[40] !== 1'bz) && SAXIGP3AWADDR[40]; // rv 0 + assign SAXIGP3AWADDR_in[41] = (SAXIGP3AWADDR[41] !== 1'bz) && SAXIGP3AWADDR[41]; // rv 0 + assign SAXIGP3AWADDR_in[42] = (SAXIGP3AWADDR[42] !== 1'bz) && SAXIGP3AWADDR[42]; // rv 0 + assign SAXIGP3AWADDR_in[43] = (SAXIGP3AWADDR[43] !== 1'bz) && SAXIGP3AWADDR[43]; // rv 0 + assign SAXIGP3AWADDR_in[44] = (SAXIGP3AWADDR[44] !== 1'bz) && SAXIGP3AWADDR[44]; // rv 0 + assign SAXIGP3AWADDR_in[45] = (SAXIGP3AWADDR[45] !== 1'bz) && SAXIGP3AWADDR[45]; // rv 0 + assign SAXIGP3AWADDR_in[46] = (SAXIGP3AWADDR[46] !== 1'bz) && SAXIGP3AWADDR[46]; // rv 0 + assign SAXIGP3AWADDR_in[47] = (SAXIGP3AWADDR[47] !== 1'bz) && SAXIGP3AWADDR[47]; // rv 0 + assign SAXIGP3AWADDR_in[48] = (SAXIGP3AWADDR[48] !== 1'bz) && SAXIGP3AWADDR[48]; // rv 0 + assign SAXIGP3AWADDR_in[4] = (SAXIGP3AWADDR[4] !== 1'bz) && SAXIGP3AWADDR[4]; // rv 0 + assign SAXIGP3AWADDR_in[5] = (SAXIGP3AWADDR[5] !== 1'bz) && SAXIGP3AWADDR[5]; // rv 0 + assign SAXIGP3AWADDR_in[6] = (SAXIGP3AWADDR[6] !== 1'bz) && SAXIGP3AWADDR[6]; // rv 0 + assign SAXIGP3AWADDR_in[7] = (SAXIGP3AWADDR[7] !== 1'bz) && SAXIGP3AWADDR[7]; // rv 0 + assign SAXIGP3AWADDR_in[8] = (SAXIGP3AWADDR[8] !== 1'bz) && SAXIGP3AWADDR[8]; // rv 0 + assign SAXIGP3AWADDR_in[9] = (SAXIGP3AWADDR[9] !== 1'bz) && SAXIGP3AWADDR[9]; // rv 0 + assign SAXIGP3AWBURST_in[0] = (SAXIGP3AWBURST[0] !== 1'bz) && SAXIGP3AWBURST[0]; // rv 0 + assign SAXIGP3AWBURST_in[1] = (SAXIGP3AWBURST[1] !== 1'bz) && SAXIGP3AWBURST[1]; // rv 0 + assign SAXIGP3AWCACHE_in[0] = (SAXIGP3AWCACHE[0] !== 1'bz) && SAXIGP3AWCACHE[0]; // rv 0 + assign SAXIGP3AWCACHE_in[1] = (SAXIGP3AWCACHE[1] !== 1'bz) && SAXIGP3AWCACHE[1]; // rv 0 + assign SAXIGP3AWCACHE_in[2] = (SAXIGP3AWCACHE[2] !== 1'bz) && SAXIGP3AWCACHE[2]; // rv 0 + assign SAXIGP3AWCACHE_in[3] = (SAXIGP3AWCACHE[3] !== 1'bz) && SAXIGP3AWCACHE[3]; // rv 0 + assign SAXIGP3AWID_in[0] = (SAXIGP3AWID[0] !== 1'bz) && SAXIGP3AWID[0]; // rv 0 + assign SAXIGP3AWID_in[1] = (SAXIGP3AWID[1] !== 1'bz) && SAXIGP3AWID[1]; // rv 0 + assign SAXIGP3AWID_in[2] = (SAXIGP3AWID[2] !== 1'bz) && SAXIGP3AWID[2]; // rv 0 + assign SAXIGP3AWID_in[3] = (SAXIGP3AWID[3] !== 1'bz) && SAXIGP3AWID[3]; // rv 0 + assign SAXIGP3AWID_in[4] = (SAXIGP3AWID[4] !== 1'bz) && SAXIGP3AWID[4]; // rv 0 + assign SAXIGP3AWID_in[5] = (SAXIGP3AWID[5] !== 1'bz) && SAXIGP3AWID[5]; // rv 0 + assign SAXIGP3AWLEN_in[0] = (SAXIGP3AWLEN[0] !== 1'bz) && SAXIGP3AWLEN[0]; // rv 0 + assign SAXIGP3AWLEN_in[1] = (SAXIGP3AWLEN[1] !== 1'bz) && SAXIGP3AWLEN[1]; // rv 0 + assign SAXIGP3AWLEN_in[2] = (SAXIGP3AWLEN[2] !== 1'bz) && SAXIGP3AWLEN[2]; // rv 0 + assign SAXIGP3AWLEN_in[3] = (SAXIGP3AWLEN[3] !== 1'bz) && SAXIGP3AWLEN[3]; // rv 0 + assign SAXIGP3AWLEN_in[4] = (SAXIGP3AWLEN[4] !== 1'bz) && SAXIGP3AWLEN[4]; // rv 0 + assign SAXIGP3AWLEN_in[5] = (SAXIGP3AWLEN[5] !== 1'bz) && SAXIGP3AWLEN[5]; // rv 0 + assign SAXIGP3AWLEN_in[6] = (SAXIGP3AWLEN[6] !== 1'bz) && SAXIGP3AWLEN[6]; // rv 0 + assign SAXIGP3AWLEN_in[7] = (SAXIGP3AWLEN[7] !== 1'bz) && SAXIGP3AWLEN[7]; // rv 0 + assign SAXIGP3AWLOCK_in = (SAXIGP3AWLOCK !== 1'bz) && SAXIGP3AWLOCK; // rv 0 + assign SAXIGP3AWPROT_in[0] = (SAXIGP3AWPROT[0] !== 1'bz) && SAXIGP3AWPROT[0]; // rv 0 + assign SAXIGP3AWPROT_in[1] = (SAXIGP3AWPROT[1] !== 1'bz) && SAXIGP3AWPROT[1]; // rv 0 + assign SAXIGP3AWPROT_in[2] = (SAXIGP3AWPROT[2] !== 1'bz) && SAXIGP3AWPROT[2]; // rv 0 + assign SAXIGP3AWQOS_in[0] = (SAXIGP3AWQOS[0] !== 1'bz) && SAXIGP3AWQOS[0]; // rv 0 + assign SAXIGP3AWQOS_in[1] = (SAXIGP3AWQOS[1] !== 1'bz) && SAXIGP3AWQOS[1]; // rv 0 + assign SAXIGP3AWQOS_in[2] = (SAXIGP3AWQOS[2] !== 1'bz) && SAXIGP3AWQOS[2]; // rv 0 + assign SAXIGP3AWQOS_in[3] = (SAXIGP3AWQOS[3] !== 1'bz) && SAXIGP3AWQOS[3]; // rv 0 + assign SAXIGP3AWSIZE_in[0] = (SAXIGP3AWSIZE[0] !== 1'bz) && SAXIGP3AWSIZE[0]; // rv 0 + assign SAXIGP3AWSIZE_in[1] = (SAXIGP3AWSIZE[1] !== 1'bz) && SAXIGP3AWSIZE[1]; // rv 0 + assign SAXIGP3AWSIZE_in[2] = (SAXIGP3AWSIZE[2] !== 1'bz) && SAXIGP3AWSIZE[2]; // rv 0 + assign SAXIGP3AWUSER_in = (SAXIGP3AWUSER !== 1'bz) && SAXIGP3AWUSER; // rv 0 + assign SAXIGP3AWVALID_in = (SAXIGP3AWVALID !== 1'bz) && SAXIGP3AWVALID; // rv 0 + assign SAXIGP3BREADY_in = (SAXIGP3BREADY !== 1'bz) && SAXIGP3BREADY; // rv 0 + assign SAXIGP3RCLK_in = (SAXIGP3RCLK !== 1'bz) && SAXIGP3RCLK; // rv 0 + assign SAXIGP3RREADY_in = (SAXIGP3RREADY !== 1'bz) && SAXIGP3RREADY; // rv 0 + assign SAXIGP3WCLK_in = (SAXIGP3WCLK !== 1'bz) && SAXIGP3WCLK; // rv 0 + assign SAXIGP3WDATA_in[0] = (SAXIGP3WDATA[0] !== 1'bz) && SAXIGP3WDATA[0]; // rv 0 + assign SAXIGP3WDATA_in[100] = (SAXIGP3WDATA[100] !== 1'bz) && SAXIGP3WDATA[100]; // rv 0 + assign SAXIGP3WDATA_in[101] = (SAXIGP3WDATA[101] !== 1'bz) && SAXIGP3WDATA[101]; // rv 0 + assign SAXIGP3WDATA_in[102] = (SAXIGP3WDATA[102] !== 1'bz) && SAXIGP3WDATA[102]; // rv 0 + assign SAXIGP3WDATA_in[103] = (SAXIGP3WDATA[103] !== 1'bz) && SAXIGP3WDATA[103]; // rv 0 + assign SAXIGP3WDATA_in[104] = (SAXIGP3WDATA[104] !== 1'bz) && SAXIGP3WDATA[104]; // rv 0 + assign SAXIGP3WDATA_in[105] = (SAXIGP3WDATA[105] !== 1'bz) && SAXIGP3WDATA[105]; // rv 0 + assign SAXIGP3WDATA_in[106] = (SAXIGP3WDATA[106] !== 1'bz) && SAXIGP3WDATA[106]; // rv 0 + assign SAXIGP3WDATA_in[107] = (SAXIGP3WDATA[107] !== 1'bz) && SAXIGP3WDATA[107]; // rv 0 + assign SAXIGP3WDATA_in[108] = (SAXIGP3WDATA[108] !== 1'bz) && SAXIGP3WDATA[108]; // rv 0 + assign SAXIGP3WDATA_in[109] = (SAXIGP3WDATA[109] !== 1'bz) && SAXIGP3WDATA[109]; // rv 0 + assign SAXIGP3WDATA_in[10] = (SAXIGP3WDATA[10] !== 1'bz) && SAXIGP3WDATA[10]; // rv 0 + assign SAXIGP3WDATA_in[110] = (SAXIGP3WDATA[110] !== 1'bz) && SAXIGP3WDATA[110]; // rv 0 + assign SAXIGP3WDATA_in[111] = (SAXIGP3WDATA[111] !== 1'bz) && SAXIGP3WDATA[111]; // rv 0 + assign SAXIGP3WDATA_in[112] = (SAXIGP3WDATA[112] !== 1'bz) && SAXIGP3WDATA[112]; // rv 0 + assign SAXIGP3WDATA_in[113] = (SAXIGP3WDATA[113] !== 1'bz) && SAXIGP3WDATA[113]; // rv 0 + assign SAXIGP3WDATA_in[114] = (SAXIGP3WDATA[114] !== 1'bz) && SAXIGP3WDATA[114]; // rv 0 + assign SAXIGP3WDATA_in[115] = (SAXIGP3WDATA[115] !== 1'bz) && SAXIGP3WDATA[115]; // rv 0 + assign SAXIGP3WDATA_in[116] = (SAXIGP3WDATA[116] !== 1'bz) && SAXIGP3WDATA[116]; // rv 0 + assign SAXIGP3WDATA_in[117] = (SAXIGP3WDATA[117] !== 1'bz) && SAXIGP3WDATA[117]; // rv 0 + assign SAXIGP3WDATA_in[118] = (SAXIGP3WDATA[118] !== 1'bz) && SAXIGP3WDATA[118]; // rv 0 + assign SAXIGP3WDATA_in[119] = (SAXIGP3WDATA[119] !== 1'bz) && SAXIGP3WDATA[119]; // rv 0 + assign SAXIGP3WDATA_in[11] = (SAXIGP3WDATA[11] !== 1'bz) && SAXIGP3WDATA[11]; // rv 0 + assign SAXIGP3WDATA_in[120] = (SAXIGP3WDATA[120] !== 1'bz) && SAXIGP3WDATA[120]; // rv 0 + assign SAXIGP3WDATA_in[121] = (SAXIGP3WDATA[121] !== 1'bz) && SAXIGP3WDATA[121]; // rv 0 + assign SAXIGP3WDATA_in[122] = (SAXIGP3WDATA[122] !== 1'bz) && SAXIGP3WDATA[122]; // rv 0 + assign SAXIGP3WDATA_in[123] = (SAXIGP3WDATA[123] !== 1'bz) && SAXIGP3WDATA[123]; // rv 0 + assign SAXIGP3WDATA_in[124] = (SAXIGP3WDATA[124] !== 1'bz) && SAXIGP3WDATA[124]; // rv 0 + assign SAXIGP3WDATA_in[125] = (SAXIGP3WDATA[125] !== 1'bz) && SAXIGP3WDATA[125]; // rv 0 + assign SAXIGP3WDATA_in[126] = (SAXIGP3WDATA[126] !== 1'bz) && SAXIGP3WDATA[126]; // rv 0 + assign SAXIGP3WDATA_in[127] = (SAXIGP3WDATA[127] !== 1'bz) && SAXIGP3WDATA[127]; // rv 0 + assign SAXIGP3WDATA_in[12] = (SAXIGP3WDATA[12] !== 1'bz) && SAXIGP3WDATA[12]; // rv 0 + assign SAXIGP3WDATA_in[13] = (SAXIGP3WDATA[13] !== 1'bz) && SAXIGP3WDATA[13]; // rv 0 + assign SAXIGP3WDATA_in[14] = (SAXIGP3WDATA[14] !== 1'bz) && SAXIGP3WDATA[14]; // rv 0 + assign SAXIGP3WDATA_in[15] = (SAXIGP3WDATA[15] !== 1'bz) && SAXIGP3WDATA[15]; // rv 0 + assign SAXIGP3WDATA_in[16] = (SAXIGP3WDATA[16] !== 1'bz) && SAXIGP3WDATA[16]; // rv 0 + assign SAXIGP3WDATA_in[17] = (SAXIGP3WDATA[17] !== 1'bz) && SAXIGP3WDATA[17]; // rv 0 + assign SAXIGP3WDATA_in[18] = (SAXIGP3WDATA[18] !== 1'bz) && SAXIGP3WDATA[18]; // rv 0 + assign SAXIGP3WDATA_in[19] = (SAXIGP3WDATA[19] !== 1'bz) && SAXIGP3WDATA[19]; // rv 0 + assign SAXIGP3WDATA_in[1] = (SAXIGP3WDATA[1] !== 1'bz) && SAXIGP3WDATA[1]; // rv 0 + assign SAXIGP3WDATA_in[20] = (SAXIGP3WDATA[20] !== 1'bz) && SAXIGP3WDATA[20]; // rv 0 + assign SAXIGP3WDATA_in[21] = (SAXIGP3WDATA[21] !== 1'bz) && SAXIGP3WDATA[21]; // rv 0 + assign SAXIGP3WDATA_in[22] = (SAXIGP3WDATA[22] !== 1'bz) && SAXIGP3WDATA[22]; // rv 0 + assign SAXIGP3WDATA_in[23] = (SAXIGP3WDATA[23] !== 1'bz) && SAXIGP3WDATA[23]; // rv 0 + assign SAXIGP3WDATA_in[24] = (SAXIGP3WDATA[24] !== 1'bz) && SAXIGP3WDATA[24]; // rv 0 + assign SAXIGP3WDATA_in[25] = (SAXIGP3WDATA[25] !== 1'bz) && SAXIGP3WDATA[25]; // rv 0 + assign SAXIGP3WDATA_in[26] = (SAXIGP3WDATA[26] !== 1'bz) && SAXIGP3WDATA[26]; // rv 0 + assign SAXIGP3WDATA_in[27] = (SAXIGP3WDATA[27] !== 1'bz) && SAXIGP3WDATA[27]; // rv 0 + assign SAXIGP3WDATA_in[28] = (SAXIGP3WDATA[28] !== 1'bz) && SAXIGP3WDATA[28]; // rv 0 + assign SAXIGP3WDATA_in[29] = (SAXIGP3WDATA[29] !== 1'bz) && SAXIGP3WDATA[29]; // rv 0 + assign SAXIGP3WDATA_in[2] = (SAXIGP3WDATA[2] !== 1'bz) && SAXIGP3WDATA[2]; // rv 0 + assign SAXIGP3WDATA_in[30] = (SAXIGP3WDATA[30] !== 1'bz) && SAXIGP3WDATA[30]; // rv 0 + assign SAXIGP3WDATA_in[31] = (SAXIGP3WDATA[31] !== 1'bz) && SAXIGP3WDATA[31]; // rv 0 + assign SAXIGP3WDATA_in[32] = (SAXIGP3WDATA[32] !== 1'bz) && SAXIGP3WDATA[32]; // rv 0 + assign SAXIGP3WDATA_in[33] = (SAXIGP3WDATA[33] !== 1'bz) && SAXIGP3WDATA[33]; // rv 0 + assign SAXIGP3WDATA_in[34] = (SAXIGP3WDATA[34] !== 1'bz) && SAXIGP3WDATA[34]; // rv 0 + assign SAXIGP3WDATA_in[35] = (SAXIGP3WDATA[35] !== 1'bz) && SAXIGP3WDATA[35]; // rv 0 + assign SAXIGP3WDATA_in[36] = (SAXIGP3WDATA[36] !== 1'bz) && SAXIGP3WDATA[36]; // rv 0 + assign SAXIGP3WDATA_in[37] = (SAXIGP3WDATA[37] !== 1'bz) && SAXIGP3WDATA[37]; // rv 0 + assign SAXIGP3WDATA_in[38] = (SAXIGP3WDATA[38] !== 1'bz) && SAXIGP3WDATA[38]; // rv 0 + assign SAXIGP3WDATA_in[39] = (SAXIGP3WDATA[39] !== 1'bz) && SAXIGP3WDATA[39]; // rv 0 + assign SAXIGP3WDATA_in[3] = (SAXIGP3WDATA[3] !== 1'bz) && SAXIGP3WDATA[3]; // rv 0 + assign SAXIGP3WDATA_in[40] = (SAXIGP3WDATA[40] !== 1'bz) && SAXIGP3WDATA[40]; // rv 0 + assign SAXIGP3WDATA_in[41] = (SAXIGP3WDATA[41] !== 1'bz) && SAXIGP3WDATA[41]; // rv 0 + assign SAXIGP3WDATA_in[42] = (SAXIGP3WDATA[42] !== 1'bz) && SAXIGP3WDATA[42]; // rv 0 + assign SAXIGP3WDATA_in[43] = (SAXIGP3WDATA[43] !== 1'bz) && SAXIGP3WDATA[43]; // rv 0 + assign SAXIGP3WDATA_in[44] = (SAXIGP3WDATA[44] !== 1'bz) && SAXIGP3WDATA[44]; // rv 0 + assign SAXIGP3WDATA_in[45] = (SAXIGP3WDATA[45] !== 1'bz) && SAXIGP3WDATA[45]; // rv 0 + assign SAXIGP3WDATA_in[46] = (SAXIGP3WDATA[46] !== 1'bz) && SAXIGP3WDATA[46]; // rv 0 + assign SAXIGP3WDATA_in[47] = (SAXIGP3WDATA[47] !== 1'bz) && SAXIGP3WDATA[47]; // rv 0 + assign SAXIGP3WDATA_in[48] = (SAXIGP3WDATA[48] !== 1'bz) && SAXIGP3WDATA[48]; // rv 0 + assign SAXIGP3WDATA_in[49] = (SAXIGP3WDATA[49] !== 1'bz) && SAXIGP3WDATA[49]; // rv 0 + assign SAXIGP3WDATA_in[4] = (SAXIGP3WDATA[4] !== 1'bz) && SAXIGP3WDATA[4]; // rv 0 + assign SAXIGP3WDATA_in[50] = (SAXIGP3WDATA[50] !== 1'bz) && SAXIGP3WDATA[50]; // rv 0 + assign SAXIGP3WDATA_in[51] = (SAXIGP3WDATA[51] !== 1'bz) && SAXIGP3WDATA[51]; // rv 0 + assign SAXIGP3WDATA_in[52] = (SAXIGP3WDATA[52] !== 1'bz) && SAXIGP3WDATA[52]; // rv 0 + assign SAXIGP3WDATA_in[53] = (SAXIGP3WDATA[53] !== 1'bz) && SAXIGP3WDATA[53]; // rv 0 + assign SAXIGP3WDATA_in[54] = (SAXIGP3WDATA[54] !== 1'bz) && SAXIGP3WDATA[54]; // rv 0 + assign SAXIGP3WDATA_in[55] = (SAXIGP3WDATA[55] !== 1'bz) && SAXIGP3WDATA[55]; // rv 0 + assign SAXIGP3WDATA_in[56] = (SAXIGP3WDATA[56] !== 1'bz) && SAXIGP3WDATA[56]; // rv 0 + assign SAXIGP3WDATA_in[57] = (SAXIGP3WDATA[57] !== 1'bz) && SAXIGP3WDATA[57]; // rv 0 + assign SAXIGP3WDATA_in[58] = (SAXIGP3WDATA[58] !== 1'bz) && SAXIGP3WDATA[58]; // rv 0 + assign SAXIGP3WDATA_in[59] = (SAXIGP3WDATA[59] !== 1'bz) && SAXIGP3WDATA[59]; // rv 0 + assign SAXIGP3WDATA_in[5] = (SAXIGP3WDATA[5] !== 1'bz) && SAXIGP3WDATA[5]; // rv 0 + assign SAXIGP3WDATA_in[60] = (SAXIGP3WDATA[60] !== 1'bz) && SAXIGP3WDATA[60]; // rv 0 + assign SAXIGP3WDATA_in[61] = (SAXIGP3WDATA[61] !== 1'bz) && SAXIGP3WDATA[61]; // rv 0 + assign SAXIGP3WDATA_in[62] = (SAXIGP3WDATA[62] !== 1'bz) && SAXIGP3WDATA[62]; // rv 0 + assign SAXIGP3WDATA_in[63] = (SAXIGP3WDATA[63] !== 1'bz) && SAXIGP3WDATA[63]; // rv 0 + assign SAXIGP3WDATA_in[64] = (SAXIGP3WDATA[64] !== 1'bz) && SAXIGP3WDATA[64]; // rv 0 + assign SAXIGP3WDATA_in[65] = (SAXIGP3WDATA[65] !== 1'bz) && SAXIGP3WDATA[65]; // rv 0 + assign SAXIGP3WDATA_in[66] = (SAXIGP3WDATA[66] !== 1'bz) && SAXIGP3WDATA[66]; // rv 0 + assign SAXIGP3WDATA_in[67] = (SAXIGP3WDATA[67] !== 1'bz) && SAXIGP3WDATA[67]; // rv 0 + assign SAXIGP3WDATA_in[68] = (SAXIGP3WDATA[68] !== 1'bz) && SAXIGP3WDATA[68]; // rv 0 + assign SAXIGP3WDATA_in[69] = (SAXIGP3WDATA[69] !== 1'bz) && SAXIGP3WDATA[69]; // rv 0 + assign SAXIGP3WDATA_in[6] = (SAXIGP3WDATA[6] !== 1'bz) && SAXIGP3WDATA[6]; // rv 0 + assign SAXIGP3WDATA_in[70] = (SAXIGP3WDATA[70] !== 1'bz) && SAXIGP3WDATA[70]; // rv 0 + assign SAXIGP3WDATA_in[71] = (SAXIGP3WDATA[71] !== 1'bz) && SAXIGP3WDATA[71]; // rv 0 + assign SAXIGP3WDATA_in[72] = (SAXIGP3WDATA[72] !== 1'bz) && SAXIGP3WDATA[72]; // rv 0 + assign SAXIGP3WDATA_in[73] = (SAXIGP3WDATA[73] !== 1'bz) && SAXIGP3WDATA[73]; // rv 0 + assign SAXIGP3WDATA_in[74] = (SAXIGP3WDATA[74] !== 1'bz) && SAXIGP3WDATA[74]; // rv 0 + assign SAXIGP3WDATA_in[75] = (SAXIGP3WDATA[75] !== 1'bz) && SAXIGP3WDATA[75]; // rv 0 + assign SAXIGP3WDATA_in[76] = (SAXIGP3WDATA[76] !== 1'bz) && SAXIGP3WDATA[76]; // rv 0 + assign SAXIGP3WDATA_in[77] = (SAXIGP3WDATA[77] !== 1'bz) && SAXIGP3WDATA[77]; // rv 0 + assign SAXIGP3WDATA_in[78] = (SAXIGP3WDATA[78] !== 1'bz) && SAXIGP3WDATA[78]; // rv 0 + assign SAXIGP3WDATA_in[79] = (SAXIGP3WDATA[79] !== 1'bz) && SAXIGP3WDATA[79]; // rv 0 + assign SAXIGP3WDATA_in[7] = (SAXIGP3WDATA[7] !== 1'bz) && SAXIGP3WDATA[7]; // rv 0 + assign SAXIGP3WDATA_in[80] = (SAXIGP3WDATA[80] !== 1'bz) && SAXIGP3WDATA[80]; // rv 0 + assign SAXIGP3WDATA_in[81] = (SAXIGP3WDATA[81] !== 1'bz) && SAXIGP3WDATA[81]; // rv 0 + assign SAXIGP3WDATA_in[82] = (SAXIGP3WDATA[82] !== 1'bz) && SAXIGP3WDATA[82]; // rv 0 + assign SAXIGP3WDATA_in[83] = (SAXIGP3WDATA[83] !== 1'bz) && SAXIGP3WDATA[83]; // rv 0 + assign SAXIGP3WDATA_in[84] = (SAXIGP3WDATA[84] !== 1'bz) && SAXIGP3WDATA[84]; // rv 0 + assign SAXIGP3WDATA_in[85] = (SAXIGP3WDATA[85] !== 1'bz) && SAXIGP3WDATA[85]; // rv 0 + assign SAXIGP3WDATA_in[86] = (SAXIGP3WDATA[86] !== 1'bz) && SAXIGP3WDATA[86]; // rv 0 + assign SAXIGP3WDATA_in[87] = (SAXIGP3WDATA[87] !== 1'bz) && SAXIGP3WDATA[87]; // rv 0 + assign SAXIGP3WDATA_in[88] = (SAXIGP3WDATA[88] !== 1'bz) && SAXIGP3WDATA[88]; // rv 0 + assign SAXIGP3WDATA_in[89] = (SAXIGP3WDATA[89] !== 1'bz) && SAXIGP3WDATA[89]; // rv 0 + assign SAXIGP3WDATA_in[8] = (SAXIGP3WDATA[8] !== 1'bz) && SAXIGP3WDATA[8]; // rv 0 + assign SAXIGP3WDATA_in[90] = (SAXIGP3WDATA[90] !== 1'bz) && SAXIGP3WDATA[90]; // rv 0 + assign SAXIGP3WDATA_in[91] = (SAXIGP3WDATA[91] !== 1'bz) && SAXIGP3WDATA[91]; // rv 0 + assign SAXIGP3WDATA_in[92] = (SAXIGP3WDATA[92] !== 1'bz) && SAXIGP3WDATA[92]; // rv 0 + assign SAXIGP3WDATA_in[93] = (SAXIGP3WDATA[93] !== 1'bz) && SAXIGP3WDATA[93]; // rv 0 + assign SAXIGP3WDATA_in[94] = (SAXIGP3WDATA[94] !== 1'bz) && SAXIGP3WDATA[94]; // rv 0 + assign SAXIGP3WDATA_in[95] = (SAXIGP3WDATA[95] !== 1'bz) && SAXIGP3WDATA[95]; // rv 0 + assign SAXIGP3WDATA_in[96] = (SAXIGP3WDATA[96] !== 1'bz) && SAXIGP3WDATA[96]; // rv 0 + assign SAXIGP3WDATA_in[97] = (SAXIGP3WDATA[97] !== 1'bz) && SAXIGP3WDATA[97]; // rv 0 + assign SAXIGP3WDATA_in[98] = (SAXIGP3WDATA[98] !== 1'bz) && SAXIGP3WDATA[98]; // rv 0 + assign SAXIGP3WDATA_in[99] = (SAXIGP3WDATA[99] !== 1'bz) && SAXIGP3WDATA[99]; // rv 0 + assign SAXIGP3WDATA_in[9] = (SAXIGP3WDATA[9] !== 1'bz) && SAXIGP3WDATA[9]; // rv 0 + assign SAXIGP3WLAST_in = (SAXIGP3WLAST !== 1'bz) && SAXIGP3WLAST; // rv 0 + assign SAXIGP3WSTRB_in[0] = (SAXIGP3WSTRB[0] !== 1'bz) && SAXIGP3WSTRB[0]; // rv 0 + assign SAXIGP3WSTRB_in[10] = (SAXIGP3WSTRB[10] !== 1'bz) && SAXIGP3WSTRB[10]; // rv 0 + assign SAXIGP3WSTRB_in[11] = (SAXIGP3WSTRB[11] !== 1'bz) && SAXIGP3WSTRB[11]; // rv 0 + assign SAXIGP3WSTRB_in[12] = (SAXIGP3WSTRB[12] !== 1'bz) && SAXIGP3WSTRB[12]; // rv 0 + assign SAXIGP3WSTRB_in[13] = (SAXIGP3WSTRB[13] !== 1'bz) && SAXIGP3WSTRB[13]; // rv 0 + assign SAXIGP3WSTRB_in[14] = (SAXIGP3WSTRB[14] !== 1'bz) && SAXIGP3WSTRB[14]; // rv 0 + assign SAXIGP3WSTRB_in[15] = (SAXIGP3WSTRB[15] !== 1'bz) && SAXIGP3WSTRB[15]; // rv 0 + assign SAXIGP3WSTRB_in[1] = (SAXIGP3WSTRB[1] !== 1'bz) && SAXIGP3WSTRB[1]; // rv 0 + assign SAXIGP3WSTRB_in[2] = (SAXIGP3WSTRB[2] !== 1'bz) && SAXIGP3WSTRB[2]; // rv 0 + assign SAXIGP3WSTRB_in[3] = (SAXIGP3WSTRB[3] !== 1'bz) && SAXIGP3WSTRB[3]; // rv 0 + assign SAXIGP3WSTRB_in[4] = (SAXIGP3WSTRB[4] !== 1'bz) && SAXIGP3WSTRB[4]; // rv 0 + assign SAXIGP3WSTRB_in[5] = (SAXIGP3WSTRB[5] !== 1'bz) && SAXIGP3WSTRB[5]; // rv 0 + assign SAXIGP3WSTRB_in[6] = (SAXIGP3WSTRB[6] !== 1'bz) && SAXIGP3WSTRB[6]; // rv 0 + assign SAXIGP3WSTRB_in[7] = (SAXIGP3WSTRB[7] !== 1'bz) && SAXIGP3WSTRB[7]; // rv 0 + assign SAXIGP3WSTRB_in[8] = (SAXIGP3WSTRB[8] !== 1'bz) && SAXIGP3WSTRB[8]; // rv 0 + assign SAXIGP3WSTRB_in[9] = (SAXIGP3WSTRB[9] !== 1'bz) && SAXIGP3WSTRB[9]; // rv 0 + assign SAXIGP3WVALID_in = (SAXIGP3WVALID !== 1'bz) && SAXIGP3WVALID; // rv 0 + assign SAXIGP4ARADDR_in[0] = (SAXIGP4ARADDR[0] !== 1'bz) && SAXIGP4ARADDR[0]; // rv 0 + assign SAXIGP4ARADDR_in[10] = (SAXIGP4ARADDR[10] !== 1'bz) && SAXIGP4ARADDR[10]; // rv 0 + assign SAXIGP4ARADDR_in[11] = (SAXIGP4ARADDR[11] !== 1'bz) && SAXIGP4ARADDR[11]; // rv 0 + assign SAXIGP4ARADDR_in[12] = (SAXIGP4ARADDR[12] !== 1'bz) && SAXIGP4ARADDR[12]; // rv 0 + assign SAXIGP4ARADDR_in[13] = (SAXIGP4ARADDR[13] !== 1'bz) && SAXIGP4ARADDR[13]; // rv 0 + assign SAXIGP4ARADDR_in[14] = (SAXIGP4ARADDR[14] !== 1'bz) && SAXIGP4ARADDR[14]; // rv 0 + assign SAXIGP4ARADDR_in[15] = (SAXIGP4ARADDR[15] !== 1'bz) && SAXIGP4ARADDR[15]; // rv 0 + assign SAXIGP4ARADDR_in[16] = (SAXIGP4ARADDR[16] !== 1'bz) && SAXIGP4ARADDR[16]; // rv 0 + assign SAXIGP4ARADDR_in[17] = (SAXIGP4ARADDR[17] !== 1'bz) && SAXIGP4ARADDR[17]; // rv 0 + assign SAXIGP4ARADDR_in[18] = (SAXIGP4ARADDR[18] !== 1'bz) && SAXIGP4ARADDR[18]; // rv 0 + assign SAXIGP4ARADDR_in[19] = (SAXIGP4ARADDR[19] !== 1'bz) && SAXIGP4ARADDR[19]; // rv 0 + assign SAXIGP4ARADDR_in[1] = (SAXIGP4ARADDR[1] !== 1'bz) && SAXIGP4ARADDR[1]; // rv 0 + assign SAXIGP4ARADDR_in[20] = (SAXIGP4ARADDR[20] !== 1'bz) && SAXIGP4ARADDR[20]; // rv 0 + assign SAXIGP4ARADDR_in[21] = (SAXIGP4ARADDR[21] !== 1'bz) && SAXIGP4ARADDR[21]; // rv 0 + assign SAXIGP4ARADDR_in[22] = (SAXIGP4ARADDR[22] !== 1'bz) && SAXIGP4ARADDR[22]; // rv 0 + assign SAXIGP4ARADDR_in[23] = (SAXIGP4ARADDR[23] !== 1'bz) && SAXIGP4ARADDR[23]; // rv 0 + assign SAXIGP4ARADDR_in[24] = (SAXIGP4ARADDR[24] !== 1'bz) && SAXIGP4ARADDR[24]; // rv 0 + assign SAXIGP4ARADDR_in[25] = (SAXIGP4ARADDR[25] !== 1'bz) && SAXIGP4ARADDR[25]; // rv 0 + assign SAXIGP4ARADDR_in[26] = (SAXIGP4ARADDR[26] !== 1'bz) && SAXIGP4ARADDR[26]; // rv 0 + assign SAXIGP4ARADDR_in[27] = (SAXIGP4ARADDR[27] !== 1'bz) && SAXIGP4ARADDR[27]; // rv 0 + assign SAXIGP4ARADDR_in[28] = (SAXIGP4ARADDR[28] !== 1'bz) && SAXIGP4ARADDR[28]; // rv 0 + assign SAXIGP4ARADDR_in[29] = (SAXIGP4ARADDR[29] !== 1'bz) && SAXIGP4ARADDR[29]; // rv 0 + assign SAXIGP4ARADDR_in[2] = (SAXIGP4ARADDR[2] !== 1'bz) && SAXIGP4ARADDR[2]; // rv 0 + assign SAXIGP4ARADDR_in[30] = (SAXIGP4ARADDR[30] !== 1'bz) && SAXIGP4ARADDR[30]; // rv 0 + assign SAXIGP4ARADDR_in[31] = (SAXIGP4ARADDR[31] !== 1'bz) && SAXIGP4ARADDR[31]; // rv 0 + assign SAXIGP4ARADDR_in[32] = (SAXIGP4ARADDR[32] !== 1'bz) && SAXIGP4ARADDR[32]; // rv 0 + assign SAXIGP4ARADDR_in[33] = (SAXIGP4ARADDR[33] !== 1'bz) && SAXIGP4ARADDR[33]; // rv 0 + assign SAXIGP4ARADDR_in[34] = (SAXIGP4ARADDR[34] !== 1'bz) && SAXIGP4ARADDR[34]; // rv 0 + assign SAXIGP4ARADDR_in[35] = (SAXIGP4ARADDR[35] !== 1'bz) && SAXIGP4ARADDR[35]; // rv 0 + assign SAXIGP4ARADDR_in[36] = (SAXIGP4ARADDR[36] !== 1'bz) && SAXIGP4ARADDR[36]; // rv 0 + assign SAXIGP4ARADDR_in[37] = (SAXIGP4ARADDR[37] !== 1'bz) && SAXIGP4ARADDR[37]; // rv 0 + assign SAXIGP4ARADDR_in[38] = (SAXIGP4ARADDR[38] !== 1'bz) && SAXIGP4ARADDR[38]; // rv 0 + assign SAXIGP4ARADDR_in[39] = (SAXIGP4ARADDR[39] !== 1'bz) && SAXIGP4ARADDR[39]; // rv 0 + assign SAXIGP4ARADDR_in[3] = (SAXIGP4ARADDR[3] !== 1'bz) && SAXIGP4ARADDR[3]; // rv 0 + assign SAXIGP4ARADDR_in[40] = (SAXIGP4ARADDR[40] !== 1'bz) && SAXIGP4ARADDR[40]; // rv 0 + assign SAXIGP4ARADDR_in[41] = (SAXIGP4ARADDR[41] !== 1'bz) && SAXIGP4ARADDR[41]; // rv 0 + assign SAXIGP4ARADDR_in[42] = (SAXIGP4ARADDR[42] !== 1'bz) && SAXIGP4ARADDR[42]; // rv 0 + assign SAXIGP4ARADDR_in[43] = (SAXIGP4ARADDR[43] !== 1'bz) && SAXIGP4ARADDR[43]; // rv 0 + assign SAXIGP4ARADDR_in[44] = (SAXIGP4ARADDR[44] !== 1'bz) && SAXIGP4ARADDR[44]; // rv 0 + assign SAXIGP4ARADDR_in[45] = (SAXIGP4ARADDR[45] !== 1'bz) && SAXIGP4ARADDR[45]; // rv 0 + assign SAXIGP4ARADDR_in[46] = (SAXIGP4ARADDR[46] !== 1'bz) && SAXIGP4ARADDR[46]; // rv 0 + assign SAXIGP4ARADDR_in[47] = (SAXIGP4ARADDR[47] !== 1'bz) && SAXIGP4ARADDR[47]; // rv 0 + assign SAXIGP4ARADDR_in[48] = (SAXIGP4ARADDR[48] !== 1'bz) && SAXIGP4ARADDR[48]; // rv 0 + assign SAXIGP4ARADDR_in[4] = (SAXIGP4ARADDR[4] !== 1'bz) && SAXIGP4ARADDR[4]; // rv 0 + assign SAXIGP4ARADDR_in[5] = (SAXIGP4ARADDR[5] !== 1'bz) && SAXIGP4ARADDR[5]; // rv 0 + assign SAXIGP4ARADDR_in[6] = (SAXIGP4ARADDR[6] !== 1'bz) && SAXIGP4ARADDR[6]; // rv 0 + assign SAXIGP4ARADDR_in[7] = (SAXIGP4ARADDR[7] !== 1'bz) && SAXIGP4ARADDR[7]; // rv 0 + assign SAXIGP4ARADDR_in[8] = (SAXIGP4ARADDR[8] !== 1'bz) && SAXIGP4ARADDR[8]; // rv 0 + assign SAXIGP4ARADDR_in[9] = (SAXIGP4ARADDR[9] !== 1'bz) && SAXIGP4ARADDR[9]; // rv 0 + assign SAXIGP4ARBURST_in[0] = (SAXIGP4ARBURST[0] !== 1'bz) && SAXIGP4ARBURST[0]; // rv 0 + assign SAXIGP4ARBURST_in[1] = (SAXIGP4ARBURST[1] !== 1'bz) && SAXIGP4ARBURST[1]; // rv 0 + assign SAXIGP4ARCACHE_in[0] = (SAXIGP4ARCACHE[0] !== 1'bz) && SAXIGP4ARCACHE[0]; // rv 0 + assign SAXIGP4ARCACHE_in[1] = (SAXIGP4ARCACHE[1] !== 1'bz) && SAXIGP4ARCACHE[1]; // rv 0 + assign SAXIGP4ARCACHE_in[2] = (SAXIGP4ARCACHE[2] !== 1'bz) && SAXIGP4ARCACHE[2]; // rv 0 + assign SAXIGP4ARCACHE_in[3] = (SAXIGP4ARCACHE[3] !== 1'bz) && SAXIGP4ARCACHE[3]; // rv 0 + assign SAXIGP4ARID_in[0] = (SAXIGP4ARID[0] !== 1'bz) && SAXIGP4ARID[0]; // rv 0 + assign SAXIGP4ARID_in[1] = (SAXIGP4ARID[1] !== 1'bz) && SAXIGP4ARID[1]; // rv 0 + assign SAXIGP4ARID_in[2] = (SAXIGP4ARID[2] !== 1'bz) && SAXIGP4ARID[2]; // rv 0 + assign SAXIGP4ARID_in[3] = (SAXIGP4ARID[3] !== 1'bz) && SAXIGP4ARID[3]; // rv 0 + assign SAXIGP4ARID_in[4] = (SAXIGP4ARID[4] !== 1'bz) && SAXIGP4ARID[4]; // rv 0 + assign SAXIGP4ARID_in[5] = (SAXIGP4ARID[5] !== 1'bz) && SAXIGP4ARID[5]; // rv 0 + assign SAXIGP4ARLEN_in[0] = (SAXIGP4ARLEN[0] !== 1'bz) && SAXIGP4ARLEN[0]; // rv 0 + assign SAXIGP4ARLEN_in[1] = (SAXIGP4ARLEN[1] !== 1'bz) && SAXIGP4ARLEN[1]; // rv 0 + assign SAXIGP4ARLEN_in[2] = (SAXIGP4ARLEN[2] !== 1'bz) && SAXIGP4ARLEN[2]; // rv 0 + assign SAXIGP4ARLEN_in[3] = (SAXIGP4ARLEN[3] !== 1'bz) && SAXIGP4ARLEN[3]; // rv 0 + assign SAXIGP4ARLEN_in[4] = (SAXIGP4ARLEN[4] !== 1'bz) && SAXIGP4ARLEN[4]; // rv 0 + assign SAXIGP4ARLEN_in[5] = (SAXIGP4ARLEN[5] !== 1'bz) && SAXIGP4ARLEN[5]; // rv 0 + assign SAXIGP4ARLEN_in[6] = (SAXIGP4ARLEN[6] !== 1'bz) && SAXIGP4ARLEN[6]; // rv 0 + assign SAXIGP4ARLEN_in[7] = (SAXIGP4ARLEN[7] !== 1'bz) && SAXIGP4ARLEN[7]; // rv 0 + assign SAXIGP4ARLOCK_in = (SAXIGP4ARLOCK !== 1'bz) && SAXIGP4ARLOCK; // rv 0 + assign SAXIGP4ARPROT_in[0] = (SAXIGP4ARPROT[0] !== 1'bz) && SAXIGP4ARPROT[0]; // rv 0 + assign SAXIGP4ARPROT_in[1] = (SAXIGP4ARPROT[1] !== 1'bz) && SAXIGP4ARPROT[1]; // rv 0 + assign SAXIGP4ARPROT_in[2] = (SAXIGP4ARPROT[2] !== 1'bz) && SAXIGP4ARPROT[2]; // rv 0 + assign SAXIGP4ARQOS_in[0] = (SAXIGP4ARQOS[0] !== 1'bz) && SAXIGP4ARQOS[0]; // rv 0 + assign SAXIGP4ARQOS_in[1] = (SAXIGP4ARQOS[1] !== 1'bz) && SAXIGP4ARQOS[1]; // rv 0 + assign SAXIGP4ARQOS_in[2] = (SAXIGP4ARQOS[2] !== 1'bz) && SAXIGP4ARQOS[2]; // rv 0 + assign SAXIGP4ARQOS_in[3] = (SAXIGP4ARQOS[3] !== 1'bz) && SAXIGP4ARQOS[3]; // rv 0 + assign SAXIGP4ARSIZE_in[0] = (SAXIGP4ARSIZE[0] !== 1'bz) && SAXIGP4ARSIZE[0]; // rv 0 + assign SAXIGP4ARSIZE_in[1] = (SAXIGP4ARSIZE[1] !== 1'bz) && SAXIGP4ARSIZE[1]; // rv 0 + assign SAXIGP4ARSIZE_in[2] = (SAXIGP4ARSIZE[2] !== 1'bz) && SAXIGP4ARSIZE[2]; // rv 0 + assign SAXIGP4ARUSER_in = (SAXIGP4ARUSER !== 1'bz) && SAXIGP4ARUSER; // rv 0 + assign SAXIGP4ARVALID_in = (SAXIGP4ARVALID !== 1'bz) && SAXIGP4ARVALID; // rv 0 + assign SAXIGP4AWADDR_in[0] = (SAXIGP4AWADDR[0] !== 1'bz) && SAXIGP4AWADDR[0]; // rv 0 + assign SAXIGP4AWADDR_in[10] = (SAXIGP4AWADDR[10] !== 1'bz) && SAXIGP4AWADDR[10]; // rv 0 + assign SAXIGP4AWADDR_in[11] = (SAXIGP4AWADDR[11] !== 1'bz) && SAXIGP4AWADDR[11]; // rv 0 + assign SAXIGP4AWADDR_in[12] = (SAXIGP4AWADDR[12] !== 1'bz) && SAXIGP4AWADDR[12]; // rv 0 + assign SAXIGP4AWADDR_in[13] = (SAXIGP4AWADDR[13] !== 1'bz) && SAXIGP4AWADDR[13]; // rv 0 + assign SAXIGP4AWADDR_in[14] = (SAXIGP4AWADDR[14] !== 1'bz) && SAXIGP4AWADDR[14]; // rv 0 + assign SAXIGP4AWADDR_in[15] = (SAXIGP4AWADDR[15] !== 1'bz) && SAXIGP4AWADDR[15]; // rv 0 + assign SAXIGP4AWADDR_in[16] = (SAXIGP4AWADDR[16] !== 1'bz) && SAXIGP4AWADDR[16]; // rv 0 + assign SAXIGP4AWADDR_in[17] = (SAXIGP4AWADDR[17] !== 1'bz) && SAXIGP4AWADDR[17]; // rv 0 + assign SAXIGP4AWADDR_in[18] = (SAXIGP4AWADDR[18] !== 1'bz) && SAXIGP4AWADDR[18]; // rv 0 + assign SAXIGP4AWADDR_in[19] = (SAXIGP4AWADDR[19] !== 1'bz) && SAXIGP4AWADDR[19]; // rv 0 + assign SAXIGP4AWADDR_in[1] = (SAXIGP4AWADDR[1] !== 1'bz) && SAXIGP4AWADDR[1]; // rv 0 + assign SAXIGP4AWADDR_in[20] = (SAXIGP4AWADDR[20] !== 1'bz) && SAXIGP4AWADDR[20]; // rv 0 + assign SAXIGP4AWADDR_in[21] = (SAXIGP4AWADDR[21] !== 1'bz) && SAXIGP4AWADDR[21]; // rv 0 + assign SAXIGP4AWADDR_in[22] = (SAXIGP4AWADDR[22] !== 1'bz) && SAXIGP4AWADDR[22]; // rv 0 + assign SAXIGP4AWADDR_in[23] = (SAXIGP4AWADDR[23] !== 1'bz) && SAXIGP4AWADDR[23]; // rv 0 + assign SAXIGP4AWADDR_in[24] = (SAXIGP4AWADDR[24] !== 1'bz) && SAXIGP4AWADDR[24]; // rv 0 + assign SAXIGP4AWADDR_in[25] = (SAXIGP4AWADDR[25] !== 1'bz) && SAXIGP4AWADDR[25]; // rv 0 + assign SAXIGP4AWADDR_in[26] = (SAXIGP4AWADDR[26] !== 1'bz) && SAXIGP4AWADDR[26]; // rv 0 + assign SAXIGP4AWADDR_in[27] = (SAXIGP4AWADDR[27] !== 1'bz) && SAXIGP4AWADDR[27]; // rv 0 + assign SAXIGP4AWADDR_in[28] = (SAXIGP4AWADDR[28] !== 1'bz) && SAXIGP4AWADDR[28]; // rv 0 + assign SAXIGP4AWADDR_in[29] = (SAXIGP4AWADDR[29] !== 1'bz) && SAXIGP4AWADDR[29]; // rv 0 + assign SAXIGP4AWADDR_in[2] = (SAXIGP4AWADDR[2] !== 1'bz) && SAXIGP4AWADDR[2]; // rv 0 + assign SAXIGP4AWADDR_in[30] = (SAXIGP4AWADDR[30] !== 1'bz) && SAXIGP4AWADDR[30]; // rv 0 + assign SAXIGP4AWADDR_in[31] = (SAXIGP4AWADDR[31] !== 1'bz) && SAXIGP4AWADDR[31]; // rv 0 + assign SAXIGP4AWADDR_in[32] = (SAXIGP4AWADDR[32] !== 1'bz) && SAXIGP4AWADDR[32]; // rv 0 + assign SAXIGP4AWADDR_in[33] = (SAXIGP4AWADDR[33] !== 1'bz) && SAXIGP4AWADDR[33]; // rv 0 + assign SAXIGP4AWADDR_in[34] = (SAXIGP4AWADDR[34] !== 1'bz) && SAXIGP4AWADDR[34]; // rv 0 + assign SAXIGP4AWADDR_in[35] = (SAXIGP4AWADDR[35] !== 1'bz) && SAXIGP4AWADDR[35]; // rv 0 + assign SAXIGP4AWADDR_in[36] = (SAXIGP4AWADDR[36] !== 1'bz) && SAXIGP4AWADDR[36]; // rv 0 + assign SAXIGP4AWADDR_in[37] = (SAXIGP4AWADDR[37] !== 1'bz) && SAXIGP4AWADDR[37]; // rv 0 + assign SAXIGP4AWADDR_in[38] = (SAXIGP4AWADDR[38] !== 1'bz) && SAXIGP4AWADDR[38]; // rv 0 + assign SAXIGP4AWADDR_in[39] = (SAXIGP4AWADDR[39] !== 1'bz) && SAXIGP4AWADDR[39]; // rv 0 + assign SAXIGP4AWADDR_in[3] = (SAXIGP4AWADDR[3] !== 1'bz) && SAXIGP4AWADDR[3]; // rv 0 + assign SAXIGP4AWADDR_in[40] = (SAXIGP4AWADDR[40] !== 1'bz) && SAXIGP4AWADDR[40]; // rv 0 + assign SAXIGP4AWADDR_in[41] = (SAXIGP4AWADDR[41] !== 1'bz) && SAXIGP4AWADDR[41]; // rv 0 + assign SAXIGP4AWADDR_in[42] = (SAXIGP4AWADDR[42] !== 1'bz) && SAXIGP4AWADDR[42]; // rv 0 + assign SAXIGP4AWADDR_in[43] = (SAXIGP4AWADDR[43] !== 1'bz) && SAXIGP4AWADDR[43]; // rv 0 + assign SAXIGP4AWADDR_in[44] = (SAXIGP4AWADDR[44] !== 1'bz) && SAXIGP4AWADDR[44]; // rv 0 + assign SAXIGP4AWADDR_in[45] = (SAXIGP4AWADDR[45] !== 1'bz) && SAXIGP4AWADDR[45]; // rv 0 + assign SAXIGP4AWADDR_in[46] = (SAXIGP4AWADDR[46] !== 1'bz) && SAXIGP4AWADDR[46]; // rv 0 + assign SAXIGP4AWADDR_in[47] = (SAXIGP4AWADDR[47] !== 1'bz) && SAXIGP4AWADDR[47]; // rv 0 + assign SAXIGP4AWADDR_in[48] = (SAXIGP4AWADDR[48] !== 1'bz) && SAXIGP4AWADDR[48]; // rv 0 + assign SAXIGP4AWADDR_in[4] = (SAXIGP4AWADDR[4] !== 1'bz) && SAXIGP4AWADDR[4]; // rv 0 + assign SAXIGP4AWADDR_in[5] = (SAXIGP4AWADDR[5] !== 1'bz) && SAXIGP4AWADDR[5]; // rv 0 + assign SAXIGP4AWADDR_in[6] = (SAXIGP4AWADDR[6] !== 1'bz) && SAXIGP4AWADDR[6]; // rv 0 + assign SAXIGP4AWADDR_in[7] = (SAXIGP4AWADDR[7] !== 1'bz) && SAXIGP4AWADDR[7]; // rv 0 + assign SAXIGP4AWADDR_in[8] = (SAXIGP4AWADDR[8] !== 1'bz) && SAXIGP4AWADDR[8]; // rv 0 + assign SAXIGP4AWADDR_in[9] = (SAXIGP4AWADDR[9] !== 1'bz) && SAXIGP4AWADDR[9]; // rv 0 + assign SAXIGP4AWBURST_in[0] = (SAXIGP4AWBURST[0] !== 1'bz) && SAXIGP4AWBURST[0]; // rv 0 + assign SAXIGP4AWBURST_in[1] = (SAXIGP4AWBURST[1] !== 1'bz) && SAXIGP4AWBURST[1]; // rv 0 + assign SAXIGP4AWCACHE_in[0] = (SAXIGP4AWCACHE[0] !== 1'bz) && SAXIGP4AWCACHE[0]; // rv 0 + assign SAXIGP4AWCACHE_in[1] = (SAXIGP4AWCACHE[1] !== 1'bz) && SAXIGP4AWCACHE[1]; // rv 0 + assign SAXIGP4AWCACHE_in[2] = (SAXIGP4AWCACHE[2] !== 1'bz) && SAXIGP4AWCACHE[2]; // rv 0 + assign SAXIGP4AWCACHE_in[3] = (SAXIGP4AWCACHE[3] !== 1'bz) && SAXIGP4AWCACHE[3]; // rv 0 + assign SAXIGP4AWID_in[0] = (SAXIGP4AWID[0] !== 1'bz) && SAXIGP4AWID[0]; // rv 0 + assign SAXIGP4AWID_in[1] = (SAXIGP4AWID[1] !== 1'bz) && SAXIGP4AWID[1]; // rv 0 + assign SAXIGP4AWID_in[2] = (SAXIGP4AWID[2] !== 1'bz) && SAXIGP4AWID[2]; // rv 0 + assign SAXIGP4AWID_in[3] = (SAXIGP4AWID[3] !== 1'bz) && SAXIGP4AWID[3]; // rv 0 + assign SAXIGP4AWID_in[4] = (SAXIGP4AWID[4] !== 1'bz) && SAXIGP4AWID[4]; // rv 0 + assign SAXIGP4AWID_in[5] = (SAXIGP4AWID[5] !== 1'bz) && SAXIGP4AWID[5]; // rv 0 + assign SAXIGP4AWLEN_in[0] = (SAXIGP4AWLEN[0] !== 1'bz) && SAXIGP4AWLEN[0]; // rv 0 + assign SAXIGP4AWLEN_in[1] = (SAXIGP4AWLEN[1] !== 1'bz) && SAXIGP4AWLEN[1]; // rv 0 + assign SAXIGP4AWLEN_in[2] = (SAXIGP4AWLEN[2] !== 1'bz) && SAXIGP4AWLEN[2]; // rv 0 + assign SAXIGP4AWLEN_in[3] = (SAXIGP4AWLEN[3] !== 1'bz) && SAXIGP4AWLEN[3]; // rv 0 + assign SAXIGP4AWLEN_in[4] = (SAXIGP4AWLEN[4] !== 1'bz) && SAXIGP4AWLEN[4]; // rv 0 + assign SAXIGP4AWLEN_in[5] = (SAXIGP4AWLEN[5] !== 1'bz) && SAXIGP4AWLEN[5]; // rv 0 + assign SAXIGP4AWLEN_in[6] = (SAXIGP4AWLEN[6] !== 1'bz) && SAXIGP4AWLEN[6]; // rv 0 + assign SAXIGP4AWLEN_in[7] = (SAXIGP4AWLEN[7] !== 1'bz) && SAXIGP4AWLEN[7]; // rv 0 + assign SAXIGP4AWLOCK_in = (SAXIGP4AWLOCK !== 1'bz) && SAXIGP4AWLOCK; // rv 0 + assign SAXIGP4AWPROT_in[0] = (SAXIGP4AWPROT[0] !== 1'bz) && SAXIGP4AWPROT[0]; // rv 0 + assign SAXIGP4AWPROT_in[1] = (SAXIGP4AWPROT[1] !== 1'bz) && SAXIGP4AWPROT[1]; // rv 0 + assign SAXIGP4AWPROT_in[2] = (SAXIGP4AWPROT[2] !== 1'bz) && SAXIGP4AWPROT[2]; // rv 0 + assign SAXIGP4AWQOS_in[0] = (SAXIGP4AWQOS[0] !== 1'bz) && SAXIGP4AWQOS[0]; // rv 0 + assign SAXIGP4AWQOS_in[1] = (SAXIGP4AWQOS[1] !== 1'bz) && SAXIGP4AWQOS[1]; // rv 0 + assign SAXIGP4AWQOS_in[2] = (SAXIGP4AWQOS[2] !== 1'bz) && SAXIGP4AWQOS[2]; // rv 0 + assign SAXIGP4AWQOS_in[3] = (SAXIGP4AWQOS[3] !== 1'bz) && SAXIGP4AWQOS[3]; // rv 0 + assign SAXIGP4AWSIZE_in[0] = (SAXIGP4AWSIZE[0] !== 1'bz) && SAXIGP4AWSIZE[0]; // rv 0 + assign SAXIGP4AWSIZE_in[1] = (SAXIGP4AWSIZE[1] !== 1'bz) && SAXIGP4AWSIZE[1]; // rv 0 + assign SAXIGP4AWSIZE_in[2] = (SAXIGP4AWSIZE[2] !== 1'bz) && SAXIGP4AWSIZE[2]; // rv 0 + assign SAXIGP4AWUSER_in = (SAXIGP4AWUSER !== 1'bz) && SAXIGP4AWUSER; // rv 0 + assign SAXIGP4AWVALID_in = (SAXIGP4AWVALID !== 1'bz) && SAXIGP4AWVALID; // rv 0 + assign SAXIGP4BREADY_in = (SAXIGP4BREADY !== 1'bz) && SAXIGP4BREADY; // rv 0 + assign SAXIGP4RCLK_in = (SAXIGP4RCLK !== 1'bz) && SAXIGP4RCLK; // rv 0 + assign SAXIGP4RREADY_in = (SAXIGP4RREADY !== 1'bz) && SAXIGP4RREADY; // rv 0 + assign SAXIGP4WCLK_in = (SAXIGP4WCLK !== 1'bz) && SAXIGP4WCLK; // rv 0 + assign SAXIGP4WDATA_in[0] = (SAXIGP4WDATA[0] !== 1'bz) && SAXIGP4WDATA[0]; // rv 0 + assign SAXIGP4WDATA_in[100] = (SAXIGP4WDATA[100] !== 1'bz) && SAXIGP4WDATA[100]; // rv 0 + assign SAXIGP4WDATA_in[101] = (SAXIGP4WDATA[101] !== 1'bz) && SAXIGP4WDATA[101]; // rv 0 + assign SAXIGP4WDATA_in[102] = (SAXIGP4WDATA[102] !== 1'bz) && SAXIGP4WDATA[102]; // rv 0 + assign SAXIGP4WDATA_in[103] = (SAXIGP4WDATA[103] !== 1'bz) && SAXIGP4WDATA[103]; // rv 0 + assign SAXIGP4WDATA_in[104] = (SAXIGP4WDATA[104] !== 1'bz) && SAXIGP4WDATA[104]; // rv 0 + assign SAXIGP4WDATA_in[105] = (SAXIGP4WDATA[105] !== 1'bz) && SAXIGP4WDATA[105]; // rv 0 + assign SAXIGP4WDATA_in[106] = (SAXIGP4WDATA[106] !== 1'bz) && SAXIGP4WDATA[106]; // rv 0 + assign SAXIGP4WDATA_in[107] = (SAXIGP4WDATA[107] !== 1'bz) && SAXIGP4WDATA[107]; // rv 0 + assign SAXIGP4WDATA_in[108] = (SAXIGP4WDATA[108] !== 1'bz) && SAXIGP4WDATA[108]; // rv 0 + assign SAXIGP4WDATA_in[109] = (SAXIGP4WDATA[109] !== 1'bz) && SAXIGP4WDATA[109]; // rv 0 + assign SAXIGP4WDATA_in[10] = (SAXIGP4WDATA[10] !== 1'bz) && SAXIGP4WDATA[10]; // rv 0 + assign SAXIGP4WDATA_in[110] = (SAXIGP4WDATA[110] !== 1'bz) && SAXIGP4WDATA[110]; // rv 0 + assign SAXIGP4WDATA_in[111] = (SAXIGP4WDATA[111] !== 1'bz) && SAXIGP4WDATA[111]; // rv 0 + assign SAXIGP4WDATA_in[112] = (SAXIGP4WDATA[112] !== 1'bz) && SAXIGP4WDATA[112]; // rv 0 + assign SAXIGP4WDATA_in[113] = (SAXIGP4WDATA[113] !== 1'bz) && SAXIGP4WDATA[113]; // rv 0 + assign SAXIGP4WDATA_in[114] = (SAXIGP4WDATA[114] !== 1'bz) && SAXIGP4WDATA[114]; // rv 0 + assign SAXIGP4WDATA_in[115] = (SAXIGP4WDATA[115] !== 1'bz) && SAXIGP4WDATA[115]; // rv 0 + assign SAXIGP4WDATA_in[116] = (SAXIGP4WDATA[116] !== 1'bz) && SAXIGP4WDATA[116]; // rv 0 + assign SAXIGP4WDATA_in[117] = (SAXIGP4WDATA[117] !== 1'bz) && SAXIGP4WDATA[117]; // rv 0 + assign SAXIGP4WDATA_in[118] = (SAXIGP4WDATA[118] !== 1'bz) && SAXIGP4WDATA[118]; // rv 0 + assign SAXIGP4WDATA_in[119] = (SAXIGP4WDATA[119] !== 1'bz) && SAXIGP4WDATA[119]; // rv 0 + assign SAXIGP4WDATA_in[11] = (SAXIGP4WDATA[11] !== 1'bz) && SAXIGP4WDATA[11]; // rv 0 + assign SAXIGP4WDATA_in[120] = (SAXIGP4WDATA[120] !== 1'bz) && SAXIGP4WDATA[120]; // rv 0 + assign SAXIGP4WDATA_in[121] = (SAXIGP4WDATA[121] !== 1'bz) && SAXIGP4WDATA[121]; // rv 0 + assign SAXIGP4WDATA_in[122] = (SAXIGP4WDATA[122] !== 1'bz) && SAXIGP4WDATA[122]; // rv 0 + assign SAXIGP4WDATA_in[123] = (SAXIGP4WDATA[123] !== 1'bz) && SAXIGP4WDATA[123]; // rv 0 + assign SAXIGP4WDATA_in[124] = (SAXIGP4WDATA[124] !== 1'bz) && SAXIGP4WDATA[124]; // rv 0 + assign SAXIGP4WDATA_in[125] = (SAXIGP4WDATA[125] !== 1'bz) && SAXIGP4WDATA[125]; // rv 0 + assign SAXIGP4WDATA_in[126] = (SAXIGP4WDATA[126] !== 1'bz) && SAXIGP4WDATA[126]; // rv 0 + assign SAXIGP4WDATA_in[127] = (SAXIGP4WDATA[127] !== 1'bz) && SAXIGP4WDATA[127]; // rv 0 + assign SAXIGP4WDATA_in[12] = (SAXIGP4WDATA[12] !== 1'bz) && SAXIGP4WDATA[12]; // rv 0 + assign SAXIGP4WDATA_in[13] = (SAXIGP4WDATA[13] !== 1'bz) && SAXIGP4WDATA[13]; // rv 0 + assign SAXIGP4WDATA_in[14] = (SAXIGP4WDATA[14] !== 1'bz) && SAXIGP4WDATA[14]; // rv 0 + assign SAXIGP4WDATA_in[15] = (SAXIGP4WDATA[15] !== 1'bz) && SAXIGP4WDATA[15]; // rv 0 + assign SAXIGP4WDATA_in[16] = (SAXIGP4WDATA[16] !== 1'bz) && SAXIGP4WDATA[16]; // rv 0 + assign SAXIGP4WDATA_in[17] = (SAXIGP4WDATA[17] !== 1'bz) && SAXIGP4WDATA[17]; // rv 0 + assign SAXIGP4WDATA_in[18] = (SAXIGP4WDATA[18] !== 1'bz) && SAXIGP4WDATA[18]; // rv 0 + assign SAXIGP4WDATA_in[19] = (SAXIGP4WDATA[19] !== 1'bz) && SAXIGP4WDATA[19]; // rv 0 + assign SAXIGP4WDATA_in[1] = (SAXIGP4WDATA[1] !== 1'bz) && SAXIGP4WDATA[1]; // rv 0 + assign SAXIGP4WDATA_in[20] = (SAXIGP4WDATA[20] !== 1'bz) && SAXIGP4WDATA[20]; // rv 0 + assign SAXIGP4WDATA_in[21] = (SAXIGP4WDATA[21] !== 1'bz) && SAXIGP4WDATA[21]; // rv 0 + assign SAXIGP4WDATA_in[22] = (SAXIGP4WDATA[22] !== 1'bz) && SAXIGP4WDATA[22]; // rv 0 + assign SAXIGP4WDATA_in[23] = (SAXIGP4WDATA[23] !== 1'bz) && SAXIGP4WDATA[23]; // rv 0 + assign SAXIGP4WDATA_in[24] = (SAXIGP4WDATA[24] !== 1'bz) && SAXIGP4WDATA[24]; // rv 0 + assign SAXIGP4WDATA_in[25] = (SAXIGP4WDATA[25] !== 1'bz) && SAXIGP4WDATA[25]; // rv 0 + assign SAXIGP4WDATA_in[26] = (SAXIGP4WDATA[26] !== 1'bz) && SAXIGP4WDATA[26]; // rv 0 + assign SAXIGP4WDATA_in[27] = (SAXIGP4WDATA[27] !== 1'bz) && SAXIGP4WDATA[27]; // rv 0 + assign SAXIGP4WDATA_in[28] = (SAXIGP4WDATA[28] !== 1'bz) && SAXIGP4WDATA[28]; // rv 0 + assign SAXIGP4WDATA_in[29] = (SAXIGP4WDATA[29] !== 1'bz) && SAXIGP4WDATA[29]; // rv 0 + assign SAXIGP4WDATA_in[2] = (SAXIGP4WDATA[2] !== 1'bz) && SAXIGP4WDATA[2]; // rv 0 + assign SAXIGP4WDATA_in[30] = (SAXIGP4WDATA[30] !== 1'bz) && SAXIGP4WDATA[30]; // rv 0 + assign SAXIGP4WDATA_in[31] = (SAXIGP4WDATA[31] !== 1'bz) && SAXIGP4WDATA[31]; // rv 0 + assign SAXIGP4WDATA_in[32] = (SAXIGP4WDATA[32] !== 1'bz) && SAXIGP4WDATA[32]; // rv 0 + assign SAXIGP4WDATA_in[33] = (SAXIGP4WDATA[33] !== 1'bz) && SAXIGP4WDATA[33]; // rv 0 + assign SAXIGP4WDATA_in[34] = (SAXIGP4WDATA[34] !== 1'bz) && SAXIGP4WDATA[34]; // rv 0 + assign SAXIGP4WDATA_in[35] = (SAXIGP4WDATA[35] !== 1'bz) && SAXIGP4WDATA[35]; // rv 0 + assign SAXIGP4WDATA_in[36] = (SAXIGP4WDATA[36] !== 1'bz) && SAXIGP4WDATA[36]; // rv 0 + assign SAXIGP4WDATA_in[37] = (SAXIGP4WDATA[37] !== 1'bz) && SAXIGP4WDATA[37]; // rv 0 + assign SAXIGP4WDATA_in[38] = (SAXIGP4WDATA[38] !== 1'bz) && SAXIGP4WDATA[38]; // rv 0 + assign SAXIGP4WDATA_in[39] = (SAXIGP4WDATA[39] !== 1'bz) && SAXIGP4WDATA[39]; // rv 0 + assign SAXIGP4WDATA_in[3] = (SAXIGP4WDATA[3] !== 1'bz) && SAXIGP4WDATA[3]; // rv 0 + assign SAXIGP4WDATA_in[40] = (SAXIGP4WDATA[40] !== 1'bz) && SAXIGP4WDATA[40]; // rv 0 + assign SAXIGP4WDATA_in[41] = (SAXIGP4WDATA[41] !== 1'bz) && SAXIGP4WDATA[41]; // rv 0 + assign SAXIGP4WDATA_in[42] = (SAXIGP4WDATA[42] !== 1'bz) && SAXIGP4WDATA[42]; // rv 0 + assign SAXIGP4WDATA_in[43] = (SAXIGP4WDATA[43] !== 1'bz) && SAXIGP4WDATA[43]; // rv 0 + assign SAXIGP4WDATA_in[44] = (SAXIGP4WDATA[44] !== 1'bz) && SAXIGP4WDATA[44]; // rv 0 + assign SAXIGP4WDATA_in[45] = (SAXIGP4WDATA[45] !== 1'bz) && SAXIGP4WDATA[45]; // rv 0 + assign SAXIGP4WDATA_in[46] = (SAXIGP4WDATA[46] !== 1'bz) && SAXIGP4WDATA[46]; // rv 0 + assign SAXIGP4WDATA_in[47] = (SAXIGP4WDATA[47] !== 1'bz) && SAXIGP4WDATA[47]; // rv 0 + assign SAXIGP4WDATA_in[48] = (SAXIGP4WDATA[48] !== 1'bz) && SAXIGP4WDATA[48]; // rv 0 + assign SAXIGP4WDATA_in[49] = (SAXIGP4WDATA[49] !== 1'bz) && SAXIGP4WDATA[49]; // rv 0 + assign SAXIGP4WDATA_in[4] = (SAXIGP4WDATA[4] !== 1'bz) && SAXIGP4WDATA[4]; // rv 0 + assign SAXIGP4WDATA_in[50] = (SAXIGP4WDATA[50] !== 1'bz) && SAXIGP4WDATA[50]; // rv 0 + assign SAXIGP4WDATA_in[51] = (SAXIGP4WDATA[51] !== 1'bz) && SAXIGP4WDATA[51]; // rv 0 + assign SAXIGP4WDATA_in[52] = (SAXIGP4WDATA[52] !== 1'bz) && SAXIGP4WDATA[52]; // rv 0 + assign SAXIGP4WDATA_in[53] = (SAXIGP4WDATA[53] !== 1'bz) && SAXIGP4WDATA[53]; // rv 0 + assign SAXIGP4WDATA_in[54] = (SAXIGP4WDATA[54] !== 1'bz) && SAXIGP4WDATA[54]; // rv 0 + assign SAXIGP4WDATA_in[55] = (SAXIGP4WDATA[55] !== 1'bz) && SAXIGP4WDATA[55]; // rv 0 + assign SAXIGP4WDATA_in[56] = (SAXIGP4WDATA[56] !== 1'bz) && SAXIGP4WDATA[56]; // rv 0 + assign SAXIGP4WDATA_in[57] = (SAXIGP4WDATA[57] !== 1'bz) && SAXIGP4WDATA[57]; // rv 0 + assign SAXIGP4WDATA_in[58] = (SAXIGP4WDATA[58] !== 1'bz) && SAXIGP4WDATA[58]; // rv 0 + assign SAXIGP4WDATA_in[59] = (SAXIGP4WDATA[59] !== 1'bz) && SAXIGP4WDATA[59]; // rv 0 + assign SAXIGP4WDATA_in[5] = (SAXIGP4WDATA[5] !== 1'bz) && SAXIGP4WDATA[5]; // rv 0 + assign SAXIGP4WDATA_in[60] = (SAXIGP4WDATA[60] !== 1'bz) && SAXIGP4WDATA[60]; // rv 0 + assign SAXIGP4WDATA_in[61] = (SAXIGP4WDATA[61] !== 1'bz) && SAXIGP4WDATA[61]; // rv 0 + assign SAXIGP4WDATA_in[62] = (SAXIGP4WDATA[62] !== 1'bz) && SAXIGP4WDATA[62]; // rv 0 + assign SAXIGP4WDATA_in[63] = (SAXIGP4WDATA[63] !== 1'bz) && SAXIGP4WDATA[63]; // rv 0 + assign SAXIGP4WDATA_in[64] = (SAXIGP4WDATA[64] !== 1'bz) && SAXIGP4WDATA[64]; // rv 0 + assign SAXIGP4WDATA_in[65] = (SAXIGP4WDATA[65] !== 1'bz) && SAXIGP4WDATA[65]; // rv 0 + assign SAXIGP4WDATA_in[66] = (SAXIGP4WDATA[66] !== 1'bz) && SAXIGP4WDATA[66]; // rv 0 + assign SAXIGP4WDATA_in[67] = (SAXIGP4WDATA[67] !== 1'bz) && SAXIGP4WDATA[67]; // rv 0 + assign SAXIGP4WDATA_in[68] = (SAXIGP4WDATA[68] !== 1'bz) && SAXIGP4WDATA[68]; // rv 0 + assign SAXIGP4WDATA_in[69] = (SAXIGP4WDATA[69] !== 1'bz) && SAXIGP4WDATA[69]; // rv 0 + assign SAXIGP4WDATA_in[6] = (SAXIGP4WDATA[6] !== 1'bz) && SAXIGP4WDATA[6]; // rv 0 + assign SAXIGP4WDATA_in[70] = (SAXIGP4WDATA[70] !== 1'bz) && SAXIGP4WDATA[70]; // rv 0 + assign SAXIGP4WDATA_in[71] = (SAXIGP4WDATA[71] !== 1'bz) && SAXIGP4WDATA[71]; // rv 0 + assign SAXIGP4WDATA_in[72] = (SAXIGP4WDATA[72] !== 1'bz) && SAXIGP4WDATA[72]; // rv 0 + assign SAXIGP4WDATA_in[73] = (SAXIGP4WDATA[73] !== 1'bz) && SAXIGP4WDATA[73]; // rv 0 + assign SAXIGP4WDATA_in[74] = (SAXIGP4WDATA[74] !== 1'bz) && SAXIGP4WDATA[74]; // rv 0 + assign SAXIGP4WDATA_in[75] = (SAXIGP4WDATA[75] !== 1'bz) && SAXIGP4WDATA[75]; // rv 0 + assign SAXIGP4WDATA_in[76] = (SAXIGP4WDATA[76] !== 1'bz) && SAXIGP4WDATA[76]; // rv 0 + assign SAXIGP4WDATA_in[77] = (SAXIGP4WDATA[77] !== 1'bz) && SAXIGP4WDATA[77]; // rv 0 + assign SAXIGP4WDATA_in[78] = (SAXIGP4WDATA[78] !== 1'bz) && SAXIGP4WDATA[78]; // rv 0 + assign SAXIGP4WDATA_in[79] = (SAXIGP4WDATA[79] !== 1'bz) && SAXIGP4WDATA[79]; // rv 0 + assign SAXIGP4WDATA_in[7] = (SAXIGP4WDATA[7] !== 1'bz) && SAXIGP4WDATA[7]; // rv 0 + assign SAXIGP4WDATA_in[80] = (SAXIGP4WDATA[80] !== 1'bz) && SAXIGP4WDATA[80]; // rv 0 + assign SAXIGP4WDATA_in[81] = (SAXIGP4WDATA[81] !== 1'bz) && SAXIGP4WDATA[81]; // rv 0 + assign SAXIGP4WDATA_in[82] = (SAXIGP4WDATA[82] !== 1'bz) && SAXIGP4WDATA[82]; // rv 0 + assign SAXIGP4WDATA_in[83] = (SAXIGP4WDATA[83] !== 1'bz) && SAXIGP4WDATA[83]; // rv 0 + assign SAXIGP4WDATA_in[84] = (SAXIGP4WDATA[84] !== 1'bz) && SAXIGP4WDATA[84]; // rv 0 + assign SAXIGP4WDATA_in[85] = (SAXIGP4WDATA[85] !== 1'bz) && SAXIGP4WDATA[85]; // rv 0 + assign SAXIGP4WDATA_in[86] = (SAXIGP4WDATA[86] !== 1'bz) && SAXIGP4WDATA[86]; // rv 0 + assign SAXIGP4WDATA_in[87] = (SAXIGP4WDATA[87] !== 1'bz) && SAXIGP4WDATA[87]; // rv 0 + assign SAXIGP4WDATA_in[88] = (SAXIGP4WDATA[88] !== 1'bz) && SAXIGP4WDATA[88]; // rv 0 + assign SAXIGP4WDATA_in[89] = (SAXIGP4WDATA[89] !== 1'bz) && SAXIGP4WDATA[89]; // rv 0 + assign SAXIGP4WDATA_in[8] = (SAXIGP4WDATA[8] !== 1'bz) && SAXIGP4WDATA[8]; // rv 0 + assign SAXIGP4WDATA_in[90] = (SAXIGP4WDATA[90] !== 1'bz) && SAXIGP4WDATA[90]; // rv 0 + assign SAXIGP4WDATA_in[91] = (SAXIGP4WDATA[91] !== 1'bz) && SAXIGP4WDATA[91]; // rv 0 + assign SAXIGP4WDATA_in[92] = (SAXIGP4WDATA[92] !== 1'bz) && SAXIGP4WDATA[92]; // rv 0 + assign SAXIGP4WDATA_in[93] = (SAXIGP4WDATA[93] !== 1'bz) && SAXIGP4WDATA[93]; // rv 0 + assign SAXIGP4WDATA_in[94] = (SAXIGP4WDATA[94] !== 1'bz) && SAXIGP4WDATA[94]; // rv 0 + assign SAXIGP4WDATA_in[95] = (SAXIGP4WDATA[95] !== 1'bz) && SAXIGP4WDATA[95]; // rv 0 + assign SAXIGP4WDATA_in[96] = (SAXIGP4WDATA[96] !== 1'bz) && SAXIGP4WDATA[96]; // rv 0 + assign SAXIGP4WDATA_in[97] = (SAXIGP4WDATA[97] !== 1'bz) && SAXIGP4WDATA[97]; // rv 0 + assign SAXIGP4WDATA_in[98] = (SAXIGP4WDATA[98] !== 1'bz) && SAXIGP4WDATA[98]; // rv 0 + assign SAXIGP4WDATA_in[99] = (SAXIGP4WDATA[99] !== 1'bz) && SAXIGP4WDATA[99]; // rv 0 + assign SAXIGP4WDATA_in[9] = (SAXIGP4WDATA[9] !== 1'bz) && SAXIGP4WDATA[9]; // rv 0 + assign SAXIGP4WLAST_in = (SAXIGP4WLAST !== 1'bz) && SAXIGP4WLAST; // rv 0 + assign SAXIGP4WSTRB_in[0] = (SAXIGP4WSTRB[0] !== 1'bz) && SAXIGP4WSTRB[0]; // rv 0 + assign SAXIGP4WSTRB_in[10] = (SAXIGP4WSTRB[10] !== 1'bz) && SAXIGP4WSTRB[10]; // rv 0 + assign SAXIGP4WSTRB_in[11] = (SAXIGP4WSTRB[11] !== 1'bz) && SAXIGP4WSTRB[11]; // rv 0 + assign SAXIGP4WSTRB_in[12] = (SAXIGP4WSTRB[12] !== 1'bz) && SAXIGP4WSTRB[12]; // rv 0 + assign SAXIGP4WSTRB_in[13] = (SAXIGP4WSTRB[13] !== 1'bz) && SAXIGP4WSTRB[13]; // rv 0 + assign SAXIGP4WSTRB_in[14] = (SAXIGP4WSTRB[14] !== 1'bz) && SAXIGP4WSTRB[14]; // rv 0 + assign SAXIGP4WSTRB_in[15] = (SAXIGP4WSTRB[15] !== 1'bz) && SAXIGP4WSTRB[15]; // rv 0 + assign SAXIGP4WSTRB_in[1] = (SAXIGP4WSTRB[1] !== 1'bz) && SAXIGP4WSTRB[1]; // rv 0 + assign SAXIGP4WSTRB_in[2] = (SAXIGP4WSTRB[2] !== 1'bz) && SAXIGP4WSTRB[2]; // rv 0 + assign SAXIGP4WSTRB_in[3] = (SAXIGP4WSTRB[3] !== 1'bz) && SAXIGP4WSTRB[3]; // rv 0 + assign SAXIGP4WSTRB_in[4] = (SAXIGP4WSTRB[4] !== 1'bz) && SAXIGP4WSTRB[4]; // rv 0 + assign SAXIGP4WSTRB_in[5] = (SAXIGP4WSTRB[5] !== 1'bz) && SAXIGP4WSTRB[5]; // rv 0 + assign SAXIGP4WSTRB_in[6] = (SAXIGP4WSTRB[6] !== 1'bz) && SAXIGP4WSTRB[6]; // rv 0 + assign SAXIGP4WSTRB_in[7] = (SAXIGP4WSTRB[7] !== 1'bz) && SAXIGP4WSTRB[7]; // rv 0 + assign SAXIGP4WSTRB_in[8] = (SAXIGP4WSTRB[8] !== 1'bz) && SAXIGP4WSTRB[8]; // rv 0 + assign SAXIGP4WSTRB_in[9] = (SAXIGP4WSTRB[9] !== 1'bz) && SAXIGP4WSTRB[9]; // rv 0 + assign SAXIGP4WVALID_in = (SAXIGP4WVALID !== 1'bz) && SAXIGP4WVALID; // rv 0 + assign SAXIGP5ARADDR_in[0] = (SAXIGP5ARADDR[0] !== 1'bz) && SAXIGP5ARADDR[0]; // rv 0 + assign SAXIGP5ARADDR_in[10] = (SAXIGP5ARADDR[10] !== 1'bz) && SAXIGP5ARADDR[10]; // rv 0 + assign SAXIGP5ARADDR_in[11] = (SAXIGP5ARADDR[11] !== 1'bz) && SAXIGP5ARADDR[11]; // rv 0 + assign SAXIGP5ARADDR_in[12] = (SAXIGP5ARADDR[12] !== 1'bz) && SAXIGP5ARADDR[12]; // rv 0 + assign SAXIGP5ARADDR_in[13] = (SAXIGP5ARADDR[13] !== 1'bz) && SAXIGP5ARADDR[13]; // rv 0 + assign SAXIGP5ARADDR_in[14] = (SAXIGP5ARADDR[14] !== 1'bz) && SAXIGP5ARADDR[14]; // rv 0 + assign SAXIGP5ARADDR_in[15] = (SAXIGP5ARADDR[15] !== 1'bz) && SAXIGP5ARADDR[15]; // rv 0 + assign SAXIGP5ARADDR_in[16] = (SAXIGP5ARADDR[16] !== 1'bz) && SAXIGP5ARADDR[16]; // rv 0 + assign SAXIGP5ARADDR_in[17] = (SAXIGP5ARADDR[17] !== 1'bz) && SAXIGP5ARADDR[17]; // rv 0 + assign SAXIGP5ARADDR_in[18] = (SAXIGP5ARADDR[18] !== 1'bz) && SAXIGP5ARADDR[18]; // rv 0 + assign SAXIGP5ARADDR_in[19] = (SAXIGP5ARADDR[19] !== 1'bz) && SAXIGP5ARADDR[19]; // rv 0 + assign SAXIGP5ARADDR_in[1] = (SAXIGP5ARADDR[1] !== 1'bz) && SAXIGP5ARADDR[1]; // rv 0 + assign SAXIGP5ARADDR_in[20] = (SAXIGP5ARADDR[20] !== 1'bz) && SAXIGP5ARADDR[20]; // rv 0 + assign SAXIGP5ARADDR_in[21] = (SAXIGP5ARADDR[21] !== 1'bz) && SAXIGP5ARADDR[21]; // rv 0 + assign SAXIGP5ARADDR_in[22] = (SAXIGP5ARADDR[22] !== 1'bz) && SAXIGP5ARADDR[22]; // rv 0 + assign SAXIGP5ARADDR_in[23] = (SAXIGP5ARADDR[23] !== 1'bz) && SAXIGP5ARADDR[23]; // rv 0 + assign SAXIGP5ARADDR_in[24] = (SAXIGP5ARADDR[24] !== 1'bz) && SAXIGP5ARADDR[24]; // rv 0 + assign SAXIGP5ARADDR_in[25] = (SAXIGP5ARADDR[25] !== 1'bz) && SAXIGP5ARADDR[25]; // rv 0 + assign SAXIGP5ARADDR_in[26] = (SAXIGP5ARADDR[26] !== 1'bz) && SAXIGP5ARADDR[26]; // rv 0 + assign SAXIGP5ARADDR_in[27] = (SAXIGP5ARADDR[27] !== 1'bz) && SAXIGP5ARADDR[27]; // rv 0 + assign SAXIGP5ARADDR_in[28] = (SAXIGP5ARADDR[28] !== 1'bz) && SAXIGP5ARADDR[28]; // rv 0 + assign SAXIGP5ARADDR_in[29] = (SAXIGP5ARADDR[29] !== 1'bz) && SAXIGP5ARADDR[29]; // rv 0 + assign SAXIGP5ARADDR_in[2] = (SAXIGP5ARADDR[2] !== 1'bz) && SAXIGP5ARADDR[2]; // rv 0 + assign SAXIGP5ARADDR_in[30] = (SAXIGP5ARADDR[30] !== 1'bz) && SAXIGP5ARADDR[30]; // rv 0 + assign SAXIGP5ARADDR_in[31] = (SAXIGP5ARADDR[31] !== 1'bz) && SAXIGP5ARADDR[31]; // rv 0 + assign SAXIGP5ARADDR_in[32] = (SAXIGP5ARADDR[32] !== 1'bz) && SAXIGP5ARADDR[32]; // rv 0 + assign SAXIGP5ARADDR_in[33] = (SAXIGP5ARADDR[33] !== 1'bz) && SAXIGP5ARADDR[33]; // rv 0 + assign SAXIGP5ARADDR_in[34] = (SAXIGP5ARADDR[34] !== 1'bz) && SAXIGP5ARADDR[34]; // rv 0 + assign SAXIGP5ARADDR_in[35] = (SAXIGP5ARADDR[35] !== 1'bz) && SAXIGP5ARADDR[35]; // rv 0 + assign SAXIGP5ARADDR_in[36] = (SAXIGP5ARADDR[36] !== 1'bz) && SAXIGP5ARADDR[36]; // rv 0 + assign SAXIGP5ARADDR_in[37] = (SAXIGP5ARADDR[37] !== 1'bz) && SAXIGP5ARADDR[37]; // rv 0 + assign SAXIGP5ARADDR_in[38] = (SAXIGP5ARADDR[38] !== 1'bz) && SAXIGP5ARADDR[38]; // rv 0 + assign SAXIGP5ARADDR_in[39] = (SAXIGP5ARADDR[39] !== 1'bz) && SAXIGP5ARADDR[39]; // rv 0 + assign SAXIGP5ARADDR_in[3] = (SAXIGP5ARADDR[3] !== 1'bz) && SAXIGP5ARADDR[3]; // rv 0 + assign SAXIGP5ARADDR_in[40] = (SAXIGP5ARADDR[40] !== 1'bz) && SAXIGP5ARADDR[40]; // rv 0 + assign SAXIGP5ARADDR_in[41] = (SAXIGP5ARADDR[41] !== 1'bz) && SAXIGP5ARADDR[41]; // rv 0 + assign SAXIGP5ARADDR_in[42] = (SAXIGP5ARADDR[42] !== 1'bz) && SAXIGP5ARADDR[42]; // rv 0 + assign SAXIGP5ARADDR_in[43] = (SAXIGP5ARADDR[43] !== 1'bz) && SAXIGP5ARADDR[43]; // rv 0 + assign SAXIGP5ARADDR_in[44] = (SAXIGP5ARADDR[44] !== 1'bz) && SAXIGP5ARADDR[44]; // rv 0 + assign SAXIGP5ARADDR_in[45] = (SAXIGP5ARADDR[45] !== 1'bz) && SAXIGP5ARADDR[45]; // rv 0 + assign SAXIGP5ARADDR_in[46] = (SAXIGP5ARADDR[46] !== 1'bz) && SAXIGP5ARADDR[46]; // rv 0 + assign SAXIGP5ARADDR_in[47] = (SAXIGP5ARADDR[47] !== 1'bz) && SAXIGP5ARADDR[47]; // rv 0 + assign SAXIGP5ARADDR_in[48] = (SAXIGP5ARADDR[48] !== 1'bz) && SAXIGP5ARADDR[48]; // rv 0 + assign SAXIGP5ARADDR_in[4] = (SAXIGP5ARADDR[4] !== 1'bz) && SAXIGP5ARADDR[4]; // rv 0 + assign SAXIGP5ARADDR_in[5] = (SAXIGP5ARADDR[5] !== 1'bz) && SAXIGP5ARADDR[5]; // rv 0 + assign SAXIGP5ARADDR_in[6] = (SAXIGP5ARADDR[6] !== 1'bz) && SAXIGP5ARADDR[6]; // rv 0 + assign SAXIGP5ARADDR_in[7] = (SAXIGP5ARADDR[7] !== 1'bz) && SAXIGP5ARADDR[7]; // rv 0 + assign SAXIGP5ARADDR_in[8] = (SAXIGP5ARADDR[8] !== 1'bz) && SAXIGP5ARADDR[8]; // rv 0 + assign SAXIGP5ARADDR_in[9] = (SAXIGP5ARADDR[9] !== 1'bz) && SAXIGP5ARADDR[9]; // rv 0 + assign SAXIGP5ARBURST_in[0] = (SAXIGP5ARBURST[0] !== 1'bz) && SAXIGP5ARBURST[0]; // rv 0 + assign SAXIGP5ARBURST_in[1] = (SAXIGP5ARBURST[1] !== 1'bz) && SAXIGP5ARBURST[1]; // rv 0 + assign SAXIGP5ARCACHE_in[0] = (SAXIGP5ARCACHE[0] !== 1'bz) && SAXIGP5ARCACHE[0]; // rv 0 + assign SAXIGP5ARCACHE_in[1] = (SAXIGP5ARCACHE[1] !== 1'bz) && SAXIGP5ARCACHE[1]; // rv 0 + assign SAXIGP5ARCACHE_in[2] = (SAXIGP5ARCACHE[2] !== 1'bz) && SAXIGP5ARCACHE[2]; // rv 0 + assign SAXIGP5ARCACHE_in[3] = (SAXIGP5ARCACHE[3] !== 1'bz) && SAXIGP5ARCACHE[3]; // rv 0 + assign SAXIGP5ARID_in[0] = (SAXIGP5ARID[0] !== 1'bz) && SAXIGP5ARID[0]; // rv 0 + assign SAXIGP5ARID_in[1] = (SAXIGP5ARID[1] !== 1'bz) && SAXIGP5ARID[1]; // rv 0 + assign SAXIGP5ARID_in[2] = (SAXIGP5ARID[2] !== 1'bz) && SAXIGP5ARID[2]; // rv 0 + assign SAXIGP5ARID_in[3] = (SAXIGP5ARID[3] !== 1'bz) && SAXIGP5ARID[3]; // rv 0 + assign SAXIGP5ARID_in[4] = (SAXIGP5ARID[4] !== 1'bz) && SAXIGP5ARID[4]; // rv 0 + assign SAXIGP5ARID_in[5] = (SAXIGP5ARID[5] !== 1'bz) && SAXIGP5ARID[5]; // rv 0 + assign SAXIGP5ARLEN_in[0] = (SAXIGP5ARLEN[0] !== 1'bz) && SAXIGP5ARLEN[0]; // rv 0 + assign SAXIGP5ARLEN_in[1] = (SAXIGP5ARLEN[1] !== 1'bz) && SAXIGP5ARLEN[1]; // rv 0 + assign SAXIGP5ARLEN_in[2] = (SAXIGP5ARLEN[2] !== 1'bz) && SAXIGP5ARLEN[2]; // rv 0 + assign SAXIGP5ARLEN_in[3] = (SAXIGP5ARLEN[3] !== 1'bz) && SAXIGP5ARLEN[3]; // rv 0 + assign SAXIGP5ARLEN_in[4] = (SAXIGP5ARLEN[4] !== 1'bz) && SAXIGP5ARLEN[4]; // rv 0 + assign SAXIGP5ARLEN_in[5] = (SAXIGP5ARLEN[5] !== 1'bz) && SAXIGP5ARLEN[5]; // rv 0 + assign SAXIGP5ARLEN_in[6] = (SAXIGP5ARLEN[6] !== 1'bz) && SAXIGP5ARLEN[6]; // rv 0 + assign SAXIGP5ARLEN_in[7] = (SAXIGP5ARLEN[7] !== 1'bz) && SAXIGP5ARLEN[7]; // rv 0 + assign SAXIGP5ARLOCK_in = (SAXIGP5ARLOCK !== 1'bz) && SAXIGP5ARLOCK; // rv 0 + assign SAXIGP5ARPROT_in[0] = (SAXIGP5ARPROT[0] !== 1'bz) && SAXIGP5ARPROT[0]; // rv 0 + assign SAXIGP5ARPROT_in[1] = (SAXIGP5ARPROT[1] !== 1'bz) && SAXIGP5ARPROT[1]; // rv 0 + assign SAXIGP5ARPROT_in[2] = (SAXIGP5ARPROT[2] !== 1'bz) && SAXIGP5ARPROT[2]; // rv 0 + assign SAXIGP5ARQOS_in[0] = (SAXIGP5ARQOS[0] !== 1'bz) && SAXIGP5ARQOS[0]; // rv 0 + assign SAXIGP5ARQOS_in[1] = (SAXIGP5ARQOS[1] !== 1'bz) && SAXIGP5ARQOS[1]; // rv 0 + assign SAXIGP5ARQOS_in[2] = (SAXIGP5ARQOS[2] !== 1'bz) && SAXIGP5ARQOS[2]; // rv 0 + assign SAXIGP5ARQOS_in[3] = (SAXIGP5ARQOS[3] !== 1'bz) && SAXIGP5ARQOS[3]; // rv 0 + assign SAXIGP5ARSIZE_in[0] = (SAXIGP5ARSIZE[0] !== 1'bz) && SAXIGP5ARSIZE[0]; // rv 0 + assign SAXIGP5ARSIZE_in[1] = (SAXIGP5ARSIZE[1] !== 1'bz) && SAXIGP5ARSIZE[1]; // rv 0 + assign SAXIGP5ARSIZE_in[2] = (SAXIGP5ARSIZE[2] !== 1'bz) && SAXIGP5ARSIZE[2]; // rv 0 + assign SAXIGP5ARUSER_in = (SAXIGP5ARUSER !== 1'bz) && SAXIGP5ARUSER; // rv 0 + assign SAXIGP5ARVALID_in = (SAXIGP5ARVALID !== 1'bz) && SAXIGP5ARVALID; // rv 0 + assign SAXIGP5AWADDR_in[0] = (SAXIGP5AWADDR[0] !== 1'bz) && SAXIGP5AWADDR[0]; // rv 0 + assign SAXIGP5AWADDR_in[10] = (SAXIGP5AWADDR[10] !== 1'bz) && SAXIGP5AWADDR[10]; // rv 0 + assign SAXIGP5AWADDR_in[11] = (SAXIGP5AWADDR[11] !== 1'bz) && SAXIGP5AWADDR[11]; // rv 0 + assign SAXIGP5AWADDR_in[12] = (SAXIGP5AWADDR[12] !== 1'bz) && SAXIGP5AWADDR[12]; // rv 0 + assign SAXIGP5AWADDR_in[13] = (SAXIGP5AWADDR[13] !== 1'bz) && SAXIGP5AWADDR[13]; // rv 0 + assign SAXIGP5AWADDR_in[14] = (SAXIGP5AWADDR[14] !== 1'bz) && SAXIGP5AWADDR[14]; // rv 0 + assign SAXIGP5AWADDR_in[15] = (SAXIGP5AWADDR[15] !== 1'bz) && SAXIGP5AWADDR[15]; // rv 0 + assign SAXIGP5AWADDR_in[16] = (SAXIGP5AWADDR[16] !== 1'bz) && SAXIGP5AWADDR[16]; // rv 0 + assign SAXIGP5AWADDR_in[17] = (SAXIGP5AWADDR[17] !== 1'bz) && SAXIGP5AWADDR[17]; // rv 0 + assign SAXIGP5AWADDR_in[18] = (SAXIGP5AWADDR[18] !== 1'bz) && SAXIGP5AWADDR[18]; // rv 0 + assign SAXIGP5AWADDR_in[19] = (SAXIGP5AWADDR[19] !== 1'bz) && SAXIGP5AWADDR[19]; // rv 0 + assign SAXIGP5AWADDR_in[1] = (SAXIGP5AWADDR[1] !== 1'bz) && SAXIGP5AWADDR[1]; // rv 0 + assign SAXIGP5AWADDR_in[20] = (SAXIGP5AWADDR[20] !== 1'bz) && SAXIGP5AWADDR[20]; // rv 0 + assign SAXIGP5AWADDR_in[21] = (SAXIGP5AWADDR[21] !== 1'bz) && SAXIGP5AWADDR[21]; // rv 0 + assign SAXIGP5AWADDR_in[22] = (SAXIGP5AWADDR[22] !== 1'bz) && SAXIGP5AWADDR[22]; // rv 0 + assign SAXIGP5AWADDR_in[23] = (SAXIGP5AWADDR[23] !== 1'bz) && SAXIGP5AWADDR[23]; // rv 0 + assign SAXIGP5AWADDR_in[24] = (SAXIGP5AWADDR[24] !== 1'bz) && SAXIGP5AWADDR[24]; // rv 0 + assign SAXIGP5AWADDR_in[25] = (SAXIGP5AWADDR[25] !== 1'bz) && SAXIGP5AWADDR[25]; // rv 0 + assign SAXIGP5AWADDR_in[26] = (SAXIGP5AWADDR[26] !== 1'bz) && SAXIGP5AWADDR[26]; // rv 0 + assign SAXIGP5AWADDR_in[27] = (SAXIGP5AWADDR[27] !== 1'bz) && SAXIGP5AWADDR[27]; // rv 0 + assign SAXIGP5AWADDR_in[28] = (SAXIGP5AWADDR[28] !== 1'bz) && SAXIGP5AWADDR[28]; // rv 0 + assign SAXIGP5AWADDR_in[29] = (SAXIGP5AWADDR[29] !== 1'bz) && SAXIGP5AWADDR[29]; // rv 0 + assign SAXIGP5AWADDR_in[2] = (SAXIGP5AWADDR[2] !== 1'bz) && SAXIGP5AWADDR[2]; // rv 0 + assign SAXIGP5AWADDR_in[30] = (SAXIGP5AWADDR[30] !== 1'bz) && SAXIGP5AWADDR[30]; // rv 0 + assign SAXIGP5AWADDR_in[31] = (SAXIGP5AWADDR[31] !== 1'bz) && SAXIGP5AWADDR[31]; // rv 0 + assign SAXIGP5AWADDR_in[32] = (SAXIGP5AWADDR[32] !== 1'bz) && SAXIGP5AWADDR[32]; // rv 0 + assign SAXIGP5AWADDR_in[33] = (SAXIGP5AWADDR[33] !== 1'bz) && SAXIGP5AWADDR[33]; // rv 0 + assign SAXIGP5AWADDR_in[34] = (SAXIGP5AWADDR[34] !== 1'bz) && SAXIGP5AWADDR[34]; // rv 0 + assign SAXIGP5AWADDR_in[35] = (SAXIGP5AWADDR[35] !== 1'bz) && SAXIGP5AWADDR[35]; // rv 0 + assign SAXIGP5AWADDR_in[36] = (SAXIGP5AWADDR[36] !== 1'bz) && SAXIGP5AWADDR[36]; // rv 0 + assign SAXIGP5AWADDR_in[37] = (SAXIGP5AWADDR[37] !== 1'bz) && SAXIGP5AWADDR[37]; // rv 0 + assign SAXIGP5AWADDR_in[38] = (SAXIGP5AWADDR[38] !== 1'bz) && SAXIGP5AWADDR[38]; // rv 0 + assign SAXIGP5AWADDR_in[39] = (SAXIGP5AWADDR[39] !== 1'bz) && SAXIGP5AWADDR[39]; // rv 0 + assign SAXIGP5AWADDR_in[3] = (SAXIGP5AWADDR[3] !== 1'bz) && SAXIGP5AWADDR[3]; // rv 0 + assign SAXIGP5AWADDR_in[40] = (SAXIGP5AWADDR[40] !== 1'bz) && SAXIGP5AWADDR[40]; // rv 0 + assign SAXIGP5AWADDR_in[41] = (SAXIGP5AWADDR[41] !== 1'bz) && SAXIGP5AWADDR[41]; // rv 0 + assign SAXIGP5AWADDR_in[42] = (SAXIGP5AWADDR[42] !== 1'bz) && SAXIGP5AWADDR[42]; // rv 0 + assign SAXIGP5AWADDR_in[43] = (SAXIGP5AWADDR[43] !== 1'bz) && SAXIGP5AWADDR[43]; // rv 0 + assign SAXIGP5AWADDR_in[44] = (SAXIGP5AWADDR[44] !== 1'bz) && SAXIGP5AWADDR[44]; // rv 0 + assign SAXIGP5AWADDR_in[45] = (SAXIGP5AWADDR[45] !== 1'bz) && SAXIGP5AWADDR[45]; // rv 0 + assign SAXIGP5AWADDR_in[46] = (SAXIGP5AWADDR[46] !== 1'bz) && SAXIGP5AWADDR[46]; // rv 0 + assign SAXIGP5AWADDR_in[47] = (SAXIGP5AWADDR[47] !== 1'bz) && SAXIGP5AWADDR[47]; // rv 0 + assign SAXIGP5AWADDR_in[48] = (SAXIGP5AWADDR[48] !== 1'bz) && SAXIGP5AWADDR[48]; // rv 0 + assign SAXIGP5AWADDR_in[4] = (SAXIGP5AWADDR[4] !== 1'bz) && SAXIGP5AWADDR[4]; // rv 0 + assign SAXIGP5AWADDR_in[5] = (SAXIGP5AWADDR[5] !== 1'bz) && SAXIGP5AWADDR[5]; // rv 0 + assign SAXIGP5AWADDR_in[6] = (SAXIGP5AWADDR[6] !== 1'bz) && SAXIGP5AWADDR[6]; // rv 0 + assign SAXIGP5AWADDR_in[7] = (SAXIGP5AWADDR[7] !== 1'bz) && SAXIGP5AWADDR[7]; // rv 0 + assign SAXIGP5AWADDR_in[8] = (SAXIGP5AWADDR[8] !== 1'bz) && SAXIGP5AWADDR[8]; // rv 0 + assign SAXIGP5AWADDR_in[9] = (SAXIGP5AWADDR[9] !== 1'bz) && SAXIGP5AWADDR[9]; // rv 0 + assign SAXIGP5AWBURST_in[0] = (SAXIGP5AWBURST[0] !== 1'bz) && SAXIGP5AWBURST[0]; // rv 0 + assign SAXIGP5AWBURST_in[1] = (SAXIGP5AWBURST[1] !== 1'bz) && SAXIGP5AWBURST[1]; // rv 0 + assign SAXIGP5AWCACHE_in[0] = (SAXIGP5AWCACHE[0] !== 1'bz) && SAXIGP5AWCACHE[0]; // rv 0 + assign SAXIGP5AWCACHE_in[1] = (SAXIGP5AWCACHE[1] !== 1'bz) && SAXIGP5AWCACHE[1]; // rv 0 + assign SAXIGP5AWCACHE_in[2] = (SAXIGP5AWCACHE[2] !== 1'bz) && SAXIGP5AWCACHE[2]; // rv 0 + assign SAXIGP5AWCACHE_in[3] = (SAXIGP5AWCACHE[3] !== 1'bz) && SAXIGP5AWCACHE[3]; // rv 0 + assign SAXIGP5AWID_in[0] = (SAXIGP5AWID[0] !== 1'bz) && SAXIGP5AWID[0]; // rv 0 + assign SAXIGP5AWID_in[1] = (SAXIGP5AWID[1] !== 1'bz) && SAXIGP5AWID[1]; // rv 0 + assign SAXIGP5AWID_in[2] = (SAXIGP5AWID[2] !== 1'bz) && SAXIGP5AWID[2]; // rv 0 + assign SAXIGP5AWID_in[3] = (SAXIGP5AWID[3] !== 1'bz) && SAXIGP5AWID[3]; // rv 0 + assign SAXIGP5AWID_in[4] = (SAXIGP5AWID[4] !== 1'bz) && SAXIGP5AWID[4]; // rv 0 + assign SAXIGP5AWID_in[5] = (SAXIGP5AWID[5] !== 1'bz) && SAXIGP5AWID[5]; // rv 0 + assign SAXIGP5AWLEN_in[0] = (SAXIGP5AWLEN[0] !== 1'bz) && SAXIGP5AWLEN[0]; // rv 0 + assign SAXIGP5AWLEN_in[1] = (SAXIGP5AWLEN[1] !== 1'bz) && SAXIGP5AWLEN[1]; // rv 0 + assign SAXIGP5AWLEN_in[2] = (SAXIGP5AWLEN[2] !== 1'bz) && SAXIGP5AWLEN[2]; // rv 0 + assign SAXIGP5AWLEN_in[3] = (SAXIGP5AWLEN[3] !== 1'bz) && SAXIGP5AWLEN[3]; // rv 0 + assign SAXIGP5AWLEN_in[4] = (SAXIGP5AWLEN[4] !== 1'bz) && SAXIGP5AWLEN[4]; // rv 0 + assign SAXIGP5AWLEN_in[5] = (SAXIGP5AWLEN[5] !== 1'bz) && SAXIGP5AWLEN[5]; // rv 0 + assign SAXIGP5AWLEN_in[6] = (SAXIGP5AWLEN[6] !== 1'bz) && SAXIGP5AWLEN[6]; // rv 0 + assign SAXIGP5AWLEN_in[7] = (SAXIGP5AWLEN[7] !== 1'bz) && SAXIGP5AWLEN[7]; // rv 0 + assign SAXIGP5AWLOCK_in = (SAXIGP5AWLOCK !== 1'bz) && SAXIGP5AWLOCK; // rv 0 + assign SAXIGP5AWPROT_in[0] = (SAXIGP5AWPROT[0] !== 1'bz) && SAXIGP5AWPROT[0]; // rv 0 + assign SAXIGP5AWPROT_in[1] = (SAXIGP5AWPROT[1] !== 1'bz) && SAXIGP5AWPROT[1]; // rv 0 + assign SAXIGP5AWPROT_in[2] = (SAXIGP5AWPROT[2] !== 1'bz) && SAXIGP5AWPROT[2]; // rv 0 + assign SAXIGP5AWQOS_in[0] = (SAXIGP5AWQOS[0] !== 1'bz) && SAXIGP5AWQOS[0]; // rv 0 + assign SAXIGP5AWQOS_in[1] = (SAXIGP5AWQOS[1] !== 1'bz) && SAXIGP5AWQOS[1]; // rv 0 + assign SAXIGP5AWQOS_in[2] = (SAXIGP5AWQOS[2] !== 1'bz) && SAXIGP5AWQOS[2]; // rv 0 + assign SAXIGP5AWQOS_in[3] = (SAXIGP5AWQOS[3] !== 1'bz) && SAXIGP5AWQOS[3]; // rv 0 + assign SAXIGP5AWSIZE_in[0] = (SAXIGP5AWSIZE[0] !== 1'bz) && SAXIGP5AWSIZE[0]; // rv 0 + assign SAXIGP5AWSIZE_in[1] = (SAXIGP5AWSIZE[1] !== 1'bz) && SAXIGP5AWSIZE[1]; // rv 0 + assign SAXIGP5AWSIZE_in[2] = (SAXIGP5AWSIZE[2] !== 1'bz) && SAXIGP5AWSIZE[2]; // rv 0 + assign SAXIGP5AWUSER_in = (SAXIGP5AWUSER !== 1'bz) && SAXIGP5AWUSER; // rv 0 + assign SAXIGP5AWVALID_in = (SAXIGP5AWVALID !== 1'bz) && SAXIGP5AWVALID; // rv 0 + assign SAXIGP5BREADY_in = (SAXIGP5BREADY !== 1'bz) && SAXIGP5BREADY; // rv 0 + assign SAXIGP5RCLK_in = (SAXIGP5RCLK !== 1'bz) && SAXIGP5RCLK; // rv 0 + assign SAXIGP5RREADY_in = (SAXIGP5RREADY !== 1'bz) && SAXIGP5RREADY; // rv 0 + assign SAXIGP5WCLK_in = (SAXIGP5WCLK !== 1'bz) && SAXIGP5WCLK; // rv 0 + assign SAXIGP5WDATA_in[0] = (SAXIGP5WDATA[0] !== 1'bz) && SAXIGP5WDATA[0]; // rv 0 + assign SAXIGP5WDATA_in[100] = (SAXIGP5WDATA[100] !== 1'bz) && SAXIGP5WDATA[100]; // rv 0 + assign SAXIGP5WDATA_in[101] = (SAXIGP5WDATA[101] !== 1'bz) && SAXIGP5WDATA[101]; // rv 0 + assign SAXIGP5WDATA_in[102] = (SAXIGP5WDATA[102] !== 1'bz) && SAXIGP5WDATA[102]; // rv 0 + assign SAXIGP5WDATA_in[103] = (SAXIGP5WDATA[103] !== 1'bz) && SAXIGP5WDATA[103]; // rv 0 + assign SAXIGP5WDATA_in[104] = (SAXIGP5WDATA[104] !== 1'bz) && SAXIGP5WDATA[104]; // rv 0 + assign SAXIGP5WDATA_in[105] = (SAXIGP5WDATA[105] !== 1'bz) && SAXIGP5WDATA[105]; // rv 0 + assign SAXIGP5WDATA_in[106] = (SAXIGP5WDATA[106] !== 1'bz) && SAXIGP5WDATA[106]; // rv 0 + assign SAXIGP5WDATA_in[107] = (SAXIGP5WDATA[107] !== 1'bz) && SAXIGP5WDATA[107]; // rv 0 + assign SAXIGP5WDATA_in[108] = (SAXIGP5WDATA[108] !== 1'bz) && SAXIGP5WDATA[108]; // rv 0 + assign SAXIGP5WDATA_in[109] = (SAXIGP5WDATA[109] !== 1'bz) && SAXIGP5WDATA[109]; // rv 0 + assign SAXIGP5WDATA_in[10] = (SAXIGP5WDATA[10] !== 1'bz) && SAXIGP5WDATA[10]; // rv 0 + assign SAXIGP5WDATA_in[110] = (SAXIGP5WDATA[110] !== 1'bz) && SAXIGP5WDATA[110]; // rv 0 + assign SAXIGP5WDATA_in[111] = (SAXIGP5WDATA[111] !== 1'bz) && SAXIGP5WDATA[111]; // rv 0 + assign SAXIGP5WDATA_in[112] = (SAXIGP5WDATA[112] !== 1'bz) && SAXIGP5WDATA[112]; // rv 0 + assign SAXIGP5WDATA_in[113] = (SAXIGP5WDATA[113] !== 1'bz) && SAXIGP5WDATA[113]; // rv 0 + assign SAXIGP5WDATA_in[114] = (SAXIGP5WDATA[114] !== 1'bz) && SAXIGP5WDATA[114]; // rv 0 + assign SAXIGP5WDATA_in[115] = (SAXIGP5WDATA[115] !== 1'bz) && SAXIGP5WDATA[115]; // rv 0 + assign SAXIGP5WDATA_in[116] = (SAXIGP5WDATA[116] !== 1'bz) && SAXIGP5WDATA[116]; // rv 0 + assign SAXIGP5WDATA_in[117] = (SAXIGP5WDATA[117] !== 1'bz) && SAXIGP5WDATA[117]; // rv 0 + assign SAXIGP5WDATA_in[118] = (SAXIGP5WDATA[118] !== 1'bz) && SAXIGP5WDATA[118]; // rv 0 + assign SAXIGP5WDATA_in[119] = (SAXIGP5WDATA[119] !== 1'bz) && SAXIGP5WDATA[119]; // rv 0 + assign SAXIGP5WDATA_in[11] = (SAXIGP5WDATA[11] !== 1'bz) && SAXIGP5WDATA[11]; // rv 0 + assign SAXIGP5WDATA_in[120] = (SAXIGP5WDATA[120] !== 1'bz) && SAXIGP5WDATA[120]; // rv 0 + assign SAXIGP5WDATA_in[121] = (SAXIGP5WDATA[121] !== 1'bz) && SAXIGP5WDATA[121]; // rv 0 + assign SAXIGP5WDATA_in[122] = (SAXIGP5WDATA[122] !== 1'bz) && SAXIGP5WDATA[122]; // rv 0 + assign SAXIGP5WDATA_in[123] = (SAXIGP5WDATA[123] !== 1'bz) && SAXIGP5WDATA[123]; // rv 0 + assign SAXIGP5WDATA_in[124] = (SAXIGP5WDATA[124] !== 1'bz) && SAXIGP5WDATA[124]; // rv 0 + assign SAXIGP5WDATA_in[125] = (SAXIGP5WDATA[125] !== 1'bz) && SAXIGP5WDATA[125]; // rv 0 + assign SAXIGP5WDATA_in[126] = (SAXIGP5WDATA[126] !== 1'bz) && SAXIGP5WDATA[126]; // rv 0 + assign SAXIGP5WDATA_in[127] = (SAXIGP5WDATA[127] !== 1'bz) && SAXIGP5WDATA[127]; // rv 0 + assign SAXIGP5WDATA_in[12] = (SAXIGP5WDATA[12] !== 1'bz) && SAXIGP5WDATA[12]; // rv 0 + assign SAXIGP5WDATA_in[13] = (SAXIGP5WDATA[13] !== 1'bz) && SAXIGP5WDATA[13]; // rv 0 + assign SAXIGP5WDATA_in[14] = (SAXIGP5WDATA[14] !== 1'bz) && SAXIGP5WDATA[14]; // rv 0 + assign SAXIGP5WDATA_in[15] = (SAXIGP5WDATA[15] !== 1'bz) && SAXIGP5WDATA[15]; // rv 0 + assign SAXIGP5WDATA_in[16] = (SAXIGP5WDATA[16] !== 1'bz) && SAXIGP5WDATA[16]; // rv 0 + assign SAXIGP5WDATA_in[17] = (SAXIGP5WDATA[17] !== 1'bz) && SAXIGP5WDATA[17]; // rv 0 + assign SAXIGP5WDATA_in[18] = (SAXIGP5WDATA[18] !== 1'bz) && SAXIGP5WDATA[18]; // rv 0 + assign SAXIGP5WDATA_in[19] = (SAXIGP5WDATA[19] !== 1'bz) && SAXIGP5WDATA[19]; // rv 0 + assign SAXIGP5WDATA_in[1] = (SAXIGP5WDATA[1] !== 1'bz) && SAXIGP5WDATA[1]; // rv 0 + assign SAXIGP5WDATA_in[20] = (SAXIGP5WDATA[20] !== 1'bz) && SAXIGP5WDATA[20]; // rv 0 + assign SAXIGP5WDATA_in[21] = (SAXIGP5WDATA[21] !== 1'bz) && SAXIGP5WDATA[21]; // rv 0 + assign SAXIGP5WDATA_in[22] = (SAXIGP5WDATA[22] !== 1'bz) && SAXIGP5WDATA[22]; // rv 0 + assign SAXIGP5WDATA_in[23] = (SAXIGP5WDATA[23] !== 1'bz) && SAXIGP5WDATA[23]; // rv 0 + assign SAXIGP5WDATA_in[24] = (SAXIGP5WDATA[24] !== 1'bz) && SAXIGP5WDATA[24]; // rv 0 + assign SAXIGP5WDATA_in[25] = (SAXIGP5WDATA[25] !== 1'bz) && SAXIGP5WDATA[25]; // rv 0 + assign SAXIGP5WDATA_in[26] = (SAXIGP5WDATA[26] !== 1'bz) && SAXIGP5WDATA[26]; // rv 0 + assign SAXIGP5WDATA_in[27] = (SAXIGP5WDATA[27] !== 1'bz) && SAXIGP5WDATA[27]; // rv 0 + assign SAXIGP5WDATA_in[28] = (SAXIGP5WDATA[28] !== 1'bz) && SAXIGP5WDATA[28]; // rv 0 + assign SAXIGP5WDATA_in[29] = (SAXIGP5WDATA[29] !== 1'bz) && SAXIGP5WDATA[29]; // rv 0 + assign SAXIGP5WDATA_in[2] = (SAXIGP5WDATA[2] !== 1'bz) && SAXIGP5WDATA[2]; // rv 0 + assign SAXIGP5WDATA_in[30] = (SAXIGP5WDATA[30] !== 1'bz) && SAXIGP5WDATA[30]; // rv 0 + assign SAXIGP5WDATA_in[31] = (SAXIGP5WDATA[31] !== 1'bz) && SAXIGP5WDATA[31]; // rv 0 + assign SAXIGP5WDATA_in[32] = (SAXIGP5WDATA[32] !== 1'bz) && SAXIGP5WDATA[32]; // rv 0 + assign SAXIGP5WDATA_in[33] = (SAXIGP5WDATA[33] !== 1'bz) && SAXIGP5WDATA[33]; // rv 0 + assign SAXIGP5WDATA_in[34] = (SAXIGP5WDATA[34] !== 1'bz) && SAXIGP5WDATA[34]; // rv 0 + assign SAXIGP5WDATA_in[35] = (SAXIGP5WDATA[35] !== 1'bz) && SAXIGP5WDATA[35]; // rv 0 + assign SAXIGP5WDATA_in[36] = (SAXIGP5WDATA[36] !== 1'bz) && SAXIGP5WDATA[36]; // rv 0 + assign SAXIGP5WDATA_in[37] = (SAXIGP5WDATA[37] !== 1'bz) && SAXIGP5WDATA[37]; // rv 0 + assign SAXIGP5WDATA_in[38] = (SAXIGP5WDATA[38] !== 1'bz) && SAXIGP5WDATA[38]; // rv 0 + assign SAXIGP5WDATA_in[39] = (SAXIGP5WDATA[39] !== 1'bz) && SAXIGP5WDATA[39]; // rv 0 + assign SAXIGP5WDATA_in[3] = (SAXIGP5WDATA[3] !== 1'bz) && SAXIGP5WDATA[3]; // rv 0 + assign SAXIGP5WDATA_in[40] = (SAXIGP5WDATA[40] !== 1'bz) && SAXIGP5WDATA[40]; // rv 0 + assign SAXIGP5WDATA_in[41] = (SAXIGP5WDATA[41] !== 1'bz) && SAXIGP5WDATA[41]; // rv 0 + assign SAXIGP5WDATA_in[42] = (SAXIGP5WDATA[42] !== 1'bz) && SAXIGP5WDATA[42]; // rv 0 + assign SAXIGP5WDATA_in[43] = (SAXIGP5WDATA[43] !== 1'bz) && SAXIGP5WDATA[43]; // rv 0 + assign SAXIGP5WDATA_in[44] = (SAXIGP5WDATA[44] !== 1'bz) && SAXIGP5WDATA[44]; // rv 0 + assign SAXIGP5WDATA_in[45] = (SAXIGP5WDATA[45] !== 1'bz) && SAXIGP5WDATA[45]; // rv 0 + assign SAXIGP5WDATA_in[46] = (SAXIGP5WDATA[46] !== 1'bz) && SAXIGP5WDATA[46]; // rv 0 + assign SAXIGP5WDATA_in[47] = (SAXIGP5WDATA[47] !== 1'bz) && SAXIGP5WDATA[47]; // rv 0 + assign SAXIGP5WDATA_in[48] = (SAXIGP5WDATA[48] !== 1'bz) && SAXIGP5WDATA[48]; // rv 0 + assign SAXIGP5WDATA_in[49] = (SAXIGP5WDATA[49] !== 1'bz) && SAXIGP5WDATA[49]; // rv 0 + assign SAXIGP5WDATA_in[4] = (SAXIGP5WDATA[4] !== 1'bz) && SAXIGP5WDATA[4]; // rv 0 + assign SAXIGP5WDATA_in[50] = (SAXIGP5WDATA[50] !== 1'bz) && SAXIGP5WDATA[50]; // rv 0 + assign SAXIGP5WDATA_in[51] = (SAXIGP5WDATA[51] !== 1'bz) && SAXIGP5WDATA[51]; // rv 0 + assign SAXIGP5WDATA_in[52] = (SAXIGP5WDATA[52] !== 1'bz) && SAXIGP5WDATA[52]; // rv 0 + assign SAXIGP5WDATA_in[53] = (SAXIGP5WDATA[53] !== 1'bz) && SAXIGP5WDATA[53]; // rv 0 + assign SAXIGP5WDATA_in[54] = (SAXIGP5WDATA[54] !== 1'bz) && SAXIGP5WDATA[54]; // rv 0 + assign SAXIGP5WDATA_in[55] = (SAXIGP5WDATA[55] !== 1'bz) && SAXIGP5WDATA[55]; // rv 0 + assign SAXIGP5WDATA_in[56] = (SAXIGP5WDATA[56] !== 1'bz) && SAXIGP5WDATA[56]; // rv 0 + assign SAXIGP5WDATA_in[57] = (SAXIGP5WDATA[57] !== 1'bz) && SAXIGP5WDATA[57]; // rv 0 + assign SAXIGP5WDATA_in[58] = (SAXIGP5WDATA[58] !== 1'bz) && SAXIGP5WDATA[58]; // rv 0 + assign SAXIGP5WDATA_in[59] = (SAXIGP5WDATA[59] !== 1'bz) && SAXIGP5WDATA[59]; // rv 0 + assign SAXIGP5WDATA_in[5] = (SAXIGP5WDATA[5] !== 1'bz) && SAXIGP5WDATA[5]; // rv 0 + assign SAXIGP5WDATA_in[60] = (SAXIGP5WDATA[60] !== 1'bz) && SAXIGP5WDATA[60]; // rv 0 + assign SAXIGP5WDATA_in[61] = (SAXIGP5WDATA[61] !== 1'bz) && SAXIGP5WDATA[61]; // rv 0 + assign SAXIGP5WDATA_in[62] = (SAXIGP5WDATA[62] !== 1'bz) && SAXIGP5WDATA[62]; // rv 0 + assign SAXIGP5WDATA_in[63] = (SAXIGP5WDATA[63] !== 1'bz) && SAXIGP5WDATA[63]; // rv 0 + assign SAXIGP5WDATA_in[64] = (SAXIGP5WDATA[64] !== 1'bz) && SAXIGP5WDATA[64]; // rv 0 + assign SAXIGP5WDATA_in[65] = (SAXIGP5WDATA[65] !== 1'bz) && SAXIGP5WDATA[65]; // rv 0 + assign SAXIGP5WDATA_in[66] = (SAXIGP5WDATA[66] !== 1'bz) && SAXIGP5WDATA[66]; // rv 0 + assign SAXIGP5WDATA_in[67] = (SAXIGP5WDATA[67] !== 1'bz) && SAXIGP5WDATA[67]; // rv 0 + assign SAXIGP5WDATA_in[68] = (SAXIGP5WDATA[68] !== 1'bz) && SAXIGP5WDATA[68]; // rv 0 + assign SAXIGP5WDATA_in[69] = (SAXIGP5WDATA[69] !== 1'bz) && SAXIGP5WDATA[69]; // rv 0 + assign SAXIGP5WDATA_in[6] = (SAXIGP5WDATA[6] !== 1'bz) && SAXIGP5WDATA[6]; // rv 0 + assign SAXIGP5WDATA_in[70] = (SAXIGP5WDATA[70] !== 1'bz) && SAXIGP5WDATA[70]; // rv 0 + assign SAXIGP5WDATA_in[71] = (SAXIGP5WDATA[71] !== 1'bz) && SAXIGP5WDATA[71]; // rv 0 + assign SAXIGP5WDATA_in[72] = (SAXIGP5WDATA[72] !== 1'bz) && SAXIGP5WDATA[72]; // rv 0 + assign SAXIGP5WDATA_in[73] = (SAXIGP5WDATA[73] !== 1'bz) && SAXIGP5WDATA[73]; // rv 0 + assign SAXIGP5WDATA_in[74] = (SAXIGP5WDATA[74] !== 1'bz) && SAXIGP5WDATA[74]; // rv 0 + assign SAXIGP5WDATA_in[75] = (SAXIGP5WDATA[75] !== 1'bz) && SAXIGP5WDATA[75]; // rv 0 + assign SAXIGP5WDATA_in[76] = (SAXIGP5WDATA[76] !== 1'bz) && SAXIGP5WDATA[76]; // rv 0 + assign SAXIGP5WDATA_in[77] = (SAXIGP5WDATA[77] !== 1'bz) && SAXIGP5WDATA[77]; // rv 0 + assign SAXIGP5WDATA_in[78] = (SAXIGP5WDATA[78] !== 1'bz) && SAXIGP5WDATA[78]; // rv 0 + assign SAXIGP5WDATA_in[79] = (SAXIGP5WDATA[79] !== 1'bz) && SAXIGP5WDATA[79]; // rv 0 + assign SAXIGP5WDATA_in[7] = (SAXIGP5WDATA[7] !== 1'bz) && SAXIGP5WDATA[7]; // rv 0 + assign SAXIGP5WDATA_in[80] = (SAXIGP5WDATA[80] !== 1'bz) && SAXIGP5WDATA[80]; // rv 0 + assign SAXIGP5WDATA_in[81] = (SAXIGP5WDATA[81] !== 1'bz) && SAXIGP5WDATA[81]; // rv 0 + assign SAXIGP5WDATA_in[82] = (SAXIGP5WDATA[82] !== 1'bz) && SAXIGP5WDATA[82]; // rv 0 + assign SAXIGP5WDATA_in[83] = (SAXIGP5WDATA[83] !== 1'bz) && SAXIGP5WDATA[83]; // rv 0 + assign SAXIGP5WDATA_in[84] = (SAXIGP5WDATA[84] !== 1'bz) && SAXIGP5WDATA[84]; // rv 0 + assign SAXIGP5WDATA_in[85] = (SAXIGP5WDATA[85] !== 1'bz) && SAXIGP5WDATA[85]; // rv 0 + assign SAXIGP5WDATA_in[86] = (SAXIGP5WDATA[86] !== 1'bz) && SAXIGP5WDATA[86]; // rv 0 + assign SAXIGP5WDATA_in[87] = (SAXIGP5WDATA[87] !== 1'bz) && SAXIGP5WDATA[87]; // rv 0 + assign SAXIGP5WDATA_in[88] = (SAXIGP5WDATA[88] !== 1'bz) && SAXIGP5WDATA[88]; // rv 0 + assign SAXIGP5WDATA_in[89] = (SAXIGP5WDATA[89] !== 1'bz) && SAXIGP5WDATA[89]; // rv 0 + assign SAXIGP5WDATA_in[8] = (SAXIGP5WDATA[8] !== 1'bz) && SAXIGP5WDATA[8]; // rv 0 + assign SAXIGP5WDATA_in[90] = (SAXIGP5WDATA[90] !== 1'bz) && SAXIGP5WDATA[90]; // rv 0 + assign SAXIGP5WDATA_in[91] = (SAXIGP5WDATA[91] !== 1'bz) && SAXIGP5WDATA[91]; // rv 0 + assign SAXIGP5WDATA_in[92] = (SAXIGP5WDATA[92] !== 1'bz) && SAXIGP5WDATA[92]; // rv 0 + assign SAXIGP5WDATA_in[93] = (SAXIGP5WDATA[93] !== 1'bz) && SAXIGP5WDATA[93]; // rv 0 + assign SAXIGP5WDATA_in[94] = (SAXIGP5WDATA[94] !== 1'bz) && SAXIGP5WDATA[94]; // rv 0 + assign SAXIGP5WDATA_in[95] = (SAXIGP5WDATA[95] !== 1'bz) && SAXIGP5WDATA[95]; // rv 0 + assign SAXIGP5WDATA_in[96] = (SAXIGP5WDATA[96] !== 1'bz) && SAXIGP5WDATA[96]; // rv 0 + assign SAXIGP5WDATA_in[97] = (SAXIGP5WDATA[97] !== 1'bz) && SAXIGP5WDATA[97]; // rv 0 + assign SAXIGP5WDATA_in[98] = (SAXIGP5WDATA[98] !== 1'bz) && SAXIGP5WDATA[98]; // rv 0 + assign SAXIGP5WDATA_in[99] = (SAXIGP5WDATA[99] !== 1'bz) && SAXIGP5WDATA[99]; // rv 0 + assign SAXIGP5WDATA_in[9] = (SAXIGP5WDATA[9] !== 1'bz) && SAXIGP5WDATA[9]; // rv 0 + assign SAXIGP5WLAST_in = (SAXIGP5WLAST !== 1'bz) && SAXIGP5WLAST; // rv 0 + assign SAXIGP5WSTRB_in[0] = (SAXIGP5WSTRB[0] !== 1'bz) && SAXIGP5WSTRB[0]; // rv 0 + assign SAXIGP5WSTRB_in[10] = (SAXIGP5WSTRB[10] !== 1'bz) && SAXIGP5WSTRB[10]; // rv 0 + assign SAXIGP5WSTRB_in[11] = (SAXIGP5WSTRB[11] !== 1'bz) && SAXIGP5WSTRB[11]; // rv 0 + assign SAXIGP5WSTRB_in[12] = (SAXIGP5WSTRB[12] !== 1'bz) && SAXIGP5WSTRB[12]; // rv 0 + assign SAXIGP5WSTRB_in[13] = (SAXIGP5WSTRB[13] !== 1'bz) && SAXIGP5WSTRB[13]; // rv 0 + assign SAXIGP5WSTRB_in[14] = (SAXIGP5WSTRB[14] !== 1'bz) && SAXIGP5WSTRB[14]; // rv 0 + assign SAXIGP5WSTRB_in[15] = (SAXIGP5WSTRB[15] !== 1'bz) && SAXIGP5WSTRB[15]; // rv 0 + assign SAXIGP5WSTRB_in[1] = (SAXIGP5WSTRB[1] !== 1'bz) && SAXIGP5WSTRB[1]; // rv 0 + assign SAXIGP5WSTRB_in[2] = (SAXIGP5WSTRB[2] !== 1'bz) && SAXIGP5WSTRB[2]; // rv 0 + assign SAXIGP5WSTRB_in[3] = (SAXIGP5WSTRB[3] !== 1'bz) && SAXIGP5WSTRB[3]; // rv 0 + assign SAXIGP5WSTRB_in[4] = (SAXIGP5WSTRB[4] !== 1'bz) && SAXIGP5WSTRB[4]; // rv 0 + assign SAXIGP5WSTRB_in[5] = (SAXIGP5WSTRB[5] !== 1'bz) && SAXIGP5WSTRB[5]; // rv 0 + assign SAXIGP5WSTRB_in[6] = (SAXIGP5WSTRB[6] !== 1'bz) && SAXIGP5WSTRB[6]; // rv 0 + assign SAXIGP5WSTRB_in[7] = (SAXIGP5WSTRB[7] !== 1'bz) && SAXIGP5WSTRB[7]; // rv 0 + assign SAXIGP5WSTRB_in[8] = (SAXIGP5WSTRB[8] !== 1'bz) && SAXIGP5WSTRB[8]; // rv 0 + assign SAXIGP5WSTRB_in[9] = (SAXIGP5WSTRB[9] !== 1'bz) && SAXIGP5WSTRB[9]; // rv 0 + assign SAXIGP5WVALID_in = (SAXIGP5WVALID !== 1'bz) && SAXIGP5WVALID; // rv 0 + assign SAXIGP6ARADDR_in[0] = (SAXIGP6ARADDR[0] !== 1'bz) && SAXIGP6ARADDR[0]; // rv 0 + assign SAXIGP6ARADDR_in[10] = (SAXIGP6ARADDR[10] !== 1'bz) && SAXIGP6ARADDR[10]; // rv 0 + assign SAXIGP6ARADDR_in[11] = (SAXIGP6ARADDR[11] !== 1'bz) && SAXIGP6ARADDR[11]; // rv 0 + assign SAXIGP6ARADDR_in[12] = (SAXIGP6ARADDR[12] !== 1'bz) && SAXIGP6ARADDR[12]; // rv 0 + assign SAXIGP6ARADDR_in[13] = (SAXIGP6ARADDR[13] !== 1'bz) && SAXIGP6ARADDR[13]; // rv 0 + assign SAXIGP6ARADDR_in[14] = (SAXIGP6ARADDR[14] !== 1'bz) && SAXIGP6ARADDR[14]; // rv 0 + assign SAXIGP6ARADDR_in[15] = (SAXIGP6ARADDR[15] !== 1'bz) && SAXIGP6ARADDR[15]; // rv 0 + assign SAXIGP6ARADDR_in[16] = (SAXIGP6ARADDR[16] !== 1'bz) && SAXIGP6ARADDR[16]; // rv 0 + assign SAXIGP6ARADDR_in[17] = (SAXIGP6ARADDR[17] !== 1'bz) && SAXIGP6ARADDR[17]; // rv 0 + assign SAXIGP6ARADDR_in[18] = (SAXIGP6ARADDR[18] !== 1'bz) && SAXIGP6ARADDR[18]; // rv 0 + assign SAXIGP6ARADDR_in[19] = (SAXIGP6ARADDR[19] !== 1'bz) && SAXIGP6ARADDR[19]; // rv 0 + assign SAXIGP6ARADDR_in[1] = (SAXIGP6ARADDR[1] !== 1'bz) && SAXIGP6ARADDR[1]; // rv 0 + assign SAXIGP6ARADDR_in[20] = (SAXIGP6ARADDR[20] !== 1'bz) && SAXIGP6ARADDR[20]; // rv 0 + assign SAXIGP6ARADDR_in[21] = (SAXIGP6ARADDR[21] !== 1'bz) && SAXIGP6ARADDR[21]; // rv 0 + assign SAXIGP6ARADDR_in[22] = (SAXIGP6ARADDR[22] !== 1'bz) && SAXIGP6ARADDR[22]; // rv 0 + assign SAXIGP6ARADDR_in[23] = (SAXIGP6ARADDR[23] !== 1'bz) && SAXIGP6ARADDR[23]; // rv 0 + assign SAXIGP6ARADDR_in[24] = (SAXIGP6ARADDR[24] !== 1'bz) && SAXIGP6ARADDR[24]; // rv 0 + assign SAXIGP6ARADDR_in[25] = (SAXIGP6ARADDR[25] !== 1'bz) && SAXIGP6ARADDR[25]; // rv 0 + assign SAXIGP6ARADDR_in[26] = (SAXIGP6ARADDR[26] !== 1'bz) && SAXIGP6ARADDR[26]; // rv 0 + assign SAXIGP6ARADDR_in[27] = (SAXIGP6ARADDR[27] !== 1'bz) && SAXIGP6ARADDR[27]; // rv 0 + assign SAXIGP6ARADDR_in[28] = (SAXIGP6ARADDR[28] !== 1'bz) && SAXIGP6ARADDR[28]; // rv 0 + assign SAXIGP6ARADDR_in[29] = (SAXIGP6ARADDR[29] !== 1'bz) && SAXIGP6ARADDR[29]; // rv 0 + assign SAXIGP6ARADDR_in[2] = (SAXIGP6ARADDR[2] !== 1'bz) && SAXIGP6ARADDR[2]; // rv 0 + assign SAXIGP6ARADDR_in[30] = (SAXIGP6ARADDR[30] !== 1'bz) && SAXIGP6ARADDR[30]; // rv 0 + assign SAXIGP6ARADDR_in[31] = (SAXIGP6ARADDR[31] !== 1'bz) && SAXIGP6ARADDR[31]; // rv 0 + assign SAXIGP6ARADDR_in[32] = (SAXIGP6ARADDR[32] !== 1'bz) && SAXIGP6ARADDR[32]; // rv 0 + assign SAXIGP6ARADDR_in[33] = (SAXIGP6ARADDR[33] !== 1'bz) && SAXIGP6ARADDR[33]; // rv 0 + assign SAXIGP6ARADDR_in[34] = (SAXIGP6ARADDR[34] !== 1'bz) && SAXIGP6ARADDR[34]; // rv 0 + assign SAXIGP6ARADDR_in[35] = (SAXIGP6ARADDR[35] !== 1'bz) && SAXIGP6ARADDR[35]; // rv 0 + assign SAXIGP6ARADDR_in[36] = (SAXIGP6ARADDR[36] !== 1'bz) && SAXIGP6ARADDR[36]; // rv 0 + assign SAXIGP6ARADDR_in[37] = (SAXIGP6ARADDR[37] !== 1'bz) && SAXIGP6ARADDR[37]; // rv 0 + assign SAXIGP6ARADDR_in[38] = (SAXIGP6ARADDR[38] !== 1'bz) && SAXIGP6ARADDR[38]; // rv 0 + assign SAXIGP6ARADDR_in[39] = (SAXIGP6ARADDR[39] !== 1'bz) && SAXIGP6ARADDR[39]; // rv 0 + assign SAXIGP6ARADDR_in[3] = (SAXIGP6ARADDR[3] !== 1'bz) && SAXIGP6ARADDR[3]; // rv 0 + assign SAXIGP6ARADDR_in[40] = (SAXIGP6ARADDR[40] !== 1'bz) && SAXIGP6ARADDR[40]; // rv 0 + assign SAXIGP6ARADDR_in[41] = (SAXIGP6ARADDR[41] !== 1'bz) && SAXIGP6ARADDR[41]; // rv 0 + assign SAXIGP6ARADDR_in[42] = (SAXIGP6ARADDR[42] !== 1'bz) && SAXIGP6ARADDR[42]; // rv 0 + assign SAXIGP6ARADDR_in[43] = (SAXIGP6ARADDR[43] !== 1'bz) && SAXIGP6ARADDR[43]; // rv 0 + assign SAXIGP6ARADDR_in[44] = (SAXIGP6ARADDR[44] !== 1'bz) && SAXIGP6ARADDR[44]; // rv 0 + assign SAXIGP6ARADDR_in[45] = (SAXIGP6ARADDR[45] !== 1'bz) && SAXIGP6ARADDR[45]; // rv 0 + assign SAXIGP6ARADDR_in[46] = (SAXIGP6ARADDR[46] !== 1'bz) && SAXIGP6ARADDR[46]; // rv 0 + assign SAXIGP6ARADDR_in[47] = (SAXIGP6ARADDR[47] !== 1'bz) && SAXIGP6ARADDR[47]; // rv 0 + assign SAXIGP6ARADDR_in[48] = (SAXIGP6ARADDR[48] !== 1'bz) && SAXIGP6ARADDR[48]; // rv 0 + assign SAXIGP6ARADDR_in[4] = (SAXIGP6ARADDR[4] !== 1'bz) && SAXIGP6ARADDR[4]; // rv 0 + assign SAXIGP6ARADDR_in[5] = (SAXIGP6ARADDR[5] !== 1'bz) && SAXIGP6ARADDR[5]; // rv 0 + assign SAXIGP6ARADDR_in[6] = (SAXIGP6ARADDR[6] !== 1'bz) && SAXIGP6ARADDR[6]; // rv 0 + assign SAXIGP6ARADDR_in[7] = (SAXIGP6ARADDR[7] !== 1'bz) && SAXIGP6ARADDR[7]; // rv 0 + assign SAXIGP6ARADDR_in[8] = (SAXIGP6ARADDR[8] !== 1'bz) && SAXIGP6ARADDR[8]; // rv 0 + assign SAXIGP6ARADDR_in[9] = (SAXIGP6ARADDR[9] !== 1'bz) && SAXIGP6ARADDR[9]; // rv 0 + assign SAXIGP6ARBURST_in[0] = (SAXIGP6ARBURST[0] !== 1'bz) && SAXIGP6ARBURST[0]; // rv 0 + assign SAXIGP6ARBURST_in[1] = (SAXIGP6ARBURST[1] !== 1'bz) && SAXIGP6ARBURST[1]; // rv 0 + assign SAXIGP6ARCACHE_in[0] = (SAXIGP6ARCACHE[0] !== 1'bz) && SAXIGP6ARCACHE[0]; // rv 0 + assign SAXIGP6ARCACHE_in[1] = (SAXIGP6ARCACHE[1] !== 1'bz) && SAXIGP6ARCACHE[1]; // rv 0 + assign SAXIGP6ARCACHE_in[2] = (SAXIGP6ARCACHE[2] !== 1'bz) && SAXIGP6ARCACHE[2]; // rv 0 + assign SAXIGP6ARCACHE_in[3] = (SAXIGP6ARCACHE[3] !== 1'bz) && SAXIGP6ARCACHE[3]; // rv 0 + assign SAXIGP6ARID_in[0] = (SAXIGP6ARID[0] !== 1'bz) && SAXIGP6ARID[0]; // rv 0 + assign SAXIGP6ARID_in[1] = (SAXIGP6ARID[1] !== 1'bz) && SAXIGP6ARID[1]; // rv 0 + assign SAXIGP6ARID_in[2] = (SAXIGP6ARID[2] !== 1'bz) && SAXIGP6ARID[2]; // rv 0 + assign SAXIGP6ARID_in[3] = (SAXIGP6ARID[3] !== 1'bz) && SAXIGP6ARID[3]; // rv 0 + assign SAXIGP6ARID_in[4] = (SAXIGP6ARID[4] !== 1'bz) && SAXIGP6ARID[4]; // rv 0 + assign SAXIGP6ARID_in[5] = (SAXIGP6ARID[5] !== 1'bz) && SAXIGP6ARID[5]; // rv 0 + assign SAXIGP6ARLEN_in[0] = (SAXIGP6ARLEN[0] !== 1'bz) && SAXIGP6ARLEN[0]; // rv 0 + assign SAXIGP6ARLEN_in[1] = (SAXIGP6ARLEN[1] !== 1'bz) && SAXIGP6ARLEN[1]; // rv 0 + assign SAXIGP6ARLEN_in[2] = (SAXIGP6ARLEN[2] !== 1'bz) && SAXIGP6ARLEN[2]; // rv 0 + assign SAXIGP6ARLEN_in[3] = (SAXIGP6ARLEN[3] !== 1'bz) && SAXIGP6ARLEN[3]; // rv 0 + assign SAXIGP6ARLEN_in[4] = (SAXIGP6ARLEN[4] !== 1'bz) && SAXIGP6ARLEN[4]; // rv 0 + assign SAXIGP6ARLEN_in[5] = (SAXIGP6ARLEN[5] !== 1'bz) && SAXIGP6ARLEN[5]; // rv 0 + assign SAXIGP6ARLEN_in[6] = (SAXIGP6ARLEN[6] !== 1'bz) && SAXIGP6ARLEN[6]; // rv 0 + assign SAXIGP6ARLEN_in[7] = (SAXIGP6ARLEN[7] !== 1'bz) && SAXIGP6ARLEN[7]; // rv 0 + assign SAXIGP6ARLOCK_in = (SAXIGP6ARLOCK !== 1'bz) && SAXIGP6ARLOCK; // rv 0 + assign SAXIGP6ARPROT_in[0] = (SAXIGP6ARPROT[0] !== 1'bz) && SAXIGP6ARPROT[0]; // rv 0 + assign SAXIGP6ARPROT_in[1] = (SAXIGP6ARPROT[1] !== 1'bz) && SAXIGP6ARPROT[1]; // rv 0 + assign SAXIGP6ARPROT_in[2] = (SAXIGP6ARPROT[2] !== 1'bz) && SAXIGP6ARPROT[2]; // rv 0 + assign SAXIGP6ARQOS_in[0] = (SAXIGP6ARQOS[0] !== 1'bz) && SAXIGP6ARQOS[0]; // rv 0 + assign SAXIGP6ARQOS_in[1] = (SAXIGP6ARQOS[1] !== 1'bz) && SAXIGP6ARQOS[1]; // rv 0 + assign SAXIGP6ARQOS_in[2] = (SAXIGP6ARQOS[2] !== 1'bz) && SAXIGP6ARQOS[2]; // rv 0 + assign SAXIGP6ARQOS_in[3] = (SAXIGP6ARQOS[3] !== 1'bz) && SAXIGP6ARQOS[3]; // rv 0 + assign SAXIGP6ARSIZE_in[0] = (SAXIGP6ARSIZE[0] !== 1'bz) && SAXIGP6ARSIZE[0]; // rv 0 + assign SAXIGP6ARSIZE_in[1] = (SAXIGP6ARSIZE[1] !== 1'bz) && SAXIGP6ARSIZE[1]; // rv 0 + assign SAXIGP6ARSIZE_in[2] = (SAXIGP6ARSIZE[2] !== 1'bz) && SAXIGP6ARSIZE[2]; // rv 0 + assign SAXIGP6ARUSER_in = (SAXIGP6ARUSER !== 1'bz) && SAXIGP6ARUSER; // rv 0 + assign SAXIGP6ARVALID_in = (SAXIGP6ARVALID !== 1'bz) && SAXIGP6ARVALID; // rv 0 + assign SAXIGP6AWADDR_in[0] = (SAXIGP6AWADDR[0] !== 1'bz) && SAXIGP6AWADDR[0]; // rv 0 + assign SAXIGP6AWADDR_in[10] = (SAXIGP6AWADDR[10] !== 1'bz) && SAXIGP6AWADDR[10]; // rv 0 + assign SAXIGP6AWADDR_in[11] = (SAXIGP6AWADDR[11] !== 1'bz) && SAXIGP6AWADDR[11]; // rv 0 + assign SAXIGP6AWADDR_in[12] = (SAXIGP6AWADDR[12] !== 1'bz) && SAXIGP6AWADDR[12]; // rv 0 + assign SAXIGP6AWADDR_in[13] = (SAXIGP6AWADDR[13] !== 1'bz) && SAXIGP6AWADDR[13]; // rv 0 + assign SAXIGP6AWADDR_in[14] = (SAXIGP6AWADDR[14] !== 1'bz) && SAXIGP6AWADDR[14]; // rv 0 + assign SAXIGP6AWADDR_in[15] = (SAXIGP6AWADDR[15] !== 1'bz) && SAXIGP6AWADDR[15]; // rv 0 + assign SAXIGP6AWADDR_in[16] = (SAXIGP6AWADDR[16] !== 1'bz) && SAXIGP6AWADDR[16]; // rv 0 + assign SAXIGP6AWADDR_in[17] = (SAXIGP6AWADDR[17] !== 1'bz) && SAXIGP6AWADDR[17]; // rv 0 + assign SAXIGP6AWADDR_in[18] = (SAXIGP6AWADDR[18] !== 1'bz) && SAXIGP6AWADDR[18]; // rv 0 + assign SAXIGP6AWADDR_in[19] = (SAXIGP6AWADDR[19] !== 1'bz) && SAXIGP6AWADDR[19]; // rv 0 + assign SAXIGP6AWADDR_in[1] = (SAXIGP6AWADDR[1] !== 1'bz) && SAXIGP6AWADDR[1]; // rv 0 + assign SAXIGP6AWADDR_in[20] = (SAXIGP6AWADDR[20] !== 1'bz) && SAXIGP6AWADDR[20]; // rv 0 + assign SAXIGP6AWADDR_in[21] = (SAXIGP6AWADDR[21] !== 1'bz) && SAXIGP6AWADDR[21]; // rv 0 + assign SAXIGP6AWADDR_in[22] = (SAXIGP6AWADDR[22] !== 1'bz) && SAXIGP6AWADDR[22]; // rv 0 + assign SAXIGP6AWADDR_in[23] = (SAXIGP6AWADDR[23] !== 1'bz) && SAXIGP6AWADDR[23]; // rv 0 + assign SAXIGP6AWADDR_in[24] = (SAXIGP6AWADDR[24] !== 1'bz) && SAXIGP6AWADDR[24]; // rv 0 + assign SAXIGP6AWADDR_in[25] = (SAXIGP6AWADDR[25] !== 1'bz) && SAXIGP6AWADDR[25]; // rv 0 + assign SAXIGP6AWADDR_in[26] = (SAXIGP6AWADDR[26] !== 1'bz) && SAXIGP6AWADDR[26]; // rv 0 + assign SAXIGP6AWADDR_in[27] = (SAXIGP6AWADDR[27] !== 1'bz) && SAXIGP6AWADDR[27]; // rv 0 + assign SAXIGP6AWADDR_in[28] = (SAXIGP6AWADDR[28] !== 1'bz) && SAXIGP6AWADDR[28]; // rv 0 + assign SAXIGP6AWADDR_in[29] = (SAXIGP6AWADDR[29] !== 1'bz) && SAXIGP6AWADDR[29]; // rv 0 + assign SAXIGP6AWADDR_in[2] = (SAXIGP6AWADDR[2] !== 1'bz) && SAXIGP6AWADDR[2]; // rv 0 + assign SAXIGP6AWADDR_in[30] = (SAXIGP6AWADDR[30] !== 1'bz) && SAXIGP6AWADDR[30]; // rv 0 + assign SAXIGP6AWADDR_in[31] = (SAXIGP6AWADDR[31] !== 1'bz) && SAXIGP6AWADDR[31]; // rv 0 + assign SAXIGP6AWADDR_in[32] = (SAXIGP6AWADDR[32] !== 1'bz) && SAXIGP6AWADDR[32]; // rv 0 + assign SAXIGP6AWADDR_in[33] = (SAXIGP6AWADDR[33] !== 1'bz) && SAXIGP6AWADDR[33]; // rv 0 + assign SAXIGP6AWADDR_in[34] = (SAXIGP6AWADDR[34] !== 1'bz) && SAXIGP6AWADDR[34]; // rv 0 + assign SAXIGP6AWADDR_in[35] = (SAXIGP6AWADDR[35] !== 1'bz) && SAXIGP6AWADDR[35]; // rv 0 + assign SAXIGP6AWADDR_in[36] = (SAXIGP6AWADDR[36] !== 1'bz) && SAXIGP6AWADDR[36]; // rv 0 + assign SAXIGP6AWADDR_in[37] = (SAXIGP6AWADDR[37] !== 1'bz) && SAXIGP6AWADDR[37]; // rv 0 + assign SAXIGP6AWADDR_in[38] = (SAXIGP6AWADDR[38] !== 1'bz) && SAXIGP6AWADDR[38]; // rv 0 + assign SAXIGP6AWADDR_in[39] = (SAXIGP6AWADDR[39] !== 1'bz) && SAXIGP6AWADDR[39]; // rv 0 + assign SAXIGP6AWADDR_in[3] = (SAXIGP6AWADDR[3] !== 1'bz) && SAXIGP6AWADDR[3]; // rv 0 + assign SAXIGP6AWADDR_in[40] = (SAXIGP6AWADDR[40] !== 1'bz) && SAXIGP6AWADDR[40]; // rv 0 + assign SAXIGP6AWADDR_in[41] = (SAXIGP6AWADDR[41] !== 1'bz) && SAXIGP6AWADDR[41]; // rv 0 + assign SAXIGP6AWADDR_in[42] = (SAXIGP6AWADDR[42] !== 1'bz) && SAXIGP6AWADDR[42]; // rv 0 + assign SAXIGP6AWADDR_in[43] = (SAXIGP6AWADDR[43] !== 1'bz) && SAXIGP6AWADDR[43]; // rv 0 + assign SAXIGP6AWADDR_in[44] = (SAXIGP6AWADDR[44] !== 1'bz) && SAXIGP6AWADDR[44]; // rv 0 + assign SAXIGP6AWADDR_in[45] = (SAXIGP6AWADDR[45] !== 1'bz) && SAXIGP6AWADDR[45]; // rv 0 + assign SAXIGP6AWADDR_in[46] = (SAXIGP6AWADDR[46] !== 1'bz) && SAXIGP6AWADDR[46]; // rv 0 + assign SAXIGP6AWADDR_in[47] = (SAXIGP6AWADDR[47] !== 1'bz) && SAXIGP6AWADDR[47]; // rv 0 + assign SAXIGP6AWADDR_in[48] = (SAXIGP6AWADDR[48] !== 1'bz) && SAXIGP6AWADDR[48]; // rv 0 + assign SAXIGP6AWADDR_in[4] = (SAXIGP6AWADDR[4] !== 1'bz) && SAXIGP6AWADDR[4]; // rv 0 + assign SAXIGP6AWADDR_in[5] = (SAXIGP6AWADDR[5] !== 1'bz) && SAXIGP6AWADDR[5]; // rv 0 + assign SAXIGP6AWADDR_in[6] = (SAXIGP6AWADDR[6] !== 1'bz) && SAXIGP6AWADDR[6]; // rv 0 + assign SAXIGP6AWADDR_in[7] = (SAXIGP6AWADDR[7] !== 1'bz) && SAXIGP6AWADDR[7]; // rv 0 + assign SAXIGP6AWADDR_in[8] = (SAXIGP6AWADDR[8] !== 1'bz) && SAXIGP6AWADDR[8]; // rv 0 + assign SAXIGP6AWADDR_in[9] = (SAXIGP6AWADDR[9] !== 1'bz) && SAXIGP6AWADDR[9]; // rv 0 + assign SAXIGP6AWBURST_in[0] = (SAXIGP6AWBURST[0] !== 1'bz) && SAXIGP6AWBURST[0]; // rv 0 + assign SAXIGP6AWBURST_in[1] = (SAXIGP6AWBURST[1] !== 1'bz) && SAXIGP6AWBURST[1]; // rv 0 + assign SAXIGP6AWCACHE_in[0] = (SAXIGP6AWCACHE[0] !== 1'bz) && SAXIGP6AWCACHE[0]; // rv 0 + assign SAXIGP6AWCACHE_in[1] = (SAXIGP6AWCACHE[1] !== 1'bz) && SAXIGP6AWCACHE[1]; // rv 0 + assign SAXIGP6AWCACHE_in[2] = (SAXIGP6AWCACHE[2] !== 1'bz) && SAXIGP6AWCACHE[2]; // rv 0 + assign SAXIGP6AWCACHE_in[3] = (SAXIGP6AWCACHE[3] !== 1'bz) && SAXIGP6AWCACHE[3]; // rv 0 + assign SAXIGP6AWID_in[0] = (SAXIGP6AWID[0] !== 1'bz) && SAXIGP6AWID[0]; // rv 0 + assign SAXIGP6AWID_in[1] = (SAXIGP6AWID[1] !== 1'bz) && SAXIGP6AWID[1]; // rv 0 + assign SAXIGP6AWID_in[2] = (SAXIGP6AWID[2] !== 1'bz) && SAXIGP6AWID[2]; // rv 0 + assign SAXIGP6AWID_in[3] = (SAXIGP6AWID[3] !== 1'bz) && SAXIGP6AWID[3]; // rv 0 + assign SAXIGP6AWID_in[4] = (SAXIGP6AWID[4] !== 1'bz) && SAXIGP6AWID[4]; // rv 0 + assign SAXIGP6AWID_in[5] = (SAXIGP6AWID[5] !== 1'bz) && SAXIGP6AWID[5]; // rv 0 + assign SAXIGP6AWLEN_in[0] = (SAXIGP6AWLEN[0] !== 1'bz) && SAXIGP6AWLEN[0]; // rv 0 + assign SAXIGP6AWLEN_in[1] = (SAXIGP6AWLEN[1] !== 1'bz) && SAXIGP6AWLEN[1]; // rv 0 + assign SAXIGP6AWLEN_in[2] = (SAXIGP6AWLEN[2] !== 1'bz) && SAXIGP6AWLEN[2]; // rv 0 + assign SAXIGP6AWLEN_in[3] = (SAXIGP6AWLEN[3] !== 1'bz) && SAXIGP6AWLEN[3]; // rv 0 + assign SAXIGP6AWLEN_in[4] = (SAXIGP6AWLEN[4] !== 1'bz) && SAXIGP6AWLEN[4]; // rv 0 + assign SAXIGP6AWLEN_in[5] = (SAXIGP6AWLEN[5] !== 1'bz) && SAXIGP6AWLEN[5]; // rv 0 + assign SAXIGP6AWLEN_in[6] = (SAXIGP6AWLEN[6] !== 1'bz) && SAXIGP6AWLEN[6]; // rv 0 + assign SAXIGP6AWLEN_in[7] = (SAXIGP6AWLEN[7] !== 1'bz) && SAXIGP6AWLEN[7]; // rv 0 + assign SAXIGP6AWLOCK_in = (SAXIGP6AWLOCK !== 1'bz) && SAXIGP6AWLOCK; // rv 0 + assign SAXIGP6AWPROT_in[0] = (SAXIGP6AWPROT[0] !== 1'bz) && SAXIGP6AWPROT[0]; // rv 0 + assign SAXIGP6AWPROT_in[1] = (SAXIGP6AWPROT[1] !== 1'bz) && SAXIGP6AWPROT[1]; // rv 0 + assign SAXIGP6AWPROT_in[2] = (SAXIGP6AWPROT[2] !== 1'bz) && SAXIGP6AWPROT[2]; // rv 0 + assign SAXIGP6AWQOS_in[0] = (SAXIGP6AWQOS[0] !== 1'bz) && SAXIGP6AWQOS[0]; // rv 0 + assign SAXIGP6AWQOS_in[1] = (SAXIGP6AWQOS[1] !== 1'bz) && SAXIGP6AWQOS[1]; // rv 0 + assign SAXIGP6AWQOS_in[2] = (SAXIGP6AWQOS[2] !== 1'bz) && SAXIGP6AWQOS[2]; // rv 0 + assign SAXIGP6AWQOS_in[3] = (SAXIGP6AWQOS[3] !== 1'bz) && SAXIGP6AWQOS[3]; // rv 0 + assign SAXIGP6AWSIZE_in[0] = (SAXIGP6AWSIZE[0] !== 1'bz) && SAXIGP6AWSIZE[0]; // rv 0 + assign SAXIGP6AWSIZE_in[1] = (SAXIGP6AWSIZE[1] !== 1'bz) && SAXIGP6AWSIZE[1]; // rv 0 + assign SAXIGP6AWSIZE_in[2] = (SAXIGP6AWSIZE[2] !== 1'bz) && SAXIGP6AWSIZE[2]; // rv 0 + assign SAXIGP6AWUSER_in = (SAXIGP6AWUSER !== 1'bz) && SAXIGP6AWUSER; // rv 0 + assign SAXIGP6AWVALID_in = (SAXIGP6AWVALID !== 1'bz) && SAXIGP6AWVALID; // rv 0 + assign SAXIGP6BREADY_in = (SAXIGP6BREADY !== 1'bz) && SAXIGP6BREADY; // rv 0 + assign SAXIGP6RCLK_in = (SAXIGP6RCLK !== 1'bz) && SAXIGP6RCLK; // rv 0 + assign SAXIGP6RREADY_in = (SAXIGP6RREADY !== 1'bz) && SAXIGP6RREADY; // rv 0 + assign SAXIGP6WCLK_in = (SAXIGP6WCLK !== 1'bz) && SAXIGP6WCLK; // rv 0 + assign SAXIGP6WDATA_in[0] = (SAXIGP6WDATA[0] !== 1'bz) && SAXIGP6WDATA[0]; // rv 0 + assign SAXIGP6WDATA_in[100] = (SAXIGP6WDATA[100] !== 1'bz) && SAXIGP6WDATA[100]; // rv 0 + assign SAXIGP6WDATA_in[101] = (SAXIGP6WDATA[101] !== 1'bz) && SAXIGP6WDATA[101]; // rv 0 + assign SAXIGP6WDATA_in[102] = (SAXIGP6WDATA[102] !== 1'bz) && SAXIGP6WDATA[102]; // rv 0 + assign SAXIGP6WDATA_in[103] = (SAXIGP6WDATA[103] !== 1'bz) && SAXIGP6WDATA[103]; // rv 0 + assign SAXIGP6WDATA_in[104] = (SAXIGP6WDATA[104] !== 1'bz) && SAXIGP6WDATA[104]; // rv 0 + assign SAXIGP6WDATA_in[105] = (SAXIGP6WDATA[105] !== 1'bz) && SAXIGP6WDATA[105]; // rv 0 + assign SAXIGP6WDATA_in[106] = (SAXIGP6WDATA[106] !== 1'bz) && SAXIGP6WDATA[106]; // rv 0 + assign SAXIGP6WDATA_in[107] = (SAXIGP6WDATA[107] !== 1'bz) && SAXIGP6WDATA[107]; // rv 0 + assign SAXIGP6WDATA_in[108] = (SAXIGP6WDATA[108] !== 1'bz) && SAXIGP6WDATA[108]; // rv 0 + assign SAXIGP6WDATA_in[109] = (SAXIGP6WDATA[109] !== 1'bz) && SAXIGP6WDATA[109]; // rv 0 + assign SAXIGP6WDATA_in[10] = (SAXIGP6WDATA[10] !== 1'bz) && SAXIGP6WDATA[10]; // rv 0 + assign SAXIGP6WDATA_in[110] = (SAXIGP6WDATA[110] !== 1'bz) && SAXIGP6WDATA[110]; // rv 0 + assign SAXIGP6WDATA_in[111] = (SAXIGP6WDATA[111] !== 1'bz) && SAXIGP6WDATA[111]; // rv 0 + assign SAXIGP6WDATA_in[112] = (SAXIGP6WDATA[112] !== 1'bz) && SAXIGP6WDATA[112]; // rv 0 + assign SAXIGP6WDATA_in[113] = (SAXIGP6WDATA[113] !== 1'bz) && SAXIGP6WDATA[113]; // rv 0 + assign SAXIGP6WDATA_in[114] = (SAXIGP6WDATA[114] !== 1'bz) && SAXIGP6WDATA[114]; // rv 0 + assign SAXIGP6WDATA_in[115] = (SAXIGP6WDATA[115] !== 1'bz) && SAXIGP6WDATA[115]; // rv 0 + assign SAXIGP6WDATA_in[116] = (SAXIGP6WDATA[116] !== 1'bz) && SAXIGP6WDATA[116]; // rv 0 + assign SAXIGP6WDATA_in[117] = (SAXIGP6WDATA[117] !== 1'bz) && SAXIGP6WDATA[117]; // rv 0 + assign SAXIGP6WDATA_in[118] = (SAXIGP6WDATA[118] !== 1'bz) && SAXIGP6WDATA[118]; // rv 0 + assign SAXIGP6WDATA_in[119] = (SAXIGP6WDATA[119] !== 1'bz) && SAXIGP6WDATA[119]; // rv 0 + assign SAXIGP6WDATA_in[11] = (SAXIGP6WDATA[11] !== 1'bz) && SAXIGP6WDATA[11]; // rv 0 + assign SAXIGP6WDATA_in[120] = (SAXIGP6WDATA[120] !== 1'bz) && SAXIGP6WDATA[120]; // rv 0 + assign SAXIGP6WDATA_in[121] = (SAXIGP6WDATA[121] !== 1'bz) && SAXIGP6WDATA[121]; // rv 0 + assign SAXIGP6WDATA_in[122] = (SAXIGP6WDATA[122] !== 1'bz) && SAXIGP6WDATA[122]; // rv 0 + assign SAXIGP6WDATA_in[123] = (SAXIGP6WDATA[123] !== 1'bz) && SAXIGP6WDATA[123]; // rv 0 + assign SAXIGP6WDATA_in[124] = (SAXIGP6WDATA[124] !== 1'bz) && SAXIGP6WDATA[124]; // rv 0 + assign SAXIGP6WDATA_in[125] = (SAXIGP6WDATA[125] !== 1'bz) && SAXIGP6WDATA[125]; // rv 0 + assign SAXIGP6WDATA_in[126] = (SAXIGP6WDATA[126] !== 1'bz) && SAXIGP6WDATA[126]; // rv 0 + assign SAXIGP6WDATA_in[127] = (SAXIGP6WDATA[127] !== 1'bz) && SAXIGP6WDATA[127]; // rv 0 + assign SAXIGP6WDATA_in[12] = (SAXIGP6WDATA[12] !== 1'bz) && SAXIGP6WDATA[12]; // rv 0 + assign SAXIGP6WDATA_in[13] = (SAXIGP6WDATA[13] !== 1'bz) && SAXIGP6WDATA[13]; // rv 0 + assign SAXIGP6WDATA_in[14] = (SAXIGP6WDATA[14] !== 1'bz) && SAXIGP6WDATA[14]; // rv 0 + assign SAXIGP6WDATA_in[15] = (SAXIGP6WDATA[15] !== 1'bz) && SAXIGP6WDATA[15]; // rv 0 + assign SAXIGP6WDATA_in[16] = (SAXIGP6WDATA[16] !== 1'bz) && SAXIGP6WDATA[16]; // rv 0 + assign SAXIGP6WDATA_in[17] = (SAXIGP6WDATA[17] !== 1'bz) && SAXIGP6WDATA[17]; // rv 0 + assign SAXIGP6WDATA_in[18] = (SAXIGP6WDATA[18] !== 1'bz) && SAXIGP6WDATA[18]; // rv 0 + assign SAXIGP6WDATA_in[19] = (SAXIGP6WDATA[19] !== 1'bz) && SAXIGP6WDATA[19]; // rv 0 + assign SAXIGP6WDATA_in[1] = (SAXIGP6WDATA[1] !== 1'bz) && SAXIGP6WDATA[1]; // rv 0 + assign SAXIGP6WDATA_in[20] = (SAXIGP6WDATA[20] !== 1'bz) && SAXIGP6WDATA[20]; // rv 0 + assign SAXIGP6WDATA_in[21] = (SAXIGP6WDATA[21] !== 1'bz) && SAXIGP6WDATA[21]; // rv 0 + assign SAXIGP6WDATA_in[22] = (SAXIGP6WDATA[22] !== 1'bz) && SAXIGP6WDATA[22]; // rv 0 + assign SAXIGP6WDATA_in[23] = (SAXIGP6WDATA[23] !== 1'bz) && SAXIGP6WDATA[23]; // rv 0 + assign SAXIGP6WDATA_in[24] = (SAXIGP6WDATA[24] !== 1'bz) && SAXIGP6WDATA[24]; // rv 0 + assign SAXIGP6WDATA_in[25] = (SAXIGP6WDATA[25] !== 1'bz) && SAXIGP6WDATA[25]; // rv 0 + assign SAXIGP6WDATA_in[26] = (SAXIGP6WDATA[26] !== 1'bz) && SAXIGP6WDATA[26]; // rv 0 + assign SAXIGP6WDATA_in[27] = (SAXIGP6WDATA[27] !== 1'bz) && SAXIGP6WDATA[27]; // rv 0 + assign SAXIGP6WDATA_in[28] = (SAXIGP6WDATA[28] !== 1'bz) && SAXIGP6WDATA[28]; // rv 0 + assign SAXIGP6WDATA_in[29] = (SAXIGP6WDATA[29] !== 1'bz) && SAXIGP6WDATA[29]; // rv 0 + assign SAXIGP6WDATA_in[2] = (SAXIGP6WDATA[2] !== 1'bz) && SAXIGP6WDATA[2]; // rv 0 + assign SAXIGP6WDATA_in[30] = (SAXIGP6WDATA[30] !== 1'bz) && SAXIGP6WDATA[30]; // rv 0 + assign SAXIGP6WDATA_in[31] = (SAXIGP6WDATA[31] !== 1'bz) && SAXIGP6WDATA[31]; // rv 0 + assign SAXIGP6WDATA_in[32] = (SAXIGP6WDATA[32] !== 1'bz) && SAXIGP6WDATA[32]; // rv 0 + assign SAXIGP6WDATA_in[33] = (SAXIGP6WDATA[33] !== 1'bz) && SAXIGP6WDATA[33]; // rv 0 + assign SAXIGP6WDATA_in[34] = (SAXIGP6WDATA[34] !== 1'bz) && SAXIGP6WDATA[34]; // rv 0 + assign SAXIGP6WDATA_in[35] = (SAXIGP6WDATA[35] !== 1'bz) && SAXIGP6WDATA[35]; // rv 0 + assign SAXIGP6WDATA_in[36] = (SAXIGP6WDATA[36] !== 1'bz) && SAXIGP6WDATA[36]; // rv 0 + assign SAXIGP6WDATA_in[37] = (SAXIGP6WDATA[37] !== 1'bz) && SAXIGP6WDATA[37]; // rv 0 + assign SAXIGP6WDATA_in[38] = (SAXIGP6WDATA[38] !== 1'bz) && SAXIGP6WDATA[38]; // rv 0 + assign SAXIGP6WDATA_in[39] = (SAXIGP6WDATA[39] !== 1'bz) && SAXIGP6WDATA[39]; // rv 0 + assign SAXIGP6WDATA_in[3] = (SAXIGP6WDATA[3] !== 1'bz) && SAXIGP6WDATA[3]; // rv 0 + assign SAXIGP6WDATA_in[40] = (SAXIGP6WDATA[40] !== 1'bz) && SAXIGP6WDATA[40]; // rv 0 + assign SAXIGP6WDATA_in[41] = (SAXIGP6WDATA[41] !== 1'bz) && SAXIGP6WDATA[41]; // rv 0 + assign SAXIGP6WDATA_in[42] = (SAXIGP6WDATA[42] !== 1'bz) && SAXIGP6WDATA[42]; // rv 0 + assign SAXIGP6WDATA_in[43] = (SAXIGP6WDATA[43] !== 1'bz) && SAXIGP6WDATA[43]; // rv 0 + assign SAXIGP6WDATA_in[44] = (SAXIGP6WDATA[44] !== 1'bz) && SAXIGP6WDATA[44]; // rv 0 + assign SAXIGP6WDATA_in[45] = (SAXIGP6WDATA[45] !== 1'bz) && SAXIGP6WDATA[45]; // rv 0 + assign SAXIGP6WDATA_in[46] = (SAXIGP6WDATA[46] !== 1'bz) && SAXIGP6WDATA[46]; // rv 0 + assign SAXIGP6WDATA_in[47] = (SAXIGP6WDATA[47] !== 1'bz) && SAXIGP6WDATA[47]; // rv 0 + assign SAXIGP6WDATA_in[48] = (SAXIGP6WDATA[48] !== 1'bz) && SAXIGP6WDATA[48]; // rv 0 + assign SAXIGP6WDATA_in[49] = (SAXIGP6WDATA[49] !== 1'bz) && SAXIGP6WDATA[49]; // rv 0 + assign SAXIGP6WDATA_in[4] = (SAXIGP6WDATA[4] !== 1'bz) && SAXIGP6WDATA[4]; // rv 0 + assign SAXIGP6WDATA_in[50] = (SAXIGP6WDATA[50] !== 1'bz) && SAXIGP6WDATA[50]; // rv 0 + assign SAXIGP6WDATA_in[51] = (SAXIGP6WDATA[51] !== 1'bz) && SAXIGP6WDATA[51]; // rv 0 + assign SAXIGP6WDATA_in[52] = (SAXIGP6WDATA[52] !== 1'bz) && SAXIGP6WDATA[52]; // rv 0 + assign SAXIGP6WDATA_in[53] = (SAXIGP6WDATA[53] !== 1'bz) && SAXIGP6WDATA[53]; // rv 0 + assign SAXIGP6WDATA_in[54] = (SAXIGP6WDATA[54] !== 1'bz) && SAXIGP6WDATA[54]; // rv 0 + assign SAXIGP6WDATA_in[55] = (SAXIGP6WDATA[55] !== 1'bz) && SAXIGP6WDATA[55]; // rv 0 + assign SAXIGP6WDATA_in[56] = (SAXIGP6WDATA[56] !== 1'bz) && SAXIGP6WDATA[56]; // rv 0 + assign SAXIGP6WDATA_in[57] = (SAXIGP6WDATA[57] !== 1'bz) && SAXIGP6WDATA[57]; // rv 0 + assign SAXIGP6WDATA_in[58] = (SAXIGP6WDATA[58] !== 1'bz) && SAXIGP6WDATA[58]; // rv 0 + assign SAXIGP6WDATA_in[59] = (SAXIGP6WDATA[59] !== 1'bz) && SAXIGP6WDATA[59]; // rv 0 + assign SAXIGP6WDATA_in[5] = (SAXIGP6WDATA[5] !== 1'bz) && SAXIGP6WDATA[5]; // rv 0 + assign SAXIGP6WDATA_in[60] = (SAXIGP6WDATA[60] !== 1'bz) && SAXIGP6WDATA[60]; // rv 0 + assign SAXIGP6WDATA_in[61] = (SAXIGP6WDATA[61] !== 1'bz) && SAXIGP6WDATA[61]; // rv 0 + assign SAXIGP6WDATA_in[62] = (SAXIGP6WDATA[62] !== 1'bz) && SAXIGP6WDATA[62]; // rv 0 + assign SAXIGP6WDATA_in[63] = (SAXIGP6WDATA[63] !== 1'bz) && SAXIGP6WDATA[63]; // rv 0 + assign SAXIGP6WDATA_in[64] = (SAXIGP6WDATA[64] !== 1'bz) && SAXIGP6WDATA[64]; // rv 0 + assign SAXIGP6WDATA_in[65] = (SAXIGP6WDATA[65] !== 1'bz) && SAXIGP6WDATA[65]; // rv 0 + assign SAXIGP6WDATA_in[66] = (SAXIGP6WDATA[66] !== 1'bz) && SAXIGP6WDATA[66]; // rv 0 + assign SAXIGP6WDATA_in[67] = (SAXIGP6WDATA[67] !== 1'bz) && SAXIGP6WDATA[67]; // rv 0 + assign SAXIGP6WDATA_in[68] = (SAXIGP6WDATA[68] !== 1'bz) && SAXIGP6WDATA[68]; // rv 0 + assign SAXIGP6WDATA_in[69] = (SAXIGP6WDATA[69] !== 1'bz) && SAXIGP6WDATA[69]; // rv 0 + assign SAXIGP6WDATA_in[6] = (SAXIGP6WDATA[6] !== 1'bz) && SAXIGP6WDATA[6]; // rv 0 + assign SAXIGP6WDATA_in[70] = (SAXIGP6WDATA[70] !== 1'bz) && SAXIGP6WDATA[70]; // rv 0 + assign SAXIGP6WDATA_in[71] = (SAXIGP6WDATA[71] !== 1'bz) && SAXIGP6WDATA[71]; // rv 0 + assign SAXIGP6WDATA_in[72] = (SAXIGP6WDATA[72] !== 1'bz) && SAXIGP6WDATA[72]; // rv 0 + assign SAXIGP6WDATA_in[73] = (SAXIGP6WDATA[73] !== 1'bz) && SAXIGP6WDATA[73]; // rv 0 + assign SAXIGP6WDATA_in[74] = (SAXIGP6WDATA[74] !== 1'bz) && SAXIGP6WDATA[74]; // rv 0 + assign SAXIGP6WDATA_in[75] = (SAXIGP6WDATA[75] !== 1'bz) && SAXIGP6WDATA[75]; // rv 0 + assign SAXIGP6WDATA_in[76] = (SAXIGP6WDATA[76] !== 1'bz) && SAXIGP6WDATA[76]; // rv 0 + assign SAXIGP6WDATA_in[77] = (SAXIGP6WDATA[77] !== 1'bz) && SAXIGP6WDATA[77]; // rv 0 + assign SAXIGP6WDATA_in[78] = (SAXIGP6WDATA[78] !== 1'bz) && SAXIGP6WDATA[78]; // rv 0 + assign SAXIGP6WDATA_in[79] = (SAXIGP6WDATA[79] !== 1'bz) && SAXIGP6WDATA[79]; // rv 0 + assign SAXIGP6WDATA_in[7] = (SAXIGP6WDATA[7] !== 1'bz) && SAXIGP6WDATA[7]; // rv 0 + assign SAXIGP6WDATA_in[80] = (SAXIGP6WDATA[80] !== 1'bz) && SAXIGP6WDATA[80]; // rv 0 + assign SAXIGP6WDATA_in[81] = (SAXIGP6WDATA[81] !== 1'bz) && SAXIGP6WDATA[81]; // rv 0 + assign SAXIGP6WDATA_in[82] = (SAXIGP6WDATA[82] !== 1'bz) && SAXIGP6WDATA[82]; // rv 0 + assign SAXIGP6WDATA_in[83] = (SAXIGP6WDATA[83] !== 1'bz) && SAXIGP6WDATA[83]; // rv 0 + assign SAXIGP6WDATA_in[84] = (SAXIGP6WDATA[84] !== 1'bz) && SAXIGP6WDATA[84]; // rv 0 + assign SAXIGP6WDATA_in[85] = (SAXIGP6WDATA[85] !== 1'bz) && SAXIGP6WDATA[85]; // rv 0 + assign SAXIGP6WDATA_in[86] = (SAXIGP6WDATA[86] !== 1'bz) && SAXIGP6WDATA[86]; // rv 0 + assign SAXIGP6WDATA_in[87] = (SAXIGP6WDATA[87] !== 1'bz) && SAXIGP6WDATA[87]; // rv 0 + assign SAXIGP6WDATA_in[88] = (SAXIGP6WDATA[88] !== 1'bz) && SAXIGP6WDATA[88]; // rv 0 + assign SAXIGP6WDATA_in[89] = (SAXIGP6WDATA[89] !== 1'bz) && SAXIGP6WDATA[89]; // rv 0 + assign SAXIGP6WDATA_in[8] = (SAXIGP6WDATA[8] !== 1'bz) && SAXIGP6WDATA[8]; // rv 0 + assign SAXIGP6WDATA_in[90] = (SAXIGP6WDATA[90] !== 1'bz) && SAXIGP6WDATA[90]; // rv 0 + assign SAXIGP6WDATA_in[91] = (SAXIGP6WDATA[91] !== 1'bz) && SAXIGP6WDATA[91]; // rv 0 + assign SAXIGP6WDATA_in[92] = (SAXIGP6WDATA[92] !== 1'bz) && SAXIGP6WDATA[92]; // rv 0 + assign SAXIGP6WDATA_in[93] = (SAXIGP6WDATA[93] !== 1'bz) && SAXIGP6WDATA[93]; // rv 0 + assign SAXIGP6WDATA_in[94] = (SAXIGP6WDATA[94] !== 1'bz) && SAXIGP6WDATA[94]; // rv 0 + assign SAXIGP6WDATA_in[95] = (SAXIGP6WDATA[95] !== 1'bz) && SAXIGP6WDATA[95]; // rv 0 + assign SAXIGP6WDATA_in[96] = (SAXIGP6WDATA[96] !== 1'bz) && SAXIGP6WDATA[96]; // rv 0 + assign SAXIGP6WDATA_in[97] = (SAXIGP6WDATA[97] !== 1'bz) && SAXIGP6WDATA[97]; // rv 0 + assign SAXIGP6WDATA_in[98] = (SAXIGP6WDATA[98] !== 1'bz) && SAXIGP6WDATA[98]; // rv 0 + assign SAXIGP6WDATA_in[99] = (SAXIGP6WDATA[99] !== 1'bz) && SAXIGP6WDATA[99]; // rv 0 + assign SAXIGP6WDATA_in[9] = (SAXIGP6WDATA[9] !== 1'bz) && SAXIGP6WDATA[9]; // rv 0 + assign SAXIGP6WLAST_in = (SAXIGP6WLAST !== 1'bz) && SAXIGP6WLAST; // rv 0 + assign SAXIGP6WSTRB_in[0] = (SAXIGP6WSTRB[0] !== 1'bz) && SAXIGP6WSTRB[0]; // rv 0 + assign SAXIGP6WSTRB_in[10] = (SAXIGP6WSTRB[10] !== 1'bz) && SAXIGP6WSTRB[10]; // rv 0 + assign SAXIGP6WSTRB_in[11] = (SAXIGP6WSTRB[11] !== 1'bz) && SAXIGP6WSTRB[11]; // rv 0 + assign SAXIGP6WSTRB_in[12] = (SAXIGP6WSTRB[12] !== 1'bz) && SAXIGP6WSTRB[12]; // rv 0 + assign SAXIGP6WSTRB_in[13] = (SAXIGP6WSTRB[13] !== 1'bz) && SAXIGP6WSTRB[13]; // rv 0 + assign SAXIGP6WSTRB_in[14] = (SAXIGP6WSTRB[14] !== 1'bz) && SAXIGP6WSTRB[14]; // rv 0 + assign SAXIGP6WSTRB_in[15] = (SAXIGP6WSTRB[15] !== 1'bz) && SAXIGP6WSTRB[15]; // rv 0 + assign SAXIGP6WSTRB_in[1] = (SAXIGP6WSTRB[1] !== 1'bz) && SAXIGP6WSTRB[1]; // rv 0 + assign SAXIGP6WSTRB_in[2] = (SAXIGP6WSTRB[2] !== 1'bz) && SAXIGP6WSTRB[2]; // rv 0 + assign SAXIGP6WSTRB_in[3] = (SAXIGP6WSTRB[3] !== 1'bz) && SAXIGP6WSTRB[3]; // rv 0 + assign SAXIGP6WSTRB_in[4] = (SAXIGP6WSTRB[4] !== 1'bz) && SAXIGP6WSTRB[4]; // rv 0 + assign SAXIGP6WSTRB_in[5] = (SAXIGP6WSTRB[5] !== 1'bz) && SAXIGP6WSTRB[5]; // rv 0 + assign SAXIGP6WSTRB_in[6] = (SAXIGP6WSTRB[6] !== 1'bz) && SAXIGP6WSTRB[6]; // rv 0 + assign SAXIGP6WSTRB_in[7] = (SAXIGP6WSTRB[7] !== 1'bz) && SAXIGP6WSTRB[7]; // rv 0 + assign SAXIGP6WSTRB_in[8] = (SAXIGP6WSTRB[8] !== 1'bz) && SAXIGP6WSTRB[8]; // rv 0 + assign SAXIGP6WSTRB_in[9] = (SAXIGP6WSTRB[9] !== 1'bz) && SAXIGP6WSTRB[9]; // rv 0 + assign SAXIGP6WVALID_in = (SAXIGP6WVALID !== 1'bz) && SAXIGP6WVALID; // rv 0 +`endif + assign AIBPMUAFIFMFPDACK_in = (AIBPMUAFIFMFPDACK !== 1'bz) && AIBPMUAFIFMFPDACK; // rv 0 + assign AIBPMUAFIFMLPDACK_in = (AIBPMUAFIFMLPDACK !== 1'bz) && AIBPMUAFIFMLPDACK; // rv 0 + assign DPAUXDATAIN_in = (DPAUXDATAIN !== 1'bz) && DPAUXDATAIN; // rv 0 + assign DPEXTERNALCUSTOMEVENT1_in = (DPEXTERNALCUSTOMEVENT1 !== 1'bz) && DPEXTERNALCUSTOMEVENT1; // rv 0 + assign DPEXTERNALCUSTOMEVENT2_in = (DPEXTERNALCUSTOMEVENT2 !== 1'bz) && DPEXTERNALCUSTOMEVENT2; // rv 0 + assign DPEXTERNALVSYNCEVENT_in = (DPEXTERNALVSYNCEVENT !== 1'bz) && DPEXTERNALVSYNCEVENT; // rv 0 + assign DPHOTPLUGDETECT_in = (DPHOTPLUGDETECT !== 1'bz) && DPHOTPLUGDETECT; // rv 0 + assign EMIOCAN0PHYRX_in = (EMIOCAN0PHYRX !== 1'bz) && EMIOCAN0PHYRX; // rv 0 + assign EMIOCAN1PHYRX_in = (EMIOCAN1PHYRX !== 1'bz) && EMIOCAN1PHYRX; // rv 0 + assign EMIOENET0DMATXSTATUSTOG_in = (EMIOENET0DMATXSTATUSTOG !== 1'bz) && EMIOENET0DMATXSTATUSTOG; // rv 0 + assign EMIOENET0EXTINTIN_in = (EMIOENET0EXTINTIN !== 1'bz) && EMIOENET0EXTINTIN; // rv 0 + assign EMIOENET0GMIICOL_in = (EMIOENET0GMIICOL !== 1'bz) && EMIOENET0GMIICOL; // rv 0 + assign EMIOENET0GMIICRS_in = (EMIOENET0GMIICRS !== 1'bz) && EMIOENET0GMIICRS; // rv 0 + assign EMIOENET0GMIITXCLK_in = (EMIOENET0GMIITXCLK === 1'bz) || EMIOENET0GMIITXCLK; // rv 1 + assign EMIOENET0MDIOI_in = (EMIOENET0MDIOI !== 1'bz) && EMIOENET0MDIOI; // rv 0 + assign EMIOENET0RXWOVERFLOW_in = (EMIOENET0RXWOVERFLOW !== 1'bz) && EMIOENET0RXWOVERFLOW; // rv 0 + assign EMIOENET1DMATXSTATUSTOG_in = (EMIOENET1DMATXSTATUSTOG !== 1'bz) && EMIOENET1DMATXSTATUSTOG; // rv 0 + assign EMIOENET1EXTINTIN_in = (EMIOENET1EXTINTIN !== 1'bz) && EMIOENET1EXTINTIN; // rv 0 + assign EMIOENET1GMIICOL_in = (EMIOENET1GMIICOL !== 1'bz) && EMIOENET1GMIICOL; // rv 0 + assign EMIOENET1GMIICRS_in = (EMIOENET1GMIICRS !== 1'bz) && EMIOENET1GMIICRS; // rv 0 + assign EMIOENET1GMIITXCLK_in = (EMIOENET1GMIITXCLK === 1'bz) || EMIOENET1GMIITXCLK; // rv 1 + assign EMIOENET1MDIOI_in = (EMIOENET1MDIOI !== 1'bz) && EMIOENET1MDIOI; // rv 0 + assign EMIOENET1RXWOVERFLOW_in = (EMIOENET1RXWOVERFLOW !== 1'bz) && EMIOENET1RXWOVERFLOW; // rv 0 + assign EMIOENET2DMATXSTATUSTOG_in = (EMIOENET2DMATXSTATUSTOG !== 1'bz) && EMIOENET2DMATXSTATUSTOG; // rv 0 + assign EMIOENET2EXTINTIN_in = (EMIOENET2EXTINTIN !== 1'bz) && EMIOENET2EXTINTIN; // rv 0 + assign EMIOENET2GMIICOL_in = (EMIOENET2GMIICOL !== 1'bz) && EMIOENET2GMIICOL; // rv 0 + assign EMIOENET2GMIICRS_in = (EMIOENET2GMIICRS !== 1'bz) && EMIOENET2GMIICRS; // rv 0 + assign EMIOENET2GMIITXCLK_in = (EMIOENET2GMIITXCLK === 1'bz) || EMIOENET2GMIITXCLK; // rv 1 + assign EMIOENET2MDIOI_in = (EMIOENET2MDIOI !== 1'bz) && EMIOENET2MDIOI; // rv 0 + assign EMIOENET2RXWOVERFLOW_in = (EMIOENET2RXWOVERFLOW !== 1'bz) && EMIOENET2RXWOVERFLOW; // rv 0 + assign EMIOENET3DMATXSTATUSTOG_in = (EMIOENET3DMATXSTATUSTOG !== 1'bz) && EMIOENET3DMATXSTATUSTOG; // rv 0 + assign EMIOENET3EXTINTIN_in = (EMIOENET3EXTINTIN !== 1'bz) && EMIOENET3EXTINTIN; // rv 0 + assign EMIOENET3GMIICOL_in = (EMIOENET3GMIICOL !== 1'bz) && EMIOENET3GMIICOL; // rv 0 + assign EMIOENET3GMIICRS_in = (EMIOENET3GMIICRS !== 1'bz) && EMIOENET3GMIICRS; // rv 0 + assign EMIOENET3GMIITXCLK_in = (EMIOENET3GMIITXCLK === 1'bz) || EMIOENET3GMIITXCLK; // rv 1 + assign EMIOENET3MDIOI_in = (EMIOENET3MDIOI !== 1'bz) && EMIOENET3MDIOI; // rv 0 + assign EMIOENET3RXWOVERFLOW_in = (EMIOENET3RXWOVERFLOW !== 1'bz) && EMIOENET3RXWOVERFLOW; // rv 0 + assign EMIOENETTSUCLK_in = (EMIOENETTSUCLK !== 1'bz) && EMIOENETTSUCLK; // rv 0 + assign EMIOGPIOI_in[0] = (EMIOGPIOI[0] !== 1'bz) && EMIOGPIOI[0]; // rv 0 + assign EMIOGPIOI_in[10] = (EMIOGPIOI[10] !== 1'bz) && EMIOGPIOI[10]; // rv 0 + assign EMIOGPIOI_in[11] = (EMIOGPIOI[11] !== 1'bz) && EMIOGPIOI[11]; // rv 0 + assign EMIOGPIOI_in[12] = (EMIOGPIOI[12] !== 1'bz) && EMIOGPIOI[12]; // rv 0 + assign EMIOGPIOI_in[13] = (EMIOGPIOI[13] !== 1'bz) && EMIOGPIOI[13]; // rv 0 + assign EMIOGPIOI_in[14] = (EMIOGPIOI[14] !== 1'bz) && EMIOGPIOI[14]; // rv 0 + assign EMIOGPIOI_in[15] = (EMIOGPIOI[15] !== 1'bz) && EMIOGPIOI[15]; // rv 0 + assign EMIOGPIOI_in[16] = (EMIOGPIOI[16] !== 1'bz) && EMIOGPIOI[16]; // rv 0 + assign EMIOGPIOI_in[17] = (EMIOGPIOI[17] !== 1'bz) && EMIOGPIOI[17]; // rv 0 + assign EMIOGPIOI_in[18] = (EMIOGPIOI[18] !== 1'bz) && EMIOGPIOI[18]; // rv 0 + assign EMIOGPIOI_in[19] = (EMIOGPIOI[19] !== 1'bz) && EMIOGPIOI[19]; // rv 0 + assign EMIOGPIOI_in[1] = (EMIOGPIOI[1] !== 1'bz) && EMIOGPIOI[1]; // rv 0 + assign EMIOGPIOI_in[20] = (EMIOGPIOI[20] !== 1'bz) && EMIOGPIOI[20]; // rv 0 + assign EMIOGPIOI_in[21] = (EMIOGPIOI[21] !== 1'bz) && EMIOGPIOI[21]; // rv 0 + assign EMIOGPIOI_in[22] = (EMIOGPIOI[22] !== 1'bz) && EMIOGPIOI[22]; // rv 0 + assign EMIOGPIOI_in[23] = (EMIOGPIOI[23] !== 1'bz) && EMIOGPIOI[23]; // rv 0 + assign EMIOGPIOI_in[24] = (EMIOGPIOI[24] !== 1'bz) && EMIOGPIOI[24]; // rv 0 + assign EMIOGPIOI_in[25] = (EMIOGPIOI[25] !== 1'bz) && EMIOGPIOI[25]; // rv 0 + assign EMIOGPIOI_in[26] = (EMIOGPIOI[26] !== 1'bz) && EMIOGPIOI[26]; // rv 0 + assign EMIOGPIOI_in[27] = (EMIOGPIOI[27] !== 1'bz) && EMIOGPIOI[27]; // rv 0 + assign EMIOGPIOI_in[28] = (EMIOGPIOI[28] !== 1'bz) && EMIOGPIOI[28]; // rv 0 + assign EMIOGPIOI_in[29] = (EMIOGPIOI[29] !== 1'bz) && EMIOGPIOI[29]; // rv 0 + assign EMIOGPIOI_in[2] = (EMIOGPIOI[2] !== 1'bz) && EMIOGPIOI[2]; // rv 0 + assign EMIOGPIOI_in[30] = (EMIOGPIOI[30] !== 1'bz) && EMIOGPIOI[30]; // rv 0 + assign EMIOGPIOI_in[31] = (EMIOGPIOI[31] !== 1'bz) && EMIOGPIOI[31]; // rv 0 + assign EMIOGPIOI_in[32] = (EMIOGPIOI[32] !== 1'bz) && EMIOGPIOI[32]; // rv 0 + assign EMIOGPIOI_in[33] = (EMIOGPIOI[33] !== 1'bz) && EMIOGPIOI[33]; // rv 0 + assign EMIOGPIOI_in[34] = (EMIOGPIOI[34] !== 1'bz) && EMIOGPIOI[34]; // rv 0 + assign EMIOGPIOI_in[35] = (EMIOGPIOI[35] !== 1'bz) && EMIOGPIOI[35]; // rv 0 + assign EMIOGPIOI_in[36] = (EMIOGPIOI[36] !== 1'bz) && EMIOGPIOI[36]; // rv 0 + assign EMIOGPIOI_in[37] = (EMIOGPIOI[37] !== 1'bz) && EMIOGPIOI[37]; // rv 0 + assign EMIOGPIOI_in[38] = (EMIOGPIOI[38] !== 1'bz) && EMIOGPIOI[38]; // rv 0 + assign EMIOGPIOI_in[39] = (EMIOGPIOI[39] !== 1'bz) && EMIOGPIOI[39]; // rv 0 + assign EMIOGPIOI_in[3] = (EMIOGPIOI[3] !== 1'bz) && EMIOGPIOI[3]; // rv 0 + assign EMIOGPIOI_in[40] = (EMIOGPIOI[40] !== 1'bz) && EMIOGPIOI[40]; // rv 0 + assign EMIOGPIOI_in[41] = (EMIOGPIOI[41] !== 1'bz) && EMIOGPIOI[41]; // rv 0 + assign EMIOGPIOI_in[42] = (EMIOGPIOI[42] !== 1'bz) && EMIOGPIOI[42]; // rv 0 + assign EMIOGPIOI_in[43] = (EMIOGPIOI[43] !== 1'bz) && EMIOGPIOI[43]; // rv 0 + assign EMIOGPIOI_in[44] = (EMIOGPIOI[44] !== 1'bz) && EMIOGPIOI[44]; // rv 0 + assign EMIOGPIOI_in[45] = (EMIOGPIOI[45] !== 1'bz) && EMIOGPIOI[45]; // rv 0 + assign EMIOGPIOI_in[46] = (EMIOGPIOI[46] !== 1'bz) && EMIOGPIOI[46]; // rv 0 + assign EMIOGPIOI_in[47] = (EMIOGPIOI[47] !== 1'bz) && EMIOGPIOI[47]; // rv 0 + assign EMIOGPIOI_in[48] = (EMIOGPIOI[48] !== 1'bz) && EMIOGPIOI[48]; // rv 0 + assign EMIOGPIOI_in[49] = (EMIOGPIOI[49] !== 1'bz) && EMIOGPIOI[49]; // rv 0 + assign EMIOGPIOI_in[4] = (EMIOGPIOI[4] !== 1'bz) && EMIOGPIOI[4]; // rv 0 + assign EMIOGPIOI_in[50] = (EMIOGPIOI[50] !== 1'bz) && EMIOGPIOI[50]; // rv 0 + assign EMIOGPIOI_in[51] = (EMIOGPIOI[51] !== 1'bz) && EMIOGPIOI[51]; // rv 0 + assign EMIOGPIOI_in[52] = (EMIOGPIOI[52] !== 1'bz) && EMIOGPIOI[52]; // rv 0 + assign EMIOGPIOI_in[53] = (EMIOGPIOI[53] !== 1'bz) && EMIOGPIOI[53]; // rv 0 + assign EMIOGPIOI_in[54] = (EMIOGPIOI[54] !== 1'bz) && EMIOGPIOI[54]; // rv 0 + assign EMIOGPIOI_in[55] = (EMIOGPIOI[55] !== 1'bz) && EMIOGPIOI[55]; // rv 0 + assign EMIOGPIOI_in[56] = (EMIOGPIOI[56] !== 1'bz) && EMIOGPIOI[56]; // rv 0 + assign EMIOGPIOI_in[57] = (EMIOGPIOI[57] !== 1'bz) && EMIOGPIOI[57]; // rv 0 + assign EMIOGPIOI_in[58] = (EMIOGPIOI[58] !== 1'bz) && EMIOGPIOI[58]; // rv 0 + assign EMIOGPIOI_in[59] = (EMIOGPIOI[59] !== 1'bz) && EMIOGPIOI[59]; // rv 0 + assign EMIOGPIOI_in[5] = (EMIOGPIOI[5] !== 1'bz) && EMIOGPIOI[5]; // rv 0 + assign EMIOGPIOI_in[60] = (EMIOGPIOI[60] !== 1'bz) && EMIOGPIOI[60]; // rv 0 + assign EMIOGPIOI_in[61] = (EMIOGPIOI[61] !== 1'bz) && EMIOGPIOI[61]; // rv 0 + assign EMIOGPIOI_in[62] = (EMIOGPIOI[62] !== 1'bz) && EMIOGPIOI[62]; // rv 0 + assign EMIOGPIOI_in[63] = (EMIOGPIOI[63] !== 1'bz) && EMIOGPIOI[63]; // rv 0 + assign EMIOGPIOI_in[64] = (EMIOGPIOI[64] !== 1'bz) && EMIOGPIOI[64]; // rv 0 + assign EMIOGPIOI_in[65] = (EMIOGPIOI[65] !== 1'bz) && EMIOGPIOI[65]; // rv 0 + assign EMIOGPIOI_in[66] = (EMIOGPIOI[66] !== 1'bz) && EMIOGPIOI[66]; // rv 0 + assign EMIOGPIOI_in[67] = (EMIOGPIOI[67] !== 1'bz) && EMIOGPIOI[67]; // rv 0 + assign EMIOGPIOI_in[68] = (EMIOGPIOI[68] !== 1'bz) && EMIOGPIOI[68]; // rv 0 + assign EMIOGPIOI_in[69] = (EMIOGPIOI[69] !== 1'bz) && EMIOGPIOI[69]; // rv 0 + assign EMIOGPIOI_in[6] = (EMIOGPIOI[6] !== 1'bz) && EMIOGPIOI[6]; // rv 0 + assign EMIOGPIOI_in[70] = (EMIOGPIOI[70] !== 1'bz) && EMIOGPIOI[70]; // rv 0 + assign EMIOGPIOI_in[71] = (EMIOGPIOI[71] !== 1'bz) && EMIOGPIOI[71]; // rv 0 + assign EMIOGPIOI_in[72] = (EMIOGPIOI[72] !== 1'bz) && EMIOGPIOI[72]; // rv 0 + assign EMIOGPIOI_in[73] = (EMIOGPIOI[73] !== 1'bz) && EMIOGPIOI[73]; // rv 0 + assign EMIOGPIOI_in[74] = (EMIOGPIOI[74] !== 1'bz) && EMIOGPIOI[74]; // rv 0 + assign EMIOGPIOI_in[75] = (EMIOGPIOI[75] !== 1'bz) && EMIOGPIOI[75]; // rv 0 + assign EMIOGPIOI_in[76] = (EMIOGPIOI[76] !== 1'bz) && EMIOGPIOI[76]; // rv 0 + assign EMIOGPIOI_in[77] = (EMIOGPIOI[77] !== 1'bz) && EMIOGPIOI[77]; // rv 0 + assign EMIOGPIOI_in[78] = (EMIOGPIOI[78] !== 1'bz) && EMIOGPIOI[78]; // rv 0 + assign EMIOGPIOI_in[79] = (EMIOGPIOI[79] !== 1'bz) && EMIOGPIOI[79]; // rv 0 + assign EMIOGPIOI_in[7] = (EMIOGPIOI[7] !== 1'bz) && EMIOGPIOI[7]; // rv 0 + assign EMIOGPIOI_in[80] = (EMIOGPIOI[80] !== 1'bz) && EMIOGPIOI[80]; // rv 0 + assign EMIOGPIOI_in[81] = (EMIOGPIOI[81] !== 1'bz) && EMIOGPIOI[81]; // rv 0 + assign EMIOGPIOI_in[82] = (EMIOGPIOI[82] !== 1'bz) && EMIOGPIOI[82]; // rv 0 + assign EMIOGPIOI_in[83] = (EMIOGPIOI[83] !== 1'bz) && EMIOGPIOI[83]; // rv 0 + assign EMIOGPIOI_in[84] = (EMIOGPIOI[84] !== 1'bz) && EMIOGPIOI[84]; // rv 0 + assign EMIOGPIOI_in[85] = (EMIOGPIOI[85] !== 1'bz) && EMIOGPIOI[85]; // rv 0 + assign EMIOGPIOI_in[86] = (EMIOGPIOI[86] !== 1'bz) && EMIOGPIOI[86]; // rv 0 + assign EMIOGPIOI_in[87] = (EMIOGPIOI[87] !== 1'bz) && EMIOGPIOI[87]; // rv 0 + assign EMIOGPIOI_in[88] = (EMIOGPIOI[88] !== 1'bz) && EMIOGPIOI[88]; // rv 0 + assign EMIOGPIOI_in[89] = (EMIOGPIOI[89] !== 1'bz) && EMIOGPIOI[89]; // rv 0 + assign EMIOGPIOI_in[8] = (EMIOGPIOI[8] !== 1'bz) && EMIOGPIOI[8]; // rv 0 + assign EMIOGPIOI_in[90] = (EMIOGPIOI[90] !== 1'bz) && EMIOGPIOI[90]; // rv 0 + assign EMIOGPIOI_in[91] = (EMIOGPIOI[91] !== 1'bz) && EMIOGPIOI[91]; // rv 0 + assign EMIOGPIOI_in[92] = (EMIOGPIOI[92] !== 1'bz) && EMIOGPIOI[92]; // rv 0 + assign EMIOGPIOI_in[93] = (EMIOGPIOI[93] !== 1'bz) && EMIOGPIOI[93]; // rv 0 + assign EMIOGPIOI_in[94] = (EMIOGPIOI[94] !== 1'bz) && EMIOGPIOI[94]; // rv 0 + assign EMIOGPIOI_in[95] = (EMIOGPIOI[95] !== 1'bz) && EMIOGPIOI[95]; // rv 0 + assign EMIOGPIOI_in[9] = (EMIOGPIOI[9] !== 1'bz) && EMIOGPIOI[9]; // rv 0 + assign EMIOHUBPORTOVERCRNTUSB20_in = (EMIOHUBPORTOVERCRNTUSB20 !== 1'bz) && EMIOHUBPORTOVERCRNTUSB20; // rv 0 + assign EMIOHUBPORTOVERCRNTUSB21_in = (EMIOHUBPORTOVERCRNTUSB21 !== 1'bz) && EMIOHUBPORTOVERCRNTUSB21; // rv 0 + assign EMIOHUBPORTOVERCRNTUSB30_in = (EMIOHUBPORTOVERCRNTUSB30 !== 1'bz) && EMIOHUBPORTOVERCRNTUSB30; // rv 0 + assign EMIOHUBPORTOVERCRNTUSB31_in = (EMIOHUBPORTOVERCRNTUSB31 !== 1'bz) && EMIOHUBPORTOVERCRNTUSB31; // rv 0 + assign EMIOI2C0SCLI_in = (EMIOI2C0SCLI !== 1'bz) && EMIOI2C0SCLI; // rv 0 + assign EMIOI2C0SDAI_in = (EMIOI2C0SDAI !== 1'bz) && EMIOI2C0SDAI; // rv 0 + assign EMIOI2C1SCLI_in = (EMIOI2C1SCLI !== 1'bz) && EMIOI2C1SCLI; // rv 0 + assign EMIOI2C1SDAI_in = (EMIOI2C1SDAI !== 1'bz) && EMIOI2C1SDAI; // rv 0 + assign EMIOSDIO0CDN_in = (EMIOSDIO0CDN !== 1'bz) && EMIOSDIO0CDN; // rv 0 + assign EMIOSDIO0CMDIN_in = (EMIOSDIO0CMDIN !== 1'bz) && EMIOSDIO0CMDIN; // rv 0 + assign EMIOSDIO0DATAIN_in[0] = (EMIOSDIO0DATAIN[0] !== 1'bz) && EMIOSDIO0DATAIN[0]; // rv 0 + assign EMIOSDIO0DATAIN_in[1] = (EMIOSDIO0DATAIN[1] !== 1'bz) && EMIOSDIO0DATAIN[1]; // rv 0 + assign EMIOSDIO0DATAIN_in[2] = (EMIOSDIO0DATAIN[2] !== 1'bz) && EMIOSDIO0DATAIN[2]; // rv 0 + assign EMIOSDIO0DATAIN_in[3] = (EMIOSDIO0DATAIN[3] !== 1'bz) && EMIOSDIO0DATAIN[3]; // rv 0 + assign EMIOSDIO0DATAIN_in[4] = (EMIOSDIO0DATAIN[4] !== 1'bz) && EMIOSDIO0DATAIN[4]; // rv 0 + assign EMIOSDIO0DATAIN_in[5] = (EMIOSDIO0DATAIN[5] !== 1'bz) && EMIOSDIO0DATAIN[5]; // rv 0 + assign EMIOSDIO0DATAIN_in[6] = (EMIOSDIO0DATAIN[6] !== 1'bz) && EMIOSDIO0DATAIN[6]; // rv 0 + assign EMIOSDIO0DATAIN_in[7] = (EMIOSDIO0DATAIN[7] !== 1'bz) && EMIOSDIO0DATAIN[7]; // rv 0 + assign EMIOSDIO0FBCLKIN_in = (EMIOSDIO0FBCLKIN !== 1'bz) && EMIOSDIO0FBCLKIN; // rv 0 + assign EMIOSDIO0WP_in = (EMIOSDIO0WP === 1'bz) || EMIOSDIO0WP; // rv 1 + assign EMIOSDIO1CDN_in = (EMIOSDIO1CDN !== 1'bz) && EMIOSDIO1CDN; // rv 0 + assign EMIOSDIO1CMDIN_in = (EMIOSDIO1CMDIN !== 1'bz) && EMIOSDIO1CMDIN; // rv 0 + assign EMIOSDIO1DATAIN_in[0] = (EMIOSDIO1DATAIN[0] !== 1'bz) && EMIOSDIO1DATAIN[0]; // rv 0 + assign EMIOSDIO1DATAIN_in[1] = (EMIOSDIO1DATAIN[1] !== 1'bz) && EMIOSDIO1DATAIN[1]; // rv 0 + assign EMIOSDIO1DATAIN_in[2] = (EMIOSDIO1DATAIN[2] !== 1'bz) && EMIOSDIO1DATAIN[2]; // rv 0 + assign EMIOSDIO1DATAIN_in[3] = (EMIOSDIO1DATAIN[3] !== 1'bz) && EMIOSDIO1DATAIN[3]; // rv 0 + assign EMIOSDIO1DATAIN_in[4] = (EMIOSDIO1DATAIN[4] !== 1'bz) && EMIOSDIO1DATAIN[4]; // rv 0 + assign EMIOSDIO1DATAIN_in[5] = (EMIOSDIO1DATAIN[5] !== 1'bz) && EMIOSDIO1DATAIN[5]; // rv 0 + assign EMIOSDIO1DATAIN_in[6] = (EMIOSDIO1DATAIN[6] !== 1'bz) && EMIOSDIO1DATAIN[6]; // rv 0 + assign EMIOSDIO1DATAIN_in[7] = (EMIOSDIO1DATAIN[7] !== 1'bz) && EMIOSDIO1DATAIN[7]; // rv 0 + assign EMIOSDIO1FBCLKIN_in = (EMIOSDIO1FBCLKIN !== 1'bz) && EMIOSDIO1FBCLKIN; // rv 0 + assign EMIOSDIO1WP_in = (EMIOSDIO1WP === 1'bz) || EMIOSDIO1WP; // rv 1 + assign EMIOSPI0MI_in = (EMIOSPI0MI !== 1'bz) && EMIOSPI0MI; // rv 0 + assign EMIOSPI0SI_in = (EMIOSPI0SI !== 1'bz) && EMIOSPI0SI; // rv 0 + assign EMIOSPI1MI_in = (EMIOSPI1MI !== 1'bz) && EMIOSPI1MI; // rv 0 + assign EMIOSPI1SI_in = (EMIOSPI1SI !== 1'bz) && EMIOSPI1SI; // rv 0 + assign EMIOTTC0CLKI_in[0] = (EMIOTTC0CLKI[0] !== 1'bz) && EMIOTTC0CLKI[0]; // rv 0 + assign EMIOTTC0CLKI_in[1] = (EMIOTTC0CLKI[1] !== 1'bz) && EMIOTTC0CLKI[1]; // rv 0 + assign EMIOTTC0CLKI_in[2] = (EMIOTTC0CLKI[2] !== 1'bz) && EMIOTTC0CLKI[2]; // rv 0 + assign EMIOTTC1CLKI_in[0] = (EMIOTTC1CLKI[0] !== 1'bz) && EMIOTTC1CLKI[0]; // rv 0 + assign EMIOTTC1CLKI_in[1] = (EMIOTTC1CLKI[1] !== 1'bz) && EMIOTTC1CLKI[1]; // rv 0 + assign EMIOTTC1CLKI_in[2] = (EMIOTTC1CLKI[2] !== 1'bz) && EMIOTTC1CLKI[2]; // rv 0 + assign EMIOTTC2CLKI_in[0] = (EMIOTTC2CLKI[0] !== 1'bz) && EMIOTTC2CLKI[0]; // rv 0 + assign EMIOTTC2CLKI_in[1] = (EMIOTTC2CLKI[1] !== 1'bz) && EMIOTTC2CLKI[1]; // rv 0 + assign EMIOTTC2CLKI_in[2] = (EMIOTTC2CLKI[2] !== 1'bz) && EMIOTTC2CLKI[2]; // rv 0 + assign EMIOTTC3CLKI_in[0] = (EMIOTTC3CLKI[0] !== 1'bz) && EMIOTTC3CLKI[0]; // rv 0 + assign EMIOTTC3CLKI_in[1] = (EMIOTTC3CLKI[1] !== 1'bz) && EMIOTTC3CLKI[1]; // rv 0 + assign EMIOTTC3CLKI_in[2] = (EMIOTTC3CLKI[2] !== 1'bz) && EMIOTTC3CLKI[2]; // rv 0 + assign EMIOUART0CTSN_in = (EMIOUART0CTSN !== 1'bz) && EMIOUART0CTSN; // rv 0 + assign EMIOUART0DCDN_in = (EMIOUART0DCDN !== 1'bz) && EMIOUART0DCDN; // rv 0 + assign EMIOUART0DSRN_in = (EMIOUART0DSRN !== 1'bz) && EMIOUART0DSRN; // rv 0 + assign EMIOUART0RIN_in = (EMIOUART0RIN !== 1'bz) && EMIOUART0RIN; // rv 0 + assign EMIOUART0RX_in = (EMIOUART0RX !== 1'bz) && EMIOUART0RX; // rv 0 + assign EMIOUART1CTSN_in = (EMIOUART1CTSN !== 1'bz) && EMIOUART1CTSN; // rv 0 + assign EMIOUART1DCDN_in = (EMIOUART1DCDN !== 1'bz) && EMIOUART1DCDN; // rv 0 + assign EMIOUART1DSRN_in = (EMIOUART1DSRN !== 1'bz) && EMIOUART1DSRN; // rv 0 + assign EMIOUART1RIN_in = (EMIOUART1RIN !== 1'bz) && EMIOUART1RIN; // rv 0 + assign EMIOUART1RX_in = (EMIOUART1RX !== 1'bz) && EMIOUART1RX; // rv 0 + assign EMIOWDT0CLKI_in = (EMIOWDT0CLKI !== 1'bz) && EMIOWDT0CLKI; // rv 0 + assign EMIOWDT1CLKI_in = (EMIOWDT1CLKI !== 1'bz) && EMIOWDT1CLKI; // rv 0 + assign FMIOGEM0FIFORXCLKFROMPL_in = (FMIOGEM0FIFORXCLKFROMPL !== 1'bz) && FMIOGEM0FIFORXCLKFROMPL; // rv 0 + assign FMIOGEM0SIGNALDETECT_in = (FMIOGEM0SIGNALDETECT !== 1'bz) && FMIOGEM0SIGNALDETECT; // rv 0 + assign FMIOGEM1FIFORXCLKFROMPL_in = (FMIOGEM1FIFORXCLKFROMPL !== 1'bz) && FMIOGEM1FIFORXCLKFROMPL; // rv 0 + assign FMIOGEM1SIGNALDETECT_in = (FMIOGEM1SIGNALDETECT !== 1'bz) && FMIOGEM1SIGNALDETECT; // rv 0 + assign FMIOGEM2FIFORXCLKFROMPL_in = (FMIOGEM2FIFORXCLKFROMPL !== 1'bz) && FMIOGEM2FIFORXCLKFROMPL; // rv 0 + assign FMIOGEM2SIGNALDETECT_in = (FMIOGEM2SIGNALDETECT !== 1'bz) && FMIOGEM2SIGNALDETECT; // rv 0 + assign FMIOGEM3FIFORXCLKFROMPL_in = (FMIOGEM3FIFORXCLKFROMPL !== 1'bz) && FMIOGEM3FIFORXCLKFROMPL; // rv 0 + assign FMIOGEM3SIGNALDETECT_in = (FMIOGEM3SIGNALDETECT !== 1'bz) && FMIOGEM3SIGNALDETECT; // rv 0 + assign FTMGPI_in[0] = (FTMGPI[0] !== 1'bz) && FTMGPI[0]; // rv 0 + assign FTMGPI_in[10] = (FTMGPI[10] !== 1'bz) && FTMGPI[10]; // rv 0 + assign FTMGPI_in[11] = (FTMGPI[11] !== 1'bz) && FTMGPI[11]; // rv 0 + assign FTMGPI_in[12] = (FTMGPI[12] !== 1'bz) && FTMGPI[12]; // rv 0 + assign FTMGPI_in[13] = (FTMGPI[13] !== 1'bz) && FTMGPI[13]; // rv 0 + assign FTMGPI_in[14] = (FTMGPI[14] !== 1'bz) && FTMGPI[14]; // rv 0 + assign FTMGPI_in[15] = (FTMGPI[15] !== 1'bz) && FTMGPI[15]; // rv 0 + assign FTMGPI_in[16] = (FTMGPI[16] !== 1'bz) && FTMGPI[16]; // rv 0 + assign FTMGPI_in[17] = (FTMGPI[17] !== 1'bz) && FTMGPI[17]; // rv 0 + assign FTMGPI_in[18] = (FTMGPI[18] !== 1'bz) && FTMGPI[18]; // rv 0 + assign FTMGPI_in[19] = (FTMGPI[19] !== 1'bz) && FTMGPI[19]; // rv 0 + assign FTMGPI_in[1] = (FTMGPI[1] !== 1'bz) && FTMGPI[1]; // rv 0 + assign FTMGPI_in[20] = (FTMGPI[20] !== 1'bz) && FTMGPI[20]; // rv 0 + assign FTMGPI_in[21] = (FTMGPI[21] !== 1'bz) && FTMGPI[21]; // rv 0 + assign FTMGPI_in[22] = (FTMGPI[22] !== 1'bz) && FTMGPI[22]; // rv 0 + assign FTMGPI_in[23] = (FTMGPI[23] !== 1'bz) && FTMGPI[23]; // rv 0 + assign FTMGPI_in[24] = (FTMGPI[24] !== 1'bz) && FTMGPI[24]; // rv 0 + assign FTMGPI_in[25] = (FTMGPI[25] !== 1'bz) && FTMGPI[25]; // rv 0 + assign FTMGPI_in[26] = (FTMGPI[26] !== 1'bz) && FTMGPI[26]; // rv 0 + assign FTMGPI_in[27] = (FTMGPI[27] !== 1'bz) && FTMGPI[27]; // rv 0 + assign FTMGPI_in[28] = (FTMGPI[28] !== 1'bz) && FTMGPI[28]; // rv 0 + assign FTMGPI_in[29] = (FTMGPI[29] !== 1'bz) && FTMGPI[29]; // rv 0 + assign FTMGPI_in[2] = (FTMGPI[2] !== 1'bz) && FTMGPI[2]; // rv 0 + assign FTMGPI_in[30] = (FTMGPI[30] !== 1'bz) && FTMGPI[30]; // rv 0 + assign FTMGPI_in[31] = (FTMGPI[31] !== 1'bz) && FTMGPI[31]; // rv 0 + assign FTMGPI_in[3] = (FTMGPI[3] !== 1'bz) && FTMGPI[3]; // rv 0 + assign FTMGPI_in[4] = (FTMGPI[4] !== 1'bz) && FTMGPI[4]; // rv 0 + assign FTMGPI_in[5] = (FTMGPI[5] !== 1'bz) && FTMGPI[5]; // rv 0 + assign FTMGPI_in[6] = (FTMGPI[6] !== 1'bz) && FTMGPI[6]; // rv 0 + assign FTMGPI_in[7] = (FTMGPI[7] !== 1'bz) && FTMGPI[7]; // rv 0 + assign FTMGPI_in[8] = (FTMGPI[8] !== 1'bz) && FTMGPI[8]; // rv 0 + assign FTMGPI_in[9] = (FTMGPI[9] !== 1'bz) && FTMGPI[9]; // rv 0 + assign NFIQ0LPDRPU_in = (NFIQ0LPDRPU === 1'bz) || NFIQ0LPDRPU; // rv 1 + assign NFIQ1LPDRPU_in = (NFIQ1LPDRPU === 1'bz) || NFIQ1LPDRPU; // rv 1 + assign NIRQ0LPDRPU_in = (NIRQ0LPDRPU === 1'bz) || NIRQ0LPDRPU; // rv 1 + assign NIRQ1LPDRPU_in = (NIRQ1LPDRPU === 1'bz) || NIRQ1LPDRPU; // rv 1 + assign PLACPINACT_in = (PLACPINACT !== 1'bz) && PLACPINACT; // rv 0 + assign PLFPGASTOP_in[0] = (PLFPGASTOP[0] !== 1'bz) && PLFPGASTOP[0]; // rv 0 + assign PLFPGASTOP_in[1] = (PLFPGASTOP[1] !== 1'bz) && PLFPGASTOP[1]; // rv 0 + assign PLFPGASTOP_in[2] = (PLFPGASTOP[2] !== 1'bz) && PLFPGASTOP[2]; // rv 0 + assign PLFPGASTOP_in[3] = (PLFPGASTOP[3] !== 1'bz) && PLFPGASTOP[3]; // rv 0 + assign PLLAUXREFCLKFPD_in[0] = (PLLAUXREFCLKFPD[0] !== 1'bz) && PLLAUXREFCLKFPD[0]; // rv 0 + assign PLLAUXREFCLKFPD_in[1] = (PLLAUXREFCLKFPD[1] !== 1'bz) && PLLAUXREFCLKFPD[1]; // rv 0 + assign PLLAUXREFCLKFPD_in[2] = (PLLAUXREFCLKFPD[2] !== 1'bz) && PLLAUXREFCLKFPD[2]; // rv 0 + assign PLLAUXREFCLKLPD_in[0] = (PLLAUXREFCLKLPD[0] !== 1'bz) && PLLAUXREFCLKLPD[0]; // rv 0 + assign PLLAUXREFCLKLPD_in[1] = (PLLAUXREFCLKLPD[1] !== 1'bz) && PLLAUXREFCLKLPD[1]; // rv 0 + assign PLPMUGPI_in[0] = (PLPMUGPI[0] !== 1'bz) && PLPMUGPI[0]; // rv 0 + assign PLPMUGPI_in[10] = (PLPMUGPI[10] !== 1'bz) && PLPMUGPI[10]; // rv 0 + assign PLPMUGPI_in[11] = (PLPMUGPI[11] !== 1'bz) && PLPMUGPI[11]; // rv 0 + assign PLPMUGPI_in[12] = (PLPMUGPI[12] !== 1'bz) && PLPMUGPI[12]; // rv 0 + assign PLPMUGPI_in[13] = (PLPMUGPI[13] !== 1'bz) && PLPMUGPI[13]; // rv 0 + assign PLPMUGPI_in[14] = (PLPMUGPI[14] !== 1'bz) && PLPMUGPI[14]; // rv 0 + assign PLPMUGPI_in[15] = (PLPMUGPI[15] !== 1'bz) && PLPMUGPI[15]; // rv 0 + assign PLPMUGPI_in[16] = (PLPMUGPI[16] !== 1'bz) && PLPMUGPI[16]; // rv 0 + assign PLPMUGPI_in[17] = (PLPMUGPI[17] !== 1'bz) && PLPMUGPI[17]; // rv 0 + assign PLPMUGPI_in[18] = (PLPMUGPI[18] !== 1'bz) && PLPMUGPI[18]; // rv 0 + assign PLPMUGPI_in[19] = (PLPMUGPI[19] !== 1'bz) && PLPMUGPI[19]; // rv 0 + assign PLPMUGPI_in[1] = (PLPMUGPI[1] !== 1'bz) && PLPMUGPI[1]; // rv 0 + assign PLPMUGPI_in[20] = (PLPMUGPI[20] !== 1'bz) && PLPMUGPI[20]; // rv 0 + assign PLPMUGPI_in[21] = (PLPMUGPI[21] !== 1'bz) && PLPMUGPI[21]; // rv 0 + assign PLPMUGPI_in[22] = (PLPMUGPI[22] !== 1'bz) && PLPMUGPI[22]; // rv 0 + assign PLPMUGPI_in[23] = (PLPMUGPI[23] !== 1'bz) && PLPMUGPI[23]; // rv 0 + assign PLPMUGPI_in[24] = (PLPMUGPI[24] !== 1'bz) && PLPMUGPI[24]; // rv 0 + assign PLPMUGPI_in[25] = (PLPMUGPI[25] !== 1'bz) && PLPMUGPI[25]; // rv 0 + assign PLPMUGPI_in[26] = (PLPMUGPI[26] !== 1'bz) && PLPMUGPI[26]; // rv 0 + assign PLPMUGPI_in[27] = (PLPMUGPI[27] !== 1'bz) && PLPMUGPI[27]; // rv 0 + assign PLPMUGPI_in[28] = (PLPMUGPI[28] !== 1'bz) && PLPMUGPI[28]; // rv 0 + assign PLPMUGPI_in[29] = (PLPMUGPI[29] !== 1'bz) && PLPMUGPI[29]; // rv 0 + assign PLPMUGPI_in[2] = (PLPMUGPI[2] !== 1'bz) && PLPMUGPI[2]; // rv 0 + assign PLPMUGPI_in[30] = (PLPMUGPI[30] !== 1'bz) && PLPMUGPI[30]; // rv 0 + assign PLPMUGPI_in[31] = (PLPMUGPI[31] !== 1'bz) && PLPMUGPI[31]; // rv 0 + assign PLPMUGPI_in[3] = (PLPMUGPI[3] !== 1'bz) && PLPMUGPI[3]; // rv 0 + assign PLPMUGPI_in[4] = (PLPMUGPI[4] !== 1'bz) && PLPMUGPI[4]; // rv 0 + assign PLPMUGPI_in[5] = (PLPMUGPI[5] !== 1'bz) && PLPMUGPI[5]; // rv 0 + assign PLPMUGPI_in[6] = (PLPMUGPI[6] !== 1'bz) && PLPMUGPI[6]; // rv 0 + assign PLPMUGPI_in[7] = (PLPMUGPI[7] !== 1'bz) && PLPMUGPI[7]; // rv 0 + assign PLPMUGPI_in[8] = (PLPMUGPI[8] !== 1'bz) && PLPMUGPI[8]; // rv 0 + assign PLPMUGPI_in[9] = (PLPMUGPI[9] !== 1'bz) && PLPMUGPI[9]; // rv 0 + assign PLPSAPUGICFIQ_in[0] = (PLPSAPUGICFIQ[0] !== 1'bz) && PLPSAPUGICFIQ[0]; // rv 0 + assign PLPSAPUGICFIQ_in[1] = (PLPSAPUGICFIQ[1] !== 1'bz) && PLPSAPUGICFIQ[1]; // rv 0 + assign PLPSAPUGICFIQ_in[2] = (PLPSAPUGICFIQ[2] !== 1'bz) && PLPSAPUGICFIQ[2]; // rv 0 + assign PLPSAPUGICFIQ_in[3] = (PLPSAPUGICFIQ[3] !== 1'bz) && PLPSAPUGICFIQ[3]; // rv 0 + assign PLPSAPUGICIRQ_in[0] = (PLPSAPUGICIRQ[0] !== 1'bz) && PLPSAPUGICIRQ[0]; // rv 0 + assign PLPSAPUGICIRQ_in[1] = (PLPSAPUGICIRQ[1] !== 1'bz) && PLPSAPUGICIRQ[1]; // rv 0 + assign PLPSAPUGICIRQ_in[2] = (PLPSAPUGICIRQ[2] !== 1'bz) && PLPSAPUGICIRQ[2]; // rv 0 + assign PLPSAPUGICIRQ_in[3] = (PLPSAPUGICIRQ[3] !== 1'bz) && PLPSAPUGICIRQ[3]; // rv 0 + assign PLPSEVENTI_in = (PLPSEVENTI !== 1'bz) && PLPSEVENTI; // rv 0 + assign PLPSIRQ0_in[0] = (PLPSIRQ0[0] !== 1'bz) && PLPSIRQ0[0]; // rv 0 + assign PLPSIRQ0_in[1] = (PLPSIRQ0[1] !== 1'bz) && PLPSIRQ0[1]; // rv 0 + assign PLPSIRQ0_in[2] = (PLPSIRQ0[2] !== 1'bz) && PLPSIRQ0[2]; // rv 0 + assign PLPSIRQ0_in[3] = (PLPSIRQ0[3] !== 1'bz) && PLPSIRQ0[3]; // rv 0 + assign PLPSIRQ0_in[4] = (PLPSIRQ0[4] !== 1'bz) && PLPSIRQ0[4]; // rv 0 + assign PLPSIRQ0_in[5] = (PLPSIRQ0[5] !== 1'bz) && PLPSIRQ0[5]; // rv 0 + assign PLPSIRQ0_in[6] = (PLPSIRQ0[6] !== 1'bz) && PLPSIRQ0[6]; // rv 0 + assign PLPSIRQ0_in[7] = (PLPSIRQ0[7] !== 1'bz) && PLPSIRQ0[7]; // rv 0 + assign PLPSIRQ1_in[0] = (PLPSIRQ1[0] !== 1'bz) && PLPSIRQ1[0]; // rv 0 + assign PLPSIRQ1_in[1] = (PLPSIRQ1[1] !== 1'bz) && PLPSIRQ1[1]; // rv 0 + assign PLPSIRQ1_in[2] = (PLPSIRQ1[2] !== 1'bz) && PLPSIRQ1[2]; // rv 0 + assign PLPSIRQ1_in[3] = (PLPSIRQ1[3] !== 1'bz) && PLPSIRQ1[3]; // rv 0 + assign PLPSIRQ1_in[4] = (PLPSIRQ1[4] !== 1'bz) && PLPSIRQ1[4]; // rv 0 + assign PLPSIRQ1_in[5] = (PLPSIRQ1[5] !== 1'bz) && PLPSIRQ1[5]; // rv 0 + assign PLPSIRQ1_in[6] = (PLPSIRQ1[6] !== 1'bz) && PLPSIRQ1[6]; // rv 0 + assign PLPSIRQ1_in[7] = (PLPSIRQ1[7] !== 1'bz) && PLPSIRQ1[7]; // rv 0 + assign PLPSTRACECLK_in = (PLPSTRACECLK !== 1'bz) && PLPSTRACECLK; // rv 0 + assign PLPSTRIGACK_in[0] = (PLPSTRIGACK[0] !== 1'bz) && PLPSTRIGACK[0]; // rv 0 + assign PLPSTRIGACK_in[1] = (PLPSTRIGACK[1] !== 1'bz) && PLPSTRIGACK[1]; // rv 0 + assign PLPSTRIGACK_in[2] = (PLPSTRIGACK[2] !== 1'bz) && PLPSTRIGACK[2]; // rv 0 + assign PLPSTRIGACK_in[3] = (PLPSTRIGACK[3] !== 1'bz) && PLPSTRIGACK[3]; // rv 0 + assign PLPSTRIGGER_in[0] = (PLPSTRIGGER[0] !== 1'bz) && PLPSTRIGGER[0]; // rv 0 + assign PLPSTRIGGER_in[1] = (PLPSTRIGGER[1] !== 1'bz) && PLPSTRIGGER[1]; // rv 0 + assign PLPSTRIGGER_in[2] = (PLPSTRIGGER[2] !== 1'bz) && PLPSTRIGGER[2]; // rv 0 + assign PLPSTRIGGER_in[3] = (PLPSTRIGGER[3] !== 1'bz) && PLPSTRIGGER[3]; // rv 0 + assign PMUERRORFROMPL_in[0] = (PMUERRORFROMPL[0] !== 1'bz) && PMUERRORFROMPL[0]; // rv 0 + assign PMUERRORFROMPL_in[1] = (PMUERRORFROMPL[1] !== 1'bz) && PMUERRORFROMPL[1]; // rv 0 + assign PMUERRORFROMPL_in[2] = (PMUERRORFROMPL[2] !== 1'bz) && PMUERRORFROMPL[2]; // rv 0 + assign PMUERRORFROMPL_in[3] = (PMUERRORFROMPL[3] !== 1'bz) && PMUERRORFROMPL[3]; // rv 0 + assign PSS_ALTO_CORE_PAD_MGTRXN0IN_in = PSS_ALTO_CORE_PAD_MGTRXN0IN; + assign PSS_ALTO_CORE_PAD_MGTRXN1IN_in = PSS_ALTO_CORE_PAD_MGTRXN1IN; + assign PSS_ALTO_CORE_PAD_MGTRXN2IN_in = PSS_ALTO_CORE_PAD_MGTRXN2IN; + assign PSS_ALTO_CORE_PAD_MGTRXN3IN_in = PSS_ALTO_CORE_PAD_MGTRXN3IN; + assign PSS_ALTO_CORE_PAD_MGTRXP0IN_in = PSS_ALTO_CORE_PAD_MGTRXP0IN; + assign PSS_ALTO_CORE_PAD_MGTRXP1IN_in = PSS_ALTO_CORE_PAD_MGTRXP1IN; + assign PSS_ALTO_CORE_PAD_MGTRXP2IN_in = PSS_ALTO_CORE_PAD_MGTRXP2IN; + assign PSS_ALTO_CORE_PAD_MGTRXP3IN_in = PSS_ALTO_CORE_PAD_MGTRXP3IN; + assign PSS_ALTO_CORE_PAD_PADI_in = PSS_ALTO_CORE_PAD_PADI; + assign PSS_ALTO_CORE_PAD_REFN0IN_in = PSS_ALTO_CORE_PAD_REFN0IN; + assign PSS_ALTO_CORE_PAD_REFN1IN_in = PSS_ALTO_CORE_PAD_REFN1IN; + assign PSS_ALTO_CORE_PAD_REFN2IN_in = PSS_ALTO_CORE_PAD_REFN2IN; + assign PSS_ALTO_CORE_PAD_REFN3IN_in = PSS_ALTO_CORE_PAD_REFN3IN; + assign PSS_ALTO_CORE_PAD_REFP0IN_in = PSS_ALTO_CORE_PAD_REFP0IN; + assign PSS_ALTO_CORE_PAD_REFP1IN_in = PSS_ALTO_CORE_PAD_REFP1IN; + assign PSS_ALTO_CORE_PAD_REFP2IN_in = PSS_ALTO_CORE_PAD_REFP2IN; + assign PSS_ALTO_CORE_PAD_REFP3IN_in = PSS_ALTO_CORE_PAD_REFP3IN; + assign RPUEVENTI0_in = (RPUEVENTI0 !== 1'bz) && RPUEVENTI0; // rv 0 + assign RPUEVENTI1_in = (RPUEVENTI1 !== 1'bz) && RPUEVENTI1; // rv 0 + assign STMEVENT_in[0] = (STMEVENT[0] !== 1'bz) && STMEVENT[0]; // rv 0 + assign STMEVENT_in[10] = (STMEVENT[10] !== 1'bz) && STMEVENT[10]; // rv 0 + assign STMEVENT_in[11] = (STMEVENT[11] !== 1'bz) && STMEVENT[11]; // rv 0 + assign STMEVENT_in[12] = (STMEVENT[12] !== 1'bz) && STMEVENT[12]; // rv 0 + assign STMEVENT_in[13] = (STMEVENT[13] !== 1'bz) && STMEVENT[13]; // rv 0 + assign STMEVENT_in[14] = (STMEVENT[14] !== 1'bz) && STMEVENT[14]; // rv 0 + assign STMEVENT_in[15] = (STMEVENT[15] !== 1'bz) && STMEVENT[15]; // rv 0 + assign STMEVENT_in[16] = (STMEVENT[16] !== 1'bz) && STMEVENT[16]; // rv 0 + assign STMEVENT_in[17] = (STMEVENT[17] !== 1'bz) && STMEVENT[17]; // rv 0 + assign STMEVENT_in[18] = (STMEVENT[18] !== 1'bz) && STMEVENT[18]; // rv 0 + assign STMEVENT_in[19] = (STMEVENT[19] !== 1'bz) && STMEVENT[19]; // rv 0 + assign STMEVENT_in[1] = (STMEVENT[1] !== 1'bz) && STMEVENT[1]; // rv 0 + assign STMEVENT_in[20] = (STMEVENT[20] !== 1'bz) && STMEVENT[20]; // rv 0 + assign STMEVENT_in[21] = (STMEVENT[21] !== 1'bz) && STMEVENT[21]; // rv 0 + assign STMEVENT_in[22] = (STMEVENT[22] !== 1'bz) && STMEVENT[22]; // rv 0 + assign STMEVENT_in[23] = (STMEVENT[23] !== 1'bz) && STMEVENT[23]; // rv 0 + assign STMEVENT_in[24] = (STMEVENT[24] !== 1'bz) && STMEVENT[24]; // rv 0 + assign STMEVENT_in[25] = (STMEVENT[25] !== 1'bz) && STMEVENT[25]; // rv 0 + assign STMEVENT_in[26] = (STMEVENT[26] !== 1'bz) && STMEVENT[26]; // rv 0 + assign STMEVENT_in[27] = (STMEVENT[27] !== 1'bz) && STMEVENT[27]; // rv 0 + assign STMEVENT_in[28] = (STMEVENT[28] !== 1'bz) && STMEVENT[28]; // rv 0 + assign STMEVENT_in[29] = (STMEVENT[29] !== 1'bz) && STMEVENT[29]; // rv 0 + assign STMEVENT_in[2] = (STMEVENT[2] !== 1'bz) && STMEVENT[2]; // rv 0 + assign STMEVENT_in[30] = (STMEVENT[30] !== 1'bz) && STMEVENT[30]; // rv 0 + assign STMEVENT_in[31] = (STMEVENT[31] !== 1'bz) && STMEVENT[31]; // rv 0 + assign STMEVENT_in[32] = (STMEVENT[32] !== 1'bz) && STMEVENT[32]; // rv 0 + assign STMEVENT_in[33] = (STMEVENT[33] !== 1'bz) && STMEVENT[33]; // rv 0 + assign STMEVENT_in[34] = (STMEVENT[34] !== 1'bz) && STMEVENT[34]; // rv 0 + assign STMEVENT_in[35] = (STMEVENT[35] !== 1'bz) && STMEVENT[35]; // rv 0 + assign STMEVENT_in[36] = (STMEVENT[36] !== 1'bz) && STMEVENT[36]; // rv 0 + assign STMEVENT_in[37] = (STMEVENT[37] !== 1'bz) && STMEVENT[37]; // rv 0 + assign STMEVENT_in[38] = (STMEVENT[38] !== 1'bz) && STMEVENT[38]; // rv 0 + assign STMEVENT_in[39] = (STMEVENT[39] !== 1'bz) && STMEVENT[39]; // rv 0 + assign STMEVENT_in[3] = (STMEVENT[3] !== 1'bz) && STMEVENT[3]; // rv 0 + assign STMEVENT_in[40] = (STMEVENT[40] !== 1'bz) && STMEVENT[40]; // rv 0 + assign STMEVENT_in[41] = (STMEVENT[41] !== 1'bz) && STMEVENT[41]; // rv 0 + assign STMEVENT_in[42] = (STMEVENT[42] !== 1'bz) && STMEVENT[42]; // rv 0 + assign STMEVENT_in[43] = (STMEVENT[43] !== 1'bz) && STMEVENT[43]; // rv 0 + assign STMEVENT_in[44] = (STMEVENT[44] !== 1'bz) && STMEVENT[44]; // rv 0 + assign STMEVENT_in[45] = (STMEVENT[45] !== 1'bz) && STMEVENT[45]; // rv 0 + assign STMEVENT_in[46] = (STMEVENT[46] !== 1'bz) && STMEVENT[46]; // rv 0 + assign STMEVENT_in[47] = (STMEVENT[47] !== 1'bz) && STMEVENT[47]; // rv 0 + assign STMEVENT_in[48] = (STMEVENT[48] !== 1'bz) && STMEVENT[48]; // rv 0 + assign STMEVENT_in[49] = (STMEVENT[49] !== 1'bz) && STMEVENT[49]; // rv 0 + assign STMEVENT_in[4] = (STMEVENT[4] !== 1'bz) && STMEVENT[4]; // rv 0 + assign STMEVENT_in[50] = (STMEVENT[50] !== 1'bz) && STMEVENT[50]; // rv 0 + assign STMEVENT_in[51] = (STMEVENT[51] !== 1'bz) && STMEVENT[51]; // rv 0 + assign STMEVENT_in[52] = (STMEVENT[52] !== 1'bz) && STMEVENT[52]; // rv 0 + assign STMEVENT_in[53] = (STMEVENT[53] !== 1'bz) && STMEVENT[53]; // rv 0 + assign STMEVENT_in[54] = (STMEVENT[54] !== 1'bz) && STMEVENT[54]; // rv 0 + assign STMEVENT_in[55] = (STMEVENT[55] !== 1'bz) && STMEVENT[55]; // rv 0 + assign STMEVENT_in[56] = (STMEVENT[56] !== 1'bz) && STMEVENT[56]; // rv 0 + assign STMEVENT_in[57] = (STMEVENT[57] !== 1'bz) && STMEVENT[57]; // rv 0 + assign STMEVENT_in[58] = (STMEVENT[58] !== 1'bz) && STMEVENT[58]; // rv 0 + assign STMEVENT_in[59] = (STMEVENT[59] !== 1'bz) && STMEVENT[59]; // rv 0 + assign STMEVENT_in[5] = (STMEVENT[5] !== 1'bz) && STMEVENT[5]; // rv 0 + assign STMEVENT_in[6] = (STMEVENT[6] !== 1'bz) && STMEVENT[6]; // rv 0 + assign STMEVENT_in[7] = (STMEVENT[7] !== 1'bz) && STMEVENT[7]; // rv 0 + assign STMEVENT_in[8] = (STMEVENT[8] !== 1'bz) && STMEVENT[8]; // rv 0 + assign STMEVENT_in[9] = (STMEVENT[9] !== 1'bz) && STMEVENT[9]; // rv 0 + + +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (ADMAFCICLK[0] => ADMA2PLCACK[0]) = (0:0:0, 0:0:0); + (ADMAFCICLK[0] => ADMA2PLTVLD[0]) = (0:0:0, 0:0:0); + (ADMAFCICLK[1] => ADMA2PLCACK[1]) = (0:0:0, 0:0:0); + (ADMAFCICLK[1] => ADMA2PLTVLD[1]) = (0:0:0, 0:0:0); + (ADMAFCICLK[2] => ADMA2PLCACK[2]) = (0:0:0, 0:0:0); + (ADMAFCICLK[2] => ADMA2PLTVLD[2]) = (0:0:0, 0:0:0); + (ADMAFCICLK[3] => ADMA2PLCACK[3]) = (0:0:0, 0:0:0); + (ADMAFCICLK[3] => ADMA2PLTVLD[3]) = (0:0:0, 0:0:0); + (ADMAFCICLK[4] => ADMA2PLCACK[4]) = (0:0:0, 0:0:0); + (ADMAFCICLK[4] => ADMA2PLTVLD[4]) = (0:0:0, 0:0:0); + (ADMAFCICLK[5] => ADMA2PLCACK[5]) = (0:0:0, 0:0:0); + (ADMAFCICLK[5] => ADMA2PLTVLD[5]) = (0:0:0, 0:0:0); + (ADMAFCICLK[6] => ADMA2PLCACK[6]) = (0:0:0, 0:0:0); + (ADMAFCICLK[6] => ADMA2PLTVLD[6]) = (0:0:0, 0:0:0); + (ADMAFCICLK[7] => ADMA2PLCACK[7]) = (0:0:0, 0:0:0); + (ADMAFCICLK[7] => ADMA2PLTVLD[7]) = (0:0:0, 0:0:0); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[0]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[10]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[11]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[12]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[13]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[14]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[15]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[16]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[17]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[18]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[19]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[1]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[20]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[21]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[22]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[23]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[24]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[25]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[26]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[27]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[28]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[29]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[2]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[30]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[31]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[3]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[4]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[5]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[6]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[7]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[8]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTDATA[9]) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTID) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPMAXISMIXEDAUDIOTVALID) = (100:100:100, 100:100:100); + (DPSAXISAUDIOCLK => DPSAXISAUDIOTREADY) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPLIVEVIDEODEOUT) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTHSYNC) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[0]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[10]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[11]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[12]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[13]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[14]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[15]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[16]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[17]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[18]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[19]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[1]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[20]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[21]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[22]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[23]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[24]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[25]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[26]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[27]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[28]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[29]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[2]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[30]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[31]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[32]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[33]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[34]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[35]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[3]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[4]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[5]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[6]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[7]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[8]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTPIXEL1[9]) = (100:100:100, 100:100:100); + (DPVIDEOINCLK => DPVIDEOOUTVSYNC) = (100:100:100, 100:100:100); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET0GMIITXCLK => EMIOENET0GMIITXER) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET1GMIITXCLK => EMIOENET1GMIITXER) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET2GMIITXCLK => EMIOENET2GMIITXER) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[0]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[1]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[2]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[3]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[4]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[5]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[6]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXD[7]) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXEN) = (0:0:0, 0:0:0); + (EMIOENET3GMIITXCLK => EMIOENET3GMIITXER) = (0:0:0, 0:0:0); + (EMIOSPI0SCLKI => EMIOSPI0SO) = (100:100:100, 100:100:100); + (EMIOSPI1SCLKI => EMIOSPI1SO) = (100:100:100, 100:100:100); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[0]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[1]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[2]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[3]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[4]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[5]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[6]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWDATA[7]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWEOP) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWERR) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWFLUSH) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSOP) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[0]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[10]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[11]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[12]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[13]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[14]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[15]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[16]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[17]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[18]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[19]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[1]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[20]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[21]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[22]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[23]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[24]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[25]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[26]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[27]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[28]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[29]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[2]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[30]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[31]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[32]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[33]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[34]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[35]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[36]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[37]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[38]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[39]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[3]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[40]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[41]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[42]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[43]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[44]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[4]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[5]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[6]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[7]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[8]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWSTATUS[9]) = (0:0:0, 0:0:0); + (FMIOGEM0FIFORXCLKFROMPL => EMIOENET0RXWWR) = (0:0:0, 0:0:0); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0DMATXENDTOG) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0TXRRD) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0TXRSTATUS[0]) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0TXRSTATUS[1]) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0TXRSTATUS[2]) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOENET0TXRSTATUS[3]) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0DELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0PDELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0PDELAYRESPTX) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0SYNCFRAMETX) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0TXRFIXEDLAT) = (100:100:100, 100:100:100); + (FMIOGEM0FIFOTXCLKFROMPL => EMIOGEM0TXSOF) = (100:100:100, 100:100:100); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[0]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[1]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[2]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[3]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[4]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[5]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[6]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWDATA[7]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWEOP) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWERR) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWFLUSH) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSOP) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[0]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[10]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[11]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[12]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[13]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[14]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[15]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[16]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[17]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[18]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[19]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[1]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[20]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[21]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[22]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[23]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[24]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[25]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[26]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[27]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[28]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[29]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[2]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[30]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[31]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[32]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[33]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[34]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[35]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[36]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[37]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[38]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[39]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[3]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[40]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[41]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[42]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[43]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[44]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[4]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[5]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[6]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[7]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[8]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWSTATUS[9]) = (0:0:0, 0:0:0); + (FMIOGEM1FIFORXCLKFROMPL => EMIOENET1RXWWR) = (0:0:0, 0:0:0); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1DMATXENDTOG) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1TXRRD) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1TXRSTATUS[0]) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1TXRSTATUS[1]) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1TXRSTATUS[2]) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOENET1TXRSTATUS[3]) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1DELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1PDELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1PDELAYRESPTX) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1SYNCFRAMETX) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1TXRFIXEDLAT) = (100:100:100, 100:100:100); + (FMIOGEM1FIFOTXCLKFROMPL => EMIOGEM1TXSOF) = (100:100:100, 100:100:100); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[0]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[1]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[2]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[3]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[4]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[5]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[6]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWDATA[7]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWEOP) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWERR) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWFLUSH) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSOP) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[0]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[10]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[11]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[12]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[13]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[14]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[15]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[16]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[17]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[18]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[19]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[1]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[20]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[21]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[22]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[23]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[24]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[25]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[26]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[27]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[28]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[29]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[2]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[30]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[31]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[32]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[33]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[34]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[35]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[36]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[37]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[38]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[39]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[3]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[40]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[41]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[42]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[43]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[44]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[4]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[5]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[6]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[7]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[8]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWSTATUS[9]) = (0:0:0, 0:0:0); + (FMIOGEM2FIFORXCLKFROMPL => EMIOENET2RXWWR) = (0:0:0, 0:0:0); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2DMATXENDTOG) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2TXRRD) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2TXRSTATUS[0]) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2TXRSTATUS[1]) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2TXRSTATUS[2]) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOENET2TXRSTATUS[3]) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2DELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2PDELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2PDELAYRESPTX) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2SYNCFRAMETX) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2TXRFIXEDLAT) = (100:100:100, 100:100:100); + (FMIOGEM2FIFOTXCLKFROMPL => EMIOGEM2TXSOF) = (100:100:100, 100:100:100); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[0]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[1]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[2]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[3]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[4]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[5]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[6]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWDATA[7]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWEOP) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWERR) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWFLUSH) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSOP) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[0]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[10]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[11]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[12]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[13]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[14]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[15]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[16]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[17]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[18]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[19]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[1]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[20]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[21]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[22]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[23]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[24]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[25]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[26]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[27]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[28]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[29]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[2]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[30]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[31]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[32]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[33]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[34]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[35]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[36]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[37]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[38]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[39]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[3]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[40]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[41]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[42]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[43]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[44]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[4]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[5]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[6]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[7]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[8]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWSTATUS[9]) = (0:0:0, 0:0:0); + (FMIOGEM3FIFORXCLKFROMPL => EMIOENET3RXWWR) = (0:0:0, 0:0:0); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3DMATXENDTOG) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3TXRRD) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3TXRSTATUS[0]) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3TXRSTATUS[1]) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3TXRSTATUS[2]) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOENET3TXRSTATUS[3]) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3DELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3PDELAYREQTX) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3PDELAYRESPTX) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3SYNCFRAMETX) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3TXRFIXEDLAT) = (100:100:100, 100:100:100); + (FMIOGEM3FIFOTXCLKFROMPL => EMIOGEM3TXSOF) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[0]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[10]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[11]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[12]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[13]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[14]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[15]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[16]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[17]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[18]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[19]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[1]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[20]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[21]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[22]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[23]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[24]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[25]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[26]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[27]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[28]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[29]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[2]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[30]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[31]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[32]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[33]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[34]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[35]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[36]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[37]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[38]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[39]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[3]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[40]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[41]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[42]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[43]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[44]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[45]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[46]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[47]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[48]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[49]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[4]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[50]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[51]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[52]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[53]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[54]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[55]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[56]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[57]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[58]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[59]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[5]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[60]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[61]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[62]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[63]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[64]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[65]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[66]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[67]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[68]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[69]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[6]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[70]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[71]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[72]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[73]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[74]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[75]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[76]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[77]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[78]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[79]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[7]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[80]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[81]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[82]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[83]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[84]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[85]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[86]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[87]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[88]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[89]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[8]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[90]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[91]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[92]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[93]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOENET0GEMTSUTIMERCNT[9]) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOGEM0TSUTIMERCMPVAL) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOGEM1TSUTIMERCMPVAL) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOGEM2TSUTIMERCMPVAL) = (100:100:100, 100:100:100); + (FMIOGEMTSUCLKFROMPL => EMIOGEM3TSUTIMERCMPVAL) = (100:100:100, 100:100:100); + (GDMAFCICLK[0] => GDMA2PLCACK[0]) = (0:0:0, 0:0:0); + (GDMAFCICLK[0] => GDMA2PLTVLD[0]) = (0:0:0, 0:0:0); + (GDMAFCICLK[1] => GDMA2PLCACK[1]) = (0:0:0, 0:0:0); + (GDMAFCICLK[1] => GDMA2PLTVLD[1]) = (0:0:0, 0:0:0); + (GDMAFCICLK[2] => GDMA2PLCACK[2]) = (0:0:0, 0:0:0); + (GDMAFCICLK[2] => GDMA2PLTVLD[2]) = (0:0:0, 0:0:0); + (GDMAFCICLK[3] => GDMA2PLCACK[3]) = (0:0:0, 0:0:0); + (GDMAFCICLK[3] => GDMA2PLTVLD[3]) = (0:0:0, 0:0:0); + (GDMAFCICLK[4] => GDMA2PLCACK[4]) = (0:0:0, 0:0:0); + (GDMAFCICLK[4] => GDMA2PLTVLD[4]) = (0:0:0, 0:0:0); + (GDMAFCICLK[5] => GDMA2PLCACK[5]) = (0:0:0, 0:0:0); + (GDMAFCICLK[5] => GDMA2PLTVLD[5]) = (0:0:0, 0:0:0); + (GDMAFCICLK[6] => GDMA2PLCACK[6]) = (0:0:0, 0:0:0); + (GDMAFCICLK[6] => GDMA2PLTVLD[6]) = (0:0:0, 0:0:0); + (GDMAFCICLK[7] => GDMA2PLCACK[7]) = (0:0:0, 0:0:0); + (GDMAFCICLK[7] => GDMA2PLTVLD[7]) = (0:0:0, 0:0:0); + (MAXIGP0ACLK => MAXIGP0ARADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARID[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARLOCK) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0ARVALID) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWID[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWLOCK) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0AWVALID) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0BREADY) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0RREADY) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[100]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[101]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[102]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[103]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[104]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[105]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[106]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[107]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[108]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[109]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[110]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[111]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[112]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[113]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[114]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[115]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[116]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[117]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[118]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[119]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[120]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[121]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[122]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[123]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[124]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[125]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[126]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[127]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[16]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[17]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[18]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[19]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[20]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[21]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[22]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[23]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[24]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[25]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[26]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[27]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[28]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[29]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[30]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[31]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[32]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[33]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[34]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[35]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[36]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[37]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[38]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[39]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[40]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[41]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[42]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[43]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[44]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[45]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[46]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[47]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[48]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[49]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[50]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[51]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[52]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[53]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[54]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[55]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[56]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[57]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[58]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[59]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[60]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[61]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[62]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[63]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[64]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[65]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[66]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[67]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[68]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[69]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[70]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[71]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[72]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[73]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[74]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[75]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[76]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[77]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[78]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[79]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[80]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[81]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[82]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[83]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[84]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[85]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[86]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[87]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[88]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[89]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[90]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[91]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[92]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[93]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[94]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[95]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[96]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[97]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[98]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[99]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WDATA[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WLAST) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[0]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[10]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[11]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[12]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[13]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[14]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[15]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[1]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[2]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[3]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[4]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[5]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[6]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[7]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[8]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WSTRB[9]) = (100:100:100, 100:100:100); + (MAXIGP0ACLK => MAXIGP0WVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARID[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARLOCK) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1ARVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWID[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWLOCK) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1AWVALID) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1BREADY) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1RREADY) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[100]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[101]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[102]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[103]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[104]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[105]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[106]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[107]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[108]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[109]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[110]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[111]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[112]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[113]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[114]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[115]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[116]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[117]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[118]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[119]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[120]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[121]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[122]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[123]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[124]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[125]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[126]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[127]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[16]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[17]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[18]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[19]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[20]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[21]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[22]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[23]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[24]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[25]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[26]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[27]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[28]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[29]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[30]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[31]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[32]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[33]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[34]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[35]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[36]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[37]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[38]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[39]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[40]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[41]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[42]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[43]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[44]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[45]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[46]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[47]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[48]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[49]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[50]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[51]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[52]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[53]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[54]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[55]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[56]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[57]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[58]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[59]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[60]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[61]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[62]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[63]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[64]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[65]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[66]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[67]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[68]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[69]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[70]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[71]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[72]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[73]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[74]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[75]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[76]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[77]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[78]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[79]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[80]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[81]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[82]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[83]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[84]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[85]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[86]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[87]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[88]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[89]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[90]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[91]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[92]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[93]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[94]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[95]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[96]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[97]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[98]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[99]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WDATA[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WLAST) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[0]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[10]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[11]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[12]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[13]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[14]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[15]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[1]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[2]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[3]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[4]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[5]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[6]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[7]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[8]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WSTRB[9]) = (100:100:100, 100:100:100); + (MAXIGP1ACLK => MAXIGP1WVALID) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARID[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARLOCK) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2ARVALID) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[16]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[17]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[18]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[19]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[20]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[21]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[22]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[23]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[24]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[25]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[26]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[27]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[28]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[29]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[30]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[31]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[32]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[33]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[34]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[35]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[36]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[37]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[38]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[39]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWADDR[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWBURST[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWBURST[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWCACHE[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWCACHE[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWCACHE[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWCACHE[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWID[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLEN[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWLOCK) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWPROT[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWPROT[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWPROT[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWQOS[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWQOS[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWQOS[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWQOS[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWSIZE[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWSIZE[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWSIZE[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWUSER[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2AWVALID) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2BREADY) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2RREADY) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[100]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[101]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[102]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[103]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[104]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[105]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[106]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[107]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[108]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[109]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[110]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[111]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[112]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[113]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[114]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[115]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[116]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[117]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[118]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[119]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[120]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[121]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[122]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[123]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[124]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[125]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[126]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[127]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[16]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[17]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[18]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[19]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[20]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[21]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[22]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[23]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[24]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[25]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[26]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[27]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[28]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[29]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[30]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[31]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[32]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[33]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[34]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[35]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[36]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[37]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[38]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[39]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[40]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[41]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[42]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[43]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[44]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[45]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[46]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[47]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[48]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[49]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[50]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[51]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[52]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[53]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[54]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[55]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[56]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[57]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[58]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[59]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[60]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[61]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[62]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[63]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[64]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[65]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[66]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[67]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[68]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[69]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[70]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[71]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[72]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[73]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[74]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[75]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[76]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[77]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[78]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[79]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[80]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[81]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[82]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[83]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[84]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[85]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[86]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[87]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[88]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[89]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[90]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[91]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[92]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[93]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[94]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[95]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[96]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[97]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[98]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[99]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WDATA[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WLAST) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[0]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[10]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[11]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[12]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[13]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[14]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[15]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[1]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[2]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[3]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[4]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[5]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[6]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[7]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[8]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WSTRB[9]) = (100:100:100, 100:100:100); + (MAXIGP2ACLK => MAXIGP2WVALID) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[10]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[11]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[12]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[13]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[14]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[15]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[16]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[17]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[18]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[19]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[20]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[21]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[22]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[23]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[24]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[25]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[26]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[27]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[28]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[29]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[30]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[31]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[32]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[33]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[34]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[35]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[36]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[37]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[38]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[39]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[40]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[41]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[42]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[43]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[4]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[5]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[6]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[7]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[8]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACADDR[9]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACPROT[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACPROT[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACPROT[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACSNOOP[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACSNOOP[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACSNOOP[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACSNOOP[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDACVALID) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDARREADY) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDAWREADY) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[4]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBID[5]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBRESP[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBRESP[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDBVALID) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDCDREADY) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDCRREADY) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[100]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[101]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[102]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[103]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[104]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[105]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[106]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[107]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[108]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[109]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[10]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[110]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[111]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[112]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[113]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[114]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[115]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[116]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[117]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[118]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[119]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[11]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[120]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[121]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[122]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[123]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[124]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[125]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[126]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[127]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[12]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[13]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[14]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[15]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[16]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[17]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[18]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[19]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[20]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[21]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[22]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[23]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[24]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[25]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[26]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[27]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[28]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[29]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[30]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[31]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[32]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[33]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[34]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[35]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[36]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[37]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[38]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[39]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[40]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[41]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[42]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[43]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[44]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[45]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[46]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[47]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[48]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[49]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[4]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[50]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[51]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[52]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[53]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[54]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[55]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[56]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[57]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[58]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[59]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[5]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[60]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[61]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[62]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[63]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[64]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[65]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[66]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[67]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[68]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[69]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[6]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[70]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[71]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[72]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[73]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[74]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[75]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[76]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[77]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[78]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[79]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[7]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[80]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[81]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[82]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[83]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[84]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[85]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[86]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[87]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[88]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[89]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[8]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[90]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[91]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[92]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[93]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[94]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[95]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[96]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[97]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[98]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[99]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRDATA[9]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[4]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRID[5]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRLAST) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRRESP[0]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRRESP[1]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRRESP[2]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRRESP[3]) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDRVALID) = (100:100:100, 100:100:100); + (PLACECLK => SACEFPDWREADY) = (100:100:100, 100:100:100); + (PLPSTRACECLK => PSPLTRACECTL) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[0]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[10]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[11]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[12]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[13]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[14]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[15]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[16]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[17]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[18]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[19]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[1]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[20]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[21]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[22]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[23]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[24]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[25]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[26]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[27]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[28]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[29]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[2]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[30]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[31]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[3]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[4]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[5]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[6]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[7]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[8]) = (0:0:0, 0:0:0); + (PLPSTRACECLK => PSPLTRACEDATA[9]) = (0:0:0, 0:0:0); + (SAXIACPACLK => SAXIACPARREADY) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPAWREADY) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[3]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBID[4]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBRESP[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBRESP[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPBVALID) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[100]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[101]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[102]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[103]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[104]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[105]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[106]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[107]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[108]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[109]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[10]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[110]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[111]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[112]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[113]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[114]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[115]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[116]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[117]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[118]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[119]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[11]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[120]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[121]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[122]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[123]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[124]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[125]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[126]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[127]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[12]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[13]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[14]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[15]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[16]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[17]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[18]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[19]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[20]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[21]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[22]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[23]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[24]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[25]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[26]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[27]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[28]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[29]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[30]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[31]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[32]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[33]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[34]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[35]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[36]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[37]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[38]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[39]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[3]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[40]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[41]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[42]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[43]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[44]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[45]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[46]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[47]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[48]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[49]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[4]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[50]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[51]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[52]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[53]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[54]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[55]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[56]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[57]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[58]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[59]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[5]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[60]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[61]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[62]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[63]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[64]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[65]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[66]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[67]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[68]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[69]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[6]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[70]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[71]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[72]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[73]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[74]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[75]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[76]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[77]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[78]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[79]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[7]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[80]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[81]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[82]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[83]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[84]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[85]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[86]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[87]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[88]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[89]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[8]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[90]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[91]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[92]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[93]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[94]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[95]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[96]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[97]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[98]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[99]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRDATA[9]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[2]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[3]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRID[4]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRLAST) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRRESP[0]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRRESP[1]) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPRVALID) = (100:100:100, 100:100:100); + (SAXIACPACLK => SAXIACPWREADY) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0ARREADY) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[0]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[1]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[2]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[3]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[4]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RID[5]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RLAST) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP0RCLK => SAXIGP0RVALID) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0AWREADY) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[0]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[1]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[2]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[3]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[4]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BID[5]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0BVALID) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP0WCLK => SAXIGP0WREADY) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1ARREADY) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[0]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[1]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[2]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[3]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[4]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RID[5]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RLAST) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP1RCLK => SAXIGP1RVALID) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1AWREADY) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[0]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[1]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[2]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[3]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[4]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BID[5]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1BVALID) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP1WCLK => SAXIGP1WREADY) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2ARREADY) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[0]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[1]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[2]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[3]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[4]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RID[5]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RLAST) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP2RCLK => SAXIGP2RVALID) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2AWREADY) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[0]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[1]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[2]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[3]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[4]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BID[5]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2BVALID) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP2WCLK => SAXIGP2WREADY) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3ARREADY) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[0]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[1]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[2]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[3]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[4]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RID[5]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RLAST) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP3RCLK => SAXIGP3RVALID) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3AWREADY) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[0]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[1]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[2]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[3]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[4]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BID[5]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3BVALID) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP3WCLK => SAXIGP3WREADY) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4ARREADY) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[0]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[1]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[2]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[3]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[4]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RID[5]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RLAST) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP4RCLK => SAXIGP4RVALID) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4AWREADY) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[0]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[1]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[2]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[3]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[4]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BID[5]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4BVALID) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP4WCLK => SAXIGP4WREADY) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5ARREADY) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[0]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[1]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[2]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[3]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[4]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RID[5]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RLAST) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP5RCLK => SAXIGP5RVALID) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5AWREADY) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[0]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[1]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[2]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[3]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[4]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BID[5]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5BVALID) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP5WCLK => SAXIGP5WREADY) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6ARREADY) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[0]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[100]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[101]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[102]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[103]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[104]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[105]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[106]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[107]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[108]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[109]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[10]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[110]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[111]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[112]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[113]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[114]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[115]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[116]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[117]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[118]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[119]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[11]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[120]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[121]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[122]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[123]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[124]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[125]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[126]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[127]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[12]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[13]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[14]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[15]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[16]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[17]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[18]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[19]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[1]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[20]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[21]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[22]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[23]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[24]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[25]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[26]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[27]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[28]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[29]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[2]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[30]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[31]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[32]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[33]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[34]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[35]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[36]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[37]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[38]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[39]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[3]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[40]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[41]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[42]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[43]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[44]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[45]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[46]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[47]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[48]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[49]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[4]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[50]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[51]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[52]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[53]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[54]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[55]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[56]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[57]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[58]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[59]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[5]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[60]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[61]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[62]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[63]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[64]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[65]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[66]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[67]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[68]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[69]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[6]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[70]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[71]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[72]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[73]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[74]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[75]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[76]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[77]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[78]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[79]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[7]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[80]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[81]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[82]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[83]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[84]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[85]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[86]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[87]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[88]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[89]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[8]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[90]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[91]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[92]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[93]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[94]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[95]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[96]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[97]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[98]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[99]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RDATA[9]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[0]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[1]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[2]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[3]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[4]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RID[5]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RLAST) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP6RCLK => SAXIGP6RVALID) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6AWREADY) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[0]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[1]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[2]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[3]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[4]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BID[5]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BRESP[0]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BRESP[1]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6BVALID) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WACOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WACOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WACOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WACOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[0]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[1]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[2]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[3]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[4]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[5]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[6]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WCOUNT[7]) = (100:100:100, 100:100:100); + (SAXIGP6WCLK => SAXIGP6WREADY) = (100:100:100, 100:100:100); + // (EMIOENET0MDIOMDC => EMIOENET0MDIOO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET0MDIOMDC => EMIOENET0MDIOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET1MDIOMDC => EMIOENET1MDIOO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET1MDIOMDC => EMIOENET1MDIOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET2MDIOMDC => EMIOENET2MDIOO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET2MDIOMDC => EMIOENET2MDIOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET3MDIOMDC => EMIOENET3MDIOO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOENET3MDIOMDC => EMIOENET3MDIOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0CMDENA) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0CMDOUT) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[3]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[4]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[5]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[6]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAENA[7]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[3]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[4]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[5]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[6]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO0CLKOUT => EMIOSDIO0DATAOUT[7]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1CMDENA) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1CMDOUT) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[3]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[4]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[5]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[6]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAENA[7]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[3]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[4]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[5]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[6]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSDIO1CLKOUT => EMIOSDIO1DATAOUT[7]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0MO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0MOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0SCLKTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0SSNTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0SSON[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0SSON[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0SSON[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI0SCLKO => EMIOSPI0STN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1MO) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1MOTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1SCLKTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1SSNTN) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1SSON[0]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1SSON[1]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1SSON[2]) = (0:0:0, 0:0:0); // error prop output to output + // (EMIOSPI1SCLKO => EMIOSPI1STN) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge ADMAFCICLK[0], 0:0:0, notifier); + $period (negedge ADMAFCICLK[1], 0:0:0, notifier); + $period (negedge ADMAFCICLK[2], 0:0:0, notifier); + $period (negedge ADMAFCICLK[3], 0:0:0, notifier); + $period (negedge ADMAFCICLK[4], 0:0:0, notifier); + $period (negedge ADMAFCICLK[5], 0:0:0, notifier); + $period (negedge ADMAFCICLK[6], 0:0:0, notifier); + $period (negedge ADMAFCICLK[7], 0:0:0, notifier); + $period (negedge DDRCREFRESHPLCLK, 0:0:0, notifier); + $period (negedge DPSAXISAUDIOCLK, 0:0:0, notifier); + $period (negedge DPVIDEOINCLK, 0:0:0, notifier); + $period (negedge EMIOENET0GMIIRXCLK, 0:0:0, notifier); + $period (negedge EMIOENET0GMIITXCLK, 0:0:0, notifier); + $period (negedge EMIOENET0MDIOMDC, 0:0:0, notifier); + $period (negedge EMIOENET1GMIIRXCLK, 0:0:0, notifier); + $period (negedge EMIOENET1GMIITXCLK, 0:0:0, notifier); + $period (negedge EMIOENET1MDIOMDC, 0:0:0, notifier); + $period (negedge EMIOENET2GMIIRXCLK, 0:0:0, notifier); + $period (negedge EMIOENET2GMIITXCLK, 0:0:0, notifier); + $period (negedge EMIOENET2MDIOMDC, 0:0:0, notifier); + $period (negedge EMIOENET3GMIIRXCLK, 0:0:0, notifier); + $period (negedge EMIOENET3GMIITXCLK, 0:0:0, notifier); + $period (negedge EMIOENET3MDIOMDC, 0:0:0, notifier); + $period (negedge EMIOENETTSUCLK, 0:0:0, notifier); + $period (negedge EMIOSDIO0CLKOUT, 0:0:0, notifier); + $period (negedge EMIOSDIO0FBCLKIN, 0:0:0, notifier); + $period (negedge EMIOSDIO1CLKOUT, 0:0:0, notifier); + $period (negedge EMIOSDIO1FBCLKIN, 0:0:0, notifier); + $period (negedge EMIOSPI0SCLKI, 0:0:0, notifier); + $period (negedge EMIOSPI0SCLKO, 0:0:0, notifier); + $period (negedge EMIOSPI1SCLKI, 0:0:0, notifier); + $period (negedge EMIOSPI1SCLKO, 0:0:0, notifier); + $period (negedge EMIOTTC0CLKI[0], 0:0:0, notifier); + $period (negedge EMIOTTC0CLKI[1], 0:0:0, notifier); + $period (negedge EMIOTTC0CLKI[2], 0:0:0, notifier); + $period (negedge EMIOTTC1CLKI[0], 0:0:0, notifier); + $period (negedge EMIOTTC1CLKI[1], 0:0:0, notifier); + $period (negedge EMIOTTC1CLKI[2], 0:0:0, notifier); + $period (negedge EMIOTTC2CLKI[0], 0:0:0, notifier); + $period (negedge EMIOTTC2CLKI[1], 0:0:0, notifier); + $period (negedge EMIOTTC2CLKI[2], 0:0:0, notifier); + $period (negedge EMIOTTC3CLKI[0], 0:0:0, notifier); + $period (negedge EMIOTTC3CLKI[1], 0:0:0, notifier); + $period (negedge EMIOTTC3CLKI[2], 0:0:0, notifier); + $period (negedge EMIOWDT0CLKI, 0:0:0, notifier); + $period (negedge EMIOWDT1CLKI, 0:0:0, notifier); + $period (negedge FMIOGEM0FIFORXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM0FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM1FIFORXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM1FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM2FIFORXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM2FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM3FIFORXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEM3FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (negedge FMIOGEMTSUCLKFROMPL, 0:0:0, notifier); + $period (negedge GDMAFCICLK[0], 0:0:0, notifier); + $period (negedge GDMAFCICLK[1], 0:0:0, notifier); + $period (negedge GDMAFCICLK[2], 0:0:0, notifier); + $period (negedge GDMAFCICLK[3], 0:0:0, notifier); + $period (negedge GDMAFCICLK[4], 0:0:0, notifier); + $period (negedge GDMAFCICLK[5], 0:0:0, notifier); + $period (negedge GDMAFCICLK[6], 0:0:0, notifier); + $period (negedge GDMAFCICLK[7], 0:0:0, notifier); + $period (negedge MAXIGP0ACLK, 0:0:0, notifier); + $period (negedge MAXIGP1ACLK, 0:0:0, notifier); + $period (negedge MAXIGP2ACLK, 0:0:0, notifier); + $period (negedge PLACECLK, 0:0:0, notifier); + $period (negedge PLLAUXREFCLKFPD[0], 0:0:0, notifier); + $period (negedge PLLAUXREFCLKFPD[1], 0:0:0, notifier); + $period (negedge PLLAUXREFCLKFPD[2], 0:0:0, notifier); + $period (negedge PLLAUXREFCLKLPD[0], 0:0:0, notifier); + $period (negedge PLLAUXREFCLKLPD[1], 0:0:0, notifier); + $period (negedge PLPSTRACECLK, 0:0:0, notifier); + $period (negedge SAXIACPACLK, 0:0:0, notifier); + $period (negedge SAXIGP0RCLK, 0:0:0, notifier); + $period (negedge SAXIGP0WCLK, 0:0:0, notifier); + $period (negedge SAXIGP1RCLK, 0:0:0, notifier); + $period (negedge SAXIGP1WCLK, 0:0:0, notifier); + $period (negedge SAXIGP2RCLK, 0:0:0, notifier); + $period (negedge SAXIGP2WCLK, 0:0:0, notifier); + $period (negedge SAXIGP3RCLK, 0:0:0, notifier); + $period (negedge SAXIGP3WCLK, 0:0:0, notifier); + $period (negedge SAXIGP4RCLK, 0:0:0, notifier); + $period (negedge SAXIGP4WCLK, 0:0:0, notifier); + $period (negedge SAXIGP5RCLK, 0:0:0, notifier); + $period (negedge SAXIGP5WCLK, 0:0:0, notifier); + $period (negedge SAXIGP6RCLK, 0:0:0, notifier); + $period (negedge SAXIGP6WCLK, 0:0:0, notifier); + $period (posedge ADMAFCICLK[0], 0:0:0, notifier); + $period (posedge ADMAFCICLK[1], 0:0:0, notifier); + $period (posedge ADMAFCICLK[2], 0:0:0, notifier); + $period (posedge ADMAFCICLK[3], 0:0:0, notifier); + $period (posedge ADMAFCICLK[4], 0:0:0, notifier); + $period (posedge ADMAFCICLK[5], 0:0:0, notifier); + $period (posedge ADMAFCICLK[6], 0:0:0, notifier); + $period (posedge ADMAFCICLK[7], 0:0:0, notifier); + $period (posedge DDRCREFRESHPLCLK, 0:0:0, notifier); + $period (posedge DPSAXISAUDIOCLK, 0:0:0, notifier); + $period (posedge DPVIDEOINCLK, 0:0:0, notifier); + $period (posedge EMIOENET0GMIIRXCLK, 0:0:0, notifier); + $period (posedge EMIOENET0GMIITXCLK, 0:0:0, notifier); + $period (posedge EMIOENET0MDIOMDC, 0:0:0, notifier); + $period (posedge EMIOENET1GMIIRXCLK, 0:0:0, notifier); + $period (posedge EMIOENET1GMIITXCLK, 0:0:0, notifier); + $period (posedge EMIOENET1MDIOMDC, 0:0:0, notifier); + $period (posedge EMIOENET2GMIIRXCLK, 0:0:0, notifier); + $period (posedge EMIOENET2GMIITXCLK, 0:0:0, notifier); + $period (posedge EMIOENET2MDIOMDC, 0:0:0, notifier); + $period (posedge EMIOENET3GMIIRXCLK, 0:0:0, notifier); + $period (posedge EMIOENET3GMIITXCLK, 0:0:0, notifier); + $period (posedge EMIOENET3MDIOMDC, 0:0:0, notifier); + $period (posedge EMIOENETTSUCLK, 0:0:0, notifier); + $period (posedge EMIOSDIO0CLKOUT, 0:0:0, notifier); + $period (posedge EMIOSDIO0FBCLKIN, 0:0:0, notifier); + $period (posedge EMIOSDIO1CLKOUT, 0:0:0, notifier); + $period (posedge EMIOSDIO1FBCLKIN, 0:0:0, notifier); + $period (posedge EMIOSPI0SCLKI, 0:0:0, notifier); + $period (posedge EMIOSPI0SCLKO, 0:0:0, notifier); + $period (posedge EMIOSPI1SCLKI, 0:0:0, notifier); + $period (posedge EMIOSPI1SCLKO, 0:0:0, notifier); + $period (posedge EMIOTTC0CLKI[0], 0:0:0, notifier); + $period (posedge EMIOTTC0CLKI[1], 0:0:0, notifier); + $period (posedge EMIOTTC0CLKI[2], 0:0:0, notifier); + $period (posedge EMIOTTC1CLKI[0], 0:0:0, notifier); + $period (posedge EMIOTTC1CLKI[1], 0:0:0, notifier); + $period (posedge EMIOTTC1CLKI[2], 0:0:0, notifier); + $period (posedge EMIOTTC2CLKI[0], 0:0:0, notifier); + $period (posedge EMIOTTC2CLKI[1], 0:0:0, notifier); + $period (posedge EMIOTTC2CLKI[2], 0:0:0, notifier); + $period (posedge EMIOTTC3CLKI[0], 0:0:0, notifier); + $period (posedge EMIOTTC3CLKI[1], 0:0:0, notifier); + $period (posedge EMIOTTC3CLKI[2], 0:0:0, notifier); + $period (posedge EMIOWDT0CLKI, 0:0:0, notifier); + $period (posedge EMIOWDT1CLKI, 0:0:0, notifier); + $period (posedge FMIOGEM0FIFORXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM0FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM1FIFORXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM1FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM2FIFORXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM2FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM3FIFORXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEM3FIFOTXCLKFROMPL, 0:0:0, notifier); + $period (posedge FMIOGEMTSUCLKFROMPL, 0:0:0, notifier); + $period (posedge GDMAFCICLK[0], 0:0:0, notifier); + $period (posedge GDMAFCICLK[1], 0:0:0, notifier); + $period (posedge GDMAFCICLK[2], 0:0:0, notifier); + $period (posedge GDMAFCICLK[3], 0:0:0, notifier); + $period (posedge GDMAFCICLK[4], 0:0:0, notifier); + $period (posedge GDMAFCICLK[5], 0:0:0, notifier); + $period (posedge GDMAFCICLK[6], 0:0:0, notifier); + $period (posedge GDMAFCICLK[7], 0:0:0, notifier); + $period (posedge MAXIGP0ACLK, 0:0:0, notifier); + $period (posedge MAXIGP1ACLK, 0:0:0, notifier); + $period (posedge MAXIGP2ACLK, 0:0:0, notifier); + $period (posedge PLACECLK, 0:0:0, notifier); + $period (posedge PLLAUXREFCLKFPD[0], 0:0:0, notifier); + $period (posedge PLLAUXREFCLKFPD[1], 0:0:0, notifier); + $period (posedge PLLAUXREFCLKFPD[2], 0:0:0, notifier); + $period (posedge PLLAUXREFCLKLPD[0], 0:0:0, notifier); + $period (posedge PLLAUXREFCLKLPD[1], 0:0:0, notifier); + $period (posedge PLPSTRACECLK, 0:0:0, notifier); + $period (posedge SAXIACPACLK, 0:0:0, notifier); + $period (posedge SAXIGP0RCLK, 0:0:0, notifier); + $period (posedge SAXIGP0WCLK, 0:0:0, notifier); + $period (posedge SAXIGP1RCLK, 0:0:0, notifier); + $period (posedge SAXIGP1WCLK, 0:0:0, notifier); + $period (posedge SAXIGP2RCLK, 0:0:0, notifier); + $period (posedge SAXIGP2WCLK, 0:0:0, notifier); + $period (posedge SAXIGP3RCLK, 0:0:0, notifier); + $period (posedge SAXIGP3WCLK, 0:0:0, notifier); + $period (posedge SAXIGP4RCLK, 0:0:0, notifier); + $period (posedge SAXIGP4WCLK, 0:0:0, notifier); + $period (posedge SAXIGP5RCLK, 0:0:0, notifier); + $period (posedge SAXIGP5WCLK, 0:0:0, notifier); + $period (posedge SAXIGP6RCLK, 0:0:0, notifier); + $period (posedge SAXIGP6WCLK, 0:0:0, notifier); + $setuphold (posedge ADMAFCICLK[0], negedge PL2ADMACVLD[0], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[0], PL2ADMACVLD_delay[0]); + $setuphold (posedge ADMAFCICLK[0], negedge PL2ADMATACK[0], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[0], PL2ADMATACK_delay[0]); + $setuphold (posedge ADMAFCICLK[0], posedge PL2ADMACVLD[0], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[0], PL2ADMACVLD_delay[0]); + $setuphold (posedge ADMAFCICLK[0], posedge PL2ADMATACK[0], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[0], PL2ADMATACK_delay[0]); + $setuphold (posedge ADMAFCICLK[1], negedge PL2ADMACVLD[1], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[1], PL2ADMACVLD_delay[1]); + $setuphold (posedge ADMAFCICLK[1], negedge PL2ADMATACK[1], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[1], PL2ADMATACK_delay[1]); + $setuphold (posedge ADMAFCICLK[1], posedge PL2ADMACVLD[1], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[1], PL2ADMACVLD_delay[1]); + $setuphold (posedge ADMAFCICLK[1], posedge PL2ADMATACK[1], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[1], PL2ADMATACK_delay[1]); + $setuphold (posedge ADMAFCICLK[2], negedge PL2ADMACVLD[2], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[2], PL2ADMACVLD_delay[2]); + $setuphold (posedge ADMAFCICLK[2], negedge PL2ADMATACK[2], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[2], PL2ADMATACK_delay[2]); + $setuphold (posedge ADMAFCICLK[2], posedge PL2ADMACVLD[2], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[2], PL2ADMACVLD_delay[2]); + $setuphold (posedge ADMAFCICLK[2], posedge PL2ADMATACK[2], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[2], PL2ADMATACK_delay[2]); + $setuphold (posedge ADMAFCICLK[3], negedge PL2ADMACVLD[3], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[3], PL2ADMACVLD_delay[3]); + $setuphold (posedge ADMAFCICLK[3], negedge PL2ADMATACK[3], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[3], PL2ADMATACK_delay[3]); + $setuphold (posedge ADMAFCICLK[3], posedge PL2ADMACVLD[3], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[3], PL2ADMACVLD_delay[3]); + $setuphold (posedge ADMAFCICLK[3], posedge PL2ADMATACK[3], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[3], PL2ADMATACK_delay[3]); + $setuphold (posedge ADMAFCICLK[4], negedge PL2ADMACVLD[4], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[4], PL2ADMACVLD_delay[4]); + $setuphold (posedge ADMAFCICLK[4], negedge PL2ADMATACK[4], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[4], PL2ADMATACK_delay[4]); + $setuphold (posedge ADMAFCICLK[4], posedge PL2ADMACVLD[4], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[4], PL2ADMACVLD_delay[4]); + $setuphold (posedge ADMAFCICLK[4], posedge PL2ADMATACK[4], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[4], PL2ADMATACK_delay[4]); + $setuphold (posedge ADMAFCICLK[5], negedge PL2ADMACVLD[5], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[5], PL2ADMACVLD_delay[5]); + $setuphold (posedge ADMAFCICLK[5], negedge PL2ADMATACK[5], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[5], PL2ADMATACK_delay[5]); + $setuphold (posedge ADMAFCICLK[5], posedge PL2ADMACVLD[5], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[5], PL2ADMACVLD_delay[5]); + $setuphold (posedge ADMAFCICLK[5], posedge PL2ADMATACK[5], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[5], PL2ADMATACK_delay[5]); + $setuphold (posedge ADMAFCICLK[6], negedge PL2ADMACVLD[6], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[6], PL2ADMACVLD_delay[6]); + $setuphold (posedge ADMAFCICLK[6], negedge PL2ADMATACK[6], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[6], PL2ADMATACK_delay[6]); + $setuphold (posedge ADMAFCICLK[6], posedge PL2ADMACVLD[6], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[6], PL2ADMACVLD_delay[6]); + $setuphold (posedge ADMAFCICLK[6], posedge PL2ADMATACK[6], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[6], PL2ADMATACK_delay[6]); + $setuphold (posedge ADMAFCICLK[7], negedge PL2ADMACVLD[7], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[7], PL2ADMACVLD_delay[7]); + $setuphold (posedge ADMAFCICLK[7], negedge PL2ADMATACK[7], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[7], PL2ADMATACK_delay[7]); + $setuphold (posedge ADMAFCICLK[7], posedge PL2ADMACVLD[7], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[7], PL2ADMACVLD_delay[7]); + $setuphold (posedge ADMAFCICLK[7], posedge PL2ADMATACK[7], 0:0:0, 0:0:0, notifier, , , ADMAFCICLK_delay[7], PL2ADMATACK_delay[7]); + $setuphold (posedge DDRCREFRESHPLCLK, negedge DDRCEXTREFRESHRANK0REQ, 0:0:0, 0:0:0, notifier, , , DDRCREFRESHPLCLK_delay, DDRCEXTREFRESHRANK0REQ_delay); + $setuphold (posedge DDRCREFRESHPLCLK, negedge DDRCEXTREFRESHRANK1REQ, 0:0:0, 0:0:0, notifier, , , DDRCREFRESHPLCLK_delay, DDRCEXTREFRESHRANK1REQ_delay); + $setuphold (posedge DDRCREFRESHPLCLK, posedge DDRCEXTREFRESHRANK0REQ, 0:0:0, 0:0:0, notifier, , , DDRCREFRESHPLCLK_delay, DDRCEXTREFRESHRANK0REQ_delay); + $setuphold (posedge DDRCREFRESHPLCLK, posedge DDRCEXTREFRESHRANK1REQ, 0:0:0, 0:0:0, notifier, , , DDRCREFRESHPLCLK_delay, DDRCEXTREFRESHRANK1REQ_delay); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPMAXISMIXEDAUDIOTREADY, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPMAXISMIXEDAUDIOTREADY_delay); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[0], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[0]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[10], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[10]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[11], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[11]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[12], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[12]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[13], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[13]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[14], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[14]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[15], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[15]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[16], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[16]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[17], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[17]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[18], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[18]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[19], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[19]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[1], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[1]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[20], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[20]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[21], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[21]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[22], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[22]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[23], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[23]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[24], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[24]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[25], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[25]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[26], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[26]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[27], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[27]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[28], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[28]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[29], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[29]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[2], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[2]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[30], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[30]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[31], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[31]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[3], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[3]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[4], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[4]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[5], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[5]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[6], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[6]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[7], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[7]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[8], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[8]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTDATA[9], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[9]); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTID, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTID_delay); + $setuphold (posedge DPSAXISAUDIOCLK, negedge DPSAXISAUDIOTVALID, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTVALID_delay); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPMAXISMIXEDAUDIOTREADY, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPMAXISMIXEDAUDIOTREADY_delay); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[0], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[0]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[10], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[10]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[11], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[11]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[12], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[12]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[13], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[13]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[14], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[14]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[15], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[15]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[16], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[16]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[17], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[17]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[18], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[18]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[19], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[19]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[1], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[1]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[20], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[20]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[21], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[21]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[22], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[22]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[23], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[23]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[24], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[24]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[25], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[25]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[26], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[26]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[27], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[27]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[28], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[28]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[29], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[29]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[2], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[2]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[30], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[30]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[31], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[31]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[3], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[3]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[4], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[4]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[5], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[5]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[6], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[6]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[7], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[7]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[8], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[8]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTDATA[9], 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTDATA_delay[9]); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTID, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTID_delay); + $setuphold (posedge DPSAXISAUDIOCLK, posedge DPSAXISAUDIOTVALID, 0:0:0, 0:0:0, notifier, , , DPSAXISAUDIOCLK_delay, DPSAXISAUDIOTVALID_delay); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[0]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[1]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[2]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[3]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[4]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[5]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[6]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXALPHAIN[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[7]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[0]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[10], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[10]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[11], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[11]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[12], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[12]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[13], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[13]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[14], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[14]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[15], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[15]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[16], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[16]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[17], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[17]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[18], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[18]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[19], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[19]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[1]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[20], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[20]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[21], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[21]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[22], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[22]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[23], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[23]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[24], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[24]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[25], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[25]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[26], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[26]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[27], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[27]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[28], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[28]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[29], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[29]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[2]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[30], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[30]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[31], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[31]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[32], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[32]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[33], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[33]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[34], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[34]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[35], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[35]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[3]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[4]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[5]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[6]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[7]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[8], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[8]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEGFXPIXEL1IN[9], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[9]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINDE, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINDE_delay); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINHSYNC, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINHSYNC_delay); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[0]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[10], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[10]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[11], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[11]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[12], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[12]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[13], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[13]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[14], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[14]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[15], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[15]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[16], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[16]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[17], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[17]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[18], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[18]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[19], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[19]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[1]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[20], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[20]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[21], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[21]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[22], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[22]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[23], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[23]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[24], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[24]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[25], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[25]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[26], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[26]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[27], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[27]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[28], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[28]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[29], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[29]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[2]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[30], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[30]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[31], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[31]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[32], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[32]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[33], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[33]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[34], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[34]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[35], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[35]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[3]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[4]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[5]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[6]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[7]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[8], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[8]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINPIXEL1[9], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[9]); + $setuphold (posedge DPVIDEOINCLK, negedge DPLIVEVIDEOINVSYNC, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINVSYNC_delay); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[0]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[1]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[2]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[3]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[4]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[5]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[6]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXALPHAIN[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXALPHAIN_delay[7]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[0]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[10], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[10]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[11], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[11]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[12], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[12]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[13], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[13]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[14], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[14]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[15], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[15]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[16], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[16]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[17], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[17]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[18], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[18]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[19], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[19]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[1]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[20], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[20]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[21], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[21]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[22], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[22]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[23], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[23]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[24], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[24]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[25], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[25]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[26], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[26]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[27], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[27]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[28], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[28]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[29], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[29]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[2]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[30], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[30]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[31], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[31]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[32], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[32]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[33], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[33]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[34], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[34]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[35], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[35]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[3]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[4]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[5]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[6]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[7]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[8], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[8]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEGFXPIXEL1IN[9], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEGFXPIXEL1IN_delay[9]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINDE, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINDE_delay); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINHSYNC, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINHSYNC_delay); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[0], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[0]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[10], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[10]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[11], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[11]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[12], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[12]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[13], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[13]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[14], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[14]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[15], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[15]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[16], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[16]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[17], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[17]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[18], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[18]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[19], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[19]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[1], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[1]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[20], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[20]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[21], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[21]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[22], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[22]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[23], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[23]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[24], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[24]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[25], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[25]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[26], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[26]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[27], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[27]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[28], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[28]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[29], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[29]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[2], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[2]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[30], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[30]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[31], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[31]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[32], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[32]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[33], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[33]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[34], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[34]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[35], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[35]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[3], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[3]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[4], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[4]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[5], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[5]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[6], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[6]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[7], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[7]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[8], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[8]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINPIXEL1[9], 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINPIXEL1_delay[9]); + $setuphold (posedge DPVIDEOINCLK, posedge DPLIVEVIDEOINVSYNC, 0:0:0, 0:0:0, notifier, , , DPVIDEOINCLK_delay, DPLIVEVIDEOINVSYNC_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXDV_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET0GMIIRXCLK, negedge EMIOENET0GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXER_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXDV_delay); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET0GMIIRXCLK, posedge EMIOENET0GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET0GMIIRXCLK_delay, EMIOENET0GMIIRXER_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXDV_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET1GMIIRXCLK, negedge EMIOENET1GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXER_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXDV_delay); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET1GMIIRXCLK, posedge EMIOENET1GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET1GMIIRXCLK_delay, EMIOENET1GMIIRXER_delay); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXDV_delay); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET2GMIIRXCLK, negedge EMIOENET2GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXER_delay); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXDV_delay); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET2GMIIRXCLK, posedge EMIOENET2GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET2GMIIRXCLK_delay, EMIOENET2GMIIRXER_delay); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXDV_delay); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET3GMIIRXCLK, negedge EMIOENET3GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXER_delay); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXDV, 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXDV_delay); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[0], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[0]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[1], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[1]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[2], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[2]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[3], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[3]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[4], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[4]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[5], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[5]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[6], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[6]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXD[7], 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXD_delay[7]); + $setuphold (posedge EMIOENET3GMIIRXCLK, posedge EMIOENET3GMIIRXER, 0:0:0, 0:0:0, notifier, , , EMIOENET3GMIIRXCLK_delay, EMIOENET3GMIIRXER_delay); + $setuphold (posedge EMIOSPI0SCLKI, negedge EMIOSPI0SSIN, 0:0:0, 0:0:0, notifier, , , EMIOSPI0SCLKI_delay, EMIOSPI0SSIN_delay); + $setuphold (posedge EMIOSPI0SCLKI, posedge EMIOSPI0SSIN, 0:0:0, 0:0:0, notifier, , , EMIOSPI0SCLKI_delay, EMIOSPI0SSIN_delay); + $setuphold (posedge EMIOSPI1SCLKI, negedge EMIOSPI1SSIN, 0:0:0, 0:0:0, notifier, , , EMIOSPI1SCLKI_delay, EMIOSPI1SSIN_delay); + $setuphold (posedge EMIOSPI1SCLKI, posedge EMIOSPI1SSIN, 0:0:0, 0:0:0, notifier, , , EMIOSPI1SCLKI_delay, EMIOSPI1SSIN_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRCONTROL_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATARDY_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXREOP_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRERR_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRSOP_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, negedge EMIOENET0TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRVALID_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRCONTROL_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATARDY_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXREOP_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRERR_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRSOP_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM0FIFOTXCLKFROMPL, posedge EMIOENET0TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM0FIFOTXCLKFROMPL_delay, EMIOENET0TXRVALID_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRCONTROL_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATARDY_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXREOP_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRERR_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRSOP_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, negedge EMIOENET1TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRVALID_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRCONTROL_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATARDY_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXREOP_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRERR_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRSOP_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM1FIFOTXCLKFROMPL, posedge EMIOENET1TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM1FIFOTXCLKFROMPL_delay, EMIOENET1TXRVALID_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRCONTROL_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATARDY_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXREOP_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRERR_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRSOP_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, negedge EMIOENET2TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRVALID_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRCONTROL_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATARDY_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXREOP_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRERR_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRSOP_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM2FIFOTXCLKFROMPL, posedge EMIOENET2TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM2FIFOTXCLKFROMPL_delay, EMIOENET2TXRVALID_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRCONTROL_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATARDY_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXREOP_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRERR_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRSOP_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, negedge EMIOENET3TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRVALID_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRCONTROL, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRCONTROL_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATARDY, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATARDY_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[0], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[0]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[1], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[1]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[2], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[2]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[3], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[3]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[4], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[4]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[5], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[5]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[6], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[6]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRDATA[7], 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRDATA_delay[7]); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXREOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXREOP_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRERR, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRERR_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRFLUSHED, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRFLUSHED_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRSOP, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRSOP_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRUNDERFLOW, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRUNDERFLOW_delay); + $setuphold (posedge FMIOGEM3FIFOTXCLKFROMPL, posedge EMIOENET3TXRVALID, 0:0:0, 0:0:0, notifier, , , FMIOGEM3FIFOTXCLKFROMPL_delay, EMIOENET3TXRVALID_delay); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM0TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM0TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM0TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM0TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM1TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM1TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM1TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM1TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM2TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM2TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM2TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM2TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM3TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM3TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, negedge EMIOGEM3TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM3TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM0TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM0TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM0TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM0TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM1TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM1TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM1TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM1TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM2TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM2TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM2TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM2TSUINCCTRL_delay[1]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM3TSUINCCTRL[0], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM3TSUINCCTRL_delay[0]); + $setuphold (posedge FMIOGEMTSUCLKFROMPL, posedge EMIOGEM3TSUINCCTRL[1], 0:0:0, 0:0:0, notifier, , , FMIOGEMTSUCLKFROMPL_delay, EMIOGEM3TSUINCCTRL_delay[1]); + $setuphold (posedge GDMAFCICLK[0], negedge PL2GDMACVLD[0], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[0], PL2GDMACVLD_delay[0]); + $setuphold (posedge GDMAFCICLK[0], negedge PL2GDMATACK[0], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[0], PL2GDMATACK_delay[0]); + $setuphold (posedge GDMAFCICLK[0], posedge PL2GDMACVLD[0], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[0], PL2GDMACVLD_delay[0]); + $setuphold (posedge GDMAFCICLK[0], posedge PL2GDMATACK[0], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[0], PL2GDMATACK_delay[0]); + $setuphold (posedge GDMAFCICLK[1], negedge PL2GDMACVLD[1], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[1], PL2GDMACVLD_delay[1]); + $setuphold (posedge GDMAFCICLK[1], negedge PL2GDMATACK[1], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[1], PL2GDMATACK_delay[1]); + $setuphold (posedge GDMAFCICLK[1], posedge PL2GDMACVLD[1], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[1], PL2GDMACVLD_delay[1]); + $setuphold (posedge GDMAFCICLK[1], posedge PL2GDMATACK[1], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[1], PL2GDMATACK_delay[1]); + $setuphold (posedge GDMAFCICLK[2], negedge PL2GDMACVLD[2], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[2], PL2GDMACVLD_delay[2]); + $setuphold (posedge GDMAFCICLK[2], negedge PL2GDMATACK[2], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[2], PL2GDMATACK_delay[2]); + $setuphold (posedge GDMAFCICLK[2], posedge PL2GDMACVLD[2], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[2], PL2GDMACVLD_delay[2]); + $setuphold (posedge GDMAFCICLK[2], posedge PL2GDMATACK[2], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[2], PL2GDMATACK_delay[2]); + $setuphold (posedge GDMAFCICLK[3], negedge PL2GDMACVLD[3], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[3], PL2GDMACVLD_delay[3]); + $setuphold (posedge GDMAFCICLK[3], negedge PL2GDMATACK[3], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[3], PL2GDMATACK_delay[3]); + $setuphold (posedge GDMAFCICLK[3], posedge PL2GDMACVLD[3], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[3], PL2GDMACVLD_delay[3]); + $setuphold (posedge GDMAFCICLK[3], posedge PL2GDMATACK[3], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[3], PL2GDMATACK_delay[3]); + $setuphold (posedge GDMAFCICLK[4], negedge PL2GDMACVLD[4], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[4], PL2GDMACVLD_delay[4]); + $setuphold (posedge GDMAFCICLK[4], negedge PL2GDMATACK[4], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[4], PL2GDMATACK_delay[4]); + $setuphold (posedge GDMAFCICLK[4], posedge PL2GDMACVLD[4], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[4], PL2GDMACVLD_delay[4]); + $setuphold (posedge GDMAFCICLK[4], posedge PL2GDMATACK[4], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[4], PL2GDMATACK_delay[4]); + $setuphold (posedge GDMAFCICLK[5], negedge PL2GDMACVLD[5], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[5], PL2GDMACVLD_delay[5]); + $setuphold (posedge GDMAFCICLK[5], negedge PL2GDMATACK[5], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[5], PL2GDMATACK_delay[5]); + $setuphold (posedge GDMAFCICLK[5], posedge PL2GDMACVLD[5], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[5], PL2GDMACVLD_delay[5]); + $setuphold (posedge GDMAFCICLK[5], posedge PL2GDMATACK[5], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[5], PL2GDMATACK_delay[5]); + $setuphold (posedge GDMAFCICLK[6], negedge PL2GDMACVLD[6], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[6], PL2GDMACVLD_delay[6]); + $setuphold (posedge GDMAFCICLK[6], negedge PL2GDMATACK[6], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[6], PL2GDMATACK_delay[6]); + $setuphold (posedge GDMAFCICLK[6], posedge PL2GDMACVLD[6], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[6], PL2GDMACVLD_delay[6]); + $setuphold (posedge GDMAFCICLK[6], posedge PL2GDMATACK[6], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[6], PL2GDMATACK_delay[6]); + $setuphold (posedge GDMAFCICLK[7], negedge PL2GDMACVLD[7], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[7], PL2GDMACVLD_delay[7]); + $setuphold (posedge GDMAFCICLK[7], negedge PL2GDMATACK[7], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[7], PL2GDMATACK_delay[7]); + $setuphold (posedge GDMAFCICLK[7], posedge PL2GDMACVLD[7], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[7], PL2GDMACVLD_delay[7]); + $setuphold (posedge GDMAFCICLK[7], posedge PL2GDMATACK[7], 0:0:0, 0:0:0, notifier, , , GDMAFCICLK_delay[7], PL2GDMATACK_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0ARREADY_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0AWREADY_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[12]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[13]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[14]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[15]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BVALID_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[100]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[101]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[102]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[103]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[104]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[105]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[106]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[107]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[108]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[109]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[110]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[111]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[112]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[113]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[114]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[115]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[116]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[117]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[118]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[119]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[120]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[121]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[122]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[123]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[124]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[125]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[126]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[127]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[12]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[13]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[14]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[15]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[16]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[17]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[18]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[19]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[20]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[21]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[22]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[23]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[24]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[25]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[26]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[27]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[28]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[29]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[30]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[31]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[32]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[33]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[34]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[35]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[36]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[37]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[38]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[39]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[40]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[41]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[42]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[43]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[44]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[45]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[46]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[47]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[48]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[49]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[50]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[51]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[52]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[53]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[54]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[55]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[56]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[57]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[58]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[59]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[60]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[61]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[62]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[63]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[64]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[65]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[66]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[67]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[68]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[69]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[70]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[71]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[72]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[73]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[74]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[75]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[76]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[77]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[78]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[79]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[80]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[81]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[82]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[83]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[84]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[85]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[86]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[87]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[88]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[89]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[90]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[91]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[92]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[93]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[94]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[95]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[96]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[97]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[98]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[99]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[12]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[13]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[14]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[15]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RLAST_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RVALID_delay); + $setuphold (posedge MAXIGP0ACLK, negedge MAXIGP0WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0WREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0ARREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0AWREADY_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[12]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[13]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[14]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[15]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0BVALID_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[100]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[101]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[102]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[103]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[104]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[105]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[106]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[107]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[108]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[109]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[110]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[111]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[112]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[113]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[114]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[115]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[116]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[117]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[118]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[119]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[120]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[121]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[122]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[123]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[124]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[125]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[126]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[127]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[12]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[13]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[14]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[15]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[16]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[17]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[18]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[19]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[20]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[21]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[22]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[23]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[24]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[25]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[26]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[27]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[28]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[29]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[30]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[31]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[32]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[33]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[34]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[35]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[36]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[37]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[38]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[39]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[40]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[41]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[42]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[43]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[44]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[45]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[46]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[47]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[48]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[49]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[50]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[51]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[52]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[53]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[54]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[55]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[56]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[57]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[58]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[59]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[60]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[61]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[62]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[63]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[64]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[65]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[66]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[67]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[68]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[69]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[70]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[71]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[72]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[73]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[74]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[75]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[76]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[77]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[78]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[79]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[80]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[81]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[82]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[83]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[84]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[85]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[86]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[87]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[88]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[89]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[90]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[91]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[92]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[93]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[94]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[95]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[96]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[97]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[98]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[99]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RDATA_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[10]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[11]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[12]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[13]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[14]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[15]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[2]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[3]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[4]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[5]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[6]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[7]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[8]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RID_delay[9]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RLAST_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[0]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RRESP_delay[1]); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0RVALID_delay); + $setuphold (posedge MAXIGP0ACLK, posedge MAXIGP0WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP0ACLK_delay, MAXIGP0WREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1ARREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1AWREADY_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[12]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[13]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[14]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[15]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BVALID_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[100]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[101]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[102]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[103]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[104]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[105]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[106]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[107]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[108]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[109]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[110]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[111]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[112]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[113]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[114]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[115]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[116]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[117]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[118]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[119]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[120]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[121]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[122]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[123]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[124]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[125]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[126]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[127]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[12]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[13]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[14]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[15]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[16]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[17]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[18]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[19]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[20]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[21]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[22]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[23]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[24]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[25]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[26]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[27]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[28]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[29]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[30]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[31]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[32]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[33]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[34]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[35]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[36]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[37]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[38]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[39]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[40]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[41]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[42]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[43]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[44]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[45]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[46]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[47]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[48]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[49]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[50]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[51]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[52]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[53]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[54]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[55]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[56]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[57]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[58]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[59]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[60]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[61]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[62]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[63]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[64]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[65]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[66]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[67]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[68]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[69]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[70]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[71]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[72]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[73]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[74]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[75]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[76]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[77]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[78]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[79]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[80]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[81]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[82]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[83]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[84]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[85]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[86]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[87]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[88]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[89]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[90]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[91]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[92]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[93]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[94]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[95]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[96]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[97]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[98]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[99]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[12]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[13]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[14]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[15]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RLAST_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RVALID_delay); + $setuphold (posedge MAXIGP1ACLK, negedge MAXIGP1WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1WREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1ARREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1AWREADY_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[12]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[13]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[14]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[15]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1BVALID_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[100]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[101]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[102]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[103]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[104]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[105]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[106]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[107]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[108]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[109]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[110]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[111]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[112]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[113]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[114]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[115]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[116]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[117]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[118]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[119]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[120]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[121]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[122]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[123]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[124]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[125]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[126]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[127]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[12]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[13]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[14]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[15]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[16]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[17]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[18]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[19]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[20]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[21]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[22]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[23]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[24]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[25]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[26]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[27]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[28]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[29]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[30]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[31]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[32]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[33]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[34]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[35]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[36]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[37]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[38]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[39]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[40]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[41]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[42]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[43]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[44]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[45]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[46]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[47]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[48]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[49]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[50]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[51]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[52]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[53]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[54]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[55]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[56]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[57]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[58]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[59]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[60]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[61]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[62]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[63]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[64]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[65]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[66]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[67]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[68]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[69]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[70]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[71]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[72]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[73]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[74]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[75]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[76]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[77]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[78]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[79]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[80]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[81]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[82]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[83]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[84]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[85]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[86]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[87]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[88]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[89]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[90]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[91]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[92]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[93]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[94]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[95]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[96]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[97]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[98]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[99]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RDATA_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[10]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[11]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[12]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[13]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[14]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[15]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[2]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[3]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[4]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[5]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[6]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[7]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[8]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RID_delay[9]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RLAST_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[0]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RRESP_delay[1]); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1RVALID_delay); + $setuphold (posedge MAXIGP1ACLK, posedge MAXIGP1WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP1ACLK_delay, MAXIGP1WREADY_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2ARREADY_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2AWREADY_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[0]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[10]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[11]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[12]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[13]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[14]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[15]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[1]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[2]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[3]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[4]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[5]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[6]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[7]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[8]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[9]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BRESP_delay[0]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BRESP_delay[1]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BVALID_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[0]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[100]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[101]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[102]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[103]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[104]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[105]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[106]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[107]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[108]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[109]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[10]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[110]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[111]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[112]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[113]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[114]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[115]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[116]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[117]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[118]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[119]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[11]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[120]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[121]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[122]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[123]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[124]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[125]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[126]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[127]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[12]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[13]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[14]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[15]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[16]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[17]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[18]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[19]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[1]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[20]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[21]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[22]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[23]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[24]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[25]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[26]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[27]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[28]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[29]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[2]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[30]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[31]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[32]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[33]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[34]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[35]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[36]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[37]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[38]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[39]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[3]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[40]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[41]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[42]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[43]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[44]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[45]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[46]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[47]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[48]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[49]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[4]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[50]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[51]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[52]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[53]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[54]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[55]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[56]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[57]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[58]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[59]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[5]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[60]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[61]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[62]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[63]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[64]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[65]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[66]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[67]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[68]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[69]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[6]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[70]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[71]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[72]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[73]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[74]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[75]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[76]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[77]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[78]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[79]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[7]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[80]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[81]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[82]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[83]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[84]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[85]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[86]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[87]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[88]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[89]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[8]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[90]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[91]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[92]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[93]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[94]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[95]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[96]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[97]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[98]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[99]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[9]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[0]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[10]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[11]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[12]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[13]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[14]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[15]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[1]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[2]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[3]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[4]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[5]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[6]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[7]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[8]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[9]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RLAST_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RRESP_delay[0]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RRESP_delay[1]); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RVALID_delay); + $setuphold (posedge MAXIGP2ACLK, negedge MAXIGP2WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2WREADY_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2ARREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2ARREADY_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2AWREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2AWREADY_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[0]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[10]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[11]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[12]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[13]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[14]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[15]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[1]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[2]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[3]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[4]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[5]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[6]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[7]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[8]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BID_delay[9]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BRESP_delay[0]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BRESP_delay[1]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2BVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2BVALID_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[0]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[100], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[100]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[101], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[101]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[102], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[102]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[103], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[103]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[104], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[104]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[105], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[105]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[106], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[106]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[107], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[107]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[108], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[108]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[109], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[109]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[10]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[110], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[110]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[111], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[111]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[112], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[112]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[113], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[113]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[114], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[114]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[115], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[115]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[116], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[116]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[117], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[117]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[118], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[118]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[119], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[119]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[11]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[120], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[120]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[121], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[121]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[122], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[122]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[123], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[123]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[124], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[124]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[125], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[125]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[126], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[126]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[127], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[127]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[12]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[13]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[14]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[15]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[16], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[16]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[17], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[17]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[18], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[18]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[19], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[19]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[1]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[20], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[20]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[21], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[21]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[22], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[22]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[23], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[23]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[24], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[24]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[25], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[25]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[26], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[26]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[27], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[27]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[28], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[28]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[29], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[29]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[2]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[30], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[30]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[31], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[31]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[32], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[32]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[33], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[33]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[34], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[34]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[35], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[35]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[36], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[36]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[37], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[37]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[38], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[38]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[39], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[39]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[3]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[40], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[40]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[41], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[41]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[42], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[42]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[43], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[43]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[44], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[44]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[45], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[45]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[46], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[46]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[47], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[47]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[48], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[48]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[49], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[49]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[4]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[50], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[50]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[51], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[51]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[52], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[52]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[53], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[53]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[54], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[54]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[55], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[55]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[56], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[56]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[57], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[57]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[58], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[58]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[59], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[59]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[5]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[60], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[60]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[61], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[61]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[62], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[62]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[63], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[63]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[64], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[64]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[65], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[65]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[66], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[66]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[67], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[67]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[68], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[68]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[69], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[69]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[6]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[70], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[70]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[71], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[71]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[72], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[72]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[73], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[73]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[74], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[74]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[75], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[75]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[76], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[76]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[77], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[77]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[78], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[78]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[79], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[79]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[7]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[80], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[80]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[81], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[81]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[82], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[82]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[83], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[83]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[84], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[84]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[85], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[85]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[86], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[86]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[87], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[87]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[88], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[88]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[89], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[89]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[8]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[90], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[90]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[91], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[91]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[92], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[92]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[93], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[93]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[94], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[94]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[95], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[95]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[96], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[96]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[97], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[97]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[98], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[98]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[99], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[99]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RDATA[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RDATA_delay[9]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[0]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[10], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[10]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[11], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[11]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[12], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[12]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[13], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[13]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[14], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[14]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[15], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[15]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[1]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[2], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[2]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[3], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[3]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[4], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[4]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[5], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[5]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[6], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[6]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[7], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[7]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[8], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[8]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RID[9], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RID_delay[9]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RLAST, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RLAST_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RRESP[0], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RRESP_delay[0]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RRESP[1], 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RRESP_delay[1]); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2RVALID, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2RVALID_delay); + $setuphold (posedge MAXIGP2ACLK, posedge MAXIGP2WREADY, 0:0:0, 0:0:0, notifier, , , MAXIGP2ACLK_delay, MAXIGP2WREADY_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDACREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDACREADY_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[16]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[17]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[18]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[19]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[20]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[21]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[22]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[23]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[24]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[25]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[26]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[27]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[28]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[29]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[30]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[31]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[32]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[33]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[34]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[35]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[36]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[37]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[38]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[39]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[40]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[41]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[42]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[43]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDARADDR[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDARBAR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBAR_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARBAR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBAR_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARBURST[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBURST_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARBURST[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBURST_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARCACHE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARCACHE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARCACHE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARCACHE[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARDOMAIN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARDOMAIN_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARDOMAIN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARDOMAIN_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDARID[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLEN[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDARLOCK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLOCK_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDARPROT[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARPROT[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARPROT[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARQOS[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARQOS[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARQOS[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARQOS[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARREGION[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARREGION[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARREGION[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARREGION[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSIZE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSIZE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSIZE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSNOOP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSNOOP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSNOOP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARSNOOP[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDARUSER[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDARVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARVALID_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[16]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[17]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[18]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[19]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[20]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[21]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[22]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[23]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[24]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[25]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[26]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[27]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[28]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[29]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[30]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[31]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[32]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[33]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[34]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[35]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[36]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[37]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[38]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[39]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[40]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[41]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[42]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[43]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWADDR[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWBAR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBAR_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWBAR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBAR_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWBURST[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBURST_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWBURST[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBURST_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWCACHE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWCACHE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWCACHE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWCACHE[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWDOMAIN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWDOMAIN_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWDOMAIN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWDOMAIN_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWID[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLEN[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWLOCK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLOCK_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDAWPROT[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWPROT[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWPROT[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWQOS[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWQOS[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWQOS[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWQOS[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWREGION[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWREGION[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWREGION[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWREGION[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSIZE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSIZE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSIZE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSNOOP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSNOOP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWSNOOP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWUSER[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDAWVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWVALID_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDBREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDBREADY_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[100], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[100]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[101], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[101]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[102], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[102]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[103], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[103]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[104], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[104]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[105], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[105]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[106], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[106]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[107], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[107]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[108], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[108]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[109], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[109]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[110], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[110]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[111], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[111]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[112], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[112]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[113], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[113]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[114], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[114]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[115], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[115]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[116], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[116]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[117], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[117]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[118], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[118]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[119], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[119]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[120], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[120]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[121], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[121]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[122], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[122]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[123], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[123]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[124], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[124]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[125], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[125]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[126], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[126]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[127], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[127]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[16]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[17]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[18]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[19]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[20]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[21]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[22]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[23]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[24]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[25]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[26]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[27]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[28]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[29]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[30]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[31]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[32]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[33]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[34]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[35]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[36]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[37]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[38]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[39]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[40]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[41]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[42]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[43]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[44], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[44]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[45], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[45]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[46], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[46]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[47], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[47]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[48], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[48]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[49], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[49]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[50], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[50]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[51], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[51]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[52], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[52]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[53], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[53]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[54], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[54]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[55], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[55]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[56], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[56]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[57], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[57]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[58], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[58]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[59], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[59]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[60], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[60]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[61], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[61]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[62], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[62]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[63], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[63]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[64], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[64]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[65], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[65]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[66], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[66]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[67], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[67]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[68], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[68]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[69], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[69]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[70], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[70]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[71], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[71]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[72], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[72]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[73], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[73]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[74], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[74]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[75], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[75]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[76], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[76]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[77], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[77]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[78], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[78]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[79], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[79]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[80], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[80]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[81], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[81]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[82], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[82]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[83], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[83]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[84], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[84]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[85], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[85]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[86], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[86]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[87], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[87]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[88], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[88]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[89], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[89]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[90], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[90]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[91], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[91]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[92], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[92]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[93], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[93]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[94], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[94]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[95], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[95]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[96], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[96]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[97], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[97]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[98], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[98]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[99], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[99]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDDATA[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDCDLAST, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDLAST_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDCDVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDVALID_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDCRRESP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDCRRESP[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDCRRESP[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDCRVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRVALID_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDRACK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDRACK_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDRREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDRREADY_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDWACK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWACK_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[100], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[100]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[101], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[101]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[102], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[102]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[103], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[103]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[104], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[104]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[105], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[105]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[106], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[106]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[107], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[107]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[108], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[108]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[109], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[109]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[110], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[110]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[111], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[111]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[112], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[112]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[113], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[113]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[114], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[114]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[115], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[115]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[116], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[116]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[117], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[117]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[118], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[118]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[119], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[119]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[120], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[120]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[121], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[121]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[122], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[122]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[123], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[123]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[124], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[124]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[125], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[125]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[126], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[126]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[127], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[127]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[16]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[17]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[18]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[19]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[20]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[21]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[22]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[23]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[24]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[25]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[26]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[27]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[28]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[29]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[30]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[31]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[32]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[33]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[34]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[35]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[36]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[37]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[38]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[39]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[40]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[41]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[42]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[43]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[44], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[44]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[45], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[45]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[46], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[46]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[47], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[47]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[48], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[48]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[49], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[49]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[50], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[50]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[51], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[51]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[52], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[52]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[53], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[53]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[54], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[54]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[55], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[55]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[56], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[56]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[57], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[57]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[58], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[58]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[59], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[59]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[60], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[60]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[61], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[61]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[62], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[62]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[63], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[63]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[64], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[64]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[65], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[65]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[66], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[66]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[67], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[67]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[68], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[68]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[69], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[69]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[70], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[70]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[71], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[71]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[72], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[72]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[73], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[73]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[74], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[74]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[75], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[75]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[76], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[76]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[77], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[77]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[78], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[78]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[79], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[79]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[80], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[80]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[81], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[81]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[82], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[82]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[83], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[83]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[84], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[84]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[85], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[85]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[86], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[86]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[87], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[87]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[88], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[88]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[89], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[89]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[90], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[90]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[91], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[91]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[92], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[92]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[93], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[93]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[94], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[94]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[95], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[95]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[96], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[96]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[97], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[97]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[98], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[98]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[99], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[99]); + $setuphold (posedge PLACECLK, negedge SACEFPDWDATA[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDWLAST, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWLAST_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[0]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[10]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[11]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[12]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[13]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[14]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[15]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[1]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[2]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[3]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[4]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[5]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[6]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[7]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[8]); + $setuphold (posedge PLACECLK, negedge SACEFPDWSTRB[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[9]); + $setuphold (posedge PLACECLK, negedge SACEFPDWUSER, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWUSER_delay); + $setuphold (posedge PLACECLK, negedge SACEFPDWVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWVALID_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDACREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDACREADY_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[16]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[17]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[18]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[19]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[20]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[21]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[22]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[23]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[24]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[25]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[26]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[27]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[28]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[29]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[30]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[31]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[32]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[33]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[34]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[35]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[36]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[37]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[38]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[39]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[40]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[41]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[42]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[43]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDARADDR[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARADDR_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDARBAR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBAR_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARBAR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBAR_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARBURST[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBURST_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARBURST[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARBURST_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARCACHE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARCACHE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARCACHE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARCACHE[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARCACHE_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARDOMAIN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARDOMAIN_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARDOMAIN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARDOMAIN_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDARID[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARID_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLEN[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLEN_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDARLOCK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARLOCK_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDARPROT[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARPROT[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARPROT[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARPROT_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARQOS[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARQOS[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARQOS[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARQOS[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARQOS_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARREGION[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARREGION[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARREGION[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARREGION[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARREGION_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSIZE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSIZE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSIZE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSIZE_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSNOOP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSNOOP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSNOOP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARSNOOP[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARSNOOP_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDARUSER[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARUSER_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDARVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDARVALID_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[16]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[17]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[18]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[19]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[20]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[21]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[22]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[23]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[24]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[25]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[26]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[27]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[28]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[29]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[30]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[31]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[32]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[33]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[34]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[35]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[36]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[37]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[38]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[39]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[40]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[41]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[42]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[43]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWADDR[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWADDR_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWBAR[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBAR_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWBAR[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBAR_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWBURST[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBURST_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWBURST[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWBURST_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWCACHE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWCACHE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWCACHE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWCACHE[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWCACHE_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWDOMAIN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWDOMAIN_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWDOMAIN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWDOMAIN_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWID[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWID_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLEN[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLEN_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWLOCK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWLOCK_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDAWPROT[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWPROT[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWPROT[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWPROT_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWQOS[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWQOS[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWQOS[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWQOS[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWQOS_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWREGION[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWREGION[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWREGION[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWREGION[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWREGION_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSIZE[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSIZE[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSIZE[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSIZE_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSNOOP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSNOOP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWSNOOP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWSNOOP_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWUSER[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWUSER_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDAWVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDAWVALID_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDBREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDBREADY_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[100], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[100]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[101], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[101]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[102], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[102]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[103], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[103]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[104], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[104]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[105], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[105]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[106], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[106]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[107], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[107]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[108], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[108]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[109], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[109]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[110], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[110]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[111], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[111]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[112], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[112]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[113], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[113]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[114], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[114]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[115], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[115]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[116], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[116]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[117], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[117]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[118], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[118]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[119], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[119]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[120], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[120]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[121], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[121]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[122], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[122]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[123], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[123]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[124], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[124]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[125], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[125]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[126], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[126]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[127], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[127]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[16]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[17]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[18]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[19]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[20]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[21]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[22]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[23]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[24]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[25]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[26]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[27]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[28]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[29]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[30]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[31]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[32]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[33]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[34]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[35]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[36]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[37]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[38]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[39]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[40]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[41]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[42]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[43]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[44], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[44]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[45], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[45]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[46], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[46]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[47], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[47]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[48], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[48]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[49], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[49]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[50], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[50]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[51], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[51]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[52], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[52]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[53], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[53]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[54], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[54]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[55], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[55]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[56], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[56]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[57], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[57]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[58], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[58]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[59], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[59]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[60], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[60]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[61], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[61]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[62], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[62]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[63], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[63]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[64], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[64]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[65], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[65]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[66], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[66]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[67], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[67]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[68], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[68]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[69], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[69]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[70], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[70]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[71], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[71]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[72], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[72]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[73], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[73]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[74], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[74]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[75], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[75]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[76], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[76]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[77], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[77]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[78], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[78]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[79], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[79]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[80], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[80]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[81], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[81]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[82], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[82]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[83], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[83]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[84], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[84]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[85], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[85]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[86], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[86]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[87], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[87]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[88], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[88]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[89], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[89]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[90], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[90]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[91], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[91]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[92], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[92]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[93], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[93]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[94], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[94]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[95], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[95]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[96], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[96]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[97], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[97]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[98], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[98]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[99], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[99]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDDATA[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDDATA_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDCDLAST, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDLAST_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDCDVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCDVALID_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDCRRESP[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDCRRESP[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDCRRESP[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRRESP_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDCRVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDCRVALID_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDRACK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDRACK_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDRREADY, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDRREADY_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDWACK, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWACK_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[100], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[100]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[101], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[101]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[102], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[102]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[103], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[103]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[104], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[104]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[105], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[105]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[106], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[106]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[107], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[107]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[108], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[108]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[109], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[109]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[110], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[110]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[111], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[111]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[112], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[112]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[113], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[113]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[114], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[114]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[115], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[115]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[116], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[116]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[117], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[117]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[118], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[118]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[119], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[119]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[120], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[120]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[121], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[121]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[122], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[122]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[123], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[123]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[124], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[124]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[125], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[125]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[126], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[126]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[127], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[127]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[16], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[16]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[17], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[17]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[18], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[18]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[19], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[19]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[20], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[20]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[21], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[21]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[22], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[22]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[23], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[23]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[24], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[24]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[25], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[25]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[26], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[26]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[27], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[27]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[28], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[28]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[29], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[29]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[30], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[30]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[31], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[31]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[32], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[32]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[33], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[33]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[34], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[34]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[35], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[35]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[36], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[36]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[37], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[37]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[38], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[38]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[39], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[39]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[40], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[40]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[41], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[41]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[42], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[42]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[43], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[43]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[44], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[44]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[45], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[45]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[46], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[46]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[47], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[47]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[48], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[48]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[49], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[49]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[50], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[50]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[51], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[51]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[52], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[52]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[53], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[53]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[54], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[54]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[55], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[55]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[56], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[56]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[57], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[57]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[58], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[58]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[59], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[59]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[60], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[60]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[61], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[61]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[62], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[62]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[63], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[63]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[64], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[64]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[65], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[65]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[66], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[66]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[67], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[67]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[68], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[68]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[69], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[69]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[70], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[70]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[71], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[71]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[72], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[72]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[73], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[73]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[74], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[74]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[75], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[75]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[76], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[76]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[77], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[77]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[78], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[78]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[79], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[79]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[80], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[80]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[81], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[81]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[82], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[82]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[83], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[83]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[84], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[84]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[85], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[85]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[86], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[86]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[87], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[87]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[88], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[88]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[89], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[89]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[90], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[90]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[91], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[91]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[92], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[92]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[93], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[93]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[94], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[94]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[95], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[95]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[96], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[96]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[97], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[97]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[98], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[98]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[99], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[99]); + $setuphold (posedge PLACECLK, posedge SACEFPDWDATA[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWDATA_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDWLAST, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWLAST_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[0], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[0]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[10], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[10]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[11], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[11]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[12], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[12]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[13], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[13]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[14], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[14]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[15], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[15]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[1], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[1]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[2], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[2]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[3], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[3]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[4], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[4]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[5], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[5]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[6], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[6]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[7], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[7]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[8], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[8]); + $setuphold (posedge PLACECLK, posedge SACEFPDWSTRB[9], 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWSTRB_delay[9]); + $setuphold (posedge PLACECLK, posedge SACEFPDWUSER, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWUSER_delay); + $setuphold (posedge PLACECLK, posedge SACEFPDWVALID, 0:0:0, 0:0:0, notifier, , , PLACECLK_delay, SACEFPDWVALID_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[32]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[33]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[34]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[35]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[36]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[37]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[38]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[39]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARID[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPARVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARVALID_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[32]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[33]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[34]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[35]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[36]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[37]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[38]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[39]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWID[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPAWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWVALID_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPBREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPBREADY_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPRREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPRREADY_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[100]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[101]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[102]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[103]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[104]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[105]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[106]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[107]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[108]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[109]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[110]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[111]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[112]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[113]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[114]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[115]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[116]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[117]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[118]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[119]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[120]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[121]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[122]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[123]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[124]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[125]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[126]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[127]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[16]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[17]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[18]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[19]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[20]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[21]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[22]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[23]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[24]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[25]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[26]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[27]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[28]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[29]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[30]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[31]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[32]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[33]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[34]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[35]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[36]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[37]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[38]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[39]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[40]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[41]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[42]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[43]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[44]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[45]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[46]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[47]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[48]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[49]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[50]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[51]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[52]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[53]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[54]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[55]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[56]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[57]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[58]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[59]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[60]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[61]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[62]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[63]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[64]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[65]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[66]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[67]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[68]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[69]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[70]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[71]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[72]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[73]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[74]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[75]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[76]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[77]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[78]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[79]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[80]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[81]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[82]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[83]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[84]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[85]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[86]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[87]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[88]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[89]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[90]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[91]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[92]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[93]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[94]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[95]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[96]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[97]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[98]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[99]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWLAST, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWLAST_delay); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[0]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[10]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[11]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[12]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[13]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[14]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[15]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[1]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[2]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[3]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[4]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[5]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[6]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[7]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[8]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[9]); + $setuphold (posedge SAXIACPACLK, negedge SAXIACPWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[32]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[33]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[34]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[35]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[36]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[37]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[38]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[39]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARID[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARID_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLEN_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARLOCK_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARQOS_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARSIZE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPARVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPARVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[32]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[33]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[34]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[35]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[36]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[37]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[38]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[39]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWADDR_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWBURST_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWCACHE_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWID[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWID_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLEN_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWLOCK_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWPROT_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWQOS_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWSIZE_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWUSER[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWUSER_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPAWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPAWVALID_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPBREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPBREADY_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPRREADY, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPRREADY_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[100]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[101]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[102]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[103]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[104]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[105]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[106]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[107]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[108]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[109]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[110]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[111]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[112]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[113]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[114]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[115]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[116]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[117]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[118]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[119]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[120]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[121]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[122]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[123]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[124]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[125]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[126]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[127]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[16]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[17]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[18]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[19]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[20]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[21]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[22]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[23]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[24]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[25]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[26]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[27]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[28]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[29]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[30]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[31]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[32]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[33]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[34]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[35]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[36]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[37]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[38]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[39]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[40]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[41]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[42]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[43]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[44]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[45]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[46]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[47]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[48]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[49]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[50]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[51]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[52]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[53]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[54]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[55]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[56]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[57]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[58]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[59]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[60]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[61]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[62]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[63]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[64]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[65]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[66]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[67]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[68]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[69]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[70]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[71]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[72]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[73]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[74]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[75]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[76]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[77]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[78]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[79]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[80]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[81]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[82]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[83]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[84]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[85]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[86]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[87]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[88]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[89]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[90]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[91]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[92]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[93]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[94]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[95]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[96]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[97]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[98]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[99]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWDATA_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWLAST, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWLAST_delay); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[0]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[10]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[11]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[12]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[13]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[14]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[15]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[1]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[2]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[3]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[4]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[5]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[6]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[7]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[8]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWSTRB_delay[9]); + $setuphold (posedge SAXIACPACLK, posedge SAXIACPWVALID, 0:0:0, 0:0:0, notifier, , , SAXIACPACLK_delay, SAXIACPWVALID_delay); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[10]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[11]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[12]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[13]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[14]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[15]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[16]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[17]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[18]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[19]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[20]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[21]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[22]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[23]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[24]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[25]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[26]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[27]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[28]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[29]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[30]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[31]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[32]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[33]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[34]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[35]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[36]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[37]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[38]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[39]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[3]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[40]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[41]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[42]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[43]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[44]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[45]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[46]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[47]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[48]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[4]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[5]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[6]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[7]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[8]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[9]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARBURST_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARBURST_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[3]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[3]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[4]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[5]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[3]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[4]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[5]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[6]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[7]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLOCK_delay); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[3]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[0]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[1]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[2]); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARUSER_delay); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARVALID_delay); + $setuphold (posedge SAXIGP0RCLK, negedge SAXIGP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0RREADY_delay); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[10]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[11]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[12]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[13]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[14]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[15]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[16]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[17]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[18]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[19]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[20]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[21]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[22]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[23]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[24]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[25]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[26]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[27]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[28]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[29]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[30]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[31]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[32]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[33]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[34]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[35]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[36]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[37]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[38]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[39]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[3]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[40]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[41]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[42]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[43]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[44]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[45]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[46]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[47]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[48]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[4]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[5]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[6]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[7]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[8]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARADDR_delay[9]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARBURST_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARBURST_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARCACHE_delay[3]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[3]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[4]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARID_delay[5]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[3]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[4]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[5]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[6]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLEN_delay[7]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARLOCK_delay); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARPROT_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARQOS_delay[3]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[0]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[1]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARSIZE_delay[2]); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARUSER_delay); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0ARVALID_delay); + $setuphold (posedge SAXIGP0RCLK, posedge SAXIGP0RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0RCLK_delay, SAXIGP0RREADY_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[10]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[11]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[12]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[13]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[14]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[15]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[16]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[17]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[18]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[19]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[20]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[21]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[22]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[23]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[24]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[25]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[26]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[27]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[28]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[29]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[30]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[31]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[32]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[33]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[34]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[35]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[36]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[37]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[38]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[39]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[40]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[41]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[42]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[43]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[44]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[45]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[46]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[47]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[48]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[4]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[5]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[6]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[7]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[8]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[9]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWBURST_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWBURST_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[4]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[5]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[4]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[5]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[6]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[7]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLOCK_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWUSER_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWVALID_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0BREADY_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[100]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[101]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[102]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[103]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[104]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[105]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[106]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[107]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[108]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[109]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[10]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[110]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[111]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[112]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[113]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[114]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[115]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[116]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[117]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[118]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[119]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[11]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[120]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[121]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[122]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[123]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[124]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[125]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[126]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[127]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[12]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[13]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[14]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[15]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[16]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[17]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[18]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[19]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[20]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[21]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[22]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[23]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[24]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[25]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[26]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[27]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[28]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[29]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[30]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[31]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[32]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[33]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[34]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[35]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[36]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[37]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[38]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[39]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[40]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[41]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[42]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[43]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[44]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[45]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[46]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[47]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[48]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[49]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[4]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[50]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[51]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[52]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[53]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[54]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[55]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[56]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[57]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[58]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[59]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[5]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[60]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[61]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[62]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[63]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[64]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[65]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[66]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[67]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[68]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[69]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[6]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[70]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[71]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[72]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[73]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[74]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[75]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[76]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[77]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[78]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[79]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[7]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[80]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[81]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[82]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[83]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[84]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[85]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[86]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[87]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[88]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[89]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[8]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[90]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[91]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[92]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[93]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[94]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[95]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[96]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[97]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[98]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[99]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[9]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WLAST_delay); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[0]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[10]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[11]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[12]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[13]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[14]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[15]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[1]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[2]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[3]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[4]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[5]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[6]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[7]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[8]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[9]); + $setuphold (posedge SAXIGP0WCLK, negedge SAXIGP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WVALID_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[10]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[11]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[12]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[13]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[14]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[15]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[16]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[17]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[18]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[19]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[20]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[21]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[22]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[23]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[24]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[25]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[26]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[27]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[28]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[29]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[30]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[31]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[32]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[33]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[34]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[35]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[36]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[37]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[38]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[39]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[40]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[41]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[42]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[43]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[44]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[45]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[46]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[47]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[48]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[4]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[5]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[6]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[7]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[8]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWADDR_delay[9]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWBURST_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWBURST_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWCACHE_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[4]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWID_delay[5]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[4]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[5]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[6]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLEN_delay[7]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWLOCK_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWPROT_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWQOS_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWSIZE_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWUSER_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0AWVALID_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0BREADY_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[100]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[101]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[102]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[103]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[104]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[105]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[106]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[107]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[108]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[109]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[10]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[110]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[111]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[112]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[113]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[114]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[115]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[116]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[117]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[118]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[119]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[11]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[120]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[121]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[122]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[123]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[124]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[125]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[126]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[127]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[12]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[13]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[14]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[15]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[16]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[17]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[18]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[19]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[20]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[21]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[22]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[23]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[24]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[25]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[26]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[27]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[28]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[29]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[30]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[31]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[32]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[33]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[34]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[35]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[36]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[37]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[38]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[39]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[40]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[41]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[42]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[43]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[44]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[45]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[46]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[47]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[48]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[49]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[4]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[50]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[51]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[52]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[53]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[54]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[55]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[56]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[57]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[58]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[59]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[5]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[60]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[61]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[62]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[63]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[64]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[65]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[66]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[67]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[68]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[69]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[6]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[70]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[71]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[72]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[73]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[74]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[75]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[76]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[77]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[78]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[79]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[7]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[80]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[81]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[82]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[83]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[84]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[85]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[86]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[87]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[88]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[89]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[8]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[90]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[91]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[92]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[93]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[94]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[95]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[96]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[97]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[98]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[99]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WDATA_delay[9]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WLAST_delay); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[0]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[10]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[11]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[12]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[13]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[14]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[15]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[1]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[2]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[3]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[4]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[5]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[6]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[7]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[8]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WSTRB_delay[9]); + $setuphold (posedge SAXIGP0WCLK, posedge SAXIGP0WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP0WCLK_delay, SAXIGP0WVALID_delay); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[10]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[11]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[12]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[13]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[14]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[15]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[16]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[17]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[18]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[19]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[20]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[21]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[22]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[23]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[24]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[25]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[26]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[27]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[28]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[29]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[30]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[31]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[32]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[33]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[34]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[35]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[36]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[37]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[38]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[39]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[3]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[40]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[41]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[42]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[43]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[44]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[45]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[46]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[47]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[48]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[4]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[5]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[6]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[7]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[8]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[9]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARBURST_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARBURST_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[3]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[3]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[4]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[5]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[3]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[4]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[5]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[6]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[7]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLOCK_delay); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[3]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[0]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[1]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[2]); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARUSER_delay); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARVALID_delay); + $setuphold (posedge SAXIGP1RCLK, negedge SAXIGP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1RREADY_delay); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[10]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[11]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[12]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[13]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[14]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[15]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[16]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[17]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[18]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[19]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[20]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[21]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[22]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[23]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[24]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[25]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[26]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[27]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[28]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[29]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[30]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[31]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[32]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[33]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[34]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[35]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[36]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[37]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[38]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[39]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[3]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[40]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[41]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[42]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[43]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[44]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[45]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[46]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[47]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[48]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[4]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[5]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[6]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[7]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[8]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARADDR_delay[9]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARBURST_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARBURST_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARCACHE_delay[3]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[3]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[4]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARID_delay[5]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[3]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[4]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[5]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[6]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLEN_delay[7]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARLOCK_delay); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARPROT_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARQOS_delay[3]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[0]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[1]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARSIZE_delay[2]); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARUSER_delay); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1ARVALID_delay); + $setuphold (posedge SAXIGP1RCLK, posedge SAXIGP1RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1RCLK_delay, SAXIGP1RREADY_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[10]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[11]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[12]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[13]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[14]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[15]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[16]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[17]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[18]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[19]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[20]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[21]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[22]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[23]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[24]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[25]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[26]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[27]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[28]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[29]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[30]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[31]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[32]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[33]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[34]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[35]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[36]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[37]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[38]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[39]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[40]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[41]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[42]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[43]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[44]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[45]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[46]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[47]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[48]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[4]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[5]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[6]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[7]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[8]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[9]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWBURST_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWBURST_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[4]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[5]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[4]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[5]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[6]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[7]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLOCK_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWUSER_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWVALID_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1BREADY_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[100]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[101]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[102]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[103]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[104]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[105]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[106]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[107]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[108]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[109]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[10]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[110]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[111]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[112]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[113]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[114]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[115]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[116]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[117]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[118]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[119]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[11]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[120]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[121]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[122]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[123]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[124]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[125]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[126]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[127]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[12]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[13]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[14]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[15]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[16]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[17]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[18]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[19]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[20]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[21]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[22]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[23]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[24]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[25]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[26]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[27]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[28]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[29]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[30]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[31]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[32]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[33]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[34]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[35]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[36]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[37]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[38]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[39]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[40]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[41]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[42]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[43]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[44]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[45]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[46]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[47]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[48]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[49]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[4]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[50]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[51]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[52]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[53]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[54]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[55]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[56]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[57]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[58]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[59]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[5]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[60]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[61]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[62]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[63]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[64]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[65]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[66]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[67]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[68]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[69]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[6]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[70]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[71]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[72]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[73]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[74]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[75]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[76]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[77]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[78]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[79]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[7]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[80]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[81]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[82]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[83]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[84]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[85]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[86]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[87]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[88]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[89]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[8]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[90]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[91]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[92]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[93]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[94]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[95]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[96]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[97]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[98]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[99]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[9]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WLAST_delay); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[0]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[10]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[11]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[12]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[13]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[14]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[15]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[1]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[2]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[3]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[4]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[5]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[6]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[7]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[8]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[9]); + $setuphold (posedge SAXIGP1WCLK, negedge SAXIGP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WVALID_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[10]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[11]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[12]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[13]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[14]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[15]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[16]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[17]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[18]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[19]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[20]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[21]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[22]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[23]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[24]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[25]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[26]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[27]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[28]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[29]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[30]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[31]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[32]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[33]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[34]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[35]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[36]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[37]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[38]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[39]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[40]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[41]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[42]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[43]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[44]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[45]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[46]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[47]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[48]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[4]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[5]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[6]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[7]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[8]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWADDR_delay[9]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWBURST_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWBURST_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWCACHE_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[4]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWID_delay[5]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[4]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[5]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[6]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLEN_delay[7]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWLOCK_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWPROT_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWQOS_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWSIZE_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWUSER_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1AWVALID_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1BREADY_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[100]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[101]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[102]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[103]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[104]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[105]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[106]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[107]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[108]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[109]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[10]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[110]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[111]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[112]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[113]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[114]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[115]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[116]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[117]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[118]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[119]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[11]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[120]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[121]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[122]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[123]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[124]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[125]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[126]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[127]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[12]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[13]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[14]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[15]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[16]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[17]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[18]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[19]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[20]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[21]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[22]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[23]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[24]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[25]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[26]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[27]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[28]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[29]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[30]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[31]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[32]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[33]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[34]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[35]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[36]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[37]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[38]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[39]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[40]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[41]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[42]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[43]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[44]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[45]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[46]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[47]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[48]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[49]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[4]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[50]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[51]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[52]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[53]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[54]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[55]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[56]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[57]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[58]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[59]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[5]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[60]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[61]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[62]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[63]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[64]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[65]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[66]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[67]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[68]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[69]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[6]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[70]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[71]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[72]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[73]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[74]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[75]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[76]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[77]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[78]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[79]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[7]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[80]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[81]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[82]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[83]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[84]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[85]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[86]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[87]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[88]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[89]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[8]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[90]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[91]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[92]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[93]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[94]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[95]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[96]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[97]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[98]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[99]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WDATA_delay[9]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WLAST_delay); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[0]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[10]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[11]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[12]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[13]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[14]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[15]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[1]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[2]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[3]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[4]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[5]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[6]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[7]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[8]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WSTRB_delay[9]); + $setuphold (posedge SAXIGP1WCLK, posedge SAXIGP1WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP1WCLK_delay, SAXIGP1WVALID_delay); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[10]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[11]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[12]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[13]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[14]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[15]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[16]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[17]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[18]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[19]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[20]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[21]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[22]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[23]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[24]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[25]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[26]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[27]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[28]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[29]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[30]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[31]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[32]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[33]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[34]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[35]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[36]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[37]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[38]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[39]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[3]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[40]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[41]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[42]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[43]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[44]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[45]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[46]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[47]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[48]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[4]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[5]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[6]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[7]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[8]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[9]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARBURST_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARBURST_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[3]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[3]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[4]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[5]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[3]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[4]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[5]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[6]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[7]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLOCK_delay); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[3]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[0]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[1]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[2]); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARUSER_delay); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARVALID_delay); + $setuphold (posedge SAXIGP2RCLK, negedge SAXIGP2RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2RREADY_delay); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[10]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[11]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[12]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[13]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[14]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[15]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[16]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[17]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[18]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[19]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[20]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[21]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[22]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[23]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[24]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[25]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[26]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[27]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[28]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[29]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[30]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[31]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[32]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[33]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[34]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[35]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[36]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[37]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[38]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[39]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[3]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[40]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[41]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[42]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[43]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[44]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[45]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[46]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[47]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[48]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[4]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[5]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[6]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[7]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[8]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARADDR_delay[9]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARBURST_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARBURST_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARCACHE_delay[3]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[3]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[4]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARID_delay[5]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[3]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[4]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[5]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[6]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLEN_delay[7]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARLOCK_delay); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARPROT_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARQOS_delay[3]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[0]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[1]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARSIZE_delay[2]); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARUSER_delay); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2ARVALID_delay); + $setuphold (posedge SAXIGP2RCLK, posedge SAXIGP2RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP2RCLK_delay, SAXIGP2RREADY_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[10]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[11]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[12]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[13]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[14]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[15]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[16]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[17]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[18]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[19]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[20]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[21]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[22]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[23]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[24]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[25]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[26]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[27]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[28]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[29]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[30]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[31]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[32]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[33]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[34]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[35]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[36]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[37]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[38]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[39]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[40]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[41]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[42]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[43]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[44]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[45]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[46]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[47]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[48]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[4]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[5]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[6]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[7]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[8]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[9]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWBURST_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWBURST_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[4]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[5]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[4]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[5]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[6]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[7]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLOCK_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWUSER_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWVALID_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2BREADY_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[100]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[101]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[102]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[103]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[104]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[105]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[106]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[107]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[108]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[109]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[10]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[110]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[111]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[112]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[113]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[114]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[115]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[116]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[117]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[118]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[119]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[11]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[120]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[121]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[122]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[123]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[124]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[125]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[126]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[127]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[12]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[13]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[14]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[15]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[16]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[17]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[18]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[19]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[20]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[21]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[22]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[23]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[24]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[25]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[26]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[27]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[28]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[29]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[30]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[31]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[32]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[33]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[34]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[35]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[36]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[37]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[38]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[39]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[40]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[41]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[42]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[43]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[44]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[45]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[46]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[47]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[48]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[49]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[4]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[50]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[51]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[52]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[53]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[54]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[55]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[56]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[57]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[58]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[59]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[5]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[60]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[61]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[62]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[63]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[64]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[65]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[66]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[67]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[68]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[69]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[6]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[70]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[71]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[72]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[73]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[74]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[75]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[76]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[77]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[78]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[79]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[7]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[80]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[81]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[82]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[83]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[84]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[85]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[86]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[87]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[88]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[89]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[8]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[90]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[91]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[92]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[93]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[94]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[95]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[96]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[97]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[98]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[99]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[9]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WLAST_delay); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[0]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[10]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[11]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[12]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[13]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[14]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[15]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[1]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[2]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[3]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[4]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[5]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[6]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[7]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[8]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[9]); + $setuphold (posedge SAXIGP2WCLK, negedge SAXIGP2WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WVALID_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[10]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[11]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[12]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[13]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[14]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[15]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[16]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[17]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[18]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[19]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[20]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[21]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[22]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[23]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[24]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[25]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[26]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[27]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[28]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[29]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[30]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[31]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[32]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[33]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[34]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[35]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[36]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[37]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[38]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[39]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[40]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[41]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[42]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[43]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[44]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[45]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[46]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[47]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[48]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[4]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[5]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[6]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[7]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[8]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWADDR_delay[9]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWBURST_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWBURST_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWCACHE_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[4]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWID_delay[5]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[4]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[5]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[6]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLEN_delay[7]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWLOCK_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWPROT_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWQOS_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWSIZE_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWUSER_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2AWVALID_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2BREADY_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[100]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[101]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[102]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[103]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[104]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[105]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[106]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[107]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[108]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[109]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[10]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[110]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[111]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[112]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[113]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[114]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[115]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[116]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[117]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[118]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[119]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[11]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[120]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[121]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[122]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[123]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[124]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[125]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[126]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[127]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[12]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[13]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[14]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[15]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[16]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[17]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[18]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[19]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[20]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[21]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[22]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[23]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[24]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[25]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[26]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[27]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[28]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[29]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[30]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[31]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[32]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[33]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[34]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[35]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[36]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[37]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[38]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[39]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[40]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[41]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[42]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[43]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[44]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[45]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[46]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[47]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[48]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[49]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[4]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[50]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[51]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[52]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[53]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[54]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[55]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[56]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[57]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[58]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[59]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[5]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[60]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[61]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[62]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[63]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[64]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[65]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[66]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[67]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[68]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[69]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[6]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[70]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[71]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[72]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[73]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[74]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[75]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[76]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[77]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[78]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[79]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[7]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[80]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[81]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[82]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[83]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[84]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[85]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[86]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[87]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[88]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[89]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[8]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[90]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[91]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[92]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[93]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[94]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[95]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[96]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[97]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[98]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[99]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WDATA_delay[9]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WLAST_delay); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[0]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[10]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[11]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[12]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[13]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[14]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[15]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[1]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[2]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[3]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[4]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[5]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[6]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[7]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[8]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WSTRB_delay[9]); + $setuphold (posedge SAXIGP2WCLK, posedge SAXIGP2WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP2WCLK_delay, SAXIGP2WVALID_delay); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[10]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[11]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[12]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[13]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[14]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[15]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[16]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[17]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[18]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[19]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[20]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[21]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[22]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[23]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[24]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[25]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[26]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[27]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[28]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[29]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[30]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[31]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[32]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[33]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[34]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[35]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[36]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[37]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[38]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[39]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[3]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[40]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[41]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[42]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[43]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[44]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[45]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[46]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[47]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[48]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[4]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[5]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[6]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[7]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[8]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[9]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARBURST_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARBURST_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[3]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[3]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[4]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[5]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[3]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[4]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[5]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[6]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[7]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLOCK_delay); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[3]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[0]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[1]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[2]); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARUSER_delay); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARVALID_delay); + $setuphold (posedge SAXIGP3RCLK, negedge SAXIGP3RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3RREADY_delay); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[10]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[11]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[12]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[13]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[14]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[15]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[16]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[17]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[18]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[19]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[20]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[21]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[22]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[23]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[24]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[25]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[26]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[27]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[28]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[29]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[30]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[31]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[32]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[33]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[34]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[35]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[36]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[37]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[38]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[39]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[3]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[40]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[41]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[42]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[43]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[44]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[45]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[46]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[47]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[48]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[4]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[5]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[6]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[7]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[8]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARADDR_delay[9]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARBURST_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARBURST_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARCACHE_delay[3]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[3]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[4]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARID_delay[5]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[3]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[4]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[5]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[6]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLEN_delay[7]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARLOCK_delay); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARPROT_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARQOS_delay[3]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[0]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[1]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARSIZE_delay[2]); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARUSER_delay); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3ARVALID_delay); + $setuphold (posedge SAXIGP3RCLK, posedge SAXIGP3RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP3RCLK_delay, SAXIGP3RREADY_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[10]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[11]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[12]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[13]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[14]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[15]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[16]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[17]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[18]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[19]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[20]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[21]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[22]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[23]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[24]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[25]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[26]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[27]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[28]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[29]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[30]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[31]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[32]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[33]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[34]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[35]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[36]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[37]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[38]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[39]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[40]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[41]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[42]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[43]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[44]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[45]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[46]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[47]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[48]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[4]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[5]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[6]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[7]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[8]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[9]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWBURST_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWBURST_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[4]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[5]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[4]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[5]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[6]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[7]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLOCK_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWUSER_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWVALID_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3BREADY_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[100]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[101]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[102]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[103]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[104]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[105]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[106]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[107]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[108]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[109]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[10]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[110]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[111]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[112]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[113]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[114]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[115]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[116]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[117]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[118]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[119]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[11]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[120]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[121]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[122]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[123]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[124]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[125]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[126]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[127]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[12]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[13]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[14]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[15]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[16]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[17]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[18]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[19]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[20]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[21]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[22]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[23]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[24]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[25]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[26]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[27]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[28]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[29]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[30]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[31]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[32]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[33]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[34]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[35]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[36]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[37]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[38]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[39]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[40]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[41]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[42]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[43]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[44]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[45]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[46]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[47]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[48]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[49]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[4]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[50]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[51]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[52]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[53]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[54]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[55]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[56]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[57]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[58]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[59]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[5]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[60]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[61]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[62]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[63]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[64]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[65]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[66]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[67]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[68]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[69]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[6]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[70]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[71]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[72]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[73]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[74]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[75]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[76]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[77]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[78]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[79]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[7]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[80]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[81]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[82]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[83]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[84]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[85]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[86]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[87]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[88]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[89]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[8]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[90]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[91]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[92]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[93]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[94]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[95]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[96]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[97]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[98]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[99]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[9]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WLAST_delay); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[0]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[10]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[11]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[12]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[13]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[14]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[15]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[1]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[2]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[3]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[4]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[5]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[6]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[7]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[8]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[9]); + $setuphold (posedge SAXIGP3WCLK, negedge SAXIGP3WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WVALID_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[10]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[11]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[12]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[13]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[14]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[15]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[16]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[17]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[18]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[19]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[20]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[21]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[22]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[23]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[24]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[25]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[26]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[27]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[28]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[29]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[30]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[31]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[32]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[33]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[34]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[35]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[36]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[37]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[38]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[39]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[40]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[41]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[42]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[43]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[44]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[45]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[46]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[47]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[48]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[4]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[5]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[6]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[7]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[8]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWADDR_delay[9]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWBURST_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWBURST_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWCACHE_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[4]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWID_delay[5]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[4]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[5]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[6]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLEN_delay[7]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWLOCK_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWPROT_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWQOS_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWSIZE_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWUSER_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3AWVALID_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3BREADY_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[100]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[101]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[102]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[103]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[104]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[105]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[106]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[107]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[108]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[109]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[10]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[110]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[111]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[112]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[113]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[114]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[115]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[116]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[117]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[118]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[119]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[11]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[120]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[121]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[122]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[123]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[124]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[125]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[126]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[127]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[12]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[13]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[14]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[15]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[16]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[17]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[18]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[19]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[20]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[21]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[22]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[23]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[24]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[25]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[26]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[27]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[28]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[29]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[30]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[31]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[32]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[33]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[34]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[35]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[36]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[37]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[38]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[39]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[40]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[41]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[42]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[43]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[44]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[45]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[46]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[47]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[48]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[49]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[4]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[50]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[51]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[52]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[53]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[54]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[55]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[56]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[57]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[58]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[59]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[5]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[60]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[61]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[62]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[63]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[64]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[65]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[66]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[67]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[68]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[69]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[6]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[70]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[71]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[72]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[73]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[74]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[75]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[76]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[77]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[78]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[79]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[7]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[80]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[81]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[82]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[83]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[84]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[85]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[86]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[87]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[88]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[89]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[8]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[90]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[91]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[92]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[93]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[94]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[95]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[96]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[97]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[98]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[99]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WDATA_delay[9]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WLAST_delay); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[0]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[10]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[11]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[12]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[13]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[14]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[15]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[1]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[2]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[3]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[4]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[5]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[6]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[7]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[8]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WSTRB_delay[9]); + $setuphold (posedge SAXIGP3WCLK, posedge SAXIGP3WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP3WCLK_delay, SAXIGP3WVALID_delay); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[10]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[11]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[12]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[13]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[14]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[15]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[16]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[17]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[18]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[19]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[20]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[21]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[22]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[23]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[24]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[25]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[26]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[27]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[28]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[29]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[30]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[31]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[32]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[33]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[34]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[35]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[36]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[37]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[38]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[39]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[3]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[40]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[41]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[42]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[43]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[44]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[45]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[46]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[47]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[48]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[4]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[5]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[6]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[7]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[8]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[9]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARBURST_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARBURST_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[3]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[3]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[4]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[5]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[3]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[4]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[5]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[6]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[7]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLOCK_delay); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[3]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[0]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[1]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[2]); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARUSER_delay); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARVALID_delay); + $setuphold (posedge SAXIGP4RCLK, negedge SAXIGP4RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4RREADY_delay); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[10]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[11]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[12]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[13]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[14]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[15]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[16]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[17]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[18]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[19]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[20]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[21]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[22]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[23]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[24]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[25]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[26]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[27]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[28]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[29]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[30]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[31]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[32]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[33]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[34]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[35]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[36]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[37]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[38]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[39]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[3]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[40]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[41]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[42]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[43]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[44]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[45]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[46]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[47]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[48]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[4]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[5]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[6]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[7]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[8]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARADDR_delay[9]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARBURST_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARBURST_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARCACHE_delay[3]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[3]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[4]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARID_delay[5]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[3]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[4]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[5]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[6]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLEN_delay[7]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARLOCK_delay); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARPROT_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARQOS_delay[3]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[0]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[1]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARSIZE_delay[2]); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARUSER_delay); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4ARVALID_delay); + $setuphold (posedge SAXIGP4RCLK, posedge SAXIGP4RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP4RCLK_delay, SAXIGP4RREADY_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[10]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[11]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[12]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[13]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[14]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[15]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[16]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[17]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[18]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[19]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[20]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[21]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[22]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[23]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[24]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[25]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[26]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[27]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[28]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[29]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[30]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[31]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[32]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[33]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[34]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[35]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[36]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[37]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[38]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[39]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[40]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[41]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[42]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[43]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[44]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[45]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[46]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[47]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[48]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[4]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[5]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[6]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[7]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[8]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[9]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWBURST_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWBURST_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[4]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[5]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[4]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[5]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[6]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[7]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLOCK_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWUSER_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWVALID_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4BREADY_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[100]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[101]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[102]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[103]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[104]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[105]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[106]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[107]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[108]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[109]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[10]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[110]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[111]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[112]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[113]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[114]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[115]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[116]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[117]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[118]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[119]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[11]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[120]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[121]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[122]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[123]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[124]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[125]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[126]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[127]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[12]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[13]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[14]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[15]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[16]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[17]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[18]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[19]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[20]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[21]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[22]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[23]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[24]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[25]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[26]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[27]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[28]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[29]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[30]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[31]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[32]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[33]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[34]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[35]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[36]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[37]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[38]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[39]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[40]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[41]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[42]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[43]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[44]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[45]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[46]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[47]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[48]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[49]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[4]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[50]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[51]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[52]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[53]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[54]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[55]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[56]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[57]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[58]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[59]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[5]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[60]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[61]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[62]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[63]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[64]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[65]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[66]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[67]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[68]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[69]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[6]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[70]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[71]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[72]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[73]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[74]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[75]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[76]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[77]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[78]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[79]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[7]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[80]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[81]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[82]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[83]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[84]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[85]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[86]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[87]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[88]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[89]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[8]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[90]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[91]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[92]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[93]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[94]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[95]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[96]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[97]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[98]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[99]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[9]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WLAST_delay); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[0]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[10]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[11]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[12]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[13]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[14]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[15]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[1]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[2]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[3]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[4]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[5]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[6]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[7]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[8]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[9]); + $setuphold (posedge SAXIGP4WCLK, negedge SAXIGP4WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WVALID_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[10]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[11]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[12]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[13]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[14]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[15]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[16]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[17]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[18]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[19]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[20]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[21]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[22]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[23]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[24]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[25]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[26]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[27]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[28]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[29]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[30]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[31]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[32]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[33]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[34]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[35]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[36]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[37]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[38]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[39]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[40]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[41]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[42]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[43]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[44]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[45]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[46]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[47]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[48]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[4]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[5]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[6]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[7]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[8]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWADDR_delay[9]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWBURST_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWBURST_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWCACHE_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[4]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWID_delay[5]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[4]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[5]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[6]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLEN_delay[7]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWLOCK_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWPROT_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWQOS_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWSIZE_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWUSER_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4AWVALID_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4BREADY_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[100]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[101]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[102]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[103]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[104]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[105]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[106]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[107]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[108]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[109]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[10]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[110]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[111]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[112]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[113]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[114]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[115]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[116]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[117]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[118]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[119]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[11]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[120]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[121]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[122]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[123]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[124]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[125]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[126]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[127]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[12]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[13]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[14]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[15]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[16]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[17]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[18]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[19]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[20]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[21]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[22]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[23]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[24]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[25]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[26]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[27]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[28]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[29]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[30]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[31]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[32]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[33]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[34]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[35]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[36]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[37]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[38]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[39]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[40]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[41]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[42]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[43]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[44]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[45]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[46]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[47]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[48]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[49]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[4]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[50]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[51]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[52]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[53]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[54]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[55]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[56]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[57]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[58]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[59]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[5]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[60]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[61]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[62]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[63]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[64]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[65]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[66]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[67]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[68]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[69]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[6]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[70]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[71]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[72]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[73]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[74]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[75]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[76]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[77]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[78]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[79]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[7]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[80]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[81]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[82]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[83]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[84]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[85]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[86]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[87]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[88]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[89]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[8]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[90]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[91]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[92]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[93]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[94]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[95]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[96]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[97]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[98]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[99]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WDATA_delay[9]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WLAST_delay); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[0]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[10]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[11]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[12]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[13]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[14]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[15]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[1]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[2]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[3]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[4]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[5]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[6]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[7]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[8]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WSTRB_delay[9]); + $setuphold (posedge SAXIGP4WCLK, posedge SAXIGP4WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP4WCLK_delay, SAXIGP4WVALID_delay); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[10]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[11]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[12]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[13]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[14]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[15]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[16]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[17]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[18]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[19]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[20]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[21]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[22]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[23]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[24]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[25]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[26]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[27]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[28]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[29]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[30]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[31]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[32]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[33]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[34]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[35]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[36]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[37]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[38]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[39]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[3]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[40]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[41]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[42]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[43]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[44]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[45]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[46]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[47]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[48]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[4]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[5]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[6]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[7]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[8]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[9]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARBURST_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARBURST_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[3]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[3]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[4]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[5]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[3]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[4]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[5]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[6]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[7]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLOCK_delay); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[3]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[0]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[1]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[2]); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARUSER_delay); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARVALID_delay); + $setuphold (posedge SAXIGP5RCLK, negedge SAXIGP5RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5RREADY_delay); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[10]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[11]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[12]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[13]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[14]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[15]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[16]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[17]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[18]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[19]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[20]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[21]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[22]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[23]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[24]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[25]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[26]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[27]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[28]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[29]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[30]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[31]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[32]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[33]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[34]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[35]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[36]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[37]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[38]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[39]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[3]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[40]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[41]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[42]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[43]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[44]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[45]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[46]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[47]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[48]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[4]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[5]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[6]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[7]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[8]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARADDR_delay[9]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARBURST_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARBURST_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARCACHE_delay[3]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[3]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[4]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARID_delay[5]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[3]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[4]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[5]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[6]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLEN_delay[7]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARLOCK_delay); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARPROT_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARQOS_delay[3]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[0]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[1]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARSIZE_delay[2]); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARUSER_delay); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5ARVALID_delay); + $setuphold (posedge SAXIGP5RCLK, posedge SAXIGP5RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP5RCLK_delay, SAXIGP5RREADY_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[10]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[11]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[12]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[13]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[14]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[15]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[16]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[17]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[18]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[19]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[20]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[21]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[22]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[23]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[24]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[25]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[26]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[27]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[28]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[29]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[30]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[31]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[32]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[33]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[34]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[35]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[36]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[37]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[38]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[39]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[40]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[41]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[42]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[43]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[44]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[45]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[46]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[47]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[48]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[4]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[5]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[6]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[7]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[8]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[9]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWBURST_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWBURST_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[4]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[5]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[4]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[5]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[6]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[7]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLOCK_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWUSER_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWVALID_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5BREADY_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[100]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[101]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[102]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[103]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[104]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[105]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[106]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[107]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[108]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[109]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[10]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[110]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[111]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[112]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[113]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[114]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[115]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[116]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[117]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[118]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[119]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[11]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[120]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[121]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[122]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[123]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[124]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[125]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[126]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[127]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[12]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[13]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[14]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[15]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[16]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[17]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[18]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[19]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[20]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[21]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[22]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[23]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[24]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[25]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[26]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[27]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[28]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[29]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[30]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[31]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[32]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[33]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[34]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[35]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[36]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[37]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[38]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[39]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[40]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[41]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[42]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[43]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[44]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[45]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[46]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[47]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[48]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[49]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[4]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[50]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[51]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[52]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[53]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[54]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[55]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[56]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[57]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[58]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[59]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[5]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[60]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[61]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[62]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[63]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[64]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[65]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[66]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[67]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[68]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[69]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[6]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[70]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[71]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[72]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[73]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[74]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[75]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[76]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[77]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[78]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[79]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[7]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[80]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[81]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[82]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[83]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[84]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[85]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[86]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[87]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[88]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[89]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[8]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[90]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[91]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[92]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[93]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[94]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[95]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[96]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[97]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[98]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[99]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[9]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WLAST_delay); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[0]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[10]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[11]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[12]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[13]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[14]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[15]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[1]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[2]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[3]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[4]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[5]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[6]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[7]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[8]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[9]); + $setuphold (posedge SAXIGP5WCLK, negedge SAXIGP5WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WVALID_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[10]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[11]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[12]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[13]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[14]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[15]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[16]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[17]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[18]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[19]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[20]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[21]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[22]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[23]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[24]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[25]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[26]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[27]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[28]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[29]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[30]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[31]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[32]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[33]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[34]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[35]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[36]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[37]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[38]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[39]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[40]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[41]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[42]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[43]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[44]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[45]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[46]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[47]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[48]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[4]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[5]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[6]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[7]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[8]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWADDR_delay[9]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWBURST_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWBURST_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWCACHE_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[4]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWID_delay[5]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[4]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[5]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[6]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLEN_delay[7]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWLOCK_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWPROT_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWQOS_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWSIZE_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWUSER_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5AWVALID_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5BREADY_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[100]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[101]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[102]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[103]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[104]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[105]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[106]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[107]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[108]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[109]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[10]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[110]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[111]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[112]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[113]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[114]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[115]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[116]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[117]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[118]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[119]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[11]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[120]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[121]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[122]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[123]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[124]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[125]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[126]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[127]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[12]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[13]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[14]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[15]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[16]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[17]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[18]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[19]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[20]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[21]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[22]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[23]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[24]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[25]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[26]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[27]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[28]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[29]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[30]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[31]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[32]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[33]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[34]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[35]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[36]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[37]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[38]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[39]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[40]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[41]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[42]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[43]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[44]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[45]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[46]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[47]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[48]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[49]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[4]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[50]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[51]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[52]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[53]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[54]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[55]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[56]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[57]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[58]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[59]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[5]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[60]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[61]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[62]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[63]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[64]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[65]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[66]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[67]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[68]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[69]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[6]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[70]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[71]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[72]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[73]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[74]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[75]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[76]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[77]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[78]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[79]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[7]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[80]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[81]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[82]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[83]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[84]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[85]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[86]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[87]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[88]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[89]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[8]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[90]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[91]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[92]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[93]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[94]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[95]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[96]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[97]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[98]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[99]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WDATA_delay[9]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WLAST_delay); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[0]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[10]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[11]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[12]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[13]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[14]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[15]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[1]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[2]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[3]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[4]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[5]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[6]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[7]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[8]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WSTRB_delay[9]); + $setuphold (posedge SAXIGP5WCLK, posedge SAXIGP5WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP5WCLK_delay, SAXIGP5WVALID_delay); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[10]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[11]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[12]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[13]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[14]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[15]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[16]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[17]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[18]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[19]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[20]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[21]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[22]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[23]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[24]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[25]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[26]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[27]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[28]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[29]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[30]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[31]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[32]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[33]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[34]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[35]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[36]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[37]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[38]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[39]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[3]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[40]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[41]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[42]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[43]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[44]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[45]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[46]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[47]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[48]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[4]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[5]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[6]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[7]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[8]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[9]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARBURST_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARBURST_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[3]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[3]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[4]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[5]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[3]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[4]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[5]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[6]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[7]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLOCK_delay); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[3]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[0]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[1]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[2]); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARUSER_delay); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARVALID_delay); + $setuphold (posedge SAXIGP6RCLK, negedge SAXIGP6RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6RREADY_delay); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[10]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[11]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[12]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[13]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[14]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[15]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[16]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[17]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[18]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[19]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[20]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[21]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[22]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[23]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[24]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[25]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[26]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[27]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[28]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[29]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[30]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[31]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[32]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[33]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[34]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[35]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[36]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[37]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[38]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[39]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[3]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[40]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[41]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[42]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[43]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[44]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[45]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[46]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[47]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[48]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[4]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[5]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[6]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[7]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[8]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARADDR_delay[9]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARBURST_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARBURST_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARCACHE_delay[3]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[3]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[4]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARID_delay[5]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[3]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[4]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[5]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[6]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLEN_delay[7]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARLOCK_delay); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARPROT_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARQOS_delay[3]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[0]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[1]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARSIZE_delay[2]); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARUSER_delay); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6ARVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6ARVALID_delay); + $setuphold (posedge SAXIGP6RCLK, posedge SAXIGP6RREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP6RCLK_delay, SAXIGP6RREADY_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[10]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[11]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[12]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[13]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[14]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[15]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[16]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[17]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[18]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[19]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[20]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[21]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[22]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[23]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[24]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[25]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[26]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[27]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[28]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[29]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[30]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[31]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[32]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[33]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[34]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[35]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[36]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[37]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[38]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[39]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[40]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[41]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[42]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[43]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[44]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[45]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[46]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[47]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[48]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[4]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[5]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[6]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[7]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[8]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[9]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWBURST_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWBURST_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[4]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[5]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[4]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[5]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[6]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[7]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLOCK_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWUSER_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWVALID_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6BREADY_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[100]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[101]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[102]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[103]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[104]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[105]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[106]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[107]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[108]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[109]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[10]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[110]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[111]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[112]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[113]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[114]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[115]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[116]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[117]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[118]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[119]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[11]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[120]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[121]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[122]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[123]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[124]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[125]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[126]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[127]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[12]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[13]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[14]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[15]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[16]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[17]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[18]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[19]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[20]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[21]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[22]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[23]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[24]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[25]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[26]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[27]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[28]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[29]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[30]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[31]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[32]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[33]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[34]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[35]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[36]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[37]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[38]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[39]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[40]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[41]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[42]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[43]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[44]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[45]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[46]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[47]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[48]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[49]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[4]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[50]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[51]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[52]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[53]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[54]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[55]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[56]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[57]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[58]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[59]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[5]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[60]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[61]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[62]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[63]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[64]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[65]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[66]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[67]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[68]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[69]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[6]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[70]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[71]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[72]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[73]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[74]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[75]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[76]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[77]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[78]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[79]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[7]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[80]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[81]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[82]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[83]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[84]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[85]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[86]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[87]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[88]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[89]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[8]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[90]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[91]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[92]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[93]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[94]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[95]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[96]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[97]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[98]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[99]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[9]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WLAST_delay); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[0]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[10]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[11]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[12]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[13]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[14]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[15]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[1]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[2]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[3]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[4]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[5]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[6]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[7]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[8]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[9]); + $setuphold (posedge SAXIGP6WCLK, negedge SAXIGP6WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WVALID_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[10]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[11]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[12]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[13]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[14]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[15]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[16]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[17]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[18]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[19]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[20]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[21]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[22]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[23]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[24]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[25]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[26]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[27]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[28]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[29]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[30]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[31]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[32]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[33]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[34]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[35]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[36]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[37]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[38]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[39]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[40]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[41]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[42]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[43]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[44]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[45]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[46]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[47]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[48]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[4]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[5]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[6]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[7]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[8]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWADDR[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWADDR_delay[9]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWBURST[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWBURST_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWBURST[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWBURST_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWCACHE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWCACHE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWCACHE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWCACHE[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWCACHE_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[4]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWID[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWID_delay[5]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[4]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[5]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[6]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLEN[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLEN_delay[7]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWLOCK, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWLOCK_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWPROT[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWPROT[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWPROT[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWPROT_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWQOS[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWQOS[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWQOS[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWQOS[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWQOS_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWSIZE[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWSIZE[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWSIZE[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWSIZE_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWUSER, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWUSER_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6AWVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6AWVALID_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6BREADY, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6BREADY_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[100], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[100]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[101], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[101]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[102], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[102]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[103], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[103]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[104], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[104]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[105], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[105]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[106], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[106]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[107], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[107]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[108], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[108]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[109], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[109]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[10]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[110], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[110]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[111], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[111]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[112], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[112]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[113], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[113]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[114], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[114]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[115], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[115]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[116], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[116]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[117], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[117]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[118], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[118]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[119], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[119]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[11]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[120], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[120]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[121], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[121]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[122], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[122]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[123], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[123]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[124], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[124]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[125], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[125]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[126], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[126]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[127], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[127]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[12]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[13]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[14]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[15]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[16], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[16]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[17], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[17]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[18], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[18]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[19], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[19]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[20], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[20]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[21], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[21]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[22], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[22]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[23], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[23]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[24], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[24]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[25], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[25]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[26], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[26]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[27], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[27]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[28], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[28]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[29], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[29]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[30], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[30]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[31], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[31]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[32], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[32]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[33], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[33]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[34], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[34]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[35], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[35]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[36], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[36]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[37], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[37]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[38], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[38]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[39], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[39]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[40], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[40]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[41], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[41]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[42], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[42]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[43], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[43]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[44], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[44]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[45], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[45]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[46], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[46]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[47], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[47]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[48], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[48]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[49], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[49]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[4]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[50], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[50]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[51], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[51]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[52], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[52]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[53], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[53]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[54], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[54]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[55], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[55]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[56], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[56]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[57], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[57]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[58], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[58]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[59], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[59]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[5]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[60], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[60]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[61], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[61]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[62], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[62]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[63], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[63]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[64], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[64]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[65], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[65]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[66], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[66]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[67], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[67]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[68], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[68]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[69], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[69]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[6]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[70], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[70]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[71], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[71]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[72], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[72]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[73], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[73]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[74], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[74]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[75], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[75]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[76], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[76]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[77], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[77]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[78], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[78]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[79], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[79]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[7]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[80], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[80]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[81], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[81]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[82], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[82]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[83], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[83]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[84], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[84]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[85], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[85]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[86], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[86]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[87], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[87]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[88], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[88]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[89], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[89]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[8]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[90], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[90]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[91], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[91]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[92], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[92]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[93], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[93]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[94], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[94]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[95], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[95]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[96], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[96]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[97], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[97]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[98], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[98]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[99], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[99]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WDATA[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WDATA_delay[9]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WLAST, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WLAST_delay); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[0], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[0]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[10], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[10]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[11], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[11]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[12], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[12]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[13], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[13]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[14], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[14]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[15], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[15]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[1], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[1]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[2], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[2]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[3], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[3]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[4], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[4]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[5], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[5]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[6], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[6]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[7], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[7]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[8], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[8]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WSTRB[9], 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WSTRB_delay[9]); + $setuphold (posedge SAXIGP6WCLK, posedge SAXIGP6WVALID, 0:0:0, 0:0:0, notifier, , , SAXIGP6WCLK_delay, SAXIGP6WVALID_delay); + $width (negedge ADMAFCICLK[0], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[1], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[2], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[3], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[4], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[5], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[6], 0:0:0, 0, notifier); + $width (negedge ADMAFCICLK[7], 0:0:0, 0, notifier); + $width (negedge DDRCREFRESHPLCLK, 0:0:0, 0, notifier); + $width (negedge DPSAXISAUDIOCLK, 0:0:0, 0, notifier); + $width (negedge DPVIDEOINCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET0GMIIRXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET0GMIITXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET1GMIIRXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET1GMIITXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET2GMIIRXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET2GMIITXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET3GMIIRXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENET3GMIITXCLK, 0:0:0, 0, notifier); + $width (negedge EMIOENETTSUCLK, 0:0:0, 0, notifier); + $width (negedge EMIOSDIO0FBCLKIN, 0:0:0, 0, notifier); + $width (negedge EMIOSDIO1FBCLKIN, 0:0:0, 0, notifier); + $width (negedge EMIOSPI0SCLKI, 0:0:0, 0, notifier); + $width (negedge EMIOSPI1SCLKI, 0:0:0, 0, notifier); + $width (negedge EMIOTTC0CLKI[0], 0:0:0, 0, notifier); + $width (negedge EMIOTTC0CLKI[1], 0:0:0, 0, notifier); + $width (negedge EMIOTTC0CLKI[2], 0:0:0, 0, notifier); + $width (negedge EMIOTTC1CLKI[0], 0:0:0, 0, notifier); + $width (negedge EMIOTTC1CLKI[1], 0:0:0, 0, notifier); + $width (negedge EMIOTTC1CLKI[2], 0:0:0, 0, notifier); + $width (negedge EMIOTTC2CLKI[0], 0:0:0, 0, notifier); + $width (negedge EMIOTTC2CLKI[1], 0:0:0, 0, notifier); + $width (negedge EMIOTTC2CLKI[2], 0:0:0, 0, notifier); + $width (negedge EMIOTTC3CLKI[0], 0:0:0, 0, notifier); + $width (negedge EMIOTTC3CLKI[1], 0:0:0, 0, notifier); + $width (negedge EMIOTTC3CLKI[2], 0:0:0, 0, notifier); + $width (negedge EMIOWDT0CLKI, 0:0:0, 0, notifier); + $width (negedge EMIOWDT1CLKI, 0:0:0, 0, notifier); + $width (negedge FMIOGEM0FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM0FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM1FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM1FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM2FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM2FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM3FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEM3FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge FMIOGEMTSUCLKFROMPL, 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[0], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[1], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[2], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[3], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[4], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[5], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[6], 0:0:0, 0, notifier); + $width (negedge GDMAFCICLK[7], 0:0:0, 0, notifier); + $width (negedge MAXIGP0ACLK, 0:0:0, 0, notifier); + $width (negedge MAXIGP1ACLK, 0:0:0, 0, notifier); + $width (negedge MAXIGP2ACLK, 0:0:0, 0, notifier); + $width (negedge PLACECLK, 0:0:0, 0, notifier); + $width (negedge PLLAUXREFCLKFPD[0], 0:0:0, 0, notifier); + $width (negedge PLLAUXREFCLKFPD[1], 0:0:0, 0, notifier); + $width (negedge PLLAUXREFCLKFPD[2], 0:0:0, 0, notifier); + $width (negedge PLLAUXREFCLKLPD[0], 0:0:0, 0, notifier); + $width (negedge PLLAUXREFCLKLPD[1], 0:0:0, 0, notifier); + $width (negedge PLPSTRACECLK, 0:0:0, 0, notifier); + $width (negedge SAXIACPACLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP0RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP0WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP1RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP1WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP2RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP2WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP3RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP3WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP4RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP4WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP5RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP5WCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP6RCLK, 0:0:0, 0, notifier); + $width (negedge SAXIGP6WCLK, 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[0], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[1], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[2], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[3], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[4], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[5], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[6], 0:0:0, 0, notifier); + $width (posedge ADMAFCICLK[7], 0:0:0, 0, notifier); + $width (posedge DDRCREFRESHPLCLK, 0:0:0, 0, notifier); + $width (posedge DPSAXISAUDIOCLK, 0:0:0, 0, notifier); + $width (posedge DPVIDEOINCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET0GMIIRXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET0GMIITXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET1GMIIRXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET1GMIITXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET2GMIIRXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET2GMIITXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET3GMIIRXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENET3GMIITXCLK, 0:0:0, 0, notifier); + $width (posedge EMIOENETTSUCLK, 0:0:0, 0, notifier); + $width (posedge EMIOSDIO0FBCLKIN, 0:0:0, 0, notifier); + $width (posedge EMIOSDIO1FBCLKIN, 0:0:0, 0, notifier); + $width (posedge EMIOSPI0SCLKI, 0:0:0, 0, notifier); + $width (posedge EMIOSPI1SCLKI, 0:0:0, 0, notifier); + $width (posedge EMIOTTC0CLKI[0], 0:0:0, 0, notifier); + $width (posedge EMIOTTC0CLKI[1], 0:0:0, 0, notifier); + $width (posedge EMIOTTC0CLKI[2], 0:0:0, 0, notifier); + $width (posedge EMIOTTC1CLKI[0], 0:0:0, 0, notifier); + $width (posedge EMIOTTC1CLKI[1], 0:0:0, 0, notifier); + $width (posedge EMIOTTC1CLKI[2], 0:0:0, 0, notifier); + $width (posedge EMIOTTC2CLKI[0], 0:0:0, 0, notifier); + $width (posedge EMIOTTC2CLKI[1], 0:0:0, 0, notifier); + $width (posedge EMIOTTC2CLKI[2], 0:0:0, 0, notifier); + $width (posedge EMIOTTC3CLKI[0], 0:0:0, 0, notifier); + $width (posedge EMIOTTC3CLKI[1], 0:0:0, 0, notifier); + $width (posedge EMIOTTC3CLKI[2], 0:0:0, 0, notifier); + $width (posedge EMIOWDT0CLKI, 0:0:0, 0, notifier); + $width (posedge EMIOWDT1CLKI, 0:0:0, 0, notifier); + $width (posedge FMIOGEM0FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM0FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM1FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM1FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM2FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM2FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM3FIFORXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEM3FIFOTXCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge FMIOGEMTSUCLKFROMPL, 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[0], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[1], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[2], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[3], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[4], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[5], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[6], 0:0:0, 0, notifier); + $width (posedge GDMAFCICLK[7], 0:0:0, 0, notifier); + $width (posedge MAXIGP0ACLK, 0:0:0, 0, notifier); + $width (posedge MAXIGP1ACLK, 0:0:0, 0, notifier); + $width (posedge MAXIGP2ACLK, 0:0:0, 0, notifier); + $width (posedge PLACECLK, 0:0:0, 0, notifier); + $width (posedge PLLAUXREFCLKFPD[0], 0:0:0, 0, notifier); + $width (posedge PLLAUXREFCLKFPD[1], 0:0:0, 0, notifier); + $width (posedge PLLAUXREFCLKFPD[2], 0:0:0, 0, notifier); + $width (posedge PLLAUXREFCLKLPD[0], 0:0:0, 0, notifier); + $width (posedge PLLAUXREFCLKLPD[1], 0:0:0, 0, notifier); + $width (posedge PLPSTRACECLK, 0:0:0, 0, notifier); + $width (posedge SAXIACPACLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP0RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP0WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP1RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP1WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP2RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP2WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP3RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP3WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP4RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP4WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP5RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP5WCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP6RCLK, 0:0:0, 0, notifier); + $width (posedge SAXIGP6WCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/PULLDOWN.v b/verilog/src/unisims/PULLDOWN.v new file mode 100644 index 0000000..cf0f686 --- /dev/null +++ b/verilog/src/unisims/PULLDOWN.v @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Resistor to GND +// /___/ /\ Filename : PULLDOWN.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +`celldefine + +module PULLDOWN (O); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + + wire A; + + pulldown (A); + buf (weak0,weak1) #(100,100) (O,A); + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/PULLUP.v b/verilog/src/unisims/PULLUP.v new file mode 100644 index 0000000..7a89f2c --- /dev/null +++ b/verilog/src/unisims/PULLUP.v @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Resistor to VCC +// /___/ /\ Filename : PULLUP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +`celldefine + +module PULLUP (O); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + + wire A; + + pullup (A); + buf (weak0,weak1) #(100,100) (O,A); + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/RAM128X1D.v b/verilog/src/unisims/RAM128X1D.v new file mode 100644 index 0000000..3a4b9bd --- /dev/null +++ b/verilog/src/unisims/RAM128X1D.v @@ -0,0 +1,184 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Dual Port Synchronous RAM 128-Deep by 1-Wide +// /___/ /\ Filename : RAM128X1D.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 01/18/08 - Add support for negative setup/hold timing check (CR457308). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM128X1D #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [127:0] INIT = 128'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output DPO, + output SPO, + + input [6:0] A, + input D, + input [6:0] DPRA, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM128X1D"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [6:0] A_in; + wire [6:0] DPRA_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [6:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = A; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + assign DPRA_in = DPRA; + + reg [127:0] mem; + + initial + mem = INIT; + + assign DPO = mem[DPRA_in]; + assign SPO = mem[A_in]; + + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DPO) = (0:0:0, 0:0:0); + (WCLK => SPO) = (0:0:0, 0:0:0); + (A[0] => SPO) = (0:0:0, 0:0:0); + (A[1] => SPO) = (0:0:0, 0:0:0); + (A[2] => SPO) = (0:0:0, 0:0:0); + (A[3] => SPO) = (0:0:0, 0:0:0); + (A[4] => SPO) = (0:0:0, 0:0:0); + (A[5] => SPO) = (0:0:0, 0:0:0); + (A[6] => SPO) = (0:0:0, 0:0:0); + (DPRA[0] => DPO) = (0:0:0, 0:0:0); + (DPRA[1] => DPO) = (0:0:0, 0:0:0); + (DPRA[2] => DPO) = (0:0:0, 0:0:0); + (DPRA[3] => DPO) = (0:0:0, 0:0:0); + (DPRA[4] => DPO) = (0:0:0, 0:0:0); + (DPRA[5] => DPO) = (0:0:0, 0:0:0); + (DPRA[6] => DPO) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM128X1S.v b/verilog/src/unisims/RAM128X1S.v new file mode 100644 index 0000000..77792c0 --- /dev/null +++ b/verilog/src/unisims/RAM128X1S.v @@ -0,0 +1,175 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Synchronous RAM 128-Deep by 1-Wide +// /___/ /\ Filename : RAM128X1S.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM128X1S #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [127:0] INIT = 128'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output O, + + input A0, + input A1, + input A2, + input A3, + input A4, + input A5, + input A6, + input D, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM128X1S"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [6:0] A_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [6:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = {A6, A5, A4, A3, A2, A1, A0}; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + reg [127:0] mem; + + initial + mem = INIT; + + assign O = mem[A_in]; + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => O) = (0:0:0, 0:0:0); + (A0 => O) = (0:0:0, 0:0:0); + (A1 => O) = (0:0:0, 0:0:0); + (A2 => O) = (0:0:0, 0:0:0); + (A3 => O) = (0:0:0, 0:0:0); + (A4 => O) = (0:0:0, 0:0:0); + (A5 => O) = (0:0:0, 0:0:0); + (A6 => O) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge A6, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge A6, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge A6, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge A6, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM256X1D.v b/verilog/src/unisims/RAM256X1D.v new file mode 100644 index 0000000..dfec034 --- /dev/null +++ b/verilog/src/unisims/RAM256X1D.v @@ -0,0 +1,186 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Dual Port Synchronous RAM 256-Deep by 1-Wide +// /___/ /\ Filename : RAM256X1D.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/12 - Initial version, from RAM128X1D +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM256X1D #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [255:0] INIT = 256'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output DPO, + output SPO, + + input [7:0] A, + input D, + input [7:0] DPRA, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM256X1D"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [7:0] A_in; + wire [7:0] DPRA_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [7:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = A; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + assign DPRA_in = DPRA; + + reg [255:0] mem; + + initial + mem = INIT; + + assign DPO = mem[DPRA_in]; + assign SPO = mem[A_in]; + + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DPO) = (0:0:0, 0:0:0); + (WCLK => SPO) = (0:0:0, 0:0:0); + (A[0] => SPO) = (0:0:0, 0:0:0); + (A[1] => SPO) = (0:0:0, 0:0:0); + (A[2] => SPO) = (0:0:0, 0:0:0); + (A[3] => SPO) = (0:0:0, 0:0:0); + (A[4] => SPO) = (0:0:0, 0:0:0); + (A[5] => SPO) = (0:0:0, 0:0:0); + (A[6] => SPO) = (0:0:0, 0:0:0); + (A[7] => SPO) = (0:0:0, 0:0:0); + (DPRA[0] => DPO) = (0:0:0, 0:0:0); + (DPRA[1] => DPO) = (0:0:0, 0:0:0); + (DPRA[2] => DPO) = (0:0:0, 0:0:0); + (DPRA[3] => DPO) = (0:0:0, 0:0:0); + (DPRA[4] => DPO) = (0:0:0, 0:0:0); + (DPRA[5] => DPO) = (0:0:0, 0:0:0); + (DPRA[6] => DPO) = (0:0:0, 0:0:0); + (DPRA[7] => DPO) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM256X1S.v b/verilog/src/unisims/RAM256X1S.v new file mode 100644 index 0000000..1f413f5 --- /dev/null +++ b/verilog/src/unisims/RAM256X1S.v @@ -0,0 +1,167 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Synchronous RAM 256-Deep by 1-Wide +// /___/ /\ Filename : RAM256X1S.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM256X1S #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [255:0] INIT = 256'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output O, + + input [7:0] A, + input D, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM256X1S"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [7:0] A_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [7:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = A; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + reg [255:0] mem; + + initial + mem = INIT; + + assign O = mem[A_in]; + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => O) = (0:0:0, 0:0:0); + (A *> O) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM32M.v b/verilog/src/unisims/RAM32M.v new file mode 100644 index 0000000..0b8fa82 --- /dev/null +++ b/verilog/src/unisims/RAM32M.v @@ -0,0 +1,259 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 32-Deep by 8-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM32M.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/21/06 - Initial version. +// 12/01/06 - Fix cut/past error for port C and D (CR 430051) +// 05/07/08 - Add negative setup/hold support (CR468872) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM32M #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT_A = 64'h0000000000000000, + parameter [63:0] INIT_B = 64'h0000000000000000, + parameter [63:0] INIT_C = 64'h0000000000000000, + parameter [63:0] INIT_D = 64'h0000000000000000, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM32M"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire [4:0] ADDRD_in; + wire [1:0] DIA_in; + wire [1:0] DIB_in; + wire [1:0] DIC_in; + wire [1:0] DID_in; + wire WCLK_in; + wire WE_in; + +`ifdef XIL_TIMING + wire [4:0] ADDRD_dly; + wire [1:0] DIA_dly; + wire [1:0] DIB_dly; + wire [1:0] DIC_dly; + wire [1:0] DID_dly; + wire WCLK_dly; + wire WE_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign ADDRD_in = ADDRD_dly; + assign DIA_in = DIA_dly; + assign DIB_in = DIB_dly; + assign DIC_in = DIC_dly; + assign DID_in = DID_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign ADDRD_in = ADDRD; + assign DIA_in = DIA; + assign DIB_in = DIB; + assign DIC_in = DIC; + assign DID_in = DID; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + reg [5:0] addr_in2, addr_in1; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + end + + always @(ADDRD_in) begin + addr_in2 = 2 * ADDRD_in; + addr_in1 = 2 * ADDRD_in + 1; + end + + always @(posedge WCLK_in) + if (WE_in) begin + mem_a[addr_in2] <= #100 DIA_in[0]; + mem_a[addr_in1] <= #100 DIA_in[1]; + mem_b[addr_in2] <= #100 DIB_in[0]; + mem_b[addr_in1] <= #100 DIB_in[1]; + mem_c[addr_in2] <= #100 DIC_in[0]; + mem_c[addr_in1] <= #100 DIC_in[1]; + mem_d[addr_in2] <= #100 DID_in[0]; + mem_d[addr_in1] <= #100 DID_in[1]; + end + + assign DOA[0] = mem_a[2*ADDRA]; + assign DOA[1] = mem_a[2*ADDRA + 1]; + assign DOB[0] = mem_b[2*ADDRB]; + assign DOB[1] = mem_b[2*ADDRB + 1]; + assign DOC[0] = mem_c[2*ADDRC]; + assign DOC[1] = mem_c[2*ADDRC + 1]; + assign DOD[0] = mem_d[2*ADDRD_in]; + assign DOD[1] = mem_d[2*ADDRD_in + 1]; + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[addr_in2] <= 1'bx; + mem_a[addr_in1] <= 1'bx; + mem_b[addr_in2] <= 1'bx; + mem_b[addr_in1] <= 1'bx; + mem_c[addr_in2] <= 1'bx; + mem_c[addr_in1] <= 1'bx; + mem_d[addr_in2] <= 1'bx; + mem_d[addr_in1] <= 1'bx; + end + + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DOA[0]) = (0:0:0, 0:0:0); + (WCLK => DOA[1]) = (0:0:0, 0:0:0); + (WCLK => DOB[0]) = (0:0:0, 0:0:0); + (WCLK => DOB[1]) = (0:0:0, 0:0:0); + (WCLK => DOC[0]) = (0:0:0, 0:0:0); + (WCLK => DOC[1]) = (0:0:0, 0:0:0); + (WCLK => DOD[0]) = (0:0:0, 0:0:0); + (WCLK => DOD[1]) = (0:0:0, 0:0:0); + (ADDRA *> DOA[0]) = (0:0:0, 0:0:0); + (ADDRA *> DOA[1]) = (0:0:0, 0:0:0); + (ADDRB *> DOB[0]) = (0:0:0, 0:0:0); + (ADDRB *> DOB[1]) = (0:0:0, 0:0:0); + (ADDRC *> DOC[0]) = (0:0:0, 0:0:0); + (ADDRC *> DOC[1]) = (0:0:0, 0:0:0); + (ADDRD *> DOD[0]) = (0:0:0, 0:0:0); + (ADDRD *> DOD[1]) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]); + $setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]); + $setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]); + $setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]); + $setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]); + $setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]); + $setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]); + $setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]); + $setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]); + $setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]); + $setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]); + $setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]); + $setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]); + $setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]); + $setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]); + $setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]); + $setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]); + $setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]); + $setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]); + $setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]); + $setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM32M16.v b/verilog/src/unisims/RAM32M16.v new file mode 100644 index 0000000..ecf48e0 --- /dev/null +++ b/verilog/src/unisims/RAM32M16.v @@ -0,0 +1,364 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 32-Deep by 16-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM32M16.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/12 - Initial version, from RAM32M +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM32M16 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT_A = 64'h0000000000000000, + parameter [63:0] INIT_B = 64'h0000000000000000, + parameter [63:0] INIT_C = 64'h0000000000000000, + parameter [63:0] INIT_D = 64'h0000000000000000, + parameter [63:0] INIT_E = 64'h0000000000000000, + parameter [63:0] INIT_F = 64'h0000000000000000, + parameter [63:0] INIT_G = 64'h0000000000000000, + parameter [63:0] INIT_H = 64'h0000000000000000, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + output [1:0] DOE, + output [1:0] DOF, + output [1:0] DOG, + output [1:0] DOH, + + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [4:0] ADDRE, + input [4:0] ADDRF, + input [4:0] ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM32M16"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire [4:0] ADDRH_in; + wire [1:0] DIA_in; + wire [1:0] DIB_in; + wire [1:0] DIC_in; + wire [1:0] DID_in; + wire [1:0] DIE_in; + wire [1:0] DIF_in; + wire [1:0] DIG_in; + wire [1:0] DIH_in; + wire WCLK_in; + wire WE_in; + +`ifdef XIL_TIMING + wire [4:0] ADDRH_dly; + wire [1:0] DIA_dly; + wire [1:0] DIB_dly; + wire [1:0] DIC_dly; + wire [1:0] DID_dly; + wire [1:0] DIE_dly; + wire [1:0] DIF_dly; + wire [1:0] DIG_dly; + wire [1:0] DIH_dly; + wire WCLK_dly; + wire WE_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign ADDRH_in = ADDRH_dly; + assign DIA_in = DIA_dly; + assign DIB_in = DIB_dly; + assign DIC_in = DIC_dly; + assign DID_in = DID_dly; + assign DIE_in = DIE_dly; + assign DIF_in = DIF_dly; + assign DIG_in = DIG_dly; + assign DIH_in = DIH_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign ADDRH_in = ADDRH; + assign DIA_in = DIA; + assign DIB_in = DIB; + assign DIC_in = DIC; + assign DID_in = DID; + assign DIE_in = DIE; + assign DIF_in = DIF; + assign DIG_in = DIG; + assign DIH_in = DIH; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + reg [63:0] mem_e, mem_f, mem_g, mem_h; + reg [5:0] addr_in2, addr_in1; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + mem_e = INIT_E; + mem_f = INIT_F; + mem_g = INIT_G; + mem_h = INIT_H; + end + + always @(ADDRH_in) begin + addr_in2 = 2 * ADDRH_in; + addr_in1 = 2 * ADDRH_in + 1; + end + + always @(posedge WCLK_in) + if (WE_in) begin + mem_a[addr_in2] <= #100 DIA_in[0]; + mem_a[addr_in1] <= #100 DIA_in[1]; + mem_b[addr_in2] <= #100 DIB_in[0]; + mem_b[addr_in1] <= #100 DIB_in[1]; + mem_c[addr_in2] <= #100 DIC_in[0]; + mem_c[addr_in1] <= #100 DIC_in[1]; + mem_d[addr_in2] <= #100 DID_in[0]; + mem_d[addr_in1] <= #100 DID_in[1]; + mem_e[addr_in2] <= #100 DIE_in[0]; + mem_e[addr_in1] <= #100 DIE_in[1]; + mem_f[addr_in2] <= #100 DIF_in[0]; + mem_f[addr_in1] <= #100 DIF_in[1]; + mem_g[addr_in2] <= #100 DIG_in[0]; + mem_g[addr_in1] <= #100 DIG_in[1]; + mem_h[addr_in2] <= #100 DIH_in[0]; + mem_h[addr_in1] <= #100 DIH_in[1]; + end + + assign DOA[0] = mem_a[2*ADDRA]; + assign DOA[1] = mem_a[2*ADDRA + 1]; + assign DOB[0] = mem_b[2*ADDRB]; + assign DOB[1] = mem_b[2*ADDRB + 1]; + assign DOC[0] = mem_c[2*ADDRC]; + assign DOC[1] = mem_c[2*ADDRC + 1]; + assign DOD[0] = mem_d[2*ADDRD]; + assign DOD[1] = mem_d[2*ADDRD + 1]; + assign DOE[0] = mem_e[2*ADDRE]; + assign DOE[1] = mem_e[2*ADDRE + 1]; + assign DOF[0] = mem_f[2*ADDRF]; + assign DOF[1] = mem_f[2*ADDRF + 1]; + assign DOG[0] = mem_g[2*ADDRG]; + assign DOG[1] = mem_g[2*ADDRG + 1]; + assign DOH[0] = mem_h[2*ADDRH_in]; + assign DOH[1] = mem_h[2*ADDRH_in + 1]; + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[addr_in2] <= 1'bx; + mem_a[addr_in1] <= 1'bx; + mem_b[addr_in2] <= 1'bx; + mem_b[addr_in1] <= 1'bx; + mem_c[addr_in2] <= 1'bx; + mem_c[addr_in1] <= 1'bx; + mem_d[addr_in2] <= 1'bx; + mem_d[addr_in1] <= 1'bx; + mem_e[addr_in2] <= 1'bx; + mem_e[addr_in1] <= 1'bx; + mem_f[addr_in2] <= 1'bx; + mem_f[addr_in1] <= 1'bx; + mem_g[addr_in2] <= 1'bx; + mem_g[addr_in1] <= 1'bx; + mem_h[addr_in2] <= 1'bx; + mem_h[addr_in1] <= 1'bx; + end + + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DOA[0]) = (0:0:0, 0:0:0); + (WCLK => DOA[1]) = (0:0:0, 0:0:0); + (WCLK => DOB[0]) = (0:0:0, 0:0:0); + (WCLK => DOB[1]) = (0:0:0, 0:0:0); + (WCLK => DOC[0]) = (0:0:0, 0:0:0); + (WCLK => DOC[1]) = (0:0:0, 0:0:0); + (WCLK => DOD[0]) = (0:0:0, 0:0:0); + (WCLK => DOD[1]) = (0:0:0, 0:0:0); + (WCLK => DOE[0]) = (0:0:0, 0:0:0); + (WCLK => DOE[1]) = (0:0:0, 0:0:0); + (WCLK => DOF[0]) = (0:0:0, 0:0:0); + (WCLK => DOF[1]) = (0:0:0, 0:0:0); + (WCLK => DOG[0]) = (0:0:0, 0:0:0); + (WCLK => DOG[1]) = (0:0:0, 0:0:0); + (WCLK => DOH[0]) = (0:0:0, 0:0:0); + (WCLK => DOH[1]) = (0:0:0, 0:0:0); + (ADDRA *> DOA[0]) = (0:0:0, 0:0:0); + (ADDRA *> DOA[1]) = (0:0:0, 0:0:0); + (ADDRB *> DOB[0]) = (0:0:0, 0:0:0); + (ADDRB *> DOB[1]) = (0:0:0, 0:0:0); + (ADDRC *> DOC[0]) = (0:0:0, 0:0:0); + (ADDRC *> DOC[1]) = (0:0:0, 0:0:0); + (ADDRD *> DOD[0]) = (0:0:0, 0:0:0); + (ADDRD *> DOD[1]) = (0:0:0, 0:0:0); + (ADDRE *> DOE[0]) = (0:0:0, 0:0:0); + (ADDRE *> DOE[1]) = (0:0:0, 0:0:0); + (ADDRF *> DOF[0]) = (0:0:0, 0:0:0); + (ADDRF *> DOF[1]) = (0:0:0, 0:0:0); + (ADDRG *> DOG[0]) = (0:0:0, 0:0:0); + (ADDRG *> DOG[1]) = (0:0:0, 0:0:0); + (ADDRH *> DOH[0]) = (0:0:0, 0:0:0); + (ADDRH *> DOH[1]) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]); + $setuphold (negedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]); + $setuphold (negedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]); + $setuphold (negedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]); + $setuphold (negedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]); + $setuphold (negedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]); + $setuphold (negedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]); + $setuphold (negedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]); + $setuphold (negedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]); + $setuphold (negedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]); + $setuphold (negedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]); + $setuphold (negedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]); + $setuphold (negedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]); + $setuphold (negedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]); + $setuphold (negedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]); + $setuphold (posedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]); + $setuphold (posedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]); + $setuphold (posedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]); + $setuphold (posedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]); + $setuphold (posedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]); + $setuphold (posedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]); + $setuphold (posedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]); + $setuphold (posedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]); + $setuphold (posedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]); + $setuphold (posedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]); + $setuphold (posedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]); + $setuphold (posedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]); + $setuphold (posedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]); + $setuphold (posedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM32X16DR8.v b/verilog/src/unisims/RAM32X16DR8.v new file mode 100755 index 0000000..5f5f23d --- /dev/null +++ b/verilog/src/unisims/RAM32X16DR8.v @@ -0,0 +1,359 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RAM32X16DR8 +// /___/ /\ Filename : RAM32X16DR8.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM32X16DR8 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output [1:0] DOH, + + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM32X16DR8"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAM32X16DR8_dr.v" +`else + reg [0:0] IS_WCLK_INVERTED_REG = IS_WCLK_INVERTED; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire WCLK_in; + wire WE_in; + wire [1:0] DIA_in; + wire [1:0] DIB_in; + wire [1:0] DIC_in; + wire [1:0] DID_in; + wire [1:0] DIE_in; + wire [1:0] DIF_in; + wire [1:0] DIG_in; + wire [1:0] DIH_in; + wire [4:0] ADDRH_in; + wire [5:0] ADDRA_in; + wire [5:0] ADDRB_in; + wire [5:0] ADDRC_in; + wire [5:0] ADDRD_in; + wire [5:0] ADDRE_in; + wire [5:0] ADDRF_in; + wire [5:0] ADDRG_in; + +`ifdef XIL_TIMING + wire [4:0] ADDRH_dly; + wire [1:0] DIA_dly; + wire [1:0] DIB_dly; + wire [1:0] DIC_dly; + wire [1:0] DID_dly; + wire [1:0] DIE_dly; + wire [1:0] DIF_dly; + wire [1:0] DIG_dly; + wire [1:0] DIH_dly; + wire WCLK_dly; + wire WE_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign ADDRA_in = ADDRA; + assign ADDRB_in = ADDRB; + assign ADDRC_in = ADDRC; + assign ADDRD_in = ADDRD; + assign ADDRE_in = ADDRE; + assign ADDRF_in = ADDRF; + assign ADDRG_in = ADDRG; + assign ADDRH_in = ADDRH_dly; + assign DIA_in = DIA_dly; + assign DIB_in = DIB_dly; + assign DIC_in = DIC_dly; + assign DID_in = DID_dly; + assign DIE_in = DIE_dly; + assign DIF_in = DIF_dly; + assign DIG_in = DIG_dly; + assign DIH_in = DIH_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_REG; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign ADDRA_in = ADDRA; + assign ADDRB_in = ADDRB; + assign ADDRC_in = ADDRC; + assign ADDRD_in = ADDRD; + assign ADDRE_in = ADDRE; + assign ADDRF_in = ADDRF; + assign ADDRG_in = ADDRG; + assign ADDRH_in = ADDRH; + assign DIA_in = DIA; + assign DIB_in = DIB; + assign DIC_in = DIC; + assign DID_in = DID; + assign DIE_in = DIE; + assign DIF_in = DIF; + assign DIG_in = DIG; + assign DIH_in = DIH; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_REG; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +// begin behavioral model + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + reg [63:0] mem_e, mem_f, mem_g, mem_h; + reg [5:0] addr_in1, addr_in2; + + always @(ADDRH_in) begin + addr_in1 = 2 * ADDRH_in; + addr_in2 = 2 * ADDRH_in + 1; + end + + always @(posedge WCLK_in) + if (WE_in) begin + mem_a[addr_in1] <= #100 DIA_in[0]; + mem_a[addr_in2] <= #100 DIA_in[1]; + mem_b[addr_in1] <= #100 DIB_in[0]; + mem_b[addr_in2] <= #100 DIB_in[1]; + mem_c[addr_in1] <= #100 DIC_in[0]; + mem_c[addr_in2] <= #100 DIC_in[1]; + mem_d[addr_in1] <= #100 DID_in[0]; + mem_d[addr_in2] <= #100 DID_in[1]; + mem_e[addr_in1] <= #100 DIE_in[0]; + mem_e[addr_in2] <= #100 DIE_in[1]; + mem_f[addr_in1] <= #100 DIF_in[0]; + mem_f[addr_in2] <= #100 DIF_in[1]; + mem_g[addr_in1] <= #100 DIG_in[0]; + mem_g[addr_in2] <= #100 DIG_in[1]; + mem_h[addr_in1] <= #100 DIH_in[0]; + mem_h[addr_in2] <= #100 DIH_in[1]; + end + + assign DOA = mem_a[ADDRA_in]; + assign DOB = mem_b[ADDRB_in]; + assign DOC = mem_c[ADDRC_in]; + assign DOD = mem_d[ADDRD_in]; + assign DOE = mem_e[ADDRE_in]; + assign DOF = mem_f[ADDRF_in]; + assign DOG = mem_g[ADDRG_in]; + assign DOH[0] = mem_h[2*ADDRH_in]; + assign DOH[1] = mem_h[2*ADDRH_in + 1]; + + +// end behavioral model + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[addr_in1] <= 1'bx; + mem_a[addr_in2] <= 1'bx; + mem_b[addr_in1] <= 1'bx; + mem_b[addr_in2] <= 1'bx; + mem_c[addr_in1] <= 1'bx; + mem_c[addr_in2] <= 1'bx; + mem_d[addr_in1] <= 1'bx; + mem_d[addr_in2] <= 1'bx; + mem_e[addr_in1] <= 1'bx; + mem_e[addr_in2] <= 1'bx; + mem_f[addr_in1] <= 1'bx; + mem_f[addr_in2] <= 1'bx; + mem_g[addr_in1] <= 1'bx; + mem_g[addr_in2] <= 1'bx; + mem_h[addr_in1] <= 1'bx; + mem_h[addr_in2] <= 1'bx; + end + + assign sh_clk_en_p = ~IS_WCLK_INVERTED_REG; + assign sh_clk_en_n = IS_WCLK_INVERTED_REG; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_REG; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_REG; + + specify + (WCLK => DOA) = (0:0:0, 0:0:0); + (WCLK => DOB) = (0:0:0, 0:0:0); + (WCLK => DOC) = (0:0:0, 0:0:0); + (WCLK => DOD) = (0:0:0, 0:0:0); + (WCLK => DOE) = (0:0:0, 0:0:0); + (WCLK => DOF) = (0:0:0, 0:0:0); + (WCLK => DOG) = (0:0:0, 0:0:0); + (WCLK => DOH[0]) = (0:0:0, 0:0:0); + (WCLK => DOH[1]) = (0:0:0, 0:0:0); + (ADDRA *> DOA) = (0:0:0, 0:0:0); + (ADDRB *> DOB) = (0:0:0, 0:0:0); + (ADDRC *> DOC) = (0:0:0, 0:0:0); + (ADDRD *> DOD) = (0:0:0, 0:0:0); + (ADDRE *> DOE) = (0:0:0, 0:0:0); + (ADDRF *> DOF) = (0:0:0, 0:0:0); + (ADDRG *> DOG) = (0:0:0, 0:0:0); + (ADDRH *> DOH[0]) = (0:0:0, 0:0:0); + (ADDRH *> DOH[1]) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]); + $setuphold (negedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]); + $setuphold (negedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]); + $setuphold (negedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]); + $setuphold (negedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]); + $setuphold (negedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]); + $setuphold (negedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]); + $setuphold (negedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]); + $setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]); + $setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]); + $setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]); + $setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]); + $setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]); + $setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]); + $setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]); + $setuphold (negedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]); + $setuphold (negedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]); + $setuphold (negedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]); + $setuphold (negedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]); + $setuphold (negedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]); + $setuphold (negedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]); + $setuphold (negedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]); + $setuphold (negedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]); + $setuphold (posedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]); + $setuphold (posedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]); + $setuphold (posedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]); + $setuphold (posedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]); + $setuphold (posedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]); + $setuphold (posedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]); + $setuphold (posedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]); + $setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]); + $setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]); + $setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]); + $setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]); + $setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]); + $setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]); + $setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]); + $setuphold (posedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]); + $setuphold (posedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]); + $setuphold (posedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]); + $setuphold (posedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]); + $setuphold (posedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]); + $setuphold (posedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]); + $setuphold (posedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]); + $setuphold (posedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM32X1D.v b/verilog/src/unisims/RAM32X1D.v new file mode 100644 index 0000000..0e3e0f4 --- /dev/null +++ b/verilog/src/unisims/RAM32X1D.v @@ -0,0 +1,181 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1D.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 01/18/08 - Add support for negative setup/hold timing check (CR457308). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM32X1D #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [31:0] INIT = 32'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output DPO, + output SPO, + + input A0, + input A1, + input A2, + input A3, + input A4, + input D, + input DPRA0, + input DPRA1, + input DPRA2, + input DPRA3, + input DPRA4, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM32X1D"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [4:0] A_in; + wire [4:0] DPRA_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [4:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = {A4, A3, A2, A1, A0}; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + assign DPRA_in = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + + + reg [31:0] mem; + + initial + mem = INIT; + + assign DPO = mem[DPRA_in]; + assign SPO = mem[A_in]; + + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DPO) = (0:0:0, 0:0:0); + (WCLK => SPO) = (0:0:0, 0:0:0); + (A0 => SPO) = (0:0:0, 0:0:0); + (A1 => SPO) = (0:0:0, 0:0:0); + (A2 => SPO) = (0:0:0, 0:0:0); + (A3 => SPO) = (0:0:0, 0:0:0); + (A4 => SPO) = (0:0:0, 0:0:0); + (DPRA0 => DPO) = (0:0:0, 0:0:0); + (DPRA1 => DPO) = (0:0:0, 0:0:0); + (DPRA2 => DPO) = (0:0:0, 0:0:0); + (DPRA3 => DPO) = (0:0:0, 0:0:0); + (DPRA4 => DPO) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM32X1S.v b/verilog/src/unisims/RAM32X1S.v new file mode 100644 index 0000000..c810aa4 --- /dev/null +++ b/verilog/src/unisims/RAM32X1S.v @@ -0,0 +1,163 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1S.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM32X1S #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [31:0] INIT = 32'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output O, + + input A0, + input A1, + input A2, + input A3, + input A4, + input D, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM32X1S"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [4:0] A_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [4:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = {A4, A3, A2, A1, A0}; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + reg [31:0] mem; + + initial + mem = INIT; + + assign O = mem[A_in]; + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => O) = (0:0:0, 0:0:0); + (A0 => O) = (0:0:0, 0:0:0); + (A1 => O) = (0:0:0, 0:0:0); + (A2 => O) = (0:0:0, 0:0:0); + (A3 => O) = (0:0:0, 0:0:0); + (A4 => O) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM512X1S.v b/verilog/src/unisims/RAM512X1S.v new file mode 100644 index 0000000..9e1c1b9 --- /dev/null +++ b/verilog/src/unisims/RAM512X1S.v @@ -0,0 +1,169 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Synchronous RAM 512-Deep by 1-Wide +// /___/ /\ Filename : RAM512X1S.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/12 - Initial version, from RAM256X1S +// 09/17/12 - 678488 fix file name +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM512X1S #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [511:0] INIT = 512'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output O, + + input [8:0] A, + input D, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM512X1S"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [8:0] A_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [8:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = A; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + reg [511:0] mem; + + initial + mem = INIT; + + assign O = mem[A_in]; + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => O) = (0:0:0, 0:0:0); + (A *> O) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, negedge A[8], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[8]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]); + $setuphold (negedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[7]); + $setuphold (negedge WCLK, posedge A[8], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[8]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, negedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, negedge A[8], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[8]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]); + $setuphold (posedge WCLK, posedge A[7], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[7]); + $setuphold (posedge WCLK, posedge A[8], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[8]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM64M.v b/verilog/src/unisims/RAM64M.v new file mode 100644 index 0000000..9bf5aa9 --- /dev/null +++ b/verilog/src/unisims/RAM64M.v @@ -0,0 +1,221 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 64-Deep by 4-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM64M.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/21/06 - Initial version. +// 12/01/06 - Fix the cut/past error for port C and D (CR 430051) +// 05/07/08 - Add negative setup/hold support (CR468872) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM64M #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT_A = 64'h0000000000000000, + parameter [63:0] INIT_B = 64'h0000000000000000, + parameter [63:0] INIT_C = 64'h0000000000000000, + parameter [63:0] INIT_D = 64'h0000000000000000, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output DOA, + output DOB, + output DOC, + output DOD, + + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input DIA, + input DIB, + input DIC, + input DID, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM64M"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire [5:0] ADDRD_in; + wire DIA_in; + wire DIB_in; + wire DIC_in; + wire DID_in; + wire WCLK_in; + wire WE_in; + +`ifdef XIL_TIMING + wire [5:0] ADDRD_dly; + wire DIA_dly; + wire DIB_dly; + wire DIC_dly; + wire DID_dly; + wire WCLK_dly; + wire WE_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign ADDRD_in = ADDRD_dly; + assign DIA_in = DIA_dly; + assign DIB_in = DIB_dly; + assign DIC_in = DIC_dly; + assign DID_in = DID_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign ADDRD_in = ADDRD; + assign DIA_in = DIA; + assign DIB_in = DIB; + assign DIC_in = DIC; + assign DID_in = DID; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + end + + always @(posedge WCLK_in) + if (WE_in) begin + mem_a[ADDRD_in] <= #100 DIA_in; + mem_b[ADDRD_in] <= #100 DIB_in; + mem_c[ADDRD_in] <= #100 DIC_in; + mem_d[ADDRD_in] <= #100 DID_in; + end + + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD_in]; + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[ADDRD_in] <= 1'bx; + mem_b[ADDRD_in] <= 1'bx; + mem_c[ADDRD_in] <= 1'bx; + mem_d[ADDRD_in] <= 1'bx; + end + + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DOA) = (0:0:0, 0:0:0); + (WCLK => DOB) = (0:0:0, 0:0:0); + (WCLK => DOC) = (0:0:0, 0:0:0); + (WCLK => DOD) = (0:0:0, 0:0:0); + (ADDRA *> DOA) = (0:0:0, 0:0:0); + (ADDRB *> DOB) = (0:0:0, 0:0:0); + (ADDRC *> DOC) = (0:0:0, 0:0:0); + (ADDRD *> DOD) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]); + $setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]); + $setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]); + $setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]); + $setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]); + $setuphold (negedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]); + $setuphold (negedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly); + $setuphold (negedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly); + $setuphold (negedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly); + $setuphold (negedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]); + $setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]); + $setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]); + $setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]); + $setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]); + $setuphold (negedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]); + $setuphold (negedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly); + $setuphold (negedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly); + $setuphold (negedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly); + $setuphold (negedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]); + $setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]); + $setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]); + $setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]); + $setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]); + $setuphold (posedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]); + $setuphold (posedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly); + $setuphold (posedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly); + $setuphold (posedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly); + $setuphold (posedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]); + $setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]); + $setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]); + $setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]); + $setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]); + $setuphold (posedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]); + $setuphold (posedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly); + $setuphold (posedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly); + $setuphold (posedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly); + $setuphold (posedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM64M8.v b/verilog/src/unisims/RAM64M8.v new file mode 100644 index 0000000..339b054 --- /dev/null +++ b/verilog/src/unisims/RAM64M8.v @@ -0,0 +1,291 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 64-Deep by 8-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM64M8.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/12 - Initial version, from RAM64M +// 09/17/12 - 678604 - fix compilation errors +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM64M8 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT_A = 64'h0000000000000000, + parameter [63:0] INIT_B = 64'h0000000000000000, + parameter [63:0] INIT_C = 64'h0000000000000000, + parameter [63:0] INIT_D = 64'h0000000000000000, + parameter [63:0] INIT_E = 64'h0000000000000000, + parameter [63:0] INIT_F = 64'h0000000000000000, + parameter [63:0] INIT_G = 64'h0000000000000000, + parameter [63:0] INIT_H = 64'h0000000000000000, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output DOH, + + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [5:0] ADDRH, + input DIA, + input DIB, + input DIC, + input DID, + input DIE, + input DIF, + input DIG, + input DIH, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM64M8"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire [5:0] ADDRH_in; + wire DIA_in; + wire DIB_in; + wire DIC_in; + wire DID_in; + wire DIE_in; + wire DIF_in; + wire DIG_in; + wire DIH_in; + wire WCLK_in; + wire WE_in; + +`ifdef XIL_TIMING + wire [5:0] ADDRH_dly; + wire DIA_dly; + wire DIB_dly; + wire DIC_dly; + wire DID_dly; + wire DIE_dly; + wire DIF_dly; + wire DIG_dly; + wire DIH_dly; + wire WCLK_dly; + wire WE_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign ADDRH_in = ADDRH_dly; + assign DIA_in = DIA_dly; + assign DIB_in = DIB_dly; + assign DIC_in = DIC_dly; + assign DID_in = DID_dly; + assign DIE_in = DIE_dly; + assign DIF_in = DIF_dly; + assign DIG_in = DIG_dly; + assign DIH_in = DIH_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign ADDRH_in = ADDRH; + assign DIA_in = DIA; + assign DIB_in = DIB; + assign DIC_in = DIC; + assign DID_in = DID; + assign DIE_in = DIE; + assign DIF_in = DIF; + assign DIG_in = DIG; + assign DIH_in = DIH; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + reg [63:0] mem_e, mem_f, mem_g, mem_h; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + mem_e = INIT_E; + mem_f = INIT_F; + mem_g = INIT_G; + mem_h = INIT_H; + end + + always @(posedge WCLK_in) + if (WE_in) begin + mem_a[ADDRH_in] <= #100 DIA_in; + mem_b[ADDRH_in] <= #100 DIB_in; + mem_c[ADDRH_in] <= #100 DIC_in; + mem_d[ADDRH_in] <= #100 DID_in; + mem_e[ADDRH_in] <= #100 DIE_in; + mem_f[ADDRH_in] <= #100 DIF_in; + mem_g[ADDRH_in] <= #100 DIG_in; + mem_h[ADDRH_in] <= #100 DIH_in; + end + + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + assign DOE = mem_e[ADDRE]; + assign DOF = mem_f[ADDRF]; + assign DOG = mem_g[ADDRG]; + assign DOH = mem_h[ADDRH_in]; + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[ADDRH_in] <= 1'bx; + mem_b[ADDRH_in] <= 1'bx; + mem_c[ADDRH_in] <= 1'bx; + mem_d[ADDRH_in] <= 1'bx; + mem_e[ADDRH_in] <= 1'bx; + mem_f[ADDRH_in] <= 1'bx; + mem_g[ADDRH_in] <= 1'bx; + mem_h[ADDRH_in] <= 1'bx; + end + + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DOA) = (0:0:0, 0:0:0); + (WCLK => DOB) = (0:0:0, 0:0:0); + (WCLK => DOC) = (0:0:0, 0:0:0); + (WCLK => DOD) = (0:0:0, 0:0:0); + (WCLK => DOE) = (0:0:0, 0:0:0); + (WCLK => DOF) = (0:0:0, 0:0:0); + (WCLK => DOG) = (0:0:0, 0:0:0); + (WCLK => DOH) = (0:0:0, 0:0:0); + (ADDRA *> DOA) = (0:0:0, 0:0:0); + (ADDRB *> DOB) = (0:0:0, 0:0:0); + (ADDRC *> DOC) = (0:0:0, 0:0:0); + (ADDRD *> DOD) = (0:0:0, 0:0:0); + (ADDRE *> DOE) = (0:0:0, 0:0:0); + (ADDRF *> DOF) = (0:0:0, 0:0:0); + (ADDRG *> DOG) = (0:0:0, 0:0:0); + (ADDRH *> DOH) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, negedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[5]); + $setuphold (negedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly); + $setuphold (negedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly); + $setuphold (negedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly); + $setuphold (negedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly); + $setuphold (negedge WCLK, negedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly); + $setuphold (negedge WCLK, negedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly); + $setuphold (negedge WCLK, negedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly); + $setuphold (negedge WCLK, negedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]); + $setuphold (negedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]); + $setuphold (negedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]); + $setuphold (negedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]); + $setuphold (negedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]); + $setuphold (negedge WCLK, posedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[5]); + $setuphold (negedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly); + $setuphold (negedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly); + $setuphold (negedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly); + $setuphold (negedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly); + $setuphold (negedge WCLK, posedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly); + $setuphold (negedge WCLK, posedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly); + $setuphold (negedge WCLK, posedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly); + $setuphold (negedge WCLK, posedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, negedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[5]); + $setuphold (posedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly); + $setuphold (posedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly); + $setuphold (posedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly); + $setuphold (posedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly); + $setuphold (posedge WCLK, negedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly); + $setuphold (posedge WCLK, negedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly); + $setuphold (posedge WCLK, negedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly); + $setuphold (posedge WCLK, negedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]); + $setuphold (posedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]); + $setuphold (posedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]); + $setuphold (posedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]); + $setuphold (posedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]); + $setuphold (posedge WCLK, posedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[5]); + $setuphold (posedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly); + $setuphold (posedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly); + $setuphold (posedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly); + $setuphold (posedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly); + $setuphold (posedge WCLK, posedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly); + $setuphold (posedge WCLK, posedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly); + $setuphold (posedge WCLK, posedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly); + $setuphold (posedge WCLK, posedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM64X1D.v b/verilog/src/unisims/RAM64X1D.v new file mode 100644 index 0000000..5f7e36b --- /dev/null +++ b/verilog/src/unisims/RAM64X1D.v @@ -0,0 +1,188 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1D.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 01/18/08 - Add support for negative setup/hold timing check (CR457308). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM64X1D #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output DPO, + output SPO, + + input A0, + input A1, + input A2, + input A3, + input A4, + input A5, + input D, + input DPRA0, + input DPRA1, + input DPRA2, + input DPRA3, + input DPRA4, + input DPRA5, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM64X1D"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [5:0] A_in; + wire [5:0] DPRA_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [5:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = {A5, A4, A3, A2, A1, A0}; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + assign DPRA_in = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + + reg [63:0] mem; + + initial + mem = INIT; + + assign DPO = mem[DPRA_in]; + assign SPO = mem[A_in]; + + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => DPO) = (0:0:0, 0:0:0); + (WCLK => SPO) = (0:0:0, 0:0:0); + (A0 => SPO) = (0:0:0, 0:0:0); + (A1 => SPO) = (0:0:0, 0:0:0); + (A2 => SPO) = (0:0:0, 0:0:0); + (A3 => SPO) = (0:0:0, 0:0:0); + (A4 => SPO) = (0:0:0, 0:0:0); + (A5 => SPO) = (0:0:0, 0:0:0); + (DPRA0 => DPO) = (0:0:0, 0:0:0); + (DPRA1 => DPO) = (0:0:0, 0:0:0); + (DPRA2 => DPO) = (0:0:0, 0:0:0); + (DPRA3 => DPO) = (0:0:0, 0:0:0); + (DPRA4 => DPO) = (0:0:0, 0:0:0); + (DPRA5 => DPO) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM64X1S.v b/verilog/src/unisims/RAM64X1S.v new file mode 100644 index 0000000..ccb846f --- /dev/null +++ b/verilog/src/unisims/RAM64X1S.v @@ -0,0 +1,169 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1S.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/18/13 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM64X1S #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +) ( + output O, + + input A0, + input A1, + input A2, + input A3, + input A4, + input A5, + input D, + input WCLK, + input WE +); + +// define constants + localparam MODULE_NAME = "RAM64X1S"; + + reg trig_attr = 1'b0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire IS_WCLK_INVERTED_BIN; + + wire D_in; + wire WCLK_in; + wire WE_in; + wire [5:0] A_in; + + assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED; + +`ifdef XIL_TIMING + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [5:0] A_dly; + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign A_in = A_dly; + assign D_in = D_dly; + assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE_dly; // rv 1 +`else + assign A_in = {A5, A4, A3, A2, A1, A0}; + assign D_in = D; + assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + reg [63:0] mem; + + initial + mem = INIT; + + assign O = mem[A_in]; + always @(posedge WCLK_in) + if (WE_in == 1'b1) mem[A_in] <= #100 D_in; + +`ifdef XIL_TIMING + always @(notifier) mem[A_in] <= 1'bx; + assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN; + assign sh_clk_en_n = IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN; + assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN; + + specify + (WCLK => O) = (0:0:0, 0:0:0); + (A0 => O) = (0:0:0, 0:0:0); + (A1 => O) = (0:0:0, 0:0:0); + (A2 => O) = (0:0:0, 0:0:0); + (A3 => O) = (0:0:0, 0:0:0); + (A4 => O) = (0:0:0, 0:0:0); + (A5 => O) = (0:0:0, 0:0:0); + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A5, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAM64X8SW.v b/verilog/src/unisims/RAM64X8SW.v new file mode 100644 index 0000000..e9483bc --- /dev/null +++ b/verilog/src/unisims/RAM64X8SW.v @@ -0,0 +1,360 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 64-Deep 8-bit Read 1-bit Write Multi Port RAM +// /___/ /\ Filename : RAM64X8SW.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 11/09/15 - Initial version. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAM64X8SW #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT_A = 64'h0000000000000000, + parameter [63:0] INIT_B = 64'h0000000000000000, + parameter [63:0] INIT_C = 64'h0000000000000000, + parameter [63:0] INIT_D = 64'h0000000000000000, + parameter [63:0] INIT_E = 64'h0000000000000000, + parameter [63:0] INIT_F = 64'h0000000000000000, + parameter [63:0] INIT_G = 64'h0000000000000000, + parameter [63:0] INIT_H = 64'h0000000000000000, + parameter [0:0] IS_WCLK_INVERTED = 1'b0 +)( + output [7:0] O, + + input [5:0] A, + input D, + input WCLK, + input WE, + input [2:0] WSEL +); + +// define constants + localparam MODULE_NAME = "RAM64X8SW"; + + +`ifdef XIL_TIMING + wire [5:0] A_dly; + wire D_dly; + wire WCLK_dly; + wire WE_dly; + wire [2:0] WSEL_dly; +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + reg [63:0] mem_e, mem_f, mem_g, mem_h; + reg [7:0] O_out; + + assign O = O_out; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + mem_e = INIT_E; + mem_f = INIT_F; + mem_g = INIT_G; + mem_h = INIT_H; + #100; + O_out = {mem_a[A], mem_b[A], mem_c[A], mem_d[A], mem_e[A], mem_f[A], mem_g[A], mem_h[A]}; + end + +generate if (IS_WCLK_INVERTED == 1'b0) begin : write_block +`ifdef XIL_TIMING + always @(posedge WCLK_dly) + if ((WE === 1'bz) || WE_dly) begin + case (WSEL_dly) + 3'b111: begin + if (mem_a[A_dly] !== D_dly) mem_a[A_dly] <= D_dly; + end + 3'b110: begin + if (mem_b[A_dly] !== D_dly) mem_b[A_dly] <= D_dly; + end + 3'b101: begin + if (mem_c[A_dly] !== D_dly) mem_c[A_dly] <= D_dly; + end + 3'b100: begin + if (mem_d[A_dly] !== D_dly) mem_d[A_dly] <= D_dly; + end + 3'b011: begin + if (mem_e[A_dly] !== D_dly) mem_e[A_dly] <= D_dly; + end + 3'b010: begin + if (mem_f[A_dly] !== D_dly) mem_f[A_dly] <= D_dly; + end + 3'b001: begin + if (mem_g[A_dly] !== D_dly) mem_g[A_dly] <= D_dly; + end + 3'b000: begin + if (mem_h[A_dly] !== D_dly) mem_h[A_dly] <= D_dly; + end + endcase + end +`else + always @(posedge WCLK) + if ((WE === 1'bz) || WE) begin + case (WSEL) + 3'b111: begin + if (mem_a[A] !== D) mem_a[A] <= D; + end + 3'b110: begin + if (mem_b[A] !== D) mem_b[A] <= D; + end + 3'b101: begin + if (mem_c[A] !== D) mem_c[A] <= D; + end + 3'b100: begin + if (mem_d[A] !== D) mem_d[A] <= D; + end + 3'b011: begin + if (mem_e[A] !== D) mem_e[A] <= D; + end + 3'b010: begin + if (mem_f[A] !== D) mem_f[A] <= D; + end + 3'b001: begin + if (mem_g[A] !== D) mem_g[A] <= D; + end + 3'b000: begin + if (mem_h[A] !== D) mem_h[A] <= D; + end + endcase + end +`endif +end else begin : write_block +`ifdef XIL_TIMING + always @(negedge WCLK_dly) + if ((WE === 1'bz) || WE_dly) begin + case (WSEL_dly) + 3'b111: begin + if (mem_a[A_dly] !== D_dly) mem_a[A_dly] <= D_dly; + end + 3'b110: begin + if (mem_b[A_dly] !== D_dly) mem_b[A_dly] <= D_dly; + end + 3'b101: begin + if (mem_c[A_dly] !== D_dly) mem_c[A_dly] <= D_dly; + end + 3'b100: begin + if (mem_d[A_dly] !== D_dly) mem_d[A_dly] <= D_dly; + end + 3'b011: begin + if (mem_e[A_dly] !== D_dly) mem_e[A_dly] <= D_dly; + end + 3'b010: begin + if (mem_f[A_dly] !== D_dly) mem_f[A_dly] <= D_dly; + end + 3'b001: begin + if (mem_g[A_dly] !== D_dly) mem_g[A_dly] <= D_dly; + end + 3'b000: begin + if (mem_h[A_dly] !== D_dly) mem_h[A_dly] <= D_dly; + end + endcase + end +`else + always @(negedge WCLK) + if ((WE === 1'bz) || WE) begin + case (WSEL) + 3'b111: begin + if (mem_a[A] !== D) mem_a[A] <= D; + end + 3'b110: begin + if (mem_b[A] !== D) mem_b[A] <= D; + end + 3'b101: begin + if (mem_c[A] !== D) mem_c[A] <= D; + end + 3'b100: begin + if (mem_d[A] !== D) mem_d[A] <= D; + end + 3'b011: begin + if (mem_e[A] !== D) mem_e[A] <= D; + end + 3'b010: begin + if (mem_f[A] !== D) mem_f[A] <= D; + end + 3'b001: begin + if (mem_g[A] !== D) mem_g[A] <= D; + end + 3'b000: begin + if (mem_h[A] !== D) mem_h[A] <= D; + end + endcase + end +`endif +end +endgenerate + +`ifdef XIL_TIMING + always @ (mem_a[A_dly] or A_dly) begin + if (O_out[7] !== mem_a[A_dly]) O_out[7] = mem_a[A_dly]; + end + always @ (mem_b[A_dly] or A_dly) begin + if (O_out[6] !== mem_b[A_dly]) O_out[6] = mem_b[A_dly]; + end + always @ (mem_c[A_dly] or A_dly) begin + if (O_out[5] !== mem_c[A_dly]) O_out[5] = mem_c[A_dly]; + end + always @ (mem_d[A_dly] or A_dly) begin + if (O_out[4] !== mem_d[A_dly]) O_out[4] = mem_d[A_dly]; + end + always @ (mem_e[A_dly] or A_dly) begin + if (O_out[3] !== mem_e[A_dly]) O_out[3] = mem_e[A_dly]; + end + always @ (mem_f[A_dly] or A_dly) begin + if (O_out[2] !== mem_f[A_dly]) O_out[2] = mem_f[A_dly]; + end + always @ (mem_g[A_dly] or A_dly) begin + if (O_out[1] !== mem_g[A_dly]) O_out[1] = mem_g[A_dly]; + end + always @ (mem_h[A_dly] or A_dly) begin + if (O_out[0] !== mem_h[A_dly]) O_out[0] = mem_h[A_dly]; + end +`else + always @ (mem_a[A] or A) begin + if (O_out[7] !== mem_a[A]) O_out[7] = mem_a[A]; + end + always @ (mem_b[A] or A) begin + if (O_out[6] !== mem_b[A]) O_out[6] = mem_b[A]; + end + always @ (mem_c[A] or A) begin + if (O_out[5] !== mem_c[A]) O_out[5] = mem_c[A]; + end + always @ (mem_d[A] or A) begin + if (O_out[4] !== mem_d[A]) O_out[4] = mem_d[A]; + end + always @ (mem_e[A] or A) begin + if (O_out[3] !== mem_e[A]) O_out[3] = mem_e[A]; + end + always @ (mem_f[A] or A) begin + if (O_out[2] !== mem_f[A]) O_out[2] = mem_f[A]; + end + always @ (mem_g[A] or A) begin + if (O_out[1] !== mem_g[A]) O_out[1] = mem_g[A]; + end + always @ (mem_h[A] or A) begin + if (O_out[0] !== mem_h[A]) O_out[0] = mem_h[A]; + end +`endif + +`ifdef XIL_TIMING + always @(notifier) begin + mem_a[A_dly] <= 1'bx; + mem_b[A_dly] <= 1'bx; + mem_c[A_dly] <= 1'bx; + mem_d[A_dly] <= 1'bx; + mem_e[A_dly] <= 1'bx; + mem_f[A_dly] <= 1'bx; + mem_g[A_dly] <= 1'bx; + mem_h[A_dly] <= 1'bx; + end +`endif + +// end behavioral model + +`ifdef XIL_TIMING + wire sh_clk_en_p; + wire sh_clk_en_n; + + assign sh_clk_en_p = ~IS_WCLK_INVERTED; + assign sh_clk_en_n = IS_WCLK_INVERTED; + + wire sh_we_clk_en_p; + wire sh_we_clk_en_n; + + assign sh_we_clk_en_p = (WE || (WE === 1'bz)) && ~IS_WCLK_INVERTED; + assign sh_we_clk_en_n = (WE || (WE === 1'bz)) && IS_WCLK_INVERTED; +`endif + + specify + (WCLK *> O) = (100:100:100, 100:100:100); + (A *> O) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge WCLK &&& WE, 0:0:0, notifier); + $period (posedge WCLK &&& WE, 0:0:0, notifier); + $setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, negedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]); + $setuphold (negedge WCLK, negedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]); + $setuphold (negedge WCLK, negedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]); + $setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly); + $setuphold (negedge WCLK, posedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]); + $setuphold (negedge WCLK, posedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]); + $setuphold (negedge WCLK, posedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]); + $setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, negedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]); + $setuphold (posedge WCLK, negedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]); + $setuphold (posedge WCLK, negedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]); + $setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]); + $setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]); + $setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]); + $setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]); + $setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]); + $setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]); + $setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly); + $setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly); + $setuphold (posedge WCLK, posedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]); + $setuphold (posedge WCLK, posedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]); + $setuphold (posedge WCLK, posedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMB18E1.v b/verilog/src/unisims/RAMB18E1.v new file mode 100644 index 0000000..20dce8e --- /dev/null +++ b/verilog/src/unisims/RAMB18E1.v @@ -0,0 +1,4993 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB18E1.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 02/26/08 - Initial version. +// 07/25/08 - Fixed ECC in register mode. (IR 477257) +// 07/30/08 - Updated to support SDP mode with smaller port width <= 18. (IR 477258) +// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964) +// 03/11/09 - X's the unused bits of outputs (CR 511363). +// 03/12/09 - Removed parameter from specify block (CR 503821). +// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). +// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450). +// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327). +// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010). +// 11/18/09 - Define tasks and functions before calling (CR 532610). +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010). +// 04/01/10 - Fixed clocks detection for collision (CR 552123). +// 05/11/10 - Updated clocks detection for collision (CR 557624). +// - Added attribute RDADDR_COLLISION_HWCONFIG. (CR 557971). +// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807). +// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// 07/08/10 - Added SIM_DEVICE attribute (CR 567633). +// 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672). +// 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507). +// 09/16/10 - Updated from bit to bus timing (CR 575523). +// 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924). +// 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953). +// 12/10/10 - Converted parameter to wire in specify block (CR 574534). +// 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053). +// 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004). +// 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942). +// 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942). +// 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129). +// 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844). +// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190). +// 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482). +// 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399). +// 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454). +// 03/15/12 - Reverted CR 584399 (CR 651279). +// 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934). +// 07/25/13 - Added invertible pins support (CR 715417). +// 09/04/13 - Removed warning for memp (CR 728988). +// 03/24/14 - Balanced all iniputs with xor (CR778933). +// 08/29/14 - Added negative timing check (CR 821138). +// 09/05/14 - Fixed timing check (CR 822107) +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/22/14 - Added #1 to $finish (CR 808642). +// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module RAMB18E1 (DOADO, DOBDO, DOPADOP, DOPBDOP, + ADDRARDADDR, ADDRBWRADDR, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "7SERIES"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + + input CLKARDCLK; + input CLKBWRCLK; + input ENARDEN; + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + input RSTRAMARSTRAM; + input RSTRAMB; + input RSTREGARSTREG; + input RSTREGB; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input [1:0] WEA; + input [3:0] WEBWE; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [1:0] dangle_out2; + wire [3:0] dangle_out4; + wire [5:0] dangle_out6; + wire [8:0] dangle_out9; + wire [15:0] dangle_out16; + wire [31:0] dangle_out32; + wire [47:0] dangle_out48; + wire [15:0] doado_wire, dobdo_wire; + wire [1:0] dopadop_wire, dopbdop_wire; + reg [15:0] doado_out, dobdo_out; + reg [1:0] dopadop_out, dopbdop_out; + reg notifier, notifier_a, notifier_b; + reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4; + reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9; + reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13; + reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4; + reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9; + reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13; + reg attr_err = 1'b0; + + wire regcearegce_in; + wire regceb_in; + wire [13:0] addrardaddr_in; + wire [13:0] addrbwraddr_in; + wire [15:0] diadi_in; + wire [15:0] dibdi_in; + wire [1:0] dipadip_in; + wire [1:0] dipbdip_in; + wire [1:0] wea_in; + wire [3:0] webwe_in; + + wire clkardclk_in; + wire clkbwrclk_in; + wire enarden_in; + wire enbwren_in; + wire rstramarstram_in; + wire rstramb_in; + wire rstregarstreg_in; + wire rstregb_in; + +`ifdef XIL_TIMING + wire CLKARDCLK_delay; + wire CLKBWRCLK_delay; + wire ENARDEN_delay; + wire ENBWREN_delay; + wire REGCEAREGCE_delay; + wire REGCEB_delay; + wire RSTRAMARSTRAM_delay; + wire RSTRAMB_delay; + wire RSTREGARSTREG_delay; + wire RSTREGB_delay; + wire [13:0] ADDRARDADDR_delay; + wire [13:0] ADDRBWRADDR_delay; + wire [15:0] DIADI_delay; + wire [15:0] DIBDI_delay; + wire [1:0] DIPADIP_delay; + wire [1:0] DIPBDIP_delay; + wire [1:0] WEA_delay; + wire [3:0] WEBWE_delay; +`endif + +`ifdef XIL_TIMING + assign regcearegce_in = REGCEAREGCE_delay; + assign regceb_in = REGCEB_delay; + assign addrardaddr_in = ADDRARDADDR_delay; + assign addrbwraddr_in = ADDRBWRADDR_delay; + assign diadi_in = DIADI_delay; + assign dibdi_in = DIBDI_delay; + assign dipadip_in = DIPADIP_delay; + assign dipbdip_in = DIPBDIP_delay; + assign wea_in = WEA_delay; + assign webwe_in = WEBWE_delay; + assign clkardclk_in = CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED; + assign clkbwrclk_in = CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED; + assign enarden_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED; + assign enbwren_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED; + assign rstramarstram_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED; + assign rstramb_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED; + assign rstregarstreg_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED; + assign rstregb_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED; +`else + assign regcearegce_in = REGCEAREGCE; + assign regceb_in = REGCEB; + assign addrardaddr_in = ADDRARDADDR; + assign addrbwraddr_in = ADDRBWRADDR; + assign diadi_in = DIADI; + assign dibdi_in = DIBDI; + assign dipadip_in = DIPADIP; + assign dipbdip_in = DIPBDIP; + assign wea_in = WEA; + assign webwe_in = WEBWE; + assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED; + assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED; + assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED; + assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED; + assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED; + assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED; + assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED; + assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED; +`endif + + initial begin + + + if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end // initial begin + + + // special handle for sdp width = 36 + localparam [35:0] init_sdp = (READ_WIDTH_A == 36) ? {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : {INIT_B, INIT_A}; + localparam [35:0] srval_sdp = (READ_WIDTH_A == 36) ? {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : {SRVAL_B, SRVAL_A}; + + + generate + case (RAM_MODE) + + "TDP" : begin : gen_tdp + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(INIT_A), + .INIT_B(INIT_B), + .INIT_FILE(INIT_FILE), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_TDP (.ADDRA({2'b0,addrardaddr_in}), + .ADDRB({2'b0,addrbwraddr_in}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(dangle_out), + .DIA({48'b0,diadi_in}), + .DIB({48'b0,dibdi_in}), + .DIPA({2'b0,dipadip_in}), + .DIPB({6'b0,dipbdip_in}), + .DOA({dangle_out48,doado_wire}), + .DOB({dangle_out16,dobdo_wire}), + .DOPA({dangle_out6,dopadop_wire}), + .DOPB({dangle_out2,dopbdop_wire}), + .ECCPARITY(dangle_out8), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(dangle_out), + .WEA({4{wea_in}}), + .WEB({2{webwe_in}})); + + end // case: "TDP" + "SDP" : begin : gen_sdp + + if (WRITE_WIDTH_B == 36) begin : gen_wide + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A({36'b0,init_sdp}), + .INIT_B({36'b0,init_sdp}), + .INIT_FILE(INIT_FILE), + .SRVAL_A({36'b0,{srval_sdp}}), + .SRVAL_B({36'b0,{srval_sdp}}), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_A), + .WRITE_WIDTH_A(WRITE_WIDTH_B), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}), + .ADDRB({2'b0,addrbwraddr_in}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(dangle_out), + .DIA(64'b0), + .DIB({32'b0,dibdi_in,diadi_in}), + .DIPA(4'b0), + .DIPB({4'b0,dipbdip_in,dipadip_in}), + .DOA({dangle_out32,dobdo_wire,doado_wire}), + .DOB(dangle_out32), + .DOPA({dangle_out4,dopbdop_wire,dopadop_wire}), + .DOPB(dangle_out4), + .ECCPARITY(dangle_out8), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(dangle_out), + .WEA(8'b0), + .WEB({2{webwe_in}})); + + end // if (WRITE_WIDTH_B == 36) + else begin : gen_narrow + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A({36'b0,init_sdp}), + .INIT_B({36'b0,init_sdp}), + .INIT_FILE(INIT_FILE), + .SRVAL_A({36'b0,{srval_sdp}}), + .SRVAL_B({36'b0,{srval_sdp}}), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_A), + .WRITE_WIDTH_A(WRITE_WIDTH_B), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}), + .ADDRB({2'b0,addrbwraddr_in}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(dangle_out), + .DIA(64'b0), + .DIB({48'b0,dibdi_in}), + .DIPA(4'b0), + .DIPB({6'b0,dipbdip_in}), + .DOA({dangle_out32,dobdo_wire,doado_wire}), + .DOB(dangle_out32), + .DOPA({dangle_out4,dopbdop_wire,dopadop_wire}), + .DOPB(dangle_out4), + .ECCPARITY(dangle_out8), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(dangle_out), + .WEA(8'b0), + .WEB({2{webwe_in}})); + end // else: !if(WRITE_WIDTH_B == 36) + + end // case: "SDP" + + endcase // case(RAM_MODE) + endgenerate + + +//*** Timing Checks Start here + + reg [15:0] DOADO_out; + reg [15:0] DOBDO_out; + reg [1:0] DOPADOP_out; + reg [1:0] DOPBDOP_out; + + assign DOADO = DOADO_out; + assign DOBDO = DOBDO_out; + assign DOPADOP = DOPADOP_out; + assign DOPBDOP = DOPBDOP_out; + + always @(doado_wire or rstramb_in or GSR) DOADO_out = doado_wire; + always @(dobdo_wire or rstramb_in or GSR) DOBDO_out = dobdo_wire; + always @(dopadop_wire or rstramb_in or GSR) DOPADOP_out = dopadop_wire; + always @(dopbdop_wire or rstramb_in or GSR) DOPBDOP_out = dopbdop_wire; + +`ifdef XIL_TIMING + + wire clkardclk_en_n; + wire clkardclk_en_p; + wire clkbwrclk_en_n; + wire clkbwrclk_en_p; + assign clkardclk_en_n = IS_CLKARDCLK_INVERTED; + assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED; + assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED; + assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED; + + wire enarden_clka_n = enarden_in && clkardclk_en_n; + wire enarden_clka_p = enarden_in && clkardclk_en_p; + wire enbwren_clkb_n = enbwren_in && clkbwrclk_en_n; + wire enbwren_clkb_p = enbwren_in && clkbwrclk_en_p; + + wire diadi0_enable_n = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_n; + wire diadi0_enable_p = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_p; + + wire dibdi0_enable_n = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_n) : (enbwren_in && webwe_in[2] && clkbwrclk_en_n) ; + wire dibdi0_enable_p = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_p) : (enbwren_in && webwe_in[2] && clkbwrclk_en_p) ; + + wire sdp_dia0_clkwr_n = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_n; + wire sdp_dia0_clkwr_p = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_p; + + + always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or + notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or + notifier_addra11 or notifier_addra12 or notifier_addra13) begin + doado_out <= 16'hxxxx; + dopadop_out <= 2'bxx; + end + + always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or + notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or + notifier_addrb11 or notifier_addrb12 or notifier_addrb13) begin + + dobdo_out <= 16'hxxxx; + dopbdop_out <= 2'bxx; + + if (RAM_MODE == "SDP") begin + doado_out <= 16'hxxxx; + dopadop_out <= 2'bxx; + end + + end + + + always @(notifier_addra0) begin + task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK"); + end + + always @(notifier_addra1) begin + task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK"); + end + + always @(notifier_addra2) begin + task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK"); + end + + always @(notifier_addra3) begin + task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK"); + end + + always @(notifier_addra4) begin + task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK"); + end + + always @(notifier_addra5) begin + task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK"); + end + + always @(notifier_addra6) begin + task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK"); + end + + always @(notifier_addra7) begin + task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK"); + end + + always @(notifier_addra8) begin + task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK"); + end + + always @(notifier_addra9) begin + task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK"); + end + + always @(notifier_addra10) begin + task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK"); + end + + always @(notifier_addra11) begin + task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK"); + end + + always @(notifier_addra12) begin + task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK"); + end + + always @(notifier_addra13) begin + task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK"); + end + + + always @(notifier_addrb0) begin + task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK"); + end + + always @(notifier_addrb1) begin + task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK"); + end + + always @(notifier_addrb2) begin + task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK"); + end + + always @(notifier_addrb3) begin + task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK"); + end + + always @(notifier_addrb4) begin + task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK"); + end + + always @(notifier_addrb5) begin + task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK"); + end + + always @(notifier_addrb6) begin + task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK"); + end + + always @(notifier_addrb7) begin + task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK"); + end + + always @(notifier_addrb8) begin + task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK"); + end + + always @(notifier_addrb9) begin + task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK"); + end + + always @(notifier_addrb10) begin + task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK"); + end + + always @(notifier_addrb11) begin + task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK"); + end + + always @(notifier_addrb12) begin + task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK"); + end + + always @(notifier_addrb13) begin + task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK"); + end + + + task task_warn_msg; + + input [8*15:1] addr_str; + input [8*9:1] clk_str; + + begin + + $display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str); + + end + + endtask // task_warn_msg + +`endif // `ifdef XIL_TIMING + + + wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0; + + specify + + (CLKARDCLK *> DOADO) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100); + + if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100); + if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100); + if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100); + if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + $setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); + $setuphold (posedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); + $setuphold (posedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); + + $setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); + $setuphold (posedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); + $setuphold (posedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (posedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (posedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (posedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); + + $setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); + $setuphold (negedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); + $setuphold (negedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); + + $setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); + $setuphold (negedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); + $setuphold (negedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (negedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (negedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (negedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); + + $period (negedge CLKARDCLK, 0:0:0, notifier_a); + $period (negedge CLKBWRCLK, 0:0:0, notifier_b); + $period (posedge CLKARDCLK, 0:0:0, notifier_a); + $period (posedge CLKBWRCLK, 0:0:0, notifier_b); + $width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); + $width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); + $width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); + $width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); + +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB18E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. RAMB18E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module RB18_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR, + ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB); + + output CASCADEOUTA; + output CASCADEOUTB; + output DBITERR; + output SBITERR; + output [8:0] RDADDRECC; + output reg [63:0] DOA; + output reg [31:0] DOB; + output reg [7:0] DOPA; + output reg [3:0] DOPB; + output [7:0] ECCPARITY; + + input ENA, CLKA, CASCADEINA, REGCEA; + input ENB, CLKB, CASCADEINB, REGCEB; + input GSR; + input RSTRAMA, RSTRAMB; + input RSTREGA, RSTREGB; + input INJECTDBITERR, INJECTSBITERR; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [63:0] DIA; + input [63:0] DIB; + input [3:0] DIPA; + input [7:0] DIPB; + input [7:0] WEA; + input [7:0] WEB; + + parameter DOA_REG = 0; + parameter DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [71:0] INIT_A = 72'h0; + parameter [71:0] INIT_B = 72'h0; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "7SERIES"; + parameter [71:0] SRVAL_A = 72'h0; + parameter [71:0] SRVAL_B = 72'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter INIT_FILE = "NONE"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameters are changed. + parameter BRAM_SIZE = 36; +// xilinx_internal_parameter off + + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset; + integer viol_time = 0; + integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int; + integer ram_mode_int, en_ecc_write_int, en_ecc_read_int; + integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0; + + reg addra_in_15_reg_bram, addrb_in_15_reg_bram; + reg addra_in_15_reg, addrb_in_15_reg; + reg addra_in_15_reg1, addrb_in_15_reg1; + reg junk1; + reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; + reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0; + reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0; + reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0; + reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0; + reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; + reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; + reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; + reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; + + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, syndrome = 8'b0; + reg [7:0] dipb_in_ecc; + reg [71:0] ecc_bit_position; + reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; + reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx; + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_outreg = 0, sbiterr_outreg = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + + reg [7:0] wea_reg; + reg enb_reg; + reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg; + reg outp_a = 1'b0, outp_b = 1'b0, junkp; + reg rising_clka = 1'b0, rising_clkb = 1'b0; + reg [15:0] addra_reg, addrb_reg; + + reg [63:0] dia_reg, dib_reg; + reg [3:0] dipa_reg; + reg [7:0] dipb_reg; + reg [1:0] viol_type = 2'b00; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0; + reg [8:0] rdaddrecc_out_out = 9'b0; + reg finish_error = 0; + + time time_port_a, time_port_b; + + wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in; + wire [7:0] wea_in; + wire [7:0] web_in; + wire cascadeina_in, cascadeinb_in; + wire injectdbiterr_in, injectsbiterr_in; + wire rstrega_in, rstregb_in; + reg [15:0] ox_addra_reconstruct, ox_addrb_reconstruct; + reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg; + + wire temp_wire; // trigger NCsim at initial time + assign temp_wire = 1; + + time time_clka_period, time_clkb_period, time_period; + reg time_skew_a_flag = 0; + reg time_skew_b_flag = 0; + + assign CASCADEOUTA = DOA[0]; + assign CASCADEOUTB = DOB[0]; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDADDRECC = rdaddrecc_out_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign rstrega_in = RSTREGA; + assign rstregb_in = RSTREGB; + + + localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100; + + + // Determine memory size + localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && + WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : + (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && + WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : + (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && + READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : + (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && + READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 72; + + localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : + (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : + (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : + (WRITE_WIDTH_A == 72) ? 64 : 64; + + localparam wa_width_0 = 0; + + localparam wa_width_1 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : + (WRITE_WIDTH_A == 72) ? 8 : 0; + + localparam wa_width_2 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 16 : + (WRITE_WIDTH_A == 72) ? 16 : 0; + + localparam wa_width_3 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 24 : + (WRITE_WIDTH_A == 72) ? 24 : 0; + + localparam wa_width_4 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 32 : 0; + + localparam wa_width_5 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 40 : 0; + + localparam wa_width_6 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 48 : 0; + + localparam wa_width_7 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 56 : 0; + + localparam wa_width_n = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : + (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : + (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : + (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : + (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : + (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : + (WRITE_WIDTH_B == 72) ? 64 : 64; + + localparam wb_width_0 = 0; + + localparam wb_width_1 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : + (WRITE_WIDTH_B == 72) ? 8 : 0; + + localparam wb_width_2 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 16 : + (WRITE_WIDTH_B == 72) ? 16 : 0; + + localparam wb_width_3 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 24 : + (WRITE_WIDTH_B == 72) ? 24 : 0; + + localparam wb_width_4 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 32 : 0; + + localparam wb_width_5 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 40 : 0; + + localparam wb_width_6 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 48 : 0; + + localparam wb_width_7 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 56 : 0; + + localparam wb_width_n = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : + (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : + (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : + (WRITE_WIDTH_B == 72) ? 8 : 8; + + + localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : + (WRITE_WIDTH_A == 36) ? 4 : (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : + (WRITE_WIDTH_B == 36) ? 4 : (WRITE_WIDTH_B == 72) ? 8 : 8; + + localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : + (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : + (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : + (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : + (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 64 : 64) : 64; + + localparam ra_width_n = (ra_width == 1) ? 1 : (ra_width == 2) ? 2 : + (ra_width == 4) ? 4 : (ra_width == 8) ? 8 : + (ra_width == 16) ? 8 : (ra_width == 32) ? 8 : + (ra_width == 64) ? 8 : 8; + + localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : + (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : + (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 32 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : + (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : + (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 32 : 32) : 32; + + localparam rb_width_0 = 0; + + localparam rb_width_1 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : + (rb_width == 64) ? 8 : 8; + + localparam rb_width_2 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 16 : + (rb_width == 64) ? 16 : 16; + + localparam rb_width_3 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 24 : + (rb_width == 64) ? 24 : 24; + + localparam rb_width_4 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 32 : 32; + + localparam rb_width_5 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 40 : 40; + + localparam rb_width_6 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 48 : 48; + + localparam rb_width_7 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 56 : 56; + + localparam rb_width_n = (rb_width == 1) ? 1 : (rb_width == 2) ? 2 : + (rb_width == 4) ? 4 : (rb_width == 8) ? 8 : + (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : + (rb_width == 64) ? 8 : 8; + + localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : + (READ_WIDTH_A == 36) ? 4 : (READ_WIDTH_A == 72) ? 8 : 1; + + localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : + (READ_WIDTH_B == 36) ? 4 : (READ_WIDTH_B == 72) ? 4 : 1; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : + (widest_width == 72) ? 6 : 0; + + always @(*) begin + if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin + if (BRAM_SIZE == 36) ox_addra_reconstruct[15:0] = {1'b0,ADDRA[14:8],8'b0}; + else if (BRAM_SIZE == 18) ox_addra_reconstruct[15:0] = {2'b0,ADDRA[13:7],7'b0}; + else ox_addra_reconstruct[15:0] = ADDRA; + end else ox_addra_reconstruct[15:0] = ADDRA; + end + + always @(*) begin + if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin + if (BRAM_SIZE == 36) ox_addrb_reconstruct[15:0] = {1'b0,ADDRB[14:8],8'b0}; + else if (BRAM_SIZE == 18) ox_addrb_reconstruct[15:0] = {2'b0,ADDRB[13:7],7'b0}; + else ox_addrb_reconstruct[15:0] = ADDRB; + end else ox_addrb_reconstruct[15:0] = ADDRB; + end + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : + (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : + (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : + (widest_width == 72) ? 64 : 64; + + localparam width_0 = 0; + + localparam width_1 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : + (widest_width == 72) ? 8 : 0; + + localparam width_2 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 16 : + (widest_width == 72) ? 16 : 0; + + localparam width_3 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 24 : + (widest_width == 72) ? 24 : 0; + + localparam width_4 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 32 : 0; + + localparam width_5 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 40 : 0; + + localparam width_6 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 48 : 0; + + localparam width_7 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 56 : 0; + + localparam width_n = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : + (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : + (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : + (widest_width == 72) ? 8 : 8; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : + (widest_width == 36) ? 4 : + (widest_width == 72) ? 8 : 1; + + + localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : 10) : 10; + + localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : 10) : 10; + + localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : + (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : + (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : + (WRITE_WIDTH_A == 72) ? 6 : 10; + + localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : + (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : + (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : + (WRITE_WIDTH_B == 72) ? 6 : 10; + + localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10; + + localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10; + + localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10; + + localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10; + + localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; + localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; + localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; + localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; + localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; + localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; + localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; + + localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : + (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 32768; + + localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 4096; + + reg [width+widthp-1:0] tmp_mem [0 : mem_depth-1]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer index = 0; + + +/******************************************** task and function **************************************/ + + task task_ram; + + input ram_we; + input [7:0] ram_di; + input ram_dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (ram_we == 1'b1) begin + + mem_task = ram_di; + + if (width >= 8) + memp_task = ram_dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input ram_col_we_o; + input ram_col_we; + input [7:0] ram_col_di; + input ram_col_dip; + inout [7:0] ram_col_mem_task; + inout ram_col_memp_task; + integer ram_col_i; + + begin + + if (ram_col_we == 1'b1) begin + + for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1) + if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)) + ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i]; + + if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))) + ram_col_memp_task = ram_col_dip; + + end + end + + endtask // task_ram_col + + + task task_ram_ox; + + input ram_ox_we_o; + input ram_ox_we; + input [7:0] ram_ox_di; + input ram_ox_dip; + inout [7:0] ram_ox_mem_task; + inout ram_ox_memp_task; + integer ram_ox_i; + + begin + + if (ram_ox_we == 1'b1) begin + + for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1) + ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i]; + + if (width >= 8) + ram_ox_memp_task = ram_ox_dip; + + end + end + + endtask // task_ram_ox + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] x_buf_do_tmp; + input [7:0] dop_ltmp; + inout [7:0] x_buf_dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + x_buf_do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + x_buf_dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + +task task_col_wr_ram_a; + input [1:0] col_wr_ram_a_seq; + input [7:0] col_wr_ram_a_web_tmp; + input [7:0] col_wr_ram_a_wea_tmp; + input [63:0] col_wr_ram_a_dia_tmp; + input [7:0] col_wr_ram_a_dipa_tmp; + input [15:0] col_wr_ram_a_addrb_tmp; + input [15:0] col_wr_ram_a_addra_tmp; + begin + case (wa_width) + 1, 2, 4 : begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 16 + 32 : if (width >= 32) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + else if (wa_width < width) begin + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + end + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 32 + 64 : if (width >= 64) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][width_4 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][width_5 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][width_6 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][width_7 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + end // case: 64 + endcase // case(wa_width) + end +endtask // task_col_wr_ram_a + + +task task_ox_wr_ram_a; + input [1:0] ox_wr_ram_a_seq; + input [7:0] ox_wr_ram_a_web_tmp; + input [7:0] ox_wr_ram_a_wea_tmp; + input [63:0] ox_wr_ram_a_dia_tmp; + input [7:0] ox_wr_ram_a_dipa_tmp; + input [15:0] ox_wr_ram_a_addrb_tmp; + input [15:0] ox_wr_ram_a_addra_tmp; + + begin + case (wa_width) + 1, 2, 4 : begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + wa_width_1) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 16 + 32 : if ( width >= 32) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // case: 64 + endcase // case(wa_width) + end +endtask // task_ox_wr_ram_a + + +task task_col_wr_ram_b; + input [1:0] col_wr_ram_b_seq; + input [7:0] col_wr_ram_b_wea_tmp; + input [7:0] col_wr_ram_b_web_tmp; + input [63:0] col_wr_ram_b_dib_tmp; + input [7:0] col_wr_ram_b_dipb_tmp; + input [15:0] col_wr_ram_b_addra_tmp; + input [15:0] col_wr_ram_b_addrb_tmp; + + begin + case (wb_width) + + 1, 2, 4 : begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_n) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) + end // case: 16 + 32 : if (width >= 32) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_col_wr_ram_b + + +task task_ox_wr_ram_b; + input [1:0] ox_wr_ram_b_seq; + input [7:0] ox_wr_ram_b_wea_tmp; + input [7:0] ox_wr_ram_b_web_tmp; + input [63:0] ox_wr_ram_b_dib_tmp; + input [7:0] ox_wr_ram_b_dipb_tmp; + input [15:0] ox_wr_ram_b_addra_tmp; + input [15:0] ox_wr_ram_b_addrb_tmp; + + begin + case (wb_width) + 1, 2, 4 : begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) + end // case: 16 + 32 : if (width >= 32) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_ox_wr_ram_b + + +task task_wr_ram_a; + input [7:0] wr_ram_a_wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] wr_ram_a_addra_tmp; + begin + case (wa_width) + 1, 2, 4 : begin + if (wa_width >= width) + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width_n], junk1); + end + 8 : if (width >= 8) begin + if (wa_width >= width) + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]); + else + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + end + 16 : if (width >= 16) begin + if (wa_width >= width) begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + end else begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + end // case: 16 + 32 : if (width >= 32) begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + end // case: 32 + endcase // case(wa_width) + end +endtask // task_wr_ram_a + + +task task_wr_ram_b; + input [7:0] wr_ram_b_web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] wr_ram_b_addrb_tmp; + begin + case (wb_width) + 1, 2, 4 : begin + if (wb_width >= width) + task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); + end + 8 : if (width >= 8) begin + if (wb_width >= width) + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]); + else + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + end + 16 : if (width >= 16) begin + if (wb_width >= width) begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + end else begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + end // case: 16 + 32 : if (width >= 32) begin + if (wb_width >= width) begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + end else begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + end // else: !if(wb_width >= width) + end // case: 32 + 64 : if (width >= 64) begin // only valid with ECC single bit correction for 64 bits + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_wr_ram_b + + +task task_col_rd_ram_a; + input [1:0] col_rd_ram_a_seq; // 1 is bypass + input [7:0] col_rd_ram_a_web_tmp; + input [7:0] col_rd_ram_a_wea_tmp; + input [15:0] col_rd_ram_a_addra_tmp; + inout [63:0] col_rd_ram_a_doa_tmp; + inout [7:0] col_rd_ram_a_dopa_tmp; + reg [63:0] doa_ltmp; + reg [7:0] dopa_ltmp; + + begin + doa_ltmp= 64'b0; + dopa_ltmp= 8'b0; + case (ra_width) + 1, 2, 4 : begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; + else + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]]; + dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]]; + end else begin + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width_n]; + dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end // case: 8 + 16 : if (width >= 16) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1]; + end else begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1]; + end else begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) + ra_width_n) +: ra_width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end + 32 : if (width >= 32) begin + if (ra_width >= width) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][width_2 +: width_n]; + dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][width_3 +: width_n]; + dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + end // if (ra_width >= width) + end + 64 : if (width >= 64) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][width_2 +: width_n]; + dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][width_3 +: width_n]; + dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin + doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][width_4 +: width_n]; + dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1]; + task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin + doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][width_5 +: width_n]; + dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1]; + task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin + doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][width_6 +: width_n]; + dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1]; + task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin + doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][width_7 +: width_n]; + dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1]; + task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end + endcase // case(ra_width) + end +endtask // task_col_rd_ram_a + + +task task_col_rd_ram_b; + input [1:0] col_rd_ram_b_seq; // 1 is bypass + input [7:0] col_rd_ram_b_wea_tmp; + input [7:0] col_rd_ram_b_web_tmp; + input [15:0] col_rd_ram_b_addrb_tmp; + inout [63:0] col_rd_ram_b_dob_tmp; + inout [7:0] col_rd_ram_b_dopb_tmp; + reg [63:0] col_rd_ram_b_dob_ltmp; + reg [7:0] col_rd_ram_b_dopb_ltmp; + + begin + col_rd_ram_b_dob_ltmp= 64'b0; + col_rd_ram_b_dopb_ltmp= 8'b0; + + case (rb_width) + 1, 2, 4 : begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; + else + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width_n]; + + task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]]; + col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]]; + end else begin + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + + end + end // case: 8 + 16 : if (width >= 16) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) + rb_width_n) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end + 32 : if (width >= 32) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_1) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_2 +: width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_2) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1]; + end + task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_3 +: width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_3) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1]; + end + task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end + 64 : if (width >= 64) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1]; + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1]; + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_2 +: width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1]; + task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_3 +: width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1]; + task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_4 +: width_n]; + col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1]; + task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_5 +: width_n]; + col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1]; + task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_6 +: width_n]; + col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1]; + task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_7 +: width_n]; + col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1]; + task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + end + endcase // case(rb_width) + end +endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] rd_ram_a_addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:3]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_widthp) +: ra_widthp]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:4]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_widthp) +: ra_widthp]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:5]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_widthp) +: ra_widthp]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:6]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] rd_ram_b_addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]]; + end + 64 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]]; + end + end + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input wea_tmp; + input web_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") + + if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + + end + else + $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + col_wr_wr_msg = 0; + + end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) + else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp); + + end + else begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) + $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); + else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01)) + $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); + + end // else: !if(chk_ox_msg == 1) + + col_wra_rdb_msg = 0; + + end + else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + end + else begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) + $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); + else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01)) + $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); + + end // else: !if(chk_ox_msg == 1) + + col_wrb_rda_msg = 0; + + end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) + + end + + endtask // chk_for_col_msg + + + task task_col_ecc_read; + + inout [63:0] do_tmp; + inout [7:0] dop_tmp; + input [15:0] addr_tmp; + + reg [71:0] task_ecc_bit_position; + reg [7:0] task_dopr_ecc, task_syndrome; + reg [63:0] task_di_in_ecc_corrected; + reg [7:0] task_dip_in_ecc_corrected; + + begin + + if (|do_tmp === 1'bx) begin // if there is collision + dbiterr_out <= 1'bx; + sbiterr_out <= 1'bx; + end + else begin + + task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); + + task_syndrome = task_dopr_ecc ^ dop_tmp; + + if (task_syndrome !== 0) begin + + if (task_syndrome[7]) begin // dectect single bit error + + task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; + + + if (task_syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output + + task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory + + do_tmp = task_di_in_ecc_corrected; + + task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_tmp = task_dip_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!task_syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (task_syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(task_syndrome !== 0) + + end + + end + + endtask // task_col_ecc_read + + + function [7:0] fn_dip_ecc; + + input encode; + input [63:0] di_in; + input [7:0] dip_in; + + begin + + fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + if (encode == 1'b1) + + fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + else + fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + end + + endfunction // fn_dip_ecc + +/******************************************** END task and function **************************************/ + + + initial begin + if (INIT_FILE == "NONE") begin // memory initialization from attributes + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + + if (BRAM_SIZE == 36) begin + mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; + mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; + mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; + mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; + mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; + mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; + mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; + mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; + mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; + mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; + mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; + mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; + mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; + mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; + mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; + mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; + mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; + mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; + mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; + mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; + mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; + mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; + mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; + mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; + mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; + mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; + mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; + mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; + mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; + mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; + mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; + mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; + mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; + mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; + mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; + mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; + mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; + mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; + mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; + mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; + mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; + mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; + mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; + mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; + mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; + mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; + mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; + mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; + mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; + mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; + mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; + mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; + mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; + mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; + mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; + mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; + mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; + mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; + mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; + mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; + mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; + mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; + mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; + mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; + end // if (BRAM_SIZE == 36) + end // for (count = 0; count < init_mult; count = count + 1) + + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + if (BRAM_SIZE == 36) begin + memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; + memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; + memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; + memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; + memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; + memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; + memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; + memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; + end + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin // memory initialization from memory file + for (j = 0; j < mem_depth; j = j + 1) begin + for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin + tmp_mem[j][j1] = 1'b0; + end + end + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + end + 9 : if ((width == 8) && (widthp == 1)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 18 : if ((width == 16) && (widthp == 2)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 36 : if ((width == 32) && (widthp == 4)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 72 : if ((width == 64) && (widthp == 8)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + endcase // case(widest_width) + end // else: !if(INIT_FILE == "NONE") + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int = 1; + "FALSE" : en_ecc_write_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int = 1; + "FALSE" : en_ecc_read_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + case (RAM_MODE) + "TDP" : begin + ram_mode_int = 1; + + if (en_ecc_write_int == 1) begin + $display("DRC Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE); + finish_error = 1; + end + + if (en_ecc_read_int == 1) begin + $display("DRC Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ); + finish_error = 1; + end + + end // case: "TDP" + "SDP" : begin + ram_mode_int = 0; + + if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin + + $display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB18E1 instance %m."); + + finish_error = 1; + + end + + + if (BRAM_SIZE == 18) begin + if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin + + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP."); + + finish_error = 1; + end + end + else begin + + if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP."); + finish_error = 1; + end + end // else: !if(BRAM_SIZE == 18) + + end // case: "SDP" + default : begin + $display("Attribute Syntax Error : The attribute RAM_MODE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE); + finish_error = 1; + end + endcase + + + case (WRITE_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_A) + + + case (WRITE_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_B) + + + case (READ_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_A) + + + case (READ_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_B) + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB18E1 instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a = 2'b00; + "READ_FIRST" : wr_mode_a = 2'b01; + "NO_CHANGE" : wr_mode_a = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b = 2'b00; + "READ_FIRST" : wr_mode_b = 2'b01; + "NO_CHANGE" : wr_mode_b = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + case (RAM_EXTENSION_A) + "UPPER" : cascade_a = 2'b11; + "LOWER" : cascade_a = 2'b01; + "NONE" : cascade_a = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); + finish_error = 1; + end + endcase + + + case (RAM_EXTENSION_B) + "UPPER" : cascade_b = 2'b11; + "LOWER" : cascade_b = 2'b01; + "NONE" : cascade_b = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB18E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + case (RSTREG_PRIORITY_A) + "RSTREG" : rstreg_priority_a_int = 1; + "REGCE" : rstreg_priority_a_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A); + finish_error = 1; + end + endcase + + + case (RSTREG_PRIORITY_B) + "RSTREG" : rstreg_priority_b_int = 1; + "REGCE" : rstreg_priority_b_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B); + finish_error = 1; + end + endcase + + + if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin + $display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB18E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE."); + finish_error = 1; + end + + + case (RDADDR_COLLISION_HWCONFIG) + "DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0; + "PERFORMANCE" : rdaddr_collision_hwconfig_int = 1; + default : begin + $display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB18E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG); + finish_error = 1; + end + endcase + + + if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE); + finish_error = 1; + end + + + if (finish_error == 1) + #1 $finish; + + + end // initial begin + + + // GSR + always @(GSR) + if (GSR) begin + + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + assign rdaddrecc_out = 9'b0; + + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + deassign rdaddrecc_out; + + end + + + always @(time_clka_period or time_clkb_period) begin + + if (time_clka_period != 0 && time_clkb_period != 0) begin + + if (time_clka_period <= time_clkb_period) begin + + if (time_clka_period <= SETUP_READ_FIRST) begin + time_period = time_clka_period; + end + else begin + time_period = SETUP_READ_FIRST; + end + + end + else if (time_clkb_period <= SETUP_READ_FIRST) + time_period = time_clkb_period; + else + time_period = SETUP_READ_FIRST; + + end + end + + // registering signals + always @(posedge CLKA) begin + +`ifdef MODEL_TECH + #0 rising_clka = 1; // mentor race condition check +`else + rising_clka = 1; +`endif + if (time_skew_a_flag == 0) begin + if ($time > 110000) begin + time_clka_period = $time - time_port_a; + time_skew_a_flag = 1; + end + end + + + if (ENA === 1'b1) begin + time_port_a = $time; + addra_reg = ADDRA; + wea_reg = WEA; + dia_reg = DIA; + dipa_reg = DIPA; + ox_addra_reconstruct_reg = ox_addra_reconstruct; + end + + end + + always @(posedge CLKB) begin + +`ifdef MODEL_TECH + #0 rising_clkb = 1; // mentor race condition check +`else + rising_clkb = 1; +`endif + + if (time_skew_b_flag == 0) begin + if ($time > 110000) begin + time_clkb_period = $time - time_port_b; + time_skew_b_flag = 1; + end + end + + + if (ENB === 1'b1) begin + time_port_b = $time; + addrb_reg = ADDRB; + web_reg = WEB; + enb_reg = ENB; + dib_reg = DIB; + dipb_reg = DIPB; + ox_addrb_reconstruct_reg = ox_addrb_reconstruct; + end + + end // always @ (posedge CLKB) + + + // CLKA and CLKB + always @(posedge rising_clka or posedge rising_clkb) begin + + // Registering addr[15] for cascade mode + if (rising_clka) + if (cascade_a[1]) + addra_in_15_reg_bram = ~ADDRA[15]; + else + addra_in_15_reg_bram = ADDRA[15]; + + if (rising_clkb) + if (cascade_b[1]) + addrb_in_15_reg_bram = ~ADDRB[15]; + else + addrb_in_15_reg_bram = ADDRB[15]; + + if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (GSR === 1'b0) begin + + if (time_port_a > time_port_b) begin + + if (time_port_a - time_port_b <= sync_clk_skew) begin + viol_time = 1; + end + else if (time_port_a - time_port_b <= time_period) begin + viol_time = 2; + end + end + else begin + + if (time_port_b - time_port_a <= sync_clk_skew) begin + viol_time = 1; + end + else if (time_port_b - time_port_a <= time_period) begin + viol_time = 2; + end + + end // else: !if(time_port_a > time_port_b) + + + if (ENA === 1'b0 || ENB === 1'b0) + viol_time = 0; + + + if ((WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000)) + if ((WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00)) + viol_time = 0; + + + if (viol_time != 0) begin + + if (SIM_DEVICE == "VIRTEX6") begin + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + + if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b01; + chk_col_same_clk = 1; + + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin + doa_buf = dob_buf; + dopa_buf = dopb_buf; + end + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin + dob_buf = doa_buf; + dopb_buf = dopa_buf; + end + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + chk_col_same_clk = 0; + + task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin + task_col_wr_ram_a (2'b10, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b10, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + end + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin + + viol_type = 2'b01; + chk_ox_msg = 1; + chk_ox_same_clk = 1; + + if (time_port_a > time_port_b) + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + else if (time_port_b > time_port_a) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + + chk_ox_msg = 0; + chk_ox_same_clk = 0; + + task_ox_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + + if (rdaddr_collision_hwconfig_int == 1) begin + task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, ADDRB); + end + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (rising_clka && rising_clkb) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + + + if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b10, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin + + viol_type = 2'b10; + chk_ox_msg = 1; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + // get msg + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + chk_ox_msg = 0; + + task_ox_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, addrb_reg); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + + + if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + + task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin + + viol_type = 2'b11; + chk_ox_msg = 1; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + // get msg + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + chk_ox_msg = 0; + + task_ox_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, ADDRB); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (!rising_clka && rising_clkb) + + + end // if (SIM_DEVICE == "VIRTEX6") + else begin // 7series + + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + + if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b01; + chk_col_same_clk = 1; + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin + doa_buf = dob_buf; + dopa_buf = dopb_buf; + end + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin + dob_buf = doa_buf; + dopb_buf = dopa_buf; + end + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + chk_col_same_clk = 0; + + task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if ((rising_clka && rising_clkb) || viol_time == 1) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + + + if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + + end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + + + if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + + task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + + end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if (!rising_clka && rising_clkb) + + + end // else: !if(SIM_DEVICE == "VIRTEX6") + + + + end // if (viol_time != 0) + end // if (GSR === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) + + +/**************************** Port A ****************************************/ + if (rising_clka) begin + + // DRC + if (RSTRAMA === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m."); + + // end DRC + + + // registering ADDRA[15] the second time + if (REGCEA) + addra_in_15_reg1 = addra_in_15_reg; + + + if (ENA && (wr_mode_a != 2'b10 || WEA[0] == 0 || RSTRAMA == 1'b1)) + if (cascade_a[1]) + addra_in_15_reg = ~ADDRA[15]; + else + addra_in_15_reg = ADDRA[15]; + + + if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin + + // SRVAL + if (RSTRAMA === 1'b1) begin + + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + + if (viol_time == 0) begin + + // Read first + if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + + // ECC decode + if (ram_mode_int == 0 && en_ecc_read_int == 1) begin + + dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); + + syndrome = dopr_ecc ^ dopa_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + doa_buf = dia_in_ecc_corrected; + + dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dopa_buf = dipa_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(syndrome !== 0) + + + // output of rdaddrecc + rdaddrecc_out[8:0] <= ADDRA[14:6]; + + end // if (ram_mode_int == 0 && en_ecc_read_int == 1) + end // if (wr_mode_a == 2'b01) + + + // Write + task_wr_ram_a (WEA, DIA, DIPA, ADDRA); + + // Read if not read first + if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1)) + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + end // if (viol_time == 0) + + end // if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) + + end // if (rising_clka) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkb) begin + + // DRC + if (RSTRAMB === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m."); + + if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin + + if (injectsbiterr_in === 1) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m."); + + if (injectdbiterr_in === 1) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m."); + + end + // End DRC + + + if (REGCEB) + addrb_in_15_reg1 = addrb_in_15_reg; + + + if (ENB && (wr_mode_b != 2'b10 || WEB[0] == 0 || RSTRAMB == 1'b1)) + if (cascade_b[1]) + addrb_in_15_reg = ~ADDRB[15]; + else + addrb_in_15_reg = ADDRB[15]; + + + if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + + // SRVAL + if (RSTRAMB === 1'b1) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + end + + + if (viol_time == 0) begin + + // ECC encode + if (ram_mode_int == 0 && en_ecc_write_int == 1) begin + dip_ecc = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc; + dipb_in_ecc = dip_ecc; + end + else + dipb_in_ecc = DIPB; + + + dib_in_ecc = DIB; + + + // injecting error + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin // double bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + dib_in_ecc[62] = ~dib_in_ecc[62]; + end + else if (injectsbiterr_in === 1) begin // single bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + // Read first + if (wr_mode_b == 2'b01 && RSTRAMB === 1'b0) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + + // Write + task_wr_ram_b (WEB, dib_in_ecc, dipb_in_ecc, ADDRB); + + + // Read if not read first + if (wr_mode_b != 2'b01 && RSTRAMB === 1'b0) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + end // if (viol_time == 0) + + + end // if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) + + end // if (rising_clkb) + // end of port B + + + if (GSR == 1'b0) begin + + // writing outputs of port A + if (ENA && (rising_clka || viol_time != 0)) begin + + if (RSTRAMA === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))) begin + + doa_out <= doa_buf; + + if (ra_width >= 8) + dopa_out <= dopa_buf; + + end + + end + + + // writing outputs of port B + if (ENB && (rising_clkb || viol_time != 0)) begin + + if (RSTRAMB === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) begin + + dob_out <= dob_buf; + + if (rb_width >= 8) + dopb_out <= dopb_buf; + + end + + end + + end // if (GSR == 1'b0) + + + viol_time = 0; +`ifdef MODEL_TECH + #0 rising_clka = 0; // mentor race condition check + #0 rising_clkb = 0; // mentor race condition check +`else + rising_clka = 0; + rising_clkb = 0; +`endif + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + end // always @ (posedge rising_clka or posedge rising_clkb) + + + // ********* Cascade Port A ******** + always @(posedge CLKA or CASCADEINA or addra_in_15_reg or doa_out or dopa_out) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin + doa_out_mux[0] = CASCADEINA; + end + else begin + doa_out_mux = doa_out; + + if (ra_width >= 8) + dopa_out_mux = dopa_out; + + end + + end + + // output register mode + always @(posedge CLKA or CASCADEINA or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin + doa_outreg_mux[0] = CASCADEINA; + end + else begin + doa_outreg_mux = doa_outreg; + + if (ra_width >= 8) + dopa_outreg_mux = dopa_outreg; + + end + + end + + + // ********* Cascade Port B ******** + always @(posedge CLKB or CASCADEINB or addrb_in_15_reg or dob_out or dopb_out) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin + dob_out_mux[0] = CASCADEINB; + end + else begin + dob_out_mux = dob_out; + + if (rb_width >= 8) + dopb_out_mux = dopb_out; + + end + + end + + // output register mode + always @(posedge CLKB or CASCADEINB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin + dob_outreg_mux[0] = CASCADEINB; + end + else begin + dob_outreg_mux = dob_outreg; + + if (rb_width >= 8) + dopb_outreg_mux = dopb_outreg; + + end + + end // always @ (posedge REGCLKB or CASCADEINREGB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) + + + // ***** Output Registers **** Port A ***** + always @(posedge CLKA or posedge GSR) begin + + if (DOA_REG == 1) begin + + if (GSR == 1'b1) begin + + rdaddrecc_outreg <= 9'b0; + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (GSR == 1'b0) begin + + if (REGCEA === 1'b1) begin + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + rdaddrecc_outreg <= rdaddrecc_out; + end + + + if (rstreg_priority_a_int == 0) begin // Virtex5 behavior + + if (REGCEA == 1'b1) begin + if (RSTREGA == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (RSTREGA == 1'b0) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end // if (REGCEA == 1'b1) + + end // if (rstreg_priority_a_int == 1'b0) + else begin + + if (RSTREGA == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + + else if (RSTREGA == 1'b0) begin + + if (REGCEA == 1'b1) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end + end // else: !if(rstreg_priority_a_int == 1'b0) + + end // if (GSR == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge CLKA or posedge GSR) + + + always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin + + case (DOA_REG) + + 0 : begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + rdaddrecc_out_out = rdaddrecc_out; + DOA[0 +: ra_width] = doa_out_mux[0 +: ra_width]; + + if (ra_width >= 8) + DOPA[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp]; + + end + 1 : begin + dbiterr_out_out = dbiterr_outreg; + sbiterr_out_out = sbiterr_outreg; + DOA[0 +: ra_width] = doa_outreg_mux[0 +: ra_width]; + rdaddrecc_out_out = rdaddrecc_outreg; + + if (ra_width >= 8) + DOPA[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge CLKB or posedge GSR) begin + + if (DOB_REG == 1) begin + + if (GSR == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (GSR == 1'b0) begin + + if (rstreg_priority_b_int == 0) begin // Virtex5 behavior + + if (REGCEB == 1'b1) begin + if (RSTREGB == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (RSTREGB == 1'b0) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end // if (REGCEB == 1'b1) + + end // if (rstreg_priority_b_int == 1'b0) + else begin + + if (RSTREGB == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + + else if (RSTREGB == 1'b0) begin + + if (REGCEB == 1'b1) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end + end // else: !if(rstreg_priority_b_int == 1'b0) + + end // if (GSR == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge CLKB or posedge GSR) + + + always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin + + case (DOB_REG) + + 0 : begin + DOB[0 +: rb_width] = dob_out_mux[0 +: rb_width]; + + if (rb_width >= 8) + DOPB[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp]; + end + 1 : begin + DOB[0 +: rb_width] = dob_outreg_mux[0 +: rb_width]; + + if (rb_width >= 8) + DOPB[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) + + +endmodule // RB18_INTERNAL_VLOG + +`endcelldefine + +// end of RB18_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/src/unisims/RAMB18E2.v b/verilog/src/unisims/RAMB18E2.v new file mode 100644 index 0000000..c2e71ee --- /dev/null +++ b/verilog/src/unisims/RAMB18E2.v @@ -0,0 +1,2870 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 18K-bit Configurable Synchronous Block RAM +// /___/ /\ Filename : RAMB18E2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/28/2013 - intial from FIFO +// 03/09/2013 - update from various initial CR - collisions +// 03/22/2013 - sync5 yaml update, port ordering +// 03/25/2013 - 707719 - Add sync5 cascade feature +// 03/27/2013 - revert NO_CHANGE fix +// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP +// 04/23/2013 - PR683925 - add invertible pin support. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMB18E2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE_ORDER_A = "NONE", + parameter CASCADE_ORDER_B = "NONE", + parameter CLOCK_DOMAINS = "INDEPENDENT", + parameter integer DOA_REG = 1, + parameter integer DOB_REG = 1, + parameter ENADDRENA = "FALSE", + parameter ENADDRENB = "FALSE", + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [17:0] INIT_A = 18'h00000, + parameter [17:0] INIT_B = 18'h00000, + parameter INIT_FILE = "NONE", + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0, + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0, + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0, + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0, + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0, + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0, + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0, + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0, + parameter RDADDRCHANGEA = "FALSE", + parameter RDADDRCHANGEB = "FALSE", + parameter integer READ_WIDTH_A = 0, + parameter integer READ_WIDTH_B = 0, + parameter RSTREG_PRIORITY_A = "RSTREG", + parameter RSTREG_PRIORITY_B = "RSTREG", + parameter SIM_COLLISION_CHECK = "ALL", + parameter SLEEP_ASYNC = "FALSE", + parameter [17:0] SRVAL_A = 18'h00000, + parameter [17:0] SRVAL_B = 18'h00000, + parameter WRITE_MODE_A = "NO_CHANGE", + parameter WRITE_MODE_B = "NO_CHANGE", + parameter integer WRITE_WIDTH_A = 0, + parameter integer WRITE_WIDTH_B = 0 +)( + output [15:0] CASDOUTA, + output [15:0] CASDOUTB, + output [1:0] CASDOUTPA, + output [1:0] CASDOUTPB, + output [15:0] DOUTADOUT, + output [15:0] DOUTBDOUT, + output [1:0] DOUTPADOUTP, + output [1:0] DOUTPBDOUTP, + + input [13:0] ADDRARDADDR, + input [13:0] ADDRBWRADDR, + input ADDRENA, + input ADDRENB, + input CASDIMUXA, + input CASDIMUXB, + input [15:0] CASDINA, + input [15:0] CASDINB, + input [1:0] CASDINPA, + input [1:0] CASDINPB, + input CASDOMUXA, + input CASDOMUXB, + input CASDOMUXEN_A, + input CASDOMUXEN_B, + input CASOREGIMUXA, + input CASOREGIMUXB, + input CASOREGIMUXEN_A, + input CASOREGIMUXEN_B, + input CLKARDCLK, + input CLKBWRCLK, + input [15:0] DINADIN, + input [15:0] DINBDIN, + input [1:0] DINPADINP, + input [1:0] DINPBDINP, + input ENARDEN, + input ENBWREN, + input REGCEAREGCE, + input REGCEB, + input RSTRAMARSTRAM, + input RSTRAMB, + input RSTREGARSTREG, + input RSTREGB, + input SLEEP, + input [1:0] WEA, + input [3:0] WEBWE +); + +// define constants + localparam MODULE_NAME = "RAMB18E2"; + +// Parameter encodings and registers + localparam CASCADE_ORDER_A_FIRST = 1; + localparam CASCADE_ORDER_A_LAST = 2; + localparam CASCADE_ORDER_A_MIDDLE = 3; + localparam CASCADE_ORDER_A_NONE = 0; + localparam CASCADE_ORDER_B_FIRST = 1; + localparam CASCADE_ORDER_B_LAST = 2; + localparam CASCADE_ORDER_B_MIDDLE = 3; + localparam CASCADE_ORDER_B_NONE = 0; + localparam CLOCK_DOMAINS_COMMON = 1; + localparam CLOCK_DOMAINS_INDEPENDENT = 0; + localparam DOA_REG_0 = 1; + localparam DOA_REG_1 = 0; + localparam DOB_REG_0 = 1; + localparam DOB_REG_1 = 0; + localparam ENADDRENA_FALSE = 0; + localparam ENADDRENA_TRUE = 1; + localparam ENADDRENB_FALSE = 0; + localparam ENADDRENB_TRUE = 1; + localparam RDADDRCHANGEA_FALSE = 0; + localparam RDADDRCHANGEA_TRUE = 1; + localparam RDADDRCHANGEB_FALSE = 0; + localparam RDADDRCHANGEB_TRUE = 1; + localparam READ_WIDTH_A_0 = 1; + localparam READ_WIDTH_A_1 = 1; + localparam READ_WIDTH_A_18 = 16; + localparam READ_WIDTH_A_2 = 2; + localparam READ_WIDTH_A_36 = 32; + localparam READ_WIDTH_A_4 = 4; + localparam READ_WIDTH_A_9 = 8; + localparam READ_WIDTH_B_0 = 1; + localparam READ_WIDTH_B_1 = 1; + localparam READ_WIDTH_B_18 = 16; + localparam READ_WIDTH_B_2 = 2; + localparam READ_WIDTH_B_4 = 4; + localparam READ_WIDTH_B_9 = 8; + localparam RSTREG_PRIORITY_A_REGCE = 1; + localparam RSTREG_PRIORITY_A_RSTREG = 0; + localparam RSTREG_PRIORITY_B_REGCE = 1; + localparam RSTREG_PRIORITY_B_RSTREG = 0; + localparam SIM_COLLISION_CHECK_ALL = 0; + localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1; + localparam SIM_COLLISION_CHECK_NONE = 2; + localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3; + localparam SLEEP_ASYNC_FALSE = 0; + localparam SLEEP_ASYNC_TRUE = 1; + localparam WRITE_MODE_A_NO_CHANGE = 0; + localparam WRITE_MODE_A_READ_FIRST = 1; + localparam WRITE_MODE_A_WRITE_FIRST = 2; + localparam WRITE_MODE_B_NO_CHANGE = 0; + localparam WRITE_MODE_B_READ_FIRST = 1; + localparam WRITE_MODE_B_WRITE_FIRST = 2; + localparam WRITE_WIDTH_A_0 = 1; + localparam WRITE_WIDTH_A_1 = 1; + localparam WRITE_WIDTH_A_18 = 16; + localparam WRITE_WIDTH_A_2 = 2; + localparam WRITE_WIDTH_A_4 = 4; + localparam WRITE_WIDTH_A_9 = 8; + localparam WRITE_WIDTH_B_0 = 1; + localparam WRITE_WIDTH_B_1 = 1; + localparam WRITE_WIDTH_B_18 = 16; + localparam WRITE_WIDTH_B_2 = 2; + localparam WRITE_WIDTH_B_36 = 32; + localparam WRITE_WIDTH_B_4 = 4; + localparam WRITE_WIDTH_B_9 = 8; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "RAMB18E2_dr.v" +`else + localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A; + localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B; + localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS; + localparam [0:0] DOA_REG_REG = DOA_REG; + localparam [0:0] DOB_REG_REG = DOB_REG; + localparam [40:1] ENADDRENA_REG = ENADDRENA; + localparam [40:1] ENADDRENB_REG = ENADDRENB; + localparam [255:0] INITP_00_REG = INITP_00; + localparam [255:0] INITP_01_REG = INITP_01; + localparam [255:0] INITP_02_REG = INITP_02; + localparam [255:0] INITP_03_REG = INITP_03; + localparam [255:0] INITP_04_REG = INITP_04; + localparam [255:0] INITP_05_REG = INITP_05; + localparam [255:0] INITP_06_REG = INITP_06; + localparam [255:0] INITP_07_REG = INITP_07; + localparam [255:0] INIT_00_REG = INIT_00; + localparam [255:0] INIT_01_REG = INIT_01; + localparam [255:0] INIT_02_REG = INIT_02; + localparam [255:0] INIT_03_REG = INIT_03; + localparam [255:0] INIT_04_REG = INIT_04; + localparam [255:0] INIT_05_REG = INIT_05; + localparam [255:0] INIT_06_REG = INIT_06; + localparam [255:0] INIT_07_REG = INIT_07; + localparam [255:0] INIT_08_REG = INIT_08; + localparam [255:0] INIT_09_REG = INIT_09; + localparam [255:0] INIT_0A_REG = INIT_0A; + localparam [255:0] INIT_0B_REG = INIT_0B; + localparam [255:0] INIT_0C_REG = INIT_0C; + localparam [255:0] INIT_0D_REG = INIT_0D; + localparam [255:0] INIT_0E_REG = INIT_0E; + localparam [255:0] INIT_0F_REG = INIT_0F; + localparam [255:0] INIT_10_REG = INIT_10; + localparam [255:0] INIT_11_REG = INIT_11; + localparam [255:0] INIT_12_REG = INIT_12; + localparam [255:0] INIT_13_REG = INIT_13; + localparam [255:0] INIT_14_REG = INIT_14; + localparam [255:0] INIT_15_REG = INIT_15; + localparam [255:0] INIT_16_REG = INIT_16; + localparam [255:0] INIT_17_REG = INIT_17; + localparam [255:0] INIT_18_REG = INIT_18; + localparam [255:0] INIT_19_REG = INIT_19; + localparam [255:0] INIT_1A_REG = INIT_1A; + localparam [255:0] INIT_1B_REG = INIT_1B; + localparam [255:0] INIT_1C_REG = INIT_1C; + localparam [255:0] INIT_1D_REG = INIT_1D; + localparam [255:0] INIT_1E_REG = INIT_1E; + localparam [255:0] INIT_1F_REG = INIT_1F; + localparam [255:0] INIT_20_REG = INIT_20; + localparam [255:0] INIT_21_REG = INIT_21; + localparam [255:0] INIT_22_REG = INIT_22; + localparam [255:0] INIT_23_REG = INIT_23; + localparam [255:0] INIT_24_REG = INIT_24; + localparam [255:0] INIT_25_REG = INIT_25; + localparam [255:0] INIT_26_REG = INIT_26; + localparam [255:0] INIT_27_REG = INIT_27; + localparam [255:0] INIT_28_REG = INIT_28; + localparam [255:0] INIT_29_REG = INIT_29; + localparam [255:0] INIT_2A_REG = INIT_2A; + localparam [255:0] INIT_2B_REG = INIT_2B; + localparam [255:0] INIT_2C_REG = INIT_2C; + localparam [255:0] INIT_2D_REG = INIT_2D; + localparam [255:0] INIT_2E_REG = INIT_2E; + localparam [255:0] INIT_2F_REG = INIT_2F; + localparam [255:0] INIT_30_REG = INIT_30; + localparam [255:0] INIT_31_REG = INIT_31; + localparam [255:0] INIT_32_REG = INIT_32; + localparam [255:0] INIT_33_REG = INIT_33; + localparam [255:0] INIT_34_REG = INIT_34; + localparam [255:0] INIT_35_REG = INIT_35; + localparam [255:0] INIT_36_REG = INIT_36; + localparam [255:0] INIT_37_REG = INIT_37; + localparam [255:0] INIT_38_REG = INIT_38; + localparam [255:0] INIT_39_REG = INIT_39; + localparam [255:0] INIT_3A_REG = INIT_3A; + localparam [255:0] INIT_3B_REG = INIT_3B; + localparam [255:0] INIT_3C_REG = INIT_3C; + localparam [255:0] INIT_3D_REG = INIT_3D; + localparam [255:0] INIT_3E_REG = INIT_3E; + localparam [255:0] INIT_3F_REG = INIT_3F; + localparam [17:0] INIT_A_REG = INIT_A; + localparam [17:0] INIT_B_REG = INIT_B; + localparam INIT_FILE_REG = INIT_FILE; + localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED; + localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED; + localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED; + localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED; + localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED; + localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED; + localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED; + localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED; + localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA; + localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB; + localparam [5:0] READ_WIDTH_A_REG = READ_WIDTH_A; + localparam [4:0] READ_WIDTH_B_REG = READ_WIDTH_B; + localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A; + localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B; + localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK; + localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC; + localparam [17:0] SRVAL_A_REG = SRVAL_A; + localparam [17:0] SRVAL_B_REG = SRVAL_B; + localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A; + localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B; + localparam [4:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A; + localparam [5:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B; +`endif + + wire [1:0] CASCADE_ORDER_A_BIN; + wire [1:0] CASCADE_ORDER_B_BIN; + wire CLOCK_DOMAINS_BIN; + wire DOA_REG_BIN; + wire DOB_REG_BIN; + wire ENADDRENA_BIN; + wire ENADDRENB_BIN; + wire [255:0] INITP_BIN [0:7]; + wire [255:0] INIT_BIN [0:63]; + wire [17:0] INIT_A_BIN; + wire [17:0] INIT_B_BIN; + wire IS_CLKARDCLK_INVERTED_BIN; + wire IS_CLKBWRCLK_INVERTED_BIN; + wire IS_ENARDEN_INVERTED_BIN; + wire IS_ENBWREN_INVERTED_BIN; + wire IS_RSTRAMARSTRAM_INVERTED_BIN; + wire IS_RSTRAMB_INVERTED_BIN; + wire IS_RSTREGARSTREG_INVERTED_BIN; + wire IS_RSTREGB_INVERTED_BIN; + wire RDADDRCHANGEA_BIN; + wire RDADDRCHANGEB_BIN; + wire [5:0] READ_WIDTH_A_BIN; + wire [5:0] READ_WIDTH_B_BIN; + wire RSTREG_PRIORITY_A_BIN; + wire RSTREG_PRIORITY_B_BIN; + wire [1:0] SIM_COLLISION_CHECK_BIN; + wire SLEEP_ASYNC_BIN; + wire [17:0] SRVAL_A_BIN; + wire [17:0] SRVAL_B_BIN; + wire [1:0] WRITE_MODE_A_BIN; + wire [1:0] WRITE_MODE_B_BIN; + wire [6:0] WRITE_WIDTH_A_BIN; + wire [6:0] WRITE_WIDTH_B_BIN; + reg INIT_MEM = 0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR || INIT_MEM; + + wire [15:0] CASDOUTA_out; + wire [15:0] CASDOUTB_out; + reg [15:0] DOUTADOUT_out; + reg [15:0] DOUTBDOUT_out; + wire [1:0] CASDOUTPA_out; + wire [1:0] CASDOUTPB_out; + reg [1:0] DOUTPADOUTP_out; + reg [1:0] DOUTPBDOUTP_out; + + wire ADDRENA_in; + wire ADDRENB_in; + wire CASDIMUXA_in; + wire CASDIMUXB_in; + wire CASDOMUXA_in; + wire CASDOMUXB_in; + wire CASDOMUXEN_A_in; + wire CASDOMUXEN_B_in; + wire CASOREGIMUXA_in; + wire CASOREGIMUXB_in; + wire CASOREGIMUXEN_A_in; + wire CASOREGIMUXEN_B_in; + wire CLKARDCLK_in; + wire CLKBWRCLK_in; + wire ENARDEN_in; + wire ENBWREN_in; + wire REGCEAREGCE_in; + wire REGCEB_in; + wire RSTRAMARSTRAM_in; + wire RSTRAMB_in; + wire RSTREGARSTREG_in; + wire RSTREGB_in; + wire SLEEP_in; + reg [13:0] ADDRARDADDR_in; + reg [13:0] ADDRBWRADDR_in; + wire [15:0] CASDINA_in; + wire [15:0] CASDINB_in; + reg [15:0] DINADIN_in; + reg [15:0] DINBDIN_in; + wire [1:0] CASDINPA_in; + wire [1:0] CASDINPB_in; + reg [1:0] DINPADINP_in; + reg [1:0] DINPBDINP_in; + wire [1:0] WEA_in; + wire [3:0] WEBWE_in; + +`ifdef XIL_TIMING + wire ADDRENA_delay; + wire ADDRENB_delay; + wire CASDIMUXA_delay; + wire CASDIMUXB_delay; + wire CASDOMUXA_delay; + wire CASDOMUXB_delay; + wire CASDOMUXEN_A_delay; + wire CASDOMUXEN_B_delay; + wire CASOREGIMUXA_delay; + wire CASOREGIMUXB_delay; + wire CASOREGIMUXEN_A_delay; + wire CASOREGIMUXEN_B_delay; + wire CLKARDCLK_delay; + wire CLKBWRCLK_delay; + wire ENARDEN_delay; + wire ENBWREN_delay; + wire REGCEAREGCE_delay; + wire REGCEB_delay; + wire RSTRAMARSTRAM_delay; + wire RSTRAMB_delay; + wire RSTREGARSTREG_delay; + wire RSTREGB_delay; + wire SLEEP_delay; + wire [13:0] ADDRARDADDR_delay; + wire [13:0] ADDRBWRADDR_delay; + wire [15:0] CASDINA_delay; + wire [15:0] CASDINB_delay; + wire [15:0] DINADIN_delay; + wire [15:0] DINBDIN_delay; + wire [1:0] CASDINPA_delay; + wire [1:0] CASDINPB_delay; + wire [1:0] DINPADINP_delay; + wire [1:0] DINPBDINP_delay; + wire [1:0] WEA_delay; + wire [3:0] WEBWE_delay; +`endif + + assign CASDOUTA = CASDOUTA_out; + assign CASDOUTB = CASDOUTB_out; + assign CASDOUTPA = CASDOUTPA_out; + assign CASDOUTPB = CASDOUTPB_out; + assign DOUTADOUT = DOUTADOUT_out; + assign DOUTBDOUT = DOUTBDOUT_out; + assign DOUTPADOUTP = DOUTPADOUTP_out; + assign DOUTPBDOUTP = DOUTPBDOUTP_out; + +`ifdef XIL_TIMING + always @ (*) ADDRARDADDR_in = ADDRARDADDR_delay; + always @ (*) ADDRBWRADDR_in = ADDRBWRADDR_delay; + assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA_delay; // rv 1 + assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB_delay; // rv 1 + assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA_delay; // rv 0 + assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB_delay; // rv 0 + assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA_delay[0]; // rv 0 + assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA_delay[10]; // rv 0 + assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA_delay[11]; // rv 0 + assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA_delay[12]; // rv 0 + assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA_delay[13]; // rv 0 + assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA_delay[14]; // rv 0 + assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA_delay[15]; // rv 0 + assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA_delay[1]; // rv 0 + assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA_delay[2]; // rv 0 + assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA_delay[3]; // rv 0 + assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA_delay[4]; // rv 0 + assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA_delay[5]; // rv 0 + assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA_delay[6]; // rv 0 + assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA_delay[7]; // rv 0 + assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA_delay[8]; // rv 0 + assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA_delay[9]; // rv 0 + assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB_delay[0]; // rv 0 + assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB_delay[10]; // rv 0 + assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB_delay[11]; // rv 0 + assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB_delay[12]; // rv 0 + assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB_delay[13]; // rv 0 + assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB_delay[14]; // rv 0 + assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB_delay[15]; // rv 0 + assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB_delay[1]; // rv 0 + assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB_delay[2]; // rv 0 + assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB_delay[3]; // rv 0 + assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB_delay[4]; // rv 0 + assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB_delay[5]; // rv 0 + assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB_delay[6]; // rv 0 + assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB_delay[7]; // rv 0 + assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB_delay[8]; // rv 0 + assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB_delay[9]; // rv 0 + assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA_delay[0]; // rv 0 + assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA_delay[1]; // rv 0 + assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB_delay[0]; // rv 0 + assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB_delay[1]; // rv 0 + assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA_delay; // rv 0 + assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB_delay; // rv 0 + assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A_delay; // rv 1 + assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B_delay; // rv 1 + assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA_delay; // rv 0 + assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB_delay; // rv 0 + assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A_delay; // rv 1 + assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B_delay; // rv 1 + assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0 + assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0 + always @ (*) DINADIN_in = DINADIN_delay; + always @ (*) DINBDIN_in = DINBDIN_delay; + always @ (*) DINPADINP_in = DINPADINP_delay; + always @ (*) DINPBDINP_in = DINPBDINP_delay; + assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN); // rv 0 + assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN); // rv 0 + assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE_delay; // rv 1 + assign REGCEB_in = (REGCEB === 1'bz) || REGCEB_delay; // rv 1 + assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0 + assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN); // rv 0 + assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0 + assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 + assign WEA_in[0] = (WEA[0] === 1'bz) || WEA_delay[0]; // rv 1 + assign WEA_in[1] = (WEA[1] === 1'bz) || WEA_delay[1]; // rv 1 + assign WEBWE_in[0] = (WEBWE[0] === 1'bz) || WEBWE_delay[0]; // rv 1 + assign WEBWE_in[1] = (WEBWE[1] === 1'bz) || WEBWE_delay[1]; // rv 1 + assign WEBWE_in[2] = (WEBWE[2] === 1'bz) || WEBWE_delay[2]; // rv 1 + assign WEBWE_in[3] = (WEBWE[3] === 1'bz) || WEBWE_delay[3]; // rv 1 +`else + always @ (*) ADDRARDADDR_in = ADDRARDADDR; + always @ (*) ADDRBWRADDR_in = ADDRBWRADDR; + assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA; // rv 1 + assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB; // rv 1 + assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA; // rv 0 + assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB; // rv 0 + assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA[0]; // rv 0 + assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA[10]; // rv 0 + assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA[11]; // rv 0 + assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA[12]; // rv 0 + assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA[13]; // rv 0 + assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA[14]; // rv 0 + assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA[15]; // rv 0 + assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA[1]; // rv 0 + assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA[2]; // rv 0 + assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA[3]; // rv 0 + assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA[4]; // rv 0 + assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA[5]; // rv 0 + assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA[6]; // rv 0 + assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA[7]; // rv 0 + assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA[8]; // rv 0 + assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA[9]; // rv 0 + assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB[0]; // rv 0 + assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB[10]; // rv 0 + assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB[11]; // rv 0 + assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB[12]; // rv 0 + assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB[13]; // rv 0 + assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB[14]; // rv 0 + assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB[15]; // rv 0 + assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB[1]; // rv 0 + assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB[2]; // rv 0 + assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB[3]; // rv 0 + assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB[4]; // rv 0 + assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB[5]; // rv 0 + assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB[6]; // rv 0 + assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB[7]; // rv 0 + assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB[8]; // rv 0 + assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB[9]; // rv 0 + assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA[0]; // rv 0 + assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA[1]; // rv 0 + assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB[0]; // rv 0 + assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB[1]; // rv 0 + assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA; // rv 0 + assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB; // rv 0 + assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A; // rv 1 + assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B; // rv 1 + assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA; // rv 0 + assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB; // rv 0 + assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A; // rv 1 + assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B; // rv 1 + assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0 + assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0 +// always @ (CLKARDCLK) begin +// if ((CLKARDCLK === 1'bz) || // rv 0 +// (CLKARDCLK === IS_CLKARDCLK_INVERTED_BIN)) CLKARDCLK_in = 1'b0; +// else CLKARDCLK_in = 1'b1; +// end +// always @ (CLKBWRCLK) begin +// if ((CLKBWRCLK === 1'bz) || // rv 0 +// (CLKBWRCLK === IS_CLKBWRCLK_INVERTED_BIN)) CLKBWRCLK_in = 1'b0; +// else CLKBWRCLK_in = 1'b1; +// end + always @ (*) DINADIN_in = DINADIN; + always @ (*) DINBDIN_in = DINBDIN; + always @ (*) DINPADINP_in = DINPADINP; + always @ (*) DINPBDINP_in = DINPBDINP; + assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN ^ IS_ENARDEN_INVERTED_BIN); // rv 0 + assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN ^ IS_ENBWREN_INVERTED_BIN); // rv 0 + assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE; // rv 1 + assign REGCEB_in = (REGCEB === 1'bz) || REGCEB; // rv 1 + assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0 + assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB ^ IS_RSTRAMB_INVERTED_BIN); // rv 0 + assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0 + assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB ^ IS_RSTREGB_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 + assign WEA_in[0] = (WEA[0] === 1'bz) || WEA[0]; // rv 1 + assign WEA_in[1] = (WEA[1] === 1'bz) || WEA[1]; // rv 1 + assign WEBWE_in[0] = (WEBWE[0] === 1'bz) || WEBWE[0]; // rv 1 + assign WEBWE_in[1] = (WEBWE[1] === 1'bz) || WEBWE[1]; // rv 1 + assign WEBWE_in[2] = (WEBWE[2] === 1'bz) || WEBWE[2]; // rv 1 + assign WEBWE_in[3] = (WEBWE[3] === 1'bz) || WEBWE[3]; // rv 1 +`endif + +// internal variables, signals, busses + localparam integer ADDR_WIDTH = 14; + localparam integer INIT_WIDTH = 36; + localparam integer D_WIDTH = 32; + localparam integer DP_WIDTH = 4; + + localparam mem_width = 1; + localparam memp_width = 1; + localparam mem_size = 16384; + localparam mem_depth = mem_size; + localparam memp_depth = mem_size/8; + localparam mem_pad = 32; + localparam memp_pad = 4; +//localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : READ_WIDTH_B; + localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? ((READ_WIDTH_A == 0) ? 1 : READ_WIDTH_A) : + READ_WIDTH_B; + localparam tmp_memp_width = (tmp_mem_width < 9) ? 0 : + (tmp_mem_width < 18) ? 1 : + (tmp_mem_width < 36) ? 2 : + (tmp_mem_width < 72) ? 4 : 8; + localparam tmp_mem_depth = mem_size/(tmp_mem_width-tmp_memp_width); + reg [tmp_mem_width-1:0] tmp_mem_tmp = 0; + integer t_coll_min = 50; + integer t_coll_max = 500 - 99; + reg [255:0] INITP_TMP; + reg [255:0] INIT_TMP; + integer i=0; + integer j=0; + integer k=0; + integer ra=0; + integer raa=0; + integer raw=0; + integer wb=0; + integer rb=0; + integer rbb=0; + integer rbw=0; + integer wa=0; + integer rd_loops_a = 1; + integer wr_loops_a = 1; + integer rd_loops_b = 1; + integer rd_loops_f = 1; + integer wr_loops_b = 1; + localparam max_rd_loops = D_WIDTH; + localparam max_wr_loops = D_WIDTH; + wire SLEEP_A_int; + wire SLEEP_B_int; + reg [1:0] SLEEP_A_reg = 2'b0; + reg [1:0] SLEEP_B_reg = 2'b0; + wire RSTREG_A_int; + wire REGCE_A_int; + wire ADDRENA_int; + wire ADDRENB_int; + wire RSTREG_B_int; + wire REGCE_B_int; + reg CASDOMUXA_reg = 1'b0; + reg CASOREGIMUXA_reg = 1'b0; + reg CASDOMUXB_reg = 1'b0; + reg CASOREGIMUXB_reg = 1'b0; + wire CASDOMUXB_int; + wire [INIT_WIDTH-1:0] INIT_A_int; + wire [INIT_WIDTH-1:0] SRVAL_A_int; + wire [INIT_WIDTH/2-1:0] INIT_B_int; + wire [INIT_WIDTH/2-1:0] SRVAL_B_int; + + wire mem_wr_en_a; + reg mem_wr_en_a_wf = 1'b0; + reg [D_WIDTH/2-1:0] mem_we_a; + reg [DP_WIDTH/2-1:0] memp_we_a; + wire [D_WIDTH/2-1:0] mem_rm_doutb; + wire [DP_WIDTH/2-1:0] memp_rm_doutb; + wire [D_WIDTH-1:0] mem_rm_a; + wire [D_WIDTH-1:0] mem_rm_b; + wire [D_WIDTH-1:0] mem_wm_a; + wire [D_WIDTH-1:0] mem_wm_b; + reg wr_data_matches = 0; + reg wr_a_data_matches_rd_b_data = 0; + reg wr_b_data_matches_rd_a_data = 0; + wire mem_wr_en_b; + reg mem_wr_en_b_wf = 1'b0; + reg [D_WIDTH-1:0] mem_we_b; + reg [DP_WIDTH-1:0] memp_we_b; + wire [D_WIDTH-1:0] mem_rm_douta; + wire [DP_WIDTH-1:0] memp_rm_douta; + wire mem_rd_en_a; + wire mem_rst_a; + reg mem_is_rst_a = 1'b0; + wire mem_rd_en_b; + wire mem_rst_b; + reg mem_is_rst_b = 1'b0; + + reg mem [0 : mem_depth+mem_pad-1]; + reg [D_WIDTH/2-1 : 0] mem_wr_a; + reg wr_a_event = 1'b0; + reg wr_a_wf_event = 1'b0; + reg [D_WIDTH-1 : 0] ram_rd_a; + reg [D_WIDTH-1 : 0] mem_rd_a_wf; + reg [D_WIDTH-1 : 0] mem_wr_b; + reg wr_b_event = 1'b0; + reg wr_b_wf_event = 1'b0; + reg [D_WIDTH-1 : 0] mem_rd_b; + reg [D_WIDTH-1 : 0] mem_rd_b_rf; + reg [D_WIDTH-1 : 0] mem_rd_b_wf; + reg [D_WIDTH-1 : 0] mem_a_reg; + reg [D_WIDTH-1 : 0] mem_a_reg_mux; + reg [D_WIDTH-1 : 0] mem_a_lat; + reg [D_WIDTH/2-1 : 0] mem_b_reg; + reg [D_WIDTH/2-1 : 0] mem_b_reg_mux; + reg [D_WIDTH/2-1 : 0] mem_b_lat; + reg memp [0 : memp_depth+memp_pad-1]; + reg [DP_WIDTH-1 : 0] memp_wr_a; + reg [DP_WIDTH-1 : 0] ramp_rd_a; + reg [DP_WIDTH-1 : 0] memp_rd_a_wf; + reg [DP_WIDTH-1 : 0] memp_wr_b; + reg [DP_WIDTH-1 : 0] memp_rd_b; + reg [DP_WIDTH-1 : 0] memp_rd_b_rf; + reg [DP_WIDTH-1 : 0] memp_rd_b_wf; + reg [DP_WIDTH-1 : 0] memp_a_reg; + reg [DP_WIDTH-1 : 0] memp_a_reg_mux; + reg [DP_WIDTH-1 : 0] memp_a_lat; + reg [DP_WIDTH-1 : 0] memp_a_out; + reg [DP_WIDTH/2-1 : 0] memp_b_reg; + reg [DP_WIDTH/2-1 : 0] memp_b_reg_mux; + reg [DP_WIDTH/2-1 : 0] memp_b_lat; + reg [DP_WIDTH/2-1 : 0] memp_b_out; + wire [ADDR_WIDTH-1:0] rd_addr_a_mask; + wire [ADDR_WIDTH-1:0] rd_addr_b_mask; + wire [ADDR_WIDTH-1:0] wr_addr_a_mask; + wire [ADDR_WIDTH-1:0] wr_addr_b_mask; + reg [ADDR_WIDTH-1:0] rd_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_a_last = 0; + reg [ADDR_WIDTH-1:0] rd_addr_a_last = 0; + reg rd_addr_a_valid = 0; + reg rd_addr_a_nochange = 0; + reg [63:0] rd_addr_a_count = 0; + reg [63:0] rd_addr_a_nocount = 0; + reg [ADDR_WIDTH-1:0] rd_addr_b = 0; + reg [ADDR_WIDTH-1:0] wr_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b_last = 0; + reg [ADDR_WIDTH-1:0] rd_addr_b_last = 0; + reg rd_addr_b_valid = 0; + reg rd_addr_b_nochange = 0; + reg [63:0] rd_addr_b_count = 0; + reg [63:0] rd_addr_b_nocount = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b = 0; + reg wr_a_rd_b_addr_coll = 1'b0; + reg wr_addr_coll = 1'b0; + reg wr_b_rd_a_addr_coll = 1'b0; + wire sdp_mode; + wire sdp_mode_wr; + wire sdp_mode_rd; + +// clk period for collision window variables +integer t_max_a=3000, t_max_b=3000; +integer clk_period_a=10000, clk_period_b=10000; +reg clk_a_slowest = 1'b0; //victor drc +reg [63:0] total_clks_a=1, total_clks_b=1; +reg clka_toggled=1'b0, clkb_toggled=1'b0; +reg clka_done=1'b0, clkb_done=1'b0; +reg clka_timeout=0, clkb_timeout=0; +reg clka_changed = 1'b0; +reg clkb_changed = 1'b0; +wire clks_done; +reg en_clk_sync = 1'b0; + +task read_init_file; +reg [tmp_mem_width-1:0] tmp_mem [0:tmp_mem_depth-1]; +integer w,d; +begin + $readmemh (INIT_FILE_REG, tmp_mem); + for (d=0;d 0) begin + for (w=0;w READ_WIDTH_B_BIN) rd_loops_f <= READ_WIDTH_A_BIN; + else rd_loops_f <= READ_WIDTH_B_BIN; + end + always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN; + always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN; + +// determine clk period for collision window. +assign clks_done = clka_done && clkb_done; +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + clka_timeout = 0; + clka_done = 0; + if (glblGSR) @(negedge glblGSR); + @(posedge CLKARDCLK_in); + @(posedge CLKARDCLK_in); + @(posedge CLKARDCLK_in); + clka_timeout <= #6000 1; + @(posedge CLKARDCLK_in or posedge clka_timeout); + if (~clka_timeout) begin + t_max_a = $time/1.0; + @ (negedge CLKARDCLK_in) t_max_a = $time/1.0 - t_max_a; + end else begin + t_max_a = 2000; + end + clka_done = 1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + clk_period_a = $time/1.0; + @(posedge CLKARDCLK_in) + clk_period_a = $time/1.0 - clk_period_a; + clka_toggled = 1'b1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + clk_period_b = $time/1.0; + @(posedge CLKBWRCLK_in) + clk_period_b = $time/1.0 - clk_period_b; + clkb_toggled = 1'b1; +end + +//victor drc +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + if (clk_period_a <= clk_period_b) + clk_a_slowest <= 1'b0; + else + clk_a_slowest <= 1'b1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + clkb_timeout = 0; + clkb_done = 0; + if (glblGSR) @(negedge glblGSR); + @(posedge CLKBWRCLK_in); + @(posedge CLKBWRCLK_in); + @(posedge CLKBWRCLK_in); + clkb_timeout <= #6000 1; + @(posedge CLKBWRCLK_in or posedge clkb_timeout); + if (~clkb_timeout) begin + t_max_b = $time; + @ (negedge CLKBWRCLK_in) t_max_b = $time - t_max_b; + end else begin + t_max_b = 2000; + end + clkb_done = 1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge clks_done); + if (((t_max_a > 50) && (t_max_a <= 1500)) && + ((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 99; + if (((t_max_b > 50) && (t_max_b <= 1500)) && + ((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 99; + if ((t_max_a <= 50) && (t_max_b <= 50)) t_coll_max = 500 -99; + if ((t_max_a > 1500) && (t_max_b > 1500)) t_coll_max = 3000 -99; +end + + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) begin + SLEEP_A_reg <= 2'b0; + end + else begin + SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in}; + end + end + + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR) begin + SLEEP_B_reg <= 2'b0; + end + else begin + SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in}; + end + end + + assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in; + assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in; + + assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_36) ? 1'b1 : 1'b0; + assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? 1'b1 : 1'b0; + assign sdp_mode = sdp_mode_rd || sdp_mode_wr; + assign REGCE_A_int = REGCEAREGCE_in; + assign REGCE_B_int = REGCEB_in; + assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ? + RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in); + assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ? + RSTREGB_in : (RSTREGB_in && REGCEB_in); + assign ADDRENA_int = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_in : 1'b1; + assign ADDRENB_int = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_in : 1'b1; + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin + DOUTADOUT_out = CASDINA_in; + DOUTPADOUTP_out = CASDINPA_in; + end + else if (DOA_REG_BIN == DOA_REG_1) begin + DOUTADOUT_out = mem_a_reg ^ mem_rm_douta; + DOUTPADOUTP_out = memp_a_reg ^ memp_rm_douta; + end + else if (mem_wr_en_a_wf) begin + DOUTADOUT_out = mem_rd_a_wf ^ mem_rm_douta; + DOUTPADOUTP_out = memp_rd_a_wf ^ memp_rm_douta; + end + else begin + DOUTADOUT_out = mem_a_lat ^ mem_rm_douta; + DOUTPADOUTP_out = memp_a_lat ^ memp_rm_douta; + end + end + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDOMUXB_int) begin + DOUTBDOUT_out = CASDINB_in; + DOUTPBDOUTP_out = CASDINPB_in; + end + else if (sdp_mode_rd) begin + if (DOA_REG_BIN == DOA_REG_1) begin + DOUTBDOUT_out = mem_a_reg[31:16] ^ mem_rm_douta[31:16]; + DOUTPBDOUTP_out = memp_a_reg[3:2] ^ memp_rm_douta[3:2]; + end + else if (mem_wr_en_a_wf) begin + DOUTBDOUT_out = mem_rd_a_wf[31:16] ^ mem_rm_douta[31:16]; + DOUTPBDOUTP_out = memp_rd_a_wf[3:2] ^ memp_rm_douta[3:2]; + end + else begin + DOUTBDOUT_out = mem_a_lat[31:16] ^ mem_rm_douta[31:16]; + DOUTPBDOUTP_out = memp_a_lat[3:2] ^ memp_rm_douta[3:2]; + end + end + else begin + if (DOB_REG_BIN == DOB_REG_1) begin + DOUTBDOUT_out = mem_b_reg ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_b_reg ^ memp_rm_doutb; + end + else if (mem_wr_en_b_wf) begin + DOUTBDOUT_out = mem_rd_b_wf ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_rd_b_wf ^ memp_rm_doutb; + end + else begin + DOUTBDOUT_out = mem_b_lat ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_b_lat ^ memp_rm_doutb; + end + end + end + + assign INIT_A_int = + (READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{4{INIT_A_BIN[8]}}, {4{INIT_A_BIN[7:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{2{INIT_A_BIN[17:16]}}, {2{INIT_A_BIN[15:0]}}} : + {INIT_B_BIN[17:16],INIT_A_BIN[17:16],INIT_B_BIN[15:0],INIT_A_BIN[15:0]}; + + assign INIT_B_int = + (READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{2{INIT_B_BIN[8]}}, {2{INIT_B_BIN[7:0]}}} : + INIT_B_BIN; + + assign SRVAL_A_int = + (READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{4{SRVAL_A_BIN[8]}}, {4{SRVAL_A_BIN[7:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{2{SRVAL_A_BIN[17:16]}}, {2{SRVAL_A_BIN[15:0]}}} : + {SRVAL_B_BIN[17:16],SRVAL_A_BIN[17:16],SRVAL_B_BIN[15:0],SRVAL_A_BIN[15:0]}; + assign SRVAL_B_int = + (READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{2{SRVAL_B_BIN[8]}}, {2{SRVAL_B_BIN[7:0]}}} : + SRVAL_B_BIN; +// cascade out + assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + DOUTADOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}}; + assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ? + DOUTBDOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ? + DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}}; +// start model internals + +// cascade control + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) CASDOMUXA_reg <= 1'b0; + else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in; + end + + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) CASOREGIMUXA_reg <= 1'b0; + else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in; + end + + assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? + CASDOMUXA_reg : CASDOMUXB_reg; + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR || sdp_mode) CASDOMUXB_reg <= 1'b0; + else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in; + end + + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR || sdp_mode) CASOREGIMUXB_reg <= 1'b0; + else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in; + end + +// collison detection +reg coll_win_wr_clk_a_min = 1'b0; +reg coll_win_wr_clk_b_min = 1'b0; +reg coll_win_rd_clk_a_min = 1'b0; +reg coll_win_rd_clk_b_min = 1'b0; +reg coll_win_wr_clk_a_max = 1'b0; +reg coll_win_wr_clk_b_max = 1'b0; +reg coll_win_rd_clk_a_max = 1'b0; +reg coll_win_rd_clk_b_max = 1'b0; +reg wr_b_wr_a_coll = 1'b0; +reg wr_b_rd_a_coll = 1'b0; +reg rd_b_wr_a_coll = 1'b0; +reg wr_a_wr_b_coll = 1'b0; +reg wr_a_rd_b_coll = 1'b0; +reg rd_a_wr_b_coll = 1'b0; + +wire coll_wr_sim; +wire coll_wr_b_wr_a; +wire coll_wr_b_rd_a_sim; +wire coll_wr_b_rd_a; +//wire coll_rd_b_wr_a_sim; +wire coll_rd_b_wr_a; +wire coll_wr_a_wr_b; +wire coll_wr_a_rd_b_sim; +wire coll_wr_a_rd_b; +//wire coll_rd_a_wr_b_sim; +wire coll_rd_a_wr_b; + +assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min; +assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max; +assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min; +//assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min; +assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min; +//assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min; +assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max; +assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max; +assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max; +assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max; +assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max; + +always @(posedge CLKARDCLK_in) begin + if (mem_wr_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) & ~sdp_mode) begin + if (coll_win_wr_clk_a_max) begin + coll_win_wr_clk_a_max = 1'b0; + if (clks_done) clka_changed = 1'b1; + end else if (clks_done) begin + clka_changed = 1'b0; + coll_win_wr_clk_a_min <= #1 1'b1; + coll_win_wr_clk_a_max <= #99 1'b1; + coll_win_wr_clk_a_min <= #(t_coll_min) 1'b0; + coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0; + end + end +end + +always @(posedge coll_wr_sim) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-1] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b); + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-2] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_wr_b) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-3] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last); + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-4] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_rd_b_sim) begin + if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-5] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) and a READ on port B (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b); + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-6] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b); + else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_rd_b) begin + if (~wr_a_data_matches_rd_b_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-7] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last); + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-8] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKBWRCLK_in) begin + if (mem_wr_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if (coll_win_wr_clk_b_max) begin + coll_win_wr_clk_b_max = 1'b0; + if (clks_done) clkb_changed = 1'b1; + end else if (clks_done) begin + clkb_changed = 1'b0; + coll_win_wr_clk_b_min <= #1 1'b1; + coll_win_wr_clk_b_max <= #99 1'b1; + coll_win_wr_clk_b_min <= #(t_coll_min) 1'b0; + coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0; + end + end +end + + +always @(posedge coll_wr_b_wr_a) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-9] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last); + wr_b_wr_a_coll <= #10 1'b1; + wr_b_wr_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-10] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_wr_a_coll <= #10 1'b1; + wr_b_wr_a_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_b_rd_a_sim) begin + if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-11] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) and READ on port A (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a); + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-12] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a); + else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_b_rd_a) begin + if (~wr_b_data_matches_rd_a_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-13] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last); + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-14] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKARDCLK_in) begin + if (mem_rd_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if (coll_win_rd_clk_a_max) begin + coll_win_rd_clk_a_max = 1'b0; + if (clks_done) clka_changed = 1'b1; + end else if (clks_done) begin + clka_changed = 1'b0; + coll_win_rd_clk_a_min <= #1 1'b1; + coll_win_rd_clk_a_max <= #99 1'b1; + coll_win_rd_clk_a_min <= #(t_coll_min) 1'b0; + coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0; + end + end +end + +//always @(posedge coll_rd_a_wr_b_sim) begin +// if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin +// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin +// $display("Error: [Unisim %s-15] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b); +// rd_a_wr_b_coll <= #10 1'b1; +// rd_a_wr_b_coll <= #100 1'b0; +// end +// else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) +// $display("Error: [Unisim %s-16] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b); +// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin +// rd_a_wr_b_coll <= #10 1'b1; +// rd_a_wr_b_coll <= #100 1'b0; +// end +// end +//end + +always @(posedge coll_rd_a_wr_b) begin + if (~wr_b_data_matches_rd_a_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-17] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last); + rd_a_wr_b_coll <= #10 1'b1; + rd_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-18] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + rd_a_wr_b_coll <= #10 1'b1; + rd_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKBWRCLK_in) begin + if (mem_rd_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) && ~sdp_mode) begin + if (coll_win_rd_clk_b_max) begin + coll_win_rd_clk_b_max = 1'b0; + if (clks_done) clkb_changed = 1'b1; + end else if (clks_done) begin + clkb_changed = 1'b0; + coll_win_rd_clk_b_min <= #1 1'b1; + coll_win_rd_clk_b_max <= #99 1'b1; + coll_win_rd_clk_b_min <= #(t_coll_min) 1'b0; + coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0; + end + end +end + + +always @(posedge coll_rd_b_wr_a) begin + if (~wr_a_data_matches_rd_b_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-21] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last); + rd_b_wr_a_coll <= #10 1'b1; + rd_b_wr_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-22] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + rd_b_wr_a_coll <= #10 1'b1; + rd_b_wr_a_coll <= #100 1'b0; + end + end +end + +// output register + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) mem_a_reg_mux = {CASDINB_in, CASDINA_in}; + else if (mem_wr_en_a_wf) mem_a_reg_mux = mem_rd_a_wf; + else mem_a_reg_mux = mem_a_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) memp_a_reg_mux = {CASDINPB_in, CASDINPA_in}; + else if (mem_wr_en_a_wf) memp_a_reg_mux = memp_rd_a_wf; + else memp_a_reg_mux = memp_a_lat; + end + + always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_reg, mem_a_reg} <= #100 INIT_A_int; + end + else if (RSTREG_A_int) begin + {memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int; + end + else if (REGCE_A_int) begin + mem_a_reg <= #100 mem_a_reg_mux; + memp_a_reg <= #100 memp_a_reg_mux; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && + CASOREGIMUXB_reg) mem_b_reg_mux = CASDINB_in; + else if (mem_wr_en_b_wf) mem_b_reg_mux = mem_rd_b_wf; + else mem_b_reg_mux = mem_b_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && + CASOREGIMUXB_reg) memp_b_reg_mux = CASDINPB_in; + else if (mem_wr_en_b_wf) memp_b_reg_mux = memp_rd_b_wf; + else memp_b_reg_mux = memp_b_lat; + end + always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM || sdp_mode) begin + {memp_b_reg, mem_b_reg} <= #100 INIT_B_int; + end + else if (RSTREG_B_int) begin + {memp_b_reg, mem_b_reg} <= #100 SRVAL_B_int; + end + else if (REGCE_B_int) begin + mem_b_reg <= #100 mem_b_reg_mux; + memp_b_reg <= #100 memp_b_reg_mux; + end + end + +// read engine + always @ (posedge CLKARDCLK_in) begin + if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && ~sdp_mode && mem_rd_en_a && ~glblGSR) begin + mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a; + end + end + + always @ (posedge CLKBWRCLK_in) begin + if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b && ~glblGSR) begin + mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b; + end + end + + always @ (wr_a_wf_event or INIT_MEM) begin + if (coll_wr_sim || coll_wr_b_wr_a || coll_wr_a_wr_b) begin + for (raw=0;raw= 8) begin + for (raw=0;raw= 8) begin + for (raw=0;raw= 8) begin + for (raa=0;raa> ra; + if (ra> (D_WIDTH+ra); + end + end + end + else if (SLEEP_A_int && mem_rd_en_a) begin + $display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_a <= 1'b0; + for (ra=0;ra> ra; + if (ra> (D_WIDTH+ra); + end + end + end + end + else if (rd_a_wr_b_coll || wr_b_rd_a_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin + if (~wr_b_data_matches_rd_a_data && + ((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) || + (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin + mem_is_rst_a <= 1'b0; + for (ra=0;ra= 8) begin + for (rbw=0;rbw> rb; + if (rb> (D_WIDTH/2+rb); + end + end + end + else if (SLEEP_B_int && mem_rd_en_b && ~sdp_mode) begin + $display("Error: [Unisim %s-24] DRC : READ on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_b <= 1'b0; + for (rb=0;rb> rb; + if (rb> (D_WIDTH/2+rb); + end + end + end + end + else if (rd_b_wr_a_coll || wr_a_rd_b_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin + mem_is_rst_b <= 1'b0; + if (~wr_a_data_matches_rd_b_data && + ((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) || + (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin + for (rb=0;rb= 8) begin + for (wa=0;wa WRITE_WIDTH_B_4) begin + for (wb=0;wb>(max_rd_loops-rd_loops_a); + assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b); + assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a); + assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b); + + always @(*) begin + if (~sdp_mode && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_a_last & rd_addr_b_mask) == (rd_addr_b_last & wr_addr_a_mask)) wr_a_rd_b_addr_coll = 1'b1; + else wr_a_rd_b_addr_coll = 1'b0; + end + else wr_a_rd_b_addr_coll = 1'b0; + end + + always @(*) begin + if (~sdp_mode && mem_wr_en_b && mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_a_last & wr_addr_b_mask) == (wr_addr_b_last & wr_addr_a_mask)) wr_addr_coll = 1'b1; + else wr_addr_coll = 1'b0; + end + else wr_addr_coll = 1'b0; + end + + always @(*) begin + if (mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_b_last & rd_addr_a_mask) == (rd_addr_a_last & wr_addr_b_mask)) wr_b_rd_a_addr_coll = 1'b1; + else wr_b_rd_a_addr_coll = 1'b0; + end + else wr_b_rd_a_addr_coll = 1'b0; + end + + always @ (WEA_in or glblGSR) begin + mem_we_a = {{8{WEA_in[1]}},{8{WEA_in[0]}}}; + if (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) memp_we_a = WEA_in; + else memp_we_a = 2'b0; + end + always @ (WEBWE_in or glblGSR) begin + mem_we_b = {{8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}}; + if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) memp_we_b = WEBWE_in; + else memp_we_b = 4'b0; + end + +`ifdef XIL_TIMING + reg notifier; + wire clkardclk_en_n; + wire clkardclk_en_p; + wire clkbwrclk_en_n; + wire clkbwrclk_en_p; + assign clkardclk_en_n = IS_CLKARDCLK_INVERTED_BIN; + assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED_BIN; + assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED_BIN; + assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED_BIN; +`endif + + specify + (CASDINA *> CASDOUTA) = (0:0:0, 0:0:0); + (CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0); + (CASDINB *> CASDOUTB) = (0:0:0, 0:0:0); + (CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0); + (CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0); + (CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0); + (CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0); + (CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0); + (CLKARDCLK *> CASDOUTA) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTB) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTPA) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTPB) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTADOUT) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTBDOUT) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTPADOUTP) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100); + (CLKBWRCLK *> CASDOUTB) = (100:100:100, 100:100:100); + (CLKBWRCLK *> CASDOUTPB) = (100:100:100, 100:100:100); + (CLKBWRCLK *> DOUTBDOUT) = (100:100:100, 100:100:100); + (CLKBWRCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKARDCLK, 0:0:0, notifier); + $period (negedge CLKBWRCLK, 0:0:0, notifier); + $period (posedge CLKARDCLK, 0:0:0, notifier); + $period (posedge CLKBWRCLK, 0:0:0, notifier); + $setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay); + $setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay); + $setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay); + $setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay); + $setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay); + $setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay); + $setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay); + $setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay); + $setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay); + $setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay); + $setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay); + $setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay); + $setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay); + $width (negedge CLKARDCLK, 0:0:0, 0, notifier); + $width (negedge CLKBWRCLK, 0:0:0, 0, notifier); + $width (posedge CLKARDCLK, 0:0:0, 0, notifier); + $width (posedge CLKBWRCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMB36E1.v b/verilog/src/unisims/RAMB36E1.v new file mode 100644 index 0000000..c91f764 --- /dev/null +++ b/verilog/src/unisims/RAMB36E1.v @@ -0,0 +1,5364 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB36E1.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 02/26/08 - Initial version. +// 07/25/08 - Fixed ECC in register mode. (IR 477257) +// 07/30/08 - Updated to support SDP mode with smaller port width <= 36. (IR 477258) +// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964) +// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 11/20/08 - Changed RDADDRECC[12:0] to [8:0] (IR 496907). +// 03/11/09 - X's the unused bits of outputs (CR 511363). +// 03/12/09 - Removed parameter from specify block (CR 503821). +// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). +// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450). +// 04/17/09 - Implemented X's in sbiterr and dbiterr outputs during collision in ECC mode (CR 508071). +// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327). +// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010). +// 11/16/09 - Implemented DRC for ADDR[15] in non-cascade mode (CR 535882). +// 11/18/09 - Define tasks and functions before calling (CR 532610). +// 11/24/09 - Undo CR 535882, bitgen or map is going to tie off ADDR[15] instead. +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010). +// 04/01/10 - Fixed clocks detection for collision (CR 552123). +// 05/11/10 - Updated clocks detection for collision (CR 557624). +// - Added attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807). +// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// 07/08/10 - Added SIM_DEVICE attribute (CR 567633). +// 07/09/10 - Fixed INJECTSBITERR and INJECTDBITERR behaviors (CR 565234). +// 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672). +// 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507). +// 09/16/10 - Updated from bit to bus timing (CR 575523). +// 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924). +// 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953). +// 12/10/10 - Converted parameter to wire in specify block (CR 574534). +// 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053). +// 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004). +// 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942). +// 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942). +// 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129). +// 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844). +// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190). +// 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670). +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482). +// 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399). +// 02/23/12 - Fixed SDP mode when write width is 32 and read width is 64 (CR 647335). +// 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454). +// 03/15/12 - Reverted CR 584399 (CR 651279). +// 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934). +// 07/25/13 - Added invertible pins support (CR 715417). +// 09/04/13 - Removed warning for memp (CR 728988). +// 03/24/14 - Balanced all iniputs with xor (CR778933). +// 08/29/14 - Added negative timing check (CR 821138). +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/22/14 - Added #1 to $finish (CR 808642). +// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966). +// End Revision + +`timescale 1 ps / 1 ps +`celldefine + +module RAMB36E1 (CASCADEOUTA, CASCADEOUTB, DBITERR, DOADO, DOBDO, DOPADOP, DOPBDOP, ECCPARITY, RDADDRECC, SBITERR, + ADDRARDADDR, ADDRBWRADDR, CASCADEINA, CASCADEINB, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + +`ifdef XIL_TIMING + parameter LOC = "UNPLACED"; +`endif + + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "7SERIES"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output CASCADEOUTA; + output CASCADEOUTB; + output DBITERR; + output [31:0] DOADO; + output [31:0] DOBDO; + output [3:0] DOPADOP; + output [3:0] DOPBDOP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR; + + input CLKARDCLK; + input CLKBWRCLK; + input ENARDEN; + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + input RSTRAMARSTRAM; + input RSTRAMB; + input RSTREGARSTREG; + input RSTREGB; + input CASCADEINA; + input CASCADEINB; + input INJECTDBITERR; + input INJECTSBITERR; + input [15:0] ADDRARDADDR; + input [15:0] ADDRBWRADDR; + input [31:0] DIADI; + input [31:0] DIBDI; + input [3:0] DIPADIP; + input [3:0] DIPBDIP; + input [3:0] WEA; + input [7:0] WEBWE; + + tri0 GSR = glbl.GSR; + + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + wire [31:0] doado_wire, dobdo_wire; + wire [3:0] dopadop_wire, dopbdop_wire; + wire cascadeouta_wire, cascadeoutb_wire; + reg [31:0] doado_out, dobdo_out; + reg [3:0] dopadop_out, dopbdop_out; + reg cascadeouta_out, cascadeoutb_out; + reg notifier, notifier_a, notifier_b; + reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4; + reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9; + reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13, notifier_addra14; + reg notifier_addra15; + reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4; + reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9; + reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13, notifier_addrb14; + reg notifier_addrb15; + reg attr_err = 1'b0; + + wire cascadeina_in, regcearegce_in; + wire cascadeinb_in, regceb_in; + wire injectdbiterr_in, injectsbiterr_in; + wire [15:0] addrardaddr_in; + wire [15:0] addrbwraddr_in; + wire [31:0] diadi_in; + wire [31:0] dibdi_in; + wire [3:0] dipadip_in; + wire [3:0] dipbdip_in; + wire [3:0] wea_in; + wire [7:0] webwe_in; + + wire clkardclk_in; + wire clkbwrclk_in; + wire enarden_in; + wire enbwren_in; + wire rstramarstram_in; + wire rstramb_in; + wire rstregarstreg_in; + wire rstregb_in; + +`ifdef XIL_TIMING + wire CLKARDCLK_delay; + wire CLKBWRCLK_delay; + wire ENARDEN_delay; + wire ENBWREN_delay; + wire INJECTDBITERR_delay; + wire INJECTSBITERR_delay; + wire REGCEAREGCE_delay; + wire REGCEB_delay; + wire RSTRAMARSTRAM_delay; + wire RSTRAMB_delay; + wire RSTREGARSTREG_delay; + wire RSTREGB_delay; + wire [15:0] ADDRARDADDR_delay; + wire [15:0] ADDRBWRADDR_delay; + wire [31:0] DIADI_delay; + wire [31:0] DIBDI_delay; + wire [3:0] DIPADIP_delay; + wire [3:0] DIPBDIP_delay; + wire [3:0] WEA_delay; + wire [7:0] WEBWE_delay; +`endif + +`ifdef XIL_TIMING + assign cascadeina_in = CASCADEINA; + assign cascadeinb_in = CASCADEINB; + assign regcearegce_in = REGCEAREGCE_delay; + assign regceb_in = REGCEB_delay; + assign injectdbiterr_in = INJECTDBITERR_delay; + assign injectsbiterr_in = INJECTSBITERR_delay; + assign addrardaddr_in = ADDRARDADDR_delay; + assign addrbwraddr_in = ADDRBWRADDR_delay; + assign diadi_in = DIADI_delay; + assign dibdi_in = DIBDI_delay; + assign dipadip_in = DIPADIP_delay; + assign dipbdip_in = DIPBDIP_delay; + assign wea_in = WEA_delay; + assign webwe_in = WEBWE_delay; + assign clkardclk_in = CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED; + assign clkbwrclk_in = CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED; + assign enarden_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED; + assign enbwren_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED; + assign rstramarstram_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED; + assign rstramb_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED; + assign rstregarstreg_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED; + assign rstregb_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED; +`else + assign cascadeina_in = CASCADEINA; + assign cascadeinb_in = CASCADEINB; + assign regcearegce_in = REGCEAREGCE; + assign regceb_in = REGCEB; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign addrardaddr_in = ADDRARDADDR; + assign addrbwraddr_in = ADDRBWRADDR; + assign diadi_in = DIADI; + assign dibdi_in = DIBDI; + assign dipadip_in = DIPADIP; + assign dipbdip_in = DIPBDIP; + assign wea_in = WEA; + assign webwe_in = WEBWE; + assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED; + assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED; + assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED; + assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED; + assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED; + assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED; + assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED; + assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED; +`endif + + initial begin + + + if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end // initial begin + + + + // special handle for sdp width = 72 and < 72 + localparam [71:0] init_sdp = (READ_WIDTH_A == 72) ? {INIT_B[35:32],INIT_A[35:32],INIT_B[31:0],INIT_A[31:0]} : {INIT_B, INIT_A}; + localparam [71:0] srval_sdp = (READ_WIDTH_A == 72) ? {SRVAL_B[35:32],SRVAL_A[35:32],SRVAL_B[31:0],SRVAL_A[31:0]} : {SRVAL_B, SRVAL_A}; + + + generate + case (RAM_MODE) + + "TDP" : begin : gen_tdp + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(INIT_A), + .INIT_B(INIT_B), + .INIT_FILE(INIT_FILE), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_TDP (.ADDRA(addrardaddr_in), + .ADDRB(addrbwraddr_in), + .CASCADEINA(cascadeina_in), + .CASCADEINB(cascadeinb_in), + .CASCADEOUTA(cascadeouta_wire), + .CASCADEOUTB(cascadeoutb_wire), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(DBITERR), + .DIA({32'b0,diadi_in}), + .DIB({32'b0,dibdi_in}), + .DIPA(dipadip_in), + .DIPB({4'b0,dipbdip_in}), + .DOA({dangle_out32,doado_wire}), + .DOB(dobdo_wire), + .DOPA({dangle_out4,dopadop_wire}), + .DOPB(dopbdop_wire), + .ECCPARITY(ECCPARITY), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(RDADDRECC), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(SBITERR), + .WEA({2{wea_in}}), + .WEB(webwe_in)); + + end // case: "TDP" + "SDP" : begin : gen_sdp + + if (WRITE_WIDTH_B == 72) begin : gen_wide + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(init_sdp), + .INIT_B(init_sdp), + .INIT_FILE(INIT_FILE), + .SRVAL_A(srval_sdp), + .SRVAL_B(srval_sdp), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_A), + .WRITE_WIDTH_A(WRITE_WIDTH_B), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_SDP (.ADDRA(addrardaddr_in), + .ADDRB(addrbwraddr_in), + .CASCADEINA(cascadeina_in), + .CASCADEINB(cascadeinb_in), + .CASCADEOUTA(cascadeouta_wire), + .CASCADEOUTB(cascadeoutb_wire), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(DBITERR), + .DIA(64'b0), + .DIB({dibdi_in,diadi_in}), + .DIPA(4'b0), + .DIPB({dipbdip_in,dipadip_in}), + .DOA({dobdo_wire,doado_wire}), + .DOB(dangle_out32), + .DOPA({dopbdop_wire,dopadop_wire}), + .DOPB(dangle_out4), + .ECCPARITY(ECCPARITY), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(injectdbiterr_in), + .INJECTSBITERR(injectsbiterr_in), + .RDADDRECC(RDADDRECC), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(SBITERR), + .WEA(8'b0), + .WEB(webwe_in)); + + end // if (WRITE_WIDTH_B == 72) + else begin : gen_narrow + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(init_sdp), + .INIT_B(init_sdp), + .INIT_FILE(INIT_FILE), + .SRVAL_A(srval_sdp), + .SRVAL_B(srval_sdp), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_A), + .WRITE_WIDTH_A(WRITE_WIDTH_B), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .SIM_DEVICE(SIM_DEVICE), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_SDP (.ADDRA(addrardaddr_in), + .ADDRB(addrbwraddr_in), + .CASCADEINA(cascadeina_in), + .CASCADEINB(cascadeinb_in), + .CASCADEOUTA(cascadeouta_wire), + .CASCADEOUTB(cascadeoutb_wire), + .CLKA(clkardclk_in), + .CLKB(clkbwrclk_in), + .DBITERR(DBITERR), + .DIA(64'b0), + .DIB({32'b0,dibdi_in}), + .DIPA(4'b0), + .DIPB({4'b0,dipbdip_in}), + .DOA({dobdo_wire,doado_wire}), + .DOB(dangle_out32), + .DOPA({dopbdop_wire,dopadop_wire}), + .DOPB(dangle_out4), + .ECCPARITY(ECCPARITY), + .ENA(enarden_in), + .ENB(enbwren_in), + .GSR(GSR), + .INJECTDBITERR(injectdbiterr_in), + .INJECTSBITERR(injectsbiterr_in), + .RDADDRECC(RDADDRECC), + .REGCEA(regcearegce_in), + .REGCEB(regceb_in), + .RSTRAMA(rstramarstram_in), + .RSTRAMB(rstramb_in), + .RSTREGA(rstregarstreg_in), + .RSTREGB(rstregb_in), + .SBITERR(SBITERR), + .WEA(8'b0), + .WEB(webwe_in)); + + end // else: !if(WRITE_WIDTH_B == 72) + + end // case: "SDP" + + endcase // case(RAM_MODE) + endgenerate + + +//*** Timing Checks Start here + + reg CASCADEOUTA_out; + reg CASCADEOUTB_out; + reg [31:0] DOADO_out; + reg [31:0] DOBDO_out; + reg [3:0] DOPADOP_out; + reg [3:0] DOPBDOP_out; + + assign CASCADEOUTA = CASCADEOUTA_out; + assign CASCADEOUTB = CASCADEOUTB_out; + assign DOADO = DOADO_out; + assign DOBDO = DOBDO_out; + assign DOPADOP = DOPADOP_out; + assign DOPBDOP = DOPBDOP_out; + + always @(doado_wire or rstramb_in or GSR) DOADO_out = doado_wire; + always @(dobdo_wire or rstramb_in or GSR) DOBDO_out = dobdo_wire; + always @(dopadop_wire or rstramb_in or GSR) DOPADOP_out = dopadop_wire; + always @(dopbdop_wire or rstramb_in or GSR) DOPBDOP_out = dopbdop_wire; + always @(cascadeouta_wire or rstramb_in or GSR) CASCADEOUTA_out = cascadeouta_wire; + always @(cascadeoutb_wire or rstramb_in or GSR) CASCADEOUTB_out = cascadeoutb_wire; + +`ifdef XIL_TIMING + + wire clkardclk_en_n; + wire clkardclk_en_p; + wire clkbwrclk_en_n; + wire clkbwrclk_en_p; + assign clkardclk_en_n = IS_CLKARDCLK_INVERTED; + assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED; + assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED; + assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED; + + wire enarden_clka_n = enarden_in && clkardclk_en_n; + wire enarden_clka_p = enarden_in && clkardclk_en_p; + wire enbwren_clkb_n = enbwren_in && clkbwrclk_en_n; + wire enbwren_clkb_p = enbwren_in && clkbwrclk_en_p; + + wire diadi0_enable_n = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_n; + wire diadi0_enable_p = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_p; + + wire dibdi0_enable_n = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_n) : (enbwren_in && webwe_in[4] && clkbwrclk_en_n) ; + wire dibdi0_enable_p = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_p) : (enbwren_in && webwe_in[4] && clkbwrclk_en_p) ; + + wire sdp_dia0_clkwr_n = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_n; + wire sdp_dia0_clkwr_p = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_p; + + always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or notifier_addra11 or notifier_addra12 or notifier_addra13 or notifier_addra14 or notifier_addra15) begin + doado_out <= 32'hxxxxxxxx; + dopadop_out <= 4'hx; + cascadeouta_out <= 1'bx; + end + + always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or notifier_addrb11 or notifier_addrb12 or notifier_addrb13 or notifier_addrb14 or notifier_addrb15) begin + dobdo_out <= 32'hxxxxxxxx; + dopbdop_out <= 4'hx; + cascadeoutb_out <= 1'bx; + + if (RAM_MODE == "SDP") begin + doado_out <= 32'hxxxxxxxx; + dopadop_out <= 4'hx; + cascadeouta_out <= 1'bx; + end + + end + + + always @(notifier_addra0) begin + task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK"); + end + + always @(notifier_addra1) begin + task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK"); + end + + always @(notifier_addra2) begin + task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK"); + end + + always @(notifier_addra3) begin + task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK"); + end + + always @(notifier_addra4) begin + task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK"); + end + + always @(notifier_addra5) begin + task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK"); + end + + always @(notifier_addra6) begin + task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK"); + end + + always @(notifier_addra7) begin + task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK"); + end + + always @(notifier_addra8) begin + task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK"); + end + + always @(notifier_addra9) begin + task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK"); + end + + always @(notifier_addra10) begin + task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK"); + end + + always @(notifier_addra11) begin + task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK"); + end + + always @(notifier_addra12) begin + task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK"); + end + + always @(notifier_addra13) begin + task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK"); + end + + always @(notifier_addra14) begin + task_warn_msg ("ADDRARDADDR[14]", "CLKARDCLK"); + end + + always @(notifier_addra15) begin + task_warn_msg ("ADDRARDADDR[15]", "CLKARDCLK"); + end + + + always @(notifier_addrb0) begin + task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK"); + end + + always @(notifier_addrb1) begin + task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK"); + end + + always @(notifier_addrb2) begin + task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK"); + end + + always @(notifier_addrb3) begin + task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK"); + end + + always @(notifier_addrb4) begin + task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK"); + end + + always @(notifier_addrb5) begin + task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK"); + end + + always @(notifier_addrb6) begin + task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK"); + end + + always @(notifier_addrb7) begin + task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK"); + end + + always @(notifier_addrb8) begin + task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK"); + end + + always @(notifier_addrb9) begin + task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK"); + end + + always @(notifier_addrb10) begin + task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK"); + end + + always @(notifier_addrb11) begin + task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK"); + end + + always @(notifier_addrb12) begin + task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK"); + end + + always @(notifier_addrb13) begin + task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK"); + end + + always @(notifier_addrb14) begin + task_warn_msg ("ADDRBWRADDR[14]", "CLKBWRCLK"); + end + + always @(notifier_addrb15) begin + task_warn_msg ("ADDRBWRADDR[15]", "CLKBWRCLK"); + end + + + task task_warn_msg; + + input [8*15:1] addr_str; + input [8*9:1] clk_str; + + begin + + $display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str); + + end + + endtask // task_warn_msg + +`endif // `ifdef XIL_TIMING + + + wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0; + +`ifdef XIL_TIMING + wire ram_extension_a_wire = (RAM_EXTENSION_A == "UPPER") ? 1 : 0; + wire ram_extension_b_wire = (RAM_EXTENSION_B == "UPPER") ? 1 : 0; +`endif // `ifdef XIL_TIMING + + specify + + (CASCADEINA *> DOADO) = (0:0:0, 0:0:0); + (CASCADEINB *> DOBDO) = (0:0:0, 0:0:0); + (CLKARDCLK *> DOADO) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100); + (CLKARDCLK *> RDADDRECC) = (100:100:100, 100:100:100); + (CLKARDCLK => DBITERR) = (100:100:100, 100:100:100); + (CLKARDCLK => SBITERR) = (100:100:100, 100:100:100); + (CLKARDCLK => CASCADEOUTA) = (100:100:100, 100:100:100); + + if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100); + if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100); + + if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100); + if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100); + (CLKBWRCLK *> ECCPARITY) = (100:100:100, 100:100:100); + (CLKBWRCLK => CASCADEOUTB) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + if (ram_extension_a_wire == 1) (CASCADEINA => DOADO[0]) = (0:0:0, 0:0:0); + if (ram_extension_b_wire == 1) (CASCADEINB => DOBDO[0]) = (0:0:0, 0:0:0); + + $setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); + $setuphold (posedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); + $setuphold (posedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); + + $setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); + $setuphold (posedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); + $setuphold (posedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (posedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (posedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (posedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (posedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); + + $setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); + $setuphold (negedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); + $setuphold (negedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); + + $setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); + $setuphold (negedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); + $setuphold (negedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); + $setuphold (negedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (negedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); + $setuphold (negedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (negedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); + $setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); + + $period (negedge CLKARDCLK, 0:0:0, notifier_a); + $period (negedge CLKBWRCLK, 0:0:0, notifier_b); + $period (posedge CLKARDCLK, 0:0:0, notifier_a); + $period (posedge CLKBWRCLK, 0:0:0, notifier_b); + $width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); + $width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); + $width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); + $width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); + +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB36E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. RAMB36E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module RB36_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR, + ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB); + + output CASCADEOUTA; + output CASCADEOUTB; + output DBITERR; + output SBITERR; + output [8:0] RDADDRECC; + output reg [63:0] DOA; + output reg [31:0] DOB; + output reg [7:0] DOPA; + output reg [3:0] DOPB; + output [7:0] ECCPARITY; + + input ENA, CLKA, CASCADEINA, REGCEA; + input ENB, CLKB, CASCADEINB, REGCEB; + input GSR; + input RSTRAMA, RSTRAMB; + input RSTREGA, RSTREGB; + input INJECTDBITERR, INJECTSBITERR; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [63:0] DIA; + input [63:0] DIB; + input [3:0] DIPA; + input [7:0] DIPB; + input [7:0] WEA; + input [7:0] WEB; + + parameter DOA_REG = 0; + parameter DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [71:0] INIT_A = 72'h0; + parameter [71:0] INIT_B = 72'h0; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "7SERIES"; + parameter [71:0] SRVAL_A = 72'h0; + parameter [71:0] SRVAL_B = 72'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter INIT_FILE = "NONE"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameters are changed. + parameter BRAM_SIZE = 36; +// xilinx_internal_parameter off + + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset; + integer viol_time = 0; + integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int; + integer ram_mode_int, en_ecc_write_int, en_ecc_read_int; + integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0; + + reg addra_in_15_reg_bram, addrb_in_15_reg_bram; + reg addra_in_15_reg, addrb_in_15_reg; + reg addra_in_15_reg1, addrb_in_15_reg1; + reg junk1; + reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; + reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0; + reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0; + reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0; + reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0; + reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; + reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; + reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; + reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; + + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, syndrome = 8'b0; + reg [7:0] dipb_in_ecc; + reg [71:0] ecc_bit_position; + reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; + reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx; + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_outreg = 0, sbiterr_outreg = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + + reg [7:0] wea_reg; + reg enb_reg; + reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg; + reg outp_a = 1'b0, outp_b = 1'b0, junkp; + reg rising_clka = 1'b0, rising_clkb = 1'b0; + reg [15:0] addra_reg, addrb_reg; + + reg [63:0] dia_reg, dib_reg; + reg [3:0] dipa_reg; + reg [7:0] dipb_reg; + reg [1:0] viol_type = 2'b00; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0; + reg [8:0] rdaddrecc_out_out = 9'b0; + reg finish_error = 0; + + time time_port_a, time_port_b; + + wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in; + wire [7:0] wea_in; + wire [7:0] web_in; + wire cascadeina_in, cascadeinb_in; + wire injectdbiterr_in, injectsbiterr_in; + wire rstrega_in, rstregb_in; + reg [15:0] ox_addra_reconstruct, ox_addrb_reconstruct; + reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg; + + wire temp_wire; // trigger NCsim at initial time + assign temp_wire = 1; + + time time_clka_period, time_clkb_period, time_period; + reg time_skew_a_flag = 0; + reg time_skew_b_flag = 0; + + assign CASCADEOUTA = DOA[0]; + assign CASCADEOUTB = DOB[0]; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDADDRECC = rdaddrecc_out_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign rstrega_in = RSTREGA; + assign rstregb_in = RSTREGB; + + + localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100; + + + // Determine memory size + localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && + WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : + (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && + WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : + (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && + READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : + (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && + READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 72; + + localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : + (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : + (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : + (WRITE_WIDTH_A == 72) ? 64 : 64; + + localparam wa_width_0 = 0; + + localparam wa_width_1 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : + (WRITE_WIDTH_A == 72) ? 8 : 0; + + localparam wa_width_2 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 16 : + (WRITE_WIDTH_A == 72) ? 16 : 0; + + localparam wa_width_3 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 24 : + (WRITE_WIDTH_A == 72) ? 24 : 0; + + localparam wa_width_4 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 32 : 0; + + localparam wa_width_5 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 40 : 0; + + localparam wa_width_6 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 48 : 0; + + localparam wa_width_7 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : + (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : + (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : + (WRITE_WIDTH_A == 72) ? 56 : 0; + + localparam wa_width_n = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : + (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : + (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : + (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : + (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : + (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : + (WRITE_WIDTH_B == 72) ? 64 : 64; + + localparam wb_width_0 = 0; + + localparam wb_width_1 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : + (WRITE_WIDTH_B == 72) ? 8 : 0; + + localparam wb_width_2 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 16 : + (WRITE_WIDTH_B == 72) ? 16 : 0; + + localparam wb_width_3 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 24 : + (WRITE_WIDTH_B == 72) ? 24 : 0; + + localparam wb_width_4 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 32 : 0; + + localparam wb_width_5 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 40 : 0; + + localparam wb_width_6 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 48 : 0; + + localparam wb_width_7 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : + (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : + (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : + (WRITE_WIDTH_B == 72) ? 56 : 0; + + localparam wb_width_n = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : + (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : + (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : + (WRITE_WIDTH_B == 72) ? 8 : 8; + + + localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : + (WRITE_WIDTH_A == 36) ? 4 : (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : + (WRITE_WIDTH_B == 36) ? 4 : (WRITE_WIDTH_B == 72) ? 8 : 8; + + localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : + (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : + (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : + (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : + (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 64 : 64) : 64; + + localparam ra_width_n = (ra_width == 1) ? 1 : (ra_width == 2) ? 2 : + (ra_width == 4) ? 4 : (ra_width == 8) ? 8 : + (ra_width == 16) ? 8 : (ra_width == 32) ? 8 : + (ra_width == 64) ? 8 : 8; + + localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : + (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : + (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 32 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : + (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : + (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 32 : 32) : 32; + + localparam rb_width_0 = 0; + + localparam rb_width_1 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : + (rb_width == 64) ? 8 : 8; + + localparam rb_width_2 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 16 : + (rb_width == 64) ? 16 : 16; + + localparam rb_width_3 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 24 : + (rb_width == 64) ? 24 : 24; + + localparam rb_width_4 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 32 : 32; + + localparam rb_width_5 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 40 : 40; + + localparam rb_width_6 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 48 : 48; + + localparam rb_width_7 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : + (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : + (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : + (rb_width == 64) ? 56 : 56; + + localparam rb_width_n = (rb_width == 1) ? 1 : (rb_width == 2) ? 2 : + (rb_width == 4) ? 4 : (rb_width == 8) ? 8 : + (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : + (rb_width == 64) ? 8 : 8; + + localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : + (READ_WIDTH_A == 36) ? 4 : (READ_WIDTH_A == 72) ? 8 : 1; + + localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : + (READ_WIDTH_B == 36) ? 4 : (READ_WIDTH_B == 72) ? 4 : 1; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : + (widest_width == 72) ? 6 : 0; + + always @(*) begin + if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin + if (BRAM_SIZE == 36) ox_addra_reconstruct[15:0] = {1'b0,ADDRA[14:8],8'b0}; + else if (BRAM_SIZE == 18) ox_addra_reconstruct[15:0] = {2'b0,ADDRA[13:7],7'b0}; + else ox_addra_reconstruct[15:0] = ADDRA; + end else ox_addra_reconstruct[15:0] = ADDRA; + end + + always @(*) begin + if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin + if (BRAM_SIZE == 36) ox_addrb_reconstruct[15:0] = {1'b0,ADDRB[14:8],8'b0}; + else if (BRAM_SIZE == 18) ox_addrb_reconstruct[15:0] = {2'b0,ADDRB[13:7],7'b0}; + else ox_addrb_reconstruct[15:0] = ADDRB; + end else ox_addrb_reconstruct[15:0] = ADDRB; + end + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : + (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : + (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : + (widest_width == 72) ? 64 : 64; + + localparam width_0 = 0; + + localparam width_1 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : + (widest_width == 72) ? 8 : 0; + + localparam width_2 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 16 : + (widest_width == 72) ? 16 : 0; + + localparam width_3 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 24 : + (widest_width == 72) ? 24 : 0; + + localparam width_4 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 32 : 0; + + localparam width_5 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 40 : 0; + + localparam width_6 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 48 : 0; + + localparam width_7 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : + (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : + (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : + (widest_width == 72) ? 56 : 0; + + localparam width_n = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : + (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : + (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : + (widest_width == 72) ? 8 : 8; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : + (widest_width == 36) ? 4 : + (widest_width == 72) ? 8 : 1; + + + localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : 10) : 10; + + localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : 10) : 10; + + localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : + (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : + (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : + (WRITE_WIDTH_A == 72) ? 6 : 10; + + localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : + (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : + (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : + (WRITE_WIDTH_B == 72) ? 6 : 10; + + localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? + ((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10; + + localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? + ((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10; + + localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10; + + localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10; + + localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10; + + localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; + localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; + localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; + localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; + localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; + localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; + localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; + + localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : + (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 32768; + + localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 4096; + + reg [width+widthp-1:0] tmp_mem [0 : mem_depth-1]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer index = 0; + + +/******************************************** task and function **************************************/ + + task task_ram; + + input ram_we; + input [7:0] ram_di; + input ram_dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (ram_we == 1'b1) begin + + mem_task = ram_di; + + if (width >= 8) + memp_task = ram_dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input ram_col_we_o; + input ram_col_we; + input [7:0] ram_col_di; + input ram_col_dip; + inout [7:0] ram_col_mem_task; + inout ram_col_memp_task; + integer ram_col_i; + + begin + + if (ram_col_we == 1'b1) begin + + for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1) + if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)) + ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i]; + + if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))) + ram_col_memp_task = ram_col_dip; + + end + end + + endtask // task_ram_col + + + task task_ram_ox; + + input ram_ox_we_o; + input ram_ox_we; + input [7:0] ram_ox_di; + input ram_ox_dip; + inout [7:0] ram_ox_mem_task; + inout ram_ox_memp_task; + integer ram_ox_i; + + begin + + if (ram_ox_we == 1'b1) begin + + for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1) + ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i]; + + if (width >= 8) + ram_ox_memp_task = ram_ox_dip; + + end + end + + endtask // task_ram_ox + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] x_buf_do_tmp; + input [7:0] dop_ltmp; + inout [7:0] x_buf_dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + x_buf_do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + x_buf_dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + +task task_col_wr_ram_a; + input [1:0] col_wr_ram_a_seq; + input [7:0] col_wr_ram_a_web_tmp; + input [7:0] col_wr_ram_a_wea_tmp; + input [63:0] col_wr_ram_a_dia_tmp; + input [7:0] col_wr_ram_a_dipa_tmp; + input [15:0] col_wr_ram_a_addrb_tmp; + input [15:0] col_wr_ram_a_addra_tmp; + begin + case (wa_width) + 1, 2, 4 : begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 16 + 32 : if (width >= 32) begin + if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + else if (wa_width < width) begin + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + end + + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + else if (wa_width < width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 32 + 64 : if (width >= 64) begin + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][width_4 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][width_5 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][width_6 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][width_7 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + else + task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + if (col_wr_ram_a_seq == 2'b00) + chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); + + end // case: 64 + endcase // case(wa_width) + end +endtask // task_col_wr_ram_a + + +task task_ox_wr_ram_a; + input [1:0] ox_wr_ram_a_seq; + input [7:0] ox_wr_ram_a_web_tmp; + input [7:0] ox_wr_ram_a_wea_tmp; + input [63:0] ox_wr_ram_a_dia_tmp; + input [7:0] ox_wr_ram_a_dipa_tmp; + input [15:0] ox_wr_ram_a_addrb_tmp; + input [15:0] ox_wr_ram_a_addra_tmp; + + begin + case (wa_width) + 1, 2, 4 : begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + if (wa_width >= width) + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + wa_width_1) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 16 + 32 : if ( width >= 32) begin + if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // if (wa_width <= wb_width) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + + task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); + if (ox_wr_ram_a_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); + end // case: 64 + endcase // case(wa_width) + end +endtask // task_ox_wr_ram_a + + +task task_col_wr_ram_b; + input [1:0] col_wr_ram_b_seq; + input [7:0] col_wr_ram_b_wea_tmp; + input [7:0] col_wr_ram_b_web_tmp; + input [63:0] col_wr_ram_b_dib_tmp; + input [7:0] col_wr_ram_b_dipb_tmp; + input [15:0] col_wr_ram_b_addra_tmp; + input [15:0] col_wr_ram_b_addrb_tmp; + + begin + case (wb_width) + + 1, 2, 4 : begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_n) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) + end // case: 16 + 32 : if (width >= 32) begin + if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + else + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + + task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + if (col_wr_ram_b_seq == 2'b00) + chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_col_wr_ram_b + + +task task_ox_wr_ram_b; + input [1:0] ox_wr_ram_b_seq; + input [7:0] ox_wr_ram_b_wea_tmp; + input [7:0] ox_wr_ram_b_web_tmp; + input [63:0] ox_wr_ram_b_dib_tmp; + input [7:0] ox_wr_ram_b_dipb_tmp; + input [15:0] ox_wr_ram_b_addra_tmp; + input [15:0] ox_wr_ram_b_addrb_tmp; + + begin + case (wb_width) + 1, 2, 4 : begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // if (wb_width <= wa_width) + end // case: 8 + 16 : if (width >= 16) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) + end // case: 16 + 32 : if (width >= 32) begin + if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + if (wb_width >= width) + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + else + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) + end // case: 32 + 64 : if (width >= 64) begin + task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + + task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + if (ox_wr_ram_b_seq == 2'b00) + chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_ox_wr_ram_b + + +task task_wr_ram_a; + input [7:0] wr_ram_a_wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] wr_ram_a_addra_tmp; + begin + case (wa_width) + 1, 2, 4 : begin + if (wa_width >= width) + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width_n], junk1); + end + 8 : if (width >= 8) begin + if (wa_width >= width) + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]); + else + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); + end + 16 : if (width >= 16) begin + if (wa_width >= width) begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); + end else begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + end // case: 16 + 32 : if (width >= 32) begin + task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]); + task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); + task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); + task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); + end // case: 32 + endcase // case(wa_width) + end +endtask // task_wr_ram_a + + +task task_wr_ram_b; + input [7:0] wr_ram_b_web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] wr_ram_b_addrb_tmp; + begin + case (wb_width) + 1, 2, 4 : begin + if (wb_width >= width) + task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); + end + 8 : if (width >= 8) begin + if (wb_width >= width) + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]); + else + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + end + 16 : if (width >= 16) begin + if (wb_width >= width) begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); + end else begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + end // case: 16 + 32 : if (width >= 32) begin + if (wb_width >= width) begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); + end else begin + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + end // else: !if(wb_width >= width) + end // case: 32 + 64 : if (width >= 64) begin // only valid with ECC single bit correction for 64 bits + task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]); + task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); + task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); + task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); + task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); + task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); + task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); + task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); + end // case: 64 + endcase // case(wb_width) + end +endtask // task_wr_ram_b + + +task task_col_rd_ram_a; + input [1:0] col_rd_ram_a_seq; // 1 is bypass + input [7:0] col_rd_ram_a_web_tmp; + input [7:0] col_rd_ram_a_wea_tmp; + input [15:0] col_rd_ram_a_addra_tmp; + inout [63:0] col_rd_ram_a_doa_tmp; + inout [7:0] col_rd_ram_a_dopa_tmp; + reg [63:0] doa_ltmp; + reg [7:0] dopa_ltmp; + + begin + doa_ltmp= 64'b0; + dopa_ltmp= 8'b0; + case (ra_width) + 1, 2, 4 : begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; + else + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]]; + dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]]; + end else begin + doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width_n]; + dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end // case: 8 + 16 : if (width >= 16) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1]; + end else begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1]; + end else begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) + ra_width_n) +: ra_width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end + 32 : if (width >= 32) begin + if (ra_width >= width) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][width_2 +: width_n]; + dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][width_3 +: width_n]; + dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + end // if (ra_width >= width) + end + 64 : if (width >= 64) begin + if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][width_0 +: width_n]; + dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][width_1 +: width_n]; + dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][width_2 +: width_n]; + dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][width_3 +: width_n]; + dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin + doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][width_4 +: width_n]; + dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1]; + task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin + doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][width_5 +: width_n]; + dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1]; + task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin + doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][width_6 +: width_n]; + dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1]; + task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + + if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin + doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][width_7 +: width_n]; + dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1]; + task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); + end + end + endcase // case(ra_width) + end +endtask // task_col_rd_ram_a + + +task task_col_rd_ram_b; + input [1:0] col_rd_ram_b_seq; // 1 is bypass + input [7:0] col_rd_ram_b_wea_tmp; + input [7:0] col_rd_ram_b_web_tmp; + input [15:0] col_rd_ram_b_addrb_tmp; + inout [63:0] col_rd_ram_b_dob_tmp; + inout [7:0] col_rd_ram_b_dopb_tmp; + reg [63:0] col_rd_ram_b_dob_ltmp; + reg [7:0] col_rd_ram_b_dopb_ltmp; + + begin + col_rd_ram_b_dob_ltmp= 64'b0; + col_rd_ram_b_dopb_ltmp= 8'b0; + + case (rb_width) + 1, 2, 4 : begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; + else + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width_n]; + + task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end // case: 1, 2, 4 + 8 : if (width >= 8) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]]; + col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]]; + end else begin + col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + + end + end // case: 8 + 16 : if (width >= 16) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) + rb_width_n) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end + 32 : if (width >= 32) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_1) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_2 +: width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_2) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1]; + end + task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin + if (rb_width >= width) begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_3 +: width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1]; + end else begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_3) +: rb_width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1]; + end + task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + end + 64 : if (width >= 64) begin + if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_0 +: width_n]; + col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1]; + task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_1 +: width_n]; + col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1]; + task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_2 +: width_n]; + col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1]; + task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_3 +: width_n]; + col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1]; + task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_4 +: width_n]; + col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1]; + task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_5 +: width_n]; + col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1]; + task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_6 +: width_n]; + col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1]; + task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin + col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_7 +: width_n]; + col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1]; + task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); + end + + end + endcase // case(rb_width) + end +endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] rd_ram_a_addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:3]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_widthp) +: ra_widthp]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:4]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_widthp) +: ra_widthp]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:5]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]]; + end + else begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_width) +: ra_width]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_widthp) +: ra_widthp]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[rd_ram_a_addra_tmp[14:6]]; + dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] rd_ram_b_addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]]; + end + 64 : begin + if (rb_width >= width) begin + dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]]; + dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]]; + end + end + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input wea_tmp; + input web_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") + + if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + + end + else + $display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + col_wr_wr_msg = 0; + + end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) + else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp); + + end + else begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) + $display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); + else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01)) + $display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); + + end // else: !if(chk_ox_msg == 1) + + col_wra_rdb_msg = 0; + + end + else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if (chk_ox_msg == 1) begin + + if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) + $display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp); + + end + else begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) + $display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); + else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01)) + $display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); + + end // else: !if(chk_ox_msg == 1) + + col_wrb_rda_msg = 0; + + end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) + + end + + endtask // chk_for_col_msg + + + task task_col_ecc_read; + + inout [63:0] do_tmp; + inout [7:0] dop_tmp; + input [15:0] addr_tmp; + + reg [71:0] task_ecc_bit_position; + reg [7:0] task_dopr_ecc, task_syndrome; + reg [63:0] task_di_in_ecc_corrected; + reg [7:0] task_dip_in_ecc_corrected; + + begin + + if (|do_tmp === 1'bx) begin // if there is collision + dbiterr_out <= 1'bx; + sbiterr_out <= 1'bx; + end + else begin + + task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); + + task_syndrome = task_dopr_ecc ^ dop_tmp; + + if (task_syndrome !== 0) begin + + if (task_syndrome[7]) begin // dectect single bit error + + task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; + + + if (task_syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output + + task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory + + do_tmp = task_di_in_ecc_corrected; + + task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_tmp = task_dip_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!task_syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (task_syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(task_syndrome !== 0) + + end + + end + + endtask // task_col_ecc_read + + + function [7:0] fn_dip_ecc; + + input encode; + input [63:0] di_in; + input [7:0] dip_in; + + begin + + fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + if (encode == 1'b1) + + fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + else + fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + end + + endfunction // fn_dip_ecc + +/******************************************** END task and function **************************************/ + + + initial begin + if (INIT_FILE == "NONE") begin // memory initialization from attributes + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + + if (BRAM_SIZE == 36) begin + mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; + mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; + mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; + mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; + mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; + mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; + mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; + mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; + mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; + mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; + mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; + mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; + mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; + mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; + mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; + mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; + mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; + mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; + mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; + mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; + mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; + mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; + mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; + mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; + mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; + mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; + mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; + mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; + mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; + mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; + mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; + mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; + mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; + mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; + mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; + mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; + mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; + mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; + mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; + mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; + mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; + mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; + mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; + mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; + mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; + mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; + mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; + mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; + mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; + mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; + mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; + mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; + mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; + mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; + mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; + mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; + mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; + mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; + mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; + mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; + mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; + mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; + mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; + mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; + end // if (BRAM_SIZE == 36) + end // for (count = 0; count < init_mult; count = count + 1) + + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + if (BRAM_SIZE == 36) begin + memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; + memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; + memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; + memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; + memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; + memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; + memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; + memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; + end + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin // memory initialization from memory file + for (j = 0; j < mem_depth; j = j + 1) begin + for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin + tmp_mem[j][j1] = 1'b0; + end + end + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + end + 9 : if ((width == 8) && (widthp == 1)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 18 : if ((width == 16) && (widthp == 2)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 36 : if ((width == 32) && (widthp == 4)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + 72 : if ((width == 64) && (widthp == 8)) begin + for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: width]; + memp[i_mem] = tmp_mem[i_mem][width +: widthp]; + end + end + endcase // case(widest_width) + end // else: !if(INIT_FILE == "NONE") + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int = 1; + "FALSE" : en_ecc_write_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int = 1; + "FALSE" : en_ecc_read_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + case (RAM_MODE) + "TDP" : begin + ram_mode_int = 1; + + if (en_ecc_write_int == 1) begin + $display("DRC Error : The attribute EN_ECC_WRITE on RAMB36E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE); + finish_error = 1; + end + + if (en_ecc_read_int == 1) begin + $display("DRC Error : The attribute EN_ECC_READ on RAMB36E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ); + finish_error = 1; + end + + end // case: "TDP" + "SDP" : begin + ram_mode_int = 0; + + if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin + + $display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB36E1 instance %m."); + + finish_error = 1; + + end + + + if (BRAM_SIZE == 18) begin + if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin + + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP."); + + finish_error = 1; + end + end + else begin + + if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP."); + finish_error = 1; + end + end // else: !if(BRAM_SIZE == 18) + + end // case: "SDP" + default : begin + $display("Attribute Syntax Error : The attribute RAM_MODE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE); + finish_error = 1; + end + endcase + + + case (WRITE_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_A) + + + case (WRITE_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_B) + + + case (READ_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_A) + + + case (READ_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_B) + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB36E1 instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a = 2'b00; + "READ_FIRST" : wr_mode_a = 2'b01; + "NO_CHANGE" : wr_mode_a = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b = 2'b00; + "READ_FIRST" : wr_mode_b = 2'b01; + "NO_CHANGE" : wr_mode_b = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + case (RAM_EXTENSION_A) + "UPPER" : cascade_a = 2'b11; + "LOWER" : cascade_a = 2'b01; + "NONE" : cascade_a = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); + finish_error = 1; + end + endcase + + + case (RAM_EXTENSION_B) + "UPPER" : cascade_b = 2'b11; + "LOWER" : cascade_b = 2'b01; + "NONE" : cascade_b = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB36E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + case (RSTREG_PRIORITY_A) + "RSTREG" : rstreg_priority_a_int = 1; + "REGCE" : rstreg_priority_a_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A); + finish_error = 1; + end + endcase + + + case (RSTREG_PRIORITY_B) + "RSTREG" : rstreg_priority_b_int = 1; + "REGCE" : rstreg_priority_b_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B); + finish_error = 1; + end + endcase + + + if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin + $display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB36E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE."); + finish_error = 1; + end + + + case (RDADDR_COLLISION_HWCONFIG) + "DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0; + "PERFORMANCE" : rdaddr_collision_hwconfig_int = 1; + default : begin + $display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB36E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG); + finish_error = 1; + end + endcase + + + if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE); + finish_error = 1; + end + + + if (finish_error == 1) + #1 $finish; + + + end // initial begin + + + // GSR + always @(GSR) + if (GSR) begin + + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + assign rdaddrecc_out = 9'b0; + + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + deassign rdaddrecc_out; + + end + + + always @(time_clka_period or time_clkb_period) begin + + if (time_clka_period != 0 && time_clkb_period != 0) begin + + if (time_clka_period <= time_clkb_period) begin + + if (time_clka_period <= SETUP_READ_FIRST) begin + time_period = time_clka_period; + end + else begin + time_period = SETUP_READ_FIRST; + end + + end + else if (time_clkb_period <= SETUP_READ_FIRST) + time_period = time_clkb_period; + else + time_period = SETUP_READ_FIRST; + + end + end + + // registering signals + always @(posedge CLKA) begin + +`ifdef MODEL_TECH + #0 rising_clka = 1; // mentor race condition check +`else + rising_clka = 1; +`endif + if (time_skew_a_flag == 0) begin + if ($time > 110000) begin + time_clka_period = $time - time_port_a; + time_skew_a_flag = 1; + end + end + + + if (ENA === 1'b1) begin + time_port_a = $time; + addra_reg = ADDRA; + wea_reg = WEA; + dia_reg = DIA; + dipa_reg = DIPA; + ox_addra_reconstruct_reg = ox_addra_reconstruct; + end + + end + + always @(posedge CLKB) begin + +`ifdef MODEL_TECH + #0 rising_clkb = 1; // mentor race condition check +`else + rising_clkb = 1; +`endif + + if (time_skew_b_flag == 0) begin + if ($time > 110000) begin + time_clkb_period = $time - time_port_b; + time_skew_b_flag = 1; + end + end + + + if (ENB === 1'b1) begin + time_port_b = $time; + addrb_reg = ADDRB; + web_reg = WEB; + enb_reg = ENB; + dib_reg = DIB; + dipb_reg = DIPB; + ox_addrb_reconstruct_reg = ox_addrb_reconstruct; + end + + end // always @ (posedge CLKB) + + + // CLKA and CLKB + always @(posedge rising_clka or posedge rising_clkb) begin + + // Registering addr[15] for cascade mode + if (rising_clka) + if (cascade_a[1]) + addra_in_15_reg_bram = ~ADDRA[15]; + else + addra_in_15_reg_bram = ADDRA[15]; + + if (rising_clkb) + if (cascade_b[1]) + addrb_in_15_reg_bram = ~ADDRB[15]; + else + addrb_in_15_reg_bram = ADDRB[15]; + + if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (GSR === 1'b0) begin + + if (time_port_a > time_port_b) begin + + if (time_port_a - time_port_b <= sync_clk_skew) begin + viol_time = 1; + end + else if (time_port_a - time_port_b <= time_period) begin + viol_time = 2; + end + end + else begin + + if (time_port_b - time_port_a <= sync_clk_skew) begin + viol_time = 1; + end + else if (time_port_b - time_port_a <= time_period) begin + viol_time = 2; + end + + end // else: !if(time_port_a > time_port_b) + + + if (ENA === 1'b0 || ENB === 1'b0) + viol_time = 0; + + + if ((WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000)) + if ((WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00)) + viol_time = 0; + + + if (viol_time != 0) begin + + if (SIM_DEVICE == "VIRTEX6") begin + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + + if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b01; + chk_col_same_clk = 1; + + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin + doa_buf = dob_buf; + dopa_buf = dopb_buf; + end + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin + dob_buf = doa_buf; + dopb_buf = dopa_buf; + end + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + chk_col_same_clk = 0; + + task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin + task_col_wr_ram_a (2'b10, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b10, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + end + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin + + viol_type = 2'b01; + chk_ox_msg = 1; + chk_ox_same_clk = 1; + + if (time_port_a > time_port_b) + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + else if (time_port_b > time_port_a) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + + chk_ox_msg = 0; + chk_ox_same_clk = 0; + + task_ox_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + + if (rdaddr_collision_hwconfig_int == 1) begin + task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, ADDRB); + end + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (rising_clka && rising_clkb) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + + + if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b10, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin + + viol_type = 2'b10; + chk_ox_msg = 1; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + // get msg + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + chk_ox_msg = 0; + + task_ox_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, addrb_reg); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + + + if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + + task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin + + viol_type = 2'b11; + chk_ox_msg = 1; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + // get msg + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + chk_ox_msg = 0; + + task_ox_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, ADDRB); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) + else + viol_time = 0; + + + end // if (!rising_clka && rising_clkb) + + + end // if (SIM_DEVICE == "VIRTEX6") + else begin // 7series + + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + + if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b01; + chk_col_same_clk = 1; + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin + doa_buf = dob_buf; + dopa_buf = dopb_buf; + end + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin + dob_buf = doa_buf; + dopb_buf = dopa_buf; + end + else begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + end + + + task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); + task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); + chk_col_same_clk = 0; + + task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); + + + dib_ecc_col = DIB; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); + + if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if ((rising_clka && rising_clkb) || viol_time == 1) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + + + if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); + task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); + + + dib_ecc_col = dib_reg; + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, ADDRA); + + + end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + + + if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); + + task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); + + + dib_ecc_col = DIB; + + + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + + end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) + else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin + + $display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); + + $finish; + + end + else + viol_time = 0; + + + end // if (!rising_clka && rising_clkb) + + + end // else: !if(SIM_DEVICE == "VIRTEX6") + + + + end // if (viol_time != 0) + end // if (GSR === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) + + +/**************************** Port A ****************************************/ + if (rising_clka) begin + + // DRC + if (RSTRAMA === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB36E1 instance %m."); + + // end DRC + + + // registering ADDRA[15] the second time + if (REGCEA) + addra_in_15_reg1 = addra_in_15_reg; + + + if (ENA && (wr_mode_a != 2'b10 || WEA[0] == 0 || RSTRAMA == 1'b1)) + if (cascade_a[1]) + addra_in_15_reg = ~ADDRA[15]; + else + addra_in_15_reg = ADDRA[15]; + + + if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin + + // SRVAL + if (RSTRAMA === 1'b1) begin + + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + + if (viol_time == 0) begin + + // Read first + if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + + // ECC decode + if (ram_mode_int == 0 && en_ecc_read_int == 1) begin + + dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); + + syndrome = dopr_ecc ^ dopa_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + doa_buf = dia_in_ecc_corrected; + + dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dopa_buf = dipa_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(syndrome !== 0) + + + // output of rdaddrecc + rdaddrecc_out[8:0] <= ADDRA[14:6]; + + end // if (ram_mode_int == 0 && en_ecc_read_int == 1) + end // if (wr_mode_a == 2'b01) + + + // Write + task_wr_ram_a (WEA, DIA, DIPA, ADDRA); + + // Read if not read first + if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1)) + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + end // if (viol_time == 0) + + end // if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) + + end // if (rising_clka) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkb) begin + + // DRC + if (RSTRAMB === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB36E1 instance %m."); + + if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin + + if (injectsbiterr_in === 1) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB36E1 instance %m."); + + if (injectdbiterr_in === 1) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB36E1 instance %m."); + + end + // End DRC + + + if (REGCEB) + addrb_in_15_reg1 = addrb_in_15_reg; + + + if (ENB && (wr_mode_b != 2'b10 || WEB[0] == 0 || RSTRAMB == 1'b1)) + if (cascade_b[1]) + addrb_in_15_reg = ~ADDRB[15]; + else + addrb_in_15_reg = ADDRB[15]; + + + if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + + // SRVAL + if (RSTRAMB === 1'b1) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + end + + + if (viol_time == 0) begin + + // ECC encode + if (ram_mode_int == 0 && en_ecc_write_int == 1) begin + dip_ecc = fn_dip_ecc(1'b1, DIB, DIPB); + eccparity_out = dip_ecc; + dipb_in_ecc = dip_ecc; + end + else + dipb_in_ecc = DIPB; + + + dib_in_ecc = DIB; + + + // injecting error + if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin + + if (injectdbiterr_in === 1) begin // double bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + dib_in_ecc[62] = ~dib_in_ecc[62]; + end + else if (injectsbiterr_in === 1) begin // single bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + end + + end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) + + + // Read first + if (wr_mode_b == 2'b01 && RSTRAMB === 1'b0) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + + // Write + task_wr_ram_b (WEB, dib_in_ecc, dipb_in_ecc, ADDRB); + + + // Read if not read first + if (wr_mode_b != 2'b01 && RSTRAMB === 1'b0) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + end // if (viol_time == 0) + + + end // if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) + + end // if (rising_clkb) + // end of port B + + + if (GSR == 1'b0) begin + + // writing outputs of port A + if (ENA && (rising_clka || viol_time != 0)) begin + + if (RSTRAMA === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))) begin + + doa_out <= doa_buf; + + if (ra_width >= 8) + dopa_out <= dopa_buf; + + end + + end + + + // writing outputs of port B + if (ENB && (rising_clkb || viol_time != 0)) begin + + if (RSTRAMB === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) begin + + dob_out <= dob_buf; + + if (rb_width >= 8) + dopb_out <= dopb_buf; + + end + + end + + end // if (GSR == 1'b0) + + + viol_time = 0; +`ifdef MODEL_TECH + #0 rising_clka = 0; // mentor race condition check + #0 rising_clkb = 0; // mentor race condition check +`else + rising_clka = 0; + rising_clkb = 0; +`endif + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + end // always @ (posedge rising_clka or posedge rising_clkb) + + + // ********* Cascade Port A ******** + always @(posedge CLKA or CASCADEINA or addra_in_15_reg or doa_out or dopa_out) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin + doa_out_mux[0] = CASCADEINA; + end + else begin + doa_out_mux = doa_out; + + if (ra_width >= 8) + dopa_out_mux = dopa_out; + + end + + end + + // output register mode + always @(posedge CLKA or CASCADEINA or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin + doa_outreg_mux[0] = CASCADEINA; + end + else begin + doa_outreg_mux = doa_outreg; + + if (ra_width >= 8) + dopa_outreg_mux = dopa_outreg; + + end + + end + + + // ********* Cascade Port B ******** + always @(posedge CLKB or CASCADEINB or addrb_in_15_reg or dob_out or dopb_out) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin + dob_out_mux[0] = CASCADEINB; + end + else begin + dob_out_mux = dob_out; + + if (rb_width >= 8) + dopb_out_mux = dopb_out; + + end + + end + + // output register mode + always @(posedge CLKB or CASCADEINB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin + dob_outreg_mux[0] = CASCADEINB; + end + else begin + dob_outreg_mux = dob_outreg; + + if (rb_width >= 8) + dopb_outreg_mux = dopb_outreg; + + end + + end // always @ (posedge REGCLKB or CASCADEINREGB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) + + + // ***** Output Registers **** Port A ***** + always @(posedge CLKA or posedge GSR) begin + + if (DOA_REG == 1) begin + + if (GSR == 1'b1) begin + + rdaddrecc_outreg <= 9'b0; + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (GSR == 1'b0) begin + + if (REGCEA === 1'b1) begin + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + rdaddrecc_outreg <= rdaddrecc_out; + end + + + if (rstreg_priority_a_int == 0) begin // Virtex5 behavior + + if (REGCEA == 1'b1) begin + if (RSTREGA == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (RSTREGA == 1'b0) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end // if (REGCEA == 1'b1) + + end // if (rstreg_priority_a_int == 1'b0) + else begin + + if (RSTREGA == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + + else if (RSTREGA == 1'b0) begin + + if (REGCEA == 1'b1) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end + end // else: !if(rstreg_priority_a_int == 1'b0) + + end // if (GSR == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge CLKA or posedge GSR) + + + always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin + + case (DOA_REG) + + 0 : begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + rdaddrecc_out_out = rdaddrecc_out; + DOA[0 +: ra_width] = doa_out_mux[0 +: ra_width]; + + if (ra_width >= 8) + DOPA[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp]; + + end + 1 : begin + dbiterr_out_out = dbiterr_outreg; + sbiterr_out_out = sbiterr_outreg; + DOA[0 +: ra_width] = doa_outreg_mux[0 +: ra_width]; + rdaddrecc_out_out = rdaddrecc_outreg; + + if (ra_width >= 8) + DOPA[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RAMB36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge CLKB or posedge GSR) begin + + if (DOB_REG == 1) begin + + if (GSR == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (GSR == 1'b0) begin + + if (rstreg_priority_b_int == 0) begin // Virtex5 behavior + + if (REGCEB == 1'b1) begin + if (RSTREGB == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (RSTREGB == 1'b0) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end // if (REGCEB == 1'b1) + + end // if (rstreg_priority_b_int == 1'b0) + else begin + + if (RSTREGB == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + + else if (RSTREGB == 1'b0) begin + + if (REGCEB == 1'b1) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end + end // else: !if(rstreg_priority_b_int == 1'b0) + + end // if (GSR == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge CLKB or posedge GSR) + + + always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin + + case (DOB_REG) + + 0 : begin + DOB[0 +: rb_width] = dob_out_mux[0 +: rb_width]; + + if (rb_width >= 8) + DOPB[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp]; + end + 1 : begin + DOB[0 +: rb_width] = dob_outreg_mux[0 +: rb_width]; + + if (rb_width >= 8) + DOPB[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RAMB36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) + + +endmodule // RB36_INTERNAL_VLOG + +`endcelldefine + +// end of RB36_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/src/unisims/RAMB36E2.v b/verilog/src/unisims/RAMB36E2.v new file mode 100644 index 0000000..02da692 --- /dev/null +++ b/verilog/src/unisims/RAMB36E2.v @@ -0,0 +1,3726 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2014 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2014.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 36K-bit Configurable Synchronous Block RAM +// /___/ /\ Filename : RAMB36E2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 02/28/2013 - intial from FIFO +// 03/09/2013 - update from various initial CR - collisions +// 03/19/2013 - 707443 - RDADDRECC not hooked up +// 03/22/2013 - sync5 yaml update, port ordering +// 03/25/2013 - 707719 - Add sync5 cascade feature +// 03/27/2013 - revert NO_CHANGE fix +// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP +// 04/23/2013 - PR683925 - add invertible pin support. +// 04/26/2013 - 714182 - RDADDRECC bits shifted by 1. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMB36E2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE_ORDER_A = "NONE", + parameter CASCADE_ORDER_B = "NONE", + parameter CLOCK_DOMAINS = "INDEPENDENT", + parameter integer DOA_REG = 1, + parameter integer DOB_REG = 1, + parameter ENADDRENA = "FALSE", + parameter ENADDRENB = "FALSE", + parameter EN_ECC_PIPE = "FALSE", + parameter EN_ECC_READ = "FALSE", + parameter EN_ECC_WRITE = "FALSE", + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000, + parameter [35:0] INIT_A = 36'h000000000, + parameter [35:0] INIT_B = 36'h000000000, + parameter INIT_FILE = "NONE", + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0, + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0, + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0, + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0, + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0, + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0, + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0, + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0, + parameter RDADDRCHANGEA = "FALSE", + parameter RDADDRCHANGEB = "FALSE", + parameter integer READ_WIDTH_A = 0, + parameter integer READ_WIDTH_B = 0, + parameter RSTREG_PRIORITY_A = "RSTREG", + parameter RSTREG_PRIORITY_B = "RSTREG", + parameter SIM_COLLISION_CHECK = "ALL", + parameter SLEEP_ASYNC = "FALSE", + parameter [35:0] SRVAL_A = 36'h000000000, + parameter [35:0] SRVAL_B = 36'h000000000, + parameter WRITE_MODE_A = "NO_CHANGE", + parameter WRITE_MODE_B = "NO_CHANGE", + parameter integer WRITE_WIDTH_A = 0, + parameter integer WRITE_WIDTH_B = 0 +)( + output [31:0] CASDOUTA, + output [31:0] CASDOUTB, + output [3:0] CASDOUTPA, + output [3:0] CASDOUTPB, + output CASOUTDBITERR, + output CASOUTSBITERR, + output DBITERR, + output [31:0] DOUTADOUT, + output [31:0] DOUTBDOUT, + output [3:0] DOUTPADOUTP, + output [3:0] DOUTPBDOUTP, + output [7:0] ECCPARITY, + output [8:0] RDADDRECC, + output SBITERR, + + input [14:0] ADDRARDADDR, + input [14:0] ADDRBWRADDR, + input ADDRENA, + input ADDRENB, + input CASDIMUXA, + input CASDIMUXB, + input [31:0] CASDINA, + input [31:0] CASDINB, + input [3:0] CASDINPA, + input [3:0] CASDINPB, + input CASDOMUXA, + input CASDOMUXB, + input CASDOMUXEN_A, + input CASDOMUXEN_B, + input CASINDBITERR, + input CASINSBITERR, + input CASOREGIMUXA, + input CASOREGIMUXB, + input CASOREGIMUXEN_A, + input CASOREGIMUXEN_B, + input CLKARDCLK, + input CLKBWRCLK, + input [31:0] DINADIN, + input [31:0] DINBDIN, + input [3:0] DINPADINP, + input [3:0] DINPBDINP, + input ECCPIPECE, + input ENARDEN, + input ENBWREN, + input INJECTDBITERR, + input INJECTSBITERR, + input REGCEAREGCE, + input REGCEB, + input RSTRAMARSTRAM, + input RSTRAMB, + input RSTREGARSTREG, + input RSTREGB, + input SLEEP, + input [3:0] WEA, + input [7:0] WEBWE +); + +// define constants + localparam MODULE_NAME = "RAMB36E2"; + +// Parameter encodings and registers + localparam CASCADE_ORDER_A_FIRST = 1; + localparam CASCADE_ORDER_A_LAST = 2; + localparam CASCADE_ORDER_A_MIDDLE = 3; + localparam CASCADE_ORDER_A_NONE = 0; + localparam CASCADE_ORDER_B_FIRST = 1; + localparam CASCADE_ORDER_B_LAST = 2; + localparam CASCADE_ORDER_B_MIDDLE = 3; + localparam CASCADE_ORDER_B_NONE = 0; + localparam CLOCK_DOMAINS_COMMON = 1; + localparam CLOCK_DOMAINS_INDEPENDENT = 0; + localparam DOA_REG_0 = 1; + localparam DOA_REG_1 = 0; + localparam DOB_REG_0 = 1; + localparam DOB_REG_1 = 0; + localparam ENADDRENA_FALSE = 0; + localparam ENADDRENA_TRUE = 1; + localparam ENADDRENB_FALSE = 0; + localparam ENADDRENB_TRUE = 1; + localparam EN_ECC_PIPE_FALSE = 0; + localparam EN_ECC_PIPE_TRUE = 1; + localparam EN_ECC_READ_FALSE = 0; + localparam EN_ECC_READ_TRUE = 1; + localparam EN_ECC_WRITE_FALSE = 0; + localparam EN_ECC_WRITE_TRUE = 1; + localparam RDADDRCHANGEA_FALSE = 0; + localparam RDADDRCHANGEA_TRUE = 1; + localparam RDADDRCHANGEB_FALSE = 0; + localparam RDADDRCHANGEB_TRUE = 1; + localparam READ_WIDTH_A_0 = 1; + localparam READ_WIDTH_A_1 = 1; + localparam READ_WIDTH_A_18 = 16; + localparam READ_WIDTH_A_2 = 2; + localparam READ_WIDTH_A_36 = 32; + localparam READ_WIDTH_A_4 = 4; + localparam READ_WIDTH_A_72 = 64; + localparam READ_WIDTH_A_9 = 8; + localparam READ_WIDTH_B_0 = 1; + localparam READ_WIDTH_B_1 = 1; + localparam READ_WIDTH_B_18 = 16; + localparam READ_WIDTH_B_2 = 2; + localparam READ_WIDTH_B_36 = 32; + localparam READ_WIDTH_B_4 = 4; + localparam READ_WIDTH_B_9 = 8; + localparam RSTREG_PRIORITY_A_REGCE = 1; + localparam RSTREG_PRIORITY_A_RSTREG = 0; + localparam RSTREG_PRIORITY_B_REGCE = 1; + localparam RSTREG_PRIORITY_B_RSTREG = 0; + localparam SIM_COLLISION_CHECK_ALL = 0; + localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1; + localparam SIM_COLLISION_CHECK_NONE = 2; + localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3; + localparam SLEEP_ASYNC_FALSE = 0; + localparam SLEEP_ASYNC_TRUE = 1; + localparam WRITE_MODE_A_NO_CHANGE = 0; + localparam WRITE_MODE_A_READ_FIRST = 1; + localparam WRITE_MODE_A_WRITE_FIRST = 2; + localparam WRITE_MODE_B_NO_CHANGE = 0; + localparam WRITE_MODE_B_READ_FIRST = 1; + localparam WRITE_MODE_B_WRITE_FIRST = 2; + localparam WRITE_WIDTH_A_0 = 1; + localparam WRITE_WIDTH_A_1 = 1; + localparam WRITE_WIDTH_A_18 = 16; + localparam WRITE_WIDTH_A_2 = 2; + localparam WRITE_WIDTH_A_36 = 32; + localparam WRITE_WIDTH_A_4 = 4; + localparam WRITE_WIDTH_A_9 = 8; + localparam WRITE_WIDTH_B_0 = 1; + localparam WRITE_WIDTH_B_1 = 1; + localparam WRITE_WIDTH_B_18 = 16; + localparam WRITE_WIDTH_B_2 = 2; + localparam WRITE_WIDTH_B_36 = 32; + localparam WRITE_WIDTH_B_4 = 4; + localparam WRITE_WIDTH_B_72 = 64; + localparam WRITE_WIDTH_B_9 = 8; + +// include dynamic registers - XILINX test only + reg trig_attr = 1'b0; +`ifdef XIL_DR + `include "RAMB36E2_dr.v" +`else + localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A; + localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B; + localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS; + localparam [0:0] DOA_REG_REG = DOA_REG; + localparam [0:0] DOB_REG_REG = DOB_REG; + localparam [40:1] ENADDRENA_REG = ENADDRENA; + localparam [40:1] ENADDRENB_REG = ENADDRENB; + localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE; + localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ; + localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE; + localparam [255:0] INITP_00_REG = INITP_00; + localparam [255:0] INITP_01_REG = INITP_01; + localparam [255:0] INITP_02_REG = INITP_02; + localparam [255:0] INITP_03_REG = INITP_03; + localparam [255:0] INITP_04_REG = INITP_04; + localparam [255:0] INITP_05_REG = INITP_05; + localparam [255:0] INITP_06_REG = INITP_06; + localparam [255:0] INITP_07_REG = INITP_07; + localparam [255:0] INITP_08_REG = INITP_08; + localparam [255:0] INITP_09_REG = INITP_09; + localparam [255:0] INITP_0A_REG = INITP_0A; + localparam [255:0] INITP_0B_REG = INITP_0B; + localparam [255:0] INITP_0C_REG = INITP_0C; + localparam [255:0] INITP_0D_REG = INITP_0D; + localparam [255:0] INITP_0E_REG = INITP_0E; + localparam [255:0] INITP_0F_REG = INITP_0F; + localparam [255:0] INIT_00_REG = INIT_00; + localparam [255:0] INIT_01_REG = INIT_01; + localparam [255:0] INIT_02_REG = INIT_02; + localparam [255:0] INIT_03_REG = INIT_03; + localparam [255:0] INIT_04_REG = INIT_04; + localparam [255:0] INIT_05_REG = INIT_05; + localparam [255:0] INIT_06_REG = INIT_06; + localparam [255:0] INIT_07_REG = INIT_07; + localparam [255:0] INIT_08_REG = INIT_08; + localparam [255:0] INIT_09_REG = INIT_09; + localparam [255:0] INIT_0A_REG = INIT_0A; + localparam [255:0] INIT_0B_REG = INIT_0B; + localparam [255:0] INIT_0C_REG = INIT_0C; + localparam [255:0] INIT_0D_REG = INIT_0D; + localparam [255:0] INIT_0E_REG = INIT_0E; + localparam [255:0] INIT_0F_REG = INIT_0F; + localparam [255:0] INIT_10_REG = INIT_10; + localparam [255:0] INIT_11_REG = INIT_11; + localparam [255:0] INIT_12_REG = INIT_12; + localparam [255:0] INIT_13_REG = INIT_13; + localparam [255:0] INIT_14_REG = INIT_14; + localparam [255:0] INIT_15_REG = INIT_15; + localparam [255:0] INIT_16_REG = INIT_16; + localparam [255:0] INIT_17_REG = INIT_17; + localparam [255:0] INIT_18_REG = INIT_18; + localparam [255:0] INIT_19_REG = INIT_19; + localparam [255:0] INIT_1A_REG = INIT_1A; + localparam [255:0] INIT_1B_REG = INIT_1B; + localparam [255:0] INIT_1C_REG = INIT_1C; + localparam [255:0] INIT_1D_REG = INIT_1D; + localparam [255:0] INIT_1E_REG = INIT_1E; + localparam [255:0] INIT_1F_REG = INIT_1F; + localparam [255:0] INIT_20_REG = INIT_20; + localparam [255:0] INIT_21_REG = INIT_21; + localparam [255:0] INIT_22_REG = INIT_22; + localparam [255:0] INIT_23_REG = INIT_23; + localparam [255:0] INIT_24_REG = INIT_24; + localparam [255:0] INIT_25_REG = INIT_25; + localparam [255:0] INIT_26_REG = INIT_26; + localparam [255:0] INIT_27_REG = INIT_27; + localparam [255:0] INIT_28_REG = INIT_28; + localparam [255:0] INIT_29_REG = INIT_29; + localparam [255:0] INIT_2A_REG = INIT_2A; + localparam [255:0] INIT_2B_REG = INIT_2B; + localparam [255:0] INIT_2C_REG = INIT_2C; + localparam [255:0] INIT_2D_REG = INIT_2D; + localparam [255:0] INIT_2E_REG = INIT_2E; + localparam [255:0] INIT_2F_REG = INIT_2F; + localparam [255:0] INIT_30_REG = INIT_30; + localparam [255:0] INIT_31_REG = INIT_31; + localparam [255:0] INIT_32_REG = INIT_32; + localparam [255:0] INIT_33_REG = INIT_33; + localparam [255:0] INIT_34_REG = INIT_34; + localparam [255:0] INIT_35_REG = INIT_35; + localparam [255:0] INIT_36_REG = INIT_36; + localparam [255:0] INIT_37_REG = INIT_37; + localparam [255:0] INIT_38_REG = INIT_38; + localparam [255:0] INIT_39_REG = INIT_39; + localparam [255:0] INIT_3A_REG = INIT_3A; + localparam [255:0] INIT_3B_REG = INIT_3B; + localparam [255:0] INIT_3C_REG = INIT_3C; + localparam [255:0] INIT_3D_REG = INIT_3D; + localparam [255:0] INIT_3E_REG = INIT_3E; + localparam [255:0] INIT_3F_REG = INIT_3F; + localparam [255:0] INIT_40_REG = INIT_40; + localparam [255:0] INIT_41_REG = INIT_41; + localparam [255:0] INIT_42_REG = INIT_42; + localparam [255:0] INIT_43_REG = INIT_43; + localparam [255:0] INIT_44_REG = INIT_44; + localparam [255:0] INIT_45_REG = INIT_45; + localparam [255:0] INIT_46_REG = INIT_46; + localparam [255:0] INIT_47_REG = INIT_47; + localparam [255:0] INIT_48_REG = INIT_48; + localparam [255:0] INIT_49_REG = INIT_49; + localparam [255:0] INIT_4A_REG = INIT_4A; + localparam [255:0] INIT_4B_REG = INIT_4B; + localparam [255:0] INIT_4C_REG = INIT_4C; + localparam [255:0] INIT_4D_REG = INIT_4D; + localparam [255:0] INIT_4E_REG = INIT_4E; + localparam [255:0] INIT_4F_REG = INIT_4F; + localparam [255:0] INIT_50_REG = INIT_50; + localparam [255:0] INIT_51_REG = INIT_51; + localparam [255:0] INIT_52_REG = INIT_52; + localparam [255:0] INIT_53_REG = INIT_53; + localparam [255:0] INIT_54_REG = INIT_54; + localparam [255:0] INIT_55_REG = INIT_55; + localparam [255:0] INIT_56_REG = INIT_56; + localparam [255:0] INIT_57_REG = INIT_57; + localparam [255:0] INIT_58_REG = INIT_58; + localparam [255:0] INIT_59_REG = INIT_59; + localparam [255:0] INIT_5A_REG = INIT_5A; + localparam [255:0] INIT_5B_REG = INIT_5B; + localparam [255:0] INIT_5C_REG = INIT_5C; + localparam [255:0] INIT_5D_REG = INIT_5D; + localparam [255:0] INIT_5E_REG = INIT_5E; + localparam [255:0] INIT_5F_REG = INIT_5F; + localparam [255:0] INIT_60_REG = INIT_60; + localparam [255:0] INIT_61_REG = INIT_61; + localparam [255:0] INIT_62_REG = INIT_62; + localparam [255:0] INIT_63_REG = INIT_63; + localparam [255:0] INIT_64_REG = INIT_64; + localparam [255:0] INIT_65_REG = INIT_65; + localparam [255:0] INIT_66_REG = INIT_66; + localparam [255:0] INIT_67_REG = INIT_67; + localparam [255:0] INIT_68_REG = INIT_68; + localparam [255:0] INIT_69_REG = INIT_69; + localparam [255:0] INIT_6A_REG = INIT_6A; + localparam [255:0] INIT_6B_REG = INIT_6B; + localparam [255:0] INIT_6C_REG = INIT_6C; + localparam [255:0] INIT_6D_REG = INIT_6D; + localparam [255:0] INIT_6E_REG = INIT_6E; + localparam [255:0] INIT_6F_REG = INIT_6F; + localparam [255:0] INIT_70_REG = INIT_70; + localparam [255:0] INIT_71_REG = INIT_71; + localparam [255:0] INIT_72_REG = INIT_72; + localparam [255:0] INIT_73_REG = INIT_73; + localparam [255:0] INIT_74_REG = INIT_74; + localparam [255:0] INIT_75_REG = INIT_75; + localparam [255:0] INIT_76_REG = INIT_76; + localparam [255:0] INIT_77_REG = INIT_77; + localparam [255:0] INIT_78_REG = INIT_78; + localparam [255:0] INIT_79_REG = INIT_79; + localparam [255:0] INIT_7A_REG = INIT_7A; + localparam [255:0] INIT_7B_REG = INIT_7B; + localparam [255:0] INIT_7C_REG = INIT_7C; + localparam [255:0] INIT_7D_REG = INIT_7D; + localparam [255:0] INIT_7E_REG = INIT_7E; + localparam [255:0] INIT_7F_REG = INIT_7F; + localparam [35:0] INIT_A_REG = INIT_A; + localparam [35:0] INIT_B_REG = INIT_B; + localparam INIT_FILE_REG = INIT_FILE; + localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED; + localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED; + localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED; + localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED; + localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED; + localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED; + localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED; + localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED; + localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA; + localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB; + localparam [6:0] READ_WIDTH_A_REG = READ_WIDTH_A; + localparam [5:0] READ_WIDTH_B_REG = READ_WIDTH_B; + localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A; + localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B; + localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK; + localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC; + localparam [35:0] SRVAL_A_REG = SRVAL_A; + localparam [35:0] SRVAL_B_REG = SRVAL_B; + localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A; + localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B; + localparam [5:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A; + localparam [6:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B; +`endif + + wire [1:0] CASCADE_ORDER_A_BIN; + wire [1:0] CASCADE_ORDER_B_BIN; + wire CLOCK_DOMAINS_BIN; + wire DOA_REG_BIN; + wire DOB_REG_BIN; + wire ENADDRENA_BIN; + wire ENADDRENB_BIN; + wire EN_ECC_PIPE_BIN; + wire EN_ECC_READ_BIN; + wire EN_ECC_WRITE_BIN; + wire [255:0] INITP_BIN [0:15]; + wire [255:0] INIT_BIN [0:127]; + wire [35:0] INIT_A_BIN; + wire [35:0] INIT_B_BIN; + wire IS_CLKARDCLK_INVERTED_BIN; + wire IS_CLKBWRCLK_INVERTED_BIN; + wire IS_ENARDEN_INVERTED_BIN; + wire IS_ENBWREN_INVERTED_BIN; + wire IS_RSTRAMARSTRAM_INVERTED_BIN; + wire IS_RSTRAMB_INVERTED_BIN; + wire IS_RSTREGARSTREG_INVERTED_BIN; + wire IS_RSTREGB_INVERTED_BIN; + wire RDADDRCHANGEA_BIN; + wire RDADDRCHANGEB_BIN; + wire [6:0] READ_WIDTH_A_BIN; + wire [6:0] READ_WIDTH_B_BIN; + wire RSTREG_PRIORITY_A_BIN; + wire RSTREG_PRIORITY_B_BIN; + wire [1:0] SIM_COLLISION_CHECK_BIN; + wire SLEEP_ASYNC_BIN; + wire [35:0] SRVAL_A_BIN; + wire [35:0] SRVAL_B_BIN; + wire [1:0] WRITE_MODE_A_BIN; + wire [1:0] WRITE_MODE_B_BIN; + wire [6:0] WRITE_WIDTH_A_BIN; + wire [6:0] WRITE_WIDTH_B_BIN; + reg INIT_MEM = 0; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR || INIT_MEM; + + wire CASOUTDBITERR_out; + wire CASOUTSBITERR_out; + reg DBITERR_out; + reg SBITERR_out; + wire [31:0] CASDOUTA_out; + wire [31:0] CASDOUTB_out; + reg [31:0] DOUTADOUT_out; + reg [31:0] DOUTBDOUT_out; + wire [3:0] CASDOUTPA_out; + wire [3:0] CASDOUTPB_out; + reg [3:0] DOUTPADOUTP_out; + reg [3:0] DOUTPBDOUTP_out; + wire [7:0] ECCPARITY_out; + wire [8:0] RDADDRECC_out; + + wire ADDRENA_in; + wire ADDRENB_in; + wire CASDIMUXA_in; + wire CASDIMUXB_in; + wire CASDOMUXA_in; + wire CASDOMUXB_in; + wire CASDOMUXEN_A_in; + wire CASDOMUXEN_B_in; + wire CASINDBITERR_in; + wire CASINSBITERR_in; + wire CASOREGIMUXA_in; + wire CASOREGIMUXB_in; + wire CASOREGIMUXEN_A_in; + wire CASOREGIMUXEN_B_in; + wire CLKARDCLK_in; + wire CLKBWRCLK_in; + wire ECCPIPECE_in; + wire ENARDEN_in; + wire ENBWREN_in; + wire INJECTDBITERR_in; + wire INJECTSBITERR_in; + wire REGCEAREGCE_in; + wire REGCEB_in; + wire RSTRAMARSTRAM_in; + wire RSTRAMB_in; + wire RSTREGARSTREG_in; + wire RSTREGB_in; + wire SLEEP_in; + reg [14:0] ADDRARDADDR_in; + reg [14:0] ADDRBWRADDR_in; + wire [31:0] CASDINA_in; + wire [31:0] CASDINB_in; + reg [31:0] DINADIN_in; + reg [31:0] DINBDIN_in; + wire [3:0] CASDINPA_in; + wire [3:0] CASDINPB_in; + reg [3:0] DINPADINP_in; + reg [3:0] DINPBDINP_in; + wire [3:0] WEA_in; + wire [7:0] WEBWE_in; + +`ifdef XIL_TIMING + wire ADDRENA_delay; + wire ADDRENB_delay; + wire CASDIMUXA_delay; + wire CASDIMUXB_delay; + wire CASDOMUXA_delay; + wire CASDOMUXB_delay; + wire CASDOMUXEN_A_delay; + wire CASDOMUXEN_B_delay; + wire CASINDBITERR_delay; + wire CASINSBITERR_delay; + wire CASOREGIMUXA_delay; + wire CASOREGIMUXB_delay; + wire CASOREGIMUXEN_A_delay; + wire CASOREGIMUXEN_B_delay; + wire CLKARDCLK_delay; + wire CLKBWRCLK_delay; + wire ECCPIPECE_delay; + wire ENARDEN_delay; + wire ENBWREN_delay; + wire INJECTDBITERR_delay; + wire INJECTSBITERR_delay; + wire REGCEAREGCE_delay; + wire REGCEB_delay; + wire RSTRAMARSTRAM_delay; + wire RSTRAMB_delay; + wire RSTREGARSTREG_delay; + wire RSTREGB_delay; + wire SLEEP_delay; + wire [14:0] ADDRARDADDR_delay; + wire [14:0] ADDRBWRADDR_delay; + wire [31:0] CASDINA_delay; + wire [31:0] CASDINB_delay; + wire [31:0] DINADIN_delay; + wire [31:0] DINBDIN_delay; + wire [3:0] CASDINPA_delay; + wire [3:0] CASDINPB_delay; + wire [3:0] DINPADINP_delay; + wire [3:0] DINPBDINP_delay; + wire [3:0] WEA_delay; + wire [7:0] WEBWE_delay; +`endif + + assign CASDOUTA = CASDOUTA_out; + assign CASDOUTB = CASDOUTB_out; + assign CASDOUTPA = CASDOUTPA_out; + assign CASDOUTPB = CASDOUTPB_out; + assign CASOUTDBITERR = CASOUTDBITERR_out; + assign CASOUTSBITERR = CASOUTSBITERR_out; + assign DBITERR = DBITERR_out; + assign DOUTADOUT = DOUTADOUT_out; + assign DOUTBDOUT = DOUTBDOUT_out; + assign DOUTPADOUTP = DOUTPADOUTP_out; + assign DOUTPBDOUTP = DOUTPBDOUTP_out; + assign ECCPARITY = ECCPARITY_out; + assign RDADDRECC = RDADDRECC_out; + assign SBITERR = SBITERR_out; + +`ifdef XIL_TIMING + always @ (*) ADDRARDADDR_in = ADDRARDADDR_delay; + always @ (*) ADDRBWRADDR_in = ADDRBWRADDR_delay; + assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA_delay; // rv 1 + assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB_delay; // rv 1 + assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA_delay; // rv 0 + assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB_delay; // rv 0 + assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA_delay[0]; // rv 0 + assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA_delay[10]; // rv 0 + assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA_delay[11]; // rv 0 + assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA_delay[12]; // rv 0 + assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA_delay[13]; // rv 0 + assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA_delay[14]; // rv 0 + assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA_delay[15]; // rv 0 + assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA_delay[16]; // rv 0 + assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA_delay[17]; // rv 0 + assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA_delay[18]; // rv 0 + assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA_delay[19]; // rv 0 + assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA_delay[1]; // rv 0 + assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA_delay[20]; // rv 0 + assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA_delay[21]; // rv 0 + assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA_delay[22]; // rv 0 + assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA_delay[23]; // rv 0 + assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA_delay[24]; // rv 0 + assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA_delay[25]; // rv 0 + assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA_delay[26]; // rv 0 + assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA_delay[27]; // rv 0 + assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA_delay[28]; // rv 0 + assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA_delay[29]; // rv 0 + assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA_delay[2]; // rv 0 + assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA_delay[30]; // rv 0 + assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA_delay[31]; // rv 0 + assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA_delay[3]; // rv 0 + assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA_delay[4]; // rv 0 + assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA_delay[5]; // rv 0 + assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA_delay[6]; // rv 0 + assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA_delay[7]; // rv 0 + assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA_delay[8]; // rv 0 + assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA_delay[9]; // rv 0 + assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB_delay[0]; // rv 0 + assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB_delay[10]; // rv 0 + assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB_delay[11]; // rv 0 + assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB_delay[12]; // rv 0 + assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB_delay[13]; // rv 0 + assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB_delay[14]; // rv 0 + assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB_delay[15]; // rv 0 + assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB_delay[16]; // rv 0 + assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB_delay[17]; // rv 0 + assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB_delay[18]; // rv 0 + assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB_delay[19]; // rv 0 + assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB_delay[1]; // rv 0 + assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB_delay[20]; // rv 0 + assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB_delay[21]; // rv 0 + assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB_delay[22]; // rv 0 + assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB_delay[23]; // rv 0 + assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB_delay[24]; // rv 0 + assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB_delay[25]; // rv 0 + assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB_delay[26]; // rv 0 + assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB_delay[27]; // rv 0 + assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB_delay[28]; // rv 0 + assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB_delay[29]; // rv 0 + assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB_delay[2]; // rv 0 + assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB_delay[30]; // rv 0 + assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB_delay[31]; // rv 0 + assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB_delay[3]; // rv 0 + assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB_delay[4]; // rv 0 + assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB_delay[5]; // rv 0 + assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB_delay[6]; // rv 0 + assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB_delay[7]; // rv 0 + assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB_delay[8]; // rv 0 + assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB_delay[9]; // rv 0 + assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA_delay[0]; // rv 0 + assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA_delay[1]; // rv 0 + assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA_delay[2]; // rv 0 + assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA_delay[3]; // rv 0 + assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB_delay[0]; // rv 0 + assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB_delay[1]; // rv 0 + assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB_delay[2]; // rv 0 + assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB_delay[3]; // rv 0 + assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA_delay; // rv 0 + assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB_delay; // rv 0 + assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A_delay; // rv 1 + assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B_delay; // rv 1 + assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR_delay; // rv 0 + assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR_delay; // rv 0 + assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA_delay; // rv 0 + assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB_delay; // rv 0 + assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A_delay; // rv 1 + assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B_delay; // rv 1 + assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0 + assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0 + always @ (*) DINADIN_in = DINADIN_delay; + always @ (*) DINBDIN_in = DINBDIN_delay; + always @ (*) DINPADINP_in = DINPADINP_delay; + always @ (*) DINPBDINP_in = DINPBDINP_delay; + assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE_delay; // rv 1 + assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN); // rv 0 + assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN); // rv 0 + assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR_delay; // rv 0 + assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR_delay; // rv 0 + assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE_delay; // rv 1 + assign REGCEB_in = (REGCEB === 1'bz) || REGCEB_delay; // rv 1 + assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0 + assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN); // rv 0 + assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0 + assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 + assign WEA_in[0] = (WEA[0] === 1'bz) || WEA_delay[0]; // rv 1 + assign WEA_in[1] = (WEA[1] === 1'bz) || WEA_delay[1]; // rv 1 + assign WEA_in[2] = (WEA[2] === 1'bz) || WEA_delay[2]; // rv 1 + assign WEA_in[3] = (WEA[3] === 1'bz) || WEA_delay[3]; // rv 1 + assign WEBWE_in = WEBWE_delay; +`else + always @ (*) ADDRARDADDR_in = ADDRARDADDR; + always @ (*) ADDRBWRADDR_in = ADDRBWRADDR; + assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA; // rv 1 + assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB; // rv 1 + assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA; // rv 0 + assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB; // rv 0 + assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA[0]; // rv 0 + assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA[10]; // rv 0 + assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA[11]; // rv 0 + assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA[12]; // rv 0 + assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA[13]; // rv 0 + assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA[14]; // rv 0 + assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA[15]; // rv 0 + assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA[16]; // rv 0 + assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA[17]; // rv 0 + assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA[18]; // rv 0 + assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA[19]; // rv 0 + assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA[1]; // rv 0 + assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA[20]; // rv 0 + assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA[21]; // rv 0 + assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA[22]; // rv 0 + assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA[23]; // rv 0 + assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA[24]; // rv 0 + assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA[25]; // rv 0 + assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA[26]; // rv 0 + assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA[27]; // rv 0 + assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA[28]; // rv 0 + assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA[29]; // rv 0 + assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA[2]; // rv 0 + assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA[30]; // rv 0 + assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA[31]; // rv 0 + assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA[3]; // rv 0 + assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA[4]; // rv 0 + assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA[5]; // rv 0 + assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA[6]; // rv 0 + assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA[7]; // rv 0 + assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA[8]; // rv 0 + assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA[9]; // rv 0 + assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB[0]; // rv 0 + assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB[10]; // rv 0 + assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB[11]; // rv 0 + assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB[12]; // rv 0 + assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB[13]; // rv 0 + assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB[14]; // rv 0 + assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB[15]; // rv 0 + assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB[16]; // rv 0 + assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB[17]; // rv 0 + assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB[18]; // rv 0 + assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB[19]; // rv 0 + assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB[1]; // rv 0 + assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB[20]; // rv 0 + assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB[21]; // rv 0 + assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB[22]; // rv 0 + assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB[23]; // rv 0 + assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB[24]; // rv 0 + assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB[25]; // rv 0 + assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB[26]; // rv 0 + assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB[27]; // rv 0 + assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB[28]; // rv 0 + assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB[29]; // rv 0 + assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB[2]; // rv 0 + assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB[30]; // rv 0 + assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB[31]; // rv 0 + assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB[3]; // rv 0 + assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB[4]; // rv 0 + assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB[5]; // rv 0 + assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB[6]; // rv 0 + assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB[7]; // rv 0 + assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB[8]; // rv 0 + assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB[9]; // rv 0 + assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA[0]; // rv 0 + assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA[1]; // rv 0 + assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA[2]; // rv 0 + assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA[3]; // rv 0 + assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB[0]; // rv 0 + assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB[1]; // rv 0 + assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB[2]; // rv 0 + assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB[3]; // rv 0 + assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA; // rv 0 + assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB; // rv 0 + assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A; // rv 1 + assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B; // rv 1 + assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR; // rv 0 + assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR; // rv 0 + assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA; // rv 0 + assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB; // rv 0 + assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A; // rv 1 + assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B; // rv 1 + assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0 + assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0 +// always @ (CLKARDCLK) begin +// if ((CLKARDCLK === 1'bz) || // rv 0 +// (CLKARDCLK === IS_CLKARDCLK_INVERTED_BIN)) CLKARDCLK_in = 1'b0; +// else CLKARDCLK_in = 1'b1; +// end +// always @ (CLKBWRCLK) begin +// if ((CLKBWRCLK === 1'bz) || // rv 0 +// (CLKBWRCLK === IS_CLKBWRCLK_INVERTED_BIN)) CLKBWRCLK_in = 1'b0; +// else CLKBWRCLK_in = 1'b1; +// end + always @ (*) DINADIN_in = DINADIN; + always @ (*) DINBDIN_in = DINBDIN; + always @ (*) DINPADINP_in = DINPADINP; + always @ (*) DINPBDINP_in = DINPBDINP; + assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE; // rv 1 + assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN ^ IS_ENARDEN_INVERTED_BIN); // rv 0 + assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN ^ IS_ENBWREN_INVERTED_BIN); // rv 0 + assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR; // rv 0 + assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR; // rv 0 + assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE; // rv 1 + assign REGCEB_in = (REGCEB === 1'bz) || REGCEB; // rv 1 + assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0 + assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB ^ IS_RSTRAMB_INVERTED_BIN); // rv 0 + assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0 + assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB ^ IS_RSTREGB_INVERTED_BIN); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 + assign WEA_in[0] = (WEA[0] === 1'bz) || WEA[0]; // rv 1 + assign WEA_in[1] = (WEA[1] === 1'bz) || WEA[1]; // rv 1 + assign WEA_in[2] = (WEA[2] === 1'bz) || WEA[2]; // rv 1 + assign WEA_in[3] = (WEA[3] === 1'bz) || WEA[3]; // rv 1 + assign WEBWE_in = WEBWE; +`endif + +// internal variables, signals, busses + localparam integer ADDR_WIDTH = 15; + localparam integer INIT_WIDTH = 72; + localparam integer D_WIDTH = 64; + localparam integer DP_WIDTH = 8; + + localparam mem_width = 1; + localparam memp_width = 1; + localparam mem_size = 32768; + localparam mem_depth = mem_size; + localparam memp_depth = mem_size/8; + localparam mem_pad = 64; + localparam memp_pad = 8; + localparam encode = 1'b1; + localparam decode = 1'b0; +//localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : READ_WIDTH_B; + localparam tmp_mem_width = (READ_WIDTH_A >= READ_WIDTH_B) ? ((READ_WIDTH_A == 0) ? 1 : READ_WIDTH_A) : + READ_WIDTH_B; + localparam tmp_memp_width = (tmp_mem_width < 9) ? 0 : + (tmp_mem_width < 18) ? 1 : + (tmp_mem_width < 36) ? 2 : + (tmp_mem_width < 72) ? 4 : 8; + localparam tmp_mem_depth = mem_size/(tmp_mem_width-tmp_memp_width); + reg [tmp_mem_width-1:0] tmp_mem_tmp = 0; + integer t_coll_min = 50; + integer t_coll_max = 500 - 99; + reg [255:0] INITP_TMP; + reg [255:0] INIT_TMP; + integer i=0; + integer j=0; + integer k=0; + integer ra=0; + integer raa=0; + integer raw=0; + integer wb=0; + integer rb=0; + integer rbb=0; + integer rbw=0; + integer wa=0; + integer rd_loops_a = 1; + integer wr_loops_a = 1; + integer rd_loops_b = 1; + integer rd_loops_f = 1; + integer wr_loops_b = 1; + localparam max_rd_loops = D_WIDTH; + localparam max_wr_loops = D_WIDTH; + wire WREN_ecc; + wire SLEEP_A_int; + wire SLEEP_B_int; + reg [1:0] SLEEP_A_reg = 2'b0; + reg [1:0] SLEEP_B_reg = 2'b0; + wire RSTREG_A_int; + wire REGCE_A_int; + wire ADDRENA_int; + wire ADDRENB_int; + wire RSTREG_B_int; + wire REGCE_B_int; + reg CASDOMUXA_reg = 1'b0; + reg CASOREGIMUXA_reg = 1'b0; + reg CASDOMUXB_reg = 1'b0; + reg CASOREGIMUXB_reg = 1'b0; + wire CASDOMUXB_int; + wire INJECTDBITERR_int; + wire INJECTSBITERR_int; + reg [6:0] error_bit = 7'b0; + reg [DP_WIDTH-1:0] eccparity_reg = 8'h00; + wire [INIT_WIDTH-1:0] INIT_A_int; + wire [INIT_WIDTH-1:0] SRVAL_A_int; + wire [INIT_WIDTH/2-1:0] INIT_B_int; + wire [INIT_WIDTH/2-1:0] SRVAL_B_int; + + wire mem_wr_en_a; + reg mem_wr_en_a_wf = 1'b0; + reg [D_WIDTH/2-1:0] mem_we_a; + reg [DP_WIDTH/2-1:0] memp_we_a; + wire [D_WIDTH/2-1:0] mem_rm_doutb; + wire [DP_WIDTH/2-1:0] memp_rm_doutb; + wire [D_WIDTH-1:0] mem_rm_a; + wire [D_WIDTH-1:0] mem_rm_b; + wire [D_WIDTH-1:0] mem_wm_a; + wire [D_WIDTH-1:0] mem_wm_b; + reg wr_data_matches = 0; + reg wr_a_data_matches_rd_b_data = 0; + reg wr_b_data_matches_rd_a_data = 0; + wire mem_wr_en_b; + reg mem_wr_en_b_wf = 1'b0; + reg [D_WIDTH-1:0] mem_we_b; + reg [DP_WIDTH-1:0] memp_we_b; + wire [D_WIDTH-1:0] mem_rm_douta; + wire [DP_WIDTH-1:0] memp_rm_douta; + wire mem_rd_en_a; + wire mem_rst_a; + reg mem_is_rst_a = 1'b0; + reg first_read = 1'b0; + wire mem_rd_en_b; + wire mem_rst_b; + reg mem_is_rst_b = 1'b0; + + reg mem [0 : mem_depth+mem_pad-1]; + reg [D_WIDTH/2-1 : 0] mem_wr_a; + reg wr_a_event = 1'b0; + reg wr_a_wf_event = 1'b0; + reg [D_WIDTH-1 : 0] ram_rd_a; + reg [D_WIDTH-1 : 0] mem_rd_a_wf; + reg [D_WIDTH-1 : 0] mem_wr_b; + reg wr_b_event = 1'b0; + reg wr_b_wf_event = 1'b0; + reg [D_WIDTH-1 : 0] mem_rd_b; + reg [D_WIDTH-1 : 0] mem_rd_b_rf; + reg [D_WIDTH-1 : 0] mem_rd_b_wf; + reg [D_WIDTH-1 : 0] mem_a_reg; + reg [D_WIDTH-1 : 0] mem_a_reg_mux; + reg [D_WIDTH-1 : 0] mem_a_lat; + reg [D_WIDTH-1 : 0] mem_a_pipe; + reg [D_WIDTH/2-1 : 0] mem_b_reg; + reg [D_WIDTH/2-1 : 0] mem_b_reg_mux; + reg [D_WIDTH/2-1 : 0] mem_b_lat; + reg memp [0 : memp_depth+memp_pad-1]; + reg [DP_WIDTH-1 : 0] memp_wr_a; + reg [DP_WIDTH-1 : 0] ramp_rd_a; + reg [DP_WIDTH-1 : 0] memp_rd_a_wf; + reg [DP_WIDTH-1 : 0] memp_wr_b; + reg [DP_WIDTH-1 : 0] memp_rd_b; + reg [DP_WIDTH-1 : 0] memp_rd_b_rf; + reg [DP_WIDTH-1 : 0] memp_rd_b_wf; + reg [DP_WIDTH-1 : 0] memp_a_reg; + reg [DP_WIDTH-1 : 0] memp_a_reg_mux; + reg [DP_WIDTH-1 : 0] memp_a_lat; + reg [DP_WIDTH-1 : 0] memp_a_out; + reg [DP_WIDTH-1 : 0] memp_a_pipe; + reg [DP_WIDTH/2-1 : 0] memp_b_reg; + reg [DP_WIDTH/2-1 : 0] memp_b_reg_mux; + reg [DP_WIDTH/2-1 : 0] memp_b_lat; + reg [DP_WIDTH/2-1 : 0] memp_b_out; + wire dbit_int; + wire sbit_int; + reg dbit_lat = 0; + reg sbit_lat = 0; + reg dbit_pipe = 0; + reg sbit_pipe = 0; + reg dbit_reg = 0; + reg sbit_reg = 0; + wire [8:0] r_a_ecc_ecc; + reg [8:0] r_a_ecc_lat = 9'b0; + reg [8:0] r_a_ecc_pipe = 9'b0; + reg [8:0] r_a_ecc_reg = 9'b0; + reg dbit_ecc; + reg sbit_ecc; + wire [ADDR_WIDTH-1:0] rd_addr_a_mask; + wire [ADDR_WIDTH-1:0] rd_addr_b_mask; + wire [ADDR_WIDTH-1:0] wr_addr_a_mask; + wire [ADDR_WIDTH-1:0] wr_addr_b_mask; + reg [ADDR_WIDTH-1:0] rd_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_a_last = 0; + reg [ADDR_WIDTH-1:0] rd_addr_a_last = 0; + reg rd_addr_a_valid = 0; + reg rd_addr_a_nochange = 0; + reg [63:0] rd_addr_a_count = 0; + reg [63:0] rd_addr_a_nocount = 0; + reg [ADDR_WIDTH-1:0] rd_addr_b = 0; + reg [ADDR_WIDTH-1:0] wr_addr_a = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b_last = 0; + reg [ADDR_WIDTH-1:0] rd_addr_b_last = 0; + reg rd_addr_b_valid = 0; + reg rd_addr_b_nochange = 0; + reg [63:0] rd_addr_b_count = 0; + reg [63:0] rd_addr_b_nocount = 0; + reg [ADDR_WIDTH-1:0] wr_addr_b = 0; + reg wr_a_rd_b_addr_coll = 1'b0; + reg wr_addr_coll = 1'b0; + reg wr_b_rd_a_addr_coll = 1'b0; + reg [7:0] synd_wr; + reg [7:0] synd_rd; + reg [7:0] synd_ecc; + + wire sdp_mode; + wire sdp_mode_wr; + wire sdp_mode_rd; + +// clk period for collision window variables +integer t_max_a=3000, t_max_b=3000; +integer clk_period_a=10000, clk_period_b=10000; +reg clk_a_slowest = 1'b0; //victor drc +reg [63:0] total_clks_a=1, total_clks_b=1; +reg clka_toggled=1'b0, clkb_toggled=1'b0; +reg clka_done=1'b0, clkb_done=1'b0; +reg clka_timeout=0, clkb_timeout=0; +reg clka_changed = 1'b0; +reg clkb_changed = 1'b0; +wire clks_done; +reg en_clk_sync = 1'b0; + +// define tasks, functions + +function [7:0] fn_ecc ( + input encode, + input [63:0] d_i, + input [7:0] dp_i + ); + reg ecc_7; +begin + fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^ + d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^ + d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^ + d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^ + d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^ + d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^ + d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63]; + + fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^ + d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^ + d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^ + d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^ + d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^ + d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^ + d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63]; + + fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ + d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^ + d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ + d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ + d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ + d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ + d_i[62] ^ d_i[63]; + + ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^ + d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ + d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ + d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ + d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ + d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ + d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ + d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ + d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ + d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ + d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ + d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^ + d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + if (encode) begin + fn_ecc[7] = ecc_7 ^ + fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^ + fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6]; + end + else begin + fn_ecc[7] = ecc_7 ^ + dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^ + dp_i[4] ^ dp_i[5] ^ dp_i[6]; + end +end +endfunction // fn_ecc + +function [71:0] fn_cor_bit ( + input [6:0] error_bit, + input [63:0] d_i, + input [7:0] dp_i + ); + reg [71:0] cor_int; +begin + cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4], + d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0], + dp_i[7]}; + cor_int[error_bit] = ~cor_int[error_bit]; + fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16], + cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65], + cor_int[63:33], cor_int[31:17], cor_int[15:9], + cor_int[7:5], cor_int[3]}; +end +endfunction // fn_cor_bit + +task read_init_file; +reg [tmp_mem_width-1:0] tmp_mem [0:tmp_mem_depth-1]; +integer w,d; +begin + $readmemh (INIT_FILE_REG, tmp_mem); + for (d=0;d 0) begin + for (w=0;w READ_WIDTH_B_BIN) rd_loops_f <= READ_WIDTH_A_BIN; + else rd_loops_f <= READ_WIDTH_B_BIN; + end + always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN; + always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN; + +// determine clk period for collision window. +assign clks_done = clka_done && clkb_done; +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + clka_timeout = 0; + clka_done = 0; + if (glblGSR) @(negedge glblGSR); + @(posedge CLKARDCLK_in); + @(posedge CLKARDCLK_in); + @(posedge CLKARDCLK_in); + clka_timeout <= #6000 1; + @(posedge CLKARDCLK_in or posedge clka_timeout); + if (~clka_timeout) begin + t_max_a = $time/1.0; + @ (negedge CLKARDCLK_in) t_max_a = $time/1.0 - t_max_a; + end else begin + t_max_a = 2000; + end + clka_done = 1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + @(posedge CLKARDCLK_in) + clk_period_a = $time/1.0; + @(posedge CLKARDCLK_in) + clk_period_a = $time/1.0 - clk_period_a; + clka_toggled = 1'b1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + @(posedge CLKBWRCLK_in) + clk_period_b = $time/1.0; + @(posedge CLKBWRCLK_in) + clk_period_b = $time/1.0 - clk_period_b; + clkb_toggled = 1'b1; +end + +//victor drc +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + if (clk_period_a <= clk_period_b) + clk_a_slowest <= 1'b0; + else + clk_a_slowest <= 1'b1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + clkb_timeout = 0; + clkb_done = 0; + if (glblGSR) @(negedge glblGSR); + @(posedge CLKBWRCLK_in); + @(posedge CLKBWRCLK_in); + @(posedge CLKBWRCLK_in); + clkb_timeout <= #6000 1; + @(posedge CLKBWRCLK_in or posedge clkb_timeout); + if (~clkb_timeout) begin + t_max_b = $time; + @ (negedge CLKBWRCLK_in) t_max_b = $time - t_max_b; + end else begin + t_max_b = 2000; + end + clkb_done = 1; +end + +always @(posedge trig_attr or posedge clka_changed or posedge clkb_changed) begin + @(posedge clks_done); + if (((t_max_a > 50) && (t_max_a <= 1500)) && + ((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 99; + if (((t_max_b > 50) && (t_max_b <= 1500)) && + ((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 99; + if ((t_max_a <= 50) && (t_max_b <= 50)) t_coll_max = 500 -99; + if ((t_max_a > 1500) && (t_max_b > 1500)) t_coll_max = 3000 -99; +end + + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) begin + SLEEP_A_reg <= 2'b0; + end + else begin + SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in}; + end + end + + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR) begin + SLEEP_B_reg <= 2'b0; + end + else begin + SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in}; + end + end + + assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in; + assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in; + + assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? 1'b1 : 1'b0; + assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ? 1'b1 : 1'b0; + assign sdp_mode = sdp_mode_rd || sdp_mode_wr; + assign REGCE_A_int = REGCEAREGCE_in; + assign REGCE_B_int = REGCEB_in; + assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ? + RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in); + assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ? + RSTREGB_in : (RSTREGB_in && REGCEB_in); + assign ADDRENA_int = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_in : 1'b1; + assign ADDRENB_int = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_in : 1'b1; + assign WREN_ecc = ECCPIPECE_in && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && first_read; + assign ECCPARITY_out = eccparity_reg; + assign RDADDRECC_out = (DOA_REG_BIN == DOA_REG_1) ? r_a_ecc_reg : r_a_ecc_ecc; + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin + SBITERR_out = CASINSBITERR_in; + DBITERR_out = CASINDBITERR_in; + end + else if (DOA_REG_BIN == DOA_REG_1) begin + SBITERR_out = sbit_reg; + DBITERR_out = dbit_reg; + end + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin + SBITERR_out = sbit_pipe; + DBITERR_out = dbit_pipe; + end + else begin + SBITERR_out = sbit_lat; + DBITERR_out = dbit_lat; + end + end + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin + DOUTADOUT_out = CASDINA_in; + DOUTPADOUTP_out = CASDINPA_in; + end + else if (DOA_REG_BIN == DOA_REG_1) begin + DOUTADOUT_out = mem_a_reg ^ mem_rm_douta; + DOUTPADOUTP_out = memp_a_reg ^ memp_rm_douta; + end + else if (mem_wr_en_a_wf) begin + DOUTADOUT_out = mem_rd_a_wf ^ mem_rm_douta; + DOUTPADOUTP_out = memp_rd_a_wf ^ memp_rm_douta; + end + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin + DOUTADOUT_out = mem_a_pipe ^ mem_rm_douta; + DOUTPADOUTP_out = memp_a_pipe ^ memp_rm_douta; + end + else begin + DOUTADOUT_out = mem_a_lat ^ mem_rm_douta; + DOUTPADOUTP_out = memp_a_lat ^ memp_rm_douta; + end + end + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDOMUXB_int) begin + DOUTBDOUT_out = CASDINB_in; + DOUTPBDOUTP_out = CASDINPB_in; + end + else if (sdp_mode_rd) begin + if (DOA_REG_BIN == DOA_REG_1) begin + DOUTBDOUT_out = mem_a_reg[63:32] ^ mem_rm_douta[63:32]; + DOUTPBDOUTP_out = memp_a_reg[7:4] ^ memp_rm_douta[7:4]; + end + else if (mem_wr_en_a_wf) begin + DOUTBDOUT_out = mem_rd_a_wf[63:32] ^ mem_rm_douta[63:32]; + DOUTPBDOUTP_out = memp_rd_a_wf[7:4] ^ memp_rm_douta[7:4]; + end + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin + DOUTBDOUT_out = mem_a_pipe[63:32] ^ mem_rm_douta[63:32]; + DOUTPBDOUTP_out = memp_a_pipe[7:4] ^ memp_rm_douta[7:4]; + end + else begin + DOUTBDOUT_out = mem_a_lat[63:32] ^ mem_rm_douta[63:32]; + DOUTPBDOUTP_out = memp_a_lat[7:4] ^ memp_rm_douta[7:4]; + end + end + else begin + if (DOB_REG_BIN == DOB_REG_1) begin + DOUTBDOUT_out = mem_b_reg ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_b_reg ^ memp_rm_doutb; + end + else if (mem_wr_en_b_wf) begin + DOUTBDOUT_out = mem_rd_b_wf ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_rd_b_wf ^ memp_rm_doutb; + end + else begin + DOUTBDOUT_out = mem_b_lat ^ mem_rm_doutb; + DOUTPBDOUTP_out = memp_b_lat ^ memp_rm_doutb; + end + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) dbit_ecc = CASINDBITERR_in; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) dbit_ecc = dbit_pipe; + else dbit_ecc = dbit_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) sbit_ecc = CASINSBITERR_in; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) sbit_ecc = sbit_pipe; + else sbit_ecc = sbit_lat; + end + assign r_a_ecc_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? r_a_ecc_pipe : r_a_ecc_lat; + assign INIT_A_int = + (READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{INIT_A_BIN[8]}}, {8{INIT_A_BIN[7:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{INIT_A_BIN[17:16]}}, {4{INIT_A_BIN[15:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{INIT_A_BIN[35:32]}}, {2{INIT_A_BIN[31:0]}}} : + {INIT_B_BIN[35:32],INIT_A_BIN[35:32],INIT_B_BIN[31:0],INIT_A_BIN[31:0]}; + + assign INIT_B_int = + (READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{INIT_B_BIN[8]}}, {4{INIT_B_BIN[7:0]}}} : + (READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{INIT_B_BIN[17:16]}}, {2{INIT_B_BIN[15:0]}}} : + INIT_B_BIN; + + assign SRVAL_A_int = + (READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{SRVAL_A_BIN[8]}}, {8{SRVAL_A_BIN[7:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{SRVAL_A_BIN[17:16]}}, {4{SRVAL_A_BIN[15:0]}}} : + (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{SRVAL_A_BIN[35:32]}}, {2{SRVAL_A_BIN[31:0]}}} : + {SRVAL_B_BIN[35:32],SRVAL_A_BIN[35:32],SRVAL_B_BIN[31:0],SRVAL_A_BIN[31:0]}; + assign SRVAL_B_int = + (READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{SRVAL_B_BIN[8]}}, {4{SRVAL_B_BIN[7:0]}}} : + (READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{SRVAL_B_BIN[17:16]}}, {2{SRVAL_B_BIN[15:0]}}} : + SRVAL_B_BIN; +// cascade out + assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + DOUTADOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}}; + assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ? + DOUTBDOUT_out : {D_WIDTH-1{1'b0}}; + assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ? + DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}}; + assign CASOUTDBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + DBITERR_out : 1'b0; + assign CASOUTSBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ? + SBITERR_out : 1'b0; +// start model internals + +// cascade control + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) CASDOMUXA_reg <= 1'b0; + else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in; + end + + always @ (posedge CLKARDCLK_in) begin + if (glblGSR) CASOREGIMUXA_reg <= 1'b0; + else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in; + end + + assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ? + CASDOMUXA_reg : CASDOMUXB_reg; + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR || sdp_mode) CASDOMUXB_reg <= 1'b0; + else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in; + end + + always @ (posedge CLKBWRCLK_in) begin + if (glblGSR || sdp_mode) CASOREGIMUXB_reg <= 1'b0; + else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in; + end + +// collison detection +reg coll_win_wr_clk_a_min = 1'b0; +reg coll_win_wr_clk_b_min = 1'b0; +reg coll_win_rd_clk_a_min = 1'b0; +reg coll_win_rd_clk_b_min = 1'b0; +reg coll_win_wr_clk_a_max = 1'b0; +reg coll_win_wr_clk_b_max = 1'b0; +reg coll_win_rd_clk_a_max = 1'b0; +reg coll_win_rd_clk_b_max = 1'b0; +reg wr_b_wr_a_coll = 1'b0; +reg wr_b_rd_a_coll = 1'b0; +reg rd_b_wr_a_coll = 1'b0; +reg wr_a_wr_b_coll = 1'b0; +reg wr_a_rd_b_coll = 1'b0; +reg rd_a_wr_b_coll = 1'b0; + +wire coll_wr_sim; +wire coll_wr_b_wr_a; +wire coll_wr_b_rd_a_sim; +wire coll_wr_b_rd_a; +//wire coll_rd_b_wr_a_sim; +wire coll_rd_b_wr_a; +wire coll_wr_a_wr_b; +wire coll_wr_a_rd_b_sim; +wire coll_wr_a_rd_b; +//wire coll_rd_a_wr_b_sim; +wire coll_rd_a_wr_b; + +assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min; +assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max; +assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min; +//assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min; +assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min; +//assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min; +assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max; +assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max; +assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max; +assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max; +assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max; + +always @(posedge CLKARDCLK_in) begin + if (mem_wr_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) & ~sdp_mode) begin + if (coll_win_wr_clk_a_max) begin + coll_win_wr_clk_a_max = 1'b0; + if (clks_done) clka_changed = 1'b1; + end else if (clks_done) begin + clka_changed = 1'b0; + coll_win_wr_clk_a_min <= #1 1'b1; + coll_win_wr_clk_a_max <= #99 1'b1; + coll_win_wr_clk_a_min <= #(t_coll_min) 1'b0; + coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0; + end + end +end + +always @(posedge coll_wr_sim) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-1] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b); + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-2] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_wr_b) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-3] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last); + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-4] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_wr_b_coll <= #10 1'b1; + wr_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_rd_b_sim) begin + if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-5] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) and a READ on port B (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b); + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-6] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b); + else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_a_rd_b) begin + if (~wr_a_data_matches_rd_b_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-7] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last); + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-8] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_a_rd_b_coll <= #10 1'b1; + wr_a_rd_b_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKBWRCLK_in) begin + if (mem_wr_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if (coll_win_wr_clk_b_max) begin + coll_win_wr_clk_b_max = 1'b0; + if (clks_done) clkb_changed = 1'b1; + end else if (clks_done) begin + clkb_changed = 1'b0; + coll_win_wr_clk_b_min <= #1 1'b1; + coll_win_wr_clk_b_max <= #99 1'b1; + coll_win_wr_clk_b_min <= #(t_coll_min) 1'b0; + coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0; + end + end +end + + +always @(posedge coll_wr_b_wr_a) begin + if (~wr_data_matches) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-9] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last); + wr_b_wr_a_coll <= #10 1'b1; + wr_b_wr_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-10] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_wr_a_coll <= #10 1'b1; + wr_b_wr_a_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_b_rd_a_sim) begin + if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-11] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) and READ on port A (%h) occured.\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a); + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-12] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a); + else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + end +end + +always @(posedge coll_wr_b_rd_a) begin + if (~wr_b_data_matches_rd_a_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-13] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last); + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-14] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + wr_b_rd_a_coll <= #10 1'b1; + wr_b_rd_a_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKARDCLK_in) begin + if (mem_rd_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if (coll_win_rd_clk_a_max) begin + coll_win_rd_clk_a_max = 1'b0; + if (clks_done) clka_changed = 1'b1; + end else if (clks_done) begin + clka_changed = 1'b0; + coll_win_rd_clk_a_min <= #1 1'b1; + coll_win_rd_clk_a_max <= #99 1'b1; + coll_win_rd_clk_a_min <= #(t_coll_min) 1'b0; + coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0; + end + end +end + +//always @(posedge coll_rd_a_wr_b_sim) begin +// if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin +// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin +// $display("Error: [Unisim %s-15] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b); +// rd_a_wr_b_coll <= #10 1'b1; +// rd_a_wr_b_coll <= #100 1'b0; +// end +// else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) +// $display("Error: [Unisim %s-16] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b); +// if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin +// rd_a_wr_b_coll <= #10 1'b1; +// rd_a_wr_b_coll <= #100 1'b0; +// end +// end +//end + +always @(posedge coll_rd_a_wr_b) begin + if (~wr_b_data_matches_rd_a_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-17] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last); + rd_a_wr_b_coll <= #10 1'b1; + rd_a_wr_b_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-18] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + rd_a_wr_b_coll <= #10 1'b1; + rd_a_wr_b_coll <= #100 1'b0; + end + end +end + +always @(posedge CLKBWRCLK_in) begin + if (mem_rd_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) && ~sdp_mode) begin + if (coll_win_rd_clk_b_max) begin + coll_win_rd_clk_b_max = 1'b0; + if (clks_done) clkb_changed = 1'b1; + end else if (clks_done) begin + clkb_changed = 1'b0; + coll_win_rd_clk_b_min <= #1 1'b1; + coll_win_rd_clk_b_max <= #99 1'b1; + coll_win_rd_clk_b_min <= #(t_coll_min) 1'b0; + coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0; + end + end +end + + +always @(posedge coll_rd_b_wr_a) begin + if (~wr_a_data_matches_rd_b_data) begin + if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin + $display("Error: [Unisim %s-21] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last); + rd_b_wr_a_coll <= #10 1'b1; + rd_b_wr_a_coll <= #100 1'b0; + end + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY) + $display("Error: [Unisim %s-22] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a_last); + else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin + rd_b_wr_a_coll <= #10 1'b1; + rd_b_wr_a_coll <= #100 1'b0; + end + end +end + +// output register + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) mem_a_reg_mux = {CASDINB_in, CASDINA_in}; + else if (mem_wr_en_a_wf) mem_a_reg_mux = mem_rd_a_wf; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) mem_a_reg_mux = mem_a_pipe; + else mem_a_reg_mux = mem_a_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && + CASOREGIMUXA_reg) memp_a_reg_mux = {CASDINPB_in, CASDINPA_in}; + else if (mem_wr_en_a_wf) memp_a_reg_mux = memp_rd_a_wf; + else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) memp_a_reg_mux = memp_a_pipe; + else memp_a_reg_mux = memp_a_lat; + end + + always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_reg, mem_a_reg} <= #100 INIT_A_int; + end + else if (RSTREG_A_int) begin + {memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int; + end + else if (REGCE_A_int) begin + mem_a_reg <= #100 mem_a_reg_mux; + memp_a_reg <= #100 memp_a_reg_mux; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && + CASOREGIMUXB_reg) mem_b_reg_mux = CASDINB_in; + else if (mem_wr_en_b_wf) mem_b_reg_mux = mem_rd_b_wf; + else mem_b_reg_mux = mem_b_lat; + end + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && + CASOREGIMUXB_reg) memp_b_reg_mux = CASDINPB_in; + else if (mem_wr_en_b_wf) memp_b_reg_mux = memp_rd_b_wf; + else memp_b_reg_mux = memp_b_lat; + end + always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM || sdp_mode) begin + {memp_b_reg, mem_b_reg} <= #100 INIT_B_int; + end + else if (RSTREG_B_int) begin + {memp_b_reg, mem_b_reg} <= #100 SRVAL_B_int; + end + else if (REGCE_B_int) begin + mem_b_reg <= #100 mem_b_reg_mux; + memp_b_reg <= #100 memp_b_reg_mux; + end + end + +// bit err reg + always @ (posedge CLKARDCLK_in or glblGSR) begin + if (glblGSR || mem_rst_a) begin + dbit_reg <= 1'b0; + sbit_reg <= 1'b0; + r_a_ecc_reg <= 9'h0; + end + else if (REGCE_A_int) begin + dbit_reg <= dbit_ecc; + sbit_reg <= sbit_ecc; + r_a_ecc_reg <= r_a_ecc_ecc; + end + end + +// ecc pipe register + always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin + if (glblGSR || INIT_MEM) begin + {memp_a_pipe, mem_a_pipe} <= #100 INIT_A_int; + dbit_pipe <= #100 1'b0; + sbit_pipe <= #100 1'b0; + r_a_ecc_pipe <= #100 9'b0; + end + else if (WREN_ecc) begin + mem_a_pipe <= #100 mem_a_lat; + memp_a_pipe <= #100 memp_a_lat; + dbit_pipe <= #100 dbit_lat; + sbit_pipe <= #100 sbit_lat; + r_a_ecc_pipe <= #100 r_a_ecc_lat; + end + end + +// read engine + always @ (posedge CLKARDCLK_in) begin + if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && ~sdp_mode && mem_rd_en_a && ~glblGSR) begin + mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a; + end + end + + always @ (posedge CLKBWRCLK_in) begin + if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b && ~glblGSR) begin + mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b; + end + end + + always @ (wr_a_wf_event or INIT_MEM) begin + if (coll_wr_sim || coll_wr_b_wr_a || coll_wr_a_wr_b) begin + for (raw=0;raw= 8) begin + for (raw=0;raw= 8) begin + for (raw=0;raw= 8) begin + for (raa=0;raa> ra; + if (ra> (D_WIDTH+ra); + end + end + first_read <= 1'b0; + end + else if (SLEEP_A_int && mem_rd_en_a) begin + $display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_a <= 1'b0; + for (ra=0;ra> ra; + if (ra> (D_WIDTH+ra); + end + end + end + end + else if (rd_a_wr_b_coll || wr_b_rd_a_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin + if (~wr_b_data_matches_rd_a_data && + ((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) || + (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin + mem_is_rst_a <= 1'b0; + for (ra=0;ra= 8) begin + for (rbw=0;rbw> rb; + if (rb> (D_WIDTH/2+rb); + end + end + end + else if (SLEEP_B_int && mem_rd_en_b && ~sdp_mode) begin + $display("Error: [Unisim %s-24] DRC : READ on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0); + mem_is_rst_b <= 1'b0; + for (rb=0;rb> rb; + if (rb> (D_WIDTH/2+rb); + end + end + end + end + else if (rd_b_wr_a_coll || wr_a_rd_b_coll || wr_a_wr_b_coll || wr_b_wr_a_coll) begin + mem_is_rst_b <= 1'b0; + if (~wr_a_data_matches_rd_b_data && + ((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) || + (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin + for (rb=0;rb= 8) begin + for (wa=0;wa WRITE_WIDTH_B_4) begin + for (wb=0;wb>(max_rd_loops-rd_loops_a); + assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b); + assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a); + assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b); + + always @(*) begin + if (~sdp_mode && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_a_last & rd_addr_b_mask) == (rd_addr_b_last & wr_addr_a_mask)) wr_a_rd_b_addr_coll = 1'b1; + else wr_a_rd_b_addr_coll = 1'b0; + end + else wr_a_rd_b_addr_coll = 1'b0; + end + + always @(*) begin + if (~sdp_mode && mem_wr_en_b && mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_a_last & wr_addr_b_mask) == (wr_addr_b_last & wr_addr_a_mask)) wr_addr_coll = 1'b1; + else wr_addr_coll = 1'b0; + end + else wr_addr_coll = 1'b0; + end + + always @(*) begin + if (mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a && ~mem_rst_a && ~mem_rst_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin + if ((wr_addr_b_last & rd_addr_a_mask) == (rd_addr_a_last & wr_addr_b_mask)) wr_b_rd_a_addr_coll = 1'b1; + else wr_b_rd_a_addr_coll = 1'b0; + end + else wr_b_rd_a_addr_coll = 1'b0; + end + + always @ (WEA_in or glblGSR) begin + mem_we_a = {{8{WEA_in[3]}},{8{WEA_in[2]}},{8{WEA_in[1]}},{8{WEA_in[0]}}}; + if (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) memp_we_a = WEA_in; + else memp_we_a = 4'b0; + end + always @ (WEBWE_in or glblGSR) begin + mem_we_b = {{8{WEBWE_in[7]}},{8{WEBWE_in[6]}},{8{WEBWE_in[5]}},{8{WEBWE_in[4]}}, + {8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}}; + if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) memp_we_b = WEBWE_in; + else memp_we_b = 8'b0; + end +// eccparity is flopped + always @ (*) begin + if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) synd_wr = 8'b0; + else begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in) + synd_wr = fn_ecc(encode, {CASDINB_in, CASDINA_in}, {CASDINPB_in, CASDINPA_in}); + else + synd_wr = fn_ecc(encode, {DINBDIN_in, DINADIN_in}, {DINPBDINP_in, DINPADINP_in}); + end + end + + always @ (*) begin + if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin + if (coll_wr_b_rd_a_sim && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) + synd_rd = fn_ecc(decode, mem_rd_b_rf, memp_rd_b_rf); + else + synd_rd = fn_ecc(decode, ram_rd_a, ramp_rd_a); + end + else synd_rd = 8'b0; + + if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin + if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) + synd_ecc = synd_rd ^ memp_rd_b_rf; + else + synd_ecc = synd_rd ^ ramp_rd_a; + end + else + synd_ecc = 8'b0; + + + //CR-1055052 + if(synd_ecc[7] && synd_ecc[6:0] >71) begin + $display("Error: [Unisim %s-23] DRC : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code. @%0t Instance: %m", $time, MODULE_NAME); + $finish; + end + end + + assign sbit_int = (|synd_ecc && synd_ecc[7]); + assign dbit_int = (|synd_ecc && ~synd_ecc[7]); + always @(posedge CLKARDCLK_in) begin + if (mem_rd_en_a && mem_rst_a) begin + sbit_lat <= 1'b0; + dbit_lat <= 1'b0; + error_bit <= 7'b0; + r_a_ecc_lat <= 9'b0; + end + else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin + sbit_lat <= sbit_int; + dbit_lat <= dbit_int; + error_bit <= synd_ecc[6:0]; + r_a_ecc_lat <= rd_addr_a[ADDR_WIDTH-1:ADDR_WIDTH-9]; + end + end + +// assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ? +// fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) : +// {memp_rd_a, mem_rd_a}; + + always @ (posedge CLKBWRCLK_in or glblGSR) begin + if(glblGSR || (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE)) + eccparity_reg <= 8'h00; + else if (ENBWREN_in) + eccparity_reg <= synd_wr; + end + +`ifdef XIL_TIMING + reg notifier; + wire clkardclk_en_n; + wire clkardclk_en_p; + wire clkbwrclk_en_n; + wire clkbwrclk_en_p; + assign clkardclk_en_n = IS_CLKARDCLK_INVERTED_BIN; + assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED_BIN; + assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED_BIN; + assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED_BIN; +`endif + + specify + (CASDINA *> CASDOUTA) = (0:0:0, 0:0:0); + (CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0); + (CASDINB *> CASDOUTB) = (0:0:0, 0:0:0); + (CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0); + (CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0); + (CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0); + (CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0); + (CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0); + (CASINDBITERR => CASOUTDBITERR) = (0:0:0, 0:0:0); + (CASINDBITERR => DBITERR) = (0:0:0, 0:0:0); + (CASINSBITERR => CASOUTSBITERR) = (0:0:0, 0:0:0); + (CASINSBITERR => SBITERR) = (0:0:0, 0:0:0); + (CLKARDCLK *> CASDOUTA) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTB) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTPA) = (100:100:100, 100:100:100); + (CLKARDCLK *> CASDOUTPB) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTADOUT) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTBDOUT) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTPADOUTP) = (100:100:100, 100:100:100); + (CLKARDCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100); + (CLKARDCLK *> RDADDRECC) = (100:100:100, 100:100:100); + (CLKARDCLK => CASOUTDBITERR) = (100:100:100, 100:100:100); + (CLKARDCLK => CASOUTSBITERR) = (100:100:100, 100:100:100); + (CLKARDCLK => DBITERR) = (100:100:100, 100:100:100); + (CLKARDCLK => SBITERR) = (100:100:100, 100:100:100); + (CLKBWRCLK *> CASDOUTB) = (100:100:100, 100:100:100); + (CLKBWRCLK *> CASDOUTPB) = (100:100:100, 100:100:100); + (CLKBWRCLK *> DOUTBDOUT) = (100:100:100, 100:100:100); + (CLKBWRCLK *> DOUTPBDOUTP) = (100:100:100, 100:100:100); + (CLKBWRCLK *> ECCPARITY) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLKARDCLK, 0:0:0, notifier); + $period (negedge CLKBWRCLK, 0:0:0, notifier); + $period (posedge CLKARDCLK, 0:0:0, notifier); + $period (posedge CLKBWRCLK, 0:0:0, notifier); + $setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINDBITERR_delay); + $setuphold (negedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINSBITERR_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay); + $setuphold (negedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ECCPIPECE_delay); + $setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay); + $setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINDBITERR_delay); + $setuphold (negedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASINSBITERR_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINADIN_delay); + $setuphold (negedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ECCPIPECE_delay); + $setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, REGCEB_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, SLEEP_delay); + $setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEA_delay); + $setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_n,clkardclk_en_n, CLKARDCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay); + $setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (negedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (negedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEA_delay); + $setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_n,clkbwrclk_en_n, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINDBITERR_delay); + $setuphold (posedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINSBITERR_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay); + $setuphold (posedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ECCPIPECE_delay); + $setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay); + $setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINDBITERR_delay); + $setuphold (posedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASINSBITERR_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINADIN_delay); + $setuphold (posedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ECCPIPECE_delay); + $setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, REGCEB_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, SLEEP_delay); + $setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEA_delay); + $setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkardclk_en_p,clkardclk_en_p, CLKARDCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay); + $setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRARDADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENA_delay); + $setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ADDRENB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDIMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDINPB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASDOMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXA_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXB_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay); + $setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay); + $setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINADIN_delay); + $setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINBDIN_delay); + $setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPADINP_delay); + $setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, DINPBDINP_delay); + $setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENARDEN_delay); + $setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); + $setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTDBITERR_delay); + $setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, INJECTSBITERR_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEAREGCE_delay); + $setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMARSTRAM_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTRAMB_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGARSTREG_delay); + $setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); + $setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEA_delay); + $setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,clkbwrclk_en_p,clkbwrclk_en_p, CLKBWRCLK_delay, WEBWE_delay); + $width (negedge CLKARDCLK, 0:0:0, 0, notifier); + $width (negedge CLKBWRCLK, 0:0:0, 0, notifier); + $width (posedge CLKARDCLK, 0:0:0, 0, notifier); + $width (posedge CLKBWRCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMD32.v b/verilog/src/unisims/RAMD32.v new file mode 100644 index 0000000..8a7d671 --- /dev/null +++ b/verilog/src/unisims/RAMD32.v @@ -0,0 +1,240 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAMD32.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/10 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine. +// 04/16/13 - 683925 - Add invertible pin support. +// 10/22/14 - 808642 - Added #1 to $finish. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMD32 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [31:0] INIT = 32'h00000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output O, + + input CLK, + input I, + input RADR0, + input RADR1, + input RADR2, + input RADR3, + input RADR4, + input WADR0, + input WADR1, + input WADR2, + input WADR3, + input WADR4, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMD32"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMD32_dr.v" +`else + reg [31:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_in; + wire I_in; + wire RADR0_in; + wire RADR1_in; + wire RADR2_in; + wire RADR3_in; + wire RADR4_in; + wire WADR0_in; + wire WADR1_in; + wire WADR2_in; + wire WADR3_in; + wire WADR4_in; + wire WE_in; + +`ifdef XIL_TIMING + wire CLK_delay; + wire I_delay; + wire WADR0_delay; + wire WADR1_delay; + wire WADR2_delay; + wire WADR3_delay; + wire WADR4_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG; + assign I_in = I_delay; + assign WADR0_in = WADR0_delay; + assign WADR1_in = WADR1_delay; + assign WADR2_in = WADR2_delay; + assign WADR3_in = WADR3_delay; + assign WADR4_in = WADR4_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign CLK_in = CLK ^ IS_CLK_INVERTED_REG; + assign I_in = I; + assign WADR0_in = WADR0; + assign WADR1_in = WADR1; + assign WADR2_in = WADR2; + assign WADR3_in = WADR3; + assign WADR4_in = WADR4; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + + assign RADR0_in = RADR0; + assign RADR1_in = RADR1; + assign RADR2_in = RADR2; + assign RADR3_in = RADR3; + assign RADR4_in = RADR4; + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [31:0] mem; + reg O_out; + + assign O = O_out; + +`ifndef XIL_XECLIB + initial begin + mem = INIT; + O_out = mem[{RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}]; + end +`endif + + always @(posedge CLK_in) + if (WE_in == 1'b1) begin + mem[{WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = I_in; + end + + always @ (*) begin + O_out = mem[{RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}]; + end + +`ifdef XIL_TIMING + always @(notifier) mem[{WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = 1'bx; +`endif + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + + assign we_clk_en_n = WE_in && IS_CLK_INVERTED_REG; + assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_REG; +`endif + + specify + (CLK => O) = (100:100:100, 100:100:100); + (I => O) = (0:0:0, 0:0:0); + (RADR0 => O) = (0:0:0, 0:0:0); + (RADR1 => O) = (0:0:0, 0:0:0); + (RADR2 => O) = (0:0:0, 0:0:0); + (RADR3 => O) = (0:0:0, 0:0:0); + (RADR4 => O) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK &&& WE, 0:0:0, notifier); + $period (posedge CLK &&& WE, 0:0:0, notifier); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMD32M64.v b/verilog/src/unisims/RAMD32M64.v new file mode 100644 index 0000000..260d0a0 --- /dev/null +++ b/verilog/src/unisims/RAMD32M64.v @@ -0,0 +1,253 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2019.2 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RAMD32M64 +// /___/ /\ Filename : RAMD32M64.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMD32M64 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output O, + + input CLK, + input I, + input RADR0, + input RADR1, + input RADR2, + input RADR3, + input RADR4, + input RADR5, + input WADR0, + input WADR1, + input WADR2, + input WADR3, + input WADR4, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMD32M64"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMD32M64_dr.v" +`else + reg [63:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_in; + wire I_in; + wire RADR0_in; + wire RADR1_in; + wire RADR2_in; + wire RADR3_in; + wire RADR4_in; + wire RADR5_in; + wire WADR0_in; + wire WADR1_in; + wire WADR2_in; + wire WADR3_in; + wire WADR4_in; + wire WE_in; + +`ifdef XIL_TIMING + wire CLK_delay; + wire I_delay; + wire RADR0_delay; + wire RADR1_delay; + wire RADR2_delay; + wire RADR3_delay; + wire RADR4_delay; + wire RADR5_delay; + wire WADR0_delay; + wire WADR1_delay; + wire WADR2_delay; + wire WADR3_delay; + wire WADR4_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG; + assign I_in = I_delay; + assign RADR0_in = RADR0_delay; + assign RADR1_in = RADR1_delay; + assign RADR2_in = RADR2_delay; + assign RADR3_in = RADR3_delay; + assign RADR4_in = RADR4_delay; + assign RADR5_in = RADR5_delay; + assign WADR0_in = WADR0_delay; + assign WADR1_in = WADR1_delay; + assign WADR2_in = WADR2_delay; + assign WADR3_in = WADR3_delay; + assign WADR4_in = WADR4_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign CLK_in = CLK ^ IS_CLK_INVERTED_REG; + assign I_in = I; + assign RADR0_in = RADR0; + assign RADR1_in = RADR1; + assign RADR2_in = RADR2; + assign RADR3_in = RADR3; + assign RADR4_in = RADR4; + assign RADR5_in = RADR5; + assign WADR0_in = WADR0; + assign WADR1_in = WADR1; + assign WADR2_in = WADR2; + assign WADR3_in = WADR3; + assign WADR4_in = WADR4; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + #1; + trig_attr = ~trig_attr; +end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + + specify + (CLK => O) = (100:100:100, 100:100:100); + (RADR0 => O) = (0:0:0, 0:0:0); + (RADR1 => O) = (0:0:0, 0:0:0); + (RADR2 => O) = (0:0:0, 0:0:0); + (RADR3 => O) = (0:0:0, 0:0:0); + (RADR4 => O) = (0:0:0, 0:0:0); + (RADR5 => O) = (0:0:0, 0:0:0); + (WADR0 => O) = (0:0:0, 0:0:0); + (WADR1 => O) = (0:0:0, 0:0:0); + (WADR2 => O) = (0:0:0, 0:0:0); + (WADR3 => O) = (0:0:0, 0:0:0); + (WADR4 => O) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge RADR0, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR0_delay); + $setuphold (negedge CLK, negedge RADR1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR1_delay); + $setuphold (negedge CLK, negedge RADR2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR2_delay); + $setuphold (negedge CLK, negedge RADR3, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR3_delay); + $setuphold (negedge CLK, negedge RADR4, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR4_delay); + $setuphold (negedge CLK, negedge RADR5, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR5_delay); + $setuphold (negedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge RADR0, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR0_delay); + $setuphold (negedge CLK, posedge RADR1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR1_delay); + $setuphold (negedge CLK, posedge RADR2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR2_delay); + $setuphold (negedge CLK, posedge RADR3, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR3_delay); + $setuphold (negedge CLK, posedge RADR4, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR4_delay); + $setuphold (negedge CLK, posedge RADR5, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RADR5_delay); + $setuphold (negedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge RADR0, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR0_delay); + $setuphold (posedge CLK, negedge RADR1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR1_delay); + $setuphold (posedge CLK, negedge RADR2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR2_delay); + $setuphold (posedge CLK, negedge RADR3, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR3_delay); + $setuphold (posedge CLK, negedge RADR4, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR4_delay); + $setuphold (posedge CLK, negedge RADR5, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR5_delay); + $setuphold (posedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge RADR0, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR0_delay); + $setuphold (posedge CLK, posedge RADR1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR1_delay); + $setuphold (posedge CLK, posedge RADR2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR2_delay); + $setuphold (posedge CLK, posedge RADR3, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR3_delay); + $setuphold (posedge CLK, posedge RADR4, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR4_delay); + $setuphold (posedge CLK, posedge RADR5, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RADR5_delay); + $setuphold (posedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMD64E.v b/verilog/src/unisims/RAMD64E.v new file mode 100644 index 0000000..f45dfaa --- /dev/null +++ b/verilog/src/unisims/RAMD64E.v @@ -0,0 +1,297 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAMD64E.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/10 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine. +// 03/21/12 - 649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7. +// 04/16/13 - 683925 - Add invertible pin support. +// 10/22/14 - 808642 - Added #1 to $finish. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMD64E #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [1:0] RAM_ADDRESS_MASK = 2'b00, + parameter [1:0] RAM_ADDRESS_SPACE = 2'b00 +)( + output O, + + input CLK, + input I, + input RADR0, + input RADR1, + input RADR2, + input RADR3, + input RADR4, + input RADR5, + input WADR0, + input WADR1, + input WADR2, + input WADR3, + input WADR4, + input WADR5, + input WADR6, + input WADR7, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMD64E"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMD64E_dr.v" +`else + reg [63:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [1:0] RAM_ADDRESS_MASK_REG = RAM_ADDRESS_MASK; + reg [1:0] RAM_ADDRESS_SPACE_REG = RAM_ADDRESS_SPACE; +`endif + +`ifdef XIL_XECLIB + wire IS_CLK_INVERTED_BIN; +`else + reg IS_CLK_INVERTED_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire CLK_in; + wire I_in; + wire RADR0_in; + wire RADR1_in; + wire RADR2_in; + wire RADR3_in; + wire RADR4_in; + wire RADR5_in; + wire WADR0_in; + wire WADR1_in; + wire WADR2_in; + wire WADR3_in; + wire WADR4_in; + wire WADR5_in; + wire WADR6_in; + wire WADR7_in; + wire WE_in; + +`ifdef XIL_TIMING + wire CLK_delay; + wire I_delay; + wire WADR0_delay; + wire WADR1_delay; + wire WADR2_delay; + wire WADR3_delay; + wire WADR4_delay; + wire WADR5_delay; + wire WADR6_delay; + wire WADR7_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign I_in = I_delay; + assign WADR0_in = WADR0_delay; + assign WADR1_in = WADR1_delay; + assign WADR2_in = WADR2_delay; + assign WADR3_in = WADR3_delay; + assign WADR4_in = WADR4_delay; + assign WADR5_in = WADR5_delay; + assign WADR6_in = WADR6_delay; + assign WADR7_in = WADR7_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign CLK_in = CLK ^ IS_CLK_INVERTED_BIN; + assign I_in = I; + assign WADR0_in = WADR0; + assign WADR1_in = WADR1; + assign WADR2_in = WADR2; + assign WADR3_in = WADR3; + assign WADR4_in = WADR4; + assign WADR5_in = WADR5; + assign WADR6_in = WADR6; + assign WADR7_in = WADR7; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + assign RADR0_in = RADR0; + assign RADR1_in = RADR1; + assign RADR2_in = RADR2; + assign RADR3_in = RADR3; + assign RADR4_in = RADR4; + assign RADR5_in = RADR5; + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + +`else + always @ (trig_attr) begin + #1; + IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-101] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [63:0] mem; + reg O_out; + + assign O = O_out; + +`ifndef XIL_XECLIB + initial begin + mem = INIT; + O_out = mem[{RADR5_in,RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}]; + end +`endif + + always @(posedge CLK_in) + if (WE_in == 1'b1 && + (RAM_ADDRESS_MASK_REG[1] || WADR7_in == RAM_ADDRESS_SPACE_REG[1]) && + (RAM_ADDRESS_MASK_REG[0] || WADR6_in == RAM_ADDRESS_SPACE_REG[0]) ) begin + mem[{WADR5_in,WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = I_in; + end + + always @ (*) begin + O_out = mem[{RADR5_in,RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}]; + end + +`ifdef XIL_TIMING + always @(notifier) mem[{WADR5_in,WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = 1'bx; +`endif + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; + + wire we_clk_en_n; + wire we_clk_en_p; + + assign we_clk_en_n = WE_in && IS_CLK_INVERTED_BIN; + assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_BIN; +`endif + + specify + (CLK => O) = (100:100:100, 100:100:100); + (RADR0 => O) = (0:0:0, 0:0:0); + (RADR1 => O) = (0:0:0, 0:0:0); + (RADR2 => O) = (0:0:0, 0:0:0); + (RADR3 => O) = (0:0:0, 0:0:0); + (RADR4 => O) = (0:0:0, 0:0:0); + (RADR5 => O) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK &&& WE, 0:0:0, notifier); + $period (posedge CLK &&& WE, 0:0:0, notifier); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, negedge WADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR5_delay); + $setuphold (negedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay); + $setuphold (negedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay); + $setuphold (negedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay); + $setuphold (negedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay); + $setuphold (negedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay); + $setuphold (negedge CLK, posedge WADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR5_delay); + $setuphold (negedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, negedge WADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR5_delay); + $setuphold (posedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay); + $setuphold (posedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay); + $setuphold (posedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay); + $setuphold (posedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay); + $setuphold (posedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay); + $setuphold (posedge CLK, posedge WADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR5_delay); + $setuphold (posedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMS32.v b/verilog/src/unisims/RAMS32.v new file mode 100644 index 0000000..81a0719 --- /dev/null +++ b/verilog/src/unisims/RAMS32.v @@ -0,0 +1,228 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Static Single Port Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAMS32.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/10 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine. +// 04/16/13 - 683925 - add invertible pin support. +// 10/22/14 - 808642 - Added #1 to $finish. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMS32 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [31:0] INIT = 32'h00000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output O, + + input ADR0, + input ADR1, + input ADR2, + input ADR3, + input ADR4, + input CLK, + input I, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMS32"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMS32_dr.v" +`else + reg [31:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire ADR0_in; + wire ADR1_in; + wire ADR2_in; + wire ADR3_in; + wire ADR4_in; + wire CLK_in; + wire I_in; + wire WE_in; + +`ifdef XIL_TIMING + wire ADR0_delay; + wire ADR1_delay; + wire ADR2_delay; + wire ADR3_delay; + wire ADR4_delay; + wire CLK_delay; + wire I_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign ADR0_in = ADR0_delay; + assign ADR1_in = ADR1_delay; + assign ADR2_in = ADR2_delay; + assign ADR3_in = ADR3_delay; + assign ADR4_in = ADR4_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG; + assign I_in = I_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign ADR0_in = ADR0; + assign ADR1_in = ADR1; + assign ADR2_in = ADR2; + assign ADR3_in = ADR3; + assign ADR4_in = ADR4; + assign CLK_in = CLK ^ IS_CLK_INVERTED_REG; + assign I_in = I; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + +`ifndef XIL_XECLIB + initial begin + trig_attr = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [31:0] mem; + reg O_out; + + assign O = O_out; + +`ifndef XIL_XECLIB + initial begin + mem = INIT; + O_out = mem[{ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end +`endif + + always @(posedge CLK_in) + if (WE_in == 1'b1) begin + mem[{ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] = I_in; + end + + always @ (*) begin + O_out = mem[{ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end + +`ifdef XIL_TIMING + always @(notifier) mem[{ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] <= 1'bx; +`endif + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + + wire we_clk_en_n; + wire we_clk_en_p; + + assign we_clk_en_n = WE_in && IS_CLK_INVERTED_REG; + assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_REG; +`endif + + specify + (ADR0 => O) = (0:0:0, 0:0:0); + (ADR1 => O) = (0:0:0, 0:0:0); + (ADR2 => O) = (0:0:0, 0:0:0); + (ADR3 => O) = (0:0:0, 0:0:0); + (ADR4 => O) = (0:0:0, 0:0:0); + (CLK => O) = (100:100:100, 100:100:100); + (I => O) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK &&& WE, 0:0:0, notifier); + $period (posedge CLK &&& WE, 0:0:0, notifier); + $setuphold (negedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMS64E.v b/verilog/src/unisims/RAMS64E.v new file mode 100644 index 0000000..1e5560a --- /dev/null +++ b/verilog/src/unisims/RAMS64E.v @@ -0,0 +1,278 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Static Single Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAMS64E.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/02/10 - Initial version. +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine. +// 03/21/12 - 649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7. +// 04/16/13 - 683925 - add invertible pin support. +// 10/22/14 - 808642 - Added #1 to $finish. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMS64E #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [1:0] RAM_ADDRESS_MASK = 2'b00, + parameter [1:0] RAM_ADDRESS_SPACE = 2'b00 +)( + output O, + + input ADR0, + input ADR1, + input ADR2, + input ADR3, + input ADR4, + input ADR5, + input CLK, + input I, + input WADR6, + input WADR7, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMS64E"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMS64E_dr.v" +`else + reg [63:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [1:0] RAM_ADDRESS_MASK_REG = RAM_ADDRESS_MASK; + reg [1:0] RAM_ADDRESS_SPACE_REG = RAM_ADDRESS_SPACE; +`endif + +`ifdef XIL_XECLIB + wire IS_CLK_INVERTED_BIN; +`else + reg IS_CLK_INVERTED_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire ADR0_in; + wire ADR1_in; + wire ADR2_in; + wire ADR3_in; + wire ADR4_in; + wire ADR5_in; + wire CLK_in; + wire I_in; + wire WADR6_in; + wire WADR7_in; + wire WE_in; + +`ifdef XIL_TIMING + wire ADR0_delay; + wire ADR1_delay; + wire ADR2_delay; + wire ADR3_delay; + wire ADR4_delay; + wire ADR5_delay; + wire CLK_delay; + wire I_delay; + wire WADR6_delay; + wire WADR7_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign ADR0_in = ADR0_delay; + assign ADR1_in = ADR1_delay; + assign ADR2_in = ADR2_delay; + assign ADR3_in = ADR3_delay; + assign ADR4_in = ADR4_delay; + assign ADR5_in = ADR5_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign I_in = I_delay; + assign WADR6_in = WADR6_delay; + assign WADR7_in = WADR7_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign ADR0_in = ADR0; + assign ADR1_in = ADR1; + assign ADR2_in = ADR2; + assign ADR3_in = ADR3; + assign ADR4_in = ADR4; + assign ADR5_in = ADR5; + assign CLK_in = CLK ^ IS_CLK_INVERTED_BIN; + assign I_in = I; + assign WADR6_in = WADR6; + assign WADR7_in = WADR7; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + +`else + always @ (trig_attr) begin + #1; + IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-101] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [63:0] mem; + reg O_out; + + assign O = O_out; + +`ifndef XIL_XECLIB + initial begin + mem = INIT; + O_out = mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end +`endif + + always @(posedge CLK_in) + if (WE_in == 1'b1 && + (RAM_ADDRESS_MASK_REG[1] || WADR7_in == RAM_ADDRESS_SPACE_REG[1]) && + (RAM_ADDRESS_MASK_REG[0] || WADR6_in == RAM_ADDRESS_SPACE_REG[0]) ) begin + mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] = I_in; + end + + always @ (*) begin + O_out = mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end + +`ifdef XIL_TIMING + always @(notifier) mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] <= 1'bx; +`endif + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; + + wire we_clk_en_n; + wire we_clk_en_p; + + assign we_clk_en_n = WE_in && IS_CLK_INVERTED_BIN; + assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_BIN; +`endif + + specify + (ADR0 => O) = (0:0:0, 0:0:0); + (ADR1 => O) = (0:0:0, 0:0:0); + (ADR2 => O) = (0:0:0, 0:0:0); + (ADR3 => O) = (0:0:0, 0:0:0); + (ADR4 => O) = (0:0:0, 0:0:0); + (ADR5 => O) = (0:0:0, 0:0:0); + (CLK => O) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK &&& WE, 0:0:0, notifier); + $period (posedge CLK &&& WE, 0:0:0, notifier); + $setuphold (negedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, negedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR5_delay); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, posedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR5_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, negedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR5_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, posedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR5_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RAMS64E1.v b/verilog/src/unisims/RAMS64E1.v new file mode 100644 index 0000000..4176322 --- /dev/null +++ b/verilog/src/unisims/RAMS64E1.v @@ -0,0 +1,281 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Static Single Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAMS64E1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 04/16/13 - Initial from RAMS64E. +// 10/22/14 - 808642 - Added #1 to $finish. +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RAMS64E1 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [63:0] INIT = 64'h0000000000000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [2:0] RAM_ADDRESS_MASK = 3'b000, + parameter [2:0] RAM_ADDRESS_SPACE = 3'b000 +)( + output O, + + input ADR0, + input ADR1, + input ADR2, + input ADR3, + input ADR4, + input ADR5, + input CLK, + input I, + input WADR6, + input WADR7, + input WADR8, + input WE +); + +// define constants + localparam MODULE_NAME = "RAMS64E1"; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RAMS64E1_dr.v" +`else + reg [63:0] INIT_REG = INIT; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [2:0] RAM_ADDRESS_MASK_REG = RAM_ADDRESS_MASK; + reg [2:0] RAM_ADDRESS_SPACE_REG = RAM_ADDRESS_SPACE; +`endif + +`ifdef XIL_XECLIB + wire IS_CLK_INVERTED_BIN; +`else + reg IS_CLK_INVERTED_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + + wire ADR0_in; + wire ADR1_in; + wire ADR2_in; + wire ADR3_in; + wire ADR4_in; + wire ADR5_in; + wire CLK_in; + wire I_in; + wire WADR6_in; + wire WADR7_in; + wire WADR8_in; + wire WE_in; + +`ifdef XIL_TIMING + wire ADR0_delay; + wire ADR1_delay; + wire ADR2_delay; + wire ADR3_delay; + wire ADR4_delay; + wire ADR5_delay; + wire CLK_delay; + wire I_delay; + wire WADR6_delay; + wire WADR7_delay; + wire WADR8_delay; + wire WE_delay; +`endif + +`ifdef XIL_TIMING + assign ADR0_in = ADR0_delay; + assign ADR1_in = ADR1_delay; + assign ADR2_in = ADR2_delay; + assign ADR3_in = ADR3_delay; + assign ADR4_in = ADR4_delay; + assign ADR5_in = ADR5_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign I_in = I_delay; + assign WADR6_in = WADR6_delay; + assign WADR7_in = WADR7_delay; + assign WADR8_in = WADR8_delay; + assign WE_in = (WE === 1'bz) || WE_delay; // rv 1 +`else + assign ADR0_in = ADR0; + assign ADR1_in = ADR1; + assign ADR2_in = ADR2; + assign ADR3_in = ADR3; + assign ADR4_in = ADR4; + assign ADR5_in = ADR5; + assign CLK_in = CLK ^ IS_CLK_INVERTED_BIN; + assign I_in = I; + assign WADR6_in = WADR6; + assign WADR7_in = WADR7; + assign WADR8_in = WADR8; + assign WE_in = (WE === 1'bz) || WE; // rv 1 +`endif + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + +`else + always @ (trig_attr) begin + #1; + IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + end +`endif + +`ifndef XIL_TIMING + initial begin + $display("Error: [Unisim %s-101] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME); + #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model + + reg [63:0] mem; + reg O_out; + + assign O = O_out; + +`ifndef XIL_XECLIB + initial begin + mem = INIT; + O_out = mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end +`endif + + always @(posedge CLK_in) + if (WE_in == 1'b1 && + (RAM_ADDRESS_MASK_REG[2] || WADR8_in == RAM_ADDRESS_SPACE_REG[2]) && + (RAM_ADDRESS_MASK_REG[1] || WADR7_in == RAM_ADDRESS_SPACE_REG[1]) && + (RAM_ADDRESS_MASK_REG[0] || WADR6_in == RAM_ADDRESS_SPACE_REG[0]) ) begin + mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] = I_in; + end + + always @ (*) begin + O_out = mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}]; + end + +`ifdef XIL_TIMING + always @(notifier) mem[{ADR5_in, ADR4_in, ADR3_in, ADR2_in, ADR1_in, ADR0_in}] <= 1'bx; +`endif + +// end behavioral model + +`ifndef XIL_XECLIB + wire clk_en_n; + wire clk_en_p; + wire we_clk_en_n; + wire we_clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; + assign we_clk_en_n = WE_in && IS_CLK_INVERTED_BIN; + assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_BIN; + + specify + (ADR0 => O) = (0:0:0, 0:0:0); + (ADR1 => O) = (0:0:0, 0:0:0); + (ADR2 => O) = (0:0:0, 0:0:0); + (ADR3 => O) = (0:0:0, 0:0:0); + (ADR4 => O) = (0:0:0, 0:0:0); + (ADR5 => O) = (0:0:0, 0:0:0); + (CLK => O) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK &&& WE, 0:0:0, notifier); + $period (posedge CLK &&& WE, 0:0:0, notifier); + $setuphold (negedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, negedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR5_delay); + $setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, negedge WADR8, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR8_delay); + $setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (negedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR0_delay); + $setuphold (negedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR1_delay); + $setuphold (negedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR2_delay); + $setuphold (negedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR3_delay); + $setuphold (negedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR4_delay); + $setuphold (negedge CLK, posedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, ADR5_delay); + $setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay); + $setuphold (negedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR6_delay); + $setuphold (negedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR7_delay); + $setuphold (negedge CLK, posedge WADR8, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR8_delay); + $setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay); + $setuphold (posedge CLK, negedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, negedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, negedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, negedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, negedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, negedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR5_delay); + $setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, negedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, negedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, negedge WADR8, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR8_delay); + $setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $setuphold (posedge CLK, posedge ADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR0_delay); + $setuphold (posedge CLK, posedge ADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR1_delay); + $setuphold (posedge CLK, posedge ADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR2_delay); + $setuphold (posedge CLK, posedge ADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR3_delay); + $setuphold (posedge CLK, posedge ADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR4_delay); + $setuphold (posedge CLK, posedge ADR5, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, ADR5_delay); + $setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay); + $setuphold (posedge CLK, posedge WADR6, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR6_delay); + $setuphold (posedge CLK, posedge WADR7, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR7_delay); + $setuphold (posedge CLK, posedge WADR8, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR8_delay); + $setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RFADC.v b/verilog/src/unisims/RFADC.v new file mode 100644 index 0000000..48f5059 --- /dev/null +++ b/verilog/src/unisims/RFADC.v @@ -0,0 +1,2263 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2020.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RFADC +// /___/ /\ Filename : RFADC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RFADC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer OPT_ANALOG = 0, + parameter integer OPT_CLK_DIST = 0, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter integer XPA_ACTIVE_DUTYCYCLE = 100, + parameter integer XPA_CFG0 = 0, + parameter integer XPA_CFG1 = 0, + parameter integer XPA_CFG2 = 0, + parameter XPA_NUM_ADCS = "0", + parameter integer XPA_NUM_DDCS = 0, + parameter XPA_PLL_USED = "EXTERNAL", + parameter integer XPA_SAMPLE_RATE_MSPS = 0 +)( + output CLK_ADC, + output CLK_DIST_OUT_NORTH, + output CLK_DIST_OUT_SOUTH, + output [191:0] DATA_ADC0, + output [191:0] DATA_ADC1, + output [191:0] DATA_ADC2, + output [191:0] DATA_ADC3, + output [15:0] DOUT, + output DRDY, + output PLL_DMON_OUT, + output PLL_REFCLK_OUT, + output [23:0] STATUS_ADC0, + output [23:0] STATUS_ADC1, + output [23:0] STATUS_ADC2, + output [23:0] STATUS_ADC3, + output [23:0] STATUS_COMMON, + output SYSREF_OUT_NORTH, + output SYSREF_OUT_SOUTH, + output T1_ALLOWED_SOUTH, + + input ADC_CLK_N, + input ADC_CLK_P, + input CLK_DIST_IN_NORTH, + input CLK_DIST_IN_SOUTH, + input CLK_FIFO_LM, + input [15:0] CONTROL_ADC0, + input [15:0] CONTROL_ADC1, + input [15:0] CONTROL_ADC2, + input [15:0] CONTROL_ADC3, + input [15:0] CONTROL_COMMON, + input [11:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input FABRIC_CLK, + input PLL_MONCLK, + input PLL_REFCLK_IN, + input SYSREF_IN_NORTH, + input SYSREF_IN_SOUTH, + input SYSREF_N, + input SYSREF_P, + input T1_ALLOWED_NORTH, + input VIN0_N, + input VIN0_P, + input VIN1_N, + input VIN1_P, + input VIN2_N, + input VIN2_P, + input VIN3_N, + input VIN3_P, + input VIN_I01_N, + input VIN_I01_P, + input VIN_I23_N, + input VIN_I23_P +); + +// define constants + localparam MODULE_NAME = "RFADC"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RFADC_dr.v" +`else + reg [15:0] OPT_ANALOG_REG = OPT_ANALOG; + reg [15:0] OPT_CLK_DIST_REG = OPT_CLK_DIST; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [6:0] XPA_ACTIVE_DUTYCYCLE_REG = XPA_ACTIVE_DUTYCYCLE; + reg [15:0] XPA_CFG0_REG = XPA_CFG0; + reg [15:0] XPA_CFG1_REG = XPA_CFG1; + reg [15:0] XPA_CFG2_REG = XPA_CFG2; + reg [16:1] XPA_NUM_ADCS_REG = XPA_NUM_ADCS; + reg [2:0] XPA_NUM_DDCS_REG = XPA_NUM_DDCS; + reg [112:1] XPA_PLL_USED_REG = XPA_PLL_USED; + reg [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_ADC_SPARE_out; + wire CLK_ADC_out; + wire CLK_DIST_OUT_NORTH_out; + wire CLK_DIST_OUT_SOUTH_out; + wire DRDY_out; + wire PLL_DMON_OUT_out; + wire PLL_REFCLK_OUT_out; + wire SYSREF_OUT_NORTH_out; + wire SYSREF_OUT_SOUTH_out; + wire T1_ALLOWED_SOUTH_out; + wire [15:0] DOUT_out; + wire [15:0] TEST_STATUS_out; + wire [191:0] DATA_ADC0_out; + wire [191:0] DATA_ADC1_out; + wire [191:0] DATA_ADC2_out; + wire [191:0] DATA_ADC3_out; + wire [1:0] PLL_SCAN_OUT_B_FD_out; + wire [23:0] STATUS_ADC0_out; + wire [23:0] STATUS_ADC1_out; + wire [23:0] STATUS_ADC2_out; + wire [23:0] STATUS_ADC3_out; + wire [23:0] STATUS_COMMON_out; + wire [299:0] TEST_SO_out; + + wire ADC_CLK_N_in; + wire ADC_CLK_P_in; + wire CLK_DIST_IN_NORTH_in; + wire CLK_DIST_IN_SOUTH_in; + wire CLK_FIFO_LM_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire FABRIC_CLK_in; + wire PLL_MONCLK_in; + wire PLL_REFCLK_IN_in; + wire PLL_SCAN_EN_B_FD_in; + wire PLL_SCAN_MODE_B_FD_in; + wire PLL_SCAN_RST_EN_FD_in; + wire SYSREF_IN_NORTH_in; + wire SYSREF_IN_SOUTH_in; + wire SYSREF_N_in; + wire SYSREF_P_in; + wire T1_ALLOWED_NORTH_in; + wire TEST_SCAN_MODE_B_in; + wire TEST_SCAN_RESET_in; + wire TEST_SE_B_in; + wire VIN0_N_in; + wire VIN0_P_in; + wire VIN1_N_in; + wire VIN1_P_in; + wire VIN2_N_in; + wire VIN2_P_in; + wire VIN3_N_in; + wire VIN3_P_in; + wire VIN_I01_N_in; + wire VIN_I01_P_in; + wire VIN_I23_N_in; + wire VIN_I23_P_in; + wire [11:0] DADDR_in; + wire [15:0] CONTROL_ADC0_in; + wire [15:0] CONTROL_ADC1_in; + wire [15:0] CONTROL_ADC2_in; + wire [15:0] CONTROL_ADC3_in; + wire [15:0] CONTROL_COMMON_in; + wire [15:0] DI_in; + wire [15:0] TEST_SCAN_CTRL_in; + wire [1:0] PLL_SCAN_CLK_FD_in; + wire [1:0] PLL_SCAN_IN_FD_in; + wire [299:0] TEST_SI_in; + wire [4:0] TEST_SCAN_CLK_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire FABRIC_CLK_delay; + wire [11:0] DADDR_delay; + wire [15:0] CONTROL_ADC0_delay; + wire [15:0] CONTROL_ADC1_delay; + wire [15:0] CONTROL_ADC2_delay; + wire [15:0] CONTROL_ADC3_delay; + wire [15:0] CONTROL_COMMON_delay; + wire [15:0] DI_delay; +`endif + + real VIN0_N_real = 1.0; + real VIN0_P_real = 1.0; + real VIN1_N_real = 1.0; + real VIN1_P_real = 1.0; + real VIN2_N_real = 1.0; + real VIN2_P_real = 1.0; + real VIN3_N_real = 1.0; + real VIN3_P_real = 1.0; + real VIN_I01_N_real = 1.0; + real VIN_I01_P_real = 1.0; + real VIN_I23_N_real = 1.0; + real VIN_I23_P_real = 1.0; + + assign CLK_ADC = CLK_ADC_out; + assign CLK_DIST_OUT_NORTH = CLK_DIST_OUT_NORTH_out; + assign CLK_DIST_OUT_SOUTH = CLK_DIST_OUT_SOUTH_out; + assign DATA_ADC0 = DATA_ADC0_out; + assign DATA_ADC1 = DATA_ADC1_out; + assign DATA_ADC2 = DATA_ADC2_out; + assign DATA_ADC3 = DATA_ADC3_out; + assign DOUT = DOUT_out; + assign DRDY = DRDY_out; + assign PLL_DMON_OUT = PLL_DMON_OUT_out; + assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out; + assign STATUS_ADC0 = STATUS_ADC0_out; + assign STATUS_ADC1 = STATUS_ADC1_out; + assign STATUS_ADC2 = STATUS_ADC2_out; + assign STATUS_ADC3 = STATUS_ADC3_out; + assign STATUS_COMMON = STATUS_COMMON_out; + assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out; + assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out; + assign T1_ALLOWED_SOUTH = T1_ALLOWED_SOUTH_out; + +`ifdef XIL_TIMING + assign CONTROL_ADC0_in = CONTROL_ADC0_delay; + assign CONTROL_ADC1_in = CONTROL_ADC1_delay; + assign CONTROL_ADC2_in = CONTROL_ADC2_delay; + assign CONTROL_ADC3_in = CONTROL_ADC3_delay; + assign CONTROL_COMMON_in = CONTROL_COMMON_delay; + assign DADDR_in = DADDR_delay; + assign DCLK_in = DCLK_delay; + assign DEN_in = DEN_delay; + assign DI_in = DI_delay; + assign DWE_in = DWE_delay; + assign FABRIC_CLK_in = FABRIC_CLK_delay; +`else + assign CONTROL_ADC0_in = CONTROL_ADC0; + assign CONTROL_ADC1_in = CONTROL_ADC1; + assign CONTROL_ADC2_in = CONTROL_ADC2; + assign CONTROL_ADC3_in = CONTROL_ADC3; + assign CONTROL_COMMON_in = CONTROL_COMMON; + assign DADDR_in = DADDR; + assign DCLK_in = DCLK; + assign DEN_in = DEN; + assign DI_in = DI; + assign DWE_in = DWE; + assign FABRIC_CLK_in = FABRIC_CLK; +`endif + + assign ADC_CLK_N_in = ADC_CLK_N; + assign ADC_CLK_P_in = ADC_CLK_P; + assign CLK_DIST_IN_NORTH_in = CLK_DIST_IN_NORTH; + assign CLK_DIST_IN_SOUTH_in = CLK_DIST_IN_SOUTH; + assign CLK_FIFO_LM_in = CLK_FIFO_LM; + assign PLL_MONCLK_in = PLL_MONCLK; + assign PLL_REFCLK_IN_in = PLL_REFCLK_IN; + assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH; + assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH; + assign SYSREF_N_in = SYSREF_N; + assign SYSREF_P_in = SYSREF_P; + assign T1_ALLOWED_NORTH_in = T1_ALLOWED_NORTH; + assign VIN0_N_in = VIN0_N; + assign VIN0_P_in = VIN0_P; + assign VIN1_N_in = VIN1_N; + assign VIN1_P_in = VIN1_P; + assign VIN2_N_in = VIN2_N; + assign VIN2_P_in = VIN2_P; + assign VIN3_N_in = VIN3_N; + assign VIN3_P_in = VIN3_P; + assign VIN_I01_N_in = VIN_I01_N; + assign VIN_I01_P_in = VIN_I01_P; + assign VIN_I23_N_in = VIN_I23_N; + assign VIN_I23_P_in = VIN_I23_P; + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((OPT_ANALOG_REG < 0) || (OPT_ANALOG_REG > 65535))) begin + $display("Error: [Unisim %s-101] OPT_ANALOG attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, OPT_ANALOG_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OPT_CLK_DIST_REG < 0) || (OPT_CLK_DIST_REG > 65535))) begin + $display("Error: [Unisim %s-102] OPT_CLK_DIST attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, OPT_CLK_DIST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-103] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_ACTIVE_DUTYCYCLE_REG < 0) || (XPA_ACTIVE_DUTYCYCLE_REG > 100))) begin + $display("Error: [Unisim %s-104] XPA_ACTIVE_DUTYCYCLE attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, XPA_ACTIVE_DUTYCYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin + $display("Error: [Unisim %s-105] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin + $display("Error: [Unisim %s-106] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG2_REG < 0) || (XPA_CFG2_REG > 65535))) begin + $display("Error: [Unisim %s-107] XPA_CFG2 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_ADCS_REG != "0") && + (XPA_NUM_ADCS_REG != "1") && + (XPA_NUM_ADCS_REG != "1I") && + (XPA_NUM_ADCS_REG != "2") && + (XPA_NUM_ADCS_REG != "2I") && + (XPA_NUM_ADCS_REG != "3") && + (XPA_NUM_ADCS_REG != "4"))) begin + $display("Error: [Unisim %s-108] XPA_NUM_ADCS attribute is set to %s. Legal values for this attribute are 0, 1, 1I, 2, 2I, 3 or 4. Instance: %m", MODULE_NAME, XPA_NUM_ADCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DDCS_REG < 0) || (XPA_NUM_DDCS_REG > 4))) begin + $display("Error: [Unisim %s-109] XPA_NUM_DDCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DDCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_PLL_USED_REG != "EXTERNAL") && + (XPA_PLL_USED_REG != "DISTRIBUTED_T1") && + (XPA_PLL_USED_REG != "INTERNAL_PLL"))) begin + $display("Error: [Unisim %s-110] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are EXTERNAL, DISTRIBUTED_T1 or INTERNAL_PLL. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin + $display("Error: [Unisim %s-111] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + + +assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off +assign TEST_SCAN_CLK_in = 5'b11111; // tie off + +assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_IN_FD_in = 2'b11; // tie off +assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off +assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off +assign TEST_SCAN_MODE_B_in = 1'b1; // tie off +assign TEST_SCAN_RESET_in = 1'b1; // tie off +assign TEST_SE_B_in = 1'b1; // tie off +assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + + SIP_RFADC SIP_RFADC_INST ( + .OPT_ANALOG (OPT_ANALOG_REG), + .OPT_CLK_DIST (OPT_CLK_DIST_REG), + .SIM_DEVICE (SIM_DEVICE_REG), + .XPA_ACTIVE_DUTYCYCLE (XPA_ACTIVE_DUTYCYCLE_REG), + .XPA_CFG0 (XPA_CFG0_REG), + .XPA_CFG1 (XPA_CFG1_REG), + .XPA_CFG2 (XPA_CFG2_REG), + .XPA_NUM_ADCS (XPA_NUM_ADCS_REG), + .XPA_NUM_DDCS (XPA_NUM_DDCS_REG), + .XPA_PLL_USED (XPA_PLL_USED_REG), + .XPA_SAMPLE_RATE_MSPS (XPA_SAMPLE_RATE_MSPS_REG), + .CLK_ADC (CLK_ADC_out), + .CLK_ADC_SPARE (CLK_ADC_SPARE_out), + .CLK_DIST_OUT_NORTH (CLK_DIST_OUT_NORTH_out), + .CLK_DIST_OUT_SOUTH (CLK_DIST_OUT_SOUTH_out), + .DATA_ADC0 (DATA_ADC0_out), + .DATA_ADC1 (DATA_ADC1_out), + .DATA_ADC2 (DATA_ADC2_out), + .DATA_ADC3 (DATA_ADC3_out), + .DOUT (DOUT_out), + .DRDY (DRDY_out), + .PLL_DMON_OUT (PLL_DMON_OUT_out), + .PLL_REFCLK_OUT (PLL_REFCLK_OUT_out), + .PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out), + .STATUS_ADC0 (STATUS_ADC0_out), + .STATUS_ADC1 (STATUS_ADC1_out), + .STATUS_ADC2 (STATUS_ADC2_out), + .STATUS_ADC3 (STATUS_ADC3_out), + .STATUS_COMMON (STATUS_COMMON_out), + .SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out), + .SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out), + .T1_ALLOWED_SOUTH (T1_ALLOWED_SOUTH_out), + .TEST_SO (TEST_SO_out), + .TEST_STATUS (TEST_STATUS_out), + .ADC_CLK_N (ADC_CLK_N_in), + .ADC_CLK_P (ADC_CLK_P_in), + .CLK_DIST_IN_NORTH (CLK_DIST_IN_NORTH_in), + .CLK_DIST_IN_SOUTH (CLK_DIST_IN_SOUTH_in), + .CLK_FIFO_LM (CLK_FIFO_LM_in), + .CONTROL_ADC0 (CONTROL_ADC0_in), + .CONTROL_ADC1 (CONTROL_ADC1_in), + .CONTROL_ADC2 (CONTROL_ADC2_in), + .CONTROL_ADC3 (CONTROL_ADC3_in), + .CONTROL_COMMON (CONTROL_COMMON_in), + .DADDR (DADDR_in), + .DCLK (DCLK_in), + .DEN (DEN_in), + .DI (DI_in), + .DWE (DWE_in), + .FABRIC_CLK (FABRIC_CLK_in), + .PLL_MONCLK (PLL_MONCLK_in), + .PLL_REFCLK_IN (PLL_REFCLK_IN_in), + .PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in), + .PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in), + .PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in), + .PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in), + .PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in), + .SYSREF_IN_NORTH (SYSREF_IN_NORTH_in), + .SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in), + .SYSREF_N (SYSREF_N_in), + .SYSREF_P (SYSREF_P_in), + .T1_ALLOWED_NORTH (T1_ALLOWED_NORTH_in), + .TEST_SCAN_CLK (TEST_SCAN_CLK_in), + .TEST_SCAN_CTRL (TEST_SCAN_CTRL_in), + .TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in), + .TEST_SCAN_RESET (TEST_SCAN_RESET_in), + .TEST_SE_B (TEST_SE_B_in), + .TEST_SI (TEST_SI_in), + .VIN0_N (VIN0_N_real), + .VIN0_P (VIN0_P_real), + .VIN1_N (VIN1_N_real), + .VIN1_P (VIN1_P_real), + .VIN2_N (VIN2_N_real), + .VIN2_P (VIN2_P_real), + .VIN3_N (VIN3_N_real), + .VIN3_P (VIN3_P_real), + .VIN_I01_N (VIN_I01_N_real), + .VIN_I01_P (VIN_I01_P_real), + .VIN_I23_N (VIN_I23_N_real), + .VIN_I23_P (VIN_I23_P_real), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_XECLIB + specify + (CLK_FIFO_LM => DATA_ADC0[0]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[100]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[101]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[102]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[103]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[104]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[105]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[106]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[107]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[108]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[109]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[110]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[111]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[112]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[113]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[114]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[115]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[116]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[117]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[118]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[119]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[120]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[121]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[122]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[123]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[124]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[125]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[126]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[127]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[128]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[129]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[130]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[131]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[132]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[133]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[134]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[135]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[136]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[137]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[138]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[139]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[13]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[140]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[141]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[142]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[143]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[144]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[145]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[146]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[147]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[148]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[149]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[14]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[150]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[151]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[152]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[153]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[154]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[155]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[156]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[157]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[158]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[159]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[15]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[160]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[161]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[162]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[163]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[164]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[165]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[166]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[167]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[168]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[169]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[16]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[170]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[171]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[172]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[173]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[174]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[175]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[176]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[177]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[178]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[179]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[17]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[180]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[181]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[182]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[183]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[184]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[185]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[186]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[187]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[188]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[189]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[18]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[190]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[191]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[19]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[1]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[20]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[21]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[22]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[23]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[24]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[25]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[26]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[27]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[28]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[29]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[2]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[30]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[31]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[32]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[33]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[34]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[35]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[36]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[37]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[38]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[39]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[3]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[40]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[41]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[42]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[43]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[44]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[45]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[46]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[47]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[48]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[49]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[4]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[50]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[51]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[52]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[53]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[54]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[55]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[56]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[57]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[58]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[59]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[5]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[60]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[61]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[62]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[63]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[64]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[65]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[66]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[67]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[68]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[69]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[6]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[70]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[71]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[72]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[73]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[74]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[75]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[76]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[77]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[78]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[79]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[7]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[80]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[81]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[82]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[83]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[84]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[85]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[86]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[87]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[88]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[89]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[90]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[91]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[92]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[93]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[94]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[95]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[96]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[97]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[98]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[99]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC0[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[0]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[100]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[101]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[102]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[103]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[104]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[105]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[106]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[107]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[108]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[109]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[110]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[111]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[112]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[113]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[114]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[115]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[116]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[117]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[118]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[119]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[120]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[121]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[122]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[123]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[124]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[125]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[126]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[127]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[128]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[129]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[130]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[131]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[132]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[133]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[134]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[135]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[136]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[137]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[138]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[139]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[13]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[140]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[141]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[142]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[143]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[144]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[145]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[146]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[147]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[148]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[149]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[14]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[150]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[151]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[152]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[153]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[154]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[155]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[156]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[157]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[158]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[159]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[15]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[160]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[161]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[162]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[163]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[164]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[165]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[166]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[167]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[168]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[169]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[16]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[170]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[171]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[172]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[173]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[174]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[175]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[176]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[177]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[178]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[179]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[17]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[180]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[181]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[182]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[183]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[184]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[185]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[186]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[187]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[188]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[189]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[18]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[190]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[191]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[19]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[1]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[20]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[21]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[22]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[23]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[24]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[25]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[26]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[27]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[28]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[29]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[2]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[30]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[31]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[32]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[33]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[34]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[35]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[36]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[37]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[38]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[39]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[3]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[40]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[41]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[42]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[43]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[44]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[45]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[46]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[47]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[48]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[49]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[4]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[50]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[51]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[52]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[53]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[54]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[55]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[56]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[57]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[58]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[59]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[5]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[60]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[61]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[62]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[63]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[64]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[65]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[66]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[67]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[68]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[69]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[6]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[70]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[71]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[72]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[73]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[74]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[75]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[76]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[77]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[78]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[79]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[7]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[80]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[81]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[82]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[83]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[84]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[85]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[86]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[87]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[88]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[89]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[90]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[91]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[92]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[93]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[94]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[95]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[96]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[97]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[98]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[99]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC1[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[0]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[100]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[101]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[102]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[103]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[104]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[105]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[106]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[107]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[108]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[109]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[110]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[111]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[112]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[113]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[114]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[115]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[116]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[117]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[118]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[119]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[120]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[121]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[122]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[123]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[124]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[125]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[126]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[127]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[128]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[129]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[130]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[131]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[132]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[133]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[134]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[135]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[136]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[137]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[138]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[139]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[13]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[140]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[141]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[142]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[143]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[144]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[145]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[146]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[147]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[148]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[149]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[14]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[150]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[151]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[152]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[153]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[154]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[155]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[156]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[157]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[158]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[159]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[15]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[160]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[161]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[162]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[163]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[164]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[165]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[166]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[167]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[168]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[169]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[16]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[170]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[171]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[172]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[173]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[174]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[175]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[176]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[177]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[178]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[179]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[17]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[180]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[181]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[182]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[183]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[184]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[185]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[186]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[187]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[188]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[189]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[18]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[190]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[191]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[19]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[1]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[20]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[21]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[22]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[23]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[24]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[25]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[26]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[27]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[28]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[29]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[2]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[30]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[31]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[32]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[33]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[34]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[35]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[36]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[37]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[38]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[39]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[3]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[40]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[41]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[42]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[43]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[44]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[45]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[46]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[47]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[48]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[49]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[4]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[50]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[51]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[52]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[53]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[54]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[55]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[56]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[57]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[58]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[59]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[5]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[60]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[61]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[62]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[63]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[64]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[65]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[66]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[67]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[68]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[69]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[6]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[70]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[71]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[72]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[73]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[74]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[75]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[76]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[77]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[78]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[79]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[7]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[80]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[81]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[82]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[83]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[84]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[85]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[86]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[87]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[88]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[89]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[90]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[91]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[92]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[93]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[94]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[95]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[96]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[97]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[98]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[99]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC2[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[0]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[100]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[101]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[102]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[103]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[104]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[105]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[106]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[107]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[108]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[109]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[110]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[111]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[112]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[113]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[114]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[115]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[116]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[117]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[118]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[119]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[120]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[121]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[122]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[123]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[124]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[125]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[126]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[127]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[128]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[129]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[130]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[131]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[132]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[133]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[134]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[135]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[136]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[137]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[138]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[139]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[13]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[140]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[141]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[142]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[143]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[144]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[145]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[146]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[147]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[148]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[149]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[14]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[150]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[151]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[152]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[153]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[154]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[155]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[156]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[157]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[158]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[159]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[15]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[160]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[161]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[162]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[163]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[164]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[165]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[166]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[167]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[168]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[169]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[16]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[170]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[171]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[172]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[173]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[174]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[175]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[176]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[177]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[178]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[179]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[17]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[180]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[181]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[182]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[183]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[184]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[185]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[186]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[187]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[188]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[189]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[18]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[190]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[191]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[19]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[1]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[20]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[21]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[22]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[23]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[24]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[25]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[26]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[27]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[28]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[29]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[2]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[30]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[31]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[32]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[33]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[34]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[35]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[36]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[37]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[38]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[39]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[3]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[40]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[41]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[42]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[43]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[44]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[45]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[46]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[47]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[48]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[49]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[4]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[50]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[51]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[52]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[53]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[54]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[55]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[56]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[57]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[58]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[59]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[5]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[60]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[61]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[62]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[63]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[64]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[65]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[66]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[67]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[68]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[69]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[6]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[70]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[71]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[72]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[73]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[74]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[75]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[76]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[77]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[78]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[79]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[7]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[80]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[81]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[82]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[83]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[84]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[85]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[86]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[87]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[88]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[89]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[90]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[91]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[92]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[93]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[94]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[95]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[96]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[97]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[98]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[99]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => DATA_ADC3[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC0[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC0[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC0[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC0[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC0[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC1[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC1[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC1[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC1[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC1[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC2[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC2[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC2[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC2[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC2[9]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC3[10]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC3[11]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC3[12]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC3[8]) = (0:0:0, 0:0:0); + (CLK_FIFO_LM => STATUS_ADC3[9]) = (0:0:0, 0:0:0); + (DCLK => DOUT[0]) = (100:100:100, 100:100:100); + (DCLK => DOUT[10]) = (100:100:100, 100:100:100); + (DCLK => DOUT[11]) = (100:100:100, 100:100:100); + (DCLK => DOUT[12]) = (100:100:100, 100:100:100); + (DCLK => DOUT[13]) = (100:100:100, 100:100:100); + (DCLK => DOUT[14]) = (100:100:100, 100:100:100); + (DCLK => DOUT[15]) = (100:100:100, 100:100:100); + (DCLK => DOUT[1]) = (100:100:100, 100:100:100); + (DCLK => DOUT[2]) = (100:100:100, 100:100:100); + (DCLK => DOUT[3]) = (100:100:100, 100:100:100); + (DCLK => DOUT[4]) = (100:100:100, 100:100:100); + (DCLK => DOUT[5]) = (100:100:100, 100:100:100); + (DCLK => DOUT[6]) = (100:100:100, 100:100:100); + (DCLK => DOUT[7]) = (100:100:100, 100:100:100); + (DCLK => DOUT[8]) = (100:100:100, 100:100:100); + (DCLK => DOUT[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[0]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[100]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[101]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[102]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[103]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[104]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[105]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[106]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[107]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[108]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[109]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[110]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[111]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[112]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[113]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[114]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[115]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[116]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[117]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[118]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[119]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[120]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[121]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[122]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[123]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[124]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[125]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[126]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[127]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[128]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[129]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[130]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[131]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[132]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[133]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[134]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[135]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[136]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[137]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[138]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[139]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[13]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[140]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[141]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[142]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[143]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[144]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[145]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[146]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[147]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[148]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[149]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[14]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[150]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[151]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[152]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[153]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[154]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[155]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[156]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[157]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[158]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[159]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[15]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[160]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[161]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[162]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[163]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[164]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[165]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[166]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[167]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[168]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[169]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[16]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[170]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[171]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[172]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[173]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[174]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[175]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[176]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[177]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[178]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[179]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[17]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[180]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[181]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[182]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[183]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[184]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[185]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[186]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[187]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[188]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[189]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[18]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[190]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[191]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[19]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[1]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[20]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[21]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[22]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[23]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[24]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[25]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[26]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[27]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[28]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[29]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[2]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[30]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[31]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[32]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[33]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[34]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[35]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[36]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[37]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[38]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[39]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[3]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[40]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[41]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[42]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[43]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[44]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[45]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[46]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[47]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[48]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[49]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[4]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[50]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[51]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[52]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[53]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[54]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[55]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[56]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[57]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[58]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[59]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[5]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[60]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[61]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[62]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[63]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[64]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[65]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[66]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[67]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[68]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[69]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[70]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[71]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[72]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[73]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[74]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[75]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[76]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[77]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[78]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[79]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[7]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[80]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[81]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[82]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[83]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[84]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[85]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[86]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[87]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[88]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[89]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[90]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[91]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[92]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[93]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[94]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[95]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[96]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[97]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[98]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[99]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC0[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[0]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[100]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[101]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[102]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[103]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[104]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[105]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[106]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[107]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[108]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[109]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[110]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[111]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[112]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[113]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[114]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[115]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[116]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[117]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[118]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[119]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[120]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[121]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[122]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[123]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[124]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[125]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[126]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[127]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[128]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[129]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[130]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[131]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[132]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[133]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[134]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[135]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[136]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[137]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[138]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[139]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[13]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[140]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[141]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[142]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[143]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[144]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[145]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[146]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[147]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[148]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[149]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[14]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[150]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[151]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[152]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[153]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[154]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[155]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[156]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[157]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[158]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[159]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[15]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[160]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[161]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[162]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[163]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[164]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[165]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[166]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[167]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[168]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[169]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[16]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[170]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[171]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[172]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[173]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[174]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[175]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[176]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[177]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[178]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[179]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[17]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[180]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[181]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[182]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[183]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[184]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[185]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[186]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[187]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[188]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[189]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[18]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[190]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[191]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[19]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[1]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[20]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[21]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[22]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[23]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[24]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[25]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[26]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[27]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[28]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[29]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[2]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[30]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[31]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[32]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[33]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[34]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[35]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[36]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[37]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[38]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[39]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[3]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[40]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[41]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[42]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[43]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[44]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[45]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[46]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[47]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[48]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[49]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[4]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[50]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[51]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[52]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[53]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[54]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[55]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[56]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[57]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[58]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[59]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[5]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[60]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[61]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[62]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[63]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[64]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[65]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[66]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[67]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[68]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[69]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[70]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[71]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[72]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[73]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[74]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[75]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[76]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[77]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[78]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[79]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[7]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[80]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[81]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[82]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[83]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[84]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[85]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[86]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[87]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[88]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[89]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[90]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[91]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[92]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[93]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[94]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[95]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[96]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[97]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[98]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[99]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC1[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[0]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[100]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[101]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[102]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[103]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[104]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[105]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[106]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[107]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[108]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[109]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[110]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[111]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[112]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[113]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[114]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[115]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[116]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[117]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[118]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[119]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[120]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[121]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[122]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[123]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[124]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[125]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[126]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[127]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[128]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[129]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[130]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[131]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[132]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[133]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[134]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[135]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[136]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[137]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[138]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[139]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[13]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[140]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[141]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[142]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[143]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[144]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[145]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[146]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[147]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[148]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[149]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[14]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[150]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[151]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[152]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[153]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[154]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[155]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[156]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[157]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[158]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[159]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[15]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[160]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[161]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[162]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[163]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[164]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[165]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[166]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[167]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[168]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[169]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[16]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[170]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[171]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[172]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[173]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[174]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[175]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[176]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[177]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[178]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[179]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[17]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[180]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[181]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[182]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[183]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[184]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[185]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[186]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[187]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[188]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[189]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[18]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[190]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[191]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[19]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[1]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[20]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[21]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[22]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[23]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[24]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[25]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[26]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[27]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[28]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[29]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[2]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[30]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[31]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[32]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[33]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[34]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[35]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[36]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[37]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[38]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[39]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[3]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[40]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[41]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[42]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[43]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[44]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[45]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[46]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[47]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[48]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[49]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[4]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[50]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[51]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[52]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[53]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[54]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[55]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[56]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[57]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[58]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[59]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[5]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[60]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[61]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[62]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[63]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[64]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[65]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[66]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[67]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[68]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[69]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[70]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[71]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[72]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[73]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[74]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[75]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[76]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[77]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[78]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[79]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[7]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[80]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[81]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[82]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[83]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[84]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[85]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[86]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[87]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[88]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[89]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[90]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[91]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[92]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[93]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[94]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[95]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[96]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[97]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[98]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[99]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC2[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[0]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[100]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[101]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[102]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[103]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[104]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[105]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[106]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[107]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[108]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[109]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[110]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[111]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[112]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[113]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[114]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[115]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[116]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[117]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[118]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[119]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[120]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[121]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[122]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[123]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[124]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[125]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[126]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[127]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[128]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[129]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[130]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[131]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[132]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[133]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[134]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[135]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[136]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[137]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[138]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[139]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[13]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[140]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[141]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[142]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[143]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[144]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[145]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[146]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[147]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[148]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[149]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[14]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[150]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[151]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[152]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[153]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[154]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[155]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[156]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[157]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[158]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[159]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[15]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[160]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[161]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[162]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[163]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[164]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[165]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[166]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[167]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[168]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[169]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[16]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[170]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[171]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[172]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[173]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[174]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[175]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[176]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[177]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[178]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[179]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[17]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[180]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[181]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[182]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[183]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[184]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[185]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[186]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[187]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[188]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[189]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[18]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[190]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[191]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[19]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[1]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[20]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[21]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[22]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[23]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[24]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[25]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[26]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[27]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[28]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[29]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[2]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[30]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[31]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[32]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[33]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[34]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[35]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[36]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[37]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[38]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[39]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[3]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[40]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[41]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[42]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[43]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[44]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[45]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[46]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[47]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[48]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[49]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[4]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[50]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[51]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[52]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[53]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[54]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[55]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[56]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[57]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[58]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[59]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[5]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[60]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[61]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[62]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[63]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[64]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[65]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[66]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[67]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[68]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[69]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[70]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[71]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[72]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[73]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[74]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[75]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[76]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[77]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[78]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[79]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[7]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[80]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[81]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[82]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[83]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[84]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[85]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[86]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[87]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[88]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[89]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[90]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[91]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[92]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[93]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[94]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[95]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[96]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[97]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[98]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[99]) = (100:100:100, 100:100:100); + (FABRIC_CLK => DATA_ADC3[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC0[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC0[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC0[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC0[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC0[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC1[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC1[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC1[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC1[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC1[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC2[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC2[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC2[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC2[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC2[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC3[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC3[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC3[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC3[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_ADC3[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_COMMON[5]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK_ADC, 0:0:0, notifier); + $period (negedge CLK_FIFO_LM, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge FABRIC_CLK, 0:0:0, notifier); + $period (negedge PLL_DMON_OUT, 0:0:0, notifier); + $period (negedge PLL_MONCLK, 0:0:0, notifier); + $period (negedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (negedge PLL_REFCLK_OUT, 0:0:0, notifier); + $period (posedge CLK_ADC, 0:0:0, notifier); + $period (posedge CLK_FIFO_LM, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge FABRIC_CLK, 0:0:0, notifier); + $period (posedge PLL_DMON_OUT, 0:0:0, notifier); + $period (posedge PLL_MONCLK, 0:0:0, notifier); + $period (posedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (posedge PLL_REFCLK_OUT, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[15]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[2]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[3]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[4]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[5]); + $setuphold (posedge DCLK, negedge CONTROL_ADC0[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[6]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[15]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[2]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[3]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[4]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[5]); + $setuphold (posedge DCLK, negedge CONTROL_ADC1[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[6]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[15]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[2]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[3]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[4]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[5]); + $setuphold (posedge DCLK, negedge CONTROL_ADC2[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[6]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[15]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[2]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[3]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[4]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[5]); + $setuphold (posedge DCLK, negedge CONTROL_ADC3[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[6]); + $setuphold (posedge DCLK, negedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[15]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[2]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[3]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[4]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[5]); + $setuphold (posedge DCLK, posedge CONTROL_ADC0[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC0_delay[6]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[15]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[2]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[3]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[4]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[5]); + $setuphold (posedge DCLK, posedge CONTROL_ADC1[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC1_delay[6]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[15]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[2]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[3]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[4]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[5]); + $setuphold (posedge DCLK, posedge CONTROL_ADC2[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC2_delay[6]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[15]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[2]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[3]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[4]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[5]); + $setuphold (posedge DCLK, posedge CONTROL_ADC3[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_ADC3_delay[6]); + $setuphold (posedge DCLK, posedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[12]); + $setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[12]); + $width (negedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (negedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier); + $width (posedge CLK_FIFO_LM, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (posedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RFDAC.v b/verilog/src/unisims/RFDAC.v new file mode 100644 index 0000000..f757e6c --- /dev/null +++ b/verilog/src/unisims/RFDAC.v @@ -0,0 +1,2677 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2019 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2020.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RFDAC +// /___/ /\ Filename : RFDAC.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RFDAC #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer OPT_CLK_DIST = 0, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter integer XPA_ACTIVE_DUTYCYCLE = 100, + parameter integer XPA_CFG0 = 0, + parameter integer XPA_CFG1 = 0, + parameter integer XPA_CFG2 = 0, + parameter integer XPA_NUM_DACS = 0, + parameter integer XPA_NUM_DUCS = 0, + parameter XPA_PLL_USED = "EXTERNAL", + parameter integer XPA_SAMPLE_RATE_MSPS = 0 +)( + output CLK_DAC, + output CLK_DIST_OUT_NORTH, + output CLK_DIST_OUT_SOUTH, + output [15:0] DOUT, + output DRDY, + output PLL_DMON_OUT, + output PLL_REFCLK_OUT, + output [23:0] STATUS_COMMON, + output [23:0] STATUS_DAC0, + output [23:0] STATUS_DAC1, + output [23:0] STATUS_DAC2, + output [23:0] STATUS_DAC3, + output SYSREF_OUT_NORTH, + output SYSREF_OUT_SOUTH, + output T1_ALLOWED_SOUTH, + output VOUT0_N, + output VOUT0_P, + output VOUT1_N, + output VOUT1_P, + output VOUT2_N, + output VOUT2_P, + output VOUT3_N, + output VOUT3_P, + + input CLK_DIST_IN_NORTH, + input CLK_DIST_IN_SOUTH, + input CLK_FIFO_LM, + input [15:0] CONTROL_COMMON, + input [15:0] CONTROL_DAC0, + input [15:0] CONTROL_DAC1, + input [15:0] CONTROL_DAC2, + input [15:0] CONTROL_DAC3, + input DAC_CLK_N, + input DAC_CLK_P, + input [11:0] DADDR, + input [255:0] DATA_DAC0, + input [255:0] DATA_DAC1, + input [255:0] DATA_DAC2, + input [255:0] DATA_DAC3, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input FABRIC_CLK, + input PLL_MONCLK, + input PLL_REFCLK_IN, + input SYSREF_IN_NORTH, + input SYSREF_IN_SOUTH, + input SYSREF_N, + input SYSREF_P, + input T1_ALLOWED_NORTH +); + +// define constants + localparam MODULE_NAME = "RFDAC"; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "RFDAC_dr.v" +`else + reg [15:0] OPT_CLK_DIST_REG = OPT_CLK_DIST; + reg [152:1] SIM_DEVICE_REG = SIM_DEVICE; + reg [6:0] XPA_ACTIVE_DUTYCYCLE_REG = XPA_ACTIVE_DUTYCYCLE; + reg [15:0] XPA_CFG0_REG = XPA_CFG0; + reg [15:0] XPA_CFG1_REG = XPA_CFG1; + reg [15:0] XPA_CFG2_REG = XPA_CFG2; + reg [2:0] XPA_NUM_DACS_REG = XPA_NUM_DACS; + reg [2:0] XPA_NUM_DUCS_REG = XPA_NUM_DUCS; + reg [112:1] XPA_PLL_USED_REG = XPA_PLL_USED; + reg [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS; +`endif + +`ifdef XIL_XECLIB +reg glblGSR = 1'b0; +`else +tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_DAC_SPARE_out; + wire CLK_DAC_out; + wire CLK_DIST_OUT_NORTH_out; + wire CLK_DIST_OUT_SOUTH_out; + wire DRDY_out; + wire PLL_DMON_OUT_out; + wire PLL_REFCLK_OUT_out; + wire SYSREF_OUT_NORTH_out; + wire SYSREF_OUT_SOUTH_out; + wire T1_ALLOWED_SOUTH_out; + wire VOUT0_N_out; + wire VOUT0_P_out; + wire VOUT1_N_out; + wire VOUT1_P_out; + wire VOUT2_N_out; + wire VOUT2_P_out; + wire VOUT3_N_out; + wire VOUT3_P_out; + wire [15:0] DOUT_out; + wire [15:0] TEST_STATUS_out; + wire [1:0] PLL_SCAN_OUT_B_FD_out; + wire [23:0] STATUS_COMMON_out; + wire [23:0] STATUS_DAC0_out; + wire [23:0] STATUS_DAC1_out; + wire [23:0] STATUS_DAC2_out; + wire [23:0] STATUS_DAC3_out; + wire [299:0] TEST_SO_out; + + wire CLK_DIST_IN_NORTH_in; + wire CLK_DIST_IN_SOUTH_in; + wire CLK_FIFO_LM_in; + wire DAC_CLK_N_in; + wire DAC_CLK_P_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire FABRIC_CLK_in; + wire PLL_MONCLK_in; + wire PLL_REFCLK_IN_in; + wire PLL_SCAN_EN_B_FD_in; + wire PLL_SCAN_MODE_B_FD_in; + wire PLL_SCAN_RST_EN_FD_in; + wire SYSREF_IN_NORTH_in; + wire SYSREF_IN_SOUTH_in; + wire SYSREF_N_in; + wire SYSREF_P_in; + wire T1_ALLOWED_NORTH_in; + wire TEST_SCAN_MODE_B_in; + wire TEST_SCAN_RESET_in; + wire TEST_SE_B_in; + wire [11:0] DADDR_in; + wire [15:0] CONTROL_COMMON_in; + wire [15:0] CONTROL_DAC0_in; + wire [15:0] CONTROL_DAC1_in; + wire [15:0] CONTROL_DAC2_in; + wire [15:0] CONTROL_DAC3_in; + wire [15:0] DI_in; + wire [15:0] TEST_SCAN_CTRL_in; + wire [1:0] PLL_SCAN_CLK_FD_in; + wire [1:0] PLL_SCAN_IN_FD_in; + wire [255:0] DATA_DAC0_in; + wire [255:0] DATA_DAC1_in; + wire [255:0] DATA_DAC2_in; + wire [255:0] DATA_DAC3_in; + wire [299:0] TEST_SI_in; + wire [4:0] TEST_SCAN_CLK_in; + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire FABRIC_CLK_delay; + wire [11:0] DADDR_delay; + wire [15:0] CONTROL_COMMON_delay; + wire [15:0] CONTROL_DAC0_delay; + wire [15:0] CONTROL_DAC1_delay; + wire [15:0] CONTROL_DAC2_delay; + wire [15:0] CONTROL_DAC3_delay; + wire [15:0] DI_delay; + wire [255:0] DATA_DAC0_delay; + wire [255:0] DATA_DAC1_delay; + wire [255:0] DATA_DAC2_delay; + wire [255:0] DATA_DAC3_delay; +`endif + + real VOUT0_N_real; + real VOUT0_P_real; + real VOUT1_N_real; + real VOUT1_P_real; + real VOUT2_N_real; + real VOUT2_P_real; + real VOUT3_N_real; + real VOUT3_P_real; + + assign CLK_DAC = CLK_DAC_out; + assign CLK_DIST_OUT_NORTH = CLK_DIST_OUT_NORTH_out; + assign CLK_DIST_OUT_SOUTH = CLK_DIST_OUT_SOUTH_out; + assign DOUT = DOUT_out; + assign DRDY = DRDY_out; + assign PLL_DMON_OUT = PLL_DMON_OUT_out; + assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out; + assign STATUS_COMMON = STATUS_COMMON_out; + assign STATUS_DAC0 = STATUS_DAC0_out; + assign STATUS_DAC1 = STATUS_DAC1_out; + assign STATUS_DAC2 = STATUS_DAC2_out; + assign STATUS_DAC3 = STATUS_DAC3_out; + assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out; + assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out; + assign T1_ALLOWED_SOUTH = T1_ALLOWED_SOUTH_out; + assign VOUT0_N = VOUT0_N_out; + assign VOUT0_P = VOUT0_P_out; + assign VOUT1_N = VOUT1_N_out; + assign VOUT1_P = VOUT1_P_out; + assign VOUT2_N = VOUT2_N_out; + assign VOUT2_P = VOUT2_P_out; + assign VOUT3_N = VOUT3_N_out; + assign VOUT3_P = VOUT3_P_out; + +`ifdef XIL_TIMING + assign CONTROL_COMMON_in = CONTROL_COMMON_delay; + assign CONTROL_DAC0_in = CONTROL_DAC0_delay; + assign CONTROL_DAC1_in = CONTROL_DAC1_delay; + assign CONTROL_DAC2_in = CONTROL_DAC2_delay; + assign CONTROL_DAC3_in = CONTROL_DAC3_delay; + assign DADDR_in = DADDR_delay; + assign DATA_DAC0_in = DATA_DAC0_delay; + assign DATA_DAC1_in = DATA_DAC1_delay; + assign DATA_DAC2_in = DATA_DAC2_delay; + assign DATA_DAC3_in = DATA_DAC3_delay; + assign DCLK_in = DCLK_delay; + assign DEN_in = DEN_delay; + assign DI_in = DI_delay; + assign DWE_in = DWE_delay; + assign FABRIC_CLK_in = FABRIC_CLK_delay; +`else + assign CONTROL_COMMON_in = CONTROL_COMMON; + assign CONTROL_DAC0_in = CONTROL_DAC0; + assign CONTROL_DAC1_in = CONTROL_DAC1; + assign CONTROL_DAC2_in = CONTROL_DAC2; + assign CONTROL_DAC3_in = CONTROL_DAC3; + assign DADDR_in = DADDR; + assign DATA_DAC0_in = DATA_DAC0; + assign DATA_DAC1_in = DATA_DAC1; + assign DATA_DAC2_in = DATA_DAC2; + assign DATA_DAC3_in = DATA_DAC3; + assign DCLK_in = DCLK; + assign DEN_in = DEN; + assign DI_in = DI; + assign DWE_in = DWE; + assign FABRIC_CLK_in = FABRIC_CLK; +`endif + + assign CLK_DIST_IN_NORTH_in = CLK_DIST_IN_NORTH; + assign CLK_DIST_IN_SOUTH_in = CLK_DIST_IN_SOUTH; + assign CLK_FIFO_LM_in = CLK_FIFO_LM; + assign DAC_CLK_N_in = DAC_CLK_N; + assign DAC_CLK_P_in = DAC_CLK_P; + assign PLL_MONCLK_in = PLL_MONCLK; + assign PLL_REFCLK_IN_in = PLL_REFCLK_IN; + assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH; + assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH; + assign SYSREF_N_in = SYSREF_N; + assign SYSREF_P_in = SYSREF_P; + assign T1_ALLOWED_NORTH_in = T1_ALLOWED_NORTH; + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((OPT_CLK_DIST_REG < 0) || (OPT_CLK_DIST_REG > 65535))) begin + $display("Error: [Unisim %s-101] OPT_CLK_DIST attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, OPT_CLK_DIST_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_ACTIVE_DUTYCYCLE_REG < 0) || (XPA_ACTIVE_DUTYCYCLE_REG > 100))) begin + $display("Error: [Unisim %s-103] XPA_ACTIVE_DUTYCYCLE attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, XPA_ACTIVE_DUTYCYCLE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin + $display("Error: [Unisim %s-104] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin + $display("Error: [Unisim %s-105] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_CFG2_REG < 0) || (XPA_CFG2_REG > 65535))) begin + $display("Error: [Unisim %s-106] XPA_CFG2 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG2_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DACS_REG < 0) || (XPA_NUM_DACS_REG > 4))) begin + $display("Error: [Unisim %s-107] XPA_NUM_DACS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DACS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_NUM_DUCS_REG < 0) || (XPA_NUM_DUCS_REG > 4))) begin + $display("Error: [Unisim %s-108] XPA_NUM_DUCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DUCS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_PLL_USED_REG != "EXTERNAL") && + (XPA_PLL_USED_REG != "DISTRIBUTED_T1") && + (XPA_PLL_USED_REG != "INTERNAL_PLL"))) begin + $display("Error: [Unisim %s-109] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are EXTERNAL, DISTRIBUTED_T1 or INTERNAL_PLL. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin + $display("Error: [Unisim %s-110] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + + +assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off +assign TEST_SCAN_CLK_in = 5'b11111; // tie off + +assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_IN_FD_in = 2'b11; // tie off +assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off +assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off +assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off +assign TEST_SCAN_MODE_B_in = 1'b1; // tie off +assign TEST_SCAN_RESET_in = 1'b1; // tie off +assign TEST_SE_B_in = 1'b1; // tie off +assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off + + SIP_RFDAC SIP_RFDAC_INST ( + .OPT_CLK_DIST (OPT_CLK_DIST_REG), + .SIM_DEVICE (SIM_DEVICE_REG), + .XPA_ACTIVE_DUTYCYCLE (XPA_ACTIVE_DUTYCYCLE_REG), + .XPA_CFG0 (XPA_CFG0_REG), + .XPA_CFG1 (XPA_CFG1_REG), + .XPA_CFG2 (XPA_CFG2_REG), + .XPA_NUM_DACS (XPA_NUM_DACS_REG), + .XPA_NUM_DUCS (XPA_NUM_DUCS_REG), + .XPA_PLL_USED (XPA_PLL_USED_REG), + .XPA_SAMPLE_RATE_MSPS (XPA_SAMPLE_RATE_MSPS_REG), + .CLK_DAC (CLK_DAC_out), + .CLK_DAC_SPARE (CLK_DAC_SPARE_out), + .CLK_DIST_OUT_NORTH (CLK_DIST_OUT_NORTH_out), + .CLK_DIST_OUT_SOUTH (CLK_DIST_OUT_SOUTH_out), + .DOUT (DOUT_out), + .DRDY (DRDY_out), + .PLL_DMON_OUT (PLL_DMON_OUT_out), + .PLL_REFCLK_OUT (PLL_REFCLK_OUT_out), + .PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out), + .STATUS_COMMON (STATUS_COMMON_out), + .STATUS_DAC0 (STATUS_DAC0_out), + .STATUS_DAC1 (STATUS_DAC1_out), + .STATUS_DAC2 (STATUS_DAC2_out), + .STATUS_DAC3 (STATUS_DAC3_out), + .SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out), + .SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out), + .T1_ALLOWED_SOUTH (T1_ALLOWED_SOUTH_out), + .TEST_SO (TEST_SO_out), + .TEST_STATUS (TEST_STATUS_out), + .VOUT0_N (VOUT0_N_real), + .VOUT0_P (VOUT0_P_real), + .VOUT1_N (VOUT1_N_real), + .VOUT1_P (VOUT1_P_real), + .VOUT2_N (VOUT2_N_real), + .VOUT2_P (VOUT2_P_real), + .VOUT3_N (VOUT3_N_real), + .VOUT3_P (VOUT3_P_real), + .CLK_DIST_IN_NORTH (CLK_DIST_IN_NORTH_in), + .CLK_DIST_IN_SOUTH (CLK_DIST_IN_SOUTH_in), + .CLK_FIFO_LM (CLK_FIFO_LM_in), + .CONTROL_COMMON (CONTROL_COMMON_in), + .CONTROL_DAC0 (CONTROL_DAC0_in), + .CONTROL_DAC1 (CONTROL_DAC1_in), + .CONTROL_DAC2 (CONTROL_DAC2_in), + .CONTROL_DAC3 (CONTROL_DAC3_in), + .DAC_CLK_N (DAC_CLK_N_in), + .DAC_CLK_P (DAC_CLK_P_in), + .DADDR (DADDR_in), + .DATA_DAC0 (DATA_DAC0_in), + .DATA_DAC1 (DATA_DAC1_in), + .DATA_DAC2 (DATA_DAC2_in), + .DATA_DAC3 (DATA_DAC3_in), + .DCLK (DCLK_in), + .DEN (DEN_in), + .DI (DI_in), + .DWE (DWE_in), + .FABRIC_CLK (FABRIC_CLK_in), + .PLL_MONCLK (PLL_MONCLK_in), + .PLL_REFCLK_IN (PLL_REFCLK_IN_in), + .PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in), + .PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in), + .PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in), + .PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in), + .PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in), + .SYSREF_IN_NORTH (SYSREF_IN_NORTH_in), + .SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in), + .SYSREF_N (SYSREF_N_in), + .SYSREF_P (SYSREF_P_in), + .T1_ALLOWED_NORTH (T1_ALLOWED_NORTH_in), + .TEST_SCAN_CLK (TEST_SCAN_CLK_in), + .TEST_SCAN_CTRL (TEST_SCAN_CTRL_in), + .TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in), + .TEST_SCAN_RESET (TEST_SCAN_RESET_in), + .TEST_SE_B (TEST_SE_B_in), + .TEST_SI (TEST_SI_in), + .GSR (glblGSR) + ); + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_XECLIB + specify + (DCLK => DOUT[0]) = (100:100:100, 100:100:100); + (DCLK => DOUT[10]) = (100:100:100, 100:100:100); + (DCLK => DOUT[11]) = (100:100:100, 100:100:100); + (DCLK => DOUT[12]) = (100:100:100, 100:100:100); + (DCLK => DOUT[13]) = (100:100:100, 100:100:100); + (DCLK => DOUT[14]) = (100:100:100, 100:100:100); + (DCLK => DOUT[15]) = (100:100:100, 100:100:100); + (DCLK => DOUT[1]) = (100:100:100, 100:100:100); + (DCLK => DOUT[2]) = (100:100:100, 100:100:100); + (DCLK => DOUT[3]) = (100:100:100, 100:100:100); + (DCLK => DOUT[4]) = (100:100:100, 100:100:100); + (DCLK => DOUT[5]) = (100:100:100, 100:100:100); + (DCLK => DOUT[6]) = (100:100:100, 100:100:100); + (DCLK => DOUT[7]) = (100:100:100, 100:100:100); + (DCLK => DOUT[8]) = (100:100:100, 100:100:100); + (DCLK => DOUT[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC0[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC0[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC0[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC0[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC0[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC1[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC1[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC1[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC1[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC1[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC2[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC2[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC2[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC2[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC2[9]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC3[10]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC3[11]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC3[12]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC3[8]) = (100:100:100, 100:100:100); + (FABRIC_CLK => STATUS_DAC3[9]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK_DAC, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (negedge FABRIC_CLK, 0:0:0, notifier); + $period (negedge PLL_DMON_OUT, 0:0:0, notifier); + $period (negedge PLL_MONCLK, 0:0:0, notifier); + $period (negedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (negedge PLL_REFCLK_OUT, 0:0:0, notifier); + $period (posedge CLK_DAC, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $period (posedge FABRIC_CLK, 0:0:0, notifier); + $period (posedge PLL_DMON_OUT, 0:0:0, notifier); + $period (posedge PLL_MONCLK, 0:0:0, notifier); + $period (posedge PLL_REFCLK_IN, 0:0:0, notifier); + $period (posedge PLL_REFCLK_OUT, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]); + $setuphold (posedge DCLK, negedge CONTROL_DAC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_DAC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_DAC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_DAC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_DAC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_DAC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[14]); + $setuphold (posedge DCLK, negedge CONTROL_DAC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[13]); + $setuphold (posedge DCLK, negedge CONTROL_DAC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[14]); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]); + $setuphold (posedge DCLK, posedge CONTROL_DAC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_DAC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_DAC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_DAC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_DAC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_DAC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[14]); + $setuphold (posedge DCLK, posedge CONTROL_DAC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[13]); + $setuphold (posedge DCLK, posedge CONTROL_DAC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[14]); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]); + $setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay); + $setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[0]); + $setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[0]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[100]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[101]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[102]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[103]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[104]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[105]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[106]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[107]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[108]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[109]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[10]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[110]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[111]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[112]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[113]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[114]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[115]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[116]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[117]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[118]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[119]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[11]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[120]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[121]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[122]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[123]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[124]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[125]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[126]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[127]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[128]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[129]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[12]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[130]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[131]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[132]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[133]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[134]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[135]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[136]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[137]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[138]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[139]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[13]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[140]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[141]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[142]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[143]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[144]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[145]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[146]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[147]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[148]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[149]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[14]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[150]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[151]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[152]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[153]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[154]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[155]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[156]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[157]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[158]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[159]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[15]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[160]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[161]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[162]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[163]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[164]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[165]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[166]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[167]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[168]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[169]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[16]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[170]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[171]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[172]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[173]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[174]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[175]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[176]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[177]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[178]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[179]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[17]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[180]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[181]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[182]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[183]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[184]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[185]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[186]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[187]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[188]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[189]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[18]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[190]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[191]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[192]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[193]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[194]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[195]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[196]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[197]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[198]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[199]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[19]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[1]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[200]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[201]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[202]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[203]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[204]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[205]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[206]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[207]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[208]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[209]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[20]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[210]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[211]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[212]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[213]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[214]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[215]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[216]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[217]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[218]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[219]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[21]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[220]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[221]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[222]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[223]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[224]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[225]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[226]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[227]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[228]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[229]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[22]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[230]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[231]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[232]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[233]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[234]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[235]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[236]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[237]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[238]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[239]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[23]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[240]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[241]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[242]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[243]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[244]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[245]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[246]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[247]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[248]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[249]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[24]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[250]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[251]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[252]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[253]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[254]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[255]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[25]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[26]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[27]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[28]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[29]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[2]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[30]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[31]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[32]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[33]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[34]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[35]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[36]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[37]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[38]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[39]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[3]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[40]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[41]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[42]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[43]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[44]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[45]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[46]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[47]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[48]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[49]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[4]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[50]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[51]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[52]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[53]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[54]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[55]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[56]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[57]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[58]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[59]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[5]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[60]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[61]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[62]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[63]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[64]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[65]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[66]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[67]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[68]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[69]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[6]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[70]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[71]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[72]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[73]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[74]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[75]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[76]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[77]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[78]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[79]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[7]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[80]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[81]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[82]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[83]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[84]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[85]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[86]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[87]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[88]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[89]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[8]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[90]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[91]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[92]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[93]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[94]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[95]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[96]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[97]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[98]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[99]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[9]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[0]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[100]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[101]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[102]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[103]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[104]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[105]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[106]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[107]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[108]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[109]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[10]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[110]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[111]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[112]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[113]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[114]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[115]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[116]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[117]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[118]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[119]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[11]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[120]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[121]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[122]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[123]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[124]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[125]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[126]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[127]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[128]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[129]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[12]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[130]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[131]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[132]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[133]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[134]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[135]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[136]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[137]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[138]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[139]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[13]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[140]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[141]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[142]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[143]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[144]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[145]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[146]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[147]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[148]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[149]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[14]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[150]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[151]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[152]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[153]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[154]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[155]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[156]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[157]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[158]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[159]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[15]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[160]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[161]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[162]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[163]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[164]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[165]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[166]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[167]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[168]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[169]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[16]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[170]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[171]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[172]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[173]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[174]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[175]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[176]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[177]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[178]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[179]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[17]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[180]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[181]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[182]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[183]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[184]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[185]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[186]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[187]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[188]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[189]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[18]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[190]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[191]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[192]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[193]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[194]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[195]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[196]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[197]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[198]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[199]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[19]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[1]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[200]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[201]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[202]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[203]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[204]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[205]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[206]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[207]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[208]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[209]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[20]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[210]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[211]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[212]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[213]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[214]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[215]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[216]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[217]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[218]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[219]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[21]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[220]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[221]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[222]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[223]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[224]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[225]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[226]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[227]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[228]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[229]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[22]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[230]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[231]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[232]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[233]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[234]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[235]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[236]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[237]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[238]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[239]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[23]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[240]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[241]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[242]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[243]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[244]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[245]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[246]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[247]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[248]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[249]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[24]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[250]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[251]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[252]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[253]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[254]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[255]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[25]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[26]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[27]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[28]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[29]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[2]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[30]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[31]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[32]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[33]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[34]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[35]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[36]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[37]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[38]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[39]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[3]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[40]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[41]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[42]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[43]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[44]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[45]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[46]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[47]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[48]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[49]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[4]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[50]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[51]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[52]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[53]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[54]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[55]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[56]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[57]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[58]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[59]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[5]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[60]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[61]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[62]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[63]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[64]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[65]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[66]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[67]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[68]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[69]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[6]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[70]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[71]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[72]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[73]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[74]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[75]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[76]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[77]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[78]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[79]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[7]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[80]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[81]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[82]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[83]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[84]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[85]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[86]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[87]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[88]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[89]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[8]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[90]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[91]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[92]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[93]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[94]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[95]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[96]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[97]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[98]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[99]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[9]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[0]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[100]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[101]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[102]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[103]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[104]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[105]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[106]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[107]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[108]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[109]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[10]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[110]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[111]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[112]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[113]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[114]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[115]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[116]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[117]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[118]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[119]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[11]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[120]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[121]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[122]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[123]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[124]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[125]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[126]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[127]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[128]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[129]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[12]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[130]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[131]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[132]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[133]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[134]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[135]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[136]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[137]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[138]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[139]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[13]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[140]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[141]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[142]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[143]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[144]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[145]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[146]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[147]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[148]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[149]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[14]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[150]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[151]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[152]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[153]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[154]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[155]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[156]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[157]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[158]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[159]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[15]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[160]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[161]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[162]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[163]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[164]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[165]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[166]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[167]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[168]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[169]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[16]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[170]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[171]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[172]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[173]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[174]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[175]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[176]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[177]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[178]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[179]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[17]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[180]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[181]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[182]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[183]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[184]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[185]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[186]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[187]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[188]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[189]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[18]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[190]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[191]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[192]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[193]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[194]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[195]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[196]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[197]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[198]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[199]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[19]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[1]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[200]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[201]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[202]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[203]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[204]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[205]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[206]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[207]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[208]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[209]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[20]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[210]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[211]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[212]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[213]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[214]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[215]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[216]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[217]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[218]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[219]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[21]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[220]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[221]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[222]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[223]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[224]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[225]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[226]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[227]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[228]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[229]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[22]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[230]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[231]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[232]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[233]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[234]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[235]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[236]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[237]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[238]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[239]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[23]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[240]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[241]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[242]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[243]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[244]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[245]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[246]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[247]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[248]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[249]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[24]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[250]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[251]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[252]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[253]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[254]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[255]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[25]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[26]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[27]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[28]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[29]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[2]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[30]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[31]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[32]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[33]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[34]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[35]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[36]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[37]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[38]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[39]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[3]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[40]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[41]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[42]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[43]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[44]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[45]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[46]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[47]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[48]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[49]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[4]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[50]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[51]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[52]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[53]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[54]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[55]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[56]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[57]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[58]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[59]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[5]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[60]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[61]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[62]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[63]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[64]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[65]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[66]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[67]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[68]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[69]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[6]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[70]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[71]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[72]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[73]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[74]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[75]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[76]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[77]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[78]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[79]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[7]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[80]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[81]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[82]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[83]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[84]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[85]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[86]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[87]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[88]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[89]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[8]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[90]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[91]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[92]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[93]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[94]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[95]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[96]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[97]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[98]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[99]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[9]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[0]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[100]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[101]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[102]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[103]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[104]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[105]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[106]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[107]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[108]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[109]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[10]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[110]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[111]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[112]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[113]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[114]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[115]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[116]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[117]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[118]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[119]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[11]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[120]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[121]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[122]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[123]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[124]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[125]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[126]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[127]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[128]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[129]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[12]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[130]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[131]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[132]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[133]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[134]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[135]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[136]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[137]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[138]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[139]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[13]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[140]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[141]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[142]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[143]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[144]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[145]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[146]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[147]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[148]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[149]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[14]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[150]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[151]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[152]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[153]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[154]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[155]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[156]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[157]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[158]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[159]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[15]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[160]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[161]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[162]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[163]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[164]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[165]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[166]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[167]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[168]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[169]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[16]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[170]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[171]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[172]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[173]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[174]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[175]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[176]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[177]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[178]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[179]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[17]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[180]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[181]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[182]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[183]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[184]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[185]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[186]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[187]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[188]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[189]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[18]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[190]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[191]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[192]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[193]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[194]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[195]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[196]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[197]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[198]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[199]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[19]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[1]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[200]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[201]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[202]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[203]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[204]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[205]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[206]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[207]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[208]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[209]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[20]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[210]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[211]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[212]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[213]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[214]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[215]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[216]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[217]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[218]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[219]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[21]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[220]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[221]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[222]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[223]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[224]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[225]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[226]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[227]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[228]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[229]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[22]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[230]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[231]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[232]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[233]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[234]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[235]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[236]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[237]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[238]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[239]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[23]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[240]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[241]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[242]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[243]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[244]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[245]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[246]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[247]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[248]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[249]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[24]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[250]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[251]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[252]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[253]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[254]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[255]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[25]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[26]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[27]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[28]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[29]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[2]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[30]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[31]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[32]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[33]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[34]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[35]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[36]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[37]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[38]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[39]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[3]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[40]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[41]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[42]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[43]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[44]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[45]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[46]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[47]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[48]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[49]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[4]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[50]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[51]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[52]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[53]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[54]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[55]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[56]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[57]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[58]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[59]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[5]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[60]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[61]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[62]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[63]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[64]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[65]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[66]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[67]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[68]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[69]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[6]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[70]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[71]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[72]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[73]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[74]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[75]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[76]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[77]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[78]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[79]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[7]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[80]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[81]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[82]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[83]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[84]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[85]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[86]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[87]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[88]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[89]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[8]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[90]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[91]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[92]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[93]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[94]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[95]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[96]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[97]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[98]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[99]); + $setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[9]); + $setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[0]); + $setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[0]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[100]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[101]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[102]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[103]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[104]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[105]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[106]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[107]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[108]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[109]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[10]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[110]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[111]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[112]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[113]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[114]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[115]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[116]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[117]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[118]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[119]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[11]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[120]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[121]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[122]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[123]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[124]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[125]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[126]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[127]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[128]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[129]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[12]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[130]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[131]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[132]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[133]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[134]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[135]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[136]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[137]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[138]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[139]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[13]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[140]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[141]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[142]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[143]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[144]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[145]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[146]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[147]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[148]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[149]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[14]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[150]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[151]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[152]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[153]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[154]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[155]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[156]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[157]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[158]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[159]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[160]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[161]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[162]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[163]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[164]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[165]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[166]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[167]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[168]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[169]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[16]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[170]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[171]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[172]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[173]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[174]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[175]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[176]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[177]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[178]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[179]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[17]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[180]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[181]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[182]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[183]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[184]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[185]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[186]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[187]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[188]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[189]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[18]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[190]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[191]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[192]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[193]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[194]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[195]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[196]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[197]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[198]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[199]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[19]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[1]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[200]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[201]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[202]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[203]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[204]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[205]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[206]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[207]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[208]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[209]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[20]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[210]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[211]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[212]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[213]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[214]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[215]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[216]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[217]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[218]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[219]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[21]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[220]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[221]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[222]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[223]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[224]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[225]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[226]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[227]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[228]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[229]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[22]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[230]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[231]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[232]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[233]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[234]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[235]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[236]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[237]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[238]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[239]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[23]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[240]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[241]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[242]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[243]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[244]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[245]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[246]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[247]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[248]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[249]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[24]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[250]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[251]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[252]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[253]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[254]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[255]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[25]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[26]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[27]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[28]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[29]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[2]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[30]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[31]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[32]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[33]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[34]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[35]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[36]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[37]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[38]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[39]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[3]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[40]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[41]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[42]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[43]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[44]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[45]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[46]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[47]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[48]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[49]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[4]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[50]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[51]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[52]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[53]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[54]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[55]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[56]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[57]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[58]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[59]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[5]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[60]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[61]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[62]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[63]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[64]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[65]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[66]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[67]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[68]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[69]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[6]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[70]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[71]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[72]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[73]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[74]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[75]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[76]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[77]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[78]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[79]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[7]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[80]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[81]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[82]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[83]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[84]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[85]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[86]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[87]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[88]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[89]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[8]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[90]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[91]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[92]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[93]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[94]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[95]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[96]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[97]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[98]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[99]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[9]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[0]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[100]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[101]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[102]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[103]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[104]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[105]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[106]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[107]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[108]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[109]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[10]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[110]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[111]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[112]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[113]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[114]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[115]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[116]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[117]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[118]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[119]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[11]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[120]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[121]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[122]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[123]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[124]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[125]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[126]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[127]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[128]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[129]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[12]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[130]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[131]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[132]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[133]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[134]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[135]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[136]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[137]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[138]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[139]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[13]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[140]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[141]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[142]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[143]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[144]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[145]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[146]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[147]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[148]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[149]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[14]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[150]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[151]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[152]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[153]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[154]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[155]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[156]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[157]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[158]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[159]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[160]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[161]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[162]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[163]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[164]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[165]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[166]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[167]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[168]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[169]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[16]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[170]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[171]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[172]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[173]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[174]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[175]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[176]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[177]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[178]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[179]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[17]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[180]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[181]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[182]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[183]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[184]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[185]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[186]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[187]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[188]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[189]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[18]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[190]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[191]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[192]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[193]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[194]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[195]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[196]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[197]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[198]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[199]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[19]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[1]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[200]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[201]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[202]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[203]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[204]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[205]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[206]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[207]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[208]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[209]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[20]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[210]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[211]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[212]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[213]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[214]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[215]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[216]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[217]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[218]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[219]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[21]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[220]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[221]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[222]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[223]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[224]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[225]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[226]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[227]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[228]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[229]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[22]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[230]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[231]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[232]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[233]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[234]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[235]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[236]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[237]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[238]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[239]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[23]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[240]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[241]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[242]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[243]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[244]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[245]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[246]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[247]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[248]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[249]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[24]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[250]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[251]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[252]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[253]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[254]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[255]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[25]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[26]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[27]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[28]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[29]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[2]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[30]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[31]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[32]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[33]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[34]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[35]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[36]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[37]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[38]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[39]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[3]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[40]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[41]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[42]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[43]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[44]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[45]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[46]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[47]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[48]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[49]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[4]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[50]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[51]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[52]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[53]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[54]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[55]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[56]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[57]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[58]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[59]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[5]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[60]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[61]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[62]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[63]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[64]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[65]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[66]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[67]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[68]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[69]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[6]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[70]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[71]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[72]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[73]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[74]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[75]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[76]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[77]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[78]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[79]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[7]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[80]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[81]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[82]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[83]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[84]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[85]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[86]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[87]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[88]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[89]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[8]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[90]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[91]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[92]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[93]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[94]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[95]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[96]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[97]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[98]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[99]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[9]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[0]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[100]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[101]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[102]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[103]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[104]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[105]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[106]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[107]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[108]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[109]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[10]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[110]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[111]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[112]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[113]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[114]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[115]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[116]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[117]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[118]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[119]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[11]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[120]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[121]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[122]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[123]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[124]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[125]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[126]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[127]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[128]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[129]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[12]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[130]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[131]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[132]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[133]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[134]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[135]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[136]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[137]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[138]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[139]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[13]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[140]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[141]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[142]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[143]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[144]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[145]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[146]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[147]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[148]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[149]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[14]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[150]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[151]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[152]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[153]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[154]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[155]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[156]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[157]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[158]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[159]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[160]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[161]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[162]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[163]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[164]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[165]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[166]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[167]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[168]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[169]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[16]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[170]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[171]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[172]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[173]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[174]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[175]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[176]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[177]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[178]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[179]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[17]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[180]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[181]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[182]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[183]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[184]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[185]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[186]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[187]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[188]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[189]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[18]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[190]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[191]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[192]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[193]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[194]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[195]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[196]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[197]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[198]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[199]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[19]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[1]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[200]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[201]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[202]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[203]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[204]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[205]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[206]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[207]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[208]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[209]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[20]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[210]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[211]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[212]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[213]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[214]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[215]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[216]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[217]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[218]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[219]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[21]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[220]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[221]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[222]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[223]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[224]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[225]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[226]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[227]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[228]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[229]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[22]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[230]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[231]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[232]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[233]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[234]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[235]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[236]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[237]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[238]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[239]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[23]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[240]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[241]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[242]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[243]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[244]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[245]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[246]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[247]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[248]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[249]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[24]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[250]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[251]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[252]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[253]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[254]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[255]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[25]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[26]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[27]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[28]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[29]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[2]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[30]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[31]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[32]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[33]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[34]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[35]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[36]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[37]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[38]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[39]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[3]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[40]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[41]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[42]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[43]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[44]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[45]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[46]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[47]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[48]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[49]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[4]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[50]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[51]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[52]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[53]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[54]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[55]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[56]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[57]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[58]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[59]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[5]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[60]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[61]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[62]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[63]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[64]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[65]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[66]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[67]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[68]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[69]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[6]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[70]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[71]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[72]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[73]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[74]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[75]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[76]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[77]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[78]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[79]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[7]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[80]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[81]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[82]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[83]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[84]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[85]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[86]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[87]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[88]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[89]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[8]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[90]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[91]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[92]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[93]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[94]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[95]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[96]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[97]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[98]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[99]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[9]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[0]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[100]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[101]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[102]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[103]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[104]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[105]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[106]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[107]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[108]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[109]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[10]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[110]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[111]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[112]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[113]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[114]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[115]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[116]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[117]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[118]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[119]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[11]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[120]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[121]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[122]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[123]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[124]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[125]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[126]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[127]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[128]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[129]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[12]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[130]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[131]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[132]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[133]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[134]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[135]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[136]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[137]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[138]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[139]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[13]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[140]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[141]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[142]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[143]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[144]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[145]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[146]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[147]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[148]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[149]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[14]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[150]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[151]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[152]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[153]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[154]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[155]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[156]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[157]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[158]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[159]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[15]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[160]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[161]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[162]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[163]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[164]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[165]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[166]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[167]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[168]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[169]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[16]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[170]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[171]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[172]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[173]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[174]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[175]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[176]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[177]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[178]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[179]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[17]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[180]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[181]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[182]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[183]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[184]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[185]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[186]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[187]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[188]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[189]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[18]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[190]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[191]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[192]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[193]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[194]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[195]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[196]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[197]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[198]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[199]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[19]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[1]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[200]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[201]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[202]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[203]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[204]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[205]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[206]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[207]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[208]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[209]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[20]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[210]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[211]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[212]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[213]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[214]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[215]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[216]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[217]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[218]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[219]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[21]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[220]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[221]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[222]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[223]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[224]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[225]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[226]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[227]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[228]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[229]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[22]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[230]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[231]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[232]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[233]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[234]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[235]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[236]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[237]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[238]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[239]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[23]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[240]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[241]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[242]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[243]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[244]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[245]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[246]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[247]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[248]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[249]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[24]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[250]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[251]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[252]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[253]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[254]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[255]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[25]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[26]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[27]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[28]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[29]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[2]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[30]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[31]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[32]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[33]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[34]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[35]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[36]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[37]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[38]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[39]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[3]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[40]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[41]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[42]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[43]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[44]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[45]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[46]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[47]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[48]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[49]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[4]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[50]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[51]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[52]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[53]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[54]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[55]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[56]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[57]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[58]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[59]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[5]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[60]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[61]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[62]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[63]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[64]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[65]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[66]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[67]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[68]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[69]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[6]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[70]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[71]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[72]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[73]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[74]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[75]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[76]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[77]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[78]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[79]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[7]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[80]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[81]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[82]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[83]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[84]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[85]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[86]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[87]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[88]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[89]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[8]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[90]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[91]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[92]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[93]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[94]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[95]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[96]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[97]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[98]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[99]); + $setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[9]); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (negedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (negedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); + $width (posedge FABRIC_CLK, 0:0:0, 0, notifier); + $width (posedge PLL_MONCLK, 0:0:0, 0, notifier); + $width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RIU_OR.v b/verilog/src/unisims/RIU_OR.v new file mode 100644 index 0000000..cda22ff --- /dev/null +++ b/verilog/src/unisims/RIU_OR.v @@ -0,0 +1,145 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RIU_OR +// /___/ /\ Filename : RIU_OR.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RIU_OR #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0 +)( + output [15:0] RIU_RD_DATA, + output RIU_RD_VALID, + + input [15:0] RIU_RD_DATA_LOW, + input [15:0] RIU_RD_DATA_UPP, + input RIU_RD_VALID_LOW, + input RIU_RD_VALID_UPP +); + +// define constants + localparam MODULE_NAME = "RIU_OR"; + +// Parameter encodings and registers + localparam SIM_DEVICE_ULTRASCALE = 0; + localparam SIM_DEVICE_ULTRASCALE_PLUS = 1; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 2; + localparam SIM_DEVICE_ULTRASCALE_PLUS_ES2 = 3; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +//`ifdef XIL_DR +// `include "RIU_OR_dr.v" +//`else + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; +//`endif + + wire [1:0] SIM_DEVICE_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire RIU_RD_VALID_out; + wire [15:0] RIU_RD_DATA_out; + + wire RIU_RD_VALID_LOW_in; + wire RIU_RD_VALID_UPP_in; + wire [15:0] RIU_RD_DATA_LOW_in; + wire [15:0] RIU_RD_DATA_UPP_in; + + assign RIU_RD_DATA = RIU_RD_DATA_out; + assign RIU_RD_VALID = RIU_RD_VALID_out; + + assign RIU_RD_DATA_LOW_in = RIU_RD_DATA_LOW; + assign RIU_RD_DATA_UPP_in = RIU_RD_DATA_UPP; + assign RIU_RD_VALID_LOW_in = RIU_RD_VALID_LOW; + assign RIU_RD_VALID_UPP_in = RIU_RD_VALID_UPP; + + assign SIM_DEVICE_BIN = + (SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 : + SIM_DEVICE_ULTRASCALE; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-102] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign RIU_RD_DATA_out = RIU_RD_DATA_UPP_in | RIU_RD_DATA_LOW_in; + assign RIU_RD_VALID_out = RIU_RD_VALID_UPP_in & RIU_RD_VALID_LOW_in; + + specify + (RIU_RD_DATA_LOW *> RIU_RD_DATA) = (0:0:0, 0:0:0); + (RIU_RD_DATA_UPP *> RIU_RD_DATA) = (0:0:0, 0:0:0); + (RIU_RD_VALID_LOW => RIU_RD_VALID) = (0:0:0, 0:0:0); + (RIU_RD_VALID_UPP => RIU_RD_VALID) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RXTX_BITSLICE.v b/verilog/src/unisims/RXTX_BITSLICE.v new file mode 100644 index 0000000..c0e3dbd --- /dev/null +++ b/verilog/src/unisims/RXTX_BITSLICE.v @@ -0,0 +1,1001 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RXTX_BITSLICE +// /___/ /\ Filename : RXTX_BITSLICE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RXTX_BITSLICE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter ENABLE_PRE_EMPHASIS = "FALSE", + parameter FIFO_SYNC_MODE = "FALSE", + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_RX_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0, + parameter [0:0] IS_RX_RST_INVERTED = 1'b0, + parameter [0:0] IS_TX_CLK_INVERTED = 1'b0, + parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0, + parameter [0:0] IS_TX_RST_INVERTED = 1'b0, + parameter LOOPBACK = "FALSE", + parameter NATIVE_ODELAY_BYPASS = "FALSE", + parameter RX_DATA_TYPE = "DATA", + parameter integer RX_DATA_WIDTH = 8, + parameter RX_DELAY_FORMAT = "TIME", + parameter RX_DELAY_TYPE = "FIXED", + parameter integer RX_DELAY_VALUE = 0, + parameter real RX_REFCLK_FREQUENCY = 300.0, + parameter RX_UPDATE_MODE = "ASYNC", + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter TBYTE_CTL = "TBYTE_IN", + parameter integer TX_DATA_WIDTH = 8, + parameter TX_DELAY_FORMAT = "TIME", + parameter TX_DELAY_TYPE = "FIXED", + parameter integer TX_DELAY_VALUE = 0, + parameter TX_OUTPUT_PHASE_90 = "FALSE", + parameter real TX_REFCLK_FREQUENCY = 300.0, + parameter TX_UPDATE_MODE = "ASYNC" +)( + output FIFO_EMPTY, + output FIFO_WRCLK_OUT, + output O, + output [7:0] Q, + output [39:0] RX_BIT_CTRL_OUT, + output [8:0] RX_CNTVALUEOUT, + output [39:0] TX_BIT_CTRL_OUT, + output [8:0] TX_CNTVALUEOUT, + output T_OUT, + + input [7:0] D, + input DATAIN, + input FIFO_RD_CLK, + input FIFO_RD_EN, + input [39:0] RX_BIT_CTRL_IN, + input RX_CE, + input RX_CLK, + input [8:0] RX_CNTVALUEIN, + input RX_EN_VTC, + input RX_INC, + input RX_LOAD, + input RX_RST, + input RX_RST_DLY, + input T, + input TBYTE_IN, + input [39:0] TX_BIT_CTRL_IN, + input TX_CE, + input TX_CLK, + input [8:0] TX_CNTVALUEIN, + input TX_EN_VTC, + input TX_INC, + input TX_LOAD, + input TX_RST, + input TX_RST_DLY +); + +// define constants + localparam MODULE_NAME = "RXTX_BITSLICE"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only + + reg warning_flag = 1'b1; +`ifdef XIL_DR + `include "RXTX_BITSLICE_dr.v" +`else + localparam [40:1] ENABLE_PRE_EMPHASIS_REG = ENABLE_PRE_EMPHASIS; + localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE; + localparam [0:0] INIT_REG = INIT; + localparam [0:0] IS_RX_CLK_INVERTED_REG = IS_RX_CLK_INVERTED; + localparam [0:0] IS_RX_RST_DLY_INVERTED_REG = IS_RX_RST_DLY_INVERTED; + localparam [0:0] IS_RX_RST_INVERTED_REG = IS_RX_RST_INVERTED; + localparam [0:0] IS_TX_CLK_INVERTED_REG = IS_TX_CLK_INVERTED; + localparam [0:0] IS_TX_RST_DLY_INVERTED_REG = IS_TX_RST_DLY_INVERTED; + localparam [0:0] IS_TX_RST_INVERTED_REG = IS_TX_RST_INVERTED; + localparam [40:1] LOOPBACK_REG = LOOPBACK; + localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS; + localparam [112:1] RX_DATA_TYPE_REG = RX_DATA_TYPE; + localparam [31:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH; + localparam [40:1] RX_DELAY_FORMAT_REG = RX_DELAY_FORMAT; + localparam [64:1] RX_DELAY_TYPE_REG = RX_DELAY_TYPE; + localparam [31:0] RX_DELAY_VALUE_REG = RX_DELAY_VALUE; + localparam real RX_REFCLK_FREQUENCY_REG = RX_REFCLK_FREQUENCY; + localparam [48:1] RX_UPDATE_MODE_REG = RX_UPDATE_MODE; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL; + localparam [31:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH; + localparam [40:1] TX_DELAY_FORMAT_REG = TX_DELAY_FORMAT; + localparam [64:1] TX_DELAY_TYPE_REG = TX_DELAY_TYPE; + localparam [31:0] TX_DELAY_VALUE_REG = TX_DELAY_VALUE; + localparam [40:1] TX_OUTPUT_PHASE_90_REG = TX_OUTPUT_PHASE_90; + localparam real TX_REFCLK_FREQUENCY_REG = TX_REFCLK_FREQUENCY; + localparam [48:1] TX_UPDATE_MODE_REG = TX_UPDATE_MODE; +`endif + + localparam [40:1] DDR_DIS_DQS_REG = "TRUE"; + localparam [40:1] FIFO_ENABLE_REG = "TRUE"; + localparam [5:0] SPARE_REG = 6'b000000; + localparam [0:0] RX_DC_ADJ_EN_REG = 1'b0; + localparam [2:0] RX_FDLY_REG = 3'b010; + localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE"; + localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE"; + localparam [40:1] TXRX_LOOPBACK_REG = "FALSE"; + localparam [0:0] TX_DC_ADJ_EN_REG = 1'b0; + localparam [2:0] TX_FDLY_REG = 3'b010; + localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE"; + localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE"; + localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE"; + + wire IS_RX_CLK_INVERTED_BIN; + wire IS_RX_RST_DLY_INVERTED_BIN; + wire IS_RX_RST_INVERTED_BIN; + wire IS_TX_CLK_INVERTED_BIN; + wire IS_TX_RST_DLY_INVERTED_BIN; + wire IS_TX_RST_INVERTED_BIN; + wire [63:0] RX_REFCLK_FREQUENCY_BIN; + wire [63:0] SIM_VERSION_BIN; + wire [63:0] TX_REFCLK_FREQUENCY_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire IDELAY_DATAIN0_out; + wire IDELAY_DATAOUT_out; + wire ODELAY_DATAIN0_out; + wire ODELAY_DATAOUT_out; + + wire FIFO_EMPTY_out; + wire FIFO_WRCLK_OUT_out; + wire O_out; + wire TX2RX_CASC_OUT_out; + wire T_OUT_out; + wire [39:0] RX_BIT_CTRL_OUT_out; + wire [39:0] TX_BIT_CTRL_OUT_out; + wire [7:0] Q_out; + wire [8:0] RX_CNTVALUEOUT_out; + wire [8:0] TX_CNTVALUEOUT_out; + + wire FIFO_EMPTY_delay; + wire FIFO_WRCLK_OUT_delay; + wire O_delay; + wire T_OUT_delay; + wire [39:0] RX_BIT_CTRL_OUT_delay; + wire [39:0] TX_BIT_CTRL_OUT_delay; + wire [7:0] Q_delay; + wire [8:0] RX_CNTVALUEOUT_delay; + wire [8:0] TX_CNTVALUEOUT_delay; + + wire DATAIN_in; + wire FIFO_RD_CLK_in; + wire FIFO_RD_EN_in; + wire IFD_CE_in; + wire OFD_CE_in; + wire RX2TX_CASC_RETURN_IN_in; + wire RX_CE_in; + wire RX_CLKDIV_in; + wire RX_CLK_C_B_in; + wire RX_CLK_C_in; + wire RX_CLK_in; + wire RX_DATAIN1_in; + wire RX_EN_VTC_in; + wire RX_INC_in; + wire RX_LOAD_in; + wire RX_RST_DLY_in; + wire RX_RST_in; + wire TBYTE_IN_in; + wire TX2RX_CASC_IN_in; + wire TX_CE_in; + wire TX_CLK_in; + wire TX_EN_VTC_in; + wire TX_INC_in; + wire TX_LOAD_in; + wire TX_OCLKDIV_in; + wire TX_OCLK_in; + wire TX_RST_DLY_in; + wire TX_RST_in; + wire T_in; + wire [39:0] RX_BIT_CTRL_IN_in; + wire [39:0] TX_BIT_CTRL_IN_in; + wire [7:0] D_in; + wire [8:0] RX_CNTVALUEIN_in; + wire [8:0] TX_CNTVALUEIN_in; + + wire DATAIN_delay; + wire FIFO_RD_CLK_delay; + wire FIFO_RD_EN_delay; + wire RX_CE_delay; + wire RX_CLK_delay; + wire RX_EN_VTC_delay; + wire RX_INC_delay; + wire RX_LOAD_delay; + wire RX_RST_DLY_delay; + wire RX_RST_delay; + wire TBYTE_IN_delay; + wire TX_CE_delay; + wire TX_CLK_delay; + wire TX_EN_VTC_delay; + wire TX_INC_delay; + wire TX_LOAD_delay; + wire TX_RST_DLY_delay; + wire TX_RST_delay; + wire T_delay; + wire [39:0] RX_BIT_CTRL_IN_delay; + wire [39:0] TX_BIT_CTRL_IN_delay; + wire [7:0] D_delay; + wire [8:0] RX_CNTVALUEIN_delay; + wire [8:0] TX_CNTVALUEIN_delay; + + assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay; + assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay; + assign #(out_delay) O = O_delay; + assign #(out_delay) Q = Q_delay; + assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay; + assign #(out_delay) RX_CNTVALUEOUT = (RX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : RX_CNTVALUEOUT_delay; + assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay; + assign #(out_delay) TX_CNTVALUEOUT = (TX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : TX_CNTVALUEOUT_delay; + assign #(out_delay) T_OUT = T_OUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK; + assign #(inclk_delay) RX_CLK_delay = RX_CLK; + assign #(inclk_delay) TX_CLK_delay = TX_CLK; + + assign #(in_delay) D_delay = D; + assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN; + assign #(in_delay) RX_CE_delay = RX_CE; + assign #(in_delay) RX_CNTVALUEIN_delay = RX_CNTVALUEIN; + assign #(in_delay) RX_INC_delay = RX_INC; + assign #(in_delay) RX_LOAD_delay = RX_LOAD; + assign #(in_delay) TX_CE_delay = TX_CE; + assign #(in_delay) TX_CNTVALUEIN_delay = TX_CNTVALUEIN; + assign #(in_delay) TX_INC_delay = TX_INC; + assign #(in_delay) TX_LOAD_delay = TX_LOAD; + assign #(in_delay) TX_BIT_CTRL_IN_delay[25] = TX_BIT_CTRL_IN[25]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[26] = TX_BIT_CTRL_IN[26]; +`endif + +// inputs with no timing checks + assign #(in_delay) DATAIN_delay = DATAIN; + assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN; + assign #(in_delay) RX_EN_VTC_delay = RX_EN_VTC; + assign #(in_delay) RX_RST_DLY_delay = RX_RST_DLY; + assign #(in_delay) RX_RST_delay = RX_RST; + assign #(in_delay) TBYTE_IN_delay = TBYTE_IN; + assign #(in_delay) TX_BIT_CTRL_IN_delay[0] = TX_BIT_CTRL_IN[0]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[1] = TX_BIT_CTRL_IN[1]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[2] = TX_BIT_CTRL_IN[2]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[3] = TX_BIT_CTRL_IN[3]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[4] = TX_BIT_CTRL_IN[4]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[5] = TX_BIT_CTRL_IN[5]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[6] = TX_BIT_CTRL_IN[6]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[7] = TX_BIT_CTRL_IN[7]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[8] = TX_BIT_CTRL_IN[8]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[9] = TX_BIT_CTRL_IN[9]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[10] = TX_BIT_CTRL_IN[10]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[11] = TX_BIT_CTRL_IN[11]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[12] = TX_BIT_CTRL_IN[12]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[13] = TX_BIT_CTRL_IN[13]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[14] = TX_BIT_CTRL_IN[14]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[15] = TX_BIT_CTRL_IN[15]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[16] = TX_BIT_CTRL_IN[16]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[17] = TX_BIT_CTRL_IN[17]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[18] = TX_BIT_CTRL_IN[18]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[19] = TX_BIT_CTRL_IN[19]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[20] = TX_BIT_CTRL_IN[20]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[21] = TX_BIT_CTRL_IN[21]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[22] = TX_BIT_CTRL_IN[22]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[23] = TX_BIT_CTRL_IN[23]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[24] = TX_BIT_CTRL_IN[24]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[27] = TX_BIT_CTRL_IN[27]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[28] = TX_BIT_CTRL_IN[28]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[29] = TX_BIT_CTRL_IN[29]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[30] = TX_BIT_CTRL_IN[30]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[31] = TX_BIT_CTRL_IN[31]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[32] = TX_BIT_CTRL_IN[32]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[33] = TX_BIT_CTRL_IN[33]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[34] = TX_BIT_CTRL_IN[34]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[35] = TX_BIT_CTRL_IN[35]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[36] = TX_BIT_CTRL_IN[36]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[37] = TX_BIT_CTRL_IN[37]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[38] = TX_BIT_CTRL_IN[38]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[39] = TX_BIT_CTRL_IN[39]; + assign #(in_delay) TX_EN_VTC_delay = TX_EN_VTC; + assign #(in_delay) TX_RST_DLY_delay = TX_RST_DLY; + assign #(in_delay) TX_RST_delay = TX_RST; + assign #(in_delay) T_delay = T; + + assign FIFO_EMPTY_delay = FIFO_EMPTY_out; + assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out; + assign O_delay = O_out; + assign Q_delay = Q_out; + assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out; + assign RX_CNTVALUEOUT_delay = RX_CNTVALUEOUT_out; + assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out; + assign TX_CNTVALUEOUT_delay = TX_CNTVALUEOUT_out; + assign T_OUT_delay = T_OUT_out; + + assign DATAIN_in = DATAIN_delay; + assign D_in = D_delay; + assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay; + assign FIFO_RD_EN_in = FIFO_RD_EN_delay; + assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay; + assign RX_CE_in = RX_CE_delay; + assign RX_CLK_in = RX_CLK_delay ^ IS_RX_CLK_INVERTED_BIN; + assign RX_CNTVALUEIN_in = RX_CNTVALUEIN_delay; + assign RX_EN_VTC_in = RX_EN_VTC_delay; + assign RX_INC_in = RX_INC_delay; + assign RX_LOAD_in = RX_LOAD_delay; + assign RX_RST_DLY_in = RX_RST_DLY_delay ^ IS_RX_RST_DLY_INVERTED_BIN; + assign RX_RST_in = RX_RST_delay ^ IS_RX_RST_INVERTED_BIN; + assign TBYTE_IN_in = TBYTE_IN_delay; + assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay; + assign TX_CE_in = TX_CE_delay; + assign TX_CLK_in = TX_CLK_delay ^ IS_TX_CLK_INVERTED_BIN; + assign TX_CNTVALUEIN_in = TX_CNTVALUEIN_delay; + assign TX_EN_VTC_in = TX_EN_VTC_delay; + assign TX_INC_in = TX_INC_delay; + assign TX_LOAD_in = TX_LOAD_delay; + assign TX_RST_DLY_in = TX_RST_DLY_delay ^ IS_TX_RST_DLY_INVERTED_BIN; + assign TX_RST_in = TX_RST_delay ^ IS_TX_RST_INVERTED_BIN; + assign T_in = T_delay; + + assign IS_RX_CLK_INVERTED_BIN = IS_RX_CLK_INVERTED_REG; + + assign IS_RX_RST_DLY_INVERTED_BIN = IS_RX_RST_DLY_INVERTED_REG; + + assign IS_RX_RST_INVERTED_BIN = IS_RX_RST_INVERTED_REG; + + assign IS_TX_CLK_INVERTED_BIN = IS_TX_CLK_INVERTED_REG; + + assign IS_TX_RST_DLY_INVERTED_BIN = IS_TX_RST_DLY_INVERTED_REG; + + assign IS_TX_RST_INVERTED_BIN = IS_TX_RST_INVERTED_REG; + + assign RX_REFCLK_FREQUENCY_BIN = RX_REFCLK_FREQUENCY_REG * 1000; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + assign TX_REFCLK_FREQUENCY_BIN = TX_REFCLK_FREQUENCY_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @(RX_EN_VTC_in or TX_EN_VTC_in) begin + if ((RX_EN_VTC_in ===0 || TX_EN_VTC_in ===0 )&& (RX_DELAY_FORMAT_REG == "TIME" || TX_DELAY_FORMAT_REG == "TIME") && warning_flag == 1'b1 ) begin + $display("Warning: [Unisim %s-1] BISC Calibration : DELAY_FORMAT set to TIME with RX_EN_VTC/TX_EN_VTC signal set to 0. In hardware, when the RX_EN_VTC/TX_EN_VTC signal is low during the initial calibration process, the BISC will never complete and the DLY_RDY and VTC_RDY status signals from the BITSLICE_CONTROL remain low. Simulation will not reflect this behavior. In simulation, the DLY_RDY and VTC_RDY from the BITSLICE_CONTROL will assert high. You should ensure the RX_EN_VTC/TX_EN_VTC signal is held high during initial BISC self calibration to ensure BISC completes in hardware. See Select IO Userguide UG571 for more information.Instance: %m", MODULE_NAME); + warning_flag = 1'b0; + end + end + + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((ENABLE_PRE_EMPHASIS_REG != "FALSE") && + (ENABLE_PRE_EMPHASIS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-102] ENABLE_PRE_EMPHASIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENABLE_PRE_EMPHASIS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIFO_SYNC_MODE_REG != "FALSE") && + (FIFO_SYNC_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-103] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((LOOPBACK_REG != "FALSE") && + (LOOPBACK_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] LOOPBACK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LOOPBACK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((NATIVE_ODELAY_BYPASS_REG != "FALSE") && + (NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_TYPE_REG != "DATA") && + (RX_DATA_TYPE_REG != "CLOCK") && + (RX_DATA_TYPE_REG != "DATA_AND_CLOCK") && + (RX_DATA_TYPE_REG != "SERIAL"))) begin + $display("Error: [Unisim %s-113] RX_DATA_TYPE attribute is set to %s. Legal values for this attribute are DATA, CLOCK, DATA_AND_CLOCK or SERIAL. Instance: %m", MODULE_NAME, RX_DATA_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DATA_WIDTH_REG != 8) && + (RX_DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-114] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DELAY_FORMAT_REG != "TIME") && + (RX_DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-116] RX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, RX_DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RX_DELAY_TYPE_REG != "FIXED") && + (RX_DELAY_TYPE_REG != "VAR_LOAD") && + (RX_DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-117] RX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, RX_DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-118] RX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, RX_DELAY_VALUE_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-118] RX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, RX_DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (RX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (RX_REFCLK_FREQUENCY_REG < 300.0 || RX_REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-122] RX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, RX_REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (RX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (RX_REFCLK_FREQUENCY_REG < 200.0 || RX_REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-122] RX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, RX_REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + ((RX_UPDATE_MODE_REG != "ASYNC") && + (RX_UPDATE_MODE_REG != "MANUAL") && + (RX_UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-123] RX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, RX_UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-124] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-125] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TBYTE_CTL_REG != "TBYTE_IN") && + (TBYTE_CTL_REG != "T"))) begin + $display("Error: [Unisim %s-126] TBYTE_CTL attribute is set to %s. Legal values for this attribute are TBYTE_IN or T. Instance: %m", MODULE_NAME, TBYTE_CTL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DATA_WIDTH_REG != 8) && + (TX_DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-128] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DELAY_FORMAT_REG != "TIME") && + (TX_DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-130] TX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, TX_DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_DELAY_TYPE_REG != "FIXED") && + (TX_DELAY_TYPE_REG != "VAR_LOAD") && + (TX_DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-131] TX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, TX_DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-132] TX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-132] TX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TX_OUTPUT_PHASE_90_REG != "FALSE") && + (TX_OUTPUT_PHASE_90_REG != "TRUE"))) begin + $display("Error: [Unisim %s-134] TX_OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_OUTPUT_PHASE_90_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (TX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (TX_REFCLK_FREQUENCY_REG < 300.0 || TX_REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-136] TX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (TX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (TX_REFCLK_FREQUENCY_REG < 200.0 || TX_REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-136] TX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + ((TX_UPDATE_MODE_REG != "ASYNC") && + (TX_UPDATE_MODE_REG != "MANUAL") && + (TX_UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-138] TX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, TX_UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (TX_DELAY_FORMAT_REG != RX_DELAY_FORMAT_REG)) begin + $display("Error: [Unisim %s-139] TX_DELAY_FORMAT = %s is not same as RX_DELAY_FORMAT = %s. [RX/TX]_DELAY_FORMAT attributes must be set to same value. Instance: %m", MODULE_NAME, TX_DELAY_FORMAT_REG, RX_DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (RX_DELAY_FORMAT_REG == TX_DELAY_FORMAT_REG && TX_DELAY_FORMAT_REG == "TIME" && TX_DELAY_VALUE_REG != RX_DELAY_VALUE_REG)) begin + $display("Error: [Unisim %s-140] [RX/TX]_DELAY_FORMAT is set to TIME and TX_DELAY_VALUE is set to %d is and RX_DELAY_VALUE is set to %d. Both RX_DELAY_VALUE and TX_DELAY_VALUE must be set to same value when [RX/TX]_DELAY_FORMAT is set to TIME. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG, RX_DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (TX_REFCLK_FREQUENCY_REG != RX_REFCLK_FREQUENCY_REG)) begin + $display("Error: [Unisim %s-141] TX_REFCLK_FREQUENCY = %f is not same as RX_REFCLK_FREQUENCY = %f. [RX/TX]_REFCLK_FREQUENCY attributes must be set to same value. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG, RX_REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (TX_DATA_WIDTH_REG != RX_DATA_WIDTH_REG)) begin + $display("Error: [Unisim %s-142] TX_DATA_WIDTH is set to %d and RX_DATA_WIDTH is set to %d. Both RX_DATA_WIDTH and TX_DATA_WIDTH attributes must be set to same value. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG, RX_DATA_WIDTH_REG); + attr_err = 1'b1; + end + + + if (attr_err == 1'b1) #1 $finish; + end + + assign RX_CLKDIV_in = 1'b1; // tie off + assign RX_CLK_C_B_in = 1'b1; // tie off + assign RX_CLK_C_in = 1'b1; // tie off + assign TX_OCLKDIV_in = 1'b1; // tie off + assign TX_OCLK_in = 1'b1; // tie off + + assign IFD_CE_in = 1'b0; // tie off + assign OFD_CE_in = 1'b0; // tie off + assign RX2TX_CASC_RETURN_IN_in = 1'b1; // tie off + assign RX_DATAIN1_in = 1'b0; // tie off + assign TX2RX_CASC_IN_in = 1'b1; // tie off + +generate + +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_RXTX_BITSLICE_D1 SIP_RXTX_BITSLICE_INST ( + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .FIFO_ENABLE (FIFO_ENABLE_REG), + .SPARE (SPARE_REG), + .INIT (INIT_REG), + .LOOPBACK (LOOPBACK_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .RX_DATA_TYPE (RX_DATA_TYPE_REG), + .RX_DATA_WIDTH (RX_DATA_WIDTH_REG), + .RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG), + .RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG), + .RX_DELAY_TYPE (RX_DELAY_TYPE_REG), + .RX_DELAY_VALUE (RX_DELAY_VALUE_REG), + .RX_FDLY (RX_FDLY_REG), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN), + .RX_UPDATE_MODE (RX_UPDATE_MODE_REG), + .TBYTE_CTL (TBYTE_CTL_REG), + .TXRX_LOOPBACK (TXRX_LOOPBACK_REG), + .TX_DATA_WIDTH (TX_DATA_WIDTH_REG), + .TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG), + .TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG), + .TX_DELAY_TYPE (TX_DELAY_TYPE_REG), + .TX_DELAY_VALUE (TX_DELAY_VALUE_REG), + .TX_FDLY (TX_FDLY_REG), + .TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .TX_UPDATE_MODE (TX_UPDATE_MODE_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .FIFO_EMPTY (FIFO_EMPTY_out), + .FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out), + .O (O_out), + .Q (Q_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .RX_CNTVALUEOUT (RX_CNTVALUEOUT_out), + .TX2RX_CASC_OUT (TX2RX_CASC_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .TX_CNTVALUEOUT (TX_CNTVALUEOUT_out), + .T_OUT (T_OUT_out), + .D (D_in), + .DATAIN (DATAIN_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .OFD_CE (OFD_CE_in), + .RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_CE (RX_CE_in), + .RX_CLK (RX_CLK_in), + .RX_CLKDIV (RX_CLKDIV_in), + .RX_CLK_C (RX_CLK_C_in), + .RX_CLK_C_B (RX_CLK_C_B_in), + .RX_CNTVALUEIN (RX_CNTVALUEIN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .RX_EN_VTC (RX_EN_VTC_in), + .RX_INC (RX_INC_in), + .RX_LOAD (RX_LOAD_in), + .RX_RST (RX_RST_in), + .RX_RST_DLY (RX_RST_DLY_in), + .T (T_in), + .TBYTE_IN (TBYTE_IN_in), + .TX2RX_CASC_IN (TX2RX_CASC_IN_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .TX_CE (TX_CE_in), + .TX_CLK (TX_CLK_in), + .TX_CNTVALUEIN (TX_CNTVALUEIN_in), + .TX_EN_VTC (TX_EN_VTC_in), + .TX_INC (TX_INC_in), + .TX_LOAD (TX_LOAD_in), + .TX_OCLK (TX_OCLK_in), + .TX_OCLKDIV (TX_OCLKDIV_in), + .TX_RST (TX_RST_in), + .TX_RST_DLY (TX_RST_DLY_in), + .SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out), + .SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out), + .SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out), + .SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out), + .GSR (glblGSR) + ); + end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + + SIP_RXTX_BITSLICE_K2 SIP_RXTX_BITSLICE_INST ( + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .INIT (INIT_REG), + .LOOPBACK (LOOPBACK_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .RX_DATA_TYPE (RX_DATA_TYPE_REG), + .RX_DATA_WIDTH (RX_DATA_WIDTH_REG), + .RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG), + .RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG), + .RX_DELAY_TYPE (RX_DELAY_TYPE_REG), + .RX_DELAY_VALUE (RX_DELAY_VALUE_REG), + .RX_FDLY (RX_FDLY_REG), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN), + .RX_UPDATE_MODE (RX_UPDATE_MODE_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .TBYTE_CTL (TBYTE_CTL_REG), + .TXRX_LOOPBACK (TXRX_LOOPBACK_REG), + .TX_DATA_WIDTH (TX_DATA_WIDTH_REG), + .TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG), + .TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG), + .TX_DELAY_TYPE (TX_DELAY_TYPE_REG), + .TX_DELAY_VALUE (TX_DELAY_VALUE_REG), + .TX_FDLY (TX_FDLY_REG), + .TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .TX_UPDATE_MODE (TX_UPDATE_MODE_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .FIFO_EMPTY (FIFO_EMPTY_out), + .FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out), + .O (O_out), + .Q (Q_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .RX_CNTVALUEOUT (RX_CNTVALUEOUT_out), + .TX2RX_CASC_OUT (TX2RX_CASC_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .TX_CNTVALUEOUT (TX_CNTVALUEOUT_out), + .T_OUT (T_OUT_out), + .D (D_in), + .DATAIN (DATAIN_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .OFD_CE (OFD_CE_in), + .RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_CE (RX_CE_in), + .RX_CLK (RX_CLK_in), + .RX_CLKDIV (RX_CLKDIV_in), + .RX_CLK_C (RX_CLK_C_in), + .RX_CLK_C_B (RX_CLK_C_B_in), + .RX_CNTVALUEIN (RX_CNTVALUEIN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .RX_EN_VTC (RX_EN_VTC_in), + .RX_INC (RX_INC_in), + .RX_LOAD (RX_LOAD_in), + .RX_RST (RX_RST_in), + .RX_RST_DLY (RX_RST_DLY_in), + .T (T_in), + .TBYTE_IN (TBYTE_IN_in), + .TX2RX_CASC_IN (TX2RX_CASC_IN_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .TX_CE (TX_CE_in), + .TX_CLK (TX_CLK_in), + .TX_CNTVALUEIN (TX_CNTVALUEIN_in), + .TX_EN_VTC (TX_EN_VTC_in), + .TX_INC (TX_INC_in), + .TX_LOAD (TX_LOAD_in), + .TX_OCLK (TX_OCLK_in), + .TX_OCLKDIV (TX_OCLKDIV_in), + .TX_RST (TX_RST_in), + .TX_RST_DLY (TX_RST_DLY_in), + .SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out), + .SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out), + .SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out), + .SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out), + .GSR (glblGSR) + ); +end +endgenerate + +`ifdef XIL_TIMING + wire rx_clk_en_n; + wire rx_clk_en_p; + wire tx_clk_en_n; + wire tx_clk_en_p; + + assign rx_clk_en_n = IS_RX_CLK_INVERTED_BIN; + assign rx_clk_en_p = ~IS_RX_CLK_INVERTED_BIN; + assign tx_clk_en_n = IS_TX_CLK_INVERTED_BIN; + assign tx_clk_en_p = ~IS_TX_CLK_INVERTED_BIN; +`endif + + specify + (DATAIN => Q[4]) = (0:0:0, 0:0:0); + (DATAIN => Q[5]) = (0:0:0, 0:0:0); + (DATAIN => RX_BIT_CTRL_OUT[9]) = (0:0:0, 0:0:0); + (D[0] => O) = (0:0:0, 0:0:0); + (D[1] => T_OUT) = (0:0:0, 0:0:0); + (FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[0]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[1]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[2]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[3]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[4]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[5]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[6]) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => Q[7]) = (100:100:100, 100:100:100); + (RX_BIT_CTRL_IN[20] => FIFO_WRCLK_OUT) = (0:0:0, 0:0:0); + (RX_CLK => RX_CNTVALUEOUT[0]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[1]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[2]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[3]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[4]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[5]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[6]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[7]) = (100:100:100, 100:100:100); + (RX_CLK => RX_CNTVALUEOUT[8]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[0]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[1]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[2]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[3]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[4]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[5]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[6]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[7]) = (100:100:100, 100:100:100); + (TX_CLK => TX_CNTVALUEOUT[8]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge FIFO_RD_CLK, 0:0:0, notifier); + $period (negedge RX_BIT_CTRL_IN[20], 0:0:0, notifier); + $period (negedge RX_CLK, 0:0:0, notifier); + $period (negedge TX_BIT_CTRL_IN[25], 0:0:0, notifier); + $period (negedge TX_BIT_CTRL_IN[26], 0:0:0, notifier); + $period (negedge TX_CLK, 0:0:0, notifier); + $period (posedge FIFO_RD_CLK, 0:0:0, notifier); + $period (posedge RX_BIT_CTRL_IN[20], 0:0:0, notifier); + $period (posedge RX_CLK, 0:0:0, notifier); + $period (posedge TX_BIT_CTRL_IN[25], 0:0:0, notifier); + $period (posedge TX_BIT_CTRL_IN[26], 0:0:0, notifier); + $period (posedge TX_CLK, 0:0:0, notifier); + $setuphold (negedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CE_delay); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[0]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[1]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[2]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[3]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[4]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[5]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[6]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[7]); + $setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[8]); + $setuphold (negedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_INC_delay); + $setuphold (negedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_LOAD_delay); + $setuphold (negedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CE_delay); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[0]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[1]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[2]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[3]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[4]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[5]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[6]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[7]); + $setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[8]); + $setuphold (negedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_INC_delay); + $setuphold (negedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_LOAD_delay); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]); + $setuphold (negedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CE_delay); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[0]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[1]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[2]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[3]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[4]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[5]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[6]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[7]); + $setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[8]); + $setuphold (negedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_INC_delay); + $setuphold (negedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_LOAD_delay); + $setuphold (negedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CE_delay); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[0]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[1]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[2]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[3]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[4]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[5]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[6]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[7]); + $setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[8]); + $setuphold (negedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_INC_delay); + $setuphold (negedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_LOAD_delay); + $setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $setuphold (posedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CE_delay); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[0]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[1]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[2]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[3]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[4]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[5]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[6]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[7]); + $setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[8]); + $setuphold (posedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_INC_delay); + $setuphold (posedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_LOAD_delay); + $setuphold (posedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CE_delay); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[0]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[1]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[2]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[3]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[4]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[5]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[6]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[7]); + $setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[8]); + $setuphold (posedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_INC_delay); + $setuphold (posedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_LOAD_delay); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CE_delay); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[0]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[1]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[2]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[3]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[4]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[5]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[6]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[7]); + $setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[8]); + $setuphold (posedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_INC_delay); + $setuphold (posedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_LOAD_delay); + $setuphold (posedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CE_delay); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[0]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[1]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[2]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[3]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[4]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[5]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[6]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[7]); + $setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[8]); + $setuphold (posedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_INC_delay); + $setuphold (posedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_LOAD_delay); + $width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (negedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier); + $width (negedge RX_CLK, 0:0:0, 0, notifier); + $width (negedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier); + $width (negedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier); + $width (negedge TX_CLK, 0:0:0, 0, notifier); + $width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (posedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier); + $width (posedge RX_CLK, 0:0:0, 0, notifier); + $width (posedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier); + $width (posedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier); + $width (posedge TX_CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/RX_BITSLICE.v b/verilog/src/unisims/RX_BITSLICE.v new file mode 100644 index 0000000..c5403ea --- /dev/null +++ b/verilog/src/unisims/RX_BITSLICE.v @@ -0,0 +1,644 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / RX_BITSLICE +// /___/ /\ Filename : RX_BITSLICE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module RX_BITSLICE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter CASCADE = "FALSE", + parameter DATA_TYPE = "DATA", + parameter integer DATA_WIDTH = 8, + parameter DELAY_FORMAT = "TIME", + parameter DELAY_TYPE = "FIXED", + parameter integer DELAY_VALUE = 0, + parameter integer DELAY_VALUE_EXT = 0, + parameter FIFO_SYNC_MODE = "FALSE", + parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0, + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REFCLK_FREQUENCY = 300.0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter UPDATE_MODE = "ASYNC", + parameter UPDATE_MODE_EXT = "ASYNC" +)( + output [8:0] CNTVALUEOUT, + output [8:0] CNTVALUEOUT_EXT, + output FIFO_EMPTY, + output FIFO_WRCLK_OUT, + output [7:0] Q, + output [39:0] RX_BIT_CTRL_OUT, + output [39:0] TX_BIT_CTRL_OUT, + + input CE, + input CE_EXT, + input CLK, + input CLK_EXT, + input [8:0] CNTVALUEIN, + input [8:0] CNTVALUEIN_EXT, + input DATAIN, + input EN_VTC, + input EN_VTC_EXT, + input FIFO_RD_CLK, + input FIFO_RD_EN, + input INC, + input INC_EXT, + input LOAD, + input LOAD_EXT, + input RST, + input RST_DLY, + input RST_DLY_EXT, + input [39:0] RX_BIT_CTRL_IN, + input [39:0] TX_BIT_CTRL_IN +); + +// define constants + localparam MODULE_NAME = "RX_BITSLICE"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only + reg warning_flag = 1'b1; +`ifdef XIL_DR + `include "RX_BITSLICE_dr.v" +`else + localparam [40:1] CASCADE_REG = CASCADE; + localparam [112:1] DATA_TYPE_REG = DATA_TYPE; + localparam [31:0] DATA_WIDTH_REG = DATA_WIDTH; + localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT; + localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE; + localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE; + localparam [31:0] DELAY_VALUE_EXT_REG = DELAY_VALUE_EXT; + localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE; + localparam [0:0] IS_CLK_EXT_INVERTED_REG = IS_CLK_EXT_INVERTED; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_DLY_EXT_INVERTED_REG = IS_RST_DLY_EXT_INVERTED; + localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE; + localparam [48:1] UPDATE_MODE_EXT_REG = UPDATE_MODE_EXT; +`endif + + localparam [0:0] DC_ADJ_EN_REG = 1'b0; + localparam [0:0] DC_ADJ_EN_EXT_REG = 1'b0; + localparam [40:1] DDR_DIS_DQS_REG = "TRUE"; + localparam [40:1] FIFO_ENABLE_REG = "TRUE"; + localparam [5:0] SPARE_REG = 6'b000000; + localparam [2:0] FDLY_REG = 3'b010; + localparam [2:0] FDLY_EXT_REG = 3'b010; + localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE"; + localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE"; + localparam [64:1] TBYTE_CTL_REG = "T"; + localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE"; + localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE"; + localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE"; + + wire IS_CLK_EXT_INVERTED_BIN; + wire IS_CLK_INVERTED_BIN; + wire IS_RST_DLY_EXT_INVERTED_BIN; + wire IS_RST_DLY_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire [63:0] REFCLK_FREQUENCY_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire FIFO_EMPTY_out; + wire FIFO_WRCLK_OUT_out; + wire [39:0] RX_BIT_CTRL_OUT_out; + wire [39:0] TX_BIT_CTRL_OUT_out; + wire [7:0] Q_out; + wire [8:0] CNTVALUEOUT_EXT_out; + wire [8:0] CNTVALUEOUT_out; + + wire FIFO_EMPTY_delay; + wire FIFO_WRCLK_OUT_delay; + wire [39:0] RX_BIT_CTRL_OUT_delay; + wire [39:0] TX_BIT_CTRL_OUT_delay; + wire [7:0] Q_delay; + wire [8:0] CNTVALUEOUT_EXT_delay; + wire [8:0] CNTVALUEOUT_delay; + + wire CE_EXT_in; + wire CE_in; + wire CLK_EXT_in; + wire CLK_in; + wire DATAIN_in; + wire EN_VTC_EXT_in; + wire EN_VTC_in; + wire FIFO_RD_CLK_in; + wire FIFO_RD_EN_in; + wire IFD_CE_in; + wire INC_EXT_in; + wire INC_in; + wire LOAD_EXT_in; + wire LOAD_in; + wire OFD_CE_in; + wire RST_DLY_EXT_in; + wire RST_DLY_in; + wire RST_in; + wire RX_DATAIN1_in; + wire TX_RST_in; + wire T_in; + wire [39:0] RX_BIT_CTRL_IN_in; + wire [39:0] TX_BIT_CTRL_IN_in; + wire [7:0] TX_D_in; + wire [8:0] CNTVALUEIN_EXT_in; + wire [8:0] CNTVALUEIN_in; + + wire CE_EXT_delay; + wire CE_delay; + wire CLK_EXT_delay; + wire CLK_delay; + wire DATAIN_delay; + wire EN_VTC_EXT_delay; + wire EN_VTC_delay; + wire FIFO_RD_CLK_delay; + wire FIFO_RD_EN_delay; + wire INC_EXT_delay; + wire INC_delay; + wire LOAD_EXT_delay; + wire LOAD_delay; + wire RST_DLY_EXT_delay; + wire RST_DLY_delay; + wire RST_delay; + wire [39:0] RX_BIT_CTRL_IN_delay; + wire [39:0] TX_BIT_CTRL_IN_delay; + wire [8:0] CNTVALUEIN_EXT_delay; + wire [8:0] CNTVALUEIN_delay; + wire IDELAY_DATAIN0_out; + wire IDELAY_DATAOUT_out; + + + assign #(out_delay) CNTVALUEOUT = (EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : CNTVALUEOUT_delay; + assign #(out_delay) CNTVALUEOUT_EXT = CNTVALUEOUT_EXT_delay; + assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay; + assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay; + assign #(out_delay) Q = Q_delay; + assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay; + assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLK_EXT_delay = CLK_EXT; + assign #(inclk_delay) CLK_delay = CLK; + + assign #(in_delay) CE_EXT_delay = CE_EXT; + assign #(in_delay) CE_delay = CE; + assign #(in_delay) CNTVALUEIN_EXT_delay = CNTVALUEIN_EXT; + assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN; + assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN; + assign #(in_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK; + assign #(in_delay) INC_EXT_delay = INC_EXT; + assign #(in_delay) INC_delay = INC; + assign #(in_delay) LOAD_EXT_delay = LOAD_EXT; + assign #(in_delay) LOAD_delay = LOAD; +`endif + +// inputs with no timing checks + assign #(in_delay) DATAIN_delay = DATAIN; + assign #(in_delay) EN_VTC_EXT_delay = EN_VTC_EXT; + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) RST_DLY_EXT_delay = RST_DLY_EXT; + assign #(in_delay) RST_DLY_delay = RST_DLY; + assign #(in_delay) RST_delay = RST; + assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN; + assign #(in_delay) TX_BIT_CTRL_IN_delay = TX_BIT_CTRL_IN; + + assign CNTVALUEOUT_EXT_delay = CNTVALUEOUT_EXT_out; + assign CNTVALUEOUT_delay = CNTVALUEOUT_out; + assign FIFO_EMPTY_delay = FIFO_EMPTY_out; + assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out; + assign Q_delay = Q_out; + assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out; + assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out; + + assign CE_EXT_in = CE_EXT_delay; + assign CE_in = CE_delay; + assign CLK_EXT_in = CLK_EXT_delay ^ IS_CLK_EXT_INVERTED_BIN; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign CNTVALUEIN_EXT_in = CNTVALUEIN_EXT_delay; + assign CNTVALUEIN_in = CNTVALUEIN_delay; + assign DATAIN_in = DATAIN_delay; + assign EN_VTC_EXT_in = EN_VTC_EXT_delay; + assign EN_VTC_in = EN_VTC_delay; + assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay; + assign FIFO_RD_EN_in = FIFO_RD_EN_delay; + assign INC_EXT_in = INC_EXT_delay; + assign INC_in = INC_delay; + assign LOAD_EXT_in = LOAD_EXT_delay; + assign LOAD_in = LOAD_delay; + assign RST_DLY_EXT_in = RST_DLY_EXT_delay ^ IS_RST_DLY_EXT_INVERTED_BIN; + assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN; + assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN; + assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay; + assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay; + + assign IS_CLK_EXT_INVERTED_BIN = IS_CLK_EXT_INVERTED_REG; + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign IS_RST_DLY_EXT_INVERTED_BIN = IS_RST_DLY_EXT_INVERTED_REG; + + assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @(EN_VTC_in) begin + if (EN_VTC_in ===0 && DELAY_FORMAT_REG == "TIME" && warning_flag === 1'b1 ) begin + $display("Warning: [Unisim %s-1] BISC Calibration : DELAY_FORMAT set to TIME with EN_VTC signal set to 0. In hardware, when the EN_VTC signal is low during the initial calibration process, the BISC will never complete and the DLY_RDY and VTC_RDY status signals from the BITSLICE_CONTROL remain low. Simulation will not reflect this behavior. In simulation, the DLY_RDY and VTC_RDY from the BITSLICE_CONTROL will assert high. You should ensure the EN_VTC signal is held high during initial BISC self calibration to ensure BISC completes in hardware. See Select IO Userguide UG571 for more information.Instance: %m", MODULE_NAME); + warning_flag = 1'b0; + end + end + + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CASCADE_REG != "FALSE") && + (CASCADE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-101] CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CASCADE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATA_TYPE_REG != "DATA") && + (DATA_TYPE_REG != "CLOCK") && + (DATA_TYPE_REG != "DATA_AND_CLOCK") && + (DATA_TYPE_REG != "SERIAL"))) begin + $display("Error: [Unisim %s-102] DATA_TYPE attribute is set to %s. Legal values for this attribute are DATA, CLOCK, DATA_AND_CLOCK or SERIAL. Instance: %m", MODULE_NAME, DATA_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DATA_WIDTH_REG != 8) && + (DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-103] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_FORMAT_REG != "TIME") && + (DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-107] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_TYPE_REG != "FIXED") && + (DELAY_TYPE_REG != "VAR_LOAD") && + (DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-108] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-109] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-109] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_EXT_REG < 0) || (DELAY_VALUE_EXT_REG > 1250)))) begin + $display("Error: [Unisim %s-110] DELAY_VALUE_EXT attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_EXT_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_EXT_REG < 0) || (DELAY_VALUE_EXT_REG > 1100)))) begin + $display("Error: [Unisim %s-110] DELAY_VALUE_EXT attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_EXT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((FIFO_SYNC_MODE_REG != "FALSE") && + (FIFO_SYNC_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-119] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-119] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-122] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-123] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_REG != "ASYNC") && + (UPDATE_MODE_REG != "MANUAL") && + (UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-127] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_EXT_REG != "ASYNC") && + (UPDATE_MODE_EXT_REG != "MANUAL") && + (UPDATE_MODE_EXT_REG != "SYNC"))) begin + $display("Error: [Unisim %s-128] UPDATE_MODE_EXT attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_EXT_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign IFD_CE_in = 1'b0; // tie off + assign OFD_CE_in = 1'b0; // tie off + assign RX_DATAIN1_in = 1'b0; // tie off + assign TX_D_in = 8'b00000000; // tie off + assign TX_RST_in = 1'b0; // tie off + assign T_in = 1'b1; // tie off + +generate +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_RX_BITSLICE_D1 SIP_RX_BITSLICE_INST ( + .CASCADE (CASCADE_REG), + .DATA_TYPE (DATA_TYPE_REG), + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DC_ADJ_EN_EXT (DC_ADJ_EN_EXT_REG), + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .DELAY_VALUE_EXT (DELAY_VALUE_EXT_REG), + .FDLY (FDLY_REG), + .FDLY_EXT (FDLY_EXT_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .TBYTE_CTL (TBYTE_CTL_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .UPDATE_MODE (UPDATE_MODE_REG), + .UPDATE_MODE_EXT (UPDATE_MODE_EXT_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .CNTVALUEOUT (CNTVALUEOUT_out), + .CNTVALUEOUT_EXT (CNTVALUEOUT_EXT_out), + .FIFO_EMPTY (FIFO_EMPTY_out), + .FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out), + .Q (Q_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .CE (CE_in), + .CE_EXT (CE_EXT_in), + .CLK (CLK_in), + .CLK_EXT (CLK_EXT_in), + .CNTVALUEIN (CNTVALUEIN_in), + .CNTVALUEIN_EXT (CNTVALUEIN_EXT_in), + .DATAIN (DATAIN_in), + .EN_VTC (EN_VTC_in), + .EN_VTC_EXT (EN_VTC_EXT_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .INC (INC_in), + .INC_EXT (INC_EXT_in), + .LOAD (LOAD_in), + .LOAD_EXT (LOAD_EXT_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .RST_DLY_EXT (RST_DLY_EXT_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .T (T_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .TX_D (TX_D_in), + .TX_RST (TX_RST_in), + .SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out), + .SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out), + .SPARE(SPARE_REG), + .FIFO_ENABLE(FIFO_ENABLE_REG), + .GSR (glblGSR) + ); +end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + SIP_RX_BITSLICE_K2 SIP_RX_BITSLICE_INST ( + .CASCADE (CASCADE_REG), + .DATA_TYPE (DATA_TYPE_REG), + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DC_ADJ_EN_EXT (DC_ADJ_EN_EXT_REG), + .DDR_DIS_DQS (DDR_DIS_DQS_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .DELAY_VALUE_EXT (DELAY_VALUE_EXT_REG), + .FDLY (FDLY_REG), + .FDLY_EXT (FDLY_EXT_REG), + .FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .TBYTE_CTL (TBYTE_CTL_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .UPDATE_MODE (UPDATE_MODE_REG), + .UPDATE_MODE_EXT (UPDATE_MODE_EXT_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .CNTVALUEOUT (CNTVALUEOUT_out), + .CNTVALUEOUT_EXT (CNTVALUEOUT_EXT_out), + .FIFO_EMPTY (FIFO_EMPTY_out), + .FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out), + .Q (Q_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .CE (CE_in), + .CE_EXT (CE_EXT_in), + .CLK (CLK_in), + .CLK_EXT (CLK_EXT_in), + .CNTVALUEIN (CNTVALUEIN_in), + .CNTVALUEIN_EXT (CNTVALUEIN_EXT_in), + .DATAIN (DATAIN_in), + .EN_VTC (EN_VTC_in), + .EN_VTC_EXT (EN_VTC_EXT_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .INC (INC_in), + .INC_EXT (INC_EXT_in), + .LOAD (LOAD_in), + .LOAD_EXT (LOAD_EXT_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .RST_DLY_EXT (RST_DLY_EXT_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .T (T_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .TX_D (TX_D_in), + .TX_RST (TX_RST_in), + .SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out), + .SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out), + .GSR (glblGSR) + ); +end +endgenerate + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + wire clk_ext_en_n; + wire clk_ext_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; + assign clk_ext_en_n = IS_CLK_EXT_INVERTED_BIN; + assign clk_ext_en_p = ~IS_CLK_EXT_INVERTED_BIN; +`endif + + specify + (CLK *> CNTVALUEOUT) = (100:100:100, 100:100:100); + (CLK_EXT *> CNTVALUEOUT_EXT) = (100:100:100, 100:100:100); + (DATAIN *> Q) = (0:0:0, 0:0:0); + (DATAIN *> RX_BIT_CTRL_OUT) = (0:0:0, 0:0:0); + (FIFO_RD_CLK *> Q) = (100:100:100, 100:100:100); + (FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100); + (RX_BIT_CTRL_IN *> FIFO_WRCLK_OUT) = (0:0:0, 0:0:0); + // (FIFO_WRCLK_OUT => FIFO_EMPTY) = (0:0:0, 0:0:0); // error prop output to output +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (negedge CLK_EXT, 0:0:0, notifier); + $period (negedge FIFO_RD_CLK, 0:0:0, notifier); + $period (negedge RX_BIT_CTRL_IN[20], 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge CLK_EXT, 0:0:0, notifier); + $period (posedge FIFO_RD_CLK, 0:0:0, notifier); + $period (posedge RX_BIT_CTRL_IN[20], 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay); + $setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CE_EXT_delay); + $setuphold (negedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CNTVALUEIN_EXT_delay); + $setuphold (negedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, INC_EXT_delay); + $setuphold (negedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, LOAD_EXT_delay); + $setuphold (negedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CE_EXT_delay); + $setuphold (negedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, CNTVALUEIN_EXT_delay); + $setuphold (negedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, INC_EXT_delay); + $setuphold (negedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_n, clk_ext_en_n, CLK_EXT_delay, LOAD_EXT_delay); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay); + $setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CE_EXT_delay); + $setuphold (posedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CNTVALUEIN_EXT_delay); + $setuphold (posedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, INC_EXT_delay); + $setuphold (posedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, LOAD_EXT_delay); + $setuphold (posedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CE_EXT_delay); + $setuphold (posedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, CNTVALUEIN_EXT_delay); + $setuphold (posedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, INC_EXT_delay); + $setuphold (posedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier, clk_ext_en_p, clk_ext_en_p, CLK_EXT_delay, LOAD_EXT_delay); + $setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge CLK_EXT, 0:0:0, 0, notifier); + $width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (negedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK_EXT, 0:0:0, 0, notifier); + $width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier); + $width (posedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SIM_CONFIGE2.v b/verilog/src/unisims/SIM_CONFIGE2.v new file mode 100644 index 0000000..e588666 --- /dev/null +++ b/verilog/src/unisims/SIM_CONFIGE2.v @@ -0,0 +1,2493 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIGE2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 12/04/10 - Initial version +// 03/14/11 - Make crc_ck 1 cycle long (CR599232) +// 03/17/11 - Handle CSB toggle (CR601925) +// 03/24/11 - Add cbi_b_ins to sync to negedge clock(CR603092) +// 05/03/11 - delay outbus 1 cycle (CR605404) +// 05/20/11 - initial done_cycle_reg (CR611383) +// 07/01/11 - Generate startup_set_pulse when rw_en=1 (595934) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 02/21/13 - Updated output latency to 3 clock cycles (CR 701426). +// 09/09/13 - Fixed output IDCODE (CR 727695). +// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079). +// 02/14/14 - Fixed Non-Continous data loading problem (CR 690809). +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module SIM_CONFIGE2 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DEVICE_ID = 32'h0, + parameter ICAP_SUPPORT = "FALSE", + parameter ICAP_WIDTH = "X8" +) ( + output CSOB, + inout DONE, + input CCLK, + input CSB, + inout [31:0] D, + inout INITB, + input [2:0] M, + input PROGB, + input RDWRB +); + + localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt"; + localparam cfg_Tprog = 250000; // min PROG must be low + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + +// tri0 GSR, GTS, GWE; + + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + wire rdwr_b_in; + reg rdwr_b_in1; + reg checka_en; + reg init_b_out; + reg [3:0] done_o; + integer frame_data_fd; + integer farn; + integer ib; + integer ib_skp, ci, bi; + reg frame_data_wen; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire [31:0] d_in; + wire [31:0] d_out; + wire busy_out; + wire cso_b_out; + wire csi_b_in; + reg csi_b_ins; + wire d_out_en; + wire pll_locked; + reg pll_lockwt; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire [3:0] desync_flag; + wire [3:0] crc_rst; + reg [3:0] crc_bypass; + reg icap_on; + reg icap_clr; + reg icap_sync; + reg icap_desynch; + reg rd_desynch; + reg rd_desynch_tmp; + reg icap_init_done; + reg icap_init_done_dly; + wire [3:0] desynch_set1; + reg [1:0] icap_bw; + +// assign DONE = p_up; +// assign INITB = p_up; + assign (strong1, weak0) glbl.GSR = GSR; + assign (strong1, weak0) glbl.GTS = GTS; + assign glbl.PROGB_GLBL = PROGB; + assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1; + + buf buf_cso (CSOB, cso_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_cs (csi_b_in, CSB); + + buf buf_din[31:0] (d_in, D); + bufif1 buf_dout[31:0] (D, d_out, d_out_en); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge; + time prog_pulse_low; + reg mode_sample_flag; + reg [3:0] buswid_flag_init; + reg [3:0] buswid_flag; + reg [1:0] buswidth[3:0]; + wire [1:0] buswidth_ibtmp; + reg [1:0] buswidth_tmp[3:0]; + reg [31:0] pack_in_reg[3:0]; + reg [31:0] pack_in_reg_tmp0; + reg [31:0] pack_in_reg_tmps0; + reg [31:0] pack_in_reg_tmp; + reg [4:0] reg_addr[3:0]; + reg [4:0] reg_addr_tmp; + reg [3:0] new_data_in_flag; + reg [3:0] wr_flag; + reg [3:0] rd_flag; + reg [3:0] cmd_wr_flag; + reg [3:0] cmd_reg_new_flag; + reg [3:0] cmd_rd_flag; + reg [3:0] bus_sync_flag; + reg [3:0] conti_data_flag; + integer wr_cnt[3:0]; + integer conti_data_cnt[3:0]; + integer rd_data_cnt[3:0]; + integer abort_cnt; + reg [2:0] st_state0; + reg [2:0] st_state1; + reg [2:0] st_state2; + reg [2:0] st_state3; + reg [2:0] st_state0i; + reg [2:0] st_state1i; + reg [2:0] st_state2i; + reg [2:0] st_state3i; + reg startup_begin_flag0; + reg startup_end_flag0; + reg startup_begin_flag1; + reg startup_end_flag1; + reg startup_begin_flag2; + reg startup_end_flag2; + reg startup_begin_flag3; + reg startup_end_flag3; + reg [3:0] crc_ck; + reg [3:0] crc_ck_en; + reg [3:0] crc_err_flag; + wire [3:0] crc_err_flag_tot; + reg [3:0] crc_err_flag_reg; + wire [3:0] crc_en; + reg [31:0] crc_curr[3:0]; + reg [31:0] crc_curr_tmp; + wire [31:0] crc_curr_cktmp; + reg [31:0] crc_new; + reg [36:0] crc_input; + reg [31:0] rbcrc_curr[3:0]; + reg [31:0] rbcrc_new; + reg [36:0] rbcrc_input; + reg [3:0] gwe_out; + reg [3:0] gts_out; + reg [31:0] d_o; + reg [31:0] outbus; + reg [31:0] outbus_dly; + reg [31:0] outbus_dly1; + reg busy_o; + reg [31:0] tmp_val1; + reg [31:0] tmp_val2; + reg [31:0] crc_reg[3:0]; + reg [31:0] crc_reg_tmp; + wire [31:0] crc_reg_cktmp; + reg [31:0] far_reg[3:0]; + reg [31:0] far_addr; + reg [31:0] fdri_reg[3:0]; + reg [31:0] fdro_reg[3:0]; + reg [4:0] cmd_reg[3:0]; + reg [31:0] ctl0_reg[3:0]; + reg [31:0] mask_reg[3:0]; + wire [31:0] stat_reg[3:0]; + wire [31:0] stat_reg_tmp0; + wire [31:0] stat_reg_tmp1; + wire [31:0] stat_reg_tmp2; + wire [31:0] stat_reg_tmp3; + reg [31:0] lout_reg[3:0]; + reg [31:0] cor0_reg[3:0]; + reg [31:0] cor0_reg_tmp0; + reg [31:0] cor0_reg_tmp1; + reg [31:0] cor0_reg_tmp2; + reg [31:0] cor0_reg_tmp3; + reg [31:0] mfwr_reg[3:0]; + reg [31:0] cbc_reg[3:0]; + reg [31:0] idcode_reg[3:0]; + reg [31:0] axss_reg[3:0]; + reg [31:0] cor1_reg[3:0]; + reg [31:0] cor1_reg_tmp0; + reg [31:0] cor1_reg_tmp1; + reg [31:0] cor1_reg_tmp2; + reg [31:0] cor1_reg_tmp3; + reg [31:0] csob_reg[3:0]; + reg [31:0] wbstar_reg[3:0]; + reg [31:0] timer_reg[3:0]; + reg [31:0] rbcrc_hw_reg[3:0]; + reg [31:0] rbcrc_sw_reg[3:0]; + reg [31:0] rbcrc_live_reg[3:0]; + reg [31:0] efar_reg[3:0]; + reg [31:0] bootsts_reg[3:0]; + reg [31:0] ctl1_reg[3:0]; + reg [31:0] testmode_reg[3:0]; + reg [31:0] memrd_param_reg[3:0]; + reg [31:0] dwc_reg[3:0]; + reg [31:0] trim_reg[3:0]; + reg [31:0] bout_reg[3:0]; + reg [31:0] bspi_reg[3:0]; + reg [2:0] mode_pin_in; + reg [2:0] mode_reg; + reg [3:0] crc_reset; + reg [3:0] gsr_set; + reg [3:0] gts_usr_b; + reg [3:0] done_pin_drv; + + reg [3:0] shutdown_set; + reg [3:0] desynch_set; + reg [2:0] done_cycle_reg0; + reg [2:0] done_cycle_reg1; + reg [2:0] done_cycle_reg2; + reg [2:0] done_cycle_reg3; + reg [2:0] gts_cycle_reg0; + reg [2:0] gts_cycle_reg1; + reg [2:0] gts_cycle_reg2; + reg [2:0] gts_cycle_reg3; + reg [2:0] gwe_cycle_reg0; + reg [2:0] gwe_cycle_reg1; + reg [2:0] gwe_cycle_reg2; + reg [2:0] gwe_cycle_reg3; + reg init_pin; + reg init_rst; + reg [2:0] nx_st_state0; + reg [2:0] nx_st_state1; + reg [2:0] nx_st_state2; + reg [2:0] nx_st_state3; + reg [3:0] ghigh_b; + reg [3:0] gts_cfg_b; + reg [3:0] eos_startup; + reg [3:0] startup_set; + reg [1:0] startup_set_pulse0; + reg [1:0] startup_set_pulse1; + reg [1:0] startup_set_pulse2; + reg [1:0] startup_set_pulse3; + reg abort_out_en; + reg [31:0] tmp_dword; + reg [15:0] tmp_word; + reg [7:0] tmp_byte; + reg [3:0] id_error_flag; + wire id_error_flag_t; + reg [3:0] iprog_b; + wire iprog_b_t; + reg [3:0] i_init_b_cmd; + wire i_init_b_cmd_t; + reg i_init_b; + reg [7:0] abort_status; + reg [3:0] persist_en; + reg [3:0] rst_sync; + reg [3:0] abort_dis; + reg [2:0] lock_cycle_reg0; + reg [2:0] lock_cycle_reg1; + reg [2:0] lock_cycle_reg2; + reg [2:0] lock_cycle_reg3; + reg [3:0] rbcrc_no_pin; + reg abort_flag_rst; + reg [3:0] gsr_st_out; + reg [3:0] gsr_cmd_out; + reg [3:0] gsr_cmd_out_pulse; + reg d_o_en; + wire rst_intl; + wire rw_en_tmp1; + wire [3:0] rw_en; + wire [3:0] gsr_out; + wire [3:0] cfgerr_b_flag; + reg [3:0] abort_flag; + integer downcont_cnt; + reg rst_en; + reg prog_b_a; + reg [3:0] csbo_flag; + reg [3:0] bout_flag; + reg [3:0] bout_flags; + reg [3:0] bout_bf; + reg [3:0] bout_en; + reg rd_sw_en; + integer csbo_cnt[3:0]; + integer bout_cnt[3:0]; + integer bout_cnt_tmp; + reg [4:0] rd_reg_addr[3:0]; + reg done_release; + + wire iprog_b_0; + wire iprog_b_1; + wire iprog_b_2; + wire iprog_b_3; + wire i_init_b_cmd_0; + wire i_init_b_cmd_1; + wire i_init_b_cmd_2; + wire i_init_b_cmd_3; + wire rw_en_tmp; + wire desync_flag_t; + wire abort_dis_bi; + + assign (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out; + + assign (weak1, strong0) DONE = (done_o[0] !== 1'b0) && + ((bout_en[1] == 0) || (done_o[1] !== 1'b0)) && + ((bout_en[2] == 0) || (done_o[2] !== 1'b0)) && + ((bout_en[3] == 0) || (done_o[3] !== 1'b0)); +// +// assign (weak1, strong0) DONE= (bout_en[1] == 0) || done_o[1]; +// assign (weak1, strong0) DONE= (bout_en[2] == 0) || done_o[2]; +// assign (weak1, strong0) DONE= (bout_en[3] == 0) || done_o[3]; + + + localparam MODULE_NAME = "SIM_CONFIGE2"; + + initial begin + if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093") + bout_en = 4'b0011; + else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093") + bout_en = 4'b0111; + else if (DEVICE_ID == "036A6093") + bout_en = 4'b1111; + else + bout_en = 4'b0001; + end + + + + initial begin + buswidth_tmp[0] = 2'b00; + buswidth_tmp[1] = 2'b00; + buswidth_tmp[2] = 2'b00; + buswidth_tmp[3] = 2'b00; + pack_in_reg[0] = 32'b0; + pack_in_reg[1] = 32'b0; + pack_in_reg[2] = 32'b0; + pack_in_reg[3] = 32'b0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + pack_in_reg_tmp = 32'b0; + crc_curr[0] = 32'b0; + crc_curr[1] = 32'b0; + crc_curr[2] = 32'b0; + crc_curr[3] = 32'b0; + rbcrc_curr[0] = 32'b0; + rbcrc_curr[1] = 32'b0; + rbcrc_curr[2] = 32'b0; + rbcrc_curr[3] = 32'b0; + ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + cor0_reg[0] = 32'b00000000000000000011111111101100; + cor0_reg[1] = 32'b00000000000000000011111111101100; + cor0_reg[2] = 32'b00000000000000000011111111101100; + cor0_reg[3] = 32'b00000000000000000011111111101100; + cor0_reg_tmp0 = cor0_reg[0]; + cor0_reg_tmp1 = cor0_reg[1]; + cor0_reg_tmp2 = cor0_reg[2]; + cor0_reg_tmp3 = cor0_reg[3]; + done_cycle_reg0 = cor0_reg_tmp0[14:12]; + lock_cycle_reg0 = cor0_reg_tmp0[8:6]; + done_cycle_reg1 = cor0_reg_tmp0[14:12]; + lock_cycle_reg1 = cor0_reg_tmp0[8:6]; + done_cycle_reg2 = cor0_reg_tmp0[14:12]; + lock_cycle_reg2 = cor0_reg_tmp0[8:6]; + done_cycle_reg3 = cor0_reg_tmp0[14:12]; + lock_cycle_reg3 = cor0_reg_tmp0[8:6]; + cor1_reg[0] = 32'b0; + cor1_reg[1] = 32'b0; + cor1_reg[2] = 32'b0; + cor1_reg[3] = 32'b0; + cor1_reg_tmp0 = 32'b0; + cor1_reg_tmp1 = 32'b0; + cor1_reg_tmp2 = 32'b0; + cor1_reg_tmp3 = 32'b0; + wbstar_reg[0] = 32'b0; + wbstar_reg[1] = 32'b0; + wbstar_reg[2] = 32'b0; + wbstar_reg[3] = 32'b0; + timer_reg[0] = 32'b0; + timer_reg[1] = 32'b0; + timer_reg[2] = 32'b0; + timer_reg[3] = 32'b0; + bootsts_reg[0] = 32'b0; + bootsts_reg[1] = 32'b0; + bootsts_reg[2] = 32'b0; + bootsts_reg[3] = 32'b0; + ctl1_reg[0] = 32'b0; + ctl1_reg[1] = 32'b0; + ctl1_reg[2] = 32'b0; + ctl1_reg[3] = 32'b0; + testmode_reg[0] = 32'b0; + testmode_reg[1] = 32'b0; + testmode_reg[2] = 32'b0; + testmode_reg[3] = 32'b0; + memrd_param_reg[0] = 32'b0; + memrd_param_reg[1] = 32'b0; + memrd_param_reg[2] = 32'b0; + memrd_param_reg[3] = 32'b0; + dwc_reg[0] = 32'b0; + dwc_reg[1] = 32'b0; + dwc_reg[2] = 32'b0; + dwc_reg[3] = 32'b0; + trim_reg[0] = 32'b0; + trim_reg[1] = 32'b0; + trim_reg[2] = 32'b0; + trim_reg[3] = 32'b0; + bout_reg[0] = 32'b0; + bout_reg[1] = 32'b0; + bout_reg[2] = 32'b0; + bout_reg[3] = 32'b0; + bspi_reg[0] = 32'h000B; + bspi_reg[1] = 32'h000B; + bspi_reg[2] = 32'h000B; + bspi_reg[3] = 32'h000B; + rd_reg_addr[0] = 5'b0; + rd_reg_addr[1] = 5'b0; + rd_reg_addr[2] = 5'b0; + rd_reg_addr[3] = 5'b0; + wr_cnt[0] = 0; + wr_cnt[1] = 0; + wr_cnt[2] = 0; + wr_cnt[3] = 0; + bout_cnt[0] = 0; + bout_cnt[1] = 0; + bout_cnt[2] = 0; + bout_cnt[3] = 0; + done_o = 4'b0; + checka_en = 1'b0; + init_b_out = 1'b1; + farn = 0; + ib = 0; + csi_b_ins = 1'b1; + crc_bypass = 4'b0000; + icap_clr = 1'b0; + icap_desynch = 1'b0; + rd_desynch = 1'b0; + rd_desynch_tmp = 1'b0; + icap_init_done = 1'b0; + icap_init_done_dly = 1'b0; + prog_pulse_low_edge = 0; + prog_pulse_low = 0; + mode_sample_flag = 1'b0; + buswid_flag_init = 4'b0000; + buswid_flag = 4'b0000; + new_data_in_flag = 4'b0000; + wr_flag = 4'b0000; + rd_flag = 4'b0000; + cmd_wr_flag = 4'b0000; + cmd_reg_new_flag = 4'b0000; + cmd_rd_flag = 4'b0000; + bus_sync_flag = 4'b0000; + conti_data_flag = 4'b0000; + st_state0 = STARTUP_PH0; + st_state1 = STARTUP_PH0; + st_state2 = STARTUP_PH0; + st_state3 = STARTUP_PH0; + st_state0i = STARTUP_PH0; + st_state1i = STARTUP_PH0; + st_state2i = STARTUP_PH0; + st_state3i = STARTUP_PH0; + startup_begin_flag0 = 1'b0; + startup_end_flag0 = 1'b0; + startup_begin_flag1 = 1'b0; + startup_end_flag1 = 1'b0; + startup_begin_flag2 = 1'b0; + startup_end_flag2 = 1'b0; + startup_begin_flag3 = 1'b0; + startup_end_flag3 = 1'b0; + crc_ck = 4'b0000; + crc_ck_en = 4'b1111; + crc_err_flag = 4'b0000; + crc_err_flag_reg = 4'b0000; + gwe_out = 4'b0000; + gts_out = 4'b1111; + d_o = 32'h0; + outbus = 32'h0; + outbus_dly = 32'h0; + outbus_dly1 = 32'h0; + busy_o = 1'b0; + mode_pin_in = 3'b000; + crc_reset = 4'b0000; + gsr_set = 4'b0000; + gts_usr_b = 4'b1111; // was 4'b111 + done_pin_drv = 4'b0000; + shutdown_set = 4'b0000; + desynch_set = 4'b0000; + done_cycle_reg0 = 3'b011; + done_cycle_reg1 = 3'b011; + done_cycle_reg2 = 3'b011; + done_cycle_reg3 = 3'b011; + gts_cycle_reg0 = 3'b101; + gts_cycle_reg1 = 3'b101; + gts_cycle_reg2 = 3'b101; + gts_cycle_reg3 = 3'b101; + gwe_cycle_reg0 = 3'b100; + gwe_cycle_reg1 = 3'b100; + gwe_cycle_reg2 = 3'b100; + gwe_cycle_reg3 = 3'b100; + init_rst = 1'b0; + nx_st_state0 = 3'b000; + nx_st_state1 = 3'b000; + nx_st_state2 = 3'b000; + nx_st_state3 = 3'b000; + ghigh_b = 4'b0000; + gts_cfg_b = 4'b0000; + eos_startup = 4'b0000; + startup_set = 4'b0000; + startup_set_pulse0 = 2'b00; + startup_set_pulse1 = 2'b00; + startup_set_pulse2 = 2'b00; + startup_set_pulse3 = 2'b00; + abort_out_en = 1'b0; + id_error_flag = 4'b0000; + iprog_b = 4'b1111; + i_init_b_cmd = 4'b1111; + i_init_b = 1'b0; + abort_status = 8'b00000000; + persist_en = 1'b0; + rst_sync = 1'b0; + abort_dis = 1'b0; + lock_cycle_reg0 = 3'b000; + lock_cycle_reg1 = 3'b000; + lock_cycle_reg2 = 3'b000; + lock_cycle_reg3 = 3'b000; + rbcrc_no_pin = 4'b0000; + abort_flag_rst = 1'b0; + gsr_st_out = 4'b1111; + gsr_cmd_out = 4'b0000; + gsr_cmd_out_pulse = 4'b0000; + d_o_en = 1'b0; + abort_flag = 4'b0000; + downcont_cnt = 0; + rst_en = 1'b0; + prog_b_a = 1'b1; + csbo_flag = 4'b0000; + bout_flag = 4'b0000; + bout_flags = 4'b0000; + bout_bf = 4'b0000; + rd_sw_en = 1'b0; + done_release = 1'b0; + end + + + initial begin + + case (ICAP_SUPPORT) + "FALSE" : icap_on = 0; + "TRUE" : icap_on = 1; + default : icap_on = 0; + endcase + + if (DEVICE_ID == 32'h0 && icap_on == 0) begin + $display("Error: [Unisim %s-1] DEVICE_ID attribute is not set. Instance: %m", MODULE_NAME); + end + + if (ICAP_SUPPORT == "TRUE") begin + case (ICAP_WIDTH) + "X8" : icap_bw = 2'b01; + "X16" : icap_bw = 2'b10; + "X32" : icap_bw = 2'b11; + default : icap_bw = 2'b01; + endcase + + frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w"); + if (frame_data_fd != 0) begin + frame_data_wen = 1; + $fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n"); + end + end + else begin + icap_bw = 2'b00; + frame_data_wen = 0; + end + + icap_sync = 0; + + end + + + assign GSR = gsr_out[0]; + assign GTS = gts_out[0]; + assign GWE = gwe_out[0]; + assign busy_out = busy_o; + assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0]; + assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1]; + assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2]; + assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3]; + assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0]; + assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1]; + assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2]; + assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3]; + assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0]; + assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8]; + assign d_out_en = d_o_en; + assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1; + assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111; + + + always @(posedge cclk_in) begin + outbus_dly <= outbus_dly1; + outbus_dly1 <= outbus; + end + + always @(posedge cclk_in or csi_b_in) + if (csi_b_in == 1) + csi_b_ins <= csi_b_in; + else begin + if (cclk_in != 1) + csi_b_ins <= csi_b_in; + else + @(negedge cclk_in) + csi_b_ins <= csi_b_in; + end + + always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] ) + if (abort_out_en == 1) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib]; + + + assign init_b_t = init_b_in & i_init_b_cmd_t; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + assign iprog_b_0 = iprog_b[0]; + assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1; + assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1; + assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1; + + assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0; + + assign i_init_b_cmd_0 = i_init_b_cmd[0]; + assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1; + assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1; + assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1; + + assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2 + & i_init_b_cmd_3; + + always @( rst_en or init_rst or prog_b_in or iprog_b_t ) + if (icap_on == 0) begin + if (init_rst == 1) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + end + + assign id_error_flag_t = &id_error_flag; + + always @(posedge id_error_flag_t) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en == 1) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b_t & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in !== 3'b110) begin + mode_sample_flag <= 0; + if ( icap_on == 0) + $display("Error: [Unisim %s-2] Input M is %h. Only Slave SelectMAP mode M=110 is supported. Instance %m.", MODULE_NAME, m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 && icap_on == 0) + $display("Error: [Unisim %s-3] PROGB is not high when INITB goes high at time %t. Instance %m.", MODULE_NAME, $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0) + $display("Error: [Unisim %s-4] Mode pine M[2:0] changed after rising edge of INITB at time %t. Instance %m.", MODULE_NAME, $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in == 0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog && icap_on == 0) + $display("Error: [Unisim %s-5] Low time of PROGB is less than required minimum Tprogram time %d at time %t. Instance %m.", MODULE_NAME, cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0 ) begin + buswid_flag_init <= 4'b0; + buswid_flag <= 4'b0; + buswidth_tmp[0] <= 2'b00; + buswidth_tmp[1] <= 2'b00; + buswidth_tmp[2] <= 2'b00; + buswidth_tmp[3] <= 2'b00; + end + else + if (buswid_flag[ib] == 0) begin + if (bus_en == 1 && rdwr_b_in == 0) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (buswid_flag_init[ib] == 0) begin + if (tmp_byte == 8'hBB) + buswid_flag_init[ib] <= 1; + end + else begin + if (tmp_byte == 8'h11) begin // x8 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b01; + end + else if (tmp_byte == 8'h22) begin // x16 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b10; + end + else if (tmp_byte == 8'h44) begin // x32 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b11; + end + else begin + buswid_flag[ib] <= 0; + buswidth_tmp[ib] <= 2'b00; + buswid_flag_init[ib] <= 0; + if (icap_on == 0) + $display("Error: [Unisim %s-6] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB at time %t. Instance %m.", MODULE_NAME, $time); + else + $display("Error: [Unisim %s-7] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE3 instance at time %t. Instance %m.", MODULE_NAME, $time); + + end + end + end + end + + assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib]; + + always @(buswidth_ibtmp) + buswidth[ib] = buswidth_ibtmp; + + assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0; + + assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0; + assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0; + assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0; + assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0; + + + assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch; + assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch; + assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch; + assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch; + assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0]; + assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1]; + assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2]; + assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3]; + + always @(posedge eos_startup[0]) + if (icap_on == 1) begin + $fclose(frame_data_fd); + icap_init_done <= 1; + @(posedge cclk_in); + @(posedge cclk_in) + if (icap_init_done_dly == 0) + icap_desynch <= 1; + @(posedge cclk_in); + @(posedge cclk_in) begin + icap_desynch <= 0; + icap_init_done_dly <= 1; + end + @(posedge cclk_in); + @(posedge cclk_in); + @(posedge cclk_in); + end + else begin + icap_clr <= 0; + icap_desynch <= 0; + end + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in == 0) + rd_sw_en <= 0; + else begin + if (csi_b_in == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + assign desync_flag_t = |desync_flag; + + always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin + if (desync_flag[ib] == 1) begin + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + if (desync_flag[0] == 1 ) begin + new_data_in_flag[0] = 0; + bus_sync_flag[0] = 0; + wr_cnt[0] = 0; + wr_flag[0] = 0; + rd_flag[0] = 0; + end + if (desync_flag[1] == 1 ) begin + new_data_in_flag[1] = 0; + bus_sync_flag[1] = 0; + wr_cnt[1] = 0; + wr_flag[1] = 0; + rd_flag[1] = 0; + end + if (desync_flag[2] == 1 ) begin + new_data_in_flag[2] = 0; + bus_sync_flag[2] = 0; + wr_cnt[2] = 0; + wr_flag[2] = 0; + rd_flag[2] = 0; + end + if (desync_flag[3] == 1 ) begin + new_data_in_flag[3] = 0; + bus_sync_flag[3] = 0; + wr_cnt[3] = 0; + wr_flag[3] = 0; + rd_flag[3] = 0; + end + if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin + new_data_in_flag = 4'b0; + wr_cnt[0] = 0; + wr_cnt[1] = 0; + wr_cnt[2] = 0; + wr_cnt[3] = 0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + else begin + if (icap_clr == 1) begin + new_data_in_flag <= 4'b0; + wr_cnt[0] <= 0; + wr_cnt[1] <= 0; + wr_cnt[2] <= 0; + wr_cnt[3] <= 0; + wr_flag <= 4'b0; + rd_flag <= 4'b0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin + if (rdwr_b_in == 0) begin + wr_flag[ib] <= 1; + rd_flag[ib] <= 0; + if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (bus_sync_flag[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99 + && pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 0; + end + else begin + pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16]; + pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8]; + pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0]; + pack_in_reg_tmp0[7:0] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + end + end + else begin + if (wr_cnt[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[31:24] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 1; + end + else if (wr_cnt[ib] == 1) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[23:16] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 2; + end + else if (wr_cnt[ib] == 2) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[15:8] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 3; + end + else if (wr_cnt[ib] == 3) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[7:0] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 1; + wr_cnt[ib] <= 0; + end + end + end + else if (buswidth[ib] == 2'b10) begin + tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])}; + if (bus_sync_flag[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin + wr_cnt[ib] <= 0; + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + end + else begin + pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0]; + pack_in_reg_tmp0[15:0] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 0; + end + end + else begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (wr_cnt[ib] == 0) begin + pack_in_reg_tmp0[31:16] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 1; + end + else if (wr_cnt[ib] == 1) begin + pack_in_reg_tmp0[15:0] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 1; + wr_cnt[ib] <= 0; + end + end + end + else if (buswidth[ib] == 2'b11 ) begin + tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]), + bit_revers8(d_in[7:0])}; + pack_in_reg_tmp0 <= tmp_dword; + pack_in_reg_tmps0 <= tmp_dword; + if (bus_sync_flag[ib] == 0) begin + if (tmp_dword == 32'hAA995566) begin + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + end + end + else begin + pack_in_reg_tmp0 <= tmp_dword; + pack_in_reg_tmps0 <= tmp_dword; + new_data_in_flag[ib] <= 1; + end + end + end + else begin + wr_flag[ib] <= 0; + new_data_in_flag[ib] <= 0; + if (rd_sw_en ==1) + rd_flag[ib] <= 1; + end + end + else begin + wr_flag[ib] <= 0; + rd_flag[ib] <= 0; + new_data_in_flag[ib] <= 0; + end + end + end + + + always @(pack_in_reg_tmps0 or desync_flag or icap_clr) + begin + if (desync_flag[0] == 1 || icap_clr == 1) + pack_in_reg[0] = 32'b0; + if (desync_flag[1] == 1 || icap_clr == 1) + pack_in_reg[1] = 32'b0; + if (desync_flag[2] == 1 || icap_clr == 1) + pack_in_reg[2] = 32'b0; + if (desync_flag[3] == 1 || icap_clr == 1) + pack_in_reg[3] = 32'b0; + + if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin + pack_in_reg[0] = pack_in_reg_tmps0; + end + else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0) + pack_in_reg[1] = pack_in_reg_tmps0; + else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0) + pack_in_reg[2] = pack_in_reg_tmps0; + else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0) + pack_in_reg[3] = pack_in_reg_tmps0; + end + + + task rst_pack_dec; + input ib_d; + begin + conti_data_flag[ib_d] <= 0; + conti_data_cnt[ib_d] <= 0; + cmd_wr_flag[ib_d] <= 0; + cmd_rd_flag[ib_d] <= 0; + id_error_flag[ib_d] <= 0; + crc_curr[ib_d] <= 32'b0; + crc_ck[ib_d] <= 0; + csbo_cnt[ib_d] <= 0; + csbo_flag[ib_d] <= 0; + downcont_cnt <= 0; + rd_data_cnt[ib_d] <= 0; + end + endtask + + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + rst_pack_dec(0); + rst_pack_dec(1); + rst_pack_dec(2); + rst_pack_dec(3); + bout_flag <= 4'b0; + bout_cnt[0] <= 0; + bout_cnt[1] <= 0; + bout_cnt[2] <= 0; + bout_cnt[3] <= 0; + end + else begin + if (icap_clr == 1) begin + rst_pack_dec(0); + rst_pack_dec(1); + rst_pack_dec(2); + rst_pack_dec(3); + bout_flag <= 4'b0; + bout_cnt[0] <= 0; + bout_cnt[1] <= 0; + bout_cnt[2] <= 0; + bout_cnt[3] <= 0; + end + if (crc_reset[ib] == 1 ) begin + crc_reg[ib] <= 32'b0; + crc_ck[ib] <= 0; + crc_curr[ib] <= 32'b0; + end + if (crc_ck[ib] == 1) begin + crc_curr[ib] <= 32'b0; + crc_ck[ib] <= 0; + end + + if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin + bout_flag[0] <= 0; + bout_cnt[0] <= 0; + rst_pack_dec(0); + end + if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin + bout_flag[1] <= 0; + bout_cnt[1] <= 0; + rst_pack_dec(1); + end + if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin + bout_flag[2] <= 0; + bout_cnt[2] <= 0; + rst_pack_dec(2); + end + if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin + bout_flag[3] <= 0; + bout_cnt[3] <= 0; + rst_pack_dec(3); + end + if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0 + && desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin + pack_in_reg_tmp = pack_in_reg[ib]; + if (conti_data_flag[ib] == 1 ) begin + reg_addr_tmp = reg_addr[ib]; + case (reg_addr_tmp) + 5'b00000 : begin + crc_reg[ib] <= pack_in_reg[ib]; + crc_reg_tmp <= pack_in_reg[ib]; + crc_ck[ib] <= 1; + end + 5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]}; + + 5'b00010 : fdri_reg[ib] <= pack_in_reg[ib]; + 5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0]; + 5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]); + 5'b00110 : mask_reg[ib] <= pack_in_reg[ib]; + 5'b01000 : lout_reg[ib] <= pack_in_reg[ib]; + 5'b01001 : cor0_reg[ib] <= pack_in_reg[ib]; + 5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib]; + 5'b01011 : cbc_reg[ib] <= pack_in_reg[ib]; + 5'b01100 : begin + idcode_reg[ib] <= pack_in_reg[ib]; + if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag[ib] <= 1; + if (icap_on == 0) + $display("Error: [Unisim %s-8] Written value to IDCODE register is %h which does not match with DEVICE ID %h on %s at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, MODULE_NAME, $time); + else + $display("Error: [Unisim %s-9] Written value to IDCODE register is %h which does not match with DEVICE ID %h on ICAPE3 at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, $time); + end + else + id_error_flag[ib] <= 0; + end + 5'b01101 : axss_reg[ib] <= pack_in_reg[ib]; + 5'b01110 : cor1_reg[ib] <= pack_in_reg[ib]; + 5'b01111 : csob_reg[ib] <= pack_in_reg[ib]; + 5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib]; + 5'b10001 : timer_reg[ib] <= pack_in_reg[ib]; + 5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib]; + 5'b10111 : testmode_reg[ib] <= pack_in_reg[ib]; + 5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]); + 5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]}; + 5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]}; + 5'b11011 : trim_reg[ib] <= pack_in_reg[ib]; + 5'b11110 : bout_reg[ib] <= pack_in_reg[ib]; + 5'b11111 : bspi_reg[ib] <= pack_in_reg[ib]; + endcase + + if (reg_addr[ib] != 5'b00000) + crc_ck[ib] <= 0; + + if (reg_addr_tmp == 5'b00100) + cmd_reg_new_flag[ib] <= 1; + else + cmd_reg_new_flag[ib] <= 0; + + if (crc_en[ib] == 1) begin + if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111) + crc_curr[ib] = 32'b0; + else begin + if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14 + && reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin + crc_input = {reg_addr[ib], pack_in_reg_tmp}; + crc_curr_tmp = crc_curr[ib]; + crc_new = bcc_next(crc_curr_tmp, crc_input); + crc_curr[ib] <= crc_new; + end + end + end + + if (conti_data_cnt[ib] <= 1) begin + conti_data_cnt[ib] <= 0; + end + else + conti_data_cnt[ib] <= conti_data_cnt[ib] - 1; + end + else if (conti_data_flag[ib] == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en[ib] == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg[ib]}; + crc_new = bcc_next(crc_curr[ib], crc_input); + crc_curr[ib] <= crc_new; + end + if (ib == 0) begin + if (farn <= 80) + farn <= farn + 1; + else begin + far_addr <= far_addr + 1; + farn <= 0; + end + if (frame_data_wen == 1 && icap_init_done == 0) begin + rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]}; + rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input); + rbcrc_curr[ib] <= rbcrc_new; + $fwriteh(frame_data_fd, far_addr); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, pack_in_reg[ib]); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, rbcrc_new); + $fwriteh(frame_data_fd, "\n"); + end + end + end + + if (pack_in_reg_tmp[31:29] == 3'b010 ) begin + bout_cnt_tmp = bout_cnt[ib]; + if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + downcont_cnt <= pack_in_reg_tmp[26:0]; + far_addr <= far_reg[ib]; + end + else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + bout_flag[ib] <= 1; + bout_cnt[ib] <= pack_in_reg_tmp[26:0]; + end + else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + csbo_flag[ib] <= 1; + csbo_cnt[ib] <= pack_in_reg_tmp[26:0]; + end + end + else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg_tmp[10:0] != 11'b0) begin + cmd_rd_flag[ib] <= 1; + cmd_wr_flag[ib] <= 0; + rd_data_cnt[ib] <= 4; + conti_data_cnt[ib] <= 0; + conti_data_flag[ib] <= 0; + rd_reg_addr[ib] <= pack_in_reg_tmp[17:13]; + end + end + else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg + lout_reg[ib] <= pack_in_reg_tmp; + conti_data_flag[ib] = 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + cmd_wr_flag[ib] <= 1; + conti_data_cnt[ib] <= 5'b0; + end + else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg + bout_reg[ib] <= pack_in_reg_tmp; + bout_flags[ib] <= 1; + conti_data_flag[ib] = 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + cmd_wr_flag[ib] <= 1; + conti_data_cnt[ib]<= 5'b0; + end + else begin + if (pack_in_reg_tmp[10:0] != 10'b0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 1; + conti_data_flag[ib] <= 1; + conti_data_cnt[ib] <= pack_in_reg_tmp[10:0]; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + end + else begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 1; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + end + end + end + else begin + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + end + end + end // if (conti_data_flag == 0 ) + if (csbo_cnt[ib] != 0 ) begin + if (csbo_flag[ib] == 1) + csbo_cnt[ib] <= csbo_cnt[ib] - 1; + end + else + csbo_flag[ib] <= 0; + + if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin + if (bout_cnt[0] == 1) begin + bout_cnt[0] <= 0; + bout_flag[0] <= 0; + end + else + bout_cnt[0] <= bout_cnt[0] - 1; + end + + if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin + if (bout_cnt[1] == 1) begin + bout_cnt[1] <= 0; + bout_flag[1] <= 0; + end + else + bout_cnt[1] <= bout_cnt[1] - 1; + end + + if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin + bout_cnt[2] <= bout_cnt[2] - 1; + if (bout_cnt[2] == 1) begin + bout_cnt[2] <= 0; + bout_flag[2] <= 0; + end + else + bout_cnt[2] <= bout_cnt[2] - 1; + end + + if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin + if (bout_cnt[3] == 1) begin + bout_cnt[3] <= 0; + bout_flag[3] <= 0; + end + else + bout_cnt[3] <= bout_cnt[3] - 1; + end + + if (conti_data_cnt[ib] == 5'b00001 ) + conti_data_flag[ib] <= 0; + + if (crc_ck[ib] == 1 || icap_init_done == 1) + crc_ck[ib] <= 0; + end + + if (rw_en[ib] == 1 && csi_b_ins == 0) begin + if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1) + rd_data_cnt[ib] <= 0; + else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin + cmd_rd_flag[ib] <= 0; + end + else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1) + rd_data_cnt[ib] <= rd_data_cnt[ib] - 1; + + if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1) + downcont_cnt <= downcont_cnt - 1; + end + + + if (cmd_reg_new_flag[ib] == 1 ) + cmd_reg_new_flag[ib] <= 0; + + end + + + always @(bout_flag) + if (bout_flag[3] == 1) begin + ib = 3; + ib_skp = 1; + end + else if (bout_flag[2] == 1) begin + ib = 3; + ib_skp = 0; + end + else if (bout_flag[1] == 1) begin + ib = 2; + ib_skp = 0; + end + else if (bout_flag[0] == 1) begin + ib = 1; + ib_skp = 0; + end + else begin + ib = 0; + ib_skp = 0; + end + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + outbus <= 32'b0; + end + else begin + if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr[ib]) + 5'b00000 : if (buswidth[ib] == 2'b01) + rdbk_byte(crc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(crc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]); + 5'b00001 : if (buswidth[ib] == 2'b01) + rdbk_byte(far_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(far_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(far_reg[ib], rd_data_cnt[ib]); + 5'b00011 : if (buswidth[ib] == 2'b01) + rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]); + 5'b00100 : if (buswidth[ib] == 2'b01) + rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]); + 5'b00101 : if (buswidth[ib] == 2'b01) + rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]); + 5'b00110 : if (buswidth[ib] == 2'b01) + rdbk_byte(mask_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(mask_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]); + 5'b00111 : if (buswidth[ib] == 2'b01) + rdbk_byte(stat_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(stat_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]); + 5'b01001 : if (buswidth[ib] == 2'b01) + rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]); + 5'b01100 : if (buswidth[ib] == 2'b01) + rdbk_byte(DEVICE_ID, rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(DEVICE_ID, rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]); + 5'b01101 : if (buswidth[ib] == 2'b01) + rdbk_byte(axss_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(axss_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]); + 5'b01110 : if (buswidth[ib] == 2'b01) + rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]); + 5'b10000 : if (buswidth[ib] == 2'b01) + rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]); + 5'b10001 : if (buswidth[ib] == 2'b01) + rdbk_byte(timer_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(timer_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]); + 5'b10010 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + 5'b10011 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + 5'b10100 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]); + 5'b10101 : if (buswidth[ib] == 2'b01) + rdbk_byte(efar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(efar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]); + 5'b10110 : if (buswidth[ib] == 2'b01) + rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]); + 5'b11000 : if (buswidth[ib] == 2'b01) + rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]); + 5'b11001 : if (buswidth[ib] == 2'b01) + rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]); + 5'b11010 : if (buswidth[ib] == 2'b01) + rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]); + 5'b11011 : if (buswidth[ib] == 2'b01) + rdbk_byte(trim_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(trim_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]); + 5'b11111 : if (buswidth[ib] == 2'b01) + rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]); + endcase + if (ib != 0) begin + if (rd_data_cnt[ib] == 1) + rd_desynch_tmp <= 1; + end + end + else begin + outbus <= 32'b0; + rd_desynch <= rd_desynch_tmp; + rd_desynch_tmp <= 0; + end + end + + assign crc_rst[0] = crc_reset[0] | ~rst_intl; + assign crc_rst[1] = crc_reset[1] | ~rst_intl; + assign crc_rst[2] = crc_reset[2] | ~rst_intl; + assign crc_rst[3] = crc_reset[3] | ~rst_intl; + + assign crc_curr_cktmp = crc_curr[0]; + assign crc_reg_cktmp = crc_reg[0]; + + + + always @(posedge cclk_in or posedge crc_rst[0] ) + if (crc_rst[0] == 1) begin + crc_err_flag[0] <= 0; + crc_ck_en[0] <= 1; + end + else + if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin + if (crc_curr[0] != crc_reg[0]) + crc_err_flag[0] <= 1; + else + crc_err_flag[0] <= 0; + + crc_ck_en[0] <= 0; + end + else begin + crc_err_flag[0] <= 0; + crc_ck_en[0] <= 1; + end + + always @(posedge cclk_in or posedge crc_rst[1] ) + if (crc_rst[1] == 1) begin + crc_err_flag[1] <= 0; + crc_ck_en[1] <= 1; + end + else + if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin + if (crc_curr[1] != crc_reg[1]) + crc_err_flag[1] <= 1; + else + crc_err_flag[1] <= 0; + + crc_ck_en[1] <= 0; + end + else begin + crc_err_flag[1] <= 0; + crc_ck_en[1] <= 1; + + end + + always @(posedge cclk_in or posedge crc_rst[2] ) + if (crc_rst[2] == 1) begin + crc_err_flag[2] <= 0; + crc_ck_en[2] <= 1; + end + else + if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin + if (crc_curr[2] != crc_reg[2]) + crc_err_flag[2] <= 1; + else + crc_err_flag[2] <= 0; + + crc_ck_en[2] <= 0; + end + else begin + crc_err_flag[2] <= 0; + crc_ck_en[2] <= 1; + end + + always @(posedge cclk_in or posedge crc_rst[3] ) + if (crc_rst[3] == 1) begin + crc_err_flag[3] <= 0; + crc_ck_en[3] <= 1; + end + else + if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin + if (crc_curr[3] != crc_reg[3]) + crc_err_flag[3] <= 1; + else + crc_err_flag[3] <= 0; + + crc_ck_en[3] <= 0; + end + else begin + crc_err_flag[3] <= 0; + crc_ck_en[3] <= 1; + end + + always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0]) + if (rst_intl == 0) + crc_err_flag_reg[0] <= 0; + else if (crc_err_flag[0] == 1) + crc_err_flag_reg[0] <= 1; + else + crc_err_flag_reg[0] <= 0; + + always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1]) + if (rst_intl == 0) + crc_err_flag_reg[1] <= 0; + else if (crc_err_flag[1] == 1) + crc_err_flag_reg[1] <= 1; + else + crc_err_flag_reg[1] <= 0; + + always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2]) + if (rst_intl == 0) + crc_err_flag_reg[2] <= 0; + else if (crc_err_flag[2] == 1) + crc_err_flag_reg[2] <= 1; + else + crc_err_flag_reg[2] <= 0; + + always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3]) + if (rst_intl == 0) + crc_err_flag_reg[3] <= 0; + else if (crc_err_flag[3] == 1) + crc_err_flag_reg[3] <= 1; + else + crc_err_flag_reg[3] <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + startup_set <= 4'b0; + crc_reset <= 4'b0; + gsr_cmd_out <= 4'b0; + shutdown_set <= 4'b0; + desynch_set <= 4'b0; + ghigh_b <= 4'b0; + end + else + for (ci = 0; ci <=3; ci = ci+1) begin + if (cmd_reg_new_flag[ci] == 1) begin + if (cmd_reg[ci] == 5'b00011) + ghigh_b[ci] <= 1; + else if (cmd_reg[ci] == 5'b01000) + ghigh_b[ci] <= 0; + + if (cmd_reg[ci] == 5'b00101) + startup_set[ci] <= 1; + else + startup_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b00111) + crc_reset[ci] <= 1; + else + crc_reset[ci] <= 0; + + if (cmd_reg[ci] == 5'b01010) + gsr_cmd_out[ci] <= 1; + else + gsr_cmd_out[ci] <= 0; + + if (cmd_reg[ci] == 5'b01011) + shutdown_set[ci] <= 1; + else + shutdown_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b01101) + desynch_set[ci] <= 1; + else + desynch_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b01111) begin + iprog_b[ci] <= 0; + i_init_b_cmd[ci] <= 0; + iprog_b[ci] <= #cfg_Tprog 1; + i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set[ci] <= 0; + crc_reset[ci] <= 0; + gsr_cmd_out[ci] <= 0; + shutdown_set[ci] <= 0; + desynch_set[ci] <= 0; + end + end + + always @(posedge startup_set[0] or posedge desynch_set[0] or posedge rw_en[0] ) + if (rw_en[0] == 1 || desynch_set[0] == 1) + begin + if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin + if (icap_on == 0) + startup_set_pulse0 <= 2'b01; + else begin + startup_set_pulse0 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse0 <= 2'b00; + end + end + else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin + startup_set_pulse0 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse0 <= 2'b00; + end + end + + always @(posedge startup_set[1] or posedge desynch_set[1] or posedge rw_en[1] ) + if (rw_en[1] == 1 || desynch_set[1] == 1) + begin + if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin + if (icap_on == 0) + startup_set_pulse1 <= 2'b01; + else begin + startup_set_pulse1 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse1 <= 2'b00; + end + end + else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin + startup_set_pulse1 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse1 <= 2'b00; + end + end + + always @(posedge startup_set[2] or posedge desynch_set[2] or posedge rw_en[2]) + if (rw_en[2] == 1 || desynch_set[2] == 1) + begin + if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin + if (icap_on == 0) + startup_set_pulse2 <= 2'b01; + else begin + startup_set_pulse2 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse2 <= 2'b00; + end + end + else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin + startup_set_pulse2 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse2 <= 2'b00; + end + end + + always @(posedge startup_set[3] or posedge desynch_set[3] or posedge rw_en[3]) + if (rw_en[3] == 1 || desynch_set[3] == 1) + begin + if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin + if (icap_on == 0) + startup_set_pulse3 <= 2'b01; + else begin + startup_set_pulse3 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse3 <= 2'b00; + end + end + else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin + startup_set_pulse3 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse3 <= 2'b00; + end + end + + always @(posedge gsr_cmd_out[0] or negedge rw_en[0]) + if (rw_en[0] == 0) + gsr_cmd_out_pulse[0] <= 0; + else + begin + gsr_cmd_out_pulse[0] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[0] <= 0; + end + + always @(posedge gsr_cmd_out[1] or negedge rw_en[1]) + if (rw_en[1] == 0) + gsr_cmd_out_pulse[1] <= 0; + else + begin + gsr_cmd_out_pulse[1] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[1] <= 0; + end + + always @(posedge gsr_cmd_out[2] or negedge rw_en[2]) + if (rw_en[2] == 0) + gsr_cmd_out_pulse[2] <= 0; + else + begin + gsr_cmd_out_pulse[2] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[2] <= 0; + end + + always @(posedge gsr_cmd_out[3] or negedge rw_en[3]) + if (rw_en[3] == 0) + gsr_cmd_out_pulse[3] <= 0; + else + begin + gsr_cmd_out_pulse[3] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[3] <= 0; + end + + reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3; + + always @(ctl0_reg[0]) begin + ctl0_reg_tmp0 = ctl0_reg[0]; + if (ctl0_reg_tmp0[9] == 1) + abort_dis[0] = 1; + else + abort_dis[0] = 0; + if (ctl0_reg_tmp0[3] == 1) + persist_en[0] = 1; + else + persist_en[0] = 0; + if (ctl0_reg_tmp0[0] == 1) + gts_usr_b[0] = 1; + else + gts_usr_b[0] = 0; + end + + always @(ctl0_reg[1]) begin + ctl0_reg_tmp1 = ctl0_reg[1]; + if (ctl0_reg_tmp1[9] == 1) + abort_dis[1] = 1; + else + abort_dis[1] = 0; + if (ctl0_reg_tmp1[3] == 1) + persist_en[1] = 1; + else + persist_en[1] = 0; + if (ctl0_reg_tmp1[0] == 1) + gts_usr_b[1] = 1; + else + gts_usr_b[1] = 0; + end + + always @(ctl0_reg[2]) begin + ctl0_reg_tmp2 = ctl0_reg[2]; + if (ctl0_reg_tmp2[9] == 1) + abort_dis[2] = 1; + else + abort_dis[2] = 0; + if (ctl0_reg_tmp2[3] == 1) + persist_en[2] = 1; + else + persist_en[2] = 0; + if (ctl0_reg_tmp0[2] == 1) + gts_usr_b[2] = 1; + else + gts_usr_b[2] = 0; + end + + always @(ctl0_reg[3]) begin + ctl0_reg_tmp3 = ctl0_reg[3]; + if (ctl0_reg_tmp3[9] == 1) + abort_dis[3] = 1; + else + abort_dis[3] = 0; + if (ctl0_reg_tmp3[3] == 1) + persist_en[3] = 1; + else + persist_en[3] = 0; + if (ctl0_reg_tmp3[0] == 1) + gts_usr_b[3] = 1; + else + gts_usr_b[3] = 0; + end + + always @(cor0_reg[0]) + begin + cor0_reg_tmp0 = cor0_reg[0]; + done_cycle_reg0 = cor0_reg_tmp0[14:12]; + lock_cycle_reg0 = cor0_reg_tmp0[8:6]; + gts_cycle_reg0 = cor0_reg_tmp0[5:3]; + gwe_cycle_reg0 = cor0_reg_tmp0[2:0]; + + if (cor0_reg_tmp0[24] == 1'b1) + done_pin_drv[0] = 1; + else + done_pin_drv[0] = 0; + + if (cor0_reg_tmp0[28] == 1'b1) + crc_bypass[0] = 1; + else + crc_bypass[0] = 0; + end + + always @(cor0_reg[1]) + begin + cor0_reg_tmp1 = cor0_reg[1]; + done_cycle_reg1 = cor0_reg_tmp1[14:12]; + lock_cycle_reg1 = cor0_reg_tmp1[8:6]; + gts_cycle_reg1 = cor0_reg_tmp1[5:3]; + gwe_cycle_reg1 = cor0_reg_tmp1[2:0]; + + if (cor0_reg_tmp1[24] == 1'b1) + done_pin_drv[1] = 1; + else + done_pin_drv[1] = 0; + + if (cor0_reg_tmp1[28] == 1'b1) + crc_bypass[1] = 1; + else + crc_bypass[1] = 0; + end + + always @(cor0_reg[2]) + begin + cor0_reg_tmp2 = cor0_reg[2]; + done_cycle_reg2 = cor0_reg_tmp2[14:12]; + lock_cycle_reg2 = cor0_reg_tmp2[8:6]; + gts_cycle_reg2 = cor0_reg_tmp2[5:3]; + gwe_cycle_reg2 = cor0_reg_tmp2[2:0]; + + if (cor0_reg_tmp2[24] == 1'b1) + done_pin_drv[2] = 1; + else + done_pin_drv[2] = 0; + + if (cor0_reg_tmp2[28] == 1'b1) + crc_bypass[2] = 1; + else + crc_bypass[2] = 0; + end + + always @(cor0_reg[3]) + begin + cor0_reg_tmp3 = cor0_reg[3]; + done_cycle_reg3 = cor0_reg_tmp3[14:12]; + lock_cycle_reg3 = cor0_reg_tmp3[8:6]; + gts_cycle_reg3 = cor0_reg_tmp3[5:3]; + gwe_cycle_reg3 = cor0_reg_tmp3[2:0]; + + if (cor0_reg_tmp3[24] == 1'b1) + done_pin_drv[3] = 1; + else + done_pin_drv[3] = 0; + + if (cor0_reg_tmp3[28] == 1'b1) + crc_bypass[3] = 1; + else + crc_bypass[3] = 0; + end + + always @(cor1_reg[0]) begin + cor1_reg_tmp0 = cor1_reg[0]; + rbcrc_no_pin[0] = cor1_reg_tmp0[8]; + end + + always @(cor1_reg[1]) begin + cor1_reg_tmp1 = cor1_reg[1]; + rbcrc_no_pin[1] = cor1_reg_tmp1[8]; + end + + always @(cor1_reg[2]) begin + cor1_reg_tmp2 = cor1_reg[2]; + rbcrc_no_pin[2] = cor1_reg_tmp2[8]; + end + + always @(cor1_reg[3]) begin + cor1_reg_tmp3 = cor1_reg[3]; + rbcrc_no_pin[3] = cor1_reg_tmp3[8]; + end + + assign stat_reg_tmp0[31:27] = 5'b00000; + assign stat_reg_tmp1[31:27] = 5'b00000; + assign stat_reg_tmp2[31:27] = 5'b00000; + assign stat_reg_tmp3[31:27] = 5'b00000; + assign stat_reg_tmp0[24:21] = 4'bxxx0; + assign stat_reg_tmp1[24:21] = 4'bxxx0; + assign stat_reg_tmp2[24:21] = 4'bxxx0; + assign stat_reg_tmp3[24:21] = 4'bxxx0; + assign stat_reg_tmp0[17:16] = 2'b0; + assign stat_reg_tmp1[17:16] = 2'b0; + assign stat_reg_tmp2[17:16] = 2'b0; + assign stat_reg_tmp3[17:16] = 2'b0; + assign stat_reg_tmp0[14] = DONE; + assign stat_reg_tmp1[14] = DONE; + assign stat_reg_tmp2[14] = DONE; + assign stat_reg_tmp3[14] = DONE; + assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0; + assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0; + assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0; + assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0; + assign stat_reg_tmp0[12] = INITB; + assign stat_reg_tmp1[12] = INITB; + assign stat_reg_tmp2[12] = INITB; + assign stat_reg_tmp3[12] = INITB; + assign stat_reg_tmp0[11] = mode_sample_flag; + assign stat_reg_tmp1[11] = mode_sample_flag; + assign stat_reg_tmp2[11] = mode_sample_flag; + assign stat_reg_tmp3[11] = mode_sample_flag; + assign stat_reg_tmp0[10:8] = mode_pin_in; + assign stat_reg_tmp1[10:8] = mode_pin_in; + assign stat_reg_tmp2[10:8] = mode_pin_in; + assign stat_reg_tmp3[10:8] = mode_pin_in; + assign stat_reg_tmp0[3] = 1'b1; + assign stat_reg_tmp1[3] = 1'b1; + assign stat_reg_tmp2[3] = 1'b1; + assign stat_reg_tmp3[3] = 1'b1; + assign stat_reg_tmp0[2] = pll_locked; + assign stat_reg_tmp1[2] = pll_locked; + assign stat_reg_tmp2[2] = pll_locked; + assign stat_reg_tmp3[2] = pll_locked; + assign stat_reg_tmp0[1] = 1'b0; + assign stat_reg_tmp1[1] = 1'b0; + assign stat_reg_tmp2[1] = 1'b0; + assign stat_reg_tmp3[1] = 1'b0; + + assign stat_reg_tmp0[26:25] = buswidth[0]; + assign stat_reg_tmp0[20:18] = st_state0; + assign stat_reg_tmp0[15] = id_error_flag[0]; + assign stat_reg_tmp0[7] = ghigh_b[0]; + assign stat_reg_tmp0[6] = gwe_out[0]; + assign stat_reg_tmp0[5] = gts_cfg_b[0]; + assign stat_reg_tmp0[4] = eos_startup[0]; + assign stat_reg_tmp0[0] = crc_err_flag_reg[0]; + + assign stat_reg_tmp1[26:25] = buswidth[1]; + assign stat_reg_tmp1[20:18] = st_state1; + assign stat_reg_tmp1[15] = id_error_flag[1]; + assign stat_reg_tmp1[7] = ghigh_b[1]; + assign stat_reg_tmp1[6] = gwe_out[1]; + assign stat_reg_tmp1[5] = gts_cfg_b[1]; + assign stat_reg_tmp1[4] = eos_startup[1]; + assign stat_reg_tmp1[0] = crc_err_flag_reg[1]; + + assign stat_reg_tmp2[26:25] = buswidth[2]; + assign stat_reg_tmp2[20:18] = st_state2; + assign stat_reg_tmp2[15] = id_error_flag[2]; + assign stat_reg_tmp2[7] = ghigh_b[2]; + assign stat_reg_tmp2[6] = gwe_out[2]; + assign stat_reg_tmp2[5] = gts_cfg_b[2]; + assign stat_reg_tmp2[4] = eos_startup[2]; + assign stat_reg_tmp2[0] = crc_err_flag_reg[2]; + + assign stat_reg_tmp3[26:25] = buswidth[3]; + assign stat_reg_tmp3[20:18] = st_state3; + assign stat_reg_tmp3[15] = id_error_flag[3]; + assign stat_reg_tmp3[7] = ghigh_b[3]; + assign stat_reg_tmp3[6] = gwe_out[3]; + assign stat_reg_tmp3[5] = gts_cfg_b[3]; + assign stat_reg_tmp3[4] = eos_startup[3]; + assign stat_reg_tmp3[0] = crc_err_flag_reg[3]; + + assign stat_reg[0] = stat_reg_tmp0; + assign stat_reg[1] = stat_reg_tmp1; + assign stat_reg[2] = stat_reg_tmp2; + assign stat_reg[3] = stat_reg_tmp3; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state0 <= STARTUP_PH0; + st_state1 <= STARTUP_PH0; + st_state2 <= STARTUP_PH0; + st_state3 <= STARTUP_PH0; + startup_begin_flag0 <= 0; + startup_begin_flag1 <= 0; + startup_begin_flag2 <= 0; + startup_begin_flag3 <= 0; + startup_end_flag0 <= 0; + startup_end_flag1 <= 0; + startup_end_flag2 <= 0; + startup_end_flag3 <= 0; + end + else begin + st_state0i = st_state0; + cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0, + st_state0i, nx_st_state0,lock_cycle_reg0); + + st_state1i = st_state1; + cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1, + st_state1i, nx_st_state1,lock_cycle_reg1); + + st_state2i = st_state2; + cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2, + st_state2i, nx_st_state2,lock_cycle_reg2); + + st_state3i = st_state3; + cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3, + st_state3i, nx_st_state3,lock_cycle_reg3); + end + + task cur_st_tsk; + output stup_bflag; + output stup_eflag; + output [2:0] cst_o; + input [2:0] cst_in; + input [2:0] nst_in; + input [2:0] lock_cycle_in; + begin + if (nst_in == STARTUP_PH1) begin + stup_bflag = 1; + stup_eflag = 0; + end + else if (cst_in == STARTUP_PH7) begin + stup_eflag = 1; + stup_bflag = 0; + end + if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin + cst_o = nst_in; + end + else + cst_o = cst_in; + end + endtask + + always @(st_state0 or startup_set_pulse0 or DONE ) begin + nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0); + end + + always @(st_state1 or startup_set_pulse1 or DONE ) begin + nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1); + end + + always @(st_state2 or startup_set_pulse2 or DONE ) begin + nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2); + end + + always @(st_state3 or startup_set_pulse3 or DONE ) begin + nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3); + end + + task nx_st_tsk; + output [2:0] nx_st; + input [2:0] cur_st; + input [1:0] stup_pulse; + input [2:0] done_cycle_in; + begin + if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in)) + case (cur_st) + STARTUP_PH0 : if (stup_pulse == 2'b11 ) + nx_st = STARTUP_PH1; + else + nx_st = STARTUP_PH0; + STARTUP_PH1 : nx_st = STARTUP_PH2; + + STARTUP_PH2 : nx_st = STARTUP_PH3; + + STARTUP_PH3 : nx_st = STARTUP_PH4; + + STARTUP_PH4 : nx_st = STARTUP_PH5; + + STARTUP_PH5 : nx_st = STARTUP_PH6; + + STARTUP_PH6 : nx_st = STARTUP_PH7; + + STARTUP_PH7 : nx_st = STARTUP_PH0; + endcase + end + endtask + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 4'b0; + gts_out <= 4'b1111; + eos_startup <= 4'b0; + gsr_st_out <= 4'b1111; + done_o <= 4'b0; + end + else begin + if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin + if (DONE !== 0 || done_pin_drv[0] === 1) + done_o[0] <= 1'b1; + else + done_o[0] <= 1'bz; + end + + if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin + if (DONE !== 0 || done_pin_drv[1] == 1) + done_o[1] <= 1'b1; + else + done_o[1] <= 1'bz; + end + + if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin + if (DONE !== 0 || done_pin_drv[2] == 1) + done_o[2] <= 1'b1; + else + done_o[2] <= 1'bz; + end + + if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin + if (DONE !== 0 || done_pin_drv[3] == 1) + done_o[3] <= 1'b1; + else + done_o[3] <= 1'bz; + end + + if (st_state0 == gwe_cycle_reg0) + gwe_out[0] <= 1; + if (st_state1 == gwe_cycle_reg1) + gwe_out[1] <= 1; + if (st_state2 == gwe_cycle_reg2) + gwe_out[2] <= 1; + if (st_state3 == gwe_cycle_reg3) + gwe_out[3] <= 1; + + if (st_state0 == gts_cycle_reg0 ) + gts_out[0] <= 0; + if (st_state1 == gts_cycle_reg1 ) + gts_out[1] <= 0; + if (st_state2 == gts_cycle_reg2 ) + gts_out[2] <= 0; + if (st_state3 == gts_cycle_reg3 ) + gts_out[3] <= 0; + + if (st_state0 == STARTUP_PH6 ) + gsr_st_out[0] <= 0; + if (st_state1 == STARTUP_PH6 ) + gsr_st_out[1] <= 0; + if (st_state2 == STARTUP_PH6 ) + gsr_st_out[2] <= 0; + if (st_state3 == STARTUP_PH6 ) + gsr_st_out[3] <= 0; + + if (st_state0 == STARTUP_PH7 ) + eos_startup[0] <= 1; + if (st_state1 == STARTUP_PH7 ) + eos_startup[1] <= 1; + if (st_state2 == STARTUP_PH7 ) + eos_startup[2] <= 1; + if (st_state3 == STARTUP_PH7 ) + eos_startup[3] <= 1; + end + + assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0]; + assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1]; + assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2]; + assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3]; + + assign abort_dis_bi = abort_dis[ib]; + + always @(posedge cclk_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin + abort_flag[ib] <= 0; + checka_en <= 0; + rdwr_b_in1 <= rdwr_b_in; + end + else begin + if ( abort_dis_bi == 0 && csi_b_in == 0) begin + if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin + abort_flag[ib] <= 1; + if (icap_on == 0) + $display("Warning: [Unisim %s-10]Warning : RDWRB changes when CSB low, which causes Configuration abort at time %t. Instance %m", MODULE_NAME, $time); + end + end + else + abort_flag[ib] <= 0; + + rdwr_b_in1 <= rdwr_b_in; + checka_en <= 1; + end + + always @(posedge abort_flag[ib]) + begin + abort_out_en <= 1; + abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) begin + abort_out_en <= 0; + abort_flag_rst <= 1; + end + @(posedge cclk_in) + abort_flag_rst <= 0; + end + + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + +task rdbk_byte; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + outbus[31:8] <= 24'b0; + if (rd_dcnt==1) + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + else if (rd_dcnt==2) + outbus[7:0] <= bit_revers8(rdbk_reg[15:8]); + else if (rd_dcnt==3) + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + else if (rd_dcnt==4) + outbus[7:0] <= bit_revers8(rdbk_reg[31:24]); + end +endtask + +task rdbk_wd; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + outbus[31:16] <= 16'b0; + if (rd_dcnt==1) + outbus[15:0] <= 16'b0; + else if (rd_dcnt==2) + outbus[15:0] <= 16'b0; + else if (rd_dcnt==3) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + end + else if (rd_dcnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + outbus[15:8] <= bit_revers8(rdbk_reg[31:24]); + end + end +endtask + +task rdbk_2wd; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + if (rd_dcnt==1) + outbus <= 32'b0; + else if (rd_dcnt==2) + outbus <= 32'b0; + else if (rd_dcnt==3) + outbus <= 32'b0; + else if (rd_dcnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + outbus[23:16] <= bit_revers8(rdbk_reg[23:16]); + outbus[31:24] <= bit_revers8(rdbk_reg[31:24]); + end + end +endtask + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SIM_CONFIGE3.v b/verilog/src/unisims/SIM_CONFIGE3.v new file mode 100644 index 0000000..7ba7651 --- /dev/null +++ b/verilog/src/unisims/SIM_CONFIGE3.v @@ -0,0 +1,2507 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIGE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/31/12 - Initial version +// 09/09/13 - Fixed output IDCODE (CR 727695). +// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079). +// 02/14/14 - Fixed Non-Continous data loading problem (CR 690809). +// 05/28/14 - New simulation library message format. +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module SIM_CONFIGE3 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter DEVICE_ID = 32'h0, + parameter ICAP_SUPPORT = "FALSE", + parameter ICAP_WIDTH = "X8" +) ( + output AVAIL, + output CSOB, + output PRDONE, + output PRERROR, + inout DONE, + input CCLK, + input CSB, + inout [31:0] D, + inout INITB, + input [2:0] M, + input PROGB, + input RDWRB +); + + localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt"; + localparam cfg_Tprog = 250000; // min PROG must be low + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + +// tri0 GSR, GTS, GWE; + + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + wire rdwr_b_in; + reg rdwr_b_in1; + reg checka_en; + reg init_b_out; + reg [3:0] done_o; + integer frame_data_fd; + integer farn; + integer ib; + integer ib_skp, ci, bi; + reg frame_data_wen; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire [31:0] d_in; + wire [31:0] d_out; + wire busy_out; + wire cso_b_out; + wire csi_b_in; + reg csi_b_ins; + wire d_out_en; + wire pll_locked; + reg pll_lockwt; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire [3:0] desync_flag; + wire [3:0] crc_rst; + reg [3:0] crc_bypass; + reg icap_on; + reg icap_clr; + reg icap_sync; + reg icap_desynch; + reg rd_desynch; + reg rd_desynch_tmp; + reg icap_init_done; + reg icap_init_done_dly; + wire [3:0] desynch_set1; + reg [1:0] icap_bw; + +// assign DONE = p_up; +// assign INITB = p_up; + assign (strong1, weak0) glbl.GSR = GSR; + assign (strong1, weak0) glbl.GTS = GTS; + assign glbl.PROGB_GLBL = PROGB; + assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1; + + buf buf_cso (CSOB, cso_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_cs (csi_b_in, CSB); + + buf buf_din[31:0] (d_in, D); + bufif1 buf_dout[31:0] (D, d_out, d_out_en); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge; + time prog_pulse_low; + reg mode_sample_flag; + reg [3:0] buswid_flag_init; + reg [3:0] buswid_flag; + reg [1:0] buswidth[3:0]; + wire [1:0] buswidth_ibtmp; + reg [1:0] buswidth_tmp[3:0]; + reg [31:0] pack_in_reg[3:0]; + reg [31:0] pack_in_reg_tmp0; + reg [31:0] pack_in_reg_tmps0; + reg [31:0] pack_in_reg_tmp; + reg [4:0] reg_addr[3:0]; + reg [4:0] reg_addr_tmp; + reg [3:0] new_data_in_flag; + reg [3:0] wr_flag; + reg [3:0] rd_flag; + reg [3:0] cmd_wr_flag; + reg [3:0] cmd_reg_new_flag; + reg [3:0] cmd_rd_flag; + reg [3:0] bus_sync_flag; + reg [3:0] conti_data_flag; + integer wr_cnt[3:0]; + integer conti_data_cnt[3:0]; + integer rd_data_cnt[3:0]; + integer abort_cnt; + reg [2:0] st_state0; + reg [2:0] st_state1; + reg [2:0] st_state2; + reg [2:0] st_state3; + reg [2:0] st_state0i; + reg [2:0] st_state1i; + reg [2:0] st_state2i; + reg [2:0] st_state3i; + reg startup_begin_flag0; + reg startup_end_flag0; + reg startup_begin_flag1; + reg startup_end_flag1; + reg startup_begin_flag2; + reg startup_end_flag2; + reg startup_begin_flag3; + reg startup_end_flag3; + reg [3:0] crc_ck; + reg [3:0] crc_ck_en; + reg [3:0] crc_err_flag; + wire [3:0] crc_err_flag_tot; + reg [3:0] crc_err_flag_reg; + wire [3:0] crc_en; + reg [31:0] crc_curr[3:0]; + reg [31:0] crc_curr_tmp; + wire [31:0] crc_curr_cktmp; + reg [31:0] crc_new; + reg [36:0] crc_input; + reg [31:0] rbcrc_curr[3:0]; + reg [31:0] rbcrc_new; + reg [36:0] rbcrc_input; + reg [3:0] gwe_out; + reg [3:0] gts_out; + reg [31:0] d_o; + reg [31:0] outbus; + reg [31:0] outbus_dly; + reg [31:0] outbus_dly1; + reg busy_o; + reg [31:0] tmp_val1; + reg [31:0] tmp_val2; + reg [31:0] crc_reg[3:0]; + reg [31:0] crc_reg_tmp; + wire [31:0] crc_reg_cktmp; + reg [31:0] far_reg[3:0]; + reg [31:0] far_addr; + reg [31:0] fdri_reg[3:0]; + reg [31:0] fdro_reg[3:0]; + reg [4:0] cmd_reg[3:0]; + reg [31:0] ctl0_reg[3:0]; + reg [31:0] mask_reg[3:0]; + wire [31:0] stat_reg[3:0]; + wire [31:0] stat_reg_tmp0; + wire [31:0] stat_reg_tmp1; + wire [31:0] stat_reg_tmp2; + wire [31:0] stat_reg_tmp3; + reg [31:0] lout_reg[3:0]; + reg [31:0] cor0_reg[3:0]; + reg [31:0] cor0_reg_tmp0; + reg [31:0] cor0_reg_tmp1; + reg [31:0] cor0_reg_tmp2; + reg [31:0] cor0_reg_tmp3; + reg [31:0] mfwr_reg[3:0]; + reg [31:0] cbc_reg[3:0]; + reg [31:0] idcode_reg[3:0]; + reg [31:0] axss_reg[3:0]; + reg [31:0] cor1_reg[3:0]; + reg [31:0] cor1_reg_tmp0; + reg [31:0] cor1_reg_tmp1; + reg [31:0] cor1_reg_tmp2; + reg [31:0] cor1_reg_tmp3; + reg [31:0] csob_reg[3:0]; + reg [31:0] wbstar_reg[3:0]; + reg [31:0] timer_reg[3:0]; + reg [31:0] rbcrc_hw_reg[3:0]; + reg [31:0] rbcrc_sw_reg[3:0]; + reg [31:0] rbcrc_live_reg[3:0]; + reg [31:0] efar_reg[3:0]; + reg [31:0] bootsts_reg[3:0]; + reg [31:0] ctl1_reg[3:0]; + reg [31:0] testmode_reg[3:0]; + reg [31:0] memrd_param_reg[3:0]; + reg [31:0] dwc_reg[3:0]; + reg [31:0] trim_reg[3:0]; + reg [31:0] bout_reg[3:0]; + reg [31:0] bspi_reg[3:0]; + reg [2:0] mode_pin_in; + reg [2:0] mode_reg; + reg [3:0] crc_reset; + reg [3:0] gsr_set; + reg [3:0] gts_usr_b; + reg [3:0] done_pin_drv; + + reg [3:0] shutdown_set; + reg [3:0] desynch_set; + reg [2:0] done_cycle_reg0; + reg [2:0] done_cycle_reg1; + reg [2:0] done_cycle_reg2; + reg [2:0] done_cycle_reg3; + reg [2:0] gts_cycle_reg0; + reg [2:0] gts_cycle_reg1; + reg [2:0] gts_cycle_reg2; + reg [2:0] gts_cycle_reg3; + reg [2:0] gwe_cycle_reg0; + reg [2:0] gwe_cycle_reg1; + reg [2:0] gwe_cycle_reg2; + reg [2:0] gwe_cycle_reg3; + reg init_pin; + reg init_rst; + reg [2:0] nx_st_state0; + reg [2:0] nx_st_state1; + reg [2:0] nx_st_state2; + reg [2:0] nx_st_state3; + reg [3:0] ghigh_b; + reg [3:0] gts_cfg_b; + reg [3:0] eos_startup; + reg [3:0] startup_set; + reg [1:0] startup_set_pulse0; + reg [1:0] startup_set_pulse1; + reg [1:0] startup_set_pulse2; + reg [1:0] startup_set_pulse3; + reg abort_out_en; + reg [31:0] tmp_dword; + reg [15:0] tmp_word; + reg [7:0] tmp_byte; + reg [3:0] id_error_flag; + wire id_error_flag_t; + reg [3:0] iprog_b; + wire iprog_b_t; + reg [3:0] i_init_b_cmd; + wire i_init_b_cmd_t; + reg i_init_b; + reg [7:0] abort_status; + reg [3:0] persist_en; + reg [3:0] rst_sync; + reg [3:0] abort_dis; + reg [2:0] lock_cycle_reg0; + reg [2:0] lock_cycle_reg1; + reg [2:0] lock_cycle_reg2; + reg [2:0] lock_cycle_reg3; + reg [3:0] rbcrc_no_pin; + reg abort_flag_rst; + reg [3:0] gsr_st_out; + reg [3:0] gsr_cmd_out; + reg [3:0] gsr_cmd_out_pulse; + reg d_o_en; + wire rst_intl; + wire rw_en_tmp1; + wire [3:0] rw_en; + wire [3:0] gsr_out; + wire [3:0] cfgerr_b_flag; + reg [3:0] abort_flag; + integer downcont_cnt; + reg rst_en; + reg prog_b_a; + reg [3:0] csbo_flag; + reg [3:0] bout_flag; + reg [3:0] bout_flags; + reg [3:0] bout_bf; + reg [3:0] bout_en; + reg rd_sw_en; + integer csbo_cnt[3:0]; + integer bout_cnt[3:0]; + integer bout_cnt_tmp; + reg [4:0] rd_reg_addr[3:0]; + reg done_release; + + wire iprog_b_0; + wire iprog_b_1; + wire iprog_b_2; + wire iprog_b_3; + wire i_init_b_cmd_0; + wire i_init_b_cmd_1; + wire i_init_b_cmd_2; + wire i_init_b_cmd_3; + wire rw_en_tmp; + wire desync_flag_t; + wire abort_dis_bi; + + assign (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out; + + assign (weak1, strong0) DONE = (done_o[0] !== 1'b0) && + ((bout_en[1] == 0) || (done_o[1] !== 1'b0)) && + ((bout_en[2] == 0) || (done_o[2] !== 1'b0)) && + ((bout_en[3] == 0) || (done_o[3] !== 1'b0)); +// +// assign (weak1, strong0) DONE= (bout_en[1] == 0) || done_o[1]; +// assign (weak1, strong0) DONE= (bout_en[2] == 0) || done_o[2]; +// assign (weak1, strong0) DONE= (bout_en[3] == 0) || done_o[3]; + + + reg PRDONE_out; + assign PRDONE = PRDONE_out; + + reg fdri_rst_prdone_flag; + localparam MODULE_NAME = "SIM_CONFIGE3"; + + always @(fdri_rst_prdone_flag or desync_flag or eos_startup) + if (fdri_rst_prdone_flag) begin + PRDONE_out = 1'b0; + end else if ((&desync_flag) & (&eos_startup)) begin + PRDONE_out = 1'b1; + end + + assign PRERROR = (|rw_en) & (|crc_err_flag_tot); + + initial begin + if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093") + bout_en = 4'b0011; + else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093") + bout_en = 4'b0111; + else if (DEVICE_ID == "036A6093") + bout_en = 4'b1111; + else + bout_en = 4'b0001; + end + + + + initial begin + buswidth_tmp[0] = 2'b00; + buswidth_tmp[1] = 2'b00; + buswidth_tmp[2] = 2'b00; + buswidth_tmp[3] = 2'b00; + pack_in_reg[0] = 32'b0; + pack_in_reg[1] = 32'b0; + pack_in_reg[2] = 32'b0; + pack_in_reg[3] = 32'b0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + pack_in_reg_tmp = 32'b0; + crc_curr[0] = 32'b0; + crc_curr[1] = 32'b0; + crc_curr[2] = 32'b0; + crc_curr[3] = 32'b0; + rbcrc_curr[0] = 32'b0; + rbcrc_curr[1] = 32'b0; + rbcrc_curr[2] = 32'b0; + rbcrc_curr[3] = 32'b0; + ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1; + cor0_reg[0] = 32'b00000000000000000011111111101100; + cor0_reg[1] = 32'b00000000000000000011111111101100; + cor0_reg[2] = 32'b00000000000000000011111111101100; + cor0_reg[3] = 32'b00000000000000000011111111101100; + cor0_reg_tmp0 = cor0_reg[0]; + cor0_reg_tmp1 = cor0_reg[1]; + cor0_reg_tmp2 = cor0_reg[2]; + cor0_reg_tmp3 = cor0_reg[3]; + done_cycle_reg0 = cor0_reg_tmp0[14:12]; + lock_cycle_reg0 = cor0_reg_tmp0[8:6]; + done_cycle_reg1 = cor0_reg_tmp0[14:12]; + lock_cycle_reg1 = cor0_reg_tmp0[8:6]; + done_cycle_reg2 = cor0_reg_tmp0[14:12]; + lock_cycle_reg2 = cor0_reg_tmp0[8:6]; + done_cycle_reg3 = cor0_reg_tmp0[14:12]; + lock_cycle_reg3 = cor0_reg_tmp0[8:6]; + cor1_reg[0] = 32'b0; + cor1_reg[1] = 32'b0; + cor1_reg[2] = 32'b0; + cor1_reg[3] = 32'b0; + cor1_reg_tmp0 = 32'b0; + cor1_reg_tmp1 = 32'b0; + cor1_reg_tmp2 = 32'b0; + cor1_reg_tmp3 = 32'b0; + wbstar_reg[0] = 32'b0; + wbstar_reg[1] = 32'b0; + wbstar_reg[2] = 32'b0; + wbstar_reg[3] = 32'b0; + timer_reg[0] = 32'b0; + timer_reg[1] = 32'b0; + timer_reg[2] = 32'b0; + timer_reg[3] = 32'b0; + bootsts_reg[0] = 32'b0; + bootsts_reg[1] = 32'b0; + bootsts_reg[2] = 32'b0; + bootsts_reg[3] = 32'b0; + ctl1_reg[0] = 32'b0; + ctl1_reg[1] = 32'b0; + ctl1_reg[2] = 32'b0; + ctl1_reg[3] = 32'b0; + testmode_reg[0] = 32'b0; + testmode_reg[1] = 32'b0; + testmode_reg[2] = 32'b0; + testmode_reg[3] = 32'b0; + memrd_param_reg[0] = 32'b0; + memrd_param_reg[1] = 32'b0; + memrd_param_reg[2] = 32'b0; + memrd_param_reg[3] = 32'b0; + dwc_reg[0] = 32'b0; + dwc_reg[1] = 32'b0; + dwc_reg[2] = 32'b0; + dwc_reg[3] = 32'b0; + trim_reg[0] = 32'b0; + trim_reg[1] = 32'b0; + trim_reg[2] = 32'b0; + trim_reg[3] = 32'b0; + bout_reg[0] = 32'b0; + bout_reg[1] = 32'b0; + bout_reg[2] = 32'b0; + bout_reg[3] = 32'b0; + bspi_reg[0] = 32'h000B; + bspi_reg[1] = 32'h000B; + bspi_reg[2] = 32'h000B; + bspi_reg[3] = 32'h000B; + rd_reg_addr[0] = 5'b0; + rd_reg_addr[1] = 5'b0; + rd_reg_addr[2] = 5'b0; + rd_reg_addr[3] = 5'b0; + wr_cnt[0] = 0; + wr_cnt[1] = 0; + wr_cnt[2] = 0; + wr_cnt[3] = 0; + bout_cnt[0] = 0; + bout_cnt[1] = 0; + bout_cnt[2] = 0; + bout_cnt[3] = 0; + done_o = 4'b0; + checka_en = 1'b0; + init_b_out = 1'b1; + farn = 0; + ib = 0; + csi_b_ins = 1'b1; + crc_bypass = 4'b0000; + icap_clr = 1'b0; + icap_desynch = 1'b0; + rd_desynch = 1'b0; + rd_desynch_tmp = 1'b0; + icap_init_done = 1'b0; + icap_init_done_dly = 1'b0; + prog_pulse_low_edge = 0; + prog_pulse_low = 0; + mode_sample_flag = 1'b0; + buswid_flag_init = 4'b0000; + buswid_flag = 4'b0000; + new_data_in_flag = 4'b0000; + wr_flag = 4'b0000; + rd_flag = 4'b0000; + cmd_wr_flag = 4'b0000; + cmd_reg_new_flag = 4'b0000; + cmd_rd_flag = 4'b0000; + bus_sync_flag = 4'b0000; + conti_data_flag = 4'b0000; + st_state0 = STARTUP_PH0; + st_state1 = STARTUP_PH0; + st_state2 = STARTUP_PH0; + st_state3 = STARTUP_PH0; + st_state0i = STARTUP_PH0; + st_state1i = STARTUP_PH0; + st_state2i = STARTUP_PH0; + st_state3i = STARTUP_PH0; + startup_begin_flag0 = 1'b0; + startup_end_flag0 = 1'b0; + startup_begin_flag1 = 1'b0; + startup_end_flag1 = 1'b0; + startup_begin_flag2 = 1'b0; + startup_end_flag2 = 1'b0; + startup_begin_flag3 = 1'b0; + startup_end_flag3 = 1'b0; + crc_ck = 4'b0000; + crc_ck_en = 4'b1111; + crc_err_flag = 4'b0000; + crc_err_flag_reg = 4'b0000; + gwe_out = 4'b0000; + gts_out = 4'b1111; + d_o = 32'h0; + outbus = 32'h0; + outbus_dly = 32'h0; + outbus_dly1 = 32'h0; + busy_o = 1'b0; + mode_pin_in = 3'b000; + crc_reset = 4'b0000; + gsr_set = 4'b0000; + gts_usr_b = 4'b1111; // was 4'b111 + done_pin_drv = 4'b0000; + shutdown_set = 4'b0000; + desynch_set = 4'b0000; + done_cycle_reg0 = 3'b011; + done_cycle_reg1 = 3'b011; + done_cycle_reg2 = 3'b011; + done_cycle_reg3 = 3'b011; + gts_cycle_reg0 = 3'b101; + gts_cycle_reg1 = 3'b101; + gts_cycle_reg2 = 3'b101; + gts_cycle_reg3 = 3'b101; + gwe_cycle_reg0 = 3'b100; + gwe_cycle_reg1 = 3'b100; + gwe_cycle_reg2 = 3'b100; + gwe_cycle_reg3 = 3'b100; + init_rst = 1'b0; + nx_st_state0 = 3'b000; + nx_st_state1 = 3'b000; + nx_st_state2 = 3'b000; + nx_st_state3 = 3'b000; + ghigh_b = 4'b0000; + gts_cfg_b = 4'b0000; + eos_startup = 4'b0000; + startup_set = 4'b0000; + startup_set_pulse0 = 2'b00; + startup_set_pulse1 = 2'b00; + startup_set_pulse2 = 2'b00; + startup_set_pulse3 = 2'b00; + abort_out_en = 1'b0; + id_error_flag = 4'b0000; + iprog_b = 4'b1111; + i_init_b_cmd = 4'b1111; + i_init_b = 1'b0; + abort_status = 8'b00000000; + persist_en = 1'b0; + rst_sync = 1'b0; + abort_dis = 1'b0; + lock_cycle_reg0 = 3'b000; + lock_cycle_reg1 = 3'b000; + lock_cycle_reg2 = 3'b000; + lock_cycle_reg3 = 3'b000; + rbcrc_no_pin = 4'b0000; + abort_flag_rst = 1'b0; + gsr_st_out = 4'b1111; + gsr_cmd_out = 4'b0000; + gsr_cmd_out_pulse = 4'b0000; + d_o_en = 1'b0; + abort_flag = 4'b0000; + downcont_cnt = 0; + rst_en = 1'b0; + prog_b_a = 1'b1; + csbo_flag = 4'b0000; + bout_flag = 4'b0000; + bout_flags = 4'b0000; + bout_bf = 4'b0000; + rd_sw_en = 1'b0; + done_release = 1'b0; + PRDONE_out = 1'b0; + fdri_rst_prdone_flag = 1'b0; + end + + + initial begin + + case (ICAP_SUPPORT) + "FALSE" : icap_on = 0; + "TRUE" : icap_on = 1; + default : icap_on = 0; + endcase + + if (DEVICE_ID == 32'h0 && icap_on == 0) begin + $display("Error: [Unisim %s-1] DEVICE_ID attribute is not set. Instance: %m", MODULE_NAME); + end + + if (ICAP_SUPPORT == "TRUE") begin + case (ICAP_WIDTH) + "X8" : icap_bw = 2'b01; + "X16" : icap_bw = 2'b10; + "X32" : icap_bw = 2'b11; + default : icap_bw = 2'b01; + endcase + + frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w"); + if (frame_data_fd != 0) begin + frame_data_wen = 1; + $fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n"); + end + end + else begin + icap_bw = 2'b00; + frame_data_wen = 0; + end + + icap_sync = 0; + + end + + + assign GSR = gsr_out[0]; + assign GTS = gts_out[0]; + assign GWE = gwe_out[0]; + assign busy_out = busy_o; + assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0]; + assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1]; + assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2]; + assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3]; + assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0]; + assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1]; + assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2]; + assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3]; + assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0]; + assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8]; + assign d_out_en = d_o_en; + assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1; + assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111; + + + always @(posedge cclk_in) begin + outbus_dly <= outbus_dly1; + outbus_dly1 <= outbus; + end + + always @(posedge cclk_in or csi_b_in) + if (csi_b_in == 1) + csi_b_ins <= csi_b_in; + else begin + if (cclk_in != 1) + csi_b_ins <= csi_b_in; + else + @(negedge cclk_in) + csi_b_ins <= csi_b_in; + end + + always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] ) + if (abort_out_en == 1) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib]; + + + assign init_b_t = init_b_in & i_init_b_cmd_t; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + assign iprog_b_0 = iprog_b[0]; + assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1; + assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1; + assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1; + + assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0; + + assign i_init_b_cmd_0 = i_init_b_cmd[0]; + assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1; + assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1; + assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1; + + assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2 + & i_init_b_cmd_3; + + always @( rst_en or init_rst or prog_b_in or iprog_b_t ) + if (icap_on == 0) begin + if (init_rst == 1) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + end + + assign id_error_flag_t = &id_error_flag; + + always @(posedge id_error_flag_t) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en == 1) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b_t & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in !== 3'b110) begin + mode_sample_flag <= 0; + if ( icap_on == 0) + $display("Error: [Unisim %s-2] Input M is %h. Only Slave SelectMAP mode M=110 is supported. Instance %m.", MODULE_NAME, m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 && icap_on == 0) + $display("Error: [Unisim %s-3] PROGB is not high when INITB goes high at time %t. Instance %m.", MODULE_NAME, $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0) + $display("Error: [Unisim %s-4] Mode pine M[2:0] changed after rising edge of INITB at time %t. Instance %m.", MODULE_NAME, $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in == 0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog && icap_on == 0) + $display("Error: [Unisim %s-5] Low time of PROGB is less than required minimum Tprogram time %d at time %t. Instance %m.", MODULE_NAME, cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0 ) begin + buswid_flag_init <= 4'b0; + buswid_flag <= 4'b0; + buswidth_tmp[0] <= 2'b00; + buswidth_tmp[1] <= 2'b00; + buswidth_tmp[2] <= 2'b00; + buswidth_tmp[3] <= 2'b00; + end + else + if (buswid_flag[ib] == 0) begin + if (bus_en == 1 && rdwr_b_in == 0) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (buswid_flag_init[ib] == 0) begin + if (tmp_byte == 8'hBB) + buswid_flag_init[ib] <= 1; + end + else begin + if (tmp_byte == 8'h11) begin // x8 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b01; + end + else if (tmp_byte == 8'h22) begin // x16 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b10; + end + else if (tmp_byte == 8'h44) begin // x32 + buswid_flag[ib] <= 1; + buswidth_tmp[ib] <= 2'b11; + end + else begin + buswid_flag[ib] <= 0; + buswidth_tmp[ib] <= 2'b00; + buswid_flag_init[ib] <= 0; + if (icap_on == 0) + $display("Error: [Unisim %s-6] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB at time %t. Instance %m.", MODULE_NAME, $time); + else + $display("Error: [Unisim %s-7] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE3 instance at time %t. Instance %m.", MODULE_NAME, $time); + + end + end + end + end + + assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib]; + + always @(buswidth_ibtmp) + buswidth[ib] = buswidth_ibtmp; + + assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0; + + assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0; + assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0; + assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0; + assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0; + + + assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch; + assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch; + assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch; + assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch; + assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0]; + assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1]; + assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2]; + assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3]; + + always @(posedge eos_startup[0]) + if (icap_on == 1) begin + $fclose(frame_data_fd); + icap_init_done <= 1; + @(posedge cclk_in); + @(posedge cclk_in) + if (icap_init_done_dly == 0) + icap_desynch <= 1; + @(posedge cclk_in); + @(posedge cclk_in) begin + icap_desynch <= 0; + icap_init_done_dly <= 1; + end + @(posedge cclk_in); + @(posedge cclk_in); + @(posedge cclk_in); + end + else begin + icap_clr <= 0; + icap_desynch <= 0; + end + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in == 0) + rd_sw_en <= 0; + else begin + if (csi_b_in == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + assign desync_flag_t = |desync_flag; + + always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin + if (desync_flag[ib] == 1) begin + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + if (desync_flag[0] == 1 ) begin + new_data_in_flag[0] = 0; + bus_sync_flag[0] = 0; + wr_cnt[0] = 0; + wr_flag[0] = 0; + rd_flag[0] = 0; + end + if (desync_flag[1] == 1 ) begin + new_data_in_flag[1] = 0; + bus_sync_flag[1] = 0; + wr_cnt[1] = 0; + wr_flag[1] = 0; + rd_flag[1] = 0; + end + if (desync_flag[2] == 1 ) begin + new_data_in_flag[2] = 0; + bus_sync_flag[2] = 0; + wr_cnt[2] = 0; + wr_flag[2] = 0; + rd_flag[2] = 0; + end + if (desync_flag[3] == 1 ) begin + new_data_in_flag[3] = 0; + bus_sync_flag[3] = 0; + wr_cnt[3] = 0; + wr_flag[3] = 0; + rd_flag[3] = 0; + end + if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin + new_data_in_flag = 4'b0; + wr_cnt[0] = 0; + wr_cnt[1] = 0; + wr_cnt[2] = 0; + wr_cnt[3] = 0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + else begin + if (icap_clr == 1) begin + new_data_in_flag <= 4'b0; + wr_cnt[0] <= 0; + wr_cnt[1] <= 0; + wr_cnt[2] <= 0; + wr_cnt[3] <= 0; + wr_flag <= 4'b0; + rd_flag <= 4'b0; + pack_in_reg_tmp0 = 32'b0; + pack_in_reg_tmps0 = 32'b0; + end + else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin + if (rdwr_b_in == 0) begin + wr_flag[ib] <= 1; + rd_flag[ib] <= 0; + if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (bus_sync_flag[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99 + && pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 0; + end + else begin + pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16]; + pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8]; + pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0]; + pack_in_reg_tmp0[7:0] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + end + end + else begin + if (wr_cnt[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[31:24] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 1; + end + else if (wr_cnt[ib] == 1) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[23:16] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 2; + end + else if (wr_cnt[ib] == 2) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[15:8] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 3; + end + else if (wr_cnt[ib] == 3) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + pack_in_reg_tmp0[7:0] = tmp_byte; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 1; + wr_cnt[ib] <= 0; + end + end + end + else if (buswidth[ib] == 2'b10) begin + tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])}; + if (bus_sync_flag[ib] == 0) begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin + wr_cnt[ib] <= 0; + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + end + else begin + pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0]; + pack_in_reg_tmp0[15:0] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 0; + end + end + else begin + pack_in_reg_tmp0 = pack_in_reg[ib]; + if (wr_cnt[ib] == 0) begin + pack_in_reg_tmp0[31:16] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 0; + wr_cnt[ib] <= 1; + end + else if (wr_cnt[ib] == 1) begin + pack_in_reg_tmp0[15:0] = tmp_word; + pack_in_reg_tmps0 <= pack_in_reg_tmp0; + new_data_in_flag[ib] <= 1; + wr_cnt[ib] <= 0; + end + end + end + else if (buswidth[ib] == 2'b11 ) begin + tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]), + bit_revers8(d_in[7:0])}; + pack_in_reg_tmp0 <= tmp_dword; + pack_in_reg_tmps0 <= tmp_dword; + if (bus_sync_flag[ib] == 0) begin + if (tmp_dword == 32'hAA995566) begin + bus_sync_flag[ib] <= 1; + new_data_in_flag[ib] <= 0; + end + end + else begin + pack_in_reg_tmp0 <= tmp_dword; + pack_in_reg_tmps0 <= tmp_dword; + new_data_in_flag[ib] <= 1; + end + end + end + else begin + wr_flag[ib] <= 0; + new_data_in_flag[ib] <= 0; + if (rd_sw_en ==1) + rd_flag[ib] <= 1; + end + end + else begin + wr_flag[ib] <= 0; + rd_flag[ib] <= 0; + new_data_in_flag[ib] <= 0; + end + end + end + + + always @(pack_in_reg_tmps0 or desync_flag or icap_clr) + begin + if (desync_flag[0] == 1 || icap_clr == 1) + pack_in_reg[0] = 32'b0; + if (desync_flag[1] == 1 || icap_clr == 1) + pack_in_reg[1] = 32'b0; + if (desync_flag[2] == 1 || icap_clr == 1) + pack_in_reg[2] = 32'b0; + if (desync_flag[3] == 1 || icap_clr == 1) + pack_in_reg[3] = 32'b0; + + if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin + pack_in_reg[0] = pack_in_reg_tmps0; + end + else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0) + pack_in_reg[1] = pack_in_reg_tmps0; + else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0) + pack_in_reg[2] = pack_in_reg_tmps0; + else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0) + pack_in_reg[3] = pack_in_reg_tmps0; + end + + + task rst_pack_dec; + input ib_d; + begin + conti_data_flag[ib_d] <= 0; + conti_data_cnt[ib_d] <= 0; + cmd_wr_flag[ib_d] <= 0; + cmd_rd_flag[ib_d] <= 0; + id_error_flag[ib_d] <= 0; + crc_curr[ib_d] <= 32'b0; + crc_ck[ib_d] <= 0; + csbo_cnt[ib_d] <= 0; + csbo_flag[ib_d] <= 0; + downcont_cnt <= 0; + rd_data_cnt[ib_d] <= 0; + end + endtask + + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + rst_pack_dec(0); + rst_pack_dec(1); + rst_pack_dec(2); + rst_pack_dec(3); + bout_flag <= 4'b0; + bout_cnt[0] <= 0; + bout_cnt[1] <= 0; + bout_cnt[2] <= 0; + bout_cnt[3] <= 0; + end + else begin + if (icap_clr == 1) begin + rst_pack_dec(0); + rst_pack_dec(1); + rst_pack_dec(2); + rst_pack_dec(3); + bout_flag <= 4'b0; + bout_cnt[0] <= 0; + bout_cnt[1] <= 0; + bout_cnt[2] <= 0; + bout_cnt[3] <= 0; + end + if (crc_reset[ib] == 1 ) begin + crc_reg[ib] <= 32'b0; + crc_ck[ib] <= 0; + crc_curr[ib] <= 32'b0; + end + if (crc_ck[ib] == 1) begin + crc_curr[ib] <= 32'b0; + crc_ck[ib] <= 0; + end + + if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin + bout_flag[0] <= 0; + bout_cnt[0] <= 0; + rst_pack_dec(0); + end + if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin + bout_flag[1] <= 0; + bout_cnt[1] <= 0; + rst_pack_dec(1); + end + if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin + bout_flag[2] <= 0; + bout_cnt[2] <= 0; + rst_pack_dec(2); + end + if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin + bout_flag[3] <= 0; + bout_cnt[3] <= 0; + rst_pack_dec(3); + end + if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0 + && desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin + pack_in_reg_tmp = pack_in_reg[ib]; + if (conti_data_flag[ib] == 1 ) begin + reg_addr_tmp = reg_addr[ib]; + case (reg_addr_tmp) + 5'b00000 : begin + crc_reg[ib] <= pack_in_reg[ib]; + crc_reg_tmp <= pack_in_reg[ib]; + crc_ck[ib] <= 1; + end + 5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]}; + + 5'b00010 : begin + fdri_reg[ib] <= pack_in_reg[ib]; + fdri_rst_prdone_flag <= ~fdri_rst_prdone_flag; + end + 5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0]; + 5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]); + 5'b00110 : mask_reg[ib] <= pack_in_reg[ib]; + 5'b01000 : lout_reg[ib] <= pack_in_reg[ib]; + 5'b01001 : cor0_reg[ib] <= pack_in_reg[ib]; + 5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib]; + 5'b01011 : cbc_reg[ib] <= pack_in_reg[ib]; + 5'b01100 : begin + idcode_reg[ib] <= pack_in_reg[ib]; + if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag[ib] <= 1; + if (icap_on == 0) + $display("Error: [Unisim %s-8] Written value to IDCODE register is %h which does not match with DEVICE ID %h on %s at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, MODULE_NAME, $time); + else + $display("Error: [Unisim %s-9] Written value to IDCODE register is %h which does not match with DEVICE ID %h on ICAPE3 at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, $time); + end + else + id_error_flag[ib] <= 0; + end + 5'b01101 : axss_reg[ib] <= pack_in_reg[ib]; + 5'b01110 : cor1_reg[ib] <= pack_in_reg[ib]; + 5'b01111 : csob_reg[ib] <= pack_in_reg[ib]; + 5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib]; + 5'b10001 : timer_reg[ib] <= pack_in_reg[ib]; + 5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib]; + 5'b10111 : testmode_reg[ib] <= pack_in_reg[ib]; + 5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]); + 5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]}; + 5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]}; + 5'b11011 : trim_reg[ib] <= pack_in_reg[ib]; + 5'b11110 : bout_reg[ib] <= pack_in_reg[ib]; + 5'b11111 : bspi_reg[ib] <= pack_in_reg[ib]; + endcase + + if (reg_addr[ib] != 5'b00000) + crc_ck[ib] <= 0; + + if (reg_addr_tmp == 5'b00100) + cmd_reg_new_flag[ib] <= 1; + else + cmd_reg_new_flag[ib] <= 0; + + if (crc_en[ib] == 1) begin + if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111) + crc_curr[ib] = 32'b0; + else begin + if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14 + && reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin + crc_input = {reg_addr[ib], pack_in_reg_tmp}; + crc_curr_tmp = crc_curr[ib]; + crc_new = bcc_next(crc_curr_tmp, crc_input); + crc_curr[ib] <= crc_new; + end + end + end + + if (conti_data_cnt[ib] <= 1) begin + conti_data_cnt[ib] <= 0; + end + else + conti_data_cnt[ib] <= conti_data_cnt[ib] - 1; + end + else if (conti_data_flag[ib] == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en[ib] == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg[ib]}; + crc_new = bcc_next(crc_curr[ib], crc_input); + crc_curr[ib] <= crc_new; + end + if (ib == 0) begin + if (farn <= 80) + farn <= farn + 1; + else begin + far_addr <= far_addr + 1; + farn <= 0; + end + if (frame_data_wen == 1 && icap_init_done == 0) begin + rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]}; + rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input); + rbcrc_curr[ib] <= rbcrc_new; + $fwriteh(frame_data_fd, far_addr); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, pack_in_reg[ib]); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, rbcrc_new); + $fwriteh(frame_data_fd, "\n"); + end + end + end + + if (pack_in_reg_tmp[31:29] == 3'b010 ) begin + bout_cnt_tmp = bout_cnt[ib]; + if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + downcont_cnt <= pack_in_reg_tmp[26:0]; + far_addr <= far_reg[ib]; + end + else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + bout_flag[ib] <= 1; + bout_cnt[ib] <= pack_in_reg_tmp[26:0]; + end + else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + csbo_flag[ib] <= 1; + csbo_cnt[ib] <= pack_in_reg_tmp[26:0]; + end + end + else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg_tmp[10:0] != 11'b0) begin + cmd_rd_flag[ib] <= 1; + cmd_wr_flag[ib] <= 0; + rd_data_cnt[ib] <= 4; + conti_data_cnt[ib] <= 0; + conti_data_flag[ib] <= 0; + rd_reg_addr[ib] <= pack_in_reg_tmp[17:13]; + end + end + else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg + lout_reg[ib] <= pack_in_reg_tmp; + conti_data_flag[ib] = 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + cmd_wr_flag[ib] <= 1; + conti_data_cnt[ib] <= 5'b0; + end + else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg + bout_reg[ib] <= pack_in_reg_tmp; + bout_flags[ib] <= 1; + conti_data_flag[ib] = 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + cmd_wr_flag[ib] <= 1; + conti_data_cnt[ib]<= 5'b0; + end + else begin + if (pack_in_reg_tmp[10:0] != 10'b0) begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 1; + conti_data_flag[ib] <= 1; + conti_data_cnt[ib] <= pack_in_reg_tmp[10:0]; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + end + else begin + cmd_rd_flag[ib] <= 0; + cmd_wr_flag[ib] <= 1; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + reg_addr[ib] <= pack_in_reg_tmp[17:13]; + reg_addr_tmp <= pack_in_reg_tmp[17:13]; + end + end + end + else begin + cmd_wr_flag[ib] <= 0; + conti_data_flag[ib] <= 0; + conti_data_cnt[ib] <= 0; + end + end + end // if (conti_data_flag == 0 ) + if (csbo_cnt[ib] != 0 ) begin + if (csbo_flag[ib] == 1) + csbo_cnt[ib] <= csbo_cnt[ib] - 1; + end + else + csbo_flag[ib] <= 0; + + if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin + if (bout_cnt[0] == 1) begin + bout_cnt[0] <= 0; + bout_flag[0] <= 0; + end + else + bout_cnt[0] <= bout_cnt[0] - 1; + end + + if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin + if (bout_cnt[1] == 1) begin + bout_cnt[1] <= 0; + bout_flag[1] <= 0; + end + else + bout_cnt[1] <= bout_cnt[1] - 1; + end + + if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin + bout_cnt[2] <= bout_cnt[2] - 1; + if (bout_cnt[2] == 1) begin + bout_cnt[2] <= 0; + bout_flag[2] <= 0; + end + else + bout_cnt[2] <= bout_cnt[2] - 1; + end + + if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin + if (bout_cnt[3] == 1) begin + bout_cnt[3] <= 0; + bout_flag[3] <= 0; + end + else + bout_cnt[3] <= bout_cnt[3] - 1; + end + + if (conti_data_cnt[ib] == 5'b00001 ) + conti_data_flag[ib] <= 0; + + if (crc_ck[ib] == 1 || icap_init_done == 1) + crc_ck[ib] <= 0; + end + + if (rw_en[ib] == 1 && csi_b_ins == 0) begin + if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1) + rd_data_cnt[ib] <= 0; + else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin + cmd_rd_flag[ib] <= 0; + end + else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1) + rd_data_cnt[ib] <= rd_data_cnt[ib] - 1; + + if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1) + downcont_cnt <= downcont_cnt - 1; + end + + + if (cmd_reg_new_flag[ib] == 1 ) + cmd_reg_new_flag[ib] <= 0; + + end + + + always @(bout_flag) + if (bout_flag[3] == 1) begin + ib = 3; + ib_skp = 1; + end + else if (bout_flag[2] == 1) begin + ib = 3; + ib_skp = 0; + end + else if (bout_flag[1] == 1) begin + ib = 2; + ib_skp = 0; + end + else if (bout_flag[0] == 1) begin + ib = 1; + ib_skp = 0; + end + else begin + ib = 0; + ib_skp = 0; + end + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + outbus <= 32'b0; + end + else begin + if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr[ib]) + 5'b00000 : if (buswidth[ib] == 2'b01) + rdbk_byte(crc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(crc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]); + 5'b00001 : if (buswidth[ib] == 2'b01) + rdbk_byte(far_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(far_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(far_reg[ib], rd_data_cnt[ib]); + 5'b00011 : if (buswidth[ib] == 2'b01) + rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]); + 5'b00100 : if (buswidth[ib] == 2'b01) + rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]); + 5'b00101 : if (buswidth[ib] == 2'b01) + rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]); + 5'b00110 : if (buswidth[ib] == 2'b01) + rdbk_byte(mask_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(mask_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]); + 5'b00111 : if (buswidth[ib] == 2'b01) + rdbk_byte(stat_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(stat_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]); + 5'b01001 : if (buswidth[ib] == 2'b01) + rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]); + 5'b01100 : if (buswidth[ib] == 2'b01) + rdbk_byte(DEVICE_ID, rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(DEVICE_ID, rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]); + 5'b01101 : if (buswidth[ib] == 2'b01) + rdbk_byte(axss_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(axss_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]); + 5'b01110 : if (buswidth[ib] == 2'b01) + rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]); + 5'b10000 : if (buswidth[ib] == 2'b01) + rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]); + 5'b10001 : if (buswidth[ib] == 2'b01) + rdbk_byte(timer_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(timer_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]); + 5'b10010 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]); + 5'b10011 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]); + 5'b10100 : if (buswidth[ib] == 2'b01) + rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]); + 5'b10101 : if (buswidth[ib] == 2'b01) + rdbk_byte(efar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(efar_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]); + 5'b10110 : if (buswidth[ib] == 2'b01) + rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]); + 5'b11000 : if (buswidth[ib] == 2'b01) + rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]); + 5'b11001 : if (buswidth[ib] == 2'b01) + rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]); + 5'b11010 : if (buswidth[ib] == 2'b01) + rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]); + 5'b11011 : if (buswidth[ib] == 2'b01) + rdbk_byte(trim_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(trim_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]); + 5'b11111 : if (buswidth[ib] == 2'b01) + rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b10) + rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]); + else if (buswidth[ib] == 2'b11) + rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]); + endcase + if (ib != 0) begin + if (rd_data_cnt[ib] == 1) + rd_desynch_tmp <= 1; + end + end + else begin + outbus <= 32'b0; + rd_desynch <= rd_desynch_tmp; + rd_desynch_tmp <= 0; + end + end + + assign crc_rst[0] = crc_reset[0] | ~rst_intl; + assign crc_rst[1] = crc_reset[1] | ~rst_intl; + assign crc_rst[2] = crc_reset[2] | ~rst_intl; + assign crc_rst[3] = crc_reset[3] | ~rst_intl; + + assign crc_curr_cktmp = crc_curr[0]; + assign crc_reg_cktmp = crc_reg[0]; + + + + always @(posedge cclk_in or posedge crc_rst[0] ) + if (crc_rst[0] == 1) begin + crc_err_flag[0] <= 0; + crc_ck_en[0] <= 1; + end + else + if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin + if (crc_curr[0] != crc_reg[0]) + crc_err_flag[0] <= 1; + else + crc_err_flag[0] <= 0; + + crc_ck_en[0] <= 0; + end + else begin + crc_err_flag[0] <= 0; + crc_ck_en[0] <= 1; + end + + always @(posedge cclk_in or posedge crc_rst[1] ) + if (crc_rst[1] == 1) begin + crc_err_flag[1] <= 0; + crc_ck_en[1] <= 1; + end + else + if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin + if (crc_curr[1] != crc_reg[1]) + crc_err_flag[1] <= 1; + else + crc_err_flag[1] <= 0; + + crc_ck_en[1] <= 0; + end + else begin + crc_err_flag[1] <= 0; + crc_ck_en[1] <= 1; + + end + + always @(posedge cclk_in or posedge crc_rst[2] ) + if (crc_rst[2] == 1) begin + crc_err_flag[2] <= 0; + crc_ck_en[2] <= 1; + end + else + if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin + if (crc_curr[2] != crc_reg[2]) + crc_err_flag[2] <= 1; + else + crc_err_flag[2] <= 0; + + crc_ck_en[2] <= 0; + end + else begin + crc_err_flag[2] <= 0; + crc_ck_en[2] <= 1; + end + + always @(posedge cclk_in or posedge crc_rst[3] ) + if (crc_rst[3] == 1) begin + crc_err_flag[3] <= 0; + crc_ck_en[3] <= 1; + end + else + if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin + if (crc_curr[3] != crc_reg[3]) + crc_err_flag[3] <= 1; + else + crc_err_flag[3] <= 0; + + crc_ck_en[3] <= 0; + end + else begin + crc_err_flag[3] <= 0; + crc_ck_en[3] <= 1; + end + + always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0]) + if (rst_intl == 0) + crc_err_flag_reg[0] <= 0; + else if (crc_err_flag[0] == 1) + crc_err_flag_reg[0] <= 1; + else + crc_err_flag_reg[0] <= 0; + + always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1]) + if (rst_intl == 0) + crc_err_flag_reg[1] <= 0; + else if (crc_err_flag[1] == 1) + crc_err_flag_reg[1] <= 1; + else + crc_err_flag_reg[1] <= 0; + + always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2]) + if (rst_intl == 0) + crc_err_flag_reg[2] <= 0; + else if (crc_err_flag[2] == 1) + crc_err_flag_reg[2] <= 1; + else + crc_err_flag_reg[2] <= 0; + + always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3]) + if (rst_intl == 0) + crc_err_flag_reg[3] <= 0; + else if (crc_err_flag[3] == 1) + crc_err_flag_reg[3] <= 1; + else + crc_err_flag_reg[3] <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + startup_set <= 4'b0; + crc_reset <= 4'b0; + gsr_cmd_out <= 4'b0; + shutdown_set <= 4'b0; + desynch_set <= 4'b0; + ghigh_b <= 4'b0; + end + else + for (ci = 0; ci <=3; ci = ci+1) begin + if (cmd_reg_new_flag[ci] == 1) begin + if (cmd_reg[ci] == 5'b00011) + ghigh_b[ci] <= 1; + else if (cmd_reg[ci] == 5'b01000) + ghigh_b[ci] <= 0; + + if (cmd_reg[ci] == 5'b00101) + startup_set[ci] <= 1; + else + startup_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b00111) + crc_reset[ci] <= 1; + else + crc_reset[ci] <= 0; + + if (cmd_reg[ci] == 5'b01010) + gsr_cmd_out[ci] <= 1; + else + gsr_cmd_out[ci] <= 0; + + if (cmd_reg[ci] == 5'b01011) + shutdown_set[ci] <= 1; + else + shutdown_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b01101) + desynch_set[ci] <= 1; + else + desynch_set[ci] <= 0; + + if (cmd_reg[ci] == 5'b01111) begin + iprog_b[ci] <= 0; + i_init_b_cmd[ci] <= 0; + iprog_b[ci] <= #cfg_Tprog 1; + i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set[ci] <= 0; + crc_reset[ci] <= 0; + gsr_cmd_out[ci] <= 0; + shutdown_set[ci] <= 0; + desynch_set[ci] <= 0; + end + end + + always @(posedge startup_set[0] or posedge desynch_set[0] or posedge rw_en[0] ) + if (rw_en[0] == 1 || desynch_set[0] == 1) + begin + if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin + if (icap_on == 0) + startup_set_pulse0 <= 2'b01; + else begin + startup_set_pulse0 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse0 <= 2'b00; + end + end + else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin + startup_set_pulse0 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse0 <= 2'b00; + end + end + + always @(posedge startup_set[1] or posedge desynch_set[1] or posedge rw_en[1] ) + if (rw_en[1] == 1 || desynch_set[1] == 1) + begin + if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin + if (icap_on == 0) + startup_set_pulse1 <= 2'b01; + else begin + startup_set_pulse1 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse1 <= 2'b00; + end + end + else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin + startup_set_pulse1 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse1 <= 2'b00; + end + end + + always @(posedge startup_set[2] or posedge desynch_set[2] or posedge rw_en[2]) + if (rw_en[2] == 1 || desynch_set[2] == 1) + begin + if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin + if (icap_on == 0) + startup_set_pulse2 <= 2'b01; + else begin + startup_set_pulse2 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse2 <= 2'b00; + end + end + else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin + startup_set_pulse2 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse2 <= 2'b00; + end + end + + always @(posedge startup_set[3] or posedge desynch_set[3] or posedge rw_en[3]) + if (rw_en[3] == 1 || desynch_set[3] == 1) + begin + if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin + if (icap_on == 0) + startup_set_pulse3 <= 2'b01; + else begin + startup_set_pulse3 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse3 <= 2'b00; + end + end + else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin + startup_set_pulse3 <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse3 <= 2'b00; + end + end + + always @(posedge gsr_cmd_out[0] or negedge rw_en[0]) + if (rw_en[0] == 0) + gsr_cmd_out_pulse[0] <= 0; + else + begin + gsr_cmd_out_pulse[0] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[0] <= 0; + end + + always @(posedge gsr_cmd_out[1] or negedge rw_en[1]) + if (rw_en[1] == 0) + gsr_cmd_out_pulse[1] <= 0; + else + begin + gsr_cmd_out_pulse[1] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[1] <= 0; + end + + always @(posedge gsr_cmd_out[2] or negedge rw_en[2]) + if (rw_en[2] == 0) + gsr_cmd_out_pulse[2] <= 0; + else + begin + gsr_cmd_out_pulse[2] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[2] <= 0; + end + + always @(posedge gsr_cmd_out[3] or negedge rw_en[3]) + if (rw_en[3] == 0) + gsr_cmd_out_pulse[3] <= 0; + else + begin + gsr_cmd_out_pulse[3] <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse[3] <= 0; + end + + reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3; + + always @(ctl0_reg[0]) begin + ctl0_reg_tmp0 = ctl0_reg[0]; + if (ctl0_reg_tmp0[9] == 1) + abort_dis[0] = 1; + else + abort_dis[0] = 0; + if (ctl0_reg_tmp0[3] == 1) + persist_en[0] = 1; + else + persist_en[0] = 0; + if (ctl0_reg_tmp0[0] == 1) + gts_usr_b[0] = 1; + else + gts_usr_b[0] = 0; + end + + always @(ctl0_reg[1]) begin + ctl0_reg_tmp1 = ctl0_reg[1]; + if (ctl0_reg_tmp1[9] == 1) + abort_dis[1] = 1; + else + abort_dis[1] = 0; + if (ctl0_reg_tmp1[3] == 1) + persist_en[1] = 1; + else + persist_en[1] = 0; + if (ctl0_reg_tmp1[0] == 1) + gts_usr_b[1] = 1; + else + gts_usr_b[1] = 0; + end + + always @(ctl0_reg[2]) begin + ctl0_reg_tmp2 = ctl0_reg[2]; + if (ctl0_reg_tmp2[9] == 1) + abort_dis[2] = 1; + else + abort_dis[2] = 0; + if (ctl0_reg_tmp2[3] == 1) + persist_en[2] = 1; + else + persist_en[2] = 0; + if (ctl0_reg_tmp0[2] == 1) + gts_usr_b[2] = 1; + else + gts_usr_b[2] = 0; + end + + always @(ctl0_reg[3]) begin + ctl0_reg_tmp3 = ctl0_reg[3]; + if (ctl0_reg_tmp3[9] == 1) + abort_dis[3] = 1; + else + abort_dis[3] = 0; + if (ctl0_reg_tmp3[3] == 1) + persist_en[3] = 1; + else + persist_en[3] = 0; + if (ctl0_reg_tmp3[0] == 1) + gts_usr_b[3] = 1; + else + gts_usr_b[3] = 0; + end + + always @(cor0_reg[0]) + begin + cor0_reg_tmp0 = cor0_reg[0]; + done_cycle_reg0 = cor0_reg_tmp0[14:12]; + lock_cycle_reg0 = cor0_reg_tmp0[8:6]; + gts_cycle_reg0 = cor0_reg_tmp0[5:3]; + gwe_cycle_reg0 = cor0_reg_tmp0[2:0]; + + if (cor0_reg_tmp0[24] == 1'b1) + done_pin_drv[0] = 1; + else + done_pin_drv[0] = 0; + + if (cor0_reg_tmp0[28] == 1'b1) + crc_bypass[0] = 1; + else + crc_bypass[0] = 0; + end + + always @(cor0_reg[1]) + begin + cor0_reg_tmp1 = cor0_reg[1]; + done_cycle_reg1 = cor0_reg_tmp1[14:12]; + lock_cycle_reg1 = cor0_reg_tmp1[8:6]; + gts_cycle_reg1 = cor0_reg_tmp1[5:3]; + gwe_cycle_reg1 = cor0_reg_tmp1[2:0]; + + if (cor0_reg_tmp1[24] == 1'b1) + done_pin_drv[1] = 1; + else + done_pin_drv[1] = 0; + + if (cor0_reg_tmp1[28] == 1'b1) + crc_bypass[1] = 1; + else + crc_bypass[1] = 0; + end + + always @(cor0_reg[2]) + begin + cor0_reg_tmp2 = cor0_reg[2]; + done_cycle_reg2 = cor0_reg_tmp2[14:12]; + lock_cycle_reg2 = cor0_reg_tmp2[8:6]; + gts_cycle_reg2 = cor0_reg_tmp2[5:3]; + gwe_cycle_reg2 = cor0_reg_tmp2[2:0]; + + if (cor0_reg_tmp2[24] == 1'b1) + done_pin_drv[2] = 1; + else + done_pin_drv[2] = 0; + + if (cor0_reg_tmp2[28] == 1'b1) + crc_bypass[2] = 1; + else + crc_bypass[2] = 0; + end + + always @(cor0_reg[3]) + begin + cor0_reg_tmp3 = cor0_reg[3]; + done_cycle_reg3 = cor0_reg_tmp3[14:12]; + lock_cycle_reg3 = cor0_reg_tmp3[8:6]; + gts_cycle_reg3 = cor0_reg_tmp3[5:3]; + gwe_cycle_reg3 = cor0_reg_tmp3[2:0]; + + if (cor0_reg_tmp3[24] == 1'b1) + done_pin_drv[3] = 1; + else + done_pin_drv[3] = 0; + + if (cor0_reg_tmp3[28] == 1'b1) + crc_bypass[3] = 1; + else + crc_bypass[3] = 0; + end + + always @(cor1_reg[0]) begin + cor1_reg_tmp0 = cor1_reg[0]; + rbcrc_no_pin[0] = cor1_reg_tmp0[8]; + end + + always @(cor1_reg[1]) begin + cor1_reg_tmp1 = cor1_reg[1]; + rbcrc_no_pin[1] = cor1_reg_tmp1[8]; + end + + always @(cor1_reg[2]) begin + cor1_reg_tmp2 = cor1_reg[2]; + rbcrc_no_pin[2] = cor1_reg_tmp2[8]; + end + + always @(cor1_reg[3]) begin + cor1_reg_tmp3 = cor1_reg[3]; + rbcrc_no_pin[3] = cor1_reg_tmp3[8]; + end + + assign stat_reg_tmp0[31:27] = 5'b00000; + assign stat_reg_tmp1[31:27] = 5'b00000; + assign stat_reg_tmp2[31:27] = 5'b00000; + assign stat_reg_tmp3[31:27] = 5'b00000; + assign stat_reg_tmp0[24:21] = 4'bxxx0; + assign stat_reg_tmp1[24:21] = 4'bxxx0; + assign stat_reg_tmp2[24:21] = 4'bxxx0; + assign stat_reg_tmp3[24:21] = 4'bxxx0; + assign stat_reg_tmp0[17:16] = 2'b0; + assign stat_reg_tmp1[17:16] = 2'b0; + assign stat_reg_tmp2[17:16] = 2'b0; + assign stat_reg_tmp3[17:16] = 2'b0; + assign stat_reg_tmp0[14] = DONE; + assign stat_reg_tmp1[14] = DONE; + assign stat_reg_tmp2[14] = DONE; + assign stat_reg_tmp3[14] = DONE; + assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0; + assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0; + assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0; + assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0; + assign stat_reg_tmp0[12] = INITB; + assign stat_reg_tmp1[12] = INITB; + assign stat_reg_tmp2[12] = INITB; + assign stat_reg_tmp3[12] = INITB; + assign stat_reg_tmp0[11] = mode_sample_flag; + assign stat_reg_tmp1[11] = mode_sample_flag; + assign stat_reg_tmp2[11] = mode_sample_flag; + assign stat_reg_tmp3[11] = mode_sample_flag; + assign stat_reg_tmp0[10:8] = mode_pin_in; + assign stat_reg_tmp1[10:8] = mode_pin_in; + assign stat_reg_tmp2[10:8] = mode_pin_in; + assign stat_reg_tmp3[10:8] = mode_pin_in; + assign stat_reg_tmp0[3] = 1'b1; + assign stat_reg_tmp1[3] = 1'b1; + assign stat_reg_tmp2[3] = 1'b1; + assign stat_reg_tmp3[3] = 1'b1; + assign stat_reg_tmp0[2] = pll_locked; + assign stat_reg_tmp1[2] = pll_locked; + assign stat_reg_tmp2[2] = pll_locked; + assign stat_reg_tmp3[2] = pll_locked; + assign stat_reg_tmp0[1] = 1'b0; + assign stat_reg_tmp1[1] = 1'b0; + assign stat_reg_tmp2[1] = 1'b0; + assign stat_reg_tmp3[1] = 1'b0; + + assign stat_reg_tmp0[26:25] = buswidth[0]; + assign stat_reg_tmp0[20:18] = st_state0; + assign stat_reg_tmp0[15] = id_error_flag[0]; + assign stat_reg_tmp0[7] = ghigh_b[0]; + assign stat_reg_tmp0[6] = gwe_out[0]; + assign stat_reg_tmp0[5] = gts_cfg_b[0]; + assign stat_reg_tmp0[4] = eos_startup[0]; + assign stat_reg_tmp0[0] = crc_err_flag_reg[0]; + + assign stat_reg_tmp1[26:25] = buswidth[1]; + assign stat_reg_tmp1[20:18] = st_state1; + assign stat_reg_tmp1[15] = id_error_flag[1]; + assign stat_reg_tmp1[7] = ghigh_b[1]; + assign stat_reg_tmp1[6] = gwe_out[1]; + assign stat_reg_tmp1[5] = gts_cfg_b[1]; + assign stat_reg_tmp1[4] = eos_startup[1]; + assign stat_reg_tmp1[0] = crc_err_flag_reg[1]; + + assign stat_reg_tmp2[26:25] = buswidth[2]; + assign stat_reg_tmp2[20:18] = st_state2; + assign stat_reg_tmp2[15] = id_error_flag[2]; + assign stat_reg_tmp2[7] = ghigh_b[2]; + assign stat_reg_tmp2[6] = gwe_out[2]; + assign stat_reg_tmp2[5] = gts_cfg_b[2]; + assign stat_reg_tmp2[4] = eos_startup[2]; + assign stat_reg_tmp2[0] = crc_err_flag_reg[2]; + + assign stat_reg_tmp3[26:25] = buswidth[3]; + assign stat_reg_tmp3[20:18] = st_state3; + assign stat_reg_tmp3[15] = id_error_flag[3]; + assign stat_reg_tmp3[7] = ghigh_b[3]; + assign stat_reg_tmp3[6] = gwe_out[3]; + assign stat_reg_tmp3[5] = gts_cfg_b[3]; + assign stat_reg_tmp3[4] = eos_startup[3]; + assign stat_reg_tmp3[0] = crc_err_flag_reg[3]; + + assign stat_reg[0] = stat_reg_tmp0; + assign stat_reg[1] = stat_reg_tmp1; + assign stat_reg[2] = stat_reg_tmp2; + assign stat_reg[3] = stat_reg_tmp3; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state0 <= STARTUP_PH0; + st_state1 <= STARTUP_PH0; + st_state2 <= STARTUP_PH0; + st_state3 <= STARTUP_PH0; + startup_begin_flag0 <= 0; + startup_begin_flag1 <= 0; + startup_begin_flag2 <= 0; + startup_begin_flag3 <= 0; + startup_end_flag0 <= 0; + startup_end_flag1 <= 0; + startup_end_flag2 <= 0; + startup_end_flag3 <= 0; + end + else begin + st_state0i = st_state0; + cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0, + st_state0i, nx_st_state0,lock_cycle_reg0); + + st_state1i = st_state1; + cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1, + st_state1i, nx_st_state1,lock_cycle_reg1); + + st_state2i = st_state2; + cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2, + st_state2i, nx_st_state2,lock_cycle_reg2); + + st_state3i = st_state3; + cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3, + st_state3i, nx_st_state3,lock_cycle_reg3); + end + + task cur_st_tsk; + output stup_bflag; + output stup_eflag; + output [2:0] cst_o; + input [2:0] cst_in; + input [2:0] nst_in; + input [2:0] lock_cycle_in; + begin + if (nst_in == STARTUP_PH1) begin + stup_bflag = 1; + stup_eflag = 0; + end + else if (cst_in == STARTUP_PH7) begin + stup_eflag = 1; + stup_bflag = 0; + end + if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin + cst_o = nst_in; + end + else + cst_o = cst_in; + end + endtask + + always @(st_state0 or startup_set_pulse0 or DONE ) begin + nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0); + end + + always @(st_state1 or startup_set_pulse1 or DONE ) begin + nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1); + end + + always @(st_state2 or startup_set_pulse2 or DONE ) begin + nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2); + end + + always @(st_state3 or startup_set_pulse3 or DONE ) begin + nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3); + end + + task nx_st_tsk; + output [2:0] nx_st; + input [2:0] cur_st; + input [1:0] stup_pulse; + input [2:0] done_cycle_in; + begin + if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in)) + case (cur_st) + STARTUP_PH0 : if (stup_pulse == 2'b11 ) + nx_st = STARTUP_PH1; + else + nx_st = STARTUP_PH0; + STARTUP_PH1 : nx_st = STARTUP_PH2; + + STARTUP_PH2 : nx_st = STARTUP_PH3; + + STARTUP_PH3 : nx_st = STARTUP_PH4; + + STARTUP_PH4 : nx_st = STARTUP_PH5; + + STARTUP_PH5 : nx_st = STARTUP_PH6; + + STARTUP_PH6 : nx_st = STARTUP_PH7; + + STARTUP_PH7 : nx_st = STARTUP_PH0; + endcase + end + endtask + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 4'b0; + gts_out <= 4'b1111; + eos_startup <= 4'b0; + gsr_st_out <= 4'b1111; + done_o <= 4'b0; + end + else begin + if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin + if (DONE !== 0 || done_pin_drv[0] === 1) + done_o[0] <= 1'b1; + else + done_o[0] <= 1'bz; + end + + if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin + if (DONE !== 0 || done_pin_drv[1] == 1) + done_o[1] <= 1'b1; + else + done_o[1] <= 1'bz; + end + + if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin + if (DONE !== 0 || done_pin_drv[2] == 1) + done_o[2] <= 1'b1; + else + done_o[2] <= 1'bz; + end + + if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin + if (DONE !== 0 || done_pin_drv[3] == 1) + done_o[3] <= 1'b1; + else + done_o[3] <= 1'bz; + end + + if (st_state0 == gwe_cycle_reg0) + gwe_out[0] <= 1; + if (st_state1 == gwe_cycle_reg1) + gwe_out[1] <= 1; + if (st_state2 == gwe_cycle_reg2) + gwe_out[2] <= 1; + if (st_state3 == gwe_cycle_reg3) + gwe_out[3] <= 1; + + if (st_state0 == gts_cycle_reg0 ) + gts_out[0] <= 0; + if (st_state1 == gts_cycle_reg1 ) + gts_out[1] <= 0; + if (st_state2 == gts_cycle_reg2 ) + gts_out[2] <= 0; + if (st_state3 == gts_cycle_reg3 ) + gts_out[3] <= 0; + + if (st_state0 == STARTUP_PH6 ) + gsr_st_out[0] <= 0; + if (st_state1 == STARTUP_PH6 ) + gsr_st_out[1] <= 0; + if (st_state2 == STARTUP_PH6 ) + gsr_st_out[2] <= 0; + if (st_state3 == STARTUP_PH6 ) + gsr_st_out[3] <= 0; + + if (st_state0 == STARTUP_PH7 ) + eos_startup[0] <= 1; + if (st_state1 == STARTUP_PH7 ) + eos_startup[1] <= 1; + if (st_state2 == STARTUP_PH7 ) + eos_startup[2] <= 1; + if (st_state3 == STARTUP_PH7 ) + eos_startup[3] <= 1; + end + + assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0]; + assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1]; + assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2]; + assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3]; + + assign abort_dis_bi = abort_dis[ib]; + + always @(posedge cclk_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin + abort_flag[ib] <= 0; + checka_en <= 0; + rdwr_b_in1 <= rdwr_b_in; + end + else begin + if ( abort_dis_bi == 0 && csi_b_in == 0) begin + if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin + abort_flag[ib] <= 1; + if (icap_on == 0) + $display("Warning: [Unisim %s-10]Warning : RDWRB changes when CSB low, which causes Configuration abort at time %t. Instance %m", MODULE_NAME, $time); + end + end + else + abort_flag[ib] <= 0; + + rdwr_b_in1 <= rdwr_b_in; + checka_en <= 1; + end + + always @(posedge abort_flag[ib]) + begin + abort_out_en <= 1; + abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) begin + abort_out_en <= 0; + abort_flag_rst <= 1; + end + @(posedge cclk_in) + abort_flag_rst <= 0; + end + + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + +task rdbk_byte; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + outbus[31:8] <= 24'b0; + if (rd_dcnt==1) + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + else if (rd_dcnt==2) + outbus[7:0] <= bit_revers8(rdbk_reg[15:8]); + else if (rd_dcnt==3) + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + else if (rd_dcnt==4) + outbus[7:0] <= bit_revers8(rdbk_reg[31:24]); + end +endtask + +task rdbk_wd; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + outbus[31:16] <= 16'b0; + if (rd_dcnt==1) + outbus[15:0] <= 16'b0; + else if (rd_dcnt==2) + outbus[15:0] <= 16'b0; + else if (rd_dcnt==3) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + end + else if (rd_dcnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + outbus[15:8] <= bit_revers8(rdbk_reg[31:24]); + end + end +endtask + +task rdbk_2wd; + input [31:0] rdbk_reg; + input integer rd_dcnt; + begin + if (rd_dcnt==1) + outbus <= 32'b0; + else if (rd_dcnt==2) + outbus <= 32'b0; + else if (rd_dcnt==3) + outbus <= 32'b0; + else if (rd_dcnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + outbus[23:16] <= bit_revers8(rdbk_reg[23:16]); + outbus[31:24] <= bit_revers8(rdbk_reg[31:24]); + end + end +endtask + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SRL16E.v b/verilog/src/unisims/SRL16E.v new file mode 100644 index 0000000..d84c613 --- /dev/null +++ b/verilog/src/unisims/SRL16E.v @@ -0,0 +1,162 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Clock Enable +// /___/ /\ Filename : SRL16E.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 05/07/08 - 468872 - Add negative setup/hold support +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 04/16/13 - 683925 - add invertible pin support. +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module SRL16E #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [15:0] INIT = 16'h0000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output Q, + + input A0, + input A1, + input A2, + input A3, + input CE, + input CLK, + input D +); + +`ifdef XIL_TIMING + wire CE_dly; + wire CLK_dly; + wire D_dly; +`endif + + reg [15:0] data = INIT; + reg first_time = 1'b1; + + initial + begin + assign data = INIT; + first_time <= #100000 1'b0; +`ifdef XIL_TIMING + while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`else + while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`endif + deassign data; + end + +`ifdef XIL_TIMING +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin // rv 1 + data[15:0] <= {data[14:0], D_dly}; + end + end +end else begin : generate_block1 + always @(negedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D_dly}; + end + end +end +endgenerate +`else +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D}; + end + end +end else begin : generate_block1 + always @(negedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D}; + end + end +end +endgenerate +`endif + + assign Q = data[{A3, A2, A1, A0}]; + +`ifdef XIL_TIMING + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_ce_clk_en_p; + wire sh_ce_clk_en_n; + + always @(notifier) + data[0] = 1'bx; + + assign sh_clk_en_p = ~IS_CLK_INVERTED; + assign sh_clk_en_n = IS_CLK_INVERTED; + assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED; + assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED; +`endif + + specify + (A0 => Q) = (0:0:0, 0:0:0); + (A1 => Q) = (0:0:0, 0:0:0); + (A2 => Q) = (0:0:0, 0:0:0); + (A3 => Q) = (0:0:0, 0:0:0); + (CLK => Q) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SRLC16E.v b/verilog/src/unisims/SRLC16E.v new file mode 100644 index 0000000..3ba735b --- /dev/null +++ b/verilog/src/unisims/SRLC16E.v @@ -0,0 +1,165 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC16E.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC paramter; +// 05/07/08 - 468872 - Add negative setup/hold support +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 04/16/13 - 683925 - add invertible pin support. +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module SRLC16E #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [15:0] INIT = 16'h0000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output Q, + output Q15, + + input A0, + input A1, + input A2, + input A3, + input CE, + input CLK, + input D +); + +`ifdef XIL_TIMING + wire CE_dly; + wire CLK_dly; + wire D_dly; +`endif + + reg [15:0] data = INIT; + reg first_time = 1'b1; + + initial + begin + assign data = INIT; + first_time <= #100000 1'b0; +`ifdef XIL_TIMING + while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`else + while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`endif + deassign data; + end + +`ifdef XIL_TIMING +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D_dly}; + end + end +end else begin : generate_block1 + always @(negedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D_dly}; + end + end +end +endgenerate +`else +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D}; + end + end +end else begin : generate_block1 + always @(negedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin //rv 1 + data[15:0] <= {data[14:0], D}; + end + end +end +endgenerate +`endif + + assign Q = data[{A3, A2, A1, A0}]; + assign Q15 = data[15]; + +`ifdef XIL_TIMING + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_ce_clk_en_p; + wire sh_ce_clk_en_n; + + always @(notifier) + data[0] = 1'bx; + + assign sh_clk_en_p = ~IS_CLK_INVERTED; + assign sh_clk_en_n = IS_CLK_INVERTED; + assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED; + assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED; +`endif + + specify + (A0 => Q) = (0:0:0, 0:0:0); + (A1 => Q) = (0:0:0, 0:0:0); + (A2 => Q) = (0:0:0, 0:0:0); + (A3 => Q) = (0:0:0, 0:0:0); + (CLK => Q) = (100:100:100, 100:100:100); + (CLK => Q15) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SRLC32E.v b/verilog/src/unisims/SRLC32E.v new file mode 100644 index 0000000..be5660b --- /dev/null +++ b/verilog/src/unisims/SRLC32E.v @@ -0,0 +1,164 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 32-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC32E.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision +// 03/15/05 - Initial version. +// 01/07/06 - 222733 - Add LOC parameter +// 01/18/06 - 224341 - Add timing path for A1, A2, A3, A4 +// 05/07/08 - 468872 - Add negative setup/hold support +// 12/13/11 - 524859 - Added `celldefine and `endcelldefine +// 04/16/13 - 683925 - add invertible pin support. +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps + +`celldefine + +module SRLC32E #( + `ifdef XIL_TIMING + parameter LOC = "UNPLACED", + `endif + parameter [31:0] INIT = 32'h00000000, + parameter [0:0] IS_CLK_INVERTED = 1'b0 +)( + output Q, + output Q31, + + input [4:0] A, + input CE, + input CLK, + input D +); + +`ifdef XIL_TIMING + wire CE_dly; + wire CLK_dly; + wire D_dly; +`endif + + reg [31:0] data = INIT; + reg first_time = 1'b1; + + initial + begin + assign data = INIT; + first_time <= #100000 1'b0; +`ifdef XIL_TIMING + while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`else + while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) || + ((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) && + (first_time == 1'b1)) #1000; +`endif + deassign data; + end + +`ifdef XIL_TIMING +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin // rv 1 + data[31:0] <= {data[30:0], D_dly}; + end + end +end else begin : generate_block1 + always @(negedge CLK_dly) begin + if (CE_dly == 1'b1 || CE_dly === 1'bz) begin //rv 1 + data[31:0] <= {data[30:0], D_dly}; + end + end +end +endgenerate +`else +generate +if (IS_CLK_INVERTED == 1'b0) begin : generate_block1 + always @(posedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin //rv 1 + data[31:0] <= {data[30:0], D}; + end + end +end else begin : generate_block1 + always @(negedge CLK) begin + if (CE == 1'b1 || CE === 1'bz) begin // rv 1 + data[31:0] <= {data[30:0], D}; + end + end +end +endgenerate +`endif + + assign Q = data[A]; + assign Q31 = data[31]; + +`ifdef XIL_TIMING + + reg notifier; + + wire sh_clk_en_p; + wire sh_clk_en_n; + wire sh_ce_clk_en_p; + wire sh_ce_clk_en_n; + + always @(notifier) + data[0] = 1'bx; + + assign sh_clk_en_p = ~IS_CLK_INVERTED; + assign sh_clk_en_n = IS_CLK_INVERTED; + assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED; + assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED; +`endif + + specify + (A[0] => Q) = (0:0:0, 0:0:0); + (A[1] => Q) = (0:0:0, 0:0:0); + (A[2] => Q) = (0:0:0, 0:0:0); + (A[3] => Q) = (0:0:0, 0:0:0); + (A[4] => Q) = (0:0:0, 0:0:0); + (CLK => Q) = (100:100:100, 100:100:100); + (CLK => Q31) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly); + $setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly); + $setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/STARTUPE2.v b/verilog/src/unisims/STARTUPE2.v new file mode 100644 index 0000000..4b51a0f --- /dev/null +++ b/verilog/src/unisims/STARTUPE2.v @@ -0,0 +1,179 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls +// /___/ /\ Filename : STARTUPE2.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 03/08/10 - Initial version. +// 10/26/10 - CR 573665 -- Added PREQ support. +// 01/26/11 - CR 591438 -- Added SIM_CCLK_FREQ +// 06/16/11 - CR 610112 -- SIM_CCLK_FREQ attribute check fix +// 08/23/11 - CR 608084 -- Passed USRCCLKO to glbl.CCLKO +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 08/23/12 - Fixed GSR (CR 673651). +// 02/06/14 - Fixed tristate of USRCCLKTS (CR 766066). +// 05/27/14 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module STARTUPE2 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter PROG_USR = "FALSE", + parameter real SIM_CCLK_FREQ = 0.0 +)( + output CFGCLK, + output CFGMCLK, + output EOS, + output PREQ, + + input CLK, + input GSR, + input GTS, + input KEYCLEARB, + input PACK, + input USRCCLKO, + input USRCCLKTS, + input USRDONEO, + input USRDONETS +); + + reg SIM_CCLK_FREQ_BINARY; + reg [2:0] PROG_USR_BINARY; + + time CFGMCLK_PERIOD = 15384; + reg cfgmclk_out; + localparam MODULE_NAME = "STARTUPE2"; + + assign (strong1,weak0) glbl.GSR = GSR; + assign (strong1,weak0) glbl.GTS = GTS; + + wire start_count; + integer edge_count; + reg preq_deassert; + reg PREQ_out; + wire EOS_out; + +// Counters and Flags + reg [2:0] edge_count_cclko; + reg [2:0] cclko_wait_count; + reg start_glbl_cclko; + + initial begin + case (PROG_USR) + "FALSE" : PROG_USR_BINARY = 3'b000; + "TRUE" : PROG_USR_BINARY = 3'b111; + default : begin + $display("Error: [Unisim %s-101] PROG_USR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PROG_USR); + #1 $finish; + end + endcase + + if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0)) + SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ; + else begin + $display("Error: [Unisim %s-102] SIM_CCLK_FREQ attribute is set to %f. Legal values for this attribute are 0.0 to 10.0. Instance: %m", MODULE_NAME, SIM_CCLK_FREQ); + #1 $finish; + end + + end +//------------------------------------------------------------------------------- +//----------------- Initial ----------------------------------------------------- +//------------------------------------------------------------------------------- + initial begin + cfgmclk_out = 0; + edge_count = 0; + preq_deassert = 1'b0; + PREQ_out = 1'b0; + edge_count_cclko = 3'b000; + cclko_wait_count = 3'b010; + start_glbl_cclko = 1'b0; + forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out; + end + +//------------------------------------------------------------------------------- +//-------------------- PREQ ----------------------------------------------------- +//------------------------------------------------------------------------------- + + assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0; + + always @(posedge cfgmclk_out) begin + if(start_count) + edge_count = edge_count + 1; + else + edge_count = 0; + + if(edge_count == 35) + preq_deassert <= 1'b1; + else + preq_deassert <= 1'b0; + end + + + always @(negedge glbl.PROGB_GLBL, posedge preq_deassert) + PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert; + +//------------------------------------------------------------------------------- +//-------------------- ERROR MSG ------------------------------------------------ +//------------------------------------------------------------------------------- + always @(posedge PACK) begin + if(PREQ_out == 1'b0) + $display("Warning: [Unisim %s-1] PACK received with no associate PREQ. Instance: %m", MODULE_NAME); + end + +//------------------------------------------------------------------------------- +//--------------------- EOS ----------------------------------------------------- +//------------------------------------------------------------------------------- + + assign EOS_out = ~glbl.GSR; +//------------------------------------------------------------------------------- +//-------------------- glbl.CCLKO --------------------------------------------- +//------------------------------------------------------------------------------- + + always @(posedge USRCCLKO) begin + if(EOS_out) edge_count_cclko <= edge_count_cclko + 1; + end + + always @(edge_count_cclko) + if (edge_count_cclko == cclko_wait_count) + start_glbl_cclko = 1; + +//------------------------------------------------------------------------------- +//-------------------- OUTPUT --------------------------------------------------- +//------------------------------------------------------------------------------- + + assign CFGMCLK = cfgmclk_out; + assign PREQ = PREQ_out; + assign EOS = EOS_out; + assign glbl.CCLKO_GLBL = start_glbl_cclko ? (~USRCCLKTS ? USRCCLKO : 1'bz) : 1'b1; + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/STARTUPE3.v b/verilog/src/unisims/STARTUPE3.v new file mode 100644 index 0000000..1bf4330 --- /dev/null +++ b/verilog/src/unisims/STARTUPE3.v @@ -0,0 +1,185 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls +// /___/ /\ Filename : STARTUPE3.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 07/12/13 - Initial version. +// 02/06/14 - Fixed tristate of USRCCLKTS (CR 766066). +// 04/15/14 - Updated FCSBO, DO and DI to connect to glbl (CR 763244). +// 05/27/14 - New simulation library message format. +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module STARTUPE3 #( + `ifdef XIL_TIMING //Simprim + parameter LOC = "UNPLACED", + `endif + parameter PROG_USR = "FALSE", + parameter real SIM_CCLK_FREQ = 0.0 +)( + output CFGCLK, + output CFGMCLK, + output [3:0] DI, + output EOS, + output PREQ, + + input [3:0] DO, + input [3:0] DTS, + input FCSBO, + input FCSBTS, + input GSR, + input GTS, + input KEYCLEARB, + input PACK, + input USRCCLKO, + input USRCCLKTS, + input USRDONEO, + input USRDONETS +); + + reg SIM_CCLK_FREQ_BINARY; + reg [2:0] PROG_USR_BINARY; + + time CFGMCLK_PERIOD = 20000; + reg cfgmclk_out; + localparam MODULE_NAME = "STARTUPE3"; + + assign (strong1,weak0) glbl.GSR = GSR; + assign (strong1,weak0) glbl.GTS = GTS; + + wire start_count; + integer edge_count; + reg preq_deassert; + reg PREQ_out; + wire EOS_out; + +// Counters and Flags + reg [2:0] edge_count_cclko; + reg [2:0] cclko_wait_count; + reg start_glbl_cclko; + + initial begin + case (PROG_USR) + "FALSE" : PROG_USR_BINARY = 3'b000; + "TRUE" : PROG_USR_BINARY = 3'b111; + default : begin + $display("Error: [Unisim %s-101] PROG_USR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PROG_USR); + #1 $finish; + end + endcase + + if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0)) + SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ; + else begin + $display("Error: [Unisim %s-102] SIM_CCLK_FREQ attribute is set to %f. Legal values for this attribute are 0.0 to 10.0. Instance: %m", MODULE_NAME, SIM_CCLK_FREQ); + #1 $finish; + end + + end +//------------------------------------------------------------------------------- +//----------------- Initial ----------------------------------------------------- +//------------------------------------------------------------------------------- + initial begin + cfgmclk_out = 0; + edge_count = 0; + preq_deassert = 1'b0; + PREQ_out = 1'b0; + edge_count_cclko = 3'b000; + cclko_wait_count = 3'b010; + start_glbl_cclko = 1'b0; + forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out; + end + +//------------------------------------------------------------------------------- +//-------------------- PREQ ----------------------------------------------------- +//------------------------------------------------------------------------------- + + assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0; + + always @(posedge cfgmclk_out) begin + if(start_count) + edge_count = edge_count + 1; + else + edge_count = 0; + + if(edge_count == 35) + preq_deassert <= 1'b1; + else + preq_deassert <= 1'b0; + end + + + always @(negedge glbl.PROGB_GLBL, posedge preq_deassert) + PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert; + +//------------------------------------------------------------------------------- +//-------------------- ERROR MSG ------------------------------------------------ +//------------------------------------------------------------------------------- + always @(posedge PACK) begin + if(PREQ_out == 1'b0) + $display("Warning: [Unisim %s-1] PACK received with no associate PREQ. Instance: %m", MODULE_NAME); + end + +//------------------------------------------------------------------------------- +//--------------------- EOS ----------------------------------------------------- +//------------------------------------------------------------------------------- + + assign EOS_out = ~glbl.GSR; +//------------------------------------------------------------------------------- +//-------------------- glbl.CCLKO --------------------------------------------- +//------------------------------------------------------------------------------- + + always @(posedge USRCCLKO) begin + if(EOS_out) edge_count_cclko <= edge_count_cclko + 1; + end + + always @(edge_count_cclko) + if (edge_count_cclko == cclko_wait_count) + start_glbl_cclko = 1; + +//------------------------------------------------------------------------------- +//-------------------- OUTPUT --------------------------------------------------- +//------------------------------------------------------------------------------- + + assign CFGMCLK = cfgmclk_out; + assign PREQ = PREQ_out; + assign EOS = EOS_out; + assign glbl.CCLKO_GLBL = start_glbl_cclko ? (~USRCCLKTS ? USRCCLKO : 1'bz) : 1'b1; + + assign glbl.FCSBO_GLBL = ~FCSBTS ? FCSBO : 1'bz; + assign glbl.DO_GLBL[0] = ~DTS[0] ? DO[0] : 1'bz; + assign glbl.DO_GLBL[1] = ~DTS[1] ? DO[1] : 1'bz; + assign glbl.DO_GLBL[2] = ~DTS[2] ? DO[2] : 1'bz; + assign glbl.DO_GLBL[3] = ~DTS[3] ? DO[3] : 1'bz; + assign DI = glbl.DI_GLBL; + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SYSMONE1.v b/verilog/src/unisims/SYSMONE1.v new file mode 100644 index 0000000..cff8ab5 --- /dev/null +++ b/verilog/src/unisims/SYSMONE1.v @@ -0,0 +1,3454 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / System Monitor +// /___/ /\ Filename : SYSMONE1.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 01/31/13 - Initial version. +// 03/19/13 - Fixed fatal width problem (CR 707214). +// - Update MUXADDR width (CR 706758). +// 03/20/13 - Fixed output MSB problem (CR 706163). +// - Remove SCL and SDA ports (CR 707646). +// 04/26/13 - Add invertible pin support (PR 683925). +// 05/01/13 - Fixed DRC for IS_*_INVERTED parameters (CR 715818). +// 05/08/13 - Changed Vuser1-4 to Vuser 0-3 (CR 716783). +// 06/04/13 - Added I2CSCLK and I2CSDA ports (CR 721147). +// 06/19/13 - Fixed CHANNEL output (CR 717955). +// 10/15/13 - Added I2C simulation support (CR 707725). +// 10/28/13 - Removed DRC for event mode timing (CR 736315). +// 11/15/13 - Updated I2C support for in and output instead of inout (CR 742395). +// 11/22/13 - Updated VBRAM to VCCBRAM (CR 755165). +// 01/21/14 - Added missing timing (CR 767834). +// 01/21/14 - Fixed Vuser (CR 766501). +// 03/20/14 - Fixed event driven mode in single pass sequence (CR 764936). +// 03/21/14 - Balanced all inputs with xor (CR 778933). +// 04/30/14 - Initialized chan_val and chan_valn (CR 782388). +// 05/27/14 - New simulation library message format. +// 06/17/14 - Fixed default mode sequencer (CR 800173) +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/22/14 - Added #1 to $finish (CR 808642). +// 12/12/14 - Added missing WIDTH timing check for CONVST (CR 836426). +// Updated new temperature calculation (CR 828651). +// 02/04/15 - Fixed DO output with DCLK division 4 or lower (CR 840852). +// 02/19/15 - Fixed I2C initial sync issue (CR 847938). +// 03/06/15 - Fixed I2C addr when I2C_OR = 0 at initial time. +// 03/17/15 - Fixed sequencer out of bound (CR 850975). +// 04/10/15 - Updated new temperature calculation (CR 828651). +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ps / 1ps + +`celldefine + + module SYSMONE1 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] INIT_40 = 16'h0000, + parameter [15:0] INIT_41 = 16'h0000, + parameter [15:0] INIT_42 = 16'h0000, + parameter [15:0] INIT_43 = 16'h0000, + parameter [15:0] INIT_44 = 16'h0000, + parameter [15:0] INIT_45 = 16'h0000, + parameter [15:0] INIT_46 = 16'h0000, + parameter [15:0] INIT_47 = 16'h0000, + parameter [15:0] INIT_48 = 16'h0000, + parameter [15:0] INIT_49 = 16'h0000, + parameter [15:0] INIT_4A = 16'h0000, + parameter [15:0] INIT_4B = 16'h0000, + parameter [15:0] INIT_4C = 16'h0000, + parameter [15:0] INIT_4D = 16'h0000, + parameter [15:0] INIT_4E = 16'h0000, + parameter [15:0] INIT_4F = 16'h0000, + parameter [15:0] INIT_50 = 16'h0000, + parameter [15:0] INIT_51 = 16'h0000, + parameter [15:0] INIT_52 = 16'h0000, + parameter [15:0] INIT_53 = 16'h0000, + parameter [15:0] INIT_54 = 16'h0000, + parameter [15:0] INIT_55 = 16'h0000, + parameter [15:0] INIT_56 = 16'h0000, + parameter [15:0] INIT_57 = 16'h0000, + parameter [15:0] INIT_58 = 16'h0000, + parameter [15:0] INIT_59 = 16'h0000, + parameter [15:0] INIT_5A = 16'h0000, + parameter [15:0] INIT_5B = 16'h0000, + parameter [15:0] INIT_5C = 16'h0000, + parameter [15:0] INIT_5D = 16'h0000, + parameter [15:0] INIT_5E = 16'h0000, + parameter [15:0] INIT_5F = 16'h0000, + parameter [15:0] INIT_60 = 16'h0000, + parameter [15:0] INIT_61 = 16'h0000, + parameter [15:0] INIT_62 = 16'h0000, + parameter [15:0] INIT_63 = 16'h0000, + parameter [15:0] INIT_64 = 16'h0000, + parameter [15:0] INIT_65 = 16'h0000, + parameter [15:0] INIT_66 = 16'h0000, + parameter [15:0] INIT_67 = 16'h0000, + parameter [15:0] INIT_68 = 16'h0000, + parameter [15:0] INIT_69 = 16'h0000, + parameter [15:0] INIT_6A = 16'h0000, + parameter [15:0] INIT_6B = 16'h0000, + parameter [15:0] INIT_6C = 16'h0000, + parameter [15:0] INIT_6D = 16'h0000, + parameter [15:0] INIT_6E = 16'h0000, + parameter [15:0] INIT_6F = 16'h0000, + parameter [15:0] INIT_70 = 16'h0000, + parameter [15:0] INIT_71 = 16'h0000, + parameter [15:0] INIT_72 = 16'h0000, + parameter [15:0] INIT_73 = 16'h0000, + parameter [15:0] INIT_74 = 16'h0000, + parameter [15:0] INIT_75 = 16'h0000, + parameter [15:0] INIT_76 = 16'h0000, + parameter [15:0] INIT_77 = 16'h0000, + parameter [15:0] INIT_78 = 16'h0000, + parameter [15:0] INIT_79 = 16'h0000, + parameter [15:0] INIT_7A = 16'h0000, + parameter [15:0] INIT_7B = 16'h0000, + parameter [15:0] INIT_7C = 16'h0000, + parameter [15:0] INIT_7D = 16'h0000, + parameter [15:0] INIT_7E = 16'h0000, + parameter [15:0] INIT_7F = 16'h0000, + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0, + parameter [0:0] IS_DCLK_INVERTED = 1'b0, + parameter SIM_MONITOR_FILE = "design.txt", + parameter integer SYSMON_VUSER0_BANK = 0, + parameter SYSMON_VUSER0_MONITOR = "NONE", + parameter integer SYSMON_VUSER1_BANK = 0, + parameter SYSMON_VUSER1_MONITOR = "NONE", + parameter integer SYSMON_VUSER2_BANK = 0, + parameter SYSMON_VUSER2_MONITOR = "NONE", + parameter integer SYSMON_VUSER3_BANK = 0, + parameter SYSMON_VUSER3_MONITOR = "NONE" +)( + + output [15:0] ALM, + output BUSY, + output [5:0] CHANNEL, + output [15:0] DO, + output DRDY, + output EOC, + output EOS, + output I2C_SCLK_TS, + output I2C_SDA_TS, + output JTAGBUSY, + output JTAGLOCKED, + output JTAGMODIFIED, + output [4:0] MUXADDR, + output OT, + + input CONVST, + input CONVSTCLK, + input [7:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input I2C_SCLK, + input I2C_SDA, + input RESET, + input [15:0] VAUXN, + input [15:0] VAUXP, + input VN, + input VP + ); + +// define constants + localparam MODULE_NAME = "SYSMONE1"; + +// Parameter encodings and registers + //localparam SIM_DEVICE_ULTRASCALE_PLUS = 0; + //localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 1; + //localparam SIM_DEVICE_ZYNQ_ULTRASCALE = 2; + //localparam SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 = 3; + //localparam SIM_MONITOR_FILE_design_txt = 0; + //localparam SYSMON_VUSER0_MONITOR_NONE = 0; + //localparam SYSMON_VUSER1_MONITOR_NONE = 0; + //localparam SYSMON_VUSER2_MONITOR_NONE = 0; + //localparam SYSMON_VUSER3_MONITOR_NONE = 0; + + reg trig_attr = 1'b0; + reg trig_dep_attr = 1'b0; + reg trig_i2c_addr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "SYSMONE1_dr.v" +`else + localparam [15:0] INIT_40_REG = INIT_40; + localparam [15:0] INIT_41_REG = INIT_41; + localparam [15:0] INIT_42_REG = INIT_42; + localparam [15:0] INIT_43_REG = INIT_43; + localparam [15:0] INIT_44_REG = INIT_44; + localparam [15:0] INIT_45_REG = INIT_45; + localparam [15:0] INIT_46_REG = INIT_46; + localparam [15:0] INIT_47_REG = INIT_47; + localparam [15:0] INIT_48_REG = INIT_48; + localparam [15:0] INIT_49_REG = INIT_49; + localparam [15:0] INIT_4A_REG = INIT_4A; + localparam [15:0] INIT_4B_REG = INIT_4B; + localparam [15:0] INIT_4C_REG = INIT_4C; + localparam [15:0] INIT_4D_REG = INIT_4D; + localparam [15:0] INIT_4E_REG = INIT_4E; + localparam [15:0] INIT_4F_REG = INIT_4F; + localparam [15:0] INIT_50_REG = INIT_50; + localparam [15:0] INIT_51_REG = INIT_51; + localparam [15:0] INIT_52_REG = INIT_52; + localparam [15:0] INIT_53_REG = INIT_53; + localparam [15:0] INIT_54_REG = INIT_54; + localparam [15:0] INIT_55_REG = INIT_55; + localparam [15:0] INIT_56_REG = INIT_56; + localparam [15:0] INIT_57_REG = INIT_57; + localparam [15:0] INIT_58_REG = INIT_58; + localparam [15:0] INIT_59_REG = INIT_59; + localparam [15:0] INIT_5A_REG = INIT_5A; + localparam [15:0] INIT_5B_REG = INIT_5B; + localparam [15:0] INIT_5C_REG = INIT_5C; + localparam [15:0] INIT_5D_REG = INIT_5D; + localparam [15:0] INIT_5E_REG = INIT_5E; + localparam [15:0] INIT_5F_REG = INIT_5F; + localparam [15:0] INIT_60_REG = INIT_60; + localparam [15:0] INIT_61_REG = INIT_61; + localparam [15:0] INIT_62_REG = INIT_62; + localparam [15:0] INIT_63_REG = INIT_63; + localparam [15:0] INIT_64_REG = INIT_64; + localparam [15:0] INIT_65_REG = INIT_65; + localparam [15:0] INIT_66_REG = INIT_66; + localparam [15:0] INIT_67_REG = INIT_67; + localparam [15:0] INIT_68_REG = INIT_68; + localparam [15:0] INIT_69_REG = INIT_69; + localparam [15:0] INIT_6A_REG = INIT_6A; + localparam [15:0] INIT_6B_REG = INIT_6B; + localparam [15:0] INIT_6C_REG = INIT_6C; + localparam [15:0] INIT_6D_REG = INIT_6D; + localparam [15:0] INIT_6E_REG = INIT_6E; + localparam [15:0] INIT_6F_REG = INIT_6F; + localparam [15:0] INIT_70_REG = INIT_70; + localparam [15:0] INIT_71_REG = INIT_71; + localparam [15:0] INIT_72_REG = INIT_72; + localparam [15:0] INIT_73_REG = INIT_73; + localparam [15:0] INIT_74_REG = INIT_74; + localparam [15:0] INIT_75_REG = INIT_75; + localparam [15:0] INIT_76_REG = INIT_76; + localparam [15:0] INIT_77_REG = INIT_77; + localparam [15:0] INIT_78_REG = INIT_78; + localparam [15:0] INIT_79_REG = INIT_79; + localparam [15:0] INIT_7A_REG = INIT_7A; + localparam [15:0] INIT_7B_REG = INIT_7B; + localparam [15:0] INIT_7C_REG = INIT_7C; + localparam [15:0] INIT_7D_REG = INIT_7D; + localparam [15:0] INIT_7E_REG = INIT_7E; + localparam [15:0] INIT_7F_REG = INIT_7F; + localparam [0:0] IS_CONVSTCLK_INVERTED_REG = IS_CONVSTCLK_INVERTED; + localparam [0:0] IS_DCLK_INVERTED_REG = IS_DCLK_INVERTED; + localparam [80:1] SIM_MONITOR_FILE_REG = SIM_MONITOR_FILE; + localparam [9:0] SYSMON_VUSER0_BANK_REG = SYSMON_VUSER0_BANK; + localparam [32:1] SYSMON_VUSER0_MONITOR_REG = SYSMON_VUSER0_MONITOR; + localparam [9:0] SYSMON_VUSER1_BANK_REG = SYSMON_VUSER1_BANK; + localparam [32:1] SYSMON_VUSER1_MONITOR_REG = SYSMON_VUSER1_MONITOR; + localparam [9:0] SYSMON_VUSER2_BANK_REG = SYSMON_VUSER2_BANK; + localparam [32:1] SYSMON_VUSER2_MONITOR_REG = SYSMON_VUSER2_MONITOR; + localparam [9:0] SYSMON_VUSER3_BANK_REG = SYSMON_VUSER3_BANK; + localparam [32:1] SYSMON_VUSER3_MONITOR_REG = SYSMON_VUSER3_MONITOR; +`endif + + wire [15:0] INIT_40_BIN; + wire [15:0] INIT_41_BIN; + wire [15:0] INIT_42_BIN; + wire [15:0] INIT_43_BIN; + wire [15:0] INIT_44_BIN; + wire [15:0] INIT_45_BIN; + wire [15:0] INIT_46_BIN; + wire [15:0] INIT_47_BIN; + wire [15:0] INIT_48_BIN; + wire [15:0] INIT_49_BIN; + wire [15:0] INIT_4A_BIN; + wire [15:0] INIT_4B_BIN; + wire [15:0] INIT_4C_BIN; + wire [15:0] INIT_4D_BIN; + wire [15:0] INIT_4E_BIN; + wire [15:0] INIT_4F_BIN; + wire [15:0] INIT_50_BIN; + wire [15:0] INIT_51_BIN; + wire [15:0] INIT_52_BIN; + wire [15:0] INIT_53_BIN; + wire [15:0] INIT_54_BIN; + wire [15:0] INIT_55_BIN; + wire [15:0] INIT_56_BIN; + wire [15:0] INIT_57_BIN; + wire [15:0] INIT_58_BIN; + wire [15:0] INIT_59_BIN; + wire [15:0] INIT_5A_BIN; + wire [15:0] INIT_5B_BIN; + wire [15:0] INIT_5C_BIN; + wire [15:0] INIT_5D_BIN; + wire [15:0] INIT_5E_BIN; + wire [15:0] INIT_5F_BIN; + wire [15:0] INIT_60_BIN; + wire [15:0] INIT_61_BIN; + wire [15:0] INIT_62_BIN; + wire [15:0] INIT_63_BIN; + wire [15:0] INIT_64_BIN; + wire [15:0] INIT_65_BIN; + wire [15:0] INIT_66_BIN; + wire [15:0] INIT_67_BIN; + wire [15:0] INIT_68_BIN; + wire [15:0] INIT_69_BIN; + wire [15:0] INIT_6A_BIN; + wire [15:0] INIT_6B_BIN; + wire [15:0] INIT_6C_BIN; + wire [15:0] INIT_6D_BIN; + wire [15:0] INIT_6E_BIN; + wire [15:0] INIT_6F_BIN; + wire [15:0] INIT_70_BIN; + wire [15:0] INIT_71_BIN; + wire [15:0] INIT_72_BIN; + wire [15:0] INIT_73_BIN; + wire [15:0] INIT_74_BIN; + wire [15:0] INIT_75_BIN; + wire [15:0] INIT_76_BIN; + wire [15:0] INIT_77_BIN; + wire [15:0] INIT_78_BIN; + wire [15:0] INIT_79_BIN; + wire [15:0] INIT_7A_BIN; + wire [15:0] INIT_7B_BIN; + wire [15:0] INIT_7C_BIN; + wire [15:0] INIT_7D_BIN; + wire [15:0] INIT_7E_BIN; + wire [15:0] INIT_7F_BIN; + wire IS_CONVSTCLK_INVERTED_BIN; + wire IS_DCLK_INVERTED_BIN; + wire SIM_MONITOR_FILE_BIN; + wire [9:0] SYSMON_VUSER0_BANK_BIN; + wire SYSMON_VUSER0_MONITOR_BIN; + wire [9:0] SYSMON_VUSER1_BANK_BIN; + wire SYSMON_VUSER1_MONITOR_BIN; + wire [9:0] SYSMON_VUSER2_BANK_BIN; + wire SYSMON_VUSER2_MONITOR_BIN; + wire [9:0] SYSMON_VUSER3_BANK_BIN; + wire SYSMON_VUSER3_MONITOR_BIN; + + `ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; + `else + reg attr_test = 1'b0; + `endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg BUSY_out; + reg DRDY_out; + reg EOC_out; + reg EOS_out; + wire I2C_SCLK_TS_out; + reg I2C_SDA_TS_out; + wire JTAGBUSY_out; + wire JTAGLOCKED_out; + wire JTAGMODIFIED_out; + reg OT_out; + reg [15:0] ALM_out; + reg [15:0] DO_out; + reg [4:0] MUXADDR_out; + reg [5:0] CHANNEL_out; + + wire CONVSTCLK_in; + wire CONVST_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire I2C_SCLK_in; + wire I2C_SDA_in; + wire RESET_in; + wire VN_in; + wire VP_in; + wire [15:0] DI_in; + wire [15:0] VAUXN_in; + wire [15:0] VAUXP_in; + wire [7:0] DADDR_in; + + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire [15:0] DI_delay; + wire [7:0] DADDR_delay; + wire RESET_delay; +`endif + + assign ALM = ALM_out; + assign BUSY = BUSY_out; + assign CHANNEL = CHANNEL_out; + assign DO = DO_out; + assign DRDY = DRDY_out; + assign EOC = EOC_out; + assign EOS = EOS_out; + assign I2C_SCLK_TS = I2C_SCLK_TS_out; + assign I2C_SDA_TS = I2C_SDA_TS_out; + assign JTAGBUSY = JTAGBUSY_out; + assign JTAGLOCKED = JTAGLOCKED_out; + assign JTAGMODIFIED = JTAGMODIFIED_out; + assign MUXADDR = MUXADDR_out; + assign OT = OT_out; + + wire [7:0] DADDR_inv; + wire DCLK_inv; + wire DEN_inv; + wire DWE_inv; + wire RESET_in_inv; + wire [15:0] DI_inv; + wire I2C_SCLK_inv; + wire I2C_SDA_inv; + + `ifdef XIL_TIMING + assign DADDR_inv = DADDR_delay; + assign DCLK_inv = DCLK_delay; + assign DEN_inv = DEN_delay; + assign DI_inv = DI_delay; + assign DWE_inv = DWE_delay; + `else + assign DADDR_inv = DADDR; + assign DCLK_inv = DCLK; + assign DEN_inv = DEN; + assign DI_inv = DI; + assign DWE_inv = DWE; + `endif + assign I2C_SCLK_inv = I2C_SCLK; + assign I2C_SDA_inv = I2C_SDA; + + assign DADDR_in = DADDR_inv ^ 7'b0000000; + assign DCLK_in = DCLK_inv ^ IS_DCLK_INVERTED_BIN; + assign DEN_in = DEN_inv ^ 1'b0; + assign DI_in = DI_inv ^ 16'h0000; + assign DWE_in = DWE_inv ^ 1'b0; + assign RESET_in = RESET; + assign CONVSTCLK_in = CONVSTCLK ^ IS_CONVSTCLK_INVERTED_BIN; + assign CONVST_in = CONVST ^ 1'b0; + assign I2C_SCLK_in = I2C_SCLK_inv ^ 1'b0; + assign I2C_SDA_in = I2C_SDA_inv ^ 1'b0; + assign VAUXN_in = VAUXN; + assign VAUXP_in = VAUXP; + assign VN_in = VN; + assign VP_in = VP; + + assign INIT_40_BIN = INIT_40_REG; + + assign INIT_41_BIN = INIT_41_REG; + + assign INIT_42_BIN = INIT_42_REG; + + assign INIT_43_BIN = INIT_43_REG; + + assign INIT_44_BIN = INIT_44_REG; + + assign INIT_45_BIN = INIT_45_REG; + + assign INIT_46_BIN = INIT_46_REG; + + assign INIT_47_BIN = INIT_47_REG; + + assign INIT_48_BIN = INIT_48_REG; + + assign INIT_49_BIN = INIT_49_REG; + + assign INIT_4A_BIN = INIT_4A_REG; + + assign INIT_4B_BIN = INIT_4B_REG; + + assign INIT_4C_BIN = INIT_4C_REG; + + assign INIT_4D_BIN = INIT_4D_REG; + + assign INIT_4E_BIN = INIT_4E_REG; + + assign INIT_4F_BIN = INIT_4F_REG; + + assign INIT_50_BIN = INIT_50_REG; + + assign INIT_51_BIN = INIT_51_REG; + + assign INIT_52_BIN = INIT_52_REG; + + assign INIT_53_BIN = INIT_53_REG; + + assign INIT_54_BIN = INIT_54_REG; + + assign INIT_55_BIN = INIT_55_REG; + + assign INIT_56_BIN = INIT_56_REG; + + assign INIT_57_BIN = INIT_57_REG; + + assign INIT_58_BIN = INIT_58_REG; + + assign INIT_59_BIN = INIT_59_REG; + + assign INIT_5A_BIN = INIT_5A_REG; + + assign INIT_5B_BIN = INIT_5B_REG; + + assign INIT_5C_BIN = INIT_5C_REG; + + assign INIT_5D_BIN = INIT_5D_REG; + + assign INIT_5E_BIN = INIT_5E_REG; + + assign INIT_5F_BIN = INIT_5F_REG; + + assign INIT_60_BIN = INIT_60_REG; + + assign INIT_61_BIN = INIT_61_REG; + + assign INIT_62_BIN = INIT_62_REG; + + assign INIT_63_BIN = INIT_63_REG; + + assign INIT_64_BIN = INIT_64_REG; + + assign INIT_65_BIN = INIT_65_REG; + + assign INIT_66_BIN = INIT_66_REG; + + assign INIT_67_BIN = INIT_67_REG; + + assign INIT_68_BIN = INIT_68_REG; + + assign INIT_69_BIN = INIT_69_REG; + + assign INIT_6A_BIN = INIT_6A_REG; + + assign INIT_6B_BIN = INIT_6B_REG; + + assign INIT_6C_BIN = INIT_6C_REG; + + assign INIT_6D_BIN = INIT_6D_REG; + + assign INIT_6E_BIN = INIT_6E_REG; + + assign INIT_6F_BIN = INIT_6F_REG; + + assign INIT_70_BIN = INIT_70_REG; + + assign INIT_71_BIN = INIT_71_REG; + + assign INIT_72_BIN = INIT_72_REG; + + assign INIT_73_BIN = INIT_73_REG; + + assign INIT_74_BIN = INIT_74_REG; + + assign INIT_75_BIN = INIT_75_REG; + + assign INIT_76_BIN = INIT_76_REG; + + assign INIT_77_BIN = INIT_77_REG; + + assign INIT_78_BIN = INIT_78_REG; + + assign INIT_79_BIN = INIT_79_REG; + + assign INIT_7A_BIN = INIT_7A_REG; + + assign INIT_7B_BIN = INIT_7B_REG; + + assign INIT_7C_BIN = INIT_7C_REG; + + assign INIT_7D_BIN = INIT_7D_REG; + + assign INIT_7E_BIN = INIT_7E_REG; + + assign INIT_7F_BIN = INIT_7F_REG; + + assign IS_CONVSTCLK_INVERTED_BIN = IS_CONVSTCLK_INVERTED_REG; + + assign IS_DCLK_INVERTED_BIN = IS_DCLK_INVERTED_REG; + + // assign SIM_DEVICE_BIN = + // (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + // (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + // (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE") ? SIM_DEVICE_ZYNQ_ULTRASCALE : + // (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE_ES1") ? SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 : + // SIM_DEVICE_ULTRASCALE_PLUS; + // + // assign SIM_MONITOR_FILE_BIN = + // (SIM_MONITOR_FILE_REG == "design.txt") ? SIM_MONITOR_FILE_design_txt : + // SIM_MONITOR_FILE_design_txt; + // + assign SYSMON_VUSER0_BANK_BIN = SYSMON_VUSER0_BANK_REG; + + // assign SYSMON_VUSER0_MONITOR_BIN = + // (SYSMON_VUSER0_MONITOR_REG == "NONE") ? SYSMON_VUSER0_MONITOR_NONE : + // SYSMON_VUSER0_MONITOR_NONE; + + assign SYSMON_VUSER1_BANK_BIN = SYSMON_VUSER1_BANK_REG; + + // assign SYSMON_VUSER1_MONITOR_BIN = + // (SYSMON_VUSER1_MONITOR_REG == "NONE") ? SYSMON_VUSER1_MONITOR_NONE : + // SYSMON_VUSER1_MONITOR_NONE; + + assign SYSMON_VUSER2_BANK_BIN = SYSMON_VUSER2_BANK_REG; + + // assign SYSMON_VUSER2_MONITOR_BIN = + // (SYSMON_VUSER2_MONITOR_REG == "NONE") ? SYSMON_VUSER2_MONITOR_NONE : + // SYSMON_VUSER2_MONITOR_NONE; + + assign SYSMON_VUSER3_BANK_BIN = SYSMON_VUSER3_BANK_REG; + + // assign SYSMON_VUSER3_MONITOR_BIN = + // (SYSMON_VUSER3_MONITOR_REG == "NONE") ? SYSMON_VUSER3_MONITOR_NONE : + // SYSMON_VUSER3_MONITOR_NONE; + + initial begin + trig_attr = 0; + #1; + trig_i2c_addr = 1; + trig_attr = 1; + #2 trig_dep_attr = 1; + end + + always @(posedge trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((SYSMON_VUSER0_BANK_REG < 0) || (SYSMON_VUSER0_BANK_REG > 999))) begin + $display("Error: [Unisim %s-170] SYSMON_VUSER0_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER0_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER1_BANK_REG < 0) || (SYSMON_VUSER1_BANK_REG > 999))) begin + $display("Error: [Unisim %s-172] SYSMON_VUSER1_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER1_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER2_BANK_REG < 0) || (SYSMON_VUSER2_BANK_REG > 999))) begin + $display("Error: [Unisim %s-174] SYSMON_VUSER2_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER2_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER3_BANK_REG < 0) || (SYSMON_VUSER3_BANK_REG > 999))) begin + $display("Error: [Unisim %s-176] SYSMON_VUSER3_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER3_BANK_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end // always @ (trig_attr) + + + always @(trig_dep_attr) begin + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[8]==1) && (INIT_40_BIN[5:0] != 6'b000011) && (INIT_40_BIN[5:0] < 6'b010000))) + $display("Warning: [Unisim %s-1] INIT_40 attribute is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_40_BIN); + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]!=4'b0011) && (INIT_4E_BIN[10:0]!=11'd0) && (INIT_4E_BIN[15:12]!=4'd0))) + $display("Warning: [Unisim %s-2] INIT_4E attribute is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_4E_BIN); + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[13:12]!=2'b00) && (INIT_46_BIN != 16'h0000) && (INIT_48_BIN != 16'h0000) && (INIT_49_BIN != 16'h0000))) + $display("Warning: [Unisim %s-3] INIT_46, INIT_48 and INIT_49 attributes are set to %x, %x, and %x respectively. These attributes must be set to 0000h in single channel mode with averaging enabled. Instance: %m", MODULE_NAME, INIT_46_BIN, INIT_48_BIN, INIT_49_BIN); + + // CR1004434 + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]==4'b0001|| INIT_41_BIN[15:12]==4'b0010) && INIT_46_BIN[3:0]!=4'b0000) || //single pass or cont mode and vuser selected + (INIT_41_BIN[15:12]==4'b0011 && INIT_40_BIN[5:2]==4'b1000) //single channel mode and vuser is selected + ) + $display("Warning: [Unisim %s-177] INIT_40 and INIT_41 attributes are set to %x and %x respectively. VUSER is selected. In Kintex devices, SYSMONE1 model has no way of knowing whether VUSER has a 6V range or a 3V range and assumes all channels have 3V range. If HR banks are selected, the value stored in the model's registers will be different than that of the actual hardware; and only for this specific case VUSER simulation checks should be ignored. Instance: %m", MODULE_NAME, INIT_40_BIN, INIT_41_BIN); + end // always @ (trig_dep_attr) + + + // Total UNISIM %s- warning message next: 59 + + localparam CONV_CNT_P = 37; + localparam CONV_CNT = 48; + + //Convergence periods + localparam CONV_CAL_PER_RST = 6; + localparam CONV_CAL_PER_0 = 2; + localparam CONV_NOTCAL_PER_1 = 18; // //minus 3 ->old comment + localparam CONV_CAL_PER_2 = 96; + localparam CONV_CAL_PER_3 = 96; + localparam CONV_CAL_PER_4 = 44; + localparam CONV_CAL_PER_5 = 21; + + //sequencer operation + localparam [3:0] SEQ_DEFAULT_MODE = 4'b0000 ; + localparam [1:0] SEQ_DEFAULT_MODE2 = 2'b11 ; + localparam [3:0] SEQ_SINGLE_PASS = 4'b0001 ; + localparam [3:0] SEQ_CONT_CHAN = 4'b0010 ; + localparam [3:0] SEQ_SINGLE_CHAN = 4'b0011 ;//means sequencer is off + + //`define CALIBRATION_ALWAYS_FIRST + + //adc_state + localparam S0_ST = 0, + S1_ST = 1, + S2_ST = 2, + S3_ST = 3, + S5_ST = 5, + S6_ST = 6; + + time time_out, prev_time_out; + + integer temperature_index = -1, time_index = -1, vccaux_index = -1; + integer vccbram_index = -1; + integer vccint_index = -1, vn_index = -1, vp_index = -1; + integer vccpint_index = -1; + integer vccpaux_index = -1; + integer vccpdro_index = -1; + integer vauxp_idx[15:0]; integer vauxn_idx[15:0]; + integer vuser0_index = -1, vuser1_index = -1; + integer vuser2_index = -1, vuser3_index = -1; + integer char_1, char_2, fs, fd; + integer num_arg, num_val; + integer clk_count; + reg clk_count_rst = 0; + integer seq_count, seq_count_a; + integer seq_status_avg, acq_count; + integer conv_avg_count [63:0]; + wire [7:0] avg_amount; + integer conv_acc [63:0]; + integer conv_result_int; + integer conv_count; + integer h, i, j, k, l, m, n, p; + integer file_line; + + // string + reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46; + reg [8*600:1] one_line; + reg [8*12:1] label [46:0]; + reg [8*12:1] tmp_label; + reg end_of_file; + + real tmp_va0, tmp_va1, column_real00, column_real100, column_real101; + real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46; + + // array of real numbers + reg [63:0] column_real [CONV_CNT-1 :0]; + reg [63:0] chan_val [CONV_CNT_P-1:0]; + reg [63:0] chan_val_tmp [CONV_CNT_P-1:0]; + reg [63:0] chan_valn [CONV_CNT_P-1:0]; + reg [63:0] chan_valn_tmp [CONV_CNT_P-1:0]; + reg [63:0] mn_in_diff [CONV_CNT_P-1:0]; + reg [63:0] mn_in2_diff [CONV_CNT_P-1:0]; + reg [63:0] mn_in_uni [CONV_CNT_P-1:0]; + reg [63:0] mn_in2_uni [CONV_CNT_P-1:0]; + reg [63:0] mn_comm_in [CONV_CNT_P-1:0]; + reg [63:0] mn_comm2_in [CONV_CNT_P-1:0]; + + real chan_val_p_tmp, chan_val_n_tmp; + real mn_mux_in, mn_in_tmp, mn_comm_in_tmp, mn_in_comm; + real tmp_v, tmp_v1; + real adc_temp_result, adc_intpwr_result; + real adc_ext_result; + + reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly; + reg soft_reset = 0; + reg en_data_flag; + reg first_cal_chan; + reg seq_en; + reg seq_en_dly; + wire [15:0] flag_reg0, flag_reg1; + reg [15:0] ot_limit_reg = 16'hCA30; + reg [15:0] tmp_otv; + reg [23:0] conv_acc_vec; + reg [15:0] conv_result; + reg [15:0] conv_result_reg, conv_acc_result; + wire [7:0] curr_clkdiv_sel; + reg [15:0] alm_out_reg; + reg [5:0] curr_chan, curr_chan_lat; + reg [15:0] data_written; + reg [2:0] adc_state, adc_next_state; + reg conv_start, conv_end; + reg eos_en, eos_tmp_en; + reg DRDY_out_tmp1, DRDY_out_tmp2, DRDY_out_tmp3; + reg ot_out_reg; + reg [15:0] DO_out_rdtmp; + reg [15:0] data_reg [63:0]; + reg [15:0] dr_sram [255:64]; + reg sysclk; + reg adcclk_tmp; + wire adcclk; + wire sysmone1_en, sysmone12_en; + reg [3:0] curr_seq1_0; + reg [3:0] curr_seq1_0_lat; + reg curr_e_c, curr_b_u, curr_acq; + reg seq_count_en; + reg [5:0] acq_chan; + reg [4:0] acq_chan_m; + + wire ext_mux_en; + wire [5:0] ext_mux_chan; + wire default_mode; + wire single_pass_mode; + wire cont_seq_mode; + wire single_chan_mode; + reg acq_b_u; + reg single_pass_finished; + reg acq_acqsel; + wire acq_e_c; + reg acq_e_c_tmp5, acq_e_c_tmp6; + reg [1:0] averaging, averaging_d; + reg eoc_en, eoc_en_delay; + reg EOC_out_tmp, EOS_out_tmp; + reg EOC_out_tmp1, EOS_out_tmp1; + reg EOC_out_pre; + reg EOC_out_pre2; + reg busy_r, busy_r_rst; + reg busy_sync1, busy_sync2; + wire busy_sync_fall, busy_sync_rise; + reg rst_lock, rst_lock_early, rst_lock_late; + reg sim_file_flag; + reg [7:0] DADDR_in_lat; + reg [15:0] curr_seq, curr_seq_m; + reg busy_rst, busy_conv, busy_seq_rst; + wire [3:0] seq1_0; + reg [3:0] seq_bits; + reg ot_en, alm_update, drp_update, cal_chan_update; + reg [13:0] alm_en; + reg [4:0] scon_tmp; + wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_chan_reg3; + wire [15:0] seq_acq_reg1, seq_acq_reg2, seq_acq_reg3; + wire [15:0] seq_avg_reg1, seq_avg_reg2, seq_avg_reg3; + wire [15:0] seq_bu_reg1, seq_bu_reg2, seq_bu_reg3; + reg [15:0] cfg_reg1_init; + + reg [5:0] seq_curr_i, seq_curr_ia; + integer busy_rst_cnt; + integer si; + integer hr_tot_chan; + integer seq_mem [37:0]; + + wire rst_in, adc_convst; + wire [15:0] cfg_reg0; + wire [15:0] cfg_reg1; + wire [15:0] cfg_reg2; + wire [15:0] cfg_reg3; + reg reserved_addr_pre; + reg read_only_pre; + reg RESERVED_ADDR; + reg READ_ONLY; + wire i2c_addr_cap = 0; + wire i2c_addr_cap_ne; + reg i2c_addr_cap_d; + wire convst_in_pre; + reg CONVST_reg; + wire rst_in_not_seq; + wire adcclk_div1; + wire gsr_in; + assign JTAGBUSY_out = 0; + assign JTAGLOCKED_out = 0; + assign JTAGMODIFIED_out = 0; + assign gsr_in = glblGSR; + + // initialize chan_val and chan_valn + integer ii, jj; + initial begin + for (ii = 0; ii < CONV_CNT_P; ii = ii + 1) + chan_val[ii] = 64'd0; + for (jj = 0; jj < 36; jj = jj + 1) + chan_valn[jj] = 64'd0; + end + + // initialize vauxn_idx and vauxp_idx + integer mm, nn; + initial begin + for (mm = 0; mm < 16; mm = mm + 1) + vauxn_idx[mm] = -1; + for (nn = 0; nn < 16; nn = nn + 1) + vauxp_idx[nn] = -1; + end + + //CR 675227 + //for single pass mode + + integer halt_adc = 0; + reg int_rst; + reg int_rst_halt_adc = 0; + + always @(posedge RESET_in) + halt_adc <= 0; + + always @(seq1_0) begin + if (halt_adc == 2 && single_pass_mode) begin + halt_adc <= 0; + int_rst_halt_adc <= 1; + @(posedge DCLK_in) + int_rst_halt_adc <= 0; + end + + end + + real i2c_vpvn_addr_tmp; + integer i2c_conv_result_int; + reg i2c_en; + reg i2c_oride; + reg [6:0] i2c_device_addr; + reg [6:0] i2c_device_addr_vpvn; + reg [15:0] conv_result_i2c_addr; + + initial begin + i2c_en = 1; + end + + // I2C slave address mapping + always @(*) begin + i2c_en = cfg_reg3[7]; + i2c_oride = cfg_reg3[15]; + i2c_device_addr = (i2c_oride) ? cfg_reg3[14:8]: i2c_device_addr_vpvn; + end + + + assign convst_in_pre = (CONVST_in===1 || CONVSTCLK_in===1) ? 1: 0; + + always @(posedge convst_in_pre or negedge convst_in_pre or posedge rst_in) + if (rst_in == 1 || rst_lock == 1) + CONVST_reg <= 0; + else if (convst_in_pre == 1) + CONVST_reg <= 1; + else if (convst_in_pre == 0) + CONVST_reg <= 0; + + + always @(posedge trig_attr) begin + dr_sram[8'h40] = INIT_40_BIN; + dr_sram[8'h41] = INIT_41_BIN; + dr_sram[8'h42] = INIT_42_BIN; + dr_sram[8'h43] = INIT_43_BIN; + dr_sram[8'h44] = INIT_44_BIN; + dr_sram[8'h45] = INIT_45_BIN; + dr_sram[8'h46] = INIT_46_BIN; + dr_sram[8'h47] = INIT_47_BIN; + dr_sram[8'h48] = INIT_48_BIN; + dr_sram[8'h49] = INIT_49_BIN; + dr_sram[8'h4A] = INIT_4A_BIN; + dr_sram[8'h4B] = INIT_4B_BIN; + dr_sram[8'h4C] = INIT_4C_BIN; + dr_sram[8'h4D] = INIT_4D_BIN; + dr_sram[8'h4E] = INIT_4E_BIN; + dr_sram[8'h4F] = INIT_4F_BIN; + dr_sram[8'h50] = INIT_50_BIN; + dr_sram[8'h51] = INIT_51_BIN; + dr_sram[8'h52] = INIT_52_BIN; + + tmp_otv = INIT_53_BIN; + if (tmp_otv [3:0] == 4'b0011) begin + dr_sram[8'h53] = INIT_53_BIN; + ot_limit_reg = INIT_53_BIN; + end + else begin + dr_sram[8'h53] = 16'hCA30; + ot_limit_reg = 16'hCA30; + end + + dr_sram[8'h54] = INIT_54_BIN; + dr_sram[8'h55] = INIT_55_BIN; + dr_sram[8'h56] = INIT_56_BIN; + dr_sram[8'h57] = INIT_57_BIN; + dr_sram[8'h58] = INIT_58_BIN; + dr_sram[8'h59] = INIT_59_BIN; + dr_sram[8'h5A] = INIT_5A_BIN; + dr_sram[8'h5B] = INIT_5B_BIN; + dr_sram[8'h5C] = INIT_5C_BIN; + dr_sram[8'h5D] = INIT_5D_BIN; + dr_sram[8'h5E] = INIT_5E_BIN; + dr_sram[8'h5F] = INIT_5F_BIN; + dr_sram[8'h60] = INIT_60_BIN; + dr_sram[8'h61] = INIT_61_BIN; + dr_sram[8'h62] = INIT_62_BIN; + dr_sram[8'h63] = INIT_63_BIN; + dr_sram[8'h68] = INIT_68_BIN; + dr_sram[8'h69] = INIT_69_BIN; + dr_sram[8'h6A] = INIT_6A_BIN; + dr_sram[8'h6B] = INIT_6B_BIN; + dr_sram[8'h78] = INIT_78_BIN; + dr_sram[8'h79] = INIT_79_BIN; + dr_sram[8'h7A] = INIT_7A_BIN; + dr_sram[8'h7B] = INIT_7B_BIN; + dr_sram[8'h7C] = INIT_7C_BIN; + + end // always @ (trig_attr) + + + + // read input file + initial begin + char_1 = 0; + char_2 = 0; + time_out = 0; + sim_file_flag = 0; + file_line = -1; + end_of_file = 0; + fd = $fopen(SIM_MONITOR_FILE, "r"); + if (fd == 0) begin + $display("Error: [Unisim %s-4] The analog data file %s was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt. Instance: %m", MODULE_NAME, SIM_MONITOR_FILE); + sim_file_flag = 1; + #1 $finish; + end + + if (sim_file_flag == 0) begin + while (end_of_file==0) begin + file_line = file_line + 1; + char_1 = $fgetc (fd); + char_2 = $fgetc (fd); + //if(char_2==`EOFile) + if(char_2== -1) + end_of_file = 1; + else begin // not end of file + // Ignore Comments + if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + // Getting labels + else if ((char_1 == "T" & char_2 == "I" ) || + (char_1 == "T" & char_2 == "i" ) || + (char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s ", + label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46); + + label[0] = label0; + label[1] = label1; + label[2] = label2; + label[3] = label3; + label[4] = label4; + label[5] = label5; + label[6] = label6; + label[7] = label7; + label[8] = label8; + label[9] = label9; + label[10] = label10; + label[11] = label11; + label[12] = label12; + label[13] = label13; + label[14] = label14; + label[15] = label15; + label[16] = label16; + label[17] = label17; + label[18] = label18; + label[19] = label19; + label[20] = label20; + label[21] = label21; + label[22] = label22; + label[23] = label23; + label[24] = label24; + label[25] = label25; + label[26] = label26; + label[27] = label27; + label[28] = label28; + label[29] = label29; + label[30] = label30; + label[31] = label31; + label[32] = label32; + label[33] = label33; + label[34] = label34; + label[35] = label35; + label[36] = label36; + label[37] = label37; + label[38] = label38; + label[39] = label39; + label[40] = label40; + label[41] = label41; + label[42] = label42; + label[43] = label43; + label[44] = label44; + label[45] = label45; + label[46] = label46; + + for (m = 0; m < num_arg; m = m +1) begin + tmp_label = 96'b0; + tmp_label = to_upcase_label(label[m]); + case (tmp_label) + "TEMP" : temperature_index = m; + "TIME" : time_index = m; + "VCCAUX" : vccaux_index = m; + "VCCINT" : vccint_index = m; + "VCCBRAM" : vccbram_index = m; + "VCCPINT" : vccpint_index = m; + "VCCPAUX" : vccpaux_index = m; + "VCCDDRO" : vccpdro_index = m; + "VN" : vn_index = m; + "VAUXN[0]" : vauxn_idx[0] = m; + "VAUXN[1]" : vauxn_idx[1] = m; + "VAUXN[2]" : vauxn_idx[2] = m; + "VAUXN[3]" : vauxn_idx[3] = m; + "VAUXN[4]" : vauxn_idx[4] = m; + "VAUXN[5]" : vauxn_idx[5] = m; + "VAUXN[6]" : vauxn_idx[6] = m; + "VAUXN[7]" : vauxn_idx[7] = m; + "VAUXN[8]" : vauxn_idx[8] = m; + "VAUXN[9]" : vauxn_idx[9] = m; + "VAUXN[10]" : vauxn_idx[10] = m; + "VAUXN[11]" : vauxn_idx[11] = m; + "VAUXN[12]" : vauxn_idx[12] = m; + "VAUXN[13]" : vauxn_idx[13] = m; + "VAUXN[14]" : vauxn_idx[14] = m; + "VAUXN[15]" : vauxn_idx[15] = m; + "VP" : vp_index = m; + "VAUXP[0]" : vauxp_idx[0] = m; + "VAUXP[1]" : vauxp_idx[1] = m; + "VAUXP[2]" : vauxp_idx[2] = m; + "VAUXP[3]" : vauxp_idx[3] = m; + "VAUXP[4]" : vauxp_idx[4] = m; + "VAUXP[5]" : vauxp_idx[5] = m; + "VAUXP[6]" : vauxp_idx[6] = m; + "VAUXP[7]" : vauxp_idx[7] = m; + "VAUXP[8]" : vauxp_idx[8] = m; + "VAUXP[9]" : vauxp_idx[9] = m; + "VAUXP[10]" : vauxp_idx[10] = m; + "VAUXP[11]" : vauxp_idx[11] = m; + "VAUXP[12]" : vauxp_idx[12] = m; + "VAUXP[13]" : vauxp_idx[13] = m; + "VAUXP[14]" : vauxp_idx[14] = m; + "VAUXP[15]" : vauxp_idx[15] = m; + "VUSER0" : vuser0_index = m; + "VUSER1" : vuser1_index = m; + "VUSER2" : vuser2_index = m; + "VUSER3" : vuser3_index = m; + default : begin + $display("Error: [Unisim %s-5] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label); + infile_format; + end + endcase + end // for (m = 0; m < num_arg; m = m +1) + + + end // Getting labels + + // Getting column values + else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + column_real0 = 0.0; + column_real1 = 0.0; + column_real2 = 0.0; + column_real3 = 0.0; + column_real4 = 0.0; + column_real5 = 0.0; + column_real6 = 0.0; + column_real7 = 0.0; + column_real8 = 0.0; + column_real9 = 0.0; + column_real10 = 0.0; + column_real11 = 0.0; + column_real12 = 0.0; + column_real13 = 0.0; + column_real14 = 0.0; + column_real15 = 0.0; + column_real16 = 0.0; + column_real17 = 0.0; + column_real18 = 0.0; + column_real19 = 0.0; + column_real20 = 0.0; + column_real21 = 0.0; + column_real22 = 0.0; + column_real23 = 0.0; + column_real24 = 0.0; + column_real25 = 0.0; + column_real26 = 0.0; + column_real27 = 0.0; + column_real28 = 0.0; + column_real29 = 0.0; + column_real30 = 0.0; + column_real31 = 0.0; + column_real32 = 0.0; + column_real33 = 0.0; + column_real34 = 0.0; + column_real35 = 0.0; + column_real36 = 0.0; + column_real37 = 0.0; + column_real38 = 0.0; + column_real39 = 0.0; + column_real40 = 0.0; + column_real41 = 0.0; + column_real42 = 0.0; + column_real43 = 0.0; + column_real44 = 0.0; + column_real45 = 0.0; + column_real46 = 0.0; + + num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46); + + column_real[0] = $realtobits(column_real0); + column_real[1] = $realtobits(column_real1); + column_real[2] = $realtobits(column_real2); + column_real[3] = $realtobits(column_real3); + column_real[4] = $realtobits(column_real4); + column_real[5] = $realtobits(column_real5); + column_real[6] = $realtobits(column_real6); + column_real[7] = $realtobits(column_real7); + column_real[8] = $realtobits(column_real8); + column_real[9] = $realtobits(column_real9); + column_real[10] = $realtobits(column_real10); + column_real[11] = $realtobits(column_real11); + column_real[12] = $realtobits(column_real12); + column_real[13] = $realtobits(column_real13); + column_real[14] = $realtobits(column_real14); + column_real[15] = $realtobits(column_real15); + column_real[16] = $realtobits(column_real16); + column_real[17] = $realtobits(column_real17); + column_real[18] = $realtobits(column_real18); + column_real[19] = $realtobits(column_real19); + column_real[20] = $realtobits(column_real20); + column_real[21] = $realtobits(column_real21); + column_real[22] = $realtobits(column_real22); + column_real[23] = $realtobits(column_real23); + column_real[24] = $realtobits(column_real24); + column_real[25] = $realtobits(column_real25); + column_real[26] = $realtobits(column_real26); + column_real[27] = $realtobits(column_real27); + column_real[28] = $realtobits(column_real28); + column_real[29] = $realtobits(column_real29); + column_real[30] = $realtobits(column_real30); + column_real[31] = $realtobits(column_real31); + column_real[32] = $realtobits(column_real32); + column_real[33] = $realtobits(column_real33); + column_real[34] = $realtobits(column_real34); + column_real[35] = $realtobits(column_real35); + column_real[36] = $realtobits(column_real36); + column_real[37] = $realtobits(column_real37); + column_real[38] = $realtobits(column_real38); + column_real[39] = $realtobits(column_real39); + column_real[40] = $realtobits(column_real40); + column_real[41] = $realtobits(column_real41); + column_real[42] = $realtobits(column_real42); + column_real[43] = $realtobits(column_real43); + column_real[44] = $realtobits(column_real44); + column_real[45] = $realtobits(column_real45); + column_real[46] = $realtobits(column_real46); + + chan_val[0] = column_real[temperature_index]; + chan_val[1] = column_real[vccint_index]; + chan_val[2] = column_real[vccaux_index]; + chan_val[3] = column_real[vp_index]; + chan_val[6] = column_real[vccbram_index]; + chan_val[13] = column_real[vccpint_index]; + chan_val[14] = column_real[vccpaux_index]; + chan_val[15] = column_real[vccpdro_index]; + chan_val[16] = column_real[vauxp_idx[0]]; + chan_val[17] = column_real[vauxp_idx[1]]; + chan_val[18] = column_real[vauxp_idx[2]]; + chan_val[19] = column_real[vauxp_idx[3]]; + chan_val[20] = column_real[vauxp_idx[4]]; + chan_val[21] = column_real[vauxp_idx[5]]; + chan_val[22] = column_real[vauxp_idx[6]]; + chan_val[23] = column_real[vauxp_idx[7]]; + chan_val[24] = column_real[vauxp_idx[8]]; + chan_val[25] = column_real[vauxp_idx[9]]; + chan_val[26] = column_real[vauxp_idx[10]]; + chan_val[27] = column_real[vauxp_idx[11]]; + chan_val[28] = column_real[vauxp_idx[12]]; + chan_val[29] = column_real[vauxp_idx[13]]; + chan_val[30] = column_real[vauxp_idx[14]]; + chan_val[31] = column_real[vauxp_idx[15]]; + chan_val[32] = column_real[vuser0_index]; + chan_val[33] = column_real[vuser1_index]; + chan_val[34] = column_real[vuser2_index]; + chan_val[35] = column_real[vuser3_index]; + + chan_valn[3] = column_real[vn_index]; + chan_valn[16] = column_real[vauxn_idx[0]]; + chan_valn[17] = column_real[vauxn_idx[1]]; + chan_valn[18] = column_real[vauxn_idx[2]]; + chan_valn[19] = column_real[vauxn_idx[3]]; + chan_valn[20] = column_real[vauxn_idx[4]]; + chan_valn[21] = column_real[vauxn_idx[5]]; + chan_valn[22] = column_real[vauxn_idx[6]]; + chan_valn[23] = column_real[vauxn_idx[7]]; + chan_valn[24] = column_real[vauxn_idx[8]]; + chan_valn[25] = column_real[vauxn_idx[9]]; + chan_valn[26] = column_real[vauxn_idx[10]]; + chan_valn[27] = column_real[vauxn_idx[11]]; + chan_valn[28] = column_real[vauxn_idx[12]]; + chan_valn[29] = column_real[vauxn_idx[13]]; + chan_valn[30] = column_real[vauxn_idx[14]]; + chan_valn[31] = column_real[vauxn_idx[15]]; + + + // identify columns + if (time_index != -1) begin + prev_time_out = time_out; + time_out = $bitstoreal(column_real[time_index]); + if (prev_time_out > time_out) begin + $display("Error: [Unisim %s-6] Time value %f is invalid in the input file. Time value should be increasing. Instance: %m", MODULE_NAME, time_out); + infile_format; + end + end + else begin + $display("Error: [Unisim %s-7] No TIME label is found in the analog data file. Instance: %m", MODULE_NAME); + infile_format; + #1 $finish; + end + + # ((time_out - prev_time_out) * 1000); + + for (p = 0; p < CONV_CNT_P; p = p + 1) begin + // assign to real before minus - to work around a bug in modelsim + chan_val_tmp[p] = chan_val[p]; + chan_valn_tmp[p] = chan_valn[p]; + mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]); + mn_in_diff[p] = $realtobits(mn_in_tmp); + mn_in_uni[p] = chan_val[p]; + end + end // if (char_1 == "0" | char_1 == "9") + // Ignore any non-comment, label + else begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + end + end // while (end_file == 0) + + + end // if (sim_file_flag == 0) + end // initial begin + + // Obtain I2C slave address powerup value + always @(posedge trig_i2c_addr) begin + i2c_vpvn_addr_tmp = $bitstoreal(mn_in_uni[3]) * 65536.0; + if (i2c_vpvn_addr_tmp > 65535.0) + i2c_conv_result_int = 65535; + else if (i2c_vpvn_addr_tmp < 0.0) + i2c_conv_result_int = 0; + else begin + i2c_conv_result_int = $rtoi(i2c_vpvn_addr_tmp); + if (i2c_vpvn_addr_tmp - i2c_conv_result_int > 0.9999) + i2c_conv_result_int = i2c_conv_result_int + 1; + end + // I2C address measured and assigned at startup is recorded at address 38h + conv_result_i2c_addr = i2c_conv_result_int; + if(!i2c_oride) + data_reg[56] = i2c_conv_result_int; + + + // convert i2c address + case (conv_result_i2c_addr[15:12]) + 4'h0 : i2c_device_addr_vpvn = 7'b0110010; + 4'h1 : i2c_device_addr_vpvn = 7'b0001011; + 4'h2 : i2c_device_addr_vpvn = 7'b0010011; + 4'h3 : i2c_device_addr_vpvn = 7'b0011011; + 4'h4 : i2c_device_addr_vpvn = 7'b0100011; + 4'h5 : i2c_device_addr_vpvn = 7'b0101011; + 4'h6 : i2c_device_addr_vpvn = 7'b0110011; + 4'h7 : i2c_device_addr_vpvn = 7'b0111011; + 4'h8 : i2c_device_addr_vpvn = 7'b1000011; + 4'h9 : i2c_device_addr_vpvn = 7'b1001011; + 4'ha : i2c_device_addr_vpvn = 7'b1010011; + 4'hb : i2c_device_addr_vpvn = 7'b1011011; + 4'hc : i2c_device_addr_vpvn = 7'b1100011; + 4'hd : i2c_device_addr_vpvn = 7'b1101011; + 4'he : i2c_device_addr_vpvn = 7'b1110011; + 4'hf : i2c_device_addr_vpvn = 7'b0111010; + default : begin + i2c_device_addr_vpvn = 7'b0000000; + //$display("Warning: [Unisim %s-25] Invalid I2C address is found. Instance: %m", MODULE_NAME); + end + endcase + end + + task infile_format; + begin + $display("\n***** SYSMONE1 Simulation analog Data File Format *****\n"); + $display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n"); + $display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VCCBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] ..... \n"); + $display("TIME must be in first column.\n"); + $display("Time values need to be integer in ns scale.\n"); + $display("Analog values need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n"); + $display("Each line including header line can not have extra space after the last character/digit.\n"); + $display("Each data line must have the same number of columns as the header line.\n"); + $display("Comment line can start with -- or //\n"); + $display("Example:\n"); + $display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n"); + $display("000 125.6 1.0 0.7 0.4 0.3 0.6\n"); + $display("200 25.6 0.8 0.5 0.3 0.8 0.2\n"); + end + endtask //task infile_format + + function [12*8:1] to_upcase_label; + input [12*8:1] in_label; + reg [8:1] tmp_reg; + begin + for (i=0; i< 12; i=i+1) begin + for (j=1; j<=8; j= j+1) + tmp_reg[j] = in_label[i*8+j]; + if ((tmp_reg >96) && (tmp_reg<123)) + tmp_reg = tmp_reg -32; + for (j=1; j<=8; j= j+1) + to_upcase_label[i*8+j] = tmp_reg[j]; + end + end + endfunction + + // end read input file + + // Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only + always @( posedge busy_r ) begin + if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin + chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]); + chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]); + + if ( chan_val_n_tmp > chan_val_p_tmp) + $display("Warning: [Unisim %s-8] The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0) + $display("Warning: [Unisim %s-9] The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, acq_chan, chan_val_n_tmp, $time/1000.0); + end + end + + reg seq_reset_busy_out = 0; + wire rst_in_out; + + always @(posedge DCLK_in or posedge rst_in_out) begin + if (rst_in_out) begin + busy_rst <= 1; + rst_lock <= 1; + rst_lock_early <= 1; + rst_lock_late <= 1; + busy_rst_cnt <= 0; + end + else begin + if (rst_lock == 1) begin + if (busy_rst_cnt < 29) begin + busy_rst_cnt <= busy_rst_cnt + 1; + if ( busy_rst_cnt == 26) + rst_lock_early <= 0; + end + else begin + busy_rst <= 0; + rst_lock = 0; + end + end + if (BUSY_out == 0) + rst_lock_late <= 0; + end + end + + initial begin + BUSY_out = 0; + busy_rst = 0; + busy_conv = 0; + busy_seq_rst = 0; + end + + always @(busy_rst or busy_conv or rst_lock) begin + if (rst_lock) + BUSY_out = busy_rst; + else + BUSY_out = busy_conv; + end + + always @(posedge DCLK_in or posedge rst_in) begin + if (rst_in) begin + busy_conv <= 0; + end + else begin + if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03) + busy_conv <= busy_seq_rst; + else if (busy_sync_fall) + busy_conv <= 0; + else if (busy_sync_rise) + busy_conv <= 1; + end + end + + always @(posedge DCLK_in or posedge rst_in) begin + if (rst_in) + cal_chan_update <= 0; + else begin + if (conv_count == CONV_CAL_PER_5 && curr_chan == 6'd8) + cal_chan_update <= 1; + else + cal_chan_update <= 0; + end + end + + //always @(posedge adcclk or rst_lock) + always @(posedge DCLK_in or rst_lock) begin + if (rst_lock) begin + busy_sync1 <= 0; + busy_sync2 <= 0; + end + else begin + busy_sync1 <= busy_r; + busy_sync2 <= busy_sync1; + end + end + + assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0; + assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0; + + always @(negedge BUSY_out or posedge busy_r) + if (seq_reset_flag == 1 && default_mode && curr_clkdiv_sel <= 8'h03) begin + repeat (5) @(posedge DCLK_in); + busy_seq_rst <= 1; + end + else if (seq_reset_flag == 1 && !default_mode && curr_clkdiv_sel <= 8'h03) begin + repeat (7) @(posedge DCLK_in); + busy_seq_rst <= 1; + end + else + busy_seq_rst <= 0; + + //assign muxaddr_o = (rst_lock_early) ? 5'b0 : (curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0 || sysmone12_en == 1) ? acq_chan_m : 5'b0; + + always @(posedge adcclk or posedge RESET_in ) begin + if (RESET_in) + MUXADDR_out <= 5'b0; + else begin + if(ext_mux_en &&(curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0 || sysmone12_en == 1)) + MUXADDR_out <= acq_chan_m; + else + MUXADDR_out <= 5'b0; + end + end + + always @(negedge BUSY_out or posedge BUSY_out or posedge rst_in_out or posedge cal_chan_update ) + if (rst_in_out || rst_lock_late) + CHANNEL_out <= 5'd0; + else if (BUSY_out ==1 && (cal_chan_update == 1) ) + CHANNEL_out <= 6'd8; + else if (BUSY_out == 0) begin + if ((curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0) || sysmone12_en == 1) + CHANNEL_out <= curr_chan; + else + CHANNEL_out <= 5'b0; + curr_chan_lat <= curr_chan; + averaging_d <= averaging; + end + + + // START double latch rst_in + + reg rst_in1_tmp6; + reg rst_in2_tmp6; + wire RESET_in_t; + wire rst_in2; + + initial begin + int_rst = 1; + repeat (2) @(posedge DCLK_in); + int_rst <= 0; + end + + initial begin + rst_in1_tmp6 = 0; + rst_in2_tmp6 = 0; + end + + assign #1 RESET_in_t = int_rst_halt_adc | RESET_in | int_rst | soft_reset | gsr_in; + + + always@(posedge adcclk or posedge RESET_in_t) + if (RESET_in_t) begin + rst_in2_tmp6 <= 1; + rst_in1_tmp6 <= 1; + end + else begin + rst_in2_tmp6 <= rst_in1_tmp6; + rst_in1_tmp6 <= RESET_in_t; + end + + assign rst_in2 = rst_in2_tmp6; + assign #10 rst_in_not_seq = rst_in2; + assign rst_in = rst_in_not_seq | seq_reset_dly; + assign rst_in_out = rst_in_not_seq | seq_reset_busy_out; + + always @(posedge seq_reset) begin + repeat (2) @(posedge DCLK_in); + seq_reset_dly = 1; + repeat (2) @(negedge DCLK_in); + seq_reset_busy_out = 1; + repeat (3) @(posedge DCLK_in); + seq_reset_dly = 0; + seq_reset_busy_out = 0; + end + + always @(posedge seq_reset_dly or posedge busy_r) + if (seq_reset_dly) + seq_reset_flag <= 1; + else + seq_reset_flag <= 0; + + always @(posedge seq_reset_flag or posedge BUSY_out) + if (seq_reset_flag) + seq_reset_flag_dly <= 1; + else //if(!CHANNEL_out==6'd8) + seq_reset_flag_dly <= 0; + + always @(posedge BUSY_out ) + if (seq_reset_flag_dly == 1 && acq_chan == 6'd8 && default_mode ) + first_cal_chan <= 1; + else + first_cal_chan <= 0; + + + + initial begin + sysclk = 0; + adcclk_tmp = 0; + seq_count = 1; + seq_count_a = 1; + eos_en = 0; + eos_tmp_en = 0; + clk_count = -1; + acq_acqsel = 0; + acq_e_c_tmp6 = 0; + acq_e_c_tmp5 = 0; + eoc_en = 0; + eoc_en_delay = 0; + rst_lock = 0; + rst_lock_early = 0; + alm_update = 0; + drp_update = 0; + cal_chan_update = 0; + adc_state = S3_ST; + scon_tmp = 0; + busy_r = 0; + busy_r_rst = 0; + busy_sync1 = 0; + busy_sync2 = 0; + conv_count = 0; + conv_end = 0; + seq_status_avg = 0; + for (i = 0; i <=63; i = i +1) begin + conv_avg_count[i] = 0; + conv_acc[i] = 0; + end + single_pass_finished = 0; + for (k = 0; k <= 31; k = k + 1) begin + data_reg[k] = 16'b0; + end + seq_count_en = 0; + EOS_out_tmp = 0; + EOC_out_tmp = 0; + EOS_out_tmp1 = 0; + EOC_out_tmp1 = 0; + EOS_out = 0; + EOC_out = 0; + EOC_out_pre = 0; + EOC_out_pre2 = 0; + averaging = 0; + averaging_d = 0; + curr_e_c = 0; + curr_b_u = 0; + curr_acq = 0; + curr_seq1_0 = 0; + curr_seq1_0_lat = 0; + DADDR_in_lat = 0; + //min and max registers' reset value assignments + data_reg[32] = 16'h0000; + data_reg[33] = 16'h0000; + data_reg[34] = 16'h0000; + data_reg[35] = 16'h0000; + data_reg[36] = 16'hFFFF; + data_reg[37] = 16'hFFFF; + data_reg[38] = 16'hFFFF; + data_reg[39] = 16'hFFFF; + data_reg[40] = 16'h0000; + data_reg[41] = 16'h0000; + data_reg[42] = 16'h0000; + data_reg[43] = 16'h0000; //reserved + data_reg[44] = 16'hFFFF; + data_reg[45] = 16'hFFFF; + data_reg[46] = 16'hFFFF; + data_reg[47] = 16'h0000; //reserved + + ot_out_reg = 0; + OT_out = 0; + alm_out_reg = 0; + ALM_out = 0; + curr_chan = 'd0; + acq_chan = 'd0; + acq_chan_m = 'd0; + curr_chan_lat = 'd0; + BUSY_out = 0; + curr_seq = 0; + curr_seq_m = 0; + hr_tot_chan = 0; + seq_reset_flag_dly = 0; + seq_reset_flag = 0; + seq_reset_dly = 0; + ot_en = 1; + alm_en = 13'h1FFF; + DO_out_rdtmp = 0; + acq_b_u = 0; + conv_result_int = 0; + conv_result = 0; + conv_result_reg = 0; + reserved_addr_pre = 0; + end + + + // state machine + always @(posedge adcclk or posedge rst_in or sim_file_flag) begin + //CR 675227 + if (!(halt_adc == 2 && single_chan_mode )) begin + if (sim_file_flag == 1'b1) + adc_state <= S0_ST; + else if (rst_in == 1'b1 || rst_lock_early == 1) + adc_state <= S0_ST; + else if (rst_in == 1'b0) + adc_state <= adc_next_state; + end + end + + always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin + case (adc_state) + S0_ST : adc_next_state = S2_ST; + + S2_ST : if (conv_start) + adc_next_state = S3_ST; + else + adc_next_state = S2_ST; + + S3_ST : if (conv_end) + adc_next_state = S5_ST; + else + adc_next_state = S3_ST; + + S5_ST : if (curr_seq1_0_lat == SEQ_SINGLE_PASS ) begin + //CR 675227 if (eos_en) + if (eos_tmp_en) + adc_next_state = S1_ST; + else + adc_next_state = S2_ST; + end + else + adc_next_state = S2_ST; + + S1_ST : adc_next_state = S0_ST; + + default : + adc_next_state = S0_ST; + + endcase // case(adc_state) + + end + +// end state machine + + +// DRPORT - SRAM + initial begin + DRDY_out = 0; + DRDY_out_tmp1 = 0; + DRDY_out_tmp2 = 0; + DRDY_out_tmp3 = 0; + en_data_flag = 0; + DO_out = 16'b0; + seq_reset = 0; + cfg_reg1_init = INIT_41_BIN; + seq_en = 0; + seq_en_dly = 0; + seq_en <= #20 (cfg_reg1_init[15:12] != 4'b0011 ) ? 1 : 0; + seq_en <= #150 0; + end + + always @(posedge DRDY_out_tmp3 or posedge gsr_in) begin + if (gsr_in == 1) + DRDY_out <= 0; + else begin + @(posedge DCLK_in) + DRDY_out <= 1; + @(posedge DCLK_in) + DRDY_out <= 0; + end + end + + function is_reserved_address; + input [7:0] address_in; + reg is_reserved_address_pre; + begin + + is_reserved_address_pre = ((address_in >= 8'h07 && address_in <= 8'h0F) || + (address_in >= 8'h28 && address_in <= 8'h37) || + (address_in >= 8'h39 && address_in <= 8'h3D) || + (address_in >= 8'h44 && address_in <= 8'h45) || + (address_in >= 8'h58 && address_in <= 8'h5F) || + (address_in >= 8'h64 && address_in <= 8'h67) || + (address_in >= 8'h6C && address_in <= 8'h7F) || + (address_in >= 8'h84 && address_in <= 8'h9F) || + (address_in >= 8'hA4 && address_in <= 8'hA7) || + (address_in >= 8'hAC && address_in <= 8'hFF) + ); + if(is_reserved_address_pre) + $display("Warning: [Unisim %s-11] The input address=h%x at time %.3f ns is accessing a RESERVED location. The data in this location is invalid. Instance: %m", MODULE_NAME, address_in, $time/1000.0); + is_reserved_address = is_reserved_address_pre; + end + endfunction + + function is_readonly_address; + input [7:0] address_in; + reg is_readonly_address_pre; + begin + + is_readonly_address_pre = ((address_in <= 8'h3F) || + (address_in >= 8'h80 && address_in <= 8'hAB) + ); + if(is_readonly_address_pre) + $display("Warning: [Unisim %s-19] The input address=h%x at time %.3f ns is accessing a READ ONLY location. The data won't be written. Instance: %m", MODULE_NAME, address_in, $time/1000.0); + is_readonly_address = is_readonly_address_pre; + end + endfunction + + always @(posedge DCLK_in or posedge gsr_in) begin + if (gsr_in == 1) begin + DADDR_in_lat <= 8'b0; + DO_out <= 16'b0; + end + else begin + if (DEN_in == 1'b1) begin + if (DRDY_out_tmp1 == 1'b0) begin + DRDY_out_tmp1 <= 1'b1; + en_data_flag = 1; + DADDR_in_lat <= DADDR_in; + end + else if (DADDR_in != DADDR_in_lat) + $display("Warning: [Unisim %s-10] Input pin DEN at time %.3f ns can not be continuously set to high. Please wait for DRDY to be high and then set DEN to high again. Instance: %m", MODULE_NAME, $time/1000.0); + end // if (DEN_in == 1'b1) + else + DRDY_out_tmp1 <= 1'b0; + + DRDY_out_tmp2 <= DRDY_out_tmp1; + DRDY_out_tmp3 <= DRDY_out_tmp2; + + if (DRDY_out_tmp1 == 1) + en_data_flag = 0; + + if (DRDY_out_tmp3 == 1) begin + DO_out <= DO_out_rdtmp; + end + + if (DEN_in == 1 && is_reserved_address(DADDR_in) ) + reserved_addr_pre <= 1; + else if (DWE_in == 1'b1 && DEN_in == 1'b1 && en_data_flag == 1) begin + //write to all available and writable addresses. + dr_sram[DADDR_in] <= DI_in; + //check write access + if (is_readonly_address(DADDR_in)) + read_only_pre <= 1; + else begin + read_only_pre <= 0; + + // post processing after DRP write + if (DADDR_in == 8'h03) + soft_reset <= 1; + else if ( DADDR_in == 8'h53 && DI_in[3:0] == 4'b0011) + ot_limit_reg[15:4] <= DI_in[15:4]; + else if (DADDR_in == 8'h41 ) begin // && en_data_flag == 1) begin is above + //if (DEN_in == 1'b1 && DWE_in == 1'b1) begin + if (DI_in[15:12] != cfg_reg1[15:12]) // writing with the same seq[3:0] will not restart the sequence, matching with hw + seq_reset <= 1'b1; + else + seq_reset <= 1'b0; + + if (DI_in[15:12] != SEQ_SINGLE_CHAN) + seq_en <= 1'b1; + else + seq_en <= 1'b0; + end //DADDR_in == 8'h41 + end // not read only + end // dwe ==1 + + if (seq_en == 1) + seq_en <= 1'b0; + if (seq_reset == 1) + seq_reset <= 1'b0; + if (soft_reset == 1) + soft_reset <= 0; + + end // if (gsr == 1) + end //always + + reg display_configuration_warnings; + reg [7:0] cfg_check_addr; + always @(posedge DCLK_in or posedge rst_in) begin + if(rst_in) begin + display_configuration_warnings <= 0; + cfg_check_addr <= 0; + end + else begin + if(DEN_in && DWE_in) begin + display_configuration_warnings <= 1; + cfg_check_addr <= DADDR_in; + end + else begin + display_configuration_warnings <= 0; + cfg_check_addr <= 0; + end + end + end + + always @(posedge display_configuration_warnings) begin + if(cfg_check_addr == 8'h40) + if (cfg_reg0[5:0] == 6'd7 || (cfg_reg0[5:0] >= 6'd9 && cfg_reg0[5:0] <= 6'd12) || cfg_reg0[5:0] >= 6'd36) + $display("Warning: [Unisim %s-14] Config register 0 bits [5:0] at 40h cannot not be set to an invalid analog channel value as %0b. Instance: %m", MODULE_NAME, cfg_reg0[5:0], $time/1000.0,); + if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41) + if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[8]==1) && (cfg_reg0[5:0] != 6'd3) && (cfg_reg0[5:0] < 6'd16)) + $display("Warning: [Unisim %s-15] In single channel mode if the selected channel is not analog, config register 0 bit[8] must be set to 0. Long acqusition mode is only allowed for external channels, not in single channel mode. Instance: %m", MODULE_NAME, DI_in, DADDR_in, $time/1000.0); + if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41|| cfg_check_addr==8'h46|| cfg_check_addr==8'h48|| cfg_check_addr==8'h49) + if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000) && (seq_chan_reg3 != 16'h0000)) + $display("Warning: [Unisim %s-16] In single channel mode, ADC channel selection registers 46h, 48h and 49h must be set to 0, these are set to %x, %x and %x respectively. Averaging must be enabled. Instance: %m", MODULE_NAME, seq_chan_reg3, seq_chan_reg1, seq_chan_reg2, $time/1000.0); + if(cfg_check_addr == 8'h4E || cfg_check_addr==8'h41) + if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4E][10:0]!=11'd0) || (dr_sram['h4E][15:12]!=4'd0))) + $display("Warning: [Unisim %s-18] The Control Register 4Eh value set is to %x. Bits [15:12] and [10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0); + if(cfg_check_addr == 8'h42) + if (cfg_reg2[4]==1) + $display("Warning: [Unisim %s-12] The config reg 2 =%x is invalid. Bit [4] must be set to 0. Instance: %m", MODULE_NAME, cfg_reg2, $time/1000.0); + if(cfg_check_addr == 8'h43) + if (cfg_reg3[3:0]!=4'd0) + $display("Warning: [Unisim %s-17] The config reg 3 =%x is invalid. Bits [3:0] must be set to 000. Instance: %m", MODULE_NAME, cfg_reg3, $time/1000.0); + // CR1004434 + if (cfg_check_addr == 8'h40 || cfg_check_addr ==8'h41) + if (((cfg_reg1[15:12]==4'b0001|| cfg_reg1[15:12]==4'b0010) && dr_sram['h46][3:0]!=4'b0000) || //single pass or cont mode and vuser selected + (cfg_reg1[15:12]==4'b0011 && cfg_reg0[5:2]==4'b1000) ) //single channel mode and vuser is selected + $display("Warning: [Unisim %s-178] The control registers 40h and 41h are set to %x and %x respectively. VUSER is selected. In Kintex devices, SYSMONE1 model has no way of knowing whether VUSER has a 6V range or a 3V range and assumes all channels have 3V range. If 6V banks are selected, the value stored in the model's registers will be different than that of the actual hardware. Instance: %m", + MODULE_NAME, cfg_reg0, cfg_reg1 ); + end + + + // DO bus data out + + assign flag_reg0 = {8'b0, ALM_out[6:3], OT_out, ALM_out[2:0]}; + assign flag_reg1 = {10'b0, ALM_out[13:8]}; + + always @(*) begin + reserved_addr_pre = is_reserved_address(DADDR_in_lat); + if(reserved_addr_pre) + DO_out_rdtmp = 16'b0; + else begin //readable addresses + if ( DADDR_in_lat <= 8'h3D) + DO_out_rdtmp = data_reg[DADDR_in_lat]; + else if (DADDR_in_lat == 8'h3E) + DO_out_rdtmp = flag_reg1; + else if (DADDR_in_lat == 8'h3F) + DO_out_rdtmp = flag_reg0; + else + DO_out_rdtmp = dr_sram[DADDR_in_lat]; + end + end + +// end DRP RAM + + + assign cfg_reg0 = dr_sram[8'h40]; + assign cfg_reg1 = dr_sram[8'h41]; + assign cfg_reg2 = dr_sram[8'h42]; + assign cfg_reg3 = dr_sram[8'h43]; + assign seq_chan_reg1 = dr_sram[8'h48]; + assign seq_chan_reg2 = dr_sram[8'h49]; + assign seq_chan_reg3 = dr_sram[8'h46]; + assign seq_avg_reg1 = dr_sram[8'h4A]; + assign seq_avg_reg2 = dr_sram[8'h4B]; + assign seq_avg_reg3 = dr_sram[8'h47]; + assign seq_bu_reg1 = dr_sram[8'h4C]; + assign seq_bu_reg2 = dr_sram[8'h4D]; + assign seq_bu_reg3 = dr_sram[8'h78]; + assign seq_acq_reg1 = dr_sram[8'h4E]; + assign seq_acq_reg2 = dr_sram[8'h4F]; + assign seq_acq_reg3 = dr_sram[8'h79]; + + + assign seq1_0 = cfg_reg1[15:12]; + assign default_mode = (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11); + assign single_pass_mode = (seq1_0 == 4'b0001); + assign cont_seq_mode = (seq1_0 == 4'b0010); + assign single_chan_mode = (seq1_0 == 4'b0011); + assign ext_mux_chan = cfg_reg0[5:0]; + assign ext_mux_en = cfg_reg0[11]; // && (~default_mode) ?? + + always @(posedge drp_update or posedge rst_in) begin + if (rst_in) begin + repeat (2) @(posedge DCLK_in); + seq_bits = seq1_0; + end + else begin + seq_bits = curr_seq1_0; + if (seq_bits == SEQ_DEFAULT_MODE) begin + alm_en <= 'd0; + ot_en <= 1; + end + else begin + ot_en <= ~cfg_reg1[0]; + alm_en[2:0] <= ~cfg_reg1[3:1]; + alm_en[6:3] <= ~cfg_reg1[11:8]; + alm_en[11:8] <= ~cfg_reg3[3:0]; //TODO check this with UG + end + end + end + + //--------------------- end DRPORT - sram + + //---- I2C logic start ---------------------------------------------------- + parameter ST_I2C_IDLE = 2'd0, + ST_I2C_GET_ADDR = 2'd1, + ST_I2C_GET_CMD = 2'd2, + ST_I2C_READ = 2'd3; + + localparam I2C_DRP_RD = 4'b0001; // read + localparam I2C_DRP_WR = 4'b0010; // write + localparam I2C_DRP_NO = 4'b0000; // no operation + + + + reg [1:0] i2c_state; + reg i2c_start; + reg i2c_start_reset; + reg i2c_stop; + reg i2c_stop_reset; + reg [3:0] i2c_bit_counter; + reg [2:0] i2c_byte_counter; + wire i2c_lsb_bit; + wire i2c_ack_bit; + wire [15:0] i2c_drp_data; + wire [9:0] i2c_drp_addr; + wire [3:0] i2c_drp_cmd ; + reg [31:0] i2c_cmd_in; + reg [7:0] i2c_data_in; + wire i2c_addr_match; + wire i2c_addr_match_wop; + wire i2c_rw_bit; + wire i2c_rd_cmd_pre; + reg i2c_rd_cmd; + reg i2c_ack_in; //ack from master to slave, negated. + wire i2c_cmd_end; + wire i2c_rd_end; + reg i2c_cmd_received; + reg [15:0] i2c_data_out; + wire i2c_wr_exec; + + assign i2c_addr_match = (i2c_data_in[7:1]==i2c_device_addr[6:0]) ? 1 : 0; + assign i2c_addr_match_wop = i2c_addr_match; + + + always @(posedge RESET_in or posedge i2c_start_reset or negedge I2C_SDA_in) begin + if(RESET_in || i2c_start_reset) + i2c_start <= 1'b0; + else + i2c_start <= I2C_SCLK_in; + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_start_reset <= 1'b0; + else + i2c_start_reset <= i2c_start; + end + + always @(posedge RESET_in or posedge i2c_stop_reset or posedge I2C_SDA_in) begin + if(RESET_in || i2c_stop_reset) + i2c_stop <= 1'b0; + else + i2c_stop <= I2C_SCLK_in; + end + + always @(posedge RESET_in or posedge i2c_stop) begin + if(RESET_in) + i2c_stop_reset = 1'b0; + else begin + repeat (16) @(posedge DCLK_in); + i2c_stop_reset = 1; + repeat (16) @(posedge DCLK_in); + i2c_stop_reset = 0; + end + end + + assign i2c_lsb_bit = (i2c_bit_counter== 4'd7) && ~i2c_start; + assign i2c_ack_bit = (i2c_bit_counter== 4'd8) && ~i2c_start; + + always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_start) begin + if(RESET_in || i2c_start) + i2c_bit_counter <= 'd0; + else begin + if (i2c_ack_bit) + i2c_bit_counter <= 'd0; + else + i2c_bit_counter <= i2c_bit_counter + 'd1; + end + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_data_in <= 'd0; + else if(!i2c_ack_bit) + i2c_data_in <= {i2c_data_in[6:0],I2C_SDA_in} ; + end + + assign i2c_drp_data = i2c_cmd_in[15:0]; + assign i2c_drp_addr = i2c_cmd_in[25:16]; + assign i2c_drp_cmd = i2c_cmd_in[29:26]; + + + always @(posedge I2C_SCLK_in) begin + //if(RESET_in) + // i2c_cmd_in <= 'd0; + //else if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD ) + if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD ) + i2c_cmd_in <= {i2c_data_in,i2c_cmd_in[31:8]} ; + end + assign i2c_rd_cmd_pre = i2c_rw_bit && I2C_SDA_in; + + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop) + i2c_rd_cmd <= 1'b0; + else begin + if (i2c_state==ST_I2C_IDLE) + i2c_rd_cmd <= 1'b0; + else if (i2c_rw_bit ) + i2c_rd_cmd <= i2c_data_in[0] ; + end + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_ack_in <= 'd0; + else if(i2c_ack_bit) + i2c_ack_in <= ~I2C_SDA_in; //ACK from master to slave, negated. + else if ((i2c_state==ST_I2C_IDLE) || i2c_bit_counter=='d1) + i2c_ack_in <= 0; + end + + assign i2c_cmd_end = i2c_ack_bit && (i2c_byte_counter==3'd3); + assign i2c_rd_end = i2c_ack_bit && (i2c_byte_counter==3'd1); + + always @(posedge RESET_in or posedge i2c_stop or posedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop) + i2c_cmd_received <= 0; + else if (i2c_cmd_end) + i2c_cmd_received <= 1; + else if (i2c_state==ST_I2C_READ) + i2c_cmd_received <= 0; + end + + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_start || i2c_stop) + i2c_byte_counter <= 0; + else if(i2c_ack_bit && (i2c_state == ST_I2C_GET_CMD || i2c_state == ST_I2C_READ )) + i2c_byte_counter <= i2c_byte_counter + 1; + end + + //I2C state machine. + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop)// && ~i2c_en) + i2c_state <= ST_I2C_IDLE; + else if(i2c_start) + i2c_state <= ST_I2C_GET_ADDR; + else if (i2c_ack_bit) + case (i2c_state) + ST_I2C_GET_ADDR : begin + if(!i2c_addr_match) begin + i2c_state <= ST_I2C_IDLE; + $display("Warning: [Unisim %s-54] I2C command address h%0X not matching the device address h%0X @time %0t", + MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time); + end + else if (~i2c_cmd_received) + i2c_state <= ST_I2C_GET_CMD; + else if(i2c_drp_cmd==I2C_DRP_RD) //if you received a command earlier, it had to be a drp read command. + i2c_state <= ST_I2C_READ; + else + i2c_state <= ST_I2C_IDLE; + end + ST_I2C_GET_CMD : begin + if (i2c_cmd_end) begin + i2c_state <= ST_I2C_IDLE; + $display("Info: [Unisim %s] I2C command received @time %0t", MODULE_NAME, $time); + end + end + ST_I2C_READ : begin + if(i2c_rd_end) + i2c_state <= ST_I2C_IDLE; + end + default : i2c_state <= ST_I2C_IDLE; + endcase + end + + //i2c write command execute + assign i2c_wr_exec = (i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR); + + always @(negedge I2C_SCLK_in) begin + if(!RESET_in) begin + if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR) + if(i2c_drp_addr>='h40) + dr_sram[i2c_drp_addr] <= i2c_drp_data; + //else + // data_reg[i2c_drp_addr] <= i2c_drp_data; + end + end + + //i2c read command execute + always @(negedge I2C_SCLK_in) begin + if(!RESET_in) begin + if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_RD && i2c_state==ST_I2C_GET_ADDR && !i2c_ack_bit) begin //fetch the data + if(i2c_drp_addr>='h40) + i2c_data_out <= dr_sram[i2c_drp_addr]; + else + i2c_data_out <= data_reg[i2c_drp_addr]; + end + else if(i2c_lsb_bit && i2c_state==ST_I2C_READ) + i2c_data_out <= {8'b0,i2c_data_out[15:8]};// shift the higher byte to lower. + else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out. + i2c_data_out <= {i2c_data_out[15:8],i2c_data_out[6:0],1'b0}; + end + end + + //Pull down SDA to transfer a zero to the master. + always@(posedge RESET_in or negedge I2C_SCLK_in) begin + if (RESET_in) + I2C_SDA_TS_out <= 1; + else begin + if (i2c_start) + I2C_SDA_TS_out <= 1; + else if (i2c_lsb_bit) //acknowledge the end of a 1 byte transfer from master + I2C_SDA_TS_out <= ! (((i2c_state==ST_I2C_GET_ADDR) && i2c_addr_match) || + ((i2c_state==ST_I2C_GET_CMD ) && !(i2c_rd_cmd && i2c_byte_counter=='d3)) //send NACK at the last byte of command, only if read command + ); + else if ((i2c_ack_bit && //first bit of next slave to master transfer + ((i2c_state==ST_I2C_GET_ADDR) && (i2c_drp_cmd==I2C_DRP_RD) )) || + (i2c_state==ST_I2C_READ && !i2c_rd_end)) //or read continued + I2C_SDA_TS_out <= i2c_data_out[7]; + else + I2C_SDA_TS_out <= 1; + end + end + + // clock stretching + assign I2C_SCLK_TS_out = 1'b1; + + //---- End of I2C logic ------------------------------------------------ + // Clock divider, generate and adcclk + + always @(posedge DCLK_in) + sysclk <= ~sysclk; + + always @(posedge DCLK_in ) begin + if (curr_clkdiv_sel > 'd2 || clk_count_rst) begin + if ((clk_count >= curr_clkdiv_sel-1) || clk_count_rst) + clk_count <= 0; + else + clk_count <= clk_count + 1; + + if(clk_count_rst) + adcclk_tmp <= 1; + //else if(clk_count <= curr_clkdiv_sel/2 -2) + else if(clk_count <= curr_clkdiv_sel/2 -1) //CR-1003761 + adcclk_tmp <= 1; + else + adcclk_tmp <= 0; + end + else + adcclk_tmp <= ~adcclk_tmp; + end + + wire adcclk_r; + + assign curr_clkdiv_sel = cfg_reg2[15:8]; + assign sysmone1_en = (cfg_reg2[5]===1 && cfg_reg2[4]===1) ? 0 : 1; + assign sysmone12_en = (cfg_reg2[5]===1 ) ? 0 : 1; + assign adcclk_div1 = (curr_clkdiv_sel > 'd2) ? 0 : 1; + assign adcclk_r = (adcclk_div1) ? ~sysclk : adcclk_tmp; + assign adcclk = (sysmone1_en) ? adcclk_r : 0; + + // end clock divider + + // latch configuration registers + wire [15:0] cfg_reg0_seq, cfg_reg0_adc; + reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5; + reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6; + reg [1:0] acq_avg; + + + + //always @( seq1_0 or single_pass_finished or curr_seq_m or cfg_reg0_adc or rst_in) begin + always @(*) begin + if (rst_in == 0) begin + if ( default_mode) //default mode + acq_chan_m = curr_seq_m[4:0]; + else if (cont_seq_mode || (single_pass_mode && !single_pass_finished)) //continuous mode or single pass active state + acq_chan_m = curr_seq_m[4:0]; + else //single pass mode deactive state or single channel mode + acq_chan_m = cfg_reg0_adc[4:0]; + end + end + + //CR 675227 always @( seq1_0 or single_pass_finished or curr_seq or cfg_reg0_adc or rst_in) begin + always @(*) begin + if ((single_pass_mode && !single_pass_finished) || + cont_seq_mode) //|| default_mode ) CR 927318: default mode doesn't support acq adjustability + acq_acqsel = curr_seq[8]; + else if (single_chan_mode) + acq_acqsel = cfg_reg0_adc[8]; + else + acq_acqsel = 0; + end + + always @(single_pass_finished or curr_seq or cfg_reg0_adc or rst_in) begin + if (rst_in == 0) begin + if (default_mode) begin // default mode + acq_avg = 2'b01; + acq_chan = curr_seq[5:0]; + acq_b_u = 0; + end + //else if (!single_chan_mode && single_pass_finished == 0) begin // either continuous or single pass mode + else if (cont_seq_mode || (single_pass_mode && !single_pass_finished)) begin // either continuous or active single pass mode + acq_avg = curr_seq[13:12]; + acq_chan = curr_seq[5:0]; + acq_b_u = curr_seq[10]; + end + else begin + acq_avg = cfg_reg0_adc[13:12]; + acq_chan = cfg_reg0_adc[5:0]; + acq_b_u = cfg_reg0_adc[10]; + + //CR 675227 + // CR 764936 if (seq1_0 == 4'b0001) begin + //when doing one pass when a CONVST BUSY should assert and then an EOC be seen, + //the user can assert a CONVST again without having to write to the sequence register to start the sequence again. + if (single_pass_mode && !acq_e_c) begin // if single pass and not event driven + halt_adc = halt_adc + 1; + if (halt_adc == 2) //need to wait for EOS. + dr_sram[8'h41][15:12] = SEQ_SINGLE_CHAN ;//4'b0011; //from single pass, go to single channel + end + end + end + end + + reg single_chan_conv_end; + reg [3:0] conv_end_reg_read; + reg busy_reg_read; + reg first_after_reset_tmp5; + reg first_after_reset_tmp6; + + always@(posedge adcclk or posedge rst_in) begin + if(rst_in) + conv_end_reg_read <= 4'b0; + else + conv_end_reg_read <= {conv_end_reg_read[2:0], (single_chan_conv_end | conv_end)}; + end + + always@(posedge DCLK_in or posedge rst_in) begin + if(rst_in) + busy_reg_read <= 1; + else + busy_reg_read <= ~conv_end_reg_read[2]; + end + +// i2c write + assign cfg_reg0_adc = (i2c_stop) ? cfg_reg0 : cfg_reg0_adc_tmp6; +// assign cfg_reg0_adc = cfg_reg0_adc_tmp6; + assign cfg_reg0_seq = cfg_reg0_seq_tmp6; + assign acq_e_c = acq_e_c_tmp6; + + always @(negedge BUSY_out or rst_in) + if(rst_in) begin + cfg_reg0_seq_tmp6 <= 16'b0; + cfg_reg0_adc_tmp6 <= 16'b0; + acq_e_c_tmp6 <= 0; + first_after_reset_tmp6 <= 1; + end + else begin + repeat(3) @(posedge DCLK); + if(first_after_reset_tmp6) begin + first_after_reset_tmp6<=0; + cfg_reg0_adc_tmp6 <= cfg_reg0; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + else begin + cfg_reg0_adc_tmp6 <= cfg_reg0_seq; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + acq_e_c_tmp6 <= cfg_reg0[9]; + end + + always @(posedge conv_start or posedge busy_r_rst or posedge rst_in) + if (rst_in ==1) + busy_r <= 0; + else if (conv_start && rst_lock == 0) + busy_r <= 1; + else if (busy_r_rst) + busy_r <= 0; + + always @(negedge BUSY_out ) + if (single_pass_finished == 1) //from single pass, go to single channel + if (curr_seq1_0 == SEQ_SINGLE_PASS || curr_seq1_0 == SEQ_SINGLE_CHAN) // CR 764936 + //when doing one pass when a CONVST BUSY should assert and then an EOC be seen, + //the user can assert a CONVST again without having to write to the sequence register to start the sequence again. + curr_seq1_0 <= SEQ_SINGLE_CHAN; //4'b0011; + else + curr_seq1_0 <= SEQ_DEFAULT_MODE; //4'b0000; + else + curr_seq1_0 <= seq1_0; + + always @(posedge conv_start or rst_in ) + if (rst_in == 1) begin + mn_mux_in <= 0.0; + curr_chan <= 6'b0; + end + else begin + curr_chan <= acq_chan; + curr_seq1_0_lat <= curr_seq1_0; + + if ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31)) begin + if (ext_mux_en) begin + tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan]); + mn_mux_in <= tmp_v; + end + else begin + tmp_v = $bitstoreal(mn_in_diff[acq_chan]); + mn_mux_in <= tmp_v; + end + end + else + mn_mux_in <= $bitstoreal(mn_in_uni[acq_chan]); + + if ( acq_chan == 7 || (acq_chan >= 9 && acq_chan <= 12) || acq_chan >= 36) + $display("Warning: [Unisim %s-14] The analog channel %x at time %.3f ns is invalid. Check register 40h[5:0]. Instance: %m", MODULE_NAME, acq_chan, $time/1000.0); + + if ((single_pass_mode && !single_pass_finished) || cont_seq_mode || default_mode ) begin + averaging <= curr_seq[13:12]; + curr_b_u <= curr_seq[10]; + curr_e_c <= curr_seq[9]; + curr_acq <= curr_seq[8]; + end + else begin + averaging <= acq_avg; + curr_b_u <= acq_b_u; + curr_e_c <= cfg_reg0[9]; + curr_acq <= cfg_reg0[8]; + end + end // if (rst_in == 0) + + // end of latch configuration registers + + //----------------------------------------------------------------- + + // sequence control + + + always @(seq_en) + seq_en_dly <= #1 seq_en; + + always @(posedge seq_en_dly) begin + if (single_pass_mode || cont_seq_mode) begin //single pass or continuous sequence mode + // high rate sequence + hr_tot_chan = 0; + for (si=0; si<= 15; si=si+1) begin + if (seq_chan_reg1[si] ==1) begin + hr_tot_chan = hr_tot_chan + 1; + seq_mem[hr_tot_chan] = si; //seq_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31. + end + end + for (si=16; si<= 31; si=si+1) begin + if (seq_chan_reg2[si-16] ==1) begin + hr_tot_chan = hr_tot_chan + 1; + seq_mem[hr_tot_chan] = si; + end + end + for (si=32; si<= 35; si=si+1) begin + if (seq_chan_reg3[si-32] ==1) begin + hr_tot_chan = hr_tot_chan + 1; + seq_mem[hr_tot_chan] = si; + end + end + end + else if (default_mode ) begin //default mode + if(cfg_reg0[11]) + $display("Error: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in default mode. Instance: %m", MODULE_NAME); + + hr_tot_chan = 5; + seq_mem[1] = 0; + seq_mem[2] = 8; + seq_mem[3] = 9; + seq_mem[4] = 10; + seq_mem[5] = 14; + end + end //always + + + always @( seq_count or negedge seq_en_dly) begin + seq_curr_i = seq_mem[seq_count]; + curr_seq = 16'b0; + if (seq_curr_i >= 0 && seq_curr_i <= 15) begin + curr_seq [2:0] = seq_curr_i[2:0]; + curr_seq [4:3] = 2'b01; + curr_seq [8] = seq_acq_reg1[seq_curr_i]; + curr_seq [10] = seq_bu_reg1[seq_curr_i]; + + if (default_mode) + curr_seq [13:12] = 2'b01; + else if (seq_avg_reg1[seq_curr_i]) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + + if (seq_curr_i >= 0 && seq_curr_i <=7) + curr_seq [4:3] = 2'b01; + else + curr_seq [4:3] = 2'b00; + end + else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin + curr_seq [4:0] = seq_curr_i; + curr_seq [8] = seq_acq_reg2[seq_curr_i - 16]; + curr_seq [10] = seq_bu_reg2[seq_curr_i - 16]; + if (seq_avg_reg2[seq_curr_i - 16] == 1) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + end // if (seq_curr_i >= 16 && seq_curr_i <= 31) + else if (seq_curr_i > 31 && seq_curr_i <= 35) begin + curr_seq [5:0] = seq_curr_i; + curr_seq [8] = seq_acq_reg3[seq_curr_i - 32]; + curr_seq [10] = seq_bu_reg3[seq_curr_i - 32]; + if (seq_avg_reg3[seq_curr_i - 32] == 1) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + end + end + + + always @( seq_count_a or negedge seq_en_dly) begin + seq_curr_ia = seq_mem[seq_count_a]; + curr_seq_m = 16'b0; + if (seq_curr_ia >= 0 && seq_curr_ia <= 15) begin + curr_seq_m [2:0] = seq_curr_ia[2:0]; + curr_seq_m [4:3] = 2'b01; + curr_seq_m [8] = seq_acq_reg1[seq_curr_ia]; + curr_seq_m [10] = seq_bu_reg1[seq_curr_ia]; + + if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) + curr_seq_m [13:12] = 2'b01; + else if (seq_avg_reg1[seq_curr_ia] == 1) + curr_seq_m [13:12] = cfg_reg0[13:12]; + else + curr_seq_m [13:12] = 2'b00; + + if (seq_curr_ia >= 0 && seq_curr_ia <=7) + curr_seq_m [4:3] = 2'b01; + else + curr_seq_m [4:3] = 2'b00; + end + else if (seq_curr_ia >= 16 && seq_curr_ia <= 31) begin + curr_seq_m [4:0] = seq_curr_ia; + curr_seq_m [8] = seq_acq_reg2[seq_curr_ia - 16]; + curr_seq_m [10] = seq_bu_reg2[seq_curr_ia - 16]; + if (seq_avg_reg2[seq_curr_ia - 16] == 1) + curr_seq_m [13:12] = cfg_reg0[13:12]; + else + curr_seq_m [13:12] = 2'b00; + end + else if (seq_curr_ia > 31 && seq_curr_ia <= 35) begin + curr_seq_m [5:0] = seq_curr_ia; + curr_seq_m [8] = seq_acq_reg3[seq_curr_ia - 32]; + curr_seq_m [10] = seq_bu_reg3[seq_curr_ia - 32]; + if (seq_avg_reg3[seq_curr_ia - 32] == 1) + curr_seq_m [13:12] = cfg_reg0[13:12]; + else + curr_seq_m [13:12] = 2'b00; + end + end // always @ ( seq_count_a or negedge seq_en_dly) + + + always @(posedge BUSY_out or posedge rst_in ) begin + if (rst_in == 1 || rst_lock == 1 ) + seq_count_a <= 1; + else begin + if ( curr_seq1_0_lat == SEQ_SINGLE_CHAN ) + seq_count_a <= 1; + else begin + if (seq_count_a >= 37 || seq_count_a >= hr_tot_chan) + seq_count_a <= 1; + else + seq_count_a <= seq_count_a +1; + end + end + end //always + + + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1 ) begin + seq_count <= 1; + eos_en <= 0; + end + else begin + + if ((seq_count == hr_tot_chan) && + (adc_state == S3_ST && adc_next_state == S5_ST) && + (curr_seq1_0_lat != SEQ_SINGLE_CHAN) && rst_lock == 0) + eos_tmp_en <= 1; + else + eos_tmp_en <= 0; + + if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk + eos_en <= 1; + else + eos_en <= 0; + + if (eos_tmp_en == 1 || (curr_seq1_0_lat == SEQ_SINGLE_CHAN)) begin + seq_count <= 1; + end + else if (seq_count_en == 1) begin + if (seq_count >= 37) + seq_count <= 1; + else + seq_count <= seq_count +1; + end + end // else: !if(rst_in == 1 ) + +// end sequence control + + // Acquisition + reg first_acq; + reg shorten_acq; + wire BUSY_out_dly; + + assign #10 BUSY_out_dly = BUSY_out; + + always @(adc_state or posedge rst_in or first_acq) begin + if(rst_in) + shorten_acq = 0; + else if(BUSY_out_dly==0 && adc_state==S2_ST && first_acq==1) + shorten_acq = 1; + else + shorten_acq = 0; + end + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1 || rst_lock == 1) begin + acq_count <= 1; + first_acq <= 1; + end + else begin + if (adc_state == S2_ST && rst_lock == 0 && (acq_e_c==0)) begin + first_acq <= 0; + if (acq_acqsel == 1) begin + if (acq_count <= 11) + acq_count <= acq_count + 1 + shorten_acq; + end + else begin + if (acq_count <= 4) + acq_count <= acq_count + 1 + shorten_acq; + end // else: !if(acq_acqsel == 1) + + if (adc_next_state == S3_ST) + if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4)) + $display ("Warning: [Unisim %s-21] Acquisition time is not long enough at time %t. Instance: %m", MODULE_NAME, $time); + end // if (adc_state == S2_ST) + else + acq_count <= (first_acq) ? 1 : 0; + end // if (rst_in == 0) + + // continuous mode + reg conv_start_cont; + wire reset_conv_start; + wire conv_start_sel; + + always @(adc_state or acq_acqsel or acq_count) + if (adc_state == S2_ST) begin + if (rst_lock == 0) begin + // CR 800173 + // if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03)) && + // ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) ) + if ((acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) // acq time, adcclk cycles 4 or 10 + conv_start_cont = 1; + else + conv_start_cont = 0; + end + end // if (adc_state == S2_ST) + else + conv_start_cont = 0; + + + assign conv_start_sel = (acq_e_c) ? CONVST_reg : conv_start_cont; + assign reset_conv_start = rst_in | (conv_count==CONV_CAL_PER_0); + + always@(posedge conv_start_sel or posedge reset_conv_start) begin + if(reset_conv_start) + conv_start <= 0; + else + conv_start <= 1; + end + + +// end acquisition + +// Conversion + always @(adc_state or adc_next_state or curr_chan or mn_mux_in or curr_b_u) begin + if ((adc_state == S3_ST && adc_next_state == S5_ST) || adc_state == S5_ST) begin + if (curr_chan == 0) begin // temperature conversion + adc_temp_result = (mn_mux_in + 273.6777) * 0.0019945*65536.0; //CR 861679 + + if (adc_temp_result >= 65535.0) + conv_result_int = 65535; + else if (adc_temp_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_temp_result); + if (adc_temp_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 1 || curr_chan == 2 || curr_chan ==6 || + curr_chan == 13 || curr_chan == 14 || curr_chan == 15 || + (curr_chan >= 32 && curr_chan <= 35)) begin // internal power conversion + adc_intpwr_result = mn_mux_in * 65536.0 / 3.0; + if (adc_intpwr_result >= 65535.0) + conv_result_int = 65535; + else if (adc_intpwr_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_intpwr_result); + if (adc_intpwr_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin + adc_ext_result = (mn_mux_in) * 65536.0; + if (curr_b_u == 1) begin + if (adc_ext_result > 32767.0) + conv_result_int = 32767; + else if (adc_ext_result < -32768.0) + conv_result_int = -32768; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else begin + if (adc_ext_result > 65535.0) + conv_result_int = 65535; + else if (adc_ext_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + end + else begin + conv_result_int = 0; + end + end + + conv_result = conv_result_int; + + end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u) + + + reg busy_r_rst_done; + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) begin + busy_r_rst <= 0; + busy_r_rst_done <= 0; + conv_count <= CONV_CAL_PER_RST; + conv_end <= 0; + end + else begin + if(adc_state == S2_ST) begin + busy_r_rst_done <= 1; + busy_r_rst <= (!busy_r_rst_done) ? 1 : 0; + if (conv_start == 1) begin + conv_count <= 0; + conv_end <= 0; + end + end + else if (adc_state == S3_ST ) begin + busy_r_rst_done <= 0; + conv_count = conv_count + 1; + if ((curr_chan!=5'b01000 ) && (conv_count==CONV_NOTCAL_PER_1 ) || + (curr_chan==5'b01000 ) && (conv_count==CONV_CAL_PER_2 ) && (first_cal_chan) || + (curr_chan==5'b01000 ) && (conv_count==CONV_CAL_PER_3 ) && (!first_cal_chan)) + conv_end <= 1; + else + conv_end <= 0; + end + else begin //all other adc_state's except for S2_ST and S3_ST + conv_end <= 0; + conv_count <= 0; + end + end + end//always + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) + conv_result_reg <= 0; + else begin + if (adc_state == S5_ST) + conv_result_reg <= conv_result; + end + end + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) + single_chan_conv_end <= 0; + else begin + // jmcgrath - to model the behaviour correctly when a cal chanel is being converted + // an signal to signify the conversion has ended must be produced - this is for single channel mode + single_chan_conv_end <= 0; + if( (conv_count ==CONV_NOTCAL_PER_1) || (conv_count == CONV_CAL_PER_4)) + single_chan_conv_end <= 1; + end + end + + assign avg_amount = averaging==2'b00 ? 0 : + averaging==2'b01 ? 15 : + averaging==2'b10 ? 63 : + 255 ; //2'b11 + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) begin + seq_status_avg <= 0; + for (i = 0; i <=35; i = i +1) begin + conv_avg_count[i] <= 0; // array of integer + end + end + else begin + if (adc_state == S3_ST && adc_next_state == S5_ST && rst_lock == 0) begin + if(averaging==2'b00) begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + end + else begin //averaging is on + if (conv_avg_count[curr_chan] == avg_amount) begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_avg_count[curr_chan] == 0) begin + seq_status_avg <= seq_status_avg + 1; + end + conv_avg_count[curr_chan] <= conv_avg_count[curr_chan] + 1; + end + end // averaging>0 + end // if (adc_state == S3_ST && adc_next_state == S5_ST) + else begin + eoc_en <= 0; + end + end // else + end //always + // end conversion + + + // average + always @(adc_state or conv_acc[curr_chan]) + if (adc_state == S5_ST ) + // no signed or unsigned differences for bit vector conv_acc_vec + conv_acc_vec = conv_acc[curr_chan]; + else + conv_acc_vec = 24'd0; + + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + for (j = 0; j <= 63; j = j + 1) begin + conv_acc[j] <= 0; + end + conv_acc_result <= 16'd0; + end + else begin + if (adc_state == S3_ST && adc_next_state == S5_ST) begin + if (averaging != 2'b00 && rst_lock != 1) + conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int; + else + conv_acc[curr_chan] <= 0; + end // if (adc_state == S3_ST && adc_next_state == S5_ST) + else if (eoc_en == 1) begin + case (averaging) + 2'b00 : conv_acc_result <= 16'd0; + 2'b01 : conv_acc_result <= conv_acc_vec[19:4]; + 2'b10 : conv_acc_result <= conv_acc_vec[21:6]; + 2'b11 : conv_acc_result <= conv_acc_vec[23:8]; + endcase + conv_acc[curr_chan] <= 0; + end + end // if (rst_in == 0) + + // end average + + // single sequence + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) + single_pass_finished <= 0; + else + if (adc_state == S1_ST) + single_pass_finished <= 1; //single pass sequence selected and sequence has ended. + end + // end state + + always @(posedge adcclk or posedge rst_in) + if (rst_in) begin + seq_count_en <= 0; + EOS_out_tmp <= 0; + EOC_out_tmp <= 0; + end + else begin + if ((adc_state == S3_ST && adc_next_state == S5_ST) && (curr_seq1_0_lat != SEQ_SINGLE_CHAN ) && !rst_lock ) + seq_count_en <= 1; + else + seq_count_en <= 0; + + if (!rst_lock) begin + EOS_out_tmp <= eos_en; + eoc_en_delay <= eoc_en; + EOC_out_tmp <= eoc_en_delay; + end + else begin + EOS_out_tmp <= 0; + eoc_en_delay <= 0; + EOC_out_tmp <= 0; + end + end + + + + always @(posedge EOC_out_pre2 or posedge rst_in_not_seq) begin + if (rst_in_not_seq == 1) begin + data_reg[32] = 16'h0000; + data_reg[33] = 16'h0000; + data_reg[34] = 16'h0000; + data_reg[35] = 16'h0000; + data_reg[36] = 16'hFFFF; + data_reg[37] = 16'hFFFF; + data_reg[38] = 16'hFFFF; + data_reg[39] = 16'hFFFF; + data_reg[40] = 16'h0000; + data_reg[41] = 16'h0000; + data_reg[42] = 16'h0000; + data_reg[44] = 16'hFFFF; + data_reg[45] = 16'hFFFF; + data_reg[46] = 16'hFFFF; + end + else if ( rst_lock == 0) begin //also posedge EOC_out_pre2 + // current or averaged values' update to status registers + if ((curr_chan_lat >= 0 && curr_chan_lat <= 3) || (curr_chan_lat == 6) || + (curr_chan_lat >= 13 && curr_chan_lat <= 31)) begin + if (averaging_d == 2'b00) + data_reg[curr_chan_lat] <= conv_result_reg; + else + data_reg[curr_chan_lat] <= conv_acc_result; + end + else if (curr_chan_lat >= 32 && curr_chan_lat <= 35) begin //VUser0-3 + if (averaging_d == 2'b00) + dr_sram[curr_chan_lat + 96] <= conv_result_reg; //80h-83h + else + dr_sram[curr_chan_lat + 96] <= conv_acc_result; + end + else if (curr_chan_lat == 4) // VREFP + data_reg[curr_chan_lat] <= 16'h0000; // CR-961722 Simulation always simulates the internal reference behavior. Hence VrefP=0V + else if (curr_chan_lat == 5) // VREFN + data_reg[curr_chan_lat] <= 16'h0000; + + //min and max values' update + if (curr_chan_lat == 0 || curr_chan_lat == 1 || curr_chan_lat == 2) begin //TEMPERATURE, VCCINT and VCCAUX max and min + if (averaging_d == 2'b00) begin + if (conv_result_reg > data_reg[32 + curr_chan_lat]) + data_reg[32 + curr_chan_lat] <= conv_result_reg; + if (conv_result_reg < data_reg[36 + curr_chan_lat]) + data_reg[36 + curr_chan_lat] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[32 + curr_chan_lat]) + data_reg[32 + curr_chan_lat] <= conv_acc_result; + if (conv_acc_result < data_reg[36 + curr_chan_lat]) + data_reg[36 + curr_chan_lat] <= conv_acc_result; + end + end + + else if (curr_chan_lat == 6) begin //VCCBRAM max and min + if (averaging_d == 2'b00) begin + if (conv_result_reg > data_reg[35]) + data_reg[35] <= conv_result_reg; + if (conv_result_reg < data_reg[39]) + data_reg[39] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[35]) + data_reg[35] <= conv_acc_result; + if (conv_acc_result < data_reg[39]) + data_reg[39] <= conv_acc_result; + end + end + else if (curr_chan_lat >= 13 && curr_chan_lat <= 15) begin // VPSINTLP, VPSINTFP , VPSAUX + if (averaging_d == 2'b00) begin + if (conv_result_reg > data_reg[27+curr_chan_lat]) + data_reg[27+curr_chan_lat] <= conv_result_reg; + if (conv_result_reg < data_reg[31+curr_chan_lat]) + data_reg[31+curr_chan_lat] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[27+curr_chan_lat]) + data_reg[27+curr_chan_lat] <= conv_acc_result; + if (conv_acc_result < data_reg[31+curr_chan_lat]) + data_reg[31+curr_chan_lat] <= conv_acc_result; + end + end + else if (curr_chan_lat >= 32 && curr_chan_lat <=35) begin //Vuser0-3 + if (averaging_d == 2'b00) begin + if (conv_result_reg < dr_sram[curr_chan_lat+136]) + dr_sram[curr_chan_lat+136] <= conv_result_reg; + if (conv_result_reg > dr_sram[curr_chan_lat+128]) + dr_sram[curr_chan_lat+128] <= conv_result_reg; + end + else begin + if (conv_acc_result < dr_sram[curr_chan_lat+136]) + dr_sram[curr_chan_lat+136] <= conv_acc_result; + if (conv_acc_result > dr_sram[curr_chan_lat+128]) + dr_sram[curr_chan_lat+128] <= conv_acc_result; + end + end + + end // ( rst_lock == 0) + end//always + + + // current measurement data + always @(negedge busy_r or posedge rst_in_not_seq ) + if (rst_in_not_seq) + data_written <= 16'd0; + else begin + if (averaging == 2'b00) + data_written <= conv_result_reg; + else + data_written <= conv_acc_result; + end + + + reg [4:0] op_count=15; + reg BUSY_out_sync; + wire BUSY_out_low_edge; + +// eos and eoc + + always @( posedge EOC_out_tmp or posedge EOC_out or posedge rst_in) + if (rst_in ==1) + EOC_out_tmp1 <= 0; + else if ( EOC_out ==1) + EOC_out_tmp1 <= 0; + else if (EOC_out_tmp == 1) begin + if (curr_chan != 5'b01000 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0))) //not calibration and check power + EOC_out_tmp1 <= 1; + else + EOC_out_tmp1 <= 0; + end + + always @( posedge EOS_out_tmp or posedge EOS_out or posedge rst_in) + if (rst_in ==1) + EOS_out_tmp1 <= 0; + else if (EOS_out ==1) + EOS_out_tmp1 <= 0; + else if (EOS_out_tmp == 1 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0))) + EOS_out_tmp1 <= 1; + + assign BUSY_out_low_edge = (BUSY_out==0 && BUSY_out_sync==1) ? 1 : 0; + + always @( posedge DCLK_in or posedge rst_in) begin + if (rst_in) + op_count <= 15; + else begin + if (BUSY_out_low_edge==1 ) + op_count <= 0; + else if(op_count < 22) + op_count <= op_count +1; + end + end + + always @(posedge DCLK_in or posedge rst_in) begin + if (rst_in) begin + EOC_out <= 0; + EOS_out <= 0; + EOC_out_pre <= 0; + EOC_out_pre2 <= 0; + end + else begin + if(op_count== 16) begin + EOC_out <= EOC_out_tmp1; + EOS_out <= EOS_out_tmp1; + EOC_out_pre <=0; + EOC_out_pre2 <=0; + end + else if (op_count==15) begin + EOC_out <= 0; + EOS_out <= 0; + EOC_out_pre <= EOC_out_tmp1; + EOC_out_pre2 <=0; + end + else if (op_count==14) begin + EOC_out <= 0; + EOS_out <= 0; + EOC_out_pre <=0; + EOC_out_pre2 <= EOC_out_tmp1; + end + else begin + EOC_out <= 0; + EOS_out <= 0; + EOC_out_pre <= 0; + EOC_out_pre2 <= 0; + end + end + end + + always @( posedge DCLK_in or posedge rst_in) begin + if (rst_in) begin + BUSY_out_sync <= 0; + drp_update <= 0; + alm_update <= 0; + end + else begin // if(rst_in==0) begin + BUSY_out_sync <= BUSY_out; + drp_update <= (op_count==3)? 1 : 0; + alm_update <= (op_count==5 && EOC_out_tmp1==1) ? 1 : 0; + end + end + +// end eos and eoc + +// alarm + + always @( posedge alm_update or posedge rst_in_not_seq ) begin + if (rst_in_not_seq == 1) begin + ot_out_reg <= 0; + alm_out_reg <= 8'b0; + end + else if (rst_lock == 0) begin + if (curr_chan_lat == 0) begin // temperature + if (data_written >= ot_limit_reg) + ot_out_reg <= 1; + else if (data_written < dr_sram[8'h57]) + ot_out_reg <= 0; + + if (data_written > dr_sram[8'h50]) + alm_out_reg[0] <= 1; + else if (data_written < dr_sram[8'h54]) + alm_out_reg[0] <= 0; + end + + if (curr_chan_lat == 1) begin // VCC INT + if (data_written > dr_sram[8'h51] || data_written < dr_sram[8'h55]) + alm_out_reg[1] <= 1; + else + alm_out_reg[1] <= 0; + end + + if (curr_chan_lat == 2) begin //VCCAUX + if (data_written > dr_sram[8'h52] || data_written < dr_sram[8'h56]) + alm_out_reg[2] <= 1; + else + alm_out_reg[2] <= 0; + end + + if (curr_chan_lat == 6) begin // VCC BRAM + if (data_written > dr_sram[8'h58] || data_written < dr_sram[8'h5C]) + alm_out_reg[3] <= 1; + else + alm_out_reg[3] <= 0; + end + if (curr_chan_lat == 13) begin //VCC PSINTLP + if (data_written > dr_sram[8'h59] || data_written < dr_sram[8'h5D]) + alm_out_reg[4] <= 1; + else + alm_out_reg[4] <= 0; + end + if (curr_chan_lat == 14) begin // VCC PSINTFP + if (data_written > dr_sram[8'h5A] || data_written < dr_sram[8'h5E]) + alm_out_reg[5] <= 1; + else + alm_out_reg[5] <= 0; + end + if (curr_chan_lat == 15) begin // VCC PSAUX + if (data_written > dr_sram[8'h5B] || data_written < dr_sram[8'h5F]) + alm_out_reg[6] <= 1; + else + alm_out_reg[6] <= 0; + end + if (curr_chan_lat == 32) begin // VUSER 0 + if (data_written > dr_sram[8'h60] || data_written < dr_sram[8'h68]) + alm_out_reg[8] <= 1; + else + alm_out_reg[8] <= 0; + end + if (curr_chan_lat == 33) begin // VUSER 1 + if (data_written > dr_sram[8'h61] || data_written < dr_sram[8'h69]) + alm_out_reg[9] <= 1; + else + alm_out_reg[9] <= 0; + end + if (curr_chan_lat == 34) begin // VUSER 2 + if (data_written > dr_sram[8'h62] || data_written < dr_sram[8'h6A]) + alm_out_reg[10] <= 1; + else + alm_out_reg[10] <= 0; + end + if (curr_chan_lat == 35) begin // VUSER 3 + if (data_written > dr_sram[8'h63] || data_written < dr_sram[8'h6B]) + alm_out_reg[11] <= 1; + else + alm_out_reg[11] <= 0; + end + end//rst_lock + end // always + + //always @(ot_out_reg or ot_en or alm_out_reg or alm_en) begin + always @(*) begin + OT_out = ot_out_reg & ot_en; + + ALM_out[6:0] = alm_out_reg[6:0] & alm_en[6:0]; + ALM_out[7] = |ALM_out[6:0]; + ALM_out[11:8] = alm_out_reg[11:8] & alm_en[11:8]; + ALM_out[14:12] = 'd0; // Reserved + ALM_out[15] = (|ALM_out[11:8]) | (|ALM_out[6:0]); + end + + // end alarm + + //*** Timing_Checks_Start_here + +`ifdef XIL_TIMING + reg notifier; + + wire dclk_en_n; + wire dclk_en_p; + + assign dclk_en_n = IS_DCLK_INVERTED_BIN; + assign dclk_en_p = ~IS_DCLK_INVERTED_BIN; + + reg notifier_do; + + wire rst_en_n = ~RESET_in && dclk_en_n; + wire rst_en_p = ~RESET_in && dclk_en_p; + + always @(notifier) begin + alm_out_reg = 16'bx; + OT_out = 1'bx; + BUSY_out = 1'bx; + EOC_out = 1'bx; + EOS_out = 1'bx; + curr_chan = 5'bx; + DRDY_out = 1'bx; + DO_out = 16'bx; + end + + always @(notifier_do) begin + DRDY_out = 1'bx; + DO_out = 16'bx; + end + + +`endif + + specify + (DCLK => ALM[0]) = (100:100:100, 100:100:100); + (DCLK => ALM[10]) = (100:100:100, 100:100:100); + (DCLK => ALM[11]) = (100:100:100, 100:100:100); + (DCLK => ALM[12]) = (100:100:100, 100:100:100); + (DCLK => ALM[13]) = (100:100:100, 100:100:100); + (DCLK => ALM[15]) = (100:100:100, 100:100:100); + (DCLK => ALM[1]) = (100:100:100, 100:100:100); + (DCLK => ALM[2]) = (100:100:100, 100:100:100); + (DCLK => ALM[3]) = (100:100:100, 100:100:100); + (DCLK => ALM[4]) = (100:100:100, 100:100:100); + (DCLK => ALM[5]) = (100:100:100, 100:100:100); + (DCLK => ALM[6]) = (100:100:100, 100:100:100); + (DCLK => ALM[7]) = (100:100:100, 100:100:100); + (DCLK => ALM[8]) = (100:100:100, 100:100:100); + (DCLK => ALM[9]) = (100:100:100, 100:100:100); + (DCLK => BUSY) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[0]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[1]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[2]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[3]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[4]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[5]) = (100:100:100, 100:100:100); + (DCLK => DO[0]) = (100:100:100, 100:100:100); + (DCLK => DO[10]) = (100:100:100, 100:100:100); + (DCLK => DO[11]) = (100:100:100, 100:100:100); + (DCLK => DO[12]) = (100:100:100, 100:100:100); + (DCLK => DO[13]) = (100:100:100, 100:100:100); + (DCLK => DO[14]) = (100:100:100, 100:100:100); + (DCLK => DO[15]) = (100:100:100, 100:100:100); + (DCLK => DO[1]) = (100:100:100, 100:100:100); + (DCLK => DO[2]) = (100:100:100, 100:100:100); + (DCLK => DO[3]) = (100:100:100, 100:100:100); + (DCLK => DO[4]) = (100:100:100, 100:100:100); + (DCLK => DO[5]) = (100:100:100, 100:100:100); + (DCLK => DO[6]) = (100:100:100, 100:100:100); + (DCLK => DO[7]) = (100:100:100, 100:100:100); + (DCLK => DO[8]) = (100:100:100, 100:100:100); + (DCLK => DO[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => EOC) = (100:100:100, 100:100:100); + (DCLK => EOS) = (100:100:100, 100:100:100); + (DCLK => JTAGBUSY) = (100:100:100, 100:100:100); + (DCLK => JTAGLOCKED) = (100:100:100, 100:100:100); + (DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[0]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[1]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[2]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[3]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[4]) = (100:100:100, 100:100:100); + (DCLK => OT) = (100:100:100, 100:100:100); + `ifdef XIL_TIMING + $period (negedge CONVST, 0:0:0, notifier); + $period (negedge CONVSTCLK, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (posedge CONVST, 0:0:0, notifier); + $period (posedge CONVSTCLK, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $recrem (negedge RESET, negedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_n, dclk_en_n, RESET_delay, DCLK_delay); + $recrem (negedge RESET, posedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_p, dclk_en_p, RESET_delay, DCLK_delay); + $recrem (posedge RESET, negedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_n, dclk_en_n, RESET_delay, DCLK_delay); + $recrem (posedge RESET, posedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_p, dclk_en_p, RESET_delay, DCLK_delay); + $setuphold (negedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]); + $setuphold (negedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]); + $setuphold (negedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]); + $setuphold (negedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]); + $setuphold (negedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]); + $setuphold (negedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]); + $setuphold (negedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]); + $setuphold (negedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]); + $setuphold (negedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay); + $setuphold (negedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]); + $setuphold (negedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]); + $setuphold (negedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]); + $setuphold (negedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]); + $setuphold (negedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]); + $setuphold (negedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]); + $setuphold (negedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]); + $setuphold (negedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]); + $setuphold (negedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[2]); + $setuphold (negedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[3]); + $setuphold (negedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]); + $setuphold (negedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]); + $setuphold (negedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]); + $setuphold (negedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]); + $setuphold (negedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]); + $setuphold (negedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]); + $setuphold (negedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay); + $setuphold (negedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]); + $setuphold (negedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]); + $setuphold (negedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]); + $setuphold (negedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]); + $setuphold (negedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]); + $setuphold (negedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]); + $setuphold (negedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]); + $setuphold (negedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]); + $setuphold (negedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay); + $setuphold (negedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]); + $setuphold (negedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]); + $setuphold (negedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]); + $setuphold (negedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]); + $setuphold (negedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]); + $setuphold (negedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]); + $setuphold (negedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]); + $setuphold (negedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]); + $setuphold (negedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[2]); + $setuphold (negedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[3]); + $setuphold (negedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]); + $setuphold (negedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]); + $setuphold (negedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]); + $setuphold (negedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]); + $setuphold (negedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]); + $setuphold (negedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]); + $setuphold (negedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay); + $width (negedge CONVST, 0:0:0, 0, notifier); + $width (negedge CONVSTCLK, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (posedge CONVST, 0:0:0, 0, notifier); + $width (posedge CONVSTCLK, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; +endspecify + + //`undef CALIBRATION_ALWAYS_FIRST + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/SYSMONE4.v b/verilog/src/unisims/SYSMONE4.v new file mode 100644 index 0000000..37831df --- /dev/null +++ b/verilog/src/unisims/SYSMONE4.v @@ -0,0 +1,4698 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / Xilinx Analog-to-Digital Converter and System Monitor +// /___/ /\ Filename : SYSMONE4.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ps / 1ps + +`celldefine + + module SYSMONE4 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter [15:0] COMMON_N_SOURCE = 16'hFFFF, + parameter [15:0] INIT_40 = 16'h0000, + parameter [15:0] INIT_41 = 16'h0000, + parameter [15:0] INIT_42 = 16'h0000, + parameter [15:0] INIT_43 = 16'h0000, + parameter [15:0] INIT_44 = 16'h0000, + parameter [15:0] INIT_45 = 16'h0000, + parameter [15:0] INIT_46 = 16'h0000, + parameter [15:0] INIT_47 = 16'h0000, + parameter [15:0] INIT_48 = 16'h0000, + parameter [15:0] INIT_49 = 16'h0000, + parameter [15:0] INIT_4A = 16'h0000, + parameter [15:0] INIT_4B = 16'h0000, + parameter [15:0] INIT_4C = 16'h0000, + parameter [15:0] INIT_4D = 16'h0000, + parameter [15:0] INIT_4E = 16'h0000, + parameter [15:0] INIT_4F = 16'h0000, + parameter [15:0] INIT_50 = 16'h0000, + parameter [15:0] INIT_51 = 16'h0000, + parameter [15:0] INIT_52 = 16'h0000, + parameter [15:0] INIT_53 = 16'h0000, + parameter [15:0] INIT_54 = 16'h0000, + parameter [15:0] INIT_55 = 16'h0000, + parameter [15:0] INIT_56 = 16'h0000, + parameter [15:0] INIT_57 = 16'h0000, + parameter [15:0] INIT_58 = 16'h0000, + parameter [15:0] INIT_59 = 16'h0000, + parameter [15:0] INIT_5A = 16'h0000, + parameter [15:0] INIT_5B = 16'h0000, + parameter [15:0] INIT_5C = 16'h0000, + parameter [15:0] INIT_5D = 16'h0000, + parameter [15:0] INIT_5E = 16'h0000, + parameter [15:0] INIT_5F = 16'h0000, + parameter [15:0] INIT_60 = 16'h0000, + parameter [15:0] INIT_61 = 16'h0000, + parameter [15:0] INIT_62 = 16'h0000, + parameter [15:0] INIT_63 = 16'h0000, + parameter [15:0] INIT_64 = 16'h0000, + parameter [15:0] INIT_65 = 16'h0000, + parameter [15:0] INIT_66 = 16'h0000, + parameter [15:0] INIT_67 = 16'h0000, + parameter [15:0] INIT_68 = 16'h0000, + parameter [15:0] INIT_69 = 16'h0000, + parameter [15:0] INIT_6A = 16'h0000, + parameter [15:0] INIT_6B = 16'h0000, + parameter [15:0] INIT_6C = 16'h0000, + parameter [15:0] INIT_6D = 16'h0000, + parameter [15:0] INIT_6E = 16'h0000, + parameter [15:0] INIT_6F = 16'h0000, + parameter [15:0] INIT_70 = 16'h0000, + parameter [15:0] INIT_71 = 16'h0000, + parameter [15:0] INIT_72 = 16'h0000, + parameter [15:0] INIT_73 = 16'h0000, + parameter [15:0] INIT_74 = 16'h0000, + parameter [15:0] INIT_75 = 16'h0000, + parameter [15:0] INIT_76 = 16'h0000, + parameter [15:0] INIT_77 = 16'h0000, + parameter [15:0] INIT_78 = 16'h0000, + parameter [15:0] INIT_79 = 16'h0000, + parameter [15:0] INIT_7A = 16'h0000, + parameter [15:0] INIT_7B = 16'h0000, + parameter [15:0] INIT_7C = 16'h0000, + parameter [15:0] INIT_7D = 16'h0000, + parameter [15:0] INIT_7E = 16'h0000, + parameter [15:0] INIT_7F = 16'h0000, + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0, + parameter [0:0] IS_DCLK_INVERTED = 1'b0, + parameter SIM_DEVICE = "ULTRASCALE_PLUS", + parameter SIM_MONITOR_FILE = "design.txt", + parameter integer SYSMON_VUSER0_BANK = 0, + parameter SYSMON_VUSER0_MONITOR = "NONE", + parameter integer SYSMON_VUSER1_BANK = 0, + parameter SYSMON_VUSER1_MONITOR = "NONE", + parameter integer SYSMON_VUSER2_BANK = 0, + parameter SYSMON_VUSER2_MONITOR = "NONE", + parameter integer SYSMON_VUSER3_BANK = 0, + parameter SYSMON_VUSER3_MONITOR = "NONE" +)( + output [15:0] ADC_DATA, + output [15:0] ALM, + output BUSY, + output [5:0] CHANNEL, + output [15:0] DO, + output DRDY, + output EOC, + output EOS, + output I2C_SCLK_TS, + output I2C_SDA_TS, + output JTAGBUSY, + output JTAGLOCKED, + output JTAGMODIFIED, + output [4:0] MUXADDR, + output OT, + output SMBALERT_TS, + + input CONVST, + input CONVSTCLK, + input [7:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input I2C_SCLK, + input I2C_SDA, + input RESET, + input [15:0] VAUXN, + input [15:0] VAUXP, + input VN, + input VP + ); + +// define constants + localparam MODULE_NAME = "SYSMONE4"; + +// Parameter encodings and registers + //localparam SIM_DEVICE_ULTRASCALE_PLUS = 0; + //localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 1; + //localparam SIM_DEVICE_ZYNQ_ULTRASCALE = 2; + //localparam SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 = 3; + //localparam SIM_MONITOR_FILE_design_txt = 0; + //localparam SYSMON_VUSER0_MONITOR_NONE = 0; + //localparam SYSMON_VUSER1_MONITOR_NONE = 0; + //localparam SYSMON_VUSER2_MONITOR_NONE = 0; + //localparam SYSMON_VUSER3_MONITOR_NONE = 0; + + reg trig_attr = 1'b0; + reg trig_dep_attr = 1'b0; + reg trig_i2c_addr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "SYSMONE4_dr.v" +`else + localparam [15:0] COMMON_N_SOURCE_REG = COMMON_N_SOURCE; + localparam [15:0] INIT_40_REG = INIT_40; + localparam [15:0] INIT_41_REG = INIT_41; + localparam [15:0] INIT_42_REG = INIT_42; + localparam [15:0] INIT_43_REG = INIT_43; + localparam [15:0] INIT_44_REG = INIT_44; + localparam [15:0] INIT_45_REG = INIT_45; + localparam [15:0] INIT_46_REG = INIT_46; + localparam [15:0] INIT_47_REG = INIT_47; + localparam [15:0] INIT_48_REG = INIT_48; + localparam [15:0] INIT_49_REG = INIT_49; + localparam [15:0] INIT_4A_REG = INIT_4A; + localparam [15:0] INIT_4B_REG = INIT_4B; + localparam [15:0] INIT_4C_REG = INIT_4C; + localparam [15:0] INIT_4D_REG = INIT_4D; + localparam [15:0] INIT_4E_REG = INIT_4E; + localparam [15:0] INIT_4F_REG = INIT_4F; + localparam [15:0] INIT_50_REG = INIT_50; + localparam [15:0] INIT_51_REG = INIT_51; + localparam [15:0] INIT_52_REG = INIT_52; + localparam [15:0] INIT_53_REG = INIT_53; + localparam [15:0] INIT_54_REG = INIT_54; + localparam [15:0] INIT_55_REG = INIT_55; + localparam [15:0] INIT_56_REG = INIT_56; + localparam [15:0] INIT_57_REG = INIT_57; + localparam [15:0] INIT_58_REG = INIT_58; + localparam [15:0] INIT_59_REG = INIT_59; + localparam [15:0] INIT_5A_REG = INIT_5A; + localparam [15:0] INIT_5B_REG = INIT_5B; + localparam [15:0] INIT_5C_REG = INIT_5C; + localparam [15:0] INIT_5D_REG = INIT_5D; + localparam [15:0] INIT_5E_REG = INIT_5E; + localparam [15:0] INIT_5F_REG = INIT_5F; + localparam [15:0] INIT_60_REG = INIT_60; + localparam [15:0] INIT_61_REG = INIT_61; + localparam [15:0] INIT_62_REG = INIT_62; + localparam [15:0] INIT_63_REG = INIT_63; + localparam [15:0] INIT_64_REG = INIT_64; + localparam [15:0] INIT_65_REG = INIT_65; + localparam [15:0] INIT_66_REG = INIT_66; + localparam [15:0] INIT_67_REG = INIT_67; + localparam [15:0] INIT_68_REG = INIT_68; + localparam [15:0] INIT_69_REG = INIT_69; + localparam [15:0] INIT_6A_REG = INIT_6A; + localparam [15:0] INIT_6B_REG = INIT_6B; + localparam [15:0] INIT_6C_REG = INIT_6C; + localparam [15:0] INIT_6D_REG = INIT_6D; + localparam [15:0] INIT_6E_REG = INIT_6E; + localparam [15:0] INIT_6F_REG = INIT_6F; + localparam [15:0] INIT_70_REG = INIT_70; + localparam [15:0] INIT_71_REG = INIT_71; + localparam [15:0] INIT_72_REG = INIT_72; + localparam [15:0] INIT_73_REG = INIT_73; + localparam [15:0] INIT_74_REG = INIT_74; + localparam [15:0] INIT_75_REG = INIT_75; + localparam [15:0] INIT_76_REG = INIT_76; + localparam [15:0] INIT_77_REG = INIT_77; + localparam [15:0] INIT_78_REG = INIT_78; + localparam [15:0] INIT_79_REG = INIT_79; + localparam [15:0] INIT_7A_REG = INIT_7A; + localparam [15:0] INIT_7B_REG = INIT_7B; + localparam [15:0] INIT_7C_REG = INIT_7C; + localparam [15:0] INIT_7D_REG = INIT_7D; + localparam [15:0] INIT_7E_REG = INIT_7E; + localparam [15:0] INIT_7F_REG = INIT_7F; + localparam [0:0] IS_CONVSTCLK_INVERTED_REG = IS_CONVSTCLK_INVERTED; + localparam [0:0] IS_DCLK_INVERTED_REG = IS_DCLK_INVERTED; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam [80:1] SIM_MONITOR_FILE_REG = SIM_MONITOR_FILE; + localparam [9:0] SYSMON_VUSER0_BANK_REG = SYSMON_VUSER0_BANK; + localparam [32:1] SYSMON_VUSER0_MONITOR_REG = SYSMON_VUSER0_MONITOR; + localparam [9:0] SYSMON_VUSER1_BANK_REG = SYSMON_VUSER1_BANK; + localparam [32:1] SYSMON_VUSER1_MONITOR_REG = SYSMON_VUSER1_MONITOR; + localparam [9:0] SYSMON_VUSER2_BANK_REG = SYSMON_VUSER2_BANK; + localparam [32:1] SYSMON_VUSER2_MONITOR_REG = SYSMON_VUSER2_MONITOR; + localparam [9:0] SYSMON_VUSER3_BANK_REG = SYSMON_VUSER3_BANK; + localparam [32:1] SYSMON_VUSER3_MONITOR_REG = SYSMON_VUSER3_MONITOR; +`endif + + wire [15:0] COMMON_N_SOURCE_BIN; + wire [15:0] INIT_40_BIN; + wire [15:0] INIT_41_BIN; + wire [15:0] INIT_42_BIN; + wire [15:0] INIT_43_BIN; + wire [15:0] INIT_44_BIN; + wire [15:0] INIT_45_BIN; + wire [15:0] INIT_46_BIN; + wire [15:0] INIT_47_BIN; + wire [15:0] INIT_48_BIN; + wire [15:0] INIT_49_BIN; + wire [15:0] INIT_4A_BIN; + wire [15:0] INIT_4B_BIN; + wire [15:0] INIT_4C_BIN; + wire [15:0] INIT_4D_BIN; + wire [15:0] INIT_4E_BIN; + wire [15:0] INIT_4F_BIN; + wire [15:0] INIT_50_BIN; + wire [15:0] INIT_51_BIN; + wire [15:0] INIT_52_BIN; + wire [15:0] INIT_53_BIN; + wire [15:0] INIT_54_BIN; + wire [15:0] INIT_55_BIN; + wire [15:0] INIT_56_BIN; + wire [15:0] INIT_57_BIN; + wire [15:0] INIT_58_BIN; + wire [15:0] INIT_59_BIN; + wire [15:0] INIT_5A_BIN; + wire [15:0] INIT_5B_BIN; + wire [15:0] INIT_5C_BIN; + wire [15:0] INIT_5D_BIN; + wire [15:0] INIT_5E_BIN; + wire [15:0] INIT_5F_BIN; + wire [15:0] INIT_60_BIN; + wire [15:0] INIT_61_BIN; + wire [15:0] INIT_62_BIN; + wire [15:0] INIT_63_BIN; + wire [15:0] INIT_64_BIN; + wire [15:0] INIT_65_BIN; + wire [15:0] INIT_66_BIN; + wire [15:0] INIT_67_BIN; + wire [15:0] INIT_68_BIN; + wire [15:0] INIT_69_BIN; + wire [15:0] INIT_6A_BIN; + wire [15:0] INIT_6B_BIN; + wire [15:0] INIT_6C_BIN; + wire [15:0] INIT_6D_BIN; + wire [15:0] INIT_6E_BIN; + wire [15:0] INIT_6F_BIN; + wire [15:0] INIT_70_BIN; + wire [15:0] INIT_71_BIN; + wire [15:0] INIT_72_BIN; + wire [15:0] INIT_73_BIN; + wire [15:0] INIT_74_BIN; + wire [15:0] INIT_75_BIN; + wire [15:0] INIT_76_BIN; + wire [15:0] INIT_77_BIN; + wire [15:0] INIT_78_BIN; + wire [15:0] INIT_79_BIN; + wire [15:0] INIT_7A_BIN; + wire [15:0] INIT_7B_BIN; + wire [15:0] INIT_7C_BIN; + wire [15:0] INIT_7D_BIN; + wire [15:0] INIT_7E_BIN; + wire [15:0] INIT_7F_BIN; + wire IS_CONVSTCLK_INVERTED_BIN; + wire IS_DCLK_INVERTED_BIN; + wire [1:0] SIM_DEVICE_BIN; + wire SIM_MONITOR_FILE_BIN; + wire [9:0] SYSMON_VUSER0_BANK_BIN; + wire SYSMON_VUSER0_MONITOR_BIN; + wire [9:0] SYSMON_VUSER1_BANK_BIN; + wire SYSMON_VUSER1_MONITOR_BIN; + wire [9:0] SYSMON_VUSER2_BANK_BIN; + wire SYSMON_VUSER2_MONITOR_BIN; + wire [9:0] SYSMON_VUSER3_BANK_BIN; + wire SYSMON_VUSER3_MONITOR_BIN; + + `ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; + `else + reg attr_test = 1'b0; + `endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + reg BUSY_out; + reg DRDY_out; + reg EOC_out; + reg EOS_out; + wire I2C_SCLK_TS_out; + reg I2C_SDA_TS_out; + wire JTAGBUSY_out; + wire JTAGLOCKED_out; + wire JTAGMODIFIED_out; + reg OT_out; + reg SMBALERT_TS_out; + reg [15:0] ADC_DATA_out; + reg [15:0] ALM_out; + reg [15:0] DO_out; + reg [4:0] MUXADDR_out; + reg [5:0] CHANNEL_out; + + wire CONVSTCLK_in; + wire CONVST_in; + wire DCLK_in; + wire DEN_in; + wire DWE_in; + wire I2C_SCLK_in; + wire I2C_SDA_in; + wire RESET_in; + wire VN_in; + wire VP_in; + wire [15:0] DI_in; + wire [15:0] VAUXN_in; + wire [15:0] VAUXP_in; + wire [7:0] DADDR_in; + + +`ifdef XIL_TIMING + wire DCLK_delay; + wire DEN_delay; + wire DWE_delay; + wire [15:0] DI_delay; + wire [7:0] DADDR_delay; +`endif + + assign ADC_DATA = ADC_DATA_out; + assign ALM = ALM_out; + assign BUSY = BUSY_out; + assign CHANNEL = CHANNEL_out; + assign DO = DO_out; + assign DRDY = DRDY_out; + assign EOC = EOC_out; + assign EOS = EOS_out; + assign I2C_SCLK_TS = I2C_SCLK_TS_out; + assign I2C_SDA_TS = I2C_SDA_TS_out; + assign JTAGBUSY = JTAGBUSY_out; + assign JTAGLOCKED = JTAGLOCKED_out; + assign JTAGMODIFIED = JTAGMODIFIED_out; + assign MUXADDR = MUXADDR_out; + assign OT = OT_out; + assign SMBALERT_TS = SMBALERT_TS_out; + + wire [7:0] DADDR_inv; + wire DCLK_inv; + wire DEN_inv; + wire DWE_inv; + wire RESET_in_inv; + wire [15:0] DI_inv; + wire I2C_SCLK_inv; + wire I2C_SDA_inv; + + `ifdef XIL_TIMING + assign DADDR_inv = DADDR_delay; + assign DCLK_inv = DCLK_delay; + assign DEN_inv = DEN_delay; + assign DI_inv = DI_delay; + assign DWE_inv = DWE_delay; + `else + assign DADDR_inv = DADDR; + assign DCLK_inv = DCLK; + assign DEN_inv = DEN; + assign DI_inv = DI; + assign DWE_inv = DWE; + `endif + assign I2C_SCLK_inv = I2C_SCLK; + assign I2C_SDA_inv = I2C_SDA; + + assign DADDR_in = DADDR_inv ^ 7'b0000000; + assign DCLK_in = DCLK_inv ^ IS_DCLK_INVERTED_BIN; + assign DEN_in = DEN_inv ^ 1'b0; + assign DI_in = DI_inv ^ 16'h0000; + assign DWE_in = DWE_inv ^ 1'b0; + assign RESET_in = RESET; + assign CONVSTCLK_in = CONVSTCLK ^ IS_CONVSTCLK_INVERTED_BIN; + assign CONVST_in = CONVST ^ 1'b0; + assign I2C_SCLK_in = I2C_SCLK_inv ^ 1'b0; + assign I2C_SDA_in = I2C_SDA_inv ^ 1'b0; + assign VAUXN_in = VAUXN; + assign VAUXP_in = VAUXP; + assign VN_in = VN; + assign VP_in = VP; + + assign COMMON_N_SOURCE_BIN = COMMON_N_SOURCE_REG; + + assign INIT_40_BIN = INIT_40_REG; + + assign INIT_41_BIN = INIT_41_REG; + + assign INIT_42_BIN = INIT_42_REG; + + assign INIT_43_BIN = INIT_43_REG; + + assign INIT_44_BIN = INIT_44_REG; + + assign INIT_45_BIN = INIT_45_REG; + + assign INIT_46_BIN = INIT_46_REG; + + assign INIT_47_BIN = INIT_47_REG; + + assign INIT_48_BIN = INIT_48_REG; + + assign INIT_49_BIN = INIT_49_REG; + + assign INIT_4A_BIN = INIT_4A_REG; + + assign INIT_4B_BIN = INIT_4B_REG; + + assign INIT_4C_BIN = INIT_4C_REG; + + assign INIT_4D_BIN = INIT_4D_REG; + + assign INIT_4E_BIN = INIT_4E_REG; + + assign INIT_4F_BIN = INIT_4F_REG; + + assign INIT_50_BIN = INIT_50_REG; + + assign INIT_51_BIN = INIT_51_REG; + + assign INIT_52_BIN = INIT_52_REG; + + assign INIT_53_BIN = INIT_53_REG; + + assign INIT_54_BIN = INIT_54_REG; + + assign INIT_55_BIN = INIT_55_REG; + + assign INIT_56_BIN = INIT_56_REG; + + assign INIT_57_BIN = INIT_57_REG; + + assign INIT_58_BIN = INIT_58_REG; + + assign INIT_59_BIN = INIT_59_REG; + + assign INIT_5A_BIN = INIT_5A_REG; + + assign INIT_5B_BIN = INIT_5B_REG; + + assign INIT_5C_BIN = INIT_5C_REG; + + assign INIT_5D_BIN = INIT_5D_REG; + + assign INIT_5E_BIN = INIT_5E_REG; + + assign INIT_5F_BIN = INIT_5F_REG; + + assign INIT_60_BIN = INIT_60_REG; + + assign INIT_61_BIN = INIT_61_REG; + + assign INIT_62_BIN = INIT_62_REG; + + assign INIT_63_BIN = INIT_63_REG; + + assign INIT_64_BIN = INIT_64_REG; + + assign INIT_65_BIN = INIT_65_REG; + + assign INIT_66_BIN = INIT_66_REG; + + assign INIT_67_BIN = INIT_67_REG; + + assign INIT_68_BIN = INIT_68_REG; + + assign INIT_69_BIN = INIT_69_REG; + + assign INIT_6A_BIN = INIT_6A_REG; + + assign INIT_6B_BIN = INIT_6B_REG; + + assign INIT_6C_BIN = INIT_6C_REG; + + assign INIT_6D_BIN = INIT_6D_REG; + + assign INIT_6E_BIN = INIT_6E_REG; + + assign INIT_6F_BIN = INIT_6F_REG; + + assign INIT_70_BIN = INIT_70_REG; + + assign INIT_71_BIN = INIT_71_REG; + + assign INIT_72_BIN = INIT_72_REG; + + assign INIT_73_BIN = INIT_73_REG; + + assign INIT_74_BIN = INIT_74_REG; + + assign INIT_75_BIN = INIT_75_REG; + + assign INIT_76_BIN = INIT_76_REG; + + assign INIT_77_BIN = INIT_77_REG; + + assign INIT_78_BIN = INIT_78_REG; + + assign INIT_79_BIN = INIT_79_REG; + + assign INIT_7A_BIN = INIT_7A_REG; + + assign INIT_7B_BIN = INIT_7B_REG; + + assign INIT_7C_BIN = INIT_7C_REG; + + assign INIT_7D_BIN = INIT_7D_REG; + + assign INIT_7E_BIN = INIT_7E_REG; + + assign INIT_7F_BIN = INIT_7F_REG; + + assign IS_CONVSTCLK_INVERTED_BIN = IS_CONVSTCLK_INVERTED_REG; + + assign IS_DCLK_INVERTED_BIN = IS_DCLK_INVERTED_REG; + + // assign SIM_DEVICE_BIN = + // (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS : + // (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 : + // (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE") ? SIM_DEVICE_ZYNQ_ULTRASCALE : + // (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE_ES1") ? SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 : + // SIM_DEVICE_ULTRASCALE_PLUS; + // + // assign SIM_MONITOR_FILE_BIN = + // (SIM_MONITOR_FILE_REG == "design.txt") ? SIM_MONITOR_FILE_design_txt : + // SIM_MONITOR_FILE_design_txt; + // + assign SYSMON_VUSER0_BANK_BIN = SYSMON_VUSER0_BANK_REG; + + // assign SYSMON_VUSER0_MONITOR_BIN = + // (SYSMON_VUSER0_MONITOR_REG == "NONE") ? SYSMON_VUSER0_MONITOR_NONE : + // SYSMON_VUSER0_MONITOR_NONE; + + assign SYSMON_VUSER1_BANK_BIN = SYSMON_VUSER1_BANK_REG; + + // assign SYSMON_VUSER1_MONITOR_BIN = + // (SYSMON_VUSER1_MONITOR_REG == "NONE") ? SYSMON_VUSER1_MONITOR_NONE : + // SYSMON_VUSER1_MONITOR_NONE; + + assign SYSMON_VUSER2_BANK_BIN = SYSMON_VUSER2_BANK_REG; + + // assign SYSMON_VUSER2_MONITOR_BIN = + // (SYSMON_VUSER2_MONITOR_REG == "NONE") ? SYSMON_VUSER2_MONITOR_NONE : + // SYSMON_VUSER2_MONITOR_NONE; + + assign SYSMON_VUSER3_BANK_BIN = SYSMON_VUSER3_BANK_REG; + + // assign SYSMON_VUSER3_MONITOR_BIN = + // (SYSMON_VUSER3_MONITOR_REG == "NONE") ? SYSMON_VUSER3_MONITOR_NONE : + // SYSMON_VUSER3_MONITOR_NONE; + + initial begin + trig_attr = 0; + #1; + trig_i2c_addr = 1; + trig_attr = 1; + #2 trig_dep_attr = 1; + end + + time time_check; + + always @(posedge trig_attr) begin + #1; + time_check=$time; + if(time_check != 2) + $display("Warning: [Unisim %s-69] SYSMONE4 time resolution has been overridden. It should be left as picoseconds. The model will not function correctly this way.", MODULE_NAME); + + if ((attr_test == 1'b1) || + ((SIM_DEVICE != "ULTRASCALE_PLUS") && + (SIM_DEVICE != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE != "ULTRASCALE_PLUS_ES2") && + (SIM_DEVICE != "ZYNQ_ULTRASCALE") && + (SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1") && + (SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2") + )) begin + $display("Error: [Unisim %s-168] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, ZYNQ_ULTRASCALE, ZYNQ_ULTRASCALE_ES1, or ZYNQ_ULTRASCALE_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER0_BANK_REG < 0) || (SYSMON_VUSER0_BANK_REG > 999))) begin + $display("Error: [Unisim %s-170] SYSMON_VUSER0_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER0_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER1_BANK_REG < 0) || (SYSMON_VUSER1_BANK_REG > 999))) begin + $display("Error: [Unisim %s-172] SYSMON_VUSER1_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER1_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER2_BANK_REG < 0) || (SYSMON_VUSER2_BANK_REG > 999))) begin + $display("Error: [Unisim %s-174] SYSMON_VUSER2_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER2_BANK_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SYSMON_VUSER3_BANK_REG < 0) || (SYSMON_VUSER3_BANK_REG > 999))) begin + $display("Error: [Unisim %s-176] SYSMON_VUSER3_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER3_BANK_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) + #1 $finish; + + end // always @ (trig_attr) + + + always @(trig_dep_attr) begin + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[8]==1) && (INIT_40_BIN[5:0] != 6'b000011) && (INIT_40_BIN[5:0] < 6'b010000))) + $display("Warning: [Unisim %s-1] INIT_40 attribute is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_40_BIN); + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]!=4'b0011) && (INIT_4E_BIN[10:0]!=11'd0) && (INIT_4E_BIN[15:12]!=4'd0))) + $display("Warning: [Unisim %s-2] INIT_4E attribute is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_4E_BIN); + + if ((attr_test == 1'b1) || + ((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[13:12]!=2'b00) && (INIT_46_BIN != 16'h0000) && (INIT_48_BIN != 16'h0000) && (INIT_49_BIN != 16'h0000))) + $display("Warning: [Unisim %s-3] INIT_46, INIT_48 and INIT_49 attributes are set to %x, %x, and %x respectively. These attributes must be set to 0000h in single channel mode with averaging enabled. Instance: %m", MODULE_NAME, INIT_46_BIN, INIT_48_BIN, INIT_49_BIN); + + if ((attr_test == 1'b1) || // CR 952216 + (INIT_44_BIN[3:0]!=4'b0000)) + $display("Info: [Unisim %s-59] INIT_44[3:0] is set to %0b. For related VUSER banks, where 0-6V range has been selected, analog input file must reflect the selected input range. Instance: %m", MODULE_NAME, INIT_44_BIN[3:0]); + + end // always @ (trig_dep_attr) + + + // Total UNISIM %s- warning message next: 70 + + localparam CONV_CNT_P = 37; + localparam CONV_CNT = 48; + + //sequencer operation + localparam [3:0] SEQ_DEFAULT_MODE = 4'b0000 ; + localparam [1:0] SEQ_DEFAULT_MODE2 = 2'b11 ; + localparam [3:0] SEQ_SINGLE_PASS = 4'b0001 ; + localparam [3:0] SEQ_CONT_CHAN = 4'b0010 ; + localparam [3:0] SEQ_SINGLE_CHAN = 4'b0011 ;//means sequencer is off + + //lr_rate + localparam [1:0] LR_EVERY_OTHER = 2'b00; + localparam [1:0] LR_EVERY_4TH = 2'b01; + localparam [1:0] LR_EVERY_16TH = 2'b10; + localparam [1:0] LR_EVERY_64TH = 2'b11; + + localparam [1:0] LR_EOS_HR_ONLY1 = 2'b00; + localparam [1:0] LR_EOS_LR_ONLY = 2'b01; + localparam [1:0] LR_EOS_HR_LR = 2'b10; + localparam [1:0] LR_EOS_HR_ONLY2 = 2'b11; + + + localparam OT_LIMIT_DEFAULT = 16'hCB03; + + //adc_state + localparam ST_A_FIRST_CALIB = 0, + ST_A_CALIB = 1, + ST_A_WAIT = 2, + ST_A_CHAN = 3, + ST_A_ALM = 4, + ST_A_EOC = 5, + ST_A_WAIT_ED = 6; + + localparam CMD_PAGE = 8'h00; + localparam CMD_CLEAR_FAULT = 8'h03; + localparam CMD_CAPABILITY = 8'h19; + localparam CMD_VOUT_MODE = 8'h20; + localparam CMD_VOUT_OV_FAULT_LIMIT = 8'h40; + localparam CMD_VOUT_UV_FAULT_LIMIT = 8'h44; + localparam CMD_OT_FAULT_LIMIT = 8'h4F; + localparam CMD_OT_WARNING_LIMIT = 8'h51; + localparam CMD_UT_WARNING_LIMIT = 8'h52; + localparam CMD_UT_FAULT_LIMIT = 8'h53; + localparam CMD_STATUS_BYTE = 8'h78; + localparam CMD_STATUS_WORD = 8'h79; + localparam CMD_STATUS_VOUT = 8'h7A; + localparam CMD_STATUS_TEMPERATURE = 8'h7D; + localparam CMD_STATUS_CML = 8'h7E; + localparam CMD_READ_VOUT = 8'h88; + localparam CMD_READ_TEMPERATURE_1 = 8'h8D; + localparam CMD_PMBUS_REVISION = 8'h98; + localparam CMD_MFR_ID = 8'h99; + localparam CMD_MFR_MODEL = 8'h9A; + localparam CMD_MFR_REVISION = 8'h9B; + localparam CMD_MFR_SELECT_REG = 8'hD0; + localparam CMD_MFR_ACCESS_REG = 8'hD1; + localparam CMD_MFR_READ_VOUT_MAX = 8'hD2; + localparam CMD_MFR_READ_VOUT_MIN = 8'hD3; + localparam CMD_MFR_ENABLE_VUSER_HR = 8'hD5; + localparam CMD_MFR_READ_TEMP_MAX = 8'hD6; + localparam CMD_MFR_READ_TEMP_MIN = 8'hD7; + + localparam eoc_distance = 18; + localparam alm_distance = 15; + + time time_out; + time prev_time_out; + + integer temperature_index = -1; + integer time_index = -1; + integer vccaux_index = -1; + integer vccbram_index = -1; + integer vccint_index = -1; + integer vn_index = -1; + integer vp_index = -1; + integer vccpsintlp_index = -1; + integer vccpsintfp_index = -1; + integer vccpsaux_index = -1; + integer vauxp_idx[15:0]; + integer vauxn_idx[15:0]; + integer vuser0_index = -1; + integer vuser1_index = -1; + integer vuser2_index = -1; + integer vuser3_index = -1; + integer char_1; + integer char_2; + integer fs; + integer fd; + integer num_arg; + integer num_val; + integer adcclk_count; + reg adcclk_count_rst = 0; + wire adcclk_period_start; + wire adcclk_period_end; + reg adcclk_period_end_d; + wire [8:0] avg_amount; + wire avg_en; + wire [1:0] averaging; + wire avg_final_loop; + wire avg_final_loop_hr; + wire avg_final_loop_lr; + wire seq_lr_selected_p; + reg seq_lr_selected; + reg [1:0] seq_lr_selected_d; + reg add_channel_hr_p; + reg add_channel_lr_p; + reg add_channel; + integer conv_acc [63:0]; + integer conv_result_int; + integer h, i, j, k, l, m, n, p; + integer file_line; + + // string + reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46; + reg [8*600:1] one_line; + reg [8*12:1] label [46:0]; + reg [8*12:1] tmp_label; + reg end_of_file; + + real tmp_va0; + real tmp_va1; + real column_real00; + real column_real100; + real column_real101; + real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46; + + // array of real numbers + reg [63:0] column_real [CONV_CNT-1 :0]; + reg [63:0] chan_val [CONV_CNT_P-1:0]; + reg [63:0] chan_val_tmp [CONV_CNT_P-1:0]; + reg [63:0] chan_valn [CONV_CNT_P-1:0]; + reg [63:0] chan_valn_tmp [CONV_CNT_P-1:0]; + reg [63:0] mn_in_diff [CONV_CNT_P-1:0]; + reg [63:0] mn_in2_diff [CONV_CNT_P-1:0]; + reg [63:0] mn_in_uni [CONV_CNT_P-1:0]; + reg [63:0] mn_in2_uni [CONV_CNT_P-1:0]; + reg [63:0] mn_comm_in [CONV_CNT_P-1:0]; + reg [63:0] mn_comm2_in [CONV_CNT_P-1:0]; + + real chan_val_p_tmp; + real chan_val_n_tmp; + real mn_mux_in; + real mn_in_tmp; + real mn_comm_in_tmp; + real mn_in_comm; + real tmp_v; + real tmp_v1; + real adc_temp_result; + real adc_intpwr_result; + real adc_ext_result; + + reg init_rst; + reg [2:0] initialize; + reg int_rst_sync1; + reg int_rst_sync2; + wire int_rst_combined; + wire int_rst_combined_d; + reg alm_rst; + reg seq_rst; + reg soft_rst = 0; + reg en_data_flag; + wire [15:0] flag_reg0; + wire [15:0] flag_reg1; + reg [15:0] ot_limit_reg = OT_LIMIT_DEFAULT; + reg [15:0] tmp_otv; + reg [23:0] conv_acc_vec; + reg [15:0] conv_result; + reg [15:0] conv_result_reg; + reg [15:0] conv_acc_result; + wire [7:0] curr_clkdiv_sel; + reg [15:0] alm_out_reg; + reg [15:0] data_written; + reg [2:0] adc_state; + reg [2:0] adc_next_state; + reg [2:0] adc_state_d_dclk; + reg [2:0] adc_state_d; + reg st_first_calib_chan; + + reg DRDY_out_pre1; + reg DRDY_out_pre2; + reg DRDY_out_pre3; + reg ot_out_reg; + reg ut_fault; + reg ut_warn; + reg ut_fault_reg; //under temperature fault register for PMBus capability. + reg ut_warn_reg; //under temperature warning register for PMBus capability. + reg [15:0] alm_ut_reg; //under temperature fault registers for PMBUS capability + reg [11:1] alm_ut; + reg [15:0] DO_out_rdtmp; + reg [15:0] data_reg [63:0]; + reg [15:0] dr_sram [255:64]; + reg sysclk; + reg adcclk_tmp; + wire adcclk; + wire adcclk_div1; + + wire ext_mux; + wire ext_mux_en; + wire [5:0] ext_mux_chan_id; + wire [5:0] single_chan_id; + wire default_mode; + wire single_pass_mode; + wire single_pass_active; + wire cont_seq_mode; + wire single_chan_mode; + wire event_driven_mode; + wire cont_sampl_mode; + wire bipolar_mode; + reg single_pass_finished; + reg single_pass_finished_d; + wire single_pass_finished_pe; + + reg sim_file_flag; + reg [7:0] DADDR_in_lat; + wire [3:0] op_mode; + reg [3:0] seq_bits; + reg ot_en; + reg [13:0] alm_en; + wire [15:0] seq_hr_chan_reg1; + wire [15:0] seq_hr_chan_reg2; + wire [15:0] seq_hr_chan_reg3; + wire [47:0] seq_hr_chan_reg_comb; + wire [15:0] seq_lr_chan_reg1; + wire [15:0] seq_lr_chan_reg2; + wire [15:0] seq_lr_chan_reg3; + wire [47:0] seq_lr_chan_reg_comb; + wire [15:0] seq_acq_ext_reg1; + wire [15:0] seq_acq_ext_reg2; + wire [47:0] seq_acq_ext_reg_comb; + wire [15:0] seq_avg_reg1; + wire [15:0] seq_avg_reg2; + wire [15:0] seq_avg_reg3; + wire [15:0] seq_bipolar_reg1; + wire [15:0] seq_bipolar_reg2; + wire [47:0] seq_bipolar_reg_comb; + + reg [5:0] seq_curr_i, seq_curr_ia; + integer busy_rst_cnt; + reg [5:0] si; + integer kk; + integer hr_tot_chan; + integer lr_tot_chan; + wire [15:0] int_tot_per; + wire [15:0] hr_lr_tot_per; + wire [15:0] tot_per; + integer seq_hr_mem [CONV_CNT_P:0]; + integer seq_lr_mem [CONV_CNT_P:0]; + + wire lr_chan_on; + wire cont_seq_only_hr; + reg lr_calib_on; + + wire sysmon_rst; + wire [15:0] cfg_reg0; + wire [15:0] cfg_reg1; + wire [15:0] cfg_reg2; + wire [15:0] cfg_reg3; + wire [15:0] cfg_reg4; + reg reserved_addr_pre; + reg read_only_pre; + //blh tests related + wire blh_test=0; + integer blh_read_index=0; + reg RESERVED_ADDR; + reg READ_ONLY; + + wire convst_in_ored; + wire convst_in_pre; + wire rst_in_not_seq; + wire gsr_in; + reg [1:0] lr_eos ; + reg [1:0] lr_rate; + + real i2c_vpvn_addr_tmp; + integer i2c_conv_result_int; + reg i2c_en; + reg i2c_oride; + reg [6:0] i2c_device_addr; + reg [6:0] i2c_device_addr_vpvn; + reg [15:0] conv_result_i2c_addr; + wire i2c_wr_exec; + wire [15:0] i2c_drp_data; + wire [9:0] i2c_drp_addr; + wire pmb_en_bit; + wire pmb_en; + reg [7:0] pmb_sel_addr; //select address for MFR command + reg [7 :0] pmb_drsram_addr; + reg [15:0] pmb_drsram_wr_data; + reg [3:0] pmb_drsram_bit_idx; + reg [7:0] pmb_drsram_addr_page; + reg pmb_valid_page; + reg pmb_wr_exec; + reg [7:0] pmb_cmd_in; + reg [15:0] pmb_data_in; + wire [3:0] bank_sel_6V; //indicates if 6V bank has been selected for vuser0-3. + + assign JTAGBUSY_out = 0; + assign JTAGLOCKED_out = 0; + assign JTAGMODIFIED_out = 0; + assign gsr_in = glblGSR; + + //-------------------------------------------------- + //-------------------------------------------------- + integer out_counter; + integer ed_counter; + integer cs_counter; + integer cal_counter; + + reg out_counter_inc; + reg ed_counter_inc; + wire chan_asrt_1; + wire chan_asrt_2; + wire chan_asrt_3; + reg chan_asrt_4; + reg chan_asrt_5; + reg chan_asrt_6; + wire alm_asrt; + wire eoc_asrt; + wire busy_start; + wire busy_end; + wire busy_end_out; + wire busy_start_ed; + wire busy_start_cs; + reg busy_start_cs_d; + wire busy_end_ed; + wire busy_end_ed_out; + wire busy_end_ed_wait; + wire busy_end_cs; + wire busy_end_cs_out; + reg busy_end_d; + reg busy_end_out_d; + wire busy_end_pe; + wire chan_asrt; + wire chan_asrt_ed; + wire chan_asrt_cs; + wire chan_asrt_pe; + wire chan_asrt_dclk; + reg chan_asrt_d; + wire conv_track; + wire conv_track_ed; + wire conv_track_cs; + wire cal_end_level; + reg cal_end_level_d; + wire cal_end; + wire convst_pre_dclk_pe; + wire convst_pre_adcclk_pe; + reg convst_saved; + reg convst_adcclk_d1; + reg convst_adcclk_d2; + reg convst_dclk_d1; + reg one_pass_end; + wire [3:0] cal_factor; + wire [3:0] cal_factor2; + wire [8:0] first_cal_limit; + wire [8:0] later_cal_limit; + wire [5:0] conv_period; + wire [4:0] busy_start_point; + wire [4:0] cs_count_tot; + wire [8:0] cal_limit; + reg conversion_before_calib; + reg tot_final_conversion; + reg hr_final_conversion; + reg lr_final_conversion; + + wire acq_ext; + reg acq_ext_cur; + reg acq_ext_cur_d; + reg bipolar_cur; + reg avg_cur; + integer chan_reg_id_cur; // the index number for accessing configuration registers + integer chan_out_id_cur; // the number that shows up at the output + reg acq_ext_next; + reg bipolar_next; + reg avg_next; + integer chan_reg_id_next; + integer chan_out_id_next; + + // initialize chan_val and chan_valn + integer ii, jj; + initial begin + for (ii = 0; ii < CONV_CNT_P; ii = ii + 1) + chan_val[ii] = 64'd0; + for (jj = 0; jj < 36; jj = jj + 1) + chan_valn[jj] = 64'd0; + end + + // initialize vauxn_idx and vauxp_idx + integer mm, nn; + initial begin + for (mm = 0; mm < 16; mm = mm + 1) + vauxn_idx[mm] = -1; + for (nn = 0; nn < 16; nn = nn + 1) + vauxp_idx[nn] = -1; + end + + + initial begin + i2c_en = 1; + pmb_sel_addr = 0; + end + + // I2C slave address mapping + always @(*) begin + i2c_oride = cfg_reg3[15]; + i2c_device_addr = (i2c_oride) ? cfg_reg3[14:8]: i2c_device_addr_vpvn; + end + + assign convst_in_ored = (CONVST_in===1 || CONVSTCLK_in===1) ? 1: 0; + assign convst_in_pre = sysmon_rst ? 0 : (convst_in_ored && event_driven_mode & ~BUSY_out); + + integer dd; + always @(posedge trig_attr) begin + dr_sram[8'h40] = INIT_40_BIN; + dr_sram[8'h41] = INIT_41_BIN; + dr_sram[8'h42] = INIT_42_BIN; + dr_sram[8'h43] = INIT_43_BIN; + dr_sram[8'h44] = INIT_44_BIN; + dr_sram[8'h45] = INIT_45_BIN; + dr_sram[8'h46] = INIT_46_BIN; + dr_sram[8'h47] = INIT_47_BIN; + dr_sram[8'h48] = INIT_48_BIN; + dr_sram[8'h49] = INIT_49_BIN; + dr_sram[8'h4A] = INIT_4A_BIN; + dr_sram[8'h4B] = INIT_4B_BIN; + dr_sram[8'h4C] = INIT_4C_BIN; + dr_sram[8'h4D] = INIT_4D_BIN; + dr_sram[8'h4E] = INIT_4E_BIN; + dr_sram[8'h4F] = INIT_4F_BIN; + dr_sram[8'h50] = INIT_50_BIN; + dr_sram[8'h51] = INIT_51_BIN; + dr_sram[8'h52] = INIT_52_BIN; + + // User can overwrite the ot_limit_reg only while enabling automatic shutdown. + // Otherwise default value will be kept. + tmp_otv = INIT_53_BIN; + if (tmp_otv [3:0] == 4'b0011) begin + dr_sram[8'h53] = INIT_53_BIN; + ot_limit_reg = INIT_53_BIN; + $display("Info: [Unisim %s-20] OT upper limit has been overwritten and automatic shutdown bits have been set 53h = h%0h. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, INIT_53_BIN, $time/1000.0,); + end + else begin + dr_sram[8'h53] = 16'hCB00; + ot_limit_reg = 16'hCB00; // default value for OT is 125C + end + + dr_sram[8'h54] = INIT_54_BIN; + dr_sram[8'h55] = INIT_55_BIN; + dr_sram[8'h56] = INIT_56_BIN; + dr_sram[8'h57] = INIT_57_BIN; + dr_sram[8'h58] = INIT_58_BIN; + dr_sram[8'h59] = INIT_59_BIN; + dr_sram[8'h5A] = INIT_5A_BIN; + dr_sram[8'h5B] = INIT_5B_BIN; + dr_sram[8'h5C] = INIT_5C_BIN; + dr_sram[8'h5D] = INIT_5D_BIN; + dr_sram[8'h5E] = INIT_5E_BIN; + dr_sram[8'h5F] = INIT_5F_BIN; + dr_sram[8'h60] = INIT_60_BIN; + dr_sram[8'h61] = INIT_61_BIN; + dr_sram[8'h62] = INIT_62_BIN; + dr_sram[8'h63] = INIT_63_BIN; + dr_sram[8'h68] = INIT_68_BIN; + dr_sram[8'h69] = INIT_69_BIN; + dr_sram[8'h6A] = INIT_6A_BIN; + dr_sram[8'h6B] = INIT_6B_BIN; + dr_sram[8'h78] = INIT_78_BIN; + dr_sram[8'h79] = INIT_79_BIN; + dr_sram[8'h7A] = INIT_7A_BIN; + dr_sram[8'h7B] = INIT_7B_BIN; + dr_sram[8'h7C] = INIT_7C_BIN; + + for (dd=8'h80; dd<8'hFF; dd=dd+1) + dr_sram[dd] = 0; + + dr_sram[8'hA8] = 16'hFFFF; //min vuser0 + dr_sram[8'hA9] = 16'hFFFF; + dr_sram[8'hAA] = 16'hFFFF; + dr_sram[8'hAB] = 16'hFFFF; + + end // always @ (trig_attr) + + + // read input file + initial begin + char_1 = 0; + char_2 = 0; + time_out = 0; + sim_file_flag = 0; + file_line = -1; + end_of_file = 0; + fd = $fopen(SIM_MONITOR_FILE, "r"); + if (fd == 0) begin + $display("Error: [Unisim %s-4] The analog data file %s was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt. Instance: %m", MODULE_NAME, SIM_MONITOR_FILE); + sim_file_flag = 1; + #1 $finish; + end + + if (sim_file_flag == 0) begin + while (end_of_file==0) begin + file_line = file_line + 1; + char_1 = $fgetc (fd); + char_2 = $fgetc (fd); + //if(char_2==`EOFile) + if(char_2== -1) + end_of_file = 1; + else begin // not end of file + // Ignore Comments + if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + // Getting labels + else if ((char_1 == "T" & char_2 == "I" ) || + (char_1 == "T" & char_2 == "i" ) || + (char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s ", + label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46); + + label[0] = label0; + label[1] = label1; + label[2] = label2; + label[3] = label3; + label[4] = label4; + label[5] = label5; + label[6] = label6; + label[7] = label7; + label[8] = label8; + label[9] = label9; + label[10] = label10; + label[11] = label11; + label[12] = label12; + label[13] = label13; + label[14] = label14; + label[15] = label15; + label[16] = label16; + label[17] = label17; + label[18] = label18; + label[19] = label19; + label[20] = label20; + label[21] = label21; + label[22] = label22; + label[23] = label23; + label[24] = label24; + label[25] = label25; + label[26] = label26; + label[27] = label27; + label[28] = label28; + label[29] = label29; + label[30] = label30; + label[31] = label31; + label[32] = label32; + label[33] = label33; + label[34] = label34; + label[35] = label35; + label[36] = label36; + label[37] = label37; + label[38] = label38; + label[39] = label39; + label[40] = label40; + label[41] = label41; + label[42] = label42; + label[43] = label43; + label[44] = label44; + label[45] = label45; + label[46] = label46; + + for (m = 0; m < num_arg; m = m +1) begin + tmp_label = 96'b0; + tmp_label = to_upcase_label(label[m]); + case (tmp_label) + "TEMP" : temperature_index = m; + "TIME" : time_index = m; + "VCCAUX" : vccaux_index = m; + "VCCINT" : vccint_index = m; + "VCCBRAM" : vccbram_index = m; + "VCCPSINTLP", + "VCC_PSINTLP" : + begin + vccpsintlp_index = m; + if (SIM_DEVICE != "ZYNQ_ULTRASCALE" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2") + $display("Error: [Unisim %s-22] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label); + if ("VCCPSINTLP" == tmp_label) + $display("Error: [Unisim %s-47] The channel name %s is deprecated. Please use VCC_PSINTLP instead. Instance: %m", MODULE_NAME, tmp_label); + end + "VCCPSINTFP", + "VCC_PSINTFP" : + begin + vccpsintfp_index = m; + if (SIM_DEVICE != "ZYNQ_ULTRASCALE" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2") + $display("Error: [Unisim %s-23] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label); + if ("VCCPSINTFP" == tmp_label) + $display("Error: [Unisim %s-48] The channel name %s is deprecated. Please use VCC_PSINTFP instead. Instance: %m", MODULE_NAME, tmp_label); + end + "VCCPSAUX", + "VCC_PSAUX" : begin + vccpsaux_index = m; + if (SIM_DEVICE != "ZYNQ_ULTRASCALE" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" && + SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2") + $display("Error: [Unisim %s-24] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label); + if ("VCCPSAUX" == tmp_label) + $display("Error: [Unisim %s-49] The channel name %s is deprecated. Please use VCC_PSAUX instead. Instance: %m", MODULE_NAME, tmp_label); + end + "VN" : vn_index = m; + "VAUXN[0]" : vauxn_idx[0] = m; + "VAUXN[1]" : vauxn_idx[1] = m; + "VAUXN[2]" : vauxn_idx[2] = m; + "VAUXN[3]" : vauxn_idx[3] = m; + "VAUXN[4]" : vauxn_idx[4] = m; + "VAUXN[5]" : vauxn_idx[5] = m; + "VAUXN[6]" : vauxn_idx[6] = m; + "VAUXN[7]" : vauxn_idx[7] = m; + "VAUXN[8]" : vauxn_idx[8] = m; + "VAUXN[9]" : vauxn_idx[9] = m; + "VAUXN[10]" : vauxn_idx[10] = m; + "VAUXN[11]" : vauxn_idx[11] = m; + "VAUXN[12]" : vauxn_idx[12] = m; + "VAUXN[13]" : vauxn_idx[13] = m; + "VAUXN[14]" : vauxn_idx[14] = m; + "VAUXN[15]" : vauxn_idx[15] = m; + "VP" : vp_index = m; + "VAUXP[0]" : vauxp_idx[0] = m; + "VAUXP[1]" : vauxp_idx[1] = m; + "VAUXP[2]" : vauxp_idx[2] = m; + "VAUXP[3]" : vauxp_idx[3] = m; + "VAUXP[4]" : vauxp_idx[4] = m; + "VAUXP[5]" : vauxp_idx[5] = m; + "VAUXP[6]" : vauxp_idx[6] = m; + "VAUXP[7]" : vauxp_idx[7] = m; + "VAUXP[8]" : vauxp_idx[8] = m; + "VAUXP[9]" : vauxp_idx[9] = m; + "VAUXP[10]" : vauxp_idx[10] = m; + "VAUXP[11]" : vauxp_idx[11] = m; + "VAUXP[12]" : vauxp_idx[12] = m; + "VAUXP[13]" : vauxp_idx[13] = m; + "VAUXP[14]" : vauxp_idx[14] = m; + "VAUXP[15]" : vauxp_idx[15] = m; + "VUSER0" : vuser0_index = m; + "VUSER1" : vuser1_index = m; + "VUSER2" : vuser2_index = m; + "VUSER3" : vuser3_index = m; + //"VCCAMS" : vccams_index = m; + default : begin + $display("Error: [Unisim %s-5] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label); + infile_format; + end + endcase + end // for (m = 0; m < num_arg; m = m +1) + + // COMMON_N_SOURCE + if(COMMON_N_SOURCE != 16'hFFFF && vauxn_idx[COMMON_N_SOURCE[3:0]] == -1) begin + $display("Warning: [Unisim %s-58]: Common-N Source is selected as VAUXN[%0d]. This input does not exist in the stimulus file. It must be provided.", + MODULE_NAME, COMMON_N_SOURCE[3:0]); + for (n = 0; n < 16; n = n + 1) begin + if ((vauxn_idx[n] == -1) && (vauxp_idx[n] != -1)) + vauxn_idx[n] = vauxn_idx[COMMON_N_SOURCE[3:0]]; + end // for + end + + end // Getting labels + + // Getting column values + else if (char_1 ==" " | char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + column_real0 = 0.0; + column_real1 = 0.0; + column_real2 = 0.0; + column_real3 = 0.0; + column_real4 = 0.0; + column_real5 = 0.0; + column_real6 = 0.0; + column_real7 = 0.0; + column_real8 = 0.0; + column_real9 = 0.0; + column_real10 = 0.0; + column_real11 = 0.0; + column_real12 = 0.0; + column_real13 = 0.0; + column_real14 = 0.0; + column_real15 = 0.0; + column_real16 = 0.0; + column_real17 = 0.0; + column_real18 = 0.0; + column_real19 = 0.0; + column_real20 = 0.0; + column_real21 = 0.0; + column_real22 = 0.0; + column_real23 = 0.0; + column_real24 = 0.0; + column_real25 = 0.0; + column_real26 = 0.0; + column_real27 = 0.0; + column_real28 = 0.0; + column_real29 = 0.0; + column_real30 = 0.0; + column_real31 = 0.0; + column_real32 = 0.0; + column_real33 = 0.0; + column_real34 = 0.0; + column_real35 = 0.0; + column_real36 = 0.0; + column_real37 = 0.0; + column_real38 = 0.0; + column_real39 = 0.0; + column_real40 = 0.0; + column_real41 = 0.0; + column_real42 = 0.0; + column_real43 = 0.0; + column_real44 = 0.0; + column_real45 = 0.0; + column_real46 = 0.0; + + num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46); + + column_real[0] = $realtobits(column_real0); + column_real[1] = $realtobits(column_real1); + column_real[2] = $realtobits(column_real2); + column_real[3] = $realtobits(column_real3); + column_real[4] = $realtobits(column_real4); + column_real[5] = $realtobits(column_real5); + column_real[6] = $realtobits(column_real6); + column_real[7] = $realtobits(column_real7); + column_real[8] = $realtobits(column_real8); + column_real[9] = $realtobits(column_real9); + column_real[10] = $realtobits(column_real10); + column_real[11] = $realtobits(column_real11); + column_real[12] = $realtobits(column_real12); + column_real[13] = $realtobits(column_real13); + column_real[14] = $realtobits(column_real14); + column_real[15] = $realtobits(column_real15); + column_real[16] = $realtobits(column_real16); + column_real[17] = $realtobits(column_real17); + column_real[18] = $realtobits(column_real18); + column_real[19] = $realtobits(column_real19); + column_real[20] = $realtobits(column_real20); + column_real[21] = $realtobits(column_real21); + column_real[22] = $realtobits(column_real22); + column_real[23] = $realtobits(column_real23); + column_real[24] = $realtobits(column_real24); + column_real[25] = $realtobits(column_real25); + column_real[26] = $realtobits(column_real26); + column_real[27] = $realtobits(column_real27); + column_real[28] = $realtobits(column_real28); + column_real[29] = $realtobits(column_real29); + column_real[30] = $realtobits(column_real30); + column_real[31] = $realtobits(column_real31); + column_real[32] = $realtobits(column_real32); + column_real[33] = $realtobits(column_real33); + column_real[34] = $realtobits(column_real34); + column_real[35] = $realtobits(column_real35); + column_real[36] = $realtobits(column_real36); + column_real[37] = $realtobits(column_real37); + column_real[38] = $realtobits(column_real38); + column_real[39] = $realtobits(column_real39); + column_real[40] = $realtobits(column_real40); + column_real[41] = $realtobits(column_real41); + column_real[42] = $realtobits(column_real42); + column_real[43] = $realtobits(column_real43); + column_real[44] = $realtobits(column_real44); + column_real[45] = $realtobits(column_real45); + column_real[46] = $realtobits(column_real46); + + chan_val[0] = column_real[temperature_index]; + chan_val[1] = column_real[vccint_index]; + chan_val[2] = column_real[vccaux_index]; + chan_val[3] = column_real[vp_index]; + chan_val[6] = column_real[vccbram_index]; + chan_val[13] = column_real[vccpsintlp_index]; + chan_val[14] = column_real[vccpsintfp_index]; + chan_val[15] = column_real[vccpsaux_index]; + chan_val[16] = column_real[vauxp_idx[0]]; + chan_val[17] = column_real[vauxp_idx[1]]; + chan_val[18] = column_real[vauxp_idx[2]]; + chan_val[19] = column_real[vauxp_idx[3]]; + chan_val[20] = column_real[vauxp_idx[4]]; + chan_val[21] = column_real[vauxp_idx[5]]; + chan_val[22] = column_real[vauxp_idx[6]]; + chan_val[23] = column_real[vauxp_idx[7]]; + chan_val[24] = column_real[vauxp_idx[8]]; + chan_val[25] = column_real[vauxp_idx[9]]; + chan_val[26] = column_real[vauxp_idx[10]]; + chan_val[27] = column_real[vauxp_idx[11]]; + chan_val[28] = column_real[vauxp_idx[12]]; + chan_val[29] = column_real[vauxp_idx[13]]; + chan_val[30] = column_real[vauxp_idx[14]]; + chan_val[31] = column_real[vauxp_idx[15]]; + chan_val[32] = column_real[vuser0_index]; + chan_val[33] = column_real[vuser1_index]; + chan_val[34] = column_real[vuser2_index]; + chan_val[35] = column_real[vuser3_index]; + + chan_valn[3] = column_real[vn_index]; + chan_valn[16] = column_real[vauxn_idx[0]]; + chan_valn[17] = column_real[vauxn_idx[1]]; + chan_valn[18] = column_real[vauxn_idx[2]]; + chan_valn[19] = column_real[vauxn_idx[3]]; + chan_valn[20] = column_real[vauxn_idx[4]]; + chan_valn[21] = column_real[vauxn_idx[5]]; + chan_valn[22] = column_real[vauxn_idx[6]]; + chan_valn[23] = column_real[vauxn_idx[7]]; + chan_valn[24] = column_real[vauxn_idx[8]]; + chan_valn[25] = column_real[vauxn_idx[9]]; + chan_valn[26] = column_real[vauxn_idx[10]]; + chan_valn[27] = column_real[vauxn_idx[11]]; + chan_valn[28] = column_real[vauxn_idx[12]]; + chan_valn[29] = column_real[vauxn_idx[13]]; + chan_valn[30] = column_real[vauxn_idx[14]]; + chan_valn[31] = column_real[vauxn_idx[15]]; + + + // identify columns + if (time_index != -1) begin + prev_time_out = time_out; + time_out = $bitstoreal(column_real[time_index]); + if (prev_time_out > time_out) begin + $display("Error: [Unisim %s-6] Time value %f is invalid in the input file. Time value should be increasing. Instance: %m", MODULE_NAME, time_out); + infile_format; + end + end + else begin + $display("Error: [Unisim %s-7] No TIME label is found in the analog data file. Instance: %m", MODULE_NAME); + infile_format; + #1 $finish; + end + + # ((time_out - prev_time_out) * 1000); + + for (p = 0; p < CONV_CNT_P; p = p + 1) begin + // assign to real before minus - to work around a bug in modelsim + chan_val_tmp[p] = chan_val[p]; + chan_valn_tmp[p] = chan_valn[p]; + mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]); + mn_in_diff[p] = $realtobits(mn_in_tmp); + mn_in_uni[p] = chan_val[p]; + end + end // if (char_1 == "0" | char_1 == "9") + // Ignore any non-comment, label + else begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + end + end // while (end_file == 0) + + + end // if (sim_file_flag == 0) + end // initial begin + + always@(posedge chan_asrt_1) begin + if(sysmon_rst==0 && blh_test==1) begin + blh_read_index = chan_out_id_next; + chan_val_tmp [blh_read_index] = chan_val[blh_read_index]; + chan_valn_tmp[blh_read_index] = chan_valn[blh_read_index]; + mn_in_tmp = $bitstoreal(chan_val [blh_read_index]) + - $bitstoreal(chan_valn[blh_read_index]); + mn_in_diff[blh_read_index] = $realtobits(mn_in_tmp); + mn_in_uni[blh_read_index] = chan_val[blh_read_index]; + end + end + + // Obtain I2C slave address powerup value + always @(posedge trig_i2c_addr) begin + i2c_vpvn_addr_tmp = $bitstoreal(mn_in_uni[3]) * 65536.0; + if (i2c_vpvn_addr_tmp > 65535.0) + i2c_conv_result_int = 65535; + else if (i2c_vpvn_addr_tmp < 0.0) + i2c_conv_result_int = 0; + else begin + i2c_conv_result_int = $rtoi(i2c_vpvn_addr_tmp); + if (i2c_vpvn_addr_tmp - i2c_conv_result_int > 0.9999) + i2c_conv_result_int = i2c_conv_result_int + 1; + end + // I2C address measured and assigned at startup is recorded at address 38h + conv_result_i2c_addr = i2c_conv_result_int; + if(!i2c_oride) + data_reg[56] = i2c_conv_result_int; + + + // convert i2c address + case (conv_result_i2c_addr[15:12]) + 4'h0 : i2c_device_addr_vpvn = 7'b0110010; + 4'h1 : i2c_device_addr_vpvn = 7'b0001011; + 4'h2 : i2c_device_addr_vpvn = 7'b0010011; + 4'h3 : i2c_device_addr_vpvn = 7'b0011011; + 4'h4 : i2c_device_addr_vpvn = 7'b0100011; + 4'h5 : i2c_device_addr_vpvn = 7'b0101011; + 4'h6 : i2c_device_addr_vpvn = 7'b0110011; + 4'h7 : i2c_device_addr_vpvn = 7'b0111011; + 4'h8 : i2c_device_addr_vpvn = 7'b1000011; + 4'h9 : i2c_device_addr_vpvn = 7'b1001011; + 4'ha : i2c_device_addr_vpvn = 7'b1010011; + 4'hb : i2c_device_addr_vpvn = 7'b1011011; + 4'hc : i2c_device_addr_vpvn = 7'b1100011; + 4'hd : i2c_device_addr_vpvn = 7'b1101011; + 4'he : i2c_device_addr_vpvn = 7'b1110011; + 4'hf : i2c_device_addr_vpvn = 7'b0111010; + default : begin + i2c_device_addr_vpvn = 7'b0000000; + //$display("Warning: [Unisim %s-25] Invalid I2C address is found. Instance: %m", MODULE_NAME); + end + endcase + end + + task infile_format; + begin + $display("\n***** SYSMONE4 Simulation analog Data File Format *****\n"); + $display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n"); + $display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VCCBRAM VCC_PSINTLP VCC_PSINTFP VCC_PSAUX VP VN VAUXP[0] VAUXN[0] ..... \n"); + $display("TIME must be in first column.\n"); + $display("Time values need to be integer in ns scale.\n"); + $display("Analog values need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n"); + $display("Each line including header line can not have extra space after the last character/digit.\n"); + $display("Each data line must have the same number of columns as the header line.\n"); + $display("Comment line can start with -- or //\n"); + $display("Example:\n"); + $display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n"); + $display("000 125.6 1.0 0.7 0.4 0.3 0.6\n"); + $display("200 25.6 0.8 0.5 0.3 0.8 0.2\n"); + end + endtask //task infile_format + + function [12*8:1] to_upcase_label; + input [12*8:1] in_label; + reg [8:1] tmp_reg; + begin + for (i=0; i< 12; i=i+1) begin + for (j=1; j<=8; j= j+1) + tmp_reg[j] = in_label[i*8+j]; + if ((tmp_reg >96) && (tmp_reg<123)) + tmp_reg = tmp_reg -32; + for (j=1; j<=8; j= j+1) + to_upcase_label[i*8+j] = tmp_reg[j]; + end + end + endfunction + + // end read input file + + //convert combined register index to channel output + //or vice-a-versa + function [5:0] conv_combregid_to_chanout; + input [5:0] combregid; //unsigned + begin + // invalid channel outputs are 7, 9-12, and >=36. They show up as selected via registers + if(combregid<=7) + conv_combregid_to_chanout = combregid+8; + else if(combregid>=8 && combregid<=15) + conv_combregid_to_chanout = combregid-8; + else + conv_combregid_to_chanout = combregid; + end + endfunction + + always @(posedge DCLK_in or posedge sysmon_rst ) begin + if (sysmon_rst==1) + MUXADDR_out <= 5'b0; + else begin + if(ext_mux_en==0) + MUXADDR_out <= 5'b0; + else if((|initialize) || adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB) + MUXADDR_out <= 8; // stay in calibration until first channel conversion + else if(chan_asrt_6==1 || (CHANNEL_out==8 && busy_end_out_d )) + MUXADDR_out <= chan_out_id_next; + end + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst==1) + CHANNEL_out <= 8; + else begin + if((|initialize) || chan_asrt_6==1) + CHANNEL_out <= chan_out_id_cur; + end + end + + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst==1) + ADC_DATA_out <= 0; + else if(eoc_asrt==1) begin + if (chan_out_id_cur >= 32) + ADC_DATA_out <= dr_sram[chan_out_id_cur + 96]; + else if (chan_out_id_cur >= 0 && chan_out_id_cur <= 31) + ADC_DATA_out <= data_reg[chan_out_id_cur]; + end + end + + //----------------------------------------------------------------- + // internal reset generation + //----------------------------------------------------------------- + + initial begin + alm_rst = 0; + init_rst = 1; + if (RESET_in == 1'b1) begin + @(negedge RESET_in); + end + repeat (2) @(posedge DCLK_in); + init_rst = 0; + alm_rst = 1; + repeat (2) @(posedge DCLK_in); + alm_rst = 0; + end + + assign int_rst_combined = init_rst | soft_rst | seq_rst; //all internally generated + assign #10 int_rst_combined_d = int_rst_combined; + assign sysmon_rst = int_rst_sync2 | RESET_in | gsr_in; //combined reset + + initial begin + int_rst_sync1 = 0; + int_rst_sync2 = 0; + end + + //synchronize internally generated reset to adcclk + always@(posedge adcclk or posedge int_rst_combined_d) begin + if (int_rst_combined_d) begin + int_rst_sync1 <= 1; + int_rst_sync2 <= 1; + end + else begin + int_rst_sync1 <= int_rst_combined_d; + int_rst_sync2 <= int_rst_sync1; + end + end + + always @(posedge sysmon_rst or posedge DCLK_in) begin + if(sysmon_rst ) + initialize <= 3'b001; + else + initialize <= {initialize[1:0],1'b0}; + end + + + + initial begin + sysclk = 0; + adcclk_tmp = 0; + adcclk_count = -1; + //for (i = 0; i <=63; i = i +1) begin + // conv_acc[i] = 0; + //end + DADDR_in_lat = 0; + //data registers reset + for (k = 0; k <= 31; k = k + 1) begin + data_reg[k] = 16'h0000; + end + //min and max registers' reset value assignments + data_reg[32] = 16'h0000; + data_reg[33] = 16'h0000; + data_reg[34] = 16'h0000; + data_reg[35] = 16'h0000; + data_reg[36] = 16'hFFFF; + data_reg[37] = 16'hFFFF; + data_reg[38] = 16'hFFFF; + data_reg[39] = 16'hFFFF; + data_reg[40] = 16'h0000; + data_reg[41] = 16'h0000; + data_reg[42] = 16'h0000; + data_reg[43] = 16'h0000; //reserved + data_reg[44] = 16'hFFFF; + data_reg[45] = 16'hFFFF; + data_reg[46] = 16'hFFFF; + data_reg[47] = 16'h0000; //reserved + + ot_out_reg = 0; + OT_out = 0; + alm_out_reg = 0; + ALM_out = 0; + hr_tot_chan = 0; + lr_tot_chan = 0; + ot_en = 1; + alm_en = 13'h1FFF; + DO_out_rdtmp = 0; + conv_result_int = 0; + conv_result = 0; + conv_result_reg = 0; + READ_ONLY = 0; + reserved_addr_pre = 0; + lr_calib_on = 0; + end //end of initial + + //---------------------------------------------------------------- + // ADC state machine + // to manage timing of output ports CHANNEL, BUSY, EOC, EOS, ALM + //---------------------------------------------------------------- + always @(*) begin + if(sysmon_rst || (|initialize)) + adc_next_state<= ST_A_FIRST_CALIB; + else begin + case (adc_state) + ST_A_FIRST_CALIB : if(cont_sampl_mode && cal_end && !single_pass_finished) + adc_next_state <= ST_A_CHAN; + else if(event_driven_mode && cal_end) + adc_next_state <= ST_A_WAIT_ED; + ST_A_CALIB : if(cont_sampl_mode && cal_end && !single_pass_mode) + adc_next_state <= ST_A_CHAN; + else if(event_driven_mode && cal_end) begin + if(convst_pre_adcclk_pe) + adc_next_state <= ST_A_CHAN; + else + adc_next_state <= ST_A_WAIT_ED; + end + ST_A_WAIT_ED : if(convst_pre_adcclk_pe) + adc_next_state <= ST_A_WAIT; + ST_A_WAIT : if(cont_sampl_mode && single_pass_mode && hr_final_conversion && acq_ext_cur) begin + if(BUSY_out) + adc_next_state <= ST_A_FIRST_CALIB; + else + adc_next_state <= ST_A_WAIT; + end + else if(conversion_before_calib && !single_chan_mode && chan_asrt_dclk ) + adc_next_state <= ST_A_CALIB; + else if(chan_asrt_dclk) + adc_next_state <= ST_A_CHAN; + ST_A_CHAN : if(convst_pre_adcclk_pe ) + adc_next_state <= ST_A_WAIT; + else if (alm_asrt) + adc_next_state <= ST_A_ALM; + ST_A_ALM : if(convst_pre_adcclk_pe ) + adc_next_state <= ST_A_WAIT; + else if(eoc_asrt) + adc_next_state <= ST_A_EOC; + ST_A_EOC : if(convst_pre_adcclk_pe ) + adc_next_state <= ST_A_WAIT; + else if(cont_sampl_mode && single_pass_mode && hr_final_conversion && !acq_ext_cur) + adc_next_state <= ST_A_FIRST_CALIB; + else if (event_driven_mode) + adc_next_state <= ST_A_WAIT_ED; + else + adc_next_state <= ST_A_WAIT; + default : adc_next_state <= ST_A_FIRST_CALIB; + endcase + end + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + adc_state <= ST_A_FIRST_CALIB; + else + adc_state <= adc_next_state; + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + adc_state_d_dclk <= ST_A_FIRST_CALIB; + else + adc_state_d_dclk <= adc_state; + end + + always @(posedge adcclk or posedge sysmon_rst) begin + if(sysmon_rst) + adc_state_d = ST_A_FIRST_CALIB; + else begin + #1; + adc_state_d = adc_state; + end + end + + // signal to stay high until the end of the first ST_A_CHAN + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + st_first_calib_chan <=1; + else begin + if(adc_state==ST_A_CHAN && adc_next_state!=ST_A_CHAN) + st_first_calib_chan <=0; + end + end + + assign chan_asrt_1 = chan_asrt_pe; + assign #1 chan_asrt_2 = chan_asrt_1; + assign #1 chan_asrt_3 = chan_asrt_2; + assign alm_asrt = (out_counter == alm_distance) && !(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB); + assign eoc_asrt = (out_counter == eoc_distance) && !(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB); + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + chan_asrt_4 <= 0; + chan_asrt_5 <= 0; + chan_asrt_6 <= 0; + end + else begin + chan_asrt_4 <= chan_asrt_3; + chan_asrt_5 <= chan_asrt_4; + chan_asrt_6 <= busy_end_pe; + end + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + out_counter <= 0; + else begin + if(chan_asrt_dclk || + (cal_end && (adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB)) || + out_counter == eoc_distance) + out_counter <= 0; + else if(out_counter_inc)// && adc_state!=ST_A_CALIB) + out_counter <= out_counter + 1; + end + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + out_counter_inc <=0; + else begin + if (chan_asrt_dclk) + out_counter_inc <=1; + else if(out_counter == eoc_distance-1) + out_counter_inc <=0; + end + end + + //acquisition extension + assign acq_ext = cfg_reg0[8]; + + //event driven mode busy generation + assign busy_start_ed = (ed_counter == 1 && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB); + assign busy_end_ed = (ed_counter == 22 || (busy_end_ed_wait && ~convst_saved)); //&&first calib or calib might be better. + assign busy_end_ed_out = (busy_end_ed && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB); + assign chan_asrt_ed = (ed_counter == 21); + assign conv_track_ed = ((ed_counter == 0||ed_counter==22) && CHANNEL_out!=8 ); + assign busy_end_ed_wait = (adc_state == ST_A_WAIT_ED && adc_state_d_dclk != ST_A_WAIT_ED); + + always @(posedge adcclk or posedge sysmon_rst or posedge convst_pre_dclk_pe) begin + if(sysmon_rst || convst_pre_dclk_pe) + ed_counter <= 0; + else begin + if(!ed_counter_inc || adc_state_d==ST_A_FIRST_CALIB || adc_state_d==ST_A_CALIB || adc_state==ST_A_WAIT_ED ) + ed_counter <= 0; + else if(ed_counter_inc) + ed_counter <= ed_counter + 1; + end + end + + + always @(posedge sysmon_rst or posedge DCLK_in) begin + if(sysmon_rst) + ed_counter_inc <=0; + else begin + if(convst_pre_adcclk_pe && !(adc_state_d==ST_A_FIRST_CALIB || adc_state_d==ST_A_CALIB)) + ed_counter_inc <=1; + else if(ed_counter==22) + ed_counter_inc <=0; + end + end + + //continuous sampling mode busy generation + assign busy_start_point= (acq_ext_cur_d) ? 5'd10 : 5'd4; + assign cs_count_tot = (acq_ext_cur_d) ? 5'd31 : 5'd25; + assign busy_start_cs = (cs_counter == busy_start_point && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB) || + (cal_counter==4 && adc_state==ST_A_CALIB) ; + assign busy_end_cs = (cs_counter == 0 && adc_state!=ST_A_FIRST_CALIB ); + assign busy_end_cs_out = (cs_counter == 0 && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB); + assign chan_asrt_cs = (cs_counter == cs_count_tot); + assign conv_track_cs = (cs_counter == 0 && adc_state==ST_A_CHAN); + + + always @(posedge adcclk or posedge sysmon_rst) begin + if(sysmon_rst) begin + cs_counter <= 0; + acq_ext_cur_d <=0; + end + else begin + if(cs_counter==cs_count_tot || adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB) begin + cs_counter <= 0; + acq_ext_cur_d <= acq_ext_cur; + end + else if(cs_counter < cs_count_tot) + cs_counter <= cs_counter + 1; + end + end + + assign busy_start = initialize[2] || (event_driven_mode && busy_start_ed) || (~event_driven_mode && busy_start_cs_d); + assign busy_end = (event_driven_mode && busy_end_ed) || (~event_driven_mode && busy_end_cs); + assign busy_end_out = (event_driven_mode && busy_end_ed_out)|| (~event_driven_mode && busy_end_cs_out); + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + BUSY_out <= 0; + else begin + if(busy_start) + BUSY_out <= 1; + else if (busy_end_out) + BUSY_out <= 0; + end + end + + assign chan_asrt = (event_driven_mode && chan_asrt_ed) || (~event_driven_mode && chan_asrt_cs); + assign chan_asrt_pe = chan_asrt & ~chan_asrt_d; + assign chan_asrt_dclk = (curr_clkdiv_sel>2) ? (chan_asrt & adcclk_period_end_d) : (chan_asrt & chan_asrt_d) ; + assign busy_end_pe = busy_end & ~busy_end_d; + assign conv_track = event_driven_mode ? conv_track_ed : conv_track_cs; + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + chan_asrt_d <= 0; + busy_start_cs_d <= 0; + busy_end_d <= 0; + busy_end_out_d <= 0; + end + else begin + chan_asrt_d <= chan_asrt; + busy_start_cs_d <= busy_start_cs; + busy_end_d <= busy_end; + busy_end_out_d <= busy_end_out; + end + end + + + // BUSY should assert 1 dclk cycle after next adcclk posedge after convst_in_pre + assign convst_pre_adcclk_pe = convst_in_pre & ~convst_adcclk_d2; + assign convst_pre_dclk_pe = convst_in_pre & ~convst_dclk_d1; + + always @(posedge adcclk or posedge sysmon_rst) begin + if(sysmon_rst) begin + convst_adcclk_d1 <= 0; + convst_adcclk_d2 <= 0; + end + else begin + convst_adcclk_d1 <= convst_in_pre ; + convst_adcclk_d2 <= convst_adcclk_d1 ; + end + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + convst_dclk_d1 <= 0; + else + convst_dclk_d1 <= convst_in_pre; + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + convst_saved <= 0; + end + else begin + if(convst_pre_adcclk_pe && (adc_state==ST_A_CHAN || adc_state==ST_A_ALM)) + convst_saved <= 1; + else if (adc_state==ST_A_WAIT || busy_end) + convst_saved <= 0; + end + end + + + // Calibration timing + // calibration period in effect is cal_factor * conversion period + assign cal_factor = single_chan_mode? 1: 3; // short calibration for single channel mode to mimick coming out of reset + assign cal_factor2 = 3; + assign conv_period = event_driven_mode ? 22 : (26+(acq_ext_cur_d ? 6 : 0)) ; + assign first_cal_limit = (cal_factor -1)*conv_period +1; + assign later_cal_limit = (cal_factor2-1)*conv_period +2; + assign cal_limit = (adc_state==ST_A_FIRST_CALIB) ? first_cal_limit : later_cal_limit; + + assign cal_end_level = (cal_counter==cal_limit-1) && BUSY_out; + //assign cal_end_pre = (cal_counter==cal_limit-2); + assign cal_end = cal_end_level && ~cal_end_level_d; + + always @(posedge adcclk or posedge sysmon_rst) begin + if(sysmon_rst) + cal_counter <= 0; + else begin + if((conversion_before_calib && busy_end && adc_state!=ST_A_CALIB ) || adc_state==ST_A_WAIT_ED || adc_state==ST_A_WAIT) + cal_counter <= 0; + else if((adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB) && cal_counter <= cal_limit-1 && BUSY_out) + cal_counter <= cal_counter + 1; + end + end + + always @(posedge adcclk or posedge sysmon_rst) begin + if(sysmon_rst) + cal_end_level_d <= 0; + else + cal_end_level_d <= cal_end_level; + end + + //----------------------------------------------------------------------- + // DRPORT - SRAM + //----------------------------------------------------------------------- + initial begin + DRDY_out = 0; + DRDY_out_pre1 = 0; + DRDY_out_pre2 = 0; + DRDY_out_pre3 = 0; + en_data_flag = 0; + DO_out = 16'b0; + end + +// always @(posedge DRDY_out_pre3 or posedge gsr_in) begin + always @(DRDY_out_pre3 or posedge gsr_in) begin + if (gsr_in == 1) + DRDY_out <= 0; +// DRDY_out <= DRDY_out_pre3; // temp + else begin +// else if (DRDY_out_pre3) begin // temp + @(posedge DCLK_in) + DRDY_out <= 1; + @(posedge DCLK_in) + DRDY_out <= 0; + end + end + + function is_reserved_address; + input [7:0] address_in; + reg is_reserved_address_pre; + begin + + is_reserved_address_pre = ( address_in == 8'h07 || + (address_in >= 8'h0B && address_in <= 8'h0C) || + address_in == 8'h2B || + (address_in >= 8'h2F && address_in <= 8'h37) || + (address_in >= 8'h39 && address_in <= 8'h3D) || + address_in == 8'h45 || + (address_in >= 8'h64 && address_in <= 8'h67) || + (address_in >= 8'h6C && address_in <= 8'h79) || + (address_in >= 8'h7D && address_in <= 8'h7F) || + (address_in >= 8'h84 && address_in <= 8'h9F) || + (address_in >= 8'hA4 && address_in <= 8'hA7) || + (address_in >= 8'hAC && address_in <= 8'hFF) + ); + if(is_reserved_address_pre) + $display("Warning: [Unisim %s-11] The input address=h%x at time %.3f ns is accessing a RESERVED location. The data in this location is invalid. Instance: %m", MODULE_NAME, address_in, $time/1000.0); + is_reserved_address = is_reserved_address_pre; + end + endfunction + + function is_readonly_address; + input [7:0] address_in; + reg is_readonly_address_pre; + begin + + is_readonly_address_pre = ((address_in <= 8'h02) || // poke hole at 03 CR 993584 + (address_in >= 8'h04 && address_in <= 8'h3F) || + (address_in >= 8'h80 && address_in <= 8'hAB) + ); + if(is_readonly_address_pre) + $display("Warning: [Unisim %s-19] The input address=h%x at time %.3f ns is accessing a READ ONLY location. The data won't be written. Instance: %m", MODULE_NAME, address_in, $time/1000.0); + is_readonly_address = is_readonly_address_pre; + end + endfunction + + always @(posedge DCLK_in or posedge gsr_in) begin + if (gsr_in == 1) begin + DADDR_in_lat <= 8'b0; + DO_out <= 16'b0; + read_only_pre <= 0; + READ_ONLY <= 0; + RESERVED_ADDR <= 0; +// DRDY_out_pre1 <= DEN_in; // temp +// DRDY_out_pre2 <= DRDY_out_pre1; // temp +// DRDY_out_pre3 <= DRDY_out_pre2; // temp + end + else begin + if (DEN_in == 1'b1) begin + read_only_pre <= 0; + if (DRDY_out_pre1 == 1'b0) begin + DRDY_out_pre1 <= 1'b1; + en_data_flag = 1; + DADDR_in_lat <= DADDR_in; + end + else + $display("Warning: [Unisim %s-10] Input pin DEN can be high for 1 DCLK cycle only. Please wait for DRDY to be high for setting DEN to high again. Instance: %m, time: %.3f ns", MODULE_NAME, $time/1000.0); + end // if (DEN_in == 1'b1) + else + DRDY_out_pre1 <= 1'b0; + + DRDY_out_pre2 <= DRDY_out_pre1; + DRDY_out_pre3 <= DRDY_out_pre2; + + if (DRDY_out_pre1 == 1) + en_data_flag = 0; + + if (DRDY_out_pre3 == 1) begin + RESERVED_ADDR <= reserved_addr_pre; + READ_ONLY <= read_only_pre; + if(DWE_in==0) begin + DO_out <= DO_out_rdtmp; + end + end + + if (DEN_in == 1 && is_reserved_address(DADDR_in) ) + reserved_addr_pre <= 1; + else if (DWE_in == 1'b1 && DEN_in == 1'b1 && en_data_flag == 1) begin + //write to all available and writable addresses. + //check write access + if (is_readonly_address(DADDR_in)) + read_only_pre <= 1; + else begin + read_only_pre <= 0; + if (DADDR_in != 8'h03) begin // no dr_sram at addr 3 + dr_sram[DADDR_in] <= DI_in; + end + end // not read only + end // dwe ==1 + + // CR-764936 in event driven mode, when doing one pass when a CONVST BUSY should assert and then an EOC be seen, + // the user can assert a CONVST again without having to write to the sequence register to start the sequence again. + // if continuous sampling, after one pass, the sequencer goes to single channel mode. + if(single_pass_finished_pe && !event_driven_mode) begin + dr_sram[8'h41][15:12] <= SEQ_SINGLE_CHAN ;//4'b0011; //from single pass, go to single channel + end + + end // if (gsr == 1) + end //always + + reg post_process; + reg [7:0] cfg_check_addr; + reg [15:0] cfg_in; + + //post processing generalized. + always @(posedge DCLK_in or posedge gsr_in) begin + if(gsr_in) begin + post_process <= 0; + cfg_check_addr <= 0; + cfg_in <= 0; + end + else begin + if(initialize[2]) begin + post_process <= 0; + cfg_check_addr <= 0; + cfg_in <= 0; + end + else if(DEN_in && DWE_in) begin + post_process <= 1; + cfg_check_addr <= DADDR_in; + cfg_in <= DI_in; + end + else if(i2c_wr_exec) begin + post_process <= 1; + cfg_check_addr <= i2c_drp_addr[7:0]; + cfg_in <= i2c_drp_data; + end + else if(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG) begin + post_process <= 1; + cfg_check_addr <= pmb_sel_addr; + cfg_in <= pmb_data_in; + end + else begin + post_process <= 0; + cfg_check_addr <= 0; + cfg_in <= 0; + end + end + end //always + + //post processing generalized. + always @(posedge DCLK_in or posedge gsr_in) begin + if (gsr_in == 1) begin + soft_rst <= 0; + end + else begin + if(post_process) begin + if (cfg_check_addr == 8'h03) + soft_rst <= 1; + else if ( cfg_check_addr == 8'h53 && cfg_in[3:0] == 4'b0011) + ot_limit_reg <= cfg_in;// overwrite the OT upper limit + end + + if (soft_rst == 1) + soft_rst <= 0; + end + end//always + + always @(posedge post_process) begin + if(cfg_check_addr == 8'h40) + if (cfg_reg0[5:0] == 6'd7 || (cfg_reg0[5:0] >= 6'd9 && cfg_reg0[5:0] <= 6'd12) || cfg_reg0[5:0] >= 6'd36) + $display("Warning: [Unisim %s-14] Config register 0 bits [5:0] at 40h cannot not be set to an invalid analog channel value as %0b. Instance: %m", MODULE_NAME, cfg_reg0[5:0], $time/1000.0,); + if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41) + if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[8]==1) && (cfg_reg0[5:0] != 6'd3) && !(cfg_reg0[5:0] >= 6'd16 && cfg_reg0 <= 31)) + $display("Warning: [Unisim %s-15] In single channel mode if the selected channel is not analog, config register 0 bit[8] must be set to 0. Long acqusition mode is only allowed for external channels, not in single channel mode. Instance: %m", MODULE_NAME, DI_in, DADDR_in, $time/1000.0); + if(cfg_check_addr==8'h41|| cfg_check_addr==8'h46|| cfg_check_addr==8'h48|| cfg_check_addr==8'h49) + if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (seq_hr_chan_reg1 != 16'h0000) && (seq_hr_chan_reg2 != 16'h0000) && (seq_hr_chan_reg3 != 16'h0000)) + $display("Info: [Unisim %s-16] In single channel mode, ADC channel selection registers 46h, 48h and 49h will be ignored; these are set to %x, %x and %x respectively. Instance: %m", MODULE_NAME, seq_hr_chan_reg3, seq_hr_chan_reg1, seq_hr_chan_reg2, $time/1000.0); + if(cfg_check_addr==8'h41|| cfg_check_addr==8'h7A|| cfg_check_addr==8'h7B|| cfg_check_addr==8'h7C) + if ((cfg_reg1[15:12]!=SEQ_CONT_CHAN) && (seq_lr_chan_reg1 != 16'h0000) && (seq_lr_chan_reg2 != 16'h0000) && (seq_lr_chan_reg3 != 16'h0000)) + $display("Info: [Unisim %s-13] In modes other than continuous sequence mode, ADC slow rate channel selection registers 7Ah, 7Bh and 7Ch will be ignored; these are set to %x, %x and %x respectively. Instance: %m", MODULE_NAME, seq_lr_chan_reg3, seq_lr_chan_reg1, seq_lr_chan_reg2, $time/1000.0); + if(cfg_check_addr == 8'h4E || cfg_check_addr==8'h41) + if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4E][10:0]!=11'd0) || (dr_sram['h4E][15:12]!=4'd0))) + $display("Info: [Unisim %s-18] The Control Register 4Eh value set is to %x. Bits [15:12] and [10:0] of this register will be ignored. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0); + if(cfg_check_addr == 8'h42) + if (cfg_reg2[4:0]!=5'd0) + $display("Warning: [Unisim %s-12] The config reg 2 =h%x is invalid. Bit [4:0] must be set to 5'b00000. Instance: %m", MODULE_NAME, cfg_reg2, $time/1000.0); + if(cfg_check_addr == 8'h40) + if(cfg_reg0[13:12]!=2'b00 && !avg_en ) + $display("Info: [Unisim %s-61] When cfg_reg0[13:12] is set to have averaging on: Single pass mode doesn't allow it. Continuous mode needs to have at least one channel in the high rate or low rate sequence needs to have averaging enabled. Otherwise averaging is disabled. Instance: %m", MODULE_NAME, $time/1000.0); + if(cfg_check_addr == 8'h4C || cfg_check_addr==8'h41) + if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4C][10:0]!=11'd0) || (dr_sram['h4C][15:12]!=4'd0))) + $display("Info: [Unisim %s-17] The Control Register 4Ch value set is to %x. Bits [15:12] and [10:0] of this register will be ignored. Bipolar mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0); + if(cfg_check_addr == 8'h53) + if(cfg_in[3:0]==4'b0011) + $display("Info: [Unisim %s-20] OT upper limit has been overwritten and automatic shutdown bits have been set by input h%0h. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, cfg_in, $time/1000.0,); + else // cfg_in[3:0] != 4'b0011 + $display("Info: [Unisim %s-21] OT upper limit can only be overwritten while enabling automatic shutdown, hence input value h%0h will be ignored and the default value will be kept. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, cfg_in, $time/1000.0,); + if(cfg_check_addr == 8'h4A) + if(cfg_in[13:12]!=2'b00 || cfg_in[0] ) + $display("Info: [Unisim %s-26] Calibration, VREFP, and VREFN channels do not allow averaging. Some or all of the bits 0,12,13 of 4A are set to 1 and they will be ignored. Instance: %m", MODULE_NAME, $time/1000.0); + + end // post_process + + + initial begin + seq_rst = 0; + end + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst==1) + seq_rst <= 1'b0; + else begin + if((single_pass_finished_pe && ~event_driven_mode) || //single pass finished + (DWE_in==1 && DEN_in==1 && DADDR_in==8'h41 && (DI_in[15:12]!=cfg_reg1[15:12]) ) || // switching to a different operating mode + (i2c_wr_exec && i2c_drp_addr==10'h41 && i2c_drp_data[15:12]!=cfg_reg1[15:12]) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h41 && pmb_data_in[15:12]!=cfg_reg1[15:12]) || + (single_chan_mode && DWE_in==1 && DEN_in==1 && DADDR_in==8'h40 && (DI_in[5:0] != cfg_reg0[5:0]) ) || //change the channel selection in single channel mode + (i2c_wr_exec && i2c_drp_addr==10'h40 && i2c_drp_data[5:0]!=cfg_reg0[5:0]) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h40 && pmb_data_in[5:0]!=cfg_reg0[5:0]) || + (pmb_wr_exec && pmb_cmd_in==CMD_PAGE) //page command adds a new channel to the sequence hence the reset + ) + seq_rst <= 1'b1; + else + seq_rst <= 1'b0; + end + end //always + + // If user adds a new channel to the sequences, then it will be + // added after the EOS of the last + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst==1) begin + add_channel_hr_p <= 1'b0; + add_channel_lr_p <= 1'b0; + end + else begin + if((DWE_in==1 && DEN_in==1 && DADDR_in==8'h48 && DI_in!=seq_hr_chan_reg1 ) || + (i2c_wr_exec && i2c_drp_addr==10'h48 && i2c_drp_data!=seq_hr_chan_reg1 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h48 && pmb_data_in!=seq_hr_chan_reg1) || + (DWE_in==1 && DEN_in==1 && DADDR_in==8'h49 && DI_in!=seq_hr_chan_reg2 ) || + (i2c_wr_exec && i2c_drp_addr==10'h49 && i2c_drp_data!=seq_hr_chan_reg2 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h49 && pmb_data_in!=seq_hr_chan_reg2) || + (DWE_in==1 && DEN_in==1 && DADDR_in==8'h46 && DI_in!=seq_hr_chan_reg3 ) || + (i2c_wr_exec && i2c_drp_addr==10'h46 && i2c_drp_data!=seq_hr_chan_reg3 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h46 && pmb_data_in!=seq_hr_chan_reg3) + ) + add_channel_hr_p <= 1; + else if(add_channel) + add_channel_hr_p <= 0; + + + if((DWE_in==1 && DEN_in==1 && DADDR_in==8'h7A && DI_in!=seq_lr_chan_reg1 ) || + (i2c_wr_exec && i2c_drp_addr==10'h7A && i2c_drp_data!=seq_lr_chan_reg1 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7A && pmb_data_in!=seq_lr_chan_reg1) || + (DWE_in==1 && DEN_in==1 && DADDR_in==8'h7B && DI_in!=seq_lr_chan_reg2 ) || + (i2c_wr_exec && i2c_drp_addr==10'h7B && i2c_drp_data!=seq_lr_chan_reg2 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7B && pmb_data_in!=seq_lr_chan_reg2) || + (DWE_in==1 && DEN_in==1 && DADDR_in==8'h7C && DI_in!=seq_lr_chan_reg3 ) || + (i2c_wr_exec && i2c_drp_addr==10'h7C && i2c_drp_data!=seq_lr_chan_reg3 ) || + (pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7C && pmb_data_in!=seq_lr_chan_reg3) + ) + add_channel_lr_p <= 1; + else if(add_channel) + add_channel_lr_p <= 0; + + end + end //always + + + + // DO bus data out + + assign flag_reg0 = {8'b0, ALM_out[6:3], OT_out, ALM_out[2:0]}; + assign flag_reg1 = {10'b0, ALM_out[13:8]}; + + always @(posedge DCLK or posedge gsr_in ) begin + if(gsr_in==1 ) + DO_out_rdtmp <= 0; + else if(DRDY_out_pre2) begin + reserved_addr_pre = is_reserved_address(DADDR_in_lat); + if(reserved_addr_pre) + DO_out_rdtmp <= 0; + else begin //readable addresses + if (DADDR_in_lat <= 8'h3D) + DO_out_rdtmp <= data_reg[DADDR_in_lat]; + else if (DADDR_in_lat == 8'h3E) + DO_out_rdtmp <= flag_reg1; + else if (DADDR_in_lat == 8'h3F) + DO_out_rdtmp <= flag_reg0; + else begin + DO_out_rdtmp <= dr_sram[DADDR_in_lat]; + end + end + end + end + + //----------------------------------------------------------------------- + // END of DRPORT - SRAM + //----------------------------------------------------------------------- + + + //----------------------------------------------------------------------- + // Configuration and settings + //----------------------------------------------------------------------- + assign cfg_reg0 = dr_sram[8'h40]; + assign cfg_reg1 = dr_sram[8'h41]; + assign cfg_reg2 = dr_sram[8'h42]; + assign cfg_reg3 = dr_sram[8'h43]; + assign cfg_reg4 = dr_sram[8'h44]; + assign seq_hr_chan_reg1 = dr_sram[8'h48] & 16'h7FE1; //ignore reserved bits + assign seq_hr_chan_reg2 = dr_sram[8'h49]; + assign seq_hr_chan_reg3 = dr_sram[8'h46] & 16'h000F; //ignore reserved bits + assign seq_lr_chan_reg1 = dr_sram[8'h7A] & 16'h7FE1; //ignore reserved bits + assign seq_lr_chan_reg2 = dr_sram[8'h7B]; + assign seq_lr_chan_reg3 = dr_sram[8'h7C] & 16'h000F; //ignore reserved bits + assign seq_avg_reg1 = dr_sram[8'h4A] & 16'h4FE0; //ignore reserved bits + assign seq_avg_reg2 = dr_sram[8'h4B]; + assign seq_avg_reg3 = dr_sram[8'h47] & 16'h000F; //ignore reserved bits + assign seq_bipolar_reg1 = dr_sram[8'h4C] & 16'h0800; //ignore reserved bits + assign seq_bipolar_reg2 = dr_sram[8'h4D]; + assign seq_acq_ext_reg1 = dr_sram[8'h4E] & 16'h0800; //ignore reserved bits + assign seq_acq_ext_reg2 = dr_sram[8'h4F]; + + assign seq_hr_chan_reg_comb = {seq_hr_chan_reg3, seq_hr_chan_reg2, seq_hr_chan_reg1}; + assign seq_lr_chan_reg_comb = {seq_lr_chan_reg3, seq_lr_chan_reg2, seq_lr_chan_reg1}; + assign seq_acq_ext_reg_comb = {16'h0000,seq_acq_ext_reg2,seq_acq_ext_reg1}; + assign seq_bipolar_reg_comb = {16'h0000,seq_bipolar_reg2,seq_bipolar_reg1}; + // + + assign op_mode = cfg_reg1[15:12]; + assign default_mode = (op_mode == 4'b0000 || op_mode[3:2] == 2'b11); + assign single_pass_mode = (op_mode == 4'b0001); + assign cont_seq_mode = (op_mode == 4'b0010); + assign single_chan_mode = (op_mode == 4'b0011); + assign single_chan_id = cfg_reg0[5:0]; + assign ext_mux_chan_id = cfg_reg0[5:0]; + assign ext_mux_en = cfg_reg0[11] && (~default_mode || single_chan_mode); + assign ext_mux = cfg_reg0[11]; + assign event_driven_mode = cfg_reg0[9]; + assign cont_sampl_mode = !event_driven_mode; + assign bipolar_mode = cfg_reg0[10]; + assign single_pass_active = single_pass_mode && ~(single_pass_finished && cont_sampl_mode); + + always @(posedge sysmon_rst or posedge DCLK_in) begin //at initialization or sequence restart + if( sysmon_rst) begin + alm_en <= 0; + ot_en <= 0; + end + else if(initialize[2] || single_pass_finished_pe || chan_asrt_5) begin + if (default_mode) begin + alm_en <= 0; + ot_en <= 1; + end + else begin + ot_en <= ~cfg_reg1[0]; + alm_en[2:0] <= ~cfg_reg1[3:1]; + alm_en[6:3] <= ~cfg_reg1[11:8]; + alm_en[11:8] <= ~cfg_reg3[3:0]; + end + end + end + + //6V range support for VUSER0-3 + //0: 0-3V, 1: 0-6V + assign bank_sel_6V[3:0] = cfg_reg4[3:0]; // CR 949547 + + assign single_pass_finished_pe = single_pass_finished & ~single_pass_finished_d; + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + single_pass_finished <= 0; + single_pass_finished_d <= 0; + end + else begin + if(|initialize )begin + single_pass_finished <= 0; + single_pass_finished_d <= 0; + end + else begin + if(single_pass_mode && + ((!acq_ext_cur && EOS_out)|| + (acq_ext_cur && hr_final_conversion && adc_state==ST_A_WAIT && busy_start_cs)) ) + single_pass_finished <= 1; + single_pass_finished_d <= single_pass_finished; + end + end + end + + //------------------------------------------------------------------------- + //---- I2C logic start -------------------------------------------------- + //---- PMBus logic start -------------------------------------------------- + //------------------------------------------------------------------------- + + parameter ST_I2C_IDLE = 2'd0, + ST_I2C_GET_ADDR = 2'd1, + ST_I2C_GET_CMD = 2'd2, + ST_I2C_READ = 2'd3; + + localparam I2C_DRP_RD = 4'b0001; // read + localparam I2C_DRP_WR = 4'b0010; // write + localparam I2C_DRP_NO = 4'b0000; // no operation + + parameter ST_PMB_IDLE = 3'd0, + ST_PMB_GET_ADDR = 3'd1, + ST_PMB_GET_CMD = 3'd2, + ST_PMB_WRITE = 3'd3, + ST_PMB_READ = 3'd4; + + + localparam PMB_ALERT_RESPONSE_ADDR = 7'b0001100; + + + reg [1:0] i2c_state; + reg i2c_start; + reg i2c_start_reset; + reg i2c_stop; + reg i2c_stop_reset; + reg [3:0] i2c_bit_counter; + reg [2:0] i2c_byte_counter; + wire i2c_lsb_bit; + wire i2c_ack_bit; + wire [3:0] i2c_drp_cmd ; + reg [31:0] i2c_cmd_in; + reg [7:0] i2c_data_in; + wire i2c_addr_match; + wire i2c_addr_match_wop; + wire i2c_rw_bit; + wire i2c_rd_cmd_pre; + reg i2c_rd_cmd; + reg i2c_ack_in; //ack from master to slave, negated. + wire i2c_cmd_end; + wire i2c_rd_end; + reg i2c_cmd_received; + reg [15:0] i2c_data_out; + + reg [2:0] pmb_state; + reg [2:0] pmb_tot_bytes; + wire pmb_data_end; + wire [7:0] pmb_cmd_pre; + reg [31:0] pmb_data_out; + reg pmb_wr_exec_2; + reg pmb_wr_exec_d; + wire pmb_wr_exec_pe; + reg [7:0] pmb_curr_chan_id; + reg pmb_read_only_cmd; + reg [7:0] pmb_status_vout; + reg [7:0] pmb_status_temperature; + reg [7:0] pmb_status_cml; + reg [7:0] pmb_clr_status_vout; + reg [7:0] pmb_clr_status_temperature; + reg [7:0] pmb_clr_status_cml; + reg [7:0] pmb_status_word; //upper byte + reg [7:0] pmb_status_byte; //lower byte + reg pmb_unsp_cmd; + reg pmb_unsp_data; + reg pmb_paged; + reg pmb_selected; + reg [7:0] pmb_page_index; + reg [7:0] pmb_page_stat; + reg [7:0] pmb_page_max; //max stored value address + reg [7:0] pmb_page_min; //min stored value address + reg [7:0] pmb_page_up_l; //upper limit register address + reg [7:0] pmb_page_lo_l; //lower limit register address + reg [3:0] pmb_page_alm_id; //alarm index for over/under voltage + reg pmb_page_6V; + wire pmb_ara_rcvd; + reg pmb_ara; //alert response address + reg clear_faults; + wire pmb_clear; + + + //i2c or pmbus selection changes on the fly with i2c command address selection + //i2c_addr_match_wop -> i2c address match without protocol match + assign i2c_addr_match_wop = ((i2c_data_in[7:4]==i2c_device_addr[6:3]) && (i2c_data_in[2:1]==i2c_device_addr[1:0])) ? 1 : 0; + assign i2c_addr_match = ((i2c_oride && (i2c_data_in[7:1]==i2c_device_addr[6:0])) || + (~i2c_oride && i2c_addr_match_wop )) + ? 1 : 0; + assign pmb_en_bit = i2c_data_in[3] && i2c_ack_bit && (i2c_state==ST_I2C_GET_ADDR || pmb_state==ST_PMB_GET_ADDR); //0:i2c, 1:pmbus + + assign pmb_ara_rcvd = ((i2c_data_in[6:0]==PMB_ALERT_RESPONSE_ADDR || i2c_data_in[7:1]==PMB_ALERT_RESPONSE_ADDR ) && + (i2c_lsb_bit ||i2c_ack_bit)); + + assign pmb_clear = pmb_ara || clear_faults; + + always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_stop) begin + if (RESET_in || i2c_stop ) + pmb_ara <= 0; //this should be a pulse. + else begin + if (pmb_state==ST_PMB_IDLE) + pmb_ara <= 0; //this should be a pulse. + else + pmb_ara <= pmb_ara_rcvd && (pmb_state==ST_PMB_GET_ADDR) && i2c_rd_cmd_pre; + end + end + + assign pmb_en = !i2c_en; + always @(posedge RESET_in or negedge I2C_SCLK_in) begin + if (RESET_in) begin + i2c_en <=1; + end + else begin + if(i2c_oride) + i2c_en <= ~cfg_reg3[10]; + else if(i2c_ack_bit && (i2c_state==ST_I2C_GET_ADDR || pmb_state==ST_PMB_GET_ADDR) && i2c_addr_match_wop) + i2c_en <= ~i2c_data_in[3]; + end + end + + always @(posedge RESET_in or posedge i2c_start_reset or negedge I2C_SDA_in) begin + if(RESET_in || i2c_start_reset) + i2c_start <= 1'b0; + else + i2c_start <= I2C_SCLK_in; + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_start_reset <= 1'b0; + else + i2c_start_reset <= i2c_start; + end + + always @(posedge RESET_in or posedge i2c_stop_reset or posedge I2C_SDA_in) begin + if(RESET_in || i2c_stop_reset) + i2c_stop <= 1'b0; + else + i2c_stop <= I2C_SCLK_in; + end + + always @(posedge RESET_in or posedge i2c_stop) begin + if(RESET_in) + i2c_stop_reset = 1'b0; + else begin + repeat (16) @(posedge DCLK_in); + i2c_stop_reset = 1; + repeat (16) @(posedge DCLK_in); + i2c_stop_reset = 0; + end + end + + assign i2c_lsb_bit = (i2c_bit_counter== 4'd7) && ~i2c_start; + assign i2c_ack_bit = (i2c_bit_counter== 4'd8) && ~i2c_start; + + always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_start) begin + if(RESET_in || i2c_start) + i2c_bit_counter <= 'd0; + else begin + if (i2c_ack_bit) + i2c_bit_counter <= 'd0; + else + i2c_bit_counter <= i2c_bit_counter + 'd1; + end + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_data_in <= 'd0; + else if(!i2c_ack_bit) + i2c_data_in <= {i2c_data_in[6:0],I2C_SDA_in} ; + end + + assign i2c_drp_data = i2c_cmd_in[15:0]; + assign i2c_drp_addr = i2c_cmd_in[25:16]; + assign i2c_drp_cmd = i2c_cmd_in[29:26]; + + + always @(posedge I2C_SCLK_in) begin + //if(RESET_in) + // i2c_cmd_in <= 'd0; + //else if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD ) + if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD ) + i2c_cmd_in <= {i2c_data_in,i2c_cmd_in[31:8]} ; + end + + assign pmb_cmd_pre = i2c_data_in[7:0]; + + always @(posedge I2C_SCLK_in) begin + //if(RESET_in) + // pmb_cmd_in <= 'd0; + //else if (i2c_ack_bit && pmb_state == ST_PMB_GET_CMD) + if (i2c_ack_bit && pmb_state == ST_PMB_GET_CMD) + pmb_cmd_in <= i2c_data_in; + end + + assign i2c_rw_bit = i2c_lsb_bit && (i2c_state == ST_I2C_GET_ADDR || pmb_state ==ST_PMB_GET_ADDR); + assign i2c_rd_cmd_pre = i2c_rw_bit && I2C_SDA_in; + + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop) + i2c_rd_cmd <= 1'b0; + else begin + if (i2c_state==ST_I2C_IDLE && pmb_state==ST_PMB_IDLE) + i2c_rd_cmd <= 1'b0; + else if (i2c_rw_bit ) + i2c_rd_cmd <= i2c_data_in[0] ; + end + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if(RESET_in) + i2c_ack_in <= 'd0; + else if(i2c_ack_bit) + i2c_ack_in <= ~I2C_SDA_in; //ACK from master to slave, negated. + else if ((i2c_state==ST_I2C_IDLE && pmb_state==ST_PMB_IDLE) || i2c_bit_counter=='d1) + i2c_ack_in <= 0; + end + + assign i2c_cmd_end = i2c_ack_bit && (i2c_byte_counter==3'd3); + assign i2c_rd_end = i2c_ack_bit && (i2c_byte_counter==3'd1); + + always @(posedge RESET_in or posedge i2c_stop or posedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop) + i2c_cmd_received <= 0; + else if (i2c_cmd_end) + i2c_cmd_received <= 1; + else if (i2c_state==ST_I2C_READ) + i2c_cmd_received <= 0; + end + + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_start || i2c_stop) + i2c_byte_counter <= 0; + else if(i2c_ack_bit && (i2c_state == ST_I2C_GET_CMD || i2c_state == ST_I2C_READ || + pmb_state == ST_PMB_WRITE || pmb_state == ST_PMB_READ )) + i2c_byte_counter <= i2c_byte_counter + 1; + end + + //I2C state machine. + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop)// && ~i2c_en) + i2c_state <= ST_I2C_IDLE; + else if(i2c_start) + i2c_state <= ST_I2C_GET_ADDR; + else if (i2c_ack_bit) + case (i2c_state) + ST_I2C_GET_ADDR : begin + if(!(i2c_addr_match && !pmb_en_bit)) begin + i2c_state <= ST_I2C_IDLE; + $display("Info: [Unisim %s-54] I2C command address h%0X not matching the device address h%0X @time %0t", + MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time); + end + else if (~i2c_cmd_received) + i2c_state <= ST_I2C_GET_CMD; + else if(i2c_drp_cmd==I2C_DRP_RD) //if you received a command earlier, it had to be a drp read command. + i2c_state <= ST_I2C_READ; + else + i2c_state <= ST_I2C_IDLE; + end + ST_I2C_GET_CMD : begin + if (i2c_cmd_end) begin + i2c_state <= ST_I2C_IDLE; + $display("Info: [Unisim %s] I2C command received @time %0t", MODULE_NAME, $time); + end + end + ST_I2C_READ : begin + if(i2c_rd_end) + i2c_state <= ST_I2C_IDLE; + end + default : i2c_state <= ST_I2C_IDLE; + endcase + end + + //i2c write command execute + assign i2c_wr_exec = (i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR); + + always @(posedge DCLK_in ) begin + if(!sysmon_rst) begin + if(i2c_wr_exec && + !(is_readonly_address(i2c_drp_addr)) && !is_reserved_address(i2c_drp_addr) ) + dr_sram[i2c_drp_addr] <= i2c_drp_data; + end + end + + //i2c read command execute + always @(negedge I2C_SCLK_in) begin + if(!RESET_in) begin + if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_RD && i2c_state==ST_I2C_GET_ADDR && !i2c_ack_bit) begin //fetch the data + if(i2c_drp_addr>='h40) + i2c_data_out <= dr_sram[i2c_drp_addr]; + else + i2c_data_out <= data_reg[i2c_drp_addr]; + end + else if(i2c_lsb_bit && i2c_state==ST_I2C_READ) + i2c_data_out <= {8'b0,i2c_data_out[15:8]};// shift the higher byte to lower. + else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out. + i2c_data_out <= {i2c_data_out[15:8],i2c_data_out[6:0],1'b0}; + end + end + + assign pmb_data_end = i2c_ack_bit && (i2c_byte_counter==(pmb_tot_bytes-1)); + + //Pull down SDA to transfer a zero to the master. + always@(posedge RESET_in or negedge I2C_SCLK_in) begin + if (RESET_in) + I2C_SDA_TS_out <= 1; + else begin + if (i2c_start) + I2C_SDA_TS_out <= 1; + else if (i2c_lsb_bit) //acknowledge the end of a 1 byte transfer from master + I2C_SDA_TS_out <= ! (((i2c_state==ST_I2C_GET_ADDR) && (i2c_addr_match || pmb_ara_rcvd)) || //will also be true for pmbus + ((i2c_state==ST_I2C_GET_CMD ) && !(i2c_rd_cmd && i2c_byte_counter=='d3)) || //send NACK at the last byte of command, only if read command + (pmb_state==ST_PMB_GET_CMD) || + (pmb_state==ST_PMB_WRITE) //send ACK for all write command bytes + ); + else if ((i2c_ack_bit && //first bit of next slave to master transfer + ((i2c_state==ST_I2C_GET_ADDR) && (i2c_drp_cmd==I2C_DRP_RD) )) || + (i2c_state==ST_I2C_READ && !i2c_rd_end)) //or read continued + I2C_SDA_TS_out <= i2c_data_out[7]; + else if(((i2c_ack_bit && pmb_state==ST_PMB_GET_ADDR) && i2c_rd_cmd) || //first bit of next slave to master transfer + (pmb_state==ST_PMB_READ && !pmb_data_end)) //or read continued + I2C_SDA_TS_out <= pmb_data_out[7]; + else + I2C_SDA_TS_out <= 1; + end + end + + // clock stretching + assign I2C_SCLK_TS_out = 1'b1; + + //---- End of I2C logic ------------------------------------------------ + //---- PMBUS only from here on ----------------------------------------- + + // PMBUS state machine + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in || i2c_stop) + pmb_state <= ST_PMB_IDLE; + else if(i2c_start) + pmb_state <= ST_PMB_GET_ADDR; + else if (i2c_ack_bit) + case (pmb_state) + ST_PMB_GET_ADDR : begin + if(!(i2c_addr_match && pmb_en_bit)) begin + if(pmb_ara_rcvd) begin + if(!i2c_rd_cmd) begin + pmb_state <= ST_PMB_IDLE; + $display("Info: [Unisim %s-57] PMBus Alert Response Address received together with a write bit instead of a read bit. It will be ignored. @time %0t", + MODULE_NAME, $time); + end + else //ARA received. Send the device address as a response + pmb_state <= ST_PMB_READ; + end + else begin + pmb_state <= ST_PMB_IDLE; + if(pmb_en_bit) + $display("Info: [Unisim %s-64] PMBus command address h%0X not matching the device address h%0X @time %0t", + MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time); + end + end + else if (!i2c_rd_cmd) //write command comes only before command id. + pmb_state <= ST_PMB_GET_CMD; + else + pmb_state <= ST_PMB_READ; + end + ST_PMB_GET_CMD : begin + $display("Info: [Unisim %s] PMBus command received @time %0t", MODULE_NAME, $time); + if(pmb_cmd_pre==CMD_CLEAR_FAULT) //clear fault has 0 bytes of succeeding data, so go to idle. + pmb_state <= ST_PMB_IDLE; + else //get succeeding data. if it is a read command, restart will take it to ST_PMB_IDLE. + pmb_state <= ST_PMB_WRITE; + end + ST_PMB_WRITE : begin + if(pmb_data_end) + pmb_state <= ST_PMB_IDLE; + end + ST_PMB_READ : begin + if(pmb_data_end) + pmb_state <= ST_PMB_IDLE; + end + default : begin + pmb_state <= ST_PMB_IDLE; + end + endcase + end + + + //Parse PMB command + always @(posedge RESET_in or negedge I2C_SCLK_in) begin + if(RESET_in) begin + pmb_tot_bytes <= 'd0; + pmb_unsp_cmd <= 0; + pmb_paged <= 0; + pmb_selected <= 0; + end + else if(i2c_ack_bit && pmb_state==ST_PMB_GET_CMD) begin + pmb_unsp_cmd <= 0; + case (pmb_cmd_pre) + CMD_PAGE : begin + pmb_tot_bytes <= 'd1; + pmb_paged <= 1; + end + CMD_CLEAR_FAULT : begin + pmb_tot_bytes <= 'd0; + end + CMD_CAPABILITY,CMD_VOUT_MODE,CMD_STATUS_BYTE, + CMD_STATUS_VOUT, CMD_STATUS_TEMPERATURE, CMD_STATUS_CML, + CMD_PMBUS_REVISION, CMD_MFR_ENABLE_VUSER_HR + : begin + pmb_tot_bytes <= 'd1; + end + CMD_VOUT_OV_FAULT_LIMIT, CMD_VOUT_UV_FAULT_LIMIT, + CMD_OT_FAULT_LIMIT , CMD_OT_WARNING_LIMIT , + CMD_UT_WARNING_LIMIT , CMD_UT_FAULT_LIMIT , + CMD_STATUS_WORD , CMD_READ_VOUT , + CMD_READ_TEMPERATURE_1 , CMD_MFR_ACCESS_REG , + CMD_MFR_READ_VOUT_MAX , CMD_MFR_READ_VOUT_MIN , + CMD_MFR_READ_TEMP_MAX , CMD_MFR_READ_TEMP_MIN + : begin + pmb_tot_bytes <= 'd2; + end + CMD_MFR_ID,CMD_MFR_MODEL: begin + pmb_tot_bytes <= 'd4; + end + CMD_MFR_REVISION : begin + pmb_tot_bytes <= 'd3; + end + CMD_MFR_SELECT_REG : begin + pmb_tot_bytes <= 'd2; + pmb_selected <= 1; + end + default: begin + pmb_unsp_cmd<=1; //Unsupported command + $display("Warning: [Unisim %s-56] PMBus received invalid command ID h%0X @ time %0t ", MODULE_NAME, pmb_cmd_pre, $time); + end + endcase + + end + else if(pmb_ara_rcvd && pmb_state==ST_PMB_GET_ADDR) //Alert Response Address (ARA) has 1 byte response. + pmb_tot_bytes <= 1; + else begin + pmb_unsp_cmd <= 0; + end + end + + always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin + if(RESET_in ||i2c_stop) + clear_faults <= 0; + else if(i2c_ack_bit && pmb_state==ST_PMB_GET_CMD && pmb_cmd_pre==CMD_CLEAR_FAULT) + clear_faults <= 1; + else + clear_faults <= 0; + end + + always @(posedge RESET_in or posedge I2C_SCLK_in) begin + if (RESET_in) + pmb_data_in <= 'd0; + else if(i2c_ack_bit && pmb_state == ST_PMB_WRITE) + if(pmb_tot_bytes>1) + pmb_data_in <= {i2c_data_in,pmb_data_in[15:8]} ; //Most significant byte arrives later. + else + pmb_data_in <= {8'd0,i2c_data_in} ; //1 byte, that's it. + end + + //convert from linear 16 to drp format -> PMBus WRITE + function [15:0] linear16_to_drp; + input [15:0] mantissa; //unsigned + reg [16:0] linear17_to_drp; + begin + if(pmb_page_6V) // CR 949547 + linear16_to_drp = (mantissa *2)/3; + else begin + linear17_to_drp = (mantissa *4)/3; + if(linear17_to_drp > 17'h0FFFF) begin + linear16_to_drp = 16'hFFFF; + if(pmb_wr_exec_pe) //display message only once. + $display("Warning: [Unisim %s-62] The maximum value you can write to a DRP supply register is 16'hFFFF. Hence for PMBus it is 16'hAAAA. The input value has been saturated to max.", MODULE_NAME, $time); + end + else + linear16_to_drp = linear17_to_drp[15:0]; + end + //$display("linear16_to_drp: mantissa :h%0h, output=h%0h @%0t",mantissa , linear16_to_drp, $time); + end + endfunction + + //convert from drp format to linear 16 -> PMBus READ + function [15:0] drp_to_linear16; + input [15:0] voltage_drp; //unsigned + reg [16:0] drp_to_linear17; + begin + if(pmb_page_6V) begin // CR 949547 + drp_to_linear17 = (voltage_drp *3)/2; + if(drp_to_linear17 > 17'h0FFFF) begin + drp_to_linear16 = 16'hFFFF; + if(i2c_lsb_bit) //display message only once + $display("Warning: [Unisim %s-63] The maximum value you can read from a DRP supply register is 16'hFFFF. Hence for PMBus it is 16'hAAAA. The return value has been saturated to max.", MODULE_NAME, $time); + end + else + drp_to_linear16 = drp_to_linear17[15:0]; + end + else + drp_to_linear16 = (voltage_drp *3)/4; + //$display("drp_to_linear16: voltage_drp=h%0h, output=h%0h, drp_to_linear17=h%0h @%0t",voltage_drp, drp_to_linear16, drp_to_linear17, $time); + end + endfunction + + //convert from linear 11 to integer -> PMBus WRITE + function [15:0] linear11_to_drp; + input [15:0] exp_mants; //both signed + //input limit; // 0 if reading current or min/max value 1: reading temp limits + real exp; + real mants; + real temp_coeff; + real temp_offset; + real two_p_bits; + real real_result; + begin + exp =$signed(exp_mants[15:11]); + mants =$signed(exp_mants[10:0]); + //temp_coeff = limit ? 502.9098 : 491.2065 ; + //temp_offset = limit ? 273.8195 : 273.15 ; + //two_p_bits = limit ? 65536: 65535; + temp_coeff = 503.975 ; + temp_offset = 273.15 ; + two_p_bits = 65536; + real_result = (mants * (2** exp)); //mants * 2^exp + real_result = (real_result + temp_offset) * (two_p_bits / temp_coeff); + //linear11_to_drp = $rtoi(real_result); + linear11_to_drp = real_result; + //$display("linear11_to_drp: exp_mants=h%0h, mantissa=d%0d, exp:d%0d, real_result=g%0g, output=h%0h @%0t\n", + // exp_mants, mants, exp, real_result, linear11_to_drp, $time/1000); + end + endfunction + + // Convert from integer to to linear 11 -> PMBus READ + // Exponent is -1 hard coded during PMBus reads. + function [15:0] drp_to_linear11; + input [15:0] drp_temp; //unsigned. temperature in drp format + //input limit; + real temp_coeff; + real temp_offset; + real two_p_bits; + real real_result; + reg signed [10:0] mantissa; + begin + //temp_coeff = limit ? 502.9098 : 491.2065 ; + //temp_offset = limit ? 273.8195 : 273.15 ; + //two_p_bits = limit ? 65536: 65535; + temp_coeff = 503.975; + temp_offset = 273.15; + two_p_bits = 65536; + real_result = 2* ((drp_temp * temp_coeff / two_p_bits) - temp_offset); + //mantissa = $rtoi (real_result); + mantissa = real_result; + drp_to_linear11 = {5'h1F,mantissa}; + //$display("drp_to_linear11: drp_temp=h%0h, real_result = g%0g, real_result = h%0g, mantissa=h%0h, output= h%0h @%0t\n", + // drp_temp, real_result, real_result, mantissa, drp_to_linear11, $time/1000); + end + endfunction + + always @(posedge RESET_in or posedge i2c_stop or posedge i2c_start or negedge I2C_SCLK_in) begin + if(RESET_in ||i2c_stop ||i2c_start ) + pmb_wr_exec <= 0; + else if (pmb_state==ST_PMB_WRITE && pmb_data_end) + pmb_wr_exec <= 1; + else + pmb_wr_exec <= 0; + end + + assign pmb_wr_exec_pe = pmb_wr_exec & ~pmb_wr_exec_d; + + always @(posedge RESET_in or posedge i2c_stop or posedge i2c_start or posedge DCLK_in) begin + if(RESET_in ||i2c_stop ||i2c_start ) + pmb_wr_exec_d <= 0; + else + pmb_wr_exec_d <= pmb_wr_exec; + end + + always @(posedge DCLK_in) begin + @(posedge pmb_wr_exec); + if (pmb_cmd_in==CMD_PAGE || + pmb_cmd_in==CMD_VOUT_UV_FAULT_LIMIT || + pmb_cmd_in==CMD_VOUT_OV_FAULT_LIMIT || + pmb_cmd_in==CMD_OT_FAULT_LIMIT || + pmb_cmd_in==CMD_OT_WARNING_LIMIT || + pmb_cmd_in==CMD_UT_FAULT_LIMIT || + pmb_cmd_in==CMD_UT_WARNING_LIMIT || + pmb_cmd_in==CMD_MFR_ACCESS_REG + ) + @(negedge pmb_wr_exec); + @(posedge DCLK_in); + pmb_wr_exec_2 = 1; + @(posedge DCLK_in); + pmb_wr_exec_2 = 0; + end + + //PMB write execute + always @(posedge RESET_in or posedge pmb_wr_exec or posedge DCLK_in) begin + if(RESET_in) begin + pmb_read_only_cmd <=0; + pmb_clr_status_vout <='d0; + pmb_clr_status_temperature <='d0; + pmb_clr_status_cml <='d0; + pmb_drsram_wr_data <='d0; + pmb_drsram_addr <='d0; + end + else if(pmb_wr_exec) begin + pmb_read_only_cmd <=0; + pmb_clr_status_vout <='d0; + pmb_clr_status_temperature <='d0; + pmb_clr_status_cml <='d0; + pmb_drsram_wr_data <='d0; + pmb_drsram_addr <='d0; + case (pmb_cmd_in) + CMD_PAGE : ; //seperated to another always block for readibility + CMD_CLEAR_FAULT : pmb_read_only_cmd <=1; //Error: Too many bytes + CMD_VOUT_OV_FAULT_LIMIT : begin + dr_sram[pmb_page_up_l] <= linear16_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear16_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= pmb_page_up_l; + end + CMD_VOUT_UV_FAULT_LIMIT : begin + dr_sram[pmb_page_lo_l] <= linear16_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear16_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= pmb_page_lo_l; + end + CMD_OT_FAULT_LIMIT : begin + dr_sram[8'h53] <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= 8'h53; + end + CMD_OT_WARNING_LIMIT : begin + dr_sram[8'h50] <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= 8'h50; + end + CMD_UT_WARNING_LIMIT : begin + dr_sram[8'h54] <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= 8'h54; + end + CMD_UT_FAULT_LIMIT : begin + dr_sram[8'h57] <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]); + pmb_drsram_addr <= 8'h57; + end + CMD_STATUS_VOUT : pmb_clr_status_vout <= pmb_data_in[7:0]; + CMD_STATUS_TEMPERATURE : pmb_clr_status_temperature <= pmb_data_in[7:0]; + CMD_STATUS_CML : pmb_clr_status_cml <= pmb_data_in[7:0]; + CMD_MFR_SELECT_REG : begin + pmb_sel_addr <= pmb_data_in[7:0]; + // Checked reserved error message + if(is_reserved_address(pmb_sel_addr)) + $display("Warning: [Unisim %s] PMBus MFR_SELECT_REG command is trying to point to a RESERVED location h%0X.", MODULE_NAME, pmb_sel_addr, $time/1000.0); + end + CMD_MFR_ACCESS_REG : begin + if(pmb_sel_addr >= 8'h40) + dr_sram[pmb_sel_addr] <= pmb_data_in[15:0]; + pmb_drsram_addr <= pmb_sel_addr; + pmb_drsram_wr_data <= pmb_data_in[15:0]; + end + CMD_CAPABILITY , CMD_VOUT_MODE , + CMD_STATUS_BYTE , CMD_STATUS_WORD , + CMD_READ_VOUT , CMD_READ_TEMPERATURE_1, + CMD_PMBUS_REVISION , CMD_MFR_ID , + CMD_MFR_MODEL , CMD_MFR_REVISION , + CMD_MFR_READ_VOUT_MAX , CMD_MFR_READ_VOUT_MIN , + CMD_MFR_READ_TEMP_MAX , CMD_MFR_READ_TEMP_MIN , + CMD_MFR_ENABLE_VUSER_HR: + begin + pmb_read_only_cmd <=1; //Error: Too many bytes + end + //default: + endcase + end //else if + else begin //pmb_wr_exec==0 and posedge (dclk_in) + pmb_read_only_cmd <=0; + pmb_clr_status_vout <='d0; + pmb_clr_status_temperature <='d0; + pmb_clr_status_cml <='d0; + // Keep pmb_drsram_addr and pmb_drsram_wr_data values + // as they will be used with delay + end + end //always + + //PMB write execute for page command + always @(posedge RESET_in or posedge pmb_wr_exec or negedge I2C_SCLK_in) begin + if(RESET_in) begin + pmb_drsram_bit_idx <= 'd0; + pmb_drsram_addr_page <= 'd0; + pmb_page_index <= 'd0; + pmb_page_stat <= 'd0; + pmb_page_max <= 'd0; + pmb_page_min <= 'd0; + pmb_page_up_l <= 'd0; + pmb_page_lo_l <= 'd0; + pmb_page_alm_id <= 'd1; + pmb_valid_page <= 0; + pmb_page_6V <= 0; + end + else if(pmb_wr_exec && pmb_cmd_in==CMD_PAGE) begin // || pmb_cmd_in==CMD_MFR_SELECT_REG) begin + pmb_page_index <= pmb_data_in[7:0]; + pmb_drsram_bit_idx <= 'd0; + pmb_drsram_addr_page<= 'd0; + case (pmb_data_in[7:0]) + 8'd1: begin //VCC INT + dr_sram[8'h48][9]<= 1'b1; //Add this channel to sequence + pmb_drsram_addr_page <= 8'h48; + pmb_drsram_bit_idx <= 'd9; + pmb_page_stat <= 8'h01; + pmb_page_max <= 8'h21; + pmb_page_min <= 8'h25; + pmb_page_up_l <= 8'h51; + pmb_page_lo_l <= 8'h55; + pmb_page_alm_id <= 'd1; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd2: begin //VCC AUX + dr_sram[8'h48][10]<= 1'b1; + pmb_drsram_addr_page <= 8'h48; + pmb_drsram_bit_idx <= 'd10; + pmb_page_stat <= 8'h02; + pmb_page_max <= 8'h22; + pmb_page_min <= 8'h26; + pmb_page_up_l <= 8'h52; + pmb_page_lo_l <= 8'h56; + pmb_page_alm_id <= 'd2; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd6: begin //VCC BRAM + dr_sram[8'h48][14]<= 1'b1; + pmb_drsram_addr_page <= 8'h48; + pmb_drsram_bit_idx <= 'd14; + pmb_page_stat <= 8'h06; + pmb_page_max <= 8'h23; + pmb_page_min <= 8'h27; + pmb_page_up_l <= 8'h58; + pmb_page_lo_l <= 8'h5C; + pmb_page_alm_id <= 'd3; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd13:begin // VCC PSINTLP + dr_sram[8'h48][7]<= 1'b1; + pmb_drsram_addr_page<= 8'h48; + pmb_drsram_bit_idx <= 'd7; + pmb_page_stat <= 8'h0D; + pmb_page_max <= 8'h28; + pmb_page_min <= 8'h2C; + pmb_page_up_l <= 8'h59; + pmb_page_lo_l <= 8'h5D; + pmb_page_alm_id <= 'd4; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd14:begin // VCC PSINTFP + dr_sram[8'h48][6]<= 1'b1; + pmb_drsram_addr_page<= 8'h48; + pmb_drsram_bit_idx <= 'd6; + pmb_page_stat <= 8'h0E; + pmb_page_max <= 8'h29; + pmb_page_min <= 8'h2D; + pmb_page_up_l <= 8'h5A; + pmb_page_lo_l <= 8'h5E; + pmb_page_alm_id <= 'd5; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd15:begin // VCC PSAUX + dr_sram[8'h48][5]<= 1'b1; + pmb_drsram_addr_page<= 8'h48; + pmb_drsram_bit_idx <= 'd5; + pmb_page_stat <= 8'h0F; + pmb_page_max <= 8'h2A; + pmb_page_min <= 8'h2E; + pmb_page_up_l <= 8'h5B; + pmb_page_lo_l <= 8'h5F; + pmb_page_alm_id <= 'd6; + pmb_valid_page <= 1; + pmb_page_6V <= 0; + end + 8'd32:begin //VUSER 0 + dr_sram[8'h46][0]<= 1'b1; + pmb_drsram_addr_page<= 8'h46; + pmb_drsram_bit_idx <= 'd0; + pmb_page_stat <= 8'h80; + pmb_page_max <= 8'hA0; + pmb_page_min <= 8'hA8; + pmb_page_up_l <= 8'h60; + pmb_page_lo_l <= 8'h68; + pmb_page_alm_id <= 'd8; + pmb_valid_page <= 1; + pmb_page_6V <= bank_sel_6V[0]; + end + 8'd33:begin //VUSER 1 + dr_sram[8'h46][1]<= 1'b1; + pmb_drsram_addr_page<= 8'h46; + pmb_drsram_bit_idx <= 'd1; + pmb_page_stat <= 8'h81; + pmb_page_max <= 8'hA1; + pmb_page_min <= 8'hA9; + pmb_page_up_l <= 8'h61; + pmb_page_lo_l <= 8'h69; + pmb_page_alm_id <= 'd9; + pmb_valid_page <= 1; + pmb_page_6V <= bank_sel_6V[1]; + end + 8'd34:begin //VUSER 2 + dr_sram[8'h46][2]<= 1'b1; + pmb_drsram_addr_page<= 8'h46; + pmb_drsram_bit_idx <= 'd2; + pmb_page_stat <= 8'h82; + pmb_page_max <= 8'hA2; + pmb_page_min <= 8'hAA; + pmb_page_up_l <= 8'h62; + pmb_page_lo_l <= 8'h6A; + pmb_page_alm_id <= 'd10; + pmb_valid_page <= 1; + pmb_page_6V <= bank_sel_6V[2]; + end + 8'd35:begin //VUSER 3 + dr_sram[8'h46][3]<= 1'b1; + pmb_drsram_addr_page<= 8'h46; + pmb_drsram_bit_idx <= 'd3; + pmb_page_stat <= 8'h83; + pmb_page_max <= 8'hA3; + pmb_page_min <= 8'hAB; + pmb_page_up_l <= 8'h63; + pmb_page_lo_l <= 8'h6B; + pmb_page_alm_id <= 'd11; + pmb_valid_page <= 1; + pmb_page_6V <= bank_sel_6V[3]; + end + default:begin + pmb_drsram_addr_page<= 'd0; + pmb_drsram_bit_idx <= 'd0; + pmb_page_stat <= 8'd0; + pmb_page_max <= 8'd0; + pmb_page_min <= 8'd0; + pmb_page_up_l <= 8'd0; + pmb_page_lo_l <= 8'd0; + pmb_page_alm_id <= 'd1; + pmb_valid_page <= 0; + pmb_page_6V <= 0; + $display("Warning: [Unisim %s-55] PMBus page command received an invalid Page index @ time %0t", MODULE_NAME, $time); + end + endcase + end // pmb_wr_exec + else begin + end + end //always + + //PMBus read execute + always @(posedge RESET_in or negedge I2C_SCLK_in) begin + if(RESET_in) + pmb_unsp_data <= 0; //unsupported data // This is not a read command + else begin + // need to fetch before we know if we are going to get a read or write request + if(pmb_state==ST_PMB_GET_ADDR & !i2c_ack_bit) begin + pmb_data_out <= 32'h00000000; + case (pmb_cmd_in) + CMD_PAGE : pmb_data_out[7:0] <= pmb_page_index; + CMD_CLEAR_FAULT : begin + pmb_unsp_data <= 1; //unsupported data // This is not a read command. validate after + pmb_data_out[31:0] <= 31'hXXXXXXXX; //invalid command gets and x. + end + CMD_CAPABILITY : pmb_data_out[7:0] <= 8'h30; + CMD_VOUT_MODE : pmb_data_out[7:0] <= 8'h12; + CMD_VOUT_OV_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear16(dr_sram[pmb_page_up_l]); + CMD_VOUT_UV_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear16(dr_sram[pmb_page_lo_l]); + CMD_OT_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h53]); + CMD_OT_WARNING_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h50]); + CMD_UT_WARNING_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h54]); + CMD_UT_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h57]); + CMD_STATUS_BYTE : pmb_data_out[7:0] <= pmb_status_byte; + CMD_STATUS_WORD : pmb_data_out[15:0] <= {pmb_status_word,pmb_status_byte}; + CMD_STATUS_VOUT : pmb_data_out[7:0] <= pmb_status_vout; + CMD_STATUS_TEMPERATURE : pmb_data_out[7:0] <= pmb_status_temperature; + CMD_STATUS_CML : pmb_data_out[7:0] <= pmb_status_cml; + CMD_READ_VOUT : begin + if(pmb_page_stat >= 8'h40) + pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_stat]); + else + pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_stat]); + end + CMD_READ_TEMPERATURE_1 : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h00]); + CMD_PMBUS_REVISION : pmb_data_out[7:0] <= 8'h42; + CMD_MFR_ID : begin + pmb_data_out[7:0] <= 8'h03; //in block read, first byte is the length of the rest of the data + pmb_data_out[15:8] <= 8'h93; + pmb_data_out[23:16] <= 8'h00; + pmb_data_out[31:24] <= 8'h00; + + end + CMD_MFR_MODEL : begin + pmb_data_out[7:0] <= 8'h03; //in block read, first byte is the length of the rest of the data + pmb_data_out[15:8] <= 8'h00; + pmb_data_out[23:16] <= 8'h00; + pmb_data_out[31:24] <= 8'h00; + end + CMD_MFR_REVISION : begin + pmb_data_out[7:0] <= 8'h02; //in block read, first byte is the length of the rest of the data + pmb_data_out[15:8] <= 8'h00; + pmb_data_out[23:16] <= 8'h00; + end + CMD_MFR_SELECT_REG : pmb_data_out[7:0] <= pmb_sel_addr; + CMD_MFR_ACCESS_REG : begin + if(pmb_sel_addr >= 8'h40) + pmb_data_out[15:0] <= dr_sram [pmb_sel_addr]; + else + pmb_data_out[15:0] <= data_reg[pmb_sel_addr]; + end + CMD_MFR_READ_VOUT_MAX : begin + if(pmb_page_max>='h40) + pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_max]); + else + pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_max]); + end + CMD_MFR_READ_VOUT_MIN : begin + if(pmb_page_min>='h40) + pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_min]); + else + pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_min]); + end + CMD_MFR_ENABLE_VUSER_HR : pmb_data_out[3:0] <= cfg_reg4[3:0]; // as is + CMD_MFR_READ_TEMP_MAX : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h20]); + CMD_MFR_READ_TEMP_MIN : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h24]); + default: begin + pmb_data_out[31:0] <= 32'h00000000; //invalid command + end + endcase + + if (pmb_ara_rcvd ) begin //&& (pmb_state==ST_PMB_GET_ADDR)) begin + pmb_data_out[31:8] <= 24'd0; + pmb_data_out[7:1] <= i2c_device_addr | 7'b0000100; + pmb_data_out[0] <= 1'b0; //lsb of the response is don't care. + end + end + else if (i2c_lsb_bit && pmb_state==ST_PMB_READ ) + pmb_data_out <= {8'b0,pmb_data_out[31:8]}; //shift the higher byte to lower + else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out. + pmb_data_out <= {pmb_data_out[31:8],pmb_data_out[6:0],1'b0}; + end + end //always + + // PMBus fault handling + always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin + if(sysmon_rst || pmb_clear) begin + pmb_status_word <= 'd0; + pmb_status_byte <= 'd0; + end + else begin + pmb_status_word[7] <= |pmb_status_vout[7:0]; + pmb_status_word[6:0] <= 7'd0; //Reserved + + pmb_status_byte[7:6] <= 2'd0; //Reserved + pmb_status_byte[5] <= pmb_status_vout[7]; + pmb_status_byte[4:3] <= 2'd0; //Reserved + pmb_status_byte[2] <= |pmb_status_temperature[7:0]; + pmb_status_byte[1] <= |pmb_status_cml[7:0]; + pmb_status_byte[0] <= 1'b0; //None of the above is undefined + end + end + + always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin + if(sysmon_rst || pmb_clear) + pmb_status_temperature <='d0; + else begin + pmb_status_temperature[7] <= pmb_clr_status_temperature[7] ? 0 : (OT_out & !ut_fault); + pmb_status_temperature[6] <= pmb_clr_status_temperature[6] ? 0 : (ALM_out[0] & !ut_warn); + pmb_status_temperature[5] <= pmb_clr_status_temperature[5] ? 0 : ut_warn; + pmb_status_temperature[4] <= pmb_clr_status_temperature[4] ? 0 : ut_fault; + pmb_status_temperature[3:0] <= 4'd0; + end + end + + always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin + if(sysmon_rst || pmb_clear) + pmb_status_vout <= 'd0; + else if (pmb_paged) begin + pmb_status_vout[7] <= pmb_clr_status_vout[7]? 0: (ALM_out[pmb_page_alm_id] && !alm_ut[pmb_page_alm_id]); //Over voltage + pmb_status_vout[6:5] <= 'd0; //Reserved + pmb_status_vout[4] <= pmb_clr_status_vout[4]? 0: alm_ut[pmb_page_alm_id]; //Under voltage + pmb_status_vout[3:0] <= 'd0; //Reserved + end + end + + always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin + if(sysmon_rst || pmb_clear) + pmb_status_cml <= 'd0; + else begin + pmb_status_cml[7] <= pmb_clr_status_cml[7] ? 0 : pmb_unsp_cmd; + pmb_status_cml[6] <= pmb_clr_status_cml[6] ? 0 : (pmb_unsp_data || pmb_read_only_cmd); + pmb_status_cml[5:2] <= 'd0; //Reserved + pmb_status_cml[1] <= pmb_clr_status_cml[1] ? 0 : 0; //Other/TBD + pmb_status_cml[0] <= 'd0; //Reserved + end + end + + always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin + if(sysmon_rst || pmb_clear ) + SMBALERT_TS_out <= 1; // active negative + else begin + SMBALERT_TS_out <= !((|pmb_status_word) || (|pmb_status_byte)); + end + end + + //---- End of PMBus logic ------------------------------------------------ + + //--------------------------------------------------------------------- + // Clock divider, generate and adcclk + + assign adcclk_period_end = (adcclk_count ==curr_clkdiv_sel-1); + assign adcclk_period_start = (adcclk_count == 0); + + always @(posedge DCLK_in) + adcclk_period_end_d <= adcclk_period_end; + + always @(posedge DCLK_in) + sysclk <= ~sysclk; + + always @(posedge DCLK_in ) begin + if (curr_clkdiv_sel > 'd2 || adcclk_count_rst) begin + if ((adcclk_count >= curr_clkdiv_sel-1) || adcclk_count_rst) + adcclk_count <= 0; + else + adcclk_count <= adcclk_count + 1; + + if(adcclk_count_rst) + adcclk_tmp <= 1; + else if(adcclk_count <= curr_clkdiv_sel/2 -1) + adcclk_tmp <= 1; + else + adcclk_tmp <= 0; + end + else + adcclk_tmp <= ~adcclk_tmp; + end + + assign curr_clkdiv_sel = cfg_reg2[15:8]; + assign adcclk_div1 = (curr_clkdiv_sel > 'd2) ? 0 : 1; + assign adcclk = (adcclk_div1) ? ~sysclk : adcclk_tmp; + + // end clock divider + + //----------------------------------------------------------------- + // sequence control + //----------------------------------------------------------------- + + + assign lr_chan_on = (lr_tot_chan>0) && cont_seq_mode; + assign cont_seq_only_hr = (lr_tot_chan==0) && cont_seq_mode; + + + // CR-961759 When channel selection registers are changed, the update is after end of the sequence. + // In dual channel, EOS is optional, hence EOS_out is not used. + always @(posedge sysmon_rst or posedge DCLK_in) begin + if( sysmon_rst) + add_channel <= 0; + else begin //it has to be the final EOS of the final channel in the big loop hence tot_final_conversion + if(eoc_asrt && (!avg_en||avg_final_loop) && tot_final_conversion && (add_channel_hr_p||add_channel_lr_p)) + add_channel <= 1; + else + add_channel <= 0; + end + end + + always @(posedge sysmon_rst or posedge DCLK_in) begin //at initialization or sequence restart + if( sysmon_rst) begin + for(kk=0; kk<=CONV_CNT_P; kk=kk+1) begin + seq_hr_mem[kk] = 0; + seq_lr_mem[kk] = 0; + hr_tot_chan = 0; + lr_tot_chan = 0; + lr_calib_on = 0; + end + end + else if(initialize[1] || add_channel) begin + lr_calib_on = 0; + if (single_pass_active || cont_seq_mode) begin //single pass or continuous sequence mode + // high rate sequence + hr_tot_chan = 0; + for (si=0; (si<= 47&&hr_tot_chan<=31); si=si+1) begin + if ((seq_hr_chan_reg_comb[si] ==1) //begin + || (si==0 && seq_hr_chan_reg_comb[0]==0 && single_pass_active)) begin //calibration has to be added to single pass mode if not available + seq_hr_mem[hr_tot_chan] = si; + hr_tot_chan = hr_tot_chan + 1; + //seq_hr_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31. + if (hr_tot_chan==32) + $display ("Info: [Unisim %s-60] Max allowed channels are 31. Please check the high rate channel selection (46h,48h,49h). After 31, channels will be ignored.", MODULE_NAME); + end + end + if (cont_seq_mode) begin + //review for low rate high rate selection interaction + lr_tot_chan = 0; + for (si=0; si<= 47; si=si+1) begin + if (seq_lr_chan_reg_comb[si] ==1) begin + //low rate + if(seq_lr_chan_reg_comb[si]==seq_hr_chan_reg_comb[si] && !((si>=1 && si<=4)||si==15||(si>=36 && si<=47)) ) begin //CR 863886 + //handle duplicates first + case (si) + 6'h00 : begin + $display ("Info: [Unisim %s-29] In attribute INIT_7A[0], Calibration has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME); + lr_calib_on=0; + end + 6'h05 : $display ("Info: [Unisim %s-30] In attribute INIT_7A[5], VCC_PSAUX has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h06 : $display ("Info: [Unisim %s-31] In attribute INIT_7A[6], VCC_PSINTFP has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h07 : $display ("Info: [Unisim %s-32] In attribute INIT_7A[7], VCC_PSINTLP has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h08 : $display ("Info: [Unisim %s-33] In attribute INIT_7A[8], TEMPERATURE has already been selected for the ADC channel sequence with INIT_48[8]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h09 : $display ("Info: [Unisim %s-34] In attribute INIT_7A[9], INT_AVG has already been selected for the ADC channel sequence with INIT_48[9]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h0A : $display ("Info: [Unisim %s-35] In attribute INIT_7A[10], AUX_AVG has already been selected for the ADC channel sequence with INIT_48[10]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h0B : $display ("Info: [Unisim %s-36] In attribute INIT_7A[11], VpVn has already been selected for the ADC channel sequence with INIT_48[11]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h0C : $display ("Info: [Unisim %s-37] In attribute INIT_7A[12], VREFP has already been selected for the ADC channel sequence with INIT_48[12]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h0D : $display ("Info: [Unisim %s-38] In attribute INIT_7A[13], VREFN has already been selected for the ADC channel sequence with INIT_48[13]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h0E : $display ("Info: [Unisim %s-39] In attribute INIT_7A[14], BRAM has already been selected for the ADC channel sequence with INIT_48[14]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h10, 6'h11, 6'h12, 6'h13, 6'h14, 6'h15, 6'h16, 6'h17,6'h18, 6'h19, 6'h1A, 6'h1B,6'h1C, 6'h1D, 6'h1E, 6'h1F : + $display ("Info: [Unisim %s-41] In attribute INIT_7B[%0d], auxiliary analog input has already been selected for the ADC channel sequence with INIT_49[%0d]. It will be ignored in the low rate sequence.", MODULE_NAME, (si-16), (si-16)); + 6'h20 : $display ("Info: [Unisim %s-42] In attribute INIT_7C[0], USER0 has already been selected for the ADC channel sequence with INIT_46[0]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h21 : $display ("Info: [Unisim %s-43] In attribute INIT_7C[1], USER1 has already been selected for the ADC channel sequence with INIT_46[1]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h22 : $display ("Info: [Unisim %s-44] In attribute INIT_7C[2], USER2 has already been selected for the ADC channel sequence with INIT_46[2]. It will be ignored in the low rate sequence.", MODULE_NAME); + 6'h23 : $display ("Info: [Unisim %s-45] In attribute INIT_7C[3], USER3 has already been selected for the ADC channel sequence with INIT_46[3]. It will be ignored in the low rate sequence.", MODULE_NAME); + default : $display ("Info: [Unisim %s-40] In attribute INIT_7A, INIT_7B or INIT_7C, same selections have already been selected for the ADC channel sequence with INIT_46[],INIT_48[], or INIT_49[]. They will be ignored in the low rate sequence.", MODULE_NAME); + endcase + end + else begin + //not duplicate in low and high rate, only in low rate. stays as is. + seq_lr_mem[lr_tot_chan] = si; //seq_lr_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31. + lr_tot_chan = lr_tot_chan + 1; + if(si==0 && seq_lr_chan_reg_comb[0]==1) + lr_calib_on = 1; + end + end + else if(seq_hr_chan_reg_comb[si]==0 &&(si==0 || si==8)) begin + // handle missing ones + // seq_lr_chan_reg_comb[si]==0. Calibration and temperature are disabled in both by the user + seq_lr_mem[lr_tot_chan] = si; + lr_tot_chan = lr_tot_chan + 1; + if(si==0) begin + lr_calib_on = 1; + $display ("Info: [Unisim %s-51] Neither attribute INIT_7A[0] nor INIT_48[0] have been selected. Calibration will be enabled in the low rate sequence anyway.", MODULE_NAME); + end + else //si==8 + $display ("Info: [Unisim %s-52] Neither attribute INIT_7A[8] nor INIT_48[8] have been selected. Temperature will be enabled in the low rate sequence anyway.", MODULE_NAME); + end + end + end //for + if(hr_tot_chan==0) begin + $display ("Error: [Unisim %s-65] No channel was selected for HR. This is not a valid option. Simulation exiting.", MODULE_NAME); + #1 $finish; + end + end //cont_seq_mode for low rate + else if (default_mode ) begin //default mode + if(ext_mux) + $display("Info: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in default mode. Instance: %m", MODULE_NAME); + + if (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE == "ULTRASCALE_PLUS_ES1" || SIM_DEVICE == "ULTRASCALE_PLUS_ES2") begin + hr_tot_chan = 5; + seq_hr_mem[0] = 0; + seq_hr_mem[1] = 8; + seq_hr_mem[2] = 9; + seq_hr_mem[3] = 10; + seq_hr_mem[4] = 14; + end + else if (SIM_DEVICE == "ZYNQ_ULTRASCALE" || SIM_DEVICE == "ZYNQ_ULTRASCALE_ES1" || SIM_DEVICE == "ZYNQ_ULTRASCALE_ES2") begin + hr_tot_chan = 8; + seq_hr_mem[0] = 0; + seq_hr_mem[1] = 5; + seq_hr_mem[2] = 6; + seq_hr_mem[3] = 7; + seq_hr_mem[4] = 8; + seq_hr_mem[5] = 9; + seq_hr_mem[6] = 10; + seq_hr_mem[7] = 14; + end + end // default_mode + else if(single_chan_mode && ext_mux) + $display("Info: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in single channel mode. Instance: %m", MODULE_NAME); + end //initialize[1] || add_channel + end //always + + wire [15:0] chan_avg_hr_reg1; + wire [15:0] chan_avg_hr_reg2; + wire [15:0] chan_avg_hr_reg3; + wire [47:0] seq_avg_hr_reg_comb ; + wire chan_avg_hr_set; + + wire [15:0] chan_avg_lr_reg1; + wire [15:0] chan_avg_lr_reg2; + wire [15:0] chan_avg_lr_reg3; + wire [47:0] seq_avg_lr_reg_comb; + wire chan_avg_lr_set; + + assign chan_avg_hr_reg1 = seq_hr_chan_reg1 & seq_avg_reg1; + assign chan_avg_hr_reg2 = seq_hr_chan_reg2 & seq_avg_reg2; + assign chan_avg_hr_reg3 = seq_hr_chan_reg3 & seq_avg_reg3; + assign seq_avg_hr_reg_comb = {chan_avg_hr_reg3, chan_avg_hr_reg2, chan_avg_hr_reg1}; + assign chan_avg_hr_set = |seq_avg_hr_reg_comb; + + assign chan_avg_lr_reg1 = seq_lr_chan_reg1 & seq_avg_reg1; + assign chan_avg_lr_reg2 = seq_lr_chan_reg2 & seq_avg_reg2; + assign chan_avg_lr_reg3 = seq_lr_chan_reg3 & seq_avg_reg3; + assign seq_avg_lr_reg_comb = {chan_avg_lr_reg3, chan_avg_lr_reg2, chan_avg_lr_reg1}; + assign chan_avg_lr_set = |seq_avg_lr_reg_comb; + + //hr_lr_tot_per is the total period of the combined high and low rate sequences + assign int_tot_per = (hr_tot_chan * (4 ** lr_rate)) +1; + assign hr_lr_tot_per = lr_chan_on ? (int_tot_per * lr_tot_chan) : hr_tot_chan ; + assign tot_per = cont_seq_mode ? hr_lr_tot_per: + (single_pass_active|| default_mode) ? hr_tot_chan : + 1; //single_chan_mode + // or in unknown mode just calibrate + + // CR-961533 + // When SLOW_SEQ or SLOW_EOS are changed dynamically, the change should take place + // after mode change as per rtl design. + always @(posedge DCLK_in or posedge sysmon_rst) begin + if (sysmon_rst) begin + lr_eos <= 0; + lr_rate <= 0; + end + else if(initialize[0]) begin + lr_eos[1:0] <= cfg_reg4[11:10]; + lr_rate[1:0] <= cfg_reg4[9:8]; + end + end + + integer conv_tot_count; + integer conv_hr_count; + integer conv_lr_count; + wire [15:0] conv_hr_count_p; + wire [15:0] conv_lr_count_p; + integer avg_loop_count_hr; + integer avg_loop_count_lr; + + assign avg_final_loop = (!avg_en) || + (!avg_cur) || + (avg_final_loop_hr && !seq_lr_selected) || + (avg_final_loop_lr && seq_lr_selected) ; + assign avg_final_loop_hr = (avg_loop_count_hr == avg_amount); + assign avg_final_loop_lr = (avg_loop_count_lr == avg_amount); + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + conversion_before_calib <= 0; + hr_final_conversion <= 0; + tot_final_conversion <= 0; + lr_final_conversion <= 0; + end + else begin + if(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB) begin + conversion_before_calib <= 0; + hr_final_conversion <= 0; + tot_final_conversion <= 0; + lr_final_conversion <= 0; + end + else if(conv_track)begin //check + conversion_before_calib <= (CHANNEL_out!=8) && + ~(event_driven_mode && single_pass_mode) && + ((lr_chan_on && + ((~lr_calib_on && conv_hr_count==hr_tot_chan-1 && seq_lr_selected) || + ( lr_calib_on && conv_tot_count==tot_per-1))) || + (!lr_chan_on && conv_hr_count==hr_tot_chan-1) ); + hr_final_conversion <= (((hr_tot_chan==1 && !lr_calib_on) || CHANNEL_out!=8) && (conv_hr_count==hr_tot_chan-1)) || + (single_chan_mode && CHANNEL_out!=8); + tot_final_conversion <= (CHANNEL_out!=8) &&(conv_tot_count==tot_per-1); + lr_final_conversion <= (~lr_calib_on && conv_tot_count==tot_per-1) || + (lr_calib_on && lr_tot_chan>1 && conv_tot_count==tot_per-int_tot_per) || + (lr_calib_on && lr_tot_chan==1); + end + end + end //always + + + assign seq_lr_selected_p = lr_chan_on && //!seq_lr_selected && + ((lr_calib_on && ( conv_tot_count %int_tot_per)==int_tot_per-1) || //calibration being always on puts lr on first if calib is on lr channel. + (!lr_calib_on&& ( conv_tot_count %int_tot_per)==int_tot_per-2) ); //otherwise it is the last + + //pre calculate + assign conv_hr_count_p = (conv_hr_count < hr_tot_chan-1) ? (conv_hr_count+1) : (event_driven_mode && single_pass_mode) ? 1 : 0; + assign conv_lr_count_p = (conv_lr_count < lr_tot_chan-1) ? (conv_lr_count+1) : 0; + + always @(posedge sysmon_rst or posedge initialize[2] or posedge chan_asrt_1) begin + if(sysmon_rst) begin + conv_tot_count <= 0; + conv_hr_count <= 0; + conv_lr_count <= 0; + seq_lr_selected <= 0; + end + else begin + if( initialize[2] ) begin + conv_tot_count <= 0; + if(cont_seq_mode && lr_calib_on) begin + seq_lr_selected <= 1; + conv_hr_count <= 0; + conv_lr_count <= 0; + end + else begin + seq_lr_selected <= 0; + conv_hr_count <= 0; + conv_lr_count <= 0; + end + end + else if(chan_asrt_1 ) begin + //increase counters + if (conv_tot_count=16 && single_chan_id<=31)) begin + acq_ext_next <= acq_ext; + bipolar_next <= bipolar_mode; + end + else begin + acq_ext_next <= 0; + bipolar_next <= 0; + if(acq_ext || bipolar_mode) + $display("Info: [Unisim %s-68] In single channel mode, acquisition extension or bipolar mode cannot be enabled for non-analog channels. They will be ignored. Instance: %m", MODULE_NAME); + end + avg_next <= avg_en; + end + + end //initialization + + else if(chan_asrt_2) begin + + //Update current *_cur <=*_next; + chan_reg_id_cur <= chan_reg_id_next; + chan_out_id_cur <= chan_out_id_next; + acq_ext_cur <= acq_ext_next; + bipolar_cur <= bipolar_next; + avg_cur <= avg_next; + + //Update *_next + if(single_pass_active || + default_mode || + cont_seq_only_hr || + (lr_chan_on && !seq_lr_selected_p) + ) begin + chan_reg_id_next <= seq_hr_mem[conv_hr_count_p]; + chan_out_id_next <= conv_combregid_to_chanout(seq_hr_mem[conv_hr_count_p]); + acq_ext_next <= seq_acq_ext_reg_comb[seq_hr_mem[conv_hr_count_p]]; + bipolar_next <= seq_bipolar_reg_comb[seq_hr_mem[conv_hr_count_p]]; + avg_next <= avg_en ? (default_mode ? 1: seq_avg_hr_reg_comb[seq_hr_mem[conv_hr_count_p]]) : 0; + end + else if (cont_seq_mode) begin// lr_tot_chan>0 && seq_lr_selected + chan_reg_id_next <= seq_lr_mem[conv_lr_count]; + chan_out_id_next <= conv_combregid_to_chanout(seq_lr_mem[conv_lr_count]); + acq_ext_next <= seq_acq_ext_reg_comb[seq_lr_mem[conv_lr_count]]; + bipolar_next <= seq_bipolar_reg_comb[seq_lr_mem[conv_lr_count]]; + avg_next <= avg_en ? seq_avg_lr_reg_comb[seq_lr_mem[conv_lr_count]] : 0 ; + end + //else if single_chan_mode: in single channel mode no need to update the next. + + end + end + + + //----------------------------------------------------------- + // EOC and EOS + //----------------------------------------------------------- + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) begin + EOC_out <= 0; + EOS_out <= 0; + end + else begin + if(eoc_asrt && (!avg_en || !avg_cur || (avg_en && avg_cur && avg_final_loop) ) ) begin + EOC_out <= 1; + if(((!lr_chan_on && hr_final_conversion) || // eos selection is available only when lr chan is active. otherwise always on. + (lr_chan_on && hr_final_conversion && !seq_lr_selected && lr_eos!=LR_EOS_LR_ONLY) || //hr + (lr_chan_on && lr_final_conversion && seq_lr_selected && (lr_eos==LR_EOS_HR_LR || lr_eos==LR_EOS_LR_ONLY)) //lr + ) && !single_chan_mode) //CR-1049898 + EOS_out <= 1; + else + EOS_out <= 0; + end + else begin + EOC_out <= 0; + EOS_out <= 0; + end + end + end + + + + +//----------------------------------------------------- +// Conversion +//----------------------------------------------------- + + always @(posedge sysmon_rst or posedge chan_asrt_1) begin + if (sysmon_rst == 1) begin + mn_mux_in <= 0.0; + end + else if(chan_asrt_1) begin + if ( chan_out_id_next == 7 || (chan_out_id_next >= 9 && chan_out_id_next <= 12) || chan_out_id_next >= 36) + $display("Warning: [Unisim %s-14] The analog channel %x at time %.3f ns is invalid. Check register 40h[5:0]. Instance: %m", MODULE_NAME, chan_out_id_next, $time/1000.0); + //K else if(bipolar_next) begin //can only be enabled for channels 3,16-31 + else if ((chan_out_id_next == 3) || (chan_out_id_next >= 16 && chan_out_id_next <= 31)) begin + if (ext_mux_en) begin + tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan_id]); + mn_mux_in <= tmp_v; + end + else begin + tmp_v = $bitstoreal(mn_in_diff[chan_out_id_next]); + mn_mux_in <= tmp_v; + end + end + else + mn_mux_in <= $bitstoreal(mn_in_uni[chan_out_id_next]); + + end //chan_asrt_1 + end //always + + // Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only + //always @(posedge DCLK_in or posedge sysmon_rst ) begin + always @(posedge chan_asrt_3 ) begin + if (!sysmon_rst) + if( chan_asrt_3 && !bipolar_mode && ((chan_out_id_cur == 3) || (chan_out_id_cur >= 16 && chan_out_id_cur <= 31))) begin + chan_val_p_tmp = $bitstoreal(chan_val_tmp [chan_out_id_cur]); + chan_val_n_tmp = $bitstoreal(chan_valn_tmp[chan_out_id_cur]); + + if (!bipolar_cur &&( chan_val_n_tmp > chan_val_p_tmp)) + $display("Warning: [Unisim %s-8] The N input for external channel %x must be smaller than P input when in unipolar mode. (P=%0.2f N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + if (!bipolar_cur &&( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0)) + $display("Warning: [Unisim %s-9] The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode. (N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_n_tmp, $time/1000.0); + if (bipolar_cur && (((chan_val_p_tmp-chan_val_n_tmp) > 0.5)|| ((chan_val_p_tmp-chan_val_n_tmp) <-0.5))) + $display("Warning: [Unisim %s-56] Vp-Vn for external channel %x must be in [-0.5,0.5] V range when in bipolar mode. (P=%0.2f N=%0.2f ) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + end + end + + + always @(posedge chan_asrt_3) begin + if (chan_out_id_cur == 0) begin // adc temperature conversion + if(SIM_DEVICE=="ULTRASCALE_PLUS" || SIM_DEVICE=="ZYNQ_ULTRASCALE" || SIM_DEVICE=="ULTRASCALE_PLUS_ES2" || SIM_DEVICE=="ZYNQ_ULTRASCALE_ES2") + adc_temp_result = (mn_mux_in + 280.2308787) * 0.00196343 * 65535.0; //CR 961722 10/20/2016. Internal reference + else // ES1 + adc_temp_result = (mn_mux_in + 273.15) * 0.00203580 * 65535.0; //CR 912341 + + if (adc_temp_result >= 65535.0) + conv_result_int = 65535; + else if (adc_temp_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_temp_result); + if (adc_temp_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (chan_out_id_cur == 1 || chan_out_id_cur == 2 || chan_out_id_cur ==6 || + chan_out_id_cur == 13 || chan_out_id_cur == 14 || chan_out_id_cur == 15 || + (chan_out_id_cur >= 32 && chan_out_id_cur <= 35)) begin // internal power conversion + + if((chan_out_id_cur >= 32 && chan_out_id_cur <= 35) && + bank_sel_6V[chan_out_id_cur-32]==1) // CR 949547 + adc_intpwr_result = mn_mux_in * 65536.0 / 6.0; //6V range is selected, only available for VUSER ports + else + adc_intpwr_result = mn_mux_in * 65536.0 / 3.0; //3V range, hence divide by 3 + + if (adc_intpwr_result >= 65535.0) // max value is 'hFFFF + conv_result_int = 65535; + else if (adc_intpwr_result < 0.0) // min value is 0 + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_intpwr_result); + if (adc_intpwr_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (chan_out_id_cur == 3 || (chan_out_id_cur >=16 && chan_out_id_cur <= 31)) begin + adc_ext_result = (mn_mux_in) * 65536.0 ; //1V input range, hence divide by 1 + if (bipolar_cur == 1) begin //bipolar maps -0.5V to 0.5V to -32768-32767 range + if (adc_ext_result > 32767.0) //+0.5V + conv_result_int = 32767; + else if (adc_ext_result < -32768.0) //-0.5V + conv_result_int = -32768; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else begin //unipolar maps 0V to 1V to 0-65535 range + if (adc_ext_result > 65535.0) + conv_result_int = 65535; + else if (adc_ext_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + end + else begin //invalid channel + conv_result_int = 0; + end + + conv_result = conv_result_int; + + end // always + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if (sysmon_rst == 1) + conv_result_reg <= 0; + else begin + if (chan_asrt_4) + conv_result_reg <= conv_result; + end + end + + + //--------------------------------------------------------- + // average + //--------------------------------------------------------- + assign averaging = default_mode ? 2'b01 : cfg_reg0[13:12]; + assign avg_amount = averaging==2'b00 ? 0 : + averaging==2'b01 ? 15 : + averaging==2'b10 ? 63 : + averaging==2'b11 ? 255 : + 0; + + // In continuous mode, at least 1 channel in HR or LR should have averaging + // enabled so that averaging is practically enabled. + assign avg_en = single_pass_mode ? 0 : + default_mode ? 1 : + (averaging!=2'b00 && (single_chan_mode || chan_avg_hr_set || chan_avg_lr_set)); + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if (sysmon_rst) begin + conv_acc_result = 16'd0; + conv_acc_vec = 24'd0; + for (j = 0; j <= 63; j = j + 1) + conv_acc[j] = 0; + end + else begin + if(EOC_out==1 && avg_cur && avg_final_loop) begin + conv_acc_result = 16'd0; + conv_acc_vec = 24'd0; + conv_acc[chan_out_id_cur] = 0; + end + else if (chan_asrt_4 && avg_cur) begin + conv_acc[chan_out_id_cur] = conv_acc[chan_out_id_cur] + conv_result_int; + + conv_acc_vec = conv_acc[chan_out_id_cur]; + + case (averaging) + 2'b00 : conv_acc_result = 16'd0; + 2'b01 : conv_acc_result = conv_acc_vec[19:4]; + 2'b10 : conv_acc_result = conv_acc_vec[21:6]; + 2'b11 : conv_acc_result = conv_acc_vec[23:8]; + endcase + end + end // if (sysmon_rst == 0) + end + + // end average + + + always @( posedge DCLK_in or posedge alm_rst or posedge gsr_in ) begin + if(alm_rst ==1 || gsr_in==1) begin + data_reg[32] = 16'h0000; + data_reg[33] = 16'h0000; + data_reg[34] = 16'h0000; + data_reg[35] = 16'h0000; + data_reg[36] = 16'hFFFF; + data_reg[37] = 16'hFFFF; + data_reg[38] = 16'hFFFF; + data_reg[39] = 16'hFFFF; + data_reg[40] = 16'h0000; + data_reg[41] = 16'h0000; + data_reg[42] = 16'h0000; + data_reg[44] = 16'hFFFF; + data_reg[45] = 16'hFFFF; + data_reg[46] = 16'hFFFF; + dr_sram [160] = 16'h0000; + dr_sram [161] = 16'h0000; + dr_sram [162] = 16'h0000; + dr_sram [163] = 16'h0000; + dr_sram [168] = 16'hFFFF; + dr_sram [169] = 16'hFFFF; + dr_sram [170] = 16'hFFFF; + dr_sram [171] = 16'hFFFF; + end + else if (alm_asrt && avg_final_loop) begin + // current or averaged values' update to status registers + if ((chan_out_id_cur >= 0 && chan_out_id_cur <= 3) || (chan_out_id_cur == 6) || + (chan_out_id_cur >= 13 && chan_out_id_cur <= 31)) begin + if (avg_cur == 0) + data_reg[chan_out_id_cur] <= conv_result_reg; + else if(avg_final_loop) + data_reg[chan_out_id_cur] <= conv_acc_result; + end + else if (chan_out_id_cur >= 32 && chan_out_id_cur <= 35) begin //VUser0-3 + if (avg_cur == 0) + dr_sram[chan_out_id_cur + 96] <= conv_result_reg; //80h-83h + else if(avg_final_loop) + dr_sram[chan_out_id_cur + 96] <= conv_acc_result; + end + else if (chan_out_id_cur == 4) // VREFP + data_reg[chan_out_id_cur] <= 16'h0000; // CR-961722 Simulation always simulates the internal reference behavior. Hence VrefP=0V + else if (chan_out_id_cur == 5) // VREFN + data_reg[chan_out_id_cur] <= 16'h0000; + + //min and max values' update + if (chan_out_id_cur == 0 || chan_out_id_cur == 1 || chan_out_id_cur == 2) begin //TEMPERATURE, VCCINT and VCCAUX max and min + if (avg_cur == 0) begin + if (conv_result_reg > data_reg[32 + chan_out_id_cur]) + data_reg[32 + chan_out_id_cur] <= conv_result_reg; + if (conv_result_reg < data_reg[36 + chan_out_id_cur]) + data_reg[36 + chan_out_id_cur] <= conv_result_reg; + end + else if(avg_final_loop) begin + if (conv_acc_result > data_reg[32 + chan_out_id_cur]) + data_reg[32 + chan_out_id_cur] <= conv_acc_result; + if (conv_acc_result < data_reg[36 + chan_out_id_cur]) + data_reg[36 + chan_out_id_cur] <= conv_acc_result; + end + end + + else if (chan_out_id_cur == 6) begin //VCCBRAM max and min + if (avg_cur == 0) begin + if (conv_result_reg > data_reg[35]) + data_reg[35] <= conv_result_reg; + if (conv_result_reg < data_reg[39]) + data_reg[39] <= conv_result_reg; + end + else if(avg_final_loop) begin + if (conv_acc_result > data_reg[35]) + data_reg[35] <= conv_acc_result; + if (conv_acc_result < data_reg[39]) + data_reg[39] <= conv_acc_result; + end + end + else if (chan_out_id_cur >= 13 && chan_out_id_cur <= 15) begin // VPSINTLP, VPSINTFP , VPSAUX + if (avg_cur == 0) begin + if (conv_result_reg > data_reg[27+chan_out_id_cur]) + data_reg[27+chan_out_id_cur] <= conv_result_reg; + if (conv_result_reg < data_reg[31+chan_out_id_cur]) + data_reg[31+chan_out_id_cur] <= conv_result_reg; + end + else if(avg_final_loop) begin + if (conv_acc_result > data_reg[27+chan_out_id_cur]) + data_reg[27+chan_out_id_cur] <= conv_acc_result; + if (conv_acc_result < data_reg[31+chan_out_id_cur]) + data_reg[31+chan_out_id_cur] <= conv_acc_result; + end + end + else if (chan_out_id_cur >= 32 && chan_out_id_cur <=35) begin //Vuser0-3 + if (avg_cur == 0) begin + if (conv_result_reg < dr_sram[chan_out_id_cur+136]) + dr_sram[chan_out_id_cur+136] <= conv_result_reg; + if (conv_result_reg > dr_sram[chan_out_id_cur+128]) + dr_sram[chan_out_id_cur+128] <= conv_result_reg; + end + else if(avg_final_loop) begin + if (conv_acc_result < dr_sram[chan_out_id_cur+136]) + dr_sram[chan_out_id_cur+136] <= conv_acc_result; + if (conv_acc_result > dr_sram[chan_out_id_cur+128]) + dr_sram[chan_out_id_cur+128] <= conv_acc_result; + end + end + + end // ( rst_lock == 0) + end//always + + + always @(posedge DCLK_in or posedge sysmon_rst) begin + if(sysmon_rst) + data_written <= 0; + else if(chan_asrt_5) begin + if (avg_cur) + data_written <= conv_acc_result; + else + data_written <= conv_result_reg; + end + end + + always @( posedge DCLK_in or posedge alm_rst or posedge gsr_in ) begin + if(alm_rst ==1 || gsr_in==1) begin + ot_out_reg <= 0; + alm_out_reg <= 8'b0; + end + else if (alm_asrt && avg_final_loop) begin + if (chan_out_id_cur == 0) begin // temperature + if (data_written[15:4] >= ot_limit_reg[15:4]) begin + ot_out_reg <= 1; + end else if (dr_sram[8'h57][0] == 1'b1) begin + if (data_written[15:1] < dr_sram[8'h57][15:1]) begin + ot_out_reg <= 1; + end else begin + ot_out_reg <= 0; + end + end else if (data_written[15:1] < dr_sram[8'h57][15:1]) begin + ot_out_reg <= 0; + end + + if (data_written > dr_sram[8'h50]) begin + alm_out_reg[0] <= 1; + end else if (dr_sram[8'h54][0] == 1'b1) begin + if (data_written[15:1] < dr_sram[8'h54][15:1]) begin + alm_out_reg[0] <= 1; + end else begin + alm_out_reg[0] <= 0; + end + end else if (data_written[15:1] < dr_sram[8'h54][15:1]) begin + alm_out_reg[0] <= 0; + end + end + + if (chan_out_id_cur == 1) begin // VCC INT + if (data_written > dr_sram[8'h51] || data_written < dr_sram[8'h55]) + alm_out_reg[1] <= 1; + else + alm_out_reg[1] <= 0; + end + + if (chan_out_id_cur == 2) begin //VCCAUX + if (data_written > dr_sram[8'h52] || data_written < dr_sram[8'h56]) + alm_out_reg[2] <= 1; + else + alm_out_reg[2] <= 0; + end + + if (chan_out_id_cur == 6) begin // VCC BRAM + if (data_written > dr_sram[8'h58] || data_written < dr_sram[8'h5C]) + alm_out_reg[3] <= 1; + else + alm_out_reg[3] <= 0; + end + if (chan_out_id_cur == 13) begin //VCC PSINTLP + if (data_written > dr_sram[8'h59] || data_written < dr_sram[8'h5D]) + alm_out_reg[4] <= 1; + else + alm_out_reg[4] <= 0; + end + if (chan_out_id_cur == 14) begin // VCC PSINTFP + if (data_written > dr_sram[8'h5A] || data_written < dr_sram[8'h5E]) + alm_out_reg[5] <= 1; + else + alm_out_reg[5] <= 0; + end + if (chan_out_id_cur == 15) begin // VCC PSAUX + if (data_written > dr_sram[8'h5B] || data_written < dr_sram[8'h5F]) + alm_out_reg[6] <= 1; + else + alm_out_reg[6] <= 0; + end + if (chan_out_id_cur == 32) begin // VUSER 0 + if (data_written > dr_sram[8'h60] || data_written < dr_sram[8'h68]) + alm_out_reg[8] <= 1; + else + alm_out_reg[8] <= 0; + end + if (chan_out_id_cur == 33) begin // VUSER 1 + if (data_written > dr_sram[8'h61] || data_written < dr_sram[8'h69]) + alm_out_reg[9] <= 1; + else + alm_out_reg[9] <= 0; + end + if (chan_out_id_cur == 34) begin // VUSER 2 + if (data_written > dr_sram[8'h62] || data_written < dr_sram[8'h6A]) + alm_out_reg[10] <= 1; + else + alm_out_reg[10] <= 0; + end + if (chan_out_id_cur == 35) begin // VUSER 3 + if (data_written > dr_sram[8'h63] || data_written < dr_sram[8'h6B]) + alm_out_reg[11] <= 1; + else + alm_out_reg[11] <= 0; + end + end//rst_lock + end // always + + + always @(*) begin + ut_fault = ut_fault_reg & ot_en; + ut_warn = ut_warn_reg & alm_en[0]; + alm_ut[11:1] = alm_ut_reg[11:1] & alm_en[11:1]; + end + + always @( posedge DCLK_in or posedge sysmon_rst ) begin + if(sysmon_rst ==1 ) begin + ut_fault_reg <= 0; + ut_warn_reg <= 0; + alm_ut_reg <= 'd0; + end + else if (alm_asrt && avg_final_loop) begin + case (chan_out_id_cur) + 'd0: begin //temperature + ut_fault_reg <= (data_written < dr_sram[8'h57]) ? 1 : 0; + ut_warn_reg <= (data_written < dr_sram[8'h54]) ? 1 : 0; + end + 'd1: alm_ut_reg[1] <= (data_written < dr_sram[8'h55]) ? 1 : 0; // VCC INT + 'd2: alm_ut_reg[2] <= (data_written < dr_sram[8'h56]) ? 1 : 0; // VCCAUX + 'd6: alm_ut_reg[3] <= (data_written < dr_sram[8'h5C]) ? 1 : 0; // VCC BRAM + 'd13: alm_ut_reg[4] <= (data_written < dr_sram[8'h5D]) ? 1 : 0; // VCC PSINTLP + 'd14: alm_ut_reg[5] <= (data_written < dr_sram[8'h5E]) ? 1 : 0; // VCC PSINTFP + 'd15: alm_ut_reg[6] <= (data_written < dr_sram[8'h5F]) ? 1 : 0; // VCC PSAUX + 'd32: alm_ut_reg[8] <= (data_written < dr_sram[8'h68]) ? 1 : 0; // VUSER 0 + 'd33: alm_ut_reg[9] <= (data_written < dr_sram[8'h69]) ? 1 : 0; // VUSER 1 + 'd34: alm_ut_reg[10] <= (data_written < dr_sram[8'h6A]) ? 1 : 0; // VUSER 2 + 'd35: alm_ut_reg[11] <= (data_written < dr_sram[8'h6B]) ? 1 : 0; // VUSER 3 + default: ; //do nothing + endcase + end + end//always + + always @(*) begin + OT_out = ot_out_reg & ot_en; + + ALM_out[6:0] = alm_out_reg[6:0] & alm_en[6:0]; + ALM_out[7] = |ALM_out[6:0]; + ALM_out[11:8] = alm_out_reg[11:8] & alm_en[11:8]; + ALM_out[14:12] = 'd0; // Reserved + ALM_out[15] = (|ALM_out[11:8]) | (|ALM_out[6:0]); + end + + always @(posedge OT_out) begin + if(sysmon_rst==0 && ot_limit_reg[3:0]==4'b0011) + $display("Warning: [Unisim %s-25] OT is high and automatic shutdown in 53h has been enabled. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, $time/1000.0,); + end + + // end alarm + + //*** Timing_Checks_Start_here + +`ifdef XIL_TIMING + reg notifier; + + wire dclk_en_n; + wire dclk_en_p; + + assign dclk_en_n = IS_DCLK_INVERTED_BIN; + assign dclk_en_p = ~IS_DCLK_INVERTED_BIN; + + reg notifier_do; + + wire rst_en_n = ~RESET_in && dclk_en_n; + wire rst_en_p = ~RESET_in && dclk_en_p; + + always @(notifier) begin + alm_out_reg = 16'bx; + OT_out = 1'bx; + BUSY_out = 1'bx; + EOC_out = 1'bx; + EOS_out = 1'bx; + DRDY_out = 1'bx; + DO_out = 16'bx; + end + + always @(notifier_do) begin + DRDY_out = 1'bx; + DO_out = 16'bx; + end + + +`endif + + specify + (DCLK => ADC_DATA[0]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[10]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[11]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[12]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[13]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[14]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[15]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[1]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[2]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[3]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[4]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[5]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[6]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[7]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[8]) = (100:100:100, 100:100:100); + (DCLK => ADC_DATA[9]) = (100:100:100, 100:100:100); + (DCLK => ALM[0]) = (100:100:100, 100:100:100); + (DCLK => ALM[10]) = (100:100:100, 100:100:100); + (DCLK => ALM[11]) = (100:100:100, 100:100:100); + (DCLK => ALM[12]) = (100:100:100, 100:100:100); + (DCLK => ALM[13]) = (100:100:100, 100:100:100); + (DCLK => ALM[15]) = (100:100:100, 100:100:100); + (DCLK => ALM[1]) = (100:100:100, 100:100:100); + (DCLK => ALM[2]) = (100:100:100, 100:100:100); + (DCLK => ALM[3]) = (100:100:100, 100:100:100); + (DCLK => ALM[4]) = (100:100:100, 100:100:100); + (DCLK => ALM[5]) = (100:100:100, 100:100:100); + (DCLK => ALM[6]) = (100:100:100, 100:100:100); + (DCLK => ALM[7]) = (100:100:100, 100:100:100); + (DCLK => ALM[8]) = (100:100:100, 100:100:100); + (DCLK => ALM[9]) = (100:100:100, 100:100:100); + (DCLK => BUSY) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[0]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[1]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[2]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[3]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[4]) = (100:100:100, 100:100:100); + (DCLK => CHANNEL[5]) = (100:100:100, 100:100:100); + (DCLK => DO[0]) = (100:100:100, 100:100:100); + (DCLK => DO[10]) = (100:100:100, 100:100:100); + (DCLK => DO[11]) = (100:100:100, 100:100:100); + (DCLK => DO[12]) = (100:100:100, 100:100:100); + (DCLK => DO[13]) = (100:100:100, 100:100:100); + (DCLK => DO[14]) = (100:100:100, 100:100:100); + (DCLK => DO[15]) = (100:100:100, 100:100:100); + (DCLK => DO[1]) = (100:100:100, 100:100:100); + (DCLK => DO[2]) = (100:100:100, 100:100:100); + (DCLK => DO[3]) = (100:100:100, 100:100:100); + (DCLK => DO[4]) = (100:100:100, 100:100:100); + (DCLK => DO[5]) = (100:100:100, 100:100:100); + (DCLK => DO[6]) = (100:100:100, 100:100:100); + (DCLK => DO[7]) = (100:100:100, 100:100:100); + (DCLK => DO[8]) = (100:100:100, 100:100:100); + (DCLK => DO[9]) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => EOC) = (100:100:100, 100:100:100); + (DCLK => EOS) = (100:100:100, 100:100:100); + (DCLK => I2C_SCLK_TS) = (100:100:100, 100:100:100); + (DCLK => I2C_SDA_TS) = (100:100:100, 100:100:100); + (DCLK => JTAGBUSY) = (100:100:100, 100:100:100); + (DCLK => JTAGLOCKED) = (100:100:100, 100:100:100); + (DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[0]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[1]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[2]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[3]) = (100:100:100, 100:100:100); + (DCLK => MUXADDR[4]) = (100:100:100, 100:100:100); + (DCLK => OT) = (100:100:100, 100:100:100); + (DCLK => SMBALERT_TS) = (100:100:100, 100:100:100); + (RESET => BUSY) = (0:0:0, 0:0:0); + (posedge RESET => (ADC_DATA[0] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[10] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[11] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[12] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[13] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[14] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[15] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[1] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[2] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[3] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[4] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[5] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[6] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[7] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[8] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ADC_DATA[9] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[0] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[10] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[11] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[12] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[13] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[15] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[1] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[2] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[3] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[4] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[5] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[6] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[7] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[8] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (ALM[9] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[0] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[1] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[2] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[3] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[4] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (CHANNEL[5] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (EOC +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (EOS +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (MUXADDR[0] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (MUXADDR[1] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (MUXADDR[2] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (MUXADDR[3] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (MUXADDR[4] +: 0)) = (100:100:100, 100:100:100); + (posedge RESET => (OT +: 0)) = (100:100:100, 100:100:100); + `ifdef XIL_TIMING + $period (negedge CONVST, 0:0:0, notifier); + $period (negedge CONVSTCLK, 0:0:0, notifier); + $period (negedge DCLK, 0:0:0, notifier); + $period (posedge CONVST, 0:0:0, notifier); + $period (posedge CONVSTCLK, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $setuphold (negedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]); + $setuphold (negedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]); + $setuphold (negedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]); + $setuphold (negedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]); + $setuphold (negedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]); + $setuphold (negedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]); + $setuphold (negedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]); + $setuphold (negedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]); + $setuphold (negedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay); + $setuphold (negedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]); + $setuphold (negedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]); + $setuphold (negedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]); + $setuphold (negedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]); + $setuphold (negedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]); + $setuphold (negedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]); + $setuphold (negedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]); + $setuphold (negedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]); + $setuphold (negedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[2]); + $setuphold (negedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[3]); + $setuphold (negedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]); + $setuphold (negedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]); + $setuphold (negedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]); + $setuphold (negedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]); + $setuphold (negedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]); + $setuphold (negedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]); + $setuphold (negedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay); + $setuphold (negedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]); + $setuphold (negedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]); + $setuphold (negedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]); + $setuphold (negedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]); + $setuphold (negedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]); + $setuphold (negedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]); + $setuphold (negedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]); + $setuphold (negedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]); + $setuphold (negedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay); + $setuphold (negedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]); + $setuphold (negedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]); + $setuphold (negedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]); + $setuphold (negedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]); + $setuphold (negedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]); + $setuphold (negedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]); + $setuphold (negedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]); + $setuphold (negedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]); + $setuphold (negedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[2]); + $setuphold (negedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[3]); + $setuphold (negedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]); + $setuphold (negedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]); + $setuphold (negedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]); + $setuphold (negedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]); + $setuphold (negedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]); + $setuphold (negedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]); + $setuphold (negedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay); + $setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]); + $setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]); + $setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]); + $setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]); + $setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]); + $setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]); + $setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]); + $setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay); + $setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]); + $setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]); + $setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]); + $setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]); + $setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]); + $setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]); + $setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]); + $setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]); + $setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]); + $setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]); + $setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]); + $setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]); + $setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]); + $setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]); + $setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]); + $setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay); + $width (negedge CONVST, 0:0:0, 0, notifier); + $width (negedge CONVSTCLK, 0:0:0, 0, notifier); + $width (negedge DCLK, 0:0:0, 0, notifier); + $width (posedge CONVST, 0:0:0, 0, notifier); + $width (posedge CONVSTCLK, 0:0:0, 0, notifier); + $width (posedge DCLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; +endspecify + + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/TX_BITSLICE.v b/verilog/src/unisims/TX_BITSLICE.v new file mode 100644 index 0000000..c03bdf6 --- /dev/null +++ b/verilog/src/unisims/TX_BITSLICE.v @@ -0,0 +1,651 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / TX_BITSLICE +// /___/ /\ Filename : TX_BITSLICE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module TX_BITSLICE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DATA_WIDTH = 8, + parameter DELAY_FORMAT = "TIME", + parameter DELAY_TYPE = "FIXED", + parameter integer DELAY_VALUE = 0, + parameter ENABLE_PRE_EMPHASIS = "FALSE", + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter NATIVE_ODELAY_BYPASS = "FALSE", + parameter OUTPUT_PHASE_90 = "FALSE", + parameter real REFCLK_FREQUENCY = 300.0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter TBYTE_CTL = "TBYTE_IN", + parameter UPDATE_MODE = "ASYNC" +)( + output [8:0] CNTVALUEOUT, + output O, + output [39:0] RX_BIT_CTRL_OUT, + output [39:0] TX_BIT_CTRL_OUT, + output T_OUT, + + input CE, + input CLK, + input [8:0] CNTVALUEIN, + input [7:0] D, + input EN_VTC, + input INC, + input LOAD, + input RST, + input RST_DLY, + input [39:0] RX_BIT_CTRL_IN, + input T, + input TBYTE_IN, + input [39:0] TX_BIT_CTRL_IN +); + +// define constants + localparam MODULE_NAME = "TX_BITSLICE"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only + reg warning_flag = 1'b1; +`ifdef XIL_DR + `include "TX_BITSLICE_dr.v" +`else + localparam [31:0] DATA_WIDTH_REG = DATA_WIDTH; + localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT; + localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE; + localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE; + localparam [40:1] ENABLE_PRE_EMPHASIS_REG = ENABLE_PRE_EMPHASIS; + localparam [0:0] INIT_REG = INIT; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS; + localparam [40:1] OUTPUT_PHASE_90_REG = OUTPUT_PHASE_90; + localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL; + localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE; +`endif + + localparam [0:0] DC_ADJ_EN_REG = 1'b0; + localparam [2:0] FDLY_REG = 3'b010; + localparam [5:0] SPARE_REG = 6'b000000; + localparam [40:1] FIFO_ENABLE_REG = "TRUE"; + localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE"; + localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE"; + localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE"; + localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE"; + localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE"; + localparam [40:1] RX_DELAY_FORMAT_REG = "COUNT"; + localparam [112:1] RX_DATA_TYPE_REG = "DATA_AND_CLOCK"; + + + wire IS_CLK_INVERTED_BIN; + wire IS_RST_DLY_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire [63:0] REFCLK_FREQUENCY_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire O_out; + wire T_OUT_out; + wire [39:0] RX_BIT_CTRL_OUT_out; + wire [39:0] TX_BIT_CTRL_OUT_out; + wire [8:0] CNTVALUEOUT_out; + + wire O_delay; + wire T_OUT_delay; + wire [39:0] RX_BIT_CTRL_OUT_delay; + wire [39:0] TX_BIT_CTRL_OUT_delay; + wire [8:0] CNTVALUEOUT_delay; + + wire CE_in; + wire CLK_in; + wire EN_VTC_in; + wire FIFO_RD_CLK_in; + wire FIFO_RD_EN_in; + wire IFD_CE_in; + wire INC_in; + wire LOAD_in; + wire OFD_CE_in; + wire RST_DLY_in; + wire RST_in; + wire RX_CE_in; + wire RX_CLK_in; + wire RX_DATAIN1_in; + wire RX_EN_VTC_in; + wire RX_INC_in; + wire RX_LOAD_in; + wire RX_RESET_in; + wire RX_RST_in; + wire TBYTE_IN_in; + wire T_in; + wire [39:0] RX_BIT_CTRL_IN_in; + wire [39:0] TX_BIT_CTRL_IN_in; + wire [7:0] D_in; + wire [8:0] CNTVALUEIN_in; + wire [8:0] RX_CNTVALUEIN_in; + + wire CE_delay; + wire CLK_delay; + wire EN_VTC_delay; + wire INC_delay; + wire LOAD_delay; + wire RST_DLY_delay; + wire RST_delay; + wire TBYTE_IN_delay; + wire T_delay; + wire [39:0] RX_BIT_CTRL_IN_delay; + wire [39:0] TX_BIT_CTRL_IN_delay; + wire [7:0] D_delay; + wire [8:0] CNTVALUEIN_delay; + wire ODELAY_DATAIN0_out; + wire ODELAY_DATAOUT_out; + + assign #(out_delay) CNTVALUEOUT = (EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : CNTVALUEOUT_delay; + assign #(out_delay) O = O_delay; + assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay; + assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay; + assign #(out_delay) T_OUT = T_OUT_delay; + +`ifdef XIL_TIMING + reg notifier; +`endif + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLK_delay = CLK; + + assign #(in_delay) CE_delay = CE; + assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN; + assign #(in_delay) D_delay = D; + assign #(in_delay) INC_delay = INC; + assign #(in_delay) LOAD_delay = LOAD; + assign #(in_delay) TX_BIT_CTRL_IN_delay[25] = TX_BIT_CTRL_IN[25]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[26] = TX_BIT_CTRL_IN[26]; +`endif + +// inputs with no timing checks + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) RST_DLY_delay = RST_DLY; + assign #(in_delay) RST_delay = RST; + assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN; + assign #(in_delay) TBYTE_IN_delay = TBYTE_IN; + assign #(in_delay) TX_BIT_CTRL_IN_delay[0] = TX_BIT_CTRL_IN[0]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[1] = TX_BIT_CTRL_IN[1]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[2] = TX_BIT_CTRL_IN[2]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[3] = TX_BIT_CTRL_IN[3]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[4] = TX_BIT_CTRL_IN[4]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[5] = TX_BIT_CTRL_IN[5]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[6] = TX_BIT_CTRL_IN[6]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[7] = TX_BIT_CTRL_IN[7]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[8] = TX_BIT_CTRL_IN[8]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[9] = TX_BIT_CTRL_IN[9]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[10] = TX_BIT_CTRL_IN[10]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[11] = TX_BIT_CTRL_IN[11]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[12] = TX_BIT_CTRL_IN[12]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[13] = TX_BIT_CTRL_IN[13]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[14] = TX_BIT_CTRL_IN[14]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[15] = TX_BIT_CTRL_IN[15]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[16] = TX_BIT_CTRL_IN[16]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[17] = TX_BIT_CTRL_IN[17]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[18] = TX_BIT_CTRL_IN[18]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[19] = TX_BIT_CTRL_IN[19]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[20] = TX_BIT_CTRL_IN[20]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[21] = TX_BIT_CTRL_IN[21]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[22] = TX_BIT_CTRL_IN[22]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[23] = TX_BIT_CTRL_IN[23]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[24] = TX_BIT_CTRL_IN[24]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[27] = TX_BIT_CTRL_IN[27]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[28] = TX_BIT_CTRL_IN[28]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[29] = TX_BIT_CTRL_IN[29]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[30] = TX_BIT_CTRL_IN[30]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[31] = TX_BIT_CTRL_IN[31]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[32] = TX_BIT_CTRL_IN[32]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[33] = TX_BIT_CTRL_IN[33]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[34] = TX_BIT_CTRL_IN[34]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[35] = TX_BIT_CTRL_IN[35]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[36] = TX_BIT_CTRL_IN[36]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[37] = TX_BIT_CTRL_IN[37]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[38] = TX_BIT_CTRL_IN[38]; + assign #(in_delay) TX_BIT_CTRL_IN_delay[39] = TX_BIT_CTRL_IN[39]; + assign #(in_delay) T_delay = T; + + assign CNTVALUEOUT_delay = CNTVALUEOUT_out; + assign O_delay = O_out; + assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out; + assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out; + assign T_OUT_delay = T_OUT_out; + + assign CE_in = CE_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign CNTVALUEIN_in = CNTVALUEIN_delay; + assign D_in = D_delay; + assign EN_VTC_in = EN_VTC_delay; + assign INC_in = INC_delay; + assign LOAD_in = LOAD_delay; + assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN; + assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN; + assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay; + assign TBYTE_IN_in = TBYTE_IN_delay; + assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay; + assign T_in = T_delay; + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @(EN_VTC_in) begin + if (EN_VTC_in ===0 && DELAY_FORMAT_REG == "TIME" && warning_flag === 1'b1 ) begin + $display("Warning: [Unisim %s-1] BISC Calibration : DELAY_FORMAT set to TIME with EN_VTC signal set to 0. In hardware, when the EN_VTC signal is low during the initial calibration process, the BISC will never complete and the DLY_RDY and VTC_RDY status signals from the BITSLICE_CONTROL remain low. Simulation will not reflect this behavior. In simulation, the DLY_RDY and VTC_RDY from the BITSLICE_CONTROL will assert high. You should ensure the EN_VTC signal is held high during initial BISC self calibration to ensure BISC completes in hardware. See Select IO Userguide UG571 for more information.Instance: %m", MODULE_NAME); + warning_flag = 1'b0; + end + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DATA_WIDTH_REG != 8) && + (DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_FORMAT_REG != "TIME") && + (DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-103] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_TYPE_REG != "FIXED") && + (DELAY_TYPE_REG != "VAR_LOAD") && + (DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-104] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + + + if ((attr_test == 1'b1) || + ((ENABLE_PRE_EMPHASIS_REG != "FALSE") && + (ENABLE_PRE_EMPHASIS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] ENABLE_PRE_EMPHASIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENABLE_PRE_EMPHASIS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((NATIVE_ODELAY_BYPASS_REG != "FALSE") && + (NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OUTPUT_PHASE_90_REG != "FALSE") && + (OUTPUT_PHASE_90_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OUTPUT_PHASE_90_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-114] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-114] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-117] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-118] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((TBYTE_CTL_REG != "TBYTE_IN") && + (TBYTE_CTL_REG != "T"))) begin + $display("Error: [Unisim %s-119] TBYTE_CTL attribute is set to %s. Legal values for this attribute are TBYTE_IN or T. Instance: %m", MODULE_NAME, TBYTE_CTL_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_REG != "ASYNC") && + (UPDATE_MODE_REG != "MANUAL") && + (UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-122] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + assign RX_CLK_in = 1'b1; // tie off + + assign FIFO_RD_CLK_in = 1'b0; // tie off + assign FIFO_RD_EN_in = 1'b0; // tie off + assign IFD_CE_in = 1'b0; // tie off + assign OFD_CE_in = 1'b0; // tie off + assign RX_CE_in = 1'b0; // tie off + assign RX_CNTVALUEIN_in = 9'b000000000; // tie off + assign RX_DATAIN1_in = 1'b0; // tie off + assign RX_EN_VTC_in = 1'b1; // tie off + assign RX_INC_in = 1'b0; // tie off + assign RX_LOAD_in = 1'b0; // tie off + assign RX_RESET_in = 1'b0; // tie off + assign RX_RST_in = 1'b0; // tie off + +generate +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_TX_BITSLICE_D1 SIP_TX_BITSLICE_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG), + .FIFO_ENABLE (FIFO_ENABLE_REG), + .SPARE (SPARE_REG), + .FDLY (FDLY_REG), + .INIT (INIT_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .RX_DATA_TYPE (RX_DATA_TYPE_REG), + .RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .TBYTE_CTL (TBYTE_CTL_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .UPDATE_MODE (UPDATE_MODE_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .CNTVALUEOUT (CNTVALUEOUT_out), + .O (O_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .T_OUT (T_OUT_out), + .CE (CE_in), + .CLK (CLK_in), + .CNTVALUEIN (CNTVALUEIN_in), + .D (D_in), + .EN_VTC (EN_VTC_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .INC (INC_in), + .LOAD (LOAD_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_CE (RX_CE_in), + .RX_CLK (RX_CLK_in), + .RX_CNTVALUEIN (RX_CNTVALUEIN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .RX_EN_VTC (RX_EN_VTC_in), + .RX_INC (RX_INC_in), + .RX_LOAD (RX_LOAD_in), + .RX_RESET (RX_RESET_in), + .RX_RST (RX_RST_in), + .T (T_in), + .TBYTE_IN (TBYTE_IN_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out), + .SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out), + .GSR (glblGSR) + ); +end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + SIP_TX_BITSLICE_K2 SIP_TX_BITSLICE_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG), + .FDLY (FDLY_REG), + .INIT (INIT_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .RX_DATA_TYPE (RX_DATA_TYPE_REG), + .RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG), + .RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG), + .RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG), + .SIM_VERSION (SIM_VERSION_BIN), + .TBYTE_CTL (TBYTE_CTL_REG), + .TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG), + .TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG), + .UPDATE_MODE (UPDATE_MODE_REG), + .XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG), + .CNTVALUEOUT (CNTVALUEOUT_out), + .O (O_out), + .RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out), + .TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out), + .T_OUT (T_OUT_out), + .CE (CE_in), + .CLK (CLK_in), + .CNTVALUEIN (CNTVALUEIN_in), + .D (D_in), + .EN_VTC (EN_VTC_in), + .FIFO_RD_CLK (FIFO_RD_CLK_in), + .FIFO_RD_EN (FIFO_RD_EN_in), + .IFD_CE (IFD_CE_in), + .INC (INC_in), + .LOAD (LOAD_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in), + .RX_CE (RX_CE_in), + .RX_CLK (RX_CLK_in), + .RX_CNTVALUEIN (RX_CNTVALUEIN_in), + .RX_DATAIN1 (RX_DATAIN1_in), + .RX_EN_VTC (RX_EN_VTC_in), + .RX_INC (RX_INC_in), + .RX_LOAD (RX_LOAD_in), + .RX_RESET (RX_RESET_in), + .RX_RST (RX_RST_in), + .T (T_in), + .TBYTE_IN (TBYTE_IN_in), + .TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in), + .SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out), + .SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out), + .GSR (glblGSR) + ); +end +endgenerate + +`ifdef XIL_TIMING + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; +`endif + + specify + (CLK => CNTVALUEOUT[0]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[1]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[2]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[3]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[4]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[5]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[6]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[7]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[8]) = (100:100:100, 100:100:100); + (D[0] => O) = (0:0:0, 0:0:0); + (D[1] => T_OUT) = (0:0:0, 0:0:0); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (negedge TX_BIT_CTRL_IN[25], 0:0:0, notifier); + $period (negedge TX_BIT_CTRL_IN[26], 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $period (posedge TX_BIT_CTRL_IN[25], 0:0:0, notifier); + $period (posedge TX_BIT_CTRL_IN[26], 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (negedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (negedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (negedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (negedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (negedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (negedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (negedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (negedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (negedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (negedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (negedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (negedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (negedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (negedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (negedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (negedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]); + $setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]); + $setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (posedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (posedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (posedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (posedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (posedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (posedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (posedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (posedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (posedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (posedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (posedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (posedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (posedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (posedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (posedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (posedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]); + $setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]); + $setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier); + $width (negedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier); + $width (posedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/TX_BITSLICE_TRI.v b/verilog/src/unisims/TX_BITSLICE_TRI.v new file mode 100644 index 0000000..6f7fde8 --- /dev/null +++ b/verilog/src/unisims/TX_BITSLICE_TRI.v @@ -0,0 +1,438 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2016 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2016.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / TX_BITSLICE_TRI +// /___/ /\ Filename : TX_BITSLICE_TRI.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module TX_BITSLICE_TRI #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer DATA_WIDTH = 8, + parameter DELAY_FORMAT = "TIME", + parameter DELAY_TYPE = "FIXED", + parameter integer DELAY_VALUE = 0, + parameter [0:0] INIT = 1'b1, + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter NATIVE_ODELAY_BYPASS = "FALSE", + parameter OUTPUT_PHASE_90 = "FALSE", + parameter real REFCLK_FREQUENCY = 300.0, + parameter SIM_DEVICE = "ULTRASCALE", + parameter real SIM_VERSION = 2.0, + parameter UPDATE_MODE = "ASYNC" +)( + output [39:0] BIT_CTRL_OUT, + output [8:0] CNTVALUEOUT, + output TRI_OUT, + + input [39:0] BIT_CTRL_IN, + input CE, + input CLK, + input [8:0] CNTVALUEIN, + input EN_VTC, + input INC, + input LOAD, + input RST, + input RST_DLY +); + +// define constants + localparam MODULE_NAME = "TX_BITSLICE_TRI"; + localparam in_delay = 0; + localparam out_delay = 0; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "TX_BITSLICE_TRI_dr.v" +`else + localparam [31:0] DATA_WIDTH_REG = DATA_WIDTH; + localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT; + localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE; + localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE; + localparam [0:0] INIT_REG = INIT; + localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED; + localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; + localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS; + localparam [40:1] OUTPUT_PHASE_90_REG = OUTPUT_PHASE_90; + localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY; + localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE; + localparam real SIM_VERSION_REG = SIM_VERSION; + localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE; +`endif + + localparam [0:0] DC_ADJ_EN_REG = 1'b0; + localparam [2:0] FDLY_REG = 3'b010; + localparam [2:0] SPARE_REG = 3'b000; + + wire IS_CLK_INVERTED_BIN; + wire IS_RST_DLY_INVERTED_BIN; + wire IS_RST_INVERTED_BIN; + wire [63:0] REFCLK_FREQUENCY_BIN; + wire [63:0] SIM_VERSION_BIN; + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + + wire CDATAOUT_out; + wire TRI_OUT_out; + wire [39:0] BIT_CTRL_OUT_out; + wire [8:0] CNTVALUEOUT_out; + + wire TRI_OUT_delay; + wire [39:0] BIT_CTRL_OUT_delay; + wire [8:0] CNTVALUEOUT_delay; + + wire CDATAIN0_in; + wire CDATAIN1_in; + wire CE_in; + wire CLK_in; + wire EN_VTC_in; + wire INC_in; + wire LOAD_in; + wire OFD_CE_in; + wire RST_DLY_in; + wire RST_in; + wire [39:0] BIT_CTRL_IN_in; + wire [8:0] CNTVALUEIN_in; + + wire CE_delay; + wire CLK_delay; + wire EN_VTC_delay; + wire INC_delay; + wire LOAD_delay; + wire RST_DLY_delay; + wire RST_delay; + wire [39:0] BIT_CTRL_IN_delay; + wire [8:0] CNTVALUEIN_delay; + + assign #(out_delay) BIT_CTRL_OUT = BIT_CTRL_OUT_delay; + assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay; + assign #(out_delay) TRI_OUT = TRI_OUT_delay; + +`ifndef XIL_TIMING // inputs with timing checks + assign #(inclk_delay) CLK_delay = CLK; + + assign #(in_delay) CE_delay = CE; + assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN; + assign #(in_delay) INC_delay = INC; + assign #(in_delay) LOAD_delay = LOAD; +`endif + +// inputs with no timing checks + assign #(in_delay) BIT_CTRL_IN_delay = BIT_CTRL_IN; + assign #(in_delay) EN_VTC_delay = EN_VTC; + assign #(in_delay) RST_DLY_delay = RST_DLY; + assign #(in_delay) RST_delay = RST; + + assign BIT_CTRL_OUT_delay = BIT_CTRL_OUT_out; + assign CNTVALUEOUT_delay = CNTVALUEOUT_out; + assign TRI_OUT_delay = TRI_OUT_out; + + assign BIT_CTRL_IN_in = BIT_CTRL_IN_delay; + assign CE_in = CE_delay; + assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN; + assign CNTVALUEIN_in = CNTVALUEIN_delay; + assign EN_VTC_in = EN_VTC_delay; + assign INC_in = INC_delay; + assign LOAD_in = LOAD_delay; + assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN; + assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN; + + + assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG; + + assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG; + + assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; + + assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000; + + assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000; + + initial begin + #1; + trig_attr = ~trig_attr; + end + + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((DATA_WIDTH_REG != 8) && + (DATA_WIDTH_REG != 4))) begin + $display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_FORMAT_REG != "TIME") && + (DELAY_FORMAT_REG != "COUNT"))) begin + $display("Error: [Unisim %s-103] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DELAY_TYPE_REG != "FIXED") && + (DELAY_TYPE_REG != "VAR_LOAD") && + (DELAY_TYPE_REG != "VARIABLE"))) begin + $display("Error: [Unisim %s-104] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin + $display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + ((NATIVE_ODELAY_BYPASS_REG != "FALSE") && + (NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OUTPUT_PHASE_90_REG != "FALSE") && + (OUTPUT_PHASE_90_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OUTPUT_PHASE_90_REG); + attr_err = 1'b1; + end + + + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin + $display("Error: [Unisim %s-113] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + if ((attr_test == 1'b1) || + (DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin + $display("Error: [Unisim %s-113] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_DEVICE_REG != "ULTRASCALE") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") && + (SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin + $display("Error: [Unisim %s-114] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((SIM_VERSION_REG != 2.0) && + (SIM_VERSION_REG != 1.0))) begin + $display("Error: [Unisim %s-115] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((UPDATE_MODE_REG != "ASYNC") && + (UPDATE_MODE_REG != "MANUAL") && + (UPDATE_MODE_REG != "SYNC"))) begin + $display("Error: [Unisim %s-116] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end + + + assign CDATAIN0_in = 1'b1; // tie off + assign CDATAIN1_in = 1'b1; // tie off + assign OFD_CE_in = 1'b0; // tie off + +generate + +if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1 + SIP_TX_BITSLICE_TRI_D1 SIP_TX_BITSLICE_TRI_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .FDLY (FDLY_REG), + .SPARE (SPARE_REG), + .INIT (INIT_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .UPDATE_MODE (UPDATE_MODE_REG), + .BIT_CTRL_OUT (BIT_CTRL_OUT_out), + .CDATAOUT (CDATAOUT_out), + .CNTVALUEOUT (CNTVALUEOUT_out), + .TRI_OUT (TRI_OUT_out), + .BIT_CTRL_IN (BIT_CTRL_IN_in), + .CDATAIN0 (CDATAIN0_in), + .CDATAIN1 (CDATAIN1_in), + .CE (CE_in), + .CLK (CLK_in), + .CNTVALUEIN (CNTVALUEIN_in), + .EN_VTC (EN_VTC_in), + .INC (INC_in), + .LOAD (LOAD_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .GSR (glblGSR) + ); +end +else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1 + SIP_TX_BITSLICE_TRI_K2 SIP_TX_BITSLICE_TRI_INST ( + .DATA_WIDTH (DATA_WIDTH_REG), + .DC_ADJ_EN (DC_ADJ_EN_REG), + .DELAY_FORMAT (DELAY_FORMAT_REG), + .DELAY_TYPE (DELAY_TYPE_REG), + .DELAY_VALUE (DELAY_VALUE_REG), + .FDLY (FDLY_REG), + .INIT (INIT_REG), + .NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG), + .OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN), + .SIM_VERSION (SIM_VERSION_BIN), + .UPDATE_MODE (UPDATE_MODE_REG), + .BIT_CTRL_OUT (BIT_CTRL_OUT_out), + .CDATAOUT (CDATAOUT_out), + .CNTVALUEOUT (CNTVALUEOUT_out), + .TRI_OUT (TRI_OUT_out), + .BIT_CTRL_IN (BIT_CTRL_IN_in), + .CDATAIN0 (CDATAIN0_in), + .CDATAIN1 (CDATAIN1_in), + .CE (CE_in), + .CLK (CLK_in), + .CNTVALUEIN (CNTVALUEIN_in), + .EN_VTC (EN_VTC_in), + .INC (INC_in), + .LOAD (LOAD_in), + .OFD_CE (OFD_CE_in), + .RST (RST_in), + .RST_DLY (RST_DLY_in), + .GSR (glblGSR) + ); +end +endgenerate + +`ifdef XIL_TIMING + reg notifier; + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_BIN; + assign clk_en_p = ~IS_CLK_INVERTED_BIN; +`endif + + specify + (CLK => CNTVALUEOUT[0]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[1]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[2]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[3]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[4]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[5]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[6]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[7]) = (100:100:100, 100:100:100); + (CLK => CNTVALUEOUT[8]) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (negedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (negedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (negedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (negedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (negedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (negedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (negedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (negedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay); + $setuphold (negedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (negedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (negedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (negedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (negedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (negedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (negedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (negedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (negedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay); + $setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (posedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (posedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (posedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (posedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (posedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (posedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (posedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (posedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay); + $setuphold (posedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]); + $setuphold (posedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]); + $setuphold (posedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]); + $setuphold (posedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]); + $setuphold (posedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]); + $setuphold (posedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]); + $setuphold (posedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]); + $setuphold (posedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]); + $setuphold (posedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]); + $setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay); + $setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/URAM288.v b/verilog/src/unisims/URAM288.v new file mode 100644 index 0000000..1ed5dc4 --- /dev/null +++ b/verilog/src/unisims/URAM288.v @@ -0,0 +1,3938 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 288K-bit High-Density Memory Building Block +// /___/ /\ Filename : URAM288.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/31/2014 - Initial functional version +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module URAM288 #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer AUTO_SLEEP_LATENCY = 8, + parameter integer AVG_CONS_INACTIVE_CYCLES = 10, + parameter BWE_MODE_A = "PARITY_INTERLEAVED", + parameter BWE_MODE_B = "PARITY_INTERLEAVED", + parameter CASCADE_ORDER_A = "NONE", + parameter CASCADE_ORDER_B = "NONE", + parameter EN_AUTO_SLEEP_MODE = "FALSE", + parameter EN_ECC_RD_A = "FALSE", + parameter EN_ECC_RD_B = "FALSE", + parameter EN_ECC_WR_A = "FALSE", + parameter EN_ECC_WR_B = "FALSE", + parameter IREG_PRE_A = "FALSE", + parameter IREG_PRE_B = "FALSE", + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_EN_A_INVERTED = 1'b0, + parameter [0:0] IS_EN_B_INVERTED = 1'b0, + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0, + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0, + parameter [0:0] IS_RST_A_INVERTED = 1'b0, + parameter [0:0] IS_RST_B_INVERTED = 1'b0, + parameter MATRIX_ID = "NONE", + parameter integer NUM_UNIQUE_SELF_ADDR_A = 1, + parameter integer NUM_UNIQUE_SELF_ADDR_B = 1, + parameter integer NUM_URAM_IN_MATRIX = 1, + parameter OREG_A = "FALSE", + parameter OREG_B = "FALSE", + parameter OREG_ECC_A = "FALSE", + parameter OREG_ECC_B = "FALSE", + parameter REG_CAS_A = "FALSE", + parameter REG_CAS_B = "FALSE", + parameter RST_MODE_A = "SYNC", + parameter RST_MODE_B = "SYNC", + parameter [10:0] SELF_ADDR_A = 11'h000, + parameter [10:0] SELF_ADDR_B = 11'h000, + parameter [10:0] SELF_MASK_A = 11'h7FF, + parameter [10:0] SELF_MASK_B = 11'h7FF, + parameter USE_EXT_CE_A = "FALSE", + parameter USE_EXT_CE_B = "FALSE" +)( + output [22:0] CAS_OUT_ADDR_A, + output [22:0] CAS_OUT_ADDR_B, + output [8:0] CAS_OUT_BWE_A, + output [8:0] CAS_OUT_BWE_B, + output CAS_OUT_DBITERR_A, + output CAS_OUT_DBITERR_B, + output [71:0] CAS_OUT_DIN_A, + output [71:0] CAS_OUT_DIN_B, + output [71:0] CAS_OUT_DOUT_A, + output [71:0] CAS_OUT_DOUT_B, + output CAS_OUT_EN_A, + output CAS_OUT_EN_B, + output CAS_OUT_RDACCESS_A, + output CAS_OUT_RDACCESS_B, + output CAS_OUT_RDB_WR_A, + output CAS_OUT_RDB_WR_B, + output CAS_OUT_SBITERR_A, + output CAS_OUT_SBITERR_B, + output DBITERR_A, + output DBITERR_B, + output [71:0] DOUT_A, + output [71:0] DOUT_B, + output RDACCESS_A, + output RDACCESS_B, + output SBITERR_A, + output SBITERR_B, + + input [22:0] ADDR_A, + input [22:0] ADDR_B, + input [8:0] BWE_A, + input [8:0] BWE_B, + input [22:0] CAS_IN_ADDR_A, + input [22:0] CAS_IN_ADDR_B, + input [8:0] CAS_IN_BWE_A, + input [8:0] CAS_IN_BWE_B, + input CAS_IN_DBITERR_A, + input CAS_IN_DBITERR_B, + input [71:0] CAS_IN_DIN_A, + input [71:0] CAS_IN_DIN_B, + input [71:0] CAS_IN_DOUT_A, + input [71:0] CAS_IN_DOUT_B, + input CAS_IN_EN_A, + input CAS_IN_EN_B, + input CAS_IN_RDACCESS_A, + input CAS_IN_RDACCESS_B, + input CAS_IN_RDB_WR_A, + input CAS_IN_RDB_WR_B, + input CAS_IN_SBITERR_A, + input CAS_IN_SBITERR_B, + input CLK, + input [71:0] DIN_A, + input [71:0] DIN_B, + input EN_A, + input EN_B, + input INJECT_DBITERR_A, + input INJECT_DBITERR_B, + input INJECT_SBITERR_A, + input INJECT_SBITERR_B, + input OREG_CE_A, + input OREG_CE_B, + input OREG_ECC_CE_A, + input OREG_ECC_CE_B, + input RDB_WR_A, + input RDB_WR_B, + input RST_A, + input RST_B, + input SLEEP +); + +// define constants + localparam MODULE_NAME = "URAM288"; + +// Parameter encodings and registers + localparam BWE_MODE_A_PARITY_INDEPENDENT = 1; + localparam BWE_MODE_A_PARITY_INTERLEAVED = 0; + localparam BWE_MODE_B_PARITY_INDEPENDENT = 1; + localparam BWE_MODE_B_PARITY_INTERLEAVED = 0; + localparam CASCADE_ORDER_A_FIRST = 1; + localparam CASCADE_ORDER_A_LAST = 2; + localparam CASCADE_ORDER_A_MIDDLE = 3; + localparam CASCADE_ORDER_A_NONE = 0; + localparam CASCADE_ORDER_B_FIRST = 1; + localparam CASCADE_ORDER_B_LAST = 2; + localparam CASCADE_ORDER_B_MIDDLE = 3; + localparam CASCADE_ORDER_B_NONE = 0; + localparam EN_AUTO_SLEEP_MODE_FALSE = 0; + localparam EN_AUTO_SLEEP_MODE_TRUE = 1; + localparam EN_ECC_RD_A_FALSE = 0; + localparam EN_ECC_RD_A_TRUE = 1; + localparam EN_ECC_RD_B_FALSE = 0; + localparam EN_ECC_RD_B_TRUE = 1; + localparam EN_ECC_WR_A_FALSE = 0; + localparam EN_ECC_WR_A_TRUE = 1; + localparam EN_ECC_WR_B_FALSE = 0; + localparam EN_ECC_WR_B_TRUE = 1; + localparam IREG_PRE_A_FALSE = 0; + localparam IREG_PRE_A_TRUE = 1; + localparam IREG_PRE_B_FALSE = 0; + localparam IREG_PRE_B_TRUE = 1; + localparam OREG_A_FALSE = 0; + localparam OREG_A_TRUE = 1; + localparam OREG_B_FALSE = 0; + localparam OREG_B_TRUE = 1; + localparam OREG_ECC_A_FALSE = 0; + localparam OREG_ECC_A_TRUE = 1; + localparam OREG_ECC_B_FALSE = 0; + localparam OREG_ECC_B_TRUE = 1; + localparam REG_CAS_A_FALSE = 0; + localparam REG_CAS_A_TRUE = 1; + localparam REG_CAS_B_FALSE = 0; + localparam REG_CAS_B_TRUE = 1; + localparam RST_MODE_A_ASYNC = 1; + localparam RST_MODE_A_SYNC = 0; + localparam RST_MODE_B_ASYNC = 1; + localparam RST_MODE_B_SYNC = 0; + localparam USE_EXT_CE_A_FALSE = 0; + localparam USE_EXT_CE_A_TRUE = 1; + localparam USE_EXT_CE_B_FALSE = 0; + localparam USE_EXT_CE_B_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "URAM288_dr.v" +`else + reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY; + reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES; + reg [144:1] BWE_MODE_A_REG = BWE_MODE_A; + reg [144:1] BWE_MODE_B_REG = BWE_MODE_B; + reg [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A; + reg [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B; + reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE; + reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A; + reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B; + reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A; + reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B; + reg [40:1] IREG_PRE_A_REG = IREG_PRE_A; + reg [40:1] IREG_PRE_B_REG = IREG_PRE_B; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED; + reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED; + reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED; + reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED; + reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED; + reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED; + reg [32:1] MATRIX_ID_REG = MATRIX_ID; + reg [31:0] NUM_UNIQUE_SELF_ADDR_A_REG = NUM_UNIQUE_SELF_ADDR_A; + reg [31:0] NUM_UNIQUE_SELF_ADDR_B_REG = NUM_UNIQUE_SELF_ADDR_B; + reg [31:0] NUM_URAM_IN_MATRIX_REG = NUM_URAM_IN_MATRIX; + reg [40:1] OREG_A_REG = OREG_A; + reg [40:1] OREG_B_REG = OREG_B; + reg [40:1] OREG_ECC_A_REG = OREG_ECC_A; + reg [40:1] OREG_ECC_B_REG = OREG_ECC_B; + reg [40:1] REG_CAS_A_REG = REG_CAS_A; + reg [40:1] REG_CAS_B_REG = REG_CAS_B; + reg [40:1] RST_MODE_A_REG = RST_MODE_A; + reg [40:1] RST_MODE_B_REG = RST_MODE_B; + reg [10:0] SELF_ADDR_A_REG = SELF_ADDR_A; + reg [10:0] SELF_ADDR_B_REG = SELF_ADDR_B; + reg [10:0] SELF_MASK_A_REG = SELF_MASK_A; + reg [10:0] SELF_MASK_B_REG = SELF_MASK_B; + reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A; + reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B; +`endif + +`ifdef XIL_XECLIB + wire [3:0] AUTO_SLEEP_LATENCY_BIN; + wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; + wire BWE_MODE_A_BIN; + wire BWE_MODE_B_BIN; + wire [1:0] CASCADE_ORDER_A_BIN; + wire [1:0] CASCADE_ORDER_B_BIN; + wire EN_AUTO_SLEEP_MODE_BIN; + wire EN_ECC_RD_A_BIN; + wire EN_ECC_RD_B_BIN; + wire EN_ECC_WR_A_BIN; + wire EN_ECC_WR_B_BIN; + wire IREG_PRE_A_BIN; + wire IREG_PRE_B_BIN; + wire [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN; + wire [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN; + wire [11:0] NUM_URAM_IN_MATRIX_BIN; + wire OREG_A_BIN; + wire OREG_B_BIN; + wire OREG_ECC_A_BIN; + wire OREG_ECC_B_BIN; + wire REG_CAS_A_BIN; + wire REG_CAS_B_BIN; + wire RST_MODE_A_BIN; + wire RST_MODE_B_BIN; + wire USE_EXT_CE_A_BIN; + wire USE_EXT_CE_B_BIN; +`else + reg [3:0] AUTO_SLEEP_LATENCY_BIN; + reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; + reg BWE_MODE_A_BIN; + reg BWE_MODE_B_BIN; + reg [1:0] CASCADE_ORDER_A_BIN; + reg [1:0] CASCADE_ORDER_B_BIN; + reg EN_AUTO_SLEEP_MODE_BIN; + reg EN_ECC_RD_A_BIN; + reg EN_ECC_RD_B_BIN; + reg EN_ECC_WR_A_BIN; + reg EN_ECC_WR_B_BIN; + reg IREG_PRE_A_BIN; + reg IREG_PRE_B_BIN; + reg [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN; + reg [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN; + reg [11:0] NUM_URAM_IN_MATRIX_BIN; + reg OREG_A_BIN; + reg OREG_B_BIN; + reg OREG_ECC_A_BIN; + reg OREG_ECC_B_BIN; + reg REG_CAS_A_BIN; + reg REG_CAS_B_BIN; + reg RST_MODE_A_BIN; + reg RST_MODE_B_BIN; + reg USE_EXT_CE_A_BIN; + reg USE_EXT_CE_B_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CAS_IN_DBITERR_A_in; + wire CAS_IN_DBITERR_B_in; + wire CAS_IN_EN_A_in; + wire CAS_IN_EN_B_in; + wire CAS_IN_RDACCESS_A_in; + wire CAS_IN_RDACCESS_B_in; + wire CAS_IN_RDB_WR_A_in; + wire CAS_IN_RDB_WR_B_in; + wire CAS_IN_SBITERR_A_in; + wire CAS_IN_SBITERR_B_in; + wire CLK_in; + wire EN_A_in; + wire EN_B_in; + wire INJECT_DBITERR_A_in; + wire INJECT_DBITERR_B_in; + wire INJECT_SBITERR_A_in; + wire INJECT_SBITERR_B_in; + wire OREG_CE_A_in; + wire OREG_CE_B_in; + wire OREG_ECC_CE_A_in; + wire OREG_ECC_CE_B_in; + wire RDB_WR_A_in; + wire RDB_WR_B_in; + wire RST_A_in; + wire RST_B_in; + wire SLEEP_in; + wire [22:0] ADDR_A_in; + wire [22:0] ADDR_B_in; + wire [22:0] CAS_IN_ADDR_A_in; + wire [22:0] CAS_IN_ADDR_B_in; + wire [71:0] CAS_IN_DIN_A_in; + wire [71:0] CAS_IN_DIN_B_in; + wire [71:0] CAS_IN_DOUT_A_in; + wire [71:0] CAS_IN_DOUT_B_in; + wire [71:0] DIN_A_in; + wire [71:0] DIN_B_in; + wire [8:0] BWE_A_in; + wire [8:0] BWE_B_in; + wire [8:0] CAS_IN_BWE_A_in; + wire [8:0] CAS_IN_BWE_B_in; + +`ifdef XIL_TIMING + wire CAS_IN_DBITERR_A_delay; + wire CAS_IN_DBITERR_B_delay; + wire CAS_IN_EN_A_delay; + wire CAS_IN_EN_B_delay; + wire CAS_IN_RDACCESS_A_delay; + wire CAS_IN_RDACCESS_B_delay; + wire CAS_IN_RDB_WR_A_delay; + wire CAS_IN_RDB_WR_B_delay; + wire CAS_IN_SBITERR_A_delay; + wire CAS_IN_SBITERR_B_delay; + wire CLK_delay; + wire EN_A_delay; + wire EN_B_delay; + wire INJECT_DBITERR_A_delay; + wire INJECT_DBITERR_B_delay; + wire INJECT_SBITERR_A_delay; + wire INJECT_SBITERR_B_delay; + wire OREG_CE_A_delay; + wire OREG_CE_B_delay; + wire OREG_ECC_CE_A_delay; + wire OREG_ECC_CE_B_delay; + wire RDB_WR_A_delay; + wire RDB_WR_B_delay; + wire RST_A_delay; + wire RST_B_delay; + wire SLEEP_delay; + wire [22:0] ADDR_A_delay; + wire [22:0] ADDR_B_delay; + wire [22:0] CAS_IN_ADDR_A_delay; + wire [22:0] CAS_IN_ADDR_B_delay; + wire [71:0] CAS_IN_DIN_A_delay; + wire [71:0] CAS_IN_DIN_B_delay; + wire [71:0] CAS_IN_DOUT_A_delay; + wire [71:0] CAS_IN_DOUT_B_delay; + wire [71:0] DIN_A_delay; + wire [71:0] DIN_B_delay; + wire [8:0] BWE_A_delay; + wire [8:0] BWE_B_delay; + wire [8:0] CAS_IN_BWE_A_delay; + wire [8:0] CAS_IN_BWE_B_delay; +`endif + +`ifdef XIL_TIMING + assign ADDR_A_in = ADDR_A_delay; + assign ADDR_B_in = ADDR_B_delay; + assign BWE_A_in = BWE_A_delay; + assign BWE_B_in = BWE_B_delay; + assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A_delay[0]; // rv 0 + assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A_delay[10]; // rv 0 + assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A_delay[11]; // rv 0 + assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A_delay[12]; // rv 0 + assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A_delay[13]; // rv 0 + assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A_delay[14]; // rv 0 + assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A_delay[15]; // rv 0 + assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A_delay[16]; // rv 0 + assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A_delay[17]; // rv 0 + assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A_delay[18]; // rv 0 + assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A_delay[19]; // rv 0 + assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A_delay[1]; // rv 0 + assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A_delay[20]; // rv 0 + assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A_delay[21]; // rv 0 + assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A_delay[22]; // rv 0 + assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A_delay[2]; // rv 0 + assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A_delay[3]; // rv 0 + assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A_delay[4]; // rv 0 + assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A_delay[5]; // rv 0 + assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A_delay[6]; // rv 0 + assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A_delay[7]; // rv 0 + assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A_delay[8]; // rv 0 + assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A_delay[9]; // rv 0 + assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B_delay[0]; // rv 0 + assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B_delay[10]; // rv 0 + assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B_delay[11]; // rv 0 + assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B_delay[12]; // rv 0 + assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B_delay[13]; // rv 0 + assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B_delay[14]; // rv 0 + assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B_delay[15]; // rv 0 + assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B_delay[16]; // rv 0 + assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B_delay[17]; // rv 0 + assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B_delay[18]; // rv 0 + assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B_delay[19]; // rv 0 + assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B_delay[1]; // rv 0 + assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B_delay[20]; // rv 0 + assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B_delay[21]; // rv 0 + assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B_delay[22]; // rv 0 + assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B_delay[2]; // rv 0 + assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B_delay[3]; // rv 0 + assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B_delay[4]; // rv 0 + assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B_delay[5]; // rv 0 + assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B_delay[6]; // rv 0 + assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B_delay[7]; // rv 0 + assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B_delay[8]; // rv 0 + assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B_delay[9]; // rv 0 + assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A_delay[0]; // rv 0 + assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A_delay[1]; // rv 0 + assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A_delay[2]; // rv 0 + assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A_delay[3]; // rv 0 + assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A_delay[4]; // rv 0 + assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A_delay[5]; // rv 0 + assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A_delay[6]; // rv 0 + assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A_delay[7]; // rv 0 + assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A_delay[8]; // rv 0 + assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B_delay[0]; // rv 0 + assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B_delay[1]; // rv 0 + assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B_delay[2]; // rv 0 + assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B_delay[3]; // rv 0 + assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B_delay[4]; // rv 0 + assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B_delay[5]; // rv 0 + assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B_delay[6]; // rv 0 + assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B_delay[7]; // rv 0 + assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B_delay[8]; // rv 0 + assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A_delay; // rv 0 + assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B_delay; // rv 0 + assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A_delay[0]; // rv 0 + assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A_delay[10]; // rv 0 + assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A_delay[11]; // rv 0 + assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A_delay[12]; // rv 0 + assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A_delay[13]; // rv 0 + assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A_delay[14]; // rv 0 + assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A_delay[15]; // rv 0 + assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A_delay[16]; // rv 0 + assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A_delay[17]; // rv 0 + assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A_delay[18]; // rv 0 + assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A_delay[19]; // rv 0 + assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A_delay[1]; // rv 0 + assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A_delay[20]; // rv 0 + assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A_delay[21]; // rv 0 + assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A_delay[22]; // rv 0 + assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A_delay[23]; // rv 0 + assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A_delay[24]; // rv 0 + assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A_delay[25]; // rv 0 + assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A_delay[26]; // rv 0 + assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A_delay[27]; // rv 0 + assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A_delay[28]; // rv 0 + assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A_delay[29]; // rv 0 + assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A_delay[2]; // rv 0 + assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A_delay[30]; // rv 0 + assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A_delay[31]; // rv 0 + assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A_delay[32]; // rv 0 + assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A_delay[33]; // rv 0 + assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A_delay[34]; // rv 0 + assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A_delay[35]; // rv 0 + assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A_delay[36]; // rv 0 + assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A_delay[37]; // rv 0 + assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A_delay[38]; // rv 0 + assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A_delay[39]; // rv 0 + assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A_delay[3]; // rv 0 + assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A_delay[40]; // rv 0 + assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A_delay[41]; // rv 0 + assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A_delay[42]; // rv 0 + assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A_delay[43]; // rv 0 + assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A_delay[44]; // rv 0 + assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A_delay[45]; // rv 0 + assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A_delay[46]; // rv 0 + assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A_delay[47]; // rv 0 + assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A_delay[48]; // rv 0 + assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A_delay[49]; // rv 0 + assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A_delay[4]; // rv 0 + assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A_delay[50]; // rv 0 + assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A_delay[51]; // rv 0 + assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A_delay[52]; // rv 0 + assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A_delay[53]; // rv 0 + assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A_delay[54]; // rv 0 + assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A_delay[55]; // rv 0 + assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A_delay[56]; // rv 0 + assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A_delay[57]; // rv 0 + assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A_delay[58]; // rv 0 + assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A_delay[59]; // rv 0 + assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A_delay[5]; // rv 0 + assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A_delay[60]; // rv 0 + assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A_delay[61]; // rv 0 + assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A_delay[62]; // rv 0 + assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A_delay[63]; // rv 0 + assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A_delay[64]; // rv 0 + assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A_delay[65]; // rv 0 + assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A_delay[66]; // rv 0 + assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A_delay[67]; // rv 0 + assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A_delay[68]; // rv 0 + assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A_delay[69]; // rv 0 + assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A_delay[6]; // rv 0 + assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A_delay[70]; // rv 0 + assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A_delay[71]; // rv 0 + assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A_delay[7]; // rv 0 + assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A_delay[8]; // rv 0 + assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A_delay[9]; // rv 0 + assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B_delay[0]; // rv 0 + assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B_delay[10]; // rv 0 + assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B_delay[11]; // rv 0 + assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B_delay[12]; // rv 0 + assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B_delay[13]; // rv 0 + assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B_delay[14]; // rv 0 + assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B_delay[15]; // rv 0 + assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B_delay[16]; // rv 0 + assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B_delay[17]; // rv 0 + assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B_delay[18]; // rv 0 + assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B_delay[19]; // rv 0 + assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B_delay[1]; // rv 0 + assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B_delay[20]; // rv 0 + assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B_delay[21]; // rv 0 + assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B_delay[22]; // rv 0 + assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B_delay[23]; // rv 0 + assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B_delay[24]; // rv 0 + assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B_delay[25]; // rv 0 + assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B_delay[26]; // rv 0 + assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B_delay[27]; // rv 0 + assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B_delay[28]; // rv 0 + assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B_delay[29]; // rv 0 + assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B_delay[2]; // rv 0 + assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B_delay[30]; // rv 0 + assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B_delay[31]; // rv 0 + assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B_delay[32]; // rv 0 + assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B_delay[33]; // rv 0 + assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B_delay[34]; // rv 0 + assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B_delay[35]; // rv 0 + assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B_delay[36]; // rv 0 + assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B_delay[37]; // rv 0 + assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B_delay[38]; // rv 0 + assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B_delay[39]; // rv 0 + assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B_delay[3]; // rv 0 + assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B_delay[40]; // rv 0 + assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B_delay[41]; // rv 0 + assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B_delay[42]; // rv 0 + assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B_delay[43]; // rv 0 + assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B_delay[44]; // rv 0 + assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B_delay[45]; // rv 0 + assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B_delay[46]; // rv 0 + assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B_delay[47]; // rv 0 + assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B_delay[48]; // rv 0 + assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B_delay[49]; // rv 0 + assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B_delay[4]; // rv 0 + assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B_delay[50]; // rv 0 + assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B_delay[51]; // rv 0 + assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B_delay[52]; // rv 0 + assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B_delay[53]; // rv 0 + assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B_delay[54]; // rv 0 + assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B_delay[55]; // rv 0 + assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B_delay[56]; // rv 0 + assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B_delay[57]; // rv 0 + assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B_delay[58]; // rv 0 + assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B_delay[59]; // rv 0 + assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B_delay[5]; // rv 0 + assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B_delay[60]; // rv 0 + assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B_delay[61]; // rv 0 + assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B_delay[62]; // rv 0 + assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B_delay[63]; // rv 0 + assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B_delay[64]; // rv 0 + assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B_delay[65]; // rv 0 + assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B_delay[66]; // rv 0 + assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B_delay[67]; // rv 0 + assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B_delay[68]; // rv 0 + assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B_delay[69]; // rv 0 + assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B_delay[6]; // rv 0 + assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B_delay[70]; // rv 0 + assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B_delay[71]; // rv 0 + assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B_delay[7]; // rv 0 + assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B_delay[8]; // rv 0 + assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B_delay[9]; // rv 0 + assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A_delay[0]; // rv 0 + assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A_delay[10]; // rv 0 + assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A_delay[11]; // rv 0 + assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A_delay[12]; // rv 0 + assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A_delay[13]; // rv 0 + assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A_delay[14]; // rv 0 + assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A_delay[15]; // rv 0 + assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A_delay[16]; // rv 0 + assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A_delay[17]; // rv 0 + assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A_delay[18]; // rv 0 + assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A_delay[19]; // rv 0 + assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A_delay[1]; // rv 0 + assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A_delay[20]; // rv 0 + assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A_delay[21]; // rv 0 + assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A_delay[22]; // rv 0 + assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A_delay[23]; // rv 0 + assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A_delay[24]; // rv 0 + assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A_delay[25]; // rv 0 + assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A_delay[26]; // rv 0 + assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A_delay[27]; // rv 0 + assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A_delay[28]; // rv 0 + assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A_delay[29]; // rv 0 + assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A_delay[2]; // rv 0 + assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A_delay[30]; // rv 0 + assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A_delay[31]; // rv 0 + assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A_delay[32]; // rv 0 + assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A_delay[33]; // rv 0 + assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A_delay[34]; // rv 0 + assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A_delay[35]; // rv 0 + assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A_delay[36]; // rv 0 + assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A_delay[37]; // rv 0 + assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A_delay[38]; // rv 0 + assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A_delay[39]; // rv 0 + assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A_delay[3]; // rv 0 + assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A_delay[40]; // rv 0 + assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A_delay[41]; // rv 0 + assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A_delay[42]; // rv 0 + assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A_delay[43]; // rv 0 + assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A_delay[44]; // rv 0 + assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A_delay[45]; // rv 0 + assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A_delay[46]; // rv 0 + assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A_delay[47]; // rv 0 + assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A_delay[48]; // rv 0 + assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A_delay[49]; // rv 0 + assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A_delay[4]; // rv 0 + assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A_delay[50]; // rv 0 + assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A_delay[51]; // rv 0 + assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A_delay[52]; // rv 0 + assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A_delay[53]; // rv 0 + assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A_delay[54]; // rv 0 + assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A_delay[55]; // rv 0 + assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A_delay[56]; // rv 0 + assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A_delay[57]; // rv 0 + assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A_delay[58]; // rv 0 + assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A_delay[59]; // rv 0 + assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A_delay[5]; // rv 0 + assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A_delay[60]; // rv 0 + assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A_delay[61]; // rv 0 + assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A_delay[62]; // rv 0 + assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A_delay[63]; // rv 0 + assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A_delay[64]; // rv 0 + assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A_delay[65]; // rv 0 + assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A_delay[66]; // rv 0 + assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A_delay[67]; // rv 0 + assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A_delay[68]; // rv 0 + assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A_delay[69]; // rv 0 + assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A_delay[6]; // rv 0 + assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A_delay[70]; // rv 0 + assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A_delay[71]; // rv 0 + assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A_delay[7]; // rv 0 + assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A_delay[8]; // rv 0 + assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A_delay[9]; // rv 0 + assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B_delay[0]; // rv 0 + assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B_delay[10]; // rv 0 + assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B_delay[11]; // rv 0 + assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B_delay[12]; // rv 0 + assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B_delay[13]; // rv 0 + assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B_delay[14]; // rv 0 + assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B_delay[15]; // rv 0 + assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B_delay[16]; // rv 0 + assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B_delay[17]; // rv 0 + assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B_delay[18]; // rv 0 + assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B_delay[19]; // rv 0 + assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B_delay[1]; // rv 0 + assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B_delay[20]; // rv 0 + assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B_delay[21]; // rv 0 + assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B_delay[22]; // rv 0 + assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B_delay[23]; // rv 0 + assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B_delay[24]; // rv 0 + assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B_delay[25]; // rv 0 + assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B_delay[26]; // rv 0 + assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B_delay[27]; // rv 0 + assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B_delay[28]; // rv 0 + assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B_delay[29]; // rv 0 + assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B_delay[2]; // rv 0 + assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B_delay[30]; // rv 0 + assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B_delay[31]; // rv 0 + assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B_delay[32]; // rv 0 + assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B_delay[33]; // rv 0 + assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B_delay[34]; // rv 0 + assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B_delay[35]; // rv 0 + assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B_delay[36]; // rv 0 + assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B_delay[37]; // rv 0 + assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B_delay[38]; // rv 0 + assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B_delay[39]; // rv 0 + assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B_delay[3]; // rv 0 + assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B_delay[40]; // rv 0 + assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B_delay[41]; // rv 0 + assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B_delay[42]; // rv 0 + assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B_delay[43]; // rv 0 + assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B_delay[44]; // rv 0 + assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B_delay[45]; // rv 0 + assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B_delay[46]; // rv 0 + assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B_delay[47]; // rv 0 + assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B_delay[48]; // rv 0 + assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B_delay[49]; // rv 0 + assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B_delay[4]; // rv 0 + assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B_delay[50]; // rv 0 + assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B_delay[51]; // rv 0 + assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B_delay[52]; // rv 0 + assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B_delay[53]; // rv 0 + assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B_delay[54]; // rv 0 + assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B_delay[55]; // rv 0 + assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B_delay[56]; // rv 0 + assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B_delay[57]; // rv 0 + assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B_delay[58]; // rv 0 + assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B_delay[59]; // rv 0 + assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B_delay[5]; // rv 0 + assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B_delay[60]; // rv 0 + assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B_delay[61]; // rv 0 + assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B_delay[62]; // rv 0 + assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B_delay[63]; // rv 0 + assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B_delay[64]; // rv 0 + assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B_delay[65]; // rv 0 + assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B_delay[66]; // rv 0 + assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B_delay[67]; // rv 0 + assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B_delay[68]; // rv 0 + assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B_delay[69]; // rv 0 + assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B_delay[6]; // rv 0 + assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B_delay[70]; // rv 0 + assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B_delay[71]; // rv 0 + assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B_delay[7]; // rv 0 + assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B_delay[8]; // rv 0 + assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B_delay[9]; // rv 0 + assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A_delay; // rv 0 + assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B_delay; // rv 0 + assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A_delay; // rv 0 + assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B_delay; // rv 0 + assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A_delay; // rv 0 + assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B_delay; // rv 0 + assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A_delay; // rv 0 + assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B_delay; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_A_in = DIN_A_delay; + assign DIN_B_in = DIN_B_delay; + assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0 + assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0 + assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0 + assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0 + assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0 + assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0 + assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1 + assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1 + assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1 + assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1 + assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 + assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 + assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0 + assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 +`else + assign ADDR_A_in = ADDR_A; + assign ADDR_B_in = ADDR_B; + assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1 + assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1 + assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1 + assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1 + assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1 + assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1 + assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1 + assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1 + assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1 + assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1 + assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1 + assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1 + assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1 + assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1 + assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1 + assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1 + assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1 + assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1 + assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A[0]; // rv 0 + assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A[10]; // rv 0 + assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A[11]; // rv 0 + assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A[12]; // rv 0 + assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A[13]; // rv 0 + assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A[14]; // rv 0 + assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A[15]; // rv 0 + assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A[16]; // rv 0 + assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A[17]; // rv 0 + assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A[18]; // rv 0 + assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A[19]; // rv 0 + assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A[1]; // rv 0 + assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A[20]; // rv 0 + assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A[21]; // rv 0 + assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A[22]; // rv 0 + assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A[2]; // rv 0 + assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A[3]; // rv 0 + assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A[4]; // rv 0 + assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A[5]; // rv 0 + assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A[6]; // rv 0 + assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A[7]; // rv 0 + assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A[8]; // rv 0 + assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A[9]; // rv 0 + assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B[0]; // rv 0 + assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B[10]; // rv 0 + assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B[11]; // rv 0 + assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B[12]; // rv 0 + assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B[13]; // rv 0 + assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B[14]; // rv 0 + assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B[15]; // rv 0 + assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B[16]; // rv 0 + assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B[17]; // rv 0 + assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B[18]; // rv 0 + assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B[19]; // rv 0 + assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B[1]; // rv 0 + assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B[20]; // rv 0 + assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B[21]; // rv 0 + assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B[22]; // rv 0 + assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B[2]; // rv 0 + assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B[3]; // rv 0 + assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B[4]; // rv 0 + assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B[5]; // rv 0 + assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B[6]; // rv 0 + assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B[7]; // rv 0 + assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B[8]; // rv 0 + assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B[9]; // rv 0 + assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A[0]; // rv 0 + assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A[1]; // rv 0 + assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A[2]; // rv 0 + assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A[3]; // rv 0 + assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A[4]; // rv 0 + assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A[5]; // rv 0 + assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A[6]; // rv 0 + assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A[7]; // rv 0 + assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A[8]; // rv 0 + assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B[0]; // rv 0 + assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B[1]; // rv 0 + assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B[2]; // rv 0 + assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B[3]; // rv 0 + assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B[4]; // rv 0 + assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B[5]; // rv 0 + assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B[6]; // rv 0 + assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B[7]; // rv 0 + assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B[8]; // rv 0 + assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A; // rv 0 + assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B; // rv 0 + assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A[0]; // rv 0 + assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A[10]; // rv 0 + assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A[11]; // rv 0 + assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A[12]; // rv 0 + assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A[13]; // rv 0 + assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A[14]; // rv 0 + assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A[15]; // rv 0 + assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A[16]; // rv 0 + assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A[17]; // rv 0 + assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A[18]; // rv 0 + assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A[19]; // rv 0 + assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A[1]; // rv 0 + assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A[20]; // rv 0 + assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A[21]; // rv 0 + assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A[22]; // rv 0 + assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A[23]; // rv 0 + assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A[24]; // rv 0 + assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A[25]; // rv 0 + assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A[26]; // rv 0 + assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A[27]; // rv 0 + assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A[28]; // rv 0 + assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A[29]; // rv 0 + assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A[2]; // rv 0 + assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A[30]; // rv 0 + assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A[31]; // rv 0 + assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A[32]; // rv 0 + assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A[33]; // rv 0 + assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A[34]; // rv 0 + assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A[35]; // rv 0 + assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A[36]; // rv 0 + assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A[37]; // rv 0 + assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A[38]; // rv 0 + assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A[39]; // rv 0 + assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A[3]; // rv 0 + assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A[40]; // rv 0 + assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A[41]; // rv 0 + assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A[42]; // rv 0 + assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A[43]; // rv 0 + assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A[44]; // rv 0 + assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A[45]; // rv 0 + assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A[46]; // rv 0 + assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A[47]; // rv 0 + assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A[48]; // rv 0 + assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A[49]; // rv 0 + assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A[4]; // rv 0 + assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A[50]; // rv 0 + assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A[51]; // rv 0 + assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A[52]; // rv 0 + assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A[53]; // rv 0 + assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A[54]; // rv 0 + assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A[55]; // rv 0 + assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A[56]; // rv 0 + assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A[57]; // rv 0 + assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A[58]; // rv 0 + assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A[59]; // rv 0 + assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A[5]; // rv 0 + assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A[60]; // rv 0 + assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A[61]; // rv 0 + assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A[62]; // rv 0 + assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A[63]; // rv 0 + assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A[64]; // rv 0 + assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A[65]; // rv 0 + assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A[66]; // rv 0 + assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A[67]; // rv 0 + assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A[68]; // rv 0 + assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A[69]; // rv 0 + assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A[6]; // rv 0 + assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A[70]; // rv 0 + assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A[71]; // rv 0 + assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A[7]; // rv 0 + assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A[8]; // rv 0 + assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A[9]; // rv 0 + assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B[0]; // rv 0 + assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B[10]; // rv 0 + assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B[11]; // rv 0 + assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B[12]; // rv 0 + assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B[13]; // rv 0 + assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B[14]; // rv 0 + assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B[15]; // rv 0 + assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B[16]; // rv 0 + assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B[17]; // rv 0 + assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B[18]; // rv 0 + assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B[19]; // rv 0 + assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B[1]; // rv 0 + assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B[20]; // rv 0 + assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B[21]; // rv 0 + assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B[22]; // rv 0 + assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B[23]; // rv 0 + assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B[24]; // rv 0 + assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B[25]; // rv 0 + assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B[26]; // rv 0 + assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B[27]; // rv 0 + assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B[28]; // rv 0 + assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B[29]; // rv 0 + assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B[2]; // rv 0 + assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B[30]; // rv 0 + assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B[31]; // rv 0 + assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B[32]; // rv 0 + assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B[33]; // rv 0 + assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B[34]; // rv 0 + assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B[35]; // rv 0 + assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B[36]; // rv 0 + assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B[37]; // rv 0 + assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B[38]; // rv 0 + assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B[39]; // rv 0 + assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B[3]; // rv 0 + assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B[40]; // rv 0 + assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B[41]; // rv 0 + assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B[42]; // rv 0 + assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B[43]; // rv 0 + assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B[44]; // rv 0 + assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B[45]; // rv 0 + assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B[46]; // rv 0 + assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B[47]; // rv 0 + assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B[48]; // rv 0 + assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B[49]; // rv 0 + assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B[4]; // rv 0 + assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B[50]; // rv 0 + assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B[51]; // rv 0 + assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B[52]; // rv 0 + assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B[53]; // rv 0 + assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B[54]; // rv 0 + assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B[55]; // rv 0 + assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B[56]; // rv 0 + assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B[57]; // rv 0 + assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B[58]; // rv 0 + assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B[59]; // rv 0 + assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B[5]; // rv 0 + assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B[60]; // rv 0 + assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B[61]; // rv 0 + assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B[62]; // rv 0 + assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B[63]; // rv 0 + assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B[64]; // rv 0 + assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B[65]; // rv 0 + assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B[66]; // rv 0 + assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B[67]; // rv 0 + assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B[68]; // rv 0 + assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B[69]; // rv 0 + assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B[6]; // rv 0 + assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B[70]; // rv 0 + assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B[71]; // rv 0 + assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B[7]; // rv 0 + assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B[8]; // rv 0 + assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B[9]; // rv 0 + assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A[0]; // rv 0 + assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A[10]; // rv 0 + assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A[11]; // rv 0 + assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A[12]; // rv 0 + assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A[13]; // rv 0 + assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A[14]; // rv 0 + assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A[15]; // rv 0 + assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A[16]; // rv 0 + assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A[17]; // rv 0 + assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A[18]; // rv 0 + assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A[19]; // rv 0 + assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A[1]; // rv 0 + assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A[20]; // rv 0 + assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A[21]; // rv 0 + assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A[22]; // rv 0 + assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A[23]; // rv 0 + assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A[24]; // rv 0 + assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A[25]; // rv 0 + assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A[26]; // rv 0 + assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A[27]; // rv 0 + assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A[28]; // rv 0 + assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A[29]; // rv 0 + assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A[2]; // rv 0 + assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A[30]; // rv 0 + assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A[31]; // rv 0 + assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A[32]; // rv 0 + assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A[33]; // rv 0 + assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A[34]; // rv 0 + assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A[35]; // rv 0 + assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A[36]; // rv 0 + assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A[37]; // rv 0 + assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A[38]; // rv 0 + assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A[39]; // rv 0 + assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A[3]; // rv 0 + assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A[40]; // rv 0 + assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A[41]; // rv 0 + assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A[42]; // rv 0 + assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A[43]; // rv 0 + assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A[44]; // rv 0 + assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A[45]; // rv 0 + assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A[46]; // rv 0 + assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A[47]; // rv 0 + assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A[48]; // rv 0 + assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A[49]; // rv 0 + assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A[4]; // rv 0 + assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A[50]; // rv 0 + assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A[51]; // rv 0 + assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A[52]; // rv 0 + assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A[53]; // rv 0 + assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A[54]; // rv 0 + assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A[55]; // rv 0 + assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A[56]; // rv 0 + assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A[57]; // rv 0 + assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A[58]; // rv 0 + assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A[59]; // rv 0 + assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A[5]; // rv 0 + assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A[60]; // rv 0 + assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A[61]; // rv 0 + assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A[62]; // rv 0 + assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A[63]; // rv 0 + assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A[64]; // rv 0 + assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A[65]; // rv 0 + assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A[66]; // rv 0 + assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A[67]; // rv 0 + assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A[68]; // rv 0 + assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A[69]; // rv 0 + assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A[6]; // rv 0 + assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A[70]; // rv 0 + assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A[71]; // rv 0 + assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A[7]; // rv 0 + assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A[8]; // rv 0 + assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A[9]; // rv 0 + assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B[0]; // rv 0 + assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B[10]; // rv 0 + assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B[11]; // rv 0 + assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B[12]; // rv 0 + assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B[13]; // rv 0 + assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B[14]; // rv 0 + assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B[15]; // rv 0 + assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B[16]; // rv 0 + assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B[17]; // rv 0 + assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B[18]; // rv 0 + assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B[19]; // rv 0 + assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B[1]; // rv 0 + assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B[20]; // rv 0 + assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B[21]; // rv 0 + assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B[22]; // rv 0 + assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B[23]; // rv 0 + assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B[24]; // rv 0 + assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B[25]; // rv 0 + assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B[26]; // rv 0 + assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B[27]; // rv 0 + assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B[28]; // rv 0 + assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B[29]; // rv 0 + assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B[2]; // rv 0 + assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B[30]; // rv 0 + assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B[31]; // rv 0 + assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B[32]; // rv 0 + assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B[33]; // rv 0 + assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B[34]; // rv 0 + assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B[35]; // rv 0 + assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B[36]; // rv 0 + assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B[37]; // rv 0 + assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B[38]; // rv 0 + assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B[39]; // rv 0 + assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B[3]; // rv 0 + assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B[40]; // rv 0 + assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B[41]; // rv 0 + assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B[42]; // rv 0 + assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B[43]; // rv 0 + assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B[44]; // rv 0 + assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B[45]; // rv 0 + assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B[46]; // rv 0 + assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B[47]; // rv 0 + assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B[48]; // rv 0 + assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B[49]; // rv 0 + assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B[4]; // rv 0 + assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B[50]; // rv 0 + assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B[51]; // rv 0 + assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B[52]; // rv 0 + assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B[53]; // rv 0 + assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B[54]; // rv 0 + assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B[55]; // rv 0 + assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B[56]; // rv 0 + assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B[57]; // rv 0 + assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B[58]; // rv 0 + assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B[59]; // rv 0 + assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B[5]; // rv 0 + assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B[60]; // rv 0 + assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B[61]; // rv 0 + assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B[62]; // rv 0 + assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B[63]; // rv 0 + assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B[64]; // rv 0 + assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B[65]; // rv 0 + assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B[66]; // rv 0 + assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B[67]; // rv 0 + assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B[68]; // rv 0 + assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B[69]; // rv 0 + assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B[6]; // rv 0 + assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B[70]; // rv 0 + assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B[71]; // rv 0 + assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B[7]; // rv 0 + assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B[8]; // rv 0 + assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B[9]; // rv 0 + assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A; // rv 0 + assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B; // rv 0 + assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A; // rv 0 + assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B; // rv 0 + assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A; // rv 0 + assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B; // rv 0 + assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A; // rv 0 + assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B; // rv 0 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_A_in = DIN_A; + assign DIN_B_in = DIN_B; + assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0 + assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0 + assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0 + assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0 + assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0 + assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0 + assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1 + assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1 + assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1 + assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1 + assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 + assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 + assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0 + assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; + + assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; + + assign BWE_MODE_A_BIN = + (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : + (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : + BWE_MODE_A_PARITY_INTERLEAVED; + + assign BWE_MODE_B_BIN = + (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : + (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : + BWE_MODE_B_PARITY_INTERLEAVED; + + assign CASCADE_ORDER_A_BIN = + (CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE : + (CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST : + (CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST : + (CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE : + CASCADE_ORDER_A_NONE; + + assign CASCADE_ORDER_B_BIN = + (CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE : + (CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST : + (CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST : + (CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE : + CASCADE_ORDER_B_NONE; + + assign EN_AUTO_SLEEP_MODE_BIN = + (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : + (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : + EN_AUTO_SLEEP_MODE_FALSE; + + assign EN_ECC_RD_A_BIN = + (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : + (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : + EN_ECC_RD_A_FALSE; + + assign EN_ECC_RD_B_BIN = + (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : + (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : + EN_ECC_RD_B_FALSE; + + assign EN_ECC_WR_A_BIN = + (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : + (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : + EN_ECC_WR_A_FALSE; + + assign EN_ECC_WR_B_BIN = + (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : + (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : + EN_ECC_WR_B_FALSE; + + assign IREG_PRE_A_BIN = + (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : + (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : + IREG_PRE_A_FALSE; + + assign IREG_PRE_B_BIN = + (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : + (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : + IREG_PRE_B_FALSE; + + assign NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0]; + + assign NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0]; + + assign NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0]; + + assign OREG_A_BIN = + (OREG_A_REG == "FALSE") ? OREG_A_FALSE : + (OREG_A_REG == "TRUE") ? OREG_A_TRUE : + OREG_A_FALSE; + + assign OREG_B_BIN = + (OREG_B_REG == "FALSE") ? OREG_B_FALSE : + (OREG_B_REG == "TRUE") ? OREG_B_TRUE : + OREG_B_FALSE; + + assign OREG_ECC_A_BIN = + (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : + (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : + OREG_ECC_A_FALSE; + + assign OREG_ECC_B_BIN = + (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : + (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : + OREG_ECC_B_FALSE; + + assign REG_CAS_A_BIN = + (REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE : + (REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE : + REG_CAS_A_FALSE; + + assign REG_CAS_B_BIN = + (REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE : + (REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE : + REG_CAS_B_FALSE; + + assign RST_MODE_A_BIN = + (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : + (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : + RST_MODE_A_SYNC; + + assign RST_MODE_B_BIN = + (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : + (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : + RST_MODE_B_SYNC; + + assign USE_EXT_CE_A_BIN = + (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : + (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : + USE_EXT_CE_A_FALSE; + + assign USE_EXT_CE_B_BIN = + (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : + (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : + USE_EXT_CE_B_FALSE; + +`else + always @ (trig_attr) begin + #1; + AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; + + AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; + + BWE_MODE_A_BIN = + (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : + (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : + BWE_MODE_A_PARITY_INTERLEAVED; + + BWE_MODE_B_BIN = + (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : + (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : + BWE_MODE_B_PARITY_INTERLEAVED; + + CASCADE_ORDER_A_BIN = + (CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE : + (CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST : + (CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST : + (CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE : + CASCADE_ORDER_A_NONE; + + CASCADE_ORDER_B_BIN = + (CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE : + (CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST : + (CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST : + (CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE : + CASCADE_ORDER_B_NONE; + + EN_AUTO_SLEEP_MODE_BIN = + (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : + (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : + EN_AUTO_SLEEP_MODE_FALSE; + + EN_ECC_RD_A_BIN = + (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : + (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : + EN_ECC_RD_A_FALSE; + + EN_ECC_RD_B_BIN = + (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : + (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : + EN_ECC_RD_B_FALSE; + + EN_ECC_WR_A_BIN = + (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : + (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : + EN_ECC_WR_A_FALSE; + + EN_ECC_WR_B_BIN = + (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : + (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : + EN_ECC_WR_B_FALSE; + + IREG_PRE_A_BIN = + (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : + (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : + IREG_PRE_A_FALSE; + + IREG_PRE_B_BIN = + (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : + (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : + IREG_PRE_B_FALSE; + + NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0]; + + NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0]; + + NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0]; + + OREG_A_BIN = + (OREG_A_REG == "FALSE") ? OREG_A_FALSE : + (OREG_A_REG == "TRUE") ? OREG_A_TRUE : + OREG_A_FALSE; + + OREG_B_BIN = + (OREG_B_REG == "FALSE") ? OREG_B_FALSE : + (OREG_B_REG == "TRUE") ? OREG_B_TRUE : + OREG_B_FALSE; + + OREG_ECC_A_BIN = + (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : + (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : + OREG_ECC_A_FALSE; + + OREG_ECC_B_BIN = + (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : + (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : + OREG_ECC_B_FALSE; + + REG_CAS_A_BIN = + (REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE : + (REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE : + REG_CAS_A_FALSE; + + REG_CAS_B_BIN = + (REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE : + (REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE : + REG_CAS_B_FALSE; + + RST_MODE_A_BIN = + (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : + (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : + RST_MODE_A_SYNC; + + RST_MODE_B_BIN = + (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : + (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : + RST_MODE_B_SYNC; + + USE_EXT_CE_A_BIN = + (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : + (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : + USE_EXT_CE_A_FALSE; + + USE_EXT_CE_B_BIN = + (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : + (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : + USE_EXT_CE_B_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((AUTO_SLEEP_LATENCY_REG != 8) && + (AUTO_SLEEP_LATENCY_REG != 3) && + (AUTO_SLEEP_LATENCY_REG != 4) && + (AUTO_SLEEP_LATENCY_REG != 5) && + (AUTO_SLEEP_LATENCY_REG != 6) && + (AUTO_SLEEP_LATENCY_REG != 7) && + (AUTO_SLEEP_LATENCY_REG != 9) && + (AUTO_SLEEP_LATENCY_REG != 10) && + (AUTO_SLEEP_LATENCY_REG != 11) && + (AUTO_SLEEP_LATENCY_REG != 12) && + (AUTO_SLEEP_LATENCY_REG != 13) && + (AUTO_SLEEP_LATENCY_REG != 14) && + (AUTO_SLEEP_LATENCY_REG != 15))) begin + $display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin + $display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BWE_MODE_A_REG != "PARITY_INTERLEAVED") && + (BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin + $display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BWE_MODE_B_REG != "PARITY_INTERLEAVED") && + (BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin + $display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_A_REG != "NONE") && + (CASCADE_ORDER_A_REG != "FIRST") && + (CASCADE_ORDER_A_REG != "LAST") && + (CASCADE_ORDER_A_REG != "MIDDLE"))) begin + $display("Error: [Unisim %s-105] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_B_REG != "NONE") && + (CASCADE_ORDER_B_REG != "FIRST") && + (CASCADE_ORDER_B_REG != "LAST") && + (CASCADE_ORDER_B_REG != "MIDDLE"))) begin + $display("Error: [Unisim %s-106] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG != "FALSE") && + (EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_RD_A_REG != "FALSE") && + (EN_ECC_RD_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_RD_B_REG != "FALSE") && + (EN_ECC_RD_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_WR_A_REG != "FALSE") && + (EN_ECC_WR_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_WR_B_REG != "FALSE") && + (EN_ECC_WR_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IREG_PRE_A_REG != "FALSE") && + (IREG_PRE_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-112] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IREG_PRE_B_REG != "FALSE") && + (IREG_PRE_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-113] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((NUM_UNIQUE_SELF_ADDR_A_REG < 1) || (NUM_UNIQUE_SELF_ADDR_A_REG > 2048))) begin + $display("Error: [Unisim %s-122] NUM_UNIQUE_SELF_ADDR_A attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((NUM_UNIQUE_SELF_ADDR_B_REG < 1) || (NUM_UNIQUE_SELF_ADDR_B_REG > 2048))) begin + $display("Error: [Unisim %s-123] NUM_UNIQUE_SELF_ADDR_B attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((NUM_URAM_IN_MATRIX_REG < 1) || (NUM_URAM_IN_MATRIX_REG > 2048))) begin + $display("Error: [Unisim %s-124] NUM_URAM_IN_MATRIX attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_URAM_IN_MATRIX_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_A_REG != "FALSE") && + (OREG_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_B_REG != "FALSE") && + (OREG_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-126] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_ECC_A_REG != "FALSE") && + (OREG_ECC_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-127] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_ECC_B_REG != "FALSE") && + (OREG_ECC_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-128] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REG_CAS_A_REG != "FALSE") && + (REG_CAS_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] REG_CAS_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((REG_CAS_B_REG != "FALSE") && + (REG_CAS_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] REG_CAS_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RST_MODE_A_REG != "SYNC") && + (RST_MODE_A_REG != "ASYNC"))) begin + $display("Error: [Unisim %s-131] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RST_MODE_B_REG != "SYNC") && + (RST_MODE_B_REG != "ASYNC"))) begin + $display("Error: [Unisim %s-132] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_EXT_CE_A_REG != "FALSE") && + (USE_EXT_CE_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-137] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_EXT_CE_B_REG != "FALSE") && + (USE_EXT_CE_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-138] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model +// define tasks, functions + +reg cas_a_warning = 1'b0; +reg cas_b_warning = 1'b0; +task is_cas_a_zero; +integer i; +begin + cas_a_warning = 1'b0; + for (i=0;i<=22;i=i+1) begin + if (CAS_IN_ADDR_A[i] !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_ADDR_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + for (i=0;i<=8;i=i+1) begin + if (CAS_IN_BWE_A[i] !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_BWE_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + if (CAS_IN_DBITERR_A !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_DBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DIN_A[i] !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_DIN_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DOUT_A[i] !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_DOUT_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + if (CAS_IN_EN_A !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_EN_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_RDACCESS_A !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_RDACCESS_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_RDB_WR_A !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_RDB_WR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_SBITERR_A !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-15] CAS_IN_SBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end +end +endtask // is_cas_a_zero + +task is_cas_a_floating; +integer i; +begin + cas_a_warning = 1'b0; + for (i=0;i<=22;i=i+1) begin + if (CAS_IN_ADDR_A[i] === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_ADDR_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + for (i=0;i<=8;i=i+1) begin + if (CAS_IN_BWE_A[i] === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_BWE_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + if (CAS_IN_DBITERR_A === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_DBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DIN_A[i] === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_DIN_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DOUT_A[i] === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_DOUT_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); + end + end + if (CAS_IN_EN_A === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_EN_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_RDACCESS_A === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_RDACCESS_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_RDB_WR_A === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_RDB_WR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + if (CAS_IN_SBITERR_A === 1'bz) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-16] CAS_IN_SBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end +end +endtask // is_cas_a_floating + +task is_cas_b_zero; +integer i; +begin + cas_b_warning = 1'b0; + for (i=0;i<=22;i=i+1) begin + if (CAS_IN_ADDR_B[i] !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_ADDR_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); + end + end + for (i=0;i<=8;i=i+1) begin + if (CAS_IN_BWE_B[i] !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_BWE_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); + end + end + if (CAS_IN_DBITERR_B !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_DBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DIN_B[i] !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_DIN_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); + end + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DOUT_B[i] !== 1'b0) begin + cas_a_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_DOUT_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); + end + end + if (CAS_IN_EN_B !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_EN_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + if (CAS_IN_RDACCESS_B !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_RDACCESS_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + if (CAS_IN_RDB_WR_B !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_RDB_WR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + if (CAS_IN_SBITERR_B !== 1'b0) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-17] CAS_IN_SBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end +end +endtask // is_cas_b_zero + +task is_cas_b_floating; +integer i; +begin + cas_b_warning = 1'b0; + for (i=0;i<=22;i=i+1) begin + if (CAS_IN_ADDR_B[i] === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_ADDR_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + for (i=0;i<=8;i=i+1) begin + if (CAS_IN_BWE_B[i] === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_BWE_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + if (CAS_IN_DBITERR_B === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_DBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DIN_B[i] === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_DIN_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + for (i=0;i<=71;i=i+1) begin + if (CAS_IN_DOUT_B[i] === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_DOUT_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); + end + end + if (CAS_IN_EN_B === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_EN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CAS_IN_RDACCESS_B === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_RDACCESS_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CAS_IN_RDB_WR_B === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_RDB_WR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end + if (CAS_IN_SBITERR_B === 1'bz) begin + cas_b_warning = 1'b1; + $display("Warning: [Unisim %s-18] CAS_IN_SBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); + end +end +endtask // is_cas_b_floating + +function [7:0] fn_ecc ( + input encode, + input [63:0] d_i, + input [7:0] dp_i + ); + reg ecc_7; +begin + fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^ + d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^ + d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^ + d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^ + d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^ + d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^ + d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63]; + + fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^ + d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^ + d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^ + d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^ + d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^ + d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^ + d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63]; + + fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ + d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^ + d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ + d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ + d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ + d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ + d_i[62] ^ d_i[63]; + + ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^ + d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ + d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ + d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ + d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ + d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ + d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ + d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ + d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ + d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ + d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ + d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^ + d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + if (encode) begin + fn_ecc[7] = ecc_7 ^ + fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^ + fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6]; + end + else begin + fn_ecc[7] = ecc_7 ^ + dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^ + dp_i[4] ^ dp_i[5] ^ dp_i[6]; + end +end +endfunction // fn_ecc + +function [71:0] fn_cor_bit ( + input [6:0] error_bit, + input [63:0] d_i, + input [7:0] dp_i + ); + reg [71:0] cor_int; +begin + cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4], + d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0], + dp_i[7]}; + cor_int[error_bit] = ~cor_int[error_bit]; + fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16], + cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65], + cor_int[63:33], cor_int[31:17], cor_int[15:9], + cor_int[7:5], cor_int[3]}; +end +endfunction // fn_cor_bit + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_A_REG != "NONE") && + (USE_EXT_CE_A_REG == "TRUE"))) begin + $display("Error: [Unisim %s-1] CASCADE_ORDER_A attribute is set to %s and USE_EXT_CE_A attribute is set to %s. EXT_CE_A can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG, USE_EXT_CE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((CASCADE_ORDER_B_REG != "NONE") && + (USE_EXT_CE_B_REG == "TRUE"))) begin + $display("Error: [Unisim %s-2] CASCADE_ORDER_B attribute is set to %s and USE_EXT_CE_B attribute is set to %s. EXT_CE_B can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG, USE_EXT_CE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + (CASCADE_ORDER_A_REG == "NONE") || + (CASCADE_ORDER_A_REG == "FIRST")) begin + is_cas_a_zero; + if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + + if ((attr_test == 1'b1) || + (CASCADE_ORDER_A_REG == "LAST") || + (CASCADE_ORDER_A_REG == "MIDDLE")) begin + is_cas_a_floating; + if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); + end + + if ((attr_test == 1'b1) || + (CASCADE_ORDER_B_REG == "NONE") || + (CASCADE_ORDER_B_REG == "FIRST")) begin + is_cas_b_zero; + if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + + if ((attr_test == 1'b1) || + (CASCADE_ORDER_B_REG == "LAST") || + (CASCADE_ORDER_B_REG == "MIDDLE")) begin + is_cas_b_floating; + if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); + end + + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && + (USE_EXT_CE_A_REG == "TRUE"))) begin + $display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && + (USE_EXT_CE_B_REG == "TRUE"))) begin + $display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end +`endif + + localparam mem_width = 72; + localparam mem_depth = 4 * 1024; + localparam encode = 1'b1; + localparam decode = 1'b0; + localparam [22:0] ADDR_INIT = 23'b0; + localparam [8:0] BWE_INIT = 9'b0; + localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}}; + localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}}; + + reg [mem_width-1 : 0 ] mem [0 : mem_depth-1]; + + integer wa; + reg [11:0] ram_addr_a; + reg [11:0] ram_addr_b; + reg ram_ce_a; + reg ram_ce_b; + reg DEEPSLEEP_in = 1'b0; + reg SHUTDOWN_in = 1'b0; + reg ram_ce_a_int=0; + reg ram_ce_b_int=0; + reg ram_ce_a_pre=0; + reg ram_ce_b_pre=0; + reg [15:1] ram_ce_a_fifo; + reg [15:1] ram_ce_b_fifo; + reg [71:0] ram_bwe_a; + reg [71:0] ram_bwe_b; + reg ram_we_a; + reg ram_we_b; + reg ram_we_a_event = 1'b0; + reg ram_we_b_event = 1'b0; + reg [71:0] ram_data_a; + reg [71:0] ram_data_b; + +// input register stages +// decisions simulate faster than assignments - wider muxes, less busses + reg [22:0] ADDR_A_reg; + reg [22:0] ADDR_B_reg; + reg [8:0] BWE_A_reg; + reg [8:0] BWE_B_reg; + reg [71:0] DIN_A_reg; + reg [71:0] DIN_B_reg; + reg EN_A_reg; + reg EN_B_reg; + reg INJECT_DBITERR_A_reg; + reg INJECT_DBITERR_B_reg; + reg INJECT_SBITERR_A_reg; + reg INJECT_SBITERR_B_reg; + reg RDB_WR_A_reg; + reg RDB_WR_B_reg; + reg [22:0] ADDR_A_int; + reg [22:0] ADDR_B_int; + reg [8:0] BWE_A_int; + reg [8:0] BWE_B_int; + reg [71:0] DIN_A_int; + reg [71:0] DIN_B_int; + reg EN_A_int; + reg EN_B_int; + reg INJECT_DBITERR_A_int; + reg INJECT_DBITERR_B_int; + reg INJECT_SBITERR_A_int; + reg INJECT_SBITERR_B_int; + reg RDB_WR_A_int; + reg RDB_WR_B_int; + + reg RST_A_async = 1'b0; + reg RST_B_async = 1'b0; + reg RST_A_sync = 1'b0; + reg RST_B_sync = 1'b0; + + integer wake_count; + wire auto_sleep; + reg shut_down; + reg a_sleep; + reg auto_sleep_A; + reg auto_sleep_B; + wire auto_wake_up_A; + wire auto_wake_up_B; + + reg CAS_OUT_DBITERR_A_out; + reg CAS_OUT_DBITERR_B_out; + reg CAS_OUT_EN_A_out; + reg CAS_OUT_EN_B_out; + reg CAS_OUT_RDACCESS_A_out; + reg CAS_OUT_RDACCESS_B_out; + reg CAS_OUT_RDB_WR_A_out; + reg CAS_OUT_RDB_WR_B_out; + reg CAS_OUT_SBITERR_A_out; + reg CAS_OUT_SBITERR_B_out; + reg DBITERR_A_out; + reg DBITERR_B_out; + reg RDACCESS_A_out; + reg RDACCESS_B_out; + reg SBITERR_A_out; + reg SBITERR_B_out; + reg [22:0] CAS_OUT_ADDR_A_out; + reg [22:0] CAS_OUT_ADDR_B_out; + reg [71:0] CAS_OUT_DIN_A_out; + reg [71:0] CAS_OUT_DIN_B_out; + reg [71:0] CAS_OUT_DOUT_A_out; + reg [71:0] CAS_OUT_DOUT_B_out; + reg [71:0] DOUT_A_out; + reg [71:0] DOUT_B_out; + reg [8:0] CAS_OUT_BWE_A_out; + reg [8:0] CAS_OUT_BWE_B_out; + + assign CAS_OUT_ADDR_A = CAS_OUT_ADDR_A_out; + assign CAS_OUT_ADDR_B = CAS_OUT_ADDR_B_out; + assign CAS_OUT_BWE_A = CAS_OUT_BWE_A_out; + assign CAS_OUT_BWE_B = CAS_OUT_BWE_B_out; + assign CAS_OUT_DBITERR_A = DBITERR_A_out; + assign CAS_OUT_DBITERR_B = DBITERR_B_out; + assign CAS_OUT_DIN_A = CAS_OUT_DIN_A_out; + assign CAS_OUT_DIN_B = CAS_OUT_DIN_B_out; + assign CAS_OUT_DOUT_A = DOUT_A_out; + assign CAS_OUT_DOUT_B = DOUT_B_out; + assign CAS_OUT_EN_A = CAS_OUT_EN_A_out; + assign CAS_OUT_EN_B = CAS_OUT_EN_B_out; + assign CAS_OUT_RDACCESS_A = RDACCESS_A_out; + assign CAS_OUT_RDACCESS_B = RDACCESS_B_out; + assign CAS_OUT_RDB_WR_A = CAS_OUT_RDB_WR_A_out; + assign CAS_OUT_RDB_WR_B = CAS_OUT_RDB_WR_B_out; + assign CAS_OUT_SBITERR_A = SBITERR_A_out; + assign CAS_OUT_SBITERR_B = SBITERR_B_out; + assign DBITERR_A = DBITERR_A_out; + assign DBITERR_B = DBITERR_B_out; + assign DOUT_A = DOUT_A_out; + assign DOUT_B = DOUT_B_out; + assign RDACCESS_A = RDACCESS_A_out; + assign RDACCESS_B = RDACCESS_B_out; + assign SBITERR_A = SBITERR_A_out; + assign SBITERR_B = SBITERR_B_out; + +`ifndef XIL_XECLIB + reg INIT_RAM = 1'b0; + initial begin + #100; INIT_RAM = 1'b1; + end +`endif + +`ifndef XIL_XECLIB + reg rst_a_warn_once = 1'b0; + reg rst_b_warn_once = 1'b0; + + always @(posedge CLK_in) begin + if ((attr_test == 1'b1) || + ((EN_A_int == 1'b1) && (RDB_WR_A_int == 1'b0) && + ((RST_A_sync == 1'b1) || (RST_A_async == 1'b1)) && + (CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + if (rst_a_warn_once == 1'b0) begin + $display("Warning: [Unisim %s-11] At time (%.3f) ns: CASCADE_ORDER_A attribute is set to %s and REG_CAS_A attribute is set to %s with RST_A and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_A attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_A when RST_A is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_A_REG, REG_CAS_A_REG); + rst_a_warn_once = 1'b1; + end + end else begin + rst_a_warn_once = 1'b0; + end + end + + always @(posedge CLK_in) begin + if ((attr_test == 1'b1) || + ((EN_B_int == 1'b1) && (RDB_WR_B_int == 1'b0) && + ((RST_B_sync == 1'b1) || (RST_B_async == 1'b1)) && + (CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + if (rst_b_warn_once == 1'b0) begin + $display("Warning: [Unisim %s-12] At time (%.3f) ns: CASCADE_ORDER_B attribute is set to %s and REG_CAS_B attribute is set to %s with RST_B and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_B attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_B when RST_B is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_B_REG, REG_CAS_B_REG); + rst_b_warn_once = 1'b1; + end + end else begin + rst_b_warn_once = 1'b0; + end + end + +`endif + + always @ (*) begin + if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin + RST_A_async = RST_A_in; + end + end + + always @ (*) begin + if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin + RST_B_async = RST_B_in; + end + end + + always @ (posedge CLK_in) begin + if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in)) + RST_A_sync <= RST_A_in; + if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in)) + RST_B_sync <= RST_B_in; + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || + (((CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) && + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_FALSE)))) begin + ADDR_A_reg <= ADDR_INIT; + EN_A_reg <= 1'b0; + RDB_WR_A_reg <= 1'b0; + BWE_A_reg <= BWE_INIT; + DIN_A_reg <= D_INIT; + INJECT_DBITERR_A_reg <= 1'b0; + INJECT_SBITERR_A_reg <= 1'b0; + end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE)) begin + EN_A_reg <= CAS_IN_EN_A_in; + if (CAS_IN_EN_A_in) begin + ADDR_A_reg[22:12] <= CAS_IN_ADDR_A_in[22:12]; + end + if (CAS_IN_EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_A_reg[11:0] <= CAS_IN_ADDR_A_in[11:0]; + BWE_A_reg <= CAS_IN_BWE_A_in; + DIN_A_reg <= CAS_IN_DIN_A_in; + RDB_WR_A_reg <= CAS_IN_RDB_WR_A_in; + end + end else begin + EN_A_reg <= EN_A_in; + if (EN_A_in) begin + ADDR_A_reg[22:12] <= ADDR_A_in[22:12]; + end + if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_A_reg[11:0] <= ADDR_A_in[11:0]; + BWE_A_reg <= BWE_A_in; + DIN_A_reg <= DIN_A_in; + INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in; + INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in; + RDB_WR_A_reg <= RDB_WR_A_in; + end + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin + ADDR_A_int = CAS_IN_ADDR_A_in; + end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + ADDR_A_int = ADDR_A_reg; + end else begin + ADDR_A_int = ADDR_A_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin + BWE_A_int = CAS_IN_BWE_A_in; + end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + BWE_A_int = BWE_A_reg; + end else begin + BWE_A_int = BWE_A_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin + DIN_A_int = CAS_IN_DIN_A_in; + end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + DIN_A_int = DIN_A_reg; + end else begin + DIN_A_int = DIN_A_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin + EN_A_int = CAS_IN_EN_A_in; + end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + EN_A_int = EN_A_reg; + end else begin + EN_A_int = EN_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg; + end else begin + INJECT_DBITERR_A_int = INJECT_DBITERR_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg; + end else begin + INJECT_SBITERR_A_int = INJECT_SBITERR_A_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin + RDB_WR_A_int = CAS_IN_RDB_WR_A_in; + end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && + (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || + (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin + RDB_WR_A_int = RDB_WR_A_reg; + end else begin + RDB_WR_A_int = RDB_WR_A_in; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || + (((CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) && + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_FALSE)))) begin + ADDR_B_reg <= ADDR_INIT; + EN_B_reg <= 1'b0; + RDB_WR_B_reg <= 1'b0; + BWE_B_reg <= BWE_INIT; + DIN_B_reg <= D_INIT; + INJECT_DBITERR_B_reg <= 1'b0; + INJECT_SBITERR_B_reg <= 1'b0; + end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE)) begin + EN_B_reg <= CAS_IN_EN_B_in; + if (CAS_IN_EN_B_in) begin + ADDR_B_reg[22:12] <= CAS_IN_ADDR_B_in[22:12]; + end + if (CAS_IN_EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_B_reg[11:0] <= CAS_IN_ADDR_B_in[11:0]; + BWE_B_reg <= CAS_IN_BWE_B_in; + DIN_B_reg <= CAS_IN_DIN_B_in; + RDB_WR_B_reg <= CAS_IN_RDB_WR_B_in; + end + end else begin + EN_B_reg <= EN_B_in; + if (EN_B_in) begin + ADDR_B_reg[22:12] <= ADDR_B_in[22:12]; + end + if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_B_reg[11:0] <= ADDR_B_in[11:0]; + BWE_B_reg <= BWE_B_in; + DIN_B_reg <= DIN_B_in; + INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in; + INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in; + RDB_WR_B_reg <= RDB_WR_B_in; + end + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin + ADDR_B_int = CAS_IN_ADDR_B_in; + end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + ADDR_B_int = ADDR_B_reg; + end else begin + ADDR_B_int = ADDR_B_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin + BWE_B_int = CAS_IN_BWE_B_in; + end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + BWE_B_int = BWE_B_reg; + end else begin + BWE_B_int = BWE_B_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin + DIN_B_int = CAS_IN_DIN_B_in; + end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + DIN_B_int = DIN_B_reg; + end else begin + DIN_B_int = DIN_B_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin + EN_B_int = CAS_IN_EN_B_in; + end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + EN_B_int = EN_B_reg; + end else begin + EN_B_int = EN_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg; + end else begin + INJECT_DBITERR_B_int = INJECT_DBITERR_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg; + end else begin + INJECT_SBITERR_B_int = INJECT_SBITERR_B_in; + end + end + + always @ (*) begin + if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin + RDB_WR_B_int = CAS_IN_RDB_WR_B_in; + end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && + (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || + (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin + RDB_WR_B_int = RDB_WR_B_reg; + end else begin + RDB_WR_B_int = RDB_WR_B_in; + end + end + +// cascade out - input controls + + always @ (*) begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin + CAS_OUT_ADDR_A_out = ADDR_INIT; + end else begin + CAS_OUT_ADDR_A_out = ADDR_A_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin + CAS_OUT_BWE_A_out = BWE_INIT; + end else begin + CAS_OUT_BWE_A_out = BWE_A_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin + CAS_OUT_DIN_A_out = D_INIT; + end else begin + CAS_OUT_DIN_A_out = DIN_A_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin + CAS_OUT_EN_A_out = 1'b0; + end else begin + CAS_OUT_EN_A_out = EN_A_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin + CAS_OUT_RDB_WR_A_out = 1'b0; + end else begin + CAS_OUT_RDB_WR_A_out = RDB_WR_A_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin + CAS_OUT_ADDR_B_out = ADDR_INIT; + end else begin + CAS_OUT_ADDR_B_out = ADDR_B_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin + CAS_OUT_BWE_B_out = BWE_INIT; + end else begin + CAS_OUT_BWE_B_out = BWE_B_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin + CAS_OUT_DIN_B_out = D_INIT; + end else begin + CAS_OUT_DIN_B_out = DIN_B_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin + CAS_OUT_EN_B_out = 1'b0; + end else begin + CAS_OUT_EN_B_out = EN_B_int; + end + end + + always @ (*) begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin + CAS_OUT_RDB_WR_B_out = 1'b0; + end else begin + CAS_OUT_RDB_WR_B_out = RDB_WR_B_int; + end + end + +// cascade=data out - outputs + + reg [71:0] ram_data_a_lat; + reg [71:0] ram_data_a_out; +// reg [71:0] ram_data_a_hold=D_INIT; + reg [71:0] ram_data_a_reg; + reg [71:0] ram_data_a_ecc=72'h000000000000000000; + reg [71:0] ram_data_b_lat; + reg [71:0] ram_data_b_out; + reg [71:0] ram_data_b_reg; + reg [71:0] ram_data_b_ecc=72'h000000000000000000; + reg RDACCESS_A_lat; +// reg RDACCESS_A_hold; + reg RDACCESS_B_lat; + reg RDACCESS_A_int; + reg RDACCESS_B_int; + reg SBITERR_A_ecc=1'b0; + reg DBITERR_A_ecc=1'b0; + reg SBITERR_B_ecc=1'b0; + reg DBITERR_B_ecc=1'b0; + + reg DBITERR_A_reg; + reg DBITERR_B_reg; + reg [71:0] DOUT_A_reg; + reg [71:0] DOUT_B_reg; + reg RDACCESS_A_reg; + reg RDACCESS_B_reg; + reg SBITERR_A_reg; + reg SBITERR_B_reg; + + reg RDACCESS_A_ecc_reg; + reg RDACCESS_B_ecc_reg; + + reg CAS_IN_DBITERR_A_reg; + reg CAS_IN_DBITERR_B_reg; + reg [71:0] CAS_IN_DOUT_A_reg; + reg [71:0] CAS_IN_DOUT_B_reg; + reg CAS_IN_RDACCESS_A_reg; + reg CAS_IN_RDACCESS_B_reg; + reg CAS_IN_SBITERR_A_reg; + reg CAS_IN_SBITERR_B_reg; + reg data_A_enable = 1'b0; + reg data_B_enable = 1'b0; + +// data/cas reg +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin +`endif + CAS_IN_DBITERR_A_reg <= 1'b0; + CAS_IN_DOUT_A_reg <= D_INIT; + CAS_IN_RDACCESS_A_reg <= 1'b0; + CAS_IN_SBITERR_A_reg <= 1'b0; + end else begin + if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) begin + CAS_IN_RDACCESS_A_reg <= CAS_IN_RDACCESS_A_in; + if (CAS_IN_RDACCESS_A_in) begin + CAS_IN_DBITERR_A_reg <= CAS_IN_DBITERR_A_in; + CAS_IN_DOUT_A_reg <= CAS_IN_DOUT_A_in; + CAS_IN_SBITERR_A_reg <= CAS_IN_SBITERR_A_in; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin +`endif + CAS_IN_DBITERR_B_reg <= 1'b0; + CAS_IN_DOUT_B_reg <= D_INIT; + CAS_IN_RDACCESS_B_reg <= 1'b0; + CAS_IN_SBITERR_B_reg <= 1'b0; + end else begin + if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) begin + CAS_IN_RDACCESS_B_reg <= CAS_IN_RDACCESS_B_in; + if (CAS_IN_RDACCESS_B_in) begin + CAS_IN_DBITERR_B_reg <= CAS_IN_DBITERR_B_in; + CAS_IN_DOUT_B_reg <= CAS_IN_DOUT_B_in; + CAS_IN_SBITERR_B_reg <= CAS_IN_SBITERR_B_in; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || +`endif + shut_down || SHUTDOWN_in) begin + RDACCESS_A_int = 1'b0; + end else begin + if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin + RDACCESS_A_int = RDACCESS_A_ecc_reg; + end else begin + RDACCESS_A_int = 1'b0; + end + end else if (OREG_A_BIN == OREG_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin + RDACCESS_A_int = RDACCESS_A_reg; + end else begin + RDACCESS_A_int = 1'b0; + end + end else begin + RDACCESS_A_int = RDACCESS_A_lat; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || +`endif + shut_down || SHUTDOWN_in) begin + RDACCESS_B_int = 1'b0; + end else begin + if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin + RDACCESS_B_int = RDACCESS_B_ecc_reg; + end else begin + RDACCESS_B_int = 1'b0; + end + end else if (OREG_B_BIN == OREG_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin + RDACCESS_B_int = RDACCESS_B_reg; + end else begin + RDACCESS_B_int = 1'b0; + end + end else begin + RDACCESS_B_int = RDACCESS_B_lat; + end + end + end + +reg cas_out_mux_sel_a; +reg cas_out_mux_sel_b; +reg cas_out_mux_sel_a_reg; +reg cas_out_mux_sel_b_reg; + + always @ (*) begin + if ((CAS_IN_RDACCESS_A_in && REG_CAS_A_BIN == REG_CAS_A_FALSE) || + (CAS_IN_RDACCESS_A_reg && REG_CAS_A_BIN == REG_CAS_A_TRUE) || + RDACCESS_A_int) begin + cas_out_mux_sel_a = ~RDACCESS_A_int; + end else begin + cas_out_mux_sel_a = ~cas_out_mux_sel_a_reg; + end + end + + always @ (*) begin + if ((CAS_IN_RDACCESS_B_in && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) || + (CAS_IN_RDACCESS_B_reg && (REG_CAS_B_BIN == REG_CAS_B_TRUE)) || + RDACCESS_B_int) begin + cas_out_mux_sel_b = ~RDACCESS_B_int; + end else begin + cas_out_mux_sel_b = ~cas_out_mux_sel_b_reg; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR) begin +`endif + cas_out_mux_sel_a_reg <= 1'b0; + end else begin + cas_out_mux_sel_a_reg <= ~cas_out_mux_sel_a; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR) begin +`endif + cas_out_mux_sel_b_reg <= 1'b0; + end else begin + cas_out_mux_sel_b_reg <= ~cas_out_mux_sel_b; + end + end + +// data out mux + always @ (*) begin + if (RST_A_async || RST_A_sync || glblGSR) begin + RDACCESS_A_out = 1'b0; + end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + cas_out_mux_sel_a) begin + if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin + RDACCESS_A_out = CAS_IN_RDACCESS_A_reg; + end else begin + RDACCESS_A_out = CAS_IN_RDACCESS_A_in; + end + end else begin + RDACCESS_A_out = RDACCESS_A_int; + end + end + + always @ (*) begin + if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin + DBITERR_A_out = 1'b0; + SBITERR_A_out = 1'b0; + end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + cas_out_mux_sel_a) begin + if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin + DBITERR_A_out = CAS_IN_DBITERR_A_reg; + SBITERR_A_out = CAS_IN_SBITERR_A_reg; + end else begin + DBITERR_A_out = CAS_IN_DBITERR_A_in; + SBITERR_A_out = CAS_IN_SBITERR_A_in; + end + end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + DBITERR_A_out = DBITERR_A_reg; + SBITERR_A_out = SBITERR_A_reg; + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DBITERR_A_out = DBITERR_A_ecc; + SBITERR_A_out = SBITERR_A_ecc; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`endif + data_A_enable <= 1'b0; + end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin + data_A_enable <= 1'b1; + end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin + data_A_enable <= 1'b1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`endif + data_B_enable <= 1'b0; + end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin + data_B_enable <= 1'b1; + end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin + data_B_enable <= 1'b1; + end + end + + always @ (posedge CLK_in) begin + if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin + $display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG); + end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin + $display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin + $display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin + $display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end + end + + always @ (posedge CLK_in) begin + if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin + $display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG); + end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin + $display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin + $display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin + $display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end + end + + always @ (*) begin + if (RST_A_async || RST_A_sync || glblGSR) begin + DOUT_A_out = D_INIT; + end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || + (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && + cas_out_mux_sel_a) begin + if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin + DOUT_A_out = CAS_IN_DOUT_A_reg; + end else begin + DOUT_A_out = CAS_IN_DOUT_A_in; + end + end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + DOUT_A_out = DOUT_A_reg; + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DOUT_A_out = ram_data_a_ecc; + end else if (data_A_enable) begin + if (OREG_A_BIN == OREG_A_TRUE) begin + DOUT_A_out = ram_data_a_reg; + end else begin + DOUT_A_out = ram_data_a_lat; + end + end else begin + DOUT_A_out = D_INIT; + end + end + + always @ (*) begin + if (RST_B_async || RST_B_sync || glblGSR) begin + RDACCESS_B_out = 1'b0; + end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + cas_out_mux_sel_b) begin + if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin + RDACCESS_B_out = CAS_IN_RDACCESS_B_reg; + end else begin + RDACCESS_B_out = CAS_IN_RDACCESS_B_in; + end + end else begin + RDACCESS_B_out = RDACCESS_B_int; + end + end + + always @ (*) begin + if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin + DBITERR_B_out = 1'b0; + SBITERR_B_out = 1'b0; + end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + cas_out_mux_sel_b) begin + if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin + DBITERR_B_out = CAS_IN_DBITERR_B_reg; + SBITERR_B_out = CAS_IN_SBITERR_B_reg; + end else begin + DBITERR_B_out = CAS_IN_DBITERR_B_in; + SBITERR_B_out = CAS_IN_SBITERR_B_in; + end + end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + DBITERR_B_out = DBITERR_B_reg; + SBITERR_B_out = SBITERR_B_reg; + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DBITERR_B_out = DBITERR_B_ecc; + SBITERR_B_out = SBITERR_B_ecc; + end + end + + always @ (*) begin + if (RST_B_async || RST_B_sync || glblGSR) begin + DOUT_B_out = D_INIT; + end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || + (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && + cas_out_mux_sel_b) begin + if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin + DOUT_B_out = CAS_IN_DOUT_B_reg; + end else begin + DOUT_B_out = CAS_IN_DOUT_B_in; + end + end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + DOUT_B_out = DOUT_B_reg; + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DOUT_B_out = ram_data_b_ecc; + end else if (data_B_enable) begin + if (OREG_B_BIN == OREG_B_TRUE) begin + DOUT_B_out = ram_data_b_reg; + end else begin + DOUT_B_out = ram_data_b_lat; + end + end else begin + DOUT_B_out = D_INIT; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + DBITERR_A_reg <= 1'b0; + SBITERR_A_reg <= 1'b0; + end else if ((~a_sleep && ~shut_down && data_A_enable) && + (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || + ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin + if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin + DBITERR_A_reg <= DBITERR_A_ecc; + SBITERR_A_reg <= SBITERR_A_ecc; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + DOUT_A_reg <= D_INIT; + end else if (~shut_down && data_A_enable) begin + if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin + if (OREG_ECC_CE_A_in) begin + if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DOUT_A_reg <= ram_data_a_ecc; + end else if (OREG_A_BIN == OREG_A_TRUE) begin + DOUT_A_reg <= ram_data_a_reg; + end else begin + DOUT_A_reg <= ram_data_a_lat; + end + end + end else if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || + ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin + if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DOUT_A_reg <= ram_data_a_ecc; + end else if (OREG_A_BIN == OREG_A_TRUE) begin + DOUT_A_reg <= ram_data_a_reg; + end else begin + DOUT_A_reg <= ram_data_a_lat; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + RDACCESS_A_ecc_reg <= 1'b0; + end else begin + if (OREG_A_BIN == OREG_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin + RDACCESS_A_ecc_reg <= RDACCESS_A_reg; + end + end else begin + RDACCESS_A_ecc_reg <= RDACCESS_A_lat; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + DBITERR_B_reg <= 1'b0; + SBITERR_B_reg <= 1'b0; + end else if ((~a_sleep && ~shut_down && data_B_enable) && + (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || + ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin + if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin + DBITERR_B_reg <= DBITERR_B_ecc; + SBITERR_B_reg <= SBITERR_B_ecc; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + DOUT_B_reg <= D_INIT; + end else if (~shut_down && data_B_enable) begin + if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin + if (OREG_ECC_CE_B_in) begin + if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DOUT_B_reg <= ram_data_b_ecc; + end else if (OREG_B_BIN == OREG_B_TRUE) begin + DOUT_B_reg <= ram_data_b_reg; + end else begin + DOUT_B_reg <= ram_data_b_lat; + end + end + end else if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || + ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin + if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DOUT_B_reg <= ram_data_b_ecc; + end else if (OREG_B_BIN == OREG_B_TRUE) begin + DOUT_B_reg <= ram_data_b_reg; + end else begin + DOUT_B_reg <= ram_data_b_lat; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + RDACCESS_B_ecc_reg <= 1'b0; + end else begin + if (OREG_B_BIN == OREG_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin + RDACCESS_B_ecc_reg <= RDACCESS_B_reg; + end + end else begin + RDACCESS_B_ecc_reg <= RDACCESS_B_lat; + end + end + end + +// ram oreg +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin + if (RST_A_in || shut_down || a_sleep || glblGSR) begin +`endif + RDACCESS_A_reg <= 1'b0; + end else begin + RDACCESS_A_reg <= RDACCESS_A_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin + if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin +`endif + ram_data_a_reg <= D_INIT; + end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin + if (OREG_CE_A_in) begin + ram_data_a_reg = ram_data_a_lat; + end + end else if (ram_ce_a_int || RDACCESS_A_reg) begin + ram_data_a_reg = ram_data_a_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin + if (RST_B_in || shut_down || a_sleep || glblGSR) begin +`endif + RDACCESS_B_reg <= 1'b0; + end else begin + RDACCESS_B_reg <= RDACCESS_B_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin + if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin +`endif + ram_data_b_reg <= D_INIT; + end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin + if (OREG_CE_B_in) begin + ram_data_b_reg = ram_data_b_lat; + end + end else if (ram_ce_b_int || RDACCESS_B_reg) begin + ram_data_b_reg = ram_data_b_lat; + end + end + + reg [15:1] ram_ce_a_fifo_in = 15'b0; + always @ (*) begin + ram_ce_a_fifo_in = 15'b0; + ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int; + end +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + ram_ce_a_fifo <= 15'b0; + end else begin + ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in; + end + end + + always @ (*) begin + if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin + ram_ce_a_pre = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int; + end else begin + ram_ce_a_pre = ram_ce_a_fifo[1]; + end + end + + always @ (*) begin + if (a_sleep || SLEEP_in || auto_sleep) begin + ram_ce_a_int = 1'b0; + end else begin + ram_ce_a_int = ram_ce_a_pre; + end + end + + reg [15:1] ram_ce_b_fifo_in = 15'b0; + always @ (*) begin + ram_ce_b_fifo_in = 15'b0; + ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int; + end +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + ram_ce_b_fifo <= 15'b0; + end else begin + ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in; + end + end + + always @ (*) begin + if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin + ram_ce_b_pre = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int; + end else begin + ram_ce_b_pre = ram_ce_b_fifo[1]; + end + end + + always @ (*) begin + if (a_sleep || SLEEP_in || auto_sleep) begin + ram_ce_b_int = 1'b0; + end else begin + ram_ce_b_int = ram_ce_b_pre; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_bwe_a <= 72'h00; + end else if (ram_ce_a_int) begin + if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin + ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF; + end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin + ram_bwe_a <= {BWE_A_int[7:0], + {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, + {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; + end else begin + ram_bwe_a <= {{8{BWE_A_int[8]}}, + {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, + {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_bwe_b <= 72'b0; + end else if (ram_ce_b_int) begin + if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin + ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF; + end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin + ram_bwe_b <= {BWE_B_int[7:0], + {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, + {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; + end else begin + ram_bwe_b <= {{8{BWE_B_int[8]}}, + {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, + {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; + end + end + end + + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_addr_a <= 12'b0; + end else if (ram_ce_a_int) begin + ram_addr_a <= ADDR_A_int[11:0]; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_addr_b <= 12'b0; + end else if (ram_ce_b_int) begin + ram_addr_b <= ADDR_B_int[11:0]; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`endif + ram_ce_a <= 1'b0; + end else begin + ram_ce_a <= ram_ce_a_int; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`endif + ram_ce_b <= 1'b0; + end else begin + ram_ce_b <= ram_ce_b_int; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin + ram_we_a <= 1'b0; + end else begin + ram_we_a <= RDB_WR_A_int; + if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin + ram_we_b <= 1'b0; + end else begin + ram_we_b <= RDB_WR_B_int; + if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_data_a <= D_INIT; + end else if (RDB_WR_A_int && ram_ce_a_int) begin + if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin + ram_data_a[63:0] <= {DIN_A_int[63], + DIN_A_int[62] ^ (INJECT_DBITERR_A_int), + DIN_A_int[61:31], + DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), + DIN_A_int[29:0]}; + ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]); + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + ram_data_a[63:0] <= {DIN_A_int[63], + DIN_A_int[62] ^ (INJECT_DBITERR_A_int), + DIN_A_int[61:31], + DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), + DIN_A_int[29:0]}; + ram_data_a[71:64] <= DIN_A_int[71:64]; + end else begin + ram_data_a <= DIN_A_int; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_data_b <= D_INIT; + end else if (RDB_WR_B_int && ram_ce_b_int) begin + if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin + ram_data_b[63:0] <= {DIN_B_int[63], + DIN_B_int[62] ^ (INJECT_DBITERR_B_int), + DIN_B_int[61:31], + DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), + DIN_B_int[29:0]}; + ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]); + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + ram_data_b[63:0] <= {DIN_B_int[63], + DIN_B_int[62] ^ (INJECT_DBITERR_B_int), + DIN_B_int[61:31], + DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), + DIN_B_int[29:0]}; + ram_data_b[71:64] <= DIN_B_int[71:64]; + end else begin + ram_data_b <= DIN_B_int; + end + end + end + +// ram + always @ (*) begin + if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || + (((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) && + (a_sleep || shut_down)))begin + RDACCESS_A_lat <= 1'b0; + end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin + RDACCESS_A_lat <= 1'b1; + end else begin + RDACCESS_A_lat <= 1'b0; + end + end + + always @ (*) begin + if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || + (((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) && + (a_sleep || shut_down)))begin + RDACCESS_B_lat <= 1'b0; + end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin + RDACCESS_B_lat <= 1'b1; + end else begin + RDACCESS_B_lat <= 1'b0; + end + end + +`ifndef XIL_XECLIB +// always @ (posedge INIT_RAM or posedge glblGSR) begin + always @ (posedge INIT_RAM) begin + for (wa=0;wa 0) && + (~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) || + (~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) || + (~SHUTDOWN_in && (wake_count > 3))) begin + wake_count <= wake_count - 1; + end else if (SHUTDOWN_in) begin + wake_count <= 9; + end else if (DEEPSLEEP_in && (wake_count <= 3)) begin + wake_count <= 3; + end else if (SLEEP_in && (wake_count <= 2)) begin + wake_count <= 2; + end else if (auto_sleep && (wake_count <= 1)) begin + wake_count <= 1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (~auto_sleep && wake_count == 1)) begin + a_sleep <= 1'b0; + end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin + a_sleep <= 1'b1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (wake_count == 1)) begin + shut_down <= 1'b0; + end else if (SHUTDOWN_in) begin + shut_down <= 1'b1; + end + end + + assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B; + assign auto_wake_up_A = ram_ce_a_fifo[3]; + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + auto_sleep_A <= 1'b0; + end else if (auto_wake_up_A && auto_sleep_A) begin + auto_sleep_A <= 1'b0; + end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin + auto_sleep_A <= 1'b1; + end + end + + assign auto_wake_up_B = ram_ce_b_fifo[3]; +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + auto_sleep_B <= 1'b0; + end else if (auto_wake_up_B && auto_sleep_B) begin + auto_sleep_B <= 1'b0; + end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin + auto_sleep_B <= 1'b1; + end + end + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + + specify + (ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0); + (ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0); + (BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0); + (BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0); + (CAS_IN_ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0); + (CAS_IN_ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0); + (CAS_IN_BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0); + (CAS_IN_BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0); + (CAS_IN_DBITERR_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_DBITERR_A => DBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_DBITERR_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_DBITERR_B => DBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0); + (CAS_IN_DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0); + (CAS_IN_DOUT_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0); + (CAS_IN_DOUT_A *> DOUT_A) = (0:0:0, 0:0:0); + (CAS_IN_DOUT_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0); + (CAS_IN_DOUT_B *> DOUT_B) = (0:0:0, 0:0:0); + (CAS_IN_EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0); + (CAS_IN_EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A *> DOUT_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => CAS_OUT_RDACCESS_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => DBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => RDACCESS_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_A => SBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B *> DOUT_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => CAS_OUT_RDACCESS_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => DBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => RDACCESS_B) = (0:0:0, 0:0:0); + (CAS_IN_RDACCESS_B => SBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0); + (CAS_IN_RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0); + (CAS_IN_SBITERR_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_SBITERR_A => SBITERR_A) = (0:0:0, 0:0:0); + (CAS_IN_SBITERR_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0); + (CAS_IN_SBITERR_B => SBITERR_B) = (0:0:0, 0:0:0); + (CLK *> CAS_OUT_ADDR_A) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_ADDR_B) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_BWE_A) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_BWE_B) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_DIN_A) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_DIN_B) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_DOUT_A) = (100:100:100, 100:100:100); + (CLK *> CAS_OUT_DOUT_B) = (100:100:100, 100:100:100); + (CLK *> DOUT_A) = (100:100:100, 100:100:100); + (CLK *> DOUT_B) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_DBITERR_A) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_DBITERR_B) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_EN_A) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_EN_B) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_RDACCESS_A) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_RDACCESS_B) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_RDB_WR_A) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_RDB_WR_B) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_SBITERR_A) = (100:100:100, 100:100:100); + (CLK => CAS_OUT_SBITERR_B) = (100:100:100, 100:100:100); + (CLK => DBITERR_A) = (100:100:100, 100:100:100); + (CLK => DBITERR_B) = (100:100:100, 100:100:100); + (CLK => RDACCESS_A) = (100:100:100, 100:100:100); + (CLK => RDACCESS_B) = (100:100:100, 100:100:100); + (CLK => SBITERR_A) = (100:100:100, 100:100:100); + (CLK => SBITERR_B) = (100:100:100, 100:100:100); + (DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0); + (DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0); + (EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0); + (EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0); + (RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0); + (RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0); + (negedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); + $recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); + $recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); + $recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); + $recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); + $recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); + $recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); + $recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); + $setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); + $setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); + $setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); + $setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay); + $setuphold (negedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay); + $setuphold (negedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay); + $setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); + $setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); + $setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); + $setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); + $setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); + $setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); + $setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); + $setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); + $setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); + $setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); + $setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); + $setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); + $setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); + $setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); + $setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay); + $setuphold (negedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay); + $setuphold (negedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay); + $setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); + $setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); + $setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); + $setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); + $setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); + $setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); + $setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); + $setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); + $setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); + $setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); + $setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); + $setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); + $setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); + $setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); + $setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay); + $setuphold (posedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay); + $setuphold (posedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay); + $setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); + $setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); + $setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); + $setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); + $setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); + $setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); + $setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); + $setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); + $setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); + $setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); + $setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); + $setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); + $setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); + $setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); + $setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay); + $setuphold (posedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay); + $setuphold (posedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay); + $setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); + $setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); + $setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); + $setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); + $setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); + $setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); + $setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); + $setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); + $setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); + $setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); + $setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge RST_A, 0:0:0, 0, notifier); + $width (negedge RST_B, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge RST_A, 0:0:0, 0, notifier); + $width (posedge RST_B, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/URAM288_BASE.v b/verilog/src/unisims/URAM288_BASE.v new file mode 100644 index 0000000..dd50660 --- /dev/null +++ b/verilog/src/unisims/URAM288_BASE.v @@ -0,0 +1,2081 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2018 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2018.3 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / 288K-bit High-Density Base Memory Building Block +// /___/ /\ Filename : URAM288_BASE.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// 10/31/2014 - Initial functional version +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module URAM288_BASE #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer AUTO_SLEEP_LATENCY = 8, + parameter integer AVG_CONS_INACTIVE_CYCLES = 10, + parameter BWE_MODE_A = "PARITY_INTERLEAVED", + parameter BWE_MODE_B = "PARITY_INTERLEAVED", + parameter EN_AUTO_SLEEP_MODE = "FALSE", + parameter EN_ECC_RD_A = "FALSE", + parameter EN_ECC_RD_B = "FALSE", + parameter EN_ECC_WR_A = "FALSE", + parameter EN_ECC_WR_B = "FALSE", + parameter IREG_PRE_A = "FALSE", + parameter IREG_PRE_B = "FALSE", + parameter [0:0] IS_CLK_INVERTED = 1'b0, + parameter [0:0] IS_EN_A_INVERTED = 1'b0, + parameter [0:0] IS_EN_B_INVERTED = 1'b0, + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0, + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0, + parameter [0:0] IS_RST_A_INVERTED = 1'b0, + parameter [0:0] IS_RST_B_INVERTED = 1'b0, + parameter OREG_A = "FALSE", + parameter OREG_B = "FALSE", + parameter OREG_ECC_A = "FALSE", + parameter OREG_ECC_B = "FALSE", + parameter RST_MODE_A = "SYNC", + parameter RST_MODE_B = "SYNC", + parameter USE_EXT_CE_A = "FALSE", + parameter USE_EXT_CE_B = "FALSE" +)( + output DBITERR_A, + output DBITERR_B, + output [71:0] DOUT_A, + output [71:0] DOUT_B, + output SBITERR_A, + output SBITERR_B, + + input [22:0] ADDR_A, + input [22:0] ADDR_B, + input [8:0] BWE_A, + input [8:0] BWE_B, + input CLK, + input [71:0] DIN_A, + input [71:0] DIN_B, + input EN_A, + input EN_B, + input INJECT_DBITERR_A, + input INJECT_DBITERR_B, + input INJECT_SBITERR_A, + input INJECT_SBITERR_B, + input OREG_CE_A, + input OREG_CE_B, + input OREG_ECC_CE_A, + input OREG_ECC_CE_B, + input RDB_WR_A, + input RDB_WR_B, + input RST_A, + input RST_B, + input SLEEP +); + +// define constants + localparam MODULE_NAME = "URAM288_BASE"; + +// Parameter encodings and registers + localparam BWE_MODE_A_PARITY_INDEPENDENT = 1; + localparam BWE_MODE_A_PARITY_INTERLEAVED = 0; + localparam BWE_MODE_B_PARITY_INDEPENDENT = 1; + localparam BWE_MODE_B_PARITY_INTERLEAVED = 0; + localparam EN_AUTO_SLEEP_MODE_FALSE = 0; + localparam EN_AUTO_SLEEP_MODE_TRUE = 1; + localparam EN_ECC_RD_A_FALSE = 0; + localparam EN_ECC_RD_A_TRUE = 1; + localparam EN_ECC_RD_B_FALSE = 0; + localparam EN_ECC_RD_B_TRUE = 1; + localparam EN_ECC_WR_A_FALSE = 0; + localparam EN_ECC_WR_A_TRUE = 1; + localparam EN_ECC_WR_B_FALSE = 0; + localparam EN_ECC_WR_B_TRUE = 1; + localparam IREG_PRE_A_FALSE = 0; + localparam IREG_PRE_A_TRUE = 1; + localparam IREG_PRE_B_FALSE = 0; + localparam IREG_PRE_B_TRUE = 1; + localparam OREG_A_FALSE = 0; + localparam OREG_A_TRUE = 1; + localparam OREG_B_FALSE = 0; + localparam OREG_B_TRUE = 1; + localparam OREG_ECC_A_FALSE = 0; + localparam OREG_ECC_A_TRUE = 1; + localparam OREG_ECC_B_FALSE = 0; + localparam OREG_ECC_B_TRUE = 1; + localparam RST_MODE_A_ASYNC = 1; + localparam RST_MODE_A_SYNC = 0; + localparam RST_MODE_B_ASYNC = 1; + localparam RST_MODE_B_SYNC = 0; + localparam USE_EXT_CE_A_FALSE = 0; + localparam USE_EXT_CE_A_TRUE = 1; + localparam USE_EXT_CE_B_FALSE = 0; + localparam USE_EXT_CE_B_TRUE = 1; + + reg trig_attr; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "URAM288_BASE_dr.v" +`else + reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY; + reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES; + reg [144:1] BWE_MODE_A_REG = BWE_MODE_A; + reg [144:1] BWE_MODE_B_REG = BWE_MODE_B; + reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE; + reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A; + reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B; + reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A; + reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B; + reg [40:1] IREG_PRE_A_REG = IREG_PRE_A; + reg [40:1] IREG_PRE_B_REG = IREG_PRE_B; + reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; + reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED; + reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED; + reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED; + reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED; + reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED; + reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED; + reg [40:1] OREG_A_REG = OREG_A; + reg [40:1] OREG_B_REG = OREG_B; + reg [40:1] OREG_ECC_A_REG = OREG_ECC_A; + reg [40:1] OREG_ECC_B_REG = OREG_ECC_B; + reg [40:1] RST_MODE_A_REG = RST_MODE_A; + reg [40:1] RST_MODE_B_REG = RST_MODE_B; + reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A; + reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B; +`endif + +`ifdef XIL_XECLIB + wire [3:0] AUTO_SLEEP_LATENCY_BIN; + wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; + wire BWE_MODE_A_BIN; + wire BWE_MODE_B_BIN; + wire EN_AUTO_SLEEP_MODE_BIN; + wire EN_ECC_RD_A_BIN; + wire EN_ECC_RD_B_BIN; + wire EN_ECC_WR_A_BIN; + wire EN_ECC_WR_B_BIN; + wire IREG_PRE_A_BIN; + wire IREG_PRE_B_BIN; + wire OREG_A_BIN; + wire OREG_B_BIN; + wire OREG_ECC_A_BIN; + wire OREG_ECC_B_BIN; + wire RST_MODE_A_BIN; + wire RST_MODE_B_BIN; + wire USE_EXT_CE_A_BIN; + wire USE_EXT_CE_B_BIN; +`else + reg [3:0] AUTO_SLEEP_LATENCY_BIN; + reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; + reg BWE_MODE_A_BIN; + reg BWE_MODE_B_BIN; + reg EN_AUTO_SLEEP_MODE_BIN; + reg EN_ECC_RD_A_BIN; + reg EN_ECC_RD_B_BIN; + reg EN_ECC_WR_A_BIN; + reg EN_ECC_WR_B_BIN; + reg IREG_PRE_A_BIN; + reg IREG_PRE_B_BIN; + reg OREG_A_BIN; + reg OREG_B_BIN; + reg OREG_ECC_A_BIN; + reg OREG_ECC_B_BIN; + reg RST_MODE_A_BIN; + reg RST_MODE_B_BIN; + reg USE_EXT_CE_A_BIN; + reg USE_EXT_CE_B_BIN; +`endif + +`ifdef XIL_XECLIB + reg glblGSR = 1'b0; +`else + tri0 glblGSR = glbl.GSR; +`endif + + wire CLK_in; + wire EN_A_in; + wire EN_B_in; + wire INJECT_DBITERR_A_in; + wire INJECT_DBITERR_B_in; + wire INJECT_SBITERR_A_in; + wire INJECT_SBITERR_B_in; + wire OREG_CE_A_in; + wire OREG_CE_B_in; + wire OREG_ECC_CE_A_in; + wire OREG_ECC_CE_B_in; + wire RDB_WR_A_in; + wire RDB_WR_B_in; + wire RST_A_in; + wire RST_B_in; + wire SLEEP_in; + wire [22:0] ADDR_A_in; + wire [22:0] ADDR_B_in; + wire [71:0] DIN_A_in; + wire [71:0] DIN_B_in; + wire [8:0] BWE_A_in; + wire [8:0] BWE_B_in; + +`ifdef XIL_TIMING + wire CLK_delay; + wire EN_A_delay; + wire EN_B_delay; + wire INJECT_DBITERR_A_delay; + wire INJECT_DBITERR_B_delay; + wire INJECT_SBITERR_A_delay; + wire INJECT_SBITERR_B_delay; + wire OREG_CE_A_delay; + wire OREG_CE_B_delay; + wire OREG_ECC_CE_A_delay; + wire OREG_ECC_CE_B_delay; + wire RDB_WR_A_delay; + wire RDB_WR_B_delay; + wire RST_A_delay; + wire RST_B_delay; + wire SLEEP_delay; + wire [22:0] ADDR_A_delay; + wire [22:0] ADDR_B_delay; + wire [71:0] DIN_A_delay; + wire [71:0] DIN_B_delay; + wire [8:0] BWE_A_delay; + wire [8:0] BWE_B_delay; +`endif + +`ifdef XIL_TIMING + assign ADDR_A_in = ADDR_A_delay; + assign ADDR_B_in = ADDR_B_delay; + assign BWE_A_in = BWE_A_delay; + assign BWE_B_in = BWE_B_delay; + assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_A_in = DIN_A_delay; + assign DIN_B_in = DIN_B_delay; + assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0 + assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0 + assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0 + assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0 + assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0 + assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0 + assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1 + assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1 + assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1 + assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1 + assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 + assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 + assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0 + assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 +`else + assign ADDR_A_in = ADDR_A; + assign ADDR_B_in = ADDR_B; + assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1 + assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1 + assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1 + assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1 + assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1 + assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1 + assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1 + assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1 + assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1 + assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1 + assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1 + assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1 + assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1 + assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1 + assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1 + assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1 + assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1 + assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1 + assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 + assign DIN_A_in = DIN_A; + assign DIN_B_in = DIN_B; + assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0 + assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0 + assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0 + assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0 + assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0 + assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0 + assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1 + assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1 + assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1 + assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1 + assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 + assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 + assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0 + assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0 + assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 +`endif + +`ifndef XIL_XECLIB + reg attr_test; + reg attr_err; + + initial begin + trig_attr = 1'b0; + `ifdef XIL_ATTR_TEST + attr_test = 1'b1; + `else + attr_test = 1'b0; + `endif + attr_err = 1'b0; + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; + + assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; + + assign BWE_MODE_A_BIN = + (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : + (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : + BWE_MODE_A_PARITY_INTERLEAVED; + + assign BWE_MODE_B_BIN = + (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : + (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : + BWE_MODE_B_PARITY_INTERLEAVED; + + assign EN_AUTO_SLEEP_MODE_BIN = + (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : + (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : + EN_AUTO_SLEEP_MODE_FALSE; + + assign EN_ECC_RD_A_BIN = + (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : + (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : + EN_ECC_RD_A_FALSE; + + assign EN_ECC_RD_B_BIN = + (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : + (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : + EN_ECC_RD_B_FALSE; + + assign EN_ECC_WR_A_BIN = + (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : + (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : + EN_ECC_WR_A_FALSE; + + assign EN_ECC_WR_B_BIN = + (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : + (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : + EN_ECC_WR_B_FALSE; + + assign IREG_PRE_A_BIN = + (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : + (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : + IREG_PRE_A_FALSE; + + assign IREG_PRE_B_BIN = + (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : + (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : + IREG_PRE_B_FALSE; + + assign OREG_A_BIN = + (OREG_A_REG == "FALSE") ? OREG_A_FALSE : + (OREG_A_REG == "TRUE") ? OREG_A_TRUE : + OREG_A_FALSE; + + assign OREG_B_BIN = + (OREG_B_REG == "FALSE") ? OREG_B_FALSE : + (OREG_B_REG == "TRUE") ? OREG_B_TRUE : + OREG_B_FALSE; + + assign OREG_ECC_A_BIN = + (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : + (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : + OREG_ECC_A_FALSE; + + assign OREG_ECC_B_BIN = + (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : + (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : + OREG_ECC_B_FALSE; + + assign RST_MODE_A_BIN = + (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : + (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : + RST_MODE_A_SYNC; + + assign RST_MODE_B_BIN = + (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : + (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : + RST_MODE_B_SYNC; + + assign USE_EXT_CE_A_BIN = + (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : + (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : + USE_EXT_CE_A_FALSE; + + assign USE_EXT_CE_B_BIN = + (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : + (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : + USE_EXT_CE_B_FALSE; + +`else + always @ (trig_attr) begin + #1; + AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; + + AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; + + BWE_MODE_A_BIN = + (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : + (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : + BWE_MODE_A_PARITY_INTERLEAVED; + + BWE_MODE_B_BIN = + (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : + (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : + BWE_MODE_B_PARITY_INTERLEAVED; + + EN_AUTO_SLEEP_MODE_BIN = + (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : + (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : + EN_AUTO_SLEEP_MODE_FALSE; + + EN_ECC_RD_A_BIN = + (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : + (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : + EN_ECC_RD_A_FALSE; + + EN_ECC_RD_B_BIN = + (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : + (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : + EN_ECC_RD_B_FALSE; + + EN_ECC_WR_A_BIN = + (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : + (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : + EN_ECC_WR_A_FALSE; + + EN_ECC_WR_B_BIN = + (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : + (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : + EN_ECC_WR_B_FALSE; + + IREG_PRE_A_BIN = + (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : + (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : + IREG_PRE_A_FALSE; + + IREG_PRE_B_BIN = + (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : + (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : + IREG_PRE_B_FALSE; + + OREG_A_BIN = + (OREG_A_REG == "FALSE") ? OREG_A_FALSE : + (OREG_A_REG == "TRUE") ? OREG_A_TRUE : + OREG_A_FALSE; + + OREG_B_BIN = + (OREG_B_REG == "FALSE") ? OREG_B_FALSE : + (OREG_B_REG == "TRUE") ? OREG_B_TRUE : + OREG_B_FALSE; + + OREG_ECC_A_BIN = + (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : + (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : + OREG_ECC_A_FALSE; + + OREG_ECC_B_BIN = + (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : + (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : + OREG_ECC_B_FALSE; + + RST_MODE_A_BIN = + (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : + (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : + RST_MODE_A_SYNC; + + RST_MODE_B_BIN = + (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : + (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : + RST_MODE_B_SYNC; + + USE_EXT_CE_A_BIN = + (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : + (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : + USE_EXT_CE_A_FALSE; + + USE_EXT_CE_B_BIN = + (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : + (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : + USE_EXT_CE_B_FALSE; + + end +`endif + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((AUTO_SLEEP_LATENCY_REG != 8) && + (AUTO_SLEEP_LATENCY_REG != 3) && + (AUTO_SLEEP_LATENCY_REG != 4) && + (AUTO_SLEEP_LATENCY_REG != 5) && + (AUTO_SLEEP_LATENCY_REG != 6) && + (AUTO_SLEEP_LATENCY_REG != 7) && + (AUTO_SLEEP_LATENCY_REG != 9) && + (AUTO_SLEEP_LATENCY_REG != 10) && + (AUTO_SLEEP_LATENCY_REG != 11) && + (AUTO_SLEEP_LATENCY_REG != 12) && + (AUTO_SLEEP_LATENCY_REG != 13) && + (AUTO_SLEEP_LATENCY_REG != 14) && + (AUTO_SLEEP_LATENCY_REG != 15))) begin + $display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin + $display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BWE_MODE_A_REG != "PARITY_INTERLEAVED") && + (BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin + $display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((BWE_MODE_B_REG != "PARITY_INTERLEAVED") && + (BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin + $display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG != "FALSE") && + (EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin + $display("Error: [Unisim %s-105] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_RD_A_REG != "FALSE") && + (EN_ECC_RD_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-106] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_RD_B_REG != "FALSE") && + (EN_ECC_RD_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-107] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_WR_A_REG != "FALSE") && + (EN_ECC_WR_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-108] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_ECC_WR_B_REG != "FALSE") && + (EN_ECC_WR_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-109] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IREG_PRE_A_REG != "FALSE") && + (IREG_PRE_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-110] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((IREG_PRE_B_REG != "FALSE") && + (IREG_PRE_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-111] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_A_REG != "FALSE") && + (OREG_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-123] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_B_REG != "FALSE") && + (OREG_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-124] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_ECC_A_REG != "FALSE") && + (OREG_ECC_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-125] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((OREG_ECC_B_REG != "FALSE") && + (OREG_ECC_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-126] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RST_MODE_A_REG != "SYNC") && + (RST_MODE_A_REG != "ASYNC"))) begin + $display("Error: [Unisim %s-127] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((RST_MODE_B_REG != "SYNC") && + (RST_MODE_B_REG != "ASYNC"))) begin + $display("Error: [Unisim %s-128] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_EXT_CE_A_REG != "FALSE") && + (USE_EXT_CE_A_REG != "TRUE"))) begin + $display("Error: [Unisim %s-129] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((USE_EXT_CE_B_REG != "FALSE") && + (USE_EXT_CE_B_REG != "TRUE"))) begin + $display("Error: [Unisim %s-130] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + end +`endif + +`ifdef XIL_TIMING + reg notifier; +`endif + +// begin behavioral model +// define tasks, functions + +function [7:0] fn_ecc ( + input encode, + input [63:0] d_i, + input [7:0] dp_i + ); + reg ecc_7; +begin + fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^ + d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^ + d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^ + d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^ + d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^ + d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^ + d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63]; + + fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^ + d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^ + d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^ + d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^ + d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^ + d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^ + d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63]; + + fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ + d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^ + d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ + d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ + d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ + d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ + d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ + d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ + d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ + d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ + d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ + d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ + d_i[56]; + + fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ + d_i[62] ^ d_i[63]; + + ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^ + d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ + d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ + d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ + d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ + d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ + d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ + d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ + d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ + d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ + d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ + d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^ + d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; + + if (encode) begin + fn_ecc[7] = ecc_7 ^ + fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^ + fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6]; + end + else begin + fn_ecc[7] = ecc_7 ^ + dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^ + dp_i[4] ^ dp_i[5] ^ dp_i[6]; + end +end +endfunction // fn_ecc + +function [71:0] fn_cor_bit ( + input [6:0] error_bit, + input [63:0] d_i, + input [7:0] dp_i + ); + reg [71:0] cor_int; +begin + cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4], + d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0], + dp_i[7]}; + cor_int[error_bit] = ~cor_int[error_bit]; + fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16], + cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65], + cor_int[63:33], cor_int[31:17], cor_int[15:9], + cor_int[7:5], cor_int[3]}; +end +endfunction // fn_cor_bit + +`ifndef XIL_XECLIB + always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && + (USE_EXT_CE_A_REG == "TRUE"))) begin + $display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && + (USE_EXT_CE_B_REG == "TRUE"))) begin + $display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; + + end +`endif + + localparam mem_width = 72; + localparam mem_depth = 4 * 1024; + localparam encode = 1'b1; + localparam decode = 1'b0; + localparam [22:0] ADDR_INIT = 23'b0; + localparam [8:0] BWE_INIT = 9'b0; + localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}}; + localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}}; + + reg [mem_width-1 : 0 ] mem [0 : mem_depth-1]; + + integer wa; + reg [11:0] ram_addr_a; + reg [11:0] ram_addr_b; + reg ram_ce_a; + reg ram_ce_b; + reg DEEPSLEEP_in = 1'b0; + reg SHUTDOWN_in = 1'b0; + reg ram_ce_a_int=0; + reg ram_ce_b_int=0; + reg ram_ce_a_pre=0; + reg ram_ce_b_pre=0; + reg [15:1] ram_ce_a_fifo; + reg [15:1] ram_ce_b_fifo; + reg [71:0] ram_bwe_a; + reg [71:0] ram_bwe_b; + reg ram_we_a; + reg ram_we_b; + reg ram_we_a_event = 1'b0; + reg ram_we_b_event = 1'b0; + reg [71:0] ram_data_a; + reg [71:0] ram_data_b; + +// input register stages +// decisions simulate faster than assignments - wider muxes, less busses + reg [22:0] ADDR_A_reg; + reg [22:0] ADDR_B_reg; + reg [8:0] BWE_A_reg; + reg [8:0] BWE_B_reg; + reg [71:0] DIN_A_reg; + reg [71:0] DIN_B_reg; + reg EN_A_reg; + reg EN_B_reg; + reg INJECT_DBITERR_A_reg; + reg INJECT_DBITERR_B_reg; + reg INJECT_SBITERR_A_reg; + reg INJECT_SBITERR_B_reg; + reg RDB_WR_A_reg; + reg RDB_WR_B_reg; + reg [22:0] ADDR_A_int; + reg [22:0] ADDR_B_int; + reg [8:0] BWE_A_int; + reg [8:0] BWE_B_int; + reg [71:0] DIN_A_int; + reg [71:0] DIN_B_int; + reg EN_A_int; + reg EN_B_int; + reg INJECT_DBITERR_A_int; + reg INJECT_DBITERR_B_int; + reg INJECT_SBITERR_A_int; + reg INJECT_SBITERR_B_int; + reg RDB_WR_A_int; + reg RDB_WR_B_int; + + reg RST_A_async = 1'b0; + reg RST_B_async = 1'b0; + reg RST_A_sync = 1'b0; + reg RST_B_sync = 1'b0; + + integer wake_count; + wire auto_sleep; + reg shut_down; + reg a_sleep; + reg auto_sleep_A; + reg auto_sleep_B; + wire auto_wake_up_A; + wire auto_wake_up_B; + + reg DBITERR_A_out; + reg DBITERR_B_out; + reg SBITERR_A_out; + reg SBITERR_B_out; + reg [71:0] DOUT_A_out; + reg [71:0] DOUT_B_out; + + assign DBITERR_A = DBITERR_A_out; + assign DBITERR_B = DBITERR_B_out; + assign DOUT_A = DOUT_A_out; + assign DOUT_B = DOUT_B_out; + assign SBITERR_A = SBITERR_A_out; + assign SBITERR_B = SBITERR_B_out; + +`ifndef XIL_XECLIB + reg INIT_RAM = 1'b0; + initial begin + #100; INIT_RAM = 1'b1; + end +`endif + + always @ (*) begin + if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin + RST_A_async = RST_A_in; + end + end + + always @ (*) begin + if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin + RST_B_async = RST_B_in; + end + end + + always @ (posedge CLK_in) begin + if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in)) + RST_A_sync <= RST_A_in; + if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in)) + RST_B_sync <= RST_B_in; + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || + (IREG_PRE_A_BIN == IREG_PRE_A_FALSE)) begin + ADDR_A_reg <= ADDR_INIT; + EN_A_reg <= 1'b0; + RDB_WR_A_reg <= 1'b0; + BWE_A_reg <= BWE_INIT; + DIN_A_reg <= D_INIT; + INJECT_DBITERR_A_reg <= 1'b0; + INJECT_SBITERR_A_reg <= 1'b0; + end else begin + EN_A_reg <= EN_A_in; + if (EN_A_in) begin + ADDR_A_reg[22:12] <= ADDR_A_in[22:12]; + end + if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_A_reg[11:0] <= ADDR_A_in[11:0]; + BWE_A_reg <= BWE_A_in; + DIN_A_reg <= DIN_A_in; + INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in; + INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in; + RDB_WR_A_reg <= RDB_WR_A_in; + end + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + ADDR_A_int = ADDR_A_reg; + end else begin + ADDR_A_int = ADDR_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + BWE_A_int = BWE_A_reg; + end else begin + BWE_A_int = BWE_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + DIN_A_int = DIN_A_reg; + end else begin + DIN_A_int = DIN_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + EN_A_int = EN_A_reg; + end else begin + EN_A_int = EN_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg; + end else begin + INJECT_DBITERR_A_int = INJECT_DBITERR_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg; + end else begin + INJECT_SBITERR_A_int = INJECT_SBITERR_A_in; + end + end + + always @ (*) begin + if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin + RDB_WR_A_int = RDB_WR_A_reg; + end else begin + RDB_WR_A_int = RDB_WR_A_in; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || + (IREG_PRE_B_BIN == IREG_PRE_B_FALSE)) begin + ADDR_B_reg <= ADDR_INIT; + EN_B_reg <= 1'b0; + RDB_WR_B_reg <= 1'b0; + BWE_B_reg <= BWE_INIT; + DIN_B_reg <= D_INIT; + INJECT_DBITERR_B_reg <= 1'b0; + INJECT_SBITERR_B_reg <= 1'b0; + end else begin + EN_B_reg <= EN_B_in; + if (EN_B_in) begin + ADDR_B_reg[22:12] <= ADDR_B_in[22:12]; + end + if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin + ADDR_B_reg[11:0] <= ADDR_B_in[11:0]; + BWE_B_reg <= BWE_B_in; + DIN_B_reg <= DIN_B_in; + INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in; + INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in; + RDB_WR_B_reg <= RDB_WR_B_in; + end + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + ADDR_B_int = ADDR_B_reg; + end else begin + ADDR_B_int = ADDR_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + BWE_B_int = BWE_B_reg; + end else begin + BWE_B_int = BWE_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + DIN_B_int = DIN_B_reg; + end else begin + DIN_B_int = DIN_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + EN_B_int = EN_B_reg; + end else begin + EN_B_int = EN_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg; + end else begin + INJECT_DBITERR_B_int = INJECT_DBITERR_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg; + end else begin + INJECT_SBITERR_B_int = INJECT_SBITERR_B_in; + end + end + + always @ (*) begin + if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin + RDB_WR_B_int = RDB_WR_B_reg; + end else begin + RDB_WR_B_int = RDB_WR_B_in; + end + end + + reg [71:0] ram_data_a_lat; + reg [71:0] ram_data_a_out; +// reg [71:0] ram_data_a_hold=D_INIT; + reg [71:0] ram_data_a_reg; + reg [71:0] ram_data_a_ecc=72'h000000000000000000; + reg [71:0] ram_data_b_lat; + reg [71:0] ram_data_b_out; + reg [71:0] ram_data_b_reg; + reg [71:0] ram_data_b_ecc=72'h000000000000000000; + reg RDACCESS_A_lat; +// reg RDACCESS_A_hold; + reg RDACCESS_B_lat; + reg RDACCESS_A_int; + reg RDACCESS_B_int; + reg SBITERR_A_ecc=1'b0; + reg DBITERR_A_ecc=1'b0; + reg SBITERR_B_ecc=1'b0; + reg DBITERR_B_ecc=1'b0; + + reg DBITERR_A_reg; + reg DBITERR_B_reg; + reg [71:0] DOUT_A_reg; + reg [71:0] DOUT_B_reg; + reg RDACCESS_A_reg; + reg RDACCESS_B_reg; + reg SBITERR_A_reg; + reg SBITERR_B_reg; + + reg RDACCESS_A_ecc_reg; + reg RDACCESS_B_ecc_reg; + + reg data_A_enable = 1'b0; + reg data_B_enable = 1'b0; + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || +`endif + shut_down || SHUTDOWN_in) begin + RDACCESS_A_int = 1'b0; + end else begin + if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin + RDACCESS_A_int = RDACCESS_A_ecc_reg; + end else begin + RDACCESS_A_int = 1'b0; + end + end else if (OREG_A_BIN == OREG_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin + RDACCESS_A_int = RDACCESS_A_reg; + end else begin + RDACCESS_A_int = 1'b0; + end + end else begin + RDACCESS_A_int = RDACCESS_A_lat; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || +`endif + shut_down || SHUTDOWN_in) begin + RDACCESS_B_int = 1'b0; + end else begin + if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin + RDACCESS_B_int = RDACCESS_B_ecc_reg; + end else begin + RDACCESS_B_int = 1'b0; + end + end else if (OREG_B_BIN == OREG_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin + RDACCESS_B_int = RDACCESS_B_reg; + end else begin + RDACCESS_B_int = 1'b0; + end + end else begin + RDACCESS_B_int = RDACCESS_B_lat; + end + end + end + + always @ (*) begin + if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin + DBITERR_A_out = 1'b0; + SBITERR_A_out = 1'b0; + end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + DBITERR_A_out = DBITERR_A_reg; + SBITERR_A_out = SBITERR_A_reg; + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DBITERR_A_out = DBITERR_A_ecc; + SBITERR_A_out = SBITERR_A_ecc; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`endif + data_A_enable <= 1'b0; + end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin + data_A_enable <= 1'b1; + end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin + data_A_enable <= 1'b1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin +`endif + data_B_enable <= 1'b0; + end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin + data_B_enable <= 1'b1; + end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin + data_B_enable <= 1'b1; + end + end + + always @ (posedge CLK_in) begin + if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin + $display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG); + end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin + $display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin + $display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin + $display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); + end + end + + always @ (posedge CLK_in) begin + if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin + $display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG); + end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin + $display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin + $display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin + $display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); + end + end + + always @ (*) begin + if (RST_A_async || RST_A_sync || glblGSR) begin + DOUT_A_out = D_INIT; + end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin + DOUT_A_out = DOUT_A_reg; + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DOUT_A_out = ram_data_a_ecc; + end else if (data_A_enable) begin + if (OREG_A_BIN == OREG_A_TRUE) begin + DOUT_A_out = ram_data_a_reg; + end else begin + DOUT_A_out = ram_data_a_lat; + end + end else begin + DOUT_A_out = D_INIT; + end + end + + always @ (*) begin + if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin + DBITERR_B_out = 1'b0; + SBITERR_B_out = 1'b0; + end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + DBITERR_B_out = DBITERR_B_reg; + SBITERR_B_out = SBITERR_B_reg; + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DBITERR_B_out = DBITERR_B_ecc; + SBITERR_B_out = SBITERR_B_ecc; + end + end + + always @ (*) begin + if (RST_B_async || RST_B_sync || glblGSR) begin + DOUT_B_out = D_INIT; + end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin + DOUT_B_out = DOUT_B_reg; + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DOUT_B_out = ram_data_b_ecc; + end else if (data_B_enable) begin + if (OREG_B_BIN == OREG_B_TRUE) begin + DOUT_B_out = ram_data_b_reg; + end else begin + DOUT_B_out = ram_data_b_lat; + end + end else begin + DOUT_B_out = D_INIT; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + DBITERR_A_reg <= 1'b0; + SBITERR_A_reg <= 1'b0; + end else if ((~a_sleep && ~shut_down && data_A_enable) && + (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || + ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin + if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin + DBITERR_A_reg <= DBITERR_A_ecc; + SBITERR_A_reg <= SBITERR_A_ecc; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + DOUT_A_reg <= D_INIT; + end else if (~shut_down && data_A_enable) begin + if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || + ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin + if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + DOUT_A_reg <= ram_data_a_ecc; + end else if (OREG_A_BIN == OREG_A_TRUE) begin + DOUT_A_reg <= ram_data_a_reg; + end else begin + DOUT_A_reg <= ram_data_a_lat; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin +`endif + RDACCESS_A_ecc_reg <= 1'b0; + end else begin + if (OREG_A_BIN == OREG_A_TRUE) begin + if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin + RDACCESS_A_ecc_reg <= RDACCESS_A_reg; + end + end else begin + RDACCESS_A_ecc_reg <= RDACCESS_A_lat; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + DBITERR_B_reg <= 1'b0; + SBITERR_B_reg <= 1'b0; + end else if ((~a_sleep && ~shut_down && data_B_enable) && + (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || + ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin + if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin + DBITERR_B_reg <= DBITERR_B_ecc; + SBITERR_B_reg <= SBITERR_B_ecc; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + DOUT_B_reg <= D_INIT; + end else if (~shut_down && data_B_enable) begin + if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || + ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin + if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + DOUT_B_reg <= ram_data_b_ecc; + end else if (OREG_B_BIN == OREG_B_TRUE) begin + DOUT_B_reg <= ram_data_b_reg; + end else begin + DOUT_B_reg <= ram_data_b_lat; + end + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin +`endif + RDACCESS_B_ecc_reg <= 1'b0; + end else begin + if (OREG_B_BIN == OREG_B_TRUE) begin + if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin + RDACCESS_B_ecc_reg <= RDACCESS_B_reg; + end + end else begin + RDACCESS_B_ecc_reg <= RDACCESS_B_lat; + end + end + end + +// ram oreg +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin + if (RST_A_in || shut_down || a_sleep || glblGSR) begin +`endif + RDACCESS_A_reg <= 1'b0; + end else begin + RDACCESS_A_reg <= RDACCESS_A_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin + if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin +`endif + ram_data_a_reg <= D_INIT; + end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin + if (OREG_CE_A_in) begin + ram_data_a_reg = ram_data_a_lat; + end + end else if (ram_ce_a_int || RDACCESS_A_reg) begin + ram_data_a_reg = ram_data_a_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin + if (RST_B_in || shut_down || a_sleep || glblGSR) begin +`endif + RDACCESS_B_reg <= 1'b0; + end else begin + RDACCESS_B_reg <= RDACCESS_B_lat; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin + if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin +`endif + ram_data_b_reg <= D_INIT; + end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin + if (OREG_CE_B_in) begin + ram_data_b_reg = ram_data_b_lat; + end + end else if (ram_ce_b_int || RDACCESS_B_reg) begin + ram_data_b_reg = ram_data_b_lat; + end + end + + reg [15:1] ram_ce_a_fifo_in = 15'b0; + always @ (*) begin + ram_ce_a_fifo_in = 15'b0; + ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = EN_A_int; + end +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + ram_ce_a_fifo <= 15'b0; + end else begin + ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in; + end + end + + always @ (*) begin + if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin + ram_ce_a_pre = EN_A_int; + end else begin + ram_ce_a_pre = ram_ce_a_fifo[1]; + end + end + + always @ (*) begin + if (a_sleep || SLEEP_in || auto_sleep) begin + ram_ce_a_int = 1'b0; + end else begin + ram_ce_a_int = ram_ce_a_pre; + end + end + + reg [15:1] ram_ce_b_fifo_in = 15'b0; + always @ (*) begin + ram_ce_b_fifo_in = 15'b0; + ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = EN_B_int; + end +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + ram_ce_b_fifo <= 15'b0; + end else begin + ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in; + end + end + + always @ (*) begin + if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin + ram_ce_b_pre = EN_B_int; + end else begin + ram_ce_b_pre = ram_ce_b_fifo[1]; + end + end + + always @ (*) begin + if (a_sleep || SLEEP_in || auto_sleep) begin + ram_ce_b_int = 1'b0; + end else begin + ram_ce_b_int = ram_ce_b_pre; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_bwe_a <= 72'h00; + end else if (ram_ce_a_int) begin + if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin + ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF; + end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin + ram_bwe_a <= {BWE_A_int[7:0], + {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, + {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; + end else begin + ram_bwe_a <= {{8{BWE_A_int[8]}}, + {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, + {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_bwe_b <= 72'b0; + end else if (ram_ce_b_int) begin + if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin + ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF; + end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin + ram_bwe_b <= {BWE_B_int[7:0], + {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, + {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; + end else begin + ram_bwe_b <= {{8{BWE_B_int[8]}}, + {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, + {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; + end + end + end + + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_addr_a <= 12'b0; + end else if (ram_ce_a_int) begin + ram_addr_a <= ADDR_A_int[11:0]; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_addr_b <= 12'b0; + end else if (ram_ce_b_int) begin + ram_addr_b <= ADDR_B_int[11:0]; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_A_async) begin + if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`else + always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin + if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`endif + ram_ce_a <= 1'b0; + end else begin + ram_ce_a <= ram_ce_a_int; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in or posedge RST_B_async) begin + if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`else + always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin + if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin +`endif + ram_ce_b <= 1'b0; + end else begin + ram_ce_b <= ram_ce_b_int; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin + ram_we_a <= 1'b0; + end else begin + ram_we_a <= RDB_WR_A_int; + if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin + ram_we_b <= 1'b0; + end else begin + ram_we_b <= RDB_WR_B_int; + if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_data_a <= D_INIT; + end else if (RDB_WR_A_int && ram_ce_a_int) begin + if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin + ram_data_a[63:0] <= {DIN_A_int[63], + DIN_A_int[62] ^ (INJECT_DBITERR_A_int), + DIN_A_int[61:31], + DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), + DIN_A_int[29:0]}; + ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]); + end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin + ram_data_a[63:0] <= {DIN_A_int[63], + DIN_A_int[62] ^ (INJECT_DBITERR_A_int), + DIN_A_int[61:31], + DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), + DIN_A_int[29:0]}; + ram_data_a[71:64] <= DIN_A_int[71:64]; + end else begin + ram_data_a <= DIN_A_int; + end + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin + ram_data_b <= D_INIT; + end else if (RDB_WR_B_int && ram_ce_b_int) begin + if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin + ram_data_b[63:0] <= {DIN_B_int[63], + DIN_B_int[62] ^ (INJECT_DBITERR_B_int), + DIN_B_int[61:31], + DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), + DIN_B_int[29:0]}; + ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]); + end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin + ram_data_b[63:0] <= {DIN_B_int[63], + DIN_B_int[62] ^ (INJECT_DBITERR_B_int), + DIN_B_int[61:31], + DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), + DIN_B_int[29:0]}; + ram_data_b[71:64] <= DIN_B_int[71:64]; + end else begin + ram_data_b <= DIN_B_int; + end + end + end + +// ram + always @ (*) begin + if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || + (((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) && + (a_sleep || shut_down)))begin + RDACCESS_A_lat <= 1'b0; + end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin + RDACCESS_A_lat <= 1'b1; + end else begin + RDACCESS_A_lat <= 1'b0; + end + end + + always @ (*) begin + if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || + (((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) && + (a_sleep || shut_down)))begin + RDACCESS_B_lat <= 1'b0; + end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin + RDACCESS_B_lat <= 1'b1; + end else begin + RDACCESS_B_lat <= 1'b0; + end + end + +`ifndef XIL_XECLIB +// always @ (posedge INIT_RAM or posedge glblGSR) begin + always @ (posedge INIT_RAM) begin + for (wa=0;wa 0) && + (~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) || + (~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) || + (~SHUTDOWN_in && (wake_count > 3))) begin + wake_count <= wake_count - 1; + end else if (SHUTDOWN_in) begin + wake_count <= 9; + end else if (DEEPSLEEP_in && (wake_count <= 3)) begin + wake_count <= 3; + end else if (SLEEP_in && (wake_count <= 2)) begin + wake_count <= 2; + end else if (auto_sleep && (wake_count <= 1)) begin + wake_count <= 1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (~auto_sleep && wake_count == 1)) begin + a_sleep <= 1'b0; + end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin + a_sleep <= 1'b1; + end + end + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (wake_count == 1)) begin + shut_down <= 1'b0; + end else if (SHUTDOWN_in) begin + shut_down <= 1'b1; + end + end + + assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B; + assign auto_wake_up_A = ram_ce_a_fifo[3]; + +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + auto_sleep_A <= 1'b0; + end else if (auto_wake_up_A && auto_sleep_A) begin + auto_sleep_A <= 1'b0; + end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin + auto_sleep_A <= 1'b1; + end + end + + assign auto_wake_up_B = ram_ce_b_fifo[3]; +`ifdef XIL_XECLIB + always @ (posedge CLK_in) begin +`else + always @ (posedge CLK_in or glblGSR) begin +`endif + if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin + auto_sleep_B <= 1'b0; + end else if (auto_wake_up_B && auto_sleep_B) begin + auto_sleep_B <= 1'b0; + end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin + auto_sleep_B <= 1'b1; + end + end + +// end behavioral model + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + + wire clk_en_n; + wire clk_en_p; + + assign clk_en_n = IS_CLK_INVERTED_REG; + assign clk_en_p = ~IS_CLK_INVERTED_REG; + +`endif + + specify + (CLK *> DOUT_A) = (100:100:100, 100:100:100); + (CLK *> DOUT_B) = (100:100:100, 100:100:100); + (CLK => DBITERR_A) = (100:100:100, 100:100:100); + (CLK => DBITERR_B) = (100:100:100, 100:100:100); + (CLK => SBITERR_A) = (100:100:100, 100:100:100); + (CLK => SBITERR_B) = (100:100:100, 100:100:100); + (negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); + (posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge CLK, 0:0:0, notifier); + $period (posedge CLK, 0:0:0, notifier); + $recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); + $recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); + $recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); + $recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); + $recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); + $recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); + $recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); + $recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); + $setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); + $setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); + $setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); + $setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); + $setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); + $setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); + $setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); + $setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); + $setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); + $setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); + $setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); + $setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); + $setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); + $setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); + $setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); + $setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); + $setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); + $setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); + $setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); + $setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); + $setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); + $setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); + $setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); + $setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); + $setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); + $setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); + $setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); + $setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); + $setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); + $setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); + $setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); + $setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); + $setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); + $setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); + $setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); + $setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); + $setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); + $setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); + $setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); + $setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); + $setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); + $setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); + $setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); + $setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); + $setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); + $setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); + $setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); + $setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); + $setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); + $setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); + $setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); + $setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); + $setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); + $setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); + $setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); + $setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); + $setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); + $setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); + $setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); + $setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); + $setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); + $setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); + $setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); + $setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); + $setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); + $setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); + $width (negedge CLK, 0:0:0, 0, notifier); + $width (negedge RST_A, 0:0:0, 0, notifier); + $width (negedge RST_B, 0:0:0, 0, notifier); + $width (posedge CLK, 0:0:0, 0, notifier); + $width (posedge RST_A, 0:0:0, 0, notifier); + $width (posedge RST_B, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/USR_ACCESSE2.v b/verilog/src/unisims/USR_ACCESSE2.v new file mode 100644 index 0000000..7f57a27 --- /dev/null +++ b/verilog/src/unisims/USR_ACCESSE2.v @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 12.1 +// \ \ Description : +// / / +// /__/ /\ Filename : USR_ACCESSE2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module USR_ACCESSE2 ( + CFGCLK, + DATA, + DATAVALID +); + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif // + + output CFGCLK; + output DATAVALID; + output [31:0] DATA; + + specify + + specparam PATHPULSE$ = 0; + endspecify +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/VCC.v b/verilog/src/unisims/VCC.v new file mode 100644 index 0000000..c1375b1 --- /dev/null +++ b/verilog/src/unisims/VCC.v @@ -0,0 +1,54 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / VCC Connection +// /___/ /\ Filename : VCC.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// End Revision + +`timescale 1 ps / 1 ps + + +`celldefine + +module VCC(P); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output P; + + assign P = 1'b1; + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/VCU.v b/verilog/src/unisims/VCU.v new file mode 100644 index 0000000..17222a6 --- /dev/null +++ b/verilog/src/unisims/VCU.v @@ -0,0 +1,4936 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2017 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2017.1 +// \ \ Description : Xilinx Unified Simulation Library Component +// / / VCU +// /___/ /\ Filename : VCU.v +// \ \ / \ +// \___\/\___\ +// +/////////////////////////////////////////////////////////////////////////////// +// Revision: +// +// End Revision: +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`celldefine + +module VCU #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif + parameter integer CORECLKREQ = 667, + parameter integer DECHORRESOLUTION = 3840, + parameter DECODERCHROMAFORMAT = "4_2_2", + parameter DECODERCODING = "H.265", + parameter integer DECODERCOLORDEPTH = 10, + parameter integer DECODERNUMCORES = 2, + parameter integer DECVERTRESOLUTION = 2160, + parameter ENABLEDECODER = "TRUE", + parameter ENABLEENCODER = "TRUE", + parameter integer ENCHORRESOLUTION = 3840, + parameter ENCODERCHROMAFORMAT = "4_2_2", + parameter ENCODERCODING = "H.265", + parameter integer ENCODERCOLORDEPTH = 10, + parameter integer ENCODERNUMCORES = 4, + parameter integer ENCVERTRESOLUTION = 2160 +)( + output VCUPLARREADYAXILITEAPB, + output VCUPLAWREADYAXILITEAPB, + output [1:0] VCUPLBRESPAXILITEAPB, + output VCUPLBVALIDAXILITEAPB, + output VCUPLCORESTATUSCLKPLL, + output [43:0] VCUPLDECARADDR0, + output [43:0] VCUPLDECARADDR1, + output [1:0] VCUPLDECARBURST0, + output [1:0] VCUPLDECARBURST1, + output [3:0] VCUPLDECARCACHE0, + output [3:0] VCUPLDECARCACHE1, + output [3:0] VCUPLDECARID0, + output [3:0] VCUPLDECARID1, + output [7:0] VCUPLDECARLEN0, + output [7:0] VCUPLDECARLEN1, + output VCUPLDECARPROT0, + output VCUPLDECARPROT1, + output [3:0] VCUPLDECARQOS0, + output [3:0] VCUPLDECARQOS1, + output [2:0] VCUPLDECARSIZE0, + output [2:0] VCUPLDECARSIZE1, + output VCUPLDECARVALID0, + output VCUPLDECARVALID1, + output [43:0] VCUPLDECAWADDR0, + output [43:0] VCUPLDECAWADDR1, + output [1:0] VCUPLDECAWBURST0, + output [1:0] VCUPLDECAWBURST1, + output [3:0] VCUPLDECAWCACHE0, + output [3:0] VCUPLDECAWCACHE1, + output [3:0] VCUPLDECAWID0, + output [3:0] VCUPLDECAWID1, + output [7:0] VCUPLDECAWLEN0, + output [7:0] VCUPLDECAWLEN1, + output VCUPLDECAWPROT0, + output VCUPLDECAWPROT1, + output [3:0] VCUPLDECAWQOS0, + output [3:0] VCUPLDECAWQOS1, + output [2:0] VCUPLDECAWSIZE0, + output [2:0] VCUPLDECAWSIZE1, + output VCUPLDECAWVALID0, + output VCUPLDECAWVALID1, + output VCUPLDECBREADY0, + output VCUPLDECBREADY1, + output VCUPLDECRREADY0, + output VCUPLDECRREADY1, + output [127:0] VCUPLDECWDATA0, + output [127:0] VCUPLDECWDATA1, + output VCUPLDECWLAST0, + output VCUPLDECWLAST1, + output VCUPLDECWVALID0, + output VCUPLDECWVALID1, + output [16:0] VCUPLENCALL2CADDR, + output VCUPLENCALL2CRVALID, + output [319:0] VCUPLENCALL2CWDATA, + output VCUPLENCALL2CWVALID, + output [43:0] VCUPLENCARADDR0, + output [43:0] VCUPLENCARADDR1, + output [1:0] VCUPLENCARBURST0, + output [1:0] VCUPLENCARBURST1, + output [3:0] VCUPLENCARCACHE0, + output [3:0] VCUPLENCARCACHE1, + output [3:0] VCUPLENCARID0, + output [3:0] VCUPLENCARID1, + output [7:0] VCUPLENCARLEN0, + output [7:0] VCUPLENCARLEN1, + output VCUPLENCARPROT0, + output VCUPLENCARPROT1, + output [3:0] VCUPLENCARQOS0, + output [3:0] VCUPLENCARQOS1, + output [2:0] VCUPLENCARSIZE0, + output [2:0] VCUPLENCARSIZE1, + output VCUPLENCARVALID0, + output VCUPLENCARVALID1, + output [43:0] VCUPLENCAWADDR0, + output [43:0] VCUPLENCAWADDR1, + output [1:0] VCUPLENCAWBURST0, + output [1:0] VCUPLENCAWBURST1, + output [3:0] VCUPLENCAWCACHE0, + output [3:0] VCUPLENCAWCACHE1, + output [3:0] VCUPLENCAWID0, + output [3:0] VCUPLENCAWID1, + output [7:0] VCUPLENCAWLEN0, + output [7:0] VCUPLENCAWLEN1, + output VCUPLENCAWPROT0, + output VCUPLENCAWPROT1, + output [3:0] VCUPLENCAWQOS0, + output [3:0] VCUPLENCAWQOS1, + output [2:0] VCUPLENCAWSIZE0, + output [2:0] VCUPLENCAWSIZE1, + output VCUPLENCAWVALID0, + output VCUPLENCAWVALID1, + output VCUPLENCBREADY0, + output VCUPLENCBREADY1, + output VCUPLENCRREADY0, + output VCUPLENCRREADY1, + output [127:0] VCUPLENCWDATA0, + output [127:0] VCUPLENCWDATA1, + output VCUPLENCWLAST0, + output VCUPLENCWLAST1, + output VCUPLENCWVALID0, + output VCUPLENCWVALID1, + output [43:0] VCUPLMCUMAXIICDCARADDR, + output [1:0] VCUPLMCUMAXIICDCARBURST, + output [3:0] VCUPLMCUMAXIICDCARCACHE, + output [2:0] VCUPLMCUMAXIICDCARID, + output [7:0] VCUPLMCUMAXIICDCARLEN, + output VCUPLMCUMAXIICDCARLOCK, + output [2:0] VCUPLMCUMAXIICDCARPROT, + output [3:0] VCUPLMCUMAXIICDCARQOS, + output [2:0] VCUPLMCUMAXIICDCARSIZE, + output VCUPLMCUMAXIICDCARVALID, + output [43:0] VCUPLMCUMAXIICDCAWADDR, + output [1:0] VCUPLMCUMAXIICDCAWBURST, + output [3:0] VCUPLMCUMAXIICDCAWCACHE, + output [2:0] VCUPLMCUMAXIICDCAWID, + output [7:0] VCUPLMCUMAXIICDCAWLEN, + output VCUPLMCUMAXIICDCAWLOCK, + output [2:0] VCUPLMCUMAXIICDCAWPROT, + output [3:0] VCUPLMCUMAXIICDCAWQOS, + output [2:0] VCUPLMCUMAXIICDCAWSIZE, + output VCUPLMCUMAXIICDCAWVALID, + output VCUPLMCUMAXIICDCBREADY, + output VCUPLMCUMAXIICDCRREADY, + output [31:0] VCUPLMCUMAXIICDCWDATA, + output VCUPLMCUMAXIICDCWLAST, + output [3:0] VCUPLMCUMAXIICDCWSTRB, + output VCUPLMCUMAXIICDCWVALID, + output VCUPLMCUSTATUSCLKPLL, + output VCUPLPINTREQ, + output VCUPLPLLSTATUSPLLLOCK, + output VCUPLPWRSUPPLYSTATUSVCCAUX, + output VCUPLPWRSUPPLYSTATUSVCUINT, + output [31:0] VCUPLRDATAAXILITEAPB, + output [1:0] VCUPLRRESPAXILITEAPB, + output VCUPLRVALIDAXILITEAPB, + output VCUPLWREADYAXILITEAPB, + + input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD, + input [19:0] PLVCUARADDRAXILITEAPB, + input [2:0] PLVCUARPROTAXILITEAPB, + input PLVCUARVALIDAXILITEAPB, + input [19:0] PLVCUAWADDRAXILITEAPB, + input [2:0] PLVCUAWPROTAXILITEAPB, + input PLVCUAWVALIDAXILITEAPB, + input PLVCUAXIDECCLK, + input PLVCUAXIENCCLK, + input PLVCUAXILITECLK, + input PLVCUAXIMCUCLK, + input PLVCUBREADYAXILITEAPB, + input PLVCUCORECLK, + input PLVCUDECARREADY0, + input PLVCUDECARREADY1, + input PLVCUDECAWREADY0, + input PLVCUDECAWREADY1, + input [3:0] PLVCUDECBID0, + input [3:0] PLVCUDECBID1, + input [1:0] PLVCUDECBRESP0, + input [1:0] PLVCUDECBRESP1, + input PLVCUDECBVALID0, + input PLVCUDECBVALID1, + input [127:0] PLVCUDECRDATA0, + input [127:0] PLVCUDECRDATA1, + input [3:0] PLVCUDECRID0, + input [3:0] PLVCUDECRID1, + input PLVCUDECRLAST0, + input PLVCUDECRLAST1, + input [1:0] PLVCUDECRRESP0, + input [1:0] PLVCUDECRRESP1, + input PLVCUDECRVALID0, + input PLVCUDECRVALID1, + input PLVCUDECWREADY0, + input PLVCUDECWREADY1, + input [319:0] PLVCUENCALL2CRDATA, + input PLVCUENCALL2CRREADY, + input PLVCUENCARREADY0, + input PLVCUENCARREADY1, + input PLVCUENCAWREADY0, + input PLVCUENCAWREADY1, + input [3:0] PLVCUENCBID0, + input [3:0] PLVCUENCBID1, + input [1:0] PLVCUENCBRESP0, + input [1:0] PLVCUENCBRESP1, + input PLVCUENCBVALID0, + input PLVCUENCBVALID1, + input PLVCUENCL2CCLK, + input [127:0] PLVCUENCRDATA0, + input [127:0] PLVCUENCRDATA1, + input [3:0] PLVCUENCRID0, + input [3:0] PLVCUENCRID1, + input PLVCUENCRLAST0, + input PLVCUENCRLAST1, + input [1:0] PLVCUENCRRESP0, + input [1:0] PLVCUENCRRESP1, + input PLVCUENCRVALID0, + input PLVCUENCRVALID1, + input PLVCUENCWREADY0, + input PLVCUENCWREADY1, + input PLVCUMCUCLK, + input PLVCUMCUMAXIICDCARREADY, + input PLVCUMCUMAXIICDCAWREADY, + input [2:0] PLVCUMCUMAXIICDCBID, + input [1:0] PLVCUMCUMAXIICDCBRESP, + input PLVCUMCUMAXIICDCBVALID, + input [31:0] PLVCUMCUMAXIICDCRDATA, + input [2:0] PLVCUMCUMAXIICDCRID, + input PLVCUMCUMAXIICDCRLAST, + input [1:0] PLVCUMCUMAXIICDCRRESP, + input PLVCUMCUMAXIICDCRVALID, + input PLVCUMCUMAXIICDCWREADY, + input PLVCUPLLREFCLKPL, + input PLVCURAWRSTN, + input PLVCURREADYAXILITEAPB, + input [31:0] PLVCUWDATAAXILITEAPB, + input [3:0] PLVCUWSTRBAXILITEAPB, + input PLVCUWVALIDAXILITEAPB +); + +// define constants + localparam MODULE_NAME = "VCU"; + +// Parameter encodings and registers + localparam DECODERCHROMAFORMAT_4_2_0 = 1; + localparam DECODERCHROMAFORMAT_4_2_2 = 0; + localparam DECODERCODING_H_264 = 1; + localparam DECODERCODING_H_265 = 0; + localparam ENABLEDECODER_FALSE = 1; + localparam ENABLEDECODER_TRUE = 0; + localparam ENABLEENCODER_FALSE = 1; + localparam ENABLEENCODER_TRUE = 0; + localparam ENCODERCHROMAFORMAT_4_2_0 = 1; + localparam ENCODERCHROMAFORMAT_4_2_2 = 0; + localparam ENCODERCODING_H_264 = 1; + localparam ENCODERCODING_H_265 = 0; + + reg trig_attr = 1'b0; +// include dynamic registers - XILINX test only +`ifdef XIL_DR + `include "VCU_dr.v" +`else + reg [31:0] CORECLKREQ_REG = CORECLKREQ; + reg [31:0] DECHORRESOLUTION_REG = DECHORRESOLUTION; + reg [40:1] DECODERCHROMAFORMAT_REG = DECODERCHROMAFORMAT; + reg [40:1] DECODERCODING_REG = DECODERCODING; + reg [31:0] DECODERCOLORDEPTH_REG = DECODERCOLORDEPTH; + reg [31:0] DECODERNUMCORES_REG = DECODERNUMCORES; + reg [31:0] DECVERTRESOLUTION_REG = DECVERTRESOLUTION; + reg [40:1] ENABLEDECODER_REG = ENABLEDECODER; + reg [40:1] ENABLEENCODER_REG = ENABLEENCODER; + reg [31:0] ENCHORRESOLUTION_REG = ENCHORRESOLUTION; + reg [40:1] ENCODERCHROMAFORMAT_REG = ENCODERCHROMAFORMAT; + reg [40:1] ENCODERCODING_REG = ENCODERCODING; + reg [31:0] ENCODERCOLORDEPTH_REG = ENCODERCOLORDEPTH; + reg [31:0] ENCODERNUMCORES_REG = ENCODERNUMCORES; + reg [31:0] ENCVERTRESOLUTION_REG = ENCVERTRESOLUTION; +`endif + +`ifdef XIL_XECLIB + wire [9:0] CORECLKREQ_BIN; + wire [13:0] DECHORRESOLUTION_BIN; + wire DECODERCHROMAFORMAT_BIN; + wire DECODERCODING_BIN; + wire [3:0] DECODERCOLORDEPTH_BIN; + wire [1:0] DECODERNUMCORES_BIN; + wire [12:0] DECVERTRESOLUTION_BIN; + wire ENABLEDECODER_BIN; + wire ENABLEENCODER_BIN; + wire [13:0] ENCHORRESOLUTION_BIN; + wire ENCODERCHROMAFORMAT_BIN; + wire ENCODERCODING_BIN; + wire [3:0] ENCODERCOLORDEPTH_BIN; + wire [2:0] ENCODERNUMCORES_BIN; + wire [12:0] ENCVERTRESOLUTION_BIN; +`else + reg [9:0] CORECLKREQ_BIN; + reg [13:0] DECHORRESOLUTION_BIN; + reg DECODERCHROMAFORMAT_BIN; + reg DECODERCODING_BIN; + reg [3:0] DECODERCOLORDEPTH_BIN; + reg [1:0] DECODERNUMCORES_BIN; + reg [12:0] DECVERTRESOLUTION_BIN; + reg ENABLEDECODER_BIN; + reg ENABLEENCODER_BIN; + reg [13:0] ENCHORRESOLUTION_BIN; + reg ENCODERCHROMAFORMAT_BIN; + reg ENCODERCODING_BIN; + reg [3:0] ENCODERCOLORDEPTH_BIN; + reg [2:0] ENCODERNUMCORES_BIN; + reg [12:0] ENCVERTRESOLUTION_BIN; +`endif + +`ifdef XIL_ATTR_TEST + reg attr_test = 1'b1; +`else + reg attr_test = 1'b0; +`endif + + reg attr_err = 1'b0; + tri0 glblGSR = glbl.GSR; + +// reg VCUPLCORESTATUSCLKPLL_out; +// reg VCUPLMCUSTATUSCLKPLL_out; + reg VCUPLARREADYAXILITEAPB_out; + reg VCUPLAWREADYAXILITEAPB_out; + reg [1:0] VCUPLBRESPAXILITEAPB_out; + reg VCUPLBVALIDAXILITEAPB_out; + reg VCUPLCORESTATUSCLKPLL_out; + reg [43:0] VCUPLDECARADDR0_out; + reg [43:0] VCUPLDECARADDR1_out; + reg [1:0] VCUPLDECARBURST0_out; + reg [1:0] VCUPLDECARBURST1_out; + reg [3:0] VCUPLDECARCACHE0_out; + reg [3:0] VCUPLDECARCACHE1_out; + reg [3:0] VCUPLDECARID0_out; + reg [3:0] VCUPLDECARID1_out; + reg [7:0] VCUPLDECARLEN0_out; + reg [7:0] VCUPLDECARLEN1_out; + reg VCUPLDECARPROT0_out; + reg VCUPLDECARPROT1_out; + reg [3:0] VCUPLDECARQOS0_out; + reg [3:0] VCUPLDECARQOS1_out; + reg [2:0] VCUPLDECARSIZE0_out; + reg [2:0] VCUPLDECARSIZE1_out; + reg VCUPLDECARVALID0_out; + reg VCUPLDECARVALID1_out; + reg [43:0] VCUPLDECAWADDR0_out; + reg [43:0] VCUPLDECAWADDR1_out; + reg [1:0] VCUPLDECAWBURST0_out; + reg [1:0] VCUPLDECAWBURST1_out; + reg [3:0] VCUPLDECAWCACHE0_out; + reg [3:0] VCUPLDECAWCACHE1_out; + reg [3:0] VCUPLDECAWID0_out; + reg [3:0] VCUPLDECAWID1_out; + reg [7:0] VCUPLDECAWLEN0_out; + reg [7:0] VCUPLDECAWLEN1_out; + reg VCUPLDECAWPROT0_out; + reg VCUPLDECAWPROT1_out; + reg [3:0] VCUPLDECAWQOS0_out; + reg [3:0] VCUPLDECAWQOS1_out; + reg [2:0] VCUPLDECAWSIZE0_out; + reg [2:0] VCUPLDECAWSIZE1_out; + reg VCUPLDECAWVALID0_out; + reg VCUPLDECAWVALID1_out; + reg VCUPLDECBREADY0_out; + reg VCUPLDECBREADY1_out; + reg VCUPLDECRREADY0_out; + reg VCUPLDECRREADY1_out; + reg [127:0] VCUPLDECWDATA0_out; + reg [127:0] VCUPLDECWDATA1_out; + reg VCUPLDECWLAST0_out; + reg VCUPLDECWLAST1_out; + reg VCUPLDECWVALID0_out; + reg VCUPLDECWVALID1_out; + reg [16:0] VCUPLENCALL2CADDR_out; + reg VCUPLENCALL2CRVALID_out; + reg [319:0] VCUPLENCALL2CWDATA_out; + reg VCUPLENCALL2CWVALID_out; + reg [43:0] VCUPLENCARADDR0_out; + reg [43:0] VCUPLENCARADDR1_out; + reg [1:0] VCUPLENCARBURST0_out; + reg [1:0] VCUPLENCARBURST1_out; + reg [3:0] VCUPLENCARCACHE0_out; + reg [3:0] VCUPLENCARCACHE1_out; + reg [3:0] VCUPLENCARID0_out; + reg [3:0] VCUPLENCARID1_out; + reg [7:0] VCUPLENCARLEN0_out; + reg [7:0] VCUPLENCARLEN1_out; + reg VCUPLENCARPROT0_out; + reg VCUPLENCARPROT1_out; + reg [3:0] VCUPLENCARQOS0_out; + reg [3:0] VCUPLENCARQOS1_out; + reg [2:0] VCUPLENCARSIZE0_out; + reg [2:0] VCUPLENCARSIZE1_out; + reg VCUPLENCARVALID0_out; + reg VCUPLENCARVALID1_out; + reg [43:0] VCUPLENCAWADDR0_out; + reg [43:0] VCUPLENCAWADDR1_out; + reg [1:0] VCUPLENCAWBURST0_out; + reg [1:0] VCUPLENCAWBURST1_out; + reg [3:0] VCUPLENCAWCACHE0_out; + reg [3:0] VCUPLENCAWCACHE1_out; + reg [3:0] VCUPLENCAWID0_out; + reg [3:0] VCUPLENCAWID1_out; + reg [7:0] VCUPLENCAWLEN0_out; + reg [7:0] VCUPLENCAWLEN1_out; + reg VCUPLENCAWPROT0_out; + reg VCUPLENCAWPROT1_out; + reg [3:0] VCUPLENCAWQOS0_out; + reg [3:0] VCUPLENCAWQOS1_out; + reg [2:0] VCUPLENCAWSIZE0_out; + reg [2:0] VCUPLENCAWSIZE1_out; + reg VCUPLENCAWVALID0_out; + reg VCUPLENCAWVALID1_out; + reg VCUPLENCBREADY0_out; + reg VCUPLENCBREADY1_out; + reg VCUPLENCRREADY0_out; + reg VCUPLENCRREADY1_out; + reg [127:0] VCUPLENCWDATA0_out; + reg [127:0] VCUPLENCWDATA1_out; + reg VCUPLENCWLAST0_out; + reg VCUPLENCWLAST1_out; + reg VCUPLENCWVALID0_out; + reg VCUPLENCWVALID1_out; + reg [43:0] VCUPLMCUMAXIICDCARADDR_out; + reg [1:0] VCUPLMCUMAXIICDCARBURST_out; + reg [3:0] VCUPLMCUMAXIICDCARCACHE_out; + reg [2:0] VCUPLMCUMAXIICDCARID_out; + reg [7:0] VCUPLMCUMAXIICDCARLEN_out; + reg VCUPLMCUMAXIICDCARLOCK_out; + reg [2:0] VCUPLMCUMAXIICDCARPROT_out; + reg [3:0] VCUPLMCUMAXIICDCARQOS_out; + reg [2:0] VCUPLMCUMAXIICDCARSIZE_out; + reg VCUPLMCUMAXIICDCARVALID_out; + reg [43:0] VCUPLMCUMAXIICDCAWADDR_out; + reg [1:0] VCUPLMCUMAXIICDCAWBURST_out; + reg [3:0] VCUPLMCUMAXIICDCAWCACHE_out; + reg [2:0] VCUPLMCUMAXIICDCAWID_out; + reg [7:0] VCUPLMCUMAXIICDCAWLEN_out; + reg VCUPLMCUMAXIICDCAWLOCK_out; + reg [2:0] VCUPLMCUMAXIICDCAWPROT_out; + reg [3:0] VCUPLMCUMAXIICDCAWQOS_out; + reg [2:0] VCUPLMCUMAXIICDCAWSIZE_out; + reg VCUPLMCUMAXIICDCAWVALID_out; + reg VCUPLMCUMAXIICDCBREADY_out; + reg VCUPLMCUMAXIICDCRREADY_out; + reg [31:0] VCUPLMCUMAXIICDCWDATA_out; + reg VCUPLMCUMAXIICDCWLAST_out; + reg [3:0] VCUPLMCUMAXIICDCWSTRB_out; + reg VCUPLMCUMAXIICDCWVALID_out; + reg VCUPLMCUSTATUSCLKPLL_out; + reg VCUPLPINTREQ_out; + reg VCUPLPLLSTATUSPLLLOCK_out; + reg VCUPLPWRSUPPLYSTATUSVCCAUX_out; + reg VCUPLPWRSUPPLYSTATUSVCUINT_out; + reg [31:0] VCUPLRDATAAXILITEAPB_out; + reg [1:0] VCUPLRRESPAXILITEAPB_out; + reg VCUPLRVALIDAXILITEAPB_out; + reg VCUPLWREADYAXILITEAPB_out; + + wire INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD_in; + wire PLVCUARVALIDAXILITEAPB_in; + wire PLVCUAWVALIDAXILITEAPB_in; + wire PLVCUAXIDECCLK_in; + wire PLVCUAXIENCCLK_in; + wire PLVCUAXILITECLK_in; + wire PLVCUAXIMCUCLK_in; + wire PLVCUBREADYAXILITEAPB_in; + wire PLVCUCORECLK_in; + wire PLVCUDECARREADY0_in; + wire PLVCUDECARREADY1_in; + wire PLVCUDECAWREADY0_in; + wire PLVCUDECAWREADY1_in; + wire PLVCUDECBVALID0_in; + wire PLVCUDECBVALID1_in; + wire PLVCUDECRLAST0_in; + wire PLVCUDECRLAST1_in; + wire PLVCUDECRVALID0_in; + wire PLVCUDECRVALID1_in; + wire PLVCUDECWREADY0_in; + wire PLVCUDECWREADY1_in; + wire PLVCUENCALL2CRREADY_in; + wire PLVCUENCARREADY0_in; + wire PLVCUENCARREADY1_in; + wire PLVCUENCAWREADY0_in; + wire PLVCUENCAWREADY1_in; + wire PLVCUENCBVALID0_in; + wire PLVCUENCBVALID1_in; + wire PLVCUENCL2CCLK_in; + wire PLVCUENCRLAST0_in; + wire PLVCUENCRLAST1_in; + wire PLVCUENCRVALID0_in; + wire PLVCUENCRVALID1_in; + wire PLVCUENCWREADY0_in; + wire PLVCUENCWREADY1_in; + wire PLVCUMCUCLK_in; + wire PLVCUMCUMAXIICDCARREADY_in; + wire PLVCUMCUMAXIICDCAWREADY_in; + wire PLVCUMCUMAXIICDCBVALID_in; + wire PLVCUMCUMAXIICDCRLAST_in; + wire PLVCUMCUMAXIICDCRVALID_in; + wire PLVCUMCUMAXIICDCWREADY_in; + wire PLVCUPLLREFCLKPL_in; + wire PLVCURAWRSTN_in; + wire PLVCURREADYAXILITEAPB_in; + wire PLVCUWVALIDAXILITEAPB_in; + wire [127:0] PLVCUDECRDATA0_in; + wire [127:0] PLVCUDECRDATA1_in; + wire [127:0] PLVCUENCRDATA0_in; + wire [127:0] PLVCUENCRDATA1_in; + wire [19:0] PLVCUARADDRAXILITEAPB_in; + wire [19:0] PLVCUAWADDRAXILITEAPB_in; + wire [1:0] PLVCUDECBRESP0_in; + wire [1:0] PLVCUDECBRESP1_in; + wire [1:0] PLVCUDECRRESP0_in; + wire [1:0] PLVCUDECRRESP1_in; + wire [1:0] PLVCUENCBRESP0_in; + wire [1:0] PLVCUENCBRESP1_in; + wire [1:0] PLVCUENCRRESP0_in; + wire [1:0] PLVCUENCRRESP1_in; + wire [1:0] PLVCUMCUMAXIICDCBRESP_in; + wire [1:0] PLVCUMCUMAXIICDCRRESP_in; + wire [2:0] PLVCUARPROTAXILITEAPB_in; + wire [2:0] PLVCUAWPROTAXILITEAPB_in; + wire [2:0] PLVCUMCUMAXIICDCBID_in; + wire [2:0] PLVCUMCUMAXIICDCRID_in; + wire [319:0] PLVCUENCALL2CRDATA_in; + wire [31:0] PLVCUMCUMAXIICDCRDATA_in; + wire [31:0] PLVCUWDATAAXILITEAPB_in; + wire [3:0] PLVCUDECBID0_in; + wire [3:0] PLVCUDECBID1_in; + wire [3:0] PLVCUDECRID0_in; + wire [3:0] PLVCUDECRID1_in; + wire [3:0] PLVCUENCBID0_in; + wire [3:0] PLVCUENCBID1_in; + wire [3:0] PLVCUENCRID0_in; + wire [3:0] PLVCUENCRID1_in; + wire [3:0] PLVCUWSTRBAXILITEAPB_in; + +`ifdef XIL_TIMING + wire PLVCUARVALIDAXILITEAPB_delay; + wire PLVCUAWVALIDAXILITEAPB_delay; + wire PLVCUAXIDECCLK_delay; + wire PLVCUAXIENCCLK_delay; + wire PLVCUAXILITECLK_delay; + wire PLVCUAXIMCUCLK_delay; + wire PLVCUBREADYAXILITEAPB_delay; + wire PLVCUDECARREADY0_delay; + wire PLVCUDECARREADY1_delay; + wire PLVCUDECAWREADY0_delay; + wire PLVCUDECAWREADY1_delay; + wire PLVCUDECBVALID0_delay; + wire PLVCUDECBVALID1_delay; + wire PLVCUDECRLAST0_delay; + wire PLVCUDECRLAST1_delay; + wire PLVCUDECRVALID0_delay; + wire PLVCUDECRVALID1_delay; + wire PLVCUDECWREADY0_delay; + wire PLVCUDECWREADY1_delay; + wire PLVCUENCALL2CRREADY_delay; + wire PLVCUENCARREADY0_delay; + wire PLVCUENCARREADY1_delay; + wire PLVCUENCAWREADY0_delay; + wire PLVCUENCAWREADY1_delay; + wire PLVCUENCBVALID0_delay; + wire PLVCUENCBVALID1_delay; + wire PLVCUENCL2CCLK_delay; + wire PLVCUENCRLAST0_delay; + wire PLVCUENCRLAST1_delay; + wire PLVCUENCRVALID0_delay; + wire PLVCUENCRVALID1_delay; + wire PLVCUENCWREADY0_delay; + wire PLVCUENCWREADY1_delay; + wire PLVCUMCUMAXIICDCARREADY_delay; + wire PLVCUMCUMAXIICDCAWREADY_delay; + wire PLVCUMCUMAXIICDCBVALID_delay; + wire PLVCUMCUMAXIICDCRLAST_delay; + wire PLVCUMCUMAXIICDCRVALID_delay; + wire PLVCUMCUMAXIICDCWREADY_delay; + wire PLVCURREADYAXILITEAPB_delay; + wire PLVCUWVALIDAXILITEAPB_delay; + wire [127:0] PLVCUDECRDATA0_delay; + wire [127:0] PLVCUDECRDATA1_delay; + wire [127:0] PLVCUENCRDATA0_delay; + wire [127:0] PLVCUENCRDATA1_delay; + wire [19:0] PLVCUARADDRAXILITEAPB_delay; + wire [19:0] PLVCUAWADDRAXILITEAPB_delay; + wire [1:0] PLVCUDECBRESP0_delay; + wire [1:0] PLVCUDECBRESP1_delay; + wire [1:0] PLVCUDECRRESP0_delay; + wire [1:0] PLVCUDECRRESP1_delay; + wire [1:0] PLVCUENCBRESP0_delay; + wire [1:0] PLVCUENCBRESP1_delay; + wire [1:0] PLVCUENCRRESP0_delay; + wire [1:0] PLVCUENCRRESP1_delay; + wire [1:0] PLVCUMCUMAXIICDCBRESP_delay; + wire [1:0] PLVCUMCUMAXIICDCRRESP_delay; + wire [2:0] PLVCUARPROTAXILITEAPB_delay; + wire [2:0] PLVCUAWPROTAXILITEAPB_delay; + wire [2:0] PLVCUMCUMAXIICDCBID_delay; + wire [2:0] PLVCUMCUMAXIICDCRID_delay; + wire [319:0] PLVCUENCALL2CRDATA_delay; + wire [31:0] PLVCUMCUMAXIICDCRDATA_delay; + wire [31:0] PLVCUWDATAAXILITEAPB_delay; + wire [3:0] PLVCUDECBID0_delay; + wire [3:0] PLVCUDECBID1_delay; + wire [3:0] PLVCUDECRID0_delay; + wire [3:0] PLVCUDECRID1_delay; + wire [3:0] PLVCUENCBID0_delay; + wire [3:0] PLVCUENCBID1_delay; + wire [3:0] PLVCUENCRID0_delay; + wire [3:0] PLVCUENCRID1_delay; + wire [3:0] PLVCUWSTRBAXILITEAPB_delay; +`endif + +// assign VCUPLCORESTATUSCLKPLL = VCUPLCORESTATUSCLKPLL_out; +// assign VCUPLMCUSTATUSCLKPLL = VCUPLMCUSTATUSCLKPLL_out; + assign VCUPLARREADYAXILITEAPB = VCUPLARREADYAXILITEAPB_out; + assign VCUPLAWREADYAXILITEAPB = VCUPLAWREADYAXILITEAPB_out; + assign VCUPLBRESPAXILITEAPB = VCUPLBRESPAXILITEAPB_out; + assign VCUPLBVALIDAXILITEAPB = VCUPLBVALIDAXILITEAPB_out; + assign VCUPLCORESTATUSCLKPLL = VCUPLCORESTATUSCLKPLL_out; + assign VCUPLDECARADDR0 = VCUPLDECARADDR0_out; + assign VCUPLDECARADDR1 = VCUPLDECARADDR1_out; + assign VCUPLDECARBURST0 = VCUPLDECARBURST0_out; + assign VCUPLDECARBURST1 = VCUPLDECARBURST1_out; + assign VCUPLDECARCACHE0 = VCUPLDECARCACHE0_out; + assign VCUPLDECARCACHE1 = VCUPLDECARCACHE1_out; + assign VCUPLDECARID0 = VCUPLDECARID0_out; + assign VCUPLDECARID1 = VCUPLDECARID1_out; + assign VCUPLDECARLEN0 = VCUPLDECARLEN0_out; + assign VCUPLDECARLEN1 = VCUPLDECARLEN1_out; + assign VCUPLDECARPROT0 = VCUPLDECARPROT0_out; + assign VCUPLDECARPROT1 = VCUPLDECARPROT1_out; + assign VCUPLDECARQOS0 = VCUPLDECARQOS0_out; + assign VCUPLDECARQOS1 = VCUPLDECARQOS1_out; + assign VCUPLDECARSIZE0 = VCUPLDECARSIZE0_out; + assign VCUPLDECARSIZE1 = VCUPLDECARSIZE1_out; + assign VCUPLDECARVALID0 = VCUPLDECARVALID0_out; + assign VCUPLDECARVALID1 = VCUPLDECARVALID1_out; + assign VCUPLDECAWADDR0 = VCUPLDECAWADDR0_out; + assign VCUPLDECAWADDR1 = VCUPLDECAWADDR1_out; + assign VCUPLDECAWBURST0 = VCUPLDECAWBURST0_out; + assign VCUPLDECAWBURST1 = VCUPLDECAWBURST1_out; + assign VCUPLDECAWCACHE0 = VCUPLDECAWCACHE0_out; + assign VCUPLDECAWCACHE1 = VCUPLDECAWCACHE1_out; + assign VCUPLDECAWID0 = VCUPLDECAWID0_out; + assign VCUPLDECAWID1 = VCUPLDECAWID1_out; + assign VCUPLDECAWLEN0 = VCUPLDECAWLEN0_out; + assign VCUPLDECAWLEN1 = VCUPLDECAWLEN1_out; + assign VCUPLDECAWPROT0 = VCUPLDECAWPROT0_out; + assign VCUPLDECAWPROT1 = VCUPLDECAWPROT1_out; + assign VCUPLDECAWQOS0 = VCUPLDECAWQOS0_out; + assign VCUPLDECAWQOS1 = VCUPLDECAWQOS1_out; + assign VCUPLDECAWSIZE0 = VCUPLDECAWSIZE0_out; + assign VCUPLDECAWSIZE1 = VCUPLDECAWSIZE1_out; + assign VCUPLDECAWVALID0 = VCUPLDECAWVALID0_out; + assign VCUPLDECAWVALID1 = VCUPLDECAWVALID1_out; + assign VCUPLDECBREADY0 = VCUPLDECBREADY0_out; + assign VCUPLDECBREADY1 = VCUPLDECBREADY1_out; + assign VCUPLDECRREADY0 = VCUPLDECRREADY0_out; + assign VCUPLDECRREADY1 = VCUPLDECRREADY1_out; + assign VCUPLDECWDATA0 = VCUPLDECWDATA0_out; + assign VCUPLDECWDATA1 = VCUPLDECWDATA1_out; + assign VCUPLDECWLAST0 = VCUPLDECWLAST0_out; + assign VCUPLDECWLAST1 = VCUPLDECWLAST1_out; + assign VCUPLDECWVALID0 = VCUPLDECWVALID0_out; + assign VCUPLDECWVALID1 = VCUPLDECWVALID1_out; + assign VCUPLENCALL2CADDR = VCUPLENCALL2CADDR_out; + assign VCUPLENCALL2CRVALID = VCUPLENCALL2CRVALID_out; + assign VCUPLENCALL2CWDATA = VCUPLENCALL2CWDATA_out; + assign VCUPLENCALL2CWVALID = VCUPLENCALL2CWVALID_out; + assign VCUPLENCARADDR0 = VCUPLENCARADDR0_out; + assign VCUPLENCARADDR1 = VCUPLENCARADDR1_out; + assign VCUPLENCARBURST0 = VCUPLENCARBURST0_out; + assign VCUPLENCARBURST1 = VCUPLENCARBURST1_out; + assign VCUPLENCARCACHE0 = VCUPLENCARCACHE0_out; + assign VCUPLENCARCACHE1 = VCUPLENCARCACHE1_out; + assign VCUPLENCARID0 = VCUPLENCARID0_out; + assign VCUPLENCARID1 = VCUPLENCARID1_out; + assign VCUPLENCARLEN0 = VCUPLENCARLEN0_out; + assign VCUPLENCARLEN1 = VCUPLENCARLEN1_out; + assign VCUPLENCARPROT0 = VCUPLENCARPROT0_out; + assign VCUPLENCARPROT1 = VCUPLENCARPROT1_out; + assign VCUPLENCARQOS0 = VCUPLENCARQOS0_out; + assign VCUPLENCARQOS1 = VCUPLENCARQOS1_out; + assign VCUPLENCARSIZE0 = VCUPLENCARSIZE0_out; + assign VCUPLENCARSIZE1 = VCUPLENCARSIZE1_out; + assign VCUPLENCARVALID0 = VCUPLENCARVALID0_out; + assign VCUPLENCARVALID1 = VCUPLENCARVALID1_out; + assign VCUPLENCAWADDR0 = VCUPLENCAWADDR0_out; + assign VCUPLENCAWADDR1 = VCUPLENCAWADDR1_out; + assign VCUPLENCAWBURST0 = VCUPLENCAWBURST0_out; + assign VCUPLENCAWBURST1 = VCUPLENCAWBURST1_out; + assign VCUPLENCAWCACHE0 = VCUPLENCAWCACHE0_out; + assign VCUPLENCAWCACHE1 = VCUPLENCAWCACHE1_out; + assign VCUPLENCAWID0 = VCUPLENCAWID0_out; + assign VCUPLENCAWID1 = VCUPLENCAWID1_out; + assign VCUPLENCAWLEN0 = VCUPLENCAWLEN0_out; + assign VCUPLENCAWLEN1 = VCUPLENCAWLEN1_out; + assign VCUPLENCAWPROT0 = VCUPLENCAWPROT0_out; + assign VCUPLENCAWPROT1 = VCUPLENCAWPROT1_out; + assign VCUPLENCAWQOS0 = VCUPLENCAWQOS0_out; + assign VCUPLENCAWQOS1 = VCUPLENCAWQOS1_out; + assign VCUPLENCAWSIZE0 = VCUPLENCAWSIZE0_out; + assign VCUPLENCAWSIZE1 = VCUPLENCAWSIZE1_out; + assign VCUPLENCAWVALID0 = VCUPLENCAWVALID0_out; + assign VCUPLENCAWVALID1 = VCUPLENCAWVALID1_out; + assign VCUPLENCBREADY0 = VCUPLENCBREADY0_out; + assign VCUPLENCBREADY1 = VCUPLENCBREADY1_out; + assign VCUPLENCRREADY0 = VCUPLENCRREADY0_out; + assign VCUPLENCRREADY1 = VCUPLENCRREADY1_out; + assign VCUPLENCWDATA0 = VCUPLENCWDATA0_out; + assign VCUPLENCWDATA1 = VCUPLENCWDATA1_out; + assign VCUPLENCWLAST0 = VCUPLENCWLAST0_out; + assign VCUPLENCWLAST1 = VCUPLENCWLAST1_out; + assign VCUPLENCWVALID0 = VCUPLENCWVALID0_out; + assign VCUPLENCWVALID1 = VCUPLENCWVALID1_out; + assign VCUPLMCUMAXIICDCARADDR = VCUPLMCUMAXIICDCARADDR_out; + assign VCUPLMCUMAXIICDCARBURST = VCUPLMCUMAXIICDCARBURST_out; + assign VCUPLMCUMAXIICDCARCACHE = VCUPLMCUMAXIICDCARCACHE_out; + assign VCUPLMCUMAXIICDCARID = VCUPLMCUMAXIICDCARID_out; + assign VCUPLMCUMAXIICDCARLEN = VCUPLMCUMAXIICDCARLEN_out; + assign VCUPLMCUMAXIICDCARLOCK = VCUPLMCUMAXIICDCARLOCK_out; + assign VCUPLMCUMAXIICDCARPROT = VCUPLMCUMAXIICDCARPROT_out; + assign VCUPLMCUMAXIICDCARQOS = VCUPLMCUMAXIICDCARQOS_out; + assign VCUPLMCUMAXIICDCARSIZE = VCUPLMCUMAXIICDCARSIZE_out; + assign VCUPLMCUMAXIICDCARVALID = VCUPLMCUMAXIICDCARVALID_out; + assign VCUPLMCUMAXIICDCAWADDR = VCUPLMCUMAXIICDCAWADDR_out; + assign VCUPLMCUMAXIICDCAWBURST = VCUPLMCUMAXIICDCAWBURST_out; + assign VCUPLMCUMAXIICDCAWCACHE = VCUPLMCUMAXIICDCAWCACHE_out; + assign VCUPLMCUMAXIICDCAWID = VCUPLMCUMAXIICDCAWID_out; + assign VCUPLMCUMAXIICDCAWLEN = VCUPLMCUMAXIICDCAWLEN_out; + assign VCUPLMCUMAXIICDCAWLOCK = VCUPLMCUMAXIICDCAWLOCK_out; + assign VCUPLMCUMAXIICDCAWPROT = VCUPLMCUMAXIICDCAWPROT_out; + assign VCUPLMCUMAXIICDCAWQOS = VCUPLMCUMAXIICDCAWQOS_out; + assign VCUPLMCUMAXIICDCAWSIZE = VCUPLMCUMAXIICDCAWSIZE_out; + assign VCUPLMCUMAXIICDCAWVALID = VCUPLMCUMAXIICDCAWVALID_out; + assign VCUPLMCUMAXIICDCBREADY = VCUPLMCUMAXIICDCBREADY_out; + assign VCUPLMCUMAXIICDCRREADY = VCUPLMCUMAXIICDCRREADY_out; + assign VCUPLMCUMAXIICDCWDATA = VCUPLMCUMAXIICDCWDATA_out; + assign VCUPLMCUMAXIICDCWLAST = VCUPLMCUMAXIICDCWLAST_out; + assign VCUPLMCUMAXIICDCWSTRB = VCUPLMCUMAXIICDCWSTRB_out; + assign VCUPLMCUMAXIICDCWVALID = VCUPLMCUMAXIICDCWVALID_out; + assign VCUPLMCUSTATUSCLKPLL = VCUPLMCUSTATUSCLKPLL_out; + assign VCUPLPINTREQ = VCUPLPINTREQ_out; + assign VCUPLPLLSTATUSPLLLOCK = VCUPLPLLSTATUSPLLLOCK_out; + assign VCUPLPWRSUPPLYSTATUSVCCAUX = VCUPLPWRSUPPLYSTATUSVCCAUX_out; + assign VCUPLPWRSUPPLYSTATUSVCUINT = VCUPLPWRSUPPLYSTATUSVCUINT_out; + assign VCUPLRDATAAXILITEAPB = VCUPLRDATAAXILITEAPB_out; + assign VCUPLRRESPAXILITEAPB = VCUPLRRESPAXILITEAPB_out; + assign VCUPLRVALIDAXILITEAPB = VCUPLRVALIDAXILITEAPB_out; + assign VCUPLWREADYAXILITEAPB = VCUPLWREADYAXILITEAPB_out; + +`ifdef XIL_TIMING + assign PLVCUARADDRAXILITEAPB_in = PLVCUARADDRAXILITEAPB_delay; + assign PLVCUARPROTAXILITEAPB_in = PLVCUARPROTAXILITEAPB_delay; + assign PLVCUARVALIDAXILITEAPB_in = PLVCUARVALIDAXILITEAPB_delay; + assign PLVCUAWADDRAXILITEAPB_in = PLVCUAWADDRAXILITEAPB_delay; + assign PLVCUAWPROTAXILITEAPB_in = PLVCUAWPROTAXILITEAPB_delay; + assign PLVCUAWVALIDAXILITEAPB_in = PLVCUAWVALIDAXILITEAPB_delay; + assign PLVCUAXIDECCLK_in = PLVCUAXIDECCLK_delay; + assign PLVCUAXIENCCLK_in = PLVCUAXIENCCLK_delay; + assign PLVCUAXILITECLK_in = PLVCUAXILITECLK_delay; + assign PLVCUAXIMCUCLK_in = PLVCUAXIMCUCLK_delay; + assign PLVCUBREADYAXILITEAPB_in = PLVCUBREADYAXILITEAPB_delay; + assign PLVCUDECARREADY0_in = PLVCUDECARREADY0_delay; + assign PLVCUDECARREADY1_in = PLVCUDECARREADY1_delay; + assign PLVCUDECAWREADY0_in = PLVCUDECAWREADY0_delay; + assign PLVCUDECAWREADY1_in = PLVCUDECAWREADY1_delay; + assign PLVCUDECBID0_in = PLVCUDECBID0_delay; + assign PLVCUDECBID1_in = PLVCUDECBID1_delay; + assign PLVCUDECBRESP0_in = PLVCUDECBRESP0_delay; + assign PLVCUDECBRESP1_in = PLVCUDECBRESP1_delay; + assign PLVCUDECBVALID0_in = PLVCUDECBVALID0_delay; + assign PLVCUDECBVALID1_in = PLVCUDECBVALID1_delay; + assign PLVCUDECRDATA0_in = PLVCUDECRDATA0_delay; + assign PLVCUDECRDATA1_in = PLVCUDECRDATA1_delay; + assign PLVCUDECRID0_in = PLVCUDECRID0_delay; + assign PLVCUDECRID1_in = PLVCUDECRID1_delay; + assign PLVCUDECRLAST0_in = PLVCUDECRLAST0_delay; + assign PLVCUDECRLAST1_in = PLVCUDECRLAST1_delay; + assign PLVCUDECRRESP0_in = PLVCUDECRRESP0_delay; + assign PLVCUDECRRESP1_in = PLVCUDECRRESP1_delay; + assign PLVCUDECRVALID0_in = PLVCUDECRVALID0_delay; + assign PLVCUDECRVALID1_in = PLVCUDECRVALID1_delay; + assign PLVCUDECWREADY0_in = PLVCUDECWREADY0_delay; + assign PLVCUDECWREADY1_in = PLVCUDECWREADY1_delay; + assign PLVCUENCALL2CRDATA_in = PLVCUENCALL2CRDATA_delay; + assign PLVCUENCALL2CRREADY_in = (PLVCUENCALL2CRREADY === 1'bz) || PLVCUENCALL2CRREADY_delay; // rv 1 + assign PLVCUENCARREADY0_in = PLVCUENCARREADY0_delay; + assign PLVCUENCARREADY1_in = PLVCUENCARREADY1_delay; + assign PLVCUENCAWREADY0_in = PLVCUENCAWREADY0_delay; + assign PLVCUENCAWREADY1_in = PLVCUENCAWREADY1_delay; + assign PLVCUENCBID0_in = PLVCUENCBID0_delay; + assign PLVCUENCBID1_in = PLVCUENCBID1_delay; + assign PLVCUENCBRESP0_in = PLVCUENCBRESP0_delay; + assign PLVCUENCBRESP1_in = PLVCUENCBRESP1_delay; + assign PLVCUENCBVALID0_in = PLVCUENCBVALID0_delay; + assign PLVCUENCBVALID1_in = PLVCUENCBVALID1_delay; + assign PLVCUENCL2CCLK_in = PLVCUENCL2CCLK_delay; + assign PLVCUENCRDATA0_in = PLVCUENCRDATA0_delay; + assign PLVCUENCRDATA1_in = PLVCUENCRDATA1_delay; + assign PLVCUENCRID0_in = PLVCUENCRID0_delay; + assign PLVCUENCRID1_in = PLVCUENCRID1_delay; + assign PLVCUENCRLAST0_in = PLVCUENCRLAST0_delay; + assign PLVCUENCRLAST1_in = PLVCUENCRLAST1_delay; + assign PLVCUENCRRESP0_in = PLVCUENCRRESP0_delay; + assign PLVCUENCRRESP1_in = PLVCUENCRRESP1_delay; + assign PLVCUENCRVALID0_in = PLVCUENCRVALID0_delay; + assign PLVCUENCRVALID1_in = PLVCUENCRVALID1_delay; + assign PLVCUENCWREADY0_in = PLVCUENCWREADY0_delay; + assign PLVCUENCWREADY1_in = PLVCUENCWREADY1_delay; + assign PLVCUMCUMAXIICDCARREADY_in = PLVCUMCUMAXIICDCARREADY_delay; + assign PLVCUMCUMAXIICDCAWREADY_in = PLVCUMCUMAXIICDCAWREADY_delay; + assign PLVCUMCUMAXIICDCBID_in = PLVCUMCUMAXIICDCBID_delay; + assign PLVCUMCUMAXIICDCBRESP_in = PLVCUMCUMAXIICDCBRESP_delay; + assign PLVCUMCUMAXIICDCBVALID_in = PLVCUMCUMAXIICDCBVALID_delay; + assign PLVCUMCUMAXIICDCRDATA_in = PLVCUMCUMAXIICDCRDATA_delay; + assign PLVCUMCUMAXIICDCRID_in = PLVCUMCUMAXIICDCRID_delay; + assign PLVCUMCUMAXIICDCRLAST_in = PLVCUMCUMAXIICDCRLAST_delay; + assign PLVCUMCUMAXIICDCRRESP_in = PLVCUMCUMAXIICDCRRESP_delay; + assign PLVCUMCUMAXIICDCRVALID_in = PLVCUMCUMAXIICDCRVALID_delay; + assign PLVCUMCUMAXIICDCWREADY_in = PLVCUMCUMAXIICDCWREADY_delay; + assign PLVCURREADYAXILITEAPB_in = PLVCURREADYAXILITEAPB_delay; + assign PLVCUWDATAAXILITEAPB_in = PLVCUWDATAAXILITEAPB_delay; + assign PLVCUWSTRBAXILITEAPB_in = PLVCUWSTRBAXILITEAPB_delay; + assign PLVCUWVALIDAXILITEAPB_in = PLVCUWVALIDAXILITEAPB_delay; +`else + assign PLVCUARADDRAXILITEAPB_in = PLVCUARADDRAXILITEAPB; + assign PLVCUARPROTAXILITEAPB_in = PLVCUARPROTAXILITEAPB; + assign PLVCUARVALIDAXILITEAPB_in = PLVCUARVALIDAXILITEAPB; + assign PLVCUAWADDRAXILITEAPB_in = PLVCUAWADDRAXILITEAPB; + assign PLVCUAWPROTAXILITEAPB_in = PLVCUAWPROTAXILITEAPB; + assign PLVCUAWVALIDAXILITEAPB_in = PLVCUAWVALIDAXILITEAPB; + assign PLVCUAXIDECCLK_in = PLVCUAXIDECCLK; + assign PLVCUAXIENCCLK_in = PLVCUAXIENCCLK; + assign PLVCUAXILITECLK_in = PLVCUAXILITECLK; + assign PLVCUAXIMCUCLK_in = PLVCUAXIMCUCLK; + assign PLVCUBREADYAXILITEAPB_in = PLVCUBREADYAXILITEAPB; + assign PLVCUDECARREADY0_in = PLVCUDECARREADY0; + assign PLVCUDECARREADY1_in = PLVCUDECARREADY1; + assign PLVCUDECAWREADY0_in = PLVCUDECAWREADY0; + assign PLVCUDECAWREADY1_in = PLVCUDECAWREADY1; + assign PLVCUDECBID0_in = PLVCUDECBID0; + assign PLVCUDECBID1_in = PLVCUDECBID1; + assign PLVCUDECBRESP0_in = PLVCUDECBRESP0; + assign PLVCUDECBRESP1_in = PLVCUDECBRESP1; + assign PLVCUDECBVALID0_in = PLVCUDECBVALID0; + assign PLVCUDECBVALID1_in = PLVCUDECBVALID1; + assign PLVCUDECRDATA0_in = PLVCUDECRDATA0; + assign PLVCUDECRDATA1_in = PLVCUDECRDATA1; + assign PLVCUDECRID0_in = PLVCUDECRID0; + assign PLVCUDECRID1_in = PLVCUDECRID1; + assign PLVCUDECRLAST0_in = PLVCUDECRLAST0; + assign PLVCUDECRLAST1_in = PLVCUDECRLAST1; + assign PLVCUDECRRESP0_in = PLVCUDECRRESP0; + assign PLVCUDECRRESP1_in = PLVCUDECRRESP1; + assign PLVCUDECRVALID0_in = PLVCUDECRVALID0; + assign PLVCUDECRVALID1_in = PLVCUDECRVALID1; + assign PLVCUDECWREADY0_in = PLVCUDECWREADY0; + assign PLVCUDECWREADY1_in = PLVCUDECWREADY1; + assign PLVCUENCALL2CRDATA_in = PLVCUENCALL2CRDATA; + assign PLVCUENCALL2CRREADY_in = (PLVCUENCALL2CRREADY === 1'bz) || PLVCUENCALL2CRREADY; // rv 1 + assign PLVCUENCARREADY0_in = PLVCUENCARREADY0; + assign PLVCUENCARREADY1_in = PLVCUENCARREADY1; + assign PLVCUENCAWREADY0_in = PLVCUENCAWREADY0; + assign PLVCUENCAWREADY1_in = PLVCUENCAWREADY1; + assign PLVCUENCBID0_in = PLVCUENCBID0; + assign PLVCUENCBID1_in = PLVCUENCBID1; + assign PLVCUENCBRESP0_in = PLVCUENCBRESP0; + assign PLVCUENCBRESP1_in = PLVCUENCBRESP1; + assign PLVCUENCBVALID0_in = PLVCUENCBVALID0; + assign PLVCUENCBVALID1_in = PLVCUENCBVALID1; + assign PLVCUENCL2CCLK_in = PLVCUENCL2CCLK; + assign PLVCUENCRDATA0_in = PLVCUENCRDATA0; + assign PLVCUENCRDATA1_in = PLVCUENCRDATA1; + assign PLVCUENCRID0_in = PLVCUENCRID0; + assign PLVCUENCRID1_in = PLVCUENCRID1; + assign PLVCUENCRLAST0_in = PLVCUENCRLAST0; + assign PLVCUENCRLAST1_in = PLVCUENCRLAST1; + assign PLVCUENCRRESP0_in = PLVCUENCRRESP0; + assign PLVCUENCRRESP1_in = PLVCUENCRRESP1; + assign PLVCUENCRVALID0_in = PLVCUENCRVALID0; + assign PLVCUENCRVALID1_in = PLVCUENCRVALID1; + assign PLVCUENCWREADY0_in = PLVCUENCWREADY0; + assign PLVCUENCWREADY1_in = PLVCUENCWREADY1; + assign PLVCUMCUMAXIICDCARREADY_in = PLVCUMCUMAXIICDCARREADY; + assign PLVCUMCUMAXIICDCAWREADY_in = PLVCUMCUMAXIICDCAWREADY; + assign PLVCUMCUMAXIICDCBID_in = PLVCUMCUMAXIICDCBID; + assign PLVCUMCUMAXIICDCBRESP_in = PLVCUMCUMAXIICDCBRESP; + assign PLVCUMCUMAXIICDCBVALID_in = PLVCUMCUMAXIICDCBVALID; + assign PLVCUMCUMAXIICDCRDATA_in = PLVCUMCUMAXIICDCRDATA; + assign PLVCUMCUMAXIICDCRID_in = PLVCUMCUMAXIICDCRID; + assign PLVCUMCUMAXIICDCRLAST_in = PLVCUMCUMAXIICDCRLAST; + assign PLVCUMCUMAXIICDCRRESP_in = PLVCUMCUMAXIICDCRRESP; + assign PLVCUMCUMAXIICDCRVALID_in = PLVCUMCUMAXIICDCRVALID; + assign PLVCUMCUMAXIICDCWREADY_in = PLVCUMCUMAXIICDCWREADY; + assign PLVCURREADYAXILITEAPB_in = PLVCURREADYAXILITEAPB; + assign PLVCUWDATAAXILITEAPB_in = PLVCUWDATAAXILITEAPB; + assign PLVCUWSTRBAXILITEAPB_in = PLVCUWSTRBAXILITEAPB; + assign PLVCUWVALIDAXILITEAPB_in = PLVCUWVALIDAXILITEAPB; +`endif + + assign INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD_in = INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD; + assign PLVCUCORECLK_in = PLVCUCORECLK; + assign PLVCUMCUCLK_in = PLVCUMCUCLK; + assign PLVCUPLLREFCLKPL_in = PLVCUPLLREFCLKPL; + assign PLVCURAWRSTN_in = PLVCURAWRSTN; + +`ifndef XIL_XECLIB + initial begin + #1; + trig_attr = ~trig_attr; + end +`endif + +`ifdef XIL_XECLIB + assign CORECLKREQ_BIN = CORECLKREQ_REG[9:0]; + + assign DECHORRESOLUTION_BIN = DECHORRESOLUTION_REG[13:0]; + + assign DECODERCHROMAFORMAT_BIN = + (DECODERCHROMAFORMAT_REG == "4_2_2") ? DECODERCHROMAFORMAT_4_2_2 : + (DECODERCHROMAFORMAT_REG == "4_2_0") ? DECODERCHROMAFORMAT_4_2_0 : + DECODERCHROMAFORMAT_4_2_2; + + assign DECODERCODING_BIN = + (DECODERCODING_REG == "H.265") ? DECODERCODING_H_265 : + (DECODERCODING_REG == "H.264") ? DECODERCODING_H_264 : + DECODERCODING_H_265; + + assign DECODERCOLORDEPTH_BIN = DECODERCOLORDEPTH_REG[3:0]; + + assign DECODERNUMCORES_BIN = DECODERNUMCORES_REG[1:0]; + + assign DECVERTRESOLUTION_BIN = DECVERTRESOLUTION_REG[12:0]; + + assign ENABLEDECODER_BIN = + (ENABLEDECODER_REG == "TRUE") ? ENABLEDECODER_TRUE : + (ENABLEDECODER_REG == "FALSE") ? ENABLEDECODER_FALSE : + ENABLEDECODER_TRUE; + + assign ENABLEENCODER_BIN = + (ENABLEENCODER_REG == "TRUE") ? ENABLEENCODER_TRUE : + (ENABLEENCODER_REG == "FALSE") ? ENABLEENCODER_FALSE : + ENABLEENCODER_TRUE; + + assign ENCHORRESOLUTION_BIN = ENCHORRESOLUTION_REG[13:0]; + + assign ENCODERCHROMAFORMAT_BIN = + (ENCODERCHROMAFORMAT_REG == "4_2_2") ? ENCODERCHROMAFORMAT_4_2_2 : + (ENCODERCHROMAFORMAT_REG == "4_2_0") ? ENCODERCHROMAFORMAT_4_2_0 : + ENCODERCHROMAFORMAT_4_2_2; + + assign ENCODERCODING_BIN = + (ENCODERCODING_REG == "H.265") ? ENCODERCODING_H_265 : + (ENCODERCODING_REG == "H.264") ? ENCODERCODING_H_264 : + ENCODERCODING_H_265; + + assign ENCODERCOLORDEPTH_BIN = ENCODERCOLORDEPTH_REG[3:0]; + + assign ENCODERNUMCORES_BIN = ENCODERNUMCORES_REG[2:0]; + + assign ENCVERTRESOLUTION_BIN = ENCVERTRESOLUTION_REG[12:0]; + +`else + always @ (trig_attr) begin + #1; + CORECLKREQ_BIN = CORECLKREQ_REG[9:0]; + + DECHORRESOLUTION_BIN = DECHORRESOLUTION_REG[13:0]; + + DECODERCHROMAFORMAT_BIN = + (DECODERCHROMAFORMAT_REG == "4_2_2") ? DECODERCHROMAFORMAT_4_2_2 : + (DECODERCHROMAFORMAT_REG == "4_2_0") ? DECODERCHROMAFORMAT_4_2_0 : + DECODERCHROMAFORMAT_4_2_2; + + DECODERCODING_BIN = + (DECODERCODING_REG == "H.265") ? DECODERCODING_H_265 : + (DECODERCODING_REG == "H.264") ? DECODERCODING_H_264 : + DECODERCODING_H_265; + + DECODERCOLORDEPTH_BIN = DECODERCOLORDEPTH_REG[3:0]; + + DECODERNUMCORES_BIN = DECODERNUMCORES_REG[1:0]; + + DECVERTRESOLUTION_BIN = DECVERTRESOLUTION_REG[12:0]; + + ENABLEDECODER_BIN = + (ENABLEDECODER_REG == "TRUE") ? ENABLEDECODER_TRUE : + (ENABLEDECODER_REG == "FALSE") ? ENABLEDECODER_FALSE : + ENABLEDECODER_TRUE; + + ENABLEENCODER_BIN = + (ENABLEENCODER_REG == "TRUE") ? ENABLEENCODER_TRUE : + (ENABLEENCODER_REG == "FALSE") ? ENABLEENCODER_FALSE : + ENABLEENCODER_TRUE; + + ENCHORRESOLUTION_BIN = ENCHORRESOLUTION_REG[13:0]; + + ENCODERCHROMAFORMAT_BIN = + (ENCODERCHROMAFORMAT_REG == "4_2_2") ? ENCODERCHROMAFORMAT_4_2_2 : + (ENCODERCHROMAFORMAT_REG == "4_2_0") ? ENCODERCHROMAFORMAT_4_2_0 : + ENCODERCHROMAFORMAT_4_2_2; + + ENCODERCODING_BIN = + (ENCODERCODING_REG == "H.265") ? ENCODERCODING_H_265 : + (ENCODERCODING_REG == "H.264") ? ENCODERCODING_H_264 : + ENCODERCODING_H_265; + + ENCODERCOLORDEPTH_BIN = ENCODERCOLORDEPTH_REG[3:0]; + + ENCODERNUMCORES_BIN = ENCODERNUMCORES_REG[2:0]; + + ENCVERTRESOLUTION_BIN = ENCVERTRESOLUTION_REG[12:0]; + + end +`endif + +`ifndef XIL_XECLIB +always @ (trig_attr) begin + #1; + if ((attr_test == 1'b1) || + ((CORECLKREQ_REG < 0) || (CORECLKREQ_REG > 667))) begin + $display("Error: [Unisim %s-101] CORECLKREQ attribute is set to %d. Legal values for this attribute are 0 to 667. Instance: %m", MODULE_NAME, CORECLKREQ_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECHORRESOLUTION_REG < 320) || (DECHORRESOLUTION_REG > 8192))) begin + $display("Error: [Unisim %s-102] DECHORRESOLUTION attribute is set to %d. Legal values for this attribute are 320 to 8192. Instance: %m", MODULE_NAME, DECHORRESOLUTION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECODERCHROMAFORMAT_REG != "4_2_2") && + (DECODERCHROMAFORMAT_REG != "4_2_0"))) begin + $display("Error: [Unisim %s-103] DECODERCHROMAFORMAT attribute is set to %s. Legal values for this attribute are 4_2_2 or 4_2_0. Instance: %m", MODULE_NAME, DECODERCHROMAFORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECODERCODING_REG != "H.265") && + (DECODERCODING_REG != "H.264"))) begin + $display("Error: [Unisim %s-104] DECODERCODING attribute is set to %s. Legal values for this attribute are H.265 or H.264. Instance: %m", MODULE_NAME, DECODERCODING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECODERCOLORDEPTH_REG != 10) && + (DECODERCOLORDEPTH_REG != 8))) begin + $display("Error: [Unisim %s-105] DECODERCOLORDEPTH attribute is set to %d. Legal values for this attribute are 10 or 8. Instance: %m", MODULE_NAME, DECODERCOLORDEPTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECODERNUMCORES_REG < 1) || (DECODERNUMCORES_REG > 2))) begin + $display("Error: [Unisim %s-106] DECODERNUMCORES attribute is set to %d. Legal values for this attribute are 1 to 2. Instance: %m", MODULE_NAME, DECODERNUMCORES_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((DECVERTRESOLUTION_REG < 240) || (DECVERTRESOLUTION_REG > 4352))) begin + $display("Error: [Unisim %s-107] DECVERTRESOLUTION attribute is set to %d. Legal values for this attribute are 240 to 4352. Instance: %m", MODULE_NAME, DECVERTRESOLUTION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENABLEDECODER_REG != "TRUE") && + (ENABLEDECODER_REG != "FALSE"))) begin + $display("Error: [Unisim %s-108] ENABLEDECODER attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ENABLEDECODER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENABLEENCODER_REG != "TRUE") && + (ENABLEENCODER_REG != "FALSE"))) begin + $display("Error: [Unisim %s-109] ENABLEENCODER attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ENABLEENCODER_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCHORRESOLUTION_REG < 320) || (ENCHORRESOLUTION_REG > 8192))) begin + $display("Error: [Unisim %s-110] ENCHORRESOLUTION attribute is set to %d. Legal values for this attribute are 320 to 8192. Instance: %m", MODULE_NAME, ENCHORRESOLUTION_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCODERCHROMAFORMAT_REG != "4_2_2") && + (ENCODERCHROMAFORMAT_REG != "4_2_0"))) begin + $display("Error: [Unisim %s-111] ENCODERCHROMAFORMAT attribute is set to %s. Legal values for this attribute are 4_2_2 or 4_2_0. Instance: %m", MODULE_NAME, ENCODERCHROMAFORMAT_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCODERCODING_REG != "H.265") && + (ENCODERCODING_REG != "H.264"))) begin + $display("Error: [Unisim %s-112] ENCODERCODING attribute is set to %s. Legal values for this attribute are H.265 or H.264. Instance: %m", MODULE_NAME, ENCODERCODING_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCODERCOLORDEPTH_REG != 10) && + (ENCODERCOLORDEPTH_REG != 8))) begin + $display("Error: [Unisim %s-113] ENCODERCOLORDEPTH attribute is set to %d. Legal values for this attribute are 10 or 8. Instance: %m", MODULE_NAME, ENCODERCOLORDEPTH_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCODERNUMCORES_REG < 1) || (ENCODERNUMCORES_REG > 4))) begin + $display("Error: [Unisim %s-114] ENCODERNUMCORES attribute is set to %d. Legal values for this attribute are 1 to 4. Instance: %m", MODULE_NAME, ENCODERNUMCORES_REG); + attr_err = 1'b1; + end + + if ((attr_test == 1'b1) || + ((ENCVERTRESOLUTION_REG < 240) || (ENCVERTRESOLUTION_REG > 4352))) begin + $display("Error: [Unisim %s-115] ENCVERTRESOLUTION attribute is set to %d. Legal values for this attribute are 240 to 4352. Instance: %m", MODULE_NAME, ENCVERTRESOLUTION_REG); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) #1 $finish; +end +`endif + + +`ifndef XIL_XECLIB +`ifdef XIL_TIMING + reg notifier; +`endif + + specify + (PLVCUAXIDECCLK => VCUPLDECARADDR0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARADDR1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARBURST0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARBURST0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARBURST1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARBURST1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARCACHE1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARID1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARLEN1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARPROT0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARPROT1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARQOS1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARSIZE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECARVALID1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWADDR1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWBURST0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWBURST0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWBURST1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWBURST1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWCACHE1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWID1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWLEN1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWPROT0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWPROT1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWQOS1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWSIZE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECAWVALID1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECBREADY0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECBREADY1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECRREADY0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECRREADY1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[100]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[101]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[102]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[103]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[104]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[105]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[106]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[107]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[108]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[109]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[110]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[111]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[112]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[113]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[114]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[115]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[116]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[117]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[118]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[119]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[120]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[121]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[122]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[123]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[124]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[125]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[126]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[127]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[44]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[45]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[46]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[47]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[48]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[49]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[50]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[51]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[52]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[53]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[54]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[55]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[56]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[57]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[58]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[59]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[60]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[61]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[62]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[63]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[64]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[65]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[66]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[67]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[68]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[69]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[70]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[71]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[72]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[73]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[74]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[75]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[76]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[77]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[78]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[79]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[80]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[81]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[82]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[83]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[84]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[85]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[86]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[87]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[88]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[89]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[90]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[91]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[92]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[93]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[94]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[95]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[96]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[97]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[98]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[99]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[100]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[101]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[102]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[103]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[104]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[105]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[106]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[107]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[108]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[109]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[110]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[111]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[112]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[113]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[114]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[115]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[116]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[117]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[118]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[119]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[120]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[121]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[122]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[123]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[124]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[125]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[126]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[127]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[44]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[45]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[46]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[47]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[48]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[49]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[50]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[51]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[52]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[53]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[54]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[55]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[56]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[57]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[58]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[59]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[60]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[61]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[62]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[63]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[64]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[65]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[66]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[67]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[68]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[69]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[70]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[71]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[72]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[73]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[74]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[75]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[76]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[77]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[78]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[79]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[80]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[81]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[82]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[83]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[84]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[85]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[86]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[87]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[88]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[89]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[90]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[91]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[92]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[93]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[94]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[95]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[96]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[97]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[98]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[99]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWDATA1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWLAST0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWLAST1) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIDECCLK => VCUPLDECWVALID1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARADDR1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARBURST0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARBURST0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARBURST1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARBURST1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARCACHE1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARID1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARLEN1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARPROT0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARPROT1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARQOS1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARSIZE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCARVALID1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWADDR1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWBURST0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWBURST0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWBURST1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWBURST1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWCACHE1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWID1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWLEN1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWPROT0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWPROT1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWQOS1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWSIZE1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCAWVALID1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCBREADY0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCBREADY1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCRREADY0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCRREADY1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[100]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[101]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[102]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[103]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[104]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[105]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[106]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[107]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[108]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[109]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[110]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[111]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[112]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[113]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[114]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[115]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[116]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[117]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[118]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[119]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[120]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[121]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[122]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[123]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[124]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[125]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[126]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[127]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[44]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[45]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[46]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[47]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[48]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[49]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[50]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[51]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[52]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[53]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[54]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[55]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[56]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[57]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[58]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[59]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[60]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[61]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[62]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[63]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[64]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[65]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[66]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[67]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[68]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[69]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[70]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[71]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[72]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[73]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[74]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[75]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[76]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[77]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[78]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[79]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[80]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[81]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[82]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[83]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[84]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[85]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[86]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[87]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[88]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[89]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[90]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[91]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[92]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[93]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[94]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[95]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[96]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[97]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[98]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[99]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA0[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[0]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[100]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[101]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[102]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[103]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[104]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[105]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[106]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[107]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[108]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[109]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[10]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[110]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[111]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[112]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[113]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[114]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[115]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[116]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[117]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[118]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[119]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[11]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[120]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[121]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[122]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[123]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[124]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[125]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[126]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[127]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[12]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[13]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[14]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[15]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[16]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[17]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[18]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[19]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[1]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[20]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[21]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[22]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[23]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[24]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[25]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[26]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[27]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[28]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[29]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[2]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[30]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[31]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[32]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[33]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[34]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[35]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[36]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[37]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[38]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[39]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[3]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[40]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[41]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[42]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[43]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[44]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[45]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[46]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[47]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[48]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[49]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[4]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[50]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[51]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[52]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[53]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[54]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[55]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[56]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[57]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[58]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[59]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[5]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[60]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[61]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[62]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[63]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[64]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[65]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[66]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[67]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[68]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[69]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[6]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[70]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[71]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[72]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[73]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[74]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[75]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[76]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[77]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[78]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[79]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[7]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[80]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[81]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[82]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[83]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[84]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[85]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[86]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[87]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[88]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[89]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[8]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[90]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[91]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[92]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[93]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[94]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[95]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[96]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[97]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[98]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[99]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWDATA1[9]) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWLAST0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWLAST1) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWVALID0) = (100:100:100, 100:100:100); + (PLVCUAXIENCCLK => VCUPLENCWVALID1) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLARREADYAXILITEAPB) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLAWREADYAXILITEAPB) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLBRESPAXILITEAPB[0]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLBRESPAXILITEAPB[1]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLBVALIDAXILITEAPB) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLPINTREQ) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[0]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[10]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[11]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[12]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[13]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[14]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[15]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[16]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[17]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[18]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[19]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[1]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[20]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[21]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[22]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[23]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[24]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[25]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[26]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[27]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[28]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[29]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[2]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[30]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[31]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[3]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[4]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[5]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[6]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[7]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[8]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[9]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRRESPAXILITEAPB[0]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRRESPAXILITEAPB[1]) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLRVALIDAXILITEAPB) = (100:100:100, 100:100:100); + (PLVCUAXILITECLK => VCUPLWREADYAXILITEAPB) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[10]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[11]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[12]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[13]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[14]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[15]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[16]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[17]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[18]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[19]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[20]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[21]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[22]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[23]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[24]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[25]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[26]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[27]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[28]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[29]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[30]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[31]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[32]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[33]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[34]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[35]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[36]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[37]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[38]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[39]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[40]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[41]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[42]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[43]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[4]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[5]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[6]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[7]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[8]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[9]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARBURST[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARBURST[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[4]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[5]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[6]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[7]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLOCK) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARVALID) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[10]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[11]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[12]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[13]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[14]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[15]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[16]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[17]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[18]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[19]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[20]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[21]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[22]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[23]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[24]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[25]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[26]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[27]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[28]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[29]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[30]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[31]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[32]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[33]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[34]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[35]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[36]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[37]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[38]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[39]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[40]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[41]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[42]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[43]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[4]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[5]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[6]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[7]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[8]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[9]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWBURST[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWBURST[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[4]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[5]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[6]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[7]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLOCK) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWVALID) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCBREADY) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCRREADY) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[10]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[11]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[12]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[13]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[14]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[15]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[16]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[17]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[18]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[19]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[20]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[21]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[22]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[23]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[24]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[25]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[26]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[27]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[28]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[29]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[30]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[31]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[4]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[5]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[6]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[7]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[8]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[9]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWLAST) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[0]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[1]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[2]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[3]) = (100:100:100, 100:100:100); + (PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWVALID) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[0]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[10]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[11]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[12]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[13]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[14]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[15]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[16]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[1]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[2]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[3]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[4]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[5]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[6]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[7]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[8]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CADDR[9]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CRVALID) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[0]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[100]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[101]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[102]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[103]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[104]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[105]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[106]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[107]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[108]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[109]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[10]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[110]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[111]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[112]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[113]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[114]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[115]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[116]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[117]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[118]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[119]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[11]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[120]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[121]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[122]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[123]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[124]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[125]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[126]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[127]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[128]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[129]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[12]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[130]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[131]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[132]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[133]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[134]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[135]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[136]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[137]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[138]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[139]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[13]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[140]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[141]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[142]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[143]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[144]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[145]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[146]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[147]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[148]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[149]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[14]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[150]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[151]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[152]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[153]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[154]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[155]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[156]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[157]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[158]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[159]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[15]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[160]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[161]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[162]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[163]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[164]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[165]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[166]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[167]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[168]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[169]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[16]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[170]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[171]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[172]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[173]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[174]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[175]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[176]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[177]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[178]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[179]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[17]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[180]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[181]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[182]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[183]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[184]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[185]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[186]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[187]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[188]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[189]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[18]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[190]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[191]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[192]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[193]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[194]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[195]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[196]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[197]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[198]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[199]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[19]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[1]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[200]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[201]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[202]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[203]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[204]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[205]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[206]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[207]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[208]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[209]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[20]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[210]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[211]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[212]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[213]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[214]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[215]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[216]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[217]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[218]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[219]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[21]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[220]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[221]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[222]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[223]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[224]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[225]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[226]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[227]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[228]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[229]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[22]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[230]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[231]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[232]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[233]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[234]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[235]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[236]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[237]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[238]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[239]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[23]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[240]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[241]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[242]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[243]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[244]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[245]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[246]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[247]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[248]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[249]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[24]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[250]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[251]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[252]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[253]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[254]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[255]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[256]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[257]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[258]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[259]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[25]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[260]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[261]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[262]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[263]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[264]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[265]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[266]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[267]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[268]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[269]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[26]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[270]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[271]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[272]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[273]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[274]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[275]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[276]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[277]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[278]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[279]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[27]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[280]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[281]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[282]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[283]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[284]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[285]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[286]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[287]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[288]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[289]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[28]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[290]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[291]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[292]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[293]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[294]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[295]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[296]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[297]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[298]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[299]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[29]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[2]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[300]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[301]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[302]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[303]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[304]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[305]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[306]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[307]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[308]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[309]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[30]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[310]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[311]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[312]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[313]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[314]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[315]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[316]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[317]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[318]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[319]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[31]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[32]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[33]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[34]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[35]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[36]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[37]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[38]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[39]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[3]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[40]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[41]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[42]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[43]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[44]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[45]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[46]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[47]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[48]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[49]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[4]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[50]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[51]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[52]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[53]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[54]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[55]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[56]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[57]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[58]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[59]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[5]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[60]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[61]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[62]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[63]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[64]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[65]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[66]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[67]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[68]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[69]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[6]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[70]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[71]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[72]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[73]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[74]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[75]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[76]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[77]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[78]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[79]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[7]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[80]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[81]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[82]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[83]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[84]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[85]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[86]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[87]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[88]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[89]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[8]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[90]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[91]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[92]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[93]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[94]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[95]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[96]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[97]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[98]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[99]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[9]) = (100:100:100, 100:100:100); + (PLVCUENCL2CCLK => VCUPLENCALL2CWVALID) = (100:100:100, 100:100:100); +`ifdef XIL_TIMING + $period (negedge PLVCUAXIDECCLK, 0:0:0, notifier); + $period (negedge PLVCUAXIENCCLK, 0:0:0, notifier); + $period (negedge PLVCUAXILITECLK, 0:0:0, notifier); + $period (negedge PLVCUAXIMCUCLK, 0:0:0, notifier); + $period (negedge PLVCUCORECLK, 0:0:0, notifier); + $period (negedge PLVCUENCL2CCLK, 0:0:0, notifier); + $period (negedge PLVCUMCUCLK, 0:0:0, notifier); + $period (negedge PLVCUPLLREFCLKPL, 0:0:0, notifier); + $period (negedge VCUPLCORESTATUSCLKPLL, 0:0:0, notifier); + $period (negedge VCUPLMCUSTATUSCLKPLL, 0:0:0, notifier); + $period (posedge PLVCUAXIDECCLK, 0:0:0, notifier); + $period (posedge PLVCUAXIENCCLK, 0:0:0, notifier); + $period (posedge PLVCUAXILITECLK, 0:0:0, notifier); + $period (posedge PLVCUAXIMCUCLK, 0:0:0, notifier); + $period (posedge PLVCUCORECLK, 0:0:0, notifier); + $period (posedge PLVCUENCL2CCLK, 0:0:0, notifier); + $period (posedge PLVCUMCUCLK, 0:0:0, notifier); + $period (posedge PLVCUPLLREFCLKPL, 0:0:0, notifier); + $period (posedge VCUPLCORESTATUSCLKPLL, 0:0:0, notifier); + $period (posedge VCUPLMCUSTATUSCLKPLL, 0:0:0, notifier); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY1_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY1_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID1_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[100]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[101]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[102]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[103]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[104]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[105]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[106]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[107]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[108]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[109]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[10]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[110]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[111]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[112]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[113]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[114]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[115]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[116]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[117]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[118]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[119]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[11]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[120]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[121]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[122]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[123]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[124]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[125]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[126]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[127]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[12]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[13]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[14]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[15]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[16]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[17]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[18]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[19]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[20]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[21]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[22]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[23]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[24]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[25]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[26]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[27]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[28]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[29]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[30]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[31]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[32]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[33]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[34]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[35]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[36]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[37]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[38]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[39]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[40]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[41]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[42]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[43]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[44]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[45]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[46]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[47]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[48]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[49]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[4]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[50]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[51]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[52]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[53]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[54]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[55]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[56]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[57]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[58]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[59]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[5]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[60]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[61]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[62]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[63]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[64]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[65]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[66]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[67]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[68]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[69]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[6]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[70]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[71]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[72]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[73]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[74]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[75]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[76]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[77]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[78]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[79]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[7]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[80]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[81]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[82]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[83]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[84]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[85]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[86]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[87]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[88]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[89]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[8]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[90]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[91]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[92]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[93]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[94]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[95]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[96]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[97]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[98]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[99]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[9]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[100]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[101]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[102]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[103]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[104]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[105]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[106]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[107]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[108]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[109]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[10]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[110]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[111]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[112]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[113]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[114]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[115]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[116]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[117]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[118]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[119]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[11]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[120]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[121]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[122]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[123]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[124]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[125]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[126]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[127]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[12]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[13]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[14]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[15]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[16]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[17]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[18]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[19]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[20]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[21]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[22]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[23]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[24]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[25]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[26]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[27]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[28]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[29]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[30]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[31]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[32]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[33]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[34]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[35]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[36]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[37]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[38]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[39]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[40]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[41]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[42]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[43]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[44]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[45]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[46]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[47]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[48]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[49]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[4]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[50]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[51]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[52]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[53]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[54]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[55]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[56]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[57]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[58]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[59]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[5]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[60]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[61]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[62]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[63]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[64]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[65]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[66]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[67]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[68]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[69]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[6]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[70]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[71]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[72]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[73]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[74]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[75]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[76]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[77]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[78]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[79]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[7]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[80]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[81]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[82]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[83]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[84]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[85]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[86]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[87]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[88]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[89]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[8]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[90]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[91]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[92]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[93]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[94]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[95]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[96]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[97]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[98]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[99]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[9]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST1_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID1_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[100]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[101]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[102]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[103]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[104]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[105]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[106]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[107]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[108]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[109]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[10]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[110]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[111]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[112]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[113]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[114]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[115]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[116]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[117]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[118]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[119]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[11]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[120]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[121]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[122]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[123]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[124]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[125]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[126]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[127]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[12]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[13]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[14]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[15]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[16]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[17]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[18]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[19]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[20]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[21]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[22]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[23]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[24]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[25]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[26]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[27]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[28]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[29]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[30]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[31]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[32]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[33]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[34]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[35]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[36]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[37]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[38]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[39]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[40]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[41]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[42]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[43]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[44]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[45]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[46]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[47]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[48]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[49]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[4]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[50]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[51]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[52]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[53]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[54]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[55]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[56]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[57]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[58]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[59]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[5]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[60]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[61]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[62]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[63]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[64]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[65]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[66]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[67]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[68]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[69]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[6]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[70]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[71]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[72]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[73]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[74]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[75]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[76]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[77]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[78]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[79]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[7]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[80]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[81]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[82]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[83]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[84]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[85]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[86]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[87]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[88]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[89]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[8]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[90]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[91]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[92]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[93]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[94]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[95]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[96]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[97]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[98]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[99]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[9]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[100]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[101]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[102]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[103]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[104]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[105]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[106]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[107]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[108]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[109]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[10]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[110]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[111]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[112]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[113]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[114]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[115]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[116]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[117]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[118]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[119]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[11]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[120]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[121]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[122]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[123]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[124]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[125]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[126]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[127]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[12]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[13]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[14]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[15]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[16]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[17]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[18]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[19]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[20]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[21]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[22]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[23]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[24]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[25]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[26]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[27]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[28]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[29]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[30]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[31]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[32]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[33]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[34]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[35]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[36]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[37]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[38]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[39]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[40]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[41]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[42]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[43]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[44]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[45]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[46]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[47]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[48]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[49]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[4]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[50]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[51]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[52]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[53]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[54]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[55]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[56]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[57]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[58]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[59]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[5]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[60]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[61]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[62]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[63]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[64]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[65]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[66]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[67]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[68]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[69]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[6]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[70]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[71]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[72]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[73]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[74]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[75]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[76]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[77]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[78]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[79]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[7]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[80]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[81]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[82]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[83]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[84]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[85]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[86]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[87]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[88]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[89]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[8]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[90]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[91]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[92]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[93]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[94]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[95]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[96]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[97]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[98]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[99]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[9]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[0]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[2]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[3]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP0_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP1_delay[1]); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID1_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY0_delay); + $setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[100]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[101]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[102]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[103]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[104]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[105]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[106]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[107]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[108]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[109]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[10]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[110]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[111]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[112]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[113]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[114]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[115]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[116]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[117]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[118]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[119]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[11]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[120]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[121]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[122]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[123]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[124]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[125]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[126]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[127]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[12]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[13]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[14]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[15]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[16]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[17]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[18]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[19]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[20]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[21]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[22]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[23]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[24]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[25]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[26]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[27]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[28]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[29]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[30]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[31]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[32]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[33]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[34]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[35]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[36]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[37]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[38]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[39]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[40]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[41]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[42]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[43]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[44]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[45]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[46]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[47]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[48]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[49]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[4]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[50]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[51]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[52]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[53]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[54]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[55]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[56]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[57]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[58]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[59]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[5]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[60]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[61]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[62]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[63]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[64]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[65]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[66]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[67]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[68]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[69]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[6]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[70]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[71]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[72]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[73]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[74]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[75]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[76]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[77]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[78]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[79]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[7]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[80]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[81]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[82]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[83]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[84]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[85]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[86]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[87]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[88]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[89]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[8]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[90]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[91]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[92]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[93]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[94]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[95]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[96]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[97]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[98]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[99]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[9]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[100]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[101]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[102]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[103]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[104]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[105]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[106]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[107]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[108]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[109]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[10]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[110]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[111]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[112]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[113]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[114]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[115]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[116]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[117]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[118]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[119]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[11]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[120]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[121]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[122]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[123]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[124]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[125]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[126]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[127]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[12]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[13]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[14]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[15]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[16]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[17]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[18]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[19]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[20]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[21]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[22]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[23]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[24]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[25]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[26]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[27]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[28]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[29]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[30]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[31]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[32]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[33]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[34]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[35]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[36]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[37]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[38]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[39]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[40]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[41]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[42]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[43]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[44]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[45]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[46]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[47]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[48]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[49]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[4]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[50]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[51]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[52]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[53]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[54]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[55]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[56]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[57]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[58]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[59]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[5]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[60]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[61]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[62]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[63]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[64]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[65]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[66]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[67]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[68]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[69]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[6]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[70]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[71]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[72]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[73]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[74]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[75]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[76]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[77]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[78]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[79]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[7]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[80]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[81]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[82]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[83]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[84]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[85]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[86]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[87]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[88]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[89]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[8]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[90]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[91]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[92]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[93]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[94]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[95]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[96]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[97]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[98]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[99]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[9]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID1_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[100]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[101]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[102]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[103]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[104]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[105]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[106]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[107]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[108]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[109]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[10]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[110]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[111]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[112]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[113]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[114]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[115]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[116]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[117]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[118]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[119]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[11]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[120]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[121]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[122]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[123]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[124]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[125]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[126]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[127]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[12]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[13]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[14]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[15]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[16]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[17]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[18]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[19]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[20]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[21]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[22]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[23]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[24]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[25]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[26]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[27]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[28]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[29]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[30]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[31]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[32]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[33]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[34]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[35]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[36]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[37]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[38]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[39]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[40]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[41]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[42]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[43]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[44]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[45]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[46]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[47]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[48]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[49]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[4]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[50]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[51]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[52]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[53]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[54]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[55]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[56]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[57]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[58]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[59]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[5]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[60]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[61]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[62]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[63]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[64]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[65]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[66]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[67]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[68]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[69]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[6]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[70]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[71]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[72]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[73]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[74]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[75]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[76]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[77]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[78]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[79]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[7]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[80]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[81]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[82]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[83]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[84]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[85]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[86]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[87]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[88]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[89]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[8]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[90]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[91]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[92]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[93]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[94]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[95]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[96]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[97]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[98]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[99]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[9]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[100]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[101]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[102]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[103]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[104]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[105]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[106]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[107]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[108]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[109]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[10]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[110]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[111]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[112]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[113]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[114]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[115]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[116]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[117]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[118]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[119]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[11]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[120]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[121]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[122]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[123]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[124]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[125]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[126]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[127]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[12]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[13]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[14]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[15]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[16]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[17]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[18]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[19]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[20]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[21]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[22]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[23]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[24]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[25]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[26]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[27]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[28]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[29]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[30]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[31]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[32]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[33]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[34]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[35]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[36]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[37]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[38]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[39]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[40]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[41]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[42]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[43]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[44]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[45]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[46]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[47]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[48]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[49]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[4]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[50]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[51]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[52]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[53]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[54]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[55]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[56]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[57]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[58]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[59]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[5]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[60]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[61]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[62]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[63]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[64]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[65]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[66]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[67]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[68]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[69]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[6]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[70]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[71]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[72]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[73]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[74]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[75]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[76]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[77]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[78]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[79]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[7]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[80]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[81]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[82]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[83]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[84]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[85]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[86]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[87]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[88]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[89]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[8]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[90]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[91]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[92]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[93]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[94]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[95]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[96]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[97]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[98]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[99]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[9]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[0]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[2]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[3]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP0_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP1_delay[1]); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID1_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY0_delay); + $setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY1_delay); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUBREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUBREADYAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCURREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCURREADYAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[20]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[21]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[22]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[23]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[24]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[25]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[26]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[27]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[28]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[29]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[30]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[31]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUBREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUBREADYAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCURREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCURREADYAXILITEAPB_delay); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[10]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[11]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[12]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[13]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[14]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[15]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[16]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[17]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[18]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[19]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[20]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[21]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[22]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[23]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[24]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[25]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[26]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[27]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[28]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[29]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[30]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[31]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[4]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[5]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[6]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[7]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[8]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[9]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[0]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[1]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[2]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[3]); + $setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWVALIDAXILITEAPB_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCARREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCARREADY_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCAWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCAWREADY_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBVALID_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[10]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[11]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[12]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[13]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[14]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[15]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[16]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[17]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[18]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[19]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[20]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[21]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[22]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[23]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[24]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[25]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[26]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[27]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[28]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[29]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[30]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[31]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[3]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[4]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[5]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[6]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[7]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[8]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[9]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRLAST, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRLAST_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRVALID_delay); + $setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCWREADY_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCARREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCARREADY_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCAWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCAWREADY_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBVALID_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[10]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[11]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[12]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[13]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[14]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[15]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[16]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[17]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[18]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[19]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[20]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[21]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[22]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[23]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[24]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[25]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[26]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[27]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[28]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[29]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[30]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[31]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[3]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[4]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[5]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[6]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[7]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[8]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[9]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[2]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRLAST, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRLAST_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[0]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[1]); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRVALID_delay); + $setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCWREADY_delay); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[0]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[100], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[100]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[101], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[101]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[102], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[102]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[103], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[103]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[104], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[104]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[105], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[105]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[106], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[106]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[107], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[107]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[108], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[108]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[109], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[109]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[10]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[110], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[110]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[111], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[111]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[112], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[112]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[113], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[113]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[114], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[114]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[115], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[115]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[116], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[116]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[117], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[117]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[118], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[118]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[119], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[119]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[11]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[120], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[120]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[121], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[121]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[122], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[122]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[123], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[123]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[124], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[124]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[125], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[125]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[126], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[126]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[127], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[127]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[128], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[128]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[129], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[129]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[12]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[130], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[130]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[131], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[131]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[132], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[132]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[133], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[133]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[134], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[134]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[135], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[135]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[136], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[136]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[137], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[137]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[138], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[138]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[139], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[139]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[13]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[140], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[140]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[141], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[141]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[142], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[142]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[143], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[143]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[144], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[144]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[145], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[145]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[146], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[146]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[147], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[147]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[148], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[148]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[149], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[149]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[14]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[150], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[150]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[151], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[151]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[152], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[152]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[153], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[153]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[154], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[154]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[155], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[155]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[156], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[156]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[157], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[157]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[158], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[158]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[159], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[159]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[15]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[160], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[160]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[161], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[161]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[162], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[162]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[163], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[163]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[164], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[164]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[165], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[165]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[166], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[166]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[167], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[167]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[168], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[168]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[169], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[169]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[16]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[170], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[170]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[171], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[171]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[172], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[172]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[173], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[173]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[174], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[174]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[175], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[175]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[176], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[176]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[177], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[177]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[178], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[178]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[179], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[179]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[17]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[180], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[180]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[181], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[181]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[182], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[182]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[183], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[183]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[184], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[184]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[185], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[185]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[186], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[186]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[187], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[187]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[188], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[188]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[189], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[189]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[18]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[190], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[190]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[191], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[191]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[192], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[192]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[193], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[193]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[194], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[194]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[195], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[195]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[196], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[196]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[197], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[197]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[198], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[198]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[199], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[199]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[19]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[1]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[200], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[200]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[201], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[201]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[202], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[202]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[203], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[203]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[204], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[204]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[205], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[205]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[206], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[206]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[207], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[207]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[208], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[208]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[209], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[209]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[20]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[210], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[210]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[211], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[211]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[212], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[212]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[213], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[213]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[214], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[214]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[215], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[215]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[216], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[216]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[217], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[217]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[218], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[218]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[219], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[219]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[21]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[220], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[220]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[221], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[221]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[222], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[222]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[223], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[223]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[224], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[224]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[225], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[225]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[226], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[226]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[227], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[227]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[228], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[228]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[229], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[229]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[22]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[230], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[230]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[231], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[231]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[232], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[232]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[233], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[233]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[234], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[234]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[235], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[235]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[236], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[236]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[237], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[237]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[238], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[238]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[239], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[239]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[23]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[240], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[240]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[241], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[241]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[242], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[242]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[243], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[243]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[244], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[244]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[245], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[245]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[246], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[246]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[247], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[247]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[248], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[248]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[249], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[249]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[24]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[250], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[250]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[251], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[251]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[252], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[252]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[253], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[253]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[254], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[254]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[255], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[255]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[256], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[256]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[257], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[257]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[258], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[258]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[259], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[259]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[25]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[260], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[260]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[261], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[261]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[262], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[262]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[263], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[263]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[264], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[264]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[265], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[265]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[266], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[266]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[267], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[267]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[268], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[268]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[269], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[269]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[26]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[270], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[270]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[271], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[271]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[272], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[272]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[273], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[273]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[274], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[274]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[275], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[275]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[276], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[276]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[277], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[277]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[278], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[278]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[279], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[279]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[27]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[280], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[280]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[281], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[281]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[282], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[282]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[283], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[283]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[284], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[284]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[285], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[285]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[286], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[286]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[287], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[287]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[288], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[288]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[289], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[289]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[28]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[290], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[290]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[291], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[291]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[292], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[292]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[293], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[293]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[294], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[294]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[295], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[295]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[296], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[296]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[297], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[297]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[298], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[298]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[299], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[299]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[29]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[2]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[300], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[300]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[301], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[301]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[302], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[302]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[303], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[303]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[304], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[304]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[305], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[305]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[306], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[306]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[307], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[307]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[308], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[308]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[309], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[309]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[30]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[310], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[310]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[311], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[311]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[312], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[312]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[313], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[313]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[314], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[314]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[315], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[315]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[316], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[316]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[317], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[317]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[318], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[318]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[319], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[319]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[31]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[32], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[32]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[33], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[33]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[34], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[34]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[35], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[35]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[36], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[36]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[37], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[37]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[38], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[38]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[39], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[39]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[3]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[40], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[40]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[41], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[41]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[42], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[42]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[43], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[43]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[44], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[44]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[45], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[45]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[46], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[46]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[47], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[47]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[48], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[48]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[49], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[49]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[4]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[50], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[50]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[51], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[51]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[52], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[52]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[53], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[53]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[54], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[54]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[55], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[55]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[56], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[56]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[57], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[57]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[58], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[58]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[59], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[59]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[5]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[60], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[60]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[61], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[61]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[62], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[62]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[63], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[63]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[64], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[64]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[65], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[65]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[66], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[66]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[67], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[67]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[68], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[68]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[69], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[69]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[6]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[70], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[70]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[71], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[71]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[72], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[72]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[73], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[73]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[74], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[74]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[75], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[75]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[76], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[76]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[77], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[77]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[78], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[78]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[79], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[79]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[7]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[80], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[80]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[81], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[81]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[82], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[82]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[83], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[83]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[84], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[84]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[85], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[85]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[86], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[86]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[87], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[87]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[88], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[88]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[89], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[89]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[8]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[90], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[90]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[91], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[91]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[92], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[92]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[93], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[93]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[94], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[94]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[95], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[95]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[96], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[96]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[97], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[97]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[98], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[98]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[99], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[99]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[9]); + $setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRREADY, 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRREADY_delay); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[0]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[100], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[100]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[101], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[101]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[102], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[102]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[103], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[103]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[104], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[104]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[105], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[105]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[106], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[106]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[107], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[107]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[108], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[108]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[109], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[109]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[10]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[110], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[110]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[111], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[111]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[112], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[112]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[113], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[113]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[114], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[114]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[115], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[115]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[116], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[116]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[117], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[117]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[118], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[118]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[119], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[119]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[11]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[120], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[120]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[121], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[121]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[122], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[122]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[123], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[123]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[124], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[124]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[125], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[125]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[126], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[126]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[127], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[127]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[128], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[128]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[129], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[129]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[12]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[130], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[130]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[131], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[131]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[132], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[132]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[133], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[133]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[134], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[134]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[135], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[135]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[136], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[136]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[137], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[137]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[138], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[138]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[139], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[139]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[13]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[140], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[140]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[141], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[141]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[142], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[142]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[143], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[143]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[144], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[144]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[145], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[145]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[146], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[146]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[147], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[147]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[148], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[148]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[149], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[149]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[14]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[150], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[150]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[151], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[151]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[152], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[152]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[153], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[153]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[154], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[154]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[155], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[155]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[156], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[156]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[157], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[157]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[158], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[158]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[159], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[159]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[15]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[160], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[160]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[161], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[161]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[162], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[162]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[163], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[163]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[164], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[164]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[165], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[165]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[166], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[166]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[167], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[167]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[168], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[168]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[169], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[169]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[16]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[170], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[170]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[171], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[171]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[172], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[172]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[173], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[173]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[174], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[174]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[175], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[175]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[176], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[176]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[177], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[177]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[178], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[178]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[179], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[179]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[17]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[180], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[180]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[181], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[181]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[182], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[182]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[183], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[183]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[184], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[184]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[185], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[185]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[186], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[186]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[187], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[187]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[188], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[188]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[189], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[189]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[18]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[190], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[190]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[191], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[191]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[192], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[192]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[193], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[193]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[194], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[194]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[195], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[195]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[196], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[196]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[197], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[197]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[198], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[198]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[199], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[199]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[19]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[1]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[200], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[200]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[201], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[201]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[202], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[202]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[203], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[203]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[204], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[204]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[205], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[205]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[206], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[206]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[207], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[207]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[208], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[208]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[209], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[209]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[20]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[210], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[210]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[211], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[211]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[212], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[212]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[213], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[213]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[214], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[214]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[215], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[215]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[216], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[216]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[217], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[217]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[218], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[218]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[219], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[219]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[21]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[220], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[220]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[221], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[221]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[222], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[222]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[223], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[223]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[224], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[224]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[225], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[225]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[226], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[226]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[227], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[227]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[228], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[228]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[229], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[229]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[22]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[230], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[230]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[231], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[231]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[232], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[232]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[233], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[233]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[234], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[234]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[235], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[235]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[236], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[236]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[237], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[237]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[238], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[238]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[239], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[239]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[23]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[240], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[240]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[241], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[241]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[242], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[242]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[243], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[243]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[244], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[244]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[245], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[245]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[246], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[246]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[247], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[247]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[248], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[248]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[249], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[249]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[24]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[250], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[250]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[251], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[251]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[252], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[252]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[253], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[253]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[254], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[254]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[255], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[255]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[256], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[256]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[257], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[257]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[258], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[258]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[259], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[259]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[25]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[260], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[260]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[261], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[261]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[262], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[262]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[263], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[263]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[264], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[264]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[265], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[265]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[266], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[266]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[267], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[267]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[268], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[268]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[269], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[269]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[26]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[270], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[270]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[271], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[271]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[272], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[272]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[273], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[273]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[274], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[274]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[275], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[275]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[276], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[276]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[277], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[277]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[278], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[278]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[279], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[279]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[27]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[280], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[280]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[281], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[281]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[282], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[282]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[283], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[283]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[284], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[284]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[285], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[285]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[286], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[286]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[287], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[287]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[288], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[288]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[289], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[289]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[28]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[290], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[290]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[291], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[291]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[292], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[292]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[293], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[293]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[294], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[294]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[295], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[295]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[296], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[296]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[297], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[297]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[298], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[298]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[299], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[299]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[29]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[2]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[300], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[300]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[301], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[301]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[302], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[302]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[303], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[303]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[304], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[304]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[305], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[305]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[306], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[306]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[307], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[307]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[308], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[308]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[309], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[309]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[30]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[310], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[310]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[311], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[311]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[312], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[312]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[313], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[313]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[314], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[314]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[315], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[315]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[316], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[316]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[317], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[317]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[318], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[318]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[319], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[319]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[31]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[32], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[32]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[33], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[33]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[34], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[34]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[35], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[35]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[36], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[36]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[37], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[37]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[38], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[38]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[39], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[39]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[3]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[40], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[40]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[41], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[41]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[42], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[42]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[43], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[43]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[44], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[44]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[45], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[45]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[46], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[46]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[47], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[47]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[48], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[48]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[49], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[49]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[4]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[50], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[50]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[51], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[51]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[52], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[52]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[53], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[53]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[54], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[54]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[55], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[55]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[56], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[56]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[57], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[57]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[58], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[58]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[59], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[59]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[5]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[60], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[60]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[61], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[61]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[62], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[62]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[63], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[63]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[64], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[64]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[65], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[65]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[66], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[66]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[67], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[67]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[68], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[68]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[69], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[69]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[6]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[70], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[70]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[71], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[71]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[72], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[72]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[73], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[73]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[74], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[74]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[75], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[75]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[76], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[76]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[77], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[77]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[78], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[78]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[79], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[79]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[7]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[80], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[80]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[81], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[81]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[82], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[82]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[83], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[83]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[84], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[84]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[85], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[85]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[86], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[86]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[87], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[87]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[88], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[88]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[89], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[89]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[8]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[90], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[90]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[91], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[91]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[92], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[92]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[93], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[93]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[94], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[94]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[95], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[95]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[96], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[96]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[97], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[97]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[98], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[98]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[99], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[99]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[9]); + $setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRREADY, 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRREADY_delay); + $width (negedge PLVCUAXIDECCLK, 0:0:0, 0, notifier); + $width (negedge PLVCUAXIENCCLK, 0:0:0, 0, notifier); + $width (negedge PLVCUAXILITECLK, 0:0:0, 0, notifier); + $width (negedge PLVCUAXIMCUCLK, 0:0:0, 0, notifier); + $width (negedge PLVCUCORECLK, 0:0:0, 0, notifier); + $width (negedge PLVCUENCL2CCLK, 0:0:0, 0, notifier); + $width (negedge PLVCUMCUCLK, 0:0:0, 0, notifier); + $width (negedge PLVCUPLLREFCLKPL, 0:0:0, 0, notifier); + $width (posedge PLVCUAXIDECCLK, 0:0:0, 0, notifier); + $width (posedge PLVCUAXIENCCLK, 0:0:0, 0, notifier); + $width (posedge PLVCUAXILITECLK, 0:0:0, 0, notifier); + $width (posedge PLVCUAXIMCUCLK, 0:0:0, 0, notifier); + $width (posedge PLVCUCORECLK, 0:0:0, 0, notifier); + $width (posedge PLVCUENCL2CCLK, 0:0:0, 0, notifier); + $width (posedge PLVCUMCUCLK, 0:0:0, 0, notifier); + $width (posedge PLVCUPLLREFCLKPL, 0:0:0, 0, notifier); +`endif + specparam PATHPULSE$ = 0; + endspecify +`endif +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/XADC.v b/verilog/src/unisims/XADC.v new file mode 100644 index 0000000..496f03b --- /dev/null +++ b/verilog/src/unisims/XADC.v @@ -0,0 +1,3136 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2015 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 2015.2 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / System Monitor +// /___/ /\ Filename : XADC.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 12/09/09 - Initial version. +// 05/24/10 - Correctly write result to data_reg for ADC2 (CR561364) +// 08/02/10 - Not generate eoc_out2 when ADC2 not used (CR568374) +// 09/09/10 - Change to bus timing +// 10/15/10 - use 273.15 for temperature calculation (CR579001) +// 10/22/10 - Add BUSY to EOS to 18 DCLK instead of 11 (CR579591) +// Extend calibration cycle to 4 conversions (CR580176) +// 11/11/10 - Match hardware (CR580660 580663 580598) +// 11/16/10 - Set seq_num=5 for sequence mode 0000 (CR579051) +// 11/29/10 - Using curr_chan_lat for data_reg update due to extend of +// eoc (CR581758) +// 12/01/10 - Set analog data to fixed channel for external mux and +// simultaneous sampling mode. (CR580598) +// 12/09/10 - Remove check for clock divider (CR586253) +// 03/03/11 - Add VCCPINT VCCPAUX VCCDDRO channel and SIM_DEVICE attibute +// (CR593005) +// 03/03/11 - disable timing check when RESET=1 (CR594618) +// 03/22/11 - use INIT_53 for ot upper limit (CR602195) +// 03/28/11 - Set data_reg range to 47:0 (CR603247) +// 03/29/11 - Set column_real range to 42:0 (CR602520) +// 08/26/11 - Change ot_limit_reg to CA3h(125 C) (CR623029) +// Allow tmp_dr_sram_out out when address 58h (CR623028) +// 09/13/11 - Add ZYNQ to SIM_DEVICE (CR624910) +// Add curr_seq2_tmps for simultaneous mode (CR621932) +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 04/05/12 - Fixed specify block to handle X's (CR 654692). +// 09/26/12 - Removed DRC for event-driven/continuous sampling mode (CR 680075). +// 10/08/12 - Fixed single pass sequence mode (CR 675227). +// 01/18/13 - Added DRP monitor (CR 695630). +// 07/26/13 - Added invertible pins support (CR 715417). +// 08/29/13 - Updated undefined address location (CR 719013). +// 10/28/13 - Removed DRC for event mode timing (CR 736315). +// 11/20/13 - Updated VBRAM to VCCBRAM (CR 755167). +// 01/09/14 - Updated to take both VBRAM and VCCBRAM (CR 767734). +// 03/20/14 - Fixed event driven mode in single pass sequence (CR 764936). +// 03/21/14 - Balanced all inputs with xor (CR 778933). +// 04/30/14 - Initialized chan_val and chan_valn (CR 782388). +// 06/17/14 - Fixed default mode sequencer (CR 800173). +// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. +// 10/22/14 - Added #1 to $finish (CR 808642). +// 02/04/15 - Fixed DO output with DCLK division 4 or lower (CR 840852). +// 02/27/15 - Fixed alarm in independent ADC mode (CR 847176). +// 06/04/15 - 865391 - Model feature to allow sequence updates without reset +// End Revision + + +`timescale 1ps / 1ps + +`celldefine + +module XADC ( + ALM, + BUSY, + CHANNEL, + DO, + DRDY, + EOC, + EOS, + JTAGBUSY, + JTAGLOCKED, + JTAGMODIFIED, + MUXADDR, + OT, + CONVST, + CONVSTCLK, + DADDR, + DCLK, + DEN, + DI, + DWE, + RESET, + VAUXN, + VAUXP, + VN, + VP + +); + + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [7:0] ALM; + output [4:0] CHANNEL; + output [4:0] MUXADDR; + + input CONVST; + input CONVSTCLK; + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; + + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + parameter IS_CONVSTCLK_INVERTED = 1'b0; + parameter IS_DCLK_INVERTED = 1'b0; + parameter SIM_DEVICE = "7SERIES"; + parameter SIM_MONITOR_FILE = "design.txt"; + + `ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + + `endif // + + localparam S1_ST = 0, + S6_ST = 1, + S2_ST = 2, + S3_ST = 3, + S5_ST = 5, + S4_ST = 6; + + time time_out; + time prev_time_out; + + integer temperature_index = -1, time_index = -1, vccaux_index = -1; + integer vccbram_index = -1; + integer vccint_index = -1, vn_index = -1, vp_index = -1; + integer vccpint_index = -1; + integer vccpaux_index = -1; + integer vccpdro_index = -1; + integer vauxp_idx0 = -1; + integer vauxn_idx0 = -1; + integer vauxp_idx1 = -1; + integer vauxn_idx1 = -1; + integer vauxp_idx2 = -1; + integer vauxn_idx2 = -1; + integer vauxp_idx3 = -1; + integer vauxn_idx3 = -1; + integer vauxp_idx4 = -1; + integer vauxn_idx4 = -1; + integer vauxp_idx5 = -1; + integer vauxn_idx5 = -1; + integer vauxp_idx6 = -1; + integer vauxn_idx6 = -1; + integer vauxp_idx7 = -1; + integer vauxn_idx7 = -1; + integer vauxp_idx8 = -1; + integer vauxn_idx8 = -1; + integer vauxp_idx9 = -1; + integer vauxn_idx9 = -1; + integer vauxp_idx10 = -1; + integer vauxn_idx10 = -1; + integer vauxp_idx11 = -1; + integer vauxn_idx11 = -1; + integer vauxp_idx12 = -1; + integer vauxn_idx12 = -1; + integer vauxp_idx13 = -1; + integer vauxn_idx13 = -1; + integer vauxp_idx14 = -1; + integer vauxn_idx14 = -1; + integer vauxp_idx15 = -1; + integer vauxn_idx15 = -1; + integer num_arg; + integer num_val; + integer clk_count; + integer seq_count; + integer seq_count2; + integer seq_count_a; + integer seq_status_avg; + integer acq_count; + integer seq_status_avg2; + integer conv_pj_count [31:0]; + integer conv_pj_count2 [31:0]; + integer conv_acc [31:0]; + integer conv_acc2 [31:0]; + integer conv_result_int; + integer conv_result_int2; + integer conv_time; + integer conv_count; + integer conv_time_cal; + integer conv_time_cal_1; + integer file_line; + integer char_1; + integer char_2; + integer fs; + integer fd; + integer h, i, j, k, l, m, n, p; + + // string + reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42; + reg [8*600:1] one_line; + reg [8*12:1] label [43:0]; + reg [8*12:1] tmp_label; + reg end_of_file; + + real tmp_va0, tmp_va1, column_real00, column_real100, column_real101; + real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42; + + // array of real numbers + // real column_real [39:0]; + // reg [63:0] column_real [39:0]; + reg [63:0] column_real [42:0]; + reg [63:0] chan_val [31:0]; + reg [63:0] chan_val_tmp [31:0]; + reg [63:0] chan_valn [31:0]; + reg [63:0] chan_valn_tmp [31:0]; + reg [63:0] mn_in_diff [31:0]; + reg [63:0] mn_in2_diff [31:0]; + reg [63:0] mn_in_uni [31:0]; + reg [63:0] mn_in2_uni [31:0]; + reg [63:0] mn_comm_in [31:0]; + reg [63:0] mn_comm2_in [31:0]; + + real chan_val_p_tmp, chan_val_n_tmp; + real mn_mux_in, mn_in_tmp, mn_comm_in_tmp, mn_in_comm; + real mn_mux_in2; + real tmp_v, tmp_v1; + real adc_temp_result, adc_intpwr_result; + real adc_temp_result2, adc_intpwr_result2; + real adc_ext_result; + real adc_ext_result2; + + reg simd_f; + reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly; + reg soft_reset = 0; + reg en_data_flag; + reg first_cal_chan; + reg seq_en; + reg seq_en_dly; + reg seq_en_drp_updt = 1'b0; + wire [15:0] status_reg; + reg [15:0] ot_limit_reg = 16'hCA30; + reg [15:0] tmp_otv; + // reg [15:0] ot_sf_limit_low_reg = 16'hAE40; + reg [23:0] conv_acc_vec; + reg [23:0] conv_acc_vec2; + reg [15:0] conv_result2; + reg [15:0] conv_result; + reg [15:0] conv_result_reg; + reg [15:0] conv_acc_result; + reg [15:0] conv_result_reg2; + reg [15:0] conv_acc_result2; + wire [7:0] curr_clkdiv_sel; + reg [7:0] alarm_out_reg; + reg [4:0] curr_chan; + reg [4:0] curr_chan_lat; + reg [4:0] curr_chan_tmp; + reg [4:0] curr_chan2, curr_chan_lat2; + reg [2:0] adc_state; + reg [2:0] next_state; + reg conv_start, conv_end; + reg eos_en, eos_tmp_en; + reg drdy_out, drdy_out_tmp1, drdy_out_tmp2, drdy_out_tmp3, drdy_out_tmp4; + reg ot_out_reg; + reg [15:0] do_out; + reg [15:0] do_out_rdtmp; + reg [15:0] data_reg [47:0]; + reg [15:0] dr_sram [127:64]; + reg sysclk, adcclk_tmp; + wire adcclk; + wire adcclk_r; + wire xadc_en, xadc2_en; + reg [3:0] curr_seq1_0, curr_seq1_0_lat; + reg [1:0] tmp_seq1_0 = 2'b00; + reg curr_e_c, curr_b_u, curr_acq; + reg ext_mux; + reg curr_e_c2, curr_b_u2, curr_acq2; + reg seq_count_en; + reg [4:0] acq_chan, acq_chan2, acq_chan_m; + reg [4:0] ext_mux_chan, ext_mux_chan2; + reg acq_b_u, acq_b_u2; + reg adc_s1_flag, acq_acqsel; + wire acq_e_c; + reg acq_e_c_tmp5, acq_e_c_tmp6; + reg [1:0] curr_pj_set, curr_pj_set_lat; + reg [1:0] curr_pj_set2, curr_pj_set_lat2; + reg eoc_en, eoc_en_delay; + reg eoc_en2, eoc_en_delay2; + reg eoc_out_tmp, eos_out_tmp; + reg eoc_out_tmp2; + reg eoc_out_tmp1, eos_out_tmp1; + reg eoc_out_tmp21; + reg eoc_out, eos_out; + reg eoc_out2, eoc_out_t; + reg eoc_last = 1'b0; + integer eoc_last_count; + reg busy_r, busy_r_rst; + reg busy_sync1, busy_sync2; + wire busy_sync_fall, busy_sync_rise; + reg [4:0] channel_out; + wire [4:0] muxaddr_o; + reg [4:0] muxaddr_out; + reg rst_lock, rst_lock_early, rst_lock_late; + reg sim_file_flag; + reg [6:0] daddr_in_lat; + reg [15:0] init40h_tmp, init41h_tmp, init42h_tmp, init4eh_tmp; + reg [7:0] alarm_out; + reg ot_out; + reg [15:0] curr_seq, curr_seq_m; + reg [15:0] curr_seq2_tmp, curr_seq2_tmps; + wire [15:0] curr_seq2; + reg busy_out, busy_rst, busy_conv, busy_out_tmp, busy_seq_rst; + reg [3:0] seq1_0, seq_bits; + reg ot_en, alarm_update, drp_update, cal_chan_update; + reg [6:0] alarm_en; + reg [4:0] scon_tmp; + wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_acq_reg1, seq_acq_reg2; + wire [15:0] seq_pj_reg1, seq_pj_reg2, seq_du_reg1, seq_du_reg2; + reg [15:0] cfg_reg1_init; + + reg [4:0] seq_curr_i, seq_curr_i2, seq_curr_ia; + integer busy_rst_cnt; + integer si, seq_num, seq_num2; + integer first_ch = 0; + reg skip_updt = 1'b0; + integer seq_mem [32:0]; + integer seq_mem2 [32:0]; + + wire rst_in, adc_convst; + wire [15:0] cfg_reg0; + wire [15:0] cfg_reg1; + wire [15:0] cfg_reg2; + wire [15:0] di_in; + wire [6:0] daddr_in; + wire [15:0] tmp_data_reg_out, tmp_dr_sram_out; + wire convst_in_tmp; + reg convst_in; + wire rst_in_not_seq; + wire adcclk_div1; + wire gsr_in; + wire convst_raw_in, convstclk_in, dclk_in, den_in, rst_input, dwe_in; + wire DCLK_dly, DEN_dly, DWE_dly; + wire [6:0] DADDR_dly; + wire [15:0] DI_dly; + wire dclk_inv, convstclk_inv; + wire convst_raw_inv, den_inv, dwe_inv, rst_input_inv; + wire [15:0] di_inv; + wire [6:0] daddr_inv; + reg attr_err = 1'b0; + + + // initialize chan_val and chan_valn + integer ii, jj; + + initial begin + for (ii = 0; ii < 32; ii = ii + 1) begin + chan_val[ii] = 64'h0000000000000000; + end + for (jj = 0; jj < 32; jj = jj + 1) begin + chan_valn[jj] = 64'h0000000000000000; + end + end + + + //drp monitor + reg den_r1 = 1'b0; + reg den_r2 = 1'b0; +// reg dwe_r1 = 1'b0; +// reg dwe_r2 = 1'b0; + + reg [1:0] sfsm = 2'b01; + + localparam FSM_IDLE = 2'b01; + localparam FSM_WAIT = 2'b10; + + + always @(posedge dclk_in) begin + // pipeline the DEN and DWE + den_r1 <= den_in; +// dwe_r1 <= dwe_in; + den_r2 <= den_r1; +// dwe_r2 <= dwe_r1; + + // Check - if DEN or DWE is more than 1 DCLK + if ((den_r1 == 1'b1) && (den_r2 == 1'b1)) begin + $display("DRC Error : DEN is high for more than 1 DCLK on %m instance"); + $finish; + end + + // DWE can only be 1 for 2 CLK if DEN is 1 for 2 clk which is not allowed. + // DWE ignored when DEN = 0 +// if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1)) begin +// $display("DRC Error : DWE is high for more than 1 DCLK on %m instance"); +// $finish; +// end + + //After the 1st DEN pulse, check the DEN and DRDY. + case (sfsm) + FSM_IDLE: + begin + if(den_in == 1'b1) + sfsm <= FSM_WAIT; + end + + FSM_WAIT: + begin + // After the 1st DEN, 4 cases can happen + // DEN DRDY NEXT STATE + // 0 0 FSM_WAIT - wait for DRDY + // 0 1 FSM_IDLE - normal operation + // 1 0 FSM_WAIT - display error and wait for DRDY + // 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle. + + //Add the check for another DPREN pulse + if(den_in === 1'b1 && drdy_out === 1'b0) begin + $display("DRC Error : DEN is enabled before DRDY returns on %m instance"); + $finish; + end + + //Add the check for another DWE pulse + // DWE ignored when DEN = 0 +// if ((dwe_in === 1'b1) && (den_in === 1'b0)) begin +// $display("DRC Error : DWE is enabled before DRDY returns on %m instance"); +// $finish; +// end + + if ((drdy_out === 1'b1) && (den_in === 1'b0)) begin + sfsm <= FSM_IDLE; + end + + if ((drdy_out === 1'b1)&& (den_in === 1'b1)) begin + sfsm <= FSM_WAIT; + end + end + + default: + begin + $display("DRC Error : Default state in DRP FSM."); + $finish; + end + endcase + + end // always @ (posedge DCLK) + //end drp monitor + + + //CR 675227 + integer halt_adc = 0; + reg int_rst; + reg int_rst_halt_adc = 0; + + always @(posedge rst_input) + halt_adc <= 0; + + always @(seq1_0) begin + if (halt_adc == 2 && seq1_0 == 4'b0001) begin + halt_adc <= 0; + int_rst_halt_adc <= 1; + @(posedge dclk_in) + int_rst_halt_adc <= 0; + end + end + + tri0 GSR = glbl.GSR; + +`ifndef XIL_TIMING + + assign BUSY = busy_out; + assign DRDY = drdy_out; + assign EOC = eoc_out; + assign EOS = eos_out; + assign OT = ot_out; + assign DO = do_out; + assign CHANNEL = channel_out; + assign MUXADDR = muxaddr_out; + assign ALM = alarm_out; + + assign convst_raw_inv = CONVST; + assign convstclk_inv = CONVSTCLK; + assign dclk_inv = DCLK; + assign den_inv = DEN; + assign rst_input_inv = RESET; + assign dwe_inv = DWE; + assign di_inv = DI; + assign daddr_inv = DADDR; + +`endif // `ifndef XIL_TIMING + +`ifdef XIL_TIMING + + assign BUSY = busy_out; + assign DRDY = drdy_out; + assign EOC = eoc_out; + assign EOS = eos_out; + assign OT = ot_out; + assign DO = do_out; + assign CHANNEL = channel_out; + assign MUXADDR = muxaddr_out; + assign ALM = alarm_out; + + assign convst_raw_inv = CONVST; + assign convstclk_inv = CONVSTCLK; + assign dclk_inv = DCLK_dly; + assign den_inv = DEN_dly; + assign rst_input_inv = RESET; + assign dwe_inv = DWE_dly; + assign di_inv = DI_dly; + assign daddr_inv = DADDR_dly; + +`endif // `ifdef XIL_TIMING + + assign convst_raw_in = convst_raw_inv ^ 1'b0; + assign den_in = den_inv ^ 1'b0; + assign dwe_in = dwe_inv ^ 1'b0; + assign rst_input = rst_input_inv ^ 1'b0; + assign di_in = di_inv ^ 16'h0000; + assign daddr_in = daddr_inv ^ 7'b0000000; + + assign convstclk_in = convstclk_inv ^ IS_CONVSTCLK_INVERTED; + assign dclk_in = dclk_inv ^ IS_DCLK_INVERTED; + assign gsr_in = GSR; + assign convst_in_tmp = (convst_raw_in===1 || convstclk_in===1) ? 1: 0; + assign JTAGLOCKED = 0; + assign JTAGMODIFIED = 0; + assign JTAGBUSY = 0; + + + always @(posedge convst_in_tmp or negedge convst_in_tmp or posedge rst_in) begin + if (rst_in == 1 || rst_lock == 1) + convst_in <= 0; + else if (convst_in_tmp == 1) + convst_in <= 1; + else if (convst_in_tmp == 0) + convst_in <= 0; + end + + + initial begin + + case (SIM_DEVICE) + "7SERIES" : simd_f = 0; + "ZYNQ" : simd_f = 1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on XADC instance %m is set to %s. Legal values for this attribute are 7SERIES, or ZYNQ.", SIM_DEVICE); + #1 $finish; + end + endcase + + init40h_tmp = INIT_40; + init41h_tmp = INIT_41; + init42h_tmp = INIT_42; + init4eh_tmp = INIT_4E; + + if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[8]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000)) + $display(" Attribute Syntax warning : The attribute INIT_40 on XADC instance %m is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_40); + + if ((init41h_tmp[15:12]!=4'b0011) && (init4eh_tmp[10:0]!=11'b0) && (init4eh_tmp[15:12]!=4'b0)) + $display(" Attribute Syntax warning : The attribute INIT_4E on XADC instance %m is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_4E); + + //if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[9]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000)) + // $display(" Attribute Syntax warning : The attribute INIT_40 on XADC instance %m is set to %x. Bit[9] of this attribute must be set to 0. Event mode timing can only be used with external channels, and only in single channel mode.", INIT_40); + + if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[13:12]!=2'b00) && (INIT_48 != 16'h0000) && (INIT_49 != 16'h0000)) + $display(" Attribute Syntax warning : INIT_48 and INIT_49 are %x and %x on XADC instance %m. Those attributes must be set to 0000h in single channel mode and averaging enabled.", INIT_48, INIT_49); + + if (init42h_tmp[1:0] != 2'b00) + $display(" Attribute Syntax Error : The attribute INIT_42 on XADC instance %m is set to %x. Bit[1:0] of this attribute must be set to 0h.", INIT_42); + + //if (init42h_tmp[15:8] < 8'b00000010) begin + // $display(" Attribute Syntax Error : The attribute INIT_42 on XADC instance %m is set to %x. Bit[15:8] of this attribute is the ADC Clock divider and must be equal or greater than 2. ", INIT_42); + // $finish; + //end + + if (INIT_43 != 16'h0) + $display(" Warning : The attribute INIT_43 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_43); + + if (INIT_44 != 16'h0) + $display(" Warning : The attribute INIT_44 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_44); + + if (INIT_45 != 16'h0) + $display(" Warning : The attribute INIT_45 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_45); + + if (INIT_46 != 16'h0) + $display(" Warning : The attribute INIT_46 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_46); + + if (INIT_47 != 16'h0) + $display(" Warning : The attribute INIT_47 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_47); + + + if (!((IS_CONVSTCLK_INVERTED >= 1'b0) && (IS_CONVSTCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_CONVSTCLK_INVERTED on XADC instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CONVSTCLK_INVERTED); + attr_err = 1'b1; + end + + if (!((IS_DCLK_INVERTED >= 1'b0) && (IS_DCLK_INVERTED <= 1'b1))) begin + $display("Attribute Syntax Error : The attribute IS_DCLK_INVERTED on XADC instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_DCLK_INVERTED); + attr_err = 1'b1; + end + + if (attr_err == 1'b1) + #1 $finish; + + end + + initial begin + dr_sram[7'h40] = INIT_40; + dr_sram[7'h41] = INIT_41; + dr_sram[7'h42] = INIT_42; + dr_sram[7'h43] = INIT_43; + dr_sram[7'h44] = INIT_44; + dr_sram[7'h45] = INIT_45; + dr_sram[7'h46] = INIT_46; + dr_sram[7'h47] = INIT_47; + dr_sram[7'h48] = INIT_48; + dr_sram[7'h49] = INIT_49; + dr_sram[7'h4A] = INIT_4A; + dr_sram[7'h4B] = INIT_4B; + dr_sram[7'h4C] = INIT_4C; + dr_sram[7'h4D] = INIT_4D; + dr_sram[7'h4E] = INIT_4E; + dr_sram[7'h4F] = INIT_4F; + dr_sram[7'h50] = INIT_50; + dr_sram[7'h51] = INIT_51; + dr_sram[7'h52] = INIT_52; + tmp_otv = INIT_53; + + if (tmp_otv [3:0] == 4'b0011) begin + dr_sram[7'h53] = INIT_53; + ot_limit_reg = INIT_53; + end + else begin + dr_sram[7'h53] = 16'hCA30; + ot_limit_reg = 16'hCA30; + end + + dr_sram[7'h54] = INIT_54; + dr_sram[7'h55] = INIT_55; + dr_sram[7'h56] = INIT_56; + dr_sram[7'h57] = INIT_57; + dr_sram[7'h58] = INIT_58; + dr_sram[7'h59] = INIT_59; + dr_sram[7'h5A] = INIT_5A; + dr_sram[7'h5B] = INIT_5B; + dr_sram[7'h5C] = INIT_5C; + dr_sram[7'h5D] = INIT_5D; + dr_sram[7'h5E] = INIT_5E; + dr_sram[7'h5F] = INIT_5F; + end // initial begin + + // read input file + initial begin + char_1 = 0; + char_2 = 0; + time_out = 0; + sim_file_flag = 0; + file_line = -1; + end_of_file = 0; + fd = $fopen(SIM_MONITOR_FILE, "r"); + + if (fd == 0) begin + $display(" *** Warning: The analog data file %s for XADC instance %m was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.\n", SIM_MONITOR_FILE); + sim_file_flag = 1; + end + + if (sim_file_flag == 0) begin + while (end_of_file==0) begin + file_line = file_line + 1; + char_1 = $fgetc (fd); + char_2 = $fgetc (fd); + // if(char_2==`EOFile) + if(char_2== -1) + end_of_file = 1; + else begin + // Ignore Comments + if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + // Getting labels + else if ((char_1 == "T" & char_2 == "I" ) || + (char_1 == "T" & char_2 == "i" ) || + (char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s", label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42); + + label[0] = label0; + label[1] = label1; + label[2] = label2; + label[3] = label3; + label[4] = label4; + label[5] = label5; + label[6] = label6; + label[7] = label7; + label[8] = label8; + label[9] = label9; + label[10] = label10; + label[11] = label11; + label[12] = label12; + label[13] = label13; + label[14] = label14; + label[15] = label15; + label[16] = label16; + label[17] = label17; + label[18] = label18; + label[19] = label19; + label[20] = label20; + label[21] = label21; + label[22] = label22; + label[23] = label23; + label[24] = label24; + label[25] = label25; + label[26] = label26; + label[27] = label27; + label[28] = label28; + label[29] = label29; + label[30] = label30; + label[31] = label31; + label[32] = label32; + label[33] = label33; + label[34] = label34; + label[35] = label35; + label[36] = label36; + label[37] = label37; + label[38] = label38; + label[39] = label39; + label[40] = label40; + label[41] = label41; + label[42] = label42; + + for (m = 0; m < num_arg; m = m +1) begin + tmp_label = 96'b0; + tmp_label = to_upcase_label(label[m]); + + case (tmp_label) + "TEMP" : temperature_index = m; + "TIME" : time_index = m; + "VCCAUX" : vccaux_index = m; + "VCCINT" : vccint_index = m; + "VCCBRAM","VBRAM" : vccbram_index = m; + "VCCPINT" : vccpint_index = m; + "VCCPAUX" : vccpaux_index = m; + "VCCDDRO" : vccpdro_index = m; + "VN" : vn_index = m; + "VAUXN[0]" : vauxn_idx0 = m; + "VAUXN[1]" : vauxn_idx1 = m; + "VAUXN[2]" : vauxn_idx2 = m; + "VAUXN[3]" : vauxn_idx3 = m; + "VAUXN[4]" : vauxn_idx4 = m; + "VAUXN[5]" : vauxn_idx5 = m; + "VAUXN[6]" : vauxn_idx6 = m; + "VAUXN[7]" : vauxn_idx7 = m; + "VAUXN[8]" : vauxn_idx8 = m; + "VAUXN[9]" : vauxn_idx9 = m; + "VAUXN[10]" : vauxn_idx10 = m; + "VAUXN[11]" : vauxn_idx11 = m; + "VAUXN[12]" : vauxn_idx12 = m; + "VAUXN[13]" : vauxn_idx13 = m; + "VAUXN[14]" : vauxn_idx14 = m; + "VAUXN[15]" : vauxn_idx15 = m; + "VP" : vp_index = m; + "VAUXP[0]" : vauxp_idx0 = m; + "VAUXP[1]" : vauxp_idx1 = m; + "VAUXP[2]" : vauxp_idx2 = m; + "VAUXP[3]" : vauxp_idx3 = m; + "VAUXP[4]" : vauxp_idx4 = m; + "VAUXP[5]" : vauxp_idx5 = m; + "VAUXP[6]" : vauxp_idx6 = m; + "VAUXP[7]" : vauxp_idx7 = m; + "VAUXP[8]" : vauxp_idx8 = m; + "VAUXP[9]" : vauxp_idx9 = m; + "VAUXP[10]" : vauxp_idx10 = m; + "VAUXP[11]" : vauxp_idx11 = m; + "VAUXP[12]" : vauxp_idx12 = m; + "VAUXP[13]" : vauxp_idx13 = m; + "VAUXP[14]" : vauxp_idx14 = m; + "VAUXP[15]" : vauxp_idx15 = m; + default : begin + $display("analog Data File Error : The channel name %s is invalid in the input file for XADC instance %m.", tmp_label); + infile_format; + end + endcase + end // for (m = 0; m < num_arg; m = m +1) + end + // Getting column values + else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + column_real0 = 0.0; + column_real1 = 0.0; + column_real2 = 0.0; + column_real3 = 0.0; + column_real4 = 0.0; + column_real5 = 0.0; + column_real6 = 0.0; + column_real7 = 0.0; + column_real8 = 0.0; + column_real9 = 0.0; + column_real10 = 0.0; + column_real11 = 0.0; + column_real12 = 0.0; + column_real13 = 0.0; + column_real14 = 0.0; + column_real15 = 0.0; + column_real16 = 0.0; + column_real17 = 0.0; + column_real18 = 0.0; + column_real19 = 0.0; + column_real20 = 0.0; + column_real21 = 0.0; + column_real22 = 0.0; + column_real23 = 0.0; + column_real24 = 0.0; + column_real25 = 0.0; + column_real26 = 0.0; + column_real27 = 0.0; + column_real28 = 0.0; + column_real29 = 0.0; + column_real30 = 0.0; + column_real31 = 0.0; + column_real32 = 0.0; + column_real33 = 0.0; + column_real34 = 0.0; + column_real35 = 0.0; + column_real36 = 0.0; + column_real37 = 0.0; + column_real38 = 0.0; + column_real39 = 0.0; + column_real40 = 0.0; + column_real41 = 0.0; + column_real42 = 0.0; + + num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42); + + column_real[0] = $realtobits(column_real0); + column_real[1] = $realtobits(column_real1); + column_real[2] = $realtobits(column_real2); + column_real[3] = $realtobits(column_real3); + column_real[4] = $realtobits(column_real4); + column_real[5] = $realtobits(column_real5); + column_real[6] = $realtobits(column_real6); + column_real[7] = $realtobits(column_real7); + column_real[8] = $realtobits(column_real8); + column_real[9] = $realtobits(column_real9); + column_real[10] = $realtobits(column_real10); + column_real[11] = $realtobits(column_real11); + column_real[12] = $realtobits(column_real12); + column_real[13] = $realtobits(column_real13); + column_real[14] = $realtobits(column_real14); + column_real[15] = $realtobits(column_real15); + column_real[16] = $realtobits(column_real16); + column_real[17] = $realtobits(column_real17); + column_real[18] = $realtobits(column_real18); + column_real[19] = $realtobits(column_real19); + column_real[20] = $realtobits(column_real20); + column_real[21] = $realtobits(column_real21); + column_real[22] = $realtobits(column_real22); + column_real[23] = $realtobits(column_real23); + column_real[24] = $realtobits(column_real24); + column_real[25] = $realtobits(column_real25); + column_real[26] = $realtobits(column_real26); + column_real[27] = $realtobits(column_real27); + column_real[28] = $realtobits(column_real28); + column_real[29] = $realtobits(column_real29); + column_real[30] = $realtobits(column_real30); + column_real[31] = $realtobits(column_real31); + column_real[32] = $realtobits(column_real32); + column_real[33] = $realtobits(column_real33); + column_real[34] = $realtobits(column_real34); + column_real[35] = $realtobits(column_real35); + column_real[36] = $realtobits(column_real36); + column_real[37] = $realtobits(column_real37); + column_real[38] = $realtobits(column_real38); + column_real[39] = $realtobits(column_real39); + column_real[40] = $realtobits(column_real40); + column_real[41] = $realtobits(column_real41); + column_real[42] = $realtobits(column_real42); + + chan_val[0] = column_real[temperature_index]; + chan_val[1] = column_real[vccint_index]; + chan_val[2] = column_real[vccaux_index]; + chan_val[3] = column_real[vp_index]; + chan_val[6] = column_real[vccbram_index]; + chan_val[13] = column_real[vccpint_index]; + chan_val[14] = column_real[vccpaux_index]; + chan_val[15] = column_real[vccpdro_index]; + chan_val[16] = column_real[vauxp_idx0]; + chan_val[17] = column_real[vauxp_idx1]; + chan_val[18] = column_real[vauxp_idx2]; + chan_val[19] = column_real[vauxp_idx3]; + chan_val[20] = column_real[vauxp_idx4]; + chan_val[21] = column_real[vauxp_idx5]; + chan_val[22] = column_real[vauxp_idx6]; + chan_val[23] = column_real[vauxp_idx7]; + chan_val[24] = column_real[vauxp_idx8]; + chan_val[25] = column_real[vauxp_idx9]; + chan_val[26] = column_real[vauxp_idx10]; + chan_val[27] = column_real[vauxp_idx11]; + chan_val[28] = column_real[vauxp_idx12]; + chan_val[29] = column_real[vauxp_idx13]; + chan_val[30] = column_real[vauxp_idx14]; + chan_val[31] = column_real[vauxp_idx15]; + + chan_valn[3] = column_real[vn_index]; + chan_valn[16] = column_real[vauxn_idx0]; + chan_valn[17] = column_real[vauxn_idx1]; + chan_valn[18] = column_real[vauxn_idx2]; + chan_valn[19] = column_real[vauxn_idx3]; + chan_valn[20] = column_real[vauxn_idx4]; + chan_valn[21] = column_real[vauxn_idx5]; + chan_valn[22] = column_real[vauxn_idx6]; + chan_valn[23] = column_real[vauxn_idx7]; + chan_valn[24] = column_real[vauxn_idx8]; + chan_valn[25] = column_real[vauxn_idx9]; + chan_valn[26] = column_real[vauxn_idx10]; + chan_valn[27] = column_real[vauxn_idx11]; + chan_valn[28] = column_real[vauxn_idx12]; + chan_valn[29] = column_real[vauxn_idx13]; + chan_valn[30] = column_real[vauxn_idx14]; + chan_valn[31] = column_real[vauxn_idx15]; + + // identify columns + if (time_index != -1) begin + prev_time_out = time_out; + time_out = $bitstoreal(column_real[time_index]); + if (prev_time_out > time_out) begin + $display("analog Data File Error : Time value %f is invalid in the input file for XADC instance %m. Time value should increase.", time_out); + infile_format; + end + end + else begin + $display("analog Data File Error : No TIME label is found in the analog data file for XADC instance %m."); + infile_format; + #1 $finish; + end + # ((time_out - prev_time_out) * 1000); + for (p = 0; p < 32; p = p + 1) begin + // assign to real before minus - to work around a bug in modelsim + chan_val_tmp[p] = chan_val[p]; + chan_valn_tmp[p] = chan_valn[p]; + mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]); + mn_in_diff[p] = $realtobits(mn_in_tmp); + mn_in_uni[p] = chan_val[p]; + end + //# ((time_out - prev_time_out) * 1000); + end // if (char_1 == "0" | char_1 == "9") + // Ignore any non-comment, label + else begin + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + end + end + end // while (end_file == 0) + end // if (sim_file_flag == 0) + end // initial begin + + task infile_format; + begin + $display("\n***** XADC Simulation analog Data File Format *****\n"); + $display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n"); + $display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VCCBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] ..... \n"); + $display("TIME must be in first column.\n"); + $display("Time value need to be integer in ns scale.\n"); + $display("analog value need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n"); + $display("Each line including header line can not have extra space after the last character/digit.\n"); + $display("Each data line must have same number of columns as the header line.\n"); + $display("Comment line start with -- or //\n"); + $display("Example:\n"); + $display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n"); + $display("000 125.6 1.0 0.7 0.4 0.3 0.6\n"); + $display("200 25.6 0.8 0.5 0.3 0.8 0.2\n"); + end + endtask //task infile_format + + function [12*8:1] to_upcase_label; + input [12*8:1] in_label; + reg [8:1] tmp_reg; + begin + for (i=0; i< 12; i=i+1) begin + for (j=1; j<=8; j= j+1) + tmp_reg[j] = in_label[i*8+j]; + if ((tmp_reg >96) && (tmp_reg<123)) + tmp_reg = tmp_reg -32; + for (j=1; j<=8; j= j+1) + to_upcase_label[i*8+j] = tmp_reg[j]; + end + end + endfunction + // end read input file + + // Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only + always @( posedge busy_r ) begin + if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin + chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]); + chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]); + + if ( chan_val_n_tmp > chan_val_p_tmp) + $display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0) + $display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan, chan_val_n_tmp, $time/1000.0); + end + if ((seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b10) && acq_b_u == 0 && rst_in == 0 && ((acq_chan2 == 3) || (acq_chan2 >= 16 && acq_chan2 <= 31))) begin + chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan2]); + chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan2]); + + if ( chan_val_n_tmp > chan_val_p_tmp) + $display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan2, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0) + $display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan2, chan_val_n_tmp, $time/1000.0); + end + end + + reg seq_reset_busy_out = 0; + wire rst_in_out; + + always @(posedge dclk_in or posedge rst_in_out) begin + if (rst_in_out) begin + busy_rst <= 1; + rst_lock <= 1; + rst_lock_early <= 1; + rst_lock_late <= 1; + busy_rst_cnt <= 0; + end + else begin + if (rst_lock == 1) begin + if (busy_rst_cnt < 29) begin + busy_rst_cnt <= busy_rst_cnt + 1; + if ( busy_rst_cnt == 26) + rst_lock_early <= 0; + end + else begin + busy_rst <= 0; + rst_lock = 0; + end + end + if (busy_out == 0) + rst_lock_late <= 0; + end + end + + initial begin + busy_out = 0; + busy_rst = 0; + busy_conv = 0; + busy_seq_rst = 0; + busy_out_tmp = 0; + end + + always @(busy_rst or busy_conv or rst_lock) begin + if (rst_lock) + busy_out = busy_rst; + else + busy_out = busy_conv; + end + + always @(posedge dclk_in or posedge rst_in) begin + if (rst_in) begin + busy_conv <= 0; + cal_chan_update <= 0; + end + else begin + if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03) + busy_conv <= busy_seq_rst; + else if (busy_sync_fall) + busy_conv <= 0; + else if (busy_sync_rise) + busy_conv <= 1; + if (conv_count == 21 && curr_chan == 5'b01000) + cal_chan_update <= 1; + else + cal_chan_update <= 0; + end + end + + always @(posedge dclk_in or rst_lock) begin + if (rst_lock) begin + busy_sync1 <= 0; + busy_sync2 <= 0; + end + else begin + busy_sync1 <= busy_r; + busy_sync2 <= busy_sync1; + end + end + + assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0; + assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0; + + always @(negedge busy_out or posedge busy_r) begin + if (seq_reset_flag == 1 && seq1_0 == 4'b0000 && curr_clkdiv_sel <= 8'h03) begin + repeat (5) @(posedge dclk_in); + busy_seq_rst <= 1; + end + else if (seq_reset_flag == 1 && seq1_0 != 4'b0000 && curr_clkdiv_sel <= 8'h03) begin + repeat (7) @(posedge dclk_in); + busy_seq_rst <= 1; + end + else + busy_seq_rst <= 0; + end + + + always @(posedge busy_out or posedge rst_in_out or negedge rst_lock_early) begin + if (rst_in_out) + muxaddr_out <= 5'b0; + else if (rst_lock_early == 0 && rst_lock_late == 1 ) + muxaddr_out <= muxaddr_o; + else begin + repeat (8) @(posedge adcclk); + muxaddr_out <= muxaddr_o; + end + end + + always @(negedge busy_out or posedge busy_out or posedge rst_in_out or posedge cal_chan_update ) begin + if (rst_in_out || rst_lock_late) + channel_out <= 5'd0; + else if (curr_seq1_0_lat[3:2] == 2'b10 && xadc2_en == 0) + channel_out <= 5'd9; //To match HW, 9=Invalid channel is shown. + else if (busy_out ==1 && (cal_chan_update == 1) ) + channel_out <= 5'b01000; + else if (busy_out == 0) begin + if (curr_seq1_0_lat[3:2] != 2'b10 && xadc2_en == 0 || xadc2_en == 1) //NOT independent adc mode + channel_out <= curr_chan; + //else //independent mode and ADC B powered down + // channel_out <= 5'd9; //To match HW, 9=Invalid channel is shown. + // //channel_out <= 5'b0; + curr_chan_lat <= curr_chan; + curr_chan_lat2 <= curr_chan2; + curr_pj_set_lat <= curr_pj_set; + curr_pj_set_lat2 <= curr_pj_set2; + end + end + + + // START double latch rst_in + + reg rst_in1_tmp5; + reg rst_in2_tmp5; + reg rst_in1_tmp6; + reg rst_in2_tmp6; + wire rst_input_t; + wire rst_in2; + + initial begin + int_rst = 1; + repeat (2) @(posedge dclk_in); + int_rst <= 0; + end + + initial begin + rst_in1_tmp5 = 0; + rst_in2_tmp5 = 0; + rst_in1_tmp6 = 0; + rst_in2_tmp6 = 0; + end + + assign #1 rst_input_t = int_rst_halt_adc | rst_input | int_rst | soft_reset; + + always@(posedge adcclk or posedge rst_input_t) begin + if (rst_input_t) begin + rst_in2_tmp6 <= 1; + rst_in1_tmp6 <= 1; + end + else begin + rst_in2_tmp6 <= rst_in1_tmp6; + rst_in1_tmp6 <= rst_input_t; + end + end + + assign rst_in2 = rst_in2_tmp6; + assign #10 rst_in_not_seq = rst_in2; + assign rst_in = rst_in_not_seq | seq_reset_dly; + assign rst_in_out = rst_in_not_seq | seq_reset_busy_out; + + always @(posedge seq_reset) begin + repeat (2) @(posedge dclk_in); + seq_reset_dly <= 1; + repeat (2) @(posedge dclk_in); + seq_reset_busy_out <= 1; + repeat (3) @(posedge dclk_in) begin + seq_reset_dly <= 0; + seq_reset_busy_out <= 0; + end + end + + always @(posedge seq_reset_dly or posedge busy_r) begin + if (seq_reset_dly) + seq_reset_flag <= 1; + else + seq_reset_flag <= 0; + end + + always @(posedge seq_reset_flag or posedge busy_out) begin + if (seq_reset_flag) + seq_reset_flag_dly <= 1; + else + seq_reset_flag_dly <= 0; + end + + always @(posedge busy_out ) begin + if (seq_reset_flag_dly == 1 && acq_chan == 5'b01000 && seq1_0 == 4'b0000) + first_cal_chan <= 1; + else + first_cal_chan <= 0; + end + + + initial begin + conv_time = 18; //minus 3 + // conv_time_cal_1 = 70; + // conv_time_cal = 70; + conv_time_cal_1 = 96; + conv_time_cal = 96; + sysclk = 0; + adcclk_tmp = 0; + seq_count = 1; + seq_count_a = 1; + seq_count2 = 1; + eos_en = 0; + eos_tmp_en = 0; + clk_count = -1; + acq_acqsel = 0; + acq_e_c_tmp6 = 0; + acq_e_c_tmp5 = 0; + eoc_en2 = 0; + eoc_en = 0; + eoc_en_delay = 0; + eoc_en_delay2 = 0; + rst_lock = 0; + rst_lock_early = 0; + alarm_update = 0; + drp_update = 0; + cal_chan_update = 0; + adc_state = S3_ST; + scon_tmp = 5'b0; + busy_r = 0; + busy_r_rst = 0; + busy_sync1 = 0; + busy_sync2 = 0; + conv_count = 0; + conv_end = 0; + seq_status_avg = 0; + seq_status_avg2 = 0; + for (i = 0; i <=20; i = i +1) begin + conv_pj_count2[i] = 0; + conv_acc2[j] = 0; + conv_pj_count[i] = 0; + conv_acc[j] = 0; + end + adc_s1_flag = 0; + for (k = 0; k <= 31; k = k + 1) begin + data_reg[k] = 16'b0; + end + seq_count_en = 0; + eos_out_tmp = 0; + eoc_out_tmp = 0; + eoc_out_tmp2 = 0; + eos_out_tmp1 = 0; + eoc_out_tmp1 = 0; + eoc_out_tmp21 = 0; + eos_out = 0; + eoc_out = 0; + eoc_out_t = 0; + eoc_out2 = 0; + curr_pj_set = 2'b0; + curr_pj_set2 = 2'b0; + curr_pj_set_lat = 2'b0; + curr_pj_set_lat2 = 2'b0; + curr_e_c = 0; + curr_b_u = 0; + curr_acq = 0; + curr_e_c2 = 0; + curr_b_u2 = 0; + curr_acq2 = 0; + curr_seq1_0 = 4'b0; + curr_seq1_0_lat = 4'b0; + seq1_0 = 4'b0; + ext_mux = 0; + ext_mux_chan = 5'b0; + ext_mux_chan2 = 5'b0; + daddr_in_lat = 7'b0; + data_reg[8] = 16'b0; + data_reg[9] = 16'b0; + data_reg[10] = 16'b0; + data_reg[32] = 16'b0; + data_reg[33] = 16'b0; + data_reg[34] = 16'b0; + data_reg[35] = 16'b0; + data_reg[36] = 16'b1111111111111111; + data_reg[37] = 16'b1111111111111111; + data_reg[38] = 16'b1111111111111111; + data_reg[39] = 16'b1111111111111111; + data_reg[40] = 16'b0; + data_reg[41] = 16'b0; + data_reg[42] = 16'b0; + data_reg[43] = 16'b0; + data_reg[44] = 16'b1111111111111111; + data_reg[45] = 16'b1111111111111111; + data_reg[46] = 16'b1111111111111111; + data_reg[47] = 16'b1111111111111111; + // data_reg[48] = 16'b0; + // data_reg[49] = 16'b0; + // data_reg[50] = 16'b0; + ot_out_reg = 0; + ot_out = 0; + alarm_out_reg = 7'b0; + alarm_out = 7'b0; + curr_chan = 5'b0; + curr_chan_lat = 5'b0; + curr_chan2 = 5'b0; + curr_chan_lat2 = 5'b0; + busy_out = 0; + busy_out_tmp = 0; + curr_seq = 16'b0; + curr_seq_m = 16'b0; + curr_seq2_tmp = 16'b0; + curr_seq2_tmps = 16'b0; + seq_num = 0; + seq_num2 = 0; + seq_reset_flag_dly = 0; + seq_reset_flag = 0; + seq_reset_dly = 0; + ot_en = 1; + alarm_en = 7'b1111111; + do_out_rdtmp = 16'b0; + acq_chan = 5'b0; + acq_chan_m = 5'b0; + acq_chan2 = 5'b0; + acq_b_u = 0; + acq_b_u2 = 0; + conv_result_int = 0; + conv_result = 0; + conv_result_reg = 0; + conv_result_int2 = 0; + conv_result2 = 0; + conv_result_reg2 = 0; + end + + + // state machine + always @(posedge adcclk or posedge rst_in or sim_file_flag) begin + //CR 675227 + if (!(halt_adc == 2 && seq1_0 == 4'b0011)) begin + if (sim_file_flag == 1'b1) + adc_state <= S1_ST; + else if (rst_in == 1'b1 || rst_lock_early == 1) + adc_state <= S1_ST; + else if (rst_in == 1'b0) + adc_state <= next_state; + end + end + + always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin + case (adc_state) + S1_ST : next_state = S2_ST; + S2_ST : if (conv_start) + next_state = S3_ST; + else + next_state = S2_ST; + S3_ST : if (conv_end) + next_state = S5_ST; + else + next_state = S3_ST; + S5_ST : if (curr_seq1_0_lat == 4'b0001) begin + //CR 675227 if (eos_en) + if (eos_tmp_en) + next_state = S6_ST; + else + next_state = S2_ST; + end + else + next_state = S2_ST; + S6_ST : next_state = S1_ST; + default : next_state = S1_ST; + endcase // case(adc_state) + end + // end state machine + + + // DRPORT - SRAM + + initial begin + drdy_out = 0; + drdy_out_tmp1 = 0; + drdy_out_tmp2 = 0; + drdy_out_tmp3 = 0; + drdy_out_tmp4 = 0; + en_data_flag = 0; + do_out = 16'b0; + seq_reset = 0; + cfg_reg1_init = INIT_41; + seq_en = 0; + seq_en_dly = 0; + seq_en <= #20 (cfg_reg1_init[15:12] != 4'b0011 ) ? 1 : 0; + seq_en <= #150 0; + end + + always @(posedge drdy_out_tmp3 or posedge gsr_in) begin + if (gsr_in == 1) + drdy_out <= 0; + else begin + @(posedge dclk_in) + drdy_out <= 1; + @(posedge dclk_in) + drdy_out <= 0; + end + end + + always @(posedge dclk_in or posedge gsr_in) begin + if (gsr_in == 1) begin + daddr_in_lat <= 7'b0; + do_out <= 16'b0; + end + else begin + if (den_in == 1'b1) begin + if (drdy_out_tmp1 == 1'b0) begin + drdy_out_tmp1 <= 1'b1; + en_data_flag = 1; + daddr_in_lat <= daddr_in; + end + else begin + if (daddr_in != daddr_in_lat) + $display("Warning : input pin DEN on XADC instance %m at time %.3f ns can not continue set to high. Need wait DRDY high and then set DEN high again.", $time/1000.0); + end + end + else + drdy_out_tmp1 <= 1'b0; + + drdy_out_tmp2 <= drdy_out_tmp1; + drdy_out_tmp3 <= drdy_out_tmp2; + + if (drdy_out_tmp1 == 1) + en_data_flag = 0; + + if (drdy_out_tmp3 == 1) + do_out <= do_out_rdtmp; + + if (den_in == 1 && (daddr_in >7'h5F || (daddr_in >= 7'h33 && daddr_in < 7'h3F))) + $display("Invalid Input Warning : The DADDR %x to XADC instance %m at time %.3f ns is accessing an undefined location. The data in this location is invalid.", daddr_in, $time/1000.0); + + // write all available daddr addresses + if (dwe_in == 1'b1 && en_data_flag == 1) begin + dr_sram[daddr_in] <= di_in; + if (daddr_in == 7'h03) + soft_reset <= 1; + + // if the window is open, allow the sequence to update + if (daddr_in == 7'h48 || daddr_in == 7'h49) + if ((eoc_last == 1'b1) && (seq1_0[3:2] == 2'b01)) + seq_en_drp_updt <= 1'b1; + + if ( daddr_in == 7'h53) begin + if (di_in[3:0] == 4'b0011) + ot_limit_reg[15:4] <= di_in[15:4]; + end + + if ( daddr_in == 7'h42 && (di_in[2:0] !=3'b000)) + $display(" Invalid Input Error : The DI bit[2:0] %x at DADDR %x on XADC instance %m at %.3f ns is invalid. These must be set to 000.", di_in[2:0], daddr_in, $time/1000.0); + + if ( daddr_in >= 7'h43 && daddr_in <= 7'h47 && (di_in[15:0] != 16'h0000)) + $display(" Invalid Input Error : The DI value %x at DADDR %x of XADC instance %m at %.3f ns is invalid. These must be set to 0000h.", di_in, daddr_in, $time/1000.0); + + if ((daddr_in == 7'h40) && + ( di_in[4:0] == 5'b00111 || (di_in[4:0] >= 5'b01001 && di_in[4:0] <= 5'b01100))) + $display("Invalid Input Warning : The DI bit4:0] at address DADDR %x to XADC instance %m at %.3f ns is %h, which is invalid analog channel.", daddr_in, $time/1000.0, di_in[4:0]); + + if (daddr_in == 7'h40) begin + if ((cfg_reg1[15:12]==4'b0011) && (di_in[8]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000)) + $display(" Invalid Input warning : The DI value is %x at DADDR %x on XADC instance %m at %.3f ns. Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels", di_in, daddr_in, $time/1000.0); + + //if ((cfg_reg1[15:12]==4'b0011) && (di_in[9]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000)) + // $display(" Invalid Input warning : The DI value is %x at DADDR %x on XADC instance %m at %.3f ns. Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels", di_in, daddr_in, $time/1000.0); + + if ((cfg_reg1[15:12]==4'b0011) && (di_in[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000)) + $display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on XADC instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0); + end + + if (daddr_in == 7'h41 && en_data_flag == 1) begin + if ((di_in[15:12]==4'b0011) && (cfg_reg0[8]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000)) + $display(" Invalid Input warning : The Control Regiter 40h value is %x on XADC instance %m at %.3f ns. Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels", cfg_reg0, $time/1000.0); + + //if ((di_in[15:12]==4'b0011) && (cfg_reg0[9]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000)) + // $display(" Invalid Input warning : The Control Regiter 40h value is %x on XADC instance %m at %.3f ns. Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels", cfg_reg0, $time/1000.0); + + if ((di_in[15:12]!=4'b0011) && (seq_acq_reg1[10:0]!=11'b0) && (seq_acq_reg1[15:12]!=4'b0)) + $display(" Invalid Input warning : The Control Regiter 4Eh value is %x on XADC instance %m at %.3f ns. Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels", seq_acq_reg1, $time/1000.0); + + if ((di_in[15:12]==4'b0011) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000)) + $display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on XADC instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0); + + end + + if (daddr_in == 7'h41 && en_data_flag == 1) begin + if (den_in == 1'b1 && dwe_in == 1'b1) begin + if (di_in[15:12] != cfg_reg1[15:12]) begin // writing with the same seq[3:0] will not restart the sequence, matching with hw + seq_reset <= 1'b1; + seq_en_drp_updt <= 1'b0; + end + else + seq_reset <= 1'b0; + if (di_in[15:12] != 4'b0011 ) begin + seq_en <= 1'b1; + seq_en_drp_updt <= 1'b0; + end + else + seq_en <= 1'b0; + end + else begin + seq_reset <= 1'b0; + seq_en <= 1'b0; + end + end + //else begin + // seq_reset <= 0; + // seq_en <= 0; + //end // if (daddr_in == 7'h41) + end // dwe ==1 + + if (seq_en == 1) + seq_en <= 1'b0; + if (seq_reset == 1) + seq_reset <= 1'b0; + if (soft_reset == 1) + soft_reset <= 0; + if (seq_en_drp_updt == 1'b1 && eos_out == 1'b1) + seq_en <= 1'b1; + if (seq_en_drp_updt == 1'b1 && seq_en == 1'b1) + seq_en_drp_updt <= 1'b0; + + end // if (gsr == 1) + end//always + + + // DO bus data out + assign tmp_dr_sram_out = ( daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h5F) ? + dr_sram[daddr_in_lat] : 16'b0; + + assign status_reg = {8'b0, alarm_out[6:3], ot_out, alarm_out[2:0]}; + + assign tmp_data_reg_out = (daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h2E) ? + data_reg[daddr_in_lat] : 16'b0; + + always @( daddr_in_lat or tmp_data_reg_out or tmp_dr_sram_out or status_reg ) begin + if ((daddr_in_lat >7'h5F || (daddr_in_lat >= 7'h2F && daddr_in_lat < 7'h3F))) begin + do_out_rdtmp = 16'bx; + end + + if (daddr_in_lat == 7'h3F) begin + do_out_rdtmp = status_reg; + end + + if ((daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h2E)) + do_out_rdtmp = tmp_data_reg_out; + else if (daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h5F) + do_out_rdtmp = tmp_dr_sram_out; + end + // end DRP RAM + + + assign cfg_reg0 = dr_sram[7'h40]; + assign cfg_reg1 = dr_sram[7'h41]; + assign cfg_reg2 = dr_sram[7'h42]; + assign seq_chan_reg1 = dr_sram[7'h48]; + assign seq_chan_reg2 = dr_sram[7'h49]; + assign seq_pj_reg1 = dr_sram[7'h4A]; + assign seq_pj_reg2 = dr_sram[7'h4B]; + assign seq_du_reg1 = dr_sram[7'h4C]; + assign seq_du_reg2 = dr_sram[7'h4D]; + assign seq_acq_reg1 = dr_sram[7'h4E]; + assign seq_acq_reg2 = dr_sram[7'h4F]; + + always @(cfg_reg1) + seq1_0 = cfg_reg1[15:12]; + always @(cfg_reg0) begin + ext_mux = cfg_reg0[11]; + ext_mux_chan = cfg_reg0[4:0]; + ext_mux_chan2 = {2'b11, cfg_reg0[2:0]}; + end + + always @(posedge drp_update or posedge rst_in) begin + if (rst_in) begin + repeat (2) @(posedge dclk_in); + seq_bits = seq1_0; + end + else + seq_bits = curr_seq1_0; + + if (seq_bits == 4'b0000) begin + alarm_en <= 8'b0; + ot_en <= 1; + end + else begin + ot_en <= ~cfg_reg1[0]; + alarm_en[2:0] <= ~cfg_reg1[3:1]; + alarm_en[6:3] <= ~cfg_reg1[11:8]; + end + end + // end DRPORT - sram + + // Clock divider, generate and adcclk + always @(posedge dclk_in) + sysclk <= ~sysclk; + + always @(posedge dclk_in) begin + if (curr_clkdiv_sel > 8'b00000010 ) begin + if (clk_count >= curr_clkdiv_sel - 1) + clk_count = 0; + else + clk_count = clk_count + 1; + + if (clk_count > (curr_clkdiv_sel/2) - 1) + adcclk_tmp <= 1; + else + adcclk_tmp <= 0; + end + else + adcclk_tmp <= ~adcclk_tmp; + end + + assign curr_clkdiv_sel = cfg_reg2[15:8]; + //power down condition cfg_reg2[5:4] + // 00: all up + // 01: invalid + // 10: ADC B down + // 11: XADC down + assign xadc_en = (cfg_reg2[5]===1 && cfg_reg2[4]===1) ? 0 : 1; + assign xadc2_en = (cfg_reg2[5]===1 ) ? 0 : 1; + assign adcclk_div1 = (curr_clkdiv_sel > 8'b00000010) ? 0 : 1; + assign adcclk_r = (adcclk_div1) ? ~sysclk : adcclk_tmp; + assign adcclk = (xadc_en) ? adcclk_r : 0; + // end clock divider + + // latch configuration registers + wire [15:0] cfg_reg0_seq, cfg_reg0_adc; + reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5; + reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6; + reg [1:0] acq_avg, acq_avg2; + + // not independent adc mode + assign muxaddr_o = (rst_lock_early) ? 5'b0 : (curr_seq1_0_lat[3:2] != 2'b10 && xadc2_en == 0 || xadc2_en == 1) ? acq_chan_m : 5'b0; + + always @( seq1_0 or adc_s1_flag or curr_seq_m or cfg_reg0_adc or rst_in) begin + if (rst_in == 0) begin + if (seq1_0[3:2] == 2'b01) begin + acq_chan_m = curr_seq_m[4:0]; + end + else if (seq1_0[3:2] == 2'b10) begin //independent ADC mode. + acq_chan_m = curr_seq_m[4:0]; + end + else if (seq1_0[3:2] == 2'b11) begin + acq_chan_m = curr_seq_m[4:0]; + end + else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin + acq_chan_m = curr_seq_m[4:0]; + end + else begin + acq_chan_m = cfg_reg0_adc[4:0]; + end + end + end + + //CR 675227 always @( seq1_0 or adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin + always @(adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin + if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010 + || seq1_0[3:2] == 2'b10 || seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b11) begin + acq_acqsel = curr_seq[8]; + end + else if (seq1_0 == 4'b0011) begin // Single channel mode, sequencer off + acq_acqsel = cfg_reg0_adc[8]; // The acquisition time on ext analog + // inputs, extending by 6 cycles. Reset + // value + end + else begin + acq_acqsel = 0; + end + + if (rst_in == 0) begin + if (seq1_0[3:2] == 2'b01) begin //simultaneous sampling mode + acq_avg = curr_seq[13:12]; + acq_chan = curr_seq[4:0]; + acq_b_u = curr_seq[10]; + acq_avg2 = curr_seq2[13:12]; + acq_chan2 = curr_seq[4:0] + 8; + acq_b_u2 = curr_seq2[10]; + end + else if (seq1_0[3:2] == 2'b10) begin //In independent adc mode , + //ADC A is doing default mode sequence and + //ADC B is doing the user selected sequence. + //ADC B is shown at CHANNEL output, therefore + //ADC 2 is assigned with ADC A settings and + //ADC 1 with ADC B. + acq_avg = curr_seq[13:12]; //ADC B + acq_chan = curr_seq[4:0]; + acq_b_u = curr_seq[10]; + acq_avg2 = 2'b01; // Average 16 samples for default sequence + acq_chan2 = curr_seq2[4:0]; + acq_b_u2 = 0; // ADCA is unipolar. + end + else if (seq1_0[3:2] == 2'b11) begin + acq_avg = 2'b01; + acq_chan = curr_seq[4:0]; + acq_b_u = 0; + end + else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin + acq_avg = curr_seq[13:12]; + acq_chan = curr_seq[4:0]; + acq_b_u = curr_seq[10]; + end + else begin + acq_avg = cfg_reg0_adc[13:12]; + acq_chan = cfg_reg0_adc[4:0]; + acq_b_u = cfg_reg0_adc[10]; + + //CR 675227 + if (seq1_0 == 4'b0001 && acq_e_c == 1'b0) begin + //CR 764936 if (seq1_0 == 4'b0001) begin + halt_adc = halt_adc + 1; + if (halt_adc == 2) + dr_sram[7'h41][15:12] = 4'b0011; + end + end //else + end//rst_in + end//always + + reg single_chan_conv_end; + reg [3:0] conv_end_reg_read; + reg busy_reg_read; + reg first_after_reset_tmp5; + reg first_after_reset_tmp6; + + always@(posedge adcclk or posedge rst_in) begin + if(rst_in) conv_end_reg_read <= 4'b0; + else conv_end_reg_read <= {conv_end_reg_read[2:0], single_chan_conv_end | conv_end}; + end + + always@(posedge DCLK or posedge rst_in) begin + if(rst_in) + busy_reg_read <= 1; + else + busy_reg_read <= ~conv_end_reg_read[2]; + end + + assign cfg_reg0_adc = cfg_reg0_adc_tmp6; + assign cfg_reg0_seq = cfg_reg0_seq_tmp6; + assign acq_e_c = acq_e_c_tmp6; + + always @(negedge busy_out or rst_in) begin + if(rst_in) begin + cfg_reg0_seq_tmp6 <= 16'b0; + cfg_reg0_adc_tmp6 <= 16'b0; + acq_e_c_tmp6 <= 0; + first_after_reset_tmp6 <= 1; + end + else begin + repeat(3) @(posedge DCLK); + if(first_after_reset_tmp6) begin + first_after_reset_tmp6<=0; + cfg_reg0_adc_tmp6 <= cfg_reg0; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + else begin + cfg_reg0_adc_tmp6 <= cfg_reg0_seq; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + acq_e_c_tmp6 <= cfg_reg0[9]; + end + end + + always @(posedge conv_start or posedge busy_r_rst or posedge rst_in) begin + if (rst_in ==1) + busy_r <= 0; + else if (conv_start && rst_lock == 0) + busy_r <= 1; + else if (busy_r_rst) + busy_r <= 0; + end + + always @(negedge busy_out ) begin + if (adc_s1_flag == 1) + //single pass sequence or single channel mode with sequencer of. + //go back to default mode after one sequence is completed + if (curr_seq1_0 == 4'b0001 || curr_seq1_0 == 4'b0011) // CR 764936 + curr_seq1_0 <= 4'b0011; + else + curr_seq1_0 <= 4'b0000; + else + curr_seq1_0 <= seq1_0; + end + + // always @(posedge conv_start or posedge rst_in ) + always @(posedge conv_start or rst_in ) begin + if (rst_in == 1) begin + mn_mux_in <= 0.0; + mn_mux_in2 <= 0.0; + curr_chan <= 5'b0; + curr_chan2 <= 5'b0; + end + else begin + if ((acq_chan == 5'b00011) || (acq_chan >= 5'b10000 && acq_chan <= 5'b11111)) begin + if (ext_mux == 1) begin + tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan]); + mn_mux_in <= tmp_v; + end + else begin + tmp_v = $bitstoreal(mn_in_diff[acq_chan]); + mn_mux_in <= tmp_v; + end + end + else + mn_mux_in <= $bitstoreal(mn_in_uni[acq_chan]); + + tmp_seq1_0 = curr_seq1_0[3:2]; + + if (tmp_seq1_0 == 2'b01 || tmp_seq1_0 == 2'b10) begin + if ((acq_chan2 == 5'b00011) || (acq_chan2 >= 5'b10000 && acq_chan2 <= 5'b11111)) begin + if (ext_mux == 1) begin + tmp_v1 = $bitstoreal(mn_in_diff[ext_mux_chan2]); + mn_mux_in2 <= tmp_v1; + end + else begin + tmp_v1 = $bitstoreal(mn_in_diff[acq_chan2]); + mn_mux_in2 <= tmp_v1; + end + end + else + mn_mux_in2 <= $bitstoreal(mn_in_uni[acq_chan2]); + end + curr_chan <= acq_chan; + curr_chan2 <= acq_chan2; + curr_seq1_0_lat <= curr_seq1_0; + + if ( acq_chan == 5'b00111 || (acq_chan >= 5'b01010 && acq_chan <= 5'b01100)) + $display("Invalid Input Warning : The analog channel %x to XADC instance %m at %.3f ns is invalid.", acq_chan, $time/1000.0); + + if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010 || seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b10 || seq1_0[3:2] == 2'b11) begin + curr_pj_set <= curr_seq[13:12]; + curr_b_u <= curr_seq[10]; + curr_e_c <= curr_seq[9]; + curr_acq <= curr_seq[8]; + curr_pj_set2 <= curr_seq2[13:12]; + curr_b_u2<= curr_seq2[10]; + curr_e_c2 <= curr_seq2[9]; + curr_acq2 <= curr_seq2[8]; + end + else begin + curr_pj_set <= acq_avg; + curr_b_u <= acq_b_u; + curr_e_c <= cfg_reg0[9]; + curr_acq <= cfg_reg0[8]; + end + end // if (rst_in == 0) + end //always + // end latch configuration registers + + + // sequence control + always @(seq_en ) + seq_en_dly <= #1 seq_en; + + always @(posedge seq_en_dly) begin + if (seq1_0 == 4'b0001 || seq1_0 == 4'b0010) begin //single pass sequence or cont sequence mode + seq_num = 0; + for (si=0; si<= 15; si=si+1) begin + if (seq_chan_reg1[si] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + for (si=16; si<= 31; si=si+1) begin + if (seq_chan_reg2[si-16] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + if (seq_num < 32) begin + for (si=seq_num+1; si<=32; si=si+1) begin + seq_mem[si] = 0; + end + end + end + // if sequence register is updated at the appropriate time, + // all but the first channel in the simultaneous sampling mode sequence + // can be changed without a reset, trying to handel some error cases too. + else if (seq1_0[3:2] == 2'b01) begin //simultaneous sampling mode + seq_num = 0; + skip_updt = 1'b0; + if (seq_en_drp_updt == 1'b1) begin + first_ch = seq_mem[1]; + if (first_ch <= 16) begin + if (first_ch == 16 && seq_chan_reg2[0] == 1'b0) begin + seq_num = 1; // first channel turned off, leave on + end + else if (first_ch < 16 && seq_chan_reg1[first_ch] == 1'b0) begin + seq_num = 1; // first channel turned off, leave on + end + for (si=0; si<= first_ch-1; si=si+1) begin + if (seq_chan_reg1[si] == 1) begin // look for a ch enabled before first_ch + skip_updt = 1'b1; // new first channel before old one, ignore + end + end + end + else begin //first_ch >16 + if (seq_chan_reg2[first_ch-16] == 1'b0) begin + seq_num = 1; // first channel turned off, leave on + end + for (si=0; si<= 15; si=si+1) begin + if (seq_chan_reg1[si] == 1) begin // look for a ch enabled before first_ch + skip_updt = 1'b1; // new first channel before old one, ignore + end + end + for (si=16; si<= first_ch-1; si=si+1) begin + if (seq_chan_reg2[si-16] == 1) begin // look for a ch enabled before first_ch + skip_updt = 1'b1; // new first channel before old one, ignore + end + end + end + end //seq_en_drp_updt == 1'b1 + if (skip_updt == 1'b0) begin + for (si=0; si<= 15; si=si+1) begin + if (seq_chan_reg1[si] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + for (si=16; si<= 23; si=si+1) begin + if (seq_chan_reg2[si-16] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + if (seq_num < 32) begin + for (si=seq_num+1; si<=32; si=si+1) begin + seq_mem[si] = 0; + end + end + end //skip_updt==0 + end //simultaneous sampling mode + else if (seq1_0[3:2] == 2'b10) begin //independent ADC mode + //reset sequences + for (si=0; si<= 31; si=si+1) begin + seq_mem [si] = 0; + seq_mem2[si] = 0; + end + //ADCB assignment, which goes to ADC 1 in the model. + seq_num = 0; + //Check register x48. + if (seq_chan_reg1[11] == 1) begin //if VP-VN dedicated analog inputs are selected + seq_num = 1; + seq_mem[1] = 11; + end + //Check register x49 + for (si=16; si<= 32; si=si+1) begin + if (seq_chan_reg2[si-16] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + //set the rest to 0 + if (seq_num < 32) begin + for (si=seq_num+1; si<=32; si=si+1) begin + seq_mem[si] = 0; + end + end + if(seq_num==0) + $display("XADC ERROR: This is not a valid selection. In independent ADC mode, ADC B has to have at least one channel in the sequence. Check registers 48h and 49h."); + //default sequence is followed in ADC A, which goes to ADC 2 in the model. + if (simd_f == 0) begin // Not a ZYNQ device + seq_num2 = 5; + seq_mem2[1] = 0; + seq_mem2[2] = 8; + seq_mem2[3] = 9; + seq_mem2[4] = 10; + seq_mem2[5] = 14; + end + else if (simd_f == 1) begin // ZYNQ device + seq_num2 = 8; + seq_mem2[1] = 0; + seq_mem2[2] = 5; + seq_mem2[3] = 6; + seq_mem2[4] = 7; + seq_mem2[5] = 8; + seq_mem2[6] = 9; + seq_mem2[7] = 10; + seq_mem2[8] = 14; + end + end + else if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) begin //default mode + if (simd_f == 0) begin // Not a ZYNQ device + seq_num = 5; + seq_mem[1] = 0; + seq_mem[2] = 8; + seq_mem[3] = 9; + seq_mem[4] = 10; + seq_mem[5] = 14; + end + else if (simd_f == 1) begin //ZYNQ device + seq_num = 8; + seq_mem[1] = 0; + seq_mem[2] = 5; + seq_mem[3] = 6; + seq_mem[4] = 7; + seq_mem[5] = 8; + seq_mem[6] = 9; + seq_mem[7] = 10; + seq_mem[8] = 14; + end + end + end //always + + always @( seq_count or negedge seq_en_dly) begin + seq_curr_i = seq_mem[seq_count]; + curr_seq = 16'b0; + if (seq_curr_i >= 0 && seq_curr_i <= 15) begin + curr_seq [2:0] = seq_curr_i[2:0]; + curr_seq [4:3] = 2'b01; //Channel select 8-15 + curr_seq [8] = seq_acq_reg1[seq_curr_i]; + curr_seq [10] = seq_du_reg1[seq_curr_i]; + + if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) //default mode + curr_seq [13:12] = 2'b01; + else if (seq_pj_reg1[seq_curr_i] == 1) // check if averaging is enabled for h4A + curr_seq [13:12] = cfg_reg0[13:12]; // set averaging count selection (16, 64, or 256) + else + curr_seq [13:12] = 2'b00; //No averaging + + if (seq_curr_i >= 0 && seq_curr_i <=7) + curr_seq [4:3] = 2'b01; //Channel select 8-15 + else + curr_seq [4:3] = 2'b00; ///Channel select 0-7 + end + else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin + curr_seq [4:0] = seq_curr_i; + curr_seq [8] = seq_acq_reg2[seq_curr_i - 16]; + curr_seq [10] = seq_du_reg2[seq_curr_i - 16]; + if (seq_pj_reg2[seq_curr_i - 16] == 1) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + if (seq_curr_i < 24) begin // simultaneous sampling mode, 1st set of aux channels + curr_seq2_tmps[4:0] = seq_curr_i + 8; + curr_seq2_tmps[8] = seq_acq_reg2[seq_curr_i - 8]; + curr_seq2_tmps[10] = seq_du_reg2[seq_curr_i - 8]; + if (seq_pj_reg2[seq_curr_i - 8] == 1) + curr_seq2_tmps[13:12] = cfg_reg0[13:12]; + else + curr_seq2_tmps [13:12] = 2'b00; + end + end + end + + // choose curr_seq2_tmps for simultaneous sampling mode. + assign curr_seq2 = (tmp_seq1_0 == 2'b01) ? curr_seq2_tmps : curr_seq2_tmp; + + always @( seq_count_a or negedge seq_en_dly) begin + seq_curr_ia = seq_mem[seq_count_a]; + curr_seq_m = 16'b0; + if (seq_curr_ia >= 0 && seq_curr_ia <= 15) begin + curr_seq_m [2:0] = seq_curr_ia[2:0]; + curr_seq_m [4:3] = 2'b01; + curr_seq_m [8] = seq_acq_reg1[seq_curr_ia]; + curr_seq_m [10] = seq_du_reg1[seq_curr_ia]; + + if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) //default mode + curr_seq_m [13:12] = 2'b01; + else if (seq_pj_reg1[seq_curr_ia] == 1) + //if(seq1_0[3:2] == 2'b10) //independent ADC. + // curr_seq_m [13:12] = 2'b01; //16 samples + //else + curr_seq_m [13:12] = cfg_reg0[13:12]; //averaging count as set + else //no averaging + curr_seq_m [13:12] = 2'b00; + + if (seq_curr_ia >= 0 && seq_curr_ia <=7) + curr_seq_m [4:3] = 2'b01; + else + curr_seq_m [4:3] = 2'b00; + end + else if (seq_curr_ia >= 16 && seq_curr_ia <= 31) begin + curr_seq_m [4:0] = seq_curr_ia; + curr_seq_m [8] = seq_acq_reg2[seq_curr_ia - 16]; + curr_seq_m [10] = seq_du_reg2[seq_curr_ia - 16]; + if (seq_pj_reg2[seq_curr_ia - 16] == 1) + curr_seq_m [13:12] = cfg_reg0[13:12]; + else + curr_seq_m [13:12] = 2'b00; + end + end + + + always @( seq_count2 or negedge seq_en_dly) begin + seq_curr_i2 = seq_mem2[seq_count2]; + curr_seq2_tmp = 16'b0; + if (seq_curr_i2 >= 0 && seq_curr_i2 <= 15) begin + curr_seq2_tmp [2:0] = seq_curr_i2[2:0]; + curr_seq2_tmp [4:3] = 2'b01; + curr_seq2_tmp [8] = seq_acq_reg1[seq_curr_i2]; + curr_seq2_tmp [9] = 0; + curr_seq2_tmp [10] = seq_du_reg1[seq_curr_i2]; + + if ( seq1_0[3:2] == 2'b10) //independent ADC. + curr_seq2_tmp [13:12] = 2'b01; // Default sequence: always average 16 samples. + else + curr_seq2_tmp [13:12] = 2'b00; // No averaging for simultaneous sampling mode + + if (seq_curr_i2 >= 0 && seq_curr_i2 <=7) + curr_seq2_tmp [4:3] = 2'b01; //select (channel +8) + else + curr_seq2_tmp [4:3] = 2'b00; //select (channel mod8) + end + else if (seq_curr_i2 >= 16 && seq_curr_i2 <= 31) begin + curr_seq2_tmp [4:0] = seq_curr_i2; + curr_seq2_tmp [8] = seq_acq_reg2[seq_curr_i2 - 16]; + curr_seq2_tmp [10] = seq_du_reg2[seq_curr_i2 - 16]; + if (seq_pj_reg2[seq_curr_i2 - 16] == 1) + curr_seq2_tmp [13:12] = cfg_reg0[13:12]; + else + curr_seq2_tmp [13:12] = 2'b00; + end + end + + always @(posedge busy_out or posedge rst_in ) begin + if (rst_in == 1 || rst_lock == 1 ) begin + seq_count_a <= 1; + end + else begin + if ( curr_seq1_0_lat == 4'b0011 ) + seq_count_a <= 1; + else begin + if (seq_count_a >= 32 || seq_count_a >= seq_num) + seq_count_a <= 1; + else + seq_count_a <= seq_count_a +1; + end + end + end + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1 ) begin + seq_count <= 1; + seq_count2 <= 1; + eos_en <= 0; + end + else begin + if (curr_seq1_0_lat[3:2] == 2'b10) begin // independent adc mode + if ((seq_count2 >= seq_num2 ) && (adc_state == S5_ST) ) + seq_count2 <= 1; + else if (seq_count_en == 1) + seq_count2 <= seq_count2 + 1; + end + + if ((seq_count == seq_num ) && (adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && rst_lock == 0) + eos_tmp_en <= 1; + else + eos_tmp_en <= 0; + + if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk + eos_en <= 1; + else + eos_en <= 0; + + if (eos_tmp_en == 1 || curr_seq1_0_lat == 4'b0011 ) + seq_count <= 1; + else if (seq_count_en == 1) begin + if (seq_count >= 32) + seq_count <= 1; + else + seq_count <= seq_count +1; + end + end // else: !if(rst_in == 1) + end + // end sequence control + + + // Acquisition + reg first_acq; + reg shorten_acq; + wire busy_out_dly; + + assign #10 busy_out_dly = busy_out; + + always @(adc_state or posedge rst_in or first_acq) begin + if(rst_in) + shorten_acq = 0; + else if(busy_out_dly==0 && adc_state==S2_ST && first_acq==1) + shorten_acq = 1; + else + shorten_acq = 0; + end + + always @(posedge adcclk or posedge rst_in) begin + // if (rst_in == 1) begin + if (rst_in == 1 || rst_lock == 1) begin + acq_count <= 1; + first_acq <=1; + end + else begin + if (adc_state == S2_ST && rst_lock == 0 && (acq_e_c==0)) begin + first_acq <= 0; + if (acq_acqsel == 1) begin + if (acq_count <= 11) + acq_count <= acq_count + 1 + shorten_acq; + end + else begin + if (acq_count <= 4) + acq_count <= acq_count + 1 + shorten_acq; + end // else: !if(acq_acqsel == 1) + + if (next_state == S3_ST) + if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4)) + $display ("Warning: Acquisition time is not long enough for XADC instance %m at time %t.", $time); + end // if (adc_state == S2_ST) + else + acq_count <= (first_acq) ? 1 : 0; + end // if (rst_in == 0 && rdt_lock==0) + end + + // continuous mode + reg conv_start_cont; + wire reset_conv_start; + wire conv_start_sel; + + always @(adc_state or acq_acqsel or acq_count) begin + if (adc_state == S2_ST) begin + if (rst_lock == 0) begin + // CR 800173 if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03)) + // && ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) ) + if( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) + conv_start_cont = 1; + else + conv_start_cont = 0; + end + end // if (adc_state == S2_ST) + else + conv_start_cont = 0; + end + + assign conv_start_sel = (acq_e_c) ? convst_in : conv_start_cont; + assign reset_conv_start = rst_in | (conv_count==2); + + always@(posedge conv_start_sel or posedge reset_conv_start) begin + if(reset_conv_start) + conv_start <= 0; + else + conv_start <= 1; + end + // end acquisition + + // Conversion + always @(adc_state or next_state or curr_chan or mn_mux_in or curr_b_u) begin + if ((adc_state == S3_ST && next_state == S5_ST) || adc_state == S5_ST) begin + if (curr_chan == 0) begin // temperature conversion + //adc_temp_result = (mn_mux_in + 273.15) * 0.001984226*65536; + adc_temp_result = (mn_mux_in + 273.15) * 0.001984225*65536; //CR 861679 + if (adc_temp_result >= 65535.0) + conv_result_int = 65535; + else if (adc_temp_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_temp_result); + if (adc_temp_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 1 || curr_chan == 2 || curr_chan ==6 || + curr_chan == 13 || curr_chan == 14 || curr_chan == 15) begin // internal power conversion + adc_intpwr_result = mn_mux_in * 65536.0 / 3.0; + if (adc_intpwr_result >= 65535.0) + conv_result_int = 65535; + else if (adc_intpwr_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_intpwr_result); + if (adc_intpwr_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin + adc_ext_result = (mn_mux_in) * 65536.0; + if (curr_b_u == 1) begin + if (adc_ext_result > 32767.0) + conv_result_int = 32767; + else if (adc_ext_result < -32768.0) + conv_result_int = -32768; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else begin + if (adc_ext_result > 65535.0) + conv_result_int = 65535; + else if (adc_ext_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + end + else begin + conv_result_int = 0; + end + end + conv_result = conv_result_int; + end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u) + + always @(adc_state or next_state or curr_chan2 or mn_mux_in2 or curr_b_u2) begin + if ((adc_state == S3_ST && next_state == S5_ST) || adc_state == S5_ST) begin + if (curr_chan2 == 0) begin // temperature conversion + adc_temp_result2 = (mn_mux_in2 + 273.15) * 0.001984225*65536; //CR 861679, CR 9633888 + if (adc_temp_result2 >= 65535.0) + conv_result_int2 = 65535; + else if (adc_temp_result2 < 0.0) + conv_result_int2 = 0; + else begin + conv_result_int2 = $rtoi(adc_temp_result2); + if (adc_temp_result2 - conv_result_int2 > 0.9999) + conv_result_int2 = conv_result_int2 + 1; + end + end + else if (curr_chan2 == 1 || curr_chan2 == 2 || curr_chan2 == 6 + || curr_chan2 == 13 || curr_chan2 == 14 || curr_chan2 == 15) begin // internal power conversion + adc_intpwr_result2 = mn_mux_in2 * 65536.0 / 3.0; + if (adc_intpwr_result2 >= 65535.0) + conv_result_int2 = 65535; + else if (adc_intpwr_result2 < 0.0) + conv_result_int2 = 0; + else begin + conv_result_int2 = $rtoi(adc_intpwr_result2); + if (adc_intpwr_result2 - conv_result_int2 > 0.9999) + conv_result_int2 = conv_result_int2 + 1; + end + end + else if (curr_chan2 == 3 || (curr_chan2 >=16 && curr_chan2 <= 31)) begin + adc_ext_result2 = (mn_mux_in2) * 65536.0; + if (curr_b_u2 == 1) begin + if (adc_ext_result2 > 32767.0) + conv_result_int2 = 32767; + else if (adc_ext_result2 < -32768.0) + conv_result_int2 = -32768; + else begin + conv_result_int2 = $rtoi(adc_ext_result2); + if (adc_ext_result2 - conv_result_int2 > 0.9999) + conv_result_int2 = conv_result_int2 + 1; + end + end + else begin + if (adc_ext_result2 > 65535.0) + conv_result_int2 = 65535; + else if (adc_ext_result2 < 0.0) + conv_result_int2 = 0; + else begin + conv_result_int2 = $rtoi(adc_ext_result2); + if (adc_ext_result2 - conv_result_int2 > 0.9999) + conv_result_int2 = conv_result_int2 + 1; + end + end + end + else begin + conv_result_int2 = 0; + end + end + conv_result2 = conv_result_int2; + end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u) + + reg busy_r_rst_done; + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) begin + conv_count <= 6; + conv_end <= 0; + seq_status_avg <= 0; + busy_r_rst <= 0; + busy_r_rst_done <= 0; + for (i = 0; i <=31; i = i +1) begin + conv_pj_count[i] <= 0; // array of integer + conv_pj_count2[i] <= 0; // array of integer + end + single_chan_conv_end <= 0; + end + else begin + if(adc_state == S2_ST) begin + if(busy_r_rst_done == 0) + busy_r_rst <= 1; + else + busy_r_rst <= 0; + busy_r_rst_done <= 1; + end + + if (adc_state == S2_ST && conv_start == 1) begin + conv_count <= 0; + conv_end <= 0; + end + else if (adc_state == S3_ST ) begin + busy_r_rst_done <= 0; + conv_count = conv_count + 1; + if ((curr_chan != 5'b01000 ) && (conv_count == conv_time ) || + (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal_1 ) && (first_cal_chan==1) + || (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal) && (first_cal_chan == 0)) + conv_end <= 1; + else + conv_end <= 0; + end + else begin + conv_end <= 0; + conv_count <= 0; + end + // jmcgrath - to model the behaviour correctly when a cal chanel is being converted + // an signal to signify the conversion has ended must be produced - this is for single channel mode + single_chan_conv_end <= 0; + if( (conv_count == conv_time) || (conv_count == 44)) + single_chan_conv_end <= 1; + if (adc_state == S3_ST && next_state == S5_ST && rst_lock == 0) begin + case (curr_pj_set) + 2'b00 : begin + eoc_en <= 1; + conv_pj_count[curr_chan] <= 0; + end + 2'b01 : if (conv_pj_count[curr_chan] == 15) begin + eoc_en <= 1; + conv_pj_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_pj_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1; + end + 2'b10 : if (conv_pj_count[curr_chan] == 63) begin + eoc_en <= 1; + conv_pj_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_pj_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1; + end + 2'b11 : if (conv_pj_count[curr_chan] == 255) begin + eoc_en <= 1; + conv_pj_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_pj_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1; + end + default :eoc_en <= 0; + endcase // case(curr_pj_set) + + case (curr_pj_set2) + 2'b00 : begin + eoc_en2 <= 1; + conv_pj_count2[curr_chan2] <= 0; + end + 2'b01 : if (conv_pj_count2[curr_chan2] == 15) begin + eoc_en2 <= 1; + conv_pj_count2[curr_chan2] <= 0; + seq_status_avg2 <= seq_status_avg2 - 1; + end + else begin + eoc_en2 <= 0; + if (conv_pj_count2[curr_chan2] == 0) + seq_status_avg2 <= seq_status_avg2 + 1; + conv_pj_count2[curr_chan2] <= conv_pj_count2[curr_chan2] + 1; + end + 2'b10 : if (conv_pj_count2[curr_chan2] == 63) begin + eoc_en2 <= 1; + conv_pj_count2[curr_chan2] <= 0; + seq_status_avg2 <= seq_status_avg2 - 1; + end + else begin + eoc_en2 <= 0; + if (conv_pj_count2[curr_chan2] == 0) + seq_status_avg2 <= seq_status_avg2 + 1; + conv_pj_count[curr_chan2] <= conv_pj_count[curr_chan2] + 1; + end + 2'b11 : if (conv_pj_count2[curr_chan2] == 255) begin + eoc_en2 <= 1; + conv_pj_count2[curr_chan2] <= 0; + seq_status_avg2 <= seq_status_avg2 - 1; + end + else begin + eoc_en2 <= 0; + if (conv_pj_count2[curr_chan2] == 0) + seq_status_avg2 <= seq_status_avg2 + 1; + conv_pj_count2[curr_chan2] <= conv_pj_count2[curr_chan2] + 1; + end + default:eoc_en2 <= 0; + endcase // case(curr_pj_set) + end // if (adc_state == S3_ST && next_state == S5_ST) + else begin + eoc_en <= 0; + eoc_en2 <= 0; + end + if (adc_state == S5_ST) begin + conv_result_reg <= conv_result; + conv_result_reg2 <= conv_result2; + end + end // if (rst_in == 0) + end + // end conversion + + + // average + always @(adc_state or conv_acc[curr_chan]) + if (adc_state == S5_ST ) + // no signed or unsigned differences for bit vector conv_acc_vec + conv_acc_vec = conv_acc[curr_chan]; + else + conv_acc_vec = 24'b00000000000000000000; + + always @(adc_state or conv_acc2[curr_chan2]) + if (adc_state == S5_ST ) + // no signed or unsigned differences for bit vector conv_acc_vec + conv_acc_vec2 = conv_acc2[curr_chan2]; + else + conv_acc_vec2 = 24'b00000000000000000000; + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) begin + for (j = 0; j <= 31; j = j + 1) begin + conv_acc[j] <= 0; + conv_acc2[j] <= 0; + end + conv_acc_result <= 16'b0000000000000000; + conv_acc_result2 <= 16'b0000000000000000; + end + else begin + if (adc_state == S3_ST && next_state == S5_ST) begin + if (curr_pj_set != 2'b00 && rst_lock != 1) + conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int; + else + conv_acc[curr_chan] <= 0; + if (curr_pj_set2 != 2'b00 && rst_lock != 1) + conv_acc2[curr_chan2] <= conv_acc2[curr_chan2] + conv_result_int2; + else + conv_acc2[curr_chan2] <= 0; + end + else begin + if (eoc_en == 1) begin + case (curr_pj_set) + 2'b00 : conv_acc_result <= 16'b0000000000000000; + 2'b01 : conv_acc_result <= conv_acc_vec[19:4]; + 2'b10 : conv_acc_result <= conv_acc_vec[21:6]; + 2'b11 : conv_acc_result <= conv_acc_vec[23:8]; + endcase + conv_acc[curr_chan] <= 0; + end + + if (eoc_en2 == 1 ) begin + case (curr_pj_set2) + 2'b00 : conv_acc_result2 <= 16'b0000000000000000; + 2'b01 : conv_acc_result2 <= conv_acc_vec2[19:4]; + 2'b10 : conv_acc_result2 <= conv_acc_vec2[21:6]; + 2'b11 : conv_acc_result2 <= conv_acc_vec2[23:8]; + endcase + conv_acc2[curr_chan2] <= 0; + end + end //states + end // if (rst_in == 0) + end + // end average + + // single sequence + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) + adc_s1_flag <= 0; + else + if (adc_state == S6_ST) + adc_s1_flag <= 1; + end + // end state + + always @(posedge adcclk or posedge rst_in) begin + if (rst_in == 1) begin + seq_count_en <= 0; + eos_out_tmp <= 0; + eoc_out_tmp <= 0; + eoc_out_tmp2 <= 0; + end + else begin + if ((adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && (rst_lock == 0)) + seq_count_en <= 1; + else + seq_count_en <= 0; + + if (rst_lock == 0) begin + eos_out_tmp <= eos_en; + eoc_en_delay <= eoc_en; + eoc_out_tmp <= eoc_en_delay; + if (curr_seq1_0_lat[3:2] != 2'b00) begin //simultaneous sampling mode, independent adc mode,or default mode + eoc_en_delay2 <= eoc_en2; + eoc_out_tmp2 <= eoc_en_delay2; + end + end + else begin + eos_out_tmp <= 0; + eoc_en_delay <= 0; + eoc_out_tmp <= 0; + eoc_en_delay2 <= 0; + eoc_out_tmp2 <= 0; + end + end + end + // assign eoc_out_t = eoc_out | eoc_out2; + always @(eoc_out or eoc_out2) + eoc_out_t <= #1 (eoc_out | eoc_out2); + + always @(posedge eoc_out_t or posedge rst_in_not_seq) begin + if (rst_in_not_seq == 1) begin + for (k = 32; k <= 39; k = k + 1) + if (k >= 36) + data_reg[k] <= 16'b1111111111111111; + else + data_reg[k] <= 16'b0000000000000000; + for (k = 40; k <= 42; k = k + 1) + data_reg[k] <= 16'b0000000000000000; + for (k = 44; k <= 46; k = k + 1) + data_reg[k] <= 16'b1111111111111111; + end + else begin + if ( rst_lock == 0) begin + if (eoc_out == 1) begin + + if ((curr_chan_lat >= 0 && curr_chan_lat <= 3) || (curr_chan_lat == 6) || + (curr_chan_lat >= 13 && curr_chan_lat <= 31)) begin + if (curr_pj_set_lat == 2'b00) + data_reg[curr_chan_lat] <= conv_result_reg; + else + data_reg[curr_chan_lat] <= conv_acc_result; + end + + if (curr_chan_lat == 4) // VREFP + data_reg[curr_chan_lat] <= 16'h6AAB; // 1.25V CR-961722 + if (curr_chan_lat == 5) // VREFN + data_reg[curr_chan_lat] <= 16'h0000; // 0V + + if (curr_chan_lat == 0 || curr_chan_lat == 1 || curr_chan_lat == 2) begin + if (curr_pj_set_lat == 2'b00) begin + if (conv_result_reg > data_reg[32 + curr_chan_lat]) + data_reg[32 + curr_chan_lat] <= conv_result_reg; + if (conv_result_reg < data_reg[36 + curr_chan_lat]) + data_reg[36 + curr_chan_lat] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[32 + curr_chan_lat]) + data_reg[32 + curr_chan_lat] <= conv_acc_result; + if (conv_acc_result < data_reg[36 + curr_chan_lat]) + data_reg[36 + curr_chan_lat] <= conv_acc_result; + end + end + if (curr_chan_lat == 6) begin + if (curr_pj_set_lat == 2'b00) begin + if (conv_result_reg > data_reg[35]) + data_reg[35] <= conv_result_reg; + if (conv_result_reg < data_reg[39]) + data_reg[39] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[35]) + data_reg[35] <= conv_acc_result; + if (conv_acc_result < data_reg[39]) + data_reg[39] <= conv_acc_result; + end + end + if (curr_chan_lat == 5'b01101) begin + if (curr_pj_set_lat == 2'b00) begin + if (conv_result_reg > data_reg[40]) + data_reg[40] <= conv_result_reg; + if (conv_result_reg < data_reg[44]) + data_reg[44] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[40]) + data_reg[40] <= conv_acc_result; + if (conv_acc_result < data_reg[44]) + data_reg[44] <= conv_acc_result; + end + end + if (curr_chan_lat == 5'b01110) begin + if (curr_pj_set_lat == 2'b00) begin + if (conv_result_reg > data_reg[41]) + data_reg[41] <= conv_result_reg; + if (conv_result_reg < data_reg[45]) + data_reg[45] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[41]) + data_reg[41] <= conv_acc_result; + if (conv_acc_result < data_reg[45]) + data_reg[45] <= conv_acc_result; + end + end + if (curr_chan_lat == 5'b01111) begin + if (curr_pj_set_lat == 2'b00) begin + if (conv_result_reg > data_reg[42]) + data_reg[42] <= conv_result_reg; + if (conv_result_reg < data_reg[46]) + data_reg[46] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[42]) + data_reg[42] <= conv_acc_result; + if (conv_acc_result < data_reg[46]) + data_reg[46] <= conv_acc_result; + end + end + end //eoc_out=1 + + if (eoc_out2 == 1) begin + if ((curr_chan_lat2 >= 0 && curr_chan_lat2 <= 3) || (curr_chan_lat2 == 6) || + (curr_chan_lat2 >= 13 && curr_chan_lat2 <= 31)) begin + if (curr_pj_set_lat2 == 2'b00) + data_reg[curr_chan_lat2] <= conv_result_reg2; + else + data_reg[curr_chan_lat2] <= conv_acc_result2; + end + if (curr_chan_lat2 == 4) + data_reg[curr_chan_lat2] <= 16'hD555; + if (curr_chan_lat2 == 5) + data_reg[curr_chan_lat2] <= 16'h0000; + + if (curr_chan_lat2 == 0 || curr_chan_lat2 == 1 || curr_chan_lat2 == 2) begin + if (curr_pj_set_lat2 == 2'b00) begin + if (conv_result_reg2 > data_reg[32 + curr_chan_lat2]) + data_reg[32 + curr_chan_lat2] <= conv_result_reg2; + if (conv_result_reg2 < data_reg[36 + curr_chan_lat2]) + data_reg[36 + curr_chan_lat2] <= conv_result_reg2; + end + else begin + if (conv_acc_result2 > data_reg[32 + curr_chan_lat2]) + data_reg[32 + curr_chan_lat2] <= conv_acc_result2; + if (conv_acc_result2 < data_reg[36 + curr_chan_lat2]) + data_reg[36 + curr_chan_lat2] <= conv_acc_result2; + end + end + if (curr_chan_lat2 == 6) begin + if (curr_pj_set_lat2 == 2'b00) begin + if (conv_result_reg2 > data_reg[35]) + data_reg[35] <= conv_result_reg2; + if (conv_result_reg2 < data_reg[39]) + data_reg[39] <= conv_result_reg2; + end + else begin + if (conv_acc_result2 > data_reg[35]) + data_reg[35] <= conv_acc_result2; + if (conv_acc_result2 < data_reg[39]) + data_reg[39] <= conv_acc_result2; + end + end + if (curr_chan_lat2 == 5'b01101) begin + if (curr_pj_set_lat2 == 2'b00) begin + if (conv_result_reg2 > data_reg[40]) + data_reg[40] <= conv_result_reg2; + if (conv_result_reg2 < data_reg[44]) + data_reg[44] <= conv_result_reg2; + end + else begin + if (conv_acc_result2 > data_reg[40]) + data_reg[40] <= conv_acc_result2; + if (conv_acc_result2 < data_reg[44]) + data_reg[44] <= conv_acc_result2; + end + end + if (curr_chan_lat2 == 5'b01110) begin + if (curr_pj_set_lat2 == 2'b00) begin + if (conv_result_reg2 > data_reg[41]) + data_reg[41] <= conv_result_reg2; + if (conv_result_reg2 < data_reg[45]) + data_reg[45] <= conv_result_reg2; + end + else begin + if (conv_acc_result2 > data_reg[41]) + data_reg[41] <= conv_acc_result2; + if (conv_acc_result2 < data_reg[45]) + data_reg[45] <= conv_acc_result2; + end + end + if (curr_chan_lat2 == 5'b01111) begin + if (curr_pj_set_lat2 == 2'b00) begin + if (conv_result_reg2 > data_reg[42]) + data_reg[42] <= conv_result_reg2; + if (conv_result_reg2 < data_reg[46]) + data_reg[46] <= conv_result_reg2; + end + else begin + if (conv_acc_result2 > data_reg[42]) + data_reg[42] <= conv_acc_result2; + if (conv_acc_result2 < data_reg[46]) + data_reg[46] <= conv_acc_result2; + end + end + end + end + end + end //always + + reg [15:0] data_written; + always @(negedge busy_r or posedge rst_in_not_seq) begin + if (rst_in_not_seq) + data_written <= 16'b0; + else begin + if (curr_seq1_0[3:2] != 2'b10) begin + if (curr_pj_set == 2'b00) + data_written <= conv_result_reg; + else + data_written <= conv_acc_result; + end + else begin + if (curr_pj_set2 == 2'b00) + data_written <= conv_result_reg2; + else + data_written <= conv_acc_result2; + end + end + end + + reg [4:0] op_count=15; + reg busy_out_sync; + wire busy_out_low_edge; + + // eos and eoc + + always @( posedge eoc_out_tmp or posedge eoc_out or posedge rst_in) begin + if (rst_in ==1) + eoc_out_tmp1 <= 0; + else if ( eoc_out ==1) + eoc_out_tmp1 <= 0; + else if ( eoc_out_tmp == 1) begin + if (curr_chan != 5'b01000 && ( xadc2_en == 1 || (curr_seq1_0[3:2] != 2'b10 && xadc2_en == 0))) + eoc_out_tmp1 <= 1; + else + eoc_out_tmp1 <= 0; + end + end + + always @( posedge eoc_out_tmp2 or posedge eoc_out2 or posedge rst_in) begin + if (rst_in ==1) + eoc_out_tmp21 <= 0; + else if ( eoc_out2 ==1) + eoc_out_tmp21 <= 0; + else if ( eoc_out_tmp2 == 1) begin + if (curr_chan2 != 5'b01000 && ( xadc2_en == 1 || (curr_seq1_0[3:2] == 2'b10 && xadc2_en == 0))) + eoc_out_tmp21 <= 1; + else + eoc_out_tmp21 <= 0; + end + end + + always @( posedge eos_out_tmp or posedge eos_out or posedge rst_in) begin + if (rst_in ==1) + eos_out_tmp1 <= 0; + else if ( eos_out ==1) + eos_out_tmp1 <= 0; + else if ( eos_out_tmp == 1 && ( xadc2_en == 1 || (curr_seq1_0[3:2] != 2'b10 && xadc2_en == 0))) + eos_out_tmp1 <= 1; + end + + assign busy_out_low_edge = (busy_out==0 && busy_out_sync==1) ? 1 : 0; + + // create a 4 clock window after the second to last EOC in which the sequence register can be updated without a reset. + always @( posedge dclk_in or posedge rst_in) begin + if (rst_in) begin + eoc_last <= 1'b0; + eoc_last_count <= 0; + end + else begin + if ((op_count == 16) && (eoc_out_tmp1 == 1'b1)) begin // EOC conditions + if (seq_count == seq_num) begin // second to last EOC, last seq starting + eoc_last <= 1'b1; + end + else begin + eoc_last <= 1'b0; + end + end + else if (eoc_last_count >= 3) begin // window size in clocks - 1 + eoc_last <= 1'b0; + end + if (eoc_last == 1'b1) begin // count clocks when window open + eoc_last_count <= eoc_last_count + 1; + end + else begin + eoc_last_count <= 0; + end + end + end + + always @( posedge dclk_in or posedge rst_in) begin + if (rst_in) begin + op_count <= 15; + busy_out_sync <= 0; + end + drp_update <= 0; + alarm_update <= 0; + eoc_out <= 0; + eoc_out2 <= 0; + eos_out <= 0; + + if(rst_in==0) begin + busy_out_sync <= busy_out; + if(op_count==3) + drp_update <= 1; + if(op_count==5 && ((eoc_out_tmp1==1 && curr_seq1_0[3:2] != 2'b10) || eoc_out_tmp21 == 1)) + alarm_update <=1; + // if(op_count==9 ) begin + if(op_count== 16 ) begin + eoc_out <= eoc_out_tmp1; + eoc_out2 <= eoc_out_tmp21; + end + //if(op_count==9) + // eos_out <= eos_out_tmp1; + if(op_count==16) + eos_out <= eos_out_tmp1; + if (busy_out_low_edge==1 ) + op_count <= 0; + else if(op_count < 22) + op_count <= op_count +1; + end + end + // end eos and eoc + + // alarm + + always @( posedge alarm_update or posedge rst_in_not_seq ) begin + if (rst_in_not_seq == 1) begin + ot_out_reg <= 0; + alarm_out_reg <= 8'b0; + end + else + if (rst_lock == 0) begin + if (curr_seq1_0[3:2] == 2'b10) // independent ADC + curr_chan_tmp = curr_chan_lat2; + else + curr_chan_tmp = curr_chan_lat; + if (curr_chan_tmp == 0) begin + if (data_written >= ot_limit_reg) + ot_out_reg <= 1; + else if (data_written < dr_sram[7'h57]) + ot_out_reg <= 0; + + if (data_written > dr_sram[7'h50]) + alarm_out_reg[0] <= 1; + else if (data_written < dr_sram[7'h54]) + alarm_out_reg[0] <= 0; + end + if (curr_chan_tmp == 1) begin + if (data_written > dr_sram[7'h51] || data_written < dr_sram[7'h55]) + alarm_out_reg[1] <= 1; + else + alarm_out_reg[1] <= 0; + end + if (curr_chan_tmp == 2) begin + if (data_written > dr_sram[7'h52] || data_written < dr_sram[7'h56]) + alarm_out_reg[2] <= 1; + else + alarm_out_reg[2] <= 0; + end + if (curr_chan_tmp == 6) begin + if (data_written > dr_sram[7'h58] || data_written < dr_sram[7'h5C]) + alarm_out_reg[3] <= 1; + else + alarm_out_reg[3] <= 0; + end + if (curr_chan_tmp == 13) begin + if (data_written > dr_sram[7'h59] || data_written < dr_sram[7'h5D]) + alarm_out_reg[4] <= 1; + else + alarm_out_reg[4] <= 0; + end + if (curr_chan_tmp == 14) begin + if (data_written > dr_sram[7'h5A] || data_written < dr_sram[7'h5E]) + alarm_out_reg[5] <= 1; + else + alarm_out_reg[5] <= 0; + end + if (curr_chan_tmp == 15) begin + if (data_written > dr_sram[7'h5B] || data_written < dr_sram[7'h5F]) + alarm_out_reg[6] <= 1; + else + alarm_out_reg[6] <= 0; + end + end // if (rst_lock == 0) + end //always + + always @(ot_out_reg or ot_en or alarm_out_reg or alarm_en) begin + ot_out = ot_out_reg & ot_en; + alarm_out[6:0] = alarm_out_reg[6:0] & alarm_en[6:0]; + alarm_out[7] = |alarm_out[6:0]; + end + + // end alarm + + //*** Timing_Checks_Start_here + +`ifdef XIL_TIMING + + reg notifier, notifier_do; + + always @(notifier) begin + alarm_out_reg = 7'bx; + ot_out = 1'bx; + busy_out = 1'bx; + eoc_out = 1'bx; + eos_out = 1'bx; + curr_chan = 5'bx; + drdy_out = 1'bx; + do_out = 16'bx; + end + + always @(notifier_do) begin + drdy_out = 1'bx; + do_out = 16'bx; + end + + wire dclk_en_n; + wire dclk_en_p; + assign dclk_en_n = IS_DCLK_INVERTED; + assign dclk_en_p = ~IS_DCLK_INVERTED; + + wire rst_en_n; + wire rst_en_p; + assign rst_en_n = ~rst_input && dclk_en_n; + assign rst_en_p = ~rst_input && dclk_en_p; + +`endif // `ifdef XIL_TIMING + + specify + (DCLK => ALM) = (100:100:100, 100:100:100); + (DCLK => BUSY) = (100:100:100, 100:100:100); + (DCLK => CHANNEL) = (100:100:100, 100:100:100); + (DCLK => DO) = (100:100:100, 100:100:100); + (DCLK => DRDY) = (100:100:100, 100:100:100); + (DCLK => EOC) = (100:100:100, 100:100:100); + (DCLK => EOS) = (100:100:100, 100:100:100); + (DCLK => JTAGBUSY) = (100:100:100, 100:100:100); + (DCLK => JTAGLOCKED) = (100:100:100, 100:100:100); + (DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100); + (DCLK => MUXADDR) = (100:100:100, 100:100:100); + (DCLK => OT) = (100:100:100, 100:100:100); + +`ifdef XIL_TIMING + + $period (posedge CONVST, 0:0:0, notifier); + $period (posedge CONVSTCLK, 0:0:0, notifier); + $period (negedge CONVSTCLK, 0:0:0, notifier); + $period (posedge DCLK, 0:0:0, notifier); + $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DADDR_dly); + $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DEN_dly); + $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DI_dly); + $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DWE_dly); + $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DADDR_dly); + $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DEN_dly); + $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DI_dly); + $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_dly,DWE_dly); + $setuphold (negedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DADDR_dly); + $setuphold (negedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DEN_dly); + $setuphold (negedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DI_dly); + $setuphold (negedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DWE_dly); + $setuphold (negedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DADDR_dly); + $setuphold (negedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DEN_dly); + $setuphold (negedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DI_dly); + $setuphold (negedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_dly,DWE_dly); + +`endif // `ifdef XIL_TIMING + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/src/unisims/XORCY.v b/verilog/src/unisims/XORCY.v new file mode 100644 index 0000000..831ddc9 --- /dev/null +++ b/verilog/src/unisims/XORCY.v @@ -0,0 +1,66 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / XOR for Carry Logic with General Output +// /___/ /\ Filename : XORCY.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +`celldefine + +module XORCY (O, CI, LI); + + +`ifdef XIL_TIMING + + parameter LOC = "UNPLACED"; + +`endif + + + output O; + + input CI, LI; + + xor X1 (O, CI, LI); + +`ifdef XIL_TIMING + + specify + + (CI => O) = (0:0:0, 0:0:0); + (LI => O) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + + endspecify + +`endif + +endmodule + +`endcelldefine + diff --git a/verilog/src/unisims/ZHOLD_DELAY.v b/verilog/src/unisims/ZHOLD_DELAY.v new file mode 100644 index 0000000..822bc7a --- /dev/null +++ b/verilog/src/unisims/ZHOLD_DELAY.v @@ -0,0 +1,200 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 13.1 +// \ \ Description : Xilinx TEST ONLY Library Component +// / / Delay Element. +// /___/ /\ Filename : ZHOLD_DELAY.v +// \ \ / \ +// \___\/\___\ +// +// Revision: +// 04/14/10 - Initial version. +// 05/12/11 - 609212 -- fix for ncsim +// 07/11/11 - 616630 -- Change/Combine attributes +// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). +// 05/10/12 - 659430 - remove GSR ref, ANSI ports, mti simprim error (add #1) +// 10/22/14 - Added #1 to $finish (CR 808642). +// End Revision + +`timescale 1 ps / 1 ps + +`celldefine + +module ZHOLD_DELAY #( +`ifdef XIL_TIMING + parameter LOC = "UNPLACED", +`endif // ifdef XIL_TIMING + parameter [0:0] IS_DLYIN_INVERTED = 1'b0, + parameter ZHOLD_FABRIC = "DEFAULT", // {"DEFAULT", "0", .... "31"} + parameter ZHOLD_IFF = "DEFAULT" // {"DEFAULT", "0", .... "31"} +) ( + output DLYFABRIC, + output DLYIFF, + input DLYIN +); + + localparam MODULE_NAME = "ZHOLD_DELAY"; + +//------------------- constants ------------------------------------ + localparam MAX_IFF_DELAY_COUNT = 31; + localparam MIN_IFF_DELAY_COUNT = 0; + + localparam MAX_IDELAY_COUNT = 31; + localparam MIN_IDELAY_COUNT = 0; + +`ifndef XIL_TIMING + real TAP_DELAY = 200.0; +`endif // ifndef XIL_TIMING + + integer idelay_count=0; + integer iff_idelay_count=0; + + // inputs + wire dlyin_in; + +`ifndef XIL_TIMING + // outputs + reg tap_out_fabric = 0; + reg tap_out_iff = 0; +`endif // ifndef XIL_TIMING + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- +`ifdef XIL_TIMING + assign #1 DLYFABRIC = dlyin_in; + assign #1 DLYIFF = dlyin_in; +`else // ifdef XIL_TIMING + assign DLYFABRIC = tap_out_fabric; + assign DLYIFF = tap_out_iff; +`endif // ifdef XIL_TIMING + +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign dlyin_in = IS_DLYIN_INVERTED ^ DLYIN; + + +//------------------------------------------------------------ +//--------------------- Initialization -------------------- +//------------------------------------------------------------ + initial begin + + //-------- ZHOLD_FABRIC check + case (ZHOLD_FABRIC) + "DEFAULT" : idelay_count = 0; + "0" : idelay_count = 0; + "1" : idelay_count = 1; + "2" : idelay_count = 2; + "3" : idelay_count = 3; + "4" : idelay_count = 4; + "5" : idelay_count = 5; + "6" : idelay_count = 6; + "7" : idelay_count = 7; + "8" : idelay_count = 8; + "9" : idelay_count = 9; + "10" : idelay_count = 10; + "11" : idelay_count = 11; + "12" : idelay_count = 12; + "13" : idelay_count = 13; + "14" : idelay_count = 14; + "15" : idelay_count = 15; + "16" : idelay_count = 16; + "17" : idelay_count = 17; + "18" : idelay_count = 18; + "19" : idelay_count = 19; + "20" : idelay_count = 20; + "21" : idelay_count = 21; + "22" : idelay_count = 22; + "23" : idelay_count = 23; + "24" : idelay_count = 24; + "25" : idelay_count = 25; + "26" : idelay_count = 26; + "27" : idelay_count = 27; + "28" : idelay_count = 28; + "29" : idelay_count = 29; + "30" : idelay_count = 30; + "31" : idelay_count = 31; + default : begin + $display("Attribute Syntax Error : The attribute ZHOLD_FABRIC on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\" ..... \"31\"",MODULE_NAME,ZHOLD_FABRIC); + #1 $finish; + end + endcase + + //-------- ZHOLD_IFF check + case (ZHOLD_IFF) + "DEFAULT" : iff_idelay_count = 0; + "0" : iff_idelay_count = 0; + "1" : iff_idelay_count = 1; + "2" : iff_idelay_count = 2; + "3" : iff_idelay_count = 3; + "4" : iff_idelay_count = 4; + "5" : iff_idelay_count = 5; + "6" : iff_idelay_count = 6; + "7" : iff_idelay_count = 7; + "8" : iff_idelay_count = 8; + "9" : iff_idelay_count = 9; + "10" : iff_idelay_count = 10; + "11" : iff_idelay_count = 11; + "12" : iff_idelay_count = 12; + "13" : iff_idelay_count = 13; + "14" : iff_idelay_count = 14; + "15" : iff_idelay_count = 15; + "16" : iff_idelay_count = 16; + "17" : iff_idelay_count = 17; + "18" : iff_idelay_count = 18; + "19" : iff_idelay_count = 19; + "20" : iff_idelay_count = 20; + "21" : iff_idelay_count = 21; + "22" : iff_idelay_count = 22; + "23" : iff_idelay_count = 23; + "24" : iff_idelay_count = 24; + "25" : iff_idelay_count = 25; + "26" : iff_idelay_count = 26; + "27" : iff_idelay_count = 27; + "28" : iff_idelay_count = 28; + "29" : iff_idelay_count = 29; + "30" : iff_idelay_count = 30; + "31" : iff_idelay_count = 31; + default : begin + $display("Attribute Syntax Error : The attribute ZHOLD_IFF on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\"...\"31\"",MODULE_NAME,ZHOLD_IFF); + #1 $finish; + end + endcase + + end // initial begin + +`ifndef XIL_TIMING + always@(dlyin_in) begin + tap_out_fabric <= #(TAP_DELAY*idelay_count) dlyin_in; + tap_out_iff <= #(TAP_DELAY*iff_idelay_count) dlyin_in; + end // end always +`endif // ifndef XIL_TIMING + +`ifdef XIL_TIMING + specify + ( DLYIN => DLYFABRIC) = (0:0:0, 0:0:0); + ( DLYIN => DLYIFF) = (0:0:0, 0:0:0); + specparam PATHPULSE$ = 0; + endspecify +`endif // ifdef XIL_TIMING + +endmodule // ZHOLD_DELAY + +`endcelldefine diff --git a/verilog/src/unisims/unisims_sv.dat b/verilog/src/unisims/unisims_sv.dat new file mode 100644 index 0000000..e390449 --- /dev/null +++ b/verilog/src/unisims/unisims_sv.dat @@ -0,0 +1,5 @@ +HSADC.v +HSDAC.v +RFDAC.v +RFADC.v +GTM_DUAL.sv